diff --git a/firrtl_black_box_resource_files.f b/firrtl_black_box_resource_files.f index 2e65d9e4..89983276 100644 --- a/firrtl_black_box_resource_files.f +++ b/firrtl_black_box_resource_files.f @@ -1 +1,3 @@ -/home/laraibkhan/Desktop/SweRV-Chislified/gated_latch.sv \ No newline at end of file +/home/laraibkhan/Desktop/SweRV-Chislified/gated_latch.sv +/home/laraibkhan/Desktop/SweRV-Chislified/dmi_wrapper.sv +/home/laraibkhan/Desktop/SweRV-Chislified/mem.sv \ No newline at end of file diff --git a/quasar_wrapper.fir b/quasar_wrapper.fir index c652dec9..9506f3e4 100644 --- a/quasar_wrapper.fir +++ b/quasar_wrapper.fir @@ -66828,81 +66828,81 @@ circuit quasar_wrapper : module dec_decode_ctl : input clock : Clock input reset : AsyncReset - output io : {flip decode_exu : {flip dec_data_en : UInt<2>, flip dec_ctl_en : UInt<2>, flip i0_ap : {land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, flip dec_i0_predict_p_d : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, flip i0_predict_fghr_d : UInt<8>, flip i0_predict_index_d : UInt<8>, flip i0_predict_btag_d : UInt<5>, flip dec_i0_rs1_en_d : UInt<1>, flip dec_i0_rs2_en_d : UInt<1>, flip dec_i0_immed_d : UInt<32>, flip dec_i0_rs1_bypass_data_d : UInt<32>, flip dec_i0_rs2_bypass_data_d : UInt<32>, flip dec_i0_select_pc_d : UInt<1>, flip dec_i0_rs1_bypass_en_d : UInt<2>, flip dec_i0_rs2_bypass_en_d : UInt<2>, flip mul_p : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}}, flip pred_correct_npc_x : UInt<31>, flip dec_extint_stall : UInt<1>, exu_i0_result_x : UInt<32>, exu_csr_rs1_x : UInt<32>}, flip dec_alu : {flip dec_i0_alu_decode_d : UInt<1>, flip dec_csr_ren_d : UInt<1>, flip dec_i0_br_immed_d : UInt<12>, exu_i0_pc_x : UInt<31>}, flip dec_div : {flip div_p : {valid : UInt<1>, bits : {unsign : UInt<1>, rem : UInt<1>}}, flip dec_div_cancel : UInt<1>}, flip dctl_busbuff : {lsu_nonblock_load_valid_m : UInt<1>, lsu_nonblock_load_tag_m : UInt<2>, lsu_nonblock_load_inv_r : UInt<1>, lsu_nonblock_load_inv_tag_r : UInt<2>, lsu_nonblock_load_data_valid : UInt<1>, lsu_nonblock_load_data_error : UInt<1>, lsu_nonblock_load_data_tag : UInt<2>, lsu_nonblock_load_data : UInt<32>}, dctl_dma : {flip dma_dccm_stall_any : UInt<1>}, flip dec_tlu_flush_extint : UInt<1>, flip dec_tlu_force_halt : UInt<1>, dec_i0_inst_wb1 : UInt<32>, dec_i0_pc_wb1 : UInt<31>, flip dec_i0_trigger_match_d : UInt<4>, flip dec_tlu_wr_pause_r : UInt<1>, flip dec_tlu_pipelining_disable : UInt<1>, flip lsu_trigger_match_m : UInt<4>, flip lsu_pmu_misaligned_m : UInt<1>, flip dec_tlu_debug_stall : UInt<1>, flip dec_tlu_flush_leak_one_r : UInt<1>, flip dec_debug_fence_d : UInt<1>, flip dec_i0_icaf_d : UInt<1>, flip dec_i0_icaf_f1_d : UInt<1>, flip dec_i0_icaf_type_d : UInt<2>, flip dec_i0_dbecc_d : UInt<1>, flip dec_i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}, flip dec_i0_bp_index : UInt<8>, flip dec_i0_bp_fghr : UInt<8>, flip dec_i0_bp_btag : UInt<5>, flip dec_i0_pc_d : UInt<31>, flip lsu_idle_any : UInt<1>, flip lsu_load_stall_any : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip exu_div_wren : UInt<1>, flip dec_tlu_i0_kill_writeb_wb : UInt<1>, flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_i0_kill_writeb_r : UInt<1>, flip dec_tlu_flush_lower_r : UInt<1>, flip dec_tlu_flush_pause_r : UInt<1>, flip dec_tlu_presync_d : UInt<1>, flip dec_tlu_postsync_d : UInt<1>, flip dec_i0_pc4_d : UInt<1>, flip dec_csr_rddata_d : UInt<32>, flip dec_csr_legal_d : UInt<1>, flip lsu_result_m : UInt<32>, flip lsu_result_corr_r : UInt<32>, flip exu_flush_final : UInt<1>, flip dec_i0_instr_d : UInt<32>, flip dec_ib0_valid_d : UInt<1>, flip free_clk : Clock, flip active_clk : Clock, flip clk_override : UInt<1>, dec_i0_rs1_d : UInt<5>, dec_i0_rs2_d : UInt<5>, dec_i0_waddr_r : UInt<5>, dec_i0_wen_r : UInt<1>, dec_i0_wdata_r : UInt<32>, lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, div_waddr_wb : UInt<5>, dec_lsu_valid_raw_d : UInt<1>, dec_lsu_offset_d : UInt<12>, dec_csr_wen_unq_d : UInt<1>, dec_csr_any_unq_d : UInt<1>, dec_csr_rdaddr_d : UInt<12>, dec_csr_wen_r : UInt<1>, dec_csr_wraddr_r : UInt<12>, dec_csr_wrdata_r : UInt<32>, dec_csr_stall_int_ff : UInt<1>, dec_tlu_i0_valid_r : UInt<1>, dec_tlu_packet_r : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, dec_tlu_i0_pc_r : UInt<31>, dec_illegal_inst : UInt<32>, dec_pmu_instr_decoded : UInt<1>, dec_pmu_decode_stall : UInt<1>, dec_pmu_presync_stall : UInt<1>, dec_pmu_postsync_stall : UInt<1>, dec_nonblock_load_wen : UInt<1>, dec_nonblock_load_waddr : UInt<5>, dec_pause_state : UInt<1>, dec_pause_state_cg : UInt<1>, dec_div_active : UInt<1>, flip scan_mode : UInt<1>, flip dec_aln : {flip dec_i0_decode_d : UInt<1>, ifu_i0_cinst : UInt<16>}, dbg_dctl : {flip dbg_cmd_wrdata : UInt<2>}} + output io : {flip decode_exu : {flip dec_data_en : UInt<2>, flip dec_ctl_en : UInt<2>, flip i0_ap : {land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, flip dec_i0_predict_p_d : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, flip i0_predict_fghr_d : UInt<8>, flip i0_predict_index_d : UInt<8>, flip i0_predict_btag_d : UInt<5>, flip dec_i0_rs1_en_d : UInt<1>, flip dec_i0_rs2_en_d : UInt<1>, flip dec_i0_immed_d : UInt<32>, flip dec_i0_rs1_bypass_data_d : UInt<32>, flip dec_i0_rs2_bypass_data_d : UInt<32>, flip dec_i0_select_pc_d : UInt<1>, flip dec_i0_rs1_bypass_en_d : UInt<2>, flip dec_i0_rs2_bypass_en_d : UInt<2>, flip mul_p : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}}, flip pred_correct_npc_x : UInt<31>, flip dec_extint_stall : UInt<1>, exu_i0_result_x : UInt<32>, exu_csr_rs1_x : UInt<32>}, flip dec_alu : {flip dec_i0_alu_decode_d : UInt<1>, flip dec_csr_ren_d : UInt<1>, flip dec_i0_br_immed_d : UInt<12>, exu_i0_pc_x : UInt<31>}, flip dec_div : {flip div_p : {valid : UInt<1>, bits : {unsign : UInt<1>, rem : UInt<1>}}, flip dec_div_cancel : UInt<1>}, flip dctl_busbuff : {lsu_nonblock_load_valid_m : UInt<1>, lsu_nonblock_load_tag_m : UInt<2>, lsu_nonblock_load_inv_r : UInt<1>, lsu_nonblock_load_inv_tag_r : UInt<2>, lsu_nonblock_load_data_valid : UInt<1>, lsu_nonblock_load_data_error : UInt<1>, lsu_nonblock_load_data_tag : UInt<2>, lsu_nonblock_load_data : UInt<32>}, dctl_dma : {flip dma_dccm_stall_any : UInt<1>}, flip dec_aln : {flip dec_i0_decode_d : UInt<1>, ifu_i0_cinst : UInt<16>}, dbg_dctl : {flip dbg_cmd_wrdata : UInt<2>}, flip dec_tlu_flush_extint : UInt<1>, flip dec_tlu_force_halt : UInt<1>, dec_i0_inst_wb1 : UInt<32>, dec_i0_pc_wb1 : UInt<31>, flip dec_i0_trigger_match_d : UInt<4>, flip dec_tlu_wr_pause_r : UInt<1>, flip dec_tlu_pipelining_disable : UInt<1>, flip lsu_trigger_match_m : UInt<4>, flip lsu_pmu_misaligned_m : UInt<1>, flip dec_tlu_debug_stall : UInt<1>, flip dec_tlu_flush_leak_one_r : UInt<1>, flip dec_debug_fence_d : UInt<1>, flip dec_i0_icaf_d : UInt<1>, flip dec_i0_icaf_f1_d : UInt<1>, flip dec_i0_icaf_type_d : UInt<2>, flip dec_i0_dbecc_d : UInt<1>, flip dec_i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}, flip dec_i0_bp_index : UInt<8>, flip dec_i0_bp_fghr : UInt<8>, flip dec_i0_bp_btag : UInt<5>, flip dec_i0_pc_d : UInt<31>, flip lsu_idle_any : UInt<1>, flip lsu_load_stall_any : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip exu_div_wren : UInt<1>, flip dec_tlu_i0_kill_writeb_wb : UInt<1>, flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_i0_kill_writeb_r : UInt<1>, flip dec_tlu_flush_lower_r : UInt<1>, flip dec_tlu_flush_pause_r : UInt<1>, flip dec_tlu_presync_d : UInt<1>, flip dec_tlu_postsync_d : UInt<1>, flip dec_i0_pc4_d : UInt<1>, flip dec_csr_rddata_d : UInt<32>, flip dec_csr_legal_d : UInt<1>, flip lsu_result_m : UInt<32>, flip lsu_result_corr_r : UInt<32>, flip exu_flush_final : UInt<1>, flip dec_i0_instr_d : UInt<32>, flip dec_ib0_valid_d : UInt<1>, flip free_clk : Clock, flip active_clk : Clock, flip clk_override : UInt<1>, dec_i0_rs1_d : UInt<5>, dec_i0_rs2_d : UInt<5>, dec_i0_waddr_r : UInt<5>, dec_i0_wen_r : UInt<1>, dec_i0_wdata_r : UInt<32>, lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, div_waddr_wb : UInt<5>, dec_lsu_valid_raw_d : UInt<1>, dec_lsu_offset_d : UInt<12>, dec_csr_wen_unq_d : UInt<1>, dec_csr_any_unq_d : UInt<1>, dec_csr_rdaddr_d : UInt<12>, dec_csr_wen_r : UInt<1>, dec_csr_wraddr_r : UInt<12>, dec_csr_wrdata_r : UInt<32>, dec_csr_stall_int_ff : UInt<1>, dec_tlu_i0_valid_r : UInt<1>, dec_tlu_packet_r : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, dec_tlu_i0_pc_r : UInt<31>, dec_illegal_inst : UInt<32>, dec_pmu_instr_decoded : UInt<1>, dec_pmu_decode_stall : UInt<1>, dec_pmu_presync_stall : UInt<1>, dec_pmu_postsync_stall : UInt<1>, dec_nonblock_load_wen : UInt<1>, dec_nonblock_load_waddr : UInt<5>, dec_pause_state : UInt<1>, dec_pause_state_cg : UInt<1>, dec_div_active : UInt<1>, flip scan_mode : UInt<1>} - wire _T : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}} @[dec_decode_ctl.scala 97:38] - _T.bits.bfp <= UInt<1>("h00") @[dec_decode_ctl.scala 97:38] - _T.bits.crc32c_w <= UInt<1>("h00") @[dec_decode_ctl.scala 97:38] - _T.bits.crc32c_h <= UInt<1>("h00") @[dec_decode_ctl.scala 97:38] - _T.bits.crc32c_b <= UInt<1>("h00") @[dec_decode_ctl.scala 97:38] - _T.bits.crc32_w <= UInt<1>("h00") @[dec_decode_ctl.scala 97:38] - _T.bits.crc32_h <= UInt<1>("h00") @[dec_decode_ctl.scala 97:38] - _T.bits.crc32_b <= UInt<1>("h00") @[dec_decode_ctl.scala 97:38] - _T.bits.unshfl <= UInt<1>("h00") @[dec_decode_ctl.scala 97:38] - _T.bits.shfl <= UInt<1>("h00") @[dec_decode_ctl.scala 97:38] - _T.bits.grev <= UInt<1>("h00") @[dec_decode_ctl.scala 97:38] - _T.bits.clmulr <= UInt<1>("h00") @[dec_decode_ctl.scala 97:38] - _T.bits.clmulh <= UInt<1>("h00") @[dec_decode_ctl.scala 97:38] - _T.bits.clmul <= UInt<1>("h00") @[dec_decode_ctl.scala 97:38] - _T.bits.bdep <= UInt<1>("h00") @[dec_decode_ctl.scala 97:38] - _T.bits.bext <= UInt<1>("h00") @[dec_decode_ctl.scala 97:38] - _T.bits.low <= UInt<1>("h00") @[dec_decode_ctl.scala 97:38] - _T.bits.rs2_sign <= UInt<1>("h00") @[dec_decode_ctl.scala 97:38] - _T.bits.rs1_sign <= UInt<1>("h00") @[dec_decode_ctl.scala 97:38] - _T.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 97:38] - io.decode_exu.mul_p.bits.bfp <= _T.bits.bfp @[dec_decode_ctl.scala 97:23] - io.decode_exu.mul_p.bits.crc32c_w <= _T.bits.crc32c_w @[dec_decode_ctl.scala 97:23] - io.decode_exu.mul_p.bits.crc32c_h <= _T.bits.crc32c_h @[dec_decode_ctl.scala 97:23] - io.decode_exu.mul_p.bits.crc32c_b <= _T.bits.crc32c_b @[dec_decode_ctl.scala 97:23] - io.decode_exu.mul_p.bits.crc32_w <= _T.bits.crc32_w @[dec_decode_ctl.scala 97:23] - io.decode_exu.mul_p.bits.crc32_h <= _T.bits.crc32_h @[dec_decode_ctl.scala 97:23] - io.decode_exu.mul_p.bits.crc32_b <= _T.bits.crc32_b @[dec_decode_ctl.scala 97:23] - io.decode_exu.mul_p.bits.unshfl <= _T.bits.unshfl @[dec_decode_ctl.scala 97:23] - io.decode_exu.mul_p.bits.shfl <= _T.bits.shfl @[dec_decode_ctl.scala 97:23] - io.decode_exu.mul_p.bits.grev <= _T.bits.grev @[dec_decode_ctl.scala 97:23] - io.decode_exu.mul_p.bits.clmulr <= _T.bits.clmulr @[dec_decode_ctl.scala 97:23] - io.decode_exu.mul_p.bits.clmulh <= _T.bits.clmulh @[dec_decode_ctl.scala 97:23] - io.decode_exu.mul_p.bits.clmul <= _T.bits.clmul @[dec_decode_ctl.scala 97:23] - io.decode_exu.mul_p.bits.bdep <= _T.bits.bdep @[dec_decode_ctl.scala 97:23] - io.decode_exu.mul_p.bits.bext <= _T.bits.bext @[dec_decode_ctl.scala 97:23] - io.decode_exu.mul_p.bits.low <= _T.bits.low @[dec_decode_ctl.scala 97:23] - io.decode_exu.mul_p.bits.rs2_sign <= _T.bits.rs2_sign @[dec_decode_ctl.scala 97:23] - io.decode_exu.mul_p.bits.rs1_sign <= _T.bits.rs1_sign @[dec_decode_ctl.scala 97:23] - io.decode_exu.mul_p.valid <= _T.valid @[dec_decode_ctl.scala 97:23] + wire _T : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}} @[dec_decode_ctl.scala 95:40] + _T.bits.bfp <= UInt<1>("h00") @[dec_decode_ctl.scala 95:40] + _T.bits.crc32c_w <= UInt<1>("h00") @[dec_decode_ctl.scala 95:40] + _T.bits.crc32c_h <= UInt<1>("h00") @[dec_decode_ctl.scala 95:40] + _T.bits.crc32c_b <= UInt<1>("h00") @[dec_decode_ctl.scala 95:40] + _T.bits.crc32_w <= UInt<1>("h00") @[dec_decode_ctl.scala 95:40] + _T.bits.crc32_h <= UInt<1>("h00") @[dec_decode_ctl.scala 95:40] + _T.bits.crc32_b <= UInt<1>("h00") @[dec_decode_ctl.scala 95:40] + _T.bits.unshfl <= UInt<1>("h00") @[dec_decode_ctl.scala 95:40] + _T.bits.shfl <= UInt<1>("h00") @[dec_decode_ctl.scala 95:40] + _T.bits.grev <= UInt<1>("h00") @[dec_decode_ctl.scala 95:40] + _T.bits.clmulr <= UInt<1>("h00") @[dec_decode_ctl.scala 95:40] + _T.bits.clmulh <= UInt<1>("h00") @[dec_decode_ctl.scala 95:40] + _T.bits.clmul <= UInt<1>("h00") @[dec_decode_ctl.scala 95:40] + _T.bits.bdep <= UInt<1>("h00") @[dec_decode_ctl.scala 95:40] + _T.bits.bext <= UInt<1>("h00") @[dec_decode_ctl.scala 95:40] + _T.bits.low <= UInt<1>("h00") @[dec_decode_ctl.scala 95:40] + _T.bits.rs2_sign <= UInt<1>("h00") @[dec_decode_ctl.scala 95:40] + _T.bits.rs1_sign <= UInt<1>("h00") @[dec_decode_ctl.scala 95:40] + _T.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 95:40] + io.decode_exu.mul_p.bits.bfp <= _T.bits.bfp @[dec_decode_ctl.scala 95:25] + io.decode_exu.mul_p.bits.crc32c_w <= _T.bits.crc32c_w @[dec_decode_ctl.scala 95:25] + io.decode_exu.mul_p.bits.crc32c_h <= _T.bits.crc32c_h @[dec_decode_ctl.scala 95:25] + io.decode_exu.mul_p.bits.crc32c_b <= _T.bits.crc32c_b @[dec_decode_ctl.scala 95:25] + io.decode_exu.mul_p.bits.crc32_w <= _T.bits.crc32_w @[dec_decode_ctl.scala 95:25] + io.decode_exu.mul_p.bits.crc32_h <= _T.bits.crc32_h @[dec_decode_ctl.scala 95:25] + io.decode_exu.mul_p.bits.crc32_b <= _T.bits.crc32_b @[dec_decode_ctl.scala 95:25] + io.decode_exu.mul_p.bits.unshfl <= _T.bits.unshfl @[dec_decode_ctl.scala 95:25] + io.decode_exu.mul_p.bits.shfl <= _T.bits.shfl @[dec_decode_ctl.scala 95:25] + io.decode_exu.mul_p.bits.grev <= _T.bits.grev @[dec_decode_ctl.scala 95:25] + io.decode_exu.mul_p.bits.clmulr <= _T.bits.clmulr @[dec_decode_ctl.scala 95:25] + io.decode_exu.mul_p.bits.clmulh <= _T.bits.clmulh @[dec_decode_ctl.scala 95:25] + io.decode_exu.mul_p.bits.clmul <= _T.bits.clmul @[dec_decode_ctl.scala 95:25] + io.decode_exu.mul_p.bits.bdep <= _T.bits.bdep @[dec_decode_ctl.scala 95:25] + io.decode_exu.mul_p.bits.bext <= _T.bits.bext @[dec_decode_ctl.scala 95:25] + io.decode_exu.mul_p.bits.low <= _T.bits.low @[dec_decode_ctl.scala 95:25] + io.decode_exu.mul_p.bits.rs2_sign <= _T.bits.rs2_sign @[dec_decode_ctl.scala 95:25] + io.decode_exu.mul_p.bits.rs1_sign <= _T.bits.rs1_sign @[dec_decode_ctl.scala 95:25] + io.decode_exu.mul_p.valid <= _T.valid @[dec_decode_ctl.scala 95:25] wire leak1_i1_stall_in : UInt<1> leak1_i1_stall_in <= UInt<1>("h00") wire leak1_i0_stall_in : UInt<1> leak1_i0_stall_in <= UInt<1>("h00") - wire i0r : {rs1 : UInt<5>, rs2 : UInt<5>, rd : UInt<5>} @[dec_decode_ctl.scala 101:17] - wire d_t : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[dec_decode_ctl.scala 102:17] - wire x_t : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[dec_decode_ctl.scala 103:17] - wire x_t_in : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[dec_decode_ctl.scala 104:20] - wire r_t : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[dec_decode_ctl.scala 105:17] - wire r_t_in : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[dec_decode_ctl.scala 106:23] - wire d_d : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[dec_decode_ctl.scala 107:17] - wire x_d : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[dec_decode_ctl.scala 108:17] - wire r_d : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[dec_decode_ctl.scala 109:17] - wire r_d_in : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[dec_decode_ctl.scala 110:20] - wire wbd : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[dec_decode_ctl.scala 111:17] - wire i0_d_c : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 112:20] - wire i0_rs1_class_d : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 113:28] - wire i0_rs2_class_d : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 114:28] + wire i0r : {rs1 : UInt<5>, rs2 : UInt<5>, rd : UInt<5>} @[dec_decode_ctl.scala 99:37] + wire d_t : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[dec_decode_ctl.scala 100:37] + wire x_t : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[dec_decode_ctl.scala 101:37] + wire x_t_in : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[dec_decode_ctl.scala 102:37] + wire r_t : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[dec_decode_ctl.scala 103:37] + wire r_t_in : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[dec_decode_ctl.scala 104:37] + wire d_d : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[dec_decode_ctl.scala 105:37] + wire x_d : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[dec_decode_ctl.scala 106:37] + wire r_d : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[dec_decode_ctl.scala 107:37] + wire r_d_in : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[dec_decode_ctl.scala 108:37] + wire wbd : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[dec_decode_ctl.scala 109:37] + wire i0_d_c : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 110:37] + wire i0_rs1_class_d : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 111:37] + wire i0_rs2_class_d : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 112:37] wire i0_rs1_depth_d : UInt<2> i0_rs1_depth_d <= UInt<1>("h00") wire i0_rs2_depth_d : UInt<2> i0_rs2_depth_d <= UInt<1>("h00") wire cam_wen : UInt<4> cam_wen <= UInt<1>("h00") - wire cam : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}[4] @[dec_decode_ctl.scala 118:17] + wire cam : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}[4] @[dec_decode_ctl.scala 116:37] wire cam_write : UInt<1> cam_write <= UInt<1>("h00") - wire cam_inv_reset_val : UInt<1>[4] @[dec_decode_ctl.scala 120:29] - wire cam_data_reset_val : UInt<1>[4] @[dec_decode_ctl.scala 121:30] - wire nonblock_load_write : UInt<1>[4] @[dec_decode_ctl.scala 122:31] - wire cam_raw : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}[4] @[dec_decode_ctl.scala 123:20] - wire cam_in : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}[4] @[dec_decode_ctl.scala 124:20] - wire i0_dp : {alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>} @[dec_decode_ctl.scala 126:18] - wire i0_dp_raw : {alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>} @[dec_decode_ctl.scala 127:22] + wire cam_inv_reset_val : UInt<1>[4] @[dec_decode_ctl.scala 118:37] + wire cam_data_reset_val : UInt<1>[4] @[dec_decode_ctl.scala 119:37] + wire nonblock_load_write : UInt<1>[4] @[dec_decode_ctl.scala 120:37] + wire cam_raw : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}[4] @[dec_decode_ctl.scala 121:37] + wire cam_in : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}[4] @[dec_decode_ctl.scala 122:37] + wire i0_dp : {alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>} @[dec_decode_ctl.scala 123:37] + wire i0_dp_raw : {alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>} @[dec_decode_ctl.scala 124:37] wire i0_rs1bypass : UInt<3> i0_rs1bypass <= UInt<1>("h00") wire i0_rs2bypass : UInt<3> @@ -67005,299 +67005,299 @@ circuit quasar_wrapper : i0_result_x <= UInt<1>("h00") wire i0_result_r : UInt<32> i0_result_r <= UInt<1>("h00") - node _T_1 = xor(io.dec_tlu_wr_pause_r, tlu_wr_pause_r1) @[dec_decode_ctl.scala 181:51] - node _T_2 = xor(tlu_wr_pause_r1, tlu_wr_pause_r2) @[dec_decode_ctl.scala 182:32] - node _T_3 = or(_T_1, _T_2) @[dec_decode_ctl.scala 181:73] - node _T_4 = xor(io.dec_tlu_flush_extint, io.decode_exu.dec_extint_stall) @[dec_decode_ctl.scala 183:32] - node _T_5 = or(_T_3, _T_4) @[dec_decode_ctl.scala 182:56] - node _T_6 = xor(leak1_i1_stall_in, leak1_i1_stall) @[dec_decode_ctl.scala 184:32] - node _T_7 = or(_T_5, _T_6) @[dec_decode_ctl.scala 183:67] - node _T_8 = xor(leak1_i0_stall_in, leak1_i0_stall) @[dec_decode_ctl.scala 185:32] - node _T_9 = or(_T_7, _T_8) @[dec_decode_ctl.scala 184:56] - node _T_10 = xor(pause_state_in, pause_stall) @[dec_decode_ctl.scala 186:32] - node _T_11 = or(_T_9, _T_10) @[dec_decode_ctl.scala 185:56] - node _T_12 = xor(ps_stall_in, postsync_stall) @[dec_decode_ctl.scala 187:32] - node _T_13 = or(_T_11, _T_12) @[dec_decode_ctl.scala 186:56] - node _T_14 = xor(io.exu_flush_final, flush_final_r) @[dec_decode_ctl.scala 188:32] - node _T_15 = or(_T_13, _T_14) @[dec_decode_ctl.scala 187:56] - node _T_16 = xor(illegal_lockout_in, illegal_lockout) @[dec_decode_ctl.scala 189:32] - node data_gate_en = or(_T_15, _T_16) @[dec_decode_ctl.scala 188:56] - node _T_17 = bits(data_gate_en, 0, 0) @[dec_decode_ctl.scala 192:56] + node _T_1 = xor(io.dec_tlu_wr_pause_r, tlu_wr_pause_r1) @[dec_decode_ctl.scala 178:54] + node _T_2 = xor(tlu_wr_pause_r1, tlu_wr_pause_r2) @[dec_decode_ctl.scala 179:54] + node _T_3 = or(_T_1, _T_2) @[dec_decode_ctl.scala 178:89] + node _T_4 = xor(io.dec_tlu_flush_extint, io.decode_exu.dec_extint_stall) @[dec_decode_ctl.scala 180:54] + node _T_5 = or(_T_3, _T_4) @[dec_decode_ctl.scala 179:89] + node _T_6 = xor(leak1_i1_stall_in, leak1_i1_stall) @[dec_decode_ctl.scala 181:54] + node _T_7 = or(_T_5, _T_6) @[dec_decode_ctl.scala 180:89] + node _T_8 = xor(leak1_i0_stall_in, leak1_i0_stall) @[dec_decode_ctl.scala 182:54] + node _T_9 = or(_T_7, _T_8) @[dec_decode_ctl.scala 181:89] + node _T_10 = xor(pause_state_in, pause_stall) @[dec_decode_ctl.scala 183:54] + node _T_11 = or(_T_9, _T_10) @[dec_decode_ctl.scala 182:89] + node _T_12 = xor(ps_stall_in, postsync_stall) @[dec_decode_ctl.scala 184:54] + node _T_13 = or(_T_11, _T_12) @[dec_decode_ctl.scala 183:89] + node _T_14 = xor(io.exu_flush_final, flush_final_r) @[dec_decode_ctl.scala 185:54] + node _T_15 = or(_T_13, _T_14) @[dec_decode_ctl.scala 184:89] + node _T_16 = xor(illegal_lockout_in, illegal_lockout) @[dec_decode_ctl.scala 186:54] + node data_gate_en = or(_T_15, _T_16) @[dec_decode_ctl.scala 185:89] + node _T_17 = bits(data_gate_en, 0, 0) @[dec_decode_ctl.scala 189:57] inst rvclkhdr of rvclkhdr_661 @[lib.scala 343:22] rvclkhdr.clock <= clock rvclkhdr.reset <= reset rvclkhdr.io.clk <= clock @[lib.scala 344:17] rvclkhdr.io.en <= _T_17 @[lib.scala 345:16] rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - node _T_18 = eq(leak1_mode, UInt<1>("h00")) @[dec_decode_ctl.scala 196:62] - node i0_brp_valid = and(io.dec_i0_brp.valid, _T_18) @[dec_decode_ctl.scala 196:60] - io.decode_exu.dec_i0_predict_p_d.bits.misp <= UInt<1>("h00") @[dec_decode_ctl.scala 197:54] - io.decode_exu.dec_i0_predict_p_d.bits.ataken <= UInt<1>("h00") @[dec_decode_ctl.scala 198:54] - io.decode_exu.dec_i0_predict_p_d.bits.boffset <= UInt<1>("h00") @[dec_decode_ctl.scala 199:54] - io.decode_exu.dec_i0_predict_p_d.bits.pcall <= i0_pcall @[dec_decode_ctl.scala 200:54] - io.decode_exu.dec_i0_predict_p_d.bits.pja <= i0_pja @[dec_decode_ctl.scala 201:54] - io.decode_exu.dec_i0_predict_p_d.bits.pret <= i0_pret @[dec_decode_ctl.scala 202:54] - io.decode_exu.dec_i0_predict_p_d.bits.prett <= io.dec_i0_brp.bits.prett @[dec_decode_ctl.scala 203:54] - io.decode_exu.dec_i0_predict_p_d.bits.pc4 <= io.dec_i0_pc4_d @[dec_decode_ctl.scala 204:54] - io.decode_exu.dec_i0_predict_p_d.bits.hist <= io.dec_i0_brp.bits.hist @[dec_decode_ctl.scala 205:54] - node _T_19 = and(i0_brp_valid, i0_legal_decode_d) @[dec_decode_ctl.scala 206:66] - io.decode_exu.dec_i0_predict_p_d.valid <= _T_19 @[dec_decode_ctl.scala 206:49] - node _T_20 = or(i0_dp_raw.condbr, i0_pcall_raw) @[dec_decode_ctl.scala 207:75] - node _T_21 = or(_T_20, i0_pja_raw) @[dec_decode_ctl.scala 207:90] - node _T_22 = or(_T_21, i0_pret_raw) @[dec_decode_ctl.scala 207:103] - node _T_23 = eq(_T_22, UInt<1>("h00")) @[dec_decode_ctl.scala 207:56] - node i0_notbr_error = and(i0_brp_valid, _T_23) @[dec_decode_ctl.scala 207:54] - node _T_24 = bits(io.dec_i0_brp.bits.hist, 1, 1) @[dec_decode_ctl.scala 210:72] - node _T_25 = and(i0_brp_valid, _T_24) @[dec_decode_ctl.scala 210:47] - node _T_26 = neq(io.dec_i0_brp.bits.toffset, i0_br_offset) @[dec_decode_ctl.scala 210:106] - node _T_27 = and(_T_25, _T_26) @[dec_decode_ctl.scala 210:76] - node _T_28 = eq(i0_pret_raw, UInt<1>("h00")) @[dec_decode_ctl.scala 210:126] - node i0_br_toffset_error = and(_T_27, _T_28) @[dec_decode_ctl.scala 210:124] - node _T_29 = and(i0_brp_valid, io.dec_i0_brp.bits.ret) @[dec_decode_ctl.scala 211:47] - node _T_30 = eq(i0_pret_raw, UInt<1>("h00")) @[dec_decode_ctl.scala 211:74] - node i0_ret_error = and(_T_29, _T_30) @[dec_decode_ctl.scala 211:72] - node _T_31 = or(io.dec_i0_brp.bits.br_error, i0_notbr_error) @[dec_decode_ctl.scala 212:62] - node _T_32 = or(_T_31, i0_br_toffset_error) @[dec_decode_ctl.scala 212:79] - node i0_br_error = or(_T_32, i0_ret_error) @[dec_decode_ctl.scala 212:101] - node _T_33 = and(i0_br_error, i0_legal_decode_d) @[dec_decode_ctl.scala 213:83] - node _T_34 = eq(leak1_mode, UInt<1>("h00")) @[dec_decode_ctl.scala 213:105] - node _T_35 = and(_T_33, _T_34) @[dec_decode_ctl.scala 213:103] - io.decode_exu.dec_i0_predict_p_d.bits.br_error <= _T_35 @[dec_decode_ctl.scala 213:67] - node _T_36 = and(io.dec_i0_brp.bits.br_start_error, i0_legal_decode_d) @[dec_decode_ctl.scala 214:105] - node _T_37 = eq(leak1_mode, UInt<1>("h00")) @[dec_decode_ctl.scala 214:127] - node _T_38 = and(_T_36, _T_37) @[dec_decode_ctl.scala 214:125] - io.decode_exu.dec_i0_predict_p_d.bits.br_start_error <= _T_38 @[dec_decode_ctl.scala 214:67] - io.decode_exu.i0_predict_index_d <= io.dec_i0_bp_index @[dec_decode_ctl.scala 215:43] - io.decode_exu.i0_predict_btag_d <= io.dec_i0_bp_btag @[dec_decode_ctl.scala 216:43] - node _T_39 = or(i0_br_error, io.dec_i0_brp.bits.br_start_error) @[dec_decode_ctl.scala 217:47] - node _T_40 = eq(leak1_mode, UInt<1>("h00")) @[dec_decode_ctl.scala 217:86] - node i0_br_error_all = and(_T_39, _T_40) @[dec_decode_ctl.scala 217:84] - io.decode_exu.dec_i0_predict_p_d.bits.toffset <= i0_br_offset @[dec_decode_ctl.scala 218:60] - io.decode_exu.i0_predict_fghr_d <= io.dec_i0_bp_fghr @[dec_decode_ctl.scala 219:43] - io.decode_exu.dec_i0_predict_p_d.bits.way <= io.dec_i0_brp.bits.way @[dec_decode_ctl.scala 220:67] - node i0_icaf_d = or(io.dec_i0_icaf_d, io.dec_i0_dbecc_d) @[dec_decode_ctl.scala 226:36] - i0_dp.legal <= i0_dp_raw.legal @[dec_decode_ctl.scala 229:9] - i0_dp.pm_alu <= i0_dp_raw.pm_alu @[dec_decode_ctl.scala 229:9] - i0_dp.fence_i <= i0_dp_raw.fence_i @[dec_decode_ctl.scala 229:9] - i0_dp.fence <= i0_dp_raw.fence @[dec_decode_ctl.scala 229:9] - i0_dp.rem <= i0_dp_raw.rem @[dec_decode_ctl.scala 229:9] - i0_dp.div <= i0_dp_raw.div @[dec_decode_ctl.scala 229:9] - i0_dp.low <= i0_dp_raw.low @[dec_decode_ctl.scala 229:9] - i0_dp.rs2_sign <= i0_dp_raw.rs2_sign @[dec_decode_ctl.scala 229:9] - i0_dp.rs1_sign <= i0_dp_raw.rs1_sign @[dec_decode_ctl.scala 229:9] - i0_dp.mul <= i0_dp_raw.mul @[dec_decode_ctl.scala 229:9] - i0_dp.mret <= i0_dp_raw.mret @[dec_decode_ctl.scala 229:9] - i0_dp.ecall <= i0_dp_raw.ecall @[dec_decode_ctl.scala 229:9] - i0_dp.ebreak <= i0_dp_raw.ebreak @[dec_decode_ctl.scala 229:9] - i0_dp.postsync <= i0_dp_raw.postsync @[dec_decode_ctl.scala 229:9] - i0_dp.presync <= i0_dp_raw.presync @[dec_decode_ctl.scala 229:9] - i0_dp.csr_imm <= i0_dp_raw.csr_imm @[dec_decode_ctl.scala 229:9] - i0_dp.csr_write <= i0_dp_raw.csr_write @[dec_decode_ctl.scala 229:9] - i0_dp.csr_set <= i0_dp_raw.csr_set @[dec_decode_ctl.scala 229:9] - i0_dp.csr_clr <= i0_dp_raw.csr_clr @[dec_decode_ctl.scala 229:9] - i0_dp.csr_read <= i0_dp_raw.csr_read @[dec_decode_ctl.scala 229:9] - i0_dp.word <= i0_dp_raw.word @[dec_decode_ctl.scala 229:9] - i0_dp.half <= i0_dp_raw.half @[dec_decode_ctl.scala 229:9] - i0_dp.by <= i0_dp_raw.by @[dec_decode_ctl.scala 229:9] - i0_dp.jal <= i0_dp_raw.jal @[dec_decode_ctl.scala 229:9] - i0_dp.blt <= i0_dp_raw.blt @[dec_decode_ctl.scala 229:9] - i0_dp.bge <= i0_dp_raw.bge @[dec_decode_ctl.scala 229:9] - i0_dp.bne <= i0_dp_raw.bne @[dec_decode_ctl.scala 229:9] - i0_dp.beq <= i0_dp_raw.beq @[dec_decode_ctl.scala 229:9] - i0_dp.condbr <= i0_dp_raw.condbr @[dec_decode_ctl.scala 229:9] - i0_dp.unsign <= i0_dp_raw.unsign @[dec_decode_ctl.scala 229:9] - i0_dp.slt <= i0_dp_raw.slt @[dec_decode_ctl.scala 229:9] - i0_dp.srl <= i0_dp_raw.srl @[dec_decode_ctl.scala 229:9] - i0_dp.sra <= i0_dp_raw.sra @[dec_decode_ctl.scala 229:9] - i0_dp.sll <= i0_dp_raw.sll @[dec_decode_ctl.scala 229:9] - i0_dp.lxor <= i0_dp_raw.lxor @[dec_decode_ctl.scala 229:9] - i0_dp.lor <= i0_dp_raw.lor @[dec_decode_ctl.scala 229:9] - i0_dp.land <= i0_dp_raw.land @[dec_decode_ctl.scala 229:9] - i0_dp.sub <= i0_dp_raw.sub @[dec_decode_ctl.scala 229:9] - i0_dp.add <= i0_dp_raw.add @[dec_decode_ctl.scala 229:9] - i0_dp.lsu <= i0_dp_raw.lsu @[dec_decode_ctl.scala 229:9] - i0_dp.store <= i0_dp_raw.store @[dec_decode_ctl.scala 229:9] - i0_dp.load <= i0_dp_raw.load @[dec_decode_ctl.scala 229:9] - i0_dp.pc <= i0_dp_raw.pc @[dec_decode_ctl.scala 229:9] - i0_dp.imm20 <= i0_dp_raw.imm20 @[dec_decode_ctl.scala 229:9] - i0_dp.shimm5 <= i0_dp_raw.shimm5 @[dec_decode_ctl.scala 229:9] - i0_dp.rd <= i0_dp_raw.rd @[dec_decode_ctl.scala 229:9] - i0_dp.imm12 <= i0_dp_raw.imm12 @[dec_decode_ctl.scala 229:9] - i0_dp.rs2 <= i0_dp_raw.rs2 @[dec_decode_ctl.scala 229:9] - i0_dp.rs1 <= i0_dp_raw.rs1 @[dec_decode_ctl.scala 229:9] - i0_dp.alu <= i0_dp_raw.alu @[dec_decode_ctl.scala 229:9] - node _T_41 = or(i0_br_error_all, i0_icaf_d) @[dec_decode_ctl.scala 230:25] - node _T_42 = bits(_T_41, 0, 0) @[dec_decode_ctl.scala 230:43] - when _T_42 : @[dec_decode_ctl.scala 230:50] - wire _T_43 : {alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>} @[dec_decode_ctl.scala 231:35] - _T_43.legal <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] - _T_43.pm_alu <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] - _T_43.fence_i <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] - _T_43.fence <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] - _T_43.rem <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] - _T_43.div <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] - _T_43.low <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] - _T_43.rs2_sign <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] - _T_43.rs1_sign <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] - _T_43.mul <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] - _T_43.mret <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] - _T_43.ecall <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] - _T_43.ebreak <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] - _T_43.postsync <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] - _T_43.presync <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] - _T_43.csr_imm <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] - _T_43.csr_write <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] - _T_43.csr_set <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] - _T_43.csr_clr <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] - _T_43.csr_read <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] - _T_43.word <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] - _T_43.half <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] - _T_43.by <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] - _T_43.jal <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] - _T_43.blt <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] - _T_43.bge <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] - _T_43.bne <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] - _T_43.beq <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] - _T_43.condbr <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] - _T_43.unsign <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] - _T_43.slt <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] - _T_43.srl <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] - _T_43.sra <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] - _T_43.sll <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] - _T_43.lxor <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] - _T_43.lor <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] - _T_43.land <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] - _T_43.sub <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] - _T_43.add <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] - _T_43.lsu <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] - _T_43.store <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] - _T_43.load <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] - _T_43.pc <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] - _T_43.imm20 <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] - _T_43.shimm5 <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] - _T_43.rd <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] - _T_43.imm12 <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] - _T_43.rs2 <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] - _T_43.rs1 <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] - _T_43.alu <= UInt<1>("h00") @[dec_decode_ctl.scala 231:35] - i0_dp.legal <= _T_43.legal @[dec_decode_ctl.scala 231:20] - i0_dp.pm_alu <= _T_43.pm_alu @[dec_decode_ctl.scala 231:20] - i0_dp.fence_i <= _T_43.fence_i @[dec_decode_ctl.scala 231:20] - i0_dp.fence <= _T_43.fence @[dec_decode_ctl.scala 231:20] - i0_dp.rem <= _T_43.rem @[dec_decode_ctl.scala 231:20] - i0_dp.div <= _T_43.div @[dec_decode_ctl.scala 231:20] - i0_dp.low <= _T_43.low @[dec_decode_ctl.scala 231:20] - i0_dp.rs2_sign <= _T_43.rs2_sign @[dec_decode_ctl.scala 231:20] - i0_dp.rs1_sign <= _T_43.rs1_sign @[dec_decode_ctl.scala 231:20] - i0_dp.mul <= _T_43.mul @[dec_decode_ctl.scala 231:20] - i0_dp.mret <= _T_43.mret @[dec_decode_ctl.scala 231:20] - i0_dp.ecall <= _T_43.ecall @[dec_decode_ctl.scala 231:20] - i0_dp.ebreak <= _T_43.ebreak @[dec_decode_ctl.scala 231:20] - i0_dp.postsync <= _T_43.postsync @[dec_decode_ctl.scala 231:20] - i0_dp.presync <= _T_43.presync @[dec_decode_ctl.scala 231:20] - i0_dp.csr_imm <= _T_43.csr_imm @[dec_decode_ctl.scala 231:20] - i0_dp.csr_write <= _T_43.csr_write @[dec_decode_ctl.scala 231:20] - i0_dp.csr_set <= _T_43.csr_set @[dec_decode_ctl.scala 231:20] - i0_dp.csr_clr <= _T_43.csr_clr @[dec_decode_ctl.scala 231:20] - i0_dp.csr_read <= _T_43.csr_read @[dec_decode_ctl.scala 231:20] - i0_dp.word <= _T_43.word @[dec_decode_ctl.scala 231:20] - i0_dp.half <= _T_43.half @[dec_decode_ctl.scala 231:20] - i0_dp.by <= _T_43.by @[dec_decode_ctl.scala 231:20] - i0_dp.jal <= _T_43.jal @[dec_decode_ctl.scala 231:20] - i0_dp.blt <= _T_43.blt @[dec_decode_ctl.scala 231:20] - i0_dp.bge <= _T_43.bge @[dec_decode_ctl.scala 231:20] - i0_dp.bne <= _T_43.bne @[dec_decode_ctl.scala 231:20] - i0_dp.beq <= _T_43.beq @[dec_decode_ctl.scala 231:20] - i0_dp.condbr <= _T_43.condbr @[dec_decode_ctl.scala 231:20] - i0_dp.unsign <= _T_43.unsign @[dec_decode_ctl.scala 231:20] - i0_dp.slt <= _T_43.slt @[dec_decode_ctl.scala 231:20] - i0_dp.srl <= _T_43.srl @[dec_decode_ctl.scala 231:20] - i0_dp.sra <= _T_43.sra @[dec_decode_ctl.scala 231:20] - i0_dp.sll <= _T_43.sll @[dec_decode_ctl.scala 231:20] - i0_dp.lxor <= _T_43.lxor @[dec_decode_ctl.scala 231:20] - i0_dp.lor <= _T_43.lor @[dec_decode_ctl.scala 231:20] - i0_dp.land <= _T_43.land @[dec_decode_ctl.scala 231:20] - i0_dp.sub <= _T_43.sub @[dec_decode_ctl.scala 231:20] - i0_dp.add <= _T_43.add @[dec_decode_ctl.scala 231:20] - i0_dp.lsu <= _T_43.lsu @[dec_decode_ctl.scala 231:20] - i0_dp.store <= _T_43.store @[dec_decode_ctl.scala 231:20] - i0_dp.load <= _T_43.load @[dec_decode_ctl.scala 231:20] - i0_dp.pc <= _T_43.pc @[dec_decode_ctl.scala 231:20] - i0_dp.imm20 <= _T_43.imm20 @[dec_decode_ctl.scala 231:20] - i0_dp.shimm5 <= _T_43.shimm5 @[dec_decode_ctl.scala 231:20] - i0_dp.rd <= _T_43.rd @[dec_decode_ctl.scala 231:20] - i0_dp.imm12 <= _T_43.imm12 @[dec_decode_ctl.scala 231:20] - i0_dp.rs2 <= _T_43.rs2 @[dec_decode_ctl.scala 231:20] - i0_dp.rs1 <= _T_43.rs1 @[dec_decode_ctl.scala 231:20] - i0_dp.alu <= _T_43.alu @[dec_decode_ctl.scala 231:20] - i0_dp.alu <= UInt<1>("h01") @[dec_decode_ctl.scala 232:20] - i0_dp.rs1 <= UInt<1>("h01") @[dec_decode_ctl.scala 233:20] - i0_dp.rs2 <= UInt<1>("h01") @[dec_decode_ctl.scala 234:20] - i0_dp.lor <= UInt<1>("h01") @[dec_decode_ctl.scala 235:20] - i0_dp.legal <= UInt<1>("h01") @[dec_decode_ctl.scala 236:20] - i0_dp.postsync <= UInt<1>("h01") @[dec_decode_ctl.scala 237:20] - skip @[dec_decode_ctl.scala 230:50] - io.decode_exu.dec_i0_select_pc_d <= i0_dp.pc @[dec_decode_ctl.scala 241:36] - node _T_44 = or(i0_dp.condbr, i0_pcall) @[dec_decode_ctl.scala 244:40] - node _T_45 = or(_T_44, i0_pja) @[dec_decode_ctl.scala 244:51] - node i0_predict_br = or(_T_45, i0_pret) @[dec_decode_ctl.scala 244:60] - node _T_46 = bits(io.dec_i0_brp.bits.hist, 1, 1) @[dec_decode_ctl.scala 246:51] - node _T_47 = and(_T_46, i0_brp_valid) @[dec_decode_ctl.scala 246:55] - node _T_48 = eq(_T_47, UInt<1>("h00")) @[dec_decode_ctl.scala 246:26] - node i0_predict_nt = and(_T_48, i0_predict_br) @[dec_decode_ctl.scala 246:71] - node _T_49 = bits(io.dec_i0_brp.bits.hist, 1, 1) @[dec_decode_ctl.scala 247:51] - node _T_50 = and(_T_49, i0_brp_valid) @[dec_decode_ctl.scala 247:55] - node i0_predict_t = and(_T_50, i0_predict_br) @[dec_decode_ctl.scala 247:71] - node i0_ap_pc2 = eq(io.dec_i0_pc4_d, UInt<1>("h00")) @[dec_decode_ctl.scala 248:20] - io.decode_exu.i0_ap.predict_nt <= i0_predict_nt @[dec_decode_ctl.scala 250:37] - io.decode_exu.i0_ap.predict_t <= i0_predict_t @[dec_decode_ctl.scala 251:37] - io.decode_exu.i0_ap.add <= i0_dp.add @[dec_decode_ctl.scala 253:31] - io.decode_exu.i0_ap.sub <= i0_dp.sub @[dec_decode_ctl.scala 254:31] - io.decode_exu.i0_ap.land <= i0_dp.land @[dec_decode_ctl.scala 255:31] - io.decode_exu.i0_ap.lor <= i0_dp.lor @[dec_decode_ctl.scala 256:31] - io.decode_exu.i0_ap.lxor <= i0_dp.lxor @[dec_decode_ctl.scala 257:31] - io.decode_exu.i0_ap.sll <= i0_dp.sll @[dec_decode_ctl.scala 258:31] - io.decode_exu.i0_ap.srl <= i0_dp.srl @[dec_decode_ctl.scala 259:31] - io.decode_exu.i0_ap.sra <= i0_dp.sra @[dec_decode_ctl.scala 260:31] - io.decode_exu.i0_ap.slt <= i0_dp.slt @[dec_decode_ctl.scala 261:31] - io.decode_exu.i0_ap.unsign <= i0_dp.unsign @[dec_decode_ctl.scala 262:31] - io.decode_exu.i0_ap.beq <= i0_dp.beq @[dec_decode_ctl.scala 263:31] - io.decode_exu.i0_ap.bne <= i0_dp.bne @[dec_decode_ctl.scala 264:31] - io.decode_exu.i0_ap.blt <= i0_dp.blt @[dec_decode_ctl.scala 265:31] - io.decode_exu.i0_ap.bge <= i0_dp.bge @[dec_decode_ctl.scala 266:31] - io.decode_exu.i0_ap.csr_write <= i0_csr_write_only_d @[dec_decode_ctl.scala 267:33] - io.decode_exu.i0_ap.csr_imm <= i0_dp.csr_imm @[dec_decode_ctl.scala 268:33] - io.decode_exu.i0_ap.jal <= i0_jal @[dec_decode_ctl.scala 269:33] - node _T_51 = eq(cam[0].valid, UInt<1>("h00")) @[dec_decode_ctl.scala 273:78] - node _T_52 = bits(_T_51, 0, 0) @[dec_decode_ctl.scala 273:137] - node _T_53 = shl(cam_write, 0) @[dec_decode_ctl.scala 273:158] - node _T_54 = eq(cam[1].valid, UInt<1>("h00")) @[dec_decode_ctl.scala 273:78] - node _T_55 = bits(cam[0].valid, 0, 0) @[dec_decode_ctl.scala 273:120] - node _T_56 = bits(_T_54, 0, 0) @[dec_decode_ctl.scala 273:129] - node _T_57 = and(_T_55, _T_56) @[dec_decode_ctl.scala 273:126] - node _T_58 = bits(_T_57, 0, 0) @[dec_decode_ctl.scala 273:137] - node _T_59 = shl(cam_write, 1) @[dec_decode_ctl.scala 273:158] - node _T_60 = eq(cam[2].valid, UInt<1>("h00")) @[dec_decode_ctl.scala 273:78] - node _T_61 = bits(cam[0].valid, 0, 0) @[dec_decode_ctl.scala 273:120] - node _T_62 = bits(cam[1].valid, 0, 0) @[dec_decode_ctl.scala 273:129] - node _T_63 = and(_T_61, _T_62) @[dec_decode_ctl.scala 273:126] - node _T_64 = bits(_T_63, 0, 0) @[dec_decode_ctl.scala 273:120] - node _T_65 = bits(_T_60, 0, 0) @[dec_decode_ctl.scala 273:129] - node _T_66 = and(_T_64, _T_65) @[dec_decode_ctl.scala 273:126] - node _T_67 = bits(_T_66, 0, 0) @[dec_decode_ctl.scala 273:137] - node _T_68 = shl(cam_write, 2) @[dec_decode_ctl.scala 273:158] - node _T_69 = eq(cam[3].valid, UInt<1>("h00")) @[dec_decode_ctl.scala 273:78] - node _T_70 = bits(cam[0].valid, 0, 0) @[dec_decode_ctl.scala 273:120] - node _T_71 = bits(cam[1].valid, 0, 0) @[dec_decode_ctl.scala 273:129] - node _T_72 = and(_T_70, _T_71) @[dec_decode_ctl.scala 273:126] - node _T_73 = bits(_T_72, 0, 0) @[dec_decode_ctl.scala 273:120] - node _T_74 = bits(cam[2].valid, 0, 0) @[dec_decode_ctl.scala 273:129] - node _T_75 = and(_T_73, _T_74) @[dec_decode_ctl.scala 273:126] - node _T_76 = bits(_T_75, 0, 0) @[dec_decode_ctl.scala 273:120] - node _T_77 = bits(_T_69, 0, 0) @[dec_decode_ctl.scala 273:129] - node _T_78 = and(_T_76, _T_77) @[dec_decode_ctl.scala 273:126] - node _T_79 = bits(_T_78, 0, 0) @[dec_decode_ctl.scala 273:137] - node _T_80 = shl(cam_write, 3) @[dec_decode_ctl.scala 273:158] + node _T_18 = eq(leak1_mode, UInt<1>("h00")) @[dec_decode_ctl.scala 192:80] + node i0_brp_valid = and(io.dec_i0_brp.valid, _T_18) @[dec_decode_ctl.scala 192:78] + io.decode_exu.dec_i0_predict_p_d.bits.misp <= UInt<1>("h00") @[dec_decode_ctl.scala 193:55] + io.decode_exu.dec_i0_predict_p_d.bits.ataken <= UInt<1>("h00") @[dec_decode_ctl.scala 194:55] + io.decode_exu.dec_i0_predict_p_d.bits.boffset <= UInt<1>("h00") @[dec_decode_ctl.scala 195:55] + io.decode_exu.dec_i0_predict_p_d.bits.pcall <= i0_pcall @[dec_decode_ctl.scala 196:55] + io.decode_exu.dec_i0_predict_p_d.bits.pja <= i0_pja @[dec_decode_ctl.scala 197:55] + io.decode_exu.dec_i0_predict_p_d.bits.pret <= i0_pret @[dec_decode_ctl.scala 198:55] + io.decode_exu.dec_i0_predict_p_d.bits.prett <= io.dec_i0_brp.bits.prett @[dec_decode_ctl.scala 199:55] + io.decode_exu.dec_i0_predict_p_d.bits.pc4 <= io.dec_i0_pc4_d @[dec_decode_ctl.scala 200:55] + io.decode_exu.dec_i0_predict_p_d.bits.hist <= io.dec_i0_brp.bits.hist @[dec_decode_ctl.scala 201:55] + node _T_19 = and(i0_brp_valid, i0_legal_decode_d) @[dec_decode_ctl.scala 202:71] + io.decode_exu.dec_i0_predict_p_d.valid <= _T_19 @[dec_decode_ctl.scala 202:55] + node _T_20 = or(i0_dp_raw.condbr, i0_pcall_raw) @[dec_decode_ctl.scala 203:92] + node _T_21 = or(_T_20, i0_pja_raw) @[dec_decode_ctl.scala 203:107] + node _T_22 = or(_T_21, i0_pret_raw) @[dec_decode_ctl.scala 203:120] + node _T_23 = eq(_T_22, UInt<1>("h00")) @[dec_decode_ctl.scala 203:73] + node i0_notbr_error = and(i0_brp_valid, _T_23) @[dec_decode_ctl.scala 203:71] + node _T_24 = bits(io.dec_i0_brp.bits.hist, 1, 1) @[dec_decode_ctl.scala 206:97] + node _T_25 = and(i0_brp_valid, _T_24) @[dec_decode_ctl.scala 206:72] + node _T_26 = neq(io.dec_i0_brp.bits.toffset, i0_br_offset) @[dec_decode_ctl.scala 206:131] + node _T_27 = and(_T_25, _T_26) @[dec_decode_ctl.scala 206:101] + node _T_28 = eq(i0_pret_raw, UInt<1>("h00")) @[dec_decode_ctl.scala 206:151] + node i0_br_toffset_error = and(_T_27, _T_28) @[dec_decode_ctl.scala 206:149] + node _T_29 = and(i0_brp_valid, io.dec_i0_brp.bits.ret) @[dec_decode_ctl.scala 207:72] + node _T_30 = eq(i0_pret_raw, UInt<1>("h00")) @[dec_decode_ctl.scala 207:99] + node i0_ret_error = and(_T_29, _T_30) @[dec_decode_ctl.scala 207:97] + node _T_31 = or(io.dec_i0_brp.bits.br_error, i0_notbr_error) @[dec_decode_ctl.scala 208:87] + node _T_32 = or(_T_31, i0_br_toffset_error) @[dec_decode_ctl.scala 208:104] + node i0_br_error = or(_T_32, i0_ret_error) @[dec_decode_ctl.scala 208:126] + node _T_33 = and(i0_br_error, i0_legal_decode_d) @[dec_decode_ctl.scala 209:72] + node _T_34 = eq(leak1_mode, UInt<1>("h00")) @[dec_decode_ctl.scala 209:94] + node _T_35 = and(_T_33, _T_34) @[dec_decode_ctl.scala 209:92] + io.decode_exu.dec_i0_predict_p_d.bits.br_error <= _T_35 @[dec_decode_ctl.scala 209:56] + node _T_36 = and(io.dec_i0_brp.bits.br_start_error, i0_legal_decode_d) @[dec_decode_ctl.scala 210:94] + node _T_37 = eq(leak1_mode, UInt<1>("h00")) @[dec_decode_ctl.scala 210:116] + node _T_38 = and(_T_36, _T_37) @[dec_decode_ctl.scala 210:114] + io.decode_exu.dec_i0_predict_p_d.bits.br_start_error <= _T_38 @[dec_decode_ctl.scala 210:56] + io.decode_exu.i0_predict_index_d <= io.dec_i0_bp_index @[dec_decode_ctl.scala 211:56] + io.decode_exu.i0_predict_btag_d <= io.dec_i0_bp_btag @[dec_decode_ctl.scala 212:56] + node _T_39 = or(i0_br_error, io.dec_i0_brp.bits.br_start_error) @[dec_decode_ctl.scala 213:72] + node _T_40 = eq(leak1_mode, UInt<1>("h00")) @[dec_decode_ctl.scala 213:111] + node i0_br_error_all = and(_T_39, _T_40) @[dec_decode_ctl.scala 213:109] + io.decode_exu.dec_i0_predict_p_d.bits.toffset <= i0_br_offset @[dec_decode_ctl.scala 214:56] + io.decode_exu.i0_predict_fghr_d <= io.dec_i0_bp_fghr @[dec_decode_ctl.scala 215:56] + io.decode_exu.dec_i0_predict_p_d.bits.way <= io.dec_i0_brp.bits.way @[dec_decode_ctl.scala 216:56] + node i0_icaf_d = or(io.dec_i0_icaf_d, io.dec_i0_dbecc_d) @[dec_decode_ctl.scala 222:43] + i0_dp.legal <= i0_dp_raw.legal @[dec_decode_ctl.scala 224:23] + i0_dp.pm_alu <= i0_dp_raw.pm_alu @[dec_decode_ctl.scala 224:23] + i0_dp.fence_i <= i0_dp_raw.fence_i @[dec_decode_ctl.scala 224:23] + i0_dp.fence <= i0_dp_raw.fence @[dec_decode_ctl.scala 224:23] + i0_dp.rem <= i0_dp_raw.rem @[dec_decode_ctl.scala 224:23] + i0_dp.div <= i0_dp_raw.div @[dec_decode_ctl.scala 224:23] + i0_dp.low <= i0_dp_raw.low @[dec_decode_ctl.scala 224:23] + i0_dp.rs2_sign <= i0_dp_raw.rs2_sign @[dec_decode_ctl.scala 224:23] + i0_dp.rs1_sign <= i0_dp_raw.rs1_sign @[dec_decode_ctl.scala 224:23] + i0_dp.mul <= i0_dp_raw.mul @[dec_decode_ctl.scala 224:23] + i0_dp.mret <= i0_dp_raw.mret @[dec_decode_ctl.scala 224:23] + i0_dp.ecall <= i0_dp_raw.ecall @[dec_decode_ctl.scala 224:23] + i0_dp.ebreak <= i0_dp_raw.ebreak @[dec_decode_ctl.scala 224:23] + i0_dp.postsync <= i0_dp_raw.postsync @[dec_decode_ctl.scala 224:23] + i0_dp.presync <= i0_dp_raw.presync @[dec_decode_ctl.scala 224:23] + i0_dp.csr_imm <= i0_dp_raw.csr_imm @[dec_decode_ctl.scala 224:23] + i0_dp.csr_write <= i0_dp_raw.csr_write @[dec_decode_ctl.scala 224:23] + i0_dp.csr_set <= i0_dp_raw.csr_set @[dec_decode_ctl.scala 224:23] + i0_dp.csr_clr <= i0_dp_raw.csr_clr @[dec_decode_ctl.scala 224:23] + i0_dp.csr_read <= i0_dp_raw.csr_read @[dec_decode_ctl.scala 224:23] + i0_dp.word <= i0_dp_raw.word @[dec_decode_ctl.scala 224:23] + i0_dp.half <= i0_dp_raw.half @[dec_decode_ctl.scala 224:23] + i0_dp.by <= i0_dp_raw.by @[dec_decode_ctl.scala 224:23] + i0_dp.jal <= i0_dp_raw.jal @[dec_decode_ctl.scala 224:23] + i0_dp.blt <= i0_dp_raw.blt @[dec_decode_ctl.scala 224:23] + i0_dp.bge <= i0_dp_raw.bge @[dec_decode_ctl.scala 224:23] + i0_dp.bne <= i0_dp_raw.bne @[dec_decode_ctl.scala 224:23] + i0_dp.beq <= i0_dp_raw.beq @[dec_decode_ctl.scala 224:23] + i0_dp.condbr <= i0_dp_raw.condbr @[dec_decode_ctl.scala 224:23] + i0_dp.unsign <= i0_dp_raw.unsign @[dec_decode_ctl.scala 224:23] + i0_dp.slt <= i0_dp_raw.slt @[dec_decode_ctl.scala 224:23] + i0_dp.srl <= i0_dp_raw.srl @[dec_decode_ctl.scala 224:23] + i0_dp.sra <= i0_dp_raw.sra @[dec_decode_ctl.scala 224:23] + i0_dp.sll <= i0_dp_raw.sll @[dec_decode_ctl.scala 224:23] + i0_dp.lxor <= i0_dp_raw.lxor @[dec_decode_ctl.scala 224:23] + i0_dp.lor <= i0_dp_raw.lor @[dec_decode_ctl.scala 224:23] + i0_dp.land <= i0_dp_raw.land @[dec_decode_ctl.scala 224:23] + i0_dp.sub <= i0_dp_raw.sub @[dec_decode_ctl.scala 224:23] + i0_dp.add <= i0_dp_raw.add @[dec_decode_ctl.scala 224:23] + i0_dp.lsu <= i0_dp_raw.lsu @[dec_decode_ctl.scala 224:23] + i0_dp.store <= i0_dp_raw.store @[dec_decode_ctl.scala 224:23] + i0_dp.load <= i0_dp_raw.load @[dec_decode_ctl.scala 224:23] + i0_dp.pc <= i0_dp_raw.pc @[dec_decode_ctl.scala 224:23] + i0_dp.imm20 <= i0_dp_raw.imm20 @[dec_decode_ctl.scala 224:23] + i0_dp.shimm5 <= i0_dp_raw.shimm5 @[dec_decode_ctl.scala 224:23] + i0_dp.rd <= i0_dp_raw.rd @[dec_decode_ctl.scala 224:23] + i0_dp.imm12 <= i0_dp_raw.imm12 @[dec_decode_ctl.scala 224:23] + i0_dp.rs2 <= i0_dp_raw.rs2 @[dec_decode_ctl.scala 224:23] + i0_dp.rs1 <= i0_dp_raw.rs1 @[dec_decode_ctl.scala 224:23] + i0_dp.alu <= i0_dp_raw.alu @[dec_decode_ctl.scala 224:23] + node _T_41 = or(i0_br_error_all, i0_icaf_d) @[dec_decode_ctl.scala 225:25] + node _T_42 = bits(_T_41, 0, 0) @[dec_decode_ctl.scala 225:43] + when _T_42 : @[dec_decode_ctl.scala 225:50] + wire _T_43 : {alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>} @[dec_decode_ctl.scala 226:38] + _T_43.legal <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] + _T_43.pm_alu <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] + _T_43.fence_i <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] + _T_43.fence <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] + _T_43.rem <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] + _T_43.div <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] + _T_43.low <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] + _T_43.rs2_sign <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] + _T_43.rs1_sign <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] + _T_43.mul <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] + _T_43.mret <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] + _T_43.ecall <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] + _T_43.ebreak <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] + _T_43.postsync <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] + _T_43.presync <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] + _T_43.csr_imm <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] + _T_43.csr_write <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] + _T_43.csr_set <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] + _T_43.csr_clr <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] + _T_43.csr_read <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] + _T_43.word <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] + _T_43.half <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] + _T_43.by <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] + _T_43.jal <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] + _T_43.blt <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] + _T_43.bge <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] + _T_43.bne <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] + _T_43.beq <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] + _T_43.condbr <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] + _T_43.unsign <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] + _T_43.slt <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] + _T_43.srl <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] + _T_43.sra <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] + _T_43.sll <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] + _T_43.lxor <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] + _T_43.lor <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] + _T_43.land <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] + _T_43.sub <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] + _T_43.add <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] + _T_43.lsu <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] + _T_43.store <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] + _T_43.load <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] + _T_43.pc <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] + _T_43.imm20 <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] + _T_43.shimm5 <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] + _T_43.rd <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] + _T_43.imm12 <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] + _T_43.rs2 <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] + _T_43.rs1 <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] + _T_43.alu <= UInt<1>("h00") @[dec_decode_ctl.scala 226:38] + i0_dp.legal <= _T_43.legal @[dec_decode_ctl.scala 226:23] + i0_dp.pm_alu <= _T_43.pm_alu @[dec_decode_ctl.scala 226:23] + i0_dp.fence_i <= _T_43.fence_i @[dec_decode_ctl.scala 226:23] + i0_dp.fence <= _T_43.fence @[dec_decode_ctl.scala 226:23] + i0_dp.rem <= _T_43.rem @[dec_decode_ctl.scala 226:23] + i0_dp.div <= _T_43.div @[dec_decode_ctl.scala 226:23] + i0_dp.low <= _T_43.low @[dec_decode_ctl.scala 226:23] + i0_dp.rs2_sign <= _T_43.rs2_sign @[dec_decode_ctl.scala 226:23] + i0_dp.rs1_sign <= _T_43.rs1_sign @[dec_decode_ctl.scala 226:23] + i0_dp.mul <= _T_43.mul @[dec_decode_ctl.scala 226:23] + i0_dp.mret <= _T_43.mret @[dec_decode_ctl.scala 226:23] + i0_dp.ecall <= _T_43.ecall @[dec_decode_ctl.scala 226:23] + i0_dp.ebreak <= _T_43.ebreak @[dec_decode_ctl.scala 226:23] + i0_dp.postsync <= _T_43.postsync @[dec_decode_ctl.scala 226:23] + i0_dp.presync <= _T_43.presync @[dec_decode_ctl.scala 226:23] + i0_dp.csr_imm <= _T_43.csr_imm @[dec_decode_ctl.scala 226:23] + i0_dp.csr_write <= _T_43.csr_write @[dec_decode_ctl.scala 226:23] + i0_dp.csr_set <= _T_43.csr_set @[dec_decode_ctl.scala 226:23] + i0_dp.csr_clr <= _T_43.csr_clr @[dec_decode_ctl.scala 226:23] + i0_dp.csr_read <= _T_43.csr_read @[dec_decode_ctl.scala 226:23] + i0_dp.word <= _T_43.word @[dec_decode_ctl.scala 226:23] + i0_dp.half <= _T_43.half @[dec_decode_ctl.scala 226:23] + i0_dp.by <= _T_43.by @[dec_decode_ctl.scala 226:23] + i0_dp.jal <= _T_43.jal @[dec_decode_ctl.scala 226:23] + i0_dp.blt <= _T_43.blt @[dec_decode_ctl.scala 226:23] + i0_dp.bge <= _T_43.bge @[dec_decode_ctl.scala 226:23] + i0_dp.bne <= _T_43.bne @[dec_decode_ctl.scala 226:23] + i0_dp.beq <= _T_43.beq @[dec_decode_ctl.scala 226:23] + i0_dp.condbr <= _T_43.condbr @[dec_decode_ctl.scala 226:23] + i0_dp.unsign <= _T_43.unsign @[dec_decode_ctl.scala 226:23] + i0_dp.slt <= _T_43.slt @[dec_decode_ctl.scala 226:23] + i0_dp.srl <= _T_43.srl @[dec_decode_ctl.scala 226:23] + i0_dp.sra <= _T_43.sra @[dec_decode_ctl.scala 226:23] + i0_dp.sll <= _T_43.sll @[dec_decode_ctl.scala 226:23] + i0_dp.lxor <= _T_43.lxor @[dec_decode_ctl.scala 226:23] + i0_dp.lor <= _T_43.lor @[dec_decode_ctl.scala 226:23] + i0_dp.land <= _T_43.land @[dec_decode_ctl.scala 226:23] + i0_dp.sub <= _T_43.sub @[dec_decode_ctl.scala 226:23] + i0_dp.add <= _T_43.add @[dec_decode_ctl.scala 226:23] + i0_dp.lsu <= _T_43.lsu @[dec_decode_ctl.scala 226:23] + i0_dp.store <= _T_43.store @[dec_decode_ctl.scala 226:23] + i0_dp.load <= _T_43.load @[dec_decode_ctl.scala 226:23] + i0_dp.pc <= _T_43.pc @[dec_decode_ctl.scala 226:23] + i0_dp.imm20 <= _T_43.imm20 @[dec_decode_ctl.scala 226:23] + i0_dp.shimm5 <= _T_43.shimm5 @[dec_decode_ctl.scala 226:23] + i0_dp.rd <= _T_43.rd @[dec_decode_ctl.scala 226:23] + i0_dp.imm12 <= _T_43.imm12 @[dec_decode_ctl.scala 226:23] + i0_dp.rs2 <= _T_43.rs2 @[dec_decode_ctl.scala 226:23] + i0_dp.rs1 <= _T_43.rs1 @[dec_decode_ctl.scala 226:23] + i0_dp.alu <= _T_43.alu @[dec_decode_ctl.scala 226:23] + i0_dp.alu <= UInt<1>("h01") @[dec_decode_ctl.scala 227:23] + i0_dp.rs1 <= UInt<1>("h01") @[dec_decode_ctl.scala 228:23] + i0_dp.rs2 <= UInt<1>("h01") @[dec_decode_ctl.scala 229:23] + i0_dp.lor <= UInt<1>("h01") @[dec_decode_ctl.scala 230:23] + i0_dp.legal <= UInt<1>("h01") @[dec_decode_ctl.scala 231:23] + i0_dp.postsync <= UInt<1>("h01") @[dec_decode_ctl.scala 232:23] + skip @[dec_decode_ctl.scala 225:50] + io.decode_exu.dec_i0_select_pc_d <= i0_dp.pc @[dec_decode_ctl.scala 236:36] + node _T_44 = or(i0_dp.condbr, i0_pcall) @[dec_decode_ctl.scala 239:54] + node _T_45 = or(_T_44, i0_pja) @[dec_decode_ctl.scala 239:65] + node i0_predict_br = or(_T_45, i0_pret) @[dec_decode_ctl.scala 239:74] + node _T_46 = bits(io.dec_i0_brp.bits.hist, 1, 1) @[dec_decode_ctl.scala 240:65] + node _T_47 = and(_T_46, i0_brp_valid) @[dec_decode_ctl.scala 240:69] + node _T_48 = eq(_T_47, UInt<1>("h00")) @[dec_decode_ctl.scala 240:40] + node i0_predict_nt = and(_T_48, i0_predict_br) @[dec_decode_ctl.scala 240:85] + node _T_49 = bits(io.dec_i0_brp.bits.hist, 1, 1) @[dec_decode_ctl.scala 241:65] + node _T_50 = and(_T_49, i0_brp_valid) @[dec_decode_ctl.scala 241:69] + node i0_predict_t = and(_T_50, i0_predict_br) @[dec_decode_ctl.scala 241:85] + node i0_ap_pc2 = eq(io.dec_i0_pc4_d, UInt<1>("h00")) @[dec_decode_ctl.scala 242:40] + io.decode_exu.i0_ap.predict_nt <= i0_predict_nt @[dec_decode_ctl.scala 244:37] + io.decode_exu.i0_ap.predict_t <= i0_predict_t @[dec_decode_ctl.scala 245:37] + io.decode_exu.i0_ap.add <= i0_dp.add @[dec_decode_ctl.scala 247:37] + io.decode_exu.i0_ap.sub <= i0_dp.sub @[dec_decode_ctl.scala 248:37] + io.decode_exu.i0_ap.land <= i0_dp.land @[dec_decode_ctl.scala 249:37] + io.decode_exu.i0_ap.lor <= i0_dp.lor @[dec_decode_ctl.scala 250:37] + io.decode_exu.i0_ap.lxor <= i0_dp.lxor @[dec_decode_ctl.scala 251:37] + io.decode_exu.i0_ap.sll <= i0_dp.sll @[dec_decode_ctl.scala 252:37] + io.decode_exu.i0_ap.srl <= i0_dp.srl @[dec_decode_ctl.scala 253:37] + io.decode_exu.i0_ap.sra <= i0_dp.sra @[dec_decode_ctl.scala 254:37] + io.decode_exu.i0_ap.slt <= i0_dp.slt @[dec_decode_ctl.scala 255:37] + io.decode_exu.i0_ap.unsign <= i0_dp.unsign @[dec_decode_ctl.scala 256:37] + io.decode_exu.i0_ap.beq <= i0_dp.beq @[dec_decode_ctl.scala 257:37] + io.decode_exu.i0_ap.bne <= i0_dp.bne @[dec_decode_ctl.scala 258:37] + io.decode_exu.i0_ap.blt <= i0_dp.blt @[dec_decode_ctl.scala 259:37] + io.decode_exu.i0_ap.bge <= i0_dp.bge @[dec_decode_ctl.scala 260:37] + io.decode_exu.i0_ap.csr_write <= i0_csr_write_only_d @[dec_decode_ctl.scala 261:37] + io.decode_exu.i0_ap.csr_imm <= i0_dp.csr_imm @[dec_decode_ctl.scala 262:37] + io.decode_exu.i0_ap.jal <= i0_jal @[dec_decode_ctl.scala 263:37] + node _T_51 = eq(cam[0].valid, UInt<1>("h00")) @[dec_decode_ctl.scala 267:78] + node _T_52 = bits(_T_51, 0, 0) @[dec_decode_ctl.scala 267:137] + node _T_53 = shl(cam_write, 0) @[dec_decode_ctl.scala 267:158] + node _T_54 = eq(cam[1].valid, UInt<1>("h00")) @[dec_decode_ctl.scala 267:78] + node _T_55 = bits(cam[0].valid, 0, 0) @[dec_decode_ctl.scala 267:120] + node _T_56 = bits(_T_54, 0, 0) @[dec_decode_ctl.scala 267:129] + node _T_57 = and(_T_55, _T_56) @[dec_decode_ctl.scala 267:126] + node _T_58 = bits(_T_57, 0, 0) @[dec_decode_ctl.scala 267:137] + node _T_59 = shl(cam_write, 1) @[dec_decode_ctl.scala 267:158] + node _T_60 = eq(cam[2].valid, UInt<1>("h00")) @[dec_decode_ctl.scala 267:78] + node _T_61 = bits(cam[0].valid, 0, 0) @[dec_decode_ctl.scala 267:120] + node _T_62 = bits(cam[1].valid, 0, 0) @[dec_decode_ctl.scala 267:129] + node _T_63 = and(_T_61, _T_62) @[dec_decode_ctl.scala 267:126] + node _T_64 = bits(_T_63, 0, 0) @[dec_decode_ctl.scala 267:120] + node _T_65 = bits(_T_60, 0, 0) @[dec_decode_ctl.scala 267:129] + node _T_66 = and(_T_64, _T_65) @[dec_decode_ctl.scala 267:126] + node _T_67 = bits(_T_66, 0, 0) @[dec_decode_ctl.scala 267:137] + node _T_68 = shl(cam_write, 2) @[dec_decode_ctl.scala 267:158] + node _T_69 = eq(cam[3].valid, UInt<1>("h00")) @[dec_decode_ctl.scala 267:78] + node _T_70 = bits(cam[0].valid, 0, 0) @[dec_decode_ctl.scala 267:120] + node _T_71 = bits(cam[1].valid, 0, 0) @[dec_decode_ctl.scala 267:129] + node _T_72 = and(_T_70, _T_71) @[dec_decode_ctl.scala 267:126] + node _T_73 = bits(_T_72, 0, 0) @[dec_decode_ctl.scala 267:120] + node _T_74 = bits(cam[2].valid, 0, 0) @[dec_decode_ctl.scala 267:129] + node _T_75 = and(_T_73, _T_74) @[dec_decode_ctl.scala 267:126] + node _T_76 = bits(_T_75, 0, 0) @[dec_decode_ctl.scala 267:120] + node _T_77 = bits(_T_69, 0, 0) @[dec_decode_ctl.scala 267:129] + node _T_78 = and(_T_76, _T_77) @[dec_decode_ctl.scala 267:126] + node _T_79 = bits(_T_78, 0, 0) @[dec_decode_ctl.scala 267:137] + node _T_80 = shl(cam_write, 3) @[dec_decode_ctl.scala 267:158] node _T_81 = mux(_T_52, _T_53, UInt<1>("h00")) @[Mux.scala 27:72] node _T_82 = mux(_T_58, _T_59, UInt<1>("h00")) @[Mux.scala 27:72] node _T_83 = mux(_T_67, _T_68, UInt<1>("h00")) @[Mux.scala 27:72] @@ -67307,410 +67307,410 @@ circuit quasar_wrapper : node _T_87 = or(_T_86, _T_84) @[Mux.scala 27:72] wire _T_88 : UInt<4> @[Mux.scala 27:72] _T_88 <= _T_87 @[Mux.scala 27:72] - cam_wen <= _T_88 @[dec_decode_ctl.scala 273:11] - cam_write <= io.dctl_busbuff.lsu_nonblock_load_valid_m @[dec_decode_ctl.scala 275:25] - node cam_write_tag = bits(io.dctl_busbuff.lsu_nonblock_load_tag_m, 1, 0) @[dec_decode_ctl.scala 276:67] - node cam_data_reset = or(io.dctl_busbuff.lsu_nonblock_load_data_valid, io.dctl_busbuff.lsu_nonblock_load_data_error) @[dec_decode_ctl.scala 281:76] - node _T_89 = bits(x_d.bits.i0load, 0, 0) @[dec_decode_ctl.scala 284:48] - node nonblock_load_rd = mux(_T_89, x_d.bits.i0rd, UInt<5>("h00")) @[dec_decode_ctl.scala 284:31] - node _T_90 = bits(i0_r_ctl_en, 0, 0) @[dec_decode_ctl.scala 288:129] + cam_wen <= _T_88 @[dec_decode_ctl.scala 267:11] + cam_write <= io.dctl_busbuff.lsu_nonblock_load_valid_m @[dec_decode_ctl.scala 269:25] + node cam_write_tag = bits(io.dctl_busbuff.lsu_nonblock_load_tag_m, 1, 0) @[dec_decode_ctl.scala 270:67] + node cam_data_reset = or(io.dctl_busbuff.lsu_nonblock_load_data_valid, io.dctl_busbuff.lsu_nonblock_load_data_error) @[dec_decode_ctl.scala 275:76] + node _T_89 = bits(x_d.bits.i0load, 0, 0) @[dec_decode_ctl.scala 278:48] + node nonblock_load_rd = mux(_T_89, x_d.bits.i0rd, UInt<5>("h00")) @[dec_decode_ctl.scala 278:31] + node _T_90 = bits(i0_r_ctl_en, 0, 0) @[dec_decode_ctl.scala 282:129] reg nonblock_load_valid_m_delay : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_90 : @[Reg.scala 28:19] nonblock_load_valid_m_delay <= io.dctl_busbuff.lsu_nonblock_load_valid_m @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node i0_load_kill_wen_r = and(nonblock_load_valid_m_delay, r_d.bits.i0load) @[dec_decode_ctl.scala 289:56] - node _T_91 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[0].bits.tag) @[dec_decode_ctl.scala 291:66] - node _T_92 = and(io.dctl_busbuff.lsu_nonblock_load_inv_r, _T_91) @[dec_decode_ctl.scala 291:45] - node _T_93 = and(_T_92, cam[0].valid) @[dec_decode_ctl.scala 291:87] - cam_inv_reset_val[0] <= _T_93 @[dec_decode_ctl.scala 291:26] - node _T_94 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam[0].bits.tag) @[dec_decode_ctl.scala 292:67] - node _T_95 = and(cam_data_reset, _T_94) @[dec_decode_ctl.scala 292:45] - node _T_96 = and(_T_95, cam_raw[0].valid) @[dec_decode_ctl.scala 292:88] - cam_data_reset_val[0] <= _T_96 @[dec_decode_ctl.scala 292:27] - wire _T_97 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[dec_decode_ctl.scala 293:28] - _T_97.bits.rd <= UInt<5>("h00") @[dec_decode_ctl.scala 293:28] - _T_97.bits.tag <= UInt<3>("h00") @[dec_decode_ctl.scala 293:28] - _T_97.bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 293:28] - _T_97.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 293:28] - cam_in[0].bits.rd <= _T_97.bits.rd @[dec_decode_ctl.scala 293:14] - cam_in[0].bits.tag <= _T_97.bits.tag @[dec_decode_ctl.scala 293:14] - cam_in[0].bits.wb <= _T_97.bits.wb @[dec_decode_ctl.scala 293:14] - cam_in[0].valid <= _T_97.valid @[dec_decode_ctl.scala 293:14] - cam[0].bits.rd <= cam_raw[0].bits.rd @[dec_decode_ctl.scala 294:11] - cam[0].bits.tag <= cam_raw[0].bits.tag @[dec_decode_ctl.scala 294:11] - cam[0].bits.wb <= cam_raw[0].bits.wb @[dec_decode_ctl.scala 294:11] - cam[0].valid <= cam_raw[0].valid @[dec_decode_ctl.scala 294:11] - node _T_98 = bits(cam_data_reset_val[0], 0, 0) @[dec_decode_ctl.scala 296:32] - when _T_98 : @[dec_decode_ctl.scala 296:39] - cam[0].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 297:20] - skip @[dec_decode_ctl.scala 296:39] - node _T_99 = bits(cam_wen, 0, 0) @[dec_decode_ctl.scala 299:17] - node _T_100 = bits(_T_99, 0, 0) @[dec_decode_ctl.scala 299:21] - when _T_100 : @[dec_decode_ctl.scala 299:28] - cam_in[0].valid <= UInt<1>("h01") @[dec_decode_ctl.scala 300:27] - cam_in[0].bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 301:32] - cam_in[0].bits.tag <= cam_write_tag @[dec_decode_ctl.scala 302:32] - cam_in[0].bits.rd <= nonblock_load_rd @[dec_decode_ctl.scala 303:32] - skip @[dec_decode_ctl.scala 299:28] - else : @[dec_decode_ctl.scala 304:131] - node _T_101 = bits(cam_inv_reset_val[0], 0, 0) @[dec_decode_ctl.scala 304:37] - node _T_102 = bits(i0_wen_r, 0, 0) @[dec_decode_ctl.scala 304:57] - node _T_103 = eq(r_d_in.bits.i0rd, cam[0].bits.rd) @[dec_decode_ctl.scala 304:85] - node _T_104 = and(_T_102, _T_103) @[dec_decode_ctl.scala 304:64] - node _T_105 = bits(cam[0].bits.wb, 0, 0) @[dec_decode_ctl.scala 304:123] - node _T_106 = and(_T_104, _T_105) @[dec_decode_ctl.scala 304:105] - node _T_107 = or(_T_101, _T_106) @[dec_decode_ctl.scala 304:44] - when _T_107 : @[dec_decode_ctl.scala 304:131] - cam_in[0].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 305:23] - skip @[dec_decode_ctl.scala 304:131] - else : @[dec_decode_ctl.scala 306:16] - cam_in[0].bits.rd <= cam[0].bits.rd @[dec_decode_ctl.scala 307:22] - cam_in[0].bits.tag <= cam[0].bits.tag @[dec_decode_ctl.scala 307:22] - cam_in[0].bits.wb <= cam[0].bits.wb @[dec_decode_ctl.scala 307:22] - cam_in[0].valid <= cam[0].valid @[dec_decode_ctl.scala 307:22] - skip @[dec_decode_ctl.scala 306:16] - node _T_108 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[dec_decode_ctl.scala 309:37] - node _T_109 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[0].bits.tag) @[dec_decode_ctl.scala 309:92] - node _T_110 = and(_T_108, _T_109) @[dec_decode_ctl.scala 309:44] - node _T_111 = eq(cam[0].valid, UInt<1>("h01")) @[dec_decode_ctl.scala 309:128] - node _T_112 = and(_T_110, _T_111) @[dec_decode_ctl.scala 309:113] - when _T_112 : @[dec_decode_ctl.scala 309:135] - cam_in[0].bits.wb <= UInt<1>("h01") @[dec_decode_ctl.scala 310:25] - skip @[dec_decode_ctl.scala 309:135] - when io.dec_tlu_force_halt : @[dec_decode_ctl.scala 313:32] - cam_in[0].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 314:23] - skip @[dec_decode_ctl.scala 313:32] - wire _T_113 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[dec_decode_ctl.scala 317:70] - _T_113.bits.rd <= UInt<5>("h00") @[dec_decode_ctl.scala 317:70] - _T_113.bits.tag <= UInt<3>("h00") @[dec_decode_ctl.scala 317:70] - _T_113.bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 317:70] - _T_113.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 317:70] - reg _T_114 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}, io.free_clk with : (reset => (reset, _T_113)) @[dec_decode_ctl.scala 317:47] - _T_114.bits.rd <= cam_in[0].bits.rd @[dec_decode_ctl.scala 317:47] - _T_114.bits.tag <= cam_in[0].bits.tag @[dec_decode_ctl.scala 317:47] - _T_114.bits.wb <= cam_in[0].bits.wb @[dec_decode_ctl.scala 317:47] - _T_114.valid <= cam_in[0].valid @[dec_decode_ctl.scala 317:47] - cam_raw[0].bits.rd <= _T_114.bits.rd @[dec_decode_ctl.scala 317:15] - cam_raw[0].bits.tag <= _T_114.bits.tag @[dec_decode_ctl.scala 317:15] - cam_raw[0].bits.wb <= _T_114.bits.wb @[dec_decode_ctl.scala 317:15] - cam_raw[0].valid <= _T_114.valid @[dec_decode_ctl.scala 317:15] - node _T_115 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam_raw[0].bits.tag) @[dec_decode_ctl.scala 318:46] - node _T_116 = and(_T_115, cam_raw[0].valid) @[dec_decode_ctl.scala 318:71] - nonblock_load_write[0] <= _T_116 @[dec_decode_ctl.scala 318:28] - node _T_117 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[1].bits.tag) @[dec_decode_ctl.scala 291:66] - node _T_118 = and(io.dctl_busbuff.lsu_nonblock_load_inv_r, _T_117) @[dec_decode_ctl.scala 291:45] - node _T_119 = and(_T_118, cam[1].valid) @[dec_decode_ctl.scala 291:87] - cam_inv_reset_val[1] <= _T_119 @[dec_decode_ctl.scala 291:26] - node _T_120 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam[1].bits.tag) @[dec_decode_ctl.scala 292:67] - node _T_121 = and(cam_data_reset, _T_120) @[dec_decode_ctl.scala 292:45] - node _T_122 = and(_T_121, cam_raw[1].valid) @[dec_decode_ctl.scala 292:88] - cam_data_reset_val[1] <= _T_122 @[dec_decode_ctl.scala 292:27] - wire _T_123 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[dec_decode_ctl.scala 293:28] - _T_123.bits.rd <= UInt<5>("h00") @[dec_decode_ctl.scala 293:28] - _T_123.bits.tag <= UInt<3>("h00") @[dec_decode_ctl.scala 293:28] - _T_123.bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 293:28] - _T_123.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 293:28] - cam_in[1].bits.rd <= _T_123.bits.rd @[dec_decode_ctl.scala 293:14] - cam_in[1].bits.tag <= _T_123.bits.tag @[dec_decode_ctl.scala 293:14] - cam_in[1].bits.wb <= _T_123.bits.wb @[dec_decode_ctl.scala 293:14] - cam_in[1].valid <= _T_123.valid @[dec_decode_ctl.scala 293:14] - cam[1].bits.rd <= cam_raw[1].bits.rd @[dec_decode_ctl.scala 294:11] - cam[1].bits.tag <= cam_raw[1].bits.tag @[dec_decode_ctl.scala 294:11] - cam[1].bits.wb <= cam_raw[1].bits.wb @[dec_decode_ctl.scala 294:11] - cam[1].valid <= cam_raw[1].valid @[dec_decode_ctl.scala 294:11] - node _T_124 = bits(cam_data_reset_val[1], 0, 0) @[dec_decode_ctl.scala 296:32] - when _T_124 : @[dec_decode_ctl.scala 296:39] - cam[1].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 297:20] - skip @[dec_decode_ctl.scala 296:39] - node _T_125 = bits(cam_wen, 1, 1) @[dec_decode_ctl.scala 299:17] - node _T_126 = bits(_T_125, 0, 0) @[dec_decode_ctl.scala 299:21] - when _T_126 : @[dec_decode_ctl.scala 299:28] - cam_in[1].valid <= UInt<1>("h01") @[dec_decode_ctl.scala 300:27] - cam_in[1].bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 301:32] - cam_in[1].bits.tag <= cam_write_tag @[dec_decode_ctl.scala 302:32] - cam_in[1].bits.rd <= nonblock_load_rd @[dec_decode_ctl.scala 303:32] - skip @[dec_decode_ctl.scala 299:28] - else : @[dec_decode_ctl.scala 304:131] - node _T_127 = bits(cam_inv_reset_val[1], 0, 0) @[dec_decode_ctl.scala 304:37] - node _T_128 = bits(i0_wen_r, 0, 0) @[dec_decode_ctl.scala 304:57] - node _T_129 = eq(r_d_in.bits.i0rd, cam[1].bits.rd) @[dec_decode_ctl.scala 304:85] - node _T_130 = and(_T_128, _T_129) @[dec_decode_ctl.scala 304:64] - node _T_131 = bits(cam[1].bits.wb, 0, 0) @[dec_decode_ctl.scala 304:123] - node _T_132 = and(_T_130, _T_131) @[dec_decode_ctl.scala 304:105] - node _T_133 = or(_T_127, _T_132) @[dec_decode_ctl.scala 304:44] - when _T_133 : @[dec_decode_ctl.scala 304:131] - cam_in[1].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 305:23] - skip @[dec_decode_ctl.scala 304:131] - else : @[dec_decode_ctl.scala 306:16] - cam_in[1].bits.rd <= cam[1].bits.rd @[dec_decode_ctl.scala 307:22] - cam_in[1].bits.tag <= cam[1].bits.tag @[dec_decode_ctl.scala 307:22] - cam_in[1].bits.wb <= cam[1].bits.wb @[dec_decode_ctl.scala 307:22] - cam_in[1].valid <= cam[1].valid @[dec_decode_ctl.scala 307:22] - skip @[dec_decode_ctl.scala 306:16] - node _T_134 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[dec_decode_ctl.scala 309:37] - node _T_135 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[1].bits.tag) @[dec_decode_ctl.scala 309:92] - node _T_136 = and(_T_134, _T_135) @[dec_decode_ctl.scala 309:44] - node _T_137 = eq(cam[1].valid, UInt<1>("h01")) @[dec_decode_ctl.scala 309:128] - node _T_138 = and(_T_136, _T_137) @[dec_decode_ctl.scala 309:113] - when _T_138 : @[dec_decode_ctl.scala 309:135] - cam_in[1].bits.wb <= UInt<1>("h01") @[dec_decode_ctl.scala 310:25] - skip @[dec_decode_ctl.scala 309:135] - when io.dec_tlu_force_halt : @[dec_decode_ctl.scala 313:32] - cam_in[1].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 314:23] - skip @[dec_decode_ctl.scala 313:32] - wire _T_139 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[dec_decode_ctl.scala 317:70] - _T_139.bits.rd <= UInt<5>("h00") @[dec_decode_ctl.scala 317:70] - _T_139.bits.tag <= UInt<3>("h00") @[dec_decode_ctl.scala 317:70] - _T_139.bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 317:70] - _T_139.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 317:70] - reg _T_140 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}, io.free_clk with : (reset => (reset, _T_139)) @[dec_decode_ctl.scala 317:47] - _T_140.bits.rd <= cam_in[1].bits.rd @[dec_decode_ctl.scala 317:47] - _T_140.bits.tag <= cam_in[1].bits.tag @[dec_decode_ctl.scala 317:47] - _T_140.bits.wb <= cam_in[1].bits.wb @[dec_decode_ctl.scala 317:47] - _T_140.valid <= cam_in[1].valid @[dec_decode_ctl.scala 317:47] - cam_raw[1].bits.rd <= _T_140.bits.rd @[dec_decode_ctl.scala 317:15] - cam_raw[1].bits.tag <= _T_140.bits.tag @[dec_decode_ctl.scala 317:15] - cam_raw[1].bits.wb <= _T_140.bits.wb @[dec_decode_ctl.scala 317:15] - cam_raw[1].valid <= _T_140.valid @[dec_decode_ctl.scala 317:15] - node _T_141 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam_raw[1].bits.tag) @[dec_decode_ctl.scala 318:46] - node _T_142 = and(_T_141, cam_raw[1].valid) @[dec_decode_ctl.scala 318:71] - nonblock_load_write[1] <= _T_142 @[dec_decode_ctl.scala 318:28] - node _T_143 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[2].bits.tag) @[dec_decode_ctl.scala 291:66] - node _T_144 = and(io.dctl_busbuff.lsu_nonblock_load_inv_r, _T_143) @[dec_decode_ctl.scala 291:45] - node _T_145 = and(_T_144, cam[2].valid) @[dec_decode_ctl.scala 291:87] - cam_inv_reset_val[2] <= _T_145 @[dec_decode_ctl.scala 291:26] - node _T_146 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam[2].bits.tag) @[dec_decode_ctl.scala 292:67] - node _T_147 = and(cam_data_reset, _T_146) @[dec_decode_ctl.scala 292:45] - node _T_148 = and(_T_147, cam_raw[2].valid) @[dec_decode_ctl.scala 292:88] - cam_data_reset_val[2] <= _T_148 @[dec_decode_ctl.scala 292:27] - wire _T_149 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[dec_decode_ctl.scala 293:28] - _T_149.bits.rd <= UInt<5>("h00") @[dec_decode_ctl.scala 293:28] - _T_149.bits.tag <= UInt<3>("h00") @[dec_decode_ctl.scala 293:28] - _T_149.bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 293:28] - _T_149.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 293:28] - cam_in[2].bits.rd <= _T_149.bits.rd @[dec_decode_ctl.scala 293:14] - cam_in[2].bits.tag <= _T_149.bits.tag @[dec_decode_ctl.scala 293:14] - cam_in[2].bits.wb <= _T_149.bits.wb @[dec_decode_ctl.scala 293:14] - cam_in[2].valid <= _T_149.valid @[dec_decode_ctl.scala 293:14] - cam[2].bits.rd <= cam_raw[2].bits.rd @[dec_decode_ctl.scala 294:11] - cam[2].bits.tag <= cam_raw[2].bits.tag @[dec_decode_ctl.scala 294:11] - cam[2].bits.wb <= cam_raw[2].bits.wb @[dec_decode_ctl.scala 294:11] - cam[2].valid <= cam_raw[2].valid @[dec_decode_ctl.scala 294:11] - node _T_150 = bits(cam_data_reset_val[2], 0, 0) @[dec_decode_ctl.scala 296:32] - when _T_150 : @[dec_decode_ctl.scala 296:39] - cam[2].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 297:20] - skip @[dec_decode_ctl.scala 296:39] - node _T_151 = bits(cam_wen, 2, 2) @[dec_decode_ctl.scala 299:17] - node _T_152 = bits(_T_151, 0, 0) @[dec_decode_ctl.scala 299:21] - when _T_152 : @[dec_decode_ctl.scala 299:28] - cam_in[2].valid <= UInt<1>("h01") @[dec_decode_ctl.scala 300:27] - cam_in[2].bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 301:32] - cam_in[2].bits.tag <= cam_write_tag @[dec_decode_ctl.scala 302:32] - cam_in[2].bits.rd <= nonblock_load_rd @[dec_decode_ctl.scala 303:32] - skip @[dec_decode_ctl.scala 299:28] - else : @[dec_decode_ctl.scala 304:131] - node _T_153 = bits(cam_inv_reset_val[2], 0, 0) @[dec_decode_ctl.scala 304:37] - node _T_154 = bits(i0_wen_r, 0, 0) @[dec_decode_ctl.scala 304:57] - node _T_155 = eq(r_d_in.bits.i0rd, cam[2].bits.rd) @[dec_decode_ctl.scala 304:85] - node _T_156 = and(_T_154, _T_155) @[dec_decode_ctl.scala 304:64] - node _T_157 = bits(cam[2].bits.wb, 0, 0) @[dec_decode_ctl.scala 304:123] - node _T_158 = and(_T_156, _T_157) @[dec_decode_ctl.scala 304:105] - node _T_159 = or(_T_153, _T_158) @[dec_decode_ctl.scala 304:44] - when _T_159 : @[dec_decode_ctl.scala 304:131] - cam_in[2].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 305:23] - skip @[dec_decode_ctl.scala 304:131] - else : @[dec_decode_ctl.scala 306:16] - cam_in[2].bits.rd <= cam[2].bits.rd @[dec_decode_ctl.scala 307:22] - cam_in[2].bits.tag <= cam[2].bits.tag @[dec_decode_ctl.scala 307:22] - cam_in[2].bits.wb <= cam[2].bits.wb @[dec_decode_ctl.scala 307:22] - cam_in[2].valid <= cam[2].valid @[dec_decode_ctl.scala 307:22] - skip @[dec_decode_ctl.scala 306:16] - node _T_160 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[dec_decode_ctl.scala 309:37] - node _T_161 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[2].bits.tag) @[dec_decode_ctl.scala 309:92] - node _T_162 = and(_T_160, _T_161) @[dec_decode_ctl.scala 309:44] - node _T_163 = eq(cam[2].valid, UInt<1>("h01")) @[dec_decode_ctl.scala 309:128] - node _T_164 = and(_T_162, _T_163) @[dec_decode_ctl.scala 309:113] - when _T_164 : @[dec_decode_ctl.scala 309:135] - cam_in[2].bits.wb <= UInt<1>("h01") @[dec_decode_ctl.scala 310:25] - skip @[dec_decode_ctl.scala 309:135] - when io.dec_tlu_force_halt : @[dec_decode_ctl.scala 313:32] - cam_in[2].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 314:23] - skip @[dec_decode_ctl.scala 313:32] - wire _T_165 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[dec_decode_ctl.scala 317:70] - _T_165.bits.rd <= UInt<5>("h00") @[dec_decode_ctl.scala 317:70] - _T_165.bits.tag <= UInt<3>("h00") @[dec_decode_ctl.scala 317:70] - _T_165.bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 317:70] - _T_165.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 317:70] - reg _T_166 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}, io.free_clk with : (reset => (reset, _T_165)) @[dec_decode_ctl.scala 317:47] - _T_166.bits.rd <= cam_in[2].bits.rd @[dec_decode_ctl.scala 317:47] - _T_166.bits.tag <= cam_in[2].bits.tag @[dec_decode_ctl.scala 317:47] - _T_166.bits.wb <= cam_in[2].bits.wb @[dec_decode_ctl.scala 317:47] - _T_166.valid <= cam_in[2].valid @[dec_decode_ctl.scala 317:47] - cam_raw[2].bits.rd <= _T_166.bits.rd @[dec_decode_ctl.scala 317:15] - cam_raw[2].bits.tag <= _T_166.bits.tag @[dec_decode_ctl.scala 317:15] - cam_raw[2].bits.wb <= _T_166.bits.wb @[dec_decode_ctl.scala 317:15] - cam_raw[2].valid <= _T_166.valid @[dec_decode_ctl.scala 317:15] - node _T_167 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam_raw[2].bits.tag) @[dec_decode_ctl.scala 318:46] - node _T_168 = and(_T_167, cam_raw[2].valid) @[dec_decode_ctl.scala 318:71] - nonblock_load_write[2] <= _T_168 @[dec_decode_ctl.scala 318:28] - node _T_169 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[3].bits.tag) @[dec_decode_ctl.scala 291:66] - node _T_170 = and(io.dctl_busbuff.lsu_nonblock_load_inv_r, _T_169) @[dec_decode_ctl.scala 291:45] - node _T_171 = and(_T_170, cam[3].valid) @[dec_decode_ctl.scala 291:87] - cam_inv_reset_val[3] <= _T_171 @[dec_decode_ctl.scala 291:26] - node _T_172 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam[3].bits.tag) @[dec_decode_ctl.scala 292:67] - node _T_173 = and(cam_data_reset, _T_172) @[dec_decode_ctl.scala 292:45] - node _T_174 = and(_T_173, cam_raw[3].valid) @[dec_decode_ctl.scala 292:88] - cam_data_reset_val[3] <= _T_174 @[dec_decode_ctl.scala 292:27] - wire _T_175 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[dec_decode_ctl.scala 293:28] - _T_175.bits.rd <= UInt<5>("h00") @[dec_decode_ctl.scala 293:28] - _T_175.bits.tag <= UInt<3>("h00") @[dec_decode_ctl.scala 293:28] - _T_175.bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 293:28] - _T_175.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 293:28] - cam_in[3].bits.rd <= _T_175.bits.rd @[dec_decode_ctl.scala 293:14] - cam_in[3].bits.tag <= _T_175.bits.tag @[dec_decode_ctl.scala 293:14] - cam_in[3].bits.wb <= _T_175.bits.wb @[dec_decode_ctl.scala 293:14] - cam_in[3].valid <= _T_175.valid @[dec_decode_ctl.scala 293:14] - cam[3].bits.rd <= cam_raw[3].bits.rd @[dec_decode_ctl.scala 294:11] - cam[3].bits.tag <= cam_raw[3].bits.tag @[dec_decode_ctl.scala 294:11] - cam[3].bits.wb <= cam_raw[3].bits.wb @[dec_decode_ctl.scala 294:11] - cam[3].valid <= cam_raw[3].valid @[dec_decode_ctl.scala 294:11] - node _T_176 = bits(cam_data_reset_val[3], 0, 0) @[dec_decode_ctl.scala 296:32] - when _T_176 : @[dec_decode_ctl.scala 296:39] - cam[3].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 297:20] - skip @[dec_decode_ctl.scala 296:39] - node _T_177 = bits(cam_wen, 3, 3) @[dec_decode_ctl.scala 299:17] - node _T_178 = bits(_T_177, 0, 0) @[dec_decode_ctl.scala 299:21] - when _T_178 : @[dec_decode_ctl.scala 299:28] - cam_in[3].valid <= UInt<1>("h01") @[dec_decode_ctl.scala 300:27] - cam_in[3].bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 301:32] - cam_in[3].bits.tag <= cam_write_tag @[dec_decode_ctl.scala 302:32] - cam_in[3].bits.rd <= nonblock_load_rd @[dec_decode_ctl.scala 303:32] - skip @[dec_decode_ctl.scala 299:28] - else : @[dec_decode_ctl.scala 304:131] - node _T_179 = bits(cam_inv_reset_val[3], 0, 0) @[dec_decode_ctl.scala 304:37] - node _T_180 = bits(i0_wen_r, 0, 0) @[dec_decode_ctl.scala 304:57] - node _T_181 = eq(r_d_in.bits.i0rd, cam[3].bits.rd) @[dec_decode_ctl.scala 304:85] - node _T_182 = and(_T_180, _T_181) @[dec_decode_ctl.scala 304:64] - node _T_183 = bits(cam[3].bits.wb, 0, 0) @[dec_decode_ctl.scala 304:123] - node _T_184 = and(_T_182, _T_183) @[dec_decode_ctl.scala 304:105] - node _T_185 = or(_T_179, _T_184) @[dec_decode_ctl.scala 304:44] - when _T_185 : @[dec_decode_ctl.scala 304:131] - cam_in[3].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 305:23] - skip @[dec_decode_ctl.scala 304:131] - else : @[dec_decode_ctl.scala 306:16] - cam_in[3].bits.rd <= cam[3].bits.rd @[dec_decode_ctl.scala 307:22] - cam_in[3].bits.tag <= cam[3].bits.tag @[dec_decode_ctl.scala 307:22] - cam_in[3].bits.wb <= cam[3].bits.wb @[dec_decode_ctl.scala 307:22] - cam_in[3].valid <= cam[3].valid @[dec_decode_ctl.scala 307:22] - skip @[dec_decode_ctl.scala 306:16] - node _T_186 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[dec_decode_ctl.scala 309:37] - node _T_187 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[3].bits.tag) @[dec_decode_ctl.scala 309:92] - node _T_188 = and(_T_186, _T_187) @[dec_decode_ctl.scala 309:44] - node _T_189 = eq(cam[3].valid, UInt<1>("h01")) @[dec_decode_ctl.scala 309:128] - node _T_190 = and(_T_188, _T_189) @[dec_decode_ctl.scala 309:113] - when _T_190 : @[dec_decode_ctl.scala 309:135] - cam_in[3].bits.wb <= UInt<1>("h01") @[dec_decode_ctl.scala 310:25] - skip @[dec_decode_ctl.scala 309:135] - when io.dec_tlu_force_halt : @[dec_decode_ctl.scala 313:32] - cam_in[3].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 314:23] - skip @[dec_decode_ctl.scala 313:32] - wire _T_191 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[dec_decode_ctl.scala 317:70] - _T_191.bits.rd <= UInt<5>("h00") @[dec_decode_ctl.scala 317:70] - _T_191.bits.tag <= UInt<3>("h00") @[dec_decode_ctl.scala 317:70] - _T_191.bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 317:70] - _T_191.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 317:70] - reg _T_192 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}, io.free_clk with : (reset => (reset, _T_191)) @[dec_decode_ctl.scala 317:47] - _T_192.bits.rd <= cam_in[3].bits.rd @[dec_decode_ctl.scala 317:47] - _T_192.bits.tag <= cam_in[3].bits.tag @[dec_decode_ctl.scala 317:47] - _T_192.bits.wb <= cam_in[3].bits.wb @[dec_decode_ctl.scala 317:47] - _T_192.valid <= cam_in[3].valid @[dec_decode_ctl.scala 317:47] - cam_raw[3].bits.rd <= _T_192.bits.rd @[dec_decode_ctl.scala 317:15] - cam_raw[3].bits.tag <= _T_192.bits.tag @[dec_decode_ctl.scala 317:15] - cam_raw[3].bits.wb <= _T_192.bits.wb @[dec_decode_ctl.scala 317:15] - cam_raw[3].valid <= _T_192.valid @[dec_decode_ctl.scala 317:15] - node _T_193 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam_raw[3].bits.tag) @[dec_decode_ctl.scala 318:46] - node _T_194 = and(_T_193, cam_raw[3].valid) @[dec_decode_ctl.scala 318:71] - nonblock_load_write[3] <= _T_194 @[dec_decode_ctl.scala 318:28] - io.dec_nonblock_load_waddr <= UInt<5>("h00") @[dec_decode_ctl.scala 321:29] - node _T_195 = eq(r_d_in.bits.i0rd, io.dec_nonblock_load_waddr) @[dec_decode_ctl.scala 323:49] - node nonblock_load_cancel = and(_T_195, i0_wen_r) @[dec_decode_ctl.scala 323:81] - node _T_196 = or(nonblock_load_write[0], nonblock_load_write[1]) @[dec_decode_ctl.scala 324:108] - node _T_197 = or(_T_196, nonblock_load_write[2]) @[dec_decode_ctl.scala 324:108] - node _T_198 = or(_T_197, nonblock_load_write[3]) @[dec_decode_ctl.scala 324:108] - node _T_199 = bits(_T_198, 0, 0) @[dec_decode_ctl.scala 324:112] - node _T_200 = and(io.dctl_busbuff.lsu_nonblock_load_data_valid, _T_199) @[dec_decode_ctl.scala 324:77] - node _T_201 = eq(nonblock_load_cancel, UInt<1>("h00")) @[dec_decode_ctl.scala 324:122] - node _T_202 = and(_T_200, _T_201) @[dec_decode_ctl.scala 324:119] - io.dec_nonblock_load_wen <= _T_202 @[dec_decode_ctl.scala 324:28] - node _T_203 = eq(nonblock_load_rd, i0r.rs1) @[dec_decode_ctl.scala 325:54] - node _T_204 = and(_T_203, io.dctl_busbuff.lsu_nonblock_load_valid_m) @[dec_decode_ctl.scala 325:66] - node _T_205 = and(_T_204, io.decode_exu.dec_i0_rs1_en_d) @[dec_decode_ctl.scala 325:110] - node _T_206 = eq(nonblock_load_rd, i0r.rs2) @[dec_decode_ctl.scala 325:161] - node _T_207 = and(_T_206, io.dctl_busbuff.lsu_nonblock_load_valid_m) @[dec_decode_ctl.scala 325:173] - node _T_208 = and(_T_207, io.decode_exu.dec_i0_rs2_en_d) @[dec_decode_ctl.scala 325:217] - node i0_nonblock_boundary_stall = or(_T_205, _T_208) @[dec_decode_ctl.scala 325:142] - i0_nonblock_load_stall <= i0_nonblock_boundary_stall @[dec_decode_ctl.scala 327:26] + node i0_load_kill_wen_r = and(nonblock_load_valid_m_delay, r_d.bits.i0load) @[dec_decode_ctl.scala 283:56] + node _T_91 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[0].bits.tag) @[dec_decode_ctl.scala 285:66] + node _T_92 = and(io.dctl_busbuff.lsu_nonblock_load_inv_r, _T_91) @[dec_decode_ctl.scala 285:45] + node _T_93 = and(_T_92, cam[0].valid) @[dec_decode_ctl.scala 285:87] + cam_inv_reset_val[0] <= _T_93 @[dec_decode_ctl.scala 285:26] + node _T_94 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam[0].bits.tag) @[dec_decode_ctl.scala 286:67] + node _T_95 = and(cam_data_reset, _T_94) @[dec_decode_ctl.scala 286:45] + node _T_96 = and(_T_95, cam_raw[0].valid) @[dec_decode_ctl.scala 286:88] + cam_data_reset_val[0] <= _T_96 @[dec_decode_ctl.scala 286:27] + wire _T_97 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[dec_decode_ctl.scala 287:28] + _T_97.bits.rd <= UInt<5>("h00") @[dec_decode_ctl.scala 287:28] + _T_97.bits.tag <= UInt<3>("h00") @[dec_decode_ctl.scala 287:28] + _T_97.bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 287:28] + _T_97.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 287:28] + cam_in[0].bits.rd <= _T_97.bits.rd @[dec_decode_ctl.scala 287:14] + cam_in[0].bits.tag <= _T_97.bits.tag @[dec_decode_ctl.scala 287:14] + cam_in[0].bits.wb <= _T_97.bits.wb @[dec_decode_ctl.scala 287:14] + cam_in[0].valid <= _T_97.valid @[dec_decode_ctl.scala 287:14] + cam[0].bits.rd <= cam_raw[0].bits.rd @[dec_decode_ctl.scala 288:11] + cam[0].bits.tag <= cam_raw[0].bits.tag @[dec_decode_ctl.scala 288:11] + cam[0].bits.wb <= cam_raw[0].bits.wb @[dec_decode_ctl.scala 288:11] + cam[0].valid <= cam_raw[0].valid @[dec_decode_ctl.scala 288:11] + node _T_98 = bits(cam_data_reset_val[0], 0, 0) @[dec_decode_ctl.scala 290:32] + when _T_98 : @[dec_decode_ctl.scala 290:39] + cam[0].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 291:20] + skip @[dec_decode_ctl.scala 290:39] + node _T_99 = bits(cam_wen, 0, 0) @[dec_decode_ctl.scala 293:17] + node _T_100 = bits(_T_99, 0, 0) @[dec_decode_ctl.scala 293:21] + when _T_100 : @[dec_decode_ctl.scala 293:28] + cam_in[0].valid <= UInt<1>("h01") @[dec_decode_ctl.scala 294:27] + cam_in[0].bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 295:32] + cam_in[0].bits.tag <= cam_write_tag @[dec_decode_ctl.scala 296:32] + cam_in[0].bits.rd <= nonblock_load_rd @[dec_decode_ctl.scala 297:32] + skip @[dec_decode_ctl.scala 293:28] + else : @[dec_decode_ctl.scala 298:131] + node _T_101 = bits(cam_inv_reset_val[0], 0, 0) @[dec_decode_ctl.scala 298:37] + node _T_102 = bits(i0_wen_r, 0, 0) @[dec_decode_ctl.scala 298:57] + node _T_103 = eq(r_d_in.bits.i0rd, cam[0].bits.rd) @[dec_decode_ctl.scala 298:85] + node _T_104 = and(_T_102, _T_103) @[dec_decode_ctl.scala 298:64] + node _T_105 = bits(cam[0].bits.wb, 0, 0) @[dec_decode_ctl.scala 298:123] + node _T_106 = and(_T_104, _T_105) @[dec_decode_ctl.scala 298:105] + node _T_107 = or(_T_101, _T_106) @[dec_decode_ctl.scala 298:44] + when _T_107 : @[dec_decode_ctl.scala 298:131] + cam_in[0].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 299:23] + skip @[dec_decode_ctl.scala 298:131] + else : @[dec_decode_ctl.scala 300:16] + cam_in[0].bits.rd <= cam[0].bits.rd @[dec_decode_ctl.scala 301:22] + cam_in[0].bits.tag <= cam[0].bits.tag @[dec_decode_ctl.scala 301:22] + cam_in[0].bits.wb <= cam[0].bits.wb @[dec_decode_ctl.scala 301:22] + cam_in[0].valid <= cam[0].valid @[dec_decode_ctl.scala 301:22] + skip @[dec_decode_ctl.scala 300:16] + node _T_108 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[dec_decode_ctl.scala 303:37] + node _T_109 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[0].bits.tag) @[dec_decode_ctl.scala 303:92] + node _T_110 = and(_T_108, _T_109) @[dec_decode_ctl.scala 303:44] + node _T_111 = eq(cam[0].valid, UInt<1>("h01")) @[dec_decode_ctl.scala 303:128] + node _T_112 = and(_T_110, _T_111) @[dec_decode_ctl.scala 303:113] + when _T_112 : @[dec_decode_ctl.scala 303:135] + cam_in[0].bits.wb <= UInt<1>("h01") @[dec_decode_ctl.scala 304:25] + skip @[dec_decode_ctl.scala 303:135] + when io.dec_tlu_force_halt : @[dec_decode_ctl.scala 307:32] + cam_in[0].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 308:23] + skip @[dec_decode_ctl.scala 307:32] + wire _T_113 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[dec_decode_ctl.scala 311:70] + _T_113.bits.rd <= UInt<5>("h00") @[dec_decode_ctl.scala 311:70] + _T_113.bits.tag <= UInt<3>("h00") @[dec_decode_ctl.scala 311:70] + _T_113.bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 311:70] + _T_113.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 311:70] + reg _T_114 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}, io.free_clk with : (reset => (reset, _T_113)) @[dec_decode_ctl.scala 311:47] + _T_114.bits.rd <= cam_in[0].bits.rd @[dec_decode_ctl.scala 311:47] + _T_114.bits.tag <= cam_in[0].bits.tag @[dec_decode_ctl.scala 311:47] + _T_114.bits.wb <= cam_in[0].bits.wb @[dec_decode_ctl.scala 311:47] + _T_114.valid <= cam_in[0].valid @[dec_decode_ctl.scala 311:47] + cam_raw[0].bits.rd <= _T_114.bits.rd @[dec_decode_ctl.scala 311:15] + cam_raw[0].bits.tag <= _T_114.bits.tag @[dec_decode_ctl.scala 311:15] + cam_raw[0].bits.wb <= _T_114.bits.wb @[dec_decode_ctl.scala 311:15] + cam_raw[0].valid <= _T_114.valid @[dec_decode_ctl.scala 311:15] + node _T_115 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam_raw[0].bits.tag) @[dec_decode_ctl.scala 312:46] + node _T_116 = and(_T_115, cam_raw[0].valid) @[dec_decode_ctl.scala 312:71] + nonblock_load_write[0] <= _T_116 @[dec_decode_ctl.scala 312:28] + node _T_117 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[1].bits.tag) @[dec_decode_ctl.scala 285:66] + node _T_118 = and(io.dctl_busbuff.lsu_nonblock_load_inv_r, _T_117) @[dec_decode_ctl.scala 285:45] + node _T_119 = and(_T_118, cam[1].valid) @[dec_decode_ctl.scala 285:87] + cam_inv_reset_val[1] <= _T_119 @[dec_decode_ctl.scala 285:26] + node _T_120 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam[1].bits.tag) @[dec_decode_ctl.scala 286:67] + node _T_121 = and(cam_data_reset, _T_120) @[dec_decode_ctl.scala 286:45] + node _T_122 = and(_T_121, cam_raw[1].valid) @[dec_decode_ctl.scala 286:88] + cam_data_reset_val[1] <= _T_122 @[dec_decode_ctl.scala 286:27] + wire _T_123 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[dec_decode_ctl.scala 287:28] + _T_123.bits.rd <= UInt<5>("h00") @[dec_decode_ctl.scala 287:28] + _T_123.bits.tag <= UInt<3>("h00") @[dec_decode_ctl.scala 287:28] + _T_123.bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 287:28] + _T_123.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 287:28] + cam_in[1].bits.rd <= _T_123.bits.rd @[dec_decode_ctl.scala 287:14] + cam_in[1].bits.tag <= _T_123.bits.tag @[dec_decode_ctl.scala 287:14] + cam_in[1].bits.wb <= _T_123.bits.wb @[dec_decode_ctl.scala 287:14] + cam_in[1].valid <= _T_123.valid @[dec_decode_ctl.scala 287:14] + cam[1].bits.rd <= cam_raw[1].bits.rd @[dec_decode_ctl.scala 288:11] + cam[1].bits.tag <= cam_raw[1].bits.tag @[dec_decode_ctl.scala 288:11] + cam[1].bits.wb <= cam_raw[1].bits.wb @[dec_decode_ctl.scala 288:11] + cam[1].valid <= cam_raw[1].valid @[dec_decode_ctl.scala 288:11] + node _T_124 = bits(cam_data_reset_val[1], 0, 0) @[dec_decode_ctl.scala 290:32] + when _T_124 : @[dec_decode_ctl.scala 290:39] + cam[1].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 291:20] + skip @[dec_decode_ctl.scala 290:39] + node _T_125 = bits(cam_wen, 1, 1) @[dec_decode_ctl.scala 293:17] + node _T_126 = bits(_T_125, 0, 0) @[dec_decode_ctl.scala 293:21] + when _T_126 : @[dec_decode_ctl.scala 293:28] + cam_in[1].valid <= UInt<1>("h01") @[dec_decode_ctl.scala 294:27] + cam_in[1].bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 295:32] + cam_in[1].bits.tag <= cam_write_tag @[dec_decode_ctl.scala 296:32] + cam_in[1].bits.rd <= nonblock_load_rd @[dec_decode_ctl.scala 297:32] + skip @[dec_decode_ctl.scala 293:28] + else : @[dec_decode_ctl.scala 298:131] + node _T_127 = bits(cam_inv_reset_val[1], 0, 0) @[dec_decode_ctl.scala 298:37] + node _T_128 = bits(i0_wen_r, 0, 0) @[dec_decode_ctl.scala 298:57] + node _T_129 = eq(r_d_in.bits.i0rd, cam[1].bits.rd) @[dec_decode_ctl.scala 298:85] + node _T_130 = and(_T_128, _T_129) @[dec_decode_ctl.scala 298:64] + node _T_131 = bits(cam[1].bits.wb, 0, 0) @[dec_decode_ctl.scala 298:123] + node _T_132 = and(_T_130, _T_131) @[dec_decode_ctl.scala 298:105] + node _T_133 = or(_T_127, _T_132) @[dec_decode_ctl.scala 298:44] + when _T_133 : @[dec_decode_ctl.scala 298:131] + cam_in[1].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 299:23] + skip @[dec_decode_ctl.scala 298:131] + else : @[dec_decode_ctl.scala 300:16] + cam_in[1].bits.rd <= cam[1].bits.rd @[dec_decode_ctl.scala 301:22] + cam_in[1].bits.tag <= cam[1].bits.tag @[dec_decode_ctl.scala 301:22] + cam_in[1].bits.wb <= cam[1].bits.wb @[dec_decode_ctl.scala 301:22] + cam_in[1].valid <= cam[1].valid @[dec_decode_ctl.scala 301:22] + skip @[dec_decode_ctl.scala 300:16] + node _T_134 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[dec_decode_ctl.scala 303:37] + node _T_135 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[1].bits.tag) @[dec_decode_ctl.scala 303:92] + node _T_136 = and(_T_134, _T_135) @[dec_decode_ctl.scala 303:44] + node _T_137 = eq(cam[1].valid, UInt<1>("h01")) @[dec_decode_ctl.scala 303:128] + node _T_138 = and(_T_136, _T_137) @[dec_decode_ctl.scala 303:113] + when _T_138 : @[dec_decode_ctl.scala 303:135] + cam_in[1].bits.wb <= UInt<1>("h01") @[dec_decode_ctl.scala 304:25] + skip @[dec_decode_ctl.scala 303:135] + when io.dec_tlu_force_halt : @[dec_decode_ctl.scala 307:32] + cam_in[1].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 308:23] + skip @[dec_decode_ctl.scala 307:32] + wire _T_139 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[dec_decode_ctl.scala 311:70] + _T_139.bits.rd <= UInt<5>("h00") @[dec_decode_ctl.scala 311:70] + _T_139.bits.tag <= UInt<3>("h00") @[dec_decode_ctl.scala 311:70] + _T_139.bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 311:70] + _T_139.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 311:70] + reg _T_140 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}, io.free_clk with : (reset => (reset, _T_139)) @[dec_decode_ctl.scala 311:47] + _T_140.bits.rd <= cam_in[1].bits.rd @[dec_decode_ctl.scala 311:47] + _T_140.bits.tag <= cam_in[1].bits.tag @[dec_decode_ctl.scala 311:47] + _T_140.bits.wb <= cam_in[1].bits.wb @[dec_decode_ctl.scala 311:47] + _T_140.valid <= cam_in[1].valid @[dec_decode_ctl.scala 311:47] + cam_raw[1].bits.rd <= _T_140.bits.rd @[dec_decode_ctl.scala 311:15] + cam_raw[1].bits.tag <= _T_140.bits.tag @[dec_decode_ctl.scala 311:15] + cam_raw[1].bits.wb <= _T_140.bits.wb @[dec_decode_ctl.scala 311:15] + cam_raw[1].valid <= _T_140.valid @[dec_decode_ctl.scala 311:15] + node _T_141 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam_raw[1].bits.tag) @[dec_decode_ctl.scala 312:46] + node _T_142 = and(_T_141, cam_raw[1].valid) @[dec_decode_ctl.scala 312:71] + nonblock_load_write[1] <= _T_142 @[dec_decode_ctl.scala 312:28] + node _T_143 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[2].bits.tag) @[dec_decode_ctl.scala 285:66] + node _T_144 = and(io.dctl_busbuff.lsu_nonblock_load_inv_r, _T_143) @[dec_decode_ctl.scala 285:45] + node _T_145 = and(_T_144, cam[2].valid) @[dec_decode_ctl.scala 285:87] + cam_inv_reset_val[2] <= _T_145 @[dec_decode_ctl.scala 285:26] + node _T_146 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam[2].bits.tag) @[dec_decode_ctl.scala 286:67] + node _T_147 = and(cam_data_reset, _T_146) @[dec_decode_ctl.scala 286:45] + node _T_148 = and(_T_147, cam_raw[2].valid) @[dec_decode_ctl.scala 286:88] + cam_data_reset_val[2] <= _T_148 @[dec_decode_ctl.scala 286:27] + wire _T_149 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[dec_decode_ctl.scala 287:28] + _T_149.bits.rd <= UInt<5>("h00") @[dec_decode_ctl.scala 287:28] + _T_149.bits.tag <= UInt<3>("h00") @[dec_decode_ctl.scala 287:28] + _T_149.bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 287:28] + _T_149.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 287:28] + cam_in[2].bits.rd <= _T_149.bits.rd @[dec_decode_ctl.scala 287:14] + cam_in[2].bits.tag <= _T_149.bits.tag @[dec_decode_ctl.scala 287:14] + cam_in[2].bits.wb <= _T_149.bits.wb @[dec_decode_ctl.scala 287:14] + cam_in[2].valid <= _T_149.valid @[dec_decode_ctl.scala 287:14] + cam[2].bits.rd <= cam_raw[2].bits.rd @[dec_decode_ctl.scala 288:11] + cam[2].bits.tag <= cam_raw[2].bits.tag @[dec_decode_ctl.scala 288:11] + cam[2].bits.wb <= cam_raw[2].bits.wb @[dec_decode_ctl.scala 288:11] + cam[2].valid <= cam_raw[2].valid @[dec_decode_ctl.scala 288:11] + node _T_150 = bits(cam_data_reset_val[2], 0, 0) @[dec_decode_ctl.scala 290:32] + when _T_150 : @[dec_decode_ctl.scala 290:39] + cam[2].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 291:20] + skip @[dec_decode_ctl.scala 290:39] + node _T_151 = bits(cam_wen, 2, 2) @[dec_decode_ctl.scala 293:17] + node _T_152 = bits(_T_151, 0, 0) @[dec_decode_ctl.scala 293:21] + when _T_152 : @[dec_decode_ctl.scala 293:28] + cam_in[2].valid <= UInt<1>("h01") @[dec_decode_ctl.scala 294:27] + cam_in[2].bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 295:32] + cam_in[2].bits.tag <= cam_write_tag @[dec_decode_ctl.scala 296:32] + cam_in[2].bits.rd <= nonblock_load_rd @[dec_decode_ctl.scala 297:32] + skip @[dec_decode_ctl.scala 293:28] + else : @[dec_decode_ctl.scala 298:131] + node _T_153 = bits(cam_inv_reset_val[2], 0, 0) @[dec_decode_ctl.scala 298:37] + node _T_154 = bits(i0_wen_r, 0, 0) @[dec_decode_ctl.scala 298:57] + node _T_155 = eq(r_d_in.bits.i0rd, cam[2].bits.rd) @[dec_decode_ctl.scala 298:85] + node _T_156 = and(_T_154, _T_155) @[dec_decode_ctl.scala 298:64] + node _T_157 = bits(cam[2].bits.wb, 0, 0) @[dec_decode_ctl.scala 298:123] + node _T_158 = and(_T_156, _T_157) @[dec_decode_ctl.scala 298:105] + node _T_159 = or(_T_153, _T_158) @[dec_decode_ctl.scala 298:44] + when _T_159 : @[dec_decode_ctl.scala 298:131] + cam_in[2].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 299:23] + skip @[dec_decode_ctl.scala 298:131] + else : @[dec_decode_ctl.scala 300:16] + cam_in[2].bits.rd <= cam[2].bits.rd @[dec_decode_ctl.scala 301:22] + cam_in[2].bits.tag <= cam[2].bits.tag @[dec_decode_ctl.scala 301:22] + cam_in[2].bits.wb <= cam[2].bits.wb @[dec_decode_ctl.scala 301:22] + cam_in[2].valid <= cam[2].valid @[dec_decode_ctl.scala 301:22] + skip @[dec_decode_ctl.scala 300:16] + node _T_160 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[dec_decode_ctl.scala 303:37] + node _T_161 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[2].bits.tag) @[dec_decode_ctl.scala 303:92] + node _T_162 = and(_T_160, _T_161) @[dec_decode_ctl.scala 303:44] + node _T_163 = eq(cam[2].valid, UInt<1>("h01")) @[dec_decode_ctl.scala 303:128] + node _T_164 = and(_T_162, _T_163) @[dec_decode_ctl.scala 303:113] + when _T_164 : @[dec_decode_ctl.scala 303:135] + cam_in[2].bits.wb <= UInt<1>("h01") @[dec_decode_ctl.scala 304:25] + skip @[dec_decode_ctl.scala 303:135] + when io.dec_tlu_force_halt : @[dec_decode_ctl.scala 307:32] + cam_in[2].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 308:23] + skip @[dec_decode_ctl.scala 307:32] + wire _T_165 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[dec_decode_ctl.scala 311:70] + _T_165.bits.rd <= UInt<5>("h00") @[dec_decode_ctl.scala 311:70] + _T_165.bits.tag <= UInt<3>("h00") @[dec_decode_ctl.scala 311:70] + _T_165.bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 311:70] + _T_165.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 311:70] + reg _T_166 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}, io.free_clk with : (reset => (reset, _T_165)) @[dec_decode_ctl.scala 311:47] + _T_166.bits.rd <= cam_in[2].bits.rd @[dec_decode_ctl.scala 311:47] + _T_166.bits.tag <= cam_in[2].bits.tag @[dec_decode_ctl.scala 311:47] + _T_166.bits.wb <= cam_in[2].bits.wb @[dec_decode_ctl.scala 311:47] + _T_166.valid <= cam_in[2].valid @[dec_decode_ctl.scala 311:47] + cam_raw[2].bits.rd <= _T_166.bits.rd @[dec_decode_ctl.scala 311:15] + cam_raw[2].bits.tag <= _T_166.bits.tag @[dec_decode_ctl.scala 311:15] + cam_raw[2].bits.wb <= _T_166.bits.wb @[dec_decode_ctl.scala 311:15] + cam_raw[2].valid <= _T_166.valid @[dec_decode_ctl.scala 311:15] + node _T_167 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam_raw[2].bits.tag) @[dec_decode_ctl.scala 312:46] + node _T_168 = and(_T_167, cam_raw[2].valid) @[dec_decode_ctl.scala 312:71] + nonblock_load_write[2] <= _T_168 @[dec_decode_ctl.scala 312:28] + node _T_169 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[3].bits.tag) @[dec_decode_ctl.scala 285:66] + node _T_170 = and(io.dctl_busbuff.lsu_nonblock_load_inv_r, _T_169) @[dec_decode_ctl.scala 285:45] + node _T_171 = and(_T_170, cam[3].valid) @[dec_decode_ctl.scala 285:87] + cam_inv_reset_val[3] <= _T_171 @[dec_decode_ctl.scala 285:26] + node _T_172 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam[3].bits.tag) @[dec_decode_ctl.scala 286:67] + node _T_173 = and(cam_data_reset, _T_172) @[dec_decode_ctl.scala 286:45] + node _T_174 = and(_T_173, cam_raw[3].valid) @[dec_decode_ctl.scala 286:88] + cam_data_reset_val[3] <= _T_174 @[dec_decode_ctl.scala 286:27] + wire _T_175 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[dec_decode_ctl.scala 287:28] + _T_175.bits.rd <= UInt<5>("h00") @[dec_decode_ctl.scala 287:28] + _T_175.bits.tag <= UInt<3>("h00") @[dec_decode_ctl.scala 287:28] + _T_175.bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 287:28] + _T_175.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 287:28] + cam_in[3].bits.rd <= _T_175.bits.rd @[dec_decode_ctl.scala 287:14] + cam_in[3].bits.tag <= _T_175.bits.tag @[dec_decode_ctl.scala 287:14] + cam_in[3].bits.wb <= _T_175.bits.wb @[dec_decode_ctl.scala 287:14] + cam_in[3].valid <= _T_175.valid @[dec_decode_ctl.scala 287:14] + cam[3].bits.rd <= cam_raw[3].bits.rd @[dec_decode_ctl.scala 288:11] + cam[3].bits.tag <= cam_raw[3].bits.tag @[dec_decode_ctl.scala 288:11] + cam[3].bits.wb <= cam_raw[3].bits.wb @[dec_decode_ctl.scala 288:11] + cam[3].valid <= cam_raw[3].valid @[dec_decode_ctl.scala 288:11] + node _T_176 = bits(cam_data_reset_val[3], 0, 0) @[dec_decode_ctl.scala 290:32] + when _T_176 : @[dec_decode_ctl.scala 290:39] + cam[3].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 291:20] + skip @[dec_decode_ctl.scala 290:39] + node _T_177 = bits(cam_wen, 3, 3) @[dec_decode_ctl.scala 293:17] + node _T_178 = bits(_T_177, 0, 0) @[dec_decode_ctl.scala 293:21] + when _T_178 : @[dec_decode_ctl.scala 293:28] + cam_in[3].valid <= UInt<1>("h01") @[dec_decode_ctl.scala 294:27] + cam_in[3].bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 295:32] + cam_in[3].bits.tag <= cam_write_tag @[dec_decode_ctl.scala 296:32] + cam_in[3].bits.rd <= nonblock_load_rd @[dec_decode_ctl.scala 297:32] + skip @[dec_decode_ctl.scala 293:28] + else : @[dec_decode_ctl.scala 298:131] + node _T_179 = bits(cam_inv_reset_val[3], 0, 0) @[dec_decode_ctl.scala 298:37] + node _T_180 = bits(i0_wen_r, 0, 0) @[dec_decode_ctl.scala 298:57] + node _T_181 = eq(r_d_in.bits.i0rd, cam[3].bits.rd) @[dec_decode_ctl.scala 298:85] + node _T_182 = and(_T_180, _T_181) @[dec_decode_ctl.scala 298:64] + node _T_183 = bits(cam[3].bits.wb, 0, 0) @[dec_decode_ctl.scala 298:123] + node _T_184 = and(_T_182, _T_183) @[dec_decode_ctl.scala 298:105] + node _T_185 = or(_T_179, _T_184) @[dec_decode_ctl.scala 298:44] + when _T_185 : @[dec_decode_ctl.scala 298:131] + cam_in[3].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 299:23] + skip @[dec_decode_ctl.scala 298:131] + else : @[dec_decode_ctl.scala 300:16] + cam_in[3].bits.rd <= cam[3].bits.rd @[dec_decode_ctl.scala 301:22] + cam_in[3].bits.tag <= cam[3].bits.tag @[dec_decode_ctl.scala 301:22] + cam_in[3].bits.wb <= cam[3].bits.wb @[dec_decode_ctl.scala 301:22] + cam_in[3].valid <= cam[3].valid @[dec_decode_ctl.scala 301:22] + skip @[dec_decode_ctl.scala 300:16] + node _T_186 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[dec_decode_ctl.scala 303:37] + node _T_187 = eq(io.dctl_busbuff.lsu_nonblock_load_inv_tag_r, cam[3].bits.tag) @[dec_decode_ctl.scala 303:92] + node _T_188 = and(_T_186, _T_187) @[dec_decode_ctl.scala 303:44] + node _T_189 = eq(cam[3].valid, UInt<1>("h01")) @[dec_decode_ctl.scala 303:128] + node _T_190 = and(_T_188, _T_189) @[dec_decode_ctl.scala 303:113] + when _T_190 : @[dec_decode_ctl.scala 303:135] + cam_in[3].bits.wb <= UInt<1>("h01") @[dec_decode_ctl.scala 304:25] + skip @[dec_decode_ctl.scala 303:135] + when io.dec_tlu_force_halt : @[dec_decode_ctl.scala 307:32] + cam_in[3].valid <= UInt<1>("h00") @[dec_decode_ctl.scala 308:23] + skip @[dec_decode_ctl.scala 307:32] + wire _T_191 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}} @[dec_decode_ctl.scala 311:70] + _T_191.bits.rd <= UInt<5>("h00") @[dec_decode_ctl.scala 311:70] + _T_191.bits.tag <= UInt<3>("h00") @[dec_decode_ctl.scala 311:70] + _T_191.bits.wb <= UInt<1>("h00") @[dec_decode_ctl.scala 311:70] + _T_191.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 311:70] + reg _T_192 : {valid : UInt<1>, bits : {wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}}, io.free_clk with : (reset => (reset, _T_191)) @[dec_decode_ctl.scala 311:47] + _T_192.bits.rd <= cam_in[3].bits.rd @[dec_decode_ctl.scala 311:47] + _T_192.bits.tag <= cam_in[3].bits.tag @[dec_decode_ctl.scala 311:47] + _T_192.bits.wb <= cam_in[3].bits.wb @[dec_decode_ctl.scala 311:47] + _T_192.valid <= cam_in[3].valid @[dec_decode_ctl.scala 311:47] + cam_raw[3].bits.rd <= _T_192.bits.rd @[dec_decode_ctl.scala 311:15] + cam_raw[3].bits.tag <= _T_192.bits.tag @[dec_decode_ctl.scala 311:15] + cam_raw[3].bits.wb <= _T_192.bits.wb @[dec_decode_ctl.scala 311:15] + cam_raw[3].valid <= _T_192.valid @[dec_decode_ctl.scala 311:15] + node _T_193 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, cam_raw[3].bits.tag) @[dec_decode_ctl.scala 312:46] + node _T_194 = and(_T_193, cam_raw[3].valid) @[dec_decode_ctl.scala 312:71] + nonblock_load_write[3] <= _T_194 @[dec_decode_ctl.scala 312:28] + io.dec_nonblock_load_waddr <= UInt<5>("h00") @[dec_decode_ctl.scala 315:29] + node _T_195 = eq(r_d_in.bits.i0rd, io.dec_nonblock_load_waddr) @[dec_decode_ctl.scala 317:49] + node nonblock_load_cancel = and(_T_195, i0_wen_r) @[dec_decode_ctl.scala 317:81] + node _T_196 = or(nonblock_load_write[0], nonblock_load_write[1]) @[dec_decode_ctl.scala 318:108] + node _T_197 = or(_T_196, nonblock_load_write[2]) @[dec_decode_ctl.scala 318:108] + node _T_198 = or(_T_197, nonblock_load_write[3]) @[dec_decode_ctl.scala 318:108] + node _T_199 = bits(_T_198, 0, 0) @[dec_decode_ctl.scala 318:112] + node _T_200 = and(io.dctl_busbuff.lsu_nonblock_load_data_valid, _T_199) @[dec_decode_ctl.scala 318:77] + node _T_201 = eq(nonblock_load_cancel, UInt<1>("h00")) @[dec_decode_ctl.scala 318:122] + node _T_202 = and(_T_200, _T_201) @[dec_decode_ctl.scala 318:119] + io.dec_nonblock_load_wen <= _T_202 @[dec_decode_ctl.scala 318:28] + node _T_203 = eq(nonblock_load_rd, i0r.rs1) @[dec_decode_ctl.scala 319:54] + node _T_204 = and(_T_203, io.dctl_busbuff.lsu_nonblock_load_valid_m) @[dec_decode_ctl.scala 319:66] + node _T_205 = and(_T_204, io.decode_exu.dec_i0_rs1_en_d) @[dec_decode_ctl.scala 319:110] + node _T_206 = eq(nonblock_load_rd, i0r.rs2) @[dec_decode_ctl.scala 319:161] + node _T_207 = and(_T_206, io.dctl_busbuff.lsu_nonblock_load_valid_m) @[dec_decode_ctl.scala 319:173] + node _T_208 = and(_T_207, io.decode_exu.dec_i0_rs2_en_d) @[dec_decode_ctl.scala 319:217] + node i0_nonblock_boundary_stall = or(_T_205, _T_208) @[dec_decode_ctl.scala 319:142] + i0_nonblock_load_stall <= i0_nonblock_boundary_stall @[dec_decode_ctl.scala 321:26] node _T_209 = bits(nonblock_load_write[0], 0, 0) @[Bitwise.scala 72:15] node _T_210 = mux(_T_209, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] - node _T_211 = and(_T_210, cam[0].bits.rd) @[dec_decode_ctl.scala 329:88] - node _T_212 = and(io.decode_exu.dec_i0_rs1_en_d, cam[0].valid) @[dec_decode_ctl.scala 329:137] - node _T_213 = eq(cam[0].bits.rd, i0r.rs1) @[dec_decode_ctl.scala 329:170] - node _T_214 = and(_T_212, _T_213) @[dec_decode_ctl.scala 329:152] - node _T_215 = and(io.decode_exu.dec_i0_rs2_en_d, cam[0].valid) @[dec_decode_ctl.scala 329:214] - node _T_216 = eq(cam[0].bits.rd, i0r.rs2) @[dec_decode_ctl.scala 329:247] - node _T_217 = and(_T_215, _T_216) @[dec_decode_ctl.scala 329:229] + node _T_211 = and(_T_210, cam[0].bits.rd) @[dec_decode_ctl.scala 323:88] + node _T_212 = and(io.decode_exu.dec_i0_rs1_en_d, cam[0].valid) @[dec_decode_ctl.scala 323:137] + node _T_213 = eq(cam[0].bits.rd, i0r.rs1) @[dec_decode_ctl.scala 323:170] + node _T_214 = and(_T_212, _T_213) @[dec_decode_ctl.scala 323:152] + node _T_215 = and(io.decode_exu.dec_i0_rs2_en_d, cam[0].valid) @[dec_decode_ctl.scala 323:214] + node _T_216 = eq(cam[0].bits.rd, i0r.rs2) @[dec_decode_ctl.scala 323:247] + node _T_217 = and(_T_215, _T_216) @[dec_decode_ctl.scala 323:229] node _T_218 = bits(nonblock_load_write[1], 0, 0) @[Bitwise.scala 72:15] node _T_219 = mux(_T_218, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] - node _T_220 = and(_T_219, cam[1].bits.rd) @[dec_decode_ctl.scala 329:88] - node _T_221 = and(io.decode_exu.dec_i0_rs1_en_d, cam[1].valid) @[dec_decode_ctl.scala 329:137] - node _T_222 = eq(cam[1].bits.rd, i0r.rs1) @[dec_decode_ctl.scala 329:170] - node _T_223 = and(_T_221, _T_222) @[dec_decode_ctl.scala 329:152] - node _T_224 = and(io.decode_exu.dec_i0_rs2_en_d, cam[1].valid) @[dec_decode_ctl.scala 329:214] - node _T_225 = eq(cam[1].bits.rd, i0r.rs2) @[dec_decode_ctl.scala 329:247] - node _T_226 = and(_T_224, _T_225) @[dec_decode_ctl.scala 329:229] + node _T_220 = and(_T_219, cam[1].bits.rd) @[dec_decode_ctl.scala 323:88] + node _T_221 = and(io.decode_exu.dec_i0_rs1_en_d, cam[1].valid) @[dec_decode_ctl.scala 323:137] + node _T_222 = eq(cam[1].bits.rd, i0r.rs1) @[dec_decode_ctl.scala 323:170] + node _T_223 = and(_T_221, _T_222) @[dec_decode_ctl.scala 323:152] + node _T_224 = and(io.decode_exu.dec_i0_rs2_en_d, cam[1].valid) @[dec_decode_ctl.scala 323:214] + node _T_225 = eq(cam[1].bits.rd, i0r.rs2) @[dec_decode_ctl.scala 323:247] + node _T_226 = and(_T_224, _T_225) @[dec_decode_ctl.scala 323:229] node _T_227 = bits(nonblock_load_write[2], 0, 0) @[Bitwise.scala 72:15] node _T_228 = mux(_T_227, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] - node _T_229 = and(_T_228, cam[2].bits.rd) @[dec_decode_ctl.scala 329:88] - node _T_230 = and(io.decode_exu.dec_i0_rs1_en_d, cam[2].valid) @[dec_decode_ctl.scala 329:137] - node _T_231 = eq(cam[2].bits.rd, i0r.rs1) @[dec_decode_ctl.scala 329:170] - node _T_232 = and(_T_230, _T_231) @[dec_decode_ctl.scala 329:152] - node _T_233 = and(io.decode_exu.dec_i0_rs2_en_d, cam[2].valid) @[dec_decode_ctl.scala 329:214] - node _T_234 = eq(cam[2].bits.rd, i0r.rs2) @[dec_decode_ctl.scala 329:247] - node _T_235 = and(_T_233, _T_234) @[dec_decode_ctl.scala 329:229] + node _T_229 = and(_T_228, cam[2].bits.rd) @[dec_decode_ctl.scala 323:88] + node _T_230 = and(io.decode_exu.dec_i0_rs1_en_d, cam[2].valid) @[dec_decode_ctl.scala 323:137] + node _T_231 = eq(cam[2].bits.rd, i0r.rs1) @[dec_decode_ctl.scala 323:170] + node _T_232 = and(_T_230, _T_231) @[dec_decode_ctl.scala 323:152] + node _T_233 = and(io.decode_exu.dec_i0_rs2_en_d, cam[2].valid) @[dec_decode_ctl.scala 323:214] + node _T_234 = eq(cam[2].bits.rd, i0r.rs2) @[dec_decode_ctl.scala 323:247] + node _T_235 = and(_T_233, _T_234) @[dec_decode_ctl.scala 323:229] node _T_236 = bits(nonblock_load_write[3], 0, 0) @[Bitwise.scala 72:15] node _T_237 = mux(_T_236, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] - node _T_238 = and(_T_237, cam[3].bits.rd) @[dec_decode_ctl.scala 329:88] - node _T_239 = and(io.decode_exu.dec_i0_rs1_en_d, cam[3].valid) @[dec_decode_ctl.scala 329:137] - node _T_240 = eq(cam[3].bits.rd, i0r.rs1) @[dec_decode_ctl.scala 329:170] - node _T_241 = and(_T_239, _T_240) @[dec_decode_ctl.scala 329:152] - node _T_242 = and(io.decode_exu.dec_i0_rs2_en_d, cam[3].valid) @[dec_decode_ctl.scala 329:214] - node _T_243 = eq(cam[3].bits.rd, i0r.rs2) @[dec_decode_ctl.scala 329:247] - node _T_244 = and(_T_242, _T_243) @[dec_decode_ctl.scala 329:229] - node _T_245 = or(_T_211, _T_220) @[dec_decode_ctl.scala 330:69] - node _T_246 = or(_T_245, _T_229) @[dec_decode_ctl.scala 330:69] - node waddr = or(_T_246, _T_238) @[dec_decode_ctl.scala 330:69] - node _T_247 = or(_T_214, _T_223) @[dec_decode_ctl.scala 330:102] - node _T_248 = or(_T_247, _T_232) @[dec_decode_ctl.scala 330:102] - node ld_stall_1 = or(_T_248, _T_241) @[dec_decode_ctl.scala 330:102] - node _T_249 = or(_T_217, _T_226) @[dec_decode_ctl.scala 330:134] - node _T_250 = or(_T_249, _T_235) @[dec_decode_ctl.scala 330:134] - node ld_stall_2 = or(_T_250, _T_244) @[dec_decode_ctl.scala 330:134] - io.dec_nonblock_load_waddr <= waddr @[dec_decode_ctl.scala 331:29] - node _T_251 = or(ld_stall_1, ld_stall_2) @[dec_decode_ctl.scala 332:38] - node _T_252 = or(_T_251, i0_nonblock_boundary_stall) @[dec_decode_ctl.scala 332:51] - i0_nonblock_load_stall <= _T_252 @[dec_decode_ctl.scala 332:25] - node _T_253 = eq(i0_predict_br, UInt<1>("h00")) @[dec_decode_ctl.scala 341:34] - node i0_br_unpred = and(i0_dp.jal, _T_253) @[dec_decode_ctl.scala 341:32] + node _T_238 = and(_T_237, cam[3].bits.rd) @[dec_decode_ctl.scala 323:88] + node _T_239 = and(io.decode_exu.dec_i0_rs1_en_d, cam[3].valid) @[dec_decode_ctl.scala 323:137] + node _T_240 = eq(cam[3].bits.rd, i0r.rs1) @[dec_decode_ctl.scala 323:170] + node _T_241 = and(_T_239, _T_240) @[dec_decode_ctl.scala 323:152] + node _T_242 = and(io.decode_exu.dec_i0_rs2_en_d, cam[3].valid) @[dec_decode_ctl.scala 323:214] + node _T_243 = eq(cam[3].bits.rd, i0r.rs2) @[dec_decode_ctl.scala 323:247] + node _T_244 = and(_T_242, _T_243) @[dec_decode_ctl.scala 323:229] + node _T_245 = or(_T_211, _T_220) @[dec_decode_ctl.scala 324:69] + node _T_246 = or(_T_245, _T_229) @[dec_decode_ctl.scala 324:69] + node waddr = or(_T_246, _T_238) @[dec_decode_ctl.scala 324:69] + node _T_247 = or(_T_214, _T_223) @[dec_decode_ctl.scala 324:102] + node _T_248 = or(_T_247, _T_232) @[dec_decode_ctl.scala 324:102] + node ld_stall_1 = or(_T_248, _T_241) @[dec_decode_ctl.scala 324:102] + node _T_249 = or(_T_217, _T_226) @[dec_decode_ctl.scala 324:134] + node _T_250 = or(_T_249, _T_235) @[dec_decode_ctl.scala 324:134] + node ld_stall_2 = or(_T_250, _T_244) @[dec_decode_ctl.scala 324:134] + io.dec_nonblock_load_waddr <= waddr @[dec_decode_ctl.scala 325:29] + node _T_251 = or(ld_stall_1, ld_stall_2) @[dec_decode_ctl.scala 326:38] + node _T_252 = or(_T_251, i0_nonblock_boundary_stall) @[dec_decode_ctl.scala 326:51] + i0_nonblock_load_stall <= _T_252 @[dec_decode_ctl.scala 326:25] + node _T_253 = eq(i0_predict_br, UInt<1>("h00")) @[dec_decode_ctl.scala 335:34] + node i0_br_unpred = and(i0_dp.jal, _T_253) @[dec_decode_ctl.scala 335:32] node _T_254 = bits(i0_legal_decode_d, 0, 0) @[Bitwise.scala 72:15] node _T_255 = mux(_T_254, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_256 = and(csr_read, io.dec_csr_wen_unq_d) @[dec_decode_ctl.scala 353:16] - node _T_257 = bits(_T_256, 0, 0) @[dec_decode_ctl.scala 353:30] - node _T_258 = eq(csr_read, UInt<1>("h00")) @[dec_decode_ctl.scala 354:6] - node _T_259 = and(_T_258, io.dec_csr_wen_unq_d) @[dec_decode_ctl.scala 354:16] - node _T_260 = bits(_T_259, 0, 0) @[dec_decode_ctl.scala 354:30] - node _T_261 = eq(io.dec_csr_wen_unq_d, UInt<1>("h00")) @[dec_decode_ctl.scala 355:18] - node _T_262 = and(csr_read, _T_261) @[dec_decode_ctl.scala 355:16] - node _T_263 = bits(_T_262, 0, 0) @[dec_decode_ctl.scala 355:30] + node _T_256 = and(csr_read, io.dec_csr_wen_unq_d) @[dec_decode_ctl.scala 347:16] + node _T_257 = bits(_T_256, 0, 0) @[dec_decode_ctl.scala 347:30] + node _T_258 = eq(csr_read, UInt<1>("h00")) @[dec_decode_ctl.scala 348:6] + node _T_259 = and(_T_258, io.dec_csr_wen_unq_d) @[dec_decode_ctl.scala 348:16] + node _T_260 = bits(_T_259, 0, 0) @[dec_decode_ctl.scala 348:30] + node _T_261 = eq(io.dec_csr_wen_unq_d, UInt<1>("h00")) @[dec_decode_ctl.scala 349:18] + node _T_262 = and(csr_read, _T_261) @[dec_decode_ctl.scala 349:16] + node _T_263 = bits(_T_262, 0, 0) @[dec_decode_ctl.scala 349:30] node _T_264 = mux(i0_dp.mul, UInt<4>("h01"), UInt<4>("h00")) @[Mux.scala 98:16] node _T_265 = mux(i0_dp.load, UInt<4>("h02"), _T_264) @[Mux.scala 98:16] node _T_266 = mux(i0_dp.store, UInt<4>("h03"), _T_265) @[Mux.scala 98:16] @@ -67725,244 +67725,244 @@ circuit quasar_wrapper : node _T_275 = mux(i0_dp.mret, UInt<4>("h0c"), _T_274) @[Mux.scala 98:16] node _T_276 = mux(i0_dp.condbr, UInt<4>("h0d"), _T_275) @[Mux.scala 98:16] node _T_277 = mux(i0_dp.jal, UInt<4>("h0e"), _T_276) @[Mux.scala 98:16] - node _T_278 = and(_T_255, _T_277) @[dec_decode_ctl.scala 345:49] - d_t.pmu_i0_itype <= _T_278 @[dec_decode_ctl.scala 345:21] - inst i0_dec of dec_dec_ctl @[dec_decode_ctl.scala 362:22] + node _T_278 = and(_T_255, _T_277) @[dec_decode_ctl.scala 339:49] + d_t.pmu_i0_itype <= _T_278 @[dec_decode_ctl.scala 339:21] + inst i0_dec of dec_dec_ctl @[dec_decode_ctl.scala 356:22] i0_dec.clock <= clock i0_dec.reset <= reset - i0_dec.io.ins <= io.dec_i0_instr_d @[dec_decode_ctl.scala 363:16] - i0_dp_raw.legal <= i0_dec.io.out.legal @[dec_decode_ctl.scala 364:12] - i0_dp_raw.pm_alu <= i0_dec.io.out.pm_alu @[dec_decode_ctl.scala 364:12] - i0_dp_raw.fence_i <= i0_dec.io.out.fence_i @[dec_decode_ctl.scala 364:12] - i0_dp_raw.fence <= i0_dec.io.out.fence @[dec_decode_ctl.scala 364:12] - i0_dp_raw.rem <= i0_dec.io.out.rem @[dec_decode_ctl.scala 364:12] - i0_dp_raw.div <= i0_dec.io.out.div @[dec_decode_ctl.scala 364:12] - i0_dp_raw.low <= i0_dec.io.out.low @[dec_decode_ctl.scala 364:12] - i0_dp_raw.rs2_sign <= i0_dec.io.out.rs2_sign @[dec_decode_ctl.scala 364:12] - i0_dp_raw.rs1_sign <= i0_dec.io.out.rs1_sign @[dec_decode_ctl.scala 364:12] - i0_dp_raw.mul <= i0_dec.io.out.mul @[dec_decode_ctl.scala 364:12] - i0_dp_raw.mret <= i0_dec.io.out.mret @[dec_decode_ctl.scala 364:12] - i0_dp_raw.ecall <= i0_dec.io.out.ecall @[dec_decode_ctl.scala 364:12] - i0_dp_raw.ebreak <= i0_dec.io.out.ebreak @[dec_decode_ctl.scala 364:12] - i0_dp_raw.postsync <= i0_dec.io.out.postsync @[dec_decode_ctl.scala 364:12] - i0_dp_raw.presync <= i0_dec.io.out.presync @[dec_decode_ctl.scala 364:12] - i0_dp_raw.csr_imm <= i0_dec.io.out.csr_imm @[dec_decode_ctl.scala 364:12] - i0_dp_raw.csr_write <= i0_dec.io.out.csr_write @[dec_decode_ctl.scala 364:12] - i0_dp_raw.csr_set <= i0_dec.io.out.csr_set @[dec_decode_ctl.scala 364:12] - i0_dp_raw.csr_clr <= i0_dec.io.out.csr_clr @[dec_decode_ctl.scala 364:12] - i0_dp_raw.csr_read <= i0_dec.io.out.csr_read @[dec_decode_ctl.scala 364:12] - i0_dp_raw.word <= i0_dec.io.out.word @[dec_decode_ctl.scala 364:12] - i0_dp_raw.half <= i0_dec.io.out.half @[dec_decode_ctl.scala 364:12] - i0_dp_raw.by <= i0_dec.io.out.by @[dec_decode_ctl.scala 364:12] - i0_dp_raw.jal <= i0_dec.io.out.jal @[dec_decode_ctl.scala 364:12] - i0_dp_raw.blt <= i0_dec.io.out.blt @[dec_decode_ctl.scala 364:12] - i0_dp_raw.bge <= i0_dec.io.out.bge @[dec_decode_ctl.scala 364:12] - i0_dp_raw.bne <= i0_dec.io.out.bne @[dec_decode_ctl.scala 364:12] - i0_dp_raw.beq <= i0_dec.io.out.beq @[dec_decode_ctl.scala 364:12] - i0_dp_raw.condbr <= i0_dec.io.out.condbr @[dec_decode_ctl.scala 364:12] - i0_dp_raw.unsign <= i0_dec.io.out.unsign @[dec_decode_ctl.scala 364:12] - i0_dp_raw.slt <= i0_dec.io.out.slt @[dec_decode_ctl.scala 364:12] - i0_dp_raw.srl <= i0_dec.io.out.srl @[dec_decode_ctl.scala 364:12] - i0_dp_raw.sra <= i0_dec.io.out.sra @[dec_decode_ctl.scala 364:12] - i0_dp_raw.sll <= i0_dec.io.out.sll @[dec_decode_ctl.scala 364:12] - i0_dp_raw.lxor <= i0_dec.io.out.lxor @[dec_decode_ctl.scala 364:12] - i0_dp_raw.lor <= i0_dec.io.out.lor @[dec_decode_ctl.scala 364:12] - i0_dp_raw.land <= i0_dec.io.out.land @[dec_decode_ctl.scala 364:12] - i0_dp_raw.sub <= i0_dec.io.out.sub @[dec_decode_ctl.scala 364:12] - i0_dp_raw.add <= i0_dec.io.out.add @[dec_decode_ctl.scala 364:12] - i0_dp_raw.lsu <= i0_dec.io.out.lsu @[dec_decode_ctl.scala 364:12] - i0_dp_raw.store <= i0_dec.io.out.store @[dec_decode_ctl.scala 364:12] - i0_dp_raw.load <= i0_dec.io.out.load @[dec_decode_ctl.scala 364:12] - i0_dp_raw.pc <= i0_dec.io.out.pc @[dec_decode_ctl.scala 364:12] - i0_dp_raw.imm20 <= i0_dec.io.out.imm20 @[dec_decode_ctl.scala 364:12] - i0_dp_raw.shimm5 <= i0_dec.io.out.shimm5 @[dec_decode_ctl.scala 364:12] - i0_dp_raw.rd <= i0_dec.io.out.rd @[dec_decode_ctl.scala 364:12] - i0_dp_raw.imm12 <= i0_dec.io.out.imm12 @[dec_decode_ctl.scala 364:12] - i0_dp_raw.rs2 <= i0_dec.io.out.rs2 @[dec_decode_ctl.scala 364:12] - i0_dp_raw.rs1 <= i0_dec.io.out.rs1 @[dec_decode_ctl.scala 364:12] - i0_dp_raw.alu <= i0_dec.io.out.alu @[dec_decode_ctl.scala 364:12] - reg _T_279 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 366:45] - _T_279 <= io.lsu_idle_any @[dec_decode_ctl.scala 366:45] - lsu_idle <= _T_279 @[dec_decode_ctl.scala 366:11] - node _T_280 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 369:73] - node _T_281 = and(leak1_i1_stall, _T_280) @[dec_decode_ctl.scala 369:71] - node _T_282 = or(io.dec_tlu_flush_leak_one_r, _T_281) @[dec_decode_ctl.scala 369:53] - leak1_i1_stall_in <= _T_282 @[dec_decode_ctl.scala 369:21] - reg _T_283 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 370:56] - _T_283 <= leak1_i1_stall_in @[dec_decode_ctl.scala 370:56] - leak1_i1_stall <= _T_283 @[dec_decode_ctl.scala 370:21] - leak1_mode <= leak1_i1_stall @[dec_decode_ctl.scala 371:14] - node _T_284 = and(io.dec_aln.dec_i0_decode_d, leak1_i1_stall) @[dec_decode_ctl.scala 372:53] - node _T_285 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 372:91] - node _T_286 = and(leak1_i0_stall, _T_285) @[dec_decode_ctl.scala 372:89] - node _T_287 = or(_T_284, _T_286) @[dec_decode_ctl.scala 372:71] - leak1_i0_stall_in <= _T_287 @[dec_decode_ctl.scala 372:21] - reg _T_288 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 373:56] - _T_288 <= leak1_i0_stall_in @[dec_decode_ctl.scala 373:56] - leak1_i0_stall <= _T_288 @[dec_decode_ctl.scala 373:21] - node _T_289 = bits(io.dec_i0_instr_d, 31, 31) @[dec_decode_ctl.scala 377:29] - node _T_290 = bits(io.dec_i0_instr_d, 19, 12) @[dec_decode_ctl.scala 377:36] - node _T_291 = bits(io.dec_i0_instr_d, 20, 20) @[dec_decode_ctl.scala 377:46] - node _T_292 = bits(io.dec_i0_instr_d, 30, 21) @[dec_decode_ctl.scala 377:53] + i0_dec.io.ins <= io.dec_i0_instr_d @[dec_decode_ctl.scala 357:16] + i0_dp_raw.legal <= i0_dec.io.out.legal @[dec_decode_ctl.scala 358:12] + i0_dp_raw.pm_alu <= i0_dec.io.out.pm_alu @[dec_decode_ctl.scala 358:12] + i0_dp_raw.fence_i <= i0_dec.io.out.fence_i @[dec_decode_ctl.scala 358:12] + i0_dp_raw.fence <= i0_dec.io.out.fence @[dec_decode_ctl.scala 358:12] + i0_dp_raw.rem <= i0_dec.io.out.rem @[dec_decode_ctl.scala 358:12] + i0_dp_raw.div <= i0_dec.io.out.div @[dec_decode_ctl.scala 358:12] + i0_dp_raw.low <= i0_dec.io.out.low @[dec_decode_ctl.scala 358:12] + i0_dp_raw.rs2_sign <= i0_dec.io.out.rs2_sign @[dec_decode_ctl.scala 358:12] + i0_dp_raw.rs1_sign <= i0_dec.io.out.rs1_sign @[dec_decode_ctl.scala 358:12] + i0_dp_raw.mul <= i0_dec.io.out.mul @[dec_decode_ctl.scala 358:12] + i0_dp_raw.mret <= i0_dec.io.out.mret @[dec_decode_ctl.scala 358:12] + i0_dp_raw.ecall <= i0_dec.io.out.ecall @[dec_decode_ctl.scala 358:12] + i0_dp_raw.ebreak <= i0_dec.io.out.ebreak @[dec_decode_ctl.scala 358:12] + i0_dp_raw.postsync <= i0_dec.io.out.postsync @[dec_decode_ctl.scala 358:12] + i0_dp_raw.presync <= i0_dec.io.out.presync @[dec_decode_ctl.scala 358:12] + i0_dp_raw.csr_imm <= i0_dec.io.out.csr_imm @[dec_decode_ctl.scala 358:12] + i0_dp_raw.csr_write <= i0_dec.io.out.csr_write @[dec_decode_ctl.scala 358:12] + i0_dp_raw.csr_set <= i0_dec.io.out.csr_set @[dec_decode_ctl.scala 358:12] + i0_dp_raw.csr_clr <= i0_dec.io.out.csr_clr @[dec_decode_ctl.scala 358:12] + i0_dp_raw.csr_read <= i0_dec.io.out.csr_read @[dec_decode_ctl.scala 358:12] + i0_dp_raw.word <= i0_dec.io.out.word @[dec_decode_ctl.scala 358:12] + i0_dp_raw.half <= i0_dec.io.out.half @[dec_decode_ctl.scala 358:12] + i0_dp_raw.by <= i0_dec.io.out.by @[dec_decode_ctl.scala 358:12] + i0_dp_raw.jal <= i0_dec.io.out.jal @[dec_decode_ctl.scala 358:12] + i0_dp_raw.blt <= i0_dec.io.out.blt @[dec_decode_ctl.scala 358:12] + i0_dp_raw.bge <= i0_dec.io.out.bge @[dec_decode_ctl.scala 358:12] + i0_dp_raw.bne <= i0_dec.io.out.bne @[dec_decode_ctl.scala 358:12] + i0_dp_raw.beq <= i0_dec.io.out.beq @[dec_decode_ctl.scala 358:12] + i0_dp_raw.condbr <= i0_dec.io.out.condbr @[dec_decode_ctl.scala 358:12] + i0_dp_raw.unsign <= i0_dec.io.out.unsign @[dec_decode_ctl.scala 358:12] + i0_dp_raw.slt <= i0_dec.io.out.slt @[dec_decode_ctl.scala 358:12] + i0_dp_raw.srl <= i0_dec.io.out.srl @[dec_decode_ctl.scala 358:12] + i0_dp_raw.sra <= i0_dec.io.out.sra @[dec_decode_ctl.scala 358:12] + i0_dp_raw.sll <= i0_dec.io.out.sll @[dec_decode_ctl.scala 358:12] + i0_dp_raw.lxor <= i0_dec.io.out.lxor @[dec_decode_ctl.scala 358:12] + i0_dp_raw.lor <= i0_dec.io.out.lor @[dec_decode_ctl.scala 358:12] + i0_dp_raw.land <= i0_dec.io.out.land @[dec_decode_ctl.scala 358:12] + i0_dp_raw.sub <= i0_dec.io.out.sub @[dec_decode_ctl.scala 358:12] + i0_dp_raw.add <= i0_dec.io.out.add @[dec_decode_ctl.scala 358:12] + i0_dp_raw.lsu <= i0_dec.io.out.lsu @[dec_decode_ctl.scala 358:12] + i0_dp_raw.store <= i0_dec.io.out.store @[dec_decode_ctl.scala 358:12] + i0_dp_raw.load <= i0_dec.io.out.load @[dec_decode_ctl.scala 358:12] + i0_dp_raw.pc <= i0_dec.io.out.pc @[dec_decode_ctl.scala 358:12] + i0_dp_raw.imm20 <= i0_dec.io.out.imm20 @[dec_decode_ctl.scala 358:12] + i0_dp_raw.shimm5 <= i0_dec.io.out.shimm5 @[dec_decode_ctl.scala 358:12] + i0_dp_raw.rd <= i0_dec.io.out.rd @[dec_decode_ctl.scala 358:12] + i0_dp_raw.imm12 <= i0_dec.io.out.imm12 @[dec_decode_ctl.scala 358:12] + i0_dp_raw.rs2 <= i0_dec.io.out.rs2 @[dec_decode_ctl.scala 358:12] + i0_dp_raw.rs1 <= i0_dec.io.out.rs1 @[dec_decode_ctl.scala 358:12] + i0_dp_raw.alu <= i0_dec.io.out.alu @[dec_decode_ctl.scala 358:12] + reg _T_279 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 360:45] + _T_279 <= io.lsu_idle_any @[dec_decode_ctl.scala 360:45] + lsu_idle <= _T_279 @[dec_decode_ctl.scala 360:11] + node _T_280 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 363:73] + node _T_281 = and(leak1_i1_stall, _T_280) @[dec_decode_ctl.scala 363:71] + node _T_282 = or(io.dec_tlu_flush_leak_one_r, _T_281) @[dec_decode_ctl.scala 363:53] + leak1_i1_stall_in <= _T_282 @[dec_decode_ctl.scala 363:21] + reg _T_283 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 364:56] + _T_283 <= leak1_i1_stall_in @[dec_decode_ctl.scala 364:56] + leak1_i1_stall <= _T_283 @[dec_decode_ctl.scala 364:21] + leak1_mode <= leak1_i1_stall @[dec_decode_ctl.scala 365:14] + node _T_284 = and(io.dec_aln.dec_i0_decode_d, leak1_i1_stall) @[dec_decode_ctl.scala 366:53] + node _T_285 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 366:91] + node _T_286 = and(leak1_i0_stall, _T_285) @[dec_decode_ctl.scala 366:89] + node _T_287 = or(_T_284, _T_286) @[dec_decode_ctl.scala 366:71] + leak1_i0_stall_in <= _T_287 @[dec_decode_ctl.scala 366:21] + reg _T_288 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 367:56] + _T_288 <= leak1_i0_stall_in @[dec_decode_ctl.scala 367:56] + leak1_i0_stall <= _T_288 @[dec_decode_ctl.scala 367:21] + node _T_289 = bits(io.dec_i0_instr_d, 31, 31) @[dec_decode_ctl.scala 371:29] + node _T_290 = bits(io.dec_i0_instr_d, 19, 12) @[dec_decode_ctl.scala 371:36] + node _T_291 = bits(io.dec_i0_instr_d, 20, 20) @[dec_decode_ctl.scala 371:46] + node _T_292 = bits(io.dec_i0_instr_d, 30, 21) @[dec_decode_ctl.scala 371:53] node _T_293 = cat(_T_291, _T_292) @[Cat.scala 29:58] node _T_294 = cat(_T_289, _T_290) @[Cat.scala 29:58] node i0_pcall_imm = cat(_T_294, _T_293) @[Cat.scala 29:58] - node _T_295 = bits(i0_pcall_imm, 11, 11) @[dec_decode_ctl.scala 378:46] - node _T_296 = bits(_T_295, 0, 0) @[dec_decode_ctl.scala 378:51] - node _T_297 = bits(i0_pcall_imm, 19, 12) @[dec_decode_ctl.scala 378:71] - node _T_298 = eq(_T_297, UInt<8>("h0ff")) @[dec_decode_ctl.scala 378:79] - node _T_299 = bits(i0_pcall_imm, 19, 12) @[dec_decode_ctl.scala 378:104] - node _T_300 = eq(_T_299, UInt<8>("h00")) @[dec_decode_ctl.scala 378:112] - node i0_pcall_12b_offset = mux(_T_296, _T_298, _T_300) @[dec_decode_ctl.scala 378:33] - node _T_301 = and(i0_pcall_12b_offset, i0_dp_raw.imm20) @[dec_decode_ctl.scala 379:47] - node _T_302 = eq(i0r.rd, UInt<5>("h01")) @[dec_decode_ctl.scala 379:76] - node _T_303 = eq(i0r.rd, UInt<5>("h05")) @[dec_decode_ctl.scala 379:98] - node _T_304 = or(_T_302, _T_303) @[dec_decode_ctl.scala 379:89] - node i0_pcall_case = and(_T_301, _T_304) @[dec_decode_ctl.scala 379:65] - node _T_305 = and(i0_pcall_12b_offset, i0_dp_raw.imm20) @[dec_decode_ctl.scala 380:47] - node _T_306 = eq(i0r.rd, UInt<5>("h01")) @[dec_decode_ctl.scala 380:76] - node _T_307 = eq(i0r.rd, UInt<5>("h05")) @[dec_decode_ctl.scala 380:98] - node _T_308 = or(_T_306, _T_307) @[dec_decode_ctl.scala 380:89] - node _T_309 = eq(_T_308, UInt<1>("h00")) @[dec_decode_ctl.scala 380:67] - node i0_pja_case = and(_T_305, _T_309) @[dec_decode_ctl.scala 380:65] - node _T_310 = and(i0_dp_raw.jal, i0_pcall_case) @[dec_decode_ctl.scala 381:38] - i0_pcall_raw <= _T_310 @[dec_decode_ctl.scala 381:20] - node _T_311 = and(i0_dp.jal, i0_pcall_case) @[dec_decode_ctl.scala 382:38] - i0_pcall <= _T_311 @[dec_decode_ctl.scala 382:20] - node _T_312 = and(i0_dp_raw.jal, i0_pja_case) @[dec_decode_ctl.scala 383:38] - i0_pja_raw <= _T_312 @[dec_decode_ctl.scala 383:20] - node _T_313 = and(i0_dp.jal, i0_pja_case) @[dec_decode_ctl.scala 384:38] - i0_pja <= _T_313 @[dec_decode_ctl.scala 384:20] - node _T_314 = or(i0_pcall_raw, i0_pja_raw) @[dec_decode_ctl.scala 385:41] - node _T_315 = bits(_T_314, 0, 0) @[dec_decode_ctl.scala 385:55] - node _T_316 = bits(i0_pcall_imm, 11, 0) @[dec_decode_ctl.scala 385:75] - node _T_317 = bits(io.dec_i0_instr_d, 31, 31) @[dec_decode_ctl.scala 385:90] - node _T_318 = bits(io.dec_i0_instr_d, 7, 7) @[dec_decode_ctl.scala 385:97] - node _T_319 = bits(io.dec_i0_instr_d, 30, 25) @[dec_decode_ctl.scala 385:103] - node _T_320 = bits(io.dec_i0_instr_d, 11, 8) @[dec_decode_ctl.scala 385:113] + node _T_295 = bits(i0_pcall_imm, 11, 11) @[dec_decode_ctl.scala 372:46] + node _T_296 = bits(_T_295, 0, 0) @[dec_decode_ctl.scala 372:51] + node _T_297 = bits(i0_pcall_imm, 19, 12) @[dec_decode_ctl.scala 372:71] + node _T_298 = eq(_T_297, UInt<8>("h0ff")) @[dec_decode_ctl.scala 372:79] + node _T_299 = bits(i0_pcall_imm, 19, 12) @[dec_decode_ctl.scala 372:104] + node _T_300 = eq(_T_299, UInt<8>("h00")) @[dec_decode_ctl.scala 372:112] + node i0_pcall_12b_offset = mux(_T_296, _T_298, _T_300) @[dec_decode_ctl.scala 372:33] + node _T_301 = and(i0_pcall_12b_offset, i0_dp_raw.imm20) @[dec_decode_ctl.scala 373:47] + node _T_302 = eq(i0r.rd, UInt<5>("h01")) @[dec_decode_ctl.scala 373:76] + node _T_303 = eq(i0r.rd, UInt<5>("h05")) @[dec_decode_ctl.scala 373:98] + node _T_304 = or(_T_302, _T_303) @[dec_decode_ctl.scala 373:89] + node i0_pcall_case = and(_T_301, _T_304) @[dec_decode_ctl.scala 373:65] + node _T_305 = and(i0_pcall_12b_offset, i0_dp_raw.imm20) @[dec_decode_ctl.scala 374:47] + node _T_306 = eq(i0r.rd, UInt<5>("h01")) @[dec_decode_ctl.scala 374:76] + node _T_307 = eq(i0r.rd, UInt<5>("h05")) @[dec_decode_ctl.scala 374:98] + node _T_308 = or(_T_306, _T_307) @[dec_decode_ctl.scala 374:89] + node _T_309 = eq(_T_308, UInt<1>("h00")) @[dec_decode_ctl.scala 374:67] + node i0_pja_case = and(_T_305, _T_309) @[dec_decode_ctl.scala 374:65] + node _T_310 = and(i0_dp_raw.jal, i0_pcall_case) @[dec_decode_ctl.scala 375:38] + i0_pcall_raw <= _T_310 @[dec_decode_ctl.scala 375:20] + node _T_311 = and(i0_dp.jal, i0_pcall_case) @[dec_decode_ctl.scala 376:38] + i0_pcall <= _T_311 @[dec_decode_ctl.scala 376:20] + node _T_312 = and(i0_dp_raw.jal, i0_pja_case) @[dec_decode_ctl.scala 377:38] + i0_pja_raw <= _T_312 @[dec_decode_ctl.scala 377:20] + node _T_313 = and(i0_dp.jal, i0_pja_case) @[dec_decode_ctl.scala 378:38] + i0_pja <= _T_313 @[dec_decode_ctl.scala 378:20] + node _T_314 = or(i0_pcall_raw, i0_pja_raw) @[dec_decode_ctl.scala 379:41] + node _T_315 = bits(_T_314, 0, 0) @[dec_decode_ctl.scala 379:55] + node _T_316 = bits(i0_pcall_imm, 11, 0) @[dec_decode_ctl.scala 379:75] + node _T_317 = bits(io.dec_i0_instr_d, 31, 31) @[dec_decode_ctl.scala 379:90] + node _T_318 = bits(io.dec_i0_instr_d, 7, 7) @[dec_decode_ctl.scala 379:97] + node _T_319 = bits(io.dec_i0_instr_d, 30, 25) @[dec_decode_ctl.scala 379:103] + node _T_320 = bits(io.dec_i0_instr_d, 11, 8) @[dec_decode_ctl.scala 379:113] node _T_321 = cat(_T_319, _T_320) @[Cat.scala 29:58] node _T_322 = cat(_T_317, _T_318) @[Cat.scala 29:58] node _T_323 = cat(_T_322, _T_321) @[Cat.scala 29:58] - node _T_324 = mux(_T_315, _T_316, _T_323) @[dec_decode_ctl.scala 385:26] - i0_br_offset <= _T_324 @[dec_decode_ctl.scala 385:20] - node _T_325 = and(i0_dp_raw.jal, i0_dp_raw.imm12) @[dec_decode_ctl.scala 387:37] - node _T_326 = eq(i0r.rd, UInt<5>("h00")) @[dec_decode_ctl.scala 387:65] - node _T_327 = and(_T_325, _T_326) @[dec_decode_ctl.scala 387:55] - node _T_328 = eq(i0r.rs1, UInt<5>("h01")) @[dec_decode_ctl.scala 387:89] - node _T_329 = eq(i0r.rs1, UInt<5>("h05")) @[dec_decode_ctl.scala 387:111] - node _T_330 = or(_T_328, _T_329) @[dec_decode_ctl.scala 387:101] - node i0_pret_case = and(_T_327, _T_330) @[dec_decode_ctl.scala 387:79] - node _T_331 = and(i0_dp_raw.jal, i0_pret_case) @[dec_decode_ctl.scala 388:32] - i0_pret_raw <= _T_331 @[dec_decode_ctl.scala 388:15] - node _T_332 = and(i0_dp.jal, i0_pret_case) @[dec_decode_ctl.scala 389:32] - i0_pret <= _T_332 @[dec_decode_ctl.scala 389:15] - node _T_333 = eq(i0_pcall_case, UInt<1>("h00")) @[dec_decode_ctl.scala 390:35] - node _T_334 = and(i0_dp.jal, _T_333) @[dec_decode_ctl.scala 390:32] - node _T_335 = eq(i0_pja_case, UInt<1>("h00")) @[dec_decode_ctl.scala 390:52] - node _T_336 = and(_T_334, _T_335) @[dec_decode_ctl.scala 390:50] - node _T_337 = eq(i0_pret_case, UInt<1>("h00")) @[dec_decode_ctl.scala 390:67] - node _T_338 = and(_T_336, _T_337) @[dec_decode_ctl.scala 390:65] - i0_jal <= _T_338 @[dec_decode_ctl.scala 390:15] - io.dec_div.div_p.valid <= div_decode_d @[dec_decode_ctl.scala 393:29] - io.dec_div.div_p.bits.unsign <= i0_dp.unsign @[dec_decode_ctl.scala 394:34] - io.dec_div.div_p.bits.rem <= i0_dp.rem @[dec_decode_ctl.scala 395:34] - io.decode_exu.mul_p.valid <= mul_decode_d @[dec_decode_ctl.scala 397:32] - io.decode_exu.mul_p.bits.rs1_sign <= i0_dp.rs1_sign @[dec_decode_ctl.scala 398:37] - io.decode_exu.mul_p.bits.rs2_sign <= i0_dp.rs2_sign @[dec_decode_ctl.scala 399:37] - io.decode_exu.mul_p.bits.low <= i0_dp.low @[dec_decode_ctl.scala 400:37] - reg _T_339 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 402:69] - _T_339 <= io.dec_tlu_flush_extint @[dec_decode_ctl.scala 402:69] - io.decode_exu.dec_extint_stall <= _T_339 @[dec_decode_ctl.scala 402:34] - wire _T_340 : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[dec_decode_ctl.scala 404:27] - _T_340.bits.store_data_bypass_m <= UInt<1>("h00") @[dec_decode_ctl.scala 404:27] - _T_340.bits.load_ldst_bypass_d <= UInt<1>("h00") @[dec_decode_ctl.scala 404:27] - _T_340.bits.store_data_bypass_d <= UInt<1>("h00") @[dec_decode_ctl.scala 404:27] - _T_340.bits.dma <= UInt<1>("h00") @[dec_decode_ctl.scala 404:27] - _T_340.bits.unsign <= UInt<1>("h00") @[dec_decode_ctl.scala 404:27] - _T_340.bits.store <= UInt<1>("h00") @[dec_decode_ctl.scala 404:27] - _T_340.bits.load <= UInt<1>("h00") @[dec_decode_ctl.scala 404:27] - _T_340.bits.dword <= UInt<1>("h00") @[dec_decode_ctl.scala 404:27] - _T_340.bits.word <= UInt<1>("h00") @[dec_decode_ctl.scala 404:27] - _T_340.bits.half <= UInt<1>("h00") @[dec_decode_ctl.scala 404:27] - _T_340.bits.by <= UInt<1>("h00") @[dec_decode_ctl.scala 404:27] - _T_340.bits.fast_int <= UInt<1>("h00") @[dec_decode_ctl.scala 404:27] - _T_340.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 404:27] - io.lsu_p.bits.store_data_bypass_m <= _T_340.bits.store_data_bypass_m @[dec_decode_ctl.scala 404:12] - io.lsu_p.bits.load_ldst_bypass_d <= _T_340.bits.load_ldst_bypass_d @[dec_decode_ctl.scala 404:12] - io.lsu_p.bits.store_data_bypass_d <= _T_340.bits.store_data_bypass_d @[dec_decode_ctl.scala 404:12] - io.lsu_p.bits.dma <= _T_340.bits.dma @[dec_decode_ctl.scala 404:12] - io.lsu_p.bits.unsign <= _T_340.bits.unsign @[dec_decode_ctl.scala 404:12] - io.lsu_p.bits.store <= _T_340.bits.store @[dec_decode_ctl.scala 404:12] - io.lsu_p.bits.load <= _T_340.bits.load @[dec_decode_ctl.scala 404:12] - io.lsu_p.bits.dword <= _T_340.bits.dword @[dec_decode_ctl.scala 404:12] - io.lsu_p.bits.word <= _T_340.bits.word @[dec_decode_ctl.scala 404:12] - io.lsu_p.bits.half <= _T_340.bits.half @[dec_decode_ctl.scala 404:12] - io.lsu_p.bits.by <= _T_340.bits.by @[dec_decode_ctl.scala 404:12] - io.lsu_p.bits.fast_int <= _T_340.bits.fast_int @[dec_decode_ctl.scala 404:12] - io.lsu_p.valid <= _T_340.valid @[dec_decode_ctl.scala 404:12] - when io.decode_exu.dec_extint_stall : @[dec_decode_ctl.scala 405:40] - io.lsu_p.bits.load <= UInt<1>("h01") @[dec_decode_ctl.scala 406:29] - io.lsu_p.bits.word <= UInt<1>("h01") @[dec_decode_ctl.scala 407:29] - io.lsu_p.bits.fast_int <= UInt<1>("h01") @[dec_decode_ctl.scala 408:29] - io.lsu_p.valid <= UInt<1>("h01") @[dec_decode_ctl.scala 409:24] - skip @[dec_decode_ctl.scala 405:40] - else : @[dec_decode_ctl.scala 410:15] - io.lsu_p.valid <= lsu_decode_d @[dec_decode_ctl.scala 411:35] - io.lsu_p.bits.load <= i0_dp.load @[dec_decode_ctl.scala 412:40] - io.lsu_p.bits.store <= i0_dp.store @[dec_decode_ctl.scala 413:40] - io.lsu_p.bits.by <= i0_dp.by @[dec_decode_ctl.scala 414:40] - io.lsu_p.bits.half <= i0_dp.half @[dec_decode_ctl.scala 415:40] - io.lsu_p.bits.word <= i0_dp.word @[dec_decode_ctl.scala 416:40] - io.lsu_p.bits.load_ldst_bypass_d <= load_ldst_bypass_d @[dec_decode_ctl.scala 417:40] - io.lsu_p.bits.store_data_bypass_d <= store_data_bypass_d @[dec_decode_ctl.scala 418:40] - io.lsu_p.bits.store_data_bypass_m <= store_data_bypass_m @[dec_decode_ctl.scala 419:40] - io.lsu_p.bits.unsign <= i0_dp.unsign @[dec_decode_ctl.scala 420:40] - skip @[dec_decode_ctl.scala 410:15] - io.dec_alu.dec_csr_ren_d <= i0_dp.csr_read @[dec_decode_ctl.scala 424:29] - node _T_341 = bits(i0_legal_decode_d, 0, 0) @[dec_decode_ctl.scala 425:56] - node _T_342 = and(i0_dp.csr_read, _T_341) @[dec_decode_ctl.scala 425:36] - csr_read <= _T_342 @[dec_decode_ctl.scala 425:18] - node _T_343 = eq(io.dec_debug_fence_d, UInt<1>("h00")) @[dec_decode_ctl.scala 427:42] - node i0_csr_write = and(i0_dp.csr_write, _T_343) @[dec_decode_ctl.scala 427:40] - node _T_344 = bits(i0_legal_decode_d, 0, 0) @[dec_decode_ctl.scala 428:61] - node csr_clr_d = and(i0_dp.csr_clr, _T_344) @[dec_decode_ctl.scala 428:41] - node _T_345 = bits(i0_legal_decode_d, 0, 0) @[dec_decode_ctl.scala 429:59] - node csr_set_d = and(i0_dp.csr_set, _T_345) @[dec_decode_ctl.scala 429:39] - node _T_346 = bits(i0_legal_decode_d, 0, 0) @[dec_decode_ctl.scala 430:59] - node csr_write_d = and(i0_csr_write, _T_346) @[dec_decode_ctl.scala 430:39] - node _T_347 = eq(i0_dp.csr_read, UInt<1>("h00")) @[dec_decode_ctl.scala 432:41] - node _T_348 = and(i0_csr_write, _T_347) @[dec_decode_ctl.scala 432:39] - i0_csr_write_only_d <= _T_348 @[dec_decode_ctl.scala 432:23] - node _T_349 = or(i0_dp.csr_clr, i0_dp.csr_set) @[dec_decode_ctl.scala 433:42] - node _T_350 = or(_T_349, i0_csr_write) @[dec_decode_ctl.scala 433:58] - io.dec_csr_wen_unq_d <= _T_350 @[dec_decode_ctl.scala 433:24] - node _T_351 = bits(io.dec_i0_instr_d, 31, 20) @[dec_decode_ctl.scala 436:30] - io.dec_csr_rdaddr_d <= _T_351 @[dec_decode_ctl.scala 436:24] - io.dec_csr_wraddr_r <= r_d.bits.csrwaddr @[dec_decode_ctl.scala 437:23] - node _T_352 = and(r_d.bits.csrwen, r_d.valid) @[dec_decode_ctl.scala 441:39] - node _T_353 = eq(io.dec_tlu_i0_kill_writeb_r, UInt<1>("h00")) @[dec_decode_ctl.scala 441:53] - node _T_354 = and(_T_352, _T_353) @[dec_decode_ctl.scala 441:51] - io.dec_csr_wen_r <= _T_354 @[dec_decode_ctl.scala 441:20] - node _T_355 = eq(r_d.bits.csrwaddr, UInt<10>("h0300")) @[dec_decode_ctl.scala 444:50] - node _T_356 = eq(r_d.bits.csrwaddr, UInt<10>("h0304")) @[dec_decode_ctl.scala 444:85] - node _T_357 = or(_T_355, _T_356) @[dec_decode_ctl.scala 444:64] - node _T_358 = and(_T_357, r_d.bits.csrwen) @[dec_decode_ctl.scala 444:100] - node _T_359 = and(_T_358, r_d.valid) @[dec_decode_ctl.scala 444:118] - node _T_360 = eq(io.dec_tlu_i0_kill_writeb_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 444:132] - node _T_361 = and(_T_359, _T_360) @[dec_decode_ctl.scala 444:130] - io.dec_csr_stall_int_ff <= _T_361 @[dec_decode_ctl.scala 444:27] - reg csr_read_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 446:52] - csr_read_x <= csr_read @[dec_decode_ctl.scala 446:52] - reg csr_clr_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 447:51] - csr_clr_x <= csr_clr_d @[dec_decode_ctl.scala 447:51] - reg csr_set_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 448:51] - csr_set_x <= csr_set_d @[dec_decode_ctl.scala 448:51] - reg csr_write_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 449:53] - csr_write_x <= csr_write_d @[dec_decode_ctl.scala 449:53] - reg csr_imm_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 450:51] - csr_imm_x <= i0_dp.csr_imm @[dec_decode_ctl.scala 450:51] - node _T_362 = bits(io.dec_i0_instr_d, 19, 15) @[dec_decode_ctl.scala 453:27] - node _T_363 = bits(i0_x_data_en, 0, 0) @[dec_decode_ctl.scala 453:48] + node _T_324 = mux(_T_315, _T_316, _T_323) @[dec_decode_ctl.scala 379:26] + i0_br_offset <= _T_324 @[dec_decode_ctl.scala 379:20] + node _T_325 = and(i0_dp_raw.jal, i0_dp_raw.imm12) @[dec_decode_ctl.scala 381:37] + node _T_326 = eq(i0r.rd, UInt<5>("h00")) @[dec_decode_ctl.scala 381:65] + node _T_327 = and(_T_325, _T_326) @[dec_decode_ctl.scala 381:55] + node _T_328 = eq(i0r.rs1, UInt<5>("h01")) @[dec_decode_ctl.scala 381:89] + node _T_329 = eq(i0r.rs1, UInt<5>("h05")) @[dec_decode_ctl.scala 381:111] + node _T_330 = or(_T_328, _T_329) @[dec_decode_ctl.scala 381:101] + node i0_pret_case = and(_T_327, _T_330) @[dec_decode_ctl.scala 381:79] + node _T_331 = and(i0_dp_raw.jal, i0_pret_case) @[dec_decode_ctl.scala 382:32] + i0_pret_raw <= _T_331 @[dec_decode_ctl.scala 382:15] + node _T_332 = and(i0_dp.jal, i0_pret_case) @[dec_decode_ctl.scala 383:32] + i0_pret <= _T_332 @[dec_decode_ctl.scala 383:15] + node _T_333 = eq(i0_pcall_case, UInt<1>("h00")) @[dec_decode_ctl.scala 384:35] + node _T_334 = and(i0_dp.jal, _T_333) @[dec_decode_ctl.scala 384:32] + node _T_335 = eq(i0_pja_case, UInt<1>("h00")) @[dec_decode_ctl.scala 384:52] + node _T_336 = and(_T_334, _T_335) @[dec_decode_ctl.scala 384:50] + node _T_337 = eq(i0_pret_case, UInt<1>("h00")) @[dec_decode_ctl.scala 384:67] + node _T_338 = and(_T_336, _T_337) @[dec_decode_ctl.scala 384:65] + i0_jal <= _T_338 @[dec_decode_ctl.scala 384:15] + io.dec_div.div_p.valid <= div_decode_d @[dec_decode_ctl.scala 387:29] + io.dec_div.div_p.bits.unsign <= i0_dp.unsign @[dec_decode_ctl.scala 388:34] + io.dec_div.div_p.bits.rem <= i0_dp.rem @[dec_decode_ctl.scala 389:34] + io.decode_exu.mul_p.valid <= mul_decode_d @[dec_decode_ctl.scala 391:32] + io.decode_exu.mul_p.bits.rs1_sign <= i0_dp.rs1_sign @[dec_decode_ctl.scala 392:37] + io.decode_exu.mul_p.bits.rs2_sign <= i0_dp.rs2_sign @[dec_decode_ctl.scala 393:37] + io.decode_exu.mul_p.bits.low <= i0_dp.low @[dec_decode_ctl.scala 394:37] + reg _T_339 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 396:69] + _T_339 <= io.dec_tlu_flush_extint @[dec_decode_ctl.scala 396:69] + io.decode_exu.dec_extint_stall <= _T_339 @[dec_decode_ctl.scala 396:34] + wire _T_340 : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[dec_decode_ctl.scala 398:27] + _T_340.bits.store_data_bypass_m <= UInt<1>("h00") @[dec_decode_ctl.scala 398:27] + _T_340.bits.load_ldst_bypass_d <= UInt<1>("h00") @[dec_decode_ctl.scala 398:27] + _T_340.bits.store_data_bypass_d <= UInt<1>("h00") @[dec_decode_ctl.scala 398:27] + _T_340.bits.dma <= UInt<1>("h00") @[dec_decode_ctl.scala 398:27] + _T_340.bits.unsign <= UInt<1>("h00") @[dec_decode_ctl.scala 398:27] + _T_340.bits.store <= UInt<1>("h00") @[dec_decode_ctl.scala 398:27] + _T_340.bits.load <= UInt<1>("h00") @[dec_decode_ctl.scala 398:27] + _T_340.bits.dword <= UInt<1>("h00") @[dec_decode_ctl.scala 398:27] + _T_340.bits.word <= UInt<1>("h00") @[dec_decode_ctl.scala 398:27] + _T_340.bits.half <= UInt<1>("h00") @[dec_decode_ctl.scala 398:27] + _T_340.bits.by <= UInt<1>("h00") @[dec_decode_ctl.scala 398:27] + _T_340.bits.fast_int <= UInt<1>("h00") @[dec_decode_ctl.scala 398:27] + _T_340.valid <= UInt<1>("h00") @[dec_decode_ctl.scala 398:27] + io.lsu_p.bits.store_data_bypass_m <= _T_340.bits.store_data_bypass_m @[dec_decode_ctl.scala 398:12] + io.lsu_p.bits.load_ldst_bypass_d <= _T_340.bits.load_ldst_bypass_d @[dec_decode_ctl.scala 398:12] + io.lsu_p.bits.store_data_bypass_d <= _T_340.bits.store_data_bypass_d @[dec_decode_ctl.scala 398:12] + io.lsu_p.bits.dma <= _T_340.bits.dma @[dec_decode_ctl.scala 398:12] + io.lsu_p.bits.unsign <= _T_340.bits.unsign @[dec_decode_ctl.scala 398:12] + io.lsu_p.bits.store <= _T_340.bits.store @[dec_decode_ctl.scala 398:12] + io.lsu_p.bits.load <= _T_340.bits.load @[dec_decode_ctl.scala 398:12] + io.lsu_p.bits.dword <= _T_340.bits.dword @[dec_decode_ctl.scala 398:12] + io.lsu_p.bits.word <= _T_340.bits.word @[dec_decode_ctl.scala 398:12] + io.lsu_p.bits.half <= _T_340.bits.half @[dec_decode_ctl.scala 398:12] + io.lsu_p.bits.by <= _T_340.bits.by @[dec_decode_ctl.scala 398:12] + io.lsu_p.bits.fast_int <= _T_340.bits.fast_int @[dec_decode_ctl.scala 398:12] + io.lsu_p.valid <= _T_340.valid @[dec_decode_ctl.scala 398:12] + when io.decode_exu.dec_extint_stall : @[dec_decode_ctl.scala 399:40] + io.lsu_p.bits.load <= UInt<1>("h01") @[dec_decode_ctl.scala 400:29] + io.lsu_p.bits.word <= UInt<1>("h01") @[dec_decode_ctl.scala 401:29] + io.lsu_p.bits.fast_int <= UInt<1>("h01") @[dec_decode_ctl.scala 402:29] + io.lsu_p.valid <= UInt<1>("h01") @[dec_decode_ctl.scala 403:24] + skip @[dec_decode_ctl.scala 399:40] + else : @[dec_decode_ctl.scala 404:15] + io.lsu_p.valid <= lsu_decode_d @[dec_decode_ctl.scala 405:35] + io.lsu_p.bits.load <= i0_dp.load @[dec_decode_ctl.scala 406:40] + io.lsu_p.bits.store <= i0_dp.store @[dec_decode_ctl.scala 407:40] + io.lsu_p.bits.by <= i0_dp.by @[dec_decode_ctl.scala 408:40] + io.lsu_p.bits.half <= i0_dp.half @[dec_decode_ctl.scala 409:40] + io.lsu_p.bits.word <= i0_dp.word @[dec_decode_ctl.scala 410:40] + io.lsu_p.bits.load_ldst_bypass_d <= load_ldst_bypass_d @[dec_decode_ctl.scala 411:40] + io.lsu_p.bits.store_data_bypass_d <= store_data_bypass_d @[dec_decode_ctl.scala 412:40] + io.lsu_p.bits.store_data_bypass_m <= store_data_bypass_m @[dec_decode_ctl.scala 413:40] + io.lsu_p.bits.unsign <= i0_dp.unsign @[dec_decode_ctl.scala 414:40] + skip @[dec_decode_ctl.scala 404:15] + io.dec_alu.dec_csr_ren_d <= i0_dp.csr_read @[dec_decode_ctl.scala 418:29] + node _T_341 = bits(i0_legal_decode_d, 0, 0) @[dec_decode_ctl.scala 419:56] + node _T_342 = and(i0_dp.csr_read, _T_341) @[dec_decode_ctl.scala 419:36] + csr_read <= _T_342 @[dec_decode_ctl.scala 419:18] + node _T_343 = eq(io.dec_debug_fence_d, UInt<1>("h00")) @[dec_decode_ctl.scala 421:42] + node i0_csr_write = and(i0_dp.csr_write, _T_343) @[dec_decode_ctl.scala 421:40] + node _T_344 = bits(i0_legal_decode_d, 0, 0) @[dec_decode_ctl.scala 422:61] + node csr_clr_d = and(i0_dp.csr_clr, _T_344) @[dec_decode_ctl.scala 422:41] + node _T_345 = bits(i0_legal_decode_d, 0, 0) @[dec_decode_ctl.scala 423:59] + node csr_set_d = and(i0_dp.csr_set, _T_345) @[dec_decode_ctl.scala 423:39] + node _T_346 = bits(i0_legal_decode_d, 0, 0) @[dec_decode_ctl.scala 424:59] + node csr_write_d = and(i0_csr_write, _T_346) @[dec_decode_ctl.scala 424:39] + node _T_347 = eq(i0_dp.csr_read, UInt<1>("h00")) @[dec_decode_ctl.scala 426:41] + node _T_348 = and(i0_csr_write, _T_347) @[dec_decode_ctl.scala 426:39] + i0_csr_write_only_d <= _T_348 @[dec_decode_ctl.scala 426:23] + node _T_349 = or(i0_dp.csr_clr, i0_dp.csr_set) @[dec_decode_ctl.scala 427:42] + node _T_350 = or(_T_349, i0_csr_write) @[dec_decode_ctl.scala 427:58] + io.dec_csr_wen_unq_d <= _T_350 @[dec_decode_ctl.scala 427:24] + node _T_351 = bits(io.dec_i0_instr_d, 31, 20) @[dec_decode_ctl.scala 430:30] + io.dec_csr_rdaddr_d <= _T_351 @[dec_decode_ctl.scala 430:24] + io.dec_csr_wraddr_r <= r_d.bits.csrwaddr @[dec_decode_ctl.scala 431:23] + node _T_352 = and(r_d.bits.csrwen, r_d.valid) @[dec_decode_ctl.scala 435:39] + node _T_353 = eq(io.dec_tlu_i0_kill_writeb_r, UInt<1>("h00")) @[dec_decode_ctl.scala 435:53] + node _T_354 = and(_T_352, _T_353) @[dec_decode_ctl.scala 435:51] + io.dec_csr_wen_r <= _T_354 @[dec_decode_ctl.scala 435:20] + node _T_355 = eq(r_d.bits.csrwaddr, UInt<10>("h0300")) @[dec_decode_ctl.scala 438:50] + node _T_356 = eq(r_d.bits.csrwaddr, UInt<10>("h0304")) @[dec_decode_ctl.scala 438:85] + node _T_357 = or(_T_355, _T_356) @[dec_decode_ctl.scala 438:64] + node _T_358 = and(_T_357, r_d.bits.csrwen) @[dec_decode_ctl.scala 438:100] + node _T_359 = and(_T_358, r_d.valid) @[dec_decode_ctl.scala 438:118] + node _T_360 = eq(io.dec_tlu_i0_kill_writeb_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 438:132] + node _T_361 = and(_T_359, _T_360) @[dec_decode_ctl.scala 438:130] + io.dec_csr_stall_int_ff <= _T_361 @[dec_decode_ctl.scala 438:27] + reg csr_read_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 440:52] + csr_read_x <= csr_read @[dec_decode_ctl.scala 440:52] + reg csr_clr_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 441:51] + csr_clr_x <= csr_clr_d @[dec_decode_ctl.scala 441:51] + reg csr_set_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 442:51] + csr_set_x <= csr_set_d @[dec_decode_ctl.scala 442:51] + reg csr_write_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 443:53] + csr_write_x <= csr_write_d @[dec_decode_ctl.scala 443:53] + reg csr_imm_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 444:51] + csr_imm_x <= i0_dp.csr_imm @[dec_decode_ctl.scala 444:51] + node _T_362 = bits(io.dec_i0_instr_d, 19, 15) @[dec_decode_ctl.scala 447:27] + node _T_363 = bits(i0_x_data_en, 0, 0) @[dec_decode_ctl.scala 447:48] inst rvclkhdr_1 of rvclkhdr_662 @[lib.scala 368:23] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset @@ -67971,7 +67971,7 @@ circuit quasar_wrapper : rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg csrimm_x : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] csrimm_x <= _T_362 @[lib.scala 374:16] - node _T_364 = bits(i0_x_data_en, 0, 0) @[dec_decode_ctl.scala 454:62] + node _T_364 = bits(i0_x_data_en, 0, 0) @[dec_decode_ctl.scala 448:62] inst rvclkhdr_2 of rvclkhdr_663 @[lib.scala 368:23] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset @@ -67980,7 +67980,7 @@ circuit quasar_wrapper : rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg csr_rddata_x : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] csr_rddata_x <= io.dec_csr_rddata_d @[lib.scala 374:16] - node _T_365 = bits(csr_imm_x, 0, 0) @[dec_decode_ctl.scala 457:15] + node _T_365 = bits(csr_imm_x, 0, 0) @[dec_decode_ctl.scala 451:15] wire _T_366 : UInt<1>[27] @[lib.scala 12:48] _T_366[0] <= UInt<1>("h00") @[lib.scala 12:48] _T_366[1] <= UInt<1>("h00") @[lib.scala 12:48] @@ -68035,18 +68035,18 @@ circuit quasar_wrapper : node _T_390 = cat(_T_389, _T_366[24]) @[Cat.scala 29:58] node _T_391 = cat(_T_390, _T_366[25]) @[Cat.scala 29:58] node _T_392 = cat(_T_391, _T_366[26]) @[Cat.scala 29:58] - node _T_393 = bits(csrimm_x, 4, 0) @[dec_decode_ctl.scala 457:53] + node _T_393 = bits(csrimm_x, 4, 0) @[dec_decode_ctl.scala 451:53] node _T_394 = cat(_T_392, _T_393) @[Cat.scala 29:58] - node _T_395 = bits(csr_imm_x, 0, 0) @[dec_decode_ctl.scala 458:16] - node _T_396 = eq(_T_395, UInt<1>("h00")) @[dec_decode_ctl.scala 458:5] + node _T_395 = bits(csr_imm_x, 0, 0) @[dec_decode_ctl.scala 452:16] + node _T_396 = eq(_T_395, UInt<1>("h00")) @[dec_decode_ctl.scala 452:5] node _T_397 = mux(_T_365, _T_394, UInt<1>("h00")) @[Mux.scala 27:72] node _T_398 = mux(_T_396, io.decode_exu.exu_csr_rs1_x, UInt<1>("h00")) @[Mux.scala 27:72] node _T_399 = or(_T_397, _T_398) @[Mux.scala 27:72] wire csr_mask_x : UInt<32> @[Mux.scala 27:72] csr_mask_x <= _T_399 @[Mux.scala 27:72] - node _T_400 = not(csr_mask_x) @[dec_decode_ctl.scala 461:38] - node _T_401 = and(csr_rddata_x, _T_400) @[dec_decode_ctl.scala 461:35] - node _T_402 = or(csr_rddata_x, csr_mask_x) @[dec_decode_ctl.scala 462:35] + node _T_400 = not(csr_mask_x) @[dec_decode_ctl.scala 455:38] + node _T_401 = and(csr_rddata_x, _T_400) @[dec_decode_ctl.scala 455:35] + node _T_402 = or(csr_rddata_x, csr_mask_x) @[dec_decode_ctl.scala 456:35] node _T_403 = mux(csr_clr_x, _T_401, UInt<1>("h00")) @[Mux.scala 27:72] node _T_404 = mux(csr_set_x, _T_402, UInt<1>("h00")) @[Mux.scala 27:72] node _T_405 = mux(csr_write_x, csr_mask_x, UInt<1>("h00")) @[Mux.scala 27:72] @@ -68054,42 +68054,42 @@ circuit quasar_wrapper : node _T_407 = or(_T_406, _T_405) @[Mux.scala 27:72] wire write_csr_data_x : UInt @[Mux.scala 27:72] write_csr_data_x <= _T_407 @[Mux.scala 27:72] - node _T_408 = eq(io.dec_tlu_flush_pause_r, UInt<1>("h00")) @[dec_decode_ctl.scala 465:49] - node _T_409 = and(io.dec_tlu_flush_lower_r, _T_408) @[dec_decode_ctl.scala 465:47] + node _T_408 = eq(io.dec_tlu_flush_pause_r, UInt<1>("h00")) @[dec_decode_ctl.scala 459:49] + node _T_409 = and(io.dec_tlu_flush_lower_r, _T_408) @[dec_decode_ctl.scala 459:47] node _T_410 = mux(UInt<1>("h00"), UInt<31>("h07fffffff"), UInt<31>("h00")) @[Bitwise.scala 72:12] - node _T_411 = bits(write_csr_data, 0, 0) @[dec_decode_ctl.scala 465:145] + node _T_411 = bits(write_csr_data, 0, 0) @[dec_decode_ctl.scala 459:145] node _T_412 = cat(_T_410, _T_411) @[Cat.scala 29:58] - node _T_413 = eq(write_csr_data, _T_412) @[dec_decode_ctl.scala 465:109] - node _T_414 = and(pause_stall, _T_413) @[dec_decode_ctl.scala 465:91] - node clear_pause = or(_T_409, _T_414) @[dec_decode_ctl.scala 465:76] - node _T_415 = or(io.dec_tlu_wr_pause_r, pause_stall) @[dec_decode_ctl.scala 466:44] - node _T_416 = eq(clear_pause, UInt<1>("h00")) @[dec_decode_ctl.scala 466:61] - node _T_417 = and(_T_415, _T_416) @[dec_decode_ctl.scala 466:59] - pause_state_in <= _T_417 @[dec_decode_ctl.scala 466:18] - reg _T_418 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 467:50] - _T_418 <= pause_state_in @[dec_decode_ctl.scala 467:50] - pause_stall <= _T_418 @[dec_decode_ctl.scala 467:15] - io.dec_pause_state <= pause_stall @[dec_decode_ctl.scala 468:22] - reg _T_419 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 469:55] - _T_419 <= io.dec_tlu_wr_pause_r @[dec_decode_ctl.scala 469:55] - tlu_wr_pause_r1 <= _T_419 @[dec_decode_ctl.scala 469:19] - reg _T_420 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 470:55] - _T_420 <= tlu_wr_pause_r1 @[dec_decode_ctl.scala 470:55] - tlu_wr_pause_r2 <= _T_420 @[dec_decode_ctl.scala 470:19] - node _T_421 = eq(tlu_wr_pause_r1, UInt<1>("h00")) @[dec_decode_ctl.scala 472:44] - node _T_422 = eq(tlu_wr_pause_r2, UInt<1>("h00")) @[dec_decode_ctl.scala 472:64] - node _T_423 = and(_T_421, _T_422) @[dec_decode_ctl.scala 472:61] - node _T_424 = and(pause_stall, _T_423) @[dec_decode_ctl.scala 472:41] - io.dec_pause_state_cg <= _T_424 @[dec_decode_ctl.scala 472:25] - node _T_425 = sub(write_csr_data, UInt<32>("h01")) @[dec_decode_ctl.scala 475:59] - node _T_426 = tail(_T_425, 1) @[dec_decode_ctl.scala 475:59] - node _T_427 = mux(io.dec_tlu_wr_pause_r, io.dec_csr_wrdata_r, write_csr_data_x) @[dec_decode_ctl.scala 476:8] - node write_csr_data_in = mux(pause_stall, _T_426, _T_427) @[dec_decode_ctl.scala 475:30] - node _T_428 = or(csr_clr_x, csr_set_x) @[dec_decode_ctl.scala 477:34] - node _T_429 = or(_T_428, csr_write_x) @[dec_decode_ctl.scala 477:46] - node _T_430 = and(_T_429, csr_read_x) @[dec_decode_ctl.scala 477:61] - node _T_431 = or(_T_430, io.dec_tlu_wr_pause_r) @[dec_decode_ctl.scala 477:75] - node csr_data_wen = or(_T_431, pause_stall) @[dec_decode_ctl.scala 477:99] + node _T_413 = eq(write_csr_data, _T_412) @[dec_decode_ctl.scala 459:109] + node _T_414 = and(pause_stall, _T_413) @[dec_decode_ctl.scala 459:91] + node clear_pause = or(_T_409, _T_414) @[dec_decode_ctl.scala 459:76] + node _T_415 = or(io.dec_tlu_wr_pause_r, pause_stall) @[dec_decode_ctl.scala 460:44] + node _T_416 = eq(clear_pause, UInt<1>("h00")) @[dec_decode_ctl.scala 460:61] + node _T_417 = and(_T_415, _T_416) @[dec_decode_ctl.scala 460:59] + pause_state_in <= _T_417 @[dec_decode_ctl.scala 460:18] + reg _T_418 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 461:50] + _T_418 <= pause_state_in @[dec_decode_ctl.scala 461:50] + pause_stall <= _T_418 @[dec_decode_ctl.scala 461:15] + io.dec_pause_state <= pause_stall @[dec_decode_ctl.scala 462:22] + reg _T_419 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 463:55] + _T_419 <= io.dec_tlu_wr_pause_r @[dec_decode_ctl.scala 463:55] + tlu_wr_pause_r1 <= _T_419 @[dec_decode_ctl.scala 463:19] + reg _T_420 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 464:55] + _T_420 <= tlu_wr_pause_r1 @[dec_decode_ctl.scala 464:55] + tlu_wr_pause_r2 <= _T_420 @[dec_decode_ctl.scala 464:19] + node _T_421 = eq(tlu_wr_pause_r1, UInt<1>("h00")) @[dec_decode_ctl.scala 466:44] + node _T_422 = eq(tlu_wr_pause_r2, UInt<1>("h00")) @[dec_decode_ctl.scala 466:64] + node _T_423 = and(_T_421, _T_422) @[dec_decode_ctl.scala 466:61] + node _T_424 = and(pause_stall, _T_423) @[dec_decode_ctl.scala 466:41] + io.dec_pause_state_cg <= _T_424 @[dec_decode_ctl.scala 466:25] + node _T_425 = sub(write_csr_data, UInt<32>("h01")) @[dec_decode_ctl.scala 469:59] + node _T_426 = tail(_T_425, 1) @[dec_decode_ctl.scala 469:59] + node _T_427 = mux(io.dec_tlu_wr_pause_r, io.dec_csr_wrdata_r, write_csr_data_x) @[dec_decode_ctl.scala 470:8] + node write_csr_data_in = mux(pause_stall, _T_426, _T_427) @[dec_decode_ctl.scala 469:30] + node _T_428 = or(csr_clr_x, csr_set_x) @[dec_decode_ctl.scala 471:34] + node _T_429 = or(_T_428, csr_write_x) @[dec_decode_ctl.scala 471:46] + node _T_430 = and(_T_429, csr_read_x) @[dec_decode_ctl.scala 471:61] + node _T_431 = or(_T_430, io.dec_tlu_wr_pause_r) @[dec_decode_ctl.scala 471:75] + node csr_data_wen = or(_T_431, pause_stall) @[dec_decode_ctl.scala 471:99] inst rvclkhdr_3 of rvclkhdr_664 @[lib.scala 368:23] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset @@ -68098,33 +68098,33 @@ circuit quasar_wrapper : rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_432 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_432 <= write_csr_data_in @[lib.scala 374:16] - write_csr_data <= _T_432 @[dec_decode_ctl.scala 478:18] - node _T_433 = bits(r_d.bits.csrwonly, 0, 0) @[dec_decode_ctl.scala 484:49] - node _T_434 = mux(_T_433, i0_result_corr_r, write_csr_data) @[dec_decode_ctl.scala 484:30] - io.dec_csr_wrdata_r <= _T_434 @[dec_decode_ctl.scala 484:24] - node _T_435 = or(x_d.bits.csrwonly, r_d.bits.csrwonly) @[dec_decode_ctl.scala 486:43] - node prior_csr_write = or(_T_435, wbd.bits.csrwonly) @[dec_decode_ctl.scala 486:63] - node _T_436 = bits(io.dbg_dctl.dbg_cmd_wrdata, 0, 0) @[dec_decode_ctl.scala 488:76] - node debug_fence_i = and(io.dec_debug_fence_d, _T_436) @[dec_decode_ctl.scala 488:48] - node _T_437 = bits(io.dbg_dctl.dbg_cmd_wrdata, 1, 1) @[dec_decode_ctl.scala 489:76] - node debug_fence_raw = and(io.dec_debug_fence_d, _T_437) @[dec_decode_ctl.scala 489:48] - node _T_438 = or(debug_fence_raw, debug_fence_i) @[dec_decode_ctl.scala 490:40] - debug_fence <= _T_438 @[dec_decode_ctl.scala 490:21] - node _T_439 = or(i0_dp.presync, io.dec_tlu_presync_d) @[dec_decode_ctl.scala 493:34] - node _T_440 = or(_T_439, debug_fence_i) @[dec_decode_ctl.scala 493:57] - node _T_441 = or(_T_440, debug_fence_raw) @[dec_decode_ctl.scala 493:73] - node i0_presync = or(_T_441, io.dec_tlu_pipelining_disable) @[dec_decode_ctl.scala 493:91] - node _T_442 = or(i0_dp.postsync, io.dec_tlu_postsync_d) @[dec_decode_ctl.scala 496:36] - node _T_443 = or(_T_442, debug_fence_i) @[dec_decode_ctl.scala 496:60] - node _T_444 = bits(io.dec_i0_instr_d, 31, 20) @[dec_decode_ctl.scala 496:104] - node _T_445 = eq(_T_444, UInt<11>("h07c2")) @[dec_decode_ctl.scala 496:112] - node _T_446 = and(i0_csr_write_only_d, _T_445) @[dec_decode_ctl.scala 496:99] - node i0_postsync = or(_T_443, _T_446) @[dec_decode_ctl.scala 496:76] - node any_csr_d = or(i0_dp.csr_read, i0_csr_write) @[dec_decode_ctl.scala 498:34] - io.dec_csr_any_unq_d <= any_csr_d @[dec_decode_ctl.scala 499:24] - node _T_447 = eq(any_csr_d, UInt<1>("h00")) @[dec_decode_ctl.scala 500:40] - node _T_448 = or(_T_447, io.dec_csr_legal_d) @[dec_decode_ctl.scala 500:51] - node i0_legal = and(i0_dp.legal, _T_448) @[dec_decode_ctl.scala 500:37] + write_csr_data <= _T_432 @[dec_decode_ctl.scala 472:18] + node _T_433 = bits(r_d.bits.csrwonly, 0, 0) @[dec_decode_ctl.scala 478:49] + node _T_434 = mux(_T_433, i0_result_corr_r, write_csr_data) @[dec_decode_ctl.scala 478:30] + io.dec_csr_wrdata_r <= _T_434 @[dec_decode_ctl.scala 478:24] + node _T_435 = or(x_d.bits.csrwonly, r_d.bits.csrwonly) @[dec_decode_ctl.scala 480:43] + node prior_csr_write = or(_T_435, wbd.bits.csrwonly) @[dec_decode_ctl.scala 480:63] + node _T_436 = bits(io.dbg_dctl.dbg_cmd_wrdata, 0, 0) @[dec_decode_ctl.scala 482:76] + node debug_fence_i = and(io.dec_debug_fence_d, _T_436) @[dec_decode_ctl.scala 482:48] + node _T_437 = bits(io.dbg_dctl.dbg_cmd_wrdata, 1, 1) @[dec_decode_ctl.scala 483:76] + node debug_fence_raw = and(io.dec_debug_fence_d, _T_437) @[dec_decode_ctl.scala 483:48] + node _T_438 = or(debug_fence_raw, debug_fence_i) @[dec_decode_ctl.scala 484:40] + debug_fence <= _T_438 @[dec_decode_ctl.scala 484:21] + node _T_439 = or(i0_dp.presync, io.dec_tlu_presync_d) @[dec_decode_ctl.scala 487:34] + node _T_440 = or(_T_439, debug_fence_i) @[dec_decode_ctl.scala 487:57] + node _T_441 = or(_T_440, debug_fence_raw) @[dec_decode_ctl.scala 487:73] + node i0_presync = or(_T_441, io.dec_tlu_pipelining_disable) @[dec_decode_ctl.scala 487:91] + node _T_442 = or(i0_dp.postsync, io.dec_tlu_postsync_d) @[dec_decode_ctl.scala 490:36] + node _T_443 = or(_T_442, debug_fence_i) @[dec_decode_ctl.scala 490:60] + node _T_444 = bits(io.dec_i0_instr_d, 31, 20) @[dec_decode_ctl.scala 490:104] + node _T_445 = eq(_T_444, UInt<11>("h07c2")) @[dec_decode_ctl.scala 490:112] + node _T_446 = and(i0_csr_write_only_d, _T_445) @[dec_decode_ctl.scala 490:99] + node i0_postsync = or(_T_443, _T_446) @[dec_decode_ctl.scala 490:76] + node any_csr_d = or(i0_dp.csr_read, i0_csr_write) @[dec_decode_ctl.scala 492:34] + io.dec_csr_any_unq_d <= any_csr_d @[dec_decode_ctl.scala 493:24] + node _T_447 = eq(any_csr_d, UInt<1>("h00")) @[dec_decode_ctl.scala 494:40] + node _T_448 = or(_T_447, io.dec_csr_legal_d) @[dec_decode_ctl.scala 494:51] + node i0_legal = and(i0_dp.legal, _T_448) @[dec_decode_ctl.scala 494:37] wire _T_449 : UInt<1>[16] @[lib.scala 12:48] _T_449[0] <= UInt<1>("h00") @[lib.scala 12:48] _T_449[1] <= UInt<1>("h00") @[lib.scala 12:48] @@ -68158,11 +68158,11 @@ circuit quasar_wrapper : node _T_463 = cat(_T_462, _T_449[14]) @[Cat.scala 29:58] node _T_464 = cat(_T_463, _T_449[15]) @[Cat.scala 29:58] node _T_465 = cat(_T_464, io.dec_aln.ifu_i0_cinst) @[Cat.scala 29:58] - node i0_inst_d = mux(io.dec_i0_pc4_d, io.dec_i0_instr_d, _T_465) @[dec_decode_ctl.scala 501:27] - node _T_466 = eq(i0_legal, UInt<1>("h00")) @[dec_decode_ctl.scala 504:57] - node shift_illegal = and(io.dec_aln.dec_i0_decode_d, _T_466) @[dec_decode_ctl.scala 504:55] - node _T_467 = eq(illegal_lockout, UInt<1>("h00")) @[dec_decode_ctl.scala 505:44] - node illegal_inst_en = and(shift_illegal, _T_467) @[dec_decode_ctl.scala 505:42] + node i0_inst_d = mux(io.dec_i0_pc4_d, io.dec_i0_instr_d, _T_465) @[dec_decode_ctl.scala 495:27] + node _T_466 = eq(i0_legal, UInt<1>("h00")) @[dec_decode_ctl.scala 498:57] + node shift_illegal = and(io.dec_aln.dec_i0_decode_d, _T_466) @[dec_decode_ctl.scala 498:55] + node _T_467 = eq(illegal_lockout, UInt<1>("h00")) @[dec_decode_ctl.scala 499:44] + node illegal_inst_en = and(shift_illegal, _T_467) @[dec_decode_ctl.scala 499:42] inst rvclkhdr_4 of rvclkhdr_665 @[lib.scala 368:23] rvclkhdr_4.clock <= clock rvclkhdr_4.reset <= reset @@ -68171,94 +68171,94 @@ circuit quasar_wrapper : rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg _T_468 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] _T_468 <= i0_inst_d @[lib.scala 374:16] - io.dec_illegal_inst <= _T_468 @[dec_decode_ctl.scala 506:23] - node _T_469 = or(shift_illegal, illegal_lockout) @[dec_decode_ctl.scala 507:40] - node _T_470 = eq(flush_final_r, UInt<1>("h00")) @[dec_decode_ctl.scala 507:61] - node _T_471 = and(_T_469, _T_470) @[dec_decode_ctl.scala 507:59] - illegal_lockout_in <= _T_471 @[dec_decode_ctl.scala 507:22] - reg _T_472 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 508:54] - _T_472 <= illegal_lockout_in @[dec_decode_ctl.scala 508:54] - illegal_lockout <= _T_472 @[dec_decode_ctl.scala 508:19] - node i0_div_prior_div_stall = and(i0_dp.div, io.dec_div_active) @[dec_decode_ctl.scala 509:42] - node _T_473 = and(i0_dp.csr_read, prior_csr_write) @[dec_decode_ctl.scala 511:40] - node _T_474 = or(_T_473, io.decode_exu.dec_extint_stall) @[dec_decode_ctl.scala 511:59] - node _T_475 = or(_T_474, pause_stall) @[dec_decode_ctl.scala 511:92] - node _T_476 = or(_T_475, leak1_i0_stall) @[dec_decode_ctl.scala 511:106] - node _T_477 = or(_T_476, io.dec_tlu_debug_stall) @[dec_decode_ctl.scala 512:20] - node _T_478 = or(_T_477, postsync_stall) @[dec_decode_ctl.scala 512:45] - node _T_479 = or(_T_478, presync_stall) @[dec_decode_ctl.scala 512:62] - node _T_480 = or(i0_dp.fence, debug_fence) @[dec_decode_ctl.scala 513:19] - node _T_481 = eq(lsu_idle, UInt<1>("h00")) @[dec_decode_ctl.scala 513:36] - node _T_482 = and(_T_480, _T_481) @[dec_decode_ctl.scala 513:34] - node _T_483 = or(_T_479, _T_482) @[dec_decode_ctl.scala 512:79] - node _T_484 = or(_T_483, i0_nonblock_load_stall) @[dec_decode_ctl.scala 513:47] - node _T_485 = or(_T_484, i0_load_block_d) @[dec_decode_ctl.scala 513:72] - node _T_486 = or(_T_485, i0_nonblock_div_stall) @[dec_decode_ctl.scala 514:21] - node i0_block_raw_d = or(_T_486, i0_div_prior_div_stall) @[dec_decode_ctl.scala 514:45] - node _T_487 = or(io.lsu_store_stall_any, io.dctl_dma.dma_dccm_stall_any) @[dec_decode_ctl.scala 516:65] - node i0_store_stall_d = and(i0_dp.store, _T_487) @[dec_decode_ctl.scala 516:39] - node _T_488 = or(io.lsu_load_stall_any, io.dctl_dma.dma_dccm_stall_any) @[dec_decode_ctl.scala 517:63] - node i0_load_stall_d = and(i0_dp.load, _T_488) @[dec_decode_ctl.scala 517:38] - node _T_489 = or(i0_block_raw_d, i0_store_stall_d) @[dec_decode_ctl.scala 518:38] - node i0_block_d = or(_T_489, i0_load_stall_d) @[dec_decode_ctl.scala 518:57] - node _T_490 = eq(i0_block_d, UInt<1>("h00")) @[dec_decode_ctl.scala 522:54] - node _T_491 = and(io.dec_ib0_valid_d, _T_490) @[dec_decode_ctl.scala 522:52] - node _T_492 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 522:71] - node _T_493 = and(_T_491, _T_492) @[dec_decode_ctl.scala 522:69] - node _T_494 = eq(flush_final_r, UInt<1>("h00")) @[dec_decode_ctl.scala 522:99] - node _T_495 = and(_T_493, _T_494) @[dec_decode_ctl.scala 522:97] - io.dec_aln.dec_i0_decode_d <= _T_495 @[dec_decode_ctl.scala 522:30] - node _T_496 = eq(i0_block_raw_d, UInt<1>("h00")) @[dec_decode_ctl.scala 523:46] - node _T_497 = and(io.dec_ib0_valid_d, _T_496) @[dec_decode_ctl.scala 523:44] - node _T_498 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 523:63] - node _T_499 = and(_T_497, _T_498) @[dec_decode_ctl.scala 523:61] - node _T_500 = eq(flush_final_r, UInt<1>("h00")) @[dec_decode_ctl.scala 523:91] - node i0_exudecode_d = and(_T_499, _T_500) @[dec_decode_ctl.scala 523:89] - node i0_exulegal_decode_d = and(i0_exudecode_d, i0_legal) @[dec_decode_ctl.scala 524:46] - io.dec_pmu_instr_decoded <= io.dec_aln.dec_i0_decode_d @[dec_decode_ctl.scala 527:28] - node _T_501 = eq(io.dec_aln.dec_i0_decode_d, UInt<1>("h00")) @[dec_decode_ctl.scala 528:51] - node _T_502 = and(io.dec_ib0_valid_d, _T_501) @[dec_decode_ctl.scala 528:49] - io.dec_pmu_decode_stall <= _T_502 @[dec_decode_ctl.scala 528:27] - node _T_503 = bits(postsync_stall, 0, 0) @[dec_decode_ctl.scala 529:47] - io.dec_pmu_postsync_stall <= _T_503 @[dec_decode_ctl.scala 529:29] - node _T_504 = bits(presync_stall, 0, 0) @[dec_decode_ctl.scala 530:46] - io.dec_pmu_presync_stall <= _T_504 @[dec_decode_ctl.scala 530:29] - node prior_inflight = or(x_d.valid, r_d.valid) @[dec_decode_ctl.scala 534:41] - node prior_inflight_eff = mux(i0_dp.div, x_d.valid, prior_inflight) @[dec_decode_ctl.scala 535:31] - node _T_505 = and(i0_presync, prior_inflight_eff) @[dec_decode_ctl.scala 537:37] - presync_stall <= _T_505 @[dec_decode_ctl.scala 537:22] - reg _T_506 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 538:53] - _T_506 <= ps_stall_in @[dec_decode_ctl.scala 538:53] - postsync_stall <= _T_506 @[dec_decode_ctl.scala 538:18] - node _T_507 = eq(i0_legal, UInt<1>("h00")) @[dec_decode_ctl.scala 540:64] - node _T_508 = or(i0_postsync, _T_507) @[dec_decode_ctl.scala 540:62] - node _T_509 = and(io.dec_aln.dec_i0_decode_d, _T_508) @[dec_decode_ctl.scala 540:47] - node _T_510 = and(postsync_stall, x_d.valid) @[dec_decode_ctl.scala 540:96] - node _T_511 = or(_T_509, _T_510) @[dec_decode_ctl.scala 540:77] - ps_stall_in <= _T_511 @[dec_decode_ctl.scala 540:15] - node _T_512 = and(i0_exulegal_decode_d, i0_dp.alu) @[dec_decode_ctl.scala 542:58] - io.dec_alu.dec_i0_alu_decode_d <= _T_512 @[dec_decode_ctl.scala 542:34] - node _T_513 = and(i0_legal_decode_d, i0_dp.lsu) @[dec_decode_ctl.scala 544:40] - lsu_decode_d <= _T_513 @[dec_decode_ctl.scala 544:16] - node _T_514 = and(i0_exulegal_decode_d, i0_dp.mul) @[dec_decode_ctl.scala 545:40] - mul_decode_d <= _T_514 @[dec_decode_ctl.scala 545:16] - node _T_515 = and(i0_exulegal_decode_d, i0_dp.div) @[dec_decode_ctl.scala 546:40] - div_decode_d <= _T_515 @[dec_decode_ctl.scala 546:16] - node _T_516 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 548:45] - node _T_517 = and(r_d.valid, _T_516) @[dec_decode_ctl.scala 548:43] - io.dec_tlu_i0_valid_r <= _T_517 @[dec_decode_ctl.scala 548:29] - d_t.legal <= i0_legal_decode_d @[dec_decode_ctl.scala 551:26] - node _T_518 = and(i0_icaf_d, i0_legal_decode_d) @[dec_decode_ctl.scala 552:40] - d_t.icaf <= _T_518 @[dec_decode_ctl.scala 552:26] - node _T_519 = and(io.dec_i0_icaf_f1_d, i0_legal_decode_d) @[dec_decode_ctl.scala 553:50] - d_t.icaf_f1 <= _T_519 @[dec_decode_ctl.scala 553:26] - d_t.icaf_type <= io.dec_i0_icaf_type_d @[dec_decode_ctl.scala 554:26] - node _T_520 = or(i0_dp.fence_i, debug_fence_i) @[dec_decode_ctl.scala 556:44] - node _T_521 = and(_T_520, i0_legal_decode_d) @[dec_decode_ctl.scala 556:61] - d_t.fence_i <= _T_521 @[dec_decode_ctl.scala 556:26] - d_t.pmu_i0_br_unpred <= i0_br_unpred @[dec_decode_ctl.scala 559:26] - d_t.pmu_divide <= UInt<1>("h00") @[dec_decode_ctl.scala 560:26] - d_t.pmu_lsu_misaligned <= UInt<1>("h00") @[dec_decode_ctl.scala 561:26] + io.dec_illegal_inst <= _T_468 @[dec_decode_ctl.scala 500:23] + node _T_469 = or(shift_illegal, illegal_lockout) @[dec_decode_ctl.scala 501:40] + node _T_470 = eq(flush_final_r, UInt<1>("h00")) @[dec_decode_ctl.scala 501:61] + node _T_471 = and(_T_469, _T_470) @[dec_decode_ctl.scala 501:59] + illegal_lockout_in <= _T_471 @[dec_decode_ctl.scala 501:22] + reg _T_472 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 502:54] + _T_472 <= illegal_lockout_in @[dec_decode_ctl.scala 502:54] + illegal_lockout <= _T_472 @[dec_decode_ctl.scala 502:19] + node i0_div_prior_div_stall = and(i0_dp.div, io.dec_div_active) @[dec_decode_ctl.scala 503:42] + node _T_473 = and(i0_dp.csr_read, prior_csr_write) @[dec_decode_ctl.scala 505:40] + node _T_474 = or(_T_473, io.decode_exu.dec_extint_stall) @[dec_decode_ctl.scala 505:59] + node _T_475 = or(_T_474, pause_stall) @[dec_decode_ctl.scala 505:92] + node _T_476 = or(_T_475, leak1_i0_stall) @[dec_decode_ctl.scala 505:106] + node _T_477 = or(_T_476, io.dec_tlu_debug_stall) @[dec_decode_ctl.scala 506:20] + node _T_478 = or(_T_477, postsync_stall) @[dec_decode_ctl.scala 506:45] + node _T_479 = or(_T_478, presync_stall) @[dec_decode_ctl.scala 506:62] + node _T_480 = or(i0_dp.fence, debug_fence) @[dec_decode_ctl.scala 507:19] + node _T_481 = eq(lsu_idle, UInt<1>("h00")) @[dec_decode_ctl.scala 507:36] + node _T_482 = and(_T_480, _T_481) @[dec_decode_ctl.scala 507:34] + node _T_483 = or(_T_479, _T_482) @[dec_decode_ctl.scala 506:79] + node _T_484 = or(_T_483, i0_nonblock_load_stall) @[dec_decode_ctl.scala 507:47] + node _T_485 = or(_T_484, i0_load_block_d) @[dec_decode_ctl.scala 507:72] + node _T_486 = or(_T_485, i0_nonblock_div_stall) @[dec_decode_ctl.scala 508:21] + node i0_block_raw_d = or(_T_486, i0_div_prior_div_stall) @[dec_decode_ctl.scala 508:45] + node _T_487 = or(io.lsu_store_stall_any, io.dctl_dma.dma_dccm_stall_any) @[dec_decode_ctl.scala 510:65] + node i0_store_stall_d = and(i0_dp.store, _T_487) @[dec_decode_ctl.scala 510:39] + node _T_488 = or(io.lsu_load_stall_any, io.dctl_dma.dma_dccm_stall_any) @[dec_decode_ctl.scala 511:63] + node i0_load_stall_d = and(i0_dp.load, _T_488) @[dec_decode_ctl.scala 511:38] + node _T_489 = or(i0_block_raw_d, i0_store_stall_d) @[dec_decode_ctl.scala 512:38] + node i0_block_d = or(_T_489, i0_load_stall_d) @[dec_decode_ctl.scala 512:57] + node _T_490 = eq(i0_block_d, UInt<1>("h00")) @[dec_decode_ctl.scala 516:54] + node _T_491 = and(io.dec_ib0_valid_d, _T_490) @[dec_decode_ctl.scala 516:52] + node _T_492 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 516:71] + node _T_493 = and(_T_491, _T_492) @[dec_decode_ctl.scala 516:69] + node _T_494 = eq(flush_final_r, UInt<1>("h00")) @[dec_decode_ctl.scala 516:99] + node _T_495 = and(_T_493, _T_494) @[dec_decode_ctl.scala 516:97] + io.dec_aln.dec_i0_decode_d <= _T_495 @[dec_decode_ctl.scala 516:30] + node _T_496 = eq(i0_block_raw_d, UInt<1>("h00")) @[dec_decode_ctl.scala 517:46] + node _T_497 = and(io.dec_ib0_valid_d, _T_496) @[dec_decode_ctl.scala 517:44] + node _T_498 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 517:63] + node _T_499 = and(_T_497, _T_498) @[dec_decode_ctl.scala 517:61] + node _T_500 = eq(flush_final_r, UInt<1>("h00")) @[dec_decode_ctl.scala 517:91] + node i0_exudecode_d = and(_T_499, _T_500) @[dec_decode_ctl.scala 517:89] + node i0_exulegal_decode_d = and(i0_exudecode_d, i0_legal) @[dec_decode_ctl.scala 518:46] + io.dec_pmu_instr_decoded <= io.dec_aln.dec_i0_decode_d @[dec_decode_ctl.scala 521:28] + node _T_501 = eq(io.dec_aln.dec_i0_decode_d, UInt<1>("h00")) @[dec_decode_ctl.scala 522:51] + node _T_502 = and(io.dec_ib0_valid_d, _T_501) @[dec_decode_ctl.scala 522:49] + io.dec_pmu_decode_stall <= _T_502 @[dec_decode_ctl.scala 522:27] + node _T_503 = bits(postsync_stall, 0, 0) @[dec_decode_ctl.scala 523:47] + io.dec_pmu_postsync_stall <= _T_503 @[dec_decode_ctl.scala 523:29] + node _T_504 = bits(presync_stall, 0, 0) @[dec_decode_ctl.scala 524:46] + io.dec_pmu_presync_stall <= _T_504 @[dec_decode_ctl.scala 524:29] + node prior_inflight = or(x_d.valid, r_d.valid) @[dec_decode_ctl.scala 528:41] + node prior_inflight_eff = mux(i0_dp.div, x_d.valid, prior_inflight) @[dec_decode_ctl.scala 529:31] + node _T_505 = and(i0_presync, prior_inflight_eff) @[dec_decode_ctl.scala 531:37] + presync_stall <= _T_505 @[dec_decode_ctl.scala 531:22] + reg _T_506 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 532:53] + _T_506 <= ps_stall_in @[dec_decode_ctl.scala 532:53] + postsync_stall <= _T_506 @[dec_decode_ctl.scala 532:18] + node _T_507 = eq(i0_legal, UInt<1>("h00")) @[dec_decode_ctl.scala 534:64] + node _T_508 = or(i0_postsync, _T_507) @[dec_decode_ctl.scala 534:62] + node _T_509 = and(io.dec_aln.dec_i0_decode_d, _T_508) @[dec_decode_ctl.scala 534:47] + node _T_510 = and(postsync_stall, x_d.valid) @[dec_decode_ctl.scala 534:96] + node _T_511 = or(_T_509, _T_510) @[dec_decode_ctl.scala 534:77] + ps_stall_in <= _T_511 @[dec_decode_ctl.scala 534:15] + node _T_512 = and(i0_exulegal_decode_d, i0_dp.alu) @[dec_decode_ctl.scala 536:58] + io.dec_alu.dec_i0_alu_decode_d <= _T_512 @[dec_decode_ctl.scala 536:34] + node _T_513 = and(i0_legal_decode_d, i0_dp.lsu) @[dec_decode_ctl.scala 538:40] + lsu_decode_d <= _T_513 @[dec_decode_ctl.scala 538:16] + node _T_514 = and(i0_exulegal_decode_d, i0_dp.mul) @[dec_decode_ctl.scala 539:40] + mul_decode_d <= _T_514 @[dec_decode_ctl.scala 539:16] + node _T_515 = and(i0_exulegal_decode_d, i0_dp.div) @[dec_decode_ctl.scala 540:40] + div_decode_d <= _T_515 @[dec_decode_ctl.scala 540:16] + node _T_516 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 542:45] + node _T_517 = and(r_d.valid, _T_516) @[dec_decode_ctl.scala 542:43] + io.dec_tlu_i0_valid_r <= _T_517 @[dec_decode_ctl.scala 542:29] + d_t.legal <= i0_legal_decode_d @[dec_decode_ctl.scala 545:26] + node _T_518 = and(i0_icaf_d, i0_legal_decode_d) @[dec_decode_ctl.scala 546:40] + d_t.icaf <= _T_518 @[dec_decode_ctl.scala 546:26] + node _T_519 = and(io.dec_i0_icaf_f1_d, i0_legal_decode_d) @[dec_decode_ctl.scala 547:50] + d_t.icaf_f1 <= _T_519 @[dec_decode_ctl.scala 547:26] + d_t.icaf_type <= io.dec_i0_icaf_type_d @[dec_decode_ctl.scala 548:26] + node _T_520 = or(i0_dp.fence_i, debug_fence_i) @[dec_decode_ctl.scala 550:44] + node _T_521 = and(_T_520, i0_legal_decode_d) @[dec_decode_ctl.scala 550:61] + d_t.fence_i <= _T_521 @[dec_decode_ctl.scala 550:26] + d_t.pmu_i0_br_unpred <= i0_br_unpred @[dec_decode_ctl.scala 553:26] + d_t.pmu_divide <= UInt<1>("h00") @[dec_decode_ctl.scala 554:26] + d_t.pmu_lsu_misaligned <= UInt<1>("h00") @[dec_decode_ctl.scala 555:26] wire _T_522 : UInt<1>[4] @[lib.scala 12:48] _T_522[0] <= io.dec_aln.dec_i0_decode_d @[lib.scala 12:48] _T_522[1] <= io.dec_aln.dec_i0_decode_d @[lib.scala 12:48] @@ -68267,9 +68267,9 @@ circuit quasar_wrapper : node _T_523 = cat(_T_522[0], _T_522[1]) @[Cat.scala 29:58] node _T_524 = cat(_T_523, _T_522[2]) @[Cat.scala 29:58] node _T_525 = cat(_T_524, _T_522[3]) @[Cat.scala 29:58] - node _T_526 = and(io.dec_i0_trigger_match_d, _T_525) @[dec_decode_ctl.scala 563:56] - d_t.i0trigger <= _T_526 @[dec_decode_ctl.scala 563:26] - node _T_527 = bits(i0_x_ctl_en, 0, 0) @[dec_decode_ctl.scala 566:33] + node _T_526 = and(io.dec_i0_trigger_match_d, _T_525) @[dec_decode_ctl.scala 557:56] + d_t.i0trigger <= _T_526 @[dec_decode_ctl.scala 557:26] + node _T_527 = bits(i0_x_ctl_en, 0, 0) @[dec_decode_ctl.scala 560:33] inst rvclkhdr_5 of rvclkhdr_666 @[lib.scala 378:23] rvclkhdr_5.clock <= clock rvclkhdr_5.reset <= reset @@ -68298,26 +68298,26 @@ circuit quasar_wrapper : _T_529.icaf_f1 <= d_t.icaf_f1 @[lib.scala 384:16] _T_529.icaf <= d_t.icaf @[lib.scala 384:16] _T_529.legal <= d_t.legal @[lib.scala 384:16] - x_t.pmu_lsu_misaligned <= _T_529.pmu_lsu_misaligned @[dec_decode_ctl.scala 566:7] - x_t.pmu_divide <= _T_529.pmu_divide @[dec_decode_ctl.scala 566:7] - x_t.pmu_i0_br_unpred <= _T_529.pmu_i0_br_unpred @[dec_decode_ctl.scala 566:7] - x_t.pmu_i0_itype <= _T_529.pmu_i0_itype @[dec_decode_ctl.scala 566:7] - x_t.i0trigger <= _T_529.i0trigger @[dec_decode_ctl.scala 566:7] - x_t.fence_i <= _T_529.fence_i @[dec_decode_ctl.scala 566:7] - x_t.icaf_type <= _T_529.icaf_type @[dec_decode_ctl.scala 566:7] - x_t.icaf_f1 <= _T_529.icaf_f1 @[dec_decode_ctl.scala 566:7] - x_t.icaf <= _T_529.icaf @[dec_decode_ctl.scala 566:7] - x_t.legal <= _T_529.legal @[dec_decode_ctl.scala 566:7] - x_t_in.pmu_lsu_misaligned <= x_t.pmu_lsu_misaligned @[dec_decode_ctl.scala 568:10] - x_t_in.pmu_divide <= x_t.pmu_divide @[dec_decode_ctl.scala 568:10] - x_t_in.pmu_i0_br_unpred <= x_t.pmu_i0_br_unpred @[dec_decode_ctl.scala 568:10] - x_t_in.pmu_i0_itype <= x_t.pmu_i0_itype @[dec_decode_ctl.scala 568:10] - x_t_in.i0trigger <= x_t.i0trigger @[dec_decode_ctl.scala 568:10] - x_t_in.fence_i <= x_t.fence_i @[dec_decode_ctl.scala 568:10] - x_t_in.icaf_type <= x_t.icaf_type @[dec_decode_ctl.scala 568:10] - x_t_in.icaf_f1 <= x_t.icaf_f1 @[dec_decode_ctl.scala 568:10] - x_t_in.icaf <= x_t.icaf @[dec_decode_ctl.scala 568:10] - x_t_in.legal <= x_t.legal @[dec_decode_ctl.scala 568:10] + x_t.pmu_lsu_misaligned <= _T_529.pmu_lsu_misaligned @[dec_decode_ctl.scala 560:7] + x_t.pmu_divide <= _T_529.pmu_divide @[dec_decode_ctl.scala 560:7] + x_t.pmu_i0_br_unpred <= _T_529.pmu_i0_br_unpred @[dec_decode_ctl.scala 560:7] + x_t.pmu_i0_itype <= _T_529.pmu_i0_itype @[dec_decode_ctl.scala 560:7] + x_t.i0trigger <= _T_529.i0trigger @[dec_decode_ctl.scala 560:7] + x_t.fence_i <= _T_529.fence_i @[dec_decode_ctl.scala 560:7] + x_t.icaf_type <= _T_529.icaf_type @[dec_decode_ctl.scala 560:7] + x_t.icaf_f1 <= _T_529.icaf_f1 @[dec_decode_ctl.scala 560:7] + x_t.icaf <= _T_529.icaf @[dec_decode_ctl.scala 560:7] + x_t.legal <= _T_529.legal @[dec_decode_ctl.scala 560:7] + x_t_in.pmu_lsu_misaligned <= x_t.pmu_lsu_misaligned @[dec_decode_ctl.scala 562:10] + x_t_in.pmu_divide <= x_t.pmu_divide @[dec_decode_ctl.scala 562:10] + x_t_in.pmu_i0_br_unpred <= x_t.pmu_i0_br_unpred @[dec_decode_ctl.scala 562:10] + x_t_in.pmu_i0_itype <= x_t.pmu_i0_itype @[dec_decode_ctl.scala 562:10] + x_t_in.i0trigger <= x_t.i0trigger @[dec_decode_ctl.scala 562:10] + x_t_in.fence_i <= x_t.fence_i @[dec_decode_ctl.scala 562:10] + x_t_in.icaf_type <= x_t.icaf_type @[dec_decode_ctl.scala 562:10] + x_t_in.icaf_f1 <= x_t.icaf_f1 @[dec_decode_ctl.scala 562:10] + x_t_in.icaf <= x_t.icaf @[dec_decode_ctl.scala 562:10] + x_t_in.legal <= x_t.legal @[dec_decode_ctl.scala 562:10] wire _T_530 : UInt<1>[4] @[lib.scala 12:48] _T_530[0] <= io.dec_tlu_flush_lower_wb @[lib.scala 12:48] _T_530[1] <= io.dec_tlu_flush_lower_wb @[lib.scala 12:48] @@ -68326,10 +68326,10 @@ circuit quasar_wrapper : node _T_531 = cat(_T_530[0], _T_530[1]) @[Cat.scala 29:58] node _T_532 = cat(_T_531, _T_530[2]) @[Cat.scala 29:58] node _T_533 = cat(_T_532, _T_530[3]) @[Cat.scala 29:58] - node _T_534 = not(_T_533) @[dec_decode_ctl.scala 569:39] - node _T_535 = and(x_t.i0trigger, _T_534) @[dec_decode_ctl.scala 569:37] - x_t_in.i0trigger <= _T_535 @[dec_decode_ctl.scala 569:20] - node _T_536 = bits(i0_x_ctl_en, 0, 0) @[dec_decode_ctl.scala 571:36] + node _T_534 = not(_T_533) @[dec_decode_ctl.scala 563:39] + node _T_535 = and(x_t.i0trigger, _T_534) @[dec_decode_ctl.scala 563:37] + x_t_in.i0trigger <= _T_535 @[dec_decode_ctl.scala 563:20] + node _T_536 = bits(i0_x_ctl_en, 0, 0) @[dec_decode_ctl.scala 565:36] inst rvclkhdr_6 of rvclkhdr_667 @[lib.scala 378:23] rvclkhdr_6.clock <= clock rvclkhdr_6.reset <= reset @@ -68358,31 +68358,31 @@ circuit quasar_wrapper : _T_538.icaf_f1 <= x_t_in.icaf_f1 @[lib.scala 384:16] _T_538.icaf <= x_t_in.icaf @[lib.scala 384:16] _T_538.legal <= x_t_in.legal @[lib.scala 384:16] - r_t.pmu_lsu_misaligned <= _T_538.pmu_lsu_misaligned @[dec_decode_ctl.scala 571:7] - r_t.pmu_divide <= _T_538.pmu_divide @[dec_decode_ctl.scala 571:7] - r_t.pmu_i0_br_unpred <= _T_538.pmu_i0_br_unpred @[dec_decode_ctl.scala 571:7] - r_t.pmu_i0_itype <= _T_538.pmu_i0_itype @[dec_decode_ctl.scala 571:7] - r_t.i0trigger <= _T_538.i0trigger @[dec_decode_ctl.scala 571:7] - r_t.fence_i <= _T_538.fence_i @[dec_decode_ctl.scala 571:7] - r_t.icaf_type <= _T_538.icaf_type @[dec_decode_ctl.scala 571:7] - r_t.icaf_f1 <= _T_538.icaf_f1 @[dec_decode_ctl.scala 571:7] - r_t.icaf <= _T_538.icaf @[dec_decode_ctl.scala 571:7] - r_t.legal <= _T_538.legal @[dec_decode_ctl.scala 571:7] - reg lsu_trigger_match_r : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 572:36] - lsu_trigger_match_r <= io.lsu_trigger_match_m @[dec_decode_ctl.scala 572:36] - reg lsu_pmu_misaligned_r : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 573:37] - lsu_pmu_misaligned_r <= io.lsu_pmu_misaligned_m @[dec_decode_ctl.scala 573:37] - r_t_in.pmu_lsu_misaligned <= r_t.pmu_lsu_misaligned @[dec_decode_ctl.scala 575:10] - r_t_in.pmu_divide <= r_t.pmu_divide @[dec_decode_ctl.scala 575:10] - r_t_in.pmu_i0_br_unpred <= r_t.pmu_i0_br_unpred @[dec_decode_ctl.scala 575:10] - r_t_in.pmu_i0_itype <= r_t.pmu_i0_itype @[dec_decode_ctl.scala 575:10] - r_t_in.i0trigger <= r_t.i0trigger @[dec_decode_ctl.scala 575:10] - r_t_in.fence_i <= r_t.fence_i @[dec_decode_ctl.scala 575:10] - r_t_in.icaf_type <= r_t.icaf_type @[dec_decode_ctl.scala 575:10] - r_t_in.icaf_f1 <= r_t.icaf_f1 @[dec_decode_ctl.scala 575:10] - r_t_in.icaf <= r_t.icaf @[dec_decode_ctl.scala 575:10] - r_t_in.legal <= r_t.legal @[dec_decode_ctl.scala 575:10] - node _T_539 = or(r_d.bits.i0load, r_d.bits.i0store) @[dec_decode_ctl.scala 577:61] + r_t.pmu_lsu_misaligned <= _T_538.pmu_lsu_misaligned @[dec_decode_ctl.scala 565:7] + r_t.pmu_divide <= _T_538.pmu_divide @[dec_decode_ctl.scala 565:7] + r_t.pmu_i0_br_unpred <= _T_538.pmu_i0_br_unpred @[dec_decode_ctl.scala 565:7] + r_t.pmu_i0_itype <= _T_538.pmu_i0_itype @[dec_decode_ctl.scala 565:7] + r_t.i0trigger <= _T_538.i0trigger @[dec_decode_ctl.scala 565:7] + r_t.fence_i <= _T_538.fence_i @[dec_decode_ctl.scala 565:7] + r_t.icaf_type <= _T_538.icaf_type @[dec_decode_ctl.scala 565:7] + r_t.icaf_f1 <= _T_538.icaf_f1 @[dec_decode_ctl.scala 565:7] + r_t.icaf <= _T_538.icaf @[dec_decode_ctl.scala 565:7] + r_t.legal <= _T_538.legal @[dec_decode_ctl.scala 565:7] + reg lsu_trigger_match_r : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 566:36] + lsu_trigger_match_r <= io.lsu_trigger_match_m @[dec_decode_ctl.scala 566:36] + reg lsu_pmu_misaligned_r : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 567:37] + lsu_pmu_misaligned_r <= io.lsu_pmu_misaligned_m @[dec_decode_ctl.scala 567:37] + r_t_in.pmu_lsu_misaligned <= r_t.pmu_lsu_misaligned @[dec_decode_ctl.scala 569:10] + r_t_in.pmu_divide <= r_t.pmu_divide @[dec_decode_ctl.scala 569:10] + r_t_in.pmu_i0_br_unpred <= r_t.pmu_i0_br_unpred @[dec_decode_ctl.scala 569:10] + r_t_in.pmu_i0_itype <= r_t.pmu_i0_itype @[dec_decode_ctl.scala 569:10] + r_t_in.i0trigger <= r_t.i0trigger @[dec_decode_ctl.scala 569:10] + r_t_in.fence_i <= r_t.fence_i @[dec_decode_ctl.scala 569:10] + r_t_in.icaf_type <= r_t.icaf_type @[dec_decode_ctl.scala 569:10] + r_t_in.icaf_f1 <= r_t.icaf_f1 @[dec_decode_ctl.scala 569:10] + r_t_in.icaf <= r_t.icaf @[dec_decode_ctl.scala 569:10] + r_t_in.legal <= r_t.legal @[dec_decode_ctl.scala 569:10] + node _T_539 = or(r_d.bits.i0load, r_d.bits.i0store) @[dec_decode_ctl.scala 571:61] wire _T_540 : UInt<1>[4] @[lib.scala 12:48] _T_540[0] <= _T_539 @[lib.scala 12:48] _T_540[1] <= _T_539 @[lib.scala 12:48] @@ -68391,83 +68391,83 @@ circuit quasar_wrapper : node _T_541 = cat(_T_540[0], _T_540[1]) @[Cat.scala 29:58] node _T_542 = cat(_T_541, _T_540[2]) @[Cat.scala 29:58] node _T_543 = cat(_T_542, _T_540[3]) @[Cat.scala 29:58] - node _T_544 = and(_T_543, lsu_trigger_match_r) @[dec_decode_ctl.scala 577:82] - node _T_545 = or(_T_544, r_t.i0trigger) @[dec_decode_ctl.scala 577:105] - r_t_in.i0trigger <= _T_545 @[dec_decode_ctl.scala 577:33] - r_t_in.pmu_lsu_misaligned <= lsu_pmu_misaligned_r @[dec_decode_ctl.scala 578:33] - node _T_546 = bits(io.dec_tlu_flush_lower_wb, 0, 0) @[dec_decode_ctl.scala 580:35] - when _T_546 : @[dec_decode_ctl.scala 580:43] - wire _T_547 : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[dec_decode_ctl.scala 580:66] - _T_547.pmu_lsu_misaligned <= UInt<1>("h00") @[dec_decode_ctl.scala 580:66] - _T_547.pmu_divide <= UInt<1>("h00") @[dec_decode_ctl.scala 580:66] - _T_547.pmu_i0_br_unpred <= UInt<1>("h00") @[dec_decode_ctl.scala 580:66] - _T_547.pmu_i0_itype <= UInt<4>("h00") @[dec_decode_ctl.scala 580:66] - _T_547.i0trigger <= UInt<4>("h00") @[dec_decode_ctl.scala 580:66] - _T_547.fence_i <= UInt<1>("h00") @[dec_decode_ctl.scala 580:66] - _T_547.icaf_type <= UInt<2>("h00") @[dec_decode_ctl.scala 580:66] - _T_547.icaf_f1 <= UInt<1>("h00") @[dec_decode_ctl.scala 580:66] - _T_547.icaf <= UInt<1>("h00") @[dec_decode_ctl.scala 580:66] - _T_547.legal <= UInt<1>("h00") @[dec_decode_ctl.scala 580:66] - r_t_in.pmu_lsu_misaligned <= _T_547.pmu_lsu_misaligned @[dec_decode_ctl.scala 580:51] - r_t_in.pmu_divide <= _T_547.pmu_divide @[dec_decode_ctl.scala 580:51] - r_t_in.pmu_i0_br_unpred <= _T_547.pmu_i0_br_unpred @[dec_decode_ctl.scala 580:51] - r_t_in.pmu_i0_itype <= _T_547.pmu_i0_itype @[dec_decode_ctl.scala 580:51] - r_t_in.i0trigger <= _T_547.i0trigger @[dec_decode_ctl.scala 580:51] - r_t_in.fence_i <= _T_547.fence_i @[dec_decode_ctl.scala 580:51] - r_t_in.icaf_type <= _T_547.icaf_type @[dec_decode_ctl.scala 580:51] - r_t_in.icaf_f1 <= _T_547.icaf_f1 @[dec_decode_ctl.scala 580:51] - r_t_in.icaf <= _T_547.icaf @[dec_decode_ctl.scala 580:51] - r_t_in.legal <= _T_547.legal @[dec_decode_ctl.scala 580:51] - skip @[dec_decode_ctl.scala 580:43] - io.dec_tlu_packet_r.pmu_lsu_misaligned <= r_t_in.pmu_lsu_misaligned @[dec_decode_ctl.scala 582:39] - io.dec_tlu_packet_r.pmu_divide <= r_t_in.pmu_divide @[dec_decode_ctl.scala 582:39] - io.dec_tlu_packet_r.pmu_i0_br_unpred <= r_t_in.pmu_i0_br_unpred @[dec_decode_ctl.scala 582:39] - io.dec_tlu_packet_r.pmu_i0_itype <= r_t_in.pmu_i0_itype @[dec_decode_ctl.scala 582:39] - io.dec_tlu_packet_r.i0trigger <= r_t_in.i0trigger @[dec_decode_ctl.scala 582:39] - io.dec_tlu_packet_r.fence_i <= r_t_in.fence_i @[dec_decode_ctl.scala 582:39] - io.dec_tlu_packet_r.icaf_type <= r_t_in.icaf_type @[dec_decode_ctl.scala 582:39] - io.dec_tlu_packet_r.icaf_f1 <= r_t_in.icaf_f1 @[dec_decode_ctl.scala 582:39] - io.dec_tlu_packet_r.icaf <= r_t_in.icaf @[dec_decode_ctl.scala 582:39] - io.dec_tlu_packet_r.legal <= r_t_in.legal @[dec_decode_ctl.scala 582:39] - node _T_548 = and(r_d.bits.i0div, r_d.valid) @[dec_decode_ctl.scala 583:58] - io.dec_tlu_packet_r.pmu_divide <= _T_548 @[dec_decode_ctl.scala 583:39] - reg _T_549 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 586:52] - _T_549 <= io.exu_flush_final @[dec_decode_ctl.scala 586:52] - flush_final_r <= _T_549 @[dec_decode_ctl.scala 586:17] - node _T_550 = eq(i0_block_d, UInt<1>("h00")) @[dec_decode_ctl.scala 588:54] - node _T_551 = and(io.dec_ib0_valid_d, _T_550) @[dec_decode_ctl.scala 588:52] - node _T_552 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 588:68] - node _T_553 = and(_T_551, _T_552) @[dec_decode_ctl.scala 588:66] - node _T_554 = eq(flush_final_r, UInt<1>("h00")) @[dec_decode_ctl.scala 588:96] - node _T_555 = and(_T_553, _T_554) @[dec_decode_ctl.scala 588:94] - io.dec_aln.dec_i0_decode_d <= _T_555 @[dec_decode_ctl.scala 588:30] - node _T_556 = bits(io.dec_i0_instr_d, 19, 15) @[dec_decode_ctl.scala 590:16] - i0r.rs1 <= _T_556 @[dec_decode_ctl.scala 590:11] - node _T_557 = bits(io.dec_i0_instr_d, 24, 20) @[dec_decode_ctl.scala 591:16] - i0r.rs2 <= _T_557 @[dec_decode_ctl.scala 591:11] - node _T_558 = bits(io.dec_i0_instr_d, 11, 7) @[dec_decode_ctl.scala 592:16] - i0r.rd <= _T_558 @[dec_decode_ctl.scala 592:11] - node _T_559 = neq(i0r.rs1, UInt<5>("h00")) @[dec_decode_ctl.scala 594:60] - node _T_560 = and(i0_dp.rs1, _T_559) @[dec_decode_ctl.scala 594:49] - io.decode_exu.dec_i0_rs1_en_d <= _T_560 @[dec_decode_ctl.scala 594:35] - node _T_561 = neq(i0r.rs2, UInt<5>("h00")) @[dec_decode_ctl.scala 595:60] - node _T_562 = and(i0_dp.rs2, _T_561) @[dec_decode_ctl.scala 595:49] - io.decode_exu.dec_i0_rs2_en_d <= _T_562 @[dec_decode_ctl.scala 595:35] - node _T_563 = neq(i0r.rd, UInt<5>("h00")) @[dec_decode_ctl.scala 596:48] - node i0_rd_en_d = and(i0_dp.rd, _T_563) @[dec_decode_ctl.scala 596:37] - io.dec_i0_rs1_d <= i0r.rs1 @[dec_decode_ctl.scala 597:19] - io.dec_i0_rs2_d <= i0r.rs2 @[dec_decode_ctl.scala 598:19] - node i0_jalimm20 = and(i0_dp.jal, i0_dp.imm20) @[dec_decode_ctl.scala 600:38] - node _T_564 = eq(i0_dp.jal, UInt<1>("h00")) @[dec_decode_ctl.scala 601:27] - node i0_uiimm20 = and(_T_564, i0_dp.imm20) @[dec_decode_ctl.scala 601:38] - node _T_565 = eq(i0_dp.csr_read, UInt<1>("h00")) @[dec_decode_ctl.scala 605:5] + node _T_544 = and(_T_543, lsu_trigger_match_r) @[dec_decode_ctl.scala 571:82] + node _T_545 = or(_T_544, r_t.i0trigger) @[dec_decode_ctl.scala 571:105] + r_t_in.i0trigger <= _T_545 @[dec_decode_ctl.scala 571:33] + r_t_in.pmu_lsu_misaligned <= lsu_pmu_misaligned_r @[dec_decode_ctl.scala 572:33] + node _T_546 = bits(io.dec_tlu_flush_lower_wb, 0, 0) @[dec_decode_ctl.scala 574:35] + when _T_546 : @[dec_decode_ctl.scala 574:43] + wire _T_547 : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[dec_decode_ctl.scala 574:66] + _T_547.pmu_lsu_misaligned <= UInt<1>("h00") @[dec_decode_ctl.scala 574:66] + _T_547.pmu_divide <= UInt<1>("h00") @[dec_decode_ctl.scala 574:66] + _T_547.pmu_i0_br_unpred <= UInt<1>("h00") @[dec_decode_ctl.scala 574:66] + _T_547.pmu_i0_itype <= UInt<4>("h00") @[dec_decode_ctl.scala 574:66] + _T_547.i0trigger <= UInt<4>("h00") @[dec_decode_ctl.scala 574:66] + _T_547.fence_i <= UInt<1>("h00") @[dec_decode_ctl.scala 574:66] + _T_547.icaf_type <= UInt<2>("h00") @[dec_decode_ctl.scala 574:66] + _T_547.icaf_f1 <= UInt<1>("h00") @[dec_decode_ctl.scala 574:66] + _T_547.icaf <= UInt<1>("h00") @[dec_decode_ctl.scala 574:66] + _T_547.legal <= UInt<1>("h00") @[dec_decode_ctl.scala 574:66] + r_t_in.pmu_lsu_misaligned <= _T_547.pmu_lsu_misaligned @[dec_decode_ctl.scala 574:51] + r_t_in.pmu_divide <= _T_547.pmu_divide @[dec_decode_ctl.scala 574:51] + r_t_in.pmu_i0_br_unpred <= _T_547.pmu_i0_br_unpred @[dec_decode_ctl.scala 574:51] + r_t_in.pmu_i0_itype <= _T_547.pmu_i0_itype @[dec_decode_ctl.scala 574:51] + r_t_in.i0trigger <= _T_547.i0trigger @[dec_decode_ctl.scala 574:51] + r_t_in.fence_i <= _T_547.fence_i @[dec_decode_ctl.scala 574:51] + r_t_in.icaf_type <= _T_547.icaf_type @[dec_decode_ctl.scala 574:51] + r_t_in.icaf_f1 <= _T_547.icaf_f1 @[dec_decode_ctl.scala 574:51] + r_t_in.icaf <= _T_547.icaf @[dec_decode_ctl.scala 574:51] + r_t_in.legal <= _T_547.legal @[dec_decode_ctl.scala 574:51] + skip @[dec_decode_ctl.scala 574:43] + io.dec_tlu_packet_r.pmu_lsu_misaligned <= r_t_in.pmu_lsu_misaligned @[dec_decode_ctl.scala 576:39] + io.dec_tlu_packet_r.pmu_divide <= r_t_in.pmu_divide @[dec_decode_ctl.scala 576:39] + io.dec_tlu_packet_r.pmu_i0_br_unpred <= r_t_in.pmu_i0_br_unpred @[dec_decode_ctl.scala 576:39] + io.dec_tlu_packet_r.pmu_i0_itype <= r_t_in.pmu_i0_itype @[dec_decode_ctl.scala 576:39] + io.dec_tlu_packet_r.i0trigger <= r_t_in.i0trigger @[dec_decode_ctl.scala 576:39] + io.dec_tlu_packet_r.fence_i <= r_t_in.fence_i @[dec_decode_ctl.scala 576:39] + io.dec_tlu_packet_r.icaf_type <= r_t_in.icaf_type @[dec_decode_ctl.scala 576:39] + io.dec_tlu_packet_r.icaf_f1 <= r_t_in.icaf_f1 @[dec_decode_ctl.scala 576:39] + io.dec_tlu_packet_r.icaf <= r_t_in.icaf @[dec_decode_ctl.scala 576:39] + io.dec_tlu_packet_r.legal <= r_t_in.legal @[dec_decode_ctl.scala 576:39] + node _T_548 = and(r_d.bits.i0div, r_d.valid) @[dec_decode_ctl.scala 577:58] + io.dec_tlu_packet_r.pmu_divide <= _T_548 @[dec_decode_ctl.scala 577:39] + reg _T_549 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 580:52] + _T_549 <= io.exu_flush_final @[dec_decode_ctl.scala 580:52] + flush_final_r <= _T_549 @[dec_decode_ctl.scala 580:17] + node _T_550 = eq(i0_block_d, UInt<1>("h00")) @[dec_decode_ctl.scala 582:54] + node _T_551 = and(io.dec_ib0_valid_d, _T_550) @[dec_decode_ctl.scala 582:52] + node _T_552 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 582:68] + node _T_553 = and(_T_551, _T_552) @[dec_decode_ctl.scala 582:66] + node _T_554 = eq(flush_final_r, UInt<1>("h00")) @[dec_decode_ctl.scala 582:96] + node _T_555 = and(_T_553, _T_554) @[dec_decode_ctl.scala 582:94] + io.dec_aln.dec_i0_decode_d <= _T_555 @[dec_decode_ctl.scala 582:30] + node _T_556 = bits(io.dec_i0_instr_d, 19, 15) @[dec_decode_ctl.scala 584:16] + i0r.rs1 <= _T_556 @[dec_decode_ctl.scala 584:11] + node _T_557 = bits(io.dec_i0_instr_d, 24, 20) @[dec_decode_ctl.scala 585:16] + i0r.rs2 <= _T_557 @[dec_decode_ctl.scala 585:11] + node _T_558 = bits(io.dec_i0_instr_d, 11, 7) @[dec_decode_ctl.scala 586:16] + i0r.rd <= _T_558 @[dec_decode_ctl.scala 586:11] + node _T_559 = neq(i0r.rs1, UInt<5>("h00")) @[dec_decode_ctl.scala 588:60] + node _T_560 = and(i0_dp.rs1, _T_559) @[dec_decode_ctl.scala 588:49] + io.decode_exu.dec_i0_rs1_en_d <= _T_560 @[dec_decode_ctl.scala 588:35] + node _T_561 = neq(i0r.rs2, UInt<5>("h00")) @[dec_decode_ctl.scala 589:60] + node _T_562 = and(i0_dp.rs2, _T_561) @[dec_decode_ctl.scala 589:49] + io.decode_exu.dec_i0_rs2_en_d <= _T_562 @[dec_decode_ctl.scala 589:35] + node _T_563 = neq(i0r.rd, UInt<5>("h00")) @[dec_decode_ctl.scala 590:48] + node i0_rd_en_d = and(i0_dp.rd, _T_563) @[dec_decode_ctl.scala 590:37] + io.dec_i0_rs1_d <= i0r.rs1 @[dec_decode_ctl.scala 591:19] + io.dec_i0_rs2_d <= i0r.rs2 @[dec_decode_ctl.scala 592:19] + node i0_jalimm20 = and(i0_dp.jal, i0_dp.imm20) @[dec_decode_ctl.scala 594:38] + node _T_564 = eq(i0_dp.jal, UInt<1>("h00")) @[dec_decode_ctl.scala 595:27] + node i0_uiimm20 = and(_T_564, i0_dp.imm20) @[dec_decode_ctl.scala 595:38] + node _T_565 = eq(i0_dp.csr_read, UInt<1>("h00")) @[dec_decode_ctl.scala 599:5] node _T_566 = mux(i0_dp.csr_read, io.dec_csr_rddata_d, UInt<1>("h00")) @[Mux.scala 27:72] node _T_567 = mux(_T_565, i0_immed_d, UInt<1>("h00")) @[Mux.scala 27:72] node _T_568 = or(_T_566, _T_567) @[Mux.scala 27:72] wire _T_569 : UInt<32> @[Mux.scala 27:72] _T_569 <= _T_568 @[Mux.scala 27:72] - io.decode_exu.dec_i0_immed_d <= _T_569 @[dec_decode_ctl.scala 603:32] - node _T_570 = bits(io.dec_i0_instr_d, 31, 31) @[dec_decode_ctl.scala 608:38] + io.decode_exu.dec_i0_immed_d <= _T_569 @[dec_decode_ctl.scala 597:32] + node _T_570 = bits(io.dec_i0_instr_d, 31, 31) @[dec_decode_ctl.scala 602:38] wire _T_571 : UInt<1>[20] @[lib.scala 12:48] _T_571[0] <= _T_570 @[lib.scala 12:48] _T_571[1] <= _T_570 @[lib.scala 12:48] @@ -68508,7 +68508,7 @@ circuit quasar_wrapper : node _T_588 = cat(_T_587, _T_571[17]) @[Cat.scala 29:58] node _T_589 = cat(_T_588, _T_571[18]) @[Cat.scala 29:58] node _T_590 = cat(_T_589, _T_571[19]) @[Cat.scala 29:58] - node _T_591 = bits(io.dec_i0_instr_d, 31, 20) @[dec_decode_ctl.scala 608:46] + node _T_591 = bits(io.dec_i0_instr_d, 31, 20) @[dec_decode_ctl.scala 602:46] node _T_592 = cat(_T_590, _T_591) @[Cat.scala 29:58] wire _T_593 : UInt<1>[27] @[lib.scala 12:48] _T_593[0] <= UInt<1>("h00") @[lib.scala 12:48] @@ -68564,9 +68564,9 @@ circuit quasar_wrapper : node _T_617 = cat(_T_616, _T_593[24]) @[Cat.scala 29:58] node _T_618 = cat(_T_617, _T_593[25]) @[Cat.scala 29:58] node _T_619 = cat(_T_618, _T_593[26]) @[Cat.scala 29:58] - node _T_620 = bits(io.dec_i0_instr_d, 24, 20) @[dec_decode_ctl.scala 609:43] + node _T_620 = bits(io.dec_i0_instr_d, 24, 20) @[dec_decode_ctl.scala 603:43] node _T_621 = cat(_T_619, _T_620) @[Cat.scala 29:58] - node _T_622 = bits(io.dec_i0_instr_d, 31, 31) @[dec_decode_ctl.scala 610:38] + node _T_622 = bits(io.dec_i0_instr_d, 31, 31) @[dec_decode_ctl.scala 604:38] wire _T_623 : UInt<1>[12] @[lib.scala 12:48] _T_623[0] <= _T_622 @[lib.scala 12:48] _T_623[1] <= _T_622 @[lib.scala 12:48] @@ -68591,14 +68591,14 @@ circuit quasar_wrapper : node _T_632 = cat(_T_631, _T_623[9]) @[Cat.scala 29:58] node _T_633 = cat(_T_632, _T_623[10]) @[Cat.scala 29:58] node _T_634 = cat(_T_633, _T_623[11]) @[Cat.scala 29:58] - node _T_635 = bits(io.dec_i0_instr_d, 19, 12) @[dec_decode_ctl.scala 610:46] - node _T_636 = bits(io.dec_i0_instr_d, 20, 20) @[dec_decode_ctl.scala 610:56] - node _T_637 = bits(io.dec_i0_instr_d, 30, 21) @[dec_decode_ctl.scala 610:63] + node _T_635 = bits(io.dec_i0_instr_d, 19, 12) @[dec_decode_ctl.scala 604:46] + node _T_636 = bits(io.dec_i0_instr_d, 20, 20) @[dec_decode_ctl.scala 604:56] + node _T_637 = bits(io.dec_i0_instr_d, 30, 21) @[dec_decode_ctl.scala 604:63] node _T_638 = cat(_T_637, UInt<1>("h00")) @[Cat.scala 29:58] node _T_639 = cat(_T_634, _T_635) @[Cat.scala 29:58] node _T_640 = cat(_T_639, _T_636) @[Cat.scala 29:58] node _T_641 = cat(_T_640, _T_638) @[Cat.scala 29:58] - node _T_642 = bits(io.dec_i0_instr_d, 31, 12) @[dec_decode_ctl.scala 611:30] + node _T_642 = bits(io.dec_i0_instr_d, 31, 12) @[dec_decode_ctl.scala 605:30] wire _T_643 : UInt<1>[12] @[lib.scala 12:48] _T_643[0] <= UInt<1>("h00") @[lib.scala 12:48] _T_643[1] <= UInt<1>("h00") @[lib.scala 12:48] @@ -68624,8 +68624,8 @@ circuit quasar_wrapper : node _T_653 = cat(_T_652, _T_643[10]) @[Cat.scala 29:58] node _T_654 = cat(_T_653, _T_643[11]) @[Cat.scala 29:58] node _T_655 = cat(_T_642, _T_654) @[Cat.scala 29:58] - node _T_656 = and(i0_csr_write_only_d, i0_dp.csr_imm) @[dec_decode_ctl.scala 612:26] - node _T_657 = bits(_T_656, 0, 0) @[dec_decode_ctl.scala 612:43] + node _T_656 = and(i0_csr_write_only_d, i0_dp.csr_imm) @[dec_decode_ctl.scala 606:26] + node _T_657 = bits(_T_656, 0, 0) @[dec_decode_ctl.scala 606:43] wire _T_658 : UInt<1>[27] @[lib.scala 12:48] _T_658[0] <= UInt<1>("h00") @[lib.scala 12:48] _T_658[1] <= UInt<1>("h00") @[lib.scala 12:48] @@ -68680,7 +68680,7 @@ circuit quasar_wrapper : node _T_682 = cat(_T_681, _T_658[24]) @[Cat.scala 29:58] node _T_683 = cat(_T_682, _T_658[25]) @[Cat.scala 29:58] node _T_684 = cat(_T_683, _T_658[26]) @[Cat.scala 29:58] - node _T_685 = bits(io.dec_i0_instr_d, 19, 15) @[dec_decode_ctl.scala 612:72] + node _T_685 = bits(io.dec_i0_instr_d, 19, 15) @[dec_decode_ctl.scala 606:72] node _T_686 = cat(_T_684, _T_685) @[Cat.scala 29:58] node _T_687 = mux(i0_dp.imm12, _T_592, UInt<1>("h00")) @[Mux.scala 27:72] node _T_688 = mux(i0_dp.shimm5, _T_621, UInt<1>("h00")) @[Mux.scala 27:72] @@ -68693,649 +68693,657 @@ circuit quasar_wrapper : node _T_695 = or(_T_694, _T_691) @[Mux.scala 27:72] wire _T_696 : UInt<32> @[Mux.scala 27:72] _T_696 <= _T_695 @[Mux.scala 27:72] - i0_immed_d <= _T_696 @[dec_decode_ctl.scala 607:14] - node _T_697 = and(io.dec_aln.dec_i0_decode_d, i0_legal) @[dec_decode_ctl.scala 614:54] - i0_legal_decode_d <= _T_697 @[dec_decode_ctl.scala 614:24] - node _T_698 = and(i0_dp.mul, i0_legal_decode_d) @[dec_decode_ctl.scala 616:44] - i0_d_c.mul <= _T_698 @[dec_decode_ctl.scala 616:29] - node _T_699 = and(i0_dp.load, i0_legal_decode_d) @[dec_decode_ctl.scala 617:44] - i0_d_c.load <= _T_699 @[dec_decode_ctl.scala 617:29] - node _T_700 = and(i0_dp.alu, i0_legal_decode_d) @[dec_decode_ctl.scala 618:44] - i0_d_c.alu <= _T_700 @[dec_decode_ctl.scala 618:29] - node _T_701 = bits(i0_x_ctl_en, 0, 0) @[dec_decode_ctl.scala 620:71] - reg i0_x_c : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>}, io.active_clk @[Reg.scala 15:16] - when _T_701 : @[Reg.scala 16:19] - i0_x_c.alu <= i0_d_c.alu @[Reg.scala 16:23] - i0_x_c.load <= i0_d_c.load @[Reg.scala 16:23] - i0_x_c.mul <= i0_d_c.mul @[Reg.scala 16:23] - skip @[Reg.scala 16:19] - node _T_702 = bits(i0_r_ctl_en, 0, 0) @[dec_decode_ctl.scala 621:71] - reg i0_r_c : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>}, io.active_clk @[Reg.scala 15:16] - when _T_702 : @[Reg.scala 16:19] - i0_r_c.alu <= i0_x_c.alu @[Reg.scala 16:23] - i0_r_c.load <= i0_x_c.load @[Reg.scala 16:23] - i0_r_c.mul <= i0_x_c.mul @[Reg.scala 16:23] - skip @[Reg.scala 16:19] - node _T_703 = bits(i0_pipe_en, 3, 1) @[dec_decode_ctl.scala 622:91] - reg _T_704 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 622:80] - _T_704 <= _T_703 @[dec_decode_ctl.scala 622:80] - node _T_705 = cat(io.dec_aln.dec_i0_decode_d, _T_704) @[Cat.scala 29:58] - i0_pipe_en <= _T_705 @[dec_decode_ctl.scala 622:14] - node _T_706 = bits(i0_pipe_en, 3, 2) @[dec_decode_ctl.scala 624:43] - node _T_707 = orr(_T_706) @[dec_decode_ctl.scala 624:49] - node _T_708 = or(_T_707, io.clk_override) @[dec_decode_ctl.scala 624:53] - i0_x_ctl_en <= _T_708 @[dec_decode_ctl.scala 624:29] - node _T_709 = bits(i0_pipe_en, 2, 1) @[dec_decode_ctl.scala 625:43] - node _T_710 = orr(_T_709) @[dec_decode_ctl.scala 625:49] - node _T_711 = or(_T_710, io.clk_override) @[dec_decode_ctl.scala 625:53] - i0_r_ctl_en <= _T_711 @[dec_decode_ctl.scala 625:29] - node _T_712 = bits(i0_pipe_en, 1, 0) @[dec_decode_ctl.scala 626:43] - node _T_713 = orr(_T_712) @[dec_decode_ctl.scala 626:49] - node _T_714 = or(_T_713, io.clk_override) @[dec_decode_ctl.scala 626:53] - i0_wb_ctl_en <= _T_714 @[dec_decode_ctl.scala 626:29] - node _T_715 = bits(i0_pipe_en, 3, 3) @[dec_decode_ctl.scala 627:44] - node _T_716 = or(_T_715, io.clk_override) @[dec_decode_ctl.scala 627:50] - i0_x_data_en <= _T_716 @[dec_decode_ctl.scala 627:29] - node _T_717 = bits(i0_pipe_en, 2, 2) @[dec_decode_ctl.scala 628:44] - node _T_718 = or(_T_717, io.clk_override) @[dec_decode_ctl.scala 628:50] - i0_r_data_en <= _T_718 @[dec_decode_ctl.scala 628:29] - node _T_719 = bits(i0_pipe_en, 1, 1) @[dec_decode_ctl.scala 629:44] - node _T_720 = or(_T_719, io.clk_override) @[dec_decode_ctl.scala 629:50] - i0_wb_data_en <= _T_720 @[dec_decode_ctl.scala 629:29] - node _T_721 = bits(i0_pipe_en, 0, 0) @[dec_decode_ctl.scala 630:44] - node _T_722 = or(_T_721, io.clk_override) @[dec_decode_ctl.scala 630:50] - i0_wb1_data_en <= _T_722 @[dec_decode_ctl.scala 630:29] - node _T_723 = cat(i0_x_data_en, i0_r_data_en) @[Cat.scala 29:58] - io.decode_exu.dec_data_en <= _T_723 @[dec_decode_ctl.scala 632:38] - node _T_724 = cat(i0_x_ctl_en, i0_r_ctl_en) @[Cat.scala 29:58] - io.decode_exu.dec_ctl_en <= _T_724 @[dec_decode_ctl.scala 633:38] - d_d.bits.i0rd <= i0r.rd @[dec_decode_ctl.scala 635:34] - node _T_725 = and(i0_rd_en_d, i0_legal_decode_d) @[dec_decode_ctl.scala 636:50] - d_d.bits.i0v <= _T_725 @[dec_decode_ctl.scala 636:34] - d_d.valid <= io.dec_aln.dec_i0_decode_d @[dec_decode_ctl.scala 637:27] - node _T_726 = and(i0_dp.load, i0_legal_decode_d) @[dec_decode_ctl.scala 639:50] - d_d.bits.i0load <= _T_726 @[dec_decode_ctl.scala 639:34] - node _T_727 = and(i0_dp.store, i0_legal_decode_d) @[dec_decode_ctl.scala 640:50] - d_d.bits.i0store <= _T_727 @[dec_decode_ctl.scala 640:34] - node _T_728 = and(i0_dp.div, i0_legal_decode_d) @[dec_decode_ctl.scala 641:50] - d_d.bits.i0div <= _T_728 @[dec_decode_ctl.scala 641:34] - node _T_729 = and(io.dec_csr_wen_unq_d, i0_legal_decode_d) @[dec_decode_ctl.scala 643:61] - d_d.bits.csrwen <= _T_729 @[dec_decode_ctl.scala 643:34] - node _T_730 = and(i0_csr_write_only_d, io.dec_aln.dec_i0_decode_d) @[dec_decode_ctl.scala 644:58] - d_d.bits.csrwonly <= _T_730 @[dec_decode_ctl.scala 644:34] - node _T_731 = bits(io.dec_i0_instr_d, 31, 20) @[dec_decode_ctl.scala 645:40] - d_d.bits.csrwaddr <= _T_731 @[dec_decode_ctl.scala 645:34] - node _T_732 = bits(i0_x_ctl_en, 0, 0) @[dec_decode_ctl.scala 647:34] + i0_immed_d <= _T_696 @[dec_decode_ctl.scala 601:14] + node _T_697 = and(io.dec_aln.dec_i0_decode_d, i0_legal) @[dec_decode_ctl.scala 608:54] + i0_legal_decode_d <= _T_697 @[dec_decode_ctl.scala 608:24] + node _T_698 = and(i0_dp.mul, i0_legal_decode_d) @[dec_decode_ctl.scala 610:44] + i0_d_c.mul <= _T_698 @[dec_decode_ctl.scala 610:29] + node _T_699 = and(i0_dp.load, i0_legal_decode_d) @[dec_decode_ctl.scala 611:44] + i0_d_c.load <= _T_699 @[dec_decode_ctl.scala 611:29] + node _T_700 = and(i0_dp.alu, i0_legal_decode_d) @[dec_decode_ctl.scala 612:44] + i0_d_c.alu <= _T_700 @[dec_decode_ctl.scala 612:29] + wire _T_701 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 614:70] + _T_701.alu <= UInt<1>("h00") @[dec_decode_ctl.scala 614:70] + _T_701.load <= UInt<1>("h00") @[dec_decode_ctl.scala 614:70] + _T_701.mul <= UInt<1>("h00") @[dec_decode_ctl.scala 614:70] + node _T_702 = bits(i0_x_ctl_en, 0, 0) @[dec_decode_ctl.scala 614:92] + reg i0_x_c : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>}, io.active_clk with : (reset => (reset, _T_701)) @[Reg.scala 27:20] + when _T_702 : @[Reg.scala 28:19] + i0_x_c.alu <= i0_d_c.alu @[Reg.scala 28:23] + i0_x_c.load <= i0_d_c.load @[Reg.scala 28:23] + i0_x_c.mul <= i0_d_c.mul @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + wire _T_703 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 615:70] + _T_703.alu <= UInt<1>("h00") @[dec_decode_ctl.scala 615:70] + _T_703.load <= UInt<1>("h00") @[dec_decode_ctl.scala 615:70] + _T_703.mul <= UInt<1>("h00") @[dec_decode_ctl.scala 615:70] + node _T_704 = bits(i0_r_ctl_en, 0, 0) @[dec_decode_ctl.scala 615:92] + reg i0_r_c : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>}, io.active_clk with : (reset => (reset, _T_703)) @[Reg.scala 27:20] + when _T_704 : @[Reg.scala 28:19] + i0_r_c.alu <= i0_x_c.alu @[Reg.scala 28:23] + i0_r_c.load <= i0_x_c.load @[Reg.scala 28:23] + i0_r_c.mul <= i0_x_c.mul @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_705 = bits(i0_pipe_en, 3, 1) @[dec_decode_ctl.scala 616:91] + reg _T_706 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 616:80] + _T_706 <= _T_705 @[dec_decode_ctl.scala 616:80] + node _T_707 = cat(io.dec_aln.dec_i0_decode_d, _T_706) @[Cat.scala 29:58] + i0_pipe_en <= _T_707 @[dec_decode_ctl.scala 616:14] + node _T_708 = bits(i0_pipe_en, 3, 2) @[dec_decode_ctl.scala 618:43] + node _T_709 = orr(_T_708) @[dec_decode_ctl.scala 618:49] + node _T_710 = or(_T_709, io.clk_override) @[dec_decode_ctl.scala 618:53] + i0_x_ctl_en <= _T_710 @[dec_decode_ctl.scala 618:29] + node _T_711 = bits(i0_pipe_en, 2, 1) @[dec_decode_ctl.scala 619:43] + node _T_712 = orr(_T_711) @[dec_decode_ctl.scala 619:49] + node _T_713 = or(_T_712, io.clk_override) @[dec_decode_ctl.scala 619:53] + i0_r_ctl_en <= _T_713 @[dec_decode_ctl.scala 619:29] + node _T_714 = bits(i0_pipe_en, 1, 0) @[dec_decode_ctl.scala 620:43] + node _T_715 = orr(_T_714) @[dec_decode_ctl.scala 620:49] + node _T_716 = or(_T_715, io.clk_override) @[dec_decode_ctl.scala 620:53] + i0_wb_ctl_en <= _T_716 @[dec_decode_ctl.scala 620:29] + node _T_717 = bits(i0_pipe_en, 3, 3) @[dec_decode_ctl.scala 621:44] + node _T_718 = or(_T_717, io.clk_override) @[dec_decode_ctl.scala 621:50] + i0_x_data_en <= _T_718 @[dec_decode_ctl.scala 621:29] + node _T_719 = bits(i0_pipe_en, 2, 2) @[dec_decode_ctl.scala 622:44] + node _T_720 = or(_T_719, io.clk_override) @[dec_decode_ctl.scala 622:50] + i0_r_data_en <= _T_720 @[dec_decode_ctl.scala 622:29] + node _T_721 = bits(i0_pipe_en, 1, 1) @[dec_decode_ctl.scala 623:44] + node _T_722 = or(_T_721, io.clk_override) @[dec_decode_ctl.scala 623:50] + i0_wb_data_en <= _T_722 @[dec_decode_ctl.scala 623:29] + node _T_723 = bits(i0_pipe_en, 0, 0) @[dec_decode_ctl.scala 624:44] + node _T_724 = or(_T_723, io.clk_override) @[dec_decode_ctl.scala 624:50] + i0_wb1_data_en <= _T_724 @[dec_decode_ctl.scala 624:29] + node _T_725 = cat(i0_x_data_en, i0_r_data_en) @[Cat.scala 29:58] + io.decode_exu.dec_data_en <= _T_725 @[dec_decode_ctl.scala 626:38] + node _T_726 = cat(i0_x_ctl_en, i0_r_ctl_en) @[Cat.scala 29:58] + io.decode_exu.dec_ctl_en <= _T_726 @[dec_decode_ctl.scala 627:38] + d_d.bits.i0rd <= i0r.rd @[dec_decode_ctl.scala 629:34] + node _T_727 = and(i0_rd_en_d, i0_legal_decode_d) @[dec_decode_ctl.scala 630:50] + d_d.bits.i0v <= _T_727 @[dec_decode_ctl.scala 630:34] + d_d.valid <= io.dec_aln.dec_i0_decode_d @[dec_decode_ctl.scala 631:27] + node _T_728 = and(i0_dp.load, i0_legal_decode_d) @[dec_decode_ctl.scala 633:50] + d_d.bits.i0load <= _T_728 @[dec_decode_ctl.scala 633:34] + node _T_729 = and(i0_dp.store, i0_legal_decode_d) @[dec_decode_ctl.scala 634:50] + d_d.bits.i0store <= _T_729 @[dec_decode_ctl.scala 634:34] + node _T_730 = and(i0_dp.div, i0_legal_decode_d) @[dec_decode_ctl.scala 635:50] + d_d.bits.i0div <= _T_730 @[dec_decode_ctl.scala 635:34] + node _T_731 = and(io.dec_csr_wen_unq_d, i0_legal_decode_d) @[dec_decode_ctl.scala 637:61] + d_d.bits.csrwen <= _T_731 @[dec_decode_ctl.scala 637:34] + node _T_732 = and(i0_csr_write_only_d, io.dec_aln.dec_i0_decode_d) @[dec_decode_ctl.scala 638:58] + d_d.bits.csrwonly <= _T_732 @[dec_decode_ctl.scala 638:34] + node _T_733 = bits(io.dec_i0_instr_d, 31, 20) @[dec_decode_ctl.scala 639:40] + d_d.bits.csrwaddr <= _T_733 @[dec_decode_ctl.scala 639:34] + node _T_734 = bits(i0_x_ctl_en, 0, 0) @[dec_decode_ctl.scala 641:34] inst rvclkhdr_7 of rvclkhdr_668 @[lib.scala 378:23] rvclkhdr_7.clock <= clock rvclkhdr_7.reset <= reset rvclkhdr_7.io.clk <= clock @[lib.scala 380:18] - rvclkhdr_7.io.en <= _T_732 @[lib.scala 381:17] + rvclkhdr_7.io.en <= _T_734 @[lib.scala 381:17] rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 382:24] - wire _T_733 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[lib.scala 384:33] - _T_733.bits.csrwaddr <= UInt<12>("h00") @[lib.scala 384:33] - _T_733.bits.csrwonly <= UInt<1>("h00") @[lib.scala 384:33] - _T_733.bits.csrwen <= UInt<1>("h00") @[lib.scala 384:33] - _T_733.bits.i0v <= UInt<1>("h00") @[lib.scala 384:33] - _T_733.bits.i0div <= UInt<1>("h00") @[lib.scala 384:33] - _T_733.bits.i0store <= UInt<1>("h00") @[lib.scala 384:33] - _T_733.bits.i0load <= UInt<1>("h00") @[lib.scala 384:33] - _T_733.bits.i0rd <= UInt<5>("h00") @[lib.scala 384:33] - _T_733.valid <= UInt<1>("h00") @[lib.scala 384:33] - reg _T_734 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}}, rvclkhdr_7.io.l1clk with : (reset => (reset, _T_733)) @[lib.scala 384:16] - _T_734.bits.csrwaddr <= d_d.bits.csrwaddr @[lib.scala 384:16] - _T_734.bits.csrwonly <= d_d.bits.csrwonly @[lib.scala 384:16] - _T_734.bits.csrwen <= d_d.bits.csrwen @[lib.scala 384:16] - _T_734.bits.i0v <= d_d.bits.i0v @[lib.scala 384:16] - _T_734.bits.i0div <= d_d.bits.i0div @[lib.scala 384:16] - _T_734.bits.i0store <= d_d.bits.i0store @[lib.scala 384:16] - _T_734.bits.i0load <= d_d.bits.i0load @[lib.scala 384:16] - _T_734.bits.i0rd <= d_d.bits.i0rd @[lib.scala 384:16] - _T_734.valid <= d_d.valid @[lib.scala 384:16] - x_d.bits.csrwaddr <= _T_734.bits.csrwaddr @[dec_decode_ctl.scala 647:7] - x_d.bits.csrwonly <= _T_734.bits.csrwonly @[dec_decode_ctl.scala 647:7] - x_d.bits.csrwen <= _T_734.bits.csrwen @[dec_decode_ctl.scala 647:7] - x_d.bits.i0v <= _T_734.bits.i0v @[dec_decode_ctl.scala 647:7] - x_d.bits.i0div <= _T_734.bits.i0div @[dec_decode_ctl.scala 647:7] - x_d.bits.i0store <= _T_734.bits.i0store @[dec_decode_ctl.scala 647:7] - x_d.bits.i0load <= _T_734.bits.i0load @[dec_decode_ctl.scala 647:7] - x_d.bits.i0rd <= _T_734.bits.i0rd @[dec_decode_ctl.scala 647:7] - x_d.valid <= _T_734.valid @[dec_decode_ctl.scala 647:7] - wire x_d_in : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[dec_decode_ctl.scala 648:20] - x_d_in.bits.csrwaddr <= x_d.bits.csrwaddr @[dec_decode_ctl.scala 649:10] - x_d_in.bits.csrwonly <= x_d.bits.csrwonly @[dec_decode_ctl.scala 649:10] - x_d_in.bits.csrwen <= x_d.bits.csrwen @[dec_decode_ctl.scala 649:10] - x_d_in.bits.i0v <= x_d.bits.i0v @[dec_decode_ctl.scala 649:10] - x_d_in.bits.i0div <= x_d.bits.i0div @[dec_decode_ctl.scala 649:10] - x_d_in.bits.i0store <= x_d.bits.i0store @[dec_decode_ctl.scala 649:10] - x_d_in.bits.i0load <= x_d.bits.i0load @[dec_decode_ctl.scala 649:10] - x_d_in.bits.i0rd <= x_d.bits.i0rd @[dec_decode_ctl.scala 649:10] - x_d_in.valid <= x_d.valid @[dec_decode_ctl.scala 649:10] - node _T_735 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 650:49] - node _T_736 = and(x_d.bits.i0v, _T_735) @[dec_decode_ctl.scala 650:47] - node _T_737 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 650:78] - node _T_738 = and(_T_736, _T_737) @[dec_decode_ctl.scala 650:76] - x_d_in.bits.i0v <= _T_738 @[dec_decode_ctl.scala 650:27] - node _T_739 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 651:35] - node _T_740 = and(x_d.valid, _T_739) @[dec_decode_ctl.scala 651:33] - node _T_741 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 651:64] - node _T_742 = and(_T_740, _T_741) @[dec_decode_ctl.scala 651:62] - x_d_in.valid <= _T_742 @[dec_decode_ctl.scala 651:20] - node _T_743 = bits(i0_r_ctl_en, 0, 0) @[dec_decode_ctl.scala 653:36] + wire _T_735 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[lib.scala 384:33] + _T_735.bits.csrwaddr <= UInt<12>("h00") @[lib.scala 384:33] + _T_735.bits.csrwonly <= UInt<1>("h00") @[lib.scala 384:33] + _T_735.bits.csrwen <= UInt<1>("h00") @[lib.scala 384:33] + _T_735.bits.i0v <= UInt<1>("h00") @[lib.scala 384:33] + _T_735.bits.i0div <= UInt<1>("h00") @[lib.scala 384:33] + _T_735.bits.i0store <= UInt<1>("h00") @[lib.scala 384:33] + _T_735.bits.i0load <= UInt<1>("h00") @[lib.scala 384:33] + _T_735.bits.i0rd <= UInt<5>("h00") @[lib.scala 384:33] + _T_735.valid <= UInt<1>("h00") @[lib.scala 384:33] + reg _T_736 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}}, rvclkhdr_7.io.l1clk with : (reset => (reset, _T_735)) @[lib.scala 384:16] + _T_736.bits.csrwaddr <= d_d.bits.csrwaddr @[lib.scala 384:16] + _T_736.bits.csrwonly <= d_d.bits.csrwonly @[lib.scala 384:16] + _T_736.bits.csrwen <= d_d.bits.csrwen @[lib.scala 384:16] + _T_736.bits.i0v <= d_d.bits.i0v @[lib.scala 384:16] + _T_736.bits.i0div <= d_d.bits.i0div @[lib.scala 384:16] + _T_736.bits.i0store <= d_d.bits.i0store @[lib.scala 384:16] + _T_736.bits.i0load <= d_d.bits.i0load @[lib.scala 384:16] + _T_736.bits.i0rd <= d_d.bits.i0rd @[lib.scala 384:16] + _T_736.valid <= d_d.valid @[lib.scala 384:16] + x_d.bits.csrwaddr <= _T_736.bits.csrwaddr @[dec_decode_ctl.scala 641:7] + x_d.bits.csrwonly <= _T_736.bits.csrwonly @[dec_decode_ctl.scala 641:7] + x_d.bits.csrwen <= _T_736.bits.csrwen @[dec_decode_ctl.scala 641:7] + x_d.bits.i0v <= _T_736.bits.i0v @[dec_decode_ctl.scala 641:7] + x_d.bits.i0div <= _T_736.bits.i0div @[dec_decode_ctl.scala 641:7] + x_d.bits.i0store <= _T_736.bits.i0store @[dec_decode_ctl.scala 641:7] + x_d.bits.i0load <= _T_736.bits.i0load @[dec_decode_ctl.scala 641:7] + x_d.bits.i0rd <= _T_736.bits.i0rd @[dec_decode_ctl.scala 641:7] + x_d.valid <= _T_736.valid @[dec_decode_ctl.scala 641:7] + wire x_d_in : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[dec_decode_ctl.scala 642:20] + x_d_in.bits.csrwaddr <= x_d.bits.csrwaddr @[dec_decode_ctl.scala 643:10] + x_d_in.bits.csrwonly <= x_d.bits.csrwonly @[dec_decode_ctl.scala 643:10] + x_d_in.bits.csrwen <= x_d.bits.csrwen @[dec_decode_ctl.scala 643:10] + x_d_in.bits.i0v <= x_d.bits.i0v @[dec_decode_ctl.scala 643:10] + x_d_in.bits.i0div <= x_d.bits.i0div @[dec_decode_ctl.scala 643:10] + x_d_in.bits.i0store <= x_d.bits.i0store @[dec_decode_ctl.scala 643:10] + x_d_in.bits.i0load <= x_d.bits.i0load @[dec_decode_ctl.scala 643:10] + x_d_in.bits.i0rd <= x_d.bits.i0rd @[dec_decode_ctl.scala 643:10] + x_d_in.valid <= x_d.valid @[dec_decode_ctl.scala 643:10] + node _T_737 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 644:49] + node _T_738 = and(x_d.bits.i0v, _T_737) @[dec_decode_ctl.scala 644:47] + node _T_739 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 644:78] + node _T_740 = and(_T_738, _T_739) @[dec_decode_ctl.scala 644:76] + x_d_in.bits.i0v <= _T_740 @[dec_decode_ctl.scala 644:27] + node _T_741 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 645:35] + node _T_742 = and(x_d.valid, _T_741) @[dec_decode_ctl.scala 645:33] + node _T_743 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[dec_decode_ctl.scala 645:64] + node _T_744 = and(_T_742, _T_743) @[dec_decode_ctl.scala 645:62] + x_d_in.valid <= _T_744 @[dec_decode_ctl.scala 645:20] + node _T_745 = bits(i0_r_ctl_en, 0, 0) @[dec_decode_ctl.scala 647:36] inst rvclkhdr_8 of rvclkhdr_669 @[lib.scala 378:23] rvclkhdr_8.clock <= clock rvclkhdr_8.reset <= reset rvclkhdr_8.io.clk <= clock @[lib.scala 380:18] - rvclkhdr_8.io.en <= _T_743 @[lib.scala 381:17] + rvclkhdr_8.io.en <= _T_745 @[lib.scala 381:17] rvclkhdr_8.io.scan_mode <= io.scan_mode @[lib.scala 382:24] - wire _T_744 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[lib.scala 384:33] - _T_744.bits.csrwaddr <= UInt<12>("h00") @[lib.scala 384:33] - _T_744.bits.csrwonly <= UInt<1>("h00") @[lib.scala 384:33] - _T_744.bits.csrwen <= UInt<1>("h00") @[lib.scala 384:33] - _T_744.bits.i0v <= UInt<1>("h00") @[lib.scala 384:33] - _T_744.bits.i0div <= UInt<1>("h00") @[lib.scala 384:33] - _T_744.bits.i0store <= UInt<1>("h00") @[lib.scala 384:33] - _T_744.bits.i0load <= UInt<1>("h00") @[lib.scala 384:33] - _T_744.bits.i0rd <= UInt<5>("h00") @[lib.scala 384:33] - _T_744.valid <= UInt<1>("h00") @[lib.scala 384:33] - reg _T_745 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}}, rvclkhdr_8.io.l1clk with : (reset => (reset, _T_744)) @[lib.scala 384:16] - _T_745.bits.csrwaddr <= x_d_in.bits.csrwaddr @[lib.scala 384:16] - _T_745.bits.csrwonly <= x_d_in.bits.csrwonly @[lib.scala 384:16] - _T_745.bits.csrwen <= x_d_in.bits.csrwen @[lib.scala 384:16] - _T_745.bits.i0v <= x_d_in.bits.i0v @[lib.scala 384:16] - _T_745.bits.i0div <= x_d_in.bits.i0div @[lib.scala 384:16] - _T_745.bits.i0store <= x_d_in.bits.i0store @[lib.scala 384:16] - _T_745.bits.i0load <= x_d_in.bits.i0load @[lib.scala 384:16] - _T_745.bits.i0rd <= x_d_in.bits.i0rd @[lib.scala 384:16] - _T_745.valid <= x_d_in.valid @[lib.scala 384:16] - r_d.bits.csrwaddr <= _T_745.bits.csrwaddr @[dec_decode_ctl.scala 653:7] - r_d.bits.csrwonly <= _T_745.bits.csrwonly @[dec_decode_ctl.scala 653:7] - r_d.bits.csrwen <= _T_745.bits.csrwen @[dec_decode_ctl.scala 653:7] - r_d.bits.i0v <= _T_745.bits.i0v @[dec_decode_ctl.scala 653:7] - r_d.bits.i0div <= _T_745.bits.i0div @[dec_decode_ctl.scala 653:7] - r_d.bits.i0store <= _T_745.bits.i0store @[dec_decode_ctl.scala 653:7] - r_d.bits.i0load <= _T_745.bits.i0load @[dec_decode_ctl.scala 653:7] - r_d.bits.i0rd <= _T_745.bits.i0rd @[dec_decode_ctl.scala 653:7] - r_d.valid <= _T_745.valid @[dec_decode_ctl.scala 653:7] - r_d_in.bits.csrwaddr <= r_d.bits.csrwaddr @[dec_decode_ctl.scala 654:10] - r_d_in.bits.csrwonly <= r_d.bits.csrwonly @[dec_decode_ctl.scala 654:10] - r_d_in.bits.csrwen <= r_d.bits.csrwen @[dec_decode_ctl.scala 654:10] - r_d_in.bits.i0v <= r_d.bits.i0v @[dec_decode_ctl.scala 654:10] - r_d_in.bits.i0div <= r_d.bits.i0div @[dec_decode_ctl.scala 654:10] - r_d_in.bits.i0store <= r_d.bits.i0store @[dec_decode_ctl.scala 654:10] - r_d_in.bits.i0load <= r_d.bits.i0load @[dec_decode_ctl.scala 654:10] - r_d_in.bits.i0rd <= r_d.bits.i0rd @[dec_decode_ctl.scala 654:10] - r_d_in.valid <= r_d.valid @[dec_decode_ctl.scala 654:10] - r_d_in.bits.i0rd <= r_d.bits.i0rd @[dec_decode_ctl.scala 655:22] - node _T_746 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 657:51] - node _T_747 = and(r_d.bits.i0v, _T_746) @[dec_decode_ctl.scala 657:49] - r_d_in.bits.i0v <= _T_747 @[dec_decode_ctl.scala 657:27] - node _T_748 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 658:37] - node _T_749 = and(r_d.valid, _T_748) @[dec_decode_ctl.scala 658:35] - r_d_in.valid <= _T_749 @[dec_decode_ctl.scala 658:20] - node _T_750 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 659:51] - node _T_751 = and(r_d.bits.i0load, _T_750) @[dec_decode_ctl.scala 659:49] - r_d_in.bits.i0load <= _T_751 @[dec_decode_ctl.scala 659:27] - node _T_752 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 660:51] - node _T_753 = and(r_d.bits.i0store, _T_752) @[dec_decode_ctl.scala 660:49] - r_d_in.bits.i0store <= _T_753 @[dec_decode_ctl.scala 660:27] - node _T_754 = bits(i0_wb_ctl_en, 0, 0) @[dec_decode_ctl.scala 662:37] + wire _T_746 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[lib.scala 384:33] + _T_746.bits.csrwaddr <= UInt<12>("h00") @[lib.scala 384:33] + _T_746.bits.csrwonly <= UInt<1>("h00") @[lib.scala 384:33] + _T_746.bits.csrwen <= UInt<1>("h00") @[lib.scala 384:33] + _T_746.bits.i0v <= UInt<1>("h00") @[lib.scala 384:33] + _T_746.bits.i0div <= UInt<1>("h00") @[lib.scala 384:33] + _T_746.bits.i0store <= UInt<1>("h00") @[lib.scala 384:33] + _T_746.bits.i0load <= UInt<1>("h00") @[lib.scala 384:33] + _T_746.bits.i0rd <= UInt<5>("h00") @[lib.scala 384:33] + _T_746.valid <= UInt<1>("h00") @[lib.scala 384:33] + reg _T_747 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}}, rvclkhdr_8.io.l1clk with : (reset => (reset, _T_746)) @[lib.scala 384:16] + _T_747.bits.csrwaddr <= x_d_in.bits.csrwaddr @[lib.scala 384:16] + _T_747.bits.csrwonly <= x_d_in.bits.csrwonly @[lib.scala 384:16] + _T_747.bits.csrwen <= x_d_in.bits.csrwen @[lib.scala 384:16] + _T_747.bits.i0v <= x_d_in.bits.i0v @[lib.scala 384:16] + _T_747.bits.i0div <= x_d_in.bits.i0div @[lib.scala 384:16] + _T_747.bits.i0store <= x_d_in.bits.i0store @[lib.scala 384:16] + _T_747.bits.i0load <= x_d_in.bits.i0load @[lib.scala 384:16] + _T_747.bits.i0rd <= x_d_in.bits.i0rd @[lib.scala 384:16] + _T_747.valid <= x_d_in.valid @[lib.scala 384:16] + r_d.bits.csrwaddr <= _T_747.bits.csrwaddr @[dec_decode_ctl.scala 647:7] + r_d.bits.csrwonly <= _T_747.bits.csrwonly @[dec_decode_ctl.scala 647:7] + r_d.bits.csrwen <= _T_747.bits.csrwen @[dec_decode_ctl.scala 647:7] + r_d.bits.i0v <= _T_747.bits.i0v @[dec_decode_ctl.scala 647:7] + r_d.bits.i0div <= _T_747.bits.i0div @[dec_decode_ctl.scala 647:7] + r_d.bits.i0store <= _T_747.bits.i0store @[dec_decode_ctl.scala 647:7] + r_d.bits.i0load <= _T_747.bits.i0load @[dec_decode_ctl.scala 647:7] + r_d.bits.i0rd <= _T_747.bits.i0rd @[dec_decode_ctl.scala 647:7] + r_d.valid <= _T_747.valid @[dec_decode_ctl.scala 647:7] + r_d_in.bits.csrwaddr <= r_d.bits.csrwaddr @[dec_decode_ctl.scala 648:10] + r_d_in.bits.csrwonly <= r_d.bits.csrwonly @[dec_decode_ctl.scala 648:10] + r_d_in.bits.csrwen <= r_d.bits.csrwen @[dec_decode_ctl.scala 648:10] + r_d_in.bits.i0v <= r_d.bits.i0v @[dec_decode_ctl.scala 648:10] + r_d_in.bits.i0div <= r_d.bits.i0div @[dec_decode_ctl.scala 648:10] + r_d_in.bits.i0store <= r_d.bits.i0store @[dec_decode_ctl.scala 648:10] + r_d_in.bits.i0load <= r_d.bits.i0load @[dec_decode_ctl.scala 648:10] + r_d_in.bits.i0rd <= r_d.bits.i0rd @[dec_decode_ctl.scala 648:10] + r_d_in.valid <= r_d.valid @[dec_decode_ctl.scala 648:10] + r_d_in.bits.i0rd <= r_d.bits.i0rd @[dec_decode_ctl.scala 649:22] + node _T_748 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 651:51] + node _T_749 = and(r_d.bits.i0v, _T_748) @[dec_decode_ctl.scala 651:49] + r_d_in.bits.i0v <= _T_749 @[dec_decode_ctl.scala 651:27] + node _T_750 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 652:37] + node _T_751 = and(r_d.valid, _T_750) @[dec_decode_ctl.scala 652:35] + r_d_in.valid <= _T_751 @[dec_decode_ctl.scala 652:20] + node _T_752 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 653:51] + node _T_753 = and(r_d.bits.i0load, _T_752) @[dec_decode_ctl.scala 653:49] + r_d_in.bits.i0load <= _T_753 @[dec_decode_ctl.scala 653:27] + node _T_754 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[dec_decode_ctl.scala 654:51] + node _T_755 = and(r_d.bits.i0store, _T_754) @[dec_decode_ctl.scala 654:49] + r_d_in.bits.i0store <= _T_755 @[dec_decode_ctl.scala 654:27] + node _T_756 = bits(i0_wb_ctl_en, 0, 0) @[dec_decode_ctl.scala 656:37] inst rvclkhdr_9 of rvclkhdr_670 @[lib.scala 378:23] rvclkhdr_9.clock <= clock rvclkhdr_9.reset <= reset rvclkhdr_9.io.clk <= clock @[lib.scala 380:18] - rvclkhdr_9.io.en <= _T_754 @[lib.scala 381:17] + rvclkhdr_9.io.en <= _T_756 @[lib.scala 381:17] rvclkhdr_9.io.scan_mode <= io.scan_mode @[lib.scala 382:24] - wire _T_755 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[lib.scala 384:33] - _T_755.bits.csrwaddr <= UInt<12>("h00") @[lib.scala 384:33] - _T_755.bits.csrwonly <= UInt<1>("h00") @[lib.scala 384:33] - _T_755.bits.csrwen <= UInt<1>("h00") @[lib.scala 384:33] - _T_755.bits.i0v <= UInt<1>("h00") @[lib.scala 384:33] - _T_755.bits.i0div <= UInt<1>("h00") @[lib.scala 384:33] - _T_755.bits.i0store <= UInt<1>("h00") @[lib.scala 384:33] - _T_755.bits.i0load <= UInt<1>("h00") @[lib.scala 384:33] - _T_755.bits.i0rd <= UInt<5>("h00") @[lib.scala 384:33] - _T_755.valid <= UInt<1>("h00") @[lib.scala 384:33] - reg _T_756 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}}, rvclkhdr_9.io.l1clk with : (reset => (reset, _T_755)) @[lib.scala 384:16] - _T_756.bits.csrwaddr <= r_d_in.bits.csrwaddr @[lib.scala 384:16] - _T_756.bits.csrwonly <= r_d_in.bits.csrwonly @[lib.scala 384:16] - _T_756.bits.csrwen <= r_d_in.bits.csrwen @[lib.scala 384:16] - _T_756.bits.i0v <= r_d_in.bits.i0v @[lib.scala 384:16] - _T_756.bits.i0div <= r_d_in.bits.i0div @[lib.scala 384:16] - _T_756.bits.i0store <= r_d_in.bits.i0store @[lib.scala 384:16] - _T_756.bits.i0load <= r_d_in.bits.i0load @[lib.scala 384:16] - _T_756.bits.i0rd <= r_d_in.bits.i0rd @[lib.scala 384:16] - _T_756.valid <= r_d_in.valid @[lib.scala 384:16] - wbd.bits.csrwaddr <= _T_756.bits.csrwaddr @[dec_decode_ctl.scala 662:7] - wbd.bits.csrwonly <= _T_756.bits.csrwonly @[dec_decode_ctl.scala 662:7] - wbd.bits.csrwen <= _T_756.bits.csrwen @[dec_decode_ctl.scala 662:7] - wbd.bits.i0v <= _T_756.bits.i0v @[dec_decode_ctl.scala 662:7] - wbd.bits.i0div <= _T_756.bits.i0div @[dec_decode_ctl.scala 662:7] - wbd.bits.i0store <= _T_756.bits.i0store @[dec_decode_ctl.scala 662:7] - wbd.bits.i0load <= _T_756.bits.i0load @[dec_decode_ctl.scala 662:7] - wbd.bits.i0rd <= _T_756.bits.i0rd @[dec_decode_ctl.scala 662:7] - wbd.valid <= _T_756.valid @[dec_decode_ctl.scala 662:7] - io.dec_i0_waddr_r <= r_d_in.bits.i0rd @[dec_decode_ctl.scala 664:27] - node _T_757 = eq(io.dec_tlu_i0_kill_writeb_r, UInt<1>("h00")) @[dec_decode_ctl.scala 665:47] - node _T_758 = and(r_d_in.bits.i0v, _T_757) @[dec_decode_ctl.scala 665:45] - i0_wen_r <= _T_758 @[dec_decode_ctl.scala 665:25] - node _T_759 = eq(r_d_in.bits.i0div, UInt<1>("h00")) @[dec_decode_ctl.scala 666:49] - node _T_760 = and(i0_wen_r, _T_759) @[dec_decode_ctl.scala 666:47] - node _T_761 = eq(i0_load_kill_wen_r, UInt<1>("h00")) @[dec_decode_ctl.scala 666:70] - node _T_762 = and(_T_760, _T_761) @[dec_decode_ctl.scala 666:68] - io.dec_i0_wen_r <= _T_762 @[dec_decode_ctl.scala 666:32] - io.dec_i0_wdata_r <= i0_result_corr_r @[dec_decode_ctl.scala 667:26] - node _T_763 = bits(i0_r_data_en, 0, 0) @[dec_decode_ctl.scala 669:57] + wire _T_757 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}} @[lib.scala 384:33] + _T_757.bits.csrwaddr <= UInt<12>("h00") @[lib.scala 384:33] + _T_757.bits.csrwonly <= UInt<1>("h00") @[lib.scala 384:33] + _T_757.bits.csrwen <= UInt<1>("h00") @[lib.scala 384:33] + _T_757.bits.i0v <= UInt<1>("h00") @[lib.scala 384:33] + _T_757.bits.i0div <= UInt<1>("h00") @[lib.scala 384:33] + _T_757.bits.i0store <= UInt<1>("h00") @[lib.scala 384:33] + _T_757.bits.i0load <= UInt<1>("h00") @[lib.scala 384:33] + _T_757.bits.i0rd <= UInt<5>("h00") @[lib.scala 384:33] + _T_757.valid <= UInt<1>("h00") @[lib.scala 384:33] + reg _T_758 : {valid : UInt<1>, bits : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}}, rvclkhdr_9.io.l1clk with : (reset => (reset, _T_757)) @[lib.scala 384:16] + _T_758.bits.csrwaddr <= r_d_in.bits.csrwaddr @[lib.scala 384:16] + _T_758.bits.csrwonly <= r_d_in.bits.csrwonly @[lib.scala 384:16] + _T_758.bits.csrwen <= r_d_in.bits.csrwen @[lib.scala 384:16] + _T_758.bits.i0v <= r_d_in.bits.i0v @[lib.scala 384:16] + _T_758.bits.i0div <= r_d_in.bits.i0div @[lib.scala 384:16] + _T_758.bits.i0store <= r_d_in.bits.i0store @[lib.scala 384:16] + _T_758.bits.i0load <= r_d_in.bits.i0load @[lib.scala 384:16] + _T_758.bits.i0rd <= r_d_in.bits.i0rd @[lib.scala 384:16] + _T_758.valid <= r_d_in.valid @[lib.scala 384:16] + wbd.bits.csrwaddr <= _T_758.bits.csrwaddr @[dec_decode_ctl.scala 656:7] + wbd.bits.csrwonly <= _T_758.bits.csrwonly @[dec_decode_ctl.scala 656:7] + wbd.bits.csrwen <= _T_758.bits.csrwen @[dec_decode_ctl.scala 656:7] + wbd.bits.i0v <= _T_758.bits.i0v @[dec_decode_ctl.scala 656:7] + wbd.bits.i0div <= _T_758.bits.i0div @[dec_decode_ctl.scala 656:7] + wbd.bits.i0store <= _T_758.bits.i0store @[dec_decode_ctl.scala 656:7] + wbd.bits.i0load <= _T_758.bits.i0load @[dec_decode_ctl.scala 656:7] + wbd.bits.i0rd <= _T_758.bits.i0rd @[dec_decode_ctl.scala 656:7] + wbd.valid <= _T_758.valid @[dec_decode_ctl.scala 656:7] + io.dec_i0_waddr_r <= r_d_in.bits.i0rd @[dec_decode_ctl.scala 658:27] + node _T_759 = eq(io.dec_tlu_i0_kill_writeb_r, UInt<1>("h00")) @[dec_decode_ctl.scala 659:47] + node _T_760 = and(r_d_in.bits.i0v, _T_759) @[dec_decode_ctl.scala 659:45] + i0_wen_r <= _T_760 @[dec_decode_ctl.scala 659:25] + node _T_761 = eq(r_d_in.bits.i0div, UInt<1>("h00")) @[dec_decode_ctl.scala 660:49] + node _T_762 = and(i0_wen_r, _T_761) @[dec_decode_ctl.scala 660:47] + node _T_763 = eq(i0_load_kill_wen_r, UInt<1>("h00")) @[dec_decode_ctl.scala 660:70] + node _T_764 = and(_T_762, _T_763) @[dec_decode_ctl.scala 660:68] + io.dec_i0_wen_r <= _T_764 @[dec_decode_ctl.scala 660:32] + io.dec_i0_wdata_r <= i0_result_corr_r @[dec_decode_ctl.scala 661:26] + node _T_765 = bits(i0_r_data_en, 0, 0) @[dec_decode_ctl.scala 663:57] inst rvclkhdr_10 of rvclkhdr_671 @[lib.scala 368:23] rvclkhdr_10.clock <= clock rvclkhdr_10.reset <= reset rvclkhdr_10.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_10.io.en <= _T_763 @[lib.scala 371:17] + rvclkhdr_10.io.en <= _T_765 @[lib.scala 371:17] rvclkhdr_10.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg i0_result_r_raw : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] i0_result_r_raw <= i0_result_x @[lib.scala 374:16] - node _T_764 = and(x_d.bits.i0v, x_d.bits.i0load) @[dec_decode_ctl.scala 675:47] - node _T_765 = bits(_T_764, 0, 0) @[dec_decode_ctl.scala 675:66] - node _T_766 = mux(_T_765, io.lsu_result_m, io.decode_exu.exu_i0_result_x) @[dec_decode_ctl.scala 675:32] - i0_result_x <= _T_766 @[dec_decode_ctl.scala 675:26] - i0_result_r <= i0_result_r_raw @[dec_decode_ctl.scala 676:26] - node _T_767 = and(r_d.bits.i0v, r_d.bits.i0load) @[dec_decode_ctl.scala 680:42] - node _T_768 = bits(_T_767, 0, 0) @[dec_decode_ctl.scala 680:61] - node _T_769 = mux(_T_768, io.lsu_result_corr_r, i0_result_r_raw) @[dec_decode_ctl.scala 680:27] - i0_result_corr_r <= _T_769 @[dec_decode_ctl.scala 680:21] - node _T_770 = eq(i0_dp.jal, UInt<1>("h00")) @[dec_decode_ctl.scala 681:73] - node _T_771 = and(io.decode_exu.i0_ap.predict_nt, _T_770) @[dec_decode_ctl.scala 681:71] - node _T_772 = bits(_T_771, 0, 0) @[dec_decode_ctl.scala 681:85] - wire _T_773 : UInt<1>[10] @[lib.scala 12:48] - _T_773[0] <= UInt<1>("h00") @[lib.scala 12:48] - _T_773[1] <= UInt<1>("h00") @[lib.scala 12:48] - _T_773[2] <= UInt<1>("h00") @[lib.scala 12:48] - _T_773[3] <= UInt<1>("h00") @[lib.scala 12:48] - _T_773[4] <= UInt<1>("h00") @[lib.scala 12:48] - _T_773[5] <= UInt<1>("h00") @[lib.scala 12:48] - _T_773[6] <= UInt<1>("h00") @[lib.scala 12:48] - _T_773[7] <= UInt<1>("h00") @[lib.scala 12:48] - _T_773[8] <= UInt<1>("h00") @[lib.scala 12:48] - _T_773[9] <= UInt<1>("h00") @[lib.scala 12:48] - node _T_774 = cat(_T_773[0], _T_773[1]) @[Cat.scala 29:58] - node _T_775 = cat(_T_774, _T_773[2]) @[Cat.scala 29:58] - node _T_776 = cat(_T_775, _T_773[3]) @[Cat.scala 29:58] - node _T_777 = cat(_T_776, _T_773[4]) @[Cat.scala 29:58] - node _T_778 = cat(_T_777, _T_773[5]) @[Cat.scala 29:58] - node _T_779 = cat(_T_778, _T_773[6]) @[Cat.scala 29:58] - node _T_780 = cat(_T_779, _T_773[7]) @[Cat.scala 29:58] - node _T_781 = cat(_T_780, _T_773[8]) @[Cat.scala 29:58] - node _T_782 = cat(_T_781, _T_773[9]) @[Cat.scala 29:58] - node _T_783 = cat(_T_782, io.dec_i0_pc4_d) @[Cat.scala 29:58] - node _T_784 = cat(_T_783, i0_ap_pc2) @[Cat.scala 29:58] - node _T_785 = mux(_T_772, i0_br_offset, _T_784) @[dec_decode_ctl.scala 681:38] - io.dec_alu.dec_i0_br_immed_d <= _T_785 @[dec_decode_ctl.scala 681:32] + node _T_766 = and(x_d.bits.i0v, x_d.bits.i0load) @[dec_decode_ctl.scala 669:47] + node _T_767 = bits(_T_766, 0, 0) @[dec_decode_ctl.scala 669:66] + node _T_768 = mux(_T_767, io.lsu_result_m, io.decode_exu.exu_i0_result_x) @[dec_decode_ctl.scala 669:32] + i0_result_x <= _T_768 @[dec_decode_ctl.scala 669:26] + i0_result_r <= i0_result_r_raw @[dec_decode_ctl.scala 670:26] + node _T_769 = and(r_d.bits.i0v, r_d.bits.i0load) @[dec_decode_ctl.scala 674:42] + node _T_770 = bits(_T_769, 0, 0) @[dec_decode_ctl.scala 674:61] + node _T_771 = mux(_T_770, io.lsu_result_corr_r, i0_result_r_raw) @[dec_decode_ctl.scala 674:27] + i0_result_corr_r <= _T_771 @[dec_decode_ctl.scala 674:21] + node _T_772 = eq(i0_dp.jal, UInt<1>("h00")) @[dec_decode_ctl.scala 675:73] + node _T_773 = and(io.decode_exu.i0_ap.predict_nt, _T_772) @[dec_decode_ctl.scala 675:71] + node _T_774 = bits(_T_773, 0, 0) @[dec_decode_ctl.scala 675:85] + wire _T_775 : UInt<1>[10] @[lib.scala 12:48] + _T_775[0] <= UInt<1>("h00") @[lib.scala 12:48] + _T_775[1] <= UInt<1>("h00") @[lib.scala 12:48] + _T_775[2] <= UInt<1>("h00") @[lib.scala 12:48] + _T_775[3] <= UInt<1>("h00") @[lib.scala 12:48] + _T_775[4] <= UInt<1>("h00") @[lib.scala 12:48] + _T_775[5] <= UInt<1>("h00") @[lib.scala 12:48] + _T_775[6] <= UInt<1>("h00") @[lib.scala 12:48] + _T_775[7] <= UInt<1>("h00") @[lib.scala 12:48] + _T_775[8] <= UInt<1>("h00") @[lib.scala 12:48] + _T_775[9] <= UInt<1>("h00") @[lib.scala 12:48] + node _T_776 = cat(_T_775[0], _T_775[1]) @[Cat.scala 29:58] + node _T_777 = cat(_T_776, _T_775[2]) @[Cat.scala 29:58] + node _T_778 = cat(_T_777, _T_775[3]) @[Cat.scala 29:58] + node _T_779 = cat(_T_778, _T_775[4]) @[Cat.scala 29:58] + node _T_780 = cat(_T_779, _T_775[5]) @[Cat.scala 29:58] + node _T_781 = cat(_T_780, _T_775[6]) @[Cat.scala 29:58] + node _T_782 = cat(_T_781, _T_775[7]) @[Cat.scala 29:58] + node _T_783 = cat(_T_782, _T_775[8]) @[Cat.scala 29:58] + node _T_784 = cat(_T_783, _T_775[9]) @[Cat.scala 29:58] + node _T_785 = cat(_T_784, io.dec_i0_pc4_d) @[Cat.scala 29:58] + node _T_786 = cat(_T_785, i0_ap_pc2) @[Cat.scala 29:58] + node _T_787 = mux(_T_774, i0_br_offset, _T_786) @[dec_decode_ctl.scala 675:38] + io.dec_alu.dec_i0_br_immed_d <= _T_787 @[dec_decode_ctl.scala 675:32] wire last_br_immed_d : UInt<12> last_br_immed_d <= UInt<1>("h00") - node _T_786 = bits(io.decode_exu.i0_ap.predict_nt, 0, 0) @[dec_decode_ctl.scala 683:59] - wire _T_787 : UInt<1>[10] @[lib.scala 12:48] - _T_787[0] <= UInt<1>("h00") @[lib.scala 12:48] - _T_787[1] <= UInt<1>("h00") @[lib.scala 12:48] - _T_787[2] <= UInt<1>("h00") @[lib.scala 12:48] - _T_787[3] <= UInt<1>("h00") @[lib.scala 12:48] - _T_787[4] <= UInt<1>("h00") @[lib.scala 12:48] - _T_787[5] <= UInt<1>("h00") @[lib.scala 12:48] - _T_787[6] <= UInt<1>("h00") @[lib.scala 12:48] - _T_787[7] <= UInt<1>("h00") @[lib.scala 12:48] - _T_787[8] <= UInt<1>("h00") @[lib.scala 12:48] - _T_787[9] <= UInt<1>("h00") @[lib.scala 12:48] - node _T_788 = cat(_T_787[0], _T_787[1]) @[Cat.scala 29:58] - node _T_789 = cat(_T_788, _T_787[2]) @[Cat.scala 29:58] - node _T_790 = cat(_T_789, _T_787[3]) @[Cat.scala 29:58] - node _T_791 = cat(_T_790, _T_787[4]) @[Cat.scala 29:58] - node _T_792 = cat(_T_791, _T_787[5]) @[Cat.scala 29:58] - node _T_793 = cat(_T_792, _T_787[6]) @[Cat.scala 29:58] - node _T_794 = cat(_T_793, _T_787[7]) @[Cat.scala 29:58] - node _T_795 = cat(_T_794, _T_787[8]) @[Cat.scala 29:58] - node _T_796 = cat(_T_795, _T_787[9]) @[Cat.scala 29:58] - node _T_797 = cat(_T_796, io.dec_i0_pc4_d) @[Cat.scala 29:58] - node _T_798 = cat(_T_797, i0_ap_pc2) @[Cat.scala 29:58] - node _T_799 = mux(_T_786, _T_798, i0_br_offset) @[dec_decode_ctl.scala 683:25] - last_br_immed_d <= _T_799 @[dec_decode_ctl.scala 683:19] + node _T_788 = bits(io.decode_exu.i0_ap.predict_nt, 0, 0) @[dec_decode_ctl.scala 677:59] + wire _T_789 : UInt<1>[10] @[lib.scala 12:48] + _T_789[0] <= UInt<1>("h00") @[lib.scala 12:48] + _T_789[1] <= UInt<1>("h00") @[lib.scala 12:48] + _T_789[2] <= UInt<1>("h00") @[lib.scala 12:48] + _T_789[3] <= UInt<1>("h00") @[lib.scala 12:48] + _T_789[4] <= UInt<1>("h00") @[lib.scala 12:48] + _T_789[5] <= UInt<1>("h00") @[lib.scala 12:48] + _T_789[6] <= UInt<1>("h00") @[lib.scala 12:48] + _T_789[7] <= UInt<1>("h00") @[lib.scala 12:48] + _T_789[8] <= UInt<1>("h00") @[lib.scala 12:48] + _T_789[9] <= UInt<1>("h00") @[lib.scala 12:48] + node _T_790 = cat(_T_789[0], _T_789[1]) @[Cat.scala 29:58] + node _T_791 = cat(_T_790, _T_789[2]) @[Cat.scala 29:58] + node _T_792 = cat(_T_791, _T_789[3]) @[Cat.scala 29:58] + node _T_793 = cat(_T_792, _T_789[4]) @[Cat.scala 29:58] + node _T_794 = cat(_T_793, _T_789[5]) @[Cat.scala 29:58] + node _T_795 = cat(_T_794, _T_789[6]) @[Cat.scala 29:58] + node _T_796 = cat(_T_795, _T_789[7]) @[Cat.scala 29:58] + node _T_797 = cat(_T_796, _T_789[8]) @[Cat.scala 29:58] + node _T_798 = cat(_T_797, _T_789[9]) @[Cat.scala 29:58] + node _T_799 = cat(_T_798, io.dec_i0_pc4_d) @[Cat.scala 29:58] + node _T_800 = cat(_T_799, i0_ap_pc2) @[Cat.scala 29:58] + node _T_801 = mux(_T_788, _T_800, i0_br_offset) @[dec_decode_ctl.scala 677:25] + last_br_immed_d <= _T_801 @[dec_decode_ctl.scala 677:19] wire last_br_immed_x : UInt<12> last_br_immed_x <= UInt<1>("h00") - node _T_800 = bits(i0_x_data_en, 0, 0) @[dec_decode_ctl.scala 685:58] + node _T_802 = bits(i0_x_data_en, 0, 0) @[dec_decode_ctl.scala 679:58] inst rvclkhdr_11 of rvclkhdr_672 @[lib.scala 368:23] rvclkhdr_11.clock <= clock rvclkhdr_11.reset <= reset rvclkhdr_11.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_11.io.en <= _T_800 @[lib.scala 371:17] + rvclkhdr_11.io.en <= _T_802 @[lib.scala 371:17] rvclkhdr_11.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_801 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_801 <= last_br_immed_d @[lib.scala 374:16] - last_br_immed_x <= _T_801 @[dec_decode_ctl.scala 685:19] - node _T_802 = and(x_d.bits.i0div, x_d.valid) @[dec_decode_ctl.scala 689:45] - node _T_803 = and(r_d.bits.i0div, r_d.valid) @[dec_decode_ctl.scala 689:76] - node div_e1_to_r = or(_T_802, _T_803) @[dec_decode_ctl.scala 689:58] - node _T_804 = and(x_d.bits.i0div, x_d.valid) @[dec_decode_ctl.scala 691:48] - node _T_805 = eq(x_d.bits.i0rd, UInt<5>("h00")) @[dec_decode_ctl.scala 691:77] - node _T_806 = and(_T_804, _T_805) @[dec_decode_ctl.scala 691:60] - node _T_807 = and(x_d.bits.i0div, x_d.valid) @[dec_decode_ctl.scala 692:21] - node _T_808 = and(_T_807, io.dec_tlu_flush_lower_r) @[dec_decode_ctl.scala 692:33] - node _T_809 = or(_T_806, _T_808) @[dec_decode_ctl.scala 691:94] - node _T_810 = and(r_d.bits.i0div, r_d.valid) @[dec_decode_ctl.scala 693:21] - node _T_811 = and(_T_810, io.dec_tlu_flush_lower_r) @[dec_decode_ctl.scala 693:33] - node _T_812 = and(_T_811, io.dec_tlu_i0_kill_writeb_r) @[dec_decode_ctl.scala 693:60] - node div_flush = or(_T_809, _T_812) @[dec_decode_ctl.scala 692:62] - node _T_813 = and(io.dec_div_active, div_flush) @[dec_decode_ctl.scala 697:51] - node _T_814 = eq(div_e1_to_r, UInt<1>("h00")) @[dec_decode_ctl.scala 698:26] - node _T_815 = and(io.dec_div_active, _T_814) @[dec_decode_ctl.scala 698:24] - node _T_816 = eq(r_d.bits.i0rd, io.div_waddr_wb) @[dec_decode_ctl.scala 698:56] - node _T_817 = and(_T_815, _T_816) @[dec_decode_ctl.scala 698:39] - node _T_818 = and(_T_817, i0_wen_r) @[dec_decode_ctl.scala 698:77] - node nonblock_div_cancel = or(_T_813, _T_818) @[dec_decode_ctl.scala 697:65] - node _T_819 = bits(nonblock_div_cancel, 0, 0) @[dec_decode_ctl.scala 700:61] - io.dec_div.dec_div_cancel <= _T_819 @[dec_decode_ctl.scala 700:37] - node i0_div_decode_d = and(i0_legal_decode_d, i0_dp.div) @[dec_decode_ctl.scala 701:55] - node _T_820 = eq(io.exu_div_wren, UInt<1>("h00")) @[dec_decode_ctl.scala 703:62] - node _T_821 = and(io.dec_div_active, _T_820) @[dec_decode_ctl.scala 703:60] - node _T_822 = eq(nonblock_div_cancel, UInt<1>("h00")) @[dec_decode_ctl.scala 703:81] - node _T_823 = and(_T_821, _T_822) @[dec_decode_ctl.scala 703:79] - node div_active_in = or(i0_div_decode_d, _T_823) @[dec_decode_ctl.scala 703:39] - reg _T_824 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 705:54] - _T_824 <= div_active_in @[dec_decode_ctl.scala 705:54] - io.dec_div_active <= _T_824 @[dec_decode_ctl.scala 705:21] - node _T_825 = and(io.decode_exu.dec_i0_rs1_en_d, io.dec_div_active) @[dec_decode_ctl.scala 708:60] - node _T_826 = eq(io.div_waddr_wb, i0r.rs1) @[dec_decode_ctl.scala 708:99] - node _T_827 = and(_T_825, _T_826) @[dec_decode_ctl.scala 708:80] - node _T_828 = and(io.decode_exu.dec_i0_rs2_en_d, io.dec_div_active) @[dec_decode_ctl.scala 709:36] - node _T_829 = eq(io.div_waddr_wb, i0r.rs2) @[dec_decode_ctl.scala 709:75] - node _T_830 = and(_T_828, _T_829) @[dec_decode_ctl.scala 709:56] - node _T_831 = or(_T_827, _T_830) @[dec_decode_ctl.scala 708:113] - i0_nonblock_div_stall <= _T_831 @[dec_decode_ctl.scala 708:26] - node _T_832 = bits(i0_div_decode_d, 0, 0) @[dec_decode_ctl.scala 711:59] - reg _T_833 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_832 : @[Reg.scala 28:19] - _T_833 <= i0r.rd @[Reg.scala 28:23] + reg _T_803 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_803 <= last_br_immed_d @[lib.scala 374:16] + last_br_immed_x <= _T_803 @[dec_decode_ctl.scala 679:19] + node _T_804 = and(x_d.bits.i0div, x_d.valid) @[dec_decode_ctl.scala 683:45] + node _T_805 = and(r_d.bits.i0div, r_d.valid) @[dec_decode_ctl.scala 683:76] + node div_e1_to_r = or(_T_804, _T_805) @[dec_decode_ctl.scala 683:58] + node _T_806 = and(x_d.bits.i0div, x_d.valid) @[dec_decode_ctl.scala 685:48] + node _T_807 = eq(x_d.bits.i0rd, UInt<5>("h00")) @[dec_decode_ctl.scala 685:77] + node _T_808 = and(_T_806, _T_807) @[dec_decode_ctl.scala 685:60] + node _T_809 = and(x_d.bits.i0div, x_d.valid) @[dec_decode_ctl.scala 686:21] + node _T_810 = and(_T_809, io.dec_tlu_flush_lower_r) @[dec_decode_ctl.scala 686:33] + node _T_811 = or(_T_808, _T_810) @[dec_decode_ctl.scala 685:94] + node _T_812 = and(r_d.bits.i0div, r_d.valid) @[dec_decode_ctl.scala 687:21] + node _T_813 = and(_T_812, io.dec_tlu_flush_lower_r) @[dec_decode_ctl.scala 687:33] + node _T_814 = and(_T_813, io.dec_tlu_i0_kill_writeb_r) @[dec_decode_ctl.scala 687:60] + node div_flush = or(_T_811, _T_814) @[dec_decode_ctl.scala 686:62] + node _T_815 = and(io.dec_div_active, div_flush) @[dec_decode_ctl.scala 691:51] + node _T_816 = eq(div_e1_to_r, UInt<1>("h00")) @[dec_decode_ctl.scala 692:26] + node _T_817 = and(io.dec_div_active, _T_816) @[dec_decode_ctl.scala 692:24] + node _T_818 = eq(r_d.bits.i0rd, io.div_waddr_wb) @[dec_decode_ctl.scala 692:56] + node _T_819 = and(_T_817, _T_818) @[dec_decode_ctl.scala 692:39] + node _T_820 = and(_T_819, i0_wen_r) @[dec_decode_ctl.scala 692:77] + node nonblock_div_cancel = or(_T_815, _T_820) @[dec_decode_ctl.scala 691:65] + node _T_821 = bits(nonblock_div_cancel, 0, 0) @[dec_decode_ctl.scala 694:61] + io.dec_div.dec_div_cancel <= _T_821 @[dec_decode_ctl.scala 694:37] + node i0_div_decode_d = and(i0_legal_decode_d, i0_dp.div) @[dec_decode_ctl.scala 695:55] + node _T_822 = eq(io.exu_div_wren, UInt<1>("h00")) @[dec_decode_ctl.scala 697:62] + node _T_823 = and(io.dec_div_active, _T_822) @[dec_decode_ctl.scala 697:60] + node _T_824 = eq(nonblock_div_cancel, UInt<1>("h00")) @[dec_decode_ctl.scala 697:81] + node _T_825 = and(_T_823, _T_824) @[dec_decode_ctl.scala 697:79] + node div_active_in = or(i0_div_decode_d, _T_825) @[dec_decode_ctl.scala 697:39] + reg _T_826 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_decode_ctl.scala 699:54] + _T_826 <= div_active_in @[dec_decode_ctl.scala 699:54] + io.dec_div_active <= _T_826 @[dec_decode_ctl.scala 699:21] + node _T_827 = and(io.decode_exu.dec_i0_rs1_en_d, io.dec_div_active) @[dec_decode_ctl.scala 702:60] + node _T_828 = eq(io.div_waddr_wb, i0r.rs1) @[dec_decode_ctl.scala 702:99] + node _T_829 = and(_T_827, _T_828) @[dec_decode_ctl.scala 702:80] + node _T_830 = and(io.decode_exu.dec_i0_rs2_en_d, io.dec_div_active) @[dec_decode_ctl.scala 703:36] + node _T_831 = eq(io.div_waddr_wb, i0r.rs2) @[dec_decode_ctl.scala 703:75] + node _T_832 = and(_T_830, _T_831) @[dec_decode_ctl.scala 703:56] + node _T_833 = or(_T_829, _T_832) @[dec_decode_ctl.scala 702:113] + i0_nonblock_div_stall <= _T_833 @[dec_decode_ctl.scala 702:26] + node _T_834 = bits(i0_div_decode_d, 0, 0) @[dec_decode_ctl.scala 705:59] + reg _T_835 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_834 : @[Reg.scala 28:19] + _T_835 <= i0r.rd @[Reg.scala 28:23] skip @[Reg.scala 28:19] - io.div_waddr_wb <= _T_833 @[dec_decode_ctl.scala 711:19] - node _T_834 = bits(i0_inst_d, 24, 7) @[dec_decode_ctl.scala 718:34] - node _T_835 = bits(i0_div_decode_d, 0, 0) @[dec_decode_ctl.scala 718:57] + io.div_waddr_wb <= _T_835 @[dec_decode_ctl.scala 705:19] + node _T_836 = bits(i0_inst_d, 24, 7) @[dec_decode_ctl.scala 712:34] + node _T_837 = bits(i0_div_decode_d, 0, 0) @[dec_decode_ctl.scala 712:57] inst rvclkhdr_12 of rvclkhdr_673 @[lib.scala 368:23] rvclkhdr_12.clock <= clock rvclkhdr_12.reset <= reset rvclkhdr_12.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_12.io.en <= _T_835 @[lib.scala 371:17] + rvclkhdr_12.io.en <= _T_837 @[lib.scala 371:17] rvclkhdr_12.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg div_inst : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - div_inst <= _T_834 @[lib.scala 374:16] - node _T_836 = bits(i0_x_data_en, 0, 0) @[dec_decode_ctl.scala 719:49] + div_inst <= _T_836 @[lib.scala 374:16] + node _T_838 = bits(i0_x_data_en, 0, 0) @[dec_decode_ctl.scala 713:49] inst rvclkhdr_13 of rvclkhdr_674 @[lib.scala 368:23] rvclkhdr_13.clock <= clock rvclkhdr_13.reset <= reset rvclkhdr_13.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_13.io.en <= _T_836 @[lib.scala 371:17] + rvclkhdr_13.io.en <= _T_838 @[lib.scala 371:17] rvclkhdr_13.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg i0_inst_x : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] i0_inst_x <= i0_inst_d @[lib.scala 374:16] - node _T_837 = bits(i0_r_data_en, 0, 0) @[dec_decode_ctl.scala 720:49] + node _T_839 = bits(i0_r_data_en, 0, 0) @[dec_decode_ctl.scala 714:49] inst rvclkhdr_14 of rvclkhdr_675 @[lib.scala 368:23] rvclkhdr_14.clock <= clock rvclkhdr_14.reset <= reset rvclkhdr_14.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_14.io.en <= _T_837 @[lib.scala 371:17] + rvclkhdr_14.io.en <= _T_839 @[lib.scala 371:17] rvclkhdr_14.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg i0_inst_r : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] i0_inst_r <= i0_inst_x @[lib.scala 374:16] - node _T_838 = bits(i0_wb_data_en, 0, 0) @[dec_decode_ctl.scala 722:50] + node _T_840 = bits(i0_wb_data_en, 0, 0) @[dec_decode_ctl.scala 716:50] inst rvclkhdr_15 of rvclkhdr_676 @[lib.scala 368:23] rvclkhdr_15.clock <= clock rvclkhdr_15.reset <= reset rvclkhdr_15.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_15.io.en <= _T_838 @[lib.scala 371:17] + rvclkhdr_15.io.en <= _T_840 @[lib.scala 371:17] rvclkhdr_15.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg i0_inst_wb : UInt, rvclkhdr_15.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] i0_inst_wb <= i0_inst_r @[lib.scala 374:16] - node _T_839 = bits(i0_wb1_data_en, 0, 0) @[dec_decode_ctl.scala 723:53] + node _T_841 = bits(i0_wb1_data_en, 0, 0) @[dec_decode_ctl.scala 717:53] inst rvclkhdr_16 of rvclkhdr_677 @[lib.scala 368:23] rvclkhdr_16.clock <= clock rvclkhdr_16.reset <= reset rvclkhdr_16.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_16.io.en <= _T_839 @[lib.scala 371:17] + rvclkhdr_16.io.en <= _T_841 @[lib.scala 371:17] rvclkhdr_16.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_840 : UInt, rvclkhdr_16.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_840 <= i0_inst_wb @[lib.scala 374:16] - io.dec_i0_inst_wb1 <= _T_840 @[dec_decode_ctl.scala 723:22] - node _T_841 = bits(i0_wb_data_en, 0, 0) @[dec_decode_ctl.scala 724:53] + reg _T_842 : UInt, rvclkhdr_16.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_842 <= i0_inst_wb @[lib.scala 374:16] + io.dec_i0_inst_wb1 <= _T_842 @[dec_decode_ctl.scala 717:22] + node _T_843 = bits(i0_wb_data_en, 0, 0) @[dec_decode_ctl.scala 718:53] inst rvclkhdr_17 of rvclkhdr_678 @[lib.scala 368:23] rvclkhdr_17.clock <= clock rvclkhdr_17.reset <= reset rvclkhdr_17.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_17.io.en <= _T_841 @[lib.scala 371:17] + rvclkhdr_17.io.en <= _T_843 @[lib.scala 371:17] rvclkhdr_17.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg i0_pc_wb : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] i0_pc_wb <= io.dec_tlu_i0_pc_r @[lib.scala 374:16] - node _T_842 = bits(i0_wb1_data_en, 0, 0) @[dec_decode_ctl.scala 726:49] + node _T_844 = bits(i0_wb1_data_en, 0, 0) @[dec_decode_ctl.scala 720:49] inst rvclkhdr_18 of rvclkhdr_679 @[lib.scala 368:23] rvclkhdr_18.clock <= clock rvclkhdr_18.reset <= reset rvclkhdr_18.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_18.io.en <= _T_842 @[lib.scala 371:17] + rvclkhdr_18.io.en <= _T_844 @[lib.scala 371:17] rvclkhdr_18.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_843 : UInt, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_843 <= i0_pc_wb @[lib.scala 374:16] - io.dec_i0_pc_wb1 <= _T_843 @[dec_decode_ctl.scala 726:20] - node _T_844 = bits(i0_r_data_en, 0, 0) @[dec_decode_ctl.scala 727:64] + reg _T_845 : UInt, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_845 <= i0_pc_wb @[lib.scala 374:16] + io.dec_i0_pc_wb1 <= _T_845 @[dec_decode_ctl.scala 720:20] + node _T_846 = bits(i0_r_data_en, 0, 0) @[dec_decode_ctl.scala 721:64] inst rvclkhdr_19 of rvclkhdr_680 @[lib.scala 368:23] rvclkhdr_19.clock <= clock rvclkhdr_19.reset <= reset rvclkhdr_19.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_19.io.en <= _T_844 @[lib.scala 371:17] + rvclkhdr_19.io.en <= _T_846 @[lib.scala 371:17] rvclkhdr_19.io.scan_mode <= io.scan_mode @[lib.scala 372:24] reg dec_i0_pc_r : UInt, rvclkhdr_19.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] dec_i0_pc_r <= io.dec_alu.exu_i0_pc_x @[lib.scala 374:16] - io.dec_tlu_i0_pc_r <= dec_i0_pc_r @[dec_decode_ctl.scala 729:27] - node _T_845 = cat(io.dec_alu.exu_i0_pc_x, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_846 = cat(last_br_immed_x, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_847 = bits(_T_845, 12, 1) @[lib.scala 68:24] - node _T_848 = bits(_T_846, 12, 1) @[lib.scala 68:40] - node _T_849 = add(_T_847, _T_848) @[lib.scala 68:31] - node _T_850 = bits(_T_845, 31, 13) @[lib.scala 69:20] - node _T_851 = add(_T_850, UInt<1>("h01")) @[lib.scala 69:27] - node _T_852 = tail(_T_851, 1) @[lib.scala 69:27] - node _T_853 = bits(_T_845, 31, 13) @[lib.scala 70:20] - node _T_854 = sub(_T_853, UInt<1>("h01")) @[lib.scala 70:27] - node _T_855 = tail(_T_854, 1) @[lib.scala 70:27] - node _T_856 = bits(_T_846, 12, 12) @[lib.scala 71:22] - node _T_857 = bits(_T_849, 12, 12) @[lib.scala 72:39] - node _T_858 = eq(_T_857, UInt<1>("h00")) @[lib.scala 72:28] - node _T_859 = xor(_T_856, _T_858) @[lib.scala 72:26] - node _T_860 = bits(_T_859, 0, 0) @[lib.scala 72:64] - node _T_861 = bits(_T_845, 31, 13) @[lib.scala 72:76] - node _T_862 = eq(_T_856, UInt<1>("h00")) @[lib.scala 73:20] - node _T_863 = bits(_T_849, 12, 12) @[lib.scala 73:39] - node _T_864 = and(_T_862, _T_863) @[lib.scala 73:26] - node _T_865 = bits(_T_864, 0, 0) @[lib.scala 73:64] - node _T_866 = bits(_T_849, 12, 12) @[lib.scala 74:39] - node _T_867 = eq(_T_866, UInt<1>("h00")) @[lib.scala 74:28] - node _T_868 = and(_T_856, _T_867) @[lib.scala 74:26] - node _T_869 = bits(_T_868, 0, 0) @[lib.scala 74:64] - node _T_870 = mux(_T_860, _T_861, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_871 = mux(_T_865, _T_852, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_872 = mux(_T_869, _T_855, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_873 = or(_T_870, _T_871) @[Mux.scala 27:72] - node _T_874 = or(_T_873, _T_872) @[Mux.scala 27:72] - wire _T_875 : UInt<19> @[Mux.scala 27:72] - _T_875 <= _T_874 @[Mux.scala 27:72] - node _T_876 = bits(_T_849, 11, 0) @[lib.scala 74:94] - node _T_877 = cat(_T_875, _T_876) @[Cat.scala 29:58] - node temp_pred_correct_npc_x = cat(_T_877, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_878 = bits(temp_pred_correct_npc_x, 31, 1) @[dec_decode_ctl.scala 734:62] - io.decode_exu.pred_correct_npc_x <= _T_878 @[dec_decode_ctl.scala 734:36] - node _T_879 = and(io.decode_exu.dec_i0_rs1_en_d, x_d.bits.i0v) @[dec_decode_ctl.scala 738:59] - node _T_880 = eq(x_d.bits.i0rd, i0r.rs1) @[dec_decode_ctl.scala 738:91] - node i0_rs1_depend_i0_x = and(_T_879, _T_880) @[dec_decode_ctl.scala 738:74] - node _T_881 = and(io.decode_exu.dec_i0_rs1_en_d, r_d.bits.i0v) @[dec_decode_ctl.scala 739:59] - node _T_882 = eq(r_d.bits.i0rd, i0r.rs1) @[dec_decode_ctl.scala 739:91] - node i0_rs1_depend_i0_r = and(_T_881, _T_882) @[dec_decode_ctl.scala 739:74] - node _T_883 = and(io.decode_exu.dec_i0_rs2_en_d, x_d.bits.i0v) @[dec_decode_ctl.scala 741:59] - node _T_884 = eq(x_d.bits.i0rd, i0r.rs2) @[dec_decode_ctl.scala 741:91] - node i0_rs2_depend_i0_x = and(_T_883, _T_884) @[dec_decode_ctl.scala 741:74] - node _T_885 = and(io.decode_exu.dec_i0_rs2_en_d, r_d.bits.i0v) @[dec_decode_ctl.scala 742:59] - node _T_886 = eq(r_d.bits.i0rd, i0r.rs2) @[dec_decode_ctl.scala 742:91] - node i0_rs2_depend_i0_r = and(_T_885, _T_886) @[dec_decode_ctl.scala 742:74] - node _T_887 = bits(i0_rs1_depend_i0_x, 0, 0) @[dec_decode_ctl.scala 744:44] - node _T_888 = bits(i0_rs1_depend_i0_r, 0, 0) @[dec_decode_ctl.scala 744:81] - wire _T_889 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 744:109] - _T_889.alu <= UInt<1>("h00") @[dec_decode_ctl.scala 744:109] - _T_889.load <= UInt<1>("h00") @[dec_decode_ctl.scala 744:109] - _T_889.mul <= UInt<1>("h00") @[dec_decode_ctl.scala 744:109] - node _T_890 = mux(_T_888, i0_r_c, _T_889) @[dec_decode_ctl.scala 744:61] - node _T_891 = mux(_T_887, i0_x_c, _T_890) @[dec_decode_ctl.scala 744:24] - i0_rs1_class_d.alu <= _T_891.alu @[dec_decode_ctl.scala 744:18] - i0_rs1_class_d.load <= _T_891.load @[dec_decode_ctl.scala 744:18] - i0_rs1_class_d.mul <= _T_891.mul @[dec_decode_ctl.scala 744:18] - node _T_892 = bits(i0_rs1_depend_i0_x, 0, 0) @[dec_decode_ctl.scala 745:44] - node _T_893 = bits(i0_rs1_depend_i0_r, 0, 0) @[dec_decode_ctl.scala 745:83] - node _T_894 = mux(_T_893, UInt<2>("h02"), UInt<1>("h00")) @[dec_decode_ctl.scala 745:63] - node _T_895 = mux(_T_892, UInt<2>("h01"), _T_894) @[dec_decode_ctl.scala 745:24] - i0_rs1_depth_d <= _T_895 @[dec_decode_ctl.scala 745:18] - node _T_896 = bits(i0_rs2_depend_i0_x, 0, 0) @[dec_decode_ctl.scala 746:44] - node _T_897 = bits(i0_rs2_depend_i0_r, 0, 0) @[dec_decode_ctl.scala 746:81] - wire _T_898 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 746:109] - _T_898.alu <= UInt<1>("h00") @[dec_decode_ctl.scala 746:109] - _T_898.load <= UInt<1>("h00") @[dec_decode_ctl.scala 746:109] - _T_898.mul <= UInt<1>("h00") @[dec_decode_ctl.scala 746:109] - node _T_899 = mux(_T_897, i0_r_c, _T_898) @[dec_decode_ctl.scala 746:61] - node _T_900 = mux(_T_896, i0_x_c, _T_899) @[dec_decode_ctl.scala 746:24] - i0_rs2_class_d.alu <= _T_900.alu @[dec_decode_ctl.scala 746:18] - i0_rs2_class_d.load <= _T_900.load @[dec_decode_ctl.scala 746:18] - i0_rs2_class_d.mul <= _T_900.mul @[dec_decode_ctl.scala 746:18] - node _T_901 = bits(i0_rs2_depend_i0_x, 0, 0) @[dec_decode_ctl.scala 747:44] - node _T_902 = bits(i0_rs2_depend_i0_r, 0, 0) @[dec_decode_ctl.scala 747:83] - node _T_903 = mux(_T_902, UInt<2>("h02"), UInt<1>("h00")) @[dec_decode_ctl.scala 747:63] - node _T_904 = mux(_T_901, UInt<2>("h01"), _T_903) @[dec_decode_ctl.scala 747:24] - i0_rs2_depth_d <= _T_904 @[dec_decode_ctl.scala 747:18] - i0_load_block_d <= UInt<1>("h00") @[dec_decode_ctl.scala 757:21] - node _T_905 = or(i0_dp.load, i0_dp.store) @[dec_decode_ctl.scala 758:43] - node _T_906 = bits(i0_rs1_depth_d, 0, 0) @[dec_decode_ctl.scala 758:74] - node _T_907 = and(_T_905, _T_906) @[dec_decode_ctl.scala 758:58] - node _T_908 = and(_T_907, i0_rs1_class_d.load) @[dec_decode_ctl.scala 758:78] - load_ldst_bypass_d <= _T_908 @[dec_decode_ctl.scala 758:27] - node _T_909 = bits(i0_rs2_depth_d, 0, 0) @[dec_decode_ctl.scala 759:59] - node _T_910 = and(i0_dp.store, _T_909) @[dec_decode_ctl.scala 759:43] - node _T_911 = and(_T_910, i0_rs2_class_d.load) @[dec_decode_ctl.scala 759:63] - store_data_bypass_d <= _T_911 @[dec_decode_ctl.scala 759:25] - store_data_bypass_m <= UInt<1>("h00") @[dec_decode_ctl.scala 760:25] - node _T_912 = and(io.decode_exu.dec_i0_rs1_en_d, io.dec_nonblock_load_wen) @[dec_decode_ctl.scala 764:73] - node _T_913 = eq(io.dec_nonblock_load_waddr, i0r.rs1) @[dec_decode_ctl.scala 764:130] - node i0_rs1_nonblock_load_bypass_en_d = and(_T_912, _T_913) @[dec_decode_ctl.scala 764:100] - node _T_914 = and(io.decode_exu.dec_i0_rs2_en_d, io.dec_nonblock_load_wen) @[dec_decode_ctl.scala 766:73] - node _T_915 = eq(io.dec_nonblock_load_waddr, i0r.rs2) @[dec_decode_ctl.scala 766:130] - node i0_rs2_nonblock_load_bypass_en_d = and(_T_914, _T_915) @[dec_decode_ctl.scala 766:100] - node _T_916 = bits(i0_rs1_depth_d, 0, 0) @[dec_decode_ctl.scala 769:41] - node _T_917 = or(i0_rs1_class_d.alu, i0_rs1_class_d.mul) @[dec_decode_ctl.scala 769:66] - node _T_918 = and(_T_916, _T_917) @[dec_decode_ctl.scala 769:45] - node _T_919 = bits(i0_rs1_depth_d, 0, 0) @[dec_decode_ctl.scala 769:104] - node _T_920 = and(_T_919, i0_rs1_class_d.load) @[dec_decode_ctl.scala 769:108] - node _T_921 = bits(i0_rs1_depth_d, 1, 1) @[dec_decode_ctl.scala 769:149] - node _T_922 = or(i0_rs1_class_d.alu, i0_rs1_class_d.mul) @[dec_decode_ctl.scala 769:175] - node _T_923 = or(_T_922, i0_rs1_class_d.load) @[dec_decode_ctl.scala 769:196] - node _T_924 = and(_T_921, _T_923) @[dec_decode_ctl.scala 769:153] - node _T_925 = cat(_T_918, _T_920) @[Cat.scala 29:58] - node _T_926 = cat(_T_925, _T_924) @[Cat.scala 29:58] - i0_rs1bypass <= _T_926 @[dec_decode_ctl.scala 769:18] - node _T_927 = bits(i0_rs2_depth_d, 0, 0) @[dec_decode_ctl.scala 771:41] - node _T_928 = or(i0_rs2_class_d.alu, i0_rs2_class_d.mul) @[dec_decode_ctl.scala 771:67] - node _T_929 = and(_T_927, _T_928) @[dec_decode_ctl.scala 771:45] - node _T_930 = bits(i0_rs2_depth_d, 0, 0) @[dec_decode_ctl.scala 771:105] - node _T_931 = and(_T_930, i0_rs2_class_d.load) @[dec_decode_ctl.scala 771:109] - node _T_932 = bits(i0_rs2_depth_d, 1, 1) @[dec_decode_ctl.scala 771:149] - node _T_933 = or(i0_rs2_class_d.alu, i0_rs2_class_d.mul) @[dec_decode_ctl.scala 771:175] - node _T_934 = or(_T_933, i0_rs2_class_d.load) @[dec_decode_ctl.scala 771:196] - node _T_935 = and(_T_932, _T_934) @[dec_decode_ctl.scala 771:153] - node _T_936 = cat(_T_929, _T_931) @[Cat.scala 29:58] - node _T_937 = cat(_T_936, _T_935) @[Cat.scala 29:58] - i0_rs2bypass <= _T_937 @[dec_decode_ctl.scala 771:18] - node _T_938 = bits(i0_rs1bypass, 2, 2) @[dec_decode_ctl.scala 773:65] - node _T_939 = bits(i0_rs1bypass, 1, 1) @[dec_decode_ctl.scala 773:82] - node _T_940 = bits(i0_rs1bypass, 0, 0) @[dec_decode_ctl.scala 773:100] - node _T_941 = or(_T_939, _T_940) @[dec_decode_ctl.scala 773:86] - node _T_942 = bits(i0_rs1bypass, 2, 2) @[dec_decode_ctl.scala 773:120] - node _T_943 = eq(_T_942, UInt<1>("h00")) @[dec_decode_ctl.scala 773:107] - node _T_944 = and(_T_943, i0_rs1_nonblock_load_bypass_en_d) @[dec_decode_ctl.scala 773:124] - node _T_945 = or(_T_941, _T_944) @[dec_decode_ctl.scala 773:104] - node _T_946 = cat(_T_938, _T_945) @[Cat.scala 29:58] - io.decode_exu.dec_i0_rs1_bypass_en_d <= _T_946 @[dec_decode_ctl.scala 773:45] - node _T_947 = bits(i0_rs2bypass, 2, 2) @[dec_decode_ctl.scala 774:65] - node _T_948 = bits(i0_rs2bypass, 1, 1) @[dec_decode_ctl.scala 774:82] - node _T_949 = bits(i0_rs2bypass, 0, 0) @[dec_decode_ctl.scala 774:100] - node _T_950 = or(_T_948, _T_949) @[dec_decode_ctl.scala 774:86] - node _T_951 = bits(i0_rs2bypass, 2, 2) @[dec_decode_ctl.scala 774:120] - node _T_952 = eq(_T_951, UInt<1>("h00")) @[dec_decode_ctl.scala 774:107] - node _T_953 = and(_T_952, i0_rs2_nonblock_load_bypass_en_d) @[dec_decode_ctl.scala 774:124] - node _T_954 = or(_T_950, _T_953) @[dec_decode_ctl.scala 774:104] - node _T_955 = cat(_T_947, _T_954) @[Cat.scala 29:58] - io.decode_exu.dec_i0_rs2_bypass_en_d <= _T_955 @[dec_decode_ctl.scala 774:45] - node _T_956 = bits(i0_rs1bypass, 1, 1) @[dec_decode_ctl.scala 778:17] - node _T_957 = bits(_T_956, 0, 0) @[dec_decode_ctl.scala 778:21] - node _T_958 = bits(i0_rs1bypass, 0, 0) @[dec_decode_ctl.scala 779:17] - node _T_959 = bits(_T_958, 0, 0) @[dec_decode_ctl.scala 779:21] - node _T_960 = bits(i0_rs1bypass, 1, 1) @[dec_decode_ctl.scala 780:19] - node _T_961 = eq(_T_960, UInt<1>("h00")) @[dec_decode_ctl.scala 780:6] - node _T_962 = bits(i0_rs1bypass, 0, 0) @[dec_decode_ctl.scala 780:38] - node _T_963 = eq(_T_962, UInt<1>("h00")) @[dec_decode_ctl.scala 780:25] - node _T_964 = and(_T_961, _T_963) @[dec_decode_ctl.scala 780:23] - node _T_965 = and(_T_964, i0_rs1_nonblock_load_bypass_en_d) @[dec_decode_ctl.scala 780:42] - node _T_966 = bits(_T_965, 0, 0) @[dec_decode_ctl.scala 780:78] - node _T_967 = mux(_T_957, io.lsu_result_m, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_968 = mux(_T_959, i0_result_r, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_969 = mux(_T_966, io.dctl_busbuff.lsu_nonblock_load_data, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_970 = or(_T_967, _T_968) @[Mux.scala 27:72] - node _T_971 = or(_T_970, _T_969) @[Mux.scala 27:72] - wire _T_972 : UInt<32> @[Mux.scala 27:72] - _T_972 <= _T_971 @[Mux.scala 27:72] - io.decode_exu.dec_i0_rs1_bypass_data_d <= _T_972 @[dec_decode_ctl.scala 777:42] - node _T_973 = bits(i0_rs2bypass, 1, 1) @[dec_decode_ctl.scala 783:17] - node _T_974 = bits(_T_973, 0, 0) @[dec_decode_ctl.scala 783:21] - node _T_975 = bits(i0_rs2bypass, 0, 0) @[dec_decode_ctl.scala 784:17] - node _T_976 = bits(_T_975, 0, 0) @[dec_decode_ctl.scala 784:21] - node _T_977 = bits(i0_rs2bypass, 1, 1) @[dec_decode_ctl.scala 785:19] - node _T_978 = eq(_T_977, UInt<1>("h00")) @[dec_decode_ctl.scala 785:6] - node _T_979 = bits(i0_rs2bypass, 0, 0) @[dec_decode_ctl.scala 785:38] - node _T_980 = eq(_T_979, UInt<1>("h00")) @[dec_decode_ctl.scala 785:25] - node _T_981 = and(_T_978, _T_980) @[dec_decode_ctl.scala 785:23] - node _T_982 = and(_T_981, i0_rs2_nonblock_load_bypass_en_d) @[dec_decode_ctl.scala 785:42] - node _T_983 = bits(_T_982, 0, 0) @[dec_decode_ctl.scala 785:78] - node _T_984 = mux(_T_974, io.lsu_result_m, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_985 = mux(_T_976, i0_result_r, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_986 = mux(_T_983, io.dctl_busbuff.lsu_nonblock_load_data, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_987 = or(_T_984, _T_985) @[Mux.scala 27:72] - node _T_988 = or(_T_987, _T_986) @[Mux.scala 27:72] - wire _T_989 : UInt<32> @[Mux.scala 27:72] - _T_989 <= _T_988 @[Mux.scala 27:72] - io.decode_exu.dec_i0_rs2_bypass_data_d <= _T_989 @[dec_decode_ctl.scala 782:42] - node _T_990 = or(i0_dp_raw.load, i0_dp_raw.store) @[dec_decode_ctl.scala 787:68] - node _T_991 = and(io.dec_ib0_valid_d, _T_990) @[dec_decode_ctl.scala 787:50] - node _T_992 = eq(io.dctl_dma.dma_dccm_stall_any, UInt<1>("h00")) @[dec_decode_ctl.scala 787:89] - node _T_993 = and(_T_991, _T_992) @[dec_decode_ctl.scala 787:87] - node _T_994 = eq(i0_block_raw_d, UInt<1>("h00")) @[dec_decode_ctl.scala 787:123] - node _T_995 = and(_T_993, _T_994) @[dec_decode_ctl.scala 787:121] - node _T_996 = or(_T_995, io.decode_exu.dec_extint_stall) @[dec_decode_ctl.scala 787:140] - io.dec_lsu_valid_raw_d <= _T_996 @[dec_decode_ctl.scala 787:26] - node _T_997 = eq(io.decode_exu.dec_extint_stall, UInt<1>("h00")) @[dec_decode_ctl.scala 789:6] - node _T_998 = and(_T_997, i0_dp.lsu) @[dec_decode_ctl.scala 789:38] - node _T_999 = and(_T_998, i0_dp.load) @[dec_decode_ctl.scala 789:50] - node _T_1000 = bits(_T_999, 0, 0) @[dec_decode_ctl.scala 789:64] - node _T_1001 = bits(io.dec_i0_instr_d, 31, 20) @[dec_decode_ctl.scala 789:81] - node _T_1002 = eq(io.decode_exu.dec_extint_stall, UInt<1>("h00")) @[dec_decode_ctl.scala 790:6] - node _T_1003 = and(_T_1002, i0_dp.lsu) @[dec_decode_ctl.scala 790:38] - node _T_1004 = and(_T_1003, i0_dp.store) @[dec_decode_ctl.scala 790:50] - node _T_1005 = bits(_T_1004, 0, 0) @[dec_decode_ctl.scala 790:65] - node _T_1006 = bits(io.dec_i0_instr_d, 31, 25) @[dec_decode_ctl.scala 790:85] - node _T_1007 = bits(io.dec_i0_instr_d, 11, 7) @[dec_decode_ctl.scala 790:95] - node _T_1008 = cat(_T_1006, _T_1007) @[Cat.scala 29:58] - node _T_1009 = mux(_T_1000, _T_1001, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1010 = mux(_T_1005, _T_1008, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1011 = or(_T_1009, _T_1010) @[Mux.scala 27:72] - wire _T_1012 : UInt<12> @[Mux.scala 27:72] - _T_1012 <= _T_1011 @[Mux.scala 27:72] - io.dec_lsu_offset_d <= _T_1012 @[dec_decode_ctl.scala 788:23] + io.dec_tlu_i0_pc_r <= dec_i0_pc_r @[dec_decode_ctl.scala 723:27] + node _T_847 = cat(io.dec_alu.exu_i0_pc_x, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_848 = cat(last_br_immed_x, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_849 = bits(_T_847, 12, 1) @[lib.scala 68:24] + node _T_850 = bits(_T_848, 12, 1) @[lib.scala 68:40] + node _T_851 = add(_T_849, _T_850) @[lib.scala 68:31] + node _T_852 = bits(_T_847, 31, 13) @[lib.scala 69:20] + node _T_853 = add(_T_852, UInt<1>("h01")) @[lib.scala 69:27] + node _T_854 = tail(_T_853, 1) @[lib.scala 69:27] + node _T_855 = bits(_T_847, 31, 13) @[lib.scala 70:20] + node _T_856 = sub(_T_855, UInt<1>("h01")) @[lib.scala 70:27] + node _T_857 = tail(_T_856, 1) @[lib.scala 70:27] + node _T_858 = bits(_T_848, 12, 12) @[lib.scala 71:22] + node _T_859 = bits(_T_851, 12, 12) @[lib.scala 72:39] + node _T_860 = eq(_T_859, UInt<1>("h00")) @[lib.scala 72:28] + node _T_861 = xor(_T_858, _T_860) @[lib.scala 72:26] + node _T_862 = bits(_T_861, 0, 0) @[lib.scala 72:64] + node _T_863 = bits(_T_847, 31, 13) @[lib.scala 72:76] + node _T_864 = eq(_T_858, UInt<1>("h00")) @[lib.scala 73:20] + node _T_865 = bits(_T_851, 12, 12) @[lib.scala 73:39] + node _T_866 = and(_T_864, _T_865) @[lib.scala 73:26] + node _T_867 = bits(_T_866, 0, 0) @[lib.scala 73:64] + node _T_868 = bits(_T_851, 12, 12) @[lib.scala 74:39] + node _T_869 = eq(_T_868, UInt<1>("h00")) @[lib.scala 74:28] + node _T_870 = and(_T_858, _T_869) @[lib.scala 74:26] + node _T_871 = bits(_T_870, 0, 0) @[lib.scala 74:64] + node _T_872 = mux(_T_862, _T_863, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_873 = mux(_T_867, _T_854, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_874 = mux(_T_871, _T_857, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_875 = or(_T_872, _T_873) @[Mux.scala 27:72] + node _T_876 = or(_T_875, _T_874) @[Mux.scala 27:72] + wire _T_877 : UInt<19> @[Mux.scala 27:72] + _T_877 <= _T_876 @[Mux.scala 27:72] + node _T_878 = bits(_T_851, 11, 0) @[lib.scala 74:94] + node _T_879 = cat(_T_877, _T_878) @[Cat.scala 29:58] + node temp_pred_correct_npc_x = cat(_T_879, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_880 = bits(temp_pred_correct_npc_x, 31, 1) @[dec_decode_ctl.scala 728:62] + io.decode_exu.pred_correct_npc_x <= _T_880 @[dec_decode_ctl.scala 728:36] + node _T_881 = and(io.decode_exu.dec_i0_rs1_en_d, x_d.bits.i0v) @[dec_decode_ctl.scala 732:59] + node _T_882 = eq(x_d.bits.i0rd, i0r.rs1) @[dec_decode_ctl.scala 732:91] + node i0_rs1_depend_i0_x = and(_T_881, _T_882) @[dec_decode_ctl.scala 732:74] + node _T_883 = and(io.decode_exu.dec_i0_rs1_en_d, r_d.bits.i0v) @[dec_decode_ctl.scala 733:59] + node _T_884 = eq(r_d.bits.i0rd, i0r.rs1) @[dec_decode_ctl.scala 733:91] + node i0_rs1_depend_i0_r = and(_T_883, _T_884) @[dec_decode_ctl.scala 733:74] + node _T_885 = and(io.decode_exu.dec_i0_rs2_en_d, x_d.bits.i0v) @[dec_decode_ctl.scala 735:59] + node _T_886 = eq(x_d.bits.i0rd, i0r.rs2) @[dec_decode_ctl.scala 735:91] + node i0_rs2_depend_i0_x = and(_T_885, _T_886) @[dec_decode_ctl.scala 735:74] + node _T_887 = and(io.decode_exu.dec_i0_rs2_en_d, r_d.bits.i0v) @[dec_decode_ctl.scala 736:59] + node _T_888 = eq(r_d.bits.i0rd, i0r.rs2) @[dec_decode_ctl.scala 736:91] + node i0_rs2_depend_i0_r = and(_T_887, _T_888) @[dec_decode_ctl.scala 736:74] + node _T_889 = bits(i0_rs1_depend_i0_x, 0, 0) @[dec_decode_ctl.scala 738:44] + node _T_890 = bits(i0_rs1_depend_i0_r, 0, 0) @[dec_decode_ctl.scala 738:81] + wire _T_891 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 738:109] + _T_891.alu <= UInt<1>("h00") @[dec_decode_ctl.scala 738:109] + _T_891.load <= UInt<1>("h00") @[dec_decode_ctl.scala 738:109] + _T_891.mul <= UInt<1>("h00") @[dec_decode_ctl.scala 738:109] + node _T_892 = mux(_T_890, i0_r_c, _T_891) @[dec_decode_ctl.scala 738:61] + node _T_893 = mux(_T_889, i0_x_c, _T_892) @[dec_decode_ctl.scala 738:24] + i0_rs1_class_d.alu <= _T_893.alu @[dec_decode_ctl.scala 738:18] + i0_rs1_class_d.load <= _T_893.load @[dec_decode_ctl.scala 738:18] + i0_rs1_class_d.mul <= _T_893.mul @[dec_decode_ctl.scala 738:18] + node _T_894 = bits(i0_rs1_depend_i0_x, 0, 0) @[dec_decode_ctl.scala 739:44] + node _T_895 = bits(i0_rs1_depend_i0_r, 0, 0) @[dec_decode_ctl.scala 739:83] + node _T_896 = mux(_T_895, UInt<2>("h02"), UInt<1>("h00")) @[dec_decode_ctl.scala 739:63] + node _T_897 = mux(_T_894, UInt<2>("h01"), _T_896) @[dec_decode_ctl.scala 739:24] + i0_rs1_depth_d <= _T_897 @[dec_decode_ctl.scala 739:18] + node _T_898 = bits(i0_rs2_depend_i0_x, 0, 0) @[dec_decode_ctl.scala 740:44] + node _T_899 = bits(i0_rs2_depend_i0_r, 0, 0) @[dec_decode_ctl.scala 740:81] + wire _T_900 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[dec_decode_ctl.scala 740:109] + _T_900.alu <= UInt<1>("h00") @[dec_decode_ctl.scala 740:109] + _T_900.load <= UInt<1>("h00") @[dec_decode_ctl.scala 740:109] + _T_900.mul <= UInt<1>("h00") @[dec_decode_ctl.scala 740:109] + node _T_901 = mux(_T_899, i0_r_c, _T_900) @[dec_decode_ctl.scala 740:61] + node _T_902 = mux(_T_898, i0_x_c, _T_901) @[dec_decode_ctl.scala 740:24] + i0_rs2_class_d.alu <= _T_902.alu @[dec_decode_ctl.scala 740:18] + i0_rs2_class_d.load <= _T_902.load @[dec_decode_ctl.scala 740:18] + i0_rs2_class_d.mul <= _T_902.mul @[dec_decode_ctl.scala 740:18] + node _T_903 = bits(i0_rs2_depend_i0_x, 0, 0) @[dec_decode_ctl.scala 741:44] + node _T_904 = bits(i0_rs2_depend_i0_r, 0, 0) @[dec_decode_ctl.scala 741:83] + node _T_905 = mux(_T_904, UInt<2>("h02"), UInt<1>("h00")) @[dec_decode_ctl.scala 741:63] + node _T_906 = mux(_T_903, UInt<2>("h01"), _T_905) @[dec_decode_ctl.scala 741:24] + i0_rs2_depth_d <= _T_906 @[dec_decode_ctl.scala 741:18] + i0_load_block_d <= UInt<1>("h00") @[dec_decode_ctl.scala 751:21] + node _T_907 = or(i0_dp.load, i0_dp.store) @[dec_decode_ctl.scala 752:43] + node _T_908 = bits(i0_rs1_depth_d, 0, 0) @[dec_decode_ctl.scala 752:74] + node _T_909 = and(_T_907, _T_908) @[dec_decode_ctl.scala 752:58] + node _T_910 = and(_T_909, i0_rs1_class_d.load) @[dec_decode_ctl.scala 752:78] + load_ldst_bypass_d <= _T_910 @[dec_decode_ctl.scala 752:27] + node _T_911 = bits(i0_rs2_depth_d, 0, 0) @[dec_decode_ctl.scala 753:59] + node _T_912 = and(i0_dp.store, _T_911) @[dec_decode_ctl.scala 753:43] + node _T_913 = and(_T_912, i0_rs2_class_d.load) @[dec_decode_ctl.scala 753:63] + store_data_bypass_d <= _T_913 @[dec_decode_ctl.scala 753:25] + store_data_bypass_m <= UInt<1>("h00") @[dec_decode_ctl.scala 754:25] + node _T_914 = and(io.decode_exu.dec_i0_rs1_en_d, io.dec_nonblock_load_wen) @[dec_decode_ctl.scala 758:73] + node _T_915 = eq(io.dec_nonblock_load_waddr, i0r.rs1) @[dec_decode_ctl.scala 758:130] + node i0_rs1_nonblock_load_bypass_en_d = and(_T_914, _T_915) @[dec_decode_ctl.scala 758:100] + node _T_916 = and(io.decode_exu.dec_i0_rs2_en_d, io.dec_nonblock_load_wen) @[dec_decode_ctl.scala 760:73] + node _T_917 = eq(io.dec_nonblock_load_waddr, i0r.rs2) @[dec_decode_ctl.scala 760:130] + node i0_rs2_nonblock_load_bypass_en_d = and(_T_916, _T_917) @[dec_decode_ctl.scala 760:100] + node _T_918 = bits(i0_rs1_depth_d, 0, 0) @[dec_decode_ctl.scala 763:41] + node _T_919 = or(i0_rs1_class_d.alu, i0_rs1_class_d.mul) @[dec_decode_ctl.scala 763:66] + node _T_920 = and(_T_918, _T_919) @[dec_decode_ctl.scala 763:45] + node _T_921 = bits(i0_rs1_depth_d, 0, 0) @[dec_decode_ctl.scala 763:104] + node _T_922 = and(_T_921, i0_rs1_class_d.load) @[dec_decode_ctl.scala 763:108] + node _T_923 = bits(i0_rs1_depth_d, 1, 1) @[dec_decode_ctl.scala 763:149] + node _T_924 = or(i0_rs1_class_d.alu, i0_rs1_class_d.mul) @[dec_decode_ctl.scala 763:175] + node _T_925 = or(_T_924, i0_rs1_class_d.load) @[dec_decode_ctl.scala 763:196] + node _T_926 = and(_T_923, _T_925) @[dec_decode_ctl.scala 763:153] + node _T_927 = cat(_T_920, _T_922) @[Cat.scala 29:58] + node _T_928 = cat(_T_927, _T_926) @[Cat.scala 29:58] + i0_rs1bypass <= _T_928 @[dec_decode_ctl.scala 763:18] + node _T_929 = bits(i0_rs2_depth_d, 0, 0) @[dec_decode_ctl.scala 765:41] + node _T_930 = or(i0_rs2_class_d.alu, i0_rs2_class_d.mul) @[dec_decode_ctl.scala 765:67] + node _T_931 = and(_T_929, _T_930) @[dec_decode_ctl.scala 765:45] + node _T_932 = bits(i0_rs2_depth_d, 0, 0) @[dec_decode_ctl.scala 765:105] + node _T_933 = and(_T_932, i0_rs2_class_d.load) @[dec_decode_ctl.scala 765:109] + node _T_934 = bits(i0_rs2_depth_d, 1, 1) @[dec_decode_ctl.scala 765:149] + node _T_935 = or(i0_rs2_class_d.alu, i0_rs2_class_d.mul) @[dec_decode_ctl.scala 765:175] + node _T_936 = or(_T_935, i0_rs2_class_d.load) @[dec_decode_ctl.scala 765:196] + node _T_937 = and(_T_934, _T_936) @[dec_decode_ctl.scala 765:153] + node _T_938 = cat(_T_931, _T_933) @[Cat.scala 29:58] + node _T_939 = cat(_T_938, _T_937) @[Cat.scala 29:58] + i0_rs2bypass <= _T_939 @[dec_decode_ctl.scala 765:18] + node _T_940 = bits(i0_rs1bypass, 2, 2) @[dec_decode_ctl.scala 767:65] + node _T_941 = bits(i0_rs1bypass, 1, 1) @[dec_decode_ctl.scala 767:82] + node _T_942 = bits(i0_rs1bypass, 0, 0) @[dec_decode_ctl.scala 767:100] + node _T_943 = or(_T_941, _T_942) @[dec_decode_ctl.scala 767:86] + node _T_944 = bits(i0_rs1bypass, 2, 2) @[dec_decode_ctl.scala 767:120] + node _T_945 = eq(_T_944, UInt<1>("h00")) @[dec_decode_ctl.scala 767:107] + node _T_946 = and(_T_945, i0_rs1_nonblock_load_bypass_en_d) @[dec_decode_ctl.scala 767:124] + node _T_947 = or(_T_943, _T_946) @[dec_decode_ctl.scala 767:104] + node _T_948 = cat(_T_940, _T_947) @[Cat.scala 29:58] + io.decode_exu.dec_i0_rs1_bypass_en_d <= _T_948 @[dec_decode_ctl.scala 767:45] + node _T_949 = bits(i0_rs2bypass, 2, 2) @[dec_decode_ctl.scala 768:65] + node _T_950 = bits(i0_rs2bypass, 1, 1) @[dec_decode_ctl.scala 768:82] + node _T_951 = bits(i0_rs2bypass, 0, 0) @[dec_decode_ctl.scala 768:100] + node _T_952 = or(_T_950, _T_951) @[dec_decode_ctl.scala 768:86] + node _T_953 = bits(i0_rs2bypass, 2, 2) @[dec_decode_ctl.scala 768:120] + node _T_954 = eq(_T_953, UInt<1>("h00")) @[dec_decode_ctl.scala 768:107] + node _T_955 = and(_T_954, i0_rs2_nonblock_load_bypass_en_d) @[dec_decode_ctl.scala 768:124] + node _T_956 = or(_T_952, _T_955) @[dec_decode_ctl.scala 768:104] + node _T_957 = cat(_T_949, _T_956) @[Cat.scala 29:58] + io.decode_exu.dec_i0_rs2_bypass_en_d <= _T_957 @[dec_decode_ctl.scala 768:45] + node _T_958 = bits(i0_rs1bypass, 1, 1) @[dec_decode_ctl.scala 772:17] + node _T_959 = bits(_T_958, 0, 0) @[dec_decode_ctl.scala 772:21] + node _T_960 = bits(i0_rs1bypass, 0, 0) @[dec_decode_ctl.scala 773:17] + node _T_961 = bits(_T_960, 0, 0) @[dec_decode_ctl.scala 773:21] + node _T_962 = bits(i0_rs1bypass, 1, 1) @[dec_decode_ctl.scala 774:19] + node _T_963 = eq(_T_962, UInt<1>("h00")) @[dec_decode_ctl.scala 774:6] + node _T_964 = bits(i0_rs1bypass, 0, 0) @[dec_decode_ctl.scala 774:38] + node _T_965 = eq(_T_964, UInt<1>("h00")) @[dec_decode_ctl.scala 774:25] + node _T_966 = and(_T_963, _T_965) @[dec_decode_ctl.scala 774:23] + node _T_967 = and(_T_966, i0_rs1_nonblock_load_bypass_en_d) @[dec_decode_ctl.scala 774:42] + node _T_968 = bits(_T_967, 0, 0) @[dec_decode_ctl.scala 774:78] + node _T_969 = mux(_T_959, io.lsu_result_m, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_970 = mux(_T_961, i0_result_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_971 = mux(_T_968, io.dctl_busbuff.lsu_nonblock_load_data, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_972 = or(_T_969, _T_970) @[Mux.scala 27:72] + node _T_973 = or(_T_972, _T_971) @[Mux.scala 27:72] + wire _T_974 : UInt<32> @[Mux.scala 27:72] + _T_974 <= _T_973 @[Mux.scala 27:72] + io.decode_exu.dec_i0_rs1_bypass_data_d <= _T_974 @[dec_decode_ctl.scala 771:42] + node _T_975 = bits(i0_rs2bypass, 1, 1) @[dec_decode_ctl.scala 777:17] + node _T_976 = bits(_T_975, 0, 0) @[dec_decode_ctl.scala 777:21] + node _T_977 = bits(i0_rs2bypass, 0, 0) @[dec_decode_ctl.scala 778:17] + node _T_978 = bits(_T_977, 0, 0) @[dec_decode_ctl.scala 778:21] + node _T_979 = bits(i0_rs2bypass, 1, 1) @[dec_decode_ctl.scala 779:19] + node _T_980 = eq(_T_979, UInt<1>("h00")) @[dec_decode_ctl.scala 779:6] + node _T_981 = bits(i0_rs2bypass, 0, 0) @[dec_decode_ctl.scala 779:38] + node _T_982 = eq(_T_981, UInt<1>("h00")) @[dec_decode_ctl.scala 779:25] + node _T_983 = and(_T_980, _T_982) @[dec_decode_ctl.scala 779:23] + node _T_984 = and(_T_983, i0_rs2_nonblock_load_bypass_en_d) @[dec_decode_ctl.scala 779:42] + node _T_985 = bits(_T_984, 0, 0) @[dec_decode_ctl.scala 779:78] + node _T_986 = mux(_T_976, io.lsu_result_m, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_987 = mux(_T_978, i0_result_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_988 = mux(_T_985, io.dctl_busbuff.lsu_nonblock_load_data, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_989 = or(_T_986, _T_987) @[Mux.scala 27:72] + node _T_990 = or(_T_989, _T_988) @[Mux.scala 27:72] + wire _T_991 : UInt<32> @[Mux.scala 27:72] + _T_991 <= _T_990 @[Mux.scala 27:72] + io.decode_exu.dec_i0_rs2_bypass_data_d <= _T_991 @[dec_decode_ctl.scala 776:42] + node _T_992 = or(i0_dp_raw.load, i0_dp_raw.store) @[dec_decode_ctl.scala 781:68] + node _T_993 = and(io.dec_ib0_valid_d, _T_992) @[dec_decode_ctl.scala 781:50] + node _T_994 = eq(io.dctl_dma.dma_dccm_stall_any, UInt<1>("h00")) @[dec_decode_ctl.scala 781:89] + node _T_995 = and(_T_993, _T_994) @[dec_decode_ctl.scala 781:87] + node _T_996 = eq(i0_block_raw_d, UInt<1>("h00")) @[dec_decode_ctl.scala 781:123] + node _T_997 = and(_T_995, _T_996) @[dec_decode_ctl.scala 781:121] + node _T_998 = or(_T_997, io.decode_exu.dec_extint_stall) @[dec_decode_ctl.scala 781:140] + io.dec_lsu_valid_raw_d <= _T_998 @[dec_decode_ctl.scala 781:26] + node _T_999 = eq(io.decode_exu.dec_extint_stall, UInt<1>("h00")) @[dec_decode_ctl.scala 783:6] + node _T_1000 = and(_T_999, i0_dp.lsu) @[dec_decode_ctl.scala 783:38] + node _T_1001 = and(_T_1000, i0_dp.load) @[dec_decode_ctl.scala 783:50] + node _T_1002 = bits(_T_1001, 0, 0) @[dec_decode_ctl.scala 783:64] + node _T_1003 = bits(io.dec_i0_instr_d, 31, 20) @[dec_decode_ctl.scala 783:81] + node _T_1004 = eq(io.decode_exu.dec_extint_stall, UInt<1>("h00")) @[dec_decode_ctl.scala 784:6] + node _T_1005 = and(_T_1004, i0_dp.lsu) @[dec_decode_ctl.scala 784:38] + node _T_1006 = and(_T_1005, i0_dp.store) @[dec_decode_ctl.scala 784:50] + node _T_1007 = bits(_T_1006, 0, 0) @[dec_decode_ctl.scala 784:65] + node _T_1008 = bits(io.dec_i0_instr_d, 31, 25) @[dec_decode_ctl.scala 784:85] + node _T_1009 = bits(io.dec_i0_instr_d, 11, 7) @[dec_decode_ctl.scala 784:95] + node _T_1010 = cat(_T_1008, _T_1009) @[Cat.scala 29:58] + node _T_1011 = mux(_T_1002, _T_1003, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1012 = mux(_T_1007, _T_1010, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1013 = or(_T_1011, _T_1012) @[Mux.scala 27:72] + wire _T_1014 : UInt<12> @[Mux.scala 27:72] + _T_1014 <= _T_1013 @[Mux.scala 27:72] + io.dec_lsu_offset_d <= _T_1014 @[dec_decode_ctl.scala 782:23] extmodule gated_latch_681 : output Q : Clock @@ -74020,380 +74028,381 @@ circuit quasar_wrapper : node _T_751 = eq(_T_750, UInt<12>("h07ca")) @[dec_tlu_ctl.scala 2127:100] node _T_752 = and(_T_749, _T_751) @[dec_tlu_ctl.scala 2127:71] node _T_753 = bits(_T_752, 0, 0) @[dec_tlu_ctl.scala 2129:34] - node _T_754 = bits(io.ifu_ic_debug_rd_data, 70, 64) @[dec_tlu_ctl.scala 2129:86] - node _T_755 = mux(_T_753, io.dec_csr_wrdata_r, _T_754) @[dec_tlu_ctl.scala 2129:21] - node _T_756 = or(_T_752, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2131:78] - node _T_757 = bits(_T_756, 0, 0) @[dec_tlu_ctl.scala 2131:111] - reg _T_758 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_757 : @[Reg.scala 28:19] - _T_758 <= _T_755 @[Reg.scala 28:23] + node _T_754 = bits(io.dec_csr_wrdata_r, 6, 0) @[dec_tlu_ctl.scala 2129:61] + node _T_755 = bits(io.ifu_ic_debug_rd_data, 70, 64) @[dec_tlu_ctl.scala 2129:91] + node _T_756 = mux(_T_753, _T_754, _T_755) @[dec_tlu_ctl.scala 2129:21] + node _T_757 = or(_T_752, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2131:78] + node _T_758 = bits(_T_757, 0, 0) @[dec_tlu_ctl.scala 2131:111] + reg _T_759 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_758 : @[Reg.scala 28:19] + _T_759 <= _T_756 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - _T_748 <= _T_758 @[dec_tlu_ctl.scala 2131:13] - node _T_759 = cat(UInt<25>("h00"), _T_748) @[Cat.scala 29:58] - dicad1 <= _T_759 @[dec_tlu_ctl.scala 2132:9] - node _T_760 = bits(dicad1, 6, 0) @[dec_tlu_ctl.scala 2154:74] - node _T_761 = bits(dicad0h, 31, 0) @[dec_tlu_ctl.scala 2154:88] - node _T_762 = bits(dicad0, 31, 0) @[dec_tlu_ctl.scala 2154:102] - node _T_763 = cat(_T_760, _T_761) @[Cat.scala 29:58] - node _T_764 = cat(_T_763, _T_762) @[Cat.scala 29:58] - io.dec_tlu_ic_diag_pkt.icache_wrdata <= _T_764 @[dec_tlu_ctl.scala 2154:61] + _T_748 <= _T_759 @[dec_tlu_ctl.scala 2131:13] + node _T_760 = cat(UInt<25>("h00"), _T_748) @[Cat.scala 29:58] + dicad1 <= _T_760 @[dec_tlu_ctl.scala 2132:9] + node _T_761 = bits(dicad1, 6, 0) @[dec_tlu_ctl.scala 2154:69] + node _T_762 = bits(dicad0h, 31, 0) @[dec_tlu_ctl.scala 2154:83] + node _T_763 = bits(dicad0, 31, 0) @[dec_tlu_ctl.scala 2154:97] + node _T_764 = cat(_T_761, _T_762) @[Cat.scala 29:58] + node _T_765 = cat(_T_764, _T_763) @[Cat.scala 29:58] + io.dec_tlu_ic_diag_pkt.icache_wrdata <= _T_765 @[dec_tlu_ctl.scala 2154:56] io.dec_tlu_ic_diag_pkt.icache_dicawics <= dicawics @[dec_tlu_ctl.scala 2157:41] - node _T_765 = and(io.allow_dbg_halt_csr_write, io.dec_csr_any_unq_d) @[dec_tlu_ctl.scala 2159:52] - node _T_766 = and(_T_765, io.dec_i0_decode_d) @[dec_tlu_ctl.scala 2159:75] - node _T_767 = not(io.dec_csr_wen_unq_d) @[dec_tlu_ctl.scala 2159:98] - node _T_768 = and(_T_766, _T_767) @[dec_tlu_ctl.scala 2159:96] - node _T_769 = bits(io.dec_csr_rdaddr_d, 11, 0) @[dec_tlu_ctl.scala 2159:142] - node _T_770 = eq(_T_769, UInt<12>("h07cb")) @[dec_tlu_ctl.scala 2159:149] - node icache_rd_valid = and(_T_768, _T_770) @[dec_tlu_ctl.scala 2159:120] - node _T_771 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2160:52] - node _T_772 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2160:97] - node _T_773 = eq(_T_772, UInt<12>("h07cb")) @[dec_tlu_ctl.scala 2160:104] - node icache_wr_valid = and(_T_771, _T_773) @[dec_tlu_ctl.scala 2160:75] + node _T_766 = and(io.allow_dbg_halt_csr_write, io.dec_csr_any_unq_d) @[dec_tlu_ctl.scala 2159:52] + node _T_767 = and(_T_766, io.dec_i0_decode_d) @[dec_tlu_ctl.scala 2159:75] + node _T_768 = not(io.dec_csr_wen_unq_d) @[dec_tlu_ctl.scala 2159:98] + node _T_769 = and(_T_767, _T_768) @[dec_tlu_ctl.scala 2159:96] + node _T_770 = bits(io.dec_csr_rdaddr_d, 11, 0) @[dec_tlu_ctl.scala 2159:142] + node _T_771 = eq(_T_770, UInt<12>("h07cb")) @[dec_tlu_ctl.scala 2159:149] + node icache_rd_valid = and(_T_769, _T_771) @[dec_tlu_ctl.scala 2159:120] + node _T_772 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2160:52] + node _T_773 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2160:97] + node _T_774 = eq(_T_773, UInt<12>("h07cb")) @[dec_tlu_ctl.scala 2160:104] + node icache_wr_valid = and(_T_772, _T_774) @[dec_tlu_ctl.scala 2160:75] reg icache_rd_valid_f : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2162:58] icache_rd_valid_f <= icache_rd_valid @[dec_tlu_ctl.scala 2162:58] reg icache_wr_valid_f : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2163:58] icache_wr_valid_f <= icache_wr_valid @[dec_tlu_ctl.scala 2163:58] io.dec_tlu_ic_diag_pkt.icache_rd_valid <= icache_rd_valid_f @[dec_tlu_ctl.scala 2165:41] io.dec_tlu_ic_diag_pkt.icache_wr_valid <= icache_wr_valid_f @[dec_tlu_ctl.scala 2166:41] - node _T_774 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2174:62] - node _T_775 = eq(_T_774, UInt<12>("h07a0")) @[dec_tlu_ctl.scala 2174:69] - node wr_mtsel_r = and(io.dec_csr_wen_r_mod, _T_775) @[dec_tlu_ctl.scala 2174:40] - node _T_776 = bits(wr_mtsel_r, 0, 0) @[dec_tlu_ctl.scala 2175:32] - node _T_777 = bits(io.dec_csr_wrdata_r, 1, 0) @[dec_tlu_ctl.scala 2175:59] - node mtsel_ns = mux(_T_776, _T_777, mtsel) @[dec_tlu_ctl.scala 2175:20] - reg _T_778 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2177:43] - _T_778 <= mtsel_ns @[dec_tlu_ctl.scala 2177:43] - mtsel <= _T_778 @[dec_tlu_ctl.scala 2177:8] - node _T_779 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 2212:38] - node _T_780 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 2212:64] - node _T_781 = not(_T_780) @[dec_tlu_ctl.scala 2212:44] - node tdata_load = and(_T_779, _T_781) @[dec_tlu_ctl.scala 2212:42] - node _T_782 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 2214:40] - node _T_783 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 2214:66] - node _T_784 = not(_T_783) @[dec_tlu_ctl.scala 2214:46] - node tdata_opcode = and(_T_782, _T_784) @[dec_tlu_ctl.scala 2214:44] - node _T_785 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 2216:41] - node _T_786 = and(_T_785, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2216:46] - node _T_787 = bits(io.dec_csr_wrdata_r, 12, 12) @[dec_tlu_ctl.scala 2216:90] - node tdata_action = and(_T_786, _T_787) @[dec_tlu_ctl.scala 2216:69] - node _T_788 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 2218:47] - node _T_789 = and(_T_788, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2218:52] - node _T_790 = bits(io.dec_csr_wrdata_r, 20, 19) @[dec_tlu_ctl.scala 2218:94] - node _T_791 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 2218:136] - node _T_792 = bits(io.dec_csr_wrdata_r, 7, 6) @[dec_tlu_ctl.scala 2219:43] - node _T_793 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 2219:83] - node _T_794 = cat(_T_793, tdata_load) @[Cat.scala 29:58] - node _T_795 = cat(_T_792, tdata_opcode) @[Cat.scala 29:58] - node _T_796 = cat(_T_795, _T_794) @[Cat.scala 29:58] - node _T_797 = cat(tdata_action, _T_791) @[Cat.scala 29:58] - node _T_798 = cat(_T_789, _T_790) @[Cat.scala 29:58] - node _T_799 = cat(_T_798, _T_797) @[Cat.scala 29:58] - node tdata_wrdata_r = cat(_T_799, _T_796) @[Cat.scala 29:58] - node _T_800 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2222:92] - node _T_801 = eq(_T_800, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2222:99] - node _T_802 = and(io.dec_csr_wen_r_mod, _T_801) @[dec_tlu_ctl.scala 2222:70] - node _T_803 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2222:121] - node _T_804 = and(_T_802, _T_803) @[dec_tlu_ctl.scala 2222:112] - node _T_805 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2222:154] - node _T_806 = not(_T_805) @[dec_tlu_ctl.scala 2222:138] - node _T_807 = or(_T_806, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2222:170] - node _T_808 = and(_T_804, _T_807) @[dec_tlu_ctl.scala 2222:135] - node _T_809 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2222:92] - node _T_810 = eq(_T_809, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2222:99] - node _T_811 = and(io.dec_csr_wen_r_mod, _T_810) @[dec_tlu_ctl.scala 2222:70] - node _T_812 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2222:121] - node _T_813 = and(_T_811, _T_812) @[dec_tlu_ctl.scala 2222:112] - node _T_814 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2222:154] - node _T_815 = not(_T_814) @[dec_tlu_ctl.scala 2222:138] - node _T_816 = or(_T_815, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2222:170] - node _T_817 = and(_T_813, _T_816) @[dec_tlu_ctl.scala 2222:135] - node _T_818 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2222:92] - node _T_819 = eq(_T_818, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2222:99] - node _T_820 = and(io.dec_csr_wen_r_mod, _T_819) @[dec_tlu_ctl.scala 2222:70] - node _T_821 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2222:121] - node _T_822 = and(_T_820, _T_821) @[dec_tlu_ctl.scala 2222:112] - node _T_823 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2222:154] - node _T_824 = not(_T_823) @[dec_tlu_ctl.scala 2222:138] - node _T_825 = or(_T_824, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2222:170] - node _T_826 = and(_T_822, _T_825) @[dec_tlu_ctl.scala 2222:135] - node _T_827 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2222:92] - node _T_828 = eq(_T_827, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2222:99] - node _T_829 = and(io.dec_csr_wen_r_mod, _T_828) @[dec_tlu_ctl.scala 2222:70] - node _T_830 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2222:121] - node _T_831 = and(_T_829, _T_830) @[dec_tlu_ctl.scala 2222:112] - node _T_832 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2222:154] - node _T_833 = not(_T_832) @[dec_tlu_ctl.scala 2222:138] - node _T_834 = or(_T_833, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2222:170] - node _T_835 = and(_T_831, _T_834) @[dec_tlu_ctl.scala 2222:135] + node _T_775 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2174:62] + node _T_776 = eq(_T_775, UInt<12>("h07a0")) @[dec_tlu_ctl.scala 2174:69] + node wr_mtsel_r = and(io.dec_csr_wen_r_mod, _T_776) @[dec_tlu_ctl.scala 2174:40] + node _T_777 = bits(wr_mtsel_r, 0, 0) @[dec_tlu_ctl.scala 2175:32] + node _T_778 = bits(io.dec_csr_wrdata_r, 1, 0) @[dec_tlu_ctl.scala 2175:59] + node mtsel_ns = mux(_T_777, _T_778, mtsel) @[dec_tlu_ctl.scala 2175:20] + reg _T_779 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2177:43] + _T_779 <= mtsel_ns @[dec_tlu_ctl.scala 2177:43] + mtsel <= _T_779 @[dec_tlu_ctl.scala 2177:8] + node _T_780 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 2212:38] + node _T_781 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 2212:64] + node _T_782 = not(_T_781) @[dec_tlu_ctl.scala 2212:44] + node tdata_load = and(_T_780, _T_782) @[dec_tlu_ctl.scala 2212:42] + node _T_783 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 2214:40] + node _T_784 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 2214:66] + node _T_785 = not(_T_784) @[dec_tlu_ctl.scala 2214:46] + node tdata_opcode = and(_T_783, _T_785) @[dec_tlu_ctl.scala 2214:44] + node _T_786 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 2216:41] + node _T_787 = and(_T_786, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2216:46] + node _T_788 = bits(io.dec_csr_wrdata_r, 12, 12) @[dec_tlu_ctl.scala 2216:90] + node tdata_action = and(_T_787, _T_788) @[dec_tlu_ctl.scala 2216:69] + node _T_789 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 2218:47] + node _T_790 = and(_T_789, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2218:52] + node _T_791 = bits(io.dec_csr_wrdata_r, 20, 19) @[dec_tlu_ctl.scala 2218:94] + node _T_792 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 2218:136] + node _T_793 = bits(io.dec_csr_wrdata_r, 7, 6) @[dec_tlu_ctl.scala 2219:43] + node _T_794 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 2219:83] + node _T_795 = cat(_T_794, tdata_load) @[Cat.scala 29:58] + node _T_796 = cat(_T_793, tdata_opcode) @[Cat.scala 29:58] + node _T_797 = cat(_T_796, _T_795) @[Cat.scala 29:58] + node _T_798 = cat(tdata_action, _T_792) @[Cat.scala 29:58] + node _T_799 = cat(_T_790, _T_791) @[Cat.scala 29:58] + node _T_800 = cat(_T_799, _T_798) @[Cat.scala 29:58] + node tdata_wrdata_r = cat(_T_800, _T_797) @[Cat.scala 29:58] + node _T_801 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2222:92] + node _T_802 = eq(_T_801, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2222:99] + node _T_803 = and(io.dec_csr_wen_r_mod, _T_802) @[dec_tlu_ctl.scala 2222:70] + node _T_804 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2222:121] + node _T_805 = and(_T_803, _T_804) @[dec_tlu_ctl.scala 2222:112] + node _T_806 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2222:154] + node _T_807 = not(_T_806) @[dec_tlu_ctl.scala 2222:138] + node _T_808 = or(_T_807, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2222:170] + node _T_809 = and(_T_805, _T_808) @[dec_tlu_ctl.scala 2222:135] + node _T_810 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2222:92] + node _T_811 = eq(_T_810, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2222:99] + node _T_812 = and(io.dec_csr_wen_r_mod, _T_811) @[dec_tlu_ctl.scala 2222:70] + node _T_813 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2222:121] + node _T_814 = and(_T_812, _T_813) @[dec_tlu_ctl.scala 2222:112] + node _T_815 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2222:154] + node _T_816 = not(_T_815) @[dec_tlu_ctl.scala 2222:138] + node _T_817 = or(_T_816, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2222:170] + node _T_818 = and(_T_814, _T_817) @[dec_tlu_ctl.scala 2222:135] + node _T_819 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2222:92] + node _T_820 = eq(_T_819, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2222:99] + node _T_821 = and(io.dec_csr_wen_r_mod, _T_820) @[dec_tlu_ctl.scala 2222:70] + node _T_822 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2222:121] + node _T_823 = and(_T_821, _T_822) @[dec_tlu_ctl.scala 2222:112] + node _T_824 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2222:154] + node _T_825 = not(_T_824) @[dec_tlu_ctl.scala 2222:138] + node _T_826 = or(_T_825, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2222:170] + node _T_827 = and(_T_823, _T_826) @[dec_tlu_ctl.scala 2222:135] + node _T_828 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2222:92] + node _T_829 = eq(_T_828, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2222:99] + node _T_830 = and(io.dec_csr_wen_r_mod, _T_829) @[dec_tlu_ctl.scala 2222:70] + node _T_831 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2222:121] + node _T_832 = and(_T_830, _T_831) @[dec_tlu_ctl.scala 2222:112] + node _T_833 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2222:154] + node _T_834 = not(_T_833) @[dec_tlu_ctl.scala 2222:138] + node _T_835 = or(_T_834, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2222:170] + node _T_836 = and(_T_832, _T_835) @[dec_tlu_ctl.scala 2222:135] wire wr_mtdata1_t_r : UInt<1>[4] @[dec_tlu_ctl.scala 2222:42] - wr_mtdata1_t_r[0] <= _T_808 @[dec_tlu_ctl.scala 2222:42] - wr_mtdata1_t_r[1] <= _T_817 @[dec_tlu_ctl.scala 2222:42] - wr_mtdata1_t_r[2] <= _T_826 @[dec_tlu_ctl.scala 2222:42] - wr_mtdata1_t_r[3] <= _T_835 @[dec_tlu_ctl.scala 2222:42] - node _T_836 = bits(wr_mtdata1_t_r[0], 0, 0) @[dec_tlu_ctl.scala 2223:68] - node _T_837 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2223:111] - node _T_838 = bits(io.update_hit_bit_r, 0, 0) @[dec_tlu_ctl.scala 2223:135] - node _T_839 = bits(io.mtdata1_t[0], 8, 8) @[dec_tlu_ctl.scala 2223:156] - node _T_840 = or(_T_838, _T_839) @[dec_tlu_ctl.scala 2223:139] - node _T_841 = bits(io.mtdata1_t[0], 7, 0) @[dec_tlu_ctl.scala 2223:176] - node _T_842 = cat(_T_837, _T_840) @[Cat.scala 29:58] - node _T_843 = cat(_T_842, _T_841) @[Cat.scala 29:58] - node _T_844 = mux(_T_836, tdata_wrdata_r, _T_843) @[dec_tlu_ctl.scala 2223:49] - node _T_845 = bits(wr_mtdata1_t_r[1], 0, 0) @[dec_tlu_ctl.scala 2223:68] - node _T_846 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2223:111] - node _T_847 = bits(io.update_hit_bit_r, 1, 1) @[dec_tlu_ctl.scala 2223:135] - node _T_848 = bits(io.mtdata1_t[1], 8, 8) @[dec_tlu_ctl.scala 2223:156] - node _T_849 = or(_T_847, _T_848) @[dec_tlu_ctl.scala 2223:139] - node _T_850 = bits(io.mtdata1_t[1], 7, 0) @[dec_tlu_ctl.scala 2223:176] - node _T_851 = cat(_T_846, _T_849) @[Cat.scala 29:58] - node _T_852 = cat(_T_851, _T_850) @[Cat.scala 29:58] - node _T_853 = mux(_T_845, tdata_wrdata_r, _T_852) @[dec_tlu_ctl.scala 2223:49] - node _T_854 = bits(wr_mtdata1_t_r[2], 0, 0) @[dec_tlu_ctl.scala 2223:68] - node _T_855 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2223:111] - node _T_856 = bits(io.update_hit_bit_r, 2, 2) @[dec_tlu_ctl.scala 2223:135] - node _T_857 = bits(io.mtdata1_t[2], 8, 8) @[dec_tlu_ctl.scala 2223:156] - node _T_858 = or(_T_856, _T_857) @[dec_tlu_ctl.scala 2223:139] - node _T_859 = bits(io.mtdata1_t[2], 7, 0) @[dec_tlu_ctl.scala 2223:176] - node _T_860 = cat(_T_855, _T_858) @[Cat.scala 29:58] - node _T_861 = cat(_T_860, _T_859) @[Cat.scala 29:58] - node _T_862 = mux(_T_854, tdata_wrdata_r, _T_861) @[dec_tlu_ctl.scala 2223:49] - node _T_863 = bits(wr_mtdata1_t_r[3], 0, 0) @[dec_tlu_ctl.scala 2223:68] - node _T_864 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2223:111] - node _T_865 = bits(io.update_hit_bit_r, 3, 3) @[dec_tlu_ctl.scala 2223:135] - node _T_866 = bits(io.mtdata1_t[3], 8, 8) @[dec_tlu_ctl.scala 2223:156] - node _T_867 = or(_T_865, _T_866) @[dec_tlu_ctl.scala 2223:139] - node _T_868 = bits(io.mtdata1_t[3], 7, 0) @[dec_tlu_ctl.scala 2223:176] - node _T_869 = cat(_T_864, _T_867) @[Cat.scala 29:58] - node _T_870 = cat(_T_869, _T_868) @[Cat.scala 29:58] - node _T_871 = mux(_T_863, tdata_wrdata_r, _T_870) @[dec_tlu_ctl.scala 2223:49] + wr_mtdata1_t_r[0] <= _T_809 @[dec_tlu_ctl.scala 2222:42] + wr_mtdata1_t_r[1] <= _T_818 @[dec_tlu_ctl.scala 2222:42] + wr_mtdata1_t_r[2] <= _T_827 @[dec_tlu_ctl.scala 2222:42] + wr_mtdata1_t_r[3] <= _T_836 @[dec_tlu_ctl.scala 2222:42] + node _T_837 = bits(wr_mtdata1_t_r[0], 0, 0) @[dec_tlu_ctl.scala 2223:68] + node _T_838 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2223:111] + node _T_839 = bits(io.update_hit_bit_r, 0, 0) @[dec_tlu_ctl.scala 2223:135] + node _T_840 = bits(io.mtdata1_t[0], 8, 8) @[dec_tlu_ctl.scala 2223:156] + node _T_841 = or(_T_839, _T_840) @[dec_tlu_ctl.scala 2223:139] + node _T_842 = bits(io.mtdata1_t[0], 7, 0) @[dec_tlu_ctl.scala 2223:176] + node _T_843 = cat(_T_838, _T_841) @[Cat.scala 29:58] + node _T_844 = cat(_T_843, _T_842) @[Cat.scala 29:58] + node _T_845 = mux(_T_837, tdata_wrdata_r, _T_844) @[dec_tlu_ctl.scala 2223:49] + node _T_846 = bits(wr_mtdata1_t_r[1], 0, 0) @[dec_tlu_ctl.scala 2223:68] + node _T_847 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2223:111] + node _T_848 = bits(io.update_hit_bit_r, 1, 1) @[dec_tlu_ctl.scala 2223:135] + node _T_849 = bits(io.mtdata1_t[1], 8, 8) @[dec_tlu_ctl.scala 2223:156] + node _T_850 = or(_T_848, _T_849) @[dec_tlu_ctl.scala 2223:139] + node _T_851 = bits(io.mtdata1_t[1], 7, 0) @[dec_tlu_ctl.scala 2223:176] + node _T_852 = cat(_T_847, _T_850) @[Cat.scala 29:58] + node _T_853 = cat(_T_852, _T_851) @[Cat.scala 29:58] + node _T_854 = mux(_T_846, tdata_wrdata_r, _T_853) @[dec_tlu_ctl.scala 2223:49] + node _T_855 = bits(wr_mtdata1_t_r[2], 0, 0) @[dec_tlu_ctl.scala 2223:68] + node _T_856 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2223:111] + node _T_857 = bits(io.update_hit_bit_r, 2, 2) @[dec_tlu_ctl.scala 2223:135] + node _T_858 = bits(io.mtdata1_t[2], 8, 8) @[dec_tlu_ctl.scala 2223:156] + node _T_859 = or(_T_857, _T_858) @[dec_tlu_ctl.scala 2223:139] + node _T_860 = bits(io.mtdata1_t[2], 7, 0) @[dec_tlu_ctl.scala 2223:176] + node _T_861 = cat(_T_856, _T_859) @[Cat.scala 29:58] + node _T_862 = cat(_T_861, _T_860) @[Cat.scala 29:58] + node _T_863 = mux(_T_855, tdata_wrdata_r, _T_862) @[dec_tlu_ctl.scala 2223:49] + node _T_864 = bits(wr_mtdata1_t_r[3], 0, 0) @[dec_tlu_ctl.scala 2223:68] + node _T_865 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2223:111] + node _T_866 = bits(io.update_hit_bit_r, 3, 3) @[dec_tlu_ctl.scala 2223:135] + node _T_867 = bits(io.mtdata1_t[3], 8, 8) @[dec_tlu_ctl.scala 2223:156] + node _T_868 = or(_T_866, _T_867) @[dec_tlu_ctl.scala 2223:139] + node _T_869 = bits(io.mtdata1_t[3], 7, 0) @[dec_tlu_ctl.scala 2223:176] + node _T_870 = cat(_T_865, _T_868) @[Cat.scala 29:58] + node _T_871 = cat(_T_870, _T_869) @[Cat.scala 29:58] + node _T_872 = mux(_T_864, tdata_wrdata_r, _T_871) @[dec_tlu_ctl.scala 2223:49] wire mtdata1_t_ns : UInt<10>[4] @[dec_tlu_ctl.scala 2223:40] - mtdata1_t_ns[0] <= _T_844 @[dec_tlu_ctl.scala 2223:40] - mtdata1_t_ns[1] <= _T_853 @[dec_tlu_ctl.scala 2223:40] - mtdata1_t_ns[2] <= _T_862 @[dec_tlu_ctl.scala 2223:40] - mtdata1_t_ns[3] <= _T_871 @[dec_tlu_ctl.scala 2223:40] - reg _T_872 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2225:74] - _T_872 <= mtdata1_t_ns[0] @[dec_tlu_ctl.scala 2225:74] - io.mtdata1_t[0] <= _T_872 @[dec_tlu_ctl.scala 2225:39] + mtdata1_t_ns[0] <= _T_845 @[dec_tlu_ctl.scala 2223:40] + mtdata1_t_ns[1] <= _T_854 @[dec_tlu_ctl.scala 2223:40] + mtdata1_t_ns[2] <= _T_863 @[dec_tlu_ctl.scala 2223:40] + mtdata1_t_ns[3] <= _T_872 @[dec_tlu_ctl.scala 2223:40] reg _T_873 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2225:74] - _T_873 <= mtdata1_t_ns[1] @[dec_tlu_ctl.scala 2225:74] - io.mtdata1_t[1] <= _T_873 @[dec_tlu_ctl.scala 2225:39] + _T_873 <= mtdata1_t_ns[0] @[dec_tlu_ctl.scala 2225:74] + io.mtdata1_t[0] <= _T_873 @[dec_tlu_ctl.scala 2225:39] reg _T_874 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2225:74] - _T_874 <= mtdata1_t_ns[2] @[dec_tlu_ctl.scala 2225:74] - io.mtdata1_t[2] <= _T_874 @[dec_tlu_ctl.scala 2225:39] + _T_874 <= mtdata1_t_ns[1] @[dec_tlu_ctl.scala 2225:74] + io.mtdata1_t[1] <= _T_874 @[dec_tlu_ctl.scala 2225:39] reg _T_875 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2225:74] - _T_875 <= mtdata1_t_ns[3] @[dec_tlu_ctl.scala 2225:74] - io.mtdata1_t[3] <= _T_875 @[dec_tlu_ctl.scala 2225:39] - node _T_876 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2228:58] - node _T_877 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2228:104] - node _T_878 = bits(io.mtdata1_t[0], 8, 7) @[dec_tlu_ctl.scala 2228:142] - node _T_879 = bits(io.mtdata1_t[0], 6, 5) @[dec_tlu_ctl.scala 2228:174] - node _T_880 = bits(io.mtdata1_t[0], 4, 3) @[dec_tlu_ctl.scala 2228:206] - node _T_881 = bits(io.mtdata1_t[0], 2, 0) @[dec_tlu_ctl.scala 2228:238] - node _T_882 = cat(UInt<3>("h00"), _T_881) @[Cat.scala 29:58] - node _T_883 = cat(_T_879, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_884 = cat(_T_883, _T_880) @[Cat.scala 29:58] - node _T_885 = cat(_T_884, _T_882) @[Cat.scala 29:58] - node _T_886 = cat(_T_878, UInt<6>("h00")) @[Cat.scala 29:58] - node _T_887 = cat(UInt<4>("h02"), _T_877) @[Cat.scala 29:58] - node _T_888 = cat(_T_887, UInt<6>("h01f")) @[Cat.scala 29:58] - node _T_889 = cat(_T_888, _T_886) @[Cat.scala 29:58] - node _T_890 = cat(_T_889, _T_885) @[Cat.scala 29:58] - node _T_891 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2228:58] - node _T_892 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2228:104] - node _T_893 = bits(io.mtdata1_t[1], 8, 7) @[dec_tlu_ctl.scala 2228:142] - node _T_894 = bits(io.mtdata1_t[1], 6, 5) @[dec_tlu_ctl.scala 2228:174] - node _T_895 = bits(io.mtdata1_t[1], 4, 3) @[dec_tlu_ctl.scala 2228:206] - node _T_896 = bits(io.mtdata1_t[1], 2, 0) @[dec_tlu_ctl.scala 2228:238] - node _T_897 = cat(UInt<3>("h00"), _T_896) @[Cat.scala 29:58] - node _T_898 = cat(_T_894, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_899 = cat(_T_898, _T_895) @[Cat.scala 29:58] - node _T_900 = cat(_T_899, _T_897) @[Cat.scala 29:58] - node _T_901 = cat(_T_893, UInt<6>("h00")) @[Cat.scala 29:58] - node _T_902 = cat(UInt<4>("h02"), _T_892) @[Cat.scala 29:58] - node _T_903 = cat(_T_902, UInt<6>("h01f")) @[Cat.scala 29:58] - node _T_904 = cat(_T_903, _T_901) @[Cat.scala 29:58] - node _T_905 = cat(_T_904, _T_900) @[Cat.scala 29:58] - node _T_906 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2228:58] - node _T_907 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2228:104] - node _T_908 = bits(io.mtdata1_t[2], 8, 7) @[dec_tlu_ctl.scala 2228:142] - node _T_909 = bits(io.mtdata1_t[2], 6, 5) @[dec_tlu_ctl.scala 2228:174] - node _T_910 = bits(io.mtdata1_t[2], 4, 3) @[dec_tlu_ctl.scala 2228:206] - node _T_911 = bits(io.mtdata1_t[2], 2, 0) @[dec_tlu_ctl.scala 2228:238] - node _T_912 = cat(UInt<3>("h00"), _T_911) @[Cat.scala 29:58] - node _T_913 = cat(_T_909, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_914 = cat(_T_913, _T_910) @[Cat.scala 29:58] - node _T_915 = cat(_T_914, _T_912) @[Cat.scala 29:58] - node _T_916 = cat(_T_908, UInt<6>("h00")) @[Cat.scala 29:58] - node _T_917 = cat(UInt<4>("h02"), _T_907) @[Cat.scala 29:58] - node _T_918 = cat(_T_917, UInt<6>("h01f")) @[Cat.scala 29:58] - node _T_919 = cat(_T_918, _T_916) @[Cat.scala 29:58] - node _T_920 = cat(_T_919, _T_915) @[Cat.scala 29:58] - node _T_921 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2228:58] - node _T_922 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2228:104] - node _T_923 = bits(io.mtdata1_t[3], 8, 7) @[dec_tlu_ctl.scala 2228:142] - node _T_924 = bits(io.mtdata1_t[3], 6, 5) @[dec_tlu_ctl.scala 2228:174] - node _T_925 = bits(io.mtdata1_t[3], 4, 3) @[dec_tlu_ctl.scala 2228:206] - node _T_926 = bits(io.mtdata1_t[3], 2, 0) @[dec_tlu_ctl.scala 2228:238] - node _T_927 = cat(UInt<3>("h00"), _T_926) @[Cat.scala 29:58] - node _T_928 = cat(_T_924, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_929 = cat(_T_928, _T_925) @[Cat.scala 29:58] - node _T_930 = cat(_T_929, _T_927) @[Cat.scala 29:58] - node _T_931 = cat(_T_923, UInt<6>("h00")) @[Cat.scala 29:58] - node _T_932 = cat(UInt<4>("h02"), _T_922) @[Cat.scala 29:58] - node _T_933 = cat(_T_932, UInt<6>("h01f")) @[Cat.scala 29:58] - node _T_934 = cat(_T_933, _T_931) @[Cat.scala 29:58] - node _T_935 = cat(_T_934, _T_930) @[Cat.scala 29:58] - node _T_936 = mux(_T_876, _T_890, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_937 = mux(_T_891, _T_905, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_938 = mux(_T_906, _T_920, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_939 = mux(_T_921, _T_935, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_940 = or(_T_936, _T_937) @[Mux.scala 27:72] - node _T_941 = or(_T_940, _T_938) @[Mux.scala 27:72] + _T_875 <= mtdata1_t_ns[2] @[dec_tlu_ctl.scala 2225:74] + io.mtdata1_t[2] <= _T_875 @[dec_tlu_ctl.scala 2225:39] + reg _T_876 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2225:74] + _T_876 <= mtdata1_t_ns[3] @[dec_tlu_ctl.scala 2225:74] + io.mtdata1_t[3] <= _T_876 @[dec_tlu_ctl.scala 2225:39] + node _T_877 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2228:58] + node _T_878 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2228:104] + node _T_879 = bits(io.mtdata1_t[0], 8, 7) @[dec_tlu_ctl.scala 2228:142] + node _T_880 = bits(io.mtdata1_t[0], 6, 5) @[dec_tlu_ctl.scala 2228:174] + node _T_881 = bits(io.mtdata1_t[0], 4, 3) @[dec_tlu_ctl.scala 2228:206] + node _T_882 = bits(io.mtdata1_t[0], 2, 0) @[dec_tlu_ctl.scala 2228:238] + node _T_883 = cat(UInt<3>("h00"), _T_882) @[Cat.scala 29:58] + node _T_884 = cat(_T_880, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_885 = cat(_T_884, _T_881) @[Cat.scala 29:58] + node _T_886 = cat(_T_885, _T_883) @[Cat.scala 29:58] + node _T_887 = cat(_T_879, UInt<6>("h00")) @[Cat.scala 29:58] + node _T_888 = cat(UInt<4>("h02"), _T_878) @[Cat.scala 29:58] + node _T_889 = cat(_T_888, UInt<6>("h01f")) @[Cat.scala 29:58] + node _T_890 = cat(_T_889, _T_887) @[Cat.scala 29:58] + node _T_891 = cat(_T_890, _T_886) @[Cat.scala 29:58] + node _T_892 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2228:58] + node _T_893 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2228:104] + node _T_894 = bits(io.mtdata1_t[1], 8, 7) @[dec_tlu_ctl.scala 2228:142] + node _T_895 = bits(io.mtdata1_t[1], 6, 5) @[dec_tlu_ctl.scala 2228:174] + node _T_896 = bits(io.mtdata1_t[1], 4, 3) @[dec_tlu_ctl.scala 2228:206] + node _T_897 = bits(io.mtdata1_t[1], 2, 0) @[dec_tlu_ctl.scala 2228:238] + node _T_898 = cat(UInt<3>("h00"), _T_897) @[Cat.scala 29:58] + node _T_899 = cat(_T_895, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_900 = cat(_T_899, _T_896) @[Cat.scala 29:58] + node _T_901 = cat(_T_900, _T_898) @[Cat.scala 29:58] + node _T_902 = cat(_T_894, UInt<6>("h00")) @[Cat.scala 29:58] + node _T_903 = cat(UInt<4>("h02"), _T_893) @[Cat.scala 29:58] + node _T_904 = cat(_T_903, UInt<6>("h01f")) @[Cat.scala 29:58] + node _T_905 = cat(_T_904, _T_902) @[Cat.scala 29:58] + node _T_906 = cat(_T_905, _T_901) @[Cat.scala 29:58] + node _T_907 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2228:58] + node _T_908 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2228:104] + node _T_909 = bits(io.mtdata1_t[2], 8, 7) @[dec_tlu_ctl.scala 2228:142] + node _T_910 = bits(io.mtdata1_t[2], 6, 5) @[dec_tlu_ctl.scala 2228:174] + node _T_911 = bits(io.mtdata1_t[2], 4, 3) @[dec_tlu_ctl.scala 2228:206] + node _T_912 = bits(io.mtdata1_t[2], 2, 0) @[dec_tlu_ctl.scala 2228:238] + node _T_913 = cat(UInt<3>("h00"), _T_912) @[Cat.scala 29:58] + node _T_914 = cat(_T_910, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_915 = cat(_T_914, _T_911) @[Cat.scala 29:58] + node _T_916 = cat(_T_915, _T_913) @[Cat.scala 29:58] + node _T_917 = cat(_T_909, UInt<6>("h00")) @[Cat.scala 29:58] + node _T_918 = cat(UInt<4>("h02"), _T_908) @[Cat.scala 29:58] + node _T_919 = cat(_T_918, UInt<6>("h01f")) @[Cat.scala 29:58] + node _T_920 = cat(_T_919, _T_917) @[Cat.scala 29:58] + node _T_921 = cat(_T_920, _T_916) @[Cat.scala 29:58] + node _T_922 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2228:58] + node _T_923 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2228:104] + node _T_924 = bits(io.mtdata1_t[3], 8, 7) @[dec_tlu_ctl.scala 2228:142] + node _T_925 = bits(io.mtdata1_t[3], 6, 5) @[dec_tlu_ctl.scala 2228:174] + node _T_926 = bits(io.mtdata1_t[3], 4, 3) @[dec_tlu_ctl.scala 2228:206] + node _T_927 = bits(io.mtdata1_t[3], 2, 0) @[dec_tlu_ctl.scala 2228:238] + node _T_928 = cat(UInt<3>("h00"), _T_927) @[Cat.scala 29:58] + node _T_929 = cat(_T_925, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_930 = cat(_T_929, _T_926) @[Cat.scala 29:58] + node _T_931 = cat(_T_930, _T_928) @[Cat.scala 29:58] + node _T_932 = cat(_T_924, UInt<6>("h00")) @[Cat.scala 29:58] + node _T_933 = cat(UInt<4>("h02"), _T_923) @[Cat.scala 29:58] + node _T_934 = cat(_T_933, UInt<6>("h01f")) @[Cat.scala 29:58] + node _T_935 = cat(_T_934, _T_932) @[Cat.scala 29:58] + node _T_936 = cat(_T_935, _T_931) @[Cat.scala 29:58] + node _T_937 = mux(_T_877, _T_891, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_938 = mux(_T_892, _T_906, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_939 = mux(_T_907, _T_921, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_940 = mux(_T_922, _T_936, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_941 = or(_T_937, _T_938) @[Mux.scala 27:72] node _T_942 = or(_T_941, _T_939) @[Mux.scala 27:72] + node _T_943 = or(_T_942, _T_940) @[Mux.scala 27:72] wire mtdata1_tsel_out : UInt<32> @[Mux.scala 27:72] - mtdata1_tsel_out <= _T_942 @[Mux.scala 27:72] - node _T_943 = bits(io.mtdata1_t[0], 7, 7) @[dec_tlu_ctl.scala 2230:58] - io.trigger_pkt_any[0].select <= _T_943 @[dec_tlu_ctl.scala 2230:40] - node _T_944 = bits(io.mtdata1_t[0], 4, 4) @[dec_tlu_ctl.scala 2231:61] - io.trigger_pkt_any[0].match_pkt <= _T_944 @[dec_tlu_ctl.scala 2231:43] - node _T_945 = bits(io.mtdata1_t[0], 1, 1) @[dec_tlu_ctl.scala 2232:58] - io.trigger_pkt_any[0].store <= _T_945 @[dec_tlu_ctl.scala 2232:40] - node _T_946 = bits(io.mtdata1_t[0], 0, 0) @[dec_tlu_ctl.scala 2233:58] - io.trigger_pkt_any[0].load <= _T_946 @[dec_tlu_ctl.scala 2233:40] - node _T_947 = bits(io.mtdata1_t[0], 2, 2) @[dec_tlu_ctl.scala 2234:58] - io.trigger_pkt_any[0].execute <= _T_947 @[dec_tlu_ctl.scala 2234:40] - node _T_948 = bits(io.mtdata1_t[0], 3, 3) @[dec_tlu_ctl.scala 2235:58] - io.trigger_pkt_any[0].m <= _T_948 @[dec_tlu_ctl.scala 2235:40] - node _T_949 = bits(io.mtdata1_t[1], 7, 7) @[dec_tlu_ctl.scala 2230:58] - io.trigger_pkt_any[1].select <= _T_949 @[dec_tlu_ctl.scala 2230:40] - node _T_950 = bits(io.mtdata1_t[1], 4, 4) @[dec_tlu_ctl.scala 2231:61] - io.trigger_pkt_any[1].match_pkt <= _T_950 @[dec_tlu_ctl.scala 2231:43] - node _T_951 = bits(io.mtdata1_t[1], 1, 1) @[dec_tlu_ctl.scala 2232:58] - io.trigger_pkt_any[1].store <= _T_951 @[dec_tlu_ctl.scala 2232:40] - node _T_952 = bits(io.mtdata1_t[1], 0, 0) @[dec_tlu_ctl.scala 2233:58] - io.trigger_pkt_any[1].load <= _T_952 @[dec_tlu_ctl.scala 2233:40] - node _T_953 = bits(io.mtdata1_t[1], 2, 2) @[dec_tlu_ctl.scala 2234:58] - io.trigger_pkt_any[1].execute <= _T_953 @[dec_tlu_ctl.scala 2234:40] - node _T_954 = bits(io.mtdata1_t[1], 3, 3) @[dec_tlu_ctl.scala 2235:58] - io.trigger_pkt_any[1].m <= _T_954 @[dec_tlu_ctl.scala 2235:40] - node _T_955 = bits(io.mtdata1_t[2], 7, 7) @[dec_tlu_ctl.scala 2230:58] - io.trigger_pkt_any[2].select <= _T_955 @[dec_tlu_ctl.scala 2230:40] - node _T_956 = bits(io.mtdata1_t[2], 4, 4) @[dec_tlu_ctl.scala 2231:61] - io.trigger_pkt_any[2].match_pkt <= _T_956 @[dec_tlu_ctl.scala 2231:43] - node _T_957 = bits(io.mtdata1_t[2], 1, 1) @[dec_tlu_ctl.scala 2232:58] - io.trigger_pkt_any[2].store <= _T_957 @[dec_tlu_ctl.scala 2232:40] - node _T_958 = bits(io.mtdata1_t[2], 0, 0) @[dec_tlu_ctl.scala 2233:58] - io.trigger_pkt_any[2].load <= _T_958 @[dec_tlu_ctl.scala 2233:40] - node _T_959 = bits(io.mtdata1_t[2], 2, 2) @[dec_tlu_ctl.scala 2234:58] - io.trigger_pkt_any[2].execute <= _T_959 @[dec_tlu_ctl.scala 2234:40] - node _T_960 = bits(io.mtdata1_t[2], 3, 3) @[dec_tlu_ctl.scala 2235:58] - io.trigger_pkt_any[2].m <= _T_960 @[dec_tlu_ctl.scala 2235:40] - node _T_961 = bits(io.mtdata1_t[3], 7, 7) @[dec_tlu_ctl.scala 2230:58] - io.trigger_pkt_any[3].select <= _T_961 @[dec_tlu_ctl.scala 2230:40] - node _T_962 = bits(io.mtdata1_t[3], 4, 4) @[dec_tlu_ctl.scala 2231:61] - io.trigger_pkt_any[3].match_pkt <= _T_962 @[dec_tlu_ctl.scala 2231:43] - node _T_963 = bits(io.mtdata1_t[3], 1, 1) @[dec_tlu_ctl.scala 2232:58] - io.trigger_pkt_any[3].store <= _T_963 @[dec_tlu_ctl.scala 2232:40] - node _T_964 = bits(io.mtdata1_t[3], 0, 0) @[dec_tlu_ctl.scala 2233:58] - io.trigger_pkt_any[3].load <= _T_964 @[dec_tlu_ctl.scala 2233:40] - node _T_965 = bits(io.mtdata1_t[3], 2, 2) @[dec_tlu_ctl.scala 2234:58] - io.trigger_pkt_any[3].execute <= _T_965 @[dec_tlu_ctl.scala 2234:40] - node _T_966 = bits(io.mtdata1_t[3], 3, 3) @[dec_tlu_ctl.scala 2235:58] - io.trigger_pkt_any[3].m <= _T_966 @[dec_tlu_ctl.scala 2235:40] - node _T_967 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2242:91] - node _T_968 = eq(_T_967, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2242:98] - node _T_969 = and(io.dec_csr_wen_r_mod, _T_968) @[dec_tlu_ctl.scala 2242:69] - node _T_970 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2242:120] - node _T_971 = and(_T_969, _T_970) @[dec_tlu_ctl.scala 2242:111] - node _T_972 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2242:153] - node _T_973 = not(_T_972) @[dec_tlu_ctl.scala 2242:137] - node _T_974 = or(_T_973, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2242:169] - node _T_975 = and(_T_971, _T_974) @[dec_tlu_ctl.scala 2242:134] - node _T_976 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2242:91] - node _T_977 = eq(_T_976, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2242:98] - node _T_978 = and(io.dec_csr_wen_r_mod, _T_977) @[dec_tlu_ctl.scala 2242:69] - node _T_979 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2242:120] - node _T_980 = and(_T_978, _T_979) @[dec_tlu_ctl.scala 2242:111] - node _T_981 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2242:153] - node _T_982 = not(_T_981) @[dec_tlu_ctl.scala 2242:137] - node _T_983 = or(_T_982, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2242:169] - node _T_984 = and(_T_980, _T_983) @[dec_tlu_ctl.scala 2242:134] - node _T_985 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2242:91] - node _T_986 = eq(_T_985, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2242:98] - node _T_987 = and(io.dec_csr_wen_r_mod, _T_986) @[dec_tlu_ctl.scala 2242:69] - node _T_988 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2242:120] - node _T_989 = and(_T_987, _T_988) @[dec_tlu_ctl.scala 2242:111] - node _T_990 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2242:153] - node _T_991 = not(_T_990) @[dec_tlu_ctl.scala 2242:137] - node _T_992 = or(_T_991, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2242:169] - node _T_993 = and(_T_989, _T_992) @[dec_tlu_ctl.scala 2242:134] - node _T_994 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2242:91] - node _T_995 = eq(_T_994, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2242:98] - node _T_996 = and(io.dec_csr_wen_r_mod, _T_995) @[dec_tlu_ctl.scala 2242:69] - node _T_997 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2242:120] - node _T_998 = and(_T_996, _T_997) @[dec_tlu_ctl.scala 2242:111] - node _T_999 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2242:153] - node _T_1000 = not(_T_999) @[dec_tlu_ctl.scala 2242:137] - node _T_1001 = or(_T_1000, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2242:169] - node _T_1002 = and(_T_998, _T_1001) @[dec_tlu_ctl.scala 2242:134] + mtdata1_tsel_out <= _T_943 @[Mux.scala 27:72] + node _T_944 = bits(io.mtdata1_t[0], 7, 7) @[dec_tlu_ctl.scala 2230:58] + io.trigger_pkt_any[0].select <= _T_944 @[dec_tlu_ctl.scala 2230:40] + node _T_945 = bits(io.mtdata1_t[0], 4, 4) @[dec_tlu_ctl.scala 2231:61] + io.trigger_pkt_any[0].match_pkt <= _T_945 @[dec_tlu_ctl.scala 2231:43] + node _T_946 = bits(io.mtdata1_t[0], 1, 1) @[dec_tlu_ctl.scala 2232:58] + io.trigger_pkt_any[0].store <= _T_946 @[dec_tlu_ctl.scala 2232:40] + node _T_947 = bits(io.mtdata1_t[0], 0, 0) @[dec_tlu_ctl.scala 2233:58] + io.trigger_pkt_any[0].load <= _T_947 @[dec_tlu_ctl.scala 2233:40] + node _T_948 = bits(io.mtdata1_t[0], 2, 2) @[dec_tlu_ctl.scala 2234:58] + io.trigger_pkt_any[0].execute <= _T_948 @[dec_tlu_ctl.scala 2234:40] + node _T_949 = bits(io.mtdata1_t[0], 3, 3) @[dec_tlu_ctl.scala 2235:58] + io.trigger_pkt_any[0].m <= _T_949 @[dec_tlu_ctl.scala 2235:40] + node _T_950 = bits(io.mtdata1_t[1], 7, 7) @[dec_tlu_ctl.scala 2230:58] + io.trigger_pkt_any[1].select <= _T_950 @[dec_tlu_ctl.scala 2230:40] + node _T_951 = bits(io.mtdata1_t[1], 4, 4) @[dec_tlu_ctl.scala 2231:61] + io.trigger_pkt_any[1].match_pkt <= _T_951 @[dec_tlu_ctl.scala 2231:43] + node _T_952 = bits(io.mtdata1_t[1], 1, 1) @[dec_tlu_ctl.scala 2232:58] + io.trigger_pkt_any[1].store <= _T_952 @[dec_tlu_ctl.scala 2232:40] + node _T_953 = bits(io.mtdata1_t[1], 0, 0) @[dec_tlu_ctl.scala 2233:58] + io.trigger_pkt_any[1].load <= _T_953 @[dec_tlu_ctl.scala 2233:40] + node _T_954 = bits(io.mtdata1_t[1], 2, 2) @[dec_tlu_ctl.scala 2234:58] + io.trigger_pkt_any[1].execute <= _T_954 @[dec_tlu_ctl.scala 2234:40] + node _T_955 = bits(io.mtdata1_t[1], 3, 3) @[dec_tlu_ctl.scala 2235:58] + io.trigger_pkt_any[1].m <= _T_955 @[dec_tlu_ctl.scala 2235:40] + node _T_956 = bits(io.mtdata1_t[2], 7, 7) @[dec_tlu_ctl.scala 2230:58] + io.trigger_pkt_any[2].select <= _T_956 @[dec_tlu_ctl.scala 2230:40] + node _T_957 = bits(io.mtdata1_t[2], 4, 4) @[dec_tlu_ctl.scala 2231:61] + io.trigger_pkt_any[2].match_pkt <= _T_957 @[dec_tlu_ctl.scala 2231:43] + node _T_958 = bits(io.mtdata1_t[2], 1, 1) @[dec_tlu_ctl.scala 2232:58] + io.trigger_pkt_any[2].store <= _T_958 @[dec_tlu_ctl.scala 2232:40] + node _T_959 = bits(io.mtdata1_t[2], 0, 0) @[dec_tlu_ctl.scala 2233:58] + io.trigger_pkt_any[2].load <= _T_959 @[dec_tlu_ctl.scala 2233:40] + node _T_960 = bits(io.mtdata1_t[2], 2, 2) @[dec_tlu_ctl.scala 2234:58] + io.trigger_pkt_any[2].execute <= _T_960 @[dec_tlu_ctl.scala 2234:40] + node _T_961 = bits(io.mtdata1_t[2], 3, 3) @[dec_tlu_ctl.scala 2235:58] + io.trigger_pkt_any[2].m <= _T_961 @[dec_tlu_ctl.scala 2235:40] + node _T_962 = bits(io.mtdata1_t[3], 7, 7) @[dec_tlu_ctl.scala 2230:58] + io.trigger_pkt_any[3].select <= _T_962 @[dec_tlu_ctl.scala 2230:40] + node _T_963 = bits(io.mtdata1_t[3], 4, 4) @[dec_tlu_ctl.scala 2231:61] + io.trigger_pkt_any[3].match_pkt <= _T_963 @[dec_tlu_ctl.scala 2231:43] + node _T_964 = bits(io.mtdata1_t[3], 1, 1) @[dec_tlu_ctl.scala 2232:58] + io.trigger_pkt_any[3].store <= _T_964 @[dec_tlu_ctl.scala 2232:40] + node _T_965 = bits(io.mtdata1_t[3], 0, 0) @[dec_tlu_ctl.scala 2233:58] + io.trigger_pkt_any[3].load <= _T_965 @[dec_tlu_ctl.scala 2233:40] + node _T_966 = bits(io.mtdata1_t[3], 2, 2) @[dec_tlu_ctl.scala 2234:58] + io.trigger_pkt_any[3].execute <= _T_966 @[dec_tlu_ctl.scala 2234:40] + node _T_967 = bits(io.mtdata1_t[3], 3, 3) @[dec_tlu_ctl.scala 2235:58] + io.trigger_pkt_any[3].m <= _T_967 @[dec_tlu_ctl.scala 2235:40] + node _T_968 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2242:91] + node _T_969 = eq(_T_968, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2242:98] + node _T_970 = and(io.dec_csr_wen_r_mod, _T_969) @[dec_tlu_ctl.scala 2242:69] + node _T_971 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2242:120] + node _T_972 = and(_T_970, _T_971) @[dec_tlu_ctl.scala 2242:111] + node _T_973 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2242:153] + node _T_974 = not(_T_973) @[dec_tlu_ctl.scala 2242:137] + node _T_975 = or(_T_974, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2242:169] + node _T_976 = and(_T_972, _T_975) @[dec_tlu_ctl.scala 2242:134] + node _T_977 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2242:91] + node _T_978 = eq(_T_977, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2242:98] + node _T_979 = and(io.dec_csr_wen_r_mod, _T_978) @[dec_tlu_ctl.scala 2242:69] + node _T_980 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2242:120] + node _T_981 = and(_T_979, _T_980) @[dec_tlu_ctl.scala 2242:111] + node _T_982 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2242:153] + node _T_983 = not(_T_982) @[dec_tlu_ctl.scala 2242:137] + node _T_984 = or(_T_983, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2242:169] + node _T_985 = and(_T_981, _T_984) @[dec_tlu_ctl.scala 2242:134] + node _T_986 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2242:91] + node _T_987 = eq(_T_986, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2242:98] + node _T_988 = and(io.dec_csr_wen_r_mod, _T_987) @[dec_tlu_ctl.scala 2242:69] + node _T_989 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2242:120] + node _T_990 = and(_T_988, _T_989) @[dec_tlu_ctl.scala 2242:111] + node _T_991 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2242:153] + node _T_992 = not(_T_991) @[dec_tlu_ctl.scala 2242:137] + node _T_993 = or(_T_992, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2242:169] + node _T_994 = and(_T_990, _T_993) @[dec_tlu_ctl.scala 2242:134] + node _T_995 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2242:91] + node _T_996 = eq(_T_995, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2242:98] + node _T_997 = and(io.dec_csr_wen_r_mod, _T_996) @[dec_tlu_ctl.scala 2242:69] + node _T_998 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2242:120] + node _T_999 = and(_T_997, _T_998) @[dec_tlu_ctl.scala 2242:111] + node _T_1000 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2242:153] + node _T_1001 = not(_T_1000) @[dec_tlu_ctl.scala 2242:137] + node _T_1002 = or(_T_1001, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2242:169] + node _T_1003 = and(_T_999, _T_1002) @[dec_tlu_ctl.scala 2242:134] wire wr_mtdata2_t_r : UInt<1>[4] @[dec_tlu_ctl.scala 2242:42] - wr_mtdata2_t_r[0] <= _T_975 @[dec_tlu_ctl.scala 2242:42] - wr_mtdata2_t_r[1] <= _T_984 @[dec_tlu_ctl.scala 2242:42] - wr_mtdata2_t_r[2] <= _T_993 @[dec_tlu_ctl.scala 2242:42] - wr_mtdata2_t_r[3] <= _T_1002 @[dec_tlu_ctl.scala 2242:42] - node _T_1003 = bits(wr_mtdata2_t_r[0], 0, 0) @[dec_tlu_ctl.scala 2243:84] + wr_mtdata2_t_r[0] <= _T_976 @[dec_tlu_ctl.scala 2242:42] + wr_mtdata2_t_r[1] <= _T_985 @[dec_tlu_ctl.scala 2242:42] + wr_mtdata2_t_r[2] <= _T_994 @[dec_tlu_ctl.scala 2242:42] + wr_mtdata2_t_r[3] <= _T_1003 @[dec_tlu_ctl.scala 2242:42] + node _T_1004 = bits(wr_mtdata2_t_r[0], 0, 0) @[dec_tlu_ctl.scala 2243:84] inst rvclkhdr_22 of rvclkhdr_742 @[lib.scala 368:23] rvclkhdr_22.clock <= clock rvclkhdr_22.reset <= reset rvclkhdr_22.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_22.io.en <= _T_1003 @[lib.scala 371:17] + rvclkhdr_22.io.en <= _T_1004 @[lib.scala 371:17] rvclkhdr_22.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_1004 : UInt, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_1004 <= io.dec_csr_wrdata_r @[lib.scala 374:16] - mtdata2_t[0] <= _T_1004 @[dec_tlu_ctl.scala 2243:36] - node _T_1005 = bits(wr_mtdata2_t_r[1], 0, 0) @[dec_tlu_ctl.scala 2243:84] + reg _T_1005 : UInt, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_1005 <= io.dec_csr_wrdata_r @[lib.scala 374:16] + mtdata2_t[0] <= _T_1005 @[dec_tlu_ctl.scala 2243:36] + node _T_1006 = bits(wr_mtdata2_t_r[1], 0, 0) @[dec_tlu_ctl.scala 2243:84] inst rvclkhdr_23 of rvclkhdr_743 @[lib.scala 368:23] rvclkhdr_23.clock <= clock rvclkhdr_23.reset <= reset rvclkhdr_23.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_23.io.en <= _T_1005 @[lib.scala 371:17] + rvclkhdr_23.io.en <= _T_1006 @[lib.scala 371:17] rvclkhdr_23.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_1006 : UInt, rvclkhdr_23.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_1006 <= io.dec_csr_wrdata_r @[lib.scala 374:16] - mtdata2_t[1] <= _T_1006 @[dec_tlu_ctl.scala 2243:36] - node _T_1007 = bits(wr_mtdata2_t_r[2], 0, 0) @[dec_tlu_ctl.scala 2243:84] + reg _T_1007 : UInt, rvclkhdr_23.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_1007 <= io.dec_csr_wrdata_r @[lib.scala 374:16] + mtdata2_t[1] <= _T_1007 @[dec_tlu_ctl.scala 2243:36] + node _T_1008 = bits(wr_mtdata2_t_r[2], 0, 0) @[dec_tlu_ctl.scala 2243:84] inst rvclkhdr_24 of rvclkhdr_744 @[lib.scala 368:23] rvclkhdr_24.clock <= clock rvclkhdr_24.reset <= reset rvclkhdr_24.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_24.io.en <= _T_1007 @[lib.scala 371:17] + rvclkhdr_24.io.en <= _T_1008 @[lib.scala 371:17] rvclkhdr_24.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_1008 : UInt, rvclkhdr_24.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_1008 <= io.dec_csr_wrdata_r @[lib.scala 374:16] - mtdata2_t[2] <= _T_1008 @[dec_tlu_ctl.scala 2243:36] - node _T_1009 = bits(wr_mtdata2_t_r[3], 0, 0) @[dec_tlu_ctl.scala 2243:84] + reg _T_1009 : UInt, rvclkhdr_24.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_1009 <= io.dec_csr_wrdata_r @[lib.scala 374:16] + mtdata2_t[2] <= _T_1009 @[dec_tlu_ctl.scala 2243:36] + node _T_1010 = bits(wr_mtdata2_t_r[3], 0, 0) @[dec_tlu_ctl.scala 2243:84] inst rvclkhdr_25 of rvclkhdr_745 @[lib.scala 368:23] rvclkhdr_25.clock <= clock rvclkhdr_25.reset <= reset rvclkhdr_25.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_25.io.en <= _T_1009 @[lib.scala 371:17] + rvclkhdr_25.io.en <= _T_1010 @[lib.scala 371:17] rvclkhdr_25.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_1010 : UInt, rvclkhdr_25.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_1010 <= io.dec_csr_wrdata_r @[lib.scala 374:16] - mtdata2_t[3] <= _T_1010 @[dec_tlu_ctl.scala 2243:36] - node _T_1011 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2247:57] - node _T_1012 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2247:57] - node _T_1013 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2247:57] - node _T_1014 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2247:57] - node _T_1015 = mux(_T_1011, mtdata2_t[0], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1016 = mux(_T_1012, mtdata2_t[1], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1017 = mux(_T_1013, mtdata2_t[2], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1018 = mux(_T_1014, mtdata2_t[3], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1019 = or(_T_1015, _T_1016) @[Mux.scala 27:72] - node _T_1020 = or(_T_1019, _T_1017) @[Mux.scala 27:72] + reg _T_1011 : UInt, rvclkhdr_25.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_1011 <= io.dec_csr_wrdata_r @[lib.scala 374:16] + mtdata2_t[3] <= _T_1011 @[dec_tlu_ctl.scala 2243:36] + node _T_1012 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2247:57] + node _T_1013 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2247:57] + node _T_1014 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2247:57] + node _T_1015 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2247:57] + node _T_1016 = mux(_T_1012, mtdata2_t[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1017 = mux(_T_1013, mtdata2_t[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1018 = mux(_T_1014, mtdata2_t[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1019 = mux(_T_1015, mtdata2_t[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1020 = or(_T_1016, _T_1017) @[Mux.scala 27:72] node _T_1021 = or(_T_1020, _T_1018) @[Mux.scala 27:72] + node _T_1022 = or(_T_1021, _T_1019) @[Mux.scala 27:72] wire mtdata2_tsel_out : UInt<32> @[Mux.scala 27:72] - mtdata2_tsel_out <= _T_1021 @[Mux.scala 27:72] + mtdata2_tsel_out <= _T_1022 @[Mux.scala 27:72] io.trigger_pkt_any[0].tdata2 <= mtdata2_t[0] @[dec_tlu_ctl.scala 2248:51] io.trigger_pkt_any[1].tdata2 <= mtdata2_t[1] @[dec_tlu_ctl.scala 2248:51] io.trigger_pkt_any[2].tdata2 <= mtdata2_t[2] @[dec_tlu_ctl.scala 2248:51] @@ -74402,239 +74411,238 @@ circuit quasar_wrapper : mhpme_vec[1] <= mhpme4 @[dec_tlu_ctl.scala 2259:15] mhpme_vec[2] <= mhpme5 @[dec_tlu_ctl.scala 2260:15] mhpme_vec[3] <= mhpme6 @[dec_tlu_ctl.scala 2261:15] - node _T_1022 = bits(io.tlu_i0_commit_cmt, 0, 0) @[Bitwise.scala 72:15] - node _T_1023 = mux(_T_1022, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node pmu_i0_itype_qual = and(io.dec_tlu_packet_r.pmu_i0_itype, _T_1023) @[dec_tlu_ctl.scala 2267:59] + node _T_1023 = bits(io.tlu_i0_commit_cmt, 0, 0) @[Bitwise.scala 72:15] + node _T_1024 = mux(_T_1023, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node pmu_i0_itype_qual = and(io.dec_tlu_packet_r.pmu_i0_itype, _T_1024) @[dec_tlu_ctl.scala 2267:59] wire mhpmc_inc_r : UInt<1>[4] @[dec_tlu_ctl.scala 2268:24] wire mhpmc_inc_r_d1 : UInt<1>[4] @[dec_tlu_ctl.scala 2269:27] - node _T_1024 = bits(mcountinhibit, 3, 3) @[dec_tlu_ctl.scala 2273:38] - node _T_1025 = not(_T_1024) @[dec_tlu_ctl.scala 2273:24] - node _T_1026 = eq(mhpme_vec[0], UInt<1>("h01")) @[dec_tlu_ctl.scala 2274:34] - node _T_1027 = bits(_T_1026, 0, 0) @[dec_tlu_ctl.scala 2274:62] - node _T_1028 = eq(mhpme_vec[0], UInt<2>("h02")) @[dec_tlu_ctl.scala 2275:34] - node _T_1029 = bits(_T_1028, 0, 0) @[dec_tlu_ctl.scala 2275:62] - node _T_1030 = eq(mhpme_vec[0], UInt<2>("h03")) @[dec_tlu_ctl.scala 2276:34] - node _T_1031 = bits(_T_1030, 0, 0) @[dec_tlu_ctl.scala 2276:62] - node _T_1032 = eq(mhpme_vec[0], UInt<3>("h04")) @[dec_tlu_ctl.scala 2277:34] - node _T_1033 = bits(_T_1032, 0, 0) @[dec_tlu_ctl.scala 2277:62] - node _T_1034 = not(io.illegal_r) @[dec_tlu_ctl.scala 2277:96] - node _T_1035 = and(io.tlu_i0_commit_cmt, _T_1034) @[dec_tlu_ctl.scala 2277:94] - node _T_1036 = eq(mhpme_vec[0], UInt<3>("h05")) @[dec_tlu_ctl.scala 2278:34] - node _T_1037 = bits(_T_1036, 0, 0) @[dec_tlu_ctl.scala 2278:62] - node _T_1038 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2278:96] - node _T_1039 = and(io.tlu_i0_commit_cmt, _T_1038) @[dec_tlu_ctl.scala 2278:94] - node _T_1040 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:117] - node _T_1041 = and(_T_1039, _T_1040) @[dec_tlu_ctl.scala 2278:115] - node _T_1042 = eq(mhpme_vec[0], UInt<3>("h06")) @[dec_tlu_ctl.scala 2279:34] - node _T_1043 = bits(_T_1042, 0, 0) @[dec_tlu_ctl.scala 2279:62] - node _T_1044 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2279:94] - node _T_1045 = not(io.illegal_r) @[dec_tlu_ctl.scala 2279:117] - node _T_1046 = and(_T_1044, _T_1045) @[dec_tlu_ctl.scala 2279:115] - node _T_1047 = eq(mhpme_vec[0], UInt<3>("h07")) @[dec_tlu_ctl.scala 2280:34] - node _T_1048 = bits(_T_1047, 0, 0) @[dec_tlu_ctl.scala 2280:62] - node _T_1049 = eq(mhpme_vec[0], UInt<4>("h08")) @[dec_tlu_ctl.scala 2281:34] - node _T_1050 = bits(_T_1049, 0, 0) @[dec_tlu_ctl.scala 2281:62] - node _T_1051 = eq(mhpme_vec[0], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2282:34] - node _T_1052 = bits(_T_1051, 0, 0) @[dec_tlu_ctl.scala 2282:62] - node _T_1053 = eq(mhpme_vec[0], UInt<4>("h09")) @[dec_tlu_ctl.scala 2283:34] - node _T_1054 = bits(_T_1053, 0, 0) @[dec_tlu_ctl.scala 2283:62] - node _T_1055 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2283:91] - node _T_1056 = eq(mhpme_vec[0], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2284:34] - node _T_1057 = bits(_T_1056, 0, 0) @[dec_tlu_ctl.scala 2284:62] - node _T_1058 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2284:105] - node _T_1059 = eq(mhpme_vec[0], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2285:34] - node _T_1060 = bits(_T_1059, 0, 0) @[dec_tlu_ctl.scala 2285:62] - node _T_1061 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2285:91] - node _T_1062 = eq(mhpme_vec[0], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2286:34] - node _T_1063 = bits(_T_1062, 0, 0) @[dec_tlu_ctl.scala 2286:62] - node _T_1064 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2286:91] - node _T_1065 = eq(mhpme_vec[0], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2287:34] - node _T_1066 = bits(_T_1065, 0, 0) @[dec_tlu_ctl.scala 2287:62] - node _T_1067 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2287:91] - node _T_1068 = and(_T_1067, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2287:100] - node _T_1069 = eq(mhpme_vec[0], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2288:34] - node _T_1070 = bits(_T_1069, 0, 0) @[dec_tlu_ctl.scala 2288:62] - node _T_1071 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2288:91] - node _T_1072 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2288:142] - node _T_1073 = and(_T_1071, _T_1072) @[dec_tlu_ctl.scala 2288:101] - node _T_1074 = eq(mhpme_vec[0], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2289:34] - node _T_1075 = bits(_T_1074, 0, 0) @[dec_tlu_ctl.scala 2289:59] - node _T_1076 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2289:89] - node _T_1077 = eq(mhpme_vec[0], UInt<5>("h010")) @[dec_tlu_ctl.scala 2290:34] - node _T_1078 = bits(_T_1077, 0, 0) @[dec_tlu_ctl.scala 2290:59] - node _T_1079 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2290:89] - node _T_1080 = eq(mhpme_vec[0], UInt<5>("h012")) @[dec_tlu_ctl.scala 2291:34] - node _T_1081 = bits(_T_1080, 0, 0) @[dec_tlu_ctl.scala 2291:59] - node _T_1082 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2291:89] - node _T_1083 = eq(mhpme_vec[0], UInt<5>("h011")) @[dec_tlu_ctl.scala 2292:34] - node _T_1084 = bits(_T_1083, 0, 0) @[dec_tlu_ctl.scala 2292:59] - node _T_1085 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2292:89] - node _T_1086 = eq(mhpme_vec[0], UInt<5>("h013")) @[dec_tlu_ctl.scala 2293:34] - node _T_1087 = bits(_T_1086, 0, 0) @[dec_tlu_ctl.scala 2293:59] - node _T_1088 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2293:89] - node _T_1089 = eq(mhpme_vec[0], UInt<5>("h014")) @[dec_tlu_ctl.scala 2294:34] - node _T_1090 = bits(_T_1089, 0, 0) @[dec_tlu_ctl.scala 2294:59] - node _T_1091 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2294:89] - node _T_1092 = eq(mhpme_vec[0], UInt<5>("h015")) @[dec_tlu_ctl.scala 2295:34] - node _T_1093 = bits(_T_1092, 0, 0) @[dec_tlu_ctl.scala 2295:59] - node _T_1094 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2295:89] - node _T_1095 = eq(mhpme_vec[0], UInt<5>("h016")) @[dec_tlu_ctl.scala 2296:34] - node _T_1096 = bits(_T_1095, 0, 0) @[dec_tlu_ctl.scala 2296:59] - node _T_1097 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2296:89] - node _T_1098 = eq(mhpme_vec[0], UInt<5>("h017")) @[dec_tlu_ctl.scala 2297:34] - node _T_1099 = bits(_T_1098, 0, 0) @[dec_tlu_ctl.scala 2297:59] - node _T_1100 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2297:89] - node _T_1101 = eq(mhpme_vec[0], UInt<5>("h018")) @[dec_tlu_ctl.scala 2298:34] - node _T_1102 = bits(_T_1101, 0, 0) @[dec_tlu_ctl.scala 2298:59] - node _T_1103 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2298:89] - node _T_1104 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2298:122] - node _T_1105 = or(_T_1103, _T_1104) @[dec_tlu_ctl.scala 2298:101] - node _T_1106 = eq(mhpme_vec[0], UInt<5>("h019")) @[dec_tlu_ctl.scala 2299:34] - node _T_1107 = bits(_T_1106, 0, 0) @[dec_tlu_ctl.scala 2299:62] - node _T_1108 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2299:95] - node _T_1109 = eq(mhpme_vec[0], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2300:34] - node _T_1110 = bits(_T_1109, 0, 0) @[dec_tlu_ctl.scala 2300:62] - node _T_1111 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:97] - node _T_1112 = eq(mhpme_vec[0], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2301:34] - node _T_1113 = bits(_T_1112, 0, 0) @[dec_tlu_ctl.scala 2301:62] - node _T_1114 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2301:110] - node _T_1115 = eq(mhpme_vec[0], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2302:34] - node _T_1116 = bits(_T_1115, 0, 0) @[dec_tlu_ctl.scala 2302:62] - node _T_1117 = eq(mhpme_vec[0], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2303:34] - node _T_1118 = bits(_T_1117, 0, 0) @[dec_tlu_ctl.scala 2303:62] - node _T_1119 = eq(mhpme_vec[0], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2304:34] - node _T_1120 = bits(_T_1119, 0, 0) @[dec_tlu_ctl.scala 2304:62] - node _T_1121 = eq(mhpme_vec[0], UInt<6>("h020")) @[dec_tlu_ctl.scala 2305:34] - node _T_1122 = bits(_T_1121, 0, 0) @[dec_tlu_ctl.scala 2305:62] - node _T_1123 = eq(mhpme_vec[0], UInt<6>("h022")) @[dec_tlu_ctl.scala 2306:34] - node _T_1124 = bits(_T_1123, 0, 0) @[dec_tlu_ctl.scala 2306:62] - node _T_1125 = eq(mhpme_vec[0], UInt<6>("h023")) @[dec_tlu_ctl.scala 2307:34] - node _T_1126 = bits(_T_1125, 0, 0) @[dec_tlu_ctl.scala 2307:62] - node _T_1127 = eq(mhpme_vec[0], UInt<6>("h024")) @[dec_tlu_ctl.scala 2308:34] - node _T_1128 = bits(_T_1127, 0, 0) @[dec_tlu_ctl.scala 2308:62] - node _T_1129 = eq(mhpme_vec[0], UInt<6>("h025")) @[dec_tlu_ctl.scala 2309:34] - node _T_1130 = bits(_T_1129, 0, 0) @[dec_tlu_ctl.scala 2309:62] - node _T_1131 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2309:98] - node _T_1132 = or(_T_1131, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2309:120] - node _T_1133 = eq(mhpme_vec[0], UInt<6>("h026")) @[dec_tlu_ctl.scala 2310:34] - node _T_1134 = bits(_T_1133, 0, 0) @[dec_tlu_ctl.scala 2310:62] - node _T_1135 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2310:92] - node _T_1136 = or(_T_1135, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2310:117] - node _T_1137 = eq(mhpme_vec[0], UInt<6>("h027")) @[dec_tlu_ctl.scala 2311:34] - node _T_1138 = bits(_T_1137, 0, 0) @[dec_tlu_ctl.scala 2311:62] - node _T_1139 = eq(mhpme_vec[0], UInt<6>("h028")) @[dec_tlu_ctl.scala 2312:34] - node _T_1140 = bits(_T_1139, 0, 0) @[dec_tlu_ctl.scala 2312:62] - node _T_1141 = eq(mhpme_vec[0], UInt<6>("h029")) @[dec_tlu_ctl.scala 2313:34] - node _T_1142 = bits(_T_1141, 0, 0) @[dec_tlu_ctl.scala 2313:62] - node _T_1143 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2313:97] - node _T_1144 = and(_T_1143, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2313:129] - node _T_1145 = eq(mhpme_vec[0], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2314:34] - node _T_1146 = bits(_T_1145, 0, 0) @[dec_tlu_ctl.scala 2314:62] - node _T_1147 = eq(mhpme_vec[0], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2315:34] - node _T_1148 = bits(_T_1147, 0, 0) @[dec_tlu_ctl.scala 2315:62] - node _T_1149 = eq(mhpme_vec[0], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2316:34] - node _T_1150 = bits(_T_1149, 0, 0) @[dec_tlu_ctl.scala 2316:62] - node _T_1151 = eq(mhpme_vec[0], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2317:34] - node _T_1152 = bits(_T_1151, 0, 0) @[dec_tlu_ctl.scala 2317:62] - node _T_1153 = eq(mhpme_vec[0], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2318:34] - node _T_1154 = bits(_T_1153, 0, 0) @[dec_tlu_ctl.scala 2318:62] - node _T_1155 = eq(mhpme_vec[0], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2319:34] - node _T_1156 = bits(_T_1155, 0, 0) @[dec_tlu_ctl.scala 2319:62] - node _T_1157 = eq(mhpme_vec[0], UInt<6>("h030")) @[dec_tlu_ctl.scala 2320:34] - node _T_1158 = bits(_T_1157, 0, 0) @[dec_tlu_ctl.scala 2320:62] - node _T_1159 = eq(mhpme_vec[0], UInt<6>("h031")) @[dec_tlu_ctl.scala 2321:34] - node _T_1160 = bits(_T_1159, 0, 0) @[dec_tlu_ctl.scala 2321:62] - node _T_1161 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2321:84] - node _T_1162 = bits(_T_1161, 0, 0) @[dec_tlu_ctl.scala 2321:84] - node _T_1163 = not(_T_1162) @[dec_tlu_ctl.scala 2321:73] - node _T_1164 = eq(mhpme_vec[0], UInt<6>("h032")) @[dec_tlu_ctl.scala 2322:34] - node _T_1165 = bits(_T_1164, 0, 0) @[dec_tlu_ctl.scala 2322:62] - node _T_1166 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2322:84] - node _T_1167 = bits(_T_1166, 0, 0) @[dec_tlu_ctl.scala 2322:84] - node _T_1168 = not(_T_1167) @[dec_tlu_ctl.scala 2322:73] - node _T_1169 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2322:107] - node _T_1170 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2322:118] - node _T_1171 = and(_T_1169, _T_1170) @[dec_tlu_ctl.scala 2322:113] - node _T_1172 = orr(_T_1171) @[dec_tlu_ctl.scala 2322:125] - node _T_1173 = and(_T_1168, _T_1172) @[dec_tlu_ctl.scala 2322:98] - node _T_1174 = eq(mhpme_vec[0], UInt<6>("h036")) @[dec_tlu_ctl.scala 2323:34] - node _T_1175 = bits(_T_1174, 0, 0) @[dec_tlu_ctl.scala 2323:62] - node _T_1176 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2323:91] - node _T_1177 = eq(mhpme_vec[0], UInt<6>("h037")) @[dec_tlu_ctl.scala 2324:34] - node _T_1178 = bits(_T_1177, 0, 0) @[dec_tlu_ctl.scala 2324:62] - node _T_1179 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2324:94] - node _T_1180 = eq(mhpme_vec[0], UInt<6>("h038")) @[dec_tlu_ctl.scala 2325:34] - node _T_1181 = bits(_T_1180, 0, 0) @[dec_tlu_ctl.scala 2325:62] - node _T_1182 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2325:94] - node _T_1183 = eq(mhpme_vec[0], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2327:34] - node _T_1184 = bits(_T_1183, 0, 0) @[dec_tlu_ctl.scala 2327:62] - node _T_1185 = eq(mhpme_vec[0], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2328:34] - node _T_1186 = bits(_T_1185, 0, 0) @[dec_tlu_ctl.scala 2328:62] - node _T_1187 = eq(mhpme_vec[0], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2329:34] - node _T_1188 = bits(_T_1187, 0, 0) @[dec_tlu_ctl.scala 2329:62] - node _T_1189 = eq(mhpme_vec[0], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2330:34] - node _T_1190 = bits(_T_1189, 0, 0) @[dec_tlu_ctl.scala 2330:62] - node _T_1191 = eq(mhpme_vec[0], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2331:34] - node _T_1192 = bits(_T_1191, 0, 0) @[dec_tlu_ctl.scala 2331:62] - node _T_1193 = mux(_T_1027, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1194 = mux(_T_1029, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1195 = mux(_T_1031, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1196 = mux(_T_1033, _T_1035, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1197 = mux(_T_1037, _T_1041, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1198 = mux(_T_1043, _T_1046, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1199 = mux(_T_1048, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1200 = mux(_T_1050, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1201 = mux(_T_1052, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1202 = mux(_T_1054, _T_1055, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1203 = mux(_T_1057, _T_1058, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1204 = mux(_T_1060, _T_1061, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1205 = mux(_T_1063, _T_1064, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1206 = mux(_T_1066, _T_1068, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1207 = mux(_T_1070, _T_1073, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1208 = mux(_T_1075, _T_1076, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1209 = mux(_T_1078, _T_1079, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1210 = mux(_T_1081, _T_1082, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1211 = mux(_T_1084, _T_1085, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1212 = mux(_T_1087, _T_1088, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1213 = mux(_T_1090, _T_1091, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1214 = mux(_T_1093, _T_1094, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1215 = mux(_T_1096, _T_1097, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1216 = mux(_T_1099, _T_1100, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1217 = mux(_T_1102, _T_1105, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1218 = mux(_T_1107, _T_1108, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1219 = mux(_T_1110, _T_1111, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1220 = mux(_T_1113, _T_1114, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1221 = mux(_T_1116, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1222 = mux(_T_1118, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1223 = mux(_T_1120, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1224 = mux(_T_1122, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1225 = mux(_T_1124, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1226 = mux(_T_1126, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1227 = mux(_T_1128, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1228 = mux(_T_1130, _T_1132, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1229 = mux(_T_1134, _T_1136, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1230 = mux(_T_1138, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1231 = mux(_T_1140, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1232 = mux(_T_1142, _T_1144, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1233 = mux(_T_1146, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1234 = mux(_T_1148, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1235 = mux(_T_1150, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1236 = mux(_T_1152, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1237 = mux(_T_1154, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1238 = mux(_T_1156, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1239 = mux(_T_1158, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1240 = mux(_T_1160, _T_1163, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1241 = mux(_T_1165, _T_1173, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1242 = mux(_T_1175, _T_1176, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1243 = mux(_T_1178, _T_1179, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1244 = mux(_T_1181, _T_1182, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1245 = mux(_T_1184, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1246 = mux(_T_1186, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1247 = mux(_T_1188, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1248 = mux(_T_1190, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1249 = mux(_T_1192, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1250 = or(_T_1193, _T_1194) @[Mux.scala 27:72] - node _T_1251 = or(_T_1250, _T_1195) @[Mux.scala 27:72] + node _T_1025 = bits(mcountinhibit, 3, 3) @[dec_tlu_ctl.scala 2273:38] + node _T_1026 = not(_T_1025) @[dec_tlu_ctl.scala 2273:24] + node _T_1027 = eq(mhpme_vec[0], UInt<1>("h01")) @[dec_tlu_ctl.scala 2274:34] + node _T_1028 = bits(_T_1027, 0, 0) @[dec_tlu_ctl.scala 2274:62] + node _T_1029 = eq(mhpme_vec[0], UInt<2>("h02")) @[dec_tlu_ctl.scala 2275:34] + node _T_1030 = bits(_T_1029, 0, 0) @[dec_tlu_ctl.scala 2275:62] + node _T_1031 = eq(mhpme_vec[0], UInt<2>("h03")) @[dec_tlu_ctl.scala 2276:34] + node _T_1032 = bits(_T_1031, 0, 0) @[dec_tlu_ctl.scala 2276:62] + node _T_1033 = eq(mhpme_vec[0], UInt<3>("h04")) @[dec_tlu_ctl.scala 2277:34] + node _T_1034 = bits(_T_1033, 0, 0) @[dec_tlu_ctl.scala 2277:62] + node _T_1035 = not(io.illegal_r) @[dec_tlu_ctl.scala 2277:96] + node _T_1036 = and(io.tlu_i0_commit_cmt, _T_1035) @[dec_tlu_ctl.scala 2277:94] + node _T_1037 = eq(mhpme_vec[0], UInt<3>("h05")) @[dec_tlu_ctl.scala 2278:34] + node _T_1038 = bits(_T_1037, 0, 0) @[dec_tlu_ctl.scala 2278:62] + node _T_1039 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2278:96] + node _T_1040 = and(io.tlu_i0_commit_cmt, _T_1039) @[dec_tlu_ctl.scala 2278:94] + node _T_1041 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:117] + node _T_1042 = and(_T_1040, _T_1041) @[dec_tlu_ctl.scala 2278:115] + node _T_1043 = eq(mhpme_vec[0], UInt<3>("h06")) @[dec_tlu_ctl.scala 2279:34] + node _T_1044 = bits(_T_1043, 0, 0) @[dec_tlu_ctl.scala 2279:62] + node _T_1045 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2279:94] + node _T_1046 = not(io.illegal_r) @[dec_tlu_ctl.scala 2279:117] + node _T_1047 = and(_T_1045, _T_1046) @[dec_tlu_ctl.scala 2279:115] + node _T_1048 = eq(mhpme_vec[0], UInt<3>("h07")) @[dec_tlu_ctl.scala 2280:34] + node _T_1049 = bits(_T_1048, 0, 0) @[dec_tlu_ctl.scala 2280:62] + node _T_1050 = eq(mhpme_vec[0], UInt<4>("h08")) @[dec_tlu_ctl.scala 2281:34] + node _T_1051 = bits(_T_1050, 0, 0) @[dec_tlu_ctl.scala 2281:62] + node _T_1052 = eq(mhpme_vec[0], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2282:34] + node _T_1053 = bits(_T_1052, 0, 0) @[dec_tlu_ctl.scala 2282:62] + node _T_1054 = eq(mhpme_vec[0], UInt<4>("h09")) @[dec_tlu_ctl.scala 2283:34] + node _T_1055 = bits(_T_1054, 0, 0) @[dec_tlu_ctl.scala 2283:62] + node _T_1056 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2283:91] + node _T_1057 = eq(mhpme_vec[0], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2284:34] + node _T_1058 = bits(_T_1057, 0, 0) @[dec_tlu_ctl.scala 2284:62] + node _T_1059 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2284:105] + node _T_1060 = eq(mhpme_vec[0], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2285:34] + node _T_1061 = bits(_T_1060, 0, 0) @[dec_tlu_ctl.scala 2285:62] + node _T_1062 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2285:91] + node _T_1063 = eq(mhpme_vec[0], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2286:34] + node _T_1064 = bits(_T_1063, 0, 0) @[dec_tlu_ctl.scala 2286:62] + node _T_1065 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2286:91] + node _T_1066 = eq(mhpme_vec[0], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2287:34] + node _T_1067 = bits(_T_1066, 0, 0) @[dec_tlu_ctl.scala 2287:62] + node _T_1068 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2287:91] + node _T_1069 = and(_T_1068, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2287:100] + node _T_1070 = eq(mhpme_vec[0], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2288:34] + node _T_1071 = bits(_T_1070, 0, 0) @[dec_tlu_ctl.scala 2288:62] + node _T_1072 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2288:91] + node _T_1073 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2288:142] + node _T_1074 = and(_T_1072, _T_1073) @[dec_tlu_ctl.scala 2288:101] + node _T_1075 = eq(mhpme_vec[0], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2289:34] + node _T_1076 = bits(_T_1075, 0, 0) @[dec_tlu_ctl.scala 2289:59] + node _T_1077 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2289:89] + node _T_1078 = eq(mhpme_vec[0], UInt<5>("h010")) @[dec_tlu_ctl.scala 2290:34] + node _T_1079 = bits(_T_1078, 0, 0) @[dec_tlu_ctl.scala 2290:59] + node _T_1080 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2290:89] + node _T_1081 = eq(mhpme_vec[0], UInt<5>("h012")) @[dec_tlu_ctl.scala 2291:34] + node _T_1082 = bits(_T_1081, 0, 0) @[dec_tlu_ctl.scala 2291:59] + node _T_1083 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2291:89] + node _T_1084 = eq(mhpme_vec[0], UInt<5>("h011")) @[dec_tlu_ctl.scala 2292:34] + node _T_1085 = bits(_T_1084, 0, 0) @[dec_tlu_ctl.scala 2292:59] + node _T_1086 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2292:89] + node _T_1087 = eq(mhpme_vec[0], UInt<5>("h013")) @[dec_tlu_ctl.scala 2293:34] + node _T_1088 = bits(_T_1087, 0, 0) @[dec_tlu_ctl.scala 2293:59] + node _T_1089 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2293:89] + node _T_1090 = eq(mhpme_vec[0], UInt<5>("h014")) @[dec_tlu_ctl.scala 2294:34] + node _T_1091 = bits(_T_1090, 0, 0) @[dec_tlu_ctl.scala 2294:59] + node _T_1092 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2294:89] + node _T_1093 = eq(mhpme_vec[0], UInt<5>("h015")) @[dec_tlu_ctl.scala 2295:34] + node _T_1094 = bits(_T_1093, 0, 0) @[dec_tlu_ctl.scala 2295:59] + node _T_1095 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2295:89] + node _T_1096 = eq(mhpme_vec[0], UInt<5>("h016")) @[dec_tlu_ctl.scala 2296:34] + node _T_1097 = bits(_T_1096, 0, 0) @[dec_tlu_ctl.scala 2296:59] + node _T_1098 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2296:89] + node _T_1099 = eq(mhpme_vec[0], UInt<5>("h017")) @[dec_tlu_ctl.scala 2297:34] + node _T_1100 = bits(_T_1099, 0, 0) @[dec_tlu_ctl.scala 2297:59] + node _T_1101 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2297:89] + node _T_1102 = eq(mhpme_vec[0], UInt<5>("h018")) @[dec_tlu_ctl.scala 2298:34] + node _T_1103 = bits(_T_1102, 0, 0) @[dec_tlu_ctl.scala 2298:59] + node _T_1104 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2298:89] + node _T_1105 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2298:122] + node _T_1106 = or(_T_1104, _T_1105) @[dec_tlu_ctl.scala 2298:101] + node _T_1107 = eq(mhpme_vec[0], UInt<5>("h019")) @[dec_tlu_ctl.scala 2299:34] + node _T_1108 = bits(_T_1107, 0, 0) @[dec_tlu_ctl.scala 2299:62] + node _T_1109 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2299:95] + node _T_1110 = eq(mhpme_vec[0], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2300:34] + node _T_1111 = bits(_T_1110, 0, 0) @[dec_tlu_ctl.scala 2300:62] + node _T_1112 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:97] + node _T_1113 = eq(mhpme_vec[0], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2301:34] + node _T_1114 = bits(_T_1113, 0, 0) @[dec_tlu_ctl.scala 2301:62] + node _T_1115 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2301:110] + node _T_1116 = eq(mhpme_vec[0], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2302:34] + node _T_1117 = bits(_T_1116, 0, 0) @[dec_tlu_ctl.scala 2302:62] + node _T_1118 = eq(mhpme_vec[0], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2303:34] + node _T_1119 = bits(_T_1118, 0, 0) @[dec_tlu_ctl.scala 2303:62] + node _T_1120 = eq(mhpme_vec[0], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2304:34] + node _T_1121 = bits(_T_1120, 0, 0) @[dec_tlu_ctl.scala 2304:62] + node _T_1122 = eq(mhpme_vec[0], UInt<6>("h020")) @[dec_tlu_ctl.scala 2305:34] + node _T_1123 = bits(_T_1122, 0, 0) @[dec_tlu_ctl.scala 2305:62] + node _T_1124 = eq(mhpme_vec[0], UInt<6>("h022")) @[dec_tlu_ctl.scala 2306:34] + node _T_1125 = bits(_T_1124, 0, 0) @[dec_tlu_ctl.scala 2306:62] + node _T_1126 = eq(mhpme_vec[0], UInt<6>("h023")) @[dec_tlu_ctl.scala 2307:34] + node _T_1127 = bits(_T_1126, 0, 0) @[dec_tlu_ctl.scala 2307:62] + node _T_1128 = eq(mhpme_vec[0], UInt<6>("h024")) @[dec_tlu_ctl.scala 2308:34] + node _T_1129 = bits(_T_1128, 0, 0) @[dec_tlu_ctl.scala 2308:62] + node _T_1130 = eq(mhpme_vec[0], UInt<6>("h025")) @[dec_tlu_ctl.scala 2309:34] + node _T_1131 = bits(_T_1130, 0, 0) @[dec_tlu_ctl.scala 2309:62] + node _T_1132 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2309:98] + node _T_1133 = or(_T_1132, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2309:120] + node _T_1134 = eq(mhpme_vec[0], UInt<6>("h026")) @[dec_tlu_ctl.scala 2310:34] + node _T_1135 = bits(_T_1134, 0, 0) @[dec_tlu_ctl.scala 2310:62] + node _T_1136 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2310:92] + node _T_1137 = or(_T_1136, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2310:117] + node _T_1138 = eq(mhpme_vec[0], UInt<6>("h027")) @[dec_tlu_ctl.scala 2311:34] + node _T_1139 = bits(_T_1138, 0, 0) @[dec_tlu_ctl.scala 2311:62] + node _T_1140 = eq(mhpme_vec[0], UInt<6>("h028")) @[dec_tlu_ctl.scala 2312:34] + node _T_1141 = bits(_T_1140, 0, 0) @[dec_tlu_ctl.scala 2312:62] + node _T_1142 = eq(mhpme_vec[0], UInt<6>("h029")) @[dec_tlu_ctl.scala 2313:34] + node _T_1143 = bits(_T_1142, 0, 0) @[dec_tlu_ctl.scala 2313:62] + node _T_1144 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2313:97] + node _T_1145 = and(_T_1144, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2313:129] + node _T_1146 = eq(mhpme_vec[0], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2314:34] + node _T_1147 = bits(_T_1146, 0, 0) @[dec_tlu_ctl.scala 2314:62] + node _T_1148 = eq(mhpme_vec[0], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2315:34] + node _T_1149 = bits(_T_1148, 0, 0) @[dec_tlu_ctl.scala 2315:62] + node _T_1150 = eq(mhpme_vec[0], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2316:34] + node _T_1151 = bits(_T_1150, 0, 0) @[dec_tlu_ctl.scala 2316:62] + node _T_1152 = eq(mhpme_vec[0], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2317:34] + node _T_1153 = bits(_T_1152, 0, 0) @[dec_tlu_ctl.scala 2317:62] + node _T_1154 = eq(mhpme_vec[0], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2318:34] + node _T_1155 = bits(_T_1154, 0, 0) @[dec_tlu_ctl.scala 2318:62] + node _T_1156 = eq(mhpme_vec[0], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2319:34] + node _T_1157 = bits(_T_1156, 0, 0) @[dec_tlu_ctl.scala 2319:62] + node _T_1158 = eq(mhpme_vec[0], UInt<6>("h030")) @[dec_tlu_ctl.scala 2320:34] + node _T_1159 = bits(_T_1158, 0, 0) @[dec_tlu_ctl.scala 2320:62] + node _T_1160 = eq(mhpme_vec[0], UInt<6>("h031")) @[dec_tlu_ctl.scala 2321:34] + node _T_1161 = bits(_T_1160, 0, 0) @[dec_tlu_ctl.scala 2321:62] + node _T_1162 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2321:84] + node _T_1163 = bits(_T_1162, 0, 0) @[dec_tlu_ctl.scala 2321:84] + node _T_1164 = not(_T_1163) @[dec_tlu_ctl.scala 2321:73] + node _T_1165 = eq(mhpme_vec[0], UInt<6>("h032")) @[dec_tlu_ctl.scala 2322:34] + node _T_1166 = bits(_T_1165, 0, 0) @[dec_tlu_ctl.scala 2322:62] + node _T_1167 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2322:84] + node _T_1168 = bits(_T_1167, 0, 0) @[dec_tlu_ctl.scala 2322:84] + node _T_1169 = not(_T_1168) @[dec_tlu_ctl.scala 2322:73] + node _T_1170 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2322:107] + node _T_1171 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2322:118] + node _T_1172 = and(_T_1170, _T_1171) @[dec_tlu_ctl.scala 2322:113] + node _T_1173 = orr(_T_1172) @[dec_tlu_ctl.scala 2322:125] + node _T_1174 = and(_T_1169, _T_1173) @[dec_tlu_ctl.scala 2322:98] + node _T_1175 = eq(mhpme_vec[0], UInt<6>("h036")) @[dec_tlu_ctl.scala 2323:34] + node _T_1176 = bits(_T_1175, 0, 0) @[dec_tlu_ctl.scala 2323:62] + node _T_1177 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2323:91] + node _T_1178 = eq(mhpme_vec[0], UInt<6>("h037")) @[dec_tlu_ctl.scala 2324:34] + node _T_1179 = bits(_T_1178, 0, 0) @[dec_tlu_ctl.scala 2324:62] + node _T_1180 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2324:94] + node _T_1181 = eq(mhpme_vec[0], UInt<6>("h038")) @[dec_tlu_ctl.scala 2325:34] + node _T_1182 = bits(_T_1181, 0, 0) @[dec_tlu_ctl.scala 2325:62] + node _T_1183 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2325:94] + node _T_1184 = eq(mhpme_vec[0], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2327:34] + node _T_1185 = bits(_T_1184, 0, 0) @[dec_tlu_ctl.scala 2327:62] + node _T_1186 = eq(mhpme_vec[0], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2328:34] + node _T_1187 = bits(_T_1186, 0, 0) @[dec_tlu_ctl.scala 2328:62] + node _T_1188 = eq(mhpme_vec[0], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2329:34] + node _T_1189 = bits(_T_1188, 0, 0) @[dec_tlu_ctl.scala 2329:62] + node _T_1190 = eq(mhpme_vec[0], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2330:34] + node _T_1191 = bits(_T_1190, 0, 0) @[dec_tlu_ctl.scala 2330:62] + node _T_1192 = eq(mhpme_vec[0], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2331:34] + node _T_1193 = bits(_T_1192, 0, 0) @[dec_tlu_ctl.scala 2331:62] + node _T_1194 = mux(_T_1028, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1195 = mux(_T_1030, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1196 = mux(_T_1032, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1197 = mux(_T_1034, _T_1036, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1198 = mux(_T_1038, _T_1042, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1199 = mux(_T_1044, _T_1047, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1200 = mux(_T_1049, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1201 = mux(_T_1051, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1202 = mux(_T_1053, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1203 = mux(_T_1055, _T_1056, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1204 = mux(_T_1058, _T_1059, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1205 = mux(_T_1061, _T_1062, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1206 = mux(_T_1064, _T_1065, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1207 = mux(_T_1067, _T_1069, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1208 = mux(_T_1071, _T_1074, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1209 = mux(_T_1076, _T_1077, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1210 = mux(_T_1079, _T_1080, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1211 = mux(_T_1082, _T_1083, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1212 = mux(_T_1085, _T_1086, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1213 = mux(_T_1088, _T_1089, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1214 = mux(_T_1091, _T_1092, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1215 = mux(_T_1094, _T_1095, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1216 = mux(_T_1097, _T_1098, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1217 = mux(_T_1100, _T_1101, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1218 = mux(_T_1103, _T_1106, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1219 = mux(_T_1108, _T_1109, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1220 = mux(_T_1111, _T_1112, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1221 = mux(_T_1114, _T_1115, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1222 = mux(_T_1117, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1223 = mux(_T_1119, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1224 = mux(_T_1121, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1225 = mux(_T_1123, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1226 = mux(_T_1125, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1227 = mux(_T_1127, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1228 = mux(_T_1129, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1229 = mux(_T_1131, _T_1133, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1230 = mux(_T_1135, _T_1137, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1231 = mux(_T_1139, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1232 = mux(_T_1141, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1233 = mux(_T_1143, _T_1145, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1234 = mux(_T_1147, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1235 = mux(_T_1149, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1236 = mux(_T_1151, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1237 = mux(_T_1153, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1238 = mux(_T_1155, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1239 = mux(_T_1157, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1240 = mux(_T_1159, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1241 = mux(_T_1161, _T_1164, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1242 = mux(_T_1166, _T_1174, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1243 = mux(_T_1176, _T_1177, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1244 = mux(_T_1179, _T_1180, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1245 = mux(_T_1182, _T_1183, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1246 = mux(_T_1185, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1247 = mux(_T_1187, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1248 = mux(_T_1189, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1249 = mux(_T_1191, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1250 = mux(_T_1193, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1251 = or(_T_1194, _T_1195) @[Mux.scala 27:72] node _T_1252 = or(_T_1251, _T_1196) @[Mux.scala 27:72] node _T_1253 = or(_T_1252, _T_1197) @[Mux.scala 27:72] node _T_1254 = or(_T_1253, _T_1198) @[Mux.scala 27:72] @@ -74689,238 +74697,238 @@ circuit quasar_wrapper : node _T_1303 = or(_T_1302, _T_1247) @[Mux.scala 27:72] node _T_1304 = or(_T_1303, _T_1248) @[Mux.scala 27:72] node _T_1305 = or(_T_1304, _T_1249) @[Mux.scala 27:72] - wire _T_1306 : UInt<1> @[Mux.scala 27:72] - _T_1306 <= _T_1305 @[Mux.scala 27:72] - node _T_1307 = and(_T_1025, _T_1306) @[dec_tlu_ctl.scala 2273:44] - mhpmc_inc_r[0] <= _T_1307 @[dec_tlu_ctl.scala 2273:19] - node _T_1308 = bits(mcountinhibit, 4, 4) @[dec_tlu_ctl.scala 2273:38] - node _T_1309 = not(_T_1308) @[dec_tlu_ctl.scala 2273:24] - node _T_1310 = eq(mhpme_vec[1], UInt<1>("h01")) @[dec_tlu_ctl.scala 2274:34] - node _T_1311 = bits(_T_1310, 0, 0) @[dec_tlu_ctl.scala 2274:62] - node _T_1312 = eq(mhpme_vec[1], UInt<2>("h02")) @[dec_tlu_ctl.scala 2275:34] - node _T_1313 = bits(_T_1312, 0, 0) @[dec_tlu_ctl.scala 2275:62] - node _T_1314 = eq(mhpme_vec[1], UInt<2>("h03")) @[dec_tlu_ctl.scala 2276:34] - node _T_1315 = bits(_T_1314, 0, 0) @[dec_tlu_ctl.scala 2276:62] - node _T_1316 = eq(mhpme_vec[1], UInt<3>("h04")) @[dec_tlu_ctl.scala 2277:34] - node _T_1317 = bits(_T_1316, 0, 0) @[dec_tlu_ctl.scala 2277:62] - node _T_1318 = not(io.illegal_r) @[dec_tlu_ctl.scala 2277:96] - node _T_1319 = and(io.tlu_i0_commit_cmt, _T_1318) @[dec_tlu_ctl.scala 2277:94] - node _T_1320 = eq(mhpme_vec[1], UInt<3>("h05")) @[dec_tlu_ctl.scala 2278:34] - node _T_1321 = bits(_T_1320, 0, 0) @[dec_tlu_ctl.scala 2278:62] - node _T_1322 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2278:96] - node _T_1323 = and(io.tlu_i0_commit_cmt, _T_1322) @[dec_tlu_ctl.scala 2278:94] - node _T_1324 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:117] - node _T_1325 = and(_T_1323, _T_1324) @[dec_tlu_ctl.scala 2278:115] - node _T_1326 = eq(mhpme_vec[1], UInt<3>("h06")) @[dec_tlu_ctl.scala 2279:34] - node _T_1327 = bits(_T_1326, 0, 0) @[dec_tlu_ctl.scala 2279:62] - node _T_1328 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2279:94] - node _T_1329 = not(io.illegal_r) @[dec_tlu_ctl.scala 2279:117] - node _T_1330 = and(_T_1328, _T_1329) @[dec_tlu_ctl.scala 2279:115] - node _T_1331 = eq(mhpme_vec[1], UInt<3>("h07")) @[dec_tlu_ctl.scala 2280:34] - node _T_1332 = bits(_T_1331, 0, 0) @[dec_tlu_ctl.scala 2280:62] - node _T_1333 = eq(mhpme_vec[1], UInt<4>("h08")) @[dec_tlu_ctl.scala 2281:34] - node _T_1334 = bits(_T_1333, 0, 0) @[dec_tlu_ctl.scala 2281:62] - node _T_1335 = eq(mhpme_vec[1], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2282:34] - node _T_1336 = bits(_T_1335, 0, 0) @[dec_tlu_ctl.scala 2282:62] - node _T_1337 = eq(mhpme_vec[1], UInt<4>("h09")) @[dec_tlu_ctl.scala 2283:34] - node _T_1338 = bits(_T_1337, 0, 0) @[dec_tlu_ctl.scala 2283:62] - node _T_1339 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2283:91] - node _T_1340 = eq(mhpme_vec[1], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2284:34] - node _T_1341 = bits(_T_1340, 0, 0) @[dec_tlu_ctl.scala 2284:62] - node _T_1342 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2284:105] - node _T_1343 = eq(mhpme_vec[1], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2285:34] - node _T_1344 = bits(_T_1343, 0, 0) @[dec_tlu_ctl.scala 2285:62] - node _T_1345 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2285:91] - node _T_1346 = eq(mhpme_vec[1], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2286:34] - node _T_1347 = bits(_T_1346, 0, 0) @[dec_tlu_ctl.scala 2286:62] - node _T_1348 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2286:91] - node _T_1349 = eq(mhpme_vec[1], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2287:34] - node _T_1350 = bits(_T_1349, 0, 0) @[dec_tlu_ctl.scala 2287:62] - node _T_1351 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2287:91] - node _T_1352 = and(_T_1351, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2287:100] - node _T_1353 = eq(mhpme_vec[1], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2288:34] - node _T_1354 = bits(_T_1353, 0, 0) @[dec_tlu_ctl.scala 2288:62] - node _T_1355 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2288:91] - node _T_1356 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2288:142] - node _T_1357 = and(_T_1355, _T_1356) @[dec_tlu_ctl.scala 2288:101] - node _T_1358 = eq(mhpme_vec[1], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2289:34] - node _T_1359 = bits(_T_1358, 0, 0) @[dec_tlu_ctl.scala 2289:59] - node _T_1360 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2289:89] - node _T_1361 = eq(mhpme_vec[1], UInt<5>("h010")) @[dec_tlu_ctl.scala 2290:34] - node _T_1362 = bits(_T_1361, 0, 0) @[dec_tlu_ctl.scala 2290:59] - node _T_1363 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2290:89] - node _T_1364 = eq(mhpme_vec[1], UInt<5>("h012")) @[dec_tlu_ctl.scala 2291:34] - node _T_1365 = bits(_T_1364, 0, 0) @[dec_tlu_ctl.scala 2291:59] - node _T_1366 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2291:89] - node _T_1367 = eq(mhpme_vec[1], UInt<5>("h011")) @[dec_tlu_ctl.scala 2292:34] - node _T_1368 = bits(_T_1367, 0, 0) @[dec_tlu_ctl.scala 2292:59] - node _T_1369 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2292:89] - node _T_1370 = eq(mhpme_vec[1], UInt<5>("h013")) @[dec_tlu_ctl.scala 2293:34] - node _T_1371 = bits(_T_1370, 0, 0) @[dec_tlu_ctl.scala 2293:59] - node _T_1372 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2293:89] - node _T_1373 = eq(mhpme_vec[1], UInt<5>("h014")) @[dec_tlu_ctl.scala 2294:34] - node _T_1374 = bits(_T_1373, 0, 0) @[dec_tlu_ctl.scala 2294:59] - node _T_1375 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2294:89] - node _T_1376 = eq(mhpme_vec[1], UInt<5>("h015")) @[dec_tlu_ctl.scala 2295:34] - node _T_1377 = bits(_T_1376, 0, 0) @[dec_tlu_ctl.scala 2295:59] - node _T_1378 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2295:89] - node _T_1379 = eq(mhpme_vec[1], UInt<5>("h016")) @[dec_tlu_ctl.scala 2296:34] - node _T_1380 = bits(_T_1379, 0, 0) @[dec_tlu_ctl.scala 2296:59] - node _T_1381 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2296:89] - node _T_1382 = eq(mhpme_vec[1], UInt<5>("h017")) @[dec_tlu_ctl.scala 2297:34] - node _T_1383 = bits(_T_1382, 0, 0) @[dec_tlu_ctl.scala 2297:59] - node _T_1384 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2297:89] - node _T_1385 = eq(mhpme_vec[1], UInt<5>("h018")) @[dec_tlu_ctl.scala 2298:34] - node _T_1386 = bits(_T_1385, 0, 0) @[dec_tlu_ctl.scala 2298:59] - node _T_1387 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2298:89] - node _T_1388 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2298:122] - node _T_1389 = or(_T_1387, _T_1388) @[dec_tlu_ctl.scala 2298:101] - node _T_1390 = eq(mhpme_vec[1], UInt<5>("h019")) @[dec_tlu_ctl.scala 2299:34] - node _T_1391 = bits(_T_1390, 0, 0) @[dec_tlu_ctl.scala 2299:62] - node _T_1392 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2299:95] - node _T_1393 = eq(mhpme_vec[1], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2300:34] - node _T_1394 = bits(_T_1393, 0, 0) @[dec_tlu_ctl.scala 2300:62] - node _T_1395 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:97] - node _T_1396 = eq(mhpme_vec[1], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2301:34] - node _T_1397 = bits(_T_1396, 0, 0) @[dec_tlu_ctl.scala 2301:62] - node _T_1398 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2301:110] - node _T_1399 = eq(mhpme_vec[1], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2302:34] - node _T_1400 = bits(_T_1399, 0, 0) @[dec_tlu_ctl.scala 2302:62] - node _T_1401 = eq(mhpme_vec[1], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2303:34] - node _T_1402 = bits(_T_1401, 0, 0) @[dec_tlu_ctl.scala 2303:62] - node _T_1403 = eq(mhpme_vec[1], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2304:34] - node _T_1404 = bits(_T_1403, 0, 0) @[dec_tlu_ctl.scala 2304:62] - node _T_1405 = eq(mhpme_vec[1], UInt<6>("h020")) @[dec_tlu_ctl.scala 2305:34] - node _T_1406 = bits(_T_1405, 0, 0) @[dec_tlu_ctl.scala 2305:62] - node _T_1407 = eq(mhpme_vec[1], UInt<6>("h022")) @[dec_tlu_ctl.scala 2306:34] - node _T_1408 = bits(_T_1407, 0, 0) @[dec_tlu_ctl.scala 2306:62] - node _T_1409 = eq(mhpme_vec[1], UInt<6>("h023")) @[dec_tlu_ctl.scala 2307:34] - node _T_1410 = bits(_T_1409, 0, 0) @[dec_tlu_ctl.scala 2307:62] - node _T_1411 = eq(mhpme_vec[1], UInt<6>("h024")) @[dec_tlu_ctl.scala 2308:34] - node _T_1412 = bits(_T_1411, 0, 0) @[dec_tlu_ctl.scala 2308:62] - node _T_1413 = eq(mhpme_vec[1], UInt<6>("h025")) @[dec_tlu_ctl.scala 2309:34] - node _T_1414 = bits(_T_1413, 0, 0) @[dec_tlu_ctl.scala 2309:62] - node _T_1415 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2309:98] - node _T_1416 = or(_T_1415, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2309:120] - node _T_1417 = eq(mhpme_vec[1], UInt<6>("h026")) @[dec_tlu_ctl.scala 2310:34] - node _T_1418 = bits(_T_1417, 0, 0) @[dec_tlu_ctl.scala 2310:62] - node _T_1419 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2310:92] - node _T_1420 = or(_T_1419, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2310:117] - node _T_1421 = eq(mhpme_vec[1], UInt<6>("h027")) @[dec_tlu_ctl.scala 2311:34] - node _T_1422 = bits(_T_1421, 0, 0) @[dec_tlu_ctl.scala 2311:62] - node _T_1423 = eq(mhpme_vec[1], UInt<6>("h028")) @[dec_tlu_ctl.scala 2312:34] - node _T_1424 = bits(_T_1423, 0, 0) @[dec_tlu_ctl.scala 2312:62] - node _T_1425 = eq(mhpme_vec[1], UInt<6>("h029")) @[dec_tlu_ctl.scala 2313:34] - node _T_1426 = bits(_T_1425, 0, 0) @[dec_tlu_ctl.scala 2313:62] - node _T_1427 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2313:97] - node _T_1428 = and(_T_1427, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2313:129] - node _T_1429 = eq(mhpme_vec[1], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2314:34] - node _T_1430 = bits(_T_1429, 0, 0) @[dec_tlu_ctl.scala 2314:62] - node _T_1431 = eq(mhpme_vec[1], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2315:34] - node _T_1432 = bits(_T_1431, 0, 0) @[dec_tlu_ctl.scala 2315:62] - node _T_1433 = eq(mhpme_vec[1], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2316:34] - node _T_1434 = bits(_T_1433, 0, 0) @[dec_tlu_ctl.scala 2316:62] - node _T_1435 = eq(mhpme_vec[1], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2317:34] - node _T_1436 = bits(_T_1435, 0, 0) @[dec_tlu_ctl.scala 2317:62] - node _T_1437 = eq(mhpme_vec[1], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2318:34] - node _T_1438 = bits(_T_1437, 0, 0) @[dec_tlu_ctl.scala 2318:62] - node _T_1439 = eq(mhpme_vec[1], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2319:34] - node _T_1440 = bits(_T_1439, 0, 0) @[dec_tlu_ctl.scala 2319:62] - node _T_1441 = eq(mhpme_vec[1], UInt<6>("h030")) @[dec_tlu_ctl.scala 2320:34] - node _T_1442 = bits(_T_1441, 0, 0) @[dec_tlu_ctl.scala 2320:62] - node _T_1443 = eq(mhpme_vec[1], UInt<6>("h031")) @[dec_tlu_ctl.scala 2321:34] - node _T_1444 = bits(_T_1443, 0, 0) @[dec_tlu_ctl.scala 2321:62] - node _T_1445 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2321:84] - node _T_1446 = bits(_T_1445, 0, 0) @[dec_tlu_ctl.scala 2321:84] - node _T_1447 = not(_T_1446) @[dec_tlu_ctl.scala 2321:73] - node _T_1448 = eq(mhpme_vec[1], UInt<6>("h032")) @[dec_tlu_ctl.scala 2322:34] - node _T_1449 = bits(_T_1448, 0, 0) @[dec_tlu_ctl.scala 2322:62] - node _T_1450 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2322:84] - node _T_1451 = bits(_T_1450, 0, 0) @[dec_tlu_ctl.scala 2322:84] - node _T_1452 = not(_T_1451) @[dec_tlu_ctl.scala 2322:73] - node _T_1453 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2322:107] - node _T_1454 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2322:118] - node _T_1455 = and(_T_1453, _T_1454) @[dec_tlu_ctl.scala 2322:113] - node _T_1456 = orr(_T_1455) @[dec_tlu_ctl.scala 2322:125] - node _T_1457 = and(_T_1452, _T_1456) @[dec_tlu_ctl.scala 2322:98] - node _T_1458 = eq(mhpme_vec[1], UInt<6>("h036")) @[dec_tlu_ctl.scala 2323:34] - node _T_1459 = bits(_T_1458, 0, 0) @[dec_tlu_ctl.scala 2323:62] - node _T_1460 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2323:91] - node _T_1461 = eq(mhpme_vec[1], UInt<6>("h037")) @[dec_tlu_ctl.scala 2324:34] - node _T_1462 = bits(_T_1461, 0, 0) @[dec_tlu_ctl.scala 2324:62] - node _T_1463 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2324:94] - node _T_1464 = eq(mhpme_vec[1], UInt<6>("h038")) @[dec_tlu_ctl.scala 2325:34] - node _T_1465 = bits(_T_1464, 0, 0) @[dec_tlu_ctl.scala 2325:62] - node _T_1466 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2325:94] - node _T_1467 = eq(mhpme_vec[1], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2327:34] - node _T_1468 = bits(_T_1467, 0, 0) @[dec_tlu_ctl.scala 2327:62] - node _T_1469 = eq(mhpme_vec[1], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2328:34] - node _T_1470 = bits(_T_1469, 0, 0) @[dec_tlu_ctl.scala 2328:62] - node _T_1471 = eq(mhpme_vec[1], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2329:34] - node _T_1472 = bits(_T_1471, 0, 0) @[dec_tlu_ctl.scala 2329:62] - node _T_1473 = eq(mhpme_vec[1], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2330:34] - node _T_1474 = bits(_T_1473, 0, 0) @[dec_tlu_ctl.scala 2330:62] - node _T_1475 = eq(mhpme_vec[1], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2331:34] - node _T_1476 = bits(_T_1475, 0, 0) @[dec_tlu_ctl.scala 2331:62] - node _T_1477 = mux(_T_1311, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1478 = mux(_T_1313, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1479 = mux(_T_1315, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1480 = mux(_T_1317, _T_1319, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1481 = mux(_T_1321, _T_1325, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1482 = mux(_T_1327, _T_1330, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1483 = mux(_T_1332, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1484 = mux(_T_1334, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1485 = mux(_T_1336, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1486 = mux(_T_1338, _T_1339, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1487 = mux(_T_1341, _T_1342, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1488 = mux(_T_1344, _T_1345, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1489 = mux(_T_1347, _T_1348, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1490 = mux(_T_1350, _T_1352, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1491 = mux(_T_1354, _T_1357, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1492 = mux(_T_1359, _T_1360, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1493 = mux(_T_1362, _T_1363, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1494 = mux(_T_1365, _T_1366, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1495 = mux(_T_1368, _T_1369, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1496 = mux(_T_1371, _T_1372, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1497 = mux(_T_1374, _T_1375, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1498 = mux(_T_1377, _T_1378, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1499 = mux(_T_1380, _T_1381, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1500 = mux(_T_1383, _T_1384, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1501 = mux(_T_1386, _T_1389, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1502 = mux(_T_1391, _T_1392, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1503 = mux(_T_1394, _T_1395, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1504 = mux(_T_1397, _T_1398, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1505 = mux(_T_1400, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1506 = mux(_T_1402, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1507 = mux(_T_1404, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1508 = mux(_T_1406, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1509 = mux(_T_1408, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1510 = mux(_T_1410, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1511 = mux(_T_1412, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1512 = mux(_T_1414, _T_1416, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1513 = mux(_T_1418, _T_1420, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1514 = mux(_T_1422, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1515 = mux(_T_1424, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1516 = mux(_T_1426, _T_1428, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1517 = mux(_T_1430, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1518 = mux(_T_1432, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1519 = mux(_T_1434, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1520 = mux(_T_1436, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1521 = mux(_T_1438, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1522 = mux(_T_1440, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1523 = mux(_T_1442, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1524 = mux(_T_1444, _T_1447, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1525 = mux(_T_1449, _T_1457, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1526 = mux(_T_1459, _T_1460, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1527 = mux(_T_1462, _T_1463, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1528 = mux(_T_1465, _T_1466, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1529 = mux(_T_1468, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1530 = mux(_T_1470, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1531 = mux(_T_1472, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1532 = mux(_T_1474, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1533 = mux(_T_1476, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1534 = or(_T_1477, _T_1478) @[Mux.scala 27:72] - node _T_1535 = or(_T_1534, _T_1479) @[Mux.scala 27:72] + node _T_1306 = or(_T_1305, _T_1250) @[Mux.scala 27:72] + wire _T_1307 : UInt<1> @[Mux.scala 27:72] + _T_1307 <= _T_1306 @[Mux.scala 27:72] + node _T_1308 = and(_T_1026, _T_1307) @[dec_tlu_ctl.scala 2273:44] + mhpmc_inc_r[0] <= _T_1308 @[dec_tlu_ctl.scala 2273:19] + node _T_1309 = bits(mcountinhibit, 4, 4) @[dec_tlu_ctl.scala 2273:38] + node _T_1310 = not(_T_1309) @[dec_tlu_ctl.scala 2273:24] + node _T_1311 = eq(mhpme_vec[1], UInt<1>("h01")) @[dec_tlu_ctl.scala 2274:34] + node _T_1312 = bits(_T_1311, 0, 0) @[dec_tlu_ctl.scala 2274:62] + node _T_1313 = eq(mhpme_vec[1], UInt<2>("h02")) @[dec_tlu_ctl.scala 2275:34] + node _T_1314 = bits(_T_1313, 0, 0) @[dec_tlu_ctl.scala 2275:62] + node _T_1315 = eq(mhpme_vec[1], UInt<2>("h03")) @[dec_tlu_ctl.scala 2276:34] + node _T_1316 = bits(_T_1315, 0, 0) @[dec_tlu_ctl.scala 2276:62] + node _T_1317 = eq(mhpme_vec[1], UInt<3>("h04")) @[dec_tlu_ctl.scala 2277:34] + node _T_1318 = bits(_T_1317, 0, 0) @[dec_tlu_ctl.scala 2277:62] + node _T_1319 = not(io.illegal_r) @[dec_tlu_ctl.scala 2277:96] + node _T_1320 = and(io.tlu_i0_commit_cmt, _T_1319) @[dec_tlu_ctl.scala 2277:94] + node _T_1321 = eq(mhpme_vec[1], UInt<3>("h05")) @[dec_tlu_ctl.scala 2278:34] + node _T_1322 = bits(_T_1321, 0, 0) @[dec_tlu_ctl.scala 2278:62] + node _T_1323 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2278:96] + node _T_1324 = and(io.tlu_i0_commit_cmt, _T_1323) @[dec_tlu_ctl.scala 2278:94] + node _T_1325 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:117] + node _T_1326 = and(_T_1324, _T_1325) @[dec_tlu_ctl.scala 2278:115] + node _T_1327 = eq(mhpme_vec[1], UInt<3>("h06")) @[dec_tlu_ctl.scala 2279:34] + node _T_1328 = bits(_T_1327, 0, 0) @[dec_tlu_ctl.scala 2279:62] + node _T_1329 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2279:94] + node _T_1330 = not(io.illegal_r) @[dec_tlu_ctl.scala 2279:117] + node _T_1331 = and(_T_1329, _T_1330) @[dec_tlu_ctl.scala 2279:115] + node _T_1332 = eq(mhpme_vec[1], UInt<3>("h07")) @[dec_tlu_ctl.scala 2280:34] + node _T_1333 = bits(_T_1332, 0, 0) @[dec_tlu_ctl.scala 2280:62] + node _T_1334 = eq(mhpme_vec[1], UInt<4>("h08")) @[dec_tlu_ctl.scala 2281:34] + node _T_1335 = bits(_T_1334, 0, 0) @[dec_tlu_ctl.scala 2281:62] + node _T_1336 = eq(mhpme_vec[1], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2282:34] + node _T_1337 = bits(_T_1336, 0, 0) @[dec_tlu_ctl.scala 2282:62] + node _T_1338 = eq(mhpme_vec[1], UInt<4>("h09")) @[dec_tlu_ctl.scala 2283:34] + node _T_1339 = bits(_T_1338, 0, 0) @[dec_tlu_ctl.scala 2283:62] + node _T_1340 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2283:91] + node _T_1341 = eq(mhpme_vec[1], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2284:34] + node _T_1342 = bits(_T_1341, 0, 0) @[dec_tlu_ctl.scala 2284:62] + node _T_1343 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2284:105] + node _T_1344 = eq(mhpme_vec[1], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2285:34] + node _T_1345 = bits(_T_1344, 0, 0) @[dec_tlu_ctl.scala 2285:62] + node _T_1346 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2285:91] + node _T_1347 = eq(mhpme_vec[1], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2286:34] + node _T_1348 = bits(_T_1347, 0, 0) @[dec_tlu_ctl.scala 2286:62] + node _T_1349 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2286:91] + node _T_1350 = eq(mhpme_vec[1], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2287:34] + node _T_1351 = bits(_T_1350, 0, 0) @[dec_tlu_ctl.scala 2287:62] + node _T_1352 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2287:91] + node _T_1353 = and(_T_1352, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2287:100] + node _T_1354 = eq(mhpme_vec[1], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2288:34] + node _T_1355 = bits(_T_1354, 0, 0) @[dec_tlu_ctl.scala 2288:62] + node _T_1356 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2288:91] + node _T_1357 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2288:142] + node _T_1358 = and(_T_1356, _T_1357) @[dec_tlu_ctl.scala 2288:101] + node _T_1359 = eq(mhpme_vec[1], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2289:34] + node _T_1360 = bits(_T_1359, 0, 0) @[dec_tlu_ctl.scala 2289:59] + node _T_1361 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2289:89] + node _T_1362 = eq(mhpme_vec[1], UInt<5>("h010")) @[dec_tlu_ctl.scala 2290:34] + node _T_1363 = bits(_T_1362, 0, 0) @[dec_tlu_ctl.scala 2290:59] + node _T_1364 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2290:89] + node _T_1365 = eq(mhpme_vec[1], UInt<5>("h012")) @[dec_tlu_ctl.scala 2291:34] + node _T_1366 = bits(_T_1365, 0, 0) @[dec_tlu_ctl.scala 2291:59] + node _T_1367 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2291:89] + node _T_1368 = eq(mhpme_vec[1], UInt<5>("h011")) @[dec_tlu_ctl.scala 2292:34] + node _T_1369 = bits(_T_1368, 0, 0) @[dec_tlu_ctl.scala 2292:59] + node _T_1370 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2292:89] + node _T_1371 = eq(mhpme_vec[1], UInt<5>("h013")) @[dec_tlu_ctl.scala 2293:34] + node _T_1372 = bits(_T_1371, 0, 0) @[dec_tlu_ctl.scala 2293:59] + node _T_1373 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2293:89] + node _T_1374 = eq(mhpme_vec[1], UInt<5>("h014")) @[dec_tlu_ctl.scala 2294:34] + node _T_1375 = bits(_T_1374, 0, 0) @[dec_tlu_ctl.scala 2294:59] + node _T_1376 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2294:89] + node _T_1377 = eq(mhpme_vec[1], UInt<5>("h015")) @[dec_tlu_ctl.scala 2295:34] + node _T_1378 = bits(_T_1377, 0, 0) @[dec_tlu_ctl.scala 2295:59] + node _T_1379 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2295:89] + node _T_1380 = eq(mhpme_vec[1], UInt<5>("h016")) @[dec_tlu_ctl.scala 2296:34] + node _T_1381 = bits(_T_1380, 0, 0) @[dec_tlu_ctl.scala 2296:59] + node _T_1382 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2296:89] + node _T_1383 = eq(mhpme_vec[1], UInt<5>("h017")) @[dec_tlu_ctl.scala 2297:34] + node _T_1384 = bits(_T_1383, 0, 0) @[dec_tlu_ctl.scala 2297:59] + node _T_1385 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2297:89] + node _T_1386 = eq(mhpme_vec[1], UInt<5>("h018")) @[dec_tlu_ctl.scala 2298:34] + node _T_1387 = bits(_T_1386, 0, 0) @[dec_tlu_ctl.scala 2298:59] + node _T_1388 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2298:89] + node _T_1389 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2298:122] + node _T_1390 = or(_T_1388, _T_1389) @[dec_tlu_ctl.scala 2298:101] + node _T_1391 = eq(mhpme_vec[1], UInt<5>("h019")) @[dec_tlu_ctl.scala 2299:34] + node _T_1392 = bits(_T_1391, 0, 0) @[dec_tlu_ctl.scala 2299:62] + node _T_1393 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2299:95] + node _T_1394 = eq(mhpme_vec[1], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2300:34] + node _T_1395 = bits(_T_1394, 0, 0) @[dec_tlu_ctl.scala 2300:62] + node _T_1396 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:97] + node _T_1397 = eq(mhpme_vec[1], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2301:34] + node _T_1398 = bits(_T_1397, 0, 0) @[dec_tlu_ctl.scala 2301:62] + node _T_1399 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2301:110] + node _T_1400 = eq(mhpme_vec[1], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2302:34] + node _T_1401 = bits(_T_1400, 0, 0) @[dec_tlu_ctl.scala 2302:62] + node _T_1402 = eq(mhpme_vec[1], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2303:34] + node _T_1403 = bits(_T_1402, 0, 0) @[dec_tlu_ctl.scala 2303:62] + node _T_1404 = eq(mhpme_vec[1], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2304:34] + node _T_1405 = bits(_T_1404, 0, 0) @[dec_tlu_ctl.scala 2304:62] + node _T_1406 = eq(mhpme_vec[1], UInt<6>("h020")) @[dec_tlu_ctl.scala 2305:34] + node _T_1407 = bits(_T_1406, 0, 0) @[dec_tlu_ctl.scala 2305:62] + node _T_1408 = eq(mhpme_vec[1], UInt<6>("h022")) @[dec_tlu_ctl.scala 2306:34] + node _T_1409 = bits(_T_1408, 0, 0) @[dec_tlu_ctl.scala 2306:62] + node _T_1410 = eq(mhpme_vec[1], UInt<6>("h023")) @[dec_tlu_ctl.scala 2307:34] + node _T_1411 = bits(_T_1410, 0, 0) @[dec_tlu_ctl.scala 2307:62] + node _T_1412 = eq(mhpme_vec[1], UInt<6>("h024")) @[dec_tlu_ctl.scala 2308:34] + node _T_1413 = bits(_T_1412, 0, 0) @[dec_tlu_ctl.scala 2308:62] + node _T_1414 = eq(mhpme_vec[1], UInt<6>("h025")) @[dec_tlu_ctl.scala 2309:34] + node _T_1415 = bits(_T_1414, 0, 0) @[dec_tlu_ctl.scala 2309:62] + node _T_1416 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2309:98] + node _T_1417 = or(_T_1416, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2309:120] + node _T_1418 = eq(mhpme_vec[1], UInt<6>("h026")) @[dec_tlu_ctl.scala 2310:34] + node _T_1419 = bits(_T_1418, 0, 0) @[dec_tlu_ctl.scala 2310:62] + node _T_1420 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2310:92] + node _T_1421 = or(_T_1420, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2310:117] + node _T_1422 = eq(mhpme_vec[1], UInt<6>("h027")) @[dec_tlu_ctl.scala 2311:34] + node _T_1423 = bits(_T_1422, 0, 0) @[dec_tlu_ctl.scala 2311:62] + node _T_1424 = eq(mhpme_vec[1], UInt<6>("h028")) @[dec_tlu_ctl.scala 2312:34] + node _T_1425 = bits(_T_1424, 0, 0) @[dec_tlu_ctl.scala 2312:62] + node _T_1426 = eq(mhpme_vec[1], UInt<6>("h029")) @[dec_tlu_ctl.scala 2313:34] + node _T_1427 = bits(_T_1426, 0, 0) @[dec_tlu_ctl.scala 2313:62] + node _T_1428 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2313:97] + node _T_1429 = and(_T_1428, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2313:129] + node _T_1430 = eq(mhpme_vec[1], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2314:34] + node _T_1431 = bits(_T_1430, 0, 0) @[dec_tlu_ctl.scala 2314:62] + node _T_1432 = eq(mhpme_vec[1], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2315:34] + node _T_1433 = bits(_T_1432, 0, 0) @[dec_tlu_ctl.scala 2315:62] + node _T_1434 = eq(mhpme_vec[1], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2316:34] + node _T_1435 = bits(_T_1434, 0, 0) @[dec_tlu_ctl.scala 2316:62] + node _T_1436 = eq(mhpme_vec[1], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2317:34] + node _T_1437 = bits(_T_1436, 0, 0) @[dec_tlu_ctl.scala 2317:62] + node _T_1438 = eq(mhpme_vec[1], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2318:34] + node _T_1439 = bits(_T_1438, 0, 0) @[dec_tlu_ctl.scala 2318:62] + node _T_1440 = eq(mhpme_vec[1], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2319:34] + node _T_1441 = bits(_T_1440, 0, 0) @[dec_tlu_ctl.scala 2319:62] + node _T_1442 = eq(mhpme_vec[1], UInt<6>("h030")) @[dec_tlu_ctl.scala 2320:34] + node _T_1443 = bits(_T_1442, 0, 0) @[dec_tlu_ctl.scala 2320:62] + node _T_1444 = eq(mhpme_vec[1], UInt<6>("h031")) @[dec_tlu_ctl.scala 2321:34] + node _T_1445 = bits(_T_1444, 0, 0) @[dec_tlu_ctl.scala 2321:62] + node _T_1446 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2321:84] + node _T_1447 = bits(_T_1446, 0, 0) @[dec_tlu_ctl.scala 2321:84] + node _T_1448 = not(_T_1447) @[dec_tlu_ctl.scala 2321:73] + node _T_1449 = eq(mhpme_vec[1], UInt<6>("h032")) @[dec_tlu_ctl.scala 2322:34] + node _T_1450 = bits(_T_1449, 0, 0) @[dec_tlu_ctl.scala 2322:62] + node _T_1451 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2322:84] + node _T_1452 = bits(_T_1451, 0, 0) @[dec_tlu_ctl.scala 2322:84] + node _T_1453 = not(_T_1452) @[dec_tlu_ctl.scala 2322:73] + node _T_1454 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2322:107] + node _T_1455 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2322:118] + node _T_1456 = and(_T_1454, _T_1455) @[dec_tlu_ctl.scala 2322:113] + node _T_1457 = orr(_T_1456) @[dec_tlu_ctl.scala 2322:125] + node _T_1458 = and(_T_1453, _T_1457) @[dec_tlu_ctl.scala 2322:98] + node _T_1459 = eq(mhpme_vec[1], UInt<6>("h036")) @[dec_tlu_ctl.scala 2323:34] + node _T_1460 = bits(_T_1459, 0, 0) @[dec_tlu_ctl.scala 2323:62] + node _T_1461 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2323:91] + node _T_1462 = eq(mhpme_vec[1], UInt<6>("h037")) @[dec_tlu_ctl.scala 2324:34] + node _T_1463 = bits(_T_1462, 0, 0) @[dec_tlu_ctl.scala 2324:62] + node _T_1464 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2324:94] + node _T_1465 = eq(mhpme_vec[1], UInt<6>("h038")) @[dec_tlu_ctl.scala 2325:34] + node _T_1466 = bits(_T_1465, 0, 0) @[dec_tlu_ctl.scala 2325:62] + node _T_1467 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2325:94] + node _T_1468 = eq(mhpme_vec[1], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2327:34] + node _T_1469 = bits(_T_1468, 0, 0) @[dec_tlu_ctl.scala 2327:62] + node _T_1470 = eq(mhpme_vec[1], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2328:34] + node _T_1471 = bits(_T_1470, 0, 0) @[dec_tlu_ctl.scala 2328:62] + node _T_1472 = eq(mhpme_vec[1], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2329:34] + node _T_1473 = bits(_T_1472, 0, 0) @[dec_tlu_ctl.scala 2329:62] + node _T_1474 = eq(mhpme_vec[1], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2330:34] + node _T_1475 = bits(_T_1474, 0, 0) @[dec_tlu_ctl.scala 2330:62] + node _T_1476 = eq(mhpme_vec[1], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2331:34] + node _T_1477 = bits(_T_1476, 0, 0) @[dec_tlu_ctl.scala 2331:62] + node _T_1478 = mux(_T_1312, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1479 = mux(_T_1314, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1480 = mux(_T_1316, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1481 = mux(_T_1318, _T_1320, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1482 = mux(_T_1322, _T_1326, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1483 = mux(_T_1328, _T_1331, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1484 = mux(_T_1333, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1485 = mux(_T_1335, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1486 = mux(_T_1337, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1487 = mux(_T_1339, _T_1340, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1488 = mux(_T_1342, _T_1343, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1489 = mux(_T_1345, _T_1346, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1490 = mux(_T_1348, _T_1349, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1491 = mux(_T_1351, _T_1353, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1492 = mux(_T_1355, _T_1358, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1493 = mux(_T_1360, _T_1361, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1494 = mux(_T_1363, _T_1364, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1495 = mux(_T_1366, _T_1367, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1496 = mux(_T_1369, _T_1370, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1497 = mux(_T_1372, _T_1373, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1498 = mux(_T_1375, _T_1376, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1499 = mux(_T_1378, _T_1379, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1500 = mux(_T_1381, _T_1382, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1501 = mux(_T_1384, _T_1385, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1502 = mux(_T_1387, _T_1390, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1503 = mux(_T_1392, _T_1393, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1504 = mux(_T_1395, _T_1396, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1505 = mux(_T_1398, _T_1399, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1506 = mux(_T_1401, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1507 = mux(_T_1403, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1508 = mux(_T_1405, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1509 = mux(_T_1407, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1510 = mux(_T_1409, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1511 = mux(_T_1411, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1512 = mux(_T_1413, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1513 = mux(_T_1415, _T_1417, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1514 = mux(_T_1419, _T_1421, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1515 = mux(_T_1423, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1516 = mux(_T_1425, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1517 = mux(_T_1427, _T_1429, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1518 = mux(_T_1431, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1519 = mux(_T_1433, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1520 = mux(_T_1435, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1521 = mux(_T_1437, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1522 = mux(_T_1439, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1523 = mux(_T_1441, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1524 = mux(_T_1443, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1525 = mux(_T_1445, _T_1448, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1526 = mux(_T_1450, _T_1458, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1527 = mux(_T_1460, _T_1461, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1528 = mux(_T_1463, _T_1464, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1529 = mux(_T_1466, _T_1467, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1530 = mux(_T_1469, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1531 = mux(_T_1471, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1532 = mux(_T_1473, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1533 = mux(_T_1475, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1534 = mux(_T_1477, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1535 = or(_T_1478, _T_1479) @[Mux.scala 27:72] node _T_1536 = or(_T_1535, _T_1480) @[Mux.scala 27:72] node _T_1537 = or(_T_1536, _T_1481) @[Mux.scala 27:72] node _T_1538 = or(_T_1537, _T_1482) @[Mux.scala 27:72] @@ -74975,238 +74983,238 @@ circuit quasar_wrapper : node _T_1587 = or(_T_1586, _T_1531) @[Mux.scala 27:72] node _T_1588 = or(_T_1587, _T_1532) @[Mux.scala 27:72] node _T_1589 = or(_T_1588, _T_1533) @[Mux.scala 27:72] - wire _T_1590 : UInt<1> @[Mux.scala 27:72] - _T_1590 <= _T_1589 @[Mux.scala 27:72] - node _T_1591 = and(_T_1309, _T_1590) @[dec_tlu_ctl.scala 2273:44] - mhpmc_inc_r[1] <= _T_1591 @[dec_tlu_ctl.scala 2273:19] - node _T_1592 = bits(mcountinhibit, 5, 5) @[dec_tlu_ctl.scala 2273:38] - node _T_1593 = not(_T_1592) @[dec_tlu_ctl.scala 2273:24] - node _T_1594 = eq(mhpme_vec[2], UInt<1>("h01")) @[dec_tlu_ctl.scala 2274:34] - node _T_1595 = bits(_T_1594, 0, 0) @[dec_tlu_ctl.scala 2274:62] - node _T_1596 = eq(mhpme_vec[2], UInt<2>("h02")) @[dec_tlu_ctl.scala 2275:34] - node _T_1597 = bits(_T_1596, 0, 0) @[dec_tlu_ctl.scala 2275:62] - node _T_1598 = eq(mhpme_vec[2], UInt<2>("h03")) @[dec_tlu_ctl.scala 2276:34] - node _T_1599 = bits(_T_1598, 0, 0) @[dec_tlu_ctl.scala 2276:62] - node _T_1600 = eq(mhpme_vec[2], UInt<3>("h04")) @[dec_tlu_ctl.scala 2277:34] - node _T_1601 = bits(_T_1600, 0, 0) @[dec_tlu_ctl.scala 2277:62] - node _T_1602 = not(io.illegal_r) @[dec_tlu_ctl.scala 2277:96] - node _T_1603 = and(io.tlu_i0_commit_cmt, _T_1602) @[dec_tlu_ctl.scala 2277:94] - node _T_1604 = eq(mhpme_vec[2], UInt<3>("h05")) @[dec_tlu_ctl.scala 2278:34] - node _T_1605 = bits(_T_1604, 0, 0) @[dec_tlu_ctl.scala 2278:62] - node _T_1606 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2278:96] - node _T_1607 = and(io.tlu_i0_commit_cmt, _T_1606) @[dec_tlu_ctl.scala 2278:94] - node _T_1608 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:117] - node _T_1609 = and(_T_1607, _T_1608) @[dec_tlu_ctl.scala 2278:115] - node _T_1610 = eq(mhpme_vec[2], UInt<3>("h06")) @[dec_tlu_ctl.scala 2279:34] - node _T_1611 = bits(_T_1610, 0, 0) @[dec_tlu_ctl.scala 2279:62] - node _T_1612 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2279:94] - node _T_1613 = not(io.illegal_r) @[dec_tlu_ctl.scala 2279:117] - node _T_1614 = and(_T_1612, _T_1613) @[dec_tlu_ctl.scala 2279:115] - node _T_1615 = eq(mhpme_vec[2], UInt<3>("h07")) @[dec_tlu_ctl.scala 2280:34] - node _T_1616 = bits(_T_1615, 0, 0) @[dec_tlu_ctl.scala 2280:62] - node _T_1617 = eq(mhpme_vec[2], UInt<4>("h08")) @[dec_tlu_ctl.scala 2281:34] - node _T_1618 = bits(_T_1617, 0, 0) @[dec_tlu_ctl.scala 2281:62] - node _T_1619 = eq(mhpme_vec[2], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2282:34] - node _T_1620 = bits(_T_1619, 0, 0) @[dec_tlu_ctl.scala 2282:62] - node _T_1621 = eq(mhpme_vec[2], UInt<4>("h09")) @[dec_tlu_ctl.scala 2283:34] - node _T_1622 = bits(_T_1621, 0, 0) @[dec_tlu_ctl.scala 2283:62] - node _T_1623 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2283:91] - node _T_1624 = eq(mhpme_vec[2], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2284:34] - node _T_1625 = bits(_T_1624, 0, 0) @[dec_tlu_ctl.scala 2284:62] - node _T_1626 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2284:105] - node _T_1627 = eq(mhpme_vec[2], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2285:34] - node _T_1628 = bits(_T_1627, 0, 0) @[dec_tlu_ctl.scala 2285:62] - node _T_1629 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2285:91] - node _T_1630 = eq(mhpme_vec[2], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2286:34] - node _T_1631 = bits(_T_1630, 0, 0) @[dec_tlu_ctl.scala 2286:62] - node _T_1632 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2286:91] - node _T_1633 = eq(mhpme_vec[2], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2287:34] - node _T_1634 = bits(_T_1633, 0, 0) @[dec_tlu_ctl.scala 2287:62] - node _T_1635 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2287:91] - node _T_1636 = and(_T_1635, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2287:100] - node _T_1637 = eq(mhpme_vec[2], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2288:34] - node _T_1638 = bits(_T_1637, 0, 0) @[dec_tlu_ctl.scala 2288:62] - node _T_1639 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2288:91] - node _T_1640 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2288:142] - node _T_1641 = and(_T_1639, _T_1640) @[dec_tlu_ctl.scala 2288:101] - node _T_1642 = eq(mhpme_vec[2], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2289:34] - node _T_1643 = bits(_T_1642, 0, 0) @[dec_tlu_ctl.scala 2289:59] - node _T_1644 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2289:89] - node _T_1645 = eq(mhpme_vec[2], UInt<5>("h010")) @[dec_tlu_ctl.scala 2290:34] - node _T_1646 = bits(_T_1645, 0, 0) @[dec_tlu_ctl.scala 2290:59] - node _T_1647 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2290:89] - node _T_1648 = eq(mhpme_vec[2], UInt<5>("h012")) @[dec_tlu_ctl.scala 2291:34] - node _T_1649 = bits(_T_1648, 0, 0) @[dec_tlu_ctl.scala 2291:59] - node _T_1650 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2291:89] - node _T_1651 = eq(mhpme_vec[2], UInt<5>("h011")) @[dec_tlu_ctl.scala 2292:34] - node _T_1652 = bits(_T_1651, 0, 0) @[dec_tlu_ctl.scala 2292:59] - node _T_1653 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2292:89] - node _T_1654 = eq(mhpme_vec[2], UInt<5>("h013")) @[dec_tlu_ctl.scala 2293:34] - node _T_1655 = bits(_T_1654, 0, 0) @[dec_tlu_ctl.scala 2293:59] - node _T_1656 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2293:89] - node _T_1657 = eq(mhpme_vec[2], UInt<5>("h014")) @[dec_tlu_ctl.scala 2294:34] - node _T_1658 = bits(_T_1657, 0, 0) @[dec_tlu_ctl.scala 2294:59] - node _T_1659 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2294:89] - node _T_1660 = eq(mhpme_vec[2], UInt<5>("h015")) @[dec_tlu_ctl.scala 2295:34] - node _T_1661 = bits(_T_1660, 0, 0) @[dec_tlu_ctl.scala 2295:59] - node _T_1662 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2295:89] - node _T_1663 = eq(mhpme_vec[2], UInt<5>("h016")) @[dec_tlu_ctl.scala 2296:34] - node _T_1664 = bits(_T_1663, 0, 0) @[dec_tlu_ctl.scala 2296:59] - node _T_1665 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2296:89] - node _T_1666 = eq(mhpme_vec[2], UInt<5>("h017")) @[dec_tlu_ctl.scala 2297:34] - node _T_1667 = bits(_T_1666, 0, 0) @[dec_tlu_ctl.scala 2297:59] - node _T_1668 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2297:89] - node _T_1669 = eq(mhpme_vec[2], UInt<5>("h018")) @[dec_tlu_ctl.scala 2298:34] - node _T_1670 = bits(_T_1669, 0, 0) @[dec_tlu_ctl.scala 2298:59] - node _T_1671 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2298:89] - node _T_1672 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2298:122] - node _T_1673 = or(_T_1671, _T_1672) @[dec_tlu_ctl.scala 2298:101] - node _T_1674 = eq(mhpme_vec[2], UInt<5>("h019")) @[dec_tlu_ctl.scala 2299:34] - node _T_1675 = bits(_T_1674, 0, 0) @[dec_tlu_ctl.scala 2299:62] - node _T_1676 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2299:95] - node _T_1677 = eq(mhpme_vec[2], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2300:34] - node _T_1678 = bits(_T_1677, 0, 0) @[dec_tlu_ctl.scala 2300:62] - node _T_1679 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:97] - node _T_1680 = eq(mhpme_vec[2], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2301:34] - node _T_1681 = bits(_T_1680, 0, 0) @[dec_tlu_ctl.scala 2301:62] - node _T_1682 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2301:110] - node _T_1683 = eq(mhpme_vec[2], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2302:34] - node _T_1684 = bits(_T_1683, 0, 0) @[dec_tlu_ctl.scala 2302:62] - node _T_1685 = eq(mhpme_vec[2], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2303:34] - node _T_1686 = bits(_T_1685, 0, 0) @[dec_tlu_ctl.scala 2303:62] - node _T_1687 = eq(mhpme_vec[2], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2304:34] - node _T_1688 = bits(_T_1687, 0, 0) @[dec_tlu_ctl.scala 2304:62] - node _T_1689 = eq(mhpme_vec[2], UInt<6>("h020")) @[dec_tlu_ctl.scala 2305:34] - node _T_1690 = bits(_T_1689, 0, 0) @[dec_tlu_ctl.scala 2305:62] - node _T_1691 = eq(mhpme_vec[2], UInt<6>("h022")) @[dec_tlu_ctl.scala 2306:34] - node _T_1692 = bits(_T_1691, 0, 0) @[dec_tlu_ctl.scala 2306:62] - node _T_1693 = eq(mhpme_vec[2], UInt<6>("h023")) @[dec_tlu_ctl.scala 2307:34] - node _T_1694 = bits(_T_1693, 0, 0) @[dec_tlu_ctl.scala 2307:62] - node _T_1695 = eq(mhpme_vec[2], UInt<6>("h024")) @[dec_tlu_ctl.scala 2308:34] - node _T_1696 = bits(_T_1695, 0, 0) @[dec_tlu_ctl.scala 2308:62] - node _T_1697 = eq(mhpme_vec[2], UInt<6>("h025")) @[dec_tlu_ctl.scala 2309:34] - node _T_1698 = bits(_T_1697, 0, 0) @[dec_tlu_ctl.scala 2309:62] - node _T_1699 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2309:98] - node _T_1700 = or(_T_1699, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2309:120] - node _T_1701 = eq(mhpme_vec[2], UInt<6>("h026")) @[dec_tlu_ctl.scala 2310:34] - node _T_1702 = bits(_T_1701, 0, 0) @[dec_tlu_ctl.scala 2310:62] - node _T_1703 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2310:92] - node _T_1704 = or(_T_1703, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2310:117] - node _T_1705 = eq(mhpme_vec[2], UInt<6>("h027")) @[dec_tlu_ctl.scala 2311:34] - node _T_1706 = bits(_T_1705, 0, 0) @[dec_tlu_ctl.scala 2311:62] - node _T_1707 = eq(mhpme_vec[2], UInt<6>("h028")) @[dec_tlu_ctl.scala 2312:34] - node _T_1708 = bits(_T_1707, 0, 0) @[dec_tlu_ctl.scala 2312:62] - node _T_1709 = eq(mhpme_vec[2], UInt<6>("h029")) @[dec_tlu_ctl.scala 2313:34] - node _T_1710 = bits(_T_1709, 0, 0) @[dec_tlu_ctl.scala 2313:62] - node _T_1711 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2313:97] - node _T_1712 = and(_T_1711, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2313:129] - node _T_1713 = eq(mhpme_vec[2], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2314:34] - node _T_1714 = bits(_T_1713, 0, 0) @[dec_tlu_ctl.scala 2314:62] - node _T_1715 = eq(mhpme_vec[2], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2315:34] - node _T_1716 = bits(_T_1715, 0, 0) @[dec_tlu_ctl.scala 2315:62] - node _T_1717 = eq(mhpme_vec[2], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2316:34] - node _T_1718 = bits(_T_1717, 0, 0) @[dec_tlu_ctl.scala 2316:62] - node _T_1719 = eq(mhpme_vec[2], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2317:34] - node _T_1720 = bits(_T_1719, 0, 0) @[dec_tlu_ctl.scala 2317:62] - node _T_1721 = eq(mhpme_vec[2], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2318:34] - node _T_1722 = bits(_T_1721, 0, 0) @[dec_tlu_ctl.scala 2318:62] - node _T_1723 = eq(mhpme_vec[2], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2319:34] - node _T_1724 = bits(_T_1723, 0, 0) @[dec_tlu_ctl.scala 2319:62] - node _T_1725 = eq(mhpme_vec[2], UInt<6>("h030")) @[dec_tlu_ctl.scala 2320:34] - node _T_1726 = bits(_T_1725, 0, 0) @[dec_tlu_ctl.scala 2320:62] - node _T_1727 = eq(mhpme_vec[2], UInt<6>("h031")) @[dec_tlu_ctl.scala 2321:34] - node _T_1728 = bits(_T_1727, 0, 0) @[dec_tlu_ctl.scala 2321:62] - node _T_1729 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2321:84] - node _T_1730 = bits(_T_1729, 0, 0) @[dec_tlu_ctl.scala 2321:84] - node _T_1731 = not(_T_1730) @[dec_tlu_ctl.scala 2321:73] - node _T_1732 = eq(mhpme_vec[2], UInt<6>("h032")) @[dec_tlu_ctl.scala 2322:34] - node _T_1733 = bits(_T_1732, 0, 0) @[dec_tlu_ctl.scala 2322:62] - node _T_1734 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2322:84] - node _T_1735 = bits(_T_1734, 0, 0) @[dec_tlu_ctl.scala 2322:84] - node _T_1736 = not(_T_1735) @[dec_tlu_ctl.scala 2322:73] - node _T_1737 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2322:107] - node _T_1738 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2322:118] - node _T_1739 = and(_T_1737, _T_1738) @[dec_tlu_ctl.scala 2322:113] - node _T_1740 = orr(_T_1739) @[dec_tlu_ctl.scala 2322:125] - node _T_1741 = and(_T_1736, _T_1740) @[dec_tlu_ctl.scala 2322:98] - node _T_1742 = eq(mhpme_vec[2], UInt<6>("h036")) @[dec_tlu_ctl.scala 2323:34] - node _T_1743 = bits(_T_1742, 0, 0) @[dec_tlu_ctl.scala 2323:62] - node _T_1744 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2323:91] - node _T_1745 = eq(mhpme_vec[2], UInt<6>("h037")) @[dec_tlu_ctl.scala 2324:34] - node _T_1746 = bits(_T_1745, 0, 0) @[dec_tlu_ctl.scala 2324:62] - node _T_1747 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2324:94] - node _T_1748 = eq(mhpme_vec[2], UInt<6>("h038")) @[dec_tlu_ctl.scala 2325:34] - node _T_1749 = bits(_T_1748, 0, 0) @[dec_tlu_ctl.scala 2325:62] - node _T_1750 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2325:94] - node _T_1751 = eq(mhpme_vec[2], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2327:34] - node _T_1752 = bits(_T_1751, 0, 0) @[dec_tlu_ctl.scala 2327:62] - node _T_1753 = eq(mhpme_vec[2], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2328:34] - node _T_1754 = bits(_T_1753, 0, 0) @[dec_tlu_ctl.scala 2328:62] - node _T_1755 = eq(mhpme_vec[2], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2329:34] - node _T_1756 = bits(_T_1755, 0, 0) @[dec_tlu_ctl.scala 2329:62] - node _T_1757 = eq(mhpme_vec[2], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2330:34] - node _T_1758 = bits(_T_1757, 0, 0) @[dec_tlu_ctl.scala 2330:62] - node _T_1759 = eq(mhpme_vec[2], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2331:34] - node _T_1760 = bits(_T_1759, 0, 0) @[dec_tlu_ctl.scala 2331:62] - node _T_1761 = mux(_T_1595, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1762 = mux(_T_1597, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1763 = mux(_T_1599, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1764 = mux(_T_1601, _T_1603, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1765 = mux(_T_1605, _T_1609, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1766 = mux(_T_1611, _T_1614, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1767 = mux(_T_1616, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1768 = mux(_T_1618, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1769 = mux(_T_1620, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1770 = mux(_T_1622, _T_1623, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1771 = mux(_T_1625, _T_1626, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1772 = mux(_T_1628, _T_1629, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1773 = mux(_T_1631, _T_1632, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1774 = mux(_T_1634, _T_1636, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1775 = mux(_T_1638, _T_1641, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1776 = mux(_T_1643, _T_1644, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1777 = mux(_T_1646, _T_1647, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1778 = mux(_T_1649, _T_1650, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1779 = mux(_T_1652, _T_1653, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1780 = mux(_T_1655, _T_1656, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1781 = mux(_T_1658, _T_1659, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1782 = mux(_T_1661, _T_1662, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1783 = mux(_T_1664, _T_1665, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1784 = mux(_T_1667, _T_1668, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1785 = mux(_T_1670, _T_1673, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1786 = mux(_T_1675, _T_1676, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1787 = mux(_T_1678, _T_1679, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1788 = mux(_T_1681, _T_1682, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1789 = mux(_T_1684, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1790 = mux(_T_1686, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1791 = mux(_T_1688, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1792 = mux(_T_1690, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1793 = mux(_T_1692, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1794 = mux(_T_1694, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1795 = mux(_T_1696, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1796 = mux(_T_1698, _T_1700, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1797 = mux(_T_1702, _T_1704, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1798 = mux(_T_1706, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1799 = mux(_T_1708, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1800 = mux(_T_1710, _T_1712, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1801 = mux(_T_1714, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1802 = mux(_T_1716, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1803 = mux(_T_1718, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1804 = mux(_T_1720, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1805 = mux(_T_1722, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1806 = mux(_T_1724, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1807 = mux(_T_1726, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1808 = mux(_T_1728, _T_1731, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1809 = mux(_T_1733, _T_1741, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1810 = mux(_T_1743, _T_1744, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1811 = mux(_T_1746, _T_1747, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1812 = mux(_T_1749, _T_1750, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1813 = mux(_T_1752, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1814 = mux(_T_1754, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1815 = mux(_T_1756, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1816 = mux(_T_1758, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1817 = mux(_T_1760, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_1818 = or(_T_1761, _T_1762) @[Mux.scala 27:72] - node _T_1819 = or(_T_1818, _T_1763) @[Mux.scala 27:72] + node _T_1590 = or(_T_1589, _T_1534) @[Mux.scala 27:72] + wire _T_1591 : UInt<1> @[Mux.scala 27:72] + _T_1591 <= _T_1590 @[Mux.scala 27:72] + node _T_1592 = and(_T_1310, _T_1591) @[dec_tlu_ctl.scala 2273:44] + mhpmc_inc_r[1] <= _T_1592 @[dec_tlu_ctl.scala 2273:19] + node _T_1593 = bits(mcountinhibit, 5, 5) @[dec_tlu_ctl.scala 2273:38] + node _T_1594 = not(_T_1593) @[dec_tlu_ctl.scala 2273:24] + node _T_1595 = eq(mhpme_vec[2], UInt<1>("h01")) @[dec_tlu_ctl.scala 2274:34] + node _T_1596 = bits(_T_1595, 0, 0) @[dec_tlu_ctl.scala 2274:62] + node _T_1597 = eq(mhpme_vec[2], UInt<2>("h02")) @[dec_tlu_ctl.scala 2275:34] + node _T_1598 = bits(_T_1597, 0, 0) @[dec_tlu_ctl.scala 2275:62] + node _T_1599 = eq(mhpme_vec[2], UInt<2>("h03")) @[dec_tlu_ctl.scala 2276:34] + node _T_1600 = bits(_T_1599, 0, 0) @[dec_tlu_ctl.scala 2276:62] + node _T_1601 = eq(mhpme_vec[2], UInt<3>("h04")) @[dec_tlu_ctl.scala 2277:34] + node _T_1602 = bits(_T_1601, 0, 0) @[dec_tlu_ctl.scala 2277:62] + node _T_1603 = not(io.illegal_r) @[dec_tlu_ctl.scala 2277:96] + node _T_1604 = and(io.tlu_i0_commit_cmt, _T_1603) @[dec_tlu_ctl.scala 2277:94] + node _T_1605 = eq(mhpme_vec[2], UInt<3>("h05")) @[dec_tlu_ctl.scala 2278:34] + node _T_1606 = bits(_T_1605, 0, 0) @[dec_tlu_ctl.scala 2278:62] + node _T_1607 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2278:96] + node _T_1608 = and(io.tlu_i0_commit_cmt, _T_1607) @[dec_tlu_ctl.scala 2278:94] + node _T_1609 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:117] + node _T_1610 = and(_T_1608, _T_1609) @[dec_tlu_ctl.scala 2278:115] + node _T_1611 = eq(mhpme_vec[2], UInt<3>("h06")) @[dec_tlu_ctl.scala 2279:34] + node _T_1612 = bits(_T_1611, 0, 0) @[dec_tlu_ctl.scala 2279:62] + node _T_1613 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2279:94] + node _T_1614 = not(io.illegal_r) @[dec_tlu_ctl.scala 2279:117] + node _T_1615 = and(_T_1613, _T_1614) @[dec_tlu_ctl.scala 2279:115] + node _T_1616 = eq(mhpme_vec[2], UInt<3>("h07")) @[dec_tlu_ctl.scala 2280:34] + node _T_1617 = bits(_T_1616, 0, 0) @[dec_tlu_ctl.scala 2280:62] + node _T_1618 = eq(mhpme_vec[2], UInt<4>("h08")) @[dec_tlu_ctl.scala 2281:34] + node _T_1619 = bits(_T_1618, 0, 0) @[dec_tlu_ctl.scala 2281:62] + node _T_1620 = eq(mhpme_vec[2], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2282:34] + node _T_1621 = bits(_T_1620, 0, 0) @[dec_tlu_ctl.scala 2282:62] + node _T_1622 = eq(mhpme_vec[2], UInt<4>("h09")) @[dec_tlu_ctl.scala 2283:34] + node _T_1623 = bits(_T_1622, 0, 0) @[dec_tlu_ctl.scala 2283:62] + node _T_1624 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2283:91] + node _T_1625 = eq(mhpme_vec[2], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2284:34] + node _T_1626 = bits(_T_1625, 0, 0) @[dec_tlu_ctl.scala 2284:62] + node _T_1627 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2284:105] + node _T_1628 = eq(mhpme_vec[2], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2285:34] + node _T_1629 = bits(_T_1628, 0, 0) @[dec_tlu_ctl.scala 2285:62] + node _T_1630 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2285:91] + node _T_1631 = eq(mhpme_vec[2], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2286:34] + node _T_1632 = bits(_T_1631, 0, 0) @[dec_tlu_ctl.scala 2286:62] + node _T_1633 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2286:91] + node _T_1634 = eq(mhpme_vec[2], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2287:34] + node _T_1635 = bits(_T_1634, 0, 0) @[dec_tlu_ctl.scala 2287:62] + node _T_1636 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2287:91] + node _T_1637 = and(_T_1636, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2287:100] + node _T_1638 = eq(mhpme_vec[2], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2288:34] + node _T_1639 = bits(_T_1638, 0, 0) @[dec_tlu_ctl.scala 2288:62] + node _T_1640 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2288:91] + node _T_1641 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2288:142] + node _T_1642 = and(_T_1640, _T_1641) @[dec_tlu_ctl.scala 2288:101] + node _T_1643 = eq(mhpme_vec[2], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2289:34] + node _T_1644 = bits(_T_1643, 0, 0) @[dec_tlu_ctl.scala 2289:59] + node _T_1645 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2289:89] + node _T_1646 = eq(mhpme_vec[2], UInt<5>("h010")) @[dec_tlu_ctl.scala 2290:34] + node _T_1647 = bits(_T_1646, 0, 0) @[dec_tlu_ctl.scala 2290:59] + node _T_1648 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2290:89] + node _T_1649 = eq(mhpme_vec[2], UInt<5>("h012")) @[dec_tlu_ctl.scala 2291:34] + node _T_1650 = bits(_T_1649, 0, 0) @[dec_tlu_ctl.scala 2291:59] + node _T_1651 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2291:89] + node _T_1652 = eq(mhpme_vec[2], UInt<5>("h011")) @[dec_tlu_ctl.scala 2292:34] + node _T_1653 = bits(_T_1652, 0, 0) @[dec_tlu_ctl.scala 2292:59] + node _T_1654 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2292:89] + node _T_1655 = eq(mhpme_vec[2], UInt<5>("h013")) @[dec_tlu_ctl.scala 2293:34] + node _T_1656 = bits(_T_1655, 0, 0) @[dec_tlu_ctl.scala 2293:59] + node _T_1657 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2293:89] + node _T_1658 = eq(mhpme_vec[2], UInt<5>("h014")) @[dec_tlu_ctl.scala 2294:34] + node _T_1659 = bits(_T_1658, 0, 0) @[dec_tlu_ctl.scala 2294:59] + node _T_1660 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2294:89] + node _T_1661 = eq(mhpme_vec[2], UInt<5>("h015")) @[dec_tlu_ctl.scala 2295:34] + node _T_1662 = bits(_T_1661, 0, 0) @[dec_tlu_ctl.scala 2295:59] + node _T_1663 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2295:89] + node _T_1664 = eq(mhpme_vec[2], UInt<5>("h016")) @[dec_tlu_ctl.scala 2296:34] + node _T_1665 = bits(_T_1664, 0, 0) @[dec_tlu_ctl.scala 2296:59] + node _T_1666 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2296:89] + node _T_1667 = eq(mhpme_vec[2], UInt<5>("h017")) @[dec_tlu_ctl.scala 2297:34] + node _T_1668 = bits(_T_1667, 0, 0) @[dec_tlu_ctl.scala 2297:59] + node _T_1669 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2297:89] + node _T_1670 = eq(mhpme_vec[2], UInt<5>("h018")) @[dec_tlu_ctl.scala 2298:34] + node _T_1671 = bits(_T_1670, 0, 0) @[dec_tlu_ctl.scala 2298:59] + node _T_1672 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2298:89] + node _T_1673 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2298:122] + node _T_1674 = or(_T_1672, _T_1673) @[dec_tlu_ctl.scala 2298:101] + node _T_1675 = eq(mhpme_vec[2], UInt<5>("h019")) @[dec_tlu_ctl.scala 2299:34] + node _T_1676 = bits(_T_1675, 0, 0) @[dec_tlu_ctl.scala 2299:62] + node _T_1677 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2299:95] + node _T_1678 = eq(mhpme_vec[2], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2300:34] + node _T_1679 = bits(_T_1678, 0, 0) @[dec_tlu_ctl.scala 2300:62] + node _T_1680 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:97] + node _T_1681 = eq(mhpme_vec[2], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2301:34] + node _T_1682 = bits(_T_1681, 0, 0) @[dec_tlu_ctl.scala 2301:62] + node _T_1683 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2301:110] + node _T_1684 = eq(mhpme_vec[2], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2302:34] + node _T_1685 = bits(_T_1684, 0, 0) @[dec_tlu_ctl.scala 2302:62] + node _T_1686 = eq(mhpme_vec[2], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2303:34] + node _T_1687 = bits(_T_1686, 0, 0) @[dec_tlu_ctl.scala 2303:62] + node _T_1688 = eq(mhpme_vec[2], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2304:34] + node _T_1689 = bits(_T_1688, 0, 0) @[dec_tlu_ctl.scala 2304:62] + node _T_1690 = eq(mhpme_vec[2], UInt<6>("h020")) @[dec_tlu_ctl.scala 2305:34] + node _T_1691 = bits(_T_1690, 0, 0) @[dec_tlu_ctl.scala 2305:62] + node _T_1692 = eq(mhpme_vec[2], UInt<6>("h022")) @[dec_tlu_ctl.scala 2306:34] + node _T_1693 = bits(_T_1692, 0, 0) @[dec_tlu_ctl.scala 2306:62] + node _T_1694 = eq(mhpme_vec[2], UInt<6>("h023")) @[dec_tlu_ctl.scala 2307:34] + node _T_1695 = bits(_T_1694, 0, 0) @[dec_tlu_ctl.scala 2307:62] + node _T_1696 = eq(mhpme_vec[2], UInt<6>("h024")) @[dec_tlu_ctl.scala 2308:34] + node _T_1697 = bits(_T_1696, 0, 0) @[dec_tlu_ctl.scala 2308:62] + node _T_1698 = eq(mhpme_vec[2], UInt<6>("h025")) @[dec_tlu_ctl.scala 2309:34] + node _T_1699 = bits(_T_1698, 0, 0) @[dec_tlu_ctl.scala 2309:62] + node _T_1700 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2309:98] + node _T_1701 = or(_T_1700, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2309:120] + node _T_1702 = eq(mhpme_vec[2], UInt<6>("h026")) @[dec_tlu_ctl.scala 2310:34] + node _T_1703 = bits(_T_1702, 0, 0) @[dec_tlu_ctl.scala 2310:62] + node _T_1704 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2310:92] + node _T_1705 = or(_T_1704, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2310:117] + node _T_1706 = eq(mhpme_vec[2], UInt<6>("h027")) @[dec_tlu_ctl.scala 2311:34] + node _T_1707 = bits(_T_1706, 0, 0) @[dec_tlu_ctl.scala 2311:62] + node _T_1708 = eq(mhpme_vec[2], UInt<6>("h028")) @[dec_tlu_ctl.scala 2312:34] + node _T_1709 = bits(_T_1708, 0, 0) @[dec_tlu_ctl.scala 2312:62] + node _T_1710 = eq(mhpme_vec[2], UInt<6>("h029")) @[dec_tlu_ctl.scala 2313:34] + node _T_1711 = bits(_T_1710, 0, 0) @[dec_tlu_ctl.scala 2313:62] + node _T_1712 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2313:97] + node _T_1713 = and(_T_1712, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2313:129] + node _T_1714 = eq(mhpme_vec[2], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2314:34] + node _T_1715 = bits(_T_1714, 0, 0) @[dec_tlu_ctl.scala 2314:62] + node _T_1716 = eq(mhpme_vec[2], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2315:34] + node _T_1717 = bits(_T_1716, 0, 0) @[dec_tlu_ctl.scala 2315:62] + node _T_1718 = eq(mhpme_vec[2], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2316:34] + node _T_1719 = bits(_T_1718, 0, 0) @[dec_tlu_ctl.scala 2316:62] + node _T_1720 = eq(mhpme_vec[2], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2317:34] + node _T_1721 = bits(_T_1720, 0, 0) @[dec_tlu_ctl.scala 2317:62] + node _T_1722 = eq(mhpme_vec[2], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2318:34] + node _T_1723 = bits(_T_1722, 0, 0) @[dec_tlu_ctl.scala 2318:62] + node _T_1724 = eq(mhpme_vec[2], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2319:34] + node _T_1725 = bits(_T_1724, 0, 0) @[dec_tlu_ctl.scala 2319:62] + node _T_1726 = eq(mhpme_vec[2], UInt<6>("h030")) @[dec_tlu_ctl.scala 2320:34] + node _T_1727 = bits(_T_1726, 0, 0) @[dec_tlu_ctl.scala 2320:62] + node _T_1728 = eq(mhpme_vec[2], UInt<6>("h031")) @[dec_tlu_ctl.scala 2321:34] + node _T_1729 = bits(_T_1728, 0, 0) @[dec_tlu_ctl.scala 2321:62] + node _T_1730 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2321:84] + node _T_1731 = bits(_T_1730, 0, 0) @[dec_tlu_ctl.scala 2321:84] + node _T_1732 = not(_T_1731) @[dec_tlu_ctl.scala 2321:73] + node _T_1733 = eq(mhpme_vec[2], UInt<6>("h032")) @[dec_tlu_ctl.scala 2322:34] + node _T_1734 = bits(_T_1733, 0, 0) @[dec_tlu_ctl.scala 2322:62] + node _T_1735 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2322:84] + node _T_1736 = bits(_T_1735, 0, 0) @[dec_tlu_ctl.scala 2322:84] + node _T_1737 = not(_T_1736) @[dec_tlu_ctl.scala 2322:73] + node _T_1738 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2322:107] + node _T_1739 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2322:118] + node _T_1740 = and(_T_1738, _T_1739) @[dec_tlu_ctl.scala 2322:113] + node _T_1741 = orr(_T_1740) @[dec_tlu_ctl.scala 2322:125] + node _T_1742 = and(_T_1737, _T_1741) @[dec_tlu_ctl.scala 2322:98] + node _T_1743 = eq(mhpme_vec[2], UInt<6>("h036")) @[dec_tlu_ctl.scala 2323:34] + node _T_1744 = bits(_T_1743, 0, 0) @[dec_tlu_ctl.scala 2323:62] + node _T_1745 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2323:91] + node _T_1746 = eq(mhpme_vec[2], UInt<6>("h037")) @[dec_tlu_ctl.scala 2324:34] + node _T_1747 = bits(_T_1746, 0, 0) @[dec_tlu_ctl.scala 2324:62] + node _T_1748 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2324:94] + node _T_1749 = eq(mhpme_vec[2], UInt<6>("h038")) @[dec_tlu_ctl.scala 2325:34] + node _T_1750 = bits(_T_1749, 0, 0) @[dec_tlu_ctl.scala 2325:62] + node _T_1751 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2325:94] + node _T_1752 = eq(mhpme_vec[2], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2327:34] + node _T_1753 = bits(_T_1752, 0, 0) @[dec_tlu_ctl.scala 2327:62] + node _T_1754 = eq(mhpme_vec[2], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2328:34] + node _T_1755 = bits(_T_1754, 0, 0) @[dec_tlu_ctl.scala 2328:62] + node _T_1756 = eq(mhpme_vec[2], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2329:34] + node _T_1757 = bits(_T_1756, 0, 0) @[dec_tlu_ctl.scala 2329:62] + node _T_1758 = eq(mhpme_vec[2], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2330:34] + node _T_1759 = bits(_T_1758, 0, 0) @[dec_tlu_ctl.scala 2330:62] + node _T_1760 = eq(mhpme_vec[2], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2331:34] + node _T_1761 = bits(_T_1760, 0, 0) @[dec_tlu_ctl.scala 2331:62] + node _T_1762 = mux(_T_1596, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1763 = mux(_T_1598, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1764 = mux(_T_1600, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1765 = mux(_T_1602, _T_1604, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1766 = mux(_T_1606, _T_1610, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1767 = mux(_T_1612, _T_1615, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1768 = mux(_T_1617, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1769 = mux(_T_1619, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1770 = mux(_T_1621, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1771 = mux(_T_1623, _T_1624, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1772 = mux(_T_1626, _T_1627, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1773 = mux(_T_1629, _T_1630, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1774 = mux(_T_1632, _T_1633, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1775 = mux(_T_1635, _T_1637, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1776 = mux(_T_1639, _T_1642, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1777 = mux(_T_1644, _T_1645, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1778 = mux(_T_1647, _T_1648, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1779 = mux(_T_1650, _T_1651, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1780 = mux(_T_1653, _T_1654, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1781 = mux(_T_1656, _T_1657, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1782 = mux(_T_1659, _T_1660, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1783 = mux(_T_1662, _T_1663, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1784 = mux(_T_1665, _T_1666, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1785 = mux(_T_1668, _T_1669, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1786 = mux(_T_1671, _T_1674, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1787 = mux(_T_1676, _T_1677, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1788 = mux(_T_1679, _T_1680, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1789 = mux(_T_1682, _T_1683, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1790 = mux(_T_1685, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1791 = mux(_T_1687, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1792 = mux(_T_1689, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1793 = mux(_T_1691, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1794 = mux(_T_1693, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1795 = mux(_T_1695, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1796 = mux(_T_1697, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1797 = mux(_T_1699, _T_1701, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1798 = mux(_T_1703, _T_1705, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1799 = mux(_T_1707, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1800 = mux(_T_1709, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1801 = mux(_T_1711, _T_1713, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1802 = mux(_T_1715, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1803 = mux(_T_1717, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1804 = mux(_T_1719, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1805 = mux(_T_1721, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1806 = mux(_T_1723, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1807 = mux(_T_1725, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1808 = mux(_T_1727, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1809 = mux(_T_1729, _T_1732, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1810 = mux(_T_1734, _T_1742, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1811 = mux(_T_1744, _T_1745, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1812 = mux(_T_1747, _T_1748, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1813 = mux(_T_1750, _T_1751, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1814 = mux(_T_1753, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1815 = mux(_T_1755, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1816 = mux(_T_1757, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1817 = mux(_T_1759, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1818 = mux(_T_1761, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1819 = or(_T_1762, _T_1763) @[Mux.scala 27:72] node _T_1820 = or(_T_1819, _T_1764) @[Mux.scala 27:72] node _T_1821 = or(_T_1820, _T_1765) @[Mux.scala 27:72] node _T_1822 = or(_T_1821, _T_1766) @[Mux.scala 27:72] @@ -75261,238 +75269,238 @@ circuit quasar_wrapper : node _T_1871 = or(_T_1870, _T_1815) @[Mux.scala 27:72] node _T_1872 = or(_T_1871, _T_1816) @[Mux.scala 27:72] node _T_1873 = or(_T_1872, _T_1817) @[Mux.scala 27:72] - wire _T_1874 : UInt<1> @[Mux.scala 27:72] - _T_1874 <= _T_1873 @[Mux.scala 27:72] - node _T_1875 = and(_T_1593, _T_1874) @[dec_tlu_ctl.scala 2273:44] - mhpmc_inc_r[2] <= _T_1875 @[dec_tlu_ctl.scala 2273:19] - node _T_1876 = bits(mcountinhibit, 6, 6) @[dec_tlu_ctl.scala 2273:38] - node _T_1877 = not(_T_1876) @[dec_tlu_ctl.scala 2273:24] - node _T_1878 = eq(mhpme_vec[3], UInt<1>("h01")) @[dec_tlu_ctl.scala 2274:34] - node _T_1879 = bits(_T_1878, 0, 0) @[dec_tlu_ctl.scala 2274:62] - node _T_1880 = eq(mhpme_vec[3], UInt<2>("h02")) @[dec_tlu_ctl.scala 2275:34] - node _T_1881 = bits(_T_1880, 0, 0) @[dec_tlu_ctl.scala 2275:62] - node _T_1882 = eq(mhpme_vec[3], UInt<2>("h03")) @[dec_tlu_ctl.scala 2276:34] - node _T_1883 = bits(_T_1882, 0, 0) @[dec_tlu_ctl.scala 2276:62] - node _T_1884 = eq(mhpme_vec[3], UInt<3>("h04")) @[dec_tlu_ctl.scala 2277:34] - node _T_1885 = bits(_T_1884, 0, 0) @[dec_tlu_ctl.scala 2277:62] - node _T_1886 = not(io.illegal_r) @[dec_tlu_ctl.scala 2277:96] - node _T_1887 = and(io.tlu_i0_commit_cmt, _T_1886) @[dec_tlu_ctl.scala 2277:94] - node _T_1888 = eq(mhpme_vec[3], UInt<3>("h05")) @[dec_tlu_ctl.scala 2278:34] - node _T_1889 = bits(_T_1888, 0, 0) @[dec_tlu_ctl.scala 2278:62] - node _T_1890 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2278:96] - node _T_1891 = and(io.tlu_i0_commit_cmt, _T_1890) @[dec_tlu_ctl.scala 2278:94] - node _T_1892 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:117] - node _T_1893 = and(_T_1891, _T_1892) @[dec_tlu_ctl.scala 2278:115] - node _T_1894 = eq(mhpme_vec[3], UInt<3>("h06")) @[dec_tlu_ctl.scala 2279:34] - node _T_1895 = bits(_T_1894, 0, 0) @[dec_tlu_ctl.scala 2279:62] - node _T_1896 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2279:94] - node _T_1897 = not(io.illegal_r) @[dec_tlu_ctl.scala 2279:117] - node _T_1898 = and(_T_1896, _T_1897) @[dec_tlu_ctl.scala 2279:115] - node _T_1899 = eq(mhpme_vec[3], UInt<3>("h07")) @[dec_tlu_ctl.scala 2280:34] - node _T_1900 = bits(_T_1899, 0, 0) @[dec_tlu_ctl.scala 2280:62] - node _T_1901 = eq(mhpme_vec[3], UInt<4>("h08")) @[dec_tlu_ctl.scala 2281:34] - node _T_1902 = bits(_T_1901, 0, 0) @[dec_tlu_ctl.scala 2281:62] - node _T_1903 = eq(mhpme_vec[3], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2282:34] - node _T_1904 = bits(_T_1903, 0, 0) @[dec_tlu_ctl.scala 2282:62] - node _T_1905 = eq(mhpme_vec[3], UInt<4>("h09")) @[dec_tlu_ctl.scala 2283:34] - node _T_1906 = bits(_T_1905, 0, 0) @[dec_tlu_ctl.scala 2283:62] - node _T_1907 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2283:91] - node _T_1908 = eq(mhpme_vec[3], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2284:34] - node _T_1909 = bits(_T_1908, 0, 0) @[dec_tlu_ctl.scala 2284:62] - node _T_1910 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2284:105] - node _T_1911 = eq(mhpme_vec[3], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2285:34] - node _T_1912 = bits(_T_1911, 0, 0) @[dec_tlu_ctl.scala 2285:62] - node _T_1913 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2285:91] - node _T_1914 = eq(mhpme_vec[3], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2286:34] - node _T_1915 = bits(_T_1914, 0, 0) @[dec_tlu_ctl.scala 2286:62] - node _T_1916 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2286:91] - node _T_1917 = eq(mhpme_vec[3], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2287:34] - node _T_1918 = bits(_T_1917, 0, 0) @[dec_tlu_ctl.scala 2287:62] - node _T_1919 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2287:91] - node _T_1920 = and(_T_1919, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2287:100] - node _T_1921 = eq(mhpme_vec[3], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2288:34] - node _T_1922 = bits(_T_1921, 0, 0) @[dec_tlu_ctl.scala 2288:62] - node _T_1923 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2288:91] - node _T_1924 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2288:142] - node _T_1925 = and(_T_1923, _T_1924) @[dec_tlu_ctl.scala 2288:101] - node _T_1926 = eq(mhpme_vec[3], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2289:34] - node _T_1927 = bits(_T_1926, 0, 0) @[dec_tlu_ctl.scala 2289:59] - node _T_1928 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2289:89] - node _T_1929 = eq(mhpme_vec[3], UInt<5>("h010")) @[dec_tlu_ctl.scala 2290:34] - node _T_1930 = bits(_T_1929, 0, 0) @[dec_tlu_ctl.scala 2290:59] - node _T_1931 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2290:89] - node _T_1932 = eq(mhpme_vec[3], UInt<5>("h012")) @[dec_tlu_ctl.scala 2291:34] - node _T_1933 = bits(_T_1932, 0, 0) @[dec_tlu_ctl.scala 2291:59] - node _T_1934 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2291:89] - node _T_1935 = eq(mhpme_vec[3], UInt<5>("h011")) @[dec_tlu_ctl.scala 2292:34] - node _T_1936 = bits(_T_1935, 0, 0) @[dec_tlu_ctl.scala 2292:59] - node _T_1937 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2292:89] - node _T_1938 = eq(mhpme_vec[3], UInt<5>("h013")) @[dec_tlu_ctl.scala 2293:34] - node _T_1939 = bits(_T_1938, 0, 0) @[dec_tlu_ctl.scala 2293:59] - node _T_1940 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2293:89] - node _T_1941 = eq(mhpme_vec[3], UInt<5>("h014")) @[dec_tlu_ctl.scala 2294:34] - node _T_1942 = bits(_T_1941, 0, 0) @[dec_tlu_ctl.scala 2294:59] - node _T_1943 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2294:89] - node _T_1944 = eq(mhpme_vec[3], UInt<5>("h015")) @[dec_tlu_ctl.scala 2295:34] - node _T_1945 = bits(_T_1944, 0, 0) @[dec_tlu_ctl.scala 2295:59] - node _T_1946 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2295:89] - node _T_1947 = eq(mhpme_vec[3], UInt<5>("h016")) @[dec_tlu_ctl.scala 2296:34] - node _T_1948 = bits(_T_1947, 0, 0) @[dec_tlu_ctl.scala 2296:59] - node _T_1949 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2296:89] - node _T_1950 = eq(mhpme_vec[3], UInt<5>("h017")) @[dec_tlu_ctl.scala 2297:34] - node _T_1951 = bits(_T_1950, 0, 0) @[dec_tlu_ctl.scala 2297:59] - node _T_1952 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2297:89] - node _T_1953 = eq(mhpme_vec[3], UInt<5>("h018")) @[dec_tlu_ctl.scala 2298:34] - node _T_1954 = bits(_T_1953, 0, 0) @[dec_tlu_ctl.scala 2298:59] - node _T_1955 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2298:89] - node _T_1956 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2298:122] - node _T_1957 = or(_T_1955, _T_1956) @[dec_tlu_ctl.scala 2298:101] - node _T_1958 = eq(mhpme_vec[3], UInt<5>("h019")) @[dec_tlu_ctl.scala 2299:34] - node _T_1959 = bits(_T_1958, 0, 0) @[dec_tlu_ctl.scala 2299:62] - node _T_1960 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2299:95] - node _T_1961 = eq(mhpme_vec[3], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2300:34] - node _T_1962 = bits(_T_1961, 0, 0) @[dec_tlu_ctl.scala 2300:62] - node _T_1963 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:97] - node _T_1964 = eq(mhpme_vec[3], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2301:34] - node _T_1965 = bits(_T_1964, 0, 0) @[dec_tlu_ctl.scala 2301:62] - node _T_1966 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2301:110] - node _T_1967 = eq(mhpme_vec[3], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2302:34] - node _T_1968 = bits(_T_1967, 0, 0) @[dec_tlu_ctl.scala 2302:62] - node _T_1969 = eq(mhpme_vec[3], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2303:34] - node _T_1970 = bits(_T_1969, 0, 0) @[dec_tlu_ctl.scala 2303:62] - node _T_1971 = eq(mhpme_vec[3], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2304:34] - node _T_1972 = bits(_T_1971, 0, 0) @[dec_tlu_ctl.scala 2304:62] - node _T_1973 = eq(mhpme_vec[3], UInt<6>("h020")) @[dec_tlu_ctl.scala 2305:34] - node _T_1974 = bits(_T_1973, 0, 0) @[dec_tlu_ctl.scala 2305:62] - node _T_1975 = eq(mhpme_vec[3], UInt<6>("h022")) @[dec_tlu_ctl.scala 2306:34] - node _T_1976 = bits(_T_1975, 0, 0) @[dec_tlu_ctl.scala 2306:62] - node _T_1977 = eq(mhpme_vec[3], UInt<6>("h023")) @[dec_tlu_ctl.scala 2307:34] - node _T_1978 = bits(_T_1977, 0, 0) @[dec_tlu_ctl.scala 2307:62] - node _T_1979 = eq(mhpme_vec[3], UInt<6>("h024")) @[dec_tlu_ctl.scala 2308:34] - node _T_1980 = bits(_T_1979, 0, 0) @[dec_tlu_ctl.scala 2308:62] - node _T_1981 = eq(mhpme_vec[3], UInt<6>("h025")) @[dec_tlu_ctl.scala 2309:34] - node _T_1982 = bits(_T_1981, 0, 0) @[dec_tlu_ctl.scala 2309:62] - node _T_1983 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2309:98] - node _T_1984 = or(_T_1983, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2309:120] - node _T_1985 = eq(mhpme_vec[3], UInt<6>("h026")) @[dec_tlu_ctl.scala 2310:34] - node _T_1986 = bits(_T_1985, 0, 0) @[dec_tlu_ctl.scala 2310:62] - node _T_1987 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2310:92] - node _T_1988 = or(_T_1987, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2310:117] - node _T_1989 = eq(mhpme_vec[3], UInt<6>("h027")) @[dec_tlu_ctl.scala 2311:34] - node _T_1990 = bits(_T_1989, 0, 0) @[dec_tlu_ctl.scala 2311:62] - node _T_1991 = eq(mhpme_vec[3], UInt<6>("h028")) @[dec_tlu_ctl.scala 2312:34] - node _T_1992 = bits(_T_1991, 0, 0) @[dec_tlu_ctl.scala 2312:62] - node _T_1993 = eq(mhpme_vec[3], UInt<6>("h029")) @[dec_tlu_ctl.scala 2313:34] - node _T_1994 = bits(_T_1993, 0, 0) @[dec_tlu_ctl.scala 2313:62] - node _T_1995 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2313:97] - node _T_1996 = and(_T_1995, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2313:129] - node _T_1997 = eq(mhpme_vec[3], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2314:34] - node _T_1998 = bits(_T_1997, 0, 0) @[dec_tlu_ctl.scala 2314:62] - node _T_1999 = eq(mhpme_vec[3], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2315:34] - node _T_2000 = bits(_T_1999, 0, 0) @[dec_tlu_ctl.scala 2315:62] - node _T_2001 = eq(mhpme_vec[3], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2316:34] - node _T_2002 = bits(_T_2001, 0, 0) @[dec_tlu_ctl.scala 2316:62] - node _T_2003 = eq(mhpme_vec[3], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2317:34] - node _T_2004 = bits(_T_2003, 0, 0) @[dec_tlu_ctl.scala 2317:62] - node _T_2005 = eq(mhpme_vec[3], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2318:34] - node _T_2006 = bits(_T_2005, 0, 0) @[dec_tlu_ctl.scala 2318:62] - node _T_2007 = eq(mhpme_vec[3], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2319:34] - node _T_2008 = bits(_T_2007, 0, 0) @[dec_tlu_ctl.scala 2319:62] - node _T_2009 = eq(mhpme_vec[3], UInt<6>("h030")) @[dec_tlu_ctl.scala 2320:34] - node _T_2010 = bits(_T_2009, 0, 0) @[dec_tlu_ctl.scala 2320:62] - node _T_2011 = eq(mhpme_vec[3], UInt<6>("h031")) @[dec_tlu_ctl.scala 2321:34] - node _T_2012 = bits(_T_2011, 0, 0) @[dec_tlu_ctl.scala 2321:62] - node _T_2013 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2321:84] - node _T_2014 = bits(_T_2013, 0, 0) @[dec_tlu_ctl.scala 2321:84] - node _T_2015 = not(_T_2014) @[dec_tlu_ctl.scala 2321:73] - node _T_2016 = eq(mhpme_vec[3], UInt<6>("h032")) @[dec_tlu_ctl.scala 2322:34] - node _T_2017 = bits(_T_2016, 0, 0) @[dec_tlu_ctl.scala 2322:62] - node _T_2018 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2322:84] - node _T_2019 = bits(_T_2018, 0, 0) @[dec_tlu_ctl.scala 2322:84] - node _T_2020 = not(_T_2019) @[dec_tlu_ctl.scala 2322:73] - node _T_2021 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2322:107] - node _T_2022 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2322:118] - node _T_2023 = and(_T_2021, _T_2022) @[dec_tlu_ctl.scala 2322:113] - node _T_2024 = orr(_T_2023) @[dec_tlu_ctl.scala 2322:125] - node _T_2025 = and(_T_2020, _T_2024) @[dec_tlu_ctl.scala 2322:98] - node _T_2026 = eq(mhpme_vec[3], UInt<6>("h036")) @[dec_tlu_ctl.scala 2323:34] - node _T_2027 = bits(_T_2026, 0, 0) @[dec_tlu_ctl.scala 2323:62] - node _T_2028 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2323:91] - node _T_2029 = eq(mhpme_vec[3], UInt<6>("h037")) @[dec_tlu_ctl.scala 2324:34] - node _T_2030 = bits(_T_2029, 0, 0) @[dec_tlu_ctl.scala 2324:62] - node _T_2031 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2324:94] - node _T_2032 = eq(mhpme_vec[3], UInt<6>("h038")) @[dec_tlu_ctl.scala 2325:34] - node _T_2033 = bits(_T_2032, 0, 0) @[dec_tlu_ctl.scala 2325:62] - node _T_2034 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2325:94] - node _T_2035 = eq(mhpme_vec[3], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2327:34] - node _T_2036 = bits(_T_2035, 0, 0) @[dec_tlu_ctl.scala 2327:62] - node _T_2037 = eq(mhpme_vec[3], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2328:34] - node _T_2038 = bits(_T_2037, 0, 0) @[dec_tlu_ctl.scala 2328:62] - node _T_2039 = eq(mhpme_vec[3], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2329:34] - node _T_2040 = bits(_T_2039, 0, 0) @[dec_tlu_ctl.scala 2329:62] - node _T_2041 = eq(mhpme_vec[3], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2330:34] - node _T_2042 = bits(_T_2041, 0, 0) @[dec_tlu_ctl.scala 2330:62] - node _T_2043 = eq(mhpme_vec[3], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2331:34] - node _T_2044 = bits(_T_2043, 0, 0) @[dec_tlu_ctl.scala 2331:62] - node _T_2045 = mux(_T_1879, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2046 = mux(_T_1881, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2047 = mux(_T_1883, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2048 = mux(_T_1885, _T_1887, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2049 = mux(_T_1889, _T_1893, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2050 = mux(_T_1895, _T_1898, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2051 = mux(_T_1900, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2052 = mux(_T_1902, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2053 = mux(_T_1904, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2054 = mux(_T_1906, _T_1907, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2055 = mux(_T_1909, _T_1910, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2056 = mux(_T_1912, _T_1913, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2057 = mux(_T_1915, _T_1916, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2058 = mux(_T_1918, _T_1920, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2059 = mux(_T_1922, _T_1925, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2060 = mux(_T_1927, _T_1928, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2061 = mux(_T_1930, _T_1931, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2062 = mux(_T_1933, _T_1934, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2063 = mux(_T_1936, _T_1937, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2064 = mux(_T_1939, _T_1940, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2065 = mux(_T_1942, _T_1943, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2066 = mux(_T_1945, _T_1946, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2067 = mux(_T_1948, _T_1949, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2068 = mux(_T_1951, _T_1952, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2069 = mux(_T_1954, _T_1957, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2070 = mux(_T_1959, _T_1960, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2071 = mux(_T_1962, _T_1963, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2072 = mux(_T_1965, _T_1966, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2073 = mux(_T_1968, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2074 = mux(_T_1970, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2075 = mux(_T_1972, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2076 = mux(_T_1974, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2077 = mux(_T_1976, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2078 = mux(_T_1978, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2079 = mux(_T_1980, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2080 = mux(_T_1982, _T_1984, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2081 = mux(_T_1986, _T_1988, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2082 = mux(_T_1990, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2083 = mux(_T_1992, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2084 = mux(_T_1994, _T_1996, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2085 = mux(_T_1998, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2086 = mux(_T_2000, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2087 = mux(_T_2002, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2088 = mux(_T_2004, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2089 = mux(_T_2006, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2090 = mux(_T_2008, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2091 = mux(_T_2010, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2092 = mux(_T_2012, _T_2015, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2093 = mux(_T_2017, _T_2025, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2094 = mux(_T_2027, _T_2028, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2095 = mux(_T_2030, _T_2031, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2096 = mux(_T_2033, _T_2034, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2097 = mux(_T_2036, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2098 = mux(_T_2038, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2099 = mux(_T_2040, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2100 = mux(_T_2042, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2101 = mux(_T_2044, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2102 = or(_T_2045, _T_2046) @[Mux.scala 27:72] - node _T_2103 = or(_T_2102, _T_2047) @[Mux.scala 27:72] + node _T_1874 = or(_T_1873, _T_1818) @[Mux.scala 27:72] + wire _T_1875 : UInt<1> @[Mux.scala 27:72] + _T_1875 <= _T_1874 @[Mux.scala 27:72] + node _T_1876 = and(_T_1594, _T_1875) @[dec_tlu_ctl.scala 2273:44] + mhpmc_inc_r[2] <= _T_1876 @[dec_tlu_ctl.scala 2273:19] + node _T_1877 = bits(mcountinhibit, 6, 6) @[dec_tlu_ctl.scala 2273:38] + node _T_1878 = not(_T_1877) @[dec_tlu_ctl.scala 2273:24] + node _T_1879 = eq(mhpme_vec[3], UInt<1>("h01")) @[dec_tlu_ctl.scala 2274:34] + node _T_1880 = bits(_T_1879, 0, 0) @[dec_tlu_ctl.scala 2274:62] + node _T_1881 = eq(mhpme_vec[3], UInt<2>("h02")) @[dec_tlu_ctl.scala 2275:34] + node _T_1882 = bits(_T_1881, 0, 0) @[dec_tlu_ctl.scala 2275:62] + node _T_1883 = eq(mhpme_vec[3], UInt<2>("h03")) @[dec_tlu_ctl.scala 2276:34] + node _T_1884 = bits(_T_1883, 0, 0) @[dec_tlu_ctl.scala 2276:62] + node _T_1885 = eq(mhpme_vec[3], UInt<3>("h04")) @[dec_tlu_ctl.scala 2277:34] + node _T_1886 = bits(_T_1885, 0, 0) @[dec_tlu_ctl.scala 2277:62] + node _T_1887 = not(io.illegal_r) @[dec_tlu_ctl.scala 2277:96] + node _T_1888 = and(io.tlu_i0_commit_cmt, _T_1887) @[dec_tlu_ctl.scala 2277:94] + node _T_1889 = eq(mhpme_vec[3], UInt<3>("h05")) @[dec_tlu_ctl.scala 2278:34] + node _T_1890 = bits(_T_1889, 0, 0) @[dec_tlu_ctl.scala 2278:62] + node _T_1891 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2278:96] + node _T_1892 = and(io.tlu_i0_commit_cmt, _T_1891) @[dec_tlu_ctl.scala 2278:94] + node _T_1893 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:117] + node _T_1894 = and(_T_1892, _T_1893) @[dec_tlu_ctl.scala 2278:115] + node _T_1895 = eq(mhpme_vec[3], UInt<3>("h06")) @[dec_tlu_ctl.scala 2279:34] + node _T_1896 = bits(_T_1895, 0, 0) @[dec_tlu_ctl.scala 2279:62] + node _T_1897 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2279:94] + node _T_1898 = not(io.illegal_r) @[dec_tlu_ctl.scala 2279:117] + node _T_1899 = and(_T_1897, _T_1898) @[dec_tlu_ctl.scala 2279:115] + node _T_1900 = eq(mhpme_vec[3], UInt<3>("h07")) @[dec_tlu_ctl.scala 2280:34] + node _T_1901 = bits(_T_1900, 0, 0) @[dec_tlu_ctl.scala 2280:62] + node _T_1902 = eq(mhpme_vec[3], UInt<4>("h08")) @[dec_tlu_ctl.scala 2281:34] + node _T_1903 = bits(_T_1902, 0, 0) @[dec_tlu_ctl.scala 2281:62] + node _T_1904 = eq(mhpme_vec[3], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2282:34] + node _T_1905 = bits(_T_1904, 0, 0) @[dec_tlu_ctl.scala 2282:62] + node _T_1906 = eq(mhpme_vec[3], UInt<4>("h09")) @[dec_tlu_ctl.scala 2283:34] + node _T_1907 = bits(_T_1906, 0, 0) @[dec_tlu_ctl.scala 2283:62] + node _T_1908 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2283:91] + node _T_1909 = eq(mhpme_vec[3], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2284:34] + node _T_1910 = bits(_T_1909, 0, 0) @[dec_tlu_ctl.scala 2284:62] + node _T_1911 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2284:105] + node _T_1912 = eq(mhpme_vec[3], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2285:34] + node _T_1913 = bits(_T_1912, 0, 0) @[dec_tlu_ctl.scala 2285:62] + node _T_1914 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2285:91] + node _T_1915 = eq(mhpme_vec[3], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2286:34] + node _T_1916 = bits(_T_1915, 0, 0) @[dec_tlu_ctl.scala 2286:62] + node _T_1917 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2286:91] + node _T_1918 = eq(mhpme_vec[3], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2287:34] + node _T_1919 = bits(_T_1918, 0, 0) @[dec_tlu_ctl.scala 2287:62] + node _T_1920 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2287:91] + node _T_1921 = and(_T_1920, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2287:100] + node _T_1922 = eq(mhpme_vec[3], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2288:34] + node _T_1923 = bits(_T_1922, 0, 0) @[dec_tlu_ctl.scala 2288:62] + node _T_1924 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2288:91] + node _T_1925 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2288:142] + node _T_1926 = and(_T_1924, _T_1925) @[dec_tlu_ctl.scala 2288:101] + node _T_1927 = eq(mhpme_vec[3], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2289:34] + node _T_1928 = bits(_T_1927, 0, 0) @[dec_tlu_ctl.scala 2289:59] + node _T_1929 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2289:89] + node _T_1930 = eq(mhpme_vec[3], UInt<5>("h010")) @[dec_tlu_ctl.scala 2290:34] + node _T_1931 = bits(_T_1930, 0, 0) @[dec_tlu_ctl.scala 2290:59] + node _T_1932 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2290:89] + node _T_1933 = eq(mhpme_vec[3], UInt<5>("h012")) @[dec_tlu_ctl.scala 2291:34] + node _T_1934 = bits(_T_1933, 0, 0) @[dec_tlu_ctl.scala 2291:59] + node _T_1935 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2291:89] + node _T_1936 = eq(mhpme_vec[3], UInt<5>("h011")) @[dec_tlu_ctl.scala 2292:34] + node _T_1937 = bits(_T_1936, 0, 0) @[dec_tlu_ctl.scala 2292:59] + node _T_1938 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2292:89] + node _T_1939 = eq(mhpme_vec[3], UInt<5>("h013")) @[dec_tlu_ctl.scala 2293:34] + node _T_1940 = bits(_T_1939, 0, 0) @[dec_tlu_ctl.scala 2293:59] + node _T_1941 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2293:89] + node _T_1942 = eq(mhpme_vec[3], UInt<5>("h014")) @[dec_tlu_ctl.scala 2294:34] + node _T_1943 = bits(_T_1942, 0, 0) @[dec_tlu_ctl.scala 2294:59] + node _T_1944 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2294:89] + node _T_1945 = eq(mhpme_vec[3], UInt<5>("h015")) @[dec_tlu_ctl.scala 2295:34] + node _T_1946 = bits(_T_1945, 0, 0) @[dec_tlu_ctl.scala 2295:59] + node _T_1947 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2295:89] + node _T_1948 = eq(mhpme_vec[3], UInt<5>("h016")) @[dec_tlu_ctl.scala 2296:34] + node _T_1949 = bits(_T_1948, 0, 0) @[dec_tlu_ctl.scala 2296:59] + node _T_1950 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2296:89] + node _T_1951 = eq(mhpme_vec[3], UInt<5>("h017")) @[dec_tlu_ctl.scala 2297:34] + node _T_1952 = bits(_T_1951, 0, 0) @[dec_tlu_ctl.scala 2297:59] + node _T_1953 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2297:89] + node _T_1954 = eq(mhpme_vec[3], UInt<5>("h018")) @[dec_tlu_ctl.scala 2298:34] + node _T_1955 = bits(_T_1954, 0, 0) @[dec_tlu_ctl.scala 2298:59] + node _T_1956 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2298:89] + node _T_1957 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2298:122] + node _T_1958 = or(_T_1956, _T_1957) @[dec_tlu_ctl.scala 2298:101] + node _T_1959 = eq(mhpme_vec[3], UInt<5>("h019")) @[dec_tlu_ctl.scala 2299:34] + node _T_1960 = bits(_T_1959, 0, 0) @[dec_tlu_ctl.scala 2299:62] + node _T_1961 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2299:95] + node _T_1962 = eq(mhpme_vec[3], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2300:34] + node _T_1963 = bits(_T_1962, 0, 0) @[dec_tlu_ctl.scala 2300:62] + node _T_1964 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:97] + node _T_1965 = eq(mhpme_vec[3], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2301:34] + node _T_1966 = bits(_T_1965, 0, 0) @[dec_tlu_ctl.scala 2301:62] + node _T_1967 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2301:110] + node _T_1968 = eq(mhpme_vec[3], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2302:34] + node _T_1969 = bits(_T_1968, 0, 0) @[dec_tlu_ctl.scala 2302:62] + node _T_1970 = eq(mhpme_vec[3], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2303:34] + node _T_1971 = bits(_T_1970, 0, 0) @[dec_tlu_ctl.scala 2303:62] + node _T_1972 = eq(mhpme_vec[3], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2304:34] + node _T_1973 = bits(_T_1972, 0, 0) @[dec_tlu_ctl.scala 2304:62] + node _T_1974 = eq(mhpme_vec[3], UInt<6>("h020")) @[dec_tlu_ctl.scala 2305:34] + node _T_1975 = bits(_T_1974, 0, 0) @[dec_tlu_ctl.scala 2305:62] + node _T_1976 = eq(mhpme_vec[3], UInt<6>("h022")) @[dec_tlu_ctl.scala 2306:34] + node _T_1977 = bits(_T_1976, 0, 0) @[dec_tlu_ctl.scala 2306:62] + node _T_1978 = eq(mhpme_vec[3], UInt<6>("h023")) @[dec_tlu_ctl.scala 2307:34] + node _T_1979 = bits(_T_1978, 0, 0) @[dec_tlu_ctl.scala 2307:62] + node _T_1980 = eq(mhpme_vec[3], UInt<6>("h024")) @[dec_tlu_ctl.scala 2308:34] + node _T_1981 = bits(_T_1980, 0, 0) @[dec_tlu_ctl.scala 2308:62] + node _T_1982 = eq(mhpme_vec[3], UInt<6>("h025")) @[dec_tlu_ctl.scala 2309:34] + node _T_1983 = bits(_T_1982, 0, 0) @[dec_tlu_ctl.scala 2309:62] + node _T_1984 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2309:98] + node _T_1985 = or(_T_1984, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2309:120] + node _T_1986 = eq(mhpme_vec[3], UInt<6>("h026")) @[dec_tlu_ctl.scala 2310:34] + node _T_1987 = bits(_T_1986, 0, 0) @[dec_tlu_ctl.scala 2310:62] + node _T_1988 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2310:92] + node _T_1989 = or(_T_1988, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2310:117] + node _T_1990 = eq(mhpme_vec[3], UInt<6>("h027")) @[dec_tlu_ctl.scala 2311:34] + node _T_1991 = bits(_T_1990, 0, 0) @[dec_tlu_ctl.scala 2311:62] + node _T_1992 = eq(mhpme_vec[3], UInt<6>("h028")) @[dec_tlu_ctl.scala 2312:34] + node _T_1993 = bits(_T_1992, 0, 0) @[dec_tlu_ctl.scala 2312:62] + node _T_1994 = eq(mhpme_vec[3], UInt<6>("h029")) @[dec_tlu_ctl.scala 2313:34] + node _T_1995 = bits(_T_1994, 0, 0) @[dec_tlu_ctl.scala 2313:62] + node _T_1996 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2313:97] + node _T_1997 = and(_T_1996, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2313:129] + node _T_1998 = eq(mhpme_vec[3], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2314:34] + node _T_1999 = bits(_T_1998, 0, 0) @[dec_tlu_ctl.scala 2314:62] + node _T_2000 = eq(mhpme_vec[3], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2315:34] + node _T_2001 = bits(_T_2000, 0, 0) @[dec_tlu_ctl.scala 2315:62] + node _T_2002 = eq(mhpme_vec[3], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2316:34] + node _T_2003 = bits(_T_2002, 0, 0) @[dec_tlu_ctl.scala 2316:62] + node _T_2004 = eq(mhpme_vec[3], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2317:34] + node _T_2005 = bits(_T_2004, 0, 0) @[dec_tlu_ctl.scala 2317:62] + node _T_2006 = eq(mhpme_vec[3], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2318:34] + node _T_2007 = bits(_T_2006, 0, 0) @[dec_tlu_ctl.scala 2318:62] + node _T_2008 = eq(mhpme_vec[3], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2319:34] + node _T_2009 = bits(_T_2008, 0, 0) @[dec_tlu_ctl.scala 2319:62] + node _T_2010 = eq(mhpme_vec[3], UInt<6>("h030")) @[dec_tlu_ctl.scala 2320:34] + node _T_2011 = bits(_T_2010, 0, 0) @[dec_tlu_ctl.scala 2320:62] + node _T_2012 = eq(mhpme_vec[3], UInt<6>("h031")) @[dec_tlu_ctl.scala 2321:34] + node _T_2013 = bits(_T_2012, 0, 0) @[dec_tlu_ctl.scala 2321:62] + node _T_2014 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2321:84] + node _T_2015 = bits(_T_2014, 0, 0) @[dec_tlu_ctl.scala 2321:84] + node _T_2016 = not(_T_2015) @[dec_tlu_ctl.scala 2321:73] + node _T_2017 = eq(mhpme_vec[3], UInt<6>("h032")) @[dec_tlu_ctl.scala 2322:34] + node _T_2018 = bits(_T_2017, 0, 0) @[dec_tlu_ctl.scala 2322:62] + node _T_2019 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2322:84] + node _T_2020 = bits(_T_2019, 0, 0) @[dec_tlu_ctl.scala 2322:84] + node _T_2021 = not(_T_2020) @[dec_tlu_ctl.scala 2322:73] + node _T_2022 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2322:107] + node _T_2023 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2322:118] + node _T_2024 = and(_T_2022, _T_2023) @[dec_tlu_ctl.scala 2322:113] + node _T_2025 = orr(_T_2024) @[dec_tlu_ctl.scala 2322:125] + node _T_2026 = and(_T_2021, _T_2025) @[dec_tlu_ctl.scala 2322:98] + node _T_2027 = eq(mhpme_vec[3], UInt<6>("h036")) @[dec_tlu_ctl.scala 2323:34] + node _T_2028 = bits(_T_2027, 0, 0) @[dec_tlu_ctl.scala 2323:62] + node _T_2029 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2323:91] + node _T_2030 = eq(mhpme_vec[3], UInt<6>("h037")) @[dec_tlu_ctl.scala 2324:34] + node _T_2031 = bits(_T_2030, 0, 0) @[dec_tlu_ctl.scala 2324:62] + node _T_2032 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2324:94] + node _T_2033 = eq(mhpme_vec[3], UInt<6>("h038")) @[dec_tlu_ctl.scala 2325:34] + node _T_2034 = bits(_T_2033, 0, 0) @[dec_tlu_ctl.scala 2325:62] + node _T_2035 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2325:94] + node _T_2036 = eq(mhpme_vec[3], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2327:34] + node _T_2037 = bits(_T_2036, 0, 0) @[dec_tlu_ctl.scala 2327:62] + node _T_2038 = eq(mhpme_vec[3], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2328:34] + node _T_2039 = bits(_T_2038, 0, 0) @[dec_tlu_ctl.scala 2328:62] + node _T_2040 = eq(mhpme_vec[3], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2329:34] + node _T_2041 = bits(_T_2040, 0, 0) @[dec_tlu_ctl.scala 2329:62] + node _T_2042 = eq(mhpme_vec[3], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2330:34] + node _T_2043 = bits(_T_2042, 0, 0) @[dec_tlu_ctl.scala 2330:62] + node _T_2044 = eq(mhpme_vec[3], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2331:34] + node _T_2045 = bits(_T_2044, 0, 0) @[dec_tlu_ctl.scala 2331:62] + node _T_2046 = mux(_T_1880, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2047 = mux(_T_1882, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2048 = mux(_T_1884, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2049 = mux(_T_1886, _T_1888, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2050 = mux(_T_1890, _T_1894, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2051 = mux(_T_1896, _T_1899, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2052 = mux(_T_1901, io.ifu_pmu_instr_aligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2053 = mux(_T_1903, io.dec_pmu_instr_decoded, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2054 = mux(_T_1905, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2055 = mux(_T_1907, _T_1908, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2056 = mux(_T_1910, _T_1911, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2057 = mux(_T_1913, _T_1914, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2058 = mux(_T_1916, _T_1917, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2059 = mux(_T_1919, _T_1921, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2060 = mux(_T_1923, _T_1926, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2061 = mux(_T_1928, _T_1929, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2062 = mux(_T_1931, _T_1932, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2063 = mux(_T_1934, _T_1935, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2064 = mux(_T_1937, _T_1938, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2065 = mux(_T_1940, _T_1941, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2066 = mux(_T_1943, _T_1944, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2067 = mux(_T_1946, _T_1947, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2068 = mux(_T_1949, _T_1950, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2069 = mux(_T_1952, _T_1953, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2070 = mux(_T_1955, _T_1958, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2071 = mux(_T_1960, _T_1961, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2072 = mux(_T_1963, _T_1964, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2073 = mux(_T_1966, _T_1967, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2074 = mux(_T_1969, io.ifu_pmu_fetch_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2075 = mux(_T_1971, io.dec_pmu_decode_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2076 = mux(_T_1973, io.dec_pmu_postsync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2077 = mux(_T_1975, io.dec_pmu_presync_stall, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2078 = mux(_T_1977, io.lsu_store_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2079 = mux(_T_1979, io.dma_dccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2080 = mux(_T_1981, io.dma_iccm_stall_any, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2081 = mux(_T_1983, _T_1985, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2082 = mux(_T_1987, _T_1989, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2083 = mux(_T_1991, io.take_ext_int, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2084 = mux(_T_1993, io.tlu_flush_lower_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2085 = mux(_T_1995, _T_1997, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2086 = mux(_T_1999, io.ifu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2087 = mux(_T_2001, io.lsu_pmu_bus_trxn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2088 = mux(_T_2003, io.lsu_pmu_bus_misaligned, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2089 = mux(_T_2005, io.ifu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2090 = mux(_T_2007, io.lsu_pmu_bus_error, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2091 = mux(_T_2009, io.ifu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2092 = mux(_T_2011, io.lsu_pmu_bus_busy, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2093 = mux(_T_2013, _T_2016, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2094 = mux(_T_2018, _T_2026, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2095 = mux(_T_2028, _T_2029, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2096 = mux(_T_2031, _T_2032, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2097 = mux(_T_2034, _T_2035, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2098 = mux(_T_2037, io.dec_tlu_pmu_fw_halted, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2099 = mux(_T_2039, io.dma_pmu_any_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2100 = mux(_T_2041, io.dma_pmu_any_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2101 = mux(_T_2043, io.dma_pmu_dccm_read, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2102 = mux(_T_2045, io.dma_pmu_dccm_write, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2103 = or(_T_2046, _T_2047) @[Mux.scala 27:72] node _T_2104 = or(_T_2103, _T_2048) @[Mux.scala 27:72] node _T_2105 = or(_T_2104, _T_2049) @[Mux.scala 27:72] node _T_2106 = or(_T_2105, _T_2050) @[Mux.scala 27:72] @@ -75547,576 +75555,576 @@ circuit quasar_wrapper : node _T_2155 = or(_T_2154, _T_2099) @[Mux.scala 27:72] node _T_2156 = or(_T_2155, _T_2100) @[Mux.scala 27:72] node _T_2157 = or(_T_2156, _T_2101) @[Mux.scala 27:72] - wire _T_2158 : UInt<1> @[Mux.scala 27:72] - _T_2158 <= _T_2157 @[Mux.scala 27:72] - node _T_2159 = and(_T_1877, _T_2158) @[dec_tlu_ctl.scala 2273:44] - mhpmc_inc_r[3] <= _T_2159 @[dec_tlu_ctl.scala 2273:19] - reg _T_2160 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2334:53] - _T_2160 <= mhpmc_inc_r[0] @[dec_tlu_ctl.scala 2334:53] - mhpmc_inc_r_d1[0] <= _T_2160 @[dec_tlu_ctl.scala 2334:20] - reg _T_2161 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2335:53] - _T_2161 <= mhpmc_inc_r[1] @[dec_tlu_ctl.scala 2335:53] - mhpmc_inc_r_d1[1] <= _T_2161 @[dec_tlu_ctl.scala 2335:20] - reg _T_2162 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2336:53] - _T_2162 <= mhpmc_inc_r[2] @[dec_tlu_ctl.scala 2336:53] - mhpmc_inc_r_d1[2] <= _T_2162 @[dec_tlu_ctl.scala 2336:20] - reg _T_2163 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2337:53] - _T_2163 <= mhpmc_inc_r[3] @[dec_tlu_ctl.scala 2337:53] - mhpmc_inc_r_d1[3] <= _T_2163 @[dec_tlu_ctl.scala 2337:20] + node _T_2158 = or(_T_2157, _T_2102) @[Mux.scala 27:72] + wire _T_2159 : UInt<1> @[Mux.scala 27:72] + _T_2159 <= _T_2158 @[Mux.scala 27:72] + node _T_2160 = and(_T_1878, _T_2159) @[dec_tlu_ctl.scala 2273:44] + mhpmc_inc_r[3] <= _T_2160 @[dec_tlu_ctl.scala 2273:19] + reg _T_2161 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2334:53] + _T_2161 <= mhpmc_inc_r[0] @[dec_tlu_ctl.scala 2334:53] + mhpmc_inc_r_d1[0] <= _T_2161 @[dec_tlu_ctl.scala 2334:20] + reg _T_2162 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2335:53] + _T_2162 <= mhpmc_inc_r[1] @[dec_tlu_ctl.scala 2335:53] + mhpmc_inc_r_d1[1] <= _T_2162 @[dec_tlu_ctl.scala 2335:20] + reg _T_2163 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2336:53] + _T_2163 <= mhpmc_inc_r[2] @[dec_tlu_ctl.scala 2336:53] + mhpmc_inc_r_d1[2] <= _T_2163 @[dec_tlu_ctl.scala 2336:20] + reg _T_2164 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2337:53] + _T_2164 <= mhpmc_inc_r[3] @[dec_tlu_ctl.scala 2337:53] + mhpmc_inc_r_d1[3] <= _T_2164 @[dec_tlu_ctl.scala 2337:20] reg perfcnt_halted_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2338:56] perfcnt_halted_d1 <= perfcnt_halted @[dec_tlu_ctl.scala 2338:56] - node _T_2164 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 2341:53] - node _T_2165 = and(io.dec_tlu_dbg_halted, _T_2164) @[dec_tlu_ctl.scala 2341:44] - node _T_2166 = or(_T_2165, io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 2341:67] - perfcnt_halted <= _T_2166 @[dec_tlu_ctl.scala 2341:17] - node _T_2167 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 2342:70] - node _T_2168 = and(io.dec_tlu_dbg_halted, _T_2167) @[dec_tlu_ctl.scala 2342:61] - node _T_2169 = not(_T_2168) @[dec_tlu_ctl.scala 2342:37] - node _T_2170 = bits(_T_2169, 0, 0) @[Bitwise.scala 72:15] - node _T_2171 = mux(_T_2170, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_2172 = bits(mhpme_vec[3], 9, 9) @[dec_tlu_ctl.scala 2342:104] - node _T_2173 = bits(mhpme_vec[2], 9, 9) @[dec_tlu_ctl.scala 2342:120] - node _T_2174 = bits(mhpme_vec[1], 9, 9) @[dec_tlu_ctl.scala 2342:136] - node _T_2175 = bits(mhpme_vec[0], 9, 9) @[dec_tlu_ctl.scala 2342:152] - node _T_2176 = cat(_T_2174, _T_2175) @[Cat.scala 29:58] - node _T_2177 = cat(_T_2172, _T_2173) @[Cat.scala 29:58] - node _T_2178 = cat(_T_2177, _T_2176) @[Cat.scala 29:58] - node perfcnt_during_sleep = and(_T_2171, _T_2178) @[dec_tlu_ctl.scala 2342:86] - node _T_2179 = bits(perfcnt_during_sleep, 0, 0) @[dec_tlu_ctl.scala 2344:88] - node _T_2180 = not(_T_2179) @[dec_tlu_ctl.scala 2344:67] - node _T_2181 = and(perfcnt_halted_d1, _T_2180) @[dec_tlu_ctl.scala 2344:65] - node _T_2182 = not(_T_2181) @[dec_tlu_ctl.scala 2344:45] - node _T_2183 = and(mhpmc_inc_r_d1[0], _T_2182) @[dec_tlu_ctl.scala 2344:43] - io.dec_tlu_perfcnt0 <= _T_2183 @[dec_tlu_ctl.scala 2344:22] - node _T_2184 = bits(perfcnt_during_sleep, 1, 1) @[dec_tlu_ctl.scala 2345:88] - node _T_2185 = not(_T_2184) @[dec_tlu_ctl.scala 2345:67] - node _T_2186 = and(perfcnt_halted_d1, _T_2185) @[dec_tlu_ctl.scala 2345:65] - node _T_2187 = not(_T_2186) @[dec_tlu_ctl.scala 2345:45] - node _T_2188 = and(mhpmc_inc_r_d1[1], _T_2187) @[dec_tlu_ctl.scala 2345:43] - io.dec_tlu_perfcnt1 <= _T_2188 @[dec_tlu_ctl.scala 2345:22] - node _T_2189 = bits(perfcnt_during_sleep, 2, 2) @[dec_tlu_ctl.scala 2346:88] - node _T_2190 = not(_T_2189) @[dec_tlu_ctl.scala 2346:67] - node _T_2191 = and(perfcnt_halted_d1, _T_2190) @[dec_tlu_ctl.scala 2346:65] - node _T_2192 = not(_T_2191) @[dec_tlu_ctl.scala 2346:45] - node _T_2193 = and(mhpmc_inc_r_d1[2], _T_2192) @[dec_tlu_ctl.scala 2346:43] - io.dec_tlu_perfcnt2 <= _T_2193 @[dec_tlu_ctl.scala 2346:22] - node _T_2194 = bits(perfcnt_during_sleep, 3, 3) @[dec_tlu_ctl.scala 2347:88] - node _T_2195 = not(_T_2194) @[dec_tlu_ctl.scala 2347:67] - node _T_2196 = and(perfcnt_halted_d1, _T_2195) @[dec_tlu_ctl.scala 2347:65] - node _T_2197 = not(_T_2196) @[dec_tlu_ctl.scala 2347:45] - node _T_2198 = and(mhpmc_inc_r_d1[3], _T_2197) @[dec_tlu_ctl.scala 2347:43] - io.dec_tlu_perfcnt3 <= _T_2198 @[dec_tlu_ctl.scala 2347:22] - node _T_2199 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2353:65] - node _T_2200 = eq(_T_2199, UInt<12>("h0b03")) @[dec_tlu_ctl.scala 2353:72] - node mhpmc3_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2200) @[dec_tlu_ctl.scala 2353:43] - node _T_2201 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2354:23] - node _T_2202 = bits(perfcnt_during_sleep, 0, 0) @[dec_tlu_ctl.scala 2354:61] - node _T_2203 = or(_T_2201, _T_2202) @[dec_tlu_ctl.scala 2354:39] - node _T_2204 = orr(mhpmc_inc_r[0]) @[dec_tlu_ctl.scala 2354:86] - node mhpmc3_wr_en1 = and(_T_2203, _T_2204) @[dec_tlu_ctl.scala 2354:66] + node _T_2165 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 2341:53] + node _T_2166 = and(io.dec_tlu_dbg_halted, _T_2165) @[dec_tlu_ctl.scala 2341:44] + node _T_2167 = or(_T_2166, io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 2341:67] + perfcnt_halted <= _T_2167 @[dec_tlu_ctl.scala 2341:17] + node _T_2168 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 2342:70] + node _T_2169 = and(io.dec_tlu_dbg_halted, _T_2168) @[dec_tlu_ctl.scala 2342:61] + node _T_2170 = not(_T_2169) @[dec_tlu_ctl.scala 2342:37] + node _T_2171 = bits(_T_2170, 0, 0) @[Bitwise.scala 72:15] + node _T_2172 = mux(_T_2171, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_2173 = bits(mhpme_vec[3], 9, 9) @[dec_tlu_ctl.scala 2342:104] + node _T_2174 = bits(mhpme_vec[2], 9, 9) @[dec_tlu_ctl.scala 2342:120] + node _T_2175 = bits(mhpme_vec[1], 9, 9) @[dec_tlu_ctl.scala 2342:136] + node _T_2176 = bits(mhpme_vec[0], 9, 9) @[dec_tlu_ctl.scala 2342:152] + node _T_2177 = cat(_T_2175, _T_2176) @[Cat.scala 29:58] + node _T_2178 = cat(_T_2173, _T_2174) @[Cat.scala 29:58] + node _T_2179 = cat(_T_2178, _T_2177) @[Cat.scala 29:58] + node perfcnt_during_sleep = and(_T_2172, _T_2179) @[dec_tlu_ctl.scala 2342:86] + node _T_2180 = bits(perfcnt_during_sleep, 0, 0) @[dec_tlu_ctl.scala 2344:88] + node _T_2181 = not(_T_2180) @[dec_tlu_ctl.scala 2344:67] + node _T_2182 = and(perfcnt_halted_d1, _T_2181) @[dec_tlu_ctl.scala 2344:65] + node _T_2183 = not(_T_2182) @[dec_tlu_ctl.scala 2344:45] + node _T_2184 = and(mhpmc_inc_r_d1[0], _T_2183) @[dec_tlu_ctl.scala 2344:43] + io.dec_tlu_perfcnt0 <= _T_2184 @[dec_tlu_ctl.scala 2344:22] + node _T_2185 = bits(perfcnt_during_sleep, 1, 1) @[dec_tlu_ctl.scala 2345:88] + node _T_2186 = not(_T_2185) @[dec_tlu_ctl.scala 2345:67] + node _T_2187 = and(perfcnt_halted_d1, _T_2186) @[dec_tlu_ctl.scala 2345:65] + node _T_2188 = not(_T_2187) @[dec_tlu_ctl.scala 2345:45] + node _T_2189 = and(mhpmc_inc_r_d1[1], _T_2188) @[dec_tlu_ctl.scala 2345:43] + io.dec_tlu_perfcnt1 <= _T_2189 @[dec_tlu_ctl.scala 2345:22] + node _T_2190 = bits(perfcnt_during_sleep, 2, 2) @[dec_tlu_ctl.scala 2346:88] + node _T_2191 = not(_T_2190) @[dec_tlu_ctl.scala 2346:67] + node _T_2192 = and(perfcnt_halted_d1, _T_2191) @[dec_tlu_ctl.scala 2346:65] + node _T_2193 = not(_T_2192) @[dec_tlu_ctl.scala 2346:45] + node _T_2194 = and(mhpmc_inc_r_d1[2], _T_2193) @[dec_tlu_ctl.scala 2346:43] + io.dec_tlu_perfcnt2 <= _T_2194 @[dec_tlu_ctl.scala 2346:22] + node _T_2195 = bits(perfcnt_during_sleep, 3, 3) @[dec_tlu_ctl.scala 2347:88] + node _T_2196 = not(_T_2195) @[dec_tlu_ctl.scala 2347:67] + node _T_2197 = and(perfcnt_halted_d1, _T_2196) @[dec_tlu_ctl.scala 2347:65] + node _T_2198 = not(_T_2197) @[dec_tlu_ctl.scala 2347:45] + node _T_2199 = and(mhpmc_inc_r_d1[3], _T_2198) @[dec_tlu_ctl.scala 2347:43] + io.dec_tlu_perfcnt3 <= _T_2199 @[dec_tlu_ctl.scala 2347:22] + node _T_2200 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2353:65] + node _T_2201 = eq(_T_2200, UInt<12>("h0b03")) @[dec_tlu_ctl.scala 2353:72] + node mhpmc3_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2201) @[dec_tlu_ctl.scala 2353:43] + node _T_2202 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2354:23] + node _T_2203 = bits(perfcnt_during_sleep, 0, 0) @[dec_tlu_ctl.scala 2354:61] + node _T_2204 = or(_T_2202, _T_2203) @[dec_tlu_ctl.scala 2354:39] + node _T_2205 = orr(mhpmc_inc_r[0]) @[dec_tlu_ctl.scala 2354:86] + node mhpmc3_wr_en1 = and(_T_2204, _T_2205) @[dec_tlu_ctl.scala 2354:66] node mhpmc3_wr_en = or(mhpmc3_wr_en0, mhpmc3_wr_en1) @[dec_tlu_ctl.scala 2355:36] - node _T_2205 = bits(mhpmc3h, 31, 0) @[dec_tlu_ctl.scala 2358:28] - node _T_2206 = bits(mhpmc3, 31, 0) @[dec_tlu_ctl.scala 2358:41] - node _T_2207 = cat(_T_2205, _T_2206) @[Cat.scala 29:58] - node _T_2208 = cat(UInt<63>("h00"), mhpmc_inc_r[0]) @[Cat.scala 29:58] - node _T_2209 = add(_T_2207, _T_2208) @[dec_tlu_ctl.scala 2358:49] - node _T_2210 = tail(_T_2209, 1) @[dec_tlu_ctl.scala 2358:49] - mhpmc3_incr <= _T_2210 @[dec_tlu_ctl.scala 2358:14] - node _T_2211 = bits(mhpmc3_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2359:36] - node _T_2212 = bits(mhpmc3_incr, 31, 0) @[dec_tlu_ctl.scala 2359:76] - node mhpmc3_ns = mux(_T_2211, io.dec_csr_wrdata_r, _T_2212) @[dec_tlu_ctl.scala 2359:21] - node _T_2213 = bits(mhpmc3_wr_en, 0, 0) @[dec_tlu_ctl.scala 2361:42] + node _T_2206 = bits(mhpmc3h, 31, 0) @[dec_tlu_ctl.scala 2358:28] + node _T_2207 = bits(mhpmc3, 31, 0) @[dec_tlu_ctl.scala 2358:41] + node _T_2208 = cat(_T_2206, _T_2207) @[Cat.scala 29:58] + node _T_2209 = cat(UInt<63>("h00"), mhpmc_inc_r[0]) @[Cat.scala 29:58] + node _T_2210 = add(_T_2208, _T_2209) @[dec_tlu_ctl.scala 2358:49] + node _T_2211 = tail(_T_2210, 1) @[dec_tlu_ctl.scala 2358:49] + mhpmc3_incr <= _T_2211 @[dec_tlu_ctl.scala 2358:14] + node _T_2212 = bits(mhpmc3_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2359:36] + node _T_2213 = bits(mhpmc3_incr, 31, 0) @[dec_tlu_ctl.scala 2359:76] + node mhpmc3_ns = mux(_T_2212, io.dec_csr_wrdata_r, _T_2213) @[dec_tlu_ctl.scala 2359:21] + node _T_2214 = bits(mhpmc3_wr_en, 0, 0) @[dec_tlu_ctl.scala 2361:42] inst rvclkhdr_26 of rvclkhdr_746 @[lib.scala 368:23] rvclkhdr_26.clock <= clock rvclkhdr_26.reset <= reset rvclkhdr_26.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_26.io.en <= _T_2213 @[lib.scala 371:17] + rvclkhdr_26.io.en <= _T_2214 @[lib.scala 371:17] rvclkhdr_26.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_2214 : UInt, rvclkhdr_26.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_2214 <= mhpmc3_ns @[lib.scala 374:16] - mhpmc3 <= _T_2214 @[dec_tlu_ctl.scala 2361:9] - node _T_2215 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2363:66] - node _T_2216 = eq(_T_2215, UInt<12>("h0b83")) @[dec_tlu_ctl.scala 2363:73] - node mhpmc3h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2216) @[dec_tlu_ctl.scala 2363:44] + reg _T_2215 : UInt, rvclkhdr_26.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2215 <= mhpmc3_ns @[lib.scala 374:16] + mhpmc3 <= _T_2215 @[dec_tlu_ctl.scala 2361:9] + node _T_2216 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2363:66] + node _T_2217 = eq(_T_2216, UInt<12>("h0b83")) @[dec_tlu_ctl.scala 2363:73] + node mhpmc3h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2217) @[dec_tlu_ctl.scala 2363:44] node mhpmc3h_wr_en = or(mhpmc3h_wr_en0, mhpmc3_wr_en1) @[dec_tlu_ctl.scala 2364:38] - node _T_2217 = bits(mhpmc3h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2365:38] - node _T_2218 = bits(mhpmc3_incr, 63, 32) @[dec_tlu_ctl.scala 2365:78] - node mhpmc3h_ns = mux(_T_2217, io.dec_csr_wrdata_r, _T_2218) @[dec_tlu_ctl.scala 2365:22] - node _T_2219 = bits(mhpmc3h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2367:46] + node _T_2218 = bits(mhpmc3h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2365:38] + node _T_2219 = bits(mhpmc3_incr, 63, 32) @[dec_tlu_ctl.scala 2365:78] + node mhpmc3h_ns = mux(_T_2218, io.dec_csr_wrdata_r, _T_2219) @[dec_tlu_ctl.scala 2365:22] + node _T_2220 = bits(mhpmc3h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2367:46] inst rvclkhdr_27 of rvclkhdr_747 @[lib.scala 368:23] rvclkhdr_27.clock <= clock rvclkhdr_27.reset <= reset rvclkhdr_27.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_27.io.en <= _T_2219 @[lib.scala 371:17] + rvclkhdr_27.io.en <= _T_2220 @[lib.scala 371:17] rvclkhdr_27.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_2220 : UInt, rvclkhdr_27.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_2220 <= mhpmc3h_ns @[lib.scala 374:16] - mhpmc3h <= _T_2220 @[dec_tlu_ctl.scala 2367:10] - node _T_2221 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2372:65] - node _T_2222 = eq(_T_2221, UInt<12>("h0b04")) @[dec_tlu_ctl.scala 2372:72] - node mhpmc4_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2222) @[dec_tlu_ctl.scala 2372:43] - node _T_2223 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2373:23] - node _T_2224 = bits(perfcnt_during_sleep, 1, 1) @[dec_tlu_ctl.scala 2373:61] - node _T_2225 = or(_T_2223, _T_2224) @[dec_tlu_ctl.scala 2373:39] - node _T_2226 = orr(mhpmc_inc_r[1]) @[dec_tlu_ctl.scala 2373:86] - node mhpmc4_wr_en1 = and(_T_2225, _T_2226) @[dec_tlu_ctl.scala 2373:66] + reg _T_2221 : UInt, rvclkhdr_27.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2221 <= mhpmc3h_ns @[lib.scala 374:16] + mhpmc3h <= _T_2221 @[dec_tlu_ctl.scala 2367:10] + node _T_2222 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2372:65] + node _T_2223 = eq(_T_2222, UInt<12>("h0b04")) @[dec_tlu_ctl.scala 2372:72] + node mhpmc4_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2223) @[dec_tlu_ctl.scala 2372:43] + node _T_2224 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2373:23] + node _T_2225 = bits(perfcnt_during_sleep, 1, 1) @[dec_tlu_ctl.scala 2373:61] + node _T_2226 = or(_T_2224, _T_2225) @[dec_tlu_ctl.scala 2373:39] + node _T_2227 = orr(mhpmc_inc_r[1]) @[dec_tlu_ctl.scala 2373:86] + node mhpmc4_wr_en1 = and(_T_2226, _T_2227) @[dec_tlu_ctl.scala 2373:66] node mhpmc4_wr_en = or(mhpmc4_wr_en0, mhpmc4_wr_en1) @[dec_tlu_ctl.scala 2374:36] - node _T_2227 = bits(mhpmc4h, 31, 0) @[dec_tlu_ctl.scala 2378:28] - node _T_2228 = bits(mhpmc4, 31, 0) @[dec_tlu_ctl.scala 2378:41] - node _T_2229 = cat(_T_2227, _T_2228) @[Cat.scala 29:58] - node _T_2230 = cat(UInt<63>("h00"), mhpmc_inc_r[1]) @[Cat.scala 29:58] - node _T_2231 = add(_T_2229, _T_2230) @[dec_tlu_ctl.scala 2378:49] - node _T_2232 = tail(_T_2231, 1) @[dec_tlu_ctl.scala 2378:49] - mhpmc4_incr <= _T_2232 @[dec_tlu_ctl.scala 2378:14] - node _T_2233 = bits(mhpmc4_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2379:36] - node _T_2234 = bits(io.dec_csr_wrdata_r, 31, 0) @[dec_tlu_ctl.scala 2379:63] - node _T_2235 = bits(mhpmc4_incr, 31, 0) @[dec_tlu_ctl.scala 2379:82] - node mhpmc4_ns = mux(_T_2233, _T_2234, _T_2235) @[dec_tlu_ctl.scala 2379:21] - node _T_2236 = bits(mhpmc4_wr_en, 0, 0) @[dec_tlu_ctl.scala 2380:43] + node _T_2228 = bits(mhpmc4h, 31, 0) @[dec_tlu_ctl.scala 2378:28] + node _T_2229 = bits(mhpmc4, 31, 0) @[dec_tlu_ctl.scala 2378:41] + node _T_2230 = cat(_T_2228, _T_2229) @[Cat.scala 29:58] + node _T_2231 = cat(UInt<63>("h00"), mhpmc_inc_r[1]) @[Cat.scala 29:58] + node _T_2232 = add(_T_2230, _T_2231) @[dec_tlu_ctl.scala 2378:49] + node _T_2233 = tail(_T_2232, 1) @[dec_tlu_ctl.scala 2378:49] + mhpmc4_incr <= _T_2233 @[dec_tlu_ctl.scala 2378:14] + node _T_2234 = bits(mhpmc4_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2379:36] + node _T_2235 = bits(io.dec_csr_wrdata_r, 31, 0) @[dec_tlu_ctl.scala 2379:63] + node _T_2236 = bits(mhpmc4_incr, 31, 0) @[dec_tlu_ctl.scala 2379:82] + node mhpmc4_ns = mux(_T_2234, _T_2235, _T_2236) @[dec_tlu_ctl.scala 2379:21] + node _T_2237 = bits(mhpmc4_wr_en, 0, 0) @[dec_tlu_ctl.scala 2380:43] inst rvclkhdr_28 of rvclkhdr_748 @[lib.scala 368:23] rvclkhdr_28.clock <= clock rvclkhdr_28.reset <= reset rvclkhdr_28.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_28.io.en <= _T_2236 @[lib.scala 371:17] + rvclkhdr_28.io.en <= _T_2237 @[lib.scala 371:17] rvclkhdr_28.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_2237 : UInt, rvclkhdr_28.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_2237 <= mhpmc4_ns @[lib.scala 374:16] - mhpmc4 <= _T_2237 @[dec_tlu_ctl.scala 2380:9] - node _T_2238 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2382:66] - node _T_2239 = eq(_T_2238, UInt<12>("h0b84")) @[dec_tlu_ctl.scala 2382:73] - node mhpmc4h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2239) @[dec_tlu_ctl.scala 2382:44] + reg _T_2238 : UInt, rvclkhdr_28.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2238 <= mhpmc4_ns @[lib.scala 374:16] + mhpmc4 <= _T_2238 @[dec_tlu_ctl.scala 2380:9] + node _T_2239 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2382:66] + node _T_2240 = eq(_T_2239, UInt<12>("h0b84")) @[dec_tlu_ctl.scala 2382:73] + node mhpmc4h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2240) @[dec_tlu_ctl.scala 2382:44] node mhpmc4h_wr_en = or(mhpmc4h_wr_en0, mhpmc4_wr_en1) @[dec_tlu_ctl.scala 2383:38] - node _T_2240 = bits(mhpmc4h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2384:38] - node _T_2241 = bits(mhpmc4_incr, 63, 32) @[dec_tlu_ctl.scala 2384:78] - node mhpmc4h_ns = mux(_T_2240, io.dec_csr_wrdata_r, _T_2241) @[dec_tlu_ctl.scala 2384:22] - node _T_2242 = bits(mhpmc4h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2385:46] + node _T_2241 = bits(mhpmc4h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2384:38] + node _T_2242 = bits(mhpmc4_incr, 63, 32) @[dec_tlu_ctl.scala 2384:78] + node mhpmc4h_ns = mux(_T_2241, io.dec_csr_wrdata_r, _T_2242) @[dec_tlu_ctl.scala 2384:22] + node _T_2243 = bits(mhpmc4h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2385:46] inst rvclkhdr_29 of rvclkhdr_749 @[lib.scala 368:23] rvclkhdr_29.clock <= clock rvclkhdr_29.reset <= reset rvclkhdr_29.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_29.io.en <= _T_2242 @[lib.scala 371:17] + rvclkhdr_29.io.en <= _T_2243 @[lib.scala 371:17] rvclkhdr_29.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_2243 : UInt, rvclkhdr_29.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_2243 <= mhpmc4h_ns @[lib.scala 374:16] - mhpmc4h <= _T_2243 @[dec_tlu_ctl.scala 2385:10] - node _T_2244 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2391:65] - node _T_2245 = eq(_T_2244, UInt<12>("h0b05")) @[dec_tlu_ctl.scala 2391:72] - node mhpmc5_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2245) @[dec_tlu_ctl.scala 2391:43] - node _T_2246 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2392:23] - node _T_2247 = bits(perfcnt_during_sleep, 2, 2) @[dec_tlu_ctl.scala 2392:61] - node _T_2248 = or(_T_2246, _T_2247) @[dec_tlu_ctl.scala 2392:39] - node _T_2249 = orr(mhpmc_inc_r[2]) @[dec_tlu_ctl.scala 2392:86] - node mhpmc5_wr_en1 = and(_T_2248, _T_2249) @[dec_tlu_ctl.scala 2392:66] + reg _T_2244 : UInt, rvclkhdr_29.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2244 <= mhpmc4h_ns @[lib.scala 374:16] + mhpmc4h <= _T_2244 @[dec_tlu_ctl.scala 2385:10] + node _T_2245 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2391:65] + node _T_2246 = eq(_T_2245, UInt<12>("h0b05")) @[dec_tlu_ctl.scala 2391:72] + node mhpmc5_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2246) @[dec_tlu_ctl.scala 2391:43] + node _T_2247 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2392:23] + node _T_2248 = bits(perfcnt_during_sleep, 2, 2) @[dec_tlu_ctl.scala 2392:61] + node _T_2249 = or(_T_2247, _T_2248) @[dec_tlu_ctl.scala 2392:39] + node _T_2250 = orr(mhpmc_inc_r[2]) @[dec_tlu_ctl.scala 2392:86] + node mhpmc5_wr_en1 = and(_T_2249, _T_2250) @[dec_tlu_ctl.scala 2392:66] node mhpmc5_wr_en = or(mhpmc5_wr_en0, mhpmc5_wr_en1) @[dec_tlu_ctl.scala 2393:36] - node _T_2250 = bits(mhpmc5h, 31, 0) @[dec_tlu_ctl.scala 2395:28] - node _T_2251 = bits(mhpmc5, 31, 0) @[dec_tlu_ctl.scala 2395:41] - node _T_2252 = cat(_T_2250, _T_2251) @[Cat.scala 29:58] - node _T_2253 = cat(UInt<63>("h00"), mhpmc_inc_r[2]) @[Cat.scala 29:58] - node _T_2254 = add(_T_2252, _T_2253) @[dec_tlu_ctl.scala 2395:49] - node _T_2255 = tail(_T_2254, 1) @[dec_tlu_ctl.scala 2395:49] - mhpmc5_incr <= _T_2255 @[dec_tlu_ctl.scala 2395:14] - node _T_2256 = bits(mhpmc5_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2396:36] - node _T_2257 = bits(mhpmc5_incr, 31, 0) @[dec_tlu_ctl.scala 2396:76] - node mhpmc5_ns = mux(_T_2256, io.dec_csr_wrdata_r, _T_2257) @[dec_tlu_ctl.scala 2396:21] - node _T_2258 = bits(mhpmc5_wr_en, 0, 0) @[dec_tlu_ctl.scala 2398:43] + node _T_2251 = bits(mhpmc5h, 31, 0) @[dec_tlu_ctl.scala 2395:28] + node _T_2252 = bits(mhpmc5, 31, 0) @[dec_tlu_ctl.scala 2395:41] + node _T_2253 = cat(_T_2251, _T_2252) @[Cat.scala 29:58] + node _T_2254 = cat(UInt<63>("h00"), mhpmc_inc_r[2]) @[Cat.scala 29:58] + node _T_2255 = add(_T_2253, _T_2254) @[dec_tlu_ctl.scala 2395:49] + node _T_2256 = tail(_T_2255, 1) @[dec_tlu_ctl.scala 2395:49] + mhpmc5_incr <= _T_2256 @[dec_tlu_ctl.scala 2395:14] + node _T_2257 = bits(mhpmc5_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2396:36] + node _T_2258 = bits(mhpmc5_incr, 31, 0) @[dec_tlu_ctl.scala 2396:76] + node mhpmc5_ns = mux(_T_2257, io.dec_csr_wrdata_r, _T_2258) @[dec_tlu_ctl.scala 2396:21] + node _T_2259 = bits(mhpmc5_wr_en, 0, 0) @[dec_tlu_ctl.scala 2398:43] inst rvclkhdr_30 of rvclkhdr_750 @[lib.scala 368:23] rvclkhdr_30.clock <= clock rvclkhdr_30.reset <= reset rvclkhdr_30.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_30.io.en <= _T_2258 @[lib.scala 371:17] + rvclkhdr_30.io.en <= _T_2259 @[lib.scala 371:17] rvclkhdr_30.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_2259 : UInt, rvclkhdr_30.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_2259 <= mhpmc5_ns @[lib.scala 374:16] - mhpmc5 <= _T_2259 @[dec_tlu_ctl.scala 2398:9] - node _T_2260 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2400:66] - node _T_2261 = eq(_T_2260, UInt<12>("h0b85")) @[dec_tlu_ctl.scala 2400:73] - node mhpmc5h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2261) @[dec_tlu_ctl.scala 2400:44] + reg _T_2260 : UInt, rvclkhdr_30.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2260 <= mhpmc5_ns @[lib.scala 374:16] + mhpmc5 <= _T_2260 @[dec_tlu_ctl.scala 2398:9] + node _T_2261 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2400:66] + node _T_2262 = eq(_T_2261, UInt<12>("h0b85")) @[dec_tlu_ctl.scala 2400:73] + node mhpmc5h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2262) @[dec_tlu_ctl.scala 2400:44] node mhpmc5h_wr_en = or(mhpmc5h_wr_en0, mhpmc5_wr_en1) @[dec_tlu_ctl.scala 2401:38] - node _T_2262 = bits(mhpmc5h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2402:38] - node _T_2263 = bits(mhpmc5_incr, 63, 32) @[dec_tlu_ctl.scala 2402:78] - node mhpmc5h_ns = mux(_T_2262, io.dec_csr_wrdata_r, _T_2263) @[dec_tlu_ctl.scala 2402:22] - node _T_2264 = bits(mhpmc5h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2404:46] + node _T_2263 = bits(mhpmc5h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2402:38] + node _T_2264 = bits(mhpmc5_incr, 63, 32) @[dec_tlu_ctl.scala 2402:78] + node mhpmc5h_ns = mux(_T_2263, io.dec_csr_wrdata_r, _T_2264) @[dec_tlu_ctl.scala 2402:22] + node _T_2265 = bits(mhpmc5h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2404:46] inst rvclkhdr_31 of rvclkhdr_751 @[lib.scala 368:23] rvclkhdr_31.clock <= clock rvclkhdr_31.reset <= reset rvclkhdr_31.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_31.io.en <= _T_2264 @[lib.scala 371:17] + rvclkhdr_31.io.en <= _T_2265 @[lib.scala 371:17] rvclkhdr_31.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_2265 : UInt, rvclkhdr_31.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_2265 <= mhpmc5h_ns @[lib.scala 374:16] - mhpmc5h <= _T_2265 @[dec_tlu_ctl.scala 2404:10] - node _T_2266 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2409:65] - node _T_2267 = eq(_T_2266, UInt<12>("h0b06")) @[dec_tlu_ctl.scala 2409:72] - node mhpmc6_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2267) @[dec_tlu_ctl.scala 2409:43] - node _T_2268 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2410:23] - node _T_2269 = bits(perfcnt_during_sleep, 3, 3) @[dec_tlu_ctl.scala 2410:61] - node _T_2270 = or(_T_2268, _T_2269) @[dec_tlu_ctl.scala 2410:39] - node _T_2271 = orr(mhpmc_inc_r[3]) @[dec_tlu_ctl.scala 2410:86] - node mhpmc6_wr_en1 = and(_T_2270, _T_2271) @[dec_tlu_ctl.scala 2410:66] + reg _T_2266 : UInt, rvclkhdr_31.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2266 <= mhpmc5h_ns @[lib.scala 374:16] + mhpmc5h <= _T_2266 @[dec_tlu_ctl.scala 2404:10] + node _T_2267 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2409:65] + node _T_2268 = eq(_T_2267, UInt<12>("h0b06")) @[dec_tlu_ctl.scala 2409:72] + node mhpmc6_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2268) @[dec_tlu_ctl.scala 2409:43] + node _T_2269 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2410:23] + node _T_2270 = bits(perfcnt_during_sleep, 3, 3) @[dec_tlu_ctl.scala 2410:61] + node _T_2271 = or(_T_2269, _T_2270) @[dec_tlu_ctl.scala 2410:39] + node _T_2272 = orr(mhpmc_inc_r[3]) @[dec_tlu_ctl.scala 2410:86] + node mhpmc6_wr_en1 = and(_T_2271, _T_2272) @[dec_tlu_ctl.scala 2410:66] node mhpmc6_wr_en = or(mhpmc6_wr_en0, mhpmc6_wr_en1) @[dec_tlu_ctl.scala 2411:36] - node _T_2272 = bits(mhpmc6h, 31, 0) @[dec_tlu_ctl.scala 2413:28] - node _T_2273 = bits(mhpmc6, 31, 0) @[dec_tlu_ctl.scala 2413:41] - node _T_2274 = cat(_T_2272, _T_2273) @[Cat.scala 29:58] - node _T_2275 = cat(UInt<63>("h00"), mhpmc_inc_r[3]) @[Cat.scala 29:58] - node _T_2276 = add(_T_2274, _T_2275) @[dec_tlu_ctl.scala 2413:49] - node _T_2277 = tail(_T_2276, 1) @[dec_tlu_ctl.scala 2413:49] - mhpmc6_incr <= _T_2277 @[dec_tlu_ctl.scala 2413:14] - node _T_2278 = bits(mhpmc6_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2414:36] - node _T_2279 = bits(mhpmc6_incr, 31, 0) @[dec_tlu_ctl.scala 2414:76] - node mhpmc6_ns = mux(_T_2278, io.dec_csr_wrdata_r, _T_2279) @[dec_tlu_ctl.scala 2414:21] - node _T_2280 = bits(mhpmc6_wr_en, 0, 0) @[dec_tlu_ctl.scala 2416:43] + node _T_2273 = bits(mhpmc6h, 31, 0) @[dec_tlu_ctl.scala 2413:28] + node _T_2274 = bits(mhpmc6, 31, 0) @[dec_tlu_ctl.scala 2413:41] + node _T_2275 = cat(_T_2273, _T_2274) @[Cat.scala 29:58] + node _T_2276 = cat(UInt<63>("h00"), mhpmc_inc_r[3]) @[Cat.scala 29:58] + node _T_2277 = add(_T_2275, _T_2276) @[dec_tlu_ctl.scala 2413:49] + node _T_2278 = tail(_T_2277, 1) @[dec_tlu_ctl.scala 2413:49] + mhpmc6_incr <= _T_2278 @[dec_tlu_ctl.scala 2413:14] + node _T_2279 = bits(mhpmc6_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2414:36] + node _T_2280 = bits(mhpmc6_incr, 31, 0) @[dec_tlu_ctl.scala 2414:76] + node mhpmc6_ns = mux(_T_2279, io.dec_csr_wrdata_r, _T_2280) @[dec_tlu_ctl.scala 2414:21] + node _T_2281 = bits(mhpmc6_wr_en, 0, 0) @[dec_tlu_ctl.scala 2416:43] inst rvclkhdr_32 of rvclkhdr_752 @[lib.scala 368:23] rvclkhdr_32.clock <= clock rvclkhdr_32.reset <= reset rvclkhdr_32.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_32.io.en <= _T_2280 @[lib.scala 371:17] + rvclkhdr_32.io.en <= _T_2281 @[lib.scala 371:17] rvclkhdr_32.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_2281 : UInt, rvclkhdr_32.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_2281 <= mhpmc6_ns @[lib.scala 374:16] - mhpmc6 <= _T_2281 @[dec_tlu_ctl.scala 2416:9] - node _T_2282 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2418:66] - node _T_2283 = eq(_T_2282, UInt<12>("h0b86")) @[dec_tlu_ctl.scala 2418:73] - node mhpmc6h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2283) @[dec_tlu_ctl.scala 2418:44] + reg _T_2282 : UInt, rvclkhdr_32.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2282 <= mhpmc6_ns @[lib.scala 374:16] + mhpmc6 <= _T_2282 @[dec_tlu_ctl.scala 2416:9] + node _T_2283 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2418:66] + node _T_2284 = eq(_T_2283, UInt<12>("h0b86")) @[dec_tlu_ctl.scala 2418:73] + node mhpmc6h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2284) @[dec_tlu_ctl.scala 2418:44] node mhpmc6h_wr_en = or(mhpmc6h_wr_en0, mhpmc6_wr_en1) @[dec_tlu_ctl.scala 2419:38] - node _T_2284 = bits(mhpmc6h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2420:38] - node _T_2285 = bits(mhpmc6_incr, 63, 32) @[dec_tlu_ctl.scala 2420:78] - node mhpmc6h_ns = mux(_T_2284, io.dec_csr_wrdata_r, _T_2285) @[dec_tlu_ctl.scala 2420:22] - node _T_2286 = bits(mhpmc6h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2422:46] + node _T_2285 = bits(mhpmc6h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2420:38] + node _T_2286 = bits(mhpmc6_incr, 63, 32) @[dec_tlu_ctl.scala 2420:78] + node mhpmc6h_ns = mux(_T_2285, io.dec_csr_wrdata_r, _T_2286) @[dec_tlu_ctl.scala 2420:22] + node _T_2287 = bits(mhpmc6h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2422:46] inst rvclkhdr_33 of rvclkhdr_753 @[lib.scala 368:23] rvclkhdr_33.clock <= clock rvclkhdr_33.reset <= reset rvclkhdr_33.io.clk <= clock @[lib.scala 370:18] - rvclkhdr_33.io.en <= _T_2286 @[lib.scala 371:17] + rvclkhdr_33.io.en <= _T_2287 @[lib.scala 371:17] rvclkhdr_33.io.scan_mode <= io.scan_mode @[lib.scala 372:24] - reg _T_2287 : UInt, rvclkhdr_33.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] - _T_2287 <= mhpmc6h_ns @[lib.scala 374:16] - mhpmc6h <= _T_2287 @[dec_tlu_ctl.scala 2422:10] - node _T_2288 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2429:50] - node _T_2289 = gt(_T_2288, UInt<10>("h0204")) @[dec_tlu_ctl.scala 2429:56] - node _T_2290 = bits(io.dec_csr_wrdata_r, 31, 10) @[dec_tlu_ctl.scala 2429:93] - node _T_2291 = orr(_T_2290) @[dec_tlu_ctl.scala 2429:102] - node _T_2292 = or(_T_2289, _T_2291) @[dec_tlu_ctl.scala 2429:71] - node _T_2293 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2429:141] - node event_saturate_r = mux(_T_2292, UInt<10>("h0204"), _T_2293) @[dec_tlu_ctl.scala 2429:28] - node _T_2294 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2431:63] - node _T_2295 = eq(_T_2294, UInt<12>("h0323")) @[dec_tlu_ctl.scala 2431:70] - node wr_mhpme3_r = and(io.dec_csr_wen_r_mod, _T_2295) @[dec_tlu_ctl.scala 2431:41] - node _T_2296 = bits(wr_mhpme3_r, 0, 0) @[dec_tlu_ctl.scala 2433:80] - reg _T_2297 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_2296 : @[Reg.scala 28:19] - _T_2297 <= event_saturate_r @[Reg.scala 28:23] + reg _T_2288 : UInt, rvclkhdr_33.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_2288 <= mhpmc6h_ns @[lib.scala 374:16] + mhpmc6h <= _T_2288 @[dec_tlu_ctl.scala 2422:10] + node _T_2289 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2429:50] + node _T_2290 = gt(_T_2289, UInt<10>("h0204")) @[dec_tlu_ctl.scala 2429:56] + node _T_2291 = bits(io.dec_csr_wrdata_r, 31, 10) @[dec_tlu_ctl.scala 2429:93] + node _T_2292 = orr(_T_2291) @[dec_tlu_ctl.scala 2429:102] + node _T_2293 = or(_T_2290, _T_2292) @[dec_tlu_ctl.scala 2429:71] + node _T_2294 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2429:141] + node event_saturate_r = mux(_T_2293, UInt<10>("h0204"), _T_2294) @[dec_tlu_ctl.scala 2429:28] + node _T_2295 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2431:63] + node _T_2296 = eq(_T_2295, UInt<12>("h0323")) @[dec_tlu_ctl.scala 2431:70] + node wr_mhpme3_r = and(io.dec_csr_wen_r_mod, _T_2296) @[dec_tlu_ctl.scala 2431:41] + node _T_2297 = bits(wr_mhpme3_r, 0, 0) @[dec_tlu_ctl.scala 2433:80] + reg _T_2298 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_2297 : @[Reg.scala 28:19] + _T_2298 <= event_saturate_r @[Reg.scala 28:23] skip @[Reg.scala 28:19] - mhpme3 <= _T_2297 @[dec_tlu_ctl.scala 2433:9] - node _T_2298 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2438:63] - node _T_2299 = eq(_T_2298, UInt<12>("h0324")) @[dec_tlu_ctl.scala 2438:70] - node wr_mhpme4_r = and(io.dec_csr_wen_r_mod, _T_2299) @[dec_tlu_ctl.scala 2438:41] - node _T_2300 = bits(wr_mhpme4_r, 0, 0) @[dec_tlu_ctl.scala 2439:80] - reg _T_2301 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_2300 : @[Reg.scala 28:19] - _T_2301 <= event_saturate_r @[Reg.scala 28:23] + mhpme3 <= _T_2298 @[dec_tlu_ctl.scala 2433:9] + node _T_2299 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2438:63] + node _T_2300 = eq(_T_2299, UInt<12>("h0324")) @[dec_tlu_ctl.scala 2438:70] + node wr_mhpme4_r = and(io.dec_csr_wen_r_mod, _T_2300) @[dec_tlu_ctl.scala 2438:41] + node _T_2301 = bits(wr_mhpme4_r, 0, 0) @[dec_tlu_ctl.scala 2439:80] + reg _T_2302 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_2301 : @[Reg.scala 28:19] + _T_2302 <= event_saturate_r @[Reg.scala 28:23] skip @[Reg.scala 28:19] - mhpme4 <= _T_2301 @[dec_tlu_ctl.scala 2439:9] - node _T_2302 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2445:63] - node _T_2303 = eq(_T_2302, UInt<12>("h0325")) @[dec_tlu_ctl.scala 2445:70] - node wr_mhpme5_r = and(io.dec_csr_wen_r_mod, _T_2303) @[dec_tlu_ctl.scala 2445:41] - node _T_2304 = bits(wr_mhpme5_r, 0, 0) @[dec_tlu_ctl.scala 2446:80] - reg _T_2305 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_2304 : @[Reg.scala 28:19] - _T_2305 <= event_saturate_r @[Reg.scala 28:23] + mhpme4 <= _T_2302 @[dec_tlu_ctl.scala 2439:9] + node _T_2303 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2445:63] + node _T_2304 = eq(_T_2303, UInt<12>("h0325")) @[dec_tlu_ctl.scala 2445:70] + node wr_mhpme5_r = and(io.dec_csr_wen_r_mod, _T_2304) @[dec_tlu_ctl.scala 2445:41] + node _T_2305 = bits(wr_mhpme5_r, 0, 0) @[dec_tlu_ctl.scala 2446:80] + reg _T_2306 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_2305 : @[Reg.scala 28:19] + _T_2306 <= event_saturate_r @[Reg.scala 28:23] skip @[Reg.scala 28:19] - mhpme5 <= _T_2305 @[dec_tlu_ctl.scala 2446:9] - node _T_2306 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2452:63] - node _T_2307 = eq(_T_2306, UInt<12>("h0326")) @[dec_tlu_ctl.scala 2452:70] - node wr_mhpme6_r = and(io.dec_csr_wen_r_mod, _T_2307) @[dec_tlu_ctl.scala 2452:41] - node _T_2308 = bits(wr_mhpme6_r, 0, 0) @[dec_tlu_ctl.scala 2453:80] - reg _T_2309 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_2308 : @[Reg.scala 28:19] - _T_2309 <= event_saturate_r @[Reg.scala 28:23] + mhpme5 <= _T_2306 @[dec_tlu_ctl.scala 2446:9] + node _T_2307 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2452:63] + node _T_2308 = eq(_T_2307, UInt<12>("h0326")) @[dec_tlu_ctl.scala 2452:70] + node wr_mhpme6_r = and(io.dec_csr_wen_r_mod, _T_2308) @[dec_tlu_ctl.scala 2452:41] + node _T_2309 = bits(wr_mhpme6_r, 0, 0) @[dec_tlu_ctl.scala 2453:80] + reg _T_2310 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_2309 : @[Reg.scala 28:19] + _T_2310 <= event_saturate_r @[Reg.scala 28:23] skip @[Reg.scala 28:19] - mhpme6 <= _T_2309 @[dec_tlu_ctl.scala 2453:9] - node _T_2310 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2469:70] - node _T_2311 = eq(_T_2310, UInt<12>("h0320")) @[dec_tlu_ctl.scala 2469:77] - node wr_mcountinhibit_r = and(io.dec_csr_wen_r_mod, _T_2311) @[dec_tlu_ctl.scala 2469:48] - node _T_2312 = bits(mcountinhibit, 0, 0) @[dec_tlu_ctl.scala 2471:54] + mhpme6 <= _T_2310 @[dec_tlu_ctl.scala 2453:9] + node _T_2311 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2469:70] + node _T_2312 = eq(_T_2311, UInt<12>("h0320")) @[dec_tlu_ctl.scala 2469:77] + node wr_mcountinhibit_r = and(io.dec_csr_wen_r_mod, _T_2312) @[dec_tlu_ctl.scala 2469:48] + node _T_2313 = bits(mcountinhibit, 0, 0) @[dec_tlu_ctl.scala 2471:54] wire temp_ncount0 : UInt<1> - temp_ncount0 <= _T_2312 - node _T_2313 = bits(mcountinhibit, 1, 1) @[dec_tlu_ctl.scala 2472:54] + temp_ncount0 <= _T_2313 + node _T_2314 = bits(mcountinhibit, 1, 1) @[dec_tlu_ctl.scala 2472:54] wire temp_ncount1 : UInt<1> - temp_ncount1 <= _T_2313 - node _T_2314 = bits(mcountinhibit, 6, 2) @[dec_tlu_ctl.scala 2473:55] + temp_ncount1 <= _T_2314 + node _T_2315 = bits(mcountinhibit, 6, 2) @[dec_tlu_ctl.scala 2473:55] wire temp_ncount6_2 : UInt<5> - temp_ncount6_2 <= _T_2314 - node _T_2315 = bits(io.dec_csr_wrdata_r, 6, 2) @[dec_tlu_ctl.scala 2474:74] - node _T_2316 = bits(wr_mcountinhibit_r, 0, 0) @[dec_tlu_ctl.scala 2474:103] - reg _T_2317 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_2316 : @[Reg.scala 28:19] - _T_2317 <= _T_2315 @[Reg.scala 28:23] + temp_ncount6_2 <= _T_2315 + node _T_2316 = bits(io.dec_csr_wrdata_r, 6, 2) @[dec_tlu_ctl.scala 2474:74] + node _T_2317 = bits(wr_mcountinhibit_r, 0, 0) @[dec_tlu_ctl.scala 2474:103] + reg _T_2318 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_2317 : @[Reg.scala 28:19] + _T_2318 <= _T_2316 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - temp_ncount6_2 <= _T_2317 @[dec_tlu_ctl.scala 2474:17] - node _T_2318 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 2476:72] - node _T_2319 = bits(wr_mcountinhibit_r, 0, 0) @[dec_tlu_ctl.scala 2476:99] - reg _T_2320 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_2319 : @[Reg.scala 28:19] - _T_2320 <= _T_2318 @[Reg.scala 28:23] + temp_ncount6_2 <= _T_2318 @[dec_tlu_ctl.scala 2474:17] + node _T_2319 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 2476:72] + node _T_2320 = bits(wr_mcountinhibit_r, 0, 0) @[dec_tlu_ctl.scala 2476:99] + reg _T_2321 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_2320 : @[Reg.scala 28:19] + _T_2321 <= _T_2319 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - temp_ncount0 <= _T_2320 @[dec_tlu_ctl.scala 2476:15] - node _T_2321 = cat(temp_ncount6_2, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2322 = cat(_T_2321, temp_ncount0) @[Cat.scala 29:58] - mcountinhibit <= _T_2322 @[dec_tlu_ctl.scala 2477:16] - node _T_2323 = or(io.i0_valid_wb, io.exc_or_int_valid_r_d1) @[dec_tlu_ctl.scala 2484:51] - node _T_2324 = or(_T_2323, io.interrupt_valid_r_d1) @[dec_tlu_ctl.scala 2484:78] - node _T_2325 = or(_T_2324, io.dec_tlu_i0_valid_wb1) @[dec_tlu_ctl.scala 2484:104] - node _T_2326 = or(_T_2325, io.dec_tlu_i0_exc_valid_wb1) @[dec_tlu_ctl.scala 2484:130] - node _T_2327 = or(_T_2326, io.dec_tlu_int_valid_wb1) @[dec_tlu_ctl.scala 2485:32] - node _T_2328 = or(_T_2327, io.clk_override) @[dec_tlu_ctl.scala 2485:59] - node _T_2329 = bits(_T_2328, 0, 0) @[dec_tlu_ctl.scala 2485:78] + temp_ncount0 <= _T_2321 @[dec_tlu_ctl.scala 2476:15] + node _T_2322 = cat(temp_ncount6_2, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2323 = cat(_T_2322, temp_ncount0) @[Cat.scala 29:58] + mcountinhibit <= _T_2323 @[dec_tlu_ctl.scala 2477:16] + node _T_2324 = or(io.i0_valid_wb, io.exc_or_int_valid_r_d1) @[dec_tlu_ctl.scala 2484:51] + node _T_2325 = or(_T_2324, io.interrupt_valid_r_d1) @[dec_tlu_ctl.scala 2484:78] + node _T_2326 = or(_T_2325, io.dec_tlu_i0_valid_wb1) @[dec_tlu_ctl.scala 2484:104] + node _T_2327 = or(_T_2326, io.dec_tlu_i0_exc_valid_wb1) @[dec_tlu_ctl.scala 2484:130] + node _T_2328 = or(_T_2327, io.dec_tlu_int_valid_wb1) @[dec_tlu_ctl.scala 2485:32] + node _T_2329 = or(_T_2328, io.clk_override) @[dec_tlu_ctl.scala 2485:59] + node _T_2330 = bits(_T_2329, 0, 0) @[dec_tlu_ctl.scala 2485:78] inst rvclkhdr_34 of rvclkhdr_754 @[lib.scala 343:22] rvclkhdr_34.clock <= clock rvclkhdr_34.reset <= reset rvclkhdr_34.io.clk <= clock @[lib.scala 344:17] - rvclkhdr_34.io.en <= _T_2329 @[lib.scala 345:16] + rvclkhdr_34.io.en <= _T_2330 @[lib.scala 345:16] rvclkhdr_34.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - reg _T_2330 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2487:62] - _T_2330 <= io.i0_valid_wb @[dec_tlu_ctl.scala 2487:62] - io.dec_tlu_i0_valid_wb1 <= _T_2330 @[dec_tlu_ctl.scala 2487:30] - node _T_2331 = or(io.i0_exception_valid_r_d1, io.lsu_i0_exc_r_d1) @[dec_tlu_ctl.scala 2488:91] - node _T_2332 = not(io.trigger_hit_dmode_r_d1) @[dec_tlu_ctl.scala 2488:137] - node _T_2333 = and(io.trigger_hit_r_d1, _T_2332) @[dec_tlu_ctl.scala 2488:135] - node _T_2334 = or(_T_2331, _T_2333) @[dec_tlu_ctl.scala 2488:112] - reg _T_2335 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2488:62] - _T_2335 <= _T_2334 @[dec_tlu_ctl.scala 2488:62] - io.dec_tlu_i0_exc_valid_wb1 <= _T_2335 @[dec_tlu_ctl.scala 2488:30] - reg _T_2336 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2489:62] - _T_2336 <= io.exc_cause_wb @[dec_tlu_ctl.scala 2489:62] - io.dec_tlu_exc_cause_wb1 <= _T_2336 @[dec_tlu_ctl.scala 2489:30] - reg _T_2337 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2490:62] - _T_2337 <= io.interrupt_valid_r_d1 @[dec_tlu_ctl.scala 2490:62] - io.dec_tlu_int_valid_wb1 <= _T_2337 @[dec_tlu_ctl.scala 2490:30] + reg _T_2331 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2487:62] + _T_2331 <= io.i0_valid_wb @[dec_tlu_ctl.scala 2487:62] + io.dec_tlu_i0_valid_wb1 <= _T_2331 @[dec_tlu_ctl.scala 2487:30] + node _T_2332 = or(io.i0_exception_valid_r_d1, io.lsu_i0_exc_r_d1) @[dec_tlu_ctl.scala 2488:91] + node _T_2333 = not(io.trigger_hit_dmode_r_d1) @[dec_tlu_ctl.scala 2488:137] + node _T_2334 = and(io.trigger_hit_r_d1, _T_2333) @[dec_tlu_ctl.scala 2488:135] + node _T_2335 = or(_T_2332, _T_2334) @[dec_tlu_ctl.scala 2488:112] + reg _T_2336 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2488:62] + _T_2336 <= _T_2335 @[dec_tlu_ctl.scala 2488:62] + io.dec_tlu_i0_exc_valid_wb1 <= _T_2336 @[dec_tlu_ctl.scala 2488:30] + reg _T_2337 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2489:62] + _T_2337 <= io.exc_cause_wb @[dec_tlu_ctl.scala 2489:62] + io.dec_tlu_exc_cause_wb1 <= _T_2337 @[dec_tlu_ctl.scala 2489:30] + reg _T_2338 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2490:62] + _T_2338 <= io.interrupt_valid_r_d1 @[dec_tlu_ctl.scala 2490:62] + io.dec_tlu_int_valid_wb1 <= _T_2338 @[dec_tlu_ctl.scala 2490:30] io.dec_tlu_mtval_wb1 <= mtval @[dec_tlu_ctl.scala 2492:24] - node _T_2338 = bits(io.csr_pkt.csr_misa, 0, 0) @[dec_tlu_ctl.scala 2498:61] - node _T_2339 = bits(io.csr_pkt.csr_mvendorid, 0, 0) @[dec_tlu_ctl.scala 2499:42] - node _T_2340 = bits(io.csr_pkt.csr_marchid, 0, 0) @[dec_tlu_ctl.scala 2500:40] - node _T_2341 = bits(io.csr_pkt.csr_mimpid, 0, 0) @[dec_tlu_ctl.scala 2501:39] - node _T_2342 = bits(io.csr_pkt.csr_mhartid, 0, 0) @[dec_tlu_ctl.scala 2502:40] - node _T_2343 = cat(io.core_id, UInt<4>("h00")) @[Cat.scala 29:58] - node _T_2344 = bits(io.csr_pkt.csr_mstatus, 0, 0) @[dec_tlu_ctl.scala 2503:40] - node _T_2345 = bits(io.mstatus, 1, 1) @[dec_tlu_ctl.scala 2503:103] - node _T_2346 = bits(io.mstatus, 0, 0) @[dec_tlu_ctl.scala 2503:128] - node _T_2347 = cat(UInt<3>("h00"), _T_2346) @[Cat.scala 29:58] - node _T_2348 = cat(_T_2347, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2349 = cat(UInt<3>("h00"), _T_2345) @[Cat.scala 29:58] - node _T_2350 = cat(UInt<19>("h00"), UInt<2>("h03")) @[Cat.scala 29:58] - node _T_2351 = cat(_T_2350, _T_2349) @[Cat.scala 29:58] - node _T_2352 = cat(_T_2351, _T_2348) @[Cat.scala 29:58] - node _T_2353 = bits(io.csr_pkt.csr_mtvec, 0, 0) @[dec_tlu_ctl.scala 2504:38] - node _T_2354 = bits(io.mtvec, 30, 1) @[dec_tlu_ctl.scala 2504:70] - node _T_2355 = bits(io.mtvec, 0, 0) @[dec_tlu_ctl.scala 2504:96] - node _T_2356 = cat(_T_2354, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2357 = cat(_T_2356, _T_2355) @[Cat.scala 29:58] - node _T_2358 = bits(io.csr_pkt.csr_mip, 0, 0) @[dec_tlu_ctl.scala 2505:36] - node _T_2359 = bits(io.mip, 5, 3) @[dec_tlu_ctl.scala 2505:78] - node _T_2360 = bits(io.mip, 2, 2) @[dec_tlu_ctl.scala 2505:102] - node _T_2361 = bits(io.mip, 1, 1) @[dec_tlu_ctl.scala 2505:123] - node _T_2362 = bits(io.mip, 0, 0) @[dec_tlu_ctl.scala 2505:144] - node _T_2363 = cat(_T_2362, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2364 = cat(_T_2361, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2365 = cat(_T_2364, _T_2363) @[Cat.scala 29:58] - node _T_2366 = cat(_T_2360, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2367 = cat(UInt<1>("h00"), _T_2359) @[Cat.scala 29:58] - node _T_2368 = cat(_T_2367, UInt<16>("h00")) @[Cat.scala 29:58] - node _T_2369 = cat(_T_2368, _T_2366) @[Cat.scala 29:58] - node _T_2370 = cat(_T_2369, _T_2365) @[Cat.scala 29:58] - node _T_2371 = bits(io.csr_pkt.csr_mie, 0, 0) @[dec_tlu_ctl.scala 2506:36] - node _T_2372 = bits(mie, 5, 3) @[dec_tlu_ctl.scala 2506:75] - node _T_2373 = bits(mie, 2, 2) @[dec_tlu_ctl.scala 2506:96] - node _T_2374 = bits(mie, 1, 1) @[dec_tlu_ctl.scala 2506:114] - node _T_2375 = bits(mie, 0, 0) @[dec_tlu_ctl.scala 2506:132] - node _T_2376 = cat(_T_2375, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2377 = cat(_T_2374, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2378 = cat(_T_2377, _T_2376) @[Cat.scala 29:58] - node _T_2379 = cat(_T_2373, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2380 = cat(UInt<1>("h00"), _T_2372) @[Cat.scala 29:58] - node _T_2381 = cat(_T_2380, UInt<16>("h00")) @[Cat.scala 29:58] - node _T_2382 = cat(_T_2381, _T_2379) @[Cat.scala 29:58] - node _T_2383 = cat(_T_2382, _T_2378) @[Cat.scala 29:58] - node _T_2384 = bits(io.csr_pkt.csr_mcyclel, 0, 0) @[dec_tlu_ctl.scala 2507:40] - node _T_2385 = bits(mcyclel, 31, 0) @[dec_tlu_ctl.scala 2507:65] - node _T_2386 = bits(io.csr_pkt.csr_mcycleh, 0, 0) @[dec_tlu_ctl.scala 2508:40] - node _T_2387 = bits(mcycleh_inc, 31, 0) @[dec_tlu_ctl.scala 2508:69] - node _T_2388 = bits(io.csr_pkt.csr_minstretl, 0, 0) @[dec_tlu_ctl.scala 2509:42] - node _T_2389 = bits(minstretl, 31, 0) @[dec_tlu_ctl.scala 2509:72] - node _T_2390 = bits(io.csr_pkt.csr_minstreth, 0, 0) @[dec_tlu_ctl.scala 2510:42] - node _T_2391 = bits(minstreth_inc, 31, 0) @[dec_tlu_ctl.scala 2510:72] - node _T_2392 = bits(io.csr_pkt.csr_mscratch, 0, 0) @[dec_tlu_ctl.scala 2511:41] - node _T_2393 = bits(mscratch, 31, 0) @[dec_tlu_ctl.scala 2511:66] - node _T_2394 = bits(io.csr_pkt.csr_mepc, 0, 0) @[dec_tlu_ctl.scala 2512:37] - node _T_2395 = cat(io.mepc, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2396 = bits(io.csr_pkt.csr_mcause, 0, 0) @[dec_tlu_ctl.scala 2513:39] - node _T_2397 = bits(mcause, 31, 0) @[dec_tlu_ctl.scala 2513:64] - node _T_2398 = bits(io.csr_pkt.csr_mscause, 0, 0) @[dec_tlu_ctl.scala 2514:40] - node _T_2399 = bits(mscause, 3, 0) @[dec_tlu_ctl.scala 2514:80] - node _T_2400 = cat(UInt<28>("h00"), _T_2399) @[Cat.scala 29:58] - node _T_2401 = bits(io.csr_pkt.csr_mtval, 0, 0) @[dec_tlu_ctl.scala 2515:38] - node _T_2402 = bits(mtval, 31, 0) @[dec_tlu_ctl.scala 2515:63] - node _T_2403 = bits(io.csr_pkt.csr_mrac, 0, 0) @[dec_tlu_ctl.scala 2516:37] - node _T_2404 = bits(mrac, 31, 0) @[dec_tlu_ctl.scala 2516:62] - node _T_2405 = bits(io.csr_pkt.csr_mdseac, 0, 0) @[dec_tlu_ctl.scala 2517:39] - node _T_2406 = bits(mdseac, 31, 0) @[dec_tlu_ctl.scala 2517:64] - node _T_2407 = bits(io.csr_pkt.csr_meivt, 0, 0) @[dec_tlu_ctl.scala 2518:38] - node _T_2408 = cat(meivt, UInt<10>("h00")) @[Cat.scala 29:58] - node _T_2409 = bits(io.csr_pkt.csr_meihap, 0, 0) @[dec_tlu_ctl.scala 2519:39] - node _T_2410 = cat(meivt, meihap) @[Cat.scala 29:58] - node _T_2411 = cat(_T_2410, UInt<2>("h00")) @[Cat.scala 29:58] - node _T_2412 = bits(io.csr_pkt.csr_meicurpl, 0, 0) @[dec_tlu_ctl.scala 2520:41] - node _T_2413 = bits(meicurpl, 3, 0) @[dec_tlu_ctl.scala 2520:81] - node _T_2414 = cat(UInt<28>("h00"), _T_2413) @[Cat.scala 29:58] - node _T_2415 = bits(io.csr_pkt.csr_meicidpl, 0, 0) @[dec_tlu_ctl.scala 2521:41] - node _T_2416 = bits(meicidpl, 3, 0) @[dec_tlu_ctl.scala 2521:81] - node _T_2417 = cat(UInt<28>("h00"), _T_2416) @[Cat.scala 29:58] - node _T_2418 = bits(io.csr_pkt.csr_meipt, 0, 0) @[dec_tlu_ctl.scala 2522:38] - node _T_2419 = bits(meipt, 3, 0) @[dec_tlu_ctl.scala 2522:78] - node _T_2420 = cat(UInt<28>("h00"), _T_2419) @[Cat.scala 29:58] - node _T_2421 = bits(io.csr_pkt.csr_mcgc, 0, 0) @[dec_tlu_ctl.scala 2523:37] - node _T_2422 = bits(mcgc, 8, 0) @[dec_tlu_ctl.scala 2523:77] - node _T_2423 = cat(UInt<23>("h00"), _T_2422) @[Cat.scala 29:58] - node _T_2424 = bits(io.csr_pkt.csr_mfdc, 0, 0) @[dec_tlu_ctl.scala 2524:37] - node _T_2425 = bits(mfdc, 18, 0) @[dec_tlu_ctl.scala 2524:77] - node _T_2426 = cat(UInt<13>("h00"), _T_2425) @[Cat.scala 29:58] - node _T_2427 = bits(io.csr_pkt.csr_dcsr, 0, 0) @[dec_tlu_ctl.scala 2525:37] - node _T_2428 = bits(io.dcsr, 15, 2) @[dec_tlu_ctl.scala 2525:85] - node _T_2429 = cat(UInt<16>("h04000"), _T_2428) @[Cat.scala 29:58] - node _T_2430 = cat(_T_2429, UInt<2>("h03")) @[Cat.scala 29:58] - node _T_2431 = bits(io.csr_pkt.csr_dpc, 0, 0) @[dec_tlu_ctl.scala 2526:36] - node _T_2432 = cat(io.dpc, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2433 = bits(io.csr_pkt.csr_dicad0, 0, 0) @[dec_tlu_ctl.scala 2527:39] - node _T_2434 = bits(dicad0, 31, 0) @[dec_tlu_ctl.scala 2527:64] - node _T_2435 = bits(io.csr_pkt.csr_dicad0h, 0, 0) @[dec_tlu_ctl.scala 2528:40] - node _T_2436 = bits(dicad0h, 31, 0) @[dec_tlu_ctl.scala 2528:65] - node _T_2437 = bits(io.csr_pkt.csr_dicad1, 0, 0) @[dec_tlu_ctl.scala 2529:39] - node _T_2438 = bits(dicad1, 31, 0) @[dec_tlu_ctl.scala 2529:64] - node _T_2439 = bits(io.csr_pkt.csr_dicawics, 0, 0) @[dec_tlu_ctl.scala 2530:41] - node _T_2440 = bits(dicawics, 16, 16) @[dec_tlu_ctl.scala 2530:80] - node _T_2441 = bits(dicawics, 15, 14) @[dec_tlu_ctl.scala 2530:104] - node _T_2442 = bits(dicawics, 13, 0) @[dec_tlu_ctl.scala 2530:131] - node _T_2443 = cat(UInt<3>("h00"), _T_2442) @[Cat.scala 29:58] - node _T_2444 = cat(_T_2443, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_2445 = cat(UInt<2>("h00"), _T_2441) @[Cat.scala 29:58] - node _T_2446 = cat(UInt<7>("h00"), _T_2440) @[Cat.scala 29:58] - node _T_2447 = cat(_T_2446, _T_2445) @[Cat.scala 29:58] - node _T_2448 = cat(_T_2447, _T_2444) @[Cat.scala 29:58] - node _T_2449 = bits(io.csr_pkt.csr_mtsel, 0, 0) @[dec_tlu_ctl.scala 2531:38] - node _T_2450 = bits(mtsel, 1, 0) @[dec_tlu_ctl.scala 2531:78] - node _T_2451 = cat(UInt<30>("h00"), _T_2450) @[Cat.scala 29:58] - node _T_2452 = bits(io.csr_pkt.csr_mtdata1, 0, 0) @[dec_tlu_ctl.scala 2532:40] - node _T_2453 = bits(mtdata1_tsel_out, 31, 0) @[dec_tlu_ctl.scala 2532:74] - node _T_2454 = bits(io.csr_pkt.csr_mtdata2, 0, 0) @[dec_tlu_ctl.scala 2533:40] - node _T_2455 = bits(mtdata2_tsel_out, 31, 0) @[dec_tlu_ctl.scala 2533:74] - node _T_2456 = bits(io.csr_pkt.csr_micect, 0, 0) @[dec_tlu_ctl.scala 2534:39] - node _T_2457 = bits(micect, 31, 0) @[dec_tlu_ctl.scala 2534:64] - node _T_2458 = bits(io.csr_pkt.csr_miccmect, 0, 0) @[dec_tlu_ctl.scala 2535:41] - node _T_2459 = bits(miccmect, 31, 0) @[dec_tlu_ctl.scala 2535:66] - node _T_2460 = bits(io.csr_pkt.csr_mdccmect, 0, 0) @[dec_tlu_ctl.scala 2536:41] - node _T_2461 = bits(mdccmect, 31, 0) @[dec_tlu_ctl.scala 2536:66] - node _T_2462 = bits(io.csr_pkt.csr_mhpmc3, 0, 0) @[dec_tlu_ctl.scala 2537:39] - node _T_2463 = bits(mhpmc3, 31, 0) @[dec_tlu_ctl.scala 2537:64] - node _T_2464 = bits(io.csr_pkt.csr_mhpmc4, 0, 0) @[dec_tlu_ctl.scala 2538:39] - node _T_2465 = bits(mhpmc4, 31, 0) @[dec_tlu_ctl.scala 2538:64] - node _T_2466 = bits(io.csr_pkt.csr_mhpmc5, 0, 0) @[dec_tlu_ctl.scala 2539:39] - node _T_2467 = bits(mhpmc5, 31, 0) @[dec_tlu_ctl.scala 2539:64] - node _T_2468 = bits(io.csr_pkt.csr_mhpmc6, 0, 0) @[dec_tlu_ctl.scala 2540:39] - node _T_2469 = bits(mhpmc6, 31, 0) @[dec_tlu_ctl.scala 2540:64] - node _T_2470 = bits(io.csr_pkt.csr_mhpmc3h, 0, 0) @[dec_tlu_ctl.scala 2541:40] - node _T_2471 = bits(mhpmc3h, 31, 0) @[dec_tlu_ctl.scala 2541:65] - node _T_2472 = bits(io.csr_pkt.csr_mhpmc4h, 0, 0) @[dec_tlu_ctl.scala 2542:40] - node _T_2473 = bits(mhpmc4h, 31, 0) @[dec_tlu_ctl.scala 2542:65] - node _T_2474 = bits(io.csr_pkt.csr_mhpmc5h, 0, 0) @[dec_tlu_ctl.scala 2543:40] - node _T_2475 = bits(mhpmc5h, 31, 0) @[dec_tlu_ctl.scala 2543:65] - node _T_2476 = bits(io.csr_pkt.csr_mhpmc6h, 0, 0) @[dec_tlu_ctl.scala 2544:40] - node _T_2477 = bits(mhpmc6h, 31, 0) @[dec_tlu_ctl.scala 2544:65] - node _T_2478 = bits(io.csr_pkt.csr_mfdht, 0, 0) @[dec_tlu_ctl.scala 2545:38] - node _T_2479 = bits(mfdht, 5, 0) @[dec_tlu_ctl.scala 2545:78] - node _T_2480 = cat(UInt<26>("h00"), _T_2479) @[Cat.scala 29:58] - node _T_2481 = bits(io.csr_pkt.csr_mfdhs, 0, 0) @[dec_tlu_ctl.scala 2546:38] - node _T_2482 = bits(mfdhs, 1, 0) @[dec_tlu_ctl.scala 2546:78] - node _T_2483 = cat(UInt<30>("h00"), _T_2482) @[Cat.scala 29:58] - node _T_2484 = bits(io.csr_pkt.csr_mhpme3, 0, 0) @[dec_tlu_ctl.scala 2547:39] - node _T_2485 = bits(mhpme3, 9, 0) @[dec_tlu_ctl.scala 2547:79] - node _T_2486 = cat(UInt<22>("h00"), _T_2485) @[Cat.scala 29:58] - node _T_2487 = bits(io.csr_pkt.csr_mhpme4, 0, 0) @[dec_tlu_ctl.scala 2548:39] - node _T_2488 = bits(mhpme4, 9, 0) @[dec_tlu_ctl.scala 2548:79] - node _T_2489 = cat(UInt<22>("h00"), _T_2488) @[Cat.scala 29:58] - node _T_2490 = bits(io.csr_pkt.csr_mhpme5, 0, 0) @[dec_tlu_ctl.scala 2549:39] - node _T_2491 = bits(mhpme5, 9, 0) @[dec_tlu_ctl.scala 2549:78] - node _T_2492 = cat(UInt<22>("h00"), _T_2491) @[Cat.scala 29:58] - node _T_2493 = bits(io.csr_pkt.csr_mhpme6, 0, 0) @[dec_tlu_ctl.scala 2550:39] - node _T_2494 = bits(mhpme6, 9, 0) @[dec_tlu_ctl.scala 2550:78] - node _T_2495 = cat(UInt<22>("h00"), _T_2494) @[Cat.scala 29:58] - node _T_2496 = bits(io.csr_pkt.csr_mcountinhibit, 0, 0) @[dec_tlu_ctl.scala 2551:46] - node _T_2497 = bits(mcountinhibit, 6, 0) @[dec_tlu_ctl.scala 2551:86] - node _T_2498 = cat(UInt<25>("h00"), _T_2497) @[Cat.scala 29:58] - node _T_2499 = bits(io.csr_pkt.csr_mpmc, 0, 0) @[dec_tlu_ctl.scala 2552:37] - node _T_2500 = cat(UInt<30>("h00"), mpmc) @[Cat.scala 29:58] - node _T_2501 = cat(_T_2500, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2502 = bits(io.dec_timer_read_d, 0, 0) @[dec_tlu_ctl.scala 2553:37] - node _T_2503 = bits(io.dec_timer_rddata_d, 31, 0) @[dec_tlu_ctl.scala 2553:76] - node _T_2504 = mux(_T_2338, UInt<32>("h040001104"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2505 = mux(_T_2339, UInt<32>("h045"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2506 = mux(_T_2340, UInt<32>("h010"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2507 = mux(_T_2341, UInt<32>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2508 = mux(_T_2342, _T_2343, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2509 = mux(_T_2344, _T_2352, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2510 = mux(_T_2353, _T_2357, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2511 = mux(_T_2358, _T_2370, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2512 = mux(_T_2371, _T_2383, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2513 = mux(_T_2384, _T_2385, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2514 = mux(_T_2386, _T_2387, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2515 = mux(_T_2388, _T_2389, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2516 = mux(_T_2390, _T_2391, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2517 = mux(_T_2392, _T_2393, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2518 = mux(_T_2394, _T_2395, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2519 = mux(_T_2396, _T_2397, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2520 = mux(_T_2398, _T_2400, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2521 = mux(_T_2401, _T_2402, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2522 = mux(_T_2403, _T_2404, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2523 = mux(_T_2405, _T_2406, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2524 = mux(_T_2407, _T_2408, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2525 = mux(_T_2409, _T_2411, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2526 = mux(_T_2412, _T_2414, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2527 = mux(_T_2415, _T_2417, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2528 = mux(_T_2418, _T_2420, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2529 = mux(_T_2421, _T_2423, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2530 = mux(_T_2424, _T_2426, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2531 = mux(_T_2427, _T_2430, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2532 = mux(_T_2431, _T_2432, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2533 = mux(_T_2433, _T_2434, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2534 = mux(_T_2435, _T_2436, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2535 = mux(_T_2437, _T_2438, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2536 = mux(_T_2439, _T_2448, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2537 = mux(_T_2449, _T_2451, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2538 = mux(_T_2452, _T_2453, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2539 = mux(_T_2454, _T_2455, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2540 = mux(_T_2456, _T_2457, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2541 = mux(_T_2458, _T_2459, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2542 = mux(_T_2460, _T_2461, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2543 = mux(_T_2462, _T_2463, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2544 = mux(_T_2464, _T_2465, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2545 = mux(_T_2466, _T_2467, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2546 = mux(_T_2468, _T_2469, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2547 = mux(_T_2470, _T_2471, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2548 = mux(_T_2472, _T_2473, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2549 = mux(_T_2474, _T_2475, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2550 = mux(_T_2476, _T_2477, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2551 = mux(_T_2478, _T_2480, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2552 = mux(_T_2481, _T_2483, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2553 = mux(_T_2484, _T_2486, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2554 = mux(_T_2487, _T_2489, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2555 = mux(_T_2490, _T_2492, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2556 = mux(_T_2493, _T_2495, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2557 = mux(_T_2496, _T_2498, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2558 = mux(_T_2499, _T_2501, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2559 = mux(_T_2502, _T_2503, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2560 = or(_T_2504, _T_2505) @[Mux.scala 27:72] - node _T_2561 = or(_T_2560, _T_2506) @[Mux.scala 27:72] + node _T_2339 = bits(io.csr_pkt.csr_misa, 0, 0) @[dec_tlu_ctl.scala 2498:61] + node _T_2340 = bits(io.csr_pkt.csr_mvendorid, 0, 0) @[dec_tlu_ctl.scala 2499:42] + node _T_2341 = bits(io.csr_pkt.csr_marchid, 0, 0) @[dec_tlu_ctl.scala 2500:40] + node _T_2342 = bits(io.csr_pkt.csr_mimpid, 0, 0) @[dec_tlu_ctl.scala 2501:39] + node _T_2343 = bits(io.csr_pkt.csr_mhartid, 0, 0) @[dec_tlu_ctl.scala 2502:40] + node _T_2344 = cat(io.core_id, UInt<4>("h00")) @[Cat.scala 29:58] + node _T_2345 = bits(io.csr_pkt.csr_mstatus, 0, 0) @[dec_tlu_ctl.scala 2503:40] + node _T_2346 = bits(io.mstatus, 1, 1) @[dec_tlu_ctl.scala 2503:103] + node _T_2347 = bits(io.mstatus, 0, 0) @[dec_tlu_ctl.scala 2503:128] + node _T_2348 = cat(UInt<3>("h00"), _T_2347) @[Cat.scala 29:58] + node _T_2349 = cat(_T_2348, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2350 = cat(UInt<3>("h00"), _T_2346) @[Cat.scala 29:58] + node _T_2351 = cat(UInt<19>("h00"), UInt<2>("h03")) @[Cat.scala 29:58] + node _T_2352 = cat(_T_2351, _T_2350) @[Cat.scala 29:58] + node _T_2353 = cat(_T_2352, _T_2349) @[Cat.scala 29:58] + node _T_2354 = bits(io.csr_pkt.csr_mtvec, 0, 0) @[dec_tlu_ctl.scala 2504:38] + node _T_2355 = bits(io.mtvec, 30, 1) @[dec_tlu_ctl.scala 2504:70] + node _T_2356 = bits(io.mtvec, 0, 0) @[dec_tlu_ctl.scala 2504:96] + node _T_2357 = cat(_T_2355, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2358 = cat(_T_2357, _T_2356) @[Cat.scala 29:58] + node _T_2359 = bits(io.csr_pkt.csr_mip, 0, 0) @[dec_tlu_ctl.scala 2505:36] + node _T_2360 = bits(io.mip, 5, 3) @[dec_tlu_ctl.scala 2505:78] + node _T_2361 = bits(io.mip, 2, 2) @[dec_tlu_ctl.scala 2505:102] + node _T_2362 = bits(io.mip, 1, 1) @[dec_tlu_ctl.scala 2505:123] + node _T_2363 = bits(io.mip, 0, 0) @[dec_tlu_ctl.scala 2505:144] + node _T_2364 = cat(_T_2363, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2365 = cat(_T_2362, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2366 = cat(_T_2365, _T_2364) @[Cat.scala 29:58] + node _T_2367 = cat(_T_2361, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2368 = cat(UInt<1>("h00"), _T_2360) @[Cat.scala 29:58] + node _T_2369 = cat(_T_2368, UInt<16>("h00")) @[Cat.scala 29:58] + node _T_2370 = cat(_T_2369, _T_2367) @[Cat.scala 29:58] + node _T_2371 = cat(_T_2370, _T_2366) @[Cat.scala 29:58] + node _T_2372 = bits(io.csr_pkt.csr_mie, 0, 0) @[dec_tlu_ctl.scala 2506:36] + node _T_2373 = bits(mie, 5, 3) @[dec_tlu_ctl.scala 2506:75] + node _T_2374 = bits(mie, 2, 2) @[dec_tlu_ctl.scala 2506:96] + node _T_2375 = bits(mie, 1, 1) @[dec_tlu_ctl.scala 2506:114] + node _T_2376 = bits(mie, 0, 0) @[dec_tlu_ctl.scala 2506:132] + node _T_2377 = cat(_T_2376, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2378 = cat(_T_2375, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2379 = cat(_T_2378, _T_2377) @[Cat.scala 29:58] + node _T_2380 = cat(_T_2374, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2381 = cat(UInt<1>("h00"), _T_2373) @[Cat.scala 29:58] + node _T_2382 = cat(_T_2381, UInt<16>("h00")) @[Cat.scala 29:58] + node _T_2383 = cat(_T_2382, _T_2380) @[Cat.scala 29:58] + node _T_2384 = cat(_T_2383, _T_2379) @[Cat.scala 29:58] + node _T_2385 = bits(io.csr_pkt.csr_mcyclel, 0, 0) @[dec_tlu_ctl.scala 2507:40] + node _T_2386 = bits(mcyclel, 31, 0) @[dec_tlu_ctl.scala 2507:65] + node _T_2387 = bits(io.csr_pkt.csr_mcycleh, 0, 0) @[dec_tlu_ctl.scala 2508:40] + node _T_2388 = bits(mcycleh_inc, 31, 0) @[dec_tlu_ctl.scala 2508:69] + node _T_2389 = bits(io.csr_pkt.csr_minstretl, 0, 0) @[dec_tlu_ctl.scala 2509:42] + node _T_2390 = bits(minstretl, 31, 0) @[dec_tlu_ctl.scala 2509:72] + node _T_2391 = bits(io.csr_pkt.csr_minstreth, 0, 0) @[dec_tlu_ctl.scala 2510:42] + node _T_2392 = bits(minstreth_inc, 31, 0) @[dec_tlu_ctl.scala 2510:72] + node _T_2393 = bits(io.csr_pkt.csr_mscratch, 0, 0) @[dec_tlu_ctl.scala 2511:41] + node _T_2394 = bits(mscratch, 31, 0) @[dec_tlu_ctl.scala 2511:66] + node _T_2395 = bits(io.csr_pkt.csr_mepc, 0, 0) @[dec_tlu_ctl.scala 2512:37] + node _T_2396 = cat(io.mepc, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2397 = bits(io.csr_pkt.csr_mcause, 0, 0) @[dec_tlu_ctl.scala 2513:39] + node _T_2398 = bits(mcause, 31, 0) @[dec_tlu_ctl.scala 2513:64] + node _T_2399 = bits(io.csr_pkt.csr_mscause, 0, 0) @[dec_tlu_ctl.scala 2514:40] + node _T_2400 = bits(mscause, 3, 0) @[dec_tlu_ctl.scala 2514:80] + node _T_2401 = cat(UInt<28>("h00"), _T_2400) @[Cat.scala 29:58] + node _T_2402 = bits(io.csr_pkt.csr_mtval, 0, 0) @[dec_tlu_ctl.scala 2515:38] + node _T_2403 = bits(mtval, 31, 0) @[dec_tlu_ctl.scala 2515:63] + node _T_2404 = bits(io.csr_pkt.csr_mrac, 0, 0) @[dec_tlu_ctl.scala 2516:37] + node _T_2405 = bits(mrac, 31, 0) @[dec_tlu_ctl.scala 2516:62] + node _T_2406 = bits(io.csr_pkt.csr_mdseac, 0, 0) @[dec_tlu_ctl.scala 2517:39] + node _T_2407 = bits(mdseac, 31, 0) @[dec_tlu_ctl.scala 2517:64] + node _T_2408 = bits(io.csr_pkt.csr_meivt, 0, 0) @[dec_tlu_ctl.scala 2518:38] + node _T_2409 = cat(meivt, UInt<10>("h00")) @[Cat.scala 29:58] + node _T_2410 = bits(io.csr_pkt.csr_meihap, 0, 0) @[dec_tlu_ctl.scala 2519:39] + node _T_2411 = cat(meivt, meihap) @[Cat.scala 29:58] + node _T_2412 = cat(_T_2411, UInt<2>("h00")) @[Cat.scala 29:58] + node _T_2413 = bits(io.csr_pkt.csr_meicurpl, 0, 0) @[dec_tlu_ctl.scala 2520:41] + node _T_2414 = bits(meicurpl, 3, 0) @[dec_tlu_ctl.scala 2520:81] + node _T_2415 = cat(UInt<28>("h00"), _T_2414) @[Cat.scala 29:58] + node _T_2416 = bits(io.csr_pkt.csr_meicidpl, 0, 0) @[dec_tlu_ctl.scala 2521:41] + node _T_2417 = bits(meicidpl, 3, 0) @[dec_tlu_ctl.scala 2521:81] + node _T_2418 = cat(UInt<28>("h00"), _T_2417) @[Cat.scala 29:58] + node _T_2419 = bits(io.csr_pkt.csr_meipt, 0, 0) @[dec_tlu_ctl.scala 2522:38] + node _T_2420 = bits(meipt, 3, 0) @[dec_tlu_ctl.scala 2522:78] + node _T_2421 = cat(UInt<28>("h00"), _T_2420) @[Cat.scala 29:58] + node _T_2422 = bits(io.csr_pkt.csr_mcgc, 0, 0) @[dec_tlu_ctl.scala 2523:37] + node _T_2423 = bits(mcgc, 8, 0) @[dec_tlu_ctl.scala 2523:77] + node _T_2424 = cat(UInt<23>("h00"), _T_2423) @[Cat.scala 29:58] + node _T_2425 = bits(io.csr_pkt.csr_mfdc, 0, 0) @[dec_tlu_ctl.scala 2524:37] + node _T_2426 = bits(mfdc, 18, 0) @[dec_tlu_ctl.scala 2524:77] + node _T_2427 = cat(UInt<13>("h00"), _T_2426) @[Cat.scala 29:58] + node _T_2428 = bits(io.csr_pkt.csr_dcsr, 0, 0) @[dec_tlu_ctl.scala 2525:37] + node _T_2429 = bits(io.dcsr, 15, 2) @[dec_tlu_ctl.scala 2525:85] + node _T_2430 = cat(UInt<16>("h04000"), _T_2429) @[Cat.scala 29:58] + node _T_2431 = cat(_T_2430, UInt<2>("h03")) @[Cat.scala 29:58] + node _T_2432 = bits(io.csr_pkt.csr_dpc, 0, 0) @[dec_tlu_ctl.scala 2526:36] + node _T_2433 = cat(io.dpc, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2434 = bits(io.csr_pkt.csr_dicad0, 0, 0) @[dec_tlu_ctl.scala 2527:39] + node _T_2435 = bits(dicad0, 31, 0) @[dec_tlu_ctl.scala 2527:64] + node _T_2436 = bits(io.csr_pkt.csr_dicad0h, 0, 0) @[dec_tlu_ctl.scala 2528:40] + node _T_2437 = bits(dicad0h, 31, 0) @[dec_tlu_ctl.scala 2528:65] + node _T_2438 = bits(io.csr_pkt.csr_dicad1, 0, 0) @[dec_tlu_ctl.scala 2529:39] + node _T_2439 = bits(dicad1, 31, 0) @[dec_tlu_ctl.scala 2529:64] + node _T_2440 = bits(io.csr_pkt.csr_dicawics, 0, 0) @[dec_tlu_ctl.scala 2530:41] + node _T_2441 = bits(dicawics, 16, 16) @[dec_tlu_ctl.scala 2530:80] + node _T_2442 = bits(dicawics, 15, 14) @[dec_tlu_ctl.scala 2530:104] + node _T_2443 = bits(dicawics, 13, 0) @[dec_tlu_ctl.scala 2530:131] + node _T_2444 = cat(UInt<3>("h00"), _T_2443) @[Cat.scala 29:58] + node _T_2445 = cat(_T_2444, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_2446 = cat(UInt<2>("h00"), _T_2442) @[Cat.scala 29:58] + node _T_2447 = cat(UInt<7>("h00"), _T_2441) @[Cat.scala 29:58] + node _T_2448 = cat(_T_2447, _T_2446) @[Cat.scala 29:58] + node _T_2449 = cat(_T_2448, _T_2445) @[Cat.scala 29:58] + node _T_2450 = bits(io.csr_pkt.csr_mtsel, 0, 0) @[dec_tlu_ctl.scala 2531:38] + node _T_2451 = bits(mtsel, 1, 0) @[dec_tlu_ctl.scala 2531:78] + node _T_2452 = cat(UInt<30>("h00"), _T_2451) @[Cat.scala 29:58] + node _T_2453 = bits(io.csr_pkt.csr_mtdata1, 0, 0) @[dec_tlu_ctl.scala 2532:40] + node _T_2454 = bits(mtdata1_tsel_out, 31, 0) @[dec_tlu_ctl.scala 2532:74] + node _T_2455 = bits(io.csr_pkt.csr_mtdata2, 0, 0) @[dec_tlu_ctl.scala 2533:40] + node _T_2456 = bits(mtdata2_tsel_out, 31, 0) @[dec_tlu_ctl.scala 2533:74] + node _T_2457 = bits(io.csr_pkt.csr_micect, 0, 0) @[dec_tlu_ctl.scala 2534:39] + node _T_2458 = bits(micect, 31, 0) @[dec_tlu_ctl.scala 2534:64] + node _T_2459 = bits(io.csr_pkt.csr_miccmect, 0, 0) @[dec_tlu_ctl.scala 2535:41] + node _T_2460 = bits(miccmect, 31, 0) @[dec_tlu_ctl.scala 2535:66] + node _T_2461 = bits(io.csr_pkt.csr_mdccmect, 0, 0) @[dec_tlu_ctl.scala 2536:41] + node _T_2462 = bits(mdccmect, 31, 0) @[dec_tlu_ctl.scala 2536:66] + node _T_2463 = bits(io.csr_pkt.csr_mhpmc3, 0, 0) @[dec_tlu_ctl.scala 2537:39] + node _T_2464 = bits(mhpmc3, 31, 0) @[dec_tlu_ctl.scala 2537:64] + node _T_2465 = bits(io.csr_pkt.csr_mhpmc4, 0, 0) @[dec_tlu_ctl.scala 2538:39] + node _T_2466 = bits(mhpmc4, 31, 0) @[dec_tlu_ctl.scala 2538:64] + node _T_2467 = bits(io.csr_pkt.csr_mhpmc5, 0, 0) @[dec_tlu_ctl.scala 2539:39] + node _T_2468 = bits(mhpmc5, 31, 0) @[dec_tlu_ctl.scala 2539:64] + node _T_2469 = bits(io.csr_pkt.csr_mhpmc6, 0, 0) @[dec_tlu_ctl.scala 2540:39] + node _T_2470 = bits(mhpmc6, 31, 0) @[dec_tlu_ctl.scala 2540:64] + node _T_2471 = bits(io.csr_pkt.csr_mhpmc3h, 0, 0) @[dec_tlu_ctl.scala 2541:40] + node _T_2472 = bits(mhpmc3h, 31, 0) @[dec_tlu_ctl.scala 2541:65] + node _T_2473 = bits(io.csr_pkt.csr_mhpmc4h, 0, 0) @[dec_tlu_ctl.scala 2542:40] + node _T_2474 = bits(mhpmc4h, 31, 0) @[dec_tlu_ctl.scala 2542:65] + node _T_2475 = bits(io.csr_pkt.csr_mhpmc5h, 0, 0) @[dec_tlu_ctl.scala 2543:40] + node _T_2476 = bits(mhpmc5h, 31, 0) @[dec_tlu_ctl.scala 2543:65] + node _T_2477 = bits(io.csr_pkt.csr_mhpmc6h, 0, 0) @[dec_tlu_ctl.scala 2544:40] + node _T_2478 = bits(mhpmc6h, 31, 0) @[dec_tlu_ctl.scala 2544:65] + node _T_2479 = bits(io.csr_pkt.csr_mfdht, 0, 0) @[dec_tlu_ctl.scala 2545:38] + node _T_2480 = bits(mfdht, 5, 0) @[dec_tlu_ctl.scala 2545:78] + node _T_2481 = cat(UInt<26>("h00"), _T_2480) @[Cat.scala 29:58] + node _T_2482 = bits(io.csr_pkt.csr_mfdhs, 0, 0) @[dec_tlu_ctl.scala 2546:38] + node _T_2483 = bits(mfdhs, 1, 0) @[dec_tlu_ctl.scala 2546:78] + node _T_2484 = cat(UInt<30>("h00"), _T_2483) @[Cat.scala 29:58] + node _T_2485 = bits(io.csr_pkt.csr_mhpme3, 0, 0) @[dec_tlu_ctl.scala 2547:39] + node _T_2486 = bits(mhpme3, 9, 0) @[dec_tlu_ctl.scala 2547:79] + node _T_2487 = cat(UInt<22>("h00"), _T_2486) @[Cat.scala 29:58] + node _T_2488 = bits(io.csr_pkt.csr_mhpme4, 0, 0) @[dec_tlu_ctl.scala 2548:39] + node _T_2489 = bits(mhpme4, 9, 0) @[dec_tlu_ctl.scala 2548:79] + node _T_2490 = cat(UInt<22>("h00"), _T_2489) @[Cat.scala 29:58] + node _T_2491 = bits(io.csr_pkt.csr_mhpme5, 0, 0) @[dec_tlu_ctl.scala 2549:39] + node _T_2492 = bits(mhpme5, 9, 0) @[dec_tlu_ctl.scala 2549:78] + node _T_2493 = cat(UInt<22>("h00"), _T_2492) @[Cat.scala 29:58] + node _T_2494 = bits(io.csr_pkt.csr_mhpme6, 0, 0) @[dec_tlu_ctl.scala 2550:39] + node _T_2495 = bits(mhpme6, 9, 0) @[dec_tlu_ctl.scala 2550:78] + node _T_2496 = cat(UInt<22>("h00"), _T_2495) @[Cat.scala 29:58] + node _T_2497 = bits(io.csr_pkt.csr_mcountinhibit, 0, 0) @[dec_tlu_ctl.scala 2551:46] + node _T_2498 = bits(mcountinhibit, 6, 0) @[dec_tlu_ctl.scala 2551:86] + node _T_2499 = cat(UInt<25>("h00"), _T_2498) @[Cat.scala 29:58] + node _T_2500 = bits(io.csr_pkt.csr_mpmc, 0, 0) @[dec_tlu_ctl.scala 2552:37] + node _T_2501 = cat(UInt<30>("h00"), mpmc) @[Cat.scala 29:58] + node _T_2502 = cat(_T_2501, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_2503 = bits(io.dec_timer_read_d, 0, 0) @[dec_tlu_ctl.scala 2553:37] + node _T_2504 = bits(io.dec_timer_rddata_d, 31, 0) @[dec_tlu_ctl.scala 2553:76] + node _T_2505 = mux(_T_2339, UInt<32>("h040001104"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2506 = mux(_T_2340, UInt<32>("h045"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2507 = mux(_T_2341, UInt<32>("h010"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2508 = mux(_T_2342, UInt<32>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2509 = mux(_T_2343, _T_2344, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2510 = mux(_T_2345, _T_2353, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2511 = mux(_T_2354, _T_2358, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2512 = mux(_T_2359, _T_2371, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2513 = mux(_T_2372, _T_2384, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2514 = mux(_T_2385, _T_2386, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2515 = mux(_T_2387, _T_2388, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2516 = mux(_T_2389, _T_2390, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2517 = mux(_T_2391, _T_2392, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2518 = mux(_T_2393, _T_2394, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2519 = mux(_T_2395, _T_2396, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2520 = mux(_T_2397, _T_2398, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2521 = mux(_T_2399, _T_2401, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2522 = mux(_T_2402, _T_2403, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2523 = mux(_T_2404, _T_2405, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2524 = mux(_T_2406, _T_2407, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2525 = mux(_T_2408, _T_2409, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2526 = mux(_T_2410, _T_2412, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2527 = mux(_T_2413, _T_2415, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2528 = mux(_T_2416, _T_2418, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2529 = mux(_T_2419, _T_2421, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2530 = mux(_T_2422, _T_2424, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2531 = mux(_T_2425, _T_2427, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2532 = mux(_T_2428, _T_2431, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2533 = mux(_T_2432, _T_2433, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2534 = mux(_T_2434, _T_2435, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2535 = mux(_T_2436, _T_2437, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2536 = mux(_T_2438, _T_2439, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2537 = mux(_T_2440, _T_2449, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2538 = mux(_T_2450, _T_2452, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2539 = mux(_T_2453, _T_2454, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2540 = mux(_T_2455, _T_2456, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2541 = mux(_T_2457, _T_2458, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2542 = mux(_T_2459, _T_2460, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2543 = mux(_T_2461, _T_2462, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2544 = mux(_T_2463, _T_2464, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2545 = mux(_T_2465, _T_2466, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2546 = mux(_T_2467, _T_2468, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2547 = mux(_T_2469, _T_2470, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2548 = mux(_T_2471, _T_2472, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2549 = mux(_T_2473, _T_2474, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2550 = mux(_T_2475, _T_2476, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2551 = mux(_T_2477, _T_2478, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2552 = mux(_T_2479, _T_2481, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2553 = mux(_T_2482, _T_2484, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2554 = mux(_T_2485, _T_2487, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2555 = mux(_T_2488, _T_2490, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2556 = mux(_T_2491, _T_2493, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2557 = mux(_T_2494, _T_2496, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2558 = mux(_T_2497, _T_2499, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2559 = mux(_T_2500, _T_2502, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2560 = mux(_T_2503, _T_2504, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2561 = or(_T_2505, _T_2506) @[Mux.scala 27:72] node _T_2562 = or(_T_2561, _T_2507) @[Mux.scala 27:72] node _T_2563 = or(_T_2562, _T_2508) @[Mux.scala 27:72] node _T_2564 = or(_T_2563, _T_2509) @[Mux.scala 27:72] @@ -76170,9 +76178,10 @@ circuit quasar_wrapper : node _T_2612 = or(_T_2611, _T_2557) @[Mux.scala 27:72] node _T_2613 = or(_T_2612, _T_2558) @[Mux.scala 27:72] node _T_2614 = or(_T_2613, _T_2559) @[Mux.scala 27:72] - wire _T_2615 : UInt @[Mux.scala 27:72] - _T_2615 <= _T_2614 @[Mux.scala 27:72] - io.dec_csr_rddata_d <= _T_2615 @[dec_tlu_ctl.scala 2497:21] + node _T_2615 = or(_T_2614, _T_2560) @[Mux.scala 27:72] + wire _T_2616 : UInt @[Mux.scala 27:72] + _T_2616 <= _T_2615 @[Mux.scala 27:72] + io.dec_csr_rddata_d <= _T_2616 @[dec_tlu_ctl.scala 2497:21] module dec_decode_csr_read : input clock : Clock @@ -77858,9 +77867,9 @@ circuit quasar_wrapper : module dec_tlu_ctl : input clock : Clock input reset : AsyncReset - output io : {flip tlu_exu : {flip dec_tlu_meihap : UInt<30>, flip dec_tlu_flush_lower_r : UInt<1>, flip dec_tlu_flush_path_r : UInt<31>, exu_i0_br_hist_r : UInt<2>, exu_i0_br_error_r : UInt<1>, exu_i0_br_start_error_r : UInt<1>, exu_i0_br_index_r : UInt<8>, exu_i0_br_valid_r : UInt<1>, exu_i0_br_mp_r : UInt<1>, exu_i0_br_middle_r : UInt<1>, exu_pmu_i0_br_misp : UInt<1>, exu_pmu_i0_br_ataken : UInt<1>, exu_pmu_i0_pc4 : UInt<1>, exu_npc_r : UInt<31>}, tlu_dma : {flip dma_pmu_dccm_read : UInt<1>, flip dma_pmu_dccm_write : UInt<1>, flip dma_pmu_any_read : UInt<1>, flip dma_pmu_any_write : UInt<1>, dec_tlu_dma_qos_prty : UInt<3>, flip dma_dccm_stall_any : UInt<1>, flip dma_iccm_stall_any : UInt<1>}, flip active_clk : Clock, flip free_clk : Clock, flip scan_mode : UInt<1>, flip rst_vec : UInt<31>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, flip lsu_fastint_stall_any : UInt<1>, flip lsu_idle_any : UInt<1>, flip dec_pmu_instr_decoded : UInt<1>, flip dec_pmu_decode_stall : UInt<1>, flip dec_pmu_presync_stall : UInt<1>, flip dec_pmu_postsync_stall : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip lsu_fir_addr : UInt<31>, flip lsu_fir_error : UInt<2>, flip iccm_dma_sb_error : UInt<1>, flip lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, flip lsu_single_ecc_error_incr : UInt<1>, flip dec_pause_state : UInt<1>, flip dec_csr_wen_unq_d : UInt<1>, flip dec_csr_any_unq_d : UInt<1>, flip dec_csr_rdaddr_d : UInt<12>, flip dec_csr_wen_r : UInt<1>, flip dec_csr_wraddr_r : UInt<12>, flip dec_csr_wrdata_r : UInt<32>, flip dec_csr_stall_int_ff : UInt<1>, flip dec_tlu_i0_valid_r : UInt<1>, flip dec_tlu_i0_pc_r : UInt<31>, flip dec_tlu_packet_r : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, flip dec_illegal_inst : UInt<32>, flip dec_i0_decode_d : UInt<1>, flip exu_i0_br_way_r : UInt<1>, dec_dbg_cmd_done : UInt<1>, dec_dbg_cmd_fail : UInt<1>, dec_tlu_dbg_halted : UInt<1>, dec_tlu_debug_mode : UInt<1>, dec_tlu_resume_ack : UInt<1>, dec_tlu_debug_stall : UInt<1>, dec_tlu_mpc_halted_only : UInt<1>, dec_tlu_flush_extint : UInt<1>, flip dbg_halt_req : UInt<1>, flip dbg_resume_req : UInt<1>, flip dec_div_active : UInt<1>, trigger_pkt_any : {select : UInt<1>, match_pkt : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip timer_int : UInt<1>, flip soft_int : UInt<1>, o_cpu_halt_status : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_run_ack : UInt<1>, o_debug_mode_status : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, dec_csr_rddata_d : UInt<32>, dec_csr_legal_d : UInt<1>, dec_tlu_i0_kill_writeb_wb : UInt<1>, dec_tlu_i0_kill_writeb_r : UInt<1>, dec_tlu_wr_pause_r : UInt<1>, dec_tlu_flush_pause_r : UInt<1>, dec_tlu_presync_d : UInt<1>, dec_tlu_postsync_d : UInt<1>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, dec_tlu_i0_exc_valid_wb1 : UInt<1>, dec_tlu_i0_valid_wb1 : UInt<1>, dec_tlu_int_valid_wb1 : UInt<1>, dec_tlu_exc_cause_wb1 : UInt<5>, dec_tlu_mtval_wb1 : UInt<32>, dec_tlu_pipelining_disable : UInt<1>, dec_tlu_misc_clk_override : UInt<1>, dec_tlu_dec_clk_override : UInt<1>, dec_tlu_ifu_clk_override : UInt<1>, dec_tlu_lsu_clk_override : UInt<1>, dec_tlu_bus_clk_override : UInt<1>, dec_tlu_pic_clk_override : UInt<1>, dec_tlu_dccm_clk_override : UInt<1>, dec_tlu_icm_clk_override : UInt<1>, flip ifu_pmu_instr_aligned : UInt<1>, flip tlu_bp : {flip dec_tlu_br0_r_pkt : {valid : UInt<1>, bits : {hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}}, flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_flush_leak_one_wb : UInt<1>, flip dec_tlu_bpred_disable : UInt<1>}, flip tlu_ifc : {flip dec_tlu_flush_noredir_wb : UInt<1>, flip dec_tlu_mrac_ff : UInt<32>, ifu_pmu_fetch_stall : UInt<1>}, flip tlu_mem : {flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_flush_err_wb : UInt<1>, flip dec_tlu_i0_commit_cmt : UInt<1>, flip dec_tlu_force_halt : UInt<1>, flip dec_tlu_fence_i_wb : UInt<1>, flip dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, flip dec_tlu_core_ecc_disable : UInt<1>, ifu_pmu_ic_miss : UInt<1>, ifu_pmu_ic_hit : UInt<1>, ifu_pmu_bus_error : UInt<1>, ifu_pmu_bus_busy : UInt<1>, ifu_pmu_bus_trxn : UInt<1>, ifu_ic_error_start : UInt<1>, ifu_iccm_rd_ecc_single_err : UInt<1>, ifu_ic_debug_rd_data : UInt<71>, ifu_ic_debug_rd_data_valid : UInt<1>, ifu_miss_state_idle : UInt<1>}, flip tlu_busbuff : {lsu_pmu_bus_trxn : UInt<1>, lsu_pmu_bus_misaligned : UInt<1>, lsu_pmu_bus_error : UInt<1>, lsu_pmu_bus_busy : UInt<1>, flip dec_tlu_external_ldfwd_disable : UInt<1>, flip dec_tlu_wb_coalescing_disable : UInt<1>, flip dec_tlu_sideeffect_posted_disable : UInt<1>, lsu_imprecise_error_load_any : UInt<1>, lsu_imprecise_error_store_any : UInt<1>, lsu_imprecise_error_addr_any : UInt<32>}, flip lsu_tlu : {lsu_pmu_load_external_m : UInt<1>, lsu_pmu_store_external_m : UInt<1>}, dec_pic : {flip pic_claimid : UInt<8>, flip pic_pl : UInt<4>, flip mhwakeup : UInt<1>, dec_tlu_meicurpl : UInt<4>, dec_tlu_meipt : UInt<4>, flip mexintpend : UInt<1>}} + output io : {flip tlu_exu : {flip dec_tlu_meihap : UInt<30>, flip dec_tlu_flush_lower_r : UInt<1>, flip dec_tlu_flush_path_r : UInt<31>, exu_i0_br_hist_r : UInt<2>, exu_i0_br_error_r : UInt<1>, exu_i0_br_start_error_r : UInt<1>, exu_i0_br_index_r : UInt<8>, exu_i0_br_valid_r : UInt<1>, exu_i0_br_mp_r : UInt<1>, exu_i0_br_middle_r : UInt<1>, exu_pmu_i0_br_misp : UInt<1>, exu_pmu_i0_br_ataken : UInt<1>, exu_pmu_i0_pc4 : UInt<1>, exu_npc_r : UInt<31>}, tlu_dma : {flip dma_pmu_dccm_read : UInt<1>, flip dma_pmu_dccm_write : UInt<1>, flip dma_pmu_any_read : UInt<1>, flip dma_pmu_any_write : UInt<1>, dec_tlu_dma_qos_prty : UInt<3>, flip dma_dccm_stall_any : UInt<1>, flip dma_iccm_stall_any : UInt<1>}, flip active_clk : Clock, flip free_clk : Clock, flip scan_mode : UInt<1>, flip rst_vec : UInt<31>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, flip lsu_fastint_stall_any : UInt<1>, flip lsu_idle_any : UInt<1>, flip dec_pmu_instr_decoded : UInt<1>, flip dec_pmu_decode_stall : UInt<1>, flip dec_pmu_presync_stall : UInt<1>, flip dec_pmu_postsync_stall : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip lsu_fir_addr : UInt<31>, flip lsu_fir_error : UInt<2>, flip iccm_dma_sb_error : UInt<1>, flip lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, flip lsu_single_ecc_error_incr : UInt<1>, flip dec_pause_state : UInt<1>, flip dec_csr_wen_unq_d : UInt<1>, flip dec_csr_any_unq_d : UInt<1>, flip dec_csr_rdaddr_d : UInt<12>, flip dec_csr_wen_r : UInt<1>, flip dec_csr_wraddr_r : UInt<12>, flip dec_csr_wrdata_r : UInt<32>, flip dec_csr_stall_int_ff : UInt<1>, flip dec_tlu_i0_valid_r : UInt<1>, flip dec_tlu_i0_pc_r : UInt<31>, flip dec_tlu_packet_r : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, flip dec_illegal_inst : UInt<32>, flip dec_i0_decode_d : UInt<1>, flip exu_i0_br_way_r : UInt<1>, dec_dbg_cmd_done : UInt<1>, dec_dbg_cmd_fail : UInt<1>, dec_tlu_dbg_halted : UInt<1>, dec_tlu_debug_mode : UInt<1>, dec_tlu_resume_ack : UInt<1>, dec_tlu_debug_stall : UInt<1>, dec_tlu_mpc_halted_only : UInt<1>, dec_tlu_flush_extint : UInt<1>, flip dbg_halt_req : UInt<1>, flip dbg_resume_req : UInt<1>, flip dec_div_active : UInt<1>, trigger_pkt_any : {select : UInt<1>, match_pkt : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip timer_int : UInt<1>, flip soft_int : UInt<1>, o_cpu_halt_status : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_run_ack : UInt<1>, o_debug_mode_status : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, dec_csr_rddata_d : UInt<32>, dec_csr_legal_d : UInt<1>, dec_tlu_i0_kill_writeb_wb : UInt<1>, dec_tlu_i0_kill_writeb_r : UInt<1>, dec_tlu_wr_pause_r : UInt<1>, dec_tlu_flush_pause_r : UInt<1>, dec_tlu_presync_d : UInt<1>, dec_tlu_postsync_d : UInt<1>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, dec_tlu_i0_exc_valid_wb1 : UInt<1>, dec_tlu_i0_valid_wb1 : UInt<1>, dec_tlu_int_valid_wb1 : UInt<1>, dec_tlu_exc_cause_wb1 : UInt<5>, dec_tlu_mtval_wb1 : UInt<32>, dec_tlu_pipelining_disable : UInt<1>, dec_tlu_misc_clk_override : UInt<1>, dec_tlu_dec_clk_override : UInt<1>, dec_tlu_ifu_clk_override : UInt<1>, dec_tlu_lsu_clk_override : UInt<1>, dec_tlu_bus_clk_override : UInt<1>, dec_tlu_pic_clk_override : UInt<1>, dec_tlu_dccm_clk_override : UInt<1>, dec_tlu_icm_clk_override : UInt<1>, dec_tlu_flush_lower_wb : UInt<1>, flip ifu_pmu_instr_aligned : UInt<1>, flip tlu_bp : {flip dec_tlu_br0_r_pkt : {valid : UInt<1>, bits : {hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}}, flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_flush_leak_one_wb : UInt<1>, flip dec_tlu_bpred_disable : UInt<1>}, flip tlu_ifc : {flip dec_tlu_flush_noredir_wb : UInt<1>, flip dec_tlu_mrac_ff : UInt<32>, ifu_pmu_fetch_stall : UInt<1>}, flip tlu_mem : {flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_flush_err_wb : UInt<1>, flip dec_tlu_i0_commit_cmt : UInt<1>, flip dec_tlu_force_halt : UInt<1>, flip dec_tlu_fence_i_wb : UInt<1>, flip dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, flip dec_tlu_core_ecc_disable : UInt<1>, ifu_pmu_ic_miss : UInt<1>, ifu_pmu_ic_hit : UInt<1>, ifu_pmu_bus_error : UInt<1>, ifu_pmu_bus_busy : UInt<1>, ifu_pmu_bus_trxn : UInt<1>, ifu_ic_error_start : UInt<1>, ifu_iccm_rd_ecc_single_err : UInt<1>, ifu_ic_debug_rd_data : UInt<71>, ifu_ic_debug_rd_data_valid : UInt<1>, ifu_miss_state_idle : UInt<1>}, flip tlu_busbuff : {lsu_pmu_bus_trxn : UInt<1>, lsu_pmu_bus_misaligned : UInt<1>, lsu_pmu_bus_error : UInt<1>, lsu_pmu_bus_busy : UInt<1>, flip dec_tlu_external_ldfwd_disable : UInt<1>, flip dec_tlu_wb_coalescing_disable : UInt<1>, flip dec_tlu_sideeffect_posted_disable : UInt<1>, lsu_imprecise_error_load_any : UInt<1>, lsu_imprecise_error_store_any : UInt<1>, lsu_imprecise_error_addr_any : UInt<32>}, flip lsu_tlu : {lsu_pmu_load_external_m : UInt<1>, lsu_pmu_store_external_m : UInt<1>}, dec_pic : {flip pic_claimid : UInt<8>, flip pic_pl : UInt<4>, flip mhwakeup : UInt<1>, dec_tlu_meicurpl : UInt<4>, dec_tlu_meipt : UInt<4>, flip mexintpend : UInt<1>}} - wire mtdata1_t : UInt<10>[4] @[dec_tlu_ctl.scala 155:67] + wire mtdata1_t : UInt<10>[4] @[dec_tlu_ctl.scala 156:67] wire pause_expired_wb : UInt<1> pause_expired_wb <= UInt<1>("h00") wire take_nmi_r_d1 : UInt<1> @@ -78087,30 +78096,30 @@ circuit quasar_wrapper : mtvec <= UInt<1>("h00") wire mip : UInt<6> mip <= UInt<1>("h00") - wire csr_pkt : {csr_misa : UInt<1>, csr_mvendorid : UInt<1>, csr_marchid : UInt<1>, csr_mimpid : UInt<1>, csr_mhartid : UInt<1>, csr_mstatus : UInt<1>, csr_mtvec : UInt<1>, csr_mip : UInt<1>, csr_mie : UInt<1>, csr_mcyclel : UInt<1>, csr_mcycleh : UInt<1>, csr_minstretl : UInt<1>, csr_minstreth : UInt<1>, csr_mscratch : UInt<1>, csr_mepc : UInt<1>, csr_mcause : UInt<1>, csr_mscause : UInt<1>, csr_mtval : UInt<1>, csr_mrac : UInt<1>, csr_dmst : UInt<1>, csr_mdseac : UInt<1>, csr_meihap : UInt<1>, csr_meivt : UInt<1>, csr_meipt : UInt<1>, csr_meicurpl : UInt<1>, csr_meicidpl : UInt<1>, csr_dcsr : UInt<1>, csr_mcgc : UInt<1>, csr_mfdc : UInt<1>, csr_dpc : UInt<1>, csr_mtsel : UInt<1>, csr_mtdata1 : UInt<1>, csr_mtdata2 : UInt<1>, csr_mhpmc3 : UInt<1>, csr_mhpmc4 : UInt<1>, csr_mhpmc5 : UInt<1>, csr_mhpmc6 : UInt<1>, csr_mhpmc3h : UInt<1>, csr_mhpmc4h : UInt<1>, csr_mhpmc5h : UInt<1>, csr_mhpmc6h : UInt<1>, csr_mhpme3 : UInt<1>, csr_mhpme4 : UInt<1>, csr_mhpme5 : UInt<1>, csr_mhpme6 : UInt<1>, csr_mcountinhibit : UInt<1>, csr_mitctl0 : UInt<1>, csr_mitctl1 : UInt<1>, csr_mitb0 : UInt<1>, csr_mitb1 : UInt<1>, csr_mitcnt0 : UInt<1>, csr_mitcnt1 : UInt<1>, csr_mpmc : UInt<1>, csr_mcpc : UInt<1>, csr_meicpct : UInt<1>, csr_mdeau : UInt<1>, csr_micect : UInt<1>, csr_miccmect : UInt<1>, csr_mdccmect : UInt<1>, csr_mfdht : UInt<1>, csr_mfdhs : UInt<1>, csr_dicawics : UInt<1>, csr_dicad0h : UInt<1>, csr_dicad0 : UInt<1>, csr_dicad1 : UInt<1>, csr_dicago : UInt<1>, presync : UInt<1>, postsync : UInt<1>, legal : UInt<1>} @[dec_tlu_ctl.scala 270:41] + wire csr_pkt : {csr_misa : UInt<1>, csr_mvendorid : UInt<1>, csr_marchid : UInt<1>, csr_mimpid : UInt<1>, csr_mhartid : UInt<1>, csr_mstatus : UInt<1>, csr_mtvec : UInt<1>, csr_mip : UInt<1>, csr_mie : UInt<1>, csr_mcyclel : UInt<1>, csr_mcycleh : UInt<1>, csr_minstretl : UInt<1>, csr_minstreth : UInt<1>, csr_mscratch : UInt<1>, csr_mepc : UInt<1>, csr_mcause : UInt<1>, csr_mscause : UInt<1>, csr_mtval : UInt<1>, csr_mrac : UInt<1>, csr_dmst : UInt<1>, csr_mdseac : UInt<1>, csr_meihap : UInt<1>, csr_meivt : UInt<1>, csr_meipt : UInt<1>, csr_meicurpl : UInt<1>, csr_meicidpl : UInt<1>, csr_dcsr : UInt<1>, csr_mcgc : UInt<1>, csr_mfdc : UInt<1>, csr_dpc : UInt<1>, csr_mtsel : UInt<1>, csr_mtdata1 : UInt<1>, csr_mtdata2 : UInt<1>, csr_mhpmc3 : UInt<1>, csr_mhpmc4 : UInt<1>, csr_mhpmc5 : UInt<1>, csr_mhpmc6 : UInt<1>, csr_mhpmc3h : UInt<1>, csr_mhpmc4h : UInt<1>, csr_mhpmc5h : UInt<1>, csr_mhpmc6h : UInt<1>, csr_mhpme3 : UInt<1>, csr_mhpme4 : UInt<1>, csr_mhpme5 : UInt<1>, csr_mhpme6 : UInt<1>, csr_mcountinhibit : UInt<1>, csr_mitctl0 : UInt<1>, csr_mitctl1 : UInt<1>, csr_mitb0 : UInt<1>, csr_mitb1 : UInt<1>, csr_mitcnt0 : UInt<1>, csr_mitcnt1 : UInt<1>, csr_mpmc : UInt<1>, csr_mcpc : UInt<1>, csr_meicpct : UInt<1>, csr_mdeau : UInt<1>, csr_micect : UInt<1>, csr_miccmect : UInt<1>, csr_mdccmect : UInt<1>, csr_mfdht : UInt<1>, csr_mfdhs : UInt<1>, csr_dicawics : UInt<1>, csr_dicad0h : UInt<1>, csr_dicad0 : UInt<1>, csr_dicad1 : UInt<1>, csr_dicago : UInt<1>, presync : UInt<1>, postsync : UInt<1>, legal : UInt<1>} @[dec_tlu_ctl.scala 271:41] wire dec_tlu_mpc_halted_only_ns : UInt<1> dec_tlu_mpc_halted_only_ns <= UInt<1>("h00") - node _T = not(dbg_halt_state_f) @[dec_tlu_ctl.scala 273:39] - node _T_1 = and(_T, mpc_halt_state_f) @[dec_tlu_ctl.scala 273:57] - dec_tlu_mpc_halted_only_ns <= _T_1 @[dec_tlu_ctl.scala 273:36] - inst int_timers of dec_timer_ctl @[dec_tlu_ctl.scala 274:30] + node _T = not(dbg_halt_state_f) @[dec_tlu_ctl.scala 274:39] + node _T_1 = and(_T, mpc_halt_state_f) @[dec_tlu_ctl.scala 274:57] + dec_tlu_mpc_halted_only_ns <= _T_1 @[dec_tlu_ctl.scala 274:36] + inst int_timers of dec_timer_ctl @[dec_tlu_ctl.scala 275:30] int_timers.clock <= clock int_timers.reset <= reset - int_timers.io.free_clk <= io.free_clk @[dec_tlu_ctl.scala 275:57] - int_timers.io.scan_mode <= io.scan_mode @[dec_tlu_ctl.scala 276:57] - int_timers.io.dec_csr_wen_r_mod <= dec_csr_wen_r_mod @[dec_tlu_ctl.scala 277:49] - int_timers.io.dec_csr_rdaddr_d <= io.dec_csr_rdaddr_d @[dec_tlu_ctl.scala 278:49] - int_timers.io.dec_csr_wraddr_r <= io.dec_csr_wraddr_r @[dec_tlu_ctl.scala 279:49] - int_timers.io.dec_csr_wrdata_r <= io.dec_csr_wrdata_r @[dec_tlu_ctl.scala 280:49] - int_timers.io.csr_mitctl0 <= csr_pkt.csr_mitctl0 @[dec_tlu_ctl.scala 281:57] - int_timers.io.csr_mitctl1 <= csr_pkt.csr_mitctl1 @[dec_tlu_ctl.scala 282:57] - int_timers.io.csr_mitb0 <= csr_pkt.csr_mitb0 @[dec_tlu_ctl.scala 283:57] - int_timers.io.csr_mitb1 <= csr_pkt.csr_mitb1 @[dec_tlu_ctl.scala 284:57] - int_timers.io.csr_mitcnt0 <= csr_pkt.csr_mitcnt0 @[dec_tlu_ctl.scala 285:57] - int_timers.io.csr_mitcnt1 <= csr_pkt.csr_mitcnt1 @[dec_tlu_ctl.scala 286:57] - int_timers.io.dec_pause_state <= io.dec_pause_state @[dec_tlu_ctl.scala 287:49] - int_timers.io.dec_tlu_pmu_fw_halted <= dec_tlu_pmu_fw_halted @[dec_tlu_ctl.scala 288:49] - int_timers.io.internal_dbg_halt_timers <= internal_dbg_halt_timers @[dec_tlu_ctl.scala 289:47] + int_timers.io.free_clk <= io.free_clk @[dec_tlu_ctl.scala 276:57] + int_timers.io.scan_mode <= io.scan_mode @[dec_tlu_ctl.scala 277:57] + int_timers.io.dec_csr_wen_r_mod <= dec_csr_wen_r_mod @[dec_tlu_ctl.scala 278:49] + int_timers.io.dec_csr_rdaddr_d <= io.dec_csr_rdaddr_d @[dec_tlu_ctl.scala 279:49] + int_timers.io.dec_csr_wraddr_r <= io.dec_csr_wraddr_r @[dec_tlu_ctl.scala 280:49] + int_timers.io.dec_csr_wrdata_r <= io.dec_csr_wrdata_r @[dec_tlu_ctl.scala 281:49] + int_timers.io.csr_mitctl0 <= csr_pkt.csr_mitctl0 @[dec_tlu_ctl.scala 282:57] + int_timers.io.csr_mitctl1 <= csr_pkt.csr_mitctl1 @[dec_tlu_ctl.scala 283:57] + int_timers.io.csr_mitb0 <= csr_pkt.csr_mitb0 @[dec_tlu_ctl.scala 284:57] + int_timers.io.csr_mitb1 <= csr_pkt.csr_mitb1 @[dec_tlu_ctl.scala 285:57] + int_timers.io.csr_mitcnt0 <= csr_pkt.csr_mitcnt0 @[dec_tlu_ctl.scala 286:57] + int_timers.io.csr_mitcnt1 <= csr_pkt.csr_mitcnt1 @[dec_tlu_ctl.scala 287:57] + int_timers.io.dec_pause_state <= io.dec_pause_state @[dec_tlu_ctl.scala 288:49] + int_timers.io.dec_tlu_pmu_fw_halted <= dec_tlu_pmu_fw_halted @[dec_tlu_ctl.scala 289:49] + int_timers.io.internal_dbg_halt_timers <= internal_dbg_halt_timers @[dec_tlu_ctl.scala 290:47] node _T_2 = cat(io.i_cpu_run_req, io.mpc_debug_halt_req) @[Cat.scala 29:58] node _T_3 = cat(_T_2, io.mpc_debug_run_req) @[Cat.scala 29:58] node _T_4 = cat(io.soft_int, io.i_cpu_halt_req) @[Cat.scala 29:58] @@ -78121,101 +78130,103 @@ circuit quasar_wrapper : _T_8 <= _T_7 @[lib.scala 37:81] reg syncro_ff : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 37:58] syncro_ff <= _T_8 @[lib.scala 37:58] - node nmi_int_sync = bits(syncro_ff, 6, 6) @[dec_tlu_ctl.scala 301:67] - node timer_int_sync = bits(syncro_ff, 5, 5) @[dec_tlu_ctl.scala 302:59] - node soft_int_sync = bits(syncro_ff, 4, 4) @[dec_tlu_ctl.scala 303:59] - node i_cpu_halt_req_sync = bits(syncro_ff, 3, 3) @[dec_tlu_ctl.scala 304:59] - node i_cpu_run_req_sync = bits(syncro_ff, 2, 2) @[dec_tlu_ctl.scala 305:59] - node mpc_debug_halt_req_sync_raw = bits(syncro_ff, 1, 1) @[dec_tlu_ctl.scala 306:51] - node mpc_debug_run_req_sync = bits(syncro_ff, 0, 0) @[dec_tlu_ctl.scala 307:51] - node _T_9 = or(dec_csr_wen_r_mod, io.dec_tlu_dec_clk_override) @[dec_tlu_ctl.scala 310:58] - node _T_10 = bits(_T_9, 0, 0) @[dec_tlu_ctl.scala 310:74] + node nmi_int_sync = bits(syncro_ff, 6, 6) @[dec_tlu_ctl.scala 302:67] + node timer_int_sync = bits(syncro_ff, 5, 5) @[dec_tlu_ctl.scala 303:59] + node soft_int_sync = bits(syncro_ff, 4, 4) @[dec_tlu_ctl.scala 304:59] + node i_cpu_halt_req_sync = bits(syncro_ff, 3, 3) @[dec_tlu_ctl.scala 305:59] + node i_cpu_run_req_sync = bits(syncro_ff, 2, 2) @[dec_tlu_ctl.scala 306:59] + node mpc_debug_halt_req_sync_raw = bits(syncro_ff, 1, 1) @[dec_tlu_ctl.scala 307:51] + node mpc_debug_run_req_sync = bits(syncro_ff, 0, 0) @[dec_tlu_ctl.scala 308:51] + node _T_9 = or(dec_csr_wen_r_mod, io.dec_tlu_dec_clk_override) @[dec_tlu_ctl.scala 311:58] + node _T_10 = bits(_T_9, 0, 0) @[dec_tlu_ctl.scala 311:74] inst rvclkhdr of rvclkhdr_716 @[lib.scala 343:22] rvclkhdr.clock <= clock rvclkhdr.reset <= reset rvclkhdr.io.clk <= clock @[lib.scala 344:17] rvclkhdr.io.en <= _T_10 @[lib.scala 345:16] rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - node _T_11 = or(io.lsu_error_pkt_r.valid, lsu_exc_valid_r_d1) @[dec_tlu_ctl.scala 311:67] - node _T_12 = or(_T_11, io.dec_tlu_dec_clk_override) @[dec_tlu_ctl.scala 311:88] - node _T_13 = bits(_T_12, 0, 0) @[dec_tlu_ctl.scala 311:104] + node _T_11 = or(io.lsu_error_pkt_r.valid, lsu_exc_valid_r_d1) @[dec_tlu_ctl.scala 312:67] + node _T_12 = or(_T_11, io.dec_tlu_dec_clk_override) @[dec_tlu_ctl.scala 312:88] + node _T_13 = bits(_T_12, 0, 0) @[dec_tlu_ctl.scala 312:104] inst rvclkhdr_1 of rvclkhdr_717 @[lib.scala 343:22] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset rvclkhdr_1.io.clk <= clock @[lib.scala 344:17] rvclkhdr_1.io.en <= _T_13 @[lib.scala 345:16] rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - node e4e5_valid = or(io.dec_tlu_i0_valid_r, e5_valid) @[dec_tlu_ctl.scala 314:30] - node _T_14 = or(debug_mode_status, i_cpu_run_req_d1) @[dec_tlu_ctl.scala 315:50] - node _T_15 = or(_T_14, interrupt_valid_r) @[dec_tlu_ctl.scala 315:69] - node _T_16 = or(_T_15, interrupt_valid_r_d1) @[dec_tlu_ctl.scala 315:89] - node _T_17 = or(_T_16, reset_delayed) @[dec_tlu_ctl.scala 315:112] - node _T_18 = or(_T_17, pause_expired_r) @[dec_tlu_ctl.scala 315:128] - node _T_19 = or(_T_18, pause_expired_wb) @[dec_tlu_ctl.scala 315:146] - node _T_20 = or(_T_19, ic_perr_r) @[dec_tlu_ctl.scala 315:165] - node _T_21 = or(_T_20, ic_perr_r_d1) @[dec_tlu_ctl.scala 315:177] - node _T_22 = or(_T_21, iccm_sbecc_r) @[dec_tlu_ctl.scala 315:192] - node _T_23 = or(_T_22, iccm_sbecc_r_d1) @[dec_tlu_ctl.scala 315:207] - node flush_clkvalid = or(_T_23, io.dec_tlu_dec_clk_override) @[dec_tlu_ctl.scala 315:225] - node _T_24 = or(e4e5_valid, io.dec_tlu_dec_clk_override) @[dec_tlu_ctl.scala 317:49] - node _T_25 = bits(_T_24, 0, 0) @[dec_tlu_ctl.scala 317:65] + node e4e5_valid = or(io.dec_tlu_i0_valid_r, e5_valid) @[dec_tlu_ctl.scala 315:30] + node _T_14 = or(debug_mode_status, i_cpu_run_req_d1) @[dec_tlu_ctl.scala 316:50] + node _T_15 = or(_T_14, interrupt_valid_r) @[dec_tlu_ctl.scala 316:69] + node _T_16 = or(_T_15, interrupt_valid_r_d1) @[dec_tlu_ctl.scala 316:89] + node _T_17 = or(_T_16, reset_delayed) @[dec_tlu_ctl.scala 316:112] + node _T_18 = or(_T_17, pause_expired_r) @[dec_tlu_ctl.scala 316:128] + node _T_19 = or(_T_18, pause_expired_wb) @[dec_tlu_ctl.scala 316:146] + node _T_20 = or(_T_19, ic_perr_r) @[dec_tlu_ctl.scala 316:165] + node _T_21 = or(_T_20, ic_perr_r_d1) @[dec_tlu_ctl.scala 316:177] + node _T_22 = or(_T_21, iccm_sbecc_r) @[dec_tlu_ctl.scala 316:192] + node _T_23 = or(_T_22, iccm_sbecc_r_d1) @[dec_tlu_ctl.scala 316:207] + node flush_clkvalid = or(_T_23, io.dec_tlu_dec_clk_override) @[dec_tlu_ctl.scala 316:225] + node _T_24 = or(e4e5_valid, io.dec_tlu_dec_clk_override) @[dec_tlu_ctl.scala 318:49] + node _T_25 = bits(_T_24, 0, 0) @[dec_tlu_ctl.scala 318:65] inst rvclkhdr_2 of rvclkhdr_718 @[lib.scala 343:22] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset rvclkhdr_2.io.clk <= clock @[lib.scala 344:17] rvclkhdr_2.io.en <= _T_25 @[lib.scala 345:16] rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - node _T_26 = or(e4e5_valid, flush_clkvalid) @[dec_tlu_ctl.scala 318:53] - node _T_27 = bits(_T_26, 0, 0) @[dec_tlu_ctl.scala 318:71] + node _T_26 = or(e4e5_valid, flush_clkvalid) @[dec_tlu_ctl.scala 319:53] + node _T_27 = bits(_T_26, 0, 0) @[dec_tlu_ctl.scala 319:71] inst rvclkhdr_3 of rvclkhdr_719 @[lib.scala 343:22] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset rvclkhdr_3.io.clk <= clock @[lib.scala 344:17] rvclkhdr_3.io.en <= _T_27 @[lib.scala 345:16] rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 346:23] - reg iccm_repair_state_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 320:80] - iccm_repair_state_d1 <= iccm_repair_state_ns @[dec_tlu_ctl.scala 320:80] - reg _T_28 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 321:89] - _T_28 <= ic_perr_r @[dec_tlu_ctl.scala 321:89] - ic_perr_r_d1 <= _T_28 @[dec_tlu_ctl.scala 321:57] - reg _T_29 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 322:89] - _T_29 <= iccm_sbecc_r @[dec_tlu_ctl.scala 322:89] - iccm_sbecc_r_d1 <= _T_29 @[dec_tlu_ctl.scala 322:57] - reg _T_30 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 323:97] - _T_30 <= io.dec_tlu_i0_valid_r @[dec_tlu_ctl.scala 323:97] - e5_valid <= _T_30 @[dec_tlu_ctl.scala 323:65] - reg _T_31 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 324:81] - _T_31 <= internal_dbg_halt_mode @[dec_tlu_ctl.scala 324:81] - debug_mode_status <= _T_31 @[dec_tlu_ctl.scala 324:49] - reg lsu_pmu_load_external_r : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 325:80] - lsu_pmu_load_external_r <= io.lsu_tlu.lsu_pmu_load_external_m @[dec_tlu_ctl.scala 325:80] - reg lsu_pmu_store_external_r : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 326:72] - lsu_pmu_store_external_r <= io.lsu_tlu.lsu_pmu_store_external_m @[dec_tlu_ctl.scala 326:72] - reg tlu_flush_lower_r_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 327:80] - tlu_flush_lower_r_d1 <= tlu_flush_lower_r @[dec_tlu_ctl.scala 327:80] - reg _T_32 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 328:73] - _T_32 <= tlu_i0_kill_writeb_r @[dec_tlu_ctl.scala 328:73] - io.dec_tlu_i0_kill_writeb_wb <= _T_32 @[dec_tlu_ctl.scala 328:41] - reg internal_dbg_halt_mode_f2 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 329:72] - internal_dbg_halt_mode_f2 <= debug_mode_status @[dec_tlu_ctl.scala 329:72] - reg _T_33 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 330:89] - _T_33 <= force_halt @[dec_tlu_ctl.scala 330:89] - io.tlu_mem.dec_tlu_force_halt <= _T_33 @[dec_tlu_ctl.scala 330:57] - io.dec_tlu_i0_kill_writeb_r <= tlu_i0_kill_writeb_r @[dec_tlu_ctl.scala 334:41] - reg reset_detect : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 335:88] - reset_detect <= UInt<1>("h01") @[dec_tlu_ctl.scala 335:88] - reg reset_detected : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 336:88] - reset_detected <= reset_detect @[dec_tlu_ctl.scala 336:88] - node _T_34 = xor(reset_detect, reset_detected) @[dec_tlu_ctl.scala 337:64] - reset_delayed <= _T_34 @[dec_tlu_ctl.scala 337:49] - reg nmi_int_delayed : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 339:72] - nmi_int_delayed <= nmi_int_sync @[dec_tlu_ctl.scala 339:72] - reg nmi_int_detected_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 340:72] - nmi_int_detected_f <= nmi_int_detected @[dec_tlu_ctl.scala 340:72] - reg nmi_lsu_load_type_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 341:72] - nmi_lsu_load_type_f <= nmi_lsu_load_type @[dec_tlu_ctl.scala 341:72] - reg nmi_lsu_store_type_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 342:72] - nmi_lsu_store_type_f <= nmi_lsu_store_type @[dec_tlu_ctl.scala 342:72] + reg iccm_repair_state_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 321:80] + iccm_repair_state_d1 <= iccm_repair_state_ns @[dec_tlu_ctl.scala 321:80] + reg _T_28 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 322:89] + _T_28 <= ic_perr_r @[dec_tlu_ctl.scala 322:89] + ic_perr_r_d1 <= _T_28 @[dec_tlu_ctl.scala 322:57] + reg _T_29 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 323:89] + _T_29 <= iccm_sbecc_r @[dec_tlu_ctl.scala 323:89] + iccm_sbecc_r_d1 <= _T_29 @[dec_tlu_ctl.scala 323:57] + reg _T_30 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 324:97] + _T_30 <= io.dec_tlu_i0_valid_r @[dec_tlu_ctl.scala 324:97] + e5_valid <= _T_30 @[dec_tlu_ctl.scala 324:65] + reg _T_31 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 325:81] + _T_31 <= internal_dbg_halt_mode @[dec_tlu_ctl.scala 325:81] + debug_mode_status <= _T_31 @[dec_tlu_ctl.scala 325:49] + reg lsu_pmu_load_external_r : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 326:80] + lsu_pmu_load_external_r <= io.lsu_tlu.lsu_pmu_load_external_m @[dec_tlu_ctl.scala 326:80] + reg lsu_pmu_store_external_r : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 327:72] + lsu_pmu_store_external_r <= io.lsu_tlu.lsu_pmu_store_external_m @[dec_tlu_ctl.scala 327:72] + reg tlu_flush_lower_r_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 328:80] + tlu_flush_lower_r_d1 <= tlu_flush_lower_r @[dec_tlu_ctl.scala 328:80] + reg _T_32 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 329:73] + _T_32 <= tlu_i0_kill_writeb_r @[dec_tlu_ctl.scala 329:73] + io.dec_tlu_i0_kill_writeb_wb <= _T_32 @[dec_tlu_ctl.scala 329:41] + reg internal_dbg_halt_mode_f2 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 330:72] + internal_dbg_halt_mode_f2 <= debug_mode_status @[dec_tlu_ctl.scala 330:72] + reg _T_33 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 331:89] + _T_33 <= force_halt @[dec_tlu_ctl.scala 331:89] + io.tlu_mem.dec_tlu_force_halt <= _T_33 @[dec_tlu_ctl.scala 331:57] + io.dec_tlu_i0_kill_writeb_r <= tlu_i0_kill_writeb_r @[dec_tlu_ctl.scala 333:41] + reg reset_detect : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 334:88] + reset_detect <= UInt<1>("h01") @[dec_tlu_ctl.scala 334:88] + reg reset_detected : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 335:88] + reset_detected <= reset_detect @[dec_tlu_ctl.scala 335:88] + node _T_34 = xor(reset_detect, reset_detected) @[dec_tlu_ctl.scala 336:64] + reset_delayed <= _T_34 @[dec_tlu_ctl.scala 336:49] + reg nmi_int_delayed : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 338:72] + nmi_int_delayed <= nmi_int_sync @[dec_tlu_ctl.scala 338:72] + reg nmi_int_detected_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 339:72] + nmi_int_detected_f <= nmi_int_detected @[dec_tlu_ctl.scala 339:72] + reg nmi_lsu_load_type_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 340:72] + nmi_lsu_load_type_f <= nmi_lsu_load_type @[dec_tlu_ctl.scala 340:72] + reg nmi_lsu_store_type_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 341:72] + nmi_lsu_store_type_f <= nmi_lsu_store_type @[dec_tlu_ctl.scala 341:72] + io.tlu_bp.dec_tlu_flush_lower_wb <= io.dec_tlu_flush_lower_wb @[dec_tlu_ctl.scala 343:42] + io.tlu_mem.dec_tlu_flush_lower_wb <= io.tlu_bp.dec_tlu_flush_lower_wb @[dec_tlu_ctl.scala 344:43] node _T_35 = not(mdseac_locked_f) @[dec_tlu_ctl.scala 346:32] node _T_36 = or(io.tlu_busbuff.lsu_imprecise_error_load_any, io.tlu_busbuff.lsu_imprecise_error_store_any) @[dec_tlu_ctl.scala 346:96] node nmi_lsu_detected = and(_T_35, _T_36) @[dec_tlu_ctl.scala 346:49] @@ -78417,7 +78428,7 @@ circuit quasar_wrapper : node dcsr_single_step_running = or(_T_177, _T_179) @[dec_tlu_ctl.scala 438:79] node dbg_cmd_done_ns = and(io.dec_tlu_i0_valid_r, io.dec_tlu_dbg_halted) @[dec_tlu_ctl.scala 440:53] node _T_180 = or(trigger_hit_dmode_r, ebreak_to_debug_mode_r) @[dec_tlu_ctl.scala 443:57] - node _T_181 = not(io.tlu_bp.dec_tlu_flush_lower_wb) @[dec_tlu_ctl.scala 443:112] + node _T_181 = not(io.dec_tlu_flush_lower_wb) @[dec_tlu_ctl.scala 443:112] node _T_182 = and(request_debug_mode_r_d1, _T_181) @[dec_tlu_ctl.scala 443:110] node request_debug_mode_r = or(_T_180, _T_182) @[dec_tlu_ctl.scala 443:83] node _T_183 = or(request_debug_mode_r_d1, request_debug_mode_done_f) @[dec_tlu_ctl.scala 445:64] @@ -78590,11 +78601,11 @@ circuit quasar_wrapper : node _T_295 = and(_T_294, i0_iside_trigger_has_pri_r) @[dec_tlu_ctl.scala 517:90] node _T_296 = and(_T_295, i0_lsu_trigger_has_pri_r) @[dec_tlu_ctl.scala 517:119] node i0trigger_qual_r = and(_T_296, trigger_enabled) @[dec_tlu_ctl.scala 517:146] - node _T_297 = or(io.tlu_bp.dec_tlu_flush_lower_wb, io.dec_tlu_dbg_halted) @[dec_tlu_ctl.scala 519:65] + node _T_297 = or(io.dec_tlu_flush_lower_wb, io.dec_tlu_dbg_halted) @[dec_tlu_ctl.scala 519:58] node _T_298 = bits(_T_297, 0, 0) @[Bitwise.scala 72:15] node _T_299 = mux(_T_298, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] node _T_300 = not(_T_299) @[dec_tlu_ctl.scala 519:23] - node i0_trigger_r = and(_T_300, i0trigger_qual_r) @[dec_tlu_ctl.scala 519:91] + node i0_trigger_r = and(_T_300, i0trigger_qual_r) @[dec_tlu_ctl.scala 519:84] node _T_301 = bits(i0_trigger_r, 3, 3) @[dec_tlu_ctl.scala 522:53] node _T_302 = bits(mtdata1_t[2], 5, 5) @[dec_tlu_ctl.scala 522:73] node _T_303 = not(_T_302) @[dec_tlu_ctl.scala 522:60] @@ -78740,7 +78751,7 @@ circuit quasar_wrapper : mdseac_locked_f <= _T_401 @[dec_tlu_ctl.scala 605:57] reg lsu_single_ecc_error_r_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 606:72] lsu_single_ecc_error_r_d1 <= io.lsu_single_ecc_error_incr @[dec_tlu_ctl.scala 606:72] - node _T_402 = not(io.tlu_bp.dec_tlu_flush_lower_wb) @[dec_tlu_ctl.scala 608:57] + node _T_402 = not(io.dec_tlu_flush_lower_wb) @[dec_tlu_ctl.scala 608:57] node lsu_exc_valid_r_raw = and(io.lsu_error_pkt_r.valid, _T_402) @[dec_tlu_ctl.scala 608:55] lsu_i0_exc_r_raw <= io.lsu_error_pkt_r.valid @[dec_tlu_ctl.scala 609:21] node _T_403 = and(lsu_i0_exc_r_raw, lsu_exc_valid_r_raw) @[dec_tlu_ctl.scala 610:40] @@ -79280,8 +79291,7 @@ circuit quasar_wrapper : node tlu_flush_path_r = mux(_T_803, io.rst_vec, _T_853) @[dec_tlu_ctl.scala 787:30] reg tlu_flush_path_r_d1 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 798:64] tlu_flush_path_r_d1 <= tlu_flush_path_r @[dec_tlu_ctl.scala 798:64] - io.tlu_bp.dec_tlu_flush_lower_wb <= tlu_flush_lower_r_d1 @[dec_tlu_ctl.scala 800:49] - io.tlu_mem.dec_tlu_flush_lower_wb <= io.tlu_bp.dec_tlu_flush_lower_wb @[dec_tlu_ctl.scala 801:41] + io.dec_tlu_flush_lower_wb <= tlu_flush_lower_r_d1 @[dec_tlu_ctl.scala 800:41] io.tlu_exu.dec_tlu_flush_lower_r <= tlu_flush_lower_r @[dec_tlu_ctl.scala 802:49] io.tlu_exu.dec_tlu_flush_path_r <= tlu_flush_path_r @[dec_tlu_ctl.scala 803:49] node _T_854 = or(lsu_exc_valid_r, i0_exception_valid_r) @[dec_tlu_ctl.scala 806:45] @@ -81403,7 +81413,7 @@ circuit quasar_wrapper : decode.io.lsu_store_stall_any <= io.lsu_store_stall_any @[dec.scala 162:48] decode.io.exu_div_wren <= io.exu_div_wren @[dec.scala 163:48] decode.io.dec_tlu_i0_kill_writeb_wb <= tlu.io.dec_tlu_i0_kill_writeb_wb @[dec.scala 164:48] - decode.io.dec_tlu_flush_lower_wb <= tlu.io.tlu_bp.dec_tlu_flush_lower_wb @[dec.scala 165:48] + decode.io.dec_tlu_flush_lower_wb <= tlu.io.dec_tlu_flush_lower_wb @[dec.scala 165:48] decode.io.dec_tlu_i0_kill_writeb_r <= tlu.io.dec_tlu_i0_kill_writeb_r @[dec.scala 166:48] decode.io.dec_tlu_flush_lower_r <= tlu.io.tlu_exu.dec_tlu_flush_lower_r @[dec.scala 167:48] decode.io.dec_tlu_flush_pause_r <= tlu.io.dec_tlu_flush_pause_r @[dec.scala 168:48] diff --git a/quasar_wrapper.v b/quasar_wrapper.v index 22ccee53..e858aa73 100644 --- a/quasar_wrapper.v +++ b/quasar_wrapper.v @@ -46049,6 +46049,9 @@ module dec_decode_ctl( input [1:0] io_dctl_busbuff_lsu_nonblock_load_data_tag, input [31:0] io_dctl_busbuff_lsu_nonblock_load_data, input io_dctl_dma_dma_dccm_stall_any, + output io_dec_aln_dec_i0_decode_d, + input [15:0] io_dec_aln_ifu_i0_cinst, + input [1:0] io_dbg_dctl_dbg_cmd_wrdata, input io_dec_tlu_flush_extint, input io_dec_tlu_force_halt, output [31:0] io_dec_i0_inst_wb1, @@ -46145,10 +46148,7 @@ module dec_decode_ctl( output io_dec_pause_state, output io_dec_pause_state_cg, output io_dec_div_active, - input io_scan_mode, - output io_dec_aln_dec_i0_decode_d, - input [15:0] io_dec_aln_ifu_i0_cinst, - input [1:0] io_dbg_dctl_dbg_cmd_wrdata + input io_scan_mode ); `ifdef RANDOMIZE_REG_INIT reg [31:0] _RAND_0; @@ -46247,57 +46247,57 @@ module dec_decode_ctl( wire rvclkhdr_io_clk; // @[lib.scala 343:22] wire rvclkhdr_io_en; // @[lib.scala 343:22] wire rvclkhdr_io_scan_mode; // @[lib.scala 343:22] - wire [31:0] i0_dec_io_ins; // @[dec_decode_ctl.scala 362:22] - wire i0_dec_io_out_alu; // @[dec_decode_ctl.scala 362:22] - wire i0_dec_io_out_rs1; // @[dec_decode_ctl.scala 362:22] - wire i0_dec_io_out_rs2; // @[dec_decode_ctl.scala 362:22] - wire i0_dec_io_out_imm12; // @[dec_decode_ctl.scala 362:22] - wire i0_dec_io_out_rd; // @[dec_decode_ctl.scala 362:22] - wire i0_dec_io_out_shimm5; // @[dec_decode_ctl.scala 362:22] - wire i0_dec_io_out_imm20; // @[dec_decode_ctl.scala 362:22] - wire i0_dec_io_out_pc; // @[dec_decode_ctl.scala 362:22] - wire i0_dec_io_out_load; // @[dec_decode_ctl.scala 362:22] - wire i0_dec_io_out_store; // @[dec_decode_ctl.scala 362:22] - wire i0_dec_io_out_lsu; // @[dec_decode_ctl.scala 362:22] - wire i0_dec_io_out_add; // @[dec_decode_ctl.scala 362:22] - wire i0_dec_io_out_sub; // @[dec_decode_ctl.scala 362:22] - wire i0_dec_io_out_land; // @[dec_decode_ctl.scala 362:22] - wire i0_dec_io_out_lor; // @[dec_decode_ctl.scala 362:22] - wire i0_dec_io_out_lxor; // @[dec_decode_ctl.scala 362:22] - wire i0_dec_io_out_sll; // @[dec_decode_ctl.scala 362:22] - wire i0_dec_io_out_sra; // @[dec_decode_ctl.scala 362:22] - wire i0_dec_io_out_srl; // @[dec_decode_ctl.scala 362:22] - wire i0_dec_io_out_slt; // @[dec_decode_ctl.scala 362:22] - wire i0_dec_io_out_unsign; // @[dec_decode_ctl.scala 362:22] - wire i0_dec_io_out_condbr; // @[dec_decode_ctl.scala 362:22] - wire i0_dec_io_out_beq; // @[dec_decode_ctl.scala 362:22] - wire i0_dec_io_out_bne; // @[dec_decode_ctl.scala 362:22] - wire i0_dec_io_out_bge; // @[dec_decode_ctl.scala 362:22] - wire i0_dec_io_out_blt; // @[dec_decode_ctl.scala 362:22] - wire i0_dec_io_out_jal; // @[dec_decode_ctl.scala 362:22] - wire i0_dec_io_out_by; // @[dec_decode_ctl.scala 362:22] - wire i0_dec_io_out_half; // @[dec_decode_ctl.scala 362:22] - wire i0_dec_io_out_word; // @[dec_decode_ctl.scala 362:22] - wire i0_dec_io_out_csr_read; // @[dec_decode_ctl.scala 362:22] - wire i0_dec_io_out_csr_clr; // @[dec_decode_ctl.scala 362:22] - wire i0_dec_io_out_csr_set; // @[dec_decode_ctl.scala 362:22] - wire i0_dec_io_out_csr_write; // @[dec_decode_ctl.scala 362:22] - wire i0_dec_io_out_csr_imm; // @[dec_decode_ctl.scala 362:22] - wire i0_dec_io_out_presync; // @[dec_decode_ctl.scala 362:22] - wire i0_dec_io_out_postsync; // @[dec_decode_ctl.scala 362:22] - wire i0_dec_io_out_ebreak; // @[dec_decode_ctl.scala 362:22] - wire i0_dec_io_out_ecall; // @[dec_decode_ctl.scala 362:22] - wire i0_dec_io_out_mret; // @[dec_decode_ctl.scala 362:22] - wire i0_dec_io_out_mul; // @[dec_decode_ctl.scala 362:22] - wire i0_dec_io_out_rs1_sign; // @[dec_decode_ctl.scala 362:22] - wire i0_dec_io_out_rs2_sign; // @[dec_decode_ctl.scala 362:22] - wire i0_dec_io_out_low; // @[dec_decode_ctl.scala 362:22] - wire i0_dec_io_out_div; // @[dec_decode_ctl.scala 362:22] - wire i0_dec_io_out_rem; // @[dec_decode_ctl.scala 362:22] - wire i0_dec_io_out_fence; // @[dec_decode_ctl.scala 362:22] - wire i0_dec_io_out_fence_i; // @[dec_decode_ctl.scala 362:22] - wire i0_dec_io_out_pm_alu; // @[dec_decode_ctl.scala 362:22] - wire i0_dec_io_out_legal; // @[dec_decode_ctl.scala 362:22] + wire [31:0] i0_dec_io_ins; // @[dec_decode_ctl.scala 356:22] + wire i0_dec_io_out_alu; // @[dec_decode_ctl.scala 356:22] + wire i0_dec_io_out_rs1; // @[dec_decode_ctl.scala 356:22] + wire i0_dec_io_out_rs2; // @[dec_decode_ctl.scala 356:22] + wire i0_dec_io_out_imm12; // @[dec_decode_ctl.scala 356:22] + wire i0_dec_io_out_rd; // @[dec_decode_ctl.scala 356:22] + wire i0_dec_io_out_shimm5; // @[dec_decode_ctl.scala 356:22] + wire i0_dec_io_out_imm20; // @[dec_decode_ctl.scala 356:22] + wire i0_dec_io_out_pc; // @[dec_decode_ctl.scala 356:22] + wire i0_dec_io_out_load; // @[dec_decode_ctl.scala 356:22] + wire i0_dec_io_out_store; // @[dec_decode_ctl.scala 356:22] + wire i0_dec_io_out_lsu; // @[dec_decode_ctl.scala 356:22] + wire i0_dec_io_out_add; // @[dec_decode_ctl.scala 356:22] + wire i0_dec_io_out_sub; // @[dec_decode_ctl.scala 356:22] + wire i0_dec_io_out_land; // @[dec_decode_ctl.scala 356:22] + wire i0_dec_io_out_lor; // @[dec_decode_ctl.scala 356:22] + wire i0_dec_io_out_lxor; // @[dec_decode_ctl.scala 356:22] + wire i0_dec_io_out_sll; // @[dec_decode_ctl.scala 356:22] + wire i0_dec_io_out_sra; // @[dec_decode_ctl.scala 356:22] + wire i0_dec_io_out_srl; // @[dec_decode_ctl.scala 356:22] + wire i0_dec_io_out_slt; // @[dec_decode_ctl.scala 356:22] + wire i0_dec_io_out_unsign; // @[dec_decode_ctl.scala 356:22] + wire i0_dec_io_out_condbr; // @[dec_decode_ctl.scala 356:22] + wire i0_dec_io_out_beq; // @[dec_decode_ctl.scala 356:22] + wire i0_dec_io_out_bne; // @[dec_decode_ctl.scala 356:22] + wire i0_dec_io_out_bge; // @[dec_decode_ctl.scala 356:22] + wire i0_dec_io_out_blt; // @[dec_decode_ctl.scala 356:22] + wire i0_dec_io_out_jal; // @[dec_decode_ctl.scala 356:22] + wire i0_dec_io_out_by; // @[dec_decode_ctl.scala 356:22] + wire i0_dec_io_out_half; // @[dec_decode_ctl.scala 356:22] + wire i0_dec_io_out_word; // @[dec_decode_ctl.scala 356:22] + wire i0_dec_io_out_csr_read; // @[dec_decode_ctl.scala 356:22] + wire i0_dec_io_out_csr_clr; // @[dec_decode_ctl.scala 356:22] + wire i0_dec_io_out_csr_set; // @[dec_decode_ctl.scala 356:22] + wire i0_dec_io_out_csr_write; // @[dec_decode_ctl.scala 356:22] + wire i0_dec_io_out_csr_imm; // @[dec_decode_ctl.scala 356:22] + wire i0_dec_io_out_presync; // @[dec_decode_ctl.scala 356:22] + wire i0_dec_io_out_postsync; // @[dec_decode_ctl.scala 356:22] + wire i0_dec_io_out_ebreak; // @[dec_decode_ctl.scala 356:22] + wire i0_dec_io_out_ecall; // @[dec_decode_ctl.scala 356:22] + wire i0_dec_io_out_mret; // @[dec_decode_ctl.scala 356:22] + wire i0_dec_io_out_mul; // @[dec_decode_ctl.scala 356:22] + wire i0_dec_io_out_rs1_sign; // @[dec_decode_ctl.scala 356:22] + wire i0_dec_io_out_rs2_sign; // @[dec_decode_ctl.scala 356:22] + wire i0_dec_io_out_low; // @[dec_decode_ctl.scala 356:22] + wire i0_dec_io_out_div; // @[dec_decode_ctl.scala 356:22] + wire i0_dec_io_out_rem; // @[dec_decode_ctl.scala 356:22] + wire i0_dec_io_out_fence; // @[dec_decode_ctl.scala 356:22] + wire i0_dec_io_out_fence_i; // @[dec_decode_ctl.scala 356:22] + wire i0_dec_io_out_pm_alu; // @[dec_decode_ctl.scala 356:22] + wire i0_dec_io_out_legal; // @[dec_decode_ctl.scala 356:22] wire rvclkhdr_1_io_l1clk; // @[lib.scala 368:23] wire rvclkhdr_1_io_clk; // @[lib.scala 368:23] wire rvclkhdr_1_io_en; // @[lib.scala 368:23] @@ -46374,249 +46374,249 @@ module dec_decode_ctl( wire rvclkhdr_19_io_clk; // @[lib.scala 368:23] wire rvclkhdr_19_io_en; // @[lib.scala 368:23] wire rvclkhdr_19_io_scan_mode; // @[lib.scala 368:23] - reg tlu_wr_pause_r1; // @[dec_decode_ctl.scala 469:55] - wire _T_1 = io_dec_tlu_wr_pause_r ^ tlu_wr_pause_r1; // @[dec_decode_ctl.scala 181:51] - reg tlu_wr_pause_r2; // @[dec_decode_ctl.scala 470:55] - wire _T_2 = tlu_wr_pause_r1 ^ tlu_wr_pause_r2; // @[dec_decode_ctl.scala 182:32] - wire _T_3 = _T_1 | _T_2; // @[dec_decode_ctl.scala 181:73] - wire _T_4 = io_dec_tlu_flush_extint ^ io_decode_exu_dec_extint_stall; // @[dec_decode_ctl.scala 183:32] - wire _T_5 = _T_3 | _T_4; // @[dec_decode_ctl.scala 182:56] - reg leak1_i1_stall; // @[dec_decode_ctl.scala 370:56] - wire _T_280 = ~io_dec_tlu_flush_lower_r; // @[dec_decode_ctl.scala 369:73] - wire _T_281 = leak1_i1_stall & _T_280; // @[dec_decode_ctl.scala 369:71] - wire leak1_i1_stall_in = io_dec_tlu_flush_leak_one_r | _T_281; // @[dec_decode_ctl.scala 369:53] - wire _T_6 = leak1_i1_stall_in ^ leak1_i1_stall; // @[dec_decode_ctl.scala 184:32] - wire _T_7 = _T_5 | _T_6; // @[dec_decode_ctl.scala 183:67] - wire _T_284 = io_dec_aln_dec_i0_decode_d & leak1_i1_stall; // @[dec_decode_ctl.scala 372:53] - reg leak1_i0_stall; // @[dec_decode_ctl.scala 373:56] - wire _T_286 = leak1_i0_stall & _T_280; // @[dec_decode_ctl.scala 372:89] - wire leak1_i0_stall_in = _T_284 | _T_286; // @[dec_decode_ctl.scala 372:71] - wire _T_8 = leak1_i0_stall_in ^ leak1_i0_stall; // @[dec_decode_ctl.scala 185:32] - wire _T_9 = _T_7 | _T_8; // @[dec_decode_ctl.scala 184:56] - reg pause_stall; // @[dec_decode_ctl.scala 467:50] - wire _T_415 = io_dec_tlu_wr_pause_r | pause_stall; // @[dec_decode_ctl.scala 466:44] - wire _T_408 = ~io_dec_tlu_flush_pause_r; // @[dec_decode_ctl.scala 465:49] - wire _T_409 = io_dec_tlu_flush_lower_r & _T_408; // @[dec_decode_ctl.scala 465:47] + reg tlu_wr_pause_r1; // @[dec_decode_ctl.scala 463:55] + wire _T_1 = io_dec_tlu_wr_pause_r ^ tlu_wr_pause_r1; // @[dec_decode_ctl.scala 178:54] + reg tlu_wr_pause_r2; // @[dec_decode_ctl.scala 464:55] + wire _T_2 = tlu_wr_pause_r1 ^ tlu_wr_pause_r2; // @[dec_decode_ctl.scala 179:54] + wire _T_3 = _T_1 | _T_2; // @[dec_decode_ctl.scala 178:89] + wire _T_4 = io_dec_tlu_flush_extint ^ io_decode_exu_dec_extint_stall; // @[dec_decode_ctl.scala 180:54] + wire _T_5 = _T_3 | _T_4; // @[dec_decode_ctl.scala 179:89] + reg leak1_i1_stall; // @[dec_decode_ctl.scala 364:56] + wire _T_280 = ~io_dec_tlu_flush_lower_r; // @[dec_decode_ctl.scala 363:73] + wire _T_281 = leak1_i1_stall & _T_280; // @[dec_decode_ctl.scala 363:71] + wire leak1_i1_stall_in = io_dec_tlu_flush_leak_one_r | _T_281; // @[dec_decode_ctl.scala 363:53] + wire _T_6 = leak1_i1_stall_in ^ leak1_i1_stall; // @[dec_decode_ctl.scala 181:54] + wire _T_7 = _T_5 | _T_6; // @[dec_decode_ctl.scala 180:89] + wire _T_284 = io_dec_aln_dec_i0_decode_d & leak1_i1_stall; // @[dec_decode_ctl.scala 366:53] + reg leak1_i0_stall; // @[dec_decode_ctl.scala 367:56] + wire _T_286 = leak1_i0_stall & _T_280; // @[dec_decode_ctl.scala 366:89] + wire leak1_i0_stall_in = _T_284 | _T_286; // @[dec_decode_ctl.scala 366:71] + wire _T_8 = leak1_i0_stall_in ^ leak1_i0_stall; // @[dec_decode_ctl.scala 182:54] + wire _T_9 = _T_7 | _T_8; // @[dec_decode_ctl.scala 181:89] + reg pause_stall; // @[dec_decode_ctl.scala 461:50] + wire _T_415 = io_dec_tlu_wr_pause_r | pause_stall; // @[dec_decode_ctl.scala 460:44] + wire _T_408 = ~io_dec_tlu_flush_pause_r; // @[dec_decode_ctl.scala 459:49] + wire _T_409 = io_dec_tlu_flush_lower_r & _T_408; // @[dec_decode_ctl.scala 459:47] reg [31:0] write_csr_data; // @[lib.scala 374:16] wire [31:0] _T_412 = {31'h0,write_csr_data[0]}; // @[Cat.scala 29:58] - wire _T_413 = write_csr_data == _T_412; // @[dec_decode_ctl.scala 465:109] - wire _T_414 = pause_stall & _T_413; // @[dec_decode_ctl.scala 465:91] - wire clear_pause = _T_409 | _T_414; // @[dec_decode_ctl.scala 465:76] - wire _T_416 = ~clear_pause; // @[dec_decode_ctl.scala 466:61] - wire pause_state_in = _T_415 & _T_416; // @[dec_decode_ctl.scala 466:59] - wire _T_10 = pause_state_in ^ pause_stall; // @[dec_decode_ctl.scala 186:32] - wire _T_11 = _T_9 | _T_10; // @[dec_decode_ctl.scala 185:56] - wire _T_18 = ~leak1_i1_stall; // @[dec_decode_ctl.scala 196:62] - wire i0_brp_valid = io_dec_i0_brp_valid & _T_18; // @[dec_decode_ctl.scala 196:60] - wire i0_dp_raw_condbr = i0_dec_io_out_condbr; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] - wire i0_dp_raw_jal = i0_dec_io_out_jal; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] + wire _T_413 = write_csr_data == _T_412; // @[dec_decode_ctl.scala 459:109] + wire _T_414 = pause_stall & _T_413; // @[dec_decode_ctl.scala 459:91] + wire clear_pause = _T_409 | _T_414; // @[dec_decode_ctl.scala 459:76] + wire _T_416 = ~clear_pause; // @[dec_decode_ctl.scala 460:61] + wire pause_state_in = _T_415 & _T_416; // @[dec_decode_ctl.scala 460:59] + wire _T_10 = pause_state_in ^ pause_stall; // @[dec_decode_ctl.scala 183:54] + wire _T_11 = _T_9 | _T_10; // @[dec_decode_ctl.scala 182:89] + wire _T_18 = ~leak1_i1_stall; // @[dec_decode_ctl.scala 192:80] + wire i0_brp_valid = io_dec_i0_brp_valid & _T_18; // @[dec_decode_ctl.scala 192:78] + wire i0_dp_raw_condbr = i0_dec_io_out_condbr; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] + wire i0_dp_raw_jal = i0_dec_io_out_jal; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] wire [19:0] i0_pcall_imm = {io_dec_i0_instr_d[31],io_dec_i0_instr_d[19:12],io_dec_i0_instr_d[20],io_dec_i0_instr_d[30:21]}; // @[Cat.scala 29:58] - wire _T_298 = i0_pcall_imm[19:12] == 8'hff; // @[dec_decode_ctl.scala 378:79] - wire _T_300 = i0_pcall_imm[19:12] == 8'h0; // @[dec_decode_ctl.scala 378:112] - wire i0_pcall_12b_offset = i0_pcall_imm[11] ? _T_298 : _T_300; // @[dec_decode_ctl.scala 378:33] - wire i0_dp_raw_imm20 = i0_dec_io_out_imm20; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] - wire _T_301 = i0_pcall_12b_offset & i0_dp_raw_imm20; // @[dec_decode_ctl.scala 379:47] - wire [4:0] i0r_rd = io_dec_i0_instr_d[11:7]; // @[dec_decode_ctl.scala 592:16] - wire _T_302 = i0r_rd == 5'h1; // @[dec_decode_ctl.scala 379:76] - wire _T_303 = i0r_rd == 5'h5; // @[dec_decode_ctl.scala 379:98] - wire _T_304 = _T_302 | _T_303; // @[dec_decode_ctl.scala 379:89] - wire i0_pcall_case = _T_301 & _T_304; // @[dec_decode_ctl.scala 379:65] - wire i0_pcall_raw = i0_dp_raw_jal & i0_pcall_case; // @[dec_decode_ctl.scala 381:38] - wire _T_20 = i0_dp_raw_condbr | i0_pcall_raw; // @[dec_decode_ctl.scala 207:75] - wire _T_309 = ~_T_304; // @[dec_decode_ctl.scala 380:67] - wire i0_pja_case = _T_301 & _T_309; // @[dec_decode_ctl.scala 380:65] - wire i0_pja_raw = i0_dp_raw_jal & i0_pja_case; // @[dec_decode_ctl.scala 383:38] - wire _T_21 = _T_20 | i0_pja_raw; // @[dec_decode_ctl.scala 207:90] - wire i0_dp_raw_imm12 = i0_dec_io_out_imm12; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] - wire _T_325 = i0_dp_raw_jal & i0_dp_raw_imm12; // @[dec_decode_ctl.scala 387:37] - wire _T_326 = i0r_rd == 5'h0; // @[dec_decode_ctl.scala 387:65] - wire _T_327 = _T_325 & _T_326; // @[dec_decode_ctl.scala 387:55] - wire [4:0] i0r_rs1 = io_dec_i0_instr_d[19:15]; // @[dec_decode_ctl.scala 590:16] - wire _T_328 = i0r_rs1 == 5'h1; // @[dec_decode_ctl.scala 387:89] - wire _T_329 = i0r_rs1 == 5'h5; // @[dec_decode_ctl.scala 387:111] - wire _T_330 = _T_328 | _T_329; // @[dec_decode_ctl.scala 387:101] - wire i0_pret_case = _T_327 & _T_330; // @[dec_decode_ctl.scala 387:79] - wire i0_pret_raw = i0_dp_raw_jal & i0_pret_case; // @[dec_decode_ctl.scala 388:32] - wire _T_22 = _T_21 | i0_pret_raw; // @[dec_decode_ctl.scala 207:103] - wire _T_23 = ~_T_22; // @[dec_decode_ctl.scala 207:56] - wire i0_notbr_error = i0_brp_valid & _T_23; // @[dec_decode_ctl.scala 207:54] - wire _T_31 = io_dec_i0_brp_bits_br_error | i0_notbr_error; // @[dec_decode_ctl.scala 212:62] - wire _T_25 = i0_brp_valid & io_dec_i0_brp_bits_hist[1]; // @[dec_decode_ctl.scala 210:47] - wire _T_314 = i0_pcall_raw | i0_pja_raw; // @[dec_decode_ctl.scala 385:41] + wire _T_298 = i0_pcall_imm[19:12] == 8'hff; // @[dec_decode_ctl.scala 372:79] + wire _T_300 = i0_pcall_imm[19:12] == 8'h0; // @[dec_decode_ctl.scala 372:112] + wire i0_pcall_12b_offset = i0_pcall_imm[11] ? _T_298 : _T_300; // @[dec_decode_ctl.scala 372:33] + wire i0_dp_raw_imm20 = i0_dec_io_out_imm20; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] + wire _T_301 = i0_pcall_12b_offset & i0_dp_raw_imm20; // @[dec_decode_ctl.scala 373:47] + wire [4:0] i0r_rd = io_dec_i0_instr_d[11:7]; // @[dec_decode_ctl.scala 586:16] + wire _T_302 = i0r_rd == 5'h1; // @[dec_decode_ctl.scala 373:76] + wire _T_303 = i0r_rd == 5'h5; // @[dec_decode_ctl.scala 373:98] + wire _T_304 = _T_302 | _T_303; // @[dec_decode_ctl.scala 373:89] + wire i0_pcall_case = _T_301 & _T_304; // @[dec_decode_ctl.scala 373:65] + wire i0_pcall_raw = i0_dp_raw_jal & i0_pcall_case; // @[dec_decode_ctl.scala 375:38] + wire _T_20 = i0_dp_raw_condbr | i0_pcall_raw; // @[dec_decode_ctl.scala 203:92] + wire _T_309 = ~_T_304; // @[dec_decode_ctl.scala 374:67] + wire i0_pja_case = _T_301 & _T_309; // @[dec_decode_ctl.scala 374:65] + wire i0_pja_raw = i0_dp_raw_jal & i0_pja_case; // @[dec_decode_ctl.scala 377:38] + wire _T_21 = _T_20 | i0_pja_raw; // @[dec_decode_ctl.scala 203:107] + wire i0_dp_raw_imm12 = i0_dec_io_out_imm12; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] + wire _T_325 = i0_dp_raw_jal & i0_dp_raw_imm12; // @[dec_decode_ctl.scala 381:37] + wire _T_326 = i0r_rd == 5'h0; // @[dec_decode_ctl.scala 381:65] + wire _T_327 = _T_325 & _T_326; // @[dec_decode_ctl.scala 381:55] + wire [4:0] i0r_rs1 = io_dec_i0_instr_d[19:15]; // @[dec_decode_ctl.scala 584:16] + wire _T_328 = i0r_rs1 == 5'h1; // @[dec_decode_ctl.scala 381:89] + wire _T_329 = i0r_rs1 == 5'h5; // @[dec_decode_ctl.scala 381:111] + wire _T_330 = _T_328 | _T_329; // @[dec_decode_ctl.scala 381:101] + wire i0_pret_case = _T_327 & _T_330; // @[dec_decode_ctl.scala 381:79] + wire i0_pret_raw = i0_dp_raw_jal & i0_pret_case; // @[dec_decode_ctl.scala 382:32] + wire _T_22 = _T_21 | i0_pret_raw; // @[dec_decode_ctl.scala 203:120] + wire _T_23 = ~_T_22; // @[dec_decode_ctl.scala 203:73] + wire i0_notbr_error = i0_brp_valid & _T_23; // @[dec_decode_ctl.scala 203:71] + wire _T_31 = io_dec_i0_brp_bits_br_error | i0_notbr_error; // @[dec_decode_ctl.scala 208:87] + wire _T_25 = i0_brp_valid & io_dec_i0_brp_bits_hist[1]; // @[dec_decode_ctl.scala 206:72] + wire _T_314 = i0_pcall_raw | i0_pja_raw; // @[dec_decode_ctl.scala 379:41] wire [11:0] _T_323 = {io_dec_i0_instr_d[31],io_dec_i0_instr_d[7],io_dec_i0_instr_d[30:25],io_dec_i0_instr_d[11:8]}; // @[Cat.scala 29:58] - wire [11:0] i0_br_offset = _T_314 ? i0_pcall_imm[11:0] : _T_323; // @[dec_decode_ctl.scala 385:26] - wire _T_26 = io_dec_i0_brp_bits_toffset != i0_br_offset; // @[dec_decode_ctl.scala 210:106] - wire _T_27 = _T_25 & _T_26; // @[dec_decode_ctl.scala 210:76] - wire _T_28 = ~i0_pret_raw; // @[dec_decode_ctl.scala 210:126] - wire i0_br_toffset_error = _T_27 & _T_28; // @[dec_decode_ctl.scala 210:124] - wire _T_32 = _T_31 | i0_br_toffset_error; // @[dec_decode_ctl.scala 212:79] - wire _T_29 = i0_brp_valid & io_dec_i0_brp_bits_ret; // @[dec_decode_ctl.scala 211:47] - wire i0_ret_error = _T_29 & _T_28; // @[dec_decode_ctl.scala 211:72] - wire i0_br_error = _T_32 | i0_ret_error; // @[dec_decode_ctl.scala 212:101] - wire _T_39 = i0_br_error | io_dec_i0_brp_bits_br_start_error; // @[dec_decode_ctl.scala 217:47] - wire i0_br_error_all = _T_39 & _T_18; // @[dec_decode_ctl.scala 217:84] - wire i0_icaf_d = io_dec_i0_icaf_d | io_dec_i0_dbecc_d; // @[dec_decode_ctl.scala 226:36] - wire _T_41 = i0_br_error_all | i0_icaf_d; // @[dec_decode_ctl.scala 230:25] - wire i0_dp_raw_postsync = i0_dec_io_out_postsync; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] - wire i0_dp_postsync = _T_41 | i0_dp_raw_postsync; // @[dec_decode_ctl.scala 230:50] - wire _T_442 = i0_dp_postsync | io_dec_tlu_postsync_d; // @[dec_decode_ctl.scala 496:36] - wire debug_fence_i = io_dec_debug_fence_d & io_dbg_dctl_dbg_cmd_wrdata[0]; // @[dec_decode_ctl.scala 488:48] - wire _T_443 = _T_442 | debug_fence_i; // @[dec_decode_ctl.scala 496:60] - wire i0_dp_raw_csr_write = i0_dec_io_out_csr_write; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] - wire i0_dp_csr_write = _T_41 ? 1'h0 : i0_dp_raw_csr_write; // @[dec_decode_ctl.scala 230:50] - wire _T_343 = ~io_dec_debug_fence_d; // @[dec_decode_ctl.scala 427:42] - wire i0_csr_write = i0_dp_csr_write & _T_343; // @[dec_decode_ctl.scala 427:40] - wire i0_dp_raw_csr_read = i0_dec_io_out_csr_read; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] - wire i0_dp_csr_read = _T_41 ? 1'h0 : i0_dp_raw_csr_read; // @[dec_decode_ctl.scala 230:50] - wire _T_347 = ~i0_dp_csr_read; // @[dec_decode_ctl.scala 432:41] - wire i0_csr_write_only_d = i0_csr_write & _T_347; // @[dec_decode_ctl.scala 432:39] - wire _T_445 = io_dec_i0_instr_d[31:20] == 12'h7c2; // @[dec_decode_ctl.scala 496:112] - wire _T_446 = i0_csr_write_only_d & _T_445; // @[dec_decode_ctl.scala 496:99] - wire i0_postsync = _T_443 | _T_446; // @[dec_decode_ctl.scala 496:76] - wire i0_dp_raw_legal = i0_dec_io_out_legal; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] - wire i0_dp_legal = _T_41 | i0_dp_raw_legal; // @[dec_decode_ctl.scala 230:50] - wire any_csr_d = i0_dp_csr_read | i0_csr_write; // @[dec_decode_ctl.scala 498:34] - wire _T_447 = ~any_csr_d; // @[dec_decode_ctl.scala 500:40] - wire _T_448 = _T_447 | io_dec_csr_legal_d; // @[dec_decode_ctl.scala 500:51] - wire i0_legal = i0_dp_legal & _T_448; // @[dec_decode_ctl.scala 500:37] - wire _T_507 = ~i0_legal; // @[dec_decode_ctl.scala 540:64] - wire _T_508 = i0_postsync | _T_507; // @[dec_decode_ctl.scala 540:62] - wire _T_509 = io_dec_aln_dec_i0_decode_d & _T_508; // @[dec_decode_ctl.scala 540:47] - reg postsync_stall; // @[dec_decode_ctl.scala 538:53] + wire [11:0] i0_br_offset = _T_314 ? i0_pcall_imm[11:0] : _T_323; // @[dec_decode_ctl.scala 379:26] + wire _T_26 = io_dec_i0_brp_bits_toffset != i0_br_offset; // @[dec_decode_ctl.scala 206:131] + wire _T_27 = _T_25 & _T_26; // @[dec_decode_ctl.scala 206:101] + wire _T_28 = ~i0_pret_raw; // @[dec_decode_ctl.scala 206:151] + wire i0_br_toffset_error = _T_27 & _T_28; // @[dec_decode_ctl.scala 206:149] + wire _T_32 = _T_31 | i0_br_toffset_error; // @[dec_decode_ctl.scala 208:104] + wire _T_29 = i0_brp_valid & io_dec_i0_brp_bits_ret; // @[dec_decode_ctl.scala 207:72] + wire i0_ret_error = _T_29 & _T_28; // @[dec_decode_ctl.scala 207:97] + wire i0_br_error = _T_32 | i0_ret_error; // @[dec_decode_ctl.scala 208:126] + wire _T_39 = i0_br_error | io_dec_i0_brp_bits_br_start_error; // @[dec_decode_ctl.scala 213:72] + wire i0_br_error_all = _T_39 & _T_18; // @[dec_decode_ctl.scala 213:109] + wire i0_icaf_d = io_dec_i0_icaf_d | io_dec_i0_dbecc_d; // @[dec_decode_ctl.scala 222:43] + wire _T_41 = i0_br_error_all | i0_icaf_d; // @[dec_decode_ctl.scala 225:25] + wire i0_dp_raw_postsync = i0_dec_io_out_postsync; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] + wire i0_dp_postsync = _T_41 | i0_dp_raw_postsync; // @[dec_decode_ctl.scala 225:50] + wire _T_442 = i0_dp_postsync | io_dec_tlu_postsync_d; // @[dec_decode_ctl.scala 490:36] + wire debug_fence_i = io_dec_debug_fence_d & io_dbg_dctl_dbg_cmd_wrdata[0]; // @[dec_decode_ctl.scala 482:48] + wire _T_443 = _T_442 | debug_fence_i; // @[dec_decode_ctl.scala 490:60] + wire i0_dp_raw_csr_write = i0_dec_io_out_csr_write; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] + wire i0_dp_csr_write = _T_41 ? 1'h0 : i0_dp_raw_csr_write; // @[dec_decode_ctl.scala 225:50] + wire _T_343 = ~io_dec_debug_fence_d; // @[dec_decode_ctl.scala 421:42] + wire i0_csr_write = i0_dp_csr_write & _T_343; // @[dec_decode_ctl.scala 421:40] + wire i0_dp_raw_csr_read = i0_dec_io_out_csr_read; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] + wire i0_dp_csr_read = _T_41 ? 1'h0 : i0_dp_raw_csr_read; // @[dec_decode_ctl.scala 225:50] + wire _T_347 = ~i0_dp_csr_read; // @[dec_decode_ctl.scala 426:41] + wire i0_csr_write_only_d = i0_csr_write & _T_347; // @[dec_decode_ctl.scala 426:39] + wire _T_445 = io_dec_i0_instr_d[31:20] == 12'h7c2; // @[dec_decode_ctl.scala 490:112] + wire _T_446 = i0_csr_write_only_d & _T_445; // @[dec_decode_ctl.scala 490:99] + wire i0_postsync = _T_443 | _T_446; // @[dec_decode_ctl.scala 490:76] + wire i0_dp_raw_legal = i0_dec_io_out_legal; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] + wire i0_dp_legal = _T_41 | i0_dp_raw_legal; // @[dec_decode_ctl.scala 225:50] + wire any_csr_d = i0_dp_csr_read | i0_csr_write; // @[dec_decode_ctl.scala 492:34] + wire _T_447 = ~any_csr_d; // @[dec_decode_ctl.scala 494:40] + wire _T_448 = _T_447 | io_dec_csr_legal_d; // @[dec_decode_ctl.scala 494:51] + wire i0_legal = i0_dp_legal & _T_448; // @[dec_decode_ctl.scala 494:37] + wire _T_507 = ~i0_legal; // @[dec_decode_ctl.scala 534:64] + wire _T_508 = i0_postsync | _T_507; // @[dec_decode_ctl.scala 534:62] + wire _T_509 = io_dec_aln_dec_i0_decode_d & _T_508; // @[dec_decode_ctl.scala 534:47] + reg postsync_stall; // @[dec_decode_ctl.scala 532:53] reg x_d_valid; // @[lib.scala 384:16] - wire _T_510 = postsync_stall & x_d_valid; // @[dec_decode_ctl.scala 540:96] - wire ps_stall_in = _T_509 | _T_510; // @[dec_decode_ctl.scala 540:77] - wire _T_12 = ps_stall_in ^ postsync_stall; // @[dec_decode_ctl.scala 187:32] - wire _T_13 = _T_11 | _T_12; // @[dec_decode_ctl.scala 186:56] - reg flush_final_r; // @[dec_decode_ctl.scala 586:52] - wire _T_14 = io_exu_flush_final ^ flush_final_r; // @[dec_decode_ctl.scala 188:32] - wire _T_15 = _T_13 | _T_14; // @[dec_decode_ctl.scala 187:56] - wire shift_illegal = io_dec_aln_dec_i0_decode_d & _T_507; // @[dec_decode_ctl.scala 504:55] - reg illegal_lockout; // @[dec_decode_ctl.scala 508:54] - wire _T_469 = shift_illegal | illegal_lockout; // @[dec_decode_ctl.scala 507:40] - wire _T_470 = ~flush_final_r; // @[dec_decode_ctl.scala 507:61] - wire illegal_lockout_in = _T_469 & _T_470; // @[dec_decode_ctl.scala 507:59] - wire _T_16 = illegal_lockout_in ^ illegal_lockout; // @[dec_decode_ctl.scala 189:32] - wire i0_legal_decode_d = io_dec_aln_dec_i0_decode_d & i0_legal; // @[dec_decode_ctl.scala 614:54] - wire _T_33 = i0_br_error & i0_legal_decode_d; // @[dec_decode_ctl.scala 213:83] - wire _T_36 = io_dec_i0_brp_bits_br_start_error & i0_legal_decode_d; // @[dec_decode_ctl.scala 214:105] - wire i0_dp_raw_pm_alu = i0_dec_io_out_pm_alu; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] - wire i0_dp_pm_alu = _T_41 ? 1'h0 : i0_dp_raw_pm_alu; // @[dec_decode_ctl.scala 230:50] - wire i0_dp_raw_fence_i = i0_dec_io_out_fence_i; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] - wire i0_dp_fence_i = _T_41 ? 1'h0 : i0_dp_raw_fence_i; // @[dec_decode_ctl.scala 230:50] - wire i0_dp_raw_fence = i0_dec_io_out_fence; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] - wire i0_dp_fence = _T_41 ? 1'h0 : i0_dp_raw_fence; // @[dec_decode_ctl.scala 230:50] - wire i0_dp_raw_rem = i0_dec_io_out_rem; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] - wire i0_dp_raw_div = i0_dec_io_out_div; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] - wire i0_dp_div = _T_41 ? 1'h0 : i0_dp_raw_div; // @[dec_decode_ctl.scala 230:50] - wire i0_dp_raw_low = i0_dec_io_out_low; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] - wire i0_dp_raw_rs2_sign = i0_dec_io_out_rs2_sign; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] - wire i0_dp_raw_rs1_sign = i0_dec_io_out_rs1_sign; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] - wire i0_dp_raw_mul = i0_dec_io_out_mul; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] - wire i0_dp_mul = _T_41 ? 1'h0 : i0_dp_raw_mul; // @[dec_decode_ctl.scala 230:50] - wire i0_dp_raw_mret = i0_dec_io_out_mret; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] - wire i0_dp_mret = _T_41 ? 1'h0 : i0_dp_raw_mret; // @[dec_decode_ctl.scala 230:50] - wire i0_dp_raw_ecall = i0_dec_io_out_ecall; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] - wire i0_dp_ecall = _T_41 ? 1'h0 : i0_dp_raw_ecall; // @[dec_decode_ctl.scala 230:50] - wire i0_dp_raw_ebreak = i0_dec_io_out_ebreak; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] - wire i0_dp_ebreak = _T_41 ? 1'h0 : i0_dp_raw_ebreak; // @[dec_decode_ctl.scala 230:50] - wire i0_dp_raw_presync = i0_dec_io_out_presync; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] - wire i0_dp_presync = _T_41 ? 1'h0 : i0_dp_raw_presync; // @[dec_decode_ctl.scala 230:50] - wire i0_dp_raw_csr_imm = i0_dec_io_out_csr_imm; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] - wire i0_dp_csr_imm = _T_41 ? 1'h0 : i0_dp_raw_csr_imm; // @[dec_decode_ctl.scala 230:50] - wire i0_dp_raw_csr_set = i0_dec_io_out_csr_set; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] - wire i0_dp_csr_set = _T_41 ? 1'h0 : i0_dp_raw_csr_set; // @[dec_decode_ctl.scala 230:50] - wire i0_dp_raw_csr_clr = i0_dec_io_out_csr_clr; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] - wire i0_dp_csr_clr = _T_41 ? 1'h0 : i0_dp_raw_csr_clr; // @[dec_decode_ctl.scala 230:50] - wire i0_dp_raw_word = i0_dec_io_out_word; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] - wire i0_dp_word = _T_41 ? 1'h0 : i0_dp_raw_word; // @[dec_decode_ctl.scala 230:50] - wire i0_dp_raw_half = i0_dec_io_out_half; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] - wire i0_dp_half = _T_41 ? 1'h0 : i0_dp_raw_half; // @[dec_decode_ctl.scala 230:50] - wire i0_dp_raw_by = i0_dec_io_out_by; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] - wire i0_dp_by = _T_41 ? 1'h0 : i0_dp_raw_by; // @[dec_decode_ctl.scala 230:50] - wire i0_dp_jal = _T_41 ? 1'h0 : i0_dp_raw_jal; // @[dec_decode_ctl.scala 230:50] - wire i0_dp_raw_blt = i0_dec_io_out_blt; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] - wire i0_dp_raw_bge = i0_dec_io_out_bge; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] - wire i0_dp_raw_bne = i0_dec_io_out_bne; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] - wire i0_dp_raw_beq = i0_dec_io_out_beq; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] - wire i0_dp_condbr = _T_41 ? 1'h0 : i0_dp_raw_condbr; // @[dec_decode_ctl.scala 230:50] - wire i0_dp_raw_unsign = i0_dec_io_out_unsign; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] - wire i0_dp_unsign = _T_41 ? 1'h0 : i0_dp_raw_unsign; // @[dec_decode_ctl.scala 230:50] - wire i0_dp_raw_slt = i0_dec_io_out_slt; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] - wire i0_dp_raw_srl = i0_dec_io_out_srl; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] - wire i0_dp_raw_sra = i0_dec_io_out_sra; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] - wire i0_dp_raw_sll = i0_dec_io_out_sll; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] - wire i0_dp_raw_lxor = i0_dec_io_out_lxor; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] - wire i0_dp_raw_lor = i0_dec_io_out_lor; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] - wire i0_dp_raw_land = i0_dec_io_out_land; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] - wire i0_dp_raw_sub = i0_dec_io_out_sub; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] - wire i0_dp_raw_add = i0_dec_io_out_add; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] - wire i0_dp_raw_lsu = i0_dec_io_out_lsu; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] - wire i0_dp_lsu = _T_41 ? 1'h0 : i0_dp_raw_lsu; // @[dec_decode_ctl.scala 230:50] - wire i0_dp_raw_store = i0_dec_io_out_store; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] - wire i0_dp_store = _T_41 ? 1'h0 : i0_dp_raw_store; // @[dec_decode_ctl.scala 230:50] - wire i0_dp_raw_load = i0_dec_io_out_load; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] - wire i0_dp_load = _T_41 ? 1'h0 : i0_dp_raw_load; // @[dec_decode_ctl.scala 230:50] - wire i0_dp_raw_pc = i0_dec_io_out_pc; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] - wire i0_dp_imm20 = _T_41 ? 1'h0 : i0_dp_raw_imm20; // @[dec_decode_ctl.scala 230:50] - wire i0_dp_raw_shimm5 = i0_dec_io_out_shimm5; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] - wire i0_dp_shimm5 = _T_41 ? 1'h0 : i0_dp_raw_shimm5; // @[dec_decode_ctl.scala 230:50] - wire i0_dp_raw_rd = i0_dec_io_out_rd; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] - wire i0_dp_rd = _T_41 ? 1'h0 : i0_dp_raw_rd; // @[dec_decode_ctl.scala 230:50] - wire i0_dp_imm12 = _T_41 ? 1'h0 : i0_dp_raw_imm12; // @[dec_decode_ctl.scala 230:50] - wire i0_dp_raw_rs2 = i0_dec_io_out_rs2; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] - wire i0_dp_rs2 = _T_41 | i0_dp_raw_rs2; // @[dec_decode_ctl.scala 230:50] - wire i0_dp_raw_rs1 = i0_dec_io_out_rs1; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] - wire i0_dp_rs1 = _T_41 | i0_dp_raw_rs1; // @[dec_decode_ctl.scala 230:50] - wire i0_dp_raw_alu = i0_dec_io_out_alu; // @[dec_decode_ctl.scala 127:22 dec_decode_ctl.scala 364:12] - wire i0_dp_alu = _T_41 | i0_dp_raw_alu; // @[dec_decode_ctl.scala 230:50] - wire i0_pcall = i0_dp_jal & i0_pcall_case; // @[dec_decode_ctl.scala 382:38] - wire _T_44 = i0_dp_condbr | i0_pcall; // @[dec_decode_ctl.scala 244:40] - wire i0_pja = i0_dp_jal & i0_pja_case; // @[dec_decode_ctl.scala 384:38] - wire _T_45 = _T_44 | i0_pja; // @[dec_decode_ctl.scala 244:51] - wire i0_pret = i0_dp_jal & i0_pret_case; // @[dec_decode_ctl.scala 389:32] - wire i0_predict_br = _T_45 | i0_pret; // @[dec_decode_ctl.scala 244:60] - wire _T_47 = io_dec_i0_brp_bits_hist[1] & i0_brp_valid; // @[dec_decode_ctl.scala 246:55] - wire _T_48 = ~_T_47; // @[dec_decode_ctl.scala 246:26] - wire i0_ap_pc2 = ~io_dec_i0_pc4_d; // @[dec_decode_ctl.scala 248:20] - wire cam_data_reset = io_dctl_busbuff_lsu_nonblock_load_data_valid | io_dctl_busbuff_lsu_nonblock_load_data_error; // @[dec_decode_ctl.scala 281:76] - reg [2:0] cam_raw_0_bits_tag; // @[dec_decode_ctl.scala 317:47] - wire [2:0] _GEN_123 = {{1'd0}, io_dctl_busbuff_lsu_nonblock_load_data_tag}; // @[dec_decode_ctl.scala 292:67] - wire _T_94 = _GEN_123 == cam_raw_0_bits_tag; // @[dec_decode_ctl.scala 292:67] - wire _T_95 = cam_data_reset & _T_94; // @[dec_decode_ctl.scala 292:45] - reg cam_raw_0_valid; // @[dec_decode_ctl.scala 317:47] - wire cam_data_reset_val_0 = _T_95 & cam_raw_0_valid; // @[dec_decode_ctl.scala 292:88] - wire cam_0_valid = cam_data_reset_val_0 ? 1'h0 : cam_raw_0_valid; // @[dec_decode_ctl.scala 296:39] - wire _T_51 = ~cam_0_valid; // @[dec_decode_ctl.scala 273:78] - reg [2:0] cam_raw_1_bits_tag; // @[dec_decode_ctl.scala 317:47] - wire _T_120 = _GEN_123 == cam_raw_1_bits_tag; // @[dec_decode_ctl.scala 292:67] - wire _T_121 = cam_data_reset & _T_120; // @[dec_decode_ctl.scala 292:45] - reg cam_raw_1_valid; // @[dec_decode_ctl.scala 317:47] - wire cam_data_reset_val_1 = _T_121 & cam_raw_1_valid; // @[dec_decode_ctl.scala 292:88] - wire cam_1_valid = cam_data_reset_val_1 ? 1'h0 : cam_raw_1_valid; // @[dec_decode_ctl.scala 296:39] - wire _T_54 = ~cam_1_valid; // @[dec_decode_ctl.scala 273:78] - wire _T_57 = cam_0_valid & _T_54; // @[dec_decode_ctl.scala 273:126] - wire [1:0] _T_59 = {io_dctl_busbuff_lsu_nonblock_load_valid_m, 1'h0}; // @[dec_decode_ctl.scala 273:158] - reg [2:0] cam_raw_2_bits_tag; // @[dec_decode_ctl.scala 317:47] - wire _T_146 = _GEN_123 == cam_raw_2_bits_tag; // @[dec_decode_ctl.scala 292:67] - wire _T_147 = cam_data_reset & _T_146; // @[dec_decode_ctl.scala 292:45] - reg cam_raw_2_valid; // @[dec_decode_ctl.scala 317:47] - wire cam_data_reset_val_2 = _T_147 & cam_raw_2_valid; // @[dec_decode_ctl.scala 292:88] - wire cam_2_valid = cam_data_reset_val_2 ? 1'h0 : cam_raw_2_valid; // @[dec_decode_ctl.scala 296:39] - wire _T_60 = ~cam_2_valid; // @[dec_decode_ctl.scala 273:78] - wire _T_63 = cam_0_valid & cam_1_valid; // @[dec_decode_ctl.scala 273:126] - wire _T_66 = _T_63 & _T_60; // @[dec_decode_ctl.scala 273:126] - wire [2:0] _T_68 = {io_dctl_busbuff_lsu_nonblock_load_valid_m, 2'h0}; // @[dec_decode_ctl.scala 273:158] - reg [2:0] cam_raw_3_bits_tag; // @[dec_decode_ctl.scala 317:47] - wire _T_172 = _GEN_123 == cam_raw_3_bits_tag; // @[dec_decode_ctl.scala 292:67] - wire _T_173 = cam_data_reset & _T_172; // @[dec_decode_ctl.scala 292:45] - reg cam_raw_3_valid; // @[dec_decode_ctl.scala 317:47] - wire cam_data_reset_val_3 = _T_173 & cam_raw_3_valid; // @[dec_decode_ctl.scala 292:88] - wire cam_3_valid = cam_data_reset_val_3 ? 1'h0 : cam_raw_3_valid; // @[dec_decode_ctl.scala 296:39] - wire _T_69 = ~cam_3_valid; // @[dec_decode_ctl.scala 273:78] - wire _T_75 = _T_63 & cam_2_valid; // @[dec_decode_ctl.scala 273:126] - wire _T_78 = _T_75 & _T_69; // @[dec_decode_ctl.scala 273:126] - wire [3:0] _T_80 = {io_dctl_busbuff_lsu_nonblock_load_valid_m, 3'h0}; // @[dec_decode_ctl.scala 273:158] + wire _T_510 = postsync_stall & x_d_valid; // @[dec_decode_ctl.scala 534:96] + wire ps_stall_in = _T_509 | _T_510; // @[dec_decode_ctl.scala 534:77] + wire _T_12 = ps_stall_in ^ postsync_stall; // @[dec_decode_ctl.scala 184:54] + wire _T_13 = _T_11 | _T_12; // @[dec_decode_ctl.scala 183:89] + reg flush_final_r; // @[dec_decode_ctl.scala 580:52] + wire _T_14 = io_exu_flush_final ^ flush_final_r; // @[dec_decode_ctl.scala 185:54] + wire _T_15 = _T_13 | _T_14; // @[dec_decode_ctl.scala 184:89] + wire shift_illegal = io_dec_aln_dec_i0_decode_d & _T_507; // @[dec_decode_ctl.scala 498:55] + reg illegal_lockout; // @[dec_decode_ctl.scala 502:54] + wire _T_469 = shift_illegal | illegal_lockout; // @[dec_decode_ctl.scala 501:40] + wire _T_470 = ~flush_final_r; // @[dec_decode_ctl.scala 501:61] + wire illegal_lockout_in = _T_469 & _T_470; // @[dec_decode_ctl.scala 501:59] + wire _T_16 = illegal_lockout_in ^ illegal_lockout; // @[dec_decode_ctl.scala 186:54] + wire i0_legal_decode_d = io_dec_aln_dec_i0_decode_d & i0_legal; // @[dec_decode_ctl.scala 608:54] + wire _T_33 = i0_br_error & i0_legal_decode_d; // @[dec_decode_ctl.scala 209:72] + wire _T_36 = io_dec_i0_brp_bits_br_start_error & i0_legal_decode_d; // @[dec_decode_ctl.scala 210:94] + wire i0_dp_raw_pm_alu = i0_dec_io_out_pm_alu; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] + wire i0_dp_pm_alu = _T_41 ? 1'h0 : i0_dp_raw_pm_alu; // @[dec_decode_ctl.scala 225:50] + wire i0_dp_raw_fence_i = i0_dec_io_out_fence_i; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] + wire i0_dp_fence_i = _T_41 ? 1'h0 : i0_dp_raw_fence_i; // @[dec_decode_ctl.scala 225:50] + wire i0_dp_raw_fence = i0_dec_io_out_fence; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] + wire i0_dp_fence = _T_41 ? 1'h0 : i0_dp_raw_fence; // @[dec_decode_ctl.scala 225:50] + wire i0_dp_raw_rem = i0_dec_io_out_rem; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] + wire i0_dp_raw_div = i0_dec_io_out_div; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] + wire i0_dp_div = _T_41 ? 1'h0 : i0_dp_raw_div; // @[dec_decode_ctl.scala 225:50] + wire i0_dp_raw_low = i0_dec_io_out_low; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] + wire i0_dp_raw_rs2_sign = i0_dec_io_out_rs2_sign; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] + wire i0_dp_raw_rs1_sign = i0_dec_io_out_rs1_sign; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] + wire i0_dp_raw_mul = i0_dec_io_out_mul; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] + wire i0_dp_mul = _T_41 ? 1'h0 : i0_dp_raw_mul; // @[dec_decode_ctl.scala 225:50] + wire i0_dp_raw_mret = i0_dec_io_out_mret; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] + wire i0_dp_mret = _T_41 ? 1'h0 : i0_dp_raw_mret; // @[dec_decode_ctl.scala 225:50] + wire i0_dp_raw_ecall = i0_dec_io_out_ecall; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] + wire i0_dp_ecall = _T_41 ? 1'h0 : i0_dp_raw_ecall; // @[dec_decode_ctl.scala 225:50] + wire i0_dp_raw_ebreak = i0_dec_io_out_ebreak; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] + wire i0_dp_ebreak = _T_41 ? 1'h0 : i0_dp_raw_ebreak; // @[dec_decode_ctl.scala 225:50] + wire i0_dp_raw_presync = i0_dec_io_out_presync; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] + wire i0_dp_presync = _T_41 ? 1'h0 : i0_dp_raw_presync; // @[dec_decode_ctl.scala 225:50] + wire i0_dp_raw_csr_imm = i0_dec_io_out_csr_imm; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] + wire i0_dp_csr_imm = _T_41 ? 1'h0 : i0_dp_raw_csr_imm; // @[dec_decode_ctl.scala 225:50] + wire i0_dp_raw_csr_set = i0_dec_io_out_csr_set; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] + wire i0_dp_csr_set = _T_41 ? 1'h0 : i0_dp_raw_csr_set; // @[dec_decode_ctl.scala 225:50] + wire i0_dp_raw_csr_clr = i0_dec_io_out_csr_clr; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] + wire i0_dp_csr_clr = _T_41 ? 1'h0 : i0_dp_raw_csr_clr; // @[dec_decode_ctl.scala 225:50] + wire i0_dp_raw_word = i0_dec_io_out_word; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] + wire i0_dp_word = _T_41 ? 1'h0 : i0_dp_raw_word; // @[dec_decode_ctl.scala 225:50] + wire i0_dp_raw_half = i0_dec_io_out_half; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] + wire i0_dp_half = _T_41 ? 1'h0 : i0_dp_raw_half; // @[dec_decode_ctl.scala 225:50] + wire i0_dp_raw_by = i0_dec_io_out_by; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] + wire i0_dp_by = _T_41 ? 1'h0 : i0_dp_raw_by; // @[dec_decode_ctl.scala 225:50] + wire i0_dp_jal = _T_41 ? 1'h0 : i0_dp_raw_jal; // @[dec_decode_ctl.scala 225:50] + wire i0_dp_raw_blt = i0_dec_io_out_blt; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] + wire i0_dp_raw_bge = i0_dec_io_out_bge; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] + wire i0_dp_raw_bne = i0_dec_io_out_bne; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] + wire i0_dp_raw_beq = i0_dec_io_out_beq; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] + wire i0_dp_condbr = _T_41 ? 1'h0 : i0_dp_raw_condbr; // @[dec_decode_ctl.scala 225:50] + wire i0_dp_raw_unsign = i0_dec_io_out_unsign; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] + wire i0_dp_unsign = _T_41 ? 1'h0 : i0_dp_raw_unsign; // @[dec_decode_ctl.scala 225:50] + wire i0_dp_raw_slt = i0_dec_io_out_slt; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] + wire i0_dp_raw_srl = i0_dec_io_out_srl; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] + wire i0_dp_raw_sra = i0_dec_io_out_sra; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] + wire i0_dp_raw_sll = i0_dec_io_out_sll; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] + wire i0_dp_raw_lxor = i0_dec_io_out_lxor; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] + wire i0_dp_raw_lor = i0_dec_io_out_lor; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] + wire i0_dp_raw_land = i0_dec_io_out_land; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] + wire i0_dp_raw_sub = i0_dec_io_out_sub; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] + wire i0_dp_raw_add = i0_dec_io_out_add; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] + wire i0_dp_raw_lsu = i0_dec_io_out_lsu; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] + wire i0_dp_lsu = _T_41 ? 1'h0 : i0_dp_raw_lsu; // @[dec_decode_ctl.scala 225:50] + wire i0_dp_raw_store = i0_dec_io_out_store; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] + wire i0_dp_store = _T_41 ? 1'h0 : i0_dp_raw_store; // @[dec_decode_ctl.scala 225:50] + wire i0_dp_raw_load = i0_dec_io_out_load; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] + wire i0_dp_load = _T_41 ? 1'h0 : i0_dp_raw_load; // @[dec_decode_ctl.scala 225:50] + wire i0_dp_raw_pc = i0_dec_io_out_pc; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] + wire i0_dp_imm20 = _T_41 ? 1'h0 : i0_dp_raw_imm20; // @[dec_decode_ctl.scala 225:50] + wire i0_dp_raw_shimm5 = i0_dec_io_out_shimm5; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] + wire i0_dp_shimm5 = _T_41 ? 1'h0 : i0_dp_raw_shimm5; // @[dec_decode_ctl.scala 225:50] + wire i0_dp_raw_rd = i0_dec_io_out_rd; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] + wire i0_dp_rd = _T_41 ? 1'h0 : i0_dp_raw_rd; // @[dec_decode_ctl.scala 225:50] + wire i0_dp_imm12 = _T_41 ? 1'h0 : i0_dp_raw_imm12; // @[dec_decode_ctl.scala 225:50] + wire i0_dp_raw_rs2 = i0_dec_io_out_rs2; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] + wire i0_dp_rs2 = _T_41 | i0_dp_raw_rs2; // @[dec_decode_ctl.scala 225:50] + wire i0_dp_raw_rs1 = i0_dec_io_out_rs1; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] + wire i0_dp_rs1 = _T_41 | i0_dp_raw_rs1; // @[dec_decode_ctl.scala 225:50] + wire i0_dp_raw_alu = i0_dec_io_out_alu; // @[dec_decode_ctl.scala 124:37 dec_decode_ctl.scala 358:12] + wire i0_dp_alu = _T_41 | i0_dp_raw_alu; // @[dec_decode_ctl.scala 225:50] + wire i0_pcall = i0_dp_jal & i0_pcall_case; // @[dec_decode_ctl.scala 376:38] + wire _T_44 = i0_dp_condbr | i0_pcall; // @[dec_decode_ctl.scala 239:54] + wire i0_pja = i0_dp_jal & i0_pja_case; // @[dec_decode_ctl.scala 378:38] + wire _T_45 = _T_44 | i0_pja; // @[dec_decode_ctl.scala 239:65] + wire i0_pret = i0_dp_jal & i0_pret_case; // @[dec_decode_ctl.scala 383:32] + wire i0_predict_br = _T_45 | i0_pret; // @[dec_decode_ctl.scala 239:74] + wire _T_47 = io_dec_i0_brp_bits_hist[1] & i0_brp_valid; // @[dec_decode_ctl.scala 240:69] + wire _T_48 = ~_T_47; // @[dec_decode_ctl.scala 240:40] + wire i0_ap_pc2 = ~io_dec_i0_pc4_d; // @[dec_decode_ctl.scala 242:40] + wire cam_data_reset = io_dctl_busbuff_lsu_nonblock_load_data_valid | io_dctl_busbuff_lsu_nonblock_load_data_error; // @[dec_decode_ctl.scala 275:76] + reg [2:0] cam_raw_0_bits_tag; // @[dec_decode_ctl.scala 311:47] + wire [2:0] _GEN_123 = {{1'd0}, io_dctl_busbuff_lsu_nonblock_load_data_tag}; // @[dec_decode_ctl.scala 286:67] + wire _T_94 = _GEN_123 == cam_raw_0_bits_tag; // @[dec_decode_ctl.scala 286:67] + wire _T_95 = cam_data_reset & _T_94; // @[dec_decode_ctl.scala 286:45] + reg cam_raw_0_valid; // @[dec_decode_ctl.scala 311:47] + wire cam_data_reset_val_0 = _T_95 & cam_raw_0_valid; // @[dec_decode_ctl.scala 286:88] + wire cam_0_valid = cam_data_reset_val_0 ? 1'h0 : cam_raw_0_valid; // @[dec_decode_ctl.scala 290:39] + wire _T_51 = ~cam_0_valid; // @[dec_decode_ctl.scala 267:78] + reg [2:0] cam_raw_1_bits_tag; // @[dec_decode_ctl.scala 311:47] + wire _T_120 = _GEN_123 == cam_raw_1_bits_tag; // @[dec_decode_ctl.scala 286:67] + wire _T_121 = cam_data_reset & _T_120; // @[dec_decode_ctl.scala 286:45] + reg cam_raw_1_valid; // @[dec_decode_ctl.scala 311:47] + wire cam_data_reset_val_1 = _T_121 & cam_raw_1_valid; // @[dec_decode_ctl.scala 286:88] + wire cam_1_valid = cam_data_reset_val_1 ? 1'h0 : cam_raw_1_valid; // @[dec_decode_ctl.scala 290:39] + wire _T_54 = ~cam_1_valid; // @[dec_decode_ctl.scala 267:78] + wire _T_57 = cam_0_valid & _T_54; // @[dec_decode_ctl.scala 267:126] + wire [1:0] _T_59 = {io_dctl_busbuff_lsu_nonblock_load_valid_m, 1'h0}; // @[dec_decode_ctl.scala 267:158] + reg [2:0] cam_raw_2_bits_tag; // @[dec_decode_ctl.scala 311:47] + wire _T_146 = _GEN_123 == cam_raw_2_bits_tag; // @[dec_decode_ctl.scala 286:67] + wire _T_147 = cam_data_reset & _T_146; // @[dec_decode_ctl.scala 286:45] + reg cam_raw_2_valid; // @[dec_decode_ctl.scala 311:47] + wire cam_data_reset_val_2 = _T_147 & cam_raw_2_valid; // @[dec_decode_ctl.scala 286:88] + wire cam_2_valid = cam_data_reset_val_2 ? 1'h0 : cam_raw_2_valid; // @[dec_decode_ctl.scala 290:39] + wire _T_60 = ~cam_2_valid; // @[dec_decode_ctl.scala 267:78] + wire _T_63 = cam_0_valid & cam_1_valid; // @[dec_decode_ctl.scala 267:126] + wire _T_66 = _T_63 & _T_60; // @[dec_decode_ctl.scala 267:126] + wire [2:0] _T_68 = {io_dctl_busbuff_lsu_nonblock_load_valid_m, 2'h0}; // @[dec_decode_ctl.scala 267:158] + reg [2:0] cam_raw_3_bits_tag; // @[dec_decode_ctl.scala 311:47] + wire _T_172 = _GEN_123 == cam_raw_3_bits_tag; // @[dec_decode_ctl.scala 286:67] + wire _T_173 = cam_data_reset & _T_172; // @[dec_decode_ctl.scala 286:45] + reg cam_raw_3_valid; // @[dec_decode_ctl.scala 311:47] + wire cam_data_reset_val_3 = _T_173 & cam_raw_3_valid; // @[dec_decode_ctl.scala 286:88] + wire cam_3_valid = cam_data_reset_val_3 ? 1'h0 : cam_raw_3_valid; // @[dec_decode_ctl.scala 290:39] + wire _T_69 = ~cam_3_valid; // @[dec_decode_ctl.scala 267:78] + wire _T_75 = _T_63 & cam_2_valid; // @[dec_decode_ctl.scala 267:126] + wire _T_78 = _T_75 & _T_69; // @[dec_decode_ctl.scala 267:126] + wire [3:0] _T_80 = {io_dctl_busbuff_lsu_nonblock_load_valid_m, 3'h0}; // @[dec_decode_ctl.scala 267:158] wire _T_81 = _T_51 & io_dctl_busbuff_lsu_nonblock_load_valid_m; // @[Mux.scala 27:72] wire [1:0] _T_82 = _T_57 ? _T_59 : 2'h0; // @[Mux.scala 27:72] wire [2:0] _T_83 = _T_66 ? _T_68 : 3'h0; // @[Mux.scala 27:72] @@ -46629,150 +46629,150 @@ module dec_decode_ctl( wire [3:0] cam_wen = _GEN_129 | _T_84; // @[Mux.scala 27:72] reg x_d_bits_i0load; // @[lib.scala 384:16] reg [4:0] x_d_bits_i0rd; // @[lib.scala 384:16] - wire [4:0] nonblock_load_rd = x_d_bits_i0load ? x_d_bits_i0rd : 5'h0; // @[dec_decode_ctl.scala 284:31] - reg [2:0] _T_704; // @[dec_decode_ctl.scala 622:80] - wire [3:0] i0_pipe_en = {io_dec_aln_dec_i0_decode_d,_T_704}; // @[Cat.scala 29:58] - wire _T_710 = |i0_pipe_en[2:1]; // @[dec_decode_ctl.scala 625:49] - wire i0_r_ctl_en = _T_710 | io_clk_override; // @[dec_decode_ctl.scala 625:53] + wire [4:0] nonblock_load_rd = x_d_bits_i0load ? x_d_bits_i0rd : 5'h0; // @[dec_decode_ctl.scala 278:31] + reg [2:0] _T_706; // @[dec_decode_ctl.scala 616:80] + wire [3:0] i0_pipe_en = {io_dec_aln_dec_i0_decode_d,_T_706}; // @[Cat.scala 29:58] + wire _T_712 = |i0_pipe_en[2:1]; // @[dec_decode_ctl.scala 619:49] + wire i0_r_ctl_en = _T_712 | io_clk_override; // @[dec_decode_ctl.scala 619:53] reg nonblock_load_valid_m_delay; // @[Reg.scala 27:20] reg r_d_bits_i0load; // @[lib.scala 384:16] - wire i0_load_kill_wen_r = nonblock_load_valid_m_delay & r_d_bits_i0load; // @[dec_decode_ctl.scala 289:56] - wire [2:0] _GEN_130 = {{1'd0}, io_dctl_busbuff_lsu_nonblock_load_inv_tag_r}; // @[dec_decode_ctl.scala 291:66] - wire _T_91 = _GEN_130 == cam_raw_0_bits_tag; // @[dec_decode_ctl.scala 291:66] - wire _T_92 = io_dctl_busbuff_lsu_nonblock_load_inv_r & _T_91; // @[dec_decode_ctl.scala 291:45] - wire cam_inv_reset_val_0 = _T_92 & cam_0_valid; // @[dec_decode_ctl.scala 291:87] + wire i0_load_kill_wen_r = nonblock_load_valid_m_delay & r_d_bits_i0load; // @[dec_decode_ctl.scala 283:56] + wire [2:0] _GEN_130 = {{1'd0}, io_dctl_busbuff_lsu_nonblock_load_inv_tag_r}; // @[dec_decode_ctl.scala 285:66] + wire _T_91 = _GEN_130 == cam_raw_0_bits_tag; // @[dec_decode_ctl.scala 285:66] + wire _T_92 = io_dctl_busbuff_lsu_nonblock_load_inv_r & _T_91; // @[dec_decode_ctl.scala 285:45] + wire cam_inv_reset_val_0 = _T_92 & cam_0_valid; // @[dec_decode_ctl.scala 285:87] reg r_d_bits_i0v; // @[lib.scala 384:16] - wire _T_746 = ~io_dec_tlu_flush_lower_wb; // @[dec_decode_ctl.scala 657:51] - wire r_d_in_bits_i0v = r_d_bits_i0v & _T_746; // @[dec_decode_ctl.scala 657:49] - wire _T_757 = ~io_dec_tlu_i0_kill_writeb_r; // @[dec_decode_ctl.scala 665:47] - wire i0_wen_r = r_d_in_bits_i0v & _T_757; // @[dec_decode_ctl.scala 665:45] + wire _T_748 = ~io_dec_tlu_flush_lower_wb; // @[dec_decode_ctl.scala 651:51] + wire r_d_in_bits_i0v = r_d_bits_i0v & _T_748; // @[dec_decode_ctl.scala 651:49] + wire _T_759 = ~io_dec_tlu_i0_kill_writeb_r; // @[dec_decode_ctl.scala 659:47] + wire i0_wen_r = r_d_in_bits_i0v & _T_759; // @[dec_decode_ctl.scala 659:45] reg [4:0] r_d_bits_i0rd; // @[lib.scala 384:16] - reg [4:0] cam_raw_0_bits_rd; // @[dec_decode_ctl.scala 317:47] - wire _T_103 = r_d_bits_i0rd == cam_raw_0_bits_rd; // @[dec_decode_ctl.scala 304:85] - wire _T_104 = i0_wen_r & _T_103; // @[dec_decode_ctl.scala 304:64] - reg cam_raw_0_bits_wb; // @[dec_decode_ctl.scala 317:47] - wire _T_106 = _T_104 & cam_raw_0_bits_wb; // @[dec_decode_ctl.scala 304:105] - wire _T_107 = cam_inv_reset_val_0 | _T_106; // @[dec_decode_ctl.scala 304:44] - wire _GEN_52 = _T_107 ? 1'h0 : cam_0_valid; // @[dec_decode_ctl.scala 304:131] - wire _GEN_55 = _T_107 ? 1'h0 : cam_raw_0_bits_wb; // @[dec_decode_ctl.scala 304:131] - wire _GEN_56 = cam_wen[0] | _GEN_52; // @[dec_decode_ctl.scala 299:28] - wire _GEN_57 = cam_wen[0] ? 1'h0 : _GEN_55; // @[dec_decode_ctl.scala 299:28] - wire _T_110 = nonblock_load_valid_m_delay & _T_91; // @[dec_decode_ctl.scala 309:44] - wire _T_112 = _T_110 & cam_0_valid; // @[dec_decode_ctl.scala 309:113] - wire nonblock_load_write_0 = _T_94 & cam_raw_0_valid; // @[dec_decode_ctl.scala 318:71] - wire _T_117 = _GEN_130 == cam_raw_1_bits_tag; // @[dec_decode_ctl.scala 291:66] - wire _T_118 = io_dctl_busbuff_lsu_nonblock_load_inv_r & _T_117; // @[dec_decode_ctl.scala 291:45] - wire cam_inv_reset_val_1 = _T_118 & cam_1_valid; // @[dec_decode_ctl.scala 291:87] - reg [4:0] cam_raw_1_bits_rd; // @[dec_decode_ctl.scala 317:47] - wire _T_129 = r_d_bits_i0rd == cam_raw_1_bits_rd; // @[dec_decode_ctl.scala 304:85] - wire _T_130 = i0_wen_r & _T_129; // @[dec_decode_ctl.scala 304:64] - reg cam_raw_1_bits_wb; // @[dec_decode_ctl.scala 317:47] - wire _T_132 = _T_130 & cam_raw_1_bits_wb; // @[dec_decode_ctl.scala 304:105] - wire _T_133 = cam_inv_reset_val_1 | _T_132; // @[dec_decode_ctl.scala 304:44] - wire _GEN_63 = _T_133 ? 1'h0 : cam_1_valid; // @[dec_decode_ctl.scala 304:131] - wire _GEN_66 = _T_133 ? 1'h0 : cam_raw_1_bits_wb; // @[dec_decode_ctl.scala 304:131] - wire _GEN_67 = cam_wen[1] | _GEN_63; // @[dec_decode_ctl.scala 299:28] - wire _GEN_68 = cam_wen[1] ? 1'h0 : _GEN_66; // @[dec_decode_ctl.scala 299:28] - wire _T_136 = nonblock_load_valid_m_delay & _T_117; // @[dec_decode_ctl.scala 309:44] - wire _T_138 = _T_136 & cam_1_valid; // @[dec_decode_ctl.scala 309:113] - wire nonblock_load_write_1 = _T_120 & cam_raw_1_valid; // @[dec_decode_ctl.scala 318:71] - wire _T_143 = _GEN_130 == cam_raw_2_bits_tag; // @[dec_decode_ctl.scala 291:66] - wire _T_144 = io_dctl_busbuff_lsu_nonblock_load_inv_r & _T_143; // @[dec_decode_ctl.scala 291:45] - wire cam_inv_reset_val_2 = _T_144 & cam_2_valid; // @[dec_decode_ctl.scala 291:87] - reg [4:0] cam_raw_2_bits_rd; // @[dec_decode_ctl.scala 317:47] - wire _T_155 = r_d_bits_i0rd == cam_raw_2_bits_rd; // @[dec_decode_ctl.scala 304:85] - wire _T_156 = i0_wen_r & _T_155; // @[dec_decode_ctl.scala 304:64] - reg cam_raw_2_bits_wb; // @[dec_decode_ctl.scala 317:47] - wire _T_158 = _T_156 & cam_raw_2_bits_wb; // @[dec_decode_ctl.scala 304:105] - wire _T_159 = cam_inv_reset_val_2 | _T_158; // @[dec_decode_ctl.scala 304:44] - wire _GEN_74 = _T_159 ? 1'h0 : cam_2_valid; // @[dec_decode_ctl.scala 304:131] - wire _GEN_77 = _T_159 ? 1'h0 : cam_raw_2_bits_wb; // @[dec_decode_ctl.scala 304:131] - wire _GEN_78 = cam_wen[2] | _GEN_74; // @[dec_decode_ctl.scala 299:28] - wire _GEN_79 = cam_wen[2] ? 1'h0 : _GEN_77; // @[dec_decode_ctl.scala 299:28] - wire _T_162 = nonblock_load_valid_m_delay & _T_143; // @[dec_decode_ctl.scala 309:44] - wire _T_164 = _T_162 & cam_2_valid; // @[dec_decode_ctl.scala 309:113] - wire nonblock_load_write_2 = _T_146 & cam_raw_2_valid; // @[dec_decode_ctl.scala 318:71] - wire _T_169 = _GEN_130 == cam_raw_3_bits_tag; // @[dec_decode_ctl.scala 291:66] - wire _T_170 = io_dctl_busbuff_lsu_nonblock_load_inv_r & _T_169; // @[dec_decode_ctl.scala 291:45] - wire cam_inv_reset_val_3 = _T_170 & cam_3_valid; // @[dec_decode_ctl.scala 291:87] - reg [4:0] cam_raw_3_bits_rd; // @[dec_decode_ctl.scala 317:47] - wire _T_181 = r_d_bits_i0rd == cam_raw_3_bits_rd; // @[dec_decode_ctl.scala 304:85] - wire _T_182 = i0_wen_r & _T_181; // @[dec_decode_ctl.scala 304:64] - reg cam_raw_3_bits_wb; // @[dec_decode_ctl.scala 317:47] - wire _T_184 = _T_182 & cam_raw_3_bits_wb; // @[dec_decode_ctl.scala 304:105] - wire _T_185 = cam_inv_reset_val_3 | _T_184; // @[dec_decode_ctl.scala 304:44] - wire _GEN_85 = _T_185 ? 1'h0 : cam_3_valid; // @[dec_decode_ctl.scala 304:131] - wire _GEN_88 = _T_185 ? 1'h0 : cam_raw_3_bits_wb; // @[dec_decode_ctl.scala 304:131] - wire _GEN_89 = cam_wen[3] | _GEN_85; // @[dec_decode_ctl.scala 299:28] - wire _GEN_90 = cam_wen[3] ? 1'h0 : _GEN_88; // @[dec_decode_ctl.scala 299:28] - wire _T_188 = nonblock_load_valid_m_delay & _T_169; // @[dec_decode_ctl.scala 309:44] - wire _T_190 = _T_188 & cam_3_valid; // @[dec_decode_ctl.scala 309:113] - wire nonblock_load_write_3 = _T_172 & cam_raw_3_valid; // @[dec_decode_ctl.scala 318:71] - wire _T_195 = r_d_bits_i0rd == io_dec_nonblock_load_waddr; // @[dec_decode_ctl.scala 323:49] - wire nonblock_load_cancel = _T_195 & i0_wen_r; // @[dec_decode_ctl.scala 323:81] - wire _T_196 = nonblock_load_write_0 | nonblock_load_write_1; // @[dec_decode_ctl.scala 324:108] - wire _T_197 = _T_196 | nonblock_load_write_2; // @[dec_decode_ctl.scala 324:108] - wire _T_198 = _T_197 | nonblock_load_write_3; // @[dec_decode_ctl.scala 324:108] - wire _T_200 = io_dctl_busbuff_lsu_nonblock_load_data_valid & _T_198; // @[dec_decode_ctl.scala 324:77] - wire _T_201 = ~nonblock_load_cancel; // @[dec_decode_ctl.scala 324:122] - wire _T_203 = nonblock_load_rd == i0r_rs1; // @[dec_decode_ctl.scala 325:54] - wire _T_204 = _T_203 & io_dctl_busbuff_lsu_nonblock_load_valid_m; // @[dec_decode_ctl.scala 325:66] - wire _T_205 = _T_204 & io_decode_exu_dec_i0_rs1_en_d; // @[dec_decode_ctl.scala 325:110] - wire [4:0] i0r_rs2 = io_dec_i0_instr_d[24:20]; // @[dec_decode_ctl.scala 591:16] - wire _T_206 = nonblock_load_rd == i0r_rs2; // @[dec_decode_ctl.scala 325:161] - wire _T_207 = _T_206 & io_dctl_busbuff_lsu_nonblock_load_valid_m; // @[dec_decode_ctl.scala 325:173] - wire _T_208 = _T_207 & io_decode_exu_dec_i0_rs2_en_d; // @[dec_decode_ctl.scala 325:217] - wire i0_nonblock_boundary_stall = _T_205 | _T_208; // @[dec_decode_ctl.scala 325:142] + reg [4:0] cam_raw_0_bits_rd; // @[dec_decode_ctl.scala 311:47] + wire _T_103 = r_d_bits_i0rd == cam_raw_0_bits_rd; // @[dec_decode_ctl.scala 298:85] + wire _T_104 = i0_wen_r & _T_103; // @[dec_decode_ctl.scala 298:64] + reg cam_raw_0_bits_wb; // @[dec_decode_ctl.scala 311:47] + wire _T_106 = _T_104 & cam_raw_0_bits_wb; // @[dec_decode_ctl.scala 298:105] + wire _T_107 = cam_inv_reset_val_0 | _T_106; // @[dec_decode_ctl.scala 298:44] + wire _GEN_52 = _T_107 ? 1'h0 : cam_0_valid; // @[dec_decode_ctl.scala 298:131] + wire _GEN_55 = _T_107 ? 1'h0 : cam_raw_0_bits_wb; // @[dec_decode_ctl.scala 298:131] + wire _GEN_56 = cam_wen[0] | _GEN_52; // @[dec_decode_ctl.scala 293:28] + wire _GEN_57 = cam_wen[0] ? 1'h0 : _GEN_55; // @[dec_decode_ctl.scala 293:28] + wire _T_110 = nonblock_load_valid_m_delay & _T_91; // @[dec_decode_ctl.scala 303:44] + wire _T_112 = _T_110 & cam_0_valid; // @[dec_decode_ctl.scala 303:113] + wire nonblock_load_write_0 = _T_94 & cam_raw_0_valid; // @[dec_decode_ctl.scala 312:71] + wire _T_117 = _GEN_130 == cam_raw_1_bits_tag; // @[dec_decode_ctl.scala 285:66] + wire _T_118 = io_dctl_busbuff_lsu_nonblock_load_inv_r & _T_117; // @[dec_decode_ctl.scala 285:45] + wire cam_inv_reset_val_1 = _T_118 & cam_1_valid; // @[dec_decode_ctl.scala 285:87] + reg [4:0] cam_raw_1_bits_rd; // @[dec_decode_ctl.scala 311:47] + wire _T_129 = r_d_bits_i0rd == cam_raw_1_bits_rd; // @[dec_decode_ctl.scala 298:85] + wire _T_130 = i0_wen_r & _T_129; // @[dec_decode_ctl.scala 298:64] + reg cam_raw_1_bits_wb; // @[dec_decode_ctl.scala 311:47] + wire _T_132 = _T_130 & cam_raw_1_bits_wb; // @[dec_decode_ctl.scala 298:105] + wire _T_133 = cam_inv_reset_val_1 | _T_132; // @[dec_decode_ctl.scala 298:44] + wire _GEN_63 = _T_133 ? 1'h0 : cam_1_valid; // @[dec_decode_ctl.scala 298:131] + wire _GEN_66 = _T_133 ? 1'h0 : cam_raw_1_bits_wb; // @[dec_decode_ctl.scala 298:131] + wire _GEN_67 = cam_wen[1] | _GEN_63; // @[dec_decode_ctl.scala 293:28] + wire _GEN_68 = cam_wen[1] ? 1'h0 : _GEN_66; // @[dec_decode_ctl.scala 293:28] + wire _T_136 = nonblock_load_valid_m_delay & _T_117; // @[dec_decode_ctl.scala 303:44] + wire _T_138 = _T_136 & cam_1_valid; // @[dec_decode_ctl.scala 303:113] + wire nonblock_load_write_1 = _T_120 & cam_raw_1_valid; // @[dec_decode_ctl.scala 312:71] + wire _T_143 = _GEN_130 == cam_raw_2_bits_tag; // @[dec_decode_ctl.scala 285:66] + wire _T_144 = io_dctl_busbuff_lsu_nonblock_load_inv_r & _T_143; // @[dec_decode_ctl.scala 285:45] + wire cam_inv_reset_val_2 = _T_144 & cam_2_valid; // @[dec_decode_ctl.scala 285:87] + reg [4:0] cam_raw_2_bits_rd; // @[dec_decode_ctl.scala 311:47] + wire _T_155 = r_d_bits_i0rd == cam_raw_2_bits_rd; // @[dec_decode_ctl.scala 298:85] + wire _T_156 = i0_wen_r & _T_155; // @[dec_decode_ctl.scala 298:64] + reg cam_raw_2_bits_wb; // @[dec_decode_ctl.scala 311:47] + wire _T_158 = _T_156 & cam_raw_2_bits_wb; // @[dec_decode_ctl.scala 298:105] + wire _T_159 = cam_inv_reset_val_2 | _T_158; // @[dec_decode_ctl.scala 298:44] + wire _GEN_74 = _T_159 ? 1'h0 : cam_2_valid; // @[dec_decode_ctl.scala 298:131] + wire _GEN_77 = _T_159 ? 1'h0 : cam_raw_2_bits_wb; // @[dec_decode_ctl.scala 298:131] + wire _GEN_78 = cam_wen[2] | _GEN_74; // @[dec_decode_ctl.scala 293:28] + wire _GEN_79 = cam_wen[2] ? 1'h0 : _GEN_77; // @[dec_decode_ctl.scala 293:28] + wire _T_162 = nonblock_load_valid_m_delay & _T_143; // @[dec_decode_ctl.scala 303:44] + wire _T_164 = _T_162 & cam_2_valid; // @[dec_decode_ctl.scala 303:113] + wire nonblock_load_write_2 = _T_146 & cam_raw_2_valid; // @[dec_decode_ctl.scala 312:71] + wire _T_169 = _GEN_130 == cam_raw_3_bits_tag; // @[dec_decode_ctl.scala 285:66] + wire _T_170 = io_dctl_busbuff_lsu_nonblock_load_inv_r & _T_169; // @[dec_decode_ctl.scala 285:45] + wire cam_inv_reset_val_3 = _T_170 & cam_3_valid; // @[dec_decode_ctl.scala 285:87] + reg [4:0] cam_raw_3_bits_rd; // @[dec_decode_ctl.scala 311:47] + wire _T_181 = r_d_bits_i0rd == cam_raw_3_bits_rd; // @[dec_decode_ctl.scala 298:85] + wire _T_182 = i0_wen_r & _T_181; // @[dec_decode_ctl.scala 298:64] + reg cam_raw_3_bits_wb; // @[dec_decode_ctl.scala 311:47] + wire _T_184 = _T_182 & cam_raw_3_bits_wb; // @[dec_decode_ctl.scala 298:105] + wire _T_185 = cam_inv_reset_val_3 | _T_184; // @[dec_decode_ctl.scala 298:44] + wire _GEN_85 = _T_185 ? 1'h0 : cam_3_valid; // @[dec_decode_ctl.scala 298:131] + wire _GEN_88 = _T_185 ? 1'h0 : cam_raw_3_bits_wb; // @[dec_decode_ctl.scala 298:131] + wire _GEN_89 = cam_wen[3] | _GEN_85; // @[dec_decode_ctl.scala 293:28] + wire _GEN_90 = cam_wen[3] ? 1'h0 : _GEN_88; // @[dec_decode_ctl.scala 293:28] + wire _T_188 = nonblock_load_valid_m_delay & _T_169; // @[dec_decode_ctl.scala 303:44] + wire _T_190 = _T_188 & cam_3_valid; // @[dec_decode_ctl.scala 303:113] + wire nonblock_load_write_3 = _T_172 & cam_raw_3_valid; // @[dec_decode_ctl.scala 312:71] + wire _T_195 = r_d_bits_i0rd == io_dec_nonblock_load_waddr; // @[dec_decode_ctl.scala 317:49] + wire nonblock_load_cancel = _T_195 & i0_wen_r; // @[dec_decode_ctl.scala 317:81] + wire _T_196 = nonblock_load_write_0 | nonblock_load_write_1; // @[dec_decode_ctl.scala 318:108] + wire _T_197 = _T_196 | nonblock_load_write_2; // @[dec_decode_ctl.scala 318:108] + wire _T_198 = _T_197 | nonblock_load_write_3; // @[dec_decode_ctl.scala 318:108] + wire _T_200 = io_dctl_busbuff_lsu_nonblock_load_data_valid & _T_198; // @[dec_decode_ctl.scala 318:77] + wire _T_201 = ~nonblock_load_cancel; // @[dec_decode_ctl.scala 318:122] + wire _T_203 = nonblock_load_rd == i0r_rs1; // @[dec_decode_ctl.scala 319:54] + wire _T_204 = _T_203 & io_dctl_busbuff_lsu_nonblock_load_valid_m; // @[dec_decode_ctl.scala 319:66] + wire _T_205 = _T_204 & io_decode_exu_dec_i0_rs1_en_d; // @[dec_decode_ctl.scala 319:110] + wire [4:0] i0r_rs2 = io_dec_i0_instr_d[24:20]; // @[dec_decode_ctl.scala 585:16] + wire _T_206 = nonblock_load_rd == i0r_rs2; // @[dec_decode_ctl.scala 319:161] + wire _T_207 = _T_206 & io_dctl_busbuff_lsu_nonblock_load_valid_m; // @[dec_decode_ctl.scala 319:173] + wire _T_208 = _T_207 & io_decode_exu_dec_i0_rs2_en_d; // @[dec_decode_ctl.scala 319:217] + wire i0_nonblock_boundary_stall = _T_205 | _T_208; // @[dec_decode_ctl.scala 319:142] wire [4:0] _T_210 = nonblock_load_write_0 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12] - wire [4:0] _T_211 = _T_210 & cam_raw_0_bits_rd; // @[dec_decode_ctl.scala 329:88] - wire _T_212 = io_decode_exu_dec_i0_rs1_en_d & cam_0_valid; // @[dec_decode_ctl.scala 329:137] - wire _T_213 = cam_raw_0_bits_rd == i0r_rs1; // @[dec_decode_ctl.scala 329:170] - wire _T_214 = _T_212 & _T_213; // @[dec_decode_ctl.scala 329:152] - wire _T_215 = io_decode_exu_dec_i0_rs2_en_d & cam_0_valid; // @[dec_decode_ctl.scala 329:214] - wire _T_216 = cam_raw_0_bits_rd == i0r_rs2; // @[dec_decode_ctl.scala 329:247] - wire _T_217 = _T_215 & _T_216; // @[dec_decode_ctl.scala 329:229] + wire [4:0] _T_211 = _T_210 & cam_raw_0_bits_rd; // @[dec_decode_ctl.scala 323:88] + wire _T_212 = io_decode_exu_dec_i0_rs1_en_d & cam_0_valid; // @[dec_decode_ctl.scala 323:137] + wire _T_213 = cam_raw_0_bits_rd == i0r_rs1; // @[dec_decode_ctl.scala 323:170] + wire _T_214 = _T_212 & _T_213; // @[dec_decode_ctl.scala 323:152] + wire _T_215 = io_decode_exu_dec_i0_rs2_en_d & cam_0_valid; // @[dec_decode_ctl.scala 323:214] + wire _T_216 = cam_raw_0_bits_rd == i0r_rs2; // @[dec_decode_ctl.scala 323:247] + wire _T_217 = _T_215 & _T_216; // @[dec_decode_ctl.scala 323:229] wire [4:0] _T_219 = nonblock_load_write_1 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12] - wire [4:0] _T_220 = _T_219 & cam_raw_1_bits_rd; // @[dec_decode_ctl.scala 329:88] - wire _T_221 = io_decode_exu_dec_i0_rs1_en_d & cam_1_valid; // @[dec_decode_ctl.scala 329:137] - wire _T_222 = cam_raw_1_bits_rd == i0r_rs1; // @[dec_decode_ctl.scala 329:170] - wire _T_223 = _T_221 & _T_222; // @[dec_decode_ctl.scala 329:152] - wire _T_224 = io_decode_exu_dec_i0_rs2_en_d & cam_1_valid; // @[dec_decode_ctl.scala 329:214] - wire _T_225 = cam_raw_1_bits_rd == i0r_rs2; // @[dec_decode_ctl.scala 329:247] - wire _T_226 = _T_224 & _T_225; // @[dec_decode_ctl.scala 329:229] + wire [4:0] _T_220 = _T_219 & cam_raw_1_bits_rd; // @[dec_decode_ctl.scala 323:88] + wire _T_221 = io_decode_exu_dec_i0_rs1_en_d & cam_1_valid; // @[dec_decode_ctl.scala 323:137] + wire _T_222 = cam_raw_1_bits_rd == i0r_rs1; // @[dec_decode_ctl.scala 323:170] + wire _T_223 = _T_221 & _T_222; // @[dec_decode_ctl.scala 323:152] + wire _T_224 = io_decode_exu_dec_i0_rs2_en_d & cam_1_valid; // @[dec_decode_ctl.scala 323:214] + wire _T_225 = cam_raw_1_bits_rd == i0r_rs2; // @[dec_decode_ctl.scala 323:247] + wire _T_226 = _T_224 & _T_225; // @[dec_decode_ctl.scala 323:229] wire [4:0] _T_228 = nonblock_load_write_2 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12] - wire [4:0] _T_229 = _T_228 & cam_raw_2_bits_rd; // @[dec_decode_ctl.scala 329:88] - wire _T_230 = io_decode_exu_dec_i0_rs1_en_d & cam_2_valid; // @[dec_decode_ctl.scala 329:137] - wire _T_231 = cam_raw_2_bits_rd == i0r_rs1; // @[dec_decode_ctl.scala 329:170] - wire _T_232 = _T_230 & _T_231; // @[dec_decode_ctl.scala 329:152] - wire _T_233 = io_decode_exu_dec_i0_rs2_en_d & cam_2_valid; // @[dec_decode_ctl.scala 329:214] - wire _T_234 = cam_raw_2_bits_rd == i0r_rs2; // @[dec_decode_ctl.scala 329:247] - wire _T_235 = _T_233 & _T_234; // @[dec_decode_ctl.scala 329:229] + wire [4:0] _T_229 = _T_228 & cam_raw_2_bits_rd; // @[dec_decode_ctl.scala 323:88] + wire _T_230 = io_decode_exu_dec_i0_rs1_en_d & cam_2_valid; // @[dec_decode_ctl.scala 323:137] + wire _T_231 = cam_raw_2_bits_rd == i0r_rs1; // @[dec_decode_ctl.scala 323:170] + wire _T_232 = _T_230 & _T_231; // @[dec_decode_ctl.scala 323:152] + wire _T_233 = io_decode_exu_dec_i0_rs2_en_d & cam_2_valid; // @[dec_decode_ctl.scala 323:214] + wire _T_234 = cam_raw_2_bits_rd == i0r_rs2; // @[dec_decode_ctl.scala 323:247] + wire _T_235 = _T_233 & _T_234; // @[dec_decode_ctl.scala 323:229] wire [4:0] _T_237 = nonblock_load_write_3 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12] - wire [4:0] _T_238 = _T_237 & cam_raw_3_bits_rd; // @[dec_decode_ctl.scala 329:88] - wire _T_239 = io_decode_exu_dec_i0_rs1_en_d & cam_3_valid; // @[dec_decode_ctl.scala 329:137] - wire _T_240 = cam_raw_3_bits_rd == i0r_rs1; // @[dec_decode_ctl.scala 329:170] - wire _T_241 = _T_239 & _T_240; // @[dec_decode_ctl.scala 329:152] - wire _T_242 = io_decode_exu_dec_i0_rs2_en_d & cam_3_valid; // @[dec_decode_ctl.scala 329:214] - wire _T_243 = cam_raw_3_bits_rd == i0r_rs2; // @[dec_decode_ctl.scala 329:247] - wire _T_244 = _T_242 & _T_243; // @[dec_decode_ctl.scala 329:229] - wire [4:0] _T_245 = _T_211 | _T_220; // @[dec_decode_ctl.scala 330:69] - wire [4:0] _T_246 = _T_245 | _T_229; // @[dec_decode_ctl.scala 330:69] - wire _T_247 = _T_214 | _T_223; // @[dec_decode_ctl.scala 330:102] - wire _T_248 = _T_247 | _T_232; // @[dec_decode_ctl.scala 330:102] - wire ld_stall_1 = _T_248 | _T_241; // @[dec_decode_ctl.scala 330:102] - wire _T_249 = _T_217 | _T_226; // @[dec_decode_ctl.scala 330:134] - wire _T_250 = _T_249 | _T_235; // @[dec_decode_ctl.scala 330:134] - wire ld_stall_2 = _T_250 | _T_244; // @[dec_decode_ctl.scala 330:134] - wire _T_251 = ld_stall_1 | ld_stall_2; // @[dec_decode_ctl.scala 332:38] - wire i0_nonblock_load_stall = _T_251 | i0_nonblock_boundary_stall; // @[dec_decode_ctl.scala 332:51] - wire _T_253 = ~i0_predict_br; // @[dec_decode_ctl.scala 341:34] + wire [4:0] _T_238 = _T_237 & cam_raw_3_bits_rd; // @[dec_decode_ctl.scala 323:88] + wire _T_239 = io_decode_exu_dec_i0_rs1_en_d & cam_3_valid; // @[dec_decode_ctl.scala 323:137] + wire _T_240 = cam_raw_3_bits_rd == i0r_rs1; // @[dec_decode_ctl.scala 323:170] + wire _T_241 = _T_239 & _T_240; // @[dec_decode_ctl.scala 323:152] + wire _T_242 = io_decode_exu_dec_i0_rs2_en_d & cam_3_valid; // @[dec_decode_ctl.scala 323:214] + wire _T_243 = cam_raw_3_bits_rd == i0r_rs2; // @[dec_decode_ctl.scala 323:247] + wire _T_244 = _T_242 & _T_243; // @[dec_decode_ctl.scala 323:229] + wire [4:0] _T_245 = _T_211 | _T_220; // @[dec_decode_ctl.scala 324:69] + wire [4:0] _T_246 = _T_245 | _T_229; // @[dec_decode_ctl.scala 324:69] + wire _T_247 = _T_214 | _T_223; // @[dec_decode_ctl.scala 324:102] + wire _T_248 = _T_247 | _T_232; // @[dec_decode_ctl.scala 324:102] + wire ld_stall_1 = _T_248 | _T_241; // @[dec_decode_ctl.scala 324:102] + wire _T_249 = _T_217 | _T_226; // @[dec_decode_ctl.scala 324:134] + wire _T_250 = _T_249 | _T_235; // @[dec_decode_ctl.scala 324:134] + wire ld_stall_2 = _T_250 | _T_244; // @[dec_decode_ctl.scala 324:134] + wire _T_251 = ld_stall_1 | ld_stall_2; // @[dec_decode_ctl.scala 326:38] + wire i0_nonblock_load_stall = _T_251 | i0_nonblock_boundary_stall; // @[dec_decode_ctl.scala 326:51] + wire _T_253 = ~i0_predict_br; // @[dec_decode_ctl.scala 335:34] wire [3:0] _T_255 = i0_legal_decode_d ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire csr_read = i0_dp_csr_read & i0_legal_decode_d; // @[dec_decode_ctl.scala 425:36] - wire _T_256 = csr_read & io_dec_csr_wen_unq_d; // @[dec_decode_ctl.scala 353:16] - wire _T_258 = ~csr_read; // @[dec_decode_ctl.scala 354:6] - wire _T_259 = _T_258 & io_dec_csr_wen_unq_d; // @[dec_decode_ctl.scala 354:16] - wire _T_261 = ~io_dec_csr_wen_unq_d; // @[dec_decode_ctl.scala 355:18] - wire _T_262 = csr_read & _T_261; // @[dec_decode_ctl.scala 355:16] + wire csr_read = i0_dp_csr_read & i0_legal_decode_d; // @[dec_decode_ctl.scala 419:36] + wire _T_256 = csr_read & io_dec_csr_wen_unq_d; // @[dec_decode_ctl.scala 347:16] + wire _T_258 = ~csr_read; // @[dec_decode_ctl.scala 348:6] + wire _T_259 = _T_258 & io_dec_csr_wen_unq_d; // @[dec_decode_ctl.scala 348:16] + wire _T_261 = ~io_dec_csr_wen_unq_d; // @[dec_decode_ctl.scala 349:18] + wire _T_262 = csr_read & _T_261; // @[dec_decode_ctl.scala 349:16] wire [3:0] _T_264 = i0_dp_mul ? 4'h1 : 4'h0; // @[Mux.scala 98:16] wire [3:0] _T_265 = i0_dp_load ? 4'h2 : _T_264; // @[Mux.scala 98:16] wire [3:0] _T_266 = i0_dp_store ? 4'h3 : _T_265; // @[Mux.scala 98:16] @@ -46787,143 +46787,143 @@ module dec_decode_ctl( wire [3:0] _T_275 = i0_dp_mret ? 4'hc : _T_274; // @[Mux.scala 98:16] wire [3:0] _T_276 = i0_dp_condbr ? 4'hd : _T_275; // @[Mux.scala 98:16] wire [3:0] _T_277 = i0_dp_jal ? 4'he : _T_276; // @[Mux.scala 98:16] - reg lsu_idle; // @[dec_decode_ctl.scala 366:45] - wire _T_333 = ~i0_pcall_case; // @[dec_decode_ctl.scala 390:35] - wire _T_334 = i0_dp_jal & _T_333; // @[dec_decode_ctl.scala 390:32] - wire _T_335 = ~i0_pja_case; // @[dec_decode_ctl.scala 390:52] - wire _T_336 = _T_334 & _T_335; // @[dec_decode_ctl.scala 390:50] - wire _T_337 = ~i0_pret_case; // @[dec_decode_ctl.scala 390:67] - reg _T_339; // @[dec_decode_ctl.scala 402:69] - wire lsu_decode_d = i0_legal_decode_d & i0_dp_lsu; // @[dec_decode_ctl.scala 544:40] - wire _T_905 = i0_dp_load | i0_dp_store; // @[dec_decode_ctl.scala 758:43] + reg lsu_idle; // @[dec_decode_ctl.scala 360:45] + wire _T_333 = ~i0_pcall_case; // @[dec_decode_ctl.scala 384:35] + wire _T_334 = i0_dp_jal & _T_333; // @[dec_decode_ctl.scala 384:32] + wire _T_335 = ~i0_pja_case; // @[dec_decode_ctl.scala 384:52] + wire _T_336 = _T_334 & _T_335; // @[dec_decode_ctl.scala 384:50] + wire _T_337 = ~i0_pret_case; // @[dec_decode_ctl.scala 384:67] + reg _T_339; // @[dec_decode_ctl.scala 396:69] + wire lsu_decode_d = i0_legal_decode_d & i0_dp_lsu; // @[dec_decode_ctl.scala 538:40] + wire _T_907 = i0_dp_load | i0_dp_store; // @[dec_decode_ctl.scala 752:43] reg x_d_bits_i0v; // @[lib.scala 384:16] - wire _T_879 = io_decode_exu_dec_i0_rs1_en_d & x_d_bits_i0v; // @[dec_decode_ctl.scala 738:59] - wire _T_880 = x_d_bits_i0rd == i0r_rs1; // @[dec_decode_ctl.scala 738:91] - wire i0_rs1_depend_i0_x = _T_879 & _T_880; // @[dec_decode_ctl.scala 738:74] - wire _T_881 = io_decode_exu_dec_i0_rs1_en_d & r_d_bits_i0v; // @[dec_decode_ctl.scala 739:59] - wire _T_882 = r_d_bits_i0rd == i0r_rs1; // @[dec_decode_ctl.scala 739:91] - wire i0_rs1_depend_i0_r = _T_881 & _T_882; // @[dec_decode_ctl.scala 739:74] - wire [1:0] _T_894 = i0_rs1_depend_i0_r ? 2'h2 : 2'h0; // @[dec_decode_ctl.scala 745:63] - wire [1:0] i0_rs1_depth_d = i0_rs1_depend_i0_x ? 2'h1 : _T_894; // @[dec_decode_ctl.scala 745:24] - wire _T_907 = _T_905 & i0_rs1_depth_d[0]; // @[dec_decode_ctl.scala 758:58] - reg i0_x_c_load; // @[Reg.scala 15:16] - reg i0_r_c_load; // @[Reg.scala 15:16] - wire _T_890_load = i0_rs1_depend_i0_r & i0_r_c_load; // @[dec_decode_ctl.scala 744:61] - wire i0_rs1_class_d_load = i0_rs1_depend_i0_x ? i0_x_c_load : _T_890_load; // @[dec_decode_ctl.scala 744:24] - wire load_ldst_bypass_d = _T_907 & i0_rs1_class_d_load; // @[dec_decode_ctl.scala 758:78] - wire _T_883 = io_decode_exu_dec_i0_rs2_en_d & x_d_bits_i0v; // @[dec_decode_ctl.scala 741:59] - wire _T_884 = x_d_bits_i0rd == i0r_rs2; // @[dec_decode_ctl.scala 741:91] - wire i0_rs2_depend_i0_x = _T_883 & _T_884; // @[dec_decode_ctl.scala 741:74] - wire _T_885 = io_decode_exu_dec_i0_rs2_en_d & r_d_bits_i0v; // @[dec_decode_ctl.scala 742:59] - wire _T_886 = r_d_bits_i0rd == i0r_rs2; // @[dec_decode_ctl.scala 742:91] - wire i0_rs2_depend_i0_r = _T_885 & _T_886; // @[dec_decode_ctl.scala 742:74] - wire [1:0] _T_903 = i0_rs2_depend_i0_r ? 2'h2 : 2'h0; // @[dec_decode_ctl.scala 747:63] - wire [1:0] i0_rs2_depth_d = i0_rs2_depend_i0_x ? 2'h1 : _T_903; // @[dec_decode_ctl.scala 747:24] - wire _T_910 = i0_dp_store & i0_rs2_depth_d[0]; // @[dec_decode_ctl.scala 759:43] - wire _T_899_load = i0_rs2_depend_i0_r & i0_r_c_load; // @[dec_decode_ctl.scala 746:61] - wire i0_rs2_class_d_load = i0_rs2_depend_i0_x ? i0_x_c_load : _T_899_load; // @[dec_decode_ctl.scala 746:24] - wire store_data_bypass_d = _T_910 & i0_rs2_class_d_load; // @[dec_decode_ctl.scala 759:63] - wire _T_349 = i0_dp_csr_clr | i0_dp_csr_set; // @[dec_decode_ctl.scala 433:42] + wire _T_881 = io_decode_exu_dec_i0_rs1_en_d & x_d_bits_i0v; // @[dec_decode_ctl.scala 732:59] + wire _T_882 = x_d_bits_i0rd == i0r_rs1; // @[dec_decode_ctl.scala 732:91] + wire i0_rs1_depend_i0_x = _T_881 & _T_882; // @[dec_decode_ctl.scala 732:74] + wire _T_883 = io_decode_exu_dec_i0_rs1_en_d & r_d_bits_i0v; // @[dec_decode_ctl.scala 733:59] + wire _T_884 = r_d_bits_i0rd == i0r_rs1; // @[dec_decode_ctl.scala 733:91] + wire i0_rs1_depend_i0_r = _T_883 & _T_884; // @[dec_decode_ctl.scala 733:74] + wire [1:0] _T_896 = i0_rs1_depend_i0_r ? 2'h2 : 2'h0; // @[dec_decode_ctl.scala 739:63] + wire [1:0] i0_rs1_depth_d = i0_rs1_depend_i0_x ? 2'h1 : _T_896; // @[dec_decode_ctl.scala 739:24] + wire _T_909 = _T_907 & i0_rs1_depth_d[0]; // @[dec_decode_ctl.scala 752:58] + reg i0_x_c_load; // @[Reg.scala 27:20] + reg i0_r_c_load; // @[Reg.scala 27:20] + wire _T_892_load = i0_rs1_depend_i0_r & i0_r_c_load; // @[dec_decode_ctl.scala 738:61] + wire i0_rs1_class_d_load = i0_rs1_depend_i0_x ? i0_x_c_load : _T_892_load; // @[dec_decode_ctl.scala 738:24] + wire load_ldst_bypass_d = _T_909 & i0_rs1_class_d_load; // @[dec_decode_ctl.scala 752:78] + wire _T_885 = io_decode_exu_dec_i0_rs2_en_d & x_d_bits_i0v; // @[dec_decode_ctl.scala 735:59] + wire _T_886 = x_d_bits_i0rd == i0r_rs2; // @[dec_decode_ctl.scala 735:91] + wire i0_rs2_depend_i0_x = _T_885 & _T_886; // @[dec_decode_ctl.scala 735:74] + wire _T_887 = io_decode_exu_dec_i0_rs2_en_d & r_d_bits_i0v; // @[dec_decode_ctl.scala 736:59] + wire _T_888 = r_d_bits_i0rd == i0r_rs2; // @[dec_decode_ctl.scala 736:91] + wire i0_rs2_depend_i0_r = _T_887 & _T_888; // @[dec_decode_ctl.scala 736:74] + wire [1:0] _T_905 = i0_rs2_depend_i0_r ? 2'h2 : 2'h0; // @[dec_decode_ctl.scala 741:63] + wire [1:0] i0_rs2_depth_d = i0_rs2_depend_i0_x ? 2'h1 : _T_905; // @[dec_decode_ctl.scala 741:24] + wire _T_912 = i0_dp_store & i0_rs2_depth_d[0]; // @[dec_decode_ctl.scala 753:43] + wire _T_901_load = i0_rs2_depend_i0_r & i0_r_c_load; // @[dec_decode_ctl.scala 740:61] + wire i0_rs2_class_d_load = i0_rs2_depend_i0_x ? i0_x_c_load : _T_901_load; // @[dec_decode_ctl.scala 740:24] + wire store_data_bypass_d = _T_912 & i0_rs2_class_d_load; // @[dec_decode_ctl.scala 753:63] + wire _T_349 = i0_dp_csr_clr | i0_dp_csr_set; // @[dec_decode_ctl.scala 427:42] reg r_d_bits_csrwen; // @[lib.scala 384:16] reg r_d_valid; // @[lib.scala 384:16] - wire _T_352 = r_d_bits_csrwen & r_d_valid; // @[dec_decode_ctl.scala 441:39] + wire _T_352 = r_d_bits_csrwen & r_d_valid; // @[dec_decode_ctl.scala 435:39] reg [11:0] r_d_bits_csrwaddr; // @[lib.scala 384:16] - wire _T_355 = r_d_bits_csrwaddr == 12'h300; // @[dec_decode_ctl.scala 444:50] - wire _T_356 = r_d_bits_csrwaddr == 12'h304; // @[dec_decode_ctl.scala 444:85] - wire _T_357 = _T_355 | _T_356; // @[dec_decode_ctl.scala 444:64] - wire _T_358 = _T_357 & r_d_bits_csrwen; // @[dec_decode_ctl.scala 444:100] - wire _T_359 = _T_358 & r_d_valid; // @[dec_decode_ctl.scala 444:118] - wire _T_360 = ~io_dec_tlu_i0_kill_writeb_wb; // @[dec_decode_ctl.scala 444:132] - reg csr_read_x; // @[dec_decode_ctl.scala 446:52] - reg csr_clr_x; // @[dec_decode_ctl.scala 447:51] - reg csr_set_x; // @[dec_decode_ctl.scala 448:51] - reg csr_write_x; // @[dec_decode_ctl.scala 449:53] - reg csr_imm_x; // @[dec_decode_ctl.scala 450:51] - wire i0_x_data_en = i0_pipe_en[3] | io_clk_override; // @[dec_decode_ctl.scala 627:50] + wire _T_355 = r_d_bits_csrwaddr == 12'h300; // @[dec_decode_ctl.scala 438:50] + wire _T_356 = r_d_bits_csrwaddr == 12'h304; // @[dec_decode_ctl.scala 438:85] + wire _T_357 = _T_355 | _T_356; // @[dec_decode_ctl.scala 438:64] + wire _T_358 = _T_357 & r_d_bits_csrwen; // @[dec_decode_ctl.scala 438:100] + wire _T_359 = _T_358 & r_d_valid; // @[dec_decode_ctl.scala 438:118] + wire _T_360 = ~io_dec_tlu_i0_kill_writeb_wb; // @[dec_decode_ctl.scala 438:132] + reg csr_read_x; // @[dec_decode_ctl.scala 440:52] + reg csr_clr_x; // @[dec_decode_ctl.scala 441:51] + reg csr_set_x; // @[dec_decode_ctl.scala 442:51] + reg csr_write_x; // @[dec_decode_ctl.scala 443:53] + reg csr_imm_x; // @[dec_decode_ctl.scala 444:51] + wire i0_x_data_en = i0_pipe_en[3] | io_clk_override; // @[dec_decode_ctl.scala 621:50] reg [4:0] csrimm_x; // @[lib.scala 374:16] reg [31:0] csr_rddata_x; // @[lib.scala 374:16] wire [31:0] _T_394 = {27'h0,csrimm_x}; // @[Cat.scala 29:58] - wire _T_396 = ~csr_imm_x; // @[dec_decode_ctl.scala 458:5] + wire _T_396 = ~csr_imm_x; // @[dec_decode_ctl.scala 452:5] wire [31:0] _T_397 = csr_imm_x ? _T_394 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_398 = _T_396 ? io_decode_exu_exu_csr_rs1_x : 32'h0; // @[Mux.scala 27:72] wire [31:0] csr_mask_x = _T_397 | _T_398; // @[Mux.scala 27:72] - wire [31:0] _T_400 = ~csr_mask_x; // @[dec_decode_ctl.scala 461:38] - wire [31:0] _T_401 = csr_rddata_x & _T_400; // @[dec_decode_ctl.scala 461:35] - wire [31:0] _T_402 = csr_rddata_x | csr_mask_x; // @[dec_decode_ctl.scala 462:35] + wire [31:0] _T_400 = ~csr_mask_x; // @[dec_decode_ctl.scala 455:38] + wire [31:0] _T_401 = csr_rddata_x & _T_400; // @[dec_decode_ctl.scala 455:35] + wire [31:0] _T_402 = csr_rddata_x | csr_mask_x; // @[dec_decode_ctl.scala 456:35] wire [31:0] _T_403 = csr_clr_x ? _T_401 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_404 = csr_set_x ? _T_402 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_405 = csr_write_x ? csr_mask_x : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_406 = _T_403 | _T_404; // @[Mux.scala 27:72] wire [31:0] write_csr_data_x = _T_406 | _T_405; // @[Mux.scala 27:72] - wire _T_421 = ~tlu_wr_pause_r1; // @[dec_decode_ctl.scala 472:44] - wire _T_422 = ~tlu_wr_pause_r2; // @[dec_decode_ctl.scala 472:64] - wire _T_423 = _T_421 & _T_422; // @[dec_decode_ctl.scala 472:61] - wire [31:0] _T_426 = write_csr_data - 32'h1; // @[dec_decode_ctl.scala 475:59] - wire _T_428 = csr_clr_x | csr_set_x; // @[dec_decode_ctl.scala 477:34] - wire _T_429 = _T_428 | csr_write_x; // @[dec_decode_ctl.scala 477:46] - wire _T_430 = _T_429 & csr_read_x; // @[dec_decode_ctl.scala 477:61] - wire _T_431 = _T_430 | io_dec_tlu_wr_pause_r; // @[dec_decode_ctl.scala 477:75] + wire _T_421 = ~tlu_wr_pause_r1; // @[dec_decode_ctl.scala 466:44] + wire _T_422 = ~tlu_wr_pause_r2; // @[dec_decode_ctl.scala 466:64] + wire _T_423 = _T_421 & _T_422; // @[dec_decode_ctl.scala 466:61] + wire [31:0] _T_426 = write_csr_data - 32'h1; // @[dec_decode_ctl.scala 469:59] + wire _T_428 = csr_clr_x | csr_set_x; // @[dec_decode_ctl.scala 471:34] + wire _T_429 = _T_428 | csr_write_x; // @[dec_decode_ctl.scala 471:46] + wire _T_430 = _T_429 & csr_read_x; // @[dec_decode_ctl.scala 471:61] + wire _T_431 = _T_430 | io_dec_tlu_wr_pause_r; // @[dec_decode_ctl.scala 471:75] reg r_d_bits_csrwonly; // @[lib.scala 384:16] - wire _T_767 = r_d_bits_i0v & r_d_bits_i0load; // @[dec_decode_ctl.scala 680:42] + wire _T_769 = r_d_bits_i0v & r_d_bits_i0load; // @[dec_decode_ctl.scala 674:42] reg [31:0] i0_result_r_raw; // @[lib.scala 374:16] - wire [31:0] i0_result_corr_r = _T_767 ? io_lsu_result_corr_r : i0_result_r_raw; // @[dec_decode_ctl.scala 680:27] + wire [31:0] i0_result_corr_r = _T_769 ? io_lsu_result_corr_r : i0_result_r_raw; // @[dec_decode_ctl.scala 674:27] reg x_d_bits_csrwonly; // @[lib.scala 384:16] - wire _T_435 = x_d_bits_csrwonly | r_d_bits_csrwonly; // @[dec_decode_ctl.scala 486:43] + wire _T_435 = x_d_bits_csrwonly | r_d_bits_csrwonly; // @[dec_decode_ctl.scala 480:43] reg wbd_bits_csrwonly; // @[lib.scala 384:16] - wire prior_csr_write = _T_435 | wbd_bits_csrwonly; // @[dec_decode_ctl.scala 486:63] - wire debug_fence_raw = io_dec_debug_fence_d & io_dbg_dctl_dbg_cmd_wrdata[1]; // @[dec_decode_ctl.scala 489:48] - wire debug_fence = debug_fence_raw | debug_fence_i; // @[dec_decode_ctl.scala 490:40] - wire _T_439 = i0_dp_presync | io_dec_tlu_presync_d; // @[dec_decode_ctl.scala 493:34] - wire _T_440 = _T_439 | debug_fence_i; // @[dec_decode_ctl.scala 493:57] - wire _T_441 = _T_440 | debug_fence_raw; // @[dec_decode_ctl.scala 493:73] - wire i0_presync = _T_441 | io_dec_tlu_pipelining_disable; // @[dec_decode_ctl.scala 493:91] + wire prior_csr_write = _T_435 | wbd_bits_csrwonly; // @[dec_decode_ctl.scala 480:63] + wire debug_fence_raw = io_dec_debug_fence_d & io_dbg_dctl_dbg_cmd_wrdata[1]; // @[dec_decode_ctl.scala 483:48] + wire debug_fence = debug_fence_raw | debug_fence_i; // @[dec_decode_ctl.scala 484:40] + wire _T_439 = i0_dp_presync | io_dec_tlu_presync_d; // @[dec_decode_ctl.scala 487:34] + wire _T_440 = _T_439 | debug_fence_i; // @[dec_decode_ctl.scala 487:57] + wire _T_441 = _T_440 | debug_fence_raw; // @[dec_decode_ctl.scala 487:73] + wire i0_presync = _T_441 | io_dec_tlu_pipelining_disable; // @[dec_decode_ctl.scala 487:91] wire [31:0] _T_465 = {16'h0,io_dec_aln_ifu_i0_cinst}; // @[Cat.scala 29:58] - wire _T_467 = ~illegal_lockout; // @[dec_decode_ctl.scala 505:44] + wire _T_467 = ~illegal_lockout; // @[dec_decode_ctl.scala 499:44] reg [31:0] _T_468; // @[lib.scala 374:16] - wire i0_div_prior_div_stall = i0_dp_div & io_dec_div_active; // @[dec_decode_ctl.scala 509:42] - wire _T_473 = i0_dp_csr_read & prior_csr_write; // @[dec_decode_ctl.scala 511:40] - wire _T_474 = _T_473 | io_decode_exu_dec_extint_stall; // @[dec_decode_ctl.scala 511:59] - wire _T_475 = _T_474 | pause_stall; // @[dec_decode_ctl.scala 511:92] - wire _T_476 = _T_475 | leak1_i0_stall; // @[dec_decode_ctl.scala 511:106] - wire _T_477 = _T_476 | io_dec_tlu_debug_stall; // @[dec_decode_ctl.scala 512:20] - wire _T_478 = _T_477 | postsync_stall; // @[dec_decode_ctl.scala 512:45] - wire prior_inflight = x_d_valid | r_d_valid; // @[dec_decode_ctl.scala 534:41] - wire prior_inflight_eff = i0_dp_div ? x_d_valid : prior_inflight; // @[dec_decode_ctl.scala 535:31] - wire presync_stall = i0_presync & prior_inflight_eff; // @[dec_decode_ctl.scala 537:37] - wire _T_479 = _T_478 | presync_stall; // @[dec_decode_ctl.scala 512:62] - wire _T_480 = i0_dp_fence | debug_fence; // @[dec_decode_ctl.scala 513:19] - wire _T_481 = ~lsu_idle; // @[dec_decode_ctl.scala 513:36] - wire _T_482 = _T_480 & _T_481; // @[dec_decode_ctl.scala 513:34] - wire _T_483 = _T_479 | _T_482; // @[dec_decode_ctl.scala 512:79] - wire _T_484 = _T_483 | i0_nonblock_load_stall; // @[dec_decode_ctl.scala 513:47] - wire _T_825 = io_decode_exu_dec_i0_rs1_en_d & io_dec_div_active; // @[dec_decode_ctl.scala 708:60] - wire _T_826 = io_div_waddr_wb == i0r_rs1; // @[dec_decode_ctl.scala 708:99] - wire _T_827 = _T_825 & _T_826; // @[dec_decode_ctl.scala 708:80] - wire _T_828 = io_decode_exu_dec_i0_rs2_en_d & io_dec_div_active; // @[dec_decode_ctl.scala 709:36] - wire _T_829 = io_div_waddr_wb == i0r_rs2; // @[dec_decode_ctl.scala 709:75] - wire _T_830 = _T_828 & _T_829; // @[dec_decode_ctl.scala 709:56] - wire i0_nonblock_div_stall = _T_827 | _T_830; // @[dec_decode_ctl.scala 708:113] - wire _T_486 = _T_484 | i0_nonblock_div_stall; // @[dec_decode_ctl.scala 514:21] - wire i0_block_raw_d = _T_486 | i0_div_prior_div_stall; // @[dec_decode_ctl.scala 514:45] - wire _T_487 = io_lsu_store_stall_any | io_dctl_dma_dma_dccm_stall_any; // @[dec_decode_ctl.scala 516:65] - wire i0_store_stall_d = i0_dp_store & _T_487; // @[dec_decode_ctl.scala 516:39] - wire _T_488 = io_lsu_load_stall_any | io_dctl_dma_dma_dccm_stall_any; // @[dec_decode_ctl.scala 517:63] - wire i0_load_stall_d = i0_dp_load & _T_488; // @[dec_decode_ctl.scala 517:38] - wire _T_489 = i0_block_raw_d | i0_store_stall_d; // @[dec_decode_ctl.scala 518:38] - wire i0_block_d = _T_489 | i0_load_stall_d; // @[dec_decode_ctl.scala 518:57] - wire _T_490 = ~i0_block_d; // @[dec_decode_ctl.scala 522:54] - wire _T_491 = io_dec_ib0_valid_d & _T_490; // @[dec_decode_ctl.scala 522:52] - wire _T_493 = _T_491 & _T_280; // @[dec_decode_ctl.scala 522:69] - wire _T_496 = ~i0_block_raw_d; // @[dec_decode_ctl.scala 523:46] - wire _T_497 = io_dec_ib0_valid_d & _T_496; // @[dec_decode_ctl.scala 523:44] - wire _T_499 = _T_497 & _T_280; // @[dec_decode_ctl.scala 523:61] - wire i0_exudecode_d = _T_499 & _T_470; // @[dec_decode_ctl.scala 523:89] - wire i0_exulegal_decode_d = i0_exudecode_d & i0_legal; // @[dec_decode_ctl.scala 524:46] - wire _T_501 = ~io_dec_aln_dec_i0_decode_d; // @[dec_decode_ctl.scala 528:51] - wire _T_520 = i0_dp_fence_i | debug_fence_i; // @[dec_decode_ctl.scala 556:44] + wire i0_div_prior_div_stall = i0_dp_div & io_dec_div_active; // @[dec_decode_ctl.scala 503:42] + wire _T_473 = i0_dp_csr_read & prior_csr_write; // @[dec_decode_ctl.scala 505:40] + wire _T_474 = _T_473 | io_decode_exu_dec_extint_stall; // @[dec_decode_ctl.scala 505:59] + wire _T_475 = _T_474 | pause_stall; // @[dec_decode_ctl.scala 505:92] + wire _T_476 = _T_475 | leak1_i0_stall; // @[dec_decode_ctl.scala 505:106] + wire _T_477 = _T_476 | io_dec_tlu_debug_stall; // @[dec_decode_ctl.scala 506:20] + wire _T_478 = _T_477 | postsync_stall; // @[dec_decode_ctl.scala 506:45] + wire prior_inflight = x_d_valid | r_d_valid; // @[dec_decode_ctl.scala 528:41] + wire prior_inflight_eff = i0_dp_div ? x_d_valid : prior_inflight; // @[dec_decode_ctl.scala 529:31] + wire presync_stall = i0_presync & prior_inflight_eff; // @[dec_decode_ctl.scala 531:37] + wire _T_479 = _T_478 | presync_stall; // @[dec_decode_ctl.scala 506:62] + wire _T_480 = i0_dp_fence | debug_fence; // @[dec_decode_ctl.scala 507:19] + wire _T_481 = ~lsu_idle; // @[dec_decode_ctl.scala 507:36] + wire _T_482 = _T_480 & _T_481; // @[dec_decode_ctl.scala 507:34] + wire _T_483 = _T_479 | _T_482; // @[dec_decode_ctl.scala 506:79] + wire _T_484 = _T_483 | i0_nonblock_load_stall; // @[dec_decode_ctl.scala 507:47] + wire _T_827 = io_decode_exu_dec_i0_rs1_en_d & io_dec_div_active; // @[dec_decode_ctl.scala 702:60] + wire _T_828 = io_div_waddr_wb == i0r_rs1; // @[dec_decode_ctl.scala 702:99] + wire _T_829 = _T_827 & _T_828; // @[dec_decode_ctl.scala 702:80] + wire _T_830 = io_decode_exu_dec_i0_rs2_en_d & io_dec_div_active; // @[dec_decode_ctl.scala 703:36] + wire _T_831 = io_div_waddr_wb == i0r_rs2; // @[dec_decode_ctl.scala 703:75] + wire _T_832 = _T_830 & _T_831; // @[dec_decode_ctl.scala 703:56] + wire i0_nonblock_div_stall = _T_829 | _T_832; // @[dec_decode_ctl.scala 702:113] + wire _T_486 = _T_484 | i0_nonblock_div_stall; // @[dec_decode_ctl.scala 508:21] + wire i0_block_raw_d = _T_486 | i0_div_prior_div_stall; // @[dec_decode_ctl.scala 508:45] + wire _T_487 = io_lsu_store_stall_any | io_dctl_dma_dma_dccm_stall_any; // @[dec_decode_ctl.scala 510:65] + wire i0_store_stall_d = i0_dp_store & _T_487; // @[dec_decode_ctl.scala 510:39] + wire _T_488 = io_lsu_load_stall_any | io_dctl_dma_dma_dccm_stall_any; // @[dec_decode_ctl.scala 511:63] + wire i0_load_stall_d = i0_dp_load & _T_488; // @[dec_decode_ctl.scala 511:38] + wire _T_489 = i0_block_raw_d | i0_store_stall_d; // @[dec_decode_ctl.scala 512:38] + wire i0_block_d = _T_489 | i0_load_stall_d; // @[dec_decode_ctl.scala 512:57] + wire _T_490 = ~i0_block_d; // @[dec_decode_ctl.scala 516:54] + wire _T_491 = io_dec_ib0_valid_d & _T_490; // @[dec_decode_ctl.scala 516:52] + wire _T_493 = _T_491 & _T_280; // @[dec_decode_ctl.scala 516:69] + wire _T_496 = ~i0_block_raw_d; // @[dec_decode_ctl.scala 517:46] + wire _T_497 = io_dec_ib0_valid_d & _T_496; // @[dec_decode_ctl.scala 517:44] + wire _T_499 = _T_497 & _T_280; // @[dec_decode_ctl.scala 517:61] + wire i0_exudecode_d = _T_499 & _T_470; // @[dec_decode_ctl.scala 517:89] + wire i0_exulegal_decode_d = i0_exudecode_d & i0_legal; // @[dec_decode_ctl.scala 518:46] + wire _T_501 = ~io_dec_aln_dec_i0_decode_d; // @[dec_decode_ctl.scala 522:51] + wire _T_520 = i0_dp_fence_i | debug_fence_i; // @[dec_decode_ctl.scala 550:44] wire [3:0] _T_525 = {io_dec_aln_dec_i0_decode_d,io_dec_aln_dec_i0_decode_d,io_dec_aln_dec_i0_decode_d,io_dec_aln_dec_i0_decode_d}; // @[Cat.scala 29:58] - wire _T_707 = |i0_pipe_en[3:2]; // @[dec_decode_ctl.scala 624:49] - wire i0_x_ctl_en = _T_707 | io_clk_override; // @[dec_decode_ctl.scala 624:53] + wire _T_709 = |i0_pipe_en[3:2]; // @[dec_decode_ctl.scala 618:49] + wire i0_x_ctl_en = _T_709 | io_clk_override; // @[dec_decode_ctl.scala 618:53] reg x_t_legal; // @[lib.scala 384:16] reg x_t_icaf; // @[lib.scala 384:16] reg x_t_icaf_f1; // @[lib.scala 384:16] @@ -46933,7 +46933,7 @@ module dec_decode_ctl( reg [3:0] x_t_pmu_i0_itype; // @[lib.scala 384:16] reg x_t_pmu_i0_br_unpred; // @[lib.scala 384:16] wire [3:0] _T_533 = {io_dec_tlu_flush_lower_wb,io_dec_tlu_flush_lower_wb,io_dec_tlu_flush_lower_wb,io_dec_tlu_flush_lower_wb}; // @[Cat.scala 29:58] - wire [3:0] _T_534 = ~_T_533; // @[dec_decode_ctl.scala 569:39] + wire [3:0] _T_534 = ~_T_533; // @[dec_decode_ctl.scala 563:39] reg r_t_legal; // @[lib.scala 384:16] reg r_t_icaf; // @[lib.scala 384:16] reg r_t_icaf_f1; // @[lib.scala 384:16] @@ -46942,22 +46942,22 @@ module dec_decode_ctl( reg [3:0] r_t_i0trigger; // @[lib.scala 384:16] reg [3:0] r_t_pmu_i0_itype; // @[lib.scala 384:16] reg r_t_pmu_i0_br_unpred; // @[lib.scala 384:16] - reg [3:0] lsu_trigger_match_r; // @[dec_decode_ctl.scala 572:36] - reg lsu_pmu_misaligned_r; // @[dec_decode_ctl.scala 573:37] + reg [3:0] lsu_trigger_match_r; // @[dec_decode_ctl.scala 566:36] + reg lsu_pmu_misaligned_r; // @[dec_decode_ctl.scala 567:37] reg r_d_bits_i0store; // @[lib.scala 384:16] - wire _T_539 = r_d_bits_i0load | r_d_bits_i0store; // @[dec_decode_ctl.scala 577:61] + wire _T_539 = r_d_bits_i0load | r_d_bits_i0store; // @[dec_decode_ctl.scala 571:61] wire [3:0] _T_543 = {_T_539,_T_539,_T_539,_T_539}; // @[Cat.scala 29:58] - wire [3:0] _T_544 = _T_543 & lsu_trigger_match_r; // @[dec_decode_ctl.scala 577:82] - wire [3:0] _T_545 = _T_544 | r_t_i0trigger; // @[dec_decode_ctl.scala 577:105] + wire [3:0] _T_544 = _T_543 & lsu_trigger_match_r; // @[dec_decode_ctl.scala 571:82] + wire [3:0] _T_545 = _T_544 | r_t_i0trigger; // @[dec_decode_ctl.scala 571:105] reg r_d_bits_i0div; // @[lib.scala 384:16] - wire _T_548 = r_d_bits_i0div & r_d_valid; // @[dec_decode_ctl.scala 583:58] - wire _T_559 = i0r_rs1 != 5'h0; // @[dec_decode_ctl.scala 594:60] - wire _T_561 = i0r_rs2 != 5'h0; // @[dec_decode_ctl.scala 595:60] - wire _T_563 = i0r_rd != 5'h0; // @[dec_decode_ctl.scala 596:48] - wire i0_rd_en_d = i0_dp_rd & _T_563; // @[dec_decode_ctl.scala 596:37] - wire i0_jalimm20 = i0_dp_jal & i0_dp_imm20; // @[dec_decode_ctl.scala 600:38] - wire _T_564 = ~i0_dp_jal; // @[dec_decode_ctl.scala 601:27] - wire i0_uiimm20 = _T_564 & i0_dp_imm20; // @[dec_decode_ctl.scala 601:38] + wire _T_548 = r_d_bits_i0div & r_d_valid; // @[dec_decode_ctl.scala 577:58] + wire _T_559 = i0r_rs1 != 5'h0; // @[dec_decode_ctl.scala 588:60] + wire _T_561 = i0r_rs2 != 5'h0; // @[dec_decode_ctl.scala 589:60] + wire _T_563 = i0r_rd != 5'h0; // @[dec_decode_ctl.scala 590:48] + wire i0_rd_en_d = i0_dp_rd & _T_563; // @[dec_decode_ctl.scala 590:37] + wire i0_jalimm20 = i0_dp_jal & i0_dp_imm20; // @[dec_decode_ctl.scala 594:38] + wire _T_564 = ~i0_dp_jal; // @[dec_decode_ctl.scala 595:27] + wire i0_uiimm20 = _T_564 & i0_dp_imm20; // @[dec_decode_ctl.scala 595:38] wire [31:0] _T_566 = i0_dp_csr_read ? io_dec_csr_rddata_d : 32'h0; // @[Mux.scala 27:72] wire [9:0] _T_580 = {io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31]}; // @[Cat.scala 29:58] wire [18:0] _T_589 = {_T_580,io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31]}; // @[Cat.scala 29:58] @@ -46972,148 +46972,148 @@ module dec_decode_ctl( wire [31:0] _T_655 = {io_dec_i0_instr_d[31:12],12'h0}; // @[Cat.scala 29:58] wire [31:0] _T_690 = i0_uiimm20 ? _T_655 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_694 = _T_693 | _T_690; // @[Mux.scala 27:72] - wire _T_656 = i0_csr_write_only_d & i0_dp_csr_imm; // @[dec_decode_ctl.scala 612:26] + wire _T_656 = i0_csr_write_only_d & i0_dp_csr_imm; // @[dec_decode_ctl.scala 606:26] wire [31:0] _T_686 = {27'h0,i0r_rs1}; // @[Cat.scala 29:58] wire [31:0] _T_691 = _T_656 ? _T_686 : 32'h0; // @[Mux.scala 27:72] wire [31:0] i0_immed_d = _T_694 | _T_691; // @[Mux.scala 27:72] wire [31:0] _T_567 = _T_347 ? i0_immed_d : 32'h0; // @[Mux.scala 27:72] - wire i0_d_c_mul = i0_dp_mul & i0_legal_decode_d; // @[dec_decode_ctl.scala 616:44] - wire i0_d_c_load = i0_dp_load & i0_legal_decode_d; // @[dec_decode_ctl.scala 617:44] - wire i0_d_c_alu = i0_dp_alu & i0_legal_decode_d; // @[dec_decode_ctl.scala 618:44] - reg i0_x_c_mul; // @[Reg.scala 15:16] - reg i0_x_c_alu; // @[Reg.scala 15:16] - reg i0_r_c_mul; // @[Reg.scala 15:16] - reg i0_r_c_alu; // @[Reg.scala 15:16] - wire _T_713 = |i0_pipe_en[1:0]; // @[dec_decode_ctl.scala 626:49] - wire i0_r_data_en = i0_pipe_en[2] | io_clk_override; // @[dec_decode_ctl.scala 628:50] + wire i0_d_c_mul = i0_dp_mul & i0_legal_decode_d; // @[dec_decode_ctl.scala 610:44] + wire i0_d_c_load = i0_dp_load & i0_legal_decode_d; // @[dec_decode_ctl.scala 611:44] + wire i0_d_c_alu = i0_dp_alu & i0_legal_decode_d; // @[dec_decode_ctl.scala 612:44] + reg i0_x_c_mul; // @[Reg.scala 27:20] + reg i0_x_c_alu; // @[Reg.scala 27:20] + reg i0_r_c_mul; // @[Reg.scala 27:20] + reg i0_r_c_alu; // @[Reg.scala 27:20] + wire _T_715 = |i0_pipe_en[1:0]; // @[dec_decode_ctl.scala 620:49] + wire i0_r_data_en = i0_pipe_en[2] | io_clk_override; // @[dec_decode_ctl.scala 622:50] reg x_d_bits_i0store; // @[lib.scala 384:16] reg x_d_bits_i0div; // @[lib.scala 384:16] reg x_d_bits_csrwen; // @[lib.scala 384:16] reg [11:0] x_d_bits_csrwaddr; // @[lib.scala 384:16] - wire _T_736 = x_d_bits_i0v & _T_746; // @[dec_decode_ctl.scala 650:47] - wire _T_740 = x_d_valid & _T_746; // @[dec_decode_ctl.scala 651:33] - wire _T_759 = ~r_d_bits_i0div; // @[dec_decode_ctl.scala 666:49] - wire _T_760 = i0_wen_r & _T_759; // @[dec_decode_ctl.scala 666:47] - wire _T_761 = ~i0_load_kill_wen_r; // @[dec_decode_ctl.scala 666:70] - wire _T_764 = x_d_bits_i0v & x_d_bits_i0load; // @[dec_decode_ctl.scala 675:47] - wire _T_771 = io_decode_exu_i0_ap_predict_nt & _T_564; // @[dec_decode_ctl.scala 681:71] - wire [11:0] _T_784 = {10'h0,io_dec_i0_pc4_d,i0_ap_pc2}; // @[Cat.scala 29:58] + wire _T_738 = x_d_bits_i0v & _T_748; // @[dec_decode_ctl.scala 644:47] + wire _T_742 = x_d_valid & _T_748; // @[dec_decode_ctl.scala 645:33] + wire _T_761 = ~r_d_bits_i0div; // @[dec_decode_ctl.scala 660:49] + wire _T_762 = i0_wen_r & _T_761; // @[dec_decode_ctl.scala 660:47] + wire _T_763 = ~i0_load_kill_wen_r; // @[dec_decode_ctl.scala 660:70] + wire _T_766 = x_d_bits_i0v & x_d_bits_i0load; // @[dec_decode_ctl.scala 669:47] + wire _T_773 = io_decode_exu_i0_ap_predict_nt & _T_564; // @[dec_decode_ctl.scala 675:71] + wire [11:0] _T_786 = {10'h0,io_dec_i0_pc4_d,i0_ap_pc2}; // @[Cat.scala 29:58] reg [11:0] last_br_immed_x; // @[lib.scala 374:16] - wire _T_802 = x_d_bits_i0div & x_d_valid; // @[dec_decode_ctl.scala 689:45] - wire div_e1_to_r = _T_802 | _T_548; // @[dec_decode_ctl.scala 689:58] - wire _T_805 = x_d_bits_i0rd == 5'h0; // @[dec_decode_ctl.scala 691:77] - wire _T_806 = _T_802 & _T_805; // @[dec_decode_ctl.scala 691:60] - wire _T_808 = _T_802 & io_dec_tlu_flush_lower_r; // @[dec_decode_ctl.scala 692:33] - wire _T_809 = _T_806 | _T_808; // @[dec_decode_ctl.scala 691:94] - wire _T_811 = _T_548 & io_dec_tlu_flush_lower_r; // @[dec_decode_ctl.scala 693:33] - wire _T_812 = _T_811 & io_dec_tlu_i0_kill_writeb_r; // @[dec_decode_ctl.scala 693:60] - wire div_flush = _T_809 | _T_812; // @[dec_decode_ctl.scala 692:62] - wire _T_813 = io_dec_div_active & div_flush; // @[dec_decode_ctl.scala 697:51] - wire _T_814 = ~div_e1_to_r; // @[dec_decode_ctl.scala 698:26] - wire _T_815 = io_dec_div_active & _T_814; // @[dec_decode_ctl.scala 698:24] - wire _T_816 = r_d_bits_i0rd == io_div_waddr_wb; // @[dec_decode_ctl.scala 698:56] - wire _T_817 = _T_815 & _T_816; // @[dec_decode_ctl.scala 698:39] - wire _T_818 = _T_817 & i0_wen_r; // @[dec_decode_ctl.scala 698:77] - wire nonblock_div_cancel = _T_813 | _T_818; // @[dec_decode_ctl.scala 697:65] - wire i0_div_decode_d = i0_legal_decode_d & i0_dp_div; // @[dec_decode_ctl.scala 701:55] - wire _T_820 = ~io_exu_div_wren; // @[dec_decode_ctl.scala 703:62] - wire _T_821 = io_dec_div_active & _T_820; // @[dec_decode_ctl.scala 703:60] - wire _T_822 = ~nonblock_div_cancel; // @[dec_decode_ctl.scala 703:81] - wire _T_823 = _T_821 & _T_822; // @[dec_decode_ctl.scala 703:79] - reg _T_824; // @[dec_decode_ctl.scala 705:54] - reg [4:0] _T_833; // @[Reg.scala 27:20] + wire _T_804 = x_d_bits_i0div & x_d_valid; // @[dec_decode_ctl.scala 683:45] + wire div_e1_to_r = _T_804 | _T_548; // @[dec_decode_ctl.scala 683:58] + wire _T_807 = x_d_bits_i0rd == 5'h0; // @[dec_decode_ctl.scala 685:77] + wire _T_808 = _T_804 & _T_807; // @[dec_decode_ctl.scala 685:60] + wire _T_810 = _T_804 & io_dec_tlu_flush_lower_r; // @[dec_decode_ctl.scala 686:33] + wire _T_811 = _T_808 | _T_810; // @[dec_decode_ctl.scala 685:94] + wire _T_813 = _T_548 & io_dec_tlu_flush_lower_r; // @[dec_decode_ctl.scala 687:33] + wire _T_814 = _T_813 & io_dec_tlu_i0_kill_writeb_r; // @[dec_decode_ctl.scala 687:60] + wire div_flush = _T_811 | _T_814; // @[dec_decode_ctl.scala 686:62] + wire _T_815 = io_dec_div_active & div_flush; // @[dec_decode_ctl.scala 691:51] + wire _T_816 = ~div_e1_to_r; // @[dec_decode_ctl.scala 692:26] + wire _T_817 = io_dec_div_active & _T_816; // @[dec_decode_ctl.scala 692:24] + wire _T_818 = r_d_bits_i0rd == io_div_waddr_wb; // @[dec_decode_ctl.scala 692:56] + wire _T_819 = _T_817 & _T_818; // @[dec_decode_ctl.scala 692:39] + wire _T_820 = _T_819 & i0_wen_r; // @[dec_decode_ctl.scala 692:77] + wire nonblock_div_cancel = _T_815 | _T_820; // @[dec_decode_ctl.scala 691:65] + wire i0_div_decode_d = i0_legal_decode_d & i0_dp_div; // @[dec_decode_ctl.scala 695:55] + wire _T_822 = ~io_exu_div_wren; // @[dec_decode_ctl.scala 697:62] + wire _T_823 = io_dec_div_active & _T_822; // @[dec_decode_ctl.scala 697:60] + wire _T_824 = ~nonblock_div_cancel; // @[dec_decode_ctl.scala 697:81] + wire _T_825 = _T_823 & _T_824; // @[dec_decode_ctl.scala 697:79] + reg _T_826; // @[dec_decode_ctl.scala 699:54] + reg [4:0] _T_835; // @[Reg.scala 27:20] reg [31:0] i0_inst_x; // @[lib.scala 374:16] reg [31:0] i0_inst_r; // @[lib.scala 374:16] reg [31:0] i0_inst_wb; // @[lib.scala 374:16] - reg [31:0] _T_840; // @[lib.scala 374:16] + reg [31:0] _T_842; // @[lib.scala 374:16] reg [30:0] i0_pc_wb; // @[lib.scala 374:16] - reg [30:0] _T_843; // @[lib.scala 374:16] + reg [30:0] _T_845; // @[lib.scala 374:16] reg [30:0] dec_i0_pc_r; // @[lib.scala 374:16] - wire [31:0] _T_845 = {io_dec_alu_exu_i0_pc_x,1'h0}; // @[Cat.scala 29:58] - wire [12:0] _T_846 = {last_br_immed_x,1'h0}; // @[Cat.scala 29:58] - wire [12:0] _T_849 = _T_845[12:1] + _T_846[12:1]; // @[lib.scala 68:31] - wire [18:0] _T_852 = _T_845[31:13] + 19'h1; // @[lib.scala 69:27] - wire [18:0] _T_855 = _T_845[31:13] - 19'h1; // @[lib.scala 70:27] - wire _T_858 = ~_T_849[12]; // @[lib.scala 72:28] - wire _T_859 = _T_846[12] ^ _T_858; // @[lib.scala 72:26] - wire _T_862 = ~_T_846[12]; // @[lib.scala 73:20] - wire _T_864 = _T_862 & _T_849[12]; // @[lib.scala 73:26] - wire _T_868 = _T_846[12] & _T_858; // @[lib.scala 74:26] - wire [18:0] _T_870 = _T_859 ? _T_845[31:13] : 19'h0; // @[Mux.scala 27:72] - wire [18:0] _T_871 = _T_864 ? _T_852 : 19'h0; // @[Mux.scala 27:72] - wire [18:0] _T_872 = _T_868 ? _T_855 : 19'h0; // @[Mux.scala 27:72] - wire [18:0] _T_873 = _T_870 | _T_871; // @[Mux.scala 27:72] - wire [18:0] _T_874 = _T_873 | _T_872; // @[Mux.scala 27:72] - wire [31:0] temp_pred_correct_npc_x = {_T_874,_T_849[11:0],1'h0}; // @[Cat.scala 29:58] - wire _T_890_mul = i0_rs1_depend_i0_r & i0_r_c_mul; // @[dec_decode_ctl.scala 744:61] - wire _T_890_alu = i0_rs1_depend_i0_r & i0_r_c_alu; // @[dec_decode_ctl.scala 744:61] - wire i0_rs1_class_d_mul = i0_rs1_depend_i0_x ? i0_x_c_mul : _T_890_mul; // @[dec_decode_ctl.scala 744:24] - wire i0_rs1_class_d_alu = i0_rs1_depend_i0_x ? i0_x_c_alu : _T_890_alu; // @[dec_decode_ctl.scala 744:24] - wire _T_899_mul = i0_rs2_depend_i0_r & i0_r_c_mul; // @[dec_decode_ctl.scala 746:61] - wire _T_899_alu = i0_rs2_depend_i0_r & i0_r_c_alu; // @[dec_decode_ctl.scala 746:61] - wire i0_rs2_class_d_mul = i0_rs2_depend_i0_x ? i0_x_c_mul : _T_899_mul; // @[dec_decode_ctl.scala 746:24] - wire i0_rs2_class_d_alu = i0_rs2_depend_i0_x ? i0_x_c_alu : _T_899_alu; // @[dec_decode_ctl.scala 746:24] - wire _T_912 = io_decode_exu_dec_i0_rs1_en_d & io_dec_nonblock_load_wen; // @[dec_decode_ctl.scala 764:73] - wire _T_913 = io_dec_nonblock_load_waddr == i0r_rs1; // @[dec_decode_ctl.scala 764:130] - wire i0_rs1_nonblock_load_bypass_en_d = _T_912 & _T_913; // @[dec_decode_ctl.scala 764:100] - wire _T_914 = io_decode_exu_dec_i0_rs2_en_d & io_dec_nonblock_load_wen; // @[dec_decode_ctl.scala 766:73] - wire _T_915 = io_dec_nonblock_load_waddr == i0r_rs2; // @[dec_decode_ctl.scala 766:130] - wire i0_rs2_nonblock_load_bypass_en_d = _T_914 & _T_915; // @[dec_decode_ctl.scala 766:100] - wire _T_917 = i0_rs1_class_d_alu | i0_rs1_class_d_mul; // @[dec_decode_ctl.scala 769:66] - wire _T_918 = i0_rs1_depth_d[0] & _T_917; // @[dec_decode_ctl.scala 769:45] - wire _T_920 = i0_rs1_depth_d[0] & i0_rs1_class_d_load; // @[dec_decode_ctl.scala 769:108] - wire _T_923 = _T_917 | i0_rs1_class_d_load; // @[dec_decode_ctl.scala 769:196] - wire _T_924 = i0_rs1_depth_d[1] & _T_923; // @[dec_decode_ctl.scala 769:153] - wire [2:0] i0_rs1bypass = {_T_918,_T_920,_T_924}; // @[Cat.scala 29:58] - wire _T_928 = i0_rs2_class_d_alu | i0_rs2_class_d_mul; // @[dec_decode_ctl.scala 771:67] - wire _T_929 = i0_rs2_depth_d[0] & _T_928; // @[dec_decode_ctl.scala 771:45] - wire _T_931 = i0_rs2_depth_d[0] & i0_rs2_class_d_load; // @[dec_decode_ctl.scala 771:109] - wire _T_934 = _T_928 | i0_rs2_class_d_load; // @[dec_decode_ctl.scala 771:196] - wire _T_935 = i0_rs2_depth_d[1] & _T_934; // @[dec_decode_ctl.scala 771:153] - wire [2:0] i0_rs2bypass = {_T_929,_T_931,_T_935}; // @[Cat.scala 29:58] - wire _T_941 = i0_rs1bypass[1] | i0_rs1bypass[0]; // @[dec_decode_ctl.scala 773:86] - wire _T_943 = ~i0_rs1bypass[2]; // @[dec_decode_ctl.scala 773:107] - wire _T_944 = _T_943 & i0_rs1_nonblock_load_bypass_en_d; // @[dec_decode_ctl.scala 773:124] - wire _T_945 = _T_941 | _T_944; // @[dec_decode_ctl.scala 773:104] - wire _T_950 = i0_rs2bypass[1] | i0_rs2bypass[0]; // @[dec_decode_ctl.scala 774:86] - wire _T_952 = ~i0_rs2bypass[2]; // @[dec_decode_ctl.scala 774:107] - wire _T_953 = _T_952 & i0_rs2_nonblock_load_bypass_en_d; // @[dec_decode_ctl.scala 774:124] - wire _T_954 = _T_950 | _T_953; // @[dec_decode_ctl.scala 774:104] - wire _T_961 = ~i0_rs1bypass[1]; // @[dec_decode_ctl.scala 780:6] - wire _T_963 = ~i0_rs1bypass[0]; // @[dec_decode_ctl.scala 780:25] - wire _T_964 = _T_961 & _T_963; // @[dec_decode_ctl.scala 780:23] - wire _T_965 = _T_964 & i0_rs1_nonblock_load_bypass_en_d; // @[dec_decode_ctl.scala 780:42] - wire [31:0] _T_967 = i0_rs1bypass[1] ? io_lsu_result_m : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_968 = i0_rs1bypass[0] ? i0_result_r_raw : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_969 = _T_965 ? io_dctl_busbuff_lsu_nonblock_load_data : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_970 = _T_967 | _T_968; // @[Mux.scala 27:72] - wire _T_978 = ~i0_rs2bypass[1]; // @[dec_decode_ctl.scala 785:6] - wire _T_980 = ~i0_rs2bypass[0]; // @[dec_decode_ctl.scala 785:25] - wire _T_981 = _T_978 & _T_980; // @[dec_decode_ctl.scala 785:23] - wire _T_982 = _T_981 & i0_rs2_nonblock_load_bypass_en_d; // @[dec_decode_ctl.scala 785:42] - wire [31:0] _T_984 = i0_rs2bypass[1] ? io_lsu_result_m : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_985 = i0_rs2bypass[0] ? i0_result_r_raw : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_986 = _T_982 ? io_dctl_busbuff_lsu_nonblock_load_data : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_987 = _T_984 | _T_985; // @[Mux.scala 27:72] - wire _T_990 = i0_dp_raw_load | i0_dp_raw_store; // @[dec_decode_ctl.scala 787:68] - wire _T_991 = io_dec_ib0_valid_d & _T_990; // @[dec_decode_ctl.scala 787:50] - wire _T_992 = ~io_dctl_dma_dma_dccm_stall_any; // @[dec_decode_ctl.scala 787:89] - wire _T_993 = _T_991 & _T_992; // @[dec_decode_ctl.scala 787:87] - wire _T_995 = _T_993 & _T_496; // @[dec_decode_ctl.scala 787:121] - wire _T_997 = ~io_decode_exu_dec_extint_stall; // @[dec_decode_ctl.scala 789:6] - wire _T_998 = _T_997 & i0_dp_lsu; // @[dec_decode_ctl.scala 789:38] - wire _T_999 = _T_998 & i0_dp_load; // @[dec_decode_ctl.scala 789:50] - wire _T_1004 = _T_998 & i0_dp_store; // @[dec_decode_ctl.scala 790:50] - wire [11:0] _T_1008 = {io_dec_i0_instr_d[31:25],i0r_rd}; // @[Cat.scala 29:58] - wire [11:0] _T_1009 = _T_999 ? io_dec_i0_instr_d[31:20] : 12'h0; // @[Mux.scala 27:72] - wire [11:0] _T_1010 = _T_1004 ? _T_1008 : 12'h0; // @[Mux.scala 27:72] + wire [31:0] _T_847 = {io_dec_alu_exu_i0_pc_x,1'h0}; // @[Cat.scala 29:58] + wire [12:0] _T_848 = {last_br_immed_x,1'h0}; // @[Cat.scala 29:58] + wire [12:0] _T_851 = _T_847[12:1] + _T_848[12:1]; // @[lib.scala 68:31] + wire [18:0] _T_854 = _T_847[31:13] + 19'h1; // @[lib.scala 69:27] + wire [18:0] _T_857 = _T_847[31:13] - 19'h1; // @[lib.scala 70:27] + wire _T_860 = ~_T_851[12]; // @[lib.scala 72:28] + wire _T_861 = _T_848[12] ^ _T_860; // @[lib.scala 72:26] + wire _T_864 = ~_T_848[12]; // @[lib.scala 73:20] + wire _T_866 = _T_864 & _T_851[12]; // @[lib.scala 73:26] + wire _T_870 = _T_848[12] & _T_860; // @[lib.scala 74:26] + wire [18:0] _T_872 = _T_861 ? _T_847[31:13] : 19'h0; // @[Mux.scala 27:72] + wire [18:0] _T_873 = _T_866 ? _T_854 : 19'h0; // @[Mux.scala 27:72] + wire [18:0] _T_874 = _T_870 ? _T_857 : 19'h0; // @[Mux.scala 27:72] + wire [18:0] _T_875 = _T_872 | _T_873; // @[Mux.scala 27:72] + wire [18:0] _T_876 = _T_875 | _T_874; // @[Mux.scala 27:72] + wire [31:0] temp_pred_correct_npc_x = {_T_876,_T_851[11:0],1'h0}; // @[Cat.scala 29:58] + wire _T_892_mul = i0_rs1_depend_i0_r & i0_r_c_mul; // @[dec_decode_ctl.scala 738:61] + wire _T_892_alu = i0_rs1_depend_i0_r & i0_r_c_alu; // @[dec_decode_ctl.scala 738:61] + wire i0_rs1_class_d_mul = i0_rs1_depend_i0_x ? i0_x_c_mul : _T_892_mul; // @[dec_decode_ctl.scala 738:24] + wire i0_rs1_class_d_alu = i0_rs1_depend_i0_x ? i0_x_c_alu : _T_892_alu; // @[dec_decode_ctl.scala 738:24] + wire _T_901_mul = i0_rs2_depend_i0_r & i0_r_c_mul; // @[dec_decode_ctl.scala 740:61] + wire _T_901_alu = i0_rs2_depend_i0_r & i0_r_c_alu; // @[dec_decode_ctl.scala 740:61] + wire i0_rs2_class_d_mul = i0_rs2_depend_i0_x ? i0_x_c_mul : _T_901_mul; // @[dec_decode_ctl.scala 740:24] + wire i0_rs2_class_d_alu = i0_rs2_depend_i0_x ? i0_x_c_alu : _T_901_alu; // @[dec_decode_ctl.scala 740:24] + wire _T_914 = io_decode_exu_dec_i0_rs1_en_d & io_dec_nonblock_load_wen; // @[dec_decode_ctl.scala 758:73] + wire _T_915 = io_dec_nonblock_load_waddr == i0r_rs1; // @[dec_decode_ctl.scala 758:130] + wire i0_rs1_nonblock_load_bypass_en_d = _T_914 & _T_915; // @[dec_decode_ctl.scala 758:100] + wire _T_916 = io_decode_exu_dec_i0_rs2_en_d & io_dec_nonblock_load_wen; // @[dec_decode_ctl.scala 760:73] + wire _T_917 = io_dec_nonblock_load_waddr == i0r_rs2; // @[dec_decode_ctl.scala 760:130] + wire i0_rs2_nonblock_load_bypass_en_d = _T_916 & _T_917; // @[dec_decode_ctl.scala 760:100] + wire _T_919 = i0_rs1_class_d_alu | i0_rs1_class_d_mul; // @[dec_decode_ctl.scala 763:66] + wire _T_920 = i0_rs1_depth_d[0] & _T_919; // @[dec_decode_ctl.scala 763:45] + wire _T_922 = i0_rs1_depth_d[0] & i0_rs1_class_d_load; // @[dec_decode_ctl.scala 763:108] + wire _T_925 = _T_919 | i0_rs1_class_d_load; // @[dec_decode_ctl.scala 763:196] + wire _T_926 = i0_rs1_depth_d[1] & _T_925; // @[dec_decode_ctl.scala 763:153] + wire [2:0] i0_rs1bypass = {_T_920,_T_922,_T_926}; // @[Cat.scala 29:58] + wire _T_930 = i0_rs2_class_d_alu | i0_rs2_class_d_mul; // @[dec_decode_ctl.scala 765:67] + wire _T_931 = i0_rs2_depth_d[0] & _T_930; // @[dec_decode_ctl.scala 765:45] + wire _T_933 = i0_rs2_depth_d[0] & i0_rs2_class_d_load; // @[dec_decode_ctl.scala 765:109] + wire _T_936 = _T_930 | i0_rs2_class_d_load; // @[dec_decode_ctl.scala 765:196] + wire _T_937 = i0_rs2_depth_d[1] & _T_936; // @[dec_decode_ctl.scala 765:153] + wire [2:0] i0_rs2bypass = {_T_931,_T_933,_T_937}; // @[Cat.scala 29:58] + wire _T_943 = i0_rs1bypass[1] | i0_rs1bypass[0]; // @[dec_decode_ctl.scala 767:86] + wire _T_945 = ~i0_rs1bypass[2]; // @[dec_decode_ctl.scala 767:107] + wire _T_946 = _T_945 & i0_rs1_nonblock_load_bypass_en_d; // @[dec_decode_ctl.scala 767:124] + wire _T_947 = _T_943 | _T_946; // @[dec_decode_ctl.scala 767:104] + wire _T_952 = i0_rs2bypass[1] | i0_rs2bypass[0]; // @[dec_decode_ctl.scala 768:86] + wire _T_954 = ~i0_rs2bypass[2]; // @[dec_decode_ctl.scala 768:107] + wire _T_955 = _T_954 & i0_rs2_nonblock_load_bypass_en_d; // @[dec_decode_ctl.scala 768:124] + wire _T_956 = _T_952 | _T_955; // @[dec_decode_ctl.scala 768:104] + wire _T_963 = ~i0_rs1bypass[1]; // @[dec_decode_ctl.scala 774:6] + wire _T_965 = ~i0_rs1bypass[0]; // @[dec_decode_ctl.scala 774:25] + wire _T_966 = _T_963 & _T_965; // @[dec_decode_ctl.scala 774:23] + wire _T_967 = _T_966 & i0_rs1_nonblock_load_bypass_en_d; // @[dec_decode_ctl.scala 774:42] + wire [31:0] _T_969 = i0_rs1bypass[1] ? io_lsu_result_m : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_970 = i0_rs1bypass[0] ? i0_result_r_raw : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_971 = _T_967 ? io_dctl_busbuff_lsu_nonblock_load_data : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_972 = _T_969 | _T_970; // @[Mux.scala 27:72] + wire _T_980 = ~i0_rs2bypass[1]; // @[dec_decode_ctl.scala 779:6] + wire _T_982 = ~i0_rs2bypass[0]; // @[dec_decode_ctl.scala 779:25] + wire _T_983 = _T_980 & _T_982; // @[dec_decode_ctl.scala 779:23] + wire _T_984 = _T_983 & i0_rs2_nonblock_load_bypass_en_d; // @[dec_decode_ctl.scala 779:42] + wire [31:0] _T_986 = i0_rs2bypass[1] ? io_lsu_result_m : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_987 = i0_rs2bypass[0] ? i0_result_r_raw : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_988 = _T_984 ? io_dctl_busbuff_lsu_nonblock_load_data : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_989 = _T_986 | _T_987; // @[Mux.scala 27:72] + wire _T_992 = i0_dp_raw_load | i0_dp_raw_store; // @[dec_decode_ctl.scala 781:68] + wire _T_993 = io_dec_ib0_valid_d & _T_992; // @[dec_decode_ctl.scala 781:50] + wire _T_994 = ~io_dctl_dma_dma_dccm_stall_any; // @[dec_decode_ctl.scala 781:89] + wire _T_995 = _T_993 & _T_994; // @[dec_decode_ctl.scala 781:87] + wire _T_997 = _T_995 & _T_496; // @[dec_decode_ctl.scala 781:121] + wire _T_999 = ~io_decode_exu_dec_extint_stall; // @[dec_decode_ctl.scala 783:6] + wire _T_1000 = _T_999 & i0_dp_lsu; // @[dec_decode_ctl.scala 783:38] + wire _T_1001 = _T_1000 & i0_dp_load; // @[dec_decode_ctl.scala 783:50] + wire _T_1006 = _T_1000 & i0_dp_store; // @[dec_decode_ctl.scala 784:50] + wire [11:0] _T_1010 = {io_dec_i0_instr_d[31:25],i0r_rd}; // @[Cat.scala 29:58] + wire [11:0] _T_1011 = _T_1001 ? io_dec_i0_instr_d[31:20] : 12'h0; // @[Mux.scala 27:72] + wire [11:0] _T_1012 = _T_1006 ? _T_1010 : 12'h0; // @[Mux.scala 27:72] rvclkhdr rvclkhdr ( // @[lib.scala 343:22] .io_l1clk(rvclkhdr_io_l1clk), .io_clk(rvclkhdr_io_clk), .io_en(rvclkhdr_io_en), .io_scan_mode(rvclkhdr_io_scan_mode) ); - dec_dec_ctl i0_dec ( // @[dec_decode_ctl.scala 362:22] + dec_dec_ctl i0_dec ( // @[dec_decode_ctl.scala 356:22] .io_ins(i0_dec_io_ins), .io_out_alu(i0_dec_io_out_alu), .io_out_rs1(i0_dec_io_out_rs1), @@ -47280,116 +47280,116 @@ module dec_decode_ctl( .io_en(rvclkhdr_19_io_en), .io_scan_mode(rvclkhdr_19_io_scan_mode) ); - assign io_decode_exu_dec_data_en = {i0_x_data_en,i0_r_data_en}; // @[dec_decode_ctl.scala 632:38] - assign io_decode_exu_dec_ctl_en = {i0_x_ctl_en,i0_r_ctl_en}; // @[dec_decode_ctl.scala 633:38] - assign io_decode_exu_i0_ap_land = _T_41 ? 1'h0 : i0_dp_raw_land; // @[dec_decode_ctl.scala 255:31] - assign io_decode_exu_i0_ap_lor = _T_41 | i0_dp_raw_lor; // @[dec_decode_ctl.scala 256:31] - assign io_decode_exu_i0_ap_lxor = _T_41 ? 1'h0 : i0_dp_raw_lxor; // @[dec_decode_ctl.scala 257:31] - assign io_decode_exu_i0_ap_sll = _T_41 ? 1'h0 : i0_dp_raw_sll; // @[dec_decode_ctl.scala 258:31] - assign io_decode_exu_i0_ap_srl = _T_41 ? 1'h0 : i0_dp_raw_srl; // @[dec_decode_ctl.scala 259:31] - assign io_decode_exu_i0_ap_sra = _T_41 ? 1'h0 : i0_dp_raw_sra; // @[dec_decode_ctl.scala 260:31] - assign io_decode_exu_i0_ap_beq = _T_41 ? 1'h0 : i0_dp_raw_beq; // @[dec_decode_ctl.scala 263:31] - assign io_decode_exu_i0_ap_bne = _T_41 ? 1'h0 : i0_dp_raw_bne; // @[dec_decode_ctl.scala 264:31] - assign io_decode_exu_i0_ap_blt = _T_41 ? 1'h0 : i0_dp_raw_blt; // @[dec_decode_ctl.scala 265:31] - assign io_decode_exu_i0_ap_bge = _T_41 ? 1'h0 : i0_dp_raw_bge; // @[dec_decode_ctl.scala 266:31] - assign io_decode_exu_i0_ap_add = _T_41 ? 1'h0 : i0_dp_raw_add; // @[dec_decode_ctl.scala 253:31] - assign io_decode_exu_i0_ap_sub = _T_41 ? 1'h0 : i0_dp_raw_sub; // @[dec_decode_ctl.scala 254:31] - assign io_decode_exu_i0_ap_slt = _T_41 ? 1'h0 : i0_dp_raw_slt; // @[dec_decode_ctl.scala 261:31] - assign io_decode_exu_i0_ap_unsign = _T_41 ? 1'h0 : i0_dp_raw_unsign; // @[dec_decode_ctl.scala 262:31] - assign io_decode_exu_i0_ap_jal = _T_336 & _T_337; // @[dec_decode_ctl.scala 269:33] - assign io_decode_exu_i0_ap_predict_t = _T_47 & i0_predict_br; // @[dec_decode_ctl.scala 251:37] - assign io_decode_exu_i0_ap_predict_nt = _T_48 & i0_predict_br; // @[dec_decode_ctl.scala 250:37] - assign io_decode_exu_i0_ap_csr_write = i0_csr_write & _T_347; // @[dec_decode_ctl.scala 267:33] - assign io_decode_exu_i0_ap_csr_imm = _T_41 ? 1'h0 : i0_dp_raw_csr_imm; // @[dec_decode_ctl.scala 268:33] - assign io_decode_exu_dec_i0_predict_p_d_valid = i0_brp_valid & i0_legal_decode_d; // @[dec_decode_ctl.scala 206:49] - assign io_decode_exu_dec_i0_predict_p_d_bits_pc4 = io_dec_i0_pc4_d; // @[dec_decode_ctl.scala 204:54] - assign io_decode_exu_dec_i0_predict_p_d_bits_hist = io_dec_i0_brp_bits_hist; // @[dec_decode_ctl.scala 205:54] - assign io_decode_exu_dec_i0_predict_p_d_bits_toffset = _T_314 ? i0_pcall_imm[11:0] : _T_323; // @[dec_decode_ctl.scala 218:60] - assign io_decode_exu_dec_i0_predict_p_d_bits_br_error = _T_33 & _T_18; // @[dec_decode_ctl.scala 213:67] - assign io_decode_exu_dec_i0_predict_p_d_bits_br_start_error = _T_36 & _T_18; // @[dec_decode_ctl.scala 214:67] - assign io_decode_exu_dec_i0_predict_p_d_bits_prett = io_dec_i0_brp_bits_prett; // @[dec_decode_ctl.scala 203:54] - assign io_decode_exu_dec_i0_predict_p_d_bits_pcall = i0_dp_jal & i0_pcall_case; // @[dec_decode_ctl.scala 200:54] - assign io_decode_exu_dec_i0_predict_p_d_bits_pret = i0_dp_jal & i0_pret_case; // @[dec_decode_ctl.scala 202:54] - assign io_decode_exu_dec_i0_predict_p_d_bits_pja = i0_dp_jal & i0_pja_case; // @[dec_decode_ctl.scala 201:54] - assign io_decode_exu_dec_i0_predict_p_d_bits_way = io_dec_i0_brp_bits_way; // @[dec_decode_ctl.scala 220:67] - assign io_decode_exu_i0_predict_fghr_d = io_dec_i0_bp_fghr; // @[dec_decode_ctl.scala 219:43] - assign io_decode_exu_i0_predict_index_d = io_dec_i0_bp_index; // @[dec_decode_ctl.scala 215:43] - assign io_decode_exu_i0_predict_btag_d = io_dec_i0_bp_btag; // @[dec_decode_ctl.scala 216:43] - assign io_decode_exu_dec_i0_rs1_en_d = i0_dp_rs1 & _T_559; // @[dec_decode_ctl.scala 594:35] - assign io_decode_exu_dec_i0_rs2_en_d = i0_dp_rs2 & _T_561; // @[dec_decode_ctl.scala 595:35] - assign io_decode_exu_dec_i0_immed_d = _T_566 | _T_567; // @[dec_decode_ctl.scala 603:32] - assign io_decode_exu_dec_i0_rs1_bypass_data_d = _T_970 | _T_969; // @[dec_decode_ctl.scala 777:42] - assign io_decode_exu_dec_i0_rs2_bypass_data_d = _T_987 | _T_986; // @[dec_decode_ctl.scala 782:42] - assign io_decode_exu_dec_i0_select_pc_d = _T_41 ? 1'h0 : i0_dp_raw_pc; // @[dec_decode_ctl.scala 241:36] - assign io_decode_exu_dec_i0_rs1_bypass_en_d = {i0_rs1bypass[2],_T_945}; // @[dec_decode_ctl.scala 773:45] - assign io_decode_exu_dec_i0_rs2_bypass_en_d = {i0_rs2bypass[2],_T_954}; // @[dec_decode_ctl.scala 774:45] - assign io_decode_exu_mul_p_valid = i0_exulegal_decode_d & i0_dp_mul; // @[dec_decode_ctl.scala 97:23 dec_decode_ctl.scala 397:32] - assign io_decode_exu_mul_p_bits_rs1_sign = _T_41 ? 1'h0 : i0_dp_raw_rs1_sign; // @[dec_decode_ctl.scala 97:23 dec_decode_ctl.scala 398:37] - assign io_decode_exu_mul_p_bits_rs2_sign = _T_41 ? 1'h0 : i0_dp_raw_rs2_sign; // @[dec_decode_ctl.scala 97:23 dec_decode_ctl.scala 399:37] - assign io_decode_exu_mul_p_bits_low = _T_41 ? 1'h0 : i0_dp_raw_low; // @[dec_decode_ctl.scala 97:23 dec_decode_ctl.scala 400:37] - assign io_decode_exu_pred_correct_npc_x = temp_pred_correct_npc_x[31:1]; // @[dec_decode_ctl.scala 734:36] - assign io_decode_exu_dec_extint_stall = _T_339; // @[dec_decode_ctl.scala 402:34] - assign io_dec_alu_dec_i0_alu_decode_d = i0_exulegal_decode_d & i0_dp_alu; // @[dec_decode_ctl.scala 542:34] - assign io_dec_alu_dec_csr_ren_d = _T_41 ? 1'h0 : i0_dp_raw_csr_read; // @[dec_decode_ctl.scala 424:29] - assign io_dec_alu_dec_i0_br_immed_d = _T_771 ? i0_br_offset : _T_784; // @[dec_decode_ctl.scala 681:32] - assign io_dec_div_div_p_valid = i0_exulegal_decode_d & i0_dp_div; // @[dec_decode_ctl.scala 393:29] - assign io_dec_div_div_p_bits_unsign = _T_41 ? 1'h0 : i0_dp_raw_unsign; // @[dec_decode_ctl.scala 394:34] - assign io_dec_div_div_p_bits_rem = _T_41 ? 1'h0 : i0_dp_raw_rem; // @[dec_decode_ctl.scala 395:34] - assign io_dec_div_dec_div_cancel = _T_813 | _T_818; // @[dec_decode_ctl.scala 700:37] - assign io_dec_i0_inst_wb1 = _T_840; // @[dec_decode_ctl.scala 723:22] - assign io_dec_i0_pc_wb1 = _T_843; // @[dec_decode_ctl.scala 726:20] - assign io_dec_i0_rs1_d = io_dec_i0_instr_d[19:15]; // @[dec_decode_ctl.scala 597:19] - assign io_dec_i0_rs2_d = io_dec_i0_instr_d[24:20]; // @[dec_decode_ctl.scala 598:19] - assign io_dec_i0_waddr_r = r_d_bits_i0rd; // @[dec_decode_ctl.scala 664:27] - assign io_dec_i0_wen_r = _T_760 & _T_761; // @[dec_decode_ctl.scala 666:32] - assign io_dec_i0_wdata_r = _T_767 ? io_lsu_result_corr_r : i0_result_r_raw; // @[dec_decode_ctl.scala 667:26] - assign io_lsu_p_valid = io_decode_exu_dec_extint_stall | lsu_decode_d; // @[dec_decode_ctl.scala 404:12 dec_decode_ctl.scala 409:24 dec_decode_ctl.scala 411:35] - assign io_lsu_p_bits_fast_int = io_decode_exu_dec_extint_stall; // @[dec_decode_ctl.scala 404:12 dec_decode_ctl.scala 408:29] - assign io_lsu_p_bits_by = io_decode_exu_dec_extint_stall ? 1'h0 : i0_dp_by; // @[dec_decode_ctl.scala 404:12 dec_decode_ctl.scala 414:40] - assign io_lsu_p_bits_half = io_decode_exu_dec_extint_stall ? 1'h0 : i0_dp_half; // @[dec_decode_ctl.scala 404:12 dec_decode_ctl.scala 415:40] - assign io_lsu_p_bits_word = io_decode_exu_dec_extint_stall | i0_dp_word; // @[dec_decode_ctl.scala 404:12 dec_decode_ctl.scala 407:29 dec_decode_ctl.scala 416:40] - assign io_lsu_p_bits_load = io_decode_exu_dec_extint_stall | i0_dp_load; // @[dec_decode_ctl.scala 404:12 dec_decode_ctl.scala 406:29 dec_decode_ctl.scala 412:40] - assign io_lsu_p_bits_store = io_decode_exu_dec_extint_stall ? 1'h0 : i0_dp_store; // @[dec_decode_ctl.scala 404:12 dec_decode_ctl.scala 413:40] - assign io_lsu_p_bits_unsign = io_decode_exu_dec_extint_stall ? 1'h0 : i0_dp_unsign; // @[dec_decode_ctl.scala 404:12 dec_decode_ctl.scala 420:40] - assign io_lsu_p_bits_store_data_bypass_d = io_decode_exu_dec_extint_stall ? 1'h0 : store_data_bypass_d; // @[dec_decode_ctl.scala 404:12 dec_decode_ctl.scala 418:40] - assign io_lsu_p_bits_load_ldst_bypass_d = io_decode_exu_dec_extint_stall ? 1'h0 : load_ldst_bypass_d; // @[dec_decode_ctl.scala 404:12 dec_decode_ctl.scala 417:40] - assign io_div_waddr_wb = _T_833; // @[dec_decode_ctl.scala 711:19] - assign io_dec_lsu_valid_raw_d = _T_995 | io_decode_exu_dec_extint_stall; // @[dec_decode_ctl.scala 787:26] - assign io_dec_lsu_offset_d = _T_1009 | _T_1010; // @[dec_decode_ctl.scala 788:23] - assign io_dec_csr_wen_unq_d = _T_349 | i0_csr_write; // @[dec_decode_ctl.scala 433:24] - assign io_dec_csr_any_unq_d = i0_dp_csr_read | i0_csr_write; // @[dec_decode_ctl.scala 499:24] - assign io_dec_csr_rdaddr_d = io_dec_i0_instr_d[31:20]; // @[dec_decode_ctl.scala 436:24] - assign io_dec_csr_wen_r = _T_352 & _T_757; // @[dec_decode_ctl.scala 441:20] - assign io_dec_csr_wraddr_r = r_d_bits_csrwaddr; // @[dec_decode_ctl.scala 437:23] - assign io_dec_csr_wrdata_r = r_d_bits_csrwonly ? i0_result_corr_r : write_csr_data; // @[dec_decode_ctl.scala 484:24] - assign io_dec_csr_stall_int_ff = _T_359 & _T_360; // @[dec_decode_ctl.scala 444:27] - assign io_dec_tlu_i0_valid_r = r_d_valid & _T_746; // @[dec_decode_ctl.scala 548:29] - assign io_dec_tlu_packet_r_legal = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_legal; // @[dec_decode_ctl.scala 582:39] - assign io_dec_tlu_packet_r_icaf = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_icaf; // @[dec_decode_ctl.scala 582:39] - assign io_dec_tlu_packet_r_icaf_f1 = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_icaf_f1; // @[dec_decode_ctl.scala 582:39] - assign io_dec_tlu_packet_r_icaf_type = io_dec_tlu_flush_lower_wb ? 2'h0 : r_t_icaf_type; // @[dec_decode_ctl.scala 582:39] - assign io_dec_tlu_packet_r_fence_i = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_fence_i; // @[dec_decode_ctl.scala 582:39] - assign io_dec_tlu_packet_r_i0trigger = io_dec_tlu_flush_lower_wb ? 4'h0 : _T_545; // @[dec_decode_ctl.scala 582:39] - assign io_dec_tlu_packet_r_pmu_i0_itype = io_dec_tlu_flush_lower_wb ? 4'h0 : r_t_pmu_i0_itype; // @[dec_decode_ctl.scala 582:39] - assign io_dec_tlu_packet_r_pmu_i0_br_unpred = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_pmu_i0_br_unpred; // @[dec_decode_ctl.scala 582:39] - assign io_dec_tlu_packet_r_pmu_divide = r_d_bits_i0div & r_d_valid; // @[dec_decode_ctl.scala 582:39 dec_decode_ctl.scala 583:39] - assign io_dec_tlu_packet_r_pmu_lsu_misaligned = io_dec_tlu_flush_lower_wb ? 1'h0 : lsu_pmu_misaligned_r; // @[dec_decode_ctl.scala 582:39] - assign io_dec_tlu_i0_pc_r = dec_i0_pc_r; // @[dec_decode_ctl.scala 729:27] - assign io_dec_illegal_inst = _T_468; // @[dec_decode_ctl.scala 506:23] - assign io_dec_pmu_instr_decoded = io_dec_aln_dec_i0_decode_d; // @[dec_decode_ctl.scala 527:28] - assign io_dec_pmu_decode_stall = io_dec_ib0_valid_d & _T_501; // @[dec_decode_ctl.scala 528:27] - assign io_dec_pmu_presync_stall = i0_presync & prior_inflight_eff; // @[dec_decode_ctl.scala 530:29] - assign io_dec_pmu_postsync_stall = postsync_stall; // @[dec_decode_ctl.scala 529:29] - assign io_dec_nonblock_load_wen = _T_200 & _T_201; // @[dec_decode_ctl.scala 324:28] - assign io_dec_nonblock_load_waddr = _T_246 | _T_238; // @[dec_decode_ctl.scala 321:29 dec_decode_ctl.scala 331:29] - assign io_dec_pause_state = pause_stall; // @[dec_decode_ctl.scala 468:22] - assign io_dec_pause_state_cg = pause_stall & _T_423; // @[dec_decode_ctl.scala 472:25] - assign io_dec_div_active = _T_824; // @[dec_decode_ctl.scala 705:21] - assign io_dec_aln_dec_i0_decode_d = _T_493 & _T_470; // @[dec_decode_ctl.scala 522:30 dec_decode_ctl.scala 588:30] + assign io_decode_exu_dec_data_en = {i0_x_data_en,i0_r_data_en}; // @[dec_decode_ctl.scala 626:38] + assign io_decode_exu_dec_ctl_en = {i0_x_ctl_en,i0_r_ctl_en}; // @[dec_decode_ctl.scala 627:38] + assign io_decode_exu_i0_ap_land = _T_41 ? 1'h0 : i0_dp_raw_land; // @[dec_decode_ctl.scala 249:37] + assign io_decode_exu_i0_ap_lor = _T_41 | i0_dp_raw_lor; // @[dec_decode_ctl.scala 250:37] + assign io_decode_exu_i0_ap_lxor = _T_41 ? 1'h0 : i0_dp_raw_lxor; // @[dec_decode_ctl.scala 251:37] + assign io_decode_exu_i0_ap_sll = _T_41 ? 1'h0 : i0_dp_raw_sll; // @[dec_decode_ctl.scala 252:37] + assign io_decode_exu_i0_ap_srl = _T_41 ? 1'h0 : i0_dp_raw_srl; // @[dec_decode_ctl.scala 253:37] + assign io_decode_exu_i0_ap_sra = _T_41 ? 1'h0 : i0_dp_raw_sra; // @[dec_decode_ctl.scala 254:37] + assign io_decode_exu_i0_ap_beq = _T_41 ? 1'h0 : i0_dp_raw_beq; // @[dec_decode_ctl.scala 257:37] + assign io_decode_exu_i0_ap_bne = _T_41 ? 1'h0 : i0_dp_raw_bne; // @[dec_decode_ctl.scala 258:37] + assign io_decode_exu_i0_ap_blt = _T_41 ? 1'h0 : i0_dp_raw_blt; // @[dec_decode_ctl.scala 259:37] + assign io_decode_exu_i0_ap_bge = _T_41 ? 1'h0 : i0_dp_raw_bge; // @[dec_decode_ctl.scala 260:37] + assign io_decode_exu_i0_ap_add = _T_41 ? 1'h0 : i0_dp_raw_add; // @[dec_decode_ctl.scala 247:37] + assign io_decode_exu_i0_ap_sub = _T_41 ? 1'h0 : i0_dp_raw_sub; // @[dec_decode_ctl.scala 248:37] + assign io_decode_exu_i0_ap_slt = _T_41 ? 1'h0 : i0_dp_raw_slt; // @[dec_decode_ctl.scala 255:37] + assign io_decode_exu_i0_ap_unsign = _T_41 ? 1'h0 : i0_dp_raw_unsign; // @[dec_decode_ctl.scala 256:37] + assign io_decode_exu_i0_ap_jal = _T_336 & _T_337; // @[dec_decode_ctl.scala 263:37] + assign io_decode_exu_i0_ap_predict_t = _T_47 & i0_predict_br; // @[dec_decode_ctl.scala 245:37] + assign io_decode_exu_i0_ap_predict_nt = _T_48 & i0_predict_br; // @[dec_decode_ctl.scala 244:37] + assign io_decode_exu_i0_ap_csr_write = i0_csr_write & _T_347; // @[dec_decode_ctl.scala 261:37] + assign io_decode_exu_i0_ap_csr_imm = _T_41 ? 1'h0 : i0_dp_raw_csr_imm; // @[dec_decode_ctl.scala 262:37] + assign io_decode_exu_dec_i0_predict_p_d_valid = i0_brp_valid & i0_legal_decode_d; // @[dec_decode_ctl.scala 202:55] + assign io_decode_exu_dec_i0_predict_p_d_bits_pc4 = io_dec_i0_pc4_d; // @[dec_decode_ctl.scala 200:55] + assign io_decode_exu_dec_i0_predict_p_d_bits_hist = io_dec_i0_brp_bits_hist; // @[dec_decode_ctl.scala 201:55] + assign io_decode_exu_dec_i0_predict_p_d_bits_toffset = _T_314 ? i0_pcall_imm[11:0] : _T_323; // @[dec_decode_ctl.scala 214:56] + assign io_decode_exu_dec_i0_predict_p_d_bits_br_error = _T_33 & _T_18; // @[dec_decode_ctl.scala 209:56] + assign io_decode_exu_dec_i0_predict_p_d_bits_br_start_error = _T_36 & _T_18; // @[dec_decode_ctl.scala 210:56] + assign io_decode_exu_dec_i0_predict_p_d_bits_prett = io_dec_i0_brp_bits_prett; // @[dec_decode_ctl.scala 199:55] + assign io_decode_exu_dec_i0_predict_p_d_bits_pcall = i0_dp_jal & i0_pcall_case; // @[dec_decode_ctl.scala 196:55] + assign io_decode_exu_dec_i0_predict_p_d_bits_pret = i0_dp_jal & i0_pret_case; // @[dec_decode_ctl.scala 198:55] + assign io_decode_exu_dec_i0_predict_p_d_bits_pja = i0_dp_jal & i0_pja_case; // @[dec_decode_ctl.scala 197:55] + assign io_decode_exu_dec_i0_predict_p_d_bits_way = io_dec_i0_brp_bits_way; // @[dec_decode_ctl.scala 216:56] + assign io_decode_exu_i0_predict_fghr_d = io_dec_i0_bp_fghr; // @[dec_decode_ctl.scala 215:56] + assign io_decode_exu_i0_predict_index_d = io_dec_i0_bp_index; // @[dec_decode_ctl.scala 211:56] + assign io_decode_exu_i0_predict_btag_d = io_dec_i0_bp_btag; // @[dec_decode_ctl.scala 212:56] + assign io_decode_exu_dec_i0_rs1_en_d = i0_dp_rs1 & _T_559; // @[dec_decode_ctl.scala 588:35] + assign io_decode_exu_dec_i0_rs2_en_d = i0_dp_rs2 & _T_561; // @[dec_decode_ctl.scala 589:35] + assign io_decode_exu_dec_i0_immed_d = _T_566 | _T_567; // @[dec_decode_ctl.scala 597:32] + assign io_decode_exu_dec_i0_rs1_bypass_data_d = _T_972 | _T_971; // @[dec_decode_ctl.scala 771:42] + assign io_decode_exu_dec_i0_rs2_bypass_data_d = _T_989 | _T_988; // @[dec_decode_ctl.scala 776:42] + assign io_decode_exu_dec_i0_select_pc_d = _T_41 ? 1'h0 : i0_dp_raw_pc; // @[dec_decode_ctl.scala 236:36] + assign io_decode_exu_dec_i0_rs1_bypass_en_d = {i0_rs1bypass[2],_T_947}; // @[dec_decode_ctl.scala 767:45] + assign io_decode_exu_dec_i0_rs2_bypass_en_d = {i0_rs2bypass[2],_T_956}; // @[dec_decode_ctl.scala 768:45] + assign io_decode_exu_mul_p_valid = i0_exulegal_decode_d & i0_dp_mul; // @[dec_decode_ctl.scala 95:25 dec_decode_ctl.scala 391:32] + assign io_decode_exu_mul_p_bits_rs1_sign = _T_41 ? 1'h0 : i0_dp_raw_rs1_sign; // @[dec_decode_ctl.scala 95:25 dec_decode_ctl.scala 392:37] + assign io_decode_exu_mul_p_bits_rs2_sign = _T_41 ? 1'h0 : i0_dp_raw_rs2_sign; // @[dec_decode_ctl.scala 95:25 dec_decode_ctl.scala 393:37] + assign io_decode_exu_mul_p_bits_low = _T_41 ? 1'h0 : i0_dp_raw_low; // @[dec_decode_ctl.scala 95:25 dec_decode_ctl.scala 394:37] + assign io_decode_exu_pred_correct_npc_x = temp_pred_correct_npc_x[31:1]; // @[dec_decode_ctl.scala 728:36] + assign io_decode_exu_dec_extint_stall = _T_339; // @[dec_decode_ctl.scala 396:34] + assign io_dec_alu_dec_i0_alu_decode_d = i0_exulegal_decode_d & i0_dp_alu; // @[dec_decode_ctl.scala 536:34] + assign io_dec_alu_dec_csr_ren_d = _T_41 ? 1'h0 : i0_dp_raw_csr_read; // @[dec_decode_ctl.scala 418:29] + assign io_dec_alu_dec_i0_br_immed_d = _T_773 ? i0_br_offset : _T_786; // @[dec_decode_ctl.scala 675:32] + assign io_dec_div_div_p_valid = i0_exulegal_decode_d & i0_dp_div; // @[dec_decode_ctl.scala 387:29] + assign io_dec_div_div_p_bits_unsign = _T_41 ? 1'h0 : i0_dp_raw_unsign; // @[dec_decode_ctl.scala 388:34] + assign io_dec_div_div_p_bits_rem = _T_41 ? 1'h0 : i0_dp_raw_rem; // @[dec_decode_ctl.scala 389:34] + assign io_dec_div_dec_div_cancel = _T_815 | _T_820; // @[dec_decode_ctl.scala 694:37] + assign io_dec_aln_dec_i0_decode_d = _T_493 & _T_470; // @[dec_decode_ctl.scala 516:30 dec_decode_ctl.scala 582:30] + assign io_dec_i0_inst_wb1 = _T_842; // @[dec_decode_ctl.scala 717:22] + assign io_dec_i0_pc_wb1 = _T_845; // @[dec_decode_ctl.scala 720:20] + assign io_dec_i0_rs1_d = io_dec_i0_instr_d[19:15]; // @[dec_decode_ctl.scala 591:19] + assign io_dec_i0_rs2_d = io_dec_i0_instr_d[24:20]; // @[dec_decode_ctl.scala 592:19] + assign io_dec_i0_waddr_r = r_d_bits_i0rd; // @[dec_decode_ctl.scala 658:27] + assign io_dec_i0_wen_r = _T_762 & _T_763; // @[dec_decode_ctl.scala 660:32] + assign io_dec_i0_wdata_r = _T_769 ? io_lsu_result_corr_r : i0_result_r_raw; // @[dec_decode_ctl.scala 661:26] + assign io_lsu_p_valid = io_decode_exu_dec_extint_stall | lsu_decode_d; // @[dec_decode_ctl.scala 398:12 dec_decode_ctl.scala 403:24 dec_decode_ctl.scala 405:35] + assign io_lsu_p_bits_fast_int = io_decode_exu_dec_extint_stall; // @[dec_decode_ctl.scala 398:12 dec_decode_ctl.scala 402:29] + assign io_lsu_p_bits_by = io_decode_exu_dec_extint_stall ? 1'h0 : i0_dp_by; // @[dec_decode_ctl.scala 398:12 dec_decode_ctl.scala 408:40] + assign io_lsu_p_bits_half = io_decode_exu_dec_extint_stall ? 1'h0 : i0_dp_half; // @[dec_decode_ctl.scala 398:12 dec_decode_ctl.scala 409:40] + assign io_lsu_p_bits_word = io_decode_exu_dec_extint_stall | i0_dp_word; // @[dec_decode_ctl.scala 398:12 dec_decode_ctl.scala 401:29 dec_decode_ctl.scala 410:40] + assign io_lsu_p_bits_load = io_decode_exu_dec_extint_stall | i0_dp_load; // @[dec_decode_ctl.scala 398:12 dec_decode_ctl.scala 400:29 dec_decode_ctl.scala 406:40] + assign io_lsu_p_bits_store = io_decode_exu_dec_extint_stall ? 1'h0 : i0_dp_store; // @[dec_decode_ctl.scala 398:12 dec_decode_ctl.scala 407:40] + assign io_lsu_p_bits_unsign = io_decode_exu_dec_extint_stall ? 1'h0 : i0_dp_unsign; // @[dec_decode_ctl.scala 398:12 dec_decode_ctl.scala 414:40] + assign io_lsu_p_bits_store_data_bypass_d = io_decode_exu_dec_extint_stall ? 1'h0 : store_data_bypass_d; // @[dec_decode_ctl.scala 398:12 dec_decode_ctl.scala 412:40] + assign io_lsu_p_bits_load_ldst_bypass_d = io_decode_exu_dec_extint_stall ? 1'h0 : load_ldst_bypass_d; // @[dec_decode_ctl.scala 398:12 dec_decode_ctl.scala 411:40] + assign io_div_waddr_wb = _T_835; // @[dec_decode_ctl.scala 705:19] + assign io_dec_lsu_valid_raw_d = _T_997 | io_decode_exu_dec_extint_stall; // @[dec_decode_ctl.scala 781:26] + assign io_dec_lsu_offset_d = _T_1011 | _T_1012; // @[dec_decode_ctl.scala 782:23] + assign io_dec_csr_wen_unq_d = _T_349 | i0_csr_write; // @[dec_decode_ctl.scala 427:24] + assign io_dec_csr_any_unq_d = i0_dp_csr_read | i0_csr_write; // @[dec_decode_ctl.scala 493:24] + assign io_dec_csr_rdaddr_d = io_dec_i0_instr_d[31:20]; // @[dec_decode_ctl.scala 430:24] + assign io_dec_csr_wen_r = _T_352 & _T_759; // @[dec_decode_ctl.scala 435:20] + assign io_dec_csr_wraddr_r = r_d_bits_csrwaddr; // @[dec_decode_ctl.scala 431:23] + assign io_dec_csr_wrdata_r = r_d_bits_csrwonly ? i0_result_corr_r : write_csr_data; // @[dec_decode_ctl.scala 478:24] + assign io_dec_csr_stall_int_ff = _T_359 & _T_360; // @[dec_decode_ctl.scala 438:27] + assign io_dec_tlu_i0_valid_r = r_d_valid & _T_748; // @[dec_decode_ctl.scala 542:29] + assign io_dec_tlu_packet_r_legal = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_legal; // @[dec_decode_ctl.scala 576:39] + assign io_dec_tlu_packet_r_icaf = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_icaf; // @[dec_decode_ctl.scala 576:39] + assign io_dec_tlu_packet_r_icaf_f1 = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_icaf_f1; // @[dec_decode_ctl.scala 576:39] + assign io_dec_tlu_packet_r_icaf_type = io_dec_tlu_flush_lower_wb ? 2'h0 : r_t_icaf_type; // @[dec_decode_ctl.scala 576:39] + assign io_dec_tlu_packet_r_fence_i = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_fence_i; // @[dec_decode_ctl.scala 576:39] + assign io_dec_tlu_packet_r_i0trigger = io_dec_tlu_flush_lower_wb ? 4'h0 : _T_545; // @[dec_decode_ctl.scala 576:39] + assign io_dec_tlu_packet_r_pmu_i0_itype = io_dec_tlu_flush_lower_wb ? 4'h0 : r_t_pmu_i0_itype; // @[dec_decode_ctl.scala 576:39] + assign io_dec_tlu_packet_r_pmu_i0_br_unpred = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_pmu_i0_br_unpred; // @[dec_decode_ctl.scala 576:39] + assign io_dec_tlu_packet_r_pmu_divide = r_d_bits_i0div & r_d_valid; // @[dec_decode_ctl.scala 576:39 dec_decode_ctl.scala 577:39] + assign io_dec_tlu_packet_r_pmu_lsu_misaligned = io_dec_tlu_flush_lower_wb ? 1'h0 : lsu_pmu_misaligned_r; // @[dec_decode_ctl.scala 576:39] + assign io_dec_tlu_i0_pc_r = dec_i0_pc_r; // @[dec_decode_ctl.scala 723:27] + assign io_dec_illegal_inst = _T_468; // @[dec_decode_ctl.scala 500:23] + assign io_dec_pmu_instr_decoded = io_dec_aln_dec_i0_decode_d; // @[dec_decode_ctl.scala 521:28] + assign io_dec_pmu_decode_stall = io_dec_ib0_valid_d & _T_501; // @[dec_decode_ctl.scala 522:27] + assign io_dec_pmu_presync_stall = i0_presync & prior_inflight_eff; // @[dec_decode_ctl.scala 524:29] + assign io_dec_pmu_postsync_stall = postsync_stall; // @[dec_decode_ctl.scala 523:29] + assign io_dec_nonblock_load_wen = _T_200 & _T_201; // @[dec_decode_ctl.scala 318:28] + assign io_dec_nonblock_load_waddr = _T_246 | _T_238; // @[dec_decode_ctl.scala 315:29 dec_decode_ctl.scala 325:29] + assign io_dec_pause_state = pause_stall; // @[dec_decode_ctl.scala 462:22] + assign io_dec_pause_state_cg = pause_stall & _T_423; // @[dec_decode_ctl.scala 466:25] + assign io_dec_div_active = _T_826; // @[dec_decode_ctl.scala 699:21] assign rvclkhdr_io_clk = clock; // @[lib.scala 344:17] assign rvclkhdr_io_en = _T_15 | _T_16; // @[lib.scala 345:16] assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] - assign i0_dec_io_ins = io_dec_i0_instr_d; // @[dec_decode_ctl.scala 363:16] + assign i0_dec_io_ins = io_dec_i0_instr_d; // @[dec_decode_ctl.scala 357:16] assign rvclkhdr_1_io_clk = clock; // @[lib.scala 370:18] assign rvclkhdr_1_io_en = i0_pipe_en[3] | io_clk_override; // @[lib.scala 371:17] assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] @@ -47403,19 +47403,19 @@ module dec_decode_ctl( assign rvclkhdr_4_io_en = shift_illegal & _T_467; // @[lib.scala 371:17] assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_5_io_clk = clock; // @[lib.scala 380:18] - assign rvclkhdr_5_io_en = _T_707 | io_clk_override; // @[lib.scala 381:17] + assign rvclkhdr_5_io_en = _T_709 | io_clk_override; // @[lib.scala 381:17] assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[lib.scala 382:24] assign rvclkhdr_6_io_clk = clock; // @[lib.scala 380:18] - assign rvclkhdr_6_io_en = _T_707 | io_clk_override; // @[lib.scala 381:17] + assign rvclkhdr_6_io_en = _T_709 | io_clk_override; // @[lib.scala 381:17] assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[lib.scala 382:24] assign rvclkhdr_7_io_clk = clock; // @[lib.scala 380:18] - assign rvclkhdr_7_io_en = _T_707 | io_clk_override; // @[lib.scala 381:17] + assign rvclkhdr_7_io_en = _T_709 | io_clk_override; // @[lib.scala 381:17] assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[lib.scala 382:24] assign rvclkhdr_8_io_clk = clock; // @[lib.scala 380:18] - assign rvclkhdr_8_io_en = _T_710 | io_clk_override; // @[lib.scala 381:17] + assign rvclkhdr_8_io_en = _T_712 | io_clk_override; // @[lib.scala 381:17] assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[lib.scala 382:24] assign rvclkhdr_9_io_clk = clock; // @[lib.scala 380:18] - assign rvclkhdr_9_io_en = _T_713 | io_clk_override; // @[lib.scala 381:17] + assign rvclkhdr_9_io_en = _T_715 | io_clk_override; // @[lib.scala 381:17] assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[lib.scala 382:24] assign rvclkhdr_10_io_clk = clock; // @[lib.scala 370:18] assign rvclkhdr_10_io_en = i0_pipe_en[2] | io_clk_override; // @[lib.scala 371:17] @@ -47523,7 +47523,7 @@ initial begin _RAND_19 = {1{`RANDOM}}; x_d_bits_i0rd = _RAND_19[4:0]; _RAND_20 = {1{`RANDOM}}; - _T_704 = _RAND_20[2:0]; + _T_706 = _RAND_20[2:0]; _RAND_21 = {1{`RANDOM}}; nonblock_load_valid_m_delay = _RAND_21[0:0]; _RAND_22 = {1{`RANDOM}}; @@ -47647,9 +47647,9 @@ initial begin _RAND_81 = {1{`RANDOM}}; last_br_immed_x = _RAND_81[11:0]; _RAND_82 = {1{`RANDOM}}; - _T_824 = _RAND_82[0:0]; + _T_826 = _RAND_82[0:0]; _RAND_83 = {1{`RANDOM}}; - _T_833 = _RAND_83[4:0]; + _T_835 = _RAND_83[4:0]; _RAND_84 = {1{`RANDOM}}; i0_inst_x = _RAND_84[31:0]; _RAND_85 = {1{`RANDOM}}; @@ -47657,11 +47657,11 @@ initial begin _RAND_86 = {1{`RANDOM}}; i0_inst_wb = _RAND_86[31:0]; _RAND_87 = {1{`RANDOM}}; - _T_840 = _RAND_87[31:0]; + _T_842 = _RAND_87[31:0]; _RAND_88 = {1{`RANDOM}}; i0_pc_wb = _RAND_88[30:0]; _RAND_89 = {1{`RANDOM}}; - _T_843 = _RAND_89[30:0]; + _T_845 = _RAND_89[30:0]; _RAND_90 = {1{`RANDOM}}; dec_i0_pc_r = _RAND_90[30:0]; `endif // RANDOMIZE_REG_INIT @@ -47726,7 +47726,7 @@ initial begin x_d_bits_i0rd = 5'h0; end if (reset) begin - _T_704 = 3'h0; + _T_706 = 3'h0; end if (reset) begin nonblock_load_valid_m_delay = 1'h0; @@ -47773,6 +47773,12 @@ initial begin if (reset) begin x_d_bits_i0v = 1'h0; end + if (reset) begin + i0_x_c_load = 1'h0; + end + if (reset) begin + i0_r_c_load = 1'h0; + end if (reset) begin r_d_bits_csrwen = 1'h0; end @@ -47878,6 +47884,18 @@ initial begin if (reset) begin r_d_bits_i0div = 1'h0; end + if (reset) begin + i0_x_c_mul = 1'h0; + end + if (reset) begin + i0_x_c_alu = 1'h0; + end + if (reset) begin + i0_r_c_mul = 1'h0; + end + if (reset) begin + i0_r_c_alu = 1'h0; + end if (reset) begin x_d_bits_i0store = 1'h0; end @@ -47894,10 +47912,10 @@ initial begin last_br_immed_x = 12'h0; end if (reset) begin - _T_824 = 1'h0; + _T_826 = 1'h0; end if (reset) begin - _T_833 = 5'h0; + _T_835 = 5'h0; end if (reset) begin i0_inst_x = 32'h0; @@ -47909,13 +47927,13 @@ initial begin i0_inst_wb = 32'h0; end if (reset) begin - _T_840 = 32'h0; + _T_842 = 32'h0; end if (reset) begin i0_pc_wb = 31'h0; end if (reset) begin - _T_843 = 31'h0; + _T_845 = 31'h0; end if (reset) begin dec_i0_pc_r = 31'h0; @@ -47926,26 +47944,6 @@ end // initial `FIRRTL_AFTER_INITIAL `endif `endif // SYNTHESIS - always @(posedge io_active_clk) begin - if (i0_x_ctl_en) begin - i0_x_c_load <= i0_d_c_load; - end - if (i0_r_ctl_en) begin - i0_r_c_load <= i0_x_c_load; - end - if (i0_x_ctl_en) begin - i0_x_c_mul <= i0_d_c_mul; - end - if (i0_x_ctl_en) begin - i0_x_c_alu <= i0_d_c_alu; - end - if (i0_r_ctl_en) begin - i0_r_c_mul <= i0_x_c_mul; - end - if (i0_r_ctl_en) begin - i0_r_c_alu <= i0_x_c_alu; - end - end always @(posedge rvclkhdr_io_l1clk or posedge reset) begin if (reset) begin tlu_wr_pause_r1 <= 1'h0; @@ -48108,9 +48106,9 @@ end // initial end always @(posedge io_active_clk or posedge reset) begin if (reset) begin - _T_704 <= 3'h0; + _T_706 <= 3'h0; end else begin - _T_704 <= i0_pipe_en[3:1]; + _T_706 <= i0_pipe_en[3:1]; end end always @(posedge io_active_clk or posedge reset) begin @@ -48131,7 +48129,7 @@ end // initial if (reset) begin r_d_bits_i0v <= 1'h0; end else begin - r_d_bits_i0v <= _T_736 & _T_280; + r_d_bits_i0v <= _T_738 & _T_280; end end always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin @@ -48242,6 +48240,20 @@ end // initial x_d_bits_i0v <= i0_rd_en_d & i0_legal_decode_d; end end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + i0_x_c_load <= 1'h0; + end else if (i0_x_ctl_en) begin + i0_x_c_load <= i0_d_c_load; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + i0_r_c_load <= 1'h0; + end else if (i0_r_ctl_en) begin + i0_r_c_load <= i0_x_c_load; + end + end always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin if (reset) begin r_d_bits_csrwen <= 1'h0; @@ -48253,7 +48265,7 @@ end // initial if (reset) begin r_d_valid <= 1'h0; end else begin - r_d_valid <= _T_740 & _T_280; + r_d_valid <= _T_742 & _T_280; end end always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin @@ -48324,7 +48336,7 @@ end // initial always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin if (reset) begin i0_result_r_raw <= 32'h0; - end else if (_T_764) begin + end else if (_T_766) begin i0_result_r_raw <= io_lsu_result_m; end else begin i0_result_r_raw <= io_decode_exu_exu_i0_result_x; @@ -48493,6 +48505,34 @@ end // initial r_d_bits_i0div <= x_d_bits_i0div; end end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + i0_x_c_mul <= 1'h0; + end else if (i0_x_ctl_en) begin + i0_x_c_mul <= i0_d_c_mul; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + i0_x_c_alu <= 1'h0; + end else if (i0_x_ctl_en) begin + i0_x_c_alu <= i0_d_c_alu; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + i0_r_c_mul <= 1'h0; + end else if (i0_r_ctl_en) begin + i0_r_c_mul <= i0_x_c_mul; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + i0_r_c_alu <= 1'h0; + end else if (i0_r_ctl_en) begin + i0_r_c_alu <= i0_x_c_alu; + end + end always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin if (reset) begin x_d_bits_i0store <= 1'h0; @@ -48525,7 +48565,7 @@ end // initial if (reset) begin last_br_immed_x <= 12'h0; end else if (io_decode_exu_i0_ap_predict_nt) begin - last_br_immed_x <= _T_784; + last_br_immed_x <= _T_786; end else if (_T_314) begin last_br_immed_x <= i0_pcall_imm[11:0]; end else begin @@ -48534,16 +48574,16 @@ end // initial end always @(posedge io_free_clk or posedge reset) begin if (reset) begin - _T_824 <= 1'h0; + _T_826 <= 1'h0; end else begin - _T_824 <= i0_div_decode_d | _T_823; + _T_826 <= i0_div_decode_d | _T_825; end end always @(posedge clock or posedge reset) begin if (reset) begin - _T_833 <= 5'h0; + _T_835 <= 5'h0; end else if (i0_div_decode_d) begin - _T_833 <= i0r_rd; + _T_835 <= i0r_rd; end end always @(posedge rvclkhdr_13_io_l1clk or posedge reset) begin @@ -48571,9 +48611,9 @@ end // initial end always @(posedge rvclkhdr_16_io_l1clk or posedge reset) begin if (reset) begin - _T_840 <= 32'h0; + _T_842 <= 32'h0; end else begin - _T_840 <= i0_inst_wb; + _T_842 <= i0_inst_wb; end end always @(posedge rvclkhdr_17_io_l1clk or posedge reset) begin @@ -48585,9 +48625,9 @@ end // initial end always @(posedge rvclkhdr_18_io_l1clk or posedge reset) begin if (reset) begin - _T_843 <= 31'h0; + _T_845 <= 31'h0; end else begin - _T_843 <= i0_pc_wb; + _T_845 <= i0_pc_wb; end end always @(posedge rvclkhdr_19_io_l1clk or posedge reset) begin @@ -51319,246 +51359,245 @@ module csr_tlu( reg [31:0] dicad0h; // @[lib.scala 374:16] wire _T_751 = io_dec_csr_wraddr_r == 12'h7ca; // @[dec_tlu_ctl.scala 2127:100] wire _T_752 = _T_663 & _T_751; // @[dec_tlu_ctl.scala 2127:71] - wire _T_756 = _T_752 | io_ifu_ic_debug_rd_data_valid; // @[dec_tlu_ctl.scala 2131:78] - reg [31:0] _T_758; // @[Reg.scala 27:20] - wire [31:0] dicad1 = {25'h0,_T_758[6:0]}; // @[Cat.scala 29:58] - wire [38:0] _T_763 = {dicad1[6:0],dicad0h}; // @[Cat.scala 29:58] - wire _T_765 = io_allow_dbg_halt_csr_write & io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 2159:52] - wire _T_766 = _T_765 & io_dec_i0_decode_d; // @[dec_tlu_ctl.scala 2159:75] - wire _T_767 = ~io_dec_csr_wen_unq_d; // @[dec_tlu_ctl.scala 2159:98] - wire _T_768 = _T_766 & _T_767; // @[dec_tlu_ctl.scala 2159:96] - wire _T_770 = io_dec_csr_rdaddr_d == 12'h7cb; // @[dec_tlu_ctl.scala 2159:149] - wire _T_773 = io_dec_csr_wraddr_r == 12'h7cb; // @[dec_tlu_ctl.scala 2160:104] + wire _T_757 = _T_752 | io_ifu_ic_debug_rd_data_valid; // @[dec_tlu_ctl.scala 2131:78] + reg [6:0] _T_759; // @[Reg.scala 27:20] + wire [31:0] dicad1 = {25'h0,_T_759}; // @[Cat.scala 29:58] + wire [38:0] _T_764 = {dicad1[6:0],dicad0h}; // @[Cat.scala 29:58] + wire _T_766 = io_allow_dbg_halt_csr_write & io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 2159:52] + wire _T_767 = _T_766 & io_dec_i0_decode_d; // @[dec_tlu_ctl.scala 2159:75] + wire _T_768 = ~io_dec_csr_wen_unq_d; // @[dec_tlu_ctl.scala 2159:98] + wire _T_769 = _T_767 & _T_768; // @[dec_tlu_ctl.scala 2159:96] + wire _T_771 = io_dec_csr_rdaddr_d == 12'h7cb; // @[dec_tlu_ctl.scala 2159:149] + wire _T_774 = io_dec_csr_wraddr_r == 12'h7cb; // @[dec_tlu_ctl.scala 2160:104] reg icache_rd_valid_f; // @[dec_tlu_ctl.scala 2162:58] reg icache_wr_valid_f; // @[dec_tlu_ctl.scala 2163:58] - wire _T_775 = io_dec_csr_wraddr_r == 12'h7a0; // @[dec_tlu_ctl.scala 2174:69] - wire wr_mtsel_r = io_dec_csr_wen_r_mod & _T_775; // @[dec_tlu_ctl.scala 2174:40] + wire _T_776 = io_dec_csr_wraddr_r == 12'h7a0; // @[dec_tlu_ctl.scala 2174:69] + wire wr_mtsel_r = io_dec_csr_wen_r_mod & _T_776; // @[dec_tlu_ctl.scala 2174:40] reg [1:0] mtsel; // @[dec_tlu_ctl.scala 2177:43] wire tdata_load = io_dec_csr_wrdata_r[0] & _T_408; // @[dec_tlu_ctl.scala 2212:42] wire tdata_opcode = io_dec_csr_wrdata_r[2] & _T_408; // @[dec_tlu_ctl.scala 2214:44] - wire _T_786 = io_dec_csr_wrdata_r[27] & io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2216:46] - wire tdata_action = _T_786 & io_dec_csr_wrdata_r[12]; // @[dec_tlu_ctl.scala 2216:69] - wire [9:0] tdata_wrdata_r = {_T_786,io_dec_csr_wrdata_r[20:19],tdata_action,io_dec_csr_wrdata_r[11],io_dec_csr_wrdata_r[7:6],tdata_opcode,io_dec_csr_wrdata_r[1],tdata_load}; // @[Cat.scala 29:58] - wire _T_801 = io_dec_csr_wraddr_r == 12'h7a1; // @[dec_tlu_ctl.scala 2222:99] - wire _T_802 = io_dec_csr_wen_r_mod & _T_801; // @[dec_tlu_ctl.scala 2222:70] - wire _T_803 = mtsel == 2'h0; // @[dec_tlu_ctl.scala 2222:121] - wire _T_804 = _T_802 & _T_803; // @[dec_tlu_ctl.scala 2222:112] - wire _T_806 = ~io_mtdata1_t_0[9]; // @[dec_tlu_ctl.scala 2222:138] - wire _T_807 = _T_806 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2222:170] - wire wr_mtdata1_t_r_0 = _T_804 & _T_807; // @[dec_tlu_ctl.scala 2222:135] - wire _T_812 = mtsel == 2'h1; // @[dec_tlu_ctl.scala 2222:121] - wire _T_813 = _T_802 & _T_812; // @[dec_tlu_ctl.scala 2222:112] - wire _T_815 = ~io_mtdata1_t_1[9]; // @[dec_tlu_ctl.scala 2222:138] - wire _T_816 = _T_815 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2222:170] - wire wr_mtdata1_t_r_1 = _T_813 & _T_816; // @[dec_tlu_ctl.scala 2222:135] - wire _T_821 = mtsel == 2'h2; // @[dec_tlu_ctl.scala 2222:121] - wire _T_822 = _T_802 & _T_821; // @[dec_tlu_ctl.scala 2222:112] - wire _T_824 = ~io_mtdata1_t_2[9]; // @[dec_tlu_ctl.scala 2222:138] - wire _T_825 = _T_824 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2222:170] - wire wr_mtdata1_t_r_2 = _T_822 & _T_825; // @[dec_tlu_ctl.scala 2222:135] - wire _T_830 = mtsel == 2'h3; // @[dec_tlu_ctl.scala 2222:121] - wire _T_831 = _T_802 & _T_830; // @[dec_tlu_ctl.scala 2222:112] - wire _T_833 = ~io_mtdata1_t_3[9]; // @[dec_tlu_ctl.scala 2222:138] - wire _T_834 = _T_833 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2222:170] - wire wr_mtdata1_t_r_3 = _T_831 & _T_834; // @[dec_tlu_ctl.scala 2222:135] - wire _T_840 = io_update_hit_bit_r[0] | io_mtdata1_t_0[8]; // @[dec_tlu_ctl.scala 2223:139] - wire [9:0] _T_843 = {io_mtdata1_t_0[9],_T_840,io_mtdata1_t_0[7:0]}; // @[Cat.scala 29:58] - wire _T_849 = io_update_hit_bit_r[1] | io_mtdata1_t_1[8]; // @[dec_tlu_ctl.scala 2223:139] - wire [9:0] _T_852 = {io_mtdata1_t_1[9],_T_849,io_mtdata1_t_1[7:0]}; // @[Cat.scala 29:58] - wire _T_858 = io_update_hit_bit_r[2] | io_mtdata1_t_2[8]; // @[dec_tlu_ctl.scala 2223:139] - wire [9:0] _T_861 = {io_mtdata1_t_2[9],_T_858,io_mtdata1_t_2[7:0]}; // @[Cat.scala 29:58] - wire _T_867 = io_update_hit_bit_r[3] | io_mtdata1_t_3[8]; // @[dec_tlu_ctl.scala 2223:139] - wire [9:0] _T_870 = {io_mtdata1_t_3[9],_T_867,io_mtdata1_t_3[7:0]}; // @[Cat.scala 29:58] - reg [9:0] _T_872; // @[dec_tlu_ctl.scala 2225:74] + wire _T_787 = io_dec_csr_wrdata_r[27] & io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2216:46] + wire tdata_action = _T_787 & io_dec_csr_wrdata_r[12]; // @[dec_tlu_ctl.scala 2216:69] + wire [9:0] tdata_wrdata_r = {_T_787,io_dec_csr_wrdata_r[20:19],tdata_action,io_dec_csr_wrdata_r[11],io_dec_csr_wrdata_r[7:6],tdata_opcode,io_dec_csr_wrdata_r[1],tdata_load}; // @[Cat.scala 29:58] + wire _T_802 = io_dec_csr_wraddr_r == 12'h7a1; // @[dec_tlu_ctl.scala 2222:99] + wire _T_803 = io_dec_csr_wen_r_mod & _T_802; // @[dec_tlu_ctl.scala 2222:70] + wire _T_804 = mtsel == 2'h0; // @[dec_tlu_ctl.scala 2222:121] + wire _T_805 = _T_803 & _T_804; // @[dec_tlu_ctl.scala 2222:112] + wire _T_807 = ~io_mtdata1_t_0[9]; // @[dec_tlu_ctl.scala 2222:138] + wire _T_808 = _T_807 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2222:170] + wire wr_mtdata1_t_r_0 = _T_805 & _T_808; // @[dec_tlu_ctl.scala 2222:135] + wire _T_813 = mtsel == 2'h1; // @[dec_tlu_ctl.scala 2222:121] + wire _T_814 = _T_803 & _T_813; // @[dec_tlu_ctl.scala 2222:112] + wire _T_816 = ~io_mtdata1_t_1[9]; // @[dec_tlu_ctl.scala 2222:138] + wire _T_817 = _T_816 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2222:170] + wire wr_mtdata1_t_r_1 = _T_814 & _T_817; // @[dec_tlu_ctl.scala 2222:135] + wire _T_822 = mtsel == 2'h2; // @[dec_tlu_ctl.scala 2222:121] + wire _T_823 = _T_803 & _T_822; // @[dec_tlu_ctl.scala 2222:112] + wire _T_825 = ~io_mtdata1_t_2[9]; // @[dec_tlu_ctl.scala 2222:138] + wire _T_826 = _T_825 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2222:170] + wire wr_mtdata1_t_r_2 = _T_823 & _T_826; // @[dec_tlu_ctl.scala 2222:135] + wire _T_831 = mtsel == 2'h3; // @[dec_tlu_ctl.scala 2222:121] + wire _T_832 = _T_803 & _T_831; // @[dec_tlu_ctl.scala 2222:112] + wire _T_834 = ~io_mtdata1_t_3[9]; // @[dec_tlu_ctl.scala 2222:138] + wire _T_835 = _T_834 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2222:170] + wire wr_mtdata1_t_r_3 = _T_832 & _T_835; // @[dec_tlu_ctl.scala 2222:135] + wire _T_841 = io_update_hit_bit_r[0] | io_mtdata1_t_0[8]; // @[dec_tlu_ctl.scala 2223:139] + wire [9:0] _T_844 = {io_mtdata1_t_0[9],_T_841,io_mtdata1_t_0[7:0]}; // @[Cat.scala 29:58] + wire _T_850 = io_update_hit_bit_r[1] | io_mtdata1_t_1[8]; // @[dec_tlu_ctl.scala 2223:139] + wire [9:0] _T_853 = {io_mtdata1_t_1[9],_T_850,io_mtdata1_t_1[7:0]}; // @[Cat.scala 29:58] + wire _T_859 = io_update_hit_bit_r[2] | io_mtdata1_t_2[8]; // @[dec_tlu_ctl.scala 2223:139] + wire [9:0] _T_862 = {io_mtdata1_t_2[9],_T_859,io_mtdata1_t_2[7:0]}; // @[Cat.scala 29:58] + wire _T_868 = io_update_hit_bit_r[3] | io_mtdata1_t_3[8]; // @[dec_tlu_ctl.scala 2223:139] + wire [9:0] _T_871 = {io_mtdata1_t_3[9],_T_868,io_mtdata1_t_3[7:0]}; // @[Cat.scala 29:58] reg [9:0] _T_873; // @[dec_tlu_ctl.scala 2225:74] reg [9:0] _T_874; // @[dec_tlu_ctl.scala 2225:74] reg [9:0] _T_875; // @[dec_tlu_ctl.scala 2225:74] - wire [31:0] _T_890 = {4'h2,io_mtdata1_t_0[9],6'h1f,io_mtdata1_t_0[8:7],6'h0,io_mtdata1_t_0[6:5],3'h0,io_mtdata1_t_0[4:3],3'h0,io_mtdata1_t_0[2:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_905 = {4'h2,io_mtdata1_t_1[9],6'h1f,io_mtdata1_t_1[8:7],6'h0,io_mtdata1_t_1[6:5],3'h0,io_mtdata1_t_1[4:3],3'h0,io_mtdata1_t_1[2:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_920 = {4'h2,io_mtdata1_t_2[9],6'h1f,io_mtdata1_t_2[8:7],6'h0,io_mtdata1_t_2[6:5],3'h0,io_mtdata1_t_2[4:3],3'h0,io_mtdata1_t_2[2:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_935 = {4'h2,io_mtdata1_t_3[9],6'h1f,io_mtdata1_t_3[8:7],6'h0,io_mtdata1_t_3[6:5],3'h0,io_mtdata1_t_3[4:3],3'h0,io_mtdata1_t_3[2:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_936 = _T_803 ? _T_890 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_937 = _T_812 ? _T_905 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_938 = _T_821 ? _T_920 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_939 = _T_830 ? _T_935 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_940 = _T_936 | _T_937; // @[Mux.scala 27:72] - wire [31:0] _T_941 = _T_940 | _T_938; // @[Mux.scala 27:72] - wire [31:0] mtdata1_tsel_out = _T_941 | _T_939; // @[Mux.scala 27:72] - wire _T_968 = io_dec_csr_wraddr_r == 12'h7a2; // @[dec_tlu_ctl.scala 2242:98] - wire _T_969 = io_dec_csr_wen_r_mod & _T_968; // @[dec_tlu_ctl.scala 2242:69] - wire _T_971 = _T_969 & _T_803; // @[dec_tlu_ctl.scala 2242:111] - wire _T_980 = _T_969 & _T_812; // @[dec_tlu_ctl.scala 2242:111] - wire _T_989 = _T_969 & _T_821; // @[dec_tlu_ctl.scala 2242:111] - wire _T_998 = _T_969 & _T_830; // @[dec_tlu_ctl.scala 2242:111] + reg [9:0] _T_876; // @[dec_tlu_ctl.scala 2225:74] + wire [31:0] _T_891 = {4'h2,io_mtdata1_t_0[9],6'h1f,io_mtdata1_t_0[8:7],6'h0,io_mtdata1_t_0[6:5],3'h0,io_mtdata1_t_0[4:3],3'h0,io_mtdata1_t_0[2:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_906 = {4'h2,io_mtdata1_t_1[9],6'h1f,io_mtdata1_t_1[8:7],6'h0,io_mtdata1_t_1[6:5],3'h0,io_mtdata1_t_1[4:3],3'h0,io_mtdata1_t_1[2:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_921 = {4'h2,io_mtdata1_t_2[9],6'h1f,io_mtdata1_t_2[8:7],6'h0,io_mtdata1_t_2[6:5],3'h0,io_mtdata1_t_2[4:3],3'h0,io_mtdata1_t_2[2:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_936 = {4'h2,io_mtdata1_t_3[9],6'h1f,io_mtdata1_t_3[8:7],6'h0,io_mtdata1_t_3[6:5],3'h0,io_mtdata1_t_3[4:3],3'h0,io_mtdata1_t_3[2:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_937 = _T_804 ? _T_891 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_938 = _T_813 ? _T_906 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_939 = _T_822 ? _T_921 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_940 = _T_831 ? _T_936 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_941 = _T_937 | _T_938; // @[Mux.scala 27:72] + wire [31:0] _T_942 = _T_941 | _T_939; // @[Mux.scala 27:72] + wire [31:0] mtdata1_tsel_out = _T_942 | _T_940; // @[Mux.scala 27:72] + wire _T_969 = io_dec_csr_wraddr_r == 12'h7a2; // @[dec_tlu_ctl.scala 2242:98] + wire _T_970 = io_dec_csr_wen_r_mod & _T_969; // @[dec_tlu_ctl.scala 2242:69] + wire _T_972 = _T_970 & _T_804; // @[dec_tlu_ctl.scala 2242:111] + wire _T_981 = _T_970 & _T_813; // @[dec_tlu_ctl.scala 2242:111] + wire _T_990 = _T_970 & _T_822; // @[dec_tlu_ctl.scala 2242:111] + wire _T_999 = _T_970 & _T_831; // @[dec_tlu_ctl.scala 2242:111] reg [31:0] mtdata2_t_0; // @[lib.scala 374:16] reg [31:0] mtdata2_t_1; // @[lib.scala 374:16] reg [31:0] mtdata2_t_2; // @[lib.scala 374:16] reg [31:0] mtdata2_t_3; // @[lib.scala 374:16] - wire [31:0] _T_1015 = _T_803 ? mtdata2_t_0 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_1016 = _T_812 ? mtdata2_t_1 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_1017 = _T_821 ? mtdata2_t_2 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_1018 = _T_830 ? mtdata2_t_3 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_1019 = _T_1015 | _T_1016; // @[Mux.scala 27:72] - wire [31:0] _T_1020 = _T_1019 | _T_1017; // @[Mux.scala 27:72] - wire [31:0] mtdata2_tsel_out = _T_1020 | _T_1018; // @[Mux.scala 27:72] - wire [3:0] _T_1023 = io_tlu_i0_commit_cmt ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] pmu_i0_itype_qual = io_dec_tlu_packet_r_pmu_i0_itype & _T_1023; // @[dec_tlu_ctl.scala 2267:59] - wire _T_1025 = ~mcountinhibit[3]; // @[dec_tlu_ctl.scala 2273:24] + wire [31:0] _T_1016 = _T_804 ? mtdata2_t_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1017 = _T_813 ? mtdata2_t_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1018 = _T_822 ? mtdata2_t_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1019 = _T_831 ? mtdata2_t_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1020 = _T_1016 | _T_1017; // @[Mux.scala 27:72] + wire [31:0] _T_1021 = _T_1020 | _T_1018; // @[Mux.scala 27:72] + wire [31:0] mtdata2_tsel_out = _T_1021 | _T_1019; // @[Mux.scala 27:72] + wire [3:0] _T_1024 = io_tlu_i0_commit_cmt ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] pmu_i0_itype_qual = io_dec_tlu_packet_r_pmu_i0_itype & _T_1024; // @[dec_tlu_ctl.scala 2267:59] + wire _T_1026 = ~mcountinhibit[3]; // @[dec_tlu_ctl.scala 2273:24] reg [9:0] mhpme3; // @[Reg.scala 27:20] - wire _T_1026 = mhpme3 == 10'h1; // @[dec_tlu_ctl.scala 2274:34] - wire _T_1028 = mhpme3 == 10'h2; // @[dec_tlu_ctl.scala 2275:34] - wire _T_1030 = mhpme3 == 10'h3; // @[dec_tlu_ctl.scala 2276:34] - wire _T_1032 = mhpme3 == 10'h4; // @[dec_tlu_ctl.scala 2277:34] - wire _T_1034 = ~io_illegal_r; // @[dec_tlu_ctl.scala 2277:96] - wire _T_1035 = io_tlu_i0_commit_cmt & _T_1034; // @[dec_tlu_ctl.scala 2277:94] - wire _T_1036 = mhpme3 == 10'h5; // @[dec_tlu_ctl.scala 2278:34] - wire _T_1038 = ~io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 2278:96] - wire _T_1039 = io_tlu_i0_commit_cmt & _T_1038; // @[dec_tlu_ctl.scala 2278:94] - wire _T_1041 = _T_1039 & _T_1034; // @[dec_tlu_ctl.scala 2278:115] - wire _T_1042 = mhpme3 == 10'h6; // @[dec_tlu_ctl.scala 2279:34] - wire _T_1044 = io_tlu_i0_commit_cmt & io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 2279:94] - wire _T_1046 = _T_1044 & _T_1034; // @[dec_tlu_ctl.scala 2279:115] - wire _T_1047 = mhpme3 == 10'h7; // @[dec_tlu_ctl.scala 2280:34] - wire _T_1049 = mhpme3 == 10'h8; // @[dec_tlu_ctl.scala 2281:34] - wire _T_1051 = mhpme3 == 10'h1e; // @[dec_tlu_ctl.scala 2282:34] - wire _T_1053 = mhpme3 == 10'h9; // @[dec_tlu_ctl.scala 2283:34] - wire _T_1055 = pmu_i0_itype_qual == 4'h1; // @[dec_tlu_ctl.scala 2283:91] - wire _T_1056 = mhpme3 == 10'ha; // @[dec_tlu_ctl.scala 2284:34] - wire _T_1058 = io_dec_tlu_packet_r_pmu_divide & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2284:105] - wire _T_1059 = mhpme3 == 10'hb; // @[dec_tlu_ctl.scala 2285:34] - wire _T_1061 = pmu_i0_itype_qual == 4'h2; // @[dec_tlu_ctl.scala 2285:91] - wire _T_1062 = mhpme3 == 10'hc; // @[dec_tlu_ctl.scala 2286:34] - wire _T_1064 = pmu_i0_itype_qual == 4'h3; // @[dec_tlu_ctl.scala 2286:91] - wire _T_1065 = mhpme3 == 10'hd; // @[dec_tlu_ctl.scala 2287:34] - wire _T_1068 = _T_1061 & io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 2287:100] - wire _T_1069 = mhpme3 == 10'he; // @[dec_tlu_ctl.scala 2288:34] - wire _T_1073 = _T_1064 & io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 2288:101] - wire _T_1074 = mhpme3 == 10'hf; // @[dec_tlu_ctl.scala 2289:34] - wire _T_1076 = pmu_i0_itype_qual == 4'h4; // @[dec_tlu_ctl.scala 2289:89] - wire _T_1077 = mhpme3 == 10'h10; // @[dec_tlu_ctl.scala 2290:34] - wire _T_1079 = pmu_i0_itype_qual == 4'h5; // @[dec_tlu_ctl.scala 2290:89] - wire _T_1080 = mhpme3 == 10'h12; // @[dec_tlu_ctl.scala 2291:34] - wire _T_1082 = pmu_i0_itype_qual == 4'h6; // @[dec_tlu_ctl.scala 2291:89] - wire _T_1083 = mhpme3 == 10'h11; // @[dec_tlu_ctl.scala 2292:34] - wire _T_1085 = pmu_i0_itype_qual == 4'h7; // @[dec_tlu_ctl.scala 2292:89] - wire _T_1086 = mhpme3 == 10'h13; // @[dec_tlu_ctl.scala 2293:34] - wire _T_1088 = pmu_i0_itype_qual == 4'h8; // @[dec_tlu_ctl.scala 2293:89] - wire _T_1089 = mhpme3 == 10'h14; // @[dec_tlu_ctl.scala 2294:34] - wire _T_1091 = pmu_i0_itype_qual == 4'h9; // @[dec_tlu_ctl.scala 2294:89] - wire _T_1092 = mhpme3 == 10'h15; // @[dec_tlu_ctl.scala 2295:34] - wire _T_1094 = pmu_i0_itype_qual == 4'ha; // @[dec_tlu_ctl.scala 2295:89] - wire _T_1095 = mhpme3 == 10'h16; // @[dec_tlu_ctl.scala 2296:34] - wire _T_1097 = pmu_i0_itype_qual == 4'hb; // @[dec_tlu_ctl.scala 2296:89] - wire _T_1098 = mhpme3 == 10'h17; // @[dec_tlu_ctl.scala 2297:34] - wire _T_1100 = pmu_i0_itype_qual == 4'hc; // @[dec_tlu_ctl.scala 2297:89] - wire _T_1101 = mhpme3 == 10'h18; // @[dec_tlu_ctl.scala 2298:34] - wire _T_1103 = pmu_i0_itype_qual == 4'hd; // @[dec_tlu_ctl.scala 2298:89] - wire _T_1104 = pmu_i0_itype_qual == 4'he; // @[dec_tlu_ctl.scala 2298:122] - wire _T_1105 = _T_1103 | _T_1104; // @[dec_tlu_ctl.scala 2298:101] - wire _T_1106 = mhpme3 == 10'h19; // @[dec_tlu_ctl.scala 2299:34] - wire _T_1108 = io_exu_pmu_i0_br_misp & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2299:95] - wire _T_1109 = mhpme3 == 10'h1a; // @[dec_tlu_ctl.scala 2300:34] - wire _T_1111 = io_exu_pmu_i0_br_ataken & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2300:97] - wire _T_1112 = mhpme3 == 10'h1b; // @[dec_tlu_ctl.scala 2301:34] - wire _T_1114 = io_dec_tlu_packet_r_pmu_i0_br_unpred & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2301:110] - wire _T_1115 = mhpme3 == 10'h1c; // @[dec_tlu_ctl.scala 2302:34] - wire _T_1119 = mhpme3 == 10'h1f; // @[dec_tlu_ctl.scala 2304:34] - wire _T_1121 = mhpme3 == 10'h20; // @[dec_tlu_ctl.scala 2305:34] - wire _T_1123 = mhpme3 == 10'h22; // @[dec_tlu_ctl.scala 2306:34] - wire _T_1125 = mhpme3 == 10'h23; // @[dec_tlu_ctl.scala 2307:34] - wire _T_1127 = mhpme3 == 10'h24; // @[dec_tlu_ctl.scala 2308:34] - wire _T_1129 = mhpme3 == 10'h25; // @[dec_tlu_ctl.scala 2309:34] - wire _T_1131 = io_i0_exception_valid_r | io_i0_trigger_hit_r; // @[dec_tlu_ctl.scala 2309:98] - wire _T_1132 = _T_1131 | io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 2309:120] - wire _T_1133 = mhpme3 == 10'h26; // @[dec_tlu_ctl.scala 2310:34] - wire _T_1135 = io_take_timer_int | io_take_int_timer0_int; // @[dec_tlu_ctl.scala 2310:92] - wire _T_1136 = _T_1135 | io_take_int_timer1_int; // @[dec_tlu_ctl.scala 2310:117] - wire _T_1137 = mhpme3 == 10'h27; // @[dec_tlu_ctl.scala 2311:34] - wire _T_1139 = mhpme3 == 10'h28; // @[dec_tlu_ctl.scala 2312:34] - wire _T_1141 = mhpme3 == 10'h29; // @[dec_tlu_ctl.scala 2313:34] - wire _T_1143 = io_dec_tlu_br0_error_r | io_dec_tlu_br0_start_error_r; // @[dec_tlu_ctl.scala 2313:97] - wire _T_1144 = _T_1143 & io_rfpc_i0_r; // @[dec_tlu_ctl.scala 2313:129] - wire _T_1145 = mhpme3 == 10'h2a; // @[dec_tlu_ctl.scala 2314:34] - wire _T_1147 = mhpme3 == 10'h2b; // @[dec_tlu_ctl.scala 2315:34] - wire _T_1149 = mhpme3 == 10'h2c; // @[dec_tlu_ctl.scala 2316:34] - wire _T_1151 = mhpme3 == 10'h2d; // @[dec_tlu_ctl.scala 2317:34] - wire _T_1153 = mhpme3 == 10'h2e; // @[dec_tlu_ctl.scala 2318:34] - wire _T_1155 = mhpme3 == 10'h2f; // @[dec_tlu_ctl.scala 2319:34] - wire _T_1157 = mhpme3 == 10'h30; // @[dec_tlu_ctl.scala 2320:34] - wire _T_1159 = mhpme3 == 10'h31; // @[dec_tlu_ctl.scala 2321:34] - wire _T_1163 = ~io_mstatus[0]; // @[dec_tlu_ctl.scala 2321:73] - wire _T_1164 = mhpme3 == 10'h32; // @[dec_tlu_ctl.scala 2322:34] - wire [5:0] _T_1171 = io_mip & mie; // @[dec_tlu_ctl.scala 2322:113] - wire _T_1172 = |_T_1171; // @[dec_tlu_ctl.scala 2322:125] - wire _T_1173 = _T_1163 & _T_1172; // @[dec_tlu_ctl.scala 2322:98] - wire _T_1174 = mhpme3 == 10'h36; // @[dec_tlu_ctl.scala 2323:34] - wire _T_1176 = pmu_i0_itype_qual == 4'hf; // @[dec_tlu_ctl.scala 2323:91] - wire _T_1177 = mhpme3 == 10'h37; // @[dec_tlu_ctl.scala 2324:34] - wire _T_1179 = io_tlu_i0_commit_cmt & io_lsu_pmu_load_external_r; // @[dec_tlu_ctl.scala 2324:94] - wire _T_1180 = mhpme3 == 10'h38; // @[dec_tlu_ctl.scala 2325:34] - wire _T_1182 = io_tlu_i0_commit_cmt & io_lsu_pmu_store_external_r; // @[dec_tlu_ctl.scala 2325:94] - wire _T_1183 = mhpme3 == 10'h200; // @[dec_tlu_ctl.scala 2327:34] - wire _T_1185 = mhpme3 == 10'h201; // @[dec_tlu_ctl.scala 2328:34] - wire _T_1187 = mhpme3 == 10'h202; // @[dec_tlu_ctl.scala 2329:34] - wire _T_1189 = mhpme3 == 10'h203; // @[dec_tlu_ctl.scala 2330:34] - wire _T_1191 = mhpme3 == 10'h204; // @[dec_tlu_ctl.scala 2331:34] - wire _T_1194 = _T_1028 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] - wire _T_1195 = _T_1030 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] - wire _T_1196 = _T_1032 & _T_1035; // @[Mux.scala 27:72] - wire _T_1197 = _T_1036 & _T_1041; // @[Mux.scala 27:72] - wire _T_1198 = _T_1042 & _T_1046; // @[Mux.scala 27:72] - wire _T_1199 = _T_1047 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] - wire _T_1200 = _T_1049 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] - wire _T_1201 = _T_1051 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] - wire _T_1202 = _T_1053 & _T_1055; // @[Mux.scala 27:72] - wire _T_1203 = _T_1056 & _T_1058; // @[Mux.scala 27:72] - wire _T_1204 = _T_1059 & _T_1061; // @[Mux.scala 27:72] - wire _T_1205 = _T_1062 & _T_1064; // @[Mux.scala 27:72] - wire _T_1206 = _T_1065 & _T_1068; // @[Mux.scala 27:72] - wire _T_1207 = _T_1069 & _T_1073; // @[Mux.scala 27:72] - wire _T_1208 = _T_1074 & _T_1076; // @[Mux.scala 27:72] - wire _T_1209 = _T_1077 & _T_1079; // @[Mux.scala 27:72] - wire _T_1210 = _T_1080 & _T_1082; // @[Mux.scala 27:72] - wire _T_1211 = _T_1083 & _T_1085; // @[Mux.scala 27:72] - wire _T_1212 = _T_1086 & _T_1088; // @[Mux.scala 27:72] - wire _T_1213 = _T_1089 & _T_1091; // @[Mux.scala 27:72] - wire _T_1214 = _T_1092 & _T_1094; // @[Mux.scala 27:72] - wire _T_1215 = _T_1095 & _T_1097; // @[Mux.scala 27:72] - wire _T_1216 = _T_1098 & _T_1100; // @[Mux.scala 27:72] - wire _T_1217 = _T_1101 & _T_1105; // @[Mux.scala 27:72] - wire _T_1218 = _T_1106 & _T_1108; // @[Mux.scala 27:72] - wire _T_1219 = _T_1109 & _T_1111; // @[Mux.scala 27:72] - wire _T_1220 = _T_1112 & _T_1114; // @[Mux.scala 27:72] - wire _T_1221 = _T_1115 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] - wire _T_1223 = _T_1119 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] - wire _T_1224 = _T_1121 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] - wire _T_1225 = _T_1123 & io_lsu_store_stall_any; // @[Mux.scala 27:72] - wire _T_1226 = _T_1125 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] - wire _T_1227 = _T_1127 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] - wire _T_1228 = _T_1129 & _T_1132; // @[Mux.scala 27:72] - wire _T_1229 = _T_1133 & _T_1136; // @[Mux.scala 27:72] - wire _T_1230 = _T_1137 & io_take_ext_int; // @[Mux.scala 27:72] - wire _T_1231 = _T_1139 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] - wire _T_1232 = _T_1141 & _T_1144; // @[Mux.scala 27:72] - wire _T_1233 = _T_1145 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_1234 = _T_1147 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_1235 = _T_1149 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] - wire _T_1236 = _T_1151 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_1237 = _T_1153 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_1238 = _T_1155 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_1239 = _T_1157 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_1240 = _T_1159 & _T_1163; // @[Mux.scala 27:72] - wire _T_1241 = _T_1164 & _T_1173; // @[Mux.scala 27:72] - wire _T_1242 = _T_1174 & _T_1176; // @[Mux.scala 27:72] - wire _T_1243 = _T_1177 & _T_1179; // @[Mux.scala 27:72] - wire _T_1244 = _T_1180 & _T_1182; // @[Mux.scala 27:72] - wire _T_1245 = _T_1183 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] - wire _T_1246 = _T_1185 & io_dma_pmu_any_read; // @[Mux.scala 27:72] - wire _T_1247 = _T_1187 & io_dma_pmu_any_write; // @[Mux.scala 27:72] - wire _T_1248 = _T_1189 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] - wire _T_1249 = _T_1191 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] - wire _T_1250 = _T_1026 | _T_1194; // @[Mux.scala 27:72] - wire _T_1251 = _T_1250 | _T_1195; // @[Mux.scala 27:72] + wire _T_1027 = mhpme3 == 10'h1; // @[dec_tlu_ctl.scala 2274:34] + wire _T_1029 = mhpme3 == 10'h2; // @[dec_tlu_ctl.scala 2275:34] + wire _T_1031 = mhpme3 == 10'h3; // @[dec_tlu_ctl.scala 2276:34] + wire _T_1033 = mhpme3 == 10'h4; // @[dec_tlu_ctl.scala 2277:34] + wire _T_1035 = ~io_illegal_r; // @[dec_tlu_ctl.scala 2277:96] + wire _T_1036 = io_tlu_i0_commit_cmt & _T_1035; // @[dec_tlu_ctl.scala 2277:94] + wire _T_1037 = mhpme3 == 10'h5; // @[dec_tlu_ctl.scala 2278:34] + wire _T_1039 = ~io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 2278:96] + wire _T_1040 = io_tlu_i0_commit_cmt & _T_1039; // @[dec_tlu_ctl.scala 2278:94] + wire _T_1042 = _T_1040 & _T_1035; // @[dec_tlu_ctl.scala 2278:115] + wire _T_1043 = mhpme3 == 10'h6; // @[dec_tlu_ctl.scala 2279:34] + wire _T_1045 = io_tlu_i0_commit_cmt & io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 2279:94] + wire _T_1047 = _T_1045 & _T_1035; // @[dec_tlu_ctl.scala 2279:115] + wire _T_1048 = mhpme3 == 10'h7; // @[dec_tlu_ctl.scala 2280:34] + wire _T_1050 = mhpme3 == 10'h8; // @[dec_tlu_ctl.scala 2281:34] + wire _T_1052 = mhpme3 == 10'h1e; // @[dec_tlu_ctl.scala 2282:34] + wire _T_1054 = mhpme3 == 10'h9; // @[dec_tlu_ctl.scala 2283:34] + wire _T_1056 = pmu_i0_itype_qual == 4'h1; // @[dec_tlu_ctl.scala 2283:91] + wire _T_1057 = mhpme3 == 10'ha; // @[dec_tlu_ctl.scala 2284:34] + wire _T_1059 = io_dec_tlu_packet_r_pmu_divide & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2284:105] + wire _T_1060 = mhpme3 == 10'hb; // @[dec_tlu_ctl.scala 2285:34] + wire _T_1062 = pmu_i0_itype_qual == 4'h2; // @[dec_tlu_ctl.scala 2285:91] + wire _T_1063 = mhpme3 == 10'hc; // @[dec_tlu_ctl.scala 2286:34] + wire _T_1065 = pmu_i0_itype_qual == 4'h3; // @[dec_tlu_ctl.scala 2286:91] + wire _T_1066 = mhpme3 == 10'hd; // @[dec_tlu_ctl.scala 2287:34] + wire _T_1069 = _T_1062 & io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 2287:100] + wire _T_1070 = mhpme3 == 10'he; // @[dec_tlu_ctl.scala 2288:34] + wire _T_1074 = _T_1065 & io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 2288:101] + wire _T_1075 = mhpme3 == 10'hf; // @[dec_tlu_ctl.scala 2289:34] + wire _T_1077 = pmu_i0_itype_qual == 4'h4; // @[dec_tlu_ctl.scala 2289:89] + wire _T_1078 = mhpme3 == 10'h10; // @[dec_tlu_ctl.scala 2290:34] + wire _T_1080 = pmu_i0_itype_qual == 4'h5; // @[dec_tlu_ctl.scala 2290:89] + wire _T_1081 = mhpme3 == 10'h12; // @[dec_tlu_ctl.scala 2291:34] + wire _T_1083 = pmu_i0_itype_qual == 4'h6; // @[dec_tlu_ctl.scala 2291:89] + wire _T_1084 = mhpme3 == 10'h11; // @[dec_tlu_ctl.scala 2292:34] + wire _T_1086 = pmu_i0_itype_qual == 4'h7; // @[dec_tlu_ctl.scala 2292:89] + wire _T_1087 = mhpme3 == 10'h13; // @[dec_tlu_ctl.scala 2293:34] + wire _T_1089 = pmu_i0_itype_qual == 4'h8; // @[dec_tlu_ctl.scala 2293:89] + wire _T_1090 = mhpme3 == 10'h14; // @[dec_tlu_ctl.scala 2294:34] + wire _T_1092 = pmu_i0_itype_qual == 4'h9; // @[dec_tlu_ctl.scala 2294:89] + wire _T_1093 = mhpme3 == 10'h15; // @[dec_tlu_ctl.scala 2295:34] + wire _T_1095 = pmu_i0_itype_qual == 4'ha; // @[dec_tlu_ctl.scala 2295:89] + wire _T_1096 = mhpme3 == 10'h16; // @[dec_tlu_ctl.scala 2296:34] + wire _T_1098 = pmu_i0_itype_qual == 4'hb; // @[dec_tlu_ctl.scala 2296:89] + wire _T_1099 = mhpme3 == 10'h17; // @[dec_tlu_ctl.scala 2297:34] + wire _T_1101 = pmu_i0_itype_qual == 4'hc; // @[dec_tlu_ctl.scala 2297:89] + wire _T_1102 = mhpme3 == 10'h18; // @[dec_tlu_ctl.scala 2298:34] + wire _T_1104 = pmu_i0_itype_qual == 4'hd; // @[dec_tlu_ctl.scala 2298:89] + wire _T_1105 = pmu_i0_itype_qual == 4'he; // @[dec_tlu_ctl.scala 2298:122] + wire _T_1106 = _T_1104 | _T_1105; // @[dec_tlu_ctl.scala 2298:101] + wire _T_1107 = mhpme3 == 10'h19; // @[dec_tlu_ctl.scala 2299:34] + wire _T_1109 = io_exu_pmu_i0_br_misp & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2299:95] + wire _T_1110 = mhpme3 == 10'h1a; // @[dec_tlu_ctl.scala 2300:34] + wire _T_1112 = io_exu_pmu_i0_br_ataken & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2300:97] + wire _T_1113 = mhpme3 == 10'h1b; // @[dec_tlu_ctl.scala 2301:34] + wire _T_1115 = io_dec_tlu_packet_r_pmu_i0_br_unpred & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2301:110] + wire _T_1116 = mhpme3 == 10'h1c; // @[dec_tlu_ctl.scala 2302:34] + wire _T_1120 = mhpme3 == 10'h1f; // @[dec_tlu_ctl.scala 2304:34] + wire _T_1122 = mhpme3 == 10'h20; // @[dec_tlu_ctl.scala 2305:34] + wire _T_1124 = mhpme3 == 10'h22; // @[dec_tlu_ctl.scala 2306:34] + wire _T_1126 = mhpme3 == 10'h23; // @[dec_tlu_ctl.scala 2307:34] + wire _T_1128 = mhpme3 == 10'h24; // @[dec_tlu_ctl.scala 2308:34] + wire _T_1130 = mhpme3 == 10'h25; // @[dec_tlu_ctl.scala 2309:34] + wire _T_1132 = io_i0_exception_valid_r | io_i0_trigger_hit_r; // @[dec_tlu_ctl.scala 2309:98] + wire _T_1133 = _T_1132 | io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 2309:120] + wire _T_1134 = mhpme3 == 10'h26; // @[dec_tlu_ctl.scala 2310:34] + wire _T_1136 = io_take_timer_int | io_take_int_timer0_int; // @[dec_tlu_ctl.scala 2310:92] + wire _T_1137 = _T_1136 | io_take_int_timer1_int; // @[dec_tlu_ctl.scala 2310:117] + wire _T_1138 = mhpme3 == 10'h27; // @[dec_tlu_ctl.scala 2311:34] + wire _T_1140 = mhpme3 == 10'h28; // @[dec_tlu_ctl.scala 2312:34] + wire _T_1142 = mhpme3 == 10'h29; // @[dec_tlu_ctl.scala 2313:34] + wire _T_1144 = io_dec_tlu_br0_error_r | io_dec_tlu_br0_start_error_r; // @[dec_tlu_ctl.scala 2313:97] + wire _T_1145 = _T_1144 & io_rfpc_i0_r; // @[dec_tlu_ctl.scala 2313:129] + wire _T_1146 = mhpme3 == 10'h2a; // @[dec_tlu_ctl.scala 2314:34] + wire _T_1148 = mhpme3 == 10'h2b; // @[dec_tlu_ctl.scala 2315:34] + wire _T_1150 = mhpme3 == 10'h2c; // @[dec_tlu_ctl.scala 2316:34] + wire _T_1152 = mhpme3 == 10'h2d; // @[dec_tlu_ctl.scala 2317:34] + wire _T_1154 = mhpme3 == 10'h2e; // @[dec_tlu_ctl.scala 2318:34] + wire _T_1156 = mhpme3 == 10'h2f; // @[dec_tlu_ctl.scala 2319:34] + wire _T_1158 = mhpme3 == 10'h30; // @[dec_tlu_ctl.scala 2320:34] + wire _T_1160 = mhpme3 == 10'h31; // @[dec_tlu_ctl.scala 2321:34] + wire _T_1164 = ~io_mstatus[0]; // @[dec_tlu_ctl.scala 2321:73] + wire _T_1165 = mhpme3 == 10'h32; // @[dec_tlu_ctl.scala 2322:34] + wire [5:0] _T_1172 = io_mip & mie; // @[dec_tlu_ctl.scala 2322:113] + wire _T_1173 = |_T_1172; // @[dec_tlu_ctl.scala 2322:125] + wire _T_1174 = _T_1164 & _T_1173; // @[dec_tlu_ctl.scala 2322:98] + wire _T_1175 = mhpme3 == 10'h36; // @[dec_tlu_ctl.scala 2323:34] + wire _T_1177 = pmu_i0_itype_qual == 4'hf; // @[dec_tlu_ctl.scala 2323:91] + wire _T_1178 = mhpme3 == 10'h37; // @[dec_tlu_ctl.scala 2324:34] + wire _T_1180 = io_tlu_i0_commit_cmt & io_lsu_pmu_load_external_r; // @[dec_tlu_ctl.scala 2324:94] + wire _T_1181 = mhpme3 == 10'h38; // @[dec_tlu_ctl.scala 2325:34] + wire _T_1183 = io_tlu_i0_commit_cmt & io_lsu_pmu_store_external_r; // @[dec_tlu_ctl.scala 2325:94] + wire _T_1184 = mhpme3 == 10'h200; // @[dec_tlu_ctl.scala 2327:34] + wire _T_1186 = mhpme3 == 10'h201; // @[dec_tlu_ctl.scala 2328:34] + wire _T_1188 = mhpme3 == 10'h202; // @[dec_tlu_ctl.scala 2329:34] + wire _T_1190 = mhpme3 == 10'h203; // @[dec_tlu_ctl.scala 2330:34] + wire _T_1192 = mhpme3 == 10'h204; // @[dec_tlu_ctl.scala 2331:34] + wire _T_1195 = _T_1029 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] + wire _T_1196 = _T_1031 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] + wire _T_1197 = _T_1033 & _T_1036; // @[Mux.scala 27:72] + wire _T_1198 = _T_1037 & _T_1042; // @[Mux.scala 27:72] + wire _T_1199 = _T_1043 & _T_1047; // @[Mux.scala 27:72] + wire _T_1200 = _T_1048 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] + wire _T_1201 = _T_1050 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] + wire _T_1202 = _T_1052 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] + wire _T_1203 = _T_1054 & _T_1056; // @[Mux.scala 27:72] + wire _T_1204 = _T_1057 & _T_1059; // @[Mux.scala 27:72] + wire _T_1205 = _T_1060 & _T_1062; // @[Mux.scala 27:72] + wire _T_1206 = _T_1063 & _T_1065; // @[Mux.scala 27:72] + wire _T_1207 = _T_1066 & _T_1069; // @[Mux.scala 27:72] + wire _T_1208 = _T_1070 & _T_1074; // @[Mux.scala 27:72] + wire _T_1209 = _T_1075 & _T_1077; // @[Mux.scala 27:72] + wire _T_1210 = _T_1078 & _T_1080; // @[Mux.scala 27:72] + wire _T_1211 = _T_1081 & _T_1083; // @[Mux.scala 27:72] + wire _T_1212 = _T_1084 & _T_1086; // @[Mux.scala 27:72] + wire _T_1213 = _T_1087 & _T_1089; // @[Mux.scala 27:72] + wire _T_1214 = _T_1090 & _T_1092; // @[Mux.scala 27:72] + wire _T_1215 = _T_1093 & _T_1095; // @[Mux.scala 27:72] + wire _T_1216 = _T_1096 & _T_1098; // @[Mux.scala 27:72] + wire _T_1217 = _T_1099 & _T_1101; // @[Mux.scala 27:72] + wire _T_1218 = _T_1102 & _T_1106; // @[Mux.scala 27:72] + wire _T_1219 = _T_1107 & _T_1109; // @[Mux.scala 27:72] + wire _T_1220 = _T_1110 & _T_1112; // @[Mux.scala 27:72] + wire _T_1221 = _T_1113 & _T_1115; // @[Mux.scala 27:72] + wire _T_1222 = _T_1116 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] + wire _T_1224 = _T_1120 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] + wire _T_1225 = _T_1122 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] + wire _T_1226 = _T_1124 & io_lsu_store_stall_any; // @[Mux.scala 27:72] + wire _T_1227 = _T_1126 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] + wire _T_1228 = _T_1128 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] + wire _T_1229 = _T_1130 & _T_1133; // @[Mux.scala 27:72] + wire _T_1230 = _T_1134 & _T_1137; // @[Mux.scala 27:72] + wire _T_1231 = _T_1138 & io_take_ext_int; // @[Mux.scala 27:72] + wire _T_1232 = _T_1140 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] + wire _T_1233 = _T_1142 & _T_1145; // @[Mux.scala 27:72] + wire _T_1234 = _T_1146 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1235 = _T_1148 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1236 = _T_1150 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] + wire _T_1237 = _T_1152 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1238 = _T_1154 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1239 = _T_1156 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1240 = _T_1158 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1241 = _T_1160 & _T_1164; // @[Mux.scala 27:72] + wire _T_1242 = _T_1165 & _T_1174; // @[Mux.scala 27:72] + wire _T_1243 = _T_1175 & _T_1177; // @[Mux.scala 27:72] + wire _T_1244 = _T_1178 & _T_1180; // @[Mux.scala 27:72] + wire _T_1245 = _T_1181 & _T_1183; // @[Mux.scala 27:72] + wire _T_1246 = _T_1184 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] + wire _T_1247 = _T_1186 & io_dma_pmu_any_read; // @[Mux.scala 27:72] + wire _T_1248 = _T_1188 & io_dma_pmu_any_write; // @[Mux.scala 27:72] + wire _T_1249 = _T_1190 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] + wire _T_1250 = _T_1192 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] + wire _T_1251 = _T_1027 | _T_1195; // @[Mux.scala 27:72] wire _T_1252 = _T_1251 | _T_1196; // @[Mux.scala 27:72] wire _T_1253 = _T_1252 | _T_1197; // @[Mux.scala 27:72] wire _T_1254 = _T_1253 | _T_1198; // @[Mux.scala 27:72] @@ -51585,8 +51624,8 @@ module csr_tlu( wire _T_1275 = _T_1274 | _T_1219; // @[Mux.scala 27:72] wire _T_1276 = _T_1275 | _T_1220; // @[Mux.scala 27:72] wire _T_1277 = _T_1276 | _T_1221; // @[Mux.scala 27:72] - wire _T_1278 = _T_1277 | _T_1201; // @[Mux.scala 27:72] - wire _T_1279 = _T_1278 | _T_1223; // @[Mux.scala 27:72] + wire _T_1278 = _T_1277 | _T_1222; // @[Mux.scala 27:72] + wire _T_1279 = _T_1278 | _T_1202; // @[Mux.scala 27:72] wire _T_1280 = _T_1279 | _T_1224; // @[Mux.scala 27:72] wire _T_1281 = _T_1280 | _T_1225; // @[Mux.scala 27:72] wire _T_1282 = _T_1281 | _T_1226; // @[Mux.scala 27:72] @@ -51613,122 +51652,122 @@ module csr_tlu( wire _T_1303 = _T_1302 | _T_1247; // @[Mux.scala 27:72] wire _T_1304 = _T_1303 | _T_1248; // @[Mux.scala 27:72] wire _T_1305 = _T_1304 | _T_1249; // @[Mux.scala 27:72] - wire mhpmc_inc_r_0 = _T_1025 & _T_1305; // @[dec_tlu_ctl.scala 2273:44] - wire _T_1309 = ~mcountinhibit[4]; // @[dec_tlu_ctl.scala 2273:24] + wire _T_1306 = _T_1305 | _T_1250; // @[Mux.scala 27:72] + wire mhpmc_inc_r_0 = _T_1026 & _T_1306; // @[dec_tlu_ctl.scala 2273:44] + wire _T_1310 = ~mcountinhibit[4]; // @[dec_tlu_ctl.scala 2273:24] reg [9:0] mhpme4; // @[Reg.scala 27:20] - wire _T_1310 = mhpme4 == 10'h1; // @[dec_tlu_ctl.scala 2274:34] - wire _T_1312 = mhpme4 == 10'h2; // @[dec_tlu_ctl.scala 2275:34] - wire _T_1314 = mhpme4 == 10'h3; // @[dec_tlu_ctl.scala 2276:34] - wire _T_1316 = mhpme4 == 10'h4; // @[dec_tlu_ctl.scala 2277:34] - wire _T_1320 = mhpme4 == 10'h5; // @[dec_tlu_ctl.scala 2278:34] - wire _T_1326 = mhpme4 == 10'h6; // @[dec_tlu_ctl.scala 2279:34] - wire _T_1331 = mhpme4 == 10'h7; // @[dec_tlu_ctl.scala 2280:34] - wire _T_1333 = mhpme4 == 10'h8; // @[dec_tlu_ctl.scala 2281:34] - wire _T_1335 = mhpme4 == 10'h1e; // @[dec_tlu_ctl.scala 2282:34] - wire _T_1337 = mhpme4 == 10'h9; // @[dec_tlu_ctl.scala 2283:34] - wire _T_1340 = mhpme4 == 10'ha; // @[dec_tlu_ctl.scala 2284:34] - wire _T_1343 = mhpme4 == 10'hb; // @[dec_tlu_ctl.scala 2285:34] - wire _T_1346 = mhpme4 == 10'hc; // @[dec_tlu_ctl.scala 2286:34] - wire _T_1349 = mhpme4 == 10'hd; // @[dec_tlu_ctl.scala 2287:34] - wire _T_1353 = mhpme4 == 10'he; // @[dec_tlu_ctl.scala 2288:34] - wire _T_1358 = mhpme4 == 10'hf; // @[dec_tlu_ctl.scala 2289:34] - wire _T_1361 = mhpme4 == 10'h10; // @[dec_tlu_ctl.scala 2290:34] - wire _T_1364 = mhpme4 == 10'h12; // @[dec_tlu_ctl.scala 2291:34] - wire _T_1367 = mhpme4 == 10'h11; // @[dec_tlu_ctl.scala 2292:34] - wire _T_1370 = mhpme4 == 10'h13; // @[dec_tlu_ctl.scala 2293:34] - wire _T_1373 = mhpme4 == 10'h14; // @[dec_tlu_ctl.scala 2294:34] - wire _T_1376 = mhpme4 == 10'h15; // @[dec_tlu_ctl.scala 2295:34] - wire _T_1379 = mhpme4 == 10'h16; // @[dec_tlu_ctl.scala 2296:34] - wire _T_1382 = mhpme4 == 10'h17; // @[dec_tlu_ctl.scala 2297:34] - wire _T_1385 = mhpme4 == 10'h18; // @[dec_tlu_ctl.scala 2298:34] - wire _T_1390 = mhpme4 == 10'h19; // @[dec_tlu_ctl.scala 2299:34] - wire _T_1393 = mhpme4 == 10'h1a; // @[dec_tlu_ctl.scala 2300:34] - wire _T_1396 = mhpme4 == 10'h1b; // @[dec_tlu_ctl.scala 2301:34] - wire _T_1399 = mhpme4 == 10'h1c; // @[dec_tlu_ctl.scala 2302:34] - wire _T_1403 = mhpme4 == 10'h1f; // @[dec_tlu_ctl.scala 2304:34] - wire _T_1405 = mhpme4 == 10'h20; // @[dec_tlu_ctl.scala 2305:34] - wire _T_1407 = mhpme4 == 10'h22; // @[dec_tlu_ctl.scala 2306:34] - wire _T_1409 = mhpme4 == 10'h23; // @[dec_tlu_ctl.scala 2307:34] - wire _T_1411 = mhpme4 == 10'h24; // @[dec_tlu_ctl.scala 2308:34] - wire _T_1413 = mhpme4 == 10'h25; // @[dec_tlu_ctl.scala 2309:34] - wire _T_1417 = mhpme4 == 10'h26; // @[dec_tlu_ctl.scala 2310:34] - wire _T_1421 = mhpme4 == 10'h27; // @[dec_tlu_ctl.scala 2311:34] - wire _T_1423 = mhpme4 == 10'h28; // @[dec_tlu_ctl.scala 2312:34] - wire _T_1425 = mhpme4 == 10'h29; // @[dec_tlu_ctl.scala 2313:34] - wire _T_1429 = mhpme4 == 10'h2a; // @[dec_tlu_ctl.scala 2314:34] - wire _T_1431 = mhpme4 == 10'h2b; // @[dec_tlu_ctl.scala 2315:34] - wire _T_1433 = mhpme4 == 10'h2c; // @[dec_tlu_ctl.scala 2316:34] - wire _T_1435 = mhpme4 == 10'h2d; // @[dec_tlu_ctl.scala 2317:34] - wire _T_1437 = mhpme4 == 10'h2e; // @[dec_tlu_ctl.scala 2318:34] - wire _T_1439 = mhpme4 == 10'h2f; // @[dec_tlu_ctl.scala 2319:34] - wire _T_1441 = mhpme4 == 10'h30; // @[dec_tlu_ctl.scala 2320:34] - wire _T_1443 = mhpme4 == 10'h31; // @[dec_tlu_ctl.scala 2321:34] - wire _T_1448 = mhpme4 == 10'h32; // @[dec_tlu_ctl.scala 2322:34] - wire _T_1458 = mhpme4 == 10'h36; // @[dec_tlu_ctl.scala 2323:34] - wire _T_1461 = mhpme4 == 10'h37; // @[dec_tlu_ctl.scala 2324:34] - wire _T_1464 = mhpme4 == 10'h38; // @[dec_tlu_ctl.scala 2325:34] - wire _T_1467 = mhpme4 == 10'h200; // @[dec_tlu_ctl.scala 2327:34] - wire _T_1469 = mhpme4 == 10'h201; // @[dec_tlu_ctl.scala 2328:34] - wire _T_1471 = mhpme4 == 10'h202; // @[dec_tlu_ctl.scala 2329:34] - wire _T_1473 = mhpme4 == 10'h203; // @[dec_tlu_ctl.scala 2330:34] - wire _T_1475 = mhpme4 == 10'h204; // @[dec_tlu_ctl.scala 2331:34] - wire _T_1478 = _T_1312 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] - wire _T_1479 = _T_1314 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] - wire _T_1480 = _T_1316 & _T_1035; // @[Mux.scala 27:72] - wire _T_1481 = _T_1320 & _T_1041; // @[Mux.scala 27:72] - wire _T_1482 = _T_1326 & _T_1046; // @[Mux.scala 27:72] - wire _T_1483 = _T_1331 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] - wire _T_1484 = _T_1333 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] - wire _T_1485 = _T_1335 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] - wire _T_1486 = _T_1337 & _T_1055; // @[Mux.scala 27:72] - wire _T_1487 = _T_1340 & _T_1058; // @[Mux.scala 27:72] - wire _T_1488 = _T_1343 & _T_1061; // @[Mux.scala 27:72] - wire _T_1489 = _T_1346 & _T_1064; // @[Mux.scala 27:72] - wire _T_1490 = _T_1349 & _T_1068; // @[Mux.scala 27:72] - wire _T_1491 = _T_1353 & _T_1073; // @[Mux.scala 27:72] - wire _T_1492 = _T_1358 & _T_1076; // @[Mux.scala 27:72] - wire _T_1493 = _T_1361 & _T_1079; // @[Mux.scala 27:72] - wire _T_1494 = _T_1364 & _T_1082; // @[Mux.scala 27:72] - wire _T_1495 = _T_1367 & _T_1085; // @[Mux.scala 27:72] - wire _T_1496 = _T_1370 & _T_1088; // @[Mux.scala 27:72] - wire _T_1497 = _T_1373 & _T_1091; // @[Mux.scala 27:72] - wire _T_1498 = _T_1376 & _T_1094; // @[Mux.scala 27:72] - wire _T_1499 = _T_1379 & _T_1097; // @[Mux.scala 27:72] - wire _T_1500 = _T_1382 & _T_1100; // @[Mux.scala 27:72] - wire _T_1501 = _T_1385 & _T_1105; // @[Mux.scala 27:72] - wire _T_1502 = _T_1390 & _T_1108; // @[Mux.scala 27:72] - wire _T_1503 = _T_1393 & _T_1111; // @[Mux.scala 27:72] - wire _T_1504 = _T_1396 & _T_1114; // @[Mux.scala 27:72] - wire _T_1505 = _T_1399 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] - wire _T_1507 = _T_1403 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] - wire _T_1508 = _T_1405 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] - wire _T_1509 = _T_1407 & io_lsu_store_stall_any; // @[Mux.scala 27:72] - wire _T_1510 = _T_1409 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] - wire _T_1511 = _T_1411 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] - wire _T_1512 = _T_1413 & _T_1132; // @[Mux.scala 27:72] - wire _T_1513 = _T_1417 & _T_1136; // @[Mux.scala 27:72] - wire _T_1514 = _T_1421 & io_take_ext_int; // @[Mux.scala 27:72] - wire _T_1515 = _T_1423 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] - wire _T_1516 = _T_1425 & _T_1144; // @[Mux.scala 27:72] - wire _T_1517 = _T_1429 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_1518 = _T_1431 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_1519 = _T_1433 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] - wire _T_1520 = _T_1435 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_1521 = _T_1437 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_1522 = _T_1439 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_1523 = _T_1441 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_1524 = _T_1443 & _T_1163; // @[Mux.scala 27:72] - wire _T_1525 = _T_1448 & _T_1173; // @[Mux.scala 27:72] - wire _T_1526 = _T_1458 & _T_1176; // @[Mux.scala 27:72] - wire _T_1527 = _T_1461 & _T_1179; // @[Mux.scala 27:72] - wire _T_1528 = _T_1464 & _T_1182; // @[Mux.scala 27:72] - wire _T_1529 = _T_1467 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] - wire _T_1530 = _T_1469 & io_dma_pmu_any_read; // @[Mux.scala 27:72] - wire _T_1531 = _T_1471 & io_dma_pmu_any_write; // @[Mux.scala 27:72] - wire _T_1532 = _T_1473 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] - wire _T_1533 = _T_1475 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] - wire _T_1534 = _T_1310 | _T_1478; // @[Mux.scala 27:72] - wire _T_1535 = _T_1534 | _T_1479; // @[Mux.scala 27:72] + wire _T_1311 = mhpme4 == 10'h1; // @[dec_tlu_ctl.scala 2274:34] + wire _T_1313 = mhpme4 == 10'h2; // @[dec_tlu_ctl.scala 2275:34] + wire _T_1315 = mhpme4 == 10'h3; // @[dec_tlu_ctl.scala 2276:34] + wire _T_1317 = mhpme4 == 10'h4; // @[dec_tlu_ctl.scala 2277:34] + wire _T_1321 = mhpme4 == 10'h5; // @[dec_tlu_ctl.scala 2278:34] + wire _T_1327 = mhpme4 == 10'h6; // @[dec_tlu_ctl.scala 2279:34] + wire _T_1332 = mhpme4 == 10'h7; // @[dec_tlu_ctl.scala 2280:34] + wire _T_1334 = mhpme4 == 10'h8; // @[dec_tlu_ctl.scala 2281:34] + wire _T_1336 = mhpme4 == 10'h1e; // @[dec_tlu_ctl.scala 2282:34] + wire _T_1338 = mhpme4 == 10'h9; // @[dec_tlu_ctl.scala 2283:34] + wire _T_1341 = mhpme4 == 10'ha; // @[dec_tlu_ctl.scala 2284:34] + wire _T_1344 = mhpme4 == 10'hb; // @[dec_tlu_ctl.scala 2285:34] + wire _T_1347 = mhpme4 == 10'hc; // @[dec_tlu_ctl.scala 2286:34] + wire _T_1350 = mhpme4 == 10'hd; // @[dec_tlu_ctl.scala 2287:34] + wire _T_1354 = mhpme4 == 10'he; // @[dec_tlu_ctl.scala 2288:34] + wire _T_1359 = mhpme4 == 10'hf; // @[dec_tlu_ctl.scala 2289:34] + wire _T_1362 = mhpme4 == 10'h10; // @[dec_tlu_ctl.scala 2290:34] + wire _T_1365 = mhpme4 == 10'h12; // @[dec_tlu_ctl.scala 2291:34] + wire _T_1368 = mhpme4 == 10'h11; // @[dec_tlu_ctl.scala 2292:34] + wire _T_1371 = mhpme4 == 10'h13; // @[dec_tlu_ctl.scala 2293:34] + wire _T_1374 = mhpme4 == 10'h14; // @[dec_tlu_ctl.scala 2294:34] + wire _T_1377 = mhpme4 == 10'h15; // @[dec_tlu_ctl.scala 2295:34] + wire _T_1380 = mhpme4 == 10'h16; // @[dec_tlu_ctl.scala 2296:34] + wire _T_1383 = mhpme4 == 10'h17; // @[dec_tlu_ctl.scala 2297:34] + wire _T_1386 = mhpme4 == 10'h18; // @[dec_tlu_ctl.scala 2298:34] + wire _T_1391 = mhpme4 == 10'h19; // @[dec_tlu_ctl.scala 2299:34] + wire _T_1394 = mhpme4 == 10'h1a; // @[dec_tlu_ctl.scala 2300:34] + wire _T_1397 = mhpme4 == 10'h1b; // @[dec_tlu_ctl.scala 2301:34] + wire _T_1400 = mhpme4 == 10'h1c; // @[dec_tlu_ctl.scala 2302:34] + wire _T_1404 = mhpme4 == 10'h1f; // @[dec_tlu_ctl.scala 2304:34] + wire _T_1406 = mhpme4 == 10'h20; // @[dec_tlu_ctl.scala 2305:34] + wire _T_1408 = mhpme4 == 10'h22; // @[dec_tlu_ctl.scala 2306:34] + wire _T_1410 = mhpme4 == 10'h23; // @[dec_tlu_ctl.scala 2307:34] + wire _T_1412 = mhpme4 == 10'h24; // @[dec_tlu_ctl.scala 2308:34] + wire _T_1414 = mhpme4 == 10'h25; // @[dec_tlu_ctl.scala 2309:34] + wire _T_1418 = mhpme4 == 10'h26; // @[dec_tlu_ctl.scala 2310:34] + wire _T_1422 = mhpme4 == 10'h27; // @[dec_tlu_ctl.scala 2311:34] + wire _T_1424 = mhpme4 == 10'h28; // @[dec_tlu_ctl.scala 2312:34] + wire _T_1426 = mhpme4 == 10'h29; // @[dec_tlu_ctl.scala 2313:34] + wire _T_1430 = mhpme4 == 10'h2a; // @[dec_tlu_ctl.scala 2314:34] + wire _T_1432 = mhpme4 == 10'h2b; // @[dec_tlu_ctl.scala 2315:34] + wire _T_1434 = mhpme4 == 10'h2c; // @[dec_tlu_ctl.scala 2316:34] + wire _T_1436 = mhpme4 == 10'h2d; // @[dec_tlu_ctl.scala 2317:34] + wire _T_1438 = mhpme4 == 10'h2e; // @[dec_tlu_ctl.scala 2318:34] + wire _T_1440 = mhpme4 == 10'h2f; // @[dec_tlu_ctl.scala 2319:34] + wire _T_1442 = mhpme4 == 10'h30; // @[dec_tlu_ctl.scala 2320:34] + wire _T_1444 = mhpme4 == 10'h31; // @[dec_tlu_ctl.scala 2321:34] + wire _T_1449 = mhpme4 == 10'h32; // @[dec_tlu_ctl.scala 2322:34] + wire _T_1459 = mhpme4 == 10'h36; // @[dec_tlu_ctl.scala 2323:34] + wire _T_1462 = mhpme4 == 10'h37; // @[dec_tlu_ctl.scala 2324:34] + wire _T_1465 = mhpme4 == 10'h38; // @[dec_tlu_ctl.scala 2325:34] + wire _T_1468 = mhpme4 == 10'h200; // @[dec_tlu_ctl.scala 2327:34] + wire _T_1470 = mhpme4 == 10'h201; // @[dec_tlu_ctl.scala 2328:34] + wire _T_1472 = mhpme4 == 10'h202; // @[dec_tlu_ctl.scala 2329:34] + wire _T_1474 = mhpme4 == 10'h203; // @[dec_tlu_ctl.scala 2330:34] + wire _T_1476 = mhpme4 == 10'h204; // @[dec_tlu_ctl.scala 2331:34] + wire _T_1479 = _T_1313 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] + wire _T_1480 = _T_1315 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] + wire _T_1481 = _T_1317 & _T_1036; // @[Mux.scala 27:72] + wire _T_1482 = _T_1321 & _T_1042; // @[Mux.scala 27:72] + wire _T_1483 = _T_1327 & _T_1047; // @[Mux.scala 27:72] + wire _T_1484 = _T_1332 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] + wire _T_1485 = _T_1334 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] + wire _T_1486 = _T_1336 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] + wire _T_1487 = _T_1338 & _T_1056; // @[Mux.scala 27:72] + wire _T_1488 = _T_1341 & _T_1059; // @[Mux.scala 27:72] + wire _T_1489 = _T_1344 & _T_1062; // @[Mux.scala 27:72] + wire _T_1490 = _T_1347 & _T_1065; // @[Mux.scala 27:72] + wire _T_1491 = _T_1350 & _T_1069; // @[Mux.scala 27:72] + wire _T_1492 = _T_1354 & _T_1074; // @[Mux.scala 27:72] + wire _T_1493 = _T_1359 & _T_1077; // @[Mux.scala 27:72] + wire _T_1494 = _T_1362 & _T_1080; // @[Mux.scala 27:72] + wire _T_1495 = _T_1365 & _T_1083; // @[Mux.scala 27:72] + wire _T_1496 = _T_1368 & _T_1086; // @[Mux.scala 27:72] + wire _T_1497 = _T_1371 & _T_1089; // @[Mux.scala 27:72] + wire _T_1498 = _T_1374 & _T_1092; // @[Mux.scala 27:72] + wire _T_1499 = _T_1377 & _T_1095; // @[Mux.scala 27:72] + wire _T_1500 = _T_1380 & _T_1098; // @[Mux.scala 27:72] + wire _T_1501 = _T_1383 & _T_1101; // @[Mux.scala 27:72] + wire _T_1502 = _T_1386 & _T_1106; // @[Mux.scala 27:72] + wire _T_1503 = _T_1391 & _T_1109; // @[Mux.scala 27:72] + wire _T_1504 = _T_1394 & _T_1112; // @[Mux.scala 27:72] + wire _T_1505 = _T_1397 & _T_1115; // @[Mux.scala 27:72] + wire _T_1506 = _T_1400 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] + wire _T_1508 = _T_1404 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] + wire _T_1509 = _T_1406 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] + wire _T_1510 = _T_1408 & io_lsu_store_stall_any; // @[Mux.scala 27:72] + wire _T_1511 = _T_1410 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] + wire _T_1512 = _T_1412 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] + wire _T_1513 = _T_1414 & _T_1133; // @[Mux.scala 27:72] + wire _T_1514 = _T_1418 & _T_1137; // @[Mux.scala 27:72] + wire _T_1515 = _T_1422 & io_take_ext_int; // @[Mux.scala 27:72] + wire _T_1516 = _T_1424 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] + wire _T_1517 = _T_1426 & _T_1145; // @[Mux.scala 27:72] + wire _T_1518 = _T_1430 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1519 = _T_1432 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1520 = _T_1434 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] + wire _T_1521 = _T_1436 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1522 = _T_1438 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1523 = _T_1440 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1524 = _T_1442 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1525 = _T_1444 & _T_1164; // @[Mux.scala 27:72] + wire _T_1526 = _T_1449 & _T_1174; // @[Mux.scala 27:72] + wire _T_1527 = _T_1459 & _T_1177; // @[Mux.scala 27:72] + wire _T_1528 = _T_1462 & _T_1180; // @[Mux.scala 27:72] + wire _T_1529 = _T_1465 & _T_1183; // @[Mux.scala 27:72] + wire _T_1530 = _T_1468 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] + wire _T_1531 = _T_1470 & io_dma_pmu_any_read; // @[Mux.scala 27:72] + wire _T_1532 = _T_1472 & io_dma_pmu_any_write; // @[Mux.scala 27:72] + wire _T_1533 = _T_1474 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] + wire _T_1534 = _T_1476 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] + wire _T_1535 = _T_1311 | _T_1479; // @[Mux.scala 27:72] wire _T_1536 = _T_1535 | _T_1480; // @[Mux.scala 27:72] wire _T_1537 = _T_1536 | _T_1481; // @[Mux.scala 27:72] wire _T_1538 = _T_1537 | _T_1482; // @[Mux.scala 27:72] @@ -51755,8 +51794,8 @@ module csr_tlu( wire _T_1559 = _T_1558 | _T_1503; // @[Mux.scala 27:72] wire _T_1560 = _T_1559 | _T_1504; // @[Mux.scala 27:72] wire _T_1561 = _T_1560 | _T_1505; // @[Mux.scala 27:72] - wire _T_1562 = _T_1561 | _T_1485; // @[Mux.scala 27:72] - wire _T_1563 = _T_1562 | _T_1507; // @[Mux.scala 27:72] + wire _T_1562 = _T_1561 | _T_1506; // @[Mux.scala 27:72] + wire _T_1563 = _T_1562 | _T_1486; // @[Mux.scala 27:72] wire _T_1564 = _T_1563 | _T_1508; // @[Mux.scala 27:72] wire _T_1565 = _T_1564 | _T_1509; // @[Mux.scala 27:72] wire _T_1566 = _T_1565 | _T_1510; // @[Mux.scala 27:72] @@ -51783,122 +51822,122 @@ module csr_tlu( wire _T_1587 = _T_1586 | _T_1531; // @[Mux.scala 27:72] wire _T_1588 = _T_1587 | _T_1532; // @[Mux.scala 27:72] wire _T_1589 = _T_1588 | _T_1533; // @[Mux.scala 27:72] - wire mhpmc_inc_r_1 = _T_1309 & _T_1589; // @[dec_tlu_ctl.scala 2273:44] - wire _T_1593 = ~mcountinhibit[5]; // @[dec_tlu_ctl.scala 2273:24] + wire _T_1590 = _T_1589 | _T_1534; // @[Mux.scala 27:72] + wire mhpmc_inc_r_1 = _T_1310 & _T_1590; // @[dec_tlu_ctl.scala 2273:44] + wire _T_1594 = ~mcountinhibit[5]; // @[dec_tlu_ctl.scala 2273:24] reg [9:0] mhpme5; // @[Reg.scala 27:20] - wire _T_1594 = mhpme5 == 10'h1; // @[dec_tlu_ctl.scala 2274:34] - wire _T_1596 = mhpme5 == 10'h2; // @[dec_tlu_ctl.scala 2275:34] - wire _T_1598 = mhpme5 == 10'h3; // @[dec_tlu_ctl.scala 2276:34] - wire _T_1600 = mhpme5 == 10'h4; // @[dec_tlu_ctl.scala 2277:34] - wire _T_1604 = mhpme5 == 10'h5; // @[dec_tlu_ctl.scala 2278:34] - wire _T_1610 = mhpme5 == 10'h6; // @[dec_tlu_ctl.scala 2279:34] - wire _T_1615 = mhpme5 == 10'h7; // @[dec_tlu_ctl.scala 2280:34] - wire _T_1617 = mhpme5 == 10'h8; // @[dec_tlu_ctl.scala 2281:34] - wire _T_1619 = mhpme5 == 10'h1e; // @[dec_tlu_ctl.scala 2282:34] - wire _T_1621 = mhpme5 == 10'h9; // @[dec_tlu_ctl.scala 2283:34] - wire _T_1624 = mhpme5 == 10'ha; // @[dec_tlu_ctl.scala 2284:34] - wire _T_1627 = mhpme5 == 10'hb; // @[dec_tlu_ctl.scala 2285:34] - wire _T_1630 = mhpme5 == 10'hc; // @[dec_tlu_ctl.scala 2286:34] - wire _T_1633 = mhpme5 == 10'hd; // @[dec_tlu_ctl.scala 2287:34] - wire _T_1637 = mhpme5 == 10'he; // @[dec_tlu_ctl.scala 2288:34] - wire _T_1642 = mhpme5 == 10'hf; // @[dec_tlu_ctl.scala 2289:34] - wire _T_1645 = mhpme5 == 10'h10; // @[dec_tlu_ctl.scala 2290:34] - wire _T_1648 = mhpme5 == 10'h12; // @[dec_tlu_ctl.scala 2291:34] - wire _T_1651 = mhpme5 == 10'h11; // @[dec_tlu_ctl.scala 2292:34] - wire _T_1654 = mhpme5 == 10'h13; // @[dec_tlu_ctl.scala 2293:34] - wire _T_1657 = mhpme5 == 10'h14; // @[dec_tlu_ctl.scala 2294:34] - wire _T_1660 = mhpme5 == 10'h15; // @[dec_tlu_ctl.scala 2295:34] - wire _T_1663 = mhpme5 == 10'h16; // @[dec_tlu_ctl.scala 2296:34] - wire _T_1666 = mhpme5 == 10'h17; // @[dec_tlu_ctl.scala 2297:34] - wire _T_1669 = mhpme5 == 10'h18; // @[dec_tlu_ctl.scala 2298:34] - wire _T_1674 = mhpme5 == 10'h19; // @[dec_tlu_ctl.scala 2299:34] - wire _T_1677 = mhpme5 == 10'h1a; // @[dec_tlu_ctl.scala 2300:34] - wire _T_1680 = mhpme5 == 10'h1b; // @[dec_tlu_ctl.scala 2301:34] - wire _T_1683 = mhpme5 == 10'h1c; // @[dec_tlu_ctl.scala 2302:34] - wire _T_1687 = mhpme5 == 10'h1f; // @[dec_tlu_ctl.scala 2304:34] - wire _T_1689 = mhpme5 == 10'h20; // @[dec_tlu_ctl.scala 2305:34] - wire _T_1691 = mhpme5 == 10'h22; // @[dec_tlu_ctl.scala 2306:34] - wire _T_1693 = mhpme5 == 10'h23; // @[dec_tlu_ctl.scala 2307:34] - wire _T_1695 = mhpme5 == 10'h24; // @[dec_tlu_ctl.scala 2308:34] - wire _T_1697 = mhpme5 == 10'h25; // @[dec_tlu_ctl.scala 2309:34] - wire _T_1701 = mhpme5 == 10'h26; // @[dec_tlu_ctl.scala 2310:34] - wire _T_1705 = mhpme5 == 10'h27; // @[dec_tlu_ctl.scala 2311:34] - wire _T_1707 = mhpme5 == 10'h28; // @[dec_tlu_ctl.scala 2312:34] - wire _T_1709 = mhpme5 == 10'h29; // @[dec_tlu_ctl.scala 2313:34] - wire _T_1713 = mhpme5 == 10'h2a; // @[dec_tlu_ctl.scala 2314:34] - wire _T_1715 = mhpme5 == 10'h2b; // @[dec_tlu_ctl.scala 2315:34] - wire _T_1717 = mhpme5 == 10'h2c; // @[dec_tlu_ctl.scala 2316:34] - wire _T_1719 = mhpme5 == 10'h2d; // @[dec_tlu_ctl.scala 2317:34] - wire _T_1721 = mhpme5 == 10'h2e; // @[dec_tlu_ctl.scala 2318:34] - wire _T_1723 = mhpme5 == 10'h2f; // @[dec_tlu_ctl.scala 2319:34] - wire _T_1725 = mhpme5 == 10'h30; // @[dec_tlu_ctl.scala 2320:34] - wire _T_1727 = mhpme5 == 10'h31; // @[dec_tlu_ctl.scala 2321:34] - wire _T_1732 = mhpme5 == 10'h32; // @[dec_tlu_ctl.scala 2322:34] - wire _T_1742 = mhpme5 == 10'h36; // @[dec_tlu_ctl.scala 2323:34] - wire _T_1745 = mhpme5 == 10'h37; // @[dec_tlu_ctl.scala 2324:34] - wire _T_1748 = mhpme5 == 10'h38; // @[dec_tlu_ctl.scala 2325:34] - wire _T_1751 = mhpme5 == 10'h200; // @[dec_tlu_ctl.scala 2327:34] - wire _T_1753 = mhpme5 == 10'h201; // @[dec_tlu_ctl.scala 2328:34] - wire _T_1755 = mhpme5 == 10'h202; // @[dec_tlu_ctl.scala 2329:34] - wire _T_1757 = mhpme5 == 10'h203; // @[dec_tlu_ctl.scala 2330:34] - wire _T_1759 = mhpme5 == 10'h204; // @[dec_tlu_ctl.scala 2331:34] - wire _T_1762 = _T_1596 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] - wire _T_1763 = _T_1598 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] - wire _T_1764 = _T_1600 & _T_1035; // @[Mux.scala 27:72] - wire _T_1765 = _T_1604 & _T_1041; // @[Mux.scala 27:72] - wire _T_1766 = _T_1610 & _T_1046; // @[Mux.scala 27:72] - wire _T_1767 = _T_1615 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] - wire _T_1768 = _T_1617 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] - wire _T_1769 = _T_1619 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] - wire _T_1770 = _T_1621 & _T_1055; // @[Mux.scala 27:72] - wire _T_1771 = _T_1624 & _T_1058; // @[Mux.scala 27:72] - wire _T_1772 = _T_1627 & _T_1061; // @[Mux.scala 27:72] - wire _T_1773 = _T_1630 & _T_1064; // @[Mux.scala 27:72] - wire _T_1774 = _T_1633 & _T_1068; // @[Mux.scala 27:72] - wire _T_1775 = _T_1637 & _T_1073; // @[Mux.scala 27:72] - wire _T_1776 = _T_1642 & _T_1076; // @[Mux.scala 27:72] - wire _T_1777 = _T_1645 & _T_1079; // @[Mux.scala 27:72] - wire _T_1778 = _T_1648 & _T_1082; // @[Mux.scala 27:72] - wire _T_1779 = _T_1651 & _T_1085; // @[Mux.scala 27:72] - wire _T_1780 = _T_1654 & _T_1088; // @[Mux.scala 27:72] - wire _T_1781 = _T_1657 & _T_1091; // @[Mux.scala 27:72] - wire _T_1782 = _T_1660 & _T_1094; // @[Mux.scala 27:72] - wire _T_1783 = _T_1663 & _T_1097; // @[Mux.scala 27:72] - wire _T_1784 = _T_1666 & _T_1100; // @[Mux.scala 27:72] - wire _T_1785 = _T_1669 & _T_1105; // @[Mux.scala 27:72] - wire _T_1786 = _T_1674 & _T_1108; // @[Mux.scala 27:72] - wire _T_1787 = _T_1677 & _T_1111; // @[Mux.scala 27:72] - wire _T_1788 = _T_1680 & _T_1114; // @[Mux.scala 27:72] - wire _T_1789 = _T_1683 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] - wire _T_1791 = _T_1687 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] - wire _T_1792 = _T_1689 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] - wire _T_1793 = _T_1691 & io_lsu_store_stall_any; // @[Mux.scala 27:72] - wire _T_1794 = _T_1693 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] - wire _T_1795 = _T_1695 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] - wire _T_1796 = _T_1697 & _T_1132; // @[Mux.scala 27:72] - wire _T_1797 = _T_1701 & _T_1136; // @[Mux.scala 27:72] - wire _T_1798 = _T_1705 & io_take_ext_int; // @[Mux.scala 27:72] - wire _T_1799 = _T_1707 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] - wire _T_1800 = _T_1709 & _T_1144; // @[Mux.scala 27:72] - wire _T_1801 = _T_1713 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_1802 = _T_1715 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_1803 = _T_1717 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] - wire _T_1804 = _T_1719 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_1805 = _T_1721 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_1806 = _T_1723 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_1807 = _T_1725 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_1808 = _T_1727 & _T_1163; // @[Mux.scala 27:72] - wire _T_1809 = _T_1732 & _T_1173; // @[Mux.scala 27:72] - wire _T_1810 = _T_1742 & _T_1176; // @[Mux.scala 27:72] - wire _T_1811 = _T_1745 & _T_1179; // @[Mux.scala 27:72] - wire _T_1812 = _T_1748 & _T_1182; // @[Mux.scala 27:72] - wire _T_1813 = _T_1751 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] - wire _T_1814 = _T_1753 & io_dma_pmu_any_read; // @[Mux.scala 27:72] - wire _T_1815 = _T_1755 & io_dma_pmu_any_write; // @[Mux.scala 27:72] - wire _T_1816 = _T_1757 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] - wire _T_1817 = _T_1759 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] - wire _T_1818 = _T_1594 | _T_1762; // @[Mux.scala 27:72] - wire _T_1819 = _T_1818 | _T_1763; // @[Mux.scala 27:72] + wire _T_1595 = mhpme5 == 10'h1; // @[dec_tlu_ctl.scala 2274:34] + wire _T_1597 = mhpme5 == 10'h2; // @[dec_tlu_ctl.scala 2275:34] + wire _T_1599 = mhpme5 == 10'h3; // @[dec_tlu_ctl.scala 2276:34] + wire _T_1601 = mhpme5 == 10'h4; // @[dec_tlu_ctl.scala 2277:34] + wire _T_1605 = mhpme5 == 10'h5; // @[dec_tlu_ctl.scala 2278:34] + wire _T_1611 = mhpme5 == 10'h6; // @[dec_tlu_ctl.scala 2279:34] + wire _T_1616 = mhpme5 == 10'h7; // @[dec_tlu_ctl.scala 2280:34] + wire _T_1618 = mhpme5 == 10'h8; // @[dec_tlu_ctl.scala 2281:34] + wire _T_1620 = mhpme5 == 10'h1e; // @[dec_tlu_ctl.scala 2282:34] + wire _T_1622 = mhpme5 == 10'h9; // @[dec_tlu_ctl.scala 2283:34] + wire _T_1625 = mhpme5 == 10'ha; // @[dec_tlu_ctl.scala 2284:34] + wire _T_1628 = mhpme5 == 10'hb; // @[dec_tlu_ctl.scala 2285:34] + wire _T_1631 = mhpme5 == 10'hc; // @[dec_tlu_ctl.scala 2286:34] + wire _T_1634 = mhpme5 == 10'hd; // @[dec_tlu_ctl.scala 2287:34] + wire _T_1638 = mhpme5 == 10'he; // @[dec_tlu_ctl.scala 2288:34] + wire _T_1643 = mhpme5 == 10'hf; // @[dec_tlu_ctl.scala 2289:34] + wire _T_1646 = mhpme5 == 10'h10; // @[dec_tlu_ctl.scala 2290:34] + wire _T_1649 = mhpme5 == 10'h12; // @[dec_tlu_ctl.scala 2291:34] + wire _T_1652 = mhpme5 == 10'h11; // @[dec_tlu_ctl.scala 2292:34] + wire _T_1655 = mhpme5 == 10'h13; // @[dec_tlu_ctl.scala 2293:34] + wire _T_1658 = mhpme5 == 10'h14; // @[dec_tlu_ctl.scala 2294:34] + wire _T_1661 = mhpme5 == 10'h15; // @[dec_tlu_ctl.scala 2295:34] + wire _T_1664 = mhpme5 == 10'h16; // @[dec_tlu_ctl.scala 2296:34] + wire _T_1667 = mhpme5 == 10'h17; // @[dec_tlu_ctl.scala 2297:34] + wire _T_1670 = mhpme5 == 10'h18; // @[dec_tlu_ctl.scala 2298:34] + wire _T_1675 = mhpme5 == 10'h19; // @[dec_tlu_ctl.scala 2299:34] + wire _T_1678 = mhpme5 == 10'h1a; // @[dec_tlu_ctl.scala 2300:34] + wire _T_1681 = mhpme5 == 10'h1b; // @[dec_tlu_ctl.scala 2301:34] + wire _T_1684 = mhpme5 == 10'h1c; // @[dec_tlu_ctl.scala 2302:34] + wire _T_1688 = mhpme5 == 10'h1f; // @[dec_tlu_ctl.scala 2304:34] + wire _T_1690 = mhpme5 == 10'h20; // @[dec_tlu_ctl.scala 2305:34] + wire _T_1692 = mhpme5 == 10'h22; // @[dec_tlu_ctl.scala 2306:34] + wire _T_1694 = mhpme5 == 10'h23; // @[dec_tlu_ctl.scala 2307:34] + wire _T_1696 = mhpme5 == 10'h24; // @[dec_tlu_ctl.scala 2308:34] + wire _T_1698 = mhpme5 == 10'h25; // @[dec_tlu_ctl.scala 2309:34] + wire _T_1702 = mhpme5 == 10'h26; // @[dec_tlu_ctl.scala 2310:34] + wire _T_1706 = mhpme5 == 10'h27; // @[dec_tlu_ctl.scala 2311:34] + wire _T_1708 = mhpme5 == 10'h28; // @[dec_tlu_ctl.scala 2312:34] + wire _T_1710 = mhpme5 == 10'h29; // @[dec_tlu_ctl.scala 2313:34] + wire _T_1714 = mhpme5 == 10'h2a; // @[dec_tlu_ctl.scala 2314:34] + wire _T_1716 = mhpme5 == 10'h2b; // @[dec_tlu_ctl.scala 2315:34] + wire _T_1718 = mhpme5 == 10'h2c; // @[dec_tlu_ctl.scala 2316:34] + wire _T_1720 = mhpme5 == 10'h2d; // @[dec_tlu_ctl.scala 2317:34] + wire _T_1722 = mhpme5 == 10'h2e; // @[dec_tlu_ctl.scala 2318:34] + wire _T_1724 = mhpme5 == 10'h2f; // @[dec_tlu_ctl.scala 2319:34] + wire _T_1726 = mhpme5 == 10'h30; // @[dec_tlu_ctl.scala 2320:34] + wire _T_1728 = mhpme5 == 10'h31; // @[dec_tlu_ctl.scala 2321:34] + wire _T_1733 = mhpme5 == 10'h32; // @[dec_tlu_ctl.scala 2322:34] + wire _T_1743 = mhpme5 == 10'h36; // @[dec_tlu_ctl.scala 2323:34] + wire _T_1746 = mhpme5 == 10'h37; // @[dec_tlu_ctl.scala 2324:34] + wire _T_1749 = mhpme5 == 10'h38; // @[dec_tlu_ctl.scala 2325:34] + wire _T_1752 = mhpme5 == 10'h200; // @[dec_tlu_ctl.scala 2327:34] + wire _T_1754 = mhpme5 == 10'h201; // @[dec_tlu_ctl.scala 2328:34] + wire _T_1756 = mhpme5 == 10'h202; // @[dec_tlu_ctl.scala 2329:34] + wire _T_1758 = mhpme5 == 10'h203; // @[dec_tlu_ctl.scala 2330:34] + wire _T_1760 = mhpme5 == 10'h204; // @[dec_tlu_ctl.scala 2331:34] + wire _T_1763 = _T_1597 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] + wire _T_1764 = _T_1599 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] + wire _T_1765 = _T_1601 & _T_1036; // @[Mux.scala 27:72] + wire _T_1766 = _T_1605 & _T_1042; // @[Mux.scala 27:72] + wire _T_1767 = _T_1611 & _T_1047; // @[Mux.scala 27:72] + wire _T_1768 = _T_1616 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] + wire _T_1769 = _T_1618 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] + wire _T_1770 = _T_1620 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] + wire _T_1771 = _T_1622 & _T_1056; // @[Mux.scala 27:72] + wire _T_1772 = _T_1625 & _T_1059; // @[Mux.scala 27:72] + wire _T_1773 = _T_1628 & _T_1062; // @[Mux.scala 27:72] + wire _T_1774 = _T_1631 & _T_1065; // @[Mux.scala 27:72] + wire _T_1775 = _T_1634 & _T_1069; // @[Mux.scala 27:72] + wire _T_1776 = _T_1638 & _T_1074; // @[Mux.scala 27:72] + wire _T_1777 = _T_1643 & _T_1077; // @[Mux.scala 27:72] + wire _T_1778 = _T_1646 & _T_1080; // @[Mux.scala 27:72] + wire _T_1779 = _T_1649 & _T_1083; // @[Mux.scala 27:72] + wire _T_1780 = _T_1652 & _T_1086; // @[Mux.scala 27:72] + wire _T_1781 = _T_1655 & _T_1089; // @[Mux.scala 27:72] + wire _T_1782 = _T_1658 & _T_1092; // @[Mux.scala 27:72] + wire _T_1783 = _T_1661 & _T_1095; // @[Mux.scala 27:72] + wire _T_1784 = _T_1664 & _T_1098; // @[Mux.scala 27:72] + wire _T_1785 = _T_1667 & _T_1101; // @[Mux.scala 27:72] + wire _T_1786 = _T_1670 & _T_1106; // @[Mux.scala 27:72] + wire _T_1787 = _T_1675 & _T_1109; // @[Mux.scala 27:72] + wire _T_1788 = _T_1678 & _T_1112; // @[Mux.scala 27:72] + wire _T_1789 = _T_1681 & _T_1115; // @[Mux.scala 27:72] + wire _T_1790 = _T_1684 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] + wire _T_1792 = _T_1688 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] + wire _T_1793 = _T_1690 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] + wire _T_1794 = _T_1692 & io_lsu_store_stall_any; // @[Mux.scala 27:72] + wire _T_1795 = _T_1694 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] + wire _T_1796 = _T_1696 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] + wire _T_1797 = _T_1698 & _T_1133; // @[Mux.scala 27:72] + wire _T_1798 = _T_1702 & _T_1137; // @[Mux.scala 27:72] + wire _T_1799 = _T_1706 & io_take_ext_int; // @[Mux.scala 27:72] + wire _T_1800 = _T_1708 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] + wire _T_1801 = _T_1710 & _T_1145; // @[Mux.scala 27:72] + wire _T_1802 = _T_1714 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1803 = _T_1716 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_1804 = _T_1718 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] + wire _T_1805 = _T_1720 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1806 = _T_1722 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_1807 = _T_1724 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1808 = _T_1726 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_1809 = _T_1728 & _T_1164; // @[Mux.scala 27:72] + wire _T_1810 = _T_1733 & _T_1174; // @[Mux.scala 27:72] + wire _T_1811 = _T_1743 & _T_1177; // @[Mux.scala 27:72] + wire _T_1812 = _T_1746 & _T_1180; // @[Mux.scala 27:72] + wire _T_1813 = _T_1749 & _T_1183; // @[Mux.scala 27:72] + wire _T_1814 = _T_1752 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] + wire _T_1815 = _T_1754 & io_dma_pmu_any_read; // @[Mux.scala 27:72] + wire _T_1816 = _T_1756 & io_dma_pmu_any_write; // @[Mux.scala 27:72] + wire _T_1817 = _T_1758 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] + wire _T_1818 = _T_1760 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] + wire _T_1819 = _T_1595 | _T_1763; // @[Mux.scala 27:72] wire _T_1820 = _T_1819 | _T_1764; // @[Mux.scala 27:72] wire _T_1821 = _T_1820 | _T_1765; // @[Mux.scala 27:72] wire _T_1822 = _T_1821 | _T_1766; // @[Mux.scala 27:72] @@ -51925,8 +51964,8 @@ module csr_tlu( wire _T_1843 = _T_1842 | _T_1787; // @[Mux.scala 27:72] wire _T_1844 = _T_1843 | _T_1788; // @[Mux.scala 27:72] wire _T_1845 = _T_1844 | _T_1789; // @[Mux.scala 27:72] - wire _T_1846 = _T_1845 | _T_1769; // @[Mux.scala 27:72] - wire _T_1847 = _T_1846 | _T_1791; // @[Mux.scala 27:72] + wire _T_1846 = _T_1845 | _T_1790; // @[Mux.scala 27:72] + wire _T_1847 = _T_1846 | _T_1770; // @[Mux.scala 27:72] wire _T_1848 = _T_1847 | _T_1792; // @[Mux.scala 27:72] wire _T_1849 = _T_1848 | _T_1793; // @[Mux.scala 27:72] wire _T_1850 = _T_1849 | _T_1794; // @[Mux.scala 27:72] @@ -51953,122 +51992,122 @@ module csr_tlu( wire _T_1871 = _T_1870 | _T_1815; // @[Mux.scala 27:72] wire _T_1872 = _T_1871 | _T_1816; // @[Mux.scala 27:72] wire _T_1873 = _T_1872 | _T_1817; // @[Mux.scala 27:72] - wire mhpmc_inc_r_2 = _T_1593 & _T_1873; // @[dec_tlu_ctl.scala 2273:44] - wire _T_1877 = ~mcountinhibit[6]; // @[dec_tlu_ctl.scala 2273:24] + wire _T_1874 = _T_1873 | _T_1818; // @[Mux.scala 27:72] + wire mhpmc_inc_r_2 = _T_1594 & _T_1874; // @[dec_tlu_ctl.scala 2273:44] + wire _T_1878 = ~mcountinhibit[6]; // @[dec_tlu_ctl.scala 2273:24] reg [9:0] mhpme6; // @[Reg.scala 27:20] - wire _T_1878 = mhpme6 == 10'h1; // @[dec_tlu_ctl.scala 2274:34] - wire _T_1880 = mhpme6 == 10'h2; // @[dec_tlu_ctl.scala 2275:34] - wire _T_1882 = mhpme6 == 10'h3; // @[dec_tlu_ctl.scala 2276:34] - wire _T_1884 = mhpme6 == 10'h4; // @[dec_tlu_ctl.scala 2277:34] - wire _T_1888 = mhpme6 == 10'h5; // @[dec_tlu_ctl.scala 2278:34] - wire _T_1894 = mhpme6 == 10'h6; // @[dec_tlu_ctl.scala 2279:34] - wire _T_1899 = mhpme6 == 10'h7; // @[dec_tlu_ctl.scala 2280:34] - wire _T_1901 = mhpme6 == 10'h8; // @[dec_tlu_ctl.scala 2281:34] - wire _T_1903 = mhpme6 == 10'h1e; // @[dec_tlu_ctl.scala 2282:34] - wire _T_1905 = mhpme6 == 10'h9; // @[dec_tlu_ctl.scala 2283:34] - wire _T_1908 = mhpme6 == 10'ha; // @[dec_tlu_ctl.scala 2284:34] - wire _T_1911 = mhpme6 == 10'hb; // @[dec_tlu_ctl.scala 2285:34] - wire _T_1914 = mhpme6 == 10'hc; // @[dec_tlu_ctl.scala 2286:34] - wire _T_1917 = mhpme6 == 10'hd; // @[dec_tlu_ctl.scala 2287:34] - wire _T_1921 = mhpme6 == 10'he; // @[dec_tlu_ctl.scala 2288:34] - wire _T_1926 = mhpme6 == 10'hf; // @[dec_tlu_ctl.scala 2289:34] - wire _T_1929 = mhpme6 == 10'h10; // @[dec_tlu_ctl.scala 2290:34] - wire _T_1932 = mhpme6 == 10'h12; // @[dec_tlu_ctl.scala 2291:34] - wire _T_1935 = mhpme6 == 10'h11; // @[dec_tlu_ctl.scala 2292:34] - wire _T_1938 = mhpme6 == 10'h13; // @[dec_tlu_ctl.scala 2293:34] - wire _T_1941 = mhpme6 == 10'h14; // @[dec_tlu_ctl.scala 2294:34] - wire _T_1944 = mhpme6 == 10'h15; // @[dec_tlu_ctl.scala 2295:34] - wire _T_1947 = mhpme6 == 10'h16; // @[dec_tlu_ctl.scala 2296:34] - wire _T_1950 = mhpme6 == 10'h17; // @[dec_tlu_ctl.scala 2297:34] - wire _T_1953 = mhpme6 == 10'h18; // @[dec_tlu_ctl.scala 2298:34] - wire _T_1958 = mhpme6 == 10'h19; // @[dec_tlu_ctl.scala 2299:34] - wire _T_1961 = mhpme6 == 10'h1a; // @[dec_tlu_ctl.scala 2300:34] - wire _T_1964 = mhpme6 == 10'h1b; // @[dec_tlu_ctl.scala 2301:34] - wire _T_1967 = mhpme6 == 10'h1c; // @[dec_tlu_ctl.scala 2302:34] - wire _T_1971 = mhpme6 == 10'h1f; // @[dec_tlu_ctl.scala 2304:34] - wire _T_1973 = mhpme6 == 10'h20; // @[dec_tlu_ctl.scala 2305:34] - wire _T_1975 = mhpme6 == 10'h22; // @[dec_tlu_ctl.scala 2306:34] - wire _T_1977 = mhpme6 == 10'h23; // @[dec_tlu_ctl.scala 2307:34] - wire _T_1979 = mhpme6 == 10'h24; // @[dec_tlu_ctl.scala 2308:34] - wire _T_1981 = mhpme6 == 10'h25; // @[dec_tlu_ctl.scala 2309:34] - wire _T_1985 = mhpme6 == 10'h26; // @[dec_tlu_ctl.scala 2310:34] - wire _T_1989 = mhpme6 == 10'h27; // @[dec_tlu_ctl.scala 2311:34] - wire _T_1991 = mhpme6 == 10'h28; // @[dec_tlu_ctl.scala 2312:34] - wire _T_1993 = mhpme6 == 10'h29; // @[dec_tlu_ctl.scala 2313:34] - wire _T_1997 = mhpme6 == 10'h2a; // @[dec_tlu_ctl.scala 2314:34] - wire _T_1999 = mhpme6 == 10'h2b; // @[dec_tlu_ctl.scala 2315:34] - wire _T_2001 = mhpme6 == 10'h2c; // @[dec_tlu_ctl.scala 2316:34] - wire _T_2003 = mhpme6 == 10'h2d; // @[dec_tlu_ctl.scala 2317:34] - wire _T_2005 = mhpme6 == 10'h2e; // @[dec_tlu_ctl.scala 2318:34] - wire _T_2007 = mhpme6 == 10'h2f; // @[dec_tlu_ctl.scala 2319:34] - wire _T_2009 = mhpme6 == 10'h30; // @[dec_tlu_ctl.scala 2320:34] - wire _T_2011 = mhpme6 == 10'h31; // @[dec_tlu_ctl.scala 2321:34] - wire _T_2016 = mhpme6 == 10'h32; // @[dec_tlu_ctl.scala 2322:34] - wire _T_2026 = mhpme6 == 10'h36; // @[dec_tlu_ctl.scala 2323:34] - wire _T_2029 = mhpme6 == 10'h37; // @[dec_tlu_ctl.scala 2324:34] - wire _T_2032 = mhpme6 == 10'h38; // @[dec_tlu_ctl.scala 2325:34] - wire _T_2035 = mhpme6 == 10'h200; // @[dec_tlu_ctl.scala 2327:34] - wire _T_2037 = mhpme6 == 10'h201; // @[dec_tlu_ctl.scala 2328:34] - wire _T_2039 = mhpme6 == 10'h202; // @[dec_tlu_ctl.scala 2329:34] - wire _T_2041 = mhpme6 == 10'h203; // @[dec_tlu_ctl.scala 2330:34] - wire _T_2043 = mhpme6 == 10'h204; // @[dec_tlu_ctl.scala 2331:34] - wire _T_2046 = _T_1880 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] - wire _T_2047 = _T_1882 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] - wire _T_2048 = _T_1884 & _T_1035; // @[Mux.scala 27:72] - wire _T_2049 = _T_1888 & _T_1041; // @[Mux.scala 27:72] - wire _T_2050 = _T_1894 & _T_1046; // @[Mux.scala 27:72] - wire _T_2051 = _T_1899 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] - wire _T_2052 = _T_1901 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] - wire _T_2053 = _T_1903 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] - wire _T_2054 = _T_1905 & _T_1055; // @[Mux.scala 27:72] - wire _T_2055 = _T_1908 & _T_1058; // @[Mux.scala 27:72] - wire _T_2056 = _T_1911 & _T_1061; // @[Mux.scala 27:72] - wire _T_2057 = _T_1914 & _T_1064; // @[Mux.scala 27:72] - wire _T_2058 = _T_1917 & _T_1068; // @[Mux.scala 27:72] - wire _T_2059 = _T_1921 & _T_1073; // @[Mux.scala 27:72] - wire _T_2060 = _T_1926 & _T_1076; // @[Mux.scala 27:72] - wire _T_2061 = _T_1929 & _T_1079; // @[Mux.scala 27:72] - wire _T_2062 = _T_1932 & _T_1082; // @[Mux.scala 27:72] - wire _T_2063 = _T_1935 & _T_1085; // @[Mux.scala 27:72] - wire _T_2064 = _T_1938 & _T_1088; // @[Mux.scala 27:72] - wire _T_2065 = _T_1941 & _T_1091; // @[Mux.scala 27:72] - wire _T_2066 = _T_1944 & _T_1094; // @[Mux.scala 27:72] - wire _T_2067 = _T_1947 & _T_1097; // @[Mux.scala 27:72] - wire _T_2068 = _T_1950 & _T_1100; // @[Mux.scala 27:72] - wire _T_2069 = _T_1953 & _T_1105; // @[Mux.scala 27:72] - wire _T_2070 = _T_1958 & _T_1108; // @[Mux.scala 27:72] - wire _T_2071 = _T_1961 & _T_1111; // @[Mux.scala 27:72] - wire _T_2072 = _T_1964 & _T_1114; // @[Mux.scala 27:72] - wire _T_2073 = _T_1967 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] - wire _T_2075 = _T_1971 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] - wire _T_2076 = _T_1973 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] - wire _T_2077 = _T_1975 & io_lsu_store_stall_any; // @[Mux.scala 27:72] - wire _T_2078 = _T_1977 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] - wire _T_2079 = _T_1979 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] - wire _T_2080 = _T_1981 & _T_1132; // @[Mux.scala 27:72] - wire _T_2081 = _T_1985 & _T_1136; // @[Mux.scala 27:72] - wire _T_2082 = _T_1989 & io_take_ext_int; // @[Mux.scala 27:72] - wire _T_2083 = _T_1991 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] - wire _T_2084 = _T_1993 & _T_1144; // @[Mux.scala 27:72] - wire _T_2085 = _T_1997 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_2086 = _T_1999 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] - wire _T_2087 = _T_2001 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] - wire _T_2088 = _T_2003 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_2089 = _T_2005 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] - wire _T_2090 = _T_2007 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_2091 = _T_2009 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] - wire _T_2092 = _T_2011 & _T_1163; // @[Mux.scala 27:72] - wire _T_2093 = _T_2016 & _T_1173; // @[Mux.scala 27:72] - wire _T_2094 = _T_2026 & _T_1176; // @[Mux.scala 27:72] - wire _T_2095 = _T_2029 & _T_1179; // @[Mux.scala 27:72] - wire _T_2096 = _T_2032 & _T_1182; // @[Mux.scala 27:72] - wire _T_2097 = _T_2035 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] - wire _T_2098 = _T_2037 & io_dma_pmu_any_read; // @[Mux.scala 27:72] - wire _T_2099 = _T_2039 & io_dma_pmu_any_write; // @[Mux.scala 27:72] - wire _T_2100 = _T_2041 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] - wire _T_2101 = _T_2043 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] - wire _T_2102 = _T_1878 | _T_2046; // @[Mux.scala 27:72] - wire _T_2103 = _T_2102 | _T_2047; // @[Mux.scala 27:72] + wire _T_1879 = mhpme6 == 10'h1; // @[dec_tlu_ctl.scala 2274:34] + wire _T_1881 = mhpme6 == 10'h2; // @[dec_tlu_ctl.scala 2275:34] + wire _T_1883 = mhpme6 == 10'h3; // @[dec_tlu_ctl.scala 2276:34] + wire _T_1885 = mhpme6 == 10'h4; // @[dec_tlu_ctl.scala 2277:34] + wire _T_1889 = mhpme6 == 10'h5; // @[dec_tlu_ctl.scala 2278:34] + wire _T_1895 = mhpme6 == 10'h6; // @[dec_tlu_ctl.scala 2279:34] + wire _T_1900 = mhpme6 == 10'h7; // @[dec_tlu_ctl.scala 2280:34] + wire _T_1902 = mhpme6 == 10'h8; // @[dec_tlu_ctl.scala 2281:34] + wire _T_1904 = mhpme6 == 10'h1e; // @[dec_tlu_ctl.scala 2282:34] + wire _T_1906 = mhpme6 == 10'h9; // @[dec_tlu_ctl.scala 2283:34] + wire _T_1909 = mhpme6 == 10'ha; // @[dec_tlu_ctl.scala 2284:34] + wire _T_1912 = mhpme6 == 10'hb; // @[dec_tlu_ctl.scala 2285:34] + wire _T_1915 = mhpme6 == 10'hc; // @[dec_tlu_ctl.scala 2286:34] + wire _T_1918 = mhpme6 == 10'hd; // @[dec_tlu_ctl.scala 2287:34] + wire _T_1922 = mhpme6 == 10'he; // @[dec_tlu_ctl.scala 2288:34] + wire _T_1927 = mhpme6 == 10'hf; // @[dec_tlu_ctl.scala 2289:34] + wire _T_1930 = mhpme6 == 10'h10; // @[dec_tlu_ctl.scala 2290:34] + wire _T_1933 = mhpme6 == 10'h12; // @[dec_tlu_ctl.scala 2291:34] + wire _T_1936 = mhpme6 == 10'h11; // @[dec_tlu_ctl.scala 2292:34] + wire _T_1939 = mhpme6 == 10'h13; // @[dec_tlu_ctl.scala 2293:34] + wire _T_1942 = mhpme6 == 10'h14; // @[dec_tlu_ctl.scala 2294:34] + wire _T_1945 = mhpme6 == 10'h15; // @[dec_tlu_ctl.scala 2295:34] + wire _T_1948 = mhpme6 == 10'h16; // @[dec_tlu_ctl.scala 2296:34] + wire _T_1951 = mhpme6 == 10'h17; // @[dec_tlu_ctl.scala 2297:34] + wire _T_1954 = mhpme6 == 10'h18; // @[dec_tlu_ctl.scala 2298:34] + wire _T_1959 = mhpme6 == 10'h19; // @[dec_tlu_ctl.scala 2299:34] + wire _T_1962 = mhpme6 == 10'h1a; // @[dec_tlu_ctl.scala 2300:34] + wire _T_1965 = mhpme6 == 10'h1b; // @[dec_tlu_ctl.scala 2301:34] + wire _T_1968 = mhpme6 == 10'h1c; // @[dec_tlu_ctl.scala 2302:34] + wire _T_1972 = mhpme6 == 10'h1f; // @[dec_tlu_ctl.scala 2304:34] + wire _T_1974 = mhpme6 == 10'h20; // @[dec_tlu_ctl.scala 2305:34] + wire _T_1976 = mhpme6 == 10'h22; // @[dec_tlu_ctl.scala 2306:34] + wire _T_1978 = mhpme6 == 10'h23; // @[dec_tlu_ctl.scala 2307:34] + wire _T_1980 = mhpme6 == 10'h24; // @[dec_tlu_ctl.scala 2308:34] + wire _T_1982 = mhpme6 == 10'h25; // @[dec_tlu_ctl.scala 2309:34] + wire _T_1986 = mhpme6 == 10'h26; // @[dec_tlu_ctl.scala 2310:34] + wire _T_1990 = mhpme6 == 10'h27; // @[dec_tlu_ctl.scala 2311:34] + wire _T_1992 = mhpme6 == 10'h28; // @[dec_tlu_ctl.scala 2312:34] + wire _T_1994 = mhpme6 == 10'h29; // @[dec_tlu_ctl.scala 2313:34] + wire _T_1998 = mhpme6 == 10'h2a; // @[dec_tlu_ctl.scala 2314:34] + wire _T_2000 = mhpme6 == 10'h2b; // @[dec_tlu_ctl.scala 2315:34] + wire _T_2002 = mhpme6 == 10'h2c; // @[dec_tlu_ctl.scala 2316:34] + wire _T_2004 = mhpme6 == 10'h2d; // @[dec_tlu_ctl.scala 2317:34] + wire _T_2006 = mhpme6 == 10'h2e; // @[dec_tlu_ctl.scala 2318:34] + wire _T_2008 = mhpme6 == 10'h2f; // @[dec_tlu_ctl.scala 2319:34] + wire _T_2010 = mhpme6 == 10'h30; // @[dec_tlu_ctl.scala 2320:34] + wire _T_2012 = mhpme6 == 10'h31; // @[dec_tlu_ctl.scala 2321:34] + wire _T_2017 = mhpme6 == 10'h32; // @[dec_tlu_ctl.scala 2322:34] + wire _T_2027 = mhpme6 == 10'h36; // @[dec_tlu_ctl.scala 2323:34] + wire _T_2030 = mhpme6 == 10'h37; // @[dec_tlu_ctl.scala 2324:34] + wire _T_2033 = mhpme6 == 10'h38; // @[dec_tlu_ctl.scala 2325:34] + wire _T_2036 = mhpme6 == 10'h200; // @[dec_tlu_ctl.scala 2327:34] + wire _T_2038 = mhpme6 == 10'h201; // @[dec_tlu_ctl.scala 2328:34] + wire _T_2040 = mhpme6 == 10'h202; // @[dec_tlu_ctl.scala 2329:34] + wire _T_2042 = mhpme6 == 10'h203; // @[dec_tlu_ctl.scala 2330:34] + wire _T_2044 = mhpme6 == 10'h204; // @[dec_tlu_ctl.scala 2331:34] + wire _T_2047 = _T_1881 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] + wire _T_2048 = _T_1883 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] + wire _T_2049 = _T_1885 & _T_1036; // @[Mux.scala 27:72] + wire _T_2050 = _T_1889 & _T_1042; // @[Mux.scala 27:72] + wire _T_2051 = _T_1895 & _T_1047; // @[Mux.scala 27:72] + wire _T_2052 = _T_1900 & io_ifu_pmu_instr_aligned; // @[Mux.scala 27:72] + wire _T_2053 = _T_1902 & io_dec_pmu_instr_decoded; // @[Mux.scala 27:72] + wire _T_2054 = _T_1904 & io_dec_pmu_decode_stall; // @[Mux.scala 27:72] + wire _T_2055 = _T_1906 & _T_1056; // @[Mux.scala 27:72] + wire _T_2056 = _T_1909 & _T_1059; // @[Mux.scala 27:72] + wire _T_2057 = _T_1912 & _T_1062; // @[Mux.scala 27:72] + wire _T_2058 = _T_1915 & _T_1065; // @[Mux.scala 27:72] + wire _T_2059 = _T_1918 & _T_1069; // @[Mux.scala 27:72] + wire _T_2060 = _T_1922 & _T_1074; // @[Mux.scala 27:72] + wire _T_2061 = _T_1927 & _T_1077; // @[Mux.scala 27:72] + wire _T_2062 = _T_1930 & _T_1080; // @[Mux.scala 27:72] + wire _T_2063 = _T_1933 & _T_1083; // @[Mux.scala 27:72] + wire _T_2064 = _T_1936 & _T_1086; // @[Mux.scala 27:72] + wire _T_2065 = _T_1939 & _T_1089; // @[Mux.scala 27:72] + wire _T_2066 = _T_1942 & _T_1092; // @[Mux.scala 27:72] + wire _T_2067 = _T_1945 & _T_1095; // @[Mux.scala 27:72] + wire _T_2068 = _T_1948 & _T_1098; // @[Mux.scala 27:72] + wire _T_2069 = _T_1951 & _T_1101; // @[Mux.scala 27:72] + wire _T_2070 = _T_1954 & _T_1106; // @[Mux.scala 27:72] + wire _T_2071 = _T_1959 & _T_1109; // @[Mux.scala 27:72] + wire _T_2072 = _T_1962 & _T_1112; // @[Mux.scala 27:72] + wire _T_2073 = _T_1965 & _T_1115; // @[Mux.scala 27:72] + wire _T_2074 = _T_1968 & io_ifu_pmu_fetch_stall; // @[Mux.scala 27:72] + wire _T_2076 = _T_1972 & io_dec_pmu_postsync_stall; // @[Mux.scala 27:72] + wire _T_2077 = _T_1974 & io_dec_pmu_presync_stall; // @[Mux.scala 27:72] + wire _T_2078 = _T_1976 & io_lsu_store_stall_any; // @[Mux.scala 27:72] + wire _T_2079 = _T_1978 & io_dma_dccm_stall_any; // @[Mux.scala 27:72] + wire _T_2080 = _T_1980 & io_dma_iccm_stall_any; // @[Mux.scala 27:72] + wire _T_2081 = _T_1982 & _T_1133; // @[Mux.scala 27:72] + wire _T_2082 = _T_1986 & _T_1137; // @[Mux.scala 27:72] + wire _T_2083 = _T_1990 & io_take_ext_int; // @[Mux.scala 27:72] + wire _T_2084 = _T_1992 & io_tlu_flush_lower_r; // @[Mux.scala 27:72] + wire _T_2085 = _T_1994 & _T_1145; // @[Mux.scala 27:72] + wire _T_2086 = _T_1998 & io_ifu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_2087 = _T_2000 & io_lsu_pmu_bus_trxn; // @[Mux.scala 27:72] + wire _T_2088 = _T_2002 & io_lsu_pmu_bus_misaligned; // @[Mux.scala 27:72] + wire _T_2089 = _T_2004 & io_ifu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_2090 = _T_2006 & io_lsu_pmu_bus_error; // @[Mux.scala 27:72] + wire _T_2091 = _T_2008 & io_ifu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_2092 = _T_2010 & io_lsu_pmu_bus_busy; // @[Mux.scala 27:72] + wire _T_2093 = _T_2012 & _T_1164; // @[Mux.scala 27:72] + wire _T_2094 = _T_2017 & _T_1174; // @[Mux.scala 27:72] + wire _T_2095 = _T_2027 & _T_1177; // @[Mux.scala 27:72] + wire _T_2096 = _T_2030 & _T_1180; // @[Mux.scala 27:72] + wire _T_2097 = _T_2033 & _T_1183; // @[Mux.scala 27:72] + wire _T_2098 = _T_2036 & io_dec_tlu_pmu_fw_halted; // @[Mux.scala 27:72] + wire _T_2099 = _T_2038 & io_dma_pmu_any_read; // @[Mux.scala 27:72] + wire _T_2100 = _T_2040 & io_dma_pmu_any_write; // @[Mux.scala 27:72] + wire _T_2101 = _T_2042 & io_dma_pmu_dccm_read; // @[Mux.scala 27:72] + wire _T_2102 = _T_2044 & io_dma_pmu_dccm_write; // @[Mux.scala 27:72] + wire _T_2103 = _T_1879 | _T_2047; // @[Mux.scala 27:72] wire _T_2104 = _T_2103 | _T_2048; // @[Mux.scala 27:72] wire _T_2105 = _T_2104 | _T_2049; // @[Mux.scala 27:72] wire _T_2106 = _T_2105 | _T_2050; // @[Mux.scala 27:72] @@ -52095,8 +52134,8 @@ module csr_tlu( wire _T_2127 = _T_2126 | _T_2071; // @[Mux.scala 27:72] wire _T_2128 = _T_2127 | _T_2072; // @[Mux.scala 27:72] wire _T_2129 = _T_2128 | _T_2073; // @[Mux.scala 27:72] - wire _T_2130 = _T_2129 | _T_2053; // @[Mux.scala 27:72] - wire _T_2131 = _T_2130 | _T_2075; // @[Mux.scala 27:72] + wire _T_2130 = _T_2129 | _T_2074; // @[Mux.scala 27:72] + wire _T_2131 = _T_2130 | _T_2054; // @[Mux.scala 27:72] wire _T_2132 = _T_2131 | _T_2076; // @[Mux.scala 27:72] wire _T_2133 = _T_2132 | _T_2077; // @[Mux.scala 27:72] wire _T_2134 = _T_2133 | _T_2078; // @[Mux.scala 27:72] @@ -52123,187 +52162,187 @@ module csr_tlu( wire _T_2155 = _T_2154 | _T_2099; // @[Mux.scala 27:72] wire _T_2156 = _T_2155 | _T_2100; // @[Mux.scala 27:72] wire _T_2157 = _T_2156 | _T_2101; // @[Mux.scala 27:72] - wire mhpmc_inc_r_3 = _T_1877 & _T_2157; // @[dec_tlu_ctl.scala 2273:44] + wire _T_2158 = _T_2157 | _T_2102; // @[Mux.scala 27:72] + wire mhpmc_inc_r_3 = _T_1878 & _T_2158; // @[dec_tlu_ctl.scala 2273:44] reg mhpmc_inc_r_d1_0; // @[dec_tlu_ctl.scala 2334:53] reg mhpmc_inc_r_d1_1; // @[dec_tlu_ctl.scala 2335:53] reg mhpmc_inc_r_d1_2; // @[dec_tlu_ctl.scala 2336:53] reg mhpmc_inc_r_d1_3; // @[dec_tlu_ctl.scala 2337:53] reg perfcnt_halted_d1; // @[dec_tlu_ctl.scala 2338:56] wire perfcnt_halted = _T_85 | io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 2341:67] - wire _T_2169 = ~_T_85; // @[dec_tlu_ctl.scala 2342:37] - wire [3:0] _T_2171 = _T_2169 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] _T_2178 = {mhpme6[9],mhpme5[9],mhpme4[9],mhpme3[9]}; // @[Cat.scala 29:58] - wire [3:0] perfcnt_during_sleep = _T_2171 & _T_2178; // @[dec_tlu_ctl.scala 2342:86] - wire _T_2180 = ~perfcnt_during_sleep[0]; // @[dec_tlu_ctl.scala 2344:67] - wire _T_2181 = perfcnt_halted_d1 & _T_2180; // @[dec_tlu_ctl.scala 2344:65] - wire _T_2182 = ~_T_2181; // @[dec_tlu_ctl.scala 2344:45] - wire _T_2185 = ~perfcnt_during_sleep[1]; // @[dec_tlu_ctl.scala 2345:67] - wire _T_2186 = perfcnt_halted_d1 & _T_2185; // @[dec_tlu_ctl.scala 2345:65] - wire _T_2187 = ~_T_2186; // @[dec_tlu_ctl.scala 2345:45] - wire _T_2190 = ~perfcnt_during_sleep[2]; // @[dec_tlu_ctl.scala 2346:67] - wire _T_2191 = perfcnt_halted_d1 & _T_2190; // @[dec_tlu_ctl.scala 2346:65] - wire _T_2192 = ~_T_2191; // @[dec_tlu_ctl.scala 2346:45] - wire _T_2195 = ~perfcnt_during_sleep[3]; // @[dec_tlu_ctl.scala 2347:67] - wire _T_2196 = perfcnt_halted_d1 & _T_2195; // @[dec_tlu_ctl.scala 2347:65] - wire _T_2197 = ~_T_2196; // @[dec_tlu_ctl.scala 2347:45] - wire _T_2200 = io_dec_csr_wraddr_r == 12'hb03; // @[dec_tlu_ctl.scala 2353:72] - wire mhpmc3_wr_en0 = io_dec_csr_wen_r_mod & _T_2200; // @[dec_tlu_ctl.scala 2353:43] - wire _T_2201 = ~perfcnt_halted; // @[dec_tlu_ctl.scala 2354:23] - wire _T_2203 = _T_2201 | perfcnt_during_sleep[0]; // @[dec_tlu_ctl.scala 2354:39] - wire _T_2204 = |mhpmc_inc_r_0; // @[dec_tlu_ctl.scala 2354:86] - wire mhpmc3_wr_en1 = _T_2203 & _T_2204; // @[dec_tlu_ctl.scala 2354:66] + wire _T_2170 = ~_T_85; // @[dec_tlu_ctl.scala 2342:37] + wire [3:0] _T_2172 = _T_2170 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_2179 = {mhpme6[9],mhpme5[9],mhpme4[9],mhpme3[9]}; // @[Cat.scala 29:58] + wire [3:0] perfcnt_during_sleep = _T_2172 & _T_2179; // @[dec_tlu_ctl.scala 2342:86] + wire _T_2181 = ~perfcnt_during_sleep[0]; // @[dec_tlu_ctl.scala 2344:67] + wire _T_2182 = perfcnt_halted_d1 & _T_2181; // @[dec_tlu_ctl.scala 2344:65] + wire _T_2183 = ~_T_2182; // @[dec_tlu_ctl.scala 2344:45] + wire _T_2186 = ~perfcnt_during_sleep[1]; // @[dec_tlu_ctl.scala 2345:67] + wire _T_2187 = perfcnt_halted_d1 & _T_2186; // @[dec_tlu_ctl.scala 2345:65] + wire _T_2188 = ~_T_2187; // @[dec_tlu_ctl.scala 2345:45] + wire _T_2191 = ~perfcnt_during_sleep[2]; // @[dec_tlu_ctl.scala 2346:67] + wire _T_2192 = perfcnt_halted_d1 & _T_2191; // @[dec_tlu_ctl.scala 2346:65] + wire _T_2193 = ~_T_2192; // @[dec_tlu_ctl.scala 2346:45] + wire _T_2196 = ~perfcnt_during_sleep[3]; // @[dec_tlu_ctl.scala 2347:67] + wire _T_2197 = perfcnt_halted_d1 & _T_2196; // @[dec_tlu_ctl.scala 2347:65] + wire _T_2198 = ~_T_2197; // @[dec_tlu_ctl.scala 2347:45] + wire _T_2201 = io_dec_csr_wraddr_r == 12'hb03; // @[dec_tlu_ctl.scala 2353:72] + wire mhpmc3_wr_en0 = io_dec_csr_wen_r_mod & _T_2201; // @[dec_tlu_ctl.scala 2353:43] + wire _T_2202 = ~perfcnt_halted; // @[dec_tlu_ctl.scala 2354:23] + wire _T_2204 = _T_2202 | perfcnt_during_sleep[0]; // @[dec_tlu_ctl.scala 2354:39] + wire _T_2205 = |mhpmc_inc_r_0; // @[dec_tlu_ctl.scala 2354:86] + wire mhpmc3_wr_en1 = _T_2204 & _T_2205; // @[dec_tlu_ctl.scala 2354:66] reg [31:0] mhpmc3h; // @[lib.scala 374:16] reg [31:0] mhpmc3; // @[lib.scala 374:16] - wire [63:0] _T_2207 = {mhpmc3h,mhpmc3}; // @[Cat.scala 29:58] - wire [63:0] _T_2208 = {63'h0,mhpmc_inc_r_0}; // @[Cat.scala 29:58] - wire [63:0] mhpmc3_incr = _T_2207 + _T_2208; // @[dec_tlu_ctl.scala 2358:49] - wire _T_2216 = io_dec_csr_wraddr_r == 12'hb83; // @[dec_tlu_ctl.scala 2363:73] - wire mhpmc3h_wr_en0 = io_dec_csr_wen_r_mod & _T_2216; // @[dec_tlu_ctl.scala 2363:44] - wire _T_2222 = io_dec_csr_wraddr_r == 12'hb04; // @[dec_tlu_ctl.scala 2372:72] - wire mhpmc4_wr_en0 = io_dec_csr_wen_r_mod & _T_2222; // @[dec_tlu_ctl.scala 2372:43] - wire _T_2225 = _T_2201 | perfcnt_during_sleep[1]; // @[dec_tlu_ctl.scala 2373:39] - wire _T_2226 = |mhpmc_inc_r_1; // @[dec_tlu_ctl.scala 2373:86] - wire mhpmc4_wr_en1 = _T_2225 & _T_2226; // @[dec_tlu_ctl.scala 2373:66] + wire [63:0] _T_2208 = {mhpmc3h,mhpmc3}; // @[Cat.scala 29:58] + wire [63:0] _T_2209 = {63'h0,mhpmc_inc_r_0}; // @[Cat.scala 29:58] + wire [63:0] mhpmc3_incr = _T_2208 + _T_2209; // @[dec_tlu_ctl.scala 2358:49] + wire _T_2217 = io_dec_csr_wraddr_r == 12'hb83; // @[dec_tlu_ctl.scala 2363:73] + wire mhpmc3h_wr_en0 = io_dec_csr_wen_r_mod & _T_2217; // @[dec_tlu_ctl.scala 2363:44] + wire _T_2223 = io_dec_csr_wraddr_r == 12'hb04; // @[dec_tlu_ctl.scala 2372:72] + wire mhpmc4_wr_en0 = io_dec_csr_wen_r_mod & _T_2223; // @[dec_tlu_ctl.scala 2372:43] + wire _T_2226 = _T_2202 | perfcnt_during_sleep[1]; // @[dec_tlu_ctl.scala 2373:39] + wire _T_2227 = |mhpmc_inc_r_1; // @[dec_tlu_ctl.scala 2373:86] + wire mhpmc4_wr_en1 = _T_2226 & _T_2227; // @[dec_tlu_ctl.scala 2373:66] reg [31:0] mhpmc4h; // @[lib.scala 374:16] reg [31:0] mhpmc4; // @[lib.scala 374:16] - wire [63:0] _T_2229 = {mhpmc4h,mhpmc4}; // @[Cat.scala 29:58] - wire [63:0] _T_2230 = {63'h0,mhpmc_inc_r_1}; // @[Cat.scala 29:58] - wire [63:0] mhpmc4_incr = _T_2229 + _T_2230; // @[dec_tlu_ctl.scala 2378:49] - wire _T_2239 = io_dec_csr_wraddr_r == 12'hb84; // @[dec_tlu_ctl.scala 2382:73] - wire mhpmc4h_wr_en0 = io_dec_csr_wen_r_mod & _T_2239; // @[dec_tlu_ctl.scala 2382:44] - wire _T_2245 = io_dec_csr_wraddr_r == 12'hb05; // @[dec_tlu_ctl.scala 2391:72] - wire mhpmc5_wr_en0 = io_dec_csr_wen_r_mod & _T_2245; // @[dec_tlu_ctl.scala 2391:43] - wire _T_2248 = _T_2201 | perfcnt_during_sleep[2]; // @[dec_tlu_ctl.scala 2392:39] - wire _T_2249 = |mhpmc_inc_r_2; // @[dec_tlu_ctl.scala 2392:86] - wire mhpmc5_wr_en1 = _T_2248 & _T_2249; // @[dec_tlu_ctl.scala 2392:66] + wire [63:0] _T_2230 = {mhpmc4h,mhpmc4}; // @[Cat.scala 29:58] + wire [63:0] _T_2231 = {63'h0,mhpmc_inc_r_1}; // @[Cat.scala 29:58] + wire [63:0] mhpmc4_incr = _T_2230 + _T_2231; // @[dec_tlu_ctl.scala 2378:49] + wire _T_2240 = io_dec_csr_wraddr_r == 12'hb84; // @[dec_tlu_ctl.scala 2382:73] + wire mhpmc4h_wr_en0 = io_dec_csr_wen_r_mod & _T_2240; // @[dec_tlu_ctl.scala 2382:44] + wire _T_2246 = io_dec_csr_wraddr_r == 12'hb05; // @[dec_tlu_ctl.scala 2391:72] + wire mhpmc5_wr_en0 = io_dec_csr_wen_r_mod & _T_2246; // @[dec_tlu_ctl.scala 2391:43] + wire _T_2249 = _T_2202 | perfcnt_during_sleep[2]; // @[dec_tlu_ctl.scala 2392:39] + wire _T_2250 = |mhpmc_inc_r_2; // @[dec_tlu_ctl.scala 2392:86] + wire mhpmc5_wr_en1 = _T_2249 & _T_2250; // @[dec_tlu_ctl.scala 2392:66] reg [31:0] mhpmc5h; // @[lib.scala 374:16] reg [31:0] mhpmc5; // @[lib.scala 374:16] - wire [63:0] _T_2252 = {mhpmc5h,mhpmc5}; // @[Cat.scala 29:58] - wire [63:0] _T_2253 = {63'h0,mhpmc_inc_r_2}; // @[Cat.scala 29:58] - wire [63:0] mhpmc5_incr = _T_2252 + _T_2253; // @[dec_tlu_ctl.scala 2395:49] - wire _T_2261 = io_dec_csr_wraddr_r == 12'hb85; // @[dec_tlu_ctl.scala 2400:73] - wire mhpmc5h_wr_en0 = io_dec_csr_wen_r_mod & _T_2261; // @[dec_tlu_ctl.scala 2400:44] - wire _T_2267 = io_dec_csr_wraddr_r == 12'hb06; // @[dec_tlu_ctl.scala 2409:72] - wire mhpmc6_wr_en0 = io_dec_csr_wen_r_mod & _T_2267; // @[dec_tlu_ctl.scala 2409:43] - wire _T_2270 = _T_2201 | perfcnt_during_sleep[3]; // @[dec_tlu_ctl.scala 2410:39] - wire _T_2271 = |mhpmc_inc_r_3; // @[dec_tlu_ctl.scala 2410:86] - wire mhpmc6_wr_en1 = _T_2270 & _T_2271; // @[dec_tlu_ctl.scala 2410:66] + wire [63:0] _T_2253 = {mhpmc5h,mhpmc5}; // @[Cat.scala 29:58] + wire [63:0] _T_2254 = {63'h0,mhpmc_inc_r_2}; // @[Cat.scala 29:58] + wire [63:0] mhpmc5_incr = _T_2253 + _T_2254; // @[dec_tlu_ctl.scala 2395:49] + wire _T_2262 = io_dec_csr_wraddr_r == 12'hb85; // @[dec_tlu_ctl.scala 2400:73] + wire mhpmc5h_wr_en0 = io_dec_csr_wen_r_mod & _T_2262; // @[dec_tlu_ctl.scala 2400:44] + wire _T_2268 = io_dec_csr_wraddr_r == 12'hb06; // @[dec_tlu_ctl.scala 2409:72] + wire mhpmc6_wr_en0 = io_dec_csr_wen_r_mod & _T_2268; // @[dec_tlu_ctl.scala 2409:43] + wire _T_2271 = _T_2202 | perfcnt_during_sleep[3]; // @[dec_tlu_ctl.scala 2410:39] + wire _T_2272 = |mhpmc_inc_r_3; // @[dec_tlu_ctl.scala 2410:86] + wire mhpmc6_wr_en1 = _T_2271 & _T_2272; // @[dec_tlu_ctl.scala 2410:66] reg [31:0] mhpmc6h; // @[lib.scala 374:16] reg [31:0] mhpmc6; // @[lib.scala 374:16] - wire [63:0] _T_2274 = {mhpmc6h,mhpmc6}; // @[Cat.scala 29:58] - wire [63:0] _T_2275 = {63'h0,mhpmc_inc_r_3}; // @[Cat.scala 29:58] - wire [63:0] mhpmc6_incr = _T_2274 + _T_2275; // @[dec_tlu_ctl.scala 2413:49] - wire _T_2283 = io_dec_csr_wraddr_r == 12'hb86; // @[dec_tlu_ctl.scala 2418:73] - wire mhpmc6h_wr_en0 = io_dec_csr_wen_r_mod & _T_2283; // @[dec_tlu_ctl.scala 2418:44] - wire _T_2289 = io_dec_csr_wrdata_r[9:0] > 10'h204; // @[dec_tlu_ctl.scala 2429:56] - wire _T_2291 = |io_dec_csr_wrdata_r[31:10]; // @[dec_tlu_ctl.scala 2429:102] - wire _T_2292 = _T_2289 | _T_2291; // @[dec_tlu_ctl.scala 2429:71] - wire _T_2295 = io_dec_csr_wraddr_r == 12'h323; // @[dec_tlu_ctl.scala 2431:70] - wire wr_mhpme3_r = io_dec_csr_wen_r_mod & _T_2295; // @[dec_tlu_ctl.scala 2431:41] - wire _T_2299 = io_dec_csr_wraddr_r == 12'h324; // @[dec_tlu_ctl.scala 2438:70] - wire wr_mhpme4_r = io_dec_csr_wen_r_mod & _T_2299; // @[dec_tlu_ctl.scala 2438:41] - wire _T_2303 = io_dec_csr_wraddr_r == 12'h325; // @[dec_tlu_ctl.scala 2445:70] - wire wr_mhpme5_r = io_dec_csr_wen_r_mod & _T_2303; // @[dec_tlu_ctl.scala 2445:41] - wire _T_2307 = io_dec_csr_wraddr_r == 12'h326; // @[dec_tlu_ctl.scala 2452:70] - wire wr_mhpme6_r = io_dec_csr_wen_r_mod & _T_2307; // @[dec_tlu_ctl.scala 2452:41] - wire _T_2311 = io_dec_csr_wraddr_r == 12'h320; // @[dec_tlu_ctl.scala 2469:77] - wire wr_mcountinhibit_r = io_dec_csr_wen_r_mod & _T_2311; // @[dec_tlu_ctl.scala 2469:48] - wire _T_2323 = io_i0_valid_wb | io_exc_or_int_valid_r_d1; // @[dec_tlu_ctl.scala 2484:51] - wire _T_2324 = _T_2323 | io_interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 2484:78] - wire _T_2325 = _T_2324 | io_dec_tlu_i0_valid_wb1; // @[dec_tlu_ctl.scala 2484:104] - wire _T_2326 = _T_2325 | io_dec_tlu_i0_exc_valid_wb1; // @[dec_tlu_ctl.scala 2484:130] - wire _T_2327 = _T_2326 | io_dec_tlu_int_valid_wb1; // @[dec_tlu_ctl.scala 2485:32] - reg _T_2330; // @[dec_tlu_ctl.scala 2487:62] - wire _T_2331 = io_i0_exception_valid_r_d1 | io_lsu_i0_exc_r_d1; // @[dec_tlu_ctl.scala 2488:91] - wire _T_2332 = ~io_trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 2488:137] - wire _T_2333 = io_trigger_hit_r_d1 & _T_2332; // @[dec_tlu_ctl.scala 2488:135] - reg _T_2335; // @[dec_tlu_ctl.scala 2488:62] - reg [4:0] _T_2336; // @[dec_tlu_ctl.scala 2489:62] - reg _T_2337; // @[dec_tlu_ctl.scala 2490:62] - wire [31:0] _T_2343 = {io_core_id,4'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2352 = {21'h3,3'h0,io_mstatus[1],3'h0,io_mstatus[0],3'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2357 = {io_mtvec[30:1],1'h0,io_mtvec[0]}; // @[Cat.scala 29:58] - wire [31:0] _T_2370 = {1'h0,io_mip[5:3],16'h0,io_mip[2],3'h0,io_mip[1],3'h0,io_mip[0],3'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2383 = {1'h0,mie[5:3],16'h0,mie[2],3'h0,mie[1],3'h0,mie[0],3'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2395 = {io_mepc,1'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2400 = {28'h0,mscause}; // @[Cat.scala 29:58] - wire [31:0] _T_2408 = {meivt,10'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2411 = {meivt,meihap,2'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2414 = {28'h0,meicurpl}; // @[Cat.scala 29:58] - wire [31:0] _T_2417 = {28'h0,meicidpl}; // @[Cat.scala 29:58] - wire [31:0] _T_2420 = {28'h0,meipt}; // @[Cat.scala 29:58] - wire [31:0] _T_2423 = {23'h0,mcgc}; // @[Cat.scala 29:58] - wire [31:0] _T_2426 = {13'h0,_T_350,4'h0,mfdc_int[11:7],_T_353,mfdc_int[5:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_2430 = {16'h4000,io_dcsr[15:2],2'h3}; // @[Cat.scala 29:58] - wire [31:0] _T_2432 = {io_dpc,1'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2448 = {7'h0,dicawics[16],2'h0,dicawics[15:14],3'h0,dicawics[13:0],3'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2451 = {30'h0,mtsel}; // @[Cat.scala 29:58] - wire [31:0] _T_2480 = {26'h0,mfdht}; // @[Cat.scala 29:58] - wire [31:0] _T_2483 = {30'h0,mfdhs}; // @[Cat.scala 29:58] - wire [31:0] _T_2486 = {22'h0,mhpme3}; // @[Cat.scala 29:58] - wire [31:0] _T_2489 = {22'h0,mhpme4}; // @[Cat.scala 29:58] - wire [31:0] _T_2492 = {22'h0,mhpme5}; // @[Cat.scala 29:58] - wire [31:0] _T_2495 = {22'h0,mhpme6}; // @[Cat.scala 29:58] - wire [31:0] _T_2498 = {25'h0,temp_ncount6_2,1'h0,temp_ncount0}; // @[Cat.scala 29:58] - wire [31:0] _T_2501 = {30'h0,mpmc,1'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_2504 = io_csr_pkt_csr_misa ? 32'h40001104 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2505 = io_csr_pkt_csr_mvendorid ? 32'h45 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2506 = io_csr_pkt_csr_marchid ? 32'h10 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2507 = io_csr_pkt_csr_mimpid ? 32'h2 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2508 = io_csr_pkt_csr_mhartid ? _T_2343 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2509 = io_csr_pkt_csr_mstatus ? _T_2352 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2510 = io_csr_pkt_csr_mtvec ? _T_2357 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2511 = io_csr_pkt_csr_mip ? _T_2370 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2512 = io_csr_pkt_csr_mie ? _T_2383 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2513 = io_csr_pkt_csr_mcyclel ? mcyclel : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2514 = io_csr_pkt_csr_mcycleh ? mcycleh_inc : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2515 = io_csr_pkt_csr_minstretl ? minstretl : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2516 = io_csr_pkt_csr_minstreth ? minstreth_inc : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2517 = io_csr_pkt_csr_mscratch ? mscratch : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2518 = io_csr_pkt_csr_mepc ? _T_2395 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2519 = io_csr_pkt_csr_mcause ? mcause : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2520 = io_csr_pkt_csr_mscause ? _T_2400 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2521 = io_csr_pkt_csr_mtval ? mtval : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2522 = io_csr_pkt_csr_mrac ? mrac : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2523 = io_csr_pkt_csr_mdseac ? mdseac : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2524 = io_csr_pkt_csr_meivt ? _T_2408 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2525 = io_csr_pkt_csr_meihap ? _T_2411 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2526 = io_csr_pkt_csr_meicurpl ? _T_2414 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2527 = io_csr_pkt_csr_meicidpl ? _T_2417 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2528 = io_csr_pkt_csr_meipt ? _T_2420 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2529 = io_csr_pkt_csr_mcgc ? _T_2423 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2530 = io_csr_pkt_csr_mfdc ? _T_2426 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2531 = io_csr_pkt_csr_dcsr ? _T_2430 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2532 = io_csr_pkt_csr_dpc ? _T_2432 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2533 = io_csr_pkt_csr_dicad0 ? dicad0[31:0] : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2534 = io_csr_pkt_csr_dicad0h ? dicad0h : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2535 = io_csr_pkt_csr_dicad1 ? dicad1 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2536 = io_csr_pkt_csr_dicawics ? _T_2448 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2537 = io_csr_pkt_csr_mtsel ? _T_2451 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2538 = io_csr_pkt_csr_mtdata1 ? mtdata1_tsel_out : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2539 = io_csr_pkt_csr_mtdata2 ? mtdata2_tsel_out : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2540 = io_csr_pkt_csr_micect ? micect : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2541 = io_csr_pkt_csr_miccmect ? miccmect : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2542 = io_csr_pkt_csr_mdccmect ? mdccmect : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2543 = io_csr_pkt_csr_mhpmc3 ? mhpmc3 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2544 = io_csr_pkt_csr_mhpmc4 ? mhpmc4 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2545 = io_csr_pkt_csr_mhpmc5 ? mhpmc5 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2546 = io_csr_pkt_csr_mhpmc6 ? mhpmc6 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2547 = io_csr_pkt_csr_mhpmc3h ? mhpmc3h : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2548 = io_csr_pkt_csr_mhpmc4h ? mhpmc4h : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2549 = io_csr_pkt_csr_mhpmc5h ? mhpmc5h : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2550 = io_csr_pkt_csr_mhpmc6h ? mhpmc6h : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2551 = io_csr_pkt_csr_mfdht ? _T_2480 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2552 = io_csr_pkt_csr_mfdhs ? _T_2483 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2553 = io_csr_pkt_csr_mhpme3 ? _T_2486 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2554 = io_csr_pkt_csr_mhpme4 ? _T_2489 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2555 = io_csr_pkt_csr_mhpme5 ? _T_2492 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2556 = io_csr_pkt_csr_mhpme6 ? _T_2495 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2557 = io_csr_pkt_csr_mcountinhibit ? _T_2498 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2558 = io_csr_pkt_csr_mpmc ? _T_2501 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2559 = io_dec_timer_read_d ? io_dec_timer_rddata_d : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2560 = _T_2504 | _T_2505; // @[Mux.scala 27:72] - wire [31:0] _T_2561 = _T_2560 | _T_2506; // @[Mux.scala 27:72] + wire [63:0] _T_2275 = {mhpmc6h,mhpmc6}; // @[Cat.scala 29:58] + wire [63:0] _T_2276 = {63'h0,mhpmc_inc_r_3}; // @[Cat.scala 29:58] + wire [63:0] mhpmc6_incr = _T_2275 + _T_2276; // @[dec_tlu_ctl.scala 2413:49] + wire _T_2284 = io_dec_csr_wraddr_r == 12'hb86; // @[dec_tlu_ctl.scala 2418:73] + wire mhpmc6h_wr_en0 = io_dec_csr_wen_r_mod & _T_2284; // @[dec_tlu_ctl.scala 2418:44] + wire _T_2290 = io_dec_csr_wrdata_r[9:0] > 10'h204; // @[dec_tlu_ctl.scala 2429:56] + wire _T_2292 = |io_dec_csr_wrdata_r[31:10]; // @[dec_tlu_ctl.scala 2429:102] + wire _T_2293 = _T_2290 | _T_2292; // @[dec_tlu_ctl.scala 2429:71] + wire _T_2296 = io_dec_csr_wraddr_r == 12'h323; // @[dec_tlu_ctl.scala 2431:70] + wire wr_mhpme3_r = io_dec_csr_wen_r_mod & _T_2296; // @[dec_tlu_ctl.scala 2431:41] + wire _T_2300 = io_dec_csr_wraddr_r == 12'h324; // @[dec_tlu_ctl.scala 2438:70] + wire wr_mhpme4_r = io_dec_csr_wen_r_mod & _T_2300; // @[dec_tlu_ctl.scala 2438:41] + wire _T_2304 = io_dec_csr_wraddr_r == 12'h325; // @[dec_tlu_ctl.scala 2445:70] + wire wr_mhpme5_r = io_dec_csr_wen_r_mod & _T_2304; // @[dec_tlu_ctl.scala 2445:41] + wire _T_2308 = io_dec_csr_wraddr_r == 12'h326; // @[dec_tlu_ctl.scala 2452:70] + wire wr_mhpme6_r = io_dec_csr_wen_r_mod & _T_2308; // @[dec_tlu_ctl.scala 2452:41] + wire _T_2312 = io_dec_csr_wraddr_r == 12'h320; // @[dec_tlu_ctl.scala 2469:77] + wire wr_mcountinhibit_r = io_dec_csr_wen_r_mod & _T_2312; // @[dec_tlu_ctl.scala 2469:48] + wire _T_2324 = io_i0_valid_wb | io_exc_or_int_valid_r_d1; // @[dec_tlu_ctl.scala 2484:51] + wire _T_2325 = _T_2324 | io_interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 2484:78] + wire _T_2326 = _T_2325 | io_dec_tlu_i0_valid_wb1; // @[dec_tlu_ctl.scala 2484:104] + wire _T_2327 = _T_2326 | io_dec_tlu_i0_exc_valid_wb1; // @[dec_tlu_ctl.scala 2484:130] + wire _T_2328 = _T_2327 | io_dec_tlu_int_valid_wb1; // @[dec_tlu_ctl.scala 2485:32] + reg _T_2331; // @[dec_tlu_ctl.scala 2487:62] + wire _T_2332 = io_i0_exception_valid_r_d1 | io_lsu_i0_exc_r_d1; // @[dec_tlu_ctl.scala 2488:91] + wire _T_2333 = ~io_trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 2488:137] + wire _T_2334 = io_trigger_hit_r_d1 & _T_2333; // @[dec_tlu_ctl.scala 2488:135] + reg _T_2336; // @[dec_tlu_ctl.scala 2488:62] + reg [4:0] _T_2337; // @[dec_tlu_ctl.scala 2489:62] + reg _T_2338; // @[dec_tlu_ctl.scala 2490:62] + wire [31:0] _T_2344 = {io_core_id,4'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2353 = {21'h3,3'h0,io_mstatus[1],3'h0,io_mstatus[0],3'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2358 = {io_mtvec[30:1],1'h0,io_mtvec[0]}; // @[Cat.scala 29:58] + wire [31:0] _T_2371 = {1'h0,io_mip[5:3],16'h0,io_mip[2],3'h0,io_mip[1],3'h0,io_mip[0],3'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2384 = {1'h0,mie[5:3],16'h0,mie[2],3'h0,mie[1],3'h0,mie[0],3'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2396 = {io_mepc,1'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2401 = {28'h0,mscause}; // @[Cat.scala 29:58] + wire [31:0] _T_2409 = {meivt,10'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2412 = {meivt,meihap,2'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2415 = {28'h0,meicurpl}; // @[Cat.scala 29:58] + wire [31:0] _T_2418 = {28'h0,meicidpl}; // @[Cat.scala 29:58] + wire [31:0] _T_2421 = {28'h0,meipt}; // @[Cat.scala 29:58] + wire [31:0] _T_2424 = {23'h0,mcgc}; // @[Cat.scala 29:58] + wire [31:0] _T_2427 = {13'h0,_T_350,4'h0,mfdc_int[11:7],_T_353,mfdc_int[5:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_2431 = {16'h4000,io_dcsr[15:2],2'h3}; // @[Cat.scala 29:58] + wire [31:0] _T_2433 = {io_dpc,1'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2449 = {7'h0,dicawics[16],2'h0,dicawics[15:14],3'h0,dicawics[13:0],3'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2452 = {30'h0,mtsel}; // @[Cat.scala 29:58] + wire [31:0] _T_2481 = {26'h0,mfdht}; // @[Cat.scala 29:58] + wire [31:0] _T_2484 = {30'h0,mfdhs}; // @[Cat.scala 29:58] + wire [31:0] _T_2487 = {22'h0,mhpme3}; // @[Cat.scala 29:58] + wire [31:0] _T_2490 = {22'h0,mhpme4}; // @[Cat.scala 29:58] + wire [31:0] _T_2493 = {22'h0,mhpme5}; // @[Cat.scala 29:58] + wire [31:0] _T_2496 = {22'h0,mhpme6}; // @[Cat.scala 29:58] + wire [31:0] _T_2499 = {25'h0,temp_ncount6_2,1'h0,temp_ncount0}; // @[Cat.scala 29:58] + wire [31:0] _T_2502 = {30'h0,mpmc,1'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_2505 = io_csr_pkt_csr_misa ? 32'h40001104 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2506 = io_csr_pkt_csr_mvendorid ? 32'h45 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2507 = io_csr_pkt_csr_marchid ? 32'h10 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2508 = io_csr_pkt_csr_mimpid ? 32'h1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2509 = io_csr_pkt_csr_mhartid ? _T_2344 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2510 = io_csr_pkt_csr_mstatus ? _T_2353 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2511 = io_csr_pkt_csr_mtvec ? _T_2358 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2512 = io_csr_pkt_csr_mip ? _T_2371 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2513 = io_csr_pkt_csr_mie ? _T_2384 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2514 = io_csr_pkt_csr_mcyclel ? mcyclel : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2515 = io_csr_pkt_csr_mcycleh ? mcycleh_inc : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2516 = io_csr_pkt_csr_minstretl ? minstretl : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2517 = io_csr_pkt_csr_minstreth ? minstreth_inc : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2518 = io_csr_pkt_csr_mscratch ? mscratch : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2519 = io_csr_pkt_csr_mepc ? _T_2396 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2520 = io_csr_pkt_csr_mcause ? mcause : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2521 = io_csr_pkt_csr_mscause ? _T_2401 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2522 = io_csr_pkt_csr_mtval ? mtval : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2523 = io_csr_pkt_csr_mrac ? mrac : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2524 = io_csr_pkt_csr_mdseac ? mdseac : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2525 = io_csr_pkt_csr_meivt ? _T_2409 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2526 = io_csr_pkt_csr_meihap ? _T_2412 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2527 = io_csr_pkt_csr_meicurpl ? _T_2415 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2528 = io_csr_pkt_csr_meicidpl ? _T_2418 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2529 = io_csr_pkt_csr_meipt ? _T_2421 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2530 = io_csr_pkt_csr_mcgc ? _T_2424 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2531 = io_csr_pkt_csr_mfdc ? _T_2427 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2532 = io_csr_pkt_csr_dcsr ? _T_2431 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2533 = io_csr_pkt_csr_dpc ? _T_2433 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2534 = io_csr_pkt_csr_dicad0 ? dicad0[31:0] : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2535 = io_csr_pkt_csr_dicad0h ? dicad0h : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2536 = io_csr_pkt_csr_dicad1 ? dicad1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2537 = io_csr_pkt_csr_dicawics ? _T_2449 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2538 = io_csr_pkt_csr_mtsel ? _T_2452 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2539 = io_csr_pkt_csr_mtdata1 ? mtdata1_tsel_out : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2540 = io_csr_pkt_csr_mtdata2 ? mtdata2_tsel_out : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2541 = io_csr_pkt_csr_micect ? micect : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2542 = io_csr_pkt_csr_miccmect ? miccmect : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2543 = io_csr_pkt_csr_mdccmect ? mdccmect : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2544 = io_csr_pkt_csr_mhpmc3 ? mhpmc3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2545 = io_csr_pkt_csr_mhpmc4 ? mhpmc4 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2546 = io_csr_pkt_csr_mhpmc5 ? mhpmc5 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2547 = io_csr_pkt_csr_mhpmc6 ? mhpmc6 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2548 = io_csr_pkt_csr_mhpmc3h ? mhpmc3h : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2549 = io_csr_pkt_csr_mhpmc4h ? mhpmc4h : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2550 = io_csr_pkt_csr_mhpmc5h ? mhpmc5h : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2551 = io_csr_pkt_csr_mhpmc6h ? mhpmc6h : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2552 = io_csr_pkt_csr_mfdht ? _T_2481 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2553 = io_csr_pkt_csr_mfdhs ? _T_2484 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2554 = io_csr_pkt_csr_mhpme3 ? _T_2487 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2555 = io_csr_pkt_csr_mhpme4 ? _T_2490 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2556 = io_csr_pkt_csr_mhpme5 ? _T_2493 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2557 = io_csr_pkt_csr_mhpme6 ? _T_2496 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2558 = io_csr_pkt_csr_mcountinhibit ? _T_2499 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2559 = io_csr_pkt_csr_mpmc ? _T_2502 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2560 = io_dec_timer_read_d ? io_dec_timer_rddata_d : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2561 = _T_2505 | _T_2506; // @[Mux.scala 27:72] wire [31:0] _T_2562 = _T_2561 | _T_2507; // @[Mux.scala 27:72] wire [31:0] _T_2563 = _T_2562 | _T_2508; // @[Mux.scala 27:72] wire [31:0] _T_2564 = _T_2563 | _T_2509; // @[Mux.scala 27:72] @@ -52356,6 +52395,7 @@ module csr_tlu( wire [31:0] _T_2611 = _T_2610 | _T_2556; // @[Mux.scala 27:72] wire [31:0] _T_2612 = _T_2611 | _T_2557; // @[Mux.scala 27:72] wire [31:0] _T_2613 = _T_2612 | _T_2558; // @[Mux.scala 27:72] + wire [31:0] _T_2614 = _T_2613 | _T_2559; // @[Mux.scala 27:72] rvclkhdr rvclkhdr ( // @[lib.scala 368:23] .io_l1clk(rvclkhdr_io_l1clk), .io_clk(rvclkhdr_io_clk), @@ -52566,7 +52606,7 @@ module csr_tlu( .io_en(rvclkhdr_34_io_en), .io_scan_mode(rvclkhdr_34_io_scan_mode) ); - assign io_dec_tlu_ic_diag_pkt_icache_wrdata = {_T_763,dicad0[31:0]}; // @[dec_tlu_ctl.scala 2154:61] + assign io_dec_tlu_ic_diag_pkt_icache_wrdata = {_T_764,dicad0[31:0]}; // @[dec_tlu_ctl.scala 2154:56] assign io_dec_tlu_ic_diag_pkt_icache_dicawics = dicawics; // @[dec_tlu_ctl.scala 2157:41] assign io_dec_tlu_ic_diag_pkt_icache_rd_valid = icache_rd_valid_f; // @[dec_tlu_ctl.scala 2165:41] assign io_dec_tlu_ic_diag_pkt_icache_wr_valid = icache_wr_valid_f; // @[dec_tlu_ctl.scala 2166:41] @@ -52598,22 +52638,22 @@ module csr_tlu( assign io_trigger_pkt_any_3_execute = io_mtdata1_t_3[2]; // @[dec_tlu_ctl.scala 2234:40] assign io_trigger_pkt_any_3_m = io_mtdata1_t_3[3]; // @[dec_tlu_ctl.scala 2235:40] assign io_trigger_pkt_any_3_tdata2 = mtdata2_t_3; // @[dec_tlu_ctl.scala 2248:51] - assign io_dec_tlu_int_valid_wb1 = _T_2337; // @[dec_tlu_ctl.scala 2490:30] - assign io_dec_tlu_i0_exc_valid_wb1 = _T_2335; // @[dec_tlu_ctl.scala 2488:30] - assign io_dec_tlu_i0_valid_wb1 = _T_2330; // @[dec_tlu_ctl.scala 2487:30] + assign io_dec_tlu_int_valid_wb1 = _T_2338; // @[dec_tlu_ctl.scala 2490:30] + assign io_dec_tlu_i0_exc_valid_wb1 = _T_2336; // @[dec_tlu_ctl.scala 2488:30] + assign io_dec_tlu_i0_valid_wb1 = _T_2331; // @[dec_tlu_ctl.scala 2487:30] assign io_dec_tlu_mtval_wb1 = mtval; // @[dec_tlu_ctl.scala 2492:24] - assign io_dec_tlu_exc_cause_wb1 = _T_2336; // @[dec_tlu_ctl.scala 2489:30] - assign io_dec_tlu_perfcnt0 = mhpmc_inc_r_d1_0 & _T_2182; // @[dec_tlu_ctl.scala 2344:22] - assign io_dec_tlu_perfcnt1 = mhpmc_inc_r_d1_1 & _T_2187; // @[dec_tlu_ctl.scala 2345:22] - assign io_dec_tlu_perfcnt2 = mhpmc_inc_r_d1_2 & _T_2192; // @[dec_tlu_ctl.scala 2346:22] - assign io_dec_tlu_perfcnt3 = mhpmc_inc_r_d1_3 & _T_2197; // @[dec_tlu_ctl.scala 2347:22] + assign io_dec_tlu_exc_cause_wb1 = _T_2337; // @[dec_tlu_ctl.scala 2489:30] + assign io_dec_tlu_perfcnt0 = mhpmc_inc_r_d1_0 & _T_2183; // @[dec_tlu_ctl.scala 2344:22] + assign io_dec_tlu_perfcnt1 = mhpmc_inc_r_d1_1 & _T_2188; // @[dec_tlu_ctl.scala 2345:22] + assign io_dec_tlu_perfcnt2 = mhpmc_inc_r_d1_2 & _T_2193; // @[dec_tlu_ctl.scala 2346:22] + assign io_dec_tlu_perfcnt3 = mhpmc_inc_r_d1_3 & _T_2198; // @[dec_tlu_ctl.scala 2347:22] assign io_dec_tlu_misc_clk_override = mcgc[8]; // @[dec_tlu_ctl.scala 1717:31] assign io_dec_tlu_dec_clk_override = mcgc[7]; // @[dec_tlu_ctl.scala 1718:31] assign io_dec_tlu_lsu_clk_override = mcgc[4]; // @[dec_tlu_ctl.scala 1720:31] assign io_dec_tlu_pic_clk_override = mcgc[2]; // @[dec_tlu_ctl.scala 1722:31] assign io_dec_tlu_dccm_clk_override = mcgc[1]; // @[dec_tlu_ctl.scala 1723:31] assign io_dec_tlu_icm_clk_override = mcgc[0]; // @[dec_tlu_ctl.scala 1724:31] - assign io_dec_csr_rddata_d = _T_2613 | _T_2559; // @[dec_tlu_ctl.scala 2497:21] + assign io_dec_csr_rddata_d = _T_2614 | _T_2560; // @[dec_tlu_ctl.scala 2497:21] assign io_dec_tlu_pipelining_disable = mfdc[0]; // @[dec_tlu_ctl.scala 1767:39] assign io_dec_tlu_wr_pause_r = _T_370 & _T_371; // @[dec_tlu_ctl.scala 1776:24] assign io_dec_tlu_meipt = meipt; // @[dec_tlu_ctl.scala 2005:19] @@ -52640,10 +52680,10 @@ module csr_tlu( assign io_mdseac_locked_ns = mdseac_en | _T_489; // @[dec_tlu_ctl.scala 1824:22] assign io_force_halt = mfdht[0] & _T_609; // @[dec_tlu_ctl.scala 1932:16] assign io_dpc = _T_726; // @[dec_tlu_ctl.scala 2069:9] - assign io_mtdata1_t_0 = _T_872; // @[dec_tlu_ctl.scala 2225:39] - assign io_mtdata1_t_1 = _T_873; // @[dec_tlu_ctl.scala 2225:39] - assign io_mtdata1_t_2 = _T_874; // @[dec_tlu_ctl.scala 2225:39] - assign io_mtdata1_t_3 = _T_875; // @[dec_tlu_ctl.scala 2225:39] + assign io_mtdata1_t_0 = _T_873; // @[dec_tlu_ctl.scala 2225:39] + assign io_mtdata1_t_1 = _T_874; // @[dec_tlu_ctl.scala 2225:39] + assign io_mtdata1_t_2 = _T_875; // @[dec_tlu_ctl.scala 2225:39] + assign io_mtdata1_t_3 = _T_876; // @[dec_tlu_ctl.scala 2225:39] assign rvclkhdr_io_clk = clock; // @[lib.scala 370:18] assign rvclkhdr_io_en = io_dec_csr_wen_r_mod & _T_58; // @[lib.scala 371:17] assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] @@ -52711,16 +52751,16 @@ module csr_tlu( assign rvclkhdr_21_io_en = wr_dicad0h_r | io_ifu_ic_debug_rd_data_valid; // @[lib.scala 371:17] assign rvclkhdr_21_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_22_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_22_io_en = _T_971 & _T_807; // @[lib.scala 371:17] + assign rvclkhdr_22_io_en = _T_972 & _T_808; // @[lib.scala 371:17] assign rvclkhdr_22_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_23_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_23_io_en = _T_980 & _T_816; // @[lib.scala 371:17] + assign rvclkhdr_23_io_en = _T_981 & _T_817; // @[lib.scala 371:17] assign rvclkhdr_23_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_24_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_24_io_en = _T_989 & _T_825; // @[lib.scala 371:17] + assign rvclkhdr_24_io_en = _T_990 & _T_826; // @[lib.scala 371:17] assign rvclkhdr_24_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_25_io_clk = clock; // @[lib.scala 370:18] - assign rvclkhdr_25_io_en = _T_998 & _T_834; // @[lib.scala 371:17] + assign rvclkhdr_25_io_en = _T_999 & _T_835; // @[lib.scala 371:17] assign rvclkhdr_25_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_26_io_clk = clock; // @[lib.scala 370:18] assign rvclkhdr_26_io_en = mhpmc3_wr_en0 | mhpmc3_wr_en1; // @[lib.scala 371:17] @@ -52747,7 +52787,7 @@ module csr_tlu( assign rvclkhdr_33_io_en = mhpmc6h_wr_en0 | mhpmc6_wr_en1; // @[lib.scala 371:17] assign rvclkhdr_33_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] assign rvclkhdr_34_io_clk = clock; // @[lib.scala 344:17] - assign rvclkhdr_34_io_en = _T_2327 | io_clk_override; // @[lib.scala 345:16] + assign rvclkhdr_34_io_en = _T_2328 | io_clk_override; // @[lib.scala 345:16] assign rvclkhdr_34_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE @@ -52867,7 +52907,7 @@ initial begin _RAND_40 = {1{`RANDOM}}; dicad0h = _RAND_40[31:0]; _RAND_41 = {1{`RANDOM}}; - _T_758 = _RAND_41[31:0]; + _T_759 = _RAND_41[6:0]; _RAND_42 = {1{`RANDOM}}; icache_rd_valid_f = _RAND_42[0:0]; _RAND_43 = {1{`RANDOM}}; @@ -52875,13 +52915,13 @@ initial begin _RAND_44 = {1{`RANDOM}}; mtsel = _RAND_44[1:0]; _RAND_45 = {1{`RANDOM}}; - _T_872 = _RAND_45[9:0]; + _T_873 = _RAND_45[9:0]; _RAND_46 = {1{`RANDOM}}; - _T_873 = _RAND_46[9:0]; + _T_874 = _RAND_46[9:0]; _RAND_47 = {1{`RANDOM}}; - _T_874 = _RAND_47[9:0]; + _T_875 = _RAND_47[9:0]; _RAND_48 = {1{`RANDOM}}; - _T_875 = _RAND_48[9:0]; + _T_876 = _RAND_48[9:0]; _RAND_49 = {1{`RANDOM}}; mtdata2_t_0 = _RAND_49[31:0]; _RAND_50 = {1{`RANDOM}}; @@ -52925,13 +52965,13 @@ initial begin _RAND_69 = {1{`RANDOM}}; mhpmc6 = _RAND_69[31:0]; _RAND_70 = {1{`RANDOM}}; - _T_2330 = _RAND_70[0:0]; + _T_2331 = _RAND_70[0:0]; _RAND_71 = {1{`RANDOM}}; - _T_2335 = _RAND_71[0:0]; + _T_2336 = _RAND_71[0:0]; _RAND_72 = {1{`RANDOM}}; - _T_2336 = _RAND_72[4:0]; + _T_2337 = _RAND_72[4:0]; _RAND_73 = {1{`RANDOM}}; - _T_2337 = _RAND_73[0:0]; + _T_2338 = _RAND_73[0:0]; `endif // RANDOMIZE_REG_INIT if (reset) begin mpmc_b = 1'h0; @@ -53057,7 +53097,7 @@ initial begin dicad0h = 32'h0; end if (reset) begin - _T_758 = 32'h0; + _T_759 = 7'h0; end if (reset) begin icache_rd_valid_f = 1'h0; @@ -53068,9 +53108,6 @@ initial begin if (reset) begin mtsel = 2'h0; end - if (reset) begin - _T_872 = 10'h0; - end if (reset) begin _T_873 = 10'h0; end @@ -53080,6 +53117,9 @@ initial begin if (reset) begin _T_875 = 10'h0; end + if (reset) begin + _T_876 = 10'h0; + end if (reset) begin mtdata2_t_0 = 32'h0; end @@ -53144,16 +53184,16 @@ initial begin mhpmc6 = 32'h0; end if (reset) begin - _T_2330 = 1'h0; + _T_2331 = 1'h0; end if (reset) begin - _T_2335 = 1'h0; + _T_2336 = 1'h0; end if (reset) begin - _T_2336 = 5'h0; + _T_2337 = 5'h0; end if (reset) begin - _T_2337 = 1'h0; + _T_2338 = 1'h0; end `endif // RANDOMIZE end // initial @@ -53484,12 +53524,12 @@ end // initial end always @(posedge io_active_clk or posedge reset) begin if (reset) begin - _T_758 <= 32'h0; - end else if (_T_756) begin + _T_759 <= 7'h0; + end else if (_T_757) begin if (_T_752) begin - _T_758 <= io_dec_csr_wrdata_r; + _T_759 <= io_dec_csr_wrdata_r[6:0]; end else begin - _T_758 <= {{25'd0}, io_ifu_ic_debug_rd_data[70:64]}; + _T_759 <= io_ifu_ic_debug_rd_data[70:64]; end end end @@ -53497,14 +53537,14 @@ end // initial if (reset) begin icache_rd_valid_f <= 1'h0; end else begin - icache_rd_valid_f <= _T_768 & _T_770; + icache_rd_valid_f <= _T_769 & _T_771; end end always @(posedge io_active_clk or posedge reset) begin if (reset) begin icache_wr_valid_f <= 1'h0; end else begin - icache_wr_valid_f <= _T_663 & _T_773; + icache_wr_valid_f <= _T_663 & _T_774; end end always @(posedge io_csr_wr_clk or posedge reset) begin @@ -53514,40 +53554,40 @@ end // initial mtsel <= io_dec_csr_wrdata_r[1:0]; end end - always @(posedge io_active_clk or posedge reset) begin - if (reset) begin - _T_872 <= 10'h0; - end else if (wr_mtdata1_t_r_0) begin - _T_872 <= tdata_wrdata_r; - end else begin - _T_872 <= _T_843; - end - end always @(posedge io_active_clk or posedge reset) begin if (reset) begin _T_873 <= 10'h0; - end else if (wr_mtdata1_t_r_1) begin + end else if (wr_mtdata1_t_r_0) begin _T_873 <= tdata_wrdata_r; end else begin - _T_873 <= _T_852; + _T_873 <= _T_844; end end always @(posedge io_active_clk or posedge reset) begin if (reset) begin _T_874 <= 10'h0; - end else if (wr_mtdata1_t_r_2) begin + end else if (wr_mtdata1_t_r_1) begin _T_874 <= tdata_wrdata_r; end else begin - _T_874 <= _T_861; + _T_874 <= _T_853; end end always @(posedge io_active_clk or posedge reset) begin if (reset) begin _T_875 <= 10'h0; - end else if (wr_mtdata1_t_r_3) begin + end else if (wr_mtdata1_t_r_2) begin _T_875 <= tdata_wrdata_r; end else begin - _T_875 <= _T_870; + _T_875 <= _T_862; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + _T_876 <= 10'h0; + end else if (wr_mtdata1_t_r_3) begin + _T_876 <= tdata_wrdata_r; + end else begin + _T_876 <= _T_871; end end always @(posedge rvclkhdr_22_io_l1clk or posedge reset) begin @@ -53582,7 +53622,7 @@ end // initial if (reset) begin mhpme3 <= 10'h0; end else if (wr_mhpme3_r) begin - if (_T_2292) begin + if (_T_2293) begin mhpme3 <= 10'h204; end else begin mhpme3 <= io_dec_csr_wrdata_r[9:0]; @@ -53593,7 +53633,7 @@ end // initial if (reset) begin mhpme4 <= 10'h0; end else if (wr_mhpme4_r) begin - if (_T_2292) begin + if (_T_2293) begin mhpme4 <= 10'h204; end else begin mhpme4 <= io_dec_csr_wrdata_r[9:0]; @@ -53604,7 +53644,7 @@ end // initial if (reset) begin mhpme5 <= 10'h0; end else if (wr_mhpme5_r) begin - if (_T_2292) begin + if (_T_2293) begin mhpme5 <= 10'h204; end else begin mhpme5 <= io_dec_csr_wrdata_r[9:0]; @@ -53615,7 +53655,7 @@ end // initial if (reset) begin mhpme6 <= 10'h0; end else if (wr_mhpme6_r) begin - if (_T_2292) begin + if (_T_2293) begin mhpme6 <= 10'h204; end else begin mhpme6 <= io_dec_csr_wrdata_r[9:0]; @@ -53626,28 +53666,28 @@ end // initial if (reset) begin mhpmc_inc_r_d1_0 <= 1'h0; end else begin - mhpmc_inc_r_d1_0 <= _T_1025 & _T_1305; + mhpmc_inc_r_d1_0 <= _T_1026 & _T_1306; end end always @(posedge io_free_clk or posedge reset) begin if (reset) begin mhpmc_inc_r_d1_1 <= 1'h0; end else begin - mhpmc_inc_r_d1_1 <= _T_1309 & _T_1589; + mhpmc_inc_r_d1_1 <= _T_1310 & _T_1590; end end always @(posedge io_free_clk or posedge reset) begin if (reset) begin mhpmc_inc_r_d1_2 <= 1'h0; end else begin - mhpmc_inc_r_d1_2 <= _T_1593 & _T_1873; + mhpmc_inc_r_d1_2 <= _T_1594 & _T_1874; end end always @(posedge io_free_clk or posedge reset) begin if (reset) begin mhpmc_inc_r_d1_3 <= 1'h0; end else begin - mhpmc_inc_r_d1_3 <= _T_1877 & _T_2157; + mhpmc_inc_r_d1_3 <= _T_1878 & _T_2158; end end always @(posedge io_free_clk or posedge reset) begin @@ -53731,30 +53771,30 @@ end // initial end always @(posedge rvclkhdr_34_io_l1clk or posedge reset) begin if (reset) begin - _T_2330 <= 1'h0; + _T_2331 <= 1'h0; end else begin - _T_2330 <= io_i0_valid_wb; + _T_2331 <= io_i0_valid_wb; end end always @(posedge rvclkhdr_34_io_l1clk or posedge reset) begin if (reset) begin - _T_2335 <= 1'h0; + _T_2336 <= 1'h0; end else begin - _T_2335 <= _T_2331 | _T_2333; + _T_2336 <= _T_2332 | _T_2334; end end always @(posedge rvclkhdr_34_io_l1clk or posedge reset) begin if (reset) begin - _T_2336 <= 5'h0; + _T_2337 <= 5'h0; end else begin - _T_2336 <= io_exc_cause_wb; + _T_2337 <= io_exc_cause_wb; end end always @(posedge rvclkhdr_34_io_l1clk or posedge reset) begin if (reset) begin - _T_2337 <= 1'h0; + _T_2338 <= 1'h0; end else begin - _T_2337 <= io_interrupt_valid_r_d1; + _T_2338 <= io_interrupt_valid_r_d1; end end endmodule @@ -54341,6 +54381,7 @@ module dec_tlu_ctl( output io_dec_tlu_pic_clk_override, output io_dec_tlu_dccm_clk_override, output io_dec_tlu_icm_clk_override, + output io_dec_tlu_flush_lower_wb, input io_ifu_pmu_instr_aligned, output io_tlu_bp_dec_tlu_br0_r_pkt_valid, output [1:0] io_tlu_bp_dec_tlu_br0_r_pkt_bits_hist, @@ -54348,7 +54389,6 @@ module dec_tlu_ctl( output io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_start_error, output io_tlu_bp_dec_tlu_br0_r_pkt_bits_way, output io_tlu_bp_dec_tlu_br0_r_pkt_bits_middle, - output io_tlu_bp_dec_tlu_flush_lower_wb, output io_tlu_bp_dec_tlu_flush_leak_one_wb, output io_tlu_bp_dec_tlu_bpred_disable, output io_tlu_ifc_dec_tlu_flush_noredir_wb, @@ -54469,26 +54509,26 @@ module dec_tlu_ctl( reg [31:0] _RAND_73; reg [31:0] _RAND_74; `endif // RANDOMIZE_REG_INIT - wire int_timers_clock; // @[dec_tlu_ctl.scala 274:30] - wire int_timers_reset; // @[dec_tlu_ctl.scala 274:30] - wire int_timers_io_free_clk; // @[dec_tlu_ctl.scala 274:30] - wire int_timers_io_scan_mode; // @[dec_tlu_ctl.scala 274:30] - wire int_timers_io_dec_csr_wen_r_mod; // @[dec_tlu_ctl.scala 274:30] - wire [11:0] int_timers_io_dec_csr_wraddr_r; // @[dec_tlu_ctl.scala 274:30] - wire [31:0] int_timers_io_dec_csr_wrdata_r; // @[dec_tlu_ctl.scala 274:30] - wire int_timers_io_csr_mitctl0; // @[dec_tlu_ctl.scala 274:30] - wire int_timers_io_csr_mitctl1; // @[dec_tlu_ctl.scala 274:30] - wire int_timers_io_csr_mitb0; // @[dec_tlu_ctl.scala 274:30] - wire int_timers_io_csr_mitb1; // @[dec_tlu_ctl.scala 274:30] - wire int_timers_io_csr_mitcnt0; // @[dec_tlu_ctl.scala 274:30] - wire int_timers_io_csr_mitcnt1; // @[dec_tlu_ctl.scala 274:30] - wire int_timers_io_dec_pause_state; // @[dec_tlu_ctl.scala 274:30] - wire int_timers_io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 274:30] - wire int_timers_io_internal_dbg_halt_timers; // @[dec_tlu_ctl.scala 274:30] - wire [31:0] int_timers_io_dec_timer_rddata_d; // @[dec_tlu_ctl.scala 274:30] - wire int_timers_io_dec_timer_read_d; // @[dec_tlu_ctl.scala 274:30] - wire int_timers_io_dec_timer_t0_pulse; // @[dec_tlu_ctl.scala 274:30] - wire int_timers_io_dec_timer_t1_pulse; // @[dec_tlu_ctl.scala 274:30] + wire int_timers_clock; // @[dec_tlu_ctl.scala 275:30] + wire int_timers_reset; // @[dec_tlu_ctl.scala 275:30] + wire int_timers_io_free_clk; // @[dec_tlu_ctl.scala 275:30] + wire int_timers_io_scan_mode; // @[dec_tlu_ctl.scala 275:30] + wire int_timers_io_dec_csr_wen_r_mod; // @[dec_tlu_ctl.scala 275:30] + wire [11:0] int_timers_io_dec_csr_wraddr_r; // @[dec_tlu_ctl.scala 275:30] + wire [31:0] int_timers_io_dec_csr_wrdata_r; // @[dec_tlu_ctl.scala 275:30] + wire int_timers_io_csr_mitctl0; // @[dec_tlu_ctl.scala 275:30] + wire int_timers_io_csr_mitctl1; // @[dec_tlu_ctl.scala 275:30] + wire int_timers_io_csr_mitb0; // @[dec_tlu_ctl.scala 275:30] + wire int_timers_io_csr_mitb1; // @[dec_tlu_ctl.scala 275:30] + wire int_timers_io_csr_mitcnt0; // @[dec_tlu_ctl.scala 275:30] + wire int_timers_io_csr_mitcnt1; // @[dec_tlu_ctl.scala 275:30] + wire int_timers_io_dec_pause_state; // @[dec_tlu_ctl.scala 275:30] + wire int_timers_io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 275:30] + wire int_timers_io_internal_dbg_halt_timers; // @[dec_tlu_ctl.scala 275:30] + wire [31:0] int_timers_io_dec_timer_rddata_d; // @[dec_tlu_ctl.scala 275:30] + wire int_timers_io_dec_timer_read_d; // @[dec_tlu_ctl.scala 275:30] + wire int_timers_io_dec_timer_t0_pulse; // @[dec_tlu_ctl.scala 275:30] + wire int_timers_io_dec_timer_t1_pulse; // @[dec_tlu_ctl.scala 275:30] wire rvclkhdr_io_l1clk; // @[lib.scala 343:22] wire rvclkhdr_io_clk; // @[lib.scala 343:22] wire rvclkhdr_io_en; // @[lib.scala 343:22] @@ -54844,25 +54884,25 @@ module dec_tlu_ctl( wire csr_read_io_csr_pkt_postsync; // @[dec_tlu_ctl.scala 1010:22] wire csr_read_io_csr_pkt_legal; // @[dec_tlu_ctl.scala 1010:22] reg dbg_halt_state_f; // @[dec_tlu_ctl.scala 366:89] - wire _T = ~dbg_halt_state_f; // @[dec_tlu_ctl.scala 273:39] + wire _T = ~dbg_halt_state_f; // @[dec_tlu_ctl.scala 274:39] reg mpc_halt_state_f; // @[dec_tlu_ctl.scala 361:89] wire [2:0] _T_3 = {io_i_cpu_run_req,io_mpc_debug_halt_req,io_mpc_debug_run_req}; // @[Cat.scala 29:58] wire [3:0] _T_6 = {io_nmi_int,io_timer_int,io_soft_int,io_i_cpu_halt_req}; // @[Cat.scala 29:58] reg [6:0] _T_8; // @[lib.scala 37:81] reg [6:0] syncro_ff; // @[lib.scala 37:58] - wire nmi_int_sync = syncro_ff[6]; // @[dec_tlu_ctl.scala 301:67] - wire i_cpu_halt_req_sync = syncro_ff[3]; // @[dec_tlu_ctl.scala 304:59] - wire i_cpu_run_req_sync = syncro_ff[2]; // @[dec_tlu_ctl.scala 305:59] - wire mpc_debug_halt_req_sync_raw = syncro_ff[1]; // @[dec_tlu_ctl.scala 306:51] - wire mpc_debug_run_req_sync = syncro_ff[0]; // @[dec_tlu_ctl.scala 307:51] + wire nmi_int_sync = syncro_ff[6]; // @[dec_tlu_ctl.scala 302:67] + wire i_cpu_halt_req_sync = syncro_ff[3]; // @[dec_tlu_ctl.scala 305:59] + wire i_cpu_run_req_sync = syncro_ff[2]; // @[dec_tlu_ctl.scala 306:59] + wire mpc_debug_halt_req_sync_raw = syncro_ff[1]; // @[dec_tlu_ctl.scala 307:51] + wire mpc_debug_run_req_sync = syncro_ff[0]; // @[dec_tlu_ctl.scala 308:51] wire dec_csr_wen_r_mod = csr_io_dec_csr_wen_r_mod; // @[dec_tlu_ctl.scala 1003:31] reg lsu_exc_valid_r_d1; // @[dec_tlu_ctl.scala 612:74] - wire _T_11 = io_lsu_error_pkt_r_valid | lsu_exc_valid_r_d1; // @[dec_tlu_ctl.scala 311:67] - reg e5_valid; // @[dec_tlu_ctl.scala 323:97] - wire e4e5_valid = io_dec_tlu_i0_valid_r | e5_valid; // @[dec_tlu_ctl.scala 314:30] - reg debug_mode_status; // @[dec_tlu_ctl.scala 324:81] + wire _T_11 = io_lsu_error_pkt_r_valid | lsu_exc_valid_r_d1; // @[dec_tlu_ctl.scala 312:67] + reg e5_valid; // @[dec_tlu_ctl.scala 324:97] + wire e4e5_valid = io_dec_tlu_i0_valid_r | e5_valid; // @[dec_tlu_ctl.scala 315:30] + reg debug_mode_status; // @[dec_tlu_ctl.scala 325:81] reg i_cpu_run_req_d1_raw; // @[dec_tlu_ctl.scala 572:80] - reg nmi_int_delayed; // @[dec_tlu_ctl.scala 339:72] + reg nmi_int_delayed; // @[dec_tlu_ctl.scala 338:72] wire _T_37 = ~nmi_int_delayed; // @[dec_tlu_ctl.scala 348:45] wire _T_38 = nmi_int_sync & _T_37; // @[dec_tlu_ctl.scala 348:43] reg mdseac_locked_f; // @[dec_tlu_ctl.scala 605:89] @@ -54870,7 +54910,7 @@ module dec_tlu_ctl( wire _T_36 = io_tlu_busbuff_lsu_imprecise_error_load_any | io_tlu_busbuff_lsu_imprecise_error_store_any; // @[dec_tlu_ctl.scala 346:96] wire nmi_lsu_detected = _T_35 & _T_36; // @[dec_tlu_ctl.scala 346:49] wire _T_39 = _T_38 | nmi_lsu_detected; // @[dec_tlu_ctl.scala 348:63] - reg nmi_int_detected_f; // @[dec_tlu_ctl.scala 340:72] + reg nmi_int_detected_f; // @[dec_tlu_ctl.scala 339:72] reg take_nmi_r_d1; // @[dec_tlu_ctl.scala 814:98] wire _T_40 = ~take_nmi_r_d1; // @[dec_tlu_ctl.scala 348:106] wire _T_41 = nmi_int_detected_f & _T_40; // @[dec_tlu_ctl.scala 348:104] @@ -54903,7 +54943,7 @@ module dec_tlu_ctl( wire _T_398 = ~i_cpu_halt_req_d1; // @[dec_tlu_ctl.scala 599:216] wire _T_399 = _T_397 & _T_398; // @[dec_tlu_ctl.scala 599:214] wire i_cpu_run_req_d1 = i_cpu_run_req_d1_raw | _T_399; // @[dec_tlu_ctl.scala 599:45] - wire _T_14 = debug_mode_status | i_cpu_run_req_d1; // @[dec_tlu_ctl.scala 315:50] + wire _T_14 = debug_mode_status | i_cpu_run_req_d1; // @[dec_tlu_ctl.scala 316:50] wire _T_685 = ~_T_43; // @[dec_tlu_ctl.scala 750:49] wire take_ext_int = take_ext_int_start_d3 & _T_685; // @[dec_tlu_ctl.scala 750:47] wire _T_698 = ~soft_int_ready; // @[dec_tlu_ctl.scala 767:40] @@ -54924,9 +54964,9 @@ module dec_tlu_ctl( wire dbg_halt_req_final = _T_106 & _T_107; // @[dec_tlu_ctl.scala 399:69] wire mpc_debug_halt_req_sync = mpc_debug_halt_req_sync_raw & _T_107; // @[dec_tlu_ctl.scala 358:67] wire _T_109 = dbg_halt_req_final | mpc_debug_halt_req_sync; // @[dec_tlu_ctl.scala 402:50] - reg reset_detect; // @[dec_tlu_ctl.scala 335:88] - reg reset_detected; // @[dec_tlu_ctl.scala 336:88] - wire reset_delayed = reset_detect ^ reset_detected; // @[dec_tlu_ctl.scala 337:64] + reg reset_detect; // @[dec_tlu_ctl.scala 334:88] + reg reset_detected; // @[dec_tlu_ctl.scala 335:88] + wire reset_delayed = reset_detect ^ reset_detected; // @[dec_tlu_ctl.scala 336:64] wire _T_110 = ~io_mpc_reset_run_req; // @[dec_tlu_ctl.scala 402:95] wire _T_111 = reset_delayed & _T_110; // @[dec_tlu_ctl.scala 402:93] wire _T_112 = _T_109 | _T_111; // @[dec_tlu_ctl.scala 402:76] @@ -55032,15 +55072,15 @@ module dec_tlu_ctl( wire _T_748 = _T_739 & _T_747; // @[dec_tlu_ctl.scala 771:62] wire _T_463 = io_dec_tlu_packet_r_pmu_i0_itype == 4'h8; // @[dec_tlu_ctl.scala 657:51] wire _T_464 = _T_463 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 657:64] - wire _T_297 = io_tlu_bp_dec_tlu_flush_lower_wb | io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 519:65] + wire _T_297 = io_dec_tlu_flush_lower_wb | io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 519:58] wire [3:0] _T_299 = _T_297 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] wire [3:0] _T_300 = ~_T_299; // @[dec_tlu_ctl.scala 519:23] wire [3:0] _T_292 = io_dec_tlu_i0_valid_r ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] wire [3:0] _T_294 = _T_292 & io_dec_tlu_packet_r_i0trigger; // @[dec_tlu_ctl.scala 517:53] - wire [9:0] mtdata1_t_3 = csr_io_mtdata1_t_3; // @[dec_tlu_ctl.scala 155:67 dec_tlu_ctl.scala 1009:33] - wire [9:0] mtdata1_t_2 = csr_io_mtdata1_t_2; // @[dec_tlu_ctl.scala 155:67 dec_tlu_ctl.scala 1009:33] - wire [9:0] mtdata1_t_1 = csr_io_mtdata1_t_1; // @[dec_tlu_ctl.scala 155:67 dec_tlu_ctl.scala 1009:33] - wire [9:0] mtdata1_t_0 = csr_io_mtdata1_t_0; // @[dec_tlu_ctl.scala 155:67 dec_tlu_ctl.scala 1009:33] + wire [9:0] mtdata1_t_3 = csr_io_mtdata1_t_3; // @[dec_tlu_ctl.scala 156:67 dec_tlu_ctl.scala 1009:33] + wire [9:0] mtdata1_t_2 = csr_io_mtdata1_t_2; // @[dec_tlu_ctl.scala 156:67 dec_tlu_ctl.scala 1009:33] + wire [9:0] mtdata1_t_1 = csr_io_mtdata1_t_1; // @[dec_tlu_ctl.scala 156:67 dec_tlu_ctl.scala 1009:33] + wire [9:0] mtdata1_t_0 = csr_io_mtdata1_t_0; // @[dec_tlu_ctl.scala 156:67 dec_tlu_ctl.scala 1009:33] wire [3:0] trigger_execute = {mtdata1_t_3[2],mtdata1_t_2[2],mtdata1_t_1[2],mtdata1_t_0[2]}; // @[Cat.scala 29:58] wire [3:0] trigger_data = {mtdata1_t_3[7],mtdata1_t_2[7],mtdata1_t_1[7],mtdata1_t_0[7]}; // @[Cat.scala 29:58] wire [3:0] _T_279 = trigger_execute & trigger_data; // @[dec_tlu_ctl.scala 509:57] @@ -55069,7 +55109,7 @@ module dec_tlu_ctl( wire _T_276 = _T_274 & mtdata1_t_0[3]; // @[dec_tlu_ctl.scala 506:352] wire [3:0] trigger_enabled = {_T_261,_T_266,_T_271,_T_276}; // @[Cat.scala 29:58] wire [3:0] i0trigger_qual_r = _T_296 & trigger_enabled; // @[dec_tlu_ctl.scala 517:146] - wire [3:0] i0_trigger_r = _T_300 & i0trigger_qual_r; // @[dec_tlu_ctl.scala 519:91] + wire [3:0] i0_trigger_r = _T_300 & i0trigger_qual_r; // @[dec_tlu_ctl.scala 519:84] wire _T_303 = ~mtdata1_t_2[5]; // @[dec_tlu_ctl.scala 522:60] wire _T_305 = _T_303 | i0_trigger_r[2]; // @[dec_tlu_ctl.scala 522:89] wire _T_306 = i0_trigger_r[3] & _T_305; // @[dec_tlu_ctl.scala 522:57] @@ -55086,12 +55126,12 @@ module dec_tlu_ctl( wire _T_466 = _T_464 & _T_465; // @[dec_tlu_ctl.scala 657:88] wire _T_468 = ~dcsr[15]; // @[dec_tlu_ctl.scala 657:110] wire _T_469 = _T_466 & _T_468; // @[dec_tlu_ctl.scala 657:108] - reg tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 327:80] + reg tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 328:80] wire _T_429 = ~tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 632:44] wire _T_430 = io_dec_tlu_i0_valid_r & _T_429; // @[dec_tlu_ctl.scala 632:42] wire _T_432 = _T_430 & _T_283; // @[dec_tlu_ctl.scala 632:66] - reg ic_perr_r_d1; // @[dec_tlu_ctl.scala 321:89] - reg iccm_sbecc_r_d1; // @[dec_tlu_ctl.scala 322:89] + reg ic_perr_r_d1; // @[dec_tlu_ctl.scala 322:89] + reg iccm_sbecc_r_d1; // @[dec_tlu_ctl.scala 323:89] wire _T_433 = ic_perr_r_d1 | iccm_sbecc_r_d1; // @[dec_tlu_ctl.scala 632:154] wire _T_435 = _T_433 & _T_107; // @[dec_tlu_ctl.scala 632:173] wire _T_436 = _T_432 | _T_435; // @[dec_tlu_ctl.scala 632:137] @@ -55121,7 +55161,7 @@ module dec_tlu_ctl( wire _T_528 = ~io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 685:92] wire i0_exception_valid_r = _T_527 & _T_528; // @[dec_tlu_ctl.scala 685:90] wire _T_789 = i0_exception_valid_r | rfpc_i0_r; // @[dec_tlu_ctl.scala 784:49] - wire _T_402 = ~io_tlu_bp_dec_tlu_flush_lower_wb; // @[dec_tlu_ctl.scala 608:57] + wire _T_402 = ~io_dec_tlu_flush_lower_wb; // @[dec_tlu_ctl.scala 608:57] wire lsu_exc_valid_r_raw = io_lsu_error_pkt_r_valid & _T_402; // @[dec_tlu_ctl.scala 608:55] wire _T_403 = io_lsu_error_pkt_r_valid & lsu_exc_valid_r_raw; // @[dec_tlu_ctl.scala 610:40] wire _T_405 = _T_403 & _T_465; // @[dec_tlu_ctl.scala 610:62] @@ -55142,7 +55182,7 @@ module dec_tlu_ctl( wire _T_421 = ~request_debug_mode_r_d1; // @[dec_tlu_ctl.scala 623:121] wire _T_422 = _T_420 & _T_421; // @[dec_tlu_ctl.scala 623:119] wire tlu_i0_commit_cmt = _T_422 & _T_465; // @[dec_tlu_ctl.scala 623:146] - reg iccm_repair_state_d1; // @[dec_tlu_ctl.scala 320:80] + reg iccm_repair_state_d1; // @[dec_tlu_ctl.scala 321:80] wire _T_444 = tlu_i0_commit_cmt & iccm_repair_state_d1; // @[dec_tlu_ctl.scala 641:52] wire _T_484 = io_dec_tlu_packet_r_pmu_i0_itype == 4'hc; // @[dec_tlu_ctl.scala 660:51] wire _T_485 = _T_484 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 660:64] @@ -55238,32 +55278,32 @@ module dec_tlu_ctl( wire _T_734 = _T_732 & _T_702; // @[dec_tlu_ctl.scala 769:231] wire take_int_timer1_int = _T_734 & _T_704; // @[dec_tlu_ctl.scala 769:247] wire interrupt_valid_r = _T_766 | take_int_timer1_int; // @[dec_tlu_ctl.scala 774:118] - wire _T_15 = _T_14 | interrupt_valid_r; // @[dec_tlu_ctl.scala 315:69] - wire _T_16 = _T_15 | interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 315:89] - wire _T_17 = _T_16 | reset_delayed; // @[dec_tlu_ctl.scala 315:112] - wire _T_18 = _T_17 | pause_expired_r; // @[dec_tlu_ctl.scala 315:128] + wire _T_15 = _T_14 | interrupt_valid_r; // @[dec_tlu_ctl.scala 316:69] + wire _T_16 = _T_15 | interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 316:89] + wire _T_17 = _T_16 | reset_delayed; // @[dec_tlu_ctl.scala 316:112] + wire _T_18 = _T_17 | pause_expired_r; // @[dec_tlu_ctl.scala 316:128] reg pause_expired_wb; // @[dec_tlu_ctl.scala 815:90] - wire _T_19 = _T_18 | pause_expired_wb; // @[dec_tlu_ctl.scala 315:146] + wire _T_19 = _T_18 | pause_expired_wb; // @[dec_tlu_ctl.scala 316:146] wire _T_496 = io_tlu_mem_ifu_ic_error_start & _T_107; // @[dec_tlu_ctl.scala 663:51] wire _T_498 = _T_152 | dcsr_single_step_running; // @[dec_tlu_ctl.scala 663:101] wire _T_499 = _T_496 & _T_498; // @[dec_tlu_ctl.scala 663:72] wire _T_500 = ~internal_pmu_fw_halt_mode_f; // @[dec_tlu_ctl.scala 663:131] wire ic_perr_r = _T_499 & _T_500; // @[dec_tlu_ctl.scala 663:129] - wire _T_20 = _T_19 | ic_perr_r; // @[dec_tlu_ctl.scala 315:165] - wire _T_21 = _T_20 | ic_perr_r_d1; // @[dec_tlu_ctl.scala 315:177] + wire _T_20 = _T_19 | ic_perr_r; // @[dec_tlu_ctl.scala 316:165] + wire _T_21 = _T_20 | ic_perr_r_d1; // @[dec_tlu_ctl.scala 316:177] wire _T_503 = io_tlu_mem_ifu_iccm_rd_ecc_single_err & _T_107; // @[dec_tlu_ctl.scala 664:59] wire _T_506 = _T_503 & _T_498; // @[dec_tlu_ctl.scala 664:80] wire iccm_sbecc_r = _T_506 & _T_500; // @[dec_tlu_ctl.scala 664:137] - wire _T_22 = _T_21 | iccm_sbecc_r; // @[dec_tlu_ctl.scala 315:192] - wire _T_23 = _T_22 | iccm_sbecc_r_d1; // @[dec_tlu_ctl.scala 315:207] - wire flush_clkvalid = _T_23 | io_dec_tlu_dec_clk_override; // @[dec_tlu_ctl.scala 315:225] - reg lsu_pmu_load_external_r; // @[dec_tlu_ctl.scala 325:80] - reg lsu_pmu_store_external_r; // @[dec_tlu_ctl.scala 326:72] - reg _T_32; // @[dec_tlu_ctl.scala 328:73] - reg internal_dbg_halt_mode_f2; // @[dec_tlu_ctl.scala 329:72] - reg _T_33; // @[dec_tlu_ctl.scala 330:89] - reg nmi_lsu_load_type_f; // @[dec_tlu_ctl.scala 341:72] - reg nmi_lsu_store_type_f; // @[dec_tlu_ctl.scala 342:72] + wire _T_22 = _T_21 | iccm_sbecc_r; // @[dec_tlu_ctl.scala 316:192] + wire _T_23 = _T_22 | iccm_sbecc_r_d1; // @[dec_tlu_ctl.scala 316:207] + wire flush_clkvalid = _T_23 | io_dec_tlu_dec_clk_override; // @[dec_tlu_ctl.scala 316:225] + reg lsu_pmu_load_external_r; // @[dec_tlu_ctl.scala 326:80] + reg lsu_pmu_store_external_r; // @[dec_tlu_ctl.scala 327:72] + reg _T_32; // @[dec_tlu_ctl.scala 329:73] + reg internal_dbg_halt_mode_f2; // @[dec_tlu_ctl.scala 330:72] + reg _T_33; // @[dec_tlu_ctl.scala 331:89] + reg nmi_lsu_load_type_f; // @[dec_tlu_ctl.scala 340:72] + reg nmi_lsu_store_type_f; // @[dec_tlu_ctl.scala 341:72] wire _T_46 = nmi_lsu_detected & io_tlu_busbuff_lsu_imprecise_error_load_any; // @[dec_tlu_ctl.scala 350:48] wire _T_49 = ~_T_41; // @[dec_tlu_ctl.scala 350:96] wire _T_50 = _T_46 & _T_49; // @[dec_tlu_ctl.scala 350:94] @@ -55448,7 +55488,7 @@ module dec_tlu_ctl( reg take_ext_int_start_d2; // @[dec_tlu_ctl.scala 744:62] wire _T_681 = take_ext_int_start | take_ext_int_start_d1; // @[dec_tlu_ctl.scala 749:46] wire _T_682 = _T_681 | take_ext_int_start_d2; // @[dec_tlu_ctl.scala 749:70] - wire csr_pkt_csr_meicpct = csr_read_io_csr_pkt_csr_meicpct; // @[dec_tlu_ctl.scala 270:41 dec_tlu_ctl.scala 1012:16] + wire csr_pkt_csr_meicpct = csr_read_io_csr_pkt_csr_meicpct; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1012:16] wire fast_int_meicpct = csr_pkt_csr_meicpct & io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 751:49] wire [30:0] mtvec = csr_io_mtvec; // @[dec_tlu_ctl.scala 1007:31] wire [30:0] _T_769 = {mtvec[30:1],1'h0}; // @[Cat.scala 29:58] @@ -55507,46 +55547,46 @@ module dec_tlu_ctl( wire _T_860 = ~illegal_r; // @[dec_tlu_ctl.scala 812:119] reg i0_valid_wb; // @[dec_tlu_ctl.scala 812:97] reg trigger_hit_r_d1; // @[dec_tlu_ctl.scala 813:89] - wire csr_pkt_presync = csr_read_io_csr_pkt_presync; // @[dec_tlu_ctl.scala 270:41 dec_tlu_ctl.scala 1012:16] + wire csr_pkt_presync = csr_read_io_csr_pkt_presync; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1012:16] wire _T_864 = csr_pkt_presync & io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 1014:42] wire _T_865 = ~io_dec_csr_wen_unq_d; // @[dec_tlu_ctl.scala 1014:67] - wire csr_pkt_postsync = csr_read_io_csr_pkt_postsync; // @[dec_tlu_ctl.scala 270:41 dec_tlu_ctl.scala 1012:16] - wire csr_pkt_csr_dcsr = csr_read_io_csr_pkt_csr_dcsr; // @[dec_tlu_ctl.scala 270:41 dec_tlu_ctl.scala 1012:16] - wire csr_pkt_csr_dpc = csr_read_io_csr_pkt_csr_dpc; // @[dec_tlu_ctl.scala 270:41 dec_tlu_ctl.scala 1012:16] + wire csr_pkt_postsync = csr_read_io_csr_pkt_postsync; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1012:16] + wire csr_pkt_csr_dcsr = csr_read_io_csr_pkt_csr_dcsr; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1012:16] + wire csr_pkt_csr_dpc = csr_read_io_csr_pkt_csr_dpc; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1012:16] wire _T_874 = csr_pkt_csr_dcsr | csr_pkt_csr_dpc; // @[dec_tlu_ctl.scala 1019:55] - wire csr_pkt_csr_dmst = csr_read_io_csr_pkt_csr_dmst; // @[dec_tlu_ctl.scala 270:41 dec_tlu_ctl.scala 1012:16] + wire csr_pkt_csr_dmst = csr_read_io_csr_pkt_csr_dmst; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1012:16] wire _T_875 = _T_874 | csr_pkt_csr_dmst; // @[dec_tlu_ctl.scala 1019:73] - wire csr_pkt_csr_dicawics = csr_read_io_csr_pkt_csr_dicawics; // @[dec_tlu_ctl.scala 270:41 dec_tlu_ctl.scala 1012:16] + wire csr_pkt_csr_dicawics = csr_read_io_csr_pkt_csr_dicawics; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1012:16] wire _T_876 = _T_875 | csr_pkt_csr_dicawics; // @[dec_tlu_ctl.scala 1019:92] - wire csr_pkt_csr_dicad0 = csr_read_io_csr_pkt_csr_dicad0; // @[dec_tlu_ctl.scala 270:41 dec_tlu_ctl.scala 1012:16] + wire csr_pkt_csr_dicad0 = csr_read_io_csr_pkt_csr_dicad0; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1012:16] wire _T_877 = _T_876 | csr_pkt_csr_dicad0; // @[dec_tlu_ctl.scala 1019:115] - wire csr_pkt_csr_dicad0h = csr_read_io_csr_pkt_csr_dicad0h; // @[dec_tlu_ctl.scala 270:41 dec_tlu_ctl.scala 1012:16] + wire csr_pkt_csr_dicad0h = csr_read_io_csr_pkt_csr_dicad0h; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1012:16] wire _T_878 = _T_877 | csr_pkt_csr_dicad0h; // @[dec_tlu_ctl.scala 1019:136] - wire csr_pkt_csr_dicad1 = csr_read_io_csr_pkt_csr_dicad1; // @[dec_tlu_ctl.scala 270:41 dec_tlu_ctl.scala 1012:16] + wire csr_pkt_csr_dicad1 = csr_read_io_csr_pkt_csr_dicad1; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1012:16] wire _T_879 = _T_878 | csr_pkt_csr_dicad1; // @[dec_tlu_ctl.scala 1019:158] - wire csr_pkt_csr_dicago = csr_read_io_csr_pkt_csr_dicago; // @[dec_tlu_ctl.scala 270:41 dec_tlu_ctl.scala 1012:16] + wire csr_pkt_csr_dicago = csr_read_io_csr_pkt_csr_dicago; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1012:16] wire _T_880 = _T_879 | csr_pkt_csr_dicago; // @[dec_tlu_ctl.scala 1019:179] wire _T_881 = ~_T_880; // @[dec_tlu_ctl.scala 1019:36] wire _T_882 = _T_881 | dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 1019:201] - wire csr_pkt_legal = csr_read_io_csr_pkt_legal; // @[dec_tlu_ctl.scala 270:41 dec_tlu_ctl.scala 1012:16] + wire csr_pkt_legal = csr_read_io_csr_pkt_legal; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1012:16] wire _T_883 = csr_pkt_legal & _T_882; // @[dec_tlu_ctl.scala 1019:33] wire _T_884 = ~fast_int_meicpct; // @[dec_tlu_ctl.scala 1019:223] wire valid_csr = _T_883 & _T_884; // @[dec_tlu_ctl.scala 1019:221] wire _T_887 = io_dec_csr_any_unq_d & valid_csr; // @[dec_tlu_ctl.scala 1021:46] - wire csr_pkt_csr_mvendorid = csr_read_io_csr_pkt_csr_mvendorid; // @[dec_tlu_ctl.scala 270:41 dec_tlu_ctl.scala 1012:16] - wire csr_pkt_csr_marchid = csr_read_io_csr_pkt_csr_marchid; // @[dec_tlu_ctl.scala 270:41 dec_tlu_ctl.scala 1012:16] + wire csr_pkt_csr_mvendorid = csr_read_io_csr_pkt_csr_mvendorid; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1012:16] + wire csr_pkt_csr_marchid = csr_read_io_csr_pkt_csr_marchid; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1012:16] wire _T_888 = csr_pkt_csr_mvendorid | csr_pkt_csr_marchid; // @[dec_tlu_ctl.scala 1021:107] - wire csr_pkt_csr_mimpid = csr_read_io_csr_pkt_csr_mimpid; // @[dec_tlu_ctl.scala 270:41 dec_tlu_ctl.scala 1012:16] + wire csr_pkt_csr_mimpid = csr_read_io_csr_pkt_csr_mimpid; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1012:16] wire _T_889 = _T_888 | csr_pkt_csr_mimpid; // @[dec_tlu_ctl.scala 1021:129] - wire csr_pkt_csr_mhartid = csr_read_io_csr_pkt_csr_mhartid; // @[dec_tlu_ctl.scala 270:41 dec_tlu_ctl.scala 1012:16] + wire csr_pkt_csr_mhartid = csr_read_io_csr_pkt_csr_mhartid; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1012:16] wire _T_890 = _T_889 | csr_pkt_csr_mhartid; // @[dec_tlu_ctl.scala 1021:150] - wire csr_pkt_csr_mdseac = csr_read_io_csr_pkt_csr_mdseac; // @[dec_tlu_ctl.scala 270:41 dec_tlu_ctl.scala 1012:16] + wire csr_pkt_csr_mdseac = csr_read_io_csr_pkt_csr_mdseac; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1012:16] wire _T_891 = _T_890 | csr_pkt_csr_mdseac; // @[dec_tlu_ctl.scala 1021:172] - wire csr_pkt_csr_meihap = csr_read_io_csr_pkt_csr_meihap; // @[dec_tlu_ctl.scala 270:41 dec_tlu_ctl.scala 1012:16] + wire csr_pkt_csr_meihap = csr_read_io_csr_pkt_csr_meihap; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1012:16] wire _T_892 = _T_891 | csr_pkt_csr_meihap; // @[dec_tlu_ctl.scala 1021:193] wire _T_893 = io_dec_csr_wen_unq_d & _T_892; // @[dec_tlu_ctl.scala 1021:82] wire _T_894 = ~_T_893; // @[dec_tlu_ctl.scala 1021:59] - dec_timer_ctl int_timers ( // @[dec_tlu_ctl.scala 274:30] + dec_timer_ctl int_timers ( // @[dec_tlu_ctl.scala 275:30] .clock(int_timers_clock), .reset(int_timers_reset), .io_free_clk(int_timers_io_free_clk), @@ -55983,8 +56023,8 @@ module dec_tlu_ctl( assign io_debug_brkpt_status = debug_brkpt_status_f; // @[dec_tlu_ctl.scala 395:31] assign io_dec_csr_rddata_d = csr_io_dec_csr_rddata_d; // @[dec_tlu_ctl.scala 897:40] assign io_dec_csr_legal_d = _T_887 & _T_894; // @[dec_tlu_ctl.scala 1021:20] - assign io_dec_tlu_i0_kill_writeb_wb = _T_32; // @[dec_tlu_ctl.scala 328:41] - assign io_dec_tlu_i0_kill_writeb_r = _T_427 | i0_trigger_hit_raw_r; // @[dec_tlu_ctl.scala 334:41] + assign io_dec_tlu_i0_kill_writeb_wb = _T_32; // @[dec_tlu_ctl.scala 329:41] + assign io_dec_tlu_i0_kill_writeb_r = _T_427 | i0_trigger_hit_raw_r; // @[dec_tlu_ctl.scala 333:41] assign io_dec_tlu_wr_pause_r = csr_io_dec_tlu_wr_pause_r; // @[dec_tlu_ctl.scala 899:40] assign io_dec_tlu_flush_pause_r = _T_208 & _T_209; // @[dec_tlu_ctl.scala 479:34] assign io_dec_tlu_presync_d = _T_864 & _T_865; // @[dec_tlu_ctl.scala 1014:23] @@ -56005,20 +56045,20 @@ module dec_tlu_ctl( assign io_dec_tlu_pic_clk_override = csr_io_dec_tlu_pic_clk_override; // @[dec_tlu_ctl.scala 894:40] assign io_dec_tlu_dccm_clk_override = csr_io_dec_tlu_dccm_clk_override; // @[dec_tlu_ctl.scala 895:40] assign io_dec_tlu_icm_clk_override = csr_io_dec_tlu_icm_clk_override; // @[dec_tlu_ctl.scala 896:40] + assign io_dec_tlu_flush_lower_wb = tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 800:41] assign io_tlu_bp_dec_tlu_br0_r_pkt_valid = _T_459 & _T_462; // @[dec_tlu_ctl.scala 652:57] assign io_tlu_bp_dec_tlu_br0_r_pkt_bits_hist = io_tlu_exu_exu_i0_br_hist_r; // @[dec_tlu_ctl.scala 649:65] assign io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_error = _T_453 & _T_429; // @[dec_tlu_ctl.scala 650:57] assign io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_start_error = _T_455 & _T_429; // @[dec_tlu_ctl.scala 651:57] assign io_tlu_bp_dec_tlu_br0_r_pkt_bits_way = io_exu_i0_br_way_r; // @[dec_tlu_ctl.scala 653:65] assign io_tlu_bp_dec_tlu_br0_r_pkt_bits_middle = io_tlu_exu_exu_i0_br_middle_r; // @[dec_tlu_ctl.scala 654:65] - assign io_tlu_bp_dec_tlu_flush_lower_wb = tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 800:49] assign io_tlu_bp_dec_tlu_flush_leak_one_wb = _T_233 & _T_234; // @[dec_tlu_ctl.scala 483:45] assign io_tlu_bp_dec_tlu_bpred_disable = csr_io_dec_tlu_bpred_disable; // @[dec_tlu_ctl.scala 902:47] assign io_tlu_ifc_dec_tlu_flush_noredir_wb = _T_205 | take_ext_int_start; // @[dec_tlu_ctl.scala 474:45] assign io_tlu_ifc_dec_tlu_mrac_ff = csr_io_dec_tlu_mrac_ff; // @[dec_tlu_ctl.scala 900:48] assign io_tlu_mem_dec_tlu_flush_err_wb = io_tlu_exu_dec_tlu_flush_lower_r & _T_433; // @[dec_tlu_ctl.scala 484:41] assign io_tlu_mem_dec_tlu_i0_commit_cmt = _T_422 & _T_465; // @[dec_tlu_ctl.scala 627:37] - assign io_tlu_mem_dec_tlu_force_halt = _T_33; // @[dec_tlu_ctl.scala 330:57] + assign io_tlu_mem_dec_tlu_force_halt = _T_33; // @[dec_tlu_ctl.scala 331:57] assign io_tlu_mem_dec_tlu_fence_i_wb = _T_492 & _T_470; // @[dec_tlu_ctl.scala 672:39] assign io_tlu_mem_dec_tlu_ic_diag_pkt_icache_wrdata = csr_io_dec_tlu_ic_diag_pkt_icache_wrdata; // @[dec_tlu_ctl.scala 881:52] assign io_tlu_mem_dec_tlu_ic_diag_pkt_icache_dicawics = csr_io_dec_tlu_ic_diag_pkt_icache_dicawics; // @[dec_tlu_ctl.scala 881:52] @@ -56032,20 +56072,20 @@ module dec_tlu_ctl( assign io_dec_pic_dec_tlu_meipt = csr_io_dec_tlu_meipt; // @[dec_tlu_ctl.scala 877:52] assign int_timers_clock = clock; assign int_timers_reset = reset; - assign int_timers_io_free_clk = io_free_clk; // @[dec_tlu_ctl.scala 275:57] - assign int_timers_io_scan_mode = io_scan_mode; // @[dec_tlu_ctl.scala 276:57] - assign int_timers_io_dec_csr_wen_r_mod = csr_io_dec_csr_wen_r_mod; // @[dec_tlu_ctl.scala 277:49] - assign int_timers_io_dec_csr_wraddr_r = io_dec_csr_wraddr_r; // @[dec_tlu_ctl.scala 279:49] - assign int_timers_io_dec_csr_wrdata_r = io_dec_csr_wrdata_r; // @[dec_tlu_ctl.scala 280:49] - assign int_timers_io_csr_mitctl0 = csr_read_io_csr_pkt_csr_mitctl0; // @[dec_tlu_ctl.scala 281:57] - assign int_timers_io_csr_mitctl1 = csr_read_io_csr_pkt_csr_mitctl1; // @[dec_tlu_ctl.scala 282:57] - assign int_timers_io_csr_mitb0 = csr_read_io_csr_pkt_csr_mitb0; // @[dec_tlu_ctl.scala 283:57] - assign int_timers_io_csr_mitb1 = csr_read_io_csr_pkt_csr_mitb1; // @[dec_tlu_ctl.scala 284:57] - assign int_timers_io_csr_mitcnt0 = csr_read_io_csr_pkt_csr_mitcnt0; // @[dec_tlu_ctl.scala 285:57] - assign int_timers_io_csr_mitcnt1 = csr_read_io_csr_pkt_csr_mitcnt1; // @[dec_tlu_ctl.scala 286:57] - assign int_timers_io_dec_pause_state = io_dec_pause_state; // @[dec_tlu_ctl.scala 287:49] - assign int_timers_io_dec_tlu_pmu_fw_halted = pmu_fw_tlu_halted_f; // @[dec_tlu_ctl.scala 288:49] - assign int_timers_io_internal_dbg_halt_timers = debug_mode_status & _T_665; // @[dec_tlu_ctl.scala 289:47] + assign int_timers_io_free_clk = io_free_clk; // @[dec_tlu_ctl.scala 276:57] + assign int_timers_io_scan_mode = io_scan_mode; // @[dec_tlu_ctl.scala 277:57] + assign int_timers_io_dec_csr_wen_r_mod = csr_io_dec_csr_wen_r_mod; // @[dec_tlu_ctl.scala 278:49] + assign int_timers_io_dec_csr_wraddr_r = io_dec_csr_wraddr_r; // @[dec_tlu_ctl.scala 280:49] + assign int_timers_io_dec_csr_wrdata_r = io_dec_csr_wrdata_r; // @[dec_tlu_ctl.scala 281:49] + assign int_timers_io_csr_mitctl0 = csr_read_io_csr_pkt_csr_mitctl0; // @[dec_tlu_ctl.scala 282:57] + assign int_timers_io_csr_mitctl1 = csr_read_io_csr_pkt_csr_mitctl1; // @[dec_tlu_ctl.scala 283:57] + assign int_timers_io_csr_mitb0 = csr_read_io_csr_pkt_csr_mitb0; // @[dec_tlu_ctl.scala 284:57] + assign int_timers_io_csr_mitb1 = csr_read_io_csr_pkt_csr_mitb1; // @[dec_tlu_ctl.scala 285:57] + assign int_timers_io_csr_mitcnt0 = csr_read_io_csr_pkt_csr_mitcnt0; // @[dec_tlu_ctl.scala 286:57] + assign int_timers_io_csr_mitcnt1 = csr_read_io_csr_pkt_csr_mitcnt1; // @[dec_tlu_ctl.scala 287:57] + assign int_timers_io_dec_pause_state = io_dec_pause_state; // @[dec_tlu_ctl.scala 288:49] + assign int_timers_io_dec_tlu_pmu_fw_halted = pmu_fw_tlu_halted_f; // @[dec_tlu_ctl.scala 289:49] + assign int_timers_io_internal_dbg_halt_timers = debug_mode_status & _T_665; // @[dec_tlu_ctl.scala 290:47] assign rvclkhdr_io_clk = clock; // @[lib.scala 344:17] assign rvclkhdr_io_en = dec_csr_wen_r_mod | io_dec_tlu_dec_clk_override; // @[lib.scala 345:16] assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] @@ -58186,6 +58226,9 @@ module dec( wire [1:0] decode_io_dctl_busbuff_lsu_nonblock_load_data_tag; // @[dec.scala 118:22] wire [31:0] decode_io_dctl_busbuff_lsu_nonblock_load_data; // @[dec.scala 118:22] wire decode_io_dctl_dma_dma_dccm_stall_any; // @[dec.scala 118:22] + wire decode_io_dec_aln_dec_i0_decode_d; // @[dec.scala 118:22] + wire [15:0] decode_io_dec_aln_ifu_i0_cinst; // @[dec.scala 118:22] + wire [1:0] decode_io_dbg_dctl_dbg_cmd_wrdata; // @[dec.scala 118:22] wire decode_io_dec_tlu_flush_extint; // @[dec.scala 118:22] wire decode_io_dec_tlu_force_halt; // @[dec.scala 118:22] wire [31:0] decode_io_dec_i0_inst_wb1; // @[dec.scala 118:22] @@ -58283,9 +58326,6 @@ module dec( wire decode_io_dec_pause_state_cg; // @[dec.scala 118:22] wire decode_io_dec_div_active; // @[dec.scala 118:22] wire decode_io_scan_mode; // @[dec.scala 118:22] - wire decode_io_dec_aln_dec_i0_decode_d; // @[dec.scala 118:22] - wire [15:0] decode_io_dec_aln_ifu_i0_cinst; // @[dec.scala 118:22] - wire [1:0] decode_io_dbg_dctl_dbg_cmd_wrdata; // @[dec.scala 118:22] wire gpr_clock; // @[dec.scala 119:19] wire gpr_reset; // @[dec.scala 119:19] wire [4:0] gpr_io_raddr0; // @[dec.scala 119:19] @@ -58448,6 +58488,7 @@ module dec( wire tlu_io_dec_tlu_pic_clk_override; // @[dec.scala 120:19] wire tlu_io_dec_tlu_dccm_clk_override; // @[dec.scala 120:19] wire tlu_io_dec_tlu_icm_clk_override; // @[dec.scala 120:19] + wire tlu_io_dec_tlu_flush_lower_wb; // @[dec.scala 120:19] wire tlu_io_ifu_pmu_instr_aligned; // @[dec.scala 120:19] wire tlu_io_tlu_bp_dec_tlu_br0_r_pkt_valid; // @[dec.scala 120:19] wire [1:0] tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_hist; // @[dec.scala 120:19] @@ -58455,7 +58496,6 @@ module dec( wire tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_start_error; // @[dec.scala 120:19] wire tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_way; // @[dec.scala 120:19] wire tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_middle; // @[dec.scala 120:19] - wire tlu_io_tlu_bp_dec_tlu_flush_lower_wb; // @[dec.scala 120:19] wire tlu_io_tlu_bp_dec_tlu_flush_leak_one_wb; // @[dec.scala 120:19] wire tlu_io_tlu_bp_dec_tlu_bpred_disable; // @[dec.scala 120:19] wire tlu_io_tlu_ifc_dec_tlu_flush_noredir_wb; // @[dec.scala 120:19] @@ -58638,6 +58678,9 @@ module dec( .io_dctl_busbuff_lsu_nonblock_load_data_tag(decode_io_dctl_busbuff_lsu_nonblock_load_data_tag), .io_dctl_busbuff_lsu_nonblock_load_data(decode_io_dctl_busbuff_lsu_nonblock_load_data), .io_dctl_dma_dma_dccm_stall_any(decode_io_dctl_dma_dma_dccm_stall_any), + .io_dec_aln_dec_i0_decode_d(decode_io_dec_aln_dec_i0_decode_d), + .io_dec_aln_ifu_i0_cinst(decode_io_dec_aln_ifu_i0_cinst), + .io_dbg_dctl_dbg_cmd_wrdata(decode_io_dbg_dctl_dbg_cmd_wrdata), .io_dec_tlu_flush_extint(decode_io_dec_tlu_flush_extint), .io_dec_tlu_force_halt(decode_io_dec_tlu_force_halt), .io_dec_i0_inst_wb1(decode_io_dec_i0_inst_wb1), @@ -58734,10 +58777,7 @@ module dec( .io_dec_pause_state(decode_io_dec_pause_state), .io_dec_pause_state_cg(decode_io_dec_pause_state_cg), .io_dec_div_active(decode_io_dec_div_active), - .io_scan_mode(decode_io_scan_mode), - .io_dec_aln_dec_i0_decode_d(decode_io_dec_aln_dec_i0_decode_d), - .io_dec_aln_ifu_i0_cinst(decode_io_dec_aln_ifu_i0_cinst), - .io_dbg_dctl_dbg_cmd_wrdata(decode_io_dbg_dctl_dbg_cmd_wrdata) + .io_scan_mode(decode_io_scan_mode) ); dec_gpr_ctl gpr ( // @[dec.scala 119:19] .clock(gpr_clock), @@ -58904,6 +58944,7 @@ module dec( .io_dec_tlu_pic_clk_override(tlu_io_dec_tlu_pic_clk_override), .io_dec_tlu_dccm_clk_override(tlu_io_dec_tlu_dccm_clk_override), .io_dec_tlu_icm_clk_override(tlu_io_dec_tlu_icm_clk_override), + .io_dec_tlu_flush_lower_wb(tlu_io_dec_tlu_flush_lower_wb), .io_ifu_pmu_instr_aligned(tlu_io_ifu_pmu_instr_aligned), .io_tlu_bp_dec_tlu_br0_r_pkt_valid(tlu_io_tlu_bp_dec_tlu_br0_r_pkt_valid), .io_tlu_bp_dec_tlu_br0_r_pkt_bits_hist(tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_hist), @@ -58911,7 +58952,6 @@ module dec( .io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_start_error(tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_start_error), .io_tlu_bp_dec_tlu_br0_r_pkt_bits_way(tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_way), .io_tlu_bp_dec_tlu_br0_r_pkt_bits_middle(tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_middle), - .io_tlu_bp_dec_tlu_flush_lower_wb(tlu_io_tlu_bp_dec_tlu_flush_lower_wb), .io_tlu_bp_dec_tlu_flush_leak_one_wb(tlu_io_tlu_bp_dec_tlu_flush_leak_one_wb), .io_tlu_bp_dec_tlu_bpred_disable(tlu_io_tlu_bp_dec_tlu_bpred_disable), .io_tlu_ifc_dec_tlu_flush_noredir_wb(tlu_io_tlu_ifc_dec_tlu_flush_noredir_wb), @@ -59169,6 +59209,8 @@ module dec( assign decode_io_dctl_busbuff_lsu_nonblock_load_data_tag = io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag; // @[dec.scala 141:26] assign decode_io_dctl_busbuff_lsu_nonblock_load_data = io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data; // @[dec.scala 141:26] assign decode_io_dctl_dma_dma_dccm_stall_any = io_dec_dma_dctl_dma_dma_dccm_stall_any; // @[dec.scala 138:22] + assign decode_io_dec_aln_ifu_i0_cinst = io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst; // @[dec.scala 133:21] + assign decode_io_dbg_dctl_dbg_cmd_wrdata = io_dec_dbg_dbg_dctl_dbg_cmd_wrdata; // @[dec.scala 150:22] assign decode_io_dec_tlu_flush_extint = tlu_io_dec_tlu_flush_extint; // @[dec.scala 139:48] assign decode_io_dec_tlu_force_halt = tlu_io_tlu_mem_dec_tlu_force_halt; // @[dec.scala 140:48] assign decode_io_dec_i0_trigger_match_d = dec_trigger_io_dec_i0_trigger_match_d; // @[dec.scala 142:48] @@ -59199,7 +59241,7 @@ module dec( assign decode_io_lsu_store_stall_any = io_lsu_store_stall_any; // @[dec.scala 162:48] assign decode_io_exu_div_wren = io_exu_div_wren; // @[dec.scala 163:48] assign decode_io_dec_tlu_i0_kill_writeb_wb = tlu_io_dec_tlu_i0_kill_writeb_wb; // @[dec.scala 164:48] - assign decode_io_dec_tlu_flush_lower_wb = tlu_io_tlu_bp_dec_tlu_flush_lower_wb; // @[dec.scala 165:48] + assign decode_io_dec_tlu_flush_lower_wb = tlu_io_dec_tlu_flush_lower_wb; // @[dec.scala 165:48] assign decode_io_dec_tlu_i0_kill_writeb_r = tlu_io_dec_tlu_i0_kill_writeb_r; // @[dec.scala 166:48] assign decode_io_dec_tlu_flush_lower_r = tlu_io_tlu_exu_dec_tlu_flush_lower_r; // @[dec.scala 167:48] assign decode_io_dec_tlu_flush_pause_r = tlu_io_dec_tlu_flush_pause_r; // @[dec.scala 168:48] @@ -59217,8 +59259,6 @@ module dec( assign decode_io_active_clk = io_active_clk; // @[dec.scala 180:48] assign decode_io_clk_override = tlu_io_dec_tlu_dec_clk_override; // @[dec.scala 181:48] assign decode_io_scan_mode = io_scan_mode; // @[dec.scala 182:48] - assign decode_io_dec_aln_ifu_i0_cinst = io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst; // @[dec.scala 133:21] - assign decode_io_dbg_dctl_dbg_cmd_wrdata = io_dec_dbg_dbg_dctl_dbg_cmd_wrdata; // @[dec.scala 150:22] assign gpr_clock = clock; assign gpr_reset = reset; assign gpr_io_raddr0 = decode_io_dec_i0_rs1_d; // @[dec.scala 189:23] diff --git a/src/main/scala/dec/dec_tlu_ctl.scala b/src/main/scala/dec/dec_tlu_ctl.scala index 030d289e..bc0c8d79 100644 --- a/src/main/scala/dec/dec_tlu_ctl.scala +++ b/src/main/scala/dec/dec_tlu_ctl.scala @@ -340,7 +340,8 @@ class dec_tlu_ctl extends Module with lib with RequireAsyncReset with CSR_VAL{ val nmi_lsu_load_type_f =withClock(io.free_clk){RegNext(nmi_lsu_load_type,0.U)} val nmi_lsu_store_type_f =withClock(io.free_clk){RegNext(nmi_lsu_store_type,0.U)} - + io.tlu_bp.dec_tlu_flush_lower_wb := io.dec_tlu_flush_lower_wb + io.tlu_mem.dec_tlu_flush_lower_wb := io.tlu_bp.dec_tlu_flush_lower_wb // Filter subsequent bus errors after the first, until the lock on MDSEAC is cleared val nmi_lsu_detected = ~mdseac_locked_f & (io.tlu_busbuff.lsu_imprecise_error_load_any | io.tlu_busbuff.lsu_imprecise_error_store_any) diff --git a/target/scala-2.12/classes/dec/csr_tlu.class b/target/scala-2.12/classes/dec/csr_tlu.class index f3452e79..327f4b50 100644 Binary files a/target/scala-2.12/classes/dec/csr_tlu.class and b/target/scala-2.12/classes/dec/csr_tlu.class differ diff --git a/target/scala-2.12/classes/dec/dec.class b/target/scala-2.12/classes/dec/dec.class index 9840b7a0..5bdff0f4 100644 Binary files a/target/scala-2.12/classes/dec/dec.class and b/target/scala-2.12/classes/dec/dec.class differ diff --git a/target/scala-2.12/classes/dec/dec_decode_ctl$$anon$1.class b/target/scala-2.12/classes/dec/dec_decode_ctl$$anon$1.class index b78a0315..2d1e1dbb 100644 Binary files a/target/scala-2.12/classes/dec/dec_decode_ctl$$anon$1.class and b/target/scala-2.12/classes/dec/dec_decode_ctl$$anon$1.class differ diff --git a/target/scala-2.12/classes/dec/dec_decode_ctl.class b/target/scala-2.12/classes/dec/dec_decode_ctl.class index 055c9906..df8af9a8 100644 Binary files a/target/scala-2.12/classes/dec/dec_decode_ctl.class and b/target/scala-2.12/classes/dec/dec_decode_ctl.class differ diff --git a/target/scala-2.12/classes/dec/dec_main$.class b/target/scala-2.12/classes/dec/dec_main$.class new file mode 100644 index 00000000..d34fba6c Binary files /dev/null and b/target/scala-2.12/classes/dec/dec_main$.class differ diff --git a/target/scala-2.12/classes/dec/dec_main$delayedInit$body.class b/target/scala-2.12/classes/dec/dec_main$delayedInit$body.class new file mode 100644 index 00000000..d85a14e8 Binary files /dev/null and b/target/scala-2.12/classes/dec/dec_main$delayedInit$body.class differ diff --git a/target/scala-2.12/classes/dec/dec_main.class b/target/scala-2.12/classes/dec/dec_main.class new file mode 100644 index 00000000..fb4d68aa Binary files /dev/null and b/target/scala-2.12/classes/dec/dec_main.class differ diff --git a/target/scala-2.12/classes/dec/dec_tlu_ctl.class b/target/scala-2.12/classes/dec/dec_tlu_ctl.class index 6538178d..1fab6346 100644 Binary files a/target/scala-2.12/classes/dec/dec_tlu_ctl.class and b/target/scala-2.12/classes/dec/dec_tlu_ctl.class differ diff --git a/target/scala-2.12/classes/dec/dec_tlu_ctl_IO.class b/target/scala-2.12/classes/dec/dec_tlu_ctl_IO.class index 685af7ea..6300180a 100644 Binary files a/target/scala-2.12/classes/dec/dec_tlu_ctl_IO.class and b/target/scala-2.12/classes/dec/dec_tlu_ctl_IO.class differ