quotient new corrected

This commit is contained in:
​Laraib Khan 2021-01-07 10:11:23 +05:00
parent 4e2d0d75c2
commit a1acaaa217
10 changed files with 2117 additions and 2143 deletions

File diff suppressed because it is too large Load Diff

File diff suppressed because it is too large Load Diff

View File

@ -602,13 +602,6 @@ class exu_div_new_3bit_fullshortq extends Module with RequireAsyncReset with lib
val shortq_shift = WireInit(0.U(5.W))
val shortq_decode = WireInit(0.U(5.W))
val shortq_shift_ff = WireInit(0.U(5.W))
val adder1_out = WireInit(0.U(34.W))
val adder2_out = WireInit(0.U(35.W))
val adder3_out = WireInit(0.U(36.W))
val adder4_out = WireInit(0.U(37.W))
val adder5_out = WireInit(0.U(37.W))
val adder6_out = WireInit(0.U(37.W))
val adder7_out = WireInit(0.U(37.W))
val valid_ff_in = io.valid_in & !io.cancel
val control_in = Cat((!io.valid_in & control_ff(2)) | (io.valid_in & io.signed_in & io.dividend_in(31)), (!io.valid_in & control_ff(1)) | (io.valid_in & io.signed_in & io.divisor_in(31)), (!io.valid_in & control_ff(0)) | (io.valid_in & io.rem_in))
val dividend_sign_ff = control_ff(2)
@ -642,13 +635,13 @@ class exu_div_new_3bit_fullshortq extends Module with RequireAsyncReset with lib
val r_adder6_sel = running_state & (quotient_new === 6.U) & !shortq_enable_ff
val r_adder7_sel = running_state & (quotient_new === 7.U) & !shortq_enable_ff
adder1_out := Cat(r_ff(30,0),a_ff(32,30)) + b_ff(33,0)
adder2_out := Cat(r_ff(31,0),a_ff(32,30)) + Cat(b_ff(33,0),0.U)
adder3_out := Cat(r_ff(32,0),a_ff(32,30)) + Cat(b_ff(34,0),0.U) + b_ff(35,0)
adder4_out := Cat(r_ff(32),r_ff(32,0),a_ff(32,30)) + Cat(b_ff(34,0),0.U(2.W))
adder5_out := Cat(r_ff(32),r_ff(32,0),a_ff(32,30)) + Cat(b_ff(34,0),0.U(2.W)) + b_ff
adder6_out := Cat(r_ff(32),r_ff(32,0),a_ff(32,30)) + Cat(b_ff(34,0),0.U(2.W)) + Cat(b_ff(35,0),0.U)
adder7_out := Cat(r_ff(32),r_ff(32,0),a_ff(32,30)) + Cat(b_ff(34,0),0.U(2.W)) + Cat(b_ff(35,0),0.U) + b_ff
val adder1_out = Cat(r_ff(30,0),a_ff(32,30)) + b_ff(33,0)
val adder2_out = Cat(r_ff(31,0),a_ff(32,30)) + Cat(b_ff(33,0),0.U)
val adder3_out = Cat(r_ff(32,0),a_ff(32,30)) + Cat(b_ff(34,0),0.U) + b_ff(35,0)
val adder4_out = Cat(r_ff(32),r_ff(32,0),a_ff(32,30)) + Cat(b_ff(34,0),0.U(2.W))
val adder5_out = Cat(r_ff(32),r_ff(32,0),a_ff(32,30)) + Cat(b_ff(34,0),0.U(2.W)) + b_ff
val adder6_out = Cat(r_ff(32),r_ff(32,0),a_ff(32,30)) + Cat(b_ff(34,0),0.U(2.W)) + Cat(b_ff(35,0),0.U)
val adder7_out = Cat(r_ff(32),r_ff(32,0),a_ff(32,30)) + Cat(b_ff(34,0),0.U(2.W)) + Cat(b_ff(35,0),0.U) + b_ff
quotient_raw := Cat((!adder7_out(36) ^ dividend_sign_ff) | ((a_ff(29,0) === 0.U) & (adder7_out === 0.U)),
(!adder6_out(36) ^ dividend_sign_ff) | ((a_ff(29,0) === 0.U) & (adder6_out === 0.U)),
(!adder5_out(36) ^ dividend_sign_ff) | ((a_ff(29,0) === 0.U) & (adder5_out === 0.U)),
@ -658,13 +651,12 @@ class exu_div_new_3bit_fullshortq extends Module with RequireAsyncReset with lib
(!adder1_out(33) ^ dividend_sign_ff) | ((a_ff(29,0) === 0.U) & (adder1_out === 0.U)), 0.U)
quotient_new := Cat ((quotient_raw(7) | quotient_raw(6) | quotient_raw(5) | quotient_raw(4)),
(quotient_raw(7) | quotient_raw(6) |(!quotient_raw(4) & quotient_raw(3)) |(!quotient_raw(3) & quotient_raw(2))),
(quotient_raw(7) | quotient_raw(6) & quotient_raw(5) |(!quotient_raw(4) & quotient_raw(3)) |(!quotient_raw(2) & quotient_raw(1))))
(quotient_raw(7) | (!quotient_raw(6) & quotient_raw(5)) | (!quotient_raw(4) & quotient_raw(3)) |(!quotient_raw(2) & quotient_raw(1))))
val twos_comp_in = Mux1H(Seq (
twos_comp_q_sel -> q_ff,
twos_comp_b_sel -> b_ff(31,0)
))
val twos_comp_out = rvtwoscomp(twos_comp_in)
val a_in = Mux1H(Seq (
(!a_shift & !shortq_enable_ff).asBool -> Cat(io.signed_in & io.dividend_in(31),io.dividend_in(31,0)),
a_shift -> Cat(a_ff(29,0),0.U(3.W)),
@ -674,9 +666,8 @@ class exu_div_new_3bit_fullshortq extends Module with RequireAsyncReset with lib
!b_twos_comp -> Cat(io.signed_in & io.divisor_in(31),io.divisor_in(31,0)),
b_twos_comp -> Cat(!divisor_sign_ff,twos_comp_out(31,0))
))
val r_in = Mux1H (Seq(
r_sign_sel -> "h1ffffffff".U(33.W),
r_sign_sel -> Fill(33,1.U),
r_restore_sel -> Cat(r_ff(29,0),a_ff(32,30)),
r_adder1_sel -> adder1_out(32,0),
r_adder2_sel -> adder2_out(32,0),
@ -732,6 +723,7 @@ class exu_div_new_3bit_fullshortq extends Module with RequireAsyncReset with lib
val dw_b_enc1 = b_enc.io.cls
val dw_a_enc = Cat (0.U, dw_a_enc1)
val dw_b_enc = Cat (0.U, dw_b_enc1)
val dw_shortq_raw = Cat(0.U,dw_b_enc) - Cat(0.U,dw_a_enc) + 1.U(7.W)
val shortq = Mux(dw_shortq_raw(6).asBool(),0.U,dw_shortq_raw(5,0))
shortq_enable := valid_ff & !shortq(5) & !(shortq(4,2) === "b111".U) & !io.cancel