colin
/
quasar
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

vwayhit corrected

This commit is contained in:
​Laraib Khan 2021-01-22 15:59:15 +05:00
parent ef2f0bbbb2
commit a25ee3cf0e
7 changed files with 2712 additions and 2276 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

111
ifu_bp_ctl.anno.json
View File

@ -1,13 +1,4 @@
[ [
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_hit_taken_f",
"sources":[
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_bpred_disable",
"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_req_f",
"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f"
]
},
{ {
"class":"firrtl.transforms.CombinationalPath", "class":"firrtl.transforms.CombinationalPath",
"sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_hist1_f", "sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_hist1_f",
@ -15,13 +6,6 @@
"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f" "~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f"
] ]
}, },
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_valid_f",
"sources":[
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_bpred_disable"
]
},
{ {
"class":"firrtl.transforms.CombinationalPath", "class":"firrtl.transforms.CombinationalPath",
"sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_inst_mask_f", "sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_inst_mask_f",
@ -29,7 +13,13 @@
"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_hit_taken_f", "~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_hit_taken_f",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_bpred_disable", "~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_bpred_disable",
"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_req_f", "~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_req_f",
"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f" "~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_flush_leak_one_wb",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_way",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
"~ifu_bp_ctl|ifu_bp_ctl>io_exu_bp_exu_i0_br_index_r"
] ]
}, },
{ {
@ -39,13 +29,6 @@
"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f" "~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f"
] ]
}, },
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_poffset_f",
"sources":[
"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f"
]
},
{ {
"class":"firrtl.transforms.CombinationalPath", "class":"firrtl.transforms.CombinationalPath",
"sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_btb_target_f", "sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_btb_target_f",
@ -53,7 +36,56 @@
"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_hit_taken_f", "~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_hit_taken_f",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_bpred_disable", "~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_bpred_disable",
"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_req_f", "~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_req_f",
"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f" "~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_flush_leak_one_wb",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_way",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
"~ifu_bp_ctl|ifu_bp_ctl>io_exu_bp_exu_i0_br_index_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_pc4_f",
"sources":[
"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f",
"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_req_f",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_flush_leak_one_wb",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_way",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
"~ifu_bp_ctl|ifu_bp_ctl>io_exu_bp_exu_i0_br_index_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_valid_f",
"sources":[
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_bpred_disable",
"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f",
"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_req_f",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_flush_leak_one_wb",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_way",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
"~ifu_bp_ctl|ifu_bp_ctl>io_exu_bp_exu_i0_br_index_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_ret_f",
"sources":[
"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f",
"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_req_f",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_flush_leak_one_wb",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_way",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
"~ifu_bp_ctl|ifu_bp_ctl>io_exu_bp_exu_i0_br_index_r"
] ]
}, },
{ {
@ -73,6 +105,35 @@
"~ifu_bp_ctl|ifu_bp_ctl>io_exu_bp_exu_i0_br_index_r" "~ifu_bp_ctl|ifu_bp_ctl>io_exu_bp_exu_i0_br_index_r"
] ]
}, },
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_poffset_f",
"sources":[
"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f",
"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_req_f",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_flush_leak_one_wb",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_way",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
"~ifu_bp_ctl|ifu_bp_ctl>io_exu_bp_exu_i0_br_index_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_hit_taken_f",
"sources":[
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_bpred_disable",
"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_req_f",
"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_flush_leak_one_wb",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_way",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
"~ifu_bp_ctl|ifu_bp_ctl>io_exu_bp_exu_i0_br_index_r"
]
},
{ {
"class":"firrtl.EmitCircuitAnnotation", "class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter" "emitter":"firrtl.VerilogEmitter"

3447
ifu_bp_ctl.fir
View File

File diff suppressed because it is too large Load Diff

1421
ifu_bp_ctl.v
View File

File diff suppressed because it is too large Load Diff

9
src/main/scala/ifu/ifu_bp_ctl.scala
View File

@ -370,9 +370,7 @@ if(!BTB_FULLYA) {
val rets_out = Wire(Vec(RET_STACK_SIZE, UInt(32.W))) val rets_out = Wire(Vec(RET_STACK_SIZE, UInt(32.W)))
rets_out := (0 until RET_STACK_SIZE).map(i=>0.U) rets_out := (0 until RET_STACK_SIZE).map(i=>0.U)
// Final target if its a RET then pop else take the target pc // Final target if its a RET then pop else take the target pc
io.ifu_bp_btb_target_f := ((Fill(31,(btb_rd_ret_f & !btb_rd_call_f & rets_out(0)(0) & io.ifu_bp_hit_taken_f)) & rets_out(0)(31,1)) |
// mux in the return stack address here for a predicted return assuming the RS is valid, quite if no prediction
io.ifu_bp_btb_target_f := ((Fill(31,(btb_rd_ret_f & !btb_rd_call_f & rets_out(0)(0) & io.ifu_bp_hit_taken_f)) & rets_out(0)(31,1)) |
(Fill(31,(!btb_rd_ret_f & !btb_rd_call_f & rets_out(0)(0) & io.ifu_bp_hit_taken_f)) & bp_btb_target_adder_f(31,1))) (Fill(31,(!btb_rd_ret_f & !btb_rd_call_f & rets_out(0)(0) & io.ifu_bp_hit_taken_f)) & bp_btb_target_adder_f(31,1)))
// Return stack // Return stack
@ -439,11 +437,10 @@ if(!BTB_FULLYA) {
// Writing is always done from dec or exu check if the dec have a valid data // Writing is always done from dec or exu check if the dec have a valid data
val btb_wr_addr = Mux(dec_tlu_error_wb.asBool, btb_error_addr_wb, exu_mp_addr) val btb_wr_addr = Mux(dec_tlu_error_wb.asBool, btb_error_addr_wb, exu_mp_addr)
val vwayhit_f = Mux1H(Seq(!io.ifc_fetch_addr_f(0).asBool->wayhit_f, vwayhit_f := Mux1H(Seq(!io.ifc_fetch_addr_f(0).asBool->wayhit_f,
io.ifc_fetch_addr_f(0).asBool->Cat(wayhit_p1_f(0), wayhit_f(1)))) & Cat(eoc_mask, 1.U(1.W)) io.ifc_fetch_addr_f(0).asBool->Cat(wayhit_p1_f(0), wayhit_f(1)))) & Cat(eoc_mask, 1.U(1.W))
// vwayhit_f := (Fill(2,io.ifc_fetch_addr_f(0)) & wayhit_f(1,0)) | ((Fill(2,io.ifc_fetch_addr_f(1)) & Cat(wayhit_p1_f(0),wayhit_f(1))) & Cat(eoc_mask,1.U))
// vwayhit_f := (Fill(2,io.ifc_fetch_addr_f(0)) & wayhit_f(1,0)) | ((Fill(2,io.ifc_fetch_addr_f(1)) & Cat(wayhit_p1_f(0),wayhit_f(1))) & Cat(eoc_mask,1.U))
val btb_bank0_rd_data_way0_out = (0 until LRU_SIZE).map(i => rvdffe(btb_wr_data, ((btb_wr_addr === i.U) & btb_wr_en_way0).asBool, clock, io.scan_mode)) val btb_bank0_rd_data_way0_out = (0 until LRU_SIZE).map(i => rvdffe(btb_wr_data, ((btb_wr_addr === i.U) & btb_wr_en_way0).asBool, clock, io.scan_mode))
val btb_bank0_rd_data_way1_out = (0 until LRU_SIZE).map(i => rvdffe(btb_wr_data, ((btb_wr_addr === i.U) & btb_wr_en_way1).asBool, clock, io.scan_mode)) val btb_bank0_rd_data_way1_out = (0 until LRU_SIZE).map(i => rvdffe(btb_wr_data, ((btb_wr_addr === i.U) & btb_wr_en_way1).asBool, clock, io.scan_mode))

BIN
target/scala-2.12/classes/ifu/bp_MAIN$.class
View File

Binary file not shown.

BIN
target/scala-2.12/classes/ifu/bp_MAIN$delayedInit$body.class
View File

Binary file not shown.

BIN
target/scala-2.12/classes/ifu/ifu_bp_ctl.class
View File

Binary file not shown.