vwayhit corrected
This commit is contained in:
Laraib Khan
parent
ef2f0bbbb2
commit
a25ee3cf0e
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@ -1,13 +1,4 @@
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[
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_hit_taken_f",
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"sources":[
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_bpred_disable",
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"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_req_f",
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"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_hist1_f",
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@ -15,13 +6,6 @@
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"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_valid_f",
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"sources":[
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_bpred_disable"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_inst_mask_f",
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@ -29,7 +13,13 @@
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"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_hit_taken_f",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_bpred_disable",
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"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_req_f",
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"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f"
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"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_flush_leak_one_wb",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_way",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
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"~ifu_bp_ctl|ifu_bp_ctl>io_exu_bp_exu_i0_br_index_r"
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]
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},
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{
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@ -39,13 +29,6 @@
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"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_poffset_f",
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"sources":[
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"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_btb_target_f",
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@ -53,7 +36,56 @@
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"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_hit_taken_f",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_bpred_disable",
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"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_req_f",
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"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f"
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"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_flush_leak_one_wb",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_way",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
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"~ifu_bp_ctl|ifu_bp_ctl>io_exu_bp_exu_i0_br_index_r"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_pc4_f",
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"sources":[
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"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f",
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"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_req_f",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_flush_leak_one_wb",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_way",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
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"~ifu_bp_ctl|ifu_bp_ctl>io_exu_bp_exu_i0_br_index_r"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_valid_f",
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"sources":[
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_bpred_disable",
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"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f",
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"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_req_f",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_flush_leak_one_wb",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_way",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
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"~ifu_bp_ctl|ifu_bp_ctl>io_exu_bp_exu_i0_br_index_r"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_ret_f",
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"sources":[
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"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f",
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"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_req_f",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_flush_leak_one_wb",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_way",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
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"~ifu_bp_ctl|ifu_bp_ctl>io_exu_bp_exu_i0_br_index_r"
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]
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},
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{
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@ -73,6 +105,35 @@
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"~ifu_bp_ctl|ifu_bp_ctl>io_exu_bp_exu_i0_br_index_r"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_poffset_f",
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"sources":[
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"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f",
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"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_req_f",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_flush_leak_one_wb",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_way",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
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"~ifu_bp_ctl|ifu_bp_ctl>io_exu_bp_exu_i0_br_index_r"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_hit_taken_f",
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"sources":[
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_bpred_disable",
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"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_req_f",
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"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_flush_leak_one_wb",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_way",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
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"~ifu_bp_ctl|ifu_bp_ctl>io_exu_bp_exu_i0_br_index_r"
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]
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},
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{
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"class":"firrtl.EmitCircuitAnnotation",
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"emitter":"firrtl.VerilogEmitter"
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3447
ifu_bp_ctl.fir
3447
ifu_bp_ctl.fir
File diff suppressed because it is too large
Load Diff
1421
ifu_bp_ctl.v
1421
ifu_bp_ctl.v
File diff suppressed because it is too large
Load Diff
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@ -370,8 +370,6 @@ if(!BTB_FULLYA) {
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val rets_out = Wire(Vec(RET_STACK_SIZE, UInt(32.W)))
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rets_out := (0 until RET_STACK_SIZE).map(i=>0.U)
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// Final target if its a RET then pop else take the target pc
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// mux in the return stack address here for a predicted return assuming the RS is valid, quite if no prediction
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io.ifu_bp_btb_target_f := ((Fill(31,(btb_rd_ret_f & !btb_rd_call_f & rets_out(0)(0) & io.ifu_bp_hit_taken_f)) & rets_out(0)(31,1)) |
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(Fill(31,(!btb_rd_ret_f & !btb_rd_call_f & rets_out(0)(0) & io.ifu_bp_hit_taken_f)) & bp_btb_target_adder_f(31,1)))
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@ -439,10 +437,9 @@ if(!BTB_FULLYA) {
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// Writing is always done from dec or exu check if the dec have a valid data
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val btb_wr_addr = Mux(dec_tlu_error_wb.asBool, btb_error_addr_wb, exu_mp_addr)
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val vwayhit_f = Mux1H(Seq(!io.ifc_fetch_addr_f(0).asBool->wayhit_f,
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vwayhit_f := Mux1H(Seq(!io.ifc_fetch_addr_f(0).asBool->wayhit_f,
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io.ifc_fetch_addr_f(0).asBool->Cat(wayhit_p1_f(0), wayhit_f(1)))) & Cat(eoc_mask, 1.U(1.W))
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// vwayhit_f := (Fill(2,io.ifc_fetch_addr_f(0)) & wayhit_f(1,0)) | ((Fill(2,io.ifc_fetch_addr_f(1)) & Cat(wayhit_p1_f(0),wayhit_f(1))) & Cat(eoc_mask,1.U))
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val btb_bank0_rd_data_way0_out = (0 until LRU_SIZE).map(i => rvdffe(btb_wr_data, ((btb_wr_addr === i.U) & btb_wr_en_way0).asBool, clock, io.scan_mode))
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