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QUASAR 2.0 Final

This commit is contained in:
​Laraib Khan 2021-04-09 14:27:44 +05:00
parent 0e91028b8d
commit a263903e7e
13 changed files with 147 additions and 361 deletions
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5
design/src/main/scala/dec/dec.scala
View File

@ -121,7 +121,10 @@ class dec extends Module with param with RequireAsyncReset{
val dec_tlu_mtval_wb1 = WireInit(UInt(32.W),0.U)
val dec_tlu_i0_exc_valid_wb1 = WireInit(Bool(),0.B)
val dec_tlu_trace_disable = WireInit(Bool(),0.B)
// val dec_i0_bp_fa_index = WireInit(UInt(log2Ceil(BTB_SIZE).W),0.U)
//val dec_debug_valid_d = WireInit(Bool(),0.B)
//--------------------------------------------------------------------------//
val instbuff = Module(new dec_ib_ctl)

120
design/src/main/scala/dec/dec_tlu_ctl.scala
View File

@ -45,7 +45,6 @@ trait CSR_VAL {
class dec_tlu_ctl_IO extends Bundle with lib {
val tlu_exu = Flipped(new tlu_exu)
val tlu_dma = new tlu_dma
// val active_clk = Input(Clock())
val free_clk = Input(Clock())
val free_l2clk = Input(Clock())
val scan_mode = Input(Bool())
@ -96,10 +95,6 @@ class dec_tlu_ctl_IO extends Bundle with lib {
val dbg_resume_req = Input(UInt(1.W)) // DM requests a resume
val dec_div_active = Input(UInt(1.W)) // oop div is active
val trigger_pkt_any = Output(Vec(4,new trigger_pkt_t))// trigger info for trigger blocks
// val pic_claimid = Input(UInt(8.W)) // pic claimid for csr
// val pic_pl = Input(UInt(4.W)) // pic priv level for csr
// val mhwakeup = Input(UInt(1.W)) // high priority external int, wakeup if halted
// val mexintpend= Input(UInt(1.W)) // external interrupt pending
val timer_int= Input(UInt(1.W)) // timer interrupt pending
val soft_int= Input(UInt(1.W)) // software interrupt pending
val o_cpu_halt_status = Output(UInt(1.W)) // PMU interface, halted
@ -114,8 +109,6 @@ class dec_tlu_ctl_IO extends Bundle with lib {
val mpc_debug_halt_ack = Output(UInt(1.W)) // Halt ack
val mpc_debug_run_ack = Output(UInt(1.W)) // Run ack
val debug_brkpt_status = Output(UInt(1.W)) // debug breakpoint
// val dec_tlu_meicurpl = Output(UInt(4.W)) // to PIC
// val dec_tlu_meipt = Output(UInt(4.W)) // to PIC
val dec_csr_rddata_d = Output(UInt(32.W)) // csr read data at wb
val dec_csr_legal_d = Output(UInt(1.W)) // csr indicates legal operation
val dec_tlu_i0_kill_writeb_wb = Output(UInt(1.W)) // I0 is flushed, don't writeback any results to arch state
@ -176,8 +169,6 @@ class dec_tlu_ctl extends Module with lib with RequireAsyncReset with CSR_VAL{
val take_ce_int =WireInit(UInt(1.W),0.U)
val take_ext_int_start =WireInit(UInt(1.W),0.U)
val ext_int_freeze =WireInit(UInt(1.W),0.U)
// val ext_int_freeze_d1 =WireInit(UInt(1.W),0.U)
// val take_ext_int_start_d1 =WireInit(UInt(1.W),0.U)
val take_ext_int_start_d2 =WireInit(UInt(1.W),0.U)
val take_ext_int_start_d3 =WireInit(UInt(1.W),0.U)
val fast_int_meicpct =WireInit(UInt(1.W),0.U)
@ -285,7 +276,6 @@ class dec_tlu_ctl extends Module with lib with RequireAsyncReset with CSR_VAL{
int_timers.io.free_l2clk :=io.free_l2clk
int_timers.io.scan_mode :=io.scan_mode
int_timers.io.dec_csr_wen_r_mod :=dec_csr_wen_r_mod
// int_timers.io.dec_csr_rdaddr_d :=io.dec_csr_rdaddr_d
int_timers.io.dec_csr_wraddr_r :=io.dec_csr_wraddr_r
int_timers.io.dec_csr_wrdata_r :=io.dec_csr_wrdata_r
int_timers.io.csr_mitctl0 :=csr_pkt.csr_mitctl0
@ -319,8 +309,7 @@ class dec_tlu_ctl extends Module with lib with RequireAsyncReset with CSR_VAL{
// for CSRs that have inpipe writes only
val csr_wr_clk=rvoclkhdr(clock,(dec_csr_wen_r_mod | clk_override).asBool,io.scan_mode)
int_timers.io.csr_wr_clk := csr_wr_clk
// val lsu_r_wb_clk=rvclkhdr(clock,(io.lsu_error_pkt_r.valid | lsu_exc_valid_r_d1 | clk_override).asBool,io.scan_mode)
val e4_valid = io.dec_tlu_i0_valid_r
val e4e5_valid = e4_valid | e5_valid
val flush_clkvalid = internal_dbg_halt_mode_f | i_cpu_run_req_d1 | interrupt_valid_r | interrupt_valid_r_d1 | reset_delayed | pause_expired_r | pause_expired_wb | ic_perr_r | iccm_sbecc_r | clk_override
@ -333,8 +322,6 @@ class dec_tlu_ctl extends Module with lib with RequireAsyncReset with CSR_VAL{
val ifu_iccm_rd_ecc_single_err_f =rvdffie(io.tlu_mem.ifu_iccm_rd_ecc_single_err,io.free_l2clk, reset.asAsyncReset(), io.scan_mode)
val iccm_repair_state_d1 =rvdffie(iccm_repair_state_ns,io.free_l2clk, reset.asAsyncReset(), io.scan_mode)
// ic_perr_r_d1 :=withClock(io.free_clk){RegNext(ic_perr_r,0.U)}
// iccm_sbecc_r_d1 :=withClock(io.free_clk){RegNext(iccm_sbecc_r,0.U)}
e5_valid :=rvdffie(e4_valid,io.free_l2clk, reset.asAsyncReset(), io.scan_mode)
internal_dbg_halt_mode_f :=rvdffie(internal_dbg_halt_mode,io.free_l2clk, reset.asAsyncReset(), io.scan_mode)
val lsu_pmu_load_external_r =rvdffie(io.lsu_tlu.lsu_pmu_load_external_m,io.free_l2clk, reset.asAsyncReset(), io.scan_mode)
@ -790,9 +777,6 @@ class dec_tlu_ctl extends Module with lib with RequireAsyncReset with CSR_VAL{
int_exc.io.take_ext_int_start_d1 := csr.io.take_ext_int_start_d1
int_exc.io.take_ext_int_start_d2 := csr.io.take_ext_int_start_d2
int_exc.io.take_ext_int_start_d3 := csr.io.take_ext_int_start_d3
// take_ext_int_start_d1 := csr.io.take_ext_int_start_d1
// take_ext_int_start_d2 := csr.io.take_ext_int_start_d2
// take_ext_int_start_d3 := csr.io.take_ext_int_start_d3
ext_int_freeze := int_exc.io.ext_int_freeze
take_ext_int := int_exc.io.take_ext_int
fast_int_meicpct := int_exc.io.fast_int_meicpct
@ -965,10 +949,8 @@ class dec_tlu_ctl extends Module with lib with RequireAsyncReset with CSR_VAL{
mdseac_locked_f := csr.io.mdseac_locked_f
csr.io.nmi_int_detected_f := nmi_int_detected_f
csr.io.internal_dbg_halt_mode_f2 := internal_dbg_halt_mode_f2
// ext_int_freeze_d1 := csr.io.ext_int_freeze_d1
csr.io.ic_perr_r := ic_perr_r
csr.io.iccm_sbecc_r := iccm_sbecc_r
// csr.io.lsu_single_ecc_error_r_d1 := lsu_single_ecc_error_r_d1
csr.io.ifu_miss_state_idle_f := ifu_miss_state_idle_f
csr.io.lsu_idle_any_f := lsu_idle_any_f
csr.io.dbg_tlu_halted_f := dbg_tlu_halted_f
@ -1179,7 +1161,6 @@ trait CSRs{
class CSR_IO extends Bundle with lib {
val free_l2clk = Input(Clock())
val free_clk = Input(Clock())
// val active_clk = Input(Clock())
val scan_mode = Input(Bool())
val dec_csr_wrdata_r = Input(UInt(32.W))
val dec_csr_wraddr_r = Input(UInt(12.W))
@ -1209,8 +1190,6 @@ class CSR_IO extends Bundle with lib {
val dec_tlu_i0_exc_valid_wb1 = Output(UInt(1.W))
val dec_tlu_i0_valid_wb1 = Output(UInt(1.W))
val dec_csr_wen_r = Input(UInt(1.W))
//val dec_tlu_force_halt = Output(UInt(1.W))
//val dec_tlu_flush_extint = Output(UInt(1.W))
val dec_tlu_mtval_wb1 = Output(UInt(32.W))
val dec_tlu_exc_cause_wb1 = Output(UInt(5.W))
val dec_tlu_perfcnt0 = Output(UInt(1.W))
@ -1236,17 +1215,7 @@ class CSR_IO extends Bundle with lib {
val dec_tlu_pic_clk_override = Output(UInt(1.W))
val dec_tlu_dccm_clk_override = Output(UInt(1.W))
val dec_tlu_icm_clk_override = Output(UInt(1.W))
//val dec_csr_legal_d = Output(UInt(1.W))
val dec_csr_rddata_d = Output(UInt(32.W))
//val dec_tlu_postsync_d = Output(UInt(1.W))
//val dec_tlu_presync_d = Output(UInt(1.W))
//val dec_tlu_flush_pause_r = Output(UInt(1.W))
//val dec_tlu_flush_lower_r = Output(UInt(1.W))
//val dec_tlu_i0_kill_writeb_r = Output(UInt(1.W))
//val dec_tlu_flush_lower_wb = Output(UInt(1.W))
//val dec_tlu_i0_kill_writeb_wb = Output(UInt(1.W))
// val dec_tlu_flush_leak_one_wb = Output(UInt(1.W))
//val dec_tlu_debug_stall = Output(UInt(1.W))
val dec_tlu_pipelining_disable = Output(UInt(1.W))
val dec_tlu_wr_pause_r = Output(UInt(1.W))
val ifu_pmu_bus_busy = Input(UInt(1.W))
@ -1388,35 +1357,24 @@ class csr_tlu extends Module with lib with CSRs with RequireAsyncReset {
val io = IO(new CSR_IO)
////////////////////////////////wires///////////////////////////////
// val lsu_single_ecc_error_r_d1 = WireInit(UInt(1.W),0.U)
// val lsu_i0_exc_r_d1 = WireInit(UInt(1.W),0.U)
val miccme_ce_req = WireInit(UInt(1.W),0.U)
val mice_ce_req = WireInit(UInt(1.W),0.U)
val mdccme_ce_req = WireInit(UInt(1.W),0.U)
val pc_r_d1 = WireInit(UInt(31.W),0.U)
val mpmc_b_ns = WireInit(UInt(1.W),0.U)
val mpmc_b = WireInit(UInt(1.W),0.U)
// val wr_mcycleh_r = WireInit(UInt(1.W), 0.U)
val mcycleh = WireInit(UInt(32.W),0.U)
// val minstretl_inc = WireInit(UInt(33.W),0.U)
val wr_minstreth_r = WireInit(UInt(1.W),0.U)
val minstretl = WireInit(UInt(32.W),0.U)
// val minstreth_inc = WireInit(UInt(32.W),0.U)
val minstreth = WireInit(UInt(32.W),0.U)
val mfdc_ns = WireInit(UInt(16.W),0.U)
val mfdc_int = WireInit(UInt(16.W),0.U)
// val mhpmc6_incr = WireInit(UInt(64.W),0.U)
// val mhpmc5_incr = WireInit(UInt(64.W),0.U)
// val mhpmc4_incr = WireInit(UInt(64.W),0.U)
// val perfcnt_halted = WireInit(UInt(1.W),0.U)
// val mhpmc3_incr = WireInit(UInt(64.W),0.U)
val mhpme_vec = Wire(Vec(4,UInt(10.W)))
val mtdata2_t = Wire(Vec(4,UInt(32.W)))
val wr_meicpct_r = WireInit(UInt(1.W),0.U)
val force_halt_ctr_f = WireInit(UInt(32.W),0.U)
val mdccmect_inc = WireInit(UInt(27.W),0.U)
val miccmect_inc = WireInit(UInt(27.W),0.U)
// val fw_halted = WireInit(UInt(1.W),0.U)
val micect_inc = WireInit(UInt(27.W),0.U)
val mdseac_en = WireInit(UInt(1.W),0.U)
val mie = WireInit(UInt(6.W),0.U)
@ -1426,25 +1384,12 @@ class csr_tlu extends Module with lib with CSRs with RequireAsyncReset {
val mscause = WireInit(UInt(4.W),0.U)
val mtval = WireInit(UInt(32.W),0.U)
val meicurpl = WireInit(UInt(4.W),0.U)
// val meicidpl = WireInit(UInt(4.W),0.U)
val meipt = WireInit(UInt(4.W),0.U)
val mfdc = WireInit(UInt(19.W),0.U)
val mtsel = WireInit(UInt(2.W),0.U)
val micect = WireInit(UInt(32.W),0.U)
val miccmect = WireInit(UInt(32.W),0.U)
val mdccmect = WireInit(UInt(32.W),0.U)
// val mhpmc3h = WireInit(UInt(32.W),0.U)
// val mhpmc3 = WireInit(UInt(32.W),0.U)
// val mhpmc4h = WireInit(UInt(32.W),0.U)
// val mhpmc4 = WireInit(UInt(32.W),0.U)
// val mhpmc5h = WireInit(UInt(32.W),0.U)
// val mhpmc5 = WireInit(UInt(32.W),0.U)
// val mhpmc6h = WireInit(UInt(32.W),0.U)
// val mhpmc6 = WireInit(UInt(32.W),0.U)
// val mhpme3 = WireInit(UInt(10.W),0.U)
// val mhpme4 = WireInit(UInt(10.W),0.U)
// val mhpme5 = WireInit(UInt(10.W),0.U)
// val mhpme6 = WireInit(UInt(10.W),0.U)
val mfdht = WireInit(UInt(6.W),0.U)
val mfdhs = WireInit(UInt(2.W),0.U)
val mcountinhibit = WireInit(UInt(7.W),0.U)
@ -1487,9 +1432,7 @@ class csr_tlu extends Module with lib with CSRs with RequireAsyncReset {
// gate MIE if we are single stepping and DCSR[STEPIE] is off
io.mstatus_mie_ns := io.mstatus(MSTATUS_MIE) & (~io.dcsr_single_step_running_f | io.dcsr(DCSR_STEPIE))
// io.mstatus := withClock(io.free_clk) {
// RegNext(mstatus_ns,0.U)
// }
// ----------------------------------------------------------------------
// MTVEC (RW)
@ -1514,9 +1457,7 @@ class csr_tlu extends Module with lib with CSRs with RequireAsyncReset {
val ce_int = (mdccme_ce_req | miccme_ce_req | mice_ce_req)
val mip_ns = Cat(ce_int, io.dec_timer_t0_pulse, io.dec_timer_t1_pulse, io.mexintpend, io.timer_int_sync, io.soft_int_sync)
// io.mip := withClock(io.free_clk) {
// RegNext(mip_ns,0.U)
// }
// ----------------------------------------------------------------------
// MIE (RW)
@ -1541,8 +1482,6 @@ class csr_tlu extends Module with lib with CSRs with RequireAsyncReset {
val wr_mcyclel_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MCYCLEL)
val mcyclel_cout_in = ~(kill_ebreak_count_r | (io.dec_tlu_dbg_halted & io.dcsr(DCSR_STOPC)) | io.dec_tlu_pmu_fw_halted | mcountinhibit(0))
// val mcyclel_cout_f = WireInit(Bool())
// val mcyclel_inc = WireInit(UInt(32.W),0.U)
val mcyclel_inc1 = WireInit(UInt(9.W),0.U)
val mcyclel_inc2 = WireInit(UInt(25.W),0.U)
mcyclel_inc1 := mcyclel(7,0) +& Cat(0.U(7.W), 1.U(1.W))
@ -1551,7 +1490,6 @@ class csr_tlu extends Module with lib with CSRs with RequireAsyncReset {
val mcyclel_ns = Mux(wr_mcyclel_r.asBool, io.dec_csr_wrdata_r, mcyclel_inc(31,0))
val mcyclel_cout = mcyclel_inc2(24).asBool
mcyclel := Cat(rvdffe(mcyclel_ns(31,8), (wr_mcyclel_r | (mcyclel_inc1(8) & mcyclel_cout_in.asUInt).asBool), io.free_l2clk, io.scan_mode),rvdffe(mcyclel_ns(7,0),( wr_mcyclel_r | mcyclel_cout_in.asUInt).asBool, io.free_l2clk, io.scan_mode))
// val mcyclel_cout_f = withClock(io.free_clk) {RegNext((mcyclel_cout & !wr_mcycleh_r),0.U)}
// ----------------------------------------------------------------------
// MCYCLEH (RW)
// [63:32] : Higher Cycle count
@ -1579,7 +1517,6 @@ class csr_tlu extends Module with lib with CSRs with RequireAsyncReset {
val i0_valid_no_ebreak_ecall_r = (io.dec_tlu_i0_valid_r & !(io.ebreak_r | io.ecall_r | io.ebreak_to_debug_mode_r | io.illegal_r | mcountinhibit(2))).asBool()
val wr_minstretl_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MINSTRETL)
// val minstretl_inc = WireInit(UInt(32.W))
val minstretl_inc1 = WireInit(UInt(9.W),0.U)
val minstretl_inc2 = WireInit(UInt(25.W),0.U)
minstretl_inc1 := minstretl(7,0) +& Cat(0.U(7.W), 1.U(1.W))
@ -1593,9 +1530,7 @@ class csr_tlu extends Module with lib with CSRs with RequireAsyncReset {
val minstretl_ns = Mux(wr_minstretl_r.asBool, io.dec_csr_wrdata_r , minstretl_inc(31,0))
minstretl := Cat(rvdffe(minstretl_ns(31,8),wr_minstretl_r | (minstretl_inc1(8) & minstret_enable),clock,io.scan_mode),rvdffe(minstretl_ns(7,0),minstret_enable.asBool,clock,io.scan_mode))
// val minstret_enable_f = withClock(io.free_clk){RegNext(minstret_enable,0.U)}
// val minstretl_cout_f = withClock(io.free_clk){RegNext((minstretl_cout & ~wr_minstreth_r),0.U)}
val minstretl_read = minstretl
// ----------------------------------------------------------------------
// MINSTRETH (RW)
@ -1604,8 +1539,6 @@ class csr_tlu extends Module with lib with CSRs with RequireAsyncReset {
wr_minstreth_r := (io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MINSTRETH)).asBool
//val minstret_enable_f = WireInit(Bool())
// val minstretl_cout_f = WireInit(Bool())
val minstreth_inc = minstreth + Cat(0.U(31.W), perfmux_flop.io.minstretl_cout_f )
val minstreth_ns = Mux(wr_minstreth_r.asBool, io.dec_csr_wrdata_r, minstreth_inc)
@ -1787,8 +1720,7 @@ class csr_tlu extends Module with lib with CSRs with RequireAsyncReset {
mfdc_int := rvdffe(mfdc_ns,wr_mfdc_r.asBool,clock,io.scan_mode)
// rvdffe #(15) mfdc_ff (.*, .en(wr_mfdc_r), .din({mfdc_ns[14:0]}), .dout(mfdc_int[14:0]));
// flip poweron value of bit 6 for AXI build
if(BUILD_AXI4){
// flip poweron valid of bit 12
@ -2205,8 +2137,6 @@ class csr_tlu extends Module with lib with CSRs with RequireAsyncReset {
val icache_rd_valid = io.allow_dbg_halt_csr_write & io.dec_csr_any_unq_d & io.dec_i0_decode_d & ~io.dec_csr_wen_unq_d & (io.dec_csr_rdaddr_d(11,0) === DICAGO)
val icache_wr_valid = io.allow_dbg_halt_csr_write & io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === DICAGO)
// val icache_rd_valid_f = WireInit(UInt(1.W),0.U)
// val icache_wr_valid_f = WireInit(UInt(1.W),0.U)
io.dec_tlu_ic_diag_pkt.icache_rd_valid := perfmux_flop.io.icache_rd_valid_f
io.dec_tlu_ic_diag_pkt.icache_wr_valid := perfmux_flop.io.icache_wr_valid_f
@ -2317,7 +2247,6 @@ class csr_tlu extends Module with lib with CSRs with RequireAsyncReset {
// Generate the muxed incs for all counters based on event type
// val mhpmc_inc_r =perfmux_flop.io.mhpmc_inc_r //mux out
perfmux_flop.io.mcountinhibit := mcountinhibit
perfmux_flop.io.mhpme_vec := mhpme_vec
perfmux_flop.io.ifu_pmu_ic_hit := io.ifu_pmu_ic_hit
@ -2366,19 +2295,8 @@ class csr_tlu extends Module with lib with CSRs with RequireAsyncReset {
perfmux_flop.io.rfpc_i0_r := io.rfpc_i0_r
perfmux_flop.io.dec_tlu_br0_start_error_r := io.dec_tlu_br0_start_error_r
//flop outputs
// mcyclel_cout_f := perfmux_flop.io.mcyclel_cout_f
// minstret_enable_f := perfmux_flop.io.minstret_enable_f
// minstretl_cout_f := perfmux_flop.io.minstretl_cout_f
// fw_halted := perfmux_flop.io.fw_halted
// meicidpl := perfmux_flop.io.meicidpl
// icache_rd_valid_f := perfmux_flop.io.icache_rd_valid_f
// icache_wr_valid_f := perfmux_flop.io.icache_wr_valid_f
// val mhpmc_inc_r_d1 = perfmux_flop.io.mhpmc_inc_r_d1
// val perfcnt_halted_d1 = perfmux_flop.io.perfcnt_halted_d1
io.mdseac_locked_f := perfmux_flop.io.mdseac_locked_f
// lsu_single_ecc_error_r_d1 := perfmux_flop.io.lsu_single_ecc_error_r_d1
io.lsu_exc_valid_r_d1 := perfmux_flop.io.lsu_exc_valid_r_d1
// lsu_i0_exc_r_d1 := perfmux_flop.io.lsu_i0_exc_r_d1
io.take_ext_int_start_d1 := perfmux_flop.io.take_ext_int_start_d1
io.take_ext_int_start_d2 := perfmux_flop.io.take_ext_int_start_d2
io.take_ext_int_start_d3 := perfmux_flop.io.take_ext_int_start_d3
@ -2421,18 +2339,6 @@ class csr_tlu extends Module with lib with CSRs with RequireAsyncReset {
perf_csrs.io.mhpmc_inc_r_d1 := perfmux_flop.io.mhpmc_inc_r_d1
perf_csrs.io.perfcnt_halted_d1 := perfmux_flop.io.perfcnt_halted_d1
//Outputs
// mhpmc3h := perf_csrs.io.mhpmc3h
// mhpmc3 := perf_csrs.io.mhpmc3
// mhpmc4h := perf_csrs.io.mhpmc4h
// mhpmc4 := perf_csrs.io.mhpmc4
// mhpmc5h := perf_csrs.io.mhpmc5h
// mhpmc5 := perf_csrs.io.mhpmc5
// mhpmc6h := perf_csrs.io.mhpmc6h
// mhpmc6 := perf_csrs.io.mhpmc6
// mhpme3 := perf_csrs.io.mhpme3
// mhpme4 := perf_csrs.io.mhpme4
// mhpme5 := perf_csrs.io.mhpme5
// mhpme6 := perf_csrs.io.mhpme6
io.dec_tlu_perfcnt0 := perf_csrs.io.dec_tlu_perfcnt0
io.dec_tlu_perfcnt1 := perf_csrs.io.dec_tlu_perfcnt1
io.dec_tlu_perfcnt2 := perf_csrs.io.dec_tlu_perfcnt2
@ -2783,7 +2689,6 @@ class perf_mux_and_flops extends Module with CSRs with lib with RequireAsyncRese
val meicidpl_ns = Input(UInt(4.W))
val icache_rd_valid = Input(Bool())
val icache_wr_valid = Input(Bool())
// val mhpmc_inc_r = Input(Bool())
val perfcnt_halted = Input(Bool())
val mstatus_ns = Input(UInt(2.W))
val scan_mode = Input(Bool())
@ -3086,10 +2991,6 @@ class int_exc extends Module with CSRs with lib with RequireAsyncReset{
if(FAST_INTERRUPT_REDIRECT) {
// take_ext_int_start_d1:=withClock(io.free_clk){RegNext(take_ext_int_start,0.U)}
// take_ext_int_start_d2:=withClock(io.free_clk){RegNext(take_ext_int_start_d1,0.U)}
// take_ext_int_start_d3:=withClock(io.free_clk){RegNext(take_ext_int_start_d2,0.U)}
// ext_int_freeze_d1 :=withClock(io.free_clk){RegNext(ext_int_freeze,0.U)}
io.take_ext_int_start := io.ext_int_ready & ~block_interrupts;
io.ext_int_freeze := io.take_ext_int_start | io.take_ext_int_start_d1 | io.take_ext_int_start_d2 | io.take_ext_int_start_d3
io.take_ext_int := io.take_ext_int_start_d3 & ~io.lsu_fir_error.orR
@ -3098,10 +2999,6 @@ class int_exc extends Module with CSRs with lib with RequireAsyncReset{
}else{
io.take_ext_int_start := 0.U(1.W)
io.ext_int_freeze := 0.U(1.W)
// io.ext_int_freeze_d1 := 0.U(1.W)
// io.take_ext_int_start_d1 := 0.U(1.W)
// io.take_ext_int_start_d2 := 0.U(1.W)
// io.take_ext_int_start_d3 := 0.U(1.W)
io.fast_int_meicpct := 0.U(1.W)
io.ignore_ext_int_due_to_lsu_stall := 0.U(1.W)
io.take_ext_int := io.ext_int_ready & ~block_interrupts
@ -3144,11 +3041,9 @@ class int_exc extends Module with CSRs with lib with RequireAsyncReset{
io.tlu_flush_path_r_d1:=rvdffpcie(tlu_flush_path_r,io.tlu_flush_lower_r,reset.asAsyncReset(),clock, io.scan_mode)//withClock(e4e5_int_clk){RegNext(tlu_flush_path_r,0.U)} ///After Combining Code revisit this
io.dec_tlu_flush_lower_wb := io.tlu_flush_lower_r_d1
// io.tlu_mem.dec_tlu_flush_lower_wb := io.dec_tlu_flush_lower_wb
io.dec_tlu_flush_lower_r := io.tlu_flush_lower_r
io.dec_tlu_flush_path_r := tlu_flush_path_r ///After Combining Code revisit this
// this is used to capture mepc, etc.
io.exc_or_int_valid_r := io.lsu_exc_valid_r | io.i0_exception_valid_r | io.interrupt_valid_r | (io.i0_trigger_hit_r & ~io.trigger_hit_dmode_r)
io.interrupt_valid_r_d1 :=rvdffie(io.interrupt_valid_r, clock,reset.asAsyncReset(),io.scan_mode)//withClock(e4e5_int_clk){RegNext(interrupt_valid_r,0.U)}
@ -3225,9 +3120,7 @@ class dec_decode_csr_read extends Module with RequireAsyncReset{
io.csr_pkt.csr_mitcnt0 :=pattern(List(6,-5,4,-2,'z'))
io.csr_pkt.csr_mitcnt1 :=pattern(List(6,2,-1,0))
io.csr_pkt.csr_mpmc :=pattern(List(6,-4,-3,2,1))
// io.csr_pkt.csr_mcpc :=pattern(List(10,6,-4,-3,-2,1))
io.csr_pkt.csr_meicpct :=pattern(List(11,6,1,'z'))
// io.csr_pkt.csr_mdeau :=pattern(List(-10,7,6,-3))
io.csr_pkt.csr_micect :=pattern(List(6,5,-3,-1,'z'))
io.csr_pkt.csr_miccmect :=pattern(List(6,5,-3,0))
io.csr_pkt.csr_mdccmect :=pattern(List(6,5,1,'z'))
@ -3390,7 +3283,6 @@ class dec_timer_ctl_IO extends Bundle{
val csr_wr_clk = Input(Clock())
val scan_mode =Input(Bool())
val dec_csr_wen_r_mod =Input(UInt(1.W)) // csr write enable at wb
// val dec_csr_rdaddr_d =Input(UInt(12.W)) // read address for csr
val dec_csr_wraddr_r =Input(UInt(12.W)) // write address for csr
val dec_csr_wrdata_r =Input(UInt(32.W)) // csr write data at wb
@ -3413,4 +3305,4 @@ class dec_timer_ctl_IO extends Bundle{
}
object tlu extends App {
(new chisel3.stage.ChiselStage).emitVerilog(new dec_tlu_ctl())
}
}

29
design/src/main/scala/dma_ctrl.scala
View File

@ -2,7 +2,6 @@
import chisel3._
import chisel3.util._
import include._
//import dbg._
import scala.collection._
import lib._
@ -69,32 +68,6 @@ class dma_ctrl extends Module with lib with RequireAsyncReset {
val dma_address_error = WireInit(Bool(), false.B)
val dma_alignment_error = WireInit(Bool(), false.B)
// val fifo_cmd_en = (0 until DEPTH).map(i=>((bus_cmd_sent & io.dma_bus_clk_en) | (io.dbg_cmd_valid & io.dbg_cmd_type(1))) & (WrPtr === i.U).asUInt()).reverse.reduce(Cat(_,_))
//
// val fifo_data_en = (0 until DEPTH).map(i => ((((bus_cmd_sent & fifo_write_in & io.dma_bus_clk_en) | (io.dbg_cmd_valid & io.dbg_cmd_type(1) & io.dbg_cmd_write)) &
// (i.U === WrPtr)) | ((dma_address_error | dma_alignment_error) & (i.U === RdPtr)) |
// (io.dccm_dma_rvalid & (i.U === io.dccm_dma_rtag)) |
// (io.iccm_dma_rvalid & (i.U === io.iccm_dma_rtag))).asUInt).reverse.reduce(Cat(_,_))
//
// val fifo_pend_en = (0 until DEPTH).map(i => ((io.dma_dccm_req | io.dma_iccm_req) & !io.dma_mem_write & (i.U === RdPtr)).asUInt).reverse.reduce(Cat(_,_))
//
// val dma_dbg_cmd_error = WireInit(Bool(), false.B)
//
// val fifo_error_en = (0 until DEPTH).map(i => (((dma_address_error.asBool | dma_alignment_error.asBool | dma_dbg_cmd_error) &
// (i.U === RdPtr)) | ((io.dccm_dma_rvalid & io.dccm_dma_ecc_error) & (i.U === io.dccm_dma_rtag)) |
// ((io.iccm_dma_rvalid & io.iccm_dma_ecc_error) & (i.U === io.iccm_dma_rtag))).asUInt).reverse.reduce(Cat(_,_))
// val fifo_error_in = Wire(Vec(DEPTH, UInt(2.W)))
// val fifo_error = Wire(Vec(DEPTH, UInt(2.W)))
// val fifo_error_bus_en = (0 until DMA_BUF_DEPTH).map(i=>(((fifo_error_in(i).orR & fifo_error_en(i)) | fifo_error(i).orR) & io.dma_bus_clk_en).asUInt).reverse.reduce(Cat(_,_))
// val fifo_done_en = (0 until DMA_BUF_DEPTH).map(i=>(((fifo_error(i).orR | fifo_error_en(i) | ((io.dma_dccm_req | io.dma_iccm_req) & io.dma_mem_write)) & (i.U === RdPtr)) |
// (io.dccm_dma_rvalid & (i.U === io.dccm_dma_rtag)) | (io.iccm_dma_rvalid & (i.U === io.iccm_dma_rtag))).asUInt).reverse.reduce(Cat(_,_))
// val fifo_done = WireInit(UInt(DEPTH.W), 0.U)
// val fifo_done_bus_en = (0 until DMA_BUF_DEPTH).map(i => ((fifo_done_en(i) | fifo_done(i)) & io.dma_bus_clk_en).asUInt).reverse.reduce(Cat(_,_))
// val bus_rsp_sent = WireInit(Bool(), false.B)
// val bus_posted_write_done = WireInit(Bool(), false.B)
// val RspPtr = WireInit(UInt(DEPTH_PTR.W), 0.U)
// val fifo_reset = (0 until DMA_BUF_DEPTH).map(i=>((((bus_rsp_sent | bus_posted_write_done) & io.dma_bus_clk_en) | io.dma_dbg_cmd_done) & (i.U === RspPtr)).asUInt()).reverse.reduce(Cat(_,_))
// fifo_error_in := (0 until DMA_BUF_DEPTH).map(i=>Mux(io.dccm_dma_rvalid & (io.dccm_dma_rtag===i.U), Cat(0.U(1.W),io.dccm_dma_ecc_error), Mux(io.iccm_dma_rvalid & (io.iccm_dma_rtag===i.U), Cat(0.U(1.W),io.iccm_dma_ecc_error), Cat(dma_address_error | dma_alignment_error | dma_dbg_cmd_error, dma_alignment_error))))
val fifo_cmd_en = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
val fifo_data_en = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
@ -155,7 +128,7 @@ class dma_ctrl extends Module with lib with RequireAsyncReset {
val fifo_posted_write = (0 until DMA_BUF_DEPTH).map(i => (withClock(dma_buffer_c1_clk) {RegEnable(fifo_posted_write_in, 0.U, fifo_cmd_en(i))})).reverse.reduce(Cat(_,_))
val fifo_dbg = (0 until DMA_BUF_DEPTH).map(i => withClock(dma_buffer_c1_clk) {RegEnable(fifo_dbg_in, 0.U, fifo_cmd_en(i))}).reverse.reduce(Cat(_,_))
val fifo_data = Wire(Vec(DMA_BUF_DEPTH,UInt(64.W)))//VecInit.tabulate(DMA_BUF_DEPTH)(i =>rvdffe(fifo_data_in(i), fifo_data_en(i), clock, io.scan_mode))
val fifo_data = Wire(Vec(DMA_BUF_DEPTH,UInt(64.W)))
(0 until DMA_BUF_DEPTH).map(i => fifo_data(i) := rvdffe(fifo_data_in(i), fifo_data_en(i), clock, io.scan_mode))
val bus_cmd_tag = WireInit(UInt(DMA_BUS_TAG.W),0.U)
val bus_cmd_mid = WireInit(UInt(DMA_BUS_ID.W),0.U)

19
design/src/main/scala/exu/exu_mul_ctl.scala
View File

@ -23,14 +23,6 @@ class exu_mul_ctl extends Module with RequireAsyncReset with lib {
val low_x = WireInit(0.U(1.W))
// *** Start - BitManip ***
// val bitmanip_sel_d = WireInit(Bool(),0.B)
// val bitmanip_sel_x = WireInit(Bool(),0.B)
// val bitmanip_d = WireInit(UInt(32.W),0.U)
// val bitmanip_x = WireInit(UInt(32.W),0.U)
// ZBE
val ap_bext = WireInit(Bool(),0.B)
val ap_bdep = WireInit(Bool(),0.B)
@ -188,14 +180,6 @@ class exu_mul_ctl extends Module with RequireAsyncReset with lib {
// return x;
// }
// logic [31:0] gorc1_d;
// logic [31:0] gorc2_d;
// logic [31:0] gorc4_d;
// logic [31:0] gorc8_d;
// logic [31:0] gorc_d;
//
val gorc1_d = ( Fill(32,io.rs2_in(0)) & Range(0, 31, 2).map(i=> Cat(io.rs1_in(i),io.rs1_in(i+1))).reverse.reduce(Cat(_,_)) ) | io.rs1_in
val gorc2_d = ( Fill(32,io.rs2_in(1)) & Range(0, 31, 4).map(i=> Cat(gorc1_d(i+1,i),gorc1_d(i+1+2,i+2))).reverse.reduce(Cat(_,_)) ) | gorc1_d
@ -378,9 +362,6 @@ class exu_mul_ctl extends Module with RequireAsyncReset with lib {
ap_crc32c_w -> crc32c_wd(32)(31,0) ,
ap_bfp -> bfp_result_d(31,0) ))
//rvdffe #(33) i_bitmanip_ff (.*, .clk(clk), .din({bitmanip_sel_d,bitmanip_d[31:0]}), .dout({bitmanip_sel_x,bitmanip_x[31:0]}), .en(bit_x_enable));
val bitmanip_sel_x = rvdffe(bitmanip_sel_d,bit_x_enable,clock,io.scan_mode)
val bitmanip_x = rvdffe(bitmanip_d,bit_x_enable,clock,io.scan_mode)

16
design/src/main/scala/ifu/ifu_aln_ctl.scala
View File

@ -14,22 +14,8 @@ class ifu_aln_ctl extends Module with lib with RequireAsyncReset {
val ic_access_fault_type_f = Input(UInt(2.W)) // Type of access fault occured
val dec_i0_decode_d = Input(Bool())
val dec_aln = new dec_aln()
// val ifu_i0_valid = Output(Bool())
// val ifu_i0_icaf = Output(Bool())
// val ifu_i0_icaf_type = Output(UInt(2.W))
// val ifu_i0_icaf_second = Output(Bool())
// val ifu_i0_dbecc = Output(Bool())
// val ifu_i0_instr = Output(UInt(32.W))
// val ifu_i0_pc = Output(UInt(31.W))
// val ifu_i0_pc4 = Output(Bool())
val ifu_bp_fa_index_f = Vec(2, Input(UInt(log2Ceil(BTB_SIZE).W)))
// val i0_brp = Output(Valid(new br_pkt_t()))
// val ifu_i0_bp_index = Output(UInt((BTB_ADDR_HI-BTB_ADDR_LO+1).W))
// val ifu_i0_bp_fghr = Output(UInt(BHT_GHR_SIZE.W))
// val ifu_i0_bp_btag = Output(UInt(BTB_BTAG_SIZE.W))
val ifu_i0_fa_index = Output(UInt(log2Ceil(BTB_SIZE).W))
// val ifu_pmu_instr_aligned = Output(Bool())
// val ifu_i0_cinst = Output(UInt(16.W))
val ifu_bp_fghr_f = Input(UInt(BHT_GHR_SIZE.W)) // Data coming from the branch predictor to put in the FP
val ifu_bp_btb_target_f = Input(UInt(31.W)) // Target for the instruction enqueue in the FP
val ifu_bp_poffset_f = Input(UInt(12.W)) // Offset to the current PC for branch
@ -513,4 +499,4 @@ class ifu_aln_ctl extends Module with lib with RequireAsyncReset {
}
//object Aligner extends App {
// (new chisel3.stage.ChiselStage).emitVerilog(new ifu_aln_ctl())
//}
//}

111
design/src/main/scala/ifu/ifu_bp_ctl.scala
View File

@ -438,60 +438,60 @@ class ifu_bp_ctl extends Module with lib with RequireAsyncReset {
btb_bank0_rd_data_way0_p1_f := Mux1H((0 until LRU_SIZE).map(i => (btb_rd_addr_p1_f === i.U).asBool -> btb_bank0_rd_data_way0_out(i)))
btb_bank0_rd_data_way1_p1_f := Mux1H((0 until LRU_SIZE).map(i => (btb_rd_addr_p1_f === i.U).asBool -> btb_bank0_rd_data_way1_out(i)))
}
// if(BTB_FULLYA){
// val fetch_mp_collision_f = WireInit(Bool(),init = false.B)
// val fetch_mp_collision_p1_f = WireInit(Bool() ,init = false.B)
//
// // Fully Associative tag hash uses bits 31:3. Bits 2:1 are the offset bits used for the 4 tag comp banks
// // Full tag used to speed up lookup. There is one 31:3 cmp per entry, and 4 2:1 cmps per entry.
// val ifc_fetch_addr_p1_f = io.ifc_fetch_addr_f(FA_CMP_LOWER-1,1) + 1.U
//
//
// // val fetch_mp_collision_f = ((io.exu_bp.exu_mp_btag(BTB_BTAG_SIZE-1,0) === io.ifc_fetch_addr_f) & exu_mp_valid & io.ifc_fetch_req_f & ~io.exu_bp.exu_mp_pkt.bits.way)
// // val fetch_mp_collision_p1_f = ( (io.exu_bp.exu_mp_btag(BTB_BTAG_SIZE-1,0) === Cat(io.ifc_fetch_addr_f(30,FA_CMP_LOWER), ifc_fetch_addr_p1_f(FA_CMP_LOWER-1,1))) & exu_mp_valid & io.ifc_fetch_req_f & ~io.exu_bp.exu_mp_pkt.bits.way)
// // val btb_upper_hit = Wire(Vec(BTB_SIZE,Bool()))
// val btb_offset_0 = WireInit(UInt(BTB_SIZE.W) ,init = 0.U)
// val btb_used = WireInit(UInt(BTB_SIZE.W) ,init = 0.U)
// val btb_offset_1 = WireInit(UInt(BTB_SIZE.W) ,init = 0.U)
// val wr0_en = WireInit(UInt(BTB_SIZE.W) ,init = 0.U)
// val btbdata = Wire(Vec(BTB_SIZE,UInt(BTB_DWIDTH.W)))
// btbdata := btbdata.map(i=> 0.U)
// val hit0 = WireInit(UInt(1.W) ,init = 0.U)
// val hit1 = WireInit(UInt(1.W) ,init = 0.U)
//
// // btb_upper_hit := (0 until BTB_SIZE).map(i=> ((btbdata(i)(BTB_DWIDTH_TOP,FA_TAG_END_UPPER) === io.ifc_fetch_addr_f(30,FA_CMP_LOWER)) & btbdata(i)(0) & ~wr0_en(i)))
// // val btb_offset_0 = (0 until BTB_SIZE).map(i=> (btbdata(i)(FA_TAG_START_LOWER,FA_TAG_END_LOWER) === io.ifc_fetch_addr_f(FA_CMP_LOWER-1,1)) & btb_upper_hit(i))
// // val btb_offset_1 = (0 until BTB_SIZE).map(i=> (btbdata(i)(FA_TAG_START_LOWER,FA_TAG_END_LOWER) === ifc_fetch_addr_p1_f(FA_CMP_LOWER-1,1)) & btb_upper_hit(i))
//
// // hit unless we are also writing this entry at the same time
// val hit0_index = MuxCase(1.U, (0 until BTB_SIZE).map(i=> btb_offset_0(i) -> i.U))
// val hit1_index = MuxCase(1.U, (0 until BTB_SIZE).map(i=> btb_offset_1(i) -> i.U))
// // Mux out the 2 potential branches
// btb_vbank0_rd_data_f := (0 until BTB_SIZE ).map(i=> if(btb_offset_1(i) == 1) Mux(fetch_mp_collision_f,btb_wr_data,btbdata(i)) else 0.U ).reverse.reduce(Cat(_,_))
// btb_vbank1_rd_data_f :=(0 until BTB_SIZE).map(i=> if(btb_offset_1(i) == 1) Mux(fetch_mp_collision_p1_f,btb_wr_data,btbdata(i)) else 0.U).reverse.reduce(Cat(_,_))
// val btb_fa_wr_addr0 = MuxCase(1.U, (0 until BTB_SIZE).map(i=> !btb_used(i) -> i.U))
//
// vwayhit_f := Cat(hit1,hit0) & Cat(eoc_mask,1.U)
// way_raw := vwayhit_f | Cat(fetch_mp_collision_p1_f, fetch_mp_collision_f)
// wr0_en := (0 until BTB_SIZE).map(i=> ((btb_fa_wr_addr0(BTB_FA_INDEX,0) === i.asUInt()) & (exu_mp_valid_write & ~io.exu_bp.exu_mp_pkt.bits.way)) |
// ((io.dec_fa_error_index === i.asUInt()) & dec_tlu_error_wb)).reverse.reduce(Cat(_,_))
// btbdata := (0 until BTB_SIZE).map(i=> rvdffe(btb_wr_data,wr0_en(i),clock,io.scan_mode))
//
// io.ifu_bp_fa_index_f(1) := Mux(hit1,hit1_index,0.U)
// io.ifu_bp_fa_index_f(0) := Mux(hit0,hit0_index,0.U)
//
// val btb_used_reset = btb_used.andR()
// val btb_used_ns = Mux1H(Seq(
// vwayhit_f(1).asBool -> (1.U(32.W) << hit1_index(BTB_FA_INDEX,0)),
// vwayhit_f(0).asBool() -> (1.U(32.W) << hit0_index(BTB_FA_INDEX,0)),
// (exu_mp_valid_write & !io.exu_bp.exu_mp_pkt.bits.way & !dec_tlu_error_wb).asBool() -> (1.U(32.W) << btb_fa_wr_addr0(BTB_FA_INDEX,0)),
// btb_used_reset.asBool -> Fill(BTB_SIZE,0.U),
// (!btb_used_reset & dec_tlu_error_wb ).asBool -> (btb_used & ~(1.U(32.W) << io.dec_fa_error_index(BTB_FA_INDEX,0))),
// !(btb_used_reset | dec_tlu_error_wb ).asBool() -> btb_used
// ))
// val write_used = btb_used_reset | io.ifu_bp_hit_taken_f | exu_mp_valid_write | dec_tlu_error_wb
// btb_used := rvdffe(btb_used_ns,write_used.asBool(),clock,io.scan_mode)
// }
if(BTB_FULLYA){
val fetch_mp_collision_f = WireInit(Bool(),init = false.B)
val fetch_mp_collision_p1_f = WireInit(Bool() ,init = false.B)
// Fully Associative tag hash uses bits 31:3. Bits 2:1 are the offset bits used for the 4 tag comp banks
// Full tag used to speed up lookup. There is one 31:3 cmp per entry, and 4 2:1 cmps per entry.
val ifc_fetch_addr_p1_f = io.ifc_fetch_addr_f(FA_CMP_LOWER-1,1) + 1.U
fetch_mp_collision_f := ((io.exu_bp.exu_mp_btag(BTB_BTAG_SIZE-1,0) === io.ifc_fetch_addr_f) & exu_mp_valid & io.ifc_fetch_req_f & ~io.exu_bp.exu_mp_pkt.bits.way)
fetch_mp_collision_p1_f := ( (io.exu_bp.exu_mp_btag(BTB_BTAG_SIZE-1,0) === Cat(io.ifc_fetch_addr_f(30,FA_CMP_LOWER), ifc_fetch_addr_p1_f(FA_CMP_LOWER-1,1))) & exu_mp_valid & io.ifc_fetch_req_f & ~io.exu_bp.exu_mp_pkt.bits.way)
val btb_upper_hit = Wire(Vec(BTB_SIZE,Bool()))
val btb_offset_0 = WireInit(UInt(BTB_SIZE.W) ,init = 0.U)
val btb_used = WireInit(UInt(BTB_SIZE.W) ,init = 0.U)
val btb_offset_1 = WireInit(UInt(BTB_SIZE.W) ,init = 0.U)
val wr0_en = WireInit(UInt(BTB_SIZE.W) ,init = 0.U)
val btbdata = Wire(Vec(BTB_SIZE,UInt(BTB_DWIDTH.W)))
btbdata := btbdata.map(i=> 0.U)
val hit0 = WireInit(UInt(1.W) ,init = 0.U)
val hit1 = WireInit(UInt(1.W) ,init = 0.U)
btb_upper_hit := (0 until BTB_SIZE).map(i=> ((btbdata(i)(BTB_DWIDTH_TOP,FA_TAG_END_UPPER) === io.ifc_fetch_addr_f(30,FA_CMP_LOWER)) & btbdata(i)(0) & ~wr0_en(i)))
//btb_offset_0 = (0 until BTB_SIZE).map(i=> (btbdata(i)(FA_TAG_START_LOWER,FA_TAG_END_LOWER) === io.ifc_fetch_addr_f(FA_CMP_LOWER-1,1)) & btb_upper_hit(i))
//btb_offset_1 = (0 until BTB_SIZE).map(i=> (btbdata(i)(FA_TAG_START_LOWER,FA_TAG_END_LOWER) === ifc_fetch_addr_p1_f(FA_CMP_LOWER-1,1)) & btb_upper_hit(i))
// hit unless we are also writing this entry at the same time
val hit0_index = MuxCase(1.U, (0 until BTB_SIZE).map(i=> btb_offset_0(i) -> i.U))
val hit1_index = MuxCase(1.U, (0 until BTB_SIZE).map(i=> btb_offset_1(i) -> i.U))
// Mux out the 2 potential branches
btb_vbank0_rd_data_f := (0 until BTB_SIZE ).map(i=> if(btb_offset_1(i) == 1) Mux(fetch_mp_collision_f,btb_wr_data,btbdata(i)) else 0.U ).reverse.reduce(Cat(_,_))
btb_vbank1_rd_data_f :=(0 until BTB_SIZE).map(i=> if(btb_offset_1(i) == 1) Mux(fetch_mp_collision_p1_f,btb_wr_data,btbdata(i)) else 0.U).reverse.reduce(Cat(_,_))
val btb_fa_wr_addr0 = MuxCase(1.U, (0 until BTB_SIZE).map(i=> !btb_used(i) -> i.U))
vwayhit_f := Cat(hit1,hit0) & Cat(eoc_mask,1.U)
way_raw := vwayhit_f | Cat(fetch_mp_collision_p1_f, fetch_mp_collision_f)
wr0_en := (0 until BTB_SIZE).map(i=> ((btb_fa_wr_addr0(BTB_FA_INDEX,0) === i.asUInt()) & (exu_mp_valid_write & ~io.exu_bp.exu_mp_pkt.bits.way)) |
((io.dec_fa_error_index === i.asUInt()) & dec_tlu_error_wb)).reverse.reduce(Cat(_,_))
btbdata := (0 until BTB_SIZE).map(i=> rvdffe(btb_wr_data,wr0_en(i),clock,io.scan_mode))
io.ifu_bp_fa_index_f(1) := Mux(hit1,hit1_index,0.U)
io.ifu_bp_fa_index_f(0) := Mux(hit0,hit0_index,0.U)
val btb_used_reset = btb_used.andR()
val btb_used_ns = Mux1H(Seq(
vwayhit_f(1).asBool -> (1.U(32.W) << hit1_index(BTB_FA_INDEX,0)),
vwayhit_f(0).asBool() -> (1.U(32.W) << hit0_index(BTB_FA_INDEX,0)),
(exu_mp_valid_write & !io.exu_bp.exu_mp_pkt.bits.way & !dec_tlu_error_wb).asBool() -> (1.U(32.W) << btb_fa_wr_addr0(BTB_FA_INDEX,0)),
btb_used_reset.asBool -> Fill(BTB_SIZE,0.U),
(!btb_used_reset & dec_tlu_error_wb ).asBool -> (btb_used & ~(1.U(32.W) << io.dec_fa_error_index(BTB_FA_INDEX,0))),
!(btb_used_reset | dec_tlu_error_wb ).asBool() -> btb_used
))
val write_used = btb_used_reset | io.ifu_bp_hit_taken_f | exu_mp_valid_write | dec_tlu_error_wb
btb_used := rvdffe(btb_used_ns,write_used.asBool(),clock,io.scan_mode)
}
val bht_bank_clken = Wire(Vec(2, Vec(BHT_ARRAY_DEPTH/NUM_BHT_LOOP, Bool())))
@ -530,6 +530,3 @@ class ifu_bp_ctl extends Module with lib with RequireAsyncReset {
bht_bank1_rd_data_f := Mux1H((0 until BHT_ARRAY_DEPTH).map(i=>(bht_rd_addr_f===i.U).asBool->bht_bank_rd_data_out(1)(i)))
bht_bank0_rd_data_p1_f := Mux1H((0 until BHT_ARRAY_DEPTH).map(i=>(bht_rd_addr_p1_f===i.U).asBool->bht_bank_rd_data_out(0)(i)))
}
//object bp_MAIN extends App {
// println((new chisel3.stage.ChiselStage).emitVerilog(new ifu_bp_ctl()))
//}

12
design/src/main/scala/lsu/lsu.scala
View File

@ -31,7 +31,6 @@ class lsu extends Module with RequireAsyncReset with param with lib {
val dec_tlu_mrac_ff = Input(UInt(32.W))
//Outputs
// val lsu_result_m = Output(UInt(32.W))
val lsu_result_corr_r = Output(UInt(32.W))
val lsu_load_stall_any = Output(Bool())
val lsu_store_stall_any = Output(Bool())
@ -56,22 +55,13 @@ class lsu extends Module with RequireAsyncReset with param with lib {
val dma_mem_tag_m = WireInit(0.U(3.W))
val lsu_raw_fwd_lo_r = WireInit(0.U(1.W))
val lsu_raw_fwd_hi_r = WireInit(0.U(1.W))
// val lsu_busm_clken = WireInit(0.U(1.W))
val lsu_bus_obuf_c1_clken = WireInit(0.U(1.W))
// val lsu_addr_d = WireInit(0.U(32.W))
// val lsu_addr_m = WireInit(0.U(32.W))
// val lsu_addr_r = WireInit(0.U(32.W))
// val end_addr_d = WireInit(0.U(32.W))
// val end_addr_m = WireInit(0.U(32.W))
// val end_addr_r = WireInit(0.U(32.W))
val lsu_busreq_r = WireInit(Bool(),false.B)
val ldst_dual_d = WireInit(Bool(),false.B)
val ldst_dual_m = WireInit(Bool(),false.B)
val ldst_dual_r = WireInit(Bool(),false.B)
val lsu_lsc_ctl = Module(new lsu_lsc_ctl())
// io.lsu_exu.lsu_result_m := lsu_lsc_ctl.io.lsu_result_m
// io.lsu_nonblock_load_data := bus_intf.io.lsu_nonblock_load_data
io.lsu_result_corr_r := lsu_lsc_ctl.io.lsu_result_corr_r
val dccm_ctl = Module(new lsu_dccm_ctl())
val stbuf = Module(new lsu_stbuf())
@ -354,4 +344,4 @@ class lsu extends Module with RequireAsyncReset with param with lib {
}
object lsu_main extends App {
println((new chisel3.stage.ChiselStage).emitVerilog(new lsu()))
}
}

3
design/src/main/scala/lsu/lsu_bus_buffer.scala
View File

@ -51,7 +51,6 @@ class lsu_bus_buffer extends Module with RequireAsyncReset with lib {
val lsu_bus_buffer_pend_any = Output(Bool())
val lsu_bus_buffer_full_any = Output(Bool())
val lsu_bus_buffer_empty_any = Output(Bool())
// val lsu_bus_idle_any = Output(Bool())
val ld_byte_hit_buf_lo = Output((UInt(4.W)))
val ld_byte_hit_buf_hi = Output((UInt(4.W)))
val ld_fwddata_buf_lo = Output((UInt(32.W)))
@ -285,7 +284,6 @@ class lsu_bus_buffer extends Module with RequireAsyncReset with lib {
val bus_cmd_ready = WireInit(Bool(), false.B)
val obuf_valid = WireInit(Bool(), false.B)
val obuf_nosend = WireInit(Bool(), false.B)
// val lsu_bus_cntr_overflow = WireInit(Bool(), false.B)
val bus_addr_match_pending = WireInit(Bool(), false.B)
obuf_wr_en := ((ibuf_buf_byp & io.lsu_commit_r & !(io.is_sideeffects_r & bus_sideeffect_pend)) |
@ -553,7 +551,6 @@ class lsu_bus_buffer extends Module with RequireAsyncReset with lib {
val lsu_nonblock_addr_offset = indexing(buf_addr, io.dctl_busbuff.lsu_nonblock_load_data_tag)(1,0)
val lsu_nonblock_sz = indexing(buf_sz, io.dctl_busbuff.lsu_nonblock_load_data_tag)
val lsu_nonblock_unsign = indexing(buf_unsign, io.dctl_busbuff.lsu_nonblock_load_data_tag)
// val lsu_nonblock_dual = indexing(buf_dual.map(_.asUInt).reverse.reduce(Cat(_,_)), io.dctl_busbuff.lsu_nonblock_load_data_tag)
val lsu_nonblock_data_unalgn = Cat(lsu_nonblock_load_data_hi, lsu_nonblock_load_data_lo) >> (lsu_nonblock_addr_offset * 8.U)
io.dctl_busbuff.lsu_nonblock_load_data_valid := lsu_nonblock_load_data_ready & !io.dctl_busbuff.lsu_nonblock_load_data_error

4
design/src/main/scala/lsu/lsu_bus_intf.scala
View File

@ -47,7 +47,6 @@ class lsu_bus_intf extends Module with RequireAsyncReset with lib {
val lsu_bus_buffer_pend_any = Output(Bool())
val lsu_bus_buffer_full_any = Output(Bool())
val lsu_bus_buffer_empty_any = Output(Bool())
//val lsu_bus_idle_any = Output(Bool())
val bus_read_data_m = Output(UInt(32.W))
val lsu_nonblock_load_data = Output((UInt(32.W)))
val dctl_busbuff = new dctl_busbuff()
@ -135,7 +134,6 @@ class lsu_bus_intf extends Module with RequireAsyncReset with lib {
io.lsu_bus_buffer_pend_any := bus_buffer.io.lsu_bus_buffer_pend_any
io.lsu_bus_buffer_full_any := bus_buffer.io.lsu_bus_buffer_full_any
io.lsu_bus_buffer_empty_any := bus_buffer.io.lsu_bus_buffer_empty_any
//io.lsu_bus_idle_any := bus_buffer.io.lsu_bus_idle_any
ld_byte_hit_buf_lo := bus_buffer.io.ld_byte_hit_buf_lo
ld_byte_hit_buf_hi := bus_buffer.io.ld_byte_hit_buf_hi
ld_fwddata_buf_lo := bus_buffer.io.ld_fwddata_buf_lo
@ -202,4 +200,4 @@ class lsu_bus_intf extends Module with RequireAsyncReset with lib {
}
object bus_intf extends App {
println((new chisel3.stage.ChiselStage).emitVerilog(new lsu_bus_intf()))
}
}

5
design/src/main/scala/lsu/lsu_lsc_ctl.scala
View File

@ -38,8 +38,6 @@ class lsu_lsc_ctl extends Module with RequireAsyncReset with lib
val picm_mask_data_m = Input(UInt(32.W))
val bus_read_data_m = Input(UInt(32.W)) //coming from bus interface
// val lsu_result_m = Output(UInt(32.W))
val lsu_result_corr_r = Output(UInt(32.W)) // This is the ECC corrected data going to RF
// lsu address down the pipe
@ -117,7 +115,6 @@ class lsu_lsc_ctl extends Module with RequireAsyncReset with lib
val addrcheck = Module(new lsu_addrcheck())
addrcheck.io.lsu_c2_m_clk := io.lsu_c2_m_clk
//val rst_l = IO(Input(1.W)) //implicit
addrcheck.io.start_addr_d := full_addr_d
addrcheck.io.end_addr_d := full_end_addr_d
addrcheck.io.lsu_pkt_d := io.lsu_pkt_d
@ -280,4 +277,4 @@ class lsu_lsc_ctl extends Module with RequireAsyncReset with lib
}
object lsc_ctl extends App {
println((new chisel3.stage.ChiselStage).emitVerilog(new lsu_lsc_ctl()))
}
}

33
design/src/main/scala/pic_ctrl.scala
View File

@ -14,31 +14,12 @@ class pic_ctrl extends Module with RequireAsyncReset with lib {
val extintsrc_req = Input(UInt (PIC_TOTAL_INT_PLUS1.W))
val lsu_pic = Flipped(new lsu_pic())
val dec_pic = Flipped(new dec_pic)
// val dec_tlu_meicurpl = Input(UInt(4.W))
// val dec_tlu_meipt = Input(UInt(4.W))
//
// val mexintpend = Output(Bool())
// val pic_claimid = Output(UInt(8.W))
// val pic_pl = Output(UInt(4.W))
// val mhwakeup = Output(Bool())
})
def cmp_and_mux (a_id : UInt, a_priority : UInt, b_id : UInt, b_priority : UInt) =
(Mux(a_priority<b_priority, b_id, a_id), Mux(a_priority<b_priority, b_priority, a_priority))
// def configurable_gw (clk : Clock, extintsrc_req_sync : UInt, meigwctrl_polarity : UInt, meigwctrl_type : UInt, meigwclr : UInt) = {
// val gw_int_pending = WireInit(UInt(1.W),0.U)
// val gw_int_pending_in = (extintsrc_req_sync ^ meigwctrl_polarity) | (gw_int_pending & !meigwclr)
// gw_int_pending := withClock(clk){RegNext(gw_int_pending_in,0.U)}
// Mux(meigwctrl_type.asBool(), ((extintsrc_req_sync ^ meigwctrl_polarity) | gw_int_pending), (extintsrc_req_sync ^ meigwctrl_polarity))
// }
// io.mexintpend := 0.U
// io.pic_claimid := 0.U
// io.pic_pl := 0.U
//io.picm_rd_data := 0.U
//io.mhwakeup := 0.U
val NUM_LEVELS = log2Ceil(PIC_TOTAL_INT_PLUS1)
val INTPRIORITY_BASE_ADDR = aslong(PIC_BASE_ADDR)
val INTPEND_BASE_ADDR = aslong(PIC_BASE_ADDR + 0x00001000)
@ -63,11 +44,10 @@ class pic_ctrl extends Module with RequireAsyncReset with lib {
val GW_CONFIG = WireInit(UInt(PIC_TOTAL_INT_PLUS1.W), init=0.U)
val intpend_rd_out = WireInit(0.U(32.W))
// val intenable_rd_out = WireInit(0.U(1.W))
val intpriority_reg_inv = Wire(Vec(PIC_TOTAL_INT_PLUS1,UInt(INTPRIORITY_BITS.W)))
val intpend_reg_extended = WireInit(0.U (INTPEND_SIZE.W))
val selected_int_priority = WireInit(0.U (INTPRIORITY_BITS.W))
val intpend_w_prior_en = Wire(Vec(PIC_TOTAL_INT_PLUS1,UInt(INTPRIORITY_BITS.W)))///////////////////
val intpend_w_prior_en = Wire(Vec(PIC_TOTAL_INT_PLUS1,UInt(INTPRIORITY_BITS.W)))
val intpend_id = Wire(Vec(PIC_TOTAL_INT_PLUS1,UInt(ID_BITS.W)))
val levelx_intpend_w_prior_en = Wire(Vec((NUM_LEVELS - NUM_LEVELS/2)+1 ,Vec ((PIC_TOTAL_INT_PLUS1 / scala.math.pow(2,NUM_LEVELS/2).toInt)+2,UInt(INTPRIORITY_BITS.W))))
for(i<- 0 until (NUM_LEVELS - NUM_LEVELS/2)+1; j<- 0 until (PIC_TOTAL_INT_PLUS1 / scala.math.pow(2,NUM_LEVELS/2).toInt)+2) levelx_intpend_w_prior_en(i)(j) := 0.U
@ -89,7 +69,6 @@ class pic_ctrl extends Module with RequireAsyncReset with lib {
val mask = WireInit(0.U(4.W))
val picm_mken_ff = WireInit(0.U(1.W))
val claimid_in = WireInit(0.U(ID_BITS.W))
//val extintsrc_req_gw = Wire(Vec(PIC_TOTAL_INT_PLUS1,UInt(1.W)))
// clocks
val pic_raddr_c1_clk = Wire(Clock())
@ -255,9 +234,6 @@ class pic_ctrl extends Module with RequireAsyncReset with lib {
}
// io.level_intpend_w_prior_en := (0 to NUM_LEVELS).map(i=>(0 to PIC_TOTAL_INT_PLUS1+1).map(j=>
// level_intpend_w_prior_en(i)(j)).reverse.reduce(Cat(_,_))).reverse.reduce(Cat(_,_))
///////////////////////////////////////////////////////////////////////
// Config Reg`
///////////////////////////////////////////////////////////////////////
@ -299,8 +275,7 @@ class pic_ctrl extends Module with RequireAsyncReset with lib {
val intpend_rd_part_out = Wire(Vec(INT_GRPS,UInt(32.W)))
(0 until INT_GRPS).map (i=> intpend_rd_part_out(i) := Fill(32,(intpend_reg_read & (picm_raddr_ff(5,2) === i.asUInt))) & intpend_reg_extended((32*i)+31,32*i))//.reverse.reduce(Cat(_,_))
intpend_rd_out := intpend_rd_part_out.reduce (_|_)
//for(i <- 0 until PIC_TOTAL_INT_PLUS1) { when (intenable_reg_re(i).asBool){ intenable_rd_out := intenable_reg(i)}.otherwise {intenable_rd_out :=0.U} }
val intenable_rd_out = MuxCase(0.U,(0 until PIC_TOTAL_INT_PLUS1).map (i=> intenable_reg_re(i).asBool -> intenable_reg(i) ))
val intenable_rd_out = MuxCase(0.U,(0 until PIC_TOTAL_INT_PLUS1).map (i=> intenable_reg_re(i).asBool -> intenable_reg(i) ))
val intpriority_rd_out = MuxCase(0.U,(0 until PIC_TOTAL_INT_PLUS1).map (i=> intpriority_reg_re(i).asBool -> intpriority_reg(i)))
val gw_config_rd_out = MuxCase(0.U,(0 until PIC_TOTAL_INT_PLUS1).map (i=> gw_config_reg_re(i).asBool -> gw_config_reg(i)))
//////////////////////////////////////////////////////////////////////////////////////////////////
@ -424,4 +399,4 @@ class pic_ctrl extends Module with RequireAsyncReset with lib {
object pic extends App {
println((new chisel3.stage.ChiselStage).emitVerilog(new pic_ctrl()))
}
}

9
design/src/main/scala/quasar.scala
View File

@ -18,9 +18,9 @@ class quasar_bundle extends Bundle with lib{
val ifu_ahb = new ahb_channel
val sb_ahb = new ahb_channel
val dma_ahb = new Bundle{
val sig = Flipped(new ahb_channel())
val hsel = Input(Bool())
val hreadyin = Input(Bool())}
val sig = Flipped(new ahb_channel())
val hsel = Input(Bool())
val hreadyin = Input(Bool())}
val active_l2clk = Output(Clock())
val free_l2clk = Output(Clock())
@ -63,7 +63,6 @@ class quasar_bundle extends Bundle with lib{
val dmi_reg_wr_en = Input(Bool())
val dmi_reg_wdata = Input(UInt(32.W))
val dmi_reg_rdata = Output(UInt(32.W))
// val dmi_hard_reset = Input(Bool())
val extintsrc_req = Input(UInt(PIC_TOTAL_INT.W))
val timer_int = Input(Bool())
val soft_int = Input(Bool())
@ -325,4 +324,4 @@ class quasar extends Module with RequireAsyncReset with lib {
}
object QUASAR extends App {
println((new chisel3.stage.ChiselStage).emitVerilog(new quasar()))
}
}

142
design/src/main/scala/quasar_wrapper.scala
View File

@ -18,84 +18,83 @@ class quasar_wrapper extends Module with lib with RequireAsyncReset {
val sb_brg = bridge_gen(SB_BUS_TAG , false)
val dma_brg = bridge_gen(DMA_BUS_TAG, true)
val lsu_bus_clk_en = Input(Bool())
val ifu_bus_clk_en = Input(Bool())
val dbg_bus_clk_en = Input(Bool())
val dma_bus_clk_en = Input(Bool())
val lsu_bus_clk_en = Input(Bool())
val ifu_bus_clk_en = Input(Bool())
val dbg_bus_clk_en = Input(Bool())
val dma_bus_clk_en = Input(Bool())
val timer_int = Input(Bool())
val soft_int = Input(Bool())
val timer_int = Input(Bool())
val soft_int = Input(Bool())
val extintsrc_req = Input(UInt(PIC_TOTAL_INT.W))
val extintsrc_req = Input(UInt(PIC_TOTAL_INT.W))
val dec_tlu_perfcnt0 = Output(Bool())
val dec_tlu_perfcnt1 = Output(Bool())
val dec_tlu_perfcnt2 = Output(Bool())
val dec_tlu_perfcnt3 = Output(Bool())
val dec_tlu_perfcnt0 = Output(Bool())
val dec_tlu_perfcnt1 = Output(Bool())
val dec_tlu_perfcnt2 = Output(Bool())
val dec_tlu_perfcnt3 = Output(Bool())
val jtag_tck = Input(Clock())
val jtag_tms = Input(Bool())
val jtag_tdi = Input(Bool())
val jtag_trst_n = Input(Bool())
val jtag_tdo = Output(Bool())
val jtag_tck = Input(Clock())
val jtag_tms = Input(Bool())
val jtag_tdi = Input(Bool())
val jtag_trst_n = Input(Bool())
val jtag_tdo = Output(Bool())
val core_id = Input(UInt(28.W))
val core_id = Input(UInt(28.W))
val mpc_debug_halt_req = Input(Bool())
val mpc_debug_run_req = Input(Bool())
val mpc_reset_run_req = Input(Bool())
val mpc_debug_halt_ack = Output(Bool())
val mpc_debug_run_ack = Output(Bool())
val debug_brkpt_status = Output(Bool())
val mpc_debug_halt_req = Input(Bool())
val mpc_debug_run_req = Input(Bool())
val mpc_reset_run_req = Input(Bool())
val mpc_debug_halt_ack = Output(Bool())
val mpc_debug_run_ack = Output(Bool())
val debug_brkpt_status = Output(Bool())
val i_cpu_halt_req = Input(Bool())
val i_cpu_run_req = Input(Bool())
val o_cpu_halt_ack = Output(Bool())
val o_cpu_halt_status = Output(Bool())
val i_cpu_halt_req = Input(Bool())
val i_cpu_run_req = Input(Bool())
val o_cpu_halt_ack = Output(Bool())
val o_cpu_halt_status = Output(Bool())
val o_debug_mode_status = Output(Bool())
val o_cpu_run_ack = Output(Bool())
val mbist_mode = Input(Bool())
val o_cpu_run_ack = Output(Bool())
val mbist_mode = Input(Bool())
val dccm_ext_in_pkt = Input(new ext_in_pkt_t(DCCM_NUM_BANKS))
val iccm_ext_in_pkt = Input(new ext_in_pkt_t(ICCM_NUM_BANKS))
val ic_data_ext_in_pkt = Input(Vec(ICACHE_NUM_WAYS,new ext_in_pkt_t(ICACHE_NUM_WAYS)))
val ic_tag_ext_in_pkt = Input(new ext_in_pkt_t(ICACHE_NUM_WAYS))
val rv_trace_pkt = new trace_pkt_t()
val scan_mode = Input(Bool())
val dccm_ext_in_pkt = Input(new ext_in_pkt_t(DCCM_NUM_BANKS))
val iccm_ext_in_pkt = Input(new ext_in_pkt_t(ICCM_NUM_BANKS))
val ic_data_ext_in_pkt = Input(Vec(ICACHE_NUM_WAYS,new ext_in_pkt_t(ICACHE_NUM_WAYS)))
val ic_tag_ext_in_pkt = Input(new ext_in_pkt_t(ICACHE_NUM_WAYS))
val rv_trace_pkt = new trace_pkt_t()
val scan_mode = Input(Bool())
})
// val core_rst_l = core.io.core_rst_l
val mem = Module(new quasar.mem())
val dmi_wrapper = Module(new dmi_wrapper())
val core = Module(new quasar())
core.io.scan_mode := io.scan_mode
core.io.scan_mode := io.scan_mode
dmi_wrapper.io.trst_n := io.jtag_trst_n
dmi_wrapper.io.tck := io.jtag_tck
dmi_wrapper.io.tms := io.jtag_tms
dmi_wrapper.io.tdi := io.jtag_tdi
dmi_wrapper.io.tck := io.jtag_tck
dmi_wrapper.io.tms := io.jtag_tms
dmi_wrapper.io.tdi := io.jtag_tdi
dmi_wrapper.io.core_clk := clock
dmi_wrapper.io.jtag_id := io.jtag_id
dmi_wrapper.io.rd_data := core.io.dmi_reg_rdata
dmi_wrapper.io.jtag_id := io.jtag_id
dmi_wrapper.io.rd_data := core.io.dmi_reg_rdata
dmi_wrapper.io.core_rst_n := io.dbg_rst_l
core.io.dmi_reg_wdata := dmi_wrapper.io.reg_wr_data
core.io.dmi_reg_addr := dmi_wrapper.io.reg_wr_addr
core.io.dmi_reg_en := dmi_wrapper.io.reg_en
core.io.dmi_reg_wr_en := dmi_wrapper.io.reg_wr_en
// core.io.dmi_hard_reset := dmi_wrapper.io.dmi_hard_reset
io.jtag_tdo := dmi_wrapper.io.tdo
core.io.dmi_reg_wdata := dmi_wrapper.io.reg_wr_data
core.io.dmi_reg_addr := dmi_wrapper.io.reg_wr_addr
core.io.dmi_reg_en := dmi_wrapper.io.reg_en
core.io.dmi_reg_wr_en := dmi_wrapper.io.reg_wr_en
io.jtag_tdo := dmi_wrapper.io.tdo
// Memory signals
mem.io.dccm_clk_override := core.io.dccm_clk_override
mem.io.icm_clk_override := core.io.icm_clk_override
mem.io.dccm_clk_override := core.io.dccm_clk_override
mem.io.icm_clk_override := core.io.icm_clk_override
mem.io.dec_tlu_core_ecc_disable := core.io.dec_tlu_core_ecc_disable
mem.io.dccm <> core.io.dccm
mem.io.rst_l := core.io.core_rst_l
mem.io.clk := core.io.active_l2clk
mem.io.scan_mode := io.scan_mode
mem.io.dccm_ext_in_pkt := io.dccm_ext_in_pkt
mem.io.iccm_ext_in_pkt := io.iccm_ext_in_pkt
mem.io.ic_data_ext_in_pkt := io.ic_data_ext_in_pkt
mem.io.ic_tag_ext_in_pkt := io.ic_tag_ext_in_pkt
mem.io.rst_l := core.io.core_rst_l
mem.io.clk := core.io.active_l2clk
mem.io.scan_mode := io.scan_mode
mem.io.dccm_ext_in_pkt := io.dccm_ext_in_pkt
mem.io.iccm_ext_in_pkt := io.iccm_ext_in_pkt
mem.io.ic_data_ext_in_pkt := io.ic_data_ext_in_pkt
mem.io.ic_tag_ext_in_pkt := io.ic_tag_ext_in_pkt
// Memory outputs
core.io.dbg_rst_l := io.dbg_rst_l
core.io.ic <> mem.io.ic
@ -116,7 +115,7 @@ class quasar_wrapper extends Module with lib with RequireAsyncReset {
else {
core.io.ifu_ahb <> io.ifu_brg
core.io.lsu_ahb <> io.lsu_brg
core.io.sb_ahb <> io.sb_brg
core.io.sb_ahb <> io.sb_brg
core.io.dma_ahb <> io.dma_brg
core.io.lsu_axi <> 0.U.asTypeOf(core.io.lsu_axi)
@ -132,13 +131,13 @@ class quasar_wrapper extends Module with lib with RequireAsyncReset {
// external halt/run interface
core.io.i_cpu_halt_req := io.i_cpu_halt_req
core.io.i_cpu_run_req := io.i_cpu_run_req
core.io.core_id := io.core_id
core.io.i_cpu_run_req := io.i_cpu_run_req
core.io.core_id := io.core_id
// external MPC halt/run interface
core.io.mpc_debug_halt_req := io.mpc_debug_halt_req
core.io.mpc_debug_run_req := io.mpc_debug_run_req
core.io.mpc_reset_run_req := io.mpc_reset_run_req
core.io.mpc_debug_run_req := io.mpc_debug_run_req
core.io.mpc_reset_run_req := io.mpc_reset_run_req
core.io.lsu_bus_clk_en := io.lsu_bus_clk_en
core.io.ifu_bus_clk_en := io.ifu_bus_clk_en
@ -146,22 +145,21 @@ class quasar_wrapper extends Module with lib with RequireAsyncReset {
core.io.dma_bus_clk_en := io.dma_bus_clk_en
core.io.timer_int := io.timer_int
core.io.soft_int := io.soft_int
core.io.soft_int := io.soft_int
core.io.extintsrc_req := io.extintsrc_req
// Outputs
io.rv_trace_pkt <> core.io.rv_trace_pkt
// external halt/run interface
io.o_cpu_halt_ack := core.io.o_cpu_halt_ack
io.o_cpu_halt_status := core.io.o_cpu_halt_status
io.o_cpu_run_ack := core.io.o_cpu_run_ack
io.o_debug_mode_status := core.io.o_debug_mode_status
io.o_cpu_halt_ack := core.io.o_cpu_halt_ack
io.o_cpu_halt_status := core.io.o_cpu_halt_status
io.o_cpu_run_ack := core.io.o_cpu_run_ack
io.o_debug_mode_status := core.io.o_debug_mode_status
io.mpc_debug_halt_ack := core.io.mpc_debug_halt_ack
io.mpc_debug_run_ack := core.io.mpc_debug_run_ack
io.debug_brkpt_status := core.io.debug_brkpt_status
io.mpc_debug_halt_ack := core.io.mpc_debug_halt_ack
io.mpc_debug_run_ack := core.io.mpc_debug_run_ack
io.debug_brkpt_status := core.io.debug_brkpt_status
io.dec_tlu_perfcnt0 := core.io.dec_tlu_perfcnt0
io.dec_tlu_perfcnt1 := core.io.dec_tlu_perfcnt1
@ -171,4 +169,4 @@ class quasar_wrapper extends Module with lib with RequireAsyncReset {
}
object QUASAR_Wrp extends App {
println((new chisel3.stage.ChiselStage).emitVerilog(new quasar_wrapper()))
}
}