EXU integrated
This commit is contained in:
waleed-lm
parent
e626196137
commit
a3c6794072
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[
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_way",
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"sources":[
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_way"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_prett",
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"sources":[
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_prett"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_valid",
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"sources":[
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_valid"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_br_start_error",
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"sources":[
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_br_start_error"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_ataken",
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"sources":[
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pret",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bge",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pja",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_blt",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_jal",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pcall",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_beq",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bne",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_a_in",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_unsign",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_b_in",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_sub"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_pret",
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"sources":[
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pret"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_pc4",
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"sources":[
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pc4"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_toffset",
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"sources":[
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_toffset"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_br_error",
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"sources":[
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_br_error"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_flush_upper_out",
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"sources":[
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_flush_lower_r",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_valid_in",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_flush_upper_x",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_jal",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pret",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_prett",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_predict_t",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_predict_nt",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bge",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pja",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_sub",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_blt",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pcall",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_beq",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bne",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_a_in",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_unsign",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_b_in"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_boffset",
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"sources":[
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_boffset"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_hist",
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"sources":[
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_hist",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pret",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bge",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pja",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_blt",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_jal",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pcall",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_beq",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bne",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_a_in",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_unsign",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_b_in",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_sub"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_pcall",
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"sources":[
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pcall"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_flush_final_out",
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"sources":[
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_flush_lower_r",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_valid_in",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_flush_upper_x",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_jal",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pret",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_prett",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_predict_t",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_predict_nt",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bge",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pja",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_sub",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_blt",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pcall",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_beq",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bne",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_a_in",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_unsign",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_b_in"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_flush_path_out",
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"sources":[
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pret",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pja",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_jal",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pcall",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_sub",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pc_in",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_brimm_in",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_b_in",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_a_in"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_misp",
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"sources":[
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_flush_upper_x",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_flush_lower_r",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pret",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_predict_t",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_predict_nt",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_prett",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bge",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pja",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_blt",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_jal",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pcall",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_sub",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_beq",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bne",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_a_in",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_unsign",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_b_in"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pred_correct_out",
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"sources":[
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_valid_in",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_predict_nt",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pret",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_predict_t",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pja",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_jal",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pcall",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bge",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_blt",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_beq",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bne",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_a_in",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_unsign",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_b_in",
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_sub"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_predict_p_out_pja",
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"sources":[
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"~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pja"
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]
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},
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{
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"class":"logger.LogLevelAnnotation",
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"globalLogLevel":{
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|
}
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||||||
|
},
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||||||
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{
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||||||
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"class":"firrtl.EmitCircuitAnnotation",
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||||||
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"emitter":"firrtl.VerilogEmitter"
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},
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{
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||||||
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"class":"firrtl.transforms.BlackBoxResourceAnno",
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"target":"el2_exu_alu_ctl.TEC_RV_ICG",
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"resourceId":"/vsrc/TEC_RV_ICG.v"
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},
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{
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"class":"firrtl.options.TargetDirAnnotation",
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"directory":"."
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},
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{
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||||||
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"class":"firrtl.options.OutputAnnotationFileAnnotation",
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"file":"el2_exu_alu_ctl"
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},
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{
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"class":"firrtl.transforms.BlackBoxTargetDirAnno",
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"targetDir":"."
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}
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]
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@ -0,0 +1,568 @@
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;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
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||||||
|
circuit el2_exu_alu_ctl :
|
||||||
|
extmodule TEC_RV_ICG :
|
||||||
|
output Q : Clock
|
||||||
|
input CK : Clock
|
||||||
|
input EN : UInt<1>
|
||||||
|
input SE : UInt<1>
|
||||||
|
|
||||||
|
defname = TEC_RV_ICG
|
||||||
|
|
||||||
|
|
||||||
|
module rvclkhdr :
|
||||||
|
input clock : Clock
|
||||||
|
input reset : Reset
|
||||||
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||||||
|
|
||||||
|
inst clkhdr of TEC_RV_ICG @[el2_lib.scala 465:26]
|
||||||
|
clkhdr.SE is invalid
|
||||||
|
clkhdr.EN is invalid
|
||||||
|
clkhdr.CK is invalid
|
||||||
|
clkhdr.Q is invalid
|
||||||
|
io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14]
|
||||||
|
clkhdr.CK <= io.clk @[el2_lib.scala 467:18]
|
||||||
|
clkhdr.EN <= io.en @[el2_lib.scala 468:18]
|
||||||
|
clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18]
|
||||||
|
|
||||||
|
extmodule TEC_RV_ICG_1 :
|
||||||
|
output Q : Clock
|
||||||
|
input CK : Clock
|
||||||
|
input EN : UInt<1>
|
||||||
|
input SE : UInt<1>
|
||||||
|
|
||||||
|
defname = TEC_RV_ICG
|
||||||
|
|
||||||
|
|
||||||
|
module rvclkhdr_1 :
|
||||||
|
input clock : Clock
|
||||||
|
input reset : Reset
|
||||||
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||||||
|
|
||||||
|
inst clkhdr of TEC_RV_ICG_1 @[el2_lib.scala 465:26]
|
||||||
|
clkhdr.SE is invalid
|
||||||
|
clkhdr.EN is invalid
|
||||||
|
clkhdr.CK is invalid
|
||||||
|
clkhdr.Q is invalid
|
||||||
|
io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14]
|
||||||
|
clkhdr.CK <= io.clk @[el2_lib.scala 467:18]
|
||||||
|
clkhdr.EN <= io.en @[el2_lib.scala 468:18]
|
||||||
|
clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18]
|
||||||
|
|
||||||
|
module el2_exu_alu_ctl :
|
||||||
|
input clock : Clock
|
||||||
|
input reset : AsyncReset
|
||||||
|
output io : {flip scan_mode : UInt<1>, flip flush_upper_x : UInt<1>, flip flush_lower_r : UInt<1>, flip enable : UInt<1>, flip valid_in : UInt<1>, flip ap : {land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, flip csr_ren_in : UInt<1>, flip a_in : SInt<32>, flip b_in : UInt<32>, flip pc_in : UInt<31>, flip pp_in : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, valid : UInt<1>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}, flip brimm_in : UInt<12>, result_ff : UInt<32>, flush_upper_out : UInt<1>, flush_final_out : UInt<1>, flush_path_out : UInt<31>, pc_ff : UInt<31>, pred_correct_out : UInt<1>, predict_p_out : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, valid : UInt<1>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}
|
||||||
|
|
||||||
|
node _T = bits(io.scan_mode, 0, 0) @[el2_exu_alu_ctl.scala 35:60]
|
||||||
|
inst rvclkhdr of rvclkhdr @[el2_lib.scala 485:23]
|
||||||
|
rvclkhdr.clock <= clock
|
||||||
|
rvclkhdr.reset <= reset
|
||||||
|
rvclkhdr.io.clk <= clock @[el2_lib.scala 487:18]
|
||||||
|
rvclkhdr.io.en <= io.enable @[el2_lib.scala 488:17]
|
||||||
|
rvclkhdr.io.scan_mode <= _T @[el2_lib.scala 489:24]
|
||||||
|
reg _T_1 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16]
|
||||||
|
_T_1 <= io.pc_in @[el2_lib.scala 491:16]
|
||||||
|
io.pc_ff <= _T_1 @[el2_exu_alu_ctl.scala 35:12]
|
||||||
|
wire result : UInt<32>
|
||||||
|
result <= UInt<1>("h00")
|
||||||
|
node _T_2 = bits(io.scan_mode, 0, 0) @[el2_exu_alu_ctl.scala 37:62]
|
||||||
|
inst rvclkhdr_1 of rvclkhdr_1 @[el2_lib.scala 485:23]
|
||||||
|
rvclkhdr_1.clock <= clock
|
||||||
|
rvclkhdr_1.reset <= reset
|
||||||
|
rvclkhdr_1.io.clk <= clock @[el2_lib.scala 487:18]
|
||||||
|
rvclkhdr_1.io.en <= io.enable @[el2_lib.scala 488:17]
|
||||||
|
rvclkhdr_1.io.scan_mode <= _T_2 @[el2_lib.scala 489:24]
|
||||||
|
reg _T_3 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16]
|
||||||
|
_T_3 <= result @[el2_lib.scala 491:16]
|
||||||
|
io.result_ff <= _T_3 @[el2_exu_alu_ctl.scala 37:16]
|
||||||
|
node _T_4 = bits(io.ap.sub, 0, 0) @[el2_exu_alu_ctl.scala 39:29]
|
||||||
|
node _T_5 = not(io.b_in) @[el2_exu_alu_ctl.scala 39:37]
|
||||||
|
node bm = mux(_T_4, _T_5, io.b_in) @[el2_exu_alu_ctl.scala 39:17]
|
||||||
|
wire aout : UInt<33>
|
||||||
|
aout <= UInt<1>("h00")
|
||||||
|
node _T_6 = bits(io.ap.sub, 0, 0) @[el2_exu_alu_ctl.scala 42:25]
|
||||||
|
node _T_7 = asUInt(io.a_in) @[Cat.scala 29:58]
|
||||||
|
node _T_8 = cat(UInt<1>("h00"), _T_7) @[Cat.scala 29:58]
|
||||||
|
node _T_9 = not(io.b_in) @[el2_exu_alu_ctl.scala 42:70]
|
||||||
|
node _T_10 = cat(UInt<1>("h00"), _T_9) @[Cat.scala 29:58]
|
||||||
|
node _T_11 = add(_T_8, _T_10) @[el2_exu_alu_ctl.scala 42:55]
|
||||||
|
node _T_12 = tail(_T_11, 1) @[el2_exu_alu_ctl.scala 42:55]
|
||||||
|
node _T_13 = cat(UInt<32>("h00"), io.ap.sub) @[Cat.scala 29:58]
|
||||||
|
node _T_14 = add(_T_12, _T_13) @[el2_exu_alu_ctl.scala 42:80]
|
||||||
|
node _T_15 = tail(_T_14, 1) @[el2_exu_alu_ctl.scala 42:80]
|
||||||
|
node _T_16 = asUInt(io.a_in) @[Cat.scala 29:58]
|
||||||
|
node _T_17 = cat(UInt<1>("h00"), _T_16) @[Cat.scala 29:58]
|
||||||
|
node _T_18 = cat(UInt<1>("h00"), io.b_in) @[Cat.scala 29:58]
|
||||||
|
node _T_19 = add(_T_17, _T_18) @[el2_exu_alu_ctl.scala 42:132]
|
||||||
|
node _T_20 = tail(_T_19, 1) @[el2_exu_alu_ctl.scala 42:132]
|
||||||
|
node _T_21 = cat(UInt<32>("h00"), io.ap.sub) @[Cat.scala 29:58]
|
||||||
|
node _T_22 = add(_T_20, _T_21) @[el2_exu_alu_ctl.scala 42:157]
|
||||||
|
node _T_23 = tail(_T_22, 1) @[el2_exu_alu_ctl.scala 42:157]
|
||||||
|
node _T_24 = mux(_T_6, _T_15, _T_23) @[el2_exu_alu_ctl.scala 42:14]
|
||||||
|
aout <= _T_24 @[el2_exu_alu_ctl.scala 42:8]
|
||||||
|
node cout = bits(aout, 32, 32) @[el2_exu_alu_ctl.scala 43:18]
|
||||||
|
node _T_25 = bits(io.a_in, 31, 31) @[el2_exu_alu_ctl.scala 45:22]
|
||||||
|
node _T_26 = not(_T_25) @[el2_exu_alu_ctl.scala 45:14]
|
||||||
|
node _T_27 = bits(bm, 31, 31) @[el2_exu_alu_ctl.scala 45:32]
|
||||||
|
node _T_28 = not(_T_27) @[el2_exu_alu_ctl.scala 45:29]
|
||||||
|
node _T_29 = and(_T_26, _T_28) @[el2_exu_alu_ctl.scala 45:27]
|
||||||
|
node _T_30 = bits(aout, 31, 31) @[el2_exu_alu_ctl.scala 45:44]
|
||||||
|
node _T_31 = and(_T_29, _T_30) @[el2_exu_alu_ctl.scala 45:37]
|
||||||
|
node _T_32 = bits(io.a_in, 31, 31) @[el2_exu_alu_ctl.scala 45:61]
|
||||||
|
node _T_33 = bits(bm, 31, 31) @[el2_exu_alu_ctl.scala 45:71]
|
||||||
|
node _T_34 = and(_T_32, _T_33) @[el2_exu_alu_ctl.scala 45:66]
|
||||||
|
node _T_35 = bits(aout, 31, 31) @[el2_exu_alu_ctl.scala 45:83]
|
||||||
|
node _T_36 = not(_T_35) @[el2_exu_alu_ctl.scala 45:78]
|
||||||
|
node _T_37 = and(_T_34, _T_36) @[el2_exu_alu_ctl.scala 45:76]
|
||||||
|
node ov = or(_T_31, _T_37) @[el2_exu_alu_ctl.scala 45:50]
|
||||||
|
node _T_38 = asSInt(io.b_in) @[el2_exu_alu_ctl.scala 47:50]
|
||||||
|
node eq = eq(io.a_in, _T_38) @[el2_exu_alu_ctl.scala 47:38]
|
||||||
|
node ne = not(eq) @[el2_exu_alu_ctl.scala 48:29]
|
||||||
|
node neg = bits(aout, 31, 31) @[el2_exu_alu_ctl.scala 49:34]
|
||||||
|
node _T_39 = not(io.ap.unsign) @[el2_exu_alu_ctl.scala 50:30]
|
||||||
|
node _T_40 = xor(neg, ov) @[el2_exu_alu_ctl.scala 50:51]
|
||||||
|
node _T_41 = and(_T_39, _T_40) @[el2_exu_alu_ctl.scala 50:44]
|
||||||
|
node _T_42 = not(cout) @[el2_exu_alu_ctl.scala 50:78]
|
||||||
|
node _T_43 = and(io.ap.unsign, _T_42) @[el2_exu_alu_ctl.scala 50:76]
|
||||||
|
node lt = or(_T_41, _T_43) @[el2_exu_alu_ctl.scala 50:58]
|
||||||
|
node ge = not(lt) @[el2_exu_alu_ctl.scala 51:29]
|
||||||
|
node _T_44 = bits(io.csr_ren_in, 0, 0) @[el2_exu_alu_ctl.scala 55:19]
|
||||||
|
node _T_45 = asSInt(io.b_in) @[el2_exu_alu_ctl.scala 55:50]
|
||||||
|
node _T_46 = bits(io.ap.land, 0, 0) @[el2_exu_alu_ctl.scala 56:16]
|
||||||
|
node _T_47 = asSInt(io.b_in) @[el2_exu_alu_ctl.scala 56:50]
|
||||||
|
node _T_48 = and(io.a_in, _T_47) @[el2_exu_alu_ctl.scala 56:39]
|
||||||
|
node _T_49 = asSInt(_T_48) @[el2_exu_alu_ctl.scala 56:39]
|
||||||
|
node _T_50 = bits(io.ap.lor, 0, 0) @[el2_exu_alu_ctl.scala 57:15]
|
||||||
|
node _T_51 = asSInt(io.b_in) @[el2_exu_alu_ctl.scala 57:50]
|
||||||
|
node _T_52 = or(io.a_in, _T_51) @[el2_exu_alu_ctl.scala 57:39]
|
||||||
|
node _T_53 = asSInt(_T_52) @[el2_exu_alu_ctl.scala 57:39]
|
||||||
|
node _T_54 = bits(io.ap.lxor, 0, 0) @[el2_exu_alu_ctl.scala 58:16]
|
||||||
|
node _T_55 = asSInt(io.b_in) @[el2_exu_alu_ctl.scala 58:50]
|
||||||
|
node _T_56 = xor(io.a_in, _T_55) @[el2_exu_alu_ctl.scala 58:39]
|
||||||
|
node _T_57 = asSInt(_T_56) @[el2_exu_alu_ctl.scala 58:39]
|
||||||
|
wire _T_58 : SInt<32> @[Mux.scala 27:72]
|
||||||
|
node _T_59 = asUInt(_T_45) @[Mux.scala 27:72]
|
||||||
|
node _T_60 = asSInt(_T_59) @[Mux.scala 27:72]
|
||||||
|
_T_58 <= _T_60 @[Mux.scala 27:72]
|
||||||
|
wire _T_61 : SInt<32> @[Mux.scala 27:72]
|
||||||
|
node _T_62 = asUInt(_T_49) @[Mux.scala 27:72]
|
||||||
|
node _T_63 = asSInt(_T_62) @[Mux.scala 27:72]
|
||||||
|
_T_61 <= _T_63 @[Mux.scala 27:72]
|
||||||
|
wire _T_64 : SInt<32> @[Mux.scala 27:72]
|
||||||
|
node _T_65 = asUInt(_T_53) @[Mux.scala 27:72]
|
||||||
|
node _T_66 = asSInt(_T_65) @[Mux.scala 27:72]
|
||||||
|
_T_64 <= _T_66 @[Mux.scala 27:72]
|
||||||
|
wire _T_67 : SInt<32> @[Mux.scala 27:72]
|
||||||
|
node _T_68 = asUInt(_T_57) @[Mux.scala 27:72]
|
||||||
|
node _T_69 = asSInt(_T_68) @[Mux.scala 27:72]
|
||||||
|
_T_67 <= _T_69 @[Mux.scala 27:72]
|
||||||
|
node _T_70 = mux(_T_44, _T_58, asSInt(UInt<1>("h00"))) @[Mux.scala 27:72]
|
||||||
|
node _T_71 = mux(_T_46, _T_61, asSInt(UInt<1>("h00"))) @[Mux.scala 27:72]
|
||||||
|
node _T_72 = mux(_T_50, _T_64, asSInt(UInt<1>("h00"))) @[Mux.scala 27:72]
|
||||||
|
node _T_73 = mux(_T_54, _T_67, asSInt(UInt<1>("h00"))) @[Mux.scala 27:72]
|
||||||
|
node _T_74 = or(_T_70, _T_71) @[Mux.scala 27:72]
|
||||||
|
node _T_75 = asSInt(_T_74) @[Mux.scala 27:72]
|
||||||
|
node _T_76 = or(_T_75, _T_72) @[Mux.scala 27:72]
|
||||||
|
node _T_77 = asSInt(_T_76) @[Mux.scala 27:72]
|
||||||
|
node _T_78 = or(_T_77, _T_73) @[Mux.scala 27:72]
|
||||||
|
node _T_79 = asSInt(_T_78) @[Mux.scala 27:72]
|
||||||
|
wire lout : SInt<32> @[Mux.scala 27:72]
|
||||||
|
node _T_80 = asUInt(_T_79) @[Mux.scala 27:72]
|
||||||
|
node _T_81 = asSInt(_T_80) @[Mux.scala 27:72]
|
||||||
|
lout <= _T_81 @[Mux.scala 27:72]
|
||||||
|
node _T_82 = bits(io.ap.sll, 0, 0) @[el2_exu_alu_ctl.scala 61:15]
|
||||||
|
node _T_83 = bits(io.b_in, 4, 0) @[el2_exu_alu_ctl.scala 61:60]
|
||||||
|
node _T_84 = cat(UInt<1>("h00"), _T_83) @[Cat.scala 29:58]
|
||||||
|
node _T_85 = sub(UInt<6>("h020"), _T_84) @[el2_exu_alu_ctl.scala 61:38]
|
||||||
|
node _T_86 = tail(_T_85, 1) @[el2_exu_alu_ctl.scala 61:38]
|
||||||
|
node _T_87 = bits(io.ap.srl, 0, 0) @[el2_exu_alu_ctl.scala 62:15]
|
||||||
|
node _T_88 = bits(io.b_in, 4, 0) @[el2_exu_alu_ctl.scala 62:60]
|
||||||
|
node _T_89 = cat(UInt<1>("h00"), _T_88) @[Cat.scala 29:58]
|
||||||
|
node _T_90 = bits(io.ap.sra, 0, 0) @[el2_exu_alu_ctl.scala 63:15]
|
||||||
|
node _T_91 = bits(io.b_in, 4, 0) @[el2_exu_alu_ctl.scala 63:60]
|
||||||
|
node _T_92 = cat(UInt<1>("h00"), _T_91) @[Cat.scala 29:58]
|
||||||
|
node _T_93 = mux(_T_82, _T_86, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||||
|
node _T_94 = mux(_T_87, _T_89, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||||
|
node _T_95 = mux(_T_90, _T_92, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||||
|
node _T_96 = or(_T_93, _T_94) @[Mux.scala 27:72]
|
||||||
|
node _T_97 = or(_T_96, _T_95) @[Mux.scala 27:72]
|
||||||
|
wire shift_amount : UInt<6> @[Mux.scala 27:72]
|
||||||
|
shift_amount <= _T_97 @[Mux.scala 27:72]
|
||||||
|
wire shift_mask : UInt<32>
|
||||||
|
shift_mask <= UInt<1>("h00")
|
||||||
|
wire _T_98 : UInt<1>[5] @[el2_lib.scala 161:48]
|
||||||
|
_T_98[0] <= io.ap.sll @[el2_lib.scala 161:48]
|
||||||
|
_T_98[1] <= io.ap.sll @[el2_lib.scala 161:48]
|
||||||
|
_T_98[2] <= io.ap.sll @[el2_lib.scala 161:48]
|
||||||
|
_T_98[3] <= io.ap.sll @[el2_lib.scala 161:48]
|
||||||
|
_T_98[4] <= io.ap.sll @[el2_lib.scala 161:48]
|
||||||
|
node _T_99 = cat(_T_98[0], _T_98[1]) @[Cat.scala 29:58]
|
||||||
|
node _T_100 = cat(_T_99, _T_98[2]) @[Cat.scala 29:58]
|
||||||
|
node _T_101 = cat(_T_100, _T_98[3]) @[Cat.scala 29:58]
|
||||||
|
node _T_102 = cat(_T_101, _T_98[4]) @[Cat.scala 29:58]
|
||||||
|
node _T_103 = bits(io.b_in, 4, 0) @[el2_exu_alu_ctl.scala 66:70]
|
||||||
|
node _T_104 = and(_T_102, _T_103) @[el2_exu_alu_ctl.scala 66:61]
|
||||||
|
node _T_105 = dshl(UInt<32>("h0ffffffff"), _T_104) @[el2_exu_alu_ctl.scala 66:39]
|
||||||
|
shift_mask <= _T_105 @[el2_exu_alu_ctl.scala 66:14]
|
||||||
|
wire shift_extend : UInt<63>
|
||||||
|
shift_extend <= UInt<1>("h00")
|
||||||
|
wire _T_106 : UInt<1>[31] @[el2_lib.scala 161:48]
|
||||||
|
_T_106[0] <= io.ap.sra @[el2_lib.scala 161:48]
|
||||||
|
_T_106[1] <= io.ap.sra @[el2_lib.scala 161:48]
|
||||||
|
_T_106[2] <= io.ap.sra @[el2_lib.scala 161:48]
|
||||||
|
_T_106[3] <= io.ap.sra @[el2_lib.scala 161:48]
|
||||||
|
_T_106[4] <= io.ap.sra @[el2_lib.scala 161:48]
|
||||||
|
_T_106[5] <= io.ap.sra @[el2_lib.scala 161:48]
|
||||||
|
_T_106[6] <= io.ap.sra @[el2_lib.scala 161:48]
|
||||||
|
_T_106[7] <= io.ap.sra @[el2_lib.scala 161:48]
|
||||||
|
_T_106[8] <= io.ap.sra @[el2_lib.scala 161:48]
|
||||||
|
_T_106[9] <= io.ap.sra @[el2_lib.scala 161:48]
|
||||||
|
_T_106[10] <= io.ap.sra @[el2_lib.scala 161:48]
|
||||||
|
_T_106[11] <= io.ap.sra @[el2_lib.scala 161:48]
|
||||||
|
_T_106[12] <= io.ap.sra @[el2_lib.scala 161:48]
|
||||||
|
_T_106[13] <= io.ap.sra @[el2_lib.scala 161:48]
|
||||||
|
_T_106[14] <= io.ap.sra @[el2_lib.scala 161:48]
|
||||||
|
_T_106[15] <= io.ap.sra @[el2_lib.scala 161:48]
|
||||||
|
_T_106[16] <= io.ap.sra @[el2_lib.scala 161:48]
|
||||||
|
_T_106[17] <= io.ap.sra @[el2_lib.scala 161:48]
|
||||||
|
_T_106[18] <= io.ap.sra @[el2_lib.scala 161:48]
|
||||||
|
_T_106[19] <= io.ap.sra @[el2_lib.scala 161:48]
|
||||||
|
_T_106[20] <= io.ap.sra @[el2_lib.scala 161:48]
|
||||||
|
_T_106[21] <= io.ap.sra @[el2_lib.scala 161:48]
|
||||||
|
_T_106[22] <= io.ap.sra @[el2_lib.scala 161:48]
|
||||||
|
_T_106[23] <= io.ap.sra @[el2_lib.scala 161:48]
|
||||||
|
_T_106[24] <= io.ap.sra @[el2_lib.scala 161:48]
|
||||||
|
_T_106[25] <= io.ap.sra @[el2_lib.scala 161:48]
|
||||||
|
_T_106[26] <= io.ap.sra @[el2_lib.scala 161:48]
|
||||||
|
_T_106[27] <= io.ap.sra @[el2_lib.scala 161:48]
|
||||||
|
_T_106[28] <= io.ap.sra @[el2_lib.scala 161:48]
|
||||||
|
_T_106[29] <= io.ap.sra @[el2_lib.scala 161:48]
|
||||||
|
_T_106[30] <= io.ap.sra @[el2_lib.scala 161:48]
|
||||||
|
node _T_107 = cat(_T_106[0], _T_106[1]) @[Cat.scala 29:58]
|
||||||
|
node _T_108 = cat(_T_107, _T_106[2]) @[Cat.scala 29:58]
|
||||||
|
node _T_109 = cat(_T_108, _T_106[3]) @[Cat.scala 29:58]
|
||||||
|
node _T_110 = cat(_T_109, _T_106[4]) @[Cat.scala 29:58]
|
||||||
|
node _T_111 = cat(_T_110, _T_106[5]) @[Cat.scala 29:58]
|
||||||
|
node _T_112 = cat(_T_111, _T_106[6]) @[Cat.scala 29:58]
|
||||||
|
node _T_113 = cat(_T_112, _T_106[7]) @[Cat.scala 29:58]
|
||||||
|
node _T_114 = cat(_T_113, _T_106[8]) @[Cat.scala 29:58]
|
||||||
|
node _T_115 = cat(_T_114, _T_106[9]) @[Cat.scala 29:58]
|
||||||
|
node _T_116 = cat(_T_115, _T_106[10]) @[Cat.scala 29:58]
|
||||||
|
node _T_117 = cat(_T_116, _T_106[11]) @[Cat.scala 29:58]
|
||||||
|
node _T_118 = cat(_T_117, _T_106[12]) @[Cat.scala 29:58]
|
||||||
|
node _T_119 = cat(_T_118, _T_106[13]) @[Cat.scala 29:58]
|
||||||
|
node _T_120 = cat(_T_119, _T_106[14]) @[Cat.scala 29:58]
|
||||||
|
node _T_121 = cat(_T_120, _T_106[15]) @[Cat.scala 29:58]
|
||||||
|
node _T_122 = cat(_T_121, _T_106[16]) @[Cat.scala 29:58]
|
||||||
|
node _T_123 = cat(_T_122, _T_106[17]) @[Cat.scala 29:58]
|
||||||
|
node _T_124 = cat(_T_123, _T_106[18]) @[Cat.scala 29:58]
|
||||||
|
node _T_125 = cat(_T_124, _T_106[19]) @[Cat.scala 29:58]
|
||||||
|
node _T_126 = cat(_T_125, _T_106[20]) @[Cat.scala 29:58]
|
||||||
|
node _T_127 = cat(_T_126, _T_106[21]) @[Cat.scala 29:58]
|
||||||
|
node _T_128 = cat(_T_127, _T_106[22]) @[Cat.scala 29:58]
|
||||||
|
node _T_129 = cat(_T_128, _T_106[23]) @[Cat.scala 29:58]
|
||||||
|
node _T_130 = cat(_T_129, _T_106[24]) @[Cat.scala 29:58]
|
||||||
|
node _T_131 = cat(_T_130, _T_106[25]) @[Cat.scala 29:58]
|
||||||
|
node _T_132 = cat(_T_131, _T_106[26]) @[Cat.scala 29:58]
|
||||||
|
node _T_133 = cat(_T_132, _T_106[27]) @[Cat.scala 29:58]
|
||||||
|
node _T_134 = cat(_T_133, _T_106[28]) @[Cat.scala 29:58]
|
||||||
|
node _T_135 = cat(_T_134, _T_106[29]) @[Cat.scala 29:58]
|
||||||
|
node _T_136 = cat(_T_135, _T_106[30]) @[Cat.scala 29:58]
|
||||||
|
node _T_137 = bits(io.a_in, 31, 31) @[el2_exu_alu_ctl.scala 69:61]
|
||||||
|
wire _T_138 : UInt<1>[31] @[el2_lib.scala 161:48]
|
||||||
|
_T_138[0] <= _T_137 @[el2_lib.scala 161:48]
|
||||||
|
_T_138[1] <= _T_137 @[el2_lib.scala 161:48]
|
||||||
|
_T_138[2] <= _T_137 @[el2_lib.scala 161:48]
|
||||||
|
_T_138[3] <= _T_137 @[el2_lib.scala 161:48]
|
||||||
|
_T_138[4] <= _T_137 @[el2_lib.scala 161:48]
|
||||||
|
_T_138[5] <= _T_137 @[el2_lib.scala 161:48]
|
||||||
|
_T_138[6] <= _T_137 @[el2_lib.scala 161:48]
|
||||||
|
_T_138[7] <= _T_137 @[el2_lib.scala 161:48]
|
||||||
|
_T_138[8] <= _T_137 @[el2_lib.scala 161:48]
|
||||||
|
_T_138[9] <= _T_137 @[el2_lib.scala 161:48]
|
||||||
|
_T_138[10] <= _T_137 @[el2_lib.scala 161:48]
|
||||||
|
_T_138[11] <= _T_137 @[el2_lib.scala 161:48]
|
||||||
|
_T_138[12] <= _T_137 @[el2_lib.scala 161:48]
|
||||||
|
_T_138[13] <= _T_137 @[el2_lib.scala 161:48]
|
||||||
|
_T_138[14] <= _T_137 @[el2_lib.scala 161:48]
|
||||||
|
_T_138[15] <= _T_137 @[el2_lib.scala 161:48]
|
||||||
|
_T_138[16] <= _T_137 @[el2_lib.scala 161:48]
|
||||||
|
_T_138[17] <= _T_137 @[el2_lib.scala 161:48]
|
||||||
|
_T_138[18] <= _T_137 @[el2_lib.scala 161:48]
|
||||||
|
_T_138[19] <= _T_137 @[el2_lib.scala 161:48]
|
||||||
|
_T_138[20] <= _T_137 @[el2_lib.scala 161:48]
|
||||||
|
_T_138[21] <= _T_137 @[el2_lib.scala 161:48]
|
||||||
|
_T_138[22] <= _T_137 @[el2_lib.scala 161:48]
|
||||||
|
_T_138[23] <= _T_137 @[el2_lib.scala 161:48]
|
||||||
|
_T_138[24] <= _T_137 @[el2_lib.scala 161:48]
|
||||||
|
_T_138[25] <= _T_137 @[el2_lib.scala 161:48]
|
||||||
|
_T_138[26] <= _T_137 @[el2_lib.scala 161:48]
|
||||||
|
_T_138[27] <= _T_137 @[el2_lib.scala 161:48]
|
||||||
|
_T_138[28] <= _T_137 @[el2_lib.scala 161:48]
|
||||||
|
_T_138[29] <= _T_137 @[el2_lib.scala 161:48]
|
||||||
|
_T_138[30] <= _T_137 @[el2_lib.scala 161:48]
|
||||||
|
node _T_139 = cat(_T_138[0], _T_138[1]) @[Cat.scala 29:58]
|
||||||
|
node _T_140 = cat(_T_139, _T_138[2]) @[Cat.scala 29:58]
|
||||||
|
node _T_141 = cat(_T_140, _T_138[3]) @[Cat.scala 29:58]
|
||||||
|
node _T_142 = cat(_T_141, _T_138[4]) @[Cat.scala 29:58]
|
||||||
|
node _T_143 = cat(_T_142, _T_138[5]) @[Cat.scala 29:58]
|
||||||
|
node _T_144 = cat(_T_143, _T_138[6]) @[Cat.scala 29:58]
|
||||||
|
node _T_145 = cat(_T_144, _T_138[7]) @[Cat.scala 29:58]
|
||||||
|
node _T_146 = cat(_T_145, _T_138[8]) @[Cat.scala 29:58]
|
||||||
|
node _T_147 = cat(_T_146, _T_138[9]) @[Cat.scala 29:58]
|
||||||
|
node _T_148 = cat(_T_147, _T_138[10]) @[Cat.scala 29:58]
|
||||||
|
node _T_149 = cat(_T_148, _T_138[11]) @[Cat.scala 29:58]
|
||||||
|
node _T_150 = cat(_T_149, _T_138[12]) @[Cat.scala 29:58]
|
||||||
|
node _T_151 = cat(_T_150, _T_138[13]) @[Cat.scala 29:58]
|
||||||
|
node _T_152 = cat(_T_151, _T_138[14]) @[Cat.scala 29:58]
|
||||||
|
node _T_153 = cat(_T_152, _T_138[15]) @[Cat.scala 29:58]
|
||||||
|
node _T_154 = cat(_T_153, _T_138[16]) @[Cat.scala 29:58]
|
||||||
|
node _T_155 = cat(_T_154, _T_138[17]) @[Cat.scala 29:58]
|
||||||
|
node _T_156 = cat(_T_155, _T_138[18]) @[Cat.scala 29:58]
|
||||||
|
node _T_157 = cat(_T_156, _T_138[19]) @[Cat.scala 29:58]
|
||||||
|
node _T_158 = cat(_T_157, _T_138[20]) @[Cat.scala 29:58]
|
||||||
|
node _T_159 = cat(_T_158, _T_138[21]) @[Cat.scala 29:58]
|
||||||
|
node _T_160 = cat(_T_159, _T_138[22]) @[Cat.scala 29:58]
|
||||||
|
node _T_161 = cat(_T_160, _T_138[23]) @[Cat.scala 29:58]
|
||||||
|
node _T_162 = cat(_T_161, _T_138[24]) @[Cat.scala 29:58]
|
||||||
|
node _T_163 = cat(_T_162, _T_138[25]) @[Cat.scala 29:58]
|
||||||
|
node _T_164 = cat(_T_163, _T_138[26]) @[Cat.scala 29:58]
|
||||||
|
node _T_165 = cat(_T_164, _T_138[27]) @[Cat.scala 29:58]
|
||||||
|
node _T_166 = cat(_T_165, _T_138[28]) @[Cat.scala 29:58]
|
||||||
|
node _T_167 = cat(_T_166, _T_138[29]) @[Cat.scala 29:58]
|
||||||
|
node _T_168 = cat(_T_167, _T_138[30]) @[Cat.scala 29:58]
|
||||||
|
node _T_169 = and(_T_136, _T_168) @[el2_exu_alu_ctl.scala 69:44]
|
||||||
|
wire _T_170 : UInt<1>[31] @[el2_lib.scala 161:48]
|
||||||
|
_T_170[0] <= io.ap.sll @[el2_lib.scala 161:48]
|
||||||
|
_T_170[1] <= io.ap.sll @[el2_lib.scala 161:48]
|
||||||
|
_T_170[2] <= io.ap.sll @[el2_lib.scala 161:48]
|
||||||
|
_T_170[3] <= io.ap.sll @[el2_lib.scala 161:48]
|
||||||
|
_T_170[4] <= io.ap.sll @[el2_lib.scala 161:48]
|
||||||
|
_T_170[5] <= io.ap.sll @[el2_lib.scala 161:48]
|
||||||
|
_T_170[6] <= io.ap.sll @[el2_lib.scala 161:48]
|
||||||
|
_T_170[7] <= io.ap.sll @[el2_lib.scala 161:48]
|
||||||
|
_T_170[8] <= io.ap.sll @[el2_lib.scala 161:48]
|
||||||
|
_T_170[9] <= io.ap.sll @[el2_lib.scala 161:48]
|
||||||
|
_T_170[10] <= io.ap.sll @[el2_lib.scala 161:48]
|
||||||
|
_T_170[11] <= io.ap.sll @[el2_lib.scala 161:48]
|
||||||
|
_T_170[12] <= io.ap.sll @[el2_lib.scala 161:48]
|
||||||
|
_T_170[13] <= io.ap.sll @[el2_lib.scala 161:48]
|
||||||
|
_T_170[14] <= io.ap.sll @[el2_lib.scala 161:48]
|
||||||
|
_T_170[15] <= io.ap.sll @[el2_lib.scala 161:48]
|
||||||
|
_T_170[16] <= io.ap.sll @[el2_lib.scala 161:48]
|
||||||
|
_T_170[17] <= io.ap.sll @[el2_lib.scala 161:48]
|
||||||
|
_T_170[18] <= io.ap.sll @[el2_lib.scala 161:48]
|
||||||
|
_T_170[19] <= io.ap.sll @[el2_lib.scala 161:48]
|
||||||
|
_T_170[20] <= io.ap.sll @[el2_lib.scala 161:48]
|
||||||
|
_T_170[21] <= io.ap.sll @[el2_lib.scala 161:48]
|
||||||
|
_T_170[22] <= io.ap.sll @[el2_lib.scala 161:48]
|
||||||
|
_T_170[23] <= io.ap.sll @[el2_lib.scala 161:48]
|
||||||
|
_T_170[24] <= io.ap.sll @[el2_lib.scala 161:48]
|
||||||
|
_T_170[25] <= io.ap.sll @[el2_lib.scala 161:48]
|
||||||
|
_T_170[26] <= io.ap.sll @[el2_lib.scala 161:48]
|
||||||
|
_T_170[27] <= io.ap.sll @[el2_lib.scala 161:48]
|
||||||
|
_T_170[28] <= io.ap.sll @[el2_lib.scala 161:48]
|
||||||
|
_T_170[29] <= io.ap.sll @[el2_lib.scala 161:48]
|
||||||
|
_T_170[30] <= io.ap.sll @[el2_lib.scala 161:48]
|
||||||
|
node _T_171 = cat(_T_170[0], _T_170[1]) @[Cat.scala 29:58]
|
||||||
|
node _T_172 = cat(_T_171, _T_170[2]) @[Cat.scala 29:58]
|
||||||
|
node _T_173 = cat(_T_172, _T_170[3]) @[Cat.scala 29:58]
|
||||||
|
node _T_174 = cat(_T_173, _T_170[4]) @[Cat.scala 29:58]
|
||||||
|
node _T_175 = cat(_T_174, _T_170[5]) @[Cat.scala 29:58]
|
||||||
|
node _T_176 = cat(_T_175, _T_170[6]) @[Cat.scala 29:58]
|
||||||
|
node _T_177 = cat(_T_176, _T_170[7]) @[Cat.scala 29:58]
|
||||||
|
node _T_178 = cat(_T_177, _T_170[8]) @[Cat.scala 29:58]
|
||||||
|
node _T_179 = cat(_T_178, _T_170[9]) @[Cat.scala 29:58]
|
||||||
|
node _T_180 = cat(_T_179, _T_170[10]) @[Cat.scala 29:58]
|
||||||
|
node _T_181 = cat(_T_180, _T_170[11]) @[Cat.scala 29:58]
|
||||||
|
node _T_182 = cat(_T_181, _T_170[12]) @[Cat.scala 29:58]
|
||||||
|
node _T_183 = cat(_T_182, _T_170[13]) @[Cat.scala 29:58]
|
||||||
|
node _T_184 = cat(_T_183, _T_170[14]) @[Cat.scala 29:58]
|
||||||
|
node _T_185 = cat(_T_184, _T_170[15]) @[Cat.scala 29:58]
|
||||||
|
node _T_186 = cat(_T_185, _T_170[16]) @[Cat.scala 29:58]
|
||||||
|
node _T_187 = cat(_T_186, _T_170[17]) @[Cat.scala 29:58]
|
||||||
|
node _T_188 = cat(_T_187, _T_170[18]) @[Cat.scala 29:58]
|
||||||
|
node _T_189 = cat(_T_188, _T_170[19]) @[Cat.scala 29:58]
|
||||||
|
node _T_190 = cat(_T_189, _T_170[20]) @[Cat.scala 29:58]
|
||||||
|
node _T_191 = cat(_T_190, _T_170[21]) @[Cat.scala 29:58]
|
||||||
|
node _T_192 = cat(_T_191, _T_170[22]) @[Cat.scala 29:58]
|
||||||
|
node _T_193 = cat(_T_192, _T_170[23]) @[Cat.scala 29:58]
|
||||||
|
node _T_194 = cat(_T_193, _T_170[24]) @[Cat.scala 29:58]
|
||||||
|
node _T_195 = cat(_T_194, _T_170[25]) @[Cat.scala 29:58]
|
||||||
|
node _T_196 = cat(_T_195, _T_170[26]) @[Cat.scala 29:58]
|
||||||
|
node _T_197 = cat(_T_196, _T_170[27]) @[Cat.scala 29:58]
|
||||||
|
node _T_198 = cat(_T_197, _T_170[28]) @[Cat.scala 29:58]
|
||||||
|
node _T_199 = cat(_T_198, _T_170[29]) @[Cat.scala 29:58]
|
||||||
|
node _T_200 = cat(_T_199, _T_170[30]) @[Cat.scala 29:58]
|
||||||
|
node _T_201 = bits(io.a_in, 30, 0) @[el2_exu_alu_ctl.scala 69:99]
|
||||||
|
node _T_202 = and(_T_200, _T_201) @[el2_exu_alu_ctl.scala 69:90]
|
||||||
|
node _T_203 = or(_T_169, _T_202) @[el2_exu_alu_ctl.scala 69:68]
|
||||||
|
node _T_204 = asUInt(io.a_in) @[Cat.scala 29:58]
|
||||||
|
node _T_205 = cat(_T_203, _T_204) @[Cat.scala 29:58]
|
||||||
|
shift_extend <= _T_205 @[el2_exu_alu_ctl.scala 69:16]
|
||||||
|
wire shift_long : UInt<63>
|
||||||
|
shift_long <= UInt<1>("h00")
|
||||||
|
node _T_206 = bits(shift_amount, 4, 0) @[el2_exu_alu_ctl.scala 72:47]
|
||||||
|
node _T_207 = dshr(shift_extend, _T_206) @[el2_exu_alu_ctl.scala 72:32]
|
||||||
|
shift_long <= _T_207 @[el2_exu_alu_ctl.scala 72:14]
|
||||||
|
node _T_208 = bits(shift_long, 31, 0) @[el2_exu_alu_ctl.scala 74:27]
|
||||||
|
node _T_209 = bits(shift_mask, 31, 0) @[el2_exu_alu_ctl.scala 74:46]
|
||||||
|
node sout = and(_T_208, _T_209) @[el2_exu_alu_ctl.scala 74:34]
|
||||||
|
node _T_210 = or(io.ap.sll, io.ap.srl) @[el2_exu_alu_ctl.scala 77:41]
|
||||||
|
node sel_shift = or(_T_210, io.ap.sra) @[el2_exu_alu_ctl.scala 77:53]
|
||||||
|
node _T_211 = or(io.ap.add, io.ap.sub) @[el2_exu_alu_ctl.scala 78:41]
|
||||||
|
node _T_212 = not(io.ap.slt) @[el2_exu_alu_ctl.scala 78:56]
|
||||||
|
node sel_adder = and(_T_211, _T_212) @[el2_exu_alu_ctl.scala 78:54]
|
||||||
|
node _T_213 = or(io.ap.jal, io.pp_in.pcall) @[el2_exu_alu_ctl.scala 79:41]
|
||||||
|
node _T_214 = or(_T_213, io.pp_in.pja) @[el2_exu_alu_ctl.scala 79:58]
|
||||||
|
node sel_pc = or(_T_214, io.pp_in.pret) @[el2_exu_alu_ctl.scala 79:73]
|
||||||
|
node _T_215 = bits(io.ap.csr_imm, 0, 0) @[el2_exu_alu_ctl.scala 80:47]
|
||||||
|
node _T_216 = asSInt(io.b_in) @[el2_exu_alu_ctl.scala 80:63]
|
||||||
|
node csr_write_data = mux(_T_215, _T_216, io.a_in) @[el2_exu_alu_ctl.scala 80:32]
|
||||||
|
node slt_one = and(io.ap.slt, lt) @[el2_exu_alu_ctl.scala 82:40]
|
||||||
|
node _T_217 = cat(io.pc_in, UInt<1>("h00")) @[Cat.scala 29:58]
|
||||||
|
node _T_218 = cat(io.brimm_in, UInt<1>("h00")) @[Cat.scala 29:58]
|
||||||
|
node _T_219 = bits(_T_217, 12, 1) @[el2_lib.scala 206:24]
|
||||||
|
node _T_220 = bits(_T_218, 12, 1) @[el2_lib.scala 206:40]
|
||||||
|
node _T_221 = add(_T_219, _T_220) @[el2_lib.scala 206:31]
|
||||||
|
node _T_222 = bits(_T_217, 31, 13) @[el2_lib.scala 207:20]
|
||||||
|
node _T_223 = add(_T_222, UInt<1>("h01")) @[el2_lib.scala 207:27]
|
||||||
|
node _T_224 = tail(_T_223, 1) @[el2_lib.scala 207:27]
|
||||||
|
node _T_225 = bits(_T_217, 31, 13) @[el2_lib.scala 208:20]
|
||||||
|
node _T_226 = sub(_T_225, UInt<1>("h01")) @[el2_lib.scala 208:27]
|
||||||
|
node _T_227 = tail(_T_226, 1) @[el2_lib.scala 208:27]
|
||||||
|
node _T_228 = bits(_T_218, 12, 12) @[el2_lib.scala 209:22]
|
||||||
|
node _T_229 = bits(_T_221, 12, 12) @[el2_lib.scala 210:39]
|
||||||
|
node _T_230 = eq(_T_229, UInt<1>("h00")) @[el2_lib.scala 210:28]
|
||||||
|
node _T_231 = xor(_T_228, _T_230) @[el2_lib.scala 210:26]
|
||||||
|
node _T_232 = bits(_T_231, 0, 0) @[el2_lib.scala 210:64]
|
||||||
|
node _T_233 = bits(_T_217, 31, 13) @[el2_lib.scala 210:76]
|
||||||
|
node _T_234 = eq(_T_228, UInt<1>("h00")) @[el2_lib.scala 211:20]
|
||||||
|
node _T_235 = bits(_T_221, 12, 12) @[el2_lib.scala 211:39]
|
||||||
|
node _T_236 = and(_T_234, _T_235) @[el2_lib.scala 211:26]
|
||||||
|
node _T_237 = bits(_T_236, 0, 0) @[el2_lib.scala 211:64]
|
||||||
|
node _T_238 = bits(_T_221, 12, 12) @[el2_lib.scala 212:39]
|
||||||
|
node _T_239 = eq(_T_238, UInt<1>("h00")) @[el2_lib.scala 212:28]
|
||||||
|
node _T_240 = and(_T_228, _T_239) @[el2_lib.scala 212:26]
|
||||||
|
node _T_241 = bits(_T_240, 0, 0) @[el2_lib.scala 212:64]
|
||||||
|
node _T_242 = mux(_T_232, _T_233, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||||
|
node _T_243 = mux(_T_237, _T_224, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||||
|
node _T_244 = mux(_T_241, _T_227, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||||
|
node _T_245 = or(_T_242, _T_243) @[Mux.scala 27:72]
|
||||||
|
node _T_246 = or(_T_245, _T_244) @[Mux.scala 27:72]
|
||||||
|
wire _T_247 : UInt<19> @[Mux.scala 27:72]
|
||||||
|
_T_247 <= _T_246 @[Mux.scala 27:72]
|
||||||
|
node _T_248 = bits(_T_221, 11, 0) @[el2_lib.scala 212:94]
|
||||||
|
node _T_249 = cat(_T_247, _T_248) @[Cat.scala 29:58]
|
||||||
|
node pcout = cat(_T_249, UInt<1>("h00")) @[Cat.scala 29:58]
|
||||||
|
node _T_250 = bits(lout, 31, 0) @[el2_exu_alu_ctl.scala 88:24]
|
||||||
|
node _T_251 = cat(UInt<31>("h00"), slt_one) @[Cat.scala 29:58]
|
||||||
|
node _T_252 = or(_T_250, _T_251) @[el2_exu_alu_ctl.scala 88:31]
|
||||||
|
node _T_253 = bits(sel_shift, 0, 0) @[el2_exu_alu_ctl.scala 89:15]
|
||||||
|
node _T_254 = bits(sout, 31, 0) @[el2_exu_alu_ctl.scala 89:41]
|
||||||
|
node _T_255 = bits(sel_adder, 0, 0) @[el2_exu_alu_ctl.scala 90:15]
|
||||||
|
node _T_256 = bits(aout, 31, 0) @[el2_exu_alu_ctl.scala 90:41]
|
||||||
|
node _T_257 = bits(sel_pc, 0, 0) @[el2_exu_alu_ctl.scala 91:12]
|
||||||
|
node _T_258 = bits(io.ap.csr_write, 0, 0) @[el2_exu_alu_ctl.scala 92:21]
|
||||||
|
node _T_259 = bits(csr_write_data, 31, 0) @[el2_exu_alu_ctl.scala 92:51]
|
||||||
|
node _T_260 = mux(_T_253, _T_254, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||||
|
node _T_261 = mux(_T_255, _T_256, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||||
|
node _T_262 = mux(_T_257, pcout, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||||
|
node _T_263 = mux(_T_258, _T_259, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||||
|
node _T_264 = or(_T_260, _T_261) @[Mux.scala 27:72]
|
||||||
|
node _T_265 = or(_T_264, _T_262) @[Mux.scala 27:72]
|
||||||
|
node _T_266 = or(_T_265, _T_263) @[Mux.scala 27:72]
|
||||||
|
wire _T_267 : UInt<32> @[Mux.scala 27:72]
|
||||||
|
_T_267 <= _T_266 @[Mux.scala 27:72]
|
||||||
|
node _T_268 = or(_T_252, _T_267) @[el2_exu_alu_ctl.scala 88:56]
|
||||||
|
result <= _T_268 @[el2_exu_alu_ctl.scala 88:16]
|
||||||
|
node _T_269 = or(io.ap.jal, io.pp_in.pcall) @[el2_exu_alu_ctl.scala 96:45]
|
||||||
|
node _T_270 = or(_T_269, io.pp_in.pja) @[el2_exu_alu_ctl.scala 97:20]
|
||||||
|
node any_jal = or(_T_270, io.pp_in.pret) @[el2_exu_alu_ctl.scala 98:20]
|
||||||
|
node _T_271 = and(io.ap.beq, eq) @[el2_exu_alu_ctl.scala 101:40]
|
||||||
|
node _T_272 = and(io.ap.bne, ne) @[el2_exu_alu_ctl.scala 101:59]
|
||||||
|
node _T_273 = or(_T_271, _T_272) @[el2_exu_alu_ctl.scala 101:46]
|
||||||
|
node _T_274 = and(io.ap.blt, lt) @[el2_exu_alu_ctl.scala 101:85]
|
||||||
|
node _T_275 = or(_T_273, _T_274) @[el2_exu_alu_ctl.scala 101:72]
|
||||||
|
node _T_276 = and(io.ap.bge, ge) @[el2_exu_alu_ctl.scala 101:104]
|
||||||
|
node _T_277 = or(_T_275, _T_276) @[el2_exu_alu_ctl.scala 101:91]
|
||||||
|
node actual_taken = or(_T_277, any_jal) @[el2_exu_alu_ctl.scala 101:110]
|
||||||
|
node _T_278 = and(io.valid_in, io.ap.predict_nt) @[el2_exu_alu_ctl.scala 106:42]
|
||||||
|
node _T_279 = eq(actual_taken, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 106:63]
|
||||||
|
node _T_280 = and(_T_278, _T_279) @[el2_exu_alu_ctl.scala 106:61]
|
||||||
|
node _T_281 = eq(any_jal, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 106:79]
|
||||||
|
node _T_282 = and(_T_280, _T_281) @[el2_exu_alu_ctl.scala 106:77]
|
||||||
|
node _T_283 = and(io.valid_in, io.ap.predict_t) @[el2_exu_alu_ctl.scala 106:104]
|
||||||
|
node _T_284 = and(_T_283, actual_taken) @[el2_exu_alu_ctl.scala 106:123]
|
||||||
|
node _T_285 = eq(any_jal, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 106:141]
|
||||||
|
node _T_286 = and(_T_284, _T_285) @[el2_exu_alu_ctl.scala 106:139]
|
||||||
|
node _T_287 = or(_T_282, _T_286) @[el2_exu_alu_ctl.scala 106:89]
|
||||||
|
io.pred_correct_out <= _T_287 @[el2_exu_alu_ctl.scala 106:26]
|
||||||
|
node _T_288 = bits(any_jal, 0, 0) @[el2_exu_alu_ctl.scala 108:37]
|
||||||
|
node _T_289 = bits(aout, 31, 1) @[el2_exu_alu_ctl.scala 108:49]
|
||||||
|
node _T_290 = bits(pcout, 31, 1) @[el2_exu_alu_ctl.scala 108:62]
|
||||||
|
node _T_291 = mux(_T_288, _T_289, _T_290) @[el2_exu_alu_ctl.scala 108:28]
|
||||||
|
io.flush_path_out <= _T_291 @[el2_exu_alu_ctl.scala 108:22]
|
||||||
|
node _T_292 = eq(actual_taken, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 111:47]
|
||||||
|
node _T_293 = and(io.ap.predict_t, _T_292) @[el2_exu_alu_ctl.scala 111:45]
|
||||||
|
node _T_294 = and(io.ap.predict_nt, actual_taken) @[el2_exu_alu_ctl.scala 111:82]
|
||||||
|
node cond_mispredict = or(_T_293, _T_294) @[el2_exu_alu_ctl.scala 111:62]
|
||||||
|
node _T_295 = bits(aout, 31, 1) @[el2_exu_alu_ctl.scala 114:70]
|
||||||
|
node _T_296 = neq(io.pp_in.prett, _T_295) @[el2_exu_alu_ctl.scala 114:62]
|
||||||
|
node target_mispredict = and(io.pp_in.pret, _T_296) @[el2_exu_alu_ctl.scala 114:44]
|
||||||
|
node _T_297 = or(io.ap.jal, cond_mispredict) @[el2_exu_alu_ctl.scala 116:42]
|
||||||
|
node _T_298 = or(_T_297, target_mispredict) @[el2_exu_alu_ctl.scala 116:60]
|
||||||
|
node _T_299 = and(_T_298, io.valid_in) @[el2_exu_alu_ctl.scala 116:81]
|
||||||
|
node _T_300 = eq(io.flush_upper_x, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 116:97]
|
||||||
|
node _T_301 = and(_T_299, _T_300) @[el2_exu_alu_ctl.scala 116:95]
|
||||||
|
node _T_302 = eq(io.flush_lower_r, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 116:119]
|
||||||
|
node _T_303 = and(_T_301, _T_302) @[el2_exu_alu_ctl.scala 116:117]
|
||||||
|
io.flush_upper_out <= _T_303 @[el2_exu_alu_ctl.scala 116:26]
|
||||||
|
node _T_304 = or(io.ap.jal, cond_mispredict) @[el2_exu_alu_ctl.scala 118:42]
|
||||||
|
node _T_305 = or(_T_304, target_mispredict) @[el2_exu_alu_ctl.scala 118:60]
|
||||||
|
node _T_306 = and(_T_305, io.valid_in) @[el2_exu_alu_ctl.scala 118:81]
|
||||||
|
node _T_307 = eq(io.flush_upper_x, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 118:97]
|
||||||
|
node _T_308 = and(_T_306, _T_307) @[el2_exu_alu_ctl.scala 118:95]
|
||||||
|
node _T_309 = or(_T_308, io.flush_lower_r) @[el2_exu_alu_ctl.scala 118:117]
|
||||||
|
io.flush_final_out <= _T_309 @[el2_exu_alu_ctl.scala 118:26]
|
||||||
|
wire newhist : UInt<2>
|
||||||
|
newhist <= UInt<1>("h00")
|
||||||
|
node _T_310 = bits(io.pp_in.hist, 1, 1) @[el2_exu_alu_ctl.scala 122:35]
|
||||||
|
node _T_311 = bits(io.pp_in.hist, 0, 0) @[el2_exu_alu_ctl.scala 122:55]
|
||||||
|
node _T_312 = and(_T_310, _T_311) @[el2_exu_alu_ctl.scala 122:39]
|
||||||
|
node _T_313 = bits(io.pp_in.hist, 0, 0) @[el2_exu_alu_ctl.scala 122:77]
|
||||||
|
node _T_314 = not(_T_313) @[el2_exu_alu_ctl.scala 122:63]
|
||||||
|
node _T_315 = and(_T_314, actual_taken) @[el2_exu_alu_ctl.scala 122:81]
|
||||||
|
node _T_316 = or(_T_312, _T_315) @[el2_exu_alu_ctl.scala 122:60]
|
||||||
|
node _T_317 = bits(io.pp_in.hist, 1, 1) @[el2_exu_alu_ctl.scala 123:20]
|
||||||
|
node _T_318 = not(_T_317) @[el2_exu_alu_ctl.scala 123:6]
|
||||||
|
node _T_319 = not(actual_taken) @[el2_exu_alu_ctl.scala 123:26]
|
||||||
|
node _T_320 = and(_T_318, _T_319) @[el2_exu_alu_ctl.scala 123:24]
|
||||||
|
node _T_321 = bits(io.pp_in.hist, 1, 1) @[el2_exu_alu_ctl.scala 123:58]
|
||||||
|
node _T_322 = and(_T_321, actual_taken) @[el2_exu_alu_ctl.scala 123:62]
|
||||||
|
node _T_323 = or(_T_320, _T_322) @[el2_exu_alu_ctl.scala 123:42]
|
||||||
|
node _T_324 = cat(_T_316, _T_323) @[Cat.scala 29:58]
|
||||||
|
newhist <= _T_324 @[el2_exu_alu_ctl.scala 122:14]
|
||||||
|
io.predict_p_out.way <= io.pp_in.way @[el2_exu_alu_ctl.scala 125:30]
|
||||||
|
io.predict_p_out.pja <= io.pp_in.pja @[el2_exu_alu_ctl.scala 125:30]
|
||||||
|
io.predict_p_out.pret <= io.pp_in.pret @[el2_exu_alu_ctl.scala 125:30]
|
||||||
|
io.predict_p_out.pcall <= io.pp_in.pcall @[el2_exu_alu_ctl.scala 125:30]
|
||||||
|
io.predict_p_out.prett <= io.pp_in.prett @[el2_exu_alu_ctl.scala 125:30]
|
||||||
|
io.predict_p_out.br_start_error <= io.pp_in.br_start_error @[el2_exu_alu_ctl.scala 125:30]
|
||||||
|
io.predict_p_out.br_error <= io.pp_in.br_error @[el2_exu_alu_ctl.scala 125:30]
|
||||||
|
io.predict_p_out.valid <= io.pp_in.valid @[el2_exu_alu_ctl.scala 125:30]
|
||||||
|
io.predict_p_out.toffset <= io.pp_in.toffset @[el2_exu_alu_ctl.scala 125:30]
|
||||||
|
io.predict_p_out.hist <= io.pp_in.hist @[el2_exu_alu_ctl.scala 125:30]
|
||||||
|
io.predict_p_out.pc4 <= io.pp_in.pc4 @[el2_exu_alu_ctl.scala 125:30]
|
||||||
|
io.predict_p_out.boffset <= io.pp_in.boffset @[el2_exu_alu_ctl.scala 125:30]
|
||||||
|
io.predict_p_out.ataken <= io.pp_in.ataken @[el2_exu_alu_ctl.scala 125:30]
|
||||||
|
io.predict_p_out.misp <= io.pp_in.misp @[el2_exu_alu_ctl.scala 125:30]
|
||||||
|
node _T_325 = not(io.flush_upper_x) @[el2_exu_alu_ctl.scala 126:33]
|
||||||
|
node _T_326 = not(io.flush_lower_r) @[el2_exu_alu_ctl.scala 126:53]
|
||||||
|
node _T_327 = and(_T_325, _T_326) @[el2_exu_alu_ctl.scala 126:51]
|
||||||
|
node _T_328 = or(cond_mispredict, target_mispredict) @[el2_exu_alu_ctl.scala 126:90]
|
||||||
|
node _T_329 = and(_T_327, _T_328) @[el2_exu_alu_ctl.scala 126:71]
|
||||||
|
io.predict_p_out.misp <= _T_329 @[el2_exu_alu_ctl.scala 126:30]
|
||||||
|
io.predict_p_out.ataken <= actual_taken @[el2_exu_alu_ctl.scala 127:30]
|
||||||
|
io.predict_p_out.hist <= newhist @[el2_exu_alu_ctl.scala 128:30]
|
||||||
|
|
||||||
|
|
@ -0,0 +1,347 @@
|
||||||
|
module rvclkhdr(
|
||||||
|
output io_l1clk,
|
||||||
|
input io_clk,
|
||||||
|
input io_en,
|
||||||
|
input io_scan_mode
|
||||||
|
);
|
||||||
|
wire clkhdr_Q; // @[el2_lib.scala 465:26]
|
||||||
|
wire clkhdr_CK; // @[el2_lib.scala 465:26]
|
||||||
|
wire clkhdr_EN; // @[el2_lib.scala 465:26]
|
||||||
|
wire clkhdr_SE; // @[el2_lib.scala 465:26]
|
||||||
|
TEC_RV_ICG clkhdr ( // @[el2_lib.scala 465:26]
|
||||||
|
.Q(clkhdr_Q),
|
||||||
|
.CK(clkhdr_CK),
|
||||||
|
.EN(clkhdr_EN),
|
||||||
|
.SE(clkhdr_SE)
|
||||||
|
);
|
||||||
|
assign io_l1clk = clkhdr_Q; // @[el2_lib.scala 466:14]
|
||||||
|
assign clkhdr_CK = io_clk; // @[el2_lib.scala 467:18]
|
||||||
|
assign clkhdr_EN = io_en; // @[el2_lib.scala 468:18]
|
||||||
|
assign clkhdr_SE = io_scan_mode; // @[el2_lib.scala 469:18]
|
||||||
|
endmodule
|
||||||
|
module el2_exu_alu_ctl(
|
||||||
|
input clock,
|
||||||
|
input reset,
|
||||||
|
input io_scan_mode,
|
||||||
|
input io_flush_upper_x,
|
||||||
|
input io_flush_lower_r,
|
||||||
|
input io_enable,
|
||||||
|
input io_valid_in,
|
||||||
|
input io_ap_land,
|
||||||
|
input io_ap_lor,
|
||||||
|
input io_ap_lxor,
|
||||||
|
input io_ap_sll,
|
||||||
|
input io_ap_srl,
|
||||||
|
input io_ap_sra,
|
||||||
|
input io_ap_beq,
|
||||||
|
input io_ap_bne,
|
||||||
|
input io_ap_blt,
|
||||||
|
input io_ap_bge,
|
||||||
|
input io_ap_add,
|
||||||
|
input io_ap_sub,
|
||||||
|
input io_ap_slt,
|
||||||
|
input io_ap_unsign,
|
||||||
|
input io_ap_jal,
|
||||||
|
input io_ap_predict_t,
|
||||||
|
input io_ap_predict_nt,
|
||||||
|
input io_ap_csr_write,
|
||||||
|
input io_ap_csr_imm,
|
||||||
|
input io_csr_ren_in,
|
||||||
|
input [31:0] io_a_in,
|
||||||
|
input [31:0] io_b_in,
|
||||||
|
input [30:0] io_pc_in,
|
||||||
|
input io_pp_in_misp,
|
||||||
|
input io_pp_in_ataken,
|
||||||
|
input io_pp_in_boffset,
|
||||||
|
input io_pp_in_pc4,
|
||||||
|
input [1:0] io_pp_in_hist,
|
||||||
|
input [11:0] io_pp_in_toffset,
|
||||||
|
input io_pp_in_valid,
|
||||||
|
input io_pp_in_br_error,
|
||||||
|
input io_pp_in_br_start_error,
|
||||||
|
input [30:0] io_pp_in_prett,
|
||||||
|
input io_pp_in_pcall,
|
||||||
|
input io_pp_in_pret,
|
||||||
|
input io_pp_in_pja,
|
||||||
|
input io_pp_in_way,
|
||||||
|
input [11:0] io_brimm_in,
|
||||||
|
output [31:0] io_result_ff,
|
||||||
|
output io_flush_upper_out,
|
||||||
|
output io_flush_final_out,
|
||||||
|
output [30:0] io_flush_path_out,
|
||||||
|
output [30:0] io_pc_ff,
|
||||||
|
output io_pred_correct_out,
|
||||||
|
output io_predict_p_out_misp,
|
||||||
|
output io_predict_p_out_ataken,
|
||||||
|
output io_predict_p_out_boffset,
|
||||||
|
output io_predict_p_out_pc4,
|
||||||
|
output [1:0] io_predict_p_out_hist,
|
||||||
|
output [11:0] io_predict_p_out_toffset,
|
||||||
|
output io_predict_p_out_valid,
|
||||||
|
output io_predict_p_out_br_error,
|
||||||
|
output io_predict_p_out_br_start_error,
|
||||||
|
output [30:0] io_predict_p_out_prett,
|
||||||
|
output io_predict_p_out_pcall,
|
||||||
|
output io_predict_p_out_pret,
|
||||||
|
output io_predict_p_out_pja,
|
||||||
|
output io_predict_p_out_way
|
||||||
|
);
|
||||||
|
`ifdef RANDOMIZE_REG_INIT
|
||||||
|
reg [31:0] _RAND_0;
|
||||||
|
reg [31:0] _RAND_1;
|
||||||
|
`endif // RANDOMIZE_REG_INIT
|
||||||
|
wire rvclkhdr_io_l1clk; // @[el2_lib.scala 485:23]
|
||||||
|
wire rvclkhdr_io_clk; // @[el2_lib.scala 485:23]
|
||||||
|
wire rvclkhdr_io_en; // @[el2_lib.scala 485:23]
|
||||||
|
wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 485:23]
|
||||||
|
wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 485:23]
|
||||||
|
wire rvclkhdr_1_io_clk; // @[el2_lib.scala 485:23]
|
||||||
|
wire rvclkhdr_1_io_en; // @[el2_lib.scala 485:23]
|
||||||
|
wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 485:23]
|
||||||
|
reg [30:0] _T_1; // @[el2_lib.scala 491:16]
|
||||||
|
reg [31:0] _T_3; // @[el2_lib.scala 491:16]
|
||||||
|
wire [31:0] _T_5 = ~io_b_in; // @[el2_exu_alu_ctl.scala 39:37]
|
||||||
|
wire [31:0] bm = io_ap_sub ? _T_5 : io_b_in; // @[el2_exu_alu_ctl.scala 39:17]
|
||||||
|
wire [32:0] _T_8 = {1'h0,io_a_in}; // @[Cat.scala 29:58]
|
||||||
|
wire [32:0] _T_10 = {1'h0,_T_5}; // @[Cat.scala 29:58]
|
||||||
|
wire [32:0] _T_12 = _T_8 + _T_10; // @[el2_exu_alu_ctl.scala 42:55]
|
||||||
|
wire [32:0] _T_13 = {32'h0,io_ap_sub}; // @[Cat.scala 29:58]
|
||||||
|
wire [32:0] _T_15 = _T_12 + _T_13; // @[el2_exu_alu_ctl.scala 42:80]
|
||||||
|
wire [32:0] _T_18 = {1'h0,io_b_in}; // @[Cat.scala 29:58]
|
||||||
|
wire [32:0] _T_20 = _T_8 + _T_18; // @[el2_exu_alu_ctl.scala 42:132]
|
||||||
|
wire [32:0] _T_23 = _T_20 + _T_13; // @[el2_exu_alu_ctl.scala 42:157]
|
||||||
|
wire [32:0] aout = io_ap_sub ? _T_15 : _T_23; // @[el2_exu_alu_ctl.scala 42:14]
|
||||||
|
wire cout = aout[32]; // @[el2_exu_alu_ctl.scala 43:18]
|
||||||
|
wire _T_26 = ~io_a_in[31]; // @[el2_exu_alu_ctl.scala 45:14]
|
||||||
|
wire _T_28 = ~bm[31]; // @[el2_exu_alu_ctl.scala 45:29]
|
||||||
|
wire _T_29 = _T_26 & _T_28; // @[el2_exu_alu_ctl.scala 45:27]
|
||||||
|
wire _T_31 = _T_29 & aout[31]; // @[el2_exu_alu_ctl.scala 45:37]
|
||||||
|
wire _T_34 = io_a_in[31] & bm[31]; // @[el2_exu_alu_ctl.scala 45:66]
|
||||||
|
wire _T_36 = ~aout[31]; // @[el2_exu_alu_ctl.scala 45:78]
|
||||||
|
wire _T_37 = _T_34 & _T_36; // @[el2_exu_alu_ctl.scala 45:76]
|
||||||
|
wire ov = _T_31 | _T_37; // @[el2_exu_alu_ctl.scala 45:50]
|
||||||
|
wire eq = $signed(io_a_in) == $signed(io_b_in); // @[el2_exu_alu_ctl.scala 47:38]
|
||||||
|
wire ne = ~eq; // @[el2_exu_alu_ctl.scala 48:29]
|
||||||
|
wire _T_39 = ~io_ap_unsign; // @[el2_exu_alu_ctl.scala 50:30]
|
||||||
|
wire _T_40 = aout[31] ^ ov; // @[el2_exu_alu_ctl.scala 50:51]
|
||||||
|
wire _T_41 = _T_39 & _T_40; // @[el2_exu_alu_ctl.scala 50:44]
|
||||||
|
wire _T_42 = ~cout; // @[el2_exu_alu_ctl.scala 50:78]
|
||||||
|
wire _T_43 = io_ap_unsign & _T_42; // @[el2_exu_alu_ctl.scala 50:76]
|
||||||
|
wire lt = _T_41 | _T_43; // @[el2_exu_alu_ctl.scala 50:58]
|
||||||
|
wire ge = ~lt; // @[el2_exu_alu_ctl.scala 51:29]
|
||||||
|
wire [31:0] _T_63 = $signed(io_a_in) & $signed(io_b_in); // @[Mux.scala 27:72]
|
||||||
|
wire [31:0] _T_66 = $signed(io_a_in) | $signed(io_b_in); // @[Mux.scala 27:72]
|
||||||
|
wire [31:0] _T_69 = $signed(io_a_in) ^ $signed(io_b_in); // @[Mux.scala 27:72]
|
||||||
|
wire [31:0] _T_70 = io_csr_ren_in ? $signed(io_b_in) : $signed(32'sh0); // @[Mux.scala 27:72]
|
||||||
|
wire [31:0] _T_71 = io_ap_land ? $signed(_T_63) : $signed(32'sh0); // @[Mux.scala 27:72]
|
||||||
|
wire [31:0] _T_72 = io_ap_lor ? $signed(_T_66) : $signed(32'sh0); // @[Mux.scala 27:72]
|
||||||
|
wire [31:0] _T_73 = io_ap_lxor ? $signed(_T_69) : $signed(32'sh0); // @[Mux.scala 27:72]
|
||||||
|
wire [31:0] _T_75 = $signed(_T_70) | $signed(_T_71); // @[Mux.scala 27:72]
|
||||||
|
wire [31:0] _T_77 = $signed(_T_75) | $signed(_T_72); // @[Mux.scala 27:72]
|
||||||
|
wire [5:0] _T_84 = {1'h0,io_b_in[4:0]}; // @[Cat.scala 29:58]
|
||||||
|
wire [5:0] _T_86 = 6'h20 - _T_84; // @[el2_exu_alu_ctl.scala 61:38]
|
||||||
|
wire [5:0] _T_93 = io_ap_sll ? _T_86 : 6'h0; // @[Mux.scala 27:72]
|
||||||
|
wire [5:0] _T_94 = io_ap_srl ? _T_84 : 6'h0; // @[Mux.scala 27:72]
|
||||||
|
wire [5:0] _T_95 = io_ap_sra ? _T_84 : 6'h0; // @[Mux.scala 27:72]
|
||||||
|
wire [5:0] _T_96 = _T_93 | _T_94; // @[Mux.scala 27:72]
|
||||||
|
wire [5:0] shift_amount = _T_96 | _T_95; // @[Mux.scala 27:72]
|
||||||
|
wire [4:0] _T_102 = {io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll}; // @[Cat.scala 29:58]
|
||||||
|
wire [4:0] _T_104 = _T_102 & io_b_in[4:0]; // @[el2_exu_alu_ctl.scala 66:61]
|
||||||
|
wire [62:0] _T_105 = 63'hffffffff << _T_104; // @[el2_exu_alu_ctl.scala 66:39]
|
||||||
|
wire [9:0] _T_115 = {io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra}; // @[Cat.scala 29:58]
|
||||||
|
wire [18:0] _T_124 = {_T_115,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra}; // @[Cat.scala 29:58]
|
||||||
|
wire [27:0] _T_133 = {_T_124,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra}; // @[Cat.scala 29:58]
|
||||||
|
wire [30:0] _T_136 = {_T_133,io_ap_sra,io_ap_sra,io_ap_sra}; // @[Cat.scala 29:58]
|
||||||
|
wire [9:0] _T_147 = {io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31]}; // @[Cat.scala 29:58]
|
||||||
|
wire [18:0] _T_156 = {_T_147,io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31]}; // @[Cat.scala 29:58]
|
||||||
|
wire [27:0] _T_165 = {_T_156,io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31]}; // @[Cat.scala 29:58]
|
||||||
|
wire [30:0] _T_168 = {_T_165,io_a_in[31],io_a_in[31],io_a_in[31]}; // @[Cat.scala 29:58]
|
||||||
|
wire [30:0] _T_169 = _T_136 & _T_168; // @[el2_exu_alu_ctl.scala 69:44]
|
||||||
|
wire [9:0] _T_179 = {io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll}; // @[Cat.scala 29:58]
|
||||||
|
wire [18:0] _T_188 = {_T_179,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll}; // @[Cat.scala 29:58]
|
||||||
|
wire [27:0] _T_197 = {_T_188,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll}; // @[Cat.scala 29:58]
|
||||||
|
wire [30:0] _T_200 = {_T_197,io_ap_sll,io_ap_sll,io_ap_sll}; // @[Cat.scala 29:58]
|
||||||
|
wire [30:0] _T_202 = _T_200 & io_a_in[30:0]; // @[el2_exu_alu_ctl.scala 69:90]
|
||||||
|
wire [30:0] _T_203 = _T_169 | _T_202; // @[el2_exu_alu_ctl.scala 69:68]
|
||||||
|
wire [62:0] shift_extend = {_T_203,io_a_in}; // @[Cat.scala 29:58]
|
||||||
|
wire [62:0] shift_long = shift_extend >> shift_amount[4:0]; // @[el2_exu_alu_ctl.scala 72:32]
|
||||||
|
wire [31:0] shift_mask = _T_105[31:0]; // @[el2_exu_alu_ctl.scala 66:14]
|
||||||
|
wire [31:0] sout = shift_long[31:0] & shift_mask; // @[el2_exu_alu_ctl.scala 74:34]
|
||||||
|
wire _T_210 = io_ap_sll | io_ap_srl; // @[el2_exu_alu_ctl.scala 77:41]
|
||||||
|
wire sel_shift = _T_210 | io_ap_sra; // @[el2_exu_alu_ctl.scala 77:53]
|
||||||
|
wire _T_211 = io_ap_add | io_ap_sub; // @[el2_exu_alu_ctl.scala 78:41]
|
||||||
|
wire _T_212 = ~io_ap_slt; // @[el2_exu_alu_ctl.scala 78:56]
|
||||||
|
wire sel_adder = _T_211 & _T_212; // @[el2_exu_alu_ctl.scala 78:54]
|
||||||
|
wire _T_213 = io_ap_jal | io_pp_in_pcall; // @[el2_exu_alu_ctl.scala 79:41]
|
||||||
|
wire _T_214 = _T_213 | io_pp_in_pja; // @[el2_exu_alu_ctl.scala 79:58]
|
||||||
|
wire sel_pc = _T_214 | io_pp_in_pret; // @[el2_exu_alu_ctl.scala 79:73]
|
||||||
|
wire slt_one = io_ap_slt & lt; // @[el2_exu_alu_ctl.scala 82:40]
|
||||||
|
wire [31:0] _T_217 = {io_pc_in,1'h0}; // @[Cat.scala 29:58]
|
||||||
|
wire [12:0] _T_218 = {io_brimm_in,1'h0}; // @[Cat.scala 29:58]
|
||||||
|
wire [12:0] _T_221 = _T_217[12:1] + _T_218[12:1]; // @[el2_lib.scala 206:31]
|
||||||
|
wire [18:0] _T_224 = _T_217[31:13] + 19'h1; // @[el2_lib.scala 207:27]
|
||||||
|
wire [18:0] _T_227 = _T_217[31:13] - 19'h1; // @[el2_lib.scala 208:27]
|
||||||
|
wire _T_230 = ~_T_221[12]; // @[el2_lib.scala 210:28]
|
||||||
|
wire _T_231 = _T_218[12] ^ _T_230; // @[el2_lib.scala 210:26]
|
||||||
|
wire _T_234 = ~_T_218[12]; // @[el2_lib.scala 211:20]
|
||||||
|
wire _T_236 = _T_234 & _T_221[12]; // @[el2_lib.scala 211:26]
|
||||||
|
wire _T_240 = _T_218[12] & _T_230; // @[el2_lib.scala 212:26]
|
||||||
|
wire [18:0] _T_242 = _T_231 ? _T_217[31:13] : 19'h0; // @[Mux.scala 27:72]
|
||||||
|
wire [18:0] _T_243 = _T_236 ? _T_224 : 19'h0; // @[Mux.scala 27:72]
|
||||||
|
wire [18:0] _T_244 = _T_240 ? _T_227 : 19'h0; // @[Mux.scala 27:72]
|
||||||
|
wire [18:0] _T_245 = _T_242 | _T_243; // @[Mux.scala 27:72]
|
||||||
|
wire [18:0] _T_246 = _T_245 | _T_244; // @[Mux.scala 27:72]
|
||||||
|
wire [31:0] pcout = {_T_246,_T_221[11:0],1'h0}; // @[Cat.scala 29:58]
|
||||||
|
wire [31:0] _T_250 = $signed(_T_77) | $signed(_T_73); // @[el2_exu_alu_ctl.scala 88:24]
|
||||||
|
wire [31:0] _T_251 = {31'h0,slt_one}; // @[Cat.scala 29:58]
|
||||||
|
wire [31:0] _T_252 = _T_250 | _T_251; // @[el2_exu_alu_ctl.scala 88:31]
|
||||||
|
wire [31:0] _T_259 = io_ap_csr_imm ? $signed(io_b_in) : $signed(io_a_in); // @[el2_exu_alu_ctl.scala 92:51]
|
||||||
|
wire [31:0] _T_260 = sel_shift ? sout : 32'h0; // @[Mux.scala 27:72]
|
||||||
|
wire [31:0] _T_261 = sel_adder ? aout[31:0] : 32'h0; // @[Mux.scala 27:72]
|
||||||
|
wire [31:0] _T_262 = sel_pc ? pcout : 32'h0; // @[Mux.scala 27:72]
|
||||||
|
wire [31:0] _T_263 = io_ap_csr_write ? _T_259 : 32'h0; // @[Mux.scala 27:72]
|
||||||
|
wire [31:0] _T_264 = _T_260 | _T_261; // @[Mux.scala 27:72]
|
||||||
|
wire [31:0] _T_265 = _T_264 | _T_262; // @[Mux.scala 27:72]
|
||||||
|
wire [31:0] _T_266 = _T_265 | _T_263; // @[Mux.scala 27:72]
|
||||||
|
wire _T_271 = io_ap_beq & eq; // @[el2_exu_alu_ctl.scala 101:40]
|
||||||
|
wire _T_272 = io_ap_bne & ne; // @[el2_exu_alu_ctl.scala 101:59]
|
||||||
|
wire _T_273 = _T_271 | _T_272; // @[el2_exu_alu_ctl.scala 101:46]
|
||||||
|
wire _T_274 = io_ap_blt & lt; // @[el2_exu_alu_ctl.scala 101:85]
|
||||||
|
wire _T_275 = _T_273 | _T_274; // @[el2_exu_alu_ctl.scala 101:72]
|
||||||
|
wire _T_276 = io_ap_bge & ge; // @[el2_exu_alu_ctl.scala 101:104]
|
||||||
|
wire _T_277 = _T_275 | _T_276; // @[el2_exu_alu_ctl.scala 101:91]
|
||||||
|
wire actual_taken = _T_277 | sel_pc; // @[el2_exu_alu_ctl.scala 101:110]
|
||||||
|
wire _T_278 = io_valid_in & io_ap_predict_nt; // @[el2_exu_alu_ctl.scala 106:42]
|
||||||
|
wire _T_279 = ~actual_taken; // @[el2_exu_alu_ctl.scala 106:63]
|
||||||
|
wire _T_280 = _T_278 & _T_279; // @[el2_exu_alu_ctl.scala 106:61]
|
||||||
|
wire _T_281 = ~sel_pc; // @[el2_exu_alu_ctl.scala 106:79]
|
||||||
|
wire _T_282 = _T_280 & _T_281; // @[el2_exu_alu_ctl.scala 106:77]
|
||||||
|
wire _T_283 = io_valid_in & io_ap_predict_t; // @[el2_exu_alu_ctl.scala 106:104]
|
||||||
|
wire _T_284 = _T_283 & actual_taken; // @[el2_exu_alu_ctl.scala 106:123]
|
||||||
|
wire _T_286 = _T_284 & _T_281; // @[el2_exu_alu_ctl.scala 106:139]
|
||||||
|
wire _T_293 = io_ap_predict_t & _T_279; // @[el2_exu_alu_ctl.scala 111:45]
|
||||||
|
wire _T_294 = io_ap_predict_nt & actual_taken; // @[el2_exu_alu_ctl.scala 111:82]
|
||||||
|
wire cond_mispredict = _T_293 | _T_294; // @[el2_exu_alu_ctl.scala 111:62]
|
||||||
|
wire _T_296 = io_pp_in_prett != aout[31:1]; // @[el2_exu_alu_ctl.scala 114:62]
|
||||||
|
wire target_mispredict = io_pp_in_pret & _T_296; // @[el2_exu_alu_ctl.scala 114:44]
|
||||||
|
wire _T_297 = io_ap_jal | cond_mispredict; // @[el2_exu_alu_ctl.scala 116:42]
|
||||||
|
wire _T_298 = _T_297 | target_mispredict; // @[el2_exu_alu_ctl.scala 116:60]
|
||||||
|
wire _T_299 = _T_298 & io_valid_in; // @[el2_exu_alu_ctl.scala 116:81]
|
||||||
|
wire _T_300 = ~io_flush_upper_x; // @[el2_exu_alu_ctl.scala 116:97]
|
||||||
|
wire _T_301 = _T_299 & _T_300; // @[el2_exu_alu_ctl.scala 116:95]
|
||||||
|
wire _T_302 = ~io_flush_lower_r; // @[el2_exu_alu_ctl.scala 116:119]
|
||||||
|
wire _T_312 = io_pp_in_hist[1] & io_pp_in_hist[0]; // @[el2_exu_alu_ctl.scala 122:39]
|
||||||
|
wire _T_314 = ~io_pp_in_hist[0]; // @[el2_exu_alu_ctl.scala 122:63]
|
||||||
|
wire _T_315 = _T_314 & actual_taken; // @[el2_exu_alu_ctl.scala 122:81]
|
||||||
|
wire _T_316 = _T_312 | _T_315; // @[el2_exu_alu_ctl.scala 122:60]
|
||||||
|
wire _T_318 = ~io_pp_in_hist[1]; // @[el2_exu_alu_ctl.scala 123:6]
|
||||||
|
wire _T_320 = _T_318 & _T_279; // @[el2_exu_alu_ctl.scala 123:24]
|
||||||
|
wire _T_322 = io_pp_in_hist[1] & actual_taken; // @[el2_exu_alu_ctl.scala 123:62]
|
||||||
|
wire _T_323 = _T_320 | _T_322; // @[el2_exu_alu_ctl.scala 123:42]
|
||||||
|
wire _T_327 = _T_300 & _T_302; // @[el2_exu_alu_ctl.scala 126:51]
|
||||||
|
wire _T_328 = cond_mispredict | target_mispredict; // @[el2_exu_alu_ctl.scala 126:90]
|
||||||
|
rvclkhdr rvclkhdr ( // @[el2_lib.scala 485:23]
|
||||||
|
.io_l1clk(rvclkhdr_io_l1clk),
|
||||||
|
.io_clk(rvclkhdr_io_clk),
|
||||||
|
.io_en(rvclkhdr_io_en),
|
||||||
|
.io_scan_mode(rvclkhdr_io_scan_mode)
|
||||||
|
);
|
||||||
|
rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 485:23]
|
||||||
|
.io_l1clk(rvclkhdr_1_io_l1clk),
|
||||||
|
.io_clk(rvclkhdr_1_io_clk),
|
||||||
|
.io_en(rvclkhdr_1_io_en),
|
||||||
|
.io_scan_mode(rvclkhdr_1_io_scan_mode)
|
||||||
|
);
|
||||||
|
assign io_result_ff = _T_3; // @[el2_exu_alu_ctl.scala 37:16]
|
||||||
|
assign io_flush_upper_out = _T_301 & _T_302; // @[el2_exu_alu_ctl.scala 116:26]
|
||||||
|
assign io_flush_final_out = _T_301 | io_flush_lower_r; // @[el2_exu_alu_ctl.scala 118:26]
|
||||||
|
assign io_flush_path_out = sel_pc ? aout[31:1] : pcout[31:1]; // @[el2_exu_alu_ctl.scala 108:22]
|
||||||
|
assign io_pc_ff = _T_1; // @[el2_exu_alu_ctl.scala 35:12]
|
||||||
|
assign io_pred_correct_out = _T_282 | _T_286; // @[el2_exu_alu_ctl.scala 106:26]
|
||||||
|
assign io_predict_p_out_misp = _T_327 & _T_328; // @[el2_exu_alu_ctl.scala 125:30 el2_exu_alu_ctl.scala 126:30]
|
||||||
|
assign io_predict_p_out_ataken = _T_277 | sel_pc; // @[el2_exu_alu_ctl.scala 125:30 el2_exu_alu_ctl.scala 127:30]
|
||||||
|
assign io_predict_p_out_boffset = io_pp_in_boffset; // @[el2_exu_alu_ctl.scala 125:30]
|
||||||
|
assign io_predict_p_out_pc4 = io_pp_in_pc4; // @[el2_exu_alu_ctl.scala 125:30]
|
||||||
|
assign io_predict_p_out_hist = {_T_316,_T_323}; // @[el2_exu_alu_ctl.scala 125:30 el2_exu_alu_ctl.scala 128:30]
|
||||||
|
assign io_predict_p_out_toffset = io_pp_in_toffset; // @[el2_exu_alu_ctl.scala 125:30]
|
||||||
|
assign io_predict_p_out_valid = io_pp_in_valid; // @[el2_exu_alu_ctl.scala 125:30]
|
||||||
|
assign io_predict_p_out_br_error = io_pp_in_br_error; // @[el2_exu_alu_ctl.scala 125:30]
|
||||||
|
assign io_predict_p_out_br_start_error = io_pp_in_br_start_error; // @[el2_exu_alu_ctl.scala 125:30]
|
||||||
|
assign io_predict_p_out_prett = io_pp_in_prett; // @[el2_exu_alu_ctl.scala 125:30]
|
||||||
|
assign io_predict_p_out_pcall = io_pp_in_pcall; // @[el2_exu_alu_ctl.scala 125:30]
|
||||||
|
assign io_predict_p_out_pret = io_pp_in_pret; // @[el2_exu_alu_ctl.scala 125:30]
|
||||||
|
assign io_predict_p_out_pja = io_pp_in_pja; // @[el2_exu_alu_ctl.scala 125:30]
|
||||||
|
assign io_predict_p_out_way = io_pp_in_way; // @[el2_exu_alu_ctl.scala 125:30]
|
||||||
|
assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 487:18]
|
||||||
|
assign rvclkhdr_io_en = io_enable; // @[el2_lib.scala 488:17]
|
||||||
|
assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24]
|
||||||
|
assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 487:18]
|
||||||
|
assign rvclkhdr_1_io_en = io_enable; // @[el2_lib.scala 488:17]
|
||||||
|
assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24]
|
||||||
|
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
||||||
|
`define RANDOMIZE
|
||||||
|
`endif
|
||||||
|
`ifdef RANDOMIZE_INVALID_ASSIGN
|
||||||
|
`define RANDOMIZE
|
||||||
|
`endif
|
||||||
|
`ifdef RANDOMIZE_REG_INIT
|
||||||
|
`define RANDOMIZE
|
||||||
|
`endif
|
||||||
|
`ifdef RANDOMIZE_MEM_INIT
|
||||||
|
`define RANDOMIZE
|
||||||
|
`endif
|
||||||
|
`ifndef RANDOM
|
||||||
|
`define RANDOM $random
|
||||||
|
`endif
|
||||||
|
`ifdef RANDOMIZE_MEM_INIT
|
||||||
|
integer initvar;
|
||||||
|
`endif
|
||||||
|
`ifndef SYNTHESIS
|
||||||
|
`ifdef FIRRTL_BEFORE_INITIAL
|
||||||
|
`FIRRTL_BEFORE_INITIAL
|
||||||
|
`endif
|
||||||
|
initial begin
|
||||||
|
`ifdef RANDOMIZE
|
||||||
|
`ifdef INIT_RANDOM
|
||||||
|
`INIT_RANDOM
|
||||||
|
`endif
|
||||||
|
`ifndef VERILATOR
|
||||||
|
`ifdef RANDOMIZE_DELAY
|
||||||
|
#`RANDOMIZE_DELAY begin end
|
||||||
|
`else
|
||||||
|
#0.002 begin end
|
||||||
|
`endif
|
||||||
|
`endif
|
||||||
|
`ifdef RANDOMIZE_REG_INIT
|
||||||
|
_RAND_0 = {1{`RANDOM}};
|
||||||
|
_T_1 = _RAND_0[30:0];
|
||||||
|
_RAND_1 = {1{`RANDOM}};
|
||||||
|
_T_3 = _RAND_1[31:0];
|
||||||
|
`endif // RANDOMIZE_REG_INIT
|
||||||
|
if (reset) begin
|
||||||
|
_T_1 = 31'h0;
|
||||||
|
end
|
||||||
|
if (reset) begin
|
||||||
|
_T_3 = 32'h0;
|
||||||
|
end
|
||||||
|
`endif // RANDOMIZE
|
||||||
|
end // initial
|
||||||
|
`ifdef FIRRTL_AFTER_INITIAL
|
||||||
|
`FIRRTL_AFTER_INITIAL
|
||||||
|
`endif
|
||||||
|
`endif // SYNTHESIS
|
||||||
|
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
|
||||||
|
if (reset) begin
|
||||||
|
_T_1 <= 31'h0;
|
||||||
|
end else begin
|
||||||
|
_T_1 <= io_pc_in;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin
|
||||||
|
if (reset) begin
|
||||||
|
_T_3 <= 32'h0;
|
||||||
|
end else begin
|
||||||
|
_T_3 <= _T_252 | _T_266;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
endmodule
|
||||||
|
|
@ -0,0 +1,30 @@
|
||||||
|
[
|
||||||
|
{
|
||||||
|
"class":"firrtl.transforms.CombinationalPath",
|
||||||
|
"sink":"~el2_exu_div_ctl|el2_exu_div_ctl>io_finish_dly",
|
||||||
|
"sources":[
|
||||||
|
"~el2_exu_div_ctl|el2_exu_div_ctl>io_cancel"
|
||||||
|
]
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"class":"firrtl.EmitCircuitAnnotation",
|
||||||
|
"emitter":"firrtl.VerilogEmitter"
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"class":"firrtl.transforms.BlackBoxResourceAnno",
|
||||||
|
"target":"el2_exu_div_ctl.TEC_RV_ICG",
|
||||||
|
"resourceId":"/vsrc/TEC_RV_ICG.v"
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"class":"firrtl.options.TargetDirAnnotation",
|
||||||
|
"directory":"."
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"class":"firrtl.options.OutputAnnotationFileAnnotation",
|
||||||
|
"file":"el2_exu_div_ctl"
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
|
||||||
|
"targetDir":"."
|
||||||
|
}
|
||||||
|
]
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,853 @@
|
||||||
|
module rvclkhdr(
|
||||||
|
output io_l1clk,
|
||||||
|
input io_clk,
|
||||||
|
input io_en,
|
||||||
|
input io_scan_mode
|
||||||
|
);
|
||||||
|
wire clkhdr_Q; // @[el2_lib.scala 465:26]
|
||||||
|
wire clkhdr_CK; // @[el2_lib.scala 465:26]
|
||||||
|
wire clkhdr_EN; // @[el2_lib.scala 465:26]
|
||||||
|
wire clkhdr_SE; // @[el2_lib.scala 465:26]
|
||||||
|
TEC_RV_ICG clkhdr ( // @[el2_lib.scala 465:26]
|
||||||
|
.Q(clkhdr_Q),
|
||||||
|
.CK(clkhdr_CK),
|
||||||
|
.EN(clkhdr_EN),
|
||||||
|
.SE(clkhdr_SE)
|
||||||
|
);
|
||||||
|
assign io_l1clk = clkhdr_Q; // @[el2_lib.scala 466:14]
|
||||||
|
assign clkhdr_CK = io_clk; // @[el2_lib.scala 467:18]
|
||||||
|
assign clkhdr_EN = io_en; // @[el2_lib.scala 468:18]
|
||||||
|
assign clkhdr_SE = io_scan_mode; // @[el2_lib.scala 469:18]
|
||||||
|
endmodule
|
||||||
|
module el2_exu_div_ctl(
|
||||||
|
input clock,
|
||||||
|
input reset,
|
||||||
|
input io_scan_mode,
|
||||||
|
input io_dp_valid,
|
||||||
|
input io_dp_unsign,
|
||||||
|
input io_dp_rem,
|
||||||
|
input [31:0] io_dividend,
|
||||||
|
input [31:0] io_divisor,
|
||||||
|
input io_cancel,
|
||||||
|
output [31:0] io_out,
|
||||||
|
output io_finish_dly
|
||||||
|
);
|
||||||
|
`ifdef RANDOMIZE_REG_INIT
|
||||||
|
reg [31:0] _RAND_0;
|
||||||
|
reg [63:0] _RAND_1;
|
||||||
|
reg [63:0] _RAND_2;
|
||||||
|
reg [31:0] _RAND_3;
|
||||||
|
reg [31:0] _RAND_4;
|
||||||
|
reg [31:0] _RAND_5;
|
||||||
|
reg [31:0] _RAND_6;
|
||||||
|
reg [31:0] _RAND_7;
|
||||||
|
reg [31:0] _RAND_8;
|
||||||
|
reg [31:0] _RAND_9;
|
||||||
|
reg [31:0] _RAND_10;
|
||||||
|
reg [63:0] _RAND_11;
|
||||||
|
reg [31:0] _RAND_12;
|
||||||
|
reg [31:0] _RAND_13;
|
||||||
|
reg [31:0] _RAND_14;
|
||||||
|
`endif // RANDOMIZE_REG_INIT
|
||||||
|
wire rvclkhdr_io_l1clk; // @[el2_lib.scala 474:22]
|
||||||
|
wire rvclkhdr_io_clk; // @[el2_lib.scala 474:22]
|
||||||
|
wire rvclkhdr_io_en; // @[el2_lib.scala 474:22]
|
||||||
|
wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 474:22]
|
||||||
|
wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 485:23]
|
||||||
|
wire rvclkhdr_1_io_clk; // @[el2_lib.scala 485:23]
|
||||||
|
wire rvclkhdr_1_io_en; // @[el2_lib.scala 485:23]
|
||||||
|
wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 485:23]
|
||||||
|
wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 485:23]
|
||||||
|
wire rvclkhdr_2_io_clk; // @[el2_lib.scala 485:23]
|
||||||
|
wire rvclkhdr_2_io_en; // @[el2_lib.scala 485:23]
|
||||||
|
wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 485:23]
|
||||||
|
wire rvclkhdr_3_io_l1clk; // @[el2_lib.scala 485:23]
|
||||||
|
wire rvclkhdr_3_io_clk; // @[el2_lib.scala 485:23]
|
||||||
|
wire rvclkhdr_3_io_en; // @[el2_lib.scala 485:23]
|
||||||
|
wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 485:23]
|
||||||
|
wire _T = ~io_cancel; // @[el2_exu_div_ctl.scala 54:30]
|
||||||
|
reg valid_ff_x; // @[el2_exu_div_ctl.scala 204:26]
|
||||||
|
wire valid_x = valid_ff_x & _T; // @[el2_exu_div_ctl.scala 54:28]
|
||||||
|
reg [32:0] q_ff; // @[el2_lib.scala 491:16]
|
||||||
|
wire _T_2 = q_ff[31:4] == 28'h0; // @[el2_exu_div_ctl.scala 60:34]
|
||||||
|
reg [32:0] m_ff; // @[el2_lib.scala 491:16]
|
||||||
|
wire _T_4 = m_ff[31:4] == 28'h0; // @[el2_exu_div_ctl.scala 60:57]
|
||||||
|
wire _T_5 = _T_2 & _T_4; // @[el2_exu_div_ctl.scala 60:43]
|
||||||
|
wire _T_7 = m_ff[31:0] != 32'h0; // @[el2_exu_div_ctl.scala 60:80]
|
||||||
|
wire _T_8 = _T_5 & _T_7; // @[el2_exu_div_ctl.scala 60:66]
|
||||||
|
reg rem_ff; // @[Reg.scala 27:20]
|
||||||
|
wire _T_9 = ~rem_ff; // @[el2_exu_div_ctl.scala 60:91]
|
||||||
|
wire _T_10 = _T_8 & _T_9; // @[el2_exu_div_ctl.scala 60:89]
|
||||||
|
wire _T_11 = _T_10 & valid_x; // @[el2_exu_div_ctl.scala 60:99]
|
||||||
|
wire _T_13 = q_ff[31:0] == 32'h0; // @[el2_exu_div_ctl.scala 61:18]
|
||||||
|
wire _T_16 = _T_13 & _T_7; // @[el2_exu_div_ctl.scala 61:27]
|
||||||
|
wire _T_18 = _T_16 & _T_9; // @[el2_exu_div_ctl.scala 61:50]
|
||||||
|
wire _T_19 = _T_18 & valid_x; // @[el2_exu_div_ctl.scala 61:60]
|
||||||
|
wire smallnum_case = _T_11 | _T_19; // @[el2_exu_div_ctl.scala 60:110]
|
||||||
|
wire pat1 = q_ff[3]; // @[el2_exu_div_ctl.scala 64:57]
|
||||||
|
wire _T_22 = ~m_ff[3]; // @[el2_exu_div_ctl.scala 65:69]
|
||||||
|
wire _T_24 = ~m_ff[2]; // @[el2_exu_div_ctl.scala 65:69]
|
||||||
|
wire _T_26 = ~m_ff[1]; // @[el2_exu_div_ctl.scala 65:69]
|
||||||
|
wire _T_27 = _T_22 & _T_24; // @[el2_exu_div_ctl.scala 65:94]
|
||||||
|
wire pat2 = _T_27 & _T_26; // @[el2_exu_div_ctl.scala 65:94]
|
||||||
|
wire _T_28 = pat1 & pat2; // @[el2_exu_div_ctl.scala 66:10]
|
||||||
|
wire _T_33 = pat1 & _T_27; // @[el2_exu_div_ctl.scala 66:10]
|
||||||
|
wire _T_35 = ~m_ff[0]; // @[el2_exu_div_ctl.scala 72:32]
|
||||||
|
wire _T_36 = _T_33 & _T_35; // @[el2_exu_div_ctl.scala 72:30]
|
||||||
|
wire pat1_2 = q_ff[2]; // @[el2_exu_div_ctl.scala 64:57]
|
||||||
|
wire _T_44 = pat1_2 & pat2; // @[el2_exu_div_ctl.scala 66:10]
|
||||||
|
wire _T_45 = _T_36 | _T_44; // @[el2_exu_div_ctl.scala 72:41]
|
||||||
|
wire pat1_3 = pat1 & pat1_2; // @[el2_exu_div_ctl.scala 64:94]
|
||||||
|
wire _T_52 = pat1_3 & _T_27; // @[el2_exu_div_ctl.scala 66:10]
|
||||||
|
wire _T_53 = _T_45 | _T_52; // @[el2_exu_div_ctl.scala 72:73]
|
||||||
|
wire _T_58 = pat1_2 & _T_27; // @[el2_exu_div_ctl.scala 66:10]
|
||||||
|
wire _T_61 = _T_58 & _T_35; // @[el2_exu_div_ctl.scala 74:30]
|
||||||
|
wire pat1_5 = q_ff[1]; // @[el2_exu_div_ctl.scala 64:57]
|
||||||
|
wire _T_69 = pat1_5 & pat2; // @[el2_exu_div_ctl.scala 66:10]
|
||||||
|
wire _T_70 = _T_61 | _T_69; // @[el2_exu_div_ctl.scala 74:41]
|
||||||
|
wire pat2_6 = _T_22 & _T_26; // @[el2_exu_div_ctl.scala 65:94]
|
||||||
|
wire _T_75 = pat1 & pat2_6; // @[el2_exu_div_ctl.scala 66:10]
|
||||||
|
wire _T_78 = _T_75 & _T_35; // @[el2_exu_div_ctl.scala 74:103]
|
||||||
|
wire _T_79 = _T_70 | _T_78; // @[el2_exu_div_ctl.scala 74:76]
|
||||||
|
wire _T_82 = ~pat1_2; // @[el2_exu_div_ctl.scala 64:69]
|
||||||
|
wire pat1_7 = pat1 & _T_82; // @[el2_exu_div_ctl.scala 64:94]
|
||||||
|
wire _T_90 = _T_27 & m_ff[1]; // @[el2_exu_div_ctl.scala 65:94]
|
||||||
|
wire pat2_7 = _T_90 & m_ff[0]; // @[el2_exu_div_ctl.scala 65:94]
|
||||||
|
wire _T_91 = pat1_7 & pat2_7; // @[el2_exu_div_ctl.scala 66:10]
|
||||||
|
wire _T_92 = _T_79 | _T_91; // @[el2_exu_div_ctl.scala 74:114]
|
||||||
|
wire _T_94 = ~pat1; // @[el2_exu_div_ctl.scala 64:69]
|
||||||
|
wire _T_97 = _T_94 & pat1_2; // @[el2_exu_div_ctl.scala 64:94]
|
||||||
|
wire pat1_8 = _T_97 & pat1_5; // @[el2_exu_div_ctl.scala 64:94]
|
||||||
|
wire _T_102 = pat1_8 & _T_27; // @[el2_exu_div_ctl.scala 66:10]
|
||||||
|
wire _T_103 = _T_92 | _T_102; // @[el2_exu_div_ctl.scala 75:43]
|
||||||
|
wire _T_107 = pat1_3 & _T_22; // @[el2_exu_div_ctl.scala 66:10]
|
||||||
|
wire _T_110 = _T_107 & _T_35; // @[el2_exu_div_ctl.scala 75:104]
|
||||||
|
wire _T_111 = _T_103 | _T_110; // @[el2_exu_div_ctl.scala 75:78]
|
||||||
|
wire _T_119 = _T_22 & m_ff[2]; // @[el2_exu_div_ctl.scala 65:94]
|
||||||
|
wire pat2_10 = _T_119 & _T_26; // @[el2_exu_div_ctl.scala 65:94]
|
||||||
|
wire _T_120 = pat1_3 & pat2_10; // @[el2_exu_div_ctl.scala 66:10]
|
||||||
|
wire _T_121 = _T_111 | _T_120; // @[el2_exu_div_ctl.scala 75:116]
|
||||||
|
wire pat1_11 = pat1 & pat1_5; // @[el2_exu_div_ctl.scala 64:94]
|
||||||
|
wire _T_128 = pat1_11 & pat2_6; // @[el2_exu_div_ctl.scala 66:10]
|
||||||
|
wire _T_129 = _T_121 | _T_128; // @[el2_exu_div_ctl.scala 76:43]
|
||||||
|
wire pat1_12 = pat1_3 & pat1_5; // @[el2_exu_div_ctl.scala 64:94]
|
||||||
|
wire _T_137 = pat1_12 & _T_119; // @[el2_exu_div_ctl.scala 66:10]
|
||||||
|
wire _T_138 = _T_129 | _T_137; // @[el2_exu_div_ctl.scala 76:77]
|
||||||
|
wire _T_142 = pat1_2 & pat1_5; // @[el2_exu_div_ctl.scala 64:94]
|
||||||
|
wire pat1_13 = _T_142 & q_ff[0]; // @[el2_exu_div_ctl.scala 64:94]
|
||||||
|
wire _T_147 = pat1_13 & pat2_6; // @[el2_exu_div_ctl.scala 66:10]
|
||||||
|
wire pat1_14 = pat1_7 & q_ff[0]; // @[el2_exu_div_ctl.scala 64:94]
|
||||||
|
wire _T_157 = _T_22 & m_ff[1]; // @[el2_exu_div_ctl.scala 65:94]
|
||||||
|
wire pat2_14 = _T_157 & m_ff[0]; // @[el2_exu_div_ctl.scala 65:94]
|
||||||
|
wire _T_158 = pat1_14 & pat2_14; // @[el2_exu_div_ctl.scala 66:10]
|
||||||
|
wire _T_159 = _T_147 | _T_158; // @[el2_exu_div_ctl.scala 78:44]
|
||||||
|
wire _T_164 = pat1_2 & pat2_6; // @[el2_exu_div_ctl.scala 66:10]
|
||||||
|
wire _T_167 = _T_164 & _T_35; // @[el2_exu_div_ctl.scala 78:111]
|
||||||
|
wire _T_168 = _T_159 | _T_167; // @[el2_exu_div_ctl.scala 78:84]
|
||||||
|
wire _T_173 = pat1_5 & _T_27; // @[el2_exu_div_ctl.scala 66:10]
|
||||||
|
wire _T_176 = _T_173 & _T_35; // @[el2_exu_div_ctl.scala 79:32]
|
||||||
|
wire _T_177 = _T_168 | _T_176; // @[el2_exu_div_ctl.scala 78:126]
|
||||||
|
wire _T_185 = q_ff[0] & pat2; // @[el2_exu_div_ctl.scala 66:10]
|
||||||
|
wire _T_186 = _T_177 | _T_185; // @[el2_exu_div_ctl.scala 79:46]
|
||||||
|
wire _T_191 = ~pat1_5; // @[el2_exu_div_ctl.scala 64:69]
|
||||||
|
wire pat1_18 = _T_97 & _T_191; // @[el2_exu_div_ctl.scala 64:94]
|
||||||
|
wire _T_201 = pat1_18 & pat2_7; // @[el2_exu_div_ctl.scala 66:10]
|
||||||
|
wire _T_202 = _T_186 | _T_201; // @[el2_exu_div_ctl.scala 79:86]
|
||||||
|
wire _T_209 = pat1_8 & _T_22; // @[el2_exu_div_ctl.scala 66:10]
|
||||||
|
wire _T_212 = _T_209 & _T_35; // @[el2_exu_div_ctl.scala 80:35]
|
||||||
|
wire _T_213 = _T_202 | _T_212; // @[el2_exu_div_ctl.scala 79:128]
|
||||||
|
wire pat2_20 = _T_24 & _T_26; // @[el2_exu_div_ctl.scala 65:94]
|
||||||
|
wire _T_218 = pat1 & pat2_20; // @[el2_exu_div_ctl.scala 66:10]
|
||||||
|
wire _T_221 = _T_218 & _T_35; // @[el2_exu_div_ctl.scala 80:74]
|
||||||
|
wire _T_222 = _T_213 | _T_221; // @[el2_exu_div_ctl.scala 80:46]
|
||||||
|
wire pat2_21 = _T_119 & m_ff[1]; // @[el2_exu_div_ctl.scala 65:94]
|
||||||
|
wire _T_231 = pat1_7 & pat2_21; // @[el2_exu_div_ctl.scala 66:10]
|
||||||
|
wire _T_232 = _T_222 | _T_231; // @[el2_exu_div_ctl.scala 80:86]
|
||||||
|
wire _T_244 = pat1_8 & pat2_10; // @[el2_exu_div_ctl.scala 66:10]
|
||||||
|
wire _T_245 = _T_232 | _T_244; // @[el2_exu_div_ctl.scala 80:128]
|
||||||
|
wire pat1_23 = _T_97 & q_ff[0]; // @[el2_exu_div_ctl.scala 64:94]
|
||||||
|
wire _T_255 = pat1_23 & pat2_6; // @[el2_exu_div_ctl.scala 66:10]
|
||||||
|
wire _T_256 = _T_245 | _T_255; // @[el2_exu_div_ctl.scala 81:46]
|
||||||
|
wire pat1_24 = pat1_7 & _T_191; // @[el2_exu_div_ctl.scala 64:94]
|
||||||
|
wire pat2_24 = _T_119 & m_ff[0]; // @[el2_exu_div_ctl.scala 65:94]
|
||||||
|
wire _T_268 = pat1_24 & pat2_24; // @[el2_exu_div_ctl.scala 66:10]
|
||||||
|
wire _T_269 = _T_256 | _T_268; // @[el2_exu_div_ctl.scala 81:86]
|
||||||
|
wire _T_274 = _T_82 & pat1_5; // @[el2_exu_div_ctl.scala 64:94]
|
||||||
|
wire pat1_25 = _T_274 & q_ff[0]; // @[el2_exu_div_ctl.scala 64:94]
|
||||||
|
wire _T_279 = pat1_25 & _T_27; // @[el2_exu_div_ctl.scala 66:10]
|
||||||
|
wire _T_280 = _T_269 | _T_279; // @[el2_exu_div_ctl.scala 81:128]
|
||||||
|
wire _T_284 = pat1_3 & _T_26; // @[el2_exu_div_ctl.scala 66:10]
|
||||||
|
wire _T_287 = _T_284 & _T_35; // @[el2_exu_div_ctl.scala 82:73]
|
||||||
|
wire _T_288 = _T_280 | _T_287; // @[el2_exu_div_ctl.scala 82:46]
|
||||||
|
wire pat1_27 = pat1_8 & q_ff[0]; // @[el2_exu_div_ctl.scala 64:94]
|
||||||
|
wire _T_299 = pat1_27 & _T_119; // @[el2_exu_div_ctl.scala 66:10]
|
||||||
|
wire _T_300 = _T_288 | _T_299; // @[el2_exu_div_ctl.scala 82:86]
|
||||||
|
wire pat2_28 = m_ff[3] & _T_24; // @[el2_exu_div_ctl.scala 65:94]
|
||||||
|
wire _T_306 = pat1_3 & pat2_28; // @[el2_exu_div_ctl.scala 66:10]
|
||||||
|
wire _T_307 = _T_300 | _T_306; // @[el2_exu_div_ctl.scala 82:128]
|
||||||
|
wire pat2_29 = pat2_28 & _T_26; // @[el2_exu_div_ctl.scala 65:94]
|
||||||
|
wire _T_316 = pat1_11 & pat2_29; // @[el2_exu_div_ctl.scala 66:10]
|
||||||
|
wire _T_317 = _T_307 | _T_316; // @[el2_exu_div_ctl.scala 83:46]
|
||||||
|
wire pat1_30 = pat1 & q_ff[0]; // @[el2_exu_div_ctl.scala 64:94]
|
||||||
|
wire _T_324 = pat1_30 & pat2_20; // @[el2_exu_div_ctl.scala 66:10]
|
||||||
|
wire _T_325 = _T_317 | _T_324; // @[el2_exu_div_ctl.scala 83:86]
|
||||||
|
wire pat1_31 = pat1 & _T_191; // @[el2_exu_div_ctl.scala 64:94]
|
||||||
|
wire pat2_31 = pat2_21 & m_ff[0]; // @[el2_exu_div_ctl.scala 65:94]
|
||||||
|
wire _T_336 = pat1_31 & pat2_31; // @[el2_exu_div_ctl.scala 66:10]
|
||||||
|
wire _T_337 = _T_325 | _T_336; // @[el2_exu_div_ctl.scala 83:128]
|
||||||
|
wire _T_342 = pat1_12 & m_ff[3]; // @[el2_exu_div_ctl.scala 66:10]
|
||||||
|
wire _T_345 = _T_342 & _T_35; // @[el2_exu_div_ctl.scala 84:75]
|
||||||
|
wire _T_346 = _T_337 | _T_345; // @[el2_exu_div_ctl.scala 84:46]
|
||||||
|
wire pat2_33 = m_ff[3] & _T_26; // @[el2_exu_div_ctl.scala 65:94]
|
||||||
|
wire _T_354 = pat1_12 & pat2_33; // @[el2_exu_div_ctl.scala 66:10]
|
||||||
|
wire _T_355 = _T_346 | _T_354; // @[el2_exu_div_ctl.scala 84:86]
|
||||||
|
wire pat1_34 = pat1_3 & q_ff[0]; // @[el2_exu_div_ctl.scala 64:94]
|
||||||
|
wire _T_363 = pat1_34 & pat2_33; // @[el2_exu_div_ctl.scala 66:10]
|
||||||
|
wire _T_364 = _T_355 | _T_363; // @[el2_exu_div_ctl.scala 84:128]
|
||||||
|
wire pat1_35 = pat1_7 & pat1_5; // @[el2_exu_div_ctl.scala 64:94]
|
||||||
|
wire _T_373 = pat1_35 & _T_157; // @[el2_exu_div_ctl.scala 66:10]
|
||||||
|
wire _T_374 = _T_364 | _T_373; // @[el2_exu_div_ctl.scala 85:46]
|
||||||
|
wire pat1_36 = pat1_11 & q_ff[0]; // @[el2_exu_div_ctl.scala 64:94]
|
||||||
|
wire _T_380 = pat1_36 & _T_24; // @[el2_exu_div_ctl.scala 66:10]
|
||||||
|
wire _T_381 = _T_374 | _T_380; // @[el2_exu_div_ctl.scala 85:86]
|
||||||
|
wire pat1_37 = pat1_12 & q_ff[0]; // @[el2_exu_div_ctl.scala 64:94]
|
||||||
|
wire _T_388 = pat1_37 & m_ff[3]; // @[el2_exu_div_ctl.scala 66:10]
|
||||||
|
wire _T_389 = _T_381 | _T_388; // @[el2_exu_div_ctl.scala 85:128]
|
||||||
|
wire _T_393 = pat1_11 & _T_24; // @[el2_exu_div_ctl.scala 66:10]
|
||||||
|
wire _T_396 = _T_393 & _T_35; // @[el2_exu_div_ctl.scala 86:72]
|
||||||
|
wire _T_397 = _T_389 | _T_396; // @[el2_exu_div_ctl.scala 86:46]
|
||||||
|
wire [1:0] _T_398 = {_T_138,_T_397}; // @[Cat.scala 29:58]
|
||||||
|
wire [1:0] _T_399 = {_T_28,_T_53}; // @[Cat.scala 29:58]
|
||||||
|
reg sign_ff; // @[Reg.scala 27:20]
|
||||||
|
wire _T_401 = sign_ff & q_ff[31]; // @[el2_exu_div_ctl.scala 96:34]
|
||||||
|
wire [32:0] short_dividend = {_T_401,q_ff[31:0]}; // @[Cat.scala 29:58]
|
||||||
|
wire _T_406 = ~short_dividend[32]; // @[el2_exu_div_ctl.scala 101:7]
|
||||||
|
wire _T_409 = short_dividend[31:24] != 8'h0; // @[el2_exu_div_ctl.scala 101:60]
|
||||||
|
wire _T_414 = short_dividend[31:23] != 9'h1ff; // @[el2_exu_div_ctl.scala 102:59]
|
||||||
|
wire _T_415 = _T_406 & _T_409; // @[Mux.scala 27:72]
|
||||||
|
wire _T_416 = short_dividend[32] & _T_414; // @[Mux.scala 27:72]
|
||||||
|
wire _T_417 = _T_415 | _T_416; // @[Mux.scala 27:72]
|
||||||
|
wire _T_424 = short_dividend[23:16] != 8'h0; // @[el2_exu_div_ctl.scala 105:60]
|
||||||
|
wire _T_429 = short_dividend[22:15] != 8'hff; // @[el2_exu_div_ctl.scala 106:59]
|
||||||
|
wire _T_430 = _T_406 & _T_424; // @[Mux.scala 27:72]
|
||||||
|
wire _T_431 = short_dividend[32] & _T_429; // @[Mux.scala 27:72]
|
||||||
|
wire _T_432 = _T_430 | _T_431; // @[Mux.scala 27:72]
|
||||||
|
wire _T_439 = short_dividend[15:8] != 8'h0; // @[el2_exu_div_ctl.scala 109:59]
|
||||||
|
wire _T_444 = short_dividend[14:7] != 8'hff; // @[el2_exu_div_ctl.scala 110:58]
|
||||||
|
wire _T_445 = _T_406 & _T_439; // @[Mux.scala 27:72]
|
||||||
|
wire _T_446 = short_dividend[32] & _T_444; // @[Mux.scala 27:72]
|
||||||
|
wire _T_447 = _T_445 | _T_446; // @[Mux.scala 27:72]
|
||||||
|
wire [2:0] a_cls = {_T_417,_T_432,_T_447}; // @[Cat.scala 29:58]
|
||||||
|
wire _T_452 = ~m_ff[32]; // @[el2_exu_div_ctl.scala 115:7]
|
||||||
|
wire _T_455 = m_ff[31:24] != 8'h0; // @[el2_exu_div_ctl.scala 115:40]
|
||||||
|
wire _T_460 = m_ff[31:24] != 8'hff; // @[el2_exu_div_ctl.scala 116:39]
|
||||||
|
wire _T_461 = _T_452 & _T_455; // @[Mux.scala 27:72]
|
||||||
|
wire _T_462 = m_ff[32] & _T_460; // @[Mux.scala 27:72]
|
||||||
|
wire _T_463 = _T_461 | _T_462; // @[Mux.scala 27:72]
|
||||||
|
wire _T_470 = m_ff[23:16] != 8'h0; // @[el2_exu_div_ctl.scala 119:40]
|
||||||
|
wire _T_475 = m_ff[23:16] != 8'hff; // @[el2_exu_div_ctl.scala 120:39]
|
||||||
|
wire _T_476 = _T_452 & _T_470; // @[Mux.scala 27:72]
|
||||||
|
wire _T_477 = m_ff[32] & _T_475; // @[Mux.scala 27:72]
|
||||||
|
wire _T_478 = _T_476 | _T_477; // @[Mux.scala 27:72]
|
||||||
|
wire _T_485 = m_ff[15:8] != 8'h0; // @[el2_exu_div_ctl.scala 123:39]
|
||||||
|
wire _T_490 = m_ff[15:8] != 8'hff; // @[el2_exu_div_ctl.scala 124:38]
|
||||||
|
wire _T_491 = _T_452 & _T_485; // @[Mux.scala 27:72]
|
||||||
|
wire _T_492 = m_ff[32] & _T_490; // @[Mux.scala 27:72]
|
||||||
|
wire _T_493 = _T_491 | _T_492; // @[Mux.scala 27:72]
|
||||||
|
wire [2:0] b_cls = {_T_463,_T_478,_T_493}; // @[Cat.scala 29:58]
|
||||||
|
wire _T_497 = a_cls[2:1] == 2'h1; // @[el2_exu_div_ctl.scala 128:19]
|
||||||
|
wire _T_500 = _T_497 & b_cls[2]; // @[el2_exu_div_ctl.scala 128:34]
|
||||||
|
wire _T_502 = a_cls == 3'h1; // @[el2_exu_div_ctl.scala 129:21]
|
||||||
|
wire _T_505 = _T_502 & b_cls[2]; // @[el2_exu_div_ctl.scala 129:36]
|
||||||
|
wire _T_506 = _T_500 | _T_505; // @[el2_exu_div_ctl.scala 128:65]
|
||||||
|
wire _T_508 = a_cls == 3'h0; // @[el2_exu_div_ctl.scala 130:21]
|
||||||
|
wire _T_511 = _T_508 & b_cls[2]; // @[el2_exu_div_ctl.scala 130:36]
|
||||||
|
wire _T_512 = _T_506 | _T_511; // @[el2_exu_div_ctl.scala 129:67]
|
||||||
|
wire _T_516 = b_cls[2:1] == 2'h1; // @[el2_exu_div_ctl.scala 131:50]
|
||||||
|
wire _T_517 = _T_502 & _T_516; // @[el2_exu_div_ctl.scala 131:36]
|
||||||
|
wire _T_518 = _T_512 | _T_517; // @[el2_exu_div_ctl.scala 130:67]
|
||||||
|
wire _T_523 = _T_508 & _T_516; // @[el2_exu_div_ctl.scala 132:36]
|
||||||
|
wire _T_524 = _T_518 | _T_523; // @[el2_exu_div_ctl.scala 131:67]
|
||||||
|
wire _T_528 = b_cls == 3'h1; // @[el2_exu_div_ctl.scala 133:50]
|
||||||
|
wire _T_529 = _T_508 & _T_528; // @[el2_exu_div_ctl.scala 133:36]
|
||||||
|
wire _T_530 = _T_524 | _T_529; // @[el2_exu_div_ctl.scala 132:67]
|
||||||
|
wire _T_535 = a_cls[2] & b_cls[2]; // @[el2_exu_div_ctl.scala 135:34]
|
||||||
|
wire _T_540 = _T_497 & _T_516; // @[el2_exu_div_ctl.scala 136:36]
|
||||||
|
wire _T_541 = _T_535 | _T_540; // @[el2_exu_div_ctl.scala 135:65]
|
||||||
|
wire _T_546 = _T_502 & _T_528; // @[el2_exu_div_ctl.scala 137:36]
|
||||||
|
wire _T_547 = _T_541 | _T_546; // @[el2_exu_div_ctl.scala 136:67]
|
||||||
|
wire _T_551 = b_cls == 3'h0; // @[el2_exu_div_ctl.scala 138:50]
|
||||||
|
wire _T_552 = _T_508 & _T_551; // @[el2_exu_div_ctl.scala 138:36]
|
||||||
|
wire _T_553 = _T_547 | _T_552; // @[el2_exu_div_ctl.scala 137:67]
|
||||||
|
wire _T_558 = a_cls[2] & _T_516; // @[el2_exu_div_ctl.scala 140:34]
|
||||||
|
wire _T_563 = _T_497 & _T_528; // @[el2_exu_div_ctl.scala 141:36]
|
||||||
|
wire _T_564 = _T_558 | _T_563; // @[el2_exu_div_ctl.scala 140:65]
|
||||||
|
wire _T_569 = _T_502 & _T_551; // @[el2_exu_div_ctl.scala 142:36]
|
||||||
|
wire _T_570 = _T_564 | _T_569; // @[el2_exu_div_ctl.scala 141:67]
|
||||||
|
wire _T_575 = a_cls[2] & _T_528; // @[el2_exu_div_ctl.scala 144:34]
|
||||||
|
wire _T_580 = _T_497 & _T_551; // @[el2_exu_div_ctl.scala 145:36]
|
||||||
|
wire _T_581 = _T_575 | _T_580; // @[el2_exu_div_ctl.scala 144:65]
|
||||||
|
wire [3:0] shortq_raw = {_T_530,_T_553,_T_570,_T_581}; // @[Cat.scala 29:58]
|
||||||
|
wire _T_586 = valid_ff_x & _T_7; // @[el2_exu_div_ctl.scala 148:35]
|
||||||
|
wire _T_587 = shortq_raw != 4'h0; // @[el2_exu_div_ctl.scala 148:78]
|
||||||
|
wire shortq_enable = _T_586 & _T_587; // @[el2_exu_div_ctl.scala 148:64]
|
||||||
|
wire [3:0] _T_589 = shortq_enable ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
||||||
|
reg [3:0] shortq_shift_xx; // @[el2_exu_div_ctl.scala 215:31]
|
||||||
|
wire [4:0] _T_598 = shortq_shift_xx[3] ? 5'h1f : 5'h0; // @[Mux.scala 27:72]
|
||||||
|
wire [4:0] _T_599 = shortq_shift_xx[2] ? 5'h18 : 5'h0; // @[Mux.scala 27:72]
|
||||||
|
wire [4:0] _T_600 = shortq_shift_xx[1] ? 5'h10 : 5'h0; // @[Mux.scala 27:72]
|
||||||
|
wire [3:0] _T_601 = shortq_shift_xx[0] ? 4'h8 : 4'h0; // @[Mux.scala 27:72]
|
||||||
|
wire [4:0] _T_602 = _T_598 | _T_599; // @[Mux.scala 27:72]
|
||||||
|
wire [4:0] _T_603 = _T_602 | _T_600; // @[Mux.scala 27:72]
|
||||||
|
wire [4:0] _GEN_4 = {{1'd0}, _T_601}; // @[Mux.scala 27:72]
|
||||||
|
wire [4:0] shortq_shift_ff = _T_603 | _GEN_4; // @[Mux.scala 27:72]
|
||||||
|
reg [5:0] count; // @[el2_exu_div_ctl.scala 207:21]
|
||||||
|
wire _T_606 = count == 6'h20; // @[el2_exu_div_ctl.scala 159:55]
|
||||||
|
wire _T_607 = count == 6'h21; // @[el2_exu_div_ctl.scala 159:76]
|
||||||
|
wire _T_608 = _T_9 ? _T_606 : _T_607; // @[el2_exu_div_ctl.scala 159:39]
|
||||||
|
wire finish = smallnum_case | _T_608; // @[el2_exu_div_ctl.scala 159:34]
|
||||||
|
reg run_state; // @[el2_exu_div_ctl.scala 206:25]
|
||||||
|
wire _T_609 = io_dp_valid | run_state; // @[el2_exu_div_ctl.scala 160:32]
|
||||||
|
wire _T_610 = _T_609 | finish; // @[el2_exu_div_ctl.scala 160:44]
|
||||||
|
reg finish_ff; // @[el2_exu_div_ctl.scala 205:25]
|
||||||
|
wire _T_612 = ~finish; // @[el2_exu_div_ctl.scala 161:48]
|
||||||
|
wire _T_613 = _T_609 & _T_612; // @[el2_exu_div_ctl.scala 161:46]
|
||||||
|
wire _T_616 = run_state & _T_612; // @[el2_exu_div_ctl.scala 162:35]
|
||||||
|
wire _T_618 = _T_616 & _T; // @[el2_exu_div_ctl.scala 162:45]
|
||||||
|
wire _T_619 = ~shortq_enable; // @[el2_exu_div_ctl.scala 162:60]
|
||||||
|
wire _T_620 = _T_618 & _T_619; // @[el2_exu_div_ctl.scala 162:58]
|
||||||
|
wire [5:0] _T_622 = _T_620 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12]
|
||||||
|
wire [5:0] _T_623 = {1'h0,shortq_shift_ff}; // @[Cat.scala 29:58]
|
||||||
|
wire [5:0] _T_625 = count + _T_623; // @[el2_exu_div_ctl.scala 162:86]
|
||||||
|
wire [5:0] _T_627 = _T_625 + 6'h1; // @[el2_exu_div_ctl.scala 162:113]
|
||||||
|
wire _T_631 = ~io_dp_unsign; // @[el2_exu_div_ctl.scala 166:20]
|
||||||
|
wire _T_632 = io_divisor != 32'h0; // @[el2_exu_div_ctl.scala 166:48]
|
||||||
|
wire sign_eff = _T_631 & _T_632; // @[el2_exu_div_ctl.scala 166:34]
|
||||||
|
wire _T_633 = ~run_state; // @[el2_exu_div_ctl.scala 170:6]
|
||||||
|
wire [32:0] _T_635 = {1'h0,io_dividend}; // @[Cat.scala 29:58]
|
||||||
|
reg shortq_enable_ff; // @[el2_exu_div_ctl.scala 214:32]
|
||||||
|
wire _T_636 = valid_ff_x | shortq_enable_ff; // @[el2_exu_div_ctl.scala 171:30]
|
||||||
|
wire _T_637 = run_state & _T_636; // @[el2_exu_div_ctl.scala 171:16]
|
||||||
|
reg dividend_neg_ff; // @[Reg.scala 27:20]
|
||||||
|
wire _T_660 = sign_ff & dividend_neg_ff; // @[el2_exu_div_ctl.scala 175:32]
|
||||||
|
wire _T_845 = |q_ff[30:0]; // @[el2_lib.scala 520:35]
|
||||||
|
wire _T_847 = ~q_ff[31]; // @[el2_lib.scala 520:40]
|
||||||
|
wire _T_849 = _T_845 ? _T_847 : q_ff[31]; // @[el2_lib.scala 520:23]
|
||||||
|
wire _T_839 = |q_ff[29:0]; // @[el2_lib.scala 520:35]
|
||||||
|
wire _T_841 = ~q_ff[30]; // @[el2_lib.scala 520:40]
|
||||||
|
wire _T_843 = _T_839 ? _T_841 : q_ff[30]; // @[el2_lib.scala 520:23]
|
||||||
|
wire _T_833 = |q_ff[28:0]; // @[el2_lib.scala 520:35]
|
||||||
|
wire _T_835 = ~q_ff[29]; // @[el2_lib.scala 520:40]
|
||||||
|
wire _T_837 = _T_833 ? _T_835 : q_ff[29]; // @[el2_lib.scala 520:23]
|
||||||
|
wire _T_827 = |q_ff[27:0]; // @[el2_lib.scala 520:35]
|
||||||
|
wire _T_829 = ~q_ff[28]; // @[el2_lib.scala 520:40]
|
||||||
|
wire _T_831 = _T_827 ? _T_829 : q_ff[28]; // @[el2_lib.scala 520:23]
|
||||||
|
wire _T_821 = |q_ff[26:0]; // @[el2_lib.scala 520:35]
|
||||||
|
wire _T_823 = ~q_ff[27]; // @[el2_lib.scala 520:40]
|
||||||
|
wire _T_825 = _T_821 ? _T_823 : q_ff[27]; // @[el2_lib.scala 520:23]
|
||||||
|
wire _T_815 = |q_ff[25:0]; // @[el2_lib.scala 520:35]
|
||||||
|
wire _T_817 = ~q_ff[26]; // @[el2_lib.scala 520:40]
|
||||||
|
wire _T_819 = _T_815 ? _T_817 : q_ff[26]; // @[el2_lib.scala 520:23]
|
||||||
|
wire _T_809 = |q_ff[24:0]; // @[el2_lib.scala 520:35]
|
||||||
|
wire _T_811 = ~q_ff[25]; // @[el2_lib.scala 520:40]
|
||||||
|
wire _T_813 = _T_809 ? _T_811 : q_ff[25]; // @[el2_lib.scala 520:23]
|
||||||
|
wire _T_803 = |q_ff[23:0]; // @[el2_lib.scala 520:35]
|
||||||
|
wire _T_805 = ~q_ff[24]; // @[el2_lib.scala 520:40]
|
||||||
|
wire _T_807 = _T_803 ? _T_805 : q_ff[24]; // @[el2_lib.scala 520:23]
|
||||||
|
wire _T_797 = |q_ff[22:0]; // @[el2_lib.scala 520:35]
|
||||||
|
wire _T_799 = ~q_ff[23]; // @[el2_lib.scala 520:40]
|
||||||
|
wire _T_801 = _T_797 ? _T_799 : q_ff[23]; // @[el2_lib.scala 520:23]
|
||||||
|
wire _T_791 = |q_ff[21:0]; // @[el2_lib.scala 520:35]
|
||||||
|
wire _T_793 = ~q_ff[22]; // @[el2_lib.scala 520:40]
|
||||||
|
wire _T_795 = _T_791 ? _T_793 : q_ff[22]; // @[el2_lib.scala 520:23]
|
||||||
|
wire _T_785 = |q_ff[20:0]; // @[el2_lib.scala 520:35]
|
||||||
|
wire _T_787 = ~q_ff[21]; // @[el2_lib.scala 520:40]
|
||||||
|
wire _T_789 = _T_785 ? _T_787 : q_ff[21]; // @[el2_lib.scala 520:23]
|
||||||
|
wire _T_779 = |q_ff[19:0]; // @[el2_lib.scala 520:35]
|
||||||
|
wire _T_781 = ~q_ff[20]; // @[el2_lib.scala 520:40]
|
||||||
|
wire _T_783 = _T_779 ? _T_781 : q_ff[20]; // @[el2_lib.scala 520:23]
|
||||||
|
wire _T_773 = |q_ff[18:0]; // @[el2_lib.scala 520:35]
|
||||||
|
wire _T_775 = ~q_ff[19]; // @[el2_lib.scala 520:40]
|
||||||
|
wire _T_777 = _T_773 ? _T_775 : q_ff[19]; // @[el2_lib.scala 520:23]
|
||||||
|
wire _T_767 = |q_ff[17:0]; // @[el2_lib.scala 520:35]
|
||||||
|
wire _T_769 = ~q_ff[18]; // @[el2_lib.scala 520:40]
|
||||||
|
wire _T_771 = _T_767 ? _T_769 : q_ff[18]; // @[el2_lib.scala 520:23]
|
||||||
|
wire _T_761 = |q_ff[16:0]; // @[el2_lib.scala 520:35]
|
||||||
|
wire _T_763 = ~q_ff[17]; // @[el2_lib.scala 520:40]
|
||||||
|
wire _T_765 = _T_761 ? _T_763 : q_ff[17]; // @[el2_lib.scala 520:23]
|
||||||
|
wire _T_755 = |q_ff[15:0]; // @[el2_lib.scala 520:35]
|
||||||
|
wire _T_757 = ~q_ff[16]; // @[el2_lib.scala 520:40]
|
||||||
|
wire _T_759 = _T_755 ? _T_757 : q_ff[16]; // @[el2_lib.scala 520:23]
|
||||||
|
wire [7:0] _T_870 = {_T_801,_T_795,_T_789,_T_783,_T_777,_T_771,_T_765,_T_759}; // @[el2_lib.scala 522:14]
|
||||||
|
wire _T_749 = |q_ff[14:0]; // @[el2_lib.scala 520:35]
|
||||||
|
wire _T_751 = ~q_ff[15]; // @[el2_lib.scala 520:40]
|
||||||
|
wire _T_753 = _T_749 ? _T_751 : q_ff[15]; // @[el2_lib.scala 520:23]
|
||||||
|
wire _T_743 = |q_ff[13:0]; // @[el2_lib.scala 520:35]
|
||||||
|
wire _T_745 = ~q_ff[14]; // @[el2_lib.scala 520:40]
|
||||||
|
wire _T_747 = _T_743 ? _T_745 : q_ff[14]; // @[el2_lib.scala 520:23]
|
||||||
|
wire _T_737 = |q_ff[12:0]; // @[el2_lib.scala 520:35]
|
||||||
|
wire _T_739 = ~q_ff[13]; // @[el2_lib.scala 520:40]
|
||||||
|
wire _T_741 = _T_737 ? _T_739 : q_ff[13]; // @[el2_lib.scala 520:23]
|
||||||
|
wire _T_731 = |q_ff[11:0]; // @[el2_lib.scala 520:35]
|
||||||
|
wire _T_733 = ~q_ff[12]; // @[el2_lib.scala 520:40]
|
||||||
|
wire _T_735 = _T_731 ? _T_733 : q_ff[12]; // @[el2_lib.scala 520:23]
|
||||||
|
wire _T_725 = |q_ff[10:0]; // @[el2_lib.scala 520:35]
|
||||||
|
wire _T_727 = ~q_ff[11]; // @[el2_lib.scala 520:40]
|
||||||
|
wire _T_729 = _T_725 ? _T_727 : q_ff[11]; // @[el2_lib.scala 520:23]
|
||||||
|
wire _T_719 = |q_ff[9:0]; // @[el2_lib.scala 520:35]
|
||||||
|
wire _T_721 = ~q_ff[10]; // @[el2_lib.scala 520:40]
|
||||||
|
wire _T_723 = _T_719 ? _T_721 : q_ff[10]; // @[el2_lib.scala 520:23]
|
||||||
|
wire _T_713 = |q_ff[8:0]; // @[el2_lib.scala 520:35]
|
||||||
|
wire _T_715 = ~q_ff[9]; // @[el2_lib.scala 520:40]
|
||||||
|
wire _T_717 = _T_713 ? _T_715 : q_ff[9]; // @[el2_lib.scala 520:23]
|
||||||
|
wire _T_707 = |q_ff[7:0]; // @[el2_lib.scala 520:35]
|
||||||
|
wire _T_709 = ~q_ff[8]; // @[el2_lib.scala 520:40]
|
||||||
|
wire _T_711 = _T_707 ? _T_709 : q_ff[8]; // @[el2_lib.scala 520:23]
|
||||||
|
wire _T_701 = |q_ff[6:0]; // @[el2_lib.scala 520:35]
|
||||||
|
wire _T_703 = ~q_ff[7]; // @[el2_lib.scala 520:40]
|
||||||
|
wire _T_705 = _T_701 ? _T_703 : q_ff[7]; // @[el2_lib.scala 520:23]
|
||||||
|
wire _T_695 = |q_ff[5:0]; // @[el2_lib.scala 520:35]
|
||||||
|
wire _T_697 = ~q_ff[6]; // @[el2_lib.scala 520:40]
|
||||||
|
wire _T_699 = _T_695 ? _T_697 : q_ff[6]; // @[el2_lib.scala 520:23]
|
||||||
|
wire _T_689 = |q_ff[4:0]; // @[el2_lib.scala 520:35]
|
||||||
|
wire _T_691 = ~q_ff[5]; // @[el2_lib.scala 520:40]
|
||||||
|
wire _T_693 = _T_689 ? _T_691 : q_ff[5]; // @[el2_lib.scala 520:23]
|
||||||
|
wire _T_683 = |q_ff[3:0]; // @[el2_lib.scala 520:35]
|
||||||
|
wire _T_685 = ~q_ff[4]; // @[el2_lib.scala 520:40]
|
||||||
|
wire _T_687 = _T_683 ? _T_685 : q_ff[4]; // @[el2_lib.scala 520:23]
|
||||||
|
wire _T_677 = |q_ff[2:0]; // @[el2_lib.scala 520:35]
|
||||||
|
wire _T_679 = ~q_ff[3]; // @[el2_lib.scala 520:40]
|
||||||
|
wire _T_681 = _T_677 ? _T_679 : q_ff[3]; // @[el2_lib.scala 520:23]
|
||||||
|
wire _T_671 = |q_ff[1:0]; // @[el2_lib.scala 520:35]
|
||||||
|
wire _T_673 = ~q_ff[2]; // @[el2_lib.scala 520:40]
|
||||||
|
wire _T_675 = _T_671 ? _T_673 : q_ff[2]; // @[el2_lib.scala 520:23]
|
||||||
|
wire _T_665 = |q_ff[0]; // @[el2_lib.scala 520:35]
|
||||||
|
wire _T_667 = ~q_ff[1]; // @[el2_lib.scala 520:40]
|
||||||
|
wire _T_669 = _T_665 ? _T_667 : q_ff[1]; // @[el2_lib.scala 520:23]
|
||||||
|
wire [6:0] _T_855 = {_T_705,_T_699,_T_693,_T_687,_T_681,_T_675,_T_669}; // @[el2_lib.scala 522:14]
|
||||||
|
wire [14:0] _T_863 = {_T_753,_T_747,_T_741,_T_735,_T_729,_T_723,_T_717,_T_711,_T_855}; // @[el2_lib.scala 522:14]
|
||||||
|
wire [30:0] _T_879 = {_T_849,_T_843,_T_837,_T_831,_T_825,_T_819,_T_813,_T_807,_T_870,_T_863}; // @[el2_lib.scala 522:14]
|
||||||
|
wire [31:0] _T_881 = {_T_879,q_ff[0]}; // @[Cat.scala 29:58]
|
||||||
|
wire [31:0] dividend_eff = _T_660 ? _T_881 : q_ff[31:0]; // @[el2_exu_div_ctl.scala 175:22]
|
||||||
|
wire [32:0] _T_917 = run_state ? 33'h1ffffffff : 33'h0; // @[Bitwise.scala 72:12]
|
||||||
|
wire _T_929 = _T_607 & rem_ff; // @[el2_exu_div_ctl.scala 191:41]
|
||||||
|
reg [32:0] a_ff; // @[el2_lib.scala 491:16]
|
||||||
|
wire rem_correct = _T_929 & a_ff[32]; // @[el2_exu_div_ctl.scala 191:50]
|
||||||
|
wire [32:0] _T_902 = rem_correct ? a_ff : 33'h0; // @[Mux.scala 27:72]
|
||||||
|
wire _T_890 = ~rem_correct; // @[el2_exu_div_ctl.scala 182:6]
|
||||||
|
wire _T_891 = ~shortq_enable_ff; // @[el2_exu_div_ctl.scala 182:21]
|
||||||
|
wire _T_892 = _T_890 & _T_891; // @[el2_exu_div_ctl.scala 182:19]
|
||||||
|
wire [32:0] _T_896 = {a_ff[31:0],q_ff[32]}; // @[Cat.scala 29:58]
|
||||||
|
wire [32:0] _T_903 = _T_892 ? _T_896 : 33'h0; // @[Mux.scala 27:72]
|
||||||
|
wire [32:0] _T_905 = _T_902 | _T_903; // @[Mux.scala 27:72]
|
||||||
|
wire _T_898 = _T_890 & shortq_enable_ff; // @[el2_exu_div_ctl.scala 183:19]
|
||||||
|
wire [55:0] _T_887 = {24'h0,dividend_eff}; // @[Cat.scala 29:58]
|
||||||
|
wire [86:0] _GEN_5 = {{31'd0}, _T_887}; // @[el2_exu_div_ctl.scala 179:47]
|
||||||
|
wire [86:0] _T_888 = _GEN_5 << shortq_shift_ff; // @[el2_exu_div_ctl.scala 179:47]
|
||||||
|
wire [55:0] a_eff_shift = _T_888[55:0]; // @[el2_exu_div_ctl.scala 179:15]
|
||||||
|
wire [32:0] _T_901 = {9'h0,a_eff_shift[55:32]}; // @[Cat.scala 29:58]
|
||||||
|
wire [32:0] _T_904 = _T_898 ? _T_901 : 33'h0; // @[Mux.scala 27:72]
|
||||||
|
wire [32:0] a_eff = _T_905 | _T_904; // @[Mux.scala 27:72]
|
||||||
|
wire [32:0] a_shift = _T_917 & a_eff; // @[el2_exu_div_ctl.scala 186:33]
|
||||||
|
wire _T_926 = a_ff[32] | rem_correct; // @[el2_exu_div_ctl.scala 190:21]
|
||||||
|
reg divisor_neg_ff; // @[Reg.scala 27:20]
|
||||||
|
wire m_already_comp = divisor_neg_ff & sign_ff; // @[el2_exu_div_ctl.scala 188:48]
|
||||||
|
wire add = _T_926 ^ m_already_comp; // @[el2_exu_div_ctl.scala 190:36]
|
||||||
|
wire [32:0] _T_885 = ~m_ff; // @[el2_exu_div_ctl.scala 178:35]
|
||||||
|
wire [32:0] m_eff = add ? m_ff : _T_885; // @[el2_exu_div_ctl.scala 178:15]
|
||||||
|
wire [32:0] _T_919 = a_shift + m_eff; // @[el2_exu_div_ctl.scala 187:41]
|
||||||
|
wire _T_920 = ~add; // @[el2_exu_div_ctl.scala 187:65]
|
||||||
|
wire [32:0] _T_921 = {32'h0,_T_920}; // @[Cat.scala 29:58]
|
||||||
|
wire [32:0] _T_923 = _T_919 + _T_921; // @[el2_exu_div_ctl.scala 187:49]
|
||||||
|
wire [32:0] a_in = _T_917 & _T_923; // @[el2_exu_div_ctl.scala 187:30]
|
||||||
|
wire _T_641 = ~a_in[32]; // @[el2_exu_div_ctl.scala 171:85]
|
||||||
|
wire [32:0] _T_642 = {dividend_eff,_T_641}; // @[Cat.scala 29:58]
|
||||||
|
wire [63:0] _GEN_6 = {{31'd0}, _T_642}; // @[el2_exu_div_ctl.scala 171:96]
|
||||||
|
wire [63:0] _T_643 = _GEN_6 << shortq_shift_ff; // @[el2_exu_div_ctl.scala 171:96]
|
||||||
|
wire _T_645 = ~_T_636; // @[el2_exu_div_ctl.scala 172:18]
|
||||||
|
wire _T_646 = run_state & _T_645; // @[el2_exu_div_ctl.scala 172:16]
|
||||||
|
wire [32:0] _T_651 = {q_ff[31:0],_T_641}; // @[Cat.scala 29:58]
|
||||||
|
wire [32:0] _T_652 = _T_633 ? _T_635 : 33'h0; // @[Mux.scala 27:72]
|
||||||
|
wire [63:0] _T_653 = _T_637 ? _T_643 : 64'h0; // @[Mux.scala 27:72]
|
||||||
|
wire [32:0] _T_654 = _T_646 ? _T_651 : 33'h0; // @[Mux.scala 27:72]
|
||||||
|
wire [63:0] _GEN_7 = {{31'd0}, _T_652}; // @[Mux.scala 27:72]
|
||||||
|
wire [63:0] _T_655 = _GEN_7 | _T_653; // @[Mux.scala 27:72]
|
||||||
|
wire [63:0] _GEN_8 = {{31'd0}, _T_654}; // @[Mux.scala 27:72]
|
||||||
|
wire [63:0] _T_656 = _T_655 | _GEN_8; // @[Mux.scala 27:72]
|
||||||
|
wire _T_659 = run_state & _T_619; // @[el2_exu_div_ctl.scala 174:48]
|
||||||
|
wire _T_910 = count != 6'h21; // @[el2_exu_div_ctl.scala 185:73]
|
||||||
|
wire _T_911 = _T_659 & _T_910; // @[el2_exu_div_ctl.scala 185:64]
|
||||||
|
wire _T_912 = io_dp_valid | _T_911; // @[el2_exu_div_ctl.scala 185:34]
|
||||||
|
wire _T_932 = dividend_neg_ff ^ divisor_neg_ff; // @[el2_exu_div_ctl.scala 192:50]
|
||||||
|
wire _T_933 = sign_ff & _T_932; // @[el2_exu_div_ctl.scala 192:31]
|
||||||
|
wire [31:0] q_ff_eff = _T_933 ? _T_881 : q_ff[31:0]; // @[el2_exu_div_ctl.scala 192:21]
|
||||||
|
wire _T_1161 = |a_ff[0]; // @[el2_lib.scala 520:35]
|
||||||
|
wire _T_1163 = ~a_ff[1]; // @[el2_lib.scala 520:40]
|
||||||
|
wire _T_1165 = _T_1161 ? _T_1163 : a_ff[1]; // @[el2_lib.scala 520:23]
|
||||||
|
wire _T_1167 = |a_ff[1:0]; // @[el2_lib.scala 520:35]
|
||||||
|
wire _T_1169 = ~a_ff[2]; // @[el2_lib.scala 520:40]
|
||||||
|
wire _T_1171 = _T_1167 ? _T_1169 : a_ff[2]; // @[el2_lib.scala 520:23]
|
||||||
|
wire _T_1173 = |a_ff[2:0]; // @[el2_lib.scala 520:35]
|
||||||
|
wire _T_1175 = ~a_ff[3]; // @[el2_lib.scala 520:40]
|
||||||
|
wire _T_1177 = _T_1173 ? _T_1175 : a_ff[3]; // @[el2_lib.scala 520:23]
|
||||||
|
wire _T_1179 = |a_ff[3:0]; // @[el2_lib.scala 520:35]
|
||||||
|
wire _T_1181 = ~a_ff[4]; // @[el2_lib.scala 520:40]
|
||||||
|
wire _T_1183 = _T_1179 ? _T_1181 : a_ff[4]; // @[el2_lib.scala 520:23]
|
||||||
|
wire _T_1185 = |a_ff[4:0]; // @[el2_lib.scala 520:35]
|
||||||
|
wire _T_1187 = ~a_ff[5]; // @[el2_lib.scala 520:40]
|
||||||
|
wire _T_1189 = _T_1185 ? _T_1187 : a_ff[5]; // @[el2_lib.scala 520:23]
|
||||||
|
wire _T_1191 = |a_ff[5:0]; // @[el2_lib.scala 520:35]
|
||||||
|
wire _T_1193 = ~a_ff[6]; // @[el2_lib.scala 520:40]
|
||||||
|
wire _T_1195 = _T_1191 ? _T_1193 : a_ff[6]; // @[el2_lib.scala 520:23]
|
||||||
|
wire _T_1197 = |a_ff[6:0]; // @[el2_lib.scala 520:35]
|
||||||
|
wire _T_1199 = ~a_ff[7]; // @[el2_lib.scala 520:40]
|
||||||
|
wire _T_1201 = _T_1197 ? _T_1199 : a_ff[7]; // @[el2_lib.scala 520:23]
|
||||||
|
wire _T_1203 = |a_ff[7:0]; // @[el2_lib.scala 520:35]
|
||||||
|
wire _T_1205 = ~a_ff[8]; // @[el2_lib.scala 520:40]
|
||||||
|
wire _T_1207 = _T_1203 ? _T_1205 : a_ff[8]; // @[el2_lib.scala 520:23]
|
||||||
|
wire _T_1209 = |a_ff[8:0]; // @[el2_lib.scala 520:35]
|
||||||
|
wire _T_1211 = ~a_ff[9]; // @[el2_lib.scala 520:40]
|
||||||
|
wire _T_1213 = _T_1209 ? _T_1211 : a_ff[9]; // @[el2_lib.scala 520:23]
|
||||||
|
wire _T_1215 = |a_ff[9:0]; // @[el2_lib.scala 520:35]
|
||||||
|
wire _T_1217 = ~a_ff[10]; // @[el2_lib.scala 520:40]
|
||||||
|
wire _T_1219 = _T_1215 ? _T_1217 : a_ff[10]; // @[el2_lib.scala 520:23]
|
||||||
|
wire _T_1221 = |a_ff[10:0]; // @[el2_lib.scala 520:35]
|
||||||
|
wire _T_1223 = ~a_ff[11]; // @[el2_lib.scala 520:40]
|
||||||
|
wire _T_1225 = _T_1221 ? _T_1223 : a_ff[11]; // @[el2_lib.scala 520:23]
|
||||||
|
wire _T_1227 = |a_ff[11:0]; // @[el2_lib.scala 520:35]
|
||||||
|
wire _T_1229 = ~a_ff[12]; // @[el2_lib.scala 520:40]
|
||||||
|
wire _T_1231 = _T_1227 ? _T_1229 : a_ff[12]; // @[el2_lib.scala 520:23]
|
||||||
|
wire _T_1233 = |a_ff[12:0]; // @[el2_lib.scala 520:35]
|
||||||
|
wire _T_1235 = ~a_ff[13]; // @[el2_lib.scala 520:40]
|
||||||
|
wire _T_1237 = _T_1233 ? _T_1235 : a_ff[13]; // @[el2_lib.scala 520:23]
|
||||||
|
wire _T_1239 = |a_ff[13:0]; // @[el2_lib.scala 520:35]
|
||||||
|
wire _T_1241 = ~a_ff[14]; // @[el2_lib.scala 520:40]
|
||||||
|
wire _T_1243 = _T_1239 ? _T_1241 : a_ff[14]; // @[el2_lib.scala 520:23]
|
||||||
|
wire _T_1245 = |a_ff[14:0]; // @[el2_lib.scala 520:35]
|
||||||
|
wire _T_1247 = ~a_ff[15]; // @[el2_lib.scala 520:40]
|
||||||
|
wire _T_1249 = _T_1245 ? _T_1247 : a_ff[15]; // @[el2_lib.scala 520:23]
|
||||||
|
wire _T_1251 = |a_ff[15:0]; // @[el2_lib.scala 520:35]
|
||||||
|
wire _T_1253 = ~a_ff[16]; // @[el2_lib.scala 520:40]
|
||||||
|
wire _T_1255 = _T_1251 ? _T_1253 : a_ff[16]; // @[el2_lib.scala 520:23]
|
||||||
|
wire _T_1257 = |a_ff[16:0]; // @[el2_lib.scala 520:35]
|
||||||
|
wire _T_1259 = ~a_ff[17]; // @[el2_lib.scala 520:40]
|
||||||
|
wire _T_1261 = _T_1257 ? _T_1259 : a_ff[17]; // @[el2_lib.scala 520:23]
|
||||||
|
wire _T_1263 = |a_ff[17:0]; // @[el2_lib.scala 520:35]
|
||||||
|
wire _T_1265 = ~a_ff[18]; // @[el2_lib.scala 520:40]
|
||||||
|
wire _T_1267 = _T_1263 ? _T_1265 : a_ff[18]; // @[el2_lib.scala 520:23]
|
||||||
|
wire _T_1269 = |a_ff[18:0]; // @[el2_lib.scala 520:35]
|
||||||
|
wire _T_1271 = ~a_ff[19]; // @[el2_lib.scala 520:40]
|
||||||
|
wire _T_1273 = _T_1269 ? _T_1271 : a_ff[19]; // @[el2_lib.scala 520:23]
|
||||||
|
wire _T_1275 = |a_ff[19:0]; // @[el2_lib.scala 520:35]
|
||||||
|
wire _T_1277 = ~a_ff[20]; // @[el2_lib.scala 520:40]
|
||||||
|
wire _T_1279 = _T_1275 ? _T_1277 : a_ff[20]; // @[el2_lib.scala 520:23]
|
||||||
|
wire _T_1281 = |a_ff[20:0]; // @[el2_lib.scala 520:35]
|
||||||
|
wire _T_1283 = ~a_ff[21]; // @[el2_lib.scala 520:40]
|
||||||
|
wire _T_1285 = _T_1281 ? _T_1283 : a_ff[21]; // @[el2_lib.scala 520:23]
|
||||||
|
wire _T_1287 = |a_ff[21:0]; // @[el2_lib.scala 520:35]
|
||||||
|
wire _T_1289 = ~a_ff[22]; // @[el2_lib.scala 520:40]
|
||||||
|
wire _T_1291 = _T_1287 ? _T_1289 : a_ff[22]; // @[el2_lib.scala 520:23]
|
||||||
|
wire _T_1293 = |a_ff[22:0]; // @[el2_lib.scala 520:35]
|
||||||
|
wire _T_1295 = ~a_ff[23]; // @[el2_lib.scala 520:40]
|
||||||
|
wire _T_1297 = _T_1293 ? _T_1295 : a_ff[23]; // @[el2_lib.scala 520:23]
|
||||||
|
wire _T_1299 = |a_ff[23:0]; // @[el2_lib.scala 520:35]
|
||||||
|
wire _T_1301 = ~a_ff[24]; // @[el2_lib.scala 520:40]
|
||||||
|
wire _T_1303 = _T_1299 ? _T_1301 : a_ff[24]; // @[el2_lib.scala 520:23]
|
||||||
|
wire _T_1305 = |a_ff[24:0]; // @[el2_lib.scala 520:35]
|
||||||
|
wire _T_1307 = ~a_ff[25]; // @[el2_lib.scala 520:40]
|
||||||
|
wire _T_1309 = _T_1305 ? _T_1307 : a_ff[25]; // @[el2_lib.scala 520:23]
|
||||||
|
wire _T_1311 = |a_ff[25:0]; // @[el2_lib.scala 520:35]
|
||||||
|
wire _T_1313 = ~a_ff[26]; // @[el2_lib.scala 520:40]
|
||||||
|
wire _T_1315 = _T_1311 ? _T_1313 : a_ff[26]; // @[el2_lib.scala 520:23]
|
||||||
|
wire _T_1317 = |a_ff[26:0]; // @[el2_lib.scala 520:35]
|
||||||
|
wire _T_1319 = ~a_ff[27]; // @[el2_lib.scala 520:40]
|
||||||
|
wire _T_1321 = _T_1317 ? _T_1319 : a_ff[27]; // @[el2_lib.scala 520:23]
|
||||||
|
wire _T_1323 = |a_ff[27:0]; // @[el2_lib.scala 520:35]
|
||||||
|
wire _T_1325 = ~a_ff[28]; // @[el2_lib.scala 520:40]
|
||||||
|
wire _T_1327 = _T_1323 ? _T_1325 : a_ff[28]; // @[el2_lib.scala 520:23]
|
||||||
|
wire _T_1329 = |a_ff[28:0]; // @[el2_lib.scala 520:35]
|
||||||
|
wire _T_1331 = ~a_ff[29]; // @[el2_lib.scala 520:40]
|
||||||
|
wire _T_1333 = _T_1329 ? _T_1331 : a_ff[29]; // @[el2_lib.scala 520:23]
|
||||||
|
wire _T_1335 = |a_ff[29:0]; // @[el2_lib.scala 520:35]
|
||||||
|
wire _T_1337 = ~a_ff[30]; // @[el2_lib.scala 520:40]
|
||||||
|
wire _T_1339 = _T_1335 ? _T_1337 : a_ff[30]; // @[el2_lib.scala 520:23]
|
||||||
|
wire _T_1341 = |a_ff[30:0]; // @[el2_lib.scala 520:35]
|
||||||
|
wire _T_1343 = ~a_ff[31]; // @[el2_lib.scala 520:40]
|
||||||
|
wire _T_1345 = _T_1341 ? _T_1343 : a_ff[31]; // @[el2_lib.scala 520:23]
|
||||||
|
wire [6:0] _T_1351 = {_T_1201,_T_1195,_T_1189,_T_1183,_T_1177,_T_1171,_T_1165}; // @[el2_lib.scala 522:14]
|
||||||
|
wire [14:0] _T_1359 = {_T_1249,_T_1243,_T_1237,_T_1231,_T_1225,_T_1219,_T_1213,_T_1207,_T_1351}; // @[el2_lib.scala 522:14]
|
||||||
|
wire [7:0] _T_1366 = {_T_1297,_T_1291,_T_1285,_T_1279,_T_1273,_T_1267,_T_1261,_T_1255}; // @[el2_lib.scala 522:14]
|
||||||
|
wire [30:0] _T_1375 = {_T_1345,_T_1339,_T_1333,_T_1327,_T_1321,_T_1315,_T_1309,_T_1303,_T_1366,_T_1359}; // @[el2_lib.scala 522:14]
|
||||||
|
wire [31:0] _T_1377 = {_T_1375,a_ff[0]}; // @[Cat.scala 29:58]
|
||||||
|
wire [31:0] a_ff_eff = _T_660 ? _T_1377 : a_ff[31:0]; // @[el2_exu_div_ctl.scala 193:21]
|
||||||
|
reg smallnum_case_ff; // @[el2_exu_div_ctl.scala 212:32]
|
||||||
|
reg [3:0] smallnum_ff; // @[el2_exu_div_ctl.scala 213:27]
|
||||||
|
wire [31:0] _T_1380 = {28'h0,smallnum_ff}; // @[Cat.scala 29:58]
|
||||||
|
wire _T_1382 = ~smallnum_case_ff; // @[el2_exu_div_ctl.scala 198:6]
|
||||||
|
wire _T_1384 = _T_1382 & _T_9; // @[el2_exu_div_ctl.scala 198:24]
|
||||||
|
wire [31:0] _T_1386 = smallnum_case_ff ? _T_1380 : 32'h0; // @[Mux.scala 27:72]
|
||||||
|
wire [31:0] _T_1387 = rem_ff ? a_ff_eff : 32'h0; // @[Mux.scala 27:72]
|
||||||
|
wire [31:0] _T_1388 = _T_1384 ? q_ff_eff : 32'h0; // @[Mux.scala 27:72]
|
||||||
|
wire [31:0] _T_1389 = _T_1386 | _T_1387; // @[Mux.scala 27:72]
|
||||||
|
wire _T_1421 = _T_631 & io_divisor[31]; // @[el2_exu_div_ctl.scala 219:36]
|
||||||
|
rvclkhdr rvclkhdr ( // @[el2_lib.scala 474:22]
|
||||||
|
.io_l1clk(rvclkhdr_io_l1clk),
|
||||||
|
.io_clk(rvclkhdr_io_clk),
|
||||||
|
.io_en(rvclkhdr_io_en),
|
||||||
|
.io_scan_mode(rvclkhdr_io_scan_mode)
|
||||||
|
);
|
||||||
|
rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 485:23]
|
||||||
|
.io_l1clk(rvclkhdr_1_io_l1clk),
|
||||||
|
.io_clk(rvclkhdr_1_io_clk),
|
||||||
|
.io_en(rvclkhdr_1_io_en),
|
||||||
|
.io_scan_mode(rvclkhdr_1_io_scan_mode)
|
||||||
|
);
|
||||||
|
rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 485:23]
|
||||||
|
.io_l1clk(rvclkhdr_2_io_l1clk),
|
||||||
|
.io_clk(rvclkhdr_2_io_clk),
|
||||||
|
.io_en(rvclkhdr_2_io_en),
|
||||||
|
.io_scan_mode(rvclkhdr_2_io_scan_mode)
|
||||||
|
);
|
||||||
|
rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 485:23]
|
||||||
|
.io_l1clk(rvclkhdr_3_io_l1clk),
|
||||||
|
.io_clk(rvclkhdr_3_io_clk),
|
||||||
|
.io_en(rvclkhdr_3_io_en),
|
||||||
|
.io_scan_mode(rvclkhdr_3_io_scan_mode)
|
||||||
|
);
|
||||||
|
assign io_out = _T_1389 | _T_1388; // @[el2_exu_div_ctl.scala 50:10 el2_exu_div_ctl.scala 195:10]
|
||||||
|
assign io_finish_dly = finish_ff & _T; // @[el2_exu_div_ctl.scala 51:17 el2_exu_div_ctl.scala 165:18]
|
||||||
|
assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 475:17]
|
||||||
|
assign rvclkhdr_io_en = _T_610 | finish_ff; // @[el2_lib.scala 476:16]
|
||||||
|
assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 477:23]
|
||||||
|
assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 487:18]
|
||||||
|
assign rvclkhdr_1_io_en = io_dp_valid | _T_659; // @[el2_lib.scala 488:17]
|
||||||
|
assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24]
|
||||||
|
assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 487:18]
|
||||||
|
assign rvclkhdr_2_io_en = _T_912 | rem_correct; // @[el2_lib.scala 488:17]
|
||||||
|
assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24]
|
||||||
|
assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 487:18]
|
||||||
|
assign rvclkhdr_3_io_en = io_dp_valid; // @[el2_lib.scala 488:17]
|
||||||
|
assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24]
|
||||||
|
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
||||||
|
`define RANDOMIZE
|
||||||
|
`endif
|
||||||
|
`ifdef RANDOMIZE_INVALID_ASSIGN
|
||||||
|
`define RANDOMIZE
|
||||||
|
`endif
|
||||||
|
`ifdef RANDOMIZE_REG_INIT
|
||||||
|
`define RANDOMIZE
|
||||||
|
`endif
|
||||||
|
`ifdef RANDOMIZE_MEM_INIT
|
||||||
|
`define RANDOMIZE
|
||||||
|
`endif
|
||||||
|
`ifndef RANDOM
|
||||||
|
`define RANDOM $random
|
||||||
|
`endif
|
||||||
|
`ifdef RANDOMIZE_MEM_INIT
|
||||||
|
integer initvar;
|
||||||
|
`endif
|
||||||
|
`ifndef SYNTHESIS
|
||||||
|
`ifdef FIRRTL_BEFORE_INITIAL
|
||||||
|
`FIRRTL_BEFORE_INITIAL
|
||||||
|
`endif
|
||||||
|
initial begin
|
||||||
|
`ifdef RANDOMIZE
|
||||||
|
`ifdef INIT_RANDOM
|
||||||
|
`INIT_RANDOM
|
||||||
|
`endif
|
||||||
|
`ifndef VERILATOR
|
||||||
|
`ifdef RANDOMIZE_DELAY
|
||||||
|
#`RANDOMIZE_DELAY begin end
|
||||||
|
`else
|
||||||
|
#0.002 begin end
|
||||||
|
`endif
|
||||||
|
`endif
|
||||||
|
`ifdef RANDOMIZE_REG_INIT
|
||||||
|
_RAND_0 = {1{`RANDOM}};
|
||||||
|
valid_ff_x = _RAND_0[0:0];
|
||||||
|
_RAND_1 = {2{`RANDOM}};
|
||||||
|
q_ff = _RAND_1[32:0];
|
||||||
|
_RAND_2 = {2{`RANDOM}};
|
||||||
|
m_ff = _RAND_2[32:0];
|
||||||
|
_RAND_3 = {1{`RANDOM}};
|
||||||
|
rem_ff = _RAND_3[0:0];
|
||||||
|
_RAND_4 = {1{`RANDOM}};
|
||||||
|
sign_ff = _RAND_4[0:0];
|
||||||
|
_RAND_5 = {1{`RANDOM}};
|
||||||
|
shortq_shift_xx = _RAND_5[3:0];
|
||||||
|
_RAND_6 = {1{`RANDOM}};
|
||||||
|
count = _RAND_6[5:0];
|
||||||
|
_RAND_7 = {1{`RANDOM}};
|
||||||
|
run_state = _RAND_7[0:0];
|
||||||
|
_RAND_8 = {1{`RANDOM}};
|
||||||
|
finish_ff = _RAND_8[0:0];
|
||||||
|
_RAND_9 = {1{`RANDOM}};
|
||||||
|
shortq_enable_ff = _RAND_9[0:0];
|
||||||
|
_RAND_10 = {1{`RANDOM}};
|
||||||
|
dividend_neg_ff = _RAND_10[0:0];
|
||||||
|
_RAND_11 = {2{`RANDOM}};
|
||||||
|
a_ff = _RAND_11[32:0];
|
||||||
|
_RAND_12 = {1{`RANDOM}};
|
||||||
|
divisor_neg_ff = _RAND_12[0:0];
|
||||||
|
_RAND_13 = {1{`RANDOM}};
|
||||||
|
smallnum_case_ff = _RAND_13[0:0];
|
||||||
|
_RAND_14 = {1{`RANDOM}};
|
||||||
|
smallnum_ff = _RAND_14[3:0];
|
||||||
|
`endif // RANDOMIZE_REG_INIT
|
||||||
|
if (reset) begin
|
||||||
|
valid_ff_x = 1'h0;
|
||||||
|
end
|
||||||
|
if (reset) begin
|
||||||
|
q_ff = 33'h0;
|
||||||
|
end
|
||||||
|
if (reset) begin
|
||||||
|
m_ff = 33'h0;
|
||||||
|
end
|
||||||
|
if (reset) begin
|
||||||
|
rem_ff = 1'h0;
|
||||||
|
end
|
||||||
|
if (reset) begin
|
||||||
|
sign_ff = 1'h0;
|
||||||
|
end
|
||||||
|
if (reset) begin
|
||||||
|
shortq_shift_xx = 4'h0;
|
||||||
|
end
|
||||||
|
if (reset) begin
|
||||||
|
count = 6'h0;
|
||||||
|
end
|
||||||
|
if (reset) begin
|
||||||
|
run_state = 1'h0;
|
||||||
|
end
|
||||||
|
if (reset) begin
|
||||||
|
finish_ff = 1'h0;
|
||||||
|
end
|
||||||
|
if (reset) begin
|
||||||
|
shortq_enable_ff = 1'h0;
|
||||||
|
end
|
||||||
|
if (reset) begin
|
||||||
|
dividend_neg_ff = 1'h0;
|
||||||
|
end
|
||||||
|
if (reset) begin
|
||||||
|
a_ff = 33'h0;
|
||||||
|
end
|
||||||
|
if (reset) begin
|
||||||
|
divisor_neg_ff = 1'h0;
|
||||||
|
end
|
||||||
|
if (reset) begin
|
||||||
|
smallnum_case_ff = 1'h0;
|
||||||
|
end
|
||||||
|
if (reset) begin
|
||||||
|
smallnum_ff = 4'h0;
|
||||||
|
end
|
||||||
|
`endif // RANDOMIZE
|
||||||
|
end // initial
|
||||||
|
`ifdef FIRRTL_AFTER_INITIAL
|
||||||
|
`FIRRTL_AFTER_INITIAL
|
||||||
|
`endif
|
||||||
|
`endif // SYNTHESIS
|
||||||
|
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
|
||||||
|
if (reset) begin
|
||||||
|
valid_ff_x <= 1'h0;
|
||||||
|
end else begin
|
||||||
|
valid_ff_x <= io_dp_valid & _T;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin
|
||||||
|
if (reset) begin
|
||||||
|
q_ff <= 33'h0;
|
||||||
|
end else begin
|
||||||
|
q_ff <= _T_656[32:0];
|
||||||
|
end
|
||||||
|
end
|
||||||
|
always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin
|
||||||
|
if (reset) begin
|
||||||
|
m_ff <= 33'h0;
|
||||||
|
end else begin
|
||||||
|
m_ff <= {_T_1421,io_divisor};
|
||||||
|
end
|
||||||
|
end
|
||||||
|
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
|
||||||
|
if (reset) begin
|
||||||
|
rem_ff <= 1'h0;
|
||||||
|
end else if (io_dp_valid) begin
|
||||||
|
rem_ff <= io_dp_rem;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
|
||||||
|
if (reset) begin
|
||||||
|
sign_ff <= 1'h0;
|
||||||
|
end else if (io_dp_valid) begin
|
||||||
|
sign_ff <= sign_eff;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
|
||||||
|
if (reset) begin
|
||||||
|
shortq_shift_xx <= 4'h0;
|
||||||
|
end else begin
|
||||||
|
shortq_shift_xx <= _T_589 & shortq_raw;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
|
||||||
|
if (reset) begin
|
||||||
|
count <= 6'h0;
|
||||||
|
end else begin
|
||||||
|
count <= _T_622 & _T_627;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
|
||||||
|
if (reset) begin
|
||||||
|
run_state <= 1'h0;
|
||||||
|
end else begin
|
||||||
|
run_state <= _T_613 & _T;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
|
||||||
|
if (reset) begin
|
||||||
|
finish_ff <= 1'h0;
|
||||||
|
end else begin
|
||||||
|
finish_ff <= finish & _T;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
|
||||||
|
if (reset) begin
|
||||||
|
shortq_enable_ff <= 1'h0;
|
||||||
|
end else begin
|
||||||
|
shortq_enable_ff <= _T_586 & _T_587;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
|
||||||
|
if (reset) begin
|
||||||
|
dividend_neg_ff <= 1'h0;
|
||||||
|
end else if (io_dp_valid) begin
|
||||||
|
dividend_neg_ff <= io_dividend[31];
|
||||||
|
end
|
||||||
|
end
|
||||||
|
always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
|
||||||
|
if (reset) begin
|
||||||
|
a_ff <= 33'h0;
|
||||||
|
end else begin
|
||||||
|
a_ff <= _T_917 & _T_923;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
|
||||||
|
if (reset) begin
|
||||||
|
divisor_neg_ff <= 1'h0;
|
||||||
|
end else if (io_dp_valid) begin
|
||||||
|
divisor_neg_ff <= io_divisor[31];
|
||||||
|
end
|
||||||
|
end
|
||||||
|
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
|
||||||
|
if (reset) begin
|
||||||
|
smallnum_case_ff <= 1'h0;
|
||||||
|
end else begin
|
||||||
|
smallnum_case_ff <= _T_11 | _T_19;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
|
||||||
|
if (reset) begin
|
||||||
|
smallnum_ff <= 4'h0;
|
||||||
|
end else begin
|
||||||
|
smallnum_ff <= {_T_399,_T_398};
|
||||||
|
end
|
||||||
|
end
|
||||||
|
endmodule
|
||||||
|
|
@ -0,0 +1,23 @@
|
||||||
|
[
|
||||||
|
{
|
||||||
|
"class":"firrtl.EmitCircuitAnnotation",
|
||||||
|
"emitter":"firrtl.VerilogEmitter"
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"class":"firrtl.transforms.BlackBoxResourceAnno",
|
||||||
|
"target":"el2_exu_mul_ctl.TEC_RV_ICG",
|
||||||
|
"resourceId":"/vsrc/TEC_RV_ICG.v"
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"class":"firrtl.options.TargetDirAnnotation",
|
||||||
|
"directory":"."
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"class":"firrtl.options.OutputAnnotationFileAnnotation",
|
||||||
|
"file":"el2_exu_mul_ctl"
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
|
||||||
|
"targetDir":"."
|
||||||
|
}
|
||||||
|
]
|
||||||
|
|
@ -0,0 +1,145 @@
|
||||||
|
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
|
||||||
|
circuit el2_exu_mul_ctl :
|
||||||
|
extmodule TEC_RV_ICG :
|
||||||
|
output Q : Clock
|
||||||
|
input CK : Clock
|
||||||
|
input EN : UInt<1>
|
||||||
|
input SE : UInt<1>
|
||||||
|
|
||||||
|
defname = TEC_RV_ICG
|
||||||
|
|
||||||
|
|
||||||
|
module rvclkhdr :
|
||||||
|
input clock : Clock
|
||||||
|
input reset : Reset
|
||||||
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||||||
|
|
||||||
|
inst clkhdr of TEC_RV_ICG @[el2_lib.scala 465:26]
|
||||||
|
clkhdr.SE is invalid
|
||||||
|
clkhdr.EN is invalid
|
||||||
|
clkhdr.CK is invalid
|
||||||
|
clkhdr.Q is invalid
|
||||||
|
io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14]
|
||||||
|
clkhdr.CK <= io.clk @[el2_lib.scala 467:18]
|
||||||
|
clkhdr.EN <= io.en @[el2_lib.scala 468:18]
|
||||||
|
clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18]
|
||||||
|
|
||||||
|
extmodule TEC_RV_ICG_1 :
|
||||||
|
output Q : Clock
|
||||||
|
input CK : Clock
|
||||||
|
input EN : UInt<1>
|
||||||
|
input SE : UInt<1>
|
||||||
|
|
||||||
|
defname = TEC_RV_ICG
|
||||||
|
|
||||||
|
|
||||||
|
module rvclkhdr_1 :
|
||||||
|
input clock : Clock
|
||||||
|
input reset : Reset
|
||||||
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||||||
|
|
||||||
|
inst clkhdr of TEC_RV_ICG_1 @[el2_lib.scala 465:26]
|
||||||
|
clkhdr.SE is invalid
|
||||||
|
clkhdr.EN is invalid
|
||||||
|
clkhdr.CK is invalid
|
||||||
|
clkhdr.Q is invalid
|
||||||
|
io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14]
|
||||||
|
clkhdr.CK <= io.clk @[el2_lib.scala 467:18]
|
||||||
|
clkhdr.EN <= io.en @[el2_lib.scala 468:18]
|
||||||
|
clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18]
|
||||||
|
|
||||||
|
extmodule TEC_RV_ICG_2 :
|
||||||
|
output Q : Clock
|
||||||
|
input CK : Clock
|
||||||
|
input EN : UInt<1>
|
||||||
|
input SE : UInt<1>
|
||||||
|
|
||||||
|
defname = TEC_RV_ICG
|
||||||
|
|
||||||
|
|
||||||
|
module rvclkhdr_2 :
|
||||||
|
input clock : Clock
|
||||||
|
input reset : Reset
|
||||||
|
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||||||
|
|
||||||
|
inst clkhdr of TEC_RV_ICG_2 @[el2_lib.scala 465:26]
|
||||||
|
clkhdr.SE is invalid
|
||||||
|
clkhdr.EN is invalid
|
||||||
|
clkhdr.CK is invalid
|
||||||
|
clkhdr.Q is invalid
|
||||||
|
io.l1clk <= clkhdr.Q @[el2_lib.scala 466:14]
|
||||||
|
clkhdr.CK <= io.clk @[el2_lib.scala 467:18]
|
||||||
|
clkhdr.EN <= io.en @[el2_lib.scala 468:18]
|
||||||
|
clkhdr.SE <= io.scan_mode @[el2_lib.scala 469:18]
|
||||||
|
|
||||||
|
module el2_exu_mul_ctl :
|
||||||
|
input clock : Clock
|
||||||
|
input reset : AsyncReset
|
||||||
|
output io : {flip scan_mode : UInt<1>, flip mul_p : {valid : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}, flip rs1_in : UInt<32>, flip rs2_in : UInt<32>, result_x : UInt<32>}
|
||||||
|
|
||||||
|
wire rs1_ext_in : SInt<33>
|
||||||
|
rs1_ext_in <= asSInt(UInt<1>("h00"))
|
||||||
|
wire rs2_ext_in : SInt<33>
|
||||||
|
rs2_ext_in <= asSInt(UInt<1>("h00"))
|
||||||
|
wire rs1_x : SInt<33>
|
||||||
|
rs1_x <= asSInt(UInt<1>("h00"))
|
||||||
|
wire rs2_x : SInt<33>
|
||||||
|
rs2_x <= asSInt(UInt<1>("h00"))
|
||||||
|
wire prod_x : SInt<66>
|
||||||
|
prod_x <= asSInt(UInt<1>("h00"))
|
||||||
|
wire low_x : UInt<1>
|
||||||
|
low_x <= UInt<1>("h00")
|
||||||
|
node _T = bits(io.rs1_in, 31, 31) @[el2_exu_mul_ctl.scala 26:50]
|
||||||
|
node _T_1 = and(io.mul_p.rs1_sign, _T) @[el2_exu_mul_ctl.scala 26:39]
|
||||||
|
node _T_2 = cat(_T_1, io.rs1_in) @[Cat.scala 29:58]
|
||||||
|
node _T_3 = asSInt(_T_2) @[el2_exu_mul_ctl.scala 26:66]
|
||||||
|
rs1_ext_in <= _T_3 @[el2_exu_mul_ctl.scala 26:14]
|
||||||
|
node _T_4 = bits(io.rs2_in, 31, 31) @[el2_exu_mul_ctl.scala 27:50]
|
||||||
|
node _T_5 = and(io.mul_p.rs2_sign, _T_4) @[el2_exu_mul_ctl.scala 27:39]
|
||||||
|
node _T_6 = cat(_T_5, io.rs2_in) @[Cat.scala 29:58]
|
||||||
|
node _T_7 = asSInt(_T_6) @[el2_exu_mul_ctl.scala 27:66]
|
||||||
|
rs2_ext_in <= _T_7 @[el2_exu_mul_ctl.scala 27:14]
|
||||||
|
node _T_8 = bits(io.mul_p.valid, 0, 0) @[el2_exu_mul_ctl.scala 36:47]
|
||||||
|
inst rvclkhdr of rvclkhdr @[el2_lib.scala 485:23]
|
||||||
|
rvclkhdr.clock <= clock
|
||||||
|
rvclkhdr.reset <= reset
|
||||||
|
rvclkhdr.io.clk <= clock @[el2_lib.scala 487:18]
|
||||||
|
rvclkhdr.io.en <= _T_8 @[el2_lib.scala 488:17]
|
||||||
|
rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 489:24]
|
||||||
|
reg _T_9 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 491:16]
|
||||||
|
_T_9 <= io.mul_p.low @[el2_lib.scala 491:16]
|
||||||
|
low_x <= _T_9 @[el2_exu_mul_ctl.scala 36:9]
|
||||||
|
node _T_10 = bits(io.mul_p.valid, 0, 0) @[el2_exu_mul_ctl.scala 37:44]
|
||||||
|
inst rvclkhdr_1 of rvclkhdr_1 @[el2_lib.scala 505:23]
|
||||||
|
rvclkhdr_1.clock <= clock
|
||||||
|
rvclkhdr_1.reset <= reset
|
||||||
|
rvclkhdr_1.io.clk <= clock @[el2_lib.scala 507:18]
|
||||||
|
rvclkhdr_1.io.en <= _T_10 @[el2_lib.scala 508:17]
|
||||||
|
rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 509:24]
|
||||||
|
reg _T_11 : SInt, rvclkhdr_1.io.l1clk with : (reset => (reset, asSInt(UInt<1>("h00")))) @[el2_lib.scala 511:16]
|
||||||
|
_T_11 <= rs1_ext_in @[el2_lib.scala 511:16]
|
||||||
|
rs1_x <= _T_11 @[el2_exu_mul_ctl.scala 37:9]
|
||||||
|
node _T_12 = bits(io.mul_p.valid, 0, 0) @[el2_exu_mul_ctl.scala 38:45]
|
||||||
|
inst rvclkhdr_2 of rvclkhdr_2 @[el2_lib.scala 505:23]
|
||||||
|
rvclkhdr_2.clock <= clock
|
||||||
|
rvclkhdr_2.reset <= reset
|
||||||
|
rvclkhdr_2.io.clk <= clock @[el2_lib.scala 507:18]
|
||||||
|
rvclkhdr_2.io.en <= _T_12 @[el2_lib.scala 508:17]
|
||||||
|
rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 509:24]
|
||||||
|
reg _T_13 : SInt, rvclkhdr_2.io.l1clk with : (reset => (reset, asSInt(UInt<1>("h00")))) @[el2_lib.scala 511:16]
|
||||||
|
_T_13 <= rs2_ext_in @[el2_lib.scala 511:16]
|
||||||
|
rs2_x <= _T_13 @[el2_exu_mul_ctl.scala 38:9]
|
||||||
|
node _T_14 = mul(rs1_x, rs2_x) @[el2_exu_mul_ctl.scala 40:20]
|
||||||
|
prod_x <= _T_14 @[el2_exu_mul_ctl.scala 40:10]
|
||||||
|
node _T_15 = bits(low_x, 0, 0) @[el2_exu_mul_ctl.scala 41:36]
|
||||||
|
node _T_16 = eq(_T_15, UInt<1>("h00")) @[el2_exu_mul_ctl.scala 41:29]
|
||||||
|
node _T_17 = bits(prod_x, 63, 32) @[el2_exu_mul_ctl.scala 41:52]
|
||||||
|
node _T_18 = bits(low_x, 0, 0) @[el2_exu_mul_ctl.scala 41:67]
|
||||||
|
node _T_19 = bits(prod_x, 31, 0) @[el2_exu_mul_ctl.scala 41:83]
|
||||||
|
node _T_20 = mux(_T_16, _T_17, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||||
|
node _T_21 = mux(_T_18, _T_19, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||||
|
node _T_22 = or(_T_20, _T_21) @[Mux.scala 27:72]
|
||||||
|
wire _T_23 : UInt<32> @[Mux.scala 27:72]
|
||||||
|
_T_23 <= _T_22 @[Mux.scala 27:72]
|
||||||
|
io.result_x <= _T_23 @[el2_exu_mul_ctl.scala 41:15]
|
||||||
|
|
||||||
|
|
@ -0,0 +1,181 @@
|
||||||
|
module rvclkhdr(
|
||||||
|
output io_l1clk,
|
||||||
|
input io_clk,
|
||||||
|
input io_en,
|
||||||
|
input io_scan_mode
|
||||||
|
);
|
||||||
|
wire clkhdr_Q; // @[el2_lib.scala 465:26]
|
||||||
|
wire clkhdr_CK; // @[el2_lib.scala 465:26]
|
||||||
|
wire clkhdr_EN; // @[el2_lib.scala 465:26]
|
||||||
|
wire clkhdr_SE; // @[el2_lib.scala 465:26]
|
||||||
|
TEC_RV_ICG clkhdr ( // @[el2_lib.scala 465:26]
|
||||||
|
.Q(clkhdr_Q),
|
||||||
|
.CK(clkhdr_CK),
|
||||||
|
.EN(clkhdr_EN),
|
||||||
|
.SE(clkhdr_SE)
|
||||||
|
);
|
||||||
|
assign io_l1clk = clkhdr_Q; // @[el2_lib.scala 466:14]
|
||||||
|
assign clkhdr_CK = io_clk; // @[el2_lib.scala 467:18]
|
||||||
|
assign clkhdr_EN = io_en; // @[el2_lib.scala 468:18]
|
||||||
|
assign clkhdr_SE = io_scan_mode; // @[el2_lib.scala 469:18]
|
||||||
|
endmodule
|
||||||
|
module el2_exu_mul_ctl(
|
||||||
|
input clock,
|
||||||
|
input reset,
|
||||||
|
input io_scan_mode,
|
||||||
|
input io_mul_p_valid,
|
||||||
|
input io_mul_p_rs1_sign,
|
||||||
|
input io_mul_p_rs2_sign,
|
||||||
|
input io_mul_p_low,
|
||||||
|
input io_mul_p_bext,
|
||||||
|
input io_mul_p_bdep,
|
||||||
|
input io_mul_p_clmul,
|
||||||
|
input io_mul_p_clmulh,
|
||||||
|
input io_mul_p_clmulr,
|
||||||
|
input io_mul_p_grev,
|
||||||
|
input io_mul_p_shfl,
|
||||||
|
input io_mul_p_unshfl,
|
||||||
|
input io_mul_p_crc32_b,
|
||||||
|
input io_mul_p_crc32_h,
|
||||||
|
input io_mul_p_crc32_w,
|
||||||
|
input io_mul_p_crc32c_b,
|
||||||
|
input io_mul_p_crc32c_h,
|
||||||
|
input io_mul_p_crc32c_w,
|
||||||
|
input io_mul_p_bfp,
|
||||||
|
input [31:0] io_rs1_in,
|
||||||
|
input [31:0] io_rs2_in,
|
||||||
|
output [31:0] io_result_x
|
||||||
|
);
|
||||||
|
`ifdef RANDOMIZE_REG_INIT
|
||||||
|
reg [31:0] _RAND_0;
|
||||||
|
reg [63:0] _RAND_1;
|
||||||
|
reg [63:0] _RAND_2;
|
||||||
|
`endif // RANDOMIZE_REG_INIT
|
||||||
|
wire rvclkhdr_io_l1clk; // @[el2_lib.scala 485:23]
|
||||||
|
wire rvclkhdr_io_clk; // @[el2_lib.scala 485:23]
|
||||||
|
wire rvclkhdr_io_en; // @[el2_lib.scala 485:23]
|
||||||
|
wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 485:23]
|
||||||
|
wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 505:23]
|
||||||
|
wire rvclkhdr_1_io_clk; // @[el2_lib.scala 505:23]
|
||||||
|
wire rvclkhdr_1_io_en; // @[el2_lib.scala 505:23]
|
||||||
|
wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 505:23]
|
||||||
|
wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 505:23]
|
||||||
|
wire rvclkhdr_2_io_clk; // @[el2_lib.scala 505:23]
|
||||||
|
wire rvclkhdr_2_io_en; // @[el2_lib.scala 505:23]
|
||||||
|
wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 505:23]
|
||||||
|
wire _T_1 = io_mul_p_rs1_sign & io_rs1_in[31]; // @[el2_exu_mul_ctl.scala 26:39]
|
||||||
|
wire _T_5 = io_mul_p_rs2_sign & io_rs2_in[31]; // @[el2_exu_mul_ctl.scala 27:39]
|
||||||
|
reg low_x; // @[el2_lib.scala 491:16]
|
||||||
|
reg [32:0] rs1_x; // @[el2_lib.scala 511:16]
|
||||||
|
reg [32:0] rs2_x; // @[el2_lib.scala 511:16]
|
||||||
|
wire [65:0] prod_x = $signed(rs1_x) * $signed(rs2_x); // @[el2_exu_mul_ctl.scala 40:20]
|
||||||
|
wire _T_16 = ~low_x; // @[el2_exu_mul_ctl.scala 41:29]
|
||||||
|
wire [31:0] _T_20 = _T_16 ? prod_x[63:32] : 32'h0; // @[Mux.scala 27:72]
|
||||||
|
wire [31:0] _T_21 = low_x ? prod_x[31:0] : 32'h0; // @[Mux.scala 27:72]
|
||||||
|
rvclkhdr rvclkhdr ( // @[el2_lib.scala 485:23]
|
||||||
|
.io_l1clk(rvclkhdr_io_l1clk),
|
||||||
|
.io_clk(rvclkhdr_io_clk),
|
||||||
|
.io_en(rvclkhdr_io_en),
|
||||||
|
.io_scan_mode(rvclkhdr_io_scan_mode)
|
||||||
|
);
|
||||||
|
rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 505:23]
|
||||||
|
.io_l1clk(rvclkhdr_1_io_l1clk),
|
||||||
|
.io_clk(rvclkhdr_1_io_clk),
|
||||||
|
.io_en(rvclkhdr_1_io_en),
|
||||||
|
.io_scan_mode(rvclkhdr_1_io_scan_mode)
|
||||||
|
);
|
||||||
|
rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 505:23]
|
||||||
|
.io_l1clk(rvclkhdr_2_io_l1clk),
|
||||||
|
.io_clk(rvclkhdr_2_io_clk),
|
||||||
|
.io_en(rvclkhdr_2_io_en),
|
||||||
|
.io_scan_mode(rvclkhdr_2_io_scan_mode)
|
||||||
|
);
|
||||||
|
assign io_result_x = _T_20 | _T_21; // @[el2_exu_mul_ctl.scala 41:15]
|
||||||
|
assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 487:18]
|
||||||
|
assign rvclkhdr_io_en = io_mul_p_valid; // @[el2_lib.scala 488:17]
|
||||||
|
assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 489:24]
|
||||||
|
assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 507:18]
|
||||||
|
assign rvclkhdr_1_io_en = io_mul_p_valid; // @[el2_lib.scala 508:17]
|
||||||
|
assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 509:24]
|
||||||
|
assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 507:18]
|
||||||
|
assign rvclkhdr_2_io_en = io_mul_p_valid; // @[el2_lib.scala 508:17]
|
||||||
|
assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 509:24]
|
||||||
|
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
||||||
|
`define RANDOMIZE
|
||||||
|
`endif
|
||||||
|
`ifdef RANDOMIZE_INVALID_ASSIGN
|
||||||
|
`define RANDOMIZE
|
||||||
|
`endif
|
||||||
|
`ifdef RANDOMIZE_REG_INIT
|
||||||
|
`define RANDOMIZE
|
||||||
|
`endif
|
||||||
|
`ifdef RANDOMIZE_MEM_INIT
|
||||||
|
`define RANDOMIZE
|
||||||
|
`endif
|
||||||
|
`ifndef RANDOM
|
||||||
|
`define RANDOM $random
|
||||||
|
`endif
|
||||||
|
`ifdef RANDOMIZE_MEM_INIT
|
||||||
|
integer initvar;
|
||||||
|
`endif
|
||||||
|
`ifndef SYNTHESIS
|
||||||
|
`ifdef FIRRTL_BEFORE_INITIAL
|
||||||
|
`FIRRTL_BEFORE_INITIAL
|
||||||
|
`endif
|
||||||
|
initial begin
|
||||||
|
`ifdef RANDOMIZE
|
||||||
|
`ifdef INIT_RANDOM
|
||||||
|
`INIT_RANDOM
|
||||||
|
`endif
|
||||||
|
`ifndef VERILATOR
|
||||||
|
`ifdef RANDOMIZE_DELAY
|
||||||
|
#`RANDOMIZE_DELAY begin end
|
||||||
|
`else
|
||||||
|
#0.002 begin end
|
||||||
|
`endif
|
||||||
|
`endif
|
||||||
|
`ifdef RANDOMIZE_REG_INIT
|
||||||
|
_RAND_0 = {1{`RANDOM}};
|
||||||
|
low_x = _RAND_0[0:0];
|
||||||
|
_RAND_1 = {2{`RANDOM}};
|
||||||
|
rs1_x = _RAND_1[32:0];
|
||||||
|
_RAND_2 = {2{`RANDOM}};
|
||||||
|
rs2_x = _RAND_2[32:0];
|
||||||
|
`endif // RANDOMIZE_REG_INIT
|
||||||
|
if (reset) begin
|
||||||
|
low_x = 1'h0;
|
||||||
|
end
|
||||||
|
if (reset) begin
|
||||||
|
rs1_x = 33'sh0;
|
||||||
|
end
|
||||||
|
if (reset) begin
|
||||||
|
rs2_x = 33'sh0;
|
||||||
|
end
|
||||||
|
`endif // RANDOMIZE
|
||||||
|
end // initial
|
||||||
|
`ifdef FIRRTL_AFTER_INITIAL
|
||||||
|
`FIRRTL_AFTER_INITIAL
|
||||||
|
`endif
|
||||||
|
`endif // SYNTHESIS
|
||||||
|
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
|
||||||
|
if (reset) begin
|
||||||
|
low_x <= 1'h0;
|
||||||
|
end else begin
|
||||||
|
low_x <= io_mul_p_low;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin
|
||||||
|
if (reset) begin
|
||||||
|
rs1_x <= 33'sh0;
|
||||||
|
end else begin
|
||||||
|
rs1_x <= {_T_1,io_rs1_in};
|
||||||
|
end
|
||||||
|
end
|
||||||
|
always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
|
||||||
|
if (reset) begin
|
||||||
|
rs2_x <= 33'sh0;
|
||||||
|
end else begin
|
||||||
|
rs2_x <= {_T_5,io_rs2_in};
|
||||||
|
end
|
||||||
|
end
|
||||||
|
endmodule
|
||||||
|
|
@ -0,0 +1,134 @@
|
||||||
|
package exu
|
||||||
|
|
||||||
|
import chisel3._
|
||||||
|
import chisel3.util._
|
||||||
|
import include._
|
||||||
|
import lib._
|
||||||
|
|
||||||
|
class el2_exu_alu_ctl extends Module with el2_lib with RequireAsyncReset{
|
||||||
|
val io = IO(new Bundle{
|
||||||
|
////////// Inputs /////////
|
||||||
|
// val clk = Input(Clock()) // Top level clock
|
||||||
|
// val rst_l = Input(UInt(1.W)) // Reset
|
||||||
|
val scan_mode = Input(UInt(1.W)) // Scan control
|
||||||
|
val flush_upper_x = Input(UInt(1.W)) // Branch flush from previous cycle
|
||||||
|
val flush_lower_r = Input(UInt(1.W)) // Master flush of entire pipeline
|
||||||
|
val enable = Input(Bool()) // Clock enable
|
||||||
|
val valid_in = Input(UInt(1.W)) // Valid
|
||||||
|
val ap = Input( new el2_alu_pkt_t ) // predecodes
|
||||||
|
val csr_ren_in = Input(UInt(1.W)) // extra decode
|
||||||
|
val a_in = Input(SInt(32.W)) // A operand
|
||||||
|
val b_in = Input(UInt(32.W)) // B operand
|
||||||
|
val pc_in = Input(UInt(31.W)) // for pc=pc+2,4 calculations
|
||||||
|
val pp_in = Input(new el2_predict_pkt_t) // Predicted branch structure
|
||||||
|
val brimm_in = Input(UInt(12.W)) // Branch offset
|
||||||
|
////////// Outputs /////////
|
||||||
|
val result_ff = Output(UInt(32.W)) // final result
|
||||||
|
val flush_upper_out = Output(UInt(1.W)) // Branch flush
|
||||||
|
val flush_final_out = Output(UInt(1.W)) // Branch flush or flush entire pipeline
|
||||||
|
val flush_path_out = Output(UInt(31.W)) // Branch flush PC
|
||||||
|
val pc_ff = Output(UInt(31.W)) // flopped PC
|
||||||
|
val pred_correct_out = Output(UInt(1.W)) // NPC control
|
||||||
|
val predict_p_out = Output(new el2_predict_pkt_t) // Predicted branch structure
|
||||||
|
})
|
||||||
|
|
||||||
|
io.pc_ff := rvdffe(io.pc_in,io.enable,clock,io.scan_mode.asBool) // any PC is run through here - doesn't have to be alu
|
||||||
|
val result = WireInit(UInt(32.W),0.U)
|
||||||
|
io.result_ff := rvdffe(result,io.enable,clock,io.scan_mode.asBool)
|
||||||
|
|
||||||
|
val bm = Mux( io.ap.sub.asBool, ~io.b_in, io.b_in) //H:b modified
|
||||||
|
|
||||||
|
val aout = WireInit(UInt(33.W),0.U)
|
||||||
|
aout := Mux(io.ap.sub.asBool,(Cat(0.U(1.W),io.a_in) + Cat(0.U(1.W),~io.b_in) + Cat(0.U(32.W),io.ap.sub)), (Cat(0.U(1.W),io.a_in) + Cat(0.U(1.W), io.b_in) + Cat(0.U(32.W),io.ap.sub)))
|
||||||
|
val cout = aout(32)
|
||||||
|
|
||||||
|
val ov = (~io.a_in(31) & ~bm(31) & aout(31)) | ( io.a_in(31) & bm(31) & ~aout(31) ) //overflow check from last bits
|
||||||
|
|
||||||
|
val eq = (io.a_in === io.b_in.asSInt)
|
||||||
|
val ne = ~eq
|
||||||
|
val neg = aout(31)// check for the last signed bit (for neg)
|
||||||
|
val lt = (~io.ap.unsign & (neg ^ ov)) | ( io.ap.unsign & ~cout) //if alu packet sends unsigned and there is no cout(i.e no overflow and unsigned pkt)
|
||||||
|
val ge = ~lt // if not less then
|
||||||
|
|
||||||
|
|
||||||
|
val lout = Mux1H(Seq(
|
||||||
|
io.csr_ren_in.asBool -> io.b_in.asSInt, //read enable read rs2
|
||||||
|
io.ap.land.asBool -> (io.a_in & io.b_in.asSInt), //and rs1 and 2
|
||||||
|
io.ap.lor.asBool -> (io.a_in | io.b_in.asSInt),
|
||||||
|
io.ap.lxor.asBool -> (io.a_in ^ io.b_in.asSInt)))
|
||||||
|
|
||||||
|
val shift_amount = Mux1H(Seq (
|
||||||
|
io.ap.sll.asBool -> (32.U(6.W) - Cat(0.U(1.W),io.b_in(4,0))), // [5] unused
|
||||||
|
io.ap.srl.asBool -> Cat(0.U(1.W),io.b_in(4,0)) ,
|
||||||
|
io.ap.sra.asBool -> Cat(0.U(1.W),io.b_in(4,0)) ))
|
||||||
|
|
||||||
|
val shift_mask = WireInit(UInt(32.W),0.U)
|
||||||
|
shift_mask := ( "hffffffff".U(32.W) << (repl(5,io.ap.sll) & io.b_in(4,0)) )
|
||||||
|
|
||||||
|
val shift_extend = WireInit(UInt(63.W),0.U)
|
||||||
|
shift_extend := Cat((repl(31,io.ap.sra) & repl(31,io.a_in(31))) | (repl(31,io.ap.sll) & io.a_in(30,0)),io.a_in)
|
||||||
|
|
||||||
|
val shift_long = WireInit(UInt(63.W),0.U)
|
||||||
|
shift_long := ( shift_extend >> shift_amount(4,0) ); // 62-32 unused
|
||||||
|
|
||||||
|
val sout = ( shift_long(31,0) & shift_mask(31,0) ); //incase of sra shift_mask is 1
|
||||||
|
|
||||||
|
|
||||||
|
val sel_shift = io.ap.sll | io.ap.srl | io.ap.sra
|
||||||
|
val sel_adder = (io.ap.add | io.ap.sub) & ~io.ap.slt
|
||||||
|
val sel_pc = io.ap.jal | io.pp_in.pcall | io.pp_in.pja | io.pp_in.pret
|
||||||
|
val csr_write_data = Mux(io.ap.csr_imm.asBool, io.b_in.asSInt, io.a_in)
|
||||||
|
|
||||||
|
val slt_one = io.ap.slt & lt
|
||||||
|
|
||||||
|
// for a conditional br pcout[] will be the opposite of the branch prediction
|
||||||
|
// for jal or pcall, it will be the link address pc+2 or pc+4
|
||||||
|
val pcout = rvbradder(Cat(io.pc_in,0.U),Cat(io.brimm_in,0.U))
|
||||||
|
|
||||||
|
result := lout(31,0) | Cat(0.U(31.W),slt_one) | (Mux1H(Seq(
|
||||||
|
sel_shift.asBool -> sout(31,0),
|
||||||
|
sel_adder.asBool -> aout(31,0),
|
||||||
|
sel_pc.asBool -> pcout,
|
||||||
|
io.ap.csr_write.asBool -> csr_write_data(31,0))))
|
||||||
|
|
||||||
|
// *** branch handling ***
|
||||||
|
|
||||||
|
val any_jal = io.ap.jal | //jal
|
||||||
|
io.pp_in.pcall | //branch is a call inst
|
||||||
|
io.pp_in.pja | //branch is a jump always
|
||||||
|
io.pp_in.pret //return inst
|
||||||
|
|
||||||
|
val actual_taken = (io.ap.beq & eq) | (io.ap.bne & ne.asUInt) | (io.ap.blt & lt) | (io.ap.bge & ge) | any_jal
|
||||||
|
|
||||||
|
// pred_correct is for the npc logic
|
||||||
|
// pred_correct indicates not to use the flush_path
|
||||||
|
// for any_jal pred_correct==0
|
||||||
|
io.pred_correct_out := (io.valid_in & io.ap.predict_nt & !actual_taken & !any_jal) | (io.valid_in & io.ap.predict_t & actual_taken & !any_jal)
|
||||||
|
// for any_jal adder output is the flush path
|
||||||
|
io.flush_path_out := Mux(any_jal.asBool, aout(31,1), pcout(31,1))
|
||||||
|
|
||||||
|
// pcall and pret are included here
|
||||||
|
val cond_mispredict = (io.ap.predict_t & !actual_taken) | (io.ap.predict_nt & actual_taken.asUInt)
|
||||||
|
|
||||||
|
// target mispredicts on ret's
|
||||||
|
val target_mispredict = io.pp_in.pret & (io.pp_in.prett =/= aout(31,1)) //predicted return target != aout
|
||||||
|
|
||||||
|
io.flush_upper_out := (io.ap.jal | cond_mispredict | target_mispredict) & io.valid_in & !io.flush_upper_x & !io.flush_lower_r
|
||||||
|
//there was no entire pipe flush (& previous cycle flush ofc(why check?)) therfore signAL 1 to flush instruction before X stage
|
||||||
|
io.flush_final_out := ( (io.ap.jal | cond_mispredict | target_mispredict) & io.valid_in & !io.flush_upper_x ) | io.flush_lower_r
|
||||||
|
//there was entire pipe flush or (there is mispred or a jal) therfore signAL 1 to flush entire pipe
|
||||||
|
|
||||||
|
val newhist = WireInit(UInt(2.W),0.U)
|
||||||
|
newhist := Cat((io.pp_in.hist(1) & io.pp_in.hist(0)) | (~io.pp_in.hist(0) & actual_taken),//newhist[1]
|
||||||
|
(~io.pp_in.hist(1) & ~actual_taken) | (io.pp_in.hist(1) & actual_taken)) //newhist[0]
|
||||||
|
|
||||||
|
io.predict_p_out := io.pp_in
|
||||||
|
io.predict_p_out.misp := ~io.flush_upper_x & ~io.flush_lower_r & (cond_mispredict | target_mispredict);// if 1 tells that it was a misprediction becauseprevious cycle was not a flush and these was no master flush(lower pipe flush) and ifu predicted taken but actually its nt
|
||||||
|
io.predict_p_out.ataken := actual_taken; // send a control signal telling it branch taken or not
|
||||||
|
io.predict_p_out.hist := newhist
|
||||||
|
}
|
||||||
|
|
||||||
|
object alu extends App{
|
||||||
|
chisel3.Driver execute(args, () =>new el2_exu_alu_ctl())
|
||||||
|
}
|
||||||
|
|
||||||
|
|
@ -0,0 +1,225 @@
|
||||||
|
package exu
|
||||||
|
|
||||||
|
import chisel3._
|
||||||
|
import chisel3.experimental.chiselName
|
||||||
|
import chisel3.util._
|
||||||
|
import include._
|
||||||
|
import lib._
|
||||||
|
|
||||||
|
@chiselName
|
||||||
|
class el2_exu_div_ctl extends Module with RequireAsyncReset with el2_lib {
|
||||||
|
val io = IO(new Bundle{
|
||||||
|
val scan_mode = Input(Bool())
|
||||||
|
val dp = Input(new el2_div_pkt_t )
|
||||||
|
val dividend = Input(UInt(32.W))
|
||||||
|
val divisor = Input(UInt(32.W))
|
||||||
|
val cancel = Input(UInt(1.W))
|
||||||
|
|
||||||
|
val out = Output(UInt(32.W))
|
||||||
|
val finish_dly = Output(UInt(1.W))
|
||||||
|
})
|
||||||
|
// val exu_div_clk = Wire(Clock())
|
||||||
|
val run_state = WireInit(0.U(1.W))
|
||||||
|
val count = WireInit(0.U(6.W))
|
||||||
|
val m_ff = WireInit(0.U(33.W))
|
||||||
|
val q_in = WireInit(0.U(33.W))
|
||||||
|
val q_ff = WireInit(0.U(33.W))
|
||||||
|
val a_in = WireInit(0.U(33.W))
|
||||||
|
val a_ff = WireInit(0.U(33.W))
|
||||||
|
val m_eff = WireInit(0.U(33.W))
|
||||||
|
val dividend_neg_ff = WireInit(0.U(1.W))
|
||||||
|
val divisor_neg_ff = WireInit(0.U(1.W))
|
||||||
|
val dividend_comp = WireInit(0.U(32.W))
|
||||||
|
val q_ff_comp = WireInit(0.U(32.W))
|
||||||
|
val a_ff_comp = WireInit(0.U(32.W))
|
||||||
|
val sign_ff = WireInit(0.U(1.W))
|
||||||
|
val rem_ff = WireInit(0.U(1.W))
|
||||||
|
val add = WireInit(0.U(1.W))
|
||||||
|
val a_eff = WireInit(0.U(33.W))
|
||||||
|
val a_eff_shift = WireInit(0.U(56.W))
|
||||||
|
val rem_correct = WireInit(0.U(1.W))
|
||||||
|
val valid_ff_x = WireInit(0.U(1.W))
|
||||||
|
val finish_ff = WireInit(0.U(1.W))
|
||||||
|
val smallnum_case_ff = WireInit(0.U(1.W))
|
||||||
|
val smallnum_ff = WireInit(0.U(4.W))
|
||||||
|
val smallnum_case = WireInit(0.U(1.W))
|
||||||
|
val count_in = WireInit(0.U(6.W))
|
||||||
|
val dividend_eff = WireInit(0.U(32.W))
|
||||||
|
val a_shift = WireInit(0.U(33.W))
|
||||||
|
|
||||||
|
io.out := 0.U
|
||||||
|
io.finish_dly := 0.U
|
||||||
|
|
||||||
|
|
||||||
|
val valid_x = valid_ff_x & !io.cancel
|
||||||
|
|
||||||
|
// START - short circuit logic for small numbers {{
|
||||||
|
// small number divides - any 4b / 4b is done in 1 cycle (divisor != 0)
|
||||||
|
// smallnum case does not cover divide by 0
|
||||||
|
|
||||||
|
smallnum_case := ((q_ff(31,4) === 0.U) & (m_ff(31,4) === 0.U) & (m_ff(31,0) =/= 0.U) & !rem_ff & valid_x) |
|
||||||
|
((q_ff(31,0) === 0.U) & (m_ff(31,0) =/= 0.U) & !rem_ff & valid_x)
|
||||||
|
|
||||||
|
def pat(x : List[Int], y : List[Int]) = {
|
||||||
|
val pat1 = (0 until x.size).map(i=> if(x(i)>=0) q_ff(x(i)) else !q_ff(x(i).abs)).reduce(_&_)
|
||||||
|
val pat2 = (0 until y.size).map(i=> if(y(i)>=0) m_ff(y(i)) else !m_ff(y(i).abs)).reduce(_&_)
|
||||||
|
pat1 & pat2
|
||||||
|
}
|
||||||
|
|
||||||
|
val smallnum = Cat(
|
||||||
|
pat(List(3),List(-3, -2, -1)),
|
||||||
|
|
||||||
|
pat(List(3),List(-3, -2))& !m_ff(0) | pat(List(2),List(-3, -2, -1)) | pat(List(3, 2),List(-3, -2)),
|
||||||
|
|
||||||
|
pat(List(2),List(-3, -2))& !m_ff(0) | pat(List(1),List(-3, -2, -1)) | pat(List(3),List(-3, -1))& !m_ff(0) |
|
||||||
|
pat(List(3, -2),List(-3, -2, 1, 0)) | pat(List(-3, 2, 1),List(-3, -2)) | pat(List(3, 2),List(-3))& !m_ff(0) |
|
||||||
|
pat(List(3, 2),List(-3, 2, -1)) | pat(List(3, 1),List(-3,-1)) | pat(List(3, 2, 1),List(-3, 2)),
|
||||||
|
|
||||||
|
pat(List(2, 1, 0),List(-3, -1)) | pat(List(3, -2, 0),List(-3, 1, 0)) | pat(List(2),List(-3, -1))& !m_ff(0) |
|
||||||
|
pat(List(1),List(-3, -2))& !m_ff(0) | pat(List(0),List(-3, -2, -1)) | pat(List(-3, 2, -1),List(-3, -2, 1, 0)) |
|
||||||
|
pat(List(-3, 2, 1),List(-3))& !m_ff(0) | pat(List(3),List(-2, -1)) & !m_ff(0) | pat(List(3, -2),List(-3, 2, 1)) |
|
||||||
|
pat(List(-3, 2, 1),List(-3, 2, -1)) | pat(List(-3, 2, 0),List(-3, -1)) | pat(List(3, -2, -1),List(-3, 2, 0)) |
|
||||||
|
pat(List(-2, 1, 0),List(-3, -2)) | pat(List(3, 2),List(-1)) & !m_ff(0) | pat(List(-3, 2, 1, 0),List(-3, 2)) |
|
||||||
|
pat(List(3, 2),List(3, -2)) | pat(List(3, 1),List(3,-2,-1)) | pat(List(3, 0),List(-2, -1)) |
|
||||||
|
pat(List(3, -1),List(-3, 2, 1, 0)) | pat(List(3, 2, 1),List(3)) & !m_ff(0) | pat(List(3, 2, 1),List(3, -1)) |
|
||||||
|
pat(List(3, 2, 0),List(3, -1)) | pat(List(3, -2, 1),List(-3, 1)) | pat(List(3, 1, 0),List(-2)) |
|
||||||
|
pat(List(3, 2, 1, 0),List(3)) |pat(List(3, 1),List(-2)) & !m_ff(0)
|
||||||
|
)
|
||||||
|
//io.test := smallnum
|
||||||
|
// END - short circuit logic for small numbers }}
|
||||||
|
|
||||||
|
// *** Start Short Q *** {{
|
||||||
|
val shortq_enable_ff = WireInit(0.U(1.W))
|
||||||
|
val short_dividend = WireInit(0.U(33.W))
|
||||||
|
val shortq_shift_xx = WireInit(0.U(4.W))
|
||||||
|
|
||||||
|
short_dividend := Cat (sign_ff & q_ff(31),q_ff(31,0))
|
||||||
|
|
||||||
|
|
||||||
|
val a_cls = Cat(
|
||||||
|
Mux1H(Seq (
|
||||||
|
!short_dividend(32).asBool -> (short_dividend(31,24) =/= Fill(8,0.U)),
|
||||||
|
short_dividend(32).asBool -> (short_dividend(31,23) =/= Fill(9,1.U))
|
||||||
|
)),
|
||||||
|
Mux1H(Seq (
|
||||||
|
!short_dividend(32).asBool -> (short_dividend(23,16) =/= Fill(8,0.U)),
|
||||||
|
short_dividend(32).asBool -> (short_dividend(22,15) =/= Fill(8,1.U))
|
||||||
|
)),
|
||||||
|
Mux1H(Seq (
|
||||||
|
!short_dividend(32).asBool -> (short_dividend(15,8) =/= Fill(8,0.U)),
|
||||||
|
short_dividend(32).asBool -> (short_dividend(14,7) =/= Fill(8,1.U))
|
||||||
|
))
|
||||||
|
)
|
||||||
|
val b_cls = Cat(
|
||||||
|
Mux1H(Seq (
|
||||||
|
!m_ff(32).asBool -> (m_ff(31,24) =/= Fill(8,0.U)),
|
||||||
|
m_ff(32).asBool -> (m_ff(31,24) =/= Fill(8,1.U))
|
||||||
|
)),
|
||||||
|
Mux1H(Seq (
|
||||||
|
!m_ff(32).asBool -> (m_ff(23,16) =/= Fill(8,0.U)),
|
||||||
|
m_ff(32).asBool -> (m_ff(23,16) =/= Fill(8,1.U))
|
||||||
|
)),
|
||||||
|
Mux1H(Seq (
|
||||||
|
!m_ff(32).asBool -> (m_ff(15,8) =/= Fill(8,0.U)),
|
||||||
|
m_ff(32).asBool -> (m_ff(15,8) =/= Fill(8,1.U))
|
||||||
|
))
|
||||||
|
)
|
||||||
|
val shortq_raw = Cat(
|
||||||
|
( (a_cls(2,1) === "b01".U ) & (b_cls(2) === "b1".U ) ) | // Shift by 32
|
||||||
|
( (a_cls(2,0) === "b001".U ) & (b_cls(2) === "b1".U ) ) |
|
||||||
|
( (a_cls(2,0) === "b000".U ) & (b_cls(2) === "b1".U ) ) |
|
||||||
|
( (a_cls(2,0) === "b001".U ) & (b_cls(2,1) === "b01".U ) ) |
|
||||||
|
( (a_cls(2,0) === "b000".U ) & (b_cls(2,1) === "b01".U ) ) |
|
||||||
|
( (a_cls(2,0) === "b000".U ) & (b_cls(2,0) === "b001".U ) ) ,
|
||||||
|
|
||||||
|
( (a_cls(2) === "b1".U ) & (b_cls(2) === "b1".U ) ) | // Shift by 24
|
||||||
|
( (a_cls(2,1) === "b01".U ) & (b_cls(2,1) === "b01".U ) ) |
|
||||||
|
( (a_cls(2,0) === "b001".U ) & (b_cls(2,0) === "b001".U ) ) |
|
||||||
|
( (a_cls(2,0) === "b000".U ) & (b_cls(2,0) === "b000".U ) ) ,
|
||||||
|
|
||||||
|
( (a_cls(2) === "b1".U ) & (b_cls(2,1) === "b01".U ) ) | // Shift by 16
|
||||||
|
( (a_cls(2,1) === "b01".U ) & (b_cls(2,0) === "b001".U ) ) |
|
||||||
|
( (a_cls(2,0) === "b001".U ) & (b_cls(2,0) === "b000".U ) ) ,
|
||||||
|
|
||||||
|
( (a_cls(2) === "b1".U ) & (b_cls(2,0) === "b001".U ) ) | // Shift by 8
|
||||||
|
( (a_cls(2,1) === "b01".U ) & (b_cls(2,0) === "b000".U ) )
|
||||||
|
|
||||||
|
)
|
||||||
|
val shortq_enable = valid_ff_x & (m_ff(31,0) =/= 0.U(32.W)) & (shortq_raw =/= 0.U(4.W))
|
||||||
|
val shortq_shift = Fill(4,shortq_enable) & shortq_raw
|
||||||
|
|
||||||
|
val shortq_shift_ff = Mux1H(Seq (
|
||||||
|
shortq_shift_xx(3).asBool -> "b11111".U,
|
||||||
|
shortq_shift_xx(2).asBool -> "b11000".U,
|
||||||
|
shortq_shift_xx(1).asBool -> "b10000".U,
|
||||||
|
shortq_shift_xx(0).asBool -> "b01000".U
|
||||||
|
))
|
||||||
|
// *** End Short *** }}
|
||||||
|
|
||||||
|
val finish = smallnum_case | Mux(!rem_ff ,count === 32.U(6.W) ,count === 33.U(6.W))
|
||||||
|
val div_clken = io.dp.valid | run_state | finish | finish_ff
|
||||||
|
val run_in = (io.dp.valid | run_state) & !finish & !io.cancel
|
||||||
|
count_in := Fill(6,(run_state & !finish & !io.cancel & !shortq_enable)) & (count + Cat(0.U,shortq_shift_ff) + (1.U)(6.W))
|
||||||
|
//io.test := count_in
|
||||||
|
|
||||||
|
io.finish_dly := finish_ff & !io.cancel
|
||||||
|
val sign_eff = !io.dp.unsign & (io.divisor =/= 0.U(32.W))
|
||||||
|
|
||||||
|
|
||||||
|
q_in := Mux1H(Seq(
|
||||||
|
(!run_state).asBool -> Cat(0.U(1.W),io.dividend) ,
|
||||||
|
(run_state & (valid_ff_x | shortq_enable_ff)).asBool -> (Cat(dividend_eff(31,0),!a_in(32)) << shortq_shift_ff) ,
|
||||||
|
(run_state & !(valid_ff_x | shortq_enable_ff)).asBool -> Cat(q_ff(31,0),!a_in(32))
|
||||||
|
))
|
||||||
|
val qff_enable = io.dp.valid | (run_state & !shortq_enable)
|
||||||
|
dividend_eff := Mux((sign_ff & dividend_neg_ff).asBool, rvtwoscomp(q_ff(31,0)),q_ff(31,0))
|
||||||
|
|
||||||
|
|
||||||
|
m_eff := Mux(add.asBool , m_ff, ~m_ff )
|
||||||
|
a_eff_shift := Cat(0.U(24.W), dividend_eff) << shortq_shift_ff
|
||||||
|
a_eff := Mux1H(Seq(
|
||||||
|
rem_correct.asBool -> a_ff ,
|
||||||
|
(!rem_correct & !shortq_enable_ff).asBool -> Cat(a_ff(31,0), q_ff(32)) ,
|
||||||
|
(!rem_correct & shortq_enable_ff).asBool -> Cat(0.U(9.W),a_eff_shift(55,32))
|
||||||
|
))
|
||||||
|
val aff_enable = io.dp.valid | (run_state & !shortq_enable & (count =/= 33.U(6.W))) | rem_correct
|
||||||
|
a_shift := Fill(33,run_state) & a_eff
|
||||||
|
a_in := Fill(33,run_state) & (a_shift + m_eff + Cat(0.U(32.W),!add))
|
||||||
|
val m_already_comp = divisor_neg_ff & sign_ff
|
||||||
|
// if m already complemented, then invert operation add->sub, sub->add
|
||||||
|
add := (a_ff(32) | rem_correct) ^ m_already_comp
|
||||||
|
rem_correct := (count === 33.U(6.W)) & rem_ff & a_ff(32)
|
||||||
|
val q_ff_eff = Mux((sign_ff & (dividend_neg_ff ^ divisor_neg_ff)).asBool,rvtwoscomp(q_ff(31,0)), q_ff(31,0))
|
||||||
|
val a_ff_eff = Mux((sign_ff & dividend_neg_ff ).asBool, rvtwoscomp(a_ff(31,0)), a_ff(31,0))
|
||||||
|
|
||||||
|
io.out := Mux1H(Seq(
|
||||||
|
smallnum_case_ff.asBool -> Cat(0.U(28.W), smallnum_ff),
|
||||||
|
rem_ff.asBool -> a_ff_eff ,
|
||||||
|
(!smallnum_case_ff & !rem_ff).asBool -> q_ff_eff
|
||||||
|
))
|
||||||
|
|
||||||
|
val exu_div_cgc = rvclkhdr(clock,div_clken.asBool,io.scan_mode)
|
||||||
|
|
||||||
|
withClock(exu_div_cgc) {
|
||||||
|
valid_ff_x := RegNext(io.dp.valid & !io.cancel, 0.U)
|
||||||
|
finish_ff := RegNext(finish & !io.cancel, 0.U)
|
||||||
|
run_state := RegNext(run_in, 0.U)
|
||||||
|
count := RegNext(count_in, 0.U)
|
||||||
|
dividend_neg_ff := RegEnable(io.dividend(31), 0.U, io.dp.valid.asBool)
|
||||||
|
divisor_neg_ff := RegEnable(io.divisor(31), 0.U, io.dp.valid.asBool)
|
||||||
|
sign_ff := RegEnable(sign_eff, 0.U, io.dp.valid.asBool)
|
||||||
|
rem_ff := RegEnable(io.dp.rem, 0.U, io.dp.valid.asBool)
|
||||||
|
smallnum_case_ff := RegNext(smallnum_case, 0.U)
|
||||||
|
smallnum_ff := RegNext(smallnum, 0.U)
|
||||||
|
shortq_enable_ff := RegNext(shortq_enable, 0.U)
|
||||||
|
shortq_shift_xx := RegNext(shortq_shift, 0.U)
|
||||||
|
}
|
||||||
|
q_ff := rvdffe(q_in, qff_enable.asBool,clock,io.scan_mode)
|
||||||
|
a_ff := rvdffe(a_in, aff_enable.asBool,clock,io.scan_mode)
|
||||||
|
m_ff := rvdffe(Cat(!io.dp.unsign & io.divisor(31), io.divisor), io.dp.valid.asBool,clock,io.scan_mode)
|
||||||
|
|
||||||
|
}
|
||||||
|
object div_main extends App{
|
||||||
|
println("Generate Verilog")
|
||||||
|
println((new chisel3.stage.ChiselStage).emitVerilog(new el2_exu_div_ctl()))
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,46 @@
|
||||||
|
package exu
|
||||||
|
|
||||||
|
import chisel3._
|
||||||
|
import chisel3.util._
|
||||||
|
import include._
|
||||||
|
import lib._
|
||||||
|
|
||||||
|
|
||||||
|
class el2_exu_mul_ctl extends Module with RequireAsyncReset with el2_lib {
|
||||||
|
val io = IO(new Bundle{
|
||||||
|
val scan_mode = Input(Bool())
|
||||||
|
val mul_p = Input(new el2_mul_pkt_t )
|
||||||
|
val rs1_in = Input(UInt(32.W))
|
||||||
|
val rs2_in = Input(UInt(32.W))
|
||||||
|
val result_x = Output(UInt(32.W))
|
||||||
|
})
|
||||||
|
|
||||||
|
val rs1_ext_in = WireInit(SInt(33.W), 0.S)
|
||||||
|
val rs2_ext_in = WireInit(SInt(33.W), 0.S)
|
||||||
|
val rs1_x = WireInit(SInt(33.W), 0.S)
|
||||||
|
val rs2_x = WireInit(SInt(33.W), 0.S)
|
||||||
|
val prod_x = WireInit(SInt(66.W), 0.S)
|
||||||
|
val low_x = WireInit(0.U(1.W))
|
||||||
|
|
||||||
|
val mul_x_enable = io.mul_p.valid
|
||||||
|
rs1_ext_in := Cat(io.mul_p.rs1_sign & io.rs1_in(31),io.rs1_in).asSInt
|
||||||
|
rs2_ext_in := Cat(io.mul_p.rs2_sign & io.rs2_in(31),io.rs2_in).asSInt
|
||||||
|
|
||||||
|
// --------------------------- Multiply ----------------------------------
|
||||||
|
// val gated_clock = rvclkhdr(clock,mul_x_enable.asBool(),io.scan_mode)
|
||||||
|
// withClock(gated_clock) {
|
||||||
|
// low_x := RegNext(io.mul_p.low, 0.U)
|
||||||
|
//rs1_x := RegNext(rs1_ext_in, 0.S)
|
||||||
|
// rs2_x := RegNext(rs2_ext_in, 0.S)
|
||||||
|
// }
|
||||||
|
low_x := rvdffe (io.mul_p.low, mul_x_enable.asBool,clock,io.scan_mode)
|
||||||
|
rs1_x := rvdffe(rs1_ext_in, mul_x_enable.asBool,clock,io.scan_mode)
|
||||||
|
rs2_x := rvdffe (rs2_ext_in, mul_x_enable.asBool,clock,io.scan_mode)
|
||||||
|
|
||||||
|
prod_x := rs1_x * rs2_x
|
||||||
|
io.result_x := Mux1H (Seq(!low_x.asBool -> prod_x(63,32), low_x.asBool -> prod_x(31,0)))
|
||||||
|
}
|
||||||
|
object mul_main extends App{
|
||||||
|
println("Generate Verilog")
|
||||||
|
println((new chisel3.stage.ChiselStage).emitVerilog(new el2_exu_mul_ctl()))
|
||||||
|
}
|
||||||
|
|
@ -130,6 +130,7 @@ class el2_ifu_ifc_ctl extends Module with el2_lib with RequireAsyncReset {
|
||||||
rvrangecheck(ICCM_SADR, ICCM_SIZE, Cat(io.ifc_fetch_addr_bf,0.U))
|
rvrangecheck(ICCM_SADR, ICCM_SIZE, Cat(io.ifc_fetch_addr_bf,0.U))
|
||||||
else (0.U, 0.U)
|
else (0.U, 0.U)
|
||||||
io.ifc_iccm_access_bf := iccm_acc_in_range_bf
|
io.ifc_iccm_access_bf := iccm_acc_in_range_bf
|
||||||
|
|
||||||
io.ifc_dma_access_ok := ( (!io.ifc_iccm_access_bf |
|
io.ifc_dma_access_ok := ( (!io.ifc_iccm_access_bf |
|
||||||
(fb_full_f & !(io.ifu_fb_consume2 | io.ifu_fb_consume1)) |
|
(fb_full_f & !(io.ifu_fb_consume2 | io.ifu_fb_consume1)) |
|
||||||
(wfm & !io.ifc_fetch_req_bf) | idle ) & !io.exu_flush_final) | dma_iccm_stall_any_f
|
(wfm & !io.ifc_fetch_req_bf) | idle ) & !io.exu_flush_final) | dma_iccm_stall_any_f
|
||||||
|
|
@ -140,7 +141,7 @@ class el2_ifu_ifc_ctl extends Module with el2_lib with RequireAsyncReset {
|
||||||
io.ifc_fetch_req_f := withClock(io.active_clk){RegNext(io.ifc_fetch_req_bf, init=0.U)}
|
io.ifc_fetch_req_f := withClock(io.active_clk){RegNext(io.ifc_fetch_req_bf, init=0.U)}
|
||||||
|
|
||||||
io.ifc_fetch_addr_f := rvdffe(io.ifc_fetch_addr_bf, io.exu_flush_final|io.ifc_fetch_req_f, clock, io.scan_mode)
|
io.ifc_fetch_addr_f := rvdffe(io.ifc_fetch_addr_bf, io.exu_flush_final|io.ifc_fetch_req_f, clock, io.scan_mode)
|
||||||
//rvdffe(io.ifc_fetch_addr_bf,(io.exu_flush_final|io.ifc_fetch_req_f).asBool,clock,io.scan_mode)
|
|
||||||
}
|
}
|
||||||
|
|
||||||
object ifu_ifc extends App {
|
object ifu_ifc extends App {
|
||||||
|
|
|
||||||
|
|
@ -501,5 +501,25 @@ trait el2_lib extends param{
|
||||||
RegNext(din,0.U.asTypeOf(din.cloneType))
|
RegNext(din,0.U.asTypeOf(din.cloneType))
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
def apply(din: SInt, en: Bool, clk: Clock, scan_mode: Bool): Bits with Num[_ >: SInt with UInt <: Bits with Num[_ >: SInt with UInt]] = {
|
||||||
|
val obj = Module(new rvclkhdr())
|
||||||
|
val l1clk = obj.io.l1clk
|
||||||
|
obj.io.clk := clk
|
||||||
|
obj.io.en := en
|
||||||
|
obj.io.scan_mode := scan_mode
|
||||||
|
withClock(l1clk) {
|
||||||
|
RegNext(din, 0.S)
|
||||||
}
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/////////////////////////////////////////////////////////
|
||||||
|
def rvtwoscomp(din:UInt) = { //Done for verification and testing
|
||||||
|
val temp = Wire(Vec(din.getWidth-1,UInt(1.W)))
|
||||||
|
for(i <- 1 to din.getWidth-1){
|
||||||
|
temp(i-1) := Mux(din(i-1,0).orR ,~din(i),din(i))
|
||||||
|
}
|
||||||
|
Cat(temp.asUInt,din(0))
|
||||||
|
}
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
|
||||||
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Reference in New Issue