Makefile updated
This commit is contained in:
waleed-lm
parent
ebdba5c6e7
commit
a4d822502c
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// SPDX-License-Identifier: Apache-2.0
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// Copyright 2018 Western Digital Corporation or it's affiliates.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//------------------------------------------------------------------------------------
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//
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// Copyright Western Digital, 2018
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// Owner : Anusha Narayanamoorthy
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// Description:
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// Wrapper module for JTAG_TAP and DMI synchronizer
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//
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//-------------------------------------------------------------------------------------
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module dmi_wrapper(
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// JTAG signals
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input trst_n, // JTAG reset
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input tck, // JTAG clock
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input tms, // Test mode select
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input tdi, // Test Data Input
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output tdo, // Test Data Output
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output tdoEnable, // Test Data Output enable
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// Processor Signals
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input core_rst_n, // Core reset
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input core_clk, // Core clock
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input [31:1] jtag_id, // JTAG ID
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input [31:0] rd_data, // 32 bit Read data from Processor
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output [31:0] reg_wr_data, // 32 bit Write data to Processor
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output [6:0] reg_wr_addr, // 7 bit reg address to Processor
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output reg_en, // 1 bit Read enable to Processor
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output reg_wr_en, // 1 bit Write enable to Processor
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output dmi_hard_reset
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);
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//Wire Declaration
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wire rd_en;
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wire wr_en;
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wire dmireset;
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//jtag_tap instantiation
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rvjtag_tap i_jtag_tap(
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.trst(trst_n), // dedicated JTAG TRST (active low) pad signal or asynchronous active low power on reset
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.tck(tck), // dedicated JTAG TCK pad signal
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.tms(tms), // dedicated JTAG TMS pad signal
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.tdi(tdi), // dedicated JTAG TDI pad signal
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.tdo(tdo), // dedicated JTAG TDO pad signal
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.tdoEnable(tdoEnable), // enable for TDO pad
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.wr_data(reg_wr_data), // 32 bit Write data
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.wr_addr(reg_wr_addr), // 7 bit Write address
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.rd_en(rd_en), // 1 bit read enable
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.wr_en(wr_en), // 1 bit Write enable
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.rd_data(rd_data), // 32 bit Read data
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.rd_status(2'b0),
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.idle(3'h0), // no need to wait to sample data
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.dmi_stat(2'b0), // no need to wait or error possible
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.version(4'h1), // debug spec 0.13 compliant
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.jtag_id(jtag_id),
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.dmi_hard_reset(dmi_hard_reset),
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.dmi_reset(dmireset)
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);
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// dmi_jtag_to_core_sync instantiation
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dmi_jtag_to_core_sync i_dmi_jtag_to_core_sync(
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.wr_en(wr_en), // 1 bit Write enable
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.rd_en(rd_en), // 1 bit Read enable
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.rst_n(core_rst_n),
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.clk(core_clk),
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.reg_en(reg_en), // 1 bit Write interface bit
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.reg_wr_en(reg_wr_en) // 1 bit Write enable
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);
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endmodule
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@ -0,0 +1 @@
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/home/waleedbinehsan/Downloads/Quasar/design/gated_latch.sv
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module gated_latch
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(
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input logic SE, EN, CK,
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output Q
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);
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logic en_ff;
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logic enable;
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assign enable = EN | SE;
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always @(CK, enable) begin
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if(!CK)
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en_ff = enable;
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end
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assign Q = CK & en_ff;
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endmodule
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module mem #(
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parameter ICACHE_BEAT_BITS,
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parameter ICCM_BITS,
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parameter ICACHE_NUM_WAYS,
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parameter DCCM_BYTE_WIDTH,
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parameter ICCM_BANK_INDEX_LO,
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parameter ICACHE_BANK_BITS,
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parameter DCCM_BITS,
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parameter ICACHE_BEAT_ADDR_HI,
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parameter ICCM_INDEX_BITS,
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parameter ICCM_BANK_HI,
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parameter ICACHE_BANKS_WAY,
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parameter ICACHE_INDEX_HI,
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parameter DCCM_NUM_BANKS,
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parameter ICACHE_BANK_HI,
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parameter ICACHE_BANK_LO,
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parameter DCCM_ENABLE= 'b1,
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parameter ICACHE_TAG_LO,
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parameter ICACHE_DATA_INDEX_LO,
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parameter ICCM_NUM_BANKS,
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parameter ICACHE_ECC,
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parameter ICACHE_ENABLE= 'b1,
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parameter DCCM_BANK_BITS,
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parameter ICCM_ENABLE= 'b1,
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parameter ICCM_BANK_BITS,
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parameter ICACHE_TAG_DEPTH,
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parameter ICACHE_WAYPACK,
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parameter DCCM_SIZE,
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parameter DCCM_FDATA_WIDTH,
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parameter ICACHE_TAG_INDEX_LO,
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parameter ICACHE_DATA_DEPTH)
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(
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input logic clk,
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input logic rst_l,
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input logic dccm_clk_override,
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input logic icm_clk_override,
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input logic dec_tlu_core_ecc_disable,
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//DCCM ports
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input logic dccm_wren,
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input logic dccm_rden,
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input logic [DCCM_BITS-1:0] dccm_wr_addr_lo,
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input logic [DCCM_BITS-1:0] dccm_wr_addr_hi,
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input logic [DCCM_BITS-1:0] dccm_rd_addr_lo,
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input logic [DCCM_BITS-1:0] dccm_rd_addr_hi,
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input logic [DCCM_FDATA_WIDTH-1:0] dccm_wr_data_lo,
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input logic [DCCM_FDATA_WIDTH-1:0] dccm_wr_data_hi,
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output logic [DCCM_FDATA_WIDTH-1:0] dccm_rd_data_lo,
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output logic [DCCM_FDATA_WIDTH-1:0] dccm_rd_data_hi,
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//`ifdef DCCM_ENABLE
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//`endif
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//ICCM ports
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input logic [ICCM_BITS-1:1] iccm_rw_addr,
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input logic iccm_buf_correct_ecc, // ICCM is doing a single bit error correct cycle
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input logic iccm_correction_state, // ICCM is doing a single bit error correct cycle
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input logic iccm_wren,
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input logic iccm_rden,
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input logic [2:0] iccm_wr_size,
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input logic [77:0] iccm_wr_data,
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output logic [63:0] iccm_rd_data,
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output logic [77:0] iccm_rd_data_ecc,
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// Icache and Itag Ports
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input logic [31:1] ic_rw_addr,
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input logic [ICACHE_NUM_WAYS-1:0] ic_tag_valid,
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input logic [ICACHE_NUM_WAYS-1:0] ic_wr_en,
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input logic ic_rd_en,
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input logic [63:0] ic_premux_data, // Premux data to be muxed with each way of the Icache.
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input logic ic_sel_premux_data, // Premux data sel
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input logic [70:0] ic_wr_data_0, // Data to fill to the Icache. With ECC
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input logic [70:0] ic_wr_data_1,
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input logic [70:0] ic_debug_wr_data, // Debug wr cache.
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output logic [70:0] ic_debug_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
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input logic [ICACHE_INDEX_HI:3] ic_debug_addr, // Read/Write addresss to the Icache.
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input logic ic_debug_rd_en, // Icache debug rd
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input logic ic_debug_wr_en, // Icache debug wr
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input logic ic_debug_tag_array, // Debug tag array
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input logic [ICACHE_NUM_WAYS-1:0] ic_debug_way, // Debug way. Rd or Wr.
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output logic [63:0] ic_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
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output logic [25:0] ic_tag_debug_rd_data,// Debug icache tag.
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output logic [ICACHE_BANKS_WAY-1:0] ic_eccerr, // ecc error per bank
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output logic [ICACHE_BANKS_WAY-1:0] ic_parerr, // parity error per bank
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output logic [ICACHE_NUM_WAYS-1:0] ic_rd_hit,
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output logic ic_tag_perr, // Icache Tag parity error
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input logic scan_mode
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);
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logic [ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data;
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assign ic_wr_data [0] = ic_wr_data_0;
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assign ic_wr_data [1] = ic_wr_data_1;
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// DCCM Instantiation
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if (DCCM_ENABLE == 1) begin: Gen_dccm_enable
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lsu_dccm_mem #(
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.DCCM_BYTE_WIDTH(DCCM_BYTE_WIDTH),
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.DCCM_BITS(DCCM_BITS),
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.DCCM_NUM_BANKS(DCCM_NUM_BANKS),
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.DCCM_BANK_BITS(DCCM_BANK_BITS),
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.DCCM_SIZE(DCCM_SIZE),
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.DCCM_FDATA_WIDTH(DCCM_FDATA_WIDTH)) dccm (
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.clk_override(dccm_clk_override),
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.*
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);
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end else begin: Gen_dccm_disable
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assign dccm_rd_data_lo = '0;
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assign dccm_rd_data_hi = '0;
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end
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if ( ICACHE_ENABLE ) begin: icache
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ifu_ic_mem #(
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.ICACHE_BEAT_BITS(ICACHE_BEAT_BITS),
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.ICACHE_NUM_WAYS(ICACHE_NUM_WAYS),
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.ICACHE_BANK_BITS(ICACHE_BANK_BITS),
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.ICACHE_BEAT_ADDR_HI(ICACHE_BEAT_ADDR_HI),
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.ICACHE_BANKS_WAY(ICACHE_BANKS_WAY),
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.ICACHE_INDEX_HI(ICACHE_INDEX_HI),
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.ICACHE_BANK_HI(ICACHE_BANK_HI),
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.ICACHE_BANK_LO(ICACHE_BANK_LO),
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.ICACHE_TAG_LO(ICACHE_TAG_LO),
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.ICACHE_DATA_INDEX_LO(ICACHE_DATA_INDEX_LO),
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.ICACHE_ECC(ICACHE_ECC),
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.ICACHE_TAG_DEPTH(ICACHE_TAG_DEPTH),
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.ICACHE_WAYPACK(ICACHE_WAYPACK),
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.ICACHE_TAG_INDEX_LO(ICACHE_TAG_INDEX_LO),
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.ICACHE_DATA_DEPTH(ICACHE_DATA_DEPTH)) icm (
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.clk_override(icm_clk_override),
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.*
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);
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end
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else begin
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assign ic_rd_hit[ICACHE_NUM_WAYS-1:0] = '0;
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assign ic_tag_perr = '0 ;
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assign ic_rd_data = '0 ;
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assign ic_tag_debug_rd_data = '0 ;
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end // else: !if( ICACHE_ENABLE )
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if (ICCM_ENABLE) begin : iccm
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ifu_iccm_mem #(
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.ICCM_BITS(ICCM_BITS),
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.ICCM_BANK_INDEX_LO(ICCM_BANK_INDEX_LO),
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.ICCM_INDEX_BITS(ICCM_INDEX_BITS),
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.ICCM_BANK_HI(ICCM_BANK_HI),
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.ICCM_NUM_BANKS(ICCM_NUM_BANKS),
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.ICCM_BANK_BITS(ICCM_BANK_BITS)) iccm (.*,
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.clk_override(icm_clk_override),
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.iccm_rw_addr(iccm_rw_addr[ICCM_BITS-1:1]),
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.iccm_rd_data(iccm_rd_data[63:0])
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);
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end
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else begin
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assign iccm_rd_data = '0 ;
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assign iccm_rd_data_ecc = '0 ;
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end
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endmodule
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File diff suppressed because it is too large
Load Diff
File diff suppressed because one or more lines are too long
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Load Diff
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@ -0,0 +1,46 @@
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[
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~sbox|sbox>io_s_box_out_valid",
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"sources":[
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"~sbox|sbox>io_op"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~sbox|sbox>io_inv_s_box_out_bits",
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"sources":[
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"~sbox|sbox>io_in"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~sbox|sbox>io_s_box_out_bits",
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"sources":[
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"~sbox|sbox>io_in"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~sbox|sbox>io_inv_s_box_out_valid",
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"sources":[
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"~sbox|sbox>io_op"
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]
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},
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{
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"class":"firrtl.EmitCircuitAnnotation",
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"emitter":"firrtl.VerilogEmitter"
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},
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{
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"class":"firrtl.options.TargetDirAnnotation",
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"directory":"."
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},
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{
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"class":"firrtl.options.OutputAnnotationFileAnnotation",
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"file":"sbox"
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},
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{
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"class":"firrtl.transforms.BlackBoxTargetDirAnno",
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"targetDir":"."
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}
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]
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@ -0,0 +1,143 @@
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;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
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circuit sbox :
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module sbox :
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input clock : Clock
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input reset : UInt<1>
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output io : {flip in : UInt<4>, flip op : UInt<1>, s_box_out : {valid : UInt<1>, bits : UInt<4>}, inv_s_box_out : {valid : UInt<1>, bits : UInt<4>}}
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node _T = eq(io.op, UInt<1>("h00")) @[quasar_wrapper.scala 183:32]
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io.s_box_out.valid <= _T @[quasar_wrapper.scala 183:29]
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io.inv_s_box_out.valid <= io.op @[quasar_wrapper.scala 184:29]
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node _T_1 = eq(io.in, UInt<1>("h00")) @[quasar_wrapper.scala 185:74]
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node _T_2 = bits(_T_1, 0, 0) @[quasar_wrapper.scala 185:89]
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node _T_3 = eq(io.in, UInt<1>("h01")) @[quasar_wrapper.scala 185:74]
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node _T_4 = bits(_T_3, 0, 0) @[quasar_wrapper.scala 185:89]
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node _T_5 = eq(io.in, UInt<2>("h02")) @[quasar_wrapper.scala 185:74]
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node _T_6 = bits(_T_5, 0, 0) @[quasar_wrapper.scala 185:89]
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node _T_7 = eq(io.in, UInt<2>("h03")) @[quasar_wrapper.scala 185:74]
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node _T_8 = bits(_T_7, 0, 0) @[quasar_wrapper.scala 185:89]
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node _T_9 = eq(io.in, UInt<3>("h04")) @[quasar_wrapper.scala 185:74]
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node _T_10 = bits(_T_9, 0, 0) @[quasar_wrapper.scala 185:89]
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node _T_11 = eq(io.in, UInt<3>("h05")) @[quasar_wrapper.scala 185:74]
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node _T_12 = bits(_T_11, 0, 0) @[quasar_wrapper.scala 185:89]
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node _T_13 = eq(io.in, UInt<3>("h06")) @[quasar_wrapper.scala 185:74]
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node _T_14 = bits(_T_13, 0, 0) @[quasar_wrapper.scala 185:89]
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node _T_15 = eq(io.in, UInt<3>("h07")) @[quasar_wrapper.scala 185:74]
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node _T_16 = bits(_T_15, 0, 0) @[quasar_wrapper.scala 185:89]
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node _T_17 = eq(io.in, UInt<4>("h08")) @[quasar_wrapper.scala 185:74]
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node _T_18 = bits(_T_17, 0, 0) @[quasar_wrapper.scala 185:89]
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node _T_19 = eq(io.in, UInt<4>("h09")) @[quasar_wrapper.scala 185:74]
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node _T_20 = bits(_T_19, 0, 0) @[quasar_wrapper.scala 185:89]
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node _T_21 = eq(io.in, UInt<4>("h0a")) @[quasar_wrapper.scala 185:74]
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node _T_22 = bits(_T_21, 0, 0) @[quasar_wrapper.scala 185:89]
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node _T_23 = eq(io.in, UInt<4>("h0b")) @[quasar_wrapper.scala 185:74]
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node _T_24 = bits(_T_23, 0, 0) @[quasar_wrapper.scala 185:89]
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node _T_25 = eq(io.in, UInt<4>("h0c")) @[quasar_wrapper.scala 185:74]
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node _T_26 = bits(_T_25, 0, 0) @[quasar_wrapper.scala 185:89]
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node _T_27 = eq(io.in, UInt<4>("h0d")) @[quasar_wrapper.scala 185:74]
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node _T_28 = bits(_T_27, 0, 0) @[quasar_wrapper.scala 185:89]
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node _T_29 = eq(io.in, UInt<4>("h0e")) @[quasar_wrapper.scala 185:74]
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node _T_30 = bits(_T_29, 0, 0) @[quasar_wrapper.scala 185:89]
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node _T_31 = eq(io.in, UInt<4>("h0f")) @[quasar_wrapper.scala 185:74]
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node _T_32 = bits(_T_31, 0, 0) @[quasar_wrapper.scala 185:89]
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node _T_33 = mux(_T_2, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_34 = mux(_T_4, UInt<2>("h03"), UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_35 = mux(_T_6, UInt<4>("h0e"), UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_36 = mux(_T_8, UInt<4>("h09"), UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_37 = mux(_T_10, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_38 = mux(_T_12, UInt<4>("h0d"), UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_39 = mux(_T_14, UInt<4>("h0a"), UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_40 = mux(_T_16, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_41 = mux(_T_18, UInt<3>("h05"), UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_42 = mux(_T_20, UInt<4>("h08"), UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_43 = mux(_T_22, UInt<4>("h0f"), UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_44 = mux(_T_24, UInt<3>("h04"), UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_45 = mux(_T_26, UInt<3>("h06"), UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_46 = mux(_T_28, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_47 = mux(_T_30, UInt<4>("h0c"), UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_48 = mux(_T_32, UInt<4>("h0b"), UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_49 = or(_T_33, _T_34) @[Mux.scala 27:72]
|
||||
node _T_50 = or(_T_49, _T_35) @[Mux.scala 27:72]
|
||||
node _T_51 = or(_T_50, _T_36) @[Mux.scala 27:72]
|
||||
node _T_52 = or(_T_51, _T_37) @[Mux.scala 27:72]
|
||||
node _T_53 = or(_T_52, _T_38) @[Mux.scala 27:72]
|
||||
node _T_54 = or(_T_53, _T_39) @[Mux.scala 27:72]
|
||||
node _T_55 = or(_T_54, _T_40) @[Mux.scala 27:72]
|
||||
node _T_56 = or(_T_55, _T_41) @[Mux.scala 27:72]
|
||||
node _T_57 = or(_T_56, _T_42) @[Mux.scala 27:72]
|
||||
node _T_58 = or(_T_57, _T_43) @[Mux.scala 27:72]
|
||||
node _T_59 = or(_T_58, _T_44) @[Mux.scala 27:72]
|
||||
node _T_60 = or(_T_59, _T_45) @[Mux.scala 27:72]
|
||||
node _T_61 = or(_T_60, _T_46) @[Mux.scala 27:72]
|
||||
node _T_62 = or(_T_61, _T_47) @[Mux.scala 27:72]
|
||||
node _T_63 = or(_T_62, _T_48) @[Mux.scala 27:72]
|
||||
wire _T_64 : UInt<4> @[Mux.scala 27:72]
|
||||
_T_64 <= _T_63 @[Mux.scala 27:72]
|
||||
io.s_box_out.bits <= _T_64 @[quasar_wrapper.scala 185:21]
|
||||
node _T_65 = eq(io.in, UInt<1>("h00")) @[quasar_wrapper.scala 186:78]
|
||||
node _T_66 = bits(_T_65, 0, 0) @[quasar_wrapper.scala 186:93]
|
||||
node _T_67 = eq(io.in, UInt<1>("h01")) @[quasar_wrapper.scala 186:78]
|
||||
node _T_68 = bits(_T_67, 0, 0) @[quasar_wrapper.scala 186:93]
|
||||
node _T_69 = eq(io.in, UInt<2>("h02")) @[quasar_wrapper.scala 186:78]
|
||||
node _T_70 = bits(_T_69, 0, 0) @[quasar_wrapper.scala 186:93]
|
||||
node _T_71 = eq(io.in, UInt<2>("h03")) @[quasar_wrapper.scala 186:78]
|
||||
node _T_72 = bits(_T_71, 0, 0) @[quasar_wrapper.scala 186:93]
|
||||
node _T_73 = eq(io.in, UInt<3>("h04")) @[quasar_wrapper.scala 186:78]
|
||||
node _T_74 = bits(_T_73, 0, 0) @[quasar_wrapper.scala 186:93]
|
||||
node _T_75 = eq(io.in, UInt<3>("h05")) @[quasar_wrapper.scala 186:78]
|
||||
node _T_76 = bits(_T_75, 0, 0) @[quasar_wrapper.scala 186:93]
|
||||
node _T_77 = eq(io.in, UInt<3>("h06")) @[quasar_wrapper.scala 186:78]
|
||||
node _T_78 = bits(_T_77, 0, 0) @[quasar_wrapper.scala 186:93]
|
||||
node _T_79 = eq(io.in, UInt<3>("h07")) @[quasar_wrapper.scala 186:78]
|
||||
node _T_80 = bits(_T_79, 0, 0) @[quasar_wrapper.scala 186:93]
|
||||
node _T_81 = eq(io.in, UInt<4>("h08")) @[quasar_wrapper.scala 186:78]
|
||||
node _T_82 = bits(_T_81, 0, 0) @[quasar_wrapper.scala 186:93]
|
||||
node _T_83 = eq(io.in, UInt<4>("h09")) @[quasar_wrapper.scala 186:78]
|
||||
node _T_84 = bits(_T_83, 0, 0) @[quasar_wrapper.scala 186:93]
|
||||
node _T_85 = eq(io.in, UInt<4>("h0a")) @[quasar_wrapper.scala 186:78]
|
||||
node _T_86 = bits(_T_85, 0, 0) @[quasar_wrapper.scala 186:93]
|
||||
node _T_87 = eq(io.in, UInt<4>("h0b")) @[quasar_wrapper.scala 186:78]
|
||||
node _T_88 = bits(_T_87, 0, 0) @[quasar_wrapper.scala 186:93]
|
||||
node _T_89 = eq(io.in, UInt<4>("h0c")) @[quasar_wrapper.scala 186:78]
|
||||
node _T_90 = bits(_T_89, 0, 0) @[quasar_wrapper.scala 186:93]
|
||||
node _T_91 = eq(io.in, UInt<4>("h0d")) @[quasar_wrapper.scala 186:78]
|
||||
node _T_92 = bits(_T_91, 0, 0) @[quasar_wrapper.scala 186:93]
|
||||
node _T_93 = eq(io.in, UInt<4>("h0e")) @[quasar_wrapper.scala 186:78]
|
||||
node _T_94 = bits(_T_93, 0, 0) @[quasar_wrapper.scala 186:93]
|
||||
node _T_95 = eq(io.in, UInt<4>("h0f")) @[quasar_wrapper.scala 186:78]
|
||||
node _T_96 = bits(_T_95, 0, 0) @[quasar_wrapper.scala 186:93]
|
||||
node _T_97 = mux(_T_66, UInt<3>("h04"), UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_98 = mux(_T_68, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_99 = mux(_T_70, UInt<4>("h0d"), UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_100 = mux(_T_72, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_101 = mux(_T_74, UInt<4>("h0b"), UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_102 = mux(_T_76, UInt<4>("h08"), UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_103 = mux(_T_78, UInt<4>("h0c"), UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_104 = mux(_T_80, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_105 = mux(_T_82, UInt<4>("h09"), UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_106 = mux(_T_84, UInt<2>("h03"), UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_107 = mux(_T_86, UInt<3>("h06"), UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_108 = mux(_T_88, UInt<4>("h0f"), UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_109 = mux(_T_90, UInt<4>("h0e"), UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_110 = mux(_T_92, UInt<3>("h05"), UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_111 = mux(_T_94, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_112 = mux(_T_96, UInt<4>("h0a"), UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_113 = or(_T_97, _T_98) @[Mux.scala 27:72]
|
||||
node _T_114 = or(_T_113, _T_99) @[Mux.scala 27:72]
|
||||
node _T_115 = or(_T_114, _T_100) @[Mux.scala 27:72]
|
||||
node _T_116 = or(_T_115, _T_101) @[Mux.scala 27:72]
|
||||
node _T_117 = or(_T_116, _T_102) @[Mux.scala 27:72]
|
||||
node _T_118 = or(_T_117, _T_103) @[Mux.scala 27:72]
|
||||
node _T_119 = or(_T_118, _T_104) @[Mux.scala 27:72]
|
||||
node _T_120 = or(_T_119, _T_105) @[Mux.scala 27:72]
|
||||
node _T_121 = or(_T_120, _T_106) @[Mux.scala 27:72]
|
||||
node _T_122 = or(_T_121, _T_107) @[Mux.scala 27:72]
|
||||
node _T_123 = or(_T_122, _T_108) @[Mux.scala 27:72]
|
||||
node _T_124 = or(_T_123, _T_109) @[Mux.scala 27:72]
|
||||
node _T_125 = or(_T_124, _T_110) @[Mux.scala 27:72]
|
||||
node _T_126 = or(_T_125, _T_111) @[Mux.scala 27:72]
|
||||
node _T_127 = or(_T_126, _T_112) @[Mux.scala 27:72]
|
||||
wire _T_128 : UInt<4> @[Mux.scala 27:72]
|
||||
_T_128 <= _T_127 @[Mux.scala 27:72]
|
||||
io.inv_s_box_out.bits <= _T_128 @[quasar_wrapper.scala 186:25]
|
||||
|
||||
|
|
@ -0,0 +1,98 @@
|
|||
module sbox(
|
||||
input clock,
|
||||
input reset,
|
||||
input [3:0] io_in,
|
||||
input io_op,
|
||||
output io_s_box_out_valid,
|
||||
output [3:0] io_s_box_out_bits,
|
||||
output io_inv_s_box_out_valid,
|
||||
output [3:0] io_inv_s_box_out_bits
|
||||
);
|
||||
wire _T_1 = io_in == 4'h0; // @[quasar_wrapper.scala 185:74]
|
||||
wire _T_3 = io_in == 4'h1; // @[quasar_wrapper.scala 185:74]
|
||||
wire _T_5 = io_in == 4'h2; // @[quasar_wrapper.scala 185:74]
|
||||
wire _T_7 = io_in == 4'h3; // @[quasar_wrapper.scala 185:74]
|
||||
wire _T_9 = io_in == 4'h4; // @[quasar_wrapper.scala 185:74]
|
||||
wire _T_11 = io_in == 4'h5; // @[quasar_wrapper.scala 185:74]
|
||||
wire _T_13 = io_in == 4'h6; // @[quasar_wrapper.scala 185:74]
|
||||
wire _T_15 = io_in == 4'h7; // @[quasar_wrapper.scala 185:74]
|
||||
wire _T_17 = io_in == 4'h8; // @[quasar_wrapper.scala 185:74]
|
||||
wire _T_19 = io_in == 4'h9; // @[quasar_wrapper.scala 185:74]
|
||||
wire _T_21 = io_in == 4'ha; // @[quasar_wrapper.scala 185:74]
|
||||
wire _T_23 = io_in == 4'hb; // @[quasar_wrapper.scala 185:74]
|
||||
wire _T_25 = io_in == 4'hc; // @[quasar_wrapper.scala 185:74]
|
||||
wire _T_27 = io_in == 4'hd; // @[quasar_wrapper.scala 185:74]
|
||||
wire _T_29 = io_in == 4'he; // @[quasar_wrapper.scala 185:74]
|
||||
wire _T_31 = io_in == 4'hf; // @[quasar_wrapper.scala 185:74]
|
||||
wire [2:0] _T_33 = _T_1 ? 3'h7 : 3'h0; // @[Mux.scala 27:72]
|
||||
wire [1:0] _T_34 = _T_3 ? 2'h3 : 2'h0; // @[Mux.scala 27:72]
|
||||
wire [3:0] _T_35 = _T_5 ? 4'he : 4'h0; // @[Mux.scala 27:72]
|
||||
wire [3:0] _T_36 = _T_7 ? 4'h9 : 4'h0; // @[Mux.scala 27:72]
|
||||
wire [3:0] _T_38 = _T_11 ? 4'hd : 4'h0; // @[Mux.scala 27:72]
|
||||
wire [3:0] _T_39 = _T_13 ? 4'ha : 4'h0; // @[Mux.scala 27:72]
|
||||
wire [2:0] _T_41 = _T_17 ? 3'h5 : 3'h0; // @[Mux.scala 27:72]
|
||||
wire [3:0] _T_42 = _T_19 ? 4'h8 : 4'h0; // @[Mux.scala 27:72]
|
||||
wire [3:0] _T_43 = _T_21 ? 4'hf : 4'h0; // @[Mux.scala 27:72]
|
||||
wire [2:0] _T_44 = _T_23 ? 3'h4 : 3'h0; // @[Mux.scala 27:72]
|
||||
wire [2:0] _T_45 = _T_25 ? 3'h6 : 3'h0; // @[Mux.scala 27:72]
|
||||
wire [1:0] _T_46 = _T_27 ? 2'h2 : 2'h0; // @[Mux.scala 27:72]
|
||||
wire [3:0] _T_47 = _T_29 ? 4'hc : 4'h0; // @[Mux.scala 27:72]
|
||||
wire [3:0] _T_48 = _T_31 ? 4'hb : 4'h0; // @[Mux.scala 27:72]
|
||||
wire [2:0] _GEN_0 = {{1'd0}, _T_34}; // @[Mux.scala 27:72]
|
||||
wire [2:0] _T_49 = _T_33 | _GEN_0; // @[Mux.scala 27:72]
|
||||
wire [3:0] _GEN_1 = {{1'd0}, _T_49}; // @[Mux.scala 27:72]
|
||||
wire [3:0] _T_50 = _GEN_1 | _T_35; // @[Mux.scala 27:72]
|
||||
wire [3:0] _T_51 = _T_50 | _T_36; // @[Mux.scala 27:72]
|
||||
wire [3:0] _T_53 = _T_51 | _T_38; // @[Mux.scala 27:72]
|
||||
wire [3:0] _T_54 = _T_53 | _T_39; // @[Mux.scala 27:72]
|
||||
wire [3:0] _GEN_2 = {{3'd0}, _T_15}; // @[Mux.scala 27:72]
|
||||
wire [3:0] _T_55 = _T_54 | _GEN_2; // @[Mux.scala 27:72]
|
||||
wire [3:0] _GEN_3 = {{1'd0}, _T_41}; // @[Mux.scala 27:72]
|
||||
wire [3:0] _T_56 = _T_55 | _GEN_3; // @[Mux.scala 27:72]
|
||||
wire [3:0] _T_57 = _T_56 | _T_42; // @[Mux.scala 27:72]
|
||||
wire [3:0] _T_58 = _T_57 | _T_43; // @[Mux.scala 27:72]
|
||||
wire [3:0] _GEN_4 = {{1'd0}, _T_44}; // @[Mux.scala 27:72]
|
||||
wire [3:0] _T_59 = _T_58 | _GEN_4; // @[Mux.scala 27:72]
|
||||
wire [3:0] _GEN_5 = {{1'd0}, _T_45}; // @[Mux.scala 27:72]
|
||||
wire [3:0] _T_60 = _T_59 | _GEN_5; // @[Mux.scala 27:72]
|
||||
wire [3:0] _GEN_6 = {{2'd0}, _T_46}; // @[Mux.scala 27:72]
|
||||
wire [3:0] _T_61 = _T_60 | _GEN_6; // @[Mux.scala 27:72]
|
||||
wire [3:0] _T_62 = _T_61 | _T_47; // @[Mux.scala 27:72]
|
||||
wire [2:0] _T_97 = _T_1 ? 3'h4 : 3'h0; // @[Mux.scala 27:72]
|
||||
wire [2:0] _T_98 = _T_3 ? 3'h7 : 3'h0; // @[Mux.scala 27:72]
|
||||
wire [3:0] _T_99 = _T_5 ? 4'hd : 4'h0; // @[Mux.scala 27:72]
|
||||
wire [3:0] _T_101 = _T_9 ? 4'hb : 4'h0; // @[Mux.scala 27:72]
|
||||
wire [3:0] _T_102 = _T_11 ? 4'h8 : 4'h0; // @[Mux.scala 27:72]
|
||||
wire [3:0] _T_103 = _T_13 ? 4'hc : 4'h0; // @[Mux.scala 27:72]
|
||||
wire [3:0] _T_105 = _T_17 ? 4'h9 : 4'h0; // @[Mux.scala 27:72]
|
||||
wire [1:0] _T_106 = _T_19 ? 2'h3 : 2'h0; // @[Mux.scala 27:72]
|
||||
wire [2:0] _T_107 = _T_21 ? 3'h6 : 3'h0; // @[Mux.scala 27:72]
|
||||
wire [3:0] _T_108 = _T_23 ? 4'hf : 4'h0; // @[Mux.scala 27:72]
|
||||
wire [3:0] _T_109 = _T_25 ? 4'he : 4'h0; // @[Mux.scala 27:72]
|
||||
wire [2:0] _T_110 = _T_27 ? 3'h5 : 3'h0; // @[Mux.scala 27:72]
|
||||
wire [1:0] _T_111 = _T_29 ? 2'h2 : 2'h0; // @[Mux.scala 27:72]
|
||||
wire [3:0] _T_112 = _T_31 ? 4'ha : 4'h0; // @[Mux.scala 27:72]
|
||||
wire [2:0] _T_113 = _T_97 | _T_98; // @[Mux.scala 27:72]
|
||||
wire [3:0] _GEN_7 = {{1'd0}, _T_113}; // @[Mux.scala 27:72]
|
||||
wire [3:0] _T_114 = _GEN_7 | _T_99; // @[Mux.scala 27:72]
|
||||
wire [3:0] _GEN_8 = {{3'd0}, _T_7}; // @[Mux.scala 27:72]
|
||||
wire [3:0] _T_115 = _T_114 | _GEN_8; // @[Mux.scala 27:72]
|
||||
wire [3:0] _T_116 = _T_115 | _T_101; // @[Mux.scala 27:72]
|
||||
wire [3:0] _T_117 = _T_116 | _T_102; // @[Mux.scala 27:72]
|
||||
wire [3:0] _T_118 = _T_117 | _T_103; // @[Mux.scala 27:72]
|
||||
wire [3:0] _T_120 = _T_118 | _T_105; // @[Mux.scala 27:72]
|
||||
wire [3:0] _GEN_9 = {{2'd0}, _T_106}; // @[Mux.scala 27:72]
|
||||
wire [3:0] _T_121 = _T_120 | _GEN_9; // @[Mux.scala 27:72]
|
||||
wire [3:0] _GEN_10 = {{1'd0}, _T_107}; // @[Mux.scala 27:72]
|
||||
wire [3:0] _T_122 = _T_121 | _GEN_10; // @[Mux.scala 27:72]
|
||||
wire [3:0] _T_123 = _T_122 | _T_108; // @[Mux.scala 27:72]
|
||||
wire [3:0] _T_124 = _T_123 | _T_109; // @[Mux.scala 27:72]
|
||||
wire [3:0] _GEN_11 = {{1'd0}, _T_110}; // @[Mux.scala 27:72]
|
||||
wire [3:0] _T_125 = _T_124 | _GEN_11; // @[Mux.scala 27:72]
|
||||
wire [3:0] _GEN_12 = {{2'd0}, _T_111}; // @[Mux.scala 27:72]
|
||||
wire [3:0] _T_126 = _T_125 | _GEN_12; // @[Mux.scala 27:72]
|
||||
assign io_s_box_out_valid = ~io_op; // @[quasar_wrapper.scala 183:29]
|
||||
assign io_s_box_out_bits = _T_62 | _T_48; // @[quasar_wrapper.scala 185:21]
|
||||
assign io_inv_s_box_out_valid = io_op; // @[quasar_wrapper.scala 184:29]
|
||||
assign io_inv_s_box_out_bits = _T_126 | _T_112; // @[quasar_wrapper.scala 186:25]
|
||||
endmodule
|
||||
|
|
@ -285,6 +285,6 @@ class quasar extends Module with RequireAsyncReset with lib {
|
|||
}
|
||||
|
||||
}
|
||||
//object QUASAR extends App {
|
||||
// println((new chisel3.stage.ChiselStage).emitVerilog(new quasar()))
|
||||
//}
|
||||
object QUASAR extends App {
|
||||
println((new chisel3.stage.ChiselStage).emitVerilog(new quasar()))
|
||||
}
|
||||
|
|
@ -160,6 +160,31 @@ class quasar_wrapper extends Module with lib with RequireAsyncReset {
|
|||
io.dec_tlu_perfcnt3 := core.io.dec_tlu_perfcnt3
|
||||
|
||||
}
|
||||
object QUASAR_Wrp extends App {
|
||||
println((new chisel3.stage.ChiselStage).emitVerilog(new quasar_wrapper()))
|
||||
|
||||
class sbox(val word_len: Int, val sbox_size:Int) extends Module{
|
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val io = IO(new Bundle{
|
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val in = Input(UInt(word_len.W))
|
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val op = Input(Bool()) // 0-> sbox, 1-> inv_sbox
|
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val s_box_out = Valid(UInt(word_len.W))
|
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val inv_s_box_out = Valid(UInt(word_len.W))
|
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})
|
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|
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def sbox_gen(x: Int) = {
|
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val r = scala.util.Random
|
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r.shuffle((0 until x*x).map(i=>i)).toList
|
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}
|
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def inv_sbox(sbox: List[Int]) = {
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List.tabulate(sbox.size)(i=>sbox.indexOf(i))
|
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}
|
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val sbox = sbox_gen(sbox_size)
|
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val inv_sbox_list = inv_sbox(sbox)
|
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println(sbox)
|
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println(inv_sbox_list)
|
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io.s_box_out.valid := !io.op
|
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io.inv_s_box_out.valid := io.op
|
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io.s_box_out.bits := Mux1H((0 until sbox_size*sbox_size).map(i=>(io.in === i.U).asBool()->sbox(i).U))
|
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io.inv_s_box_out.bits := Mux1H((0 until sbox_size*sbox_size).map(i=>(io.in === i.U).asBool()->inv_sbox_list(i).U))
|
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}
|
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object sbox_code extends App {
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println((new chisel3.stage.ChiselStage).emitVerilog(new sbox(4, 4)))
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}
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[0m[[0m[0mdebug[0m] [0m[0mJar uptodate: /home/waleedbinehsan/Downloads/Quasar/design/target/scala-2.12/chisel-module-template_2.12-3.3.0.jar[0m
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@ -1,5 +1,5 @@
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# SPDX-License-Identifier: Apache-2.0
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# Copyright 2020 Western Digital Corporation or its affiliates.
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# Copyright 2020 Lampro Mellon or its affiliates.
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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Reference in New Issue