Update el2_lsu_bus_intf.scala
Multi IO replaced with IO bundle.
This commit is contained in:
Jahanzaib Rasheed
GitHub
parent
dffa6e549b
commit
a54f947419
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@ -1,117 +1,119 @@
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class el2_lsu_lsc_ctl extends MultiIOModule
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class el2_lsu_lsc_ctl extends Module
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{
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//val clk = IO(Input(Clock())) //implicit
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//val rst_l = IO(Input(1.W)) //implicit
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val scan_mode = IO(Input(UInt(1.W)))
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val dec_tlu_external_ldfwd_disable = IO(Input(UInt(1.W))) // disable load to load forwarding for externals
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val dec_tlu_wb_coalescing_disable = IO(Input(UInt(1.W))) // disable write buffer coalescing
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val dec_tlu_sideeffect_posted_disable = IO(Input(UInt(1.W))) // disable the posted sideeffect load store to the bus
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val io = IO (new Bundle {
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//val clk = Input(Clock()) //implicit
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//val rst_l = Input(1.W) //implicit
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val scan_mode = Input(UInt(1.W))
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val dec_tlu_external_ldfwd_disable = Input(UInt(1.W)) // disable load to load forwarding for externals
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val dec_tlu_wb_coalescing_disable = Input(UInt(1.W)) // disable write buffer coalescing
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val dec_tlu_sideeffect_posted_disable = Input(UInt(1.W)) // disable the posted sideeffect load store to the bus
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// various clocks needed for the bus reads and writes
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val lsu_c1_m_clk = IO(Input(Clock()))
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val lsu_c1_r_clk = IO(Input(Clock()))
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val lsu_c2_r_clk = IO(Input(Clock()))
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val lsu_bus_ibuf_c1_clk = IO(Input(Clock()))
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val lsu_bus_obuf_c1_clk = IO(Input(Clock()))
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val lsu_bus_buf_c1_clk = IO(Input(Clock()))
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val lsu_free_c2_clk = IO(Input(Clock()))
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val free_clk = IO(Input(Clock()))
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val lsu_busm_clk = IO(Input(Clock()))
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val lsu_c1_m_clk = Input(Clock())
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val lsu_c1_r_clk = Input(Clock())
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val lsu_c2_r_clk = Input(Clock())
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val lsu_bus_ibuf_c1_clk = Input(Clock())
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val lsu_bus_obuf_c1_clk = Input(Clock())
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val lsu_bus_buf_c1_clk = Input(Clock())
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val lsu_free_c2_clk = Input(Clock())
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val free_clk = Input(Clock())
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val lsu_busm_clk = Input(Clock())
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val dec_lsu_valid_raw_d = IO(Input(UInt(1.W)))
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val lsu_busreq_m = IO(Input(UInt(1.W)))
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val dec_lsu_valid_raw_d = Input(UInt(1.W))
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val lsu_busreq_m = Input(UInt(1.W))
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val lsu_addr_d = Input(UInt(32.W))
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val lsu_addr_m = Input(UInt(32.W))
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val lsu_addr_r = Input(UInt(32.W))
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val end_addr_d = Input(UInt(32.W))
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val end_addr_m = Input(UInt(32.W))
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val end_addr_r = Input(UInt(32.W))
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val store_data_m = Input(UInt(32.W))
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val dec_tlu_force_halt = Input(UInt(1.W))
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val lsu_commit_r = Input(UInt(1.W))
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val is_sideeffects_m = Input(UInt(1.W))
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val flush_m_up = Input(UInt(1.W))
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val flush_r = Input(UInt(1.W))
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val lsu_busreq_r = Output(UInt(1.W))
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val lsu_bus_buffer_pend_any = Output(UInt(1.W))
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val lsu_bus_buffer_full_any = Output(UInt(1.W))
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val lsu_bus_buffer_empty_any = Output(UInt(1.W))
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val lsu_bus_idle_any = Output(UInt(1.W))
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val bus_read_data_m = Output(UInt(32.W))
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val lsu_imprecise_error_load_any = Output(UInt(1.W))
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val lsu_imprecise_error_store_any = Output(UInt(1.W))
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val lsu_imprecise_error_addr_any = Output(UInt(32.W))
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val lsu_nonblock_load_valid_m = Output(UInt(1.W))
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val lsu_nonblock_load_tag_m = Output(UInt(pt1.LSU_NUM_NBLOAD_WIDTH.W))
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val lsu_nonblock_load_inv_r = Output(UInt(1.W))
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val lsu_nonblock_load_inv_tag_r = Output(UInt(pt1.LSU_NUM_NBLOAD_WIDTH.W))
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val lsu_nonblock_load_data_valid = Output(UInt(1.W))
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val lsu_nonblock_load_data_error = Output(UInt(32.W))
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val lsu_nonblock_load_data_tag = Output(UInt(pt1.LSU_NUM_NBLOAD_WIDTH.W))
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val lsu_nonblock_load_data = Output(UInt(32.W))
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val lsu_pmu_bus_trxn = Output(UInt(1.W))
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val lsu_pmu_bus_misaligned = Output(UInt(1.W))
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val lsu_pmu_bus_error = Output(UInt(1.W))
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val lsu_pmu_bus_busy = Output(UInt(1.W))
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val lsu_axi_awvalid = Output(UInt(1.W))
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val lsu_axi_awready = Input(UInt(1.W))
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val lsu_axi_awid = Output(UInt(pt1.LSU_BUS_TAG.W))
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val lsu_axi_awaddr = Output(UInt(32.W))
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val lsu_axi_awregion = Output(UInt(4.W))
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val lsu_axi_awlen = Output(UInt(8.W))
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val lsu_axi_awsize = Output(UInt(3.W))
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val lsu_axi_awburst = Output(UInt(2.W))
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val lsu_axi_awlock = Output(UInt(1.W))
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val lsu_axi_awcache = Output(UInt(4.W))
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val lsu_axi_awprot = Output(UInt(3.W))
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val lsu_axi_awqos = Output(UInt(4.W))
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val lsu_axi_wvalid = Output(UInt(1.W))
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val lsu_axi_wready = Input(UInt(1.W))
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val lsu_axi_wdata = Output(UInt(64.W))
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val lsu_axi_wstrb = Output(UInt(8.W))
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val lsu_axi_wlast = Output(UInt(1.W))
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val lsu_axi_bvalid = Input(UInt(1.W))
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val lsu_axi_bready = Output(UInt(1.W))
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val lsu_axi_bresp = Input(UInt(2.W))
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val lsu_axi_bid = Input(UInt(pt1.LSU_BUS_TAG.W))
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val lsu_axi_arvalid = Output(UInt(1.W))
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val lsu_axi_arready = Input(UInt(1.W))
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val lsu_axi_arid = Output(UInt(pt1.LSU_BUS_TAG.W))
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val lsu_axi_araddr = Output(UInt(32.W))
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val lsu_axi_arregion = Output(UInt(4.W))
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val lsu_axi_arlen = Output(UInt(8.W))
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val lsu_axi_arsize = Output(UInt(3.W))
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val lsu_axi_arburst = Output(UInt(2.W))
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val lsu_axi_arlock = Output(UInt(1.W))
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val lsu_axi_arcache = Output(UInt(4.W))
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val lsu_axi_arprot = Output(UInt(3.W))
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val lsu_axi_arqos = Output(UInt(4.W))
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val lsu_axi_rvalid = Input(UInt(1.W))
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val lsu_axi_rready = Output(UInt(1.W))
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val lsu_axi_rid = Input(UInt(pt1.LSU_BUS_TAG.W))
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val lsu_axi_rdata = Input(UInt(64.W))
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val lsu_axi_rresp = Intput(UInt(2.W))
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val lsu_axi_rlast = Intput(UInt(1.W))
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val lsu_bus_clk_en = Intput(UInt(1.W))
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})
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val lsu_pkt_m = new el2_lsu_pkt_t()
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val lsu_pkt_r = new el2_lsu_pkt_t()
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val lsu_addr_d = IO(Input(UInt(32.W)))
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val lsu_addr_m = IO(Input(UInt(32.W)))
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val lsu_addr_r = IO(Input(UInt(32.W)))
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val end_addr_d = IO(Input(UInt(32.W)))
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val end_addr_m = IO(Input(UInt(32.W)))
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val end_addr_r = IO(Input(UInt(32.W)))
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val store_data_m = IO(Input(UInt(32.W)))
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val dec_tlu_force_halt = IO(Input(UInt(1.W)))
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val lsu_commit_r = IO(Input(UInt(1.W)))
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val is_sideeffects_m = IO(Input(UInt(1.W)))
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val flush_m_up = IO(Input(UInt(1.W)))
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val flush_r = IO(Input(UInt(1.W)))
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val lsu_busreq_r = IO(Output(UInt(1.W)))
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val lsu_bus_buffer_pend_any = IO(Output(UInt(1.W)))
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val lsu_bus_buffer_full_any = IO(Output(UInt(1.W)))
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val lsu_bus_buffer_empty_any = IO(Output(UInt(1.W)))
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val lsu_bus_idle_any = IO(Output(UInt(1.W)))
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val bus_read_data_m = IO(Output(UInt(32.W)))
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val lsu_imprecise_error_load_any = IO(Output(UInt(1.W)))
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val lsu_imprecise_error_store_any = IO(Output(UInt(1.W)))
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val lsu_imprecise_error_addr_any = IO(Output(UInt(32.W)))
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val lsu_nonblock_load_valid_m = IO(Output(UInt(1.W)))
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val lsu_nonblock_load_tag_m = IO(Output(UInt(pt1.LSU_NUM_NBLOAD_WIDTH.W)))
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val lsu_nonblock_load_inv_r = IO(Output(UInt(1.W)))
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val lsu_nonblock_load_inv_tag_r = IO(Output(UInt(pt1.LSU_NUM_NBLOAD_WIDTH.W)))
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val lsu_nonblock_load_data_valid = IO(Output(UInt(1.W)))
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val lsu_nonblock_load_data_error = IO(Output(UInt(32.W)))
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val lsu_nonblock_load_data_tag = IO(Output(UInt(pt1.LSU_NUM_NBLOAD_WIDTH.W)))
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val lsu_nonblock_load_data = IO(Output(UInt(32.W)))
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val lsu_pmu_bus_trxn = IO(Output(UInt(1.W)))
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val lsu_pmu_bus_misaligned = IO(Output(UInt(1.W)))
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val lsu_pmu_bus_error = IO(Output(UInt(1.W)))
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val lsu_pmu_bus_busy = IO(Output(UInt(1.W)))
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val lsu_axi_awvalid = IO(Output(UInt(1.W)))
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val lsu_axi_awready = IO(Input(UInt(1.W)))
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val lsu_axi_awid = IO(Output(UInt(pt1.LSU_BUS_TAG.W)))
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val lsu_axi_awaddr = IO(Output(UInt(32.W)))
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val lsu_axi_awregion = IO(Output(UInt(4.W)))
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val lsu_axi_awlen = IO(Output(UInt(8.W)))
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val lsu_axi_awsize = IO(Output(UInt(3.W)))
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val lsu_axi_awburst = IO(Output(UInt(2.W)))
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val lsu_axi_awlock = IO(Output(UInt(1.W)))
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val lsu_axi_awcache = IO(Output(UInt(4.W)))
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val lsu_axi_awprot = IO(Output(UInt(3.W)))
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val lsu_axi_awqos = IO(Output(UInt(4.W)))
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val lsu_axi_wvalid = IO(Output(UInt(1.W)))
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val lsu_axi_wready = IO(Input(UInt(1.W)))
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val lsu_axi_wdata = IO(Output(UInt(64.W)))
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val lsu_axi_wstrb = IO(Output(UInt(8.W)))
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val lsu_axi_wlast = IO(Output(UInt(1.W)))
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val lsu_axi_bvalid = IO(Input(UInt(1.W)))
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val lsu_axi_bready = IO(Output(UInt(1.W)))
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val lsu_axi_bresp = IO(Input(UInt(2.W)))
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val lsu_axi_bid = IO(Input(UInt(pt1.LSU_BUS_TAG.W)))
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val lsu_axi_arvalid = IO(Output(UInt(1.W)))
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val lsu_axi_arready = IO(Input(UInt(1.W)))
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val lsu_axi_arid = IO(Output(UInt(pt1.LSU_BUS_TAG.W)))
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val lsu_axi_araddr = IO(Output(UInt(32.W)))
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val lsu_axi_arregion = IO(Output(UInt(4.W)))
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val lsu_axi_arlen = IO(Output(UInt(8.W)))
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val lsu_axi_arsize = IO(Output(UInt(3.W)))
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val lsu_axi_arburst = IO(Output(UInt(2.W)))
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val lsu_axi_arlock = IO(Output(UInt(1.W)))
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val lsu_axi_arcache = IO(Output(UInt(4.W)))
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val lsu_axi_arprot = IO(Output(UInt(3.W)))
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val lsu_axi_arqos = IO(Output(UInt(4.W)))
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val lsu_axi_rvalid = IO(Input(UInt(1.W)))
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val lsu_axi_rready = IO(Output(UInt(1.W)))
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val lsu_axi_rid = IO(Input(UInt(pt1.LSU_BUS_TAG.W)))
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val lsu_axi_rdata = IO(Input(UInt(64.W)))
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val lsu_axi_rresp = IO(Intput(UInt(2.W)))
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val lsu_axi_rlast = IO(Intput(UInt(1.W)))
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val lsu_bus_clk_en = IO(Intput(UInt(1.W)))
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lsu_busreq_r := 0.U
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lsu_bus_buffer_pend_any := 0.U
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@ -170,33 +172,6 @@ class el2_lsu_lsc_ctl extends MultiIOModule
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lsu_axi_arqos := 0.U
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lsu_axi_rready := 0.U
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/*
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// Store buffer related signals
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val lsu_pkt_d = new el2_lsu_pkt_t()
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val dma_pkt_d = new el2_lsu_pkt_t()
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val lsu_pkt_m_in = new el2_lsu_pkt_t()
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val lsu_pkt_r_in = new el2_lsu_pkt_t()
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val lsu_error_pkt_m = new el2_lsu_error_pkt_t()
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val lsu_rs1_d = Mux(dec_lsu_valid_raw_d.asBool,dec_lsu_valid_raw_d, dec_lsu_valid_raw_d)
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val lsu_offset_d = dec_lsu_offset_d(11,0) & Fill(12,dec_lsu_valid_raw_d)
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val rs1_d_raw = lsu_rs1_d
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val offset_d = lsu_offset_d
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val rs1_d = Mux(lsu_pkt_d.load_ldst_bypass_d.asBool,lsu_result_m,rs1_d_raw)
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val lsadder = new rvlsadder()
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lsadder.io.rs1 := rs1_d
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lsadder.io.offset := offset_d
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val full_addr_d = lsadder.io.dout
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*/
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}
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