diff --git a/src/main/scala/lsu/el2_lsu_bus_intf.scala b/src/main/scala/lsu/el2_lsu_bus_intf.scala
index 056bfa4a..6c76afa6 100644
--- a/src/main/scala/lsu/el2_lsu_bus_intf.scala
+++ b/src/main/scala/lsu/el2_lsu_bus_intf.scala
@@ -108,10 +108,10 @@ class  el2_lsu_bus_intf extends Module
    val lsu_axi_rready      = Output(UInt(1.W))
    val lsu_axi_rid         = Input(UInt(pt1.LSU_BUS_TAG.W))
    val lsu_axi_rdata       = Input(UInt(64.W))
-   val lsu_axi_rresp       = Intput(UInt(2.W))
-   val lsu_axi_rlast       = Intput(UInt(1.W))
+   val lsu_axi_rresp       = Input(UInt(2.W))
+   val lsu_axi_rlast       = Input(UInt(1.W))
 
-   val lsu_bus_clk_en      = Intput(UInt(1.W))
+   val lsu_bus_clk_en      = Input(UInt(1.W))
    })
    
    val lsu_pkt_m = new el2_lsu_pkt_t()
@@ -180,4 +180,4 @@ class  el2_lsu_bus_intf extends Module
 }
 object busIntfMain extends App {
    println(chisel3.Driver.emitVerilog(new el2_lsu_bus_intf))
-}
\ No newline at end of file
+}