From a73ad4942e1cbb9bf68e860158ee959be222e528 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E2=80=8BLaraib=20Khan?= <​laraib.khan@lampromellon.com> Date: Thu, 10 Dec 2020 12:29:31 +0500 Subject: [PATCH] Bus Buffer Update --- dbg.anno.json | 81 ++ dbg.fir | 1240 +++++++++++++++++ dbg.v | 1044 ++++++++++++++ src/main/scala/dbg/dbg.scala | 3 + src/main/scala/lsu/cipher.scala | 49 + target/scala-2.12/classes/dbg/dbg_top$.class | Bin 0 -> 3840 bytes .../dbg/dbg_top$delayedInit$body.class | Bin 0 -> 724 bytes target/scala-2.12/classes/dbg/dbg_top.class | Bin 0 -> 768 bytes 8 files changed, 2417 insertions(+) create mode 100644 dbg.anno.json create mode 100644 dbg.fir create mode 100644 dbg.v create mode 100644 src/main/scala/lsu/cipher.scala create mode 100644 target/scala-2.12/classes/dbg/dbg_top$.class create mode 100644 target/scala-2.12/classes/dbg/dbg_top$delayedInit$body.class create mode 100644 target/scala-2.12/classes/dbg/dbg_top.class diff --git a/dbg.anno.json b/dbg.anno.json new file mode 100644 index 00000000..02722551 --- /dev/null +++ b/dbg.anno.json @@ -0,0 +1,81 @@ +[ + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dbg|dbg>io_dbg_dma_dbg_ib_dbg_cmd_valid", + "sources":[ + "~dbg|dbg>io_dbg_dec_dbg_ib_dbg_cmd_valid", + "~dbg|dbg>io_dbg_dma_io_dma_dbg_ready" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dbg|dbg>io_dbg_dec_dbg_ib_dbg_cmd_valid", + "sources":[ + "~dbg|dbg>io_dbg_dma_io_dma_dbg_ready" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dbg|dbg>io_dbg_dma_dbg_ib_dbg_cmd_addr", + "sources":[ + "~dbg|dbg>io_dbg_dec_dbg_ib_dbg_cmd_addr" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dbg|dbg>io_dbg_dma_dbg_dctl_dbg_cmd_wrdata", + "sources":[ + "~dbg|dbg>io_dbg_dec_dbg_dctl_dbg_cmd_wrdata" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dbg|dbg>io_dbg_dma_dbg_ib_dbg_cmd_type", + "sources":[ + "~dbg|dbg>io_dbg_dec_dbg_ib_dbg_cmd_type" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dbg|dbg>io_dbg_dma_dbg_ib_dbg_cmd_write", + "sources":[ + "~dbg|dbg>io_dbg_dec_dbg_ib_dbg_cmd_write" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~dbg|dbg>io_dbg_resume_req", + "sources":[ + "~dbg|dbg>io_dec_tlu_mpc_halted_only", + "~dbg|dbg>io_dec_tlu_debug_mode", + "~dbg|dbg>io_dbg_dec_dbg_ib_dbg_cmd_valid", + "~dbg|dbg>io_core_dbg_cmd_done", + "~dbg|dbg>io_dmi_reg_wr_en", + "~dbg|dbg>io_dmi_reg_en", + "~dbg|dbg>io_dbg_dma_io_dma_dbg_ready", + "~dbg|dbg>io_dmi_reg_addr", + "~dbg|dbg>reset" + ] + }, + { + "class":"firrtl.EmitCircuitAnnotation", + "emitter":"firrtl.VerilogEmitter" + }, + { + "class":"firrtl.transforms.BlackBoxResourceAnno", + "target":"dbg.gated_latch", + "resourceId":"/vsrc/gated_latch.v" + }, + { + "class":"firrtl.options.TargetDirAnnotation", + "directory":"." + }, + { + "class":"firrtl.options.OutputAnnotationFileAnnotation", + "file":"dbg" + }, + { + "class":"firrtl.transforms.BlackBoxTargetDirAnno", + "targetDir":"." + } +] \ No newline at end of file diff --git a/dbg.fir b/dbg.fir new file mode 100644 index 00000000..94bee498 --- /dev/null +++ b/dbg.fir @@ -0,0 +1,1240 @@ +;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10 +circuit dbg : + extmodule gated_latch : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_1 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_1 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_1 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_2 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_2 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_2 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_3 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_3 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_3 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_4 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_4 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_4 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_5 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_5 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_5 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + module dbg : + input clock : Clock + input reset : AsyncReset + output io : {dbg_cmd_size : UInt<2>, dbg_core_rst_l : UInt<1>, flip core_dbg_rddata : UInt<32>, flip core_dbg_cmd_done : UInt<1>, flip core_dbg_cmd_fail : UInt<1>, dbg_halt_req : UInt<1>, dbg_resume_req : UInt<1>, flip dec_tlu_debug_mode : UInt<1>, flip dec_tlu_dbg_halted : UInt<1>, flip dec_tlu_mpc_halted_only : UInt<1>, flip dec_tlu_resume_ack : UInt<1>, flip dmi_reg_en : UInt<1>, flip dmi_reg_addr : UInt<7>, flip dmi_reg_wr_en : UInt<1>, flip dmi_reg_wdata : UInt<32>, dmi_reg_rdata : UInt<32>, sb_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip dbg_dec : {dbg_ib : {flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>}, dbg_dctl : {flip dbg_cmd_wrdata : UInt<2>}}, flip dbg_dma : {dbg_ib : {flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>}, dbg_dctl : {flip dbg_cmd_wrdata : UInt<2>}}, flip dbg_dma_io : {flip dbg_dma_bubble : UInt<1>, dma_dbg_ready : UInt<1>}, flip dbg_bus_clk_en : UInt<1>, flip dbg_rst_l : UInt<1>, flip clk_override : UInt<1>, flip scan_mode : UInt<1>} + + wire dbg_state : UInt<3> + dbg_state <= UInt<3>("h00") + wire dbg_state_en : UInt<1> + dbg_state_en <= UInt<1>("h00") + wire sb_state : UInt<4> + sb_state <= UInt<4>("h00") + wire sb_state_en : UInt<1> + sb_state_en <= UInt<1>("h00") + wire dmcontrol_reg : UInt<32> + dmcontrol_reg <= UInt<32>("h00") + wire sbaddress0_reg : UInt<32> + sbaddress0_reg <= UInt<32>("h00") + wire sbcs_sbbusy_wren : UInt<1> + sbcs_sbbusy_wren <= UInt<1>("h00") + wire sbcs_sberror_wren : UInt<1> + sbcs_sberror_wren <= UInt<1>("h00") + wire sb_bus_rdata : UInt<64> + sb_bus_rdata <= UInt<64>("h00") + wire sbaddress0_reg_wren1 : UInt<1> + sbaddress0_reg_wren1 <= UInt<1>("h00") + wire dmstatus_reg : UInt<32> + dmstatus_reg <= UInt<32>("h00") + wire dmstatus_havereset : UInt<1> + dmstatus_havereset <= UInt<1>("h00") + wire dmstatus_resumeack : UInt<1> + dmstatus_resumeack <= UInt<1>("h00") + wire dmstatus_unavail : UInt<1> + dmstatus_unavail <= UInt<1>("h00") + wire dmstatus_running : UInt<1> + dmstatus_running <= UInt<1>("h00") + wire dmstatus_halted : UInt<1> + dmstatus_halted <= UInt<1>("h00") + wire abstractcs_busy_wren : UInt<1> + abstractcs_busy_wren <= UInt<1>("h00") + wire abstractcs_busy_din : UInt<1> + abstractcs_busy_din <= UInt<1>("h00") + wire sb_bus_cmd_read : UInt<1> + sb_bus_cmd_read <= UInt<1>("h00") + wire sb_bus_cmd_write_addr : UInt<1> + sb_bus_cmd_write_addr <= UInt<1>("h00") + wire sb_bus_cmd_write_data : UInt<1> + sb_bus_cmd_write_data <= UInt<1>("h00") + wire sb_bus_rsp_read : UInt<1> + sb_bus_rsp_read <= UInt<1>("h00") + wire sb_bus_rsp_error : UInt<1> + sb_bus_rsp_error <= UInt<1>("h00") + wire sb_bus_rsp_write : UInt<1> + sb_bus_rsp_write <= UInt<1>("h00") + wire sbcs_sbbusy_din : UInt<1> + sbcs_sbbusy_din <= UInt<1>("h00") + wire sbcs_sberror_din : UInt<3> + sbcs_sberror_din <= UInt<3>("h00") + wire data1_reg : UInt<32> + data1_reg <= UInt<32>("h00") + wire sbcs_reg : UInt<32> + sbcs_reg <= UInt<32>("h00") + node _T = neq(dbg_state, UInt<3>("h00")) @[dbg.scala 95:51] + node _T_1 = or(io.dmi_reg_en, _T) @[dbg.scala 95:38] + node _T_2 = or(_T_1, dbg_state_en) @[dbg.scala 95:69] + node _T_3 = or(_T_2, io.dec_tlu_dbg_halted) @[dbg.scala 95:84] + node dbg_free_clken = or(_T_3, io.clk_override) @[dbg.scala 95:108] + node _T_4 = or(io.dmi_reg_en, sb_state_en) @[dbg.scala 96:37] + node _T_5 = neq(sb_state, UInt<4>("h00")) @[dbg.scala 96:63] + node _T_6 = or(_T_4, _T_5) @[dbg.scala 96:51] + node sb_free_clken = or(_T_6, io.clk_override) @[dbg.scala 96:86] + inst rvclkhdr of rvclkhdr @[el2_lib.scala 483:22] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr.io.en <= dbg_free_clken @[el2_lib.scala 485:16] + rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + inst rvclkhdr_1 of rvclkhdr_1 @[el2_lib.scala 483:22] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_1.io.en <= sb_free_clken @[el2_lib.scala 485:16] + rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + node _T_7 = bits(io.dbg_rst_l, 0, 0) @[dbg.scala 99:41] + node _T_8 = bits(dmcontrol_reg, 0, 0) @[dbg.scala 99:60] + node _T_9 = or(_T_8, io.scan_mode) @[dbg.scala 99:64] + node dbg_dm_rst_l = and(_T_7, _T_9) @[dbg.scala 99:44] + node _T_10 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 100:39] + node _T_11 = eq(_T_10, UInt<1>("h00")) @[dbg.scala 100:25] + node _T_12 = bits(_T_11, 0, 0) @[dbg.scala 100:50] + io.dbg_core_rst_l <= _T_12 @[dbg.scala 100:21] + node _T_13 = eq(io.dmi_reg_addr, UInt<6>("h038")) @[dbg.scala 101:36] + node _T_14 = and(_T_13, io.dmi_reg_en) @[dbg.scala 101:49] + node _T_15 = and(_T_14, io.dmi_reg_wr_en) @[dbg.scala 101:65] + node _T_16 = eq(sb_state, UInt<4>("h00")) @[dbg.scala 101:96] + node sbcs_wren = and(_T_15, _T_16) @[dbg.scala 101:84] + node _T_17 = bits(io.dmi_reg_wdata, 22, 22) @[dbg.scala 102:60] + node _T_18 = and(sbcs_wren, _T_17) @[dbg.scala 102:42] + node _T_19 = neq(sb_state, UInt<4>("h00")) @[dbg.scala 102:79] + node _T_20 = and(_T_19, io.dmi_reg_en) @[dbg.scala 102:102] + node _T_21 = eq(io.dmi_reg_addr, UInt<6>("h039")) @[dbg.scala 103:23] + node _T_22 = eq(io.dmi_reg_addr, UInt<6>("h03c")) @[dbg.scala 103:55] + node _T_23 = or(_T_21, _T_22) @[dbg.scala 103:36] + node _T_24 = eq(io.dmi_reg_addr, UInt<6>("h03d")) @[dbg.scala 103:87] + node _T_25 = or(_T_23, _T_24) @[dbg.scala 103:68] + node _T_26 = and(_T_20, _T_25) @[dbg.scala 102:118] + node sbcs_sbbusyerror_wren = or(_T_18, _T_26) @[dbg.scala 102:66] + node _T_27 = bits(io.dmi_reg_wdata, 22, 22) @[dbg.scala 105:61] + node _T_28 = and(sbcs_wren, _T_27) @[dbg.scala 105:43] + node sbcs_sbbusyerror_din = not(_T_28) @[dbg.scala 105:31] + node _T_29 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 106:53] + reg temp_sbcs_22 : UInt, rvclkhdr_1.io.l1clk with : (reset => (_T_29, UInt<1>("h00"))) @[Reg.scala 27:20] + when sbcs_sbbusyerror_wren : @[Reg.scala 28:19] + temp_sbcs_22 <= sbcs_sbbusyerror_din @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_30 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 110:53] + reg temp_sbcs_21 : UInt, rvclkhdr_1.io.l1clk with : (reset => (_T_30, UInt<1>("h00"))) @[Reg.scala 27:20] + when sbcs_sbbusy_wren : @[Reg.scala 28:19] + temp_sbcs_21 <= sbcs_sbbusy_din @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_31 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 114:53] + node _T_32 = bits(io.dmi_reg_wdata, 20, 20) @[dbg.scala 115:31] + reg temp_sbcs_20 : UInt, rvclkhdr_1.io.l1clk with : (reset => (_T_31, UInt<1>("h00"))) @[Reg.scala 27:20] + when sbcs_wren : @[Reg.scala 28:19] + temp_sbcs_20 <= _T_32 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_33 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 118:56] + node _T_34 = bits(io.dmi_reg_wdata, 19, 15) @[dbg.scala 119:31] + reg temp_sbcs_19_15 : UInt, rvclkhdr_1.io.l1clk with : (reset => (_T_33, UInt<1>("h00"))) @[Reg.scala 27:20] + when sbcs_wren : @[Reg.scala 28:19] + temp_sbcs_19_15 <= _T_34 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_35 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 122:56] + node _T_36 = bits(sbcs_sberror_din, 2, 0) @[dbg.scala 123:31] + reg temp_sbcs_14_12 : UInt, rvclkhdr_1.io.l1clk with : (reset => (_T_35, UInt<1>("h00"))) @[Reg.scala 27:20] + when sbcs_sberror_wren : @[Reg.scala 28:19] + temp_sbcs_14_12 <= _T_36 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_37 = cat(UInt<7>("h020"), UInt<5>("h0f")) @[Cat.scala 29:58] + node _T_38 = cat(temp_sbcs_19_15, temp_sbcs_14_12) @[Cat.scala 29:58] + node _T_39 = cat(_T_38, _T_37) @[Cat.scala 29:58] + node _T_40 = cat(temp_sbcs_21, temp_sbcs_20) @[Cat.scala 29:58] + node _T_41 = cat(UInt<3>("h01"), UInt<6>("h00")) @[Cat.scala 29:58] + node _T_42 = cat(_T_41, temp_sbcs_22) @[Cat.scala 29:58] + node _T_43 = cat(_T_42, _T_40) @[Cat.scala 29:58] + node _T_44 = cat(_T_43, _T_39) @[Cat.scala 29:58] + sbcs_reg <= _T_44 @[dbg.scala 125:12] + node _T_45 = bits(sbcs_reg, 19, 17) @[dbg.scala 127:33] + node _T_46 = eq(_T_45, UInt<1>("h01")) @[dbg.scala 127:42] + node _T_47 = bits(sbaddress0_reg, 0, 0) @[dbg.scala 127:72] + node _T_48 = and(_T_46, _T_47) @[dbg.scala 127:56] + node _T_49 = bits(sbcs_reg, 19, 17) @[dbg.scala 128:14] + node _T_50 = eq(_T_49, UInt<2>("h02")) @[dbg.scala 128:23] + node _T_51 = bits(sbaddress0_reg, 1, 0) @[dbg.scala 128:53] + node _T_52 = orr(_T_51) @[dbg.scala 128:60] + node _T_53 = and(_T_50, _T_52) @[dbg.scala 128:37] + node _T_54 = or(_T_48, _T_53) @[dbg.scala 127:76] + node _T_55 = bits(sbcs_reg, 19, 17) @[dbg.scala 129:14] + node _T_56 = eq(_T_55, UInt<2>("h03")) @[dbg.scala 129:23] + node _T_57 = bits(sbaddress0_reg, 2, 0) @[dbg.scala 129:53] + node _T_58 = orr(_T_57) @[dbg.scala 129:60] + node _T_59 = and(_T_56, _T_58) @[dbg.scala 129:37] + node sbcs_unaligned = or(_T_54, _T_59) @[dbg.scala 128:64] + node sbcs_illegal_size = bits(sbcs_reg, 19, 19) @[dbg.scala 131:35] + node _T_60 = bits(sbcs_reg, 19, 17) @[dbg.scala 132:42] + node _T_61 = eq(_T_60, UInt<1>("h00")) @[dbg.scala 132:51] + node _T_62 = bits(_T_61, 0, 0) @[Bitwise.scala 72:15] + node _T_63 = mux(_T_62, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_64 = and(_T_63, UInt<1>("h01")) @[dbg.scala 132:64] + node _T_65 = bits(sbcs_reg, 19, 17) @[dbg.scala 132:95] + node _T_66 = eq(_T_65, UInt<1>("h01")) @[dbg.scala 132:104] + node _T_67 = bits(_T_66, 0, 0) @[Bitwise.scala 72:15] + node _T_68 = mux(_T_67, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_69 = and(_T_68, UInt<2>("h02")) @[dbg.scala 132:117] + node _T_70 = or(_T_64, _T_69) @[dbg.scala 132:76] + node _T_71 = bits(sbcs_reg, 19, 17) @[dbg.scala 133:22] + node _T_72 = eq(_T_71, UInt<2>("h02")) @[dbg.scala 133:31] + node _T_73 = bits(_T_72, 0, 0) @[Bitwise.scala 72:15] + node _T_74 = mux(_T_73, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_75 = and(_T_74, UInt<3>("h04")) @[dbg.scala 133:44] + node _T_76 = or(_T_70, _T_75) @[dbg.scala 132:129] + node _T_77 = bits(sbcs_reg, 19, 17) @[dbg.scala 133:75] + node _T_78 = eq(_T_77, UInt<2>("h03")) @[dbg.scala 133:84] + node _T_79 = bits(_T_78, 0, 0) @[Bitwise.scala 72:15] + node _T_80 = mux(_T_79, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_81 = and(_T_80, UInt<4>("h08")) @[dbg.scala 133:97] + node sbaddress0_incr = or(_T_76, _T_81) @[dbg.scala 133:56] + node _T_82 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 135:41] + node _T_83 = eq(io.dmi_reg_addr, UInt<6>("h03c")) @[dbg.scala 135:79] + node sbdata0_reg_wren0 = and(_T_82, _T_83) @[dbg.scala 135:60] + node _T_84 = eq(sb_state, UInt<4>("h07")) @[dbg.scala 136:37] + node _T_85 = and(_T_84, sb_state_en) @[dbg.scala 136:60] + node _T_86 = eq(sbcs_sberror_wren, UInt<1>("h00")) @[dbg.scala 136:76] + node sbdata0_reg_wren1 = and(_T_85, _T_86) @[dbg.scala 136:74] + node sbdata0_reg_wren = or(sbdata0_reg_wren0, sbdata0_reg_wren1) @[dbg.scala 137:44] + node _T_87 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 138:41] + node _T_88 = eq(io.dmi_reg_addr, UInt<6>("h03d")) @[dbg.scala 138:79] + node sbdata1_reg_wren0 = and(_T_87, _T_88) @[dbg.scala 138:60] + node _T_89 = eq(sb_state, UInt<4>("h07")) @[dbg.scala 139:37] + node _T_90 = and(_T_89, sb_state_en) @[dbg.scala 139:60] + node _T_91 = eq(sbcs_sberror_wren, UInt<1>("h00")) @[dbg.scala 139:76] + node sbdata1_reg_wren1 = and(_T_90, _T_91) @[dbg.scala 139:74] + node sbdata1_reg_wren = or(sbdata1_reg_wren0, sbdata1_reg_wren1) @[dbg.scala 140:44] + node _T_92 = bits(sbdata0_reg_wren0, 0, 0) @[Bitwise.scala 72:15] + node _T_93 = mux(_T_92, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_94 = and(_T_93, io.dmi_reg_wdata) @[dbg.scala 141:49] + node _T_95 = bits(sbdata0_reg_wren1, 0, 0) @[Bitwise.scala 72:15] + node _T_96 = mux(_T_95, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_97 = bits(sb_bus_rdata, 31, 0) @[dbg.scala 142:47] + node _T_98 = and(_T_96, _T_97) @[dbg.scala 142:33] + node sbdata0_din = or(_T_94, _T_98) @[dbg.scala 141:68] + node _T_99 = bits(sbdata1_reg_wren0, 0, 0) @[Bitwise.scala 72:15] + node _T_100 = mux(_T_99, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_101 = and(_T_100, io.dmi_reg_wdata) @[dbg.scala 144:49] + node _T_102 = bits(sbdata1_reg_wren1, 0, 0) @[Bitwise.scala 72:15] + node _T_103 = mux(_T_102, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_104 = bits(sb_bus_rdata, 63, 32) @[dbg.scala 145:47] + node _T_105 = and(_T_103, _T_104) @[dbg.scala 145:33] + node sbdata1_din = or(_T_101, _T_105) @[dbg.scala 144:68] + node _T_106 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 147:31] + inst rvclkhdr_2 of rvclkhdr_2 @[el2_lib.scala 508:23] + rvclkhdr_2.clock <= clock + rvclkhdr_2.reset <= _T_106 + rvclkhdr_2.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_2.io.en <= sbdata0_reg_wren @[el2_lib.scala 511:17] + rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg sbdata0_reg : UInt, rvclkhdr_2.io.l1clk with : (reset => (_T_106, UInt<1>("h00"))) @[el2_lib.scala 514:16] + sbdata0_reg <= sbdata0_din @[el2_lib.scala 514:16] + node _T_107 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 151:31] + inst rvclkhdr_3 of rvclkhdr_3 @[el2_lib.scala 508:23] + rvclkhdr_3.clock <= clock + rvclkhdr_3.reset <= _T_107 + rvclkhdr_3.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_3.io.en <= sbdata1_reg_wren @[el2_lib.scala 511:17] + rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg sbdata1_reg : UInt, rvclkhdr_3.io.l1clk with : (reset => (_T_107, UInt<1>("h00"))) @[el2_lib.scala 514:16] + sbdata1_reg <= sbdata1_din @[el2_lib.scala 514:16] + node _T_108 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 155:44] + node _T_109 = eq(io.dmi_reg_addr, UInt<6>("h039")) @[dbg.scala 155:82] + node sbaddress0_reg_wren0 = and(_T_108, _T_109) @[dbg.scala 155:63] + node sbaddress0_reg_wren = or(sbaddress0_reg_wren0, sbaddress0_reg_wren1) @[dbg.scala 156:50] + node _T_110 = bits(sbaddress0_reg_wren0, 0, 0) @[Bitwise.scala 72:15] + node _T_111 = mux(_T_110, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_112 = and(_T_111, io.dmi_reg_wdata) @[dbg.scala 157:59] + node _T_113 = bits(sbaddress0_reg_wren1, 0, 0) @[Bitwise.scala 72:15] + node _T_114 = mux(_T_113, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_115 = cat(UInt<28>("h00"), sbaddress0_incr) @[Cat.scala 29:58] + node _T_116 = add(sbaddress0_reg, _T_115) @[dbg.scala 158:54] + node _T_117 = tail(_T_116, 1) @[dbg.scala 158:54] + node _T_118 = and(_T_114, _T_117) @[dbg.scala 158:36] + node sbaddress0_reg_din = or(_T_112, _T_118) @[dbg.scala 157:78] + node _T_119 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 159:31] + inst rvclkhdr_4 of rvclkhdr_4 @[el2_lib.scala 508:23] + rvclkhdr_4.clock <= clock + rvclkhdr_4.reset <= _T_119 + rvclkhdr_4.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_4.io.en <= sbaddress0_reg_wren @[el2_lib.scala 511:17] + rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_120 : UInt, rvclkhdr_4.io.l1clk with : (reset => (_T_119, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_120 <= sbaddress0_reg_din @[el2_lib.scala 514:16] + sbaddress0_reg <= _T_120 @[dbg.scala 159:18] + node _T_121 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 163:43] + node _T_122 = eq(io.dmi_reg_addr, UInt<6>("h039")) @[dbg.scala 163:81] + node _T_123 = and(_T_121, _T_122) @[dbg.scala 163:62] + node _T_124 = bits(sbcs_reg, 20, 20) @[dbg.scala 163:104] + node sbreadonaddr_access = and(_T_123, _T_124) @[dbg.scala 163:94] + node _T_125 = eq(io.dmi_reg_wr_en, UInt<1>("h00")) @[dbg.scala 164:45] + node _T_126 = and(io.dmi_reg_en, _T_125) @[dbg.scala 164:43] + node _T_127 = eq(io.dmi_reg_addr, UInt<6>("h03c")) @[dbg.scala 164:82] + node _T_128 = and(_T_126, _T_127) @[dbg.scala 164:63] + node _T_129 = bits(sbcs_reg, 15, 15) @[dbg.scala 164:105] + node sbreadondata_access = and(_T_128, _T_129) @[dbg.scala 164:95] + node _T_130 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 165:40] + node _T_131 = eq(io.dmi_reg_addr, UInt<6>("h03c")) @[dbg.scala 165:78] + node sbdata0wr_access = and(_T_130, _T_131) @[dbg.scala 165:59] + node _T_132 = eq(io.dmi_reg_addr, UInt<5>("h010")) @[dbg.scala 166:41] + node _T_133 = and(_T_132, io.dmi_reg_en) @[dbg.scala 166:54] + node dmcontrol_wren = and(_T_133, io.dmi_reg_wr_en) @[dbg.scala 166:70] + node _T_134 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 167:49] + node _T_135 = bits(io.dmi_reg_wdata, 31, 30) @[dbg.scala 169:27] + node _T_136 = bits(io.dmi_reg_wdata, 28, 28) @[dbg.scala 169:53] + node _T_137 = bits(io.dmi_reg_wdata, 1, 1) @[dbg.scala 169:75] + node _T_138 = cat(_T_135, _T_136) @[Cat.scala 29:58] + node _T_139 = cat(_T_138, _T_137) @[Cat.scala 29:58] + reg dm_temp : UInt, rvclkhdr.io.l1clk with : (reset => (_T_134, UInt<1>("h00"))) @[Reg.scala 27:20] + when dmcontrol_wren : @[Reg.scala 28:19] + dm_temp <= _T_139 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_140 = bits(io.dmi_reg_wdata, 0, 0) @[dbg.scala 174:31] + reg dm_temp_0 : UInt, rvclkhdr.io.l1clk with : (reset => (io.dbg_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20] + when dmcontrol_wren : @[Reg.scala 28:19] + dm_temp_0 <= _T_140 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_141 = bits(dm_temp, 3, 2) @[dbg.scala 177:25] + node _T_142 = bits(dm_temp, 1, 1) @[dbg.scala 177:45] + node _T_143 = bits(dm_temp, 0, 0) @[dbg.scala 177:68] + node _T_144 = cat(UInt<26>("h00"), _T_143) @[Cat.scala 29:58] + node _T_145 = cat(_T_144, dm_temp_0) @[Cat.scala 29:58] + node _T_146 = cat(_T_141, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_147 = cat(_T_146, _T_142) @[Cat.scala 29:58] + node temp = cat(_T_147, _T_145) @[Cat.scala 29:58] + dmcontrol_reg <= temp @[dbg.scala 178:17] + node _T_148 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 180:58] + reg dmcontrol_wren_Q : UInt<1>, rvclkhdr.io.l1clk with : (reset => (_T_148, UInt<1>("h00"))) @[dbg.scala 181:12] + dmcontrol_wren_Q <= dmcontrol_wren @[dbg.scala 181:12] + node _T_149 = bits(dmstatus_havereset, 0, 0) @[Bitwise.scala 72:15] + node _T_150 = mux(_T_149, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_151 = bits(dmstatus_resumeack, 0, 0) @[Bitwise.scala 72:15] + node _T_152 = mux(_T_151, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_153 = bits(dmstatus_unavail, 0, 0) @[Bitwise.scala 72:15] + node _T_154 = mux(_T_153, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_155 = bits(dmstatus_running, 0, 0) @[Bitwise.scala 72:15] + node _T_156 = mux(_T_155, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_157 = bits(dmstatus_halted, 0, 0) @[Bitwise.scala 72:15] + node _T_158 = mux(_T_157, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_159 = cat(UInt<3>("h00"), UInt<4>("h02")) @[Cat.scala 29:58] + node _T_160 = cat(_T_156, _T_158) @[Cat.scala 29:58] + node _T_161 = cat(_T_160, UInt<1>("h01")) @[Cat.scala 29:58] + node _T_162 = cat(_T_161, _T_159) @[Cat.scala 29:58] + node _T_163 = cat(UInt<2>("h00"), _T_154) @[Cat.scala 29:58] + node _T_164 = cat(UInt<12>("h00"), _T_150) @[Cat.scala 29:58] + node _T_165 = cat(_T_164, _T_152) @[Cat.scala 29:58] + node _T_166 = cat(_T_165, _T_163) @[Cat.scala 29:58] + node _T_167 = cat(_T_166, _T_162) @[Cat.scala 29:58] + dmstatus_reg <= _T_167 @[dbg.scala 184:16] + node _T_168 = eq(dbg_state, UInt<3>("h06")) @[dbg.scala 186:44] + node _T_169 = and(_T_168, io.dec_tlu_resume_ack) @[dbg.scala 186:66] + node _T_170 = bits(dmcontrol_reg, 30, 30) @[dbg.scala 186:127] + node _T_171 = eq(_T_170, UInt<1>("h00")) @[dbg.scala 186:113] + node _T_172 = and(dmstatus_resumeack, _T_171) @[dbg.scala 186:111] + node dmstatus_resumeack_wren = or(_T_169, _T_172) @[dbg.scala 186:90] + node _T_173 = eq(dbg_state, UInt<3>("h06")) @[dbg.scala 187:43] + node dmstatus_resumeack_din = and(_T_173, io.dec_tlu_resume_ack) @[dbg.scala 187:65] + node _T_174 = eq(io.dmi_reg_addr, UInt<5>("h010")) @[dbg.scala 188:50] + node _T_175 = bits(io.dmi_reg_wdata, 1, 1) @[dbg.scala 188:81] + node _T_176 = and(_T_174, _T_175) @[dbg.scala 188:63] + node _T_177 = and(_T_176, io.dmi_reg_en) @[dbg.scala 188:85] + node dmstatus_havereset_wren = and(_T_177, io.dmi_reg_wr_en) @[dbg.scala 188:101] + node _T_178 = eq(io.dmi_reg_addr, UInt<5>("h010")) @[dbg.scala 189:49] + node _T_179 = bits(io.dmi_reg_wdata, 28, 28) @[dbg.scala 189:80] + node _T_180 = and(_T_178, _T_179) @[dbg.scala 189:62] + node _T_181 = and(_T_180, io.dmi_reg_en) @[dbg.scala 189:85] + node dmstatus_havereset_rst = and(_T_181, io.dmi_reg_wr_en) @[dbg.scala 189:101] + node temp_rst = asUInt(reset) @[dbg.scala 190:30] + node _T_182 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 191:37] + node _T_183 = eq(temp_rst, UInt<1>("h00")) @[dbg.scala 191:43] + node _T_184 = or(_T_182, _T_183) @[dbg.scala 191:41] + node _T_185 = bits(_T_184, 0, 0) @[dbg.scala 191:62] + dmstatus_unavail <= _T_185 @[dbg.scala 191:20] + node _T_186 = or(dmstatus_unavail, dmstatus_halted) @[dbg.scala 192:42] + node _T_187 = not(_T_186) @[dbg.scala 192:23] + dmstatus_running <= _T_187 @[dbg.scala 192:20] + node _T_188 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 193:57] + reg _T_189 : UInt, rvclkhdr.io.l1clk with : (reset => (_T_188, UInt<1>("h00"))) @[Reg.scala 27:20] + when dmstatus_resumeack_wren : @[Reg.scala 28:19] + _T_189 <= dmstatus_resumeack_din @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + dmstatus_resumeack <= _T_189 @[dbg.scala 193:22] + node _T_190 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 197:54] + node _T_191 = eq(io.dec_tlu_mpc_halted_only, UInt<1>("h00")) @[dbg.scala 198:37] + node _T_192 = and(io.dec_tlu_dbg_halted, _T_191) @[dbg.scala 198:35] + reg _T_193 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (_T_190, UInt<1>("h00"))) @[dbg.scala 198:12] + _T_193 <= _T_192 @[dbg.scala 198:12] + dmstatus_halted <= _T_193 @[dbg.scala 197:19] + node _T_194 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 201:57] + node _T_195 = not(dmstatus_havereset_rst) @[dbg.scala 202:15] + reg _T_196 : UInt, rvclkhdr.io.l1clk with : (reset => (_T_194, UInt<1>("h00"))) @[Reg.scala 27:20] + when dmstatus_havereset_wren : @[Reg.scala 28:19] + _T_196 <= _T_195 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + dmstatus_havereset <= _T_196 @[dbg.scala 201:22] + node haltsum0_reg = cat(UInt<31>("h00"), dmstatus_halted) @[Cat.scala 29:58] + wire abstractcs_reg : UInt<32> + abstractcs_reg <= UInt<32>("h02") + node _T_197 = bits(abstractcs_reg, 12, 12) @[dbg.scala 208:45] + node _T_198 = and(_T_197, io.dmi_reg_en) @[dbg.scala 208:50] + node _T_199 = eq(io.dmi_reg_addr, UInt<5>("h016")) @[dbg.scala 208:106] + node _T_200 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[dbg.scala 208:138] + node _T_201 = or(_T_199, _T_200) @[dbg.scala 208:119] + node _T_202 = and(io.dmi_reg_wr_en, _T_201) @[dbg.scala 208:86] + node _T_203 = eq(io.dmi_reg_addr, UInt<3>("h04")) @[dbg.scala 208:171] + node _T_204 = or(_T_202, _T_203) @[dbg.scala 208:152] + node abstractcs_error_sel0 = and(_T_198, _T_204) @[dbg.scala 208:66] + node _T_205 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 209:45] + node _T_206 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[dbg.scala 209:83] + node _T_207 = and(_T_205, _T_206) @[dbg.scala 209:64] + node _T_208 = bits(io.dmi_reg_wdata, 31, 24) @[dbg.scala 209:117] + node _T_209 = eq(_T_208, UInt<1>("h00")) @[dbg.scala 209:126] + node _T_210 = bits(io.dmi_reg_wdata, 31, 24) @[dbg.scala 209:154] + node _T_211 = eq(_T_210, UInt<2>("h02")) @[dbg.scala 209:163] + node _T_212 = or(_T_209, _T_211) @[dbg.scala 209:135] + node _T_213 = eq(_T_212, UInt<1>("h00")) @[dbg.scala 209:98] + node abstractcs_error_sel1 = and(_T_207, _T_213) @[dbg.scala 209:96] + node abstractcs_error_sel2 = and(io.core_dbg_cmd_done, io.core_dbg_cmd_fail) @[dbg.scala 210:52] + node _T_214 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 211:45] + node _T_215 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[dbg.scala 211:83] + node _T_216 = and(_T_214, _T_215) @[dbg.scala 211:64] + node _T_217 = bits(dmstatus_reg, 9, 9) @[dbg.scala 211:111] + node _T_218 = eq(_T_217, UInt<1>("h00")) @[dbg.scala 211:98] + node abstractcs_error_sel3 = and(_T_216, _T_218) @[dbg.scala 211:96] + node _T_219 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[dbg.scala 212:48] + node _T_220 = and(_T_219, io.dmi_reg_en) @[dbg.scala 212:61] + node _T_221 = and(_T_220, io.dmi_reg_wr_en) @[dbg.scala 212:77] + node _T_222 = bits(io.dmi_reg_wdata, 22, 20) @[dbg.scala 213:23] + node _T_223 = neq(_T_222, UInt<2>("h02")) @[dbg.scala 213:32] + node _T_224 = bits(io.dmi_reg_wdata, 31, 24) @[dbg.scala 213:66] + node _T_225 = eq(_T_224, UInt<2>("h02")) @[dbg.scala 213:75] + node _T_226 = bits(data1_reg, 1, 0) @[dbg.scala 213:99] + node _T_227 = orr(_T_226) @[dbg.scala 213:106] + node _T_228 = and(_T_225, _T_227) @[dbg.scala 213:87] + node _T_229 = or(_T_223, _T_228) @[dbg.scala 213:46] + node abstractcs_error_sel4 = and(_T_221, _T_229) @[dbg.scala 212:96] + node _T_230 = eq(io.dmi_reg_addr, UInt<5>("h016")) @[dbg.scala 215:48] + node _T_231 = and(_T_230, io.dmi_reg_en) @[dbg.scala 215:61] + node abstractcs_error_sel5 = and(_T_231, io.dmi_reg_wr_en) @[dbg.scala 215:77] + node _T_232 = or(abstractcs_error_sel0, abstractcs_error_sel1) @[dbg.scala 216:54] + node _T_233 = or(_T_232, abstractcs_error_sel2) @[dbg.scala 216:78] + node _T_234 = or(_T_233, abstractcs_error_sel3) @[dbg.scala 216:102] + node _T_235 = or(_T_234, abstractcs_error_sel4) @[dbg.scala 216:126] + node abstractcs_error_selor = or(_T_235, abstractcs_error_sel5) @[dbg.scala 216:150] + node _T_236 = bits(abstractcs_error_sel0, 0, 0) @[Bitwise.scala 72:15] + node _T_237 = mux(_T_236, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_238 = and(_T_237, UInt<1>("h01")) @[dbg.scala 217:62] + node _T_239 = bits(abstractcs_error_sel1, 0, 0) @[Bitwise.scala 72:15] + node _T_240 = mux(_T_239, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_241 = and(_T_240, UInt<2>("h02")) @[dbg.scala 218:37] + node _T_242 = or(_T_238, _T_241) @[dbg.scala 217:74] + node _T_243 = bits(abstractcs_error_sel2, 0, 0) @[Bitwise.scala 72:15] + node _T_244 = mux(_T_243, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_245 = and(_T_244, UInt<2>("h03")) @[dbg.scala 219:37] + node _T_246 = or(_T_242, _T_245) @[dbg.scala 218:49] + node _T_247 = bits(abstractcs_error_sel3, 0, 0) @[Bitwise.scala 72:15] + node _T_248 = mux(_T_247, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_249 = and(_T_248, UInt<3>("h04")) @[dbg.scala 220:37] + node _T_250 = or(_T_246, _T_249) @[dbg.scala 219:49] + node _T_251 = bits(abstractcs_error_sel4, 0, 0) @[Bitwise.scala 72:15] + node _T_252 = mux(_T_251, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_253 = and(_T_252, UInt<3>("h07")) @[dbg.scala 221:37] + node _T_254 = or(_T_250, _T_253) @[dbg.scala 220:49] + node _T_255 = bits(abstractcs_error_sel5, 0, 0) @[Bitwise.scala 72:15] + node _T_256 = mux(_T_255, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_257 = bits(io.dmi_reg_wdata, 10, 8) @[dbg.scala 222:57] + node _T_258 = not(_T_257) @[dbg.scala 222:40] + node _T_259 = and(_T_256, _T_258) @[dbg.scala 222:37] + node _T_260 = bits(abstractcs_reg, 10, 8) @[dbg.scala 222:91] + node _T_261 = and(_T_259, _T_260) @[dbg.scala 222:75] + node _T_262 = or(_T_254, _T_261) @[dbg.scala 221:49] + node _T_263 = not(abstractcs_error_selor) @[dbg.scala 223:15] + node _T_264 = bits(_T_263, 0, 0) @[Bitwise.scala 72:15] + node _T_265 = mux(_T_264, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_266 = bits(abstractcs_reg, 10, 8) @[dbg.scala 223:66] + node _T_267 = and(_T_265, _T_266) @[dbg.scala 223:50] + node abstractcs_error_din = or(_T_262, _T_267) @[dbg.scala 222:100] + node _T_268 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 225:53] + reg abs_temp_12 : UInt, rvclkhdr.io.l1clk with : (reset => (_T_268, UInt<1>("h00"))) @[Reg.scala 27:20] + when abstractcs_busy_wren : @[Reg.scala 28:19] + abs_temp_12 <= abstractcs_busy_din @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_269 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 229:55] + node _T_270 = bits(abstractcs_error_din, 2, 0) @[dbg.scala 230:33] + reg abs_temp_10_8 : UInt, rvclkhdr.io.l1clk with : (reset => (_T_269, UInt<1>("h00"))) @[dbg.scala 230:12] + abs_temp_10_8 <= _T_270 @[dbg.scala 230:12] + node _T_271 = cat(abs_temp_10_8, UInt<8>("h02")) @[Cat.scala 29:58] + node _T_272 = cat(UInt<19>("h00"), abs_temp_12) @[Cat.scala 29:58] + node _T_273 = cat(_T_272, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_274 = cat(_T_273, _T_271) @[Cat.scala 29:58] + abstractcs_reg <= _T_274 @[dbg.scala 233:18] + node _T_275 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[dbg.scala 235:39] + node _T_276 = and(_T_275, io.dmi_reg_en) @[dbg.scala 235:52] + node _T_277 = and(_T_276, io.dmi_reg_wr_en) @[dbg.scala 235:68] + node _T_278 = eq(dbg_state, UInt<3>("h02")) @[dbg.scala 235:100] + node command_wren = and(_T_277, _T_278) @[dbg.scala 235:87] + node _T_279 = bits(io.dmi_reg_wdata, 31, 24) @[dbg.scala 236:41] + node _T_280 = bits(io.dmi_reg_wdata, 22, 20) @[dbg.scala 236:77] + node _T_281 = bits(io.dmi_reg_wdata, 16, 0) @[dbg.scala 236:113] + node _T_282 = cat(UInt<3>("h00"), _T_281) @[Cat.scala 29:58] + node _T_283 = cat(_T_279, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_284 = cat(_T_283, _T_280) @[Cat.scala 29:58] + node command_din = cat(_T_284, _T_282) @[Cat.scala 29:58] + node _T_285 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 237:31] + reg command_reg : UInt, clock with : (reset => (_T_285, UInt<1>("h00"))) @[Reg.scala 27:20] + when command_wren : @[Reg.scala 28:19] + command_reg <= command_din @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_286 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 241:39] + node _T_287 = eq(io.dmi_reg_addr, UInt<3>("h04")) @[dbg.scala 241:77] + node _T_288 = and(_T_286, _T_287) @[dbg.scala 241:58] + node _T_289 = eq(dbg_state, UInt<3>("h02")) @[dbg.scala 241:102] + node data0_reg_wren0 = and(_T_288, _T_289) @[dbg.scala 241:89] + node _T_290 = eq(dbg_state, UInt<3>("h04")) @[dbg.scala 242:59] + node _T_291 = and(io.core_dbg_cmd_done, _T_290) @[dbg.scala 242:46] + node _T_292 = bits(command_reg, 16, 16) @[dbg.scala 242:95] + node _T_293 = eq(_T_292, UInt<1>("h00")) @[dbg.scala 242:83] + node data0_reg_wren1 = and(_T_291, _T_293) @[dbg.scala 242:81] + node data0_reg_wren = or(data0_reg_wren0, data0_reg_wren1) @[dbg.scala 244:40] + node _T_294 = bits(data0_reg_wren0, 0, 0) @[Bitwise.scala 72:15] + node _T_295 = mux(_T_294, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_296 = and(_T_295, io.dmi_reg_wdata) @[dbg.scala 245:45] + node _T_297 = bits(data0_reg_wren1, 0, 0) @[Bitwise.scala 72:15] + node _T_298 = mux(_T_297, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_299 = and(_T_298, io.core_dbg_rddata) @[dbg.scala 245:92] + node data0_din = or(_T_296, _T_299) @[dbg.scala 245:64] + node _T_300 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 246:29] + reg data0_reg : UInt, clock with : (reset => (_T_300, UInt<1>("h00"))) @[Reg.scala 27:20] + when data0_reg_wren : @[Reg.scala 28:19] + data0_reg <= data0_din @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_301 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 250:39] + node _T_302 = eq(io.dmi_reg_addr, UInt<3>("h05")) @[dbg.scala 250:77] + node _T_303 = and(_T_301, _T_302) @[dbg.scala 250:58] + node _T_304 = eq(dbg_state, UInt<3>("h02")) @[dbg.scala 250:102] + node data1_reg_wren = and(_T_303, _T_304) @[dbg.scala 250:89] + node _T_305 = bits(data1_reg_wren, 0, 0) @[Bitwise.scala 72:15] + node _T_306 = mux(_T_305, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node data1_din = and(_T_306, io.dmi_reg_wdata) @[dbg.scala 251:44] + node _T_307 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 252:26] + inst rvclkhdr_5 of rvclkhdr_5 @[el2_lib.scala 508:23] + rvclkhdr_5.clock <= clock + rvclkhdr_5.reset <= _T_307 + rvclkhdr_5.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_5.io.en <= data1_reg_wren @[el2_lib.scala 511:17] + rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_308 : UInt, rvclkhdr_5.io.l1clk with : (reset => (_T_307, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_308 <= data1_din @[el2_lib.scala 514:16] + data1_reg <= _T_308 @[dbg.scala 252:13] + wire dbg_nxtstate : UInt<3> + dbg_nxtstate <= UInt<3>("h00") + dbg_nxtstate <= UInt<3>("h00") @[dbg.scala 257:16] + dbg_state_en <= UInt<1>("h00") @[dbg.scala 258:16] + abstractcs_busy_wren <= UInt<1>("h00") @[dbg.scala 259:24] + abstractcs_busy_din <= UInt<1>("h00") @[dbg.scala 260:23] + io.dbg_halt_req <= UInt<1>("h00") @[dbg.scala 261:19] + io.dbg_resume_req <= UInt<1>("h00") @[dbg.scala 262:21] + node _T_309 = eq(UInt<3>("h00"), dbg_state) @[Conditional.scala 37:30] + when _T_309 : @[Conditional.scala 40:58] + node _T_310 = bits(dmstatus_reg, 9, 9) @[dbg.scala 265:39] + node _T_311 = or(_T_310, io.dec_tlu_mpc_halted_only) @[dbg.scala 265:43] + node _T_312 = mux(_T_311, UInt<3>("h02"), UInt<3>("h01")) @[dbg.scala 265:26] + dbg_nxtstate <= _T_312 @[dbg.scala 265:20] + node _T_313 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 266:38] + node _T_314 = eq(io.dec_tlu_debug_mode, UInt<1>("h00")) @[dbg.scala 266:45] + node _T_315 = and(_T_313, _T_314) @[dbg.scala 266:43] + node _T_316 = bits(dmstatus_reg, 9, 9) @[dbg.scala 266:83] + node _T_317 = or(_T_315, _T_316) @[dbg.scala 266:69] + node _T_318 = or(_T_317, io.dec_tlu_mpc_halted_only) @[dbg.scala 266:87] + node _T_319 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 266:133] + node _T_320 = eq(_T_319, UInt<1>("h00")) @[dbg.scala 266:119] + node _T_321 = and(_T_318, _T_320) @[dbg.scala 266:117] + dbg_state_en <= _T_321 @[dbg.scala 266:20] + node _T_322 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 267:40] + node _T_323 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 267:61] + node _T_324 = eq(_T_323, UInt<1>("h00")) @[dbg.scala 267:47] + node _T_325 = and(_T_322, _T_324) @[dbg.scala 267:45] + node _T_326 = bits(_T_325, 0, 0) @[dbg.scala 267:72] + io.dbg_halt_req <= _T_326 @[dbg.scala 267:23] + skip @[Conditional.scala 40:58] + else : @[Conditional.scala 39:67] + node _T_327 = eq(UInt<3>("h01"), dbg_state) @[Conditional.scala 37:30] + when _T_327 : @[Conditional.scala 39:67] + node _T_328 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 270:40] + node _T_329 = mux(_T_328, UInt<3>("h00"), UInt<3>("h02")) @[dbg.scala 270:26] + dbg_nxtstate <= _T_329 @[dbg.scala 270:20] + node _T_330 = bits(dmstatus_reg, 9, 9) @[dbg.scala 271:35] + node _T_331 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 271:54] + node _T_332 = or(_T_330, _T_331) @[dbg.scala 271:39] + dbg_state_en <= _T_332 @[dbg.scala 271:20] + node _T_333 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 272:59] + node _T_334 = and(dmcontrol_wren_Q, _T_333) @[dbg.scala 272:44] + node _T_335 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 272:81] + node _T_336 = not(_T_335) @[dbg.scala 272:67] + node _T_337 = and(_T_334, _T_336) @[dbg.scala 272:64] + node _T_338 = bits(_T_337, 0, 0) @[dbg.scala 272:102] + io.dbg_halt_req <= _T_338 @[dbg.scala 272:23] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_339 = eq(UInt<3>("h02"), dbg_state) @[Conditional.scala 37:30] + when _T_339 : @[Conditional.scala 39:67] + node _T_340 = bits(dmstatus_reg, 9, 9) @[dbg.scala 275:39] + node _T_341 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 275:59] + node _T_342 = eq(_T_341, UInt<1>("h00")) @[dbg.scala 275:45] + node _T_343 = and(_T_340, _T_342) @[dbg.scala 275:43] + node _T_344 = bits(dmcontrol_reg, 30, 30) @[dbg.scala 276:26] + node _T_345 = bits(dmcontrol_reg, 3, 3) @[dbg.scala 276:47] + node _T_346 = eq(_T_345, UInt<1>("h00")) @[dbg.scala 276:33] + node _T_347 = and(_T_344, _T_346) @[dbg.scala 276:31] + node _T_348 = mux(_T_347, UInt<3>("h06"), UInt<3>("h03")) @[dbg.scala 276:12] + node _T_349 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 277:26] + node _T_350 = mux(_T_349, UInt<3>("h01"), UInt<3>("h00")) @[dbg.scala 277:12] + node _T_351 = mux(_T_343, _T_348, _T_350) @[dbg.scala 275:26] + dbg_nxtstate <= _T_351 @[dbg.scala 275:20] + node _T_352 = bits(dmstatus_reg, 9, 9) @[dbg.scala 278:35] + node _T_353 = bits(dmcontrol_reg, 30, 30) @[dbg.scala 278:54] + node _T_354 = and(_T_352, _T_353) @[dbg.scala 278:39] + node _T_355 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 278:75] + node _T_356 = eq(_T_355, UInt<1>("h00")) @[dbg.scala 278:61] + node _T_357 = and(_T_354, _T_356) @[dbg.scala 278:59] + node _T_358 = and(_T_357, dmcontrol_wren_Q) @[dbg.scala 278:80] + node _T_359 = or(_T_358, command_wren) @[dbg.scala 278:99] + node _T_360 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 279:22] + node _T_361 = or(_T_359, _T_360) @[dbg.scala 278:114] + node _T_362 = bits(dmstatus_reg, 9, 9) @[dbg.scala 279:42] + node _T_363 = or(_T_362, io.dec_tlu_mpc_halted_only) @[dbg.scala 279:46] + node _T_364 = eq(_T_363, UInt<1>("h00")) @[dbg.scala 279:28] + node _T_365 = or(_T_361, _T_364) @[dbg.scala 279:26] + dbg_state_en <= _T_365 @[dbg.scala 278:20] + node _T_366 = eq(dbg_nxtstate, UInt<3>("h03")) @[dbg.scala 280:60] + node _T_367 = and(dbg_state_en, _T_366) @[dbg.scala 280:44] + abstractcs_busy_wren <= _T_367 @[dbg.scala 280:28] + abstractcs_busy_din <= UInt<1>("h01") @[dbg.scala 281:27] + node _T_368 = eq(dbg_nxtstate, UInt<3>("h06")) @[dbg.scala 282:58] + node _T_369 = and(dbg_state_en, _T_368) @[dbg.scala 282:42] + node _T_370 = bits(_T_369, 0, 0) @[dbg.scala 282:87] + io.dbg_resume_req <= _T_370 @[dbg.scala 282:25] + node _T_371 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 283:59] + node _T_372 = and(dmcontrol_wren_Q, _T_371) @[dbg.scala 283:44] + node _T_373 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 283:81] + node _T_374 = not(_T_373) @[dbg.scala 283:67] + node _T_375 = and(_T_372, _T_374) @[dbg.scala 283:64] + node _T_376 = bits(_T_375, 0, 0) @[dbg.scala 283:102] + io.dbg_halt_req <= _T_376 @[dbg.scala 283:23] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_377 = eq(UInt<3>("h03"), dbg_state) @[Conditional.scala 37:30] + when _T_377 : @[Conditional.scala 39:67] + node _T_378 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 286:40] + node _T_379 = bits(abstractcs_reg, 10, 8) @[dbg.scala 286:77] + node _T_380 = orr(_T_379) @[dbg.scala 286:85] + node _T_381 = mux(_T_380, UInt<3>("h05"), UInt<3>("h04")) @[dbg.scala 286:62] + node _T_382 = mux(_T_378, UInt<3>("h00"), _T_381) @[dbg.scala 286:26] + dbg_nxtstate <= _T_382 @[dbg.scala 286:20] + node _T_383 = bits(abstractcs_reg, 10, 8) @[dbg.scala 287:71] + node _T_384 = orr(_T_383) @[dbg.scala 287:79] + node _T_385 = or(io.dbg_dec.dbg_ib.dbg_cmd_valid, _T_384) @[dbg.scala 287:55] + node _T_386 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 287:98] + node _T_387 = or(_T_385, _T_386) @[dbg.scala 287:83] + dbg_state_en <= _T_387 @[dbg.scala 287:20] + node _T_388 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 288:59] + node _T_389 = and(dmcontrol_wren_Q, _T_388) @[dbg.scala 288:44] + node _T_390 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 288:81] + node _T_391 = not(_T_390) @[dbg.scala 288:67] + node _T_392 = and(_T_389, _T_391) @[dbg.scala 288:64] + node _T_393 = bits(_T_392, 0, 0) @[dbg.scala 288:102] + io.dbg_halt_req <= _T_393 @[dbg.scala 288:23] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_394 = eq(UInt<3>("h04"), dbg_state) @[Conditional.scala 37:30] + when _T_394 : @[Conditional.scala 39:67] + node _T_395 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 291:40] + node _T_396 = mux(_T_395, UInt<3>("h00"), UInt<3>("h05")) @[dbg.scala 291:26] + dbg_nxtstate <= _T_396 @[dbg.scala 291:20] + node _T_397 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 292:59] + node _T_398 = or(io.core_dbg_cmd_done, _T_397) @[dbg.scala 292:44] + dbg_state_en <= _T_398 @[dbg.scala 292:20] + node _T_399 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 293:59] + node _T_400 = and(dmcontrol_wren_Q, _T_399) @[dbg.scala 293:44] + node _T_401 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 293:81] + node _T_402 = not(_T_401) @[dbg.scala 293:67] + node _T_403 = and(_T_400, _T_402) @[dbg.scala 293:64] + node _T_404 = bits(_T_403, 0, 0) @[dbg.scala 293:102] + io.dbg_halt_req <= _T_404 @[dbg.scala 293:23] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_405 = eq(UInt<3>("h05"), dbg_state) @[Conditional.scala 37:30] + when _T_405 : @[Conditional.scala 39:67] + node _T_406 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 296:40] + node _T_407 = mux(_T_406, UInt<3>("h00"), UInt<3>("h02")) @[dbg.scala 296:26] + dbg_nxtstate <= _T_407 @[dbg.scala 296:20] + dbg_state_en <= UInt<1>("h01") @[dbg.scala 297:20] + abstractcs_busy_wren <= dbg_state_en @[dbg.scala 298:28] + abstractcs_busy_din <= UInt<1>("h00") @[dbg.scala 299:27] + node _T_408 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 300:59] + node _T_409 = and(dmcontrol_wren_Q, _T_408) @[dbg.scala 300:44] + node _T_410 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 300:81] + node _T_411 = not(_T_410) @[dbg.scala 300:67] + node _T_412 = and(_T_409, _T_411) @[dbg.scala 300:64] + node _T_413 = bits(_T_412, 0, 0) @[dbg.scala 300:102] + io.dbg_halt_req <= _T_413 @[dbg.scala 300:23] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_414 = eq(UInt<3>("h06"), dbg_state) @[Conditional.scala 37:30] + when _T_414 : @[Conditional.scala 39:67] + dbg_nxtstate <= UInt<3>("h00") @[dbg.scala 303:20] + node _T_415 = bits(dmstatus_reg, 17, 17) @[dbg.scala 304:35] + node _T_416 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 304:55] + node _T_417 = or(_T_415, _T_416) @[dbg.scala 304:40] + dbg_state_en <= _T_417 @[dbg.scala 304:20] + node _T_418 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 305:59] + node _T_419 = and(dmcontrol_wren_Q, _T_418) @[dbg.scala 305:44] + node _T_420 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 305:81] + node _T_421 = not(_T_420) @[dbg.scala 305:67] + node _T_422 = and(_T_419, _T_421) @[dbg.scala 305:64] + node _T_423 = bits(_T_422, 0, 0) @[dbg.scala 305:102] + io.dbg_halt_req <= _T_423 @[dbg.scala 305:23] + skip @[Conditional.scala 39:67] + node _T_424 = eq(io.dmi_reg_addr, UInt<3>("h04")) @[dbg.scala 308:52] + node _T_425 = bits(_T_424, 0, 0) @[Bitwise.scala 72:15] + node _T_426 = mux(_T_425, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_427 = and(_T_426, data0_reg) @[dbg.scala 308:71] + node _T_428 = eq(io.dmi_reg_addr, UInt<3>("h05")) @[dbg.scala 308:110] + node _T_429 = bits(_T_428, 0, 0) @[Bitwise.scala 72:15] + node _T_430 = mux(_T_429, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_431 = and(_T_430, data1_reg) @[dbg.scala 308:122] + node _T_432 = or(_T_427, _T_431) @[dbg.scala 308:83] + node _T_433 = eq(io.dmi_reg_addr, UInt<5>("h010")) @[dbg.scala 309:30] + node _T_434 = bits(_T_433, 0, 0) @[Bitwise.scala 72:15] + node _T_435 = mux(_T_434, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_436 = and(_T_435, dmcontrol_reg) @[dbg.scala 309:43] + node _T_437 = or(_T_432, _T_436) @[dbg.scala 308:134] + node _T_438 = eq(io.dmi_reg_addr, UInt<5>("h011")) @[dbg.scala 309:86] + node _T_439 = bits(_T_438, 0, 0) @[Bitwise.scala 72:15] + node _T_440 = mux(_T_439, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_441 = and(_T_440, dmstatus_reg) @[dbg.scala 309:99] + node _T_442 = or(_T_437, _T_441) @[dbg.scala 309:59] + node _T_443 = eq(io.dmi_reg_addr, UInt<5>("h016")) @[dbg.scala 310:30] + node _T_444 = bits(_T_443, 0, 0) @[Bitwise.scala 72:15] + node _T_445 = mux(_T_444, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_446 = and(_T_445, abstractcs_reg) @[dbg.scala 310:43] + node _T_447 = or(_T_442, _T_446) @[dbg.scala 309:114] + node _T_448 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[dbg.scala 310:87] + node _T_449 = bits(_T_448, 0, 0) @[Bitwise.scala 72:15] + node _T_450 = mux(_T_449, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_451 = and(_T_450, command_reg) @[dbg.scala 310:100] + node _T_452 = or(_T_447, _T_451) @[dbg.scala 310:60] + node _T_453 = eq(io.dmi_reg_addr, UInt<7>("h040")) @[dbg.scala 311:30] + node _T_454 = bits(_T_453, 0, 0) @[Bitwise.scala 72:15] + node _T_455 = mux(_T_454, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_456 = and(_T_455, haltsum0_reg) @[dbg.scala 311:43] + node _T_457 = or(_T_452, _T_456) @[dbg.scala 310:114] + node _T_458 = eq(io.dmi_reg_addr, UInt<6>("h038")) @[dbg.scala 311:85] + node _T_459 = bits(_T_458, 0, 0) @[Bitwise.scala 72:15] + node _T_460 = mux(_T_459, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_461 = and(_T_460, sbcs_reg) @[dbg.scala 311:98] + node _T_462 = or(_T_457, _T_461) @[dbg.scala 311:58] + node _T_463 = eq(io.dmi_reg_addr, UInt<6>("h039")) @[dbg.scala 312:30] + node _T_464 = bits(_T_463, 0, 0) @[Bitwise.scala 72:15] + node _T_465 = mux(_T_464, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_466 = and(_T_465, sbaddress0_reg) @[dbg.scala 312:43] + node _T_467 = or(_T_462, _T_466) @[dbg.scala 311:109] + node _T_468 = eq(io.dmi_reg_addr, UInt<6>("h03c")) @[dbg.scala 312:87] + node _T_469 = bits(_T_468, 0, 0) @[Bitwise.scala 72:15] + node _T_470 = mux(_T_469, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_471 = and(_T_470, sbdata0_reg) @[dbg.scala 312:100] + node _T_472 = or(_T_467, _T_471) @[dbg.scala 312:60] + node _T_473 = eq(io.dmi_reg_addr, UInt<6>("h03d")) @[dbg.scala 313:30] + node _T_474 = bits(_T_473, 0, 0) @[Bitwise.scala 72:15] + node _T_475 = mux(_T_474, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_476 = and(_T_475, sbdata1_reg) @[dbg.scala 313:43] + node dmi_reg_rdata_din = or(_T_472, _T_476) @[dbg.scala 312:114] + node _T_477 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 315:48] + node _T_478 = and(_T_477, temp_rst) @[dbg.scala 315:62] + reg _T_479 : UInt, rvclkhdr.io.l1clk with : (reset => (_T_478, UInt<1>("h00"))) @[Reg.scala 27:20] + when dbg_state_en : @[Reg.scala 28:19] + _T_479 <= dbg_nxtstate @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + dbg_state <= _T_479 @[dbg.scala 315:13] + node _T_480 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 320:55] + reg _T_481 : UInt, rvclkhdr.io.l1clk with : (reset => (_T_480, UInt<1>("h00"))) @[Reg.scala 27:20] + when io.dmi_reg_en : @[Reg.scala 28:19] + _T_481 <= dmi_reg_rdata_din @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.dmi_reg_rdata <= _T_481 @[dbg.scala 320:20] + node _T_482 = bits(command_reg, 31, 24) @[dbg.scala 324:53] + node _T_483 = eq(_T_482, UInt<2>("h02")) @[dbg.scala 324:62] + node _T_484 = bits(data1_reg, 31, 2) @[dbg.scala 324:88] + node _T_485 = cat(_T_484, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_486 = bits(command_reg, 11, 0) @[dbg.scala 324:133] + node _T_487 = cat(UInt<20>("h00"), _T_486) @[Cat.scala 29:58] + node _T_488 = mux(_T_483, _T_485, _T_487) @[dbg.scala 324:40] + io.dbg_dec.dbg_ib.dbg_cmd_addr <= _T_488 @[dbg.scala 324:34] + node _T_489 = bits(data0_reg, 31, 0) @[dbg.scala 325:50] + io.dbg_dec.dbg_dctl.dbg_cmd_wrdata <= _T_489 @[dbg.scala 325:38] + node _T_490 = eq(dbg_state, UInt<3>("h03")) @[dbg.scala 326:50] + node _T_491 = bits(abstractcs_reg, 10, 8) @[dbg.scala 326:91] + node _T_492 = orr(_T_491) @[dbg.scala 326:99] + node _T_493 = eq(_T_492, UInt<1>("h00")) @[dbg.scala 326:75] + node _T_494 = and(_T_490, _T_493) @[dbg.scala 326:73] + node _T_495 = and(_T_494, io.dbg_dma_io.dma_dbg_ready) @[dbg.scala 326:104] + node _T_496 = bits(_T_495, 0, 0) @[dbg.scala 326:141] + io.dbg_dec.dbg_ib.dbg_cmd_valid <= _T_496 @[dbg.scala 326:35] + node _T_497 = bits(command_reg, 16, 16) @[dbg.scala 327:49] + node _T_498 = bits(_T_497, 0, 0) @[dbg.scala 327:60] + io.dbg_dec.dbg_ib.dbg_cmd_write <= _T_498 @[dbg.scala 327:35] + node _T_499 = bits(command_reg, 31, 24) @[dbg.scala 328:53] + node _T_500 = eq(_T_499, UInt<2>("h02")) @[dbg.scala 328:62] + node _T_501 = bits(command_reg, 15, 12) @[dbg.scala 328:108] + node _T_502 = eq(_T_501, UInt<1>("h00")) @[dbg.scala 328:117] + node _T_503 = cat(UInt<1>("h00"), _T_502) @[Cat.scala 29:58] + node _T_504 = mux(_T_500, UInt<2>("h02"), _T_503) @[dbg.scala 328:40] + io.dbg_dec.dbg_ib.dbg_cmd_type <= _T_504 @[dbg.scala 328:34] + node _T_505 = bits(command_reg, 21, 20) @[dbg.scala 329:33] + io.dbg_cmd_size <= _T_505 @[dbg.scala 329:19] + node _T_506 = eq(dbg_state, UInt<3>("h03")) @[dbg.scala 330:47] + node _T_507 = bits(abstractcs_reg, 10, 8) @[dbg.scala 330:88] + node _T_508 = orr(_T_507) @[dbg.scala 330:96] + node _T_509 = eq(_T_508, UInt<1>("h00")) @[dbg.scala 330:72] + node _T_510 = and(_T_506, _T_509) @[dbg.scala 330:70] + node _T_511 = eq(dbg_state, UInt<3>("h04")) @[dbg.scala 330:114] + node _T_512 = or(_T_510, _T_511) @[dbg.scala 330:101] + node _T_513 = bits(_T_512, 0, 0) @[dbg.scala 330:143] + io.dbg_dma_io.dbg_dma_bubble <= _T_513 @[dbg.scala 330:32] + wire sb_nxtstate : UInt<4> + sb_nxtstate <= UInt<4>("h00") + sb_nxtstate <= UInt<4>("h00") @[dbg.scala 333:15] + sbcs_sbbusy_wren <= UInt<1>("h00") @[dbg.scala 335:20] + sbcs_sbbusy_din <= UInt<1>("h00") @[dbg.scala 336:19] + sbcs_sberror_wren <= UInt<1>("h00") @[dbg.scala 337:21] + sbcs_sberror_din <= UInt<3>("h00") @[dbg.scala 338:20] + sbaddress0_reg_wren1 <= UInt<1>("h00") @[dbg.scala 339:24] + node _T_514 = eq(UInt<4>("h00"), sb_state) @[Conditional.scala 37:30] + when _T_514 : @[Conditional.scala 40:58] + node _T_515 = mux(sbdata0wr_access, UInt<4>("h02"), UInt<4>("h01")) @[dbg.scala 342:25] + sb_nxtstate <= _T_515 @[dbg.scala 342:19] + node _T_516 = or(sbdata0wr_access, sbreadondata_access) @[dbg.scala 343:39] + node _T_517 = or(_T_516, sbreadonaddr_access) @[dbg.scala 343:61] + sb_state_en <= _T_517 @[dbg.scala 343:19] + sbcs_sbbusy_wren <= sb_state_en @[dbg.scala 344:24] + sbcs_sbbusy_din <= UInt<1>("h01") @[dbg.scala 345:23] + node _T_518 = bits(io.dmi_reg_wdata, 14, 12) @[dbg.scala 346:56] + node _T_519 = orr(_T_518) @[dbg.scala 346:65] + node _T_520 = and(sbcs_wren, _T_519) @[dbg.scala 346:38] + sbcs_sberror_wren <= _T_520 @[dbg.scala 346:25] + node _T_521 = bits(io.dmi_reg_wdata, 14, 12) @[dbg.scala 347:44] + node _T_522 = eq(_T_521, UInt<1>("h00")) @[dbg.scala 347:27] + node _T_523 = bits(sbcs_reg, 14, 12) @[dbg.scala 347:63] + node _T_524 = and(_T_522, _T_523) @[dbg.scala 347:53] + sbcs_sberror_din <= _T_524 @[dbg.scala 347:24] + skip @[Conditional.scala 40:58] + else : @[Conditional.scala 39:67] + node _T_525 = eq(UInt<4>("h01"), sb_state) @[Conditional.scala 37:30] + when _T_525 : @[Conditional.scala 39:67] + node _T_526 = or(sbcs_unaligned, sbcs_illegal_size) @[dbg.scala 350:41] + node _T_527 = mux(_T_526, UInt<4>("h09"), UInt<4>("h03")) @[dbg.scala 350:25] + sb_nxtstate <= _T_527 @[dbg.scala 350:19] + node _T_528 = or(io.dbg_bus_clk_en, sbcs_unaligned) @[dbg.scala 351:40] + node _T_529 = or(_T_528, sbcs_illegal_size) @[dbg.scala 351:57] + sb_state_en <= _T_529 @[dbg.scala 351:19] + node _T_530 = or(sbcs_unaligned, sbcs_illegal_size) @[dbg.scala 352:43] + sbcs_sberror_wren <= _T_530 @[dbg.scala 352:25] + node _T_531 = mux(sbcs_unaligned, UInt<2>("h03"), UInt<3>("h04")) @[dbg.scala 353:30] + sbcs_sberror_din <= _T_531 @[dbg.scala 353:24] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_532 = eq(UInt<4>("h02"), sb_state) @[Conditional.scala 37:30] + when _T_532 : @[Conditional.scala 39:67] + node _T_533 = or(sbcs_unaligned, sbcs_illegal_size) @[dbg.scala 356:41] + node _T_534 = mux(_T_533, UInt<4>("h09"), UInt<4>("h04")) @[dbg.scala 356:25] + sb_nxtstate <= _T_534 @[dbg.scala 356:19] + node _T_535 = or(io.dbg_bus_clk_en, sbcs_unaligned) @[dbg.scala 357:40] + node _T_536 = or(_T_535, sbcs_illegal_size) @[dbg.scala 357:57] + sb_state_en <= _T_536 @[dbg.scala 357:19] + node _T_537 = or(sbcs_unaligned, sbcs_illegal_size) @[dbg.scala 358:43] + sbcs_sberror_wren <= _T_537 @[dbg.scala 358:25] + node _T_538 = mux(sbcs_unaligned, UInt<2>("h03"), UInt<3>("h04")) @[dbg.scala 359:30] + sbcs_sberror_din <= _T_538 @[dbg.scala 359:24] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_539 = eq(UInt<4>("h03"), sb_state) @[Conditional.scala 37:30] + when _T_539 : @[Conditional.scala 39:67] + sb_nxtstate <= UInt<4>("h07") @[dbg.scala 362:19] + node _T_540 = and(sb_bus_cmd_read, io.dbg_bus_clk_en) @[dbg.scala 363:38] + sb_state_en <= _T_540 @[dbg.scala 363:19] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_541 = eq(UInt<4>("h04"), sb_state) @[Conditional.scala 37:30] + when _T_541 : @[Conditional.scala 39:67] + node _T_542 = and(sb_bus_cmd_write_addr, sb_bus_cmd_write_data) @[dbg.scala 366:48] + node _T_543 = mux(sb_bus_cmd_write_data, UInt<4>("h05"), UInt<4>("h06")) @[dbg.scala 366:95] + node _T_544 = mux(_T_542, UInt<4>("h08"), _T_543) @[dbg.scala 366:25] + sb_nxtstate <= _T_544 @[dbg.scala 366:19] + node _T_545 = or(sb_bus_cmd_write_addr, sb_bus_cmd_write_data) @[dbg.scala 367:45] + node _T_546 = and(_T_545, io.dbg_bus_clk_en) @[dbg.scala 367:70] + sb_state_en <= _T_546 @[dbg.scala 367:19] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_547 = eq(UInt<4>("h05"), sb_state) @[Conditional.scala 37:30] + when _T_547 : @[Conditional.scala 39:67] + sb_nxtstate <= UInt<4>("h08") @[dbg.scala 370:19] + node _T_548 = and(sb_bus_cmd_write_addr, io.dbg_bus_clk_en) @[dbg.scala 371:44] + sb_state_en <= _T_548 @[dbg.scala 371:19] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_549 = eq(UInt<4>("h06"), sb_state) @[Conditional.scala 37:30] + when _T_549 : @[Conditional.scala 39:67] + sb_nxtstate <= UInt<4>("h08") @[dbg.scala 374:19] + node _T_550 = and(sb_bus_cmd_write_data, io.dbg_bus_clk_en) @[dbg.scala 375:44] + sb_state_en <= _T_550 @[dbg.scala 375:19] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_551 = eq(UInt<4>("h07"), sb_state) @[Conditional.scala 37:30] + when _T_551 : @[Conditional.scala 39:67] + sb_nxtstate <= UInt<4>("h09") @[dbg.scala 378:19] + node _T_552 = and(sb_bus_rsp_read, io.dbg_bus_clk_en) @[dbg.scala 379:38] + sb_state_en <= _T_552 @[dbg.scala 379:19] + node _T_553 = and(sb_state_en, sb_bus_rsp_error) @[dbg.scala 380:40] + sbcs_sberror_wren <= _T_553 @[dbg.scala 380:25] + sbcs_sberror_din <= UInt<2>("h02") @[dbg.scala 381:24] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_554 = eq(UInt<4>("h08"), sb_state) @[Conditional.scala 37:30] + when _T_554 : @[Conditional.scala 39:67] + sb_nxtstate <= UInt<4>("h09") @[dbg.scala 384:19] + node _T_555 = and(sb_bus_rsp_write, io.dbg_bus_clk_en) @[dbg.scala 385:39] + sb_state_en <= _T_555 @[dbg.scala 385:19] + node _T_556 = and(sb_state_en, sb_bus_rsp_error) @[dbg.scala 386:40] + sbcs_sberror_wren <= _T_556 @[dbg.scala 386:25] + sbcs_sberror_din <= UInt<2>("h02") @[dbg.scala 387:24] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_557 = eq(UInt<4>("h09"), sb_state) @[Conditional.scala 37:30] + when _T_557 : @[Conditional.scala 39:67] + sb_nxtstate <= UInt<4>("h00") @[dbg.scala 390:19] + sb_state_en <= UInt<1>("h01") @[dbg.scala 391:19] + sbcs_sbbusy_wren <= UInt<1>("h01") @[dbg.scala 392:24] + sbcs_sbbusy_din <= UInt<1>("h00") @[dbg.scala 393:23] + node _T_558 = bits(sbcs_reg, 16, 16) @[dbg.scala 394:39] + sbaddress0_reg_wren1 <= _T_558 @[dbg.scala 394:28] + skip @[Conditional.scala 39:67] + node _T_559 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 397:46] + reg _T_560 : UInt, rvclkhdr_1.io.l1clk with : (reset => (_T_559, UInt<1>("h00"))) @[Reg.scala 27:20] + when sb_state_en : @[Reg.scala 28:19] + _T_560 <= sb_nxtstate @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + sb_state <= _T_560 @[dbg.scala 397:12] + node _T_561 = and(io.sb_axi.ar.valid, io.sb_axi.ar.ready) @[dbg.scala 401:41] + sb_bus_cmd_read <= _T_561 @[dbg.scala 401:19] + node _T_562 = and(io.sb_axi.aw.valid, io.sb_axi.aw.ready) @[dbg.scala 402:47] + sb_bus_cmd_write_addr <= _T_562 @[dbg.scala 402:25] + node _T_563 = and(io.sb_axi.w.valid, io.sb_axi.w.ready) @[dbg.scala 403:46] + sb_bus_cmd_write_data <= _T_563 @[dbg.scala 403:25] + node _T_564 = and(io.sb_axi.r.valid, io.sb_axi.r.ready) @[dbg.scala 404:40] + sb_bus_rsp_read <= _T_564 @[dbg.scala 404:19] + node _T_565 = and(io.sb_axi.b.valid, io.sb_axi.b.ready) @[dbg.scala 405:41] + sb_bus_rsp_write <= _T_565 @[dbg.scala 405:20] + node _T_566 = bits(io.sb_axi.r.bits.resp, 1, 0) @[dbg.scala 406:62] + node _T_567 = orr(_T_566) @[dbg.scala 406:69] + node _T_568 = and(sb_bus_rsp_read, _T_567) @[dbg.scala 406:39] + node _T_569 = bits(io.sb_axi.b.bits.resp, 1, 0) @[dbg.scala 406:115] + node _T_570 = orr(_T_569) @[dbg.scala 406:122] + node _T_571 = and(sb_bus_rsp_write, _T_570) @[dbg.scala 406:92] + node _T_572 = or(_T_568, _T_571) @[dbg.scala 406:73] + sb_bus_rsp_error <= _T_572 @[dbg.scala 406:20] + node _T_573 = eq(sb_state, UInt<4>("h04")) @[dbg.scala 407:36] + node _T_574 = eq(sb_state, UInt<4>("h05")) @[dbg.scala 407:71] + node _T_575 = or(_T_573, _T_574) @[dbg.scala 407:59] + node _T_576 = bits(_T_575, 0, 0) @[dbg.scala 407:106] + io.sb_axi.aw.valid <= _T_576 @[dbg.scala 407:22] + io.sb_axi.aw.bits.addr <= sbaddress0_reg @[dbg.scala 408:26] + io.sb_axi.aw.bits.id <= UInt<1>("h00") @[dbg.scala 409:24] + node _T_577 = bits(sbcs_reg, 19, 17) @[dbg.scala 410:37] + io.sb_axi.aw.bits.size <= _T_577 @[dbg.scala 410:26] + io.sb_axi.aw.bits.prot <= UInt<1>("h00") @[dbg.scala 411:26] + io.sb_axi.aw.bits.cache <= UInt<4>("h0f") @[dbg.scala 412:27] + node _T_578 = bits(sbaddress0_reg, 31, 28) @[dbg.scala 413:45] + io.sb_axi.aw.bits.region <= _T_578 @[dbg.scala 413:28] + io.sb_axi.aw.bits.len <= UInt<1>("h00") @[dbg.scala 414:25] + io.sb_axi.aw.bits.burst <= UInt<1>("h01") @[dbg.scala 415:27] + io.sb_axi.aw.bits.qos <= UInt<1>("h00") @[dbg.scala 416:25] + io.sb_axi.aw.bits.lock <= UInt<1>("h00") @[dbg.scala 417:26] + node _T_579 = eq(sb_state, UInt<4>("h04")) @[dbg.scala 418:35] + node _T_580 = eq(sb_state, UInt<4>("h06")) @[dbg.scala 418:70] + node _T_581 = or(_T_579, _T_580) @[dbg.scala 418:58] + node _T_582 = bits(_T_581, 0, 0) @[dbg.scala 418:105] + io.sb_axi.w.valid <= _T_582 @[dbg.scala 418:21] + node _T_583 = bits(sbcs_reg, 19, 17) @[dbg.scala 419:46] + node _T_584 = eq(_T_583, UInt<1>("h00")) @[dbg.scala 419:55] + node _T_585 = bits(_T_584, 0, 0) @[Bitwise.scala 72:15] + node _T_586 = mux(_T_585, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12] + node _T_587 = bits(sbdata0_reg, 7, 0) @[dbg.scala 419:87] + node _T_588 = cat(_T_587, _T_587) @[Cat.scala 29:58] + node _T_589 = cat(_T_588, _T_588) @[Cat.scala 29:58] + node _T_590 = cat(_T_589, _T_589) @[Cat.scala 29:58] + node _T_591 = and(_T_586, _T_590) @[dbg.scala 419:65] + node _T_592 = bits(sbcs_reg, 19, 17) @[dbg.scala 419:116] + node _T_593 = eq(_T_592, UInt<1>("h01")) @[dbg.scala 419:125] + node _T_594 = bits(_T_593, 0, 0) @[Bitwise.scala 72:15] + node _T_595 = mux(_T_594, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12] + node _T_596 = bits(sbdata0_reg, 15, 0) @[dbg.scala 419:159] + node _T_597 = cat(_T_596, _T_596) @[Cat.scala 29:58] + node _T_598 = cat(_T_597, _T_597) @[Cat.scala 29:58] + node _T_599 = and(_T_595, _T_598) @[dbg.scala 419:138] + node _T_600 = or(_T_591, _T_599) @[dbg.scala 419:96] + node _T_601 = bits(sbcs_reg, 19, 17) @[dbg.scala 420:23] + node _T_602 = eq(_T_601, UInt<2>("h02")) @[dbg.scala 420:32] + node _T_603 = bits(_T_602, 0, 0) @[Bitwise.scala 72:15] + node _T_604 = mux(_T_603, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12] + node _T_605 = bits(sbdata0_reg, 31, 0) @[dbg.scala 420:67] + node _T_606 = cat(_T_605, _T_605) @[Cat.scala 29:58] + node _T_607 = and(_T_604, _T_606) @[dbg.scala 420:45] + node _T_608 = or(_T_600, _T_607) @[dbg.scala 419:168] + node _T_609 = bits(sbcs_reg, 19, 17) @[dbg.scala 420:97] + node _T_610 = eq(_T_609, UInt<2>("h03")) @[dbg.scala 420:106] + node _T_611 = bits(_T_610, 0, 0) @[Bitwise.scala 72:15] + node _T_612 = mux(_T_611, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12] + node _T_613 = bits(sbdata1_reg, 31, 0) @[dbg.scala 420:136] + node _T_614 = bits(sbdata0_reg, 31, 0) @[dbg.scala 420:156] + node _T_615 = cat(_T_613, _T_614) @[Cat.scala 29:58] + node _T_616 = and(_T_612, _T_615) @[dbg.scala 420:119] + node _T_617 = or(_T_608, _T_616) @[dbg.scala 420:77] + io.sb_axi.w.bits.data <= _T_617 @[dbg.scala 419:25] + node _T_618 = bits(sbcs_reg, 19, 17) @[dbg.scala 422:45] + node _T_619 = eq(_T_618, UInt<1>("h00")) @[dbg.scala 422:54] + node _T_620 = bits(_T_619, 0, 0) @[Bitwise.scala 72:15] + node _T_621 = mux(_T_620, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_622 = bits(sbaddress0_reg, 2, 0) @[dbg.scala 422:99] + node _T_623 = dshl(UInt<8>("h01"), _T_622) @[dbg.scala 422:82] + node _T_624 = and(_T_621, _T_623) @[dbg.scala 422:67] + node _T_625 = bits(sbcs_reg, 19, 17) @[dbg.scala 423:22] + node _T_626 = eq(_T_625, UInt<1>("h01")) @[dbg.scala 423:31] + node _T_627 = bits(_T_626, 0, 0) @[Bitwise.scala 72:15] + node _T_628 = mux(_T_627, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_629 = bits(sbaddress0_reg, 2, 1) @[dbg.scala 423:80] + node _T_630 = cat(_T_629, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_631 = dshl(UInt<8>("h03"), _T_630) @[dbg.scala 423:59] + node _T_632 = and(_T_628, _T_631) @[dbg.scala 423:44] + node _T_633 = or(_T_624, _T_632) @[dbg.scala 422:107] + node _T_634 = bits(sbcs_reg, 19, 17) @[dbg.scala 424:22] + node _T_635 = eq(_T_634, UInt<2>("h02")) @[dbg.scala 424:31] + node _T_636 = bits(_T_635, 0, 0) @[Bitwise.scala 72:15] + node _T_637 = mux(_T_636, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_638 = bits(sbaddress0_reg, 2, 2) @[dbg.scala 424:80] + node _T_639 = cat(_T_638, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_640 = dshl(UInt<8>("h0f"), _T_639) @[dbg.scala 424:59] + node _T_641 = and(_T_637, _T_640) @[dbg.scala 424:44] + node _T_642 = or(_T_633, _T_641) @[dbg.scala 423:97] + node _T_643 = bits(sbcs_reg, 19, 17) @[dbg.scala 425:22] + node _T_644 = eq(_T_643, UInt<2>("h03")) @[dbg.scala 425:31] + node _T_645 = bits(_T_644, 0, 0) @[Bitwise.scala 72:15] + node _T_646 = mux(_T_645, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_647 = and(_T_646, UInt<8>("h0ff")) @[dbg.scala 425:44] + node _T_648 = or(_T_642, _T_647) @[dbg.scala 424:95] + io.sb_axi.w.bits.strb <= _T_648 @[dbg.scala 422:25] + io.sb_axi.w.bits.last <= UInt<1>("h01") @[dbg.scala 427:25] + node _T_649 = eq(sb_state, UInt<4>("h03")) @[dbg.scala 428:35] + node _T_650 = bits(_T_649, 0, 0) @[dbg.scala 428:64] + io.sb_axi.ar.valid <= _T_650 @[dbg.scala 428:22] + io.sb_axi.ar.bits.addr <= sbaddress0_reg @[dbg.scala 429:26] + io.sb_axi.ar.bits.id <= UInt<1>("h00") @[dbg.scala 430:24] + node _T_651 = bits(sbcs_reg, 19, 17) @[dbg.scala 431:37] + io.sb_axi.ar.bits.size <= _T_651 @[dbg.scala 431:26] + io.sb_axi.ar.bits.prot <= UInt<1>("h00") @[dbg.scala 432:26] + io.sb_axi.ar.bits.cache <= UInt<1>("h00") @[dbg.scala 433:27] + node _T_652 = bits(sbaddress0_reg, 31, 28) @[dbg.scala 434:45] + io.sb_axi.ar.bits.region <= _T_652 @[dbg.scala 434:28] + io.sb_axi.ar.bits.len <= UInt<1>("h00") @[dbg.scala 435:25] + io.sb_axi.ar.bits.burst <= UInt<1>("h01") @[dbg.scala 436:27] + io.sb_axi.ar.bits.qos <= UInt<1>("h00") @[dbg.scala 437:25] + io.sb_axi.ar.bits.lock <= UInt<1>("h00") @[dbg.scala 438:26] + io.sb_axi.b.ready <= UInt<1>("h01") @[dbg.scala 439:21] + io.sb_axi.r.ready <= UInt<1>("h01") @[dbg.scala 440:21] + node _T_653 = bits(sbcs_reg, 19, 17) @[dbg.scala 441:37] + node _T_654 = eq(_T_653, UInt<1>("h00")) @[dbg.scala 441:46] + node _T_655 = bits(_T_654, 0, 0) @[Bitwise.scala 72:15] + node _T_656 = mux(_T_655, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12] + node _T_657 = bits(io.sb_axi.r.bits.data, 63, 0) @[dbg.scala 441:84] + node _T_658 = bits(sbaddress0_reg, 2, 0) @[dbg.scala 441:115] + node _T_659 = mul(UInt<4>("h08"), _T_658) @[dbg.scala 441:99] + node _T_660 = dshr(_T_657, _T_659) @[dbg.scala 441:92] + node _T_661 = and(_T_660, UInt<64>("h0ff")) @[dbg.scala 441:123] + node _T_662 = and(_T_656, _T_661) @[dbg.scala 441:59] + node _T_663 = bits(sbcs_reg, 19, 17) @[dbg.scala 442:23] + node _T_664 = eq(_T_663, UInt<1>("h01")) @[dbg.scala 442:32] + node _T_665 = bits(_T_664, 0, 0) @[Bitwise.scala 72:15] + node _T_666 = mux(_T_665, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12] + node _T_667 = bits(io.sb_axi.r.bits.data, 63, 0) @[dbg.scala 442:70] + node _T_668 = bits(sbaddress0_reg, 2, 1) @[dbg.scala 442:102] + node _T_669 = mul(UInt<5>("h010"), _T_668) @[dbg.scala 442:86] + node _T_670 = dshr(_T_667, _T_669) @[dbg.scala 442:78] + node _T_671 = and(_T_670, UInt<64>("h0ffff")) @[dbg.scala 442:110] + node _T_672 = and(_T_666, _T_671) @[dbg.scala 442:45] + node _T_673 = or(_T_662, _T_672) @[dbg.scala 441:140] + node _T_674 = bits(sbcs_reg, 19, 17) @[dbg.scala 443:23] + node _T_675 = eq(_T_674, UInt<2>("h02")) @[dbg.scala 443:32] + node _T_676 = bits(_T_675, 0, 0) @[Bitwise.scala 72:15] + node _T_677 = mux(_T_676, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12] + node _T_678 = bits(io.sb_axi.r.bits.data, 63, 0) @[dbg.scala 443:70] + node _T_679 = bits(sbaddress0_reg, 2, 2) @[dbg.scala 443:102] + node _T_680 = mul(UInt<6>("h020"), _T_679) @[dbg.scala 443:86] + node _T_681 = dshr(_T_678, _T_680) @[dbg.scala 443:78] + node _T_682 = and(_T_681, UInt<64>("h0ffffffff")) @[dbg.scala 443:107] + node _T_683 = and(_T_677, _T_682) @[dbg.scala 443:45] + node _T_684 = or(_T_673, _T_683) @[dbg.scala 442:129] + node _T_685 = bits(sbcs_reg, 19, 17) @[dbg.scala 444:23] + node _T_686 = eq(_T_685, UInt<2>("h03")) @[dbg.scala 444:32] + node _T_687 = bits(_T_686, 0, 0) @[Bitwise.scala 72:15] + node _T_688 = mux(_T_687, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12] + node _T_689 = bits(io.sb_axi.r.bits.data, 63, 0) @[dbg.scala 444:68] + node _T_690 = and(_T_688, _T_689) @[dbg.scala 444:45] + node _T_691 = or(_T_684, _T_690) @[dbg.scala 443:131] + sb_bus_rdata <= _T_691 @[dbg.scala 441:16] + io.dbg_dma.dbg_ib.dbg_cmd_addr <= io.dbg_dec.dbg_ib.dbg_cmd_addr @[dbg.scala 447:39] + io.dbg_dma.dbg_dctl.dbg_cmd_wrdata <= io.dbg_dec.dbg_dctl.dbg_cmd_wrdata @[dbg.scala 448:39] + io.dbg_dma.dbg_ib.dbg_cmd_valid <= io.dbg_dec.dbg_ib.dbg_cmd_valid @[dbg.scala 449:39] + io.dbg_dma.dbg_ib.dbg_cmd_write <= io.dbg_dec.dbg_ib.dbg_cmd_write @[dbg.scala 450:39] + io.dbg_dma.dbg_ib.dbg_cmd_type <= io.dbg_dec.dbg_ib.dbg_cmd_type @[dbg.scala 451:39] + diff --git a/dbg.v b/dbg.v new file mode 100644 index 00000000..b5870c2a --- /dev/null +++ b/dbg.v @@ -0,0 +1,1044 @@ +module rvclkhdr( + output io_l1clk, + input io_clk, + input io_en, + input io_scan_mode +); + wire clkhdr_Q; // @[el2_lib.scala 474:26] + wire clkhdr_CK; // @[el2_lib.scala 474:26] + wire clkhdr_EN; // @[el2_lib.scala 474:26] + wire clkhdr_SE; // @[el2_lib.scala 474:26] + gated_latch clkhdr ( // @[el2_lib.scala 474:26] + .Q(clkhdr_Q), + .CK(clkhdr_CK), + .EN(clkhdr_EN), + .SE(clkhdr_SE) + ); + assign io_l1clk = clkhdr_Q; // @[el2_lib.scala 475:14] + assign clkhdr_CK = io_clk; // @[el2_lib.scala 476:18] + assign clkhdr_EN = io_en; // @[el2_lib.scala 477:18] + assign clkhdr_SE = io_scan_mode; // @[el2_lib.scala 478:18] +endmodule +module rvclkhdr_2( + output io_l1clk, + input io_clk, + input io_en, + input io_scan_mode +); + wire clkhdr_Q; // @[el2_lib.scala 474:26] + wire clkhdr_CK; // @[el2_lib.scala 474:26] + wire clkhdr_EN; // @[el2_lib.scala 474:26] + wire clkhdr_SE; // @[el2_lib.scala 474:26] + gated_latch clkhdr ( // @[el2_lib.scala 474:26] + .Q(clkhdr_Q), + .CK(clkhdr_CK), + .EN(clkhdr_EN), + .SE(clkhdr_SE) + ); + assign io_l1clk = clkhdr_Q; // @[el2_lib.scala 475:14] + assign clkhdr_CK = io_clk; // @[el2_lib.scala 476:18] + assign clkhdr_EN = io_en; // @[el2_lib.scala 477:18] + assign clkhdr_SE = io_scan_mode; // @[el2_lib.scala 478:18] +endmodule +module dbg( + input clock, + input reset, + output [1:0] io_dbg_cmd_size, + output io_dbg_core_rst_l, + input [31:0] io_core_dbg_rddata, + input io_core_dbg_cmd_done, + input io_core_dbg_cmd_fail, + output io_dbg_halt_req, + output io_dbg_resume_req, + input io_dec_tlu_debug_mode, + input io_dec_tlu_dbg_halted, + input io_dec_tlu_mpc_halted_only, + input io_dec_tlu_resume_ack, + input io_dmi_reg_en, + input [6:0] io_dmi_reg_addr, + input io_dmi_reg_wr_en, + input [31:0] io_dmi_reg_wdata, + output [31:0] io_dmi_reg_rdata, + input io_sb_axi_aw_ready, + output io_sb_axi_aw_valid, + output io_sb_axi_aw_bits_id, + output [31:0] io_sb_axi_aw_bits_addr, + output [3:0] io_sb_axi_aw_bits_region, + output [7:0] io_sb_axi_aw_bits_len, + output [2:0] io_sb_axi_aw_bits_size, + output [1:0] io_sb_axi_aw_bits_burst, + output io_sb_axi_aw_bits_lock, + output [3:0] io_sb_axi_aw_bits_cache, + output [2:0] io_sb_axi_aw_bits_prot, + output [3:0] io_sb_axi_aw_bits_qos, + input io_sb_axi_w_ready, + output io_sb_axi_w_valid, + output [63:0] io_sb_axi_w_bits_data, + output [7:0] io_sb_axi_w_bits_strb, + output io_sb_axi_w_bits_last, + output io_sb_axi_b_ready, + input io_sb_axi_b_valid, + input [1:0] io_sb_axi_b_bits_resp, + input io_sb_axi_b_bits_id, + input io_sb_axi_ar_ready, + output io_sb_axi_ar_valid, + output io_sb_axi_ar_bits_id, + output [31:0] io_sb_axi_ar_bits_addr, + output [3:0] io_sb_axi_ar_bits_region, + output [7:0] io_sb_axi_ar_bits_len, + output [2:0] io_sb_axi_ar_bits_size, + output [1:0] io_sb_axi_ar_bits_burst, + output io_sb_axi_ar_bits_lock, + output [3:0] io_sb_axi_ar_bits_cache, + output [2:0] io_sb_axi_ar_bits_prot, + output [3:0] io_sb_axi_ar_bits_qos, + output io_sb_axi_r_ready, + input io_sb_axi_r_valid, + input io_sb_axi_r_bits_id, + input [63:0] io_sb_axi_r_bits_data, + input [1:0] io_sb_axi_r_bits_resp, + input io_sb_axi_r_bits_last, + output io_dbg_dec_dbg_ib_dbg_cmd_valid, + output io_dbg_dec_dbg_ib_dbg_cmd_write, + output [1:0] io_dbg_dec_dbg_ib_dbg_cmd_type, + output [31:0] io_dbg_dec_dbg_ib_dbg_cmd_addr, + output [1:0] io_dbg_dec_dbg_dctl_dbg_cmd_wrdata, + output io_dbg_dma_dbg_ib_dbg_cmd_valid, + output io_dbg_dma_dbg_ib_dbg_cmd_write, + output [1:0] io_dbg_dma_dbg_ib_dbg_cmd_type, + output [31:0] io_dbg_dma_dbg_ib_dbg_cmd_addr, + output [1:0] io_dbg_dma_dbg_dctl_dbg_cmd_wrdata, + output io_dbg_dma_io_dbg_dma_bubble, + input io_dbg_dma_io_dma_dbg_ready, + input io_dbg_bus_clk_en, + input io_dbg_rst_l, + input io_clk_override, + input io_scan_mode +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; + reg [31:0] _RAND_8; + reg [31:0] _RAND_9; + reg [31:0] _RAND_10; + reg [31:0] _RAND_11; + reg [31:0] _RAND_12; + reg [31:0] _RAND_13; + reg [31:0] _RAND_14; + reg [31:0] _RAND_15; + reg [31:0] _RAND_16; + reg [31:0] _RAND_17; + reg [31:0] _RAND_18; + reg [31:0] _RAND_19; + reg [31:0] _RAND_20; + reg [31:0] _RAND_21; +`endif // RANDOMIZE_REG_INIT + wire rvclkhdr_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_1_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_1_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_2_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_2_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_3_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_3_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_3_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_4_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_4_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_4_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_4_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_5_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_5_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_5_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_5_io_scan_mode; // @[el2_lib.scala 508:23] + reg [2:0] dbg_state; // @[Reg.scala 27:20] + wire _T = dbg_state != 3'h0; // @[dbg.scala 95:51] + wire _T_1 = io_dmi_reg_en | _T; // @[dbg.scala 95:38] + wire _T_309 = 3'h0 == dbg_state; // @[Conditional.scala 37:30] + reg [3:0] dm_temp; // @[Reg.scala 27:20] + reg dm_temp_0; // @[Reg.scala 27:20] + wire [31:0] temp = {dm_temp[3:2],1'h0,dm_temp[1],26'h0,dm_temp[0],dm_temp_0}; // @[Cat.scala 29:58] + wire _T_314 = ~io_dec_tlu_debug_mode; // @[dbg.scala 266:45] + wire _T_315 = temp[31] & _T_314; // @[dbg.scala 266:43] + reg dmstatus_havereset; // @[Reg.scala 27:20] + wire [1:0] _T_150 = dmstatus_havereset ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + reg dmstatus_resumeack; // @[Reg.scala 27:20] + wire [1:0] _T_152 = dmstatus_resumeack ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire _T_183 = ~reset; // @[dbg.scala 191:43] + wire dmstatus_unavail = temp[1] | _T_183; // @[dbg.scala 191:41] + wire [1:0] _T_154 = dmstatus_unavail ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + reg dmstatus_halted; // @[dbg.scala 198:12] + wire _T_186 = dmstatus_unavail | dmstatus_halted; // @[dbg.scala 192:42] + wire dmstatus_running = ~_T_186; // @[dbg.scala 192:23] + wire [1:0] _T_156 = dmstatus_running ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_158 = dmstatus_halted ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [31:0] dmstatus_reg = {12'h0,_T_150,_T_152,2'h0,_T_154,_T_156,_T_158,1'h1,7'h2}; // @[Cat.scala 29:58] + wire _T_317 = _T_315 | dmstatus_reg[9]; // @[dbg.scala 266:69] + wire _T_318 = _T_317 | io_dec_tlu_mpc_halted_only; // @[dbg.scala 266:87] + wire _T_320 = ~temp[1]; // @[dbg.scala 266:119] + wire _T_321 = _T_318 & _T_320; // @[dbg.scala 266:117] + wire _T_327 = 3'h1 == dbg_state; // @[Conditional.scala 37:30] + wire _T_332 = dmstatus_reg[9] | temp[1]; // @[dbg.scala 271:39] + wire _T_339 = 3'h2 == dbg_state; // @[Conditional.scala 37:30] + wire _T_354 = dmstatus_reg[9] & temp[30]; // @[dbg.scala 278:39] + wire _T_356 = ~temp[31]; // @[dbg.scala 278:61] + wire _T_357 = _T_354 & _T_356; // @[dbg.scala 278:59] + reg dmcontrol_wren_Q; // @[dbg.scala 181:12] + wire _T_358 = _T_357 & dmcontrol_wren_Q; // @[dbg.scala 278:80] + wire _T_275 = io_dmi_reg_addr == 7'h17; // @[dbg.scala 235:39] + wire _T_276 = _T_275 & io_dmi_reg_en; // @[dbg.scala 235:52] + wire _T_277 = _T_276 & io_dmi_reg_wr_en; // @[dbg.scala 235:68] + wire _T_278 = dbg_state == 3'h2; // @[dbg.scala 235:100] + wire command_wren = _T_277 & _T_278; // @[dbg.scala 235:87] + wire _T_359 = _T_358 | command_wren; // @[dbg.scala 278:99] + wire _T_361 = _T_359 | temp[1]; // @[dbg.scala 278:114] + wire _T_363 = dmstatus_reg[9] | io_dec_tlu_mpc_halted_only; // @[dbg.scala 279:46] + wire _T_364 = ~_T_363; // @[dbg.scala 279:28] + wire _T_365 = _T_361 | _T_364; // @[dbg.scala 279:26] + wire _T_377 = 3'h3 == dbg_state; // @[Conditional.scala 37:30] + reg abs_temp_12; // @[Reg.scala 27:20] + reg [2:0] abs_temp_10_8; // @[dbg.scala 230:12] + wire [31:0] abstractcs_reg = {19'h0,abs_temp_12,1'h0,abs_temp_10_8,8'h2}; // @[Cat.scala 29:58] + wire _T_384 = |abstractcs_reg[10:8]; // @[dbg.scala 287:79] + wire _T_385 = io_dbg_dec_dbg_ib_dbg_cmd_valid | _T_384; // @[dbg.scala 287:55] + wire _T_387 = _T_385 | temp[1]; // @[dbg.scala 287:83] + wire _T_394 = 3'h4 == dbg_state; // @[Conditional.scala 37:30] + wire _T_398 = io_core_dbg_cmd_done | temp[1]; // @[dbg.scala 292:44] + wire _T_405 = 3'h5 == dbg_state; // @[Conditional.scala 37:30] + wire _T_414 = 3'h6 == dbg_state; // @[Conditional.scala 37:30] + wire _T_417 = dmstatus_reg[17] | temp[1]; // @[dbg.scala 304:40] + wire _GEN_13 = _T_414 & _T_417; // @[Conditional.scala 39:67] + wire _GEN_16 = _T_405 | _GEN_13; // @[Conditional.scala 39:67] + wire _GEN_21 = _T_394 ? _T_398 : _GEN_16; // @[Conditional.scala 39:67] + wire _GEN_26 = _T_377 ? _T_387 : _GEN_21; // @[Conditional.scala 39:67] + wire _GEN_31 = _T_339 ? _T_365 : _GEN_26; // @[Conditional.scala 39:67] + wire _GEN_37 = _T_327 ? _T_332 : _GEN_31; // @[Conditional.scala 39:67] + wire dbg_state_en = _T_309 ? _T_321 : _GEN_37; // @[Conditional.scala 40:58] + wire _T_2 = _T_1 | dbg_state_en; // @[dbg.scala 95:69] + wire _T_3 = _T_2 | io_dec_tlu_dbg_halted; // @[dbg.scala 95:84] + reg [3:0] sb_state; // @[Reg.scala 27:20] + wire sbcs_sbbusy_din = 4'h0 == sb_state; // @[Conditional.scala 37:30] + wire _T_130 = io_dmi_reg_en & io_dmi_reg_wr_en; // @[dbg.scala 165:40] + wire _T_131 = io_dmi_reg_addr == 7'h3c; // @[dbg.scala 165:78] + wire sbdata0wr_access = _T_130 & _T_131; // @[dbg.scala 165:59] + wire _T_125 = ~io_dmi_reg_wr_en; // @[dbg.scala 164:45] + wire _T_126 = io_dmi_reg_en & _T_125; // @[dbg.scala 164:43] + wire _T_128 = _T_126 & _T_131; // @[dbg.scala 164:63] + reg temp_sbcs_22; // @[Reg.scala 27:20] + reg temp_sbcs_21; // @[Reg.scala 27:20] + reg temp_sbcs_20; // @[Reg.scala 27:20] + reg [4:0] temp_sbcs_19_15; // @[Reg.scala 27:20] + reg [2:0] temp_sbcs_14_12; // @[Reg.scala 27:20] + wire [31:0] sbcs_reg = {9'h40,temp_sbcs_22,temp_sbcs_21,temp_sbcs_20,temp_sbcs_19_15,temp_sbcs_14_12,12'h40f}; // @[Cat.scala 29:58] + wire sbreadondata_access = _T_128 & sbcs_reg[15]; // @[dbg.scala 164:95] + wire _T_516 = sbdata0wr_access | sbreadondata_access; // @[dbg.scala 343:39] + wire _T_122 = io_dmi_reg_addr == 7'h39; // @[dbg.scala 163:81] + wire _T_123 = _T_130 & _T_122; // @[dbg.scala 163:62] + wire sbreadonaddr_access = _T_123 & sbcs_reg[20]; // @[dbg.scala 163:94] + wire _T_517 = _T_516 | sbreadonaddr_access; // @[dbg.scala 343:61] + wire _T_525 = 4'h1 == sb_state; // @[Conditional.scala 37:30] + wire _T_46 = sbcs_reg[19:17] == 3'h1; // @[dbg.scala 127:42] + reg [31:0] sbaddress0_reg; // @[el2_lib.scala 514:16] + wire _T_48 = _T_46 & sbaddress0_reg[0]; // @[dbg.scala 127:56] + wire _T_50 = sbcs_reg[19:17] == 3'h2; // @[dbg.scala 128:23] + wire _T_52 = |sbaddress0_reg[1:0]; // @[dbg.scala 128:60] + wire _T_53 = _T_50 & _T_52; // @[dbg.scala 128:37] + wire _T_54 = _T_48 | _T_53; // @[dbg.scala 127:76] + wire _T_56 = sbcs_reg[19:17] == 3'h3; // @[dbg.scala 129:23] + wire _T_58 = |sbaddress0_reg[2:0]; // @[dbg.scala 129:60] + wire _T_59 = _T_56 & _T_58; // @[dbg.scala 129:37] + wire sbcs_unaligned = _T_54 | _T_59; // @[dbg.scala 128:64] + wire _T_528 = io_dbg_bus_clk_en | sbcs_unaligned; // @[dbg.scala 351:40] + wire sbcs_illegal_size = sbcs_reg[19]; // @[dbg.scala 131:35] + wire _T_529 = _T_528 | sbcs_illegal_size; // @[dbg.scala 351:57] + wire _T_532 = 4'h2 == sb_state; // @[Conditional.scala 37:30] + wire _T_539 = 4'h3 == sb_state; // @[Conditional.scala 37:30] + wire sb_bus_cmd_read = io_sb_axi_ar_valid & io_sb_axi_ar_ready; // @[dbg.scala 401:41] + wire _T_540 = sb_bus_cmd_read & io_dbg_bus_clk_en; // @[dbg.scala 363:38] + wire _T_541 = 4'h4 == sb_state; // @[Conditional.scala 37:30] + wire sb_bus_cmd_write_addr = io_sb_axi_aw_valid & io_sb_axi_aw_ready; // @[dbg.scala 402:47] + wire sb_bus_cmd_write_data = io_sb_axi_w_valid & io_sb_axi_w_ready; // @[dbg.scala 403:46] + wire _T_545 = sb_bus_cmd_write_addr | sb_bus_cmd_write_data; // @[dbg.scala 367:45] + wire _T_546 = _T_545 & io_dbg_bus_clk_en; // @[dbg.scala 367:70] + wire _T_547 = 4'h5 == sb_state; // @[Conditional.scala 37:30] + wire _T_548 = sb_bus_cmd_write_addr & io_dbg_bus_clk_en; // @[dbg.scala 371:44] + wire _T_549 = 4'h6 == sb_state; // @[Conditional.scala 37:30] + wire _T_550 = sb_bus_cmd_write_data & io_dbg_bus_clk_en; // @[dbg.scala 375:44] + wire _T_551 = 4'h7 == sb_state; // @[Conditional.scala 37:30] + wire sb_bus_rsp_read = io_sb_axi_r_valid & io_sb_axi_r_ready; // @[dbg.scala 404:40] + wire _T_552 = sb_bus_rsp_read & io_dbg_bus_clk_en; // @[dbg.scala 379:38] + wire _T_554 = 4'h8 == sb_state; // @[Conditional.scala 37:30] + wire sb_bus_rsp_write = io_sb_axi_b_valid & io_sb_axi_b_ready; // @[dbg.scala 405:41] + wire _T_555 = sb_bus_rsp_write & io_dbg_bus_clk_en; // @[dbg.scala 385:39] + wire _T_557 = 4'h9 == sb_state; // @[Conditional.scala 37:30] + wire _GEN_55 = _T_554 ? _T_555 : _T_557; // @[Conditional.scala 39:67] + wire _GEN_62 = _T_551 ? _T_552 : _GEN_55; // @[Conditional.scala 39:67] + wire _GEN_69 = _T_549 ? _T_550 : _GEN_62; // @[Conditional.scala 39:67] + wire _GEN_76 = _T_547 ? _T_548 : _GEN_69; // @[Conditional.scala 39:67] + wire _GEN_83 = _T_541 ? _T_546 : _GEN_76; // @[Conditional.scala 39:67] + wire _GEN_90 = _T_539 ? _T_540 : _GEN_83; // @[Conditional.scala 39:67] + wire _GEN_97 = _T_532 ? _T_529 : _GEN_90; // @[Conditional.scala 39:67] + wire _GEN_104 = _T_525 ? _T_529 : _GEN_97; // @[Conditional.scala 39:67] + wire sb_state_en = sbcs_sbbusy_din ? _T_517 : _GEN_104; // @[Conditional.scala 40:58] + wire _T_4 = io_dmi_reg_en | sb_state_en; // @[dbg.scala 96:37] + wire _T_5 = sb_state != 4'h0; // @[dbg.scala 96:63] + wire _T_6 = _T_4 | _T_5; // @[dbg.scala 96:51] + wire _T_9 = temp[0] | io_scan_mode; // @[dbg.scala 99:64] + wire dbg_dm_rst_l = io_dbg_rst_l & _T_9; // @[dbg.scala 99:44] + wire _T_13 = io_dmi_reg_addr == 7'h38; // @[dbg.scala 101:36] + wire _T_14 = _T_13 & io_dmi_reg_en; // @[dbg.scala 101:49] + wire _T_15 = _T_14 & io_dmi_reg_wr_en; // @[dbg.scala 101:65] + wire _T_16 = sb_state == 4'h0; // @[dbg.scala 101:96] + wire sbcs_wren = _T_15 & _T_16; // @[dbg.scala 101:84] + wire _T_18 = sbcs_wren & io_dmi_reg_wdata[22]; // @[dbg.scala 102:42] + wire _T_20 = _T_5 & io_dmi_reg_en; // @[dbg.scala 102:102] + wire _T_23 = _T_122 | _T_131; // @[dbg.scala 103:36] + wire _T_24 = io_dmi_reg_addr == 7'h3d; // @[dbg.scala 103:87] + wire _T_25 = _T_23 | _T_24; // @[dbg.scala 103:68] + wire _T_26 = _T_20 & _T_25; // @[dbg.scala 102:118] + wire sbcs_sbbusyerror_wren = _T_18 | _T_26; // @[dbg.scala 102:66] + wire sbcs_sbbusyerror_din = ~_T_18; // @[dbg.scala 105:31] + wire _T_29 = ~dbg_dm_rst_l; // @[dbg.scala 106:53] + wire _GEN_58 = _T_554 ? 1'h0 : _T_557; // @[Conditional.scala 39:67] + wire _GEN_65 = _T_551 ? 1'h0 : _GEN_58; // @[Conditional.scala 39:67] + wire _GEN_72 = _T_549 ? 1'h0 : _GEN_65; // @[Conditional.scala 39:67] + wire _GEN_79 = _T_547 ? 1'h0 : _GEN_72; // @[Conditional.scala 39:67] + wire _GEN_86 = _T_541 ? 1'h0 : _GEN_79; // @[Conditional.scala 39:67] + wire _GEN_93 = _T_539 ? 1'h0 : _GEN_86; // @[Conditional.scala 39:67] + wire _GEN_100 = _T_532 ? 1'h0 : _GEN_93; // @[Conditional.scala 39:67] + wire _GEN_107 = _T_525 ? 1'h0 : _GEN_100; // @[Conditional.scala 39:67] + wire sbcs_sbbusy_wren = sbcs_sbbusy_din ? sb_state_en : _GEN_107; // @[Conditional.scala 40:58] + wire _T_522 = io_dmi_reg_wdata[14:12] == 3'h0; // @[dbg.scala 347:27] + wire [2:0] _GEN_118 = {{2'd0}, _T_522}; // @[dbg.scala 347:53] + wire [2:0] _T_524 = _GEN_118 & sbcs_reg[14:12]; // @[dbg.scala 347:53] + wire _T_519 = |io_dmi_reg_wdata[14:12]; // @[dbg.scala 346:65] + wire _T_520 = sbcs_wren & _T_519; // @[dbg.scala 346:38] + wire _T_530 = sbcs_unaligned | sbcs_illegal_size; // @[dbg.scala 352:43] + wire _T_567 = |io_sb_axi_r_bits_resp; // @[dbg.scala 406:69] + wire _T_568 = sb_bus_rsp_read & _T_567; // @[dbg.scala 406:39] + wire _T_570 = |io_sb_axi_b_bits_resp; // @[dbg.scala 406:122] + wire _T_571 = sb_bus_rsp_write & _T_570; // @[dbg.scala 406:92] + wire sb_bus_rsp_error = _T_568 | _T_571; // @[dbg.scala 406:73] + wire _T_553 = sb_state_en & sb_bus_rsp_error; // @[dbg.scala 380:40] + wire _GEN_56 = _T_554 & _T_553; // @[Conditional.scala 39:67] + wire _GEN_63 = _T_551 ? _T_553 : _GEN_56; // @[Conditional.scala 39:67] + wire _GEN_70 = _T_549 ? 1'h0 : _GEN_63; // @[Conditional.scala 39:67] + wire _GEN_77 = _T_547 ? 1'h0 : _GEN_70; // @[Conditional.scala 39:67] + wire _GEN_84 = _T_541 ? 1'h0 : _GEN_77; // @[Conditional.scala 39:67] + wire _GEN_91 = _T_539 ? 1'h0 : _GEN_84; // @[Conditional.scala 39:67] + wire _GEN_98 = _T_532 ? _T_530 : _GEN_91; // @[Conditional.scala 39:67] + wire _GEN_105 = _T_525 ? _T_530 : _GEN_98; // @[Conditional.scala 39:67] + wire sbcs_sberror_wren = sbcs_sbbusy_din ? _T_520 : _GEN_105; // @[Conditional.scala 40:58] + wire _T_61 = sbcs_reg[19:17] == 3'h0; // @[dbg.scala 132:51] + wire [3:0] _T_63 = _T_61 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_64 = _T_63 & 4'h1; // @[dbg.scala 132:64] + wire [3:0] _T_68 = _T_46 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_69 = _T_68 & 4'h2; // @[dbg.scala 132:117] + wire [3:0] _T_70 = _T_64 | _T_69; // @[dbg.scala 132:76] + wire [3:0] _T_74 = _T_50 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_75 = _T_74 & 4'h4; // @[dbg.scala 133:44] + wire [3:0] _T_76 = _T_70 | _T_75; // @[dbg.scala 132:129] + wire [3:0] _T_80 = _T_56 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_81 = _T_80 & 4'h8; // @[dbg.scala 133:97] + wire [3:0] sbaddress0_incr = _T_76 | _T_81; // @[dbg.scala 133:56] + wire _T_84 = sb_state == 4'h7; // @[dbg.scala 136:37] + wire _T_85 = _T_84 & sb_state_en; // @[dbg.scala 136:60] + wire _T_86 = ~sbcs_sberror_wren; // @[dbg.scala 136:76] + wire sbdata0_reg_wren1 = _T_85 & _T_86; // @[dbg.scala 136:74] + wire sbdata1_reg_wren0 = _T_130 & _T_24; // @[dbg.scala 138:60] + wire [31:0] _T_93 = sbdata0wr_access ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_94 = _T_93 & io_dmi_reg_wdata; // @[dbg.scala 141:49] + wire [31:0] _T_96 = sbdata0_reg_wren1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [63:0] _T_656 = _T_61 ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12] + wire [3:0] _GEN_119 = {{1'd0}, sbaddress0_reg[2:0]}; // @[dbg.scala 441:99] + wire [6:0] _T_659 = 4'h8 * _GEN_119; // @[dbg.scala 441:99] + wire [63:0] _T_660 = io_sb_axi_r_bits_data >> _T_659; // @[dbg.scala 441:92] + wire [63:0] _T_661 = _T_660 & 64'hff; // @[dbg.scala 441:123] + wire [63:0] _T_662 = _T_656 & _T_661; // @[dbg.scala 441:59] + wire [63:0] _T_666 = _T_46 ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12] + wire [4:0] _GEN_120 = {{3'd0}, sbaddress0_reg[2:1]}; // @[dbg.scala 442:86] + wire [6:0] _T_669 = 5'h10 * _GEN_120; // @[dbg.scala 442:86] + wire [63:0] _T_670 = io_sb_axi_r_bits_data >> _T_669; // @[dbg.scala 442:78] + wire [63:0] _T_671 = _T_670 & 64'hffff; // @[dbg.scala 442:110] + wire [63:0] _T_672 = _T_666 & _T_671; // @[dbg.scala 442:45] + wire [63:0] _T_673 = _T_662 | _T_672; // @[dbg.scala 441:140] + wire [63:0] _T_677 = _T_50 ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12] + wire [5:0] _GEN_121 = {{5'd0}, sbaddress0_reg[2]}; // @[dbg.scala 443:86] + wire [6:0] _T_680 = 6'h20 * _GEN_121; // @[dbg.scala 443:86] + wire [63:0] _T_681 = io_sb_axi_r_bits_data >> _T_680; // @[dbg.scala 443:78] + wire [63:0] _T_682 = _T_681 & 64'hffffffff; // @[dbg.scala 443:107] + wire [63:0] _T_683 = _T_677 & _T_682; // @[dbg.scala 443:45] + wire [63:0] _T_684 = _T_673 | _T_683; // @[dbg.scala 442:129] + wire [63:0] _T_688 = _T_56 ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12] + wire [63:0] _T_690 = _T_688 & io_sb_axi_r_bits_data; // @[dbg.scala 444:45] + wire [63:0] sb_bus_rdata = _T_684 | _T_690; // @[dbg.scala 443:131] + wire [31:0] _T_98 = _T_96 & sb_bus_rdata[31:0]; // @[dbg.scala 142:33] + wire [31:0] sbdata0_din = _T_94 | _T_98; // @[dbg.scala 141:68] + wire [31:0] _T_100 = sbdata1_reg_wren0 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_101 = _T_100 & io_dmi_reg_wdata; // @[dbg.scala 144:49] + wire [31:0] _T_105 = _T_96 & sb_bus_rdata[63:32]; // @[dbg.scala 145:33] + wire [31:0] sbdata1_din = _T_101 | _T_105; // @[dbg.scala 144:68] + reg [31:0] sbdata0_reg; // @[el2_lib.scala 514:16] + reg [31:0] sbdata1_reg; // @[el2_lib.scala 514:16] + wire _GEN_53 = _T_557 & sbcs_reg[16]; // @[Conditional.scala 39:67] + wire _GEN_60 = _T_554 ? 1'h0 : _GEN_53; // @[Conditional.scala 39:67] + wire _GEN_67 = _T_551 ? 1'h0 : _GEN_60; // @[Conditional.scala 39:67] + wire _GEN_74 = _T_549 ? 1'h0 : _GEN_67; // @[Conditional.scala 39:67] + wire _GEN_81 = _T_547 ? 1'h0 : _GEN_74; // @[Conditional.scala 39:67] + wire _GEN_88 = _T_541 ? 1'h0 : _GEN_81; // @[Conditional.scala 39:67] + wire _GEN_95 = _T_539 ? 1'h0 : _GEN_88; // @[Conditional.scala 39:67] + wire _GEN_102 = _T_532 ? 1'h0 : _GEN_95; // @[Conditional.scala 39:67] + wire _GEN_109 = _T_525 ? 1'h0 : _GEN_102; // @[Conditional.scala 39:67] + wire sbaddress0_reg_wren1 = sbcs_sbbusy_din ? 1'h0 : _GEN_109; // @[Conditional.scala 40:58] + wire [31:0] _T_111 = _T_123 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_112 = _T_111 & io_dmi_reg_wdata; // @[dbg.scala 157:59] + wire [31:0] _T_114 = sbaddress0_reg_wren1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_115 = {28'h0,sbaddress0_incr}; // @[Cat.scala 29:58] + wire [31:0] _T_117 = sbaddress0_reg + _T_115; // @[dbg.scala 158:54] + wire [31:0] _T_118 = _T_114 & _T_117; // @[dbg.scala 158:36] + wire [31:0] sbaddress0_reg_din = _T_112 | _T_118; // @[dbg.scala 157:78] + wire _T_132 = io_dmi_reg_addr == 7'h10; // @[dbg.scala 166:41] + wire _T_133 = _T_132 & io_dmi_reg_en; // @[dbg.scala 166:54] + wire dmcontrol_wren = _T_133 & io_dmi_reg_wr_en; // @[dbg.scala 166:70] + wire [3:0] _T_139 = {io_dmi_reg_wdata[31:30],io_dmi_reg_wdata[28],io_dmi_reg_wdata[1]}; // @[Cat.scala 29:58] + wire _T_168 = dbg_state == 3'h6; // @[dbg.scala 186:44] + wire _T_169 = _T_168 & io_dec_tlu_resume_ack; // @[dbg.scala 186:66] + wire _T_171 = ~temp[30]; // @[dbg.scala 186:113] + wire _T_172 = dmstatus_resumeack & _T_171; // @[dbg.scala 186:111] + wire dmstatus_resumeack_wren = _T_169 | _T_172; // @[dbg.scala 186:90] + wire _T_176 = _T_132 & io_dmi_reg_wdata[1]; // @[dbg.scala 188:63] + wire _T_177 = _T_176 & io_dmi_reg_en; // @[dbg.scala 188:85] + wire dmstatus_havereset_wren = _T_177 & io_dmi_reg_wr_en; // @[dbg.scala 188:101] + wire _T_180 = _T_132 & io_dmi_reg_wdata[28]; // @[dbg.scala 189:62] + wire _T_181 = _T_180 & io_dmi_reg_en; // @[dbg.scala 189:85] + wire dmstatus_havereset_rst = _T_181 & io_dmi_reg_wr_en; // @[dbg.scala 189:101] + wire _T_191 = ~io_dec_tlu_mpc_halted_only; // @[dbg.scala 198:37] + wire _T_192 = io_dec_tlu_dbg_halted & _T_191; // @[dbg.scala 198:35] + wire _T_195 = ~dmstatus_havereset_rst; // @[dbg.scala 202:15] + wire [31:0] haltsum0_reg = {31'h0,dmstatus_halted}; // @[Cat.scala 29:58] + wire _T_198 = abstractcs_reg[12] & io_dmi_reg_en; // @[dbg.scala 208:50] + wire _T_199 = io_dmi_reg_addr == 7'h16; // @[dbg.scala 208:106] + wire _T_201 = _T_199 | _T_275; // @[dbg.scala 208:119] + wire _T_202 = io_dmi_reg_wr_en & _T_201; // @[dbg.scala 208:86] + wire _T_203 = io_dmi_reg_addr == 7'h4; // @[dbg.scala 208:171] + wire _T_204 = _T_202 | _T_203; // @[dbg.scala 208:152] + wire abstractcs_error_sel0 = _T_198 & _T_204; // @[dbg.scala 208:66] + wire _T_207 = _T_130 & _T_275; // @[dbg.scala 209:64] + wire _T_209 = io_dmi_reg_wdata[31:24] == 8'h0; // @[dbg.scala 209:126] + wire _T_211 = io_dmi_reg_wdata[31:24] == 8'h2; // @[dbg.scala 209:163] + wire _T_212 = _T_209 | _T_211; // @[dbg.scala 209:135] + wire _T_213 = ~_T_212; // @[dbg.scala 209:98] + wire abstractcs_error_sel1 = _T_207 & _T_213; // @[dbg.scala 209:96] + wire abstractcs_error_sel2 = io_core_dbg_cmd_done & io_core_dbg_cmd_fail; // @[dbg.scala 210:52] + wire _T_218 = ~dmstatus_reg[9]; // @[dbg.scala 211:98] + wire abstractcs_error_sel3 = _T_207 & _T_218; // @[dbg.scala 211:96] + wire _T_223 = io_dmi_reg_wdata[22:20] != 3'h2; // @[dbg.scala 213:32] + reg [31:0] data1_reg; // @[el2_lib.scala 514:16] + wire _T_227 = |data1_reg[1:0]; // @[dbg.scala 213:106] + wire _T_228 = _T_211 & _T_227; // @[dbg.scala 213:87] + wire _T_229 = _T_223 | _T_228; // @[dbg.scala 213:46] + wire abstractcs_error_sel4 = _T_277 & _T_229; // @[dbg.scala 212:96] + wire _T_231 = _T_199 & io_dmi_reg_en; // @[dbg.scala 215:61] + wire abstractcs_error_sel5 = _T_231 & io_dmi_reg_wr_en; // @[dbg.scala 215:77] + wire _T_232 = abstractcs_error_sel0 | abstractcs_error_sel1; // @[dbg.scala 216:54] + wire _T_233 = _T_232 | abstractcs_error_sel2; // @[dbg.scala 216:78] + wire _T_234 = _T_233 | abstractcs_error_sel3; // @[dbg.scala 216:102] + wire _T_235 = _T_234 | abstractcs_error_sel4; // @[dbg.scala 216:126] + wire abstractcs_error_selor = _T_235 | abstractcs_error_sel5; // @[dbg.scala 216:150] + wire [2:0] _T_237 = abstractcs_error_sel0 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_238 = _T_237 & 3'h1; // @[dbg.scala 217:62] + wire [2:0] _T_240 = abstractcs_error_sel1 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_241 = _T_240 & 3'h2; // @[dbg.scala 218:37] + wire [2:0] _T_242 = _T_238 | _T_241; // @[dbg.scala 217:74] + wire [2:0] _T_244 = abstractcs_error_sel2 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_245 = _T_244 & 3'h3; // @[dbg.scala 219:37] + wire [2:0] _T_246 = _T_242 | _T_245; // @[dbg.scala 218:49] + wire [2:0] _T_248 = abstractcs_error_sel3 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_249 = _T_248 & 3'h4; // @[dbg.scala 220:37] + wire [2:0] _T_250 = _T_246 | _T_249; // @[dbg.scala 219:49] + wire [2:0] _T_252 = abstractcs_error_sel4 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_254 = _T_250 | _T_252; // @[dbg.scala 220:49] + wire [2:0] _T_256 = abstractcs_error_sel5 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_258 = ~io_dmi_reg_wdata[10:8]; // @[dbg.scala 222:40] + wire [2:0] _T_259 = _T_256 & _T_258; // @[dbg.scala 222:37] + wire [2:0] _T_261 = _T_259 & abstractcs_reg[10:8]; // @[dbg.scala 222:75] + wire [2:0] _T_262 = _T_254 | _T_261; // @[dbg.scala 221:49] + wire _T_263 = ~abstractcs_error_selor; // @[dbg.scala 223:15] + wire [2:0] _T_265 = _T_263 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_267 = _T_265 & abstractcs_reg[10:8]; // @[dbg.scala 223:50] + wire [2:0] abstractcs_error_din = _T_262 | _T_267; // @[dbg.scala 222:100] + wire [2:0] _T_312 = _T_363 ? 3'h2 : 3'h1; // @[dbg.scala 265:26] + wire [2:0] _T_329 = temp[1] ? 3'h0 : 3'h2; // @[dbg.scala 270:26] + wire _T_343 = dmstatus_reg[9] & _T_320; // @[dbg.scala 275:43] + wire _T_346 = ~temp[3]; // @[dbg.scala 276:33] + wire _T_347 = temp[30] & _T_346; // @[dbg.scala 276:31] + wire [2:0] _T_348 = _T_347 ? 3'h6 : 3'h3; // @[dbg.scala 276:12] + wire [2:0] _T_350 = temp[31] ? 3'h1 : 3'h0; // @[dbg.scala 277:12] + wire [2:0] _T_351 = _T_343 ? _T_348 : _T_350; // @[dbg.scala 275:26] + wire [2:0] _T_381 = _T_384 ? 3'h5 : 3'h4; // @[dbg.scala 286:62] + wire [2:0] _T_382 = temp[1] ? 3'h0 : _T_381; // @[dbg.scala 286:26] + wire [2:0] _T_396 = temp[1] ? 3'h0 : 3'h5; // @[dbg.scala 291:26] + wire [2:0] _GEN_15 = _T_405 ? _T_329 : 3'h0; // @[Conditional.scala 39:67] + wire [2:0] _GEN_20 = _T_394 ? _T_396 : _GEN_15; // @[Conditional.scala 39:67] + wire [2:0] _GEN_25 = _T_377 ? _T_382 : _GEN_20; // @[Conditional.scala 39:67] + wire [2:0] _GEN_30 = _T_339 ? _T_351 : _GEN_25; // @[Conditional.scala 39:67] + wire [2:0] _GEN_36 = _T_327 ? _T_329 : _GEN_30; // @[Conditional.scala 39:67] + wire [2:0] dbg_nxtstate = _T_309 ? _T_312 : _GEN_36; // @[Conditional.scala 40:58] + wire _T_366 = dbg_nxtstate == 3'h3; // @[dbg.scala 280:60] + wire _T_367 = dbg_state_en & _T_366; // @[dbg.scala 280:44] + wire _GEN_17 = _T_405 & dbg_state_en; // @[Conditional.scala 39:67] + wire _GEN_23 = _T_394 ? 1'h0 : _GEN_17; // @[Conditional.scala 39:67] + wire _GEN_28 = _T_377 ? 1'h0 : _GEN_23; // @[Conditional.scala 39:67] + wire _GEN_32 = _T_339 ? _T_367 : _GEN_28; // @[Conditional.scala 39:67] + wire _GEN_39 = _T_327 ? 1'h0 : _GEN_32; // @[Conditional.scala 39:67] + wire abstractcs_busy_wren = _T_309 ? 1'h0 : _GEN_39; // @[Conditional.scala 40:58] + wire [31:0] command_din = {io_dmi_reg_wdata[31:24],1'h0,io_dmi_reg_wdata[22:20],3'h0,io_dmi_reg_wdata[16:0]}; // @[Cat.scala 29:58] + reg [31:0] command_reg; // @[Reg.scala 27:20] + wire _T_288 = _T_130 & _T_203; // @[dbg.scala 241:58] + wire data0_reg_wren0 = _T_288 & _T_278; // @[dbg.scala 241:89] + wire _T_290 = dbg_state == 3'h4; // @[dbg.scala 242:59] + wire _T_291 = io_core_dbg_cmd_done & _T_290; // @[dbg.scala 242:46] + wire _T_293 = ~command_reg[16]; // @[dbg.scala 242:83] + wire data0_reg_wren1 = _T_291 & _T_293; // @[dbg.scala 242:81] + wire data0_reg_wren = data0_reg_wren0 | data0_reg_wren1; // @[dbg.scala 244:40] + wire [31:0] _T_295 = data0_reg_wren0 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_296 = _T_295 & io_dmi_reg_wdata; // @[dbg.scala 245:45] + wire [31:0] _T_298 = data0_reg_wren1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_299 = _T_298 & io_core_dbg_rddata; // @[dbg.scala 245:92] + wire [31:0] data0_din = _T_296 | _T_299; // @[dbg.scala 245:64] + reg [31:0] data0_reg; // @[Reg.scala 27:20] + wire _T_302 = io_dmi_reg_addr == 7'h5; // @[dbg.scala 250:77] + wire _T_303 = _T_130 & _T_302; // @[dbg.scala 250:58] + wire data1_reg_wren = _T_303 & _T_278; // @[dbg.scala 250:89] + wire [31:0] _T_306 = data1_reg_wren ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] data1_din = _T_306 & io_dmi_reg_wdata; // @[dbg.scala 251:44] + wire _T_325 = temp[31] & _T_320; // @[dbg.scala 267:45] + wire _T_334 = dmcontrol_wren_Q & temp[31]; // @[dbg.scala 272:44] + wire _T_337 = _T_334 & _T_320; // @[dbg.scala 272:64] + wire _T_368 = dbg_nxtstate == 3'h6; // @[dbg.scala 282:58] + wire _T_369 = dbg_state_en & _T_368; // @[dbg.scala 282:42] + wire _GEN_14 = _T_414 & _T_337; // @[Conditional.scala 39:67] + wire _GEN_19 = _T_405 ? _T_337 : _GEN_14; // @[Conditional.scala 39:67] + wire _GEN_22 = _T_394 ? _T_337 : _GEN_19; // @[Conditional.scala 39:67] + wire _GEN_27 = _T_377 ? _T_337 : _GEN_22; // @[Conditional.scala 39:67] + wire _GEN_34 = _T_339 & _T_369; // @[Conditional.scala 39:67] + wire _GEN_35 = _T_339 ? _T_337 : _GEN_27; // @[Conditional.scala 39:67] + wire _GEN_38 = _T_327 ? _T_337 : _GEN_35; // @[Conditional.scala 39:67] + wire _GEN_41 = _T_327 ? 1'h0 : _GEN_34; // @[Conditional.scala 39:67] + wire [31:0] _T_426 = _T_203 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_427 = _T_426 & data0_reg; // @[dbg.scala 308:71] + wire [31:0] _T_430 = _T_302 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_431 = _T_430 & data1_reg; // @[dbg.scala 308:122] + wire [31:0] _T_432 = _T_427 | _T_431; // @[dbg.scala 308:83] + wire [31:0] _T_435 = _T_132 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_436 = _T_435 & temp; // @[dbg.scala 309:43] + wire [31:0] _T_437 = _T_432 | _T_436; // @[dbg.scala 308:134] + wire _T_438 = io_dmi_reg_addr == 7'h11; // @[dbg.scala 309:86] + wire [31:0] _T_440 = _T_438 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_441 = _T_440 & dmstatus_reg; // @[dbg.scala 309:99] + wire [31:0] _T_442 = _T_437 | _T_441; // @[dbg.scala 309:59] + wire [31:0] _T_445 = _T_199 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_446 = _T_445 & abstractcs_reg; // @[dbg.scala 310:43] + wire [31:0] _T_447 = _T_442 | _T_446; // @[dbg.scala 309:114] + wire [31:0] _T_450 = _T_275 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_451 = _T_450 & command_reg; // @[dbg.scala 310:100] + wire [31:0] _T_452 = _T_447 | _T_451; // @[dbg.scala 310:60] + wire _T_453 = io_dmi_reg_addr == 7'h40; // @[dbg.scala 311:30] + wire [31:0] _T_455 = _T_453 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_456 = _T_455 & haltsum0_reg; // @[dbg.scala 311:43] + wire [31:0] _T_457 = _T_452 | _T_456; // @[dbg.scala 310:114] + wire [31:0] _T_460 = _T_13 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_461 = _T_460 & sbcs_reg; // @[dbg.scala 311:98] + wire [31:0] _T_462 = _T_457 | _T_461; // @[dbg.scala 311:58] + wire [31:0] _T_465 = _T_122 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_466 = _T_465 & sbaddress0_reg; // @[dbg.scala 312:43] + wire [31:0] _T_467 = _T_462 | _T_466; // @[dbg.scala 311:109] + wire [31:0] _T_470 = _T_131 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_471 = _T_470 & sbdata0_reg; // @[dbg.scala 312:100] + wire [31:0] _T_472 = _T_467 | _T_471; // @[dbg.scala 312:60] + wire [31:0] _T_475 = _T_24 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_476 = _T_475 & sbdata1_reg; // @[dbg.scala 313:43] + wire [31:0] dmi_reg_rdata_din = _T_472 | _T_476; // @[dbg.scala 312:114] + wire _T_478 = _T_29 & reset; // @[dbg.scala 315:62] + reg [31:0] _T_481; // @[Reg.scala 27:20] + wire _T_483 = command_reg[31:24] == 8'h2; // @[dbg.scala 324:62] + wire [30:0] _T_485 = {data1_reg[31:2],1'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_487 = {20'h0,command_reg[11:0]}; // @[Cat.scala 29:58] + wire _T_490 = dbg_state == 3'h3; // @[dbg.scala 326:50] + wire _T_493 = ~_T_384; // @[dbg.scala 326:75] + wire _T_494 = _T_490 & _T_493; // @[dbg.scala 326:73] + wire _T_502 = command_reg[15:12] == 4'h0; // @[dbg.scala 328:117] + wire [1:0] _T_503 = {1'h0,_T_502}; // @[Cat.scala 29:58] + wire _T_542 = sb_bus_cmd_write_addr & sb_bus_cmd_write_data; // @[dbg.scala 366:48] + wire _T_573 = sb_state == 4'h4; // @[dbg.scala 407:36] + wire _T_574 = sb_state == 4'h5; // @[dbg.scala 407:71] + wire _T_580 = sb_state == 4'h6; // @[dbg.scala 418:70] + wire [63:0] _T_590 = {sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0]}; // @[Cat.scala 29:58] + wire [63:0] _T_591 = _T_656 & _T_590; // @[dbg.scala 419:65] + wire [63:0] _T_598 = {sbdata0_reg[15:0],sbdata0_reg[15:0],sbdata0_reg[15:0],sbdata0_reg[15:0]}; // @[Cat.scala 29:58] + wire [63:0] _T_599 = _T_666 & _T_598; // @[dbg.scala 419:138] + wire [63:0] _T_600 = _T_591 | _T_599; // @[dbg.scala 419:96] + wire [63:0] _T_606 = {sbdata0_reg,sbdata0_reg}; // @[Cat.scala 29:58] + wire [63:0] _T_607 = _T_677 & _T_606; // @[dbg.scala 420:45] + wire [63:0] _T_608 = _T_600 | _T_607; // @[dbg.scala 419:168] + wire [63:0] _T_615 = {sbdata1_reg,sbdata0_reg}; // @[Cat.scala 29:58] + wire [63:0] _T_616 = _T_688 & _T_615; // @[dbg.scala 420:119] + wire [7:0] _T_621 = _T_61 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [14:0] _T_623 = 15'h1 << sbaddress0_reg[2:0]; // @[dbg.scala 422:82] + wire [14:0] _GEN_122 = {{7'd0}, _T_621}; // @[dbg.scala 422:67] + wire [14:0] _T_624 = _GEN_122 & _T_623; // @[dbg.scala 422:67] + wire [7:0] _T_628 = _T_46 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_630 = {sbaddress0_reg[2:1],1'h0}; // @[Cat.scala 29:58] + wire [14:0] _T_631 = 15'h3 << _T_630; // @[dbg.scala 423:59] + wire [14:0] _GEN_123 = {{7'd0}, _T_628}; // @[dbg.scala 423:44] + wire [14:0] _T_632 = _GEN_123 & _T_631; // @[dbg.scala 423:44] + wire [14:0] _T_633 = _T_624 | _T_632; // @[dbg.scala 422:107] + wire [7:0] _T_637 = _T_50 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_639 = {sbaddress0_reg[2],1'h0}; // @[Cat.scala 29:58] + wire [10:0] _T_640 = 11'hf << _T_639; // @[dbg.scala 424:59] + wire [10:0] _GEN_124 = {{3'd0}, _T_637}; // @[dbg.scala 424:44] + wire [10:0] _T_641 = _GEN_124 & _T_640; // @[dbg.scala 424:44] + wire [14:0] _GEN_125 = {{4'd0}, _T_641}; // @[dbg.scala 423:97] + wire [14:0] _T_642 = _T_633 | _GEN_125; // @[dbg.scala 423:97] + wire [7:0] _T_646 = _T_56 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [14:0] _GEN_126 = {{7'd0}, _T_646}; // @[dbg.scala 424:95] + wire [14:0] _T_648 = _T_642 | _GEN_126; // @[dbg.scala 424:95] + rvclkhdr rvclkhdr ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_io_l1clk), + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en), + .io_scan_mode(rvclkhdr_io_scan_mode) + ); + rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_1_io_l1clk), + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en), + .io_scan_mode(rvclkhdr_1_io_scan_mode) + ); + rvclkhdr_2 rvclkhdr_2 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_2_io_l1clk), + .io_clk(rvclkhdr_2_io_clk), + .io_en(rvclkhdr_2_io_en), + .io_scan_mode(rvclkhdr_2_io_scan_mode) + ); + rvclkhdr_2 rvclkhdr_3 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_3_io_l1clk), + .io_clk(rvclkhdr_3_io_clk), + .io_en(rvclkhdr_3_io_en), + .io_scan_mode(rvclkhdr_3_io_scan_mode) + ); + rvclkhdr_2 rvclkhdr_4 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_4_io_l1clk), + .io_clk(rvclkhdr_4_io_clk), + .io_en(rvclkhdr_4_io_en), + .io_scan_mode(rvclkhdr_4_io_scan_mode) + ); + rvclkhdr_2 rvclkhdr_5 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_5_io_l1clk), + .io_clk(rvclkhdr_5_io_clk), + .io_en(rvclkhdr_5_io_en), + .io_scan_mode(rvclkhdr_5_io_scan_mode) + ); + assign io_dbg_cmd_size = command_reg[21:20]; // @[dbg.scala 329:19] + assign io_dbg_core_rst_l = ~temp[1]; // @[dbg.scala 100:21] + assign io_dbg_halt_req = _T_309 ? _T_325 : _GEN_38; // @[dbg.scala 261:19 dbg.scala 267:23 dbg.scala 272:23 dbg.scala 283:23 dbg.scala 288:23 dbg.scala 293:23 dbg.scala 300:23 dbg.scala 305:23] + assign io_dbg_resume_req = _T_309 ? 1'h0 : _GEN_41; // @[dbg.scala 262:21 dbg.scala 282:25] + assign io_dmi_reg_rdata = _T_481; // @[dbg.scala 320:20] + assign io_sb_axi_aw_valid = _T_573 | _T_574; // @[dbg.scala 407:22] + assign io_sb_axi_aw_bits_id = 1'h0; // @[dbg.scala 409:24] + assign io_sb_axi_aw_bits_addr = sbaddress0_reg; // @[dbg.scala 408:26] + assign io_sb_axi_aw_bits_region = sbaddress0_reg[31:28]; // @[dbg.scala 413:28] + assign io_sb_axi_aw_bits_len = 8'h0; // @[dbg.scala 414:25] + assign io_sb_axi_aw_bits_size = sbcs_reg[19:17]; // @[dbg.scala 410:26] + assign io_sb_axi_aw_bits_burst = 2'h1; // @[dbg.scala 415:27] + assign io_sb_axi_aw_bits_lock = 1'h0; // @[dbg.scala 417:26] + assign io_sb_axi_aw_bits_cache = 4'hf; // @[dbg.scala 412:27] + assign io_sb_axi_aw_bits_prot = 3'h0; // @[dbg.scala 411:26] + assign io_sb_axi_aw_bits_qos = 4'h0; // @[dbg.scala 416:25] + assign io_sb_axi_w_valid = _T_573 | _T_580; // @[dbg.scala 418:21] + assign io_sb_axi_w_bits_data = _T_608 | _T_616; // @[dbg.scala 419:25] + assign io_sb_axi_w_bits_strb = _T_648[7:0]; // @[dbg.scala 422:25] + assign io_sb_axi_w_bits_last = 1'h1; // @[dbg.scala 427:25] + assign io_sb_axi_b_ready = 1'h1; // @[dbg.scala 439:21] + assign io_sb_axi_ar_valid = sb_state == 4'h3; // @[dbg.scala 428:22] + assign io_sb_axi_ar_bits_id = 1'h0; // @[dbg.scala 430:24] + assign io_sb_axi_ar_bits_addr = sbaddress0_reg; // @[dbg.scala 429:26] + assign io_sb_axi_ar_bits_region = sbaddress0_reg[31:28]; // @[dbg.scala 434:28] + assign io_sb_axi_ar_bits_len = 8'h0; // @[dbg.scala 435:25] + assign io_sb_axi_ar_bits_size = sbcs_reg[19:17]; // @[dbg.scala 431:26] + assign io_sb_axi_ar_bits_burst = 2'h1; // @[dbg.scala 436:27] + assign io_sb_axi_ar_bits_lock = 1'h0; // @[dbg.scala 438:26] + assign io_sb_axi_ar_bits_cache = 4'h0; // @[dbg.scala 433:27] + assign io_sb_axi_ar_bits_prot = 3'h0; // @[dbg.scala 432:26] + assign io_sb_axi_ar_bits_qos = 4'h0; // @[dbg.scala 437:25] + assign io_sb_axi_r_ready = 1'h1; // @[dbg.scala 440:21] + assign io_dbg_dec_dbg_ib_dbg_cmd_valid = _T_494 & io_dbg_dma_io_dma_dbg_ready; // @[dbg.scala 326:35] + assign io_dbg_dec_dbg_ib_dbg_cmd_write = command_reg[16]; // @[dbg.scala 327:35] + assign io_dbg_dec_dbg_ib_dbg_cmd_type = _T_483 ? 2'h2 : _T_503; // @[dbg.scala 328:34] + assign io_dbg_dec_dbg_ib_dbg_cmd_addr = _T_483 ? {{1'd0}, _T_485} : _T_487; // @[dbg.scala 324:34] + assign io_dbg_dec_dbg_dctl_dbg_cmd_wrdata = data0_reg[1:0]; // @[dbg.scala 325:38] + assign io_dbg_dma_dbg_ib_dbg_cmd_valid = io_dbg_dec_dbg_ib_dbg_cmd_valid; // @[dbg.scala 449:39] + assign io_dbg_dma_dbg_ib_dbg_cmd_write = io_dbg_dec_dbg_ib_dbg_cmd_write; // @[dbg.scala 450:39] + assign io_dbg_dma_dbg_ib_dbg_cmd_type = io_dbg_dec_dbg_ib_dbg_cmd_type; // @[dbg.scala 451:39] + assign io_dbg_dma_dbg_ib_dbg_cmd_addr = io_dbg_dec_dbg_ib_dbg_cmd_addr; // @[dbg.scala 447:39] + assign io_dbg_dma_dbg_dctl_dbg_cmd_wrdata = io_dbg_dec_dbg_dctl_dbg_cmd_wrdata; // @[dbg.scala 448:39] + assign io_dbg_dma_io_dbg_dma_bubble = _T_494 | _T_290; // @[dbg.scala 330:32] + assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_io_en = _T_3 | io_clk_override; // @[el2_lib.scala 485:16] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_1_io_en = _T_6 | io_clk_override; // @[el2_lib.scala 485:16] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_2_io_en = sbdata0wr_access | sbdata0_reg_wren1; // @[el2_lib.scala 511:17] + assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_3_io_en = sbdata1_reg_wren0 | sbdata0_reg_wren1; // @[el2_lib.scala 511:17] + assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_4_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_4_io_en = _T_123 | sbaddress0_reg_wren1; // @[el2_lib.scala 511:17] + assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_5_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_5_io_en = _T_303 & _T_278; // @[el2_lib.scala 511:17] + assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + dbg_state = _RAND_0[2:0]; + _RAND_1 = {1{`RANDOM}}; + dm_temp = _RAND_1[3:0]; + _RAND_2 = {1{`RANDOM}}; + dm_temp_0 = _RAND_2[0:0]; + _RAND_3 = {1{`RANDOM}}; + dmstatus_havereset = _RAND_3[0:0]; + _RAND_4 = {1{`RANDOM}}; + dmstatus_resumeack = _RAND_4[0:0]; + _RAND_5 = {1{`RANDOM}}; + dmstatus_halted = _RAND_5[0:0]; + _RAND_6 = {1{`RANDOM}}; + dmcontrol_wren_Q = _RAND_6[0:0]; + _RAND_7 = {1{`RANDOM}}; + abs_temp_12 = _RAND_7[0:0]; + _RAND_8 = {1{`RANDOM}}; + abs_temp_10_8 = _RAND_8[2:0]; + _RAND_9 = {1{`RANDOM}}; + sb_state = _RAND_9[3:0]; + _RAND_10 = {1{`RANDOM}}; + temp_sbcs_22 = _RAND_10[0:0]; + _RAND_11 = {1{`RANDOM}}; + temp_sbcs_21 = _RAND_11[0:0]; + _RAND_12 = {1{`RANDOM}}; + temp_sbcs_20 = _RAND_12[0:0]; + _RAND_13 = {1{`RANDOM}}; + temp_sbcs_19_15 = _RAND_13[4:0]; + _RAND_14 = {1{`RANDOM}}; + temp_sbcs_14_12 = _RAND_14[2:0]; + _RAND_15 = {1{`RANDOM}}; + sbaddress0_reg = _RAND_15[31:0]; + _RAND_16 = {1{`RANDOM}}; + sbdata0_reg = _RAND_16[31:0]; + _RAND_17 = {1{`RANDOM}}; + sbdata1_reg = _RAND_17[31:0]; + _RAND_18 = {1{`RANDOM}}; + data1_reg = _RAND_18[31:0]; + _RAND_19 = {1{`RANDOM}}; + command_reg = _RAND_19[31:0]; + _RAND_20 = {1{`RANDOM}}; + data0_reg = _RAND_20[31:0]; + _RAND_21 = {1{`RANDOM}}; + _T_481 = _RAND_21[31:0]; +`endif // RANDOMIZE_REG_INIT + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge rvclkhdr_io_l1clk) begin + if (_T_478) begin + dbg_state <= 3'h0; + end else if (dbg_state_en) begin + if (_T_309) begin + if (_T_363) begin + dbg_state <= 3'h2; + end else begin + dbg_state <= 3'h1; + end + end else if (_T_327) begin + if (temp[1]) begin + dbg_state <= 3'h0; + end else begin + dbg_state <= 3'h2; + end + end else if (_T_339) begin + if (_T_343) begin + if (_T_347) begin + dbg_state <= 3'h6; + end else begin + dbg_state <= 3'h3; + end + end else if (temp[31]) begin + dbg_state <= 3'h1; + end else begin + dbg_state <= 3'h0; + end + end else if (_T_377) begin + if (temp[1]) begin + dbg_state <= 3'h0; + end else if (_T_384) begin + dbg_state <= 3'h5; + end else begin + dbg_state <= 3'h4; + end + end else if (_T_394) begin + if (temp[1]) begin + dbg_state <= 3'h0; + end else begin + dbg_state <= 3'h5; + end + end else if (_T_405) begin + if (temp[1]) begin + dbg_state <= 3'h0; + end else begin + dbg_state <= 3'h2; + end + end else begin + dbg_state <= 3'h0; + end + end + if (_T_29) begin + dm_temp <= 4'h0; + end else if (dmcontrol_wren) begin + dm_temp <= _T_139; + end + if (io_dbg_rst_l) begin + dm_temp_0 <= 1'h0; + end else if (dmcontrol_wren) begin + dm_temp_0 <= io_dmi_reg_wdata[0]; + end + if (_T_29) begin + dmstatus_havereset <= 1'h0; + end else if (dmstatus_havereset_wren) begin + dmstatus_havereset <= _T_195; + end + if (_T_29) begin + dmstatus_resumeack <= 1'h0; + end else if (dmstatus_resumeack_wren) begin + dmstatus_resumeack <= _T_169; + end + if (_T_29) begin + dmstatus_halted <= 1'h0; + end else begin + dmstatus_halted <= _T_192; + end + if (_T_29) begin + dmcontrol_wren_Q <= 1'h0; + end else begin + dmcontrol_wren_Q <= dmcontrol_wren; + end + if (_T_29) begin + abs_temp_12 <= 1'h0; + end else if (abstractcs_busy_wren) begin + if (_T_309) begin + abs_temp_12 <= 1'h0; + end else if (_T_327) begin + abs_temp_12 <= 1'h0; + end else begin + abs_temp_12 <= _T_339; + end + end + if (_T_29) begin + abs_temp_10_8 <= 3'h0; + end else begin + abs_temp_10_8 <= abstractcs_error_din; + end + if (_T_29) begin + _T_481 <= 32'h0; + end else if (io_dmi_reg_en) begin + _T_481 <= dmi_reg_rdata_din; + end + end + always @(posedge rvclkhdr_1_io_l1clk) begin + if (_T_29) begin + sb_state <= 4'h0; + end else if (sb_state_en) begin + if (sbcs_sbbusy_din) begin + if (sbdata0wr_access) begin + sb_state <= 4'h2; + end else begin + sb_state <= 4'h1; + end + end else if (_T_525) begin + if (_T_530) begin + sb_state <= 4'h9; + end else begin + sb_state <= 4'h3; + end + end else if (_T_532) begin + if (_T_530) begin + sb_state <= 4'h9; + end else begin + sb_state <= 4'h4; + end + end else if (_T_539) begin + sb_state <= 4'h7; + end else if (_T_541) begin + if (_T_542) begin + sb_state <= 4'h8; + end else if (sb_bus_cmd_write_data) begin + sb_state <= 4'h5; + end else begin + sb_state <= 4'h6; + end + end else if (_T_547) begin + sb_state <= 4'h8; + end else if (_T_549) begin + sb_state <= 4'h8; + end else if (_T_551) begin + sb_state <= 4'h9; + end else if (_T_554) begin + sb_state <= 4'h9; + end else begin + sb_state <= 4'h0; + end + end + if (_T_29) begin + temp_sbcs_22 <= 1'h0; + end else if (sbcs_sbbusyerror_wren) begin + temp_sbcs_22 <= sbcs_sbbusyerror_din; + end + if (_T_29) begin + temp_sbcs_21 <= 1'h0; + end else if (sbcs_sbbusy_wren) begin + temp_sbcs_21 <= sbcs_sbbusy_din; + end + if (_T_29) begin + temp_sbcs_20 <= 1'h0; + end else if (sbcs_wren) begin + temp_sbcs_20 <= io_dmi_reg_wdata[20]; + end + if (_T_29) begin + temp_sbcs_19_15 <= 5'h0; + end else if (sbcs_wren) begin + temp_sbcs_19_15 <= io_dmi_reg_wdata[19:15]; + end + if (_T_29) begin + temp_sbcs_14_12 <= 3'h0; + end else if (sbcs_sberror_wren) begin + if (sbcs_sbbusy_din) begin + temp_sbcs_14_12 <= _T_524; + end else if (_T_525) begin + if (sbcs_unaligned) begin + temp_sbcs_14_12 <= 3'h3; + end else begin + temp_sbcs_14_12 <= 3'h4; + end + end else if (_T_532) begin + if (sbcs_unaligned) begin + temp_sbcs_14_12 <= 3'h3; + end else begin + temp_sbcs_14_12 <= 3'h4; + end + end else if (_T_539) begin + temp_sbcs_14_12 <= 3'h0; + end else if (_T_541) begin + temp_sbcs_14_12 <= 3'h0; + end else if (_T_547) begin + temp_sbcs_14_12 <= 3'h0; + end else if (_T_549) begin + temp_sbcs_14_12 <= 3'h0; + end else if (_T_551) begin + temp_sbcs_14_12 <= 3'h2; + end else if (_T_554) begin + temp_sbcs_14_12 <= 3'h2; + end else begin + temp_sbcs_14_12 <= 3'h0; + end + end + end + always @(posedge rvclkhdr_4_io_l1clk) begin + if (_T_29) begin + sbaddress0_reg <= 32'h0; + end else begin + sbaddress0_reg <= sbaddress0_reg_din; + end + end + always @(posedge rvclkhdr_2_io_l1clk) begin + if (_T_29) begin + sbdata0_reg <= 32'h0; + end else begin + sbdata0_reg <= sbdata0_din; + end + end + always @(posedge rvclkhdr_3_io_l1clk) begin + if (_T_29) begin + sbdata1_reg <= 32'h0; + end else begin + sbdata1_reg <= sbdata1_din; + end + end + always @(posedge rvclkhdr_5_io_l1clk) begin + if (_T_29) begin + data1_reg <= 32'h0; + end else begin + data1_reg <= data1_din; + end + end + always @(posedge clock) begin + if (_T_29) begin + command_reg <= 32'h0; + end else if (command_wren) begin + command_reg <= command_din; + end + if (_T_29) begin + data0_reg <= 32'h0; + end else if (data0_reg_wren) begin + data0_reg <= data0_din; + end + end +endmodule diff --git a/src/main/scala/dbg/dbg.scala b/src/main/scala/dbg/dbg.scala index 4da37c19..2eded292 100644 --- a/src/main/scala/dbg/dbg.scala +++ b/src/main/scala/dbg/dbg.scala @@ -449,4 +449,7 @@ class dbg extends Module with lib with RequireAsyncReset { io.dbg_dma.dbg_ib.dbg_cmd_valid := io.dbg_dec.dbg_ib.dbg_cmd_valid io.dbg_dma.dbg_ib.dbg_cmd_write := io.dbg_dec.dbg_ib.dbg_cmd_write io.dbg_dma.dbg_ib.dbg_cmd_type := io.dbg_dec.dbg_ib.dbg_cmd_type +} +object dbg_top extends App { + println((new chisel3.stage.ChiselStage).emitVerilog(new dbg())) } \ No newline at end of file diff --git a/src/main/scala/lsu/cipher.scala b/src/main/scala/lsu/cipher.scala new file mode 100644 index 00000000..04c39194 --- /dev/null +++ b/src/main/scala/lsu/cipher.scala @@ -0,0 +1,49 @@ +//package lsu +//import chisel3._ +//import chisel3.util._ +//import chisel3.experimental.{ChiselEnum, chiselName} +//import chisel3.util.ImplicitConversions.intToUInt +// +// +//@chiselName +//class aes extends Module{ +// val io = IO (new Bundle { +// val byteIn = Input(UInt(8.W)) +// val byteOut = Output(UInt(8.W)) +// }) +// def ROTL(x:Int,shift:Int) ={ +// val y = (x << shift) | (x >> (8 - shift)) +// y +// } +// io.byteOut := ROTL(io.byteIn,3) +// object aes extends App { +// println((new chisel3.stage.ChiselStage).emitVerilog(new aes())) +// } +//// def aes_sbox () ={ +//// +////} +///*#define ROTL8(x,shift) ((uint8_t) ((x) << (shift)) | ((x) >> (8 - (shift)))) +// +//void initialize_aes_sbox(uint8_t sbox[256]) { +// uint8_t p = 1, q = 1; +// +// /* loop invariant: p * q == 1 in the Galois field */ +// do { +// /* multiply p by 3 */ +// p = p ^ (p << 1) ^ (p & 0x80 ? 0x11B : 0); +// +// /* divide q by 3 (equals multiplication by 0xf6) */ +// q ^= q << 1; +// q ^= q << 2; +// q ^= q << 4; +// q ^= q & 0x80 ? 0x09 : 0; +// +// /* compute the affine transformation */ +// uint8_t xformed = q ^ ROTL8(q, 1) ^ ROTL8(q, 2) ^ ROTL8(q, 3) ^ ROTL8(q, 4); +// +// sbox[p] = xformed ^ 0x63; +//} while (p != 1); +// +// /* 0 is a special case since it has no inverse */ +// sbox[0] = 0x63;*/ +//} diff --git a/target/scala-2.12/classes/dbg/dbg_top$.class b/target/scala-2.12/classes/dbg/dbg_top$.class new file mode 100644 index 0000000000000000000000000000000000000000..145ec28139922ebf1447da8b904f30e94a081d19 GIT binary patch literal 3840 zcmbtXX?GJ<7=CV-qz!?VmKF+S50Zu@>>#NKZ9$4@K~t)TTBpfP8JNz5$pk1W;s)*; z?#oZ`92d3&=lD%N_@g{Nca~;KBjy~NGt0g6uFrkn=idJH_q{&=?7~k1@xtU(n%9J5 zl@d`1f%dc71ubo8=2ZIlzqI&ysIWcF}EU{N+4Wrh>-lFU~e-7<5I zW;+7n7z20XNif7jVnVa0$^xCIvsI5d$JWg$YIlYNbyIf+t%774Sue%BWf;tww$sxU zN1HTcI;)qRfl9F`ZEEN0k?Z$`j#Nz7)V5&4u9%KKEz<+mC0RI0=a~ci3AFU*4He4) zfyQLtIAQ2_hjA>!(ij@hBhcg})s^h4nO3vk4{tB9j{9?NUP2~mEpF8W?E*kVkS&^F|lJ0>z0`M z+`uM^`ma$8#xSH>W~EwfROdJa_ z+=`O6B<2%jXl9P$*i1=g!foW|7Eae!7}N|Sr#q71oyLnXynvUO^vi5btyD6| z2%WRNFuVMeeFa(v@t73olGC~~PBaXQ>m`d?#c&dA$^v>7%%tm@5<3N!(Q;9@ZO2F- zGEK|T++9MRr}-(IQOY{YCS+ba=xM&ic(f&|Fz6m(Rfrw{_{kKsxG2$^<0E#$#{|=G8#$Cl9G~KP2LwK2HaUID)SQaVN^kPc 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