commit a75dac982316a1d07ce09f48a963b9556e16bd29 Author: waleed-lm Date: Fri Sep 4 11:17:16 2020 +0500 Wrote dec_dec_ctl diff --git a/.idea/.gitignore b/.idea/.gitignore new file mode 100644 index 00000000..26d33521 --- /dev/null +++ b/.idea/.gitignore @@ -0,0 +1,3 @@ +# Default ignored files +/shelf/ +/workspace.xml diff --git a/.idea/.name b/.idea/.name new file mode 100644 index 00000000..ed8791e6 --- /dev/null +++ b/.idea/.name @@ -0,0 +1 @@ +chisel-module-template \ No newline at end of file diff --git a/.idea/codeStyles/Project.xml b/.idea/codeStyles/Project.xml new file mode 100644 index 00000000..919ce1f1 --- /dev/null +++ b/.idea/codeStyles/Project.xml @@ -0,0 +1,7 @@ + + + + + + \ No newline at end of file diff --git a/.idea/codeStyles/codeStyleConfig.xml b/.idea/codeStyles/codeStyleConfig.xml new file mode 100644 index 00000000..a55e7a17 --- /dev/null +++ b/.idea/codeStyles/codeStyleConfig.xml @@ -0,0 +1,5 @@ + + + + \ No newline at end of file diff --git a/.idea/compiler.xml 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a/.idea/libraries/sbt__org_json4s_json4s_scalap_2_12_3_6_8_jar.xml b/.idea/libraries/sbt__org_json4s_json4s_scalap_2_12_3_6_8_jar.xml new file mode 100644 index 00000000..75d91e6e --- /dev/null +++ b/.idea/libraries/sbt__org_json4s_json4s_scalap_2_12_3_6_8_jar.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + \ No newline at end of file diff --git a/.idea/libraries/sbt__org_portable_scala_portable_scala_reflect_2_12_0_1_0_jar.xml b/.idea/libraries/sbt__org_portable_scala_portable_scala_reflect_2_12_0_1_0_jar.xml new file mode 100644 index 00000000..c2cadfc1 --- /dev/null +++ b/.idea/libraries/sbt__org_portable_scala_portable_scala_reflect_2_12_0_1_0_jar.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + \ No newline at end of file diff --git a/.idea/libraries/sbt__org_scala_lang_modules_scala_jline_2_12_1_jar.xml b/.idea/libraries/sbt__org_scala_lang_modules_scala_jline_2_12_1_jar.xml new file mode 100644 index 00000000..86a8a20b --- /dev/null +++ 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a/.idea/misc.xml b/.idea/misc.xml new file mode 100644 index 00000000..894db656 --- /dev/null +++ b/.idea/misc.xml @@ -0,0 +1,4 @@ + + + + \ No newline at end of file diff --git a/.idea/modules.xml b/.idea/modules.xml new file mode 100644 index 00000000..4723e5e0 --- /dev/null +++ b/.idea/modules.xml @@ -0,0 +1,9 @@ + + + + + + + + + \ No newline at end of file diff --git a/.idea/modules/chisel-module-template-build.iml b/.idea/modules/chisel-module-template-build.iml new file mode 100644 index 00000000..0943f635 --- /dev/null +++ b/.idea/modules/chisel-module-template-build.iml @@ -0,0 +1,114 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/.idea/modules/chisel-module-template.iml b/.idea/modules/chisel-module-template.iml new file mode 100644 index 00000000..004cb04d --- /dev/null +++ b/.idea/modules/chisel-module-template.iml @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/.idea/sbt.xml b/.idea/sbt.xml new file mode 100644 index 00000000..742067a0 --- /dev/null +++ b/.idea/sbt.xml @@ -0,0 +1,17 @@ + + + + + + \ No newline at end of file diff --git a/.idea/scala_compiler.xml b/.idea/scala_compiler.xml new file mode 100644 index 00000000..d400f5af --- /dev/null +++ b/.idea/scala_compiler.xml @@ -0,0 +1,14 @@ + + + + + + + + + + + + + + \ No newline at end of file diff --git a/InoutPort.v b/InoutPort.v new file mode 100644 index 00000000..6808ea63 --- /dev/null +++ b/InoutPort.v @@ -0,0 +1,9 @@ + +module InoutPort( inout [15:0] a, + input [15:0] b, + input sel, + output [15:0] c); + assign a = sel ? 'bz : b; + assign c = sel ? a : 'bz; +endmodule + \ No newline at end of file diff --git a/MakeInout.anno.json b/MakeInout.anno.json new file mode 100644 index 00000000..f63b03d0 --- /dev/null +++ b/MakeInout.anno.json @@ -0,0 +1,24 @@ +[ + { + "class":"firrtl.EmitCircuitAnnotation", + "emitter":"firrtl.VerilogEmitter" + }, + { + "class":"firrtl.transforms.BlackBoxInlineAnno", + "target":"MakeInout.rvdff", + "name":"rvdff.v", + "text":"\nmodule InoutPort( input [15:0] in,\n input clk,\n input reset,\n output [15:0] out);\n always@(posedge clk or negedge reset)\n begin\n if(reset == 0)\n out <= 0;\n else\n out <= in\n end\nendmodule\n " + }, + { + "class":"firrtl.options.TargetDirAnnotation", + "directory":"." + }, + { + "class":"firrtl.options.OutputAnnotationFileAnnotation", + "file":"MakeInout" + }, + { + "class":"firrtl.transforms.BlackBoxTargetDirAnno", + "targetDir":"." + } +] \ No newline at end of file diff --git a/MakeInout.fir b/MakeInout.fir new file mode 100644 index 00000000..c892417e --- /dev/null +++ b/MakeInout.fir @@ -0,0 +1,26 @@ +;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10 +circuit MakeInout : + extmodule rvdff : + input in : UInt<16> + input clk : Clock + input reset : UInt<1> + output out : UInt<16> + + defname = rvdff + + + module MakeInout : + input clock : Clock + input reset : UInt<1> + output io : {flip in : UInt<16>, flip clk : Clock, flip reset : UInt<1>, out : UInt<16>} + + inst m of rvdff @[GCD.scala 40:17] + m.out is invalid + m.reset is invalid + m.clk is invalid + m.in is invalid + io.out <= m.out @[GCD.scala 42:8] + m.reset <= io.reset @[GCD.scala 42:8] + m.clk <= io.clk @[GCD.scala 42:8] + m.in <= io.in @[GCD.scala 42:8] + diff --git a/MakeInout.v b/MakeInout.v new file mode 100644 index 00000000..b6dea0a0 --- /dev/null +++ b/MakeInout.v @@ -0,0 +1,23 @@ +module MakeInout( + input clock, + input reset, + input [15:0] io_in, + input io_clk, + input io_reset, + output [15:0] io_out +); + wire [15:0] m_in; // @[GCD.scala 40:17] + wire m_clk; // @[GCD.scala 40:17] + wire m_reset; // @[GCD.scala 40:17] + wire [15:0] m_out; // @[GCD.scala 40:17] + rvdff m ( // @[GCD.scala 40:17] + .in(m_in), + .clk(m_clk), + .reset(m_reset), + .out(m_out) + ); + assign io_out = m_out; // @[GCD.scala 42:8] + assign m_in = io_in; // @[GCD.scala 42:8] + assign m_clk = io_clk; // @[GCD.scala 42:8] + assign m_reset = io_reset; // @[GCD.scala 42:8] +endmodule diff --git a/README.md b/README.md new file mode 100644 index 00000000..58d5d440 --- /dev/null +++ b/README.md @@ -0,0 +1,136 @@ +Chisel Project Template +======================= + +You've done the Chisel [tutorials](https://github.com/ucb-bar/chisel-tutorial), and now you +are ready to start your own chisel project. The following procedure should get you started +with a clean running [Chisel3](https://github.com/freechipsproject/chisel3) project. + +> More and more users are finding IntelliJ to be a powerful tool for Chisel coding. See the +[IntelliJ Installation Guide](https://github.com/ucb-bar/chisel-template/wiki/IntelliJ-Installation-Guide) for how to install it. + +## Make your own Chisel3 project +### How to get started +The first thing you want to do is clone this repo into a directory of your own. I'd recommend creating a chisel projects directory somewhere +```sh +mkdir ~/ChiselProjects +cd ~/ChiselProjects + +git clone https://github.com/ucb-bar/chisel-template.git MyChiselProject +cd MyChiselProject +``` +### Make your project into a fresh git repo +There may be more elegant way to do it, but the following works for me. **Note:** this project comes with a magnificent 339 line (at this writing) .gitignore file. + You may want to edit that first in case we missed something, whack away at it, or start it from scratch. + +#### Clear out the old git stuff +```sh +rm -rf .git +git init +git add .gitignore * +``` + +#### Rename project in build.sbt file +Use your favorite text editor to change the first line of the **build.sbt** file +(it ships as ```name := "chisel-module-template"```) to correspond +to your project.
+Perhaps as ```name := "my-chisel-project"``` + +#### Clean up the README.md file +Again use you editor of choice to make the README specific to your project. +Be sure to update (or delete) the License section and add a LICENSE file of your own. + +#### Commit your changes +``` +git commit -m 'Starting MyChiselProject' +``` +Connecting this up to github or some other remote host is an exercise left to the reader. + +### Did it work? +You should now have a project based on Chisel3 that can be run.
+So go for it, at the command line in the project root. +```sh +sbt 'testOnly gcd.GCDTester -- -z Basic' +``` +>This tells the test harness to only run the test in GCDTester that contains the word Basic +There are a number of other examples of ways to run tests in there, but we just want to see that +one works. + +You should see a whole bunch of output that ends with something like the following lines +``` +[info] [0.001] SEED 1540570744913 +test GCD Success: 168 tests passed in 1107 cycles in 0.067751 seconds 16339.24 Hz +[info] [0.050] RAN 1102 CYCLES PASSED +[info] GCDTester: +[info] GCD +[info] Basic test using Driver.execute +[info] - should be used as an alternative way to run specification +[info] using --backend-name verilator +[info] running with --is-verbose +[info] running with --generate-vcd-output on +[info] running with --generate-vcd-output off +[info] ScalaTest +[info] Run completed in 3 seconds, 184 milliseconds. +[info] Total number of tests run: 1 +[info] Suites: completed 1, aborted 0 +[info] Tests: succeeded 1, failed 0, canceled 0, ignored 0, pending 0 +[info] All tests passed. +[info] Passed: Total 1, Failed 0, Errors 0, Passed 1 +[success] Total time: 5 s, completed Oct 26, 2018 9:19:07 AM +``` +If you see the above then... + +### It worked! +You are ready to go. We have a few recommended practices and things to do. +* Use packages and following conventions for [structure](http://www.scala-sbt.org/0.13/docs/Directories.html) and [naming](http://docs.scala-lang.org/style/naming-conventions.html) +* Package names should be clearly reflected in the testing hierarchy +* Build tests for all your work. +* This template includes a dependency on the Chisel3 IOTesters, this is a reasonable starting point for most tests +* You can remove this dependency in the build.sbt file if necessary +* Change the name of your project in the build.sbt file +* Change your README.md + +There are [instructions for generating Verilog](https://github.com/freechipsproject/chisel3/wiki/Frequently-Asked-Questions#get-me-verilog) on the Chisel wiki. + +Some backends (verilator for example) produce VCD files by default, while other backends (firrtl and treadle) do not. +You can control the generation of VCD files with the `--generate-vcd-output` flag. + +To run the simulation and generate a VCD output file regardless of the backend: +```bash +sbt 'test:runMain gcd.GCDMain --generate-vcd-output on' +``` + +To run the simulation and suppress the generation of a VCD output file: +```bash +sbt 'test:runMain gcd.GCDMain --generate-vcd-output off' +``` + +## Development/Bug Fixes +This is the release version of chisel-template. If you have bug fixes or +changes you would like to see incorporated in this repo, please checkout +the master branch and submit pull requests against it. + +## License +This is free and unencumbered software released into the public domain. + +Anyone is free to copy, modify, publish, use, compile, sell, or +distribute this software, either in source code form or as a compiled +binary, for any purpose, commercial or non-commercial, and by any +means. + +In jurisdictions that recognize copyright laws, the author or authors +of this software dedicate any and all copyright interest in the +software to the public domain. We make this dedication for the benefit +of the public at large and to the detriment of our heirs and +successors. We intend this dedication to be an overt act of +relinquishment in perpetuity of all present and future rights to this +software under copyright law. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR +OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +OTHER DEALINGS IN THE SOFTWARE. + +For more information, please refer to diff --git a/RVCExpander.anno.json b/RVCExpander.anno.json new file mode 100644 index 00000000..a919f703 --- /dev/null +++ b/RVCExpander.anno.json @@ -0,0 +1,73 @@ +[ + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~RVCExpander|RVCExpander>io_out_rs2", + "sources":[ + "~RVCExpander|RVCExpander>io_in" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~RVCExpander|RVCExpander>io_out_rd", + "sources":[ + "~RVCExpander|RVCExpander>io_in" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~RVCExpander|RVCExpander>io_out_rs1", + "sources":[ + "~RVCExpander|RVCExpander>io_in" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~RVCExpander|RVCExpander>io_legal", + "sources":[ + "~RVCExpander|RVCExpander>io_in" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~RVCExpander|RVCExpander>io_out_bits", + "sources":[ + "~RVCExpander|RVCExpander>io_in" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~RVCExpander|RVCExpander>io_rvc", + "sources":[ + "~RVCExpander|RVCExpander>io_in" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~RVCExpander|RVCExpander>io_out_rs3", + "sources":[ + "~RVCExpander|RVCExpander>io_in" + ] + }, + { + "class":"logger.LogLevelAnnotation", + "globalLogLevel":{ + + } + }, + { + "class":"firrtl.EmitCircuitAnnotation", + "emitter":"firrtl.VerilogEmitter" + }, + { + "class":"firrtl.options.TargetDirAnnotation", + "directory":"." + }, + { + "class":"firrtl.options.OutputAnnotationFileAnnotation", + "file":"RVCExpander" + }, + { + "class":"firrtl.transforms.BlackBoxTargetDirAnno", + "targetDir":"." + } +] \ No newline at end of file diff --git a/RVCExpander.fir b/RVCExpander.fir new file mode 100644 index 00000000..15359549 --- /dev/null +++ b/RVCExpander.fir @@ -0,0 +1,1615 @@ +;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10 +circuit RVCExpander : + module RVCExpander : + input clock : Clock + input reset : UInt<1> + output io : {flip in : UInt<32>, out : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}, rvc : UInt<1>, legal : UInt<1>} + + node _T = bits(io.in, 1, 0) @[RVC.scala 201:20] + node _T_1 = neq(_T, UInt<2>("h03")) @[RVC.scala 201:26] + io.rvc <= _T_1 @[RVC.scala 201:12] + node _T_2 = bits(io.in, 12, 5) @[RVC.scala 58:22] + node _T_3 = orr(_T_2) @[RVC.scala 58:29] + node _T_4 = mux(_T_3, UInt<7>("h013"), UInt<7>("h01f")) @[RVC.scala 58:20] + node _T_5 = bits(io.in, 10, 7) @[RVC.scala 39:26] + node _T_6 = bits(io.in, 12, 11) @[RVC.scala 39:35] + node _T_7 = bits(io.in, 5, 5) @[RVC.scala 39:45] + node _T_8 = bits(io.in, 6, 6) @[RVC.scala 39:51] + node _T_9 = cat(_T_8, UInt<2>("h00")) @[Cat.scala 29:58] + node _T_10 = cat(_T_5, _T_6) @[Cat.scala 29:58] + node _T_11 = cat(_T_10, _T_7) @[Cat.scala 29:58] + node _T_12 = cat(_T_11, _T_9) @[Cat.scala 29:58] + node _T_13 = bits(io.in, 4, 2) @[RVC.scala 36:29] + node _T_14 = cat(UInt<2>("h01"), _T_13) @[Cat.scala 29:58] + node _T_15 = cat(_T_14, _T_4) @[Cat.scala 29:58] + node _T_16 = cat(_T_12, UInt<5>("h02")) @[Cat.scala 29:58] + node _T_17 = cat(_T_16, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_18 = cat(_T_17, _T_15) @[Cat.scala 29:58] + node _T_19 = bits(io.in, 4, 2) @[RVC.scala 36:29] + node _T_20 = cat(UInt<2>("h01"), _T_19) @[Cat.scala 29:58] + node _T_21 = bits(io.in, 4, 2) @[RVC.scala 36:29] + node _T_22 = cat(UInt<2>("h01"), _T_21) @[Cat.scala 29:58] + node _T_23 = bits(io.in, 31, 27) @[RVC.scala 25:101] + wire _T_24 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 26:19] + _T_24.bits <= _T_18 @[RVC.scala 27:14] + _T_24.rd <= _T_20 @[RVC.scala 28:12] + _T_24.rs1 <= UInt<5>("h02") @[RVC.scala 29:13] + _T_24.rs2 <= _T_22 @[RVC.scala 30:13] + _T_24.rs3 <= _T_23 @[RVC.scala 31:13] + node _T_25 = bits(io.in, 6, 5) @[RVC.scala 41:20] + node _T_26 = bits(io.in, 12, 10) @[RVC.scala 41:28] + node _T_27 = cat(_T_25, _T_26) @[Cat.scala 29:58] + node _T_28 = cat(_T_27, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_29 = bits(io.in, 9, 7) @[RVC.scala 35:29] + node _T_30 = cat(UInt<2>("h01"), _T_29) @[Cat.scala 29:58] + node _T_31 = bits(io.in, 4, 2) @[RVC.scala 36:29] + node _T_32 = cat(UInt<2>("h01"), _T_31) @[Cat.scala 29:58] + node _T_33 = cat(_T_32, UInt<7>("h07")) @[Cat.scala 29:58] + node _T_34 = cat(_T_28, _T_30) @[Cat.scala 29:58] + node _T_35 = cat(_T_34, UInt<3>("h03")) @[Cat.scala 29:58] + node _T_36 = cat(_T_35, _T_33) @[Cat.scala 29:58] + node _T_37 = bits(io.in, 4, 2) @[RVC.scala 36:29] + node _T_38 = cat(UInt<2>("h01"), _T_37) @[Cat.scala 29:58] + node _T_39 = bits(io.in, 9, 7) @[RVC.scala 35:29] + node _T_40 = cat(UInt<2>("h01"), _T_39) @[Cat.scala 29:58] + node _T_41 = bits(io.in, 4, 2) @[RVC.scala 36:29] + node _T_42 = cat(UInt<2>("h01"), _T_41) @[Cat.scala 29:58] + node _T_43 = bits(io.in, 31, 27) @[RVC.scala 25:101] + wire _T_44 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 26:19] + _T_44.bits <= _T_36 @[RVC.scala 27:14] + _T_44.rd <= _T_38 @[RVC.scala 28:12] + _T_44.rs1 <= _T_40 @[RVC.scala 29:13] + _T_44.rs2 <= _T_42 @[RVC.scala 30:13] + _T_44.rs3 <= _T_43 @[RVC.scala 31:13] + node _T_45 = bits(io.in, 5, 5) @[RVC.scala 40:20] + node _T_46 = bits(io.in, 12, 10) @[RVC.scala 40:26] + node _T_47 = bits(io.in, 6, 6) @[RVC.scala 40:36] + node _T_48 = cat(_T_47, UInt<2>("h00")) @[Cat.scala 29:58] + node _T_49 = cat(_T_45, _T_46) @[Cat.scala 29:58] + node _T_50 = cat(_T_49, _T_48) @[Cat.scala 29:58] + node _T_51 = bits(io.in, 9, 7) @[RVC.scala 35:29] + node _T_52 = cat(UInt<2>("h01"), _T_51) @[Cat.scala 29:58] + node _T_53 = bits(io.in, 4, 2) @[RVC.scala 36:29] + node _T_54 = cat(UInt<2>("h01"), _T_53) @[Cat.scala 29:58] + node _T_55 = cat(_T_54, UInt<7>("h03")) @[Cat.scala 29:58] + node _T_56 = cat(_T_50, _T_52) @[Cat.scala 29:58] + node _T_57 = cat(_T_56, UInt<3>("h02")) @[Cat.scala 29:58] + node _T_58 = cat(_T_57, _T_55) @[Cat.scala 29:58] + node _T_59 = bits(io.in, 4, 2) @[RVC.scala 36:29] + node _T_60 = cat(UInt<2>("h01"), _T_59) @[Cat.scala 29:58] + node _T_61 = bits(io.in, 9, 7) @[RVC.scala 35:29] + node _T_62 = cat(UInt<2>("h01"), _T_61) @[Cat.scala 29:58] + node _T_63 = bits(io.in, 4, 2) @[RVC.scala 36:29] + node _T_64 = cat(UInt<2>("h01"), _T_63) @[Cat.scala 29:58] + node _T_65 = bits(io.in, 31, 27) @[RVC.scala 25:101] + wire _T_66 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 26:19] + _T_66.bits <= _T_58 @[RVC.scala 27:14] + _T_66.rd <= _T_60 @[RVC.scala 28:12] + _T_66.rs1 <= _T_62 @[RVC.scala 29:13] + _T_66.rs2 <= _T_64 @[RVC.scala 30:13] + _T_66.rs3 <= _T_65 @[RVC.scala 31:13] + node _T_67 = bits(io.in, 5, 5) @[RVC.scala 40:20] + node _T_68 = bits(io.in, 12, 10) @[RVC.scala 40:26] + node _T_69 = bits(io.in, 6, 6) @[RVC.scala 40:36] + node _T_70 = cat(_T_69, UInt<2>("h00")) @[Cat.scala 29:58] + node _T_71 = cat(_T_67, _T_68) @[Cat.scala 29:58] + node _T_72 = cat(_T_71, _T_70) @[Cat.scala 29:58] + node _T_73 = bits(io.in, 9, 7) @[RVC.scala 35:29] + node _T_74 = cat(UInt<2>("h01"), _T_73) @[Cat.scala 29:58] + node _T_75 = bits(io.in, 4, 2) @[RVC.scala 36:29] + node _T_76 = cat(UInt<2>("h01"), _T_75) @[Cat.scala 29:58] + node _T_77 = cat(_T_76, UInt<7>("h07")) @[Cat.scala 29:58] + node _T_78 = cat(_T_72, _T_74) @[Cat.scala 29:58] + node _T_79 = cat(_T_78, UInt<3>("h02")) @[Cat.scala 29:58] + node _T_80 = cat(_T_79, _T_77) @[Cat.scala 29:58] + node _T_81 = bits(io.in, 4, 2) @[RVC.scala 36:29] + node _T_82 = cat(UInt<2>("h01"), _T_81) @[Cat.scala 29:58] + node _T_83 = bits(io.in, 9, 7) @[RVC.scala 35:29] + node _T_84 = cat(UInt<2>("h01"), _T_83) @[Cat.scala 29:58] + node _T_85 = bits(io.in, 4, 2) @[RVC.scala 36:29] + node _T_86 = cat(UInt<2>("h01"), _T_85) @[Cat.scala 29:58] + node _T_87 = bits(io.in, 31, 27) @[RVC.scala 25:101] + wire _T_88 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 26:19] + _T_88.bits <= _T_80 @[RVC.scala 27:14] + _T_88.rd <= _T_82 @[RVC.scala 28:12] + _T_88.rs1 <= _T_84 @[RVC.scala 29:13] + _T_88.rs2 <= _T_86 @[RVC.scala 30:13] + _T_88.rs3 <= _T_87 @[RVC.scala 31:13] + node _T_89 = bits(io.in, 5, 5) @[RVC.scala 40:20] + node _T_90 = bits(io.in, 12, 10) @[RVC.scala 40:26] + node _T_91 = bits(io.in, 6, 6) @[RVC.scala 40:36] + node _T_92 = cat(_T_91, UInt<2>("h00")) @[Cat.scala 29:58] + node _T_93 = cat(_T_89, _T_90) @[Cat.scala 29:58] + node _T_94 = cat(_T_93, _T_92) @[Cat.scala 29:58] + node _T_95 = shr(_T_94, 5) @[RVC.scala 68:32] + node _T_96 = bits(io.in, 4, 2) @[RVC.scala 36:29] + node _T_97 = cat(UInt<2>("h01"), _T_96) @[Cat.scala 29:58] + node _T_98 = bits(io.in, 9, 7) @[RVC.scala 35:29] + node _T_99 = cat(UInt<2>("h01"), _T_98) @[Cat.scala 29:58] + node _T_100 = bits(io.in, 5, 5) @[RVC.scala 40:20] + node _T_101 = bits(io.in, 12, 10) @[RVC.scala 40:26] + node _T_102 = bits(io.in, 6, 6) @[RVC.scala 40:36] + node _T_103 = cat(_T_102, UInt<2>("h00")) @[Cat.scala 29:58] + node _T_104 = cat(_T_100, _T_101) @[Cat.scala 29:58] + node _T_105 = cat(_T_104, _T_103) @[Cat.scala 29:58] + node _T_106 = bits(_T_105, 4, 0) @[RVC.scala 68:65] + node _T_107 = cat(UInt<3>("h02"), _T_106) @[Cat.scala 29:58] + node _T_108 = cat(_T_107, UInt<7>("h03f")) @[Cat.scala 29:58] + node _T_109 = cat(_T_95, _T_97) @[Cat.scala 29:58] + node _T_110 = cat(_T_109, _T_99) @[Cat.scala 29:58] + node _T_111 = cat(_T_110, _T_108) @[Cat.scala 29:58] + node _T_112 = bits(io.in, 4, 2) @[RVC.scala 36:29] + node _T_113 = cat(UInt<2>("h01"), _T_112) @[Cat.scala 29:58] + node _T_114 = bits(io.in, 9, 7) @[RVC.scala 35:29] + node _T_115 = cat(UInt<2>("h01"), _T_114) @[Cat.scala 29:58] + node _T_116 = bits(io.in, 4, 2) @[RVC.scala 36:29] + node _T_117 = cat(UInt<2>("h01"), _T_116) @[Cat.scala 29:58] + node _T_118 = bits(io.in, 31, 27) @[RVC.scala 25:101] + wire _T_119 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 26:19] + _T_119.bits <= _T_111 @[RVC.scala 27:14] + _T_119.rd <= _T_113 @[RVC.scala 28:12] + _T_119.rs1 <= _T_115 @[RVC.scala 29:13] + _T_119.rs2 <= _T_117 @[RVC.scala 30:13] + _T_119.rs3 <= _T_118 @[RVC.scala 31:13] + node _T_120 = bits(io.in, 6, 5) @[RVC.scala 41:20] + node _T_121 = bits(io.in, 12, 10) @[RVC.scala 41:28] + node _T_122 = cat(_T_120, _T_121) @[Cat.scala 29:58] + node _T_123 = cat(_T_122, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_124 = shr(_T_123, 5) @[RVC.scala 71:30] + node _T_125 = bits(io.in, 4, 2) @[RVC.scala 36:29] + node _T_126 = cat(UInt<2>("h01"), _T_125) @[Cat.scala 29:58] + node _T_127 = bits(io.in, 9, 7) @[RVC.scala 35:29] + node _T_128 = cat(UInt<2>("h01"), _T_127) @[Cat.scala 29:58] + node _T_129 = bits(io.in, 6, 5) @[RVC.scala 41:20] + node _T_130 = bits(io.in, 12, 10) @[RVC.scala 41:28] + node _T_131 = cat(_T_129, _T_130) @[Cat.scala 29:58] + node _T_132 = cat(_T_131, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_133 = bits(_T_132, 4, 0) @[RVC.scala 71:63] + node _T_134 = cat(UInt<3>("h03"), _T_133) @[Cat.scala 29:58] + node _T_135 = cat(_T_134, UInt<7>("h027")) @[Cat.scala 29:58] + node _T_136 = cat(_T_124, _T_126) @[Cat.scala 29:58] + node _T_137 = cat(_T_136, _T_128) @[Cat.scala 29:58] + node _T_138 = cat(_T_137, _T_135) @[Cat.scala 29:58] + node _T_139 = bits(io.in, 4, 2) @[RVC.scala 36:29] + node _T_140 = cat(UInt<2>("h01"), _T_139) @[Cat.scala 29:58] + node _T_141 = bits(io.in, 9, 7) @[RVC.scala 35:29] + node _T_142 = cat(UInt<2>("h01"), _T_141) @[Cat.scala 29:58] + node _T_143 = bits(io.in, 4, 2) @[RVC.scala 36:29] + node _T_144 = cat(UInt<2>("h01"), _T_143) @[Cat.scala 29:58] + node _T_145 = bits(io.in, 31, 27) @[RVC.scala 25:101] + wire _T_146 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 26:19] + _T_146.bits <= _T_138 @[RVC.scala 27:14] + _T_146.rd <= _T_140 @[RVC.scala 28:12] + _T_146.rs1 <= _T_142 @[RVC.scala 29:13] + _T_146.rs2 <= _T_144 @[RVC.scala 30:13] + _T_146.rs3 <= _T_145 @[RVC.scala 31:13] + node _T_147 = bits(io.in, 5, 5) @[RVC.scala 40:20] + node _T_148 = bits(io.in, 12, 10) @[RVC.scala 40:26] + node _T_149 = bits(io.in, 6, 6) @[RVC.scala 40:36] + node _T_150 = cat(_T_149, UInt<2>("h00")) @[Cat.scala 29:58] + node _T_151 = cat(_T_147, _T_148) @[Cat.scala 29:58] + node _T_152 = cat(_T_151, _T_150) @[Cat.scala 29:58] + node _T_153 = shr(_T_152, 5) @[RVC.scala 70:29] + node _T_154 = bits(io.in, 4, 2) @[RVC.scala 36:29] + node _T_155 = cat(UInt<2>("h01"), _T_154) @[Cat.scala 29:58] + node _T_156 = bits(io.in, 9, 7) @[RVC.scala 35:29] + node _T_157 = cat(UInt<2>("h01"), _T_156) @[Cat.scala 29:58] + node _T_158 = bits(io.in, 5, 5) @[RVC.scala 40:20] + node _T_159 = bits(io.in, 12, 10) @[RVC.scala 40:26] + node _T_160 = bits(io.in, 6, 6) @[RVC.scala 40:36] + node _T_161 = cat(_T_160, UInt<2>("h00")) @[Cat.scala 29:58] + node _T_162 = cat(_T_158, _T_159) @[Cat.scala 29:58] + node _T_163 = cat(_T_162, _T_161) @[Cat.scala 29:58] + node _T_164 = bits(_T_163, 4, 0) @[RVC.scala 70:62] + node _T_165 = cat(UInt<3>("h02"), _T_164) @[Cat.scala 29:58] + node _T_166 = cat(_T_165, UInt<7>("h023")) @[Cat.scala 29:58] + node _T_167 = cat(_T_153, _T_155) @[Cat.scala 29:58] + node _T_168 = cat(_T_167, _T_157) @[Cat.scala 29:58] + node _T_169 = cat(_T_168, _T_166) @[Cat.scala 29:58] + node _T_170 = bits(io.in, 4, 2) @[RVC.scala 36:29] + node _T_171 = cat(UInt<2>("h01"), _T_170) @[Cat.scala 29:58] + node _T_172 = bits(io.in, 9, 7) @[RVC.scala 35:29] + node _T_173 = cat(UInt<2>("h01"), _T_172) @[Cat.scala 29:58] + node _T_174 = bits(io.in, 4, 2) @[RVC.scala 36:29] + node _T_175 = cat(UInt<2>("h01"), _T_174) @[Cat.scala 29:58] + node _T_176 = bits(io.in, 31, 27) @[RVC.scala 25:101] + wire _T_177 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 26:19] + _T_177.bits <= _T_169 @[RVC.scala 27:14] + _T_177.rd <= _T_171 @[RVC.scala 28:12] + _T_177.rs1 <= _T_173 @[RVC.scala 29:13] + _T_177.rs2 <= _T_175 @[RVC.scala 30:13] + _T_177.rs3 <= _T_176 @[RVC.scala 31:13] + node _T_178 = bits(io.in, 5, 5) @[RVC.scala 40:20] + node _T_179 = bits(io.in, 12, 10) @[RVC.scala 40:26] + node _T_180 = bits(io.in, 6, 6) @[RVC.scala 40:36] + node _T_181 = cat(_T_180, UInt<2>("h00")) @[Cat.scala 29:58] + node _T_182 = cat(_T_178, _T_179) @[Cat.scala 29:58] + node _T_183 = cat(_T_182, _T_181) @[Cat.scala 29:58] + node _T_184 = shr(_T_183, 5) @[RVC.scala 73:38] + node _T_185 = bits(io.in, 4, 2) @[RVC.scala 36:29] + node _T_186 = cat(UInt<2>("h01"), _T_185) @[Cat.scala 29:58] + node _T_187 = bits(io.in, 9, 7) @[RVC.scala 35:29] + node _T_188 = cat(UInt<2>("h01"), _T_187) @[Cat.scala 29:58] + node _T_189 = bits(io.in, 5, 5) @[RVC.scala 40:20] + node _T_190 = bits(io.in, 12, 10) @[RVC.scala 40:26] + node _T_191 = bits(io.in, 6, 6) @[RVC.scala 40:36] + node _T_192 = cat(_T_191, UInt<2>("h00")) @[Cat.scala 29:58] + node _T_193 = cat(_T_189, _T_190) @[Cat.scala 29:58] + node _T_194 = cat(_T_193, _T_192) @[Cat.scala 29:58] + node _T_195 = bits(_T_194, 4, 0) @[RVC.scala 73:71] + node _T_196 = cat(UInt<3>("h02"), _T_195) @[Cat.scala 29:58] + node _T_197 = cat(_T_196, UInt<7>("h027")) @[Cat.scala 29:58] + node _T_198 = cat(_T_184, _T_186) @[Cat.scala 29:58] + node _T_199 = cat(_T_198, _T_188) @[Cat.scala 29:58] + node _T_200 = cat(_T_199, _T_197) @[Cat.scala 29:58] + node _T_201 = bits(io.in, 4, 2) @[RVC.scala 36:29] + node _T_202 = cat(UInt<2>("h01"), _T_201) @[Cat.scala 29:58] + node _T_203 = bits(io.in, 9, 7) @[RVC.scala 35:29] + node _T_204 = cat(UInt<2>("h01"), _T_203) @[Cat.scala 29:58] + node _T_205 = bits(io.in, 4, 2) @[RVC.scala 36:29] + node _T_206 = cat(UInt<2>("h01"), _T_205) @[Cat.scala 29:58] + node _T_207 = bits(io.in, 31, 27) @[RVC.scala 25:101] + wire _T_208 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 26:19] + _T_208.bits <= _T_200 @[RVC.scala 27:14] + _T_208.rd <= _T_202 @[RVC.scala 28:12] + _T_208.rs1 <= _T_204 @[RVC.scala 29:13] + _T_208.rs2 <= _T_206 @[RVC.scala 30:13] + _T_208.rs3 <= _T_207 @[RVC.scala 31:13] + node _T_209 = bits(io.in, 12, 12) @[RVC.scala 48:30] + node _T_210 = bits(_T_209, 0, 0) @[Bitwise.scala 72:15] + node _T_211 = mux(_T_210, UInt<7>("h07f"), UInt<7>("h00")) @[Bitwise.scala 72:12] + node _T_212 = bits(io.in, 6, 2) @[RVC.scala 48:38] + node _T_213 = cat(_T_211, _T_212) @[Cat.scala 29:58] + node _T_214 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_215 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_216 = cat(_T_215, UInt<7>("h013")) @[Cat.scala 29:58] + node _T_217 = cat(_T_213, _T_214) @[Cat.scala 29:58] + node _T_218 = cat(_T_217, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_219 = cat(_T_218, _T_216) @[Cat.scala 29:58] + node _T_220 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_221 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_222 = bits(io.in, 4, 2) @[RVC.scala 36:29] + node _T_223 = cat(UInt<2>("h01"), _T_222) @[Cat.scala 29:58] + node _T_224 = bits(io.in, 31, 27) @[RVC.scala 25:101] + wire _T_225 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 26:19] + _T_225.bits <= _T_219 @[RVC.scala 27:14] + _T_225.rd <= _T_220 @[RVC.scala 28:12] + _T_225.rs1 <= _T_221 @[RVC.scala 29:13] + _T_225.rs2 <= _T_223 @[RVC.scala 30:13] + _T_225.rs3 <= _T_224 @[RVC.scala 31:13] + node _T_226 = bits(io.in, 12, 12) @[RVC.scala 49:28] + node _T_227 = bits(_T_226, 0, 0) @[Bitwise.scala 72:15] + node _T_228 = mux(_T_227, UInt<10>("h03ff"), UInt<10>("h00")) @[Bitwise.scala 72:12] + node _T_229 = bits(io.in, 8, 8) @[RVC.scala 49:36] + node _T_230 = bits(io.in, 10, 9) @[RVC.scala 49:42] + node _T_231 = bits(io.in, 6, 6) @[RVC.scala 49:51] + node _T_232 = bits(io.in, 7, 7) @[RVC.scala 49:57] + node _T_233 = bits(io.in, 2, 2) @[RVC.scala 49:63] + node _T_234 = bits(io.in, 11, 11) @[RVC.scala 49:69] + node _T_235 = bits(io.in, 5, 3) @[RVC.scala 49:76] + node _T_236 = cat(_T_235, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_237 = cat(_T_233, _T_234) @[Cat.scala 29:58] + node _T_238 = cat(_T_237, _T_236) @[Cat.scala 29:58] + node _T_239 = cat(_T_231, _T_232) @[Cat.scala 29:58] + node _T_240 = cat(_T_228, _T_229) @[Cat.scala 29:58] + node _T_241 = cat(_T_240, _T_230) @[Cat.scala 29:58] + node _T_242 = cat(_T_241, _T_239) @[Cat.scala 29:58] + node _T_243 = cat(_T_242, _T_238) @[Cat.scala 29:58] + node _T_244 = bits(_T_243, 20, 20) @[RVC.scala 86:36] + node _T_245 = bits(io.in, 12, 12) @[RVC.scala 49:28] + node _T_246 = bits(_T_245, 0, 0) @[Bitwise.scala 72:15] + node _T_247 = mux(_T_246, UInt<10>("h03ff"), UInt<10>("h00")) @[Bitwise.scala 72:12] + node _T_248 = bits(io.in, 8, 8) @[RVC.scala 49:36] + node _T_249 = bits(io.in, 10, 9) @[RVC.scala 49:42] + node _T_250 = bits(io.in, 6, 6) @[RVC.scala 49:51] + node _T_251 = bits(io.in, 7, 7) @[RVC.scala 49:57] + node _T_252 = bits(io.in, 2, 2) @[RVC.scala 49:63] + node _T_253 = bits(io.in, 11, 11) @[RVC.scala 49:69] + node _T_254 = bits(io.in, 5, 3) @[RVC.scala 49:76] + node _T_255 = cat(_T_254, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_256 = cat(_T_252, _T_253) @[Cat.scala 29:58] + node _T_257 = cat(_T_256, _T_255) @[Cat.scala 29:58] + node _T_258 = cat(_T_250, _T_251) @[Cat.scala 29:58] + node _T_259 = cat(_T_247, _T_248) @[Cat.scala 29:58] + node _T_260 = cat(_T_259, _T_249) @[Cat.scala 29:58] + node _T_261 = cat(_T_260, _T_258) @[Cat.scala 29:58] + node _T_262 = cat(_T_261, _T_257) @[Cat.scala 29:58] + node _T_263 = bits(_T_262, 10, 1) @[RVC.scala 86:46] + node _T_264 = bits(io.in, 12, 12) @[RVC.scala 49:28] + node _T_265 = bits(_T_264, 0, 0) @[Bitwise.scala 72:15] + node _T_266 = mux(_T_265, UInt<10>("h03ff"), UInt<10>("h00")) @[Bitwise.scala 72:12] + node _T_267 = bits(io.in, 8, 8) @[RVC.scala 49:36] + node _T_268 = bits(io.in, 10, 9) @[RVC.scala 49:42] + node _T_269 = bits(io.in, 6, 6) @[RVC.scala 49:51] + node _T_270 = bits(io.in, 7, 7) @[RVC.scala 49:57] + node _T_271 = bits(io.in, 2, 2) @[RVC.scala 49:63] + node _T_272 = bits(io.in, 11, 11) @[RVC.scala 49:69] + node _T_273 = bits(io.in, 5, 3) @[RVC.scala 49:76] + node _T_274 = cat(_T_273, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_275 = cat(_T_271, _T_272) @[Cat.scala 29:58] + node _T_276 = cat(_T_275, _T_274) @[Cat.scala 29:58] + node _T_277 = cat(_T_269, _T_270) @[Cat.scala 29:58] + node _T_278 = cat(_T_266, _T_267) @[Cat.scala 29:58] + node _T_279 = cat(_T_278, _T_268) @[Cat.scala 29:58] + node _T_280 = cat(_T_279, _T_277) @[Cat.scala 29:58] + node _T_281 = cat(_T_280, _T_276) @[Cat.scala 29:58] + node _T_282 = bits(_T_281, 11, 11) @[RVC.scala 86:58] + node _T_283 = bits(io.in, 12, 12) @[RVC.scala 49:28] + node _T_284 = bits(_T_283, 0, 0) @[Bitwise.scala 72:15] + node _T_285 = mux(_T_284, UInt<10>("h03ff"), UInt<10>("h00")) @[Bitwise.scala 72:12] + node _T_286 = bits(io.in, 8, 8) @[RVC.scala 49:36] + node _T_287 = bits(io.in, 10, 9) @[RVC.scala 49:42] + node _T_288 = bits(io.in, 6, 6) @[RVC.scala 49:51] + node _T_289 = bits(io.in, 7, 7) @[RVC.scala 49:57] + node _T_290 = bits(io.in, 2, 2) @[RVC.scala 49:63] + node _T_291 = bits(io.in, 11, 11) @[RVC.scala 49:69] + node _T_292 = bits(io.in, 5, 3) @[RVC.scala 49:76] + node _T_293 = cat(_T_292, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_294 = cat(_T_290, _T_291) @[Cat.scala 29:58] + node _T_295 = cat(_T_294, _T_293) @[Cat.scala 29:58] + node _T_296 = cat(_T_288, _T_289) @[Cat.scala 29:58] + node _T_297 = cat(_T_285, _T_286) @[Cat.scala 29:58] + node _T_298 = cat(_T_297, _T_287) @[Cat.scala 29:58] + node _T_299 = cat(_T_298, _T_296) @[Cat.scala 29:58] + node _T_300 = cat(_T_299, _T_295) @[Cat.scala 29:58] + node _T_301 = bits(_T_300, 19, 12) @[RVC.scala 86:68] + node _T_302 = cat(_T_301, UInt<5>("h01")) @[Cat.scala 29:58] + node _T_303 = cat(_T_302, UInt<7>("h06f")) @[Cat.scala 29:58] + node _T_304 = cat(_T_244, _T_263) @[Cat.scala 29:58] + node _T_305 = cat(_T_304, _T_282) @[Cat.scala 29:58] + node _T_306 = cat(_T_305, _T_303) @[Cat.scala 29:58] + node _T_307 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_308 = bits(io.in, 4, 2) @[RVC.scala 36:29] + node _T_309 = cat(UInt<2>("h01"), _T_308) @[Cat.scala 29:58] + node _T_310 = bits(io.in, 31, 27) @[RVC.scala 25:101] + wire _T_311 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 26:19] + _T_311.bits <= _T_306 @[RVC.scala 27:14] + _T_311.rd <= UInt<5>("h01") @[RVC.scala 28:12] + _T_311.rs1 <= _T_307 @[RVC.scala 29:13] + _T_311.rs2 <= _T_309 @[RVC.scala 30:13] + _T_311.rs3 <= _T_310 @[RVC.scala 31:13] + node _T_312 = bits(io.in, 12, 12) @[RVC.scala 48:30] + node _T_313 = bits(_T_312, 0, 0) @[Bitwise.scala 72:15] + node _T_314 = mux(_T_313, UInt<7>("h07f"), UInt<7>("h00")) @[Bitwise.scala 72:12] + node _T_315 = bits(io.in, 6, 2) @[RVC.scala 48:38] + node _T_316 = cat(_T_314, _T_315) @[Cat.scala 29:58] + node _T_317 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_318 = cat(_T_317, UInt<7>("h013")) @[Cat.scala 29:58] + node _T_319 = cat(_T_316, UInt<5>("h00")) @[Cat.scala 29:58] + node _T_320 = cat(_T_319, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_321 = cat(_T_320, _T_318) @[Cat.scala 29:58] + node _T_322 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_323 = bits(io.in, 4, 2) @[RVC.scala 36:29] + node _T_324 = cat(UInt<2>("h01"), _T_323) @[Cat.scala 29:58] + node _T_325 = bits(io.in, 31, 27) @[RVC.scala 25:101] + wire _T_326 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 26:19] + _T_326.bits <= _T_321 @[RVC.scala 27:14] + _T_326.rd <= _T_322 @[RVC.scala 28:12] + _T_326.rs1 <= UInt<5>("h00") @[RVC.scala 29:13] + _T_326.rs2 <= _T_324 @[RVC.scala 30:13] + _T_326.rs3 <= _T_325 @[RVC.scala 31:13] + node _T_327 = bits(io.in, 12, 12) @[RVC.scala 48:30] + node _T_328 = bits(_T_327, 0, 0) @[Bitwise.scala 72:15] + node _T_329 = mux(_T_328, UInt<7>("h07f"), UInt<7>("h00")) @[Bitwise.scala 72:12] + node _T_330 = bits(io.in, 6, 2) @[RVC.scala 48:38] + node _T_331 = cat(_T_329, _T_330) @[Cat.scala 29:58] + node _T_332 = orr(_T_331) @[RVC.scala 95:29] + node _T_333 = mux(_T_332, UInt<7>("h037"), UInt<7>("h03f")) @[RVC.scala 95:20] + node _T_334 = bits(io.in, 12, 12) @[RVC.scala 46:30] + node _T_335 = bits(_T_334, 0, 0) @[Bitwise.scala 72:15] + node _T_336 = mux(_T_335, UInt<15>("h07fff"), UInt<15>("h00")) @[Bitwise.scala 72:12] + node _T_337 = bits(io.in, 6, 2) @[RVC.scala 46:38] + node _T_338 = cat(_T_336, _T_337) @[Cat.scala 29:58] + node _T_339 = cat(_T_338, UInt<12>("h00")) @[Cat.scala 29:58] + node _T_340 = bits(_T_339, 31, 12) @[RVC.scala 96:31] + node _T_341 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_342 = cat(_T_340, _T_341) @[Cat.scala 29:58] + node _T_343 = cat(_T_342, _T_333) @[Cat.scala 29:58] + node _T_344 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_345 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_346 = bits(io.in, 4, 2) @[RVC.scala 36:29] + node _T_347 = cat(UInt<2>("h01"), _T_346) @[Cat.scala 29:58] + node _T_348 = bits(io.in, 31, 27) @[RVC.scala 25:101] + wire _T_349 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 26:19] + _T_349.bits <= _T_343 @[RVC.scala 27:14] + _T_349.rd <= _T_344 @[RVC.scala 28:12] + _T_349.rs1 <= _T_345 @[RVC.scala 29:13] + _T_349.rs2 <= _T_347 @[RVC.scala 30:13] + _T_349.rs3 <= _T_348 @[RVC.scala 31:13] + node _T_350 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_351 = eq(_T_350, UInt<5>("h00")) @[RVC.scala 97:14] + node _T_352 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_353 = eq(_T_352, UInt<5>("h02")) @[RVC.scala 97:27] + node _T_354 = or(_T_351, _T_353) @[RVC.scala 97:21] + node _T_355 = bits(io.in, 12, 12) @[RVC.scala 48:30] + node _T_356 = bits(_T_355, 0, 0) @[Bitwise.scala 72:15] + node _T_357 = mux(_T_356, UInt<7>("h07f"), UInt<7>("h00")) @[Bitwise.scala 72:12] + node _T_358 = bits(io.in, 6, 2) @[RVC.scala 48:38] + node _T_359 = cat(_T_357, _T_358) @[Cat.scala 29:58] + node _T_360 = orr(_T_359) @[RVC.scala 91:29] + node _T_361 = mux(_T_360, UInt<7>("h013"), UInt<7>("h01f")) @[RVC.scala 91:20] + node _T_362 = bits(io.in, 12, 12) @[RVC.scala 47:34] + node _T_363 = bits(_T_362, 0, 0) @[Bitwise.scala 72:15] + node _T_364 = mux(_T_363, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_365 = bits(io.in, 4, 3) @[RVC.scala 47:42] + node _T_366 = bits(io.in, 5, 5) @[RVC.scala 47:50] + node _T_367 = bits(io.in, 2, 2) @[RVC.scala 47:56] + node _T_368 = bits(io.in, 6, 6) @[RVC.scala 47:62] + node _T_369 = cat(_T_367, _T_368) @[Cat.scala 29:58] + node _T_370 = cat(_T_369, UInt<4>("h00")) @[Cat.scala 29:58] + node _T_371 = cat(_T_364, _T_365) @[Cat.scala 29:58] + node _T_372 = cat(_T_371, _T_366) @[Cat.scala 29:58] + node _T_373 = cat(_T_372, _T_370) @[Cat.scala 29:58] + node _T_374 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_375 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_376 = cat(_T_375, _T_361) @[Cat.scala 29:58] + node _T_377 = cat(_T_373, _T_374) @[Cat.scala 29:58] + node _T_378 = cat(_T_377, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_379 = cat(_T_378, _T_376) @[Cat.scala 29:58] + node _T_380 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_381 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_382 = bits(io.in, 4, 2) @[RVC.scala 36:29] + node _T_383 = cat(UInt<2>("h01"), _T_382) @[Cat.scala 29:58] + node _T_384 = bits(io.in, 31, 27) @[RVC.scala 25:101] + wire _T_385 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 26:19] + _T_385.bits <= _T_379 @[RVC.scala 27:14] + _T_385.rd <= _T_380 @[RVC.scala 28:12] + _T_385.rs1 <= _T_381 @[RVC.scala 29:13] + _T_385.rs2 <= _T_383 @[RVC.scala 30:13] + _T_385.rs3 <= _T_384 @[RVC.scala 31:13] + node _T_386 = mux(_T_354, _T_385, _T_349) @[RVC.scala 97:10] + node _T_387 = bits(io.in, 12, 12) @[RVC.scala 51:20] + node _T_388 = bits(io.in, 6, 2) @[RVC.scala 51:27] + node _T_389 = cat(_T_387, _T_388) @[Cat.scala 29:58] + node _T_390 = bits(io.in, 9, 7) @[RVC.scala 35:29] + node _T_391 = cat(UInt<2>("h01"), _T_390) @[Cat.scala 29:58] + node _T_392 = bits(io.in, 9, 7) @[RVC.scala 35:29] + node _T_393 = cat(UInt<2>("h01"), _T_392) @[Cat.scala 29:58] + node _T_394 = cat(_T_393, UInt<7>("h013")) @[Cat.scala 29:58] + node _T_395 = cat(_T_389, _T_391) @[Cat.scala 29:58] + node _T_396 = cat(_T_395, UInt<3>("h05")) @[Cat.scala 29:58] + node _T_397 = cat(_T_396, _T_394) @[Cat.scala 29:58] + node _T_398 = bits(io.in, 12, 12) @[RVC.scala 51:20] + node _T_399 = bits(io.in, 6, 2) @[RVC.scala 51:27] + node _T_400 = cat(_T_398, _T_399) @[Cat.scala 29:58] + node _T_401 = bits(io.in, 9, 7) @[RVC.scala 35:29] + node _T_402 = cat(UInt<2>("h01"), _T_401) @[Cat.scala 29:58] + node _T_403 = bits(io.in, 9, 7) @[RVC.scala 35:29] + node _T_404 = cat(UInt<2>("h01"), _T_403) @[Cat.scala 29:58] + node _T_405 = cat(_T_404, UInt<7>("h013")) @[Cat.scala 29:58] + node _T_406 = cat(_T_400, _T_402) @[Cat.scala 29:58] + node _T_407 = cat(_T_406, UInt<3>("h05")) @[Cat.scala 29:58] + node _T_408 = cat(_T_407, _T_405) @[Cat.scala 29:58] + node _T_409 = or(_T_408, UInt<31>("h040000000")) @[RVC.scala 104:23] + node _T_410 = bits(io.in, 12, 12) @[RVC.scala 48:30] + node _T_411 = bits(_T_410, 0, 0) @[Bitwise.scala 72:15] + node _T_412 = mux(_T_411, UInt<7>("h07f"), UInt<7>("h00")) @[Bitwise.scala 72:12] + node _T_413 = bits(io.in, 6, 2) @[RVC.scala 48:38] + node _T_414 = cat(_T_412, _T_413) @[Cat.scala 29:58] + node _T_415 = bits(io.in, 9, 7) @[RVC.scala 35:29] + node _T_416 = cat(UInt<2>("h01"), _T_415) @[Cat.scala 29:58] + node _T_417 = bits(io.in, 9, 7) @[RVC.scala 35:29] + node _T_418 = cat(UInt<2>("h01"), _T_417) @[Cat.scala 29:58] + node _T_419 = cat(_T_418, UInt<7>("h013")) @[Cat.scala 29:58] + node _T_420 = cat(_T_414, _T_416) @[Cat.scala 29:58] + node _T_421 = cat(_T_420, UInt<3>("h07")) @[Cat.scala 29:58] + node _T_422 = cat(_T_421, _T_419) @[Cat.scala 29:58] + wire _T_423 : UInt<3>[8] @[RVC.scala 107:28] + _T_423[0] <= UInt<1>("h00") @[RVC.scala 107:28] + _T_423[1] <= UInt<3>("h04") @[RVC.scala 107:28] + _T_423[2] <= UInt<3>("h06") @[RVC.scala 107:28] + _T_423[3] <= UInt<3>("h07") @[RVC.scala 107:28] + _T_423[4] <= UInt<1>("h00") @[RVC.scala 107:28] + _T_423[5] <= UInt<1>("h00") @[RVC.scala 107:28] + _T_423[6] <= UInt<2>("h02") @[RVC.scala 107:28] + _T_423[7] <= UInt<2>("h03") @[RVC.scala 107:28] + node _T_424 = bits(io.in, 12, 12) @[RVC.scala 107:74] + node _T_425 = bits(io.in, 6, 5) @[RVC.scala 107:81] + node _T_426 = cat(_T_424, _T_425) @[Cat.scala 29:58] + node _T_427 = bits(io.in, 6, 5) @[RVC.scala 108:24] + node _T_428 = eq(_T_427, UInt<1>("h00")) @[RVC.scala 108:30] + node _T_429 = mux(_T_428, UInt<31>("h040000000"), UInt<1>("h00")) @[RVC.scala 108:22] + node _T_430 = bits(io.in, 12, 12) @[RVC.scala 109:24] + node _T_431 = mux(_T_430, UInt<7>("h03b"), UInt<7>("h033")) @[RVC.scala 109:22] + node _T_432 = bits(io.in, 4, 2) @[RVC.scala 36:29] + node _T_433 = cat(UInt<2>("h01"), _T_432) @[Cat.scala 29:58] + node _T_434 = bits(io.in, 9, 7) @[RVC.scala 35:29] + node _T_435 = cat(UInt<2>("h01"), _T_434) @[Cat.scala 29:58] + node _T_436 = bits(io.in, 9, 7) @[RVC.scala 35:29] + node _T_437 = cat(UInt<2>("h01"), _T_436) @[Cat.scala 29:58] + node _T_438 = cat(_T_437, _T_431) @[Cat.scala 29:58] + node _T_439 = cat(_T_433, _T_435) @[Cat.scala 29:58] + node _T_440 = cat(_T_439, _T_423[_T_426]) @[Cat.scala 29:58] + node _T_441 = cat(_T_440, _T_438) @[Cat.scala 29:58] + node _T_442 = or(_T_441, _T_429) @[RVC.scala 110:43] + wire _T_443 : UInt<32>[4] @[RVC.scala 112:19] + _T_443[0] <= _T_397 @[RVC.scala 112:19] + _T_443[1] <= _T_409 @[RVC.scala 112:19] + _T_443[2] <= _T_422 @[RVC.scala 112:19] + _T_443[3] <= _T_442 @[RVC.scala 112:19] + node _T_444 = bits(io.in, 11, 10) @[RVC.scala 112:46] + node _T_445 = bits(io.in, 9, 7) @[RVC.scala 35:29] + node _T_446 = cat(UInt<2>("h01"), _T_445) @[Cat.scala 29:58] + node _T_447 = bits(io.in, 9, 7) @[RVC.scala 35:29] + node _T_448 = cat(UInt<2>("h01"), _T_447) @[Cat.scala 29:58] + node _T_449 = bits(io.in, 4, 2) @[RVC.scala 36:29] + node _T_450 = cat(UInt<2>("h01"), _T_449) @[Cat.scala 29:58] + node _T_451 = bits(io.in, 31, 27) @[RVC.scala 25:101] + wire _T_452 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 26:19] + _T_452.bits <= _T_443[_T_444] @[RVC.scala 27:14] + _T_452.rd <= _T_446 @[RVC.scala 28:12] + _T_452.rs1 <= _T_448 @[RVC.scala 29:13] + _T_452.rs2 <= _T_450 @[RVC.scala 30:13] + _T_452.rs3 <= _T_451 @[RVC.scala 31:13] + node _T_453 = bits(io.in, 12, 12) @[RVC.scala 49:28] + node _T_454 = bits(_T_453, 0, 0) @[Bitwise.scala 72:15] + node _T_455 = mux(_T_454, UInt<10>("h03ff"), UInt<10>("h00")) @[Bitwise.scala 72:12] + node _T_456 = bits(io.in, 8, 8) @[RVC.scala 49:36] + node _T_457 = bits(io.in, 10, 9) @[RVC.scala 49:42] + node _T_458 = bits(io.in, 6, 6) @[RVC.scala 49:51] + node _T_459 = bits(io.in, 7, 7) @[RVC.scala 49:57] + node _T_460 = bits(io.in, 2, 2) @[RVC.scala 49:63] + node _T_461 = bits(io.in, 11, 11) @[RVC.scala 49:69] + node _T_462 = bits(io.in, 5, 3) @[RVC.scala 49:76] + node _T_463 = cat(_T_462, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_464 = cat(_T_460, _T_461) @[Cat.scala 29:58] + node _T_465 = cat(_T_464, _T_463) @[Cat.scala 29:58] + node _T_466 = cat(_T_458, _T_459) @[Cat.scala 29:58] + node _T_467 = cat(_T_455, _T_456) @[Cat.scala 29:58] + node _T_468 = cat(_T_467, _T_457) @[Cat.scala 29:58] + node _T_469 = cat(_T_468, _T_466) @[Cat.scala 29:58] + node _T_470 = cat(_T_469, _T_465) @[Cat.scala 29:58] + node _T_471 = bits(_T_470, 20, 20) @[RVC.scala 99:26] + node _T_472 = bits(io.in, 12, 12) @[RVC.scala 49:28] + node _T_473 = bits(_T_472, 0, 0) @[Bitwise.scala 72:15] + node _T_474 = mux(_T_473, UInt<10>("h03ff"), UInt<10>("h00")) @[Bitwise.scala 72:12] + node _T_475 = bits(io.in, 8, 8) @[RVC.scala 49:36] + node _T_476 = bits(io.in, 10, 9) @[RVC.scala 49:42] + node _T_477 = bits(io.in, 6, 6) @[RVC.scala 49:51] + node _T_478 = bits(io.in, 7, 7) @[RVC.scala 49:57] + node _T_479 = bits(io.in, 2, 2) @[RVC.scala 49:63] + node _T_480 = bits(io.in, 11, 11) @[RVC.scala 49:69] + node _T_481 = bits(io.in, 5, 3) @[RVC.scala 49:76] + node _T_482 = cat(_T_481, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_483 = cat(_T_479, _T_480) @[Cat.scala 29:58] + node _T_484 = cat(_T_483, _T_482) @[Cat.scala 29:58] + node _T_485 = cat(_T_477, _T_478) @[Cat.scala 29:58] + node _T_486 = cat(_T_474, _T_475) @[Cat.scala 29:58] + node _T_487 = cat(_T_486, _T_476) @[Cat.scala 29:58] + node _T_488 = cat(_T_487, _T_485) @[Cat.scala 29:58] + node _T_489 = cat(_T_488, _T_484) @[Cat.scala 29:58] + node _T_490 = bits(_T_489, 10, 1) @[RVC.scala 99:36] + node _T_491 = bits(io.in, 12, 12) @[RVC.scala 49:28] + node _T_492 = bits(_T_491, 0, 0) @[Bitwise.scala 72:15] + node _T_493 = mux(_T_492, UInt<10>("h03ff"), UInt<10>("h00")) @[Bitwise.scala 72:12] + node _T_494 = bits(io.in, 8, 8) @[RVC.scala 49:36] + node _T_495 = bits(io.in, 10, 9) @[RVC.scala 49:42] + node _T_496 = bits(io.in, 6, 6) @[RVC.scala 49:51] + node _T_497 = bits(io.in, 7, 7) @[RVC.scala 49:57] + node _T_498 = bits(io.in, 2, 2) @[RVC.scala 49:63] + node _T_499 = bits(io.in, 11, 11) @[RVC.scala 49:69] + node _T_500 = bits(io.in, 5, 3) @[RVC.scala 49:76] + node _T_501 = cat(_T_500, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_502 = cat(_T_498, _T_499) @[Cat.scala 29:58] + node _T_503 = cat(_T_502, _T_501) @[Cat.scala 29:58] + node _T_504 = cat(_T_496, _T_497) @[Cat.scala 29:58] + node _T_505 = cat(_T_493, _T_494) @[Cat.scala 29:58] + node _T_506 = cat(_T_505, _T_495) @[Cat.scala 29:58] + node _T_507 = cat(_T_506, _T_504) @[Cat.scala 29:58] + node _T_508 = cat(_T_507, _T_503) @[Cat.scala 29:58] + node _T_509 = bits(_T_508, 11, 11) @[RVC.scala 99:48] + node _T_510 = bits(io.in, 12, 12) @[RVC.scala 49:28] + node _T_511 = bits(_T_510, 0, 0) @[Bitwise.scala 72:15] + node _T_512 = mux(_T_511, UInt<10>("h03ff"), UInt<10>("h00")) @[Bitwise.scala 72:12] + node _T_513 = bits(io.in, 8, 8) @[RVC.scala 49:36] + node _T_514 = bits(io.in, 10, 9) @[RVC.scala 49:42] + node _T_515 = bits(io.in, 6, 6) @[RVC.scala 49:51] + node _T_516 = bits(io.in, 7, 7) @[RVC.scala 49:57] + node _T_517 = bits(io.in, 2, 2) @[RVC.scala 49:63] + node _T_518 = bits(io.in, 11, 11) @[RVC.scala 49:69] + node _T_519 = bits(io.in, 5, 3) @[RVC.scala 49:76] + node _T_520 = cat(_T_519, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_521 = cat(_T_517, _T_518) @[Cat.scala 29:58] + node _T_522 = cat(_T_521, _T_520) @[Cat.scala 29:58] + node _T_523 = cat(_T_515, _T_516) @[Cat.scala 29:58] + node _T_524 = cat(_T_512, _T_513) @[Cat.scala 29:58] + node _T_525 = cat(_T_524, _T_514) @[Cat.scala 29:58] + node _T_526 = cat(_T_525, _T_523) @[Cat.scala 29:58] + node _T_527 = cat(_T_526, _T_522) @[Cat.scala 29:58] + node _T_528 = bits(_T_527, 19, 12) @[RVC.scala 99:58] + node _T_529 = cat(_T_528, UInt<5>("h00")) @[Cat.scala 29:58] + node _T_530 = cat(_T_529, UInt<7>("h06f")) @[Cat.scala 29:58] + node _T_531 = cat(_T_471, _T_490) @[Cat.scala 29:58] + node _T_532 = cat(_T_531, _T_509) @[Cat.scala 29:58] + node _T_533 = cat(_T_532, _T_530) @[Cat.scala 29:58] + node _T_534 = bits(io.in, 9, 7) @[RVC.scala 35:29] + node _T_535 = cat(UInt<2>("h01"), _T_534) @[Cat.scala 29:58] + node _T_536 = bits(io.in, 4, 2) @[RVC.scala 36:29] + node _T_537 = cat(UInt<2>("h01"), _T_536) @[Cat.scala 29:58] + node _T_538 = bits(io.in, 31, 27) @[RVC.scala 25:101] + wire _T_539 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 26:19] + _T_539.bits <= _T_533 @[RVC.scala 27:14] + _T_539.rd <= UInt<5>("h00") @[RVC.scala 28:12] + _T_539.rs1 <= _T_535 @[RVC.scala 29:13] + _T_539.rs2 <= _T_537 @[RVC.scala 30:13] + _T_539.rs3 <= _T_538 @[RVC.scala 31:13] + node _T_540 = bits(io.in, 12, 12) @[RVC.scala 50:27] + node _T_541 = bits(_T_540, 0, 0) @[Bitwise.scala 72:15] + node _T_542 = mux(_T_541, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] + node _T_543 = bits(io.in, 6, 5) @[RVC.scala 50:35] + node _T_544 = bits(io.in, 2, 2) @[RVC.scala 50:43] + node _T_545 = bits(io.in, 11, 10) @[RVC.scala 50:49] + node _T_546 = bits(io.in, 4, 3) @[RVC.scala 50:59] + node _T_547 = cat(_T_545, _T_546) @[Cat.scala 29:58] + node _T_548 = cat(_T_547, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_549 = cat(_T_542, _T_543) @[Cat.scala 29:58] + node _T_550 = cat(_T_549, _T_544) @[Cat.scala 29:58] + node _T_551 = cat(_T_550, _T_548) @[Cat.scala 29:58] + node _T_552 = bits(_T_551, 12, 12) @[RVC.scala 100:29] + node _T_553 = bits(io.in, 12, 12) @[RVC.scala 50:27] + node _T_554 = bits(_T_553, 0, 0) @[Bitwise.scala 72:15] + node _T_555 = mux(_T_554, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] + node _T_556 = bits(io.in, 6, 5) @[RVC.scala 50:35] + node _T_557 = bits(io.in, 2, 2) @[RVC.scala 50:43] + node _T_558 = bits(io.in, 11, 10) @[RVC.scala 50:49] + node _T_559 = bits(io.in, 4, 3) @[RVC.scala 50:59] + node _T_560 = cat(_T_558, _T_559) @[Cat.scala 29:58] + node _T_561 = cat(_T_560, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_562 = cat(_T_555, _T_556) @[Cat.scala 29:58] + node _T_563 = cat(_T_562, _T_557) @[Cat.scala 29:58] + node _T_564 = cat(_T_563, _T_561) @[Cat.scala 29:58] + node _T_565 = bits(_T_564, 10, 5) @[RVC.scala 100:39] + node _T_566 = bits(io.in, 9, 7) @[RVC.scala 35:29] + node _T_567 = cat(UInt<2>("h01"), _T_566) @[Cat.scala 29:58] + node _T_568 = bits(io.in, 12, 12) @[RVC.scala 50:27] + node _T_569 = bits(_T_568, 0, 0) @[Bitwise.scala 72:15] + node _T_570 = mux(_T_569, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] + node _T_571 = bits(io.in, 6, 5) @[RVC.scala 50:35] + node _T_572 = bits(io.in, 2, 2) @[RVC.scala 50:43] + node _T_573 = bits(io.in, 11, 10) @[RVC.scala 50:49] + node _T_574 = bits(io.in, 4, 3) @[RVC.scala 50:59] + node _T_575 = cat(_T_573, _T_574) @[Cat.scala 29:58] + node _T_576 = cat(_T_575, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_577 = cat(_T_570, _T_571) @[Cat.scala 29:58] + node _T_578 = cat(_T_577, _T_572) @[Cat.scala 29:58] + node _T_579 = cat(_T_578, _T_576) @[Cat.scala 29:58] + node _T_580 = bits(_T_579, 4, 1) @[RVC.scala 100:71] + node _T_581 = bits(io.in, 12, 12) @[RVC.scala 50:27] + node _T_582 = bits(_T_581, 0, 0) @[Bitwise.scala 72:15] + node _T_583 = mux(_T_582, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] + node _T_584 = bits(io.in, 6, 5) @[RVC.scala 50:35] + node _T_585 = bits(io.in, 2, 2) @[RVC.scala 50:43] + node _T_586 = bits(io.in, 11, 10) @[RVC.scala 50:49] + node _T_587 = bits(io.in, 4, 3) @[RVC.scala 50:59] + node _T_588 = cat(_T_586, _T_587) @[Cat.scala 29:58] + node _T_589 = cat(_T_588, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_590 = cat(_T_583, _T_584) @[Cat.scala 29:58] + node _T_591 = cat(_T_590, _T_585) @[Cat.scala 29:58] + node _T_592 = cat(_T_591, _T_589) @[Cat.scala 29:58] + node _T_593 = bits(_T_592, 11, 11) @[RVC.scala 100:82] + node _T_594 = cat(_T_593, UInt<7>("h063")) @[Cat.scala 29:58] + node _T_595 = cat(UInt<3>("h00"), _T_580) @[Cat.scala 29:58] + node _T_596 = cat(_T_595, _T_594) @[Cat.scala 29:58] + node _T_597 = cat(UInt<5>("h00"), _T_567) @[Cat.scala 29:58] + node _T_598 = cat(_T_552, _T_565) @[Cat.scala 29:58] + node _T_599 = cat(_T_598, _T_597) @[Cat.scala 29:58] + node _T_600 = cat(_T_599, _T_596) @[Cat.scala 29:58] + node _T_601 = bits(io.in, 9, 7) @[RVC.scala 35:29] + node _T_602 = cat(UInt<2>("h01"), _T_601) @[Cat.scala 29:58] + node _T_603 = bits(io.in, 9, 7) @[RVC.scala 35:29] + node _T_604 = cat(UInt<2>("h01"), _T_603) @[Cat.scala 29:58] + node _T_605 = bits(io.in, 31, 27) @[RVC.scala 25:101] + wire _T_606 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 26:19] + _T_606.bits <= _T_600 @[RVC.scala 27:14] + _T_606.rd <= _T_602 @[RVC.scala 28:12] + _T_606.rs1 <= _T_604 @[RVC.scala 29:13] + _T_606.rs2 <= UInt<5>("h00") @[RVC.scala 30:13] + _T_606.rs3 <= _T_605 @[RVC.scala 31:13] + node _T_607 = bits(io.in, 12, 12) @[RVC.scala 50:27] + node _T_608 = bits(_T_607, 0, 0) @[Bitwise.scala 72:15] + node _T_609 = mux(_T_608, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] + node _T_610 = bits(io.in, 6, 5) @[RVC.scala 50:35] + node _T_611 = bits(io.in, 2, 2) @[RVC.scala 50:43] + node _T_612 = bits(io.in, 11, 10) @[RVC.scala 50:49] + node _T_613 = bits(io.in, 4, 3) @[RVC.scala 50:59] + node _T_614 = cat(_T_612, _T_613) @[Cat.scala 29:58] + node _T_615 = cat(_T_614, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_616 = cat(_T_609, _T_610) @[Cat.scala 29:58] + node _T_617 = cat(_T_616, _T_611) @[Cat.scala 29:58] + node _T_618 = cat(_T_617, _T_615) @[Cat.scala 29:58] + node _T_619 = bits(_T_618, 12, 12) @[RVC.scala 101:29] + node _T_620 = bits(io.in, 12, 12) @[RVC.scala 50:27] + node _T_621 = bits(_T_620, 0, 0) @[Bitwise.scala 72:15] + node _T_622 = mux(_T_621, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] + node _T_623 = bits(io.in, 6, 5) @[RVC.scala 50:35] + node _T_624 = bits(io.in, 2, 2) @[RVC.scala 50:43] + node _T_625 = bits(io.in, 11, 10) @[RVC.scala 50:49] + node _T_626 = bits(io.in, 4, 3) @[RVC.scala 50:59] + node _T_627 = cat(_T_625, _T_626) @[Cat.scala 29:58] + node _T_628 = cat(_T_627, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_629 = cat(_T_622, _T_623) @[Cat.scala 29:58] + node _T_630 = cat(_T_629, _T_624) @[Cat.scala 29:58] + node _T_631 = cat(_T_630, _T_628) @[Cat.scala 29:58] + node _T_632 = bits(_T_631, 10, 5) @[RVC.scala 101:39] + node _T_633 = bits(io.in, 9, 7) @[RVC.scala 35:29] + node _T_634 = cat(UInt<2>("h01"), _T_633) @[Cat.scala 29:58] + node _T_635 = bits(io.in, 12, 12) @[RVC.scala 50:27] + node _T_636 = bits(_T_635, 0, 0) @[Bitwise.scala 72:15] + node _T_637 = mux(_T_636, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] + node _T_638 = bits(io.in, 6, 5) @[RVC.scala 50:35] + node _T_639 = bits(io.in, 2, 2) @[RVC.scala 50:43] + node _T_640 = bits(io.in, 11, 10) @[RVC.scala 50:49] + node _T_641 = bits(io.in, 4, 3) @[RVC.scala 50:59] + node _T_642 = cat(_T_640, _T_641) @[Cat.scala 29:58] + node _T_643 = cat(_T_642, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_644 = cat(_T_637, _T_638) @[Cat.scala 29:58] + node _T_645 = cat(_T_644, _T_639) @[Cat.scala 29:58] + node _T_646 = cat(_T_645, _T_643) @[Cat.scala 29:58] + node _T_647 = bits(_T_646, 4, 1) @[RVC.scala 101:71] + node _T_648 = bits(io.in, 12, 12) @[RVC.scala 50:27] + node _T_649 = bits(_T_648, 0, 0) @[Bitwise.scala 72:15] + node _T_650 = mux(_T_649, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] + node _T_651 = bits(io.in, 6, 5) @[RVC.scala 50:35] + node _T_652 = bits(io.in, 2, 2) @[RVC.scala 50:43] + node _T_653 = bits(io.in, 11, 10) @[RVC.scala 50:49] + node _T_654 = bits(io.in, 4, 3) @[RVC.scala 50:59] + node _T_655 = cat(_T_653, _T_654) @[Cat.scala 29:58] + node _T_656 = cat(_T_655, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_657 = cat(_T_650, _T_651) @[Cat.scala 29:58] + node _T_658 = cat(_T_657, _T_652) @[Cat.scala 29:58] + node _T_659 = cat(_T_658, _T_656) @[Cat.scala 29:58] + node _T_660 = bits(_T_659, 11, 11) @[RVC.scala 101:82] + node _T_661 = cat(_T_660, UInt<7>("h063")) @[Cat.scala 29:58] + node _T_662 = cat(UInt<3>("h01"), _T_647) @[Cat.scala 29:58] + node _T_663 = cat(_T_662, _T_661) @[Cat.scala 29:58] + node _T_664 = cat(UInt<5>("h00"), _T_634) @[Cat.scala 29:58] + node _T_665 = cat(_T_619, _T_632) @[Cat.scala 29:58] + node _T_666 = cat(_T_665, _T_664) @[Cat.scala 29:58] + node _T_667 = cat(_T_666, _T_663) @[Cat.scala 29:58] + node _T_668 = bits(io.in, 9, 7) @[RVC.scala 35:29] + node _T_669 = cat(UInt<2>("h01"), _T_668) @[Cat.scala 29:58] + node _T_670 = bits(io.in, 31, 27) @[RVC.scala 25:101] + wire _T_671 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 26:19] + _T_671.bits <= _T_667 @[RVC.scala 27:14] + _T_671.rd <= UInt<5>("h00") @[RVC.scala 28:12] + _T_671.rs1 <= _T_669 @[RVC.scala 29:13] + _T_671.rs2 <= UInt<5>("h00") @[RVC.scala 30:13] + _T_671.rs3 <= _T_670 @[RVC.scala 31:13] + node _T_672 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_673 = orr(_T_672) @[RVC.scala 118:27] + node _T_674 = mux(_T_673, UInt<7>("h03"), UInt<7>("h01f")) @[RVC.scala 118:23] + node _T_675 = bits(io.in, 12, 12) @[RVC.scala 51:20] + node _T_676 = bits(io.in, 6, 2) @[RVC.scala 51:27] + node _T_677 = cat(_T_675, _T_676) @[Cat.scala 29:58] + node _T_678 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_679 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_680 = cat(_T_679, UInt<7>("h013")) @[Cat.scala 29:58] + node _T_681 = cat(_T_677, _T_678) @[Cat.scala 29:58] + node _T_682 = cat(_T_681, UInt<3>("h01")) @[Cat.scala 29:58] + node _T_683 = cat(_T_682, _T_680) @[Cat.scala 29:58] + node _T_684 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_685 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_686 = bits(io.in, 6, 2) @[RVC.scala 37:14] + node _T_687 = bits(io.in, 31, 27) @[RVC.scala 25:101] + wire _T_688 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 26:19] + _T_688.bits <= _T_683 @[RVC.scala 27:14] + _T_688.rd <= _T_684 @[RVC.scala 28:12] + _T_688.rs1 <= _T_685 @[RVC.scala 29:13] + _T_688.rs2 <= _T_686 @[RVC.scala 30:13] + _T_688.rs3 <= _T_687 @[RVC.scala 31:13] + node _T_689 = bits(io.in, 4, 2) @[RVC.scala 43:22] + node _T_690 = bits(io.in, 12, 12) @[RVC.scala 43:30] + node _T_691 = bits(io.in, 6, 5) @[RVC.scala 43:37] + node _T_692 = cat(_T_691, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_693 = cat(_T_689, _T_690) @[Cat.scala 29:58] + node _T_694 = cat(_T_693, _T_692) @[Cat.scala 29:58] + node _T_695 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_696 = cat(_T_695, UInt<7>("h07")) @[Cat.scala 29:58] + node _T_697 = cat(_T_694, UInt<5>("h02")) @[Cat.scala 29:58] + node _T_698 = cat(_T_697, UInt<3>("h03")) @[Cat.scala 29:58] + node _T_699 = cat(_T_698, _T_696) @[Cat.scala 29:58] + node _T_700 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_701 = bits(io.in, 6, 2) @[RVC.scala 37:14] + node _T_702 = bits(io.in, 31, 27) @[RVC.scala 25:101] + wire _T_703 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 26:19] + _T_703.bits <= _T_699 @[RVC.scala 27:14] + _T_703.rd <= _T_700 @[RVC.scala 28:12] + _T_703.rs1 <= UInt<5>("h02") @[RVC.scala 29:13] + _T_703.rs2 <= _T_701 @[RVC.scala 30:13] + _T_703.rs3 <= _T_702 @[RVC.scala 31:13] + node _T_704 = bits(io.in, 3, 2) @[RVC.scala 42:22] + node _T_705 = bits(io.in, 12, 12) @[RVC.scala 42:30] + node _T_706 = bits(io.in, 6, 4) @[RVC.scala 42:37] + node _T_707 = cat(_T_706, UInt<2>("h00")) @[Cat.scala 29:58] + node _T_708 = cat(_T_704, _T_705) @[Cat.scala 29:58] + node _T_709 = cat(_T_708, _T_707) @[Cat.scala 29:58] + node _T_710 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_711 = cat(_T_710, _T_674) @[Cat.scala 29:58] + node _T_712 = cat(_T_709, UInt<5>("h02")) @[Cat.scala 29:58] + node _T_713 = cat(_T_712, UInt<3>("h02")) @[Cat.scala 29:58] + node _T_714 = cat(_T_713, _T_711) @[Cat.scala 29:58] + node _T_715 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_716 = bits(io.in, 6, 2) @[RVC.scala 37:14] + node _T_717 = bits(io.in, 31, 27) @[RVC.scala 25:101] + wire _T_718 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 26:19] + _T_718.bits <= _T_714 @[RVC.scala 27:14] + _T_718.rd <= _T_715 @[RVC.scala 28:12] + _T_718.rs1 <= UInt<5>("h02") @[RVC.scala 29:13] + _T_718.rs2 <= _T_716 @[RVC.scala 30:13] + _T_718.rs3 <= _T_717 @[RVC.scala 31:13] + node _T_719 = bits(io.in, 3, 2) @[RVC.scala 42:22] + node _T_720 = bits(io.in, 12, 12) @[RVC.scala 42:30] + node _T_721 = bits(io.in, 6, 4) @[RVC.scala 42:37] + node _T_722 = cat(_T_721, UInt<2>("h00")) @[Cat.scala 29:58] + node _T_723 = cat(_T_719, _T_720) @[Cat.scala 29:58] + node _T_724 = cat(_T_723, _T_722) @[Cat.scala 29:58] + node _T_725 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_726 = cat(_T_725, UInt<7>("h07")) @[Cat.scala 29:58] + node _T_727 = cat(_T_724, UInt<5>("h02")) @[Cat.scala 29:58] + node _T_728 = cat(_T_727, UInt<3>("h02")) @[Cat.scala 29:58] + node _T_729 = cat(_T_728, _T_726) @[Cat.scala 29:58] + node _T_730 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_731 = bits(io.in, 6, 2) @[RVC.scala 37:14] + node _T_732 = bits(io.in, 31, 27) @[RVC.scala 25:101] + wire _T_733 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 26:19] + _T_733.bits <= _T_729 @[RVC.scala 27:14] + _T_733.rd <= _T_730 @[RVC.scala 28:12] + _T_733.rs1 <= UInt<5>("h02") @[RVC.scala 29:13] + _T_733.rs2 <= _T_731 @[RVC.scala 30:13] + _T_733.rs3 <= _T_732 @[RVC.scala 31:13] + node _T_734 = bits(io.in, 6, 2) @[RVC.scala 37:14] + node _T_735 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_736 = cat(_T_735, UInt<7>("h033")) @[Cat.scala 29:58] + node _T_737 = cat(_T_734, UInt<5>("h00")) @[Cat.scala 29:58] + node _T_738 = cat(_T_737, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_739 = cat(_T_738, _T_736) @[Cat.scala 29:58] + node _T_740 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_741 = bits(io.in, 6, 2) @[RVC.scala 37:14] + node _T_742 = bits(io.in, 31, 27) @[RVC.scala 25:101] + wire _T_743 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 26:19] + _T_743.bits <= _T_739 @[RVC.scala 27:14] + _T_743.rd <= _T_740 @[RVC.scala 28:12] + _T_743.rs1 <= UInt<5>("h00") @[RVC.scala 29:13] + _T_743.rs2 <= _T_741 @[RVC.scala 30:13] + _T_743.rs3 <= _T_742 @[RVC.scala 31:13] + node _T_744 = bits(io.in, 6, 2) @[RVC.scala 37:14] + node _T_745 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_746 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_747 = cat(_T_746, UInt<7>("h033")) @[Cat.scala 29:58] + node _T_748 = cat(_T_744, _T_745) @[Cat.scala 29:58] + node _T_749 = cat(_T_748, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_750 = cat(_T_749, _T_747) @[Cat.scala 29:58] + node _T_751 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_752 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_753 = bits(io.in, 6, 2) @[RVC.scala 37:14] + node _T_754 = bits(io.in, 31, 27) @[RVC.scala 25:101] + wire _T_755 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 26:19] + _T_755.bits <= _T_750 @[RVC.scala 27:14] + _T_755.rd <= _T_751 @[RVC.scala 28:12] + _T_755.rs1 <= _T_752 @[RVC.scala 29:13] + _T_755.rs2 <= _T_753 @[RVC.scala 30:13] + _T_755.rs3 <= _T_754 @[RVC.scala 31:13] + node _T_756 = bits(io.in, 6, 2) @[RVC.scala 37:14] + node _T_757 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_758 = cat(UInt<5>("h00"), UInt<7>("h067")) @[Cat.scala 29:58] + node _T_759 = cat(_T_756, _T_757) @[Cat.scala 29:58] + node _T_760 = cat(_T_759, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_761 = cat(_T_760, _T_758) @[Cat.scala 29:58] + node _T_762 = shr(_T_761, 7) @[RVC.scala 138:29] + node _T_763 = cat(_T_762, UInt<7>("h01f")) @[Cat.scala 29:58] + node _T_764 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_765 = orr(_T_764) @[RVC.scala 139:37] + node _T_766 = mux(_T_765, _T_761, _T_763) @[RVC.scala 139:33] + node _T_767 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_768 = bits(io.in, 6, 2) @[RVC.scala 37:14] + node _T_769 = bits(io.in, 31, 27) @[RVC.scala 25:101] + wire _T_770 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 26:19] + _T_770.bits <= _T_766 @[RVC.scala 27:14] + _T_770.rd <= UInt<5>("h00") @[RVC.scala 28:12] + _T_770.rs1 <= _T_767 @[RVC.scala 29:13] + _T_770.rs2 <= _T_768 @[RVC.scala 30:13] + _T_770.rs3 <= _T_769 @[RVC.scala 31:13] + node _T_771 = bits(io.in, 6, 2) @[RVC.scala 37:14] + node _T_772 = orr(_T_771) @[RVC.scala 140:27] + node _T_773 = mux(_T_772, _T_743, _T_770) @[RVC.scala 140:22] + node _T_774 = bits(io.in, 6, 2) @[RVC.scala 37:14] + node _T_775 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_776 = cat(UInt<5>("h01"), UInt<7>("h067")) @[Cat.scala 29:58] + node _T_777 = cat(_T_774, _T_775) @[Cat.scala 29:58] + node _T_778 = cat(_T_777, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_779 = cat(_T_778, _T_776) @[Cat.scala 29:58] + node _T_780 = shr(_T_761, 7) @[RVC.scala 142:27] + node _T_781 = cat(_T_780, UInt<7>("h073")) @[Cat.scala 29:58] + node _T_782 = or(_T_781, UInt<21>("h0100000")) @[RVC.scala 142:46] + node _T_783 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_784 = orr(_T_783) @[RVC.scala 143:37] + node _T_785 = mux(_T_784, _T_779, _T_782) @[RVC.scala 143:33] + node _T_786 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_787 = bits(io.in, 6, 2) @[RVC.scala 37:14] + node _T_788 = bits(io.in, 31, 27) @[RVC.scala 25:101] + wire _T_789 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 26:19] + _T_789.bits <= _T_785 @[RVC.scala 27:14] + _T_789.rd <= UInt<5>("h01") @[RVC.scala 28:12] + _T_789.rs1 <= _T_786 @[RVC.scala 29:13] + _T_789.rs2 <= _T_787 @[RVC.scala 30:13] + _T_789.rs3 <= _T_788 @[RVC.scala 31:13] + node _T_790 = bits(io.in, 6, 2) @[RVC.scala 37:14] + node _T_791 = orr(_T_790) @[RVC.scala 144:30] + node _T_792 = mux(_T_791, _T_755, _T_789) @[RVC.scala 144:25] + node _T_793 = bits(io.in, 12, 12) @[RVC.scala 145:12] + node _T_794 = mux(_T_793, _T_792, _T_773) @[RVC.scala 145:10] + node _T_795 = bits(io.in, 9, 7) @[RVC.scala 45:22] + node _T_796 = bits(io.in, 12, 10) @[RVC.scala 45:30] + node _T_797 = cat(_T_795, _T_796) @[Cat.scala 29:58] + node _T_798 = cat(_T_797, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_799 = shr(_T_798, 5) @[RVC.scala 129:34] + node _T_800 = bits(io.in, 6, 2) @[RVC.scala 37:14] + node _T_801 = bits(io.in, 9, 7) @[RVC.scala 45:22] + node _T_802 = bits(io.in, 12, 10) @[RVC.scala 45:30] + node _T_803 = cat(_T_801, _T_802) @[Cat.scala 29:58] + node _T_804 = cat(_T_803, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_805 = bits(_T_804, 4, 0) @[RVC.scala 129:66] + node _T_806 = cat(UInt<3>("h03"), _T_805) @[Cat.scala 29:58] + node _T_807 = cat(_T_806, UInt<7>("h027")) @[Cat.scala 29:58] + node _T_808 = cat(_T_799, _T_800) @[Cat.scala 29:58] + node _T_809 = cat(_T_808, UInt<5>("h02")) @[Cat.scala 29:58] + node _T_810 = cat(_T_809, _T_807) @[Cat.scala 29:58] + node _T_811 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_812 = bits(io.in, 6, 2) @[RVC.scala 37:14] + node _T_813 = bits(io.in, 31, 27) @[RVC.scala 25:101] + wire _T_814 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 26:19] + _T_814.bits <= _T_810 @[RVC.scala 27:14] + _T_814.rd <= _T_811 @[RVC.scala 28:12] + _T_814.rs1 <= UInt<5>("h02") @[RVC.scala 29:13] + _T_814.rs2 <= _T_812 @[RVC.scala 30:13] + _T_814.rs3 <= _T_813 @[RVC.scala 31:13] + node _T_815 = bits(io.in, 8, 7) @[RVC.scala 44:22] + node _T_816 = bits(io.in, 12, 9) @[RVC.scala 44:30] + node _T_817 = cat(_T_815, _T_816) @[Cat.scala 29:58] + node _T_818 = cat(_T_817, UInt<2>("h00")) @[Cat.scala 29:58] + node _T_819 = shr(_T_818, 5) @[RVC.scala 128:33] + node _T_820 = bits(io.in, 6, 2) @[RVC.scala 37:14] + node _T_821 = bits(io.in, 8, 7) @[RVC.scala 44:22] + node _T_822 = bits(io.in, 12, 9) @[RVC.scala 44:30] + node _T_823 = cat(_T_821, _T_822) @[Cat.scala 29:58] + node _T_824 = cat(_T_823, UInt<2>("h00")) @[Cat.scala 29:58] + node _T_825 = bits(_T_824, 4, 0) @[RVC.scala 128:65] + node _T_826 = cat(UInt<3>("h02"), _T_825) @[Cat.scala 29:58] + node _T_827 = cat(_T_826, UInt<7>("h023")) @[Cat.scala 29:58] + node _T_828 = cat(_T_819, _T_820) @[Cat.scala 29:58] + node _T_829 = cat(_T_828, UInt<5>("h02")) @[Cat.scala 29:58] + node _T_830 = cat(_T_829, _T_827) @[Cat.scala 29:58] + node _T_831 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_832 = bits(io.in, 6, 2) @[RVC.scala 37:14] + node _T_833 = bits(io.in, 31, 27) @[RVC.scala 25:101] + wire _T_834 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 26:19] + _T_834.bits <= _T_830 @[RVC.scala 27:14] + _T_834.rd <= _T_831 @[RVC.scala 28:12] + _T_834.rs1 <= UInt<5>("h02") @[RVC.scala 29:13] + _T_834.rs2 <= _T_832 @[RVC.scala 30:13] + _T_834.rs3 <= _T_833 @[RVC.scala 31:13] + node _T_835 = bits(io.in, 8, 7) @[RVC.scala 44:22] + node _T_836 = bits(io.in, 12, 9) @[RVC.scala 44:30] + node _T_837 = cat(_T_835, _T_836) @[Cat.scala 29:58] + node _T_838 = cat(_T_837, UInt<2>("h00")) @[Cat.scala 29:58] + node _T_839 = shr(_T_838, 5) @[RVC.scala 131:40] + node _T_840 = bits(io.in, 6, 2) @[RVC.scala 37:14] + node _T_841 = bits(io.in, 8, 7) @[RVC.scala 44:22] + node _T_842 = bits(io.in, 12, 9) @[RVC.scala 44:30] + node _T_843 = cat(_T_841, _T_842) @[Cat.scala 29:58] + node _T_844 = cat(_T_843, UInt<2>("h00")) @[Cat.scala 29:58] + node _T_845 = bits(_T_844, 4, 0) @[RVC.scala 131:72] + node _T_846 = cat(UInt<3>("h02"), _T_845) @[Cat.scala 29:58] + node _T_847 = cat(_T_846, UInt<7>("h027")) @[Cat.scala 29:58] + node _T_848 = cat(_T_839, _T_840) @[Cat.scala 29:58] + node _T_849 = cat(_T_848, UInt<5>("h02")) @[Cat.scala 29:58] + node _T_850 = cat(_T_849, _T_847) @[Cat.scala 29:58] + node _T_851 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_852 = bits(io.in, 6, 2) @[RVC.scala 37:14] + node _T_853 = bits(io.in, 31, 27) @[RVC.scala 25:101] + wire _T_854 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 26:19] + _T_854.bits <= _T_850 @[RVC.scala 27:14] + _T_854.rd <= _T_851 @[RVC.scala 28:12] + _T_854.rs1 <= UInt<5>("h02") @[RVC.scala 29:13] + _T_854.rs2 <= _T_852 @[RVC.scala 30:13] + _T_854.rs3 <= _T_853 @[RVC.scala 31:13] + node _T_855 = bits(io.in, 11, 7) @[RVC.scala 25:36] + node _T_856 = bits(io.in, 19, 15) @[RVC.scala 25:57] + node _T_857 = bits(io.in, 24, 20) @[RVC.scala 25:79] + node _T_858 = bits(io.in, 31, 27) @[RVC.scala 25:101] + wire _T_859 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 26:19] + _T_859.bits <= io.in @[RVC.scala 27:14] + _T_859.rd <= _T_855 @[RVC.scala 28:12] + _T_859.rs1 <= _T_856 @[RVC.scala 29:13] + _T_859.rs2 <= _T_857 @[RVC.scala 30:13] + _T_859.rs3 <= _T_858 @[RVC.scala 31:13] + node _T_860 = bits(io.in, 11, 7) @[RVC.scala 25:36] + node _T_861 = bits(io.in, 19, 15) @[RVC.scala 25:57] + node _T_862 = bits(io.in, 24, 20) @[RVC.scala 25:79] + node _T_863 = bits(io.in, 31, 27) @[RVC.scala 25:101] + wire _T_864 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 26:19] + _T_864.bits <= io.in @[RVC.scala 27:14] + _T_864.rd <= _T_860 @[RVC.scala 28:12] + _T_864.rs1 <= _T_861 @[RVC.scala 29:13] + _T_864.rs2 <= _T_862 @[RVC.scala 30:13] + _T_864.rs3 <= _T_863 @[RVC.scala 31:13] + node _T_865 = bits(io.in, 11, 7) @[RVC.scala 25:36] + node _T_866 = bits(io.in, 19, 15) @[RVC.scala 25:57] + node _T_867 = bits(io.in, 24, 20) @[RVC.scala 25:79] + node _T_868 = bits(io.in, 31, 27) @[RVC.scala 25:101] + wire _T_869 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 26:19] + _T_869.bits <= io.in @[RVC.scala 27:14] + _T_869.rd <= _T_865 @[RVC.scala 28:12] + _T_869.rs1 <= _T_866 @[RVC.scala 29:13] + _T_869.rs2 <= _T_867 @[RVC.scala 30:13] + _T_869.rs3 <= _T_868 @[RVC.scala 31:13] + node _T_870 = bits(io.in, 11, 7) @[RVC.scala 25:36] + node _T_871 = bits(io.in, 19, 15) @[RVC.scala 25:57] + node _T_872 = bits(io.in, 24, 20) @[RVC.scala 25:79] + node _T_873 = bits(io.in, 31, 27) @[RVC.scala 25:101] + wire _T_874 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 26:19] + _T_874.bits <= io.in @[RVC.scala 27:14] + _T_874.rd <= _T_870 @[RVC.scala 28:12] + _T_874.rs1 <= _T_871 @[RVC.scala 29:13] + _T_874.rs2 <= _T_872 @[RVC.scala 30:13] + _T_874.rs3 <= _T_873 @[RVC.scala 31:13] + node _T_875 = bits(io.in, 11, 7) @[RVC.scala 25:36] + node _T_876 = bits(io.in, 19, 15) @[RVC.scala 25:57] + node _T_877 = bits(io.in, 24, 20) @[RVC.scala 25:79] + node _T_878 = bits(io.in, 31, 27) @[RVC.scala 25:101] + wire _T_879 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 26:19] + _T_879.bits <= io.in @[RVC.scala 27:14] + _T_879.rd <= _T_875 @[RVC.scala 28:12] + _T_879.rs1 <= _T_876 @[RVC.scala 29:13] + _T_879.rs2 <= _T_877 @[RVC.scala 30:13] + _T_879.rs3 <= _T_878 @[RVC.scala 31:13] + node _T_880 = bits(io.in, 11, 7) @[RVC.scala 25:36] + node _T_881 = bits(io.in, 19, 15) @[RVC.scala 25:57] + node _T_882 = bits(io.in, 24, 20) @[RVC.scala 25:79] + node _T_883 = bits(io.in, 31, 27) @[RVC.scala 25:101] + wire _T_884 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 26:19] + _T_884.bits <= io.in @[RVC.scala 27:14] + _T_884.rd <= _T_880 @[RVC.scala 28:12] + _T_884.rs1 <= _T_881 @[RVC.scala 29:13] + _T_884.rs2 <= _T_882 @[RVC.scala 30:13] + _T_884.rs3 <= _T_883 @[RVC.scala 31:13] + node _T_885 = bits(io.in, 11, 7) @[RVC.scala 25:36] + node _T_886 = bits(io.in, 19, 15) @[RVC.scala 25:57] + node _T_887 = bits(io.in, 24, 20) @[RVC.scala 25:79] + node _T_888 = bits(io.in, 31, 27) @[RVC.scala 25:101] + wire _T_889 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 26:19] + _T_889.bits <= io.in @[RVC.scala 27:14] + _T_889.rd <= _T_885 @[RVC.scala 28:12] + _T_889.rs1 <= _T_886 @[RVC.scala 29:13] + _T_889.rs2 <= _T_887 @[RVC.scala 30:13] + _T_889.rs3 <= _T_888 @[RVC.scala 31:13] + node _T_890 = bits(io.in, 11, 7) @[RVC.scala 25:36] + node _T_891 = bits(io.in, 19, 15) @[RVC.scala 25:57] + node _T_892 = bits(io.in, 24, 20) @[RVC.scala 25:79] + node _T_893 = bits(io.in, 31, 27) @[RVC.scala 25:101] + wire _T_894 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 26:19] + _T_894.bits <= io.in @[RVC.scala 27:14] + _T_894.rd <= _T_890 @[RVC.scala 28:12] + _T_894.rs1 <= _T_891 @[RVC.scala 29:13] + _T_894.rs2 <= _T_892 @[RVC.scala 30:13] + _T_894.rs3 <= _T_893 @[RVC.scala 31:13] + wire _T_895 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}[32] @[RVC.scala 155:20] + _T_895[0].rs3 <= _T_24.rs3 @[RVC.scala 155:20] + _T_895[0].rs2 <= _T_24.rs2 @[RVC.scala 155:20] + _T_895[0].rs1 <= _T_24.rs1 @[RVC.scala 155:20] + _T_895[0].rd <= _T_24.rd @[RVC.scala 155:20] + _T_895[0].bits <= _T_24.bits @[RVC.scala 155:20] + _T_895[1].rs3 <= _T_44.rs3 @[RVC.scala 155:20] + _T_895[1].rs2 <= _T_44.rs2 @[RVC.scala 155:20] + _T_895[1].rs1 <= _T_44.rs1 @[RVC.scala 155:20] + _T_895[1].rd <= _T_44.rd @[RVC.scala 155:20] + _T_895[1].bits <= _T_44.bits @[RVC.scala 155:20] + _T_895[2].rs3 <= _T_66.rs3 @[RVC.scala 155:20] + _T_895[2].rs2 <= _T_66.rs2 @[RVC.scala 155:20] + _T_895[2].rs1 <= _T_66.rs1 @[RVC.scala 155:20] + _T_895[2].rd <= _T_66.rd @[RVC.scala 155:20] + _T_895[2].bits <= _T_66.bits @[RVC.scala 155:20] + _T_895[3].rs3 <= _T_88.rs3 @[RVC.scala 155:20] + _T_895[3].rs2 <= _T_88.rs2 @[RVC.scala 155:20] + _T_895[3].rs1 <= _T_88.rs1 @[RVC.scala 155:20] + _T_895[3].rd <= _T_88.rd @[RVC.scala 155:20] + _T_895[3].bits <= _T_88.bits @[RVC.scala 155:20] + _T_895[4].rs3 <= _T_119.rs3 @[RVC.scala 155:20] + _T_895[4].rs2 <= _T_119.rs2 @[RVC.scala 155:20] + _T_895[4].rs1 <= _T_119.rs1 @[RVC.scala 155:20] + _T_895[4].rd <= _T_119.rd @[RVC.scala 155:20] + _T_895[4].bits <= _T_119.bits @[RVC.scala 155:20] + _T_895[5].rs3 <= _T_146.rs3 @[RVC.scala 155:20] + _T_895[5].rs2 <= _T_146.rs2 @[RVC.scala 155:20] + _T_895[5].rs1 <= _T_146.rs1 @[RVC.scala 155:20] + _T_895[5].rd <= _T_146.rd @[RVC.scala 155:20] + _T_895[5].bits <= _T_146.bits @[RVC.scala 155:20] + _T_895[6].rs3 <= _T_177.rs3 @[RVC.scala 155:20] + _T_895[6].rs2 <= _T_177.rs2 @[RVC.scala 155:20] + _T_895[6].rs1 <= _T_177.rs1 @[RVC.scala 155:20] + _T_895[6].rd <= _T_177.rd @[RVC.scala 155:20] + _T_895[6].bits <= _T_177.bits @[RVC.scala 155:20] + _T_895[7].rs3 <= _T_208.rs3 @[RVC.scala 155:20] + _T_895[7].rs2 <= _T_208.rs2 @[RVC.scala 155:20] + _T_895[7].rs1 <= _T_208.rs1 @[RVC.scala 155:20] + _T_895[7].rd <= _T_208.rd @[RVC.scala 155:20] + _T_895[7].bits <= _T_208.bits @[RVC.scala 155:20] + _T_895[8].rs3 <= _T_225.rs3 @[RVC.scala 155:20] + _T_895[8].rs2 <= _T_225.rs2 @[RVC.scala 155:20] + _T_895[8].rs1 <= _T_225.rs1 @[RVC.scala 155:20] + _T_895[8].rd <= _T_225.rd @[RVC.scala 155:20] + _T_895[8].bits <= _T_225.bits @[RVC.scala 155:20] + _T_895[9].rs3 <= _T_311.rs3 @[RVC.scala 155:20] + _T_895[9].rs2 <= _T_311.rs2 @[RVC.scala 155:20] + _T_895[9].rs1 <= _T_311.rs1 @[RVC.scala 155:20] + _T_895[9].rd <= _T_311.rd @[RVC.scala 155:20] + _T_895[9].bits <= _T_311.bits @[RVC.scala 155:20] + _T_895[10].rs3 <= _T_326.rs3 @[RVC.scala 155:20] + _T_895[10].rs2 <= _T_326.rs2 @[RVC.scala 155:20] + _T_895[10].rs1 <= _T_326.rs1 @[RVC.scala 155:20] + _T_895[10].rd <= _T_326.rd @[RVC.scala 155:20] + _T_895[10].bits <= _T_326.bits @[RVC.scala 155:20] + _T_895[11].rs3 <= _T_386.rs3 @[RVC.scala 155:20] + _T_895[11].rs2 <= _T_386.rs2 @[RVC.scala 155:20] + _T_895[11].rs1 <= _T_386.rs1 @[RVC.scala 155:20] + _T_895[11].rd <= _T_386.rd @[RVC.scala 155:20] + _T_895[11].bits <= _T_386.bits @[RVC.scala 155:20] + _T_895[12].rs3 <= _T_452.rs3 @[RVC.scala 155:20] + _T_895[12].rs2 <= _T_452.rs2 @[RVC.scala 155:20] + _T_895[12].rs1 <= _T_452.rs1 @[RVC.scala 155:20] + _T_895[12].rd <= _T_452.rd @[RVC.scala 155:20] + _T_895[12].bits <= _T_452.bits @[RVC.scala 155:20] + _T_895[13].rs3 <= _T_539.rs3 @[RVC.scala 155:20] + _T_895[13].rs2 <= _T_539.rs2 @[RVC.scala 155:20] + _T_895[13].rs1 <= _T_539.rs1 @[RVC.scala 155:20] + _T_895[13].rd <= _T_539.rd @[RVC.scala 155:20] + _T_895[13].bits <= _T_539.bits @[RVC.scala 155:20] + _T_895[14].rs3 <= _T_606.rs3 @[RVC.scala 155:20] + _T_895[14].rs2 <= _T_606.rs2 @[RVC.scala 155:20] + _T_895[14].rs1 <= _T_606.rs1 @[RVC.scala 155:20] + _T_895[14].rd <= _T_606.rd @[RVC.scala 155:20] + _T_895[14].bits <= _T_606.bits @[RVC.scala 155:20] + _T_895[15].rs3 <= _T_671.rs3 @[RVC.scala 155:20] + _T_895[15].rs2 <= _T_671.rs2 @[RVC.scala 155:20] + _T_895[15].rs1 <= _T_671.rs1 @[RVC.scala 155:20] + _T_895[15].rd <= _T_671.rd @[RVC.scala 155:20] + _T_895[15].bits <= _T_671.bits @[RVC.scala 155:20] + _T_895[16].rs3 <= _T_688.rs3 @[RVC.scala 155:20] + _T_895[16].rs2 <= _T_688.rs2 @[RVC.scala 155:20] + _T_895[16].rs1 <= _T_688.rs1 @[RVC.scala 155:20] + _T_895[16].rd <= _T_688.rd @[RVC.scala 155:20] + _T_895[16].bits <= _T_688.bits @[RVC.scala 155:20] + _T_895[17].rs3 <= _T_703.rs3 @[RVC.scala 155:20] + _T_895[17].rs2 <= _T_703.rs2 @[RVC.scala 155:20] + _T_895[17].rs1 <= _T_703.rs1 @[RVC.scala 155:20] + _T_895[17].rd <= _T_703.rd @[RVC.scala 155:20] + _T_895[17].bits <= _T_703.bits @[RVC.scala 155:20] + _T_895[18].rs3 <= _T_718.rs3 @[RVC.scala 155:20] + _T_895[18].rs2 <= _T_718.rs2 @[RVC.scala 155:20] + _T_895[18].rs1 <= _T_718.rs1 @[RVC.scala 155:20] + _T_895[18].rd <= _T_718.rd @[RVC.scala 155:20] + _T_895[18].bits <= _T_718.bits @[RVC.scala 155:20] + _T_895[19].rs3 <= _T_733.rs3 @[RVC.scala 155:20] + _T_895[19].rs2 <= _T_733.rs2 @[RVC.scala 155:20] + _T_895[19].rs1 <= _T_733.rs1 @[RVC.scala 155:20] + _T_895[19].rd <= _T_733.rd @[RVC.scala 155:20] + _T_895[19].bits <= _T_733.bits @[RVC.scala 155:20] + _T_895[20].rs3 <= _T_794.rs3 @[RVC.scala 155:20] + _T_895[20].rs2 <= _T_794.rs2 @[RVC.scala 155:20] + _T_895[20].rs1 <= _T_794.rs1 @[RVC.scala 155:20] + _T_895[20].rd <= _T_794.rd @[RVC.scala 155:20] + _T_895[20].bits <= _T_794.bits @[RVC.scala 155:20] + _T_895[21].rs3 <= _T_814.rs3 @[RVC.scala 155:20] + _T_895[21].rs2 <= _T_814.rs2 @[RVC.scala 155:20] + _T_895[21].rs1 <= _T_814.rs1 @[RVC.scala 155:20] + _T_895[21].rd <= _T_814.rd @[RVC.scala 155:20] + _T_895[21].bits <= _T_814.bits @[RVC.scala 155:20] + _T_895[22].rs3 <= _T_834.rs3 @[RVC.scala 155:20] + _T_895[22].rs2 <= _T_834.rs2 @[RVC.scala 155:20] + _T_895[22].rs1 <= _T_834.rs1 @[RVC.scala 155:20] + _T_895[22].rd <= _T_834.rd @[RVC.scala 155:20] + _T_895[22].bits <= _T_834.bits @[RVC.scala 155:20] + _T_895[23].rs3 <= _T_854.rs3 @[RVC.scala 155:20] + _T_895[23].rs2 <= _T_854.rs2 @[RVC.scala 155:20] + _T_895[23].rs1 <= _T_854.rs1 @[RVC.scala 155:20] + _T_895[23].rd <= _T_854.rd @[RVC.scala 155:20] + _T_895[23].bits <= _T_854.bits @[RVC.scala 155:20] + _T_895[24].rs3 <= _T_859.rs3 @[RVC.scala 155:20] + _T_895[24].rs2 <= _T_859.rs2 @[RVC.scala 155:20] + _T_895[24].rs1 <= _T_859.rs1 @[RVC.scala 155:20] + _T_895[24].rd <= _T_859.rd @[RVC.scala 155:20] + _T_895[24].bits <= _T_859.bits @[RVC.scala 155:20] + _T_895[25].rs3 <= _T_864.rs3 @[RVC.scala 155:20] + _T_895[25].rs2 <= _T_864.rs2 @[RVC.scala 155:20] + _T_895[25].rs1 <= _T_864.rs1 @[RVC.scala 155:20] + _T_895[25].rd <= _T_864.rd @[RVC.scala 155:20] + _T_895[25].bits <= _T_864.bits @[RVC.scala 155:20] + _T_895[26].rs3 <= _T_869.rs3 @[RVC.scala 155:20] + _T_895[26].rs2 <= _T_869.rs2 @[RVC.scala 155:20] + _T_895[26].rs1 <= _T_869.rs1 @[RVC.scala 155:20] + _T_895[26].rd <= _T_869.rd @[RVC.scala 155:20] + _T_895[26].bits <= _T_869.bits @[RVC.scala 155:20] + _T_895[27].rs3 <= _T_874.rs3 @[RVC.scala 155:20] + _T_895[27].rs2 <= _T_874.rs2 @[RVC.scala 155:20] + _T_895[27].rs1 <= _T_874.rs1 @[RVC.scala 155:20] + _T_895[27].rd <= _T_874.rd @[RVC.scala 155:20] + _T_895[27].bits <= _T_874.bits @[RVC.scala 155:20] + _T_895[28].rs3 <= _T_879.rs3 @[RVC.scala 155:20] + _T_895[28].rs2 <= _T_879.rs2 @[RVC.scala 155:20] + _T_895[28].rs1 <= _T_879.rs1 @[RVC.scala 155:20] + _T_895[28].rd <= _T_879.rd @[RVC.scala 155:20] + _T_895[28].bits <= _T_879.bits @[RVC.scala 155:20] + _T_895[29].rs3 <= _T_884.rs3 @[RVC.scala 155:20] + _T_895[29].rs2 <= _T_884.rs2 @[RVC.scala 155:20] + _T_895[29].rs1 <= _T_884.rs1 @[RVC.scala 155:20] + _T_895[29].rd <= _T_884.rd @[RVC.scala 155:20] + _T_895[29].bits <= _T_884.bits @[RVC.scala 155:20] + _T_895[30].rs3 <= _T_889.rs3 @[RVC.scala 155:20] + _T_895[30].rs2 <= _T_889.rs2 @[RVC.scala 155:20] + _T_895[30].rs1 <= _T_889.rs1 @[RVC.scala 155:20] + _T_895[30].rd <= _T_889.rd @[RVC.scala 155:20] + _T_895[30].bits <= _T_889.bits @[RVC.scala 155:20] + _T_895[31].rs3 <= _T_894.rs3 @[RVC.scala 155:20] + _T_895[31].rs2 <= _T_894.rs2 @[RVC.scala 155:20] + _T_895[31].rs1 <= _T_894.rs1 @[RVC.scala 155:20] + _T_895[31].rd <= _T_894.rd @[RVC.scala 155:20] + _T_895[31].bits <= _T_894.bits @[RVC.scala 155:20] + node _T_896 = bits(io.in, 1, 0) @[RVC.scala 156:12] + node _T_897 = bits(io.in, 15, 13) @[RVC.scala 156:20] + node _T_898 = cat(_T_896, _T_897) @[Cat.scala 29:58] + io.out.rs3 <= _T_895[_T_898].rs3 @[RVC.scala 203:12] + io.out.rs2 <= _T_895[_T_898].rs2 @[RVC.scala 203:12] + io.out.rs1 <= _T_895[_T_898].rs1 @[RVC.scala 203:12] + io.out.rd <= _T_895[_T_898].rd @[RVC.scala 203:12] + io.out.bits <= _T_895[_T_898].bits @[RVC.scala 203:12] + node _T_899 = bits(io.in, 13, 13) @[RVC.scala 204:24] + node _T_900 = eq(_T_899, UInt<1>("h00")) @[RVC.scala 204:18] + node _T_901 = bits(io.in, 12, 12) @[RVC.scala 204:37] + node _T_902 = eq(_T_901, UInt<1>("h00")) @[RVC.scala 204:31] + node _T_903 = and(_T_900, _T_902) @[RVC.scala 204:29] + node _T_904 = bits(io.in, 11, 11) @[RVC.scala 204:49] + node _T_905 = and(_T_903, _T_904) @[RVC.scala 204:42] + node _T_906 = bits(io.in, 1, 1) @[RVC.scala 204:60] + node _T_907 = and(_T_905, _T_906) @[RVC.scala 204:54] + node _T_908 = bits(io.in, 0, 0) @[RVC.scala 204:71] + node _T_909 = eq(_T_908, UInt<1>("h00")) @[RVC.scala 204:65] + node _T_910 = and(_T_907, _T_909) @[RVC.scala 204:63] + node _T_911 = bits(io.in, 13, 13) @[RVC.scala 205:14] + node _T_912 = eq(_T_911, UInt<1>("h00")) @[RVC.scala 205:8] + node _T_913 = bits(io.in, 12, 12) @[RVC.scala 205:27] + node _T_914 = eq(_T_913, UInt<1>("h00")) @[RVC.scala 205:21] + node _T_915 = and(_T_912, _T_914) @[RVC.scala 205:19] + node _T_916 = bits(io.in, 6, 6) @[RVC.scala 205:39] + node _T_917 = and(_T_915, _T_916) @[RVC.scala 205:32] + node _T_918 = bits(io.in, 1, 1) @[RVC.scala 205:49] + node _T_919 = and(_T_917, _T_918) @[RVC.scala 205:43] + node _T_920 = bits(io.in, 0, 0) @[RVC.scala 205:60] + node _T_921 = eq(_T_920, UInt<1>("h00")) @[RVC.scala 205:54] + node _T_922 = and(_T_919, _T_921) @[RVC.scala 205:52] + node _T_923 = or(_T_910, _T_922) @[RVC.scala 204:76] + node _T_924 = bits(io.in, 15, 15) @[RVC.scala 206:14] + node _T_925 = eq(_T_924, UInt<1>("h00")) @[RVC.scala 206:8] + node _T_926 = bits(io.in, 13, 13) @[RVC.scala 206:27] + node _T_927 = eq(_T_926, UInt<1>("h00")) @[RVC.scala 206:21] + node _T_928 = and(_T_925, _T_927) @[RVC.scala 206:19] + node _T_929 = bits(io.in, 11, 11) @[RVC.scala 206:38] + node _T_930 = bits(io.in, 1, 1) @[RVC.scala 206:49] + node _T_931 = eq(_T_930, UInt<1>("h00")) @[RVC.scala 206:43] + node _T_932 = dshr(_T_929, _T_931) @[RVC.scala 206:42] + node _T_933 = bits(_T_932, 0, 0) @[RVC.scala 206:42] + node _T_934 = and(_T_928, _T_933) @[RVC.scala 206:32] + node _T_935 = or(_T_923, _T_934) @[RVC.scala 205:65] + node _T_936 = bits(io.in, 13, 13) @[RVC.scala 207:14] + node _T_937 = eq(_T_936, UInt<1>("h00")) @[RVC.scala 207:8] + node _T_938 = bits(io.in, 12, 12) @[RVC.scala 207:27] + node _T_939 = eq(_T_938, UInt<1>("h00")) @[RVC.scala 207:21] + node _T_940 = and(_T_937, _T_939) @[RVC.scala 207:19] + node _T_941 = bits(io.in, 5, 5) @[RVC.scala 207:38] + node _T_942 = and(_T_940, _T_941) @[RVC.scala 207:32] + node _T_943 = bits(io.in, 1, 1) @[RVC.scala 207:47] + node _T_944 = and(_T_942, _T_943) @[RVC.scala 207:41] + node _T_945 = bits(io.in, 0, 0) @[RVC.scala 207:58] + node _T_946 = eq(_T_945, UInt<1>("h00")) @[RVC.scala 207:52] + node _T_947 = and(_T_944, _T_946) @[RVC.scala 207:50] + node _T_948 = or(_T_935, _T_947) @[RVC.scala 206:54] + node _T_949 = bits(io.in, 13, 13) @[RVC.scala 208:14] + node _T_950 = eq(_T_949, UInt<1>("h00")) @[RVC.scala 208:8] + node _T_951 = bits(io.in, 12, 12) @[RVC.scala 208:27] + node _T_952 = eq(_T_951, UInt<1>("h00")) @[RVC.scala 208:21] + node _T_953 = and(_T_950, _T_952) @[RVC.scala 208:19] + node _T_954 = bits(io.in, 10, 10) @[RVC.scala 208:38] + node _T_955 = and(_T_953, _T_954) @[RVC.scala 208:32] + node _T_956 = bits(io.in, 1, 1) @[RVC.scala 208:50] + node _T_957 = eq(_T_956, UInt<1>("h00")) @[RVC.scala 208:44] + node _T_958 = and(_T_955, _T_957) @[RVC.scala 208:42] + node _T_959 = bits(io.in, 0, 0) @[RVC.scala 208:60] + node _T_960 = and(_T_958, _T_959) @[RVC.scala 208:54] + node _T_961 = or(_T_948, _T_960) @[RVC.scala 207:63] + node _T_962 = bits(io.in, 15, 15) @[RVC.scala 209:14] + node _T_963 = eq(_T_962, UInt<1>("h00")) @[RVC.scala 209:8] + node _T_964 = bits(io.in, 13, 13) @[RVC.scala 209:27] + node _T_965 = eq(_T_964, UInt<1>("h00")) @[RVC.scala 209:21] + node _T_966 = and(_T_963, _T_965) @[RVC.scala 209:19] + node _T_967 = bits(io.in, 6, 6) @[RVC.scala 209:38] + node _T_968 = and(_T_966, _T_967) @[RVC.scala 209:32] + node _T_969 = bits(io.in, 1, 1) @[RVC.scala 209:49] + node _T_970 = eq(_T_969, UInt<1>("h00")) @[RVC.scala 209:43] + node _T_971 = and(_T_968, _T_970) @[RVC.scala 209:41] + node _T_972 = or(_T_961, _T_971) @[RVC.scala 208:64] + node _T_973 = bits(io.in, 15, 15) @[RVC.scala 209:61] + node _T_974 = bits(io.in, 12, 12) @[RVC.scala 209:73] + node _T_975 = eq(_T_974, UInt<1>("h00")) @[RVC.scala 209:67] + node _T_976 = and(_T_973, _T_975) @[RVC.scala 209:65] + node _T_977 = bits(io.in, 1, 1) @[RVC.scala 209:86] + node _T_978 = eq(_T_977, UInt<1>("h00")) @[RVC.scala 209:80] + node _T_979 = and(_T_976, _T_978) @[RVC.scala 209:78] + node _T_980 = bits(io.in, 0, 0) @[RVC.scala 209:96] + node _T_981 = and(_T_979, _T_980) @[RVC.scala 209:90] + node _T_982 = or(_T_972, _T_981) @[RVC.scala 209:54] + node _T_983 = bits(io.in, 13, 13) @[RVC.scala 210:14] + node _T_984 = eq(_T_983, UInt<1>("h00")) @[RVC.scala 210:8] + node _T_985 = bits(io.in, 12, 12) @[RVC.scala 210:27] + node _T_986 = eq(_T_985, UInt<1>("h00")) @[RVC.scala 210:21] + node _T_987 = and(_T_984, _T_986) @[RVC.scala 210:19] + node _T_988 = bits(io.in, 9, 9) @[RVC.scala 210:38] + node _T_989 = and(_T_987, _T_988) @[RVC.scala 210:32] + node _T_990 = bits(io.in, 1, 1) @[RVC.scala 210:47] + node _T_991 = and(_T_989, _T_990) @[RVC.scala 210:41] + node _T_992 = bits(io.in, 0, 0) @[RVC.scala 210:58] + node _T_993 = eq(_T_992, UInt<1>("h00")) @[RVC.scala 210:52] + node _T_994 = and(_T_991, _T_993) @[RVC.scala 210:50] + node _T_995 = or(_T_982, _T_994) @[RVC.scala 209:100] + node _T_996 = bits(io.in, 12, 12) @[RVC.scala 211:14] + node _T_997 = eq(_T_996, UInt<1>("h00")) @[RVC.scala 211:8] + node _T_998 = bits(io.in, 6, 6) @[RVC.scala 211:25] + node _T_999 = and(_T_997, _T_998) @[RVC.scala 211:19] + node _T_1000 = bits(io.in, 1, 1) @[RVC.scala 211:36] + node _T_1001 = eq(_T_1000, UInt<1>("h00")) @[RVC.scala 211:30] + node _T_1002 = and(_T_999, _T_1001) @[RVC.scala 211:28] + node _T_1003 = bits(io.in, 0, 0) @[RVC.scala 211:46] + node _T_1004 = and(_T_1002, _T_1003) @[RVC.scala 211:40] + node _T_1005 = or(_T_995, _T_1004) @[RVC.scala 210:63] + node _T_1006 = bits(io.in, 15, 15) @[RVC.scala 212:14] + node _T_1007 = eq(_T_1006, UInt<1>("h00")) @[RVC.scala 212:8] + node _T_1008 = bits(io.in, 13, 13) @[RVC.scala 212:27] + node _T_1009 = eq(_T_1008, UInt<1>("h00")) @[RVC.scala 212:21] + node _T_1010 = and(_T_1007, _T_1009) @[RVC.scala 212:19] + node _T_1011 = bits(io.in, 5, 5) @[RVC.scala 212:38] + node _T_1012 = and(_T_1010, _T_1011) @[RVC.scala 212:32] + node _T_1013 = bits(io.in, 1, 1) @[RVC.scala 212:49] + node _T_1014 = eq(_T_1013, UInt<1>("h00")) @[RVC.scala 212:43] + node _T_1015 = and(_T_1012, _T_1014) @[RVC.scala 212:41] + node _T_1016 = or(_T_1005, _T_1015) @[RVC.scala 211:50] + node _T_1017 = bits(io.in, 13, 13) @[RVC.scala 213:14] + node _T_1018 = eq(_T_1017, UInt<1>("h00")) @[RVC.scala 213:8] + node _T_1019 = bits(io.in, 12, 12) @[RVC.scala 213:27] + node _T_1020 = eq(_T_1019, UInt<1>("h00")) @[RVC.scala 213:21] + node _T_1021 = and(_T_1018, _T_1020) @[RVC.scala 213:19] + node _T_1022 = bits(io.in, 8, 8) @[RVC.scala 213:38] + node _T_1023 = and(_T_1021, _T_1022) @[RVC.scala 213:32] + node _T_1024 = bits(io.in, 1, 1) @[RVC.scala 213:47] + node _T_1025 = and(_T_1023, _T_1024) @[RVC.scala 213:41] + node _T_1026 = bits(io.in, 0, 0) @[RVC.scala 213:58] + node _T_1027 = eq(_T_1026, UInt<1>("h00")) @[RVC.scala 213:52] + node _T_1028 = and(_T_1025, _T_1027) @[RVC.scala 213:50] + node _T_1029 = or(_T_1016, _T_1028) @[RVC.scala 212:54] + node _T_1030 = bits(io.in, 12, 12) @[RVC.scala 214:14] + node _T_1031 = eq(_T_1030, UInt<1>("h00")) @[RVC.scala 214:8] + node _T_1032 = bits(io.in, 5, 5) @[RVC.scala 214:25] + node _T_1033 = and(_T_1031, _T_1032) @[RVC.scala 214:19] + node _T_1034 = bits(io.in, 1, 1) @[RVC.scala 214:36] + node _T_1035 = eq(_T_1034, UInt<1>("h00")) @[RVC.scala 214:30] + node _T_1036 = and(_T_1033, _T_1035) @[RVC.scala 214:28] + node _T_1037 = bits(io.in, 0, 0) @[RVC.scala 214:46] + node _T_1038 = and(_T_1036, _T_1037) @[RVC.scala 214:40] + node _T_1039 = or(_T_1029, _T_1038) @[RVC.scala 213:63] + node _T_1040 = bits(io.in, 15, 15) @[RVC.scala 215:14] + node _T_1041 = eq(_T_1040, UInt<1>("h00")) @[RVC.scala 215:8] + node _T_1042 = bits(io.in, 13, 13) @[RVC.scala 215:27] + node _T_1043 = eq(_T_1042, UInt<1>("h00")) @[RVC.scala 215:21] + node _T_1044 = and(_T_1041, _T_1043) @[RVC.scala 215:19] + node _T_1045 = bits(io.in, 10, 10) @[RVC.scala 215:38] + node _T_1046 = and(_T_1044, _T_1045) @[RVC.scala 215:32] + node _T_1047 = bits(io.in, 1, 1) @[RVC.scala 215:50] + node _T_1048 = eq(_T_1047, UInt<1>("h00")) @[RVC.scala 215:44] + node _T_1049 = and(_T_1046, _T_1048) @[RVC.scala 215:42] + node _T_1050 = or(_T_1039, _T_1049) @[RVC.scala 214:50] + node _T_1051 = bits(io.in, 13, 13) @[RVC.scala 215:64] + node _T_1052 = eq(_T_1051, UInt<1>("h00")) @[RVC.scala 215:58] + node _T_1053 = bits(io.in, 12, 12) @[RVC.scala 215:77] + node _T_1054 = eq(_T_1053, UInt<1>("h00")) @[RVC.scala 215:71] + node _T_1055 = and(_T_1052, _T_1054) @[RVC.scala 215:69] + node _T_1056 = bits(io.in, 7, 7) @[RVC.scala 215:88] + node _T_1057 = and(_T_1055, _T_1056) @[RVC.scala 215:82] + node _T_1058 = bits(io.in, 1, 1) @[RVC.scala 215:97] + node _T_1059 = and(_T_1057, _T_1058) @[RVC.scala 215:91] + node _T_1060 = bits(io.in, 0, 0) @[RVC.scala 215:108] + node _T_1061 = eq(_T_1060, UInt<1>("h00")) @[RVC.scala 215:102] + node _T_1062 = and(_T_1059, _T_1061) @[RVC.scala 215:100] + node _T_1063 = or(_T_1050, _T_1062) @[RVC.scala 215:55] + node _T_1064 = bits(io.in, 12, 12) @[RVC.scala 216:12] + node _T_1065 = bits(io.in, 11, 11) @[RVC.scala 216:22] + node _T_1066 = and(_T_1064, _T_1065) @[RVC.scala 216:16] + node _T_1067 = bits(io.in, 10, 10) @[RVC.scala 216:34] + node _T_1068 = eq(_T_1067, UInt<1>("h00")) @[RVC.scala 216:28] + node _T_1069 = and(_T_1066, _T_1068) @[RVC.scala 216:26] + node _T_1070 = bits(io.in, 1, 1) @[RVC.scala 216:47] + node _T_1071 = eq(_T_1070, UInt<1>("h00")) @[RVC.scala 216:41] + node _T_1072 = and(_T_1069, _T_1071) @[RVC.scala 216:39] + node _T_1073 = bits(io.in, 0, 0) @[RVC.scala 216:57] + node _T_1074 = and(_T_1072, _T_1073) @[RVC.scala 216:51] + node _T_1075 = or(_T_1063, _T_1074) @[RVC.scala 215:113] + node _T_1076 = bits(io.in, 15, 15) @[RVC.scala 216:70] + node _T_1077 = eq(_T_1076, UInt<1>("h00")) @[RVC.scala 216:64] + node _T_1078 = bits(io.in, 13, 13) @[RVC.scala 216:83] + node _T_1079 = eq(_T_1078, UInt<1>("h00")) @[RVC.scala 216:77] + node _T_1080 = and(_T_1077, _T_1079) @[RVC.scala 216:75] + node _T_1081 = bits(io.in, 9, 9) @[RVC.scala 216:94] + node _T_1082 = and(_T_1080, _T_1081) @[RVC.scala 216:88] + node _T_1083 = bits(io.in, 1, 1) @[RVC.scala 216:105] + node _T_1084 = eq(_T_1083, UInt<1>("h00")) @[RVC.scala 216:99] + node _T_1085 = and(_T_1082, _T_1084) @[RVC.scala 216:97] + node _T_1086 = or(_T_1075, _T_1085) @[RVC.scala 216:61] + node _T_1087 = bits(io.in, 13, 13) @[RVC.scala 217:14] + node _T_1088 = eq(_T_1087, UInt<1>("h00")) @[RVC.scala 217:8] + node _T_1089 = bits(io.in, 12, 12) @[RVC.scala 217:27] + node _T_1090 = eq(_T_1089, UInt<1>("h00")) @[RVC.scala 217:21] + node _T_1091 = and(_T_1088, _T_1090) @[RVC.scala 217:19] + node _T_1092 = bits(io.in, 4, 4) @[RVC.scala 217:38] + node _T_1093 = and(_T_1091, _T_1092) @[RVC.scala 217:32] + node _T_1094 = bits(io.in, 1, 1) @[RVC.scala 217:47] + node _T_1095 = and(_T_1093, _T_1094) @[RVC.scala 217:41] + node _T_1096 = bits(io.in, 0, 0) @[RVC.scala 217:58] + node _T_1097 = eq(_T_1096, UInt<1>("h00")) @[RVC.scala 217:52] + node _T_1098 = and(_T_1095, _T_1097) @[RVC.scala 217:50] + node _T_1099 = or(_T_1086, _T_1098) @[RVC.scala 216:110] + node _T_1100 = bits(io.in, 13, 13) @[RVC.scala 217:70] + node _T_1101 = bits(io.in, 12, 12) @[RVC.scala 217:80] + node _T_1102 = and(_T_1100, _T_1101) @[RVC.scala 217:74] + node _T_1103 = bits(io.in, 1, 1) @[RVC.scala 217:92] + node _T_1104 = eq(_T_1103, UInt<1>("h00")) @[RVC.scala 217:86] + node _T_1105 = and(_T_1102, _T_1104) @[RVC.scala 217:84] + node _T_1106 = bits(io.in, 0, 0) @[RVC.scala 217:102] + node _T_1107 = and(_T_1105, _T_1106) @[RVC.scala 217:96] + node _T_1108 = or(_T_1099, _T_1107) @[RVC.scala 217:63] + node _T_1109 = bits(io.in, 15, 15) @[RVC.scala 218:14] + node _T_1110 = eq(_T_1109, UInt<1>("h00")) @[RVC.scala 218:8] + node _T_1111 = bits(io.in, 13, 13) @[RVC.scala 218:27] + node _T_1112 = eq(_T_1111, UInt<1>("h00")) @[RVC.scala 218:21] + node _T_1113 = and(_T_1110, _T_1112) @[RVC.scala 218:19] + node _T_1114 = bits(io.in, 8, 8) @[RVC.scala 218:38] + node _T_1115 = and(_T_1113, _T_1114) @[RVC.scala 218:32] + node _T_1116 = bits(io.in, 1, 1) @[RVC.scala 218:49] + node _T_1117 = eq(_T_1116, UInt<1>("h00")) @[RVC.scala 218:43] + node _T_1118 = and(_T_1115, _T_1117) @[RVC.scala 218:41] + node _T_1119 = or(_T_1108, _T_1118) @[RVC.scala 217:106] + node _T_1120 = bits(io.in, 13, 13) @[RVC.scala 218:63] + node _T_1121 = eq(_T_1120, UInt<1>("h00")) @[RVC.scala 218:57] + node _T_1122 = bits(io.in, 12, 12) @[RVC.scala 218:76] + node _T_1123 = eq(_T_1122, UInt<1>("h00")) @[RVC.scala 218:70] + node _T_1124 = and(_T_1121, _T_1123) @[RVC.scala 218:68] + node _T_1125 = bits(io.in, 3, 3) @[RVC.scala 218:87] + node _T_1126 = and(_T_1124, _T_1125) @[RVC.scala 218:81] + node _T_1127 = bits(io.in, 1, 1) @[RVC.scala 218:96] + node _T_1128 = and(_T_1126, _T_1127) @[RVC.scala 218:90] + node _T_1129 = bits(io.in, 0, 0) @[RVC.scala 218:107] + node _T_1130 = eq(_T_1129, UInt<1>("h00")) @[RVC.scala 218:101] + node _T_1131 = and(_T_1128, _T_1130) @[RVC.scala 218:99] + node _T_1132 = or(_T_1119, _T_1131) @[RVC.scala 218:54] + node _T_1133 = bits(io.in, 13, 13) @[RVC.scala 219:12] + node _T_1134 = bits(io.in, 4, 4) @[RVC.scala 219:22] + node _T_1135 = and(_T_1133, _T_1134) @[RVC.scala 219:16] + node _T_1136 = bits(io.in, 1, 1) @[RVC.scala 219:33] + node _T_1137 = eq(_T_1136, UInt<1>("h00")) @[RVC.scala 219:27] + node _T_1138 = and(_T_1135, _T_1137) @[RVC.scala 219:25] + node _T_1139 = bits(io.in, 0, 0) @[RVC.scala 219:43] + node _T_1140 = and(_T_1138, _T_1139) @[RVC.scala 219:37] + node _T_1141 = or(_T_1132, _T_1140) @[RVC.scala 218:112] + node _T_1142 = bits(io.in, 13, 13) @[RVC.scala 219:56] + node _T_1143 = eq(_T_1142, UInt<1>("h00")) @[RVC.scala 219:50] + node _T_1144 = bits(io.in, 12, 12) @[RVC.scala 219:69] + node _T_1145 = eq(_T_1144, UInt<1>("h00")) @[RVC.scala 219:63] + node _T_1146 = and(_T_1143, _T_1145) @[RVC.scala 219:61] + node _T_1147 = bits(io.in, 2, 2) @[RVC.scala 219:80] + node _T_1148 = and(_T_1146, _T_1147) @[RVC.scala 219:74] + node _T_1149 = bits(io.in, 1, 1) @[RVC.scala 219:89] + node _T_1150 = and(_T_1148, _T_1149) @[RVC.scala 219:83] + node _T_1151 = bits(io.in, 0, 0) @[RVC.scala 219:100] + node _T_1152 = eq(_T_1151, UInt<1>("h00")) @[RVC.scala 219:94] + node _T_1153 = and(_T_1150, _T_1152) @[RVC.scala 219:92] + node _T_1154 = or(_T_1141, _T_1153) @[RVC.scala 219:47] + node _T_1155 = bits(io.in, 15, 15) @[RVC.scala 220:14] + node _T_1156 = eq(_T_1155, UInt<1>("h00")) @[RVC.scala 220:8] + node _T_1157 = bits(io.in, 13, 13) @[RVC.scala 220:27] + node _T_1158 = eq(_T_1157, UInt<1>("h00")) @[RVC.scala 220:21] + node _T_1159 = and(_T_1156, _T_1158) @[RVC.scala 220:19] + node _T_1160 = bits(io.in, 7, 7) @[RVC.scala 220:38] + node _T_1161 = and(_T_1159, _T_1160) @[RVC.scala 220:32] + node _T_1162 = bits(io.in, 1, 1) @[RVC.scala 220:49] + node _T_1163 = eq(_T_1162, UInt<1>("h00")) @[RVC.scala 220:43] + node _T_1164 = and(_T_1161, _T_1163) @[RVC.scala 220:41] + node _T_1165 = or(_T_1154, _T_1164) @[RVC.scala 219:105] + node _T_1166 = bits(io.in, 13, 13) @[RVC.scala 220:61] + node _T_1167 = bits(io.in, 3, 3) @[RVC.scala 220:71] + node _T_1168 = and(_T_1166, _T_1167) @[RVC.scala 220:65] + node _T_1169 = bits(io.in, 1, 1) @[RVC.scala 220:82] + node _T_1170 = eq(_T_1169, UInt<1>("h00")) @[RVC.scala 220:76] + node _T_1171 = and(_T_1168, _T_1170) @[RVC.scala 220:74] + node _T_1172 = bits(io.in, 0, 0) @[RVC.scala 220:92] + node _T_1173 = and(_T_1171, _T_1172) @[RVC.scala 220:86] + node _T_1174 = or(_T_1165, _T_1173) @[RVC.scala 220:54] + node _T_1175 = bits(io.in, 13, 13) @[RVC.scala 221:12] + node _T_1176 = bits(io.in, 2, 2) @[RVC.scala 221:22] + node _T_1177 = and(_T_1175, _T_1176) @[RVC.scala 221:16] + node _T_1178 = bits(io.in, 1, 1) @[RVC.scala 221:33] + node _T_1179 = eq(_T_1178, UInt<1>("h00")) @[RVC.scala 221:27] + node _T_1180 = and(_T_1177, _T_1179) @[RVC.scala 221:25] + node _T_1181 = bits(io.in, 0, 0) @[RVC.scala 221:43] + node _T_1182 = and(_T_1180, _T_1181) @[RVC.scala 221:37] + node _T_1183 = or(_T_1174, _T_1182) @[RVC.scala 220:96] + node _T_1184 = bits(io.in, 14, 14) @[RVC.scala 221:54] + node _T_1185 = bits(io.in, 13, 13) @[RVC.scala 221:66] + node _T_1186 = eq(_T_1185, UInt<1>("h00")) @[RVC.scala 221:60] + node _T_1187 = and(_T_1184, _T_1186) @[RVC.scala 221:58] + node _T_1188 = bits(io.in, 1, 1) @[RVC.scala 221:79] + node _T_1189 = eq(_T_1188, UInt<1>("h00")) @[RVC.scala 221:73] + node _T_1190 = and(_T_1187, _T_1189) @[RVC.scala 221:71] + node _T_1191 = or(_T_1183, _T_1190) @[RVC.scala 221:47] + node _T_1192 = bits(io.in, 14, 14) @[RVC.scala 222:14] + node _T_1193 = eq(_T_1192, UInt<1>("h00")) @[RVC.scala 222:8] + node _T_1194 = bits(io.in, 12, 12) @[RVC.scala 222:27] + node _T_1195 = eq(_T_1194, UInt<1>("h00")) @[RVC.scala 222:21] + node _T_1196 = and(_T_1193, _T_1195) @[RVC.scala 222:19] + node _T_1197 = bits(io.in, 1, 1) @[RVC.scala 222:40] + node _T_1198 = eq(_T_1197, UInt<1>("h00")) @[RVC.scala 222:34] + node _T_1199 = and(_T_1196, _T_1198) @[RVC.scala 222:32] + node _T_1200 = bits(io.in, 0, 0) @[RVC.scala 222:50] + node _T_1201 = and(_T_1199, _T_1200) @[RVC.scala 222:44] + node _T_1202 = or(_T_1191, _T_1201) @[RVC.scala 221:84] + node _T_1203 = bits(io.in, 15, 15) @[RVC.scala 222:61] + node _T_1204 = bits(io.in, 13, 13) @[RVC.scala 222:73] + node _T_1205 = eq(_T_1204, UInt<1>("h00")) @[RVC.scala 222:67] + node _T_1206 = and(_T_1203, _T_1205) @[RVC.scala 222:65] + node _T_1207 = bits(io.in, 12, 12) @[RVC.scala 222:84] + node _T_1208 = and(_T_1206, _T_1207) @[RVC.scala 222:78] + node _T_1209 = bits(io.in, 1, 1) @[RVC.scala 222:94] + node _T_1210 = and(_T_1208, _T_1209) @[RVC.scala 222:88] + node _T_1211 = bits(io.in, 0, 0) @[RVC.scala 222:105] + node _T_1212 = eq(_T_1211, UInt<1>("h00")) @[RVC.scala 222:99] + node _T_1213 = and(_T_1210, _T_1212) @[RVC.scala 222:97] + node _T_1214 = or(_T_1202, _T_1213) @[RVC.scala 222:54] + node _T_1215 = bits(io.in, 15, 15) @[RVC.scala 223:14] + node _T_1216 = eq(_T_1215, UInt<1>("h00")) @[RVC.scala 223:8] + node _T_1217 = bits(io.in, 13, 13) @[RVC.scala 223:27] + node _T_1218 = eq(_T_1217, UInt<1>("h00")) @[RVC.scala 223:21] + node _T_1219 = and(_T_1216, _T_1218) @[RVC.scala 223:19] + node _T_1220 = bits(io.in, 12, 12) @[RVC.scala 223:40] + node _T_1221 = eq(_T_1220, UInt<1>("h00")) @[RVC.scala 223:34] + node _T_1222 = and(_T_1219, _T_1221) @[RVC.scala 223:32] + node _T_1223 = bits(io.in, 1, 1) @[RVC.scala 223:51] + node _T_1224 = and(_T_1222, _T_1223) @[RVC.scala 223:45] + node _T_1225 = bits(io.in, 0, 0) @[RVC.scala 223:62] + node _T_1226 = eq(_T_1225, UInt<1>("h00")) @[RVC.scala 223:56] + node _T_1227 = and(_T_1224, _T_1226) @[RVC.scala 223:54] + node _T_1228 = or(_T_1214, _T_1227) @[RVC.scala 222:110] + node _T_1229 = bits(io.in, 15, 15) @[RVC.scala 223:76] + node _T_1230 = eq(_T_1229, UInt<1>("h00")) @[RVC.scala 223:70] + node _T_1231 = bits(io.in, 13, 13) @[RVC.scala 223:89] + node _T_1232 = eq(_T_1231, UInt<1>("h00")) @[RVC.scala 223:83] + node _T_1233 = and(_T_1230, _T_1232) @[RVC.scala 223:81] + node _T_1234 = bits(io.in, 12, 12) @[RVC.scala 223:100] + node _T_1235 = and(_T_1233, _T_1234) @[RVC.scala 223:94] + node _T_1236 = bits(io.in, 1, 1) @[RVC.scala 223:112] + node _T_1237 = eq(_T_1236, UInt<1>("h00")) @[RVC.scala 223:106] + node _T_1238 = and(_T_1235, _T_1237) @[RVC.scala 223:104] + node _T_1239 = or(_T_1228, _T_1238) @[RVC.scala 223:67] + node _T_1240 = bits(io.in, 14, 14) @[RVC.scala 224:12] + node _T_1241 = bits(io.in, 13, 13) @[RVC.scala 224:24] + node _T_1242 = eq(_T_1241, UInt<1>("h00")) @[RVC.scala 224:18] + node _T_1243 = and(_T_1240, _T_1242) @[RVC.scala 224:16] + node _T_1244 = bits(io.in, 0, 0) @[RVC.scala 224:37] + node _T_1245 = eq(_T_1244, UInt<1>("h00")) @[RVC.scala 224:31] + node _T_1246 = and(_T_1243, _T_1245) @[RVC.scala 224:29] + node _T_1247 = or(_T_1239, _T_1246) @[RVC.scala 223:117] + io.legal <= _T_1247 @[RVC.scala 204:14] + diff --git a/RVCExpander.v b/RVCExpander.v new file mode 100644 index 00000000..194a81a8 --- /dev/null +++ b/RVCExpander.v @@ -0,0 +1,404 @@ +module RVCExpander( + input clock, + input reset, + input [31:0] io_in, + output [31:0] io_out_bits, + output [4:0] io_out_rd, + output [4:0] io_out_rs1, + output [4:0] io_out_rs2, + output [4:0] io_out_rs3, + output io_rvc, + output io_legal +); + wire _T_3 = |io_in[12:5]; // @[RVC.scala 58:29] + wire [6:0] _T_4 = _T_3 ? 7'h13 : 7'h1f; // @[RVC.scala 58:20] + wire [4:0] _T_14 = {2'h1,io_in[4:2]}; // @[Cat.scala 29:58] + wire [29:0] _T_18 = {io_in[10:7],io_in[12:11],io_in[5],io_in[6],2'h0,5'h2,3'h0,2'h1,io_in[4:2],_T_4}; // @[Cat.scala 29:58] + wire [7:0] _T_28 = {io_in[6:5],io_in[12:10],3'h0}; // @[Cat.scala 29:58] + wire [4:0] _T_30 = {2'h1,io_in[9:7]}; // @[Cat.scala 29:58] + wire [27:0] _T_36 = {io_in[6:5],io_in[12:10],3'h0,2'h1,io_in[9:7],3'h3,2'h1,io_in[4:2],7'h7}; // @[Cat.scala 29:58] + wire [6:0] _T_50 = {io_in[5],io_in[12:10],io_in[6],2'h0}; // @[Cat.scala 29:58] + wire [26:0] _T_58 = {io_in[5],io_in[12:10],io_in[6],2'h0,2'h1,io_in[9:7],3'h2,2'h1,io_in[4:2],7'h3}; // @[Cat.scala 29:58] + wire [26:0] _T_80 = {io_in[5],io_in[12:10],io_in[6],2'h0,2'h1,io_in[9:7],3'h2,2'h1,io_in[4:2],7'h7}; // @[Cat.scala 29:58] + wire [26:0] _T_111 = {_T_50[6:5],2'h1,io_in[4:2],2'h1,io_in[9:7],3'h2,_T_50[4:0],7'h3f}; // @[Cat.scala 29:58] + wire [27:0] _T_138 = {_T_28[7:5],2'h1,io_in[4:2],2'h1,io_in[9:7],3'h3,_T_28[4:0],7'h27}; // @[Cat.scala 29:58] + wire [26:0] _T_169 = {_T_50[6:5],2'h1,io_in[4:2],2'h1,io_in[9:7],3'h2,_T_50[4:0],7'h23}; // @[Cat.scala 29:58] + wire [26:0] _T_200 = {_T_50[6:5],2'h1,io_in[4:2],2'h1,io_in[9:7],3'h2,_T_50[4:0],7'h27}; // @[Cat.scala 29:58] + wire [6:0] _T_211 = io_in[12] ? 7'h7f : 7'h0; // @[Bitwise.scala 72:12] + wire [11:0] _T_213 = {_T_211,io_in[6:2]}; // @[Cat.scala 29:58] + wire [31:0] _T_219 = {_T_211,io_in[6:2],io_in[11:7],3'h0,io_in[11:7],7'h13}; // @[Cat.scala 29:58] + wire [9:0] _T_228 = io_in[12] ? 10'h3ff : 10'h0; // @[Bitwise.scala 72:12] + wire [20:0] _T_243 = {_T_228,io_in[8],io_in[10:9],io_in[6],io_in[7],io_in[2],io_in[11],io_in[5:3],1'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_306 = {_T_243[20],_T_243[10:1],_T_243[11],_T_243[19:12],5'h1,7'h6f}; // @[Cat.scala 29:58] + wire [31:0] _T_321 = {_T_211,io_in[6:2],5'h0,3'h0,io_in[11:7],7'h13}; // @[Cat.scala 29:58] + wire _T_332 = |_T_213; // @[RVC.scala 95:29] + wire [6:0] _T_333 = _T_332 ? 7'h37 : 7'h3f; // @[RVC.scala 95:20] + wire [14:0] _T_336 = io_in[12] ? 15'h7fff : 15'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_339 = {_T_336,io_in[6:2],12'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_343 = {_T_339[31:12],io_in[11:7],_T_333}; // @[Cat.scala 29:58] + wire _T_351 = io_in[11:7] == 5'h0; // @[RVC.scala 97:14] + wire _T_353 = io_in[11:7] == 5'h2; // @[RVC.scala 97:27] + wire _T_354 = _T_351 | _T_353; // @[RVC.scala 97:21] + wire [6:0] _T_361 = _T_332 ? 7'h13 : 7'h1f; // @[RVC.scala 91:20] + wire [2:0] _T_364 = io_in[12] ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_379 = {_T_364,io_in[4:3],io_in[5],io_in[2],io_in[6],4'h0,io_in[11:7],3'h0,io_in[11:7],_T_361}; // @[Cat.scala 29:58] + wire [31:0] _T_386_bits = _T_354 ? _T_379 : _T_343; // @[RVC.scala 97:10] + wire [4:0] _T_386_rd = _T_354 ? io_in[11:7] : io_in[11:7]; // @[RVC.scala 97:10] + wire [4:0] _T_386_rs2 = _T_354 ? _T_14 : _T_14; // @[RVC.scala 97:10] + wire [4:0] _T_386_rs3 = _T_354 ? io_in[31:27] : io_in[31:27]; // @[RVC.scala 97:10] + wire [25:0] _T_397 = {io_in[12],io_in[6:2],2'h1,io_in[9:7],3'h5,2'h1,io_in[9:7],7'h13}; // @[Cat.scala 29:58] + wire [30:0] _GEN_172 = {{5'd0}, _T_397}; // @[RVC.scala 104:23] + wire [30:0] _T_409 = _GEN_172 | 31'h40000000; // @[RVC.scala 104:23] + wire [31:0] _T_422 = {_T_211,io_in[6:2],2'h1,io_in[9:7],3'h7,2'h1,io_in[9:7],7'h13}; // @[Cat.scala 29:58] + wire [2:0] _T_426 = {io_in[12],io_in[6:5]}; // @[Cat.scala 29:58] + wire _T_428 = io_in[6:5] == 2'h0; // @[RVC.scala 108:30] + wire [30:0] _T_429 = _T_428 ? 31'h40000000 : 31'h0; // @[RVC.scala 108:22] + wire [6:0] _T_431 = io_in[12] ? 7'h3b : 7'h33; // @[RVC.scala 109:22] + wire [2:0] _GEN_1 = 3'h1 == _T_426 ? 3'h4 : 3'h0; // @[Cat.scala 29:58] + wire [2:0] _GEN_2 = 3'h2 == _T_426 ? 3'h6 : _GEN_1; // @[Cat.scala 29:58] + wire [2:0] _GEN_3 = 3'h3 == _T_426 ? 3'h7 : _GEN_2; // @[Cat.scala 29:58] + wire [2:0] _GEN_4 = 3'h4 == _T_426 ? 3'h0 : _GEN_3; // @[Cat.scala 29:58] + wire [2:0] _GEN_5 = 3'h5 == _T_426 ? 3'h0 : _GEN_4; // @[Cat.scala 29:58] + wire [2:0] _GEN_6 = 3'h6 == _T_426 ? 3'h2 : _GEN_5; // @[Cat.scala 29:58] + wire [2:0] _GEN_7 = 3'h7 == _T_426 ? 3'h3 : _GEN_6; // @[Cat.scala 29:58] + wire [24:0] _T_441 = {2'h1,io_in[4:2],2'h1,io_in[9:7],_GEN_7,2'h1,io_in[9:7],_T_431}; // @[Cat.scala 29:58] + wire [30:0] _GEN_173 = {{6'd0}, _T_441}; // @[RVC.scala 110:43] + wire [30:0] _T_442 = _GEN_173 | _T_429; // @[RVC.scala 110:43] + wire [31:0] _T_443_0 = {{6'd0}, _T_397}; // @[RVC.scala 112:19 RVC.scala 112:19] + wire [31:0] _T_443_1 = {{1'd0}, _T_409}; // @[RVC.scala 112:19 RVC.scala 112:19] + wire [31:0] _GEN_9 = 2'h1 == io_in[11:10] ? _T_443_1 : _T_443_0; // @[RVC.scala 27:14] + wire [31:0] _GEN_10 = 2'h2 == io_in[11:10] ? _T_422 : _GEN_9; // @[RVC.scala 27:14] + wire [31:0] _T_443_3 = {{1'd0}, _T_442}; // @[RVC.scala 112:19 RVC.scala 112:19] + wire [31:0] _GEN_11 = 2'h3 == io_in[11:10] ? _T_443_3 : _GEN_10; // @[RVC.scala 27:14] + wire [31:0] _T_533 = {_T_243[20],_T_243[10:1],_T_243[11],_T_243[19:12],5'h0,7'h6f}; // @[Cat.scala 29:58] + wire [4:0] _T_542 = io_in[12] ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12] + wire [12:0] _T_551 = {_T_542,io_in[6:5],io_in[2],io_in[11:10],io_in[4:3],1'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_600 = {_T_551[12],_T_551[10:5],5'h0,2'h1,io_in[9:7],3'h0,_T_551[4:1],_T_551[11],7'h63}; // @[Cat.scala 29:58] + wire [31:0] _T_667 = {_T_551[12],_T_551[10:5],5'h0,2'h1,io_in[9:7],3'h1,_T_551[4:1],_T_551[11],7'h63}; // @[Cat.scala 29:58] + wire _T_673 = |io_in[11:7]; // @[RVC.scala 118:27] + wire [6:0] _T_674 = _T_673 ? 7'h3 : 7'h1f; // @[RVC.scala 118:23] + wire [25:0] _T_683 = {io_in[12],io_in[6:2],io_in[11:7],3'h1,io_in[11:7],7'h13}; // @[Cat.scala 29:58] + wire [28:0] _T_699 = {io_in[4:2],io_in[12],io_in[6:5],3'h0,5'h2,3'h3,io_in[11:7],7'h7}; // @[Cat.scala 29:58] + wire [27:0] _T_714 = {io_in[3:2],io_in[12],io_in[6:4],2'h0,5'h2,3'h2,io_in[11:7],_T_674}; // @[Cat.scala 29:58] + wire [27:0] _T_729 = {io_in[3:2],io_in[12],io_in[6:4],2'h0,5'h2,3'h2,io_in[11:7],7'h7}; // @[Cat.scala 29:58] + wire [24:0] _T_739 = {io_in[6:2],5'h0,3'h0,io_in[11:7],7'h33}; // @[Cat.scala 29:58] + wire [24:0] _T_750 = {io_in[6:2],io_in[11:7],3'h0,io_in[11:7],7'h33}; // @[Cat.scala 29:58] + wire [24:0] _T_761 = {io_in[6:2],io_in[11:7],3'h0,12'h67}; // @[Cat.scala 29:58] + wire [24:0] _T_763 = {_T_761[24:7],7'h1f}; // @[Cat.scala 29:58] + wire [24:0] _T_766 = _T_673 ? _T_761 : _T_763; // @[RVC.scala 139:33] + wire _T_772 = |io_in[6:2]; // @[RVC.scala 140:27] + wire [31:0] _T_743_bits = {{7'd0}, _T_739}; // @[RVC.scala 26:19 RVC.scala 27:14] + wire [31:0] _T_770_bits = {{7'd0}, _T_766}; // @[RVC.scala 26:19 RVC.scala 27:14] + wire [31:0] _T_773_bits = _T_772 ? _T_743_bits : _T_770_bits; // @[RVC.scala 140:22] + wire [4:0] _T_773_rd = _T_772 ? io_in[11:7] : 5'h0; // @[RVC.scala 140:22] + wire [4:0] _T_773_rs1 = _T_772 ? 5'h0 : io_in[11:7]; // @[RVC.scala 140:22] + wire [4:0] _T_773_rs2 = _T_772 ? io_in[6:2] : io_in[6:2]; // @[RVC.scala 140:22] + wire [4:0] _T_773_rs3 = _T_772 ? io_in[31:27] : io_in[31:27]; // @[RVC.scala 140:22] + wire [24:0] _T_779 = {io_in[6:2],io_in[11:7],3'h0,12'he7}; // @[Cat.scala 29:58] + wire [24:0] _T_781 = {_T_761[24:7],7'h73}; // @[Cat.scala 29:58] + wire [24:0] _T_782 = _T_781 | 25'h100000; // @[RVC.scala 142:46] + wire [24:0] _T_785 = _T_673 ? _T_779 : _T_782; // @[RVC.scala 143:33] + wire [31:0] _T_755_bits = {{7'd0}, _T_750}; // @[RVC.scala 26:19 RVC.scala 27:14] + wire [31:0] _T_789_bits = {{7'd0}, _T_785}; // @[RVC.scala 26:19 RVC.scala 27:14] + wire [31:0] _T_792_bits = _T_772 ? _T_755_bits : _T_789_bits; // @[RVC.scala 144:25] + wire [4:0] _T_792_rd = _T_772 ? io_in[11:7] : 5'h1; // @[RVC.scala 144:25] + wire [4:0] _T_792_rs1 = _T_772 ? io_in[11:7] : io_in[11:7]; // @[RVC.scala 144:25] + wire [31:0] _T_794_bits = io_in[12] ? _T_792_bits : _T_773_bits; // @[RVC.scala 145:10] + wire [4:0] _T_794_rd = io_in[12] ? _T_792_rd : _T_773_rd; // @[RVC.scala 145:10] + wire [4:0] _T_794_rs1 = io_in[12] ? _T_792_rs1 : _T_773_rs1; // @[RVC.scala 145:10] + wire [4:0] _T_794_rs2 = io_in[12] ? _T_773_rs2 : _T_773_rs2; // @[RVC.scala 145:10] + wire [4:0] _T_794_rs3 = io_in[12] ? _T_773_rs3 : _T_773_rs3; // @[RVC.scala 145:10] + wire [8:0] _T_798 = {io_in[9:7],io_in[12:10],3'h0}; // @[Cat.scala 29:58] + wire [28:0] _T_810 = {_T_798[8:5],io_in[6:2],5'h2,3'h3,_T_798[4:0],7'h27}; // @[Cat.scala 29:58] + wire [7:0] _T_818 = {io_in[8:7],io_in[12:9],2'h0}; // @[Cat.scala 29:58] + wire [27:0] _T_830 = {_T_818[7:5],io_in[6:2],5'h2,3'h2,_T_818[4:0],7'h23}; // @[Cat.scala 29:58] + wire [27:0] _T_850 = {_T_818[7:5],io_in[6:2],5'h2,3'h2,_T_818[4:0],7'h27}; // @[Cat.scala 29:58] + wire [4:0] _T_898 = {io_in[1:0],io_in[15:13]}; // @[Cat.scala 29:58] + wire [31:0] _T_24_bits = {{2'd0}, _T_18}; // @[RVC.scala 26:19 RVC.scala 27:14] + wire [31:0] _T_44_bits = {{4'd0}, _T_36}; // @[RVC.scala 26:19 RVC.scala 27:14] + wire [31:0] _GEN_17 = 5'h1 == _T_898 ? _T_44_bits : _T_24_bits; // @[RVC.scala 203:12] + wire [4:0] _GEN_18 = 5'h1 == _T_898 ? _T_14 : _T_14; // @[RVC.scala 203:12] + wire [4:0] _GEN_19 = 5'h1 == _T_898 ? _T_30 : 5'h2; // @[RVC.scala 203:12] + wire [4:0] _GEN_21 = 5'h1 == _T_898 ? io_in[31:27] : io_in[31:27]; // @[RVC.scala 203:12] + wire [31:0] _T_66_bits = {{5'd0}, _T_58}; // @[RVC.scala 26:19 RVC.scala 27:14] + wire [31:0] _GEN_22 = 5'h2 == _T_898 ? _T_66_bits : _GEN_17; // @[RVC.scala 203:12] + wire [4:0] _GEN_23 = 5'h2 == _T_898 ? _T_14 : _GEN_18; // @[RVC.scala 203:12] + wire [4:0] _GEN_24 = 5'h2 == _T_898 ? _T_30 : _GEN_19; // @[RVC.scala 203:12] + wire [4:0] _GEN_26 = 5'h2 == _T_898 ? io_in[31:27] : _GEN_21; // @[RVC.scala 203:12] + wire [31:0] _T_88_bits = {{5'd0}, _T_80}; // @[RVC.scala 26:19 RVC.scala 27:14] + wire [31:0] _GEN_27 = 5'h3 == _T_898 ? _T_88_bits : _GEN_22; // @[RVC.scala 203:12] + wire [4:0] _GEN_28 = 5'h3 == _T_898 ? _T_14 : _GEN_23; // @[RVC.scala 203:12] + wire [4:0] _GEN_29 = 5'h3 == _T_898 ? _T_30 : _GEN_24; // @[RVC.scala 203:12] + wire [4:0] _GEN_31 = 5'h3 == _T_898 ? io_in[31:27] : _GEN_26; // @[RVC.scala 203:12] + wire [31:0] _T_119_bits = {{5'd0}, _T_111}; // @[RVC.scala 26:19 RVC.scala 27:14] + wire [31:0] _GEN_32 = 5'h4 == _T_898 ? _T_119_bits : _GEN_27; // @[RVC.scala 203:12] + wire [4:0] _GEN_33 = 5'h4 == _T_898 ? _T_14 : _GEN_28; // @[RVC.scala 203:12] + wire [4:0] _GEN_34 = 5'h4 == _T_898 ? _T_30 : _GEN_29; // @[RVC.scala 203:12] + wire [4:0] _GEN_36 = 5'h4 == _T_898 ? io_in[31:27] : _GEN_31; // @[RVC.scala 203:12] + wire [31:0] _T_146_bits = {{4'd0}, _T_138}; // @[RVC.scala 26:19 RVC.scala 27:14] + wire [31:0] _GEN_37 = 5'h5 == _T_898 ? _T_146_bits : _GEN_32; // @[RVC.scala 203:12] + wire [4:0] _GEN_38 = 5'h5 == _T_898 ? _T_14 : _GEN_33; // @[RVC.scala 203:12] + wire [4:0] _GEN_39 = 5'h5 == _T_898 ? _T_30 : _GEN_34; // @[RVC.scala 203:12] + wire [4:0] _GEN_41 = 5'h5 == _T_898 ? io_in[31:27] : _GEN_36; // @[RVC.scala 203:12] + wire [31:0] _T_177_bits = {{5'd0}, _T_169}; // @[RVC.scala 26:19 RVC.scala 27:14] + wire [31:0] _GEN_42 = 5'h6 == _T_898 ? _T_177_bits : _GEN_37; // @[RVC.scala 203:12] + wire [4:0] _GEN_43 = 5'h6 == _T_898 ? _T_14 : _GEN_38; // @[RVC.scala 203:12] + wire [4:0] _GEN_44 = 5'h6 == _T_898 ? _T_30 : _GEN_39; // @[RVC.scala 203:12] + wire [4:0] _GEN_46 = 5'h6 == _T_898 ? io_in[31:27] : _GEN_41; // @[RVC.scala 203:12] + wire [31:0] _T_208_bits = {{5'd0}, _T_200}; // @[RVC.scala 26:19 RVC.scala 27:14] + wire [31:0] _GEN_47 = 5'h7 == _T_898 ? _T_208_bits : _GEN_42; // @[RVC.scala 203:12] + wire [4:0] _GEN_48 = 5'h7 == _T_898 ? _T_14 : _GEN_43; // @[RVC.scala 203:12] + wire [4:0] _GEN_49 = 5'h7 == _T_898 ? _T_30 : _GEN_44; // @[RVC.scala 203:12] + wire [4:0] _GEN_51 = 5'h7 == _T_898 ? io_in[31:27] : _GEN_46; // @[RVC.scala 203:12] + wire [31:0] _GEN_52 = 5'h8 == _T_898 ? _T_219 : _GEN_47; // @[RVC.scala 203:12] + wire [4:0] _GEN_53 = 5'h8 == _T_898 ? io_in[11:7] : _GEN_48; // @[RVC.scala 203:12] + wire [4:0] _GEN_54 = 5'h8 == _T_898 ? io_in[11:7] : _GEN_49; // @[RVC.scala 203:12] + wire [4:0] _GEN_55 = 5'h8 == _T_898 ? _T_14 : _GEN_48; // @[RVC.scala 203:12] + wire [4:0] _GEN_56 = 5'h8 == _T_898 ? io_in[31:27] : _GEN_51; // @[RVC.scala 203:12] + wire [31:0] _GEN_57 = 5'h9 == _T_898 ? _T_306 : _GEN_52; // @[RVC.scala 203:12] + wire [4:0] _GEN_58 = 5'h9 == _T_898 ? 5'h1 : _GEN_53; // @[RVC.scala 203:12] + wire [4:0] _GEN_59 = 5'h9 == _T_898 ? io_in[11:7] : _GEN_54; // @[RVC.scala 203:12] + wire [4:0] _GEN_60 = 5'h9 == _T_898 ? _T_14 : _GEN_55; // @[RVC.scala 203:12] + wire [4:0] _GEN_61 = 5'h9 == _T_898 ? io_in[31:27] : _GEN_56; // @[RVC.scala 203:12] + wire [31:0] _GEN_62 = 5'ha == _T_898 ? _T_321 : _GEN_57; // @[RVC.scala 203:12] + wire [4:0] _GEN_63 = 5'ha == _T_898 ? io_in[11:7] : _GEN_58; // @[RVC.scala 203:12] + wire [4:0] _GEN_64 = 5'ha == _T_898 ? 5'h0 : _GEN_59; // @[RVC.scala 203:12] + wire [4:0] _GEN_65 = 5'ha == _T_898 ? _T_14 : _GEN_60; // @[RVC.scala 203:12] + wire [4:0] _GEN_66 = 5'ha == _T_898 ? io_in[31:27] : _GEN_61; // @[RVC.scala 203:12] + wire [31:0] _GEN_67 = 5'hb == _T_898 ? _T_386_bits : _GEN_62; // @[RVC.scala 203:12] + wire [4:0] _GEN_68 = 5'hb == _T_898 ? _T_386_rd : _GEN_63; // @[RVC.scala 203:12] + wire [4:0] _GEN_69 = 5'hb == _T_898 ? _T_386_rd : _GEN_64; // @[RVC.scala 203:12] + wire [4:0] _GEN_70 = 5'hb == _T_898 ? _T_386_rs2 : _GEN_65; // @[RVC.scala 203:12] + wire [4:0] _GEN_71 = 5'hb == _T_898 ? _T_386_rs3 : _GEN_66; // @[RVC.scala 203:12] + wire [31:0] _GEN_72 = 5'hc == _T_898 ? _GEN_11 : _GEN_67; // @[RVC.scala 203:12] + wire [4:0] _GEN_73 = 5'hc == _T_898 ? _T_30 : _GEN_68; // @[RVC.scala 203:12] + wire [4:0] _GEN_74 = 5'hc == _T_898 ? _T_30 : _GEN_69; // @[RVC.scala 203:12] + wire [4:0] _GEN_75 = 5'hc == _T_898 ? _T_14 : _GEN_70; // @[RVC.scala 203:12] + wire [4:0] _GEN_76 = 5'hc == _T_898 ? io_in[31:27] : _GEN_71; // @[RVC.scala 203:12] + wire [31:0] _GEN_77 = 5'hd == _T_898 ? _T_533 : _GEN_72; // @[RVC.scala 203:12] + wire [4:0] _GEN_78 = 5'hd == _T_898 ? 5'h0 : _GEN_73; // @[RVC.scala 203:12] + wire [4:0] _GEN_79 = 5'hd == _T_898 ? _T_30 : _GEN_74; // @[RVC.scala 203:12] + wire [4:0] _GEN_80 = 5'hd == _T_898 ? _T_14 : _GEN_75; // @[RVC.scala 203:12] + wire [4:0] _GEN_81 = 5'hd == _T_898 ? io_in[31:27] : _GEN_76; // @[RVC.scala 203:12] + wire [31:0] _GEN_82 = 5'he == _T_898 ? _T_600 : _GEN_77; // @[RVC.scala 203:12] + wire [4:0] _GEN_83 = 5'he == _T_898 ? _T_30 : _GEN_78; // @[RVC.scala 203:12] + wire [4:0] _GEN_84 = 5'he == _T_898 ? _T_30 : _GEN_79; // @[RVC.scala 203:12] + wire [4:0] _GEN_85 = 5'he == _T_898 ? 5'h0 : _GEN_80; // @[RVC.scala 203:12] + wire [4:0] _GEN_86 = 5'he == _T_898 ? io_in[31:27] : _GEN_81; // @[RVC.scala 203:12] + wire [31:0] _GEN_87 = 5'hf == _T_898 ? _T_667 : _GEN_82; // @[RVC.scala 203:12] + wire [4:0] _GEN_88 = 5'hf == _T_898 ? 5'h0 : _GEN_83; // @[RVC.scala 203:12] + wire [4:0] _GEN_89 = 5'hf == _T_898 ? _T_30 : _GEN_84; // @[RVC.scala 203:12] + wire [4:0] _GEN_90 = 5'hf == _T_898 ? 5'h0 : _GEN_85; // @[RVC.scala 203:12] + wire [4:0] _GEN_91 = 5'hf == _T_898 ? io_in[31:27] : _GEN_86; // @[RVC.scala 203:12] + wire [31:0] _T_688_bits = {{6'd0}, _T_683}; // @[RVC.scala 26:19 RVC.scala 27:14] + wire [31:0] _GEN_92 = 5'h10 == _T_898 ? _T_688_bits : _GEN_87; // @[RVC.scala 203:12] + wire [4:0] _GEN_93 = 5'h10 == _T_898 ? io_in[11:7] : _GEN_88; // @[RVC.scala 203:12] + wire [4:0] _GEN_94 = 5'h10 == _T_898 ? io_in[11:7] : _GEN_89; // @[RVC.scala 203:12] + wire [4:0] _GEN_95 = 5'h10 == _T_898 ? io_in[6:2] : _GEN_90; // @[RVC.scala 203:12] + wire [4:0] _GEN_96 = 5'h10 == _T_898 ? io_in[31:27] : _GEN_91; // @[RVC.scala 203:12] + wire [31:0] _T_703_bits = {{3'd0}, _T_699}; // @[RVC.scala 26:19 RVC.scala 27:14] + wire [31:0] _GEN_97 = 5'h11 == _T_898 ? _T_703_bits : _GEN_92; // @[RVC.scala 203:12] + wire [4:0] _GEN_98 = 5'h11 == _T_898 ? io_in[11:7] : _GEN_93; // @[RVC.scala 203:12] + wire [4:0] _GEN_99 = 5'h11 == _T_898 ? 5'h2 : _GEN_94; // @[RVC.scala 203:12] + wire [4:0] _GEN_100 = 5'h11 == _T_898 ? io_in[6:2] : _GEN_95; // @[RVC.scala 203:12] + wire [4:0] _GEN_101 = 5'h11 == _T_898 ? io_in[31:27] : _GEN_96; // @[RVC.scala 203:12] + wire [31:0] _T_718_bits = {{4'd0}, _T_714}; // @[RVC.scala 26:19 RVC.scala 27:14] + wire [31:0] _GEN_102 = 5'h12 == _T_898 ? _T_718_bits : _GEN_97; // @[RVC.scala 203:12] + wire [4:0] _GEN_103 = 5'h12 == _T_898 ? io_in[11:7] : _GEN_98; // @[RVC.scala 203:12] + wire [4:0] _GEN_104 = 5'h12 == _T_898 ? 5'h2 : _GEN_99; // @[RVC.scala 203:12] + wire [4:0] _GEN_105 = 5'h12 == _T_898 ? io_in[6:2] : _GEN_100; // @[RVC.scala 203:12] + wire [4:0] _GEN_106 = 5'h12 == _T_898 ? io_in[31:27] : _GEN_101; // @[RVC.scala 203:12] + wire [31:0] _T_733_bits = {{4'd0}, _T_729}; // @[RVC.scala 26:19 RVC.scala 27:14] + wire [31:0] _GEN_107 = 5'h13 == _T_898 ? _T_733_bits : _GEN_102; // @[RVC.scala 203:12] + wire [4:0] _GEN_108 = 5'h13 == _T_898 ? io_in[11:7] : _GEN_103; // @[RVC.scala 203:12] + wire [4:0] _GEN_109 = 5'h13 == _T_898 ? 5'h2 : _GEN_104; // @[RVC.scala 203:12] + wire [4:0] _GEN_110 = 5'h13 == _T_898 ? io_in[6:2] : _GEN_105; // @[RVC.scala 203:12] + wire [4:0] _GEN_111 = 5'h13 == _T_898 ? io_in[31:27] : _GEN_106; // @[RVC.scala 203:12] + wire [31:0] _GEN_112 = 5'h14 == _T_898 ? _T_794_bits : _GEN_107; // @[RVC.scala 203:12] + wire [4:0] _GEN_113 = 5'h14 == _T_898 ? _T_794_rd : _GEN_108; // @[RVC.scala 203:12] + wire [4:0] _GEN_114 = 5'h14 == _T_898 ? _T_794_rs1 : _GEN_109; // @[RVC.scala 203:12] + wire [4:0] _GEN_115 = 5'h14 == _T_898 ? _T_794_rs2 : _GEN_110; // @[RVC.scala 203:12] + wire [4:0] _GEN_116 = 5'h14 == _T_898 ? _T_794_rs3 : _GEN_111; // @[RVC.scala 203:12] + wire [31:0] _T_814_bits = {{3'd0}, _T_810}; // @[RVC.scala 26:19 RVC.scala 27:14] + wire [31:0] _GEN_117 = 5'h15 == _T_898 ? _T_814_bits : _GEN_112; // @[RVC.scala 203:12] + wire [4:0] _GEN_118 = 5'h15 == _T_898 ? io_in[11:7] : _GEN_113; // @[RVC.scala 203:12] + wire [4:0] _GEN_119 = 5'h15 == _T_898 ? 5'h2 : _GEN_114; // @[RVC.scala 203:12] + wire [4:0] _GEN_120 = 5'h15 == _T_898 ? io_in[6:2] : _GEN_115; // @[RVC.scala 203:12] + wire [4:0] _GEN_121 = 5'h15 == _T_898 ? io_in[31:27] : _GEN_116; // @[RVC.scala 203:12] + wire [31:0] _T_834_bits = {{4'd0}, _T_830}; // @[RVC.scala 26:19 RVC.scala 27:14] + wire [31:0] _GEN_122 = 5'h16 == _T_898 ? _T_834_bits : _GEN_117; // @[RVC.scala 203:12] + wire [4:0] _GEN_123 = 5'h16 == _T_898 ? io_in[11:7] : _GEN_118; // @[RVC.scala 203:12] + wire [4:0] _GEN_124 = 5'h16 == _T_898 ? 5'h2 : _GEN_119; // @[RVC.scala 203:12] + wire [4:0] _GEN_125 = 5'h16 == _T_898 ? io_in[6:2] : _GEN_120; // @[RVC.scala 203:12] + wire [4:0] _GEN_126 = 5'h16 == _T_898 ? io_in[31:27] : _GEN_121; // @[RVC.scala 203:12] + wire [31:0] _T_854_bits = {{4'd0}, _T_850}; // @[RVC.scala 26:19 RVC.scala 27:14] + wire [31:0] _GEN_127 = 5'h17 == _T_898 ? _T_854_bits : _GEN_122; // @[RVC.scala 203:12] + wire [4:0] _GEN_128 = 5'h17 == _T_898 ? io_in[11:7] : _GEN_123; // @[RVC.scala 203:12] + wire [4:0] _GEN_129 = 5'h17 == _T_898 ? 5'h2 : _GEN_124; // @[RVC.scala 203:12] + wire [4:0] _GEN_130 = 5'h17 == _T_898 ? io_in[6:2] : _GEN_125; // @[RVC.scala 203:12] + wire [4:0] _GEN_131 = 5'h17 == _T_898 ? io_in[31:27] : _GEN_126; // @[RVC.scala 203:12] + wire [31:0] _GEN_132 = 5'h18 == _T_898 ? io_in : _GEN_127; // @[RVC.scala 203:12] + wire [4:0] _GEN_133 = 5'h18 == _T_898 ? io_in[11:7] : _GEN_128; // @[RVC.scala 203:12] + wire [4:0] _GEN_134 = 5'h18 == _T_898 ? io_in[19:15] : _GEN_129; // @[RVC.scala 203:12] + wire [4:0] _GEN_135 = 5'h18 == _T_898 ? io_in[24:20] : _GEN_130; // @[RVC.scala 203:12] + wire [4:0] _GEN_136 = 5'h18 == _T_898 ? io_in[31:27] : _GEN_131; // @[RVC.scala 203:12] + wire [31:0] _GEN_137 = 5'h19 == _T_898 ? io_in : _GEN_132; // @[RVC.scala 203:12] + wire [4:0] _GEN_138 = 5'h19 == _T_898 ? io_in[11:7] : _GEN_133; // @[RVC.scala 203:12] + wire [4:0] _GEN_139 = 5'h19 == _T_898 ? io_in[19:15] : _GEN_134; // @[RVC.scala 203:12] + wire [4:0] _GEN_140 = 5'h19 == _T_898 ? io_in[24:20] : _GEN_135; // @[RVC.scala 203:12] + wire [4:0] _GEN_141 = 5'h19 == _T_898 ? io_in[31:27] : _GEN_136; // @[RVC.scala 203:12] + wire [31:0] _GEN_142 = 5'h1a == _T_898 ? io_in : _GEN_137; // @[RVC.scala 203:12] + wire [4:0] _GEN_143 = 5'h1a == _T_898 ? io_in[11:7] : _GEN_138; // @[RVC.scala 203:12] + wire [4:0] _GEN_144 = 5'h1a == _T_898 ? io_in[19:15] : _GEN_139; // @[RVC.scala 203:12] + wire [4:0] _GEN_145 = 5'h1a == _T_898 ? io_in[24:20] : _GEN_140; // @[RVC.scala 203:12] + wire [4:0] _GEN_146 = 5'h1a == _T_898 ? io_in[31:27] : _GEN_141; // @[RVC.scala 203:12] + wire [31:0] _GEN_147 = 5'h1b == _T_898 ? io_in : _GEN_142; // @[RVC.scala 203:12] + wire [4:0] _GEN_148 = 5'h1b == _T_898 ? io_in[11:7] : _GEN_143; // @[RVC.scala 203:12] + wire [4:0] _GEN_149 = 5'h1b == _T_898 ? io_in[19:15] : _GEN_144; // @[RVC.scala 203:12] + wire [4:0] _GEN_150 = 5'h1b == _T_898 ? io_in[24:20] : _GEN_145; // @[RVC.scala 203:12] + wire [4:0] _GEN_151 = 5'h1b == _T_898 ? io_in[31:27] : _GEN_146; // @[RVC.scala 203:12] + wire [31:0] _GEN_152 = 5'h1c == _T_898 ? io_in : _GEN_147; // @[RVC.scala 203:12] + wire [4:0] _GEN_153 = 5'h1c == _T_898 ? io_in[11:7] : _GEN_148; // @[RVC.scala 203:12] + wire [4:0] _GEN_154 = 5'h1c == _T_898 ? io_in[19:15] : _GEN_149; // @[RVC.scala 203:12] + wire [4:0] _GEN_155 = 5'h1c == _T_898 ? io_in[24:20] : _GEN_150; // @[RVC.scala 203:12] + wire [4:0] _GEN_156 = 5'h1c == _T_898 ? io_in[31:27] : _GEN_151; // @[RVC.scala 203:12] + wire [31:0] _GEN_157 = 5'h1d == _T_898 ? io_in : _GEN_152; // @[RVC.scala 203:12] + wire [4:0] _GEN_158 = 5'h1d == _T_898 ? io_in[11:7] : _GEN_153; // @[RVC.scala 203:12] + wire [4:0] _GEN_159 = 5'h1d == _T_898 ? io_in[19:15] : _GEN_154; // @[RVC.scala 203:12] + wire [4:0] _GEN_160 = 5'h1d == _T_898 ? io_in[24:20] : _GEN_155; // @[RVC.scala 203:12] + wire [4:0] _GEN_161 = 5'h1d == _T_898 ? io_in[31:27] : _GEN_156; // @[RVC.scala 203:12] + wire [31:0] _GEN_162 = 5'h1e == _T_898 ? io_in : _GEN_157; // @[RVC.scala 203:12] + wire [4:0] _GEN_163 = 5'h1e == _T_898 ? io_in[11:7] : _GEN_158; // @[RVC.scala 203:12] + wire [4:0] _GEN_164 = 5'h1e == _T_898 ? io_in[19:15] : _GEN_159; // @[RVC.scala 203:12] + wire [4:0] _GEN_165 = 5'h1e == _T_898 ? io_in[24:20] : _GEN_160; // @[RVC.scala 203:12] + wire [4:0] _GEN_166 = 5'h1e == _T_898 ? io_in[31:27] : _GEN_161; // @[RVC.scala 203:12] + wire _T_900 = ~io_in[13]; // @[RVC.scala 204:18] + wire _T_902 = ~io_in[12]; // @[RVC.scala 204:31] + wire _T_903 = _T_900 & _T_902; // @[RVC.scala 204:29] + wire _T_905 = _T_903 & io_in[11]; // @[RVC.scala 204:42] + wire _T_907 = _T_905 & io_in[1]; // @[RVC.scala 204:54] + wire _T_909 = ~io_in[0]; // @[RVC.scala 204:65] + wire _T_910 = _T_907 & _T_909; // @[RVC.scala 204:63] + wire _T_917 = _T_903 & io_in[6]; // @[RVC.scala 205:32] + wire _T_919 = _T_917 & io_in[1]; // @[RVC.scala 205:43] + wire _T_922 = _T_919 & _T_909; // @[RVC.scala 205:52] + wire _T_923 = _T_910 | _T_922; // @[RVC.scala 204:76] + wire _T_925 = ~io_in[15]; // @[RVC.scala 206:8] + wire _T_928 = _T_925 & _T_900; // @[RVC.scala 206:19] + wire _T_931 = ~io_in[1]; // @[RVC.scala 206:43] + wire _T_932 = io_in[11] >> _T_931; // @[RVC.scala 206:42] + wire _T_934 = _T_928 & _T_932; // @[RVC.scala 206:32] + wire _T_935 = _T_923 | _T_934; // @[RVC.scala 205:65] + wire _T_942 = _T_903 & io_in[5]; // @[RVC.scala 207:32] + wire _T_944 = _T_942 & io_in[1]; // @[RVC.scala 207:41] + wire _T_947 = _T_944 & _T_909; // @[RVC.scala 207:50] + wire _T_948 = _T_935 | _T_947; // @[RVC.scala 206:54] + wire _T_955 = _T_903 & io_in[10]; // @[RVC.scala 208:32] + wire _T_958 = _T_955 & _T_931; // @[RVC.scala 208:42] + wire _T_960 = _T_958 & io_in[0]; // @[RVC.scala 208:54] + wire _T_961 = _T_948 | _T_960; // @[RVC.scala 207:63] + wire _T_968 = _T_928 & io_in[6]; // @[RVC.scala 209:32] + wire _T_971 = _T_968 & _T_931; // @[RVC.scala 209:41] + wire _T_972 = _T_961 | _T_971; // @[RVC.scala 208:64] + wire _T_976 = io_in[15] & _T_902; // @[RVC.scala 209:65] + wire _T_979 = _T_976 & _T_931; // @[RVC.scala 209:78] + wire _T_981 = _T_979 & io_in[0]; // @[RVC.scala 209:90] + wire _T_982 = _T_972 | _T_981; // @[RVC.scala 209:54] + wire _T_989 = _T_903 & io_in[9]; // @[RVC.scala 210:32] + wire _T_991 = _T_989 & io_in[1]; // @[RVC.scala 210:41] + wire _T_994 = _T_991 & _T_909; // @[RVC.scala 210:50] + wire _T_995 = _T_982 | _T_994; // @[RVC.scala 209:100] + wire _T_999 = _T_902 & io_in[6]; // @[RVC.scala 211:19] + wire _T_1002 = _T_999 & _T_931; // @[RVC.scala 211:28] + wire _T_1004 = _T_1002 & io_in[0]; // @[RVC.scala 211:40] + wire _T_1005 = _T_995 | _T_1004; // @[RVC.scala 210:63] + wire _T_1012 = _T_928 & io_in[5]; // @[RVC.scala 212:32] + wire _T_1015 = _T_1012 & _T_931; // @[RVC.scala 212:41] + wire _T_1016 = _T_1005 | _T_1015; // @[RVC.scala 211:50] + wire _T_1023 = _T_903 & io_in[8]; // @[RVC.scala 213:32] + wire _T_1025 = _T_1023 & io_in[1]; // @[RVC.scala 213:41] + wire _T_1028 = _T_1025 & _T_909; // @[RVC.scala 213:50] + wire _T_1029 = _T_1016 | _T_1028; // @[RVC.scala 212:54] + wire _T_1033 = _T_902 & io_in[5]; // @[RVC.scala 214:19] + wire _T_1036 = _T_1033 & _T_931; // @[RVC.scala 214:28] + wire _T_1038 = _T_1036 & io_in[0]; // @[RVC.scala 214:40] + wire _T_1039 = _T_1029 | _T_1038; // @[RVC.scala 213:63] + wire _T_1046 = _T_928 & io_in[10]; // @[RVC.scala 215:32] + wire _T_1049 = _T_1046 & _T_931; // @[RVC.scala 215:42] + wire _T_1050 = _T_1039 | _T_1049; // @[RVC.scala 214:50] + wire _T_1057 = _T_903 & io_in[7]; // @[RVC.scala 215:82] + wire _T_1059 = _T_1057 & io_in[1]; // @[RVC.scala 215:91] + wire _T_1062 = _T_1059 & _T_909; // @[RVC.scala 215:100] + wire _T_1063 = _T_1050 | _T_1062; // @[RVC.scala 215:55] + wire _T_1066 = io_in[12] & io_in[11]; // @[RVC.scala 216:16] + wire _T_1068 = ~io_in[10]; // @[RVC.scala 216:28] + wire _T_1069 = _T_1066 & _T_1068; // @[RVC.scala 216:26] + wire _T_1072 = _T_1069 & _T_931; // @[RVC.scala 216:39] + wire _T_1074 = _T_1072 & io_in[0]; // @[RVC.scala 216:51] + wire _T_1075 = _T_1063 | _T_1074; // @[RVC.scala 215:113] + wire _T_1082 = _T_928 & io_in[9]; // @[RVC.scala 216:88] + wire _T_1085 = _T_1082 & _T_931; // @[RVC.scala 216:97] + wire _T_1086 = _T_1075 | _T_1085; // @[RVC.scala 216:61] + wire _T_1093 = _T_903 & io_in[4]; // @[RVC.scala 217:32] + wire _T_1095 = _T_1093 & io_in[1]; // @[RVC.scala 217:41] + wire _T_1098 = _T_1095 & _T_909; // @[RVC.scala 217:50] + wire _T_1099 = _T_1086 | _T_1098; // @[RVC.scala 216:110] + wire _T_1102 = io_in[13] & io_in[12]; // @[RVC.scala 217:74] + wire _T_1105 = _T_1102 & _T_931; // @[RVC.scala 217:84] + wire _T_1107 = _T_1105 & io_in[0]; // @[RVC.scala 217:96] + wire _T_1108 = _T_1099 | _T_1107; // @[RVC.scala 217:63] + wire _T_1115 = _T_928 & io_in[8]; // @[RVC.scala 218:32] + wire _T_1118 = _T_1115 & _T_931; // @[RVC.scala 218:41] + wire _T_1119 = _T_1108 | _T_1118; // @[RVC.scala 217:106] + wire _T_1126 = _T_903 & io_in[3]; // @[RVC.scala 218:81] + wire _T_1128 = _T_1126 & io_in[1]; // @[RVC.scala 218:90] + wire _T_1131 = _T_1128 & _T_909; // @[RVC.scala 218:99] + wire _T_1132 = _T_1119 | _T_1131; // @[RVC.scala 218:54] + wire _T_1135 = io_in[13] & io_in[4]; // @[RVC.scala 219:16] + wire _T_1138 = _T_1135 & _T_931; // @[RVC.scala 219:25] + wire _T_1140 = _T_1138 & io_in[0]; // @[RVC.scala 219:37] + wire _T_1141 = _T_1132 | _T_1140; // @[RVC.scala 218:112] + wire _T_1148 = _T_903 & io_in[2]; // @[RVC.scala 219:74] + wire _T_1150 = _T_1148 & io_in[1]; // @[RVC.scala 219:83] + wire _T_1153 = _T_1150 & _T_909; // @[RVC.scala 219:92] + wire _T_1154 = _T_1141 | _T_1153; // @[RVC.scala 219:47] + wire _T_1161 = _T_928 & io_in[7]; // @[RVC.scala 220:32] + wire _T_1164 = _T_1161 & _T_931; // @[RVC.scala 220:41] + wire _T_1165 = _T_1154 | _T_1164; // @[RVC.scala 219:105] + wire _T_1168 = io_in[13] & io_in[3]; // @[RVC.scala 220:65] + wire _T_1171 = _T_1168 & _T_931; // @[RVC.scala 220:74] + wire _T_1173 = _T_1171 & io_in[0]; // @[RVC.scala 220:86] + wire _T_1174 = _T_1165 | _T_1173; // @[RVC.scala 220:54] + wire _T_1177 = io_in[13] & io_in[2]; // @[RVC.scala 221:16] + wire _T_1180 = _T_1177 & _T_931; // @[RVC.scala 221:25] + wire _T_1182 = _T_1180 & io_in[0]; // @[RVC.scala 221:37] + wire _T_1183 = _T_1174 | _T_1182; // @[RVC.scala 220:96] + wire _T_1187 = io_in[14] & _T_900; // @[RVC.scala 221:58] + wire _T_1190 = _T_1187 & _T_931; // @[RVC.scala 221:71] + wire _T_1191 = _T_1183 | _T_1190; // @[RVC.scala 221:47] + wire _T_1193 = ~io_in[14]; // @[RVC.scala 222:8] + wire _T_1196 = _T_1193 & _T_902; // @[RVC.scala 222:19] + wire _T_1199 = _T_1196 & _T_931; // @[RVC.scala 222:32] + wire _T_1201 = _T_1199 & io_in[0]; // @[RVC.scala 222:44] + wire _T_1202 = _T_1191 | _T_1201; // @[RVC.scala 221:84] + wire _T_1206 = io_in[15] & _T_900; // @[RVC.scala 222:65] + wire _T_1208 = _T_1206 & io_in[12]; // @[RVC.scala 222:78] + wire _T_1210 = _T_1208 & io_in[1]; // @[RVC.scala 222:88] + wire _T_1213 = _T_1210 & _T_909; // @[RVC.scala 222:97] + wire _T_1214 = _T_1202 | _T_1213; // @[RVC.scala 222:54] + wire _T_1222 = _T_928 & _T_902; // @[RVC.scala 223:32] + wire _T_1224 = _T_1222 & io_in[1]; // @[RVC.scala 223:45] + wire _T_1227 = _T_1224 & _T_909; // @[RVC.scala 223:54] + wire _T_1228 = _T_1214 | _T_1227; // @[RVC.scala 222:110] + wire _T_1235 = _T_928 & io_in[12]; // @[RVC.scala 223:94] + wire _T_1238 = _T_1235 & _T_931; // @[RVC.scala 223:104] + wire _T_1239 = _T_1228 | _T_1238; // @[RVC.scala 223:67] + wire _T_1246 = _T_1187 & _T_909; // @[RVC.scala 224:29] + assign io_out_bits = 5'h1f == _T_898 ? io_in : _GEN_162; // @[RVC.scala 203:12] + assign io_out_rd = 5'h1f == _T_898 ? io_in[11:7] : _GEN_163; // @[RVC.scala 203:12] + assign io_out_rs1 = 5'h1f == _T_898 ? io_in[19:15] : _GEN_164; // @[RVC.scala 203:12] + assign io_out_rs2 = 5'h1f == _T_898 ? io_in[24:20] : _GEN_165; // @[RVC.scala 203:12] + assign io_out_rs3 = 5'h1f == _T_898 ? io_in[31:27] : _GEN_166; // @[RVC.scala 203:12] + assign io_rvc = io_in[1:0] != 2'h3; // @[RVC.scala 201:12] + assign io_legal = _T_1239 | _T_1246; // @[RVC.scala 204:14] +endmodule diff --git a/build.sbt b/build.sbt new file mode 100644 index 00000000..dfa04954 --- /dev/null +++ b/build.sbt @@ -0,0 +1,55 @@ +// See README.md for license details. + +def scalacOptionsVersion(scalaVersion: String): Seq[String] = { + Seq() ++ { + // If we're building with Scala > 2.11, enable the compile option + // switch to support our anonymous Bundle definitions: + // https://github.com/scala/bug/issues/10047 + CrossVersion.partialVersion(scalaVersion) match { + case Some((2, scalaMajor: Long)) if scalaMajor < 12 => Seq() + case _ => Seq("-Xsource:2.11") + } + } +} + +def javacOptionsVersion(scalaVersion: String): Seq[String] = { + Seq() ++ { + // Scala 2.12 requires Java 8. We continue to generate + // Java 7 compatible code for Scala 2.11 + // for compatibility with old clients. + CrossVersion.partialVersion(scalaVersion) match { + case Some((2, scalaMajor: Long)) if scalaMajor < 12 => + Seq("-source", "1.7", "-target", "1.7") + case _ => + Seq("-source", "1.8", "-target", "1.8") + } + } +} + +name := "chisel-module-template" + +version := "3.3.0" + +scalaVersion := "2.12.10" + +crossScalaVersions := Seq("2.12.10", "2.11.12") + +resolvers ++= Seq( + Resolver.sonatypeRepo("snapshots"), + Resolver.sonatypeRepo("releases") +) + +addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.0" cross CrossVersion.full) + +// Provide a managed dependency on X if -DXVersion="" is supplied on the command line. +val defaultVersions = Seq( + "chisel-iotesters" -> "1.4.1+", + "chiseltest" -> "0.2.1+" + ) + +libraryDependencies ++= defaultVersions.map { case (dep, ver) => + "edu.berkeley.cs" %% dep % sys.props.getOrElse(dep + "Version", ver) } + +scalacOptions ++= scalacOptionsVersion(scalaVersion.value) + +javacOptions ++= javacOptionsVersion(scalaVersion.value) diff --git a/caller.anno.json b/caller.anno.json new file mode 100644 index 00000000..93e3741a --- /dev/null +++ b/caller.anno.json @@ -0,0 +1,25 @@ +[ + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~caller|caller>io_out", + "sources":[ + "~caller|caller>io_in" + ] + }, + { + "class":"firrtl.EmitCircuitAnnotation", + "emitter":"firrtl.VerilogEmitter" + }, + { + "class":"firrtl.options.TargetDirAnnotation", + "directory":"." + }, + { + "class":"firrtl.options.OutputAnnotationFileAnnotation", + "file":"caller" + }, + { + "class":"firrtl.transforms.BlackBoxTargetDirAnno", + "targetDir":"." + } +] \ No newline at end of file diff --git a/caller.fir b/caller.fir new file mode 100644 index 00000000..62d6fd47 --- /dev/null +++ b/caller.fir @@ -0,0 +1,20 @@ +;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10 +circuit caller : + module rvdff : + input clock : Clock + input reset : Reset + output io : {flip in : UInt<32>, out : UInt} + + io.out <= io.in @[GCD.scala 12:10] + + module caller : + input clock : Clock + input reset : UInt<1> + output io : {flip in : UInt<32>, out : UInt} + + inst u0 of rvdff @[GCD.scala 21:18] + u0.clock <= clock + u0.reset <= reset + io.out <= u0.io.out @[GCD.scala 22:6] + u0.io.in <= io.in @[GCD.scala 22:6] + diff --git a/caller.v b/caller.v new file mode 100644 index 00000000..af01ec71 --- /dev/null +++ b/caller.v @@ -0,0 +1,21 @@ +module rvdff( + input [31:0] io_in, + output [31:0] io_out +); + assign io_out = io_in; // @[GCD.scala 12:10] +endmodule +module caller( + input clock, + input reset, + input [31:0] io_in, + output [31:0] io_out +); + wire [31:0] u0_io_in; // @[GCD.scala 21:18] + wire [31:0] u0_io_out; // @[GCD.scala 21:18] + rvdff u0 ( // @[GCD.scala 21:18] + .io_in(u0_io_in), + .io_out(u0_io_out) + ); + assign io_out = u0_io_out; // @[GCD.scala 22:6] + assign u0_io_in = io_in; // @[GCD.scala 22:6] +endmodule diff --git a/el2_dec_dec_ctl.anno.json b/el2_dec_dec_ctl.anno.json new file mode 100644 index 00000000..f75b78b2 --- /dev/null +++ b/el2_dec_dec_ctl.anno.json @@ -0,0 +1,374 @@ +[ + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_rd", + "sources":[ + "~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_presync", + "sources":[ + "~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_rs1_sign", + "sources":[ + "~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_rs2", + "sources":[ + "~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_pc", + "sources":[ + "~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_load", + "sources":[ + "~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_csr_clr", + "sources":[ + "~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_alu", + "sources":[ + "~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_mul", + "sources":[ + "~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_imm12", + "sources":[ + "~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_beq", + "sources":[ + "~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_sra", + "sources":[ + "~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_ebreak", + "sources":[ + "~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_by", + "sources":[ + "~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_sub", + "sources":[ + "~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + 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+ ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_add", + "sources":[ + "~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_land", + "sources":[ + "~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_half", + "sources":[ + "~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_word", + "sources":[ + "~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_bne", + "sources":[ + "~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_csr_read", + "sources":[ + "~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_lor", + "sources":[ + "~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_csr_set", + "sources":[ + "~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_srl", + "sources":[ + "~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_low", + "sources":[ + "~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_ecall", + "sources":[ + "~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_condbr", + "sources":[ + "~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_legal", + "sources":[ + "~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_lsu", + "sources":[ + "~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_postsync", + "sources":[ + "~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_imm20", + "sources":[ + "~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_rs2_sign", + "sources":[ + "~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_dec_ctl|el2_dec_dec_ctl>io_out_shimm5", + "sources":[ + "~el2_dec_dec_ctl|el2_dec_dec_ctl>io_ins" + ] + }, + { + "class":"logger.LogLevelAnnotation", + "globalLogLevel":{ + + } + }, + { + "class":"firrtl.EmitCircuitAnnotation", + "emitter":"firrtl.VerilogEmitter" + }, + { + "class":"firrtl.options.TargetDirAnnotation", + "directory":"." + }, + { + "class":"firrtl.options.OutputAnnotationFileAnnotation", + "file":"el2_dec_dec_ctl" + }, + { + "class":"firrtl.transforms.BlackBoxTargetDirAnno", + "targetDir":"." + } +] \ No newline at end of file diff --git a/el2_dec_dec_ctl.fir b/el2_dec_dec_ctl.fir new file mode 100644 index 00000000..85decf02 --- /dev/null +++ b/el2_dec_dec_ctl.fir @@ -0,0 +1,2040 @@ +;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10 +circuit el2_dec_dec_ctl : + module el2_dec_dec_ctl : + input clock : Clock + input reset : UInt<1> + output io : {flip ins : UInt<32>, out : {alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>}} + + node _T = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 72:23] + node _T_1 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 72:35] + node _T_2 = or(_T, _T_1) @[el2_dec_dec_ctl.scala 72:27] + node _T_3 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 72:49] + node _T_4 = eq(_T_3, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 72:42] + node _T_5 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 72:60] + node _T_6 = and(_T_4, _T_5) @[el2_dec_dec_ctl.scala 72:53] + node _T_7 = or(_T_2, _T_6) @[el2_dec_dec_ctl.scala 72:39] + node _T_8 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 72:75] + node _T_9 = eq(_T_8, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 72:68] + node _T_10 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 72:85] + node _T_11 = and(_T_9, _T_10) @[el2_dec_dec_ctl.scala 72:78] + node _T_12 = or(_T_7, _T_11) @[el2_dec_dec_ctl.scala 72:65] + io.out.alu <= _T_12 @[el2_dec_dec_ctl.scala 72:14] + node _T_13 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_14 = eq(_T_13, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_15 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_16 = eq(_T_15, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_17 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_18 = eq(_T_17, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_19 = and(_T_14, _T_16) @[el2_dec_dec_ctl.scala 73:51] + node _T_20 = and(_T_19, _T_18) @[el2_dec_dec_ctl.scala 73:51] + node _T_21 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_22 = eq(_T_21, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_23 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 67:33] + node _T_24 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_25 = eq(_T_24, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_26 = and(_T_22, _T_23) @[el2_dec_dec_ctl.scala 73:90] + node _T_27 = and(_T_26, _T_25) @[el2_dec_dec_ctl.scala 73:90] + node _T_28 = or(_T_20, _T_27) @[el2_dec_dec_ctl.scala 73:55] + node _T_29 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:33] + node _T_30 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_31 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_32 = eq(_T_31, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_33 = and(_T_29, _T_30) @[el2_dec_dec_ctl.scala 74:37] + node _T_34 = and(_T_33, _T_32) @[el2_dec_dec_ctl.scala 74:37] + node _T_35 = or(_T_28, _T_34) @[el2_dec_dec_ctl.scala 73:94] + node _T_36 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_37 = eq(_T_36, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_38 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 67:33] + node _T_39 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_40 = eq(_T_39, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_41 = and(_T_37, _T_38) @[el2_dec_dec_ctl.scala 74:76] + node _T_42 = and(_T_41, _T_40) @[el2_dec_dec_ctl.scala 74:76] + node _T_43 = or(_T_35, _T_42) @[el2_dec_dec_ctl.scala 74:41] + node _T_44 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:52] + node _T_45 = eq(_T_44, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_46 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_47 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_48 = eq(_T_47, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_49 = and(_T_45, _T_46) @[el2_dec_dec_ctl.scala 75:38] + node _T_50 = and(_T_49, _T_48) @[el2_dec_dec_ctl.scala 75:38] + node _T_51 = or(_T_43, _T_50) @[el2_dec_dec_ctl.scala 74:80] + node _T_52 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_53 = eq(_T_52, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_54 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:33] + node _T_55 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_56 = eq(_T_55, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_57 = and(_T_53, _T_54) @[el2_dec_dec_ctl.scala 75:76] + node _T_58 = and(_T_57, _T_56) @[el2_dec_dec_ctl.scala 75:76] + node _T_59 = or(_T_51, _T_58) @[el2_dec_dec_ctl.scala 75:42] + node _T_60 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:33] + node _T_61 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_62 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_63 = eq(_T_62, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_64 = and(_T_60, _T_61) @[el2_dec_dec_ctl.scala 76:37] + node _T_65 = and(_T_64, _T_63) @[el2_dec_dec_ctl.scala 76:37] + node _T_66 = or(_T_59, _T_65) @[el2_dec_dec_ctl.scala 75:80] + node _T_67 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_68 = eq(_T_67, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_69 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 67:33] + node _T_70 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_71 = eq(_T_70, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_72 = and(_T_68, _T_69) @[el2_dec_dec_ctl.scala 76:75] + node _T_73 = and(_T_72, _T_71) @[el2_dec_dec_ctl.scala 76:75] + node _T_74 = or(_T_66, _T_73) @[el2_dec_dec_ctl.scala 76:41] + node _T_75 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:33] + node _T_76 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_77 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_78 = eq(_T_77, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_79 = and(_T_75, _T_76) @[el2_dec_dec_ctl.scala 77:37] + node _T_80 = and(_T_79, _T_78) @[el2_dec_dec_ctl.scala 77:37] + node _T_81 = or(_T_74, _T_80) @[el2_dec_dec_ctl.scala 76:79] + node _T_82 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_83 = eq(_T_82, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_84 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 67:33] + node _T_85 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_86 = eq(_T_85, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_87 = and(_T_83, _T_84) @[el2_dec_dec_ctl.scala 77:75] + node _T_88 = and(_T_87, _T_86) @[el2_dec_dec_ctl.scala 77:75] + node _T_89 = or(_T_81, _T_88) @[el2_dec_dec_ctl.scala 77:41] + node _T_90 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:33] + node _T_91 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_92 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_93 = eq(_T_92, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_94 = and(_T_90, _T_91) @[el2_dec_dec_ctl.scala 78:37] + node _T_95 = and(_T_94, _T_93) @[el2_dec_dec_ctl.scala 78:37] + node _T_96 = or(_T_89, _T_95) @[el2_dec_dec_ctl.scala 77:79] + node _T_97 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_98 = eq(_T_97, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_99 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] + node _T_100 = eq(_T_99, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_101 = and(_T_98, _T_100) @[el2_dec_dec_ctl.scala 78:71] + node _T_102 = or(_T_96, _T_101) @[el2_dec_dec_ctl.scala 78:41] + node _T_103 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_104 = eq(_T_103, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_105 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_106 = eq(_T_105, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_107 = and(_T_104, _T_106) @[el2_dec_dec_ctl.scala 78:106] + node _T_108 = or(_T_102, _T_107) @[el2_dec_dec_ctl.scala 78:75] + io.out.rs1 <= _T_108 @[el2_dec_dec_ctl.scala 73:14] + node _T_109 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_110 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_111 = eq(_T_110, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_112 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_113 = eq(_T_112, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_114 = and(_T_109, _T_111) @[el2_dec_dec_ctl.scala 79:48] + node _T_115 = and(_T_114, _T_113) @[el2_dec_dec_ctl.scala 79:48] + node _T_116 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_117 = eq(_T_116, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_118 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_119 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_120 = eq(_T_119, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_121 = and(_T_117, _T_118) @[el2_dec_dec_ctl.scala 79:85] + node _T_122 = and(_T_121, _T_120) @[el2_dec_dec_ctl.scala 79:85] + node _T_123 = or(_T_115, _T_122) @[el2_dec_dec_ctl.scala 79:52] + io.out.rs2 <= _T_123 @[el2_dec_dec_ctl.scala 79:14] + node _T_124 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_125 = eq(_T_124, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_126 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] + node _T_127 = eq(_T_126, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_128 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:33] + node _T_129 = and(_T_125, _T_127) @[el2_dec_dec_ctl.scala 80:50] + node _T_130 = and(_T_129, _T_128) @[el2_dec_dec_ctl.scala 80:50] + node _T_131 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_132 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_133 = eq(_T_132, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_134 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_135 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_136 = eq(_T_135, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_137 = and(_T_131, _T_133) @[el2_dec_dec_ctl.scala 80:90] + node _T_138 = and(_T_137, _T_134) @[el2_dec_dec_ctl.scala 80:90] + node _T_139 = and(_T_138, _T_136) @[el2_dec_dec_ctl.scala 80:90] + node _T_140 = or(_T_130, _T_139) @[el2_dec_dec_ctl.scala 80:54] + node _T_141 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_142 = eq(_T_141, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_143 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_144 = eq(_T_143, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_145 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_146 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_147 = and(_T_142, _T_144) @[el2_dec_dec_ctl.scala 81:40] + node _T_148 = and(_T_147, _T_145) @[el2_dec_dec_ctl.scala 81:40] + node _T_149 = and(_T_148, _T_146) @[el2_dec_dec_ctl.scala 81:40] + node _T_150 = or(_T_140, _T_149) @[el2_dec_dec_ctl.scala 80:94] + node _T_151 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_152 = eq(_T_151, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_153 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_154 = eq(_T_153, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_155 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_156 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_157 = eq(_T_156, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_158 = and(_T_152, _T_154) @[el2_dec_dec_ctl.scala 81:81] + node _T_159 = and(_T_158, _T_155) @[el2_dec_dec_ctl.scala 81:81] + node _T_160 = and(_T_159, _T_157) @[el2_dec_dec_ctl.scala 81:81] + node _T_161 = or(_T_150, _T_160) @[el2_dec_dec_ctl.scala 81:44] + io.out.imm12 <= _T_161 @[el2_dec_dec_ctl.scala 80:16] + node _T_162 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 82:24] + node _T_163 = eq(_T_162, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 82:17] + node _T_164 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 82:37] + node _T_165 = eq(_T_164, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 82:30] + node _T_166 = and(_T_163, _T_165) @[el2_dec_dec_ctl.scala 82:28] + node _T_167 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 82:51] + node _T_168 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 82:63] + node _T_169 = and(_T_167, _T_168) @[el2_dec_dec_ctl.scala 82:55] + node _T_170 = or(_T_166, _T_169) @[el2_dec_dec_ctl.scala 82:42] + node _T_171 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 82:76] + node _T_172 = or(_T_170, _T_171) @[el2_dec_dec_ctl.scala 82:68] + io.out.rd <= _T_172 @[el2_dec_dec_ctl.scala 82:13] + node _T_173 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_174 = eq(_T_173, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_175 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_176 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_177 = eq(_T_176, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_178 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_179 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_180 = eq(_T_179, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_181 = and(_T_174, _T_175) @[el2_dec_dec_ctl.scala 83:58] + node _T_182 = and(_T_181, _T_177) @[el2_dec_dec_ctl.scala 83:58] + node _T_183 = and(_T_182, _T_178) @[el2_dec_dec_ctl.scala 83:58] + node _T_184 = and(_T_183, _T_180) @[el2_dec_dec_ctl.scala 83:58] + io.out.shimm5 <= _T_184 @[el2_dec_dec_ctl.scala 83:17] + node _T_185 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 84:26] + node _T_186 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 84:36] + node _T_187 = and(_T_185, _T_186) @[el2_dec_dec_ctl.scala 84:29] + node _T_188 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 84:50] + node _T_189 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 84:60] + node _T_190 = and(_T_188, _T_189) @[el2_dec_dec_ctl.scala 84:53] + node _T_191 = or(_T_187, _T_190) @[el2_dec_dec_ctl.scala 84:41] + io.out.imm20 <= _T_191 @[el2_dec_dec_ctl.scala 84:16] + node _T_192 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 85:24] + node _T_193 = eq(_T_192, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 85:17] + node _T_194 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 85:37] + node _T_195 = eq(_T_194, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 85:30] + node _T_196 = and(_T_193, _T_195) @[el2_dec_dec_ctl.scala 85:28] + node _T_197 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 85:49] + node _T_198 = and(_T_196, _T_197) @[el2_dec_dec_ctl.scala 85:41] + node _T_199 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 85:63] + node _T_200 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 85:75] + node _T_201 = and(_T_199, _T_200) @[el2_dec_dec_ctl.scala 85:67] + node _T_202 = or(_T_198, _T_201) @[el2_dec_dec_ctl.scala 85:54] + io.out.pc <= _T_202 @[el2_dec_dec_ctl.scala 85:13] + node _T_203 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_204 = eq(_T_203, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_205 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_206 = eq(_T_205, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_207 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_208 = eq(_T_207, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_209 = and(_T_204, _T_206) @[el2_dec_dec_ctl.scala 86:50] + node _T_210 = and(_T_209, _T_208) @[el2_dec_dec_ctl.scala 86:50] + io.out.load <= _T_210 @[el2_dec_dec_ctl.scala 86:15] + node _T_211 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_212 = eq(_T_211, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_213 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_214 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_215 = eq(_T_214, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_216 = and(_T_212, _T_213) @[el2_dec_dec_ctl.scala 87:50] + node _T_217 = and(_T_216, _T_215) @[el2_dec_dec_ctl.scala 87:50] + io.out.store <= _T_217 @[el2_dec_dec_ctl.scala 87:16] + node _T_218 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_219 = eq(_T_218, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_220 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_221 = eq(_T_220, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_222 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_223 = eq(_T_222, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_224 = and(_T_219, _T_221) @[el2_dec_dec_ctl.scala 88:49] + node _T_225 = and(_T_224, _T_223) @[el2_dec_dec_ctl.scala 88:49] + io.out.lsu <= _T_225 @[el2_dec_dec_ctl.scala 88:14] + node _T_226 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_227 = eq(_T_226, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_228 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_229 = eq(_T_228, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_230 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_231 = eq(_T_230, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_232 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_233 = eq(_T_232, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_234 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_235 = and(_T_227, _T_229) @[el2_dec_dec_ctl.scala 89:57] + node _T_236 = and(_T_235, _T_231) @[el2_dec_dec_ctl.scala 89:57] + node _T_237 = and(_T_236, _T_233) @[el2_dec_dec_ctl.scala 89:57] + node _T_238 = and(_T_237, _T_234) @[el2_dec_dec_ctl.scala 89:57] + node _T_239 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_240 = eq(_T_239, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_241 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] + node _T_242 = eq(_T_241, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_243 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:33] + node _T_244 = and(_T_240, _T_242) @[el2_dec_dec_ctl.scala 89:94] + node _T_245 = and(_T_244, _T_243) @[el2_dec_dec_ctl.scala 89:94] + node _T_246 = or(_T_238, _T_245) @[el2_dec_dec_ctl.scala 89:61] + node _T_247 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:52] + node _T_248 = eq(_T_247, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_249 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] + node _T_250 = eq(_T_249, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_251 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_252 = eq(_T_251, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_253 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_254 = eq(_T_253, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_255 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_256 = eq(_T_255, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_257 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_258 = eq(_T_257, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_259 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_260 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_261 = eq(_T_260, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_262 = and(_T_248, _T_250) @[el2_dec_dec_ctl.scala 90:56] + node _T_263 = and(_T_262, _T_252) @[el2_dec_dec_ctl.scala 90:56] + node _T_264 = and(_T_263, _T_254) @[el2_dec_dec_ctl.scala 90:56] + node _T_265 = and(_T_264, _T_256) @[el2_dec_dec_ctl.scala 90:56] + node _T_266 = and(_T_265, _T_258) @[el2_dec_dec_ctl.scala 90:56] + node _T_267 = and(_T_266, _T_259) @[el2_dec_dec_ctl.scala 90:56] + node _T_268 = and(_T_267, _T_261) @[el2_dec_dec_ctl.scala 90:56] + node _T_269 = or(_T_246, _T_268) @[el2_dec_dec_ctl.scala 89:98] + io.out.add <= _T_269 @[el2_dec_dec_ctl.scala 89:14] + node _T_270 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:33] + node _T_271 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_272 = eq(_T_271, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_273 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_274 = eq(_T_273, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_275 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_276 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_277 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_278 = eq(_T_277, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_279 = and(_T_270, _T_272) @[el2_dec_dec_ctl.scala 91:57] + node _T_280 = and(_T_279, _T_274) @[el2_dec_dec_ctl.scala 91:57] + node _T_281 = and(_T_280, _T_275) @[el2_dec_dec_ctl.scala 91:57] + node _T_282 = and(_T_281, _T_276) @[el2_dec_dec_ctl.scala 91:57] + node _T_283 = and(_T_282, _T_278) @[el2_dec_dec_ctl.scala 91:57] + node _T_284 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] + node _T_285 = eq(_T_284, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_286 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_287 = eq(_T_286, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_288 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_289 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_290 = eq(_T_289, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_291 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_292 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_293 = eq(_T_292, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_294 = and(_T_285, _T_287) @[el2_dec_dec_ctl.scala 91:105] + node _T_295 = and(_T_294, _T_288) @[el2_dec_dec_ctl.scala 91:105] + node _T_296 = and(_T_295, _T_290) @[el2_dec_dec_ctl.scala 91:105] + node _T_297 = and(_T_296, _T_291) @[el2_dec_dec_ctl.scala 91:105] + node _T_298 = and(_T_297, _T_293) @[el2_dec_dec_ctl.scala 91:105] + node _T_299 = or(_T_283, _T_298) @[el2_dec_dec_ctl.scala 91:61] + node _T_300 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_301 = eq(_T_300, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_302 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_303 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_304 = eq(_T_303, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_305 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_306 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_307 = eq(_T_306, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_308 = and(_T_301, _T_302) @[el2_dec_dec_ctl.scala 92:43] + node _T_309 = and(_T_308, _T_304) @[el2_dec_dec_ctl.scala 92:43] + node _T_310 = and(_T_309, _T_305) @[el2_dec_dec_ctl.scala 92:43] + node _T_311 = and(_T_310, _T_307) @[el2_dec_dec_ctl.scala 92:43] + node _T_312 = or(_T_299, _T_311) @[el2_dec_dec_ctl.scala 91:109] + node _T_313 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_314 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_315 = eq(_T_314, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_316 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_317 = eq(_T_316, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_318 = and(_T_313, _T_315) @[el2_dec_dec_ctl.scala 92:80] + node _T_319 = and(_T_318, _T_317) @[el2_dec_dec_ctl.scala 92:80] + node _T_320 = or(_T_312, _T_319) @[el2_dec_dec_ctl.scala 92:47] + io.out.sub <= _T_320 @[el2_dec_dec_ctl.scala 91:14] + node _T_321 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_322 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_323 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_324 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_325 = eq(_T_324, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_326 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_327 = eq(_T_326, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_328 = and(_T_321, _T_322) @[el2_dec_dec_ctl.scala 93:56] + node _T_329 = and(_T_328, _T_323) @[el2_dec_dec_ctl.scala 93:56] + node _T_330 = and(_T_329, _T_325) @[el2_dec_dec_ctl.scala 93:56] + node _T_331 = and(_T_330, _T_327) @[el2_dec_dec_ctl.scala 93:56] + node _T_332 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] + node _T_333 = eq(_T_332, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_334 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_335 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_336 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_337 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_338 = eq(_T_337, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_339 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_340 = eq(_T_339, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_341 = and(_T_333, _T_334) @[el2_dec_dec_ctl.scala 93:104] + node _T_342 = and(_T_341, _T_335) @[el2_dec_dec_ctl.scala 93:104] + node _T_343 = and(_T_342, _T_336) @[el2_dec_dec_ctl.scala 93:104] + node _T_344 = and(_T_343, _T_338) @[el2_dec_dec_ctl.scala 93:104] + node _T_345 = and(_T_344, _T_340) @[el2_dec_dec_ctl.scala 93:104] + node _T_346 = or(_T_331, _T_345) @[el2_dec_dec_ctl.scala 93:60] + io.out.land <= _T_346 @[el2_dec_dec_ctl.scala 93:15] + node _T_347 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_348 = eq(_T_347, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_349 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:33] + node _T_350 = and(_T_348, _T_349) @[el2_dec_dec_ctl.scala 94:45] + node _T_351 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] + node _T_352 = eq(_T_351, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_353 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_354 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_355 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_356 = eq(_T_355, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_357 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_358 = eq(_T_357, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_359 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_360 = eq(_T_359, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_361 = and(_T_352, _T_353) @[el2_dec_dec_ctl.scala 94:94] + node _T_362 = and(_T_361, _T_354) @[el2_dec_dec_ctl.scala 94:94] + node _T_363 = and(_T_362, _T_356) @[el2_dec_dec_ctl.scala 94:94] + node _T_364 = and(_T_363, _T_358) @[el2_dec_dec_ctl.scala 94:94] + node _T_365 = and(_T_364, _T_360) @[el2_dec_dec_ctl.scala 94:94] + node _T_366 = or(_T_350, _T_365) @[el2_dec_dec_ctl.scala 94:49] + node _T_367 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_368 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_369 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:33] + node _T_370 = and(_T_367, _T_368) @[el2_dec_dec_ctl.scala 95:34] + node _T_371 = and(_T_370, _T_369) @[el2_dec_dec_ctl.scala 95:34] + node _T_372 = or(_T_366, _T_371) @[el2_dec_dec_ctl.scala 94:98] + node _T_373 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_374 = eq(_T_373, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_375 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_376 = eq(_T_375, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_377 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_378 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_379 = and(_T_374, _T_376) @[el2_dec_dec_ctl.scala 95:75] + node _T_380 = and(_T_379, _T_377) @[el2_dec_dec_ctl.scala 95:75] + node _T_381 = and(_T_380, _T_378) @[el2_dec_dec_ctl.scala 95:75] + node _T_382 = or(_T_372, _T_381) @[el2_dec_dec_ctl.scala 95:38] + node _T_383 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_384 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_385 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_386 = eq(_T_385, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_387 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_388 = eq(_T_387, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_389 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_390 = eq(_T_389, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_391 = and(_T_383, _T_384) @[el2_dec_dec_ctl.scala 96:44] + node _T_392 = and(_T_391, _T_386) @[el2_dec_dec_ctl.scala 96:44] + node _T_393 = and(_T_392, _T_388) @[el2_dec_dec_ctl.scala 96:44] + node _T_394 = and(_T_393, _T_390) @[el2_dec_dec_ctl.scala 96:44] + node _T_395 = or(_T_382, _T_394) @[el2_dec_dec_ctl.scala 95:79] + io.out.lor <= _T_395 @[el2_dec_dec_ctl.scala 94:14] + node _T_396 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] + node _T_397 = eq(_T_396, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_398 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_399 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_400 = eq(_T_399, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_401 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_402 = eq(_T_401, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_403 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_404 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_405 = eq(_T_404, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_406 = and(_T_397, _T_398) @[el2_dec_dec_ctl.scala 97:61] + node _T_407 = and(_T_406, _T_400) @[el2_dec_dec_ctl.scala 97:61] + node _T_408 = and(_T_407, _T_402) @[el2_dec_dec_ctl.scala 97:61] + node _T_409 = and(_T_408, _T_403) @[el2_dec_dec_ctl.scala 97:61] + node _T_410 = and(_T_409, _T_405) @[el2_dec_dec_ctl.scala 97:61] + node _T_411 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_412 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_413 = eq(_T_412, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_414 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_415 = eq(_T_414, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_416 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_417 = eq(_T_416, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_418 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_419 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_420 = eq(_T_419, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_421 = and(_T_411, _T_413) @[el2_dec_dec_ctl.scala 97:109] + node _T_422 = and(_T_421, _T_415) @[el2_dec_dec_ctl.scala 97:109] + node _T_423 = and(_T_422, _T_417) @[el2_dec_dec_ctl.scala 97:109] + node _T_424 = and(_T_423, _T_418) @[el2_dec_dec_ctl.scala 97:109] + node _T_425 = and(_T_424, _T_420) @[el2_dec_dec_ctl.scala 97:109] + node _T_426 = or(_T_410, _T_425) @[el2_dec_dec_ctl.scala 97:65] + io.out.lxor <= _T_426 @[el2_dec_dec_ctl.scala 97:15] + node _T_427 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] + node _T_428 = eq(_T_427, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_429 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_430 = eq(_T_429, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_431 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_432 = eq(_T_431, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_433 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_434 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_435 = eq(_T_434, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_436 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_437 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_438 = eq(_T_437, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_439 = and(_T_428, _T_430) @[el2_dec_dec_ctl.scala 98:63] + node _T_440 = and(_T_439, _T_432) @[el2_dec_dec_ctl.scala 98:63] + node _T_441 = and(_T_440, _T_433) @[el2_dec_dec_ctl.scala 98:63] + node _T_442 = and(_T_441, _T_435) @[el2_dec_dec_ctl.scala 98:63] + node _T_443 = and(_T_442, _T_436) @[el2_dec_dec_ctl.scala 98:63] + node _T_444 = and(_T_443, _T_438) @[el2_dec_dec_ctl.scala 98:63] + io.out.sll <= _T_444 @[el2_dec_dec_ctl.scala 98:14] + node _T_445 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:33] + node _T_446 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_447 = eq(_T_446, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_448 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_449 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_450 = eq(_T_449, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_451 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_452 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_453 = eq(_T_452, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_454 = and(_T_445, _T_447) @[el2_dec_dec_ctl.scala 99:58] + node _T_455 = and(_T_454, _T_448) @[el2_dec_dec_ctl.scala 99:58] + node _T_456 = and(_T_455, _T_450) @[el2_dec_dec_ctl.scala 99:58] + node _T_457 = and(_T_456, _T_451) @[el2_dec_dec_ctl.scala 99:58] + node _T_458 = and(_T_457, _T_453) @[el2_dec_dec_ctl.scala 99:58] + io.out.sra <= _T_458 @[el2_dec_dec_ctl.scala 99:14] + node _T_459 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:52] + node _T_460 = eq(_T_459, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_461 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] + node _T_462 = eq(_T_461, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_463 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_464 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_465 = eq(_T_464, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_466 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_467 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_468 = eq(_T_467, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_469 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_470 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_471 = eq(_T_470, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_472 = and(_T_460, _T_462) @[el2_dec_dec_ctl.scala 100:66] + node _T_473 = and(_T_472, _T_463) @[el2_dec_dec_ctl.scala 100:66] + node _T_474 = and(_T_473, _T_465) @[el2_dec_dec_ctl.scala 100:66] + node _T_475 = and(_T_474, _T_466) @[el2_dec_dec_ctl.scala 100:66] + node _T_476 = and(_T_475, _T_468) @[el2_dec_dec_ctl.scala 100:66] + node _T_477 = and(_T_476, _T_469) @[el2_dec_dec_ctl.scala 100:66] + node _T_478 = and(_T_477, _T_471) @[el2_dec_dec_ctl.scala 100:66] + io.out.srl <= _T_478 @[el2_dec_dec_ctl.scala 100:14] + node _T_479 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] + node _T_480 = eq(_T_479, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_481 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_482 = eq(_T_481, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_483 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_484 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_485 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_486 = eq(_T_485, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_487 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_488 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_489 = eq(_T_488, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_490 = and(_T_480, _T_482) @[el2_dec_dec_ctl.scala 101:62] + node _T_491 = and(_T_490, _T_483) @[el2_dec_dec_ctl.scala 101:62] + node _T_492 = and(_T_491, _T_484) @[el2_dec_dec_ctl.scala 101:62] + node _T_493 = and(_T_492, _T_486) @[el2_dec_dec_ctl.scala 101:62] + node _T_494 = and(_T_493, _T_487) @[el2_dec_dec_ctl.scala 101:62] + node _T_495 = and(_T_494, _T_489) @[el2_dec_dec_ctl.scala 101:62] + node _T_496 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_497 = eq(_T_496, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_498 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_499 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_500 = eq(_T_499, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_501 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_502 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_503 = eq(_T_502, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_504 = and(_T_497, _T_498) @[el2_dec_dec_ctl.scala 101:106] + node _T_505 = and(_T_504, _T_500) @[el2_dec_dec_ctl.scala 101:106] + node _T_506 = and(_T_505, _T_501) @[el2_dec_dec_ctl.scala 101:106] + node _T_507 = and(_T_506, _T_503) @[el2_dec_dec_ctl.scala 101:106] + node _T_508 = or(_T_495, _T_507) @[el2_dec_dec_ctl.scala 101:66] + io.out.slt <= _T_508 @[el2_dec_dec_ctl.scala 101:14] + node _T_509 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_510 = eq(_T_509, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_511 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_512 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_513 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_514 = eq(_T_513, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_515 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_516 = eq(_T_515, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_517 = and(_T_510, _T_511) @[el2_dec_dec_ctl.scala 102:59] + node _T_518 = and(_T_517, _T_512) @[el2_dec_dec_ctl.scala 102:59] + node _T_519 = and(_T_518, _T_514) @[el2_dec_dec_ctl.scala 102:59] + node _T_520 = and(_T_519, _T_516) @[el2_dec_dec_ctl.scala 102:59] + node _T_521 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_522 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_523 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_524 = eq(_T_523, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_525 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_526 = eq(_T_525, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_527 = and(_T_521, _T_522) @[el2_dec_dec_ctl.scala 102:99] + node _T_528 = and(_T_527, _T_524) @[el2_dec_dec_ctl.scala 102:99] + node _T_529 = and(_T_528, _T_526) @[el2_dec_dec_ctl.scala 102:99] + node _T_530 = or(_T_520, _T_529) @[el2_dec_dec_ctl.scala 102:63] + node _T_531 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_532 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_533 = eq(_T_532, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_534 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_535 = eq(_T_534, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_536 = and(_T_531, _T_533) @[el2_dec_dec_ctl.scala 103:37] + node _T_537 = and(_T_536, _T_535) @[el2_dec_dec_ctl.scala 103:37] + node _T_538 = or(_T_530, _T_537) @[el2_dec_dec_ctl.scala 102:103] + node _T_539 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] + node _T_540 = eq(_T_539, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_541 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_542 = eq(_T_541, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_543 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_544 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_545 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_546 = eq(_T_545, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_547 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_548 = eq(_T_547, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_549 = and(_T_540, _T_542) @[el2_dec_dec_ctl.scala 103:86] + node _T_550 = and(_T_549, _T_543) @[el2_dec_dec_ctl.scala 103:86] + node _T_551 = and(_T_550, _T_544) @[el2_dec_dec_ctl.scala 103:86] + node _T_552 = and(_T_551, _T_546) @[el2_dec_dec_ctl.scala 103:86] + node _T_553 = and(_T_552, _T_548) @[el2_dec_dec_ctl.scala 103:86] + node _T_554 = or(_T_538, _T_553) @[el2_dec_dec_ctl.scala 103:41] + node _T_555 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:33] + node _T_556 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_557 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_558 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_559 = eq(_T_558, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_560 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_561 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_562 = eq(_T_561, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_563 = and(_T_555, _T_556) @[el2_dec_dec_ctl.scala 104:45] + node _T_564 = and(_T_563, _T_557) @[el2_dec_dec_ctl.scala 104:45] + node _T_565 = and(_T_564, _T_559) @[el2_dec_dec_ctl.scala 104:45] + node _T_566 = and(_T_565, _T_560) @[el2_dec_dec_ctl.scala 104:45] + node _T_567 = and(_T_566, _T_562) @[el2_dec_dec_ctl.scala 104:45] + node _T_568 = or(_T_554, _T_567) @[el2_dec_dec_ctl.scala 103:90] + io.out.unsign <= _T_568 @[el2_dec_dec_ctl.scala 102:17] + node _T_569 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_570 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_571 = eq(_T_570, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_572 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_573 = eq(_T_572, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_574 = and(_T_569, _T_571) @[el2_dec_dec_ctl.scala 105:51] + node _T_575 = and(_T_574, _T_573) @[el2_dec_dec_ctl.scala 105:51] + io.out.condbr <= _T_575 @[el2_dec_dec_ctl.scala 105:17] + node _T_576 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_577 = eq(_T_576, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_578 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_579 = eq(_T_578, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_580 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_581 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_582 = eq(_T_581, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_583 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_584 = eq(_T_583, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_585 = and(_T_577, _T_579) @[el2_dec_dec_ctl.scala 106:56] + node _T_586 = and(_T_585, _T_580) @[el2_dec_dec_ctl.scala 106:56] + node _T_587 = and(_T_586, _T_582) @[el2_dec_dec_ctl.scala 106:56] + node _T_588 = and(_T_587, _T_584) @[el2_dec_dec_ctl.scala 106:56] + io.out.beq <= _T_588 @[el2_dec_dec_ctl.scala 106:14] + node _T_589 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_590 = eq(_T_589, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_591 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_592 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_593 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_594 = eq(_T_593, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_595 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_596 = eq(_T_595, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_597 = and(_T_590, _T_591) @[el2_dec_dec_ctl.scala 107:55] + node _T_598 = and(_T_597, _T_592) @[el2_dec_dec_ctl.scala 107:55] + node _T_599 = and(_T_598, _T_594) @[el2_dec_dec_ctl.scala 107:55] + node _T_600 = and(_T_599, _T_596) @[el2_dec_dec_ctl.scala 107:55] + io.out.bne <= _T_600 @[el2_dec_dec_ctl.scala 107:14] + node _T_601 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_602 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_603 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_604 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_605 = eq(_T_604, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_606 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_607 = eq(_T_606, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_608 = and(_T_601, _T_602) @[el2_dec_dec_ctl.scala 108:54] + node _T_609 = and(_T_608, _T_603) @[el2_dec_dec_ctl.scala 108:54] + node _T_610 = and(_T_609, _T_605) @[el2_dec_dec_ctl.scala 108:54] + node _T_611 = and(_T_610, _T_607) @[el2_dec_dec_ctl.scala 108:54] + io.out.bge <= _T_611 @[el2_dec_dec_ctl.scala 108:14] + node _T_612 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_613 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_614 = eq(_T_613, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_615 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_616 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_617 = eq(_T_616, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_618 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_619 = eq(_T_618, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_620 = and(_T_612, _T_614) @[el2_dec_dec_ctl.scala 109:55] + node _T_621 = and(_T_620, _T_615) @[el2_dec_dec_ctl.scala 109:55] + node _T_622 = and(_T_621, _T_617) @[el2_dec_dec_ctl.scala 109:55] + node _T_623 = and(_T_622, _T_619) @[el2_dec_dec_ctl.scala 109:55] + io.out.blt <= _T_623 @[el2_dec_dec_ctl.scala 109:14] + node _T_624 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_625 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:33] + node _T_626 = and(_T_624, _T_625) @[el2_dec_dec_ctl.scala 110:44] + io.out.jal <= _T_626 @[el2_dec_dec_ctl.scala 110:14] + node _T_627 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_628 = eq(_T_627, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_629 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_630 = eq(_T_629, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_631 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_632 = eq(_T_631, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_633 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_634 = eq(_T_633, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_635 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_636 = eq(_T_635, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_637 = and(_T_628, _T_630) @[el2_dec_dec_ctl.scala 111:56] + node _T_638 = and(_T_637, _T_632) @[el2_dec_dec_ctl.scala 111:56] + node _T_639 = and(_T_638, _T_634) @[el2_dec_dec_ctl.scala 111:56] + node _T_640 = and(_T_639, _T_636) @[el2_dec_dec_ctl.scala 111:56] + io.out.by <= _T_640 @[el2_dec_dec_ctl.scala 111:13] + node _T_641 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_642 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_643 = eq(_T_642, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_644 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_645 = eq(_T_644, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_646 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_647 = eq(_T_646, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_648 = and(_T_641, _T_643) @[el2_dec_dec_ctl.scala 112:53] + node _T_649 = and(_T_648, _T_645) @[el2_dec_dec_ctl.scala 112:53] + node _T_650 = and(_T_649, _T_647) @[el2_dec_dec_ctl.scala 112:53] + io.out.half <= _T_650 @[el2_dec_dec_ctl.scala 112:15] + node _T_651 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_652 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_653 = eq(_T_652, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_654 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_655 = eq(_T_654, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_656 = and(_T_651, _T_653) @[el2_dec_dec_ctl.scala 113:50] + node _T_657 = and(_T_656, _T_655) @[el2_dec_dec_ctl.scala 113:50] + io.out.word <= _T_657 @[el2_dec_dec_ctl.scala 113:15] + node _T_658 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_659 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_660 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_661 = and(_T_658, _T_659) @[el2_dec_dec_ctl.scala 114:52] + node _T_662 = and(_T_661, _T_660) @[el2_dec_dec_ctl.scala 114:52] + node _T_663 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 67:33] + node _T_664 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_665 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_666 = and(_T_663, _T_664) @[el2_dec_dec_ctl.scala 114:87] + node _T_667 = and(_T_666, _T_665) @[el2_dec_dec_ctl.scala 114:87] + node _T_668 = or(_T_662, _T_667) @[el2_dec_dec_ctl.scala 114:56] + node _T_669 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 67:33] + node _T_670 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_671 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_672 = and(_T_669, _T_670) @[el2_dec_dec_ctl.scala 115:34] + node _T_673 = and(_T_672, _T_671) @[el2_dec_dec_ctl.scala 115:34] + node _T_674 = or(_T_668, _T_673) @[el2_dec_dec_ctl.scala 114:91] + node _T_675 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:33] + node _T_676 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_677 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_678 = and(_T_675, _T_676) @[el2_dec_dec_ctl.scala 115:69] + node _T_679 = and(_T_678, _T_677) @[el2_dec_dec_ctl.scala 115:69] + node _T_680 = or(_T_674, _T_679) @[el2_dec_dec_ctl.scala 115:38] + node _T_681 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 67:33] + node _T_682 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_683 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_684 = and(_T_681, _T_682) @[el2_dec_dec_ctl.scala 115:105] + node _T_685 = and(_T_684, _T_683) @[el2_dec_dec_ctl.scala 115:105] + node _T_686 = or(_T_680, _T_685) @[el2_dec_dec_ctl.scala 115:73] + node _T_687 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 67:33] + node _T_688 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_689 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_690 = and(_T_687, _T_688) @[el2_dec_dec_ctl.scala 116:35] + node _T_691 = and(_T_690, _T_689) @[el2_dec_dec_ctl.scala 116:35] + node _T_692 = or(_T_686, _T_691) @[el2_dec_dec_ctl.scala 115:109] + io.out.csr_read <= _T_692 @[el2_dec_dec_ctl.scala 114:19] + node _T_693 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:33] + node _T_694 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_695 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_696 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_697 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_698 = and(_T_693, _T_694) @[el2_dec_dec_ctl.scala 117:57] + node _T_699 = and(_T_698, _T_695) @[el2_dec_dec_ctl.scala 117:57] + node _T_700 = and(_T_699, _T_696) @[el2_dec_dec_ctl.scala 117:57] + node _T_701 = and(_T_700, _T_697) @[el2_dec_dec_ctl.scala 117:57] + node _T_702 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:33] + node _T_703 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_704 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_705 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_706 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_707 = and(_T_702, _T_703) @[el2_dec_dec_ctl.scala 117:99] + node _T_708 = and(_T_707, _T_704) @[el2_dec_dec_ctl.scala 117:99] + node _T_709 = and(_T_708, _T_705) @[el2_dec_dec_ctl.scala 117:99] + node _T_710 = and(_T_709, _T_706) @[el2_dec_dec_ctl.scala 117:99] + node _T_711 = or(_T_701, _T_710) @[el2_dec_dec_ctl.scala 117:61] + node _T_712 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:33] + node _T_713 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_714 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_715 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_716 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_717 = and(_T_712, _T_713) @[el2_dec_dec_ctl.scala 118:41] + node _T_718 = and(_T_717, _T_714) @[el2_dec_dec_ctl.scala 118:41] + node _T_719 = and(_T_718, _T_715) @[el2_dec_dec_ctl.scala 118:41] + node _T_720 = and(_T_719, _T_716) @[el2_dec_dec_ctl.scala 118:41] + node _T_721 = or(_T_711, _T_720) @[el2_dec_dec_ctl.scala 117:103] + node _T_722 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:33] + node _T_723 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_724 = eq(_T_723, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_725 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_726 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_727 = and(_T_722, _T_724) @[el2_dec_dec_ctl.scala 118:81] + node _T_728 = and(_T_727, _T_725) @[el2_dec_dec_ctl.scala 118:81] + node _T_729 = and(_T_728, _T_726) @[el2_dec_dec_ctl.scala 118:81] + node _T_730 = or(_T_721, _T_729) @[el2_dec_dec_ctl.scala 118:45] + node _T_731 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:33] + node _T_732 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_733 = eq(_T_732, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_734 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_735 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_736 = and(_T_731, _T_733) @[el2_dec_dec_ctl.scala 119:39] + node _T_737 = and(_T_736, _T_734) @[el2_dec_dec_ctl.scala 119:39] + node _T_738 = and(_T_737, _T_735) @[el2_dec_dec_ctl.scala 119:39] + node _T_739 = or(_T_730, _T_738) @[el2_dec_dec_ctl.scala 118:85] + io.out.csr_clr <= _T_739 @[el2_dec_dec_ctl.scala 117:18] + node _T_740 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_741 = eq(_T_740, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_742 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_743 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_744 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_745 = and(_T_741, _T_742) @[el2_dec_dec_ctl.scala 120:57] + node _T_746 = and(_T_745, _T_743) @[el2_dec_dec_ctl.scala 120:57] + node _T_747 = and(_T_746, _T_744) @[el2_dec_dec_ctl.scala 120:57] + io.out.csr_write <= _T_747 @[el2_dec_dec_ctl.scala 120:20] + node _T_748 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_749 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_750 = eq(_T_749, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_751 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_752 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_753 = and(_T_748, _T_750) @[el2_dec_dec_ctl.scala 121:55] + node _T_754 = and(_T_753, _T_751) @[el2_dec_dec_ctl.scala 121:55] + node _T_755 = and(_T_754, _T_752) @[el2_dec_dec_ctl.scala 121:55] + node _T_756 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:33] + node _T_757 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_758 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_759 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_760 = and(_T_756, _T_757) @[el2_dec_dec_ctl.scala 121:94] + node _T_761 = and(_T_760, _T_758) @[el2_dec_dec_ctl.scala 121:94] + node _T_762 = and(_T_761, _T_759) @[el2_dec_dec_ctl.scala 121:94] + node _T_763 = or(_T_755, _T_762) @[el2_dec_dec_ctl.scala 121:59] + node _T_764 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:33] + node _T_765 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_766 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_767 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_768 = and(_T_764, _T_765) @[el2_dec_dec_ctl.scala 122:38] + node _T_769 = and(_T_768, _T_766) @[el2_dec_dec_ctl.scala 122:38] + node _T_770 = and(_T_769, _T_767) @[el2_dec_dec_ctl.scala 122:38] + node _T_771 = or(_T_763, _T_770) @[el2_dec_dec_ctl.scala 121:98] + node _T_772 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:33] + node _T_773 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_774 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_775 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_776 = and(_T_772, _T_773) @[el2_dec_dec_ctl.scala 122:77] + node _T_777 = and(_T_776, _T_774) @[el2_dec_dec_ctl.scala 122:77] + node _T_778 = and(_T_777, _T_775) @[el2_dec_dec_ctl.scala 122:77] + node _T_779 = or(_T_771, _T_778) @[el2_dec_dec_ctl.scala 122:42] + node _T_780 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:33] + node _T_781 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_782 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_783 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_784 = and(_T_780, _T_781) @[el2_dec_dec_ctl.scala 123:38] + node _T_785 = and(_T_784, _T_782) @[el2_dec_dec_ctl.scala 123:38] + node _T_786 = and(_T_785, _T_783) @[el2_dec_dec_ctl.scala 123:38] + node _T_787 = or(_T_779, _T_786) @[el2_dec_dec_ctl.scala 122:81] + node _T_788 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:33] + node _T_789 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_790 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_791 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_792 = and(_T_788, _T_789) @[el2_dec_dec_ctl.scala 123:77] + node _T_793 = and(_T_792, _T_790) @[el2_dec_dec_ctl.scala 123:77] + node _T_794 = and(_T_793, _T_791) @[el2_dec_dec_ctl.scala 123:77] + node _T_795 = or(_T_787, _T_794) @[el2_dec_dec_ctl.scala 123:42] + io.out.csr_imm <= _T_795 @[el2_dec_dec_ctl.scala 121:18] + node _T_796 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:33] + node _T_797 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_798 = eq(_T_797, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_799 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_800 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_801 = and(_T_796, _T_798) @[el2_dec_dec_ctl.scala 124:55] + node _T_802 = and(_T_801, _T_799) @[el2_dec_dec_ctl.scala 124:55] + node _T_803 = and(_T_802, _T_800) @[el2_dec_dec_ctl.scala 124:55] + node _T_804 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:33] + node _T_805 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_806 = eq(_T_805, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_807 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_808 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_809 = and(_T_804, _T_806) @[el2_dec_dec_ctl.scala 124:95] + node _T_810 = and(_T_809, _T_807) @[el2_dec_dec_ctl.scala 124:95] + node _T_811 = and(_T_810, _T_808) @[el2_dec_dec_ctl.scala 124:95] + node _T_812 = or(_T_803, _T_811) @[el2_dec_dec_ctl.scala 124:59] + node _T_813 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:33] + node _T_814 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_815 = eq(_T_814, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_816 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_817 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_818 = and(_T_813, _T_815) @[el2_dec_dec_ctl.scala 125:39] + node _T_819 = and(_T_818, _T_816) @[el2_dec_dec_ctl.scala 125:39] + node _T_820 = and(_T_819, _T_817) @[el2_dec_dec_ctl.scala 125:39] + node _T_821 = or(_T_812, _T_820) @[el2_dec_dec_ctl.scala 124:99] + node _T_822 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:33] + node _T_823 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_824 = eq(_T_823, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_825 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_826 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_827 = and(_T_822, _T_824) @[el2_dec_dec_ctl.scala 125:79] + node _T_828 = and(_T_827, _T_825) @[el2_dec_dec_ctl.scala 125:79] + node _T_829 = and(_T_828, _T_826) @[el2_dec_dec_ctl.scala 125:79] + node _T_830 = or(_T_821, _T_829) @[el2_dec_dec_ctl.scala 125:43] + node _T_831 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:33] + node _T_832 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_833 = eq(_T_832, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_834 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_835 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_836 = and(_T_831, _T_833) @[el2_dec_dec_ctl.scala 126:39] + node _T_837 = and(_T_836, _T_834) @[el2_dec_dec_ctl.scala 126:39] + node _T_838 = and(_T_837, _T_835) @[el2_dec_dec_ctl.scala 126:39] + node _T_839 = or(_T_830, _T_838) @[el2_dec_dec_ctl.scala 125:83] + io.out.csr_set <= _T_839 @[el2_dec_dec_ctl.scala 124:18] + node _T_840 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 67:52] + node _T_841 = eq(_T_840, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_842 = bits(io.ins, 20, 20) @[el2_dec_dec_ctl.scala 67:33] + node _T_843 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_844 = eq(_T_843, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_845 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_846 = eq(_T_845, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_847 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_848 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_849 = and(_T_841, _T_842) @[el2_dec_dec_ctl.scala 127:62] + node _T_850 = and(_T_849, _T_844) @[el2_dec_dec_ctl.scala 127:62] + node _T_851 = and(_T_850, _T_846) @[el2_dec_dec_ctl.scala 127:62] + node _T_852 = and(_T_851, _T_847) @[el2_dec_dec_ctl.scala 127:62] + node _T_853 = and(_T_852, _T_848) @[el2_dec_dec_ctl.scala 127:62] + io.out.ebreak <= _T_853 @[el2_dec_dec_ctl.scala 127:17] + node _T_854 = bits(io.ins, 21, 21) @[el2_dec_dec_ctl.scala 67:52] + node _T_855 = eq(_T_854, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_856 = bits(io.ins, 20, 20) @[el2_dec_dec_ctl.scala 67:52] + node _T_857 = eq(_T_856, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_858 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_859 = eq(_T_858, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_860 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_861 = eq(_T_860, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_862 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_863 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_864 = and(_T_855, _T_857) @[el2_dec_dec_ctl.scala 128:62] + node _T_865 = and(_T_864, _T_859) @[el2_dec_dec_ctl.scala 128:62] + node _T_866 = and(_T_865, _T_861) @[el2_dec_dec_ctl.scala 128:62] + node _T_867 = and(_T_866, _T_862) @[el2_dec_dec_ctl.scala 128:62] + node _T_868 = and(_T_867, _T_863) @[el2_dec_dec_ctl.scala 128:62] + io.out.ecall <= _T_868 @[el2_dec_dec_ctl.scala 128:16] + node _T_869 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:33] + node _T_870 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_871 = eq(_T_870, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_872 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_873 = eq(_T_872, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_874 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_875 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_876 = and(_T_869, _T_871) @[el2_dec_dec_ctl.scala 129:56] + node _T_877 = and(_T_876, _T_873) @[el2_dec_dec_ctl.scala 129:56] + node _T_878 = and(_T_877, _T_874) @[el2_dec_dec_ctl.scala 129:56] + node _T_879 = and(_T_878, _T_875) @[el2_dec_dec_ctl.scala 129:56] + io.out.mret <= _T_879 @[el2_dec_dec_ctl.scala 129:15] + node _T_880 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:33] + node _T_881 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_882 = eq(_T_881, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_883 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_884 = eq(_T_883, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_885 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_886 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_887 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_888 = eq(_T_887, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_889 = and(_T_880, _T_882) @[el2_dec_dec_ctl.scala 130:57] + node _T_890 = and(_T_889, _T_884) @[el2_dec_dec_ctl.scala 130:57] + node _T_891 = and(_T_890, _T_885) @[el2_dec_dec_ctl.scala 130:57] + node _T_892 = and(_T_891, _T_886) @[el2_dec_dec_ctl.scala 130:57] + node _T_893 = and(_T_892, _T_888) @[el2_dec_dec_ctl.scala 130:57] + io.out.mul <= _T_893 @[el2_dec_dec_ctl.scala 130:14] + node _T_894 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:33] + node _T_895 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_896 = eq(_T_895, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_897 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_898 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_899 = eq(_T_898, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_900 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_901 = eq(_T_900, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_902 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_903 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_904 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_905 = eq(_T_904, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_906 = and(_T_894, _T_896) @[el2_dec_dec_ctl.scala 131:69] + node _T_907 = and(_T_906, _T_897) @[el2_dec_dec_ctl.scala 131:69] + node _T_908 = and(_T_907, _T_899) @[el2_dec_dec_ctl.scala 131:69] + node _T_909 = and(_T_908, _T_901) @[el2_dec_dec_ctl.scala 131:69] + node _T_910 = and(_T_909, _T_902) @[el2_dec_dec_ctl.scala 131:69] + node _T_911 = and(_T_910, _T_903) @[el2_dec_dec_ctl.scala 131:69] + node _T_912 = and(_T_911, _T_905) @[el2_dec_dec_ctl.scala 131:69] + node _T_913 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:33] + node _T_914 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_915 = eq(_T_914, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_916 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_917 = eq(_T_916, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_918 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_919 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_920 = eq(_T_919, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_921 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_922 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_923 = eq(_T_922, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_924 = and(_T_913, _T_915) @[el2_dec_dec_ctl.scala 132:50] + node _T_925 = and(_T_924, _T_917) @[el2_dec_dec_ctl.scala 132:50] + node _T_926 = and(_T_925, _T_918) @[el2_dec_dec_ctl.scala 132:50] + node _T_927 = and(_T_926, _T_920) @[el2_dec_dec_ctl.scala 132:50] + node _T_928 = and(_T_927, _T_921) @[el2_dec_dec_ctl.scala 132:50] + node _T_929 = and(_T_928, _T_923) @[el2_dec_dec_ctl.scala 132:50] + node _T_930 = or(_T_912, _T_929) @[el2_dec_dec_ctl.scala 131:73] + io.out.rs1_sign <= _T_930 @[el2_dec_dec_ctl.scala 131:19] + node _T_931 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:33] + node _T_932 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_933 = eq(_T_932, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_934 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_935 = eq(_T_934, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_936 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_937 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_938 = eq(_T_937, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_939 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_940 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_941 = eq(_T_940, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_942 = and(_T_931, _T_933) @[el2_dec_dec_ctl.scala 133:67] + node _T_943 = and(_T_942, _T_935) @[el2_dec_dec_ctl.scala 133:67] + node _T_944 = and(_T_943, _T_936) @[el2_dec_dec_ctl.scala 133:67] + node _T_945 = and(_T_944, _T_938) @[el2_dec_dec_ctl.scala 133:67] + node _T_946 = and(_T_945, _T_939) @[el2_dec_dec_ctl.scala 133:67] + node _T_947 = and(_T_946, _T_941) @[el2_dec_dec_ctl.scala 133:67] + io.out.rs2_sign <= _T_947 @[el2_dec_dec_ctl.scala 133:19] + node _T_948 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:33] + node _T_949 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_950 = eq(_T_949, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_951 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_952 = eq(_T_951, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_953 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_954 = eq(_T_953, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_955 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_956 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_957 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_958 = eq(_T_957, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_959 = and(_T_948, _T_950) @[el2_dec_dec_ctl.scala 134:62] + node _T_960 = and(_T_959, _T_952) @[el2_dec_dec_ctl.scala 134:62] + node _T_961 = and(_T_960, _T_954) @[el2_dec_dec_ctl.scala 134:62] + node _T_962 = and(_T_961, _T_955) @[el2_dec_dec_ctl.scala 134:62] + node _T_963 = and(_T_962, _T_956) @[el2_dec_dec_ctl.scala 134:62] + node _T_964 = and(_T_963, _T_958) @[el2_dec_dec_ctl.scala 134:62] + io.out.low <= _T_964 @[el2_dec_dec_ctl.scala 134:14] + node _T_965 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:33] + node _T_966 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_967 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_968 = eq(_T_967, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_969 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_970 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_971 = eq(_T_970, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_972 = and(_T_965, _T_966) @[el2_dec_dec_ctl.scala 135:54] + node _T_973 = and(_T_972, _T_968) @[el2_dec_dec_ctl.scala 135:54] + node _T_974 = and(_T_973, _T_969) @[el2_dec_dec_ctl.scala 135:54] + node _T_975 = and(_T_974, _T_971) @[el2_dec_dec_ctl.scala 135:54] + io.out.div <= _T_975 @[el2_dec_dec_ctl.scala 135:14] + node _T_976 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:33] + node _T_977 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_978 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_979 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_980 = eq(_T_979, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_981 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_982 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_983 = eq(_T_982, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_984 = and(_T_976, _T_977) @[el2_dec_dec_ctl.scala 136:57] + node _T_985 = and(_T_984, _T_978) @[el2_dec_dec_ctl.scala 136:57] + node _T_986 = and(_T_985, _T_980) @[el2_dec_dec_ctl.scala 136:57] + node _T_987 = and(_T_986, _T_981) @[el2_dec_dec_ctl.scala 136:57] + node _T_988 = and(_T_987, _T_983) @[el2_dec_dec_ctl.scala 136:57] + io.out.rem <= _T_988 @[el2_dec_dec_ctl.scala 136:14] + node _T_989 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_990 = eq(_T_989, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_991 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:33] + node _T_992 = and(_T_990, _T_991) @[el2_dec_dec_ctl.scala 137:47] + io.out.fence <= _T_992 @[el2_dec_dec_ctl.scala 137:16] + node _T_993 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_994 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_995 = eq(_T_994, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_996 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:33] + node _T_997 = and(_T_993, _T_995) @[el2_dec_dec_ctl.scala 138:52] + node _T_998 = and(_T_997, _T_996) @[el2_dec_dec_ctl.scala 138:52] + io.out.fence_i <= _T_998 @[el2_dec_dec_ctl.scala 138:18] + node _T_999 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:33] + node _T_1000 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 67:33] + node _T_1001 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1002 = eq(_T_1001, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1003 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_1004 = eq(_T_1003, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1005 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1006 = and(_T_999, _T_1000) @[el2_dec_dec_ctl.scala 139:59] + node _T_1007 = and(_T_1006, _T_1002) @[el2_dec_dec_ctl.scala 139:59] + node _T_1008 = and(_T_1007, _T_1004) @[el2_dec_dec_ctl.scala 139:59] + node _T_1009 = and(_T_1008, _T_1005) @[el2_dec_dec_ctl.scala 139:59] + node _T_1010 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1011 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:33] + node _T_1012 = and(_T_1010, _T_1011) @[el2_dec_dec_ctl.scala 139:92] + node _T_1013 = or(_T_1009, _T_1012) @[el2_dec_dec_ctl.scala 139:63] + node _T_1014 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] + node _T_1015 = eq(_T_1014, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1016 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_1017 = eq(_T_1016, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1018 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1019 = and(_T_1015, _T_1017) @[el2_dec_dec_ctl.scala 140:37] + node _T_1020 = and(_T_1019, _T_1018) @[el2_dec_dec_ctl.scala 140:37] + node _T_1021 = or(_T_1013, _T_1020) @[el2_dec_dec_ctl.scala 139:96] + node _T_1022 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_1023 = eq(_T_1022, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1024 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1025 = and(_T_1023, _T_1024) @[el2_dec_dec_ctl.scala 140:71] + node _T_1026 = or(_T_1021, _T_1025) @[el2_dec_dec_ctl.scala 140:41] + io.out.pm_alu <= _T_1026 @[el2_dec_dec_ctl.scala 139:17] + node _T_1027 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_1028 = eq(_T_1027, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1029 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:33] + node _T_1030 = and(_T_1028, _T_1029) @[el2_dec_dec_ctl.scala 141:49] + node _T_1031 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1032 = eq(_T_1031, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1033 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 67:33] + node _T_1034 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1035 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1036 = and(_T_1032, _T_1033) @[el2_dec_dec_ctl.scala 141:88] + node _T_1037 = and(_T_1036, _T_1034) @[el2_dec_dec_ctl.scala 141:88] + node _T_1038 = and(_T_1037, _T_1035) @[el2_dec_dec_ctl.scala 141:88] + node _T_1039 = or(_T_1030, _T_1038) @[el2_dec_dec_ctl.scala 141:53] + node _T_1040 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1041 = eq(_T_1040, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1042 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 67:33] + node _T_1043 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1044 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1045 = and(_T_1041, _T_1042) @[el2_dec_dec_ctl.scala 142:38] + node _T_1046 = and(_T_1045, _T_1043) @[el2_dec_dec_ctl.scala 142:38] + node _T_1047 = and(_T_1046, _T_1044) @[el2_dec_dec_ctl.scala 142:38] + node _T_1048 = or(_T_1039, _T_1047) @[el2_dec_dec_ctl.scala 141:92] + node _T_1049 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1050 = eq(_T_1049, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1051 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:33] + node _T_1052 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1053 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1054 = and(_T_1050, _T_1051) @[el2_dec_dec_ctl.scala 142:77] + node _T_1055 = and(_T_1054, _T_1052) @[el2_dec_dec_ctl.scala 142:77] + node _T_1056 = and(_T_1055, _T_1053) @[el2_dec_dec_ctl.scala 142:77] + node _T_1057 = or(_T_1048, _T_1056) @[el2_dec_dec_ctl.scala 142:42] + node _T_1058 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1059 = eq(_T_1058, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1060 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:33] + node _T_1061 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1062 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1063 = and(_T_1059, _T_1060) @[el2_dec_dec_ctl.scala 143:38] + node _T_1064 = and(_T_1063, _T_1061) @[el2_dec_dec_ctl.scala 143:38] + node _T_1065 = and(_T_1064, _T_1062) @[el2_dec_dec_ctl.scala 143:38] + node _T_1066 = or(_T_1057, _T_1065) @[el2_dec_dec_ctl.scala 142:81] + node _T_1067 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1068 = eq(_T_1067, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1069 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 67:33] + node _T_1070 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1071 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1072 = and(_T_1068, _T_1069) @[el2_dec_dec_ctl.scala 143:78] + node _T_1073 = and(_T_1072, _T_1070) @[el2_dec_dec_ctl.scala 143:78] + node _T_1074 = and(_T_1073, _T_1071) @[el2_dec_dec_ctl.scala 143:78] + node _T_1075 = or(_T_1066, _T_1074) @[el2_dec_dec_ctl.scala 143:42] + node _T_1076 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1077 = eq(_T_1076, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1078 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 67:33] + node _T_1079 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1080 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1081 = and(_T_1077, _T_1078) @[el2_dec_dec_ctl.scala 144:39] + node _T_1082 = and(_T_1081, _T_1079) @[el2_dec_dec_ctl.scala 144:39] + node _T_1083 = and(_T_1082, _T_1080) @[el2_dec_dec_ctl.scala 144:39] + node _T_1084 = or(_T_1075, _T_1083) @[el2_dec_dec_ctl.scala 143:82] + node _T_1085 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:33] + node _T_1086 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_1087 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1088 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1089 = and(_T_1085, _T_1086) @[el2_dec_dec_ctl.scala 144:78] + node _T_1090 = and(_T_1089, _T_1087) @[el2_dec_dec_ctl.scala 144:78] + node _T_1091 = and(_T_1090, _T_1088) @[el2_dec_dec_ctl.scala 144:78] + node _T_1092 = or(_T_1084, _T_1091) @[el2_dec_dec_ctl.scala 144:43] + node _T_1093 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:33] + node _T_1094 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_1095 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1096 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1097 = and(_T_1093, _T_1094) @[el2_dec_dec_ctl.scala 145:38] + node _T_1098 = and(_T_1097, _T_1095) @[el2_dec_dec_ctl.scala 145:38] + node _T_1099 = and(_T_1098, _T_1096) @[el2_dec_dec_ctl.scala 145:38] + node _T_1100 = or(_T_1092, _T_1099) @[el2_dec_dec_ctl.scala 144:82] + node _T_1101 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:33] + node _T_1102 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_1103 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1104 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1105 = and(_T_1101, _T_1102) @[el2_dec_dec_ctl.scala 145:77] + node _T_1106 = and(_T_1105, _T_1103) @[el2_dec_dec_ctl.scala 145:77] + node _T_1107 = and(_T_1106, _T_1104) @[el2_dec_dec_ctl.scala 145:77] + node _T_1108 = or(_T_1100, _T_1107) @[el2_dec_dec_ctl.scala 145:42] + node _T_1109 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:33] + node _T_1110 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_1111 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1112 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1113 = and(_T_1109, _T_1110) @[el2_dec_dec_ctl.scala 146:38] + node _T_1114 = and(_T_1113, _T_1111) @[el2_dec_dec_ctl.scala 146:38] + node _T_1115 = and(_T_1114, _T_1112) @[el2_dec_dec_ctl.scala 146:38] + node _T_1116 = or(_T_1108, _T_1115) @[el2_dec_dec_ctl.scala 145:81] + node _T_1117 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:33] + node _T_1118 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_1119 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1120 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1121 = and(_T_1117, _T_1118) @[el2_dec_dec_ctl.scala 146:77] + node _T_1122 = and(_T_1121, _T_1119) @[el2_dec_dec_ctl.scala 146:77] + node _T_1123 = and(_T_1122, _T_1120) @[el2_dec_dec_ctl.scala 146:77] + node _T_1124 = or(_T_1116, _T_1123) @[el2_dec_dec_ctl.scala 146:42] + io.out.presync <= _T_1124 @[el2_dec_dec_ctl.scala 141:18] + node _T_1125 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_1126 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_1127 = eq(_T_1126, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1128 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:33] + node _T_1129 = and(_T_1125, _T_1127) @[el2_dec_dec_ctl.scala 147:53] + node _T_1130 = and(_T_1129, _T_1128) @[el2_dec_dec_ctl.scala 147:53] + node _T_1131 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 67:52] + node _T_1132 = eq(_T_1131, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1133 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1134 = eq(_T_1133, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1135 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_1136 = eq(_T_1135, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1137 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1138 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1139 = and(_T_1132, _T_1134) @[el2_dec_dec_ctl.scala 147:98] + node _T_1140 = and(_T_1139, _T_1136) @[el2_dec_dec_ctl.scala 147:98] + node _T_1141 = and(_T_1140, _T_1137) @[el2_dec_dec_ctl.scala 147:98] + node _T_1142 = and(_T_1141, _T_1138) @[el2_dec_dec_ctl.scala 147:98] + node _T_1143 = or(_T_1130, _T_1142) @[el2_dec_dec_ctl.scala 147:57] + node _T_1144 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1145 = eq(_T_1144, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1146 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 67:33] + node _T_1147 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1148 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1149 = and(_T_1145, _T_1146) @[el2_dec_dec_ctl.scala 148:38] + node _T_1150 = and(_T_1149, _T_1147) @[el2_dec_dec_ctl.scala 148:38] + node _T_1151 = and(_T_1150, _T_1148) @[el2_dec_dec_ctl.scala 148:38] + node _T_1152 = or(_T_1143, _T_1151) @[el2_dec_dec_ctl.scala 147:102] + node _T_1153 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1154 = eq(_T_1153, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1155 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 67:33] + node _T_1156 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1157 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1158 = and(_T_1154, _T_1155) @[el2_dec_dec_ctl.scala 148:77] + node _T_1159 = and(_T_1158, _T_1156) @[el2_dec_dec_ctl.scala 148:77] + node _T_1160 = and(_T_1159, _T_1157) @[el2_dec_dec_ctl.scala 148:77] + node _T_1161 = or(_T_1152, _T_1160) @[el2_dec_dec_ctl.scala 148:42] + node _T_1162 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1163 = eq(_T_1162, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1164 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:33] + node _T_1165 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1166 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1167 = and(_T_1163, _T_1164) @[el2_dec_dec_ctl.scala 149:38] + node _T_1168 = and(_T_1167, _T_1165) @[el2_dec_dec_ctl.scala 149:38] + node _T_1169 = and(_T_1168, _T_1166) @[el2_dec_dec_ctl.scala 149:38] + node _T_1170 = or(_T_1161, _T_1169) @[el2_dec_dec_ctl.scala 148:81] + node _T_1171 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1172 = eq(_T_1171, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1173 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 67:33] + node _T_1174 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1175 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1176 = and(_T_1172, _T_1173) @[el2_dec_dec_ctl.scala 149:78] + node _T_1177 = and(_T_1176, _T_1174) @[el2_dec_dec_ctl.scala 149:78] + node _T_1178 = and(_T_1177, _T_1175) @[el2_dec_dec_ctl.scala 149:78] + node _T_1179 = or(_T_1170, _T_1178) @[el2_dec_dec_ctl.scala 149:42] + node _T_1180 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1181 = eq(_T_1180, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1182 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 67:33] + node _T_1183 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1184 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1185 = and(_T_1181, _T_1182) @[el2_dec_dec_ctl.scala 150:39] + node _T_1186 = and(_T_1185, _T_1183) @[el2_dec_dec_ctl.scala 150:39] + node _T_1187 = and(_T_1186, _T_1184) @[el2_dec_dec_ctl.scala 150:39] + node _T_1188 = or(_T_1179, _T_1187) @[el2_dec_dec_ctl.scala 149:82] + node _T_1189 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:33] + node _T_1190 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_1191 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1192 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1193 = and(_T_1189, _T_1190) @[el2_dec_dec_ctl.scala 150:78] + node _T_1194 = and(_T_1193, _T_1191) @[el2_dec_dec_ctl.scala 150:78] + node _T_1195 = and(_T_1194, _T_1192) @[el2_dec_dec_ctl.scala 150:78] + node _T_1196 = or(_T_1188, _T_1195) @[el2_dec_dec_ctl.scala 150:43] + node _T_1197 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:33] + node _T_1198 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_1199 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1200 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1201 = and(_T_1197, _T_1198) @[el2_dec_dec_ctl.scala 151:38] + node _T_1202 = and(_T_1201, _T_1199) @[el2_dec_dec_ctl.scala 151:38] + node _T_1203 = and(_T_1202, _T_1200) @[el2_dec_dec_ctl.scala 151:38] + node _T_1204 = or(_T_1196, _T_1203) @[el2_dec_dec_ctl.scala 150:82] + node _T_1205 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:33] + node _T_1206 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_1207 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1208 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1209 = and(_T_1205, _T_1206) @[el2_dec_dec_ctl.scala 151:77] + node _T_1210 = and(_T_1209, _T_1207) @[el2_dec_dec_ctl.scala 151:77] + node _T_1211 = and(_T_1210, _T_1208) @[el2_dec_dec_ctl.scala 151:77] + node _T_1212 = or(_T_1204, _T_1211) @[el2_dec_dec_ctl.scala 151:42] + node _T_1213 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:33] + node _T_1214 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_1215 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1216 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1217 = and(_T_1213, _T_1214) @[el2_dec_dec_ctl.scala 152:38] + node _T_1218 = and(_T_1217, _T_1215) @[el2_dec_dec_ctl.scala 152:38] + node _T_1219 = and(_T_1218, _T_1216) @[el2_dec_dec_ctl.scala 152:38] + node _T_1220 = or(_T_1212, _T_1219) @[el2_dec_dec_ctl.scala 151:81] + node _T_1221 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:33] + node _T_1222 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_1223 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1224 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1225 = and(_T_1221, _T_1222) @[el2_dec_dec_ctl.scala 152:77] + node _T_1226 = and(_T_1225, _T_1223) @[el2_dec_dec_ctl.scala 152:77] + node _T_1227 = and(_T_1226, _T_1224) @[el2_dec_dec_ctl.scala 152:77] + node _T_1228 = or(_T_1220, _T_1227) @[el2_dec_dec_ctl.scala 152:42] + io.out.postsync <= _T_1228 @[el2_dec_dec_ctl.scala 147:19] + node _T_1229 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 67:52] + node _T_1230 = eq(_T_1229, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1231 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:52] + node _T_1232 = eq(_T_1231, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1233 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:33] + node _T_1234 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:33] + node _T_1235 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 67:52] + node _T_1236 = eq(_T_1235, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1237 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 67:52] + node _T_1238 = eq(_T_1237, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1239 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] + node _T_1240 = eq(_T_1239, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1241 = bits(io.ins, 24, 24) @[el2_dec_dec_ctl.scala 67:52] + node _T_1242 = eq(_T_1241, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1243 = bits(io.ins, 23, 23) @[el2_dec_dec_ctl.scala 67:52] + node _T_1244 = eq(_T_1243, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1245 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 67:52] + node _T_1246 = eq(_T_1245, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1247 = bits(io.ins, 21, 21) @[el2_dec_dec_ctl.scala 67:33] + node _T_1248 = bits(io.ins, 20, 20) @[el2_dec_dec_ctl.scala 67:52] + node _T_1249 = eq(_T_1248, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1250 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:52] + node _T_1251 = eq(_T_1250, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1252 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:52] + node _T_1253 = eq(_T_1252, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1254 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:52] + node _T_1255 = eq(_T_1254, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1256 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:52] + node _T_1257 = eq(_T_1256, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1258 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:52] + node _T_1259 = eq(_T_1258, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1260 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_1261 = eq(_T_1260, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1262 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 67:52] + node _T_1263 = eq(_T_1262, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1264 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 67:52] + node _T_1265 = eq(_T_1264, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1266 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:52] + node _T_1267 = eq(_T_1266, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1268 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 67:52] + node _T_1269 = eq(_T_1268, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1270 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 67:52] + node _T_1271 = eq(_T_1270, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1272 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1273 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_1274 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1275 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] + node _T_1276 = eq(_T_1275, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1277 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_1278 = eq(_T_1277, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1279 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] + node _T_1280 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] + node _T_1281 = eq(_T_1280, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1282 = and(_T_1230, _T_1232) @[el2_dec_dec_ctl.scala 153:144] + node _T_1283 = and(_T_1282, _T_1233) @[el2_dec_dec_ctl.scala 153:144] + node _T_1284 = and(_T_1283, _T_1234) @[el2_dec_dec_ctl.scala 153:144] + node _T_1285 = and(_T_1284, _T_1236) @[el2_dec_dec_ctl.scala 153:144] + node _T_1286 = and(_T_1285, _T_1238) @[el2_dec_dec_ctl.scala 153:144] + node _T_1287 = and(_T_1286, _T_1240) @[el2_dec_dec_ctl.scala 153:144] + node _T_1288 = and(_T_1287, _T_1242) @[el2_dec_dec_ctl.scala 153:144] + node _T_1289 = and(_T_1288, _T_1244) @[el2_dec_dec_ctl.scala 153:144] + node _T_1290 = and(_T_1289, _T_1246) @[el2_dec_dec_ctl.scala 153:144] + node _T_1291 = and(_T_1290, _T_1247) @[el2_dec_dec_ctl.scala 153:144] + node _T_1292 = and(_T_1291, _T_1249) @[el2_dec_dec_ctl.scala 153:144] + node _T_1293 = and(_T_1292, _T_1251) @[el2_dec_dec_ctl.scala 153:144] + node _T_1294 = and(_T_1293, _T_1253) @[el2_dec_dec_ctl.scala 153:144] + node _T_1295 = and(_T_1294, _T_1255) @[el2_dec_dec_ctl.scala 153:144] + node _T_1296 = and(_T_1295, _T_1257) @[el2_dec_dec_ctl.scala 153:144] + node _T_1297 = and(_T_1296, _T_1259) @[el2_dec_dec_ctl.scala 153:144] + node _T_1298 = and(_T_1297, _T_1261) @[el2_dec_dec_ctl.scala 153:144] + node _T_1299 = and(_T_1298, _T_1263) @[el2_dec_dec_ctl.scala 153:144] + node _T_1300 = and(_T_1299, _T_1265) @[el2_dec_dec_ctl.scala 153:144] + node _T_1301 = and(_T_1300, _T_1267) @[el2_dec_dec_ctl.scala 153:144] + node _T_1302 = and(_T_1301, _T_1269) @[el2_dec_dec_ctl.scala 153:144] + node _T_1303 = and(_T_1302, _T_1271) @[el2_dec_dec_ctl.scala 153:144] + node _T_1304 = and(_T_1303, _T_1272) @[el2_dec_dec_ctl.scala 153:144] + node _T_1305 = and(_T_1304, _T_1273) @[el2_dec_dec_ctl.scala 153:144] + node _T_1306 = and(_T_1305, _T_1274) @[el2_dec_dec_ctl.scala 153:144] + node _T_1307 = and(_T_1306, _T_1276) @[el2_dec_dec_ctl.scala 153:144] + node _T_1308 = and(_T_1307, _T_1278) @[el2_dec_dec_ctl.scala 153:144] + node _T_1309 = and(_T_1308, _T_1279) @[el2_dec_dec_ctl.scala 153:144] + node _T_1310 = and(_T_1309, _T_1281) @[el2_dec_dec_ctl.scala 153:144] + node _T_1311 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 67:52] + node _T_1312 = eq(_T_1311, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1313 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:52] + node _T_1314 = eq(_T_1313, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1315 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:52] + node _T_1316 = eq(_T_1315, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1317 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:33] + node _T_1318 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 67:52] + node _T_1319 = eq(_T_1318, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1320 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 67:52] + node _T_1321 = eq(_T_1320, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1322 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] + node _T_1323 = eq(_T_1322, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1324 = bits(io.ins, 24, 24) @[el2_dec_dec_ctl.scala 67:52] + node _T_1325 = eq(_T_1324, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1326 = bits(io.ins, 23, 23) @[el2_dec_dec_ctl.scala 67:52] + node _T_1327 = eq(_T_1326, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1328 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 67:33] + node _T_1329 = bits(io.ins, 21, 21) @[el2_dec_dec_ctl.scala 67:52] + node _T_1330 = eq(_T_1329, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1331 = bits(io.ins, 20, 20) @[el2_dec_dec_ctl.scala 67:33] + node _T_1332 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:52] + node _T_1333 = eq(_T_1332, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1334 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:52] + node _T_1335 = eq(_T_1334, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1336 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:52] + node _T_1337 = eq(_T_1336, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1338 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:52] + node _T_1339 = eq(_T_1338, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1340 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:52] + node _T_1341 = eq(_T_1340, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1342 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_1343 = eq(_T_1342, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1344 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 67:52] + node _T_1345 = eq(_T_1344, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1346 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 67:52] + node _T_1347 = eq(_T_1346, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1348 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:52] + node _T_1349 = eq(_T_1348, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1350 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 67:52] + node _T_1351 = eq(_T_1350, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1352 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 67:52] + node _T_1353 = eq(_T_1352, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1354 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1355 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_1356 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1357 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] + node _T_1358 = eq(_T_1357, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1359 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_1360 = eq(_T_1359, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1361 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] + node _T_1362 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] + node _T_1363 = eq(_T_1362, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1364 = and(_T_1312, _T_1314) @[el2_dec_dec_ctl.scala 154:130] + node _T_1365 = and(_T_1364, _T_1316) @[el2_dec_dec_ctl.scala 154:130] + node _T_1366 = and(_T_1365, _T_1317) @[el2_dec_dec_ctl.scala 154:130] + node _T_1367 = and(_T_1366, _T_1319) @[el2_dec_dec_ctl.scala 154:130] + node _T_1368 = and(_T_1367, _T_1321) @[el2_dec_dec_ctl.scala 154:130] + node _T_1369 = and(_T_1368, _T_1323) @[el2_dec_dec_ctl.scala 154:130] + node _T_1370 = and(_T_1369, _T_1325) @[el2_dec_dec_ctl.scala 154:130] + node _T_1371 = and(_T_1370, _T_1327) @[el2_dec_dec_ctl.scala 154:130] + node _T_1372 = and(_T_1371, _T_1328) @[el2_dec_dec_ctl.scala 154:130] + node _T_1373 = and(_T_1372, _T_1330) @[el2_dec_dec_ctl.scala 154:130] + node _T_1374 = and(_T_1373, _T_1331) @[el2_dec_dec_ctl.scala 154:130] + node _T_1375 = and(_T_1374, _T_1333) @[el2_dec_dec_ctl.scala 154:130] + node _T_1376 = and(_T_1375, _T_1335) @[el2_dec_dec_ctl.scala 154:130] + node _T_1377 = and(_T_1376, _T_1337) @[el2_dec_dec_ctl.scala 154:130] + node _T_1378 = and(_T_1377, _T_1339) @[el2_dec_dec_ctl.scala 154:130] + node _T_1379 = and(_T_1378, _T_1341) @[el2_dec_dec_ctl.scala 154:130] + node _T_1380 = and(_T_1379, _T_1343) @[el2_dec_dec_ctl.scala 154:130] + node _T_1381 = and(_T_1380, _T_1345) @[el2_dec_dec_ctl.scala 154:130] + node _T_1382 = and(_T_1381, _T_1347) @[el2_dec_dec_ctl.scala 154:130] + node _T_1383 = and(_T_1382, _T_1349) @[el2_dec_dec_ctl.scala 154:130] + node _T_1384 = and(_T_1383, _T_1351) @[el2_dec_dec_ctl.scala 154:130] + node _T_1385 = and(_T_1384, _T_1353) @[el2_dec_dec_ctl.scala 154:130] + node _T_1386 = and(_T_1385, _T_1354) @[el2_dec_dec_ctl.scala 154:130] + node _T_1387 = and(_T_1386, _T_1355) @[el2_dec_dec_ctl.scala 154:130] + node _T_1388 = and(_T_1387, _T_1356) @[el2_dec_dec_ctl.scala 154:130] + node _T_1389 = and(_T_1388, _T_1358) @[el2_dec_dec_ctl.scala 154:130] + node _T_1390 = and(_T_1389, _T_1360) @[el2_dec_dec_ctl.scala 154:130] + node _T_1391 = and(_T_1390, _T_1361) @[el2_dec_dec_ctl.scala 154:130] + node _T_1392 = and(_T_1391, _T_1363) @[el2_dec_dec_ctl.scala 154:130] + node _T_1393 = or(_T_1310, _T_1392) @[el2_dec_dec_ctl.scala 153:148] + node _T_1394 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 67:52] + node _T_1395 = eq(_T_1394, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1396 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:52] + node _T_1397 = eq(_T_1396, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1398 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:52] + node _T_1399 = eq(_T_1398, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1400 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:52] + node _T_1401 = eq(_T_1400, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1402 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 67:52] + node _T_1403 = eq(_T_1402, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1404 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 67:52] + node _T_1405 = eq(_T_1404, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1406 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] + node _T_1407 = eq(_T_1406, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1408 = bits(io.ins, 24, 24) @[el2_dec_dec_ctl.scala 67:52] + node _T_1409 = eq(_T_1408, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1410 = bits(io.ins, 23, 23) @[el2_dec_dec_ctl.scala 67:52] + node _T_1411 = eq(_T_1410, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1412 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 67:52] + node _T_1413 = eq(_T_1412, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1414 = bits(io.ins, 21, 21) @[el2_dec_dec_ctl.scala 67:52] + node _T_1415 = eq(_T_1414, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1416 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:52] + node _T_1417 = eq(_T_1416, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1418 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:52] + node _T_1419 = eq(_T_1418, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1420 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:52] + node _T_1421 = eq(_T_1420, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1422 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:52] + node _T_1423 = eq(_T_1422, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1424 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:52] + node _T_1425 = eq(_T_1424, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1426 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_1427 = eq(_T_1426, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1428 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 67:52] + node _T_1429 = eq(_T_1428, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1430 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 67:52] + node _T_1431 = eq(_T_1430, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1432 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:52] + node _T_1433 = eq(_T_1432, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1434 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 67:52] + node _T_1435 = eq(_T_1434, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1436 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 67:52] + node _T_1437 = eq(_T_1436, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1438 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_1439 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1440 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] + node _T_1441 = eq(_T_1440, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1442 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_1443 = eq(_T_1442, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1444 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] + node _T_1445 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] + node _T_1446 = eq(_T_1445, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1447 = and(_T_1395, _T_1397) @[el2_dec_dec_ctl.scala 155:127] + node _T_1448 = and(_T_1447, _T_1399) @[el2_dec_dec_ctl.scala 155:127] + node _T_1449 = and(_T_1448, _T_1401) @[el2_dec_dec_ctl.scala 155:127] + node _T_1450 = and(_T_1449, _T_1403) @[el2_dec_dec_ctl.scala 155:127] + node _T_1451 = and(_T_1450, _T_1405) @[el2_dec_dec_ctl.scala 155:127] + node _T_1452 = and(_T_1451, _T_1407) @[el2_dec_dec_ctl.scala 155:127] + node _T_1453 = and(_T_1452, _T_1409) @[el2_dec_dec_ctl.scala 155:127] + node _T_1454 = and(_T_1453, _T_1411) @[el2_dec_dec_ctl.scala 155:127] + node _T_1455 = and(_T_1454, _T_1413) @[el2_dec_dec_ctl.scala 155:127] + node _T_1456 = and(_T_1455, _T_1415) @[el2_dec_dec_ctl.scala 155:127] + node _T_1457 = and(_T_1456, _T_1417) @[el2_dec_dec_ctl.scala 155:127] + node _T_1458 = and(_T_1457, _T_1419) @[el2_dec_dec_ctl.scala 155:127] + node _T_1459 = and(_T_1458, _T_1421) @[el2_dec_dec_ctl.scala 155:127] + node _T_1460 = and(_T_1459, _T_1423) @[el2_dec_dec_ctl.scala 155:127] + node _T_1461 = and(_T_1460, _T_1425) @[el2_dec_dec_ctl.scala 155:127] + node _T_1462 = and(_T_1461, _T_1427) @[el2_dec_dec_ctl.scala 155:127] + node _T_1463 = and(_T_1462, _T_1429) @[el2_dec_dec_ctl.scala 155:127] + node _T_1464 = and(_T_1463, _T_1431) @[el2_dec_dec_ctl.scala 155:127] + node _T_1465 = and(_T_1464, _T_1433) @[el2_dec_dec_ctl.scala 155:127] + node _T_1466 = and(_T_1465, _T_1435) @[el2_dec_dec_ctl.scala 155:127] + node _T_1467 = and(_T_1466, _T_1437) @[el2_dec_dec_ctl.scala 155:127] + node _T_1468 = and(_T_1467, _T_1438) @[el2_dec_dec_ctl.scala 155:127] + node _T_1469 = and(_T_1468, _T_1439) @[el2_dec_dec_ctl.scala 155:127] + node _T_1470 = and(_T_1469, _T_1441) @[el2_dec_dec_ctl.scala 155:127] + node _T_1471 = and(_T_1470, _T_1443) @[el2_dec_dec_ctl.scala 155:127] + node _T_1472 = and(_T_1471, _T_1444) @[el2_dec_dec_ctl.scala 155:127] + node _T_1473 = and(_T_1472, _T_1446) @[el2_dec_dec_ctl.scala 155:127] + node _T_1474 = or(_T_1393, _T_1473) @[el2_dec_dec_ctl.scala 154:134] + node _T_1475 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 67:52] + node _T_1476 = eq(_T_1475, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1477 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:52] + node _T_1478 = eq(_T_1477, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1479 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:52] + node _T_1480 = eq(_T_1479, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1481 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:52] + node _T_1482 = eq(_T_1481, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1483 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 67:52] + node _T_1484 = eq(_T_1483, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1485 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 67:52] + node _T_1486 = eq(_T_1485, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1487 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] + node _T_1488 = eq(_T_1487, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1489 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_1490 = eq(_T_1489, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1491 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1492 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] + node _T_1493 = eq(_T_1492, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1494 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] + node _T_1495 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] + node _T_1496 = eq(_T_1495, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1497 = and(_T_1476, _T_1478) @[el2_dec_dec_ctl.scala 156:68] + node _T_1498 = and(_T_1497, _T_1480) @[el2_dec_dec_ctl.scala 156:68] + node _T_1499 = and(_T_1498, _T_1482) @[el2_dec_dec_ctl.scala 156:68] + node _T_1500 = and(_T_1499, _T_1484) @[el2_dec_dec_ctl.scala 156:68] + node _T_1501 = and(_T_1500, _T_1486) @[el2_dec_dec_ctl.scala 156:68] + node _T_1502 = and(_T_1501, _T_1488) @[el2_dec_dec_ctl.scala 156:68] + node _T_1503 = and(_T_1502, _T_1490) @[el2_dec_dec_ctl.scala 156:68] + node _T_1504 = and(_T_1503, _T_1491) @[el2_dec_dec_ctl.scala 156:68] + node _T_1505 = and(_T_1504, _T_1493) @[el2_dec_dec_ctl.scala 156:68] + node _T_1506 = and(_T_1505, _T_1494) @[el2_dec_dec_ctl.scala 156:68] + node _T_1507 = and(_T_1506, _T_1496) @[el2_dec_dec_ctl.scala 156:68] + node _T_1508 = or(_T_1474, _T_1507) @[el2_dec_dec_ctl.scala 155:131] + node _T_1509 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 67:52] + node _T_1510 = eq(_T_1509, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1511 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:52] + node _T_1512 = eq(_T_1511, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1513 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:52] + node _T_1514 = eq(_T_1513, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1515 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 67:52] + node _T_1516 = eq(_T_1515, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1517 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 67:52] + node _T_1518 = eq(_T_1517, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1519 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] + node _T_1520 = eq(_T_1519, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1521 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_1522 = eq(_T_1521, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1523 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1524 = eq(_T_1523, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1525 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_1526 = eq(_T_1525, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1527 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_1528 = eq(_T_1527, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1529 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] + node _T_1530 = eq(_T_1529, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1531 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_1532 = eq(_T_1531, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1533 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] + node _T_1534 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] + node _T_1535 = eq(_T_1534, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1536 = and(_T_1510, _T_1512) @[el2_dec_dec_ctl.scala 157:77] + node _T_1537 = and(_T_1536, _T_1514) @[el2_dec_dec_ctl.scala 157:77] + node _T_1538 = and(_T_1537, _T_1516) @[el2_dec_dec_ctl.scala 157:77] + node _T_1539 = and(_T_1538, _T_1518) @[el2_dec_dec_ctl.scala 157:77] + node _T_1540 = and(_T_1539, _T_1520) @[el2_dec_dec_ctl.scala 157:77] + node _T_1541 = and(_T_1540, _T_1522) @[el2_dec_dec_ctl.scala 157:77] + node _T_1542 = and(_T_1541, _T_1524) @[el2_dec_dec_ctl.scala 157:77] + node _T_1543 = and(_T_1542, _T_1526) @[el2_dec_dec_ctl.scala 157:77] + node _T_1544 = and(_T_1543, _T_1528) @[el2_dec_dec_ctl.scala 157:77] + node _T_1545 = and(_T_1544, _T_1530) @[el2_dec_dec_ctl.scala 157:77] + node _T_1546 = and(_T_1545, _T_1532) @[el2_dec_dec_ctl.scala 157:77] + node _T_1547 = and(_T_1546, _T_1533) @[el2_dec_dec_ctl.scala 157:77] + node _T_1548 = and(_T_1547, _T_1535) @[el2_dec_dec_ctl.scala 157:77] + node _T_1549 = or(_T_1508, _T_1548) @[el2_dec_dec_ctl.scala 156:72] + node _T_1550 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 67:52] + node _T_1551 = eq(_T_1550, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1552 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:52] + node _T_1553 = eq(_T_1552, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1554 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:52] + node _T_1555 = eq(_T_1554, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1556 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 67:52] + node _T_1557 = eq(_T_1556, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1558 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 67:52] + node _T_1559 = eq(_T_1558, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1560 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] + node _T_1561 = eq(_T_1560, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1562 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_1563 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1564 = eq(_T_1563, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1565 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_1566 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_1567 = eq(_T_1566, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1568 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1569 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] + node _T_1570 = eq(_T_1569, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1571 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] + node _T_1572 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] + node _T_1573 = eq(_T_1572, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1574 = and(_T_1551, _T_1553) @[el2_dec_dec_ctl.scala 158:74] + node _T_1575 = and(_T_1574, _T_1555) @[el2_dec_dec_ctl.scala 158:74] + node _T_1576 = and(_T_1575, _T_1557) @[el2_dec_dec_ctl.scala 158:74] + node _T_1577 = and(_T_1576, _T_1559) @[el2_dec_dec_ctl.scala 158:74] + node _T_1578 = and(_T_1577, _T_1561) @[el2_dec_dec_ctl.scala 158:74] + node _T_1579 = and(_T_1578, _T_1562) @[el2_dec_dec_ctl.scala 158:74] + node _T_1580 = and(_T_1579, _T_1564) @[el2_dec_dec_ctl.scala 158:74] + node _T_1581 = and(_T_1580, _T_1565) @[el2_dec_dec_ctl.scala 158:74] + node _T_1582 = and(_T_1581, _T_1567) @[el2_dec_dec_ctl.scala 158:74] + node _T_1583 = and(_T_1582, _T_1568) @[el2_dec_dec_ctl.scala 158:74] + node _T_1584 = and(_T_1583, _T_1570) @[el2_dec_dec_ctl.scala 158:74] + node _T_1585 = and(_T_1584, _T_1571) @[el2_dec_dec_ctl.scala 158:74] + node _T_1586 = and(_T_1585, _T_1573) @[el2_dec_dec_ctl.scala 158:74] + node _T_1587 = or(_T_1549, _T_1586) @[el2_dec_dec_ctl.scala 157:81] + node _T_1588 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 67:52] + node _T_1589 = eq(_T_1588, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1590 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:52] + node _T_1591 = eq(_T_1590, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1592 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:52] + node _T_1593 = eq(_T_1592, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1594 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:52] + node _T_1595 = eq(_T_1594, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1596 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 67:52] + node _T_1597 = eq(_T_1596, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1598 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 67:52] + node _T_1599 = eq(_T_1598, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1600 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_1601 = eq(_T_1600, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1602 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_1603 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1604 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] + node _T_1605 = eq(_T_1604, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1606 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] + node _T_1607 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] + node _T_1608 = eq(_T_1607, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1609 = and(_T_1589, _T_1591) @[el2_dec_dec_ctl.scala 159:66] + node _T_1610 = and(_T_1609, _T_1593) @[el2_dec_dec_ctl.scala 159:66] + node _T_1611 = and(_T_1610, _T_1595) @[el2_dec_dec_ctl.scala 159:66] + node _T_1612 = and(_T_1611, _T_1597) @[el2_dec_dec_ctl.scala 159:66] + node _T_1613 = and(_T_1612, _T_1599) @[el2_dec_dec_ctl.scala 159:66] + node _T_1614 = and(_T_1613, _T_1601) @[el2_dec_dec_ctl.scala 159:66] + node _T_1615 = and(_T_1614, _T_1602) @[el2_dec_dec_ctl.scala 159:66] + node _T_1616 = and(_T_1615, _T_1603) @[el2_dec_dec_ctl.scala 159:66] + node _T_1617 = and(_T_1616, _T_1605) @[el2_dec_dec_ctl.scala 159:66] + node _T_1618 = and(_T_1617, _T_1606) @[el2_dec_dec_ctl.scala 159:66] + node _T_1619 = and(_T_1618, _T_1608) @[el2_dec_dec_ctl.scala 159:66] + node _T_1620 = or(_T_1587, _T_1619) @[el2_dec_dec_ctl.scala 158:78] + node _T_1621 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_1622 = eq(_T_1621, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1623 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1624 = eq(_T_1623, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1625 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_1626 = eq(_T_1625, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1627 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1628 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_1629 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_1630 = eq(_T_1629, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1631 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] + node _T_1632 = eq(_T_1631, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1633 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] + node _T_1634 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] + node _T_1635 = eq(_T_1634, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1636 = and(_T_1622, _T_1624) @[el2_dec_dec_ctl.scala 160:54] + node _T_1637 = and(_T_1636, _T_1626) @[el2_dec_dec_ctl.scala 160:54] + node _T_1638 = and(_T_1637, _T_1627) @[el2_dec_dec_ctl.scala 160:54] + node _T_1639 = and(_T_1638, _T_1628) @[el2_dec_dec_ctl.scala 160:54] + node _T_1640 = and(_T_1639, _T_1630) @[el2_dec_dec_ctl.scala 160:54] + node _T_1641 = and(_T_1640, _T_1632) @[el2_dec_dec_ctl.scala 160:54] + node _T_1642 = and(_T_1641, _T_1633) @[el2_dec_dec_ctl.scala 160:54] + node _T_1643 = and(_T_1642, _T_1635) @[el2_dec_dec_ctl.scala 160:54] + node _T_1644 = or(_T_1620, _T_1643) @[el2_dec_dec_ctl.scala 159:70] + node _T_1645 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_1646 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1647 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_1648 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_1649 = eq(_T_1648, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1650 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] + node _T_1651 = eq(_T_1650, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1652 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_1653 = eq(_T_1652, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1654 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] + node _T_1655 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] + node _T_1656 = eq(_T_1655, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1657 = and(_T_1645, _T_1646) @[el2_dec_dec_ctl.scala 161:48] + node _T_1658 = and(_T_1657, _T_1647) @[el2_dec_dec_ctl.scala 161:48] + node _T_1659 = and(_T_1658, _T_1649) @[el2_dec_dec_ctl.scala 161:48] + node _T_1660 = and(_T_1659, _T_1651) @[el2_dec_dec_ctl.scala 161:48] + node _T_1661 = and(_T_1660, _T_1653) @[el2_dec_dec_ctl.scala 161:48] + node _T_1662 = and(_T_1661, _T_1654) @[el2_dec_dec_ctl.scala 161:48] + node _T_1663 = and(_T_1662, _T_1656) @[el2_dec_dec_ctl.scala 161:48] + node _T_1664 = or(_T_1644, _T_1663) @[el2_dec_dec_ctl.scala 160:58] + node _T_1665 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_1666 = eq(_T_1665, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1667 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_1668 = eq(_T_1667, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1669 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_1670 = eq(_T_1669, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1671 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1672 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] + node _T_1673 = eq(_T_1672, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1674 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] + node _T_1675 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] + node _T_1676 = eq(_T_1675, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1677 = and(_T_1666, _T_1668) @[el2_dec_dec_ctl.scala 162:47] + node _T_1678 = and(_T_1677, _T_1670) @[el2_dec_dec_ctl.scala 162:47] + node _T_1679 = and(_T_1678, _T_1671) @[el2_dec_dec_ctl.scala 162:47] + node _T_1680 = and(_T_1679, _T_1673) @[el2_dec_dec_ctl.scala 162:47] + node _T_1681 = and(_T_1680, _T_1674) @[el2_dec_dec_ctl.scala 162:47] + node _T_1682 = and(_T_1681, _T_1676) @[el2_dec_dec_ctl.scala 162:47] + node _T_1683 = or(_T_1664, _T_1682) @[el2_dec_dec_ctl.scala 161:52] + node _T_1684 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_1685 = eq(_T_1684, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1686 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1687 = eq(_T_1686, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1688 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_1689 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_1690 = eq(_T_1689, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1691 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] + node _T_1692 = eq(_T_1691, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1693 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_1694 = eq(_T_1693, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1695 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] + node _T_1696 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] + node _T_1697 = eq(_T_1696, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1698 = and(_T_1685, _T_1687) @[el2_dec_dec_ctl.scala 162:99] + node _T_1699 = and(_T_1698, _T_1688) @[el2_dec_dec_ctl.scala 162:99] + node _T_1700 = and(_T_1699, _T_1690) @[el2_dec_dec_ctl.scala 162:99] + node _T_1701 = and(_T_1700, _T_1692) @[el2_dec_dec_ctl.scala 162:99] + node _T_1702 = and(_T_1701, _T_1694) @[el2_dec_dec_ctl.scala 162:99] + node _T_1703 = and(_T_1702, _T_1695) @[el2_dec_dec_ctl.scala 162:99] + node _T_1704 = and(_T_1703, _T_1697) @[el2_dec_dec_ctl.scala 162:99] + node _T_1705 = or(_T_1683, _T_1704) @[el2_dec_dec_ctl.scala 162:51] + node _T_1706 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_1707 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1708 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_1709 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1710 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] + node _T_1711 = eq(_T_1710, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1712 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_1713 = eq(_T_1712, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1714 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] + node _T_1715 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] + node _T_1716 = eq(_T_1715, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1717 = and(_T_1706, _T_1707) @[el2_dec_dec_ctl.scala 163:47] + node _T_1718 = and(_T_1717, _T_1708) @[el2_dec_dec_ctl.scala 163:47] + node _T_1719 = and(_T_1718, _T_1709) @[el2_dec_dec_ctl.scala 163:47] + node _T_1720 = and(_T_1719, _T_1711) @[el2_dec_dec_ctl.scala 163:47] + node _T_1721 = and(_T_1720, _T_1713) @[el2_dec_dec_ctl.scala 163:47] + node _T_1722 = and(_T_1721, _T_1714) @[el2_dec_dec_ctl.scala 163:47] + node _T_1723 = and(_T_1722, _T_1716) @[el2_dec_dec_ctl.scala 163:47] + node _T_1724 = or(_T_1705, _T_1723) @[el2_dec_dec_ctl.scala 162:103] + node _T_1725 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 67:52] + node _T_1726 = eq(_T_1725, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1727 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:52] + node _T_1728 = eq(_T_1727, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1729 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:52] + node _T_1730 = eq(_T_1729, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1731 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:52] + node _T_1732 = eq(_T_1731, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1733 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 67:52] + node _T_1734 = eq(_T_1733, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1735 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 67:52] + node _T_1736 = eq(_T_1735, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1737 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] + node _T_1738 = eq(_T_1737, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1739 = bits(io.ins, 24, 24) @[el2_dec_dec_ctl.scala 67:52] + node _T_1740 = eq(_T_1739, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1741 = bits(io.ins, 23, 23) @[el2_dec_dec_ctl.scala 67:52] + node _T_1742 = eq(_T_1741, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1743 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 67:52] + node _T_1744 = eq(_T_1743, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1745 = bits(io.ins, 21, 21) @[el2_dec_dec_ctl.scala 67:52] + node _T_1746 = eq(_T_1745, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1747 = bits(io.ins, 20, 20) @[el2_dec_dec_ctl.scala 67:52] + node _T_1748 = eq(_T_1747, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1749 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:52] + node _T_1750 = eq(_T_1749, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1751 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:52] + node _T_1752 = eq(_T_1751, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1753 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:52] + node _T_1754 = eq(_T_1753, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1755 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:52] + node _T_1756 = eq(_T_1755, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1757 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:52] + node _T_1758 = eq(_T_1757, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1759 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_1760 = eq(_T_1759, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1761 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1762 = eq(_T_1761, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1763 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_1764 = eq(_T_1763, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1765 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 67:52] + node _T_1766 = eq(_T_1765, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1767 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 67:52] + node _T_1768 = eq(_T_1767, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1769 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:52] + node _T_1770 = eq(_T_1769, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1771 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 67:52] + node _T_1772 = eq(_T_1771, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1773 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 67:52] + node _T_1774 = eq(_T_1773, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1775 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_1776 = eq(_T_1775, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1777 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_1778 = eq(_T_1777, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1779 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_1780 = eq(_T_1779, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1781 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:33] + node _T_1782 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:33] + node _T_1783 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] + node _T_1784 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] + node _T_1785 = eq(_T_1784, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1786 = and(_T_1726, _T_1728) @[el2_dec_dec_ctl.scala 164:142] + node _T_1787 = and(_T_1786, _T_1730) @[el2_dec_dec_ctl.scala 164:142] + node _T_1788 = and(_T_1787, _T_1732) @[el2_dec_dec_ctl.scala 164:142] + node _T_1789 = and(_T_1788, _T_1734) @[el2_dec_dec_ctl.scala 164:142] + node _T_1790 = and(_T_1789, _T_1736) @[el2_dec_dec_ctl.scala 164:142] + node _T_1791 = and(_T_1790, _T_1738) @[el2_dec_dec_ctl.scala 164:142] + node _T_1792 = and(_T_1791, _T_1740) @[el2_dec_dec_ctl.scala 164:142] + node _T_1793 = and(_T_1792, _T_1742) @[el2_dec_dec_ctl.scala 164:142] + node _T_1794 = and(_T_1793, _T_1744) @[el2_dec_dec_ctl.scala 164:142] + node _T_1795 = and(_T_1794, _T_1746) @[el2_dec_dec_ctl.scala 164:142] + node _T_1796 = and(_T_1795, _T_1748) @[el2_dec_dec_ctl.scala 164:142] + node _T_1797 = and(_T_1796, _T_1750) @[el2_dec_dec_ctl.scala 164:142] + node _T_1798 = and(_T_1797, _T_1752) @[el2_dec_dec_ctl.scala 164:142] + node _T_1799 = and(_T_1798, _T_1754) @[el2_dec_dec_ctl.scala 164:142] + node _T_1800 = and(_T_1799, _T_1756) @[el2_dec_dec_ctl.scala 164:142] + node _T_1801 = and(_T_1800, _T_1758) @[el2_dec_dec_ctl.scala 164:142] + node _T_1802 = and(_T_1801, _T_1760) @[el2_dec_dec_ctl.scala 164:142] + node _T_1803 = and(_T_1802, _T_1762) @[el2_dec_dec_ctl.scala 164:142] + node _T_1804 = and(_T_1803, _T_1764) @[el2_dec_dec_ctl.scala 164:142] + node _T_1805 = and(_T_1804, _T_1766) @[el2_dec_dec_ctl.scala 164:142] + node _T_1806 = and(_T_1805, _T_1768) @[el2_dec_dec_ctl.scala 164:142] + node _T_1807 = and(_T_1806, _T_1770) @[el2_dec_dec_ctl.scala 164:142] + node _T_1808 = and(_T_1807, _T_1772) @[el2_dec_dec_ctl.scala 164:142] + node _T_1809 = and(_T_1808, _T_1774) @[el2_dec_dec_ctl.scala 164:142] + node _T_1810 = and(_T_1809, _T_1776) @[el2_dec_dec_ctl.scala 164:142] + node _T_1811 = and(_T_1810, _T_1778) @[el2_dec_dec_ctl.scala 164:142] + node _T_1812 = and(_T_1811, _T_1780) @[el2_dec_dec_ctl.scala 164:142] + node _T_1813 = and(_T_1812, _T_1781) @[el2_dec_dec_ctl.scala 164:142] + node _T_1814 = and(_T_1813, _T_1782) @[el2_dec_dec_ctl.scala 164:142] + node _T_1815 = and(_T_1814, _T_1783) @[el2_dec_dec_ctl.scala 164:142] + node _T_1816 = and(_T_1815, _T_1785) @[el2_dec_dec_ctl.scala 164:142] + node _T_1817 = or(_T_1724, _T_1816) @[el2_dec_dec_ctl.scala 163:51] + node _T_1818 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 67:52] + node _T_1819 = eq(_T_1818, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1820 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:52] + node _T_1821 = eq(_T_1820, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1822 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:52] + node _T_1823 = eq(_T_1822, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1824 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:52] + node _T_1825 = eq(_T_1824, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1826 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:52] + node _T_1827 = eq(_T_1826, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1828 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:52] + node _T_1829 = eq(_T_1828, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1830 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:52] + node _T_1831 = eq(_T_1830, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1832 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:52] + node _T_1833 = eq(_T_1832, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1834 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:52] + node _T_1835 = eq(_T_1834, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1836 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_1837 = eq(_T_1836, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1838 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1839 = eq(_T_1838, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1840 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_1841 = eq(_T_1840, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1842 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 67:52] + node _T_1843 = eq(_T_1842, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1844 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 67:52] + node _T_1845 = eq(_T_1844, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1846 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:52] + node _T_1847 = eq(_T_1846, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1848 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 67:52] + node _T_1849 = eq(_T_1848, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1850 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 67:52] + node _T_1851 = eq(_T_1850, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1852 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_1853 = eq(_T_1852, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1854 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_1855 = eq(_T_1854, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1856 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_1857 = eq(_T_1856, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1858 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:33] + node _T_1859 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:33] + node _T_1860 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] + node _T_1861 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] + node _T_1862 = eq(_T_1861, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1863 = and(_T_1819, _T_1821) @[el2_dec_dec_ctl.scala 165:110] + node _T_1864 = and(_T_1863, _T_1823) @[el2_dec_dec_ctl.scala 165:110] + node _T_1865 = and(_T_1864, _T_1825) @[el2_dec_dec_ctl.scala 165:110] + node _T_1866 = and(_T_1865, _T_1827) @[el2_dec_dec_ctl.scala 165:110] + node _T_1867 = and(_T_1866, _T_1829) @[el2_dec_dec_ctl.scala 165:110] + node _T_1868 = and(_T_1867, _T_1831) @[el2_dec_dec_ctl.scala 165:110] + node _T_1869 = and(_T_1868, _T_1833) @[el2_dec_dec_ctl.scala 165:110] + node _T_1870 = and(_T_1869, _T_1835) @[el2_dec_dec_ctl.scala 165:110] + node _T_1871 = and(_T_1870, _T_1837) @[el2_dec_dec_ctl.scala 165:110] + node _T_1872 = and(_T_1871, _T_1839) @[el2_dec_dec_ctl.scala 165:110] + node _T_1873 = and(_T_1872, _T_1841) @[el2_dec_dec_ctl.scala 165:110] + node _T_1874 = and(_T_1873, _T_1843) @[el2_dec_dec_ctl.scala 165:110] + node _T_1875 = and(_T_1874, _T_1845) @[el2_dec_dec_ctl.scala 165:110] + node _T_1876 = and(_T_1875, _T_1847) @[el2_dec_dec_ctl.scala 165:110] + node _T_1877 = and(_T_1876, _T_1849) @[el2_dec_dec_ctl.scala 165:110] + node _T_1878 = and(_T_1877, _T_1851) @[el2_dec_dec_ctl.scala 165:110] + node _T_1879 = and(_T_1878, _T_1853) @[el2_dec_dec_ctl.scala 165:110] + node _T_1880 = and(_T_1879, _T_1855) @[el2_dec_dec_ctl.scala 165:110] + node _T_1881 = and(_T_1880, _T_1857) @[el2_dec_dec_ctl.scala 165:110] + node _T_1882 = and(_T_1881, _T_1858) @[el2_dec_dec_ctl.scala 165:110] + node _T_1883 = and(_T_1882, _T_1859) @[el2_dec_dec_ctl.scala 165:110] + node _T_1884 = and(_T_1883, _T_1860) @[el2_dec_dec_ctl.scala 165:110] + node _T_1885 = and(_T_1884, _T_1862) @[el2_dec_dec_ctl.scala 165:110] + node _T_1886 = or(_T_1817, _T_1885) @[el2_dec_dec_ctl.scala 164:146] + node _T_1887 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1888 = eq(_T_1887, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1889 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_1890 = eq(_T_1889, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1891 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_1892 = eq(_T_1891, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1893 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_1894 = eq(_T_1893, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1895 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] + node _T_1896 = eq(_T_1895, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1897 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_1898 = eq(_T_1897, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1899 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] + node _T_1900 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] + node _T_1901 = eq(_T_1900, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1902 = and(_T_1888, _T_1890) @[el2_dec_dec_ctl.scala 166:51] + node _T_1903 = and(_T_1902, _T_1892) @[el2_dec_dec_ctl.scala 166:51] + node _T_1904 = and(_T_1903, _T_1894) @[el2_dec_dec_ctl.scala 166:51] + node _T_1905 = and(_T_1904, _T_1896) @[el2_dec_dec_ctl.scala 166:51] + node _T_1906 = and(_T_1905, _T_1898) @[el2_dec_dec_ctl.scala 166:51] + node _T_1907 = and(_T_1906, _T_1899) @[el2_dec_dec_ctl.scala 166:51] + node _T_1908 = and(_T_1907, _T_1901) @[el2_dec_dec_ctl.scala 166:51] + node _T_1909 = or(_T_1886, _T_1908) @[el2_dec_dec_ctl.scala 165:114] + node _T_1910 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1911 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_1912 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_1913 = eq(_T_1912, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1914 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:33] + node _T_1915 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:33] + node _T_1916 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] + node _T_1917 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] + node _T_1918 = eq(_T_1917, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1919 = and(_T_1910, _T_1911) @[el2_dec_dec_ctl.scala 166:95] + node _T_1920 = and(_T_1919, _T_1913) @[el2_dec_dec_ctl.scala 166:95] + node _T_1921 = and(_T_1920, _T_1914) @[el2_dec_dec_ctl.scala 166:95] + node _T_1922 = and(_T_1921, _T_1915) @[el2_dec_dec_ctl.scala 166:95] + node _T_1923 = and(_T_1922, _T_1916) @[el2_dec_dec_ctl.scala 166:95] + node _T_1924 = and(_T_1923, _T_1918) @[el2_dec_dec_ctl.scala 166:95] + node _T_1925 = or(_T_1909, _T_1924) @[el2_dec_dec_ctl.scala 166:55] + node _T_1926 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_1927 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_1928 = eq(_T_1927, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1929 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_1930 = eq(_T_1929, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1931 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1932 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] + node _T_1933 = eq(_T_1932, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1934 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] + node _T_1935 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] + node _T_1936 = eq(_T_1935, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1937 = and(_T_1926, _T_1928) @[el2_dec_dec_ctl.scala 167:46] + node _T_1938 = and(_T_1937, _T_1930) @[el2_dec_dec_ctl.scala 167:46] + node _T_1939 = and(_T_1938, _T_1931) @[el2_dec_dec_ctl.scala 167:46] + node _T_1940 = and(_T_1939, _T_1933) @[el2_dec_dec_ctl.scala 167:46] + node _T_1941 = and(_T_1940, _T_1934) @[el2_dec_dec_ctl.scala 167:46] + node _T_1942 = and(_T_1941, _T_1936) @[el2_dec_dec_ctl.scala 167:46] + node _T_1943 = or(_T_1925, _T_1942) @[el2_dec_dec_ctl.scala 166:99] + node _T_1944 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_1945 = eq(_T_1944, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1946 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_1947 = eq(_T_1946, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1948 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_1949 = eq(_T_1948, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1950 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_1951 = eq(_T_1950, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1952 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] + node _T_1953 = eq(_T_1952, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1954 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_1955 = eq(_T_1954, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1956 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] + node _T_1957 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] + node _T_1958 = eq(_T_1957, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1959 = and(_T_1945, _T_1947) @[el2_dec_dec_ctl.scala 167:99] + node _T_1960 = and(_T_1959, _T_1949) @[el2_dec_dec_ctl.scala 167:99] + node _T_1961 = and(_T_1960, _T_1951) @[el2_dec_dec_ctl.scala 167:99] + node _T_1962 = and(_T_1961, _T_1953) @[el2_dec_dec_ctl.scala 167:99] + node _T_1963 = and(_T_1962, _T_1955) @[el2_dec_dec_ctl.scala 167:99] + node _T_1964 = and(_T_1963, _T_1956) @[el2_dec_dec_ctl.scala 167:99] + node _T_1965 = and(_T_1964, _T_1958) @[el2_dec_dec_ctl.scala 167:99] + node _T_1966 = or(_T_1943, _T_1965) @[el2_dec_dec_ctl.scala 167:50] + node _T_1967 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_1968 = eq(_T_1967, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1969 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1970 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] + node _T_1971 = eq(_T_1970, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1972 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:33] + node _T_1973 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] + node _T_1974 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] + node _T_1975 = eq(_T_1974, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1976 = and(_T_1968, _T_1969) @[el2_dec_dec_ctl.scala 168:42] + node _T_1977 = and(_T_1976, _T_1971) @[el2_dec_dec_ctl.scala 168:42] + node _T_1978 = and(_T_1977, _T_1972) @[el2_dec_dec_ctl.scala 168:42] + node _T_1979 = and(_T_1978, _T_1973) @[el2_dec_dec_ctl.scala 168:42] + node _T_1980 = and(_T_1979, _T_1975) @[el2_dec_dec_ctl.scala 168:42] + node _T_1981 = or(_T_1966, _T_1980) @[el2_dec_dec_ctl.scala 167:103] + io.out.legal <= _T_1981 @[el2_dec_dec_ctl.scala 153:16] + diff --git a/el2_dec_dec_ctl.v b/el2_dec_dec_ctl.v new file mode 100644 index 00000000..715641b1 --- /dev/null +++ b/el2_dec_dec_ctl.v @@ -0,0 +1,704 @@ +module el2_dec_dec_ctl( + input clock, + input reset, + input [31:0] io_ins, + output io_out_alu, + output io_out_rs1, + output io_out_rs2, + output io_out_imm12, + output io_out_rd, + output io_out_shimm5, + output io_out_imm20, + output io_out_pc, + output io_out_load, + output io_out_store, + output io_out_lsu, + output io_out_add, + output io_out_sub, + output io_out_land, + output io_out_lor, + output io_out_lxor, + output io_out_sll, + output io_out_sra, + output io_out_srl, + output io_out_slt, + output io_out_unsign, + output io_out_condbr, + output io_out_beq, + output io_out_bne, + output io_out_bge, + output io_out_blt, + output io_out_jal, + output io_out_by, + output io_out_half, + output io_out_word, + output io_out_csr_read, + output io_out_csr_clr, + output io_out_csr_set, + output io_out_csr_write, + output io_out_csr_imm, + output io_out_presync, + output io_out_postsync, + output io_out_ebreak, + output io_out_ecall, + output io_out_mret, + output io_out_mul, + output io_out_rs1_sign, + output io_out_rs2_sign, + output io_out_low, + output io_out_div, + output io_out_rem, + output io_out_fence, + output io_out_fence_i, + output io_out_pm_alu, + output io_out_legal +); + wire _T_2 = io_ins[2] | io_ins[6]; // @[el2_dec_dec_ctl.scala 72:27] + wire _T_4 = ~io_ins[25]; // @[el2_dec_dec_ctl.scala 72:42] + wire _T_6 = _T_4 & io_ins[4]; // @[el2_dec_dec_ctl.scala 72:53] + wire _T_7 = _T_2 | _T_6; // @[el2_dec_dec_ctl.scala 72:39] + wire _T_9 = ~io_ins[5]; // @[el2_dec_dec_ctl.scala 72:68] + wire _T_11 = _T_9 & io_ins[4]; // @[el2_dec_dec_ctl.scala 72:78] + wire _T_14 = ~io_ins[14]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_16 = ~io_ins[13]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_18 = ~io_ins[2]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_19 = _T_14 & _T_16; // @[el2_dec_dec_ctl.scala 73:51] + wire _T_20 = _T_19 & _T_18; // @[el2_dec_dec_ctl.scala 73:51] + wire _T_26 = _T_16 & io_ins[11]; // @[el2_dec_dec_ctl.scala 73:90] + wire _T_27 = _T_26 & _T_18; // @[el2_dec_dec_ctl.scala 73:90] + wire _T_28 = _T_20 | _T_27; // @[el2_dec_dec_ctl.scala 73:55] + wire _T_33 = io_ins[19] & io_ins[13]; // @[el2_dec_dec_ctl.scala 74:37] + wire _T_34 = _T_33 & _T_18; // @[el2_dec_dec_ctl.scala 74:37] + wire _T_35 = _T_28 | _T_34; // @[el2_dec_dec_ctl.scala 73:94] + wire _T_41 = _T_16 & io_ins[10]; // @[el2_dec_dec_ctl.scala 74:76] + wire _T_42 = _T_41 & _T_18; // @[el2_dec_dec_ctl.scala 74:76] + wire _T_43 = _T_35 | _T_42; // @[el2_dec_dec_ctl.scala 74:41] + wire _T_45 = ~io_ins[18]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_49 = _T_45 & io_ins[13]; // @[el2_dec_dec_ctl.scala 75:38] + wire _T_50 = _T_49 & _T_18; // @[el2_dec_dec_ctl.scala 75:38] + wire _T_51 = _T_43 | _T_50; // @[el2_dec_dec_ctl.scala 74:80] + wire _T_57 = _T_16 & io_ins[9]; // @[el2_dec_dec_ctl.scala 75:76] + wire _T_58 = _T_57 & _T_18; // @[el2_dec_dec_ctl.scala 75:76] + wire _T_59 = _T_51 | _T_58; // @[el2_dec_dec_ctl.scala 75:42] + wire _T_64 = io_ins[17] & io_ins[13]; // @[el2_dec_dec_ctl.scala 76:37] + wire _T_65 = _T_64 & _T_18; // @[el2_dec_dec_ctl.scala 76:37] + wire _T_66 = _T_59 | _T_65; // @[el2_dec_dec_ctl.scala 75:80] + wire _T_72 = _T_16 & io_ins[8]; // @[el2_dec_dec_ctl.scala 76:75] + wire _T_73 = _T_72 & _T_18; // @[el2_dec_dec_ctl.scala 76:75] + wire _T_74 = _T_66 | _T_73; // @[el2_dec_dec_ctl.scala 76:41] + wire _T_79 = io_ins[16] & io_ins[13]; // @[el2_dec_dec_ctl.scala 77:37] + wire _T_80 = _T_79 & _T_18; // @[el2_dec_dec_ctl.scala 77:37] + wire _T_81 = _T_74 | _T_80; // @[el2_dec_dec_ctl.scala 76:79] + wire _T_87 = _T_16 & io_ins[7]; // @[el2_dec_dec_ctl.scala 77:75] + wire _T_88 = _T_87 & _T_18; // @[el2_dec_dec_ctl.scala 77:75] + wire _T_89 = _T_81 | _T_88; // @[el2_dec_dec_ctl.scala 77:41] + wire _T_94 = io_ins[15] & io_ins[13]; // @[el2_dec_dec_ctl.scala 78:37] + wire _T_95 = _T_94 & _T_18; // @[el2_dec_dec_ctl.scala 78:37] + wire _T_96 = _T_89 | _T_95; // @[el2_dec_dec_ctl.scala 77:79] + wire _T_98 = ~io_ins[4]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_100 = ~io_ins[3]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_101 = _T_98 & _T_100; // @[el2_dec_dec_ctl.scala 78:71] + wire _T_102 = _T_96 | _T_101; // @[el2_dec_dec_ctl.scala 78:41] + wire _T_104 = ~io_ins[6]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_107 = _T_104 & _T_18; // @[el2_dec_dec_ctl.scala 78:106] + wire _T_114 = io_ins[5] & _T_98; // @[el2_dec_dec_ctl.scala 79:48] + wire _T_115 = _T_114 & _T_18; // @[el2_dec_dec_ctl.scala 79:48] + wire _T_121 = _T_104 & io_ins[5]; // @[el2_dec_dec_ctl.scala 79:85] + wire _T_122 = _T_121 & _T_18; // @[el2_dec_dec_ctl.scala 79:85] + wire _T_130 = _T_101 & io_ins[2]; // @[el2_dec_dec_ctl.scala 80:50] + wire _T_137 = io_ins[13] & _T_9; // @[el2_dec_dec_ctl.scala 80:90] + wire _T_138 = _T_137 & io_ins[4]; // @[el2_dec_dec_ctl.scala 80:90] + wire _T_139 = _T_138 & _T_18; // @[el2_dec_dec_ctl.scala 80:90] + wire _T_140 = _T_130 | _T_139; // @[el2_dec_dec_ctl.scala 80:54] + wire _T_144 = ~io_ins[12]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_147 = _T_16 & _T_144; // @[el2_dec_dec_ctl.scala 81:40] + wire _T_148 = _T_147 & io_ins[6]; // @[el2_dec_dec_ctl.scala 81:40] + wire _T_149 = _T_148 & io_ins[4]; // @[el2_dec_dec_ctl.scala 81:40] + wire _T_150 = _T_140 | _T_149; // @[el2_dec_dec_ctl.scala 80:94] + wire _T_158 = _T_144 & _T_9; // @[el2_dec_dec_ctl.scala 81:81] + wire _T_159 = _T_158 & io_ins[4]; // @[el2_dec_dec_ctl.scala 81:81] + wire _T_160 = _T_159 & _T_18; // @[el2_dec_dec_ctl.scala 81:81] + wire _T_166 = _T_9 & _T_18; // @[el2_dec_dec_ctl.scala 82:28] + wire _T_169 = io_ins[5] & io_ins[2]; // @[el2_dec_dec_ctl.scala 82:55] + wire _T_170 = _T_166 | _T_169; // @[el2_dec_dec_ctl.scala 82:42] + wire _T_181 = _T_16 & io_ins[12]; // @[el2_dec_dec_ctl.scala 83:58] + wire _T_182 = _T_181 & _T_9; // @[el2_dec_dec_ctl.scala 83:58] + wire _T_183 = _T_182 & io_ins[4]; // @[el2_dec_dec_ctl.scala 83:58] + wire _T_187 = io_ins[5] & io_ins[3]; // @[el2_dec_dec_ctl.scala 84:29] + wire _T_190 = io_ins[4] & io_ins[2]; // @[el2_dec_dec_ctl.scala 84:53] + wire _T_196 = _T_9 & _T_100; // @[el2_dec_dec_ctl.scala 85:28] + wire _T_198 = _T_196 & io_ins[2]; // @[el2_dec_dec_ctl.scala 85:41] + wire _T_209 = _T_9 & _T_98; // @[el2_dec_dec_ctl.scala 86:50] + wire _T_224 = _T_104 & _T_98; // @[el2_dec_dec_ctl.scala 88:49] + wire _T_236 = _T_19 & _T_144; // @[el2_dec_dec_ctl.scala 89:57] + wire _T_237 = _T_236 & _T_9; // @[el2_dec_dec_ctl.scala 89:57] + wire _T_238 = _T_237 & io_ins[4]; // @[el2_dec_dec_ctl.scala 89:57] + wire _T_246 = _T_238 | _T_198; // @[el2_dec_dec_ctl.scala 89:61] + wire _T_248 = ~io_ins[30]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_262 = _T_248 & _T_4; // @[el2_dec_dec_ctl.scala 90:56] + wire _T_263 = _T_262 & _T_14; // @[el2_dec_dec_ctl.scala 90:56] + wire _T_264 = _T_263 & _T_16; // @[el2_dec_dec_ctl.scala 90:56] + wire _T_265 = _T_264 & _T_144; // @[el2_dec_dec_ctl.scala 90:56] + wire _T_266 = _T_265 & _T_104; // @[el2_dec_dec_ctl.scala 90:56] + wire _T_267 = _T_266 & io_ins[4]; // @[el2_dec_dec_ctl.scala 90:56] + wire _T_268 = _T_267 & _T_18; // @[el2_dec_dec_ctl.scala 90:56] + wire _T_279 = io_ins[30] & _T_144; // @[el2_dec_dec_ctl.scala 91:57] + wire _T_280 = _T_279 & _T_104; // @[el2_dec_dec_ctl.scala 91:57] + wire _T_281 = _T_280 & io_ins[5]; // @[el2_dec_dec_ctl.scala 91:57] + wire _T_282 = _T_281 & io_ins[4]; // @[el2_dec_dec_ctl.scala 91:57] + wire _T_283 = _T_282 & _T_18; // @[el2_dec_dec_ctl.scala 91:57] + wire _T_294 = _T_4 & _T_14; // @[el2_dec_dec_ctl.scala 91:105] + wire _T_295 = _T_294 & io_ins[13]; // @[el2_dec_dec_ctl.scala 91:105] + wire _T_296 = _T_295 & _T_104; // @[el2_dec_dec_ctl.scala 91:105] + wire _T_297 = _T_296 & io_ins[4]; // @[el2_dec_dec_ctl.scala 91:105] + wire _T_298 = _T_297 & _T_18; // @[el2_dec_dec_ctl.scala 91:105] + wire _T_299 = _T_283 | _T_298; // @[el2_dec_dec_ctl.scala 91:61] + wire _T_308 = _T_14 & io_ins[13]; // @[el2_dec_dec_ctl.scala 92:43] + wire _T_309 = _T_308 & _T_9; // @[el2_dec_dec_ctl.scala 92:43] + wire _T_310 = _T_309 & io_ins[4]; // @[el2_dec_dec_ctl.scala 92:43] + wire _T_311 = _T_310 & _T_18; // @[el2_dec_dec_ctl.scala 92:43] + wire _T_312 = _T_299 | _T_311; // @[el2_dec_dec_ctl.scala 91:109] + wire _T_318 = io_ins[6] & _T_98; // @[el2_dec_dec_ctl.scala 92:80] + wire _T_319 = _T_318 & _T_18; // @[el2_dec_dec_ctl.scala 92:80] + wire _T_328 = io_ins[14] & io_ins[13]; // @[el2_dec_dec_ctl.scala 93:56] + wire _T_329 = _T_328 & io_ins[12]; // @[el2_dec_dec_ctl.scala 93:56] + wire _T_330 = _T_329 & _T_9; // @[el2_dec_dec_ctl.scala 93:56] + wire _T_331 = _T_330 & _T_18; // @[el2_dec_dec_ctl.scala 93:56] + wire _T_341 = _T_4 & io_ins[14]; // @[el2_dec_dec_ctl.scala 93:104] + wire _T_342 = _T_341 & io_ins[13]; // @[el2_dec_dec_ctl.scala 93:104] + wire _T_343 = _T_342 & io_ins[12]; // @[el2_dec_dec_ctl.scala 93:104] + wire _T_344 = _T_343 & _T_104; // @[el2_dec_dec_ctl.scala 93:104] + wire _T_345 = _T_344 & _T_18; // @[el2_dec_dec_ctl.scala 93:104] + wire _T_350 = _T_104 & io_ins[3]; // @[el2_dec_dec_ctl.scala 94:45] + wire _T_363 = _T_342 & _T_144; // @[el2_dec_dec_ctl.scala 94:94] + wire _T_364 = _T_363 & _T_104; // @[el2_dec_dec_ctl.scala 94:94] + wire _T_365 = _T_364 & _T_18; // @[el2_dec_dec_ctl.scala 94:94] + wire _T_366 = _T_350 | _T_365; // @[el2_dec_dec_ctl.scala 94:49] + wire _T_370 = io_ins[5] & io_ins[4]; // @[el2_dec_dec_ctl.scala 95:34] + wire _T_371 = _T_370 & io_ins[2]; // @[el2_dec_dec_ctl.scala 95:34] + wire _T_372 = _T_366 | _T_371; // @[el2_dec_dec_ctl.scala 94:98] + wire _T_382 = _T_372 | _T_149; // @[el2_dec_dec_ctl.scala 95:38] + wire _T_392 = _T_328 & _T_144; // @[el2_dec_dec_ctl.scala 96:44] + wire _T_393 = _T_392 & _T_9; // @[el2_dec_dec_ctl.scala 96:44] + wire _T_394 = _T_393 & _T_18; // @[el2_dec_dec_ctl.scala 96:44] + wire _T_407 = _T_341 & _T_16; // @[el2_dec_dec_ctl.scala 97:61] + wire _T_408 = _T_407 & _T_144; // @[el2_dec_dec_ctl.scala 97:61] + wire _T_409 = _T_408 & io_ins[4]; // @[el2_dec_dec_ctl.scala 97:61] + wire _T_410 = _T_409 & _T_18; // @[el2_dec_dec_ctl.scala 97:61] + wire _T_421 = io_ins[14] & _T_16; // @[el2_dec_dec_ctl.scala 97:109] + wire _T_422 = _T_421 & _T_144; // @[el2_dec_dec_ctl.scala 97:109] + wire _T_423 = _T_422 & _T_9; // @[el2_dec_dec_ctl.scala 97:109] + wire _T_424 = _T_423 & io_ins[4]; // @[el2_dec_dec_ctl.scala 97:109] + wire _T_425 = _T_424 & _T_18; // @[el2_dec_dec_ctl.scala 97:109] + wire _T_440 = _T_294 & _T_16; // @[el2_dec_dec_ctl.scala 98:63] + wire _T_441 = _T_440 & io_ins[12]; // @[el2_dec_dec_ctl.scala 98:63] + wire _T_442 = _T_441 & _T_104; // @[el2_dec_dec_ctl.scala 98:63] + wire _T_443 = _T_442 & io_ins[4]; // @[el2_dec_dec_ctl.scala 98:63] + wire _T_454 = io_ins[30] & _T_16; // @[el2_dec_dec_ctl.scala 99:58] + wire _T_455 = _T_454 & io_ins[12]; // @[el2_dec_dec_ctl.scala 99:58] + wire _T_456 = _T_455 & _T_104; // @[el2_dec_dec_ctl.scala 99:58] + wire _T_457 = _T_456 & io_ins[4]; // @[el2_dec_dec_ctl.scala 99:58] + wire _T_473 = _T_262 & io_ins[14]; // @[el2_dec_dec_ctl.scala 100:66] + wire _T_474 = _T_473 & _T_16; // @[el2_dec_dec_ctl.scala 100:66] + wire _T_475 = _T_474 & io_ins[12]; // @[el2_dec_dec_ctl.scala 100:66] + wire _T_476 = _T_475 & _T_104; // @[el2_dec_dec_ctl.scala 100:66] + wire _T_477 = _T_476 & io_ins[4]; // @[el2_dec_dec_ctl.scala 100:66] + wire _T_492 = _T_295 & io_ins[12]; // @[el2_dec_dec_ctl.scala 101:62] + wire _T_493 = _T_492 & _T_104; // @[el2_dec_dec_ctl.scala 101:62] + wire _T_494 = _T_493 & io_ins[4]; // @[el2_dec_dec_ctl.scala 101:62] + wire _T_495 = _T_494 & _T_18; // @[el2_dec_dec_ctl.scala 101:62] + wire _T_518 = _T_308 & io_ins[12]; // @[el2_dec_dec_ctl.scala 102:59] + wire _T_519 = _T_518 & _T_9; // @[el2_dec_dec_ctl.scala 102:59] + wire _T_520 = _T_519 & _T_18; // @[el2_dec_dec_ctl.scala 102:59] + wire _T_527 = io_ins[13] & io_ins[6]; // @[el2_dec_dec_ctl.scala 102:99] + wire _T_528 = _T_527 & _T_98; // @[el2_dec_dec_ctl.scala 102:99] + wire _T_529 = _T_528 & _T_18; // @[el2_dec_dec_ctl.scala 102:99] + wire _T_530 = _T_520 | _T_529; // @[el2_dec_dec_ctl.scala 102:63] + wire _T_536 = io_ins[14] & _T_9; // @[el2_dec_dec_ctl.scala 103:37] + wire _T_537 = _T_536 & _T_98; // @[el2_dec_dec_ctl.scala 103:37] + wire _T_538 = _T_530 | _T_537; // @[el2_dec_dec_ctl.scala 102:103] + wire _T_553 = _T_493 & _T_18; // @[el2_dec_dec_ctl.scala 103:86] + wire _T_554 = _T_538 | _T_553; // @[el2_dec_dec_ctl.scala 103:41] + wire _T_563 = io_ins[25] & io_ins[14]; // @[el2_dec_dec_ctl.scala 104:45] + wire _T_564 = _T_563 & io_ins[12]; // @[el2_dec_dec_ctl.scala 104:45] + wire _T_565 = _T_564 & _T_104; // @[el2_dec_dec_ctl.scala 104:45] + wire _T_566 = _T_565 & io_ins[5]; // @[el2_dec_dec_ctl.scala 104:45] + wire _T_567 = _T_566 & _T_18; // @[el2_dec_dec_ctl.scala 104:45] + wire _T_585 = _T_14 & _T_144; // @[el2_dec_dec_ctl.scala 106:56] + wire _T_586 = _T_585 & io_ins[6]; // @[el2_dec_dec_ctl.scala 106:56] + wire _T_587 = _T_586 & _T_98; // @[el2_dec_dec_ctl.scala 106:56] + wire _T_597 = _T_14 & io_ins[12]; // @[el2_dec_dec_ctl.scala 107:55] + wire _T_598 = _T_597 & io_ins[6]; // @[el2_dec_dec_ctl.scala 107:55] + wire _T_599 = _T_598 & _T_98; // @[el2_dec_dec_ctl.scala 107:55] + wire _T_608 = io_ins[14] & io_ins[12]; // @[el2_dec_dec_ctl.scala 108:54] + wire _T_609 = _T_608 & io_ins[5]; // @[el2_dec_dec_ctl.scala 108:54] + wire _T_610 = _T_609 & _T_98; // @[el2_dec_dec_ctl.scala 108:54] + wire _T_620 = io_ins[14] & _T_144; // @[el2_dec_dec_ctl.scala 109:55] + wire _T_621 = _T_620 & io_ins[5]; // @[el2_dec_dec_ctl.scala 109:55] + wire _T_622 = _T_621 & _T_98; // @[el2_dec_dec_ctl.scala 109:55] + wire _T_638 = _T_147 & _T_104; // @[el2_dec_dec_ctl.scala 111:56] + wire _T_639 = _T_638 & _T_98; // @[el2_dec_dec_ctl.scala 111:56] + wire _T_648 = io_ins[12] & _T_104; // @[el2_dec_dec_ctl.scala 112:53] + wire _T_649 = _T_648 & _T_98; // @[el2_dec_dec_ctl.scala 112:53] + wire _T_656 = io_ins[13] & _T_104; // @[el2_dec_dec_ctl.scala 113:50] + wire _T_662 = _T_527 & io_ins[4]; // @[el2_dec_dec_ctl.scala 114:52] + wire _T_666 = io_ins[7] & io_ins[6]; // @[el2_dec_dec_ctl.scala 114:87] + wire _T_667 = _T_666 & io_ins[4]; // @[el2_dec_dec_ctl.scala 114:87] + wire _T_668 = _T_662 | _T_667; // @[el2_dec_dec_ctl.scala 114:56] + wire _T_672 = io_ins[8] & io_ins[6]; // @[el2_dec_dec_ctl.scala 115:34] + wire _T_673 = _T_672 & io_ins[4]; // @[el2_dec_dec_ctl.scala 115:34] + wire _T_674 = _T_668 | _T_673; // @[el2_dec_dec_ctl.scala 114:91] + wire _T_678 = io_ins[9] & io_ins[6]; // @[el2_dec_dec_ctl.scala 115:69] + wire _T_679 = _T_678 & io_ins[4]; // @[el2_dec_dec_ctl.scala 115:69] + wire _T_680 = _T_674 | _T_679; // @[el2_dec_dec_ctl.scala 115:38] + wire _T_684 = io_ins[10] & io_ins[6]; // @[el2_dec_dec_ctl.scala 115:105] + wire _T_685 = _T_684 & io_ins[4]; // @[el2_dec_dec_ctl.scala 115:105] + wire _T_686 = _T_680 | _T_685; // @[el2_dec_dec_ctl.scala 115:73] + wire _T_690 = io_ins[11] & io_ins[6]; // @[el2_dec_dec_ctl.scala 116:35] + wire _T_691 = _T_690 & io_ins[4]; // @[el2_dec_dec_ctl.scala 116:35] + wire _T_699 = _T_94 & io_ins[12]; // @[el2_dec_dec_ctl.scala 117:57] + wire _T_700 = _T_699 & io_ins[6]; // @[el2_dec_dec_ctl.scala 117:57] + wire _T_701 = _T_700 & io_ins[4]; // @[el2_dec_dec_ctl.scala 117:57] + wire _T_708 = _T_79 & io_ins[12]; // @[el2_dec_dec_ctl.scala 117:99] + wire _T_709 = _T_708 & io_ins[6]; // @[el2_dec_dec_ctl.scala 117:99] + wire _T_710 = _T_709 & io_ins[4]; // @[el2_dec_dec_ctl.scala 117:99] + wire _T_711 = _T_701 | _T_710; // @[el2_dec_dec_ctl.scala 117:61] + wire _T_718 = _T_64 & io_ins[12]; // @[el2_dec_dec_ctl.scala 118:41] + wire _T_719 = _T_718 & io_ins[6]; // @[el2_dec_dec_ctl.scala 118:41] + wire _T_720 = _T_719 & io_ins[4]; // @[el2_dec_dec_ctl.scala 118:41] + wire _T_721 = _T_711 | _T_720; // @[el2_dec_dec_ctl.scala 117:103] + wire _T_727 = io_ins[18] & _T_144; // @[el2_dec_dec_ctl.scala 118:81] + wire _T_728 = _T_727 & io_ins[6]; // @[el2_dec_dec_ctl.scala 118:81] + wire _T_729 = _T_728 & io_ins[4]; // @[el2_dec_dec_ctl.scala 118:81] + wire _T_730 = _T_721 | _T_729; // @[el2_dec_dec_ctl.scala 118:45] + wire _T_736 = io_ins[19] & _T_144; // @[el2_dec_dec_ctl.scala 119:39] + wire _T_737 = _T_736 & io_ins[6]; // @[el2_dec_dec_ctl.scala 119:39] + wire _T_738 = _T_737 & io_ins[4]; // @[el2_dec_dec_ctl.scala 119:39] + wire _T_746 = _T_181 & io_ins[6]; // @[el2_dec_dec_ctl.scala 120:57] + wire _T_754 = _T_421 & io_ins[6]; // @[el2_dec_dec_ctl.scala 121:55] + wire _T_755 = _T_754 & io_ins[4]; // @[el2_dec_dec_ctl.scala 121:55] + wire _T_760 = io_ins[15] & io_ins[14]; // @[el2_dec_dec_ctl.scala 121:94] + wire _T_761 = _T_760 & io_ins[6]; // @[el2_dec_dec_ctl.scala 121:94] + wire _T_762 = _T_761 & io_ins[4]; // @[el2_dec_dec_ctl.scala 121:94] + wire _T_763 = _T_755 | _T_762; // @[el2_dec_dec_ctl.scala 121:59] + wire _T_768 = io_ins[16] & io_ins[14]; // @[el2_dec_dec_ctl.scala 122:38] + wire _T_769 = _T_768 & io_ins[6]; // @[el2_dec_dec_ctl.scala 122:38] + wire _T_770 = _T_769 & io_ins[4]; // @[el2_dec_dec_ctl.scala 122:38] + wire _T_771 = _T_763 | _T_770; // @[el2_dec_dec_ctl.scala 121:98] + wire _T_776 = io_ins[17] & io_ins[14]; // @[el2_dec_dec_ctl.scala 122:77] + wire _T_777 = _T_776 & io_ins[6]; // @[el2_dec_dec_ctl.scala 122:77] + wire _T_778 = _T_777 & io_ins[4]; // @[el2_dec_dec_ctl.scala 122:77] + wire _T_779 = _T_771 | _T_778; // @[el2_dec_dec_ctl.scala 122:42] + wire _T_784 = io_ins[18] & io_ins[14]; // @[el2_dec_dec_ctl.scala 123:38] + wire _T_785 = _T_784 & io_ins[6]; // @[el2_dec_dec_ctl.scala 123:38] + wire _T_786 = _T_785 & io_ins[4]; // @[el2_dec_dec_ctl.scala 123:38] + wire _T_787 = _T_779 | _T_786; // @[el2_dec_dec_ctl.scala 122:81] + wire _T_792 = io_ins[19] & io_ins[14]; // @[el2_dec_dec_ctl.scala 123:77] + wire _T_793 = _T_792 & io_ins[6]; // @[el2_dec_dec_ctl.scala 123:77] + wire _T_794 = _T_793 & io_ins[4]; // @[el2_dec_dec_ctl.scala 123:77] + wire _T_801 = io_ins[15] & _T_144; // @[el2_dec_dec_ctl.scala 124:55] + wire _T_802 = _T_801 & io_ins[6]; // @[el2_dec_dec_ctl.scala 124:55] + wire _T_803 = _T_802 & io_ins[4]; // @[el2_dec_dec_ctl.scala 124:55] + wire _T_809 = io_ins[16] & _T_144; // @[el2_dec_dec_ctl.scala 124:95] + wire _T_810 = _T_809 & io_ins[6]; // @[el2_dec_dec_ctl.scala 124:95] + wire _T_811 = _T_810 & io_ins[4]; // @[el2_dec_dec_ctl.scala 124:95] + wire _T_812 = _T_803 | _T_811; // @[el2_dec_dec_ctl.scala 124:59] + wire _T_818 = io_ins[17] & _T_144; // @[el2_dec_dec_ctl.scala 125:39] + wire _T_819 = _T_818 & io_ins[6]; // @[el2_dec_dec_ctl.scala 125:39] + wire _T_820 = _T_819 & io_ins[4]; // @[el2_dec_dec_ctl.scala 125:39] + wire _T_821 = _T_812 | _T_820; // @[el2_dec_dec_ctl.scala 124:99] + wire _T_830 = _T_821 | _T_729; // @[el2_dec_dec_ctl.scala 125:43] + wire _T_841 = ~io_ins[22]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_849 = _T_841 & io_ins[20]; // @[el2_dec_dec_ctl.scala 127:62] + wire _T_850 = _T_849 & _T_16; // @[el2_dec_dec_ctl.scala 127:62] + wire _T_851 = _T_850 & _T_144; // @[el2_dec_dec_ctl.scala 127:62] + wire _T_852 = _T_851 & io_ins[6]; // @[el2_dec_dec_ctl.scala 127:62] + wire _T_855 = ~io_ins[21]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_857 = ~io_ins[20]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_864 = _T_855 & _T_857; // @[el2_dec_dec_ctl.scala 128:62] + wire _T_865 = _T_864 & _T_16; // @[el2_dec_dec_ctl.scala 128:62] + wire _T_866 = _T_865 & _T_144; // @[el2_dec_dec_ctl.scala 128:62] + wire _T_867 = _T_866 & io_ins[6]; // @[el2_dec_dec_ctl.scala 128:62] + wire _T_876 = io_ins[29] & _T_16; // @[el2_dec_dec_ctl.scala 129:56] + wire _T_877 = _T_876 & _T_144; // @[el2_dec_dec_ctl.scala 129:56] + wire _T_878 = _T_877 & io_ins[6]; // @[el2_dec_dec_ctl.scala 129:56] + wire _T_889 = io_ins[25] & _T_14; // @[el2_dec_dec_ctl.scala 130:57] + wire _T_890 = _T_889 & _T_104; // @[el2_dec_dec_ctl.scala 130:57] + wire _T_891 = _T_890 & io_ins[5]; // @[el2_dec_dec_ctl.scala 130:57] + wire _T_892 = _T_891 & io_ins[4]; // @[el2_dec_dec_ctl.scala 130:57] + wire _T_907 = _T_889 & io_ins[13]; // @[el2_dec_dec_ctl.scala 131:69] + wire _T_908 = _T_907 & _T_144; // @[el2_dec_dec_ctl.scala 131:69] + wire _T_909 = _T_908 & _T_104; // @[el2_dec_dec_ctl.scala 131:69] + wire _T_910 = _T_909 & io_ins[5]; // @[el2_dec_dec_ctl.scala 131:69] + wire _T_911 = _T_910 & io_ins[4]; // @[el2_dec_dec_ctl.scala 131:69] + wire _T_912 = _T_911 & _T_18; // @[el2_dec_dec_ctl.scala 131:69] + wire _T_925 = _T_889 & _T_16; // @[el2_dec_dec_ctl.scala 132:50] + wire _T_926 = _T_925 & io_ins[12]; // @[el2_dec_dec_ctl.scala 132:50] + wire _T_927 = _T_926 & _T_104; // @[el2_dec_dec_ctl.scala 132:50] + wire _T_928 = _T_927 & io_ins[4]; // @[el2_dec_dec_ctl.scala 132:50] + wire _T_929 = _T_928 & _T_18; // @[el2_dec_dec_ctl.scala 132:50] + wire _T_961 = _T_925 & _T_144; // @[el2_dec_dec_ctl.scala 134:62] + wire _T_962 = _T_961 & io_ins[5]; // @[el2_dec_dec_ctl.scala 134:62] + wire _T_963 = _T_962 & io_ins[4]; // @[el2_dec_dec_ctl.scala 134:62] + wire _T_973 = _T_563 & _T_104; // @[el2_dec_dec_ctl.scala 135:54] + wire _T_974 = _T_973 & io_ins[5]; // @[el2_dec_dec_ctl.scala 135:54] + wire _T_985 = _T_563 & io_ins[13]; // @[el2_dec_dec_ctl.scala 136:57] + wire _T_986 = _T_985 & _T_104; // @[el2_dec_dec_ctl.scala 136:57] + wire _T_987 = _T_986 & io_ins[5]; // @[el2_dec_dec_ctl.scala 136:57] + wire _T_992 = _T_9 & io_ins[3]; // @[el2_dec_dec_ctl.scala 137:47] + wire _T_997 = io_ins[12] & _T_9; // @[el2_dec_dec_ctl.scala 138:52] + wire _T_998 = _T_997 & io_ins[3]; // @[el2_dec_dec_ctl.scala 138:52] + wire _T_1006 = io_ins[28] & io_ins[22]; // @[el2_dec_dec_ctl.scala 139:59] + wire _T_1007 = _T_1006 & _T_16; // @[el2_dec_dec_ctl.scala 139:59] + wire _T_1008 = _T_1007 & _T_144; // @[el2_dec_dec_ctl.scala 139:59] + wire _T_1009 = _T_1008 & io_ins[4]; // @[el2_dec_dec_ctl.scala 139:59] + wire _T_1013 = _T_1009 | _T_190; // @[el2_dec_dec_ctl.scala 139:63] + wire _T_1019 = _T_4 & _T_104; // @[el2_dec_dec_ctl.scala 140:37] + wire _T_1020 = _T_1019 & io_ins[4]; // @[el2_dec_dec_ctl.scala 140:37] + wire _T_1021 = _T_1013 | _T_1020; // @[el2_dec_dec_ctl.scala 139:96] + wire _T_1037 = _T_87 & io_ins[6]; // @[el2_dec_dec_ctl.scala 141:88] + wire _T_1038 = _T_1037 & io_ins[4]; // @[el2_dec_dec_ctl.scala 141:88] + wire _T_1039 = _T_992 | _T_1038; // @[el2_dec_dec_ctl.scala 141:53] + wire _T_1046 = _T_72 & io_ins[6]; // @[el2_dec_dec_ctl.scala 142:38] + wire _T_1047 = _T_1046 & io_ins[4]; // @[el2_dec_dec_ctl.scala 142:38] + wire _T_1048 = _T_1039 | _T_1047; // @[el2_dec_dec_ctl.scala 141:92] + wire _T_1055 = _T_57 & io_ins[6]; // @[el2_dec_dec_ctl.scala 142:77] + wire _T_1056 = _T_1055 & io_ins[4]; // @[el2_dec_dec_ctl.scala 142:77] + wire _T_1057 = _T_1048 | _T_1056; // @[el2_dec_dec_ctl.scala 142:42] + wire _T_1066 = _T_1057 | _T_1056; // @[el2_dec_dec_ctl.scala 142:81] + wire _T_1073 = _T_41 & io_ins[6]; // @[el2_dec_dec_ctl.scala 143:78] + wire _T_1074 = _T_1073 & io_ins[4]; // @[el2_dec_dec_ctl.scala 143:78] + wire _T_1075 = _T_1066 | _T_1074; // @[el2_dec_dec_ctl.scala 143:42] + wire _T_1082 = _T_26 & io_ins[6]; // @[el2_dec_dec_ctl.scala 144:39] + wire _T_1083 = _T_1082 & io_ins[4]; // @[el2_dec_dec_ctl.scala 144:39] + wire _T_1084 = _T_1075 | _T_1083; // @[el2_dec_dec_ctl.scala 143:82] + wire _T_1090 = _T_94 & io_ins[6]; // @[el2_dec_dec_ctl.scala 144:78] + wire _T_1091 = _T_1090 & io_ins[4]; // @[el2_dec_dec_ctl.scala 144:78] + wire _T_1092 = _T_1084 | _T_1091; // @[el2_dec_dec_ctl.scala 144:43] + wire _T_1098 = _T_79 & io_ins[6]; // @[el2_dec_dec_ctl.scala 145:38] + wire _T_1099 = _T_1098 & io_ins[4]; // @[el2_dec_dec_ctl.scala 145:38] + wire _T_1100 = _T_1092 | _T_1099; // @[el2_dec_dec_ctl.scala 144:82] + wire _T_1106 = _T_64 & io_ins[6]; // @[el2_dec_dec_ctl.scala 145:77] + wire _T_1107 = _T_1106 & io_ins[4]; // @[el2_dec_dec_ctl.scala 145:77] + wire _T_1108 = _T_1100 | _T_1107; // @[el2_dec_dec_ctl.scala 145:42] + wire _T_1113 = io_ins[18] & io_ins[13]; // @[el2_dec_dec_ctl.scala 146:38] + wire _T_1114 = _T_1113 & io_ins[6]; // @[el2_dec_dec_ctl.scala 146:38] + wire _T_1115 = _T_1114 & io_ins[4]; // @[el2_dec_dec_ctl.scala 146:38] + wire _T_1116 = _T_1108 | _T_1115; // @[el2_dec_dec_ctl.scala 145:81] + wire _T_1122 = _T_33 & io_ins[6]; // @[el2_dec_dec_ctl.scala 146:77] + wire _T_1123 = _T_1122 & io_ins[4]; // @[el2_dec_dec_ctl.scala 146:77] + wire _T_1139 = _T_841 & _T_16; // @[el2_dec_dec_ctl.scala 147:98] + wire _T_1140 = _T_1139 & _T_144; // @[el2_dec_dec_ctl.scala 147:98] + wire _T_1141 = _T_1140 & io_ins[6]; // @[el2_dec_dec_ctl.scala 147:98] + wire _T_1142 = _T_1141 & io_ins[4]; // @[el2_dec_dec_ctl.scala 147:98] + wire _T_1143 = _T_998 | _T_1142; // @[el2_dec_dec_ctl.scala 147:57] + wire _T_1152 = _T_1143 | _T_1038; // @[el2_dec_dec_ctl.scala 147:102] + wire _T_1161 = _T_1152 | _T_1047; // @[el2_dec_dec_ctl.scala 148:42] + wire _T_1170 = _T_1161 | _T_1056; // @[el2_dec_dec_ctl.scala 148:81] + wire _T_1179 = _T_1170 | _T_1074; // @[el2_dec_dec_ctl.scala 149:42] + wire _T_1188 = _T_1179 | _T_1083; // @[el2_dec_dec_ctl.scala 149:82] + wire _T_1196 = _T_1188 | _T_1091; // @[el2_dec_dec_ctl.scala 150:43] + wire _T_1204 = _T_1196 | _T_1099; // @[el2_dec_dec_ctl.scala 150:82] + wire _T_1212 = _T_1204 | _T_1107; // @[el2_dec_dec_ctl.scala 151:42] + wire _T_1220 = _T_1212 | _T_1115; // @[el2_dec_dec_ctl.scala 151:81] + wire _T_1230 = ~io_ins[31]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_1236 = ~io_ins[27]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_1238 = ~io_ins[26]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_1242 = ~io_ins[24]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_1244 = ~io_ins[23]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_1251 = ~io_ins[19]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_1255 = ~io_ins[17]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_1257 = ~io_ins[16]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_1259 = ~io_ins[15]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_1263 = ~io_ins[11]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_1265 = ~io_ins[10]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_1267 = ~io_ins[9]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_1269 = ~io_ins[8]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_1271 = ~io_ins[7]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_1281 = ~io_ins[0]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_1282 = _T_1230 & _T_248; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1283 = _T_1282 & io_ins[29]; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1284 = _T_1283 & io_ins[28]; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1285 = _T_1284 & _T_1236; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1286 = _T_1285 & _T_1238; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1287 = _T_1286 & _T_4; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1288 = _T_1287 & _T_1242; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1289 = _T_1288 & _T_1244; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1290 = _T_1289 & _T_841; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1291 = _T_1290 & io_ins[21]; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1292 = _T_1291 & _T_857; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1293 = _T_1292 & _T_1251; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1294 = _T_1293 & _T_45; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1295 = _T_1294 & _T_1255; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1296 = _T_1295 & _T_1257; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1297 = _T_1296 & _T_1259; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1298 = _T_1297 & _T_14; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1299 = _T_1298 & _T_1263; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1300 = _T_1299 & _T_1265; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1301 = _T_1300 & _T_1267; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1302 = _T_1301 & _T_1269; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1303 = _T_1302 & _T_1271; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1304 = _T_1303 & io_ins[6]; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1305 = _T_1304 & io_ins[5]; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1306 = _T_1305 & io_ins[4]; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1307 = _T_1306 & _T_100; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1308 = _T_1307 & _T_18; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1309 = _T_1308 & io_ins[1]; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1310 = _T_1309 & _T_1281; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1316 = ~io_ins[29]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_1365 = _T_1282 & _T_1316; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1366 = _T_1365 & io_ins[28]; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1367 = _T_1366 & _T_1236; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1368 = _T_1367 & _T_1238; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1369 = _T_1368 & _T_4; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1370 = _T_1369 & _T_1242; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1371 = _T_1370 & _T_1244; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1372 = _T_1371 & io_ins[22]; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1373 = _T_1372 & _T_855; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1374 = _T_1373 & io_ins[20]; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1375 = _T_1374 & _T_1251; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1376 = _T_1375 & _T_45; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1377 = _T_1376 & _T_1255; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1378 = _T_1377 & _T_1257; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1379 = _T_1378 & _T_1259; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1380 = _T_1379 & _T_14; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1381 = _T_1380 & _T_1263; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1382 = _T_1381 & _T_1265; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1383 = _T_1382 & _T_1267; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1384 = _T_1383 & _T_1269; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1385 = _T_1384 & _T_1271; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1386 = _T_1385 & io_ins[6]; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1387 = _T_1386 & io_ins[5]; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1388 = _T_1387 & io_ins[4]; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1389 = _T_1388 & _T_100; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1390 = _T_1389 & _T_18; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1391 = _T_1390 & io_ins[1]; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1392 = _T_1391 & _T_1281; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1393 = _T_1310 | _T_1392; // @[el2_dec_dec_ctl.scala 153:148] + wire _T_1401 = ~io_ins[28]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_1449 = _T_1365 & _T_1401; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1450 = _T_1449 & _T_1236; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1451 = _T_1450 & _T_1238; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1452 = _T_1451 & _T_4; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1453 = _T_1452 & _T_1242; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1454 = _T_1453 & _T_1244; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1455 = _T_1454 & _T_841; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1456 = _T_1455 & _T_855; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1457 = _T_1456 & _T_1251; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1458 = _T_1457 & _T_45; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1459 = _T_1458 & _T_1255; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1460 = _T_1459 & _T_1257; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1461 = _T_1460 & _T_1259; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1462 = _T_1461 & _T_14; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1463 = _T_1462 & _T_1263; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1464 = _T_1463 & _T_1265; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1465 = _T_1464 & _T_1267; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1466 = _T_1465 & _T_1269; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1467 = _T_1466 & _T_1271; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1468 = _T_1467 & io_ins[5]; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1469 = _T_1468 & io_ins[4]; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1470 = _T_1469 & _T_100; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1471 = _T_1470 & _T_18; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1472 = _T_1471 & io_ins[1]; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1473 = _T_1472 & _T_1281; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1474 = _T_1393 | _T_1473; // @[el2_dec_dec_ctl.scala 154:134] + wire _T_1503 = _T_1452 & _T_104; // @[el2_dec_dec_ctl.scala 156:68] + wire _T_1504 = _T_1503 & io_ins[4]; // @[el2_dec_dec_ctl.scala 156:68] + wire _T_1505 = _T_1504 & _T_100; // @[el2_dec_dec_ctl.scala 156:68] + wire _T_1506 = _T_1505 & io_ins[1]; // @[el2_dec_dec_ctl.scala 156:68] + wire _T_1507 = _T_1506 & _T_1281; // @[el2_dec_dec_ctl.scala 156:68] + wire _T_1508 = _T_1474 | _T_1507; // @[el2_dec_dec_ctl.scala 155:131] + wire _T_1536 = _T_1230 & _T_1316; // @[el2_dec_dec_ctl.scala 157:77] + wire _T_1537 = _T_1536 & _T_1401; // @[el2_dec_dec_ctl.scala 157:77] + wire _T_1538 = _T_1537 & _T_1236; // @[el2_dec_dec_ctl.scala 157:77] + wire _T_1539 = _T_1538 & _T_1238; // @[el2_dec_dec_ctl.scala 157:77] + wire _T_1540 = _T_1539 & _T_4; // @[el2_dec_dec_ctl.scala 157:77] + wire _T_1541 = _T_1540 & _T_14; // @[el2_dec_dec_ctl.scala 157:77] + wire _T_1542 = _T_1541 & _T_16; // @[el2_dec_dec_ctl.scala 157:77] + wire _T_1543 = _T_1542 & _T_144; // @[el2_dec_dec_ctl.scala 157:77] + wire _T_1544 = _T_1543 & _T_104; // @[el2_dec_dec_ctl.scala 157:77] + wire _T_1545 = _T_1544 & _T_100; // @[el2_dec_dec_ctl.scala 157:77] + wire _T_1546 = _T_1545 & _T_18; // @[el2_dec_dec_ctl.scala 157:77] + wire _T_1547 = _T_1546 & io_ins[1]; // @[el2_dec_dec_ctl.scala 157:77] + wire _T_1548 = _T_1547 & _T_1281; // @[el2_dec_dec_ctl.scala 157:77] + wire _T_1549 = _T_1508 | _T_1548; // @[el2_dec_dec_ctl.scala 156:72] + wire _T_1579 = _T_1540 & io_ins[14]; // @[el2_dec_dec_ctl.scala 158:74] + wire _T_1580 = _T_1579 & _T_16; // @[el2_dec_dec_ctl.scala 158:74] + wire _T_1581 = _T_1580 & io_ins[12]; // @[el2_dec_dec_ctl.scala 158:74] + wire _T_1582 = _T_1581 & _T_104; // @[el2_dec_dec_ctl.scala 158:74] + wire _T_1583 = _T_1582 & io_ins[4]; // @[el2_dec_dec_ctl.scala 158:74] + wire _T_1584 = _T_1583 & _T_100; // @[el2_dec_dec_ctl.scala 158:74] + wire _T_1585 = _T_1584 & io_ins[1]; // @[el2_dec_dec_ctl.scala 158:74] + wire _T_1586 = _T_1585 & _T_1281; // @[el2_dec_dec_ctl.scala 158:74] + wire _T_1587 = _T_1549 | _T_1586; // @[el2_dec_dec_ctl.scala 157:81] + wire _T_1614 = _T_1451 & _T_104; // @[el2_dec_dec_ctl.scala 159:66] + wire _T_1615 = _T_1614 & io_ins[5]; // @[el2_dec_dec_ctl.scala 159:66] + wire _T_1616 = _T_1615 & io_ins[4]; // @[el2_dec_dec_ctl.scala 159:66] + wire _T_1617 = _T_1616 & _T_100; // @[el2_dec_dec_ctl.scala 159:66] + wire _T_1618 = _T_1617 & io_ins[1]; // @[el2_dec_dec_ctl.scala 159:66] + wire _T_1619 = _T_1618 & _T_1281; // @[el2_dec_dec_ctl.scala 159:66] + wire _T_1620 = _T_1587 | _T_1619; // @[el2_dec_dec_ctl.scala 158:78] + wire _T_1638 = _T_236 & io_ins[6]; // @[el2_dec_dec_ctl.scala 160:54] + wire _T_1639 = _T_1638 & io_ins[5]; // @[el2_dec_dec_ctl.scala 160:54] + wire _T_1640 = _T_1639 & _T_98; // @[el2_dec_dec_ctl.scala 160:54] + wire _T_1641 = _T_1640 & _T_100; // @[el2_dec_dec_ctl.scala 160:54] + wire _T_1642 = _T_1641 & io_ins[1]; // @[el2_dec_dec_ctl.scala 160:54] + wire _T_1643 = _T_1642 & _T_1281; // @[el2_dec_dec_ctl.scala 160:54] + wire _T_1644 = _T_1620 | _T_1643; // @[el2_dec_dec_ctl.scala 159:70] + wire _T_1657 = io_ins[14] & io_ins[6]; // @[el2_dec_dec_ctl.scala 161:48] + wire _T_1658 = _T_1657 & io_ins[5]; // @[el2_dec_dec_ctl.scala 161:48] + wire _T_1659 = _T_1658 & _T_98; // @[el2_dec_dec_ctl.scala 161:48] + wire _T_1660 = _T_1659 & _T_100; // @[el2_dec_dec_ctl.scala 161:48] + wire _T_1661 = _T_1660 & _T_18; // @[el2_dec_dec_ctl.scala 161:48] + wire _T_1662 = _T_1661 & io_ins[1]; // @[el2_dec_dec_ctl.scala 161:48] + wire _T_1663 = _T_1662 & _T_1281; // @[el2_dec_dec_ctl.scala 161:48] + wire _T_1664 = _T_1644 | _T_1663; // @[el2_dec_dec_ctl.scala 160:58] + wire _T_1677 = _T_144 & _T_104; // @[el2_dec_dec_ctl.scala 162:47] + wire _T_1678 = _T_1677 & _T_9; // @[el2_dec_dec_ctl.scala 162:47] + wire _T_1679 = _T_1678 & io_ins[4]; // @[el2_dec_dec_ctl.scala 162:47] + wire _T_1680 = _T_1679 & _T_100; // @[el2_dec_dec_ctl.scala 162:47] + wire _T_1681 = _T_1680 & io_ins[1]; // @[el2_dec_dec_ctl.scala 162:47] + wire _T_1682 = _T_1681 & _T_1281; // @[el2_dec_dec_ctl.scala 162:47] + wire _T_1683 = _T_1664 | _T_1682; // @[el2_dec_dec_ctl.scala 161:52] + wire _T_1699 = _T_19 & io_ins[5]; // @[el2_dec_dec_ctl.scala 162:99] + wire _T_1700 = _T_1699 & _T_98; // @[el2_dec_dec_ctl.scala 162:99] + wire _T_1701 = _T_1700 & _T_100; // @[el2_dec_dec_ctl.scala 162:99] + wire _T_1702 = _T_1701 & _T_18; // @[el2_dec_dec_ctl.scala 162:99] + wire _T_1703 = _T_1702 & io_ins[1]; // @[el2_dec_dec_ctl.scala 162:99] + wire _T_1704 = _T_1703 & _T_1281; // @[el2_dec_dec_ctl.scala 162:99] + wire _T_1705 = _T_1683 | _T_1704; // @[el2_dec_dec_ctl.scala 162:51] + wire _T_1717 = io_ins[12] & io_ins[6]; // @[el2_dec_dec_ctl.scala 163:47] + wire _T_1718 = _T_1717 & io_ins[5]; // @[el2_dec_dec_ctl.scala 163:47] + wire _T_1719 = _T_1718 & io_ins[4]; // @[el2_dec_dec_ctl.scala 163:47] + wire _T_1720 = _T_1719 & _T_100; // @[el2_dec_dec_ctl.scala 163:47] + wire _T_1721 = _T_1720 & _T_18; // @[el2_dec_dec_ctl.scala 163:47] + wire _T_1722 = _T_1721 & io_ins[1]; // @[el2_dec_dec_ctl.scala 163:47] + wire _T_1723 = _T_1722 & _T_1281; // @[el2_dec_dec_ctl.scala 163:47] + wire _T_1724 = _T_1705 | _T_1723; // @[el2_dec_dec_ctl.scala 162:103] + wire _T_1796 = _T_1456 & _T_857; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1797 = _T_1796 & _T_1251; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1798 = _T_1797 & _T_45; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1799 = _T_1798 & _T_1255; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1800 = _T_1799 & _T_1257; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1801 = _T_1800 & _T_1259; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1802 = _T_1801 & _T_14; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1803 = _T_1802 & _T_16; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1804 = _T_1803 & _T_144; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1805 = _T_1804 & _T_1263; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1806 = _T_1805 & _T_1265; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1807 = _T_1806 & _T_1267; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1808 = _T_1807 & _T_1269; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1809 = _T_1808 & _T_1271; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1810 = _T_1809 & _T_104; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1811 = _T_1810 & _T_9; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1812 = _T_1811 & _T_98; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1813 = _T_1812 & io_ins[3]; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1814 = _T_1813 & io_ins[2]; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1815 = _T_1814 & io_ins[1]; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1816 = _T_1815 & _T_1281; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1817 = _T_1724 | _T_1816; // @[el2_dec_dec_ctl.scala 163:51] + wire _T_1866 = _T_1449 & _T_1251; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1867 = _T_1866 & _T_45; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1868 = _T_1867 & _T_1255; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1869 = _T_1868 & _T_1257; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1870 = _T_1869 & _T_1259; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1871 = _T_1870 & _T_14; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1872 = _T_1871 & _T_16; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1873 = _T_1872 & _T_144; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1874 = _T_1873 & _T_1263; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1875 = _T_1874 & _T_1265; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1876 = _T_1875 & _T_1267; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1877 = _T_1876 & _T_1269; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1878 = _T_1877 & _T_1271; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1879 = _T_1878 & _T_104; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1880 = _T_1879 & _T_9; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1881 = _T_1880 & _T_98; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1882 = _T_1881 & io_ins[3]; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1883 = _T_1882 & io_ins[2]; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1884 = _T_1883 & io_ins[1]; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1885 = _T_1884 & _T_1281; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1886 = _T_1817 | _T_1885; // @[el2_dec_dec_ctl.scala 164:146] + wire _T_1902 = _T_16 & _T_104; // @[el2_dec_dec_ctl.scala 166:51] + wire _T_1903 = _T_1902 & _T_9; // @[el2_dec_dec_ctl.scala 166:51] + wire _T_1904 = _T_1903 & _T_98; // @[el2_dec_dec_ctl.scala 166:51] + wire _T_1905 = _T_1904 & _T_100; // @[el2_dec_dec_ctl.scala 166:51] + wire _T_1906 = _T_1905 & _T_18; // @[el2_dec_dec_ctl.scala 166:51] + wire _T_1907 = _T_1906 & io_ins[1]; // @[el2_dec_dec_ctl.scala 166:51] + wire _T_1908 = _T_1907 & _T_1281; // @[el2_dec_dec_ctl.scala 166:51] + wire _T_1909 = _T_1886 | _T_1908; // @[el2_dec_dec_ctl.scala 165:114] + wire _T_1919 = io_ins[6] & io_ins[5]; // @[el2_dec_dec_ctl.scala 166:95] + wire _T_1920 = _T_1919 & _T_98; // @[el2_dec_dec_ctl.scala 166:95] + wire _T_1921 = _T_1920 & io_ins[3]; // @[el2_dec_dec_ctl.scala 166:95] + wire _T_1922 = _T_1921 & io_ins[2]; // @[el2_dec_dec_ctl.scala 166:95] + wire _T_1923 = _T_1922 & io_ins[1]; // @[el2_dec_dec_ctl.scala 166:95] + wire _T_1924 = _T_1923 & _T_1281; // @[el2_dec_dec_ctl.scala 166:95] + wire _T_1925 = _T_1909 | _T_1924; // @[el2_dec_dec_ctl.scala 166:55] + wire _T_1938 = _T_656 & _T_9; // @[el2_dec_dec_ctl.scala 167:46] + wire _T_1939 = _T_1938 & io_ins[4]; // @[el2_dec_dec_ctl.scala 167:46] + wire _T_1940 = _T_1939 & _T_100; // @[el2_dec_dec_ctl.scala 167:46] + wire _T_1941 = _T_1940 & io_ins[1]; // @[el2_dec_dec_ctl.scala 167:46] + wire _T_1942 = _T_1941 & _T_1281; // @[el2_dec_dec_ctl.scala 167:46] + wire _T_1943 = _T_1925 | _T_1942; // @[el2_dec_dec_ctl.scala 166:99] + wire _T_1960 = _T_585 & _T_104; // @[el2_dec_dec_ctl.scala 167:99] + wire _T_1961 = _T_1960 & _T_98; // @[el2_dec_dec_ctl.scala 167:99] + wire _T_1962 = _T_1961 & _T_100; // @[el2_dec_dec_ctl.scala 167:99] + wire _T_1963 = _T_1962 & _T_18; // @[el2_dec_dec_ctl.scala 167:99] + wire _T_1964 = _T_1963 & io_ins[1]; // @[el2_dec_dec_ctl.scala 167:99] + wire _T_1965 = _T_1964 & _T_1281; // @[el2_dec_dec_ctl.scala 167:99] + wire _T_1966 = _T_1943 | _T_1965; // @[el2_dec_dec_ctl.scala 167:50] + wire _T_1976 = _T_104 & io_ins[4]; // @[el2_dec_dec_ctl.scala 168:42] + wire _T_1977 = _T_1976 & _T_100; // @[el2_dec_dec_ctl.scala 168:42] + wire _T_1978 = _T_1977 & io_ins[2]; // @[el2_dec_dec_ctl.scala 168:42] + wire _T_1979 = _T_1978 & io_ins[1]; // @[el2_dec_dec_ctl.scala 168:42] + wire _T_1980 = _T_1979 & _T_1281; // @[el2_dec_dec_ctl.scala 168:42] + assign io_out_alu = _T_7 | _T_11; // @[el2_dec_dec_ctl.scala 72:14] + assign io_out_rs1 = _T_102 | _T_107; // @[el2_dec_dec_ctl.scala 73:14] + assign io_out_rs2 = _T_115 | _T_122; // @[el2_dec_dec_ctl.scala 79:14] + assign io_out_imm12 = _T_150 | _T_160; // @[el2_dec_dec_ctl.scala 80:16] + assign io_out_rd = _T_170 | io_ins[4]; // @[el2_dec_dec_ctl.scala 82:13] + assign io_out_shimm5 = _T_183 & _T_18; // @[el2_dec_dec_ctl.scala 83:17] + assign io_out_imm20 = _T_187 | _T_190; // @[el2_dec_dec_ctl.scala 84:16] + assign io_out_pc = _T_198 | _T_187; // @[el2_dec_dec_ctl.scala 85:13] + assign io_out_load = _T_209 & _T_18; // @[el2_dec_dec_ctl.scala 86:15] + assign io_out_store = _T_121 & _T_98; // @[el2_dec_dec_ctl.scala 87:16] + assign io_out_lsu = _T_224 & _T_18; // @[el2_dec_dec_ctl.scala 88:14] + assign io_out_add = _T_246 | _T_268; // @[el2_dec_dec_ctl.scala 89:14] + assign io_out_sub = _T_312 | _T_319; // @[el2_dec_dec_ctl.scala 91:14] + assign io_out_land = _T_331 | _T_345; // @[el2_dec_dec_ctl.scala 93:15] + assign io_out_lor = _T_382 | _T_394; // @[el2_dec_dec_ctl.scala 94:14] + assign io_out_lxor = _T_410 | _T_425; // @[el2_dec_dec_ctl.scala 97:15] + assign io_out_sll = _T_443 & _T_18; // @[el2_dec_dec_ctl.scala 98:14] + assign io_out_sra = _T_457 & _T_18; // @[el2_dec_dec_ctl.scala 99:14] + assign io_out_srl = _T_477 & _T_18; // @[el2_dec_dec_ctl.scala 100:14] + assign io_out_slt = _T_495 | _T_311; // @[el2_dec_dec_ctl.scala 101:14] + assign io_out_unsign = _T_554 | _T_567; // @[el2_dec_dec_ctl.scala 102:17] + assign io_out_condbr = _T_318 & _T_18; // @[el2_dec_dec_ctl.scala 105:17] + assign io_out_beq = _T_587 & _T_18; // @[el2_dec_dec_ctl.scala 106:14] + assign io_out_bne = _T_599 & _T_18; // @[el2_dec_dec_ctl.scala 107:14] + assign io_out_bge = _T_610 & _T_18; // @[el2_dec_dec_ctl.scala 108:14] + assign io_out_blt = _T_622 & _T_18; // @[el2_dec_dec_ctl.scala 109:14] + assign io_out_jal = io_ins[6] & io_ins[2]; // @[el2_dec_dec_ctl.scala 110:14] + assign io_out_by = _T_639 & _T_18; // @[el2_dec_dec_ctl.scala 111:13] + assign io_out_half = _T_649 & _T_18; // @[el2_dec_dec_ctl.scala 112:15] + assign io_out_word = _T_656 & _T_98; // @[el2_dec_dec_ctl.scala 113:15] + assign io_out_csr_read = _T_686 | _T_691; // @[el2_dec_dec_ctl.scala 114:19] + assign io_out_csr_clr = _T_730 | _T_738; // @[el2_dec_dec_ctl.scala 117:18] + assign io_out_csr_set = _T_830 | _T_738; // @[el2_dec_dec_ctl.scala 124:18] + assign io_out_csr_write = _T_746 & io_ins[4]; // @[el2_dec_dec_ctl.scala 120:20] + assign io_out_csr_imm = _T_787 | _T_794; // @[el2_dec_dec_ctl.scala 121:18] + assign io_out_presync = _T_1116 | _T_1123; // @[el2_dec_dec_ctl.scala 141:18] + assign io_out_postsync = _T_1220 | _T_1123; // @[el2_dec_dec_ctl.scala 147:19] + assign io_out_ebreak = _T_852 & io_ins[4]; // @[el2_dec_dec_ctl.scala 127:17] + assign io_out_ecall = _T_867 & io_ins[4]; // @[el2_dec_dec_ctl.scala 128:16] + assign io_out_mret = _T_878 & io_ins[4]; // @[el2_dec_dec_ctl.scala 129:15] + assign io_out_mul = _T_892 & _T_18; // @[el2_dec_dec_ctl.scala 130:14] + assign io_out_rs1_sign = _T_912 | _T_929; // @[el2_dec_dec_ctl.scala 131:19] + assign io_out_rs2_sign = _T_928 & _T_18; // @[el2_dec_dec_ctl.scala 133:19] + assign io_out_low = _T_963 & _T_18; // @[el2_dec_dec_ctl.scala 134:14] + assign io_out_div = _T_974 & _T_18; // @[el2_dec_dec_ctl.scala 135:14] + assign io_out_rem = _T_987 & _T_18; // @[el2_dec_dec_ctl.scala 136:14] + assign io_out_fence = _T_9 & io_ins[3]; // @[el2_dec_dec_ctl.scala 137:16] + assign io_out_fence_i = _T_997 & io_ins[3]; // @[el2_dec_dec_ctl.scala 138:18] + assign io_out_pm_alu = _T_1021 | _T_11; // @[el2_dec_dec_ctl.scala 139:17] + assign io_out_legal = _T_1966 | _T_1980; // @[el2_dec_dec_ctl.scala 153:16] +endmodule diff --git a/el2_ifu_compress_ctl.anno.json b/el2_ifu_compress_ctl.anno.json new file mode 100644 index 00000000..1e620c0b --- /dev/null +++ b/el2_ifu_compress_ctl.anno.json @@ -0,0 +1,25 @@ +[ + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_ifu_compress_ctl|el2_ifu_compress_ctl>io_out", + "sources":[ + "~el2_ifu_compress_ctl|el2_ifu_compress_ctl>io_in" + ] + }, + { + "class":"firrtl.EmitCircuitAnnotation", + "emitter":"firrtl.VerilogEmitter" + }, + { + "class":"firrtl.options.TargetDirAnnotation", + "directory":"." + }, + { + "class":"firrtl.options.OutputAnnotationFileAnnotation", + "file":"el2_ifu_compress_ctl" + }, + { + "class":"firrtl.transforms.BlackBoxTargetDirAnno", + "targetDir":"." + } +] \ No newline at end of file diff --git a/el2_ifu_compress_ctl.fir b/el2_ifu_compress_ctl.fir new file mode 100644 index 00000000..3bdc64e0 --- /dev/null +++ b/el2_ifu_compress_ctl.fir @@ -0,0 +1,1057 @@ +;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10 +circuit el2_ifu_compress_ctl : + module el2_ifu_compress_ctl : + input clock : Clock + input reset : UInt<1> + output io : {flip in : UInt<16>, out : UInt} + + node rs2d = bits(io.in, 6, 2) @[el2_ifu_compress_ctl.scala 14:19] + node rdd = bits(io.in, 11, 7) @[el2_ifu_compress_ctl.scala 15:18] + node _T = bits(io.in, 9, 7) @[el2_ifu_compress_ctl.scala 16:32] + node rdpd = cat(UInt<1>("h01"), _T) @[Cat.scala 29:58] + node _T_1 = bits(io.in, 4, 2) @[el2_ifu_compress_ctl.scala 17:33] + node rs2pd = cat(UInt<1>("h01"), _T_1) @[Cat.scala 29:58] + node _T_2 = bits(io.in, 15, 15) @[el2_ifu_compress_ctl.scala 18:28] + node _T_3 = bits(io.in, 14, 14) @[el2_ifu_compress_ctl.scala 18:40] + node _T_4 = eq(_T_3, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 18:34] + node _T_5 = and(_T_2, _T_4) @[el2_ifu_compress_ctl.scala 18:32] + node _T_6 = bits(io.in, 13, 13) @[el2_ifu_compress_ctl.scala 18:53] + node _T_7 = eq(_T_6, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 18:47] + node _T_8 = and(_T_5, _T_7) @[el2_ifu_compress_ctl.scala 18:45] + node _T_9 = bits(io.in, 10, 10) @[el2_ifu_compress_ctl.scala 18:64] + node _T_10 = and(_T_8, _T_9) @[el2_ifu_compress_ctl.scala 18:58] + node _T_11 = bits(io.in, 6, 6) @[el2_ifu_compress_ctl.scala 18:76] + node _T_12 = eq(_T_11, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 18:70] + node _T_13 = and(_T_10, _T_12) @[el2_ifu_compress_ctl.scala 18:68] + node _T_14 = bits(io.in, 5, 5) @[el2_ifu_compress_ctl.scala 18:88] + node _T_15 = eq(_T_14, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 18:82] + node _T_16 = and(_T_13, _T_15) @[el2_ifu_compress_ctl.scala 18:80] + node _T_17 = bits(io.in, 0, 0) @[el2_ifu_compress_ctl.scala 18:98] + node _T_18 = and(_T_16, _T_17) @[el2_ifu_compress_ctl.scala 18:92] + node _T_19 = bits(io.in, 14, 14) @[el2_ifu_compress_ctl.scala 19:23] + node _T_20 = bits(io.in, 14, 14) @[el2_ifu_compress_ctl.scala 19:35] + node _T_21 = eq(_T_20, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 19:29] + node _T_22 = and(_T_19, _T_21) @[el2_ifu_compress_ctl.scala 19:27] + node _T_23 = bits(io.in, 13, 13) @[el2_ifu_compress_ctl.scala 19:48] + node _T_24 = eq(_T_23, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 19:42] + node _T_25 = and(_T_22, _T_24) @[el2_ifu_compress_ctl.scala 19:40] + node _T_26 = bits(io.in, 11, 11) @[el2_ifu_compress_ctl.scala 19:61] + node _T_27 = eq(_T_26, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 19:55] + node _T_28 = and(_T_25, _T_27) @[el2_ifu_compress_ctl.scala 19:53] + node _T_29 = bits(io.in, 10, 10) @[el2_ifu_compress_ctl.scala 19:72] + node _T_30 = and(_T_28, _T_29) @[el2_ifu_compress_ctl.scala 19:66] + node _T_31 = bits(io.in, 0, 0) @[el2_ifu_compress_ctl.scala 19:82] + node _T_32 = and(_T_30, _T_31) @[el2_ifu_compress_ctl.scala 19:76] + node _T_33 = or(_T_18, _T_32) @[el2_ifu_compress_ctl.scala 19:15] + node _T_34 = mux(UInt<1>("h00"), UInt<9>("h01ff"), UInt<9>("h00")) @[Bitwise.scala 72:12] + node _T_35 = bits(io.in, 14, 14) @[el2_ifu_compress_ctl.scala 20:21] + node _T_36 = eq(_T_35, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 20:15] + node _T_37 = bits(io.in, 12, 12) @[el2_ifu_compress_ctl.scala 20:31] + node _T_38 = and(_T_36, _T_37) @[el2_ifu_compress_ctl.scala 20:25] + node _T_39 = bits(io.in, 11, 11) @[el2_ifu_compress_ctl.scala 20:43] + node _T_40 = eq(_T_39, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 20:37] + node _T_41 = and(_T_38, _T_40) @[el2_ifu_compress_ctl.scala 20:35] + node _T_42 = bits(io.in, 10, 10) @[el2_ifu_compress_ctl.scala 20:56] + node _T_43 = eq(_T_42, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 20:50] + node _T_44 = and(_T_41, _T_43) @[el2_ifu_compress_ctl.scala 20:48] + node _T_45 = bits(io.in, 9, 9) @[el2_ifu_compress_ctl.scala 20:69] + node _T_46 = eq(_T_45, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 20:63] + node _T_47 = and(_T_44, _T_46) @[el2_ifu_compress_ctl.scala 20:61] + node _T_48 = bits(io.in, 8, 8) @[el2_ifu_compress_ctl.scala 20:81] + node _T_49 = eq(_T_48, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 20:75] + node _T_50 = and(_T_47, _T_49) @[el2_ifu_compress_ctl.scala 20:73] + node _T_51 = bits(io.in, 7, 7) @[el2_ifu_compress_ctl.scala 20:93] + node _T_52 = eq(_T_51, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 20:87] + node _T_53 = and(_T_50, _T_52) @[el2_ifu_compress_ctl.scala 20:85] + node _T_54 = bits(io.in, 6, 6) @[el2_ifu_compress_ctl.scala 20:105] + node _T_55 = eq(_T_54, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 20:99] + node _T_56 = and(_T_53, _T_55) @[el2_ifu_compress_ctl.scala 20:97] + node _T_57 = bits(io.in, 5, 5) @[el2_ifu_compress_ctl.scala 20:117] + node _T_58 = eq(_T_57, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 20:111] + node _T_59 = and(_T_56, _T_58) @[el2_ifu_compress_ctl.scala 20:109] + node _T_60 = bits(io.in, 4, 4) @[el2_ifu_compress_ctl.scala 21:22] + node _T_61 = eq(_T_60, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 21:16] + node _T_62 = and(_T_59, _T_61) @[el2_ifu_compress_ctl.scala 20:121] + node _T_63 = bits(io.in, 3, 3) @[el2_ifu_compress_ctl.scala 21:34] + node _T_64 = eq(_T_63, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 21:28] + node _T_65 = and(_T_62, _T_64) @[el2_ifu_compress_ctl.scala 21:26] + node _T_66 = bits(io.in, 2, 2) @[el2_ifu_compress_ctl.scala 21:46] + node _T_67 = eq(_T_66, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 21:40] + node _T_68 = and(_T_65, _T_67) @[el2_ifu_compress_ctl.scala 21:38] + node _T_69 = bits(io.in, 1, 1) @[el2_ifu_compress_ctl.scala 21:56] + node _T_70 = and(_T_68, _T_69) @[el2_ifu_compress_ctl.scala 21:50] + node _T_71 = mux(UInt<1>("h00"), UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] + node _T_72 = bits(io.in, 15, 15) @[el2_ifu_compress_ctl.scala 22:20] + node _T_73 = bits(io.in, 14, 14) @[el2_ifu_compress_ctl.scala 22:32] + node _T_74 = eq(_T_73, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 22:26] + node _T_75 = and(_T_72, _T_74) @[el2_ifu_compress_ctl.scala 22:24] + node _T_76 = bits(io.in, 13, 13) @[el2_ifu_compress_ctl.scala 22:45] + node _T_77 = eq(_T_76, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 22:39] + node _T_78 = and(_T_75, _T_77) @[el2_ifu_compress_ctl.scala 22:37] + node _T_79 = bits(io.in, 11, 11) @[el2_ifu_compress_ctl.scala 22:58] + node _T_80 = eq(_T_79, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 22:52] + node _T_81 = and(_T_78, _T_80) @[el2_ifu_compress_ctl.scala 22:50] + node _T_82 = bits(io.in, 0, 0) @[el2_ifu_compress_ctl.scala 22:69] + node _T_83 = and(_T_81, _T_82) @[el2_ifu_compress_ctl.scala 22:63] + node _T_84 = bits(io.in, 15, 15) @[el2_ifu_compress_ctl.scala 23:21] + node _T_85 = bits(io.in, 14, 14) @[el2_ifu_compress_ctl.scala 23:33] + node _T_86 = eq(_T_85, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 23:27] + node _T_87 = and(_T_84, _T_86) @[el2_ifu_compress_ctl.scala 23:25] + node _T_88 = bits(io.in, 13, 13) @[el2_ifu_compress_ctl.scala 23:46] + node _T_89 = eq(_T_88, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 23:40] + node _T_90 = and(_T_87, _T_89) @[el2_ifu_compress_ctl.scala 23:38] + node _T_91 = bits(io.in, 10, 10) @[el2_ifu_compress_ctl.scala 23:59] + node _T_92 = eq(_T_91, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 23:53] + node _T_93 = and(_T_90, _T_92) @[el2_ifu_compress_ctl.scala 23:51] + node _T_94 = bits(io.in, 0, 0) @[el2_ifu_compress_ctl.scala 23:70] + node _T_95 = and(_T_93, _T_94) @[el2_ifu_compress_ctl.scala 23:64] + node _T_96 = or(_T_83, _T_95) @[el2_ifu_compress_ctl.scala 23:15] + node _T_97 = bits(io.in, 15, 15) @[el2_ifu_compress_ctl.scala 24:21] + node _T_98 = bits(io.in, 14, 14) @[el2_ifu_compress_ctl.scala 24:33] + node _T_99 = eq(_T_98, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 24:27] + node _T_100 = and(_T_97, _T_99) @[el2_ifu_compress_ctl.scala 24:25] + node _T_101 = bits(io.in, 13, 13) @[el2_ifu_compress_ctl.scala 24:46] + node _T_102 = eq(_T_101, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 24:40] + node _T_103 = and(_T_100, _T_102) @[el2_ifu_compress_ctl.scala 24:38] + node _T_104 = bits(io.in, 6, 6) @[el2_ifu_compress_ctl.scala 24:57] + node _T_105 = and(_T_103, _T_104) @[el2_ifu_compress_ctl.scala 24:51] + node _T_106 = bits(io.in, 0, 0) @[el2_ifu_compress_ctl.scala 24:66] + node _T_107 = and(_T_105, _T_106) @[el2_ifu_compress_ctl.scala 24:60] + node _T_108 = or(_T_96, _T_107) @[el2_ifu_compress_ctl.scala 24:15] + node _T_109 = bits(io.in, 15, 15) @[el2_ifu_compress_ctl.scala 25:21] + node _T_110 = bits(io.in, 14, 14) @[el2_ifu_compress_ctl.scala 25:33] + node _T_111 = eq(_T_110, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 25:27] + node _T_112 = and(_T_109, _T_111) @[el2_ifu_compress_ctl.scala 25:25] + node _T_113 = bits(io.in, 13, 13) @[el2_ifu_compress_ctl.scala 25:46] + node _T_114 = eq(_T_113, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 25:40] + node _T_115 = and(_T_112, _T_114) @[el2_ifu_compress_ctl.scala 25:38] + node _T_116 = bits(io.in, 5, 5) @[el2_ifu_compress_ctl.scala 25:57] + node _T_117 = and(_T_115, _T_116) @[el2_ifu_compress_ctl.scala 25:51] + node _T_118 = bits(io.in, 0, 0) @[el2_ifu_compress_ctl.scala 25:66] + node _T_119 = and(_T_117, _T_118) @[el2_ifu_compress_ctl.scala 25:60] + node _T_120 = or(_T_108, _T_119) @[el2_ifu_compress_ctl.scala 25:15] + node _T_121 = bits(io.in, 15, 15) @[el2_ifu_compress_ctl.scala 26:20] + node _T_122 = bits(io.in, 14, 14) @[el2_ifu_compress_ctl.scala 26:32] + node _T_123 = eq(_T_122, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 26:26] + node _T_124 = and(_T_121, _T_123) @[el2_ifu_compress_ctl.scala 26:24] + node _T_125 = bits(io.in, 13, 13) @[el2_ifu_compress_ctl.scala 26:45] + node _T_126 = eq(_T_125, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 26:39] + node _T_127 = and(_T_124, _T_126) @[el2_ifu_compress_ctl.scala 26:37] + node _T_128 = bits(io.in, 6, 6) @[el2_ifu_compress_ctl.scala 26:56] + node _T_129 = and(_T_127, _T_128) @[el2_ifu_compress_ctl.scala 26:50] + node _T_130 = bits(io.in, 5, 5) @[el2_ifu_compress_ctl.scala 26:65] + node _T_131 = and(_T_129, _T_130) @[el2_ifu_compress_ctl.scala 26:59] + node _T_132 = bits(io.in, 0, 0) @[el2_ifu_compress_ctl.scala 26:74] + node _T_133 = and(_T_131, _T_132) @[el2_ifu_compress_ctl.scala 26:68] + node _T_134 = bits(io.in, 15, 15) @[el2_ifu_compress_ctl.scala 27:21] + node _T_135 = bits(io.in, 14, 14) @[el2_ifu_compress_ctl.scala 27:33] + node _T_136 = eq(_T_135, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 27:27] + node _T_137 = and(_T_134, _T_136) @[el2_ifu_compress_ctl.scala 27:25] + node _T_138 = bits(io.in, 13, 13) @[el2_ifu_compress_ctl.scala 27:46] + node _T_139 = eq(_T_138, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 27:40] + node _T_140 = and(_T_137, _T_139) @[el2_ifu_compress_ctl.scala 27:38] + node _T_141 = bits(io.in, 11, 11) @[el2_ifu_compress_ctl.scala 27:59] + node _T_142 = eq(_T_141, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 27:53] + node _T_143 = and(_T_140, _T_142) @[el2_ifu_compress_ctl.scala 27:51] + node _T_144 = bits(io.in, 0, 0) @[el2_ifu_compress_ctl.scala 27:70] + node _T_145 = and(_T_143, _T_144) @[el2_ifu_compress_ctl.scala 27:64] + node _T_146 = or(_T_133, _T_145) @[el2_ifu_compress_ctl.scala 27:15] + node _T_147 = bits(io.in, 15, 15) @[el2_ifu_compress_ctl.scala 28:21] + node _T_148 = bits(io.in, 14, 14) @[el2_ifu_compress_ctl.scala 28:33] + node _T_149 = eq(_T_148, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 28:27] + node _T_150 = and(_T_147, _T_149) @[el2_ifu_compress_ctl.scala 28:25] + node _T_151 = bits(io.in, 13, 13) @[el2_ifu_compress_ctl.scala 28:46] + node _T_152 = eq(_T_151, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 28:40] + node _T_153 = and(_T_150, _T_152) @[el2_ifu_compress_ctl.scala 28:38] + node _T_154 = bits(io.in, 10, 10) @[el2_ifu_compress_ctl.scala 28:59] + node _T_155 = eq(_T_154, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 28:53] + node _T_156 = and(_T_153, _T_155) @[el2_ifu_compress_ctl.scala 28:51] + node _T_157 = bits(io.in, 0, 0) @[el2_ifu_compress_ctl.scala 28:70] + node _T_158 = and(_T_156, _T_157) @[el2_ifu_compress_ctl.scala 28:64] + node _T_159 = or(_T_146, _T_158) @[el2_ifu_compress_ctl.scala 28:15] + node _T_160 = bits(io.in, 15, 15) @[el2_ifu_compress_ctl.scala 29:23] + node _T_161 = eq(_T_160, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 29:17] + node _T_162 = bits(io.in, 14, 14) @[el2_ifu_compress_ctl.scala 29:36] + node _T_163 = eq(_T_162, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 29:30] + node _T_164 = and(_T_161, _T_163) @[el2_ifu_compress_ctl.scala 29:28] + node _T_165 = bits(io.in, 1, 1) @[el2_ifu_compress_ctl.scala 29:47] + node _T_166 = and(_T_164, _T_165) @[el2_ifu_compress_ctl.scala 29:41] + node _T_167 = or(_T_159, _T_166) @[el2_ifu_compress_ctl.scala 29:15] + node _T_168 = bits(io.in, 15, 15) @[el2_ifu_compress_ctl.scala 29:58] + node _T_169 = bits(io.in, 14, 14) @[el2_ifu_compress_ctl.scala 29:68] + node _T_170 = and(_T_168, _T_169) @[el2_ifu_compress_ctl.scala 29:62] + node _T_171 = bits(io.in, 13, 13) @[el2_ifu_compress_ctl.scala 29:78] + node _T_172 = and(_T_170, _T_171) @[el2_ifu_compress_ctl.scala 29:72] + node _T_173 = or(_T_167, _T_172) @[el2_ifu_compress_ctl.scala 29:51] + node _T_174 = bits(io.in, 15, 15) @[el2_ifu_compress_ctl.scala 30:20] + node _T_175 = bits(io.in, 14, 14) @[el2_ifu_compress_ctl.scala 30:32] + node _T_176 = eq(_T_175, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 30:26] + node _T_177 = and(_T_174, _T_176) @[el2_ifu_compress_ctl.scala 30:24] + node _T_178 = bits(io.in, 13, 13) @[el2_ifu_compress_ctl.scala 30:45] + node _T_179 = eq(_T_178, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 30:39] + node _T_180 = and(_T_177, _T_179) @[el2_ifu_compress_ctl.scala 30:37] + node _T_181 = bits(io.in, 6, 6) @[el2_ifu_compress_ctl.scala 30:56] + node _T_182 = and(_T_180, _T_181) @[el2_ifu_compress_ctl.scala 30:50] + node _T_183 = bits(io.in, 5, 5) @[el2_ifu_compress_ctl.scala 30:65] + node _T_184 = and(_T_182, _T_183) @[el2_ifu_compress_ctl.scala 30:59] + node _T_185 = bits(io.in, 0, 0) @[el2_ifu_compress_ctl.scala 30:74] + node _T_186 = and(_T_184, _T_185) @[el2_ifu_compress_ctl.scala 30:68] + node _T_187 = bits(io.in, 15, 15) @[el2_ifu_compress_ctl.scala 31:21] + node _T_188 = bits(io.in, 14, 14) @[el2_ifu_compress_ctl.scala 31:33] + node _T_189 = eq(_T_188, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 31:27] + node _T_190 = and(_T_187, _T_189) @[el2_ifu_compress_ctl.scala 31:25] + node _T_191 = bits(io.in, 13, 13) @[el2_ifu_compress_ctl.scala 31:46] + node _T_192 = eq(_T_191, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 31:40] + node _T_193 = and(_T_190, _T_192) @[el2_ifu_compress_ctl.scala 31:38] + node _T_194 = bits(io.in, 11, 11) @[el2_ifu_compress_ctl.scala 31:59] + node _T_195 = eq(_T_194, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 31:53] + node _T_196 = and(_T_193, _T_195) @[el2_ifu_compress_ctl.scala 31:51] + node _T_197 = bits(io.in, 0, 0) @[el2_ifu_compress_ctl.scala 31:70] + node _T_198 = and(_T_196, _T_197) @[el2_ifu_compress_ctl.scala 31:64] + node _T_199 = or(_T_186, _T_198) @[el2_ifu_compress_ctl.scala 31:15] + node _T_200 = bits(io.in, 15, 15) @[el2_ifu_compress_ctl.scala 32:21] + node _T_201 = bits(io.in, 14, 14) @[el2_ifu_compress_ctl.scala 32:33] + node _T_202 = eq(_T_201, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 32:27] + node _T_203 = and(_T_200, _T_202) @[el2_ifu_compress_ctl.scala 32:25] + node _T_204 = bits(io.in, 13, 13) @[el2_ifu_compress_ctl.scala 32:46] + node _T_205 = eq(_T_204, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 32:40] + node _T_206 = and(_T_203, _T_205) @[el2_ifu_compress_ctl.scala 32:38] + node _T_207 = bits(io.in, 10, 10) @[el2_ifu_compress_ctl.scala 32:59] + node _T_208 = eq(_T_207, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 32:53] + node _T_209 = and(_T_206, _T_208) @[el2_ifu_compress_ctl.scala 32:51] + node _T_210 = bits(io.in, 0, 0) @[el2_ifu_compress_ctl.scala 32:70] + node _T_211 = and(_T_209, _T_210) @[el2_ifu_compress_ctl.scala 32:64] + node _T_212 = or(_T_199, _T_211) @[el2_ifu_compress_ctl.scala 32:15] + node _T_213 = bits(io.in, 15, 15) @[el2_ifu_compress_ctl.scala 32:83] + node _T_214 = eq(_T_213, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 32:77] + node _T_215 = bits(io.in, 14, 14) @[el2_ifu_compress_ctl.scala 32:96] + node _T_216 = eq(_T_215, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 32:90] + node _T_217 = and(_T_214, _T_216) @[el2_ifu_compress_ctl.scala 32:88] + node _T_218 = bits(io.in, 1, 1) @[el2_ifu_compress_ctl.scala 32:107] + node _T_219 = and(_T_217, _T_218) @[el2_ifu_compress_ctl.scala 32:101] + node _T_220 = or(_T_212, _T_219) @[el2_ifu_compress_ctl.scala 32:74] + node _T_221 = bits(io.in, 15, 15) @[el2_ifu_compress_ctl.scala 33:21] + node _T_222 = bits(io.in, 14, 14) @[el2_ifu_compress_ctl.scala 33:31] + node _T_223 = and(_T_221, _T_222) @[el2_ifu_compress_ctl.scala 33:25] + node _T_224 = bits(io.in, 13, 13) @[el2_ifu_compress_ctl.scala 33:41] + node _T_225 = and(_T_223, _T_224) @[el2_ifu_compress_ctl.scala 33:35] + node _T_226 = or(_T_220, _T_225) @[el2_ifu_compress_ctl.scala 33:15] + node _T_227 = mux(UInt<1>("h00"), UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] + node _T_228 = bits(io.in, 15, 15) @[el2_ifu_compress_ctl.scala 34:20] + node _T_229 = bits(io.in, 14, 14) @[el2_ifu_compress_ctl.scala 34:32] + node _T_230 = eq(_T_229, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 34:26] + node _T_231 = and(_T_228, _T_230) @[el2_ifu_compress_ctl.scala 34:24] + node _T_232 = bits(io.in, 6, 6) @[el2_ifu_compress_ctl.scala 34:45] + node _T_233 = eq(_T_232, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 34:39] + node _T_234 = and(_T_231, _T_233) @[el2_ifu_compress_ctl.scala 34:37] + node _T_235 = bits(io.in, 5, 5) @[el2_ifu_compress_ctl.scala 34:57] + node _T_236 = eq(_T_235, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 34:51] + node _T_237 = and(_T_234, _T_236) @[el2_ifu_compress_ctl.scala 34:49] + node _T_238 = bits(io.in, 4, 4) @[el2_ifu_compress_ctl.scala 34:69] + node _T_239 = eq(_T_238, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 34:63] + node _T_240 = and(_T_237, _T_239) @[el2_ifu_compress_ctl.scala 34:61] + node _T_241 = bits(io.in, 3, 3) @[el2_ifu_compress_ctl.scala 34:81] + node _T_242 = eq(_T_241, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 34:75] + node _T_243 = and(_T_240, _T_242) @[el2_ifu_compress_ctl.scala 34:73] + node _T_244 = bits(io.in, 2, 2) @[el2_ifu_compress_ctl.scala 34:93] + node _T_245 = eq(_T_244, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 34:87] + node _T_246 = and(_T_243, _T_245) @[el2_ifu_compress_ctl.scala 34:85] + node _T_247 = bits(io.in, 0, 0) @[el2_ifu_compress_ctl.scala 34:105] + node _T_248 = eq(_T_247, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 34:99] + node _T_249 = and(_T_246, _T_248) @[el2_ifu_compress_ctl.scala 34:97] + node _T_250 = bits(io.in, 14, 14) @[el2_ifu_compress_ctl.scala 35:23] + node _T_251 = eq(_T_250, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 35:17] + node _T_252 = bits(io.in, 13, 13) @[el2_ifu_compress_ctl.scala 35:34] + node _T_253 = and(_T_251, _T_252) @[el2_ifu_compress_ctl.scala 35:28] + node _T_254 = or(_T_249, _T_253) @[el2_ifu_compress_ctl.scala 35:15] + node _T_255 = bits(io.in, 15, 15) @[el2_ifu_compress_ctl.scala 35:46] + node _T_256 = bits(io.in, 14, 14) @[el2_ifu_compress_ctl.scala 35:56] + node _T_257 = and(_T_255, _T_256) @[el2_ifu_compress_ctl.scala 35:50] + node _T_258 = bits(io.in, 0, 0) @[el2_ifu_compress_ctl.scala 35:66] + node _T_259 = and(_T_257, _T_258) @[el2_ifu_compress_ctl.scala 35:60] + node _T_260 = or(_T_254, _T_259) @[el2_ifu_compress_ctl.scala 35:39] + node _T_261 = bits(io.in, 15, 15) @[el2_ifu_compress_ctl.scala 35:76] + node _T_262 = bits(io.in, 0, 0) @[el2_ifu_compress_ctl.scala 35:88] + node _T_263 = eq(_T_262, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 35:82] + node _T_264 = and(_T_261, _T_263) @[el2_ifu_compress_ctl.scala 35:80] + node _T_265 = bits(io.in, 15, 15) @[el2_ifu_compress_ctl.scala 36:21] + node _T_266 = bits(io.in, 11, 11) @[el2_ifu_compress_ctl.scala 36:31] + node _T_267 = and(_T_265, _T_266) @[el2_ifu_compress_ctl.scala 36:25] + node _T_268 = bits(io.in, 10, 10) @[el2_ifu_compress_ctl.scala 36:41] + node _T_269 = and(_T_267, _T_268) @[el2_ifu_compress_ctl.scala 36:35] + node _T_270 = or(_T_264, _T_269) @[el2_ifu_compress_ctl.scala 36:15] + node _T_271 = bits(io.in, 13, 13) @[el2_ifu_compress_ctl.scala 36:53] + node _T_272 = bits(io.in, 8, 8) @[el2_ifu_compress_ctl.scala 36:65] + node _T_273 = eq(_T_272, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 36:59] + node _T_274 = and(_T_271, _T_273) @[el2_ifu_compress_ctl.scala 36:57] + node _T_275 = or(_T_270, _T_274) @[el2_ifu_compress_ctl.scala 36:46] + node _T_276 = bits(io.in, 13, 13) @[el2_ifu_compress_ctl.scala 37:21] + node _T_277 = bits(io.in, 8, 8) @[el2_ifu_compress_ctl.scala 37:33] + node _T_278 = eq(_T_277, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 37:27] + node _T_279 = and(_T_276, _T_278) @[el2_ifu_compress_ctl.scala 37:25] + node _T_280 = or(_T_275, _T_279) @[el2_ifu_compress_ctl.scala 37:15] + node _T_281 = bits(io.in, 13, 13) @[el2_ifu_compress_ctl.scala 37:43] + node _T_282 = bits(io.in, 7, 7) @[el2_ifu_compress_ctl.scala 37:53] + node _T_283 = and(_T_281, _T_282) @[el2_ifu_compress_ctl.scala 37:47] + node _T_284 = or(_T_280, _T_283) @[el2_ifu_compress_ctl.scala 37:37] + node _T_285 = bits(io.in, 13, 13) @[el2_ifu_compress_ctl.scala 37:62] + node _T_286 = bits(io.in, 9, 9) @[el2_ifu_compress_ctl.scala 37:72] + node _T_287 = and(_T_285, _T_286) @[el2_ifu_compress_ctl.scala 37:66] + node _T_288 = or(_T_284, _T_287) @[el2_ifu_compress_ctl.scala 37:56] + node _T_289 = bits(io.in, 13, 13) @[el2_ifu_compress_ctl.scala 37:81] + node _T_290 = bits(io.in, 10, 10) @[el2_ifu_compress_ctl.scala 37:91] + node _T_291 = and(_T_289, _T_290) @[el2_ifu_compress_ctl.scala 37:85] + node _T_292 = or(_T_288, _T_291) @[el2_ifu_compress_ctl.scala 37:75] + node _T_293 = bits(io.in, 13, 13) @[el2_ifu_compress_ctl.scala 38:21] + node _T_294 = bits(io.in, 11, 11) @[el2_ifu_compress_ctl.scala 38:31] + node _T_295 = and(_T_293, _T_294) @[el2_ifu_compress_ctl.scala 38:25] + node _T_296 = or(_T_292, _T_295) @[el2_ifu_compress_ctl.scala 38:15] + node _T_297 = bits(io.in, 13, 13) @[el2_ifu_compress_ctl.scala 38:41] + node _T_298 = bits(io.in, 14, 14) @[el2_ifu_compress_ctl.scala 38:53] + node _T_299 = eq(_T_298, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 38:47] + node _T_300 = and(_T_297, _T_299) @[el2_ifu_compress_ctl.scala 38:45] + node _T_301 = or(_T_296, _T_300) @[el2_ifu_compress_ctl.scala 38:35] + node _T_302 = bits(io.in, 14, 14) @[el2_ifu_compress_ctl.scala 38:64] + node _T_303 = bits(io.in, 15, 15) @[el2_ifu_compress_ctl.scala 38:74] + node _T_304 = and(_T_302, _T_303) @[el2_ifu_compress_ctl.scala 38:68] + node _T_305 = or(_T_301, _T_304) @[el2_ifu_compress_ctl.scala 38:58] + node _T_306 = bits(io.in, 14, 14) @[el2_ifu_compress_ctl.scala 39:21] + node _T_307 = eq(_T_306, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 39:15] + node _T_308 = bits(io.in, 11, 11) @[el2_ifu_compress_ctl.scala 39:33] + node _T_309 = eq(_T_308, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 39:27] + node _T_310 = and(_T_307, _T_309) @[el2_ifu_compress_ctl.scala 39:25] + node _T_311 = bits(io.in, 10, 10) @[el2_ifu_compress_ctl.scala 39:46] + node _T_312 = eq(_T_311, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 39:40] + node _T_313 = and(_T_310, _T_312) @[el2_ifu_compress_ctl.scala 39:38] + node _T_314 = bits(io.in, 9, 9) @[el2_ifu_compress_ctl.scala 39:59] + node _T_315 = eq(_T_314, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 39:53] + node _T_316 = and(_T_313, _T_315) @[el2_ifu_compress_ctl.scala 39:51] + node _T_317 = bits(io.in, 8, 8) @[el2_ifu_compress_ctl.scala 39:71] + node _T_318 = eq(_T_317, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 39:65] + node _T_319 = and(_T_316, _T_318) @[el2_ifu_compress_ctl.scala 39:63] + node _T_320 = bits(io.in, 7, 7) @[el2_ifu_compress_ctl.scala 39:83] + node _T_321 = eq(_T_320, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 39:77] + node _T_322 = and(_T_319, _T_321) @[el2_ifu_compress_ctl.scala 39:75] + node _T_323 = bits(io.in, 0, 0) @[el2_ifu_compress_ctl.scala 39:95] + node _T_324 = eq(_T_323, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 39:89] + node _T_325 = and(_T_322, _T_324) @[el2_ifu_compress_ctl.scala 39:87] + node _T_326 = bits(io.in, 15, 15) @[el2_ifu_compress_ctl.scala 40:23] + node _T_327 = eq(_T_326, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 40:17] + node _T_328 = bits(io.in, 14, 14) @[el2_ifu_compress_ctl.scala 40:36] + node _T_329 = eq(_T_328, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 40:30] + node _T_330 = and(_T_327, _T_329) @[el2_ifu_compress_ctl.scala 40:28] + node _T_331 = bits(io.in, 0, 0) @[el2_ifu_compress_ctl.scala 40:49] + node _T_332 = eq(_T_331, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 40:43] + node _T_333 = and(_T_330, _T_332) @[el2_ifu_compress_ctl.scala 40:41] + node _T_334 = or(_T_325, _T_333) @[el2_ifu_compress_ctl.scala 40:15] + node _T_335 = bits(io.in, 14, 14) @[el2_ifu_compress_ctl.scala 40:61] + node _T_336 = eq(_T_335, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 40:55] + node _T_337 = bits(io.in, 6, 6) @[el2_ifu_compress_ctl.scala 40:72] + node _T_338 = and(_T_336, _T_337) @[el2_ifu_compress_ctl.scala 40:66] + node _T_339 = bits(io.in, 0, 0) @[el2_ifu_compress_ctl.scala 40:83] + node _T_340 = eq(_T_339, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 40:77] + node _T_341 = and(_T_338, _T_340) @[el2_ifu_compress_ctl.scala 40:75] + node _T_342 = or(_T_334, _T_341) @[el2_ifu_compress_ctl.scala 40:53] + node _T_343 = bits(io.in, 15, 15) @[el2_ifu_compress_ctl.scala 41:23] + node _T_344 = eq(_T_343, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 41:17] + node _T_345 = bits(io.in, 14, 14) @[el2_ifu_compress_ctl.scala 41:34] + node _T_346 = and(_T_344, _T_345) @[el2_ifu_compress_ctl.scala 41:28] + node _T_347 = bits(io.in, 0, 0) @[el2_ifu_compress_ctl.scala 41:44] + node _T_348 = and(_T_346, _T_347) @[el2_ifu_compress_ctl.scala 41:38] + node _T_349 = or(_T_342, _T_348) @[el2_ifu_compress_ctl.scala 41:15] + node _T_350 = bits(io.in, 14, 14) @[el2_ifu_compress_ctl.scala 41:55] + node _T_351 = eq(_T_350, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 41:49] + node _T_352 = bits(io.in, 5, 5) @[el2_ifu_compress_ctl.scala 41:66] + node _T_353 = and(_T_351, _T_352) @[el2_ifu_compress_ctl.scala 41:60] + node _T_354 = bits(io.in, 0, 0) @[el2_ifu_compress_ctl.scala 41:77] + node _T_355 = eq(_T_354, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 41:71] + node _T_356 = and(_T_353, _T_355) @[el2_ifu_compress_ctl.scala 41:69] + node _T_357 = or(_T_349, _T_356) @[el2_ifu_compress_ctl.scala 41:47] + node _T_358 = bits(io.in, 14, 14) @[el2_ifu_compress_ctl.scala 42:23] + node _T_359 = eq(_T_358, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 42:17] + node _T_360 = bits(io.in, 4, 4) @[el2_ifu_compress_ctl.scala 42:34] + node _T_361 = and(_T_359, _T_360) @[el2_ifu_compress_ctl.scala 42:28] + node _T_362 = bits(io.in, 0, 0) @[el2_ifu_compress_ctl.scala 42:45] + node _T_363 = eq(_T_362, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 42:39] + node _T_364 = and(_T_361, _T_363) @[el2_ifu_compress_ctl.scala 42:37] + node _T_365 = or(_T_357, _T_364) @[el2_ifu_compress_ctl.scala 42:15] + node _T_366 = bits(io.in, 14, 14) @[el2_ifu_compress_ctl.scala 42:59] + node _T_367 = eq(_T_366, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 42:53] + node _T_368 = bits(io.in, 13, 13) @[el2_ifu_compress_ctl.scala 42:72] + node _T_369 = eq(_T_368, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 42:66] + node _T_370 = and(_T_367, _T_369) @[el2_ifu_compress_ctl.scala 42:64] + node _T_371 = bits(io.in, 0, 0) @[el2_ifu_compress_ctl.scala 42:83] + node _T_372 = and(_T_370, _T_371) @[el2_ifu_compress_ctl.scala 42:77] + node _T_373 = or(_T_365, _T_372) @[el2_ifu_compress_ctl.scala 42:50] + node _T_374 = bits(io.in, 14, 14) @[el2_ifu_compress_ctl.scala 43:23] + node _T_375 = eq(_T_374, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 43:17] + node _T_376 = bits(io.in, 3, 3) @[el2_ifu_compress_ctl.scala 43:34] + node _T_377 = and(_T_375, _T_376) @[el2_ifu_compress_ctl.scala 43:28] + node _T_378 = bits(io.in, 0, 0) @[el2_ifu_compress_ctl.scala 43:45] + node _T_379 = eq(_T_378, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 43:39] + node _T_380 = and(_T_377, _T_379) @[el2_ifu_compress_ctl.scala 43:37] + node _T_381 = or(_T_373, _T_380) @[el2_ifu_compress_ctl.scala 43:15] + node _T_382 = bits(io.in, 14, 14) @[el2_ifu_compress_ctl.scala 43:59] + node _T_383 = eq(_T_382, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 43:53] + node _T_384 = bits(io.in, 2, 2) @[el2_ifu_compress_ctl.scala 43:70] + node _T_385 = and(_T_383, _T_384) @[el2_ifu_compress_ctl.scala 43:64] + node _T_386 = bits(io.in, 0, 0) @[el2_ifu_compress_ctl.scala 43:81] + node _T_387 = eq(_T_386, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 43:75] + node _T_388 = and(_T_385, _T_387) @[el2_ifu_compress_ctl.scala 43:73] + node _T_389 = or(_T_381, _T_388) @[el2_ifu_compress_ctl.scala 43:50] + node _T_390 = bits(io.in, 14, 14) @[el2_ifu_compress_ctl.scala 44:21] + node _T_391 = eq(_T_390, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 44:15] + node _T_392 = bits(io.in, 13, 13) @[el2_ifu_compress_ctl.scala 44:31] + node _T_393 = and(_T_391, _T_392) @[el2_ifu_compress_ctl.scala 44:25] + node _T_394 = bits(io.in, 14, 14) @[el2_ifu_compress_ctl.scala 45:21] + node _T_395 = eq(_T_394, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 45:15] + node _T_396 = bits(io.in, 12, 12) @[el2_ifu_compress_ctl.scala 45:31] + node _T_397 = and(_T_395, _T_396) @[el2_ifu_compress_ctl.scala 45:25] + node _T_398 = bits(io.in, 11, 11) @[el2_ifu_compress_ctl.scala 45:41] + node _T_399 = and(_T_397, _T_398) @[el2_ifu_compress_ctl.scala 45:35] + node _T_400 = bits(io.in, 6, 6) @[el2_ifu_compress_ctl.scala 45:53] + node _T_401 = eq(_T_400, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 45:47] + node _T_402 = and(_T_399, _T_401) @[el2_ifu_compress_ctl.scala 45:45] + node _T_403 = bits(io.in, 5, 5) @[el2_ifu_compress_ctl.scala 45:65] + node _T_404 = eq(_T_403, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 45:59] + node _T_405 = and(_T_402, _T_404) @[el2_ifu_compress_ctl.scala 45:57] + node _T_406 = bits(io.in, 4, 4) @[el2_ifu_compress_ctl.scala 45:77] + node _T_407 = eq(_T_406, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 45:71] + node _T_408 = and(_T_405, _T_407) @[el2_ifu_compress_ctl.scala 45:69] + node _T_409 = bits(io.in, 3, 3) @[el2_ifu_compress_ctl.scala 45:89] + node _T_410 = eq(_T_409, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 45:83] + node _T_411 = and(_T_408, _T_410) @[el2_ifu_compress_ctl.scala 45:81] + node _T_412 = bits(io.in, 2, 2) @[el2_ifu_compress_ctl.scala 45:101] + node _T_413 = eq(_T_412, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 45:95] + node _T_414 = and(_T_411, _T_413) @[el2_ifu_compress_ctl.scala 45:93] + node _T_415 = bits(io.in, 1, 1) @[el2_ifu_compress_ctl.scala 45:111] + node _T_416 = and(_T_414, _T_415) @[el2_ifu_compress_ctl.scala 45:105] + node _T_417 = bits(io.in, 14, 14) @[el2_ifu_compress_ctl.scala 46:23] + node _T_418 = eq(_T_417, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 46:17] + node _T_419 = bits(io.in, 12, 12) @[el2_ifu_compress_ctl.scala 46:34] + node _T_420 = and(_T_418, _T_419) @[el2_ifu_compress_ctl.scala 46:28] + node _T_421 = bits(io.in, 10, 10) @[el2_ifu_compress_ctl.scala 46:44] + node _T_422 = and(_T_420, _T_421) @[el2_ifu_compress_ctl.scala 46:38] + node _T_423 = bits(io.in, 6, 6) @[el2_ifu_compress_ctl.scala 46:56] + node _T_424 = eq(_T_423, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 46:50] + node _T_425 = and(_T_422, _T_424) @[el2_ifu_compress_ctl.scala 46:48] + node _T_426 = bits(io.in, 5, 5) @[el2_ifu_compress_ctl.scala 46:68] + node _T_427 = eq(_T_426, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 46:62] + node _T_428 = and(_T_425, _T_427) @[el2_ifu_compress_ctl.scala 46:60] + node _T_429 = bits(io.in, 4, 4) @[el2_ifu_compress_ctl.scala 46:80] + node _T_430 = eq(_T_429, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 46:74] + node _T_431 = and(_T_428, _T_430) @[el2_ifu_compress_ctl.scala 46:72] + node _T_432 = bits(io.in, 3, 3) @[el2_ifu_compress_ctl.scala 46:92] + node _T_433 = eq(_T_432, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 46:86] + node _T_434 = and(_T_431, _T_433) @[el2_ifu_compress_ctl.scala 46:84] + node _T_435 = bits(io.in, 2, 2) @[el2_ifu_compress_ctl.scala 46:104] + node _T_436 = eq(_T_435, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 46:98] + node _T_437 = and(_T_434, _T_436) @[el2_ifu_compress_ctl.scala 46:96] + node _T_438 = bits(io.in, 1, 1) @[el2_ifu_compress_ctl.scala 46:114] + node _T_439 = and(_T_437, _T_438) @[el2_ifu_compress_ctl.scala 46:108] + node _T_440 = or(_T_416, _T_439) @[el2_ifu_compress_ctl.scala 46:15] + node _T_441 = bits(io.in, 14, 14) @[el2_ifu_compress_ctl.scala 47:23] + node _T_442 = eq(_T_441, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 47:17] + node _T_443 = bits(io.in, 12, 12) @[el2_ifu_compress_ctl.scala 47:34] + node _T_444 = and(_T_442, _T_443) @[el2_ifu_compress_ctl.scala 47:28] + node _T_445 = bits(io.in, 9, 9) @[el2_ifu_compress_ctl.scala 47:44] + node _T_446 = and(_T_444, _T_445) @[el2_ifu_compress_ctl.scala 47:38] + node _T_447 = bits(io.in, 6, 6) @[el2_ifu_compress_ctl.scala 47:55] + node _T_448 = eq(_T_447, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 47:49] + node _T_449 = and(_T_446, _T_448) @[el2_ifu_compress_ctl.scala 47:47] + node _T_450 = bits(io.in, 5, 5) @[el2_ifu_compress_ctl.scala 47:67] + node _T_451 = eq(_T_450, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 47:61] + node _T_452 = and(_T_449, _T_451) @[el2_ifu_compress_ctl.scala 47:59] + node _T_453 = bits(io.in, 4, 4) @[el2_ifu_compress_ctl.scala 47:79] + node _T_454 = eq(_T_453, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 47:73] + node _T_455 = and(_T_452, _T_454) @[el2_ifu_compress_ctl.scala 47:71] + node _T_456 = bits(io.in, 3, 3) @[el2_ifu_compress_ctl.scala 47:91] + node _T_457 = eq(_T_456, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 47:85] + node _T_458 = and(_T_455, _T_457) @[el2_ifu_compress_ctl.scala 47:83] + node _T_459 = bits(io.in, 2, 2) @[el2_ifu_compress_ctl.scala 47:103] + node _T_460 = eq(_T_459, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 47:97] + node _T_461 = and(_T_458, _T_460) @[el2_ifu_compress_ctl.scala 47:95] + node _T_462 = bits(io.in, 1, 1) @[el2_ifu_compress_ctl.scala 47:113] + node _T_463 = and(_T_461, _T_462) @[el2_ifu_compress_ctl.scala 47:107] + node _T_464 = or(_T_440, _T_463) @[el2_ifu_compress_ctl.scala 47:15] + node _T_465 = bits(io.in, 14, 14) @[el2_ifu_compress_ctl.scala 48:23] + node _T_466 = eq(_T_465, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 48:17] + node _T_467 = bits(io.in, 12, 12) @[el2_ifu_compress_ctl.scala 48:34] + node _T_468 = and(_T_466, _T_467) @[el2_ifu_compress_ctl.scala 48:28] + node _T_469 = bits(io.in, 8, 8) @[el2_ifu_compress_ctl.scala 48:44] + node _T_470 = and(_T_468, _T_469) @[el2_ifu_compress_ctl.scala 48:38] + node _T_471 = bits(io.in, 6, 6) @[el2_ifu_compress_ctl.scala 48:55] + node _T_472 = eq(_T_471, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 48:49] + node _T_473 = and(_T_470, _T_472) @[el2_ifu_compress_ctl.scala 48:47] + node _T_474 = bits(io.in, 5, 5) @[el2_ifu_compress_ctl.scala 48:67] + node _T_475 = eq(_T_474, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 48:61] + node _T_476 = and(_T_473, _T_475) @[el2_ifu_compress_ctl.scala 48:59] + node _T_477 = bits(io.in, 4, 4) @[el2_ifu_compress_ctl.scala 48:79] + node _T_478 = eq(_T_477, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 48:73] + node _T_479 = and(_T_476, _T_478) @[el2_ifu_compress_ctl.scala 48:71] + node _T_480 = bits(io.in, 3, 3) @[el2_ifu_compress_ctl.scala 48:91] + node _T_481 = eq(_T_480, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 48:85] + node _T_482 = and(_T_479, _T_481) @[el2_ifu_compress_ctl.scala 48:83] + node _T_483 = bits(io.in, 2, 2) @[el2_ifu_compress_ctl.scala 48:103] + node _T_484 = eq(_T_483, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 48:97] + node _T_485 = and(_T_482, _T_484) @[el2_ifu_compress_ctl.scala 48:95] + node _T_486 = bits(io.in, 1, 1) @[el2_ifu_compress_ctl.scala 48:113] + node _T_487 = and(_T_485, _T_486) @[el2_ifu_compress_ctl.scala 48:107] + node _T_488 = or(_T_464, _T_487) @[el2_ifu_compress_ctl.scala 48:15] + node _T_489 = bits(io.in, 14, 14) @[el2_ifu_compress_ctl.scala 49:23] + node _T_490 = eq(_T_489, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 49:17] + node _T_491 = bits(io.in, 12, 12) @[el2_ifu_compress_ctl.scala 49:34] + node _T_492 = and(_T_490, _T_491) @[el2_ifu_compress_ctl.scala 49:28] + node _T_493 = bits(io.in, 7, 7) @[el2_ifu_compress_ctl.scala 49:44] + node _T_494 = and(_T_492, _T_493) @[el2_ifu_compress_ctl.scala 49:38] + node _T_495 = bits(io.in, 6, 6) @[el2_ifu_compress_ctl.scala 49:55] + node _T_496 = eq(_T_495, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 49:49] + node _T_497 = and(_T_494, _T_496) @[el2_ifu_compress_ctl.scala 49:47] + node _T_498 = bits(io.in, 5, 5) @[el2_ifu_compress_ctl.scala 49:67] + node _T_499 = eq(_T_498, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 49:61] + node _T_500 = and(_T_497, _T_499) @[el2_ifu_compress_ctl.scala 49:59] + node _T_501 = bits(io.in, 4, 4) @[el2_ifu_compress_ctl.scala 49:79] + node _T_502 = eq(_T_501, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 49:73] + node _T_503 = and(_T_500, _T_502) @[el2_ifu_compress_ctl.scala 49:71] + node _T_504 = bits(io.in, 3, 3) @[el2_ifu_compress_ctl.scala 49:91] + node _T_505 = eq(_T_504, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 49:85] + node _T_506 = and(_T_503, _T_505) @[el2_ifu_compress_ctl.scala 49:83] + node _T_507 = bits(io.in, 2, 2) @[el2_ifu_compress_ctl.scala 49:103] + node _T_508 = eq(_T_507, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 49:97] + node _T_509 = and(_T_506, _T_508) @[el2_ifu_compress_ctl.scala 49:95] + node _T_510 = bits(io.in, 1, 1) @[el2_ifu_compress_ctl.scala 49:113] + node _T_511 = and(_T_509, _T_510) @[el2_ifu_compress_ctl.scala 49:107] + node _T_512 = or(_T_488, _T_511) @[el2_ifu_compress_ctl.scala 49:15] + node _T_513 = bits(io.in, 15, 15) @[el2_ifu_compress_ctl.scala 50:21] + node _T_514 = bits(io.in, 14, 14) @[el2_ifu_compress_ctl.scala 50:33] + node _T_515 = eq(_T_514, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 50:27] + node _T_516 = and(_T_513, _T_515) @[el2_ifu_compress_ctl.scala 50:25] + node _T_517 = bits(io.in, 12, 12) @[el2_ifu_compress_ctl.scala 50:46] + node _T_518 = eq(_T_517, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 50:40] + node _T_519 = and(_T_516, _T_518) @[el2_ifu_compress_ctl.scala 50:38] + node _T_520 = bits(io.in, 6, 6) @[el2_ifu_compress_ctl.scala 50:59] + node _T_521 = eq(_T_520, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 50:53] + node _T_522 = and(_T_519, _T_521) @[el2_ifu_compress_ctl.scala 50:51] + node _T_523 = bits(io.in, 5, 5) @[el2_ifu_compress_ctl.scala 50:71] + node _T_524 = eq(_T_523, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 50:65] + node _T_525 = and(_T_522, _T_524) @[el2_ifu_compress_ctl.scala 50:63] + node _T_526 = bits(io.in, 4, 4) @[el2_ifu_compress_ctl.scala 50:83] + node _T_527 = eq(_T_526, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 50:77] + node _T_528 = and(_T_525, _T_527) @[el2_ifu_compress_ctl.scala 50:75] + node _T_529 = bits(io.in, 3, 3) @[el2_ifu_compress_ctl.scala 50:95] + node _T_530 = eq(_T_529, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 50:89] + node _T_531 = and(_T_528, _T_530) @[el2_ifu_compress_ctl.scala 50:87] + node _T_532 = bits(io.in, 2, 2) @[el2_ifu_compress_ctl.scala 50:107] + node _T_533 = eq(_T_532, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 50:101] + node _T_534 = and(_T_531, _T_533) @[el2_ifu_compress_ctl.scala 50:99] + node _T_535 = bits(io.in, 0, 0) @[el2_ifu_compress_ctl.scala 50:119] + node _T_536 = eq(_T_535, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 50:113] + node _T_537 = and(_T_534, _T_536) @[el2_ifu_compress_ctl.scala 50:111] + node _T_538 = or(_T_512, _T_537) @[el2_ifu_compress_ctl.scala 50:15] + node _T_539 = bits(io.in, 15, 15) @[el2_ifu_compress_ctl.scala 51:23] + node _T_540 = eq(_T_539, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 51:17] + node _T_541 = bits(io.in, 13, 13) @[el2_ifu_compress_ctl.scala 51:34] + node _T_542 = and(_T_540, _T_541) @[el2_ifu_compress_ctl.scala 51:28] + node _T_543 = bits(io.in, 8, 8) @[el2_ifu_compress_ctl.scala 51:46] + node _T_544 = eq(_T_543, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 51:40] + node _T_545 = and(_T_542, _T_544) @[el2_ifu_compress_ctl.scala 51:38] + node _T_546 = or(_T_538, _T_545) @[el2_ifu_compress_ctl.scala 51:15] + node _T_547 = bits(io.in, 15, 15) @[el2_ifu_compress_ctl.scala 51:60] + node _T_548 = eq(_T_547, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 51:54] + node _T_549 = bits(io.in, 13, 13) @[el2_ifu_compress_ctl.scala 51:71] + node _T_550 = and(_T_548, _T_549) @[el2_ifu_compress_ctl.scala 51:65] + node _T_551 = bits(io.in, 7, 7) @[el2_ifu_compress_ctl.scala 51:81] + node _T_552 = and(_T_550, _T_551) @[el2_ifu_compress_ctl.scala 51:75] + node _T_553 = or(_T_546, _T_552) @[el2_ifu_compress_ctl.scala 51:51] + node _T_554 = bits(io.in, 15, 15) @[el2_ifu_compress_ctl.scala 51:94] + node _T_555 = eq(_T_554, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 51:88] + node _T_556 = bits(io.in, 13, 13) @[el2_ifu_compress_ctl.scala 51:105] + node _T_557 = and(_T_555, _T_556) @[el2_ifu_compress_ctl.scala 51:99] + node _T_558 = bits(io.in, 9, 9) @[el2_ifu_compress_ctl.scala 51:115] + node _T_559 = and(_T_557, _T_558) @[el2_ifu_compress_ctl.scala 51:109] + node _T_560 = or(_T_553, _T_559) @[el2_ifu_compress_ctl.scala 51:85] + node _T_561 = bits(io.in, 15, 15) @[el2_ifu_compress_ctl.scala 52:23] + node _T_562 = eq(_T_561, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 52:17] + node _T_563 = bits(io.in, 13, 13) @[el2_ifu_compress_ctl.scala 52:34] + node _T_564 = and(_T_562, _T_563) @[el2_ifu_compress_ctl.scala 52:28] + node _T_565 = bits(io.in, 10, 10) @[el2_ifu_compress_ctl.scala 52:44] + node _T_566 = and(_T_564, _T_565) @[el2_ifu_compress_ctl.scala 52:38] + node _T_567 = or(_T_560, _T_566) @[el2_ifu_compress_ctl.scala 52:15] + node _T_568 = bits(io.in, 15, 15) @[el2_ifu_compress_ctl.scala 52:58] + node _T_569 = eq(_T_568, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 52:52] + node _T_570 = bits(io.in, 13, 13) @[el2_ifu_compress_ctl.scala 52:69] + node _T_571 = and(_T_569, _T_570) @[el2_ifu_compress_ctl.scala 52:63] + node _T_572 = bits(io.in, 11, 11) @[el2_ifu_compress_ctl.scala 52:79] + node _T_573 = and(_T_571, _T_572) @[el2_ifu_compress_ctl.scala 52:73] + node _T_574 = or(_T_567, _T_573) @[el2_ifu_compress_ctl.scala 52:49] + node _T_575 = bits(io.in, 14, 14) @[el2_ifu_compress_ctl.scala 52:93] + node _T_576 = eq(_T_575, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 52:87] + node _T_577 = bits(io.in, 13, 13) @[el2_ifu_compress_ctl.scala 52:103] + node _T_578 = and(_T_576, _T_577) @[el2_ifu_compress_ctl.scala 52:97] + node _T_579 = or(_T_574, _T_578) @[el2_ifu_compress_ctl.scala 52:84] + node _T_580 = mux(UInt<1>("h01"), UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_581 = cat(_T_393, _T_579) @[Cat.scala 29:58] + node _T_582 = cat(_T_581, _T_580) @[Cat.scala 29:58] + node _T_583 = cat(_T_305, _T_389) @[Cat.scala 29:58] + node _T_584 = cat(_T_227, _T_260) @[Cat.scala 29:58] + node _T_585 = cat(_T_584, _T_583) @[Cat.scala 29:58] + node _T_586 = cat(_T_585, _T_582) @[Cat.scala 29:58] + node _T_587 = cat(_T_173, _T_226) @[Cat.scala 29:58] + node _T_588 = cat(_T_71, _T_120) @[Cat.scala 29:58] + node _T_589 = cat(_T_588, _T_587) @[Cat.scala 29:58] + node _T_590 = cat(_T_34, _T_70) @[Cat.scala 29:58] + node _T_591 = cat(UInt<1>("h00"), _T_33) @[Cat.scala 29:58] + node _T_592 = cat(_T_591, _T_590) @[Cat.scala 29:58] + node _T_593 = cat(_T_592, _T_589) @[Cat.scala 29:58] + node o = cat(_T_593, _T_586) @[Cat.scala 29:58] + node _T_594 = bits(io.in, 12, 12) @[el2_ifu_compress_ctl.scala 55:25] + node _T_595 = bits(io.in, 6, 2) @[el2_ifu_compress_ctl.scala 55:36] + node simm5d = cat(_T_594, _T_595) @[Cat.scala 29:58] + node _T_596 = bits(io.in, 10, 7) @[el2_ifu_compress_ctl.scala 56:25] + node _T_597 = bits(io.in, 12, 11) @[el2_ifu_compress_ctl.scala 56:38] + node _T_598 = bits(io.in, 5, 5) @[el2_ifu_compress_ctl.scala 56:52] + node _T_599 = bits(io.in, 6, 6) @[el2_ifu_compress_ctl.scala 56:62] + node _T_600 = cat(_T_598, _T_599) @[Cat.scala 29:58] + node _T_601 = cat(_T_596, _T_597) @[Cat.scala 29:58] + node uimm9d = cat(_T_601, _T_600) @[Cat.scala 29:58] + node _T_602 = bits(io.in, 12, 12) @[el2_ifu_compress_ctl.scala 57:25] + node _T_603 = bits(io.in, 4, 3) @[el2_ifu_compress_ctl.scala 57:36] + node _T_604 = bits(io.in, 5, 5) @[el2_ifu_compress_ctl.scala 57:48] + node _T_605 = bits(io.in, 2, 2) @[el2_ifu_compress_ctl.scala 57:58] + node _T_606 = bits(io.in, 6, 6) @[el2_ifu_compress_ctl.scala 57:68] + node _T_607 = cat(_T_605, _T_606) @[Cat.scala 29:58] + node _T_608 = cat(_T_602, _T_603) @[Cat.scala 29:58] + node _T_609 = cat(_T_608, _T_604) @[Cat.scala 29:58] + node simm9d = cat(_T_609, _T_607) @[Cat.scala 29:58] + node _T_610 = bits(io.in, 5, 5) @[el2_ifu_compress_ctl.scala 58:26] + node _T_611 = bits(io.in, 12, 10) @[el2_ifu_compress_ctl.scala 58:36] + node _T_612 = bits(io.in, 6, 6) @[el2_ifu_compress_ctl.scala 58:50] + node _T_613 = cat(_T_610, _T_611) @[Cat.scala 29:58] + node ulimm6d = cat(_T_613, _T_612) @[Cat.scala 29:58] + node _T_614 = bits(io.in, 3, 2) @[el2_ifu_compress_ctl.scala 59:29] + node _T_615 = bits(io.in, 12, 12) @[el2_ifu_compress_ctl.scala 59:41] + node _T_616 = bits(io.in, 6, 4) @[el2_ifu_compress_ctl.scala 59:52] + node _T_617 = cat(_T_614, _T_615) @[Cat.scala 29:58] + node ulwspimm7d = cat(_T_617, _T_616) @[Cat.scala 29:58] + node _T_618 = bits(io.in, 12, 12) @[el2_ifu_compress_ctl.scala 60:25] + node _T_619 = bits(io.in, 6, 2) @[el2_ifu_compress_ctl.scala 60:36] + node uimm5d = cat(_T_618, _T_619) @[Cat.scala 29:58] + node _T_620 = bits(io.in, 12, 12) @[el2_ifu_compress_ctl.scala 61:32] + node _T_621 = bits(_T_620, 0, 0) @[Bitwise.scala 72:15] + node _T_622 = mux(_T_621, UInt<9>("h01ff"), UInt<9>("h00")) @[Bitwise.scala 72:12] + node _T_623 = bits(io.in, 12, 12) @[el2_ifu_compress_ctl.scala 61:44] + node _T_624 = bits(io.in, 8, 8) @[el2_ifu_compress_ctl.scala 61:55] + node _T_625 = bits(io.in, 10, 9) @[el2_ifu_compress_ctl.scala 61:65] + node _T_626 = bits(io.in, 6, 6) @[el2_ifu_compress_ctl.scala 61:78] + node _T_627 = bits(io.in, 7, 7) @[el2_ifu_compress_ctl.scala 61:88] + node _T_628 = bits(io.in, 2, 2) @[el2_ifu_compress_ctl.scala 61:98] + node _T_629 = bits(io.in, 11, 11) @[el2_ifu_compress_ctl.scala 61:108] + node _T_630 = bits(io.in, 5, 4) @[el2_ifu_compress_ctl.scala 61:119] + node _T_631 = bits(io.in, 3, 3) @[el2_ifu_compress_ctl.scala 61:131] + node _T_632 = cat(_T_630, _T_631) @[Cat.scala 29:58] + node _T_633 = cat(_T_627, _T_628) @[Cat.scala 29:58] + node _T_634 = cat(_T_633, _T_629) @[Cat.scala 29:58] + node _T_635 = cat(_T_634, _T_632) @[Cat.scala 29:58] + node _T_636 = cat(_T_625, _T_626) @[Cat.scala 29:58] + node _T_637 = cat(_T_622, _T_623) @[Cat.scala 29:58] + node _T_638 = cat(_T_637, _T_624) @[Cat.scala 29:58] + node _T_639 = cat(_T_638, _T_636) @[Cat.scala 29:58] + node sjald = cat(_T_639, _T_635) @[Cat.scala 29:58] + node _T_640 = bits(io.in, 12, 12) @[el2_ifu_compress_ctl.scala 62:35] + node _T_641 = bits(_T_640, 0, 0) @[Bitwise.scala 72:15] + node _T_642 = mux(_T_641, UInt<15>("h07fff"), UInt<15>("h00")) @[Bitwise.scala 72:12] + node _T_643 = bits(io.in, 6, 2) @[el2_ifu_compress_ctl.scala 62:47] + node sluimmd = cat(_T_642, _T_643) @[Cat.scala 29:58] + node _T_644 = bits(io.in, 12, 12) @[el2_ifu_compress_ctl.scala 63:24] + node _T_645 = bits(io.in, 6, 6) @[el2_ifu_compress_ctl.scala 63:35] + node _T_646 = bits(io.in, 5, 5) @[el2_ifu_compress_ctl.scala 63:45] + node _T_647 = bits(io.in, 2, 2) @[el2_ifu_compress_ctl.scala 63:55] + node _T_648 = bits(io.in, 11, 11) @[el2_ifu_compress_ctl.scala 63:65] + node _T_649 = bits(io.in, 10, 10) @[el2_ifu_compress_ctl.scala 63:76] + node _T_650 = bits(io.in, 4, 4) @[el2_ifu_compress_ctl.scala 63:87] + node _T_651 = bits(io.in, 3, 3) @[el2_ifu_compress_ctl.scala 63:97] + node _T_652 = cat(_T_650, _T_651) @[Cat.scala 29:58] + node _T_653 = cat(_T_648, _T_649) @[Cat.scala 29:58] + node _T_654 = cat(_T_653, _T_652) @[Cat.scala 29:58] + node _T_655 = cat(_T_646, _T_647) @[Cat.scala 29:58] + node _T_656 = cat(_T_644, _T_645) @[Cat.scala 29:58] + node _T_657 = cat(_T_656, _T_655) @[Cat.scala 29:58] + node sbr8d = cat(_T_657, _T_654) @[Cat.scala 29:58] + node _T_658 = bits(io.in, 5, 5) @[el2_ifu_compress_ctl.scala 64:27] + node _T_659 = bits(io.in, 12, 10) @[el2_ifu_compress_ctl.scala 64:37] + node _T_660 = bits(io.in, 6, 6) @[el2_ifu_compress_ctl.scala 64:51] + node _T_661 = cat(_T_658, _T_659) @[Cat.scala 29:58] + node uswimm6d = cat(_T_661, _T_660) @[Cat.scala 29:58] + node _T_662 = bits(io.in, 8, 7) @[el2_ifu_compress_ctl.scala 65:29] + node _T_663 = bits(io.in, 12, 9) @[el2_ifu_compress_ctl.scala 65:41] + node uswspimm7d = cat(_T_662, _T_663) @[Cat.scala 29:58] + node _T_664 = bits(io.in, 14, 14) @[el2_ifu_compress_ctl.scala 67:21] + node _T_665 = eq(_T_664, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 67:15] + node _T_666 = bits(io.in, 6, 6) @[el2_ifu_compress_ctl.scala 67:32] + node _T_667 = and(_T_665, _T_666) @[el2_ifu_compress_ctl.scala 67:26] + node _T_668 = bits(io.in, 1, 1) @[el2_ifu_compress_ctl.scala 67:41] + node _T_669 = and(_T_667, _T_668) @[el2_ifu_compress_ctl.scala 67:35] + node _T_670 = bits(io.in, 15, 15) @[el2_ifu_compress_ctl.scala 67:54] + node _T_671 = eq(_T_670, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 67:48] + node _T_672 = bits(io.in, 14, 14) @[el2_ifu_compress_ctl.scala 67:65] + node _T_673 = and(_T_671, _T_672) @[el2_ifu_compress_ctl.scala 67:59] + node _T_674 = bits(io.in, 11, 11) @[el2_ifu_compress_ctl.scala 67:75] + node _T_675 = and(_T_673, _T_674) @[el2_ifu_compress_ctl.scala 67:69] + node _T_676 = bits(io.in, 0, 0) @[el2_ifu_compress_ctl.scala 67:85] + node _T_677 = and(_T_675, _T_676) @[el2_ifu_compress_ctl.scala 67:79] + node _T_678 = or(_T_669, _T_677) @[el2_ifu_compress_ctl.scala 67:45] + node _T_679 = bits(io.in, 14, 14) @[el2_ifu_compress_ctl.scala 67:98] + node _T_680 = eq(_T_679, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 67:92] + node _T_681 = bits(io.in, 5, 5) @[el2_ifu_compress_ctl.scala 67:109] + node _T_682 = and(_T_680, _T_681) @[el2_ifu_compress_ctl.scala 67:103] + node _T_683 = bits(io.in, 1, 1) @[el2_ifu_compress_ctl.scala 67:118] + node _T_684 = and(_T_682, _T_683) @[el2_ifu_compress_ctl.scala 67:112] + node _T_685 = or(_T_678, _T_684) @[el2_ifu_compress_ctl.scala 67:89] + node _T_686 = bits(io.in, 14, 14) @[el2_ifu_compress_ctl.scala 68:12] + node _T_687 = eq(_T_686, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 68:6] + node _T_688 = bits(io.in, 5, 5) @[el2_ifu_compress_ctl.scala 68:23] + node _T_689 = and(_T_687, _T_688) @[el2_ifu_compress_ctl.scala 68:17] + node _T_690 = bits(io.in, 1, 1) @[el2_ifu_compress_ctl.scala 68:32] + node _T_691 = and(_T_689, _T_690) @[el2_ifu_compress_ctl.scala 68:26] + node _T_692 = or(_T_685, _T_691) @[el2_ifu_compress_ctl.scala 67:122] + node _T_693 = bits(io.in, 15, 15) @[el2_ifu_compress_ctl.scala 68:45] + node _T_694 = eq(_T_693, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 68:39] + node _T_695 = bits(io.in, 14, 14) @[el2_ifu_compress_ctl.scala 68:56] + node _T_696 = and(_T_694, _T_695) @[el2_ifu_compress_ctl.scala 68:50] + node _T_697 = bits(io.in, 10, 10) @[el2_ifu_compress_ctl.scala 68:66] + node _T_698 = and(_T_696, _T_697) @[el2_ifu_compress_ctl.scala 68:60] + node _T_699 = bits(io.in, 0, 0) @[el2_ifu_compress_ctl.scala 68:76] + node _T_700 = and(_T_698, _T_699) @[el2_ifu_compress_ctl.scala 68:70] + node _T_701 = or(_T_692, _T_700) @[el2_ifu_compress_ctl.scala 68:36] + node _T_702 = bits(io.in, 14, 14) @[el2_ifu_compress_ctl.scala 68:89] + node _T_703 = eq(_T_702, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 68:83] + node _T_704 = bits(io.in, 4, 4) @[el2_ifu_compress_ctl.scala 68:100] + node _T_705 = and(_T_703, _T_704) @[el2_ifu_compress_ctl.scala 68:94] + node _T_706 = bits(io.in, 1, 1) @[el2_ifu_compress_ctl.scala 68:109] + node _T_707 = and(_T_705, _T_706) @[el2_ifu_compress_ctl.scala 68:103] + node _T_708 = or(_T_701, _T_707) @[el2_ifu_compress_ctl.scala 68:80] + node _T_709 = bits(io.in, 15, 15) @[el2_ifu_compress_ctl.scala 69:12] + node _T_710 = eq(_T_709, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 69:6] + node _T_711 = bits(io.in, 14, 14) @[el2_ifu_compress_ctl.scala 69:23] + node _T_712 = and(_T_710, _T_711) @[el2_ifu_compress_ctl.scala 69:17] + node _T_713 = bits(io.in, 9, 9) @[el2_ifu_compress_ctl.scala 69:33] + node _T_714 = and(_T_712, _T_713) @[el2_ifu_compress_ctl.scala 69:27] + node _T_715 = bits(io.in, 0, 0) @[el2_ifu_compress_ctl.scala 69:42] + node _T_716 = and(_T_714, _T_715) @[el2_ifu_compress_ctl.scala 69:36] + node _T_717 = or(_T_708, _T_716) @[el2_ifu_compress_ctl.scala 68:113] + node _T_718 = bits(io.in, 14, 14) @[el2_ifu_compress_ctl.scala 69:55] + node _T_719 = eq(_T_718, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 69:49] + node _T_720 = bits(io.in, 3, 3) @[el2_ifu_compress_ctl.scala 69:66] + node _T_721 = and(_T_719, _T_720) @[el2_ifu_compress_ctl.scala 69:60] + node _T_722 = bits(io.in, 1, 1) @[el2_ifu_compress_ctl.scala 69:75] + node _T_723 = and(_T_721, _T_722) @[el2_ifu_compress_ctl.scala 69:69] + node _T_724 = or(_T_717, _T_723) @[el2_ifu_compress_ctl.scala 69:46] + node _T_725 = bits(io.in, 15, 15) @[el2_ifu_compress_ctl.scala 69:88] + node _T_726 = eq(_T_725, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 69:82] + node _T_727 = bits(io.in, 14, 14) @[el2_ifu_compress_ctl.scala 69:99] + node _T_728 = and(_T_726, _T_727) @[el2_ifu_compress_ctl.scala 69:93] + node _T_729 = bits(io.in, 8, 8) @[el2_ifu_compress_ctl.scala 69:111] + node _T_730 = eq(_T_729, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 69:105] + node _T_731 = and(_T_728, _T_730) @[el2_ifu_compress_ctl.scala 69:103] + node _T_732 = bits(io.in, 0, 0) @[el2_ifu_compress_ctl.scala 69:121] + node _T_733 = and(_T_731, _T_732) @[el2_ifu_compress_ctl.scala 69:115] + node _T_734 = or(_T_724, _T_733) @[el2_ifu_compress_ctl.scala 69:79] + node _T_735 = bits(io.in, 14, 14) @[el2_ifu_compress_ctl.scala 70:12] + node _T_736 = eq(_T_735, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 70:6] + node _T_737 = bits(io.in, 2, 2) @[el2_ifu_compress_ctl.scala 70:23] + node _T_738 = and(_T_736, _T_737) @[el2_ifu_compress_ctl.scala 70:17] + node _T_739 = bits(io.in, 1, 1) @[el2_ifu_compress_ctl.scala 70:32] + node _T_740 = and(_T_738, _T_739) @[el2_ifu_compress_ctl.scala 70:26] + node _T_741 = or(_T_734, _T_740) @[el2_ifu_compress_ctl.scala 69:125] + node _T_742 = bits(io.in, 15, 15) @[el2_ifu_compress_ctl.scala 70:45] + node _T_743 = eq(_T_742, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 70:39] + node _T_744 = bits(io.in, 14, 14) @[el2_ifu_compress_ctl.scala 70:56] + node _T_745 = and(_T_743, _T_744) @[el2_ifu_compress_ctl.scala 70:50] + node _T_746 = bits(io.in, 7, 7) @[el2_ifu_compress_ctl.scala 70:66] + node _T_747 = and(_T_745, _T_746) @[el2_ifu_compress_ctl.scala 70:60] + node _T_748 = bits(io.in, 0, 0) @[el2_ifu_compress_ctl.scala 70:75] + node _T_749 = and(_T_747, _T_748) @[el2_ifu_compress_ctl.scala 70:69] + node _T_750 = or(_T_741, _T_749) @[el2_ifu_compress_ctl.scala 70:36] + node _T_751 = bits(io.in, 15, 15) @[el2_ifu_compress_ctl.scala 70:88] + node _T_752 = eq(_T_751, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 70:82] + node _T_753 = bits(io.in, 1, 1) @[el2_ifu_compress_ctl.scala 70:99] + node _T_754 = and(_T_752, _T_753) @[el2_ifu_compress_ctl.scala 70:93] + node _T_755 = or(_T_750, _T_754) @[el2_ifu_compress_ctl.scala 70:79] + node _T_756 = bits(io.in, 15, 15) @[el2_ifu_compress_ctl.scala 71:12] + node _T_757 = eq(_T_756, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 71:6] + node _T_758 = bits(io.in, 13, 13) @[el2_ifu_compress_ctl.scala 71:25] + node _T_759 = eq(_T_758, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 71:19] + node _T_760 = and(_T_757, _T_759) @[el2_ifu_compress_ctl.scala 71:17] + node _T_761 = bits(io.in, 0, 0) @[el2_ifu_compress_ctl.scala 71:36] + node _T_762 = and(_T_760, _T_761) @[el2_ifu_compress_ctl.scala 71:30] + node rdrd = or(_T_755, _T_762) @[el2_ifu_compress_ctl.scala 70:103] + node _T_763 = bits(io.in, 14, 14) @[el2_ifu_compress_ctl.scala 73:22] + node _T_764 = eq(_T_763, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 73:16] + node _T_765 = bits(io.in, 12, 12) @[el2_ifu_compress_ctl.scala 73:33] + node _T_766 = and(_T_764, _T_765) @[el2_ifu_compress_ctl.scala 73:27] + node _T_767 = bits(io.in, 11, 11) @[el2_ifu_compress_ctl.scala 73:43] + node _T_768 = and(_T_766, _T_767) @[el2_ifu_compress_ctl.scala 73:37] + node _T_769 = bits(io.in, 1, 1) @[el2_ifu_compress_ctl.scala 73:53] + node _T_770 = and(_T_768, _T_769) @[el2_ifu_compress_ctl.scala 73:47] + node _T_771 = bits(io.in, 14, 14) @[el2_ifu_compress_ctl.scala 73:66] + node _T_772 = eq(_T_771, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 73:60] + node _T_773 = bits(io.in, 12, 12) @[el2_ifu_compress_ctl.scala 73:77] + node _T_774 = and(_T_772, _T_773) @[el2_ifu_compress_ctl.scala 73:71] + node _T_775 = bits(io.in, 10, 10) @[el2_ifu_compress_ctl.scala 73:87] + node _T_776 = and(_T_774, _T_775) @[el2_ifu_compress_ctl.scala 73:81] + node _T_777 = bits(io.in, 1, 1) @[el2_ifu_compress_ctl.scala 73:97] + node _T_778 = and(_T_776, _T_777) @[el2_ifu_compress_ctl.scala 73:91] + node _T_779 = or(_T_770, _T_778) @[el2_ifu_compress_ctl.scala 73:57] + node _T_780 = bits(io.in, 14, 14) @[el2_ifu_compress_ctl.scala 74:12] + node _T_781 = eq(_T_780, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 74:6] + node _T_782 = bits(io.in, 12, 12) @[el2_ifu_compress_ctl.scala 74:23] + node _T_783 = and(_T_781, _T_782) @[el2_ifu_compress_ctl.scala 74:17] + node _T_784 = bits(io.in, 9, 9) @[el2_ifu_compress_ctl.scala 74:33] + node _T_785 = and(_T_783, _T_784) @[el2_ifu_compress_ctl.scala 74:27] + node _T_786 = bits(io.in, 1, 1) @[el2_ifu_compress_ctl.scala 74:42] + node _T_787 = and(_T_785, _T_786) @[el2_ifu_compress_ctl.scala 74:36] + node _T_788 = or(_T_779, _T_787) @[el2_ifu_compress_ctl.scala 73:101] + node _T_789 = bits(io.in, 14, 14) @[el2_ifu_compress_ctl.scala 74:55] + node _T_790 = eq(_T_789, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 74:49] + node _T_791 = bits(io.in, 12, 12) @[el2_ifu_compress_ctl.scala 74:66] + node _T_792 = and(_T_790, _T_791) @[el2_ifu_compress_ctl.scala 74:60] + node _T_793 = bits(io.in, 8, 8) @[el2_ifu_compress_ctl.scala 74:76] + node _T_794 = and(_T_792, _T_793) @[el2_ifu_compress_ctl.scala 74:70] + node _T_795 = bits(io.in, 1, 1) @[el2_ifu_compress_ctl.scala 74:85] + node _T_796 = and(_T_794, _T_795) @[el2_ifu_compress_ctl.scala 74:79] + node _T_797 = or(_T_788, _T_796) @[el2_ifu_compress_ctl.scala 74:46] + node _T_798 = bits(io.in, 14, 14) @[el2_ifu_compress_ctl.scala 75:12] + node _T_799 = eq(_T_798, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 75:6] + node _T_800 = bits(io.in, 12, 12) @[el2_ifu_compress_ctl.scala 75:23] + node _T_801 = and(_T_799, _T_800) @[el2_ifu_compress_ctl.scala 75:17] + node _T_802 = bits(io.in, 7, 7) @[el2_ifu_compress_ctl.scala 75:33] + node _T_803 = and(_T_801, _T_802) @[el2_ifu_compress_ctl.scala 75:27] + node _T_804 = bits(io.in, 1, 1) @[el2_ifu_compress_ctl.scala 75:42] + node _T_805 = and(_T_803, _T_804) @[el2_ifu_compress_ctl.scala 75:36] + node _T_806 = or(_T_797, _T_805) @[el2_ifu_compress_ctl.scala 74:89] + node _T_807 = bits(io.in, 14, 14) @[el2_ifu_compress_ctl.scala 76:12] + node _T_808 = eq(_T_807, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 76:6] + node _T_809 = bits(io.in, 12, 12) @[el2_ifu_compress_ctl.scala 76:25] + node _T_810 = eq(_T_809, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 76:19] + node _T_811 = and(_T_808, _T_810) @[el2_ifu_compress_ctl.scala 76:17] + node _T_812 = bits(io.in, 6, 6) @[el2_ifu_compress_ctl.scala 76:38] + node _T_813 = eq(_T_812, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 76:32] + node _T_814 = and(_T_811, _T_813) @[el2_ifu_compress_ctl.scala 76:30] + node _T_815 = bits(io.in, 5, 5) @[el2_ifu_compress_ctl.scala 76:50] + node _T_816 = eq(_T_815, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 76:44] + node _T_817 = and(_T_814, _T_816) @[el2_ifu_compress_ctl.scala 76:42] + node _T_818 = bits(io.in, 4, 4) @[el2_ifu_compress_ctl.scala 76:62] + node _T_819 = eq(_T_818, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 76:56] + node _T_820 = and(_T_817, _T_819) @[el2_ifu_compress_ctl.scala 76:54] + node _T_821 = bits(io.in, 3, 3) @[el2_ifu_compress_ctl.scala 76:74] + node _T_822 = eq(_T_821, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 76:68] + node _T_823 = and(_T_820, _T_822) @[el2_ifu_compress_ctl.scala 76:66] + node _T_824 = bits(io.in, 2, 2) @[el2_ifu_compress_ctl.scala 76:86] + node _T_825 = eq(_T_824, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 76:80] + node _T_826 = and(_T_823, _T_825) @[el2_ifu_compress_ctl.scala 76:78] + node _T_827 = bits(io.in, 1, 1) @[el2_ifu_compress_ctl.scala 76:96] + node _T_828 = and(_T_826, _T_827) @[el2_ifu_compress_ctl.scala 76:90] + node _T_829 = or(_T_806, _T_828) @[el2_ifu_compress_ctl.scala 75:46] + node _T_830 = bits(io.in, 14, 14) @[el2_ifu_compress_ctl.scala 77:12] + node _T_831 = eq(_T_830, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 77:6] + node _T_832 = bits(io.in, 12, 12) @[el2_ifu_compress_ctl.scala 77:23] + node _T_833 = and(_T_831, _T_832) @[el2_ifu_compress_ctl.scala 77:17] + node _T_834 = bits(io.in, 6, 6) @[el2_ifu_compress_ctl.scala 77:33] + node _T_835 = and(_T_833, _T_834) @[el2_ifu_compress_ctl.scala 77:27] + node _T_836 = bits(io.in, 1, 1) @[el2_ifu_compress_ctl.scala 77:42] + node _T_837 = and(_T_835, _T_836) @[el2_ifu_compress_ctl.scala 77:36] + node _T_838 = or(_T_829, _T_837) @[el2_ifu_compress_ctl.scala 76:100] + node _T_839 = bits(io.in, 14, 14) @[el2_ifu_compress_ctl.scala 77:55] + node _T_840 = eq(_T_839, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 77:49] + node _T_841 = bits(io.in, 12, 12) @[el2_ifu_compress_ctl.scala 77:66] + node _T_842 = and(_T_840, _T_841) @[el2_ifu_compress_ctl.scala 77:60] + node _T_843 = bits(io.in, 5, 5) @[el2_ifu_compress_ctl.scala 77:76] + node _T_844 = and(_T_842, _T_843) @[el2_ifu_compress_ctl.scala 77:70] + node _T_845 = bits(io.in, 1, 1) @[el2_ifu_compress_ctl.scala 77:85] + node _T_846 = and(_T_844, _T_845) @[el2_ifu_compress_ctl.scala 77:79] + node _T_847 = or(_T_838, _T_846) @[el2_ifu_compress_ctl.scala 77:46] + node _T_848 = bits(io.in, 14, 14) @[el2_ifu_compress_ctl.scala 78:12] + node _T_849 = eq(_T_848, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 78:6] + node _T_850 = bits(io.in, 12, 12) @[el2_ifu_compress_ctl.scala 78:23] + node _T_851 = and(_T_849, _T_850) @[el2_ifu_compress_ctl.scala 78:17] + node _T_852 = bits(io.in, 4, 4) @[el2_ifu_compress_ctl.scala 78:33] + node _T_853 = and(_T_851, _T_852) @[el2_ifu_compress_ctl.scala 78:27] + node _T_854 = bits(io.in, 1, 1) @[el2_ifu_compress_ctl.scala 78:42] + node _T_855 = and(_T_853, _T_854) @[el2_ifu_compress_ctl.scala 78:36] + node _T_856 = or(_T_847, _T_855) @[el2_ifu_compress_ctl.scala 77:89] + node _T_857 = bits(io.in, 14, 14) @[el2_ifu_compress_ctl.scala 78:55] + node _T_858 = eq(_T_857, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 78:49] + node _T_859 = bits(io.in, 12, 12) @[el2_ifu_compress_ctl.scala 78:66] + node _T_860 = and(_T_858, _T_859) @[el2_ifu_compress_ctl.scala 78:60] + node _T_861 = bits(io.in, 3, 3) @[el2_ifu_compress_ctl.scala 78:76] + node _T_862 = and(_T_860, _T_861) @[el2_ifu_compress_ctl.scala 78:70] + node _T_863 = bits(io.in, 1, 1) @[el2_ifu_compress_ctl.scala 78:85] + node _T_864 = and(_T_862, _T_863) @[el2_ifu_compress_ctl.scala 78:79] + node _T_865 = or(_T_856, _T_864) @[el2_ifu_compress_ctl.scala 78:46] + node _T_866 = bits(io.in, 14, 14) @[el2_ifu_compress_ctl.scala 79:12] + node _T_867 = eq(_T_866, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 79:6] + node _T_868 = bits(io.in, 12, 12) @[el2_ifu_compress_ctl.scala 79:23] + node _T_869 = and(_T_867, _T_868) @[el2_ifu_compress_ctl.scala 79:17] + node _T_870 = bits(io.in, 2, 2) @[el2_ifu_compress_ctl.scala 79:33] + node _T_871 = and(_T_869, _T_870) @[el2_ifu_compress_ctl.scala 79:27] + node _T_872 = bits(io.in, 1, 1) @[el2_ifu_compress_ctl.scala 79:42] + node _T_873 = and(_T_871, _T_872) @[el2_ifu_compress_ctl.scala 79:36] + node _T_874 = or(_T_865, _T_873) @[el2_ifu_compress_ctl.scala 78:89] + node _T_875 = bits(io.in, 15, 15) @[el2_ifu_compress_ctl.scala 79:55] + node _T_876 = eq(_T_875, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 79:49] + node _T_877 = bits(io.in, 14, 14) @[el2_ifu_compress_ctl.scala 79:68] + node _T_878 = eq(_T_877, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 79:62] + node _T_879 = and(_T_876, _T_878) @[el2_ifu_compress_ctl.scala 79:60] + node _T_880 = bits(io.in, 13, 13) @[el2_ifu_compress_ctl.scala 79:81] + node _T_881 = eq(_T_880, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 79:75] + node _T_882 = and(_T_879, _T_881) @[el2_ifu_compress_ctl.scala 79:73] + node _T_883 = bits(io.in, 0, 0) @[el2_ifu_compress_ctl.scala 79:92] + node _T_884 = and(_T_882, _T_883) @[el2_ifu_compress_ctl.scala 79:86] + node _T_885 = or(_T_874, _T_884) @[el2_ifu_compress_ctl.scala 79:46] + node _T_886 = bits(io.in, 15, 15) @[el2_ifu_compress_ctl.scala 80:12] + node _T_887 = eq(_T_886, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 80:6] + node _T_888 = bits(io.in, 14, 14) @[el2_ifu_compress_ctl.scala 80:25] + node _T_889 = eq(_T_888, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 80:19] + node _T_890 = and(_T_887, _T_889) @[el2_ifu_compress_ctl.scala 80:17] + node _T_891 = bits(io.in, 1, 1) @[el2_ifu_compress_ctl.scala 80:36] + node _T_892 = and(_T_890, _T_891) @[el2_ifu_compress_ctl.scala 80:30] + node rdrs1 = or(_T_885, _T_892) @[el2_ifu_compress_ctl.scala 79:96] + node _T_893 = bits(io.in, 15, 15) @[el2_ifu_compress_ctl.scala 82:21] + node _T_894 = bits(io.in, 6, 6) @[el2_ifu_compress_ctl.scala 82:31] + node _T_895 = and(_T_893, _T_894) @[el2_ifu_compress_ctl.scala 82:25] + node _T_896 = bits(io.in, 1, 1) @[el2_ifu_compress_ctl.scala 82:40] + node _T_897 = and(_T_895, _T_896) @[el2_ifu_compress_ctl.scala 82:34] + node _T_898 = bits(io.in, 15, 15) @[el2_ifu_compress_ctl.scala 82:51] + node _T_899 = bits(io.in, 5, 5) @[el2_ifu_compress_ctl.scala 82:61] + node _T_900 = and(_T_898, _T_899) @[el2_ifu_compress_ctl.scala 82:55] + node _T_901 = bits(io.in, 1, 1) @[el2_ifu_compress_ctl.scala 82:70] + node _T_902 = and(_T_900, _T_901) @[el2_ifu_compress_ctl.scala 82:64] + node _T_903 = or(_T_897, _T_902) @[el2_ifu_compress_ctl.scala 82:44] + node _T_904 = bits(io.in, 15, 15) @[el2_ifu_compress_ctl.scala 82:81] + node _T_905 = bits(io.in, 4, 4) @[el2_ifu_compress_ctl.scala 82:91] + node _T_906 = and(_T_904, _T_905) @[el2_ifu_compress_ctl.scala 82:85] + node _T_907 = bits(io.in, 1, 1) @[el2_ifu_compress_ctl.scala 82:100] + node _T_908 = and(_T_906, _T_907) @[el2_ifu_compress_ctl.scala 82:94] + node _T_909 = or(_T_903, _T_908) @[el2_ifu_compress_ctl.scala 82:74] + node _T_910 = bits(io.in, 15, 15) @[el2_ifu_compress_ctl.scala 83:10] + node _T_911 = bits(io.in, 3, 3) @[el2_ifu_compress_ctl.scala 83:20] + node _T_912 = and(_T_910, _T_911) @[el2_ifu_compress_ctl.scala 83:14] + node _T_913 = bits(io.in, 1, 1) @[el2_ifu_compress_ctl.scala 83:29] + node _T_914 = and(_T_912, _T_913) @[el2_ifu_compress_ctl.scala 83:23] + node _T_915 = or(_T_909, _T_914) @[el2_ifu_compress_ctl.scala 82:104] + node _T_916 = bits(io.in, 15, 15) @[el2_ifu_compress_ctl.scala 83:40] + node _T_917 = bits(io.in, 2, 2) @[el2_ifu_compress_ctl.scala 83:50] + node _T_918 = and(_T_916, _T_917) @[el2_ifu_compress_ctl.scala 83:44] + node _T_919 = bits(io.in, 1, 1) @[el2_ifu_compress_ctl.scala 83:59] + node _T_920 = and(_T_918, _T_919) @[el2_ifu_compress_ctl.scala 83:53] + node _T_921 = or(_T_915, _T_920) @[el2_ifu_compress_ctl.scala 83:33] + node _T_922 = bits(io.in, 15, 15) @[el2_ifu_compress_ctl.scala 83:70] + node _T_923 = bits(io.in, 14, 14) @[el2_ifu_compress_ctl.scala 83:80] + node _T_924 = and(_T_922, _T_923) @[el2_ifu_compress_ctl.scala 83:74] + node _T_925 = bits(io.in, 1, 1) @[el2_ifu_compress_ctl.scala 83:90] + node _T_926 = and(_T_924, _T_925) @[el2_ifu_compress_ctl.scala 83:84] + node rs2rs2 = or(_T_921, _T_926) @[el2_ifu_compress_ctl.scala 83:63] + node _T_927 = bits(io.in, 15, 15) @[el2_ifu_compress_ctl.scala 84:20] + node _T_928 = bits(io.in, 14, 14) @[el2_ifu_compress_ctl.scala 84:32] + node _T_929 = eq(_T_928, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 84:26] + node _T_930 = and(_T_927, _T_929) @[el2_ifu_compress_ctl.scala 84:24] + node _T_931 = bits(io.in, 13, 13) @[el2_ifu_compress_ctl.scala 84:45] + node _T_932 = eq(_T_931, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 84:39] + node _T_933 = and(_T_930, _T_932) @[el2_ifu_compress_ctl.scala 84:37] + node _T_934 = bits(io.in, 0, 0) @[el2_ifu_compress_ctl.scala 84:56] + node rdprd = and(_T_933, _T_934) @[el2_ifu_compress_ctl.scala 84:50] + node _T_935 = bits(io.in, 15, 15) @[el2_ifu_compress_ctl.scala 85:21] + node _T_936 = bits(io.in, 13, 13) @[el2_ifu_compress_ctl.scala 85:33] + node _T_937 = eq(_T_936, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 85:27] + node _T_938 = and(_T_935, _T_937) @[el2_ifu_compress_ctl.scala 85:25] + node _T_939 = bits(io.in, 0, 0) @[el2_ifu_compress_ctl.scala 85:44] + node _T_940 = and(_T_938, _T_939) @[el2_ifu_compress_ctl.scala 85:38] + node _T_941 = bits(io.in, 15, 15) @[el2_ifu_compress_ctl.scala 85:55] + node _T_942 = bits(io.in, 14, 14) @[el2_ifu_compress_ctl.scala 85:65] + node _T_943 = and(_T_941, _T_942) @[el2_ifu_compress_ctl.scala 85:59] + node _T_944 = bits(io.in, 0, 0) @[el2_ifu_compress_ctl.scala 85:75] + node _T_945 = and(_T_943, _T_944) @[el2_ifu_compress_ctl.scala 85:69] + node _T_946 = or(_T_940, _T_945) @[el2_ifu_compress_ctl.scala 85:48] + node _T_947 = bits(io.in, 14, 14) @[el2_ifu_compress_ctl.scala 85:86] + node _T_948 = bits(io.in, 1, 1) @[el2_ifu_compress_ctl.scala 85:98] + node _T_949 = eq(_T_948, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 85:92] + node _T_950 = and(_T_947, _T_949) @[el2_ifu_compress_ctl.scala 85:90] + node _T_951 = bits(io.in, 0, 0) @[el2_ifu_compress_ctl.scala 85:110] + node _T_952 = eq(_T_951, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 85:104] + node _T_953 = and(_T_950, _T_952) @[el2_ifu_compress_ctl.scala 85:102] + node rdprs1 = or(_T_946, _T_953) @[el2_ifu_compress_ctl.scala 85:79] + node _T_954 = bits(io.in, 15, 15) @[el2_ifu_compress_ctl.scala 86:22] + node _T_955 = bits(io.in, 14, 14) @[el2_ifu_compress_ctl.scala 86:34] + node _T_956 = eq(_T_955, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 86:28] + node _T_957 = and(_T_954, _T_956) @[el2_ifu_compress_ctl.scala 86:26] + node _T_958 = bits(io.in, 13, 13) @[el2_ifu_compress_ctl.scala 86:47] + node _T_959 = eq(_T_958, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 86:41] + node _T_960 = and(_T_957, _T_959) @[el2_ifu_compress_ctl.scala 86:39] + node _T_961 = bits(io.in, 11, 11) @[el2_ifu_compress_ctl.scala 86:58] + node _T_962 = and(_T_960, _T_961) @[el2_ifu_compress_ctl.scala 86:52] + node _T_963 = bits(io.in, 10, 10) @[el2_ifu_compress_ctl.scala 86:68] + node _T_964 = and(_T_962, _T_963) @[el2_ifu_compress_ctl.scala 86:62] + node _T_965 = bits(io.in, 0, 0) @[el2_ifu_compress_ctl.scala 86:78] + node _T_966 = and(_T_964, _T_965) @[el2_ifu_compress_ctl.scala 86:72] + node _T_967 = bits(io.in, 15, 15) @[el2_ifu_compress_ctl.scala 86:89] + node _T_968 = bits(io.in, 1, 1) @[el2_ifu_compress_ctl.scala 86:101] + node _T_969 = eq(_T_968, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 86:95] + node _T_970 = and(_T_967, _T_969) @[el2_ifu_compress_ctl.scala 86:93] + node _T_971 = bits(io.in, 0, 0) @[el2_ifu_compress_ctl.scala 86:113] + node _T_972 = eq(_T_971, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 86:107] + node _T_973 = and(_T_970, _T_972) @[el2_ifu_compress_ctl.scala 86:105] + node rs2prs2 = or(_T_966, _T_973) @[el2_ifu_compress_ctl.scala 86:82] + node _T_974 = bits(io.in, 15, 15) @[el2_ifu_compress_ctl.scala 87:22] + node _T_975 = eq(_T_974, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 87:16] + node _T_976 = bits(io.in, 1, 1) @[el2_ifu_compress_ctl.scala 87:34] + node _T_977 = eq(_T_976, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 87:28] + node _T_978 = and(_T_975, _T_977) @[el2_ifu_compress_ctl.scala 87:26] + node _T_979 = bits(io.in, 0, 0) @[el2_ifu_compress_ctl.scala 87:46] + node _T_980 = eq(_T_979, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 87:40] + node rs2prd = and(_T_978, _T_980) @[el2_ifu_compress_ctl.scala 87:38] + node _T_981 = bits(io.in, 14, 14) @[el2_ifu_compress_ctl.scala 88:23] + node _T_982 = eq(_T_981, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 88:17] + node _T_983 = bits(io.in, 1, 1) @[el2_ifu_compress_ctl.scala 88:35] + node _T_984 = eq(_T_983, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 88:29] + node _T_985 = and(_T_982, _T_984) @[el2_ifu_compress_ctl.scala 88:27] + node _T_986 = bits(io.in, 0, 0) @[el2_ifu_compress_ctl.scala 88:47] + node _T_987 = eq(_T_986, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 88:41] + node uimm9_2 = and(_T_985, _T_987) @[el2_ifu_compress_ctl.scala 88:39] + node _T_988 = bits(io.in, 15, 15) @[el2_ifu_compress_ctl.scala 89:25] + node _T_989 = eq(_T_988, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 89:19] + node _T_990 = bits(io.in, 14, 14) @[el2_ifu_compress_ctl.scala 89:35] + node _T_991 = and(_T_989, _T_990) @[el2_ifu_compress_ctl.scala 89:29] + node _T_992 = bits(io.in, 1, 1) @[el2_ifu_compress_ctl.scala 89:47] + node _T_993 = eq(_T_992, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 89:41] + node _T_994 = and(_T_991, _T_993) @[el2_ifu_compress_ctl.scala 89:39] + node _T_995 = bits(io.in, 0, 0) @[el2_ifu_compress_ctl.scala 89:59] + node _T_996 = eq(_T_995, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 89:53] + node ulwimm6_2 = and(_T_994, _T_996) @[el2_ifu_compress_ctl.scala 89:51] + node _T_997 = bits(io.in, 15, 15) @[el2_ifu_compress_ctl.scala 90:27] + node _T_998 = eq(_T_997, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 90:21] + node _T_999 = bits(io.in, 14, 14) @[el2_ifu_compress_ctl.scala 90:37] + node _T_1000 = and(_T_998, _T_999) @[el2_ifu_compress_ctl.scala 90:31] + node _T_1001 = bits(io.in, 1, 1) @[el2_ifu_compress_ctl.scala 90:47] + node ulwspimm7_2 = and(_T_1000, _T_1001) @[el2_ifu_compress_ctl.scala 90:41] + node _T_1002 = bits(io.in, 15, 15) @[el2_ifu_compress_ctl.scala 91:22] + node _T_1003 = eq(_T_1002, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 91:16] + node _T_1004 = bits(io.in, 14, 14) @[el2_ifu_compress_ctl.scala 91:33] + node _T_1005 = and(_T_1003, _T_1004) @[el2_ifu_compress_ctl.scala 91:27] + node _T_1006 = bits(io.in, 13, 13) @[el2_ifu_compress_ctl.scala 91:43] + node _T_1007 = and(_T_1005, _T_1006) @[el2_ifu_compress_ctl.scala 91:37] + node _T_1008 = bits(io.in, 11, 11) @[el2_ifu_compress_ctl.scala 91:55] + node _T_1009 = eq(_T_1008, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 91:49] + node _T_1010 = and(_T_1007, _T_1009) @[el2_ifu_compress_ctl.scala 91:47] + node _T_1011 = bits(io.in, 10, 10) @[el2_ifu_compress_ctl.scala 91:68] + node _T_1012 = eq(_T_1011, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 91:62] + node _T_1013 = and(_T_1010, _T_1012) @[el2_ifu_compress_ctl.scala 91:60] + node _T_1014 = bits(io.in, 9, 9) @[el2_ifu_compress_ctl.scala 91:81] + node _T_1015 = eq(_T_1014, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 91:75] + node _T_1016 = and(_T_1013, _T_1015) @[el2_ifu_compress_ctl.scala 91:73] + node _T_1017 = bits(io.in, 9, 9) @[el2_ifu_compress_ctl.scala 91:91] + node _T_1018 = and(_T_1016, _T_1017) @[el2_ifu_compress_ctl.scala 91:85] + node _T_1019 = bits(io.in, 7, 7) @[el2_ifu_compress_ctl.scala 91:102] + node _T_1020 = eq(_T_1019, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 91:96] + node rdeq2 = and(_T_1018, _T_1020) @[el2_ifu_compress_ctl.scala 91:94] + io.out <= o @[el2_ifu_compress_ctl.scala 111:10] + diff --git a/el2_ifu_compress_ctl.v b/el2_ifu_compress_ctl.v new file mode 100644 index 00000000..13f07c2c --- /dev/null +++ b/el2_ifu_compress_ctl.v @@ -0,0 +1,187 @@ +module el2_ifu_compress_ctl( + input clock, + input reset, + input [15:0] io_in, + output [31:0] io_out +); + wire _T_4 = ~io_in[14]; // @[el2_ifu_compress_ctl.scala 18:34] + wire _T_5 = io_in[15] & _T_4; // @[el2_ifu_compress_ctl.scala 18:32] + wire _T_7 = ~io_in[13]; // @[el2_ifu_compress_ctl.scala 18:47] + wire _T_8 = _T_5 & _T_7; // @[el2_ifu_compress_ctl.scala 18:45] + wire _T_10 = _T_8 & io_in[10]; // @[el2_ifu_compress_ctl.scala 18:58] + wire _T_12 = ~io_in[6]; // @[el2_ifu_compress_ctl.scala 18:70] + wire _T_13 = _T_10 & _T_12; // @[el2_ifu_compress_ctl.scala 18:68] + wire _T_15 = ~io_in[5]; // @[el2_ifu_compress_ctl.scala 18:82] + wire _T_16 = _T_13 & _T_15; // @[el2_ifu_compress_ctl.scala 18:80] + wire _T_18 = _T_16 & io_in[0]; // @[el2_ifu_compress_ctl.scala 18:92] + wire _T_22 = io_in[14] & _T_4; // @[el2_ifu_compress_ctl.scala 19:27] + wire _T_25 = _T_22 & _T_7; // @[el2_ifu_compress_ctl.scala 19:40] + wire _T_27 = ~io_in[11]; // @[el2_ifu_compress_ctl.scala 19:55] + wire _T_28 = _T_25 & _T_27; // @[el2_ifu_compress_ctl.scala 19:53] + wire _T_30 = _T_28 & io_in[10]; // @[el2_ifu_compress_ctl.scala 19:66] + wire _T_32 = _T_30 & io_in[0]; // @[el2_ifu_compress_ctl.scala 19:76] + wire _T_33 = _T_18 | _T_32; // @[el2_ifu_compress_ctl.scala 19:15] + wire _T_38 = _T_4 & io_in[12]; // @[el2_ifu_compress_ctl.scala 20:25] + wire _T_41 = _T_38 & _T_27; // @[el2_ifu_compress_ctl.scala 20:35] + wire _T_43 = ~io_in[10]; // @[el2_ifu_compress_ctl.scala 20:50] + wire _T_44 = _T_41 & _T_43; // @[el2_ifu_compress_ctl.scala 20:48] + wire _T_46 = ~io_in[9]; // @[el2_ifu_compress_ctl.scala 20:63] + wire _T_47 = _T_44 & _T_46; // @[el2_ifu_compress_ctl.scala 20:61] + wire _T_49 = ~io_in[8]; // @[el2_ifu_compress_ctl.scala 20:75] + wire _T_50 = _T_47 & _T_49; // @[el2_ifu_compress_ctl.scala 20:73] + wire _T_52 = ~io_in[7]; // @[el2_ifu_compress_ctl.scala 20:87] + wire _T_53 = _T_50 & _T_52; // @[el2_ifu_compress_ctl.scala 20:85] + wire _T_56 = _T_53 & _T_12; // @[el2_ifu_compress_ctl.scala 20:97] + wire _T_59 = _T_56 & _T_15; // @[el2_ifu_compress_ctl.scala 20:109] + wire _T_61 = ~io_in[4]; // @[el2_ifu_compress_ctl.scala 21:16] + wire _T_62 = _T_59 & _T_61; // @[el2_ifu_compress_ctl.scala 20:121] + wire _T_64 = ~io_in[3]; // @[el2_ifu_compress_ctl.scala 21:28] + wire _T_65 = _T_62 & _T_64; // @[el2_ifu_compress_ctl.scala 21:26] + wire _T_67 = ~io_in[2]; // @[el2_ifu_compress_ctl.scala 21:40] + wire _T_68 = _T_65 & _T_67; // @[el2_ifu_compress_ctl.scala 21:38] + wire _T_70 = _T_68 & io_in[1]; // @[el2_ifu_compress_ctl.scala 21:50] + wire _T_81 = _T_8 & _T_27; // @[el2_ifu_compress_ctl.scala 22:50] + wire _T_83 = _T_81 & io_in[0]; // @[el2_ifu_compress_ctl.scala 22:63] + wire _T_93 = _T_8 & _T_43; // @[el2_ifu_compress_ctl.scala 23:51] + wire _T_95 = _T_93 & io_in[0]; // @[el2_ifu_compress_ctl.scala 23:64] + wire _T_96 = _T_83 | _T_95; // @[el2_ifu_compress_ctl.scala 23:15] + wire _T_105 = _T_8 & io_in[6]; // @[el2_ifu_compress_ctl.scala 24:51] + wire _T_107 = _T_105 & io_in[0]; // @[el2_ifu_compress_ctl.scala 24:60] + wire _T_108 = _T_96 | _T_107; // @[el2_ifu_compress_ctl.scala 24:15] + wire _T_117 = _T_8 & io_in[5]; // @[el2_ifu_compress_ctl.scala 25:51] + wire _T_119 = _T_117 & io_in[0]; // @[el2_ifu_compress_ctl.scala 25:60] + wire _T_120 = _T_108 | _T_119; // @[el2_ifu_compress_ctl.scala 25:15] + wire _T_131 = _T_105 & io_in[5]; // @[el2_ifu_compress_ctl.scala 26:59] + wire _T_133 = _T_131 & io_in[0]; // @[el2_ifu_compress_ctl.scala 26:68] + wire _T_146 = _T_133 | _T_83; // @[el2_ifu_compress_ctl.scala 27:15] + wire _T_159 = _T_146 | _T_95; // @[el2_ifu_compress_ctl.scala 28:15] + wire _T_161 = ~io_in[15]; // @[el2_ifu_compress_ctl.scala 29:17] + wire _T_164 = _T_161 & _T_4; // @[el2_ifu_compress_ctl.scala 29:28] + wire _T_166 = _T_164 & io_in[1]; // @[el2_ifu_compress_ctl.scala 29:41] + wire _T_167 = _T_159 | _T_166; // @[el2_ifu_compress_ctl.scala 29:15] + wire _T_170 = io_in[15] & io_in[14]; // @[el2_ifu_compress_ctl.scala 29:62] + wire _T_172 = _T_170 & io_in[13]; // @[el2_ifu_compress_ctl.scala 29:72] + wire _T_173 = _T_167 | _T_172; // @[el2_ifu_compress_ctl.scala 29:51] + wire _T_234 = _T_5 & _T_12; // @[el2_ifu_compress_ctl.scala 34:37] + wire _T_237 = _T_234 & _T_15; // @[el2_ifu_compress_ctl.scala 34:49] + wire _T_240 = _T_237 & _T_61; // @[el2_ifu_compress_ctl.scala 34:61] + wire _T_243 = _T_240 & _T_64; // @[el2_ifu_compress_ctl.scala 34:73] + wire _T_246 = _T_243 & _T_67; // @[el2_ifu_compress_ctl.scala 34:85] + wire _T_248 = ~io_in[0]; // @[el2_ifu_compress_ctl.scala 34:99] + wire _T_249 = _T_246 & _T_248; // @[el2_ifu_compress_ctl.scala 34:97] + wire _T_253 = _T_4 & io_in[13]; // @[el2_ifu_compress_ctl.scala 35:28] + wire _T_254 = _T_249 | _T_253; // @[el2_ifu_compress_ctl.scala 35:15] + wire _T_259 = _T_170 & io_in[0]; // @[el2_ifu_compress_ctl.scala 35:60] + wire _T_260 = _T_254 | _T_259; // @[el2_ifu_compress_ctl.scala 35:39] + wire _T_264 = io_in[15] & _T_248; // @[el2_ifu_compress_ctl.scala 35:80] + wire _T_267 = io_in[15] & io_in[11]; // @[el2_ifu_compress_ctl.scala 36:25] + wire _T_269 = _T_267 & io_in[10]; // @[el2_ifu_compress_ctl.scala 36:35] + wire _T_270 = _T_264 | _T_269; // @[el2_ifu_compress_ctl.scala 36:15] + wire _T_274 = io_in[13] & _T_49; // @[el2_ifu_compress_ctl.scala 36:57] + wire _T_275 = _T_270 | _T_274; // @[el2_ifu_compress_ctl.scala 36:46] + wire _T_280 = _T_275 | _T_274; // @[el2_ifu_compress_ctl.scala 37:15] + wire _T_283 = io_in[13] & io_in[7]; // @[el2_ifu_compress_ctl.scala 37:47] + wire _T_284 = _T_280 | _T_283; // @[el2_ifu_compress_ctl.scala 37:37] + wire _T_287 = io_in[13] & io_in[9]; // @[el2_ifu_compress_ctl.scala 37:66] + wire _T_288 = _T_284 | _T_287; // @[el2_ifu_compress_ctl.scala 37:56] + wire _T_291 = io_in[13] & io_in[10]; // @[el2_ifu_compress_ctl.scala 37:85] + wire _T_292 = _T_288 | _T_291; // @[el2_ifu_compress_ctl.scala 37:75] + wire _T_295 = io_in[13] & io_in[11]; // @[el2_ifu_compress_ctl.scala 38:25] + wire _T_296 = _T_292 | _T_295; // @[el2_ifu_compress_ctl.scala 38:15] + wire _T_300 = io_in[13] & _T_4; // @[el2_ifu_compress_ctl.scala 38:45] + wire _T_301 = _T_296 | _T_300; // @[el2_ifu_compress_ctl.scala 38:35] + wire _T_304 = io_in[14] & io_in[15]; // @[el2_ifu_compress_ctl.scala 38:68] + wire _T_305 = _T_301 | _T_304; // @[el2_ifu_compress_ctl.scala 38:58] + wire _T_310 = _T_4 & _T_27; // @[el2_ifu_compress_ctl.scala 39:25] + wire _T_313 = _T_310 & _T_43; // @[el2_ifu_compress_ctl.scala 39:38] + wire _T_316 = _T_313 & _T_46; // @[el2_ifu_compress_ctl.scala 39:51] + wire _T_319 = _T_316 & _T_49; // @[el2_ifu_compress_ctl.scala 39:63] + wire _T_322 = _T_319 & _T_52; // @[el2_ifu_compress_ctl.scala 39:75] + wire _T_325 = _T_322 & _T_248; // @[el2_ifu_compress_ctl.scala 39:87] + wire _T_333 = _T_164 & _T_248; // @[el2_ifu_compress_ctl.scala 40:41] + wire _T_334 = _T_325 | _T_333; // @[el2_ifu_compress_ctl.scala 40:15] + wire _T_338 = _T_4 & io_in[6]; // @[el2_ifu_compress_ctl.scala 40:66] + wire _T_341 = _T_338 & _T_248; // @[el2_ifu_compress_ctl.scala 40:75] + wire _T_342 = _T_334 | _T_341; // @[el2_ifu_compress_ctl.scala 40:53] + wire _T_346 = _T_161 & io_in[14]; // @[el2_ifu_compress_ctl.scala 41:28] + wire _T_348 = _T_346 & io_in[0]; // @[el2_ifu_compress_ctl.scala 41:38] + wire _T_349 = _T_342 | _T_348; // @[el2_ifu_compress_ctl.scala 41:15] + wire _T_353 = _T_4 & io_in[5]; // @[el2_ifu_compress_ctl.scala 41:60] + wire _T_356 = _T_353 & _T_248; // @[el2_ifu_compress_ctl.scala 41:69] + wire _T_357 = _T_349 | _T_356; // @[el2_ifu_compress_ctl.scala 41:47] + wire _T_361 = _T_4 & io_in[4]; // @[el2_ifu_compress_ctl.scala 42:28] + wire _T_364 = _T_361 & _T_248; // @[el2_ifu_compress_ctl.scala 42:37] + wire _T_365 = _T_357 | _T_364; // @[el2_ifu_compress_ctl.scala 42:15] + wire _T_370 = _T_4 & _T_7; // @[el2_ifu_compress_ctl.scala 42:64] + wire _T_372 = _T_370 & io_in[0]; // @[el2_ifu_compress_ctl.scala 42:77] + wire _T_373 = _T_365 | _T_372; // @[el2_ifu_compress_ctl.scala 42:50] + wire _T_377 = _T_4 & io_in[3]; // @[el2_ifu_compress_ctl.scala 43:28] + wire _T_380 = _T_377 & _T_248; // @[el2_ifu_compress_ctl.scala 43:37] + wire _T_381 = _T_373 | _T_380; // @[el2_ifu_compress_ctl.scala 43:15] + wire _T_385 = _T_4 & io_in[2]; // @[el2_ifu_compress_ctl.scala 43:64] + wire _T_388 = _T_385 & _T_248; // @[el2_ifu_compress_ctl.scala 43:73] + wire _T_389 = _T_381 | _T_388; // @[el2_ifu_compress_ctl.scala 43:50] + wire _T_399 = _T_38 & io_in[11]; // @[el2_ifu_compress_ctl.scala 45:35] + wire _T_402 = _T_399 & _T_12; // @[el2_ifu_compress_ctl.scala 45:45] + wire _T_405 = _T_402 & _T_15; // @[el2_ifu_compress_ctl.scala 45:57] + wire _T_408 = _T_405 & _T_61; // @[el2_ifu_compress_ctl.scala 45:69] + wire _T_411 = _T_408 & _T_64; // @[el2_ifu_compress_ctl.scala 45:81] + wire _T_414 = _T_411 & _T_67; // @[el2_ifu_compress_ctl.scala 45:93] + wire _T_416 = _T_414 & io_in[1]; // @[el2_ifu_compress_ctl.scala 45:105] + wire _T_422 = _T_38 & io_in[10]; // @[el2_ifu_compress_ctl.scala 46:38] + wire _T_425 = _T_422 & _T_12; // @[el2_ifu_compress_ctl.scala 46:48] + wire _T_428 = _T_425 & _T_15; // @[el2_ifu_compress_ctl.scala 46:60] + wire _T_431 = _T_428 & _T_61; // @[el2_ifu_compress_ctl.scala 46:72] + wire _T_434 = _T_431 & _T_64; // @[el2_ifu_compress_ctl.scala 46:84] + wire _T_437 = _T_434 & _T_67; // @[el2_ifu_compress_ctl.scala 46:96] + wire _T_439 = _T_437 & io_in[1]; // @[el2_ifu_compress_ctl.scala 46:108] + wire _T_440 = _T_416 | _T_439; // @[el2_ifu_compress_ctl.scala 46:15] + wire _T_446 = _T_38 & io_in[9]; // @[el2_ifu_compress_ctl.scala 47:38] + wire _T_449 = _T_446 & _T_12; // @[el2_ifu_compress_ctl.scala 47:47] + wire _T_452 = _T_449 & _T_15; // @[el2_ifu_compress_ctl.scala 47:59] + wire _T_455 = _T_452 & _T_61; // @[el2_ifu_compress_ctl.scala 47:71] + wire _T_458 = _T_455 & _T_64; // @[el2_ifu_compress_ctl.scala 47:83] + wire _T_461 = _T_458 & _T_67; // @[el2_ifu_compress_ctl.scala 47:95] + wire _T_463 = _T_461 & io_in[1]; // @[el2_ifu_compress_ctl.scala 47:107] + wire _T_464 = _T_440 | _T_463; // @[el2_ifu_compress_ctl.scala 47:15] + wire _T_470 = _T_38 & io_in[8]; // @[el2_ifu_compress_ctl.scala 48:38] + wire _T_473 = _T_470 & _T_12; // @[el2_ifu_compress_ctl.scala 48:47] + wire _T_476 = _T_473 & _T_15; // @[el2_ifu_compress_ctl.scala 48:59] + wire _T_479 = _T_476 & _T_61; // @[el2_ifu_compress_ctl.scala 48:71] + wire _T_482 = _T_479 & _T_64; // @[el2_ifu_compress_ctl.scala 48:83] + wire _T_485 = _T_482 & _T_67; // @[el2_ifu_compress_ctl.scala 48:95] + wire _T_487 = _T_485 & io_in[1]; // @[el2_ifu_compress_ctl.scala 48:107] + wire _T_488 = _T_464 | _T_487; // @[el2_ifu_compress_ctl.scala 48:15] + wire _T_494 = _T_38 & io_in[7]; // @[el2_ifu_compress_ctl.scala 49:38] + wire _T_497 = _T_494 & _T_12; // @[el2_ifu_compress_ctl.scala 49:47] + wire _T_500 = _T_497 & _T_15; // @[el2_ifu_compress_ctl.scala 49:59] + wire _T_503 = _T_500 & _T_61; // @[el2_ifu_compress_ctl.scala 49:71] + wire _T_506 = _T_503 & _T_64; // @[el2_ifu_compress_ctl.scala 49:83] + wire _T_509 = _T_506 & _T_67; // @[el2_ifu_compress_ctl.scala 49:95] + wire _T_511 = _T_509 & io_in[1]; // @[el2_ifu_compress_ctl.scala 49:107] + wire _T_512 = _T_488 | _T_511; // @[el2_ifu_compress_ctl.scala 49:15] + wire _T_518 = ~io_in[12]; // @[el2_ifu_compress_ctl.scala 50:40] + wire _T_519 = _T_5 & _T_518; // @[el2_ifu_compress_ctl.scala 50:38] + wire _T_522 = _T_519 & _T_12; // @[el2_ifu_compress_ctl.scala 50:51] + wire _T_525 = _T_522 & _T_15; // @[el2_ifu_compress_ctl.scala 50:63] + wire _T_528 = _T_525 & _T_61; // @[el2_ifu_compress_ctl.scala 50:75] + wire _T_531 = _T_528 & _T_64; // @[el2_ifu_compress_ctl.scala 50:87] + wire _T_534 = _T_531 & _T_67; // @[el2_ifu_compress_ctl.scala 50:99] + wire _T_537 = _T_534 & _T_248; // @[el2_ifu_compress_ctl.scala 50:111] + wire _T_538 = _T_512 | _T_537; // @[el2_ifu_compress_ctl.scala 50:15] + wire _T_542 = _T_161 & io_in[13]; // @[el2_ifu_compress_ctl.scala 51:28] + wire _T_545 = _T_542 & _T_49; // @[el2_ifu_compress_ctl.scala 51:38] + wire _T_546 = _T_538 | _T_545; // @[el2_ifu_compress_ctl.scala 51:15] + wire _T_552 = _T_542 & io_in[7]; // @[el2_ifu_compress_ctl.scala 51:75] + wire _T_553 = _T_546 | _T_552; // @[el2_ifu_compress_ctl.scala 51:51] + wire _T_559 = _T_542 & io_in[9]; // @[el2_ifu_compress_ctl.scala 51:109] + wire _T_560 = _T_553 | _T_559; // @[el2_ifu_compress_ctl.scala 51:85] + wire _T_566 = _T_542 & io_in[10]; // @[el2_ifu_compress_ctl.scala 52:38] + wire _T_567 = _T_560 | _T_566; // @[el2_ifu_compress_ctl.scala 52:15] + wire _T_573 = _T_542 & io_in[11]; // @[el2_ifu_compress_ctl.scala 52:73] + wire _T_574 = _T_567 | _T_573; // @[el2_ifu_compress_ctl.scala 52:49] + wire _T_579 = _T_574 | _T_253; // @[el2_ifu_compress_ctl.scala 52:84] + wire [11:0] _T_586 = {5'h0,_T_260,_T_305,_T_389,_T_253,_T_579,2'h3}; // @[Cat.scala 29:58] + wire [19:0] _T_593 = {1'h0,_T_33,9'h0,_T_70,5'h0,_T_120,_T_173,_T_173}; // @[Cat.scala 29:58] + assign io_out = {_T_593,_T_586}; // @[el2_ifu_compress_ctl.scala 111:10] +endmodule diff --git a/firrtl_black_box_resource_files.f b/firrtl_black_box_resource_files.f new file mode 100644 index 00000000..8a57174c --- /dev/null +++ b/firrtl_black_box_resource_files.f @@ -0,0 +1 @@ +/home/waleedbinehsan/Desktop/SweRV-Chisel/rvdff.v \ No newline at end of file diff --git a/project/build.properties b/project/build.properties new file mode 100644 index 00000000..b53dc26f --- /dev/null +++ b/project/build.properties @@ -0,0 +1 @@ +sbt.version = 1.3.10 diff --git a/project/plugins.sbt b/project/plugins.sbt new file mode 100644 index 00000000..5708f81a --- /dev/null +++ b/project/plugins.sbt @@ -0,0 +1 @@ +logLevel := Level.Warn diff --git a/project/project/target/config-classes/$eafbdd71b574e8cd9359$.class b/project/project/target/config-classes/$eafbdd71b574e8cd9359$.class new file mode 100644 index 00000000..eaa7a0a4 Binary files /dev/null and b/project/project/target/config-classes/$eafbdd71b574e8cd9359$.class differ diff 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b/project/target/config-classes/$0e6da3d1a968a0bb164e.cache @@ -0,0 +1 @@ +sbt.internal.DslEntry \ No newline at end of file diff --git a/project/target/config-classes/$0e6da3d1a968a0bb164e.class b/project/target/config-classes/$0e6da3d1a968a0bb164e.class new file mode 100644 index 00000000..f269c1a8 Binary files /dev/null and b/project/target/config-classes/$0e6da3d1a968a0bb164e.class differ diff --git a/project/target/config-classes/$1446b1098fa78c24caff$.class b/project/target/config-classes/$1446b1098fa78c24caff$.class new file mode 100644 index 00000000..b62116d7 Binary files /dev/null and b/project/target/config-classes/$1446b1098fa78c24caff$.class differ diff --git a/project/target/config-classes/$1446b1098fa78c24caff.cache b/project/target/config-classes/$1446b1098fa78c24caff.cache new file mode 100644 index 00000000..050f36c6 --- /dev/null +++ b/project/target/config-classes/$1446b1098fa78c24caff.cache @@ -0,0 +1 @@ +sbt.internal.DslEntry \ No newline at end of file diff --git a/project/target/config-classes/$1446b1098fa78c24caff.class b/project/target/config-classes/$1446b1098fa78c24caff.class new file mode 100644 index 00000000..faee6aa2 Binary files /dev/null and b/project/target/config-classes/$1446b1098fa78c24caff.class differ diff --git a/project/target/config-classes/$208e6fc0b5b2fbb5a711$.class b/project/target/config-classes/$208e6fc0b5b2fbb5a711$.class new file mode 100644 index 00000000..e938b62f Binary files /dev/null and b/project/target/config-classes/$208e6fc0b5b2fbb5a711$.class differ diff --git a/project/target/config-classes/$208e6fc0b5b2fbb5a711.cache b/project/target/config-classes/$208e6fc0b5b2fbb5a711.cache new file mode 100644 index 00000000..050f36c6 --- /dev/null +++ b/project/target/config-classes/$208e6fc0b5b2fbb5a711.cache @@ -0,0 +1 @@ +sbt.internal.DslEntry \ No newline at end of file diff --git a/project/target/config-classes/$208e6fc0b5b2fbb5a711.class b/project/target/config-classes/$208e6fc0b5b2fbb5a711.class new file mode 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b/project/target/streams/_global/scalaCompilerBridgeScope/_global/streams/out new file mode 100644 index 00000000..e69de29b diff --git a/project/target/streams/_global/update/_global/streams/out b/project/target/streams/_global/update/_global/streams/out new file mode 100644 index 00000000..68fc6c75 --- /dev/null +++ b/project/target/streams/_global/update/_global/streams/out @@ -0,0 +1,3 @@ +[debug] "not up to date. inChanged = true, force = false +[debug] Updating ProjectRef(uri("file:/home/waleedbinehsan/Desktop/SweRV-Chislified-master/project/"), "swerv-chislified-master-build")... +[debug] Done updating ProjectRef(uri("file:/home/waleedbinehsan/Desktop/SweRV-Chislified-master/project/"), "swerv-chislified-master-build") diff --git a/project/target/streams/compile/_global/_global/compileBinaryFileInputs/previous b/project/target/streams/compile/_global/_global/compileBinaryFileInputs/previous new file mode 100644 index 00000000..c3e14752 --- /dev/null +++ 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sbt.nio.FileStamp]]]]",{"2.12.10":{"hashes":[],"lastModifiedTimes":[["/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/sbt/1.3.10/sbt-1.3.10.jar",1586919578000],["/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-library.jar",1568150453000],["/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/main_2.12/1.3.10/main_2.12-1.3.10.jar",1586919585000],["/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/io_2.12/1.3.4/io_2.12-1.3.4.jar",1585597895000],["/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/logic_2.12/1.3.10/logic_2.12-1.3.10.jar",1586919582000],["/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/actions_2.12/1.3.10/actions_2.12-1.3.10.jar",1586919588000],["/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/main-settings_2.12/1.3.10/main-settings_2.12-1.3.10.jar",1586919593000],["/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/run_2.12/1.3.10/run_2.12-1.3.10.jar",1586919595000],["/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/command_2.12/1.3.10/command_2.12-1.3.10.jar",1586919569000],["/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/collections_2.12/1.3.10/collections_2.12-1.3.10.jar",1586919594000],["/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/scripted-sbt-redux_2.12/1.3.10/scripted-sbt-redux_2.12-1.3.10.jar",1586919582000],["/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/scripted-plugin_2.12/1.3.10/scripted-plugin_2.12-1.3.10.jar",1586919592000],["/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-lm-integration_2.12/1.3.10/zinc-lm-integration_2.12-1.3.10.jar",1586919595000],["/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar",1554476959000],["/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/launcher-interface/1.1.3/launcher-interface-1.1.3.jar",1566946835000],["/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/logging/log4j/log4j-api/2.11.2/log4j-api-2.11.2.jar",1549415503000],["/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/logging/log4j/log4j-core/2.11.2/log4j-core-2.11.2.jar",1549415573000],["/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/logging/log4j/log4j-slf4j-impl/2.11.2/log4j-slf4j-impl-2.11.2.jar",1549415635000],["/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/cb372/scalacache-caffeine_2.12/0.20.0/scalacache-caffeine_2.12-0.20.0.jar",1510153827000],["/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/io/get-coursier/lm-coursier-shaded_2.12/2.0.0-RC6-2/lm-coursier-shaded_2.12-2.0.0-RC6-2.jar",1584360077000],["/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-logging_2.12/1.3.3/util-logging_2.12-1.3.3.jar",1576119989000],["/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/librarymanagement-core_2.12/1.3.2/librarymanagement-core_2.12-1.3.2.jar",1586906938000],["/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/librarymanagement-ivy_2.12/1.3.2/librarymanagement-ivy_2.12-1.3.2.jar",1586906935000],["/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/compiler-interface/1.3.5/compiler-interface-1.3.5.jar",1585527738000],["/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/zinc-compile_2.12/1.3.5/zinc-compile_2.12-1.3.5.jar",1585527746000],["/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/swoval/file-tree-views/2.1.3/file-tree-views-2.1.3.jar",1562617173000],["/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/net/java/dev/jna/jna/5.5.0/jna-5.5.0.jar",1572453456000],["/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/net/java/dev/jna/jna-platform/5.5.0/jna-platform-5.5.0.jar",1572453499000],["/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/util-relation_2.12/1.3.3/util-relation_2.12-1.3.3.jar",1576119995000],["/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/completion_2.12/1.3.10/completion_2.12-1.3.10.jar",1586919580000],["/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/task-system_2.12/1.3.10/task-system_2.12-1.3.10.jar",1586919576000],["/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/tasks_2.12/1.3.10/tasks_2.12-1.3.10.jar",1586919595000],["/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/testing_2.12/1.3.10/testing_2.12-1.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\ No newline at end of file diff --git a/project/target/streams/compile/_global/_global/compileOutputs/previous b/project/target/streams/compile/_global/_global/compileOutputs/previous new file mode 100644 index 00000000..135a1390 --- /dev/null +++ b/project/target/streams/compile/_global/_global/compileOutputs/previous @@ -0,0 +1 @@ +["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/home/waleedbinehsan/Desktop/SweRV-Chislified-master/project/target/streams/compile/compileOutputs/_global/streams/inc_compile_2.12.zip"]] \ No newline at end of file diff --git a/project/target/streams/compile/_global/_global/compileSourceFileInputs/previous b/project/target/streams/compile/_global/_global/compileSourceFileInputs/previous new file mode 100644 index 00000000..15829e87 --- /dev/null +++ b/project/target/streams/compile/_global/_global/compileSourceFileInputs/previous @@ -0,0 +1 @@ +["sbt.Task[scala.collection.immutable.Map[java.lang.String, scala.collection.Seq[scala.Tuple2[java.nio.file.Path, sbt.nio.FileStamp]]]]",{"2.12.10":{"hashes":[],"lastModifiedTimes":[]}}] \ No newline at end of file diff --git a/project/target/streams/compile/_global/_global/dependencyClasspathFiles/previous b/project/target/streams/compile/_global/_global/dependencyClasspathFiles/previous new file mode 100644 index 00000000..aeb063f9 --- /dev/null +++ b/project/target/streams/compile/_global/_global/dependencyClasspathFiles/previous @@ -0,0 +1 @@ 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\ No newline at end of file diff --git a/project/target/streams/compile/_global/_global/discoveredMainClasses/data b/project/target/streams/compile/_global/_global/discoveredMainClasses/data new file mode 100644 index 00000000..0637a088 --- /dev/null +++ b/project/target/streams/compile/_global/_global/discoveredMainClasses/data @@ -0,0 +1 @@ +[] \ No newline at end of file diff --git a/project/target/streams/compile/_global/_global/managedSourcePaths/previous b/project/target/streams/compile/_global/_global/managedSourcePaths/previous new file mode 100644 index 00000000..a510b125 --- /dev/null +++ b/project/target/streams/compile/_global/_global/managedSourcePaths/previous @@ -0,0 +1 @@ +["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",[]] \ No newline at end of file diff --git a/project/target/streams/compile/compile/_global/streams/out b/project/target/streams/compile/compile/_global/streams/out new file mode 100644 index 00000000..e69de29b diff --git a/project/target/streams/compile/compileIncremental/_global/streams/export b/project/target/streams/compile/compileIncremental/_global/streams/export new file mode 100644 index 00000000..e69de29b diff --git a/project/target/streams/compile/compileIncremental/_global/streams/out b/project/target/streams/compile/compileIncremental/_global/streams/out new file mode 100644 index 00000000..6db8e09d --- /dev/null +++ b/project/target/streams/compile/compileIncremental/_global/streams/out @@ -0,0 +1 @@ +[debug] Full compilation, no sources in previous analysis. diff --git a/project/target/streams/compile/copyResources/_global/streams/copy-resources b/project/target/streams/compile/copyResources/_global/streams/copy-resources new file mode 100644 index 00000000..9d348e7b --- /dev/null +++ b/project/target/streams/compile/copyResources/_global/streams/copy-resources @@ -0,0 +1 @@ +[[{},{}],{}] \ No newline at end of file diff --git a/project/target/streams/compile/copyResources/_global/streams/out b/project/target/streams/compile/copyResources/_global/streams/out new file mode 100644 index 00000000..f25042f2 --- /dev/null +++ b/project/target/streams/compile/copyResources/_global/streams/out @@ -0,0 +1,2 @@ +[debug] Copy resource mappings:  +[debug]   diff --git a/project/target/streams/compile/dependencyClasspath/_global/streams/export b/project/target/streams/compile/dependencyClasspath/_global/streams/export new file mode 100644 index 00000000..f675617e --- /dev/null +++ b/project/target/streams/compile/dependencyClasspath/_global/streams/export @@ -0,0 +1 @@ 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diff --git a/project/target/streams/compile/exportedProducts/_global/streams/export b/project/target/streams/compile/exportedProducts/_global/streams/export new file mode 100644 index 00000000..1614a19f --- /dev/null +++ b/project/target/streams/compile/exportedProducts/_global/streams/export @@ -0,0 +1 @@ +/home/waleedbinehsan/Desktop/SweRV-Chislified-master/project/target/scala-2.12/sbt-1.0/classes diff --git a/project/target/streams/compile/externalDependencyClasspath/_global/streams/export b/project/target/streams/compile/externalDependencyClasspath/_global/streams/export new file mode 100644 index 00000000..b9ea789e --- /dev/null +++ b/project/target/streams/compile/externalDependencyClasspath/_global/streams/export @@ -0,0 +1 @@ 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diff --git a/project/target/streams/compile/internalDependencyClasspath/_global/streams/export b/project/target/streams/compile/internalDependencyClasspath/_global/streams/export new file mode 100644 index 00000000..8b137891 --- /dev/null +++ b/project/target/streams/compile/internalDependencyClasspath/_global/streams/export @@ -0,0 +1 @@ + diff --git a/project/target/streams/compile/managedClasspath/_global/streams/export b/project/target/streams/compile/managedClasspath/_global/streams/export new file mode 100644 index 00000000..b9ea789e --- /dev/null +++ b/project/target/streams/compile/managedClasspath/_global/streams/export @@ -0,0 +1 @@ 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diff --git a/project/target/streams/compile/unmanagedClasspath/_global/streams/export b/project/target/streams/compile/unmanagedClasspath/_global/streams/export new file mode 100644 index 00000000..8b137891 --- /dev/null +++ b/project/target/streams/compile/unmanagedClasspath/_global/streams/export @@ -0,0 +1 @@ + diff --git a/project/target/streams/compile/unmanagedJars/_global/streams/export b/project/target/streams/compile/unmanagedJars/_global/streams/export new file mode 100644 index 00000000..8b137891 --- /dev/null +++ b/project/target/streams/compile/unmanagedJars/_global/streams/export @@ -0,0 +1 @@ + diff --git a/project/target/streams/runtime/dependencyClasspath/_global/streams/export b/project/target/streams/runtime/dependencyClasspath/_global/streams/export new file mode 100644 index 00000000..9327da1d --- /dev/null +++ b/project/target/streams/runtime/dependencyClasspath/_global/streams/export @@ -0,0 +1 @@ +/home/waleedbinehsan/Desktop/SweRV-Chislified-master/project/target/scala-2.12/sbt-1.0/classes:/home/waleedbinehsan/.sbt/1.0/plugins/target/scala-2.12/sbt-1.0/classes diff --git a/project/target/streams/runtime/exportedProducts/_global/streams/export b/project/target/streams/runtime/exportedProducts/_global/streams/export new file mode 100644 index 00000000..1614a19f --- /dev/null +++ b/project/target/streams/runtime/exportedProducts/_global/streams/export @@ -0,0 +1 @@ +/home/waleedbinehsan/Desktop/SweRV-Chislified-master/project/target/scala-2.12/sbt-1.0/classes diff --git a/project/target/streams/runtime/externalDependencyClasspath/_global/streams/export b/project/target/streams/runtime/externalDependencyClasspath/_global/streams/export new file mode 100644 index 00000000..8b137891 --- /dev/null +++ b/project/target/streams/runtime/externalDependencyClasspath/_global/streams/export @@ -0,0 +1 @@ + diff --git a/project/target/streams/runtime/fullClasspath/_global/streams/export b/project/target/streams/runtime/fullClasspath/_global/streams/export new file mode 100644 index 00000000..9327da1d --- /dev/null +++ b/project/target/streams/runtime/fullClasspath/_global/streams/export @@ -0,0 +1 @@ +/home/waleedbinehsan/Desktop/SweRV-Chislified-master/project/target/scala-2.12/sbt-1.0/classes:/home/waleedbinehsan/.sbt/1.0/plugins/target/scala-2.12/sbt-1.0/classes diff --git a/project/target/streams/runtime/internalDependencyClasspath/_global/streams/export b/project/target/streams/runtime/internalDependencyClasspath/_global/streams/export new file mode 100644 index 00000000..1614a19f --- /dev/null +++ b/project/target/streams/runtime/internalDependencyClasspath/_global/streams/export @@ -0,0 +1 @@ +/home/waleedbinehsan/Desktop/SweRV-Chislified-master/project/target/scala-2.12/sbt-1.0/classes diff --git a/project/target/streams/runtime/managedClasspath/_global/streams/export b/project/target/streams/runtime/managedClasspath/_global/streams/export new file mode 100644 index 00000000..8b137891 --- /dev/null +++ b/project/target/streams/runtime/managedClasspath/_global/streams/export @@ -0,0 +1 @@ + diff --git a/project/target/streams/runtime/unmanagedClasspath/_global/streams/export b/project/target/streams/runtime/unmanagedClasspath/_global/streams/export new file mode 100644 index 00000000..8b137891 --- /dev/null +++ b/project/target/streams/runtime/unmanagedClasspath/_global/streams/export @@ -0,0 +1 @@ + diff --git a/project/target/streams/runtime/unmanagedJars/_global/streams/export b/project/target/streams/runtime/unmanagedJars/_global/streams/export new file mode 100644 index 00000000..8b137891 --- /dev/null +++ b/project/target/streams/runtime/unmanagedJars/_global/streams/export @@ -0,0 +1 @@ + diff --git a/rvdff.anno.json b/rvdff.anno.json new file mode 100644 index 00000000..b4608402 --- /dev/null +++ b/rvdff.anno.json @@ -0,0 +1,30 @@ +[ + { + "class":"logger.LogLevelAnnotation", + "globalLogLevel":{ + + } + }, + { + "class":"firrtl.EmitCircuitAnnotation", + "emitter":"firrtl.VerilogEmitter" + }, + { + "class":"firrtl.transforms.BlackBoxInlineAnno", + "target":"rvdff.rvdff_verilog", + "name":"rvdff.v", + "text":"\nmodule InoutPort( input [15:0] in,\n input clk,\n input reset,\n output [15:0] out);\n always@(posedge clk or negedge reset)\n begin\n if(reset == 0)\n out <= 0;\n else\n out <= in\n end\nendmodule\n " + }, + { + "class":"firrtl.options.TargetDirAnnotation", + "directory":"." + }, + { + "class":"firrtl.options.OutputAnnotationFileAnnotation", + "file":"rvdff" + }, + { + "class":"firrtl.transforms.BlackBoxTargetDirAnno", + "targetDir":"." + } +] \ No newline at end of file diff --git a/rvdff.fir b/rvdff.fir new file mode 100644 index 00000000..7357875f --- /dev/null +++ b/rvdff.fir @@ -0,0 +1,28 @@ +;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10 +circuit rvdff : + extmodule rvdff_verilog : + input in : UInt<16> + input clk : Clock + input reset : UInt<1> + output out : UInt<16> + + defname = rvdff_verilog + parameter DATA_WIDTH = 32 + parameter MODE = "Sequential" + parameter RESET = "Asynchronous" + + module rvdff : + input clock : Clock + input reset : UInt<1> + output io : {flip in : UInt<16>, flip clk : Clock, flip reset : UInt<1>, out : UInt<16>} + + inst m of rvdff_verilog @[GCD.scala 41:17] + m.out is invalid + m.reset is invalid + m.clk is invalid + m.in is invalid + io.out <= m.out @[GCD.scala 43:8] + m.reset <= io.reset @[GCD.scala 43:8] + m.clk <= io.clk @[GCD.scala 43:8] + m.in <= io.in @[GCD.scala 43:8] + diff --git a/rvdff.v b/rvdff.v new file mode 100644 index 00000000..538d7a1d --- /dev/null +++ b/rvdff.v @@ -0,0 +1,23 @@ +module rvdff( + input clock, + input reset, + input [15:0] io_in, + input io_clk, + input io_reset, + output [15:0] io_out +); + wire [15:0] m_in; // @[GCD.scala 41:17] + wire m_clk; // @[GCD.scala 41:17] + wire m_reset; // @[GCD.scala 41:17] + wire [15:0] m_out; // @[GCD.scala 41:17] + rvdff_verilog #(.DATA_WIDTH(32), .MODE("Sequential"), .RESET("Asynchronous")) m ( // @[GCD.scala 41:17] + .in(m_in), + .clk(m_clk), + .reset(m_reset), + .out(m_out) + ); + assign io_out = m_out; // @[GCD.scala 43:8] + assign m_in = io_in; // @[GCD.scala 43:8] + assign m_clk = io_clk; // @[GCD.scala 43:8] + assign m_reset = io_reset; // @[GCD.scala 43:8] +endmodule diff --git a/scalastyle-config.xml b/scalastyle-config.xml new file mode 100644 index 00000000..b15add86 --- /dev/null +++ b/scalastyle-config.xml @@ -0,0 +1,110 @@ + + Scalastyle standard configuration + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + No lines ending with a ; + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + |\|\||&&|:=|<>|<=|>=|!=|===|<<|>>|##|unary_(~|\-%?|!))$]]> + + + + + + + + + + + diff --git a/scalastyle-test-config.xml b/scalastyle-test-config.xml new file mode 100644 index 00000000..399ac020 --- /dev/null +++ b/scalastyle-test-config.xml @@ -0,0 +1,109 @@ + + Scalastyle configuration for Chisel3 unit tests + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + No lines ending with a ; + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + |\|\||&&|:=|<>|<=|>=|!=|===|<<|>>|##|unary_(~|\-%?|!))$]]> + + + + + + + + + + + diff --git a/src/main/scala/dec/el2_dec_dec_ctl.scala b/src/main/scala/dec/el2_dec_dec_ctl.scala new file mode 100644 index 00000000..5188f92a --- /dev/null +++ b/src/main/scala/dec/el2_dec_dec_ctl.scala @@ -0,0 +1,174 @@ +package dec +import chisel3._ +import chisel3.util._ + +class el2_dec_pkt_t extends Bundle{ + val alu = Bool() + val rs1 = Bool() + val rs2 = Bool() + val imm12 = Bool() + val rd = Bool() + val shimm5 = Bool() + val imm20 = Bool() + val pc = Bool() + val load = Bool() + val store = Bool() + val lsu = Bool() + val add = Bool() + val sub = Bool() + val land = Bool() + val lor = Bool() + val lxor = Bool() + val sll = Bool() + val sra = Bool() + val srl = Bool() + val slt = Bool() + val unsign = Bool() + val condbr = Bool() + val beq = Bool() + val bne = Bool() + val bge = Bool() + val blt = Bool() + val jal = Bool() + val by = Bool() + val half = Bool() + val word = Bool() + val csr_read = Bool() + val csr_clr = Bool() + val csr_set = Bool() + val csr_write = Bool() + val csr_imm = Bool() + val presync = Bool() + val postsync = Bool() + val ebreak = Bool() + val ecall = Bool() + val mret = Bool() + val mul = Bool() + val rs1_sign = Bool() + val rs2_sign = Bool() + val low = Bool() + val div = Bool() + val rem = Bool() + val fence = Bool() + val fence_i = Bool() + val pm_alu = Bool() + val legal = Bool() +} + +class el2_dec_dec_ctl extends Module{ + val io = IO (new Bundle{ + val ins = Input(UInt(32.W)) + val out = Output(new el2_dec_pkt_t) + }) + + def pattern(y : List[Int]) : Array[UInt] = { + val pat : Array[UInt] = new Array[UInt](y.size) + for (i <- 0 until y.size){ + pat(i) = if(y(i)>0) io.ins(y(i)) else !io.ins(y(i).abs) + } + pat + } + + io.out.alu := io.ins(2) | io.ins(6) | (!io.ins(25)&io.ins(4)) | (!io.ins(5)&io.ins(4)) + io.out.rs1 := pattern(List(-14,-13,-2)).reduce(_&_) | pattern(List(-13,11,-2)).reduce(_&_) | + pattern(List(19,13,-2)).reduce(_&_) | pattern(List(-13,10,-2)).reduce(_&_) | + pattern(List(-18,13,-2)).reduce(_&_) | pattern(List(-13,9,-2)).reduce(_&_) | + pattern(List(17,13,-2)).reduce(_&_) | pattern(List(-13,8,-2)).reduce(_&_) | + pattern(List(16,13,-2)).reduce(_&_) | pattern(List(-13,7,-2)).reduce(_&_) | + pattern(List(15,13,-2)).reduce(_&_) |pattern(List(-4,-3)).reduce(_&_) | pattern(List(-6,-2)).reduce(_&_) + io.out.rs2 := pattern(List(5,-4,-2)).reduce(_&_) | pattern(List(-6,5,-2)).reduce(_&_) + io.out.imm12 := pattern(List(-4,-3,2)).reduce(_&_) | pattern(List(13,-5,4,-2)).reduce(_&_) | + pattern(List(-13,-12,6,4)).reduce(_&_) | pattern(List(-12,-5,4,-2)).reduce(_&_) + io.out.rd := (!io.ins(5) & !io.ins(2)) | (io.ins(5) & io.ins(2)) | io.ins(4) + io.out.shimm5 := pattern(List(-13,12,-5,4,-2)).reduce(_&_) + io.out.imm20 := (io.ins(5)&io.ins(3)) | (io.ins(4)&io.ins(2)) + io.out.pc := (!io.ins(5) & !io.ins(3) & io.ins(2)) | (io.ins(5) & io.ins(3)) + io.out.load := pattern(List(-5,-4,-2)).reduce(_&_) + io.out.store := pattern(List(-6,5,-4)).reduce(_&_) + io.out.lsu := pattern(List(-6,-4,-2)).reduce(_&_) + io.out.add := pattern(List(-14,-13,-12,-5,4)).reduce(_&_) | pattern(List(-5,-3,2)).reduce(_&_) | + pattern(List(-30,-25,-14,-13,-12,-6,4,-2)).reduce(_&_) + io.out.sub := pattern(List(30,-12,-6,5,4,-2)).reduce(_&_) | pattern(List(-25,-14,13,-6,4,-2)).reduce(_&_) | + pattern(List(-14,13,-5,4,-2)).reduce(_&_) | pattern(List(6,-4,-2)).reduce(_&_) + io.out.land := pattern(List(14,13,12,-5,-2)).reduce(_&_) | pattern(List(-25,14,13,12,-6,-2)).reduce(_&_) + io.out.lor := pattern(List(-6,3)).reduce(_&_) | pattern(List(-25,14,13,-12,-6,-2)).reduce(_&_) | + pattern(List(5,4,2)).reduce(_&_) | pattern(List(-13,-12,6,4)).reduce(_&_) | + pattern(List(14,13,-12,-5,-2)).reduce(_&_) + io.out.lxor := pattern(List(-25,14,-13,-12,4,-2)).reduce(_&_) | pattern(List(14,-13,-12,-5,4,-2)).reduce(_&_) + io.out.sll := pattern(List(-25,-14,-13,12,-6,4,-2)).reduce(_&_) + io.out.sra := pattern(List(30,-13,12,-6,4,-2)).reduce(_&_) + io.out.srl := pattern(List(-30,-25,14,-13,12,-6,4,-2)).reduce(_&_) + io.out.slt := pattern(List(-25,-14,13,12,-6,4,-2)).reduce(_&_) | pattern(List(-14,13,-5,4,-2)).reduce(_&_) + io.out.unsign := pattern(List(-14,13,12,-5,-2)).reduce(_&_) | pattern(List(13,6,-4,-2)).reduce(_&_) | + pattern(List(14,-5,-4)).reduce(_&_) | pattern(List(-25,-14,13,12,-6,-2)).reduce(_&_) | + pattern(List(25,14,12,-6,5,-2)).reduce(_&_) + io.out.condbr := pattern(List(6,-4,-2)).reduce(_&_) + io.out.beq := pattern(List(-14,-12,6,-4,-2)).reduce(_&_) + io.out.bne := pattern(List(-14,12,6,-4,-2)).reduce(_&_) + io.out.bge := pattern(List(14,12,5,-4,-2)).reduce(_&_) + io.out.blt := pattern(List(14,-12,5,-4,-2)).reduce(_&_) + io.out.jal := pattern(List(6,2)).reduce(_&_) + io.out.by := pattern(List(-13,-12,-6,-4,-2)).reduce(_&_) + io.out.half := pattern(List(12,-6,-4,-2)).reduce(_&_) + io.out.word := pattern(List(13,-6,-4)).reduce(_&_) + io.out.csr_read := pattern(List(13,6,4)).reduce(_&_) | pattern(List(7,6,4)).reduce(_&_) | + pattern(List(8,6,4)).reduce(_&_) | pattern(List(9,6,4)).reduce(_&_) | pattern(List(10,6,4)).reduce(_&_) | + pattern(List(11,6,4)).reduce(_&_) + io.out.csr_clr := pattern(List(15,13,12,6,4)).reduce(_&_) | pattern(List(16,13,12,6,4)).reduce(_&_) | + pattern(List(17,13,12,6,4)).reduce(_&_) | pattern(List(18,-12,6,4)).reduce(_&_) | + pattern(List(19,-12,6,4)).reduce(_&_) + io.out.csr_write := pattern(List(-13,12,6,4)).reduce(_&_) + io.out.csr_imm := pattern(List(14,-13,6,4)).reduce(_&_) | pattern(List(15,14,6,4)).reduce(_&_) | + pattern(List(16,14,6,4)).reduce(_&_) | pattern(List(17,14,6,4)).reduce(_&_) | + pattern(List(18,14,6,4)).reduce(_&_) | pattern(List(19,14,6,4)).reduce(_&_) + io.out.csr_set := pattern(List(15,-12,6,4)).reduce(_&_) | pattern(List(16,-12,6,4)).reduce(_&_) | + pattern(List(17,-12,6,4)).reduce(_&_) | pattern(List(18,-12,6,4)).reduce(_&_) | + pattern(List(19,-12,6,4)).reduce(_&_) + io.out.ebreak := pattern(List(-22,20,-13,-12,6,4)).reduce(_&_) + io.out.ecall := pattern(List(-21,-20,-13,-12,6,4)).reduce(_&_) + io.out.mret := pattern(List(29,-13,-12,6,4)).reduce(_&_) + io.out.mul := pattern(List(25,-14,-6,5,4,-2)).reduce(_&_) + io.out.rs1_sign := pattern(List(25,-14,13,-12,-6,5,4,-2)).reduce(_&_) | + pattern(List(25,-14,-13,12,-6,4,-2)).reduce(_&_) + io.out.rs2_sign := pattern(List(25,-14,-13,12,-6,4,-2)).reduce(_&_) + io.out.low := pattern(List(25,-14,-13,-12,5,4,-2)).reduce(_&_) + io.out.div := pattern(List(25,14,-6,5,-2)).reduce(_&_) + io.out.rem := pattern(List(25,14,13,-6,5,-2)).reduce(_&_) + io.out.fence := pattern(List(-5,3)).reduce(_&_) + io.out.fence_i := pattern(List(12,-5,3)).reduce(_&_) + io.out.pm_alu := pattern(List(28,22,-13,-12,4)).reduce(_&_) | pattern(List(4,2)).reduce(_&_) | + pattern(List(-25,-6,4)).reduce(_&_) | pattern(List(-5,4)).reduce(_&_) + io.out.presync := pattern(List(-5,3)).reduce(_&_) | pattern(List(-13,7,6,4)).reduce(_&_) | + pattern(List(-13,8,6,4)).reduce(_&_) | pattern(List(-13,9,6,4)).reduce(_&_) | + pattern(List(-13,9,6,4)).reduce(_&_) | pattern(List(-13,10,6,4)).reduce(_&_) | + pattern(List(-13,11,6,4)).reduce(_&_) | pattern(List(15,13,6,4)).reduce(_&_) | + pattern(List(16,13,6,4)).reduce(_&_) | pattern(List(17,13,6,4)).reduce(_&_) | + pattern(List(18,13,6,4)).reduce(_&_) | pattern(List(19,13,6,4)).reduce(_&_) + io.out.postsync := pattern(List(12,-5,3)).reduce(_&_) | pattern(List(-22,-13,-12,6,4)).reduce(_&_) | + pattern(List(-13,7,6,4)).reduce(_&_) | pattern(List(-13,8,6,4)).reduce(_&_) | + pattern(List(-13,9,6,4)).reduce(_&_) | pattern(List(-13,10,6,4)).reduce(_&_) | + pattern(List(-13,11,6,4)).reduce(_&_) | pattern(List(15,13,6,4)).reduce(_&_) | + pattern(List(16,13,6,4)).reduce(_&_) | pattern(List(17,13,6,4)).reduce(_&_) | + pattern(List(18,13,6,4)).reduce(_&_) | pattern(List(19,13,6,4)).reduce(_&_) + io.out.legal := pattern(List(-31,-30,29,28,-27,-26,-25,-24,-23,-22,21,-20,-19,-18,-17,-16,-15,-14,-11,-10,-9,-8,-7,6,5,4,-3,-2,1,0)).reduce(_&_) | + pattern(List(-31,-30,-29,28,-27,-26,-25,-24,-23,22,-21,20,-19,-18,-17,-16,-15,-14,-11,-10,-9,-8,-7,6,5,4,-3,-2,1,0)).reduce(_&_) | + pattern(List(-31,-30,-29,-28,-27,-26,-25,-24,-23,-22,-21,-19,-18,-17,-16,-15,-14,-11,-10,-9,-8,-7,5,4,-3,-2,1,0)).reduce(_&_) | + pattern(List(-31,-30,-29,-28,-27,-26,-25,-6,4,-3,1,0)).reduce(_&_) | + pattern(List(-31,-29,-28,-27,-26,-25,-14,-13,-12,-6,-3,-2,1,0)).reduce(_&_) | + pattern(List(-31,-29,-28,-27,-26,-25,14,-13,12,-6,4,-3,1,0)).reduce(_&_) | + pattern(List(-31,-30,-29,-28,-27,-26,-6,5,4,-3,1,0)).reduce(_&_) | + pattern(List(-14,-13,-12,6,5,-4,-3,1,0)).reduce(_&_) | + pattern(List(14,6,5,-4,-3,-2,1,0)).reduce(_&_) | + pattern(List(-12,-6,-5,4,-3,1,0)).reduce(_&_) | pattern(List(-14,-13,5,-4,-3,-2,1,0)).reduce(_&_) | + pattern(List(12,6,5,4,-3,-2,1,0)).reduce(_&_) | + pattern(List(-31,-30,-29,-28,-27,-26,-25,-24,-23,-22,-21,-20,-19,-18,-17,-16,-15,-14,-13,-12,-11,-10,-9,-8,-7,-6,-5,-4,3,2,1,0)).reduce(_&_) | + pattern(List(-31,-30,-29,-28,-19,-18,-17,-16,-15,-14,-13,-12,-11,-10,-9,-8,-7,-6,-5,-4,3,2,1,0)).reduce(_&_) | + pattern(List(-13,-6,-5,-4,-3,-2,1,0)).reduce(_&_) | pattern(List(6,5,-4,3,2,1,0)).reduce(_&_) | + pattern(List(13,-6,-5,4,-3,1,0)).reduce(_&_) | pattern(List(-14,-12,-6,-4,-3,-2,1,0)).reduce(_&_) | + pattern(List(-6,4,-3,-2,1,0)).reduce(_&_) +} + +object dec extends App { + chisel3.Driver.execute(args, () => new el2_dec_dec_ctl()) + println(Driver.emitVerilog(new el2_dec_dec_ctl())) +} diff --git a/src/main/scala/lib/GCD.scala b/src/main/scala/lib/GCD.scala new file mode 100644 index 00000000..6a0f200c --- /dev/null +++ b/src/main/scala/lib/GCD.scala @@ -0,0 +1,123 @@ +package lib + +import chisel3._ +import chisel3.util._ + +/////////////////////////////////////////////////////////////// +class rvdff(val Width:Int = 1, val short:Int = 0) extends Module with RequireAsyncReset { + val io = IO(new Bundle { + val in = Input(UInt(Width.W)) + val out = Output(UInt()) + }) + val inter = if(short==0) RegNext(io.in, init =0.U) else io.in + io.out := inter +} + +///////////////////////////////////////////////////////////// +class caller extends Module { + val io = IO(new Bundle { + val in = Input(UInt(32.W)) + val out = Output(UInt()) + }) + val u0 = Module(new rvdff(32)) + io <> u0.io +} + +/////////////////////////////////////////////////////////////// +class reg1 extends Module with RequireAsyncReset{ + val io = IO(new Bundle{ + val in = Input(Bool()) + val out = Output(Bool()) + }) + + io.out := RegNext(io.in, init = 0.U) +} + +class top extends Module with RequireAsyncReset{ + val io = IO(new Bundle{ + val in = Input(Bool()) + val out = Output(Bool()) + }) + val negReset = (~reset.asBool).asAsyncReset + val r0 = Module(new reg1) + r0.io<>io + r0.reset := negReset +} +/////////////////////////////////////////////////////////////// +class rvbradder() extends Module { + val io = IO(new Bundle { + val pc = Input(UInt(31.W)) + val offset = Input(UInt(12.W)) + val dout = Output(UInt()) + }) + val inter = io.pc(11,0) +& io.offset + val cout = inter(inter.getWidth-1) + val pc_inc = io.pc(io.pc.getWidth-1, 12) + 1.U + val pc_dec = io.pc(io.pc.getWidth-1, 12) - 1.U + val sign = io.offset(io.offset.getWidth -1) + + io.dout:= Cat(Fill(19,(sign ^(~cout))) & io.pc(io.pc.getWidth-1,12) | + (Fill(19,(~sign & cout)) & pc_inc) | + (Fill(19,(sign & ~cout)) & pc_dec) , inter(inter.getWidth-2,0)) +} + +/////////////////////////////////////////////////////////////// +class encoder_generator(val width:Int=4) extends Module { + val io = IO (new Bundle { + val in = Input (UInt(width.W)) + val out = Output (UInt(log2Ceil(width).W)) + }) + var z:Array[UInt] = new Array[UInt](width) + for(i<- 0 until width){ + z(i) = i.U + } + io.out := Mux1H(io.in , z) +} + +/////////////////////////////////////////////////////////////// +class rvrangecheck(val CCM_SADR:Int = 0, val CCM_SIZE:Int = 128) extends Module { + val io = IO(new Bundle { + val addr = Input(UInt(32.W)) + val in_range = Output(Bool()) + val in_region = Output(Bool()) + //val test = Output(UInt()) + }) + val start_addr = (CCM_SADR.U)(32.W) + val region = start_addr(31,28) + val MASK_BITS = 10+log2Ceil(CCM_SIZE) + io.in_region := io.addr(31,28) === region + val inter = if(CCM_SIZE == 48) io.addr(31, MASK_BITS) === start_addr(31, MASK_BITS) & ~(io.addr(MASK_BITS-1,MASK_BITS-2).andR) + else (io.addr(31,MASK_BITS)===start_addr(31,MASK_BITS)) + io.in_range := inter +} + + + +//////////////////////////////////////////////////////////////// +class tocopy extends Module{ + val io = IO(new Bundle { + val in1 = Input(UInt(1.W)) + val in2 = Input(UInt(1.W)) + val out = Output(UInt()) + }) + io.out := io.in1 +& io.in2 +} +class exp extends Module{ + val io = IO(new Bundle{ + val in1 = Input(UInt(1.W)) + val in2 = Input(UInt(1.W)) + val out = Output(UInt()) + }) + + val mod_array= new Array[tocopy](2) + mod_array(0) = Module(new tocopy) + mod_array(0).io.in1:=io.in1 + mod_array(0).io.in2:=io.in2 + mod_array(1) = Module(new tocopy) + mod_array(1).io.in1:=io.in1 + mod_array(1).io.in2:=io.in2 + io.out:= mod_array(0).io.out +& mod_array(1).io.out +} +//////////////////////////////////////////////////////////////// + +//println((new chisel3.stage.ChiselStage).emitVerilog(new exp)) \ No newline at end of file diff --git a/src/main/scala/lib/RVC.scala b/src/main/scala/lib/RVC.scala new file mode 100644 index 00000000..cfcacf91 --- /dev/null +++ b/src/main/scala/lib/RVC.scala @@ -0,0 +1,232 @@ +// See LICENSE.SiFive for license details. + +//package freechips.rocketchip.rocket +package lib + +import chisel3._ +import chisel3.util._ +import chisel3.util.ImplicitConversions +import chisel3.experimental._ +import Chisel.ImplicitConversions._ + +//import freechips.rocketchip.config.Parameters +//import freechips.rocketchip.tile._ +//import freechips.rocketchip.util._ + +class ExpandedInstruction extends Bundle { + val bits = UInt(32.W) + val rd = UInt(5.W) + val rs1 = UInt(5.W) + val rs2 = UInt(5.W) + val rs3 = UInt(5.W) +} + +class RVCDecoder(x: UInt, xLen: Int) { + def inst(bits: UInt, rd: UInt = x(11,7), rs1: UInt = x(19,15), rs2: UInt = x(24,20), rs3: UInt = x(31,27)) = { + val res = Wire(new ExpandedInstruction) + res.bits := bits + res.rd := rd + res.rs1 := rs1 + res.rs2 := rs2 + res.rs3 := rs3 + res + } + + def rs1p = Cat(1.U(2.W), x(9,7)) + def rs2p = Cat(1.U(2.W), x(4,2)) + def rs2 = x(6,2) + def rd = x(11,7) + def addi4spnImm = Cat(x(10,7), x(12,11), x(5), x(6), 0.U(2.W)) + def lwImm = Cat(x(5), x(12,10), x(6), 0.U(2.W)) + def ldImm = Cat(x(6,5), x(12,10), 0.U(3.W)) + def lwspImm = Cat(x(3,2), x(12), x(6,4), 0.U(2.W)) + def ldspImm = Cat(x(4,2), x(12), x(6,5), 0.U(3.W)) + def swspImm = Cat(x(8,7), x(12,9), 0.U(2.W)) + def sdspImm = Cat(x(9,7), x(12,10), 0.U(3.W)) + def luiImm = Cat(Fill(15, x(12)), x(6,2), 0.U(12.W)) + def addi16spImm = Cat(Fill(3, x(12)), x(4,3), x(5), x(2), x(6), 0.U(4.W)) + def addiImm = Cat(Fill(7, x(12)), x(6,2)) + def jImm = Cat(Fill(10, x(12)), x(8), x(10,9), x(6), x(7), x(2), x(11), x(5,3), 0.U(1.W)) + def bImm = Cat(Fill(5, x(12)), x(6,5), x(2), x(11,10), x(4,3), 0.U(1.W)) + def shamt = Cat(x(12), x(6,2)) + def x0 = 0.U(5.W) + def ra = 1.U(5.W) + def sp = 2.U(5.W) + + def q0 = { + def addi4spn = { + val opc = Mux(x(12,5).orR, 0x13.U(7.W), 0x1F.U(7.W)) + inst(Cat(addi4spnImm, sp, 0.U(3.W), rs2p, opc), rs2p, sp, rs2p) + } + def ld = inst(Cat(ldImm, rs1p, 3.U(3.W), rs2p, 0x03.U(7.W)), rs2p, rs1p, rs2p) + def lw = inst(Cat(lwImm, rs1p, 2.U(3.W), rs2p, 0x03.U(7.W)), rs2p, rs1p, rs2p) + def fld = inst(Cat(ldImm, rs1p, 3.U(3.W), rs2p, 0x07.U(7.W)), rs2p, rs1p, rs2p) + def flw = { + if (xLen == 32) inst(Cat(lwImm, rs1p, 2.U(3.W), rs2p, 0x07.U(7.W)), rs2p, rs1p, rs2p) + else ld + } + def unimp = inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x3F.U(7.W)), rs2p, rs1p, rs2p) + def sd = inst(Cat(ldImm >> 5, rs2p, rs1p, 3.U(3.W), ldImm(4,0), 0x23.U(7.W)), rs2p, rs1p, rs2p) + def sw = inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x23.U(7.W)), rs2p, rs1p, rs2p) + def fsd = inst(Cat(ldImm >> 5, rs2p, rs1p, 3.U(3.W), ldImm(4,0), 0x27.U(7.W)), rs2p, rs1p, rs2p) + def fsw = { + if (xLen == 32) inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x27.U(7.W)), rs2p, rs1p, rs2p) + else sd + } + Seq(addi4spn, fld, lw, flw, unimp, fsd, sw, fsw) + } + + def q1 = { + def addi = inst(Cat(addiImm, rd, 0.U(3.W), rd, 0x13.U(7.W)), rd, rd, rs2p) + def addiw = { + val opc = Mux(rd.orR, 0x1B.U(7.W), 0x1F.U(7.W)) + inst(Cat(addiImm, rd, 0.U(3.W), rd, opc), rd, rd, rs2p) + } + def jal = { + if (xLen == 32) inst(Cat(jImm(20), jImm(10,1), jImm(11), jImm(19,12), ra, 0x6F.U(7.W)), ra, rd, rs2p) + else addiw + } + def li = inst(Cat(addiImm, x0, 0.U(3.W), rd, 0x13.U(7.W)), rd, x0, rs2p) + def addi16sp = { + val opc = Mux(addiImm.orR, 0x13.U(7.W), 0x1F.U(7.W)) + inst(Cat(addi16spImm, rd, 0.U(3.W), rd, opc), rd, rd, rs2p) + } + def lui = { + val opc = Mux(addiImm.orR, 0x37.U(7.W), 0x3F.U(7.W)) + val me = inst(Cat(luiImm(31,12), rd, opc), rd, rd, rs2p) + Mux(rd === x0 || rd === sp, addi16sp, me) + } + def j = inst(Cat(jImm(20), jImm(10,1), jImm(11), jImm(19,12), x0, 0x6F.U(7.W)), x0, rs1p, rs2p) + def beqz = inst(Cat(bImm(12), bImm(10,5), x0, rs1p, 0.U(3.W), bImm(4,1), bImm(11), 0x63.U(7.W)), rs1p, rs1p, x0) + def bnez = inst(Cat(bImm(12), bImm(10,5), x0, rs1p, 1.U(3.W), bImm(4,1), bImm(11), 0x63.U(7.W)), x0, rs1p, x0) + def arith = { + def srli = Cat(shamt, rs1p, 5.U(3.W), rs1p, 0x13.U(7.W)) + def srai = srli | (1 << 30).U + def andi = Cat(addiImm, rs1p, 7.U(3.W), rs1p, 0x13.U(7.W)) + def rtype = { + val funct = VecInit(0.U, 4.U, 6.U, 7.U, 0.U, 0.U, 2.U, 3.U)(Cat(x(12), x(6,5))) + val sub = Mux(x(6,5) === 0.U, (1 << 30).U, 0.U) + val opc = Mux(x(12), 0x3B.U(7.W), 0x33.U(7.W)) + Cat(rs2p, rs1p, funct, rs1p, opc) | sub + } + inst(VecInit(srli, srai, andi, rtype)(x(11,10)), rs1p, rs1p, rs2p) + } + Seq(addi, jal, li, lui, arith, j, beqz, bnez) + } + + def q2 = { + val load_opc = Mux(rd.orR, 0x03.U(7.W), 0x1F.U(7.W)) + def slli = inst(Cat(shamt, rd, 1.U(3.W), rd, 0x13.U(7.W)), rd, rd, rs2) + def ldsp = inst(Cat(ldspImm, sp, 3.U(3.W), rd, load_opc), rd, sp, rs2) + def lwsp = inst(Cat(lwspImm, sp, 2.U(3.W), rd, load_opc), rd, sp, rs2) + def fldsp = inst(Cat(ldspImm, sp, 3.U(3.W), rd, 0x07.U(7.W)), rd, sp, rs2) + def flwsp = { + if (xLen == 32) inst(Cat(lwspImm, sp, 2.U(3.W), rd, 0x07.U(7.W)), rd, sp, rs2) + else ldsp + } + def sdsp = inst(Cat(sdspImm >> 5, rs2, sp, 3.U(3.W), sdspImm(4,0), 0x23.U(7.W)), rd, sp, rs2) + def swsp = inst(Cat(swspImm >> 5, rs2, sp, 2.U(3.W), swspImm(4,0), 0x23.U(7.W)), rd, sp, rs2) + def fsdsp = inst(Cat(sdspImm >> 5, rs2, sp, 3.U(3.W), sdspImm(4,0), 0x27.U(7.W)), rd, sp, rs2) + def fswsp = { + if (xLen == 32) inst(Cat(swspImm >> 5, rs2, sp, 2.U(3.W), swspImm(4,0), 0x27.U(7.W)), rd, sp, rs2) + else sdsp + } + def jalr = { + val mv = inst(Cat(rs2, x0, 0.U(3.W), rd, 0x33.U(7.W)), rd, x0, rs2) + val add = inst(Cat(rs2, rd, 0.U(3.W), rd, 0x33.U(7.W)), rd, rd, rs2) + val jr = Cat(rs2, rd, 0.U(3.W), x0, 0x67.U(7.W)) + val reserved = Cat(jr >> 7, 0x1F.U(7.W)) + val jr_reserved = inst(Mux(rd.orR, jr, reserved), x0, rd, rs2) + val jr_mv = Mux(rs2.orR, mv, jr_reserved) + val jalr = Cat(rs2, rd, 0.U(3.W), ra, 0x67.U(7.W)) + val ebreak = Cat(jr >> 7, 0x73.U(7.W)) | (1 << 20).U + val jalr_ebreak = inst(Mux(rd.orR, jalr, ebreak), ra, rd, rs2) + val jalr_add = Mux(rs2.orR, add, jalr_ebreak) + Mux(x(12), jalr_add, jr_mv) + } + Seq(slli, fldsp, lwsp, flwsp, jalr, fsdsp, swsp, fswsp) + } + + def q3 = Seq.fill(8)(passthrough) + + def passthrough = inst(x) + + def decode = { + val s = VecInit(q0 ++ q1 ++ q2 ++ q3) + s(Cat(x(1,0), x(15,13))) + } + + + + def changed_q0 = { + def addi4spn = { + val opc = Mux(x(12,5).orR, 0x13.U(7.W), 0x1F.U(7.W)) + inst(Cat(addi4spnImm, sp, 0.U(3.W), rs2p, opc), rs2p, sp, rs2p) + } + def ld = inst(Cat(ldImm, rs1p, 3.U(3.W), rs2p, 0x03.U(7.W)), rs2p, rs1p, rs2p) + def lw = inst(Cat(lwImm, rs1p, 2.U(3.W), rs2p, 0x03.U(7.W)), rs2p, rs1p, rs2p) + def fld = inst(Cat(ldImm, rs1p, 3.U(3.W), rs2p, 0x07.U(7.W)), rs2p, rs1p, rs2p) + def flw = { + if (xLen == 32) inst(Cat(lwImm, rs1p, 2.U(3.W), rs2p, 0x07.U(7.W)), rs2p, rs1p, rs2p) + else ld + } + def unimp = inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x3F.U(7.W)), rs2p, rs1p, rs2p) + def sd = inst(Cat(ldImm >> 5, rs2p, rs1p, 3.U(3.W), ldImm(4,0), 0x23.U(7.W)), rs2p, rs1p, rs2p) + def sw = inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x23.U(7.W)), rs2p, rs1p, rs2p) + def fsd = inst(Cat(ldImm >> 5, rs2p, rs1p, 3.U(3.W), ldImm(4,0), 0x27.U(7.W)), rs2p, rs1p, rs2p) + def fsw = { + if (xLen == 32) inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x27.U(7.W)), rs2p, rs1p, rs2p) + else sd + } + addi4spn + } + + def ret_q0 = VecInit(q0) + def ret_q1 = q1 + def ret_q2 = q2 + def ret_q3 = q3 +} + +class RVCExpander( val XLen: Int, val usingCompressed: Boolean) extends Module { + val io = IO(new Bundle { + val in = Input(UInt(32.W)) + val out = Output(new ExpandedInstruction) + val rvc = Output(Bool()) + val legal = Output(Bool()) + val waleed_out = Output(UInt(32.W)) + //val q1_Out = Output(new ExpandedInstruction) + //val q2_Out = Output(new ExpandedInstruction) + //val q3_Out = Output(new ExpandedInstruction) + }) + if (usingCompressed) { + io.rvc := io.in(1,0) =/= 3.U + val inst = new RVCDecoder(io.in, XLen) + io.out := inst.decode + io.legal := (!io.in(13))&(!io.in(12))&(io.in(11))&io.in(1)&(!io.in(0)) | + (!io.in(13))&(!io.in(12))&(io.in(6))&io.in(1)&(!io.in(0)) | + (!io.in(15))&(!io.in(13))&io.in(11)(!io.in(1)) | + (!io.in(13))&(!io.in(12))&io.in(5)&io.in(1)&(!io.in(0)) | + (!io.in(13))&(!io.in(12))&io.in(10)&(!io.in(1))&io.in(0) | + (!io.in(15))&(!io.in(13))&io.in(6)&(!io.in(1)) | io.in(15)&(!io.in(12))&(!io.in(1))&io.in(0) | + (!io.in(13))&(!io.in(12))&io.in(9)&io.in(1)&(!io.in(0)) | + (!io.in(12))&io.in(6)&(!io.in(1))&io.in(0) | + (!io.in(15))&(!io.in(13))&io.in(5)&(!io.in(1)) | + (!io.in(13))&(!io.in(12))&io.in(8)&io.in(1)&(!io.in(0)) | + (!io.in(12))&io.in(5)&(!io.in(1))&io.in(0) | + (!io.in(15))&(!io.in(13))&io.in(10)&(!io.in(1)) | (!io.in(13))&(!io.in(12))&io.in(7)&io.in(1)&(!io.in(0)) | + io.in(12)&io.in(11)&(!io.in(10))&(!io.in(1))&io.in(0) | (!io.in(15))&(!io.in(13))&io.in(9)&(!io.in(1)) | + (!io.in(13))&(!io.in(12))&io.in(4)&io.in(1)&(!io.in(0)) | io.in(13)&io.in(12)&(!io.in(1))&io.in(0) | + (!io.in(15))&(!io.in(13))&io.in(8)&(!io.in(1)) | (!io.in(13))&(!io.in(12))&io.in(3)&io.in(1)&(!io.in(0)) | + io.in(13)&io.in(4)&(!io.in(1))&io.in(0) | (!io.in(13))&(!io.in(12))&io.in(2)&io.in(1)&(!io.in(0)) | + (!io.in(15))&(!io.in(13))&io.in(7)&(!io.in(1)) | io.in(13)&io.in(3)&(!io.in(1))&io.in(0) | + io.in(13)&io.in(2)&(!io.in(1))&io.in(0) | io.in(14)&(!io.in(13))&(!io.in(1)) | + (!io.in(14))&(!io.in(12))&(!io.in(1))&io.in(0) | io.in(15)&(!io.in(13))&io.in(12)&io.in(1)&(!io.in(0)) | + (!io.in(15))&(!io.in(13))&(!io.in(12))&io.in(1)&(!io.in(0)) | (!io.in(15))&(!io.in(13))&io.in(12)&(!io.in(1)) | + io.in(14)&(!io.in(13))&(!io.in(0)) + io.waleed_out := Mux(io.legal,io.out.bits,0.U) + } else { + io.rvc := false.B + io.out := new RVCDecoder(io.in, XLen).passthrough + } +} + diff --git a/src/main/scala/lib/exp.sc b/src/main/scala/lib/exp.sc new file mode 100644 index 00000000..e69de29b diff --git a/src/test/scala/lib/Tester.scala b/src/test/scala/lib/Tester.scala new file mode 100644 index 00000000..dcf36414 --- /dev/null +++ b/src/test/scala/lib/Tester.scala @@ -0,0 +1,31 @@ +package lib +import java.io.File + +import chisel3.iotesters +import chisel3.iotesters.{ChiselFlatSpec, Driver, PeekPokeTester} + +class Tester(c: encoder_generator) extends PeekPokeTester(c) { + + poke(c.io.in, 1) + println(s"output at ${peek(c.io.in)} = ${peek(c.io.out)}") + poke(c.io.in, 2) + println(s"output at ${peek(c.io.in)} = ${peek(c.io.out)}") + poke(c.io.in, 4) + println(s"output at ${peek(c.io.in)} = ${peek(c.io.out)}") + poke(c.io.in, 8) + println(s"output at ${peek(c.io.in)} = ${peek(c.io.out)}") + poke(c.io.in, 16) + println(s"output at ${peek(c.io.in)} = ${peek(c.io.out)}") + poke(c.io.in, 32) + println(s"output at ${peek(c.io.in)} = ${peek(c.io.out)}") + poke(c.io.in, 64) + println(s"output at ${peek(c.io.in)} = ${peek(c.io.out)}") + poke(c.io.in, 128) + println(s"output at ${peek(c.io.in)} = ${peek(c.io.out)}") +} + +object GCDMain extends App { + iotesters.Driver.execute(args, () => new encoder_generator(8)) { + c => new Tester(c) + } +} diff --git a/target/.history b/target/.history new file mode 100644 index 00000000..d6828caf --- /dev/null +++ b/target/.history @@ -0,0 +1 @@ +;set _root_.scala.collection.Seq(historyPath := None,shellPrompt := { _ => "" },SettingKey[_root_.scala.Option[_root_.sbt.File]]("sbtStructureOutputFile") in _root_.sbt.Global := _root_.scala.Some(_root_.sbt.file("/tmp/sbt-structure.xml")),SettingKey[_root_.java.lang.String]("sbtStructureOptions") in _root_.sbt.Global := "download, resolveClassifiers");apply -cp "/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-structure-extractor/scala_2.12/sbt_1.0/2018.2.1+4-88400d3f/jars/sbt-structure-extractor.jar" org.jetbrains.sbt.CreateTasks;*/*:dumpStructure diff --git a/target/scala-2.12/chisel-module-template_2.12-3.3.0-tests.jar b/target/scala-2.12/chisel-module-template_2.12-3.3.0-tests.jar new file mode 100644 index 00000000..c2778b3a Binary files /dev/null and b/target/scala-2.12/chisel-module-template_2.12-3.3.0-tests.jar differ diff --git a/target/scala-2.12/chisel-module-template_2.12-3.3.0.jar b/target/scala-2.12/chisel-module-template_2.12-3.3.0.jar new file mode 100644 index 00000000..3a26a8a4 Binary files /dev/null and b/target/scala-2.12/chisel-module-template_2.12-3.3.0.jar differ diff --git a/target/scala-2.12/classes/dec/dec$.class b/target/scala-2.12/classes/dec/dec$.class new file mode 100644 index 00000000..3634e2ed Binary files /dev/null and b/target/scala-2.12/classes/dec/dec$.class differ diff --git a/target/scala-2.12/classes/dec/dec$delayedInit$body.class b/target/scala-2.12/classes/dec/dec$delayedInit$body.class new file mode 100644 index 00000000..c6a4f70b Binary files /dev/null and b/target/scala-2.12/classes/dec/dec$delayedInit$body.class differ diff --git a/target/scala-2.12/classes/dec/dec.class b/target/scala-2.12/classes/dec/dec.class new file mode 100644 index 00000000..a4472f55 Binary files /dev/null and b/target/scala-2.12/classes/dec/dec.class differ diff --git a/target/scala-2.12/classes/dec/el2_dec_dec_ctl$$anon$1.class b/target/scala-2.12/classes/dec/el2_dec_dec_ctl$$anon$1.class new file mode 100644 index 00000000..2925cf49 Binary files /dev/null and b/target/scala-2.12/classes/dec/el2_dec_dec_ctl$$anon$1.class differ diff --git a/target/scala-2.12/classes/dec/el2_dec_dec_ctl.class b/target/scala-2.12/classes/dec/el2_dec_dec_ctl.class new file mode 100644 index 00000000..afc6d858 Binary files /dev/null and b/target/scala-2.12/classes/dec/el2_dec_dec_ctl.class differ diff --git a/target/scala-2.12/classes/dec/el2_dec_pkt_t.class b/target/scala-2.12/classes/dec/el2_dec_pkt_t.class new file mode 100644 index 00000000..fdcc20ea Binary files /dev/null and b/target/scala-2.12/classes/dec/el2_dec_pkt_t.class differ diff --git a/target/scala-2.12/classes/lib/ExpandedInstruction.class b/target/scala-2.12/classes/lib/ExpandedInstruction.class new file mode 100644 index 00000000..54eac644 Binary files /dev/null and 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+["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-library.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar","/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar"]] \ No newline at end of file diff --git a/target/streams/compile/_global/_global/discoveredMainClasses/data b/target/streams/compile/_global/_global/discoveredMainClasses/data new file mode 100644 index 00000000..313c2299 --- /dev/null +++ b/target/streams/compile/_global/_global/discoveredMainClasses/data @@ -0,0 +1 @@ +["dec.dec"] \ No newline at end of file diff --git a/target/streams/compile/_global/_global/managedSourcePaths/previous b/target/streams/compile/_global/_global/managedSourcePaths/previous new file mode 100644 index 00000000..a510b125 --- /dev/null +++ b/target/streams/compile/_global/_global/managedSourcePaths/previous @@ -0,0 +1 @@ +["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",[]] \ No newline at end of file diff --git a/target/streams/compile/compile/_global/streams/out b/target/streams/compile/compile/_global/streams/out new file mode 100644 index 00000000..95f4a31a --- /dev/null +++ b/target/streams/compile/compile/_global/streams/out @@ -0,0 +1,6 @@ +[error] /home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/dec/el2_dec_dec_ctl.scala:173:12: type mismatch; +[error]  found : Unit +[error]  required: dec.el2_dec_dec_ctl => chisel3.iotesters.PeekPokeTester[dec.el2_dec_dec_ctl] +[error]  println(chisel3.Driver.emitVerilog(new el2_dec_dec_ctl())) +[error]  ^ +[error] one error found diff --git a/target/streams/compile/compileIncSetup/_global/streams/inc_compile_2.12.zip b/target/streams/compile/compileIncSetup/_global/streams/inc_compile_2.12.zip new file mode 100644 index 00000000..516ae9f6 Binary files /dev/null and b/target/streams/compile/compileIncSetup/_global/streams/inc_compile_2.12.zip differ diff --git a/target/streams/compile/compileIncremental/_global/streams/export b/target/streams/compile/compileIncremental/_global/streams/export new file mode 100644 index 00000000..d28b6970 --- /dev/null +++ b/target/streams/compile/compileIncremental/_global/streams/export @@ -0,0 +1 @@ +scalac -bootclasspath /home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-library.jar -classpath /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar -Xplugin:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalamacros/paradise_2.12.10/2.1.0/paradise_2.12.10-2.1.0.jar -Xsource:2.11.0 /home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/lib/RVC.scala /home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/lib/GCD.scala /home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/dec/el2_dec_dec_ctl.scala diff --git a/target/streams/compile/compileIncremental/_global/streams/out b/target/streams/compile/compileIncremental/_global/streams/out new file mode 100644 index 00000000..5ba02d9c --- /dev/null +++ b/target/streams/compile/compileIncremental/_global/streams/out @@ -0,0 +1,30 @@ +[debug]  +[debug] Initial source changes:  +[debug]  removed:Set() +[debug]  added: Set() +[debug]  modified: Set(/home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/dec/el2_dec_dec_ctl.scala) +[debug] Invalidated products: Set(/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/encoder_generator.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/rvrangecheck.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/RVCExpander$$anon$1.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/caller$$anon$2.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/dec/dec$.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/rvrangecheck$.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/exp$$anon$9.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/RVCDecoder.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/rvdff$.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/RVCExpander.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/rvbradder.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/reg1.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/reg1$$anon$3.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/tocopy.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/rvdff$$anon$1.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/tocopy$$anon$8.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/dec/el2_dec_dec_ctl.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/dec/el2_dec_pkt_t.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/top$$anon$4.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/caller.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/encoder_generator$$anon$6.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/ExpandedInstruction.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/rvrangecheck$$anon$7.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/rvdff.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/rvbradder$$anon$5.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/exp.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/top.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/encoder_generator$.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/dec/dec.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/dec/dec$delayedInit$body.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/dec/el2_dec_dec_ctl$$anon$1.class) +[debug] External API changes: API Changes: Set() +[debug] Modified binary dependencies: Set() +[debug] Initial directly invalidated classes: Set(dec.dec, dec.el2_dec_dec_ctl, dec.el2_dec_pkt_t) +[debug]  +[debug] Sources indirectly invalidated by: +[debug]  product: Set(/home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/lib/RVC.scala, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/dec/el2_dec_dec_ctl.scala, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/lib/GCD.scala) +[debug]  binary dep: Set() +[debug]  external source: Set() +[debug] All sources are invalidated. +[debug] Initial set of included nodes: dec.dec, dec.el2_dec_dec_ctl, dec.el2_dec_pkt_t +[debug] Recompiling all sources: number of invalidated sources > 50.0% of all sources +[info] Compiling 3 Scala sources to /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes ... +[debug] Getting org.scala-sbt:compiler-bridge_2.12:1.3.5:compile for Scala 2.12.10 +[debug] Getting org.scala-sbt:compiler-bridge_2.12:1.3.5:compile for Scala 2.12.10 +[debug] [zinc] Running cached compiler 3e6bed8c for Scala compiler version 2.12.10 +[debug] [zinc] The Scala compiler is invoked with: +[debug]  -Xsource:2.11 +[debug]  -Xplugin:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalamacros/paradise_2.12.10/2.1.0/paradise_2.12.10-2.1.0.jar +[debug]  -bootclasspath +[debug]  /home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-library.jar +[debug]  -classpath +[debug]  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar +[debug] Compilation failed (CompilerInterface) +[error] (Compile / compileIncremental) Compilation failed diff --git a/target/streams/compile/copyResources/_global/streams/copy-resources b/target/streams/compile/copyResources/_global/streams/copy-resources new file mode 100644 index 00000000..9d348e7b --- /dev/null +++ b/target/streams/compile/copyResources/_global/streams/copy-resources @@ -0,0 +1 @@ +[[{},{}],{}] \ No newline at end of file diff --git a/target/streams/compile/copyResources/_global/streams/out b/target/streams/compile/copyResources/_global/streams/out new file mode 100644 index 00000000..f25042f2 --- /dev/null +++ b/target/streams/compile/copyResources/_global/streams/out @@ -0,0 +1,2 @@ +[debug] Copy resource mappings:  +[debug]   diff --git a/target/streams/compile/dependencyClasspath/_global/streams/export b/target/streams/compile/dependencyClasspath/_global/streams/export new file mode 100644 index 00000000..414eb951 --- /dev/null +++ b/target/streams/compile/dependencyClasspath/_global/streams/export @@ -0,0 +1 @@ +/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-library.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar diff --git a/target/streams/compile/exportedProductJars/_global/streams/export b/target/streams/compile/exportedProductJars/_global/streams/export new file mode 100644 index 00000000..2101d78b --- /dev/null +++ b/target/streams/compile/exportedProductJars/_global/streams/export @@ -0,0 +1 @@ +/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/chisel-module-template_2.12-3.3.0.jar diff --git a/target/streams/compile/exportedProducts/_global/streams/export b/target/streams/compile/exportedProducts/_global/streams/export new file mode 100644 index 00000000..e8935eaa --- /dev/null +++ b/target/streams/compile/exportedProducts/_global/streams/export @@ -0,0 +1 @@ +/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes diff --git a/target/streams/compile/externalDependencyClasspath/_global/streams/export b/target/streams/compile/externalDependencyClasspath/_global/streams/export new file mode 100644 index 00000000..414eb951 --- /dev/null +++ b/target/streams/compile/externalDependencyClasspath/_global/streams/export @@ -0,0 +1 @@ +/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-library.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar diff --git a/target/streams/compile/internalDependencyClasspath/_global/streams/export b/target/streams/compile/internalDependencyClasspath/_global/streams/export new file mode 100644 index 00000000..8b137891 --- /dev/null +++ b/target/streams/compile/internalDependencyClasspath/_global/streams/export @@ -0,0 +1 @@ + diff --git a/target/streams/compile/mainClass/_global/streams/out b/target/streams/compile/mainClass/_global/streams/out new file mode 100644 index 00000000..3309b6b1 --- /dev/null +++ b/target/streams/compile/mainClass/_global/streams/out @@ -0,0 +1 @@ +[warn] Multiple main classes detected. Run 'show discoveredMainClasses' to see the list diff --git a/target/streams/compile/managedClasspath/_global/streams/export b/target/streams/compile/managedClasspath/_global/streams/export new file mode 100644 index 00000000..414eb951 --- /dev/null +++ b/target/streams/compile/managedClasspath/_global/streams/export @@ -0,0 +1 @@ +/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-library.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar diff --git a/target/streams/compile/packageBin/_global/streams/inputs b/target/streams/compile/packageBin/_global/streams/inputs new file mode 100644 index 00000000..89751ac1 --- /dev/null +++ b/target/streams/compile/packageBin/_global/streams/inputs @@ -0,0 +1 @@ +1741114334 \ No newline at end of file diff --git a/target/streams/compile/packageBin/_global/streams/out b/target/streams/compile/packageBin/_global/streams/out new file mode 100644 index 00000000..32b1c817 --- /dev/null +++ b/target/streams/compile/packageBin/_global/streams/out @@ -0,0 +1,79 @@ +[debug] Packaging /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/chisel-module-template_2.12-3.3.0.jar ... +[debug] Input file mappings: +[debug]  lib +[debug]  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib +[debug]  lib/encoder_generator$$anon$6.class +[debug]  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/encoder_generator$$anon$6.class +[debug]  lib/ifu_compress$$anon$1.class +[debug]  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/ifu_compress$$anon$1.class +[debug]  lib/rvrangecheck.class +[debug]  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/rvrangecheck.class +[debug]  lib/reg1.class +[debug]  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/reg1.class +[debug]  lib/RVCDriver$.class +[debug]  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/RVCDriver$.class +[debug]  lib/rvrangecheck$.class +[debug]  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/rvrangecheck$.class +[debug]  lib/exp.class +[debug]  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/exp.class +[debug]  lib/top.class +[debug]  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/top.class +[debug]  lib/rvrangecheck$$anon$7.class +[debug]  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/rvrangecheck$$anon$7.class +[debug]  lib/reg1$$anon$3.class +[debug]  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/reg1$$anon$3.class +[debug]  lib/caller$$anon$2.class +[debug]  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/caller$$anon$2.class +[debug]  lib/RVCExpander$$anon$1.class +[debug]  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/RVCExpander$$anon$1.class +[debug]  lib/exp$$anon$9.class +[debug]  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/exp$$anon$9.class +[debug]  lib/tocopy$$anon$8.class +[debug]  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/tocopy$$anon$8.class +[debug]  lib/RVCExpander.class +[debug]  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/RVCExpander.class +[debug]  lib/rvbradder.class +[debug]  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/rvbradder.class +[debug]  lib/top$$anon$4.class +[debug]  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/top$$anon$4.class +[debug]  lib/rvbradder$$anon$5.class +[debug]  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/rvbradder$$anon$5.class +[debug]  lib/rvdff$$anon$1.class +[debug]  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/rvdff$$anon$1.class +[debug]  lib/RVCDriver.class +[debug]  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/RVCDriver.class +[debug]  lib/RVCDriver$delayedInit$body.class +[debug]  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/RVCDriver$delayedInit$body.class +[debug]  lib/RVCDecoder.class +[debug]  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/RVCDecoder.class +[debug]  lib/rvdff$.class +[debug]  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/rvdff$.class +[debug]  lib/tocopy.class +[debug]  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/tocopy.class +[debug]  lib/encoder_generator.class +[debug]  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/encoder_generator.class +[debug]  lib/ifu_compress.class +[debug]  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/ifu_compress.class +[debug]  lib/encoder_generator$.class +[debug]  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/encoder_generator$.class +[debug]  lib/caller.class +[debug]  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/caller.class +[debug]  lib/rvdff.class +[debug]  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/rvdff.class +[debug]  lib/ExpandedInstruction.class +[debug]  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/ExpandedInstruction.class +[debug]  dec +[debug]  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/dec +[debug]  dec/el2_dec_dec_ctl$$anon$1.class +[debug]  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/dec/el2_dec_dec_ctl$$anon$1.class +[debug]  dec/el2_dec_pkt_t.class +[debug]  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/dec/el2_dec_pkt_t.class +[debug]  dec/el2_dec_dec_ctl.class +[debug]  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/dec/el2_dec_dec_ctl.class +[debug]  dec/dec$.class +[debug]  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/dec/dec$.class +[debug]  dec/dec.class +[debug]  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/dec/dec.class +[debug]  dec/dec$delayedInit$body.class +[debug]  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/dec/dec$delayedInit$body.class +[debug] Done packaging. diff --git a/target/streams/compile/packageBin/_global/streams/output b/target/streams/compile/packageBin/_global/streams/output new file mode 100644 index 00000000..6522d77d --- /dev/null +++ b/target/streams/compile/packageBin/_global/streams/output @@ -0,0 +1 @@ +-1898733629 \ No newline at end of file diff --git a/target/streams/compile/run/_global/streams/out b/target/streams/compile/run/_global/streams/out new file mode 100644 index 00000000..e76d069c --- /dev/null +++ b/target/streams/compile/run/_global/streams/out @@ -0,0 +1,2 @@ +[error] Nonzero exit code: 1 +[error] (Compile / run) Nonzero exit code: 1 diff --git a/target/streams/compile/unmanagedClasspath/_global/streams/export b/target/streams/compile/unmanagedClasspath/_global/streams/export new file mode 100644 index 00000000..8b137891 --- /dev/null +++ b/target/streams/compile/unmanagedClasspath/_global/streams/export @@ -0,0 +1 @@ + diff --git a/target/streams/compile/unmanagedJars/_global/streams/export b/target/streams/compile/unmanagedJars/_global/streams/export new file mode 100644 index 00000000..8b137891 --- /dev/null +++ b/target/streams/compile/unmanagedJars/_global/streams/export @@ -0,0 +1 @@ + diff --git a/target/streams/runtime/dependencyClasspathAsJars/_global/streams/export b/target/streams/runtime/dependencyClasspathAsJars/_global/streams/export new file mode 100644 index 00000000..7a8afe52 --- /dev/null +++ b/target/streams/runtime/dependencyClasspathAsJars/_global/streams/export @@ -0,0 +1 @@ +/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/chisel-module-template_2.12-3.3.0.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-library.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar diff --git a/target/streams/runtime/exportedProductJars/_global/streams/export b/target/streams/runtime/exportedProductJars/_global/streams/export new file mode 100644 index 00000000..2101d78b --- /dev/null +++ b/target/streams/runtime/exportedProductJars/_global/streams/export @@ -0,0 +1 @@ +/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/chisel-module-template_2.12-3.3.0.jar diff --git a/target/streams/runtime/exportedProducts/_global/streams/export b/target/streams/runtime/exportedProducts/_global/streams/export new file mode 100644 index 00000000..1ca901b3 --- /dev/null +++ b/target/streams/runtime/exportedProducts/_global/streams/export @@ -0,0 +1 @@ +/home/waleedbinehsan/Desktop/SweRV-Chisel/target/scala-2.12/classes diff --git a/target/streams/runtime/externalDependencyClasspath/_global/streams/export b/target/streams/runtime/externalDependencyClasspath/_global/streams/export new file mode 100644 index 00000000..414eb951 --- /dev/null +++ b/target/streams/runtime/externalDependencyClasspath/_global/streams/export @@ -0,0 +1 @@ +/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-library.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar diff --git a/target/streams/runtime/fullClasspathAsJars/_global/streams/export b/target/streams/runtime/fullClasspathAsJars/_global/streams/export new file mode 100644 index 00000000..7a8afe52 --- /dev/null +++ b/target/streams/runtime/fullClasspathAsJars/_global/streams/export @@ -0,0 +1 @@ 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diff --git a/target/streams/runtime/internalDependencyAsJars/_global/streams/export b/target/streams/runtime/internalDependencyAsJars/_global/streams/export new file mode 100644 index 00000000..2101d78b --- /dev/null +++ b/target/streams/runtime/internalDependencyAsJars/_global/streams/export @@ -0,0 +1 @@ +/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/chisel-module-template_2.12-3.3.0.jar diff --git a/target/streams/runtime/managedClasspath/_global/streams/export b/target/streams/runtime/managedClasspath/_global/streams/export new file mode 100644 index 00000000..414eb951 --- /dev/null +++ b/target/streams/runtime/managedClasspath/_global/streams/export @@ -0,0 +1 @@ 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diff --git a/target/streams/runtime/unmanagedClasspath/_global/streams/export b/target/streams/runtime/unmanagedClasspath/_global/streams/export new file mode 100644 index 00000000..8b137891 --- /dev/null +++ b/target/streams/runtime/unmanagedClasspath/_global/streams/export @@ -0,0 +1 @@ + diff --git a/target/streams/runtime/unmanagedJars/_global/streams/export b/target/streams/runtime/unmanagedJars/_global/streams/export new file mode 100644 index 00000000..8b137891 --- /dev/null +++ b/target/streams/runtime/unmanagedJars/_global/streams/export @@ -0,0 +1 @@ + diff --git a/target/streams/test/_global/_global/compileBinaryFileInputs/previous b/target/streams/test/_global/_global/compileBinaryFileInputs/previous new file mode 100644 index 00000000..5644a8fb --- /dev/null +++ b/target/streams/test/_global/_global/compileBinaryFileInputs/previous @@ -0,0 +1 @@ +["sbt.Task[scala.collection.immutable.Map[java.lang.String, scala.collection.Seq[scala.Tuple2[java.nio.file.Path, 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\ No newline at end of file diff --git a/target/streams/test/_global/_global/compileOutputs/previous b/target/streams/test/_global/_global/compileOutputs/previous new file mode 100644 index 00000000..83946969 --- /dev/null +++ b/target/streams/test/_global/_global/compileOutputs/previous @@ -0,0 +1 @@ +["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/home/waleedbinehsan/Desktop/SweRV-Chisel/target/scala-2.12/test-classes/lib/GCDMain$.class","/home/waleedbinehsan/Desktop/SweRV-Chisel/target/scala-2.12/test-classes/lib/GCDMain$delayedInit$body.class","/home/waleedbinehsan/Desktop/SweRV-Chisel/target/scala-2.12/test-classes/lib/GCDMain.class","/home/waleedbinehsan/Desktop/SweRV-Chisel/target/scala-2.12/test-classes/lib/Tester.class","/home/waleedbinehsan/Desktop/SweRV-Chisel/target/streams/test/compileOutputs/_global/streams/inc_compile_2.12.zip"]] \ No newline at end of file diff --git a/target/streams/test/_global/_global/compileSourceFileInputs/previous b/target/streams/test/_global/_global/compileSourceFileInputs/previous new file mode 100644 index 00000000..5534f881 --- /dev/null +++ b/target/streams/test/_global/_global/compileSourceFileInputs/previous @@ -0,0 +1 @@ +["sbt.Task[scala.collection.immutable.Map[java.lang.String, scala.collection.Seq[scala.Tuple2[java.nio.file.Path, sbt.nio.FileStamp]]]]",{"2.12.10":{"hashes":[["/home/waleedbinehsan/Desktop/SweRV-Chisel/src/test/scala/lib/Tester.scala","637def267b3c0dce45e9e54ee1fd153173bb8c96"]],"lastModifiedTimes":[]}}] \ No newline at end of file diff --git a/target/streams/test/_global/_global/definedTestNames/data b/target/streams/test/_global/_global/definedTestNames/data new file mode 100644 index 00000000..0637a088 --- /dev/null +++ b/target/streams/test/_global/_global/definedTestNames/data @@ -0,0 +1 @@ +[] \ No newline at end of file diff --git a/target/streams/test/_global/_global/dependencyClasspathFiles/previous b/target/streams/test/_global/_global/dependencyClasspathFiles/previous new file mode 100644 index 00000000..50e0cf77 --- /dev/null +++ b/target/streams/test/_global/_global/dependencyClasspathFiles/previous @@ -0,0 +1 @@ +["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/home/waleedbinehsan/Desktop/SweRV-Chisel/target/scala-2.12/classes","/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-library.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar","/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar","/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar"]] \ No newline at end of file diff --git a/target/streams/test/_global/_global/discoveredMainClasses/data b/target/streams/test/_global/_global/discoveredMainClasses/data new file mode 100644 index 00000000..07365fed --- /dev/null +++ b/target/streams/test/_global/_global/discoveredMainClasses/data @@ -0,0 +1 @@ +["lib.GCDMain"] \ No newline at end of file diff --git a/target/streams/test/_global/_global/managedSourcePaths/previous b/target/streams/test/_global/_global/managedSourcePaths/previous new file mode 100644 index 00000000..a510b125 --- /dev/null +++ b/target/streams/test/_global/_global/managedSourcePaths/previous @@ -0,0 +1 @@ +["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",[]] \ No newline at end of file diff --git a/target/streams/test/compile/_global/streams/out b/target/streams/test/compile/_global/streams/out new file mode 100644 index 00000000..6e9b1a83 --- /dev/null +++ b/target/streams/test/compile/_global/streams/out @@ -0,0 +1,2 @@ +[warn] there were 24 feature warnings; re-run with -feature for details +[warn] one warning found diff --git a/target/streams/test/compileIncSetup/_global/streams/inc_compile_2.12.zip b/target/streams/test/compileIncSetup/_global/streams/inc_compile_2.12.zip new file mode 100644 index 00000000..d5fb3e40 Binary files /dev/null and b/target/streams/test/compileIncSetup/_global/streams/inc_compile_2.12.zip differ diff --git a/target/streams/test/compileIncremental/_global/streams/export b/target/streams/test/compileIncremental/_global/streams/export new file mode 100644 index 00000000..e1458bc3 --- /dev/null +++ b/target/streams/test/compileIncremental/_global/streams/export @@ -0,0 +1 @@ +scalac -bootclasspath /home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-library.jar -classpath /home/waleedbinehsan/Desktop/SweRV-Chisel/target/scala-2.12/test-classes:/home/waleedbinehsan/Desktop/SweRV-Chisel/target/scala-2.12/classes:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar -Xplugin:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalamacros/paradise_2.12.10/2.1.0/paradise_2.12.10-2.1.0.jar -Xsource:2.11.0 /home/waleedbinehsan/Desktop/SweRV-Chisel/src/test/scala/lib/Tester.scala diff --git a/target/streams/test/compileIncremental/_global/streams/out b/target/streams/test/compileIncremental/_global/streams/out new file mode 100644 index 00000000..f0eadf79 --- /dev/null +++ b/target/streams/test/compileIncremental/_global/streams/out @@ -0,0 +1,30 @@ +[debug]  +[debug] Initial source changes:  +[debug]  removed:Set() +[debug]  added: Set() +[debug]  modified: Set(/home/waleedbinehsan/Desktop/SweRV-Chisel/src/test/scala/lib/Tester.scala) +[debug] Invalidated products: Set() +[debug] External API changes: API Changes: Set() +[debug] Modified binary dependencies: Set() +[debug] Initial directly invalidated classes: Set(lib.Tester, lib.GCDMain) +[debug]  +[debug] Sources indirectly invalidated by: +[debug]  product: Set() +[debug]  binary dep: Set() +[debug]  external source: Set() +[debug] All sources are invalidated. +[debug] Initial set of included nodes: lib.Tester, lib.GCDMain +[debug] Recompiling all sources: number of invalidated sources > 50.0% of all sources +[info] Compiling 1 Scala source to /home/waleedbinehsan/Desktop/SweRV-Chisel/target/scala-2.12/test-classes ... +[debug] Getting org.scala-sbt:compiler-bridge_2.12:1.3.5:compile for Scala 2.12.10 +[debug] Getting org.scala-sbt:compiler-bridge_2.12:1.3.5:compile for Scala 2.12.10 +[debug] [zinc] Running cached compiler 230db6de for Scala compiler version 2.12.10 +[debug] [zinc] The Scala compiler is invoked with: +[debug]  -Xsource:2.11 +[debug]  -Xplugin:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalamacros/paradise_2.12.10/2.1.0/paradise_2.12.10-2.1.0.jar +[debug]  -bootclasspath +[debug]  /home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-library.jar +[debug]  -classpath +[debug]  /home/waleedbinehsan/Desktop/SweRV-Chisel/target/scala-2.12/test-classes:/home/waleedbinehsan/Desktop/SweRV-Chisel/target/scala-2.12/classes:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar +[debug] Scala compilation took 3.591996551 s +[debug] Done compiling. diff --git a/target/streams/test/copyResources/_global/streams/copy-resources b/target/streams/test/copyResources/_global/streams/copy-resources new file mode 100644 index 00000000..9d348e7b --- /dev/null +++ b/target/streams/test/copyResources/_global/streams/copy-resources @@ -0,0 +1 @@ +[[{},{}],{}] \ No newline at end of file diff --git a/target/streams/test/copyResources/_global/streams/out b/target/streams/test/copyResources/_global/streams/out new file mode 100644 index 00000000..f25042f2 --- /dev/null +++ b/target/streams/test/copyResources/_global/streams/out @@ -0,0 +1,2 @@ +[debug] Copy resource mappings:  +[debug]   diff --git a/target/streams/test/definedTests/_global/streams/out b/target/streams/test/definedTests/_global/streams/out new file mode 100644 index 00000000..3c4f9cd9 --- /dev/null +++ b/target/streams/test/definedTests/_global/streams/out @@ -0,0 +1,2 @@ +[debug] Subclass fingerprints: List((org.scalacheck.Properties,false,org.scalacheck.ScalaCheckFramework$$anon$5@5736b32b), (org.scalacheck.Prop,false,org.scalacheck.ScalaCheckFramework$$anon$5@27be27a1), (org.scalacheck.Properties,true,org.scalacheck.ScalaCheckFramework$$anon$5@3c80ee2f), (org.scalacheck.Prop,true,org.scalacheck.ScalaCheckFramework$$anon$5@48ec02a3), (org.scalatest.Suite,false,org.scalatest.tools.Framework$$anon$1@2a214f7e)) +[debug] Annotation fingerprints: List((org.scalatest.WrapWith,false,org.scalatest.tools.Framework$$anon$2@47be8e93)) diff --git a/target/streams/test/dependencyClasspath/_global/streams/export b/target/streams/test/dependencyClasspath/_global/streams/export new file mode 100644 index 00000000..7ca4d19a --- /dev/null +++ b/target/streams/test/dependencyClasspath/_global/streams/export @@ -0,0 +1 @@ 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diff --git a/target/streams/test/dependencyClasspathAsJars/_global/streams/export b/target/streams/test/dependencyClasspathAsJars/_global/streams/export new file mode 100644 index 00000000..9d3ea95a --- /dev/null +++ b/target/streams/test/dependencyClasspathAsJars/_global/streams/export @@ -0,0 +1 @@ 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diff --git a/target/streams/test/exportedProductJars/_global/streams/export b/target/streams/test/exportedProductJars/_global/streams/export new file mode 100644 index 00000000..79e89e72 --- /dev/null +++ b/target/streams/test/exportedProductJars/_global/streams/export @@ -0,0 +1 @@ +/home/waleedbinehsan/Desktop/SweRV-Chisel/target/scala-2.12/chisel-module-template_2.12-3.3.0-tests.jar diff --git a/target/streams/test/exportedProducts/_global/streams/export b/target/streams/test/exportedProducts/_global/streams/export new file mode 100644 index 00000000..abbe338d --- /dev/null +++ b/target/streams/test/exportedProducts/_global/streams/export @@ -0,0 +1 @@ +/home/waleedbinehsan/Desktop/SweRV-Chisel/target/scala-2.12/test-classes diff --git a/target/streams/test/externalDependencyClasspath/_global/streams/export b/target/streams/test/externalDependencyClasspath/_global/streams/export new file mode 100644 index 00000000..414eb951 --- /dev/null +++ b/target/streams/test/externalDependencyClasspath/_global/streams/export @@ -0,0 +1 @@ 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diff --git a/target/streams/test/fullClasspath/_global/streams/export b/target/streams/test/fullClasspath/_global/streams/export new file mode 100644 index 00000000..84483c0e --- /dev/null +++ b/target/streams/test/fullClasspath/_global/streams/export @@ -0,0 +1 @@ +/home/waleedbinehsan/Desktop/SweRV-Chisel/target/scala-2.12/test-classes:/home/waleedbinehsan/Desktop/SweRV-Chisel/target/scala-2.12/classes:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-library.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar diff --git a/target/streams/test/fullClasspathAsJars/_global/streams/export b/target/streams/test/fullClasspathAsJars/_global/streams/export new file mode 100644 index 00000000..4abf0bc8 --- /dev/null +++ b/target/streams/test/fullClasspathAsJars/_global/streams/export @@ -0,0 +1 @@ +/home/waleedbinehsan/Desktop/SweRV-Chisel/target/scala-2.12/chisel-module-template_2.12-3.3.0-tests.jar:/home/waleedbinehsan/Desktop/SweRV-Chisel/target/scala-2.12/chisel-module-template_2.12-3.3.0.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-library.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar diff --git a/target/streams/test/internalDependencyAsJars/_global/streams/export b/target/streams/test/internalDependencyAsJars/_global/streams/export new file mode 100644 index 00000000..6950ec25 --- /dev/null +++ b/target/streams/test/internalDependencyAsJars/_global/streams/export @@ -0,0 +1 @@ +/home/waleedbinehsan/Desktop/SweRV-Chisel/target/scala-2.12/chisel-module-template_2.12-3.3.0.jar diff --git a/target/streams/test/internalDependencyClasspath/_global/streams/export b/target/streams/test/internalDependencyClasspath/_global/streams/export new file mode 100644 index 00000000..1ca901b3 --- /dev/null +++ b/target/streams/test/internalDependencyClasspath/_global/streams/export @@ -0,0 +1 @@ +/home/waleedbinehsan/Desktop/SweRV-Chisel/target/scala-2.12/classes diff --git a/target/streams/test/loadedTestFrameworks/_global/streams/out b/target/streams/test/loadedTestFrameworks/_global/streams/out new file mode 100644 index 00000000..6693f78e --- /dev/null +++ b/target/streams/test/loadedTestFrameworks/_global/streams/out @@ -0,0 +1,4 @@ +[debug] Framework implementation 'org.specs2.runner.Specs2Framework' not present. +[debug] Framework implementation 'org.specs2.runner.SpecsFramework' not present. +[debug] Framework implementation 'org.specs.runner.SpecsFramework' not present. +[debug] Framework implementation 'com.novocode.junit.JUnitFramework' not present. diff --git a/target/streams/test/mainClass/_global/streams/out b/target/streams/test/mainClass/_global/streams/out new file mode 100644 index 00000000..e69de29b diff --git a/target/streams/test/managedClasspath/_global/streams/export b/target/streams/test/managedClasspath/_global/streams/export new file mode 100644 index 00000000..414eb951 --- /dev/null +++ b/target/streams/test/managedClasspath/_global/streams/export @@ -0,0 +1 @@ +/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-library.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar diff --git a/target/streams/test/packageBin/_global/streams/inputs b/target/streams/test/packageBin/_global/streams/inputs new file mode 100644 index 00000000..37197e49 --- /dev/null +++ b/target/streams/test/packageBin/_global/streams/inputs @@ -0,0 +1 @@ +247105340 \ No newline at end of file diff --git a/target/streams/test/packageBin/_global/streams/out b/target/streams/test/packageBin/_global/streams/out new file mode 100644 index 00000000..52a94cda --- /dev/null +++ b/target/streams/test/packageBin/_global/streams/out @@ -0,0 +1,13 @@ +[debug] Packaging /home/waleedbinehsan/Desktop/SweRV-Chisel/target/scala-2.12/chisel-module-template_2.12-3.3.0-tests.jar ... +[debug] Input file mappings: +[debug]  lib +[debug]  /home/waleedbinehsan/Desktop/SweRV-Chisel/target/scala-2.12/test-classes/lib +[debug]  lib/GCDMain$.class +[debug]  /home/waleedbinehsan/Desktop/SweRV-Chisel/target/scala-2.12/test-classes/lib/GCDMain$.class +[debug]  lib/GCDMain$delayedInit$body.class +[debug]  /home/waleedbinehsan/Desktop/SweRV-Chisel/target/scala-2.12/test-classes/lib/GCDMain$delayedInit$body.class +[debug]  lib/Tester.class +[debug]  /home/waleedbinehsan/Desktop/SweRV-Chisel/target/scala-2.12/test-classes/lib/Tester.class +[debug]  lib/GCDMain.class +[debug]  /home/waleedbinehsan/Desktop/SweRV-Chisel/target/scala-2.12/test-classes/lib/GCDMain.class +[debug] Done packaging. diff --git a/target/streams/test/packageBin/_global/streams/output b/target/streams/test/packageBin/_global/streams/output new file mode 100644 index 00000000..6c444046 --- /dev/null +++ b/target/streams/test/packageBin/_global/streams/output @@ -0,0 +1 @@ +-344386520 \ No newline at end of file diff --git a/target/streams/test/unmanagedClasspath/_global/streams/export b/target/streams/test/unmanagedClasspath/_global/streams/export new file mode 100644 index 00000000..8b137891 --- /dev/null +++ b/target/streams/test/unmanagedClasspath/_global/streams/export @@ -0,0 +1 @@ + diff --git a/target/streams/test/unmanagedJars/_global/streams/export b/target/streams/test/unmanagedJars/_global/streams/export new file mode 100644 index 00000000..8b137891 --- /dev/null +++ b/target/streams/test/unmanagedJars/_global/streams/export @@ -0,0 +1 @@ + diff --git a/test_run_dir/lib.GCDMain1071336978/encoder_generator.anno.json b/test_run_dir/lib.GCDMain1071336978/encoder_generator.anno.json new file mode 100644 index 00000000..70bb33ce --- /dev/null +++ b/test_run_dir/lib.GCDMain1071336978/encoder_generator.anno.json @@ -0,0 +1,31 @@ +[ + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~encoder_generator|encoder_generator>io_out", + "sources":[ + "~encoder_generator|encoder_generator>io_in" + ] + }, + { + "class":"logger.LogLevelAnnotation", + "globalLogLevel":{ + + } + }, + { + "class":"firrtl.options.TargetDirAnnotation", + "directory":"test_run_dir/lib.GCDMain1071336978" + }, + { + "class":"firrtl.options.OutputAnnotationFileAnnotation", + "file":"encoder_generator" + }, + { + "class":"firrtl.EmitCircuitAnnotation", + "emitter":"firrtl.VerilogEmitter" + }, + { + "class":"firrtl.transforms.BlackBoxTargetDirAnno", + "targetDir":"test_run_dir/lib.GCDMain1071336978" + } +] \ No newline at end of file diff --git a/test_run_dir/lib.GCDMain1071336978/encoder_generator.fir b/test_run_dir/lib.GCDMain1071336978/encoder_generator.fir new file mode 100644 index 00000000..f1eb01ef --- /dev/null +++ b/test_run_dir/lib.GCDMain1071336978/encoder_generator.fir @@ -0,0 +1,22 @@ +;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10 +circuit encoder_generator : + module encoder_generator : + input clock : Clock + input reset : UInt<1> + output io : {flip in : UInt<4>, out : UInt<2>} + + node _T = bits(io.in, 0, 0) @[Mux.scala 29:36] + node _T_1 = bits(io.in, 1, 1) @[Mux.scala 29:36] + node _T_2 = bits(io.in, 2, 2) @[Mux.scala 29:36] + node _T_3 = bits(io.in, 3, 3) @[Mux.scala 29:36] + node _T_4 = mux(_T, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_5 = mux(_T_1, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_6 = mux(_T_2, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_7 = mux(_T_3, UInt<2>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_8 = or(_T_4, _T_5) @[Mux.scala 27:72] + node _T_9 = or(_T_8, _T_6) @[Mux.scala 27:72] + node _T_10 = or(_T_9, _T_7) @[Mux.scala 27:72] + wire _T_11 : UInt<2> @[Mux.scala 27:72] + _T_11 <= _T_10 @[Mux.scala 27:72] + io.out <= _T_11 @[GCD.scala 74:10] + diff --git a/test_run_dir/lib.GCDMain1071336978/encoder_generator.v b/test_run_dir/lib.GCDMain1071336978/encoder_generator.v new file mode 100644 index 00000000..2ff9a54f --- /dev/null +++ b/test_run_dir/lib.GCDMain1071336978/encoder_generator.v @@ -0,0 +1,12 @@ +module encoder_generator( + input clock, + input reset, + input [3:0] io_in, + output [1:0] io_out +); + wire [1:0] _T_6 = io_in[2] ? 2'h2 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_7 = io_in[3] ? 2'h3 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _GEN_0 = {{1'd0}, io_in[1]}; // @[Mux.scala 27:72] + wire [1:0] _T_9 = _GEN_0 | _T_6; // @[Mux.scala 27:72] + assign io_out = _T_9 | _T_7; // @[GCD.scala 74:10] +endmodule diff --git a/test_run_dir/lib.GCDMain107157556/encoder_generator.anno.json b/test_run_dir/lib.GCDMain107157556/encoder_generator.anno.json new file mode 100644 index 00000000..b691a66d --- /dev/null +++ b/test_run_dir/lib.GCDMain107157556/encoder_generator.anno.json @@ -0,0 +1,31 @@ +[ + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~encoder_generator|encoder_generator>io_out", + "sources":[ + "~encoder_generator|encoder_generator>io_in" + ] + }, + { + "class":"logger.LogLevelAnnotation", + "globalLogLevel":{ + + } + }, + { + "class":"firrtl.options.TargetDirAnnotation", + "directory":"test_run_dir/lib.GCDMain107157556" + }, + { + "class":"firrtl.options.OutputAnnotationFileAnnotation", + "file":"encoder_generator" + }, + { + "class":"firrtl.EmitCircuitAnnotation", + "emitter":"firrtl.VerilogEmitter" + }, + { + "class":"firrtl.transforms.BlackBoxTargetDirAnno", + "targetDir":"test_run_dir/lib.GCDMain107157556" + } +] \ No newline at end of file diff --git a/test_run_dir/lib.GCDMain107157556/encoder_generator.fir b/test_run_dir/lib.GCDMain107157556/encoder_generator.fir new file mode 100644 index 00000000..f1eb01ef --- /dev/null +++ b/test_run_dir/lib.GCDMain107157556/encoder_generator.fir @@ -0,0 +1,22 @@ +;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10 +circuit encoder_generator : + module encoder_generator : + input clock : Clock + input reset : UInt<1> + output io : {flip in : UInt<4>, out : UInt<2>} + + node _T = bits(io.in, 0, 0) @[Mux.scala 29:36] + node _T_1 = bits(io.in, 1, 1) @[Mux.scala 29:36] + node _T_2 = bits(io.in, 2, 2) @[Mux.scala 29:36] + node _T_3 = bits(io.in, 3, 3) @[Mux.scala 29:36] + node _T_4 = mux(_T, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_5 = mux(_T_1, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_6 = mux(_T_2, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_7 = mux(_T_3, UInt<2>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_8 = or(_T_4, _T_5) @[Mux.scala 27:72] + node _T_9 = or(_T_8, _T_6) @[Mux.scala 27:72] + node _T_10 = or(_T_9, _T_7) @[Mux.scala 27:72] + wire _T_11 : UInt<2> @[Mux.scala 27:72] + _T_11 <= _T_10 @[Mux.scala 27:72] + io.out <= _T_11 @[GCD.scala 74:10] + diff --git a/test_run_dir/lib.GCDMain107157556/encoder_generator.v b/test_run_dir/lib.GCDMain107157556/encoder_generator.v new file mode 100644 index 00000000..2ff9a54f --- /dev/null +++ b/test_run_dir/lib.GCDMain107157556/encoder_generator.v @@ -0,0 +1,12 @@ +module encoder_generator( + input clock, + input reset, + input [3:0] io_in, + output [1:0] io_out +); + wire [1:0] _T_6 = io_in[2] ? 2'h2 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_7 = io_in[3] ? 2'h3 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _GEN_0 = {{1'd0}, io_in[1]}; // @[Mux.scala 27:72] + wire [1:0] _T_9 = _GEN_0 | _T_6; // @[Mux.scala 27:72] + assign io_out = _T_9 | _T_7; // @[GCD.scala 74:10] +endmodule diff --git a/test_run_dir/lib.GCDMain166617760/RVCExpander.anno.json b/test_run_dir/lib.GCDMain166617760/RVCExpander.anno.json new file mode 100644 index 00000000..14cae659 --- /dev/null +++ b/test_run_dir/lib.GCDMain166617760/RVCExpander.anno.json @@ -0,0 +1,82 @@ +[ + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~RVCExpander|RVCExpander>io_waleed_out", + "sources":[ + "~RVCExpander|RVCExpander>io_legal", + "~RVCExpander|RVCExpander>io_out_bits", + "~RVCExpander|RVCExpander>io_in" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~RVCExpander|RVCExpander>io_out_rs2", + "sources":[ + "~RVCExpander|RVCExpander>io_in" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~RVCExpander|RVCExpander>io_out_rd", + "sources":[ + "~RVCExpander|RVCExpander>io_in" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~RVCExpander|RVCExpander>io_out_rs1", + "sources":[ + "~RVCExpander|RVCExpander>io_in" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~RVCExpander|RVCExpander>io_legal", + "sources":[ + "~RVCExpander|RVCExpander>io_in" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~RVCExpander|RVCExpander>io_out_bits", + "sources":[ + "~RVCExpander|RVCExpander>io_in" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~RVCExpander|RVCExpander>io_rvc", + "sources":[ + "~RVCExpander|RVCExpander>io_in" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~RVCExpander|RVCExpander>io_out_rs3", + "sources":[ + "~RVCExpander|RVCExpander>io_in" + ] + }, + { + "class":"logger.LogLevelAnnotation", + "globalLogLevel":{ + + } + }, + { + "class":"firrtl.options.TargetDirAnnotation", + "directory":"test_run_dir/lib.GCDMain166617760" + }, + { + "class":"firrtl.options.OutputAnnotationFileAnnotation", + "file":"RVCExpander" + }, + { + "class":"firrtl.EmitCircuitAnnotation", + "emitter":"firrtl.VerilogEmitter" + }, + { + "class":"firrtl.transforms.BlackBoxTargetDirAnno", + "targetDir":"test_run_dir/lib.GCDMain166617760" + } +] \ No newline at end of file diff --git a/test_run_dir/lib.GCDMain166617760/RVCExpander.fir b/test_run_dir/lib.GCDMain166617760/RVCExpander.fir new file mode 100644 index 00000000..64ecb9b8 --- /dev/null +++ b/test_run_dir/lib.GCDMain166617760/RVCExpander.fir @@ -0,0 +1,1617 @@ +;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10 +circuit RVCExpander : + module RVCExpander : + input clock : Clock + input reset : UInt<1> + output io : {flip in : UInt<32>, out : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}, rvc : UInt<1>, legal : UInt<1>, waleed_out : UInt<32>} + + node _T = bits(io.in, 1, 0) @[RVC.scala 202:20] + node _T_1 = neq(_T, UInt<2>("h03")) @[RVC.scala 202:26] + io.rvc <= _T_1 @[RVC.scala 202:12] + node _T_2 = bits(io.in, 12, 5) @[RVC.scala 58:22] + node _T_3 = orr(_T_2) @[RVC.scala 58:29] + node _T_4 = mux(_T_3, UInt<7>("h013"), UInt<7>("h01f")) @[RVC.scala 58:20] + node _T_5 = bits(io.in, 10, 7) @[RVC.scala 39:26] + node _T_6 = bits(io.in, 12, 11) @[RVC.scala 39:35] + node _T_7 = bits(io.in, 5, 5) @[RVC.scala 39:45] + node _T_8 = bits(io.in, 6, 6) @[RVC.scala 39:51] + node _T_9 = cat(_T_8, UInt<2>("h00")) @[Cat.scala 29:58] + node _T_10 = cat(_T_5, _T_6) @[Cat.scala 29:58] + node _T_11 = cat(_T_10, _T_7) @[Cat.scala 29:58] + node _T_12 = cat(_T_11, _T_9) @[Cat.scala 29:58] + node _T_13 = bits(io.in, 4, 2) @[RVC.scala 36:29] + node _T_14 = cat(UInt<2>("h01"), _T_13) @[Cat.scala 29:58] + node _T_15 = cat(_T_14, _T_4) @[Cat.scala 29:58] + node _T_16 = cat(_T_12, UInt<5>("h02")) @[Cat.scala 29:58] + node _T_17 = cat(_T_16, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_18 = cat(_T_17, _T_15) @[Cat.scala 29:58] + node _T_19 = bits(io.in, 4, 2) @[RVC.scala 36:29] + node _T_20 = cat(UInt<2>("h01"), _T_19) @[Cat.scala 29:58] + node _T_21 = bits(io.in, 4, 2) @[RVC.scala 36:29] + node _T_22 = cat(UInt<2>("h01"), _T_21) @[Cat.scala 29:58] + node _T_23 = bits(io.in, 31, 27) @[RVC.scala 25:101] + wire _T_24 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 26:19] + _T_24.bits <= _T_18 @[RVC.scala 27:14] + _T_24.rd <= _T_20 @[RVC.scala 28:12] + _T_24.rs1 <= UInt<5>("h02") @[RVC.scala 29:13] + _T_24.rs2 <= _T_22 @[RVC.scala 30:13] + _T_24.rs3 <= _T_23 @[RVC.scala 31:13] + node _T_25 = bits(io.in, 6, 5) @[RVC.scala 41:20] + node _T_26 = bits(io.in, 12, 10) @[RVC.scala 41:28] + node _T_27 = cat(_T_25, _T_26) @[Cat.scala 29:58] + node _T_28 = cat(_T_27, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_29 = bits(io.in, 9, 7) @[RVC.scala 35:29] + node _T_30 = cat(UInt<2>("h01"), _T_29) @[Cat.scala 29:58] + node _T_31 = bits(io.in, 4, 2) @[RVC.scala 36:29] + node _T_32 = cat(UInt<2>("h01"), _T_31) @[Cat.scala 29:58] + node _T_33 = cat(_T_32, UInt<7>("h07")) @[Cat.scala 29:58] + node _T_34 = cat(_T_28, _T_30) @[Cat.scala 29:58] + node _T_35 = cat(_T_34, UInt<3>("h03")) @[Cat.scala 29:58] + node _T_36 = cat(_T_35, _T_33) @[Cat.scala 29:58] + node _T_37 = bits(io.in, 4, 2) @[RVC.scala 36:29] + node _T_38 = cat(UInt<2>("h01"), _T_37) @[Cat.scala 29:58] + node _T_39 = bits(io.in, 9, 7) @[RVC.scala 35:29] + node _T_40 = cat(UInt<2>("h01"), _T_39) @[Cat.scala 29:58] + node _T_41 = bits(io.in, 4, 2) @[RVC.scala 36:29] + node _T_42 = cat(UInt<2>("h01"), _T_41) @[Cat.scala 29:58] + node _T_43 = bits(io.in, 31, 27) @[RVC.scala 25:101] + wire _T_44 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 26:19] + _T_44.bits <= _T_36 @[RVC.scala 27:14] + _T_44.rd <= _T_38 @[RVC.scala 28:12] + _T_44.rs1 <= _T_40 @[RVC.scala 29:13] + _T_44.rs2 <= _T_42 @[RVC.scala 30:13] + _T_44.rs3 <= _T_43 @[RVC.scala 31:13] + node _T_45 = bits(io.in, 5, 5) @[RVC.scala 40:20] + node _T_46 = bits(io.in, 12, 10) @[RVC.scala 40:26] + node _T_47 = bits(io.in, 6, 6) @[RVC.scala 40:36] + node _T_48 = cat(_T_47, UInt<2>("h00")) @[Cat.scala 29:58] + node _T_49 = cat(_T_45, _T_46) @[Cat.scala 29:58] + node _T_50 = cat(_T_49, _T_48) @[Cat.scala 29:58] + node _T_51 = bits(io.in, 9, 7) @[RVC.scala 35:29] + node _T_52 = cat(UInt<2>("h01"), _T_51) @[Cat.scala 29:58] + node _T_53 = bits(io.in, 4, 2) @[RVC.scala 36:29] + node _T_54 = cat(UInt<2>("h01"), _T_53) @[Cat.scala 29:58] + node _T_55 = cat(_T_54, UInt<7>("h03")) @[Cat.scala 29:58] + node _T_56 = cat(_T_50, _T_52) @[Cat.scala 29:58] + node _T_57 = cat(_T_56, UInt<3>("h02")) @[Cat.scala 29:58] + node _T_58 = cat(_T_57, _T_55) @[Cat.scala 29:58] + node _T_59 = bits(io.in, 4, 2) @[RVC.scala 36:29] + node _T_60 = cat(UInt<2>("h01"), _T_59) @[Cat.scala 29:58] + node _T_61 = bits(io.in, 9, 7) @[RVC.scala 35:29] + node _T_62 = cat(UInt<2>("h01"), _T_61) @[Cat.scala 29:58] + node _T_63 = bits(io.in, 4, 2) @[RVC.scala 36:29] + node _T_64 = cat(UInt<2>("h01"), _T_63) @[Cat.scala 29:58] + node _T_65 = bits(io.in, 31, 27) @[RVC.scala 25:101] + wire _T_66 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 26:19] + _T_66.bits <= _T_58 @[RVC.scala 27:14] + _T_66.rd <= _T_60 @[RVC.scala 28:12] + _T_66.rs1 <= _T_62 @[RVC.scala 29:13] + _T_66.rs2 <= _T_64 @[RVC.scala 30:13] + _T_66.rs3 <= _T_65 @[RVC.scala 31:13] + node _T_67 = bits(io.in, 5, 5) @[RVC.scala 40:20] + node _T_68 = bits(io.in, 12, 10) @[RVC.scala 40:26] + node _T_69 = bits(io.in, 6, 6) @[RVC.scala 40:36] + node _T_70 = cat(_T_69, UInt<2>("h00")) @[Cat.scala 29:58] + node _T_71 = cat(_T_67, _T_68) @[Cat.scala 29:58] + node _T_72 = cat(_T_71, _T_70) @[Cat.scala 29:58] + node _T_73 = bits(io.in, 9, 7) @[RVC.scala 35:29] + node _T_74 = cat(UInt<2>("h01"), _T_73) @[Cat.scala 29:58] + node _T_75 = bits(io.in, 4, 2) @[RVC.scala 36:29] + node _T_76 = cat(UInt<2>("h01"), _T_75) @[Cat.scala 29:58] + node _T_77 = cat(_T_76, UInt<7>("h07")) @[Cat.scala 29:58] + node _T_78 = cat(_T_72, _T_74) @[Cat.scala 29:58] + node _T_79 = cat(_T_78, UInt<3>("h02")) @[Cat.scala 29:58] + node _T_80 = cat(_T_79, _T_77) @[Cat.scala 29:58] + node _T_81 = bits(io.in, 4, 2) @[RVC.scala 36:29] + node _T_82 = cat(UInt<2>("h01"), _T_81) @[Cat.scala 29:58] + node _T_83 = bits(io.in, 9, 7) @[RVC.scala 35:29] + node _T_84 = cat(UInt<2>("h01"), _T_83) @[Cat.scala 29:58] + node _T_85 = bits(io.in, 4, 2) @[RVC.scala 36:29] + node _T_86 = cat(UInt<2>("h01"), _T_85) @[Cat.scala 29:58] + node _T_87 = bits(io.in, 31, 27) @[RVC.scala 25:101] + wire _T_88 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 26:19] + _T_88.bits <= _T_80 @[RVC.scala 27:14] + _T_88.rd <= _T_82 @[RVC.scala 28:12] + _T_88.rs1 <= _T_84 @[RVC.scala 29:13] + _T_88.rs2 <= _T_86 @[RVC.scala 30:13] + _T_88.rs3 <= _T_87 @[RVC.scala 31:13] + node _T_89 = bits(io.in, 5, 5) @[RVC.scala 40:20] + node _T_90 = bits(io.in, 12, 10) @[RVC.scala 40:26] + node _T_91 = bits(io.in, 6, 6) @[RVC.scala 40:36] + node _T_92 = cat(_T_91, UInt<2>("h00")) @[Cat.scala 29:58] + node _T_93 = cat(_T_89, _T_90) @[Cat.scala 29:58] + node _T_94 = cat(_T_93, _T_92) @[Cat.scala 29:58] + node _T_95 = shr(_T_94, 5) @[RVC.scala 68:32] + node _T_96 = bits(io.in, 4, 2) @[RVC.scala 36:29] + node _T_97 = cat(UInt<2>("h01"), _T_96) @[Cat.scala 29:58] + node _T_98 = bits(io.in, 9, 7) @[RVC.scala 35:29] + node _T_99 = cat(UInt<2>("h01"), _T_98) @[Cat.scala 29:58] + node _T_100 = bits(io.in, 5, 5) @[RVC.scala 40:20] + node _T_101 = bits(io.in, 12, 10) @[RVC.scala 40:26] + node _T_102 = bits(io.in, 6, 6) @[RVC.scala 40:36] + node _T_103 = cat(_T_102, UInt<2>("h00")) @[Cat.scala 29:58] + node _T_104 = cat(_T_100, _T_101) @[Cat.scala 29:58] + node _T_105 = cat(_T_104, _T_103) @[Cat.scala 29:58] + node _T_106 = bits(_T_105, 4, 0) @[RVC.scala 68:65] + node _T_107 = cat(UInt<3>("h02"), _T_106) @[Cat.scala 29:58] + node _T_108 = cat(_T_107, UInt<7>("h03f")) @[Cat.scala 29:58] + node _T_109 = cat(_T_95, _T_97) @[Cat.scala 29:58] + node _T_110 = cat(_T_109, _T_99) @[Cat.scala 29:58] + node _T_111 = cat(_T_110, _T_108) @[Cat.scala 29:58] + node _T_112 = bits(io.in, 4, 2) @[RVC.scala 36:29] + node _T_113 = cat(UInt<2>("h01"), _T_112) @[Cat.scala 29:58] + node _T_114 = bits(io.in, 9, 7) @[RVC.scala 35:29] + node _T_115 = cat(UInt<2>("h01"), _T_114) @[Cat.scala 29:58] + node _T_116 = bits(io.in, 4, 2) @[RVC.scala 36:29] + node _T_117 = cat(UInt<2>("h01"), _T_116) @[Cat.scala 29:58] + node _T_118 = bits(io.in, 31, 27) @[RVC.scala 25:101] + wire _T_119 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 26:19] + _T_119.bits <= _T_111 @[RVC.scala 27:14] + _T_119.rd <= _T_113 @[RVC.scala 28:12] + _T_119.rs1 <= _T_115 @[RVC.scala 29:13] + _T_119.rs2 <= _T_117 @[RVC.scala 30:13] + _T_119.rs3 <= _T_118 @[RVC.scala 31:13] + node _T_120 = bits(io.in, 6, 5) @[RVC.scala 41:20] + node _T_121 = bits(io.in, 12, 10) @[RVC.scala 41:28] + node _T_122 = cat(_T_120, _T_121) @[Cat.scala 29:58] + node _T_123 = cat(_T_122, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_124 = shr(_T_123, 5) @[RVC.scala 71:30] + node _T_125 = bits(io.in, 4, 2) @[RVC.scala 36:29] + node _T_126 = cat(UInt<2>("h01"), _T_125) @[Cat.scala 29:58] + node _T_127 = bits(io.in, 9, 7) @[RVC.scala 35:29] + node _T_128 = cat(UInt<2>("h01"), _T_127) @[Cat.scala 29:58] + node _T_129 = bits(io.in, 6, 5) @[RVC.scala 41:20] + node _T_130 = bits(io.in, 12, 10) @[RVC.scala 41:28] + node _T_131 = cat(_T_129, _T_130) @[Cat.scala 29:58] + node _T_132 = cat(_T_131, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_133 = bits(_T_132, 4, 0) @[RVC.scala 71:63] + node _T_134 = cat(UInt<3>("h03"), _T_133) @[Cat.scala 29:58] + node _T_135 = cat(_T_134, UInt<7>("h027")) @[Cat.scala 29:58] + node _T_136 = cat(_T_124, _T_126) @[Cat.scala 29:58] + node _T_137 = cat(_T_136, _T_128) @[Cat.scala 29:58] + node _T_138 = cat(_T_137, _T_135) @[Cat.scala 29:58] + node _T_139 = bits(io.in, 4, 2) @[RVC.scala 36:29] + node _T_140 = cat(UInt<2>("h01"), _T_139) @[Cat.scala 29:58] + node _T_141 = bits(io.in, 9, 7) @[RVC.scala 35:29] + node _T_142 = cat(UInt<2>("h01"), _T_141) @[Cat.scala 29:58] + node _T_143 = bits(io.in, 4, 2) @[RVC.scala 36:29] + node _T_144 = cat(UInt<2>("h01"), _T_143) @[Cat.scala 29:58] + node _T_145 = bits(io.in, 31, 27) @[RVC.scala 25:101] + wire _T_146 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 26:19] + _T_146.bits <= _T_138 @[RVC.scala 27:14] + _T_146.rd <= _T_140 @[RVC.scala 28:12] + _T_146.rs1 <= _T_142 @[RVC.scala 29:13] + _T_146.rs2 <= _T_144 @[RVC.scala 30:13] + _T_146.rs3 <= _T_145 @[RVC.scala 31:13] + node _T_147 = bits(io.in, 5, 5) @[RVC.scala 40:20] + node _T_148 = bits(io.in, 12, 10) @[RVC.scala 40:26] + node _T_149 = bits(io.in, 6, 6) @[RVC.scala 40:36] + node _T_150 = cat(_T_149, UInt<2>("h00")) @[Cat.scala 29:58] + node _T_151 = cat(_T_147, _T_148) @[Cat.scala 29:58] + node _T_152 = cat(_T_151, _T_150) @[Cat.scala 29:58] + node _T_153 = shr(_T_152, 5) @[RVC.scala 70:29] + node _T_154 = bits(io.in, 4, 2) @[RVC.scala 36:29] + node _T_155 = cat(UInt<2>("h01"), _T_154) @[Cat.scala 29:58] + node _T_156 = bits(io.in, 9, 7) @[RVC.scala 35:29] + node _T_157 = cat(UInt<2>("h01"), _T_156) @[Cat.scala 29:58] + node _T_158 = bits(io.in, 5, 5) @[RVC.scala 40:20] + node _T_159 = bits(io.in, 12, 10) @[RVC.scala 40:26] + node _T_160 = bits(io.in, 6, 6) @[RVC.scala 40:36] + node _T_161 = cat(_T_160, UInt<2>("h00")) @[Cat.scala 29:58] + node _T_162 = cat(_T_158, _T_159) @[Cat.scala 29:58] + node _T_163 = cat(_T_162, _T_161) @[Cat.scala 29:58] + node _T_164 = bits(_T_163, 4, 0) @[RVC.scala 70:62] + node _T_165 = cat(UInt<3>("h02"), _T_164) @[Cat.scala 29:58] + node _T_166 = cat(_T_165, UInt<7>("h023")) @[Cat.scala 29:58] + node _T_167 = cat(_T_153, _T_155) @[Cat.scala 29:58] + node _T_168 = cat(_T_167, _T_157) @[Cat.scala 29:58] + node _T_169 = cat(_T_168, _T_166) @[Cat.scala 29:58] + node _T_170 = bits(io.in, 4, 2) @[RVC.scala 36:29] + node _T_171 = cat(UInt<2>("h01"), _T_170) @[Cat.scala 29:58] + node _T_172 = bits(io.in, 9, 7) @[RVC.scala 35:29] + node _T_173 = cat(UInt<2>("h01"), _T_172) @[Cat.scala 29:58] + node _T_174 = bits(io.in, 4, 2) @[RVC.scala 36:29] + node _T_175 = cat(UInt<2>("h01"), _T_174) @[Cat.scala 29:58] + node _T_176 = bits(io.in, 31, 27) @[RVC.scala 25:101] + wire _T_177 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 26:19] + _T_177.bits <= _T_169 @[RVC.scala 27:14] + _T_177.rd <= _T_171 @[RVC.scala 28:12] + _T_177.rs1 <= _T_173 @[RVC.scala 29:13] + _T_177.rs2 <= _T_175 @[RVC.scala 30:13] + _T_177.rs3 <= _T_176 @[RVC.scala 31:13] + node _T_178 = bits(io.in, 5, 5) @[RVC.scala 40:20] + node _T_179 = bits(io.in, 12, 10) @[RVC.scala 40:26] + node _T_180 = bits(io.in, 6, 6) @[RVC.scala 40:36] + node _T_181 = cat(_T_180, UInt<2>("h00")) @[Cat.scala 29:58] + node _T_182 = cat(_T_178, _T_179) @[Cat.scala 29:58] + node _T_183 = cat(_T_182, _T_181) @[Cat.scala 29:58] + node _T_184 = shr(_T_183, 5) @[RVC.scala 73:38] + node _T_185 = bits(io.in, 4, 2) @[RVC.scala 36:29] + node _T_186 = cat(UInt<2>("h01"), _T_185) @[Cat.scala 29:58] + node _T_187 = bits(io.in, 9, 7) @[RVC.scala 35:29] + node _T_188 = cat(UInt<2>("h01"), _T_187) @[Cat.scala 29:58] + node _T_189 = bits(io.in, 5, 5) @[RVC.scala 40:20] + node _T_190 = bits(io.in, 12, 10) @[RVC.scala 40:26] + node _T_191 = bits(io.in, 6, 6) @[RVC.scala 40:36] + node _T_192 = cat(_T_191, UInt<2>("h00")) @[Cat.scala 29:58] + node _T_193 = cat(_T_189, _T_190) @[Cat.scala 29:58] + node _T_194 = cat(_T_193, _T_192) @[Cat.scala 29:58] + node _T_195 = bits(_T_194, 4, 0) @[RVC.scala 73:71] + node _T_196 = cat(UInt<3>("h02"), _T_195) @[Cat.scala 29:58] + node _T_197 = cat(_T_196, UInt<7>("h027")) @[Cat.scala 29:58] + node _T_198 = cat(_T_184, _T_186) @[Cat.scala 29:58] + node _T_199 = cat(_T_198, _T_188) @[Cat.scala 29:58] + node _T_200 = cat(_T_199, _T_197) @[Cat.scala 29:58] + node _T_201 = bits(io.in, 4, 2) @[RVC.scala 36:29] + node _T_202 = cat(UInt<2>("h01"), _T_201) @[Cat.scala 29:58] + node _T_203 = bits(io.in, 9, 7) @[RVC.scala 35:29] + node _T_204 = cat(UInt<2>("h01"), _T_203) @[Cat.scala 29:58] + node _T_205 = bits(io.in, 4, 2) @[RVC.scala 36:29] + node _T_206 = cat(UInt<2>("h01"), _T_205) @[Cat.scala 29:58] + node _T_207 = bits(io.in, 31, 27) @[RVC.scala 25:101] + wire _T_208 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 26:19] + _T_208.bits <= _T_200 @[RVC.scala 27:14] + _T_208.rd <= _T_202 @[RVC.scala 28:12] + _T_208.rs1 <= _T_204 @[RVC.scala 29:13] + _T_208.rs2 <= _T_206 @[RVC.scala 30:13] + _T_208.rs3 <= _T_207 @[RVC.scala 31:13] + node _T_209 = bits(io.in, 12, 12) @[RVC.scala 48:30] + node _T_210 = bits(_T_209, 0, 0) @[Bitwise.scala 72:15] + node _T_211 = mux(_T_210, UInt<7>("h07f"), UInt<7>("h00")) @[Bitwise.scala 72:12] + node _T_212 = bits(io.in, 6, 2) @[RVC.scala 48:38] + node _T_213 = cat(_T_211, _T_212) @[Cat.scala 29:58] + node _T_214 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_215 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_216 = cat(_T_215, UInt<7>("h013")) @[Cat.scala 29:58] + node _T_217 = cat(_T_213, _T_214) @[Cat.scala 29:58] + node _T_218 = cat(_T_217, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_219 = cat(_T_218, _T_216) @[Cat.scala 29:58] + node _T_220 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_221 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_222 = bits(io.in, 4, 2) @[RVC.scala 36:29] + node _T_223 = cat(UInt<2>("h01"), _T_222) @[Cat.scala 29:58] + node _T_224 = bits(io.in, 31, 27) @[RVC.scala 25:101] + wire _T_225 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 26:19] + _T_225.bits <= _T_219 @[RVC.scala 27:14] + _T_225.rd <= _T_220 @[RVC.scala 28:12] + _T_225.rs1 <= _T_221 @[RVC.scala 29:13] + _T_225.rs2 <= _T_223 @[RVC.scala 30:13] + _T_225.rs3 <= _T_224 @[RVC.scala 31:13] + node _T_226 = bits(io.in, 12, 12) @[RVC.scala 49:28] + node _T_227 = bits(_T_226, 0, 0) @[Bitwise.scala 72:15] + node _T_228 = mux(_T_227, UInt<10>("h03ff"), UInt<10>("h00")) @[Bitwise.scala 72:12] + node _T_229 = bits(io.in, 8, 8) @[RVC.scala 49:36] + node _T_230 = bits(io.in, 10, 9) @[RVC.scala 49:42] + node _T_231 = bits(io.in, 6, 6) @[RVC.scala 49:51] + node _T_232 = bits(io.in, 7, 7) @[RVC.scala 49:57] + node _T_233 = bits(io.in, 2, 2) @[RVC.scala 49:63] + node _T_234 = bits(io.in, 11, 11) @[RVC.scala 49:69] + node _T_235 = bits(io.in, 5, 3) @[RVC.scala 49:76] + node _T_236 = cat(_T_235, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_237 = cat(_T_233, _T_234) @[Cat.scala 29:58] + node _T_238 = cat(_T_237, _T_236) @[Cat.scala 29:58] + node _T_239 = cat(_T_231, _T_232) @[Cat.scala 29:58] + node _T_240 = cat(_T_228, _T_229) @[Cat.scala 29:58] + node _T_241 = cat(_T_240, _T_230) @[Cat.scala 29:58] + node _T_242 = cat(_T_241, _T_239) @[Cat.scala 29:58] + node _T_243 = cat(_T_242, _T_238) @[Cat.scala 29:58] + node _T_244 = bits(_T_243, 20, 20) @[RVC.scala 86:36] + node _T_245 = bits(io.in, 12, 12) @[RVC.scala 49:28] + node _T_246 = bits(_T_245, 0, 0) @[Bitwise.scala 72:15] + node _T_247 = mux(_T_246, UInt<10>("h03ff"), UInt<10>("h00")) @[Bitwise.scala 72:12] + node _T_248 = bits(io.in, 8, 8) @[RVC.scala 49:36] + node _T_249 = bits(io.in, 10, 9) @[RVC.scala 49:42] + node _T_250 = bits(io.in, 6, 6) @[RVC.scala 49:51] + node _T_251 = bits(io.in, 7, 7) @[RVC.scala 49:57] + node _T_252 = bits(io.in, 2, 2) @[RVC.scala 49:63] + node _T_253 = bits(io.in, 11, 11) @[RVC.scala 49:69] + node _T_254 = bits(io.in, 5, 3) @[RVC.scala 49:76] + node _T_255 = cat(_T_254, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_256 = cat(_T_252, _T_253) @[Cat.scala 29:58] + node _T_257 = cat(_T_256, _T_255) @[Cat.scala 29:58] + node _T_258 = cat(_T_250, _T_251) @[Cat.scala 29:58] + node _T_259 = cat(_T_247, _T_248) @[Cat.scala 29:58] + node _T_260 = cat(_T_259, _T_249) @[Cat.scala 29:58] + node _T_261 = cat(_T_260, _T_258) @[Cat.scala 29:58] + node _T_262 = cat(_T_261, _T_257) @[Cat.scala 29:58] + node _T_263 = bits(_T_262, 10, 1) @[RVC.scala 86:46] + node _T_264 = bits(io.in, 12, 12) @[RVC.scala 49:28] + node _T_265 = bits(_T_264, 0, 0) @[Bitwise.scala 72:15] + node _T_266 = mux(_T_265, UInt<10>("h03ff"), UInt<10>("h00")) @[Bitwise.scala 72:12] + node _T_267 = bits(io.in, 8, 8) @[RVC.scala 49:36] + node _T_268 = bits(io.in, 10, 9) @[RVC.scala 49:42] + node _T_269 = bits(io.in, 6, 6) @[RVC.scala 49:51] + node _T_270 = bits(io.in, 7, 7) @[RVC.scala 49:57] + node _T_271 = bits(io.in, 2, 2) @[RVC.scala 49:63] + node _T_272 = bits(io.in, 11, 11) @[RVC.scala 49:69] + node _T_273 = bits(io.in, 5, 3) @[RVC.scala 49:76] + node _T_274 = cat(_T_273, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_275 = cat(_T_271, _T_272) @[Cat.scala 29:58] + node _T_276 = cat(_T_275, _T_274) @[Cat.scala 29:58] + node _T_277 = cat(_T_269, _T_270) @[Cat.scala 29:58] + node _T_278 = cat(_T_266, _T_267) @[Cat.scala 29:58] + node _T_279 = cat(_T_278, _T_268) @[Cat.scala 29:58] + node _T_280 = cat(_T_279, _T_277) @[Cat.scala 29:58] + node _T_281 = cat(_T_280, _T_276) @[Cat.scala 29:58] + node _T_282 = bits(_T_281, 11, 11) @[RVC.scala 86:58] + node _T_283 = bits(io.in, 12, 12) @[RVC.scala 49:28] + node _T_284 = bits(_T_283, 0, 0) @[Bitwise.scala 72:15] + node _T_285 = mux(_T_284, UInt<10>("h03ff"), UInt<10>("h00")) @[Bitwise.scala 72:12] + node _T_286 = bits(io.in, 8, 8) @[RVC.scala 49:36] + node _T_287 = bits(io.in, 10, 9) @[RVC.scala 49:42] + node _T_288 = bits(io.in, 6, 6) @[RVC.scala 49:51] + node _T_289 = bits(io.in, 7, 7) @[RVC.scala 49:57] + node _T_290 = bits(io.in, 2, 2) @[RVC.scala 49:63] + node _T_291 = bits(io.in, 11, 11) @[RVC.scala 49:69] + node _T_292 = bits(io.in, 5, 3) @[RVC.scala 49:76] + node _T_293 = cat(_T_292, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_294 = cat(_T_290, _T_291) @[Cat.scala 29:58] + node _T_295 = cat(_T_294, _T_293) @[Cat.scala 29:58] + node _T_296 = cat(_T_288, _T_289) @[Cat.scala 29:58] + node _T_297 = cat(_T_285, _T_286) @[Cat.scala 29:58] + node _T_298 = cat(_T_297, _T_287) @[Cat.scala 29:58] + node _T_299 = cat(_T_298, _T_296) @[Cat.scala 29:58] + node _T_300 = cat(_T_299, _T_295) @[Cat.scala 29:58] + node _T_301 = bits(_T_300, 19, 12) @[RVC.scala 86:68] + node _T_302 = cat(_T_301, UInt<5>("h01")) @[Cat.scala 29:58] + node _T_303 = cat(_T_302, UInt<7>("h06f")) @[Cat.scala 29:58] + node _T_304 = cat(_T_244, _T_263) @[Cat.scala 29:58] + node _T_305 = cat(_T_304, _T_282) @[Cat.scala 29:58] + node _T_306 = cat(_T_305, _T_303) @[Cat.scala 29:58] + node _T_307 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_308 = bits(io.in, 4, 2) @[RVC.scala 36:29] + node _T_309 = cat(UInt<2>("h01"), _T_308) @[Cat.scala 29:58] + node _T_310 = bits(io.in, 31, 27) @[RVC.scala 25:101] + wire _T_311 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 26:19] + _T_311.bits <= _T_306 @[RVC.scala 27:14] + _T_311.rd <= UInt<5>("h01") @[RVC.scala 28:12] + _T_311.rs1 <= _T_307 @[RVC.scala 29:13] + _T_311.rs2 <= _T_309 @[RVC.scala 30:13] + _T_311.rs3 <= _T_310 @[RVC.scala 31:13] + node _T_312 = bits(io.in, 12, 12) @[RVC.scala 48:30] + node _T_313 = bits(_T_312, 0, 0) @[Bitwise.scala 72:15] + node _T_314 = mux(_T_313, UInt<7>("h07f"), UInt<7>("h00")) @[Bitwise.scala 72:12] + node _T_315 = bits(io.in, 6, 2) @[RVC.scala 48:38] + node _T_316 = cat(_T_314, _T_315) @[Cat.scala 29:58] + node _T_317 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_318 = cat(_T_317, UInt<7>("h013")) @[Cat.scala 29:58] + node _T_319 = cat(_T_316, UInt<5>("h00")) @[Cat.scala 29:58] + node _T_320 = cat(_T_319, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_321 = cat(_T_320, _T_318) @[Cat.scala 29:58] + node _T_322 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_323 = bits(io.in, 4, 2) @[RVC.scala 36:29] + node _T_324 = cat(UInt<2>("h01"), _T_323) @[Cat.scala 29:58] + node _T_325 = bits(io.in, 31, 27) @[RVC.scala 25:101] + wire _T_326 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 26:19] + _T_326.bits <= _T_321 @[RVC.scala 27:14] + _T_326.rd <= _T_322 @[RVC.scala 28:12] + _T_326.rs1 <= UInt<5>("h00") @[RVC.scala 29:13] + _T_326.rs2 <= _T_324 @[RVC.scala 30:13] + _T_326.rs3 <= _T_325 @[RVC.scala 31:13] + node _T_327 = bits(io.in, 12, 12) @[RVC.scala 48:30] + node _T_328 = bits(_T_327, 0, 0) @[Bitwise.scala 72:15] + node _T_329 = mux(_T_328, UInt<7>("h07f"), UInt<7>("h00")) @[Bitwise.scala 72:12] + node _T_330 = bits(io.in, 6, 2) @[RVC.scala 48:38] + node _T_331 = cat(_T_329, _T_330) @[Cat.scala 29:58] + node _T_332 = orr(_T_331) @[RVC.scala 95:29] + node _T_333 = mux(_T_332, UInt<7>("h037"), UInt<7>("h03f")) @[RVC.scala 95:20] + node _T_334 = bits(io.in, 12, 12) @[RVC.scala 46:30] + node _T_335 = bits(_T_334, 0, 0) @[Bitwise.scala 72:15] + node _T_336 = mux(_T_335, UInt<15>("h07fff"), UInt<15>("h00")) @[Bitwise.scala 72:12] + node _T_337 = bits(io.in, 6, 2) @[RVC.scala 46:38] + node _T_338 = cat(_T_336, _T_337) @[Cat.scala 29:58] + node _T_339 = cat(_T_338, UInt<12>("h00")) @[Cat.scala 29:58] + node _T_340 = bits(_T_339, 31, 12) @[RVC.scala 96:31] + node _T_341 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_342 = cat(_T_340, _T_341) @[Cat.scala 29:58] + node _T_343 = cat(_T_342, _T_333) @[Cat.scala 29:58] + node _T_344 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_345 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_346 = bits(io.in, 4, 2) @[RVC.scala 36:29] + node _T_347 = cat(UInt<2>("h01"), _T_346) @[Cat.scala 29:58] + node _T_348 = bits(io.in, 31, 27) @[RVC.scala 25:101] + wire _T_349 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 26:19] + _T_349.bits <= _T_343 @[RVC.scala 27:14] + _T_349.rd <= _T_344 @[RVC.scala 28:12] + _T_349.rs1 <= _T_345 @[RVC.scala 29:13] + _T_349.rs2 <= _T_347 @[RVC.scala 30:13] + _T_349.rs3 <= _T_348 @[RVC.scala 31:13] + node _T_350 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_351 = eq(_T_350, UInt<5>("h00")) @[RVC.scala 97:14] + node _T_352 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_353 = eq(_T_352, UInt<5>("h02")) @[RVC.scala 97:27] + node _T_354 = or(_T_351, _T_353) @[RVC.scala 97:21] + node _T_355 = bits(io.in, 12, 12) @[RVC.scala 48:30] + node _T_356 = bits(_T_355, 0, 0) @[Bitwise.scala 72:15] + node _T_357 = mux(_T_356, UInt<7>("h07f"), UInt<7>("h00")) @[Bitwise.scala 72:12] + node _T_358 = bits(io.in, 6, 2) @[RVC.scala 48:38] + node _T_359 = cat(_T_357, _T_358) @[Cat.scala 29:58] + node _T_360 = orr(_T_359) @[RVC.scala 91:29] + node _T_361 = mux(_T_360, UInt<7>("h013"), UInt<7>("h01f")) @[RVC.scala 91:20] + node _T_362 = bits(io.in, 12, 12) @[RVC.scala 47:34] + node _T_363 = bits(_T_362, 0, 0) @[Bitwise.scala 72:15] + node _T_364 = mux(_T_363, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_365 = bits(io.in, 4, 3) @[RVC.scala 47:42] + node _T_366 = bits(io.in, 5, 5) @[RVC.scala 47:50] + node _T_367 = bits(io.in, 2, 2) @[RVC.scala 47:56] + node _T_368 = bits(io.in, 6, 6) @[RVC.scala 47:62] + node _T_369 = cat(_T_367, _T_368) @[Cat.scala 29:58] + node _T_370 = cat(_T_369, UInt<4>("h00")) @[Cat.scala 29:58] + node _T_371 = cat(_T_364, _T_365) @[Cat.scala 29:58] + node _T_372 = cat(_T_371, _T_366) @[Cat.scala 29:58] + node _T_373 = cat(_T_372, _T_370) @[Cat.scala 29:58] + node _T_374 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_375 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_376 = cat(_T_375, _T_361) @[Cat.scala 29:58] + node _T_377 = cat(_T_373, _T_374) @[Cat.scala 29:58] + node _T_378 = cat(_T_377, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_379 = cat(_T_378, _T_376) @[Cat.scala 29:58] + node _T_380 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_381 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_382 = bits(io.in, 4, 2) @[RVC.scala 36:29] + node _T_383 = cat(UInt<2>("h01"), _T_382) @[Cat.scala 29:58] + node _T_384 = bits(io.in, 31, 27) @[RVC.scala 25:101] + wire _T_385 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 26:19] + _T_385.bits <= _T_379 @[RVC.scala 27:14] + _T_385.rd <= _T_380 @[RVC.scala 28:12] + _T_385.rs1 <= _T_381 @[RVC.scala 29:13] + _T_385.rs2 <= _T_383 @[RVC.scala 30:13] + _T_385.rs3 <= _T_384 @[RVC.scala 31:13] + node _T_386 = mux(_T_354, _T_385, _T_349) @[RVC.scala 97:10] + node _T_387 = bits(io.in, 12, 12) @[RVC.scala 51:20] + node _T_388 = bits(io.in, 6, 2) @[RVC.scala 51:27] + node _T_389 = cat(_T_387, _T_388) @[Cat.scala 29:58] + node _T_390 = bits(io.in, 9, 7) @[RVC.scala 35:29] + node _T_391 = cat(UInt<2>("h01"), _T_390) @[Cat.scala 29:58] + node _T_392 = bits(io.in, 9, 7) @[RVC.scala 35:29] + node _T_393 = cat(UInt<2>("h01"), _T_392) @[Cat.scala 29:58] + node _T_394 = cat(_T_393, UInt<7>("h013")) @[Cat.scala 29:58] + node _T_395 = cat(_T_389, _T_391) @[Cat.scala 29:58] + node _T_396 = cat(_T_395, UInt<3>("h05")) @[Cat.scala 29:58] + node _T_397 = cat(_T_396, _T_394) @[Cat.scala 29:58] + node _T_398 = bits(io.in, 12, 12) @[RVC.scala 51:20] + node _T_399 = bits(io.in, 6, 2) @[RVC.scala 51:27] + node _T_400 = cat(_T_398, _T_399) @[Cat.scala 29:58] + node _T_401 = bits(io.in, 9, 7) @[RVC.scala 35:29] + node _T_402 = cat(UInt<2>("h01"), _T_401) @[Cat.scala 29:58] + node _T_403 = bits(io.in, 9, 7) @[RVC.scala 35:29] + node _T_404 = cat(UInt<2>("h01"), _T_403) @[Cat.scala 29:58] + node _T_405 = cat(_T_404, UInt<7>("h013")) @[Cat.scala 29:58] + node _T_406 = cat(_T_400, _T_402) @[Cat.scala 29:58] + node _T_407 = cat(_T_406, UInt<3>("h05")) @[Cat.scala 29:58] + node _T_408 = cat(_T_407, _T_405) @[Cat.scala 29:58] + node _T_409 = or(_T_408, UInt<31>("h040000000")) @[RVC.scala 104:23] + node _T_410 = bits(io.in, 12, 12) @[RVC.scala 48:30] + node _T_411 = bits(_T_410, 0, 0) @[Bitwise.scala 72:15] + node _T_412 = mux(_T_411, UInt<7>("h07f"), UInt<7>("h00")) @[Bitwise.scala 72:12] + node _T_413 = bits(io.in, 6, 2) @[RVC.scala 48:38] + node _T_414 = cat(_T_412, _T_413) @[Cat.scala 29:58] + node _T_415 = bits(io.in, 9, 7) @[RVC.scala 35:29] + node _T_416 = cat(UInt<2>("h01"), _T_415) @[Cat.scala 29:58] + node _T_417 = bits(io.in, 9, 7) @[RVC.scala 35:29] + node _T_418 = cat(UInt<2>("h01"), _T_417) @[Cat.scala 29:58] + node _T_419 = cat(_T_418, UInt<7>("h013")) @[Cat.scala 29:58] + node _T_420 = cat(_T_414, _T_416) @[Cat.scala 29:58] + node _T_421 = cat(_T_420, UInt<3>("h07")) @[Cat.scala 29:58] + node _T_422 = cat(_T_421, _T_419) @[Cat.scala 29:58] + wire _T_423 : UInt<3>[8] @[RVC.scala 107:28] + _T_423[0] <= UInt<1>("h00") @[RVC.scala 107:28] + _T_423[1] <= UInt<3>("h04") @[RVC.scala 107:28] + _T_423[2] <= UInt<3>("h06") @[RVC.scala 107:28] + _T_423[3] <= UInt<3>("h07") @[RVC.scala 107:28] + _T_423[4] <= UInt<1>("h00") @[RVC.scala 107:28] + _T_423[5] <= UInt<1>("h00") @[RVC.scala 107:28] + _T_423[6] <= UInt<2>("h02") @[RVC.scala 107:28] + _T_423[7] <= UInt<2>("h03") @[RVC.scala 107:28] + node _T_424 = bits(io.in, 12, 12) @[RVC.scala 107:74] + node _T_425 = bits(io.in, 6, 5) @[RVC.scala 107:81] + node _T_426 = cat(_T_424, _T_425) @[Cat.scala 29:58] + node _T_427 = bits(io.in, 6, 5) @[RVC.scala 108:24] + node _T_428 = eq(_T_427, UInt<1>("h00")) @[RVC.scala 108:30] + node _T_429 = mux(_T_428, UInt<31>("h040000000"), UInt<1>("h00")) @[RVC.scala 108:22] + node _T_430 = bits(io.in, 12, 12) @[RVC.scala 109:24] + node _T_431 = mux(_T_430, UInt<7>("h03b"), UInt<7>("h033")) @[RVC.scala 109:22] + node _T_432 = bits(io.in, 4, 2) @[RVC.scala 36:29] + node _T_433 = cat(UInt<2>("h01"), _T_432) @[Cat.scala 29:58] + node _T_434 = bits(io.in, 9, 7) @[RVC.scala 35:29] + node _T_435 = cat(UInt<2>("h01"), _T_434) @[Cat.scala 29:58] + node _T_436 = bits(io.in, 9, 7) @[RVC.scala 35:29] + node _T_437 = cat(UInt<2>("h01"), _T_436) @[Cat.scala 29:58] + node _T_438 = cat(_T_437, _T_431) @[Cat.scala 29:58] + node _T_439 = cat(_T_433, _T_435) @[Cat.scala 29:58] + node _T_440 = cat(_T_439, _T_423[_T_426]) @[Cat.scala 29:58] + node _T_441 = cat(_T_440, _T_438) @[Cat.scala 29:58] + node _T_442 = or(_T_441, _T_429) @[RVC.scala 110:43] + wire _T_443 : UInt<32>[4] @[RVC.scala 112:19] + _T_443[0] <= _T_397 @[RVC.scala 112:19] + _T_443[1] <= _T_409 @[RVC.scala 112:19] + _T_443[2] <= _T_422 @[RVC.scala 112:19] + _T_443[3] <= _T_442 @[RVC.scala 112:19] + node _T_444 = bits(io.in, 11, 10) @[RVC.scala 112:46] + node _T_445 = bits(io.in, 9, 7) @[RVC.scala 35:29] + node _T_446 = cat(UInt<2>("h01"), _T_445) @[Cat.scala 29:58] + node _T_447 = bits(io.in, 9, 7) @[RVC.scala 35:29] + node _T_448 = cat(UInt<2>("h01"), _T_447) @[Cat.scala 29:58] + node _T_449 = bits(io.in, 4, 2) @[RVC.scala 36:29] + node _T_450 = cat(UInt<2>("h01"), _T_449) @[Cat.scala 29:58] + node _T_451 = bits(io.in, 31, 27) @[RVC.scala 25:101] + wire _T_452 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 26:19] + _T_452.bits <= _T_443[_T_444] @[RVC.scala 27:14] + _T_452.rd <= _T_446 @[RVC.scala 28:12] + _T_452.rs1 <= _T_448 @[RVC.scala 29:13] + _T_452.rs2 <= _T_450 @[RVC.scala 30:13] + _T_452.rs3 <= _T_451 @[RVC.scala 31:13] + node _T_453 = bits(io.in, 12, 12) @[RVC.scala 49:28] + node _T_454 = bits(_T_453, 0, 0) @[Bitwise.scala 72:15] + node _T_455 = mux(_T_454, UInt<10>("h03ff"), UInt<10>("h00")) @[Bitwise.scala 72:12] + node _T_456 = bits(io.in, 8, 8) @[RVC.scala 49:36] + node _T_457 = bits(io.in, 10, 9) @[RVC.scala 49:42] + node _T_458 = bits(io.in, 6, 6) @[RVC.scala 49:51] + node _T_459 = bits(io.in, 7, 7) @[RVC.scala 49:57] + node _T_460 = bits(io.in, 2, 2) @[RVC.scala 49:63] + node _T_461 = bits(io.in, 11, 11) @[RVC.scala 49:69] + node _T_462 = bits(io.in, 5, 3) @[RVC.scala 49:76] + node _T_463 = cat(_T_462, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_464 = cat(_T_460, _T_461) @[Cat.scala 29:58] + node _T_465 = cat(_T_464, _T_463) @[Cat.scala 29:58] + node _T_466 = cat(_T_458, _T_459) @[Cat.scala 29:58] + node _T_467 = cat(_T_455, _T_456) @[Cat.scala 29:58] + node _T_468 = cat(_T_467, _T_457) @[Cat.scala 29:58] + node _T_469 = cat(_T_468, _T_466) @[Cat.scala 29:58] + node _T_470 = cat(_T_469, _T_465) @[Cat.scala 29:58] + node _T_471 = bits(_T_470, 20, 20) @[RVC.scala 99:26] + node _T_472 = bits(io.in, 12, 12) @[RVC.scala 49:28] + node _T_473 = bits(_T_472, 0, 0) @[Bitwise.scala 72:15] + node _T_474 = mux(_T_473, UInt<10>("h03ff"), UInt<10>("h00")) @[Bitwise.scala 72:12] + node _T_475 = bits(io.in, 8, 8) @[RVC.scala 49:36] + node _T_476 = bits(io.in, 10, 9) @[RVC.scala 49:42] + node _T_477 = bits(io.in, 6, 6) @[RVC.scala 49:51] + node _T_478 = bits(io.in, 7, 7) @[RVC.scala 49:57] + node _T_479 = bits(io.in, 2, 2) @[RVC.scala 49:63] + node _T_480 = bits(io.in, 11, 11) @[RVC.scala 49:69] + node _T_481 = bits(io.in, 5, 3) @[RVC.scala 49:76] + node _T_482 = cat(_T_481, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_483 = cat(_T_479, _T_480) @[Cat.scala 29:58] + node _T_484 = cat(_T_483, _T_482) @[Cat.scala 29:58] + node _T_485 = cat(_T_477, _T_478) @[Cat.scala 29:58] + node _T_486 = cat(_T_474, _T_475) @[Cat.scala 29:58] + node _T_487 = cat(_T_486, _T_476) @[Cat.scala 29:58] + node _T_488 = cat(_T_487, _T_485) @[Cat.scala 29:58] + node _T_489 = cat(_T_488, _T_484) @[Cat.scala 29:58] + node _T_490 = bits(_T_489, 10, 1) @[RVC.scala 99:36] + node _T_491 = bits(io.in, 12, 12) @[RVC.scala 49:28] + node _T_492 = bits(_T_491, 0, 0) @[Bitwise.scala 72:15] + node _T_493 = mux(_T_492, UInt<10>("h03ff"), UInt<10>("h00")) @[Bitwise.scala 72:12] + node _T_494 = bits(io.in, 8, 8) @[RVC.scala 49:36] + node _T_495 = bits(io.in, 10, 9) @[RVC.scala 49:42] + node _T_496 = bits(io.in, 6, 6) @[RVC.scala 49:51] + node _T_497 = bits(io.in, 7, 7) @[RVC.scala 49:57] + node _T_498 = bits(io.in, 2, 2) @[RVC.scala 49:63] + node _T_499 = bits(io.in, 11, 11) @[RVC.scala 49:69] + node _T_500 = bits(io.in, 5, 3) @[RVC.scala 49:76] + node _T_501 = cat(_T_500, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_502 = cat(_T_498, _T_499) @[Cat.scala 29:58] + node _T_503 = cat(_T_502, _T_501) @[Cat.scala 29:58] + node _T_504 = cat(_T_496, _T_497) @[Cat.scala 29:58] + node _T_505 = cat(_T_493, _T_494) @[Cat.scala 29:58] + node _T_506 = cat(_T_505, _T_495) @[Cat.scala 29:58] + node _T_507 = cat(_T_506, _T_504) @[Cat.scala 29:58] + node _T_508 = cat(_T_507, _T_503) @[Cat.scala 29:58] + node _T_509 = bits(_T_508, 11, 11) @[RVC.scala 99:48] + node _T_510 = bits(io.in, 12, 12) @[RVC.scala 49:28] + node _T_511 = bits(_T_510, 0, 0) @[Bitwise.scala 72:15] + node _T_512 = mux(_T_511, UInt<10>("h03ff"), UInt<10>("h00")) @[Bitwise.scala 72:12] + node _T_513 = bits(io.in, 8, 8) @[RVC.scala 49:36] + node _T_514 = bits(io.in, 10, 9) @[RVC.scala 49:42] + node _T_515 = bits(io.in, 6, 6) @[RVC.scala 49:51] + node _T_516 = bits(io.in, 7, 7) @[RVC.scala 49:57] + node _T_517 = bits(io.in, 2, 2) @[RVC.scala 49:63] + node _T_518 = bits(io.in, 11, 11) @[RVC.scala 49:69] + node _T_519 = bits(io.in, 5, 3) @[RVC.scala 49:76] + node _T_520 = cat(_T_519, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_521 = cat(_T_517, _T_518) @[Cat.scala 29:58] + node _T_522 = cat(_T_521, _T_520) @[Cat.scala 29:58] + node _T_523 = cat(_T_515, _T_516) @[Cat.scala 29:58] + node _T_524 = cat(_T_512, _T_513) @[Cat.scala 29:58] + node _T_525 = cat(_T_524, _T_514) @[Cat.scala 29:58] + node _T_526 = cat(_T_525, _T_523) @[Cat.scala 29:58] + node _T_527 = cat(_T_526, _T_522) @[Cat.scala 29:58] + node _T_528 = bits(_T_527, 19, 12) @[RVC.scala 99:58] + node _T_529 = cat(_T_528, UInt<5>("h00")) @[Cat.scala 29:58] + node _T_530 = cat(_T_529, UInt<7>("h06f")) @[Cat.scala 29:58] + node _T_531 = cat(_T_471, _T_490) @[Cat.scala 29:58] + node _T_532 = cat(_T_531, _T_509) @[Cat.scala 29:58] + node _T_533 = cat(_T_532, _T_530) @[Cat.scala 29:58] + node _T_534 = bits(io.in, 9, 7) @[RVC.scala 35:29] + node _T_535 = cat(UInt<2>("h01"), _T_534) @[Cat.scala 29:58] + node _T_536 = bits(io.in, 4, 2) @[RVC.scala 36:29] + node _T_537 = cat(UInt<2>("h01"), _T_536) @[Cat.scala 29:58] + node _T_538 = bits(io.in, 31, 27) @[RVC.scala 25:101] + wire _T_539 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 26:19] + _T_539.bits <= _T_533 @[RVC.scala 27:14] + _T_539.rd <= UInt<5>("h00") @[RVC.scala 28:12] + _T_539.rs1 <= _T_535 @[RVC.scala 29:13] + _T_539.rs2 <= _T_537 @[RVC.scala 30:13] + _T_539.rs3 <= _T_538 @[RVC.scala 31:13] + node _T_540 = bits(io.in, 12, 12) @[RVC.scala 50:27] + node _T_541 = bits(_T_540, 0, 0) @[Bitwise.scala 72:15] + node _T_542 = mux(_T_541, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] + node _T_543 = bits(io.in, 6, 5) @[RVC.scala 50:35] + node _T_544 = bits(io.in, 2, 2) @[RVC.scala 50:43] + node _T_545 = bits(io.in, 11, 10) @[RVC.scala 50:49] + node _T_546 = bits(io.in, 4, 3) @[RVC.scala 50:59] + node _T_547 = cat(_T_545, _T_546) @[Cat.scala 29:58] + node _T_548 = cat(_T_547, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_549 = cat(_T_542, _T_543) @[Cat.scala 29:58] + node _T_550 = cat(_T_549, _T_544) @[Cat.scala 29:58] + node _T_551 = cat(_T_550, _T_548) @[Cat.scala 29:58] + node _T_552 = bits(_T_551, 12, 12) @[RVC.scala 100:29] + node _T_553 = bits(io.in, 12, 12) @[RVC.scala 50:27] + node _T_554 = bits(_T_553, 0, 0) @[Bitwise.scala 72:15] + node _T_555 = mux(_T_554, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] + node _T_556 = bits(io.in, 6, 5) @[RVC.scala 50:35] + node _T_557 = bits(io.in, 2, 2) @[RVC.scala 50:43] + node _T_558 = bits(io.in, 11, 10) @[RVC.scala 50:49] + node _T_559 = bits(io.in, 4, 3) @[RVC.scala 50:59] + node _T_560 = cat(_T_558, _T_559) @[Cat.scala 29:58] + node _T_561 = cat(_T_560, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_562 = cat(_T_555, _T_556) @[Cat.scala 29:58] + node _T_563 = cat(_T_562, _T_557) @[Cat.scala 29:58] + node _T_564 = cat(_T_563, _T_561) @[Cat.scala 29:58] + node _T_565 = bits(_T_564, 10, 5) @[RVC.scala 100:39] + node _T_566 = bits(io.in, 9, 7) @[RVC.scala 35:29] + node _T_567 = cat(UInt<2>("h01"), _T_566) @[Cat.scala 29:58] + node _T_568 = bits(io.in, 12, 12) @[RVC.scala 50:27] + node _T_569 = bits(_T_568, 0, 0) @[Bitwise.scala 72:15] + node _T_570 = mux(_T_569, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] + node _T_571 = bits(io.in, 6, 5) @[RVC.scala 50:35] + node _T_572 = bits(io.in, 2, 2) @[RVC.scala 50:43] + node _T_573 = bits(io.in, 11, 10) @[RVC.scala 50:49] + node _T_574 = bits(io.in, 4, 3) @[RVC.scala 50:59] + node _T_575 = cat(_T_573, _T_574) @[Cat.scala 29:58] + node _T_576 = cat(_T_575, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_577 = cat(_T_570, _T_571) @[Cat.scala 29:58] + node _T_578 = cat(_T_577, _T_572) @[Cat.scala 29:58] + node _T_579 = cat(_T_578, _T_576) @[Cat.scala 29:58] + node _T_580 = bits(_T_579, 4, 1) @[RVC.scala 100:71] + node _T_581 = bits(io.in, 12, 12) @[RVC.scala 50:27] + node _T_582 = bits(_T_581, 0, 0) @[Bitwise.scala 72:15] + node _T_583 = mux(_T_582, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] + node _T_584 = bits(io.in, 6, 5) @[RVC.scala 50:35] + node _T_585 = bits(io.in, 2, 2) @[RVC.scala 50:43] + node _T_586 = bits(io.in, 11, 10) @[RVC.scala 50:49] + node _T_587 = bits(io.in, 4, 3) @[RVC.scala 50:59] + node _T_588 = cat(_T_586, _T_587) @[Cat.scala 29:58] + node _T_589 = cat(_T_588, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_590 = cat(_T_583, _T_584) @[Cat.scala 29:58] + node _T_591 = cat(_T_590, _T_585) @[Cat.scala 29:58] + node _T_592 = cat(_T_591, _T_589) @[Cat.scala 29:58] + node _T_593 = bits(_T_592, 11, 11) @[RVC.scala 100:82] + node _T_594 = cat(_T_593, UInt<7>("h063")) @[Cat.scala 29:58] + node _T_595 = cat(UInt<3>("h00"), _T_580) @[Cat.scala 29:58] + node _T_596 = cat(_T_595, _T_594) @[Cat.scala 29:58] + node _T_597 = cat(UInt<5>("h00"), _T_567) @[Cat.scala 29:58] + node _T_598 = cat(_T_552, _T_565) @[Cat.scala 29:58] + node _T_599 = cat(_T_598, _T_597) @[Cat.scala 29:58] + node _T_600 = cat(_T_599, _T_596) @[Cat.scala 29:58] + node _T_601 = bits(io.in, 9, 7) @[RVC.scala 35:29] + node _T_602 = cat(UInt<2>("h01"), _T_601) @[Cat.scala 29:58] + node _T_603 = bits(io.in, 9, 7) @[RVC.scala 35:29] + node _T_604 = cat(UInt<2>("h01"), _T_603) @[Cat.scala 29:58] + node _T_605 = bits(io.in, 31, 27) @[RVC.scala 25:101] + wire _T_606 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 26:19] + _T_606.bits <= _T_600 @[RVC.scala 27:14] + _T_606.rd <= _T_602 @[RVC.scala 28:12] + _T_606.rs1 <= _T_604 @[RVC.scala 29:13] + _T_606.rs2 <= UInt<5>("h00") @[RVC.scala 30:13] + _T_606.rs3 <= _T_605 @[RVC.scala 31:13] + node _T_607 = bits(io.in, 12, 12) @[RVC.scala 50:27] + node _T_608 = bits(_T_607, 0, 0) @[Bitwise.scala 72:15] + node _T_609 = mux(_T_608, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] + node _T_610 = bits(io.in, 6, 5) @[RVC.scala 50:35] + node _T_611 = bits(io.in, 2, 2) @[RVC.scala 50:43] + node _T_612 = bits(io.in, 11, 10) @[RVC.scala 50:49] + node _T_613 = bits(io.in, 4, 3) @[RVC.scala 50:59] + node _T_614 = cat(_T_612, _T_613) @[Cat.scala 29:58] + node _T_615 = cat(_T_614, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_616 = cat(_T_609, _T_610) @[Cat.scala 29:58] + node _T_617 = cat(_T_616, _T_611) @[Cat.scala 29:58] + node _T_618 = cat(_T_617, _T_615) @[Cat.scala 29:58] + node _T_619 = bits(_T_618, 12, 12) @[RVC.scala 101:29] + node _T_620 = bits(io.in, 12, 12) @[RVC.scala 50:27] + node _T_621 = bits(_T_620, 0, 0) @[Bitwise.scala 72:15] + node _T_622 = mux(_T_621, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] + node _T_623 = bits(io.in, 6, 5) @[RVC.scala 50:35] + node _T_624 = bits(io.in, 2, 2) @[RVC.scala 50:43] + node _T_625 = bits(io.in, 11, 10) @[RVC.scala 50:49] + node _T_626 = bits(io.in, 4, 3) @[RVC.scala 50:59] + node _T_627 = cat(_T_625, _T_626) @[Cat.scala 29:58] + node _T_628 = cat(_T_627, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_629 = cat(_T_622, _T_623) @[Cat.scala 29:58] + node _T_630 = cat(_T_629, _T_624) @[Cat.scala 29:58] + node _T_631 = cat(_T_630, _T_628) @[Cat.scala 29:58] + node _T_632 = bits(_T_631, 10, 5) @[RVC.scala 101:39] + node _T_633 = bits(io.in, 9, 7) @[RVC.scala 35:29] + node _T_634 = cat(UInt<2>("h01"), _T_633) @[Cat.scala 29:58] + node _T_635 = bits(io.in, 12, 12) @[RVC.scala 50:27] + node _T_636 = bits(_T_635, 0, 0) @[Bitwise.scala 72:15] + node _T_637 = mux(_T_636, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] + node _T_638 = bits(io.in, 6, 5) @[RVC.scala 50:35] + node _T_639 = bits(io.in, 2, 2) @[RVC.scala 50:43] + node _T_640 = bits(io.in, 11, 10) @[RVC.scala 50:49] + node _T_641 = bits(io.in, 4, 3) @[RVC.scala 50:59] + node _T_642 = cat(_T_640, _T_641) @[Cat.scala 29:58] + node _T_643 = cat(_T_642, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_644 = cat(_T_637, _T_638) @[Cat.scala 29:58] + node _T_645 = cat(_T_644, _T_639) @[Cat.scala 29:58] + node _T_646 = cat(_T_645, _T_643) @[Cat.scala 29:58] + node _T_647 = bits(_T_646, 4, 1) @[RVC.scala 101:71] + node _T_648 = bits(io.in, 12, 12) @[RVC.scala 50:27] + node _T_649 = bits(_T_648, 0, 0) @[Bitwise.scala 72:15] + node _T_650 = mux(_T_649, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] + node _T_651 = bits(io.in, 6, 5) @[RVC.scala 50:35] + node _T_652 = bits(io.in, 2, 2) @[RVC.scala 50:43] + node _T_653 = bits(io.in, 11, 10) @[RVC.scala 50:49] + node _T_654 = bits(io.in, 4, 3) @[RVC.scala 50:59] + node _T_655 = cat(_T_653, _T_654) @[Cat.scala 29:58] + node _T_656 = cat(_T_655, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_657 = cat(_T_650, _T_651) @[Cat.scala 29:58] + node _T_658 = cat(_T_657, _T_652) @[Cat.scala 29:58] + node _T_659 = cat(_T_658, _T_656) @[Cat.scala 29:58] + node _T_660 = bits(_T_659, 11, 11) @[RVC.scala 101:82] + node _T_661 = cat(_T_660, UInt<7>("h063")) @[Cat.scala 29:58] + node _T_662 = cat(UInt<3>("h01"), _T_647) @[Cat.scala 29:58] + node _T_663 = cat(_T_662, _T_661) @[Cat.scala 29:58] + node _T_664 = cat(UInt<5>("h00"), _T_634) @[Cat.scala 29:58] + node _T_665 = cat(_T_619, _T_632) @[Cat.scala 29:58] + node _T_666 = cat(_T_665, _T_664) @[Cat.scala 29:58] + node _T_667 = cat(_T_666, _T_663) @[Cat.scala 29:58] + node _T_668 = bits(io.in, 9, 7) @[RVC.scala 35:29] + node _T_669 = cat(UInt<2>("h01"), _T_668) @[Cat.scala 29:58] + node _T_670 = bits(io.in, 31, 27) @[RVC.scala 25:101] + wire _T_671 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 26:19] + _T_671.bits <= _T_667 @[RVC.scala 27:14] + _T_671.rd <= UInt<5>("h00") @[RVC.scala 28:12] + _T_671.rs1 <= _T_669 @[RVC.scala 29:13] + _T_671.rs2 <= UInt<5>("h00") @[RVC.scala 30:13] + _T_671.rs3 <= _T_670 @[RVC.scala 31:13] + node _T_672 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_673 = orr(_T_672) @[RVC.scala 118:27] + node _T_674 = mux(_T_673, UInt<7>("h03"), UInt<7>("h01f")) @[RVC.scala 118:23] + node _T_675 = bits(io.in, 12, 12) @[RVC.scala 51:20] + node _T_676 = bits(io.in, 6, 2) @[RVC.scala 51:27] + node _T_677 = cat(_T_675, _T_676) @[Cat.scala 29:58] + node _T_678 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_679 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_680 = cat(_T_679, UInt<7>("h013")) @[Cat.scala 29:58] + node _T_681 = cat(_T_677, _T_678) @[Cat.scala 29:58] + node _T_682 = cat(_T_681, UInt<3>("h01")) @[Cat.scala 29:58] + node _T_683 = cat(_T_682, _T_680) @[Cat.scala 29:58] + node _T_684 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_685 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_686 = bits(io.in, 6, 2) @[RVC.scala 37:14] + node _T_687 = bits(io.in, 31, 27) @[RVC.scala 25:101] + wire _T_688 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 26:19] + _T_688.bits <= _T_683 @[RVC.scala 27:14] + _T_688.rd <= _T_684 @[RVC.scala 28:12] + _T_688.rs1 <= _T_685 @[RVC.scala 29:13] + _T_688.rs2 <= _T_686 @[RVC.scala 30:13] + _T_688.rs3 <= _T_687 @[RVC.scala 31:13] + node _T_689 = bits(io.in, 4, 2) @[RVC.scala 43:22] + node _T_690 = bits(io.in, 12, 12) @[RVC.scala 43:30] + node _T_691 = bits(io.in, 6, 5) @[RVC.scala 43:37] + node _T_692 = cat(_T_691, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_693 = cat(_T_689, _T_690) @[Cat.scala 29:58] + node _T_694 = cat(_T_693, _T_692) @[Cat.scala 29:58] + node _T_695 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_696 = cat(_T_695, UInt<7>("h07")) @[Cat.scala 29:58] + node _T_697 = cat(_T_694, UInt<5>("h02")) @[Cat.scala 29:58] + node _T_698 = cat(_T_697, UInt<3>("h03")) @[Cat.scala 29:58] + node _T_699 = cat(_T_698, _T_696) @[Cat.scala 29:58] + node _T_700 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_701 = bits(io.in, 6, 2) @[RVC.scala 37:14] + node _T_702 = bits(io.in, 31, 27) @[RVC.scala 25:101] + wire _T_703 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 26:19] + _T_703.bits <= _T_699 @[RVC.scala 27:14] + _T_703.rd <= _T_700 @[RVC.scala 28:12] + _T_703.rs1 <= UInt<5>("h02") @[RVC.scala 29:13] + _T_703.rs2 <= _T_701 @[RVC.scala 30:13] + _T_703.rs3 <= _T_702 @[RVC.scala 31:13] + node _T_704 = bits(io.in, 3, 2) @[RVC.scala 42:22] + node _T_705 = bits(io.in, 12, 12) @[RVC.scala 42:30] + node _T_706 = bits(io.in, 6, 4) @[RVC.scala 42:37] + node _T_707 = cat(_T_706, UInt<2>("h00")) @[Cat.scala 29:58] + node _T_708 = cat(_T_704, _T_705) @[Cat.scala 29:58] + node _T_709 = cat(_T_708, _T_707) @[Cat.scala 29:58] + node _T_710 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_711 = cat(_T_710, _T_674) @[Cat.scala 29:58] + node _T_712 = cat(_T_709, UInt<5>("h02")) @[Cat.scala 29:58] + node _T_713 = cat(_T_712, UInt<3>("h02")) @[Cat.scala 29:58] + node _T_714 = cat(_T_713, _T_711) @[Cat.scala 29:58] + node _T_715 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_716 = bits(io.in, 6, 2) @[RVC.scala 37:14] + node _T_717 = bits(io.in, 31, 27) @[RVC.scala 25:101] + wire _T_718 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 26:19] + _T_718.bits <= _T_714 @[RVC.scala 27:14] + _T_718.rd <= _T_715 @[RVC.scala 28:12] + _T_718.rs1 <= UInt<5>("h02") @[RVC.scala 29:13] + _T_718.rs2 <= _T_716 @[RVC.scala 30:13] + _T_718.rs3 <= _T_717 @[RVC.scala 31:13] + node _T_719 = bits(io.in, 3, 2) @[RVC.scala 42:22] + node _T_720 = bits(io.in, 12, 12) @[RVC.scala 42:30] + node _T_721 = bits(io.in, 6, 4) @[RVC.scala 42:37] + node _T_722 = cat(_T_721, UInt<2>("h00")) @[Cat.scala 29:58] + node _T_723 = cat(_T_719, _T_720) @[Cat.scala 29:58] + node _T_724 = cat(_T_723, _T_722) @[Cat.scala 29:58] + node _T_725 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_726 = cat(_T_725, UInt<7>("h07")) @[Cat.scala 29:58] + node _T_727 = cat(_T_724, UInt<5>("h02")) @[Cat.scala 29:58] + node _T_728 = cat(_T_727, UInt<3>("h02")) @[Cat.scala 29:58] + node _T_729 = cat(_T_728, _T_726) @[Cat.scala 29:58] + node _T_730 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_731 = bits(io.in, 6, 2) @[RVC.scala 37:14] + node _T_732 = bits(io.in, 31, 27) @[RVC.scala 25:101] + wire _T_733 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 26:19] + _T_733.bits <= _T_729 @[RVC.scala 27:14] + _T_733.rd <= _T_730 @[RVC.scala 28:12] + _T_733.rs1 <= UInt<5>("h02") @[RVC.scala 29:13] + _T_733.rs2 <= _T_731 @[RVC.scala 30:13] + _T_733.rs3 <= _T_732 @[RVC.scala 31:13] + node _T_734 = bits(io.in, 6, 2) @[RVC.scala 37:14] + node _T_735 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_736 = cat(_T_735, UInt<7>("h033")) @[Cat.scala 29:58] + node _T_737 = cat(_T_734, UInt<5>("h00")) @[Cat.scala 29:58] + node _T_738 = cat(_T_737, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_739 = cat(_T_738, _T_736) @[Cat.scala 29:58] + node _T_740 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_741 = bits(io.in, 6, 2) @[RVC.scala 37:14] + node _T_742 = bits(io.in, 31, 27) @[RVC.scala 25:101] + wire _T_743 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 26:19] + _T_743.bits <= _T_739 @[RVC.scala 27:14] + _T_743.rd <= _T_740 @[RVC.scala 28:12] + _T_743.rs1 <= UInt<5>("h00") @[RVC.scala 29:13] + _T_743.rs2 <= _T_741 @[RVC.scala 30:13] + _T_743.rs3 <= _T_742 @[RVC.scala 31:13] + node _T_744 = bits(io.in, 6, 2) @[RVC.scala 37:14] + node _T_745 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_746 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_747 = cat(_T_746, UInt<7>("h033")) @[Cat.scala 29:58] + node _T_748 = cat(_T_744, _T_745) @[Cat.scala 29:58] + node _T_749 = cat(_T_748, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_750 = cat(_T_749, _T_747) @[Cat.scala 29:58] + node _T_751 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_752 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_753 = bits(io.in, 6, 2) @[RVC.scala 37:14] + node _T_754 = bits(io.in, 31, 27) @[RVC.scala 25:101] + wire _T_755 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 26:19] + _T_755.bits <= _T_750 @[RVC.scala 27:14] + _T_755.rd <= _T_751 @[RVC.scala 28:12] + _T_755.rs1 <= _T_752 @[RVC.scala 29:13] + _T_755.rs2 <= _T_753 @[RVC.scala 30:13] + _T_755.rs3 <= _T_754 @[RVC.scala 31:13] + node _T_756 = bits(io.in, 6, 2) @[RVC.scala 37:14] + node _T_757 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_758 = cat(UInt<5>("h00"), UInt<7>("h067")) @[Cat.scala 29:58] + node _T_759 = cat(_T_756, _T_757) @[Cat.scala 29:58] + node _T_760 = cat(_T_759, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_761 = cat(_T_760, _T_758) @[Cat.scala 29:58] + node _T_762 = shr(_T_761, 7) @[RVC.scala 138:29] + node _T_763 = cat(_T_762, UInt<7>("h01f")) @[Cat.scala 29:58] + node _T_764 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_765 = orr(_T_764) @[RVC.scala 139:37] + node _T_766 = mux(_T_765, _T_761, _T_763) @[RVC.scala 139:33] + node _T_767 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_768 = bits(io.in, 6, 2) @[RVC.scala 37:14] + node _T_769 = bits(io.in, 31, 27) @[RVC.scala 25:101] + wire _T_770 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 26:19] + _T_770.bits <= _T_766 @[RVC.scala 27:14] + _T_770.rd <= UInt<5>("h00") @[RVC.scala 28:12] + _T_770.rs1 <= _T_767 @[RVC.scala 29:13] + _T_770.rs2 <= _T_768 @[RVC.scala 30:13] + _T_770.rs3 <= _T_769 @[RVC.scala 31:13] + node _T_771 = bits(io.in, 6, 2) @[RVC.scala 37:14] + node _T_772 = orr(_T_771) @[RVC.scala 140:27] + node _T_773 = mux(_T_772, _T_743, _T_770) @[RVC.scala 140:22] + node _T_774 = bits(io.in, 6, 2) @[RVC.scala 37:14] + node _T_775 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_776 = cat(UInt<5>("h01"), UInt<7>("h067")) @[Cat.scala 29:58] + node _T_777 = cat(_T_774, _T_775) @[Cat.scala 29:58] + node _T_778 = cat(_T_777, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_779 = cat(_T_778, _T_776) @[Cat.scala 29:58] + node _T_780 = shr(_T_761, 7) @[RVC.scala 142:27] + node _T_781 = cat(_T_780, UInt<7>("h073")) @[Cat.scala 29:58] + node _T_782 = or(_T_781, UInt<21>("h0100000")) @[RVC.scala 142:46] + node _T_783 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_784 = orr(_T_783) @[RVC.scala 143:37] + node _T_785 = mux(_T_784, _T_779, _T_782) @[RVC.scala 143:33] + node _T_786 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_787 = bits(io.in, 6, 2) @[RVC.scala 37:14] + node _T_788 = bits(io.in, 31, 27) @[RVC.scala 25:101] + wire _T_789 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 26:19] + _T_789.bits <= _T_785 @[RVC.scala 27:14] + _T_789.rd <= UInt<5>("h01") @[RVC.scala 28:12] + _T_789.rs1 <= _T_786 @[RVC.scala 29:13] + _T_789.rs2 <= _T_787 @[RVC.scala 30:13] + _T_789.rs3 <= _T_788 @[RVC.scala 31:13] + node _T_790 = bits(io.in, 6, 2) @[RVC.scala 37:14] + node _T_791 = orr(_T_790) @[RVC.scala 144:30] + node _T_792 = mux(_T_791, _T_755, _T_789) @[RVC.scala 144:25] + node _T_793 = bits(io.in, 12, 12) @[RVC.scala 145:12] + node _T_794 = mux(_T_793, _T_792, _T_773) @[RVC.scala 145:10] + node _T_795 = bits(io.in, 9, 7) @[RVC.scala 45:22] + node _T_796 = bits(io.in, 12, 10) @[RVC.scala 45:30] + node _T_797 = cat(_T_795, _T_796) @[Cat.scala 29:58] + node _T_798 = cat(_T_797, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_799 = shr(_T_798, 5) @[RVC.scala 129:34] + node _T_800 = bits(io.in, 6, 2) @[RVC.scala 37:14] + node _T_801 = bits(io.in, 9, 7) @[RVC.scala 45:22] + node _T_802 = bits(io.in, 12, 10) @[RVC.scala 45:30] + node _T_803 = cat(_T_801, _T_802) @[Cat.scala 29:58] + node _T_804 = cat(_T_803, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_805 = bits(_T_804, 4, 0) @[RVC.scala 129:66] + node _T_806 = cat(UInt<3>("h03"), _T_805) @[Cat.scala 29:58] + node _T_807 = cat(_T_806, UInt<7>("h027")) @[Cat.scala 29:58] + node _T_808 = cat(_T_799, _T_800) @[Cat.scala 29:58] + node _T_809 = cat(_T_808, UInt<5>("h02")) @[Cat.scala 29:58] + node _T_810 = cat(_T_809, _T_807) @[Cat.scala 29:58] + node _T_811 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_812 = bits(io.in, 6, 2) @[RVC.scala 37:14] + node _T_813 = bits(io.in, 31, 27) @[RVC.scala 25:101] + wire _T_814 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 26:19] + _T_814.bits <= _T_810 @[RVC.scala 27:14] + _T_814.rd <= _T_811 @[RVC.scala 28:12] + _T_814.rs1 <= UInt<5>("h02") @[RVC.scala 29:13] + _T_814.rs2 <= _T_812 @[RVC.scala 30:13] + _T_814.rs3 <= _T_813 @[RVC.scala 31:13] + node _T_815 = bits(io.in, 8, 7) @[RVC.scala 44:22] + node _T_816 = bits(io.in, 12, 9) @[RVC.scala 44:30] + node _T_817 = cat(_T_815, _T_816) @[Cat.scala 29:58] + node _T_818 = cat(_T_817, UInt<2>("h00")) @[Cat.scala 29:58] + node _T_819 = shr(_T_818, 5) @[RVC.scala 128:33] + node _T_820 = bits(io.in, 6, 2) @[RVC.scala 37:14] + node _T_821 = bits(io.in, 8, 7) @[RVC.scala 44:22] + node _T_822 = bits(io.in, 12, 9) @[RVC.scala 44:30] + node _T_823 = cat(_T_821, _T_822) @[Cat.scala 29:58] + node _T_824 = cat(_T_823, UInt<2>("h00")) @[Cat.scala 29:58] + node _T_825 = bits(_T_824, 4, 0) @[RVC.scala 128:65] + node _T_826 = cat(UInt<3>("h02"), _T_825) @[Cat.scala 29:58] + node _T_827 = cat(_T_826, UInt<7>("h023")) @[Cat.scala 29:58] + node _T_828 = cat(_T_819, _T_820) @[Cat.scala 29:58] + node _T_829 = cat(_T_828, UInt<5>("h02")) @[Cat.scala 29:58] + node _T_830 = cat(_T_829, _T_827) @[Cat.scala 29:58] + node _T_831 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_832 = bits(io.in, 6, 2) @[RVC.scala 37:14] + node _T_833 = bits(io.in, 31, 27) @[RVC.scala 25:101] + wire _T_834 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 26:19] + _T_834.bits <= _T_830 @[RVC.scala 27:14] + _T_834.rd <= _T_831 @[RVC.scala 28:12] + _T_834.rs1 <= UInt<5>("h02") @[RVC.scala 29:13] + _T_834.rs2 <= _T_832 @[RVC.scala 30:13] + _T_834.rs3 <= _T_833 @[RVC.scala 31:13] + node _T_835 = bits(io.in, 8, 7) @[RVC.scala 44:22] + node _T_836 = bits(io.in, 12, 9) @[RVC.scala 44:30] + node _T_837 = cat(_T_835, _T_836) @[Cat.scala 29:58] + node _T_838 = cat(_T_837, UInt<2>("h00")) @[Cat.scala 29:58] + node _T_839 = shr(_T_838, 5) @[RVC.scala 131:40] + node _T_840 = bits(io.in, 6, 2) @[RVC.scala 37:14] + node _T_841 = bits(io.in, 8, 7) @[RVC.scala 44:22] + node _T_842 = bits(io.in, 12, 9) @[RVC.scala 44:30] + node _T_843 = cat(_T_841, _T_842) @[Cat.scala 29:58] + node _T_844 = cat(_T_843, UInt<2>("h00")) @[Cat.scala 29:58] + node _T_845 = bits(_T_844, 4, 0) @[RVC.scala 131:72] + node _T_846 = cat(UInt<3>("h02"), _T_845) @[Cat.scala 29:58] + node _T_847 = cat(_T_846, UInt<7>("h027")) @[Cat.scala 29:58] + node _T_848 = cat(_T_839, _T_840) @[Cat.scala 29:58] + node _T_849 = cat(_T_848, UInt<5>("h02")) @[Cat.scala 29:58] + node _T_850 = cat(_T_849, _T_847) @[Cat.scala 29:58] + node _T_851 = bits(io.in, 11, 7) @[RVC.scala 38:13] + node _T_852 = bits(io.in, 6, 2) @[RVC.scala 37:14] + node _T_853 = bits(io.in, 31, 27) @[RVC.scala 25:101] + wire _T_854 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 26:19] + _T_854.bits <= _T_850 @[RVC.scala 27:14] + _T_854.rd <= _T_851 @[RVC.scala 28:12] + _T_854.rs1 <= UInt<5>("h02") @[RVC.scala 29:13] + _T_854.rs2 <= _T_852 @[RVC.scala 30:13] + _T_854.rs3 <= _T_853 @[RVC.scala 31:13] + node _T_855 = bits(io.in, 11, 7) @[RVC.scala 25:36] + node _T_856 = bits(io.in, 19, 15) @[RVC.scala 25:57] + node _T_857 = bits(io.in, 24, 20) @[RVC.scala 25:79] + node _T_858 = bits(io.in, 31, 27) @[RVC.scala 25:101] + wire _T_859 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 26:19] + _T_859.bits <= io.in @[RVC.scala 27:14] + _T_859.rd <= _T_855 @[RVC.scala 28:12] + _T_859.rs1 <= _T_856 @[RVC.scala 29:13] + _T_859.rs2 <= _T_857 @[RVC.scala 30:13] + _T_859.rs3 <= _T_858 @[RVC.scala 31:13] + node _T_860 = bits(io.in, 11, 7) @[RVC.scala 25:36] + node _T_861 = bits(io.in, 19, 15) @[RVC.scala 25:57] + node _T_862 = bits(io.in, 24, 20) @[RVC.scala 25:79] + node _T_863 = bits(io.in, 31, 27) @[RVC.scala 25:101] + wire _T_864 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 26:19] + _T_864.bits <= io.in @[RVC.scala 27:14] + _T_864.rd <= _T_860 @[RVC.scala 28:12] + _T_864.rs1 <= _T_861 @[RVC.scala 29:13] + _T_864.rs2 <= _T_862 @[RVC.scala 30:13] + _T_864.rs3 <= _T_863 @[RVC.scala 31:13] + node _T_865 = bits(io.in, 11, 7) @[RVC.scala 25:36] + node _T_866 = bits(io.in, 19, 15) @[RVC.scala 25:57] + node _T_867 = bits(io.in, 24, 20) @[RVC.scala 25:79] + node _T_868 = bits(io.in, 31, 27) @[RVC.scala 25:101] + wire _T_869 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 26:19] + _T_869.bits <= io.in @[RVC.scala 27:14] + _T_869.rd <= _T_865 @[RVC.scala 28:12] + _T_869.rs1 <= _T_866 @[RVC.scala 29:13] + _T_869.rs2 <= _T_867 @[RVC.scala 30:13] + _T_869.rs3 <= _T_868 @[RVC.scala 31:13] + node _T_870 = bits(io.in, 11, 7) @[RVC.scala 25:36] + node _T_871 = bits(io.in, 19, 15) @[RVC.scala 25:57] + node _T_872 = bits(io.in, 24, 20) @[RVC.scala 25:79] + node _T_873 = bits(io.in, 31, 27) @[RVC.scala 25:101] + wire _T_874 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 26:19] + _T_874.bits <= io.in @[RVC.scala 27:14] + _T_874.rd <= _T_870 @[RVC.scala 28:12] + _T_874.rs1 <= _T_871 @[RVC.scala 29:13] + _T_874.rs2 <= _T_872 @[RVC.scala 30:13] + _T_874.rs3 <= _T_873 @[RVC.scala 31:13] + node _T_875 = bits(io.in, 11, 7) @[RVC.scala 25:36] + node _T_876 = bits(io.in, 19, 15) @[RVC.scala 25:57] + node _T_877 = bits(io.in, 24, 20) @[RVC.scala 25:79] + node _T_878 = bits(io.in, 31, 27) @[RVC.scala 25:101] + wire _T_879 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 26:19] + _T_879.bits <= io.in @[RVC.scala 27:14] + _T_879.rd <= _T_875 @[RVC.scala 28:12] + _T_879.rs1 <= _T_876 @[RVC.scala 29:13] + _T_879.rs2 <= _T_877 @[RVC.scala 30:13] + _T_879.rs3 <= _T_878 @[RVC.scala 31:13] + node _T_880 = bits(io.in, 11, 7) @[RVC.scala 25:36] + node _T_881 = bits(io.in, 19, 15) @[RVC.scala 25:57] + node _T_882 = bits(io.in, 24, 20) @[RVC.scala 25:79] + node _T_883 = bits(io.in, 31, 27) @[RVC.scala 25:101] + wire _T_884 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 26:19] + _T_884.bits <= io.in @[RVC.scala 27:14] + _T_884.rd <= _T_880 @[RVC.scala 28:12] + _T_884.rs1 <= _T_881 @[RVC.scala 29:13] + _T_884.rs2 <= _T_882 @[RVC.scala 30:13] + _T_884.rs3 <= _T_883 @[RVC.scala 31:13] + node _T_885 = bits(io.in, 11, 7) @[RVC.scala 25:36] + node _T_886 = bits(io.in, 19, 15) @[RVC.scala 25:57] + node _T_887 = bits(io.in, 24, 20) @[RVC.scala 25:79] + node _T_888 = bits(io.in, 31, 27) @[RVC.scala 25:101] + wire _T_889 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 26:19] + _T_889.bits <= io.in @[RVC.scala 27:14] + _T_889.rd <= _T_885 @[RVC.scala 28:12] + _T_889.rs1 <= _T_886 @[RVC.scala 29:13] + _T_889.rs2 <= _T_887 @[RVC.scala 30:13] + _T_889.rs3 <= _T_888 @[RVC.scala 31:13] + node _T_890 = bits(io.in, 11, 7) @[RVC.scala 25:36] + node _T_891 = bits(io.in, 19, 15) @[RVC.scala 25:57] + node _T_892 = bits(io.in, 24, 20) @[RVC.scala 25:79] + node _T_893 = bits(io.in, 31, 27) @[RVC.scala 25:101] + wire _T_894 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 26:19] + _T_894.bits <= io.in @[RVC.scala 27:14] + _T_894.rd <= _T_890 @[RVC.scala 28:12] + _T_894.rs1 <= _T_891 @[RVC.scala 29:13] + _T_894.rs2 <= _T_892 @[RVC.scala 30:13] + _T_894.rs3 <= _T_893 @[RVC.scala 31:13] + wire _T_895 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}[32] @[RVC.scala 155:20] + _T_895[0].rs3 <= _T_24.rs3 @[RVC.scala 155:20] + _T_895[0].rs2 <= _T_24.rs2 @[RVC.scala 155:20] + _T_895[0].rs1 <= _T_24.rs1 @[RVC.scala 155:20] + _T_895[0].rd <= _T_24.rd @[RVC.scala 155:20] + _T_895[0].bits <= _T_24.bits @[RVC.scala 155:20] + _T_895[1].rs3 <= _T_44.rs3 @[RVC.scala 155:20] + _T_895[1].rs2 <= _T_44.rs2 @[RVC.scala 155:20] + _T_895[1].rs1 <= _T_44.rs1 @[RVC.scala 155:20] + _T_895[1].rd <= _T_44.rd @[RVC.scala 155:20] + _T_895[1].bits <= _T_44.bits @[RVC.scala 155:20] + _T_895[2].rs3 <= _T_66.rs3 @[RVC.scala 155:20] + _T_895[2].rs2 <= _T_66.rs2 @[RVC.scala 155:20] + _T_895[2].rs1 <= _T_66.rs1 @[RVC.scala 155:20] + _T_895[2].rd <= _T_66.rd @[RVC.scala 155:20] + _T_895[2].bits <= _T_66.bits @[RVC.scala 155:20] + _T_895[3].rs3 <= _T_88.rs3 @[RVC.scala 155:20] + _T_895[3].rs2 <= _T_88.rs2 @[RVC.scala 155:20] + _T_895[3].rs1 <= _T_88.rs1 @[RVC.scala 155:20] + _T_895[3].rd <= _T_88.rd @[RVC.scala 155:20] + _T_895[3].bits <= _T_88.bits @[RVC.scala 155:20] + _T_895[4].rs3 <= _T_119.rs3 @[RVC.scala 155:20] + _T_895[4].rs2 <= _T_119.rs2 @[RVC.scala 155:20] + _T_895[4].rs1 <= _T_119.rs1 @[RVC.scala 155:20] + _T_895[4].rd <= _T_119.rd @[RVC.scala 155:20] + _T_895[4].bits <= _T_119.bits @[RVC.scala 155:20] + _T_895[5].rs3 <= _T_146.rs3 @[RVC.scala 155:20] + _T_895[5].rs2 <= _T_146.rs2 @[RVC.scala 155:20] + _T_895[5].rs1 <= _T_146.rs1 @[RVC.scala 155:20] + _T_895[5].rd <= _T_146.rd @[RVC.scala 155:20] + _T_895[5].bits <= _T_146.bits @[RVC.scala 155:20] + _T_895[6].rs3 <= _T_177.rs3 @[RVC.scala 155:20] + _T_895[6].rs2 <= _T_177.rs2 @[RVC.scala 155:20] + _T_895[6].rs1 <= _T_177.rs1 @[RVC.scala 155:20] + _T_895[6].rd <= _T_177.rd @[RVC.scala 155:20] + _T_895[6].bits <= _T_177.bits @[RVC.scala 155:20] + _T_895[7].rs3 <= _T_208.rs3 @[RVC.scala 155:20] + _T_895[7].rs2 <= _T_208.rs2 @[RVC.scala 155:20] + _T_895[7].rs1 <= _T_208.rs1 @[RVC.scala 155:20] + _T_895[7].rd <= _T_208.rd @[RVC.scala 155:20] + _T_895[7].bits <= _T_208.bits @[RVC.scala 155:20] + _T_895[8].rs3 <= _T_225.rs3 @[RVC.scala 155:20] + _T_895[8].rs2 <= _T_225.rs2 @[RVC.scala 155:20] + _T_895[8].rs1 <= _T_225.rs1 @[RVC.scala 155:20] + _T_895[8].rd <= _T_225.rd @[RVC.scala 155:20] + _T_895[8].bits <= _T_225.bits @[RVC.scala 155:20] + _T_895[9].rs3 <= _T_311.rs3 @[RVC.scala 155:20] + _T_895[9].rs2 <= _T_311.rs2 @[RVC.scala 155:20] + _T_895[9].rs1 <= _T_311.rs1 @[RVC.scala 155:20] + _T_895[9].rd <= _T_311.rd @[RVC.scala 155:20] + _T_895[9].bits <= _T_311.bits @[RVC.scala 155:20] + _T_895[10].rs3 <= _T_326.rs3 @[RVC.scala 155:20] + _T_895[10].rs2 <= _T_326.rs2 @[RVC.scala 155:20] + _T_895[10].rs1 <= _T_326.rs1 @[RVC.scala 155:20] + _T_895[10].rd <= _T_326.rd @[RVC.scala 155:20] + _T_895[10].bits <= _T_326.bits @[RVC.scala 155:20] + _T_895[11].rs3 <= _T_386.rs3 @[RVC.scala 155:20] + _T_895[11].rs2 <= _T_386.rs2 @[RVC.scala 155:20] + _T_895[11].rs1 <= _T_386.rs1 @[RVC.scala 155:20] + _T_895[11].rd <= _T_386.rd @[RVC.scala 155:20] + _T_895[11].bits <= _T_386.bits @[RVC.scala 155:20] + _T_895[12].rs3 <= _T_452.rs3 @[RVC.scala 155:20] + _T_895[12].rs2 <= _T_452.rs2 @[RVC.scala 155:20] + _T_895[12].rs1 <= _T_452.rs1 @[RVC.scala 155:20] + _T_895[12].rd <= _T_452.rd @[RVC.scala 155:20] + _T_895[12].bits <= _T_452.bits @[RVC.scala 155:20] + _T_895[13].rs3 <= _T_539.rs3 @[RVC.scala 155:20] + _T_895[13].rs2 <= _T_539.rs2 @[RVC.scala 155:20] + _T_895[13].rs1 <= _T_539.rs1 @[RVC.scala 155:20] + _T_895[13].rd <= _T_539.rd @[RVC.scala 155:20] + _T_895[13].bits <= _T_539.bits @[RVC.scala 155:20] + _T_895[14].rs3 <= _T_606.rs3 @[RVC.scala 155:20] + _T_895[14].rs2 <= _T_606.rs2 @[RVC.scala 155:20] + _T_895[14].rs1 <= _T_606.rs1 @[RVC.scala 155:20] + _T_895[14].rd <= _T_606.rd @[RVC.scala 155:20] + _T_895[14].bits <= _T_606.bits @[RVC.scala 155:20] + _T_895[15].rs3 <= _T_671.rs3 @[RVC.scala 155:20] + _T_895[15].rs2 <= _T_671.rs2 @[RVC.scala 155:20] + _T_895[15].rs1 <= _T_671.rs1 @[RVC.scala 155:20] + _T_895[15].rd <= _T_671.rd @[RVC.scala 155:20] + _T_895[15].bits <= _T_671.bits @[RVC.scala 155:20] + _T_895[16].rs3 <= _T_688.rs3 @[RVC.scala 155:20] + _T_895[16].rs2 <= _T_688.rs2 @[RVC.scala 155:20] + _T_895[16].rs1 <= _T_688.rs1 @[RVC.scala 155:20] + _T_895[16].rd <= _T_688.rd @[RVC.scala 155:20] + _T_895[16].bits <= _T_688.bits @[RVC.scala 155:20] + _T_895[17].rs3 <= _T_703.rs3 @[RVC.scala 155:20] + _T_895[17].rs2 <= _T_703.rs2 @[RVC.scala 155:20] + _T_895[17].rs1 <= _T_703.rs1 @[RVC.scala 155:20] + _T_895[17].rd <= _T_703.rd @[RVC.scala 155:20] + _T_895[17].bits <= _T_703.bits @[RVC.scala 155:20] + _T_895[18].rs3 <= _T_718.rs3 @[RVC.scala 155:20] + _T_895[18].rs2 <= _T_718.rs2 @[RVC.scala 155:20] + _T_895[18].rs1 <= _T_718.rs1 @[RVC.scala 155:20] + _T_895[18].rd <= _T_718.rd @[RVC.scala 155:20] + _T_895[18].bits <= _T_718.bits @[RVC.scala 155:20] + _T_895[19].rs3 <= _T_733.rs3 @[RVC.scala 155:20] + _T_895[19].rs2 <= _T_733.rs2 @[RVC.scala 155:20] + _T_895[19].rs1 <= _T_733.rs1 @[RVC.scala 155:20] + _T_895[19].rd <= _T_733.rd @[RVC.scala 155:20] + _T_895[19].bits <= _T_733.bits @[RVC.scala 155:20] + _T_895[20].rs3 <= _T_794.rs3 @[RVC.scala 155:20] + _T_895[20].rs2 <= _T_794.rs2 @[RVC.scala 155:20] + _T_895[20].rs1 <= _T_794.rs1 @[RVC.scala 155:20] + _T_895[20].rd <= _T_794.rd @[RVC.scala 155:20] + _T_895[20].bits <= _T_794.bits @[RVC.scala 155:20] + _T_895[21].rs3 <= _T_814.rs3 @[RVC.scala 155:20] + _T_895[21].rs2 <= _T_814.rs2 @[RVC.scala 155:20] + _T_895[21].rs1 <= _T_814.rs1 @[RVC.scala 155:20] + _T_895[21].rd <= _T_814.rd @[RVC.scala 155:20] + _T_895[21].bits <= _T_814.bits @[RVC.scala 155:20] + _T_895[22].rs3 <= _T_834.rs3 @[RVC.scala 155:20] + _T_895[22].rs2 <= _T_834.rs2 @[RVC.scala 155:20] + _T_895[22].rs1 <= _T_834.rs1 @[RVC.scala 155:20] + _T_895[22].rd <= _T_834.rd @[RVC.scala 155:20] + _T_895[22].bits <= _T_834.bits @[RVC.scala 155:20] + _T_895[23].rs3 <= _T_854.rs3 @[RVC.scala 155:20] + _T_895[23].rs2 <= _T_854.rs2 @[RVC.scala 155:20] + _T_895[23].rs1 <= _T_854.rs1 @[RVC.scala 155:20] + _T_895[23].rd <= _T_854.rd @[RVC.scala 155:20] + _T_895[23].bits <= _T_854.bits @[RVC.scala 155:20] + _T_895[24].rs3 <= _T_859.rs3 @[RVC.scala 155:20] + _T_895[24].rs2 <= _T_859.rs2 @[RVC.scala 155:20] + _T_895[24].rs1 <= _T_859.rs1 @[RVC.scala 155:20] + _T_895[24].rd <= _T_859.rd @[RVC.scala 155:20] + _T_895[24].bits <= _T_859.bits @[RVC.scala 155:20] + _T_895[25].rs3 <= _T_864.rs3 @[RVC.scala 155:20] + _T_895[25].rs2 <= _T_864.rs2 @[RVC.scala 155:20] + _T_895[25].rs1 <= _T_864.rs1 @[RVC.scala 155:20] + _T_895[25].rd <= _T_864.rd @[RVC.scala 155:20] + _T_895[25].bits <= _T_864.bits @[RVC.scala 155:20] + _T_895[26].rs3 <= _T_869.rs3 @[RVC.scala 155:20] + _T_895[26].rs2 <= _T_869.rs2 @[RVC.scala 155:20] + _T_895[26].rs1 <= _T_869.rs1 @[RVC.scala 155:20] + _T_895[26].rd <= _T_869.rd @[RVC.scala 155:20] + _T_895[26].bits <= _T_869.bits @[RVC.scala 155:20] + _T_895[27].rs3 <= _T_874.rs3 @[RVC.scala 155:20] + _T_895[27].rs2 <= _T_874.rs2 @[RVC.scala 155:20] + _T_895[27].rs1 <= _T_874.rs1 @[RVC.scala 155:20] + _T_895[27].rd <= _T_874.rd @[RVC.scala 155:20] + _T_895[27].bits <= _T_874.bits @[RVC.scala 155:20] + _T_895[28].rs3 <= _T_879.rs3 @[RVC.scala 155:20] + _T_895[28].rs2 <= _T_879.rs2 @[RVC.scala 155:20] + _T_895[28].rs1 <= _T_879.rs1 @[RVC.scala 155:20] + _T_895[28].rd <= _T_879.rd @[RVC.scala 155:20] + _T_895[28].bits <= _T_879.bits @[RVC.scala 155:20] + _T_895[29].rs3 <= _T_884.rs3 @[RVC.scala 155:20] + _T_895[29].rs2 <= _T_884.rs2 @[RVC.scala 155:20] + _T_895[29].rs1 <= _T_884.rs1 @[RVC.scala 155:20] + _T_895[29].rd <= _T_884.rd @[RVC.scala 155:20] + _T_895[29].bits <= _T_884.bits @[RVC.scala 155:20] + _T_895[30].rs3 <= _T_889.rs3 @[RVC.scala 155:20] + _T_895[30].rs2 <= _T_889.rs2 @[RVC.scala 155:20] + _T_895[30].rs1 <= _T_889.rs1 @[RVC.scala 155:20] + _T_895[30].rd <= _T_889.rd @[RVC.scala 155:20] + _T_895[30].bits <= _T_889.bits @[RVC.scala 155:20] + _T_895[31].rs3 <= _T_894.rs3 @[RVC.scala 155:20] + _T_895[31].rs2 <= _T_894.rs2 @[RVC.scala 155:20] + _T_895[31].rs1 <= _T_894.rs1 @[RVC.scala 155:20] + _T_895[31].rd <= _T_894.rd @[RVC.scala 155:20] + _T_895[31].bits <= _T_894.bits @[RVC.scala 155:20] + node _T_896 = bits(io.in, 1, 0) @[RVC.scala 156:12] + node _T_897 = bits(io.in, 15, 13) @[RVC.scala 156:20] + node _T_898 = cat(_T_896, _T_897) @[Cat.scala 29:58] + io.out.rs3 <= _T_895[_T_898].rs3 @[RVC.scala 204:12] + io.out.rs2 <= _T_895[_T_898].rs2 @[RVC.scala 204:12] + io.out.rs1 <= _T_895[_T_898].rs1 @[RVC.scala 204:12] + io.out.rd <= _T_895[_T_898].rd @[RVC.scala 204:12] + io.out.bits <= _T_895[_T_898].bits @[RVC.scala 204:12] + node _T_899 = bits(io.in, 13, 13) @[RVC.scala 205:24] + node _T_900 = eq(_T_899, UInt<1>("h00")) @[RVC.scala 205:18] + node _T_901 = bits(io.in, 12, 12) @[RVC.scala 205:37] + node _T_902 = eq(_T_901, UInt<1>("h00")) @[RVC.scala 205:31] + node _T_903 = and(_T_900, _T_902) @[RVC.scala 205:29] + node _T_904 = bits(io.in, 11, 11) @[RVC.scala 205:49] + node _T_905 = and(_T_903, _T_904) @[RVC.scala 205:42] + node _T_906 = bits(io.in, 1, 1) @[RVC.scala 205:60] + node _T_907 = and(_T_905, _T_906) @[RVC.scala 205:54] + node _T_908 = bits(io.in, 0, 0) @[RVC.scala 205:71] + node _T_909 = eq(_T_908, UInt<1>("h00")) @[RVC.scala 205:65] + node _T_910 = and(_T_907, _T_909) @[RVC.scala 205:63] + node _T_911 = bits(io.in, 13, 13) @[RVC.scala 206:14] + node _T_912 = eq(_T_911, UInt<1>("h00")) @[RVC.scala 206:8] + node _T_913 = bits(io.in, 12, 12) @[RVC.scala 206:27] + node _T_914 = eq(_T_913, UInt<1>("h00")) @[RVC.scala 206:21] + node _T_915 = and(_T_912, _T_914) @[RVC.scala 206:19] + node _T_916 = bits(io.in, 6, 6) @[RVC.scala 206:39] + node _T_917 = and(_T_915, _T_916) @[RVC.scala 206:32] + node _T_918 = bits(io.in, 1, 1) @[RVC.scala 206:49] + node _T_919 = and(_T_917, _T_918) @[RVC.scala 206:43] + node _T_920 = bits(io.in, 0, 0) @[RVC.scala 206:60] + node _T_921 = eq(_T_920, UInt<1>("h00")) @[RVC.scala 206:54] + node _T_922 = and(_T_919, _T_921) @[RVC.scala 206:52] + node _T_923 = or(_T_910, _T_922) @[RVC.scala 205:76] + node _T_924 = bits(io.in, 15, 15) @[RVC.scala 207:14] + node _T_925 = eq(_T_924, UInt<1>("h00")) @[RVC.scala 207:8] + node _T_926 = bits(io.in, 13, 13) @[RVC.scala 207:27] + node _T_927 = eq(_T_926, UInt<1>("h00")) @[RVC.scala 207:21] + node _T_928 = and(_T_925, _T_927) @[RVC.scala 207:19] + node _T_929 = bits(io.in, 11, 11) @[RVC.scala 207:38] + node _T_930 = bits(io.in, 1, 1) @[RVC.scala 207:49] + node _T_931 = eq(_T_930, UInt<1>("h00")) @[RVC.scala 207:43] + node _T_932 = dshr(_T_929, _T_931) @[RVC.scala 207:42] + node _T_933 = bits(_T_932, 0, 0) @[RVC.scala 207:42] + node _T_934 = and(_T_928, _T_933) @[RVC.scala 207:32] + node _T_935 = or(_T_923, _T_934) @[RVC.scala 206:65] + node _T_936 = bits(io.in, 13, 13) @[RVC.scala 208:14] + node _T_937 = eq(_T_936, UInt<1>("h00")) @[RVC.scala 208:8] + node _T_938 = bits(io.in, 12, 12) @[RVC.scala 208:27] + node _T_939 = eq(_T_938, UInt<1>("h00")) @[RVC.scala 208:21] + node _T_940 = and(_T_937, _T_939) @[RVC.scala 208:19] + node _T_941 = bits(io.in, 5, 5) @[RVC.scala 208:38] + node _T_942 = and(_T_940, _T_941) @[RVC.scala 208:32] + node _T_943 = bits(io.in, 1, 1) @[RVC.scala 208:47] + node _T_944 = and(_T_942, _T_943) @[RVC.scala 208:41] + node _T_945 = bits(io.in, 0, 0) @[RVC.scala 208:58] + node _T_946 = eq(_T_945, UInt<1>("h00")) @[RVC.scala 208:52] + node _T_947 = and(_T_944, _T_946) @[RVC.scala 208:50] + node _T_948 = or(_T_935, _T_947) @[RVC.scala 207:54] + node _T_949 = bits(io.in, 13, 13) @[RVC.scala 209:14] + node _T_950 = eq(_T_949, UInt<1>("h00")) @[RVC.scala 209:8] + node _T_951 = bits(io.in, 12, 12) @[RVC.scala 209:27] + node _T_952 = eq(_T_951, UInt<1>("h00")) @[RVC.scala 209:21] + node _T_953 = and(_T_950, _T_952) @[RVC.scala 209:19] + node _T_954 = bits(io.in, 10, 10) @[RVC.scala 209:38] + node _T_955 = and(_T_953, _T_954) @[RVC.scala 209:32] + node _T_956 = bits(io.in, 1, 1) @[RVC.scala 209:50] + node _T_957 = eq(_T_956, UInt<1>("h00")) @[RVC.scala 209:44] + node _T_958 = and(_T_955, _T_957) @[RVC.scala 209:42] + node _T_959 = bits(io.in, 0, 0) @[RVC.scala 209:60] + node _T_960 = and(_T_958, _T_959) @[RVC.scala 209:54] + node _T_961 = or(_T_948, _T_960) @[RVC.scala 208:63] + node _T_962 = bits(io.in, 15, 15) @[RVC.scala 210:14] + node _T_963 = eq(_T_962, UInt<1>("h00")) @[RVC.scala 210:8] + node _T_964 = bits(io.in, 13, 13) @[RVC.scala 210:27] + node _T_965 = eq(_T_964, UInt<1>("h00")) @[RVC.scala 210:21] + node _T_966 = and(_T_963, _T_965) @[RVC.scala 210:19] + node _T_967 = bits(io.in, 6, 6) @[RVC.scala 210:38] + node _T_968 = and(_T_966, _T_967) @[RVC.scala 210:32] + node _T_969 = bits(io.in, 1, 1) @[RVC.scala 210:49] + node _T_970 = eq(_T_969, UInt<1>("h00")) @[RVC.scala 210:43] + node _T_971 = and(_T_968, _T_970) @[RVC.scala 210:41] + node _T_972 = or(_T_961, _T_971) @[RVC.scala 209:64] + node _T_973 = bits(io.in, 15, 15) @[RVC.scala 210:61] + node _T_974 = bits(io.in, 12, 12) @[RVC.scala 210:73] + node _T_975 = eq(_T_974, UInt<1>("h00")) @[RVC.scala 210:67] + node _T_976 = and(_T_973, _T_975) @[RVC.scala 210:65] + node _T_977 = bits(io.in, 1, 1) @[RVC.scala 210:86] + node _T_978 = eq(_T_977, UInt<1>("h00")) @[RVC.scala 210:80] + node _T_979 = and(_T_976, _T_978) @[RVC.scala 210:78] + node _T_980 = bits(io.in, 0, 0) @[RVC.scala 210:96] + node _T_981 = and(_T_979, _T_980) @[RVC.scala 210:90] + node _T_982 = or(_T_972, _T_981) @[RVC.scala 210:54] + node _T_983 = bits(io.in, 13, 13) @[RVC.scala 211:14] + node _T_984 = eq(_T_983, UInt<1>("h00")) @[RVC.scala 211:8] + node _T_985 = bits(io.in, 12, 12) @[RVC.scala 211:27] + node _T_986 = eq(_T_985, UInt<1>("h00")) @[RVC.scala 211:21] + node _T_987 = and(_T_984, _T_986) @[RVC.scala 211:19] + node _T_988 = bits(io.in, 9, 9) @[RVC.scala 211:38] + node _T_989 = and(_T_987, _T_988) @[RVC.scala 211:32] + node _T_990 = bits(io.in, 1, 1) @[RVC.scala 211:47] + node _T_991 = and(_T_989, _T_990) @[RVC.scala 211:41] + node _T_992 = bits(io.in, 0, 0) @[RVC.scala 211:58] + node _T_993 = eq(_T_992, UInt<1>("h00")) @[RVC.scala 211:52] + node _T_994 = and(_T_991, _T_993) @[RVC.scala 211:50] + node _T_995 = or(_T_982, _T_994) @[RVC.scala 210:100] + node _T_996 = bits(io.in, 12, 12) @[RVC.scala 212:14] + node _T_997 = eq(_T_996, UInt<1>("h00")) @[RVC.scala 212:8] + node _T_998 = bits(io.in, 6, 6) @[RVC.scala 212:25] + node _T_999 = and(_T_997, _T_998) @[RVC.scala 212:19] + node _T_1000 = bits(io.in, 1, 1) @[RVC.scala 212:36] + node _T_1001 = eq(_T_1000, UInt<1>("h00")) @[RVC.scala 212:30] + node _T_1002 = and(_T_999, _T_1001) @[RVC.scala 212:28] + node _T_1003 = bits(io.in, 0, 0) @[RVC.scala 212:46] + node _T_1004 = and(_T_1002, _T_1003) @[RVC.scala 212:40] + node _T_1005 = or(_T_995, _T_1004) @[RVC.scala 211:63] + node _T_1006 = bits(io.in, 15, 15) @[RVC.scala 213:14] + node _T_1007 = eq(_T_1006, UInt<1>("h00")) @[RVC.scala 213:8] + node _T_1008 = bits(io.in, 13, 13) @[RVC.scala 213:27] + node _T_1009 = eq(_T_1008, UInt<1>("h00")) @[RVC.scala 213:21] + node _T_1010 = and(_T_1007, _T_1009) @[RVC.scala 213:19] + node _T_1011 = bits(io.in, 5, 5) @[RVC.scala 213:38] + node _T_1012 = and(_T_1010, _T_1011) @[RVC.scala 213:32] + node _T_1013 = bits(io.in, 1, 1) @[RVC.scala 213:49] + node _T_1014 = eq(_T_1013, UInt<1>("h00")) @[RVC.scala 213:43] + node _T_1015 = and(_T_1012, _T_1014) @[RVC.scala 213:41] + node _T_1016 = or(_T_1005, _T_1015) @[RVC.scala 212:50] + node _T_1017 = bits(io.in, 13, 13) @[RVC.scala 214:14] + node _T_1018 = eq(_T_1017, UInt<1>("h00")) @[RVC.scala 214:8] + node _T_1019 = bits(io.in, 12, 12) @[RVC.scala 214:27] + node _T_1020 = eq(_T_1019, UInt<1>("h00")) @[RVC.scala 214:21] + node _T_1021 = and(_T_1018, _T_1020) @[RVC.scala 214:19] + node _T_1022 = bits(io.in, 8, 8) @[RVC.scala 214:38] + node _T_1023 = and(_T_1021, _T_1022) @[RVC.scala 214:32] + node _T_1024 = bits(io.in, 1, 1) @[RVC.scala 214:47] + node _T_1025 = and(_T_1023, _T_1024) @[RVC.scala 214:41] + node _T_1026 = bits(io.in, 0, 0) @[RVC.scala 214:58] + node _T_1027 = eq(_T_1026, UInt<1>("h00")) @[RVC.scala 214:52] + node _T_1028 = and(_T_1025, _T_1027) @[RVC.scala 214:50] + node _T_1029 = or(_T_1016, _T_1028) @[RVC.scala 213:54] + node _T_1030 = bits(io.in, 12, 12) @[RVC.scala 215:14] + node _T_1031 = eq(_T_1030, UInt<1>("h00")) @[RVC.scala 215:8] + node _T_1032 = bits(io.in, 5, 5) @[RVC.scala 215:25] + node _T_1033 = and(_T_1031, _T_1032) @[RVC.scala 215:19] + node _T_1034 = bits(io.in, 1, 1) @[RVC.scala 215:36] + node _T_1035 = eq(_T_1034, UInt<1>("h00")) @[RVC.scala 215:30] + node _T_1036 = and(_T_1033, _T_1035) @[RVC.scala 215:28] + node _T_1037 = bits(io.in, 0, 0) @[RVC.scala 215:46] + node _T_1038 = and(_T_1036, _T_1037) @[RVC.scala 215:40] + node _T_1039 = or(_T_1029, _T_1038) @[RVC.scala 214:63] + node _T_1040 = bits(io.in, 15, 15) @[RVC.scala 216:14] + node _T_1041 = eq(_T_1040, UInt<1>("h00")) @[RVC.scala 216:8] + node _T_1042 = bits(io.in, 13, 13) @[RVC.scala 216:27] + node _T_1043 = eq(_T_1042, UInt<1>("h00")) @[RVC.scala 216:21] + node _T_1044 = and(_T_1041, _T_1043) @[RVC.scala 216:19] + node _T_1045 = bits(io.in, 10, 10) @[RVC.scala 216:38] + node _T_1046 = and(_T_1044, _T_1045) @[RVC.scala 216:32] + node _T_1047 = bits(io.in, 1, 1) @[RVC.scala 216:50] + node _T_1048 = eq(_T_1047, UInt<1>("h00")) @[RVC.scala 216:44] + node _T_1049 = and(_T_1046, _T_1048) @[RVC.scala 216:42] + node _T_1050 = or(_T_1039, _T_1049) @[RVC.scala 215:50] + node _T_1051 = bits(io.in, 13, 13) @[RVC.scala 216:64] + node _T_1052 = eq(_T_1051, UInt<1>("h00")) @[RVC.scala 216:58] + node _T_1053 = bits(io.in, 12, 12) @[RVC.scala 216:77] + node _T_1054 = eq(_T_1053, UInt<1>("h00")) @[RVC.scala 216:71] + node _T_1055 = and(_T_1052, _T_1054) @[RVC.scala 216:69] + node _T_1056 = bits(io.in, 7, 7) @[RVC.scala 216:88] + node _T_1057 = and(_T_1055, _T_1056) @[RVC.scala 216:82] + node _T_1058 = bits(io.in, 1, 1) @[RVC.scala 216:97] + node _T_1059 = and(_T_1057, _T_1058) @[RVC.scala 216:91] + node _T_1060 = bits(io.in, 0, 0) @[RVC.scala 216:108] + node _T_1061 = eq(_T_1060, UInt<1>("h00")) @[RVC.scala 216:102] + node _T_1062 = and(_T_1059, _T_1061) @[RVC.scala 216:100] + node _T_1063 = or(_T_1050, _T_1062) @[RVC.scala 216:55] + node _T_1064 = bits(io.in, 12, 12) @[RVC.scala 217:12] + node _T_1065 = bits(io.in, 11, 11) @[RVC.scala 217:22] + node _T_1066 = and(_T_1064, _T_1065) @[RVC.scala 217:16] + node _T_1067 = bits(io.in, 10, 10) @[RVC.scala 217:34] + node _T_1068 = eq(_T_1067, UInt<1>("h00")) @[RVC.scala 217:28] + node _T_1069 = and(_T_1066, _T_1068) @[RVC.scala 217:26] + node _T_1070 = bits(io.in, 1, 1) @[RVC.scala 217:47] + node _T_1071 = eq(_T_1070, UInt<1>("h00")) @[RVC.scala 217:41] + node _T_1072 = and(_T_1069, _T_1071) @[RVC.scala 217:39] + node _T_1073 = bits(io.in, 0, 0) @[RVC.scala 217:57] + node _T_1074 = and(_T_1072, _T_1073) @[RVC.scala 217:51] + node _T_1075 = or(_T_1063, _T_1074) @[RVC.scala 216:113] + node _T_1076 = bits(io.in, 15, 15) @[RVC.scala 217:70] + node _T_1077 = eq(_T_1076, UInt<1>("h00")) @[RVC.scala 217:64] + node _T_1078 = bits(io.in, 13, 13) @[RVC.scala 217:83] + node _T_1079 = eq(_T_1078, UInt<1>("h00")) @[RVC.scala 217:77] + node _T_1080 = and(_T_1077, _T_1079) @[RVC.scala 217:75] + node _T_1081 = bits(io.in, 9, 9) @[RVC.scala 217:94] + node _T_1082 = and(_T_1080, _T_1081) @[RVC.scala 217:88] + node _T_1083 = bits(io.in, 1, 1) @[RVC.scala 217:105] + node _T_1084 = eq(_T_1083, UInt<1>("h00")) @[RVC.scala 217:99] + node _T_1085 = and(_T_1082, _T_1084) @[RVC.scala 217:97] + node _T_1086 = or(_T_1075, _T_1085) @[RVC.scala 217:61] + node _T_1087 = bits(io.in, 13, 13) @[RVC.scala 218:14] + node _T_1088 = eq(_T_1087, UInt<1>("h00")) @[RVC.scala 218:8] + node _T_1089 = bits(io.in, 12, 12) @[RVC.scala 218:27] + node _T_1090 = eq(_T_1089, UInt<1>("h00")) @[RVC.scala 218:21] + node _T_1091 = and(_T_1088, _T_1090) @[RVC.scala 218:19] + node _T_1092 = bits(io.in, 4, 4) @[RVC.scala 218:38] + node _T_1093 = and(_T_1091, _T_1092) @[RVC.scala 218:32] + node _T_1094 = bits(io.in, 1, 1) @[RVC.scala 218:47] + node _T_1095 = and(_T_1093, _T_1094) @[RVC.scala 218:41] + node _T_1096 = bits(io.in, 0, 0) @[RVC.scala 218:58] + node _T_1097 = eq(_T_1096, UInt<1>("h00")) @[RVC.scala 218:52] + node _T_1098 = and(_T_1095, _T_1097) @[RVC.scala 218:50] + node _T_1099 = or(_T_1086, _T_1098) @[RVC.scala 217:110] + node _T_1100 = bits(io.in, 13, 13) @[RVC.scala 218:70] + node _T_1101 = bits(io.in, 12, 12) @[RVC.scala 218:80] + node _T_1102 = and(_T_1100, _T_1101) @[RVC.scala 218:74] + node _T_1103 = bits(io.in, 1, 1) @[RVC.scala 218:92] + node _T_1104 = eq(_T_1103, UInt<1>("h00")) @[RVC.scala 218:86] + node _T_1105 = and(_T_1102, _T_1104) @[RVC.scala 218:84] + node _T_1106 = bits(io.in, 0, 0) @[RVC.scala 218:102] + node _T_1107 = and(_T_1105, _T_1106) @[RVC.scala 218:96] + node _T_1108 = or(_T_1099, _T_1107) @[RVC.scala 218:63] + node _T_1109 = bits(io.in, 15, 15) @[RVC.scala 219:14] + node _T_1110 = eq(_T_1109, UInt<1>("h00")) @[RVC.scala 219:8] + node _T_1111 = bits(io.in, 13, 13) @[RVC.scala 219:27] + node _T_1112 = eq(_T_1111, UInt<1>("h00")) @[RVC.scala 219:21] + node _T_1113 = and(_T_1110, _T_1112) @[RVC.scala 219:19] + node _T_1114 = bits(io.in, 8, 8) @[RVC.scala 219:38] + node _T_1115 = and(_T_1113, _T_1114) @[RVC.scala 219:32] + node _T_1116 = bits(io.in, 1, 1) @[RVC.scala 219:49] + node _T_1117 = eq(_T_1116, UInt<1>("h00")) @[RVC.scala 219:43] + node _T_1118 = and(_T_1115, _T_1117) @[RVC.scala 219:41] + node _T_1119 = or(_T_1108, _T_1118) @[RVC.scala 218:106] + node _T_1120 = bits(io.in, 13, 13) @[RVC.scala 219:63] + node _T_1121 = eq(_T_1120, UInt<1>("h00")) @[RVC.scala 219:57] + node _T_1122 = bits(io.in, 12, 12) @[RVC.scala 219:76] + node _T_1123 = eq(_T_1122, UInt<1>("h00")) @[RVC.scala 219:70] + node _T_1124 = and(_T_1121, _T_1123) @[RVC.scala 219:68] + node _T_1125 = bits(io.in, 3, 3) @[RVC.scala 219:87] + node _T_1126 = and(_T_1124, _T_1125) @[RVC.scala 219:81] + node _T_1127 = bits(io.in, 1, 1) @[RVC.scala 219:96] + node _T_1128 = and(_T_1126, _T_1127) @[RVC.scala 219:90] + node _T_1129 = bits(io.in, 0, 0) @[RVC.scala 219:107] + node _T_1130 = eq(_T_1129, UInt<1>("h00")) @[RVC.scala 219:101] + node _T_1131 = and(_T_1128, _T_1130) @[RVC.scala 219:99] + node _T_1132 = or(_T_1119, _T_1131) @[RVC.scala 219:54] + node _T_1133 = bits(io.in, 13, 13) @[RVC.scala 220:12] + node _T_1134 = bits(io.in, 4, 4) @[RVC.scala 220:22] + node _T_1135 = and(_T_1133, _T_1134) @[RVC.scala 220:16] + node _T_1136 = bits(io.in, 1, 1) @[RVC.scala 220:33] + node _T_1137 = eq(_T_1136, UInt<1>("h00")) @[RVC.scala 220:27] + node _T_1138 = and(_T_1135, _T_1137) @[RVC.scala 220:25] + node _T_1139 = bits(io.in, 0, 0) @[RVC.scala 220:43] + node _T_1140 = and(_T_1138, _T_1139) @[RVC.scala 220:37] + node _T_1141 = or(_T_1132, _T_1140) @[RVC.scala 219:112] + node _T_1142 = bits(io.in, 13, 13) @[RVC.scala 220:56] + node _T_1143 = eq(_T_1142, UInt<1>("h00")) @[RVC.scala 220:50] + node _T_1144 = bits(io.in, 12, 12) @[RVC.scala 220:69] + node _T_1145 = eq(_T_1144, UInt<1>("h00")) @[RVC.scala 220:63] + node _T_1146 = and(_T_1143, _T_1145) @[RVC.scala 220:61] + node _T_1147 = bits(io.in, 2, 2) @[RVC.scala 220:80] + node _T_1148 = and(_T_1146, _T_1147) @[RVC.scala 220:74] + node _T_1149 = bits(io.in, 1, 1) @[RVC.scala 220:89] + node _T_1150 = and(_T_1148, _T_1149) @[RVC.scala 220:83] + node _T_1151 = bits(io.in, 0, 0) @[RVC.scala 220:100] + node _T_1152 = eq(_T_1151, UInt<1>("h00")) @[RVC.scala 220:94] + node _T_1153 = and(_T_1150, _T_1152) @[RVC.scala 220:92] + node _T_1154 = or(_T_1141, _T_1153) @[RVC.scala 220:47] + node _T_1155 = bits(io.in, 15, 15) @[RVC.scala 221:14] + node _T_1156 = eq(_T_1155, UInt<1>("h00")) @[RVC.scala 221:8] + node _T_1157 = bits(io.in, 13, 13) @[RVC.scala 221:27] + node _T_1158 = eq(_T_1157, UInt<1>("h00")) @[RVC.scala 221:21] + node _T_1159 = and(_T_1156, _T_1158) @[RVC.scala 221:19] + node _T_1160 = bits(io.in, 7, 7) @[RVC.scala 221:38] + node _T_1161 = and(_T_1159, _T_1160) @[RVC.scala 221:32] + node _T_1162 = bits(io.in, 1, 1) @[RVC.scala 221:49] + node _T_1163 = eq(_T_1162, UInt<1>("h00")) @[RVC.scala 221:43] + node _T_1164 = and(_T_1161, _T_1163) @[RVC.scala 221:41] + node _T_1165 = or(_T_1154, _T_1164) @[RVC.scala 220:105] + node _T_1166 = bits(io.in, 13, 13) @[RVC.scala 221:61] + node _T_1167 = bits(io.in, 3, 3) @[RVC.scala 221:71] + node _T_1168 = and(_T_1166, _T_1167) @[RVC.scala 221:65] + node _T_1169 = bits(io.in, 1, 1) @[RVC.scala 221:82] + node _T_1170 = eq(_T_1169, UInt<1>("h00")) @[RVC.scala 221:76] + node _T_1171 = and(_T_1168, _T_1170) @[RVC.scala 221:74] + node _T_1172 = bits(io.in, 0, 0) @[RVC.scala 221:92] + node _T_1173 = and(_T_1171, _T_1172) @[RVC.scala 221:86] + node _T_1174 = or(_T_1165, _T_1173) @[RVC.scala 221:54] + node _T_1175 = bits(io.in, 13, 13) @[RVC.scala 222:12] + node _T_1176 = bits(io.in, 2, 2) @[RVC.scala 222:22] + node _T_1177 = and(_T_1175, _T_1176) @[RVC.scala 222:16] + node _T_1178 = bits(io.in, 1, 1) @[RVC.scala 222:33] + node _T_1179 = eq(_T_1178, UInt<1>("h00")) @[RVC.scala 222:27] + node _T_1180 = and(_T_1177, _T_1179) @[RVC.scala 222:25] + node _T_1181 = bits(io.in, 0, 0) @[RVC.scala 222:43] + node _T_1182 = and(_T_1180, _T_1181) @[RVC.scala 222:37] + node _T_1183 = or(_T_1174, _T_1182) @[RVC.scala 221:96] + node _T_1184 = bits(io.in, 14, 14) @[RVC.scala 222:54] + node _T_1185 = bits(io.in, 13, 13) @[RVC.scala 222:66] + node _T_1186 = eq(_T_1185, UInt<1>("h00")) @[RVC.scala 222:60] + node _T_1187 = and(_T_1184, _T_1186) @[RVC.scala 222:58] + node _T_1188 = bits(io.in, 1, 1) @[RVC.scala 222:79] + node _T_1189 = eq(_T_1188, UInt<1>("h00")) @[RVC.scala 222:73] + node _T_1190 = and(_T_1187, _T_1189) @[RVC.scala 222:71] + node _T_1191 = or(_T_1183, _T_1190) @[RVC.scala 222:47] + node _T_1192 = bits(io.in, 14, 14) @[RVC.scala 223:14] + node _T_1193 = eq(_T_1192, UInt<1>("h00")) @[RVC.scala 223:8] + node _T_1194 = bits(io.in, 12, 12) @[RVC.scala 223:27] + node _T_1195 = eq(_T_1194, UInt<1>("h00")) @[RVC.scala 223:21] + node _T_1196 = and(_T_1193, _T_1195) @[RVC.scala 223:19] + node _T_1197 = bits(io.in, 1, 1) @[RVC.scala 223:40] + node _T_1198 = eq(_T_1197, UInt<1>("h00")) @[RVC.scala 223:34] + node _T_1199 = and(_T_1196, _T_1198) @[RVC.scala 223:32] + node _T_1200 = bits(io.in, 0, 0) @[RVC.scala 223:50] + node _T_1201 = and(_T_1199, _T_1200) @[RVC.scala 223:44] + node _T_1202 = or(_T_1191, _T_1201) @[RVC.scala 222:84] + node _T_1203 = bits(io.in, 15, 15) @[RVC.scala 223:61] + node _T_1204 = bits(io.in, 13, 13) @[RVC.scala 223:73] + node _T_1205 = eq(_T_1204, UInt<1>("h00")) @[RVC.scala 223:67] + node _T_1206 = and(_T_1203, _T_1205) @[RVC.scala 223:65] + node _T_1207 = bits(io.in, 12, 12) @[RVC.scala 223:84] + node _T_1208 = and(_T_1206, _T_1207) @[RVC.scala 223:78] + node _T_1209 = bits(io.in, 1, 1) @[RVC.scala 223:94] + node _T_1210 = and(_T_1208, _T_1209) @[RVC.scala 223:88] + node _T_1211 = bits(io.in, 0, 0) @[RVC.scala 223:105] + node _T_1212 = eq(_T_1211, UInt<1>("h00")) @[RVC.scala 223:99] + node _T_1213 = and(_T_1210, _T_1212) @[RVC.scala 223:97] + node _T_1214 = or(_T_1202, _T_1213) @[RVC.scala 223:54] + node _T_1215 = bits(io.in, 15, 15) @[RVC.scala 224:14] + node _T_1216 = eq(_T_1215, UInt<1>("h00")) @[RVC.scala 224:8] + node _T_1217 = bits(io.in, 13, 13) @[RVC.scala 224:27] + node _T_1218 = eq(_T_1217, UInt<1>("h00")) @[RVC.scala 224:21] + node _T_1219 = and(_T_1216, _T_1218) @[RVC.scala 224:19] + node _T_1220 = bits(io.in, 12, 12) @[RVC.scala 224:40] + node _T_1221 = eq(_T_1220, UInt<1>("h00")) @[RVC.scala 224:34] + node _T_1222 = and(_T_1219, _T_1221) @[RVC.scala 224:32] + node _T_1223 = bits(io.in, 1, 1) @[RVC.scala 224:51] + node _T_1224 = and(_T_1222, _T_1223) @[RVC.scala 224:45] + node _T_1225 = bits(io.in, 0, 0) @[RVC.scala 224:62] + node _T_1226 = eq(_T_1225, UInt<1>("h00")) @[RVC.scala 224:56] + node _T_1227 = and(_T_1224, _T_1226) @[RVC.scala 224:54] + node _T_1228 = or(_T_1214, _T_1227) @[RVC.scala 223:110] + node _T_1229 = bits(io.in, 15, 15) @[RVC.scala 224:76] + node _T_1230 = eq(_T_1229, UInt<1>("h00")) @[RVC.scala 224:70] + node _T_1231 = bits(io.in, 13, 13) @[RVC.scala 224:89] + node _T_1232 = eq(_T_1231, UInt<1>("h00")) @[RVC.scala 224:83] + node _T_1233 = and(_T_1230, _T_1232) @[RVC.scala 224:81] + node _T_1234 = bits(io.in, 12, 12) @[RVC.scala 224:100] + node _T_1235 = and(_T_1233, _T_1234) @[RVC.scala 224:94] + node _T_1236 = bits(io.in, 1, 1) @[RVC.scala 224:112] + node _T_1237 = eq(_T_1236, UInt<1>("h00")) @[RVC.scala 224:106] + node _T_1238 = and(_T_1235, _T_1237) @[RVC.scala 224:104] + node _T_1239 = or(_T_1228, _T_1238) @[RVC.scala 224:67] + node _T_1240 = bits(io.in, 14, 14) @[RVC.scala 225:12] + node _T_1241 = bits(io.in, 13, 13) @[RVC.scala 225:24] + node _T_1242 = eq(_T_1241, UInt<1>("h00")) @[RVC.scala 225:18] + node _T_1243 = and(_T_1240, _T_1242) @[RVC.scala 225:16] + node _T_1244 = bits(io.in, 0, 0) @[RVC.scala 225:37] + node _T_1245 = eq(_T_1244, UInt<1>("h00")) @[RVC.scala 225:31] + node _T_1246 = and(_T_1243, _T_1245) @[RVC.scala 225:29] + node _T_1247 = or(_T_1239, _T_1246) @[RVC.scala 224:117] + io.legal <= _T_1247 @[RVC.scala 205:14] + node _T_1248 = mux(io.legal, io.out.bits, UInt<1>("h00")) @[RVC.scala 226:25] + io.waleed_out <= _T_1248 @[RVC.scala 226:19] + diff --git a/test_run_dir/lib.GCDMain166617760/RVCExpander.v b/test_run_dir/lib.GCDMain166617760/RVCExpander.v new file mode 100644 index 00000000..425de7ce --- /dev/null +++ b/test_run_dir/lib.GCDMain166617760/RVCExpander.v @@ -0,0 +1,406 @@ +module RVCExpander( + input clock, + input reset, + input [31:0] io_in, + output [31:0] io_out_bits, + output [4:0] io_out_rd, + output [4:0] io_out_rs1, + output [4:0] io_out_rs2, + output [4:0] io_out_rs3, + output io_rvc, + output io_legal, + output [31:0] io_waleed_out +); + wire _T_3 = |io_in[12:5]; // @[RVC.scala 58:29] + wire [6:0] _T_4 = _T_3 ? 7'h13 : 7'h1f; // @[RVC.scala 58:20] + wire [4:0] _T_14 = {2'h1,io_in[4:2]}; // @[Cat.scala 29:58] + wire [29:0] _T_18 = {io_in[10:7],io_in[12:11],io_in[5],io_in[6],2'h0,5'h2,3'h0,2'h1,io_in[4:2],_T_4}; // @[Cat.scala 29:58] + wire [7:0] _T_28 = {io_in[6:5],io_in[12:10],3'h0}; // @[Cat.scala 29:58] + wire [4:0] _T_30 = {2'h1,io_in[9:7]}; // @[Cat.scala 29:58] + wire [27:0] _T_36 = {io_in[6:5],io_in[12:10],3'h0,2'h1,io_in[9:7],3'h3,2'h1,io_in[4:2],7'h7}; // @[Cat.scala 29:58] + wire [6:0] _T_50 = {io_in[5],io_in[12:10],io_in[6],2'h0}; // @[Cat.scala 29:58] + wire [26:0] _T_58 = {io_in[5],io_in[12:10],io_in[6],2'h0,2'h1,io_in[9:7],3'h2,2'h1,io_in[4:2],7'h3}; // @[Cat.scala 29:58] + wire [26:0] _T_80 = {io_in[5],io_in[12:10],io_in[6],2'h0,2'h1,io_in[9:7],3'h2,2'h1,io_in[4:2],7'h7}; // @[Cat.scala 29:58] + wire [26:0] _T_111 = {_T_50[6:5],2'h1,io_in[4:2],2'h1,io_in[9:7],3'h2,_T_50[4:0],7'h3f}; // @[Cat.scala 29:58] + wire [27:0] _T_138 = {_T_28[7:5],2'h1,io_in[4:2],2'h1,io_in[9:7],3'h3,_T_28[4:0],7'h27}; // @[Cat.scala 29:58] + wire [26:0] _T_169 = {_T_50[6:5],2'h1,io_in[4:2],2'h1,io_in[9:7],3'h2,_T_50[4:0],7'h23}; // @[Cat.scala 29:58] + wire [26:0] _T_200 = {_T_50[6:5],2'h1,io_in[4:2],2'h1,io_in[9:7],3'h2,_T_50[4:0],7'h27}; // @[Cat.scala 29:58] + wire [6:0] _T_211 = io_in[12] ? 7'h7f : 7'h0; // @[Bitwise.scala 72:12] + wire [11:0] _T_213 = {_T_211,io_in[6:2]}; // @[Cat.scala 29:58] + wire [31:0] _T_219 = {_T_211,io_in[6:2],io_in[11:7],3'h0,io_in[11:7],7'h13}; // @[Cat.scala 29:58] + wire [9:0] _T_228 = io_in[12] ? 10'h3ff : 10'h0; // @[Bitwise.scala 72:12] + wire [20:0] _T_243 = {_T_228,io_in[8],io_in[10:9],io_in[6],io_in[7],io_in[2],io_in[11],io_in[5:3],1'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_306 = {_T_243[20],_T_243[10:1],_T_243[11],_T_243[19:12],5'h1,7'h6f}; // @[Cat.scala 29:58] + wire [31:0] _T_321 = {_T_211,io_in[6:2],5'h0,3'h0,io_in[11:7],7'h13}; // @[Cat.scala 29:58] + wire _T_332 = |_T_213; // @[RVC.scala 95:29] + wire [6:0] _T_333 = _T_332 ? 7'h37 : 7'h3f; // @[RVC.scala 95:20] + wire [14:0] _T_336 = io_in[12] ? 15'h7fff : 15'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_339 = {_T_336,io_in[6:2],12'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_343 = {_T_339[31:12],io_in[11:7],_T_333}; // @[Cat.scala 29:58] + wire _T_351 = io_in[11:7] == 5'h0; // @[RVC.scala 97:14] + wire _T_353 = io_in[11:7] == 5'h2; // @[RVC.scala 97:27] + wire _T_354 = _T_351 | _T_353; // @[RVC.scala 97:21] + wire [6:0] _T_361 = _T_332 ? 7'h13 : 7'h1f; // @[RVC.scala 91:20] + wire [2:0] _T_364 = io_in[12] ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_379 = {_T_364,io_in[4:3],io_in[5],io_in[2],io_in[6],4'h0,io_in[11:7],3'h0,io_in[11:7],_T_361}; // @[Cat.scala 29:58] + wire [31:0] _T_386_bits = _T_354 ? _T_379 : _T_343; // @[RVC.scala 97:10] + wire [4:0] _T_386_rd = _T_354 ? io_in[11:7] : io_in[11:7]; // @[RVC.scala 97:10] + wire [4:0] _T_386_rs2 = _T_354 ? _T_14 : _T_14; // @[RVC.scala 97:10] + wire [4:0] _T_386_rs3 = _T_354 ? io_in[31:27] : io_in[31:27]; // @[RVC.scala 97:10] + wire [25:0] _T_397 = {io_in[12],io_in[6:2],2'h1,io_in[9:7],3'h5,2'h1,io_in[9:7],7'h13}; // @[Cat.scala 29:58] + wire [30:0] _GEN_172 = {{5'd0}, _T_397}; // @[RVC.scala 104:23] + wire [30:0] _T_409 = _GEN_172 | 31'h40000000; // @[RVC.scala 104:23] + wire [31:0] _T_422 = {_T_211,io_in[6:2],2'h1,io_in[9:7],3'h7,2'h1,io_in[9:7],7'h13}; // @[Cat.scala 29:58] + wire [2:0] _T_426 = {io_in[12],io_in[6:5]}; // @[Cat.scala 29:58] + wire _T_428 = io_in[6:5] == 2'h0; // @[RVC.scala 108:30] + wire [30:0] _T_429 = _T_428 ? 31'h40000000 : 31'h0; // @[RVC.scala 108:22] + wire [6:0] _T_431 = io_in[12] ? 7'h3b : 7'h33; // @[RVC.scala 109:22] + wire [2:0] _GEN_1 = 3'h1 == _T_426 ? 3'h4 : 3'h0; // @[Cat.scala 29:58] + wire [2:0] _GEN_2 = 3'h2 == _T_426 ? 3'h6 : _GEN_1; // @[Cat.scala 29:58] + wire [2:0] _GEN_3 = 3'h3 == _T_426 ? 3'h7 : _GEN_2; // @[Cat.scala 29:58] + wire [2:0] _GEN_4 = 3'h4 == _T_426 ? 3'h0 : _GEN_3; // @[Cat.scala 29:58] + wire [2:0] _GEN_5 = 3'h5 == _T_426 ? 3'h0 : _GEN_4; // @[Cat.scala 29:58] + wire [2:0] _GEN_6 = 3'h6 == _T_426 ? 3'h2 : _GEN_5; // @[Cat.scala 29:58] + wire [2:0] _GEN_7 = 3'h7 == _T_426 ? 3'h3 : _GEN_6; // @[Cat.scala 29:58] + wire [24:0] _T_441 = {2'h1,io_in[4:2],2'h1,io_in[9:7],_GEN_7,2'h1,io_in[9:7],_T_431}; // @[Cat.scala 29:58] + wire [30:0] _GEN_173 = {{6'd0}, _T_441}; // @[RVC.scala 110:43] + wire [30:0] _T_442 = _GEN_173 | _T_429; // @[RVC.scala 110:43] + wire [31:0] _T_443_0 = {{6'd0}, _T_397}; // @[RVC.scala 112:19 RVC.scala 112:19] + wire [31:0] _T_443_1 = {{1'd0}, _T_409}; // @[RVC.scala 112:19 RVC.scala 112:19] + wire [31:0] _GEN_9 = 2'h1 == io_in[11:10] ? _T_443_1 : _T_443_0; // @[RVC.scala 27:14] + wire [31:0] _GEN_10 = 2'h2 == io_in[11:10] ? _T_422 : _GEN_9; // @[RVC.scala 27:14] + wire [31:0] _T_443_3 = {{1'd0}, _T_442}; // @[RVC.scala 112:19 RVC.scala 112:19] + wire [31:0] _GEN_11 = 2'h3 == io_in[11:10] ? _T_443_3 : _GEN_10; // @[RVC.scala 27:14] + wire [31:0] _T_533 = {_T_243[20],_T_243[10:1],_T_243[11],_T_243[19:12],5'h0,7'h6f}; // @[Cat.scala 29:58] + wire [4:0] _T_542 = io_in[12] ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12] + wire [12:0] _T_551 = {_T_542,io_in[6:5],io_in[2],io_in[11:10],io_in[4:3],1'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_600 = {_T_551[12],_T_551[10:5],5'h0,2'h1,io_in[9:7],3'h0,_T_551[4:1],_T_551[11],7'h63}; // @[Cat.scala 29:58] + wire [31:0] _T_667 = {_T_551[12],_T_551[10:5],5'h0,2'h1,io_in[9:7],3'h1,_T_551[4:1],_T_551[11],7'h63}; // @[Cat.scala 29:58] + wire _T_673 = |io_in[11:7]; // @[RVC.scala 118:27] + wire [6:0] _T_674 = _T_673 ? 7'h3 : 7'h1f; // @[RVC.scala 118:23] + wire [25:0] _T_683 = {io_in[12],io_in[6:2],io_in[11:7],3'h1,io_in[11:7],7'h13}; // @[Cat.scala 29:58] + wire [28:0] _T_699 = {io_in[4:2],io_in[12],io_in[6:5],3'h0,5'h2,3'h3,io_in[11:7],7'h7}; // @[Cat.scala 29:58] + wire [27:0] _T_714 = {io_in[3:2],io_in[12],io_in[6:4],2'h0,5'h2,3'h2,io_in[11:7],_T_674}; // @[Cat.scala 29:58] + wire [27:0] _T_729 = {io_in[3:2],io_in[12],io_in[6:4],2'h0,5'h2,3'h2,io_in[11:7],7'h7}; // @[Cat.scala 29:58] + wire [24:0] _T_739 = {io_in[6:2],5'h0,3'h0,io_in[11:7],7'h33}; // @[Cat.scala 29:58] + wire [24:0] _T_750 = {io_in[6:2],io_in[11:7],3'h0,io_in[11:7],7'h33}; // @[Cat.scala 29:58] + wire [24:0] _T_761 = {io_in[6:2],io_in[11:7],3'h0,12'h67}; // @[Cat.scala 29:58] + wire [24:0] _T_763 = {_T_761[24:7],7'h1f}; // @[Cat.scala 29:58] + wire [24:0] _T_766 = _T_673 ? _T_761 : _T_763; // @[RVC.scala 139:33] + wire _T_772 = |io_in[6:2]; // @[RVC.scala 140:27] + wire [31:0] _T_743_bits = {{7'd0}, _T_739}; // @[RVC.scala 26:19 RVC.scala 27:14] + wire [31:0] _T_770_bits = {{7'd0}, _T_766}; // @[RVC.scala 26:19 RVC.scala 27:14] + wire [31:0] _T_773_bits = _T_772 ? _T_743_bits : _T_770_bits; // @[RVC.scala 140:22] + wire [4:0] _T_773_rd = _T_772 ? io_in[11:7] : 5'h0; // @[RVC.scala 140:22] + wire [4:0] _T_773_rs1 = _T_772 ? 5'h0 : io_in[11:7]; // @[RVC.scala 140:22] + wire [4:0] _T_773_rs2 = _T_772 ? io_in[6:2] : io_in[6:2]; // @[RVC.scala 140:22] + wire [4:0] _T_773_rs3 = _T_772 ? io_in[31:27] : io_in[31:27]; // @[RVC.scala 140:22] + wire [24:0] _T_779 = {io_in[6:2],io_in[11:7],3'h0,12'he7}; // @[Cat.scala 29:58] + wire [24:0] _T_781 = {_T_761[24:7],7'h73}; // @[Cat.scala 29:58] + wire [24:0] _T_782 = _T_781 | 25'h100000; // @[RVC.scala 142:46] + wire [24:0] _T_785 = _T_673 ? _T_779 : _T_782; // @[RVC.scala 143:33] + wire [31:0] _T_755_bits = {{7'd0}, _T_750}; // @[RVC.scala 26:19 RVC.scala 27:14] + wire [31:0] _T_789_bits = {{7'd0}, _T_785}; // @[RVC.scala 26:19 RVC.scala 27:14] + wire [31:0] _T_792_bits = _T_772 ? _T_755_bits : _T_789_bits; // @[RVC.scala 144:25] + wire [4:0] _T_792_rd = _T_772 ? io_in[11:7] : 5'h1; // @[RVC.scala 144:25] + wire [4:0] _T_792_rs1 = _T_772 ? io_in[11:7] : io_in[11:7]; // @[RVC.scala 144:25] + wire [31:0] _T_794_bits = io_in[12] ? _T_792_bits : _T_773_bits; // @[RVC.scala 145:10] + wire [4:0] _T_794_rd = io_in[12] ? _T_792_rd : _T_773_rd; // @[RVC.scala 145:10] + wire [4:0] _T_794_rs1 = io_in[12] ? _T_792_rs1 : _T_773_rs1; // @[RVC.scala 145:10] + wire [4:0] _T_794_rs2 = io_in[12] ? _T_773_rs2 : _T_773_rs2; // @[RVC.scala 145:10] + wire [4:0] _T_794_rs3 = io_in[12] ? _T_773_rs3 : _T_773_rs3; // @[RVC.scala 145:10] + wire [8:0] _T_798 = {io_in[9:7],io_in[12:10],3'h0}; // @[Cat.scala 29:58] + wire [28:0] _T_810 = {_T_798[8:5],io_in[6:2],5'h2,3'h3,_T_798[4:0],7'h27}; // @[Cat.scala 29:58] + wire [7:0] _T_818 = {io_in[8:7],io_in[12:9],2'h0}; // @[Cat.scala 29:58] + wire [27:0] _T_830 = {_T_818[7:5],io_in[6:2],5'h2,3'h2,_T_818[4:0],7'h23}; // @[Cat.scala 29:58] + wire [27:0] _T_850 = {_T_818[7:5],io_in[6:2],5'h2,3'h2,_T_818[4:0],7'h27}; // @[Cat.scala 29:58] + wire [4:0] _T_898 = {io_in[1:0],io_in[15:13]}; // @[Cat.scala 29:58] + wire [31:0] _T_24_bits = {{2'd0}, _T_18}; // @[RVC.scala 26:19 RVC.scala 27:14] + wire [31:0] _T_44_bits = {{4'd0}, _T_36}; // @[RVC.scala 26:19 RVC.scala 27:14] + wire [31:0] _GEN_17 = 5'h1 == _T_898 ? _T_44_bits : _T_24_bits; // @[RVC.scala 204:12] + wire [4:0] _GEN_18 = 5'h1 == _T_898 ? _T_14 : _T_14; // @[RVC.scala 204:12] + wire [4:0] _GEN_19 = 5'h1 == _T_898 ? _T_30 : 5'h2; // @[RVC.scala 204:12] + wire [4:0] _GEN_21 = 5'h1 == _T_898 ? io_in[31:27] : io_in[31:27]; // @[RVC.scala 204:12] + wire [31:0] _T_66_bits = {{5'd0}, _T_58}; // @[RVC.scala 26:19 RVC.scala 27:14] + wire [31:0] _GEN_22 = 5'h2 == _T_898 ? _T_66_bits : _GEN_17; // @[RVC.scala 204:12] + wire [4:0] _GEN_23 = 5'h2 == _T_898 ? _T_14 : _GEN_18; // @[RVC.scala 204:12] + wire [4:0] _GEN_24 = 5'h2 == _T_898 ? _T_30 : _GEN_19; // @[RVC.scala 204:12] + wire [4:0] _GEN_26 = 5'h2 == _T_898 ? io_in[31:27] : _GEN_21; // @[RVC.scala 204:12] + wire [31:0] _T_88_bits = {{5'd0}, _T_80}; // @[RVC.scala 26:19 RVC.scala 27:14] + wire [31:0] _GEN_27 = 5'h3 == _T_898 ? _T_88_bits : _GEN_22; // @[RVC.scala 204:12] + wire [4:0] _GEN_28 = 5'h3 == _T_898 ? _T_14 : _GEN_23; // @[RVC.scala 204:12] + wire [4:0] _GEN_29 = 5'h3 == _T_898 ? _T_30 : _GEN_24; // @[RVC.scala 204:12] + wire [4:0] _GEN_31 = 5'h3 == _T_898 ? io_in[31:27] : _GEN_26; // @[RVC.scala 204:12] + wire [31:0] _T_119_bits = {{5'd0}, _T_111}; // @[RVC.scala 26:19 RVC.scala 27:14] + wire [31:0] _GEN_32 = 5'h4 == _T_898 ? _T_119_bits : _GEN_27; // @[RVC.scala 204:12] + wire [4:0] _GEN_33 = 5'h4 == _T_898 ? _T_14 : _GEN_28; // @[RVC.scala 204:12] + wire [4:0] _GEN_34 = 5'h4 == _T_898 ? _T_30 : _GEN_29; // @[RVC.scala 204:12] + wire [4:0] _GEN_36 = 5'h4 == _T_898 ? io_in[31:27] : _GEN_31; // @[RVC.scala 204:12] + wire [31:0] _T_146_bits = {{4'd0}, _T_138}; // @[RVC.scala 26:19 RVC.scala 27:14] + wire [31:0] _GEN_37 = 5'h5 == _T_898 ? _T_146_bits : _GEN_32; // @[RVC.scala 204:12] + wire [4:0] _GEN_38 = 5'h5 == _T_898 ? _T_14 : _GEN_33; // @[RVC.scala 204:12] + wire [4:0] _GEN_39 = 5'h5 == _T_898 ? _T_30 : _GEN_34; // @[RVC.scala 204:12] + wire [4:0] _GEN_41 = 5'h5 == _T_898 ? io_in[31:27] : _GEN_36; // @[RVC.scala 204:12] + wire [31:0] _T_177_bits = {{5'd0}, _T_169}; // @[RVC.scala 26:19 RVC.scala 27:14] + wire [31:0] _GEN_42 = 5'h6 == _T_898 ? _T_177_bits : _GEN_37; // @[RVC.scala 204:12] + wire [4:0] _GEN_43 = 5'h6 == _T_898 ? _T_14 : _GEN_38; // @[RVC.scala 204:12] + wire [4:0] _GEN_44 = 5'h6 == _T_898 ? _T_30 : _GEN_39; // @[RVC.scala 204:12] + wire [4:0] _GEN_46 = 5'h6 == _T_898 ? io_in[31:27] : _GEN_41; // @[RVC.scala 204:12] + wire [31:0] _T_208_bits = {{5'd0}, _T_200}; // @[RVC.scala 26:19 RVC.scala 27:14] + wire [31:0] _GEN_47 = 5'h7 == _T_898 ? _T_208_bits : _GEN_42; // @[RVC.scala 204:12] + wire [4:0] _GEN_48 = 5'h7 == _T_898 ? _T_14 : _GEN_43; // @[RVC.scala 204:12] + wire [4:0] _GEN_49 = 5'h7 == _T_898 ? _T_30 : _GEN_44; // @[RVC.scala 204:12] + wire [4:0] _GEN_51 = 5'h7 == _T_898 ? io_in[31:27] : _GEN_46; // @[RVC.scala 204:12] + wire [31:0] _GEN_52 = 5'h8 == _T_898 ? _T_219 : _GEN_47; // @[RVC.scala 204:12] + wire [4:0] _GEN_53 = 5'h8 == _T_898 ? io_in[11:7] : _GEN_48; // @[RVC.scala 204:12] + wire [4:0] _GEN_54 = 5'h8 == _T_898 ? io_in[11:7] : _GEN_49; // @[RVC.scala 204:12] + wire [4:0] _GEN_55 = 5'h8 == _T_898 ? _T_14 : _GEN_48; // @[RVC.scala 204:12] + wire [4:0] _GEN_56 = 5'h8 == _T_898 ? io_in[31:27] : _GEN_51; // @[RVC.scala 204:12] + wire [31:0] _GEN_57 = 5'h9 == _T_898 ? _T_306 : _GEN_52; // @[RVC.scala 204:12] + wire [4:0] _GEN_58 = 5'h9 == _T_898 ? 5'h1 : _GEN_53; // @[RVC.scala 204:12] + wire [4:0] _GEN_59 = 5'h9 == _T_898 ? io_in[11:7] : _GEN_54; // @[RVC.scala 204:12] + wire [4:0] _GEN_60 = 5'h9 == _T_898 ? _T_14 : _GEN_55; // @[RVC.scala 204:12] + wire [4:0] _GEN_61 = 5'h9 == _T_898 ? io_in[31:27] : _GEN_56; // @[RVC.scala 204:12] + wire [31:0] _GEN_62 = 5'ha == _T_898 ? _T_321 : _GEN_57; // @[RVC.scala 204:12] + wire [4:0] _GEN_63 = 5'ha == _T_898 ? io_in[11:7] : _GEN_58; // @[RVC.scala 204:12] + wire [4:0] _GEN_64 = 5'ha == _T_898 ? 5'h0 : _GEN_59; // @[RVC.scala 204:12] + wire [4:0] _GEN_65 = 5'ha == _T_898 ? _T_14 : _GEN_60; // @[RVC.scala 204:12] + wire [4:0] _GEN_66 = 5'ha == _T_898 ? io_in[31:27] : _GEN_61; // @[RVC.scala 204:12] + wire [31:0] _GEN_67 = 5'hb == _T_898 ? _T_386_bits : _GEN_62; // @[RVC.scala 204:12] + wire [4:0] _GEN_68 = 5'hb == _T_898 ? _T_386_rd : _GEN_63; // @[RVC.scala 204:12] + wire [4:0] _GEN_69 = 5'hb == _T_898 ? _T_386_rd : _GEN_64; // @[RVC.scala 204:12] + wire [4:0] _GEN_70 = 5'hb == _T_898 ? _T_386_rs2 : _GEN_65; // @[RVC.scala 204:12] + wire [4:0] _GEN_71 = 5'hb == _T_898 ? _T_386_rs3 : _GEN_66; // @[RVC.scala 204:12] + wire [31:0] _GEN_72 = 5'hc == _T_898 ? _GEN_11 : _GEN_67; // @[RVC.scala 204:12] + wire [4:0] _GEN_73 = 5'hc == _T_898 ? _T_30 : _GEN_68; // @[RVC.scala 204:12] + wire [4:0] _GEN_74 = 5'hc == _T_898 ? _T_30 : _GEN_69; // @[RVC.scala 204:12] + wire [4:0] _GEN_75 = 5'hc == _T_898 ? _T_14 : _GEN_70; // @[RVC.scala 204:12] + wire [4:0] _GEN_76 = 5'hc == _T_898 ? io_in[31:27] : _GEN_71; // @[RVC.scala 204:12] + wire [31:0] _GEN_77 = 5'hd == _T_898 ? _T_533 : _GEN_72; // @[RVC.scala 204:12] + wire [4:0] _GEN_78 = 5'hd == _T_898 ? 5'h0 : _GEN_73; // @[RVC.scala 204:12] + wire [4:0] _GEN_79 = 5'hd == _T_898 ? _T_30 : _GEN_74; // @[RVC.scala 204:12] + wire [4:0] _GEN_80 = 5'hd == _T_898 ? _T_14 : _GEN_75; // @[RVC.scala 204:12] + wire [4:0] _GEN_81 = 5'hd == _T_898 ? io_in[31:27] : _GEN_76; // @[RVC.scala 204:12] + wire [31:0] _GEN_82 = 5'he == _T_898 ? _T_600 : _GEN_77; // @[RVC.scala 204:12] + wire [4:0] _GEN_83 = 5'he == _T_898 ? _T_30 : _GEN_78; // @[RVC.scala 204:12] + wire [4:0] _GEN_84 = 5'he == _T_898 ? _T_30 : _GEN_79; // @[RVC.scala 204:12] + wire [4:0] _GEN_85 = 5'he == _T_898 ? 5'h0 : _GEN_80; // @[RVC.scala 204:12] + wire [4:0] _GEN_86 = 5'he == _T_898 ? io_in[31:27] : _GEN_81; // @[RVC.scala 204:12] + wire [31:0] _GEN_87 = 5'hf == _T_898 ? _T_667 : _GEN_82; // @[RVC.scala 204:12] + wire [4:0] _GEN_88 = 5'hf == _T_898 ? 5'h0 : _GEN_83; // @[RVC.scala 204:12] + wire [4:0] _GEN_89 = 5'hf == _T_898 ? _T_30 : _GEN_84; // @[RVC.scala 204:12] + wire [4:0] _GEN_90 = 5'hf == _T_898 ? 5'h0 : _GEN_85; // @[RVC.scala 204:12] + wire [4:0] _GEN_91 = 5'hf == _T_898 ? io_in[31:27] : _GEN_86; // @[RVC.scala 204:12] + wire [31:0] _T_688_bits = {{6'd0}, _T_683}; // @[RVC.scala 26:19 RVC.scala 27:14] + wire [31:0] _GEN_92 = 5'h10 == _T_898 ? _T_688_bits : _GEN_87; // @[RVC.scala 204:12] + wire [4:0] _GEN_93 = 5'h10 == _T_898 ? io_in[11:7] : _GEN_88; // @[RVC.scala 204:12] + wire [4:0] _GEN_94 = 5'h10 == _T_898 ? io_in[11:7] : _GEN_89; // @[RVC.scala 204:12] + wire [4:0] _GEN_95 = 5'h10 == _T_898 ? io_in[6:2] : _GEN_90; // @[RVC.scala 204:12] + wire [4:0] _GEN_96 = 5'h10 == _T_898 ? io_in[31:27] : _GEN_91; // @[RVC.scala 204:12] + wire [31:0] _T_703_bits = {{3'd0}, _T_699}; // @[RVC.scala 26:19 RVC.scala 27:14] + wire [31:0] _GEN_97 = 5'h11 == _T_898 ? _T_703_bits : _GEN_92; // @[RVC.scala 204:12] + wire [4:0] _GEN_98 = 5'h11 == _T_898 ? io_in[11:7] : _GEN_93; // @[RVC.scala 204:12] + wire [4:0] _GEN_99 = 5'h11 == _T_898 ? 5'h2 : _GEN_94; // @[RVC.scala 204:12] + wire [4:0] _GEN_100 = 5'h11 == _T_898 ? io_in[6:2] : _GEN_95; // @[RVC.scala 204:12] + wire [4:0] _GEN_101 = 5'h11 == _T_898 ? io_in[31:27] : _GEN_96; // @[RVC.scala 204:12] + wire [31:0] _T_718_bits = {{4'd0}, _T_714}; // @[RVC.scala 26:19 RVC.scala 27:14] + wire [31:0] _GEN_102 = 5'h12 == _T_898 ? _T_718_bits : _GEN_97; // @[RVC.scala 204:12] + wire [4:0] _GEN_103 = 5'h12 == _T_898 ? io_in[11:7] : _GEN_98; // @[RVC.scala 204:12] + wire [4:0] _GEN_104 = 5'h12 == _T_898 ? 5'h2 : _GEN_99; // @[RVC.scala 204:12] + wire [4:0] _GEN_105 = 5'h12 == _T_898 ? io_in[6:2] : _GEN_100; // @[RVC.scala 204:12] + wire [4:0] _GEN_106 = 5'h12 == _T_898 ? io_in[31:27] : _GEN_101; // @[RVC.scala 204:12] + wire [31:0] _T_733_bits = {{4'd0}, _T_729}; // @[RVC.scala 26:19 RVC.scala 27:14] + wire [31:0] _GEN_107 = 5'h13 == _T_898 ? _T_733_bits : _GEN_102; // @[RVC.scala 204:12] + wire [4:0] _GEN_108 = 5'h13 == _T_898 ? io_in[11:7] : _GEN_103; // @[RVC.scala 204:12] + wire [4:0] _GEN_109 = 5'h13 == _T_898 ? 5'h2 : _GEN_104; // @[RVC.scala 204:12] + wire [4:0] _GEN_110 = 5'h13 == _T_898 ? io_in[6:2] : _GEN_105; // @[RVC.scala 204:12] + wire [4:0] _GEN_111 = 5'h13 == _T_898 ? io_in[31:27] : _GEN_106; // @[RVC.scala 204:12] + wire [31:0] _GEN_112 = 5'h14 == _T_898 ? _T_794_bits : _GEN_107; // @[RVC.scala 204:12] + wire [4:0] _GEN_113 = 5'h14 == _T_898 ? _T_794_rd : _GEN_108; // @[RVC.scala 204:12] + wire [4:0] _GEN_114 = 5'h14 == _T_898 ? _T_794_rs1 : _GEN_109; // @[RVC.scala 204:12] + wire [4:0] _GEN_115 = 5'h14 == _T_898 ? _T_794_rs2 : _GEN_110; // @[RVC.scala 204:12] + wire [4:0] _GEN_116 = 5'h14 == _T_898 ? _T_794_rs3 : _GEN_111; // @[RVC.scala 204:12] + wire [31:0] _T_814_bits = {{3'd0}, _T_810}; // @[RVC.scala 26:19 RVC.scala 27:14] + wire [31:0] _GEN_117 = 5'h15 == _T_898 ? _T_814_bits : _GEN_112; // @[RVC.scala 204:12] + wire [4:0] _GEN_118 = 5'h15 == _T_898 ? io_in[11:7] : _GEN_113; // @[RVC.scala 204:12] + wire [4:0] _GEN_119 = 5'h15 == _T_898 ? 5'h2 : _GEN_114; // @[RVC.scala 204:12] + wire [4:0] _GEN_120 = 5'h15 == _T_898 ? io_in[6:2] : _GEN_115; // @[RVC.scala 204:12] + wire [4:0] _GEN_121 = 5'h15 == _T_898 ? io_in[31:27] : _GEN_116; // @[RVC.scala 204:12] + wire [31:0] _T_834_bits = {{4'd0}, _T_830}; // @[RVC.scala 26:19 RVC.scala 27:14] + wire [31:0] _GEN_122 = 5'h16 == _T_898 ? _T_834_bits : _GEN_117; // @[RVC.scala 204:12] + wire [4:0] _GEN_123 = 5'h16 == _T_898 ? io_in[11:7] : _GEN_118; // @[RVC.scala 204:12] + wire [4:0] _GEN_124 = 5'h16 == _T_898 ? 5'h2 : _GEN_119; // @[RVC.scala 204:12] + wire [4:0] _GEN_125 = 5'h16 == _T_898 ? io_in[6:2] : _GEN_120; // @[RVC.scala 204:12] + wire [4:0] _GEN_126 = 5'h16 == _T_898 ? io_in[31:27] : _GEN_121; // @[RVC.scala 204:12] + wire [31:0] _T_854_bits = {{4'd0}, _T_850}; // @[RVC.scala 26:19 RVC.scala 27:14] + wire [31:0] _GEN_127 = 5'h17 == _T_898 ? _T_854_bits : _GEN_122; // @[RVC.scala 204:12] + wire [4:0] _GEN_128 = 5'h17 == _T_898 ? io_in[11:7] : _GEN_123; // @[RVC.scala 204:12] + wire [4:0] _GEN_129 = 5'h17 == _T_898 ? 5'h2 : _GEN_124; // @[RVC.scala 204:12] + wire [4:0] _GEN_130 = 5'h17 == _T_898 ? io_in[6:2] : _GEN_125; // @[RVC.scala 204:12] + wire [4:0] _GEN_131 = 5'h17 == _T_898 ? io_in[31:27] : _GEN_126; // @[RVC.scala 204:12] + wire [31:0] _GEN_132 = 5'h18 == _T_898 ? io_in : _GEN_127; // @[RVC.scala 204:12] + wire [4:0] _GEN_133 = 5'h18 == _T_898 ? io_in[11:7] : _GEN_128; // @[RVC.scala 204:12] + wire [4:0] _GEN_134 = 5'h18 == _T_898 ? io_in[19:15] : _GEN_129; // @[RVC.scala 204:12] + wire [4:0] _GEN_135 = 5'h18 == _T_898 ? io_in[24:20] : _GEN_130; // @[RVC.scala 204:12] + wire [4:0] _GEN_136 = 5'h18 == _T_898 ? io_in[31:27] : _GEN_131; // @[RVC.scala 204:12] + wire [31:0] _GEN_137 = 5'h19 == _T_898 ? io_in : _GEN_132; // @[RVC.scala 204:12] + wire [4:0] _GEN_138 = 5'h19 == _T_898 ? io_in[11:7] : _GEN_133; // @[RVC.scala 204:12] + wire [4:0] _GEN_139 = 5'h19 == _T_898 ? io_in[19:15] : _GEN_134; // @[RVC.scala 204:12] + wire [4:0] _GEN_140 = 5'h19 == _T_898 ? io_in[24:20] : _GEN_135; // @[RVC.scala 204:12] + wire [4:0] _GEN_141 = 5'h19 == _T_898 ? io_in[31:27] : _GEN_136; // @[RVC.scala 204:12] + wire [31:0] _GEN_142 = 5'h1a == _T_898 ? io_in : _GEN_137; // @[RVC.scala 204:12] + wire [4:0] _GEN_143 = 5'h1a == _T_898 ? io_in[11:7] : _GEN_138; // @[RVC.scala 204:12] + wire [4:0] _GEN_144 = 5'h1a == _T_898 ? io_in[19:15] : _GEN_139; // @[RVC.scala 204:12] + wire [4:0] _GEN_145 = 5'h1a == _T_898 ? io_in[24:20] : _GEN_140; // @[RVC.scala 204:12] + wire [4:0] _GEN_146 = 5'h1a == _T_898 ? io_in[31:27] : _GEN_141; // @[RVC.scala 204:12] + wire [31:0] _GEN_147 = 5'h1b == _T_898 ? io_in : _GEN_142; // @[RVC.scala 204:12] + wire [4:0] _GEN_148 = 5'h1b == _T_898 ? io_in[11:7] : _GEN_143; // @[RVC.scala 204:12] + wire [4:0] _GEN_149 = 5'h1b == _T_898 ? io_in[19:15] : _GEN_144; // @[RVC.scala 204:12] + wire [4:0] _GEN_150 = 5'h1b == _T_898 ? io_in[24:20] : _GEN_145; // @[RVC.scala 204:12] + wire [4:0] _GEN_151 = 5'h1b == _T_898 ? io_in[31:27] : _GEN_146; // @[RVC.scala 204:12] + wire [31:0] _GEN_152 = 5'h1c == _T_898 ? io_in : _GEN_147; // @[RVC.scala 204:12] + wire [4:0] _GEN_153 = 5'h1c == _T_898 ? io_in[11:7] : _GEN_148; // @[RVC.scala 204:12] + wire [4:0] _GEN_154 = 5'h1c == _T_898 ? io_in[19:15] : _GEN_149; // @[RVC.scala 204:12] + wire [4:0] _GEN_155 = 5'h1c == _T_898 ? io_in[24:20] : _GEN_150; // @[RVC.scala 204:12] + wire [4:0] _GEN_156 = 5'h1c == _T_898 ? io_in[31:27] : _GEN_151; // @[RVC.scala 204:12] + wire [31:0] _GEN_157 = 5'h1d == _T_898 ? io_in : _GEN_152; // @[RVC.scala 204:12] + wire [4:0] _GEN_158 = 5'h1d == _T_898 ? io_in[11:7] : _GEN_153; // @[RVC.scala 204:12] + wire [4:0] _GEN_159 = 5'h1d == _T_898 ? io_in[19:15] : _GEN_154; // @[RVC.scala 204:12] + wire [4:0] _GEN_160 = 5'h1d == _T_898 ? io_in[24:20] : _GEN_155; // @[RVC.scala 204:12] + wire [4:0] _GEN_161 = 5'h1d == _T_898 ? io_in[31:27] : _GEN_156; // @[RVC.scala 204:12] + wire [31:0] _GEN_162 = 5'h1e == _T_898 ? io_in : _GEN_157; // @[RVC.scala 204:12] + wire [4:0] _GEN_163 = 5'h1e == _T_898 ? io_in[11:7] : _GEN_158; // @[RVC.scala 204:12] + wire [4:0] _GEN_164 = 5'h1e == _T_898 ? io_in[19:15] : _GEN_159; // @[RVC.scala 204:12] + wire [4:0] _GEN_165 = 5'h1e == _T_898 ? io_in[24:20] : _GEN_160; // @[RVC.scala 204:12] + wire [4:0] _GEN_166 = 5'h1e == _T_898 ? io_in[31:27] : _GEN_161; // @[RVC.scala 204:12] + wire _T_900 = ~io_in[13]; // @[RVC.scala 205:18] + wire _T_902 = ~io_in[12]; // @[RVC.scala 205:31] + wire _T_903 = _T_900 & _T_902; // @[RVC.scala 205:29] + wire _T_905 = _T_903 & io_in[11]; // @[RVC.scala 205:42] + wire _T_907 = _T_905 & io_in[1]; // @[RVC.scala 205:54] + wire _T_909 = ~io_in[0]; // @[RVC.scala 205:65] + wire _T_910 = _T_907 & _T_909; // @[RVC.scala 205:63] + wire _T_917 = _T_903 & io_in[6]; // @[RVC.scala 206:32] + wire _T_919 = _T_917 & io_in[1]; // @[RVC.scala 206:43] + wire _T_922 = _T_919 & _T_909; // @[RVC.scala 206:52] + wire _T_923 = _T_910 | _T_922; // @[RVC.scala 205:76] + wire _T_925 = ~io_in[15]; // @[RVC.scala 207:8] + wire _T_928 = _T_925 & _T_900; // @[RVC.scala 207:19] + wire _T_931 = ~io_in[1]; // @[RVC.scala 207:43] + wire _T_932 = io_in[11] >> _T_931; // @[RVC.scala 207:42] + wire _T_934 = _T_928 & _T_932; // @[RVC.scala 207:32] + wire _T_935 = _T_923 | _T_934; // @[RVC.scala 206:65] + wire _T_942 = _T_903 & io_in[5]; // @[RVC.scala 208:32] + wire _T_944 = _T_942 & io_in[1]; // @[RVC.scala 208:41] + wire _T_947 = _T_944 & _T_909; // @[RVC.scala 208:50] + wire _T_948 = _T_935 | _T_947; // @[RVC.scala 207:54] + wire _T_955 = _T_903 & io_in[10]; // @[RVC.scala 209:32] + wire _T_958 = _T_955 & _T_931; // @[RVC.scala 209:42] + wire _T_960 = _T_958 & io_in[0]; // @[RVC.scala 209:54] + wire _T_961 = _T_948 | _T_960; // @[RVC.scala 208:63] + wire _T_968 = _T_928 & io_in[6]; // @[RVC.scala 210:32] + wire _T_971 = _T_968 & _T_931; // @[RVC.scala 210:41] + wire _T_972 = _T_961 | _T_971; // @[RVC.scala 209:64] + wire _T_976 = io_in[15] & _T_902; // @[RVC.scala 210:65] + wire _T_979 = _T_976 & _T_931; // @[RVC.scala 210:78] + wire _T_981 = _T_979 & io_in[0]; // @[RVC.scala 210:90] + wire _T_982 = _T_972 | _T_981; // @[RVC.scala 210:54] + wire _T_989 = _T_903 & io_in[9]; // @[RVC.scala 211:32] + wire _T_991 = _T_989 & io_in[1]; // @[RVC.scala 211:41] + wire _T_994 = _T_991 & _T_909; // @[RVC.scala 211:50] + wire _T_995 = _T_982 | _T_994; // @[RVC.scala 210:100] + wire _T_999 = _T_902 & io_in[6]; // @[RVC.scala 212:19] + wire _T_1002 = _T_999 & _T_931; // @[RVC.scala 212:28] + wire _T_1004 = _T_1002 & io_in[0]; // @[RVC.scala 212:40] + wire _T_1005 = _T_995 | _T_1004; // @[RVC.scala 211:63] + wire _T_1012 = _T_928 & io_in[5]; // @[RVC.scala 213:32] + wire _T_1015 = _T_1012 & _T_931; // @[RVC.scala 213:41] + wire _T_1016 = _T_1005 | _T_1015; // @[RVC.scala 212:50] + wire _T_1023 = _T_903 & io_in[8]; // @[RVC.scala 214:32] + wire _T_1025 = _T_1023 & io_in[1]; // @[RVC.scala 214:41] + wire _T_1028 = _T_1025 & _T_909; // @[RVC.scala 214:50] + wire _T_1029 = _T_1016 | _T_1028; // @[RVC.scala 213:54] + wire _T_1033 = _T_902 & io_in[5]; // @[RVC.scala 215:19] + wire _T_1036 = _T_1033 & _T_931; // @[RVC.scala 215:28] + wire _T_1038 = _T_1036 & io_in[0]; // @[RVC.scala 215:40] + wire _T_1039 = _T_1029 | _T_1038; // @[RVC.scala 214:63] + wire _T_1046 = _T_928 & io_in[10]; // @[RVC.scala 216:32] + wire _T_1049 = _T_1046 & _T_931; // @[RVC.scala 216:42] + wire _T_1050 = _T_1039 | _T_1049; // @[RVC.scala 215:50] + wire _T_1057 = _T_903 & io_in[7]; // @[RVC.scala 216:82] + wire _T_1059 = _T_1057 & io_in[1]; // @[RVC.scala 216:91] + wire _T_1062 = _T_1059 & _T_909; // @[RVC.scala 216:100] + wire _T_1063 = _T_1050 | _T_1062; // @[RVC.scala 216:55] + wire _T_1066 = io_in[12] & io_in[11]; // @[RVC.scala 217:16] + wire _T_1068 = ~io_in[10]; // @[RVC.scala 217:28] + wire _T_1069 = _T_1066 & _T_1068; // @[RVC.scala 217:26] + wire _T_1072 = _T_1069 & _T_931; // @[RVC.scala 217:39] + wire _T_1074 = _T_1072 & io_in[0]; // @[RVC.scala 217:51] + wire _T_1075 = _T_1063 | _T_1074; // @[RVC.scala 216:113] + wire _T_1082 = _T_928 & io_in[9]; // @[RVC.scala 217:88] + wire _T_1085 = _T_1082 & _T_931; // @[RVC.scala 217:97] + wire _T_1086 = _T_1075 | _T_1085; // @[RVC.scala 217:61] + wire _T_1093 = _T_903 & io_in[4]; // @[RVC.scala 218:32] + wire _T_1095 = _T_1093 & io_in[1]; // @[RVC.scala 218:41] + wire _T_1098 = _T_1095 & _T_909; // @[RVC.scala 218:50] + wire _T_1099 = _T_1086 | _T_1098; // @[RVC.scala 217:110] + wire _T_1102 = io_in[13] & io_in[12]; // @[RVC.scala 218:74] + wire _T_1105 = _T_1102 & _T_931; // @[RVC.scala 218:84] + wire _T_1107 = _T_1105 & io_in[0]; // @[RVC.scala 218:96] + wire _T_1108 = _T_1099 | _T_1107; // @[RVC.scala 218:63] + wire _T_1115 = _T_928 & io_in[8]; // @[RVC.scala 219:32] + wire _T_1118 = _T_1115 & _T_931; // @[RVC.scala 219:41] + wire _T_1119 = _T_1108 | _T_1118; // @[RVC.scala 218:106] + wire _T_1126 = _T_903 & io_in[3]; // @[RVC.scala 219:81] + wire _T_1128 = _T_1126 & io_in[1]; // @[RVC.scala 219:90] + wire _T_1131 = _T_1128 & _T_909; // @[RVC.scala 219:99] + wire _T_1132 = _T_1119 | _T_1131; // @[RVC.scala 219:54] + wire _T_1135 = io_in[13] & io_in[4]; // @[RVC.scala 220:16] + wire _T_1138 = _T_1135 & _T_931; // @[RVC.scala 220:25] + wire _T_1140 = _T_1138 & io_in[0]; // @[RVC.scala 220:37] + wire _T_1141 = _T_1132 | _T_1140; // @[RVC.scala 219:112] + wire _T_1148 = _T_903 & io_in[2]; // @[RVC.scala 220:74] + wire _T_1150 = _T_1148 & io_in[1]; // @[RVC.scala 220:83] + wire _T_1153 = _T_1150 & _T_909; // @[RVC.scala 220:92] + wire _T_1154 = _T_1141 | _T_1153; // @[RVC.scala 220:47] + wire _T_1161 = _T_928 & io_in[7]; // @[RVC.scala 221:32] + wire _T_1164 = _T_1161 & _T_931; // @[RVC.scala 221:41] + wire _T_1165 = _T_1154 | _T_1164; // @[RVC.scala 220:105] + wire _T_1168 = io_in[13] & io_in[3]; // @[RVC.scala 221:65] + wire _T_1171 = _T_1168 & _T_931; // @[RVC.scala 221:74] + wire _T_1173 = _T_1171 & io_in[0]; // @[RVC.scala 221:86] + wire _T_1174 = _T_1165 | _T_1173; // @[RVC.scala 221:54] + wire _T_1177 = io_in[13] & io_in[2]; // @[RVC.scala 222:16] + wire _T_1180 = _T_1177 & _T_931; // @[RVC.scala 222:25] + wire _T_1182 = _T_1180 & io_in[0]; // @[RVC.scala 222:37] + wire _T_1183 = _T_1174 | _T_1182; // @[RVC.scala 221:96] + wire _T_1187 = io_in[14] & _T_900; // @[RVC.scala 222:58] + wire _T_1190 = _T_1187 & _T_931; // @[RVC.scala 222:71] + wire _T_1191 = _T_1183 | _T_1190; // @[RVC.scala 222:47] + wire _T_1193 = ~io_in[14]; // @[RVC.scala 223:8] + wire _T_1196 = _T_1193 & _T_902; // @[RVC.scala 223:19] + wire _T_1199 = _T_1196 & _T_931; // @[RVC.scala 223:32] + wire _T_1201 = _T_1199 & io_in[0]; // @[RVC.scala 223:44] + wire _T_1202 = _T_1191 | _T_1201; // @[RVC.scala 222:84] + wire _T_1206 = io_in[15] & _T_900; // @[RVC.scala 223:65] + wire _T_1208 = _T_1206 & io_in[12]; // @[RVC.scala 223:78] + wire _T_1210 = _T_1208 & io_in[1]; // @[RVC.scala 223:88] + wire _T_1213 = _T_1210 & _T_909; // @[RVC.scala 223:97] + wire _T_1214 = _T_1202 | _T_1213; // @[RVC.scala 223:54] + wire _T_1222 = _T_928 & _T_902; // @[RVC.scala 224:32] + wire _T_1224 = _T_1222 & io_in[1]; // @[RVC.scala 224:45] + wire _T_1227 = _T_1224 & _T_909; // @[RVC.scala 224:54] + wire _T_1228 = _T_1214 | _T_1227; // @[RVC.scala 223:110] + wire _T_1235 = _T_928 & io_in[12]; // @[RVC.scala 224:94] + wire _T_1238 = _T_1235 & _T_931; // @[RVC.scala 224:104] + wire _T_1239 = _T_1228 | _T_1238; // @[RVC.scala 224:67] + wire _T_1246 = _T_1187 & _T_909; // @[RVC.scala 225:29] + assign io_out_bits = 5'h1f == _T_898 ? io_in : _GEN_162; // @[RVC.scala 204:12] + assign io_out_rd = 5'h1f == _T_898 ? io_in[11:7] : _GEN_163; // @[RVC.scala 204:12] + assign io_out_rs1 = 5'h1f == _T_898 ? io_in[19:15] : _GEN_164; // @[RVC.scala 204:12] + assign io_out_rs2 = 5'h1f == _T_898 ? io_in[24:20] : _GEN_165; // @[RVC.scala 204:12] + assign io_out_rs3 = 5'h1f == _T_898 ? io_in[31:27] : _GEN_166; // @[RVC.scala 204:12] + assign io_rvc = io_in[1:0] != 2'h3; // @[RVC.scala 202:12] + assign io_legal = _T_1239 | _T_1246; // @[RVC.scala 205:14] + assign io_waleed_out = io_legal ? io_out_bits : 32'h0; // @[RVC.scala 226:19] +endmodule diff --git a/test_run_dir/lib.GCDMain482938682/encoder_generator.anno.json b/test_run_dir/lib.GCDMain482938682/encoder_generator.anno.json new file mode 100644 index 00000000..47396b55 --- /dev/null +++ b/test_run_dir/lib.GCDMain482938682/encoder_generator.anno.json @@ -0,0 +1,31 @@ +[ + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~encoder_generator|encoder_generator>io_out", + "sources":[ + "~encoder_generator|encoder_generator>io_in" + ] + }, + { + "class":"logger.LogLevelAnnotation", + "globalLogLevel":{ + + } + }, + { + "class":"firrtl.options.TargetDirAnnotation", + "directory":"test_run_dir/lib.GCDMain482938682" + }, + { + "class":"firrtl.options.OutputAnnotationFileAnnotation", + "file":"encoder_generator" + }, + { + "class":"firrtl.EmitCircuitAnnotation", + "emitter":"firrtl.VerilogEmitter" + }, + { + "class":"firrtl.transforms.BlackBoxTargetDirAnno", + "targetDir":"test_run_dir/lib.GCDMain482938682" + } +] \ No newline at end of file diff --git a/test_run_dir/lib.GCDMain482938682/encoder_generator.fir b/test_run_dir/lib.GCDMain482938682/encoder_generator.fir new file mode 100644 index 00000000..1b1a5b03 --- /dev/null +++ b/test_run_dir/lib.GCDMain482938682/encoder_generator.fir @@ -0,0 +1,34 @@ +;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10 +circuit encoder_generator : + module encoder_generator : + input clock : Clock + input reset : UInt<1> + output io : {flip in : UInt<8>, out : UInt<3>} + + node _T = bits(io.in, 0, 0) @[Mux.scala 29:36] + node _T_1 = bits(io.in, 1, 1) @[Mux.scala 29:36] + node _T_2 = bits(io.in, 2, 2) @[Mux.scala 29:36] + node _T_3 = bits(io.in, 3, 3) @[Mux.scala 29:36] + node _T_4 = bits(io.in, 4, 4) @[Mux.scala 29:36] + node _T_5 = bits(io.in, 5, 5) @[Mux.scala 29:36] + node _T_6 = bits(io.in, 6, 6) @[Mux.scala 29:36] + node _T_7 = bits(io.in, 7, 7) @[Mux.scala 29:36] + node _T_8 = mux(_T, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_9 = mux(_T_1, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_10 = mux(_T_2, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_11 = mux(_T_3, UInt<2>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_12 = mux(_T_4, UInt<3>("h04"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_13 = mux(_T_5, UInt<3>("h05"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_14 = mux(_T_6, UInt<3>("h06"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_15 = mux(_T_7, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_16 = or(_T_8, _T_9) @[Mux.scala 27:72] + node _T_17 = or(_T_16, _T_10) @[Mux.scala 27:72] + node _T_18 = or(_T_17, _T_11) @[Mux.scala 27:72] + node _T_19 = or(_T_18, _T_12) @[Mux.scala 27:72] + node _T_20 = or(_T_19, _T_13) @[Mux.scala 27:72] + node _T_21 = or(_T_20, _T_14) @[Mux.scala 27:72] + node _T_22 = or(_T_21, _T_15) @[Mux.scala 27:72] + wire _T_23 : UInt<3> @[Mux.scala 27:72] + _T_23 <= _T_22 @[Mux.scala 27:72] + io.out <= _T_23 @[GCD.scala 74:10] + diff --git a/test_run_dir/lib.GCDMain482938682/encoder_generator.v b/test_run_dir/lib.GCDMain482938682/encoder_generator.v new file mode 100644 index 00000000..7929c497 --- /dev/null +++ b/test_run_dir/lib.GCDMain482938682/encoder_generator.v @@ -0,0 +1,21 @@ +module encoder_generator( + input clock, + input reset, + input [7:0] io_in, + output [2:0] io_out +); + wire [1:0] _T_10 = io_in[2] ? 2'h2 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_11 = io_in[3] ? 2'h3 : 2'h0; // @[Mux.scala 27:72] + wire [2:0] _T_12 = io_in[4] ? 3'h4 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_13 = io_in[5] ? 3'h5 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_14 = io_in[6] ? 3'h6 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_15 = io_in[7] ? 3'h7 : 3'h0; // @[Mux.scala 27:72] + wire [1:0] _GEN_0 = {{1'd0}, io_in[1]}; // @[Mux.scala 27:72] + wire [1:0] _T_17 = _GEN_0 | _T_10; // @[Mux.scala 27:72] + wire [1:0] _T_18 = _T_17 | _T_11; // @[Mux.scala 27:72] + wire [2:0] _GEN_1 = {{1'd0}, _T_18}; // @[Mux.scala 27:72] + wire [2:0] _T_19 = _GEN_1 | _T_12; // @[Mux.scala 27:72] + wire [2:0] _T_20 = _T_19 | _T_13; // @[Mux.scala 27:72] + wire [2:0] _T_21 = _T_20 | _T_14; // @[Mux.scala 27:72] + assign io_out = _T_21 | _T_15; // @[GCD.scala 74:10] +endmodule diff --git a/top.anno.json b/top.anno.json new file mode 100644 index 00000000..b6aa2548 --- /dev/null +++ b/top.anno.json @@ -0,0 +1,18 @@ +[ + { + "class":"firrtl.EmitCircuitAnnotation", + "emitter":"firrtl.VerilogEmitter" + }, + { + "class":"firrtl.options.TargetDirAnnotation", + "directory":"." + }, + { + "class":"firrtl.options.OutputAnnotationFileAnnotation", + "file":"top" + }, + { + "class":"firrtl.transforms.BlackBoxTargetDirAnno", + "targetDir":"." + } +] \ No newline at end of file diff --git a/top.fir b/top.fir new file mode 100644 index 00000000..4e2854a9 --- /dev/null +++ b/top.fir @@ -0,0 +1,26 @@ +;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10 +circuit top : + module reg1 : + input clock : Clock + input reset : AsyncReset + output io : {flip in : UInt<1>, out : UInt<1>} + + reg _T : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[GCD.scala 32:20] + _T <= io.in @[GCD.scala 32:20] + io.out <= _T @[GCD.scala 32:10] + + module top : + input clock : Clock + input reset : AsyncReset + output io : {flip in : UInt<1>, out : UInt<1>} + + node _T = asUInt(reset) @[GCD.scala 40:26] + node _T_1 = not(_T) @[GCD.scala 40:19] + node negReset = asAsyncReset(_T_1) @[GCD.scala 40:34] + inst r0 of reg1 @[GCD.scala 41:18] + r0.clock <= clock + r0.reset <= reset + io.out <= r0.io.out @[GCD.scala 42:8] + r0.io.in <= io.in @[GCD.scala 42:8] + r0.reset <= negReset @[GCD.scala 43:12] + diff --git a/top.v b/top.v new file mode 100644 index 00000000..c2ef77a6 --- /dev/null +++ b/top.v @@ -0,0 +1,87 @@ +module reg1( + input clock, + input reset, + input io_in, + output io_out +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; +`endif // RANDOMIZE_REG_INIT + reg _T; // @[GCD.scala 32:20] + assign io_out = _T; // @[GCD.scala 32:10] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + _T = _RAND_0[0:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + _T = 1'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge clock or posedge reset) begin + if (reset) begin + _T <= 1'h0; + end else begin + _T <= io_in; + end + end +endmodule +module top( + input clock, + input reset, + input io_in, + output io_out +); + wire r0_clock; // @[GCD.scala 41:18] + wire r0_reset; // @[GCD.scala 41:18] + wire r0_io_in; // @[GCD.scala 41:18] + wire r0_io_out; // @[GCD.scala 41:18] + reg1 r0 ( // @[GCD.scala 41:18] + .clock(r0_clock), + .reset(r0_reset), + .io_in(r0_io_in), + .io_out(r0_io_out) + ); + assign io_out = r0_io_out; // @[GCD.scala 42:8] + assign r0_clock = clock; + assign r0_reset = ~reset; // @[GCD.scala 43:12] + assign r0_io_in = io_in; // @[GCD.scala 42:8] +endmodule