From 190229bf7f3f53f5c87b51289036e04f24518548 Mon Sep 17 00:00:00 2001 From: Sarmad-paracha <67508400+Sarmad-paracha@users.noreply.github.com> Date: Fri, 25 Sep 2020 21:01:14 +0500 Subject: [PATCH 1/5] Update el2_ifu_aln_ctl.scala --- src/main/scala/ifu/el2_ifu_aln_ctl.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/ifu/el2_ifu_aln_ctl.scala b/src/main/scala/ifu/el2_ifu_aln_ctl.scala index aeb3d5e6..458c9ad7 100644 --- a/src/main/scala/ifu/el2_ifu_aln_ctl.scala +++ b/src/main/scala/ifu/el2_ifu_aln_ctl.scala @@ -377,7 +377,7 @@ class el2_ifu_aln_ctl extends Module with el2_lib { f2pc := RegEnable(io.ifu_fetch_pc, 0.U, f2_wr_en.asBool) f2pc := RegEnable(f1pc_in, 0.U, f1_shift_wr_en.asBool) f2pc := RegEnable(f0pc_in, 0.U, f0_shift_wr_en.asBool) -} +}/* object ifu_aln extends App { println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_aln_ctl())) -} \ No newline at end of file +}*/ From 45d3f79e82e7b20acf01223d92ae125f6893bef4 Mon Sep 17 00:00:00 2001 From: Sarmad-paracha <67508400+Sarmad-paracha@users.noreply.github.com> Date: Fri, 25 Sep 2020 21:02:06 +0500 Subject: [PATCH 2/5] Update el2_ifu_bp_ctl.scala --- src/main/scala/ifu/el2_ifu_bp_ctl.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/ifu/el2_ifu_bp_ctl.scala b/src/main/scala/ifu/el2_ifu_bp_ctl.scala index 883c2e33..2c12e2ce 100644 --- a/src/main/scala/ifu/el2_ifu_bp_ctl.scala +++ b/src/main/scala/ifu/el2_ifu_bp_ctl.scala @@ -317,8 +317,8 @@ class el2_ifu_bp_ctl extends Module with el2_lib { } - +/* object ifu_bp extends App { println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_bp_ctl())) -} +}*/ From 40779e33e7b52b845b12d52db12479a3448d9eb9 Mon Sep 17 00:00:00 2001 From: Sarmad-paracha <67508400+Sarmad-paracha@users.noreply.github.com> Date: Fri, 25 Sep 2020 21:02:58 +0500 Subject: [PATCH 3/5] Update el2_ifu_ifc_ctrl.scala --- src/main/scala/ifu/el2_ifu_ifc_ctrl.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/ifu/el2_ifu_ifc_ctrl.scala b/src/main/scala/ifu/el2_ifu_ifc_ctrl.scala index f7f40e67..ca181602 100644 --- a/src/main/scala/ifu/el2_ifu_ifc_ctrl.scala +++ b/src/main/scala/ifu/el2_ifu_ifc_ctrl.scala @@ -154,7 +154,7 @@ val io = IO(new Bundle{ io.ifc_fetch_addr_f := RegEnable(io.ifc_fetch_addr_bf, init = 0.U, io.exu_flush_final|io.ifc_fetch_req_f) } - +/* object ifu_ifc extends App { println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_ifc_ctrl())) -} \ No newline at end of file +}*/ From 964a6009aff52437be34c3fba5911054f40e7675 Mon Sep 17 00:00:00 2001 From: Sarmad-paracha <67508400+Sarmad-paracha@users.noreply.github.com> Date: Fri, 25 Sep 2020 21:37:05 +0500 Subject: [PATCH 4/5] Delete el2_ifu_aln_ctl.scala --- src/main/scala/ifu/el2_ifu_aln_ctl.scala | 383 ----------------------- 1 file changed, 383 deletions(-) delete mode 100644 src/main/scala/ifu/el2_ifu_aln_ctl.scala diff --git a/src/main/scala/ifu/el2_ifu_aln_ctl.scala b/src/main/scala/ifu/el2_ifu_aln_ctl.scala deleted file mode 100644 index 458c9ad7..00000000 --- a/src/main/scala/ifu/el2_ifu_aln_ctl.scala +++ /dev/null @@ -1,383 +0,0 @@ -package ifu -import lib._ -import chisel3._ -import chisel3.util._ -import include._ - -class el2_ifu_aln_ctl extends Module with el2_lib { - val io = IO(new Bundle{ - val scan_mode = Input(Bool()) - val ifu_async_error_start = Input(Bool()) - val iccm_rd_ecc_double_err = Input(Bool()) - val ic_access_fault_f = Input(Bool()) - val ic_access_fault_type_f = Input(UInt(2.W)) - val ifu_bp_fghr_f = Input(UInt(BHT_GHR_SIZE.W)) - val ifu_bp_btb_target_f = Input(UInt(32.W)) - val ifu_bp_poffset_f = Input(UInt(12.W)) - val ifu_bp_hist0_f = Input(UInt(2.W)) - val ifu_bp_hist1_f = Input(UInt(2.W)) - val ifu_bp_pc4_f = Input(UInt(2.W)) - val ifu_bp_way_f = Input(UInt(2.W)) - val ifu_bp_valid_f = Input(UInt(2.W)) - val ifu_bp_ret_f = Input(UInt(2.W)) - val exu_flush_final = Input(Bool()) - val dec_i0_decode_d = Input(Bool()) - val ifu_fetch_data_f = Input(UInt(32.W)) - val ifu_fetch_val = Input(UInt(2.W)) - val ifu_fetch_pc = Input(UInt(32.W)) - val ifu_i0_valid = Output(Bool()) - val ifu_i0_icaf = Output(Bool()) - val ifu_i0_icaf_type = Output(UInt(2.W)) - val ifu_i0_icaf_f1 = Output(Bool()) - val ifu_i0_dbecc = Output(Bool()) - val ifu_i0_instr = Output(new ExpandedInstruction) - val ifu_i0_pc = Output(UInt(32.W)) - val ifu_i0_pc4 = Output(Bool()) - val ifu_fb_consume1 = Output(Bool()) - val ifu_fb_consume2 = Output(Bool()) - val ifu_i0_bp_index = Output(UInt((BTB_ADDR_HI-BTB_ADDR_LO).W)) - val ifu_i0_bp_fghr = Output(UInt(BHT_GHR_SIZE.W)) - val ifu_i0_bp_btag = Output(UInt(BTB_BTAG_SIZE.W)) - val ifu_pmu_instr_aligned = Output(Bool()) - val ifu_i0_cinst = Output(UInt(16.W)) - val i0_brp = Output(new el2_br_pkt_t) - }) - val MHI = 46+BHT_GHR_SIZE // 54 - val MSIZE = 47+BHT_GHR_SIZE // 55 - - val error_stall_in = WireInit(Bool(),0.U) - val alignval = WireInit(UInt(2.W), 0.U) - val q0final = WireInit(UInt(16.W), 0.U) - val q1final = WireInit(UInt(16.W), 0.U) - val wrptr_in = WireInit(UInt(2.W), init = 0.U) - val rdptr_in = WireInit(UInt(2.W), init = 0.U) - - val f2val_in = WireInit(UInt(2.W), init = 0.U) - val f1val_in = WireInit(UInt(2.W), init = 0.U) - val f0val_in = WireInit(UInt(2.W), init = 0.U) - - val q2off_in = WireInit(UInt(1.W), init = 0.U) - val q1off_in = WireInit(UInt(1.W), init = 0.U) - val q0off_in = WireInit(UInt(1.W), init = 0.U) - - val sf0_valid = WireInit(Bool(), init = 0.U) - val sf1_valid = WireInit(Bool(), init = 0.U) - - val f2_valid = WireInit(Bool(), init = 0.U) - val ifvalid = WireInit(Bool(), init = 0.U) - val shift_f2_f1 = WireInit(Bool(), init = 0.U) - val shift_f2_f0 = WireInit(Bool(), init = 0.U) - val shift_f1_f0 = WireInit(Bool(), init = 0.U) - - val f0icaf = WireInit(Bool(), init = 0.U) - val f1icaf = WireInit(Bool(), init = 0.U) - - val sf0val = WireInit(UInt(2.W), 0.U) - val sf1val = WireInit(UInt(2.W), 0.U) - - val misc0 = WireInit(UInt(MHI.W), 0.U) - val misc1 = WireInit(UInt(MHI.W), 0.U) - val misc2 = WireInit(UInt(MHI.W), 0.U) - - val brdata1 = WireInit(UInt(12.W), init = 0.U) - val brdata0 = WireInit(UInt(12.W), init = 0.U) - val brdata2 = WireInit(UInt(12.W), init = 0.U) - - - - val error_stall = RegNext(error_stall_in, init = 0.U) - val f0val = RegNext(f0val_in, init = 0.U) - error_stall_in := (error_stall | io.ifu_async_error_start) & ~io.exu_flush_final - - val i0_shift = io.dec_i0_decode_d & ~error_stall - - io.ifu_pmu_instr_aligned := i0_shift - - val aligndata = Mux1H(Seq(f0val(0).asBool -> q0final, (~f0val(1) & f0val(0)).asBool -> Cat(q1final,q0final))) - - val decompressed = Module(new el2_ifu_compress_ctl(32, true)) - - decompressed.io.in := aligndata - - decompressed.io.out <> io.ifu_i0_instr - - - // 16-bit compressed instruction from the aligner to the dec for tracer - io.ifu_i0_cinst := aligndata(15,0) - - // Checking if its a 32-bit instruction or not - val first4B = decompressed.io.rvc - val first2B = ~first4B - val alignicaf = Mux1H(Seq(f0val(1).asBool -> f0icaf, (~f0val(1) & f0val(0)).asBool -> Cat(f1icaf,f0icaf))) - - io.ifu_i0_icaf := Mux1H(Seq(first4B -> alignicaf.orR, first2B -> alignicaf(0))) - io.ifu_i0_valid := Mux1H(Seq(first4B -> alignval(1), first2B -> alignval(0))) - io.ifu_i0_pc4 := first4B - - val shift_2B = i0_shift & first2B - val shift_4B = i0_shift & first4B - val f0_shift_2B = Mux1H(Seq(shift_2B.asBool -> f0val(0), shift_4B.asBool -> (~f0val(0) & f0val(0)))) - val f1_shift_2B = f0val(0) & ~f0val(1) & shift_4B - - val wrptr = RegNext(wrptr_in, init = 0.U) - val rdptr = RegNext(wrptr_in, init = 0.U) - - val f2val = RegNext(f2val_in, init = 0.U) - val f1val = RegNext(f1val_in, init = 0.U) - - - val q2off = RegNext(q2off_in, init = 0.U) - val q1off = RegNext(q1off_in, init = 0.U) - val q0off = RegNext(q0off_in, init = 0.U) - - val fetch_to_f0 = ~sf0_valid & ~sf1_valid & ~f2_valid & ifvalid - val fetch_to_f1 = (~sf0_valid & ~sf1_valid & f2_valid & ifvalid) | - (~sf0_valid & sf1_valid & ~f2_valid & ifvalid) | - ( sf0_valid & ~sf1_valid & ~f2_valid & ifvalid) - val fetch_to_f2 = (~sf0_valid & sf1_valid & f2_valid & ifvalid) | - ( sf0_valid & sf1_valid & ~f2_valid & ifvalid) - - val f2_wr_en = fetch_to_f2 - val f1_shift_wr_en = fetch_to_f1 | shift_f2_f1 | f1_shift_2B - val f0_shift_wr_en = fetch_to_f0 | shift_f2_f0 | shift_f1_f0 | shift_2B | shift_4B - - val qren = Cat(rdptr === 2.U, rdptr === 1.U, rdptr === 0.U) - val qwen = Cat(wrptr === 2.U & ifvalid, wrptr === 1.U & ifvalid, wrptr === 0.U & ifvalid) - - rdptr_in := Mux1H(Seq((qren(0) & io.ifu_fb_consume1 & ~io.exu_flush_final).asBool -> 1.U, - (qren(1) & io.ifu_fb_consume1 & ~io.exu_flush_final).asBool -> 2.U, - (qren(2) & io.ifu_fb_consume1 & ~io.exu_flush_final).asBool -> 0.U, - (qren(0) & io.ifu_fb_consume2 & ~io.exu_flush_final).asBool -> 2.U, - (qren(1) & io.ifu_fb_consume2 & ~io.exu_flush_final).asBool -> 0.U, - (qren(2) & io.ifu_fb_consume2 & ~io.exu_flush_final).asBool -> 1.U, - (~io.ifu_fb_consume1 & ~io.ifu_fb_consume2 & ~io.exu_flush_final).asBool -> rdptr)) - - wrptr_in := Mux1H(Seq((qwen(0) & ~io.exu_flush_final).asBool -> 1.U, - (qwen(1) & ~io.exu_flush_final).asBool -> 2.U, - (qwen(2) & ~io.exu_flush_final).asBool -> 0.U, - (~ifvalid & ~io.exu_flush_final).asBool->wrptr)) - - q2off_in := Mux1H(Seq((~qwen(2) & (rdptr===2.U)).asBool->(q2off.asUInt | f0_shift_2B), - (~qwen(2) & (rdptr===1.U)).asBool->(q2off.asUInt | f1_shift_2B), - (~qwen(2) & (rdptr===0.U)).asBool->q2off)) - - q1off_in := Mux1H(Seq((~qwen(1) & (rdptr===1.U)).asBool->(q1off.asUInt | f0_shift_2B), - (~qwen(1) & (rdptr===0.U)).asBool->(q1off.asUInt | f1_shift_2B), - (~qwen(1) & (rdptr===2.U)).asBool->q1off)) - - q0off_in := Mux1H(Seq((~qwen(0) & (rdptr===0.U)).asBool -> (q0off.asUInt | f0_shift_2B), - (~qwen(0) & (rdptr===2.U)).asBool -> (q0off.asUInt | f1_shift_2B), - (~qwen(0) & (rdptr===1.U)).asBool -> q0off)) - - val q0ptr = Mux1H(Seq((rdptr===0.U)->q0off, - (rdptr===1.U)->q1off, - (rdptr===2.U)->q2off)) - - val q1ptr = Mux1H(Seq((rdptr===0.U) -> q1off, (rdptr === 1.U) -> q2off, (rdptr === 2.U) -> q0off)) - - val q0sel = Cat(q0ptr, ~q0ptr) - - val q1sel = Cat(q1ptr, ~q1ptr) - - val misc_data_in = Cat(io.iccm_rd_ecc_double_err, io.ic_access_fault_f, io.ic_access_fault_type_f, - io.ifu_bp_btb_target_f(31,1), io.ifu_bp_poffset_f, io.ifu_bp_fghr_f) - - val misceff = Mux1H(Seq(qren(0).asBool() -> Cat(misc1, misc0), - qren(1).asBool()->Cat(misc2, misc1), - qren(2).asBool()->Cat(misc0, misc2))) - - val misc1eff = misceff(misceff.getWidth-1,MHI+1) - val misc0eff = misceff(MHI, 0) - - val f1dbecc = misc1eff(misc1eff.getWidth-1) - f1icaf := misc1eff(misc1eff.getWidth-2) - val f1ictype = misc1eff(misc1eff.getWidth-3,misc1eff.getWidth-4) - val f1prett = misc1eff(misc1eff.getWidth-5,misc1eff.getWidth-35) - val f1poffset = misc1eff(BHT_GHR_SIZE+11, BHT_GHR_SIZE) - val f1fghr = misc1eff(BHT_GHR_SIZE-1, 0) - - val f0dbecc = misc0eff(misc0eff.getWidth-1) - f0icaf := misc0eff(misc0eff.getWidth-2) - val f0ictype = misc0eff(misc0eff.getWidth-3,misc0eff.getWidth-4) - val f0prett = misc0eff(misc0eff.getWidth-5,misc0eff.getWidth-35) - val f0poffset = misc0eff(BHT_GHR_SIZE+11, BHT_GHR_SIZE) - val f0fghr = misc0eff(BHT_GHR_SIZE-1, 0) - - val brdata_in = Cat(io.ifu_bp_hist1_f(1),io.ifu_bp_hist0_f(1),io.ifu_bp_pc4_f(1),io.ifu_bp_way_f(1),io.ifu_bp_valid_f(1), - io.ifu_bp_ret_f(1), io.ifu_bp_hist1_f(0),io.ifu_bp_hist0_f(0),io.ifu_bp_pc4_f(0),io.ifu_bp_way_f(0), - io.ifu_bp_valid_f(0),io.ifu_bp_ret_f(0)) - - val brdataeff = Mux1H(Seq(qren(0).asBool->Cat(brdata1,brdata0), - qren(1).asBool->Cat(brdata2,brdata1), - qren(2).asBool->Cat(brdata0,brdata2))) - - val (brdata0eff,brdata1eff) = (brdataeff(11,0) , brdataeff(23,12)) - - val q0 = WireInit(UInt(32.W), init = 0.U) - val q1 = WireInit(UInt(32.W), init = 0.U) - val q2 = WireInit(UInt(32.W), init = 0.U) - - val qeff = Mux1H(Seq(qren(0).asBool->Cat(q1,q0), - qren(1).asBool->Cat(q2,q1), - qren(2).asBool->Cat(q0,q2))) - val (q1eff, q0eff) = (qeff(63,32), qeff(31,0)) - val brdata0final = Mux1H(Seq(q0sel(0).asBool -> brdata0eff, q0sel(1).asBool -> brdata0eff(11,6))) - - val brdata1final = Mux1H(Seq(q1sel(0).asBool -> brdata1eff, q1sel(1).asBool -> brdata1eff(11,6))) - - val f0ret = Cat(brdata0final(6),brdata0final(0)) - val f0brend = Cat(brdata0final(7),brdata0final(1)) - val f0way = Cat(brdata0final(8),brdata0final(2)) - val f0pc4 = Cat(brdata0final(9),brdata0final(3)) - val f0hist0 = Cat(brdata0final(10),brdata0final(4)) - val f0hist1 = Cat(brdata0final(11),brdata0final(5)) - - val f1ret = Cat(brdata1final(6),brdata1final(0)) - val f1brend = Cat(brdata1final(7),brdata1final(1)) - val f1way = Cat(brdata1final(8),brdata1final(2)) - val f1pc4 = Cat(brdata1final(9),brdata1final(3)) - val f1hist0 = Cat(brdata1final(10),brdata1final(4)) - val f1hist1 = Cat(brdata1final(11),brdata1final(5)) - - - - f2_valid := f2val(0) - sf1_valid := sf1val(0) - sf0_valid := sf0val(0) - - val consume_fb0 = ~sf0val(0) & f0val(0) - val consume_fb1 = ~sf1val(0) & f1val(0) - - io.ifu_fb_consume1 := consume_fb0 & ~consume_fb1 & ~io.exu_flush_final - io.ifu_fb_consume2 := consume_fb0 & consume_fb1 & ~io.exu_flush_final - - ifvalid := io.ifu_fetch_val(0) - - shift_f1_f0 := ~sf0_valid & sf1_valid - shift_f2_f0 := ~sf0_valid & ~sf1_valid & f2_valid - shift_f2_f1 := ~sf0_valid & sf1_valid & f2_valid - - val f0pc = WireInit(UInt(31.W), 0.U) - val f2pc = WireInit(UInt(31.W), 0.U) - - val f0pc_plus1 = f0pc + 1.U - - val sf1pc = (Fill(31, f1_shift_2B) & f0pc_plus1) | (Fill(31, ~f1_shift_2B) & f0pc) - - val f1pc_in = Mux1H(Seq(fetch_to_f1.asBool->io.ifu_fetch_pc, - shift_f2_f1.asBool->f2pc, - (~fetch_to_f1 & ~shift_f2_f1).asBool -> sf1pc)) - - val f0pc_in = Mux1H(Seq(fetch_to_f0.asBool->io.ifu_fetch_pc, - shift_f2_f0.asBool->f2pc, - shift_f1_f0.asBool->sf1pc, - (~fetch_to_f0 & ~shift_f2_f0 & ~shift_f1_f0).asBool->f0pc_plus1)) - - f2val_in := Mux1H(Seq((fetch_to_f2 & ~io.exu_flush_final).asBool->io.ifu_fetch_val, - (~fetch_to_f2 & ~shift_f2_f1 & ~shift_f2_f0 & ~io.exu_flush_final).asBool->f2val)) - - sf1val := Mux1H(Seq(f1_shift_2B.asBool->f1val(1), ~f1_shift_2B.asBool->f1val)) - - f1val_in := Mux1H(Seq((fetch_to_f1 & ~io.exu_flush_final).asBool -> io.ifu_fetch_val, - (shift_f2_f1 & ~io.exu_flush_final).asBool->f2val, - (~fetch_to_f1 & ~shift_f2_f1 & ~shift_f1_f0 & ~io.exu_flush_final).asBool->sf1val)) - - f0val := Mux1H(Seq(shift_2B.asBool -> f0val(1), (~shift_2B & ~shift_4B).asBool -> f0val)) - - f0val_in := Mux1H(Seq((fetch_to_f0 & ~io.exu_flush_final).asBool->io.ifu_fetch_val, - (shift_f2_f0 & ~io.exu_flush_final).asBool->f2val, - (shift_f1_f0 & ~io.exu_flush_final).asBool()->sf1val, - (~fetch_to_f0 & ~shift_f2_f0 & ~shift_f1_f0 & ~io.exu_flush_final).asBool->sf0val)) - - q0final := Mux1H(Seq(q0sel(0).asBool->q0eff, q0sel(1).asBool->q0eff(31,16))) - - q1final := Mux1H(Seq(q1sel(0).asBool->q1eff(15,0), q1sel(1).asBool->q1eff(31,16))) - - alignval := Mux1H(Seq(f0val(1).asBool->3.U, (~f0val(1) & f0val(0)) -> Cat(f1val(0),1.U))) - - val aligndbecc = Mux1H(Seq(f0val(1).asBool -> Fill(2,f0dbecc), (~f0val(1) & f0val(0)).asBool -> Cat(f1dbecc,f0dbecc))) - - val alignbrend = Mux1H(Seq(f0val(1).asBool()->f0brend, (~f0val(1) & f0val(0)).asBool->Cat(f1brend(0),f0brend(0)))) - - val alignpc4 = Mux1H(Seq(f0val(1).asBool()->f0pc4, (~f0val(1) & f0val(0)).asBool->Cat(f1pc4(0),f0pc4(0)))) - - val alignret = Mux1H(Seq(f0val(1).asBool()->f0ret, (~f0val(1) & f0val(0)).asBool->Cat(f1ret(0),f0ret(0)))) - - val alignway = Mux1H(Seq(f0val(1).asBool()->f0way, (~f0val(1) & f0val(0)).asBool->Cat(f1way(0),f0way(0)))) - - val alignhist1 = Mux1H(Seq(f0val(1).asBool()->f0hist1, (~f0val(1) & f0val(0)).asBool->Cat(f1hist1(0),f0hist1(0)))) - - val alignhist0 = Mux1H(Seq(f0val(1).asBool()->f0hist0, (~f0val(1) & f0val(0)).asBool->Cat(f1hist0(0),f0hist0(0)))) - - val alignfromf1 = ~f0val(1) & f0val(0) - - val f1pc = WireInit(UInt(31.W), init = 0.U) - - val secondpc = Mux1H(Seq(f0val(1).asBool()->f0pc_plus1 , (~f0val(1) & f0val(0)).asBool->f1pc)) - - io.ifu_i0_pc := f0pc - - val firstpc = f0pc - - io.ifu_i0_icaf_type := Mux((first4B & ~f0val(1) & f0val(0) & ~alignicaf(0) & ~aligndbecc(0)).asBool, f1ictype, f0ictype) - - val icaf_eff = alignicaf(1) | aligndbecc(1) - - io.ifu_i0_icaf_f1 := first4B & icaf_eff & alignfromf1 - - io.ifu_i0_dbecc := Mux1H(Seq(first4B->aligndbecc.orR, first2B->aligndbecc(0))) - - val firstpc_hash = el2_btb_addr_hash(f0pc) - - val secondpc_hash = el2_btb_addr_hash(secondpc) - - val firstbrtag_hash = if(BTB_BTAG_FOLD) el2_btb_tag_hash_fold(firstpc) else el2_btb_tag_hash(firstpc) - - val secondbrtag_hash = if(BTB_BTAG_FOLD) el2_btb_tag_hash_fold(secondpc) else el2_btb_tag_hash(secondpc) - - io.i0_brp.valid :=(first2B & alignbrend(0)) | (first4B & alignbrend(1)) | (first4B & alignval(1) & alignbrend(0)) - - io.i0_brp.ret := (first2B & alignret(0)) | (first4B & alignret(1)) - - io.i0_brp.way := Mux((first2B | alignbrend(0)).asBool, alignway(0), alignway(1)) - io.i0_brp.hist := Cat((first2B & alignhist1(0)) | (first4B & alignhist1(1)), - (first2B & alignhist0(0)) | (first4B & alignhist0(1))) - - io.i0_brp.toffset := Mux((first4B & alignfromf1).asBool, f1poffset, f0poffset) - - io.i0_brp.prett := Mux((first4B & alignfromf1).asBool, f1prett, f0prett) - - io.i0_brp.br_start_error := (first4B & alignval(1) & alignbrend(0)) - - io.i0_brp.bank := Mux((first2B | alignbrend(0)).asBool, firstpc(1), secondpc(1)) - - val i0_brp_pc4 = (first2B & alignpc4(0)) | (first4B & alignpc4(1)) - - io.i0_brp.br_error := (io.i0_brp.valid & i0_brp_pc4 & first2B) | (io.i0_brp.valid & ~i0_brp_pc4 & first4B) - - - io.ifu_i0_bp_index := Mux((first2B | alignbrend(0)).asBool, firstpc_hash, secondpc_hash) - - io.ifu_i0_bp_fghr := Mux((first4B & alignfromf1).asBool, f1fghr, f0fghr) - - io.ifu_i0_bp_btag := Mux((first2B | alignbrend(0)).asBool, firstbrtag_hash, secondbrtag_hash) - - brdata2 := RegEnable(brdata_in, 0.U, qwen(2)) - brdata1 := RegEnable(brdata_in, 0.U, qwen(1)) - brdata0 := RegEnable(brdata_in, 0.U, qwen(0)) - - misc2 := RegEnable(misc_data_in, 0.U, qwen(2)) - misc1 := RegEnable(misc_data_in, 0.U, qwen(1)) - misc0 := RegEnable(misc_data_in, 0.U, qwen(0)) - - q2 := RegEnable(io.ifu_fetch_data_f, 0.U, qwen(2)) - q1 := RegEnable(io.ifu_fetch_data_f, 0.U, qwen(1)) - q0 := RegEnable(io.ifu_fetch_data_f, 0.U, qwen(0)) - - f2pc := RegEnable(io.ifu_fetch_pc, 0.U, f2_wr_en.asBool) - f2pc := RegEnable(f1pc_in, 0.U, f1_shift_wr_en.asBool) - f2pc := RegEnable(f0pc_in, 0.U, f0_shift_wr_en.asBool) -}/* -object ifu_aln extends App { - println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_aln_ctl())) -}*/ From 04aeb043e9021d4086e84ce06ecc2d8f7a735ec4 Mon Sep 17 00:00:00 2001 From: Sarmad-paracha <67508400+Sarmad-paracha@users.noreply.github.com> Date: Fri, 25 Sep 2020 21:39:02 +0500 Subject: [PATCH 5/5] Update el2_ifu_compress_ctl.scala --- src/main/scala/ifu/el2_ifu_compress_ctl.scala | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/main/scala/ifu/el2_ifu_compress_ctl.scala b/src/main/scala/ifu/el2_ifu_compress_ctl.scala index 50af8fc0..c99c9148 100644 --- a/src/main/scala/ifu/el2_ifu_compress_ctl.scala +++ b/src/main/scala/ifu/el2_ifu_compress_ctl.scala @@ -179,8 +179,8 @@ class RVCDecoder(x: UInt, xLen: Int) { class el2_ifu_compress_ctl( val XLen: Int, val usingCompressed: Boolean) extends Module { val io = IO(new Bundle { - val in = Input(UInt(16.W)) - val out = Output(UInt(32.W)) + val din = Input(UInt(16.W)) + val dout = Output(UInt(32.W)) //val rvc = Output(Bool()) //val legal = Output(Bool()) //val waleed_out = Output(UInt(32.W)) @@ -189,10 +189,10 @@ class el2_ifu_compress_ctl( val XLen: Int, val usingCompressed: Boolean) extends //val q3_Out = Output(new ExpandedInstruction) }) if (usingCompressed) { - val rvc = io.in(1,0) =/= 3.U - val inst = new RVCDecoder(Cat(Fill(16,0.U),io.in), XLen) + val rvc = io.din(1,0) =/= 3.U + val inst = new RVCDecoder(Cat(Fill(16,0.U),io.din), XLen) val decoded = inst.decode - io.out := Mux(rvc, 0.U, decoded.bits) + io.dout := Mux(rvc, 0.U, decoded.bits) //io.out.rd := 0.U //io.out.rs1 := 0.U //io.out.rs2 := 0.U @@ -221,7 +221,7 @@ class el2_ifu_compress_ctl( val XLen: Int, val usingCompressed: Boolean) extends io.waleed_out := Mux(io.legal,io.out.bits,0.U)*/ } else { //io.rvc := false.B - io.out := new RVCDecoder(io.in, XLen).passthrough + io.dout := new RVCDecoder(io.din, XLen).passthrough } }