diff --git a/el2_ifu_iccm_mem.anno.json b/el2_ifu_iccm_mem.anno.json
index cb681bfe..ab7e9a2d 100644
--- a/el2_ifu_iccm_mem.anno.json
+++ b/el2_ifu_iccm_mem.anno.json
@@ -1,20 +1,30 @@
 [
   {
     "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_rd_data",
+    "sink":"~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_bank_wr_data_1",
     "sources":[
-      "~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_rw_addr",
-      "~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_wren",
-      "~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_wr_size"
+      "~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_wr_data"
     ]
   },
   {
     "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_rd_data_ecc",
+    "sink":"~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_bank_wr_data_0",
     "sources":[
-      "~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_rw_addr",
-      "~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_wren",
-      "~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_wr_size"
+      "~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_wr_data"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_bank_wr_data_2",
+    "sources":[
+      "~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_wr_data"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_bank_wr_data_3",
+    "sources":[
+      "~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_wr_data"
     ]
   },
   {
diff --git a/el2_ifu_iccm_mem.fir b/el2_ifu_iccm_mem.fir
index d82190b8..f77ea2a3 100644
--- a/el2_ifu_iccm_mem.fir
+++ b/el2_ifu_iccm_mem.fir
@@ -3,7 +3,7 @@ circuit el2_ifu_iccm_mem :
   module el2_ifu_iccm_mem : 
     input clock : Clock
     input reset : UInt<1>
-    output io : {flip clk_override : UInt<1>, flip iccm_wren : UInt<1>, flip iccm_rden : UInt<1>, flip iccm_rw_addr : UInt<15>, flip iccm_buf_correct_ecc : UInt<1>, flip iccm_correction_state : UInt<1>, flip iccm_wr_size : UInt<3>, flip iccm_wr_data : UInt<78>, iccm_rd_data : UInt<64>, iccm_rd_data_ecc : UInt<78>, flip scan_mode : UInt<1>}
+    output io : {flip clk_override : UInt<1>, flip iccm_wren : UInt<1>, flip iccm_rden : UInt<1>, flip iccm_rw_addr : UInt<15>, flip iccm_buf_correct_ecc : UInt<1>, flip iccm_correction_state : UInt<1>, flip iccm_wr_size : UInt<3>, flip iccm_wr_data : UInt<78>, iccm_rd_data : UInt<64>, iccm_rd_data_ecc : UInt<78>, flip scan_mode : UInt<1>, iccm_bank_wr_data : UInt<39>[4]}
     
     io.iccm_rd_data <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 22:19]
     io.iccm_rd_data_ecc <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 23:23]
@@ -47,94 +47,99 @@ circuit el2_ifu_iccm_mem :
     node _T_27 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 33:121]
     node _T_28 = eq(_T_27, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 33:139]
     node wren_bank_3 = or(_T_26, _T_28) @[el2_ifu_iccm_mem.scala 33:106]
-    node _T_29 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 35:81]
-    node _T_30 = eq(_T_29, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 35:99]
-    node _T_31 = and(io.iccm_rden, _T_30) @[el2_ifu_iccm_mem.scala 35:64]
-    node _T_32 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 35:121]
-    node _T_33 = eq(_T_32, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 35:139]
-    node rden_bank_0 = or(_T_31, _T_33) @[el2_ifu_iccm_mem.scala 35:106]
-    node _T_34 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 35:81]
-    node _T_35 = eq(_T_34, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 35:99]
-    node _T_36 = and(io.iccm_rden, _T_35) @[el2_ifu_iccm_mem.scala 35:64]
-    node _T_37 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 35:121]
-    node _T_38 = eq(_T_37, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 35:139]
-    node rden_bank_1 = or(_T_36, _T_38) @[el2_ifu_iccm_mem.scala 35:106]
-    node _T_39 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 35:81]
-    node _T_40 = eq(_T_39, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 35:99]
-    node _T_41 = and(io.iccm_rden, _T_40) @[el2_ifu_iccm_mem.scala 35:64]
-    node _T_42 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 35:121]
-    node _T_43 = eq(_T_42, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 35:139]
-    node rden_bank_2 = or(_T_41, _T_43) @[el2_ifu_iccm_mem.scala 35:106]
-    node _T_44 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 35:81]
-    node _T_45 = eq(_T_44, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 35:99]
-    node _T_46 = and(io.iccm_rden, _T_45) @[el2_ifu_iccm_mem.scala 35:64]
-    node _T_47 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 35:121]
-    node _T_48 = eq(_T_47, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 35:139]
-    node rden_bank_3 = or(_T_46, _T_48) @[el2_ifu_iccm_mem.scala 35:106]
-    node _T_49 = or(wren_bank_0, rden_bank_0) @[el2_ifu_iccm_mem.scala 36:72]
-    node iccm_clken_0 = or(_T_49, io.clk_override) @[el2_ifu_iccm_mem.scala 36:87]
-    node _T_50 = or(wren_bank_1, rden_bank_1) @[el2_ifu_iccm_mem.scala 36:72]
-    node iccm_clken_1 = or(_T_50, io.clk_override) @[el2_ifu_iccm_mem.scala 36:87]
-    node _T_51 = or(wren_bank_2, rden_bank_2) @[el2_ifu_iccm_mem.scala 36:72]
-    node iccm_clken_2 = or(_T_51, io.clk_override) @[el2_ifu_iccm_mem.scala 36:87]
-    node _T_52 = or(wren_bank_3, rden_bank_3) @[el2_ifu_iccm_mem.scala 36:72]
-    node iccm_clken_3 = or(_T_52, io.clk_override) @[el2_ifu_iccm_mem.scala 36:87]
-    node _T_53 = bits(wren_bank_0, 0, 0) @[el2_ifu_iccm_mem.scala 37:69]
-    node _T_54 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 37:92]
-    node _T_55 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 38:23]
-    node _T_56 = eq(_T_55, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 38:41]
-    node _T_57 = bits(addr_bank_inc, 14, 3) @[el2_ifu_iccm_mem.scala 38:62]
-    node _T_58 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 38:112]
-    node _T_59 = mux(_T_56, _T_57, _T_58) @[el2_ifu_iccm_mem.scala 38:8]
-    node addr_bank_0 = mux(_T_53, _T_54, _T_59) @[el2_ifu_iccm_mem.scala 37:55]
-    node _T_60 = bits(wren_bank_1, 0, 0) @[el2_ifu_iccm_mem.scala 37:69]
-    node _T_61 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 37:92]
-    node _T_62 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 38:23]
-    node _T_63 = eq(_T_62, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 38:41]
-    node _T_64 = bits(addr_bank_inc, 14, 3) @[el2_ifu_iccm_mem.scala 38:62]
-    node _T_65 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 38:112]
-    node _T_66 = mux(_T_63, _T_64, _T_65) @[el2_ifu_iccm_mem.scala 38:8]
-    node addr_bank_1 = mux(_T_60, _T_61, _T_66) @[el2_ifu_iccm_mem.scala 37:55]
-    node _T_67 = bits(wren_bank_2, 0, 0) @[el2_ifu_iccm_mem.scala 37:69]
-    node _T_68 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 37:92]
-    node _T_69 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 38:23]
-    node _T_70 = eq(_T_69, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 38:41]
-    node _T_71 = bits(addr_bank_inc, 14, 3) @[el2_ifu_iccm_mem.scala 38:62]
-    node _T_72 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 38:112]
-    node _T_73 = mux(_T_70, _T_71, _T_72) @[el2_ifu_iccm_mem.scala 38:8]
-    node addr_bank_2 = mux(_T_67, _T_68, _T_73) @[el2_ifu_iccm_mem.scala 37:55]
-    node _T_74 = bits(wren_bank_3, 0, 0) @[el2_ifu_iccm_mem.scala 37:69]
-    node _T_75 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 37:92]
-    node _T_76 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 38:23]
-    node _T_77 = eq(_T_76, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 38:41]
-    node _T_78 = bits(addr_bank_inc, 14, 3) @[el2_ifu_iccm_mem.scala 38:62]
-    node _T_79 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 38:112]
-    node _T_80 = mux(_T_77, _T_78, _T_79) @[el2_ifu_iccm_mem.scala 38:8]
-    node addr_bank_3 = mux(_T_74, _T_75, _T_80) @[el2_ifu_iccm_mem.scala 37:55]
-    cmem iccm_mem : UInt<39>[4][4096] @[el2_ifu_iccm_mem.scala 40:21]
-    node _T_81 = and(iccm_clken_0, wren_bank_0) @[el2_ifu_iccm_mem.scala 42:68]
-    node _T_82 = and(iccm_clken_1, wren_bank_1) @[el2_ifu_iccm_mem.scala 42:68]
-    node _T_83 = and(iccm_clken_2, wren_bank_2) @[el2_ifu_iccm_mem.scala 42:68]
-    node _T_84 = and(iccm_clken_3, wren_bank_3) @[el2_ifu_iccm_mem.scala 42:68]
-    wire write_vec : UInt<1>[4] @[el2_ifu_iccm_mem.scala 42:51]
-    write_vec[0] <= _T_81 @[el2_ifu_iccm_mem.scala 42:51]
-    write_vec[1] <= _T_82 @[el2_ifu_iccm_mem.scala 42:51]
-    write_vec[2] <= _T_83 @[el2_ifu_iccm_mem.scala 42:51]
-    write_vec[3] <= _T_84 @[el2_ifu_iccm_mem.scala 42:51]
-    node _T_85 = eq(wren_bank_0, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 43:72]
-    node _T_86 = and(iccm_clken_0, _T_85) @[el2_ifu_iccm_mem.scala 43:70]
-    node _T_87 = eq(wren_bank_1, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 43:72]
-    node _T_88 = and(iccm_clken_1, _T_87) @[el2_ifu_iccm_mem.scala 43:70]
-    node _T_89 = eq(wren_bank_2, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 43:72]
-    node _T_90 = and(iccm_clken_2, _T_89) @[el2_ifu_iccm_mem.scala 43:70]
-    node _T_91 = eq(wren_bank_3, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 43:72]
-    node _T_92 = and(iccm_clken_3, _T_91) @[el2_ifu_iccm_mem.scala 43:70]
-    wire read_enable : UInt<1>[4] @[el2_ifu_iccm_mem.scala 43:53]
-    read_enable[0] <= _T_86 @[el2_ifu_iccm_mem.scala 43:53]
-    read_enable[1] <= _T_88 @[el2_ifu_iccm_mem.scala 43:53]
-    read_enable[2] <= _T_90 @[el2_ifu_iccm_mem.scala 43:53]
-    read_enable[3] <= _T_92 @[el2_ifu_iccm_mem.scala 43:53]
-    wire iccm_bank_dout : UInt<39>[4] @[el2_ifu_iccm_mem.scala 45:28]
+    io.iccm_bank_wr_data[0] <= iccm_bank_wr_data[0] @[el2_ifu_iccm_mem.scala 35:24]
+    io.iccm_bank_wr_data[1] <= iccm_bank_wr_data[1] @[el2_ifu_iccm_mem.scala 35:24]
+    io.iccm_bank_wr_data[2] <= iccm_bank_wr_data[2] @[el2_ifu_iccm_mem.scala 35:24]
+    io.iccm_bank_wr_data[3] <= iccm_bank_wr_data[3] @[el2_ifu_iccm_mem.scala 35:24]
+    node _T_29 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 36:81]
+    node _T_30 = eq(_T_29, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 36:99]
+    node _T_31 = and(io.iccm_rden, _T_30) @[el2_ifu_iccm_mem.scala 36:64]
+    node _T_32 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 36:121]
+    node _T_33 = eq(_T_32, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 36:139]
+    node rden_bank_0 = or(_T_31, _T_33) @[el2_ifu_iccm_mem.scala 36:106]
+    node _T_34 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 36:81]
+    node _T_35 = eq(_T_34, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 36:99]
+    node _T_36 = and(io.iccm_rden, _T_35) @[el2_ifu_iccm_mem.scala 36:64]
+    node _T_37 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 36:121]
+    node _T_38 = eq(_T_37, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 36:139]
+    node rden_bank_1 = or(_T_36, _T_38) @[el2_ifu_iccm_mem.scala 36:106]
+    node _T_39 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 36:81]
+    node _T_40 = eq(_T_39, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 36:99]
+    node _T_41 = and(io.iccm_rden, _T_40) @[el2_ifu_iccm_mem.scala 36:64]
+    node _T_42 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 36:121]
+    node _T_43 = eq(_T_42, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 36:139]
+    node rden_bank_2 = or(_T_41, _T_43) @[el2_ifu_iccm_mem.scala 36:106]
+    node _T_44 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 36:81]
+    node _T_45 = eq(_T_44, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 36:99]
+    node _T_46 = and(io.iccm_rden, _T_45) @[el2_ifu_iccm_mem.scala 36:64]
+    node _T_47 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 36:121]
+    node _T_48 = eq(_T_47, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 36:139]
+    node rden_bank_3 = or(_T_46, _T_48) @[el2_ifu_iccm_mem.scala 36:106]
+    node _T_49 = or(wren_bank_0, rden_bank_0) @[el2_ifu_iccm_mem.scala 37:72]
+    node iccm_clken_0 = or(_T_49, io.clk_override) @[el2_ifu_iccm_mem.scala 37:87]
+    node _T_50 = or(wren_bank_1, rden_bank_1) @[el2_ifu_iccm_mem.scala 37:72]
+    node iccm_clken_1 = or(_T_50, io.clk_override) @[el2_ifu_iccm_mem.scala 37:87]
+    node _T_51 = or(wren_bank_2, rden_bank_2) @[el2_ifu_iccm_mem.scala 37:72]
+    node iccm_clken_2 = or(_T_51, io.clk_override) @[el2_ifu_iccm_mem.scala 37:87]
+    node _T_52 = or(wren_bank_3, rden_bank_3) @[el2_ifu_iccm_mem.scala 37:72]
+    node iccm_clken_3 = or(_T_52, io.clk_override) @[el2_ifu_iccm_mem.scala 37:87]
+    node _T_53 = bits(wren_bank_0, 0, 0) @[el2_ifu_iccm_mem.scala 38:69]
+    node _T_54 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 38:92]
+    node _T_55 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 39:23]
+    node _T_56 = eq(_T_55, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 39:41]
+    node _T_57 = bits(addr_bank_inc, 14, 3) @[el2_ifu_iccm_mem.scala 39:62]
+    node _T_58 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 39:112]
+    node _T_59 = mux(_T_56, _T_57, _T_58) @[el2_ifu_iccm_mem.scala 39:8]
+    node addr_bank_0 = mux(_T_53, _T_54, _T_59) @[el2_ifu_iccm_mem.scala 38:55]
+    node _T_60 = bits(wren_bank_1, 0, 0) @[el2_ifu_iccm_mem.scala 38:69]
+    node _T_61 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 38:92]
+    node _T_62 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 39:23]
+    node _T_63 = eq(_T_62, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 39:41]
+    node _T_64 = bits(addr_bank_inc, 14, 3) @[el2_ifu_iccm_mem.scala 39:62]
+    node _T_65 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 39:112]
+    node _T_66 = mux(_T_63, _T_64, _T_65) @[el2_ifu_iccm_mem.scala 39:8]
+    node addr_bank_1 = mux(_T_60, _T_61, _T_66) @[el2_ifu_iccm_mem.scala 38:55]
+    node _T_67 = bits(wren_bank_2, 0, 0) @[el2_ifu_iccm_mem.scala 38:69]
+    node _T_68 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 38:92]
+    node _T_69 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 39:23]
+    node _T_70 = eq(_T_69, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 39:41]
+    node _T_71 = bits(addr_bank_inc, 14, 3) @[el2_ifu_iccm_mem.scala 39:62]
+    node _T_72 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 39:112]
+    node _T_73 = mux(_T_70, _T_71, _T_72) @[el2_ifu_iccm_mem.scala 39:8]
+    node addr_bank_2 = mux(_T_67, _T_68, _T_73) @[el2_ifu_iccm_mem.scala 38:55]
+    node _T_74 = bits(wren_bank_3, 0, 0) @[el2_ifu_iccm_mem.scala 38:69]
+    node _T_75 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 38:92]
+    node _T_76 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 39:23]
+    node _T_77 = eq(_T_76, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 39:41]
+    node _T_78 = bits(addr_bank_inc, 14, 3) @[el2_ifu_iccm_mem.scala 39:62]
+    node _T_79 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 39:112]
+    node _T_80 = mux(_T_77, _T_78, _T_79) @[el2_ifu_iccm_mem.scala 39:8]
+    node addr_bank_3 = mux(_T_74, _T_75, _T_80) @[el2_ifu_iccm_mem.scala 38:55]
+    cmem iccm_mem : UInt<39>[4][4096] @[el2_ifu_iccm_mem.scala 41:21]
+    node _T_81 = and(iccm_clken_0, wren_bank_0) @[el2_ifu_iccm_mem.scala 43:68]
+    node _T_82 = and(iccm_clken_1, wren_bank_1) @[el2_ifu_iccm_mem.scala 43:68]
+    node _T_83 = and(iccm_clken_2, wren_bank_2) @[el2_ifu_iccm_mem.scala 43:68]
+    node _T_84 = and(iccm_clken_3, wren_bank_3) @[el2_ifu_iccm_mem.scala 43:68]
+    wire write_vec : UInt<1>[4] @[el2_ifu_iccm_mem.scala 43:51]
+    write_vec[0] <= _T_81 @[el2_ifu_iccm_mem.scala 43:51]
+    write_vec[1] <= _T_82 @[el2_ifu_iccm_mem.scala 43:51]
+    write_vec[2] <= _T_83 @[el2_ifu_iccm_mem.scala 43:51]
+    write_vec[3] <= _T_84 @[el2_ifu_iccm_mem.scala 43:51]
+    node _T_85 = eq(wren_bank_0, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 44:72]
+    node _T_86 = and(iccm_clken_0, _T_85) @[el2_ifu_iccm_mem.scala 44:70]
+    node _T_87 = eq(wren_bank_1, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 44:72]
+    node _T_88 = and(iccm_clken_1, _T_87) @[el2_ifu_iccm_mem.scala 44:70]
+    node _T_89 = eq(wren_bank_2, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 44:72]
+    node _T_90 = and(iccm_clken_2, _T_89) @[el2_ifu_iccm_mem.scala 44:70]
+    node _T_91 = eq(wren_bank_3, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 44:72]
+    node _T_92 = and(iccm_clken_3, _T_91) @[el2_ifu_iccm_mem.scala 44:70]
+    wire read_enable : UInt<1>[4] @[el2_ifu_iccm_mem.scala 44:53]
+    read_enable[0] <= _T_86 @[el2_ifu_iccm_mem.scala 44:53]
+    read_enable[1] <= _T_88 @[el2_ifu_iccm_mem.scala 44:53]
+    read_enable[2] <= _T_90 @[el2_ifu_iccm_mem.scala 44:53]
+    read_enable[3] <= _T_92 @[el2_ifu_iccm_mem.scala 44:53]
+    wire iccm_bank_dout : UInt<39>[4] @[el2_ifu_iccm_mem.scala 46:28]
+    wire inter : UInt<39>[4] @[el2_ifu_iccm_mem.scala 47:19]
     write mport _T_93 = iccm_mem[addr_bank_0], clock
     when write_vec[0] :
       _T_93[0] <= iccm_bank_wr_data[0]
@@ -187,411 +192,423 @@ circuit el2_ifu_iccm_mem :
     when write_vec[3] :
       _T_96[3] <= iccm_bank_wr_data[3]
       skip
-    read mport _T_97 = iccm_mem[addr_bank_0], clock @[el2_ifu_iccm_mem.scala 47:34]
-    iccm_bank_dout[0] <= _T_97[0] @[el2_ifu_iccm_mem.scala 47:18]
-    iccm_bank_dout[1] <= _T_97[1] @[el2_ifu_iccm_mem.scala 47:18]
-    iccm_bank_dout[2] <= _T_97[2] @[el2_ifu_iccm_mem.scala 47:18]
-    iccm_bank_dout[3] <= _T_97[3] @[el2_ifu_iccm_mem.scala 47:18]
+    read mport _T_97 = iccm_mem[addr_bank_0], clock @[el2_ifu_iccm_mem.scala 49:25]
+    inter[0] <= _T_97[0] @[el2_ifu_iccm_mem.scala 49:9]
+    inter[1] <= _T_97[1] @[el2_ifu_iccm_mem.scala 49:9]
+    inter[2] <= _T_97[2] @[el2_ifu_iccm_mem.scala 49:9]
+    inter[3] <= _T_97[3] @[el2_ifu_iccm_mem.scala 49:9]
+    reg _T_98 : UInt, clock @[el2_ifu_iccm_mem.scala 50:62]
+    _T_98 <= inter[0] @[el2_ifu_iccm_mem.scala 50:62]
+    iccm_bank_dout[0] <= _T_98 @[el2_ifu_iccm_mem.scala 50:52]
+    reg _T_99 : UInt, clock @[el2_ifu_iccm_mem.scala 50:62]
+    _T_99 <= inter[1] @[el2_ifu_iccm_mem.scala 50:62]
+    iccm_bank_dout[1] <= _T_99 @[el2_ifu_iccm_mem.scala 50:52]
+    reg _T_100 : UInt, clock @[el2_ifu_iccm_mem.scala 50:62]
+    _T_100 <= inter[2] @[el2_ifu_iccm_mem.scala 50:62]
+    iccm_bank_dout[2] <= _T_100 @[el2_ifu_iccm_mem.scala 50:52]
+    reg _T_101 : UInt, clock @[el2_ifu_iccm_mem.scala 50:62]
+    _T_101 <= inter[3] @[el2_ifu_iccm_mem.scala 50:62]
+    iccm_bank_dout[3] <= _T_101 @[el2_ifu_iccm_mem.scala 50:52]
     wire redundant_valid : UInt<2>
     redundant_valid <= UInt<1>("h00")
-    wire redundant_address : UInt<14>[2] @[el2_ifu_iccm_mem.scala 50:31]
-    redundant_address[0] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 51:21]
-    redundant_address[1] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 51:21]
-    node _T_98 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 53:67]
-    node _T_99 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 53:90]
-    node _T_100 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 53:128]
-    node _T_101 = eq(_T_99, _T_100) @[el2_ifu_iccm_mem.scala 53:105]
-    node _T_102 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 53:163]
-    node _T_103 = eq(_T_102, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 53:169]
-    node _T_104 = and(_T_101, _T_103) @[el2_ifu_iccm_mem.scala 53:145]
-    node _T_105 = and(_T_98, _T_104) @[el2_ifu_iccm_mem.scala 53:71]
-    node _T_106 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 54:22]
-    node _T_107 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 54:60]
-    node _T_108 = eq(_T_106, _T_107) @[el2_ifu_iccm_mem.scala 54:37]
-    node _T_109 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 54:93]
-    node _T_110 = eq(_T_109, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 54:99]
-    node _T_111 = and(_T_108, _T_110) @[el2_ifu_iccm_mem.scala 54:77]
-    node _T_112 = or(_T_105, _T_111) @[el2_ifu_iccm_mem.scala 53:179]
-    node _T_113 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 53:67]
-    node _T_114 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 53:90]
-    node _T_115 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 53:128]
-    node _T_116 = eq(_T_114, _T_115) @[el2_ifu_iccm_mem.scala 53:105]
-    node _T_117 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 53:163]
-    node _T_118 = eq(_T_117, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 53:169]
-    node _T_119 = and(_T_116, _T_118) @[el2_ifu_iccm_mem.scala 53:145]
-    node _T_120 = and(_T_113, _T_119) @[el2_ifu_iccm_mem.scala 53:71]
-    node _T_121 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 54:22]
-    node _T_122 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 54:60]
-    node _T_123 = eq(_T_121, _T_122) @[el2_ifu_iccm_mem.scala 54:37]
-    node _T_124 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 54:93]
-    node _T_125 = eq(_T_124, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 54:99]
-    node _T_126 = and(_T_123, _T_125) @[el2_ifu_iccm_mem.scala 54:77]
-    node _T_127 = or(_T_120, _T_126) @[el2_ifu_iccm_mem.scala 53:179]
-    node _T_128 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 53:67]
-    node _T_129 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 53:90]
-    node _T_130 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 53:128]
-    node _T_131 = eq(_T_129, _T_130) @[el2_ifu_iccm_mem.scala 53:105]
-    node _T_132 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 53:163]
-    node _T_133 = eq(_T_132, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 53:169]
-    node _T_134 = and(_T_131, _T_133) @[el2_ifu_iccm_mem.scala 53:145]
-    node _T_135 = and(_T_128, _T_134) @[el2_ifu_iccm_mem.scala 53:71]
-    node _T_136 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 54:22]
-    node _T_137 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 54:60]
-    node _T_138 = eq(_T_136, _T_137) @[el2_ifu_iccm_mem.scala 54:37]
-    node _T_139 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 54:93]
-    node _T_140 = eq(_T_139, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 54:99]
-    node _T_141 = and(_T_138, _T_140) @[el2_ifu_iccm_mem.scala 54:77]
-    node _T_142 = or(_T_135, _T_141) @[el2_ifu_iccm_mem.scala 53:179]
-    node _T_143 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 53:67]
-    node _T_144 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 53:90]
-    node _T_145 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 53:128]
-    node _T_146 = eq(_T_144, _T_145) @[el2_ifu_iccm_mem.scala 53:105]
-    node _T_147 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 53:163]
-    node _T_148 = eq(_T_147, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 53:169]
-    node _T_149 = and(_T_146, _T_148) @[el2_ifu_iccm_mem.scala 53:145]
-    node _T_150 = and(_T_143, _T_149) @[el2_ifu_iccm_mem.scala 53:71]
-    node _T_151 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 54:22]
-    node _T_152 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 54:60]
-    node _T_153 = eq(_T_151, _T_152) @[el2_ifu_iccm_mem.scala 54:37]
-    node _T_154 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 54:93]
-    node _T_155 = eq(_T_154, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 54:99]
-    node _T_156 = and(_T_153, _T_155) @[el2_ifu_iccm_mem.scala 54:77]
-    node _T_157 = or(_T_150, _T_156) @[el2_ifu_iccm_mem.scala 53:179]
-    node _T_158 = cat(_T_157, _T_142) @[Cat.scala 29:58]
-    node _T_159 = cat(_T_158, _T_127) @[Cat.scala 29:58]
-    node sel_red1 = cat(_T_159, _T_112) @[Cat.scala 29:58]
-    node _T_160 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 55:67]
-    node _T_161 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 55:90]
-    node _T_162 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 55:128]
-    node _T_163 = eq(_T_161, _T_162) @[el2_ifu_iccm_mem.scala 55:105]
-    node _T_164 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 55:163]
-    node _T_165 = eq(_T_164, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 55:169]
-    node _T_166 = and(_T_163, _T_165) @[el2_ifu_iccm_mem.scala 55:145]
-    node _T_167 = and(_T_160, _T_166) @[el2_ifu_iccm_mem.scala 55:71]
-    node _T_168 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 56:22]
-    node _T_169 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 56:60]
-    node _T_170 = eq(_T_168, _T_169) @[el2_ifu_iccm_mem.scala 56:37]
-    node _T_171 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 56:93]
-    node _T_172 = eq(_T_171, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 56:99]
-    node _T_173 = and(_T_170, _T_172) @[el2_ifu_iccm_mem.scala 56:77]
-    node _T_174 = or(_T_167, _T_173) @[el2_ifu_iccm_mem.scala 55:179]
-    node _T_175 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 55:67]
-    node _T_176 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 55:90]
-    node _T_177 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 55:128]
-    node _T_178 = eq(_T_176, _T_177) @[el2_ifu_iccm_mem.scala 55:105]
-    node _T_179 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 55:163]
-    node _T_180 = eq(_T_179, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 55:169]
-    node _T_181 = and(_T_178, _T_180) @[el2_ifu_iccm_mem.scala 55:145]
-    node _T_182 = and(_T_175, _T_181) @[el2_ifu_iccm_mem.scala 55:71]
-    node _T_183 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 56:22]
-    node _T_184 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 56:60]
-    node _T_185 = eq(_T_183, _T_184) @[el2_ifu_iccm_mem.scala 56:37]
-    node _T_186 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 56:93]
-    node _T_187 = eq(_T_186, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 56:99]
-    node _T_188 = and(_T_185, _T_187) @[el2_ifu_iccm_mem.scala 56:77]
-    node _T_189 = or(_T_182, _T_188) @[el2_ifu_iccm_mem.scala 55:179]
-    node _T_190 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 55:67]
-    node _T_191 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 55:90]
-    node _T_192 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 55:128]
-    node _T_193 = eq(_T_191, _T_192) @[el2_ifu_iccm_mem.scala 55:105]
-    node _T_194 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 55:163]
-    node _T_195 = eq(_T_194, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 55:169]
-    node _T_196 = and(_T_193, _T_195) @[el2_ifu_iccm_mem.scala 55:145]
-    node _T_197 = and(_T_190, _T_196) @[el2_ifu_iccm_mem.scala 55:71]
-    node _T_198 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 56:22]
-    node _T_199 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 56:60]
-    node _T_200 = eq(_T_198, _T_199) @[el2_ifu_iccm_mem.scala 56:37]
-    node _T_201 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 56:93]
-    node _T_202 = eq(_T_201, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 56:99]
-    node _T_203 = and(_T_200, _T_202) @[el2_ifu_iccm_mem.scala 56:77]
-    node _T_204 = or(_T_197, _T_203) @[el2_ifu_iccm_mem.scala 55:179]
-    node _T_205 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 55:67]
-    node _T_206 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 55:90]
-    node _T_207 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 55:128]
-    node _T_208 = eq(_T_206, _T_207) @[el2_ifu_iccm_mem.scala 55:105]
-    node _T_209 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 55:163]
-    node _T_210 = eq(_T_209, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 55:169]
-    node _T_211 = and(_T_208, _T_210) @[el2_ifu_iccm_mem.scala 55:145]
-    node _T_212 = and(_T_205, _T_211) @[el2_ifu_iccm_mem.scala 55:71]
-    node _T_213 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 56:22]
-    node _T_214 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 56:60]
-    node _T_215 = eq(_T_213, _T_214) @[el2_ifu_iccm_mem.scala 56:37]
-    node _T_216 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 56:93]
-    node _T_217 = eq(_T_216, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 56:99]
-    node _T_218 = and(_T_215, _T_217) @[el2_ifu_iccm_mem.scala 56:77]
-    node _T_219 = or(_T_212, _T_218) @[el2_ifu_iccm_mem.scala 55:179]
-    node _T_220 = cat(_T_219, _T_204) @[Cat.scala 29:58]
-    node _T_221 = cat(_T_220, _T_189) @[Cat.scala 29:58]
-    node sel_red0 = cat(_T_221, _T_174) @[Cat.scala 29:58]
-    reg sel_red0_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 58:27]
-    sel_red0_q <= sel_red0 @[el2_ifu_iccm_mem.scala 58:27]
-    reg sel_red1_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 59:27]
-    sel_red1_q <= sel_red1 @[el2_ifu_iccm_mem.scala 59:27]
-    wire redundant_data : UInt<39>[2] @[el2_ifu_iccm_mem.scala 60:28]
-    redundant_data[0] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 61:18]
-    redundant_data[1] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 61:18]
-    node _T_222 = bits(sel_red1_q, 0, 0) @[el2_ifu_iccm_mem.scala 63:47]
-    node _T_223 = bits(_T_222, 0, 0) @[el2_ifu_iccm_mem.scala 63:51]
-    node _T_224 = bits(sel_red0_q, 0, 0) @[el2_ifu_iccm_mem.scala 64:47]
-    node _T_225 = bits(_T_224, 0, 0) @[el2_ifu_iccm_mem.scala 64:51]
-    node _T_226 = bits(sel_red0_q, 0, 0) @[el2_ifu_iccm_mem.scala 65:47]
-    node _T_227 = not(_T_226) @[el2_ifu_iccm_mem.scala 65:36]
-    node _T_228 = bits(sel_red1_q, 0, 0) @[el2_ifu_iccm_mem.scala 65:64]
-    node _T_229 = not(_T_228) @[el2_ifu_iccm_mem.scala 65:53]
-    node _T_230 = and(_T_227, _T_229) @[el2_ifu_iccm_mem.scala 65:51]
-    node _T_231 = bits(_T_230, 0, 0) @[el2_ifu_iccm_mem.scala 65:69]
-    node _T_232 = mux(_T_223, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_233 = mux(_T_225, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_234 = mux(_T_231, iccm_bank_dout[0], UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_235 = or(_T_232, _T_233) @[Mux.scala 27:72]
-    node _T_236 = or(_T_235, _T_234) @[Mux.scala 27:72]
+    wire redundant_address : UInt<14>[2] @[el2_ifu_iccm_mem.scala 53:31]
+    redundant_address[0] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 54:21]
+    redundant_address[1] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 54:21]
+    node _T_102 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 56:67]
+    node _T_103 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 56:90]
+    node _T_104 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 56:128]
+    node _T_105 = eq(_T_103, _T_104) @[el2_ifu_iccm_mem.scala 56:105]
+    node _T_106 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 56:163]
+    node _T_107 = eq(_T_106, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 56:169]
+    node _T_108 = and(_T_105, _T_107) @[el2_ifu_iccm_mem.scala 56:145]
+    node _T_109 = and(_T_102, _T_108) @[el2_ifu_iccm_mem.scala 56:71]
+    node _T_110 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 57:22]
+    node _T_111 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 57:60]
+    node _T_112 = eq(_T_110, _T_111) @[el2_ifu_iccm_mem.scala 57:37]
+    node _T_113 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 57:93]
+    node _T_114 = eq(_T_113, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 57:99]
+    node _T_115 = and(_T_112, _T_114) @[el2_ifu_iccm_mem.scala 57:77]
+    node _T_116 = or(_T_109, _T_115) @[el2_ifu_iccm_mem.scala 56:179]
+    node _T_117 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 56:67]
+    node _T_118 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 56:90]
+    node _T_119 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 56:128]
+    node _T_120 = eq(_T_118, _T_119) @[el2_ifu_iccm_mem.scala 56:105]
+    node _T_121 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 56:163]
+    node _T_122 = eq(_T_121, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 56:169]
+    node _T_123 = and(_T_120, _T_122) @[el2_ifu_iccm_mem.scala 56:145]
+    node _T_124 = and(_T_117, _T_123) @[el2_ifu_iccm_mem.scala 56:71]
+    node _T_125 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 57:22]
+    node _T_126 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 57:60]
+    node _T_127 = eq(_T_125, _T_126) @[el2_ifu_iccm_mem.scala 57:37]
+    node _T_128 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 57:93]
+    node _T_129 = eq(_T_128, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 57:99]
+    node _T_130 = and(_T_127, _T_129) @[el2_ifu_iccm_mem.scala 57:77]
+    node _T_131 = or(_T_124, _T_130) @[el2_ifu_iccm_mem.scala 56:179]
+    node _T_132 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 56:67]
+    node _T_133 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 56:90]
+    node _T_134 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 56:128]
+    node _T_135 = eq(_T_133, _T_134) @[el2_ifu_iccm_mem.scala 56:105]
+    node _T_136 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 56:163]
+    node _T_137 = eq(_T_136, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 56:169]
+    node _T_138 = and(_T_135, _T_137) @[el2_ifu_iccm_mem.scala 56:145]
+    node _T_139 = and(_T_132, _T_138) @[el2_ifu_iccm_mem.scala 56:71]
+    node _T_140 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 57:22]
+    node _T_141 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 57:60]
+    node _T_142 = eq(_T_140, _T_141) @[el2_ifu_iccm_mem.scala 57:37]
+    node _T_143 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 57:93]
+    node _T_144 = eq(_T_143, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 57:99]
+    node _T_145 = and(_T_142, _T_144) @[el2_ifu_iccm_mem.scala 57:77]
+    node _T_146 = or(_T_139, _T_145) @[el2_ifu_iccm_mem.scala 56:179]
+    node _T_147 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 56:67]
+    node _T_148 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 56:90]
+    node _T_149 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 56:128]
+    node _T_150 = eq(_T_148, _T_149) @[el2_ifu_iccm_mem.scala 56:105]
+    node _T_151 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 56:163]
+    node _T_152 = eq(_T_151, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 56:169]
+    node _T_153 = and(_T_150, _T_152) @[el2_ifu_iccm_mem.scala 56:145]
+    node _T_154 = and(_T_147, _T_153) @[el2_ifu_iccm_mem.scala 56:71]
+    node _T_155 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 57:22]
+    node _T_156 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 57:60]
+    node _T_157 = eq(_T_155, _T_156) @[el2_ifu_iccm_mem.scala 57:37]
+    node _T_158 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 57:93]
+    node _T_159 = eq(_T_158, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 57:99]
+    node _T_160 = and(_T_157, _T_159) @[el2_ifu_iccm_mem.scala 57:77]
+    node _T_161 = or(_T_154, _T_160) @[el2_ifu_iccm_mem.scala 56:179]
+    node _T_162 = cat(_T_161, _T_146) @[Cat.scala 29:58]
+    node _T_163 = cat(_T_162, _T_131) @[Cat.scala 29:58]
+    node sel_red1 = cat(_T_163, _T_116) @[Cat.scala 29:58]
+    node _T_164 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 58:67]
+    node _T_165 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 58:90]
+    node _T_166 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 58:128]
+    node _T_167 = eq(_T_165, _T_166) @[el2_ifu_iccm_mem.scala 58:105]
+    node _T_168 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 58:163]
+    node _T_169 = eq(_T_168, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 58:169]
+    node _T_170 = and(_T_167, _T_169) @[el2_ifu_iccm_mem.scala 58:145]
+    node _T_171 = and(_T_164, _T_170) @[el2_ifu_iccm_mem.scala 58:71]
+    node _T_172 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 59:22]
+    node _T_173 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 59:60]
+    node _T_174 = eq(_T_172, _T_173) @[el2_ifu_iccm_mem.scala 59:37]
+    node _T_175 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 59:93]
+    node _T_176 = eq(_T_175, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 59:99]
+    node _T_177 = and(_T_174, _T_176) @[el2_ifu_iccm_mem.scala 59:77]
+    node _T_178 = or(_T_171, _T_177) @[el2_ifu_iccm_mem.scala 58:179]
+    node _T_179 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 58:67]
+    node _T_180 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 58:90]
+    node _T_181 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 58:128]
+    node _T_182 = eq(_T_180, _T_181) @[el2_ifu_iccm_mem.scala 58:105]
+    node _T_183 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 58:163]
+    node _T_184 = eq(_T_183, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 58:169]
+    node _T_185 = and(_T_182, _T_184) @[el2_ifu_iccm_mem.scala 58:145]
+    node _T_186 = and(_T_179, _T_185) @[el2_ifu_iccm_mem.scala 58:71]
+    node _T_187 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 59:22]
+    node _T_188 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 59:60]
+    node _T_189 = eq(_T_187, _T_188) @[el2_ifu_iccm_mem.scala 59:37]
+    node _T_190 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 59:93]
+    node _T_191 = eq(_T_190, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 59:99]
+    node _T_192 = and(_T_189, _T_191) @[el2_ifu_iccm_mem.scala 59:77]
+    node _T_193 = or(_T_186, _T_192) @[el2_ifu_iccm_mem.scala 58:179]
+    node _T_194 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 58:67]
+    node _T_195 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 58:90]
+    node _T_196 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 58:128]
+    node _T_197 = eq(_T_195, _T_196) @[el2_ifu_iccm_mem.scala 58:105]
+    node _T_198 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 58:163]
+    node _T_199 = eq(_T_198, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 58:169]
+    node _T_200 = and(_T_197, _T_199) @[el2_ifu_iccm_mem.scala 58:145]
+    node _T_201 = and(_T_194, _T_200) @[el2_ifu_iccm_mem.scala 58:71]
+    node _T_202 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 59:22]
+    node _T_203 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 59:60]
+    node _T_204 = eq(_T_202, _T_203) @[el2_ifu_iccm_mem.scala 59:37]
+    node _T_205 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 59:93]
+    node _T_206 = eq(_T_205, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 59:99]
+    node _T_207 = and(_T_204, _T_206) @[el2_ifu_iccm_mem.scala 59:77]
+    node _T_208 = or(_T_201, _T_207) @[el2_ifu_iccm_mem.scala 58:179]
+    node _T_209 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 58:67]
+    node _T_210 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 58:90]
+    node _T_211 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 58:128]
+    node _T_212 = eq(_T_210, _T_211) @[el2_ifu_iccm_mem.scala 58:105]
+    node _T_213 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 58:163]
+    node _T_214 = eq(_T_213, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 58:169]
+    node _T_215 = and(_T_212, _T_214) @[el2_ifu_iccm_mem.scala 58:145]
+    node _T_216 = and(_T_209, _T_215) @[el2_ifu_iccm_mem.scala 58:71]
+    node _T_217 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 59:22]
+    node _T_218 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 59:60]
+    node _T_219 = eq(_T_217, _T_218) @[el2_ifu_iccm_mem.scala 59:37]
+    node _T_220 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 59:93]
+    node _T_221 = eq(_T_220, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 59:99]
+    node _T_222 = and(_T_219, _T_221) @[el2_ifu_iccm_mem.scala 59:77]
+    node _T_223 = or(_T_216, _T_222) @[el2_ifu_iccm_mem.scala 58:179]
+    node _T_224 = cat(_T_223, _T_208) @[Cat.scala 29:58]
+    node _T_225 = cat(_T_224, _T_193) @[Cat.scala 29:58]
+    node sel_red0 = cat(_T_225, _T_178) @[Cat.scala 29:58]
+    reg sel_red0_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 61:27]
+    sel_red0_q <= sel_red0 @[el2_ifu_iccm_mem.scala 61:27]
+    reg sel_red1_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 62:27]
+    sel_red1_q <= sel_red1 @[el2_ifu_iccm_mem.scala 62:27]
+    wire redundant_data : UInt<39>[2] @[el2_ifu_iccm_mem.scala 63:28]
+    redundant_data[0] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 64:18]
+    redundant_data[1] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 64:18]
+    node _T_226 = bits(sel_red1_q, 0, 0) @[el2_ifu_iccm_mem.scala 66:47]
+    node _T_227 = bits(_T_226, 0, 0) @[el2_ifu_iccm_mem.scala 66:51]
+    node _T_228 = bits(sel_red0_q, 0, 0) @[el2_ifu_iccm_mem.scala 67:47]
+    node _T_229 = bits(_T_228, 0, 0) @[el2_ifu_iccm_mem.scala 67:51]
+    node _T_230 = bits(sel_red0_q, 0, 0) @[el2_ifu_iccm_mem.scala 68:47]
+    node _T_231 = not(_T_230) @[el2_ifu_iccm_mem.scala 68:36]
+    node _T_232 = bits(sel_red1_q, 0, 0) @[el2_ifu_iccm_mem.scala 68:64]
+    node _T_233 = not(_T_232) @[el2_ifu_iccm_mem.scala 68:53]
+    node _T_234 = and(_T_231, _T_233) @[el2_ifu_iccm_mem.scala 68:51]
+    node _T_235 = bits(_T_234, 0, 0) @[el2_ifu_iccm_mem.scala 68:69]
+    node _T_236 = mux(_T_227, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_237 = mux(_T_229, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_238 = mux(_T_235, iccm_bank_dout[0], UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_239 = or(_T_236, _T_237) @[Mux.scala 27:72]
+    node _T_240 = or(_T_239, _T_238) @[Mux.scala 27:72]
     wire iccm_bank_dout_fn_0 : UInt<39> @[Mux.scala 27:72]
-    iccm_bank_dout_fn_0 <= _T_236 @[Mux.scala 27:72]
-    node _T_237 = bits(sel_red1_q, 1, 1) @[el2_ifu_iccm_mem.scala 63:47]
-    node _T_238 = bits(_T_237, 0, 0) @[el2_ifu_iccm_mem.scala 63:51]
-    node _T_239 = bits(sel_red0_q, 1, 1) @[el2_ifu_iccm_mem.scala 64:47]
-    node _T_240 = bits(_T_239, 0, 0) @[el2_ifu_iccm_mem.scala 64:51]
-    node _T_241 = bits(sel_red0_q, 1, 1) @[el2_ifu_iccm_mem.scala 65:47]
-    node _T_242 = not(_T_241) @[el2_ifu_iccm_mem.scala 65:36]
-    node _T_243 = bits(sel_red1_q, 1, 1) @[el2_ifu_iccm_mem.scala 65:64]
-    node _T_244 = not(_T_243) @[el2_ifu_iccm_mem.scala 65:53]
-    node _T_245 = and(_T_242, _T_244) @[el2_ifu_iccm_mem.scala 65:51]
-    node _T_246 = bits(_T_245, 0, 0) @[el2_ifu_iccm_mem.scala 65:69]
-    node _T_247 = mux(_T_238, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_248 = mux(_T_240, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_249 = mux(_T_246, iccm_bank_dout[1], UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_250 = or(_T_247, _T_248) @[Mux.scala 27:72]
-    node _T_251 = or(_T_250, _T_249) @[Mux.scala 27:72]
+    iccm_bank_dout_fn_0 <= _T_240 @[Mux.scala 27:72]
+    node _T_241 = bits(sel_red1_q, 1, 1) @[el2_ifu_iccm_mem.scala 66:47]
+    node _T_242 = bits(_T_241, 0, 0) @[el2_ifu_iccm_mem.scala 66:51]
+    node _T_243 = bits(sel_red0_q, 1, 1) @[el2_ifu_iccm_mem.scala 67:47]
+    node _T_244 = bits(_T_243, 0, 0) @[el2_ifu_iccm_mem.scala 67:51]
+    node _T_245 = bits(sel_red0_q, 1, 1) @[el2_ifu_iccm_mem.scala 68:47]
+    node _T_246 = not(_T_245) @[el2_ifu_iccm_mem.scala 68:36]
+    node _T_247 = bits(sel_red1_q, 1, 1) @[el2_ifu_iccm_mem.scala 68:64]
+    node _T_248 = not(_T_247) @[el2_ifu_iccm_mem.scala 68:53]
+    node _T_249 = and(_T_246, _T_248) @[el2_ifu_iccm_mem.scala 68:51]
+    node _T_250 = bits(_T_249, 0, 0) @[el2_ifu_iccm_mem.scala 68:69]
+    node _T_251 = mux(_T_242, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_252 = mux(_T_244, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_253 = mux(_T_250, iccm_bank_dout[1], UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_254 = or(_T_251, _T_252) @[Mux.scala 27:72]
+    node _T_255 = or(_T_254, _T_253) @[Mux.scala 27:72]
     wire iccm_bank_dout_fn_1 : UInt<39> @[Mux.scala 27:72]
-    iccm_bank_dout_fn_1 <= _T_251 @[Mux.scala 27:72]
-    node _T_252 = bits(sel_red1_q, 2, 2) @[el2_ifu_iccm_mem.scala 63:47]
-    node _T_253 = bits(_T_252, 0, 0) @[el2_ifu_iccm_mem.scala 63:51]
-    node _T_254 = bits(sel_red0_q, 2, 2) @[el2_ifu_iccm_mem.scala 64:47]
-    node _T_255 = bits(_T_254, 0, 0) @[el2_ifu_iccm_mem.scala 64:51]
-    node _T_256 = bits(sel_red0_q, 2, 2) @[el2_ifu_iccm_mem.scala 65:47]
-    node _T_257 = not(_T_256) @[el2_ifu_iccm_mem.scala 65:36]
-    node _T_258 = bits(sel_red1_q, 2, 2) @[el2_ifu_iccm_mem.scala 65:64]
-    node _T_259 = not(_T_258) @[el2_ifu_iccm_mem.scala 65:53]
-    node _T_260 = and(_T_257, _T_259) @[el2_ifu_iccm_mem.scala 65:51]
-    node _T_261 = bits(_T_260, 0, 0) @[el2_ifu_iccm_mem.scala 65:69]
-    node _T_262 = mux(_T_253, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_263 = mux(_T_255, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_264 = mux(_T_261, iccm_bank_dout[2], UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_265 = or(_T_262, _T_263) @[Mux.scala 27:72]
-    node _T_266 = or(_T_265, _T_264) @[Mux.scala 27:72]
+    iccm_bank_dout_fn_1 <= _T_255 @[Mux.scala 27:72]
+    node _T_256 = bits(sel_red1_q, 2, 2) @[el2_ifu_iccm_mem.scala 66:47]
+    node _T_257 = bits(_T_256, 0, 0) @[el2_ifu_iccm_mem.scala 66:51]
+    node _T_258 = bits(sel_red0_q, 2, 2) @[el2_ifu_iccm_mem.scala 67:47]
+    node _T_259 = bits(_T_258, 0, 0) @[el2_ifu_iccm_mem.scala 67:51]
+    node _T_260 = bits(sel_red0_q, 2, 2) @[el2_ifu_iccm_mem.scala 68:47]
+    node _T_261 = not(_T_260) @[el2_ifu_iccm_mem.scala 68:36]
+    node _T_262 = bits(sel_red1_q, 2, 2) @[el2_ifu_iccm_mem.scala 68:64]
+    node _T_263 = not(_T_262) @[el2_ifu_iccm_mem.scala 68:53]
+    node _T_264 = and(_T_261, _T_263) @[el2_ifu_iccm_mem.scala 68:51]
+    node _T_265 = bits(_T_264, 0, 0) @[el2_ifu_iccm_mem.scala 68:69]
+    node _T_266 = mux(_T_257, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_267 = mux(_T_259, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_268 = mux(_T_265, iccm_bank_dout[2], UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_269 = or(_T_266, _T_267) @[Mux.scala 27:72]
+    node _T_270 = or(_T_269, _T_268) @[Mux.scala 27:72]
     wire iccm_bank_dout_fn_2 : UInt<39> @[Mux.scala 27:72]
-    iccm_bank_dout_fn_2 <= _T_266 @[Mux.scala 27:72]
-    node _T_267 = bits(sel_red1_q, 3, 3) @[el2_ifu_iccm_mem.scala 63:47]
-    node _T_268 = bits(_T_267, 0, 0) @[el2_ifu_iccm_mem.scala 63:51]
-    node _T_269 = bits(sel_red0_q, 3, 3) @[el2_ifu_iccm_mem.scala 64:47]
-    node _T_270 = bits(_T_269, 0, 0) @[el2_ifu_iccm_mem.scala 64:51]
-    node _T_271 = bits(sel_red0_q, 3, 3) @[el2_ifu_iccm_mem.scala 65:47]
-    node _T_272 = not(_T_271) @[el2_ifu_iccm_mem.scala 65:36]
-    node _T_273 = bits(sel_red1_q, 3, 3) @[el2_ifu_iccm_mem.scala 65:64]
-    node _T_274 = not(_T_273) @[el2_ifu_iccm_mem.scala 65:53]
-    node _T_275 = and(_T_272, _T_274) @[el2_ifu_iccm_mem.scala 65:51]
-    node _T_276 = bits(_T_275, 0, 0) @[el2_ifu_iccm_mem.scala 65:69]
-    node _T_277 = mux(_T_268, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_278 = mux(_T_270, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_279 = mux(_T_276, iccm_bank_dout[3], UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_280 = or(_T_277, _T_278) @[Mux.scala 27:72]
-    node _T_281 = or(_T_280, _T_279) @[Mux.scala 27:72]
+    iccm_bank_dout_fn_2 <= _T_270 @[Mux.scala 27:72]
+    node _T_271 = bits(sel_red1_q, 3, 3) @[el2_ifu_iccm_mem.scala 66:47]
+    node _T_272 = bits(_T_271, 0, 0) @[el2_ifu_iccm_mem.scala 66:51]
+    node _T_273 = bits(sel_red0_q, 3, 3) @[el2_ifu_iccm_mem.scala 67:47]
+    node _T_274 = bits(_T_273, 0, 0) @[el2_ifu_iccm_mem.scala 67:51]
+    node _T_275 = bits(sel_red0_q, 3, 3) @[el2_ifu_iccm_mem.scala 68:47]
+    node _T_276 = not(_T_275) @[el2_ifu_iccm_mem.scala 68:36]
+    node _T_277 = bits(sel_red1_q, 3, 3) @[el2_ifu_iccm_mem.scala 68:64]
+    node _T_278 = not(_T_277) @[el2_ifu_iccm_mem.scala 68:53]
+    node _T_279 = and(_T_276, _T_278) @[el2_ifu_iccm_mem.scala 68:51]
+    node _T_280 = bits(_T_279, 0, 0) @[el2_ifu_iccm_mem.scala 68:69]
+    node _T_281 = mux(_T_272, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_282 = mux(_T_274, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_283 = mux(_T_280, iccm_bank_dout[3], UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_284 = or(_T_281, _T_282) @[Mux.scala 27:72]
+    node _T_285 = or(_T_284, _T_283) @[Mux.scala 27:72]
     wire iccm_bank_dout_fn_3 : UInt<39> @[Mux.scala 27:72]
-    iccm_bank_dout_fn_3 <= _T_281 @[Mux.scala 27:72]
+    iccm_bank_dout_fn_3 <= _T_285 @[Mux.scala 27:72]
     wire redundant_lru : UInt<1>
     redundant_lru <= UInt<1>("h00")
-    node _T_282 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 67:20]
-    node r0_addr_en = and(_T_282, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 67:35]
-    node r1_addr_en = and(redundant_lru, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 68:35]
-    node _T_283 = orr(sel_red0) @[el2_ifu_iccm_mem.scala 69:63]
-    node _T_284 = orr(sel_red1) @[el2_ifu_iccm_mem.scala 69:78]
-    node _T_285 = or(_T_283, _T_284) @[el2_ifu_iccm_mem.scala 69:67]
-    node _T_286 = and(_T_285, io.iccm_rden) @[el2_ifu_iccm_mem.scala 69:83]
-    node _T_287 = and(_T_286, io.iccm_correction_state) @[el2_ifu_iccm_mem.scala 69:98]
-    node redundant_lru_en = or(io.iccm_buf_correct_ecc, _T_287) @[el2_ifu_iccm_mem.scala 69:50]
-    node _T_288 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 70:55]
-    node _T_289 = orr(sel_red0) @[el2_ifu_iccm_mem.scala 70:84]
-    node _T_290 = mux(_T_289, UInt<1>("h01"), UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 70:74]
-    node redundant_lru_in = mux(io.iccm_buf_correct_ecc, _T_288, _T_290) @[el2_ifu_iccm_mem.scala 70:29]
-    reg _T_291 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    node _T_286 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 70:20]
+    node r0_addr_en = and(_T_286, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 70:35]
+    node r1_addr_en = and(redundant_lru, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 71:35]
+    node _T_287 = orr(sel_red0) @[el2_ifu_iccm_mem.scala 72:63]
+    node _T_288 = orr(sel_red1) @[el2_ifu_iccm_mem.scala 72:78]
+    node _T_289 = or(_T_287, _T_288) @[el2_ifu_iccm_mem.scala 72:67]
+    node _T_290 = and(_T_289, io.iccm_rden) @[el2_ifu_iccm_mem.scala 72:83]
+    node _T_291 = and(_T_290, io.iccm_correction_state) @[el2_ifu_iccm_mem.scala 72:98]
+    node redundant_lru_en = or(io.iccm_buf_correct_ecc, _T_291) @[el2_ifu_iccm_mem.scala 72:50]
+    node _T_292 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 73:55]
+    node _T_293 = orr(sel_red0) @[el2_ifu_iccm_mem.scala 73:84]
+    node _T_294 = mux(_T_293, UInt<1>("h01"), UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 73:74]
+    node redundant_lru_in = mux(io.iccm_buf_correct_ecc, _T_292, _T_294) @[el2_ifu_iccm_mem.scala 73:29]
+    reg _T_295 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
     when redundant_lru_en : @[Reg.scala 28:19]
-      _T_291 <= redundant_lru_in @[Reg.scala 28:23]
+      _T_295 <= redundant_lru_in @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    redundant_lru <= _T_291 @[el2_ifu_iccm_mem.scala 71:17]
-    node _T_292 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 72:52]
-    reg _T_293 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    redundant_lru <= _T_295 @[el2_ifu_iccm_mem.scala 74:17]
+    node _T_296 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 75:52]
+    reg _T_297 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
     when r0_addr_en : @[Reg.scala 28:19]
-      _T_293 <= _T_292 @[Reg.scala 28:23]
+      _T_297 <= _T_296 @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    redundant_address[0] <= _T_293 @[el2_ifu_iccm_mem.scala 72:24]
-    node _T_294 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 73:52]
-    node _T_295 = bits(r1_addr_en, 0, 0) @[el2_ifu_iccm_mem.scala 73:85]
-    reg _T_296 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when _T_295 : @[Reg.scala 28:19]
-      _T_296 <= _T_294 @[Reg.scala 28:23]
+    redundant_address[0] <= _T_297 @[el2_ifu_iccm_mem.scala 75:24]
+    node _T_298 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 76:52]
+    node _T_299 = bits(r1_addr_en, 0, 0) @[el2_ifu_iccm_mem.scala 76:85]
+    reg _T_300 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_299 : @[Reg.scala 28:19]
+      _T_300 <= _T_298 @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    redundant_address[1] <= _T_296 @[el2_ifu_iccm_mem.scala 73:24]
-    node _T_297 = bits(r1_addr_en, 0, 0) @[el2_ifu_iccm_mem.scala 74:57]
-    reg _T_298 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when _T_297 : @[Reg.scala 28:19]
-      _T_298 <= UInt<1>("h01") @[Reg.scala 28:23]
+    redundant_address[1] <= _T_300 @[el2_ifu_iccm_mem.scala 76:24]
+    node _T_301 = bits(r1_addr_en, 0, 0) @[el2_ifu_iccm_mem.scala 77:57]
+    reg _T_302 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_301 : @[Reg.scala 28:19]
+      _T_302 <= UInt<1>("h01") @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    reg _T_299 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    reg _T_303 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
     when r0_addr_en : @[Reg.scala 28:19]
-      _T_299 <= UInt<1>("h01") @[Reg.scala 28:23]
+      _T_303 <= UInt<1>("h01") @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    node _T_300 = cat(_T_298, _T_299) @[Cat.scala 29:58]
-    redundant_valid <= _T_300 @[el2_ifu_iccm_mem.scala 74:19]
-    node _T_301 = bits(io.iccm_rw_addr, 14, 2) @[el2_ifu_iccm_mem.scala 76:45]
-    node _T_302 = bits(redundant_address[0], 13, 1) @[el2_ifu_iccm_mem.scala 76:85]
-    node _T_303 = eq(_T_301, _T_302) @[el2_ifu_iccm_mem.scala 76:61]
-    node _T_304 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 77:22]
-    node _T_305 = bits(redundant_address[0], 0, 0) @[el2_ifu_iccm_mem.scala 77:48]
-    node _T_306 = and(_T_304, _T_305) @[el2_ifu_iccm_mem.scala 77:26]
-    node _T_307 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 77:70]
-    node _T_308 = eq(_T_307, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 77:75]
-    node _T_309 = or(_T_306, _T_308) @[el2_ifu_iccm_mem.scala 77:52]
-    node _T_310 = and(_T_303, _T_309) @[el2_ifu_iccm_mem.scala 76:102]
-    node _T_311 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 77:101]
-    node _T_312 = and(_T_310, _T_311) @[el2_ifu_iccm_mem.scala 77:84]
-    node _T_313 = and(_T_312, io.iccm_wren) @[el2_ifu_iccm_mem.scala 77:105]
-    node _T_314 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 78:6]
-    node _T_315 = and(_T_314, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 78:21]
-    node redundant_data0_en = or(_T_313, _T_315) @[el2_ifu_iccm_mem.scala 77:121]
-    node _T_316 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 79:49]
-    node _T_317 = bits(redundant_address[0], 0, 0) @[el2_ifu_iccm_mem.scala 79:73]
-    node _T_318 = and(_T_316, _T_317) @[el2_ifu_iccm_mem.scala 79:52]
-    node _T_319 = bits(redundant_address[0], 0, 0) @[el2_ifu_iccm_mem.scala 79:100]
-    node _T_320 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 79:122]
-    node _T_321 = eq(_T_320, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 79:127]
-    node _T_322 = and(_T_319, _T_321) @[el2_ifu_iccm_mem.scala 79:104]
-    node _T_323 = or(_T_318, _T_322) @[el2_ifu_iccm_mem.scala 79:78]
-    node _T_324 = bits(_T_323, 0, 0) @[el2_ifu_iccm_mem.scala 79:137]
-    node _T_325 = bits(io.iccm_wr_data, 77, 39) @[el2_ifu_iccm_mem.scala 80:20]
-    node _T_326 = bits(io.iccm_wr_data, 38, 0) @[el2_ifu_iccm_mem.scala 80:44]
-    node redundant_data0_in = mux(_T_324, _T_325, _T_326) @[el2_ifu_iccm_mem.scala 79:31]
-    node _T_327 = bits(redundant_data0_en, 0, 0) @[el2_ifu_iccm_mem.scala 81:78]
-    reg _T_328 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when _T_327 : @[Reg.scala 28:19]
-      _T_328 <= redundant_data0_in @[Reg.scala 28:23]
+    node _T_304 = cat(_T_302, _T_303) @[Cat.scala 29:58]
+    redundant_valid <= _T_304 @[el2_ifu_iccm_mem.scala 77:19]
+    node _T_305 = bits(io.iccm_rw_addr, 14, 2) @[el2_ifu_iccm_mem.scala 79:45]
+    node _T_306 = bits(redundant_address[0], 13, 1) @[el2_ifu_iccm_mem.scala 79:85]
+    node _T_307 = eq(_T_305, _T_306) @[el2_ifu_iccm_mem.scala 79:61]
+    node _T_308 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 80:22]
+    node _T_309 = bits(redundant_address[0], 0, 0) @[el2_ifu_iccm_mem.scala 80:48]
+    node _T_310 = and(_T_308, _T_309) @[el2_ifu_iccm_mem.scala 80:26]
+    node _T_311 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 80:70]
+    node _T_312 = eq(_T_311, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 80:75]
+    node _T_313 = or(_T_310, _T_312) @[el2_ifu_iccm_mem.scala 80:52]
+    node _T_314 = and(_T_307, _T_313) @[el2_ifu_iccm_mem.scala 79:102]
+    node _T_315 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 80:101]
+    node _T_316 = and(_T_314, _T_315) @[el2_ifu_iccm_mem.scala 80:84]
+    node _T_317 = and(_T_316, io.iccm_wren) @[el2_ifu_iccm_mem.scala 80:105]
+    node _T_318 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 81:6]
+    node _T_319 = and(_T_318, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 81:21]
+    node redundant_data0_en = or(_T_317, _T_319) @[el2_ifu_iccm_mem.scala 80:121]
+    node _T_320 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 82:49]
+    node _T_321 = bits(redundant_address[0], 0, 0) @[el2_ifu_iccm_mem.scala 82:73]
+    node _T_322 = and(_T_320, _T_321) @[el2_ifu_iccm_mem.scala 82:52]
+    node _T_323 = bits(redundant_address[0], 0, 0) @[el2_ifu_iccm_mem.scala 82:100]
+    node _T_324 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 82:122]
+    node _T_325 = eq(_T_324, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 82:127]
+    node _T_326 = and(_T_323, _T_325) @[el2_ifu_iccm_mem.scala 82:104]
+    node _T_327 = or(_T_322, _T_326) @[el2_ifu_iccm_mem.scala 82:78]
+    node _T_328 = bits(_T_327, 0, 0) @[el2_ifu_iccm_mem.scala 82:137]
+    node _T_329 = bits(io.iccm_wr_data, 77, 39) @[el2_ifu_iccm_mem.scala 83:20]
+    node _T_330 = bits(io.iccm_wr_data, 38, 0) @[el2_ifu_iccm_mem.scala 83:44]
+    node redundant_data0_in = mux(_T_328, _T_329, _T_330) @[el2_ifu_iccm_mem.scala 82:31]
+    node _T_331 = bits(redundant_data0_en, 0, 0) @[el2_ifu_iccm_mem.scala 84:78]
+    reg _T_332 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_331 : @[Reg.scala 28:19]
+      _T_332 <= redundant_data0_in @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    redundant_data[0] <= _T_328 @[el2_ifu_iccm_mem.scala 81:21]
-    node _T_329 = bits(io.iccm_rw_addr, 14, 2) @[el2_ifu_iccm_mem.scala 83:45]
-    node _T_330 = bits(redundant_address[1], 13, 1) @[el2_ifu_iccm_mem.scala 83:85]
-    node _T_331 = eq(_T_329, _T_330) @[el2_ifu_iccm_mem.scala 83:61]
-    node _T_332 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 84:22]
-    node _T_333 = bits(redundant_address[1], 0, 0) @[el2_ifu_iccm_mem.scala 84:48]
-    node _T_334 = and(_T_332, _T_333) @[el2_ifu_iccm_mem.scala 84:26]
-    node _T_335 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 84:70]
-    node _T_336 = eq(_T_335, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 84:75]
-    node _T_337 = or(_T_334, _T_336) @[el2_ifu_iccm_mem.scala 84:52]
-    node _T_338 = and(_T_331, _T_337) @[el2_ifu_iccm_mem.scala 83:102]
-    node _T_339 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 84:101]
-    node _T_340 = and(_T_338, _T_339) @[el2_ifu_iccm_mem.scala 84:84]
-    node _T_341 = and(_T_340, io.iccm_wren) @[el2_ifu_iccm_mem.scala 84:105]
-    node _T_342 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 85:6]
-    node _T_343 = and(_T_342, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 85:21]
-    node redundant_data1_en = or(_T_341, _T_343) @[el2_ifu_iccm_mem.scala 84:121]
-    node _T_344 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 86:49]
-    node _T_345 = bits(redundant_address[1], 0, 0) @[el2_ifu_iccm_mem.scala 86:73]
-    node _T_346 = and(_T_344, _T_345) @[el2_ifu_iccm_mem.scala 86:52]
-    node _T_347 = bits(redundant_address[1], 0, 0) @[el2_ifu_iccm_mem.scala 86:100]
-    node _T_348 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 86:122]
-    node _T_349 = eq(_T_348, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 86:127]
-    node _T_350 = and(_T_347, _T_349) @[el2_ifu_iccm_mem.scala 86:104]
-    node _T_351 = or(_T_346, _T_350) @[el2_ifu_iccm_mem.scala 86:78]
-    node _T_352 = bits(_T_351, 0, 0) @[el2_ifu_iccm_mem.scala 86:137]
-    node _T_353 = bits(io.iccm_wr_data, 77, 39) @[el2_ifu_iccm_mem.scala 87:20]
-    node _T_354 = bits(io.iccm_wr_data, 38, 0) @[el2_ifu_iccm_mem.scala 87:44]
-    node redundant_data1_in = mux(_T_352, _T_353, _T_354) @[el2_ifu_iccm_mem.scala 86:31]
-    node _T_355 = bits(redundant_data1_en, 0, 0) @[el2_ifu_iccm_mem.scala 88:78]
-    reg _T_356 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when _T_355 : @[Reg.scala 28:19]
-      _T_356 <= redundant_data1_in @[Reg.scala 28:23]
+    redundant_data[0] <= _T_332 @[el2_ifu_iccm_mem.scala 84:21]
+    node _T_333 = bits(io.iccm_rw_addr, 14, 2) @[el2_ifu_iccm_mem.scala 86:45]
+    node _T_334 = bits(redundant_address[1], 13, 1) @[el2_ifu_iccm_mem.scala 86:85]
+    node _T_335 = eq(_T_333, _T_334) @[el2_ifu_iccm_mem.scala 86:61]
+    node _T_336 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 87:22]
+    node _T_337 = bits(redundant_address[1], 0, 0) @[el2_ifu_iccm_mem.scala 87:48]
+    node _T_338 = and(_T_336, _T_337) @[el2_ifu_iccm_mem.scala 87:26]
+    node _T_339 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 87:70]
+    node _T_340 = eq(_T_339, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 87:75]
+    node _T_341 = or(_T_338, _T_340) @[el2_ifu_iccm_mem.scala 87:52]
+    node _T_342 = and(_T_335, _T_341) @[el2_ifu_iccm_mem.scala 86:102]
+    node _T_343 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 87:101]
+    node _T_344 = and(_T_342, _T_343) @[el2_ifu_iccm_mem.scala 87:84]
+    node _T_345 = and(_T_344, io.iccm_wren) @[el2_ifu_iccm_mem.scala 87:105]
+    node _T_346 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 88:6]
+    node _T_347 = and(_T_346, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 88:21]
+    node redundant_data1_en = or(_T_345, _T_347) @[el2_ifu_iccm_mem.scala 87:121]
+    node _T_348 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 89:49]
+    node _T_349 = bits(redundant_address[1], 0, 0) @[el2_ifu_iccm_mem.scala 89:73]
+    node _T_350 = and(_T_348, _T_349) @[el2_ifu_iccm_mem.scala 89:52]
+    node _T_351 = bits(redundant_address[1], 0, 0) @[el2_ifu_iccm_mem.scala 89:100]
+    node _T_352 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 89:122]
+    node _T_353 = eq(_T_352, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 89:127]
+    node _T_354 = and(_T_351, _T_353) @[el2_ifu_iccm_mem.scala 89:104]
+    node _T_355 = or(_T_350, _T_354) @[el2_ifu_iccm_mem.scala 89:78]
+    node _T_356 = bits(_T_355, 0, 0) @[el2_ifu_iccm_mem.scala 89:137]
+    node _T_357 = bits(io.iccm_wr_data, 77, 39) @[el2_ifu_iccm_mem.scala 90:20]
+    node _T_358 = bits(io.iccm_wr_data, 38, 0) @[el2_ifu_iccm_mem.scala 90:44]
+    node redundant_data1_in = mux(_T_356, _T_357, _T_358) @[el2_ifu_iccm_mem.scala 89:31]
+    node _T_359 = bits(redundant_data1_en, 0, 0) @[el2_ifu_iccm_mem.scala 91:78]
+    reg _T_360 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_359 : @[Reg.scala 28:19]
+      _T_360 <= redundant_data1_in @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    redundant_data[1] <= _T_356 @[el2_ifu_iccm_mem.scala 88:21]
-    node _T_357 = bits(io.iccm_rw_addr, 2, 0) @[el2_ifu_iccm_mem.scala 90:50]
-    reg iccm_rd_addr_lo_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 90:34]
-    iccm_rd_addr_lo_q <= _T_357 @[el2_ifu_iccm_mem.scala 90:34]
-    node _T_358 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 91:48]
-    reg iccm_rd_addr_hi_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 91:34]
-    iccm_rd_addr_hi_q <= _T_358 @[el2_ifu_iccm_mem.scala 91:34]
-    node _T_359 = eq(iccm_rd_addr_hi_q, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 93:86]
-    node _T_360 = bits(iccm_bank_dout_fn_0, 31, 0) @[el2_ifu_iccm_mem.scala 93:115]
-    node _T_361 = eq(iccm_rd_addr_hi_q, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 93:86]
-    node _T_362 = bits(iccm_bank_dout_fn_1, 31, 0) @[el2_ifu_iccm_mem.scala 93:115]
-    node _T_363 = eq(iccm_rd_addr_hi_q, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 93:86]
-    node _T_364 = bits(iccm_bank_dout_fn_2, 31, 0) @[el2_ifu_iccm_mem.scala 93:115]
-    node _T_365 = eq(iccm_rd_addr_hi_q, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 93:86]
-    node _T_366 = bits(iccm_bank_dout_fn_3, 31, 0) @[el2_ifu_iccm_mem.scala 93:115]
-    node _T_367 = mux(_T_359, _T_360, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_368 = mux(_T_361, _T_362, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_369 = mux(_T_363, _T_364, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_370 = mux(_T_365, _T_366, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_371 = or(_T_367, _T_368) @[Mux.scala 27:72]
-    node _T_372 = or(_T_371, _T_369) @[Mux.scala 27:72]
-    node _T_373 = or(_T_372, _T_370) @[Mux.scala 27:72]
-    wire _T_374 : UInt<32> @[Mux.scala 27:72]
-    _T_374 <= _T_373 @[Mux.scala 27:72]
-    node _T_375 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 94:59]
-    node _T_376 = eq(_T_375, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 94:77]
-    node _T_377 = bits(iccm_bank_dout_fn_0, 31, 0) @[el2_ifu_iccm_mem.scala 94:106]
-    node _T_378 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 94:59]
-    node _T_379 = eq(_T_378, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 94:77]
-    node _T_380 = bits(iccm_bank_dout_fn_1, 31, 0) @[el2_ifu_iccm_mem.scala 94:106]
-    node _T_381 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 94:59]
-    node _T_382 = eq(_T_381, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 94:77]
-    node _T_383 = bits(iccm_bank_dout_fn_2, 31, 0) @[el2_ifu_iccm_mem.scala 94:106]
-    node _T_384 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 94:59]
-    node _T_385 = eq(_T_384, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 94:77]
-    node _T_386 = bits(iccm_bank_dout_fn_3, 31, 0) @[el2_ifu_iccm_mem.scala 94:106]
-    node _T_387 = mux(_T_376, _T_377, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_388 = mux(_T_379, _T_380, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_389 = mux(_T_382, _T_383, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_390 = mux(_T_385, _T_386, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_391 = or(_T_387, _T_388) @[Mux.scala 27:72]
-    node _T_392 = or(_T_391, _T_389) @[Mux.scala 27:72]
-    node _T_393 = or(_T_392, _T_390) @[Mux.scala 27:72]
-    wire _T_394 : UInt<32> @[Mux.scala 27:72]
-    _T_394 <= _T_393 @[Mux.scala 27:72]
-    node iccm_rd_data_pre = cat(_T_374, _T_394) @[Cat.scala 29:58]
-    node _T_395 = bits(iccm_rd_addr_lo_q, 0, 0) @[el2_ifu_iccm_mem.scala 95:43]
-    node _T_396 = bits(_T_395, 0, 0) @[el2_ifu_iccm_mem.scala 95:53]
-    node _T_397 = mux(UInt<1>("h00"), UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12]
-    node _T_398 = bits(iccm_rd_data_pre, 63, 16) @[el2_ifu_iccm_mem.scala 95:89]
-    node _T_399 = cat(_T_397, _T_398) @[Cat.scala 29:58]
-    node _T_400 = mux(_T_396, _T_399, iccm_rd_data_pre) @[el2_ifu_iccm_mem.scala 95:25]
-    io.iccm_rd_data <= _T_400 @[el2_ifu_iccm_mem.scala 95:19]
-    node _T_401 = eq(iccm_rd_addr_hi_q, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 96:85]
-    node _T_402 = eq(iccm_rd_addr_hi_q, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 96:85]
-    node _T_403 = eq(iccm_rd_addr_hi_q, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 96:85]
-    node _T_404 = eq(iccm_rd_addr_hi_q, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 96:85]
-    node _T_405 = mux(_T_401, iccm_bank_dout_fn_0, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_406 = mux(_T_402, iccm_bank_dout_fn_1, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_407 = mux(_T_403, iccm_bank_dout_fn_2, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_408 = mux(_T_404, iccm_bank_dout_fn_3, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_409 = or(_T_405, _T_406) @[Mux.scala 27:72]
-    node _T_410 = or(_T_409, _T_407) @[Mux.scala 27:72]
-    node _T_411 = or(_T_410, _T_408) @[Mux.scala 27:72]
-    wire _T_412 : UInt<39> @[Mux.scala 27:72]
-    _T_412 <= _T_411 @[Mux.scala 27:72]
-    node _T_413 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 97:61]
-    node _T_414 = eq(_T_413, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 97:79]
-    node _T_415 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 97:61]
-    node _T_416 = eq(_T_415, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 97:79]
-    node _T_417 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 97:61]
-    node _T_418 = eq(_T_417, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 97:79]
-    node _T_419 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 97:61]
-    node _T_420 = eq(_T_419, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 97:79]
-    node _T_421 = mux(_T_414, iccm_bank_dout_fn_0, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_422 = mux(_T_416, iccm_bank_dout_fn_1, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_423 = mux(_T_418, iccm_bank_dout_fn_2, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_424 = mux(_T_420, iccm_bank_dout_fn_3, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_425 = or(_T_421, _T_422) @[Mux.scala 27:72]
-    node _T_426 = or(_T_425, _T_423) @[Mux.scala 27:72]
-    node _T_427 = or(_T_426, _T_424) @[Mux.scala 27:72]
-    wire _T_428 : UInt<39> @[Mux.scala 27:72]
-    _T_428 <= _T_427 @[Mux.scala 27:72]
-    node _T_429 = cat(_T_412, _T_428) @[Cat.scala 29:58]
-    io.iccm_rd_data_ecc <= _T_429 @[el2_ifu_iccm_mem.scala 96:23]
+    redundant_data[1] <= _T_360 @[el2_ifu_iccm_mem.scala 91:21]
+    node _T_361 = bits(io.iccm_rw_addr, 2, 0) @[el2_ifu_iccm_mem.scala 93:50]
+    reg iccm_rd_addr_lo_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 93:34]
+    iccm_rd_addr_lo_q <= _T_361 @[el2_ifu_iccm_mem.scala 93:34]
+    node _T_362 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 94:48]
+    reg iccm_rd_addr_hi_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 94:34]
+    iccm_rd_addr_hi_q <= _T_362 @[el2_ifu_iccm_mem.scala 94:34]
+    node _T_363 = eq(iccm_rd_addr_hi_q, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 96:86]
+    node _T_364 = bits(iccm_bank_dout_fn_0, 31, 0) @[el2_ifu_iccm_mem.scala 96:115]
+    node _T_365 = eq(iccm_rd_addr_hi_q, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 96:86]
+    node _T_366 = bits(iccm_bank_dout_fn_1, 31, 0) @[el2_ifu_iccm_mem.scala 96:115]
+    node _T_367 = eq(iccm_rd_addr_hi_q, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 96:86]
+    node _T_368 = bits(iccm_bank_dout_fn_2, 31, 0) @[el2_ifu_iccm_mem.scala 96:115]
+    node _T_369 = eq(iccm_rd_addr_hi_q, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 96:86]
+    node _T_370 = bits(iccm_bank_dout_fn_3, 31, 0) @[el2_ifu_iccm_mem.scala 96:115]
+    node _T_371 = mux(_T_363, _T_364, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_372 = mux(_T_365, _T_366, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_373 = mux(_T_367, _T_368, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_374 = mux(_T_369, _T_370, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_375 = or(_T_371, _T_372) @[Mux.scala 27:72]
+    node _T_376 = or(_T_375, _T_373) @[Mux.scala 27:72]
+    node _T_377 = or(_T_376, _T_374) @[Mux.scala 27:72]
+    wire _T_378 : UInt<32> @[Mux.scala 27:72]
+    _T_378 <= _T_377 @[Mux.scala 27:72]
+    node _T_379 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 97:59]
+    node _T_380 = eq(_T_379, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 97:77]
+    node _T_381 = bits(iccm_bank_dout_fn_0, 31, 0) @[el2_ifu_iccm_mem.scala 97:106]
+    node _T_382 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 97:59]
+    node _T_383 = eq(_T_382, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 97:77]
+    node _T_384 = bits(iccm_bank_dout_fn_1, 31, 0) @[el2_ifu_iccm_mem.scala 97:106]
+    node _T_385 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 97:59]
+    node _T_386 = eq(_T_385, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 97:77]
+    node _T_387 = bits(iccm_bank_dout_fn_2, 31, 0) @[el2_ifu_iccm_mem.scala 97:106]
+    node _T_388 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 97:59]
+    node _T_389 = eq(_T_388, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 97:77]
+    node _T_390 = bits(iccm_bank_dout_fn_3, 31, 0) @[el2_ifu_iccm_mem.scala 97:106]
+    node _T_391 = mux(_T_380, _T_381, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_392 = mux(_T_383, _T_384, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_393 = mux(_T_386, _T_387, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_394 = mux(_T_389, _T_390, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_395 = or(_T_391, _T_392) @[Mux.scala 27:72]
+    node _T_396 = or(_T_395, _T_393) @[Mux.scala 27:72]
+    node _T_397 = or(_T_396, _T_394) @[Mux.scala 27:72]
+    wire _T_398 : UInt<32> @[Mux.scala 27:72]
+    _T_398 <= _T_397 @[Mux.scala 27:72]
+    node iccm_rd_data_pre = cat(_T_378, _T_398) @[Cat.scala 29:58]
+    node _T_399 = bits(iccm_rd_addr_lo_q, 0, 0) @[el2_ifu_iccm_mem.scala 98:43]
+    node _T_400 = bits(_T_399, 0, 0) @[el2_ifu_iccm_mem.scala 98:53]
+    node _T_401 = mux(UInt<1>("h00"), UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12]
+    node _T_402 = bits(iccm_rd_data_pre, 63, 16) @[el2_ifu_iccm_mem.scala 98:89]
+    node _T_403 = cat(_T_401, _T_402) @[Cat.scala 29:58]
+    node _T_404 = mux(_T_400, _T_403, iccm_rd_data_pre) @[el2_ifu_iccm_mem.scala 98:25]
+    io.iccm_rd_data <= _T_404 @[el2_ifu_iccm_mem.scala 98:19]
+    node _T_405 = eq(iccm_rd_addr_hi_q, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 99:85]
+    node _T_406 = eq(iccm_rd_addr_hi_q, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 99:85]
+    node _T_407 = eq(iccm_rd_addr_hi_q, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 99:85]
+    node _T_408 = eq(iccm_rd_addr_hi_q, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 99:85]
+    node _T_409 = mux(_T_405, iccm_bank_dout_fn_0, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_410 = mux(_T_406, iccm_bank_dout_fn_1, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_411 = mux(_T_407, iccm_bank_dout_fn_2, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_412 = mux(_T_408, iccm_bank_dout_fn_3, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_413 = or(_T_409, _T_410) @[Mux.scala 27:72]
+    node _T_414 = or(_T_413, _T_411) @[Mux.scala 27:72]
+    node _T_415 = or(_T_414, _T_412) @[Mux.scala 27:72]
+    wire _T_416 : UInt<39> @[Mux.scala 27:72]
+    _T_416 <= _T_415 @[Mux.scala 27:72]
+    node _T_417 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 100:61]
+    node _T_418 = eq(_T_417, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 100:79]
+    node _T_419 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 100:61]
+    node _T_420 = eq(_T_419, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 100:79]
+    node _T_421 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 100:61]
+    node _T_422 = eq(_T_421, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 100:79]
+    node _T_423 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 100:61]
+    node _T_424 = eq(_T_423, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 100:79]
+    node _T_425 = mux(_T_418, iccm_bank_dout_fn_0, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_426 = mux(_T_420, iccm_bank_dout_fn_1, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_427 = mux(_T_422, iccm_bank_dout_fn_2, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_428 = mux(_T_424, iccm_bank_dout_fn_3, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_429 = or(_T_425, _T_426) @[Mux.scala 27:72]
+    node _T_430 = or(_T_429, _T_427) @[Mux.scala 27:72]
+    node _T_431 = or(_T_430, _T_428) @[Mux.scala 27:72]
+    wire _T_432 : UInt<39> @[Mux.scala 27:72]
+    _T_432 <= _T_431 @[Mux.scala 27:72]
+    node _T_433 = cat(_T_416, _T_432) @[Cat.scala 29:58]
+    io.iccm_rd_data_ecc <= _T_433 @[el2_ifu_iccm_mem.scala 99:23]
     
diff --git a/el2_ifu_iccm_mem.v b/el2_ifu_iccm_mem.v
index 9e673bcd..2a0216e0 100644
--- a/el2_ifu_iccm_mem.v
+++ b/el2_ifu_iccm_mem.v
@@ -11,7 +11,11 @@ module el2_ifu_iccm_mem(
   input  [77:0] io_iccm_wr_data,
   output [63:0] io_iccm_rd_data,
   output [77:0] io_iccm_rd_data_ecc,
-  input         io_scan_mode
+  input         io_scan_mode,
+  output [38:0] io_iccm_bank_wr_data_0,
+  output [38:0] io_iccm_bank_wr_data_1,
+  output [38:0] io_iccm_bank_wr_data_2,
+  output [38:0] io_iccm_bank_wr_data_3
 );
 `ifdef RANDOMIZE_MEM_INIT
   reg [63:0] _RAND_0;
@@ -20,94 +24,98 @@ module el2_ifu_iccm_mem(
   reg [63:0] _RAND_3;
 `endif // RANDOMIZE_MEM_INIT
 `ifdef RANDOMIZE_REG_INIT
-  reg [31:0] _RAND_4;
-  reg [31:0] _RAND_5;
-  reg [31:0] _RAND_6;
-  reg [31:0] _RAND_7;
+  reg [63:0] _RAND_4;
+  reg [63:0] _RAND_5;
+  reg [63:0] _RAND_6;
+  reg [63:0] _RAND_7;
   reg [31:0] _RAND_8;
   reg [31:0] _RAND_9;
-  reg [63:0] _RAND_10;
-  reg [63:0] _RAND_11;
+  reg [31:0] _RAND_10;
+  reg [31:0] _RAND_11;
   reg [31:0] _RAND_12;
   reg [31:0] _RAND_13;
-  reg [31:0] _RAND_14;
+  reg [63:0] _RAND_14;
+  reg [63:0] _RAND_15;
+  reg [31:0] _RAND_16;
+  reg [31:0] _RAND_17;
+  reg [31:0] _RAND_18;
 `endif // RANDOMIZE_REG_INIT
-  reg [38:0] iccm_mem_0 [0:4095]; // @[el2_ifu_iccm_mem.scala 40:21]
-  wire [38:0] iccm_mem_0__T_97_data; // @[el2_ifu_iccm_mem.scala 40:21]
-  wire [11:0] iccm_mem_0__T_97_addr; // @[el2_ifu_iccm_mem.scala 40:21]
-  wire [38:0] iccm_mem_0__T_93_data; // @[el2_ifu_iccm_mem.scala 40:21]
-  wire [11:0] iccm_mem_0__T_93_addr; // @[el2_ifu_iccm_mem.scala 40:21]
-  wire  iccm_mem_0__T_93_mask; // @[el2_ifu_iccm_mem.scala 40:21]
-  wire  iccm_mem_0__T_93_en; // @[el2_ifu_iccm_mem.scala 40:21]
-  wire [38:0] iccm_mem_0__T_94_data; // @[el2_ifu_iccm_mem.scala 40:21]
-  wire [11:0] iccm_mem_0__T_94_addr; // @[el2_ifu_iccm_mem.scala 40:21]
-  wire  iccm_mem_0__T_94_mask; // @[el2_ifu_iccm_mem.scala 40:21]
-  wire  iccm_mem_0__T_94_en; // @[el2_ifu_iccm_mem.scala 40:21]
-  wire [38:0] iccm_mem_0__T_95_data; // @[el2_ifu_iccm_mem.scala 40:21]
-  wire [11:0] iccm_mem_0__T_95_addr; // @[el2_ifu_iccm_mem.scala 40:21]
-  wire  iccm_mem_0__T_95_mask; // @[el2_ifu_iccm_mem.scala 40:21]
-  wire  iccm_mem_0__T_95_en; // @[el2_ifu_iccm_mem.scala 40:21]
-  wire [38:0] iccm_mem_0__T_96_data; // @[el2_ifu_iccm_mem.scala 40:21]
-  wire [11:0] iccm_mem_0__T_96_addr; // @[el2_ifu_iccm_mem.scala 40:21]
-  wire  iccm_mem_0__T_96_mask; // @[el2_ifu_iccm_mem.scala 40:21]
-  wire  iccm_mem_0__T_96_en; // @[el2_ifu_iccm_mem.scala 40:21]
-  reg [38:0] iccm_mem_1 [0:4095]; // @[el2_ifu_iccm_mem.scala 40:21]
-  wire [38:0] iccm_mem_1__T_97_data; // @[el2_ifu_iccm_mem.scala 40:21]
-  wire [11:0] iccm_mem_1__T_97_addr; // @[el2_ifu_iccm_mem.scala 40:21]
-  wire [38:0] iccm_mem_1__T_93_data; // @[el2_ifu_iccm_mem.scala 40:21]
-  wire [11:0] iccm_mem_1__T_93_addr; // @[el2_ifu_iccm_mem.scala 40:21]
-  wire  iccm_mem_1__T_93_mask; // @[el2_ifu_iccm_mem.scala 40:21]
-  wire  iccm_mem_1__T_93_en; // @[el2_ifu_iccm_mem.scala 40:21]
-  wire [38:0] iccm_mem_1__T_94_data; // @[el2_ifu_iccm_mem.scala 40:21]
-  wire [11:0] iccm_mem_1__T_94_addr; // @[el2_ifu_iccm_mem.scala 40:21]
-  wire  iccm_mem_1__T_94_mask; // @[el2_ifu_iccm_mem.scala 40:21]
-  wire  iccm_mem_1__T_94_en; // @[el2_ifu_iccm_mem.scala 40:21]
-  wire [38:0] iccm_mem_1__T_95_data; // @[el2_ifu_iccm_mem.scala 40:21]
-  wire [11:0] iccm_mem_1__T_95_addr; // @[el2_ifu_iccm_mem.scala 40:21]
-  wire  iccm_mem_1__T_95_mask; // @[el2_ifu_iccm_mem.scala 40:21]
-  wire  iccm_mem_1__T_95_en; // @[el2_ifu_iccm_mem.scala 40:21]
-  wire [38:0] iccm_mem_1__T_96_data; // @[el2_ifu_iccm_mem.scala 40:21]
-  wire [11:0] iccm_mem_1__T_96_addr; // @[el2_ifu_iccm_mem.scala 40:21]
-  wire  iccm_mem_1__T_96_mask; // @[el2_ifu_iccm_mem.scala 40:21]
-  wire  iccm_mem_1__T_96_en; // @[el2_ifu_iccm_mem.scala 40:21]
-  reg [38:0] iccm_mem_2 [0:4095]; // @[el2_ifu_iccm_mem.scala 40:21]
-  wire [38:0] iccm_mem_2__T_97_data; // @[el2_ifu_iccm_mem.scala 40:21]
-  wire [11:0] iccm_mem_2__T_97_addr; // @[el2_ifu_iccm_mem.scala 40:21]
-  wire [38:0] iccm_mem_2__T_93_data; // @[el2_ifu_iccm_mem.scala 40:21]
-  wire [11:0] iccm_mem_2__T_93_addr; // @[el2_ifu_iccm_mem.scala 40:21]
-  wire  iccm_mem_2__T_93_mask; // @[el2_ifu_iccm_mem.scala 40:21]
-  wire  iccm_mem_2__T_93_en; // @[el2_ifu_iccm_mem.scala 40:21]
-  wire [38:0] iccm_mem_2__T_94_data; // @[el2_ifu_iccm_mem.scala 40:21]
-  wire [11:0] iccm_mem_2__T_94_addr; // @[el2_ifu_iccm_mem.scala 40:21]
-  wire  iccm_mem_2__T_94_mask; // @[el2_ifu_iccm_mem.scala 40:21]
-  wire  iccm_mem_2__T_94_en; // @[el2_ifu_iccm_mem.scala 40:21]
-  wire [38:0] iccm_mem_2__T_95_data; // @[el2_ifu_iccm_mem.scala 40:21]
-  wire [11:0] iccm_mem_2__T_95_addr; // @[el2_ifu_iccm_mem.scala 40:21]
-  wire  iccm_mem_2__T_95_mask; // @[el2_ifu_iccm_mem.scala 40:21]
-  wire  iccm_mem_2__T_95_en; // @[el2_ifu_iccm_mem.scala 40:21]
-  wire [38:0] iccm_mem_2__T_96_data; // @[el2_ifu_iccm_mem.scala 40:21]
-  wire [11:0] iccm_mem_2__T_96_addr; // @[el2_ifu_iccm_mem.scala 40:21]
-  wire  iccm_mem_2__T_96_mask; // @[el2_ifu_iccm_mem.scala 40:21]
-  wire  iccm_mem_2__T_96_en; // @[el2_ifu_iccm_mem.scala 40:21]
-  reg [38:0] iccm_mem_3 [0:4095]; // @[el2_ifu_iccm_mem.scala 40:21]
-  wire [38:0] iccm_mem_3__T_97_data; // @[el2_ifu_iccm_mem.scala 40:21]
-  wire [11:0] iccm_mem_3__T_97_addr; // @[el2_ifu_iccm_mem.scala 40:21]
-  wire [38:0] iccm_mem_3__T_93_data; // @[el2_ifu_iccm_mem.scala 40:21]
-  wire [11:0] iccm_mem_3__T_93_addr; // @[el2_ifu_iccm_mem.scala 40:21]
-  wire  iccm_mem_3__T_93_mask; // @[el2_ifu_iccm_mem.scala 40:21]
-  wire  iccm_mem_3__T_93_en; // @[el2_ifu_iccm_mem.scala 40:21]
-  wire [38:0] iccm_mem_3__T_94_data; // @[el2_ifu_iccm_mem.scala 40:21]
-  wire [11:0] iccm_mem_3__T_94_addr; // @[el2_ifu_iccm_mem.scala 40:21]
-  wire  iccm_mem_3__T_94_mask; // @[el2_ifu_iccm_mem.scala 40:21]
-  wire  iccm_mem_3__T_94_en; // @[el2_ifu_iccm_mem.scala 40:21]
-  wire [38:0] iccm_mem_3__T_95_data; // @[el2_ifu_iccm_mem.scala 40:21]
-  wire [11:0] iccm_mem_3__T_95_addr; // @[el2_ifu_iccm_mem.scala 40:21]
-  wire  iccm_mem_3__T_95_mask; // @[el2_ifu_iccm_mem.scala 40:21]
-  wire  iccm_mem_3__T_95_en; // @[el2_ifu_iccm_mem.scala 40:21]
-  wire [38:0] iccm_mem_3__T_96_data; // @[el2_ifu_iccm_mem.scala 40:21]
-  wire [11:0] iccm_mem_3__T_96_addr; // @[el2_ifu_iccm_mem.scala 40:21]
-  wire  iccm_mem_3__T_96_mask; // @[el2_ifu_iccm_mem.scala 40:21]
-  wire  iccm_mem_3__T_96_en; // @[el2_ifu_iccm_mem.scala 40:21]
+  reg [38:0] iccm_mem_0 [0:4095]; // @[el2_ifu_iccm_mem.scala 41:21]
+  wire [38:0] iccm_mem_0__T_97_data; // @[el2_ifu_iccm_mem.scala 41:21]
+  wire [11:0] iccm_mem_0__T_97_addr; // @[el2_ifu_iccm_mem.scala 41:21]
+  wire [38:0] iccm_mem_0__T_93_data; // @[el2_ifu_iccm_mem.scala 41:21]
+  wire [11:0] iccm_mem_0__T_93_addr; // @[el2_ifu_iccm_mem.scala 41:21]
+  wire  iccm_mem_0__T_93_mask; // @[el2_ifu_iccm_mem.scala 41:21]
+  wire  iccm_mem_0__T_93_en; // @[el2_ifu_iccm_mem.scala 41:21]
+  wire [38:0] iccm_mem_0__T_94_data; // @[el2_ifu_iccm_mem.scala 41:21]
+  wire [11:0] iccm_mem_0__T_94_addr; // @[el2_ifu_iccm_mem.scala 41:21]
+  wire  iccm_mem_0__T_94_mask; // @[el2_ifu_iccm_mem.scala 41:21]
+  wire  iccm_mem_0__T_94_en; // @[el2_ifu_iccm_mem.scala 41:21]
+  wire [38:0] iccm_mem_0__T_95_data; // @[el2_ifu_iccm_mem.scala 41:21]
+  wire [11:0] iccm_mem_0__T_95_addr; // @[el2_ifu_iccm_mem.scala 41:21]
+  wire  iccm_mem_0__T_95_mask; // @[el2_ifu_iccm_mem.scala 41:21]
+  wire  iccm_mem_0__T_95_en; // @[el2_ifu_iccm_mem.scala 41:21]
+  wire [38:0] iccm_mem_0__T_96_data; // @[el2_ifu_iccm_mem.scala 41:21]
+  wire [11:0] iccm_mem_0__T_96_addr; // @[el2_ifu_iccm_mem.scala 41:21]
+  wire  iccm_mem_0__T_96_mask; // @[el2_ifu_iccm_mem.scala 41:21]
+  wire  iccm_mem_0__T_96_en; // @[el2_ifu_iccm_mem.scala 41:21]
+  reg [38:0] iccm_mem_1 [0:4095]; // @[el2_ifu_iccm_mem.scala 41:21]
+  wire [38:0] iccm_mem_1__T_97_data; // @[el2_ifu_iccm_mem.scala 41:21]
+  wire [11:0] iccm_mem_1__T_97_addr; // @[el2_ifu_iccm_mem.scala 41:21]
+  wire [38:0] iccm_mem_1__T_93_data; // @[el2_ifu_iccm_mem.scala 41:21]
+  wire [11:0] iccm_mem_1__T_93_addr; // @[el2_ifu_iccm_mem.scala 41:21]
+  wire  iccm_mem_1__T_93_mask; // @[el2_ifu_iccm_mem.scala 41:21]
+  wire  iccm_mem_1__T_93_en; // @[el2_ifu_iccm_mem.scala 41:21]
+  wire [38:0] iccm_mem_1__T_94_data; // @[el2_ifu_iccm_mem.scala 41:21]
+  wire [11:0] iccm_mem_1__T_94_addr; // @[el2_ifu_iccm_mem.scala 41:21]
+  wire  iccm_mem_1__T_94_mask; // @[el2_ifu_iccm_mem.scala 41:21]
+  wire  iccm_mem_1__T_94_en; // @[el2_ifu_iccm_mem.scala 41:21]
+  wire [38:0] iccm_mem_1__T_95_data; // @[el2_ifu_iccm_mem.scala 41:21]
+  wire [11:0] iccm_mem_1__T_95_addr; // @[el2_ifu_iccm_mem.scala 41:21]
+  wire  iccm_mem_1__T_95_mask; // @[el2_ifu_iccm_mem.scala 41:21]
+  wire  iccm_mem_1__T_95_en; // @[el2_ifu_iccm_mem.scala 41:21]
+  wire [38:0] iccm_mem_1__T_96_data; // @[el2_ifu_iccm_mem.scala 41:21]
+  wire [11:0] iccm_mem_1__T_96_addr; // @[el2_ifu_iccm_mem.scala 41:21]
+  wire  iccm_mem_1__T_96_mask; // @[el2_ifu_iccm_mem.scala 41:21]
+  wire  iccm_mem_1__T_96_en; // @[el2_ifu_iccm_mem.scala 41:21]
+  reg [38:0] iccm_mem_2 [0:4095]; // @[el2_ifu_iccm_mem.scala 41:21]
+  wire [38:0] iccm_mem_2__T_97_data; // @[el2_ifu_iccm_mem.scala 41:21]
+  wire [11:0] iccm_mem_2__T_97_addr; // @[el2_ifu_iccm_mem.scala 41:21]
+  wire [38:0] iccm_mem_2__T_93_data; // @[el2_ifu_iccm_mem.scala 41:21]
+  wire [11:0] iccm_mem_2__T_93_addr; // @[el2_ifu_iccm_mem.scala 41:21]
+  wire  iccm_mem_2__T_93_mask; // @[el2_ifu_iccm_mem.scala 41:21]
+  wire  iccm_mem_2__T_93_en; // @[el2_ifu_iccm_mem.scala 41:21]
+  wire [38:0] iccm_mem_2__T_94_data; // @[el2_ifu_iccm_mem.scala 41:21]
+  wire [11:0] iccm_mem_2__T_94_addr; // @[el2_ifu_iccm_mem.scala 41:21]
+  wire  iccm_mem_2__T_94_mask; // @[el2_ifu_iccm_mem.scala 41:21]
+  wire  iccm_mem_2__T_94_en; // @[el2_ifu_iccm_mem.scala 41:21]
+  wire [38:0] iccm_mem_2__T_95_data; // @[el2_ifu_iccm_mem.scala 41:21]
+  wire [11:0] iccm_mem_2__T_95_addr; // @[el2_ifu_iccm_mem.scala 41:21]
+  wire  iccm_mem_2__T_95_mask; // @[el2_ifu_iccm_mem.scala 41:21]
+  wire  iccm_mem_2__T_95_en; // @[el2_ifu_iccm_mem.scala 41:21]
+  wire [38:0] iccm_mem_2__T_96_data; // @[el2_ifu_iccm_mem.scala 41:21]
+  wire [11:0] iccm_mem_2__T_96_addr; // @[el2_ifu_iccm_mem.scala 41:21]
+  wire  iccm_mem_2__T_96_mask; // @[el2_ifu_iccm_mem.scala 41:21]
+  wire  iccm_mem_2__T_96_en; // @[el2_ifu_iccm_mem.scala 41:21]
+  reg [38:0] iccm_mem_3 [0:4095]; // @[el2_ifu_iccm_mem.scala 41:21]
+  wire [38:0] iccm_mem_3__T_97_data; // @[el2_ifu_iccm_mem.scala 41:21]
+  wire [11:0] iccm_mem_3__T_97_addr; // @[el2_ifu_iccm_mem.scala 41:21]
+  wire [38:0] iccm_mem_3__T_93_data; // @[el2_ifu_iccm_mem.scala 41:21]
+  wire [11:0] iccm_mem_3__T_93_addr; // @[el2_ifu_iccm_mem.scala 41:21]
+  wire  iccm_mem_3__T_93_mask; // @[el2_ifu_iccm_mem.scala 41:21]
+  wire  iccm_mem_3__T_93_en; // @[el2_ifu_iccm_mem.scala 41:21]
+  wire [38:0] iccm_mem_3__T_94_data; // @[el2_ifu_iccm_mem.scala 41:21]
+  wire [11:0] iccm_mem_3__T_94_addr; // @[el2_ifu_iccm_mem.scala 41:21]
+  wire  iccm_mem_3__T_94_mask; // @[el2_ifu_iccm_mem.scala 41:21]
+  wire  iccm_mem_3__T_94_en; // @[el2_ifu_iccm_mem.scala 41:21]
+  wire [38:0] iccm_mem_3__T_95_data; // @[el2_ifu_iccm_mem.scala 41:21]
+  wire [11:0] iccm_mem_3__T_95_addr; // @[el2_ifu_iccm_mem.scala 41:21]
+  wire  iccm_mem_3__T_95_mask; // @[el2_ifu_iccm_mem.scala 41:21]
+  wire  iccm_mem_3__T_95_en; // @[el2_ifu_iccm_mem.scala 41:21]
+  wire [38:0] iccm_mem_3__T_96_data; // @[el2_ifu_iccm_mem.scala 41:21]
+  wire [11:0] iccm_mem_3__T_96_addr; // @[el2_ifu_iccm_mem.scala 41:21]
+  wire  iccm_mem_3__T_96_mask; // @[el2_ifu_iccm_mem.scala 41:21]
+  wire  iccm_mem_3__T_96_en; // @[el2_ifu_iccm_mem.scala 41:21]
   wire  _T_1 = io_iccm_wr_size[1:0] == 2'h3; // @[el2_ifu_iccm_mem.scala 24:43]
   wire [1:0] addr_inc = _T_1 ? 2'h2 : 2'h1; // @[el2_ifu_iccm_mem.scala 24:21]
   wire [14:0] _GEN_15 = {{13'd0}, addr_inc}; // @[el2_ifu_iccm_mem.scala 25:54]
@@ -130,181 +138,181 @@ module el2_ifu_iccm_mem(
   wire  _T_26 = io_iccm_wren & _T_25; // @[el2_ifu_iccm_mem.scala 33:64]
   wire  _T_28 = addr_bank_inc[2:1] == 2'h3; // @[el2_ifu_iccm_mem.scala 33:139]
   wire  wren_bank_3 = _T_26 | _T_28; // @[el2_ifu_iccm_mem.scala 33:106]
-  wire  _T_31 = io_iccm_rden & _T_10; // @[el2_ifu_iccm_mem.scala 35:64]
-  wire  rden_bank_0 = _T_31 | _T_13; // @[el2_ifu_iccm_mem.scala 35:106]
-  wire  _T_36 = io_iccm_rden & _T_15; // @[el2_ifu_iccm_mem.scala 35:64]
-  wire  rden_bank_1 = _T_36 | _T_18; // @[el2_ifu_iccm_mem.scala 35:106]
-  wire  _T_41 = io_iccm_rden & _T_20; // @[el2_ifu_iccm_mem.scala 35:64]
-  wire  rden_bank_2 = _T_41 | _T_23; // @[el2_ifu_iccm_mem.scala 35:106]
-  wire  _T_46 = io_iccm_rden & _T_25; // @[el2_ifu_iccm_mem.scala 35:64]
-  wire  rden_bank_3 = _T_46 | _T_28; // @[el2_ifu_iccm_mem.scala 35:106]
-  wire  _T_49 = wren_bank_0 | rden_bank_0; // @[el2_ifu_iccm_mem.scala 36:72]
-  wire  iccm_clken_0 = _T_49 | io_clk_override; // @[el2_ifu_iccm_mem.scala 36:87]
-  wire  _T_50 = wren_bank_1 | rden_bank_1; // @[el2_ifu_iccm_mem.scala 36:72]
-  wire  iccm_clken_1 = _T_50 | io_clk_override; // @[el2_ifu_iccm_mem.scala 36:87]
-  wire  _T_51 = wren_bank_2 | rden_bank_2; // @[el2_ifu_iccm_mem.scala 36:72]
-  wire  iccm_clken_2 = _T_51 | io_clk_override; // @[el2_ifu_iccm_mem.scala 36:87]
-  wire  _T_52 = wren_bank_3 | rden_bank_3; // @[el2_ifu_iccm_mem.scala 36:72]
-  wire  iccm_clken_3 = _T_52 | io_clk_override; // @[el2_ifu_iccm_mem.scala 36:87]
-  wire [11:0] _T_59 = _T_13 ? addr_bank_inc[14:3] : io_iccm_rw_addr[14:3]; // @[el2_ifu_iccm_mem.scala 38:8]
-  wire [11:0] _T_66 = _T_18 ? addr_bank_inc[14:3] : io_iccm_rw_addr[14:3]; // @[el2_ifu_iccm_mem.scala 38:8]
-  wire [11:0] _T_73 = _T_23 ? addr_bank_inc[14:3] : io_iccm_rw_addr[14:3]; // @[el2_ifu_iccm_mem.scala 38:8]
-  wire [11:0] _T_80 = _T_28 ? addr_bank_inc[14:3] : io_iccm_rw_addr[14:3]; // @[el2_ifu_iccm_mem.scala 38:8]
-  reg  _T_298; // @[Reg.scala 27:20]
-  reg  _T_299; // @[Reg.scala 27:20]
-  wire [1:0] redundant_valid = {_T_298,_T_299}; // @[Cat.scala 29:58]
+  wire  _T_31 = io_iccm_rden & _T_10; // @[el2_ifu_iccm_mem.scala 36:64]
+  wire  rden_bank_0 = _T_31 | _T_13; // @[el2_ifu_iccm_mem.scala 36:106]
+  wire  _T_36 = io_iccm_rden & _T_15; // @[el2_ifu_iccm_mem.scala 36:64]
+  wire  rden_bank_1 = _T_36 | _T_18; // @[el2_ifu_iccm_mem.scala 36:106]
+  wire  _T_41 = io_iccm_rden & _T_20; // @[el2_ifu_iccm_mem.scala 36:64]
+  wire  rden_bank_2 = _T_41 | _T_23; // @[el2_ifu_iccm_mem.scala 36:106]
+  wire  _T_46 = io_iccm_rden & _T_25; // @[el2_ifu_iccm_mem.scala 36:64]
+  wire  rden_bank_3 = _T_46 | _T_28; // @[el2_ifu_iccm_mem.scala 36:106]
+  wire  _T_49 = wren_bank_0 | rden_bank_0; // @[el2_ifu_iccm_mem.scala 37:72]
+  wire  iccm_clken_0 = _T_49 | io_clk_override; // @[el2_ifu_iccm_mem.scala 37:87]
+  wire  _T_50 = wren_bank_1 | rden_bank_1; // @[el2_ifu_iccm_mem.scala 37:72]
+  wire  iccm_clken_1 = _T_50 | io_clk_override; // @[el2_ifu_iccm_mem.scala 37:87]
+  wire  _T_51 = wren_bank_2 | rden_bank_2; // @[el2_ifu_iccm_mem.scala 37:72]
+  wire  iccm_clken_2 = _T_51 | io_clk_override; // @[el2_ifu_iccm_mem.scala 37:87]
+  wire  _T_52 = wren_bank_3 | rden_bank_3; // @[el2_ifu_iccm_mem.scala 37:72]
+  wire  iccm_clken_3 = _T_52 | io_clk_override; // @[el2_ifu_iccm_mem.scala 37:87]
+  wire [11:0] _T_59 = _T_13 ? addr_bank_inc[14:3] : io_iccm_rw_addr[14:3]; // @[el2_ifu_iccm_mem.scala 39:8]
+  wire [11:0] _T_66 = _T_18 ? addr_bank_inc[14:3] : io_iccm_rw_addr[14:3]; // @[el2_ifu_iccm_mem.scala 39:8]
+  wire [11:0] _T_73 = _T_23 ? addr_bank_inc[14:3] : io_iccm_rw_addr[14:3]; // @[el2_ifu_iccm_mem.scala 39:8]
+  wire [11:0] _T_80 = _T_28 ? addr_bank_inc[14:3] : io_iccm_rw_addr[14:3]; // @[el2_ifu_iccm_mem.scala 39:8]
+  reg [38:0] iccm_bank_dout_0; // @[el2_ifu_iccm_mem.scala 50:62]
+  reg [38:0] iccm_bank_dout_1; // @[el2_ifu_iccm_mem.scala 50:62]
+  reg [38:0] iccm_bank_dout_2; // @[el2_ifu_iccm_mem.scala 50:62]
+  reg [38:0] iccm_bank_dout_3; // @[el2_ifu_iccm_mem.scala 50:62]
+  reg  _T_302; // @[Reg.scala 27:20]
+  reg  _T_303; // @[Reg.scala 27:20]
+  wire [1:0] redundant_valid = {_T_302,_T_303}; // @[Cat.scala 29:58]
   reg [13:0] redundant_address_1; // @[Reg.scala 27:20]
-  wire  _T_101 = io_iccm_rw_addr[14:1] == redundant_address_1; // @[el2_ifu_iccm_mem.scala 53:105]
-  wire  _T_104 = _T_101 & _T_10; // @[el2_ifu_iccm_mem.scala 53:145]
-  wire  _T_105 = redundant_valid[1] & _T_104; // @[el2_ifu_iccm_mem.scala 53:71]
-  wire  _T_108 = addr_bank_inc[14:1] == redundant_address_1; // @[el2_ifu_iccm_mem.scala 54:37]
-  wire  _T_111 = _T_108 & _T_13; // @[el2_ifu_iccm_mem.scala 54:77]
-  wire  _T_112 = _T_105 | _T_111; // @[el2_ifu_iccm_mem.scala 53:179]
-  wire  _T_119 = _T_101 & _T_15; // @[el2_ifu_iccm_mem.scala 53:145]
-  wire  _T_120 = redundant_valid[1] & _T_119; // @[el2_ifu_iccm_mem.scala 53:71]
-  wire  _T_126 = _T_108 & _T_18; // @[el2_ifu_iccm_mem.scala 54:77]
-  wire  _T_127 = _T_120 | _T_126; // @[el2_ifu_iccm_mem.scala 53:179]
-  wire  _T_134 = _T_101 & _T_20; // @[el2_ifu_iccm_mem.scala 53:145]
-  wire  _T_135 = redundant_valid[1] & _T_134; // @[el2_ifu_iccm_mem.scala 53:71]
-  wire  _T_141 = _T_108 & _T_23; // @[el2_ifu_iccm_mem.scala 54:77]
-  wire  _T_142 = _T_135 | _T_141; // @[el2_ifu_iccm_mem.scala 53:179]
-  wire  _T_149 = _T_101 & _T_25; // @[el2_ifu_iccm_mem.scala 53:145]
-  wire  _T_150 = redundant_valid[1] & _T_149; // @[el2_ifu_iccm_mem.scala 53:71]
-  wire  _T_156 = _T_108 & _T_28; // @[el2_ifu_iccm_mem.scala 54:77]
-  wire  _T_157 = _T_150 | _T_156; // @[el2_ifu_iccm_mem.scala 53:179]
-  wire [3:0] sel_red1 = {_T_157,_T_142,_T_127,_T_112}; // @[Cat.scala 29:58]
+  wire  _T_105 = io_iccm_rw_addr[14:1] == redundant_address_1; // @[el2_ifu_iccm_mem.scala 56:105]
+  wire  _T_108 = _T_105 & _T_10; // @[el2_ifu_iccm_mem.scala 56:145]
+  wire  _T_109 = redundant_valid[1] & _T_108; // @[el2_ifu_iccm_mem.scala 56:71]
+  wire  _T_112 = addr_bank_inc[14:1] == redundant_address_1; // @[el2_ifu_iccm_mem.scala 57:37]
+  wire  _T_115 = _T_112 & _T_13; // @[el2_ifu_iccm_mem.scala 57:77]
+  wire  _T_116 = _T_109 | _T_115; // @[el2_ifu_iccm_mem.scala 56:179]
+  wire  _T_123 = _T_105 & _T_15; // @[el2_ifu_iccm_mem.scala 56:145]
+  wire  _T_124 = redundant_valid[1] & _T_123; // @[el2_ifu_iccm_mem.scala 56:71]
+  wire  _T_130 = _T_112 & _T_18; // @[el2_ifu_iccm_mem.scala 57:77]
+  wire  _T_131 = _T_124 | _T_130; // @[el2_ifu_iccm_mem.scala 56:179]
+  wire  _T_138 = _T_105 & _T_20; // @[el2_ifu_iccm_mem.scala 56:145]
+  wire  _T_139 = redundant_valid[1] & _T_138; // @[el2_ifu_iccm_mem.scala 56:71]
+  wire  _T_145 = _T_112 & _T_23; // @[el2_ifu_iccm_mem.scala 57:77]
+  wire  _T_146 = _T_139 | _T_145; // @[el2_ifu_iccm_mem.scala 56:179]
+  wire  _T_153 = _T_105 & _T_25; // @[el2_ifu_iccm_mem.scala 56:145]
+  wire  _T_154 = redundant_valid[1] & _T_153; // @[el2_ifu_iccm_mem.scala 56:71]
+  wire  _T_160 = _T_112 & _T_28; // @[el2_ifu_iccm_mem.scala 57:77]
+  wire  _T_161 = _T_154 | _T_160; // @[el2_ifu_iccm_mem.scala 56:179]
+  wire [3:0] sel_red1 = {_T_161,_T_146,_T_131,_T_116}; // @[Cat.scala 29:58]
   reg [13:0] redundant_address_0; // @[Reg.scala 27:20]
-  wire  _T_163 = io_iccm_rw_addr[14:1] == redundant_address_0; // @[el2_ifu_iccm_mem.scala 55:105]
-  wire  _T_166 = _T_163 & _T_10; // @[el2_ifu_iccm_mem.scala 55:145]
-  wire  _T_167 = redundant_valid[0] & _T_166; // @[el2_ifu_iccm_mem.scala 55:71]
-  wire  _T_170 = addr_bank_inc[14:1] == redundant_address_0; // @[el2_ifu_iccm_mem.scala 56:37]
-  wire  _T_173 = _T_170 & _T_13; // @[el2_ifu_iccm_mem.scala 56:77]
-  wire  _T_174 = _T_167 | _T_173; // @[el2_ifu_iccm_mem.scala 55:179]
-  wire  _T_181 = _T_163 & _T_15; // @[el2_ifu_iccm_mem.scala 55:145]
-  wire  _T_182 = redundant_valid[0] & _T_181; // @[el2_ifu_iccm_mem.scala 55:71]
-  wire  _T_188 = _T_170 & _T_18; // @[el2_ifu_iccm_mem.scala 56:77]
-  wire  _T_189 = _T_182 | _T_188; // @[el2_ifu_iccm_mem.scala 55:179]
-  wire  _T_196 = _T_163 & _T_20; // @[el2_ifu_iccm_mem.scala 55:145]
-  wire  _T_197 = redundant_valid[0] & _T_196; // @[el2_ifu_iccm_mem.scala 55:71]
-  wire  _T_203 = _T_170 & _T_23; // @[el2_ifu_iccm_mem.scala 56:77]
-  wire  _T_204 = _T_197 | _T_203; // @[el2_ifu_iccm_mem.scala 55:179]
-  wire  _T_211 = _T_163 & _T_25; // @[el2_ifu_iccm_mem.scala 55:145]
-  wire  _T_212 = redundant_valid[0] & _T_211; // @[el2_ifu_iccm_mem.scala 55:71]
-  wire  _T_218 = _T_170 & _T_28; // @[el2_ifu_iccm_mem.scala 56:77]
-  wire  _T_219 = _T_212 | _T_218; // @[el2_ifu_iccm_mem.scala 55:179]
-  wire [3:0] sel_red0 = {_T_219,_T_204,_T_189,_T_174}; // @[Cat.scala 29:58]
-  reg [3:0] sel_red0_q; // @[el2_ifu_iccm_mem.scala 58:27]
-  reg [3:0] sel_red1_q; // @[el2_ifu_iccm_mem.scala 59:27]
-  wire  _T_227 = ~sel_red0_q[0]; // @[el2_ifu_iccm_mem.scala 65:36]
-  wire  _T_229 = ~sel_red1_q[0]; // @[el2_ifu_iccm_mem.scala 65:53]
-  wire  _T_230 = _T_227 & _T_229; // @[el2_ifu_iccm_mem.scala 65:51]
+  wire  _T_167 = io_iccm_rw_addr[14:1] == redundant_address_0; // @[el2_ifu_iccm_mem.scala 58:105]
+  wire  _T_170 = _T_167 & _T_10; // @[el2_ifu_iccm_mem.scala 58:145]
+  wire  _T_171 = redundant_valid[0] & _T_170; // @[el2_ifu_iccm_mem.scala 58:71]
+  wire  _T_174 = addr_bank_inc[14:1] == redundant_address_0; // @[el2_ifu_iccm_mem.scala 59:37]
+  wire  _T_177 = _T_174 & _T_13; // @[el2_ifu_iccm_mem.scala 59:77]
+  wire  _T_178 = _T_171 | _T_177; // @[el2_ifu_iccm_mem.scala 58:179]
+  wire  _T_185 = _T_167 & _T_15; // @[el2_ifu_iccm_mem.scala 58:145]
+  wire  _T_186 = redundant_valid[0] & _T_185; // @[el2_ifu_iccm_mem.scala 58:71]
+  wire  _T_192 = _T_174 & _T_18; // @[el2_ifu_iccm_mem.scala 59:77]
+  wire  _T_193 = _T_186 | _T_192; // @[el2_ifu_iccm_mem.scala 58:179]
+  wire  _T_200 = _T_167 & _T_20; // @[el2_ifu_iccm_mem.scala 58:145]
+  wire  _T_201 = redundant_valid[0] & _T_200; // @[el2_ifu_iccm_mem.scala 58:71]
+  wire  _T_207 = _T_174 & _T_23; // @[el2_ifu_iccm_mem.scala 59:77]
+  wire  _T_208 = _T_201 | _T_207; // @[el2_ifu_iccm_mem.scala 58:179]
+  wire  _T_215 = _T_167 & _T_25; // @[el2_ifu_iccm_mem.scala 58:145]
+  wire  _T_216 = redundant_valid[0] & _T_215; // @[el2_ifu_iccm_mem.scala 58:71]
+  wire  _T_222 = _T_174 & _T_28; // @[el2_ifu_iccm_mem.scala 59:77]
+  wire  _T_223 = _T_216 | _T_222; // @[el2_ifu_iccm_mem.scala 58:179]
+  wire [3:0] sel_red0 = {_T_223,_T_208,_T_193,_T_178}; // @[Cat.scala 29:58]
+  reg [3:0] sel_red0_q; // @[el2_ifu_iccm_mem.scala 61:27]
+  reg [3:0] sel_red1_q; // @[el2_ifu_iccm_mem.scala 62:27]
+  wire  _T_231 = ~sel_red0_q[0]; // @[el2_ifu_iccm_mem.scala 68:36]
+  wire  _T_233 = ~sel_red1_q[0]; // @[el2_ifu_iccm_mem.scala 68:53]
+  wire  _T_234 = _T_231 & _T_233; // @[el2_ifu_iccm_mem.scala 68:51]
   reg [38:0] redundant_data_1; // @[Reg.scala 27:20]
-  wire [38:0] _T_232 = sel_red1_q[0] ? redundant_data_1 : 39'h0; // @[Mux.scala 27:72]
+  wire [38:0] _T_236 = sel_red1_q[0] ? redundant_data_1 : 39'h0; // @[Mux.scala 27:72]
   reg [38:0] redundant_data_0; // @[Reg.scala 27:20]
-  wire [38:0] _T_233 = sel_red0_q[0] ? redundant_data_0 : 39'h0; // @[Mux.scala 27:72]
-  wire [38:0] iccm_bank_dout_0 = iccm_mem_0__T_97_data; // @[el2_ifu_iccm_mem.scala 45:28 el2_ifu_iccm_mem.scala 47:18]
-  wire [38:0] _T_234 = _T_230 ? iccm_bank_dout_0 : 39'h0; // @[Mux.scala 27:72]
-  wire [38:0] _T_235 = _T_232 | _T_233; // @[Mux.scala 27:72]
-  wire [38:0] iccm_bank_dout_fn_0 = _T_235 | _T_234; // @[Mux.scala 27:72]
-  wire  _T_242 = ~sel_red0_q[1]; // @[el2_ifu_iccm_mem.scala 65:36]
-  wire  _T_244 = ~sel_red1_q[1]; // @[el2_ifu_iccm_mem.scala 65:53]
-  wire  _T_245 = _T_242 & _T_244; // @[el2_ifu_iccm_mem.scala 65:51]
-  wire [38:0] _T_247 = sel_red1_q[1] ? redundant_data_1 : 39'h0; // @[Mux.scala 27:72]
-  wire [38:0] _T_248 = sel_red0_q[1] ? redundant_data_0 : 39'h0; // @[Mux.scala 27:72]
-  wire [38:0] iccm_bank_dout_1 = iccm_mem_1__T_97_data; // @[el2_ifu_iccm_mem.scala 45:28 el2_ifu_iccm_mem.scala 47:18]
-  wire [38:0] _T_249 = _T_245 ? iccm_bank_dout_1 : 39'h0; // @[Mux.scala 27:72]
-  wire [38:0] _T_250 = _T_247 | _T_248; // @[Mux.scala 27:72]
-  wire [38:0] iccm_bank_dout_fn_1 = _T_250 | _T_249; // @[Mux.scala 27:72]
-  wire  _T_257 = ~sel_red0_q[2]; // @[el2_ifu_iccm_mem.scala 65:36]
-  wire  _T_259 = ~sel_red1_q[2]; // @[el2_ifu_iccm_mem.scala 65:53]
-  wire  _T_260 = _T_257 & _T_259; // @[el2_ifu_iccm_mem.scala 65:51]
-  wire [38:0] _T_262 = sel_red1_q[2] ? redundant_data_1 : 39'h0; // @[Mux.scala 27:72]
-  wire [38:0] _T_263 = sel_red0_q[2] ? redundant_data_0 : 39'h0; // @[Mux.scala 27:72]
-  wire [38:0] iccm_bank_dout_2 = iccm_mem_2__T_97_data; // @[el2_ifu_iccm_mem.scala 45:28 el2_ifu_iccm_mem.scala 47:18]
-  wire [38:0] _T_264 = _T_260 ? iccm_bank_dout_2 : 39'h0; // @[Mux.scala 27:72]
-  wire [38:0] _T_265 = _T_262 | _T_263; // @[Mux.scala 27:72]
-  wire [38:0] iccm_bank_dout_fn_2 = _T_265 | _T_264; // @[Mux.scala 27:72]
-  wire  _T_272 = ~sel_red0_q[3]; // @[el2_ifu_iccm_mem.scala 65:36]
-  wire  _T_274 = ~sel_red1_q[3]; // @[el2_ifu_iccm_mem.scala 65:53]
-  wire  _T_275 = _T_272 & _T_274; // @[el2_ifu_iccm_mem.scala 65:51]
-  wire [38:0] _T_277 = sel_red1_q[3] ? redundant_data_1 : 39'h0; // @[Mux.scala 27:72]
-  wire [38:0] _T_278 = sel_red0_q[3] ? redundant_data_0 : 39'h0; // @[Mux.scala 27:72]
-  wire [38:0] iccm_bank_dout_3 = iccm_mem_3__T_97_data; // @[el2_ifu_iccm_mem.scala 45:28 el2_ifu_iccm_mem.scala 47:18]
-  wire [38:0] _T_279 = _T_275 ? iccm_bank_dout_3 : 39'h0; // @[Mux.scala 27:72]
-  wire [38:0] _T_280 = _T_277 | _T_278; // @[Mux.scala 27:72]
-  wire [38:0] iccm_bank_dout_fn_3 = _T_280 | _T_279; // @[Mux.scala 27:72]
+  wire [38:0] _T_237 = sel_red0_q[0] ? redundant_data_0 : 39'h0; // @[Mux.scala 27:72]
+  wire [38:0] _T_238 = _T_234 ? iccm_bank_dout_0 : 39'h0; // @[Mux.scala 27:72]
+  wire [38:0] _T_239 = _T_236 | _T_237; // @[Mux.scala 27:72]
+  wire [38:0] iccm_bank_dout_fn_0 = _T_239 | _T_238; // @[Mux.scala 27:72]
+  wire  _T_246 = ~sel_red0_q[1]; // @[el2_ifu_iccm_mem.scala 68:36]
+  wire  _T_248 = ~sel_red1_q[1]; // @[el2_ifu_iccm_mem.scala 68:53]
+  wire  _T_249 = _T_246 & _T_248; // @[el2_ifu_iccm_mem.scala 68:51]
+  wire [38:0] _T_251 = sel_red1_q[1] ? redundant_data_1 : 39'h0; // @[Mux.scala 27:72]
+  wire [38:0] _T_252 = sel_red0_q[1] ? redundant_data_0 : 39'h0; // @[Mux.scala 27:72]
+  wire [38:0] _T_253 = _T_249 ? iccm_bank_dout_1 : 39'h0; // @[Mux.scala 27:72]
+  wire [38:0] _T_254 = _T_251 | _T_252; // @[Mux.scala 27:72]
+  wire [38:0] iccm_bank_dout_fn_1 = _T_254 | _T_253; // @[Mux.scala 27:72]
+  wire  _T_261 = ~sel_red0_q[2]; // @[el2_ifu_iccm_mem.scala 68:36]
+  wire  _T_263 = ~sel_red1_q[2]; // @[el2_ifu_iccm_mem.scala 68:53]
+  wire  _T_264 = _T_261 & _T_263; // @[el2_ifu_iccm_mem.scala 68:51]
+  wire [38:0] _T_266 = sel_red1_q[2] ? redundant_data_1 : 39'h0; // @[Mux.scala 27:72]
+  wire [38:0] _T_267 = sel_red0_q[2] ? redundant_data_0 : 39'h0; // @[Mux.scala 27:72]
+  wire [38:0] _T_268 = _T_264 ? iccm_bank_dout_2 : 39'h0; // @[Mux.scala 27:72]
+  wire [38:0] _T_269 = _T_266 | _T_267; // @[Mux.scala 27:72]
+  wire [38:0] iccm_bank_dout_fn_2 = _T_269 | _T_268; // @[Mux.scala 27:72]
+  wire  _T_276 = ~sel_red0_q[3]; // @[el2_ifu_iccm_mem.scala 68:36]
+  wire  _T_278 = ~sel_red1_q[3]; // @[el2_ifu_iccm_mem.scala 68:53]
+  wire  _T_279 = _T_276 & _T_278; // @[el2_ifu_iccm_mem.scala 68:51]
+  wire [38:0] _T_281 = sel_red1_q[3] ? redundant_data_1 : 39'h0; // @[Mux.scala 27:72]
+  wire [38:0] _T_282 = sel_red0_q[3] ? redundant_data_0 : 39'h0; // @[Mux.scala 27:72]
+  wire [38:0] _T_283 = _T_279 ? iccm_bank_dout_3 : 39'h0; // @[Mux.scala 27:72]
+  wire [38:0] _T_284 = _T_281 | _T_282; // @[Mux.scala 27:72]
+  wire [38:0] iccm_bank_dout_fn_3 = _T_284 | _T_283; // @[Mux.scala 27:72]
   reg  redundant_lru; // @[Reg.scala 27:20]
-  wire  _T_282 = ~redundant_lru; // @[el2_ifu_iccm_mem.scala 67:20]
-  wire  r0_addr_en = _T_282 & io_iccm_buf_correct_ecc; // @[el2_ifu_iccm_mem.scala 67:35]
-  wire  r1_addr_en = redundant_lru & io_iccm_buf_correct_ecc; // @[el2_ifu_iccm_mem.scala 68:35]
-  wire  _T_283 = |sel_red0; // @[el2_ifu_iccm_mem.scala 69:63]
-  wire  _T_284 = |sel_red1; // @[el2_ifu_iccm_mem.scala 69:78]
-  wire  _T_285 = _T_283 | _T_284; // @[el2_ifu_iccm_mem.scala 69:67]
-  wire  _T_286 = _T_285 & io_iccm_rden; // @[el2_ifu_iccm_mem.scala 69:83]
-  wire  _T_287 = _T_286 & io_iccm_correction_state; // @[el2_ifu_iccm_mem.scala 69:98]
-  wire  redundant_lru_en = io_iccm_buf_correct_ecc | _T_287; // @[el2_ifu_iccm_mem.scala 69:50]
-  wire  _GEN_11 = r1_addr_en | _T_298; // @[Reg.scala 28:19]
-  wire  _GEN_12 = r0_addr_en | _T_299; // @[Reg.scala 28:19]
-  wire  _T_303 = io_iccm_rw_addr[14:2] == redundant_address_0[13:1]; // @[el2_ifu_iccm_mem.scala 76:61]
-  wire  _T_306 = io_iccm_rw_addr[1] & redundant_address_0[0]; // @[el2_ifu_iccm_mem.scala 77:26]
-  wire  _T_309 = _T_306 | _T_1; // @[el2_ifu_iccm_mem.scala 77:52]
-  wire  _T_310 = _T_303 & _T_309; // @[el2_ifu_iccm_mem.scala 76:102]
-  wire  _T_312 = _T_310 & redundant_valid[0]; // @[el2_ifu_iccm_mem.scala 77:84]
-  wire  _T_313 = _T_312 & io_iccm_wren; // @[el2_ifu_iccm_mem.scala 77:105]
-  wire  redundant_data0_en = _T_313 | r0_addr_en; // @[el2_ifu_iccm_mem.scala 77:121]
-  wire  _T_322 = redundant_address_0[0] & _T_1; // @[el2_ifu_iccm_mem.scala 79:104]
-  wire  _T_323 = _T_306 | _T_322; // @[el2_ifu_iccm_mem.scala 79:78]
-  wire  _T_331 = io_iccm_rw_addr[14:2] == redundant_address_1[13:1]; // @[el2_ifu_iccm_mem.scala 83:61]
-  wire  _T_334 = io_iccm_rw_addr[1] & redundant_address_1[0]; // @[el2_ifu_iccm_mem.scala 84:26]
-  wire  _T_337 = _T_334 | _T_1; // @[el2_ifu_iccm_mem.scala 84:52]
-  wire  _T_338 = _T_331 & _T_337; // @[el2_ifu_iccm_mem.scala 83:102]
-  wire  _T_340 = _T_338 & redundant_valid[1]; // @[el2_ifu_iccm_mem.scala 84:84]
-  wire  _T_341 = _T_340 & io_iccm_wren; // @[el2_ifu_iccm_mem.scala 84:105]
-  wire  redundant_data1_en = _T_341 | r0_addr_en; // @[el2_ifu_iccm_mem.scala 84:121]
-  wire  _T_350 = redundant_address_1[0] & _T_1; // @[el2_ifu_iccm_mem.scala 86:104]
-  wire  _T_351 = _T_334 | _T_350; // @[el2_ifu_iccm_mem.scala 86:78]
-  reg [2:0] iccm_rd_addr_lo_q; // @[el2_ifu_iccm_mem.scala 90:34]
-  reg [1:0] iccm_rd_addr_hi_q; // @[el2_ifu_iccm_mem.scala 91:34]
-  wire  _T_359 = iccm_rd_addr_hi_q == 2'h0; // @[el2_ifu_iccm_mem.scala 93:86]
-  wire  _T_361 = iccm_rd_addr_hi_q == 2'h1; // @[el2_ifu_iccm_mem.scala 93:86]
-  wire  _T_363 = iccm_rd_addr_hi_q == 2'h2; // @[el2_ifu_iccm_mem.scala 93:86]
-  wire  _T_365 = iccm_rd_addr_hi_q == 2'h3; // @[el2_ifu_iccm_mem.scala 93:86]
-  wire [31:0] _T_367 = _T_359 ? iccm_bank_dout_fn_0[31:0] : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_368 = _T_361 ? iccm_bank_dout_fn_1[31:0] : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_369 = _T_363 ? iccm_bank_dout_fn_2[31:0] : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_370 = _T_365 ? iccm_bank_dout_fn_3[31:0] : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_371 = _T_367 | _T_368; // @[Mux.scala 27:72]
-  wire [31:0] _T_372 = _T_371 | _T_369; // @[Mux.scala 27:72]
-  wire [31:0] _T_373 = _T_372 | _T_370; // @[Mux.scala 27:72]
-  wire  _T_376 = iccm_rd_addr_lo_q[1:0] == 2'h0; // @[el2_ifu_iccm_mem.scala 94:77]
-  wire  _T_379 = iccm_rd_addr_lo_q[1:0] == 2'h1; // @[el2_ifu_iccm_mem.scala 94:77]
-  wire  _T_382 = iccm_rd_addr_lo_q[1:0] == 2'h2; // @[el2_ifu_iccm_mem.scala 94:77]
-  wire  _T_385 = iccm_rd_addr_lo_q[1:0] == 2'h3; // @[el2_ifu_iccm_mem.scala 94:77]
-  wire [31:0] _T_387 = _T_376 ? iccm_bank_dout_fn_0[31:0] : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_388 = _T_379 ? iccm_bank_dout_fn_1[31:0] : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_389 = _T_382 ? iccm_bank_dout_fn_2[31:0] : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_390 = _T_385 ? iccm_bank_dout_fn_3[31:0] : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_391 = _T_387 | _T_388; // @[Mux.scala 27:72]
-  wire [31:0] _T_392 = _T_391 | _T_389; // @[Mux.scala 27:72]
-  wire [31:0] _T_393 = _T_392 | _T_390; // @[Mux.scala 27:72]
-  wire [63:0] iccm_rd_data_pre = {_T_373,_T_393}; // @[Cat.scala 29:58]
-  wire [63:0] _T_399 = {16'h0,iccm_rd_data_pre[63:16]}; // @[Cat.scala 29:58]
-  wire [38:0] _T_405 = _T_359 ? iccm_bank_dout_fn_0 : 39'h0; // @[Mux.scala 27:72]
-  wire [38:0] _T_406 = _T_361 ? iccm_bank_dout_fn_1 : 39'h0; // @[Mux.scala 27:72]
-  wire [38:0] _T_407 = _T_363 ? iccm_bank_dout_fn_2 : 39'h0; // @[Mux.scala 27:72]
-  wire [38:0] _T_408 = _T_365 ? iccm_bank_dout_fn_3 : 39'h0; // @[Mux.scala 27:72]
-  wire [38:0] _T_409 = _T_405 | _T_406; // @[Mux.scala 27:72]
-  wire [38:0] _T_410 = _T_409 | _T_407; // @[Mux.scala 27:72]
-  wire [38:0] _T_411 = _T_410 | _T_408; // @[Mux.scala 27:72]
-  wire [38:0] _T_421 = _T_376 ? iccm_bank_dout_fn_0 : 39'h0; // @[Mux.scala 27:72]
-  wire [38:0] _T_422 = _T_379 ? iccm_bank_dout_fn_1 : 39'h0; // @[Mux.scala 27:72]
-  wire [38:0] _T_423 = _T_382 ? iccm_bank_dout_fn_2 : 39'h0; // @[Mux.scala 27:72]
-  wire [38:0] _T_424 = _T_385 ? iccm_bank_dout_fn_3 : 39'h0; // @[Mux.scala 27:72]
-  wire [38:0] _T_425 = _T_421 | _T_422; // @[Mux.scala 27:72]
-  wire [38:0] _T_426 = _T_425 | _T_423; // @[Mux.scala 27:72]
-  wire [38:0] _T_427 = _T_426 | _T_424; // @[Mux.scala 27:72]
+  wire  _T_286 = ~redundant_lru; // @[el2_ifu_iccm_mem.scala 70:20]
+  wire  r0_addr_en = _T_286 & io_iccm_buf_correct_ecc; // @[el2_ifu_iccm_mem.scala 70:35]
+  wire  r1_addr_en = redundant_lru & io_iccm_buf_correct_ecc; // @[el2_ifu_iccm_mem.scala 71:35]
+  wire  _T_287 = |sel_red0; // @[el2_ifu_iccm_mem.scala 72:63]
+  wire  _T_288 = |sel_red1; // @[el2_ifu_iccm_mem.scala 72:78]
+  wire  _T_289 = _T_287 | _T_288; // @[el2_ifu_iccm_mem.scala 72:67]
+  wire  _T_290 = _T_289 & io_iccm_rden; // @[el2_ifu_iccm_mem.scala 72:83]
+  wire  _T_291 = _T_290 & io_iccm_correction_state; // @[el2_ifu_iccm_mem.scala 72:98]
+  wire  redundant_lru_en = io_iccm_buf_correct_ecc | _T_291; // @[el2_ifu_iccm_mem.scala 72:50]
+  wire  _GEN_11 = r1_addr_en | _T_302; // @[Reg.scala 28:19]
+  wire  _GEN_12 = r0_addr_en | _T_303; // @[Reg.scala 28:19]
+  wire  _T_307 = io_iccm_rw_addr[14:2] == redundant_address_0[13:1]; // @[el2_ifu_iccm_mem.scala 79:61]
+  wire  _T_310 = io_iccm_rw_addr[1] & redundant_address_0[0]; // @[el2_ifu_iccm_mem.scala 80:26]
+  wire  _T_313 = _T_310 | _T_1; // @[el2_ifu_iccm_mem.scala 80:52]
+  wire  _T_314 = _T_307 & _T_313; // @[el2_ifu_iccm_mem.scala 79:102]
+  wire  _T_316 = _T_314 & redundant_valid[0]; // @[el2_ifu_iccm_mem.scala 80:84]
+  wire  _T_317 = _T_316 & io_iccm_wren; // @[el2_ifu_iccm_mem.scala 80:105]
+  wire  redundant_data0_en = _T_317 | r0_addr_en; // @[el2_ifu_iccm_mem.scala 80:121]
+  wire  _T_326 = redundant_address_0[0] & _T_1; // @[el2_ifu_iccm_mem.scala 82:104]
+  wire  _T_327 = _T_310 | _T_326; // @[el2_ifu_iccm_mem.scala 82:78]
+  wire  _T_335 = io_iccm_rw_addr[14:2] == redundant_address_1[13:1]; // @[el2_ifu_iccm_mem.scala 86:61]
+  wire  _T_338 = io_iccm_rw_addr[1] & redundant_address_1[0]; // @[el2_ifu_iccm_mem.scala 87:26]
+  wire  _T_341 = _T_338 | _T_1; // @[el2_ifu_iccm_mem.scala 87:52]
+  wire  _T_342 = _T_335 & _T_341; // @[el2_ifu_iccm_mem.scala 86:102]
+  wire  _T_344 = _T_342 & redundant_valid[1]; // @[el2_ifu_iccm_mem.scala 87:84]
+  wire  _T_345 = _T_344 & io_iccm_wren; // @[el2_ifu_iccm_mem.scala 87:105]
+  wire  redundant_data1_en = _T_345 | r0_addr_en; // @[el2_ifu_iccm_mem.scala 87:121]
+  wire  _T_354 = redundant_address_1[0] & _T_1; // @[el2_ifu_iccm_mem.scala 89:104]
+  wire  _T_355 = _T_338 | _T_354; // @[el2_ifu_iccm_mem.scala 89:78]
+  reg [2:0] iccm_rd_addr_lo_q; // @[el2_ifu_iccm_mem.scala 93:34]
+  reg [1:0] iccm_rd_addr_hi_q; // @[el2_ifu_iccm_mem.scala 94:34]
+  wire  _T_363 = iccm_rd_addr_hi_q == 2'h0; // @[el2_ifu_iccm_mem.scala 96:86]
+  wire  _T_365 = iccm_rd_addr_hi_q == 2'h1; // @[el2_ifu_iccm_mem.scala 96:86]
+  wire  _T_367 = iccm_rd_addr_hi_q == 2'h2; // @[el2_ifu_iccm_mem.scala 96:86]
+  wire  _T_369 = iccm_rd_addr_hi_q == 2'h3; // @[el2_ifu_iccm_mem.scala 96:86]
+  wire [31:0] _T_371 = _T_363 ? iccm_bank_dout_fn_0[31:0] : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_372 = _T_365 ? iccm_bank_dout_fn_1[31:0] : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_373 = _T_367 ? iccm_bank_dout_fn_2[31:0] : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_374 = _T_369 ? iccm_bank_dout_fn_3[31:0] : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_375 = _T_371 | _T_372; // @[Mux.scala 27:72]
+  wire [31:0] _T_376 = _T_375 | _T_373; // @[Mux.scala 27:72]
+  wire [31:0] _T_377 = _T_376 | _T_374; // @[Mux.scala 27:72]
+  wire  _T_380 = iccm_rd_addr_lo_q[1:0] == 2'h0; // @[el2_ifu_iccm_mem.scala 97:77]
+  wire  _T_383 = iccm_rd_addr_lo_q[1:0] == 2'h1; // @[el2_ifu_iccm_mem.scala 97:77]
+  wire  _T_386 = iccm_rd_addr_lo_q[1:0] == 2'h2; // @[el2_ifu_iccm_mem.scala 97:77]
+  wire  _T_389 = iccm_rd_addr_lo_q[1:0] == 2'h3; // @[el2_ifu_iccm_mem.scala 97:77]
+  wire [31:0] _T_391 = _T_380 ? iccm_bank_dout_fn_0[31:0] : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_392 = _T_383 ? iccm_bank_dout_fn_1[31:0] : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_393 = _T_386 ? iccm_bank_dout_fn_2[31:0] : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_394 = _T_389 ? iccm_bank_dout_fn_3[31:0] : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_395 = _T_391 | _T_392; // @[Mux.scala 27:72]
+  wire [31:0] _T_396 = _T_395 | _T_393; // @[Mux.scala 27:72]
+  wire [31:0] _T_397 = _T_396 | _T_394; // @[Mux.scala 27:72]
+  wire [63:0] iccm_rd_data_pre = {_T_377,_T_397}; // @[Cat.scala 29:58]
+  wire [63:0] _T_403 = {16'h0,iccm_rd_data_pre[63:16]}; // @[Cat.scala 29:58]
+  wire [38:0] _T_409 = _T_363 ? iccm_bank_dout_fn_0 : 39'h0; // @[Mux.scala 27:72]
+  wire [38:0] _T_410 = _T_365 ? iccm_bank_dout_fn_1 : 39'h0; // @[Mux.scala 27:72]
+  wire [38:0] _T_411 = _T_367 ? iccm_bank_dout_fn_2 : 39'h0; // @[Mux.scala 27:72]
+  wire [38:0] _T_412 = _T_369 ? iccm_bank_dout_fn_3 : 39'h0; // @[Mux.scala 27:72]
+  wire [38:0] _T_413 = _T_409 | _T_410; // @[Mux.scala 27:72]
+  wire [38:0] _T_414 = _T_413 | _T_411; // @[Mux.scala 27:72]
+  wire [38:0] _T_415 = _T_414 | _T_412; // @[Mux.scala 27:72]
+  wire [38:0] _T_425 = _T_380 ? iccm_bank_dout_fn_0 : 39'h0; // @[Mux.scala 27:72]
+  wire [38:0] _T_426 = _T_383 ? iccm_bank_dout_fn_1 : 39'h0; // @[Mux.scala 27:72]
+  wire [38:0] _T_427 = _T_386 ? iccm_bank_dout_fn_2 : 39'h0; // @[Mux.scala 27:72]
+  wire [38:0] _T_428 = _T_389 ? iccm_bank_dout_fn_3 : 39'h0; // @[Mux.scala 27:72]
+  wire [38:0] _T_429 = _T_425 | _T_426; // @[Mux.scala 27:72]
+  wire [38:0] _T_430 = _T_429 | _T_427; // @[Mux.scala 27:72]
+  wire [38:0] _T_431 = _T_430 | _T_428; // @[Mux.scala 27:72]
   assign iccm_mem_0__T_97_addr = wren_bank_0 ? io_iccm_rw_addr[14:3] : _T_59;
-  assign iccm_mem_0__T_97_data = iccm_mem_0[iccm_mem_0__T_97_addr]; // @[el2_ifu_iccm_mem.scala 40:21]
+  assign iccm_mem_0__T_97_data = iccm_mem_0[iccm_mem_0__T_97_addr]; // @[el2_ifu_iccm_mem.scala 41:21]
   assign iccm_mem_0__T_93_data = io_iccm_wr_data[38:0];
   assign iccm_mem_0__T_93_addr = wren_bank_0 ? io_iccm_rw_addr[14:3] : _T_59;
   assign iccm_mem_0__T_93_mask = iccm_clken_0 & wren_bank_0;
@@ -322,7 +330,7 @@ module el2_ifu_iccm_mem(
   assign iccm_mem_0__T_96_mask = iccm_clken_0 & wren_bank_0;
   assign iccm_mem_0__T_96_en = 1'h1;
   assign iccm_mem_1__T_97_addr = wren_bank_0 ? io_iccm_rw_addr[14:3] : _T_59;
-  assign iccm_mem_1__T_97_data = iccm_mem_1[iccm_mem_1__T_97_addr]; // @[el2_ifu_iccm_mem.scala 40:21]
+  assign iccm_mem_1__T_97_data = iccm_mem_1[iccm_mem_1__T_97_addr]; // @[el2_ifu_iccm_mem.scala 41:21]
   assign iccm_mem_1__T_93_data = io_iccm_wr_data[77:39];
   assign iccm_mem_1__T_93_addr = wren_bank_0 ? io_iccm_rw_addr[14:3] : _T_59;
   assign iccm_mem_1__T_93_mask = iccm_clken_1 & wren_bank_1;
@@ -340,7 +348,7 @@ module el2_ifu_iccm_mem(
   assign iccm_mem_1__T_96_mask = iccm_clken_1 & wren_bank_1;
   assign iccm_mem_1__T_96_en = 1'h1;
   assign iccm_mem_2__T_97_addr = wren_bank_0 ? io_iccm_rw_addr[14:3] : _T_59;
-  assign iccm_mem_2__T_97_data = iccm_mem_2[iccm_mem_2__T_97_addr]; // @[el2_ifu_iccm_mem.scala 40:21]
+  assign iccm_mem_2__T_97_data = iccm_mem_2[iccm_mem_2__T_97_addr]; // @[el2_ifu_iccm_mem.scala 41:21]
   assign iccm_mem_2__T_93_data = io_iccm_wr_data[38:0];
   assign iccm_mem_2__T_93_addr = wren_bank_0 ? io_iccm_rw_addr[14:3] : _T_59;
   assign iccm_mem_2__T_93_mask = iccm_clken_2 & wren_bank_2;
@@ -358,7 +366,7 @@ module el2_ifu_iccm_mem(
   assign iccm_mem_2__T_96_mask = iccm_clken_2 & wren_bank_2;
   assign iccm_mem_2__T_96_en = 1'h1;
   assign iccm_mem_3__T_97_addr = wren_bank_0 ? io_iccm_rw_addr[14:3] : _T_59;
-  assign iccm_mem_3__T_97_data = iccm_mem_3[iccm_mem_3__T_97_addr]; // @[el2_ifu_iccm_mem.scala 40:21]
+  assign iccm_mem_3__T_97_data = iccm_mem_3[iccm_mem_3__T_97_addr]; // @[el2_ifu_iccm_mem.scala 41:21]
   assign iccm_mem_3__T_93_data = io_iccm_wr_data[77:39];
   assign iccm_mem_3__T_93_addr = wren_bank_0 ? io_iccm_rw_addr[14:3] : _T_59;
   assign iccm_mem_3__T_93_mask = iccm_clken_3 & wren_bank_3;
@@ -375,8 +383,12 @@ module el2_ifu_iccm_mem(
   assign iccm_mem_3__T_96_addr = wren_bank_3 ? io_iccm_rw_addr[14:3] : _T_80;
   assign iccm_mem_3__T_96_mask = iccm_clken_3 & wren_bank_3;
   assign iccm_mem_3__T_96_en = 1'h1;
-  assign io_iccm_rd_data = iccm_rd_addr_lo_q[0] ? _T_399 : iccm_rd_data_pre; // @[el2_ifu_iccm_mem.scala 22:19 el2_ifu_iccm_mem.scala 95:19]
-  assign io_iccm_rd_data_ecc = {_T_411,_T_427}; // @[el2_ifu_iccm_mem.scala 23:23 el2_ifu_iccm_mem.scala 96:23]
+  assign io_iccm_rd_data = iccm_rd_addr_lo_q[0] ? _T_403 : iccm_rd_data_pre; // @[el2_ifu_iccm_mem.scala 22:19 el2_ifu_iccm_mem.scala 98:19]
+  assign io_iccm_rd_data_ecc = {_T_415,_T_431}; // @[el2_ifu_iccm_mem.scala 23:23 el2_ifu_iccm_mem.scala 99:23]
+  assign io_iccm_bank_wr_data_0 = io_iccm_wr_data[38:0]; // @[el2_ifu_iccm_mem.scala 35:24]
+  assign io_iccm_bank_wr_data_1 = io_iccm_wr_data[77:39]; // @[el2_ifu_iccm_mem.scala 35:24]
+  assign io_iccm_bank_wr_data_2 = io_iccm_wr_data[38:0]; // @[el2_ifu_iccm_mem.scala 35:24]
+  assign io_iccm_bank_wr_data_3 = io_iccm_wr_data[77:39]; // @[el2_ifu_iccm_mem.scala 35:24]
 `ifdef RANDOMIZE_GARBAGE_ASSIGN
 `define RANDOMIZE
 `endif
@@ -426,28 +438,36 @@ initial begin
     iccm_mem_3[initvar] = _RAND_3[38:0];
 `endif // RANDOMIZE_MEM_INIT
 `ifdef RANDOMIZE_REG_INIT
-  _RAND_4 = {1{`RANDOM}};
-  _T_298 = _RAND_4[0:0];
-  _RAND_5 = {1{`RANDOM}};
-  _T_299 = _RAND_5[0:0];
-  _RAND_6 = {1{`RANDOM}};
-  redundant_address_1 = _RAND_6[13:0];
-  _RAND_7 = {1{`RANDOM}};
-  redundant_address_0 = _RAND_7[13:0];
+  _RAND_4 = {2{`RANDOM}};
+  iccm_bank_dout_0 = _RAND_4[38:0];
+  _RAND_5 = {2{`RANDOM}};
+  iccm_bank_dout_1 = _RAND_5[38:0];
+  _RAND_6 = {2{`RANDOM}};
+  iccm_bank_dout_2 = _RAND_6[38:0];
+  _RAND_7 = {2{`RANDOM}};
+  iccm_bank_dout_3 = _RAND_7[38:0];
   _RAND_8 = {1{`RANDOM}};
-  sel_red0_q = _RAND_8[3:0];
+  _T_302 = _RAND_8[0:0];
   _RAND_9 = {1{`RANDOM}};
-  sel_red1_q = _RAND_9[3:0];
-  _RAND_10 = {2{`RANDOM}};
-  redundant_data_1 = _RAND_10[38:0];
-  _RAND_11 = {2{`RANDOM}};
-  redundant_data_0 = _RAND_11[38:0];
+  _T_303 = _RAND_9[0:0];
+  _RAND_10 = {1{`RANDOM}};
+  redundant_address_1 = _RAND_10[13:0];
+  _RAND_11 = {1{`RANDOM}};
+  redundant_address_0 = _RAND_11[13:0];
   _RAND_12 = {1{`RANDOM}};
-  redundant_lru = _RAND_12[0:0];
+  sel_red0_q = _RAND_12[3:0];
   _RAND_13 = {1{`RANDOM}};
-  iccm_rd_addr_lo_q = _RAND_13[2:0];
-  _RAND_14 = {1{`RANDOM}};
-  iccm_rd_addr_hi_q = _RAND_14[1:0];
+  sel_red1_q = _RAND_13[3:0];
+  _RAND_14 = {2{`RANDOM}};
+  redundant_data_1 = _RAND_14[38:0];
+  _RAND_15 = {2{`RANDOM}};
+  redundant_data_0 = _RAND_15[38:0];
+  _RAND_16 = {1{`RANDOM}};
+  redundant_lru = _RAND_16[0:0];
+  _RAND_17 = {1{`RANDOM}};
+  iccm_rd_addr_lo_q = _RAND_17[2:0];
+  _RAND_18 = {1{`RANDOM}};
+  iccm_rd_addr_hi_q = _RAND_18[1:0];
 `endif // RANDOMIZE_REG_INIT
   `endif // RANDOMIZE
 end // initial
@@ -457,62 +477,66 @@ end // initial
 `endif // SYNTHESIS
   always @(posedge clock) begin
     if(iccm_mem_0__T_93_en & iccm_mem_0__T_93_mask) begin
-      iccm_mem_0[iccm_mem_0__T_93_addr] <= iccm_mem_0__T_93_data; // @[el2_ifu_iccm_mem.scala 40:21]
+      iccm_mem_0[iccm_mem_0__T_93_addr] <= iccm_mem_0__T_93_data; // @[el2_ifu_iccm_mem.scala 41:21]
     end
     if(iccm_mem_0__T_94_en & iccm_mem_0__T_94_mask) begin
-      iccm_mem_0[iccm_mem_0__T_94_addr] <= iccm_mem_0__T_94_data; // @[el2_ifu_iccm_mem.scala 40:21]
+      iccm_mem_0[iccm_mem_0__T_94_addr] <= iccm_mem_0__T_94_data; // @[el2_ifu_iccm_mem.scala 41:21]
     end
     if(iccm_mem_0__T_95_en & iccm_mem_0__T_95_mask) begin
-      iccm_mem_0[iccm_mem_0__T_95_addr] <= iccm_mem_0__T_95_data; // @[el2_ifu_iccm_mem.scala 40:21]
+      iccm_mem_0[iccm_mem_0__T_95_addr] <= iccm_mem_0__T_95_data; // @[el2_ifu_iccm_mem.scala 41:21]
     end
     if(iccm_mem_0__T_96_en & iccm_mem_0__T_96_mask) begin
-      iccm_mem_0[iccm_mem_0__T_96_addr] <= iccm_mem_0__T_96_data; // @[el2_ifu_iccm_mem.scala 40:21]
+      iccm_mem_0[iccm_mem_0__T_96_addr] <= iccm_mem_0__T_96_data; // @[el2_ifu_iccm_mem.scala 41:21]
     end
     if(iccm_mem_1__T_93_en & iccm_mem_1__T_93_mask) begin
-      iccm_mem_1[iccm_mem_1__T_93_addr] <= iccm_mem_1__T_93_data; // @[el2_ifu_iccm_mem.scala 40:21]
+      iccm_mem_1[iccm_mem_1__T_93_addr] <= iccm_mem_1__T_93_data; // @[el2_ifu_iccm_mem.scala 41:21]
     end
     if(iccm_mem_1__T_94_en & iccm_mem_1__T_94_mask) begin
-      iccm_mem_1[iccm_mem_1__T_94_addr] <= iccm_mem_1__T_94_data; // @[el2_ifu_iccm_mem.scala 40:21]
+      iccm_mem_1[iccm_mem_1__T_94_addr] <= iccm_mem_1__T_94_data; // @[el2_ifu_iccm_mem.scala 41:21]
     end
     if(iccm_mem_1__T_95_en & iccm_mem_1__T_95_mask) begin
-      iccm_mem_1[iccm_mem_1__T_95_addr] <= iccm_mem_1__T_95_data; // @[el2_ifu_iccm_mem.scala 40:21]
+      iccm_mem_1[iccm_mem_1__T_95_addr] <= iccm_mem_1__T_95_data; // @[el2_ifu_iccm_mem.scala 41:21]
     end
     if(iccm_mem_1__T_96_en & iccm_mem_1__T_96_mask) begin
-      iccm_mem_1[iccm_mem_1__T_96_addr] <= iccm_mem_1__T_96_data; // @[el2_ifu_iccm_mem.scala 40:21]
+      iccm_mem_1[iccm_mem_1__T_96_addr] <= iccm_mem_1__T_96_data; // @[el2_ifu_iccm_mem.scala 41:21]
     end
     if(iccm_mem_2__T_93_en & iccm_mem_2__T_93_mask) begin
-      iccm_mem_2[iccm_mem_2__T_93_addr] <= iccm_mem_2__T_93_data; // @[el2_ifu_iccm_mem.scala 40:21]
+      iccm_mem_2[iccm_mem_2__T_93_addr] <= iccm_mem_2__T_93_data; // @[el2_ifu_iccm_mem.scala 41:21]
     end
     if(iccm_mem_2__T_94_en & iccm_mem_2__T_94_mask) begin
-      iccm_mem_2[iccm_mem_2__T_94_addr] <= iccm_mem_2__T_94_data; // @[el2_ifu_iccm_mem.scala 40:21]
+      iccm_mem_2[iccm_mem_2__T_94_addr] <= iccm_mem_2__T_94_data; // @[el2_ifu_iccm_mem.scala 41:21]
     end
     if(iccm_mem_2__T_95_en & iccm_mem_2__T_95_mask) begin
-      iccm_mem_2[iccm_mem_2__T_95_addr] <= iccm_mem_2__T_95_data; // @[el2_ifu_iccm_mem.scala 40:21]
+      iccm_mem_2[iccm_mem_2__T_95_addr] <= iccm_mem_2__T_95_data; // @[el2_ifu_iccm_mem.scala 41:21]
     end
     if(iccm_mem_2__T_96_en & iccm_mem_2__T_96_mask) begin
-      iccm_mem_2[iccm_mem_2__T_96_addr] <= iccm_mem_2__T_96_data; // @[el2_ifu_iccm_mem.scala 40:21]
+      iccm_mem_2[iccm_mem_2__T_96_addr] <= iccm_mem_2__T_96_data; // @[el2_ifu_iccm_mem.scala 41:21]
     end
     if(iccm_mem_3__T_93_en & iccm_mem_3__T_93_mask) begin
-      iccm_mem_3[iccm_mem_3__T_93_addr] <= iccm_mem_3__T_93_data; // @[el2_ifu_iccm_mem.scala 40:21]
+      iccm_mem_3[iccm_mem_3__T_93_addr] <= iccm_mem_3__T_93_data; // @[el2_ifu_iccm_mem.scala 41:21]
     end
     if(iccm_mem_3__T_94_en & iccm_mem_3__T_94_mask) begin
-      iccm_mem_3[iccm_mem_3__T_94_addr] <= iccm_mem_3__T_94_data; // @[el2_ifu_iccm_mem.scala 40:21]
+      iccm_mem_3[iccm_mem_3__T_94_addr] <= iccm_mem_3__T_94_data; // @[el2_ifu_iccm_mem.scala 41:21]
     end
     if(iccm_mem_3__T_95_en & iccm_mem_3__T_95_mask) begin
-      iccm_mem_3[iccm_mem_3__T_95_addr] <= iccm_mem_3__T_95_data; // @[el2_ifu_iccm_mem.scala 40:21]
+      iccm_mem_3[iccm_mem_3__T_95_addr] <= iccm_mem_3__T_95_data; // @[el2_ifu_iccm_mem.scala 41:21]
     end
     if(iccm_mem_3__T_96_en & iccm_mem_3__T_96_mask) begin
-      iccm_mem_3[iccm_mem_3__T_96_addr] <= iccm_mem_3__T_96_data; // @[el2_ifu_iccm_mem.scala 40:21]
+      iccm_mem_3[iccm_mem_3__T_96_addr] <= iccm_mem_3__T_96_data; // @[el2_ifu_iccm_mem.scala 41:21]
+    end
+    iccm_bank_dout_0 <= iccm_mem_0__T_97_data;
+    iccm_bank_dout_1 <= iccm_mem_1__T_97_data;
+    iccm_bank_dout_2 <= iccm_mem_2__T_97_data;
+    iccm_bank_dout_3 <= iccm_mem_3__T_97_data;
+    if (reset) begin
+      _T_302 <= 1'h0;
+    end else begin
+      _T_302 <= _GEN_11;
     end
     if (reset) begin
-      _T_298 <= 1'h0;
+      _T_303 <= 1'h0;
     end else begin
-      _T_298 <= _GEN_11;
-    end
-    if (reset) begin
-      _T_299 <= 1'h0;
-    end else begin
-      _T_299 <= _GEN_12;
+      _T_303 <= _GEN_12;
     end
     if (reset) begin
       redundant_address_1 <= 14'h0;
@@ -537,7 +561,7 @@ end // initial
     if (reset) begin
       redundant_data_1 <= 39'h0;
     end else if (redundant_data1_en) begin
-      if (_T_351) begin
+      if (_T_355) begin
         redundant_data_1 <= iccm_bank_wr_data_1;
       end else begin
         redundant_data_1 <= iccm_bank_wr_data_0;
@@ -546,7 +570,7 @@ end // initial
     if (reset) begin
       redundant_data_0 <= 39'h0;
     end else if (redundant_data0_en) begin
-      if (_T_323) begin
+      if (_T_327) begin
         redundant_data_0 <= iccm_bank_wr_data_1;
       end else begin
         redundant_data_0 <= iccm_bank_wr_data_0;
@@ -556,9 +580,9 @@ end // initial
       redundant_lru <= 1'h0;
     end else if (redundant_lru_en) begin
       if (io_iccm_buf_correct_ecc) begin
-        redundant_lru <= _T_282;
+        redundant_lru <= _T_286;
       end else begin
-        redundant_lru <= _T_283;
+        redundant_lru <= _T_287;
       end
     end
     if (reset) begin
diff --git a/src/main/scala/ifu/el2_ifu_iccm_mem.scala b/src/main/scala/ifu/el2_ifu_iccm_mem.scala
index 194deb42..fa3b62d5 100644
--- a/src/main/scala/ifu/el2_ifu_iccm_mem.scala
+++ b/src/main/scala/ifu/el2_ifu_iccm_mem.scala
@@ -17,7 +17,7 @@ class el2_ifu_iccm_mem extends Module with el2_lib {
     val iccm_rd_data = Output(UInt(64.W))
     val iccm_rd_data_ecc = Output(UInt(78.W))
     val scan_mode = Input(Bool())
-
+    val iccm_bank_wr_data = Output(Vec(ICCM_NUM_BANKS, UInt(39.W)))
   })
   io.iccm_rd_data := 0.U
   io.iccm_rd_data_ecc := 0.U
@@ -32,20 +32,23 @@ class el2_ifu_iccm_mem extends Module with el2_lib {
 
   val wren_bank = (0 until ICCM_NUM_BANKS).map(i=> io.iccm_wren&(io.iccm_rw_addr(ICCM_BANK_HI-1,1)===i.U)|(addr_bank_inc(ICCM_BANK_HI-1,1)===i.U))
   val iccm_bank_wr_data = iccm_bank_wr_data_vec
+  io.iccm_bank_wr_data := iccm_bank_wr_data
   val rden_bank = (0 until ICCM_NUM_BANKS).map(i=> io.iccm_rden&(io.iccm_rw_addr(ICCM_BANK_HI-1,1)===i.U)|(addr_bank_inc(ICCM_BANK_HI-1,1)===i.U))
   val iccm_clken = for(i<- 0 until ICCM_NUM_BANKS) yield  wren_bank(i) | rden_bank(i) | io.clk_override
   val addr_bank = (0 until ICCM_NUM_BANKS).map(i=> Mux(wren_bank(i).asBool, io.iccm_rw_addr(ICCM_BITS-2, ICCM_BANK_INDEX_LO-1),
     Mux((addr_bank_inc(ICCM_BANK_HI-1,1)===i.U),addr_bank_inc(ICCM_BITS-2,ICCM_BANK_INDEX_LO-1),io.iccm_rw_addr(ICCM_BITS-2,ICCM_BANK_INDEX_LO-1))))
-  println(pow(2, ICCM_INDEX_BITS).intValue)
+
   val iccm_mem = Mem(pow(2, ICCM_INDEX_BITS).intValue, Vec(ICCM_NUM_BANKS, UInt(39.W)))
 
   val write_vec = VecInit.tabulate(ICCM_NUM_BANKS)(i=>iccm_clken(i)&wren_bank(i))
   val read_enable = VecInit.tabulate(ICCM_NUM_BANKS)(i=>iccm_clken(i)&(!wren_bank(i)))
   //io.test := addr_bank
   val iccm_bank_dout = Wire(Vec(ICCM_NUM_BANKS, UInt(39.W)))
+  val inter = Wire(Vec(ICCM_NUM_BANKS, UInt(39.W)))
   for(i<-0 until ICCM_NUM_BANKS) iccm_mem.write(addr_bank(i), iccm_bank_wr_data, write_vec)
-  iccm_bank_dout := iccm_mem.read(addr_bank(0))
-  //io.test := iccm_bank_dout
+  inter := iccm_mem.read(addr_bank(0))
+  for(i<-0 until ICCM_NUM_BANKS) iccm_bank_dout(i) := RegNext(inter(i))
+
   val redundant_valid = WireInit(UInt(2.W), init = 0.U)
   val redundant_address = Wire(Vec(2, UInt((ICCM_BITS-2).W)))
   redundant_address := (0 until 2).map(i=>0.U)
diff --git a/target/scala-2.12/classes/ifu/el2_ifu_iccm_mem$$anon$1.class b/target/scala-2.12/classes/ifu/el2_ifu_iccm_mem$$anon$1.class
index 80fe0146..0a034168 100644
Binary files a/target/scala-2.12/classes/ifu/el2_ifu_iccm_mem$$anon$1.class and b/target/scala-2.12/classes/ifu/el2_ifu_iccm_mem$$anon$1.class differ
diff --git a/target/scala-2.12/classes/ifu/el2_ifu_iccm_mem.class b/target/scala-2.12/classes/ifu/el2_ifu_iccm_mem.class
index 2ec89cc8..2bd4b251 100644
Binary files a/target/scala-2.12/classes/ifu/el2_ifu_iccm_mem.class and b/target/scala-2.12/classes/ifu/el2_ifu_iccm_mem.class differ
diff --git a/target/scala-2.12/classes/ifu/ifu_iccm$.class b/target/scala-2.12/classes/ifu/ifu_iccm$.class
index e4e13467..eecc7b1a 100644
Binary files a/target/scala-2.12/classes/ifu/ifu_iccm$.class and b/target/scala-2.12/classes/ifu/ifu_iccm$.class differ
diff --git a/target/scala-2.12/classes/ifu/ifu_iccm$delayedInit$body.class b/target/scala-2.12/classes/ifu/ifu_iccm$delayedInit$body.class
index 4d02b84c..68805253 100644
Binary files a/target/scala-2.12/classes/ifu/ifu_iccm$delayedInit$body.class and b/target/scala-2.12/classes/ifu/ifu_iccm$delayedInit$body.class differ