From a885b0e1a7b019e87736651d0a327073edddd2f0 Mon Sep 17 00:00:00 2001 From: waleed-lm Date: Thu, 8 Oct 2020 11:08:49 +0500 Subject: [PATCH] ICCM Flop done --- el2_ifu_iccm_mem.anno.json | 26 +- el2_ifu_iccm_mem.fir | 973 +++++++++--------- el2_ifu_iccm_mem.v | 630 ++++++------ src/main/scala/ifu/el2_ifu_iccm_mem.scala | 11 +- .../ifu/el2_ifu_iccm_mem$$anon$1.class | Bin 3110 -> 3721 bytes .../classes/ifu/el2_ifu_iccm_mem.class | Bin 92014 -> 92971 bytes target/scala-2.12/classes/ifu/ifu_iccm$.class | Bin 3883 -> 3883 bytes .../ifu/ifu_iccm$delayedInit$body.class | Bin 743 -> 743 bytes 8 files changed, 847 insertions(+), 793 deletions(-) diff --git a/el2_ifu_iccm_mem.anno.json b/el2_ifu_iccm_mem.anno.json index cb681bfe..ab7e9a2d 100644 --- a/el2_ifu_iccm_mem.anno.json +++ b/el2_ifu_iccm_mem.anno.json @@ -1,20 +1,30 @@ [ { "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_rd_data", + "sink":"~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_bank_wr_data_1", "sources":[ - "~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_rw_addr", - "~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_wren", - "~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_wr_size" + "~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_wr_data" ] }, { "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_rd_data_ecc", + "sink":"~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_bank_wr_data_0", "sources":[ - "~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_rw_addr", - "~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_wren", - "~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_wr_size" + "~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_wr_data" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_bank_wr_data_2", + "sources":[ + "~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_wr_data" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_bank_wr_data_3", + "sources":[ + "~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_wr_data" ] }, { diff --git a/el2_ifu_iccm_mem.fir b/el2_ifu_iccm_mem.fir index d82190b8..f77ea2a3 100644 --- a/el2_ifu_iccm_mem.fir +++ b/el2_ifu_iccm_mem.fir @@ -3,7 +3,7 @@ circuit el2_ifu_iccm_mem : module el2_ifu_iccm_mem : input clock : Clock input reset : UInt<1> - output io : {flip clk_override : UInt<1>, flip iccm_wren : UInt<1>, flip iccm_rden : UInt<1>, flip iccm_rw_addr : UInt<15>, flip iccm_buf_correct_ecc : UInt<1>, flip iccm_correction_state : UInt<1>, flip iccm_wr_size : UInt<3>, flip iccm_wr_data : UInt<78>, iccm_rd_data : UInt<64>, iccm_rd_data_ecc : UInt<78>, flip scan_mode : UInt<1>} + output io : {flip clk_override : UInt<1>, flip iccm_wren : UInt<1>, flip iccm_rden : UInt<1>, flip iccm_rw_addr : UInt<15>, flip iccm_buf_correct_ecc : UInt<1>, flip iccm_correction_state : UInt<1>, flip iccm_wr_size : UInt<3>, flip iccm_wr_data : UInt<78>, iccm_rd_data : UInt<64>, iccm_rd_data_ecc : UInt<78>, flip scan_mode : UInt<1>, iccm_bank_wr_data : UInt<39>[4]} io.iccm_rd_data <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 22:19] io.iccm_rd_data_ecc <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 23:23] @@ -47,94 +47,99 @@ circuit el2_ifu_iccm_mem : node _T_27 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 33:121] node _T_28 = eq(_T_27, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 33:139] node wren_bank_3 = or(_T_26, _T_28) @[el2_ifu_iccm_mem.scala 33:106] - node _T_29 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 35:81] - node _T_30 = eq(_T_29, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 35:99] - node _T_31 = and(io.iccm_rden, _T_30) @[el2_ifu_iccm_mem.scala 35:64] - node _T_32 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 35:121] - node _T_33 = eq(_T_32, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 35:139] - node rden_bank_0 = or(_T_31, _T_33) @[el2_ifu_iccm_mem.scala 35:106] - node _T_34 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 35:81] - node _T_35 = eq(_T_34, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 35:99] - node _T_36 = and(io.iccm_rden, _T_35) @[el2_ifu_iccm_mem.scala 35:64] - node _T_37 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 35:121] - node _T_38 = eq(_T_37, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 35:139] - node rden_bank_1 = or(_T_36, _T_38) @[el2_ifu_iccm_mem.scala 35:106] - node _T_39 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 35:81] - node _T_40 = eq(_T_39, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 35:99] - node _T_41 = and(io.iccm_rden, _T_40) @[el2_ifu_iccm_mem.scala 35:64] - node _T_42 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 35:121] - node _T_43 = eq(_T_42, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 35:139] - node rden_bank_2 = or(_T_41, _T_43) @[el2_ifu_iccm_mem.scala 35:106] - node _T_44 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 35:81] - node _T_45 = eq(_T_44, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 35:99] - node _T_46 = and(io.iccm_rden, _T_45) @[el2_ifu_iccm_mem.scala 35:64] - node _T_47 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 35:121] - node _T_48 = eq(_T_47, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 35:139] - node rden_bank_3 = or(_T_46, _T_48) @[el2_ifu_iccm_mem.scala 35:106] - node _T_49 = or(wren_bank_0, rden_bank_0) @[el2_ifu_iccm_mem.scala 36:72] - node iccm_clken_0 = or(_T_49, io.clk_override) @[el2_ifu_iccm_mem.scala 36:87] - node _T_50 = or(wren_bank_1, rden_bank_1) @[el2_ifu_iccm_mem.scala 36:72] - node iccm_clken_1 = or(_T_50, io.clk_override) @[el2_ifu_iccm_mem.scala 36:87] - node _T_51 = or(wren_bank_2, rden_bank_2) @[el2_ifu_iccm_mem.scala 36:72] - node iccm_clken_2 = or(_T_51, io.clk_override) @[el2_ifu_iccm_mem.scala 36:87] - node _T_52 = or(wren_bank_3, rden_bank_3) @[el2_ifu_iccm_mem.scala 36:72] - node iccm_clken_3 = or(_T_52, io.clk_override) @[el2_ifu_iccm_mem.scala 36:87] - node _T_53 = bits(wren_bank_0, 0, 0) @[el2_ifu_iccm_mem.scala 37:69] - node _T_54 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 37:92] - node _T_55 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 38:23] - node _T_56 = eq(_T_55, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 38:41] - node _T_57 = bits(addr_bank_inc, 14, 3) @[el2_ifu_iccm_mem.scala 38:62] - node _T_58 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 38:112] - node _T_59 = mux(_T_56, _T_57, _T_58) @[el2_ifu_iccm_mem.scala 38:8] - node addr_bank_0 = mux(_T_53, _T_54, _T_59) @[el2_ifu_iccm_mem.scala 37:55] - node _T_60 = bits(wren_bank_1, 0, 0) @[el2_ifu_iccm_mem.scala 37:69] - node _T_61 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 37:92] - node _T_62 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 38:23] - node _T_63 = eq(_T_62, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 38:41] - node _T_64 = bits(addr_bank_inc, 14, 3) @[el2_ifu_iccm_mem.scala 38:62] - node _T_65 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 38:112] - node _T_66 = mux(_T_63, _T_64, _T_65) @[el2_ifu_iccm_mem.scala 38:8] - node addr_bank_1 = mux(_T_60, _T_61, _T_66) @[el2_ifu_iccm_mem.scala 37:55] - node _T_67 = bits(wren_bank_2, 0, 0) @[el2_ifu_iccm_mem.scala 37:69] - node _T_68 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 37:92] - node _T_69 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 38:23] - node _T_70 = eq(_T_69, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 38:41] - node _T_71 = bits(addr_bank_inc, 14, 3) @[el2_ifu_iccm_mem.scala 38:62] - node _T_72 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 38:112] - node _T_73 = mux(_T_70, _T_71, _T_72) @[el2_ifu_iccm_mem.scala 38:8] - node addr_bank_2 = mux(_T_67, _T_68, _T_73) @[el2_ifu_iccm_mem.scala 37:55] - node _T_74 = bits(wren_bank_3, 0, 0) @[el2_ifu_iccm_mem.scala 37:69] - node _T_75 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 37:92] - node _T_76 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 38:23] - node _T_77 = eq(_T_76, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 38:41] - node _T_78 = bits(addr_bank_inc, 14, 3) @[el2_ifu_iccm_mem.scala 38:62] - node _T_79 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 38:112] - node _T_80 = mux(_T_77, _T_78, _T_79) @[el2_ifu_iccm_mem.scala 38:8] - node addr_bank_3 = mux(_T_74, _T_75, _T_80) @[el2_ifu_iccm_mem.scala 37:55] - cmem iccm_mem : UInt<39>[4][4096] @[el2_ifu_iccm_mem.scala 40:21] - node _T_81 = and(iccm_clken_0, wren_bank_0) @[el2_ifu_iccm_mem.scala 42:68] - node _T_82 = and(iccm_clken_1, wren_bank_1) @[el2_ifu_iccm_mem.scala 42:68] - node _T_83 = and(iccm_clken_2, wren_bank_2) @[el2_ifu_iccm_mem.scala 42:68] - node _T_84 = and(iccm_clken_3, wren_bank_3) @[el2_ifu_iccm_mem.scala 42:68] - wire write_vec : UInt<1>[4] @[el2_ifu_iccm_mem.scala 42:51] - write_vec[0] <= _T_81 @[el2_ifu_iccm_mem.scala 42:51] - write_vec[1] <= _T_82 @[el2_ifu_iccm_mem.scala 42:51] - write_vec[2] <= _T_83 @[el2_ifu_iccm_mem.scala 42:51] - write_vec[3] <= _T_84 @[el2_ifu_iccm_mem.scala 42:51] - node _T_85 = eq(wren_bank_0, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 43:72] - node _T_86 = and(iccm_clken_0, _T_85) @[el2_ifu_iccm_mem.scala 43:70] - node _T_87 = eq(wren_bank_1, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 43:72] - node _T_88 = and(iccm_clken_1, _T_87) @[el2_ifu_iccm_mem.scala 43:70] - node _T_89 = eq(wren_bank_2, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 43:72] - node _T_90 = and(iccm_clken_2, _T_89) @[el2_ifu_iccm_mem.scala 43:70] - node _T_91 = eq(wren_bank_3, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 43:72] - node _T_92 = and(iccm_clken_3, _T_91) @[el2_ifu_iccm_mem.scala 43:70] - wire read_enable : UInt<1>[4] @[el2_ifu_iccm_mem.scala 43:53] - read_enable[0] <= _T_86 @[el2_ifu_iccm_mem.scala 43:53] - read_enable[1] <= _T_88 @[el2_ifu_iccm_mem.scala 43:53] - read_enable[2] <= _T_90 @[el2_ifu_iccm_mem.scala 43:53] - read_enable[3] <= _T_92 @[el2_ifu_iccm_mem.scala 43:53] - wire iccm_bank_dout : UInt<39>[4] @[el2_ifu_iccm_mem.scala 45:28] + io.iccm_bank_wr_data[0] <= iccm_bank_wr_data[0] @[el2_ifu_iccm_mem.scala 35:24] + io.iccm_bank_wr_data[1] <= iccm_bank_wr_data[1] @[el2_ifu_iccm_mem.scala 35:24] + io.iccm_bank_wr_data[2] <= iccm_bank_wr_data[2] @[el2_ifu_iccm_mem.scala 35:24] + io.iccm_bank_wr_data[3] <= iccm_bank_wr_data[3] @[el2_ifu_iccm_mem.scala 35:24] + node _T_29 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 36:81] + node _T_30 = eq(_T_29, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 36:99] + node _T_31 = and(io.iccm_rden, _T_30) @[el2_ifu_iccm_mem.scala 36:64] + node _T_32 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 36:121] + node _T_33 = eq(_T_32, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 36:139] + node rden_bank_0 = or(_T_31, _T_33) @[el2_ifu_iccm_mem.scala 36:106] + node _T_34 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 36:81] + node _T_35 = eq(_T_34, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 36:99] + node _T_36 = and(io.iccm_rden, _T_35) @[el2_ifu_iccm_mem.scala 36:64] + node _T_37 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 36:121] + node _T_38 = eq(_T_37, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 36:139] + node rden_bank_1 = or(_T_36, _T_38) @[el2_ifu_iccm_mem.scala 36:106] + node _T_39 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 36:81] + node _T_40 = eq(_T_39, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 36:99] + node _T_41 = and(io.iccm_rden, _T_40) @[el2_ifu_iccm_mem.scala 36:64] + node _T_42 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 36:121] + node _T_43 = eq(_T_42, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 36:139] + node rden_bank_2 = or(_T_41, _T_43) @[el2_ifu_iccm_mem.scala 36:106] + node _T_44 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 36:81] + node _T_45 = eq(_T_44, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 36:99] + node _T_46 = and(io.iccm_rden, _T_45) @[el2_ifu_iccm_mem.scala 36:64] + node _T_47 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 36:121] + node _T_48 = eq(_T_47, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 36:139] + node rden_bank_3 = or(_T_46, _T_48) @[el2_ifu_iccm_mem.scala 36:106] + node _T_49 = or(wren_bank_0, rden_bank_0) @[el2_ifu_iccm_mem.scala 37:72] + node iccm_clken_0 = or(_T_49, io.clk_override) @[el2_ifu_iccm_mem.scala 37:87] + node _T_50 = or(wren_bank_1, rden_bank_1) @[el2_ifu_iccm_mem.scala 37:72] + node iccm_clken_1 = or(_T_50, io.clk_override) @[el2_ifu_iccm_mem.scala 37:87] + node _T_51 = or(wren_bank_2, rden_bank_2) @[el2_ifu_iccm_mem.scala 37:72] + node iccm_clken_2 = or(_T_51, io.clk_override) @[el2_ifu_iccm_mem.scala 37:87] + node _T_52 = or(wren_bank_3, rden_bank_3) @[el2_ifu_iccm_mem.scala 37:72] + node iccm_clken_3 = or(_T_52, io.clk_override) @[el2_ifu_iccm_mem.scala 37:87] + node _T_53 = bits(wren_bank_0, 0, 0) @[el2_ifu_iccm_mem.scala 38:69] + node _T_54 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 38:92] + node _T_55 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 39:23] + node _T_56 = eq(_T_55, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 39:41] + node _T_57 = bits(addr_bank_inc, 14, 3) @[el2_ifu_iccm_mem.scala 39:62] + node _T_58 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 39:112] + node _T_59 = mux(_T_56, _T_57, _T_58) @[el2_ifu_iccm_mem.scala 39:8] + node addr_bank_0 = mux(_T_53, _T_54, _T_59) @[el2_ifu_iccm_mem.scala 38:55] + node _T_60 = bits(wren_bank_1, 0, 0) @[el2_ifu_iccm_mem.scala 38:69] + node _T_61 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 38:92] + node _T_62 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 39:23] + node _T_63 = eq(_T_62, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 39:41] + node _T_64 = bits(addr_bank_inc, 14, 3) @[el2_ifu_iccm_mem.scala 39:62] + node _T_65 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 39:112] + node _T_66 = mux(_T_63, _T_64, _T_65) @[el2_ifu_iccm_mem.scala 39:8] + node addr_bank_1 = mux(_T_60, _T_61, _T_66) @[el2_ifu_iccm_mem.scala 38:55] + node _T_67 = bits(wren_bank_2, 0, 0) @[el2_ifu_iccm_mem.scala 38:69] + node _T_68 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 38:92] + node _T_69 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 39:23] + node _T_70 = eq(_T_69, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 39:41] + node _T_71 = bits(addr_bank_inc, 14, 3) @[el2_ifu_iccm_mem.scala 39:62] + node _T_72 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 39:112] + node _T_73 = mux(_T_70, _T_71, _T_72) @[el2_ifu_iccm_mem.scala 39:8] + node addr_bank_2 = mux(_T_67, _T_68, _T_73) @[el2_ifu_iccm_mem.scala 38:55] + node _T_74 = bits(wren_bank_3, 0, 0) @[el2_ifu_iccm_mem.scala 38:69] + node _T_75 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 38:92] + node _T_76 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 39:23] + node _T_77 = eq(_T_76, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 39:41] + node _T_78 = bits(addr_bank_inc, 14, 3) @[el2_ifu_iccm_mem.scala 39:62] + node _T_79 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 39:112] + node _T_80 = mux(_T_77, _T_78, _T_79) @[el2_ifu_iccm_mem.scala 39:8] + node addr_bank_3 = mux(_T_74, _T_75, _T_80) @[el2_ifu_iccm_mem.scala 38:55] + cmem iccm_mem : UInt<39>[4][4096] @[el2_ifu_iccm_mem.scala 41:21] + node _T_81 = and(iccm_clken_0, wren_bank_0) @[el2_ifu_iccm_mem.scala 43:68] + node _T_82 = and(iccm_clken_1, wren_bank_1) @[el2_ifu_iccm_mem.scala 43:68] + node _T_83 = and(iccm_clken_2, wren_bank_2) @[el2_ifu_iccm_mem.scala 43:68] + node _T_84 = and(iccm_clken_3, wren_bank_3) @[el2_ifu_iccm_mem.scala 43:68] + wire write_vec : UInt<1>[4] @[el2_ifu_iccm_mem.scala 43:51] + write_vec[0] <= _T_81 @[el2_ifu_iccm_mem.scala 43:51] + write_vec[1] <= _T_82 @[el2_ifu_iccm_mem.scala 43:51] + write_vec[2] <= _T_83 @[el2_ifu_iccm_mem.scala 43:51] + write_vec[3] <= _T_84 @[el2_ifu_iccm_mem.scala 43:51] + node _T_85 = eq(wren_bank_0, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 44:72] + node _T_86 = and(iccm_clken_0, _T_85) @[el2_ifu_iccm_mem.scala 44:70] + node _T_87 = eq(wren_bank_1, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 44:72] + node _T_88 = and(iccm_clken_1, _T_87) @[el2_ifu_iccm_mem.scala 44:70] + node _T_89 = eq(wren_bank_2, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 44:72] + node _T_90 = and(iccm_clken_2, _T_89) @[el2_ifu_iccm_mem.scala 44:70] + node _T_91 = eq(wren_bank_3, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 44:72] + node _T_92 = and(iccm_clken_3, _T_91) @[el2_ifu_iccm_mem.scala 44:70] + wire read_enable : UInt<1>[4] @[el2_ifu_iccm_mem.scala 44:53] + read_enable[0] <= _T_86 @[el2_ifu_iccm_mem.scala 44:53] + read_enable[1] <= _T_88 @[el2_ifu_iccm_mem.scala 44:53] + read_enable[2] <= _T_90 @[el2_ifu_iccm_mem.scala 44:53] + read_enable[3] <= _T_92 @[el2_ifu_iccm_mem.scala 44:53] + wire iccm_bank_dout : UInt<39>[4] @[el2_ifu_iccm_mem.scala 46:28] + wire inter : UInt<39>[4] @[el2_ifu_iccm_mem.scala 47:19] write mport _T_93 = iccm_mem[addr_bank_0], clock when write_vec[0] : _T_93[0] <= iccm_bank_wr_data[0] @@ -187,411 +192,423 @@ circuit el2_ifu_iccm_mem : when write_vec[3] : _T_96[3] <= iccm_bank_wr_data[3] skip - read mport _T_97 = iccm_mem[addr_bank_0], clock @[el2_ifu_iccm_mem.scala 47:34] - iccm_bank_dout[0] <= _T_97[0] @[el2_ifu_iccm_mem.scala 47:18] - iccm_bank_dout[1] <= _T_97[1] @[el2_ifu_iccm_mem.scala 47:18] - iccm_bank_dout[2] <= _T_97[2] @[el2_ifu_iccm_mem.scala 47:18] - iccm_bank_dout[3] <= _T_97[3] @[el2_ifu_iccm_mem.scala 47:18] + read mport _T_97 = iccm_mem[addr_bank_0], clock @[el2_ifu_iccm_mem.scala 49:25] + inter[0] <= _T_97[0] @[el2_ifu_iccm_mem.scala 49:9] + inter[1] <= _T_97[1] @[el2_ifu_iccm_mem.scala 49:9] + inter[2] <= _T_97[2] @[el2_ifu_iccm_mem.scala 49:9] + inter[3] <= _T_97[3] @[el2_ifu_iccm_mem.scala 49:9] + reg _T_98 : UInt, clock @[el2_ifu_iccm_mem.scala 50:62] + _T_98 <= inter[0] @[el2_ifu_iccm_mem.scala 50:62] + iccm_bank_dout[0] <= _T_98 @[el2_ifu_iccm_mem.scala 50:52] + reg _T_99 : UInt, clock @[el2_ifu_iccm_mem.scala 50:62] + _T_99 <= inter[1] @[el2_ifu_iccm_mem.scala 50:62] + iccm_bank_dout[1] <= _T_99 @[el2_ifu_iccm_mem.scala 50:52] + reg _T_100 : UInt, clock @[el2_ifu_iccm_mem.scala 50:62] + _T_100 <= inter[2] @[el2_ifu_iccm_mem.scala 50:62] + iccm_bank_dout[2] <= _T_100 @[el2_ifu_iccm_mem.scala 50:52] + reg _T_101 : UInt, clock @[el2_ifu_iccm_mem.scala 50:62] + _T_101 <= inter[3] @[el2_ifu_iccm_mem.scala 50:62] + iccm_bank_dout[3] <= _T_101 @[el2_ifu_iccm_mem.scala 50:52] wire redundant_valid : UInt<2> redundant_valid <= UInt<1>("h00") - wire redundant_address : UInt<14>[2] @[el2_ifu_iccm_mem.scala 50:31] - redundant_address[0] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 51:21] - redundant_address[1] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 51:21] - node _T_98 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 53:67] - node _T_99 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 53:90] - node _T_100 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 53:128] - node _T_101 = eq(_T_99, _T_100) @[el2_ifu_iccm_mem.scala 53:105] - node _T_102 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 53:163] - node _T_103 = eq(_T_102, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 53:169] - node _T_104 = and(_T_101, _T_103) @[el2_ifu_iccm_mem.scala 53:145] - node _T_105 = and(_T_98, _T_104) @[el2_ifu_iccm_mem.scala 53:71] - node _T_106 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 54:22] - node _T_107 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 54:60] - node _T_108 = eq(_T_106, _T_107) @[el2_ifu_iccm_mem.scala 54:37] - node _T_109 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 54:93] - node _T_110 = eq(_T_109, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 54:99] - node _T_111 = and(_T_108, _T_110) @[el2_ifu_iccm_mem.scala 54:77] - node _T_112 = or(_T_105, _T_111) @[el2_ifu_iccm_mem.scala 53:179] - node _T_113 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 53:67] - node _T_114 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 53:90] - node _T_115 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 53:128] - node _T_116 = eq(_T_114, _T_115) @[el2_ifu_iccm_mem.scala 53:105] - node _T_117 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 53:163] - node _T_118 = eq(_T_117, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 53:169] - node _T_119 = and(_T_116, _T_118) @[el2_ifu_iccm_mem.scala 53:145] - node _T_120 = and(_T_113, _T_119) @[el2_ifu_iccm_mem.scala 53:71] - node _T_121 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 54:22] - node _T_122 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 54:60] - node _T_123 = eq(_T_121, _T_122) @[el2_ifu_iccm_mem.scala 54:37] - node _T_124 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 54:93] - node _T_125 = eq(_T_124, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 54:99] - node _T_126 = and(_T_123, _T_125) @[el2_ifu_iccm_mem.scala 54:77] - node _T_127 = or(_T_120, _T_126) @[el2_ifu_iccm_mem.scala 53:179] - node _T_128 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 53:67] - node _T_129 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 53:90] - node _T_130 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 53:128] - node _T_131 = eq(_T_129, _T_130) @[el2_ifu_iccm_mem.scala 53:105] - node _T_132 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 53:163] - node _T_133 = eq(_T_132, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 53:169] - node _T_134 = and(_T_131, _T_133) @[el2_ifu_iccm_mem.scala 53:145] - node _T_135 = and(_T_128, _T_134) @[el2_ifu_iccm_mem.scala 53:71] - node _T_136 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 54:22] - node _T_137 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 54:60] - node _T_138 = eq(_T_136, _T_137) @[el2_ifu_iccm_mem.scala 54:37] - node _T_139 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 54:93] - node _T_140 = eq(_T_139, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 54:99] - node _T_141 = and(_T_138, _T_140) @[el2_ifu_iccm_mem.scala 54:77] - node _T_142 = or(_T_135, _T_141) @[el2_ifu_iccm_mem.scala 53:179] - node _T_143 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 53:67] - node _T_144 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 53:90] - node _T_145 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 53:128] - node _T_146 = eq(_T_144, _T_145) @[el2_ifu_iccm_mem.scala 53:105] - node _T_147 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 53:163] - node _T_148 = eq(_T_147, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 53:169] - node _T_149 = and(_T_146, _T_148) @[el2_ifu_iccm_mem.scala 53:145] - node _T_150 = and(_T_143, _T_149) @[el2_ifu_iccm_mem.scala 53:71] - node _T_151 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 54:22] - node _T_152 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 54:60] - node _T_153 = eq(_T_151, _T_152) @[el2_ifu_iccm_mem.scala 54:37] - node _T_154 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 54:93] - node _T_155 = eq(_T_154, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 54:99] - node _T_156 = and(_T_153, _T_155) @[el2_ifu_iccm_mem.scala 54:77] - node _T_157 = or(_T_150, _T_156) @[el2_ifu_iccm_mem.scala 53:179] - node _T_158 = cat(_T_157, _T_142) @[Cat.scala 29:58] - node _T_159 = cat(_T_158, _T_127) @[Cat.scala 29:58] - node sel_red1 = cat(_T_159, _T_112) @[Cat.scala 29:58] - node _T_160 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 55:67] - node _T_161 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 55:90] - node _T_162 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 55:128] - node _T_163 = eq(_T_161, _T_162) @[el2_ifu_iccm_mem.scala 55:105] - node _T_164 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 55:163] - node _T_165 = eq(_T_164, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 55:169] - node _T_166 = and(_T_163, _T_165) @[el2_ifu_iccm_mem.scala 55:145] - node _T_167 = and(_T_160, _T_166) @[el2_ifu_iccm_mem.scala 55:71] - node _T_168 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 56:22] - node _T_169 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 56:60] - node _T_170 = eq(_T_168, _T_169) @[el2_ifu_iccm_mem.scala 56:37] - node _T_171 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 56:93] - node _T_172 = eq(_T_171, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 56:99] - node _T_173 = and(_T_170, _T_172) @[el2_ifu_iccm_mem.scala 56:77] - node _T_174 = or(_T_167, _T_173) @[el2_ifu_iccm_mem.scala 55:179] - node _T_175 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 55:67] - node _T_176 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 55:90] - node _T_177 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 55:128] - node _T_178 = eq(_T_176, _T_177) @[el2_ifu_iccm_mem.scala 55:105] - node _T_179 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 55:163] - node _T_180 = eq(_T_179, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 55:169] - node _T_181 = and(_T_178, _T_180) @[el2_ifu_iccm_mem.scala 55:145] - node _T_182 = and(_T_175, _T_181) @[el2_ifu_iccm_mem.scala 55:71] - node _T_183 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 56:22] - node _T_184 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 56:60] - node _T_185 = eq(_T_183, _T_184) @[el2_ifu_iccm_mem.scala 56:37] - node _T_186 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 56:93] - node _T_187 = eq(_T_186, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 56:99] - node _T_188 = and(_T_185, _T_187) @[el2_ifu_iccm_mem.scala 56:77] - node _T_189 = or(_T_182, _T_188) @[el2_ifu_iccm_mem.scala 55:179] - node _T_190 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 55:67] - node _T_191 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 55:90] - node _T_192 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 55:128] - node _T_193 = eq(_T_191, _T_192) @[el2_ifu_iccm_mem.scala 55:105] - node _T_194 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 55:163] - node _T_195 = eq(_T_194, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 55:169] - node _T_196 = and(_T_193, _T_195) @[el2_ifu_iccm_mem.scala 55:145] - node _T_197 = and(_T_190, _T_196) @[el2_ifu_iccm_mem.scala 55:71] - node _T_198 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 56:22] - node _T_199 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 56:60] - node _T_200 = eq(_T_198, _T_199) @[el2_ifu_iccm_mem.scala 56:37] - node _T_201 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 56:93] - node _T_202 = eq(_T_201, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 56:99] - node _T_203 = and(_T_200, _T_202) @[el2_ifu_iccm_mem.scala 56:77] - node _T_204 = or(_T_197, _T_203) @[el2_ifu_iccm_mem.scala 55:179] - node _T_205 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 55:67] - node _T_206 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 55:90] - node _T_207 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 55:128] - node _T_208 = eq(_T_206, _T_207) @[el2_ifu_iccm_mem.scala 55:105] - node _T_209 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 55:163] - node _T_210 = eq(_T_209, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 55:169] - node _T_211 = and(_T_208, _T_210) @[el2_ifu_iccm_mem.scala 55:145] - node _T_212 = and(_T_205, _T_211) @[el2_ifu_iccm_mem.scala 55:71] - node _T_213 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 56:22] - node _T_214 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 56:60] - node _T_215 = eq(_T_213, _T_214) @[el2_ifu_iccm_mem.scala 56:37] - node _T_216 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 56:93] - node _T_217 = eq(_T_216, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 56:99] - node _T_218 = and(_T_215, _T_217) @[el2_ifu_iccm_mem.scala 56:77] - node _T_219 = or(_T_212, _T_218) @[el2_ifu_iccm_mem.scala 55:179] - node _T_220 = cat(_T_219, _T_204) @[Cat.scala 29:58] - node _T_221 = cat(_T_220, _T_189) @[Cat.scala 29:58] - node sel_red0 = cat(_T_221, _T_174) @[Cat.scala 29:58] - reg sel_red0_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 58:27] - sel_red0_q <= sel_red0 @[el2_ifu_iccm_mem.scala 58:27] - reg sel_red1_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 59:27] - sel_red1_q <= sel_red1 @[el2_ifu_iccm_mem.scala 59:27] - wire redundant_data : UInt<39>[2] @[el2_ifu_iccm_mem.scala 60:28] - redundant_data[0] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 61:18] - redundant_data[1] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 61:18] - node _T_222 = bits(sel_red1_q, 0, 0) @[el2_ifu_iccm_mem.scala 63:47] - node _T_223 = bits(_T_222, 0, 0) @[el2_ifu_iccm_mem.scala 63:51] - node _T_224 = bits(sel_red0_q, 0, 0) @[el2_ifu_iccm_mem.scala 64:47] - node _T_225 = bits(_T_224, 0, 0) @[el2_ifu_iccm_mem.scala 64:51] - node _T_226 = bits(sel_red0_q, 0, 0) @[el2_ifu_iccm_mem.scala 65:47] - node _T_227 = not(_T_226) @[el2_ifu_iccm_mem.scala 65:36] - node _T_228 = bits(sel_red1_q, 0, 0) @[el2_ifu_iccm_mem.scala 65:64] - node _T_229 = not(_T_228) @[el2_ifu_iccm_mem.scala 65:53] - node _T_230 = and(_T_227, _T_229) @[el2_ifu_iccm_mem.scala 65:51] - node _T_231 = bits(_T_230, 0, 0) @[el2_ifu_iccm_mem.scala 65:69] - node _T_232 = mux(_T_223, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_233 = mux(_T_225, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_234 = mux(_T_231, iccm_bank_dout[0], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_235 = or(_T_232, _T_233) @[Mux.scala 27:72] - node _T_236 = or(_T_235, _T_234) @[Mux.scala 27:72] + wire redundant_address : UInt<14>[2] @[el2_ifu_iccm_mem.scala 53:31] + redundant_address[0] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 54:21] + redundant_address[1] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 54:21] + node _T_102 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 56:67] + node _T_103 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 56:90] + node _T_104 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 56:128] + node _T_105 = eq(_T_103, _T_104) @[el2_ifu_iccm_mem.scala 56:105] + node _T_106 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 56:163] + node _T_107 = eq(_T_106, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 56:169] + node _T_108 = and(_T_105, _T_107) @[el2_ifu_iccm_mem.scala 56:145] + node _T_109 = and(_T_102, _T_108) @[el2_ifu_iccm_mem.scala 56:71] + node _T_110 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 57:22] + node _T_111 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 57:60] + node _T_112 = eq(_T_110, _T_111) @[el2_ifu_iccm_mem.scala 57:37] + node _T_113 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 57:93] + node _T_114 = eq(_T_113, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 57:99] + node _T_115 = and(_T_112, _T_114) @[el2_ifu_iccm_mem.scala 57:77] + node _T_116 = or(_T_109, _T_115) @[el2_ifu_iccm_mem.scala 56:179] + node _T_117 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 56:67] + node _T_118 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 56:90] + node _T_119 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 56:128] + node _T_120 = eq(_T_118, _T_119) @[el2_ifu_iccm_mem.scala 56:105] + node _T_121 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 56:163] + node _T_122 = eq(_T_121, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 56:169] + node _T_123 = and(_T_120, _T_122) @[el2_ifu_iccm_mem.scala 56:145] + node _T_124 = and(_T_117, _T_123) @[el2_ifu_iccm_mem.scala 56:71] + node _T_125 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 57:22] + node _T_126 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 57:60] + node _T_127 = eq(_T_125, _T_126) @[el2_ifu_iccm_mem.scala 57:37] + node _T_128 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 57:93] + node _T_129 = eq(_T_128, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 57:99] + node _T_130 = and(_T_127, _T_129) @[el2_ifu_iccm_mem.scala 57:77] + node _T_131 = or(_T_124, _T_130) @[el2_ifu_iccm_mem.scala 56:179] + node _T_132 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 56:67] + node _T_133 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 56:90] + node _T_134 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 56:128] + node _T_135 = eq(_T_133, _T_134) @[el2_ifu_iccm_mem.scala 56:105] + node _T_136 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 56:163] + node _T_137 = eq(_T_136, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 56:169] + node _T_138 = and(_T_135, _T_137) @[el2_ifu_iccm_mem.scala 56:145] + node _T_139 = and(_T_132, _T_138) @[el2_ifu_iccm_mem.scala 56:71] + node _T_140 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 57:22] + node _T_141 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 57:60] + node _T_142 = eq(_T_140, _T_141) @[el2_ifu_iccm_mem.scala 57:37] + node _T_143 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 57:93] + node _T_144 = eq(_T_143, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 57:99] + node _T_145 = and(_T_142, _T_144) @[el2_ifu_iccm_mem.scala 57:77] + node _T_146 = or(_T_139, _T_145) @[el2_ifu_iccm_mem.scala 56:179] + node _T_147 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 56:67] + node _T_148 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 56:90] + node _T_149 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 56:128] + node _T_150 = eq(_T_148, _T_149) @[el2_ifu_iccm_mem.scala 56:105] + node _T_151 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 56:163] + node _T_152 = eq(_T_151, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 56:169] + node _T_153 = and(_T_150, _T_152) @[el2_ifu_iccm_mem.scala 56:145] + node _T_154 = and(_T_147, _T_153) @[el2_ifu_iccm_mem.scala 56:71] + node _T_155 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 57:22] + node _T_156 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 57:60] + node _T_157 = eq(_T_155, _T_156) @[el2_ifu_iccm_mem.scala 57:37] + node _T_158 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 57:93] + node _T_159 = eq(_T_158, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 57:99] + node _T_160 = and(_T_157, _T_159) @[el2_ifu_iccm_mem.scala 57:77] + node _T_161 = or(_T_154, _T_160) @[el2_ifu_iccm_mem.scala 56:179] + node _T_162 = cat(_T_161, _T_146) @[Cat.scala 29:58] + node _T_163 = cat(_T_162, _T_131) @[Cat.scala 29:58] + node sel_red1 = cat(_T_163, _T_116) @[Cat.scala 29:58] + node _T_164 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 58:67] + node _T_165 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 58:90] + node _T_166 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 58:128] + node _T_167 = eq(_T_165, _T_166) @[el2_ifu_iccm_mem.scala 58:105] + node _T_168 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 58:163] + node _T_169 = eq(_T_168, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 58:169] + node _T_170 = and(_T_167, _T_169) @[el2_ifu_iccm_mem.scala 58:145] + node _T_171 = and(_T_164, _T_170) @[el2_ifu_iccm_mem.scala 58:71] + node _T_172 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 59:22] + node _T_173 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 59:60] + node _T_174 = eq(_T_172, _T_173) @[el2_ifu_iccm_mem.scala 59:37] + node _T_175 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 59:93] + node _T_176 = eq(_T_175, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 59:99] + node _T_177 = and(_T_174, _T_176) @[el2_ifu_iccm_mem.scala 59:77] + node _T_178 = or(_T_171, _T_177) @[el2_ifu_iccm_mem.scala 58:179] + node _T_179 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 58:67] + node _T_180 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 58:90] + node _T_181 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 58:128] + node _T_182 = eq(_T_180, _T_181) @[el2_ifu_iccm_mem.scala 58:105] + node _T_183 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 58:163] + node _T_184 = eq(_T_183, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 58:169] + node _T_185 = and(_T_182, _T_184) @[el2_ifu_iccm_mem.scala 58:145] + node _T_186 = and(_T_179, _T_185) @[el2_ifu_iccm_mem.scala 58:71] + node _T_187 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 59:22] + node _T_188 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 59:60] + node _T_189 = eq(_T_187, _T_188) @[el2_ifu_iccm_mem.scala 59:37] + node _T_190 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 59:93] + node _T_191 = eq(_T_190, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 59:99] + node _T_192 = and(_T_189, _T_191) @[el2_ifu_iccm_mem.scala 59:77] + node _T_193 = or(_T_186, _T_192) @[el2_ifu_iccm_mem.scala 58:179] + node _T_194 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 58:67] + node _T_195 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 58:90] + node _T_196 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 58:128] + node _T_197 = eq(_T_195, _T_196) @[el2_ifu_iccm_mem.scala 58:105] + node _T_198 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 58:163] + node _T_199 = eq(_T_198, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 58:169] + node _T_200 = and(_T_197, _T_199) @[el2_ifu_iccm_mem.scala 58:145] + node _T_201 = and(_T_194, _T_200) @[el2_ifu_iccm_mem.scala 58:71] + node _T_202 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 59:22] + node _T_203 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 59:60] + node _T_204 = eq(_T_202, _T_203) @[el2_ifu_iccm_mem.scala 59:37] + node _T_205 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 59:93] + node _T_206 = eq(_T_205, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 59:99] + node _T_207 = and(_T_204, _T_206) @[el2_ifu_iccm_mem.scala 59:77] + node _T_208 = or(_T_201, _T_207) @[el2_ifu_iccm_mem.scala 58:179] + node _T_209 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 58:67] + node _T_210 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 58:90] + node _T_211 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 58:128] + node _T_212 = eq(_T_210, _T_211) @[el2_ifu_iccm_mem.scala 58:105] + node _T_213 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 58:163] + node _T_214 = eq(_T_213, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 58:169] + node _T_215 = and(_T_212, _T_214) @[el2_ifu_iccm_mem.scala 58:145] + node _T_216 = and(_T_209, _T_215) @[el2_ifu_iccm_mem.scala 58:71] + node _T_217 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 59:22] + node _T_218 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 59:60] + node _T_219 = eq(_T_217, _T_218) @[el2_ifu_iccm_mem.scala 59:37] + node _T_220 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 59:93] + node _T_221 = eq(_T_220, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 59:99] + node _T_222 = and(_T_219, _T_221) @[el2_ifu_iccm_mem.scala 59:77] + node _T_223 = or(_T_216, _T_222) @[el2_ifu_iccm_mem.scala 58:179] + node _T_224 = cat(_T_223, _T_208) @[Cat.scala 29:58] + node _T_225 = cat(_T_224, _T_193) @[Cat.scala 29:58] + node sel_red0 = cat(_T_225, _T_178) @[Cat.scala 29:58] + reg sel_red0_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 61:27] + sel_red0_q <= sel_red0 @[el2_ifu_iccm_mem.scala 61:27] + reg sel_red1_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 62:27] + sel_red1_q <= sel_red1 @[el2_ifu_iccm_mem.scala 62:27] + wire redundant_data : UInt<39>[2] @[el2_ifu_iccm_mem.scala 63:28] + redundant_data[0] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 64:18] + redundant_data[1] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 64:18] + node _T_226 = bits(sel_red1_q, 0, 0) @[el2_ifu_iccm_mem.scala 66:47] + node _T_227 = bits(_T_226, 0, 0) @[el2_ifu_iccm_mem.scala 66:51] + node _T_228 = bits(sel_red0_q, 0, 0) @[el2_ifu_iccm_mem.scala 67:47] + node _T_229 = bits(_T_228, 0, 0) @[el2_ifu_iccm_mem.scala 67:51] + node _T_230 = bits(sel_red0_q, 0, 0) @[el2_ifu_iccm_mem.scala 68:47] + node _T_231 = not(_T_230) @[el2_ifu_iccm_mem.scala 68:36] + node _T_232 = bits(sel_red1_q, 0, 0) @[el2_ifu_iccm_mem.scala 68:64] + node _T_233 = not(_T_232) @[el2_ifu_iccm_mem.scala 68:53] + node _T_234 = and(_T_231, _T_233) @[el2_ifu_iccm_mem.scala 68:51] + node _T_235 = bits(_T_234, 0, 0) @[el2_ifu_iccm_mem.scala 68:69] + node _T_236 = mux(_T_227, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_237 = mux(_T_229, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_238 = mux(_T_235, iccm_bank_dout[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_239 = or(_T_236, _T_237) @[Mux.scala 27:72] + node _T_240 = or(_T_239, _T_238) @[Mux.scala 27:72] wire iccm_bank_dout_fn_0 : UInt<39> @[Mux.scala 27:72] - iccm_bank_dout_fn_0 <= _T_236 @[Mux.scala 27:72] - node _T_237 = bits(sel_red1_q, 1, 1) @[el2_ifu_iccm_mem.scala 63:47] - node _T_238 = bits(_T_237, 0, 0) @[el2_ifu_iccm_mem.scala 63:51] - node _T_239 = bits(sel_red0_q, 1, 1) @[el2_ifu_iccm_mem.scala 64:47] - node _T_240 = bits(_T_239, 0, 0) @[el2_ifu_iccm_mem.scala 64:51] - node _T_241 = bits(sel_red0_q, 1, 1) @[el2_ifu_iccm_mem.scala 65:47] - node _T_242 = not(_T_241) @[el2_ifu_iccm_mem.scala 65:36] - node _T_243 = bits(sel_red1_q, 1, 1) @[el2_ifu_iccm_mem.scala 65:64] - node _T_244 = not(_T_243) @[el2_ifu_iccm_mem.scala 65:53] - node _T_245 = and(_T_242, _T_244) @[el2_ifu_iccm_mem.scala 65:51] - node _T_246 = bits(_T_245, 0, 0) @[el2_ifu_iccm_mem.scala 65:69] - node _T_247 = mux(_T_238, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_248 = mux(_T_240, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_249 = mux(_T_246, iccm_bank_dout[1], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_250 = or(_T_247, _T_248) @[Mux.scala 27:72] - node _T_251 = or(_T_250, _T_249) @[Mux.scala 27:72] + iccm_bank_dout_fn_0 <= _T_240 @[Mux.scala 27:72] + node _T_241 = bits(sel_red1_q, 1, 1) @[el2_ifu_iccm_mem.scala 66:47] + node _T_242 = bits(_T_241, 0, 0) @[el2_ifu_iccm_mem.scala 66:51] + node _T_243 = bits(sel_red0_q, 1, 1) @[el2_ifu_iccm_mem.scala 67:47] + node _T_244 = bits(_T_243, 0, 0) @[el2_ifu_iccm_mem.scala 67:51] + node _T_245 = bits(sel_red0_q, 1, 1) @[el2_ifu_iccm_mem.scala 68:47] + node _T_246 = not(_T_245) @[el2_ifu_iccm_mem.scala 68:36] + node _T_247 = bits(sel_red1_q, 1, 1) @[el2_ifu_iccm_mem.scala 68:64] + node _T_248 = not(_T_247) @[el2_ifu_iccm_mem.scala 68:53] + node _T_249 = and(_T_246, _T_248) @[el2_ifu_iccm_mem.scala 68:51] + node _T_250 = bits(_T_249, 0, 0) @[el2_ifu_iccm_mem.scala 68:69] + node _T_251 = mux(_T_242, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_252 = mux(_T_244, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_253 = mux(_T_250, iccm_bank_dout[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_254 = or(_T_251, _T_252) @[Mux.scala 27:72] + node _T_255 = or(_T_254, _T_253) @[Mux.scala 27:72] wire iccm_bank_dout_fn_1 : UInt<39> @[Mux.scala 27:72] - iccm_bank_dout_fn_1 <= _T_251 @[Mux.scala 27:72] - node _T_252 = bits(sel_red1_q, 2, 2) @[el2_ifu_iccm_mem.scala 63:47] - node _T_253 = bits(_T_252, 0, 0) @[el2_ifu_iccm_mem.scala 63:51] - node _T_254 = bits(sel_red0_q, 2, 2) @[el2_ifu_iccm_mem.scala 64:47] - node _T_255 = bits(_T_254, 0, 0) @[el2_ifu_iccm_mem.scala 64:51] - node _T_256 = bits(sel_red0_q, 2, 2) @[el2_ifu_iccm_mem.scala 65:47] - node _T_257 = not(_T_256) @[el2_ifu_iccm_mem.scala 65:36] - node _T_258 = bits(sel_red1_q, 2, 2) @[el2_ifu_iccm_mem.scala 65:64] - node _T_259 = not(_T_258) @[el2_ifu_iccm_mem.scala 65:53] - node _T_260 = and(_T_257, _T_259) @[el2_ifu_iccm_mem.scala 65:51] - node _T_261 = bits(_T_260, 0, 0) @[el2_ifu_iccm_mem.scala 65:69] - node _T_262 = mux(_T_253, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_263 = mux(_T_255, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_264 = mux(_T_261, iccm_bank_dout[2], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_265 = or(_T_262, _T_263) @[Mux.scala 27:72] - node _T_266 = or(_T_265, _T_264) @[Mux.scala 27:72] + iccm_bank_dout_fn_1 <= _T_255 @[Mux.scala 27:72] + node _T_256 = bits(sel_red1_q, 2, 2) @[el2_ifu_iccm_mem.scala 66:47] + node _T_257 = bits(_T_256, 0, 0) @[el2_ifu_iccm_mem.scala 66:51] + node _T_258 = bits(sel_red0_q, 2, 2) @[el2_ifu_iccm_mem.scala 67:47] + node _T_259 = bits(_T_258, 0, 0) @[el2_ifu_iccm_mem.scala 67:51] + node _T_260 = bits(sel_red0_q, 2, 2) @[el2_ifu_iccm_mem.scala 68:47] + node _T_261 = not(_T_260) @[el2_ifu_iccm_mem.scala 68:36] + node _T_262 = bits(sel_red1_q, 2, 2) @[el2_ifu_iccm_mem.scala 68:64] + node _T_263 = not(_T_262) @[el2_ifu_iccm_mem.scala 68:53] + node _T_264 = and(_T_261, _T_263) @[el2_ifu_iccm_mem.scala 68:51] + node _T_265 = bits(_T_264, 0, 0) @[el2_ifu_iccm_mem.scala 68:69] + node _T_266 = mux(_T_257, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_267 = mux(_T_259, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_268 = mux(_T_265, iccm_bank_dout[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_269 = or(_T_266, _T_267) @[Mux.scala 27:72] + node _T_270 = or(_T_269, _T_268) @[Mux.scala 27:72] wire iccm_bank_dout_fn_2 : UInt<39> @[Mux.scala 27:72] - iccm_bank_dout_fn_2 <= _T_266 @[Mux.scala 27:72] - node _T_267 = bits(sel_red1_q, 3, 3) @[el2_ifu_iccm_mem.scala 63:47] - node _T_268 = bits(_T_267, 0, 0) @[el2_ifu_iccm_mem.scala 63:51] - node _T_269 = bits(sel_red0_q, 3, 3) @[el2_ifu_iccm_mem.scala 64:47] - node _T_270 = bits(_T_269, 0, 0) @[el2_ifu_iccm_mem.scala 64:51] - node _T_271 = bits(sel_red0_q, 3, 3) @[el2_ifu_iccm_mem.scala 65:47] - node _T_272 = not(_T_271) @[el2_ifu_iccm_mem.scala 65:36] - node _T_273 = bits(sel_red1_q, 3, 3) @[el2_ifu_iccm_mem.scala 65:64] - node _T_274 = not(_T_273) @[el2_ifu_iccm_mem.scala 65:53] - node _T_275 = and(_T_272, _T_274) @[el2_ifu_iccm_mem.scala 65:51] - node _T_276 = bits(_T_275, 0, 0) @[el2_ifu_iccm_mem.scala 65:69] - node _T_277 = mux(_T_268, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_278 = mux(_T_270, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_279 = mux(_T_276, iccm_bank_dout[3], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_280 = or(_T_277, _T_278) @[Mux.scala 27:72] - node _T_281 = or(_T_280, _T_279) @[Mux.scala 27:72] + iccm_bank_dout_fn_2 <= _T_270 @[Mux.scala 27:72] + node _T_271 = bits(sel_red1_q, 3, 3) @[el2_ifu_iccm_mem.scala 66:47] + node _T_272 = bits(_T_271, 0, 0) @[el2_ifu_iccm_mem.scala 66:51] + node _T_273 = bits(sel_red0_q, 3, 3) @[el2_ifu_iccm_mem.scala 67:47] + node _T_274 = bits(_T_273, 0, 0) @[el2_ifu_iccm_mem.scala 67:51] + node _T_275 = bits(sel_red0_q, 3, 3) @[el2_ifu_iccm_mem.scala 68:47] + node _T_276 = not(_T_275) @[el2_ifu_iccm_mem.scala 68:36] + node _T_277 = bits(sel_red1_q, 3, 3) @[el2_ifu_iccm_mem.scala 68:64] + node _T_278 = not(_T_277) @[el2_ifu_iccm_mem.scala 68:53] + node _T_279 = and(_T_276, _T_278) @[el2_ifu_iccm_mem.scala 68:51] + node _T_280 = bits(_T_279, 0, 0) @[el2_ifu_iccm_mem.scala 68:69] + node _T_281 = mux(_T_272, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_282 = mux(_T_274, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_283 = mux(_T_280, iccm_bank_dout[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_284 = or(_T_281, _T_282) @[Mux.scala 27:72] + node _T_285 = or(_T_284, _T_283) @[Mux.scala 27:72] wire iccm_bank_dout_fn_3 : UInt<39> @[Mux.scala 27:72] - iccm_bank_dout_fn_3 <= _T_281 @[Mux.scala 27:72] + iccm_bank_dout_fn_3 <= _T_285 @[Mux.scala 27:72] wire redundant_lru : UInt<1> redundant_lru <= UInt<1>("h00") - node _T_282 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 67:20] - node r0_addr_en = and(_T_282, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 67:35] - node r1_addr_en = and(redundant_lru, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 68:35] - node _T_283 = orr(sel_red0) @[el2_ifu_iccm_mem.scala 69:63] - node _T_284 = orr(sel_red1) @[el2_ifu_iccm_mem.scala 69:78] - node _T_285 = or(_T_283, _T_284) @[el2_ifu_iccm_mem.scala 69:67] - node _T_286 = and(_T_285, io.iccm_rden) @[el2_ifu_iccm_mem.scala 69:83] - node _T_287 = and(_T_286, io.iccm_correction_state) @[el2_ifu_iccm_mem.scala 69:98] - node redundant_lru_en = or(io.iccm_buf_correct_ecc, _T_287) @[el2_ifu_iccm_mem.scala 69:50] - node _T_288 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 70:55] - node _T_289 = orr(sel_red0) @[el2_ifu_iccm_mem.scala 70:84] - node _T_290 = mux(_T_289, UInt<1>("h01"), UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 70:74] - node redundant_lru_in = mux(io.iccm_buf_correct_ecc, _T_288, _T_290) @[el2_ifu_iccm_mem.scala 70:29] - reg _T_291 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + node _T_286 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 70:20] + node r0_addr_en = and(_T_286, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 70:35] + node r1_addr_en = and(redundant_lru, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 71:35] + node _T_287 = orr(sel_red0) @[el2_ifu_iccm_mem.scala 72:63] + node _T_288 = orr(sel_red1) @[el2_ifu_iccm_mem.scala 72:78] + node _T_289 = or(_T_287, _T_288) @[el2_ifu_iccm_mem.scala 72:67] + node _T_290 = and(_T_289, io.iccm_rden) @[el2_ifu_iccm_mem.scala 72:83] + node _T_291 = and(_T_290, io.iccm_correction_state) @[el2_ifu_iccm_mem.scala 72:98] + node redundant_lru_en = or(io.iccm_buf_correct_ecc, _T_291) @[el2_ifu_iccm_mem.scala 72:50] + node _T_292 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 73:55] + node _T_293 = orr(sel_red0) @[el2_ifu_iccm_mem.scala 73:84] + node _T_294 = mux(_T_293, UInt<1>("h01"), UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 73:74] + node redundant_lru_in = mux(io.iccm_buf_correct_ecc, _T_292, _T_294) @[el2_ifu_iccm_mem.scala 73:29] + reg _T_295 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when redundant_lru_en : @[Reg.scala 28:19] - _T_291 <= redundant_lru_in @[Reg.scala 28:23] + _T_295 <= redundant_lru_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - redundant_lru <= _T_291 @[el2_ifu_iccm_mem.scala 71:17] - node _T_292 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 72:52] - reg _T_293 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + redundant_lru <= _T_295 @[el2_ifu_iccm_mem.scala 74:17] + node _T_296 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 75:52] + reg _T_297 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when r0_addr_en : @[Reg.scala 28:19] - _T_293 <= _T_292 @[Reg.scala 28:23] + _T_297 <= _T_296 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - redundant_address[0] <= _T_293 @[el2_ifu_iccm_mem.scala 72:24] - node _T_294 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 73:52] - node _T_295 = bits(r1_addr_en, 0, 0) @[el2_ifu_iccm_mem.scala 73:85] - reg _T_296 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_295 : @[Reg.scala 28:19] - _T_296 <= _T_294 @[Reg.scala 28:23] + redundant_address[0] <= _T_297 @[el2_ifu_iccm_mem.scala 75:24] + node _T_298 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 76:52] + node _T_299 = bits(r1_addr_en, 0, 0) @[el2_ifu_iccm_mem.scala 76:85] + reg _T_300 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_299 : @[Reg.scala 28:19] + _T_300 <= _T_298 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - redundant_address[1] <= _T_296 @[el2_ifu_iccm_mem.scala 73:24] - node _T_297 = bits(r1_addr_en, 0, 0) @[el2_ifu_iccm_mem.scala 74:57] - reg _T_298 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_297 : @[Reg.scala 28:19] - _T_298 <= UInt<1>("h01") @[Reg.scala 28:23] + redundant_address[1] <= _T_300 @[el2_ifu_iccm_mem.scala 76:24] + node _T_301 = bits(r1_addr_en, 0, 0) @[el2_ifu_iccm_mem.scala 77:57] + reg _T_302 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_301 : @[Reg.scala 28:19] + _T_302 <= UInt<1>("h01") @[Reg.scala 28:23] skip @[Reg.scala 28:19] - reg _T_299 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + reg _T_303 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when r0_addr_en : @[Reg.scala 28:19] - _T_299 <= UInt<1>("h01") @[Reg.scala 28:23] + _T_303 <= UInt<1>("h01") @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_300 = cat(_T_298, _T_299) @[Cat.scala 29:58] - redundant_valid <= _T_300 @[el2_ifu_iccm_mem.scala 74:19] - node _T_301 = bits(io.iccm_rw_addr, 14, 2) @[el2_ifu_iccm_mem.scala 76:45] - node _T_302 = bits(redundant_address[0], 13, 1) @[el2_ifu_iccm_mem.scala 76:85] - node _T_303 = eq(_T_301, _T_302) @[el2_ifu_iccm_mem.scala 76:61] - node _T_304 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 77:22] - node _T_305 = bits(redundant_address[0], 0, 0) @[el2_ifu_iccm_mem.scala 77:48] - node _T_306 = and(_T_304, _T_305) @[el2_ifu_iccm_mem.scala 77:26] - node _T_307 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 77:70] - node _T_308 = eq(_T_307, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 77:75] - node _T_309 = or(_T_306, _T_308) @[el2_ifu_iccm_mem.scala 77:52] - node _T_310 = and(_T_303, _T_309) @[el2_ifu_iccm_mem.scala 76:102] - node _T_311 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 77:101] - node _T_312 = and(_T_310, _T_311) @[el2_ifu_iccm_mem.scala 77:84] - node _T_313 = and(_T_312, io.iccm_wren) @[el2_ifu_iccm_mem.scala 77:105] - node _T_314 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 78:6] - node _T_315 = and(_T_314, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 78:21] - node redundant_data0_en = or(_T_313, _T_315) @[el2_ifu_iccm_mem.scala 77:121] - node _T_316 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 79:49] - node _T_317 = bits(redundant_address[0], 0, 0) @[el2_ifu_iccm_mem.scala 79:73] - node _T_318 = and(_T_316, _T_317) @[el2_ifu_iccm_mem.scala 79:52] - node _T_319 = bits(redundant_address[0], 0, 0) @[el2_ifu_iccm_mem.scala 79:100] - node _T_320 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 79:122] - node _T_321 = eq(_T_320, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 79:127] - node _T_322 = and(_T_319, _T_321) @[el2_ifu_iccm_mem.scala 79:104] - node _T_323 = or(_T_318, _T_322) @[el2_ifu_iccm_mem.scala 79:78] - node _T_324 = bits(_T_323, 0, 0) @[el2_ifu_iccm_mem.scala 79:137] - node _T_325 = bits(io.iccm_wr_data, 77, 39) @[el2_ifu_iccm_mem.scala 80:20] - node _T_326 = bits(io.iccm_wr_data, 38, 0) @[el2_ifu_iccm_mem.scala 80:44] - node redundant_data0_in = mux(_T_324, _T_325, _T_326) @[el2_ifu_iccm_mem.scala 79:31] - node _T_327 = bits(redundant_data0_en, 0, 0) @[el2_ifu_iccm_mem.scala 81:78] - reg _T_328 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_327 : @[Reg.scala 28:19] - _T_328 <= redundant_data0_in @[Reg.scala 28:23] + node _T_304 = cat(_T_302, _T_303) @[Cat.scala 29:58] + redundant_valid <= _T_304 @[el2_ifu_iccm_mem.scala 77:19] + node _T_305 = bits(io.iccm_rw_addr, 14, 2) @[el2_ifu_iccm_mem.scala 79:45] + node _T_306 = bits(redundant_address[0], 13, 1) @[el2_ifu_iccm_mem.scala 79:85] + node _T_307 = eq(_T_305, _T_306) @[el2_ifu_iccm_mem.scala 79:61] + node _T_308 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 80:22] + node _T_309 = bits(redundant_address[0], 0, 0) @[el2_ifu_iccm_mem.scala 80:48] + node _T_310 = and(_T_308, _T_309) @[el2_ifu_iccm_mem.scala 80:26] + node _T_311 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 80:70] + node _T_312 = eq(_T_311, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 80:75] + node _T_313 = or(_T_310, _T_312) @[el2_ifu_iccm_mem.scala 80:52] + node _T_314 = and(_T_307, _T_313) @[el2_ifu_iccm_mem.scala 79:102] + node _T_315 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 80:101] + node _T_316 = and(_T_314, _T_315) @[el2_ifu_iccm_mem.scala 80:84] + node _T_317 = and(_T_316, io.iccm_wren) @[el2_ifu_iccm_mem.scala 80:105] + node _T_318 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 81:6] + node _T_319 = and(_T_318, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 81:21] + node redundant_data0_en = or(_T_317, _T_319) @[el2_ifu_iccm_mem.scala 80:121] + node _T_320 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 82:49] + node _T_321 = bits(redundant_address[0], 0, 0) @[el2_ifu_iccm_mem.scala 82:73] + node _T_322 = and(_T_320, _T_321) @[el2_ifu_iccm_mem.scala 82:52] + node _T_323 = bits(redundant_address[0], 0, 0) @[el2_ifu_iccm_mem.scala 82:100] + node _T_324 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 82:122] + node _T_325 = eq(_T_324, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 82:127] + node _T_326 = and(_T_323, _T_325) @[el2_ifu_iccm_mem.scala 82:104] + node _T_327 = or(_T_322, _T_326) @[el2_ifu_iccm_mem.scala 82:78] + node _T_328 = bits(_T_327, 0, 0) @[el2_ifu_iccm_mem.scala 82:137] + node _T_329 = bits(io.iccm_wr_data, 77, 39) @[el2_ifu_iccm_mem.scala 83:20] + node _T_330 = bits(io.iccm_wr_data, 38, 0) @[el2_ifu_iccm_mem.scala 83:44] + node redundant_data0_in = mux(_T_328, _T_329, _T_330) @[el2_ifu_iccm_mem.scala 82:31] + node _T_331 = bits(redundant_data0_en, 0, 0) @[el2_ifu_iccm_mem.scala 84:78] + reg _T_332 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_331 : @[Reg.scala 28:19] + _T_332 <= redundant_data0_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - redundant_data[0] <= _T_328 @[el2_ifu_iccm_mem.scala 81:21] - node _T_329 = bits(io.iccm_rw_addr, 14, 2) @[el2_ifu_iccm_mem.scala 83:45] - node _T_330 = bits(redundant_address[1], 13, 1) @[el2_ifu_iccm_mem.scala 83:85] - node _T_331 = eq(_T_329, _T_330) @[el2_ifu_iccm_mem.scala 83:61] - node _T_332 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 84:22] - node _T_333 = bits(redundant_address[1], 0, 0) @[el2_ifu_iccm_mem.scala 84:48] - node _T_334 = and(_T_332, _T_333) @[el2_ifu_iccm_mem.scala 84:26] - node _T_335 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 84:70] - node _T_336 = eq(_T_335, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 84:75] - node _T_337 = or(_T_334, _T_336) @[el2_ifu_iccm_mem.scala 84:52] - node _T_338 = and(_T_331, _T_337) @[el2_ifu_iccm_mem.scala 83:102] - node _T_339 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 84:101] - node _T_340 = and(_T_338, _T_339) @[el2_ifu_iccm_mem.scala 84:84] - node _T_341 = and(_T_340, io.iccm_wren) @[el2_ifu_iccm_mem.scala 84:105] - node _T_342 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 85:6] - node _T_343 = and(_T_342, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 85:21] - node redundant_data1_en = or(_T_341, _T_343) @[el2_ifu_iccm_mem.scala 84:121] - node _T_344 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 86:49] - node _T_345 = bits(redundant_address[1], 0, 0) @[el2_ifu_iccm_mem.scala 86:73] - node _T_346 = and(_T_344, _T_345) @[el2_ifu_iccm_mem.scala 86:52] - node _T_347 = bits(redundant_address[1], 0, 0) @[el2_ifu_iccm_mem.scala 86:100] - node _T_348 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 86:122] - node _T_349 = eq(_T_348, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 86:127] - node _T_350 = and(_T_347, _T_349) @[el2_ifu_iccm_mem.scala 86:104] - node _T_351 = or(_T_346, _T_350) @[el2_ifu_iccm_mem.scala 86:78] - node _T_352 = bits(_T_351, 0, 0) @[el2_ifu_iccm_mem.scala 86:137] - node _T_353 = bits(io.iccm_wr_data, 77, 39) @[el2_ifu_iccm_mem.scala 87:20] - node _T_354 = bits(io.iccm_wr_data, 38, 0) @[el2_ifu_iccm_mem.scala 87:44] - node redundant_data1_in = mux(_T_352, _T_353, _T_354) @[el2_ifu_iccm_mem.scala 86:31] - node _T_355 = bits(redundant_data1_en, 0, 0) @[el2_ifu_iccm_mem.scala 88:78] - reg _T_356 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_355 : @[Reg.scala 28:19] - _T_356 <= redundant_data1_in @[Reg.scala 28:23] + redundant_data[0] <= _T_332 @[el2_ifu_iccm_mem.scala 84:21] + node _T_333 = bits(io.iccm_rw_addr, 14, 2) @[el2_ifu_iccm_mem.scala 86:45] + node _T_334 = bits(redundant_address[1], 13, 1) @[el2_ifu_iccm_mem.scala 86:85] + node _T_335 = eq(_T_333, _T_334) @[el2_ifu_iccm_mem.scala 86:61] + node _T_336 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 87:22] + node _T_337 = bits(redundant_address[1], 0, 0) @[el2_ifu_iccm_mem.scala 87:48] + node _T_338 = and(_T_336, _T_337) @[el2_ifu_iccm_mem.scala 87:26] + node _T_339 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 87:70] + node _T_340 = eq(_T_339, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 87:75] + node _T_341 = or(_T_338, _T_340) @[el2_ifu_iccm_mem.scala 87:52] + node _T_342 = and(_T_335, _T_341) @[el2_ifu_iccm_mem.scala 86:102] + node _T_343 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 87:101] + node _T_344 = and(_T_342, _T_343) @[el2_ifu_iccm_mem.scala 87:84] + node _T_345 = and(_T_344, io.iccm_wren) @[el2_ifu_iccm_mem.scala 87:105] + node _T_346 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 88:6] + node _T_347 = and(_T_346, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 88:21] + node redundant_data1_en = or(_T_345, _T_347) @[el2_ifu_iccm_mem.scala 87:121] + node _T_348 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 89:49] + node _T_349 = bits(redundant_address[1], 0, 0) @[el2_ifu_iccm_mem.scala 89:73] + node _T_350 = and(_T_348, _T_349) @[el2_ifu_iccm_mem.scala 89:52] + node _T_351 = bits(redundant_address[1], 0, 0) @[el2_ifu_iccm_mem.scala 89:100] + node _T_352 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 89:122] + node _T_353 = eq(_T_352, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 89:127] + node _T_354 = and(_T_351, _T_353) @[el2_ifu_iccm_mem.scala 89:104] + node _T_355 = or(_T_350, _T_354) @[el2_ifu_iccm_mem.scala 89:78] + node _T_356 = bits(_T_355, 0, 0) @[el2_ifu_iccm_mem.scala 89:137] + node _T_357 = bits(io.iccm_wr_data, 77, 39) @[el2_ifu_iccm_mem.scala 90:20] + node _T_358 = bits(io.iccm_wr_data, 38, 0) @[el2_ifu_iccm_mem.scala 90:44] + node redundant_data1_in = mux(_T_356, _T_357, _T_358) @[el2_ifu_iccm_mem.scala 89:31] + node _T_359 = bits(redundant_data1_en, 0, 0) @[el2_ifu_iccm_mem.scala 91:78] + reg _T_360 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_359 : @[Reg.scala 28:19] + _T_360 <= redundant_data1_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - redundant_data[1] <= _T_356 @[el2_ifu_iccm_mem.scala 88:21] - node _T_357 = bits(io.iccm_rw_addr, 2, 0) @[el2_ifu_iccm_mem.scala 90:50] - reg iccm_rd_addr_lo_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 90:34] - iccm_rd_addr_lo_q <= _T_357 @[el2_ifu_iccm_mem.scala 90:34] - node _T_358 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 91:48] - reg iccm_rd_addr_hi_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 91:34] - iccm_rd_addr_hi_q <= _T_358 @[el2_ifu_iccm_mem.scala 91:34] - node _T_359 = eq(iccm_rd_addr_hi_q, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 93:86] - node _T_360 = bits(iccm_bank_dout_fn_0, 31, 0) @[el2_ifu_iccm_mem.scala 93:115] - node _T_361 = eq(iccm_rd_addr_hi_q, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 93:86] - node _T_362 = bits(iccm_bank_dout_fn_1, 31, 0) @[el2_ifu_iccm_mem.scala 93:115] - node _T_363 = eq(iccm_rd_addr_hi_q, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 93:86] - node _T_364 = bits(iccm_bank_dout_fn_2, 31, 0) @[el2_ifu_iccm_mem.scala 93:115] - node _T_365 = eq(iccm_rd_addr_hi_q, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 93:86] - node _T_366 = bits(iccm_bank_dout_fn_3, 31, 0) @[el2_ifu_iccm_mem.scala 93:115] - node _T_367 = mux(_T_359, _T_360, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_368 = mux(_T_361, _T_362, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_369 = mux(_T_363, _T_364, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_370 = mux(_T_365, _T_366, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_371 = or(_T_367, _T_368) @[Mux.scala 27:72] - node _T_372 = or(_T_371, _T_369) @[Mux.scala 27:72] - node _T_373 = or(_T_372, _T_370) @[Mux.scala 27:72] - wire _T_374 : UInt<32> @[Mux.scala 27:72] - _T_374 <= _T_373 @[Mux.scala 27:72] - node _T_375 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 94:59] - node _T_376 = eq(_T_375, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 94:77] - node _T_377 = bits(iccm_bank_dout_fn_0, 31, 0) @[el2_ifu_iccm_mem.scala 94:106] - node _T_378 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 94:59] - node _T_379 = eq(_T_378, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 94:77] - node _T_380 = bits(iccm_bank_dout_fn_1, 31, 0) @[el2_ifu_iccm_mem.scala 94:106] - node _T_381 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 94:59] - node _T_382 = eq(_T_381, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 94:77] - node _T_383 = bits(iccm_bank_dout_fn_2, 31, 0) @[el2_ifu_iccm_mem.scala 94:106] - node _T_384 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 94:59] - node _T_385 = eq(_T_384, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 94:77] - node _T_386 = bits(iccm_bank_dout_fn_3, 31, 0) @[el2_ifu_iccm_mem.scala 94:106] - node _T_387 = mux(_T_376, _T_377, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_388 = mux(_T_379, _T_380, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_389 = mux(_T_382, _T_383, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_390 = mux(_T_385, _T_386, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_391 = or(_T_387, _T_388) @[Mux.scala 27:72] - node _T_392 = or(_T_391, _T_389) @[Mux.scala 27:72] - node _T_393 = or(_T_392, _T_390) @[Mux.scala 27:72] - wire _T_394 : UInt<32> @[Mux.scala 27:72] - _T_394 <= _T_393 @[Mux.scala 27:72] - node iccm_rd_data_pre = cat(_T_374, _T_394) @[Cat.scala 29:58] - node _T_395 = bits(iccm_rd_addr_lo_q, 0, 0) @[el2_ifu_iccm_mem.scala 95:43] - node _T_396 = bits(_T_395, 0, 0) @[el2_ifu_iccm_mem.scala 95:53] - node _T_397 = mux(UInt<1>("h00"), UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12] - node _T_398 = bits(iccm_rd_data_pre, 63, 16) @[el2_ifu_iccm_mem.scala 95:89] - node _T_399 = cat(_T_397, _T_398) @[Cat.scala 29:58] - node _T_400 = mux(_T_396, _T_399, iccm_rd_data_pre) @[el2_ifu_iccm_mem.scala 95:25] - io.iccm_rd_data <= _T_400 @[el2_ifu_iccm_mem.scala 95:19] - node _T_401 = eq(iccm_rd_addr_hi_q, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 96:85] - node _T_402 = eq(iccm_rd_addr_hi_q, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 96:85] - node _T_403 = eq(iccm_rd_addr_hi_q, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 96:85] - node _T_404 = eq(iccm_rd_addr_hi_q, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 96:85] - node _T_405 = mux(_T_401, iccm_bank_dout_fn_0, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_406 = mux(_T_402, iccm_bank_dout_fn_1, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_407 = mux(_T_403, iccm_bank_dout_fn_2, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_408 = mux(_T_404, iccm_bank_dout_fn_3, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_409 = or(_T_405, _T_406) @[Mux.scala 27:72] - node _T_410 = or(_T_409, _T_407) @[Mux.scala 27:72] - node _T_411 = or(_T_410, _T_408) @[Mux.scala 27:72] - wire _T_412 : UInt<39> @[Mux.scala 27:72] - _T_412 <= _T_411 @[Mux.scala 27:72] - node _T_413 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 97:61] - node _T_414 = eq(_T_413, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 97:79] - node _T_415 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 97:61] - node _T_416 = eq(_T_415, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 97:79] - node _T_417 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 97:61] - node _T_418 = eq(_T_417, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 97:79] - node _T_419 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 97:61] - node _T_420 = eq(_T_419, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 97:79] - node _T_421 = mux(_T_414, iccm_bank_dout_fn_0, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_422 = mux(_T_416, iccm_bank_dout_fn_1, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_423 = mux(_T_418, iccm_bank_dout_fn_2, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_424 = mux(_T_420, iccm_bank_dout_fn_3, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_425 = or(_T_421, _T_422) @[Mux.scala 27:72] - node _T_426 = or(_T_425, _T_423) @[Mux.scala 27:72] - node _T_427 = or(_T_426, _T_424) @[Mux.scala 27:72] - wire _T_428 : UInt<39> @[Mux.scala 27:72] - _T_428 <= _T_427 @[Mux.scala 27:72] - node _T_429 = cat(_T_412, _T_428) @[Cat.scala 29:58] - io.iccm_rd_data_ecc <= _T_429 @[el2_ifu_iccm_mem.scala 96:23] + redundant_data[1] <= _T_360 @[el2_ifu_iccm_mem.scala 91:21] + node _T_361 = bits(io.iccm_rw_addr, 2, 0) @[el2_ifu_iccm_mem.scala 93:50] + reg iccm_rd_addr_lo_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 93:34] + iccm_rd_addr_lo_q <= _T_361 @[el2_ifu_iccm_mem.scala 93:34] + node _T_362 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 94:48] + reg iccm_rd_addr_hi_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 94:34] + iccm_rd_addr_hi_q <= _T_362 @[el2_ifu_iccm_mem.scala 94:34] + node _T_363 = eq(iccm_rd_addr_hi_q, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 96:86] + node _T_364 = bits(iccm_bank_dout_fn_0, 31, 0) @[el2_ifu_iccm_mem.scala 96:115] + node _T_365 = eq(iccm_rd_addr_hi_q, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 96:86] + node _T_366 = bits(iccm_bank_dout_fn_1, 31, 0) @[el2_ifu_iccm_mem.scala 96:115] + node _T_367 = eq(iccm_rd_addr_hi_q, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 96:86] + node _T_368 = bits(iccm_bank_dout_fn_2, 31, 0) @[el2_ifu_iccm_mem.scala 96:115] + node _T_369 = eq(iccm_rd_addr_hi_q, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 96:86] + node _T_370 = bits(iccm_bank_dout_fn_3, 31, 0) @[el2_ifu_iccm_mem.scala 96:115] + node _T_371 = mux(_T_363, _T_364, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_372 = mux(_T_365, _T_366, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_373 = mux(_T_367, _T_368, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_374 = mux(_T_369, _T_370, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_375 = or(_T_371, _T_372) @[Mux.scala 27:72] + node _T_376 = or(_T_375, _T_373) @[Mux.scala 27:72] + node _T_377 = or(_T_376, _T_374) @[Mux.scala 27:72] + wire _T_378 : UInt<32> @[Mux.scala 27:72] + _T_378 <= _T_377 @[Mux.scala 27:72] + node _T_379 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 97:59] + node _T_380 = eq(_T_379, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 97:77] + node _T_381 = bits(iccm_bank_dout_fn_0, 31, 0) @[el2_ifu_iccm_mem.scala 97:106] + node _T_382 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 97:59] + node _T_383 = eq(_T_382, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 97:77] + node _T_384 = bits(iccm_bank_dout_fn_1, 31, 0) @[el2_ifu_iccm_mem.scala 97:106] + node _T_385 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 97:59] + node _T_386 = eq(_T_385, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 97:77] + node _T_387 = bits(iccm_bank_dout_fn_2, 31, 0) @[el2_ifu_iccm_mem.scala 97:106] + node _T_388 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 97:59] + node _T_389 = eq(_T_388, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 97:77] + node _T_390 = bits(iccm_bank_dout_fn_3, 31, 0) @[el2_ifu_iccm_mem.scala 97:106] + node _T_391 = mux(_T_380, _T_381, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_392 = mux(_T_383, _T_384, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_393 = mux(_T_386, _T_387, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_394 = mux(_T_389, _T_390, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_395 = or(_T_391, _T_392) @[Mux.scala 27:72] + node _T_396 = or(_T_395, _T_393) @[Mux.scala 27:72] + node _T_397 = or(_T_396, _T_394) @[Mux.scala 27:72] + wire _T_398 : UInt<32> @[Mux.scala 27:72] + _T_398 <= _T_397 @[Mux.scala 27:72] + node iccm_rd_data_pre = cat(_T_378, _T_398) @[Cat.scala 29:58] + node _T_399 = bits(iccm_rd_addr_lo_q, 0, 0) @[el2_ifu_iccm_mem.scala 98:43] + node _T_400 = bits(_T_399, 0, 0) @[el2_ifu_iccm_mem.scala 98:53] + node _T_401 = mux(UInt<1>("h00"), UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12] + node _T_402 = bits(iccm_rd_data_pre, 63, 16) @[el2_ifu_iccm_mem.scala 98:89] + node _T_403 = cat(_T_401, _T_402) @[Cat.scala 29:58] + node _T_404 = mux(_T_400, _T_403, iccm_rd_data_pre) @[el2_ifu_iccm_mem.scala 98:25] + io.iccm_rd_data <= _T_404 @[el2_ifu_iccm_mem.scala 98:19] + node _T_405 = eq(iccm_rd_addr_hi_q, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 99:85] + node _T_406 = eq(iccm_rd_addr_hi_q, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 99:85] + node _T_407 = eq(iccm_rd_addr_hi_q, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 99:85] + node _T_408 = eq(iccm_rd_addr_hi_q, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 99:85] + node _T_409 = mux(_T_405, iccm_bank_dout_fn_0, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_410 = mux(_T_406, iccm_bank_dout_fn_1, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_411 = mux(_T_407, iccm_bank_dout_fn_2, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_412 = mux(_T_408, iccm_bank_dout_fn_3, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_413 = or(_T_409, _T_410) @[Mux.scala 27:72] + node _T_414 = or(_T_413, _T_411) @[Mux.scala 27:72] + node _T_415 = or(_T_414, _T_412) @[Mux.scala 27:72] + wire _T_416 : UInt<39> @[Mux.scala 27:72] + _T_416 <= _T_415 @[Mux.scala 27:72] + node _T_417 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 100:61] + node _T_418 = eq(_T_417, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 100:79] + node _T_419 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 100:61] + node _T_420 = eq(_T_419, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 100:79] + node _T_421 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 100:61] + node _T_422 = eq(_T_421, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 100:79] + node _T_423 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 100:61] + node _T_424 = eq(_T_423, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 100:79] + node _T_425 = mux(_T_418, iccm_bank_dout_fn_0, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_426 = mux(_T_420, iccm_bank_dout_fn_1, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_427 = mux(_T_422, iccm_bank_dout_fn_2, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_428 = mux(_T_424, iccm_bank_dout_fn_3, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_429 = or(_T_425, _T_426) @[Mux.scala 27:72] + node _T_430 = or(_T_429, _T_427) @[Mux.scala 27:72] + node _T_431 = or(_T_430, _T_428) @[Mux.scala 27:72] + wire _T_432 : UInt<39> @[Mux.scala 27:72] + _T_432 <= _T_431 @[Mux.scala 27:72] + node _T_433 = cat(_T_416, _T_432) @[Cat.scala 29:58] + io.iccm_rd_data_ecc <= _T_433 @[el2_ifu_iccm_mem.scala 99:23] diff --git a/el2_ifu_iccm_mem.v b/el2_ifu_iccm_mem.v index 9e673bcd..2a0216e0 100644 --- a/el2_ifu_iccm_mem.v +++ b/el2_ifu_iccm_mem.v @@ -11,7 +11,11 @@ module el2_ifu_iccm_mem( input [77:0] io_iccm_wr_data, output [63:0] io_iccm_rd_data, output [77:0] io_iccm_rd_data_ecc, - input io_scan_mode + input io_scan_mode, + output [38:0] io_iccm_bank_wr_data_0, + output [38:0] io_iccm_bank_wr_data_1, + output [38:0] io_iccm_bank_wr_data_2, + output [38:0] io_iccm_bank_wr_data_3 ); `ifdef RANDOMIZE_MEM_INIT reg [63:0] _RAND_0; @@ -20,94 +24,98 @@ module el2_ifu_iccm_mem( reg [63:0] _RAND_3; `endif // RANDOMIZE_MEM_INIT `ifdef RANDOMIZE_REG_INIT - reg [31:0] _RAND_4; - reg [31:0] _RAND_5; - reg [31:0] _RAND_6; - reg [31:0] _RAND_7; + reg [63:0] _RAND_4; + reg [63:0] _RAND_5; + reg [63:0] _RAND_6; + reg [63:0] _RAND_7; reg [31:0] _RAND_8; reg [31:0] _RAND_9; - reg [63:0] _RAND_10; - reg [63:0] _RAND_11; + reg [31:0] _RAND_10; + reg [31:0] _RAND_11; reg [31:0] _RAND_12; reg [31:0] _RAND_13; - reg [31:0] _RAND_14; + reg [63:0] _RAND_14; + reg [63:0] _RAND_15; + reg [31:0] _RAND_16; + reg [31:0] _RAND_17; + reg [31:0] _RAND_18; `endif // RANDOMIZE_REG_INIT - reg [38:0] iccm_mem_0 [0:4095]; // @[el2_ifu_iccm_mem.scala 40:21] - wire [38:0] iccm_mem_0__T_97_data; // @[el2_ifu_iccm_mem.scala 40:21] - wire [11:0] iccm_mem_0__T_97_addr; // @[el2_ifu_iccm_mem.scala 40:21] - wire [38:0] iccm_mem_0__T_93_data; // @[el2_ifu_iccm_mem.scala 40:21] - wire [11:0] iccm_mem_0__T_93_addr; // @[el2_ifu_iccm_mem.scala 40:21] - wire iccm_mem_0__T_93_mask; // @[el2_ifu_iccm_mem.scala 40:21] - wire iccm_mem_0__T_93_en; // @[el2_ifu_iccm_mem.scala 40:21] - wire [38:0] iccm_mem_0__T_94_data; // @[el2_ifu_iccm_mem.scala 40:21] - wire [11:0] iccm_mem_0__T_94_addr; // @[el2_ifu_iccm_mem.scala 40:21] - wire iccm_mem_0__T_94_mask; // @[el2_ifu_iccm_mem.scala 40:21] - wire iccm_mem_0__T_94_en; // @[el2_ifu_iccm_mem.scala 40:21] - wire [38:0] iccm_mem_0__T_95_data; // @[el2_ifu_iccm_mem.scala 40:21] - wire [11:0] iccm_mem_0__T_95_addr; // @[el2_ifu_iccm_mem.scala 40:21] - wire iccm_mem_0__T_95_mask; // @[el2_ifu_iccm_mem.scala 40:21] - wire iccm_mem_0__T_95_en; // @[el2_ifu_iccm_mem.scala 40:21] - wire [38:0] iccm_mem_0__T_96_data; // @[el2_ifu_iccm_mem.scala 40:21] - wire [11:0] iccm_mem_0__T_96_addr; // @[el2_ifu_iccm_mem.scala 40:21] - wire iccm_mem_0__T_96_mask; // @[el2_ifu_iccm_mem.scala 40:21] - wire iccm_mem_0__T_96_en; // @[el2_ifu_iccm_mem.scala 40:21] - reg [38:0] iccm_mem_1 [0:4095]; // @[el2_ifu_iccm_mem.scala 40:21] - wire [38:0] iccm_mem_1__T_97_data; // @[el2_ifu_iccm_mem.scala 40:21] - wire [11:0] iccm_mem_1__T_97_addr; // @[el2_ifu_iccm_mem.scala 40:21] - wire [38:0] iccm_mem_1__T_93_data; // @[el2_ifu_iccm_mem.scala 40:21] - wire [11:0] iccm_mem_1__T_93_addr; // @[el2_ifu_iccm_mem.scala 40:21] - wire iccm_mem_1__T_93_mask; // @[el2_ifu_iccm_mem.scala 40:21] - wire iccm_mem_1__T_93_en; // @[el2_ifu_iccm_mem.scala 40:21] - wire [38:0] iccm_mem_1__T_94_data; // @[el2_ifu_iccm_mem.scala 40:21] - wire [11:0] iccm_mem_1__T_94_addr; // @[el2_ifu_iccm_mem.scala 40:21] - wire iccm_mem_1__T_94_mask; // @[el2_ifu_iccm_mem.scala 40:21] - wire iccm_mem_1__T_94_en; // @[el2_ifu_iccm_mem.scala 40:21] - wire [38:0] iccm_mem_1__T_95_data; // @[el2_ifu_iccm_mem.scala 40:21] - wire [11:0] iccm_mem_1__T_95_addr; // @[el2_ifu_iccm_mem.scala 40:21] - wire iccm_mem_1__T_95_mask; // @[el2_ifu_iccm_mem.scala 40:21] - wire iccm_mem_1__T_95_en; // @[el2_ifu_iccm_mem.scala 40:21] - wire [38:0] iccm_mem_1__T_96_data; // @[el2_ifu_iccm_mem.scala 40:21] - wire [11:0] iccm_mem_1__T_96_addr; // @[el2_ifu_iccm_mem.scala 40:21] - wire iccm_mem_1__T_96_mask; // @[el2_ifu_iccm_mem.scala 40:21] - wire iccm_mem_1__T_96_en; // @[el2_ifu_iccm_mem.scala 40:21] - reg [38:0] iccm_mem_2 [0:4095]; // @[el2_ifu_iccm_mem.scala 40:21] - wire [38:0] iccm_mem_2__T_97_data; // @[el2_ifu_iccm_mem.scala 40:21] - wire [11:0] iccm_mem_2__T_97_addr; // @[el2_ifu_iccm_mem.scala 40:21] - wire [38:0] iccm_mem_2__T_93_data; // @[el2_ifu_iccm_mem.scala 40:21] - wire [11:0] iccm_mem_2__T_93_addr; // @[el2_ifu_iccm_mem.scala 40:21] - wire iccm_mem_2__T_93_mask; // @[el2_ifu_iccm_mem.scala 40:21] - wire iccm_mem_2__T_93_en; // @[el2_ifu_iccm_mem.scala 40:21] - wire [38:0] iccm_mem_2__T_94_data; // @[el2_ifu_iccm_mem.scala 40:21] - wire [11:0] iccm_mem_2__T_94_addr; // @[el2_ifu_iccm_mem.scala 40:21] - wire iccm_mem_2__T_94_mask; // @[el2_ifu_iccm_mem.scala 40:21] - wire iccm_mem_2__T_94_en; // @[el2_ifu_iccm_mem.scala 40:21] - wire [38:0] iccm_mem_2__T_95_data; // @[el2_ifu_iccm_mem.scala 40:21] - wire [11:0] iccm_mem_2__T_95_addr; // @[el2_ifu_iccm_mem.scala 40:21] - wire iccm_mem_2__T_95_mask; // @[el2_ifu_iccm_mem.scala 40:21] - wire iccm_mem_2__T_95_en; // @[el2_ifu_iccm_mem.scala 40:21] - wire [38:0] iccm_mem_2__T_96_data; // @[el2_ifu_iccm_mem.scala 40:21] - wire [11:0] iccm_mem_2__T_96_addr; // @[el2_ifu_iccm_mem.scala 40:21] - wire iccm_mem_2__T_96_mask; // @[el2_ifu_iccm_mem.scala 40:21] - wire iccm_mem_2__T_96_en; // @[el2_ifu_iccm_mem.scala 40:21] - reg [38:0] iccm_mem_3 [0:4095]; // @[el2_ifu_iccm_mem.scala 40:21] - wire [38:0] iccm_mem_3__T_97_data; // @[el2_ifu_iccm_mem.scala 40:21] - wire [11:0] iccm_mem_3__T_97_addr; // @[el2_ifu_iccm_mem.scala 40:21] - wire [38:0] iccm_mem_3__T_93_data; // @[el2_ifu_iccm_mem.scala 40:21] - wire [11:0] iccm_mem_3__T_93_addr; // @[el2_ifu_iccm_mem.scala 40:21] - wire iccm_mem_3__T_93_mask; // @[el2_ifu_iccm_mem.scala 40:21] - wire iccm_mem_3__T_93_en; // @[el2_ifu_iccm_mem.scala 40:21] - wire [38:0] iccm_mem_3__T_94_data; // @[el2_ifu_iccm_mem.scala 40:21] - wire [11:0] iccm_mem_3__T_94_addr; // @[el2_ifu_iccm_mem.scala 40:21] - wire iccm_mem_3__T_94_mask; // @[el2_ifu_iccm_mem.scala 40:21] - wire iccm_mem_3__T_94_en; // @[el2_ifu_iccm_mem.scala 40:21] - wire [38:0] iccm_mem_3__T_95_data; // @[el2_ifu_iccm_mem.scala 40:21] - wire [11:0] iccm_mem_3__T_95_addr; // @[el2_ifu_iccm_mem.scala 40:21] - wire iccm_mem_3__T_95_mask; // @[el2_ifu_iccm_mem.scala 40:21] - wire iccm_mem_3__T_95_en; // @[el2_ifu_iccm_mem.scala 40:21] - wire [38:0] iccm_mem_3__T_96_data; // @[el2_ifu_iccm_mem.scala 40:21] - wire [11:0] iccm_mem_3__T_96_addr; // @[el2_ifu_iccm_mem.scala 40:21] - wire iccm_mem_3__T_96_mask; // @[el2_ifu_iccm_mem.scala 40:21] - wire iccm_mem_3__T_96_en; // @[el2_ifu_iccm_mem.scala 40:21] + reg [38:0] iccm_mem_0 [0:4095]; // @[el2_ifu_iccm_mem.scala 41:21] + wire [38:0] iccm_mem_0__T_97_data; // @[el2_ifu_iccm_mem.scala 41:21] + wire [11:0] iccm_mem_0__T_97_addr; // @[el2_ifu_iccm_mem.scala 41:21] + wire [38:0] iccm_mem_0__T_93_data; // @[el2_ifu_iccm_mem.scala 41:21] + wire [11:0] iccm_mem_0__T_93_addr; // @[el2_ifu_iccm_mem.scala 41:21] + wire iccm_mem_0__T_93_mask; // @[el2_ifu_iccm_mem.scala 41:21] + wire iccm_mem_0__T_93_en; // @[el2_ifu_iccm_mem.scala 41:21] + wire [38:0] iccm_mem_0__T_94_data; // @[el2_ifu_iccm_mem.scala 41:21] + wire [11:0] iccm_mem_0__T_94_addr; // @[el2_ifu_iccm_mem.scala 41:21] + wire iccm_mem_0__T_94_mask; // @[el2_ifu_iccm_mem.scala 41:21] + wire iccm_mem_0__T_94_en; // @[el2_ifu_iccm_mem.scala 41:21] + wire [38:0] iccm_mem_0__T_95_data; // @[el2_ifu_iccm_mem.scala 41:21] + wire [11:0] iccm_mem_0__T_95_addr; // @[el2_ifu_iccm_mem.scala 41:21] + wire iccm_mem_0__T_95_mask; // @[el2_ifu_iccm_mem.scala 41:21] + wire iccm_mem_0__T_95_en; // @[el2_ifu_iccm_mem.scala 41:21] + wire [38:0] iccm_mem_0__T_96_data; // @[el2_ifu_iccm_mem.scala 41:21] + wire [11:0] iccm_mem_0__T_96_addr; // @[el2_ifu_iccm_mem.scala 41:21] + wire iccm_mem_0__T_96_mask; // @[el2_ifu_iccm_mem.scala 41:21] + wire iccm_mem_0__T_96_en; // @[el2_ifu_iccm_mem.scala 41:21] + reg [38:0] iccm_mem_1 [0:4095]; // @[el2_ifu_iccm_mem.scala 41:21] + wire [38:0] iccm_mem_1__T_97_data; // @[el2_ifu_iccm_mem.scala 41:21] + wire [11:0] iccm_mem_1__T_97_addr; // @[el2_ifu_iccm_mem.scala 41:21] + wire [38:0] iccm_mem_1__T_93_data; // @[el2_ifu_iccm_mem.scala 41:21] + wire [11:0] iccm_mem_1__T_93_addr; // @[el2_ifu_iccm_mem.scala 41:21] + wire iccm_mem_1__T_93_mask; // @[el2_ifu_iccm_mem.scala 41:21] + wire iccm_mem_1__T_93_en; // @[el2_ifu_iccm_mem.scala 41:21] + wire [38:0] iccm_mem_1__T_94_data; // @[el2_ifu_iccm_mem.scala 41:21] + wire [11:0] iccm_mem_1__T_94_addr; // @[el2_ifu_iccm_mem.scala 41:21] + wire iccm_mem_1__T_94_mask; // @[el2_ifu_iccm_mem.scala 41:21] + wire iccm_mem_1__T_94_en; // @[el2_ifu_iccm_mem.scala 41:21] + wire [38:0] iccm_mem_1__T_95_data; // @[el2_ifu_iccm_mem.scala 41:21] + wire [11:0] iccm_mem_1__T_95_addr; // @[el2_ifu_iccm_mem.scala 41:21] + wire iccm_mem_1__T_95_mask; // @[el2_ifu_iccm_mem.scala 41:21] + wire iccm_mem_1__T_95_en; // @[el2_ifu_iccm_mem.scala 41:21] + wire [38:0] iccm_mem_1__T_96_data; // @[el2_ifu_iccm_mem.scala 41:21] + wire [11:0] iccm_mem_1__T_96_addr; // @[el2_ifu_iccm_mem.scala 41:21] + wire iccm_mem_1__T_96_mask; // @[el2_ifu_iccm_mem.scala 41:21] + wire iccm_mem_1__T_96_en; // @[el2_ifu_iccm_mem.scala 41:21] + reg [38:0] iccm_mem_2 [0:4095]; // @[el2_ifu_iccm_mem.scala 41:21] + wire [38:0] iccm_mem_2__T_97_data; // @[el2_ifu_iccm_mem.scala 41:21] + wire [11:0] iccm_mem_2__T_97_addr; // @[el2_ifu_iccm_mem.scala 41:21] + wire [38:0] iccm_mem_2__T_93_data; // @[el2_ifu_iccm_mem.scala 41:21] + wire [11:0] iccm_mem_2__T_93_addr; // @[el2_ifu_iccm_mem.scala 41:21] + wire iccm_mem_2__T_93_mask; // @[el2_ifu_iccm_mem.scala 41:21] + wire iccm_mem_2__T_93_en; // @[el2_ifu_iccm_mem.scala 41:21] + wire [38:0] iccm_mem_2__T_94_data; // @[el2_ifu_iccm_mem.scala 41:21] + wire [11:0] iccm_mem_2__T_94_addr; // @[el2_ifu_iccm_mem.scala 41:21] + wire iccm_mem_2__T_94_mask; // @[el2_ifu_iccm_mem.scala 41:21] + wire iccm_mem_2__T_94_en; // @[el2_ifu_iccm_mem.scala 41:21] + wire [38:0] iccm_mem_2__T_95_data; // @[el2_ifu_iccm_mem.scala 41:21] + wire [11:0] iccm_mem_2__T_95_addr; // @[el2_ifu_iccm_mem.scala 41:21] + wire iccm_mem_2__T_95_mask; // @[el2_ifu_iccm_mem.scala 41:21] + wire iccm_mem_2__T_95_en; // @[el2_ifu_iccm_mem.scala 41:21] + wire [38:0] iccm_mem_2__T_96_data; // @[el2_ifu_iccm_mem.scala 41:21] + wire [11:0] iccm_mem_2__T_96_addr; // @[el2_ifu_iccm_mem.scala 41:21] + wire iccm_mem_2__T_96_mask; // @[el2_ifu_iccm_mem.scala 41:21] + wire iccm_mem_2__T_96_en; // @[el2_ifu_iccm_mem.scala 41:21] + reg [38:0] iccm_mem_3 [0:4095]; // @[el2_ifu_iccm_mem.scala 41:21] + wire [38:0] iccm_mem_3__T_97_data; // @[el2_ifu_iccm_mem.scala 41:21] + wire [11:0] iccm_mem_3__T_97_addr; // @[el2_ifu_iccm_mem.scala 41:21] + wire [38:0] iccm_mem_3__T_93_data; // @[el2_ifu_iccm_mem.scala 41:21] + wire [11:0] iccm_mem_3__T_93_addr; // @[el2_ifu_iccm_mem.scala 41:21] + wire iccm_mem_3__T_93_mask; // @[el2_ifu_iccm_mem.scala 41:21] + wire iccm_mem_3__T_93_en; // @[el2_ifu_iccm_mem.scala 41:21] + wire [38:0] iccm_mem_3__T_94_data; // @[el2_ifu_iccm_mem.scala 41:21] + wire [11:0] iccm_mem_3__T_94_addr; // @[el2_ifu_iccm_mem.scala 41:21] + wire iccm_mem_3__T_94_mask; // @[el2_ifu_iccm_mem.scala 41:21] + wire iccm_mem_3__T_94_en; // @[el2_ifu_iccm_mem.scala 41:21] + wire [38:0] iccm_mem_3__T_95_data; // @[el2_ifu_iccm_mem.scala 41:21] + wire [11:0] iccm_mem_3__T_95_addr; // @[el2_ifu_iccm_mem.scala 41:21] + wire iccm_mem_3__T_95_mask; // @[el2_ifu_iccm_mem.scala 41:21] + wire iccm_mem_3__T_95_en; // @[el2_ifu_iccm_mem.scala 41:21] + wire [38:0] iccm_mem_3__T_96_data; // @[el2_ifu_iccm_mem.scala 41:21] + wire [11:0] iccm_mem_3__T_96_addr; // @[el2_ifu_iccm_mem.scala 41:21] + wire iccm_mem_3__T_96_mask; // @[el2_ifu_iccm_mem.scala 41:21] + wire iccm_mem_3__T_96_en; // @[el2_ifu_iccm_mem.scala 41:21] wire _T_1 = io_iccm_wr_size[1:0] == 2'h3; // @[el2_ifu_iccm_mem.scala 24:43] wire [1:0] addr_inc = _T_1 ? 2'h2 : 2'h1; // @[el2_ifu_iccm_mem.scala 24:21] wire [14:0] _GEN_15 = {{13'd0}, addr_inc}; // @[el2_ifu_iccm_mem.scala 25:54] @@ -130,181 +138,181 @@ module el2_ifu_iccm_mem( wire _T_26 = io_iccm_wren & _T_25; // @[el2_ifu_iccm_mem.scala 33:64] wire _T_28 = addr_bank_inc[2:1] == 2'h3; // @[el2_ifu_iccm_mem.scala 33:139] wire wren_bank_3 = _T_26 | _T_28; // @[el2_ifu_iccm_mem.scala 33:106] - wire _T_31 = io_iccm_rden & _T_10; // @[el2_ifu_iccm_mem.scala 35:64] - wire rden_bank_0 = _T_31 | _T_13; // @[el2_ifu_iccm_mem.scala 35:106] - wire _T_36 = io_iccm_rden & _T_15; // @[el2_ifu_iccm_mem.scala 35:64] - wire rden_bank_1 = _T_36 | _T_18; // @[el2_ifu_iccm_mem.scala 35:106] - wire _T_41 = io_iccm_rden & _T_20; // @[el2_ifu_iccm_mem.scala 35:64] - wire rden_bank_2 = _T_41 | _T_23; // @[el2_ifu_iccm_mem.scala 35:106] - wire _T_46 = io_iccm_rden & _T_25; // @[el2_ifu_iccm_mem.scala 35:64] - wire rden_bank_3 = _T_46 | _T_28; // @[el2_ifu_iccm_mem.scala 35:106] - wire _T_49 = wren_bank_0 | rden_bank_0; // @[el2_ifu_iccm_mem.scala 36:72] - wire iccm_clken_0 = _T_49 | io_clk_override; // @[el2_ifu_iccm_mem.scala 36:87] - wire _T_50 = wren_bank_1 | rden_bank_1; // @[el2_ifu_iccm_mem.scala 36:72] - wire iccm_clken_1 = _T_50 | io_clk_override; // @[el2_ifu_iccm_mem.scala 36:87] - wire _T_51 = wren_bank_2 | rden_bank_2; // @[el2_ifu_iccm_mem.scala 36:72] - wire iccm_clken_2 = _T_51 | io_clk_override; // @[el2_ifu_iccm_mem.scala 36:87] - wire _T_52 = wren_bank_3 | rden_bank_3; // @[el2_ifu_iccm_mem.scala 36:72] - wire iccm_clken_3 = _T_52 | io_clk_override; // @[el2_ifu_iccm_mem.scala 36:87] - wire [11:0] _T_59 = _T_13 ? addr_bank_inc[14:3] : io_iccm_rw_addr[14:3]; // @[el2_ifu_iccm_mem.scala 38:8] - wire [11:0] _T_66 = _T_18 ? addr_bank_inc[14:3] : io_iccm_rw_addr[14:3]; // @[el2_ifu_iccm_mem.scala 38:8] - wire [11:0] _T_73 = _T_23 ? addr_bank_inc[14:3] : io_iccm_rw_addr[14:3]; // @[el2_ifu_iccm_mem.scala 38:8] - wire [11:0] _T_80 = _T_28 ? addr_bank_inc[14:3] : io_iccm_rw_addr[14:3]; // @[el2_ifu_iccm_mem.scala 38:8] - reg _T_298; // @[Reg.scala 27:20] - reg _T_299; // @[Reg.scala 27:20] - wire [1:0] redundant_valid = {_T_298,_T_299}; // @[Cat.scala 29:58] + wire _T_31 = io_iccm_rden & _T_10; // @[el2_ifu_iccm_mem.scala 36:64] + wire rden_bank_0 = _T_31 | _T_13; // @[el2_ifu_iccm_mem.scala 36:106] + wire _T_36 = io_iccm_rden & _T_15; // @[el2_ifu_iccm_mem.scala 36:64] + wire rden_bank_1 = _T_36 | _T_18; // @[el2_ifu_iccm_mem.scala 36:106] + wire _T_41 = io_iccm_rden & _T_20; // @[el2_ifu_iccm_mem.scala 36:64] + wire rden_bank_2 = _T_41 | _T_23; // @[el2_ifu_iccm_mem.scala 36:106] + wire _T_46 = io_iccm_rden & _T_25; // @[el2_ifu_iccm_mem.scala 36:64] + wire rden_bank_3 = _T_46 | _T_28; // @[el2_ifu_iccm_mem.scala 36:106] + wire _T_49 = wren_bank_0 | rden_bank_0; // @[el2_ifu_iccm_mem.scala 37:72] + wire iccm_clken_0 = _T_49 | io_clk_override; // @[el2_ifu_iccm_mem.scala 37:87] + wire _T_50 = wren_bank_1 | rden_bank_1; // @[el2_ifu_iccm_mem.scala 37:72] + wire iccm_clken_1 = _T_50 | io_clk_override; // @[el2_ifu_iccm_mem.scala 37:87] + wire _T_51 = wren_bank_2 | rden_bank_2; // @[el2_ifu_iccm_mem.scala 37:72] + wire iccm_clken_2 = _T_51 | io_clk_override; // @[el2_ifu_iccm_mem.scala 37:87] + wire _T_52 = wren_bank_3 | rden_bank_3; // @[el2_ifu_iccm_mem.scala 37:72] + wire iccm_clken_3 = _T_52 | io_clk_override; // @[el2_ifu_iccm_mem.scala 37:87] + wire [11:0] _T_59 = _T_13 ? addr_bank_inc[14:3] : io_iccm_rw_addr[14:3]; // @[el2_ifu_iccm_mem.scala 39:8] + wire [11:0] _T_66 = _T_18 ? addr_bank_inc[14:3] : io_iccm_rw_addr[14:3]; // @[el2_ifu_iccm_mem.scala 39:8] + wire [11:0] _T_73 = _T_23 ? addr_bank_inc[14:3] : io_iccm_rw_addr[14:3]; // @[el2_ifu_iccm_mem.scala 39:8] + wire [11:0] _T_80 = _T_28 ? addr_bank_inc[14:3] : io_iccm_rw_addr[14:3]; // @[el2_ifu_iccm_mem.scala 39:8] + reg [38:0] iccm_bank_dout_0; // @[el2_ifu_iccm_mem.scala 50:62] + reg [38:0] iccm_bank_dout_1; // @[el2_ifu_iccm_mem.scala 50:62] + reg [38:0] iccm_bank_dout_2; // @[el2_ifu_iccm_mem.scala 50:62] + reg [38:0] iccm_bank_dout_3; // @[el2_ifu_iccm_mem.scala 50:62] + reg _T_302; // @[Reg.scala 27:20] + reg _T_303; // @[Reg.scala 27:20] + wire [1:0] redundant_valid = {_T_302,_T_303}; // @[Cat.scala 29:58] reg [13:0] redundant_address_1; // @[Reg.scala 27:20] - wire _T_101 = io_iccm_rw_addr[14:1] == redundant_address_1; // @[el2_ifu_iccm_mem.scala 53:105] - wire _T_104 = _T_101 & _T_10; // @[el2_ifu_iccm_mem.scala 53:145] - wire _T_105 = redundant_valid[1] & _T_104; // @[el2_ifu_iccm_mem.scala 53:71] - wire _T_108 = addr_bank_inc[14:1] == redundant_address_1; // @[el2_ifu_iccm_mem.scala 54:37] - wire _T_111 = _T_108 & _T_13; // @[el2_ifu_iccm_mem.scala 54:77] - wire _T_112 = _T_105 | _T_111; // @[el2_ifu_iccm_mem.scala 53:179] - wire _T_119 = _T_101 & _T_15; // @[el2_ifu_iccm_mem.scala 53:145] - wire _T_120 = redundant_valid[1] & _T_119; // @[el2_ifu_iccm_mem.scala 53:71] - wire _T_126 = _T_108 & _T_18; // @[el2_ifu_iccm_mem.scala 54:77] - wire _T_127 = _T_120 | _T_126; // @[el2_ifu_iccm_mem.scala 53:179] - wire _T_134 = _T_101 & _T_20; // @[el2_ifu_iccm_mem.scala 53:145] - wire _T_135 = redundant_valid[1] & _T_134; // @[el2_ifu_iccm_mem.scala 53:71] - wire _T_141 = _T_108 & _T_23; // @[el2_ifu_iccm_mem.scala 54:77] - wire _T_142 = _T_135 | _T_141; // @[el2_ifu_iccm_mem.scala 53:179] - wire _T_149 = _T_101 & _T_25; // @[el2_ifu_iccm_mem.scala 53:145] - wire _T_150 = redundant_valid[1] & _T_149; // @[el2_ifu_iccm_mem.scala 53:71] - wire _T_156 = _T_108 & _T_28; // @[el2_ifu_iccm_mem.scala 54:77] - wire _T_157 = _T_150 | _T_156; // @[el2_ifu_iccm_mem.scala 53:179] - wire [3:0] sel_red1 = {_T_157,_T_142,_T_127,_T_112}; // @[Cat.scala 29:58] + wire _T_105 = io_iccm_rw_addr[14:1] == redundant_address_1; // @[el2_ifu_iccm_mem.scala 56:105] + wire _T_108 = _T_105 & _T_10; // @[el2_ifu_iccm_mem.scala 56:145] + wire _T_109 = redundant_valid[1] & _T_108; // @[el2_ifu_iccm_mem.scala 56:71] + wire _T_112 = addr_bank_inc[14:1] == redundant_address_1; // @[el2_ifu_iccm_mem.scala 57:37] + wire _T_115 = _T_112 & _T_13; // @[el2_ifu_iccm_mem.scala 57:77] + wire _T_116 = _T_109 | _T_115; // @[el2_ifu_iccm_mem.scala 56:179] + wire _T_123 = _T_105 & _T_15; // @[el2_ifu_iccm_mem.scala 56:145] + wire _T_124 = redundant_valid[1] & _T_123; // @[el2_ifu_iccm_mem.scala 56:71] + wire _T_130 = _T_112 & _T_18; // @[el2_ifu_iccm_mem.scala 57:77] + wire _T_131 = _T_124 | _T_130; // @[el2_ifu_iccm_mem.scala 56:179] + wire _T_138 = _T_105 & _T_20; // @[el2_ifu_iccm_mem.scala 56:145] + wire _T_139 = redundant_valid[1] & _T_138; // @[el2_ifu_iccm_mem.scala 56:71] + wire _T_145 = _T_112 & _T_23; // @[el2_ifu_iccm_mem.scala 57:77] + wire _T_146 = _T_139 | _T_145; // @[el2_ifu_iccm_mem.scala 56:179] + wire _T_153 = _T_105 & _T_25; // @[el2_ifu_iccm_mem.scala 56:145] + wire _T_154 = redundant_valid[1] & _T_153; // @[el2_ifu_iccm_mem.scala 56:71] + wire _T_160 = _T_112 & _T_28; // @[el2_ifu_iccm_mem.scala 57:77] + wire _T_161 = _T_154 | _T_160; // @[el2_ifu_iccm_mem.scala 56:179] + wire [3:0] sel_red1 = {_T_161,_T_146,_T_131,_T_116}; // @[Cat.scala 29:58] reg [13:0] redundant_address_0; // @[Reg.scala 27:20] - wire _T_163 = io_iccm_rw_addr[14:1] == redundant_address_0; // @[el2_ifu_iccm_mem.scala 55:105] - wire _T_166 = _T_163 & _T_10; // @[el2_ifu_iccm_mem.scala 55:145] - wire _T_167 = redundant_valid[0] & _T_166; // @[el2_ifu_iccm_mem.scala 55:71] - wire _T_170 = addr_bank_inc[14:1] == redundant_address_0; // @[el2_ifu_iccm_mem.scala 56:37] - wire _T_173 = _T_170 & _T_13; // @[el2_ifu_iccm_mem.scala 56:77] - wire _T_174 = _T_167 | _T_173; // @[el2_ifu_iccm_mem.scala 55:179] - wire _T_181 = _T_163 & _T_15; // @[el2_ifu_iccm_mem.scala 55:145] - wire _T_182 = redundant_valid[0] & _T_181; // @[el2_ifu_iccm_mem.scala 55:71] - wire _T_188 = _T_170 & _T_18; // @[el2_ifu_iccm_mem.scala 56:77] - wire _T_189 = _T_182 | _T_188; // @[el2_ifu_iccm_mem.scala 55:179] - wire _T_196 = _T_163 & _T_20; // @[el2_ifu_iccm_mem.scala 55:145] - wire _T_197 = redundant_valid[0] & _T_196; // @[el2_ifu_iccm_mem.scala 55:71] - wire _T_203 = _T_170 & _T_23; // @[el2_ifu_iccm_mem.scala 56:77] - wire _T_204 = _T_197 | _T_203; // @[el2_ifu_iccm_mem.scala 55:179] - wire _T_211 = _T_163 & _T_25; // @[el2_ifu_iccm_mem.scala 55:145] - wire _T_212 = redundant_valid[0] & _T_211; // @[el2_ifu_iccm_mem.scala 55:71] - wire _T_218 = _T_170 & _T_28; // @[el2_ifu_iccm_mem.scala 56:77] - wire _T_219 = _T_212 | _T_218; // @[el2_ifu_iccm_mem.scala 55:179] - wire [3:0] sel_red0 = {_T_219,_T_204,_T_189,_T_174}; // @[Cat.scala 29:58] - reg [3:0] sel_red0_q; // @[el2_ifu_iccm_mem.scala 58:27] - reg [3:0] sel_red1_q; // @[el2_ifu_iccm_mem.scala 59:27] - wire _T_227 = ~sel_red0_q[0]; // @[el2_ifu_iccm_mem.scala 65:36] - wire _T_229 = ~sel_red1_q[0]; // @[el2_ifu_iccm_mem.scala 65:53] - wire _T_230 = _T_227 & _T_229; // @[el2_ifu_iccm_mem.scala 65:51] + wire _T_167 = io_iccm_rw_addr[14:1] == redundant_address_0; // @[el2_ifu_iccm_mem.scala 58:105] + wire _T_170 = _T_167 & _T_10; // @[el2_ifu_iccm_mem.scala 58:145] + wire _T_171 = redundant_valid[0] & _T_170; // @[el2_ifu_iccm_mem.scala 58:71] + wire _T_174 = addr_bank_inc[14:1] == redundant_address_0; // @[el2_ifu_iccm_mem.scala 59:37] + wire _T_177 = _T_174 & _T_13; // @[el2_ifu_iccm_mem.scala 59:77] + wire _T_178 = _T_171 | _T_177; // @[el2_ifu_iccm_mem.scala 58:179] + wire _T_185 = _T_167 & _T_15; // @[el2_ifu_iccm_mem.scala 58:145] + wire _T_186 = redundant_valid[0] & _T_185; // @[el2_ifu_iccm_mem.scala 58:71] + wire _T_192 = _T_174 & _T_18; // @[el2_ifu_iccm_mem.scala 59:77] + wire _T_193 = _T_186 | _T_192; // @[el2_ifu_iccm_mem.scala 58:179] + wire _T_200 = _T_167 & _T_20; // @[el2_ifu_iccm_mem.scala 58:145] + wire _T_201 = redundant_valid[0] & _T_200; // @[el2_ifu_iccm_mem.scala 58:71] + wire _T_207 = _T_174 & _T_23; // @[el2_ifu_iccm_mem.scala 59:77] + wire _T_208 = _T_201 | _T_207; // @[el2_ifu_iccm_mem.scala 58:179] + wire _T_215 = _T_167 & _T_25; // @[el2_ifu_iccm_mem.scala 58:145] + wire _T_216 = redundant_valid[0] & _T_215; // @[el2_ifu_iccm_mem.scala 58:71] + wire _T_222 = _T_174 & _T_28; // @[el2_ifu_iccm_mem.scala 59:77] + wire _T_223 = _T_216 | _T_222; // @[el2_ifu_iccm_mem.scala 58:179] + wire [3:0] sel_red0 = {_T_223,_T_208,_T_193,_T_178}; // @[Cat.scala 29:58] + reg [3:0] sel_red0_q; // @[el2_ifu_iccm_mem.scala 61:27] + reg [3:0] sel_red1_q; // @[el2_ifu_iccm_mem.scala 62:27] + wire _T_231 = ~sel_red0_q[0]; // @[el2_ifu_iccm_mem.scala 68:36] + wire _T_233 = ~sel_red1_q[0]; // @[el2_ifu_iccm_mem.scala 68:53] + wire _T_234 = _T_231 & _T_233; // @[el2_ifu_iccm_mem.scala 68:51] reg [38:0] redundant_data_1; // @[Reg.scala 27:20] - wire [38:0] _T_232 = sel_red1_q[0] ? redundant_data_1 : 39'h0; // @[Mux.scala 27:72] + wire [38:0] _T_236 = sel_red1_q[0] ? redundant_data_1 : 39'h0; // @[Mux.scala 27:72] reg [38:0] redundant_data_0; // @[Reg.scala 27:20] - wire [38:0] _T_233 = sel_red0_q[0] ? redundant_data_0 : 39'h0; // @[Mux.scala 27:72] - wire [38:0] iccm_bank_dout_0 = iccm_mem_0__T_97_data; // @[el2_ifu_iccm_mem.scala 45:28 el2_ifu_iccm_mem.scala 47:18] - wire [38:0] _T_234 = _T_230 ? iccm_bank_dout_0 : 39'h0; // @[Mux.scala 27:72] - wire [38:0] _T_235 = _T_232 | _T_233; // @[Mux.scala 27:72] - wire [38:0] iccm_bank_dout_fn_0 = _T_235 | _T_234; // @[Mux.scala 27:72] - wire _T_242 = ~sel_red0_q[1]; // @[el2_ifu_iccm_mem.scala 65:36] - wire _T_244 = ~sel_red1_q[1]; // @[el2_ifu_iccm_mem.scala 65:53] - wire _T_245 = _T_242 & _T_244; // @[el2_ifu_iccm_mem.scala 65:51] - wire [38:0] _T_247 = sel_red1_q[1] ? redundant_data_1 : 39'h0; // @[Mux.scala 27:72] - wire [38:0] _T_248 = sel_red0_q[1] ? redundant_data_0 : 39'h0; // @[Mux.scala 27:72] - wire [38:0] iccm_bank_dout_1 = iccm_mem_1__T_97_data; // @[el2_ifu_iccm_mem.scala 45:28 el2_ifu_iccm_mem.scala 47:18] - wire [38:0] _T_249 = _T_245 ? iccm_bank_dout_1 : 39'h0; // @[Mux.scala 27:72] - wire [38:0] _T_250 = _T_247 | _T_248; // @[Mux.scala 27:72] - wire [38:0] iccm_bank_dout_fn_1 = _T_250 | _T_249; // @[Mux.scala 27:72] - wire _T_257 = ~sel_red0_q[2]; // @[el2_ifu_iccm_mem.scala 65:36] - wire _T_259 = ~sel_red1_q[2]; // @[el2_ifu_iccm_mem.scala 65:53] - wire _T_260 = _T_257 & _T_259; // @[el2_ifu_iccm_mem.scala 65:51] - wire [38:0] _T_262 = sel_red1_q[2] ? redundant_data_1 : 39'h0; // @[Mux.scala 27:72] - wire [38:0] _T_263 = sel_red0_q[2] ? redundant_data_0 : 39'h0; // @[Mux.scala 27:72] - wire [38:0] iccm_bank_dout_2 = iccm_mem_2__T_97_data; // @[el2_ifu_iccm_mem.scala 45:28 el2_ifu_iccm_mem.scala 47:18] - wire [38:0] _T_264 = _T_260 ? iccm_bank_dout_2 : 39'h0; // @[Mux.scala 27:72] - wire [38:0] _T_265 = _T_262 | _T_263; // @[Mux.scala 27:72] - wire [38:0] iccm_bank_dout_fn_2 = _T_265 | _T_264; // @[Mux.scala 27:72] - wire _T_272 = ~sel_red0_q[3]; // @[el2_ifu_iccm_mem.scala 65:36] - wire _T_274 = ~sel_red1_q[3]; // @[el2_ifu_iccm_mem.scala 65:53] - wire _T_275 = _T_272 & _T_274; // @[el2_ifu_iccm_mem.scala 65:51] - wire [38:0] _T_277 = sel_red1_q[3] ? redundant_data_1 : 39'h0; // @[Mux.scala 27:72] - wire [38:0] _T_278 = sel_red0_q[3] ? redundant_data_0 : 39'h0; // @[Mux.scala 27:72] - wire [38:0] iccm_bank_dout_3 = iccm_mem_3__T_97_data; // @[el2_ifu_iccm_mem.scala 45:28 el2_ifu_iccm_mem.scala 47:18] - wire [38:0] _T_279 = _T_275 ? iccm_bank_dout_3 : 39'h0; // @[Mux.scala 27:72] - wire [38:0] _T_280 = _T_277 | _T_278; // @[Mux.scala 27:72] - wire [38:0] iccm_bank_dout_fn_3 = _T_280 | _T_279; // @[Mux.scala 27:72] + wire [38:0] _T_237 = sel_red0_q[0] ? redundant_data_0 : 39'h0; // @[Mux.scala 27:72] + wire [38:0] _T_238 = _T_234 ? iccm_bank_dout_0 : 39'h0; // @[Mux.scala 27:72] + wire [38:0] _T_239 = _T_236 | _T_237; // @[Mux.scala 27:72] + wire [38:0] iccm_bank_dout_fn_0 = _T_239 | _T_238; // @[Mux.scala 27:72] + wire _T_246 = ~sel_red0_q[1]; // @[el2_ifu_iccm_mem.scala 68:36] + wire _T_248 = ~sel_red1_q[1]; // @[el2_ifu_iccm_mem.scala 68:53] + wire _T_249 = _T_246 & _T_248; // @[el2_ifu_iccm_mem.scala 68:51] + wire [38:0] _T_251 = sel_red1_q[1] ? redundant_data_1 : 39'h0; // @[Mux.scala 27:72] + wire [38:0] _T_252 = sel_red0_q[1] ? redundant_data_0 : 39'h0; // @[Mux.scala 27:72] + wire [38:0] _T_253 = _T_249 ? iccm_bank_dout_1 : 39'h0; // @[Mux.scala 27:72] + wire [38:0] _T_254 = _T_251 | _T_252; // @[Mux.scala 27:72] + wire [38:0] iccm_bank_dout_fn_1 = _T_254 | _T_253; // @[Mux.scala 27:72] + wire _T_261 = ~sel_red0_q[2]; // @[el2_ifu_iccm_mem.scala 68:36] + wire _T_263 = ~sel_red1_q[2]; // @[el2_ifu_iccm_mem.scala 68:53] + wire _T_264 = _T_261 & _T_263; // @[el2_ifu_iccm_mem.scala 68:51] + wire [38:0] _T_266 = sel_red1_q[2] ? redundant_data_1 : 39'h0; // @[Mux.scala 27:72] + wire [38:0] _T_267 = sel_red0_q[2] ? redundant_data_0 : 39'h0; // @[Mux.scala 27:72] + wire [38:0] _T_268 = _T_264 ? iccm_bank_dout_2 : 39'h0; // @[Mux.scala 27:72] + wire [38:0] _T_269 = _T_266 | _T_267; // @[Mux.scala 27:72] + wire [38:0] iccm_bank_dout_fn_2 = _T_269 | _T_268; // @[Mux.scala 27:72] + wire _T_276 = ~sel_red0_q[3]; // @[el2_ifu_iccm_mem.scala 68:36] + wire _T_278 = ~sel_red1_q[3]; // @[el2_ifu_iccm_mem.scala 68:53] + wire _T_279 = _T_276 & _T_278; // @[el2_ifu_iccm_mem.scala 68:51] + wire [38:0] _T_281 = sel_red1_q[3] ? redundant_data_1 : 39'h0; // @[Mux.scala 27:72] + wire [38:0] _T_282 = sel_red0_q[3] ? redundant_data_0 : 39'h0; // @[Mux.scala 27:72] + wire [38:0] _T_283 = _T_279 ? iccm_bank_dout_3 : 39'h0; // @[Mux.scala 27:72] + wire [38:0] _T_284 = _T_281 | _T_282; // @[Mux.scala 27:72] + wire [38:0] iccm_bank_dout_fn_3 = _T_284 | _T_283; // @[Mux.scala 27:72] reg redundant_lru; // @[Reg.scala 27:20] - wire _T_282 = ~redundant_lru; // @[el2_ifu_iccm_mem.scala 67:20] - wire r0_addr_en = _T_282 & io_iccm_buf_correct_ecc; // @[el2_ifu_iccm_mem.scala 67:35] - wire r1_addr_en = redundant_lru & io_iccm_buf_correct_ecc; // @[el2_ifu_iccm_mem.scala 68:35] - wire _T_283 = |sel_red0; // @[el2_ifu_iccm_mem.scala 69:63] - wire _T_284 = |sel_red1; // @[el2_ifu_iccm_mem.scala 69:78] - wire _T_285 = _T_283 | _T_284; // @[el2_ifu_iccm_mem.scala 69:67] - wire _T_286 = _T_285 & io_iccm_rden; // @[el2_ifu_iccm_mem.scala 69:83] - wire _T_287 = _T_286 & io_iccm_correction_state; // @[el2_ifu_iccm_mem.scala 69:98] - wire redundant_lru_en = io_iccm_buf_correct_ecc | _T_287; // @[el2_ifu_iccm_mem.scala 69:50] - wire _GEN_11 = r1_addr_en | _T_298; // @[Reg.scala 28:19] - wire _GEN_12 = r0_addr_en | _T_299; // @[Reg.scala 28:19] - wire _T_303 = io_iccm_rw_addr[14:2] == redundant_address_0[13:1]; // @[el2_ifu_iccm_mem.scala 76:61] - wire _T_306 = io_iccm_rw_addr[1] & redundant_address_0[0]; // @[el2_ifu_iccm_mem.scala 77:26] - wire _T_309 = _T_306 | _T_1; // @[el2_ifu_iccm_mem.scala 77:52] - wire _T_310 = _T_303 & _T_309; // @[el2_ifu_iccm_mem.scala 76:102] - wire _T_312 = _T_310 & redundant_valid[0]; // @[el2_ifu_iccm_mem.scala 77:84] - wire _T_313 = _T_312 & io_iccm_wren; // @[el2_ifu_iccm_mem.scala 77:105] - wire redundant_data0_en = _T_313 | r0_addr_en; // @[el2_ifu_iccm_mem.scala 77:121] - wire _T_322 = redundant_address_0[0] & _T_1; // @[el2_ifu_iccm_mem.scala 79:104] - wire _T_323 = _T_306 | _T_322; // @[el2_ifu_iccm_mem.scala 79:78] - wire _T_331 = io_iccm_rw_addr[14:2] == redundant_address_1[13:1]; // @[el2_ifu_iccm_mem.scala 83:61] - wire _T_334 = io_iccm_rw_addr[1] & redundant_address_1[0]; // @[el2_ifu_iccm_mem.scala 84:26] - wire _T_337 = _T_334 | _T_1; // @[el2_ifu_iccm_mem.scala 84:52] - wire _T_338 = _T_331 & _T_337; // @[el2_ifu_iccm_mem.scala 83:102] - wire _T_340 = _T_338 & redundant_valid[1]; // @[el2_ifu_iccm_mem.scala 84:84] - wire _T_341 = _T_340 & io_iccm_wren; // @[el2_ifu_iccm_mem.scala 84:105] - wire redundant_data1_en = _T_341 | r0_addr_en; // @[el2_ifu_iccm_mem.scala 84:121] - wire _T_350 = redundant_address_1[0] & _T_1; // @[el2_ifu_iccm_mem.scala 86:104] - wire _T_351 = _T_334 | _T_350; // @[el2_ifu_iccm_mem.scala 86:78] - reg [2:0] iccm_rd_addr_lo_q; // @[el2_ifu_iccm_mem.scala 90:34] - reg [1:0] iccm_rd_addr_hi_q; // @[el2_ifu_iccm_mem.scala 91:34] - wire _T_359 = iccm_rd_addr_hi_q == 2'h0; // @[el2_ifu_iccm_mem.scala 93:86] - wire _T_361 = iccm_rd_addr_hi_q == 2'h1; // @[el2_ifu_iccm_mem.scala 93:86] - wire _T_363 = iccm_rd_addr_hi_q == 2'h2; // @[el2_ifu_iccm_mem.scala 93:86] - wire _T_365 = iccm_rd_addr_hi_q == 2'h3; // @[el2_ifu_iccm_mem.scala 93:86] - wire [31:0] _T_367 = _T_359 ? iccm_bank_dout_fn_0[31:0] : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_368 = _T_361 ? iccm_bank_dout_fn_1[31:0] : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_369 = _T_363 ? iccm_bank_dout_fn_2[31:0] : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_370 = _T_365 ? iccm_bank_dout_fn_3[31:0] : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_371 = _T_367 | _T_368; // @[Mux.scala 27:72] - wire [31:0] _T_372 = _T_371 | _T_369; // @[Mux.scala 27:72] - wire [31:0] _T_373 = _T_372 | _T_370; // @[Mux.scala 27:72] - wire _T_376 = iccm_rd_addr_lo_q[1:0] == 2'h0; // @[el2_ifu_iccm_mem.scala 94:77] - wire _T_379 = iccm_rd_addr_lo_q[1:0] == 2'h1; // @[el2_ifu_iccm_mem.scala 94:77] - wire _T_382 = iccm_rd_addr_lo_q[1:0] == 2'h2; // @[el2_ifu_iccm_mem.scala 94:77] - wire _T_385 = iccm_rd_addr_lo_q[1:0] == 2'h3; // @[el2_ifu_iccm_mem.scala 94:77] - wire [31:0] _T_387 = _T_376 ? iccm_bank_dout_fn_0[31:0] : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_388 = _T_379 ? iccm_bank_dout_fn_1[31:0] : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_389 = _T_382 ? iccm_bank_dout_fn_2[31:0] : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_390 = _T_385 ? iccm_bank_dout_fn_3[31:0] : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_391 = _T_387 | _T_388; // @[Mux.scala 27:72] - wire [31:0] _T_392 = _T_391 | _T_389; // @[Mux.scala 27:72] - wire [31:0] _T_393 = _T_392 | _T_390; // @[Mux.scala 27:72] - wire [63:0] iccm_rd_data_pre = {_T_373,_T_393}; // @[Cat.scala 29:58] - wire [63:0] _T_399 = {16'h0,iccm_rd_data_pre[63:16]}; // @[Cat.scala 29:58] - wire [38:0] _T_405 = _T_359 ? iccm_bank_dout_fn_0 : 39'h0; // @[Mux.scala 27:72] - wire [38:0] _T_406 = _T_361 ? iccm_bank_dout_fn_1 : 39'h0; // @[Mux.scala 27:72] - wire [38:0] _T_407 = _T_363 ? iccm_bank_dout_fn_2 : 39'h0; // @[Mux.scala 27:72] - wire [38:0] _T_408 = _T_365 ? iccm_bank_dout_fn_3 : 39'h0; // @[Mux.scala 27:72] - wire [38:0] _T_409 = _T_405 | _T_406; // @[Mux.scala 27:72] - wire [38:0] _T_410 = _T_409 | _T_407; // @[Mux.scala 27:72] - wire [38:0] _T_411 = _T_410 | _T_408; // @[Mux.scala 27:72] - wire [38:0] _T_421 = _T_376 ? iccm_bank_dout_fn_0 : 39'h0; // @[Mux.scala 27:72] - wire [38:0] _T_422 = _T_379 ? iccm_bank_dout_fn_1 : 39'h0; // @[Mux.scala 27:72] - wire [38:0] _T_423 = _T_382 ? iccm_bank_dout_fn_2 : 39'h0; // @[Mux.scala 27:72] - wire [38:0] _T_424 = _T_385 ? iccm_bank_dout_fn_3 : 39'h0; // @[Mux.scala 27:72] - wire [38:0] _T_425 = _T_421 | _T_422; // @[Mux.scala 27:72] - wire [38:0] _T_426 = _T_425 | _T_423; // @[Mux.scala 27:72] - wire [38:0] _T_427 = _T_426 | _T_424; // @[Mux.scala 27:72] + wire _T_286 = ~redundant_lru; // @[el2_ifu_iccm_mem.scala 70:20] + wire r0_addr_en = _T_286 & io_iccm_buf_correct_ecc; // @[el2_ifu_iccm_mem.scala 70:35] + wire r1_addr_en = redundant_lru & io_iccm_buf_correct_ecc; // @[el2_ifu_iccm_mem.scala 71:35] + wire _T_287 = |sel_red0; // @[el2_ifu_iccm_mem.scala 72:63] + wire _T_288 = |sel_red1; // @[el2_ifu_iccm_mem.scala 72:78] + wire _T_289 = _T_287 | _T_288; // @[el2_ifu_iccm_mem.scala 72:67] + wire _T_290 = _T_289 & io_iccm_rden; // @[el2_ifu_iccm_mem.scala 72:83] + wire _T_291 = _T_290 & io_iccm_correction_state; // @[el2_ifu_iccm_mem.scala 72:98] + wire redundant_lru_en = io_iccm_buf_correct_ecc | _T_291; // @[el2_ifu_iccm_mem.scala 72:50] + wire _GEN_11 = r1_addr_en | _T_302; // @[Reg.scala 28:19] + wire _GEN_12 = r0_addr_en | _T_303; // @[Reg.scala 28:19] + wire _T_307 = io_iccm_rw_addr[14:2] == redundant_address_0[13:1]; // @[el2_ifu_iccm_mem.scala 79:61] + wire _T_310 = io_iccm_rw_addr[1] & redundant_address_0[0]; // @[el2_ifu_iccm_mem.scala 80:26] + wire _T_313 = _T_310 | _T_1; // @[el2_ifu_iccm_mem.scala 80:52] + wire _T_314 = _T_307 & _T_313; // @[el2_ifu_iccm_mem.scala 79:102] + wire _T_316 = _T_314 & redundant_valid[0]; // @[el2_ifu_iccm_mem.scala 80:84] + wire _T_317 = _T_316 & io_iccm_wren; // @[el2_ifu_iccm_mem.scala 80:105] + wire redundant_data0_en = _T_317 | r0_addr_en; // @[el2_ifu_iccm_mem.scala 80:121] + wire _T_326 = redundant_address_0[0] & _T_1; // @[el2_ifu_iccm_mem.scala 82:104] + wire _T_327 = _T_310 | _T_326; // @[el2_ifu_iccm_mem.scala 82:78] + wire _T_335 = io_iccm_rw_addr[14:2] == redundant_address_1[13:1]; // @[el2_ifu_iccm_mem.scala 86:61] + wire _T_338 = io_iccm_rw_addr[1] & redundant_address_1[0]; // @[el2_ifu_iccm_mem.scala 87:26] + wire _T_341 = _T_338 | _T_1; // @[el2_ifu_iccm_mem.scala 87:52] + wire _T_342 = _T_335 & _T_341; // @[el2_ifu_iccm_mem.scala 86:102] + wire _T_344 = _T_342 & redundant_valid[1]; // @[el2_ifu_iccm_mem.scala 87:84] + wire _T_345 = _T_344 & io_iccm_wren; // @[el2_ifu_iccm_mem.scala 87:105] + wire redundant_data1_en = _T_345 | r0_addr_en; // @[el2_ifu_iccm_mem.scala 87:121] + wire _T_354 = redundant_address_1[0] & _T_1; // @[el2_ifu_iccm_mem.scala 89:104] + wire _T_355 = _T_338 | _T_354; // @[el2_ifu_iccm_mem.scala 89:78] + reg [2:0] iccm_rd_addr_lo_q; // @[el2_ifu_iccm_mem.scala 93:34] + reg [1:0] iccm_rd_addr_hi_q; // @[el2_ifu_iccm_mem.scala 94:34] + wire _T_363 = iccm_rd_addr_hi_q == 2'h0; // @[el2_ifu_iccm_mem.scala 96:86] + wire _T_365 = iccm_rd_addr_hi_q == 2'h1; // @[el2_ifu_iccm_mem.scala 96:86] + wire _T_367 = iccm_rd_addr_hi_q == 2'h2; // @[el2_ifu_iccm_mem.scala 96:86] + wire _T_369 = iccm_rd_addr_hi_q == 2'h3; // @[el2_ifu_iccm_mem.scala 96:86] + wire [31:0] _T_371 = _T_363 ? iccm_bank_dout_fn_0[31:0] : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_372 = _T_365 ? iccm_bank_dout_fn_1[31:0] : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_373 = _T_367 ? iccm_bank_dout_fn_2[31:0] : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_374 = _T_369 ? iccm_bank_dout_fn_3[31:0] : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_375 = _T_371 | _T_372; // @[Mux.scala 27:72] + wire [31:0] _T_376 = _T_375 | _T_373; // @[Mux.scala 27:72] + wire [31:0] _T_377 = _T_376 | _T_374; // @[Mux.scala 27:72] + wire _T_380 = iccm_rd_addr_lo_q[1:0] == 2'h0; // @[el2_ifu_iccm_mem.scala 97:77] + wire _T_383 = iccm_rd_addr_lo_q[1:0] == 2'h1; // @[el2_ifu_iccm_mem.scala 97:77] + wire _T_386 = iccm_rd_addr_lo_q[1:0] == 2'h2; // @[el2_ifu_iccm_mem.scala 97:77] + wire _T_389 = iccm_rd_addr_lo_q[1:0] == 2'h3; // @[el2_ifu_iccm_mem.scala 97:77] + wire [31:0] _T_391 = _T_380 ? iccm_bank_dout_fn_0[31:0] : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_392 = _T_383 ? iccm_bank_dout_fn_1[31:0] : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_393 = _T_386 ? iccm_bank_dout_fn_2[31:0] : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_394 = _T_389 ? iccm_bank_dout_fn_3[31:0] : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_395 = _T_391 | _T_392; // @[Mux.scala 27:72] + wire [31:0] _T_396 = _T_395 | _T_393; // @[Mux.scala 27:72] + wire [31:0] _T_397 = _T_396 | _T_394; // @[Mux.scala 27:72] + wire [63:0] iccm_rd_data_pre = {_T_377,_T_397}; // @[Cat.scala 29:58] + wire [63:0] _T_403 = {16'h0,iccm_rd_data_pre[63:16]}; // @[Cat.scala 29:58] + wire [38:0] _T_409 = _T_363 ? iccm_bank_dout_fn_0 : 39'h0; // @[Mux.scala 27:72] + wire [38:0] _T_410 = _T_365 ? iccm_bank_dout_fn_1 : 39'h0; // @[Mux.scala 27:72] + wire [38:0] _T_411 = _T_367 ? iccm_bank_dout_fn_2 : 39'h0; // @[Mux.scala 27:72] + wire [38:0] _T_412 = _T_369 ? iccm_bank_dout_fn_3 : 39'h0; // @[Mux.scala 27:72] + wire [38:0] _T_413 = _T_409 | _T_410; // @[Mux.scala 27:72] + wire [38:0] _T_414 = _T_413 | _T_411; // @[Mux.scala 27:72] + wire [38:0] _T_415 = _T_414 | _T_412; // @[Mux.scala 27:72] + wire [38:0] _T_425 = _T_380 ? iccm_bank_dout_fn_0 : 39'h0; // @[Mux.scala 27:72] + wire [38:0] _T_426 = _T_383 ? iccm_bank_dout_fn_1 : 39'h0; // @[Mux.scala 27:72] + wire [38:0] _T_427 = _T_386 ? iccm_bank_dout_fn_2 : 39'h0; // @[Mux.scala 27:72] + wire [38:0] _T_428 = _T_389 ? iccm_bank_dout_fn_3 : 39'h0; // @[Mux.scala 27:72] + wire [38:0] _T_429 = _T_425 | _T_426; // @[Mux.scala 27:72] + wire [38:0] _T_430 = _T_429 | _T_427; // @[Mux.scala 27:72] + wire [38:0] _T_431 = _T_430 | _T_428; // @[Mux.scala 27:72] assign iccm_mem_0__T_97_addr = wren_bank_0 ? io_iccm_rw_addr[14:3] : _T_59; - assign iccm_mem_0__T_97_data = iccm_mem_0[iccm_mem_0__T_97_addr]; // @[el2_ifu_iccm_mem.scala 40:21] + assign iccm_mem_0__T_97_data = iccm_mem_0[iccm_mem_0__T_97_addr]; // @[el2_ifu_iccm_mem.scala 41:21] assign iccm_mem_0__T_93_data = io_iccm_wr_data[38:0]; assign iccm_mem_0__T_93_addr = wren_bank_0 ? io_iccm_rw_addr[14:3] : _T_59; assign iccm_mem_0__T_93_mask = iccm_clken_0 & wren_bank_0; @@ -322,7 +330,7 @@ module el2_ifu_iccm_mem( assign iccm_mem_0__T_96_mask = iccm_clken_0 & wren_bank_0; assign iccm_mem_0__T_96_en = 1'h1; assign iccm_mem_1__T_97_addr = wren_bank_0 ? io_iccm_rw_addr[14:3] : _T_59; - assign iccm_mem_1__T_97_data = iccm_mem_1[iccm_mem_1__T_97_addr]; // @[el2_ifu_iccm_mem.scala 40:21] + assign iccm_mem_1__T_97_data = iccm_mem_1[iccm_mem_1__T_97_addr]; // @[el2_ifu_iccm_mem.scala 41:21] assign iccm_mem_1__T_93_data = io_iccm_wr_data[77:39]; assign iccm_mem_1__T_93_addr = wren_bank_0 ? io_iccm_rw_addr[14:3] : _T_59; assign iccm_mem_1__T_93_mask = iccm_clken_1 & wren_bank_1; @@ -340,7 +348,7 @@ module el2_ifu_iccm_mem( assign iccm_mem_1__T_96_mask = iccm_clken_1 & wren_bank_1; assign iccm_mem_1__T_96_en = 1'h1; assign iccm_mem_2__T_97_addr = wren_bank_0 ? io_iccm_rw_addr[14:3] : _T_59; - assign iccm_mem_2__T_97_data = iccm_mem_2[iccm_mem_2__T_97_addr]; // @[el2_ifu_iccm_mem.scala 40:21] + assign iccm_mem_2__T_97_data = iccm_mem_2[iccm_mem_2__T_97_addr]; // @[el2_ifu_iccm_mem.scala 41:21] assign iccm_mem_2__T_93_data = io_iccm_wr_data[38:0]; assign iccm_mem_2__T_93_addr = wren_bank_0 ? io_iccm_rw_addr[14:3] : _T_59; assign iccm_mem_2__T_93_mask = iccm_clken_2 & wren_bank_2; @@ -358,7 +366,7 @@ module el2_ifu_iccm_mem( assign iccm_mem_2__T_96_mask = iccm_clken_2 & wren_bank_2; assign iccm_mem_2__T_96_en = 1'h1; assign iccm_mem_3__T_97_addr = wren_bank_0 ? io_iccm_rw_addr[14:3] : _T_59; - assign iccm_mem_3__T_97_data = iccm_mem_3[iccm_mem_3__T_97_addr]; // @[el2_ifu_iccm_mem.scala 40:21] + assign iccm_mem_3__T_97_data = iccm_mem_3[iccm_mem_3__T_97_addr]; // @[el2_ifu_iccm_mem.scala 41:21] assign iccm_mem_3__T_93_data = io_iccm_wr_data[77:39]; assign iccm_mem_3__T_93_addr = wren_bank_0 ? io_iccm_rw_addr[14:3] : _T_59; assign iccm_mem_3__T_93_mask = iccm_clken_3 & wren_bank_3; @@ -375,8 +383,12 @@ module el2_ifu_iccm_mem( assign iccm_mem_3__T_96_addr = wren_bank_3 ? io_iccm_rw_addr[14:3] : _T_80; assign iccm_mem_3__T_96_mask = iccm_clken_3 & wren_bank_3; assign iccm_mem_3__T_96_en = 1'h1; - assign io_iccm_rd_data = iccm_rd_addr_lo_q[0] ? _T_399 : iccm_rd_data_pre; // @[el2_ifu_iccm_mem.scala 22:19 el2_ifu_iccm_mem.scala 95:19] - assign io_iccm_rd_data_ecc = {_T_411,_T_427}; // @[el2_ifu_iccm_mem.scala 23:23 el2_ifu_iccm_mem.scala 96:23] + assign io_iccm_rd_data = iccm_rd_addr_lo_q[0] ? _T_403 : iccm_rd_data_pre; // @[el2_ifu_iccm_mem.scala 22:19 el2_ifu_iccm_mem.scala 98:19] + assign io_iccm_rd_data_ecc = {_T_415,_T_431}; // @[el2_ifu_iccm_mem.scala 23:23 el2_ifu_iccm_mem.scala 99:23] + assign io_iccm_bank_wr_data_0 = io_iccm_wr_data[38:0]; // @[el2_ifu_iccm_mem.scala 35:24] + assign io_iccm_bank_wr_data_1 = io_iccm_wr_data[77:39]; // @[el2_ifu_iccm_mem.scala 35:24] + assign io_iccm_bank_wr_data_2 = io_iccm_wr_data[38:0]; // @[el2_ifu_iccm_mem.scala 35:24] + assign io_iccm_bank_wr_data_3 = io_iccm_wr_data[77:39]; // @[el2_ifu_iccm_mem.scala 35:24] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif @@ -426,28 +438,36 @@ initial begin iccm_mem_3[initvar] = _RAND_3[38:0]; `endif // RANDOMIZE_MEM_INIT `ifdef RANDOMIZE_REG_INIT - _RAND_4 = {1{`RANDOM}}; - _T_298 = _RAND_4[0:0]; - _RAND_5 = {1{`RANDOM}}; - _T_299 = _RAND_5[0:0]; - _RAND_6 = {1{`RANDOM}}; - redundant_address_1 = _RAND_6[13:0]; - _RAND_7 = {1{`RANDOM}}; - redundant_address_0 = _RAND_7[13:0]; + _RAND_4 = {2{`RANDOM}}; + iccm_bank_dout_0 = _RAND_4[38:0]; + _RAND_5 = {2{`RANDOM}}; + iccm_bank_dout_1 = _RAND_5[38:0]; + _RAND_6 = {2{`RANDOM}}; + iccm_bank_dout_2 = _RAND_6[38:0]; + _RAND_7 = {2{`RANDOM}}; + iccm_bank_dout_3 = _RAND_7[38:0]; _RAND_8 = {1{`RANDOM}}; - sel_red0_q = _RAND_8[3:0]; + _T_302 = _RAND_8[0:0]; _RAND_9 = {1{`RANDOM}}; - sel_red1_q = _RAND_9[3:0]; - _RAND_10 = {2{`RANDOM}}; - redundant_data_1 = _RAND_10[38:0]; - _RAND_11 = {2{`RANDOM}}; - redundant_data_0 = _RAND_11[38:0]; + _T_303 = _RAND_9[0:0]; + _RAND_10 = {1{`RANDOM}}; + redundant_address_1 = _RAND_10[13:0]; + _RAND_11 = {1{`RANDOM}}; + redundant_address_0 = _RAND_11[13:0]; _RAND_12 = {1{`RANDOM}}; - redundant_lru = _RAND_12[0:0]; + sel_red0_q = _RAND_12[3:0]; _RAND_13 = {1{`RANDOM}}; - iccm_rd_addr_lo_q = _RAND_13[2:0]; - _RAND_14 = {1{`RANDOM}}; - iccm_rd_addr_hi_q = _RAND_14[1:0]; + sel_red1_q = _RAND_13[3:0]; + _RAND_14 = {2{`RANDOM}}; + redundant_data_1 = _RAND_14[38:0]; + _RAND_15 = {2{`RANDOM}}; + redundant_data_0 = _RAND_15[38:0]; + _RAND_16 = {1{`RANDOM}}; + redundant_lru = _RAND_16[0:0]; + _RAND_17 = {1{`RANDOM}}; + iccm_rd_addr_lo_q = _RAND_17[2:0]; + _RAND_18 = {1{`RANDOM}}; + iccm_rd_addr_hi_q = _RAND_18[1:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end // initial @@ -457,62 +477,66 @@ end // initial `endif // SYNTHESIS always @(posedge clock) begin if(iccm_mem_0__T_93_en & iccm_mem_0__T_93_mask) begin - iccm_mem_0[iccm_mem_0__T_93_addr] <= iccm_mem_0__T_93_data; // @[el2_ifu_iccm_mem.scala 40:21] + iccm_mem_0[iccm_mem_0__T_93_addr] <= iccm_mem_0__T_93_data; // @[el2_ifu_iccm_mem.scala 41:21] end if(iccm_mem_0__T_94_en & iccm_mem_0__T_94_mask) begin - iccm_mem_0[iccm_mem_0__T_94_addr] <= iccm_mem_0__T_94_data; // @[el2_ifu_iccm_mem.scala 40:21] + iccm_mem_0[iccm_mem_0__T_94_addr] <= iccm_mem_0__T_94_data; // @[el2_ifu_iccm_mem.scala 41:21] end if(iccm_mem_0__T_95_en & iccm_mem_0__T_95_mask) begin - iccm_mem_0[iccm_mem_0__T_95_addr] <= iccm_mem_0__T_95_data; // @[el2_ifu_iccm_mem.scala 40:21] + iccm_mem_0[iccm_mem_0__T_95_addr] <= iccm_mem_0__T_95_data; // @[el2_ifu_iccm_mem.scala 41:21] end if(iccm_mem_0__T_96_en & iccm_mem_0__T_96_mask) begin - iccm_mem_0[iccm_mem_0__T_96_addr] <= iccm_mem_0__T_96_data; // @[el2_ifu_iccm_mem.scala 40:21] + iccm_mem_0[iccm_mem_0__T_96_addr] <= iccm_mem_0__T_96_data; // @[el2_ifu_iccm_mem.scala 41:21] end if(iccm_mem_1__T_93_en & iccm_mem_1__T_93_mask) begin - iccm_mem_1[iccm_mem_1__T_93_addr] <= iccm_mem_1__T_93_data; // @[el2_ifu_iccm_mem.scala 40:21] + iccm_mem_1[iccm_mem_1__T_93_addr] <= iccm_mem_1__T_93_data; // @[el2_ifu_iccm_mem.scala 41:21] end if(iccm_mem_1__T_94_en & iccm_mem_1__T_94_mask) begin - iccm_mem_1[iccm_mem_1__T_94_addr] <= iccm_mem_1__T_94_data; // @[el2_ifu_iccm_mem.scala 40:21] + iccm_mem_1[iccm_mem_1__T_94_addr] <= iccm_mem_1__T_94_data; // @[el2_ifu_iccm_mem.scala 41:21] end if(iccm_mem_1__T_95_en & iccm_mem_1__T_95_mask) begin - iccm_mem_1[iccm_mem_1__T_95_addr] <= iccm_mem_1__T_95_data; // @[el2_ifu_iccm_mem.scala 40:21] + iccm_mem_1[iccm_mem_1__T_95_addr] <= iccm_mem_1__T_95_data; // @[el2_ifu_iccm_mem.scala 41:21] end if(iccm_mem_1__T_96_en & iccm_mem_1__T_96_mask) begin - iccm_mem_1[iccm_mem_1__T_96_addr] <= iccm_mem_1__T_96_data; // @[el2_ifu_iccm_mem.scala 40:21] + iccm_mem_1[iccm_mem_1__T_96_addr] <= iccm_mem_1__T_96_data; // @[el2_ifu_iccm_mem.scala 41:21] end if(iccm_mem_2__T_93_en & iccm_mem_2__T_93_mask) begin - iccm_mem_2[iccm_mem_2__T_93_addr] <= iccm_mem_2__T_93_data; // @[el2_ifu_iccm_mem.scala 40:21] + iccm_mem_2[iccm_mem_2__T_93_addr] <= iccm_mem_2__T_93_data; // @[el2_ifu_iccm_mem.scala 41:21] end if(iccm_mem_2__T_94_en & iccm_mem_2__T_94_mask) begin - iccm_mem_2[iccm_mem_2__T_94_addr] <= iccm_mem_2__T_94_data; // @[el2_ifu_iccm_mem.scala 40:21] + iccm_mem_2[iccm_mem_2__T_94_addr] <= iccm_mem_2__T_94_data; // @[el2_ifu_iccm_mem.scala 41:21] end if(iccm_mem_2__T_95_en & iccm_mem_2__T_95_mask) begin - iccm_mem_2[iccm_mem_2__T_95_addr] <= iccm_mem_2__T_95_data; // @[el2_ifu_iccm_mem.scala 40:21] + iccm_mem_2[iccm_mem_2__T_95_addr] <= iccm_mem_2__T_95_data; // @[el2_ifu_iccm_mem.scala 41:21] end if(iccm_mem_2__T_96_en & iccm_mem_2__T_96_mask) begin - iccm_mem_2[iccm_mem_2__T_96_addr] <= iccm_mem_2__T_96_data; // @[el2_ifu_iccm_mem.scala 40:21] + iccm_mem_2[iccm_mem_2__T_96_addr] <= iccm_mem_2__T_96_data; // @[el2_ifu_iccm_mem.scala 41:21] end if(iccm_mem_3__T_93_en & iccm_mem_3__T_93_mask) begin - iccm_mem_3[iccm_mem_3__T_93_addr] <= iccm_mem_3__T_93_data; // @[el2_ifu_iccm_mem.scala 40:21] + iccm_mem_3[iccm_mem_3__T_93_addr] <= iccm_mem_3__T_93_data; // @[el2_ifu_iccm_mem.scala 41:21] end if(iccm_mem_3__T_94_en & iccm_mem_3__T_94_mask) begin - iccm_mem_3[iccm_mem_3__T_94_addr] <= iccm_mem_3__T_94_data; // @[el2_ifu_iccm_mem.scala 40:21] + iccm_mem_3[iccm_mem_3__T_94_addr] <= iccm_mem_3__T_94_data; // @[el2_ifu_iccm_mem.scala 41:21] end if(iccm_mem_3__T_95_en & iccm_mem_3__T_95_mask) begin - iccm_mem_3[iccm_mem_3__T_95_addr] <= iccm_mem_3__T_95_data; // @[el2_ifu_iccm_mem.scala 40:21] + iccm_mem_3[iccm_mem_3__T_95_addr] <= iccm_mem_3__T_95_data; // @[el2_ifu_iccm_mem.scala 41:21] end if(iccm_mem_3__T_96_en & iccm_mem_3__T_96_mask) begin - iccm_mem_3[iccm_mem_3__T_96_addr] <= iccm_mem_3__T_96_data; // @[el2_ifu_iccm_mem.scala 40:21] + iccm_mem_3[iccm_mem_3__T_96_addr] <= iccm_mem_3__T_96_data; // @[el2_ifu_iccm_mem.scala 41:21] + end + iccm_bank_dout_0 <= iccm_mem_0__T_97_data; + iccm_bank_dout_1 <= iccm_mem_1__T_97_data; + iccm_bank_dout_2 <= iccm_mem_2__T_97_data; + iccm_bank_dout_3 <= iccm_mem_3__T_97_data; + if (reset) begin + _T_302 <= 1'h0; + end else begin + _T_302 <= _GEN_11; end if (reset) begin - _T_298 <= 1'h0; + _T_303 <= 1'h0; end else begin - _T_298 <= _GEN_11; - end - if (reset) begin - _T_299 <= 1'h0; - end else begin - _T_299 <= _GEN_12; + _T_303 <= _GEN_12; end if (reset) begin redundant_address_1 <= 14'h0; @@ -537,7 +561,7 @@ end // initial if (reset) begin redundant_data_1 <= 39'h0; end else if (redundant_data1_en) begin - if (_T_351) begin + if (_T_355) begin redundant_data_1 <= iccm_bank_wr_data_1; end else begin redundant_data_1 <= iccm_bank_wr_data_0; @@ -546,7 +570,7 @@ end // initial if (reset) begin redundant_data_0 <= 39'h0; end else if (redundant_data0_en) begin - if (_T_323) begin + if (_T_327) begin redundant_data_0 <= iccm_bank_wr_data_1; end else begin redundant_data_0 <= iccm_bank_wr_data_0; @@ -556,9 +580,9 @@ end // initial redundant_lru <= 1'h0; end else if (redundant_lru_en) begin if (io_iccm_buf_correct_ecc) begin - redundant_lru <= _T_282; + redundant_lru <= _T_286; end else begin - redundant_lru <= _T_283; + redundant_lru <= _T_287; end end if (reset) begin diff --git a/src/main/scala/ifu/el2_ifu_iccm_mem.scala b/src/main/scala/ifu/el2_ifu_iccm_mem.scala index 194deb42..fa3b62d5 100644 --- a/src/main/scala/ifu/el2_ifu_iccm_mem.scala +++ b/src/main/scala/ifu/el2_ifu_iccm_mem.scala @@ -17,7 +17,7 @@ class el2_ifu_iccm_mem extends Module with el2_lib { val iccm_rd_data = Output(UInt(64.W)) val iccm_rd_data_ecc = Output(UInt(78.W)) val scan_mode = Input(Bool()) - + val iccm_bank_wr_data = Output(Vec(ICCM_NUM_BANKS, UInt(39.W))) }) io.iccm_rd_data := 0.U io.iccm_rd_data_ecc := 0.U @@ -32,20 +32,23 @@ class el2_ifu_iccm_mem extends Module with el2_lib { val wren_bank = (0 until ICCM_NUM_BANKS).map(i=> io.iccm_wren&(io.iccm_rw_addr(ICCM_BANK_HI-1,1)===i.U)|(addr_bank_inc(ICCM_BANK_HI-1,1)===i.U)) val iccm_bank_wr_data = iccm_bank_wr_data_vec + io.iccm_bank_wr_data := iccm_bank_wr_data val rden_bank = (0 until ICCM_NUM_BANKS).map(i=> io.iccm_rden&(io.iccm_rw_addr(ICCM_BANK_HI-1,1)===i.U)|(addr_bank_inc(ICCM_BANK_HI-1,1)===i.U)) val iccm_clken = for(i<- 0 until ICCM_NUM_BANKS) yield wren_bank(i) | rden_bank(i) | io.clk_override val addr_bank = (0 until ICCM_NUM_BANKS).map(i=> Mux(wren_bank(i).asBool, io.iccm_rw_addr(ICCM_BITS-2, ICCM_BANK_INDEX_LO-1), Mux((addr_bank_inc(ICCM_BANK_HI-1,1)===i.U),addr_bank_inc(ICCM_BITS-2,ICCM_BANK_INDEX_LO-1),io.iccm_rw_addr(ICCM_BITS-2,ICCM_BANK_INDEX_LO-1)))) - println(pow(2, ICCM_INDEX_BITS).intValue) + val iccm_mem = Mem(pow(2, ICCM_INDEX_BITS).intValue, Vec(ICCM_NUM_BANKS, UInt(39.W))) val write_vec = VecInit.tabulate(ICCM_NUM_BANKS)(i=>iccm_clken(i)&wren_bank(i)) val read_enable = VecInit.tabulate(ICCM_NUM_BANKS)(i=>iccm_clken(i)&(!wren_bank(i))) //io.test := addr_bank val iccm_bank_dout = Wire(Vec(ICCM_NUM_BANKS, UInt(39.W))) + val inter = Wire(Vec(ICCM_NUM_BANKS, UInt(39.W))) for(i<-0 until ICCM_NUM_BANKS) iccm_mem.write(addr_bank(i), iccm_bank_wr_data, write_vec) - iccm_bank_dout := iccm_mem.read(addr_bank(0)) - //io.test := iccm_bank_dout + inter := iccm_mem.read(addr_bank(0)) + for(i<-0 until ICCM_NUM_BANKS) iccm_bank_dout(i) := RegNext(inter(i)) + val redundant_valid = WireInit(UInt(2.W), init = 0.U) val redundant_address = Wire(Vec(2, UInt((ICCM_BITS-2).W))) redundant_address := (0 until 2).map(i=>0.U) diff --git a/target/scala-2.12/classes/ifu/el2_ifu_iccm_mem$$anon$1.class b/target/scala-2.12/classes/ifu/el2_ifu_iccm_mem$$anon$1.class index 80fe0146c680e8ebf6e0a65732bfaad3da21f6d1..0a034168deb2dabfa9750510de8a25b1cdf571b4 100644 GIT binary patch literal 3721 zcma)9=~ok16#qR0V&VW{5$j5kC_$tc{5{ZA#4(8Ek_*6rBy=}XbDmm zLajiruV&=ZlA)({XUNJf>4rA3+S{8EP&U!e)Uz|BVYFBG4QF7TD?|m(=v4 zIi(YL_bU+P6JtTUn}^ zvd-!mXCZ_;nAr7u0!rFgOj#E-+txE0`J=uS*Rei?cNI5fCKT+%t}v=_ z7xV3~I+^d$pu+R(xKF`u4{^7GJs#D&Ua_>MpbdAritkm>?up%}V6R8rub{)@QeDiW z9#F8)qaIYS-=j__==2anEVL5ey=dFk?`()yK^$GK4-W~{_UoqZ3eAvqXMC^iQ(zd5te9sF{u^g8Rj@9!WhFDTA6fgJ?#h_De=DoFyJ;) z*Q1z>P}h{e&Un%EdQrxsAc>g>s&TfY^CZosyn6%B@yv=)Z&Nz?L>Q0bNr7!erho0^ zm6kH+!>C7!S6E$IGA=7n(H-H=tQ%1gHp~+5E3V3&D>9^*t0EJjVfT*ssdw##FdyWK zY#q`SJ&a~tU@Sh$_cjDWps8ra-aK|7sYo;I#+`rn|K$;s@z=T`Biw z7_E4VwIkCsKFw5}7(YF!;2keZ?+Wbq(_V}qXXWj*rkitCVp5W$y2%gS`LJ;V8{ELg^VwO=o>FHGGMYv$ez|8Hmn?T;fV@Fyv&{CC!Op`_c@R>4VrV~&TPzbW)GG#JFuMDf92d!*k|vR>wSfpeOIp8b>+Io8U}Fuo$Kcmg;?VUXS(2<|BdM*_in0>OvN z!CL~sZG56_bo)p-SP2BT2U06(X|AoHw0}(`I$l9$fHJSIz;!Tse1pszw?XHQm&k0?7za=NMlgz-As;n2*Z{ z`mqJm>_E@6ZCxYpCp6$MMDaHo#SZ=e89=i*ixzR67`IoodIw$TRXlQ>#&s6M*W}d* zoQ_6OgKxO#Ws3__xx%rY3L7~$b8g|>%6S{-?VNXTX6^8=5#MsG=EDN`j{jBE^gZVh xA?O^dO}16R*Xjr#5$G0tCv)Hxe6}^^AbgQ#8Z~K?E_m1jGao^LknK7TLJBd)eC)HE-tq zALMT&q2i?~l}h>vysJ1RN0 z&27l#%_SajsTNrg{U+wt!&1$C)H*F&5ifAlS-F%+JgZq%PNXR|X5wIi7&dVz;a=QsSZ>qAVLTrjE|@rys9i8|G~q6q zIF?9XGI2cNUN&(e;a)LuGU4bfpCDcp=o)u@H<}PQFsO`hZ0I(X@t)mfG-&G$fkT5$ z*V|RO9}`zGYoHTzEoEKwtMxd&=XvT)XtF4Sd`rhIye+W5DNK`I){E3x)X|M4)`wNC zdJj!3Y5s<^lyuw!tjXyPu`3}|o#P7W5gl08LluW{Pi zk9!7fc>-dYY0z??uFpjBEw8ZZhGFCtWTzm)M_^z8Re{3RS*ew`{BPF8GD3sfWtBA# zDVAucxAeIAdX(Joxz~bmRHvVs6ff)`IdaE3_&OcOJ)B^nE9kt=-|YXU4a^pyv8_6IB6YA*hG8 zbAz7+iWlNfO40Y|uIR4@%r3ct3+w`&{C@35U)*iT^~F6zQg#qY*(@YwtB{n9LQ=K~ zN!cVMWs8uM4MI}32T~J)mQQi~g0ljtAl*6qD^CARrUPGc?2?N*9+Qs&RKOsHNCm@D zfzM>Yh7x>82|k+z?^c2j;~f2G!#c#jf%R0+P61$QgK$CP1@X2Cs5 z@Np&hau%FZf=?*HSF+$UHJ+p~lSkXzv zk75t`T`-{YMPXo^Eoh0g|2fxxBw1aAx1 zh!gmVvYi6gayhn-uQ?ee)oIw|*iB=-r2V9ONe4*xlk&Rx>%})5JNb12zU9Az$nQue v`Dl;7^pmoQ@d1WYe80p4bDiI@cwmp=+dt-5Jc6$$4s2S2?;{T1(+d6rI^m-Q diff --git a/target/scala-2.12/classes/ifu/el2_ifu_iccm_mem.class b/target/scala-2.12/classes/ifu/el2_ifu_iccm_mem.class index 2ec89cc8fb36251c46366df8f7a39d5c8743cc01..2bd4b2513cc3c3f11504ef72788af5087ed10bf1 100644 GIT binary patch literal 92971 zcmd2^2Vfk<)tYM8oHl&&-CbUI1HAfmcCe#wS zwrO)qeMe_oWQM}Djk`M{?Mm=cUD1x*toZWhD`U!+*7sL5pHi{CKCG1ca<$S-zuKfI zdR5*4E!{s)$qVO|EA7LkXD`*1JYVk8G+%jXZzVlYm0db3y_Yt^r;I7pI)_zd7wTL- zyHJJPT1DxT=l2cCtIFPP(z64g_wsT2B+#=}2Y;@h6Mtb)&^iCWDF1dReRz~!m?8L= zW&pof&{q+TVbTrI7YO<>q)(=apGA5KdNa|p9Q1}Ly|9;{^Ku<0=)7D`db>q0%`OZH z{!qE<+ovcQ*}mE7x!PW}w6Ik3X3nt!05?07Xo|lMvo`!nXbgJk2 zVJKgpX!%C^MESC{!8$L;EGox1!c}^q90k#GG-cT3DB$I&AB1u=@N#TNIl@M?9Pl1q zj&y&k(5nvqm))QAQpo={ME$Rm>(vRpw)cT(92B@Bvec z=Zu`RvUSzu#(7irtQfy$YKA{AqcCsaq#Xez4B?S$^3v-g3sm2tQ6<^+W0wbfL&s(- z<7$<_?y5aIvxXdjYREu4ntbf$zKv5y`F+dB>C=@7tBab;hZKw&ri=}0>&r)$mW|q0 zwW4w5Li)WdJFj3>z&CYldTBwaZ)@xjiWaApL%SiURXMM;Iw0#jvtnj z7f$zA`kJ!qYZQO&?1G%U0YU%5k&{a6*Z7nL!TQqq>x(znmK3ZUKVVwtUM-y6GAKJ+ z8?$cZu+nist*~HZsc+bh^*N0zGt1T1g+Xe+(|qB~#;GlfQOy7~Q(6Xg7KO&Ai>zDVeodgI2bzn%O=l$Cx)E48I>(IEwdgdVO}w z>Y|o8N9XS}))aP@Q@(zlZ}vnbo#$IUxcHbVJ-`1}Q?I4scd|>zJiTLQ!MbUY1?UH} zRUubcq2%!V`WJ0nKYq`S#p@?V%4>|3X#TzOvX}PTuFehyG_7Vqsc+?iEJGOlgxBg500=Zx%_npvgvmE^Ot zdP8xef3;~>y#w`ZmV5QYoeQ$m+`RIc?F&i-&bajSuv+Q&P0=#_6I7pX+L*lT?D?fb z{3EJXj$b#Uvph)t>i5mo_U4q97j0WzR4_Gj!{lx2$7W||S1J1DEMwmI)tctd2u`n1 z^rP436a*#?C| z3)U64pq#t)O8;^G@?g`ja-Xkpd2V6evf>t$ll$M=zRiIVrP{8@$oy4X`_J4oZ$)-? zVOF}fT;HoqQ1mF>7c4AWU%atu-?+`=!$n&c==FIM))YqO^zG=kFg$frskU9{9W*w# zteqICTan+tzCyGUUT-;jR`wc_?aLU^F>k_v5?`i>^Zc{2S7ol5(ORW<%xmpGbK~lf z`TZ2FWK-3Oj(L#loU;aY9$1{`uXON<_BFM2y^C$^zJ z3MUMhdJOXEw|UicU%!O~^IG~tzq!Zv?Nz1pa^yev$ncDf?(!6GY|`O(l`(eMFmdyG zJv)cDzo@--RS%e!=b!8-XaA|~$LZViP!9BC#^$UI6SqcIsJZZ$!Z|vx?@jCV)p@-Z zPTW|P(|cC|$&bnIznR--&x(cX6e9vX$u6iT_(eMGP_QLyO<`-(zJ^f~HcW(k`Y<;> zR;$A2e(59 z*RM)KA2`i7%9$VaM`g$NT?9Qw#M0*;PvzOXI|=*Q=86?UB4vX1;9UDOx)%L3kSmG^6bKa3FVv%P9x z#=Oh{CC4lsxrh8BTl7yQ5#H~vp13{I*T}YU`;$HP=!@4E=V3}*WKD@HcWrBKYG~>x zZ{51BsX4NETSrrCOMAZivb?#zy*(a?O{mc}+%Vzk22?MqaUo2_xvrU;nEDJ;;ogJ0m5N!;WtX^S*QHs$9-srLMa z)@GD|k^weeVTO|>z$U_gv3v^a?_|m^ZEI`YS=!#-O4U=0yDkSoVZNqTU{qUmRn|$y zzztPeePd%=T~kW~Y;FHaRgd2?`EMKRTaFV9efW(Zzuwta*I3_CU$-Ly!Ax5a9s#+* z&g+@>1xKBY-_v)tMOx|zM`5GPJ3f@3?)cC?CNyo`+SyURu{koKs--cqE7DjS*$%0x z-Z-QAk&n-y{IcWprYdW+bqMm`QK69*{9qTl2U*%hOtbEhoz__x*$Qn6Y=huBsx3?x zy)bc1W1$%dLnkn-UC@lSNPS~nq=k%!`ivI4v9+@UO`6}Lqf3C}q5kVzI_h@RH#arH zLQx78A6^L0z+HVE=!MZF+%RZTC)RC`UKG+rRuqF=!)12Lzitz(n;B(lZtDa>+r&C< za58<=0eOk&*TU$pA(tph34eBznn22ll1Ph*oG*?j;VhJK7Q*qZg0wXXU7A~|w8Ez> z+Lk7wg}A{%<4t2*8|omlqI6kl-NMR+b=6giDyfK~%`WTQ)*P7xZ&>9b%&d;~NQ*Zf ziv}^HXB6_Bv}N_1>sGe5p?;Mrs&%W++RB$^6xOfW-B+1i8bmYAzRKe46T`_nGVo=T z&0khmT2WC`Hy=4fuc{X#KmJ=yP3h{oipnL+=A-aLnKvKIrM2_x3Zd2-^mG=nwrULw zltz~#nNhZ^%n5E?32?e{f@czU*|O4kb#oV2SD*;?wLt4l*Ys0SUDcwB%2iwmlZ_J! zc^SBvc}*EbuZv=SFRF9@UL5m#G5M~4 zme8h1Xj3uzIrXbtR9aSD2@NGw=qRB=O9>TvN~q9OLWQmpDzueQp|7i~3rlMk#M+Z+ zvGycdtUZYqYfqxZ+LLIp_9R-YJ&6YWvMS2U7uJ=PE?Q7mR<*1a!;>KJbT5%!y{xis zWmN^WFhSvUU{VA?WqG;9lEH;U)xgF0)m*29zz}Uj&)6&1woS))fO$FRb@HmkM2q{i2|3( zXqc4hMRm34W-TRoEkaRPs+Y+@BovS8)ub$5RE^SFBDLjibHr&3=YPlcWm zDm0Z)sV|R5puRkwN`1MLO8qDG<*~F_dlFx)J&6`;Pol-zlW4K_BwDOJiAMTWFD|X9 zTei4vd2MCglIrEP&?Qh^ySxZJ9VP=vMg7LQF#X25osq;q75rlnhSs|;Y5|h4VX!Yh)DV@|d+fas?7N!WA zSHcp@suot()Kyo`1AZljB24r*HH+K*d=bIMM~-&Pq4{ddj4=+1^{i3wV^Ztil@F=j zqn%9VWIUtzzPY&;H){dKK%cO&wY8(Yqpg0M z!p?PSkYrK9IoStnQ_E&2#U;3G_qIs#AD!x(qLzX)3?)nH6;v{nP%mA{#+_mPwr$P3 z6_$@ecUL+H=PJE(7*qOS4QNwSOQWImQ_=_xi$Viq#OVQUO=rt8SSmlD41mWkTwJld zx-y@Z36k(4mqE(lbY-A|RUm`kSea`MY04288@AQA)o+bpeTfXw&Z}#!qf$jRGt$zIC)TA6 z4Y-$X;YDEZ+aPgL-vI#WUaXTX+QS{uvj z8@5E?{KI0aCeFvvP69#(>;n?#Pu*UO=wY4a0fQ-zRJ=R}1d%x{Fs0Frw^JCun!-rM z3uEMPa^uqEMk<~gV~T-$_PW*`k+!y`#z-0-1H0tGV9FyEFF(!AjZ2dosd#Qwj8ivU zn%qd`QZ0&xWc9lkd^4R+h3hoaVUUyvz>i!4xV8k4ln9{iT>`ka1dx;npuSxKxV8k4 zln6w9L9FSdDO+M7z+pikDS<#WyO)I`4Gn3^))*LYSujXSV8}77PO!b{cvN*;3KaA=Uo)zKy+;hNFAss#)0VC5|BDj5xhjKftw}6YIR+EM|}sXK^oyL?zU;OCah5MN%gyj&TCIHdUfzd=AAiPC(a|fYb?!W1N7lEdi+$6r(zwWuR+I zKw8tqF*QxsmVmUTi(_hDm&I*7T&9nx<=0fRgbwJt?N9>Dm&I*7T&9nx<<@Kw8t2VrrVMEdgmwPl~B&y0!$Q zH9aY&rs>)ekk<61n3|?*OF&xFlVWO`t}Ov1)wamCW`zwMU1dL%;*XxjxG%9%zY%|U zrlXMnX43_uolgX2Bo{Z7SC!W?n6A8z96PXG6gxnxWzTVGQc2HB%1f&;Y})rC_QR4j zF{H2eafz8TN;lYDI_sXu)WcBzr2LtR^B0=uV^8eHj*WF4c-FF|z8&*}A*0>Ki?gL~ z8=jeF#|k3baqeuB!Whc?%HK$d4=^UhV%2SGZEiHT**cZu^n644rx5*@Lk<2AP81-= zg0pE5`Hv9!$Wi3YTiVPb!yBvz%iMk3S8)c=DIa>U<_CmB2MZ9Un4ZiON#PCU3+2CL zm@jD(yCbp#k9l#k*wnEbw>AxU;vC>l=P3JhLFdo-a^qR^4WFMw`BaqJ_4{Ue`j{O{ zfMjsv5pv0{* z_rM}FliA&{L?0#dN2#{O>_^3Ev@|MKFh!CtUaC~(7~h=wpf<3A;&@UxqZ{oEUmssz z)PS!a?$g_LY^`rU4qGp_)^{|Zb(AD^6}O&oj-wJ5`VjGaS*I(i2t3(zW&(wAi|ka` zhLw1y{Tnw;OqPakh;Jwr1xpU7Bur%Sl(?a_F#_LhBo~6EqD0hbzNr5ZHhW`4u+R5a zZi#|1y^q39{+ghoJ|fB0HjCspdbsQ(!|PObGDDy}f;*&0qiqmTY}CZ^9@K;+%NQdV zz9W6(sa_`V+K*O2-4qP8)K=}90tNL_B7k1olzit!ISFB`6h&L;ym zd{ceXsF2eQ*1#Imna>Bq`$vzdGT0`znXYGJG`Ak>D=duR(c$*dO-eHiwuLp3Kp930 zOCZ1b_}vZInbz46p#@I>uP}TSzRDo@=Av@N9soRhi-Q%9{|$C5JB~o{1O(kDCpsYw zU$p>RsIZaHE1$*{itEr9V&$$bpFi`mHb>OuN4BF=9qrl>F=NaMg{^hdzQ$3X(DS6K zS$ijhR_f>~7>6|rt1mOyR*?d&MWj}71FkVxE89jkS!=NE;+ORXYZIwDgSCrPy}>#} zs=;8LA{8;%4k5eQU^@k^$zZz#?Kp$&7PPGfJ6@z(4R(S^Z8z8+k!m;CUXkiF*glck zX|NMTYPZ2o5_l&VY`;kDHQ31_b)vye5q$d%_8pNr#bBq3)TstLO{7jY*y$p5roqk- zsk04srbvCyU}uTc_YHQoNS$Y}?}|JwFxdA*>LP=kBT| zVCRd}RR+62q^>d8g#!6HgIy$2HyG?>{5}s-C&oA z)SU*qT%_(Y*cBpm&|p`J)IA2fN~G>H*wrHSfWfX2x;$jCYX$8QgIy<5j~eWHk$T)< zH;B}e2D?$Do;KJ`BK0$a-7Hc+H`tFv>N$hmB9MP+upbNB^9H+Bq<&+t+eGR`gZ)IL zerK@TMe6qkyF;X2G1#3V^_syBh}0hpc9%%KVX(VJ>MesE6sbQMtV^W+Vz7He>K%jK zD^l+n>^`B@-wbxYNd4Vl4~Sp?X|M-H>fZ)?NTmK_u!lwJV}m^+QlA>^kdXb{V2=vg ze+~ASNPT6n$9c-H80-m=@*C_)k(_n9k)NF&jB~nKj>}`=MGuWR*s={D@7OA-g`-@1;H`rfA z3T1moq^b?}u1GC1*n1+i#9;4>RE@#@CQ|4DKM*POfPWXMRR;TqNTC<}r%0_c*uO+- zgTekSQpXtVLy_8Ou>XiuqrpBBsZ9p^SfsWX>=ThX)?lBCRI|Z86R8%1eJ)bl4EBXc zwHfTcBGqBAFGXsH!M+lyU3e%bQpX#LB2s${#V1nx48<=}CmD(=QYRaVCQ{!q6kViF z!^068F!=MQ=t#!*x`};oV#G+wRJ~X*@ljER6y4Y+7)K?ziT1s}FG3Z7B2TCjM` z-HypP-J2i<=V%EgpH4dW(|Bhs^v+u3owe9It7$4P#hUCLb&7Y^se*NEH+D7m0UZvr zX zzr^a%e~Hzj{}QWdS6RO$w#iz1XoXRakoh^SiP3H;!6F--V|Ltj!x-JuDHszfXYbDy ze6n%Zv29l{$$Hh;-MroC7v28Yjehp7$Zqr#JHP}}LJQNXV|Og}Bqd=bME4a7EZJ}? zwh)`!jRl)*ys~y0S5*ie+4RZcp1sEsuoJhx=st!vDdo$vRhlQ1!odn zdDGyDBXK4Z%CQ+-@XFea$t#Lt z)w|5uO-8jVN#T9GDC^1;dR@_~Soc8{^|BzR{{G6!|;!l%W9By-SM)+BS#Sk@$S&{)fazl7@1e~Hzj{}QW5|0PzB{!6SL{g+si*fs9m711vYkxWVO zq6xjyA{b;{8oh}k-tG`QvM$ZyN#3PdTr_g>aYEMp6BG6R;&mCpC!6lY@Hr;3vXOwe z&6jHgq-==dOwo641f#6mje8YGu*$3#eM3j^$R-r77k31kY{}1hpC>tx{hCj5ot&d$ zqRgU0T_UZc?*{SulyyszSBQjWvdVYAStR&mBeDI$kzkS4xZ^#f#FmJ@o|IT8_ghPX zF9#3Vtvyuc;T#5=!lvShlZrhBv>DF&neP=a*fchsejH`65|J8%%?%E=75prYp>9gd zo{!lx3^s$!B%C7^HU_+6pHcUxaZLBh8_m(&dt|WLY!2mEXs}X|cd^0B1Z}dx%0&vh z6MK*cw+)r5LZFnmZ6Z$K81Jx&hch?~HkZvKg|XWrp*iisRf!^%8f<|`l^d*Dq$&-z zP^9J=Y>}w6DuXQ+v;_uRB4`T@wp64R8>~j8mKv;9q-qVeOh_y@*m6je#u<2DEy9>>)Q8Xm_TBT{%A zS1(d{9Jf)Vwqe_y!@f1x|J2rq3Ynq~$Ho#Bdq4G=O)X6wFlNZTHwZf{)J}Crkd0Ay zVn<2z6`^HYaIy`ZX%bL(2U!9An#E82+0@yR-xAqLyH^H`mhULVz76bJ%@?~)l_qSm zjN)3a9#!F(poV%nduCaE8{P=3+|>}_M>Pf1lh8iYaisXkc>CFEfoNI*^*gj#r7GGi zD{$Nhy&I>V7F17FPlt{cyJ*h=^-S#60X%ZM5Mh zifCJZhM``f{vfFCSAU4@ZC2r^#Rb&M9F(%Aj`o0h1@?l8&crdn}1*|b%hz(p@Nj&uqnGs-RMkAqO@R!=HbLA!wZ6Lbxh`Uy_`3aEErvyt74 zC*a~1Igqa2sosSureZZ<-{=%ai%K9UITs8Sc2MmK0_z@Z2Da35GX~WAQ1^|kb>&=oP=6SKz#)JWX+?mX!F<7=*~vo znrxh&DgtMCRDCR{9#S7Slo_HyJ&B#{=rE3Scu%(-0ruT#+dJ!g(#rARDCq0jj|}Fc}m7 z6t*E+NxXXP%zIi%Hh?gS`iA;uP`zAzi?(Vb=lZP}QXH9bE?eg7%Jfg_pM&c2>R&LM zqJsO>cSr|#EZ1RUeVd`aFIfHt`(Pg__W{HTHk|S_;;28^r;Fv|4CncxCODv?5ONIf}*g|@Aj*EkN4P~upYPhFaEG)F#P&NqKN~=F0MZezufEV4+R%>g}=WA>6 zHbWuaG1U18kA$xfEks-)Au$k~9fyP<%(lkk&W@($3FY< z6m3T|JGa`11AR1J$yW%w2;(8)E5r~fu8@c` z=vK4PpoEnPcR!`+=B#Kjv~0qsmW1;f?jIgVfD`JSE5CTZWr zZM9Ve~BZ{ zi?l3jtH*g1?R3A6a_4GS1!1tO@peiaa}^yAOtFI4L&9#bbm7ZvEU|ivi6|z&vVTv;oGCJ8GwP zAjnkhF7$XIi@e@)@gEJwOf0#w5h4Bt)qE@DWN^5{UXSQYQI$2gsAD{ z%uz7WudAtTr^&*xD|-Qy7ARs(tb|^ z-OE@Du?oDhsSPI~X}HVkWoO4}ypwo6U3*Q#Jy&1*H|vHCYfhpAdLx~MwKws~f|#$q zP2H6RZZT771oxlQSzqlh)DB^jzS=uf=qj84Yo3A7k~3xXUJxq2A4E|w3+XEwnsr=O zO;f`b(k`I=9etbG=3{^4w)khd_7Ck}w20HvAx5?~y!#1%t1`3?wg1r2_7SFIbPQK> zv{%IVJrZjelD;W=u5=B(Y>NT%6YbL=^7t&|t2NX;>R$5r|Mt?gFa7xLk)Hy*D3Bxc zuZ^@d)i*aC&pRyLht~k2U9Wk(R(1W>jg9p<2B&^geM3iU+wOp_qUqK*(-~71O<|`w z*P%>NFl>oEqI`y1ykYfA%Y{Q z^0%&N;5ziS1_c|PIzK&I&k5=wJvXGHla9_19E&jd^^Nu0I_QPeX$gwqFs{88Xf-1- zP1XDA{ooOLf7mCC`gT^ETqL9qB&WgRf(2kk{4l7no9!g1q9z^Ij?XQAf@ z^gM-GmXVs&!Awm_AD*rc(=m(~4fQQ$ofzNe;*9T;w$DhQC# zn5k{0GwrG^1)@cXAHbzpvLy+9tUivaw7^hy^FCW2@0#*c&tmsl_Aqdmy)&%_>Jza# zuVdyIbsNW8jpa6mUM%W<66$_(4)as(40g{n%%z#A$TT4`9U>(;OeK+MCXVG3OQL7K zDaJT`mOh(&a}F{)sypB0A|bsjhiRmgVYxZ(w&6>aXm_@0iNrl-Ub;S4pN|Q)a7nzq zzXkIW@o|ZOel$(6CBJad>U4d9zED33ErI^SYj%93(wD+@wzck5m^QkiVoZgh*XqlH zU|o*B2UB`X1dA$oLN`N%nZwd(K%iw+0{A8;VPYz)AFrQ)RULhgq0JV0 z?1LUB=CE|qBaP->R8^RaIHsjUt%z)@?`)=dlzy^)3g)l+cd+DU8P>@W&`)!%Rk^2C z?yHn5M3f4n#u-8VbRGAd(M3Lb7CI?f6KCsX)JJ?5#r+;yvb`i1brTwVzMsQ_`nf1s z+~9+I-hh6-!d6>dy<@E5D{Yo7dRivlAzw%x@{8jv@Dm1{_Y1T%MWu{2DJk7 z^Cxbls+*3B1oX?{U~M@1rL7%3!IerdL%%}5N;V5|+^jBcX@KN4yjPCSn#_S-Hd}~e z3hCDwTD|fq8T|$*dSgiWRA%=gH2+-vM>)*UZ^1nteX*he?RbP`W~+XRaNir3iJ{-B z-)6&QSJ>S;8+3c7|N-F_9Co{ex|jp z#?XJq7r6D84CM^*rlvYYQA)b#oS8%ITiHef5aWO-7Uua$~*Ko z)AcuWyimVZXo(l<*O2Bu{V%R_Z`}QX`-;yzqc^m6TYo1A=y!21Ne?nF5X$03{FMU# z?}l=*p#2j&JVfsQrW;Q@>iD7f;Uh!2T%B!#bcrs}S|bXK2+*U!z^Gn&0P|q^4S`D}6d0QW&xM~S(XGhR%?KPRG8m5xCgiXj zG+E`>qIg&*&2f3=+@@xH;VXbO)81~Ux%+* zR%|<;5>;l7Q06EoQ<}qasTA&^W@?nTLhx3CcWw^rO}xHB=q8qak?<8xwyu!y6=IQ0 z{Dy?D5G!Qj3JG5!9sr3eBz%R_tt%vabo3|xjS@aO;!|89;iL0A#T61hI)PJMA>pIr zHN_R_LI-AwE7FBd!xUGf3!Qo?u1FU;$5LF8E_6txxFTKX1WJBI2_Ky_DXvHtI!01l zkuG#bq_`qo=m1D@MY_=Gj^c`Rp`#nc73o6fGKwqGg$`X5SELJ_s3@*T7dj)6Us1wG zXCaC!(uEE>6j!7Ronk1iNEbSyP+XBNbpD{YB30?dDQYL@fB=zIv*&h~|=xwO|x! z6l}7=9J_|xmK3ZN(JTUiyA^hU1pez@F_J7qximI^k1ii6S%I!#;9%e$wE27SD6E;U zemPV(0`~{*%3*y1Sej0^KjMugymEekT4rqr?k5-4Z(Bx7YP1}R&0UK+w{FCl?t+q2 zjcs|&D{y!pU7N&^DEJcV{P%X;&{nlz$%5~oqod%1Vy_tbL7;}=mUK-2iY9&xdudBc zD-P_%Iu#g07;VK7{Q?uDUbS>!eN{^{bfKkQ+#qlY)Mt6j$5e(^fYWSpXm2iVZgXfG zE|0MZm&e#n%ap)FNc-3<{Ep48_VrP?#+Fz6ntsQ|SNocN$M#p(H8!%^*OmAkdr|G{ z`MAb@Q~Ua8Tw~X%>$=);P5EI5s{K1%V;?Hl8@o_lbnHdtbnHasG4`SI7`sq;j6J9> ze(XfGuSrkrN9BCjddg#LJmoRAo$?r)PI-(ir#!}nQyycxDUY$)l*ia=%42LaK7hl}&$6fPd)3@#p@V*dUe zGd|UfPcvhjyv6x&?iP=6>K2c2<`$1};ueo_-WHE>+7^#-))tR((iV?#&K8ex$`+4t z#ukrp!WNG&G;uC6&G?`hcbV}$W{h*OI3G^M;xW#|;_(9}{XsK+$c!I0<44RG z=U{PuoPxz;oPovT$IbW&Gk(&HpE6^de8u^2?iG)5>J^W1<`s`|;uVi^-W88=+7*v+ z))kL&(iM+!&J~ZJH)EV`#jjs5uU|Cd-u83Gpcy}Pcz2(RQwvJQ}OsiGyabme`LlVn=#I$;(R!fipMyQipQUu z@fT+NUo-yFjK2~wok2zX3QnNnG0vajvEPhUGuF&lr&u|}(rH6DW+)GXdk@ATdeCs> z{YqcPs>hA(Qo;)ho?=?T9S4-5V{?_fab3!YE(PI)h2zE+bScFv3+{k`Kkx{`45s{- zfKn1T1cHuHjj_RjM-d(YWDOs+ouo_#HG>Vq?!>7W%aEIru1v$zjmMDI6eXR7 zpcFRMexphaaVa&^R%%u|^z+RF5n*(xuc2Td9@Fl*0DeZ&ayKE~Qr6O07wz6gC=uqe@M4DYed4YJD=Lu+#Bd zRI1Ka>X>9oVN>5Xs#J-~QX6fh8j>l6{e|D6QW0CJP05tP&M2=+HT9%R=Xs#JSVl4>QGnrD@9OhN29(A5!mr^@z zrFJD#3cDY?Ds_BMEH&Jv)Csmydy*-Ihb>-}InJeN|Z z*h+mTnNoQ0^o=St-=)-Pwo<1jQwk5fyeieBNuFD&Gi{~LN~RQ^y?IsYdp+?fw^HZW zN_{_>Qg{sLRjD31dX=mC&a;&|KbcZ^+~-xP9`#cTTuNPND|JyarSQD*8&#^>rPL+1 zQa?zh6rOc{qe?AyDRrr>)Md$(!eiHORH-E{rLM4*x-ywkc=+p8sU8i;Zl$iamAWRG zQg{ySRjD4`w!4+O&Q|LBWJ=+YxL2im)Fmu+Ro{)aQa2@23Qy;~D%GPdp~j`uk8GuG zNv0Gw3V2njM?U3N>Q-B++mb1TJquoy>d~TEt;dv~@~IUrOC7Y8>Pn^*HjsRyO09G$b+4_|eaV!b+rLe=tt5QAcJXg7@?@?Q+$C4?9%|>38>XDEsh=lP3cJC+MWvpzmHI_8rLYOjt5QAk zsr4>P{mNGA`D99A>zG%idbB>Z(WTUHY^7dErW7`wc~z=M>r)LbrG9HG^}EDMDauRA z?@gsD@%W3s!!veZ!M(~K=%Ja<@r*2Bqtk0Xe^lPU@06mapbAgDg8d0T{){Z$2XaVx z1<%P83Pn1v1f=BCT9O~yQIVL^Bbl1;kRB}%H z+*v=Lp?*FmJNTG92cPCK2fPqy=HT-=asW950_C7f&EiX!XAoC;A_KGX2o{jR1WISg zG2_j`9fHi_%Wx{@X(l^IWNUiVGVKm*r9{N>b<`H@;t`k(KMKBr%U(c zU}FK9KHZm#MnV;n?(2=*RN>gZY+j~JKNv$`3E@Y|IqVx?R{0V@5@_1kaRo=->&r`) zahjcRns1<4BWb=tR5(KL4aV*wzm?%YWHtzYgL#I-~&R{O;b%%l0>F@2yNYkVuSx>AKmaZR;DW;hT-+ z>`i#LH0Ks?!pBR6w|NsjK`PwlO?Zz~xWk+9Ua9a7Z^HYe!n?c)pC}bR-kb1A(t6(G zO?balc%L`nlcmBZc@sWGTIQ3z34cc_{2gz?r%HuS^CoU!lz4x&+;aGhE({w z-h|JT3ZLUm_$;aLx!#1&mI|NmP58S~54+Ht@b{#`7kd*vM=JaSZ^GY~3Sa6?_*|** z<=%wPlL}wyP56AN@YUXgFOUjf>rMDVsgqpqP52_I@QvPtFO~}5>`nL*sqih{gnu9v zzSW!X52eCC@g{t!RQL{W!k0;f4|o&4Tq=CGH{mO!!d>2kuapYk>rMD7sqp>Ygs+wg zKj=;P8fmL~*qiXR(wq-@6TVI={Fpc4>!rd^coV)sD*Ti;;TxsGKlLVjlT`Q_Z^AcA zg`f2%{3EIGFT4rgB6X5qc@zGzH0NJ?6TVd{{DL>(+oZz3^(OoisqjnQgm0G$zwAx; z4yo{~-h}Uz3cv16_<&USkKTmuk_x}+P55r9@Y~*m4@!mq>`k~!D*RV(!uLpp-}NSZ zuT=PbZ^HLUo8$-HgzuLM|HGT`15&mB~K3V-HJ z_>k1vUw9LKRGRab-h>~M3HzBh;m4)IK5xQLNQG5z!cR(tb#KB?NrltA2|q2XDu2+M z@K2>V8{UNR4U70iQ-78>VI0jb5e|71#tHut;T&(m&q@u}+nexnQsKVdgmGw|MD70G zgmE^kM0kKV;a^FG2YC~IUMf7qoA9swLv6M3L>3P%w6S;l^KO$qy@+`_!(Nc)JltE( zFG__+coY7uRCts(;onJx$9NNdNh&j@KSHW?@NViy$SzK zD(vwQ@&{63kB^Z5E*19p2>BmU;kDk%{7`nM%sc@4w;ZLN($9WU}R4TmHoA75+;Z|?LpG$?edlUXbD%|c(_`g!& zPH)0rN`-fN6aGpnyxWs7j>nVDw@>gUtVo6TdK30Zg-`S*?3W7f_a>}Lg-`J&tVxAW z^(L%Kg-`b+>_0=kk7;?&_c8g;ltZpe0rD(4_sc!rA>;h=3OVGy6diIA zQ-Hir4%w9g;bXm*kKirU3bSIpjwvK)x)8{3Hd)SLBeNr2zS=yvD!q z4jJb}ugSIi(mP~ajlV91^s^Ko{~(9-r2zRyIi#8bnBL&F+${}Z^0QsdHGKDjy{9nl-OM9-R z%H)vcDL^W6$jTHTeR9ZoDM0$=kX0!_s&dE$DL`s+$b~6D>T<}%DL@9~kV{j5Op`;_ zrU02PhfHC!q#Be%rm$I3&5%Q;uvt~sLq<}7%#lNGP60Ak4%w6fWN$g-aVbFdkwb1x0kW?gvNZ+Besaj|DM0p@L$;>? z8J0tKrT{rW4!JW0$boXm-6=p0l0%-50_0#h}WGfq#7)W1reX-b@>N0SSl4>5-TjeRvRl^BNeWR6`mEZ zK60*=3NMQlo-Gw#CN?J~#8a$roiyj;Vui&AhGK<}kqU2(6&9bji50Gw3b)1z zZ;*P}Myc@jSm9&hg+ry7iL}MJXP4R$D=fYS<5oMzSK+HPg(LWG1%0vMh_S1y9}}Mn z=r#5MHfHtMd(>SAedXgGzlrJN9)ILcv{j+%K{` z!u*gxj;}glmiU+eWm!O3o^a5&;OogU6jt}Bd&Rh_+{J?UYyxBNjO|iS(FShmQqMrD zV_`v;dd|J-xdr}*)bqR4i*I7-i;nD4FMZ^Ydif#s%Fsyv0rk2E)EidksyBuPhl=h| zf7GSkc1XP)}xq4XZrQr^2e8X-0__)*RU` z42^Q+J0vv4L%u^o`ObXrM5Xp(Ls*`=pPkGuU>746)wYbOU$Hz~FrN}o&w?AM`@g~` zJ#2z6pdJdS=YPdom}W6W83S&j$;>|^5#)|Em~CT2xW~?h$@7@5KCS)~p90BZgVdj~ zso=SorK!(=rm>Tt-_Jp#Pp7=2?lV7C^p1KWeX58*0ZjL)`$8cQLa5JY)#pTg`i6@7 zRGJ*M_)AGGK7UAko>*+N|0c27!S|xts5&g47h0Oc@(0wH2X?8ib*X=Ji8Le@dE3Q! zRAR=zLYH@C`s_|D^PXIvY<6~H8Mi{mCT9HL4%C~*db57;qcN<6&9eQeg8Zpp)P2aG zD!Km*b-Rjiw0Qq{9?Xu9VBS>qQuBCD7&0~YKbZ$My&b3+@ zQu0=&1+@&bhkgdb4@O+&-2+<4X{;+9Wf~c(OjstZx5GYtCHA2KdTf{0Uu#4-Ky7s4 zu1kokJ}eZHbg!dA{Su4GyVp^nF^NUqMhTFORK-!D*@*?;qoP|wmNqC^x03*TTVn8s z9fleeN=wM74aFqL!8extj9vh`R#KgJ_bqGt~(noNYo&}fABbQbdu{3QMbqLBd zmZuFjJA`*FH&@RQOxEs}6dS|oi5@VwG zl+5~}@Q)J9yzNvto1K@K^RG_M(7Ys!D4IF6ICY;M>YG>wqe>E+PY=yZEb1IHriVr( zX5>Sj%be3g>l3rf2i56b=fTrM3ln3zY?;mOO3e9z!|KyREeRR5bu`2kvocnRq3wP4 zU#y5&chxIth{K0p6Ap2>Q5NId-5$m_KWDb5XE}V%IZb(#P4~Ucrunnjbl&D^T&u*m zww{k`MHtsM@No@a5!LEwTx0KITsuaLYyN3gzk^hQ>07=1vDSqQB|*OvKA>%;F+hDt zy?nKQTv>(>4R_)v_ zbLLj=HMjDRhuo+o^V~FfZWUg0tKh5I^0ju2Zu?y(t4OjQra4Vk5t^LXWX_d|iX^2~ zoimGyWJ?%kCGcAbGK)2MUUNvp4a|+WzmATg;=Z*EOXB7116IMki+ipw*BZBxN-%EU zq}^=ZFWiY4K8@RZ?FzU>I%7R1v?8G;)VGE6+-lu;T^Snc9GH&@wI`N+7zK@%iau5C zXW{{tXoq{P(y+aWN^_fCnm5eS+-8^Nc1(O<)LeH9^`RMw)sfFI>yvfT-ITsQ*;=Qp z^!3rYWVhL+zb#Se@32dMG9GeJT`saqFR#mn(DK9vaF<3>ISmf=7TM}8N~GSMwt5H5 z%GqbDC#jsq(5%F|$t$NZv^cRyx5a666lb4ZoPE;bFh%Y3nGZszoz8MFnPx+VV!BID z_U_T{9(%8LKmHyZi>H&r@N`mpq)U7Jkb2fZbp+j7R*$16dD@fX><4-2^gz*kdUz;$ z$8L4)eM7k@nY~Cr81%Ri7*8K*V`PYhzr-m0_%dY_MXYCbh-Zkv`dL_Wfazh~R_RLB z*^K*#Mkcm1-RD9u=IK`d(741R&fDDnN%~LiTwvpI=W9IDp6$|p)usIg7Z|HzY4)ht zKh!5-&U~fvpgMXi8MGu24sesc7!EkhkQPphngQbnmW`dZ2q(1#_*Y*g>_3Y;(#%brLsGdN`d- zq)!N^J4_S|2Zf1FMXt!G(9&smsDD%^y-1ql)Yu%SNZDq_vQ3k+Rm8H*7<)jkf(;Jn zi+bye$9Cy8r+4Wqy7V<&dR=#x9>d26v%P44b5!J*Bu=GoJgCk=uA9l^uy!+4icZqT zCGl^4+d;L=A=&AYEJ!j1A;}6Dq+911A98Fmh&s>s(4c5VX~KEtdcm9E>{6n56P*2( zi8o*7Z@YynVyP6?;%l~k^Vyhlp}8;=hI;ZzoxT@NXE|J9C_P#Zy-1ehe$)BYm%H>+ zMI+PfHii~wu9aGdlR|k8#IrE-I;b9PS_X4fYNOB`oq~;FNlp$q8>HP%Cx?bc0Zr3X z17bx~S?Kfm{rY)MSJp4EV5e}`Go4buSlS9MbBSJYpMJH%4(Zq4um6~_`}EuC(Ibkn zNGf}GBH4SLvP&R~6>k0hc#F*n4U860e}HFIW3oRK&puniz6|W-%BF!Oo!}g~AJ38a z@d_CCqFCcT<|?Ia+@nG{4&CL(ecCBXUF0f^``nrIXS(!f<4aiStZ`kq&>D2B`Y#;) z!rV}A;CrxGFR_IqyNWftN+cBLw}=(dLJ%zjo>GS^ehG zp={t-{pS1Bip>5tJ$r^(5f!*TJro@OSm$ulgawH+QYo%~Wl8(_dS6(=e zo9oMPp2J+j!o!5QVg~Xh$({;9PuDbJX-H43rf3+$!^0`}01FRyEYbrIN6BCO#n?y}$OJYXn znsiMl@uW(1ww;=6c4k6IjrKTpl#B_F;TF)tV;mM38^(|JHhK4c_1YwJVCsDVIxftY z&H`!S=-OFENkKTedKRGU7_rBrDj@+k&r$}>O<#ps*+0Dq+WRF}^!&A8e{lilo3QP-6b9jrR8(7`# z$R+Xa)m}%g)ydq2k6cppZbz=^;px1P1H#iCg)9k|I11@(5~~k?)BVUbD?E#X4hhe4fX)ujc7VFx8e8La zZ zz_$W^^8wn15%Dw#oHE_*};@HWvGbW@77S3){<1LVO>4hCPS39u6tbD=(<~eQ)_b^nI-EPdg@U zds+wL`_i6C!|&-?=|j_pA-*sDnRHwSgTaBpA&AcoULL$k-JkJL#xF9SSN9w9jn&3F zb${kLnO9|AtM1P_I%{p#2E?EB%IKA)?hlO#m4xsDUg)OKy`cxx{n?|lr)NW-oXngd zIe6hSw^!~Fxx*1R=62@pQup_s-+Og$;Pp}a^y$+d@!fr%?DJD~f8V$Ie%Kd!_N(vL z)~^%soBjUX?;~}8|EK%E)c+NAfB0wNm&32A`v(jeFkwKEx__WHuR0!h7WxK7c*VVjJ{)*4tx7&dd%+CMLsOtnXoD z=*;wRvjIKG-KjxOVrJ6*m4GER(Zb-*i5XacAN;TqI|)zKy(`9q&!7=vyeA zvxMJPe(nw%HWG3+^oZ{~~Yq_+Iiq zD817H|Ev6+Ly#y9$!oD&#(04u?`fC(tgY)Y45PfdI_7Ncd%)CC;qNx)AidB-@!`oeZLa@RW?I^ z2l4xCR$w5T9XOiJ30wjPf1Z^FK4Fz<1#E8GPuRTl0Gl7&&#E$Zv!gR^Webd{tlD^w zEzCTfEy+BCEzYW7OL|?$7WaCVEeUn7rJ;YZCD}t*O>R1?%{_ql4YsUzDO=gQjIHSX zC0p5dJzLTDG`6zec($tFt%zS@tHY18H3OR2>H(LrwF5q9>j&;*8wS3{jv3UK)eovh zyqIkqyqz@+ex5aAS*Bsg5XMiv^xcgYx@KZAxeD(c`*3XCAe3S%Q}B*uT3`WaD%*^aaDf~K>3SYBWeXqxf@Xp2EhQyvCw31|V|$Dl0*E$Dj#v>MRT(>g$_18$gSIHY964Xq!MA+$#&T&7d8T^$BQOKpPsufqQ`_(1wL@;9lTZ(DFhL zfOZ^c`Jo#?YX)t2_Ds;Wf;KXHBxo(5jmXIZtrfJSzU#g=MK%3N;>SzyW#r--#+Y8#1es!Sj18s7@k3c&Sv}yhR2--=YP3`{*X!}7c z>Hj2XCxbRU{2FMdfHpJyG-%%eZN`8i&`t$y_JBd4od(*hfnm^22koeVe$dVUZO))3 z(9Q&{Y)~y|XMt8a_-xS52CZUnCurXV4G*w}3>8PEhQfMZy&rm|htd9L!Efmm(Dbq6 z?hTxOZ{R}rtF;W`kK$+XYHhmxx?{R}V&EeC*bQ|bGf&XeixVPW5{oR((({ZwEg^Eu z>%feObLKoF&(dcnu*PMvI*a4JJR@&OsPh%E$j-C4JlJ`ALgcGrk)7vcc|bl}FEg!C zgr1C!hDsaDUE`WqVCT6|Y1|>)=R)b1BsA=Gu~_1Ka?ggnBO&q)vB=`^a?i*QCo29; zvA{?1mLZPCk{18*gi8J>7OV8IT3KL3U}OT1{c$YvF^7kIWJ2WIVv*|)4|z^P!GjCcUzL5K$<9*Xz~#KX9JHp^!t*(h+0!L(p3vM4}&B;pCI zkQJ%vY!c$hEIsf9_+QR7LG#4`6<+QD;kdL zQs_`@g=P$jhEpjO9b=j})qpkoW-+#vf))x|eQOxoPN_Bu+9~Lupp$|f^y^Ma?V{9f zN*zzZ2^8$1U@ryxC^(UVlZbCW1t(K*3emnp!KoCSM#1S6oI$~v6r4rD*%W-2B)&(% zITU=Kf^#W2kAm|lxPXESiTNT5E~elT3VuMr4=K2mg3BmqP~Kwfa!Or6!IczTMZwh+ zTtiUTQtCPiuBYGz3T~v}CJJt*;71hPLd-v=)U6cUM!`=gxQl|@DY%1zJ1ICo!QB)b zq@as}dnmY$Vbm4eqO zc%6bjQ1C|z-k{)33f`jNZ3_NG!JjGk3k83r;2jFyrQkgZ-lyPi6nsFz-zoS91^=Yr zUljbCf)6S94+S4l@G%9SAW+_<3jLHWKcnDt3cjG=zZ85)!B+?rMu9?sj{-jhDg_z^ zIs&$d0{To3qc13lZ!mqRyvvkNaIlo}4yFEqfYDcL7=3kwf1-%d7n2x$B8Y#ThtYQ) z7=0;%(MKEj*J&7i3kpFS^DXu*VZIt)E%Tp2!I>1CMZwwlQn~+olsbok?^AFt1?N$4 zKK*(Dr7on@MU=Xjf=ej)0R=y#;8F@Mqu_GlyMlr%DY%MgS5t5e1=mt=9R=4@a03N5 zQg9OmHj+(p6N6da_Wi-LP7xR-+aD7c@3 z2Pk-uf`&JWs)|DfkTqFHrCzLH(A3-_hku6#SlomnnFKf>-I+*C_Qm1%II6j}*K?!J8Dk zMJ#Vq>Q5B>nS#GiKp(RA)2HYC^s#t9ecs(qA7uB_C)EA)(R2SlDD_VY{zbvRDWK17 z`{@JO{*Ng5n1W9z_>_XrDEOQL`uwq9eXTeF&9*x|Dxxlz$#nr4M?l^a)OtKANe9D9ENDhk{%R=yQ!KePB`T zOF=&h`cn|5U;qUJDWK2isr11+l|E6Y4yE7-3i2ozhJb%DhtZdB7=56Ne@u#hMTyZD zff#*ThS4`-7=7!7(KlQ82YPU5IWFn5HB5Z3Nx}4KEd?7WsHdQjg3S~(Q}BNs-7yEk zQ51&pbKg|7)LLUptqrwAN=psV5`B%9XlRLumWYUmh=_=Yh=>#s5%q1l&wu$j!m`=s_QfFn}S9U5Fpfq5K2O5|MzBg_xA4QPKyqbAFP?#ckjJ<^XAQ)y0g!Gf8Rrl zu?fD16xO4DbNje(Lt!=I>iXK+#_Gm!qmL;H8&JEozBSxXG_Jm>E!@&n(=e_)yrrgg zcSUnudqddAyb4QisNcki5&M{?uwJp8#=`JY;I-GOv>3$u3UwloT6^-&dAdJj35z3oFW~Vr~17vdjXN(`PPILAOXz zdggdNgLBF387!JU0F^6VCCw3pmFQIQaCAz?Yfu?E#Wkz?Xyn zvUGvJJst4b0=|~=%@FW{48WHN_-2B4bHGC`#RbKhM{8H0rx~QjoSHO$rWO|P^`+Z$Y6dCA-eF46t9kY*nHiZwlwFwv z{JYbXWlEr?R2h9#y&w^~bJ{O7loQ(QhuTg!jAA<7rh?K9t zN0cv9Yu9-BCQ>;@65pC`D8~?wU5-$?U5-3nj-37|#}ZzSW|X5WJyMR9W;y)cgN0lN zL$2+;NUrTZ=x*3F-^cjef%lheJS^n#pz6L$ENP@z&hY;}%*+1y2{r+nzN%;H0;e4c)JnKg$j zSA4t6_U`O9aB#p|oW8v#H1Uuvz3L{9@Ommo=u?$(YYH1m2Ih|#qKpb?D~g5}&l$0; zY-Qc53i^FcrqZy==PAnb=j0cA8Y=_kIm+rW-tIl?Mr`Rb`H;DKLGj3bQx2)$GbF2~ zkKbGDsn5(=u6QeF|C_4N1twMi+Xvdsza26 zrv$X({=*f|kZsk4rQ3@K6jA$MHnvzhWPZ1Xoecx0ZC*cQYH|0zWOwzwb4s|rhIe0E z)SNk>U_k}h`Ff*x$ianm2k*xW2GoZ_WtrkMx?%rZt64vp4kE)v$izVT)j|%M>pE_Hl~Ol7C~Fp4%q__8G|J z`S0=;i2TD@d*_V_P2U82tXFuxQ~M}$t@4czmn=7S=C3WR!|#5NC0EI`x{_&oS2p!8 z+U(8o&(G*PZDZxM{?H4RdvCAB>k4zc69s&(-UfY7Y@V-g&&=ps)H*w0Y-u`p{2}YR zso6QAe8b0trZkZJ#@d4Rl6^(18`q?Jy|a}$%E85%+lPlT3+Co|eQQQf9-|n%JmqT& znpf?cKC-z_(WZKR@8)r9k>9YXBggffvXSx|t9v~8#iKHp%_|hs`9`3uH{3L6*YB$_{fAW}hlAF+`|0ciaKp`N!H$#73&IW*Ytwi zrNT~l{blW4)qR5!tnAi*l_=NVd5!C)w-;->bH?>8LOV3JblWg~XGvlC{4t8Zbx~IS z)^2MHn(Ox!^~qQ_F3wQSrfpucFMD-H-_XWdPatR0 z`l80!3z1L7_!jS&(CUnJ;~}5XmOmiVGr*BQw@*E)Jk&m7>|p55u>+@Xte6&U2W7MJ z7c}>o&|Iw5JN3~RUTM_KK{*bcmfO3c|MZP(7Uri7Q}kBI$=lVUX-2`E0ilg0S-B(N zA3(n>XI#a2($6l`i>G%P})KYb(UGfSfR6J3tC zICFKz+Ud<@dfWWwK9gGy-M47V*kWhB)Q%Xp0qqp}anf@?QZXKO8gkYb*TWVrU#0{; zvDsVU%#Yfw+LqrBa+JlwQ67|QM6BND?O9m?yLH+Fua9|q;BS;3&T^AKt37-X=_5J$HV^`tgm``_lUqNBkStqp@xZ*+Hh+ZWlCi|Gifqdob*w%=VMLxc?ebzLV@C zN3^%rvVB8)XKX0gShFy{cTR*a_nXFmX`72Nwk@>AwsUuFYpAcSZ!2kT+*aQZUb3yN zzPYJ2H~O)pp{BLf$I>y3O-|=y84Amm5G$;wMY*k}_RyLw;oLdR%?-Ie7F1aGn4f$s z3*%w_yM%56jk2n~u5GK24OCdSXqdwK%Vre0xiwAAO}Pa=mZPv?ht%w-8P`zLv;}jE z9nFV^$5n*ewl>!-sA;Ne2)E{zH#Z;JzRkymLW1O|J~m8Yy1<979Mh59mL0VXhi<7+u7Jm2d zYza426CZ_*FsE)PKTX}xKE~BIHnz9bY-$LPD{HC??+VvdhPQ)ivOCO3eq`g*DZk7( zxv9$PY#9RlcT{M&2|w6{?n0J!5!0;6u2VY|;YLW4Zz}}P5ow{i$b-qpR2G_%P;>&t z+67H-3D?wBhnq-wsLx2T>zdo!;0j=HsP~$tw(1=<4fS=WaA))#YW2=TZ?xTdiu}))1ZmD_9)`m{A__L`yauf`%}?YY?)Sw5pmd)vKCY zP`^qU)w<=Y8u{9a!g`lS`zX_ufi%PPQ5I&;7)t0mNDh4`%@@%hp0cY4j+P>2s>)IGI~df;l}o znP(98oT}pa)$^8=m!b&vv*6Z)p6RE;>axY9b60aAOf(KC;AP-s<}+m!c`l6ky|6m^ z_oA5Ji}>$pl&z4U+ng0;<)zid3+BKWs!-N|30Pe=0mfrLR4*>BDqD%)0jjKCy1a@M zIInm`c@@l#+f#8#$=u3Ht{XJTI2be=2P>4o&^g56L6SJwLRWLi;L%! z&xM2%C}fmCA*BQgIVDg?DuF^)2^7*wppZAJtQEzTi(>UjuvmQ(ELNWci`6H=V)aR| zSbY*KR-XieeBDY*N-C=76fa&>J*TXy65Wyj@N{>PUQ;!*2e<4^OP6oQ9nBO*`1WAO?h2!s$kmd~AEwq&s-Qe|=Jay!kNvS7sJFon-3 ztthUZvtpj*5CY=4vbqcn*03JP;wcY~TUm`J4Oca*fTJqlyAhE6#Lcn3{7ks;pjxr8t&tq0KFJxIG(@ zph9C7Kdx8P`}Hu1IZUY6nYFVD0wyY|EmA3cgfE!-SMCuC9cewS?rg z2tlE#?j{C-P&}$v6S8D+IZA7hRF*6*tuBZDBM8EwS&~#%6<5JiiK1InXTrx`XpGaJ_$zhl`knSt*%;9y`pk%_0sYcm5{|( zUb&(Wo(_Wnq#|}>J(zZ5J#xG0Mo(m?i{}tWOwFSKwx=g>B?d*Jv*1rv4)2?}cuBRe zd5X!2LW-qjCDnx`Yf8%TkUy&zu|o3GTRh)sp3<@En}ZY91U=*d<<&6yK+I*W26(w9E=AQKNdQ~5Wc0o zsja>-Jg%~>rM(vWi!}`;H4P1wn56j>EaLb#H8;1lwzbr3Q`i|!36d;EI0yS+Ti>+B z35g=C+Py8D{70wwCaERhbVJEdx&;(N>E2yef>`9K*|x1=x59E!=*~(9;w&XQi!r4K z)_ykEH`N(RFU3dPdMm773_0z#8d~Pl+4S0Y8U^6EO+QK_Pu4JAhzLV{t9r+Z{(C05#$VW^}n z;Wkn43OmSINv8JWSvs{EV>yO0LKzuQhAX4ccZQo{VhjvPcM>BJz;@doYx8Jmwa8sHxE1DR;n#4%O6T`_1 zb8Fej=lf|2#$e9Ofnd@j6;F>2L1az~OKA!Qx6~^eG1B z?A6UX!YwWJb>TE+X*4|$OnRi^>7i<8Zg@1YrFAeh8XJ!$Hd5JCi=rV}eixl@hSR9< zoMsvfk`e;gQ4|55EdnGZ1gQHc0z6v;NJc)V{g8wz;JR%Td)_{M|9EfN8NpQo;%*5|uZeEdr_a6vkK&J(~oSjL)Gk#(L=4 zB9K~7AxuQ9W1A(zigR^qTTL5OdqT9dglh4U8dhP9VbQZiAT_K)*osph^lTAG&8QGo z5k(L&82U+~57V;=Nui6k|TLez9r4iO`upCls17(rpg2q+m(P!wYX z^lXYmNeMxW5fnv?fRYjdRHw5HMUk4Oq=X=*ri&sqO-TtsOidR>YMPP~f|!~viqteE zB?K`wT@UOik0XS<{r15X98< zgh)+OQbG_@(-R^!O-TtsOifRS)HEd}1Ti%|AyU(nln}(!^n^%FQ&K_@Q_~Y7HBCvi zCAD_Qn$5J{lGMh*kGZ_{08;Mg$m#=Z|!*?oUrnZYZxPe@th(@+xv{!`V$7 z$1Ioa#nJ$g_B~39%h3he^9p<8V{HuRr``H6bEa8Fbm^@5jVXtr{8@RMit`s5v*Up3 zrnXJhZP+*2TGP4}8^a@`l^3T=&o=CPX2udC+tJb4CS_wN?<*gW5FesXiseH4R^Pgm+-878Aevw%wSf)MD4z$9LK&d%uA5 z{krUURFwLA!RiN;I_mc=w3C<_3(7S-9WS)HInwuAY$sI4)3yEl!NImK$ENb-e9 zm8u;5n^PXt23A8HyMEI0?TC|R7NlhhM&N#zS zi5Gl`*ellQi7EoSl+H{bFs8dsfo--D>$HF4s)@86)attc@-N zPIY9| z;fCp>Rx0e^XxLBK>l61Jsc6$hYGDPF<660Ei+i7NL6wLt~FQ_YbKol zdz<)WwZXQF6ncam zM5@7Hhlx~^!S;&OHiI25QY{ACCsJ(&J3{c=VXz}bYL~%|5~)1~J6hoFHP|sCwa;M3 ziqw$?J5HpIHrVkZb*#Zo5UJx0_6w2vg~3h~sgn$Ll1QCmu#-g|ry1-NkvhX*r;5~B z20Klp&N0~OB6Xg@&Jd|z8thDwy3k-}iPXggJ6mwR)L`d`)a3>{SEQ~q*m)v#wZYC8 zscQ}POOd+XU>AtgjRw0=q;59YMIv>p!7di5+YNS!NbNV+r6P5g!7dZ24uf4TWVy#+ zR|wdB2D?(E9x&KdBK45Lt`@0B40er3J!Y_LMd}HIT_;jc8SHwI`jx?M5S*Ve*o^}A ztif&)soxsxW|4ZqV7G|W?+kXUNWE;Z+eGRQ2D@FP{%Ei}MCvtz?H8#x40fkTy=Abw zMC#85J0MbjF<6I4y=$<$Me45xyGKa%fx+$-sgDeHpZN6?gWWGue>d0zBJ~f0Jt$KD zG}uET^@YJ67PMa(>=6O`x4|A2ss9-4F_HS#V2_K`_Xc}{r@YKyPl}YsU{7%_Ue#bv z3z%-OUx`$j!G0}L0fRjwQij2PBPhBV>{*ct8tggoYnH)&D^fiS_Pj{-GS~|u)rYt2 zg$8?({SGbL+s|MxiC+d7>}8P}WU$|hRF1*^AW}mO_KHXiGuR(RYJ|aF6{%4MdrhQ9 z8|-zF8e_0GL~5MD-V~_ zgMBSh^#=QoNF8dhZ$zrmVBd;Vv%$U-sqF^)UZh$L_Jc^Z8wwMtora=_6kc@lh}2<* z;uWdG4Mi2HBMe0osiUybK^+F)ON#Vl{M?#2(yERjU3bW)e%&FP8g_?l>ewB!sbzP_rk*>iXgdEh-d*hx zs!RJNRG0Qks4nf7P+i(Dp}MqRLUn1sglg(l=C{O=SL-~iQ0icrozt2aoqQ4~vfer7 z^lT@Hk@J}XF`;nwSzCc8>vtVTa0QagtHz$p?L@xFQN~W>vrjm7BA+(p>rslbs9pDY|YQ6{jYl@vLDERe=Z%q+pN zWI-S+hIzuake^l-XtK&T(d5aJbdWhNCqGdyd@ZLFA^8DmA*9T8 zT1*}1raLdYb(~sYCXtmlO@7u`pvp#yrUV>SG!++0h;8#SgEJXZtLKVJQt6_<6=W`9PAdjvUX$QilSKcE;Du$kskvW?2=R^_YHJ9ywi*clMamwL|OYWGp6&?o#tyF zG4GUJWK^3(gN_5~on}qP&mFdt#Ci!c+H{iCH6dFTmZUkFhuwvgay;tCqWe2}HCuR= zG062}VMP~2=HL0z;7AWDuVS!sT6IDs(-?RQk()C(37H~UCe%kv7nV@^i0vg5tg~Lu zKIt#2NFBM5CgllpjF_j?SJfY$a_A#K4or6@;Z=^Ojh~PZwU!JSx;=gJS0$LHSTz) zD6u9YuNozmDf$g0ftQ6%cIyn4dBKLkCb7xbaZ>T_3LS>Ce&%Nd3^s*Lr5}eFY??^n z=s|Y}nz&D6P&6dw%*QNj7ENa}h|frcjRLMXXVm$P8dKfkMshUI9vN&Fn@u_98?0F5 zJ=S1z1Z=#)N<^xV4uQFpCz1!(4V9`?aKWKSr%uEz8e<(gadD4^!RE2~Brr}}Bvhwe zxH3_s83tPZ^>tU^@P9D^+uuu_995wLj%TPjiu47N<9uX%8{2WK1sb;F)(9B3onSDZCfAl&E(U+d+eGFrx=%e4GFs@O75mhqaYhI1`Ab(QAhZ;b#eC&VJyty~ zpdOq=IrVL=KJ`4D02406yrIaa z{t`{lbSox|-qTYr^s5)B7vW@(#j@VI%(b<-y`?r>-?X`TTqRGI*EhikE=glPlF}ih z`Nmxt9nOIfT^>*`Rj#INV8)Oet5XR|g={HLgS|gLFRiIyeMN`~>%P z`P3V5#K`vD39z_EZt|-)syCyGsaUl*Ejr23q7o2FZuCNh-KyRe0I%C|1lSTU8qufj zN8Q&oSDWu}E+1J|X3LnkBB<2UZMFcNAlKJ^})jx{f> zq9b3+BIg--YqI%tRS+1%ed_%I^LzyNT6fP8|cNWJutfx~)fMbr@_V$_v&?)GS zcp7mJ+Y8xuQIRhikR^F zAsVa$Loo4AVH+Zq#H-iNysMRDGZ0EqUsGQXsOPG0&;f1aT+;}D@5q#6*)%^@rf;c# z3aHPhIQle=3hq(=LNdT&xeS|XS`76)f$~@A2k&rj8$hh!m?=*qj@W~JFIaAYq0ARG z`8Pu;7pYG{hVcj|L##|P(};W8CdFT#euQw7;Fi)-xx`%icl>pduWfy?oz_Z2E7B$ev_cI{GJ1T8W*#-vGi^KD)~`v~1EbskJVNTm|ZF;W|zY+gz!w zBHLW8un7?pq=BtvUJe#ybg@GoB}-cyfW!w&lrWz9gpH!6HW*5+NNptLK`%miNO%fh zcH#+%I8}}(B|??>4Iw(8Xp;q?zipo4J#4yx)4WQNTtIeI1;7^zmqJbGN|z;WdNY@UAx8tbutR zuhzJZF}|y`490xh%FvG1jtM}PV=*rmvK)^&O~jYNl zT7%`pf#-*ts#4&Mnwk$wr2%U zp=aaXm1t9OTteANZ!dDQ)WbFkrJRq23DH$tkd!w%muf+AajgBu`CyEV`bC;zyz^F@ zw95lb)iCSxV<~zZKZ)qmu0k8irS%4^iFFg}4g43pPGV@+XxFA|S8LZHr8eXJ8VxhF zP=dibpIB-)1=tV`Gc!*ae3j$s-Ny!wjvFvkDdBZks0c&5oftC$+tYol)F0{zuIowWqYF zsmuEn78I-kuc~jsg+SUfw4e|Lj!$S;$lxf&H?d_0oP%?GQTYrM*Ihj&$u}EMifoTxwdarL0~JK*ZOg^!pR%B&-x! zy%B)I-h{$LbGGiLT3%nfm2}|K{sdoY`l;9-xyIl2Yk$`85_ABi7d>eUUe1J7ml@i- z+I!TMV%ij>JFgldUKrzr;aF~vc)-Zz&CBU+SairAXdecU$45cWVnc0LcTl_fTX$Xi zyBA*x@=~B+A}r*u47b$RG}P}AZt-eWm>?pna+R8zuf4?SL=V zEX!?0r;E#{q%YB1nzibTa+or1;k@>yT3YQausA@!-)P@vF-7|hrxW6OkeJ%= zX_zE-!$3cb`<`+eSJrYFdRVXK+1$y+>Wc0O=uGzp)vKK&632Q;ZcSaywl;cWbV`C^ zIFxHI+gZ&`42yMLr@^qE)?L^AsBdSr$w`8GIvEYt5l1D+)ly!hJZP1Aw=87S9fq4k zOOXr5bA5WI!Ys`=#*7h_I*_R;>DhigOYcDw=bEND?HEtY!$tTBc4YAKIZVA4qvr_f zbVKi@_YQzbAB+qe=>oZOOMpmG;s+g4Ub58#y|3PnsuG8>>K9(Ig?_z2FVYW!)zN===ZyC~I#yY{+nRS` z(mS%WbX2LKPt~UdfQmK83=G#Xv@0y-5v}KxI%`CLQQ<03~*EPuBvAE|L_*Nxu93{T9OGz z<_q+)fIeTxMW()OxOA|sfhGvD1_*CZu2+zti^;srFSlXJk5;l29>wl}3B*;l+^;Xw zD}UDB7I|Tr{4RY(09mbctgxaRE~8!w`MV)-rdl0d5^0f3Q$89OQU{*7DkCd)ClD#9s!CGir%bm!@7*V zJ!&a~ie;NjSCvE?1bQnr?DRG?6B<@hrDL??*l;0eX?Sx@djkyz^&R?748!$ZSbnpr z$cf?8_e8B*MUUB{pSmiwU2LHrbW3{!`eFLv&ILc(7cGj^=@I%E@^wd|0*`|GvX|!~ z21mWyFl+AL;Jlinxm6{`z&(~bF+tMqlh{+fBe5kIpT*; z4dr~1`iwSFumF9bc>KapE)l7(4CQi>`nRE6B~t$}lxs!mTSK`)q`o(ln|aEIQP4V` zo6m#8CtMbvYACmfUv)#-FH&iSazLa4hH{TcLA3its+*xaBvL^`c~qpZjq`*^^)QsD zMG9~7ZxFfl!Lb&RTVF$YM*NEL>`=RBN;b6$M|KJMik18*N~ zl>7&>N8dQVZ>(=T+K=*b04Xfj)d>AfFq9VrTP({(Hkqi;nHUjfiV$WhgqfDbvZxf% zxRWBdGX?G};Lgrs*@WvUm|!h{BjG8)lAu@)N5WHpjKvcYo&pS_#S;>qf+^M$5}tyo z))NvQx&V}8Qo=(QeTpX}Jakp3ctXNM_i&0QBs_G zbZet{B3bB4M)5?l(0z;IiDaS66vY$CLN_JyCrWte8bt9#vd|re;)!IT3k<~*$wIdi ziYJnVt{xOmBn#auD4viAv^QB3iUjk6GQ)SQ?>NjQe8(H=lj>8{QgHeyOVaPDpNOAN zHqQqDXYATVOZfFAp>`X%&EK+A1+GLFmQTWa^w5b9Q{quT}y1>xt#jh6`+93jV ziJ_gVoktXx8QMi6b%mi_DpFS&+GQezLqgfPb>UWX$tf%rmU8jcFXt4gay=fH*z|&jzj`%yQ}O{gw6nZuR1( zre@sSi}f%d2GM_td-nxTfVx*A$C|RH2FOAS*O(`82*hVO%)?X$E624qS#(Gj6ZGk=^^6m(_VZl)jzg*T z^8!5M;Hmw*5YIS%8ug4rsP;4Ehoh)mP8>vyg5x+UhvP6Rk8u>0$2f?}V;n<`!pC7$ z`*6u4>f$jj>f$jj=;AT1=i)Ig=i)K0=HhXy8Mm1+ zF6H9z9p*DGGUJQQ_!2X|)QoX~7RSf+Sv1=`_1?PGk(yFA2MTH zfW`4~{S}XK`4x{JGvmk2_z5$9(u{HC6~}wpe8zQG{27;B@fcTK@fa6f@fg=!@fep} z@fcTJ@fa6e@fg=z@fg=y@%Sb4`DHW4g;pH?2Q$WHR{R-PS@9SbS@HNaGk)ES-!S7h z&G;=d#^qHUA6HlL7#COZ_%CMsjv2pe#_yRiuB+mB@0&5Ms^ZVMsEWt9ri#b7q>9J5 zqKe13po+)1o{Gn~oQlV|nu^D`n2N`^mWs!poADQBj0>qa{3|oYWmNnbS5fg87g6!} zKW6-m8GmcW-VZ}-4yO5ibrcB1J$=yh6iju~H z5DMpNe^#LeMhP|D7HUQ^p>VR+tx&VOqN$uHp$@WzDo!R8j`X?}sx)<>=GsEdOC}Uf zr@9rYtSdqdjndRYTc}0Jgu+2tw?cJEQ_(_I*g`E%CKQgyx)o|!S2UFyrK#n%P?gDq z!ckVYLUl<~!=i**VGFe~nNT=E`?Cr)JW8n5woq%5355fbKdVp^ql7xx7HVBGp>SgJ zzbMoOTd3+}LT&t+g_<0tsTy0TP0579Imw?@Q_(`z*+PYr359cAZiU*~6_?N}N>lZ= zP=_QF3P;S`3f0&Zp?XIN)np6RoJ=U3c5^FKOIL*I6D3ruEmT`Fp>VX#tx#QZo}nnA zcGyDgOePd|Cfo|Orz@H&i4y8CTd2Lsgu*7t&ni@Dlu-L@p^iu<)R8~4P;;Y%I?5L6 z=ww1+cgU@#x-_1O7V21AsN<3eg^en=Lj9sEHWe+@iMCKDB@+sJW^RS*lA+Iws=iZf zp-xRE6!ym43e_c-upmmP(`}*7NG23E=YCe9%A$li%NFYFWI|zM@MjgOJW8l@ZK2Lf zCKUE4e^#L?qJ;XTEz||cgu+g#TcNtt_eBeJkuB84$%MkDty`hGG((OS>QY;%%aRFo zxqG3yN;Df>yrtE z4Su&mb!mNSX_TgJw1v7UnNT=u@Lv?_7F(!WlL>_*4sM0&l1)`cY3g=cs5_Dgh0_*4 zt58)@LfvT#byqT>aPY&eP+cFLgDDte^IDk*+Ts~nNT>fe*yM;hdFQp}Mpb zR2?PMZ*8HTPbL&jX}J}uOG`l;ql9|V7V3A2g;JE4l$TAR=3=LbzlM|7FaI9pHQJx@ zIJTpFHg|ec=XK=`{7xy_kfiM@pYjJB1@Q3gD8C2bAOJzU3HGM)mYKsiAQGyUcaQRp zoWCIu1b=Z%L-`Y!ysNxtGMR?WFWUan^G4sJd?e@6OJLYi>dIdsn__L1{guo0v7F`K zQ(*b2oaH}LVEMW7g<0@O{ftKa{724{whN={=SwO%hkfO&pD$5AUvWKrBhSHuFIBm- zfN$*_zH{dAEpqsda_}fpwRlu{2Jw~0Gq5TTY{61XAhci3GhQv+AV@79-6=Fo0|3e) z;7P~+EN$;D!v?H|*q=9OKuEpElP%9954*rXvW?E~$-o{ysowADhDJga0mSQ68;ywUk%?(y_bmT{V$ahj)>StDtl-c&f^;OWCw zp**x%j0}4rv)=gY!!sNpub&)wc5(IN8A#c2)|!F`D#H-ZP*Z#BOzj1z45Yr%a<&t= zjstcn0-j-JDFQqLDn-CE957O3z%v3VOOd%e^Gp>aK@tFHK_HMI`SP-jlMCUhY~wuz z^7@%5XDSTCSwB|E((IC@iIQ3M<0uC#Xp_W)-sPDr&n9#0}r&nRYV( z@oqkf3A8xfL#NA#xCHW$O$YPt^2~ag`SR}e%%LO+BaSn8nUWsYZwQ7#vvw6viKkS; zaGqdT28Q!~B*TTCMW(?yI*0?F$#+Q07gx_XK4G6<^OT#m%+FLPo(j)mv%Vv&`yKF1 zbI%$*WE4wwsI)Scx~dG;ASGVzj<``uT;-0q$+JRYL#x~oZ)jEzN{Or85w}T+YupjHOSN6=j(CSO=de5Cozk4QxFg;r&AHwk@op*cq3($HNQoQW z5g#TcZgxk!S4zCy9r58(;#POW`=rF}?ud_&*7Htx#79brce^7#N=kf~JL03IWj@>; z@i9{3Bis=mDayQsNWb5&uF;e4;zz6Q#r_yCXhHN_?t2 z;*+HocDg&_Q>4Uax+6YSN_@6E;?tzW=ei?4T}phuJK{5>#22_DK2u73kvrnEq{NrF zBR*SdB$v4(K1WJ?g*)PNrNmdcBR)?`e2qKe^QFYsxg-9il=udB#1}}3Z*oU`p_KR* zcf=P-iEnd9e6f`H4tKitrQsRf*5nnAOe$*ZDHB#co-4S0aC4SN!@pV$-r`-`>FD3r9JK`IpM)DhX#5YQF ze$E~7O;Y0L-4Wj`C4SKz@hwu~m)sHGDkc8CJL21<#ILv`zFkWEsypI4q{OegBi=71 ze$yTCol@dIxg)+yO8mAv;sa9Rcia(oNQvKbM|`)G_^{=psb6Eb42;*R)9DY4fb@l&#@@@npgpO)tAb4QFXM#L|gdj0N*aS^_R zINcpF?$ehLXSgH&jZ|UX-4Q=4CC+q5jJx~ahF?^0ryTgabEiC4NS z^FO4-tKAWQCM90$j`*Ka;&twbKbI13a7X-wlz5{%;xDDdo7@q9B_*zNNBl1-@n(0# z|CSPObw~WQl=u*L#Q%{JH@GAIMoQe|j`&+C@iuqF-${vE+!22-C2n&^{DYKuhbv-S zOD7ww?{Y`1NQw8jBlbv%_qrqYN{RQmBUYuvN4g`{q{K(NBK965KgYDR>*tuf$I4kQ zPl4rea+Xyousq&-g6sg-D)%g#F*$SGv!i%_A(wKEdzP_h!n`NSSst7M%ai0R*Qdbp zWI4;~6j+`jXIYa1%TwhwUhAG^T#cV5mon_0Wn7J)E|+qPdzNuho*|dA-aX4WDbJL% zJTwKCXUSPMroi%SIm_l0Se_$ixjhAz=gL{Oroi$%Im`AGSe`Gp%bo67#@XdBHOV0oLI<#j2ryj{-nh7?%dA!m703M}`_S>BQY%RA*PZ%cvYU2>Lpq`>lkoaLP< zutQqJiWEob?93M`+IvwSlJ zmcNm+{8I`npOv$GI|Y`{$yvUW0?XgZS-zJ7%je}R-%o+%3v%c7p?j8b&h14x%a2oF z`8#>R|K^@$oWFcY&hpa~SiUT0`B@4qe=leGc?vB5AZPhy3M^ld*Z9BOvy3yMKgy;2 z+C9s-8h=&J@|zS`z9wh+T?#B;m$UpK1(t6}S$dTeSiUJ|=}m#Q(*a-oMm1LEdMEInV$m7&*dz~ zroi$GIm_`Wu>4ZavM>dfU&&ccNP*?Q@lXa9C3H$yu&UL6>QAma9`>>6f!yn*z&#oaMR{ zSf)2d^|6fc)B{=T#^}QUJH!3*40t5#QoyM7B^t4BS1Dw&66-06U#(= zDV9nScgypTq>{{$N>UIjiTGY^B1uZ5Op0Qei0{iLVp1w)GAWjc_#Ui` z34JVjo;q2g*lDp$Mkdq=Ue01=QpL`UWs;YW$#gJTBxN!?mdWU(OvuSmJ}F7FHuAJ|vcSeLQin7=wsI57P*1;(`4^ArP|tq&5%t_h)boSGz5CUR?^iEfldWDB91twL zTfMSFz4j6HdVu$8VK0Sj( zeJb^iTKtuy7N2=UeTGnMwLhC!?ZEr3TBkZRpA%e`MDzRAm-=<6f9OzOjUuT{O!8(F z;z5ZK--ayj$mH3bnC4x%Jelm|#5B6u#Po-o}y(8vB z_B5B<&!A{i5r!6TKhFT!@dXhv@+aHr4cqyE+l~s``H4s?TERWWjmkQ zw)0Qhc0RXl=L`3?^QC1wN(M{g&gu*_&VTj0SN+z*gopXwesHw$+~9&FO$sc`4oG7O z%rA=9swBK_NAJ9Vtzv8KW;ud+eqd{(n`Nwgl1kq%TFZ1z;o6(e`fDDpJ;u(k zS{YLER;GD1j3(&IL7r#O{h-HHKH9JOoyt1jQKn(Rxe3dpWjOTHU7{cApz}JkOsx)K zwptg(cU?lh>fJ&hiF+L$?46iQ?p}unM%tq%r44%}hE$;ol4iAqyr%3_wL^&^L% zOkp`%f72m+WSP10Q6e)RU^xV~3l4#X&!wp6LADQY8vHX39p(i~6Y5ZXJ9g+UR$0Wy zt4b}QSZN}m2HQeiVG7llP$*}`j!xpGw4n~^M+fKq26{}o51HWsV^nRbk}iAvy1qw(!@SXi;_E&U6q(8 zT$N;q4S{b+OyeBV0`ttom~TfFZGI9&6wUPGPT3~~dnKlU3s0i+Nx>P3Nu3UQQgB#e zMBcwdsdG|rePZ-?rP`e2cF;K~Sdo}_lrA&bory8ucW8Z5uqh#;wt)JRA~uK3ML+Th z`wq(w))aOX^(Xj1sx>>6O<_f6a+izF#LIggdn}a22Y3^eN7*FLyKJJj8=GX$X6K?4 zDdU|;Av%$Tyc5CKHnm06iLj5*iIj^@#5=|EJ4huMD^)1gw_Yn4N&>$V+OJjSK|kt) z>bYyYqbncLR&;1yxTo`=rUi&U_MltlTF}cI}fUyZ1>oE`1U*|It1PG%kG-FkSkj$-y7*lcsd)lM?ED zid&yF<;VG?DL>vPO>yg!rnvP<(7H>XH0A%VPnry$GzC6sGJMjMD4(>+_DQw2PpY$h zQrNvu+T3-YBqTC@lD5V6Nn0I03E-f%mHVXnA2aHj+1aS;5X-}Pmat6nrJn5lTJwIb z4c=6LP}{M_yI$>9Rbcq(HN^kJFaq#YUg%> zGq;1>=5|ofMQ+rRd2X6Kw_>-s74xNI`NFn#Qmo2~lPo@IPL&l0Cni?eNeCn>G! z99a}6TQ4vx;S{XNa50XWk1#hRbJCrZenYZ_ zMOo=LMCy{=Vwe7wM5VvfF8$HiQJ}h9Y?oeMmm7mC5-T9OG?L2M=n!wQE#Bfp;$3Eo zx8JOseYSX#%Bcy?Oe~wca%zH05|eaVoEk@Q_SwbRCoK+B)FzL)>p1CmEDPTjX9Lc{ zaF@2x?$)l%yGOeoe>dh~D{u(50<~K@v^ySAk2#&fKcI zH!@?lTzjuzHcIB)h-;+1J@7a%#^#YOR@oAB>CM*!BV5GdVWZfv1FyS7nuD1h(ruB> zSDnqcPjGl*J<~iFgfUx5eS)JClQ^fjeUkW3Z7+CZZ}AU2((dcf9_r8@#RK}PSeV@_ z_6hb(m@{7%JfIH6LJa2nKAaRIl|CNwIn6zdoRjA>HgfppKKG4~a!D zkfM!_t%4lb4^M<%fteboVV8ggAn`pmmeuYt%B%Dg1TtA`J$GaZzNL{W}TGQJ?n*-%)g zmN6#i*shOQ#+YFLILj!OReqDOiw^A+l#Z`fdd*!S=Mw9<;E;q3N^gPPS$Z57%!=fz zx5GQW)S>SdcCFcF4XC+1Y0(t~a~yR0FxWYumYC(o@Q|7X2Od03Q%L1!DVn?_-9 zP=ui-n#NqPm=jR~L*xii?~6UrlOxDwcXRBNYA`iKSyDY=;z(1U&h$I z`c<^GhGNW@(q5m47MG((Xv<(ccc2m68LzQv!G4hf>UZ(17MbWB@#xbf=oQflmiV0+ za_gEQv92Xh?oqMIy+5jywsL1iS&3Y^k2p!mD=o8(Nq@XUhlh7!fs!VP#^5biSliq-iS~MHl5^kK99m?hc{4td65THk>M?`=a`k>gSE!fJSY%J!xlyqoI3b~I*bcWn z0Yv%GArcS5T#G3Pcl);+>7!zM@^I^nRMxYcgS28 zC-ZcysY7I0RinJlOcn;GCR7v81lwnjNi5DMW=SeUZxUI&x2krbb3&rOC;U$+6yjR^ zM=0dbV&72TSS@M}b(9CkB$QO__C>AoI&Gmmi6+Sw?3PoWY%U2KhB5XFVXXz8{-2?K z4%z#M`bT7UW?hkFZCd}_vUDifIajC%j!#%r{d0%B6~Vp<5mn*u280H1dA|$|aL79_ zG|(Y$blyq!yXAAXir}KeQaI;q70DWcbC0Y%xH&OLluMf)Epj*^cGTirMH0tos%uba z5Lef~LW3OY8XOud)D_c_S0vkrft*pph{ZuYv6x~QkrT?{xqltXapXQEG(?*F;w1Br zs3pXTWXIspIc=~zr=g*tT!3#vLmdL-hH@R&;;_FZ!GeTEN@(3nf@MjFqPQn<;baB8 zmxyUQOM-Ptxbr4FEHsQ4^1IM5MJqcOzt|WdLV@dFc#3arpu_U-P zF`{!Bcu6qvph|VNoh6y<#Dpxhy<7t$LL;~aeh7_lXkcV$WJCkO==0c1lZ=7M`@%Dh z3XLMBJ|#5D!89*~ALVDumj?3_3L52>m+(=#d{}EP&1{4@9Ayt0e5gKaY?IgFb9N)k zlIT&}>*!UNIVW=%3GgzG4)GN^pDz?yl1rbKABrr>naA^-Syp!1bI}mPKBwaBJ}TYz zT$P>oTw_9fCD7*&IhO**hQ>zf$C-6ir#+V`wX>;Ix$U{CI`6s0g~oAvN)L^5*wgsX zc!#{vdH?91tIBQ9Rpqwls_eAqiq^5qo~x?!o~s~Kz}1xzDsZT)FjOei71MK7{g|F> zMdv+NQK*RL-aS<0$bCX+f;9IPZhNk(PI|6QcF#32G?5FC8Jg%2U{Yw3!&)4D%gRoB zE{S!oblY>SOlB^;=aO>owC9=}n#>EC9h&SY8TO^awCrsrDKdCxUHG@Uc;9h&Z7IwLg0!8Gcvs8w!z zu9cnlTy&C~Z=&-#rY{uLb2&HCS0~Y9RL`|Krsv|zf#{%ThGz0&4hYS36mwQ+R-~Bd z(}dP0eE}>YtTo|V%U6A^xx83n+$@$DWpDQ!oTS50-;HN~u!Q|qIDtxj^5Gq{ zaBCBT?^F1OIadVDJ#oi`mX1rr6Xi*W9CO

LGkEFgrAx>oY$z+o8{cLI>IUyq7P| zXqPw@TAgHvD{8h}6GawR5IVD<`nH;!rWy(Bx3DLql^ybDSDVRCO~Xwa{tR6-$U5Rc8si zF?xsd4!p9Lha)>PaN4qo9nOwKd@p;3J%>~Mk0>uHFROceFZtf}y|3;`%TJq`b`avD z(#}ddSKZ^!_s{g>*?+kIH2;~1zYlZ|WT|`7$EO#kmmr;4UP_uMSM~4=HPAWp3EaN&&)hW-IH~6*4bHj zkumF)tPiq2R`+DzpZ#n$`1RP?;}<KA(Q``A>FSC}bqL~@d%f4|19eaD z6}>n2u2=W;nbv1fAH0;r*3#SvT{0#=Y z_wYSSi=lE-%6=0Po&19yU;zoKlRVMyTmbXMi>1s+z{SZa8IIs~E>}W1>z0I@lVfLi zRx#O?EZ7N4CtEkTqW*C7SDY4Jz_MIq;LOA=eoRKYSPz#OIWzk)G!DyBMzLN$A~$D_ zKb8(hsqgjauWK-U(f#t2|8l9FCI4UK?d(#l{(aj2 zKnG4e{IBwl8z;>8A1T7AjQ^z!PU8^cjknmW|DjHtdih_=!QF;_E6w$l`Rt(ou~sb2 z@D(^E#OC}zkjE(#U2vsL!tE#w%Ya$9pJN#7#p-dz)orYgaxV*c=CFRAvsi!6tt`j$ zdp5-LCL8KiS*~|98|GckMtED;Nbd(MPaVQWtLxYp^=38}_kE1h2C@Qe9V^ssVMW^e zY@+r7o2X~AN%~;KL)m0K7k^9G6n!1yYBo(jjZN1dWHWpLHq%!MV?GqBx{Q^i<*?GU zJ#4Q33pOwC37eljh%HFJk(C)6*h1q!tit$)m1o?|D!TV#<=tl^exEH4hFL}MOtvIz zFI$>Dj4jEoV#~7cVpZ7(SY?mxtg7b=tg`3Vtg6=)Y(?)utg81SwlXw{tqT2#t?b*4 zt?t{z*7p639o%mzTi@?QwxQp{h#zCs{oiF92b8j!0ecXi$@mS1p3CvR&z4S zy${$zzyiJ(0b2x^KkXpE$^kRd@&Ky7p8+z;4#!1{GN3a|};4eWL(VAX&P=zcq38vz^K z{X)QM02>q>3mCmBJS5l$FnU!uCwLoR^r~=f@B+Z-RpFtT=K!`Du;H2e0NVoCuq<5K z=i3U{$Shpi=c@;7MApZE9RgTh*6#s36tGd*RE`F~^0TQNjew2raWY^{fQ{|Z4p=i_ zV|q>pY#U(XdkzC^J7D8_9RgSjV1>P^0BZ%Tpw|b0wE;Gv*Y5yp2dt=fJzzTko7B4! zu$_QS?1Q^}e7gXf(g%0>_;v#}IkXh8J%C|P6tKepn;N?puy_opTLqXC=K{{z5|0StRA1I`jxTn0nB&e!*G z`xToB8>P1i{duGB@!=rQiP3LqGLU!RXYrP%-+pt>ukP}lWZ&SR?quf8hx)*ToKK16 zEbc&a&3R}-&Zot47Wad><~&j#g{2djHqMCUEUsyC&3S!7na_&l?7TzCg`PJjO1dvGalR}ASVCsgb&V|j^trClrb>V%vx zjO8pYop#On?nK4EIF_;VU4LouA4n+VrLnxk?a*$8^bPb4N?@^<$8vVQW!-u0`-Ugv zd}S&UZbW9C?Opvn}}Y?xXLb z5?_W+{vL#zn1TPh;Tl0du5`%8-J^c^%WMpp{49jHFXH})2Ou7VcraqTTZ#WNSuPvS zMgVIRh5&iUA|LS>#N${2D^&e#0^*6x@4FY+9t;HTL!6G^)9~kS#drWOUMbhIo=PTD zlz{dhT>JBh_9_1Up?#)(j^{L8(*wGpXYl9Gbi;(@NMOSyuzY>2O*_`4-6+AUkAXoB zy)j0Pqb0mfi-Y}AzevB>&huh3&+8<3H%ajBi^J3OhvQ+sA--HI4_~gx!#7F-n=XMJ zh*e~ezblXN^zZjlYXE6F!CDZo9;Wv_W)e!?Qp3N(Cw3o zj&4WMa36@G!%-+I?(S4{baIM@dm9vL;);el4-{&W3f&N`Xt;V#(Qpf#qQglm8g3?0 zboeVp!|ecy4-HJw@FKqALxWIM+#{<{cdTf*Z%@(DVJLLJlA^>qoAFB-9f3H zl-fn9-4yJh;4ljIQgAp0`zSbq@Q$S5C<=}y*fA6wOTlpz98bXs6#RmM6Dc@}f|H5j z6beqI;4}(Or{D|<&ZOWh3eG0vb0|2Mg7YXipMqafZ~+AuQm{#Ri?NF+buk5(P;e;) zmr-yzvATj%S5j~l1y@sW4F%Uya2*BLQ*Z+z-$<#OD7cw|TPWC1!L1bBM#1eA+(E&e z6x>C@0SY=OxSN7|h}FFm+((c1Q}6%<4^r?D1rO7&k5KAS3Lc~2aSEQG;7JOeB9x~o z^(zW~O~Er1{DyvbmV)Q#@wXH_Pr(Zmyy)%A*h`dpnS$R_@COQBq2P}cyh_1q6ueHs z8x*`r!CMskiGn{<@HPd1q2L_~-lgC@3jRvL`xJaY!G{!lM8U@td_uwBDEK=CpHlD- z3O=LYpA>vf!50*KNx@eX{0o8dCROOa>G5j{{zJhx6nsm;cNBb2!4C)&Mu9?shXOAJ zDg_z>7N&qcfx_tPG>m`W=2PW8rhJaeh?I9J^)UiQUj$+FSqT357e-&BVf6VG{^b)! z7x6Q?%Ae7#`iwrYgWyo+S?F2BJQetekM|e~j-}u@3XaDIpuNAK)QJ?FM8U}voI=5= z^y_JqI-OEyQ0hzy&Z6LK3eKV6Tnf&k;C#aSB?T8ya3R4iqTpf*E}`I33NEAIatf}X z;7SUvB8saixQ2pjDY%Y;>nXT_f*UEgiI8um;1&vQrQkLSZl~Z53ieZQCk1y=aDaji z3ht)h9^!H@rS7BPehMC-;6Vx=qTpc)9--h-LVk==k5ljj1y54&38-%{{A1uqb*7b*B1J-$T2%M|>cfKblW~i6G z@`($O5zv=3Rr>a&N?)r~>HCuWi;(;qj{K{ODt#wWr7s(*^esX)odSb`3<|nYKwrUA z>AQ6*eQ8e3q9B`s9u)MXpce)7RWg;nBc{@qzf}5Gm)ehl{uB&Az`tg~=&K}*zI(*K z(Zj!R!{}=*jK2H9==&XvzQe)jdm8-XDU3cvf?K8W$iJndD?X;IrC>b;8!4!zU^4}W zQm~DJb_#Y;a5x3iC^(XWV<F^ehLmya1RCdQ!s~uhbVZIf+r|=nu2F2c#eV>D40({IR#57sG?vM1utQ>$fLpg zc&2-1DD<%m#Z%%bRp=WQif4#tDD#Z>6fn;KxFt_MIjC<4S)s=so}SDT@T4>T^&UoF b;bHU qu$b`VLp(-MF&Xw8`IjD}XWue7gY%^Ck-b delta 118 zcmZ22w_0w)H5Nwm&DU8Z*%*^2f8??Sk`uVaC%bWbf?0uJQPIiYxz(X86CMqyni3u> qu$b`VLp(-MF&