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Updated Makefile to run LEC

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komaljaved-lm 2021-03-29 18:34:16 +05:00
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commit a90fe1c613
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README.md
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# Quasar RISC-V Core 1.0 from Lampro Mellon
This repository contains the SweRV-EL2 Core written in CHISEL named "Quasar".
## License
By contributing to this project, you agree that your contribution is governed by [Apache-2.0](LICENSE).
Files under the [tools](tools/) directory may be available under a different license. Please review individual file for details.
## Background
Quasar is a Chiselified version of EL2 SweRV RISC-V Core.
## Directory Structure
├── configs # Configurations dir
├── design
│ ├── project
│ ├── project
│ └── target
│ ├── snapshots
│ └── default # Where generated configuration files are created
│ ├── src
│ ├── main
│ ├── resources
│ └── vsrc # Blackbox files dir
│ └── scala # Design root dir
│ ├── dbg # Debugger
│ ├── dec # Decode, Registers and Exceptions
│ ├── dmi # DMI block
│ ├── exu # EXU (ALU/MUL/DIV)
│ ├── ifu # Fetch & Branch Prediction
│ ├── include # Bundles file
│ ├── lib # Bridges and Library
│ └── lsu # Load/Store
│ └── test
│ ├── target
│ └── test_run_dir
├── doc # PPA Report
├── generated_rtl # Quasar wrapper
├── testbench
│ ├── asm # Example assembly files
│ └── hex # Canned demo hex files
├── tools # Scripts/Makefiles
├── tracer_logs # generated log files
└── verif
├── LEC
└── sim # Simulation log/dump files
## Dependencies
- Verilator **(4.030 or later)** must be installed on the system if running with verilator.
- Vcs must be installed on the system if running with vcs.
- RISCV tool chain (based on gcc version 7.3 or higher) must be
installed so that it can be used to prepare RISCV binaries to run.
- Sbt **(1.3.13 or later)** must be installed on the system.
## Quickstart guide
1. Clone the repository
2. Setup RV_ROOT to point to the path in your local filesystem
3. Determine your configuration {optional}
4. Run make with $RV_ROOT/tools/Makefile
## Release Notes for this version
Please see [release notes](release-notes.md) for changes and bug fixes in this version of Quasar.
### Configurations
Quasar can be configured by running the script:
```
$RV_ROOT/configs/quasar.config
```
For detailed help options.
```
$RV_ROOT/configs/quasar.config -h
```
For example, to build with a DCCM of size 64Kb:
```
$RV_ROOT/configs/quasar.config -dccm_size=64
```
This will update the **default** snapshot in `$RV_ROOT/design/snapshots/default/` with parameters for a 64K DCCM.
Add `-snapshot=dccm64`, for example, if you wish to name your build snapshot *dccm64* and refer to it during the build.
There are 4 predefined target configurations: `default`, `default_ahb`, `typical_pd` and `high_perf` that can be selected via the `-target=name` option to quasar.config.
This script derives the following consistent set of include files :
```
$RV_ROOT/design/snapshots/default
├── common_defines.vh # `defines for testbench or design
├── defines.h # defines for C/assembly headers
├── param.vh # Design parameters
├── pdef.vh # Parameter structure
├── pd_defines.vh # `defines for physical design
├── perl_configs.pl # Perl %configs hash for scripting
├── pic_map_auto.h # PIC memory map based on configure size
└── whisper.json # JSON file for swerv-iss
```
#### 1. Generate scala parameter
```
make -f $RV_ROOT/tools/Makefile conf
```
This script will run `quasar.config` and derives the include file:
```
$RV_ROOT/design/src/main/scala/lib
└── param.scala # Scala design parameters
```
### Running RTL Simulation
while in a work directory:
#### 1. Set the RV_ROOT environment variable to the root of the Quasar directory structure.
Example for bash shell:
```
export RV_ROOT=$(pwd)
```
Example for csh or its derivatives:
```
setenv RV_ROOT /path/to/QUASAR
```
#### 2. Create your specific configuration
*(Skip if default is sufficient)*
*(Name your snapshot to distinguish it from the default. Without an explicit name, it will update/override the __default__ snapshot)*. For example, if `mybuild` is the name for the snapshot:
set BUILD_PATH environment variable:
```
setenv BUILD_PATH snapshots/mybuild
$RV_ROOT/configs/quasar.config [configuration options..] -snapshot=mybuild
```
Snapshots are placed in `$BUILD_PATH` directory.
#### 3. Run sbt
```
make -f $RV_ROOT/tools/Makefile sbt
```
This command will generate the Quasar wrapper in system verilog in the `generated_rtl` directory and runs the `reset_script.py`
* In the reset_script we do a post verilog-generation changes, these changes are as follows:
* Replace `posedge reset` with `negedge reset`
* Replace `if (reset)` with `if (~reset)`
#### 4. Running a simple Hello World program (verilator)
```
make -f $RV_ROOT/tools/Makefile
```
This command will build a verilator model of Quasar with AXI bus, and execute a short sequence of instructions that writes out "HELLO WORLD"
to the bus.
The simulation produces output on the screen like:
```
VerilatorTB: Start of sim
----------------------------------
Hello World from Quasar @LM !!
----------------------------------
TEST_PASSED
Finished : minstret = 437, mcycle = 922
See "exec.log" for execution trace with register updates..
```
The simulation generates following files in `$RV_ROOT/verif/sim`:
`console.log` contains what the cpu writes to the console address of 0xd0580000.
`exec.log` shows instruction trace with GPR updates.
`trace_port.csv` contains a log of the trace port.
Other log files are `dec.log`, `exu.log`, `ifu.log`, `lsu.log` and `pic.log`, generates in `$RV_ROOT/tracer_logs`.
When `debug=1` is provided, a vcd file `sim.vcd` is created and can be browsed by gtkwave or similar waveform viewers.
You can re-execute simulation using:
```
make -f $RV_ROOT/tools/Makefile verilator
```
The simulation run/build command has following generic form:
```
make -f $RV_ROOT/tools/Makefile [<simulator>] [debug=1] [snapshot=mybuild] [target=<target>] [TEST=<test>] [TEST_DIR=<path_to_test_dir>]
```
where:
```
<simulator> - can be 'verilator' (by default) , 'vcs' - Synopsys VCS. if not provided, 'make' cleans work directory, builds verilator executable and runs a test.
debug=1 - allows VCD generation for verilator and VCS and SHM waves for irun option.
<target> - predefined CPU configurations 'default' ( by default), 'default_ahb', 'typical_pd', 'high_perf'.
TEST - allows to run a C (<test>.c) or assembly (<test>.s) test, hello_world is run by default.
TEST_DIR - alternative to test source directory testbench/asm or testbench/tests.
<snapshot> - run and build executable model of custom CPU configuration, remember to provide 'snapshot' argument for runs on custom configurations.
CONF_PARAMS - allows to provide -set options to quasar.conf script to alter predefined targets parameters.
```
#### Default for VCS/Verilotor
If you want to run default configuration on verilator use the following command
```
make -f $RV_ROOT/tools/Makefile
```
For VCS use
```
make -f $RV_ROOT/tools/Makefile vcs_all
```
Example:
```
make -f $RV_ROOT/tools/Makefile verilator TEST=cmark
```
will build and simulate `testbench/asm/cmark.c` program with verilator.
If you want to compile a test only, you can run:
```
make -f $RV_ROOT/tools/Makefile program.hex TEST=<test> [TEST_DIR=/path/to/dir]
```
The Makefile uses `snapshot/<target>/link.ld` file, generated by quasar.conf script by default to build test executable. User can provide test specific linker file in form `<test_name>.ld` to build the test executable, in the same directory with the test source.
User also can create a test specific makefile in form `<test_name>.makefile`, containing building instructions how to create `program.hex` file used by simulation. The private makefile should be in the same directory as the test source. See examples in `testbench/asm` directory.
*(`program.hex` file is loaded to instruction and LSU bus memory slaves and optionally to DCCM/ICCM at the beginning of simulation)*.
User can build `program.hex` file by any other means and then run simulation with following command:
make -f $RV_ROOT/tools/Makefile <simulator>
Note: You may need to delete `program.hex` file from work directory, when run a new test.
The `$RV_ROOT/testbench/asm` directory contains following tests ready to simulate:
```
hello_world - default tes to run, prints Hello World message to screen and console.log
hello_world_dccm - the same as above, but takes the string from preloaded DCCM.
hello_world_iccm - the same as hello_world, but loads the test code to ICCM via LSU to DMA bridge and then executes
it from there. Runs on QUASAR with AXI4 buses only.
cmark - coremark benchmark running with code and data in external memories
cmark_dccm - the same as above, running data and stack from DCCM (faster)
cmark_iccm - the same as above with preloaded code to ICCM.
```
The `$RV_ROOT/testbench/hex` directory contains precompiled hex files of the tests, ready for simulation in case RISCV SW tools are not installed.
**Note**: The testbench has a simple synthesizable bridge that allows you to load the ICCM via load/store instructions. This is only supported for AXI4 builds.

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# Quasar RISC-V Core 1.0 from Lampro Mellon
## Release Notes
~~~
Initial release DATE
~~~

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[debug] Full compilation, no sources in previous analysis. [debug] Full compilation, no sources in previous analysis.

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[debug] Copy resource mappings: [debug] Copy resource mappings: 
[debug] [debug]  

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design/reset_script.py
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delete_list8 = ["posedge io_dbg_rst_l"] delete_list8 = ["posedge io_dbg_rst_l"]
delete_list9 = ["if (rst_not)"] delete_list9 = ["if (rst_not)"]
delete_list10 = ["posedge rst_not"] delete_list10 = ["posedge rst_not"]
#delete_list11 = ["TEST_RNM"] delete_list11 = ["rvclkhdr"]
fin = open(infile) fin = open(infile)
fout = open(outfile, "w+") fout = open(outfile, "w+")
@ -50,6 +50,9 @@ for line in fin:
for word in delete_list10: for word in delete_list10:
line = line.replace(word, "negedge rst_not") line = line.replace(word, "negedge rst_not")
for word in delete_list11:
line = line.replace(word, "rvclkhdr_ch")
fout.write(line) fout.write(line)
fin.close() fin.close()
fout.close() fout.close()

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[debug] Checking for meta build source updates

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873143994

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[debug] "not up to date. inChanged = true, force = false
[debug] Updating ...
[info] Updating 
[info] Resolved dependencies
[debug] Done updating 

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["DMA","QUASAR","QUASAR_Wrp","dbg.debug","dec.dec_dec","dec.dec_main","dec.tlu","exu.div_main","exu.exu_main","exu.mul","ifu.ifu_top","lib.axi4_to_ahb","lsu.buffer","lsu.bus_intf","lsu.clkdomain","lsu.dccm_ctl","lsu.lsc_ctl","lsu.lsu_main","lsu.stbuf","pic"]

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["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",[]]

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[warn] /home/users/scratch/komal.javed.data/Quasar/quasar2/design/src/main/scala/lib/lib.scala:25:5: match may not be exhaustive.
[warn] It would fail on the following inputs: (0, _), (1, _), (??, _), (_, 0), (_, 1), (_, ??), (_, _)
[warn]  (ICACHE_WAYPACK, ICACHE_ECC) match{
[warn]  ^
[warn] /home/users/scratch/komal.javed.data/Quasar/quasar2/design/src/main/scala/quasar.scala:326:8: Generated class QUASAR differs only in case from quasar.
[warn]  Such classes will overwrite one another on case-insensitive filesystems.
[warn] object QUASAR extends App {
[warn]  ^
[warn] there were 5450 feature warnings; re-run with -feature for details
[warn] three warnings found

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[debug] No changes

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[debug] Copy resource mappings:
[debug] (/home/users/scratch/komal.javed.data/Quasar/quasar2/design/src/main/resources/vsrc/dpram64.v,/home/users/scratch/komal.javed.data/Quasar/quasar2/design/target/scala-2.12/classes/vsrc/dpram64.v)
[debug] (/home/users/scratch/komal.javed.data/Quasar/quasar2/design/src/main/resources/vsrc/wb_mem_wrapper.v,/home/users/scratch/komal.javed.data/Quasar/quasar2/design/target/scala-2.12/classes/vsrc/wb_mem_wrapper.v)
[debug] (/home/users/scratch/komal.javed.data/Quasar/quasar2/design/src/main/resources/vsrc/uart_sync_flops.v,/home/users/scratch/komal.javed.data/Quasar/quasar2/design/target/scala-2.12/classes/vsrc/uart_sync_flops.v)
[debug] (/home/users/scratch/komal.javed.data/Quasar/quasar2/design/src/main/resources/vsrc/uart_wb.v,/home/users/scratch/komal.javed.data/Quasar/quasar2/design/target/scala-2.12/classes/vsrc/uart_wb.v)
[debug] (/home/users/scratch/komal.javed.data/Quasar/quasar2/design/src/main/resources/vsrc/mem_lib.sv,/home/users/scratch/komal.javed.data/Quasar/quasar2/design/target/scala-2.12/classes/vsrc/mem_lib.sv)
[debug] (/home/users/scratch/komal.javed.data/Quasar/quasar2/design/src/main/resources/vsrc/uart_transmitter.v,/home/users/scratch/komal.javed.data/Quasar/quasar2/design/target/scala-2.12/classes/vsrc/uart_transmitter.v)
[debug] (/home/users/scratch/komal.javed.data/Quasar/quasar2/design/src/main/resources/vsrc/fifo4.v,/home/users/scratch/komal.javed.data/Quasar/quasar2/design/target/scala-2.12/classes/vsrc/fifo4.v)
[debug] (/home/users/scratch/komal.javed.data/Quasar/quasar2/design/src/main/resources/vsrc/raminfr.v,/home/users/scratch/komal.javed.data/Quasar/quasar2/design/target/scala-2.12/classes/vsrc/raminfr.v)
[debug] (/home/users/scratch/komal.javed.data/Quasar/quasar2/design/src/main/resources/vsrc/dmi_wrapper.sv,/home/users/scratch/komal.javed.data/Quasar/quasar2/design/target/scala-2.12/classes/vsrc/dmi_wrapper.sv)
[debug] (/home/users/scratch/komal.javed.data/Quasar/quasar2/design/src/main/resources/vsrc/uart_regs.v,/home/users/scratch/komal.javed.data/Quasar/quasar2/design/target/scala-2.12/classes/vsrc/uart_regs.v)
[debug] (/home/users/scratch/komal.javed.data/Quasar/quasar2/design/src/main/resources/vsrc/uart_receiver.v,/home/users/scratch/komal.javed.data/Quasar/quasar2/design/target/scala-2.12/classes/vsrc/uart_receiver.v)
[debug] (/home/users/scratch/komal.javed.data/Quasar/quasar2/design/src/main/resources/vsrc/uart_defines.v,/home/users/scratch/komal.javed.data/Quasar/quasar2/design/target/scala-2.12/classes/vsrc/uart_defines.v)
[debug] (/home/users/scratch/komal.javed.data/Quasar/quasar2/design/src/main/resources/vsrc/uart_rfifo.v,/home/users/scratch/komal.javed.data/Quasar/quasar2/design/target/scala-2.12/classes/vsrc/uart_rfifo.v)
[debug] (/home/users/scratch/komal.javed.data/Quasar/quasar2/design/src/main/resources/vsrc/lsu_dccm_mem.sv,/home/users/scratch/komal.javed.data/Quasar/quasar2/design/target/scala-2.12/classes/vsrc/lsu_dccm_mem.sv)
[debug] (/home/users/scratch/komal.javed.data/Quasar/quasar2/design/src/main/resources/vsrc/mem.sv,/home/users/scratch/komal.javed.data/Quasar/quasar2/design/target/scala-2.12/classes/vsrc/mem.sv)
[debug] (/home/users/scratch/komal.javed.data/Quasar/quasar2/design/src/main/resources/vsrc/axi2wb.v,/home/users/scratch/komal.javed.data/Quasar/quasar2/design/target/scala-2.12/classes/vsrc/axi2wb.v)
[debug] (/home/users/scratch/komal.javed.data/Quasar/quasar2/design/src/main/resources/vsrc/ifu_iccm_mem.sv,/home/users/scratch/komal.javed.data/Quasar/quasar2/design/target/scala-2.12/classes/vsrc/ifu_iccm_mem.sv)
[debug] (/home/users/scratch/komal.javed.data/Quasar/quasar2/design/src/main/resources/vsrc/dmi_jtag_to_core_sync.sv,/home/users/scratch/komal.javed.data/Quasar/quasar2/design/target/scala-2.12/classes/vsrc/dmi_jtag_to_core_sync.sv)
[debug] (/home/users/scratch/komal.javed.data/Quasar/quasar2/design/src/main/resources/vsrc/gated_latch.sv,/home/users/scratch/komal.javed.data/Quasar/quasar2/design/target/scala-2.12/classes/vsrc/gated_latch.sv)
[debug] (/home/users/scratch/komal.javed.data/Quasar/quasar2/design/src/main/resources/vsrc/ifu_ic_mem.sv,/home/users/scratch/komal.javed.data/Quasar/quasar2/design/target/scala-2.12/classes/vsrc/ifu_ic_mem.sv)
[debug] (/home/users/scratch/komal.javed.data/Quasar/quasar2/design/src/main/resources/vsrc/simple_spi_top.v,/home/users/scratch/komal.javed.data/Quasar/quasar2/design/target/scala-2.12/classes/vsrc/simple_spi_top.v)
[debug] (/home/users/scratch/komal.javed.data/Quasar/quasar2/design/src/main/resources/vsrc/mem_mod.sv,/home/users/scratch/komal.javed.data/Quasar/quasar2/design/target/scala-2.12/classes/vsrc/mem_mod.sv)
[debug] (/home/users/scratch/komal.javed.data/Quasar/quasar2/design/src/main/resources/vsrc/rvjtag_tap.sv,/home/users/scratch/komal.javed.data/Quasar/quasar2/design/target/scala-2.12/classes/vsrc/rvjtag_tap.sv)
[debug] (/home/users/scratch/komal.javed.data/Quasar/quasar2/design/src/main/resources/vsrc/parameter.sv,/home/users/scratch/komal.javed.data/Quasar/quasar2/design/target/scala-2.12/classes/vsrc/parameter.sv)
[debug] (/home/users/scratch/komal.javed.data/Quasar/quasar2/design/src/main/resources/vsrc/uart_tfifo.v,/home/users/scratch/komal.javed.data/Quasar/quasar2/design/target/scala-2.12/classes/vsrc/uart_tfifo.v)
[debug] (/home/users/scratch/komal.javed.data/Quasar/quasar2/design/src/main/resources/vsrc/uart_top.v,/home/users/scratch/komal.javed.data/Quasar/quasar2/design/target/scala-2.12/classes/vsrc/uart_top.v)
[debug] (/home/users/scratch/komal.javed.data/Quasar/quasar2/design/src/main/resources/vsrc/swervolf_syscon.v,/home/users/scratch/komal.javed.data/Quasar/quasar2/design/target/scala-2.12/classes/vsrc/swervolf_syscon.v)
[debug] (/home/users/scratch/komal.javed.data/Quasar/quasar2/design/src/main/resources/vsrc/beh_lib.sv,/home/users/scratch/komal.javed.data/Quasar/quasar2/design/target/scala-2.12/classes/vsrc/beh_lib.sv)

1
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/home/users/komal.javed/.sbt/boot/scala-2.12.10/lib/scala-library.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar:/home/users/komal.javed/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar

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design/target/streams/compile/exportedProductJars/_global/streams/export
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/home/users/scratch/komal.javed.data/Quasar/quasar2/design/target/scala-2.12/quasar_2.12-3.3.0.jar

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/home/users/scratch/komal.javed.data/Quasar/quasar2/design/target/scala-2.12/classes

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/home/users/komal.javed/.sbt/boot/scala-2.12.10/lib/scala-library.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar:/home/users/komal.javed/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar

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design/target/streams/compile/internalDependencyClasspath/_global/streams/export
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design/target/streams/compile/mainClass/_global/streams/out
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[warn] Multiple main classes detected. Run 'show discoveredMainClasses' to see the list

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design/target/streams/compile/managedClasspath/_global/streams/export
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[debug] Jar uptodate: /home/users/scratch/komal.javed.data/Quasar/quasar2/design/target/scala-2.12/quasar_2.12-3.3.0.jar

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/home/users/scratch/komal.javed.data/Quasar/quasar2/design/target/scala-2.12/quasar_2.12-3.3.0.jar:/home/users/komal.javed/.sbt/boot/scala-2.12.10/lib/scala-library.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar:/home/users/komal.javed/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar

1
design/target/streams/runtime/internalDependencyAsJars/_global/streams/export
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/home/users/scratch/komal.javed.data/Quasar/quasar2/design/target/scala-2.12/quasar_2.12-3.3.0.jar

1
design/target/streams/runtime/managedClasspath/_global/streams/export
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/home/users/komal.javed/.sbt/boot/scala-2.12.10/lib/scala-library.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar:/home/users/komal.javed/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar:/home/users/komal.javed/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar

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design/target/streams/runtime/unmanagedClasspath/_global/streams/export
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design/target/streams/runtime/unmanagedJars/_global/streams/export
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1428156
test.vcd
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2
testbench/asm/hello_world.s
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@ -66,6 +66,6 @@ _finish:
.data .data
hw_data: hw_data:
.ascii "----------------------------------\n" .ascii "----------------------------------\n"
.ascii "Hello World from SweRV EL2 @WDC !!\n" .ascii " Hello World from QUASAR @LMDC !! \n"
.ascii "----------------------------------\n" .ascii "----------------------------------\n"
.byte 0 .byte 0

2
testbench/asm/hello_world_iccm.s
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@ -64,7 +64,7 @@ _finish:
.data .data
hw_data: hw_data:
.ascii "----------------------------------------\n" .ascii "----------------------------------------\n"
.ascii "Hello World from SweRV EL2 ICCM @WDC !!\n" .ascii " Hello World from QUASAR ICCM @LMDC !! \n"
.ascii "----------------------------------------\n" .ascii "----------------------------------------\n"
.byte 0 .byte 0

2
testbench/tests/hello_world/hello_world.s
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@ -37,6 +37,6 @@ loop:
.data .data
hw_data: hw_data:
.ascii "----------------------------------\n" .ascii "----------------------------------\n"
.ascii "Hello World from SweRV EL2 @WDC !!\n" .ascii "Hello World from QUASAR 2.0 @LMDC !!\n"
.ascii "----------------------------------\n" .ascii "----------------------------------\n"
.byte 0 .byte 0

101
tools/Makefile
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@ -31,7 +31,6 @@ snapshot = $(target)
QUASAR_CONFIG = ${RV_ROOT}/configs/quasar.config QUASAR_CONFIG = ${RV_ROOT}/configs/quasar.config
VCS = vcs VCS = vcs
VERILATOR = verilator VERILATOR = verilator
RIVIERA = riviera
GCC_PREFIX = /home/users/cores/chipyard/riscv-tools-install/bin/riscv64-unknown-elf GCC_PREFIX = /home/users/cores/chipyard/riscv-tools-install/bin/riscv64-unknown-elf
BUILD_DIR = ${RV_ROOT}/design/snapshots/${snapshot} BUILD_DIR = ${RV_ROOT}/design/snapshots/${snapshot}
TBDIR = ${RV_ROOT}/testbench TBDIR = ${RV_ROOT}/testbench
@ -53,6 +52,7 @@ else
endif endif
endif endif
endif endif
HEX_DIR = ${TBDIR}/hex HEX_DIR = ${TBDIR}/hex
# provide specific link file # provide specific link file
@ -62,14 +62,13 @@ else
LINK = $(TEST_DIR)/$(TEST).ld LINK = $(TEST_DIR)/$(TEST).ld
endif endif
OFILES_PATH = ${RV_ROOT}/verif/sim
OFILES = $(TEST).o OFILES = $(TEST).o
OFILES_PATH = ${RV_ROOT}/verif/sim
ifdef debug ifdef debug
DEBUG_PLUS = +dumpon DEBUG_PLUS = +dumpon
VCS_DEBUG = -debug_access VCS_DEBUG = -debug_access
VERILATOR_DEBUG = --trace VERILATOR_DEBUG = --trace
RIVIERA_DEBUG = +access +r
endif endif
VPATH = $(TEST_DIR) $(BUILD_DIR) $(TBDIR) VPATH = $(TEST_DIR) $(BUILD_DIR) $(TBDIR)
@ -91,14 +90,14 @@ CFLAGS += "-std=c++11"
# compiles), or -O for balance. # compiles), or -O for balance.
VERILATOR_MAKE_FLAGS = OPT_FAST="-Os" VERILATOR_MAKE_FLAGS = OPT_FAST="-Os"
#############Targets####################################### #############Targets#######################################
all: clean conf sbt_ verilator all: clean sbt_ verilator
vcs_all: clean conf sbt_ vcs vcs_all: clean sbt_ vcs
############ Model Builds ############################### ############ Model Builds ###############################
conf: conf:
BUILD_PATH=${BUILD_DIR} ${RV_ROOT}/configs/quasar.config -target=$(target) $(CONF_PARAMS) BUILD_PATH=${BUILD_DIR} ${RV_ROOT}/configs/quasar.config -target=$(target) $(CONF_PARAMS)
sbt_: sbt_: conf
cd ${RV_ROOT}/design/ && exec sbt "run" cd ${RV_ROOT}/design/ && exec sbt "run"
python3 ${RV_ROOT}/design/reset_script.py python3 ${RV_ROOT}/design/reset_script.py
rm -rf ${RV_ROOT}/design/quasar_wrapper.v rm -rf ${RV_ROOT}/design/quasar_wrapper.v
@ -118,45 +117,45 @@ vcs-build: ${TBFILES} conf
+error+500 -debug_access +lint=TFIPC-L \ +error+500 -debug_access +lint=TFIPC-L \
${BUILD_DIR}/common_defines.vh \ ${BUILD_DIR}/common_defines.vh \
+incdir+$(BUILD_DIR) +libext+.v $(defines) \ +incdir+$(BUILD_DIR) +libext+.v $(defines) \
-f ${RV_ROOT}/testbench/flist ${TBFILES} -l ${RV_ROOT}/verif/sim/vcs.log -f ${RV_ROOT}/testbench/flist ${TBFILES} -l $(OFILES_PATH)/vcs.log
riviera-build: ${TBFILES} ${BUILD_DIR}/defines.h
vlib work
vlog -work work \
-err VCP2694 W1 \
+incdir+${RV_ROOT}/design/lib \
+incdir+${RV_ROOT}/design/include \
+incdir+${BUILD_DIR} \
-y ${RV_ROOT}/design/lib +libext+.v+.vh \
$(defines) \
-f ${RV_ROOT}/testbench/flist \
${TBFILES}
touch riviera-build
############ TEST Simulation ############################### ############ TEST Simulation ###############################
vcs: program.hex vcs-build vcs: program.hex vcs-build
./simv $(DEBUG_PLUS) +vcs+lic+wait -l ${RV_ROOT}/verif/sim/vcs.log ./simv $(DEBUG_PLUS) +vcs+lic+wait -l $(OFILES_PATH)/vcs.log
rm -rf program.hex data.hex @rm -rf program.hex $(addprefix $(OFILES_PATH)/,csrc simv* vc_hdrs.h ucli.key console.log *.csv)
mv csrc simv* vc_hdrs.h ucli.key console.log *.csv ${RV_ROOT}/verif/sim @mv csrc simv* vc_hdrs.h ucli.key console.log *.csv $(OFILES_PATH)
mv *.log ${RV_ROOT}/tracer_logs @mv *.log ${RV_ROOT}/tracer_logs
ifeq ($(shell which fm_shell 2> /dev/null),)
lec: lec:
rm -rf ${RV_ROOT}/verif/LEC/LEC_RTL $(error Unable to locate the executable file for formality! Exiting!)
git clone https://github.com/Lampro-Mellon/LEC_RTL.git else
mv LEC_RTL ${RV_ROOT}/verif/LEC lec:
python3 ${RV_ROOT}/verif/LEC/config.py
fm_shell -f ${RV_ROOT}/verif/LEC/formality_work/run_me.fms fm_shell -f ${RV_ROOT}/verif/LEC/formality_work/run_me.fms
@mv *.log ${RV_ROOT}/verif/LEC/formality_work/formality_log @mv *.log ${RV_ROOT}/verif/LEC/formality_work/formality_log
endif
verilator: program.hex verilator-build verilator: program.hex verilator-build
./obj_dir/Vtb_top ./obj_dir/Vtb_top
rm -rf program.hex data.hex @rm -rf program.hex $(addprefix $(OFILES_PATH)/,csrc simv* vc_hdrs.h ucli.key console.log *.csv)
mv console.log *.csv obj_dir ${RV_ROOT}/verif/sim @mv console.log *.csv obj_dir $(OFILES_PATH)
mv *.log ${RV_ROOT}/tracer_logs @mv *.log ${RV_ROOT}/tracer_logs
############ TEST build ############################### ############ TEST build ###############################
ifeq ($(shell which $(GCC_PREFIX)-gcc 2> /dev/null),)
program.hex: ${BUILD_DIR}/defines.h
@echo " !!! No $(GCC_PREFIX)-gcc in path, using canned hex files !!"
cp ${HEX_DIR}/$(TEST).hex program.hex
else
ifneq (,$(wildcard $(TEST_DIR)/$(TEST).makefile))
program.hex:
@echo Building $(TEST) via $(TEST_DIR)/$(TEST).makefile
$(MAKE) -f $(TEST_DIR)/$(TEST).makefile
else
program.hex: $(OFILES) $(LINK) program.hex: $(OFILES) $(LINK)
@echo Building $(TEST) @echo Building $(TEST)
$(GCC_PREFIX)-gcc -Wl,-m,elf32lriscv -Wl,--discard-none -T$(LINK) -o $(OFILES_PATH)/$(TEST).exe \ $(GCC_PREFIX)-gcc -Wl,-m,elf32lriscv -Wl,--discard-none -T$(LINK) -o $(OFILES_PATH)/$(TEST).exe \
@ -165,6 +164,8 @@ program.hex: $(OFILES) $(LINK)
$(GCC_PREFIX)-objcopy -O verilog $(OFILES_PATH)/$(TEST).exe program.hex $(GCC_PREFIX)-objcopy -O verilog $(OFILES_PATH)/$(TEST).exe program.hex
$(GCC_PREFIX)-objdump -S $(OFILES_PATH)/$(TEST).exe > $(OFILES_PATH)/$(TEST).dis $(GCC_PREFIX)-objdump -S $(OFILES_PATH)/$(TEST).exe > $(OFILES_PATH)/$(TEST).dis
@echo Completed building $(TEST) @echo Completed building $(TEST)
endif
endif
%.o : %.s conf %.o : %.s conf
$(GCC_PREFIX)-cpp -I${BUILD_DIR} $< > $(OFILES_PATH)/$*.cpp.s $(GCC_PREFIX)-cpp -I${BUILD_DIR} $< > $(OFILES_PATH)/$*.cpp.s
@ -185,25 +186,27 @@ clean:
rm -rf ${RV_ROOT}/design/*.json rm -rf ${RV_ROOT}/design/*.json
rm -rf ${RV_ROOT}/design/*.fir rm -rf ${RV_ROOT}/design/*.fir
rm -rf ${RV_ROOT}/generated_rtl/*.sv rm -rf ${RV_ROOT}/generated_rtl/*.sv
rm -rf ${RV_ROOT}/verif/sim/*.log rm -rf $(OFILES_PATH)/*.log
rm -rf ${RV_ROOT}/verif/sim/*.s rm -rf $(OFILES_PATH)/*.s
rm -rf ${RV_ROOT}/verif/sim/*.hex rm -rf $(OFILES_PATH)/*.hex
rm -rf ${RV_ROOT}/verif/sim/*.dis rm -rf $(OFILES_PATH)/*.dis
rm -rf ${RV_ROOT}/verif/sim/*.tbl rm -rf $(OFILES_PATH)/*.tbl
rm -rf ${RV_ROOT}/verif/sim/vcs* rm -rf $(OFILES_PATH)/vcs*
rm -rf ${RV_ROOT}/verif/sim/simv* rm -rf $(OFILES_PATH)/simv*
rm -rf ${RV_ROOT}/design/src/main/scala/lib/param.scala rm -rf ${RV_ROOT}/design/src/main/scala/lib/param.scala
rm -rf ${RV_ROOT}/design/snapshots rm -rf ${RV_ROOT}/design/snapshots
rm -rf ${RV_ROOT}/verif/sim/quasar* rm -rf $(OFILES_PATH)/quasar*
rm -rf ${RV_ROOT}/verif/sim/*.exe rm -rf $(OFILES_PATH)/*.exe
rm -rf ${RV_ROOT}/verif/sim/obj* rm -rf $(OFILES_PATH)/obj*
rm -rf ${RV_ROOT}/verif/sim/*.o rm -rf $(OFILES_PATH)/*.o
rm -rf ${RV_ROOT}/verif/sim/ucli.key rm -rf $(OFILES_PATH)/ucli.key
rm -rf ${RV_ROOT}/verif/sim/vc_hdrs.h rm -rf $(OFILES_PATH)/vc_hdrs.h
rm -rf ${RV_ROOT}/verif/sim/csrc rm -rf $(OFILES_PATH)/csrc
rm -rf ${RV_ROOT}/verif/sim/*.csv rm -rf $(OFILES_PATH)/*.csv
rm -rf ${RV_ROOT}/verif/sim/work rm -rf $(OFILES_PATH)/work
rm -rf ${RV_ROOT}/verif/sim/*.dump rm -rf $(OFILES_PATH)/*.dump
rm -rf ${RV_ROOT}/verif/sim/*.fsdb rm -rf $(OFILES_PATH)/*.fsdb
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rm -rf ${RV_ROOT}/tracer_logs/*.log
rm -rf *.log *.lck *.s *.hex *.dis *.tbl vcs* simv* quasar* *.exe obj* *.o ucli.key vc_hdrs.h csrc *.csv work *.dump *.fsdb

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write enable, write addr , write data ,read enable, read address, read data

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// SPDX-License-Identifier: Apache-2.0
// Copyright 2020 Western Digital Corporation or its affiliates.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
// all flops call the rvdff flop
`define RV_FPGA_OPTIMIZE 1
`define RV_PHYSICAL 1
module rvdff #( parameter WIDTH=1, SHORT=0 )
(
input logic [WIDTH-1:0] din,
input logic clk,
input logic rst_l,
output logic [WIDTH-1:0] dout
);
if (SHORT == 1) begin
assign dout = din;
end
else begin
`ifdef RV_CLOCKGATE
always @(posedge tb_top.clk) begin
#0 $strobe("CG: %0t %m din %x dout %x clk %b width %d",$time,din,dout,clk,WIDTH);
end
`endif
always_ff @(posedge clk or negedge rst_l) begin
if (rst_l == 0)
dout[WIDTH-1:0] <= 0;
else
dout[WIDTH-1:0] <= din[WIDTH-1:0];
end
end
endmodule
// rvdff with 2:1 input mux to flop din iff sel==1
module rvdffs #( parameter WIDTH=1, SHORT=0 )
(
input logic [WIDTH-1:0] din,
input logic en,
input logic clk,
input logic rst_l,
output logic [WIDTH-1:0] dout
);
if (SHORT == 1) begin : genblock
assign dout = din;
end
else begin : genblock
rvdff #(WIDTH) dffs (.din((en) ? din[WIDTH-1:0] : dout[WIDTH-1:0]), .*);
end
endmodule
// rvdff with en and clear
module rvdffsc #( parameter WIDTH=1, SHORT=0 )
(
input logic [WIDTH-1:0] din,
input logic en,
input logic clear,
input logic clk,
input logic rst_l,
output logic [WIDTH-1:0] dout
);
logic [WIDTH-1:0] din_new;
if (SHORT == 1) begin
assign dout = din;
end
else begin
assign din_new = {WIDTH{~clear}} & (en ? din[WIDTH-1:0] : dout[WIDTH-1:0]);
rvdff #(WIDTH) dffsc (.din(din_new[WIDTH-1:0]), .*);
end
endmodule
// _fpga versions
module rvdff_fpga #( parameter WIDTH=1, SHORT=0 )
(
input logic [WIDTH-1:0] din,
input logic clk,
input logic clken,
input logic rawclk,
input logic rst_l,
output logic [WIDTH-1:0] dout
);
if (SHORT == 1) begin
assign dout = din;
end
else begin
`ifdef RV_FPGA_OPTIMIZE
rvdffs #(WIDTH) dffs (.clk(rawclk), .en(clken), .*);
`else
rvdff #(WIDTH) dff (.*);
`endif
end
endmodule
// rvdff with 2:1 input mux to flop din iff sel==1
module rvdffs_fpga #( parameter WIDTH=1, SHORT=0 )
(
input logic [WIDTH-1:0] din,
input logic en,
input logic clk,
input logic clken,
input logic rawclk,
input logic rst_l,
output logic [WIDTH-1:0] dout
);
if (SHORT == 1) begin : genblock
assign dout = din;
end
else begin : genblock
`ifdef RV_FPGA_OPTIMIZE
rvdffs #(WIDTH) dffs (.clk(rawclk), .en(clken & en), .*);
`else
rvdffs #(WIDTH) dffs (.*);
`endif
end
endmodule
// rvdff with en and clear
module rvdffsc_fpga #( parameter WIDTH=1, SHORT=0 )
(
input logic [WIDTH-1:0] din,
input logic en,
input logic clear,
input logic clk,
input logic clken,
input logic rawclk,
input logic rst_l,
output logic [WIDTH-1:0] dout
);
logic [WIDTH-1:0] din_new;
if (SHORT == 1) begin
assign dout = din;
end
else begin
`ifdef RV_FPGA_OPTIMIZE
rvdffs #(WIDTH) dffs (.clk(rawclk), .din(din[WIDTH-1:0] & {WIDTH{~clear}}),.en((en | clear) & clken), .*);
`else
rvdffsc #(WIDTH) dffsc (.*);
`endif
end
endmodule
module rvdffe #( parameter WIDTH=1, SHORT=0, OVERRIDE=0 )
(
input logic [WIDTH-1:0] din,
input logic en,
input logic clk,
input logic rst_l,
input logic scan_mode,
output logic [WIDTH-1:0] dout
);
logic l1clk;
if (SHORT == 1) begin : genblock
if (1) begin : genblock
assign dout = din;
end
end
else begin : genblock
`ifndef RV_PHYSICAL
if (WIDTH >= 8 || OVERRIDE==1) begin: genblock
`endif
`ifdef RV_FPGA_OPTIMIZE
rvdffs #(WIDTH) dff ( .* );
`else
rvclkhdr clkhdr ( .* );
rvdff #(WIDTH) dff (.*, .clk(l1clk));
`endif
`ifndef RV_PHYSICAL
end
else
$error("%m: rvdffe must be WIDTH >= 8");
`endif
end // else: !if(SHORT == 1)
endmodule // rvdffe
module rvdffpcie #( parameter WIDTH=31 )
(
input logic [WIDTH-1:0] din,
input logic clk,
input logic rst_l,
input logic en,
input logic scan_mode,
output logic [WIDTH-1:0] dout
);
`ifndef RV_PHYSICAL
if (WIDTH == 31) begin: genblock
`endif
`ifdef RV_FPGA_OPTIMIZE
rvdffs #(WIDTH) dff ( .* );
`else
rvdfflie #(.WIDTH(WIDTH), .LEFT(19)) dff (.*);
`endif
`ifndef RV_PHYSICAL
end
else
$error("%m: rvdffpcie width must be 31");
`endif
endmodule
// format: { LEFT, EXTRA }
// LEFT # of bits will be done with rvdffie, all else EXTRA with rvdffe
module rvdfflie #( parameter WIDTH=16, LEFT=8 )
(
input logic [WIDTH-1:0] din,
input logic clk,
input logic rst_l,
input logic en,
input logic scan_mode,
output logic [WIDTH-1:0] dout
);
localparam EXTRA = WIDTH-LEFT;
localparam LMSB = WIDTH-1;
localparam LLSB = LMSB-LEFT+1;
localparam XMSB = LLSB-1;
localparam XLSB = LLSB-EXTRA;
`ifndef RV_PHYSICAL
if (WIDTH >= 16 && LEFT >= 8 && EXTRA >= 8) begin: genblock
`endif
`ifdef RV_FPGA_OPTIMIZE
rvdffs #(WIDTH) dff ( .* );
`else
rvdffiee #(LEFT) dff_left (.*, .din(din[LMSB:LLSB]), .dout(dout[LMSB:LLSB]));
rvdffe #(EXTRA) dff_extra (.*, .din(din[XMSB:XLSB]), .dout(dout[XMSB:XLSB]));
`endif
`ifndef RV_PHYSICAL
end
else
$error("%m: rvdfflie musb be WIDTH >= 16 && LEFT >= 8 && EXTRA >= 8");
`endif
endmodule
// special power flop for predict packet
// format: { LEFT, RIGHT==31 }
// LEFT # of bits will be done with rvdffe; RIGHT is enabled by LEFT[LSB] & en
module rvdffppe #( parameter WIDTH=32 )
(
input logic [WIDTH-1:0] din,
input logic clk,
input logic rst_l,
input logic en,
input logic scan_mode,
output logic [WIDTH-1:0] dout
);
localparam RIGHT = 31;
localparam LEFT = WIDTH - RIGHT;
localparam LMSB = WIDTH-1;
localparam LLSB = LMSB-LEFT+1;
localparam RMSB = LLSB-1;
localparam RLSB = LLSB-RIGHT;
`ifndef RV_PHYSICAL
if (WIDTH>=32 && LEFT>=8 && RIGHT>=8) begin: genblock
`endif
`ifdef RV_FPGA_OPTIMIZE
rvdffs #(WIDTH) dff ( .* );
`else
rvdffe #(LEFT) dff_left (.*, .din(din[LMSB:LLSB]), .dout(dout[LMSB:LLSB]));
rvdffe #(RIGHT) dff_right (.*, .din(din[RMSB:RLSB]), .dout(dout[RMSB:RLSB]), .en(en & din[LLSB])); // qualify with pret
`endif
`ifndef RV_PHYSICAL
end
else
$error("%m: must be WIDTH>=32 && LEFT>=8 && RIGHT>=8");
`endif
endmodule
module rvdffie #( parameter WIDTH=1, OVERRIDE=0 )
(
input logic [WIDTH-1:0] din,
input logic clk,
input logic rst_l,
input logic scan_mode,
output logic [WIDTH-1:0] dout
);
logic l1clk;
logic en;
`ifndef RV_PHYSICAL
if (WIDTH >= 8 || OVERRIDE==1) begin: genblock
`endif
assign en = |(din ^ dout);
`ifdef RV_FPGA_OPTIMIZE
rvdffs #(WIDTH) dff ( .* );
`else
rvclkhdr clkhdr ( .* );
rvdff #(WIDTH) dff (.*, .clk(l1clk));
`endif
`ifndef RV_PHYSICAL
end
else
$error("%m: rvdffie must be WIDTH >= 8");
`endif
endmodule
// ie flop but it has an .en input
module rvdffiee #( parameter WIDTH=1, OVERRIDE=0 )
(
input logic [WIDTH-1:0] din,
input logic clk,
input logic rst_l,
input logic scan_mode,
input logic en,
output logic [WIDTH-1:0] dout
);
logic l1clk;
logic final_en;
`ifndef RV_PHYSICAL
if (WIDTH >= 8 || OVERRIDE==1) begin: genblock
`endif
assign final_en = (|(din ^ dout)) & en;
`ifdef RV_FPGA_OPTIMIZE
rvdffs #(WIDTH) dff ( .*, .en(final_en) );
`else
rvdffe #(WIDTH) dff (.*, .en(final_en));
`endif
`ifndef RV_PHYSICAL
end
else
$error("%m: rvdffie width must be >= 8");
`endif
endmodule
module rvsyncss #(parameter WIDTH = 251)
(
input logic clk,
input logic rst_l,
input logic [WIDTH-1:0] din,
output logic [WIDTH-1:0] dout
);
logic [WIDTH-1:0] din_ff1;
rvdff #(WIDTH) sync_ff1 (.*, .din (din[WIDTH-1:0]), .dout(din_ff1[WIDTH-1:0]));
rvdff #(WIDTH) sync_ff2 (.*, .din (din_ff1[WIDTH-1:0]), .dout(dout[WIDTH-1:0]));
endmodule // rvsyncss
module rvsyncss_fpga #(parameter WIDTH = 251)
(
input logic gw_clk,
input logic rawclk,
input logic clken,
input logic rst_l,
input logic [WIDTH-1:0] din,
output logic [WIDTH-1:0] dout
);
logic [WIDTH-1:0] din_ff1;
rvdff_fpga #(WIDTH) sync_ff1 (.*, .clk(gw_clk), .rawclk(rawclk), .clken(clken), .din (din[WIDTH-1:0]), .dout(din_ff1[WIDTH-1:0]));
rvdff_fpga #(WIDTH) sync_ff2 (.*, .clk(gw_clk), .rawclk(rawclk), .clken(clken), .din (din_ff1[WIDTH-1:0]), .dout(dout[WIDTH-1:0]));
endmodule // rvsyncss
module rvlsadder
(
input logic [31:0] rs1,
input logic [11:0] offset,
output logic [31:0] dout
);
logic cout;
logic sign;
logic [31:12] rs1_inc;
logic [31:12] rs1_dec;
assign {cout,dout[11:0]} = {1'b0,rs1[11:0]} + {1'b0,offset[11:0]};
assign rs1_inc[31:12] = rs1[31:12] + 1;
assign rs1_dec[31:12] = rs1[31:12] - 1;
assign sign = offset[11];
assign dout[31:12] = ({20{ sign ^~ cout}} & rs1[31:12]) |
({20{ ~sign & cout}} & rs1_inc[31:12]) |
({20{ sign & ~cout}} & rs1_dec[31:12]);
endmodule // rvlsadder
// assume we only maintain pc[31:1] in the pipe
module rvbradder
(
input [31:1] pc,
input [12:1] offset,
output [31:1] dout
);
logic cout;
logic sign;
logic [31:13] pc_inc;
logic [31:13] pc_dec;
assign {cout,dout[12:1]} = {1'b0,pc[12:1]} + {1'b0,offset[12:1]};
assign pc_inc[31:13] = pc[31:13] + 1;
assign pc_dec[31:13] = pc[31:13] - 1;
assign sign = offset[12];
assign dout[31:13] = ({19{ sign ^~ cout}} & pc[31:13]) |
({19{ ~sign & cout}} & pc_inc[31:13]) |
({19{ sign & ~cout}} & pc_dec[31:13]);
endmodule // rvbradder
// 2s complement circuit
module rvtwoscomp #( parameter WIDTH=32 )
(
input logic [WIDTH-1:0] din,
output logic [WIDTH-1:0] dout
);
logic [WIDTH-1:1] dout_temp; // holding for all other bits except for the lsb. LSB is always din
genvar i;
for ( i = 1; i < WIDTH; i++ ) begin : flip_after_first_one
assign dout_temp[i] = (|din[i-1:0]) ? ~din[i] : din[i];
end : flip_after_first_one
assign dout[WIDTH-1:0] = { dout_temp[WIDTH-1:1], din[0] };
endmodule // 2'scomp
// find first
module rvfindfirst1 #( parameter WIDTH=32, SHIFT=$clog2(WIDTH) )
(
input logic [WIDTH-1:0] din,
output logic [SHIFT-1:0] dout
);
logic done;
always_comb begin
dout[SHIFT-1:0] = {SHIFT{1'b0}};
done = 1'b0;
for ( int i = WIDTH-1; i > 0; i-- ) begin : find_first_one
done |= din[i];
dout[SHIFT-1:0] += done ? 1'b0 : 1'b1;
end : find_first_one
end
endmodule // rvfindfirst1
module rvfindfirst1hot #( parameter WIDTH=32 )
(
input logic [WIDTH-1:0] din,
output logic [WIDTH-1:0] dout
);
logic done;
always_comb begin
dout[WIDTH-1:0] = {WIDTH{1'b0}};
done = 1'b0;
for ( int i = 0; i < WIDTH; i++ ) begin : find_first_one
dout[i] = ~done & din[i];
done |= din[i];
end : find_first_one
end
endmodule // rvfindfirst1hot
// mask and match function matches bits after finding the first 0 position
// find first starting from LSB. Skip that location and match the rest of the bits
module rvmaskandmatch #( parameter WIDTH=32 )
(
input logic [WIDTH-1:0] mask, // this will have the mask in the lower bit positions
input logic [WIDTH-1:0] data, // this is what needs to be matched on the upper bits with the mask's upper bits
input logic masken, // when 1 : do mask. 0 : full match
output logic match
);
logic [WIDTH-1:0] matchvec;
logic masken_or_fullmask;
assign masken_or_fullmask = masken & ~(&mask[WIDTH-1:0]);
assign matchvec[0] = masken_or_fullmask | (mask[0] == data[0]);
genvar i;
for ( i = 1; i < WIDTH; i++ ) begin : match_after_first_zero
assign matchvec[i] = (&mask[i-1:0] & masken_or_fullmask) ? 1'b1 : (mask[i] == data[i]);
end : match_after_first_zero
assign match = &matchvec[WIDTH-1:0]; // all bits either matched or were masked off
endmodule // rvmaskandmatch
// Check if the S_ADDR <= addr < E_ADDR
module rvrangecheck #(CCM_SADR = 32'h0,
CCM_SIZE = 128) (
input logic [31:0] addr, // Address to be checked for range
output logic in_range, // S_ADDR <= start_addr < E_ADDR
output logic in_region
);
localparam REGION_BITS = 4;
localparam MASK_BITS = 10 + $clog2(CCM_SIZE);
logic [31:0] start_addr;
logic [3:0] region;
assign start_addr[31:0] = CCM_SADR;
assign region[REGION_BITS-1:0] = start_addr[31:(32-REGION_BITS)];
assign in_region = (addr[31:(32-REGION_BITS)] == region[REGION_BITS-1:0]);
if (CCM_SIZE == 48)
assign in_range = (addr[31:MASK_BITS] == start_addr[31:MASK_BITS]) & ~(&addr[MASK_BITS-1 : MASK_BITS-2]);
else
assign in_range = (addr[31:MASK_BITS] == start_addr[31:MASK_BITS]);
endmodule // rvrangechecker
// 16 bit even parity generator
module rveven_paritygen #(WIDTH = 16) (
input logic [WIDTH-1:0] data_in, // Data
output logic parity_out // generated even parity
);
assign parity_out = ^(data_in[WIDTH-1:0]) ;
endmodule // rveven_paritygen
module rveven_paritycheck #(WIDTH = 16) (
input logic [WIDTH-1:0] data_in, // Data
input logic parity_in,
output logic parity_err // Parity error
);
assign parity_err = ^(data_in[WIDTH-1:0]) ^ parity_in ;
endmodule // rveven_paritycheck
module rvecc_encode (
input [31:0] din,
output [6:0] ecc_out
);
logic [5:0] ecc_out_temp;
assign ecc_out_temp[0] = din[0]^din[1]^din[3]^din[4]^din[6]^din[8]^din[10]^din[11]^din[13]^din[15]^din[17]^din[19]^din[21]^din[23]^din[25]^din[26]^din[28]^din[30];
assign ecc_out_temp[1] = din[0]^din[2]^din[3]^din[5]^din[6]^din[9]^din[10]^din[12]^din[13]^din[16]^din[17]^din[20]^din[21]^din[24]^din[25]^din[27]^din[28]^din[31];
assign ecc_out_temp[2] = din[1]^din[2]^din[3]^din[7]^din[8]^din[9]^din[10]^din[14]^din[15]^din[16]^din[17]^din[22]^din[23]^din[24]^din[25]^din[29]^din[30]^din[31];
assign ecc_out_temp[3] = din[4]^din[5]^din[6]^din[7]^din[8]^din[9]^din[10]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25];
assign ecc_out_temp[4] = din[11]^din[12]^din[13]^din[14]^din[15]^din[16]^din[17]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25];
assign ecc_out_temp[5] = din[26]^din[27]^din[28]^din[29]^din[30]^din[31];
assign ecc_out[6:0] = {(^din[31:0])^(^ecc_out_temp[5:0]),ecc_out_temp[5:0]};
endmodule // rvecc_encode
module rvecc_decode (
input en,
input [31:0] din,
input [6:0] ecc_in,
input sed_ded, // only do detection and no correction. Used for the I$
output [31:0] dout,
output [6:0] ecc_out,
output single_ecc_error,
output double_ecc_error
);
logic [6:0] ecc_check;
logic [38:0] error_mask;
logic [38:0] din_plus_parity, dout_plus_parity;
// Generate the ecc bits
assign ecc_check[0] = ecc_in[0]^din[0]^din[1]^din[3]^din[4]^din[6]^din[8]^din[10]^din[11]^din[13]^din[15]^din[17]^din[19]^din[21]^din[23]^din[25]^din[26]^din[28]^din[30];
assign ecc_check[1] = ecc_in[1]^din[0]^din[2]^din[3]^din[5]^din[6]^din[9]^din[10]^din[12]^din[13]^din[16]^din[17]^din[20]^din[21]^din[24]^din[25]^din[27]^din[28]^din[31];
assign ecc_check[2] = ecc_in[2]^din[1]^din[2]^din[3]^din[7]^din[8]^din[9]^din[10]^din[14]^din[15]^din[16]^din[17]^din[22]^din[23]^din[24]^din[25]^din[29]^din[30]^din[31];
assign ecc_check[3] = ecc_in[3]^din[4]^din[5]^din[6]^din[7]^din[8]^din[9]^din[10]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25];
assign ecc_check[4] = ecc_in[4]^din[11]^din[12]^din[13]^din[14]^din[15]^din[16]^din[17]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25];
assign ecc_check[5] = ecc_in[5]^din[26]^din[27]^din[28]^din[29]^din[30]^din[31];
// This is the parity bit
assign ecc_check[6] = ((^din[31:0])^(^ecc_in[6:0])) & ~sed_ded;
assign single_ecc_error = en & (ecc_check[6:0] != 0) & ecc_check[6]; // this will never be on for sed_ded
assign double_ecc_error = en & (ecc_check[6:0] != 0) & ~ecc_check[6]; // all errors in the sed_ded case will be recorded as DE
// Generate the mask for error correctiong
for (genvar i=1; i<40; i++) begin
assign error_mask[i-1] = (ecc_check[5:0] == i);
end
// Generate the corrected data
assign din_plus_parity[38:0] = {ecc_in[6], din[31:26], ecc_in[5], din[25:11], ecc_in[4], din[10:4], ecc_in[3], din[3:1], ecc_in[2], din[0], ecc_in[1:0]};
assign dout_plus_parity[38:0] = single_ecc_error ? (error_mask[38:0] ^ din_plus_parity[38:0]) : din_plus_parity[38:0];
assign dout[31:0] = {dout_plus_parity[37:32], dout_plus_parity[30:16], dout_plus_parity[14:8], dout_plus_parity[6:4], dout_plus_parity[2]};
assign ecc_out[6:0] = {(dout_plus_parity[38] ^ (ecc_check[6:0] == 7'b1000000)), dout_plus_parity[31], dout_plus_parity[15], dout_plus_parity[7], dout_plus_parity[3], dout_plus_parity[1:0]};
endmodule // rvecc_decode
module rvecc_encode_64 (
input [63:0] din,
output [6:0] ecc_out
);
assign ecc_out[0] = din[0]^din[1]^din[3]^din[4]^din[6]^din[8]^din[10]^din[11]^din[13]^din[15]^din[17]^din[19]^din[21]^din[23]^din[25]^din[26]^din[28]^din[30]^din[32]^din[34]^din[36]^din[38]^din[40]^din[42]^din[44]^din[46]^din[48]^din[50]^din[52]^din[54]^din[56]^din[57]^din[59]^din[61]^din[63];
assign ecc_out[1] = din[0]^din[2]^din[3]^din[5]^din[6]^din[9]^din[10]^din[12]^din[13]^din[16]^din[17]^din[20]^din[21]^din[24]^din[25]^din[27]^din[28]^din[31]^din[32]^din[35]^din[36]^din[39]^din[40]^din[43]^din[44]^din[47]^din[48]^din[51]^din[52]^din[55]^din[56]^din[58]^din[59]^din[62]^din[63];
assign ecc_out[2] = din[1]^din[2]^din[3]^din[7]^din[8]^din[9]^din[10]^din[14]^din[15]^din[16]^din[17]^din[22]^din[23]^din[24]^din[25]^din[29]^din[30]^din[31]^din[32]^din[37]^din[38]^din[39]^din[40]^din[45]^din[46]^din[47]^din[48]^din[53]^din[54]^din[55]^din[56]^din[60]^din[61]^din[62]^din[63];
assign ecc_out[3] = din[4]^din[5]^din[6]^din[7]^din[8]^din[9]^din[10]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25]^din[33]^din[34]^din[35]^din[36]^din[37]^din[38]^din[39]^din[40]^din[49]^din[50]^din[51]^din[52]^din[53]^din[54]^din[55]^din[56];
assign ecc_out[4] = din[11]^din[12]^din[13]^din[14]^din[15]^din[16]^din[17]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25]^din[41]^din[42]^din[43]^din[44]^din[45]^din[46]^din[47]^din[48]^din[49]^din[50]^din[51]^din[52]^din[53]^din[54]^din[55]^din[56];
assign ecc_out[5] = din[26]^din[27]^din[28]^din[29]^din[30]^din[31]^din[32]^din[33]^din[34]^din[35]^din[36]^din[37]^din[38]^din[39]^din[40]^din[41]^din[42]^din[43]^din[44]^din[45]^din[46]^din[47]^din[48]^din[49]^din[50]^din[51]^din[52]^din[53]^din[54]^din[55]^din[56];
assign ecc_out[6] = din[57]^din[58]^din[59]^din[60]^din[61]^din[62]^din[63];
endmodule // rvecc_encode_64
module rvecc_decode_64 (
input en,
input [63:0] din,
input [6:0] ecc_in,
output ecc_error
);
logic [6:0] ecc_check;
// Generate the ecc bits
assign ecc_check[0] = ecc_in[0]^din[0]^din[1]^din[3]^din[4]^din[6]^din[8]^din[10]^din[11]^din[13]^din[15]^din[17]^din[19]^din[21]^din[23]^din[25]^din[26]^din[28]^din[30]^din[32]^din[34]^din[36]^din[38]^din[40]^din[42]^din[44]^din[46]^din[48]^din[50]^din[52]^din[54]^din[56]^din[57]^din[59]^din[61]^din[63];
assign ecc_check[1] = ecc_in[1]^din[0]^din[2]^din[3]^din[5]^din[6]^din[9]^din[10]^din[12]^din[13]^din[16]^din[17]^din[20]^din[21]^din[24]^din[25]^din[27]^din[28]^din[31]^din[32]^din[35]^din[36]^din[39]^din[40]^din[43]^din[44]^din[47]^din[48]^din[51]^din[52]^din[55]^din[56]^din[58]^din[59]^din[62]^din[63];
assign ecc_check[2] = ecc_in[2]^din[1]^din[2]^din[3]^din[7]^din[8]^din[9]^din[10]^din[14]^din[15]^din[16]^din[17]^din[22]^din[23]^din[24]^din[25]^din[29]^din[30]^din[31]^din[32]^din[37]^din[38]^din[39]^din[40]^din[45]^din[46]^din[47]^din[48]^din[53]^din[54]^din[55]^din[56]^din[60]^din[61]^din[62]^din[63];
assign ecc_check[3] = ecc_in[3]^din[4]^din[5]^din[6]^din[7]^din[8]^din[9]^din[10]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25]^din[33]^din[34]^din[35]^din[36]^din[37]^din[38]^din[39]^din[40]^din[49]^din[50]^din[51]^din[52]^din[53]^din[54]^din[55]^din[56];
assign ecc_check[4] = ecc_in[4]^din[11]^din[12]^din[13]^din[14]^din[15]^din[16]^din[17]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25]^din[41]^din[42]^din[43]^din[44]^din[45]^din[46]^din[47]^din[48]^din[49]^din[50]^din[51]^din[52]^din[53]^din[54]^din[55]^din[56];
assign ecc_check[5] = ecc_in[5]^din[26]^din[27]^din[28]^din[29]^din[30]^din[31]^din[32]^din[33]^din[34]^din[35]^din[36]^din[37]^din[38]^din[39]^din[40]^din[41]^din[42]^din[43]^din[44]^din[45]^din[46]^din[47]^din[48]^din[49]^din[50]^din[51]^din[52]^din[53]^din[54]^din[55]^din[56];
assign ecc_check[6] = ecc_in[6]^din[57]^din[58]^din[59]^din[60]^din[61]^din[62]^din[63];
assign ecc_error = en & (ecc_check[6:0] != 0); // all errors in the sed_ded case will be recorded as DE
endmodule // rvecc_decode_64
module TEC_RV_ICG
(
input logic SE, EN, CK,
output Q
);
logic en_ff;
logic enable;
assign enable = EN | SE;
`ifdef VERILATOR
always @(negedge CK) begin
en_ff <= enable;
end
`else
always @(CK, enable) begin
if(!CK)
en_ff = enable;
end
`endif
assign Q = CK & en_ff;
endmodule
module rvclkhdr
(
input logic en,
input logic clk,
input logic scan_mode,
output logic l1clk
);
logic SE;
assign SE = 0;
TEC_RV_ICG clkhdr ( .*, .EN(en), .CK(clk), .Q(l1clk));
endmodule // rvclkhdr
module rvoclkhdr
(
input logic en,
input logic clk,
input logic scan_mode,
output logic l1clk
);
logic SE;
assign SE = 0;
`ifdef RV_FPGA_OPTIMIZE
assign l1clk = clk;
`else
TEC_RV_ICG clkhdr ( .*, .EN(en), .CK(clk), .Q(l1clk));
`endif
endmodule

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// SPDX-License-Identifier: Apache-2.0
// Copyright 2018 Western Digital Corporation or it's affiliates.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//------------------------------------------------------------------------------------
//
// Copyright Western Digital, 2019
// Owner : Alex Grobman
// Description:
// This module Synchronizes the signals between JTAG (TCK) and
// processor (Core_clk)
//
//-------------------------------------------------------------------------------------
module dmi_jtag_to_core_sync (
// JTAG signals
input rd_en, // 1 bit Read Enable from JTAG
input wr_en, // 1 bit Write enable from JTAG
// Processor Signals
input rst_n, // Core reset
input clk, // Core clock
output reg_en, // 1 bit Write interface bit to Processor
output reg_wr_en // 1 bit Write enable to Processor
);
wire c_rd_en;
wire c_wr_en;
reg [2:0] rden, wren;
// Outputs
assign reg_en = c_wr_en | c_rd_en;
assign reg_wr_en = c_wr_en;
// synchronizers
always @ ( posedge clk or negedge rst_n) begin
if(!rst_n) begin
rden <= '0;
wren <= '0;
end
else begin
rden <= {rden[1:0], rd_en};
wren <= {wren[1:0], wr_en};
end
end
assign c_rd_en = rden[1] & ~rden[2];
assign c_wr_en = wren[1] & ~wren[2];
endmodule

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// SPDX-License-Identifier: Apache-2.0
// Copyright 2018 Western Digital Corporation or it's affiliates.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//------------------------------------------------------------------------------------
//
// Copyright Western Digital, 2018
// Owner : Anusha Narayanamoorthy
// Description:
// Wrapper module for JTAG_TAP and DMI synchronizer
//
//-------------------------------------------------------------------------------------
// `include "rvjtag_tap.sv"
// `include "dmi_jtag_to_core_sync.sv"
module dmi_wrapper(
// JTAG signals
input trst_n, // JTAG reset
input tck, // JTAG clock
input tms, // Test mode select
input tdi, // Test Data Input
output tdo, // Test Data Output
output tdoEnable, // Test Data Output enable
// Processor Signals
input core_rst_n, // Core reset
input core_clk, // Core clock
input [31:1] jtag_id, // JTAG ID
input [31:0] rd_data, // 32 bit Read data from Processor
output [31:0] reg_wr_data, // 32 bit Write data to Processor
output [6:0] reg_wr_addr, // 7 bit reg address to Processor
output reg_en, // 1 bit Read enable to Processor
output reg_wr_en, // 1 bit Write enable to Processor
output dmi_hard_reset
);
//Wire Declaration
wire rd_en;
wire wr_en;
wire dmireset;
//jtag_tap instantiation
rvjtag_tap i_jtag_tap(
.trst(trst_n), // dedicated JTAG TRST (active low) pad signal or asynchronous active low power on reset
.tck(tck), // dedicated JTAG TCK pad signal
.tms(tms), // dedicated JTAG TMS pad signal
.tdi(tdi), // dedicated JTAG TDI pad signal
.tdo(tdo), // dedicated JTAG TDO pad signal
.tdoEnable(tdoEnable), // enable for TDO pad
.wr_data(reg_wr_data), // 32 bit Write data
.wr_addr(reg_wr_addr), // 7 bit Write address
.rd_en(rd_en), // 1 bit read enable
.wr_en(wr_en), // 1 bit Write enable
.rd_data(rd_data), // 32 bit Read data
.rd_status(2'b0),
.idle(3'h0), // no need to wait to sample data
.dmi_stat(2'b0), // no need to wait or error possible
.version(4'h1), // debug spec 0.13 compliant
.jtag_id(jtag_id),
.dmi_hard_reset(dmi_hard_reset),
.dmi_reset(dmireset)
);
// dmi_jtag_to_core_sync instantiation
dmi_jtag_to_core_sync i_dmi_jtag_to_core_sync(
.wr_en(wr_en), // 1 bit Write enable
.rd_en(rd_en), // 1 bit Read enable
.rst_n(core_rst_n),
.clk(core_clk),
.reg_en(reg_en), // 1 bit Write interface bit
.reg_wr_en(reg_wr_en) // 1 bit Write enable
);
endmodule

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module gated_latch
(
input logic SE, EN, CK,
output Q
);
logic en_ff;
logic enable;
assign enable = EN | SE;
always @(CK, enable) begin
if(!CK)
en_ff = enable;
end
assign Q = CK & en_ff;
endmodule

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//********************************************************************************
// SPDX-License-Identifier: Apache-2.0
// Copyright 2020 Western Digital Corporation or its affiliates.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//********************************************************************************
//********************************************************************************
// Icache closely coupled memory --- ICCM
//********************************************************************************
module ifu_iccm_mem
`include "parameter.sv"
//#(
// parameter ICCM_BITS,
// parameter ICCM_BANK_INDEX_LO,
// parameter ICCM_INDEX_BITS,
// parameter ICCM_BANK_HI,
// parameter ICCM_NUM_BANKS,
// parameter ICCM_ENABLE= 'b1,
// parameter ICCM_BANK_BITS
//)
(
input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK.
input logic active_clk, // Clock only while core active. Through two clock headers. For flops without second clock header built in.
input logic rst_l, // reset, active low
input logic clk_override, // Override non-functional clock gating
input logic iccm_wren, // ICCM write enable
input logic iccm_rden, // ICCM read enable
input logic [ICCM_BITS-1:1] iccm_rw_addr, // ICCM read/write address
input logic iccm_buf_correct_ecc, // ICCM is doing a single bit error correct cycle
input logic iccm_correction_state, // ICCM under a correction - This is needed to guard replacements when hit
input logic [2:0] iccm_wr_size, // ICCM write size
input logic [77:0] iccm_wr_data, // ICCM write data
input iccm_ext_in_pkt_t [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt, // External packet
output logic [63:0] iccm_rd_data, // ICCM read data
output logic [77:0] iccm_rd_data_ecc, // ICCM read ecc
input logic scan_mode // Scan mode control
);
logic [ICCM_NUM_BANKS-1:0] wren_bank;
logic [ICCM_NUM_BANKS-1:0] rden_bank;
logic [ICCM_NUM_BANKS-1:0] iccm_clken;
logic [ICCM_NUM_BANKS-1:0] [ICCM_BITS-1:ICCM_BANK_INDEX_LO] addr_bank;
logic [ICCM_NUM_BANKS-1:0] [38:0] iccm_bank_dout, iccm_bank_dout_fn;
logic [ICCM_NUM_BANKS-1:0] [38:0] iccm_bank_wr_data;
logic [ICCM_BITS-1:1] addr_bank_inc;
logic [ICCM_BANK_HI : 2] iccm_rd_addr_hi_q;
logic [ICCM_BANK_HI : 1] iccm_rd_addr_lo_q;
logic [63:0] iccm_rd_data_pre;
logic [63:0] iccm_data;
logic [1:0] addr_incr;
logic [ICCM_NUM_BANKS-1:0] [38:0] iccm_bank_wr_data_vec;
// logic to handle hard persisten faults
logic [1:0] [ICCM_BITS-1:2] redundant_address;
logic [1:0] [38:0] redundant_data;
logic [1:0] redundant_valid;
logic [ICCM_NUM_BANKS-1:0] sel_red1, sel_red0, sel_red1_q, sel_red0_q;
logic [38:0] redundant_data0_in, redundant_data1_in;
logic redundant_lru, redundant_lru_in, redundant_lru_en;
logic redundant_data0_en;
logic redundant_data1_en;
logic r0_addr_en, r1_addr_en;
// Testing persistent flip
// logic [3:0] not_iccm_bank_dout;
// logic [15:3] ecc_insert_flip_in, ecc_insert_flip;
// logic flip_en, flip_match, flip_match_q;
//
// assign flip_in = (iccm_rw_addr[3:2] != 2'b00); // dont flip when bank0 - this is to make some progress in DMA streaming cases
// assign flip_en = iccm_rden;
//
// rvdffs #(1) flipmatch (.*,
// .clk(clk),
// .din(flip_in),
// .en(flip_en),
// .dout(flip_match_q));
//
// end of testing flip
assign addr_incr[1:0] = (iccm_wr_size[1:0] == 2'b11) ? 2'b10: 2'b01;
assign addr_bank_inc[ICCM_BITS-1 : 1] = iccm_rw_addr[ICCM_BITS-1 : 1] + addr_incr[1:0];
for (genvar i=0; i<ICCM_NUM_BANKS/2; i++) begin: mem_bank_data
assign iccm_bank_wr_data_vec[(2*i)] = iccm_wr_data[38:0];
assign iccm_bank_wr_data_vec[(2*i)+1] = iccm_wr_data[77:39];
end
for (genvar i=0; i<ICCM_NUM_BANKS; i++) begin: mem_bank
assign wren_bank[i] = iccm_wren & ((iccm_rw_addr[ICCM_BANK_HI:2] == i) | (addr_bank_inc[ICCM_BANK_HI:2] == i));
assign iccm_bank_wr_data[i] = iccm_bank_wr_data_vec[i];
assign rden_bank[i] = iccm_rden & ( (iccm_rw_addr[ICCM_BANK_HI:2] == i) | (addr_bank_inc[ICCM_BANK_HI:2] == i));
assign iccm_clken[i] = wren_bank[i] | rden_bank[i] | clk_override;
assign addr_bank[i][ICCM_BITS-1 : ICCM_BANK_INDEX_LO] = wren_bank[i] ? iccm_rw_addr[ICCM_BITS-1 : ICCM_BANK_INDEX_LO] :
((addr_bank_inc[ICCM_BANK_HI:2] == i) ?
addr_bank_inc[ICCM_BITS-1 : ICCM_BANK_INDEX_LO] :
iccm_rw_addr[ICCM_BITS-1 : ICCM_BANK_INDEX_LO]);
`ifdef VERILATOR
el2_ram #(.depth(1<<ICCM_INDEX_BITS), .width(39)) iccm_bank (
// Primary ports
.ME(iccm_clken[i]),
.CLK(clk),
.WE(wren_bank[i]),
.ADR(addr_bank[i]),
.D(iccm_bank_wr_data[i][38:0]),
.Q(iccm_bank_dout[i][38:0]),
.ROP ( ),
// These are used by SoC
.TEST1(iccm_ext_in_pkt[i].TEST1),
.RME(iccm_ext_in_pkt[i].RME),
.RM(iccm_ext_in_pkt[i].RM),
.LS(iccm_ext_in_pkt[i].LS),
.DS(iccm_ext_in_pkt[i].DS),
.SD(iccm_ext_in_pkt[i].SD) ,
.TEST_RNM(iccm_ext_in_pkt[i].TEST_RNM),
.BC1(iccm_ext_in_pkt[i].BC1),
.BC2(iccm_ext_in_pkt[i].BC2)
);
`else
if (ICCM_INDEX_BITS == 6 ) begin : iccm
ram_64x39 iccm_bank (
// Primary ports
.CLK(clk),
.ME(iccm_clken[i]),
.WE(wren_bank[i]),
.ADR(addr_bank[i]),
.D(iccm_bank_wr_data[i][38:0]),
.Q(iccm_bank_dout[i][38:0]),
.ROP ( ),
// These are used by SoC
.TEST1(iccm_ext_in_pkt[i].TEST1),
.RME(iccm_ext_in_pkt[i].RME),
.RM(iccm_ext_in_pkt[i].RM),
.LS(iccm_ext_in_pkt[i].LS),
.DS(iccm_ext_in_pkt[i].DS),
.SD(iccm_ext_in_pkt[i].SD) ,
.TEST_RNM(iccm_ext_in_pkt[i].TEST_RNM),
.BC1(iccm_ext_in_pkt[i].BC1),
.BC2(iccm_ext_in_pkt[i].BC2)
);
end // block: iccm
else if (ICCM_INDEX_BITS == 7 ) begin : iccm
ram_128x39 iccm_bank (
// Primary ports
.CLK(clk),
.ME(iccm_clken[i]),
.WE(wren_bank[i]),
.ADR(addr_bank[i]),
.D(iccm_bank_wr_data[i][38:0]),
.Q(iccm_bank_dout[i][38:0]),
.ROP ( ),
// These are used by SoC
.TEST1(iccm_ext_in_pkt[i].TEST1),
.RME(iccm_ext_in_pkt[i].RME),
.RM(iccm_ext_in_pkt[i].RM),
.LS(iccm_ext_in_pkt[i].LS),
.DS(iccm_ext_in_pkt[i].DS),
.SD(iccm_ext_in_pkt[i].SD) ,
.TEST_RNM(iccm_ext_in_pkt[i].TEST_RNM),
.BC1(iccm_ext_in_pkt[i].BC1),
.BC2(iccm_ext_in_pkt[i].BC2)
);
end // block: iccm
else if (ICCM_INDEX_BITS == 8 ) begin : iccm
ram_256x39 iccm_bank (
// Primary ports
.CLK(clk),
.ME(iccm_clken[i]),
.WE(wren_bank[i]),
.ADR(addr_bank[i]),
.D(iccm_bank_wr_data[i][38:0]),
.Q(iccm_bank_dout[i][38:0]),
.ROP ( ),
// These are used by SoC
.TEST1(iccm_ext_in_pkt[i].TEST1),
.RME(iccm_ext_in_pkt[i].RME),
.RM(iccm_ext_in_pkt[i].RM),
.LS(iccm_ext_in_pkt[i].LS),
.DS(iccm_ext_in_pkt[i].DS),
.SD(iccm_ext_in_pkt[i].SD) ,
.TEST_RNM(iccm_ext_in_pkt[i].TEST_RNM),
.BC1(iccm_ext_in_pkt[i].BC1),
.BC2(iccm_ext_in_pkt[i].BC2)
);
end // block: iccm
else if (ICCM_INDEX_BITS == 9 ) begin : iccm
ram_512x39 iccm_bank (
// Primary ports
.CLK(clk),
.ME(iccm_clken[i]),
.WE(wren_bank[i]),
.ADR(addr_bank[i]),
.D(iccm_bank_wr_data[i][38:0]),
.Q(iccm_bank_dout[i][38:0]),
.ROP ( ),
// These are used by SoC
.TEST1(iccm_ext_in_pkt[i].TEST1),
.RME(iccm_ext_in_pkt[i].RME),
.RM(iccm_ext_in_pkt[i].RM),
.LS(iccm_ext_in_pkt[i].LS),
.DS(iccm_ext_in_pkt[i].DS),
.SD(iccm_ext_in_pkt[i].SD) ,
.TEST_RNM(iccm_ext_in_pkt[i].TEST_RNM),
.BC1(iccm_ext_in_pkt[i].BC1),
.BC2(iccm_ext_in_pkt[i].BC2)
);
end // block: iccm
else if (ICCM_INDEX_BITS == 10 ) begin : iccm
ram_1024x39 iccm_bank (
// Primary ports
.CLK(clk),
.ME(iccm_clken[i]),
.WE(wren_bank[i]),
.ADR(addr_bank[i]),
.D(iccm_bank_wr_data[i][38:0]),
.Q(iccm_bank_dout[i][38:0]),
.ROP ( ),
// These are used by SoC
.TEST1(iccm_ext_in_pkt[i].TEST1),
.RME(iccm_ext_in_pkt[i].RME),
.RM(iccm_ext_in_pkt[i].RM),
.LS(iccm_ext_in_pkt[i].LS),
.DS(iccm_ext_in_pkt[i].DS),
.SD(iccm_ext_in_pkt[i].SD) ,
.TEST_RNM(iccm_ext_in_pkt[i].TEST_RNM),
.BC1(iccm_ext_in_pkt[i].BC1),
.BC2(iccm_ext_in_pkt[i].BC2)
);
end // block: iccm
else if (ICCM_INDEX_BITS == 11 ) begin : iccm
ram_2048x39 iccm_bank (
// Primary ports
.CLK(clk),
.ME(iccm_clken[i]),
.WE(wren_bank[i]),
.ADR(addr_bank[i]),
.D(iccm_bank_wr_data[i][38:0]),
.Q(iccm_bank_dout[i][38:0]),
.ROP ( ),
// These are used by SoC
.TEST1(iccm_ext_in_pkt[i].TEST1),
.RME(iccm_ext_in_pkt[i].RME),
.RM(iccm_ext_in_pkt[i].RM),
.LS(iccm_ext_in_pkt[i].LS),
.DS(iccm_ext_in_pkt[i].DS),
.SD(iccm_ext_in_pkt[i].SD) ,
.TEST_RNM(iccm_ext_in_pkt[i].TEST_RNM),
.BC1(iccm_ext_in_pkt[i].BC1),
.BC2(iccm_ext_in_pkt[i].BC2)
);
end // block: iccm
else if (ICCM_INDEX_BITS == 12 ) begin : iccm
ram_4096x39 iccm_bank (
// Primary ports
.CLK(clk),
.ME(iccm_clken[i]),
.WE(wren_bank[i]),
.ADR(addr_bank[i]),
.D(iccm_bank_wr_data[i][38:0]),
.Q(iccm_bank_dout[i][38:0]),
.ROP ( ),
// These are used by SoC
.TEST1(iccm_ext_in_pkt[i].TEST1),
.RME(iccm_ext_in_pkt[i].RME),
.RM(iccm_ext_in_pkt[i].RM),
.LS(iccm_ext_in_pkt[i].LS),
.DS(iccm_ext_in_pkt[i].DS),
.SD(iccm_ext_in_pkt[i].SD) ,
.TEST_RNM(iccm_ext_in_pkt[i].TEST_RNM),
.BC1(iccm_ext_in_pkt[i].BC1),
.BC2(iccm_ext_in_pkt[i].BC2)
);
end // block: iccm
else if (ICCM_INDEX_BITS == 13 ) begin : iccm
ram_8192x39 iccm_bank (
// Primary ports
.CLK(clk),
.ME(iccm_clken[i]),
.WE(wren_bank[i]),
.ADR(addr_bank[i]),
.D(iccm_bank_wr_data[i][38:0]),
.Q(iccm_bank_dout[i][38:0]),
.ROP ( ),
// These are used by SoC
.TEST1(iccm_ext_in_pkt[i].TEST1),
.RME(iccm_ext_in_pkt[i].RME),
.RM(iccm_ext_in_pkt[i].RM),
.LS(iccm_ext_in_pkt[i].LS),
.DS(iccm_ext_in_pkt[i].DS),
.SD(iccm_ext_in_pkt[i].SD) ,
.TEST_RNM(iccm_ext_in_pkt[i].TEST_RNM),
.BC1(iccm_ext_in_pkt[i].BC1),
.BC2(iccm_ext_in_pkt[i].BC2)
);
end // block: iccm
else if (ICCM_INDEX_BITS == 14 ) begin : iccm
ram_16384x39 iccm_bank (
// Primary ports
.CLK(clk),
.ME(iccm_clken[i]),
.WE(wren_bank[i]),
.ADR(addr_bank[i]),
.D(iccm_bank_wr_data[i][38:0]),
.Q(iccm_bank_dout[i][38:0]),
.ROP ( ),
// These are used by SoC
.TEST1(iccm_ext_in_pkt[i].TEST1),
.RME(iccm_ext_in_pkt[i].RME),
.RM(iccm_ext_in_pkt[i].RM),
.LS(iccm_ext_in_pkt[i].LS),
.DS(iccm_ext_in_pkt[i].DS),
.SD(iccm_ext_in_pkt[i].SD) ,
.TEST_RNM(iccm_ext_in_pkt[i].TEST_RNM),
.BC1(iccm_ext_in_pkt[i].BC1),
.BC2(iccm_ext_in_pkt[i].BC2)
);
end // block: iccm
else begin : iccm
ram_32768x39 iccm_bank (
// Primary ports
.CLK(clk),
.ME(iccm_clken[i]),
.WE(wren_bank[i]),
.ADR(addr_bank[i]),
.D(iccm_bank_wr_data[i][38:0]),
.Q(iccm_bank_dout[i][38:0]),
.ROP ( ),
// These are used by SoC
.TEST1(iccm_ext_in_pkt[i].TEST1),
.RME(iccm_ext_in_pkt[i].RME),
.RM(iccm_ext_in_pkt[i].RM),
.LS(iccm_ext_in_pkt[i].LS),
.DS(iccm_ext_in_pkt[i].DS),
.SD(iccm_ext_in_pkt[i].SD) ,
.TEST_RNM(iccm_ext_in_pkt[i].TEST_RNM),
.BC1(iccm_ext_in_pkt[i].BC1),
.BC2(iccm_ext_in_pkt[i].BC2)
);
end // block: iccm
`endif
// match the redundant rows
assign sel_red1[i] = (redundant_valid[1] & (((iccm_rw_addr[ICCM_BITS-1:2] == redundant_address[1][ICCM_BITS-1:2]) & (iccm_rw_addr[3:2] == i)) |
((addr_bank_inc[ICCM_BITS-1:2]== redundant_address[1][ICCM_BITS-1:2]) & (addr_bank_inc[3:2] == i))));
assign sel_red0[i] = (redundant_valid[0] & (((iccm_rw_addr[ICCM_BITS-1:2] == redundant_address[0][ICCM_BITS-1:2]) & (iccm_rw_addr[3:2] == i)) |
((addr_bank_inc[ICCM_BITS-1:2]== redundant_address[0][ICCM_BITS-1:2]) & (addr_bank_inc[3:2] == i))));
rvdff #(1) selred0 (.*,
.clk(active_clk),
.din(sel_red0[i]),
.dout(sel_red0_q[i]));
rvdff #(1) selred1 (.*,
.clk(active_clk),
.din(sel_red1[i]),
.dout(sel_red1_q[i]));
// muxing out the memory data with the redundant data if the address matches
assign iccm_bank_dout_fn[i][38:0] = ({39{sel_red1_q[i]}} & redundant_data[1][38:0]) |
({39{sel_red0_q[i]}} & redundant_data[0][38:0]) |
({39{~sel_red0_q[i] & ~sel_red1_q[i]}} & iccm_bank_dout[i][38:0]);
end : mem_bank
// This section does the redundancy for tolerating single bit errors
// 2x 39 bit data values with address[hi:2] and a valid bit is needed to CAM and sub out the reads/writes to the particular locations
// Also a LRU flop is kept to decide which of the redundant element to replace.
assign r0_addr_en = ~redundant_lru & iccm_buf_correct_ecc;
assign r1_addr_en = redundant_lru & iccm_buf_correct_ecc;
assign redundant_lru_en = iccm_buf_correct_ecc | (((|sel_red0[ICCM_NUM_BANKS-1:0]) | (|sel_red1[ICCM_NUM_BANKS-1:0])) & iccm_rden & iccm_correction_state);
assign redundant_lru_in = iccm_buf_correct_ecc ? ~redundant_lru : (|sel_red0[ICCM_NUM_BANKS-1:0]) ? 1'b1 : 1'b0;
rvdffs #() red_lru (.*, // LRU flop for the redundant replacements
.clk(active_clk),
.en(redundant_lru_en),
.din(redundant_lru_in),
.dout(redundant_lru));
rvdffs #(ICCM_BITS-2) r0_address (.*, // Redundant Row 0 address
.clk(active_clk),
.en(r0_addr_en),
.din(iccm_rw_addr[ICCM_BITS-1:2]),
.dout(redundant_address[0][ICCM_BITS-1:2]));
rvdffs #(ICCM_BITS-2) r1_address (.*, // Redundant Row 0 address
.clk(active_clk),
.en(r1_addr_en),
.din(iccm_rw_addr[ICCM_BITS-1:2]),
.dout(redundant_address[1][ICCM_BITS-1:2]));
rvdffs #(1) r0_valid (.*,
.clk(active_clk), // Redundant Row 0 Valid
.en(r0_addr_en),
.din(1'b1),
.dout(redundant_valid[0]));
rvdffs #(1) r1_valid (.*, // Redundant Row 1 Valid
.clk(active_clk),
.en(r1_addr_en),
.din(1'b1),
.dout(redundant_valid[1]));
// We will have to update the Redundant copies in addition to the memory on subsequent writes to this memory location.
// The data gets updated on : 1) correction cycle, 2) Future writes - this could be W writes from DMA ( match up till addr[2]) or DW writes ( match till address[3])
// The data to pick also depends on the current address[2], size and the addr[2] stored in the address field of the redundant flop. Correction cycle is always W write and the data is splat on both legs, so choosing lower Word
assign redundant_data0_en = ((iccm_rw_addr[ICCM_BITS-1:3] == redundant_address[0][ICCM_BITS-1:3]) & ((iccm_rw_addr[2] == redundant_address[0][2]) | (iccm_wr_size[1:0] == 2'b11)) & redundant_valid[0] & iccm_wren) |
(~redundant_lru & iccm_buf_correct_ecc);
assign redundant_data0_in[38:0] = (((iccm_rw_addr[2] == redundant_address[0][2]) & iccm_rw_addr[2]) | (redundant_address[0][2] & (iccm_wr_size[1:0] == 2'b11))) ? iccm_wr_data[77:39] : iccm_wr_data[38:0];
rvdffs #(39) r0_data (.*, // Redundant Row 1 data
.clk(active_clk),
.en(redundant_data0_en),
.din(redundant_data0_in[38:0]),
.dout(redundant_data[0][38:0]));
assign redundant_data1_en = ((iccm_rw_addr[ICCM_BITS-1:3] == redundant_address[1][ICCM_BITS-1:3]) & ((iccm_rw_addr[2] == redundant_address[1][2]) | (iccm_wr_size[1:0] == 2'b11)) & redundant_valid[1] & iccm_wren) |
(redundant_lru & iccm_buf_correct_ecc);
assign redundant_data1_in[38:0] = (((iccm_rw_addr[2] == redundant_address[1][2]) & iccm_rw_addr[2]) | (redundant_address[1][2] & (iccm_wr_size[1:0] == 2'b11))) ? iccm_wr_data[77:39] : iccm_wr_data[38:0];
rvdffs #(39) r1_data (.*, // Redundant Row 1 data
.clk(active_clk),
.en(redundant_data1_en),
.din(redundant_data1_in[38:0]),
.dout(redundant_data[1][38:0]));
rvdffs #(ICCM_BANK_HI) rd_addr_lo_ff (.*, .clk(active_clk), .din(iccm_rw_addr [ICCM_BANK_HI:1]), .dout(iccm_rd_addr_lo_q[ICCM_BANK_HI:1]), .en(1'b1)); // bit 0 of address is always 0
rvdffs #(ICCM_BANK_BITS) rd_addr_hi_ff (.*, .clk(active_clk), .din(addr_bank_inc[ICCM_BANK_HI:2]), .dout(iccm_rd_addr_hi_q[ICCM_BANK_HI:2]), .en(1'b1));
assign iccm_rd_data_pre[63:0] = {iccm_bank_dout_fn[iccm_rd_addr_hi_q][31:0], iccm_bank_dout_fn[iccm_rd_addr_lo_q[ICCM_BANK_HI:2]][31:0]};
assign iccm_data[63:0] = 64'({16'b0, (iccm_rd_data_pre[63:0] >> (16*iccm_rd_addr_lo_q[1]))});
assign iccm_rd_data[63:0] = {iccm_data[63:0]};
assign iccm_rd_data_ecc[77:0] = {iccm_bank_dout_fn[iccm_rd_addr_hi_q][38:0], iccm_bank_dout_fn[iccm_rd_addr_lo_q[ICCM_BANK_HI:2]][38:0]};
endmodule // ifu_iccm_mem

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verif/LEC/LEC_RTL/generated_rtl/lsu_dccm_mem.sv Normal file
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@ -0,0 +1,302 @@
// SPDX-License-Identifier: Apache-2.0
// Copyright 2020 Western Digital Corporation or its affiliates.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//********************************************************************************
// $Id$
//
//
// Owner:
// Function: DCCM for LSU pipe
// Comments: Single ported memory
//
//
// DC1 -> DC2 -> DC3 -> DC4 (Commit)
//
// //********************************************************************************
`define LOCAL_DCCM_RAM_TEST_PORTS .TEST1(dccm_ext_in_pkt[i].TEST1), \
.RME(dccm_ext_in_pkt[i].RME), \
.RM(dccm_ext_in_pkt[i].RM), \
.LS(dccm_ext_in_pkt[i].LS), \
.DS(dccm_ext_in_pkt[i].DS), \
.SD(dccm_ext_in_pkt[i].SD), \
.TEST_RNM(dccm_ext_in_pkt[i].TEST_RNM), \
.BC1(dccm_ext_in_pkt[i].BC1), \
.BC2(dccm_ext_in_pkt[i].BC2), \
module lsu_dccm_mem
`include "parameter.sv"
//#(
// parameter DCCM_BYTE_WIDTH,
// parameter DCCM_BITS,
// parameter DCCM_NUM_BANKS,
// parameter DCCM_ENABLE= 'b1,
// parameter DCCM_BANK_BITS,
// parameter DCCM_SIZE,
// parameter DCCM_FDATA_WIDTH,
// parameter DCCM_WIDTH_BITS
//)
(
input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK.
input logic active_clk, // Clock only while core active. Through two clock headers. For flops without second clock header built in.
input logic rst_l, // reset, active low
input logic clk_override, // Override non-functional clock gating
input logic dccm_wren, // write enable
input logic dccm_rden, // read enable
input logic [DCCM_BITS-1:0] dccm_wr_addr_lo, // write address
input logic [DCCM_BITS-1:0] dccm_wr_addr_hi, // write address
input logic [DCCM_BITS-1:0] dccm_rd_addr_lo, // read address
input logic [DCCM_BITS-1:0] dccm_rd_addr_hi, // read address for the upper bank in case of a misaligned access
input logic [DCCM_FDATA_WIDTH-1:0] dccm_wr_data_lo, // write data
input logic [DCCM_FDATA_WIDTH-1:0] dccm_wr_data_hi, // write data
input dccm_ext_in_pkt_t [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt, // the dccm packet from the soc
output logic [DCCM_FDATA_WIDTH-1:0] dccm_rd_data_lo, // read data from the lo bank
output logic [DCCM_FDATA_WIDTH-1:0] dccm_rd_data_hi, // read data from the hi bank
input logic scan_mode
);
//localparam DCCM_WIDTH_BITS = $clog2(DCCM_BYTE_WIDTH);
localparam DCCM_INDEX_BITS = (DCCM_BITS - DCCM_BANK_BITS - DCCM_WIDTH_BITS);
localparam DCCM_INDEX_DEPTH = ((DCCM_SIZE)*1024)/((DCCM_BYTE_WIDTH)*(DCCM_NUM_BANKS)); // Depth of memory bank
logic [DCCM_NUM_BANKS-1:0] wren_bank;
logic [DCCM_NUM_BANKS-1:0] rden_bank;
logic [DCCM_NUM_BANKS-1:0] [DCCM_BITS-1:(DCCM_BANK_BITS+2)] addr_bank;
logic [DCCM_BITS-1:(DCCM_BANK_BITS+DCCM_WIDTH_BITS)] rd_addr_even, rd_addr_odd;
logic rd_unaligned, wr_unaligned;
logic [DCCM_NUM_BANKS-1:0] [DCCM_FDATA_WIDTH-1:0] dccm_bank_dout;
logic [DCCM_FDATA_WIDTH-1:0] wrdata;
logic [DCCM_NUM_BANKS-1:0][DCCM_FDATA_WIDTH-1:0] wr_data_bank;
logic [(DCCM_WIDTH_BITS+DCCM_BANK_BITS-1):DCCM_WIDTH_BITS] dccm_rd_addr_lo_q;
logic [(DCCM_WIDTH_BITS+DCCM_BANK_BITS-1):DCCM_WIDTH_BITS] dccm_rd_addr_hi_q;
logic [DCCM_NUM_BANKS-1:0] dccm_clken;
assign rd_unaligned = (dccm_rd_addr_lo[DCCM_WIDTH_BITS+:DCCM_BANK_BITS] != dccm_rd_addr_hi[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]);
assign wr_unaligned = (dccm_wr_addr_lo[DCCM_WIDTH_BITS+:DCCM_BANK_BITS] != dccm_wr_addr_hi[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]);
// Align the read data
assign dccm_rd_data_lo[DCCM_FDATA_WIDTH-1:0] = dccm_bank_dout[dccm_rd_addr_lo_q[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]][DCCM_FDATA_WIDTH-1:0];
assign dccm_rd_data_hi[DCCM_FDATA_WIDTH-1:0] = dccm_bank_dout[dccm_rd_addr_hi_q[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]][DCCM_FDATA_WIDTH-1:0];
// 8 Banks, 16KB each (2048 x 72)
for (genvar i=0; i<DCCM_NUM_BANKS; i++) begin: mem_bank
assign wren_bank[i] = dccm_wren & ((dccm_wr_addr_hi[2+:DCCM_BANK_BITS] == i) | (dccm_wr_addr_lo[2+:DCCM_BANK_BITS] == i));
assign rden_bank[i] = dccm_rden & ((dccm_rd_addr_hi[2+:DCCM_BANK_BITS] == i) | (dccm_rd_addr_lo[2+:DCCM_BANK_BITS] == i));
assign addr_bank[i][(DCCM_BANK_BITS+DCCM_WIDTH_BITS)+:DCCM_INDEX_BITS] = wren_bank[i] ? (((dccm_wr_addr_hi[2+:DCCM_BANK_BITS] == i) & wr_unaligned) ?
dccm_wr_addr_hi[(DCCM_BANK_BITS+DCCM_WIDTH_BITS)+:DCCM_INDEX_BITS] :
dccm_wr_addr_lo[(DCCM_BANK_BITS+DCCM_WIDTH_BITS)+:DCCM_INDEX_BITS]) :
(((dccm_rd_addr_hi[2+:DCCM_BANK_BITS] == i) & rd_unaligned) ?
dccm_rd_addr_hi[(DCCM_BANK_BITS+DCCM_WIDTH_BITS)+:DCCM_INDEX_BITS] :
dccm_rd_addr_lo[(DCCM_BANK_BITS+DCCM_WIDTH_BITS)+:DCCM_INDEX_BITS]);
assign wr_data_bank[i] = ((dccm_wr_addr_hi[2+:DCCM_BANK_BITS] == i) & wr_unaligned) ? dccm_wr_data_hi[DCCM_FDATA_WIDTH-1:0] : dccm_wr_data_lo[DCCM_FDATA_WIDTH-1:0];
// clock gating section
assign dccm_clken[i] = (wren_bank[i] | rden_bank[i] | clk_override) ;
// end clock gating section
`ifdef VERILATOR
ram #(DCCM_INDEX_DEPTH,39) ram (
// Primary ports
.ME(dccm_clken[i]),
.CLK(clk),
.WE(wren_bank[i]),
.ADR(addr_bank[i]),
.D(wr_data_bank[i][DCCM_FDATA_WIDTH-1:0]),
.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
.ROP ( ),
// These are used by SoC
`LOCAL_DCCM_RAM_TEST_PORTS
.*
);
`else
if (DCCM_INDEX_DEPTH == 32768) begin : dccm
ram_32768x39 dccm_bank (
// Primary ports
.ME(dccm_clken[i]),
.CLK(clk),
.WE(wren_bank[i]),
.ADR(addr_bank[i]),
.D(wr_data_bank[i][DCCM_FDATA_WIDTH-1:0]),
.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
.ROP ( ),
// These are used by SoC
`LOCAL_DCCM_RAM_TEST_PORTS
.*
);
end
else if (DCCM_INDEX_DEPTH == 16384) begin : dccm
ram_16384x39 dccm_bank (
// Primary ports
.ME(dccm_clken[i]),
.CLK(clk),
.WE(wren_bank[i]),
.ADR(addr_bank[i]),
.D(wr_data_bank[i][DCCM_FDATA_WIDTH-1:0]),
.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
.ROP ( ),
// These are used by SoC
`LOCAL_DCCM_RAM_TEST_PORTS
.*
);
end
else if (DCCM_INDEX_DEPTH == 8192) begin : dccm
ram_8192x39 dccm_bank (
// Primary ports
.ME(dccm_clken[i]),
.CLK(clk),
.WE(wren_bank[i]),
.ADR(addr_bank[i]),
.D(wr_data_bank[i][DCCM_FDATA_WIDTH-1:0]),
.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
.ROP ( ),
// These are used by SoC
`LOCAL_DCCM_RAM_TEST_PORTS
.*
);
end
else if (DCCM_INDEX_DEPTH == 4096) begin : dccm
ram_4096x39 dccm_bank (
// Primary ports
.ME(dccm_clken[i]),
.CLK(clk),
.WE(wren_bank[i]),
.ADR(addr_bank[i]),
.D(wr_data_bank[i][DCCM_FDATA_WIDTH-1:0]),
.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
.ROP ( ),
// These are used by SoC
`LOCAL_DCCM_RAM_TEST_PORTS
.*
);
end
else if (DCCM_INDEX_DEPTH == 3072) begin : dccm
ram_3072x39 dccm_bank (
// Primary ports
.ME(dccm_clken[i]),
.CLK(clk),
.WE(wren_bank[i]),
.ADR(addr_bank[i]),
.D(wr_data_bank[i][DCCM_FDATA_WIDTH-1:0]),
.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
.ROP ( ),
// These are used by SoC
`LOCAL_DCCM_RAM_TEST_PORTS
.*
);
end
else if (DCCM_INDEX_DEPTH == 2048) begin : dccm
ram_2048x39 dccm_bank (
// Primary ports
.ME(dccm_clken[i]),
.CLK(clk),
.WE(wren_bank[i]),
.ADR(addr_bank[i]),
.D(wr_data_bank[i][DCCM_FDATA_WIDTH-1:0]),
.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
.ROP ( ),
// These are used by SoC
`LOCAL_DCCM_RAM_TEST_PORTS
.*
);
end
else if (DCCM_INDEX_DEPTH == 1024) begin : dccm
ram_1024x39 dccm_bank (
// Primary ports
.ME(dccm_clken[i]),
.CLK(clk),
.WE(wren_bank[i]),
.ADR(addr_bank[i]),
.D(wr_data_bank[i][DCCM_FDATA_WIDTH-1:0]),
.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
.ROP ( ),
// These are used by SoC
`LOCAL_DCCM_RAM_TEST_PORTS
.*
);
end
else if (DCCM_INDEX_DEPTH == 512) begin : dccm
ram_512x39 dccm_bank (
// Primary ports
.ME(dccm_clken[i]),
.CLK(clk),
.WE(wren_bank[i]),
.ADR(addr_bank[i]),
.D(wr_data_bank[i][DCCM_FDATA_WIDTH-1:0]),
.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
.ROP ( ),
// These are used by SoC
`LOCAL_DCCM_RAM_TEST_PORTS
.*
);
end
else if (DCCM_INDEX_DEPTH == 256) begin : dccm
ram_256x39 dccm_bank (
// Primary ports
.ME(dccm_clken[i]),
.CLK(clk),
.WE(wren_bank[i]),
.ADR(addr_bank[i]),
.D(wr_data_bank[i][DCCM_FDATA_WIDTH-1:0]),
.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
.ROP ( ),
// These are used by SoC
`LOCAL_DCCM_RAM_TEST_PORTS
.*
);
end
else if (DCCM_INDEX_DEPTH == 128) begin : dccm
ram_128x39 dccm_bank (
// Primary ports
.ME(dccm_clken[i]),
.CLK(clk),
.WE(wren_bank[i]),
.ADR(addr_bank[i]),
.D(wr_data_bank[i][DCCM_FDATA_WIDTH-1:0]),
.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
.ROP ( ),
// These are used by SoC
`LOCAL_DCCM_RAM_TEST_PORTS
.*
);
end
`endif
end : mem_bank
// Flops
rvdff #(DCCM_BANK_BITS) rd_addr_lo_ff (.*, .din(dccm_rd_addr_lo[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]), .dout(dccm_rd_addr_lo_q[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]), .clk(active_clk));
rvdff #(DCCM_BANK_BITS) rd_addr_hi_ff (.*, .din(dccm_rd_addr_hi[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]), .dout(dccm_rd_addr_hi_q[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]), .clk(active_clk));
`undef LOCAL_DCCM_RAM_TEST_PORTS
endmodule // lsu_dccm_mem

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verif/LEC/LEC_RTL/generated_rtl/mem.sv Normal file
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//********************************************************************************
// SPDX-License-Identifier: Apache-2.0
// Copyright 2020 Western Digital Corporation or its affiliates.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//********************************************************************************
// `include "lsu_dccm_mem.sv"
// `include "ifu_ic_mem.sv"
// `include "ifu_iccm_mem.sv"
module mem
`include "parameter.sv"
(
input logic clk,
input logic rst_l,
input logic dccm_clk_override,
input logic icm_clk_override,
input logic dec_tlu_core_ecc_disable,
//DCCM ports
input logic dccm_wren,
input logic dccm_rden,
input logic [DCCM_BITS-1:0] dccm_wr_addr_lo,
input logic [DCCM_BITS-1:0] dccm_wr_addr_hi,
input logic [DCCM_BITS-1:0] dccm_rd_addr_lo,
input logic [DCCM_BITS-1:0] dccm_rd_addr_hi,
input logic [DCCM_FDATA_WIDTH-1:0] dccm_wr_data_lo,
input logic [DCCM_FDATA_WIDTH-1:0] dccm_wr_data_hi,
output logic [DCCM_FDATA_WIDTH-1:0] dccm_rd_data_lo,
output logic [DCCM_FDATA_WIDTH-1:0] dccm_rd_data_hi,
//`ifdef DCCM_ENABLE
//input dccm_ext_in_pkt_t [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt,
input logic dccm_ext_in_pkt_TEST1_0,
input logic dccm_ext_in_pkt_RME_0,
input logic [3:0] dccm_ext_in_pkt_RM_0,
input logic dccm_ext_in_pkt_LS_0,
input logic dccm_ext_in_pkt_DS_0,
input logic dccm_ext_in_pkt_SD_0,
input logic dccm_ext_in_pkt_TEST_RNM_0,
input logic dccm_ext_in_pkt_BC1_0,
input logic dccm_ext_in_pkt_BC2_0,
input logic dccm_ext_in_pkt_TEST1_1,
input logic dccm_ext_in_pkt_RME_1,
input logic [3:0] dccm_ext_in_pkt_RM_1,
input logic dccm_ext_in_pkt_LS_1,
input logic dccm_ext_in_pkt_DS_1,
input logic dccm_ext_in_pkt_SD_1,
input logic dccm_ext_in_pkt_TEST_RNM_1,
input logic dccm_ext_in_pkt_BC1_1,
input logic dccm_ext_in_pkt_BC2_1,
input logic dccm_ext_in_pkt_TEST1_2,
input logic dccm_ext_in_pkt_RME_2,
input logic [3:0] dccm_ext_in_pkt_RM_2,
input logic dccm_ext_in_pkt_LS_2,
input logic dccm_ext_in_pkt_DS_2,
input logic dccm_ext_in_pkt_SD_2,
input logic dccm_ext_in_pkt_TEST_RNM_2,
input logic dccm_ext_in_pkt_BC1_2,
input logic dccm_ext_in_pkt_BC2_2,
input logic dccm_ext_in_pkt_TEST1_3,
input logic dccm_ext_in_pkt_RME_3,
input logic [3:0] dccm_ext_in_pkt_RM_3,
input logic dccm_ext_in_pkt_LS_3,
input logic dccm_ext_in_pkt_DS_3,
input logic dccm_ext_in_pkt_SD_3,
input logic dccm_ext_in_pkt_TEST_RNM_3,
input logic dccm_ext_in_pkt_BC1_3,
input logic dccm_ext_in_pkt_BC2_3,
//`endif
//ICCM ports
input logic iccm_ext_in_pkt_TEST1_0,
input logic iccm_ext_in_pkt_RME_0,
input logic [3:0] iccm_ext_in_pkt_RM_0,
input logic iccm_ext_in_pkt_LS_0,
input logic iccm_ext_in_pkt_DS_0,
input logic iccm_ext_in_pkt_SD_0,
input logic iccm_ext_in_pkt_TEST_RNM_0,
input logic iccm_ext_in_pkt_BC1_0,
input logic iccm_ext_in_pkt_BC2_0,
input logic iccm_ext_in_pkt_TEST1_1,
input logic iccm_ext_in_pkt_RME_1,
input logic [3:0] iccm_ext_in_pkt_RM_1,
input logic iccm_ext_in_pkt_LS_1,
input logic iccm_ext_in_pkt_DS_1,
input logic iccm_ext_in_pkt_SD_1,
input logic iccm_ext_in_pkt_TEST_RNM_1,
input logic iccm_ext_in_pkt_BC1_1,
input logic iccm_ext_in_pkt_BC2_1,
input logic iccm_ext_in_pkt_TEST1_2,
input logic iccm_ext_in_pkt_RME_2,
input logic [3:0] iccm_ext_in_pkt_RM_2,
input logic iccm_ext_in_pkt_LS_2,
input logic iccm_ext_in_pkt_DS_2,
input logic iccm_ext_in_pkt_SD_2,
input logic iccm_ext_in_pkt_TEST_RNM_2,
input logic iccm_ext_in_pkt_BC1_2,
input logic iccm_ext_in_pkt_BC2_2,
input logic iccm_ext_in_pkt_TEST1_3,
input logic iccm_ext_in_pkt_RME_3,
input logic [3:0] iccm_ext_in_pkt_RM_3,
input logic iccm_ext_in_pkt_LS_3,
input logic iccm_ext_in_pkt_DS_3,
input logic iccm_ext_in_pkt_SD_3,
input logic iccm_ext_in_pkt_TEST_RNM_3,
input logic iccm_ext_in_pkt_BC1_3,
input logic iccm_ext_in_pkt_BC2_3,
input logic [ICCM_BITS-1:1] iccm_rw_addr,
input logic iccm_buf_correct_ecc, // ICCM is doing a single bit error correct cycle
input logic iccm_correction_state, // ICCM is doing a single bit error correct cycle
input logic iccm_wren,
input logic iccm_rden,
input logic [2:0] iccm_wr_size,
input logic [77:0] iccm_wr_data,
output logic [63:0] iccm_rd_data,
output logic [77:0] iccm_rd_data_ecc,
// Icache and Itag Ports
input logic [31:1] ic_rw_addr,
input logic [ICACHE_NUM_WAYS-1:0] ic_tag_valid,
input logic [ICACHE_NUM_WAYS-1:0] ic_wr_en,
input logic ic_rd_en,
input logic [63:0] ic_premux_data, // Premux data to be muxed with each way of the Icache.
input logic ic_sel_premux_data, // Premux data sel
// input ic_data_ext_in_pkt_t [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt,
input logic ic_tag_ext_in_pkt_TEST1_0,
input logic ic_tag_ext_in_pkt_RME_0,
input logic [3:0] ic_tag_ext_in_pkt_RM_0,
input logic ic_tag_ext_in_pkt_LS_0,
input logic ic_tag_ext_in_pkt_DS_0,
input logic ic_tag_ext_in_pkt_SD_0,
input logic ic_tag_ext_in_pkt_TEST_RNM_0,
input logic ic_tag_ext_in_pkt_BC1_0,
input logic ic_tag_ext_in_pkt_BC2_0,
input logic ic_tag_ext_in_pkt_TEST1_1,
input logic ic_tag_ext_in_pkt_RME_1,
input logic [3:0] ic_tag_ext_in_pkt_RM_1,
input logic ic_tag_ext_in_pkt_LS_1,
input logic ic_tag_ext_in_pkt_DS_1,
input logic ic_tag_ext_in_pkt_SD_1,
input logic ic_tag_ext_in_pkt_TEST_RNM_1,
input logic ic_tag_ext_in_pkt_BC1_1,
input logic ic_tag_ext_in_pkt_BC2_1,
input logic ic_data_ext_in_pkt_0_TEST1_0,
input logic ic_data_ext_in_pkt_0_RME_0,
input logic [3:0] ic_data_ext_in_pkt_0_RM_0,
input logic ic_data_ext_in_pkt_0_LS_0,
input logic ic_data_ext_in_pkt_0_DS_0,
input logic ic_data_ext_in_pkt_0_SD_0,
input logic ic_data_ext_in_pkt_0_TEST_RNM_0,
input logic ic_data_ext_in_pkt_0_BC1_0,
input logic ic_data_ext_in_pkt_0_BC2_0,
input logic ic_data_ext_in_pkt_0_TEST1_1,
input logic ic_data_ext_in_pkt_0_RME_1,
input logic [3:0] ic_data_ext_in_pkt_0_RM_1,
input logic ic_data_ext_in_pkt_0_LS_1,
input logic ic_data_ext_in_pkt_0_DS_1,
input logic ic_data_ext_in_pkt_0_SD_1,
input logic ic_data_ext_in_pkt_0_TEST_RNM_1,
input logic ic_data_ext_in_pkt_0_BC1_1,
input logic ic_data_ext_in_pkt_0_BC2_1,
input logic ic_data_ext_in_pkt_1_TEST1_0,
input logic ic_data_ext_in_pkt_1_RME_0,
input logic [3:0] ic_data_ext_in_pkt_1_RM_0,
input logic ic_data_ext_in_pkt_1_LS_0,
input logic ic_data_ext_in_pkt_1_DS_0,
input logic ic_data_ext_in_pkt_1_SD_0,
input logic ic_data_ext_in_pkt_1_TEST_RNM_0,
input logic ic_data_ext_in_pkt_1_BC1_0,
input logic ic_data_ext_in_pkt_1_BC2_0,
input logic ic_data_ext_in_pkt_1_TEST1_1,
input logic ic_data_ext_in_pkt_1_RME_1,
input logic [3:0] ic_data_ext_in_pkt_1_RM_1,
input logic ic_data_ext_in_pkt_1_LS_1,
input logic ic_data_ext_in_pkt_1_DS_1,
input logic ic_data_ext_in_pkt_1_SD_1,
input logic ic_data_ext_in_pkt_1_TEST_RNM_1,
input logic ic_data_ext_in_pkt_1_BC1_1,
input logic ic_data_ext_in_pkt_1_BC2_1,
//input ic_tag_ext_in_pkt_t [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt,
// input logic [ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data, // Data to fill to the Icache. With ECC
input logic [70:0] ic_wr_data_0, // Data to fill to the Icache. With ECC
input logic [70:0] ic_wr_data_1, // Data to fill to the Icache. With ECC
input logic [70:0] ic_debug_wr_data, // Debug wr cache.
output logic [70:0] ic_debug_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
input logic [ICACHE_INDEX_HI:3] ic_debug_addr, // Read/Write addresss to the Icache.
input logic ic_debug_rd_en, // Icache debug rd
input logic ic_debug_wr_en, // Icache debug wr
input logic ic_debug_tag_array, // Debug tag array
input logic [ICACHE_NUM_WAYS-1:0] ic_debug_way, // Debug way. Rd or Wr.
output logic [63:0] ic_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
output logic [25:0] ic_tag_debug_rd_data,// Debug icache tag.
output logic [ICACHE_BANKS_WAY-1:0] ic_eccerr, // ecc error per bank
output logic [ICACHE_BANKS_WAY-1:0] ic_parerr, // parity error per bank
output logic [ICACHE_NUM_WAYS-1:0] ic_rd_hit,
output logic ic_tag_perr, // Icache Tag parity error
input logic scan_mode
);
iccm_ext_in_pkt_t [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt;
dccm_ext_in_pkt_t [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt;
ic_data_ext_in_pkt_t [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt;
ic_tag_ext_in_pkt_t [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt;
assign dccm_ext_in_pkt[0].TEST1 = dccm_ext_in_pkt_TEST1_0;
assign dccm_ext_in_pkt[0].RME = dccm_ext_in_pkt_RME_0;
assign dccm_ext_in_pkt[0].RM = dccm_ext_in_pkt_RM_0[3:0];
assign dccm_ext_in_pkt[0].LS = dccm_ext_in_pkt_LS_0;
assign dccm_ext_in_pkt[0].DS = dccm_ext_in_pkt_DS_0;
assign dccm_ext_in_pkt[0].SD = dccm_ext_in_pkt_SD_0;
assign dccm_ext_in_pkt[0].TEST_RNM = dccm_ext_in_pkt_TEST_RNM_0;
assign dccm_ext_in_pkt[0].BC1 = dccm_ext_in_pkt_BC1_0;
assign dccm_ext_in_pkt[0].BC2 = dccm_ext_in_pkt_BC2_0;
assign dccm_ext_in_pkt[1].TEST1 = dccm_ext_in_pkt_TEST1_1;
assign dccm_ext_in_pkt[1].RME = dccm_ext_in_pkt_RME_1;
assign dccm_ext_in_pkt[1].RM = dccm_ext_in_pkt_RM_1[3:0];
assign dccm_ext_in_pkt[1].LS = dccm_ext_in_pkt_LS_1;
assign dccm_ext_in_pkt[1].DS = dccm_ext_in_pkt_DS_1;
assign dccm_ext_in_pkt[1].SD = dccm_ext_in_pkt_SD_1;
assign dccm_ext_in_pkt[1].TEST_RNM = dccm_ext_in_pkt_TEST_RNM_1;
assign dccm_ext_in_pkt[1].BC1 = dccm_ext_in_pkt_BC1_1;
assign dccm_ext_in_pkt[1].BC2 = dccm_ext_in_pkt_BC2_1;
assign dccm_ext_in_pkt[2].TEST1 = dccm_ext_in_pkt_TEST1_2;
assign dccm_ext_in_pkt[2].RME = dccm_ext_in_pkt_RME_2;
assign dccm_ext_in_pkt[2].RM = dccm_ext_in_pkt_RM_2[3:0];
assign dccm_ext_in_pkt[2].LS = dccm_ext_in_pkt_LS_2;
assign dccm_ext_in_pkt[2].DS = dccm_ext_in_pkt_DS_2;
assign dccm_ext_in_pkt[2].SD = dccm_ext_in_pkt_SD_2;
assign dccm_ext_in_pkt[2].TEST_RNM = dccm_ext_in_pkt_TEST_RNM_2;
assign dccm_ext_in_pkt[2].BC1 = dccm_ext_in_pkt_BC1_2;
assign dccm_ext_in_pkt[2].BC2 = dccm_ext_in_pkt_BC2_2;
assign dccm_ext_in_pkt[3].TEST1 = dccm_ext_in_pkt_TEST1_3;
assign dccm_ext_in_pkt[3].RME = dccm_ext_in_pkt_RME_3;
assign dccm_ext_in_pkt[3].RM = dccm_ext_in_pkt_RM_3[3:0];
assign dccm_ext_in_pkt[3].LS = dccm_ext_in_pkt_LS_3;
assign dccm_ext_in_pkt[3].DS = dccm_ext_in_pkt_DS_3;
assign dccm_ext_in_pkt[3].SD = dccm_ext_in_pkt_SD_3;
assign dccm_ext_in_pkt[3].TEST_RNM = dccm_ext_in_pkt_TEST_RNM_3;
assign dccm_ext_in_pkt[3].BC1 = dccm_ext_in_pkt_BC1_3;
assign dccm_ext_in_pkt[3].BC2 = dccm_ext_in_pkt_BC2_3;
assign iccm_ext_in_pkt[0].TEST1 = iccm_ext_in_pkt_TEST1_0;
assign iccm_ext_in_pkt[0].RME = iccm_ext_in_pkt_RME_0;
assign iccm_ext_in_pkt[0].RM = iccm_ext_in_pkt_RM_0[3:0];
assign iccm_ext_in_pkt[0].LS = iccm_ext_in_pkt_LS_0;
assign iccm_ext_in_pkt[0].DS = iccm_ext_in_pkt_DS_0;
assign iccm_ext_in_pkt[0].SD = iccm_ext_in_pkt_SD_0;
assign iccm_ext_in_pkt[0].TEST_RNM = iccm_ext_in_pkt_TEST_RNM_0;
assign iccm_ext_in_pkt[0].BC1 = iccm_ext_in_pkt_BC1_0;
assign iccm_ext_in_pkt[0].BC2 = iccm_ext_in_pkt_BC2_0;
assign iccm_ext_in_pkt[1].TEST1 = iccm_ext_in_pkt_TEST1_1;
assign iccm_ext_in_pkt[1].RME = iccm_ext_in_pkt_RME_1;
assign iccm_ext_in_pkt[1].RM = iccm_ext_in_pkt_RM_1[3:0];
assign iccm_ext_in_pkt[1].LS = iccm_ext_in_pkt_LS_1;
assign iccm_ext_in_pkt[1].DS = iccm_ext_in_pkt_DS_1;
assign iccm_ext_in_pkt[1].SD = iccm_ext_in_pkt_SD_1;
assign iccm_ext_in_pkt[1].TEST_RNM = iccm_ext_in_pkt_TEST_RNM_1;
assign iccm_ext_in_pkt[1].BC1 = iccm_ext_in_pkt_BC1_1;
assign iccm_ext_in_pkt[1].BC2 = iccm_ext_in_pkt_BC2_1;
assign iccm_ext_in_pkt[2].TEST1 = iccm_ext_in_pkt_TEST1_2;
assign iccm_ext_in_pkt[2].RME = iccm_ext_in_pkt_RME_2;
assign iccm_ext_in_pkt[2].RM = iccm_ext_in_pkt_RM_2[3:0];
assign iccm_ext_in_pkt[2].LS = iccm_ext_in_pkt_LS_2;
assign iccm_ext_in_pkt[2].DS = iccm_ext_in_pkt_DS_2;
assign iccm_ext_in_pkt[2].SD = iccm_ext_in_pkt_SD_2;
assign iccm_ext_in_pkt[2].TEST_RNM = iccm_ext_in_pkt_TEST_RNM_2;
assign iccm_ext_in_pkt[2].BC1 = iccm_ext_in_pkt_BC1_2;
assign iccm_ext_in_pkt[2].BC2 = iccm_ext_in_pkt_BC2_2;
assign iccm_ext_in_pkt[3].TEST1 = iccm_ext_in_pkt_TEST1_3;
assign iccm_ext_in_pkt[3].RME = iccm_ext_in_pkt_RME_3;
assign iccm_ext_in_pkt[3].RM = iccm_ext_in_pkt_RM_3[3:0];
assign iccm_ext_in_pkt[3].LS = iccm_ext_in_pkt_LS_3;
assign iccm_ext_in_pkt[3].DS = iccm_ext_in_pkt_DS_3;
assign iccm_ext_in_pkt[3].SD = iccm_ext_in_pkt_SD_3;
assign iccm_ext_in_pkt[3].TEST_RNM = iccm_ext_in_pkt_TEST_RNM_3;
assign iccm_ext_in_pkt[3].BC1 = iccm_ext_in_pkt_BC1_3;
assign iccm_ext_in_pkt[3].BC2 = iccm_ext_in_pkt_BC2_3;
assign ic_tag_ext_in_pkt[0].TEST1 = ic_tag_ext_in_pkt_TEST1_0;
assign ic_tag_ext_in_pkt[0].RME = ic_tag_ext_in_pkt_RME_0;
assign ic_tag_ext_in_pkt[0].RM = ic_tag_ext_in_pkt_RM_0[3:0];
assign ic_tag_ext_in_pkt[0].LS = ic_tag_ext_in_pkt_LS_0;
assign ic_tag_ext_in_pkt[0].DS = ic_tag_ext_in_pkt_DS_0;
assign ic_tag_ext_in_pkt[0].SD = ic_tag_ext_in_pkt_SD_0;
assign ic_tag_ext_in_pkt[0].TEST_RNM = ic_tag_ext_in_pkt_TEST_RNM_0;
assign ic_tag_ext_in_pkt[0].BC1 = ic_tag_ext_in_pkt_BC1_0;
assign ic_tag_ext_in_pkt[0].BC2 = ic_tag_ext_in_pkt_BC2_0;
assign ic_tag_ext_in_pkt[1].TEST1 = ic_tag_ext_in_pkt_TEST1_1;
assign ic_tag_ext_in_pkt[1].RME = ic_tag_ext_in_pkt_RME_1;
assign ic_tag_ext_in_pkt[1].RM = ic_tag_ext_in_pkt_RM_1[3:0];
assign ic_tag_ext_in_pkt[1].LS = ic_tag_ext_in_pkt_LS_1;
assign ic_tag_ext_in_pkt[1].DS = ic_tag_ext_in_pkt_DS_1;
assign ic_tag_ext_in_pkt[1].SD = ic_tag_ext_in_pkt_SD_1;
assign ic_tag_ext_in_pkt[1].TEST_RNM = ic_tag_ext_in_pkt_TEST_RNM_1;
assign ic_tag_ext_in_pkt[1].BC1 = ic_tag_ext_in_pkt_BC1_1;
assign ic_tag_ext_in_pkt[1].BC2 = ic_tag_ext_in_pkt_BC2_1;
// PKT connection
assign ic_data_ext_in_pkt[0][0].TEST1 = ic_data_ext_in_pkt_0_TEST1_0;
assign ic_data_ext_in_pkt[0][0].RME = ic_data_ext_in_pkt_0_RME_0;
assign ic_data_ext_in_pkt[0][0].RM = ic_data_ext_in_pkt_0_RM_0[3:0];
assign ic_data_ext_in_pkt[0][0].LS = ic_data_ext_in_pkt_0_LS_0;
assign ic_data_ext_in_pkt[0][0].DS = ic_data_ext_in_pkt_0_DS_0;
assign ic_data_ext_in_pkt[0][0].SD = ic_data_ext_in_pkt_0_SD_0;
assign ic_data_ext_in_pkt[0][0].TEST_RNM = ic_data_ext_in_pkt_0_TEST_RNM_0;
assign ic_data_ext_in_pkt[0][0].BC1 = ic_data_ext_in_pkt_0_BC1_0;
assign ic_data_ext_in_pkt[0][0].BC2 = ic_data_ext_in_pkt_0_BC2_0;
assign ic_data_ext_in_pkt[0][1].TEST1 = ic_data_ext_in_pkt_1_TEST1_1;
assign ic_data_ext_in_pkt[0][1].RME = ic_data_ext_in_pkt_1_RME_1;
assign ic_data_ext_in_pkt[0][1].RM = ic_data_ext_in_pkt_1_RM_1[3:0];
assign ic_data_ext_in_pkt[0][1].LS = ic_data_ext_in_pkt_1_LS_1;
assign ic_data_ext_in_pkt[0][1].DS = ic_data_ext_in_pkt_1_DS_1;
assign ic_data_ext_in_pkt[0][1].SD = ic_data_ext_in_pkt_1_SD_1;
assign ic_data_ext_in_pkt[0][1].TEST_RNM = ic_data_ext_in_pkt_1_TEST_RNM_1;
assign ic_data_ext_in_pkt[0][1].BC1 = ic_data_ext_in_pkt_1_BC1_1;
assign ic_data_ext_in_pkt[0][1].BC2 = ic_data_ext_in_pkt_1_BC2_1;
assign ic_data_ext_in_pkt[1][0].TEST1 = ic_data_ext_in_pkt_1_TEST1_0;
assign ic_data_ext_in_pkt[1][0].RME = ic_data_ext_in_pkt_1_RME_0;
assign ic_data_ext_in_pkt[1][0].RM = ic_data_ext_in_pkt_1_RM_0[3:0];
assign ic_data_ext_in_pkt[1][0].LS = ic_data_ext_in_pkt_1_LS_0;
assign ic_data_ext_in_pkt[1][0].DS = ic_data_ext_in_pkt_1_DS_0;
assign ic_data_ext_in_pkt[1][0].SD = ic_data_ext_in_pkt_1_SD_0;
assign ic_data_ext_in_pkt[1][0].TEST_RNM = ic_data_ext_in_pkt_1_TEST_RNM_0;
assign ic_data_ext_in_pkt[1][0].BC1 = ic_data_ext_in_pkt_1_BC1_0;
assign ic_data_ext_in_pkt[1][0].BC2 = ic_data_ext_in_pkt_1_BC2_0;
assign ic_data_ext_in_pkt[1][1].TEST1 = ic_data_ext_in_pkt_1_TEST1_1;
assign ic_data_ext_in_pkt[1][1].RME = ic_data_ext_in_pkt_1_RME_1;
assign ic_data_ext_in_pkt[1][1].RM = ic_data_ext_in_pkt_1_RM_1[3:0];
assign ic_data_ext_in_pkt[1][1].LS = ic_data_ext_in_pkt_1_LS_1;
assign ic_data_ext_in_pkt[1][1].DS = ic_data_ext_in_pkt_1_DS_1;
assign ic_data_ext_in_pkt[1][1].SD = ic_data_ext_in_pkt_1_SD_1;
assign ic_data_ext_in_pkt[1][1].TEST_RNM = ic_data_ext_in_pkt_1_TEST_RNM_1;
assign ic_data_ext_in_pkt[1][1].BC1 = ic_data_ext_in_pkt_1_BC1_1;
assign ic_data_ext_in_pkt[1][1].BC2 = ic_data_ext_in_pkt_1_BC2_1;
rvoclkhdr active_cg ( .en(1'b1), .l1clk(active_clk), .* );
// DCCM Instantiation
if (DCCM_ENABLE == 1) begin: Gen_dccm_enable
lsu_dccm_mem #(
.DCCM_BYTE_WIDTH(DCCM_BYTE_WIDTH),
.DCCM_BITS(DCCM_BITS),
.DCCM_NUM_BANKS(DCCM_NUM_BANKS),
.DCCM_BANK_BITS(DCCM_BANK_BITS),
.DCCM_SIZE(DCCM_SIZE),
.DCCM_FDATA_WIDTH(DCCM_FDATA_WIDTH),
.DCCM_WIDTH_BITS(DCCM_WIDTH_BITS)) dccm (
.clk_override(dccm_clk_override),
.*
);
end else begin: Gen_dccm_disable
assign dccm_rd_data_lo = '0;
assign dccm_rd_data_hi = '0;
end
if ( ICACHE_ENABLE ) begin: icache
ifu_ic_mem #(
.ICACHE_BEAT_BITS(ICACHE_BEAT_BITS),
.ICACHE_NUM_WAYS(ICACHE_NUM_WAYS),
.ICACHE_BANK_BITS(ICACHE_BANK_BITS),
.ICACHE_BEAT_ADDR_HI(ICACHE_BEAT_ADDR_HI),
.ICACHE_BANKS_WAY(ICACHE_BANKS_WAY),
.ICACHE_INDEX_HI(ICACHE_INDEX_HI),
.ICACHE_BANK_HI(ICACHE_BANK_HI),
.ICACHE_BANK_LO(ICACHE_BANK_LO),
.ICACHE_TAG_LO(ICACHE_TAG_LO),
.ICACHE_DATA_INDEX_LO(ICACHE_DATA_INDEX_LO),
.ICACHE_ECC(ICACHE_ECC),
.ICACHE_TAG_DEPTH(ICACHE_TAG_DEPTH),
.ICACHE_WAYPACK(ICACHE_WAYPACK),
.ICACHE_TAG_INDEX_LO(ICACHE_TAG_INDEX_LO),
.ICACHE_DATA_DEPTH(ICACHE_DATA_DEPTH),
.ICACHE_TAG_NUM_BYPASS(ICACHE_TAG_NUM_BYPASS),
.ICACHE_TAG_NUM_BYPASS_WIDTH(ICACHE_TAG_NUM_BYPASS_WIDTH),
.ICACHE_TAG_BYPASS_ENABLE(ICACHE_TAG_BYPASS_ENABLE),
.ICACHE_NUM_BYPASS_WIDTH(ICACHE_NUM_BYPASS_WIDTH),
.ICACHE_BYPASS_ENABLE(ICACHE_BYPASS_ENABLE),
.ICACHE_LN_SZ(ICACHE_LN_SZ)) icm (
.clk_override(icm_clk_override),
.*
);
end
else begin
assign ic_rd_hit[ICACHE_NUM_WAYS-1:0] = '0;
assign ic_tag_perr = '0 ;
assign ic_rd_data = '0 ;
assign ic_tag_debug_rd_data = '0 ;
end // else: !if( ICACHE_ENABLE )
if (ICCM_ENABLE) begin : iccm
ifu_iccm_mem #(
.ICCM_BITS(ICCM_BITS),
.ICCM_BANK_INDEX_LO(ICCM_BANK_INDEX_LO),
.ICCM_INDEX_BITS(ICCM_INDEX_BITS),
.ICCM_BANK_HI(ICCM_BANK_HI),
.ICCM_NUM_BANKS(ICCM_NUM_BANKS),
.ICCM_BANK_BITS(ICCM_BANK_BITS)) iccm (.*,
.clk_override(icm_clk_override),
.iccm_rw_addr(iccm_rw_addr[ICCM_BITS-1:1]),
.iccm_rd_data(iccm_rd_data[63:0])
);
end
else begin
assign iccm_rd_data = '0 ;
assign iccm_rd_data_ecc = '0 ;
end
endmodule

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// SPDX-License-Identifier: Apache-2.0
// Copyright 2020 Western Digital Corporation or it's affiliates.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
`define LOCAL_RAM_TEST_IO \
input logic WE, \
input logic ME, \
input logic CLK, \
input logic TEST1, \
input logic RME, \
input logic [3:0] RM, \
input logic LS, \
input logic DS, \
input logic SD, \
input logic TEST_RNM, \
input logic BC1, \
input logic BC2, \
output logic ROP
`define RAM(depth, width) \
module ram_``depth``x``width( \
input logic [$clog2(depth)-1:0] ADR, \
input logic [(width-1):0] D, \
output logic [(width-1):0] Q, \
`LOCAL_RAM_TEST_IO \
); \
reg [(width-1):0] ram_core [(depth-1):0]; \
`ifdef GTLSIM \
integer i; \
initial begin \
for (i=0; i<depth; i=i+1) \
ram_core[i] = '0; \
end \
`endif \
always @(posedge CLK) begin \
`ifdef GTLSIM \
if (ME && WE) ram_core[ADR] <= D; \
`else \
if (ME && WE) begin ram_core[ADR] <= D; Q <= 'x; end \
`endif \
if (ME && ~WE) Q <= ram_core[ADR]; \
end \
assign ROP = ME; \
\
endmodule
`define RAM_BE(depth, width) \
module ram_be_``depth``x``width( \
input logic [$clog2(depth)-1:0] ADR, \
input logic [(width-1):0] D, WEM, \
output logic [(width-1):0] Q, \
`LOCAL_RAM_TEST_IO \
); \
reg [(width-1):0] ram_core [(depth-1):0]; \
`ifdef GTLSIM \
integer i; \
initial begin \
for (i=0; i<depth; i=i+1) \
ram_core[i] = '0; \
end \
`endif \
always @(posedge CLK) begin \
`ifdef GTLSIM \
if (ME && WE) ram_core[ADR] <= D & WEM | ~WEM & ram_core[ADR]; \
`else \
if (ME && WE) begin ram_core[ADR] <= D & WEM | ~WEM & ram_core[ADR]; Q <= 'x; end \
`endif \
if (ME && ~WE) Q <= ram_core[ADR]; \
end \
assign ROP = ME; \
\
endmodule
// parameterizable RAM for verilator sims
module ram #(depth=4096, width=39) (
input logic [$clog2(depth)-1:0] ADR,
input logic [(width-1):0] D,
output logic [(width-1):0] Q,
`LOCAL_RAM_TEST_IO
);
reg [(width-1):0] ram_core [(depth-1):0];
always @(posedge CLK) begin
`ifdef GTLSIM
if (ME && WE) ram_core[ADR] <= D;
`else
if (ME && WE) begin ram_core[ADR] <= D; Q <= 'x; end
`endif
if (ME && ~WE) Q <= ram_core[ADR];
end
endmodule
//=========================================================================================================================
//=================================== START OF CCM =======================================================================
//============= Possible sram sizes for a 39 bit wide memory ( 4 bytes + 7 bits ECC ) =====================================
//-------------------------------------------------------------------------------------------------------------------------
`RAM(32768, 39)
`RAM(16384, 39)
`RAM(8192, 39)
`RAM(4096, 39)
`RAM(3072, 39)
`RAM(2048, 39)
`RAM(1536, 39) // need this for the 48KB DCCM option)
`RAM(1024, 39)
`RAM(768, 39)
`RAM(512, 39)
`RAM(256, 39)
`RAM(128, 39)
`RAM(1024, 20)
`RAM(512, 20)
`RAM(256, 20)
`RAM(128, 20)
`RAM(64, 20)
`RAM(4096, 34)
`RAM(2048, 34)
`RAM(1024, 34)
`RAM(512, 34)
`RAM(256, 34)
`RAM(128, 34)
`RAM(64, 34)
`RAM(8192, 68)
`RAM(4096, 68)
`RAM(2048, 68)
`RAM(1024, 68)
`RAM(512, 68)
`RAM(256, 68)
`RAM(128, 68)
`RAM(64, 68)
`RAM(8192, 71)
`RAM(4096, 71)
`RAM(2048, 71)
`RAM(1024, 71)
`RAM(512, 71)
`RAM(256, 71)
`RAM(128, 71)
`RAM(64, 71)
`RAM(4096, 42)
`RAM(2048, 42)
`RAM(1024, 42)
`RAM(512, 42)
`RAM(256, 42)
`RAM(128, 42)
`RAM(64, 42)
`RAM(4096, 22)
`RAM(2048, 22)
`RAM(1024, 22)
`RAM(512, 22)
`RAM(256, 22)
`RAM(128, 22)
`RAM(64, 22)
`RAM(1024, 26)
`RAM(4096, 26)
`RAM(2048, 26)
`RAM(512, 26)
`RAM(256, 26)
`RAM(128, 26)
`RAM(64, 26)
`RAM(32, 26)
`RAM(32, 22)
`RAM_BE(8192, 142)
`RAM_BE(4096, 142)
`RAM_BE(2048, 142)
`RAM_BE(1024, 142)
`RAM_BE(512, 142)
`RAM_BE(256, 142)
`RAM_BE(128, 142)
`RAM_BE(64, 142)
`RAM_BE(8192, 284)
`RAM_BE(4096, 284)
`RAM_BE(2048, 284)
`RAM_BE(1024, 284)
`RAM_BE(512, 284)
`RAM_BE(256, 284)
`RAM_BE(128, 284)
`RAM_BE(64, 284)
`RAM_BE(8192, 136)
`RAM_BE(4096, 136)
`RAM_BE(2048, 136)
`RAM_BE(1024, 136)
`RAM_BE(512, 136)
`RAM_BE(256, 136)
`RAM_BE(128, 136)
`RAM_BE(64, 136)
`RAM_BE(8192, 272)
`RAM_BE(4096, 272)
`RAM_BE(2048, 272)
`RAM_BE(1024, 272)
`RAM_BE(512, 272)
`RAM_BE(256, 272)
`RAM_BE(128, 272)
`RAM_BE(64, 272)
`RAM_BE(4096, 52)
`RAM_BE(2048, 52)
`RAM_BE(1024, 52)
`RAM_BE(512, 52)
`RAM_BE(256, 52)
`RAM_BE(128, 52)
`RAM_BE(64, 52)
`RAM_BE(32, 52)
`RAM_BE(4096, 104)
`RAM_BE(2048, 104)
`RAM_BE(1024, 104)
`RAM_BE(512, 104)
`RAM_BE(256, 104)
`RAM_BE(128, 104)
`RAM_BE(64, 104)
`RAM_BE(32, 104)
`RAM_BE(4096, 44)
`RAM_BE(2048, 44)
`RAM_BE(1024, 44)
`RAM_BE(512, 44)
`RAM_BE(256, 44)
`RAM_BE(128, 44)
`RAM_BE(64, 44)
`RAM_BE(32, 44)
`RAM_BE(4096, 88)
`RAM_BE(2048, 88)
`RAM_BE(1024, 88)
`RAM_BE(512, 88)
`RAM_BE(256, 88)
`RAM_BE(128, 88)
`RAM_BE(64, 88)
`RAM_BE(32, 88)
`RAM(64, 39)
`undef RAM
`undef RAM_BE
`undef LOCAL_RAM_TEST_IO

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#(parameter AWIDTH = 7,
TAG = 1'h1,
BHT_ADDR_HI = 4'h9,
BHT_ADDR_LO = 2'h2,
BHT_ARRAY_DEPTH = 11'h100,
BHT_GHR_HASH_1 = 1'h0,
BHT_GHR_SIZE = 4'h8,
BHT_SIZE = 12'h200,
BTB_ADDR_HI = 5'h09,
BTB_ADDR_LO = 2'h2,
BTB_ARRAY_DEPTH = 9'h100,
BTB_BTAG_FOLD = 1'h0,
BTB_BTAG_SIZE = 4'h5,
BTB_FOLD2_INDEX_HASH = 1'h0,
BTB_INDEX1_HI = 5'h09,
BTB_INDEX1_LO = 5'h02,
BTB_INDEX2_HI = 5'h11,
BTB_INDEX2_LO = 5'h0A,
BTB_INDEX3_HI = 5'h19,
BTB_INDEX3_LO = 5'h12,
BTB_SIZE = 10'h200,
BUILD_AHB_LITE = 1'h0,
BUILD_AXI4 = 1'h1,
BUILD_AXI_NATIVE = 1'h1,
BUS_PRTY_DEFAULT = 2'h3,
DATA_ACCESS_ADDR0 = 32'h00000000,
DATA_ACCESS_ADDR1 = 32'h00000000,
DATA_ACCESS_ADDR2 = 32'h00000000,
DATA_ACCESS_ADDR3 = 32'h00000000,
DATA_ACCESS_ADDR4 = 32'h00000000,
DATA_ACCESS_ADDR5 = 32'h00000000,
DATA_ACCESS_ADDR6 = 32'h00000000,
DATA_ACCESS_ADDR7 = 32'h00000000,
DATA_ACCESS_ENABLE0 = 1'h0,
DATA_ACCESS_ENABLE1 = 1'h0,
DATA_ACCESS_ENABLE2 = 1'h0,
DATA_ACCESS_ENABLE3 = 1'h0,
DATA_ACCESS_ENABLE4 = 1'h0,
DATA_ACCESS_ENABLE5 = 1'h0,
DATA_ACCESS_ENABLE6 = 1'h0,
DATA_ACCESS_ENABLE7 = 1'h0,
DATA_ACCESS_MASK0 = 32'h0FFFFFFF,
DATA_ACCESS_MASK1 = 32'h0FFFFFFF,
DATA_ACCESS_MASK2 = 32'h0FFFFFFF,
DATA_ACCESS_MASK3 = 32'h0FFFFFFF,
DATA_ACCESS_MASK4 = 32'h0FFFFFFF,
DATA_ACCESS_MASK5 = 32'h0FFFFFFF,
DATA_ACCESS_MASK6 = 32'h0FFFFFFF,
DATA_ACCESS_MASK7 = 32'h0FFFFFFF,
DCCM_BANK_BITS = 3'h2,
DCCM_BITS = 5'h10,
DCCM_BYTE_WIDTH = 3'h4,
DCCM_DATA_WIDTH = 6'h20,
DCCM_ECC_WIDTH = 3'h7,
DCCM_ENABLE = 1'h1,
DCCM_FDATA_WIDTH = 6'h27,
//DCCM_INDEX_BITS = 4'hC,
DCCM_NUM_BANKS = 5'h04,
DCCM_REGION = 4'hF,
DCCM_SADR = 32'hF0040000,
DCCM_SIZE = 10'h040,
DCCM_WIDTH_BITS = 2'h2,
DMA_BUF_DEPTH = 3'h5,
DMA_BUS_ID = 1'h1,
DMA_BUS_PRTY = 2'h2,
DMA_BUS_TAG = 4'h1,
FAST_INTERRUPT_REDIRECT = 1'h1,
ICACHE_2BANKS = 1'h1,
ICACHE_BANK_BITS = 3'h1,
ICACHE_BANK_HI = 3'h3,
ICACHE_BANK_LO = 2'h3,
ICACHE_BANK_WIDTH = 4'h8,
ICACHE_BANKS_WAY = 3'h2,
ICACHE_BEAT_ADDR_HI = 4'h5,
ICACHE_BEAT_BITS = 4'h3,
ICACHE_DATA_DEPTH = 14'h0200,
ICACHE_DATA_INDEX_LO = 3'h4,
ICACHE_DATA_WIDTH = 7'h40,
ICACHE_ECC = 1'h1,
ICACHE_ENABLE = 1'h1,
ICACHE_FDATA_WIDTH = 7'h47,
ICACHE_INDEX_HI = 5'h0C,
ICACHE_LN_SZ = 7'h40,
ICACHE_NUM_BEATS = 4'h8,
ICACHE_NUM_WAYS = 3'h2,
ICACHE_ONLY = 1'h0,
ICACHE_SCND_LAST = 4'h6,
ICACHE_SIZE = 9'h010,
ICACHE_STATUS_BITS = 3'h1,
ICACHE_TAG_DEPTH = 13'h0080,
ICACHE_TAG_INDEX_LO = 3'h6,
ICACHE_TAG_LO = 5'h0D,
ICACHE_WAYPACK = 1'h0,
ICCM_BANK_BITS = 3'h2,
ICCM_BANK_HI = 5'h03,
ICCM_BANK_INDEX_LO = 5'h04,
ICCM_BITS = 5'h10,
ICCM_ENABLE = 1'h1,
ICCM_ICACHE = 1'h1,
ICCM_INDEX_BITS = 4'hC,
ICCM_NUM_BANKS = 5'h04,
ICCM_ONLY = 1'h0,
ICCM_REGION = 4'hE,
ICCM_SADR = 32'hEE000000,
ICCM_SIZE = 10'h040,
IFU_BUS_ID = 1'h1,
IFU_BUS_PRTY = 2'h2,
IFU_BUS_TAG = 4'h3,
INST_ACCESS_ADDR0 = 32'h00000000,
INST_ACCESS_ADDR1 = 32'h00000000,
INST_ACCESS_ADDR2 = 32'h00000000,
INST_ACCESS_ADDR3 = 32'h00000000,
INST_ACCESS_ADDR4 = 32'h00000000,
INST_ACCESS_ADDR5 = 32'h00000000,
INST_ACCESS_ADDR6 = 32'h00000000,
INST_ACCESS_ADDR7 = 32'h00000000,
INST_ACCESS_ENABLE0 = 1'h0,
INST_ACCESS_ENABLE1 = 1'h0,
INST_ACCESS_ENABLE2 = 1'h0,
INST_ACCESS_ENABLE3 = 1'h0,
INST_ACCESS_ENABLE4 = 1'h0,
INST_ACCESS_ENABLE5 = 1'h0,
INST_ACCESS_ENABLE6 = 1'h0,
INST_ACCESS_ENABLE7 = 1'h0,
INST_ACCESS_MASK0 = 32'h0FFFFFFF,
INST_ACCESS_MASK1 = 32'h0FFFFFFF,
INST_ACCESS_MASK2 = 32'h0FFFFFFF,
INST_ACCESS_MASK3 = 32'h0FFFFFFF,
INST_ACCESS_MASK4 = 32'h0FFFFFFF,
INST_ACCESS_MASK5 = 32'h0FFFFFFF,
INST_ACCESS_MASK6 = 32'h0FFFFFFF,
INST_ACCESS_MASK7 = 32'h0FFFFFFF,
LOAD_TO_USE_PLUS1 = 1'h0,
LSU2DMA = 1'h0,
LSU_BUS_ID = 1'h1,
LSU_BUS_PRTY = 2'h2,
LSU_BUS_TAG = 4'h3,
LSU_NUM_NBLOAD = 5'h04,
LSU_NUM_NBLOAD_WIDTH = 3'h2,
LSU_SB_BITS = 5'h10,
LSU_STBUF_DEPTH = 4'h4,
NO_ICCM_NO_ICACHE = 1'h0,
PIC_2CYCLE = 1'h0,
PIC_BASE_ADDR = 32'hF00C0000,
PIC_BITS = 5'h0F,
PIC_INT_WORDS = 4'h1,
PIC_REGION = 4'hF,
PIC_SIZE = 9'h020,
PIC_TOTAL_INT = 8'h1F,
PIC_TOTAL_INT_PLUS1 = 9'h020,
RET_STACK_SIZE = 4'h8,
SB_BUS_ID = 1'h1,
SB_BUS_PRTY = 2'h2,
SB_BUS_TAG = 4'h1,
TIMER_LEGAL_EN = 1'h1,
RV_FPGA_OPTIMIZE = 5'h01,
DIV_NEW = 5'h01,
DIV_BIT = 7'h04,
BTB_ENABLE = 5'h01,
BTB_TOFFSET_SIZE = 9'h00C,
BTB_FULLYA = 5'h00,
BITMANIP_ZBA = 5'h00 ,
BITMANIP_ZBB = 5'h01 ,
BITMANIP_ZBC = 5'h00 ,
BITMANIP_ZBE = 5'h00 ,
BITMANIP_ZBF = 5'h00 ,
BITMANIP_ZBP = 5'h00 ,
BITMANIP_ZBR = 5'h00 ,
BITMANIP_ZBS = 5'h01 ,
ICACHE_BYPASS_ENABLE = 5'h01,
ICACHE_NUM_BYPASS = 8'h02,
ICACHE_NUM_BYPASS_WIDTH = 8'h02,
ICACHE_TAG_BYPASS_ENABLE = 5'h01,
ICACHE_TAG_NUM_BYPASS = 8'h02,
ICACHE_TAG_NUM_BYPASS_WIDTH = 8'h02
)

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typedef struct packed {
logic trace_rv_i_valid_ip;
logic [31:0] trace_rv_i_insn_ip;
logic [31:0] trace_rv_i_address_ip;
logic trace_rv_i_exception_ip;
logic [4:0] trace_rv_i_ecause_ip;
logic trace_rv_i_interrupt_ip;
logic [31:0] trace_rv_i_tval_ip;
} trace_pkt_t;
typedef enum logic [3:0] {
NULL = 4'b0000,
MUL = 4'b0001,
LOAD = 4'b0010,
STORE = 4'b0011,
ALU = 4'b0100,
CSRREAD = 4'b0101,
CSRWRITE = 4'b0110,
CSRRW = 4'b0111,
EBREAK = 4'b1000,
ECALL = 4'b1001,
FENCE = 4'b1010,
FENCEI = 4'b1011,
MRET = 4'b1100,
CONDBR = 4'b1101,
JAL = 4'b1110,
BITMANIPU = 4'b1111
} inst_pkt_t;
typedef struct packed {
logic valid;
logic wb;
logic [2:0] tag;
logic [4:0] rd;
} load_cam_pkt_t;
typedef struct packed {
logic pc0_call;
logic pc0_ret;
logic pc0_pc4;
} rets_pkt_t;
typedef struct packed {
logic valid;
logic [11:0] toffset;
logic [1:0] hist;
logic br_error;
logic br_start_error;
logic bank;
logic [31:1] prett; // predicted ret target
logic way;
logic ret;
} br_pkt_t;
typedef struct packed {
logic valid;
logic [1:0] hist;
logic br_error;
logic br_start_error;
logic way;
logic middle;
} br_tlu_pkt_t;
typedef struct packed {
logic misp;
logic ataken;
logic boffset;
logic pc4;
logic [1:0] hist;
logic [11:0] toffset;
logic valid;
logic br_error;
logic br_start_error;
logic pcall;
logic pja;
logic way;
logic pret;
// for power use the pret bit to clock the prett field
logic [31:1] prett;
} predict_pkt_t;
typedef struct packed {
// unlikely to change
logic icaf;
logic icaf_second;
logic [1:0] icaf_type;
logic fence_i;
logic [3:0] i0trigger;
logic pmu_i0_br_unpred; // pmu
logic pmu_divide;
// likely to change
logic legal;
logic pmu_lsu_misaligned;
inst_pkt_t pmu_i0_itype; // pmu - instruction type
} trap_pkt_t;
typedef struct packed {
// unlikely to change
logic i0div;
logic csrwen;
logic csrwonly;
logic [11:0] csrwaddr;
// likely to change
logic [4:0] i0rd;
logic i0load;
logic i0store;
logic i0v;
logic i0valid;
} dest_pkt_t;
typedef struct packed {
logic mul;
logic load;
logic alu;
} class_pkt_t;
typedef struct packed {
logic [4:0] rs1;
logic [4:0] rs2;
logic [4:0] rd;
} reg_pkt_t;
typedef struct packed {
logic clz;
logic ctz;
logic pcnt;
logic sext_b;
logic sext_h;
logic slo;
logic sro;
logic min;
logic max;
logic pack;
logic packu;
logic packh;
logic rol;
logic ror;
logic grev;
logic gorc;
logic zbb;
logic sbset;
logic sbclr;
logic sbinv;
logic sbext;
logic sh1add;
logic sh2add;
logic sh3add;
logic zba;
logic land;
logic lor;
logic lxor;
logic sll;
logic srl;
logic sra;
logic beq;
logic bne;
logic blt;
logic bge;
logic add;
logic sub;
logic slt;
logic unsign;
logic jal;
logic predict_t;
logic predict_nt;
logic csr_write;
logic csr_imm;
} alu_pkt_t;
typedef struct packed {
logic fast_int;
/* verilator lint_off SYMRSVDWORD */
logic stack;
/* verilator lint_on SYMRSVDWORD */
logic by;
logic half;
logic word;
logic dword; // for dma
logic load;
logic store;
logic unsign;
logic dma; // dma pkt
logic store_data_bypass_d;
logic load_ldst_bypass_d;
logic store_data_bypass_m;
logic valid;
} lsu_pkt_t;
typedef struct packed {
logic inst_type; //0: Load, 1: Store
//logic dma_valid;
logic exc_type; //0: MisAligned, 1: Access Fault
logic [3:0] mscause;
logic [31:0] addr;
logic single_ecc_error;
logic exc_valid;
} lsu_error_pkt_t;
typedef struct packed {
logic clz;
logic ctz;
logic pcnt;
logic sext_b;
logic sext_h;
logic slo;
logic sro;
logic min;
logic max;
logic pack;
logic packu;
logic packh;
logic rol;
logic ror;
logic grev;
logic gorc;
logic zbb;
logic sbset;
logic sbclr;
logic sbinv;
logic sbext;
logic zbs;
logic bext;
logic bdep;
logic zbe;
logic clmul;
logic clmulh;
logic clmulr;
logic zbc;
logic shfl;
logic unshfl;
logic zbp;
logic crc32_b;
logic crc32_h;
logic crc32_w;
logic crc32c_b;
logic crc32c_h;
logic crc32c_w;
logic zbr;
logic bfp;
logic zbf;
logic sh1add;
logic sh2add;
logic sh3add;
logic zba;
logic alu;
logic rs1;
logic rs2;
logic imm12;
logic rd;
logic shimm5;
logic imm20;
logic pc;
logic load;
logic store;
logic lsu;
logic add;
logic sub;
logic land;
logic lor;
logic lxor;
logic sll;
logic sra;
logic srl;
logic slt;
logic unsign;
logic condbr;
logic beq;
logic bne;
logic bge;
logic blt;
logic jal;
logic by;
logic half;
logic word;
logic csr_read;
logic csr_clr;
logic csr_set;
logic csr_write;
logic csr_imm;
logic presync;
logic postsync;
logic ebreak;
logic ecall;
logic mret;
logic mul;
logic rs1_sign;
logic rs2_sign;
logic low;
logic div;
logic rem;
logic fence;
logic fence_i;
logic pm_alu;
logic legal;
} dec_pkt_t;
typedef struct packed {
logic valid;
logic rs1_sign;
logic rs2_sign;
logic low;
logic bext;
logic bdep;
logic clmul;
logic clmulh;
logic clmulr;
logic grev;
logic gorc;
logic shfl;
logic unshfl;
logic crc32_b;
logic crc32_h;
logic crc32_w;
logic crc32c_b;
logic crc32c_h;
logic crc32c_w;
logic bfp;
} mul_pkt_t;
typedef struct packed {
logic valid;
logic unsign;
logic rem;
} div_pkt_t;
typedef struct packed {
logic TEST1;
logic RME;
logic [3:0] RM;
logic LS;
logic DS;
logic SD;
logic TEST_RNM;
logic BC1;
logic BC2;
} iccm_ext_in_pkt_t;
typedef struct packed {
logic TEST1;
logic RME;
logic [3:0] RM;
logic LS;
logic DS;
logic SD;
logic TEST_RNM;
logic BC1;
logic BC2;
} dccm_ext_in_pkt_t;
typedef struct packed {
logic TEST1;
logic RME;
logic [3:0] RM;
logic LS;
logic DS;
logic SD;
logic TEST_RNM;
logic BC1;
logic BC2;
} ic_data_ext_in_pkt_t;
typedef struct packed {
logic TEST1;
logic RME;
logic [3:0] RM;
logic LS;
logic DS;
logic SD;
logic TEST_RNM;
logic BC1;
logic BC2;
} ic_tag_ext_in_pkt_t;
typedef struct packed {
logic select;
logic match;
logic store;
logic load;
logic execute;
logic m;
logic [31:0] tdata2;
} trigger_pkt_t;
typedef struct packed {
logic [70:0] icache_wrdata; // {dicad1[1:0], dicad0h[31:0], dicad0[31:0]}
logic [16:0] icache_dicawics; // Arraysel:24, Waysel:21:20, Index:16:3
logic icache_rd_valid;
logic icache_wr_valid;
} cache_debug_pkt_t;

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// SPDX-License-Identifier: Apache-2.0
// Copyright 2019 Western Digital Corporation or it's affiliates.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License
module rvjtag_tap
`include "parameter.sv"(
input trst,
input tck,
input tms,
input tdi,
output reg tdo,
output tdoEnable,
output [31:0] wr_data,
output [AWIDTH-1:0] wr_addr,
output wr_en,
output rd_en,
input [31:0] rd_data,
input [1:0] rd_status,
output reg dmi_reset,
output reg dmi_hard_reset,
input [2:0] idle,
input [1:0] dmi_stat,
/*
-- revisionCode : 4'h0;
-- manufacturersIdCode : 11'h45;
-- deviceIdCode : 16'h0001;
-- order MSB .. LSB -> [4 bit version or revision] [16 bit part number] [11 bit manufacturer id] [value of 1'b1 in LSB]
*/
input [31:1] jtag_id,
input [3:0] version
);
localparam USER_DR_LENGTH = AWIDTH + 34;
reg [USER_DR_LENGTH-1:0] sr, nsr, dr;
///////////////////////////////////////////////////////
// Tap controller
///////////////////////////////////////////////////////
logic[3:0] state, nstate;
logic [4:0] ir;
wire jtag_reset;
wire shift_dr;
wire pause_dr;
wire update_dr;
wire capture_dr;
wire shift_ir;
wire pause_ir ;
wire update_ir ;
wire capture_ir;
wire[1:0] dr_en;
wire devid_sel;
wire [5:0] abits;
assign abits = AWIDTH[5:0];
localparam TEST_LOGIC_RESET_STATE = 0;
localparam RUN_TEST_IDLE_STATE = 1;
localparam SELECT_DR_SCAN_STATE = 2;
localparam CAPTURE_DR_STATE = 3;
localparam SHIFT_DR_STATE = 4;
localparam EXIT1_DR_STATE = 5;
localparam PAUSE_DR_STATE = 6;
localparam EXIT2_DR_STATE = 7;
localparam UPDATE_DR_STATE = 8;
localparam SELECT_IR_SCAN_STATE = 9;
localparam CAPTURE_IR_STATE = 10;
localparam SHIFT_IR_STATE = 11;
localparam EXIT1_IR_STATE = 12;
localparam PAUSE_IR_STATE = 13;
localparam EXIT2_IR_STATE = 14;
localparam UPDATE_IR_STATE = 15;
always_comb begin
nstate = state;
case(state)
TEST_LOGIC_RESET_STATE: nstate = tms ? TEST_LOGIC_RESET_STATE : RUN_TEST_IDLE_STATE;
RUN_TEST_IDLE_STATE: nstate = tms ? SELECT_DR_SCAN_STATE : RUN_TEST_IDLE_STATE;
SELECT_DR_SCAN_STATE: nstate = tms ? SELECT_IR_SCAN_STATE : CAPTURE_DR_STATE;
CAPTURE_DR_STATE: nstate = tms ? EXIT1_DR_STATE : SHIFT_DR_STATE;
SHIFT_DR_STATE: nstate = tms ? EXIT1_DR_STATE : SHIFT_DR_STATE;
EXIT1_DR_STATE: nstate = tms ? UPDATE_DR_STATE : PAUSE_DR_STATE;
PAUSE_DR_STATE: nstate = tms ? EXIT2_DR_STATE : PAUSE_DR_STATE;
EXIT2_DR_STATE: nstate = tms ? UPDATE_DR_STATE : SHIFT_DR_STATE;
UPDATE_DR_STATE: nstate = tms ? SELECT_DR_SCAN_STATE : RUN_TEST_IDLE_STATE;
SELECT_IR_SCAN_STATE: nstate = tms ? TEST_LOGIC_RESET_STATE : CAPTURE_IR_STATE;
CAPTURE_IR_STATE: nstate = tms ? EXIT1_IR_STATE : SHIFT_IR_STATE;
SHIFT_IR_STATE: nstate = tms ? EXIT1_IR_STATE : SHIFT_IR_STATE;
EXIT1_IR_STATE: nstate = tms ? UPDATE_IR_STATE : PAUSE_IR_STATE;
PAUSE_IR_STATE: nstate = tms ? EXIT2_IR_STATE : PAUSE_IR_STATE;
EXIT2_IR_STATE: nstate = tms ? UPDATE_IR_STATE : SHIFT_IR_STATE;
UPDATE_IR_STATE: nstate = tms ? SELECT_DR_SCAN_STATE : RUN_TEST_IDLE_STATE;
default: nstate = TEST_LOGIC_RESET_STATE;
endcase
end
always @ (posedge tck or negedge trst) begin
if(!trst) state <= TEST_LOGIC_RESET_STATE;
else state <= nstate;
end
assign jtag_reset = state == TEST_LOGIC_RESET_STATE;
assign shift_dr = state == SHIFT_DR_STATE;
assign pause_dr = state == PAUSE_DR_STATE;
assign update_dr = state == UPDATE_DR_STATE;
assign capture_dr = state == CAPTURE_DR_STATE;
assign shift_ir = state == SHIFT_IR_STATE;
assign pause_ir = state == PAUSE_IR_STATE;
assign update_ir = state == UPDATE_IR_STATE;
assign capture_ir = state == CAPTURE_IR_STATE;
assign tdoEnable = shift_dr | shift_ir;
///////////////////////////////////////////////////////
// IR register
///////////////////////////////////////////////////////
always @ (negedge tck or negedge trst) begin
if (!trst) ir <= 5'b1;
else begin
if (jtag_reset) ir <= 5'b1;
else if (update_ir) ir <= (sr[4:0] == '0) ? 5'h1f :sr[4:0];
end
end
assign devid_sel = ir == 5'b00001;
assign dr_en[0] = ir == 5'b10000;
assign dr_en[1] = ir == 5'b10001;
///////////////////////////////////////////////////////
// Shift register
///////////////////////////////////////////////////////
always @ (posedge tck or negedge trst) begin
if(!trst)begin
sr <= '0;
end
else begin
sr <= nsr;
end
end
// SR next value
always_comb begin
nsr = sr;
case(1)
shift_dr: begin
case(1)
dr_en[1]: nsr = {tdi, sr[USER_DR_LENGTH-1:1]};
dr_en[0],
devid_sel: nsr = {{USER_DR_LENGTH-32{1'b0}},tdi, sr[31:1]};
default: nsr = {{USER_DR_LENGTH-1{1'b0}},tdi}; // bypass
endcase
end
capture_dr: begin
nsr[0] = 1'b0;
case(1)
dr_en[0]: nsr = {{USER_DR_LENGTH-15{1'b0}}, idle, dmi_stat, abits, version};
dr_en[1]: nsr = {{AWIDTH{1'b0}}, rd_data, rd_status};
devid_sel: nsr = {{USER_DR_LENGTH-32{1'b0}}, jtag_id, 1'b1};
endcase
end
shift_ir: nsr = {{USER_DR_LENGTH-5{1'b0}},tdi, sr[4:1]};
capture_ir: nsr = {{USER_DR_LENGTH-1{1'b0}},1'b1};
endcase
end
// TDO retiming
always @ (negedge tck ) tdo <= sr[0];
// DMI CS register
always @ (posedge tck or negedge trst) begin
if(!trst) begin
dmi_hard_reset <= 1'b0;
dmi_reset <= 1'b0;
end
else if (update_dr & dr_en[0]) begin
dmi_hard_reset <= sr[17];
dmi_reset <= sr[16];
end
else begin
dmi_hard_reset <= 1'b0;
dmi_reset <= 1'b0;
end
end
// DR register
always @ (posedge tck or negedge trst) begin
if(!trst)
dr <= '0;
else begin
if (update_dr & dr_en[1])
dr <= sr;
else
dr <= {dr[USER_DR_LENGTH-1:2],2'b0};
end
end
assign {wr_addr, wr_data, wr_en, rd_en} = dr;
endmodule

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fm_run = fm_shell -f formality_work/run_me.fms
eda_check:
@$(CHECK_EDA_PATH)
fm_run: eda_check
rm -rf LEC_RTL
git clone https://github.com/Lampro-Mellon/LEC_RTL.git
make -f $(RV_ROOT)/tools/Makefile clean
make -f $(RV_ROOT)/tools/Makefile conf
make -f $(RV_ROOT)/tools/Makefile sbt_
$(fm_run)
@mv *.log formality_work/formality_log
fm_gui: eda_check
rm -rf LEC_RTL
git clone https://github.com/Lampro-Mellon/LEC_RTL.git
make -f $(RV_ROOT)/tools/Makefile clean
make -f $(RV_ROOT)/tools/Makefile conf
make -f $(RV_ROOT)/tools/Makefile sbt_
formality &
@mv *.log formality_work/formality_log

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verif/LEC/config.py
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@ -1,5 +1,5 @@
import re import re
infile= open("./configs/snapshots/default/param.vh",'r') infile= open("./design/snapshots/default/param.vh",'r')
params = [] params = []
lines = infile.readlines() lines = infile.readlines()
for line in lines: for line in lines:

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****************************************************
Warning: Cell r:/WORK/el2_swerv_wrapper/mem references black-box design /WORK/el2_mem (FM-158)
Info: Net r:/WORK/el2_swerv/sb_hsize[2] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hsize[1] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hsize[0] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_htrans[1] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_htrans[0] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwrite is undriven.
Info: Net r:/WORK/el2_swerv/htrans[1] is undriven.
Info: Net r:/WORK/el2_swerv/htrans[0] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hmastlock is undriven.
Info: Net r:/WORK/el2_swerv/sb_hmastlock is undriven.
Info: Net r:/WORK/el2_swerv/sb_hprot[3] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hprot[2] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hprot[1] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hprot[0] is undriven.
Info: Net r:/WORK/el2_swerv/hburst[2] is undriven.
Info: Net r:/WORK/el2_swerv/hburst[1] is undriven.
Info: Net r:/WORK/el2_swerv/hburst[0] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hburst[2] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hburst[1] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hburst[0] is undriven.
Info: Net r:/WORK/el2_swerv/hsize[2] is undriven.
Info: Net r:/WORK/el2_swerv/hsize[1] is undriven.
Info: Net r:/WORK/el2_swerv/hsize[0] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hresp is undriven.
Info: Net r:/WORK/el2_swerv/hprot[3] is undriven.
Info: Net r:/WORK/el2_swerv/hprot[2] is undriven.
Info: Net r:/WORK/el2_swerv/hprot[1] is undriven.
Info: Net r:/WORK/el2_swerv/hprot[0] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[63] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[62] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[61] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[60] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[59] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[58] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[57] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[56] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[55] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[54] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[53] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[52] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[51] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[50] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[49] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[48] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[47] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[46] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[45] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[44] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[43] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[42] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[41] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[40] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[39] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[38] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[37] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[36] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[35] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[34] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[33] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[32] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[31] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[30] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[29] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[28] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[27] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[26] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[25] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[24] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[23] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[22] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[21] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[20] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[19] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[18] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[17] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[16] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[15] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[14] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[13] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[12] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[11] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[10] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[9] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[8] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[7] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[6] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[5] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[4] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[3] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[2] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[1] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[0] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_haddr[31] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_haddr[30] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_haddr[29] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_haddr[28] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_haddr[27] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_haddr[26] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_haddr[25] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_haddr[24] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_haddr[23] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_haddr[22] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_haddr[21] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_haddr[20] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_haddr[19] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_haddr[18] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_haddr[17] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_haddr[16] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_haddr[15] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_haddr[14] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_haddr[13] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_haddr[12] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_haddr[11] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_haddr[10] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_haddr[9] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_haddr[8] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_haddr[7] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_haddr[6] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_haddr[5] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_haddr[4] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_haddr[3] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_haddr[2] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_haddr[1] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_haddr[0] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hburst[2] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hburst[1] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hburst[0] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hreadyout is undriven.
Info: Net r:/WORK/el2_swerv/hwrite is undriven.
Info: Net r:/WORK/el2_swerv/sb_htrans[1] is undriven.
Info: Net r:/WORK/el2_swerv/sb_htrans[0] is undriven.
Info: Net r:/WORK/el2_swerv/sb_haddr[31] is undriven.
Info: Net r:/WORK/el2_swerv/sb_haddr[30] is undriven.
Info: Net r:/WORK/el2_swerv/sb_haddr[29] is undriven.
Info: Net r:/WORK/el2_swerv/sb_haddr[28] is undriven.
Info: Net r:/WORK/el2_swerv/sb_haddr[27] is undriven.
Info: Net r:/WORK/el2_swerv/sb_haddr[26] is undriven.
Info: Net r:/WORK/el2_swerv/sb_haddr[25] is undriven.
Info: Net r:/WORK/el2_swerv/sb_haddr[24] is undriven.
Info: Net r:/WORK/el2_swerv/sb_haddr[23] is undriven.
Info: Net r:/WORK/el2_swerv/sb_haddr[22] is undriven.
Info: Net r:/WORK/el2_swerv/sb_haddr[21] is undriven.
Info: Net r:/WORK/el2_swerv/sb_haddr[20] is undriven.
Info: Net r:/WORK/el2_swerv/sb_haddr[19] is undriven.
Info: Net r:/WORK/el2_swerv/sb_haddr[18] is undriven.
Info: Net r:/WORK/el2_swerv/sb_haddr[17] is undriven.
Info: Net r:/WORK/el2_swerv/sb_haddr[16] is undriven.
Info: Net r:/WORK/el2_swerv/sb_haddr[15] is undriven.
Info: Net r:/WORK/el2_swerv/sb_haddr[14] is undriven.
Info: Net r:/WORK/el2_swerv/sb_haddr[13] is undriven.
Info: Net r:/WORK/el2_swerv/sb_haddr[12] is undriven.
Info: Net r:/WORK/el2_swerv/sb_haddr[11] is undriven.
Info: Net r:/WORK/el2_swerv/sb_haddr[10] is undriven.
Info: Net r:/WORK/el2_swerv/sb_haddr[9] is undriven.
Info: Net r:/WORK/el2_swerv/sb_haddr[8] is undriven.
Info: Net r:/WORK/el2_swerv/sb_haddr[7] is undriven.
Info: Net r:/WORK/el2_swerv/sb_haddr[6] is undriven.
Info: Net r:/WORK/el2_swerv/sb_haddr[5] is undriven.
Info: Net r:/WORK/el2_swerv/sb_haddr[4] is undriven.
Info: Net r:/WORK/el2_swerv/sb_haddr[3] is undriven.
Info: Net r:/WORK/el2_swerv/sb_haddr[2] is undriven.
Info: Net r:/WORK/el2_swerv/sb_haddr[1] is undriven.
Info: Net r:/WORK/el2_swerv/sb_haddr[0] is undriven.
Info: Net r:/WORK/el2_swerv/hmastlock is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwrite is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[63] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[62] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[61] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[60] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[59] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[58] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[57] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[56] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[55] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[54] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[53] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[52] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[51] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[50] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[49] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[48] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[47] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[46] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[45] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[44] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[43] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[42] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[41] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[40] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[39] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[38] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[37] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[36] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[35] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[34] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[33] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[32] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[31] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[30] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[29] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[28] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[27] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[26] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[25] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[24] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[23] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[22] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[21] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[20] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[19] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[18] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[17] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[16] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[15] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[14] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[13] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[12] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[11] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[10] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[9] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[8] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[7] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[6] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[5] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[4] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[3] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[2] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[1] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[0] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hsize[2] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hsize[1] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hsize[0] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hprot[3] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hprot[2] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hprot[1] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hprot[0] is undriven.
Info: Net r:/WORK/el2_swerv/haddr[31] is undriven.
Info: Net r:/WORK/el2_swerv/haddr[30] is undriven.
Info: Net r:/WORK/el2_swerv/haddr[29] is undriven.
Info: Net r:/WORK/el2_swerv/haddr[28] is undriven.
Info: Net r:/WORK/el2_swerv/haddr[27] is undriven.
Info: Net r:/WORK/el2_swerv/haddr[26] is undriven.
Info: Net r:/WORK/el2_swerv/haddr[25] is undriven.
Info: Net r:/WORK/el2_swerv/haddr[24] is undriven.
Info: Net r:/WORK/el2_swerv/haddr[23] is undriven.
Info: Net r:/WORK/el2_swerv/haddr[22] is undriven.
Info: Net r:/WORK/el2_swerv/haddr[21] is undriven.
Info: Net r:/WORK/el2_swerv/haddr[20] is undriven.
Info: Net r:/WORK/el2_swerv/haddr[19] is undriven.
Info: Net r:/WORK/el2_swerv/haddr[18] is undriven.
Info: Net r:/WORK/el2_swerv/haddr[17] is undriven.
Info: Net r:/WORK/el2_swerv/haddr[16] is undriven.
Info: Net r:/WORK/el2_swerv/haddr[15] is undriven.
Info: Net r:/WORK/el2_swerv/haddr[14] is undriven.
Info: Net r:/WORK/el2_swerv/haddr[13] is undriven.
Info: Net r:/WORK/el2_swerv/haddr[12] is undriven.
Info: Net r:/WORK/el2_swerv/haddr[11] is undriven.
Info: Net r:/WORK/el2_swerv/haddr[10] is undriven.
Info: Net r:/WORK/el2_swerv/haddr[9] is undriven.
Info: Net r:/WORK/el2_swerv/haddr[8] is undriven.
Info: Net r:/WORK/el2_swerv/haddr[7] is undriven.
Info: Net r:/WORK/el2_swerv/haddr[6] is undriven.
Info: Net r:/WORK/el2_swerv/haddr[5] is undriven.
Info: Net r:/WORK/el2_swerv/haddr[4] is undriven.
Info: Net r:/WORK/el2_swerv/haddr[3] is undriven.
Info: Net r:/WORK/el2_swerv/haddr[2] is undriven.
Info: Net r:/WORK/el2_swerv/haddr[1] is undriven.
Info: Net r:/WORK/el2_swerv/haddr[0] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[63] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[62] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[61] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[60] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[59] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[58] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[57] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[56] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[55] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[54] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[53] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[52] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[51] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[50] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[49] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[48] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[47] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[46] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[45] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[44] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[43] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[42] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[41] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[40] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[39] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[38] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[37] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[36] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[35] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[34] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[33] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[32] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[31] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[30] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[29] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[28] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[27] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[26] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[25] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[24] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[23] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[22] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[21] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[20] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[19] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[18] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[17] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[16] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[15] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[14] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[13] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[12] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[11] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[10] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[9] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[8] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[7] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[6] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[5] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[4] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[3] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[2] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[1] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[0] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/ifu_bp_fa_index_f[1][8] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/ifu_bp_fa_index_f[1][7] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/ifu_bp_fa_index_f[1][6] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/ifu_bp_fa_index_f[1][5] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/ifu_bp_fa_index_f[1][4] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/ifu_bp_fa_index_f[1][3] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/ifu_bp_fa_index_f[1][2] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/ifu_bp_fa_index_f[1][1] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/ifu_bp_fa_index_f[1][0] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/ifu_bp_fa_index_f[0][8] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/ifu_bp_fa_index_f[0][7] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/ifu_bp_fa_index_f[0][6] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/ifu_bp_fa_index_f[0][5] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/ifu_bp_fa_index_f[0][4] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/ifu_bp_fa_index_f[0][3] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/ifu_bp_fa_index_f[0][2] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/ifu_bp_fa_index_f[0][1] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/ifu_bp_fa_index_f[0][0] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[1][15] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[1][14] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[1][13] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[1][12] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[1][11] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[1][10] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[1][9] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[1][8] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[1][7] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[1][6] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[1][5] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[1][4] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[1][3] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[1][2] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[1][1] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[1][0] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[0][15] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[0][14] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[0][13] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[0][12] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[0][11] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[0][10] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[0][9] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[0][8] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[0][7] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[0][6] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[0][5] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[0][4] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[0][3] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[0][2] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[0][1] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[0][0] is undriven.
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[br_error] is undriven.
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[br_start_error] is undriven.
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][31] is undriven.
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][30] is undriven.
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][29] is undriven.
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][28] is undriven.
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][27] is undriven.
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][26] is undriven.
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][25] is undriven.
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][24] is undriven.
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][23] is undriven.
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][22] is undriven.
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][21] is undriven.
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][20] is undriven.
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][19] is undriven.
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][18] is undriven.
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][17] is undriven.
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][16] is undriven.
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][15] is undriven.
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][14] is undriven.
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][13] is undriven.
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][12] is undriven.
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][11] is undriven.
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][10] is undriven.
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][9] is undriven.
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][8] is undriven.
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][7] is undriven.
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][6] is undriven.
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][5] is undriven.
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][4] is undriven.
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][3] is undriven.
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][2] is undriven.
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][1] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_data_ecc_hi_r[6] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_data_ecc_hi_r[5] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_data_ecc_hi_r[4] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_data_ecc_hi_r[3] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_data_ecc_hi_r[2] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_data_ecc_hi_r[1] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_data_ecc_hi_r[0] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[31] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[30] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[29] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[28] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[27] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[26] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[25] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[24] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[23] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[22] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[21] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[20] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[19] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[18] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[17] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[16] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[15] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[14] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[13] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[12] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[11] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[10] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[9] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[8] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[7] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[6] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[5] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[4] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[3] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[2] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[1] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[0] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_data_ecc_lo_r[6] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_data_ecc_lo_r[5] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_data_ecc_lo_r[4] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_data_ecc_lo_r[3] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_data_ecc_lo_r[2] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_data_ecc_lo_r[1] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_data_ecc_lo_r[0] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[31] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[30] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[29] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[28] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[27] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[26] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[25] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[24] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[23] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[22] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[21] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[20] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[19] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[18] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[17] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[16] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[15] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[14] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[13] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[12] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[11] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[10] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[9] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[8] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[7] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[6] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[5] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[4] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[3] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[2] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[1] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[0] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[31] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[30] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[29] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[28] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[27] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[26] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[25] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[24] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[23] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[22] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[21] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[20] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[19] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[18] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[17] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[16] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[15] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[14] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[13] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[12] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[11] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[10] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[9] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[8] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[7] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[6] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[5] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[4] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[3] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[2] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[1] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[0] is undriven.
Warning: Cell i:/WORK/quasar_wrapper/mem references black-box design /WORK/mem_DCCM_BANK_BITS2_DCCM_BITS16_DCCM_BYTE_WIDTH4_DCCM_ENABLE1_DCCM_FDATA_WIDTH39_DCCM_NUM_BANKS4_DCCM_SIZE64_DCCM_WIDTH_BITS2_ICACHE_BANK_BITS1_ICACHE_BANK_HI3_ICACHE_BANK_LO3_ICACHE_BANKS_WAY2_ICACHE_BEAT_ADDR_HI5_ICACHE_BEAT_BITS3_ICACHE_BYPASS_ENABLE1_ICACHE_DATA_DEPTH512_ICACHE_DATA_INDEX_LO4_ICACHE_ECC1_ICACHE_ENABLE1_ICACHE_INDEX_HI12_ICACHE_LN_SZ64_ICACHE_NUM_BYPASS2_ICACHE_NUM_BYPASS_WIDTH2_ICACHE_NUM_WAYS2_ICACHE_TAG_BYPASS_ENABLE1_ICACHE_TAG_DEPTH128_ICACHE_TAG_INDEX_LO6_ICACHE_TAG_LO13_ICACHE_TAG_NUM_BYPASS2_ICACHE_TAG_NUM_BYPASS_WIDTH2_ICACHE_WAYPACK1_ICCM_BANK_BITS2_ICCM_BANK_HI3_ICCM_BANK_INDEX_LO4_ICCM_BITS16_ICCM_ENABLE1_ICCM_INDEX_BITS12_ICCM_NUM_BANKS4 (FM-158)
****************************************************

531
verif/LEC/formality_work/formality_log/formality1.log Normal file
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@ -0,0 +1,531 @@
****************************************************
Warning: Cell r:/WORK/el2_swerv_wrapper/mem references black-box design /WORK/el2_mem (FM-158)
Info: Net r:/WORK/el2_swerv/sb_hsize[2] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hsize[1] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hsize[0] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_htrans[1] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_htrans[0] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwrite is undriven.
Info: Net r:/WORK/el2_swerv/htrans[1] is undriven.
Info: Net r:/WORK/el2_swerv/htrans[0] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hmastlock is undriven.
Info: Net r:/WORK/el2_swerv/sb_hmastlock is undriven.
Info: Net r:/WORK/el2_swerv/sb_hprot[3] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hprot[2] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hprot[1] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hprot[0] is undriven.
Info: Net r:/WORK/el2_swerv/hburst[2] is undriven.
Info: Net r:/WORK/el2_swerv/hburst[1] is undriven.
Info: Net r:/WORK/el2_swerv/hburst[0] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hburst[2] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hburst[1] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hburst[0] is undriven.
Info: Net r:/WORK/el2_swerv/hsize[2] is undriven.
Info: Net r:/WORK/el2_swerv/hsize[1] is undriven.
Info: Net r:/WORK/el2_swerv/hsize[0] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hresp is undriven.
Info: Net r:/WORK/el2_swerv/hprot[3] is undriven.
Info: Net r:/WORK/el2_swerv/hprot[2] is undriven.
Info: Net r:/WORK/el2_swerv/hprot[1] is undriven.
Info: Net r:/WORK/el2_swerv/hprot[0] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[63] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[62] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[61] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[60] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[59] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[58] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[57] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[56] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[55] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[54] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[53] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[52] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[51] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[50] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[49] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[48] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[47] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[46] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[45] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[44] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[43] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[42] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[41] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[40] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[39] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[38] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[37] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[36] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[35] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[34] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[33] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[32] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[31] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[30] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[29] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[28] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[27] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[26] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[25] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[24] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[23] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[22] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[21] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[20] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[19] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[18] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[17] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[16] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[15] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[14] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[13] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[12] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[11] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[10] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[9] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[8] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[7] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[6] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[5] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[4] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[3] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[2] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[1] is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwdata[0] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_haddr[31] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_haddr[30] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_haddr[29] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_haddr[28] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_haddr[27] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_haddr[26] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_haddr[25] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_haddr[24] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_haddr[23] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_haddr[22] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_haddr[21] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_haddr[20] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_haddr[19] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_haddr[18] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_haddr[17] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_haddr[16] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_haddr[15] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_haddr[14] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_haddr[13] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_haddr[12] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_haddr[11] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_haddr[10] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_haddr[9] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_haddr[8] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_haddr[7] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_haddr[6] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_haddr[5] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_haddr[4] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_haddr[3] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_haddr[2] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_haddr[1] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_haddr[0] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hburst[2] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hburst[1] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hburst[0] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hreadyout is undriven.
Info: Net r:/WORK/el2_swerv/hwrite is undriven.
Info: Net r:/WORK/el2_swerv/sb_htrans[1] is undriven.
Info: Net r:/WORK/el2_swerv/sb_htrans[0] is undriven.
Info: Net r:/WORK/el2_swerv/sb_haddr[31] is undriven.
Info: Net r:/WORK/el2_swerv/sb_haddr[30] is undriven.
Info: Net r:/WORK/el2_swerv/sb_haddr[29] is undriven.
Info: Net r:/WORK/el2_swerv/sb_haddr[28] is undriven.
Info: Net r:/WORK/el2_swerv/sb_haddr[27] is undriven.
Info: Net r:/WORK/el2_swerv/sb_haddr[26] is undriven.
Info: Net r:/WORK/el2_swerv/sb_haddr[25] is undriven.
Info: Net r:/WORK/el2_swerv/sb_haddr[24] is undriven.
Info: Net r:/WORK/el2_swerv/sb_haddr[23] is undriven.
Info: Net r:/WORK/el2_swerv/sb_haddr[22] is undriven.
Info: Net r:/WORK/el2_swerv/sb_haddr[21] is undriven.
Info: Net r:/WORK/el2_swerv/sb_haddr[20] is undriven.
Info: Net r:/WORK/el2_swerv/sb_haddr[19] is undriven.
Info: Net r:/WORK/el2_swerv/sb_haddr[18] is undriven.
Info: Net r:/WORK/el2_swerv/sb_haddr[17] is undriven.
Info: Net r:/WORK/el2_swerv/sb_haddr[16] is undriven.
Info: Net r:/WORK/el2_swerv/sb_haddr[15] is undriven.
Info: Net r:/WORK/el2_swerv/sb_haddr[14] is undriven.
Info: Net r:/WORK/el2_swerv/sb_haddr[13] is undriven.
Info: Net r:/WORK/el2_swerv/sb_haddr[12] is undriven.
Info: Net r:/WORK/el2_swerv/sb_haddr[11] is undriven.
Info: Net r:/WORK/el2_swerv/sb_haddr[10] is undriven.
Info: Net r:/WORK/el2_swerv/sb_haddr[9] is undriven.
Info: Net r:/WORK/el2_swerv/sb_haddr[8] is undriven.
Info: Net r:/WORK/el2_swerv/sb_haddr[7] is undriven.
Info: Net r:/WORK/el2_swerv/sb_haddr[6] is undriven.
Info: Net r:/WORK/el2_swerv/sb_haddr[5] is undriven.
Info: Net r:/WORK/el2_swerv/sb_haddr[4] is undriven.
Info: Net r:/WORK/el2_swerv/sb_haddr[3] is undriven.
Info: Net r:/WORK/el2_swerv/sb_haddr[2] is undriven.
Info: Net r:/WORK/el2_swerv/sb_haddr[1] is undriven.
Info: Net r:/WORK/el2_swerv/sb_haddr[0] is undriven.
Info: Net r:/WORK/el2_swerv/hmastlock is undriven.
Info: Net r:/WORK/el2_swerv/sb_hwrite is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[63] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[62] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[61] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[60] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[59] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[58] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[57] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[56] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[55] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[54] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[53] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[52] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[51] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[50] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[49] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[48] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[47] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[46] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[45] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[44] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[43] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[42] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[41] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[40] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[39] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[38] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[37] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[36] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[35] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[34] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[33] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[32] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[31] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[30] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[29] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[28] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[27] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[26] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[25] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[24] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[23] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[22] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[21] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[20] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[19] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[18] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[17] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[16] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[15] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[14] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[13] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[12] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[11] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[10] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[9] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[8] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[7] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[6] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[5] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[4] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[3] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[2] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[1] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hwdata[0] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hsize[2] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hsize[1] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hsize[0] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hprot[3] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hprot[2] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hprot[1] is undriven.
Info: Net r:/WORK/el2_swerv/lsu_hprot[0] is undriven.
Info: Net r:/WORK/el2_swerv/haddr[31] is undriven.
Info: Net r:/WORK/el2_swerv/haddr[30] is undriven.
Info: Net r:/WORK/el2_swerv/haddr[29] is undriven.
Info: Net r:/WORK/el2_swerv/haddr[28] is undriven.
Info: Net r:/WORK/el2_swerv/haddr[27] is undriven.
Info: Net r:/WORK/el2_swerv/haddr[26] is undriven.
Info: Net r:/WORK/el2_swerv/haddr[25] is undriven.
Info: Net r:/WORK/el2_swerv/haddr[24] is undriven.
Info: Net r:/WORK/el2_swerv/haddr[23] is undriven.
Info: Net r:/WORK/el2_swerv/haddr[22] is undriven.
Info: Net r:/WORK/el2_swerv/haddr[21] is undriven.
Info: Net r:/WORK/el2_swerv/haddr[20] is undriven.
Info: Net r:/WORK/el2_swerv/haddr[19] is undriven.
Info: Net r:/WORK/el2_swerv/haddr[18] is undriven.
Info: Net r:/WORK/el2_swerv/haddr[17] is undriven.
Info: Net r:/WORK/el2_swerv/haddr[16] is undriven.
Info: Net r:/WORK/el2_swerv/haddr[15] is undriven.
Info: Net r:/WORK/el2_swerv/haddr[14] is undriven.
Info: Net r:/WORK/el2_swerv/haddr[13] is undriven.
Info: Net r:/WORK/el2_swerv/haddr[12] is undriven.
Info: Net r:/WORK/el2_swerv/haddr[11] is undriven.
Info: Net r:/WORK/el2_swerv/haddr[10] is undriven.
Info: Net r:/WORK/el2_swerv/haddr[9] is undriven.
Info: Net r:/WORK/el2_swerv/haddr[8] is undriven.
Info: Net r:/WORK/el2_swerv/haddr[7] is undriven.
Info: Net r:/WORK/el2_swerv/haddr[6] is undriven.
Info: Net r:/WORK/el2_swerv/haddr[5] is undriven.
Info: Net r:/WORK/el2_swerv/haddr[4] is undriven.
Info: Net r:/WORK/el2_swerv/haddr[3] is undriven.
Info: Net r:/WORK/el2_swerv/haddr[2] is undriven.
Info: Net r:/WORK/el2_swerv/haddr[1] is undriven.
Info: Net r:/WORK/el2_swerv/haddr[0] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[63] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[62] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[61] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[60] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[59] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[58] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[57] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[56] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[55] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[54] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[53] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[52] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[51] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[50] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[49] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[48] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[47] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[46] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[45] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[44] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[43] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[42] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[41] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[40] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[39] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[38] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[37] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[36] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[35] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[34] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[33] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[32] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[31] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[30] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[29] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[28] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[27] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[26] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[25] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[24] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[23] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[22] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[21] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[20] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[19] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[18] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[17] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[16] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[15] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[14] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[13] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[12] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[11] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[10] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[9] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[8] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[7] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[6] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[5] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[4] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[3] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[2] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[1] is undriven.
Info: Net r:/WORK/el2_swerv/dma_hrdata[0] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/ifu_bp_fa_index_f[1][8] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/ifu_bp_fa_index_f[1][7] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/ifu_bp_fa_index_f[1][6] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/ifu_bp_fa_index_f[1][5] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/ifu_bp_fa_index_f[1][4] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/ifu_bp_fa_index_f[1][3] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/ifu_bp_fa_index_f[1][2] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/ifu_bp_fa_index_f[1][1] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/ifu_bp_fa_index_f[1][0] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/ifu_bp_fa_index_f[0][8] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/ifu_bp_fa_index_f[0][7] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/ifu_bp_fa_index_f[0][6] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/ifu_bp_fa_index_f[0][5] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/ifu_bp_fa_index_f[0][4] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/ifu_bp_fa_index_f[0][3] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/ifu_bp_fa_index_f[0][2] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/ifu_bp_fa_index_f[0][1] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/ifu_bp_fa_index_f[0][0] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[1][15] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[1][14] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[1][13] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[1][12] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[1][11] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[1][10] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[1][9] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[1][8] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[1][7] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[1][6] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[1][5] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[1][4] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[1][3] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[1][2] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[1][1] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[1][0] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[0][15] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[0][14] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[0][13] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[0][12] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[0][11] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[0][10] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[0][9] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[0][8] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[0][7] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[0][6] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[0][5] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[0][4] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[0][3] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[0][2] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[0][1] is undriven.
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[0][0] is undriven.
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[br_error] is undriven.
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[br_start_error] is undriven.
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][31] is undriven.
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][30] is undriven.
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][29] is undriven.
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][28] is undriven.
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][27] is undriven.
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][26] is undriven.
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][25] is undriven.
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][24] is undriven.
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][23] is undriven.
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][22] is undriven.
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][21] is undriven.
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][20] is undriven.
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][19] is undriven.
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][18] is undriven.
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][17] is undriven.
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][16] is undriven.
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][15] is undriven.
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][14] is undriven.
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][13] is undriven.
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][12] is undriven.
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][11] is undriven.
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][10] is undriven.
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][9] is undriven.
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][8] is undriven.
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][7] is undriven.
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][6] is undriven.
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][5] is undriven.
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][4] is undriven.
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][3] is undriven.
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][2] is undriven.
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][1] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_data_ecc_hi_r[6] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_data_ecc_hi_r[5] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_data_ecc_hi_r[4] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_data_ecc_hi_r[3] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_data_ecc_hi_r[2] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_data_ecc_hi_r[1] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_data_ecc_hi_r[0] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[31] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[30] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[29] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[28] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[27] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[26] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[25] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[24] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[23] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[22] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[21] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[20] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[19] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[18] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[17] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[16] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[15] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[14] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[13] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[12] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[11] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[10] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[9] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[8] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[7] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[6] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[5] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[4] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[3] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[2] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[1] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[0] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_data_ecc_lo_r[6] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_data_ecc_lo_r[5] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_data_ecc_lo_r[4] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_data_ecc_lo_r[3] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_data_ecc_lo_r[2] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_data_ecc_lo_r[1] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_data_ecc_lo_r[0] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[31] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[30] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[29] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[28] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[27] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[26] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[25] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[24] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[23] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[22] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[21] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[20] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[19] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[18] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[17] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[16] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[15] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[14] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[13] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[12] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[11] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[10] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[9] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[8] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[7] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[6] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[5] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[4] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[3] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[2] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[1] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[0] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[31] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[30] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[29] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[28] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[27] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[26] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[25] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[24] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[23] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[22] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[21] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[20] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[19] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[18] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[17] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[16] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[15] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[14] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[13] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[12] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[11] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[10] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[9] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[8] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[7] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[6] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[5] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[4] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[3] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[2] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[1] is undriven.
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[0] is undriven.
Warning: Cell i:/WORK/quasar_wrapper/mem references black-box design /WORK/mem_DCCM_BANK_BITS2_DCCM_BITS16_DCCM_BYTE_WIDTH4_DCCM_ENABLE1_DCCM_FDATA_WIDTH39_DCCM_NUM_BANKS4_DCCM_SIZE64_DCCM_WIDTH_BITS2_ICACHE_BANK_BITS1_ICACHE_BANK_HI3_ICACHE_BANK_LO3_ICACHE_BANKS_WAY2_ICACHE_BEAT_ADDR_HI5_ICACHE_BEAT_BITS3_ICACHE_BYPASS_ENABLE1_ICACHE_DATA_DEPTH512_ICACHE_DATA_INDEX_LO4_ICACHE_ECC1_ICACHE_ENABLE1_ICACHE_INDEX_HI12_ICACHE_LN_SZ64_ICACHE_NUM_BYPASS2_ICACHE_NUM_BYPASS_WIDTH2_ICACHE_NUM_WAYS2_ICACHE_TAG_BYPASS_ENABLE1_ICACHE_TAG_DEPTH128_ICACHE_TAG_INDEX_LO6_ICACHE_TAG_LO13_ICACHE_TAG_NUM_BYPASS2_ICACHE_TAG_NUM_BYPASS_WIDTH2_ICACHE_WAYPACK1_ICCM_BANK_BITS2_ICCM_BANK_HI3_ICCM_BANK_INDEX_LO4_ICCM_BITS16_ICCM_ENABLE1_ICCM_INDEX_BITS12_ICCM_NUM_BANKS4 (FM-158)
****************************************************

1
verif/LEC/formality_work/formality_log/readme.md
View File

@ -1 +0,0 @@
hello

76
verif/LEC/formality_work/run_me.fms
View File

@ -6,11 +6,13 @@
set LEC_ROOT [pwd]/verif/LEC set LEC_ROOT [pwd]/verif/LEC
# Set formality path to refference design # Set formality path to refference design
set fm_path_r $LEC_ROOT/LEC_RTL/Golden_RTL/ set fm_path_r $LEC_ROOT/LEC_RTL/Golden_RTL
# Synopsis Auto Setup # Synopsis Auto Setup
set synopsys_auto_setup true set synopsys_auto_setup true
set_host_options -max_cores 8
if {![file isdirectory $fm_path_r]} { if {![file isdirectory $fm_path_r]} {
puts "ERROR: path is not valid" puts "ERROR: path is not valid"
exit exit
@ -57,56 +59,68 @@ if {![file isdirectory $fm_path_r]} {
$fm_path_r/design/lsu/el2_lsu_dccm_ctl.sv $fm_path_r/design/lsu/el2_lsu_dccm_ctl.sv
$fm_path_r/design/lsu/el2_lsu_trigger.sv $fm_path_r/design/lsu/el2_lsu_trigger.sv
$fm_path_r/design/dbg/el2_dbg.sv $fm_path_r/design/dbg/el2_dbg.sv
$fm_path_r/design/dmi/dmi_wrapper.sv $fm_path_r/design/dmi/rvjtag_tap.v
$fm_path_r/design/dmi/dmi_jtag_to_core_sync.sv $fm_path_r/design/dmi/dmi_jtag_to_core_sync.v
$fm_path_r/design/dmi/rvjtag_tap.sv $fm_path_r/design/dmi/dmi_wrapper.v
" "
# Setting top reference design # Setting top reference design
set_top r:/WORK/el2_swerv_wrapper set_top r:/WORK/el2_swerv_wrapper
} }
# Loading verilog implementation file # Loading verilog implementation file
read_sverilog -i " \ read_sverilog -i " \
./generated_rtl/quasar_wrapper.sv $LEC_ROOT/LEC_RTL/generated_rtl/pkt.sv
$LEC_ROOT/LEC_RTL/generated_rtl/mem.sv
$LEC_ROOT/LEC_RTL/generated_rtl/ifu_ic_mem.sv
$LEC_ROOT/LEC_RTL/generated_rtl/ifu_iccm_mem.sv
$LEC_ROOT/LEC_RTL/generated_rtl/lsu_dccm_mem.sv
$LEC_ROOT/LEC_RTL/generated_rtl/dmi_wrapper.sv
$LEC_ROOT/LEC_RTL/generated_rtl/dmi_jtag_to_core_sync.sv
$LEC_ROOT/LEC_RTL/generated_rtl/rvjtag_tap.sv
$LEC_ROOT/LEC_RTL/generated_rtl/gated_latch.sv
$LEC_ROOT/LEC_RTL/generated_rtl/beh_lib.sv $LEC_ROOT/LEC_RTL/generated_rtl/beh_lib.sv
$LEC_ROOT/LEC_RTL/generated_rtl/mem_lib.sv $LEC_ROOT/LEC_RTL/generated_rtl/mem_lib.sv
$LEC_ROOT/LEC_RTL/generated_rtl/ltch.sv $LEC_ROOT/LEC_RTL/generated_rtl/ifu_ic_mem.sv
$LEC_ROOT/LEC_RTL/generated_rtl/gated_latch.sv
$LEC_ROOT/LEC_RTL/generated_rtl/ifu_iccm_mem.sv
$LEC_ROOT/LEC_RTL/generated_rtl/lsu_dccm_mem.sv
$LEC_ROOT/LEC_RTL/generated_rtl/mem.sv
$LEC_ROOT/LEC_RTL/generated_rtl/dmi_jtag_to_core_sync.sv
$LEC_ROOT/LEC_RTL/generated_rtl/rvjtag_tap.sv
$LEC_ROOT/LEC_RTL/generated_rtl/dmi_wrapper.sv
./generated_rtl/quasar_wrapper.sv
" "
# Setting top implementation design # Setting top implementation design
set_top i:/WORK/quasar_wrapper set_top i:/WORK/quasar_wrapper
# Setting BLack Boxes on Memories # Setting Black Boxes on Memories
set_black_box r:/WORK/el2_mem set_black_box r:/WORK/el2_mem
set_black_box i:/WORK/mem_ICACHE_BEAT_BITS* set_black_box i:/WORK/mem_DCCM_BANK_BITS*
# Setting User Match on ports
source $LEC_ROOT/setup_files/port.fms
# Setting User Match on Black Box Pins # Setting User Match on input ports
source $LEC_ROOT/setup_files/BBPIN.fms source $LEC_ROOT/setup_files/Input_ports_1.3.fms
# Setting User Match on enabels of CGC # Setting User Match on output ports
source $LEC_ROOT/setup_files/LAT.fms source $LEC_ROOT/setup_files/Output_ports_1.3.fms
# Setting User Match on Flip Flops # Setting User Match on input Black Box Pins
source $LEC_ROOT/setup_files/DFF.fms source $LEC_ROOT/setup_files/BB_input_pins_1.3.fms
# Setting up constants potentially constant registers # Setting User Match on output Black Box Pins
source $LEC_ROOT/setup_files/constant.fms source $LEC_ROOT/setup_files/BB_output_pins_1.3.fms
# Setting User Match on Flip Flops
source $LEC_ROOT/setup_files/DFF_1.3.fms
# Setting up constants potentially constant registers
source $LEC_ROOT/setup_files/Constant_1.3.fms
# Setting up dont verify points
source $LEC_ROOT/setup_files/Dont_verify_points_1.3.fms
if {[verify] != 1} { if {[verify] != 1} {
set verification_failing_points_limit 500 set verification_failing_points_limit 500
start_gui & start_gui &
} }
# Save Current Session # Save Current Session
save_session -replace $LEC_ROOT/LEC_PASSED.fss save_session -replace $LEC_ROOT/LEC_PASSED.fss
exit # Toal Elapsed Time in Seconds
elapsed_time
exit

10
verif/LEC/setup_files/BBPIN.fms
View File

@ -1,10 +0,0 @@
set_user_match r:/WORK/el2_swerv_wrapper/mem/ic_debug_addr[10] i:/WORK/quasar_wrapper/mem/ic_debug_addr[10]
set_user_match r:/WORK/el2_swerv_wrapper/mem/ic_debug_addr[11] i:/WORK/quasar_wrapper/mem/ic_debug_addr[11]
set_user_match r:/WORK/el2_swerv_wrapper/mem/ic_debug_addr[12] i:/WORK/quasar_wrapper/mem/ic_debug_addr[12]
set_user_match r:/WORK/el2_swerv_wrapper/mem/ic_debug_addr[3] i:/WORK/quasar_wrapper/mem/ic_debug_addr[3]
set_user_match r:/WORK/el2_swerv_wrapper/mem/ic_debug_addr[4] i:/WORK/quasar_wrapper/mem/ic_debug_addr[4]
set_user_match r:/WORK/el2_swerv_wrapper/mem/ic_debug_addr[5] i:/WORK/quasar_wrapper/mem/ic_debug_addr[5]
set_user_match r:/WORK/el2_swerv_wrapper/mem/ic_debug_addr[6] i:/WORK/quasar_wrapper/mem/ic_debug_addr[6]
set_user_match r:/WORK/el2_swerv_wrapper/mem/ic_debug_addr[7] i:/WORK/quasar_wrapper/mem/ic_debug_addr[7]
set_user_match r:/WORK/el2_swerv_wrapper/mem/ic_debug_addr[8] i:/WORK/quasar_wrapper/mem/ic_debug_addr[8]
set_user_match r:/WORK/el2_swerv_wrapper/mem/ic_debug_addr[9] i:/WORK/quasar_wrapper/mem/ic_debug_addr[9]

747
verif/LEC/setup_files/BB_input_pins_1.3.fms Normal file
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set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/clk i:/WORK/quasar_wrapper/mem/clk
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_clk_override i:/WORK/quasar_wrapper/mem/dccm_clk_override
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_ext_in_pkt[0]\[BC1] i:/WORK/quasar_wrapper/mem/dccm_ext_in_pkt_BC1_0
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_ext_in_pkt[0]\[BC2] i:/WORK/quasar_wrapper/mem/dccm_ext_in_pkt_BC2_0
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_ext_in_pkt[0]\[DS] i:/WORK/quasar_wrapper/mem/dccm_ext_in_pkt_DS_0
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_ext_in_pkt[0]\[LS] i:/WORK/quasar_wrapper/mem/dccm_ext_in_pkt_LS_0
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_ext_in_pkt[0]\[RME] i:/WORK/quasar_wrapper/mem/dccm_ext_in_pkt_RME_0
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_ext_in_pkt[0]\[RM][0] i:/WORK/quasar_wrapper/mem/dccm_ext_in_pkt_RM_0[0]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_ext_in_pkt[0]\[RM][1] i:/WORK/quasar_wrapper/mem/dccm_ext_in_pkt_RM_0[1]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_ext_in_pkt[0]\[RM][2] i:/WORK/quasar_wrapper/mem/dccm_ext_in_pkt_RM_0[2]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_ext_in_pkt[0]\[RM][3] i:/WORK/quasar_wrapper/mem/dccm_ext_in_pkt_RM_0[3]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_ext_in_pkt[0]\[SD] i:/WORK/quasar_wrapper/mem/dccm_ext_in_pkt_SD_0
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_ext_in_pkt[0]\[TEST1] i:/WORK/quasar_wrapper/mem/dccm_ext_in_pkt_TEST1_0
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_ext_in_pkt[0]\[TEST_RNM] i:/WORK/quasar_wrapper/mem/dccm_ext_in_pkt_TEST_RNM_0
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_ext_in_pkt[1]\[BC1] i:/WORK/quasar_wrapper/mem/dccm_ext_in_pkt_BC1_1
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_ext_in_pkt[1]\[BC2] i:/WORK/quasar_wrapper/mem/dccm_ext_in_pkt_BC2_1
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_ext_in_pkt[1]\[DS] i:/WORK/quasar_wrapper/mem/dccm_ext_in_pkt_DS_1
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_ext_in_pkt[1]\[LS] i:/WORK/quasar_wrapper/mem/dccm_ext_in_pkt_LS_1
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_ext_in_pkt[1]\[RME] i:/WORK/quasar_wrapper/mem/dccm_ext_in_pkt_RME_1
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_ext_in_pkt[1]\[RM][0] i:/WORK/quasar_wrapper/mem/dccm_ext_in_pkt_RM_1[0]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_ext_in_pkt[1]\[RM][1] i:/WORK/quasar_wrapper/mem/dccm_ext_in_pkt_RM_1[1]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_ext_in_pkt[1]\[RM][2] i:/WORK/quasar_wrapper/mem/dccm_ext_in_pkt_RM_1[2]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_ext_in_pkt[1]\[RM][3] i:/WORK/quasar_wrapper/mem/dccm_ext_in_pkt_RM_1[3]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_ext_in_pkt[1]\[SD] i:/WORK/quasar_wrapper/mem/dccm_ext_in_pkt_SD_1
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_ext_in_pkt[1]\[TEST1] i:/WORK/quasar_wrapper/mem/dccm_ext_in_pkt_TEST1_1
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_ext_in_pkt[1]\[TEST_RNM] i:/WORK/quasar_wrapper/mem/dccm_ext_in_pkt_TEST_RNM_1
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_ext_in_pkt[2]\[BC1] i:/WORK/quasar_wrapper/mem/dccm_ext_in_pkt_BC1_2
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_ext_in_pkt[2]\[BC2] i:/WORK/quasar_wrapper/mem/dccm_ext_in_pkt_BC2_2
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_ext_in_pkt[2]\[DS] i:/WORK/quasar_wrapper/mem/dccm_ext_in_pkt_DS_2
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_ext_in_pkt[2]\[LS] i:/WORK/quasar_wrapper/mem/dccm_ext_in_pkt_LS_2
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_ext_in_pkt[2]\[RME] i:/WORK/quasar_wrapper/mem/dccm_ext_in_pkt_RME_2
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_ext_in_pkt[2]\[RM][0] i:/WORK/quasar_wrapper/mem/dccm_ext_in_pkt_RM_2[0]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_ext_in_pkt[2]\[RM][1] i:/WORK/quasar_wrapper/mem/dccm_ext_in_pkt_RM_2[1]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_ext_in_pkt[2]\[RM][2] i:/WORK/quasar_wrapper/mem/dccm_ext_in_pkt_RM_2[2]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_ext_in_pkt[2]\[RM][3] i:/WORK/quasar_wrapper/mem/dccm_ext_in_pkt_RM_2[3]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_ext_in_pkt[2]\[SD] i:/WORK/quasar_wrapper/mem/dccm_ext_in_pkt_SD_2
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_ext_in_pkt[2]\[TEST1] i:/WORK/quasar_wrapper/mem/dccm_ext_in_pkt_TEST1_2
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_ext_in_pkt[2]\[TEST_RNM] i:/WORK/quasar_wrapper/mem/dccm_ext_in_pkt_TEST_RNM_2
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_ext_in_pkt[3]\[BC1] i:/WORK/quasar_wrapper/mem/dccm_ext_in_pkt_BC1_3
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_ext_in_pkt[3]\[BC2] i:/WORK/quasar_wrapper/mem/dccm_ext_in_pkt_BC2_3
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_ext_in_pkt[3]\[DS] i:/WORK/quasar_wrapper/mem/dccm_ext_in_pkt_DS_3
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_ext_in_pkt[3]\[LS] i:/WORK/quasar_wrapper/mem/dccm_ext_in_pkt_LS_3
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_ext_in_pkt[3]\[RME] i:/WORK/quasar_wrapper/mem/dccm_ext_in_pkt_RME_3
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_ext_in_pkt[3]\[RM][0] i:/WORK/quasar_wrapper/mem/dccm_ext_in_pkt_RM_3[0]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_ext_in_pkt[3]\[RM][1] i:/WORK/quasar_wrapper/mem/dccm_ext_in_pkt_RM_3[1]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_ext_in_pkt[3]\[RM][2] i:/WORK/quasar_wrapper/mem/dccm_ext_in_pkt_RM_3[2]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_ext_in_pkt[3]\[RM][3] i:/WORK/quasar_wrapper/mem/dccm_ext_in_pkt_RM_3[3]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_ext_in_pkt[3]\[SD] i:/WORK/quasar_wrapper/mem/dccm_ext_in_pkt_SD_3
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_ext_in_pkt[3]\[TEST1] i:/WORK/quasar_wrapper/mem/dccm_ext_in_pkt_TEST1_3
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_ext_in_pkt[3]\[TEST_RNM] i:/WORK/quasar_wrapper/mem/dccm_ext_in_pkt_TEST_RNM_3
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_addr_hi[0] i:/WORK/quasar_wrapper/mem/dccm_rd_addr_hi[0]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_addr_hi[10] i:/WORK/quasar_wrapper/mem/dccm_rd_addr_hi[10]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_addr_hi[11] i:/WORK/quasar_wrapper/mem/dccm_rd_addr_hi[11]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_addr_hi[12] i:/WORK/quasar_wrapper/mem/dccm_rd_addr_hi[12]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_addr_hi[13] i:/WORK/quasar_wrapper/mem/dccm_rd_addr_hi[13]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_addr_hi[14] i:/WORK/quasar_wrapper/mem/dccm_rd_addr_hi[14]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_addr_hi[15] i:/WORK/quasar_wrapper/mem/dccm_rd_addr_hi[15]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_addr_hi[1] i:/WORK/quasar_wrapper/mem/dccm_rd_addr_hi[1]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_addr_hi[2] i:/WORK/quasar_wrapper/mem/dccm_rd_addr_hi[2]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_addr_hi[3] i:/WORK/quasar_wrapper/mem/dccm_rd_addr_hi[3]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_addr_hi[4] i:/WORK/quasar_wrapper/mem/dccm_rd_addr_hi[4]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_addr_hi[5] i:/WORK/quasar_wrapper/mem/dccm_rd_addr_hi[5]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_addr_hi[6] i:/WORK/quasar_wrapper/mem/dccm_rd_addr_hi[6]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_addr_hi[7] i:/WORK/quasar_wrapper/mem/dccm_rd_addr_hi[7]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_addr_hi[8] i:/WORK/quasar_wrapper/mem/dccm_rd_addr_hi[8]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_addr_hi[9] i:/WORK/quasar_wrapper/mem/dccm_rd_addr_hi[9]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_addr_lo[0] i:/WORK/quasar_wrapper/mem/dccm_rd_addr_lo[0]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_addr_lo[10] i:/WORK/quasar_wrapper/mem/dccm_rd_addr_lo[10]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_addr_lo[11] i:/WORK/quasar_wrapper/mem/dccm_rd_addr_lo[11]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_addr_lo[12] i:/WORK/quasar_wrapper/mem/dccm_rd_addr_lo[12]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_addr_lo[13] i:/WORK/quasar_wrapper/mem/dccm_rd_addr_lo[13]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_addr_lo[14] i:/WORK/quasar_wrapper/mem/dccm_rd_addr_lo[14]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_addr_lo[15] i:/WORK/quasar_wrapper/mem/dccm_rd_addr_lo[15]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_addr_lo[1] i:/WORK/quasar_wrapper/mem/dccm_rd_addr_lo[1]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_addr_lo[2] i:/WORK/quasar_wrapper/mem/dccm_rd_addr_lo[2]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_addr_lo[3] i:/WORK/quasar_wrapper/mem/dccm_rd_addr_lo[3]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_addr_lo[4] i:/WORK/quasar_wrapper/mem/dccm_rd_addr_lo[4]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_addr_lo[5] i:/WORK/quasar_wrapper/mem/dccm_rd_addr_lo[5]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_addr_lo[6] i:/WORK/quasar_wrapper/mem/dccm_rd_addr_lo[6]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_addr_lo[7] i:/WORK/quasar_wrapper/mem/dccm_rd_addr_lo[7]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_addr_lo[8] i:/WORK/quasar_wrapper/mem/dccm_rd_addr_lo[8]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_addr_lo[9] i:/WORK/quasar_wrapper/mem/dccm_rd_addr_lo[9]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rden i:/WORK/quasar_wrapper/mem/dccm_rden
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_addr_hi[0] i:/WORK/quasar_wrapper/mem/dccm_wr_addr_hi[0]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_addr_hi[10] i:/WORK/quasar_wrapper/mem/dccm_wr_addr_hi[10]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_addr_hi[11] i:/WORK/quasar_wrapper/mem/dccm_wr_addr_hi[11]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_addr_hi[12] i:/WORK/quasar_wrapper/mem/dccm_wr_addr_hi[12]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_addr_hi[13] i:/WORK/quasar_wrapper/mem/dccm_wr_addr_hi[13]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_addr_hi[14] i:/WORK/quasar_wrapper/mem/dccm_wr_addr_hi[14]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_addr_hi[15] i:/WORK/quasar_wrapper/mem/dccm_wr_addr_hi[15]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_addr_hi[1] i:/WORK/quasar_wrapper/mem/dccm_wr_addr_hi[1]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_addr_hi[2] i:/WORK/quasar_wrapper/mem/dccm_wr_addr_hi[2]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_addr_hi[3] i:/WORK/quasar_wrapper/mem/dccm_wr_addr_hi[3]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_addr_hi[4] i:/WORK/quasar_wrapper/mem/dccm_wr_addr_hi[4]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_addr_hi[5] i:/WORK/quasar_wrapper/mem/dccm_wr_addr_hi[5]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_addr_hi[6] i:/WORK/quasar_wrapper/mem/dccm_wr_addr_hi[6]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_addr_hi[7] i:/WORK/quasar_wrapper/mem/dccm_wr_addr_hi[7]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_addr_hi[8] i:/WORK/quasar_wrapper/mem/dccm_wr_addr_hi[8]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_addr_hi[9] i:/WORK/quasar_wrapper/mem/dccm_wr_addr_hi[9]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_addr_lo[0] i:/WORK/quasar_wrapper/mem/dccm_wr_addr_lo[0]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_addr_lo[10] i:/WORK/quasar_wrapper/mem/dccm_wr_addr_lo[10]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_addr_lo[11] i:/WORK/quasar_wrapper/mem/dccm_wr_addr_lo[11]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_addr_lo[12] i:/WORK/quasar_wrapper/mem/dccm_wr_addr_lo[12]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_addr_lo[13] i:/WORK/quasar_wrapper/mem/dccm_wr_addr_lo[13]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_addr_lo[14] i:/WORK/quasar_wrapper/mem/dccm_wr_addr_lo[14]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_addr_lo[15] i:/WORK/quasar_wrapper/mem/dccm_wr_addr_lo[15]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_addr_lo[1] i:/WORK/quasar_wrapper/mem/dccm_wr_addr_lo[1]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_addr_lo[2] i:/WORK/quasar_wrapper/mem/dccm_wr_addr_lo[2]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_addr_lo[3] i:/WORK/quasar_wrapper/mem/dccm_wr_addr_lo[3]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_addr_lo[4] i:/WORK/quasar_wrapper/mem/dccm_wr_addr_lo[4]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_addr_lo[5] i:/WORK/quasar_wrapper/mem/dccm_wr_addr_lo[5]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_addr_lo[6] i:/WORK/quasar_wrapper/mem/dccm_wr_addr_lo[6]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_addr_lo[7] i:/WORK/quasar_wrapper/mem/dccm_wr_addr_lo[7]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_addr_lo[8] i:/WORK/quasar_wrapper/mem/dccm_wr_addr_lo[8]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_addr_lo[9] i:/WORK/quasar_wrapper/mem/dccm_wr_addr_lo[9]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_data_hi[0] i:/WORK/quasar_wrapper/mem/dccm_wr_data_hi[0]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_data_hi[10] i:/WORK/quasar_wrapper/mem/dccm_wr_data_hi[10]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_data_hi[11] i:/WORK/quasar_wrapper/mem/dccm_wr_data_hi[11]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_data_hi[12] i:/WORK/quasar_wrapper/mem/dccm_wr_data_hi[12]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_data_hi[13] i:/WORK/quasar_wrapper/mem/dccm_wr_data_hi[13]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_data_hi[14] i:/WORK/quasar_wrapper/mem/dccm_wr_data_hi[14]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_data_hi[15] i:/WORK/quasar_wrapper/mem/dccm_wr_data_hi[15]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_data_hi[16] i:/WORK/quasar_wrapper/mem/dccm_wr_data_hi[16]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_data_hi[17] i:/WORK/quasar_wrapper/mem/dccm_wr_data_hi[17]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_data_hi[18] i:/WORK/quasar_wrapper/mem/dccm_wr_data_hi[18]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_data_hi[19] i:/WORK/quasar_wrapper/mem/dccm_wr_data_hi[19]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_data_hi[1] i:/WORK/quasar_wrapper/mem/dccm_wr_data_hi[1]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_data_hi[20] i:/WORK/quasar_wrapper/mem/dccm_wr_data_hi[20]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_data_hi[21] i:/WORK/quasar_wrapper/mem/dccm_wr_data_hi[21]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_data_hi[22] i:/WORK/quasar_wrapper/mem/dccm_wr_data_hi[22]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_data_hi[23] i:/WORK/quasar_wrapper/mem/dccm_wr_data_hi[23]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_data_hi[24] i:/WORK/quasar_wrapper/mem/dccm_wr_data_hi[24]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_data_hi[25] i:/WORK/quasar_wrapper/mem/dccm_wr_data_hi[25]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_data_hi[26] i:/WORK/quasar_wrapper/mem/dccm_wr_data_hi[26]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_data_hi[27] i:/WORK/quasar_wrapper/mem/dccm_wr_data_hi[27]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_data_hi[28] i:/WORK/quasar_wrapper/mem/dccm_wr_data_hi[28]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_data_hi[29] i:/WORK/quasar_wrapper/mem/dccm_wr_data_hi[29]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_data_hi[2] i:/WORK/quasar_wrapper/mem/dccm_wr_data_hi[2]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_data_hi[30] i:/WORK/quasar_wrapper/mem/dccm_wr_data_hi[30]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_data_hi[31] i:/WORK/quasar_wrapper/mem/dccm_wr_data_hi[31]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_data_hi[32] i:/WORK/quasar_wrapper/mem/dccm_wr_data_hi[32]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_data_hi[33] i:/WORK/quasar_wrapper/mem/dccm_wr_data_hi[33]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_data_hi[34] i:/WORK/quasar_wrapper/mem/dccm_wr_data_hi[34]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_data_hi[35] i:/WORK/quasar_wrapper/mem/dccm_wr_data_hi[35]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_data_hi[36] i:/WORK/quasar_wrapper/mem/dccm_wr_data_hi[36]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_data_hi[37] i:/WORK/quasar_wrapper/mem/dccm_wr_data_hi[37]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_data_hi[38] i:/WORK/quasar_wrapper/mem/dccm_wr_data_hi[38]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_data_hi[3] i:/WORK/quasar_wrapper/mem/dccm_wr_data_hi[3]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_data_hi[4] i:/WORK/quasar_wrapper/mem/dccm_wr_data_hi[4]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_data_hi[5] i:/WORK/quasar_wrapper/mem/dccm_wr_data_hi[5]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_data_hi[6] i:/WORK/quasar_wrapper/mem/dccm_wr_data_hi[6]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_data_hi[7] i:/WORK/quasar_wrapper/mem/dccm_wr_data_hi[7]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_data_hi[8] i:/WORK/quasar_wrapper/mem/dccm_wr_data_hi[8]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_data_hi[9] i:/WORK/quasar_wrapper/mem/dccm_wr_data_hi[9]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_data_lo[0] i:/WORK/quasar_wrapper/mem/dccm_wr_data_lo[0]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_data_lo[10] i:/WORK/quasar_wrapper/mem/dccm_wr_data_lo[10]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_data_lo[11] i:/WORK/quasar_wrapper/mem/dccm_wr_data_lo[11]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_data_lo[12] i:/WORK/quasar_wrapper/mem/dccm_wr_data_lo[12]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_data_lo[13] i:/WORK/quasar_wrapper/mem/dccm_wr_data_lo[13]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_data_lo[14] i:/WORK/quasar_wrapper/mem/dccm_wr_data_lo[14]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_data_lo[15] i:/WORK/quasar_wrapper/mem/dccm_wr_data_lo[15]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_data_lo[16] i:/WORK/quasar_wrapper/mem/dccm_wr_data_lo[16]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_data_lo[17] i:/WORK/quasar_wrapper/mem/dccm_wr_data_lo[17]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_data_lo[18] i:/WORK/quasar_wrapper/mem/dccm_wr_data_lo[18]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_data_lo[19] i:/WORK/quasar_wrapper/mem/dccm_wr_data_lo[19]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_data_lo[1] i:/WORK/quasar_wrapper/mem/dccm_wr_data_lo[1]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_data_lo[20] i:/WORK/quasar_wrapper/mem/dccm_wr_data_lo[20]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_data_lo[21] i:/WORK/quasar_wrapper/mem/dccm_wr_data_lo[21]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_data_lo[22] i:/WORK/quasar_wrapper/mem/dccm_wr_data_lo[22]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_data_lo[23] i:/WORK/quasar_wrapper/mem/dccm_wr_data_lo[23]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_data_lo[24] i:/WORK/quasar_wrapper/mem/dccm_wr_data_lo[24]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_data_lo[25] i:/WORK/quasar_wrapper/mem/dccm_wr_data_lo[25]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_data_lo[26] i:/WORK/quasar_wrapper/mem/dccm_wr_data_lo[26]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_data_lo[27] i:/WORK/quasar_wrapper/mem/dccm_wr_data_lo[27]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_data_lo[28] i:/WORK/quasar_wrapper/mem/dccm_wr_data_lo[28]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_data_lo[29] i:/WORK/quasar_wrapper/mem/dccm_wr_data_lo[29]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_data_lo[2] i:/WORK/quasar_wrapper/mem/dccm_wr_data_lo[2]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_data_lo[30] i:/WORK/quasar_wrapper/mem/dccm_wr_data_lo[30]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_data_lo[31] i:/WORK/quasar_wrapper/mem/dccm_wr_data_lo[31]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_data_lo[32] i:/WORK/quasar_wrapper/mem/dccm_wr_data_lo[32]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_data_lo[33] i:/WORK/quasar_wrapper/mem/dccm_wr_data_lo[33]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_data_lo[34] i:/WORK/quasar_wrapper/mem/dccm_wr_data_lo[34]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_data_lo[35] i:/WORK/quasar_wrapper/mem/dccm_wr_data_lo[35]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_data_lo[36] i:/WORK/quasar_wrapper/mem/dccm_wr_data_lo[36]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_data_lo[37] i:/WORK/quasar_wrapper/mem/dccm_wr_data_lo[37]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_data_lo[38] i:/WORK/quasar_wrapper/mem/dccm_wr_data_lo[38]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_data_lo[3] i:/WORK/quasar_wrapper/mem/dccm_wr_data_lo[3]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_data_lo[4] i:/WORK/quasar_wrapper/mem/dccm_wr_data_lo[4]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_data_lo[5] i:/WORK/quasar_wrapper/mem/dccm_wr_data_lo[5]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_data_lo[6] i:/WORK/quasar_wrapper/mem/dccm_wr_data_lo[6]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_data_lo[7] i:/WORK/quasar_wrapper/mem/dccm_wr_data_lo[7]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_data_lo[8] i:/WORK/quasar_wrapper/mem/dccm_wr_data_lo[8]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wr_data_lo[9] i:/WORK/quasar_wrapper/mem/dccm_wr_data_lo[9]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_wren i:/WORK/quasar_wrapper/mem/dccm_wren
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dec_tlu_core_ecc_disable i:/WORK/quasar_wrapper/mem/dec_tlu_core_ecc_disable
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_data_ext_in_pkt[0][0]\[BC1] i:/WORK/quasar_wrapper/mem/ic_data_ext_in_pkt_0_BC1_0
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_data_ext_in_pkt[0][0]\[BC2] i:/WORK/quasar_wrapper/mem/ic_data_ext_in_pkt_0_BC2_0
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_data_ext_in_pkt[0][0]\[DS] i:/WORK/quasar_wrapper/mem/ic_data_ext_in_pkt_0_DS_0
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_data_ext_in_pkt[0][0]\[LS] i:/WORK/quasar_wrapper/mem/ic_data_ext_in_pkt_0_LS_0
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_data_ext_in_pkt[0][0]\[RME] i:/WORK/quasar_wrapper/mem/ic_data_ext_in_pkt_0_RME_0
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_data_ext_in_pkt[0][0]\[RM][0] i:/WORK/quasar_wrapper/mem/ic_data_ext_in_pkt_0_RM_0[0]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_data_ext_in_pkt[0][0]\[RM][1] i:/WORK/quasar_wrapper/mem/ic_data_ext_in_pkt_0_RM_0[1]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_data_ext_in_pkt[0][0]\[RM][2] i:/WORK/quasar_wrapper/mem/ic_data_ext_in_pkt_0_RM_0[2]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_data_ext_in_pkt[0][0]\[RM][3] i:/WORK/quasar_wrapper/mem/ic_data_ext_in_pkt_0_RM_0[3]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_data_ext_in_pkt[0][0]\[SD] i:/WORK/quasar_wrapper/mem/ic_data_ext_in_pkt_0_SD_0
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_data_ext_in_pkt[0][0]\[TEST1] i:/WORK/quasar_wrapper/mem/ic_data_ext_in_pkt_0_TEST1_0
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_data_ext_in_pkt[0][0]\[TEST_RNM] i:/WORK/quasar_wrapper/mem/ic_data_ext_in_pkt_0_TEST_RNM_0
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_data_ext_in_pkt[0][1]\[BC1] i:/WORK/quasar_wrapper/mem/ic_data_ext_in_pkt_0_BC1_1
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_data_ext_in_pkt[0][1]\[BC2] i:/WORK/quasar_wrapper/mem/ic_data_ext_in_pkt_0_BC2_1
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_data_ext_in_pkt[0][1]\[DS] i:/WORK/quasar_wrapper/mem/ic_data_ext_in_pkt_0_DS_1
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_data_ext_in_pkt[0][1]\[LS] i:/WORK/quasar_wrapper/mem/ic_data_ext_in_pkt_0_LS_1
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_data_ext_in_pkt[0][1]\[RME] i:/WORK/quasar_wrapper/mem/ic_data_ext_in_pkt_0_RME_1
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_data_ext_in_pkt[0][1]\[RM][0] i:/WORK/quasar_wrapper/mem/ic_data_ext_in_pkt_0_RM_1[0]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_data_ext_in_pkt[0][1]\[RM][1] i:/WORK/quasar_wrapper/mem/ic_data_ext_in_pkt_0_RM_1[1]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_data_ext_in_pkt[0][1]\[RM][2] i:/WORK/quasar_wrapper/mem/ic_data_ext_in_pkt_0_RM_1[2]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_data_ext_in_pkt[0][1]\[RM][3] i:/WORK/quasar_wrapper/mem/ic_data_ext_in_pkt_0_RM_1[3]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_data_ext_in_pkt[0][1]\[SD] i:/WORK/quasar_wrapper/mem/ic_data_ext_in_pkt_0_SD_1
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_data_ext_in_pkt[0][1]\[TEST1] i:/WORK/quasar_wrapper/mem/ic_data_ext_in_pkt_0_TEST1_1
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_data_ext_in_pkt[0][1]\[TEST_RNM] i:/WORK/quasar_wrapper/mem/ic_data_ext_in_pkt_0_TEST_RNM_1
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_data_ext_in_pkt[1][0]\[BC1] i:/WORK/quasar_wrapper/mem/ic_data_ext_in_pkt_1_BC1_0
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_data_ext_in_pkt[1][0]\[BC2] i:/WORK/quasar_wrapper/mem/ic_data_ext_in_pkt_1_BC2_0
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_data_ext_in_pkt[1][0]\[DS] i:/WORK/quasar_wrapper/mem/ic_data_ext_in_pkt_1_DS_0
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_data_ext_in_pkt[1][0]\[LS] i:/WORK/quasar_wrapper/mem/ic_data_ext_in_pkt_1_LS_0
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_data_ext_in_pkt[1][0]\[RME] i:/WORK/quasar_wrapper/mem/ic_data_ext_in_pkt_1_RME_0
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_data_ext_in_pkt[1][0]\[RM][0] i:/WORK/quasar_wrapper/mem/ic_data_ext_in_pkt_1_RM_0[0]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_data_ext_in_pkt[1][0]\[RM][1] i:/WORK/quasar_wrapper/mem/ic_data_ext_in_pkt_1_RM_0[1]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_data_ext_in_pkt[1][0]\[RM][2] i:/WORK/quasar_wrapper/mem/ic_data_ext_in_pkt_1_RM_0[2]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_data_ext_in_pkt[1][0]\[RM][3] i:/WORK/quasar_wrapper/mem/ic_data_ext_in_pkt_1_RM_0[3]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_data_ext_in_pkt[1][0]\[SD] i:/WORK/quasar_wrapper/mem/ic_data_ext_in_pkt_1_SD_0
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_data_ext_in_pkt[1][0]\[TEST1] i:/WORK/quasar_wrapper/mem/ic_data_ext_in_pkt_1_TEST1_0
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_data_ext_in_pkt[1][0]\[TEST_RNM] i:/WORK/quasar_wrapper/mem/ic_data_ext_in_pkt_1_TEST_RNM_0
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_data_ext_in_pkt[1][1]\[BC1] i:/WORK/quasar_wrapper/mem/ic_data_ext_in_pkt_1_BC1_1
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_data_ext_in_pkt[1][1]\[BC2] i:/WORK/quasar_wrapper/mem/ic_data_ext_in_pkt_1_BC2_1
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_data_ext_in_pkt[1][1]\[DS] i:/WORK/quasar_wrapper/mem/ic_data_ext_in_pkt_1_DS_1
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_data_ext_in_pkt[1][1]\[LS] i:/WORK/quasar_wrapper/mem/ic_data_ext_in_pkt_1_LS_1
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_data_ext_in_pkt[1][1]\[RME] i:/WORK/quasar_wrapper/mem/ic_data_ext_in_pkt_1_RME_1
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_data_ext_in_pkt[1][1]\[RM][0] i:/WORK/quasar_wrapper/mem/ic_data_ext_in_pkt_1_RM_1[0]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_data_ext_in_pkt[1][1]\[RM][1] i:/WORK/quasar_wrapper/mem/ic_data_ext_in_pkt_1_RM_1[1]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_data_ext_in_pkt[1][1]\[RM][2] i:/WORK/quasar_wrapper/mem/ic_data_ext_in_pkt_1_RM_1[2]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_data_ext_in_pkt[1][1]\[RM][3] i:/WORK/quasar_wrapper/mem/ic_data_ext_in_pkt_1_RM_1[3]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_data_ext_in_pkt[1][1]\[SD] i:/WORK/quasar_wrapper/mem/ic_data_ext_in_pkt_1_SD_1
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_data_ext_in_pkt[1][1]\[TEST1] i:/WORK/quasar_wrapper/mem/ic_data_ext_in_pkt_1_TEST1_1
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_data_ext_in_pkt[1][1]\[TEST_RNM] i:/WORK/quasar_wrapper/mem/ic_data_ext_in_pkt_1_TEST_RNM_1
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_addr[10] i:/WORK/quasar_wrapper/mem/ic_debug_addr[10]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_addr[11] i:/WORK/quasar_wrapper/mem/ic_debug_addr[11]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_addr[12] i:/WORK/quasar_wrapper/mem/ic_debug_addr[12]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_addr[3] i:/WORK/quasar_wrapper/mem/ic_debug_addr[3]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_addr[4] i:/WORK/quasar_wrapper/mem/ic_debug_addr[4]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_addr[5] i:/WORK/quasar_wrapper/mem/ic_debug_addr[5]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_addr[6] i:/WORK/quasar_wrapper/mem/ic_debug_addr[6]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_addr[7] i:/WORK/quasar_wrapper/mem/ic_debug_addr[7]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_addr[8] i:/WORK/quasar_wrapper/mem/ic_debug_addr[8]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_addr[9] i:/WORK/quasar_wrapper/mem/ic_debug_addr[9]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_rd_en i:/WORK/quasar_wrapper/mem/ic_debug_rd_en
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_tag_array i:/WORK/quasar_wrapper/mem/ic_debug_tag_array
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_way[0] i:/WORK/quasar_wrapper/mem/ic_debug_way[0]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_way[1] i:/WORK/quasar_wrapper/mem/ic_debug_way[1]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_wr_data[0] i:/WORK/quasar_wrapper/mem/ic_debug_wr_data[0]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_wr_data[10] i:/WORK/quasar_wrapper/mem/ic_debug_wr_data[10]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_wr_data[11] i:/WORK/quasar_wrapper/mem/ic_debug_wr_data[11]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_wr_data[12] i:/WORK/quasar_wrapper/mem/ic_debug_wr_data[12]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_wr_data[13] i:/WORK/quasar_wrapper/mem/ic_debug_wr_data[13]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_wr_data[14] i:/WORK/quasar_wrapper/mem/ic_debug_wr_data[14]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_wr_data[15] i:/WORK/quasar_wrapper/mem/ic_debug_wr_data[15]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_wr_data[16] i:/WORK/quasar_wrapper/mem/ic_debug_wr_data[16]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_wr_data[17] i:/WORK/quasar_wrapper/mem/ic_debug_wr_data[17]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_wr_data[18] i:/WORK/quasar_wrapper/mem/ic_debug_wr_data[18]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_wr_data[19] i:/WORK/quasar_wrapper/mem/ic_debug_wr_data[19]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_wr_data[1] i:/WORK/quasar_wrapper/mem/ic_debug_wr_data[1]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_wr_data[20] i:/WORK/quasar_wrapper/mem/ic_debug_wr_data[20]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_wr_data[21] i:/WORK/quasar_wrapper/mem/ic_debug_wr_data[21]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_wr_data[22] i:/WORK/quasar_wrapper/mem/ic_debug_wr_data[22]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_wr_data[23] i:/WORK/quasar_wrapper/mem/ic_debug_wr_data[23]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_wr_data[24] i:/WORK/quasar_wrapper/mem/ic_debug_wr_data[24]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_wr_data[25] i:/WORK/quasar_wrapper/mem/ic_debug_wr_data[25]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_wr_data[26] i:/WORK/quasar_wrapper/mem/ic_debug_wr_data[26]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_wr_data[27] i:/WORK/quasar_wrapper/mem/ic_debug_wr_data[27]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_wr_data[28] i:/WORK/quasar_wrapper/mem/ic_debug_wr_data[28]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_wr_data[29] i:/WORK/quasar_wrapper/mem/ic_debug_wr_data[29]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_wr_data[2] i:/WORK/quasar_wrapper/mem/ic_debug_wr_data[2]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_wr_data[30] i:/WORK/quasar_wrapper/mem/ic_debug_wr_data[30]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_wr_data[31] i:/WORK/quasar_wrapper/mem/ic_debug_wr_data[31]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_wr_data[32] i:/WORK/quasar_wrapper/mem/ic_debug_wr_data[32]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_wr_data[33] i:/WORK/quasar_wrapper/mem/ic_debug_wr_data[33]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_wr_data[34] i:/WORK/quasar_wrapper/mem/ic_debug_wr_data[34]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_wr_data[35] i:/WORK/quasar_wrapper/mem/ic_debug_wr_data[35]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_wr_data[36] i:/WORK/quasar_wrapper/mem/ic_debug_wr_data[36]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_wr_data[37] i:/WORK/quasar_wrapper/mem/ic_debug_wr_data[37]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_wr_data[38] i:/WORK/quasar_wrapper/mem/ic_debug_wr_data[38]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_wr_data[39] i:/WORK/quasar_wrapper/mem/ic_debug_wr_data[39]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_wr_data[3] i:/WORK/quasar_wrapper/mem/ic_debug_wr_data[3]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_wr_data[40] i:/WORK/quasar_wrapper/mem/ic_debug_wr_data[40]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_wr_data[41] i:/WORK/quasar_wrapper/mem/ic_debug_wr_data[41]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_wr_data[42] i:/WORK/quasar_wrapper/mem/ic_debug_wr_data[42]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_wr_data[43] i:/WORK/quasar_wrapper/mem/ic_debug_wr_data[43]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_wr_data[44] i:/WORK/quasar_wrapper/mem/ic_debug_wr_data[44]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_wr_data[45] i:/WORK/quasar_wrapper/mem/ic_debug_wr_data[45]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_wr_data[46] i:/WORK/quasar_wrapper/mem/ic_debug_wr_data[46]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_wr_data[47] i:/WORK/quasar_wrapper/mem/ic_debug_wr_data[47]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_wr_data[48] i:/WORK/quasar_wrapper/mem/ic_debug_wr_data[48]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_wr_data[49] i:/WORK/quasar_wrapper/mem/ic_debug_wr_data[49]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_wr_data[4] i:/WORK/quasar_wrapper/mem/ic_debug_wr_data[4]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_wr_data[50] i:/WORK/quasar_wrapper/mem/ic_debug_wr_data[50]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_wr_data[51] i:/WORK/quasar_wrapper/mem/ic_debug_wr_data[51]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_wr_data[52] i:/WORK/quasar_wrapper/mem/ic_debug_wr_data[52]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_wr_data[53] i:/WORK/quasar_wrapper/mem/ic_debug_wr_data[53]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_wr_data[54] i:/WORK/quasar_wrapper/mem/ic_debug_wr_data[54]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_wr_data[55] i:/WORK/quasar_wrapper/mem/ic_debug_wr_data[55]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_wr_data[56] i:/WORK/quasar_wrapper/mem/ic_debug_wr_data[56]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_wr_data[57] i:/WORK/quasar_wrapper/mem/ic_debug_wr_data[57]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_wr_data[58] i:/WORK/quasar_wrapper/mem/ic_debug_wr_data[58]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_wr_data[59] i:/WORK/quasar_wrapper/mem/ic_debug_wr_data[59]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_wr_data[5] i:/WORK/quasar_wrapper/mem/ic_debug_wr_data[5]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_wr_data[60] i:/WORK/quasar_wrapper/mem/ic_debug_wr_data[60]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_wr_data[61] i:/WORK/quasar_wrapper/mem/ic_debug_wr_data[61]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_wr_data[62] i:/WORK/quasar_wrapper/mem/ic_debug_wr_data[62]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_wr_data[63] i:/WORK/quasar_wrapper/mem/ic_debug_wr_data[63]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_wr_data[64] i:/WORK/quasar_wrapper/mem/ic_debug_wr_data[64]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_wr_data[65] i:/WORK/quasar_wrapper/mem/ic_debug_wr_data[65]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_wr_data[66] i:/WORK/quasar_wrapper/mem/ic_debug_wr_data[66]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_wr_data[67] i:/WORK/quasar_wrapper/mem/ic_debug_wr_data[67]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_wr_data[68] i:/WORK/quasar_wrapper/mem/ic_debug_wr_data[68]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_wr_data[69] i:/WORK/quasar_wrapper/mem/ic_debug_wr_data[69]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_wr_data[6] i:/WORK/quasar_wrapper/mem/ic_debug_wr_data[6]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_wr_data[70] i:/WORK/quasar_wrapper/mem/ic_debug_wr_data[70]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_wr_data[7] i:/WORK/quasar_wrapper/mem/ic_debug_wr_data[7]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_wr_data[8] i:/WORK/quasar_wrapper/mem/ic_debug_wr_data[8]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_wr_data[9] i:/WORK/quasar_wrapper/mem/ic_debug_wr_data[9]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_wr_en i:/WORK/quasar_wrapper/mem/ic_debug_wr_en
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_premux_data[0] i:/WORK/quasar_wrapper/mem/ic_premux_data[0]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_premux_data[10] i:/WORK/quasar_wrapper/mem/ic_premux_data[10]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_premux_data[11] i:/WORK/quasar_wrapper/mem/ic_premux_data[11]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_premux_data[12] i:/WORK/quasar_wrapper/mem/ic_premux_data[12]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_premux_data[13] i:/WORK/quasar_wrapper/mem/ic_premux_data[13]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_premux_data[14] i:/WORK/quasar_wrapper/mem/ic_premux_data[14]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_premux_data[15] i:/WORK/quasar_wrapper/mem/ic_premux_data[15]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_premux_data[16] i:/WORK/quasar_wrapper/mem/ic_premux_data[16]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_premux_data[17] i:/WORK/quasar_wrapper/mem/ic_premux_data[17]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_premux_data[18] i:/WORK/quasar_wrapper/mem/ic_premux_data[18]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_premux_data[19] i:/WORK/quasar_wrapper/mem/ic_premux_data[19]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_premux_data[1] i:/WORK/quasar_wrapper/mem/ic_premux_data[1]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_premux_data[20] i:/WORK/quasar_wrapper/mem/ic_premux_data[20]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_premux_data[21] i:/WORK/quasar_wrapper/mem/ic_premux_data[21]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_premux_data[22] i:/WORK/quasar_wrapper/mem/ic_premux_data[22]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_premux_data[23] i:/WORK/quasar_wrapper/mem/ic_premux_data[23]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_premux_data[24] i:/WORK/quasar_wrapper/mem/ic_premux_data[24]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_premux_data[25] i:/WORK/quasar_wrapper/mem/ic_premux_data[25]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_premux_data[26] i:/WORK/quasar_wrapper/mem/ic_premux_data[26]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_premux_data[27] i:/WORK/quasar_wrapper/mem/ic_premux_data[27]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_premux_data[28] i:/WORK/quasar_wrapper/mem/ic_premux_data[28]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_premux_data[29] i:/WORK/quasar_wrapper/mem/ic_premux_data[29]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_premux_data[2] i:/WORK/quasar_wrapper/mem/ic_premux_data[2]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_premux_data[30] i:/WORK/quasar_wrapper/mem/ic_premux_data[30]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_premux_data[31] i:/WORK/quasar_wrapper/mem/ic_premux_data[31]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_premux_data[32] i:/WORK/quasar_wrapper/mem/ic_premux_data[32]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_premux_data[33] i:/WORK/quasar_wrapper/mem/ic_premux_data[33]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_premux_data[34] i:/WORK/quasar_wrapper/mem/ic_premux_data[34]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_premux_data[35] i:/WORK/quasar_wrapper/mem/ic_premux_data[35]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_premux_data[36] i:/WORK/quasar_wrapper/mem/ic_premux_data[36]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_premux_data[37] i:/WORK/quasar_wrapper/mem/ic_premux_data[37]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_premux_data[38] i:/WORK/quasar_wrapper/mem/ic_premux_data[38]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_premux_data[39] i:/WORK/quasar_wrapper/mem/ic_premux_data[39]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_premux_data[3] i:/WORK/quasar_wrapper/mem/ic_premux_data[3]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_premux_data[40] i:/WORK/quasar_wrapper/mem/ic_premux_data[40]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_premux_data[41] i:/WORK/quasar_wrapper/mem/ic_premux_data[41]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_premux_data[42] i:/WORK/quasar_wrapper/mem/ic_premux_data[42]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_premux_data[43] i:/WORK/quasar_wrapper/mem/ic_premux_data[43]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_premux_data[44] i:/WORK/quasar_wrapper/mem/ic_premux_data[44]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_premux_data[45] i:/WORK/quasar_wrapper/mem/ic_premux_data[45]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_premux_data[46] i:/WORK/quasar_wrapper/mem/ic_premux_data[46]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_premux_data[47] i:/WORK/quasar_wrapper/mem/ic_premux_data[47]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_premux_data[48] i:/WORK/quasar_wrapper/mem/ic_premux_data[48]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_premux_data[49] i:/WORK/quasar_wrapper/mem/ic_premux_data[49]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_premux_data[4] i:/WORK/quasar_wrapper/mem/ic_premux_data[4]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_premux_data[50] i:/WORK/quasar_wrapper/mem/ic_premux_data[50]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_premux_data[51] i:/WORK/quasar_wrapper/mem/ic_premux_data[51]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_premux_data[52] i:/WORK/quasar_wrapper/mem/ic_premux_data[52]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_premux_data[53] i:/WORK/quasar_wrapper/mem/ic_premux_data[53]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_premux_data[54] i:/WORK/quasar_wrapper/mem/ic_premux_data[54]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_premux_data[55] i:/WORK/quasar_wrapper/mem/ic_premux_data[55]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_premux_data[56] i:/WORK/quasar_wrapper/mem/ic_premux_data[56]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_premux_data[57] i:/WORK/quasar_wrapper/mem/ic_premux_data[57]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_premux_data[58] i:/WORK/quasar_wrapper/mem/ic_premux_data[58]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_premux_data[59] i:/WORK/quasar_wrapper/mem/ic_premux_data[59]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_premux_data[5] i:/WORK/quasar_wrapper/mem/ic_premux_data[5]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_premux_data[60] i:/WORK/quasar_wrapper/mem/ic_premux_data[60]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_premux_data[61] i:/WORK/quasar_wrapper/mem/ic_premux_data[61]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_premux_data[62] i:/WORK/quasar_wrapper/mem/ic_premux_data[62]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_premux_data[63] i:/WORK/quasar_wrapper/mem/ic_premux_data[63]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_premux_data[6] i:/WORK/quasar_wrapper/mem/ic_premux_data[6]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_premux_data[7] i:/WORK/quasar_wrapper/mem/ic_premux_data[7]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_premux_data[8] i:/WORK/quasar_wrapper/mem/ic_premux_data[8]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_premux_data[9] i:/WORK/quasar_wrapper/mem/ic_premux_data[9]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rd_en i:/WORK/quasar_wrapper/mem/ic_rd_en
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rw_addr[10] i:/WORK/quasar_wrapper/mem/ic_rw_addr[10]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rw_addr[11] i:/WORK/quasar_wrapper/mem/ic_rw_addr[11]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rw_addr[12] i:/WORK/quasar_wrapper/mem/ic_rw_addr[12]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rw_addr[13] i:/WORK/quasar_wrapper/mem/ic_rw_addr[13]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rw_addr[14] i:/WORK/quasar_wrapper/mem/ic_rw_addr[14]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rw_addr[15] i:/WORK/quasar_wrapper/mem/ic_rw_addr[15]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rw_addr[16] i:/WORK/quasar_wrapper/mem/ic_rw_addr[16]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rw_addr[17] i:/WORK/quasar_wrapper/mem/ic_rw_addr[17]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rw_addr[18] i:/WORK/quasar_wrapper/mem/ic_rw_addr[18]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rw_addr[19] i:/WORK/quasar_wrapper/mem/ic_rw_addr[19]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rw_addr[1] i:/WORK/quasar_wrapper/mem/ic_rw_addr[1]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rw_addr[20] i:/WORK/quasar_wrapper/mem/ic_rw_addr[20]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rw_addr[21] i:/WORK/quasar_wrapper/mem/ic_rw_addr[21]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rw_addr[22] i:/WORK/quasar_wrapper/mem/ic_rw_addr[22]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rw_addr[23] i:/WORK/quasar_wrapper/mem/ic_rw_addr[23]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rw_addr[24] i:/WORK/quasar_wrapper/mem/ic_rw_addr[24]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rw_addr[25] i:/WORK/quasar_wrapper/mem/ic_rw_addr[25]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rw_addr[26] i:/WORK/quasar_wrapper/mem/ic_rw_addr[26]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rw_addr[27] i:/WORK/quasar_wrapper/mem/ic_rw_addr[27]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rw_addr[28] i:/WORK/quasar_wrapper/mem/ic_rw_addr[28]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rw_addr[29] i:/WORK/quasar_wrapper/mem/ic_rw_addr[29]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rw_addr[2] i:/WORK/quasar_wrapper/mem/ic_rw_addr[2]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rw_addr[30] i:/WORK/quasar_wrapper/mem/ic_rw_addr[30]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rw_addr[31] i:/WORK/quasar_wrapper/mem/ic_rw_addr[31]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rw_addr[3] i:/WORK/quasar_wrapper/mem/ic_rw_addr[3]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rw_addr[4] i:/WORK/quasar_wrapper/mem/ic_rw_addr[4]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rw_addr[5] i:/WORK/quasar_wrapper/mem/ic_rw_addr[5]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rw_addr[6] i:/WORK/quasar_wrapper/mem/ic_rw_addr[6]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rw_addr[7] i:/WORK/quasar_wrapper/mem/ic_rw_addr[7]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rw_addr[8] i:/WORK/quasar_wrapper/mem/ic_rw_addr[8]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rw_addr[9] i:/WORK/quasar_wrapper/mem/ic_rw_addr[9]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_sel_premux_data i:/WORK/quasar_wrapper/mem/ic_sel_premux_data
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_tag_ext_in_pkt[0]\[BC1] i:/WORK/quasar_wrapper/mem/ic_tag_ext_in_pkt_BC1_0
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_tag_ext_in_pkt[0]\[BC2] i:/WORK/quasar_wrapper/mem/ic_tag_ext_in_pkt_BC2_0
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_tag_ext_in_pkt[0]\[DS] i:/WORK/quasar_wrapper/mem/ic_tag_ext_in_pkt_DS_0
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_tag_ext_in_pkt[0]\[LS] i:/WORK/quasar_wrapper/mem/ic_tag_ext_in_pkt_LS_0
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_tag_ext_in_pkt[0]\[RME] i:/WORK/quasar_wrapper/mem/ic_tag_ext_in_pkt_RME_0
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_tag_ext_in_pkt[0]\[RM][0] i:/WORK/quasar_wrapper/mem/ic_tag_ext_in_pkt_RM_0[0]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_tag_ext_in_pkt[0]\[RM][1] i:/WORK/quasar_wrapper/mem/ic_tag_ext_in_pkt_RM_1[0]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_tag_ext_in_pkt[0]\[RM][2] i:/WORK/quasar_wrapper/mem/ic_tag_ext_in_pkt_RM_0[2]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_tag_ext_in_pkt[0]\[RM][3] i:/WORK/quasar_wrapper/mem/ic_tag_ext_in_pkt_RM_0[3]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_tag_ext_in_pkt[0]\[SD] i:/WORK/quasar_wrapper/mem/ic_tag_ext_in_pkt_SD_0
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_tag_ext_in_pkt[0]\[TEST1] i:/WORK/quasar_wrapper/mem/ic_tag_ext_in_pkt_TEST1_0
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_tag_ext_in_pkt[0]\[TEST_RNM] i:/WORK/quasar_wrapper/mem/ic_tag_ext_in_pkt_TEST_RNM_0
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_tag_ext_in_pkt[1]\[BC1] i:/WORK/quasar_wrapper/mem/ic_tag_ext_in_pkt_BC1_1
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_tag_ext_in_pkt[1]\[BC2] i:/WORK/quasar_wrapper/mem/ic_tag_ext_in_pkt_BC2_1
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_tag_ext_in_pkt[1]\[DS] i:/WORK/quasar_wrapper/mem/ic_tag_ext_in_pkt_DS_1
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_tag_ext_in_pkt[1]\[LS] i:/WORK/quasar_wrapper/mem/ic_tag_ext_in_pkt_LS_1
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_tag_ext_in_pkt[1]\[RME] i:/WORK/quasar_wrapper/mem/ic_tag_ext_in_pkt_RME_1
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_tag_ext_in_pkt[1]\[RM][0] i:/WORK/quasar_wrapper/mem/ic_tag_ext_in_pkt_RM_0[1]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_tag_ext_in_pkt[1]\[RM][1] i:/WORK/quasar_wrapper/mem/ic_tag_ext_in_pkt_RM_1[1]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_tag_ext_in_pkt[1]\[RM][2] i:/WORK/quasar_wrapper/mem/ic_tag_ext_in_pkt_RM_1[2]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_tag_ext_in_pkt[1]\[RM][3] i:/WORK/quasar_wrapper/mem/ic_tag_ext_in_pkt_RM_1[3]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_tag_ext_in_pkt[1]\[SD] i:/WORK/quasar_wrapper/mem/ic_tag_ext_in_pkt_SD_1
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_tag_ext_in_pkt[1]\[TEST1] i:/WORK/quasar_wrapper/mem/ic_tag_ext_in_pkt_TEST1_1
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_tag_ext_in_pkt[1]\[TEST_RNM] i:/WORK/quasar_wrapper/mem/ic_tag_ext_in_pkt_TEST_RNM_1
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_tag_valid[0] i:/WORK/quasar_wrapper/mem/ic_tag_valid[0]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_tag_valid[1] i:/WORK/quasar_wrapper/mem/ic_tag_valid[1]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[0][0] i:/WORK/quasar_wrapper/mem/ic_wr_data_0[0]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[0][10] i:/WORK/quasar_wrapper/mem/ic_wr_data_0[10]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[0][11] i:/WORK/quasar_wrapper/mem/ic_wr_data_0[11]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[0][12] i:/WORK/quasar_wrapper/mem/ic_wr_data_0[12]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[0][13] i:/WORK/quasar_wrapper/mem/ic_wr_data_0[13]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[0][14] i:/WORK/quasar_wrapper/mem/ic_wr_data_0[14]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[0][15] i:/WORK/quasar_wrapper/mem/ic_wr_data_0[15]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[0][16] i:/WORK/quasar_wrapper/mem/ic_wr_data_0[16]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[0][17] i:/WORK/quasar_wrapper/mem/ic_wr_data_0[17]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[0][18] i:/WORK/quasar_wrapper/mem/ic_wr_data_0[18]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[0][19] i:/WORK/quasar_wrapper/mem/ic_wr_data_0[19]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[0][1] i:/WORK/quasar_wrapper/mem/ic_wr_data_0[1]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[0][20] i:/WORK/quasar_wrapper/mem/ic_wr_data_0[20]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[0][21] i:/WORK/quasar_wrapper/mem/ic_wr_data_0[21]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[0][22] i:/WORK/quasar_wrapper/mem/ic_wr_data_0[22]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[0][23] i:/WORK/quasar_wrapper/mem/ic_wr_data_0[23]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[0][24] i:/WORK/quasar_wrapper/mem/ic_wr_data_0[24]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[0][25] i:/WORK/quasar_wrapper/mem/ic_wr_data_0[25]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[0][26] i:/WORK/quasar_wrapper/mem/ic_wr_data_0[26]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[0][27] i:/WORK/quasar_wrapper/mem/ic_wr_data_0[27]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[0][28] i:/WORK/quasar_wrapper/mem/ic_wr_data_0[28]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[0][29] i:/WORK/quasar_wrapper/mem/ic_wr_data_0[29]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[0][2] i:/WORK/quasar_wrapper/mem/ic_wr_data_0[2]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[0][30] i:/WORK/quasar_wrapper/mem/ic_wr_data_0[30]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[0][31] i:/WORK/quasar_wrapper/mem/ic_wr_data_0[31]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[0][32] i:/WORK/quasar_wrapper/mem/ic_wr_data_0[32]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[0][33] i:/WORK/quasar_wrapper/mem/ic_wr_data_0[33]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[0][34] i:/WORK/quasar_wrapper/mem/ic_wr_data_0[34]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[0][35] i:/WORK/quasar_wrapper/mem/ic_wr_data_0[35]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[0][36] i:/WORK/quasar_wrapper/mem/ic_wr_data_0[36]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[0][37] i:/WORK/quasar_wrapper/mem/ic_wr_data_0[37]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[0][38] i:/WORK/quasar_wrapper/mem/ic_wr_data_0[38]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[0][39] i:/WORK/quasar_wrapper/mem/ic_wr_data_0[39]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[0][3] i:/WORK/quasar_wrapper/mem/ic_wr_data_0[3]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[0][40] i:/WORK/quasar_wrapper/mem/ic_wr_data_0[40]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[0][41] i:/WORK/quasar_wrapper/mem/ic_wr_data_0[41]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[0][42] i:/WORK/quasar_wrapper/mem/ic_wr_data_0[42]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[0][43] i:/WORK/quasar_wrapper/mem/ic_wr_data_0[43]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[0][44] i:/WORK/quasar_wrapper/mem/ic_wr_data_0[44]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[0][45] i:/WORK/quasar_wrapper/mem/ic_wr_data_0[45]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[0][46] i:/WORK/quasar_wrapper/mem/ic_wr_data_0[46]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[0][47] i:/WORK/quasar_wrapper/mem/ic_wr_data_0[47]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[0][48] i:/WORK/quasar_wrapper/mem/ic_wr_data_0[48]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[0][49] i:/WORK/quasar_wrapper/mem/ic_wr_data_0[49]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[0][4] i:/WORK/quasar_wrapper/mem/ic_wr_data_0[4]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[0][50] i:/WORK/quasar_wrapper/mem/ic_wr_data_0[50]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[0][51] i:/WORK/quasar_wrapper/mem/ic_wr_data_0[51]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[0][52] i:/WORK/quasar_wrapper/mem/ic_wr_data_0[52]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[0][53] i:/WORK/quasar_wrapper/mem/ic_wr_data_0[53]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[0][54] i:/WORK/quasar_wrapper/mem/ic_wr_data_0[54]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[0][55] i:/WORK/quasar_wrapper/mem/ic_wr_data_0[55]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[0][56] i:/WORK/quasar_wrapper/mem/ic_wr_data_0[56]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[0][57] i:/WORK/quasar_wrapper/mem/ic_wr_data_0[57]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[0][58] i:/WORK/quasar_wrapper/mem/ic_wr_data_0[58]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[0][59] i:/WORK/quasar_wrapper/mem/ic_wr_data_0[59]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[0][5] i:/WORK/quasar_wrapper/mem/ic_wr_data_0[5]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[0][60] i:/WORK/quasar_wrapper/mem/ic_wr_data_0[60]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[0][61] i:/WORK/quasar_wrapper/mem/ic_wr_data_0[61]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[0][62] i:/WORK/quasar_wrapper/mem/ic_wr_data_0[62]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[0][63] i:/WORK/quasar_wrapper/mem/ic_wr_data_0[63]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[0][64] i:/WORK/quasar_wrapper/mem/ic_wr_data_0[64]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[0][65] i:/WORK/quasar_wrapper/mem/ic_wr_data_0[65]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[0][66] i:/WORK/quasar_wrapper/mem/ic_wr_data_0[66]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[0][67] i:/WORK/quasar_wrapper/mem/ic_wr_data_0[67]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[0][68] i:/WORK/quasar_wrapper/mem/ic_wr_data_0[68]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[0][69] i:/WORK/quasar_wrapper/mem/ic_wr_data_0[69]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[0][6] i:/WORK/quasar_wrapper/mem/ic_wr_data_0[6]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[0][70] i:/WORK/quasar_wrapper/mem/ic_wr_data_0[70]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[0][7] i:/WORK/quasar_wrapper/mem/ic_wr_data_0[7]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[0][8] i:/WORK/quasar_wrapper/mem/ic_wr_data_0[8]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[0][9] i:/WORK/quasar_wrapper/mem/ic_wr_data_0[9]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[1][0] i:/WORK/quasar_wrapper/mem/ic_wr_data_1[0]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[1][10] i:/WORK/quasar_wrapper/mem/ic_wr_data_1[10]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[1][11] i:/WORK/quasar_wrapper/mem/ic_wr_data_1[11]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[1][12] i:/WORK/quasar_wrapper/mem/ic_wr_data_1[12]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[1][13] i:/WORK/quasar_wrapper/mem/ic_wr_data_1[13]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[1][14] i:/WORK/quasar_wrapper/mem/ic_wr_data_1[14]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[1][15] i:/WORK/quasar_wrapper/mem/ic_wr_data_1[15]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[1][16] i:/WORK/quasar_wrapper/mem/ic_wr_data_1[16]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[1][17] i:/WORK/quasar_wrapper/mem/ic_wr_data_1[17]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[1][18] i:/WORK/quasar_wrapper/mem/ic_wr_data_1[18]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[1][19] i:/WORK/quasar_wrapper/mem/ic_wr_data_1[19]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[1][1] i:/WORK/quasar_wrapper/mem/ic_wr_data_1[1]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[1][20] i:/WORK/quasar_wrapper/mem/ic_wr_data_1[20]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[1][21] i:/WORK/quasar_wrapper/mem/ic_wr_data_1[21]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[1][22] i:/WORK/quasar_wrapper/mem/ic_wr_data_1[22]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[1][23] i:/WORK/quasar_wrapper/mem/ic_wr_data_1[23]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[1][24] i:/WORK/quasar_wrapper/mem/ic_wr_data_1[24]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[1][25] i:/WORK/quasar_wrapper/mem/ic_wr_data_1[25]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[1][26] i:/WORK/quasar_wrapper/mem/ic_wr_data_1[26]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[1][27] i:/WORK/quasar_wrapper/mem/ic_wr_data_1[27]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[1][28] i:/WORK/quasar_wrapper/mem/ic_wr_data_1[28]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[1][29] i:/WORK/quasar_wrapper/mem/ic_wr_data_1[29]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[1][2] i:/WORK/quasar_wrapper/mem/ic_wr_data_1[2]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[1][30] i:/WORK/quasar_wrapper/mem/ic_wr_data_1[30]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[1][31] i:/WORK/quasar_wrapper/mem/ic_wr_data_1[31]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[1][32] i:/WORK/quasar_wrapper/mem/ic_wr_data_1[32]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[1][33] i:/WORK/quasar_wrapper/mem/ic_wr_data_1[33]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[1][34] i:/WORK/quasar_wrapper/mem/ic_wr_data_1[34]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[1][35] i:/WORK/quasar_wrapper/mem/ic_wr_data_1[35]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[1][36] i:/WORK/quasar_wrapper/mem/ic_wr_data_1[36]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[1][37] i:/WORK/quasar_wrapper/mem/ic_wr_data_1[37]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[1][38] i:/WORK/quasar_wrapper/mem/ic_wr_data_1[38]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[1][39] i:/WORK/quasar_wrapper/mem/ic_wr_data_1[39]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[1][3] i:/WORK/quasar_wrapper/mem/ic_wr_data_1[3]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[1][40] i:/WORK/quasar_wrapper/mem/ic_wr_data_1[40]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[1][41] i:/WORK/quasar_wrapper/mem/ic_wr_data_1[41]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[1][42] i:/WORK/quasar_wrapper/mem/ic_wr_data_1[42]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[1][43] i:/WORK/quasar_wrapper/mem/ic_wr_data_1[43]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[1][44] i:/WORK/quasar_wrapper/mem/ic_wr_data_1[44]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[1][45] i:/WORK/quasar_wrapper/mem/ic_wr_data_1[45]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[1][46] i:/WORK/quasar_wrapper/mem/ic_wr_data_1[46]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[1][47] i:/WORK/quasar_wrapper/mem/ic_wr_data_1[47]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[1][48] i:/WORK/quasar_wrapper/mem/ic_wr_data_1[48]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[1][49] i:/WORK/quasar_wrapper/mem/ic_wr_data_1[49]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[1][4] i:/WORK/quasar_wrapper/mem/ic_wr_data_1[4]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[1][50] i:/WORK/quasar_wrapper/mem/ic_wr_data_1[50]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[1][51] i:/WORK/quasar_wrapper/mem/ic_wr_data_1[51]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[1][52] i:/WORK/quasar_wrapper/mem/ic_wr_data_1[52]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[1][53] i:/WORK/quasar_wrapper/mem/ic_wr_data_1[53]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[1][54] i:/WORK/quasar_wrapper/mem/ic_wr_data_1[54]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[1][55] i:/WORK/quasar_wrapper/mem/ic_wr_data_1[55]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[1][56] i:/WORK/quasar_wrapper/mem/ic_wr_data_1[56]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[1][57] i:/WORK/quasar_wrapper/mem/ic_wr_data_1[57]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[1][58] i:/WORK/quasar_wrapper/mem/ic_wr_data_1[58]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[1][59] i:/WORK/quasar_wrapper/mem/ic_wr_data_1[59]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[1][5] i:/WORK/quasar_wrapper/mem/ic_wr_data_1[5]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[1][60] i:/WORK/quasar_wrapper/mem/ic_wr_data_1[60]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[1][61] i:/WORK/quasar_wrapper/mem/ic_wr_data_1[61]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[1][62] i:/WORK/quasar_wrapper/mem/ic_wr_data_1[62]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[1][63] i:/WORK/quasar_wrapper/mem/ic_wr_data_1[63]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[1][64] i:/WORK/quasar_wrapper/mem/ic_wr_data_1[64]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[1][65] i:/WORK/quasar_wrapper/mem/ic_wr_data_1[65]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[1][66] i:/WORK/quasar_wrapper/mem/ic_wr_data_1[66]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[1][67] i:/WORK/quasar_wrapper/mem/ic_wr_data_1[67]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[1][68] i:/WORK/quasar_wrapper/mem/ic_wr_data_1[68]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[1][69] i:/WORK/quasar_wrapper/mem/ic_wr_data_1[69]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[1][6] i:/WORK/quasar_wrapper/mem/ic_wr_data_1[6]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[1][70] i:/WORK/quasar_wrapper/mem/ic_wr_data_1[70]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[1][7] i:/WORK/quasar_wrapper/mem/ic_wr_data_1[7]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[1][8] i:/WORK/quasar_wrapper/mem/ic_wr_data_1[8]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_data[1][9] i:/WORK/quasar_wrapper/mem/ic_wr_data_1[9]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_en[0] i:/WORK/quasar_wrapper/mem/ic_wr_en[0]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_wr_en[1] i:/WORK/quasar_wrapper/mem/ic_wr_en[1]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_buf_correct_ecc i:/WORK/quasar_wrapper/mem/iccm_buf_correct_ecc
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_correction_state i:/WORK/quasar_wrapper/mem/iccm_correction_state
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_ext_in_pkt[0]\[BC1] i:/WORK/quasar_wrapper/mem/iccm_ext_in_pkt_BC1_0
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_ext_in_pkt[0]\[BC2] i:/WORK/quasar_wrapper/mem/iccm_ext_in_pkt_BC1_1
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_ext_in_pkt[0]\[DS] i:/WORK/quasar_wrapper/mem/iccm_ext_in_pkt_BC1_2
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_ext_in_pkt[0]\[LS] i:/WORK/quasar_wrapper/mem/iccm_ext_in_pkt_BC1_3
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_ext_in_pkt[0]\[RME] i:/WORK/quasar_wrapper/mem/iccm_ext_in_pkt_BC2_0
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_ext_in_pkt[0]\[RM][0] i:/WORK/quasar_wrapper/mem/iccm_ext_in_pkt_RM_0[0]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_ext_in_pkt[0]\[RM][1] i:/WORK/quasar_wrapper/mem/iccm_ext_in_pkt_RM_1[0]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_ext_in_pkt[0]\[RM][2] i:/WORK/quasar_wrapper/mem/iccm_ext_in_pkt_RM_2[0]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_ext_in_pkt[0]\[RM][3] i:/WORK/quasar_wrapper/mem/iccm_ext_in_pkt_RM_3[0]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_ext_in_pkt[0]\[SD] i:/WORK/quasar_wrapper/mem/iccm_ext_in_pkt_BC2_1
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_ext_in_pkt[0]\[TEST1] i:/WORK/quasar_wrapper/mem/iccm_ext_in_pkt_BC2_2
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_ext_in_pkt[0]\[TEST_RNM] i:/WORK/quasar_wrapper/mem/iccm_ext_in_pkt_BC2_3
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_ext_in_pkt[1]\[BC1] i:/WORK/quasar_wrapper/mem/iccm_ext_in_pkt_DS_0
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_ext_in_pkt[1]\[BC2] i:/WORK/quasar_wrapper/mem/iccm_ext_in_pkt_DS_1
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_ext_in_pkt[1]\[DS] i:/WORK/quasar_wrapper/mem/iccm_ext_in_pkt_DS_2
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_ext_in_pkt[1]\[LS] i:/WORK/quasar_wrapper/mem/iccm_ext_in_pkt_DS_3
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_ext_in_pkt[1]\[RME] i:/WORK/quasar_wrapper/mem/iccm_ext_in_pkt_LS_0
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_ext_in_pkt[1]\[RM][0] i:/WORK/quasar_wrapper/mem/iccm_ext_in_pkt_RM_0[1]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_ext_in_pkt[1]\[RM][1] i:/WORK/quasar_wrapper/mem/iccm_ext_in_pkt_RM_1[1]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_ext_in_pkt[1]\[RM][2] i:/WORK/quasar_wrapper/mem/iccm_ext_in_pkt_RM_2[1]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_ext_in_pkt[1]\[RM][3] i:/WORK/quasar_wrapper/mem/iccm_ext_in_pkt_RM_3[1]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_ext_in_pkt[1]\[SD] i:/WORK/quasar_wrapper/mem/iccm_ext_in_pkt_LS_1
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_ext_in_pkt[1]\[TEST1] i:/WORK/quasar_wrapper/mem/iccm_ext_in_pkt_LS_2
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_ext_in_pkt[1]\[TEST_RNM] i:/WORK/quasar_wrapper/mem/iccm_ext_in_pkt_LS_3
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_ext_in_pkt[2]\[BC1] i:/WORK/quasar_wrapper/mem/iccm_ext_in_pkt_RME_0
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_ext_in_pkt[2]\[BC2] i:/WORK/quasar_wrapper/mem/iccm_ext_in_pkt_RME_1
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_ext_in_pkt[2]\[DS] i:/WORK/quasar_wrapper/mem/iccm_ext_in_pkt_RME_2
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_ext_in_pkt[2]\[LS] i:/WORK/quasar_wrapper/mem/iccm_ext_in_pkt_RME_3
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_ext_in_pkt[2]\[RME] i:/WORK/quasar_wrapper/mem/iccm_ext_in_pkt_RM_0[2]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_ext_in_pkt[2]\[RM][0] i:/WORK/quasar_wrapper/mem/iccm_ext_in_pkt_RM_0[3]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_ext_in_pkt[2]\[RM][1] i:/WORK/quasar_wrapper/mem/iccm_ext_in_pkt_RM_1[2]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_ext_in_pkt[2]\[RM][2] i:/WORK/quasar_wrapper/mem/iccm_ext_in_pkt_RM_1[3]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_ext_in_pkt[2]\[RM][3] i:/WORK/quasar_wrapper/mem/iccm_ext_in_pkt_RM_2[2]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_ext_in_pkt[2]\[SD] i:/WORK/quasar_wrapper/mem/iccm_ext_in_pkt_RM_2[3]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_ext_in_pkt[2]\[TEST1] i:/WORK/quasar_wrapper/mem/iccm_ext_in_pkt_RM_3[2]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_ext_in_pkt[2]\[TEST_RNM] i:/WORK/quasar_wrapper/mem/iccm_ext_in_pkt_RM_3[3]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_ext_in_pkt[3]\[BC1] i:/WORK/quasar_wrapper/mem/iccm_ext_in_pkt_SD_0
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_ext_in_pkt[3]\[BC2] i:/WORK/quasar_wrapper/mem/iccm_ext_in_pkt_SD_1
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_ext_in_pkt[3]\[DS] i:/WORK/quasar_wrapper/mem/iccm_ext_in_pkt_SD_2
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_ext_in_pkt[3]\[LS] i:/WORK/quasar_wrapper/mem/iccm_ext_in_pkt_SD_3
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_ext_in_pkt[3]\[RME] i:/WORK/quasar_wrapper/mem/iccm_ext_in_pkt_TEST1_0
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_ext_in_pkt[3]\[RM][0] i:/WORK/quasar_wrapper/mem/iccm_ext_in_pkt_TEST1_1
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_ext_in_pkt[3]\[RM][1] i:/WORK/quasar_wrapper/mem/iccm_ext_in_pkt_TEST1_2
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_ext_in_pkt[3]\[RM][2] i:/WORK/quasar_wrapper/mem/iccm_ext_in_pkt_TEST1_3
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_ext_in_pkt[3]\[RM][3] i:/WORK/quasar_wrapper/mem/iccm_ext_in_pkt_TEST_RNM_0
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_ext_in_pkt[3]\[SD] i:/WORK/quasar_wrapper/mem/iccm_ext_in_pkt_TEST_RNM_1
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_ext_in_pkt[3]\[TEST1] i:/WORK/quasar_wrapper/mem/iccm_ext_in_pkt_TEST_RNM_2
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_ext_in_pkt[3]\[TEST_RNM] i:/WORK/quasar_wrapper/mem/iccm_ext_in_pkt_TEST_RNM_3
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rden i:/WORK/quasar_wrapper/mem/iccm_rden
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rw_addr[10] i:/WORK/quasar_wrapper/mem/iccm_rw_addr[10]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rw_addr[11] i:/WORK/quasar_wrapper/mem/iccm_rw_addr[11]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rw_addr[12] i:/WORK/quasar_wrapper/mem/iccm_rw_addr[12]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rw_addr[13] i:/WORK/quasar_wrapper/mem/iccm_rw_addr[13]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rw_addr[14] i:/WORK/quasar_wrapper/mem/iccm_rw_addr[14]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rw_addr[15] i:/WORK/quasar_wrapper/mem/iccm_rw_addr[15]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rw_addr[1] i:/WORK/quasar_wrapper/mem/iccm_rw_addr[1]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rw_addr[2] i:/WORK/quasar_wrapper/mem/iccm_rw_addr[2]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rw_addr[3] i:/WORK/quasar_wrapper/mem/iccm_rw_addr[3]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rw_addr[4] i:/WORK/quasar_wrapper/mem/iccm_rw_addr[4]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rw_addr[5] i:/WORK/quasar_wrapper/mem/iccm_rw_addr[5]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rw_addr[6] i:/WORK/quasar_wrapper/mem/iccm_rw_addr[6]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rw_addr[7] i:/WORK/quasar_wrapper/mem/iccm_rw_addr[7]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rw_addr[8] i:/WORK/quasar_wrapper/mem/iccm_rw_addr[8]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rw_addr[9] i:/WORK/quasar_wrapper/mem/iccm_rw_addr[9]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_data[0] i:/WORK/quasar_wrapper/mem/iccm_wr_data[0]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_data[10] i:/WORK/quasar_wrapper/mem/iccm_wr_data[10]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_data[11] i:/WORK/quasar_wrapper/mem/iccm_wr_data[11]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_data[12] i:/WORK/quasar_wrapper/mem/iccm_wr_data[12]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_data[13] i:/WORK/quasar_wrapper/mem/iccm_wr_data[13]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_data[14] i:/WORK/quasar_wrapper/mem/iccm_wr_data[14]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_data[15] i:/WORK/quasar_wrapper/mem/iccm_wr_data[15]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_data[16] i:/WORK/quasar_wrapper/mem/iccm_wr_data[16]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_data[17] i:/WORK/quasar_wrapper/mem/iccm_wr_data[17]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_data[18] i:/WORK/quasar_wrapper/mem/iccm_wr_data[18]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_data[19] i:/WORK/quasar_wrapper/mem/iccm_wr_data[19]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_data[1] i:/WORK/quasar_wrapper/mem/iccm_wr_data[1]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_data[20] i:/WORK/quasar_wrapper/mem/iccm_wr_data[20]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_data[21] i:/WORK/quasar_wrapper/mem/iccm_wr_data[21]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_data[22] i:/WORK/quasar_wrapper/mem/iccm_wr_data[22]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_data[23] i:/WORK/quasar_wrapper/mem/iccm_wr_data[23]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_data[24] i:/WORK/quasar_wrapper/mem/iccm_wr_data[24]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_data[25] i:/WORK/quasar_wrapper/mem/iccm_wr_data[25]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_data[26] i:/WORK/quasar_wrapper/mem/iccm_wr_data[26]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_data[27] i:/WORK/quasar_wrapper/mem/iccm_wr_data[27]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_data[28] i:/WORK/quasar_wrapper/mem/iccm_wr_data[28]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_data[29] i:/WORK/quasar_wrapper/mem/iccm_wr_data[29]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_data[2] i:/WORK/quasar_wrapper/mem/iccm_wr_data[2]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_data[30] i:/WORK/quasar_wrapper/mem/iccm_wr_data[30]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_data[31] i:/WORK/quasar_wrapper/mem/iccm_wr_data[31]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_data[32] i:/WORK/quasar_wrapper/mem/iccm_wr_data[32]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_data[33] i:/WORK/quasar_wrapper/mem/iccm_wr_data[33]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_data[34] i:/WORK/quasar_wrapper/mem/iccm_wr_data[34]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_data[35] i:/WORK/quasar_wrapper/mem/iccm_wr_data[35]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_data[36] i:/WORK/quasar_wrapper/mem/iccm_wr_data[36]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_data[37] i:/WORK/quasar_wrapper/mem/iccm_wr_data[37]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_data[38] i:/WORK/quasar_wrapper/mem/iccm_wr_data[38]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_data[39] i:/WORK/quasar_wrapper/mem/iccm_wr_data[39]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_data[3] i:/WORK/quasar_wrapper/mem/iccm_wr_data[3]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_data[40] i:/WORK/quasar_wrapper/mem/iccm_wr_data[40]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_data[41] i:/WORK/quasar_wrapper/mem/iccm_wr_data[41]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_data[42] i:/WORK/quasar_wrapper/mem/iccm_wr_data[42]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_data[43] i:/WORK/quasar_wrapper/mem/iccm_wr_data[43]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_data[44] i:/WORK/quasar_wrapper/mem/iccm_wr_data[44]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_data[45] i:/WORK/quasar_wrapper/mem/iccm_wr_data[45]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_data[46] i:/WORK/quasar_wrapper/mem/iccm_wr_data[46]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_data[47] i:/WORK/quasar_wrapper/mem/iccm_wr_data[47]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_data[48] i:/WORK/quasar_wrapper/mem/iccm_wr_data[48]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_data[49] i:/WORK/quasar_wrapper/mem/iccm_wr_data[49]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_data[4] i:/WORK/quasar_wrapper/mem/iccm_wr_data[4]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_data[50] i:/WORK/quasar_wrapper/mem/iccm_wr_data[50]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_data[51] i:/WORK/quasar_wrapper/mem/iccm_wr_data[51]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_data[52] i:/WORK/quasar_wrapper/mem/iccm_wr_data[52]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_data[53] i:/WORK/quasar_wrapper/mem/iccm_wr_data[53]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_data[54] i:/WORK/quasar_wrapper/mem/iccm_wr_data[54]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_data[55] i:/WORK/quasar_wrapper/mem/iccm_wr_data[55]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_data[56] i:/WORK/quasar_wrapper/mem/iccm_wr_data[56]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_data[57] i:/WORK/quasar_wrapper/mem/iccm_wr_data[57]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_data[58] i:/WORK/quasar_wrapper/mem/iccm_wr_data[58]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_data[59] i:/WORK/quasar_wrapper/mem/iccm_wr_data[59]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_data[5] i:/WORK/quasar_wrapper/mem/iccm_wr_data[5]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_data[60] i:/WORK/quasar_wrapper/mem/iccm_wr_data[60]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_data[61] i:/WORK/quasar_wrapper/mem/iccm_wr_data[61]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_data[62] i:/WORK/quasar_wrapper/mem/iccm_wr_data[62]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_data[63] i:/WORK/quasar_wrapper/mem/iccm_wr_data[63]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_data[64] i:/WORK/quasar_wrapper/mem/iccm_wr_data[64]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_data[65] i:/WORK/quasar_wrapper/mem/iccm_wr_data[65]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_data[66] i:/WORK/quasar_wrapper/mem/iccm_wr_data[66]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_data[67] i:/WORK/quasar_wrapper/mem/iccm_wr_data[67]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_data[68] i:/WORK/quasar_wrapper/mem/iccm_wr_data[68]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_data[69] i:/WORK/quasar_wrapper/mem/iccm_wr_data[69]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_data[6] i:/WORK/quasar_wrapper/mem/iccm_wr_data[6]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_data[70] i:/WORK/quasar_wrapper/mem/iccm_wr_data[70]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_data[71] i:/WORK/quasar_wrapper/mem/iccm_wr_data[71]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_data[72] i:/WORK/quasar_wrapper/mem/iccm_wr_data[72]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_data[73] i:/WORK/quasar_wrapper/mem/iccm_wr_data[73]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_data[74] i:/WORK/quasar_wrapper/mem/iccm_wr_data[74]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_data[75] i:/WORK/quasar_wrapper/mem/iccm_wr_data[75]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_data[76] i:/WORK/quasar_wrapper/mem/iccm_wr_data[76]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_data[77] i:/WORK/quasar_wrapper/mem/iccm_wr_data[77]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_data[7] i:/WORK/quasar_wrapper/mem/iccm_wr_data[7]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_data[8] i:/WORK/quasar_wrapper/mem/iccm_wr_data[8]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_data[9] i:/WORK/quasar_wrapper/mem/iccm_wr_data[9]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_size[0] i:/WORK/quasar_wrapper/mem/iccm_wr_size[0]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_size[1] i:/WORK/quasar_wrapper/mem/iccm_wr_size[1]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wr_size[2] i:/WORK/quasar_wrapper/mem/iccm_wr_size[2]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_wren i:/WORK/quasar_wrapper/mem/iccm_wren
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/icm_clk_override i:/WORK/quasar_wrapper/mem/icm_clk_override
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/rst_l i:/WORK/quasar_wrapper/mem/rst_l
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/scan_mode i:/WORK/quasar_wrapper/mem/scan_mode

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set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_data_hi[0] i:/WORK/quasar_wrapper/mem/dccm_rd_data_hi[0]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_data_hi[10] i:/WORK/quasar_wrapper/mem/dccm_rd_data_hi[10]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_data_hi[11] i:/WORK/quasar_wrapper/mem/dccm_rd_data_hi[11]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_data_hi[12] i:/WORK/quasar_wrapper/mem/dccm_rd_data_hi[12]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_data_hi[13] i:/WORK/quasar_wrapper/mem/dccm_rd_data_hi[13]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_data_hi[14] i:/WORK/quasar_wrapper/mem/dccm_rd_data_hi[14]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_data_hi[15] i:/WORK/quasar_wrapper/mem/dccm_rd_data_hi[15]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_data_hi[16] i:/WORK/quasar_wrapper/mem/dccm_rd_data_hi[16]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_data_hi[17] i:/WORK/quasar_wrapper/mem/dccm_rd_data_hi[17]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_data_hi[18] i:/WORK/quasar_wrapper/mem/dccm_rd_data_hi[18]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_data_hi[19] i:/WORK/quasar_wrapper/mem/dccm_rd_data_hi[19]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_data_hi[1] i:/WORK/quasar_wrapper/mem/dccm_rd_data_hi[1]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_data_hi[20] i:/WORK/quasar_wrapper/mem/dccm_rd_data_hi[20]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_data_hi[21] i:/WORK/quasar_wrapper/mem/dccm_rd_data_hi[21]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_data_hi[22] i:/WORK/quasar_wrapper/mem/dccm_rd_data_hi[22]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_data_hi[23] i:/WORK/quasar_wrapper/mem/dccm_rd_data_hi[23]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_data_hi[24] i:/WORK/quasar_wrapper/mem/dccm_rd_data_hi[24]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_data_hi[25] i:/WORK/quasar_wrapper/mem/dccm_rd_data_hi[25]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_data_hi[26] i:/WORK/quasar_wrapper/mem/dccm_rd_data_hi[26]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_data_hi[27] i:/WORK/quasar_wrapper/mem/dccm_rd_data_hi[27]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_data_hi[28] i:/WORK/quasar_wrapper/mem/dccm_rd_data_hi[28]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_data_hi[29] i:/WORK/quasar_wrapper/mem/dccm_rd_data_hi[29]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_data_hi[2] i:/WORK/quasar_wrapper/mem/dccm_rd_data_hi[2]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_data_hi[30] i:/WORK/quasar_wrapper/mem/dccm_rd_data_hi[30]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_data_hi[31] i:/WORK/quasar_wrapper/mem/dccm_rd_data_hi[31]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_data_hi[32] i:/WORK/quasar_wrapper/mem/dccm_rd_data_hi[32]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_data_hi[33] i:/WORK/quasar_wrapper/mem/dccm_rd_data_hi[33]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_data_hi[34] i:/WORK/quasar_wrapper/mem/dccm_rd_data_hi[34]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_data_hi[35] i:/WORK/quasar_wrapper/mem/dccm_rd_data_hi[35]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_data_hi[36] i:/WORK/quasar_wrapper/mem/dccm_rd_data_hi[36]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_data_hi[37] i:/WORK/quasar_wrapper/mem/dccm_rd_data_hi[37]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_data_hi[38] i:/WORK/quasar_wrapper/mem/dccm_rd_data_hi[38]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_data_hi[3] i:/WORK/quasar_wrapper/mem/dccm_rd_data_hi[3]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_data_hi[4] i:/WORK/quasar_wrapper/mem/dccm_rd_data_hi[4]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_data_hi[5] i:/WORK/quasar_wrapper/mem/dccm_rd_data_hi[5]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_data_hi[6] i:/WORK/quasar_wrapper/mem/dccm_rd_data_hi[6]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_data_hi[7] i:/WORK/quasar_wrapper/mem/dccm_rd_data_hi[7]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_data_hi[8] i:/WORK/quasar_wrapper/mem/dccm_rd_data_hi[8]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_data_hi[9] i:/WORK/quasar_wrapper/mem/dccm_rd_data_hi[9]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_data_lo[0] i:/WORK/quasar_wrapper/mem/dccm_rd_data_lo[0]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_data_lo[10] i:/WORK/quasar_wrapper/mem/dccm_rd_data_lo[10]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_data_lo[11] i:/WORK/quasar_wrapper/mem/dccm_rd_data_lo[11]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_data_lo[12] i:/WORK/quasar_wrapper/mem/dccm_rd_data_lo[12]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_data_lo[13] i:/WORK/quasar_wrapper/mem/dccm_rd_data_lo[13]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_data_lo[14] i:/WORK/quasar_wrapper/mem/dccm_rd_data_lo[14]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_data_lo[15] i:/WORK/quasar_wrapper/mem/dccm_rd_data_lo[15]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_data_lo[16] i:/WORK/quasar_wrapper/mem/dccm_rd_data_lo[16]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_data_lo[17] i:/WORK/quasar_wrapper/mem/dccm_rd_data_lo[17]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_data_lo[18] i:/WORK/quasar_wrapper/mem/dccm_rd_data_lo[18]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_data_lo[19] i:/WORK/quasar_wrapper/mem/dccm_rd_data_lo[19]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_data_lo[1] i:/WORK/quasar_wrapper/mem/dccm_rd_data_lo[1]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_data_lo[20] i:/WORK/quasar_wrapper/mem/dccm_rd_data_lo[20]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_data_lo[21] i:/WORK/quasar_wrapper/mem/dccm_rd_data_lo[21]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_data_lo[22] i:/WORK/quasar_wrapper/mem/dccm_rd_data_lo[22]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_data_lo[23] i:/WORK/quasar_wrapper/mem/dccm_rd_data_lo[23]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_data_lo[24] i:/WORK/quasar_wrapper/mem/dccm_rd_data_lo[24]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_data_lo[25] i:/WORK/quasar_wrapper/mem/dccm_rd_data_lo[25]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_data_lo[26] i:/WORK/quasar_wrapper/mem/dccm_rd_data_lo[26]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_data_lo[27] i:/WORK/quasar_wrapper/mem/dccm_rd_data_lo[27]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_data_lo[28] i:/WORK/quasar_wrapper/mem/dccm_rd_data_lo[28]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_data_lo[29] i:/WORK/quasar_wrapper/mem/dccm_rd_data_lo[29]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_data_lo[2] i:/WORK/quasar_wrapper/mem/dccm_rd_data_lo[2]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_data_lo[30] i:/WORK/quasar_wrapper/mem/dccm_rd_data_lo[30]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_data_lo[31] i:/WORK/quasar_wrapper/mem/dccm_rd_data_lo[31]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_data_lo[32] i:/WORK/quasar_wrapper/mem/dccm_rd_data_lo[32]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_data_lo[33] i:/WORK/quasar_wrapper/mem/dccm_rd_data_lo[33]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_data_lo[34] i:/WORK/quasar_wrapper/mem/dccm_rd_data_lo[34]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_data_lo[35] i:/WORK/quasar_wrapper/mem/dccm_rd_data_lo[35]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_data_lo[36] i:/WORK/quasar_wrapper/mem/dccm_rd_data_lo[36]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_data_lo[37] i:/WORK/quasar_wrapper/mem/dccm_rd_data_lo[37]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_data_lo[38] i:/WORK/quasar_wrapper/mem/dccm_rd_data_lo[38]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_data_lo[3] i:/WORK/quasar_wrapper/mem/dccm_rd_data_lo[3]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_data_lo[4] i:/WORK/quasar_wrapper/mem/dccm_rd_data_lo[4]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_data_lo[5] i:/WORK/quasar_wrapper/mem/dccm_rd_data_lo[5]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_data_lo[6] i:/WORK/quasar_wrapper/mem/dccm_rd_data_lo[6]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_data_lo[7] i:/WORK/quasar_wrapper/mem/dccm_rd_data_lo[7]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_data_lo[8] i:/WORK/quasar_wrapper/mem/dccm_rd_data_lo[8]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/dccm_rd_data_lo[9] i:/WORK/quasar_wrapper/mem/dccm_rd_data_lo[9]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_rd_data[0] i:/WORK/quasar_wrapper/mem/ic_debug_rd_data[0]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_rd_data[10] i:/WORK/quasar_wrapper/mem/ic_debug_rd_data[10]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_rd_data[11] i:/WORK/quasar_wrapper/mem/ic_debug_rd_data[11]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_rd_data[12] i:/WORK/quasar_wrapper/mem/ic_debug_rd_data[12]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_rd_data[13] i:/WORK/quasar_wrapper/mem/ic_debug_rd_data[13]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_rd_data[14] i:/WORK/quasar_wrapper/mem/ic_debug_rd_data[14]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_rd_data[15] i:/WORK/quasar_wrapper/mem/ic_debug_rd_data[15]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_rd_data[16] i:/WORK/quasar_wrapper/mem/ic_debug_rd_data[16]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_rd_data[17] i:/WORK/quasar_wrapper/mem/ic_debug_rd_data[17]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_rd_data[18] i:/WORK/quasar_wrapper/mem/ic_debug_rd_data[18]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_rd_data[19] i:/WORK/quasar_wrapper/mem/ic_debug_rd_data[19]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_rd_data[1] i:/WORK/quasar_wrapper/mem/ic_debug_rd_data[1]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_rd_data[20] i:/WORK/quasar_wrapper/mem/ic_debug_rd_data[20]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_rd_data[21] i:/WORK/quasar_wrapper/mem/ic_debug_rd_data[21]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_rd_data[22] i:/WORK/quasar_wrapper/mem/ic_debug_rd_data[22]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_rd_data[23] i:/WORK/quasar_wrapper/mem/ic_debug_rd_data[23]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_rd_data[24] i:/WORK/quasar_wrapper/mem/ic_debug_rd_data[24]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_rd_data[25] i:/WORK/quasar_wrapper/mem/ic_debug_rd_data[25]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_rd_data[26] i:/WORK/quasar_wrapper/mem/ic_debug_rd_data[26]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_rd_data[27] i:/WORK/quasar_wrapper/mem/ic_debug_rd_data[27]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_rd_data[28] i:/WORK/quasar_wrapper/mem/ic_debug_rd_data[28]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_rd_data[29] i:/WORK/quasar_wrapper/mem/ic_debug_rd_data[29]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_rd_data[2] i:/WORK/quasar_wrapper/mem/ic_debug_rd_data[2]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_rd_data[30] i:/WORK/quasar_wrapper/mem/ic_debug_rd_data[30]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_rd_data[31] i:/WORK/quasar_wrapper/mem/ic_debug_rd_data[31]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_rd_data[32] i:/WORK/quasar_wrapper/mem/ic_debug_rd_data[32]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_rd_data[33] i:/WORK/quasar_wrapper/mem/ic_debug_rd_data[33]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_rd_data[34] i:/WORK/quasar_wrapper/mem/ic_debug_rd_data[34]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_rd_data[35] i:/WORK/quasar_wrapper/mem/ic_debug_rd_data[35]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_rd_data[36] i:/WORK/quasar_wrapper/mem/ic_debug_rd_data[36]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_rd_data[37] i:/WORK/quasar_wrapper/mem/ic_debug_rd_data[37]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_rd_data[38] i:/WORK/quasar_wrapper/mem/ic_debug_rd_data[38]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_rd_data[39] i:/WORK/quasar_wrapper/mem/ic_debug_rd_data[39]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_rd_data[3] i:/WORK/quasar_wrapper/mem/ic_debug_rd_data[3]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_rd_data[40] i:/WORK/quasar_wrapper/mem/ic_debug_rd_data[40]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_rd_data[41] i:/WORK/quasar_wrapper/mem/ic_debug_rd_data[41]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_rd_data[42] i:/WORK/quasar_wrapper/mem/ic_debug_rd_data[42]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_rd_data[43] i:/WORK/quasar_wrapper/mem/ic_debug_rd_data[43]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_rd_data[44] i:/WORK/quasar_wrapper/mem/ic_debug_rd_data[44]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_rd_data[45] i:/WORK/quasar_wrapper/mem/ic_debug_rd_data[45]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_rd_data[46] i:/WORK/quasar_wrapper/mem/ic_debug_rd_data[46]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_rd_data[47] i:/WORK/quasar_wrapper/mem/ic_debug_rd_data[47]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_rd_data[48] i:/WORK/quasar_wrapper/mem/ic_debug_rd_data[48]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_rd_data[49] i:/WORK/quasar_wrapper/mem/ic_debug_rd_data[49]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_rd_data[4] i:/WORK/quasar_wrapper/mem/ic_debug_rd_data[4]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_rd_data[50] i:/WORK/quasar_wrapper/mem/ic_debug_rd_data[50]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_rd_data[51] i:/WORK/quasar_wrapper/mem/ic_debug_rd_data[51]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_rd_data[52] i:/WORK/quasar_wrapper/mem/ic_debug_rd_data[52]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_rd_data[53] i:/WORK/quasar_wrapper/mem/ic_debug_rd_data[53]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_rd_data[54] i:/WORK/quasar_wrapper/mem/ic_debug_rd_data[54]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_rd_data[55] i:/WORK/quasar_wrapper/mem/ic_debug_rd_data[55]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_rd_data[56] i:/WORK/quasar_wrapper/mem/ic_debug_rd_data[56]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_rd_data[57] i:/WORK/quasar_wrapper/mem/ic_debug_rd_data[57]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_rd_data[58] i:/WORK/quasar_wrapper/mem/ic_debug_rd_data[58]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_rd_data[59] i:/WORK/quasar_wrapper/mem/ic_debug_rd_data[59]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_rd_data[5] i:/WORK/quasar_wrapper/mem/ic_debug_rd_data[5]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_rd_data[60] i:/WORK/quasar_wrapper/mem/ic_debug_rd_data[60]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_rd_data[61] i:/WORK/quasar_wrapper/mem/ic_debug_rd_data[61]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_rd_data[62] i:/WORK/quasar_wrapper/mem/ic_debug_rd_data[62]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_rd_data[63] i:/WORK/quasar_wrapper/mem/ic_debug_rd_data[63]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_rd_data[64] i:/WORK/quasar_wrapper/mem/ic_debug_rd_data[64]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_rd_data[65] i:/WORK/quasar_wrapper/mem/ic_debug_rd_data[65]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_rd_data[66] i:/WORK/quasar_wrapper/mem/ic_debug_rd_data[66]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_rd_data[67] i:/WORK/quasar_wrapper/mem/ic_debug_rd_data[67]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_rd_data[68] i:/WORK/quasar_wrapper/mem/ic_debug_rd_data[68]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_rd_data[69] i:/WORK/quasar_wrapper/mem/ic_debug_rd_data[69]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_rd_data[6] i:/WORK/quasar_wrapper/mem/ic_debug_rd_data[6]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_rd_data[70] i:/WORK/quasar_wrapper/mem/ic_debug_rd_data[70]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_rd_data[7] i:/WORK/quasar_wrapper/mem/ic_debug_rd_data[7]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_rd_data[8] i:/WORK/quasar_wrapper/mem/ic_debug_rd_data[8]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_debug_rd_data[9] i:/WORK/quasar_wrapper/mem/ic_debug_rd_data[9]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_eccerr[0] i:/WORK/quasar_wrapper/mem/ic_eccerr[0]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_eccerr[1] i:/WORK/quasar_wrapper/mem/ic_eccerr[1]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_parerr[0] i:/WORK/quasar_wrapper/mem/ic_parerr[0]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_parerr[1] i:/WORK/quasar_wrapper/mem/ic_parerr[1]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rd_data[0] i:/WORK/quasar_wrapper/mem/ic_rd_data[0]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rd_data[10] i:/WORK/quasar_wrapper/mem/ic_rd_data[10]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rd_data[11] i:/WORK/quasar_wrapper/mem/ic_rd_data[11]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rd_data[12] i:/WORK/quasar_wrapper/mem/ic_rd_data[12]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rd_data[13] i:/WORK/quasar_wrapper/mem/ic_rd_data[13]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rd_data[14] i:/WORK/quasar_wrapper/mem/ic_rd_data[14]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rd_data[15] i:/WORK/quasar_wrapper/mem/ic_rd_data[15]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rd_data[16] i:/WORK/quasar_wrapper/mem/ic_rd_data[16]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rd_data[17] i:/WORK/quasar_wrapper/mem/ic_rd_data[17]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rd_data[18] i:/WORK/quasar_wrapper/mem/ic_rd_data[18]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rd_data[19] i:/WORK/quasar_wrapper/mem/ic_rd_data[19]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rd_data[1] i:/WORK/quasar_wrapper/mem/ic_rd_data[1]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rd_data[20] i:/WORK/quasar_wrapper/mem/ic_rd_data[20]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rd_data[21] i:/WORK/quasar_wrapper/mem/ic_rd_data[21]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rd_data[22] i:/WORK/quasar_wrapper/mem/ic_rd_data[22]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rd_data[23] i:/WORK/quasar_wrapper/mem/ic_rd_data[23]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rd_data[24] i:/WORK/quasar_wrapper/mem/ic_rd_data[24]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rd_data[25] i:/WORK/quasar_wrapper/mem/ic_rd_data[25]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rd_data[26] i:/WORK/quasar_wrapper/mem/ic_rd_data[26]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rd_data[27] i:/WORK/quasar_wrapper/mem/ic_rd_data[27]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rd_data[28] i:/WORK/quasar_wrapper/mem/ic_rd_data[28]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rd_data[29] i:/WORK/quasar_wrapper/mem/ic_rd_data[29]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rd_data[2] i:/WORK/quasar_wrapper/mem/ic_rd_data[2]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rd_data[30] i:/WORK/quasar_wrapper/mem/ic_rd_data[30]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rd_data[31] i:/WORK/quasar_wrapper/mem/ic_rd_data[31]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rd_data[32] i:/WORK/quasar_wrapper/mem/ic_rd_data[32]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rd_data[33] i:/WORK/quasar_wrapper/mem/ic_rd_data[33]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rd_data[34] i:/WORK/quasar_wrapper/mem/ic_rd_data[34]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rd_data[35] i:/WORK/quasar_wrapper/mem/ic_rd_data[35]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rd_data[36] i:/WORK/quasar_wrapper/mem/ic_rd_data[36]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rd_data[37] i:/WORK/quasar_wrapper/mem/ic_rd_data[37]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rd_data[38] i:/WORK/quasar_wrapper/mem/ic_rd_data[38]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rd_data[39] i:/WORK/quasar_wrapper/mem/ic_rd_data[39]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rd_data[3] i:/WORK/quasar_wrapper/mem/ic_rd_data[3]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rd_data[40] i:/WORK/quasar_wrapper/mem/ic_rd_data[40]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rd_data[41] i:/WORK/quasar_wrapper/mem/ic_rd_data[41]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rd_data[42] i:/WORK/quasar_wrapper/mem/ic_rd_data[42]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rd_data[43] i:/WORK/quasar_wrapper/mem/ic_rd_data[43]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rd_data[44] i:/WORK/quasar_wrapper/mem/ic_rd_data[44]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rd_data[45] i:/WORK/quasar_wrapper/mem/ic_rd_data[45]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rd_data[46] i:/WORK/quasar_wrapper/mem/ic_rd_data[46]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rd_data[47] i:/WORK/quasar_wrapper/mem/ic_rd_data[47]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rd_data[48] i:/WORK/quasar_wrapper/mem/ic_rd_data[48]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rd_data[49] i:/WORK/quasar_wrapper/mem/ic_rd_data[49]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rd_data[4] i:/WORK/quasar_wrapper/mem/ic_rd_data[4]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rd_data[50] i:/WORK/quasar_wrapper/mem/ic_rd_data[50]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rd_data[51] i:/WORK/quasar_wrapper/mem/ic_rd_data[51]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rd_data[52] i:/WORK/quasar_wrapper/mem/ic_rd_data[52]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rd_data[53] i:/WORK/quasar_wrapper/mem/ic_rd_data[53]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rd_data[54] i:/WORK/quasar_wrapper/mem/ic_rd_data[54]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rd_data[55] i:/WORK/quasar_wrapper/mem/ic_rd_data[55]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rd_data[56] i:/WORK/quasar_wrapper/mem/ic_rd_data[56]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rd_data[57] i:/WORK/quasar_wrapper/mem/ic_rd_data[57]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rd_data[58] i:/WORK/quasar_wrapper/mem/ic_rd_data[58]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rd_data[59] i:/WORK/quasar_wrapper/mem/ic_rd_data[59]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rd_data[5] i:/WORK/quasar_wrapper/mem/ic_rd_data[5]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rd_data[60] i:/WORK/quasar_wrapper/mem/ic_rd_data[60]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rd_data[61] i:/WORK/quasar_wrapper/mem/ic_rd_data[61]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rd_data[62] i:/WORK/quasar_wrapper/mem/ic_rd_data[62]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rd_data[63] i:/WORK/quasar_wrapper/mem/ic_rd_data[63]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rd_data[6] i:/WORK/quasar_wrapper/mem/ic_rd_data[6]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rd_data[7] i:/WORK/quasar_wrapper/mem/ic_rd_data[7]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rd_data[8] i:/WORK/quasar_wrapper/mem/ic_rd_data[8]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rd_data[9] i:/WORK/quasar_wrapper/mem/ic_rd_data[9]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rd_hit[0] i:/WORK/quasar_wrapper/mem/ic_rd_hit[0]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_rd_hit[1] i:/WORK/quasar_wrapper/mem/ic_rd_hit[1]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ic_tag_perr i:/WORK/quasar_wrapper/mem/ic_tag_perr
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data[0] i:/WORK/quasar_wrapper/mem/iccm_rd_data[0]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data[10] i:/WORK/quasar_wrapper/mem/iccm_rd_data[10]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data[11] i:/WORK/quasar_wrapper/mem/iccm_rd_data[11]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data[12] i:/WORK/quasar_wrapper/mem/iccm_rd_data[12]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data[13] i:/WORK/quasar_wrapper/mem/iccm_rd_data[13]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data[14] i:/WORK/quasar_wrapper/mem/iccm_rd_data[14]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data[15] i:/WORK/quasar_wrapper/mem/iccm_rd_data[15]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data[16] i:/WORK/quasar_wrapper/mem/iccm_rd_data[16]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data[17] i:/WORK/quasar_wrapper/mem/iccm_rd_data[17]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data[18] i:/WORK/quasar_wrapper/mem/iccm_rd_data[18]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data[19] i:/WORK/quasar_wrapper/mem/iccm_rd_data[19]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data[1] i:/WORK/quasar_wrapper/mem/iccm_rd_data[1]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data[20] i:/WORK/quasar_wrapper/mem/iccm_rd_data[20]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data[21] i:/WORK/quasar_wrapper/mem/iccm_rd_data[21]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data[22] i:/WORK/quasar_wrapper/mem/iccm_rd_data[22]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data[23] i:/WORK/quasar_wrapper/mem/iccm_rd_data[23]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data[24] i:/WORK/quasar_wrapper/mem/iccm_rd_data[24]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data[25] i:/WORK/quasar_wrapper/mem/iccm_rd_data[25]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data[26] i:/WORK/quasar_wrapper/mem/iccm_rd_data[26]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data[27] i:/WORK/quasar_wrapper/mem/iccm_rd_data[27]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data[28] i:/WORK/quasar_wrapper/mem/iccm_rd_data[28]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data[29] i:/WORK/quasar_wrapper/mem/iccm_rd_data[29]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data[2] i:/WORK/quasar_wrapper/mem/iccm_rd_data[2]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data[30] i:/WORK/quasar_wrapper/mem/iccm_rd_data[30]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data[31] i:/WORK/quasar_wrapper/mem/iccm_rd_data[31]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data[32] i:/WORK/quasar_wrapper/mem/iccm_rd_data[32]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data[33] i:/WORK/quasar_wrapper/mem/iccm_rd_data[33]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data[34] i:/WORK/quasar_wrapper/mem/iccm_rd_data[34]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data[35] i:/WORK/quasar_wrapper/mem/iccm_rd_data[35]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data[36] i:/WORK/quasar_wrapper/mem/iccm_rd_data[36]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data[37] i:/WORK/quasar_wrapper/mem/iccm_rd_data[37]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data[38] i:/WORK/quasar_wrapper/mem/iccm_rd_data[38]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data[39] i:/WORK/quasar_wrapper/mem/iccm_rd_data[39]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data[3] i:/WORK/quasar_wrapper/mem/iccm_rd_data[3]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data[40] i:/WORK/quasar_wrapper/mem/iccm_rd_data[40]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data[41] i:/WORK/quasar_wrapper/mem/iccm_rd_data[41]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data[42] i:/WORK/quasar_wrapper/mem/iccm_rd_data[42]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data[43] i:/WORK/quasar_wrapper/mem/iccm_rd_data[43]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data[44] i:/WORK/quasar_wrapper/mem/iccm_rd_data[44]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data[45] i:/WORK/quasar_wrapper/mem/iccm_rd_data[45]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data[46] i:/WORK/quasar_wrapper/mem/iccm_rd_data[46]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data[47] i:/WORK/quasar_wrapper/mem/iccm_rd_data[47]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data[48] i:/WORK/quasar_wrapper/mem/iccm_rd_data[48]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data[49] i:/WORK/quasar_wrapper/mem/iccm_rd_data[49]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data[4] i:/WORK/quasar_wrapper/mem/iccm_rd_data[4]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data[50] i:/WORK/quasar_wrapper/mem/iccm_rd_data[50]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data[51] i:/WORK/quasar_wrapper/mem/iccm_rd_data[51]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data[52] i:/WORK/quasar_wrapper/mem/iccm_rd_data[52]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data[53] i:/WORK/quasar_wrapper/mem/iccm_rd_data[53]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data[54] i:/WORK/quasar_wrapper/mem/iccm_rd_data[54]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data[55] i:/WORK/quasar_wrapper/mem/iccm_rd_data[55]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data[56] i:/WORK/quasar_wrapper/mem/iccm_rd_data[56]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data[57] i:/WORK/quasar_wrapper/mem/iccm_rd_data[57]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data[58] i:/WORK/quasar_wrapper/mem/iccm_rd_data[58]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data[59] i:/WORK/quasar_wrapper/mem/iccm_rd_data[59]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data[5] i:/WORK/quasar_wrapper/mem/iccm_rd_data[5]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data[60] i:/WORK/quasar_wrapper/mem/iccm_rd_data[60]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data[61] i:/WORK/quasar_wrapper/mem/iccm_rd_data[61]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data[62] i:/WORK/quasar_wrapper/mem/iccm_rd_data[62]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data[63] i:/WORK/quasar_wrapper/mem/iccm_rd_data[63]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data[6] i:/WORK/quasar_wrapper/mem/iccm_rd_data[6]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data[7] i:/WORK/quasar_wrapper/mem/iccm_rd_data[7]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data[8] i:/WORK/quasar_wrapper/mem/iccm_rd_data[8]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data[9] i:/WORK/quasar_wrapper/mem/iccm_rd_data[9]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data_ecc[0] i:/WORK/quasar_wrapper/mem/iccm_rd_data_ecc[0]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data_ecc[10] i:/WORK/quasar_wrapper/mem/iccm_rd_data_ecc[10]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data_ecc[11] i:/WORK/quasar_wrapper/mem/iccm_rd_data_ecc[11]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data_ecc[12] i:/WORK/quasar_wrapper/mem/iccm_rd_data_ecc[12]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data_ecc[13] i:/WORK/quasar_wrapper/mem/iccm_rd_data_ecc[13]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data_ecc[14] i:/WORK/quasar_wrapper/mem/iccm_rd_data_ecc[14]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data_ecc[15] i:/WORK/quasar_wrapper/mem/iccm_rd_data_ecc[15]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data_ecc[16] i:/WORK/quasar_wrapper/mem/iccm_rd_data_ecc[16]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data_ecc[17] i:/WORK/quasar_wrapper/mem/iccm_rd_data_ecc[17]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data_ecc[18] i:/WORK/quasar_wrapper/mem/iccm_rd_data_ecc[18]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data_ecc[19] i:/WORK/quasar_wrapper/mem/iccm_rd_data_ecc[19]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data_ecc[1] i:/WORK/quasar_wrapper/mem/iccm_rd_data_ecc[1]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data_ecc[20] i:/WORK/quasar_wrapper/mem/iccm_rd_data_ecc[20]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data_ecc[21] i:/WORK/quasar_wrapper/mem/iccm_rd_data_ecc[21]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data_ecc[22] i:/WORK/quasar_wrapper/mem/iccm_rd_data_ecc[22]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data_ecc[23] i:/WORK/quasar_wrapper/mem/iccm_rd_data_ecc[23]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data_ecc[24] i:/WORK/quasar_wrapper/mem/iccm_rd_data_ecc[24]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data_ecc[25] i:/WORK/quasar_wrapper/mem/iccm_rd_data_ecc[25]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data_ecc[26] i:/WORK/quasar_wrapper/mem/iccm_rd_data_ecc[26]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data_ecc[27] i:/WORK/quasar_wrapper/mem/iccm_rd_data_ecc[27]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data_ecc[28] i:/WORK/quasar_wrapper/mem/iccm_rd_data_ecc[28]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data_ecc[29] i:/WORK/quasar_wrapper/mem/iccm_rd_data_ecc[29]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data_ecc[2] i:/WORK/quasar_wrapper/mem/iccm_rd_data_ecc[2]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data_ecc[30] i:/WORK/quasar_wrapper/mem/iccm_rd_data_ecc[30]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data_ecc[31] i:/WORK/quasar_wrapper/mem/iccm_rd_data_ecc[31]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data_ecc[32] i:/WORK/quasar_wrapper/mem/iccm_rd_data_ecc[32]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data_ecc[33] i:/WORK/quasar_wrapper/mem/iccm_rd_data_ecc[33]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data_ecc[34] i:/WORK/quasar_wrapper/mem/iccm_rd_data_ecc[34]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data_ecc[35] i:/WORK/quasar_wrapper/mem/iccm_rd_data_ecc[35]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data_ecc[36] i:/WORK/quasar_wrapper/mem/iccm_rd_data_ecc[36]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data_ecc[37] i:/WORK/quasar_wrapper/mem/iccm_rd_data_ecc[37]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data_ecc[38] i:/WORK/quasar_wrapper/mem/iccm_rd_data_ecc[38]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data_ecc[39] i:/WORK/quasar_wrapper/mem/iccm_rd_data_ecc[39]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data_ecc[3] i:/WORK/quasar_wrapper/mem/iccm_rd_data_ecc[3]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data_ecc[40] i:/WORK/quasar_wrapper/mem/iccm_rd_data_ecc[40]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data_ecc[41] i:/WORK/quasar_wrapper/mem/iccm_rd_data_ecc[41]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data_ecc[42] i:/WORK/quasar_wrapper/mem/iccm_rd_data_ecc[42]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data_ecc[43] i:/WORK/quasar_wrapper/mem/iccm_rd_data_ecc[43]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data_ecc[44] i:/WORK/quasar_wrapper/mem/iccm_rd_data_ecc[44]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data_ecc[45] i:/WORK/quasar_wrapper/mem/iccm_rd_data_ecc[45]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data_ecc[46] i:/WORK/quasar_wrapper/mem/iccm_rd_data_ecc[46]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data_ecc[47] i:/WORK/quasar_wrapper/mem/iccm_rd_data_ecc[47]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data_ecc[48] i:/WORK/quasar_wrapper/mem/iccm_rd_data_ecc[48]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data_ecc[49] i:/WORK/quasar_wrapper/mem/iccm_rd_data_ecc[49]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data_ecc[4] i:/WORK/quasar_wrapper/mem/iccm_rd_data_ecc[4]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data_ecc[50] i:/WORK/quasar_wrapper/mem/iccm_rd_data_ecc[50]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data_ecc[51] i:/WORK/quasar_wrapper/mem/iccm_rd_data_ecc[51]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data_ecc[52] i:/WORK/quasar_wrapper/mem/iccm_rd_data_ecc[52]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data_ecc[53] i:/WORK/quasar_wrapper/mem/iccm_rd_data_ecc[53]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data_ecc[54] i:/WORK/quasar_wrapper/mem/iccm_rd_data_ecc[54]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data_ecc[55] i:/WORK/quasar_wrapper/mem/iccm_rd_data_ecc[55]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data_ecc[56] i:/WORK/quasar_wrapper/mem/iccm_rd_data_ecc[56]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data_ecc[57] i:/WORK/quasar_wrapper/mem/iccm_rd_data_ecc[57]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data_ecc[58] i:/WORK/quasar_wrapper/mem/iccm_rd_data_ecc[58]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data_ecc[59] i:/WORK/quasar_wrapper/mem/iccm_rd_data_ecc[59]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data_ecc[5] i:/WORK/quasar_wrapper/mem/iccm_rd_data_ecc[5]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data_ecc[60] i:/WORK/quasar_wrapper/mem/iccm_rd_data_ecc[60]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data_ecc[61] i:/WORK/quasar_wrapper/mem/iccm_rd_data_ecc[61]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data_ecc[62] i:/WORK/quasar_wrapper/mem/iccm_rd_data_ecc[62]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data_ecc[63] i:/WORK/quasar_wrapper/mem/iccm_rd_data_ecc[63]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data_ecc[64] i:/WORK/quasar_wrapper/mem/iccm_rd_data_ecc[64]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data_ecc[65] i:/WORK/quasar_wrapper/mem/iccm_rd_data_ecc[65]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data_ecc[66] i:/WORK/quasar_wrapper/mem/iccm_rd_data_ecc[66]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data_ecc[67] i:/WORK/quasar_wrapper/mem/iccm_rd_data_ecc[67]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data_ecc[68] i:/WORK/quasar_wrapper/mem/iccm_rd_data_ecc[68]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data_ecc[69] i:/WORK/quasar_wrapper/mem/iccm_rd_data_ecc[69]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data_ecc[6] i:/WORK/quasar_wrapper/mem/iccm_rd_data_ecc[6]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data_ecc[70] i:/WORK/quasar_wrapper/mem/iccm_rd_data_ecc[70]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data_ecc[71] i:/WORK/quasar_wrapper/mem/iccm_rd_data_ecc[71]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data_ecc[72] i:/WORK/quasar_wrapper/mem/iccm_rd_data_ecc[72]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data_ecc[73] i:/WORK/quasar_wrapper/mem/iccm_rd_data_ecc[73]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data_ecc[74] i:/WORK/quasar_wrapper/mem/iccm_rd_data_ecc[74]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data_ecc[75] i:/WORK/quasar_wrapper/mem/iccm_rd_data_ecc[75]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data_ecc[76] i:/WORK/quasar_wrapper/mem/iccm_rd_data_ecc[76]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data_ecc[77] i:/WORK/quasar_wrapper/mem/iccm_rd_data_ecc[77]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data_ecc[7] i:/WORK/quasar_wrapper/mem/iccm_rd_data_ecc[7]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data_ecc[8] i:/WORK/quasar_wrapper/mem/iccm_rd_data_ecc[8]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/iccm_rd_data_ecc[9] i:/WORK/quasar_wrapper/mem/iccm_rd_data_ecc[9]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ictag_debug_rd_data[0] i:/WORK/quasar_wrapper/mem/ic_tag_debug_rd_data[0]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ictag_debug_rd_data[10] i:/WORK/quasar_wrapper/mem/ic_tag_debug_rd_data[10]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ictag_debug_rd_data[11] i:/WORK/quasar_wrapper/mem/ic_tag_debug_rd_data[11]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ictag_debug_rd_data[12] i:/WORK/quasar_wrapper/mem/ic_tag_debug_rd_data[12]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ictag_debug_rd_data[13] i:/WORK/quasar_wrapper/mem/ic_tag_debug_rd_data[13]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ictag_debug_rd_data[14] i:/WORK/quasar_wrapper/mem/ic_tag_debug_rd_data[14]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ictag_debug_rd_data[15] i:/WORK/quasar_wrapper/mem/ic_tag_debug_rd_data[15]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ictag_debug_rd_data[16] i:/WORK/quasar_wrapper/mem/ic_tag_debug_rd_data[16]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ictag_debug_rd_data[17] i:/WORK/quasar_wrapper/mem/ic_tag_debug_rd_data[17]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ictag_debug_rd_data[18] i:/WORK/quasar_wrapper/mem/ic_tag_debug_rd_data[18]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ictag_debug_rd_data[19] i:/WORK/quasar_wrapper/mem/ic_tag_debug_rd_data[19]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ictag_debug_rd_data[1] i:/WORK/quasar_wrapper/mem/ic_tag_debug_rd_data[1]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ictag_debug_rd_data[20] i:/WORK/quasar_wrapper/mem/ic_tag_debug_rd_data[20]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ictag_debug_rd_data[21] i:/WORK/quasar_wrapper/mem/ic_tag_debug_rd_data[21]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ictag_debug_rd_data[22] i:/WORK/quasar_wrapper/mem/ic_tag_debug_rd_data[22]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ictag_debug_rd_data[23] i:/WORK/quasar_wrapper/mem/ic_tag_debug_rd_data[23]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ictag_debug_rd_data[24] i:/WORK/quasar_wrapper/mem/ic_tag_debug_rd_data[24]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ictag_debug_rd_data[25] i:/WORK/quasar_wrapper/mem/ic_tag_debug_rd_data[25]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ictag_debug_rd_data[2] i:/WORK/quasar_wrapper/mem/ic_tag_debug_rd_data[2]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ictag_debug_rd_data[3] i:/WORK/quasar_wrapper/mem/ic_tag_debug_rd_data[3]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ictag_debug_rd_data[4] i:/WORK/quasar_wrapper/mem/ic_tag_debug_rd_data[4]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ictag_debug_rd_data[5] i:/WORK/quasar_wrapper/mem/ic_tag_debug_rd_data[5]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ictag_debug_rd_data[6] i:/WORK/quasar_wrapper/mem/ic_tag_debug_rd_data[6]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ictag_debug_rd_data[7] i:/WORK/quasar_wrapper/mem/ic_tag_debug_rd_data[7]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ictag_debug_rd_data[8] i:/WORK/quasar_wrapper/mem/ic_tag_debug_rd_data[8]
set_user_match -type pin -noninverted r:/WORK/el2_swerv_wrapper/mem/ictag_debug_rd_data[9] i:/WORK/quasar_wrapper/mem/ic_tag_debug_rd_data[9]

72
verif/LEC/setup_files/Constant_1.3.fms Normal file
View File

@ -0,0 +1,72 @@
set_constant i:/WORK/quasar_wrapper/core/dec/decode/cam_raw_0_bits_tag_reg[2] 0
set_constant i:/WORK/quasar_wrapper/core/dec/decode/cam_raw_1_bits_tag_reg[2] 0
set_constant i:/WORK/quasar_wrapper/core/dec/decode/cam_raw_2_bits_tag_reg[2] 0
set_constant i:/WORK/quasar_wrapper/core/dec/decode/cam_raw_3_bits_tag_reg[2] 0
set_constant i:/WORK/quasar_wrapper/core/dec/io_dec_dbg_dbg_dctl_dbg_cmd_wrdata[10] 0
set_constant i:/WORK/quasar_wrapper/core/dec/io_dec_dbg_dbg_dctl_dbg_cmd_wrdata[11] 0
set_constant i:/WORK/quasar_wrapper/core/dec/io_dec_dbg_dbg_dctl_dbg_cmd_wrdata[12] 0
set_constant i:/WORK/quasar_wrapper/core/dec/io_dec_dbg_dbg_dctl_dbg_cmd_wrdata[13] 0
set_constant i:/WORK/quasar_wrapper/core/dec/io_dec_dbg_dbg_dctl_dbg_cmd_wrdata[14] 0
set_constant i:/WORK/quasar_wrapper/core/dec/io_dec_dbg_dbg_dctl_dbg_cmd_wrdata[15] 0
set_constant i:/WORK/quasar_wrapper/core/dec/io_dec_dbg_dbg_dctl_dbg_cmd_wrdata[16] 0
set_constant i:/WORK/quasar_wrapper/core/dec/io_dec_dbg_dbg_dctl_dbg_cmd_wrdata[17] 0
set_constant i:/WORK/quasar_wrapper/core/dec/io_dec_dbg_dbg_dctl_dbg_cmd_wrdata[18] 0
set_constant i:/WORK/quasar_wrapper/core/dec/io_dec_dbg_dbg_dctl_dbg_cmd_wrdata[19] 0
set_constant i:/WORK/quasar_wrapper/core/dec/io_dec_dbg_dbg_dctl_dbg_cmd_wrdata[20] 0
set_constant i:/WORK/quasar_wrapper/core/dec/io_dec_dbg_dbg_dctl_dbg_cmd_wrdata[21] 0
set_constant i:/WORK/quasar_wrapper/core/dec/io_dec_dbg_dbg_dctl_dbg_cmd_wrdata[22] 0
set_constant i:/WORK/quasar_wrapper/core/dec/io_dec_dbg_dbg_dctl_dbg_cmd_wrdata[23] 0
set_constant i:/WORK/quasar_wrapper/core/dec/io_dec_dbg_dbg_dctl_dbg_cmd_wrdata[24] 0
set_constant i:/WORK/quasar_wrapper/core/dec/io_dec_dbg_dbg_dctl_dbg_cmd_wrdata[25] 0
set_constant i:/WORK/quasar_wrapper/core/dec/io_dec_dbg_dbg_dctl_dbg_cmd_wrdata[26] 0
set_constant i:/WORK/quasar_wrapper/core/dec/io_dec_dbg_dbg_dctl_dbg_cmd_wrdata[27] 0
set_constant i:/WORK/quasar_wrapper/core/dec/io_dec_dbg_dbg_dctl_dbg_cmd_wrdata[28] 0
set_constant i:/WORK/quasar_wrapper/core/dec/io_dec_dbg_dbg_dctl_dbg_cmd_wrdata[29] 0
set_constant i:/WORK/quasar_wrapper/core/dec/io_dec_dbg_dbg_dctl_dbg_cmd_wrdata[2] 0
set_constant i:/WORK/quasar_wrapper/core/dec/io_dec_dbg_dbg_dctl_dbg_cmd_wrdata[30] 0
set_constant i:/WORK/quasar_wrapper/core/dec/io_dec_dbg_dbg_dctl_dbg_cmd_wrdata[31] 0
set_constant i:/WORK/quasar_wrapper/core/dec/io_dec_dbg_dbg_dctl_dbg_cmd_wrdata[3] 0
set_constant i:/WORK/quasar_wrapper/core/dec/io_dec_dbg_dbg_dctl_dbg_cmd_wrdata[4] 0
set_constant i:/WORK/quasar_wrapper/core/dec/io_dec_dbg_dbg_dctl_dbg_cmd_wrdata[5] 0
set_constant i:/WORK/quasar_wrapper/core/dec/io_dec_dbg_dbg_dctl_dbg_cmd_wrdata[6] 0
set_constant i:/WORK/quasar_wrapper/core/dec/io_dec_dbg_dbg_dctl_dbg_cmd_wrdata[7] 0
set_constant i:/WORK/quasar_wrapper/core/dec/io_dec_dbg_dbg_dctl_dbg_cmd_wrdata[8] 0
set_constant i:/WORK/quasar_wrapper/core/dec/io_dec_dbg_dbg_dctl_dbg_cmd_wrdata[9] 0
set_constant i:/WORK/quasar_wrapper/core/dec/tlu/int_timers/mitcnt0_inc1[8] 0
set_constant i:/WORK/quasar_wrapper/core/dec/tlu/int_timers/mitcnt1_inc1[8] 0
set_constant r:/WORK/el2_swerv_wrapper/swerv/dec/dec_fa_error_index[0] 0
set_constant r:/WORK/el2_swerv_wrapper/swerv/dec/dec_fa_error_index[1] 0
set_constant r:/WORK/el2_swerv_wrapper/swerv/dec/dec_fa_error_index[2] 0
set_constant r:/WORK/el2_swerv_wrapper/swerv/dec/dec_fa_error_index[3] 0
set_constant r:/WORK/el2_swerv_wrapper/swerv/dec/dec_fa_error_index[4] 0
set_constant r:/WORK/el2_swerv_wrapper/swerv/dec/dec_fa_error_index[5] 0
set_constant r:/WORK/el2_swerv_wrapper/swerv/dec/dec_fa_error_index[6] 0
set_constant r:/WORK/el2_swerv_wrapper/swerv/dec/dec_fa_error_index[7] 0
set_constant r:/WORK/el2_swerv_wrapper/swerv/dec/dec_fa_error_index[8] 0
set_constant r:/WORK/el2_swerv_wrapper/swerv/dec/ifu_i0_fa_index[0] 0
set_constant r:/WORK/el2_swerv_wrapper/swerv/dec/ifu_i0_fa_index[1] 0
set_constant r:/WORK/el2_swerv_wrapper/swerv/dec/ifu_i0_fa_index[2] 0
set_constant r:/WORK/el2_swerv_wrapper/swerv/dec/ifu_i0_fa_index[3] 0
set_constant r:/WORK/el2_swerv_wrapper/swerv/dec/ifu_i0_fa_index[4] 0
set_constant r:/WORK/el2_swerv_wrapper/swerv/dec/ifu_i0_fa_index[5] 0
set_constant r:/WORK/el2_swerv_wrapper/swerv/dec/ifu_i0_fa_index[6] 0
set_constant r:/WORK/el2_swerv_wrapper/swerv/dec/ifu_i0_fa_index[7] 0
set_constant r:/WORK/el2_swerv_wrapper/swerv/dec/ifu_i0_fa_index[8] 0
set_constant r:/WORK/el2_swerv_wrapper/swerv/dec/tlu/excinfo_wb_ff/genblock.dff/genblock.dffs/dout_reg[0] 0
set_constant r:/WORK/el2_swerv_wrapper/swerv/dec/tlu/freeff/genblock.dff/genblock.dffs/dout_reg[7] 0
set_constant r:/WORK/el2_swerv_wrapper/swerv/dec/tlu/genblk7.mstatus_ff/genblock.dff/genblock.dffs/dout_reg[13] 0
set_constant r:/WORK/el2_swerv_wrapper/swerv/dec/tlu/genblk7.mstatus_ff/genblock.dff/genblock.dffs/dout_reg[28] 0
set_constant r:/WORK/el2_swerv_wrapper/swerv/dec/tlu/int_timers/mitcnt0_inc_cout 0
set_constant r:/WORK/el2_swerv_wrapper/swerv/dec/tlu/int_timers/mitcnt1_inc_cout 0
set_constant r:/WORK/el2_swerv_wrapper/swerv/ifu/dec_fa_error_index[0] 0
set_constant r:/WORK/el2_swerv_wrapper/swerv/ifu/dec_fa_error_index[1] 0
set_constant r:/WORK/el2_swerv_wrapper/swerv/ifu/dec_fa_error_index[2] 0
set_constant r:/WORK/el2_swerv_wrapper/swerv/ifu/dec_fa_error_index[3] 0
set_constant r:/WORK/el2_swerv_wrapper/swerv/ifu/dec_fa_error_index[4] 0
set_constant r:/WORK/el2_swerv_wrapper/swerv/ifu/dec_fa_error_index[5] 0
set_constant r:/WORK/el2_swerv_wrapper/swerv/ifu/dec_fa_error_index[6] 0
set_constant r:/WORK/el2_swerv_wrapper/swerv/ifu/dec_fa_error_index[7] 0
set_constant r:/WORK/el2_swerv_wrapper/swerv/ifu/dec_fa_error_index[8] 0
set_constant r:/WORK/el2_swerv_wrapper/swerv/lsu/bus_intf/bus_buffer/obuf_tag0ff/genblock.dffs/genblock.dffs/dout_reg[2] 0
set_constant r:/WORK/el2_swerv_wrapper/swerv/lsu/bus_intf/bus_buffer/obuf_tag1ff/genblock.dffs/genblock.dffs/dout_reg[2] 0
# set_constant r:/WORK/el2_swerv_wrapper/swerv/ifu/mem_ctl/misc1_ff/genblock.dff/genblock.dffs/dout_reg[2] 0

13793
verif/LEC/setup_files/DFF.fms
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7233
verif/LEC/setup_files/DFF_1.3.fms Normal file
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43
verif/LEC/setup_files/Dont_verify_points_1.3.fms Normal file
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@ -0,0 +1,43 @@
set_dont_verify r:/WORK/el2_swerv_wrapper/swerv/dec/decode/misc1ff/genblock.dff/genblock.dffs/dout_reg[3]
set_dont_verify r:/WORK/el2_swerv_wrapper/swerv/dec/decode/misc1ff/genblock.dff/genblock.dffs/dout_reg[2]
set_dont_verify r:/WORK/el2_swerv_wrapper/swerv/dec/tlu/excinfo_wb_ff/genblock.dff/genblock.dffs/dout_reg[0]
set_dont_verify r:/WORK/el2_swerv_wrapper/swerv/dec/tlu/freeff/genblock.dff/genblock.dffs/dout_reg[7]
set_dont_verify r:/WORK/el2_swerv_wrapper/swerv/dec/tlu/genblk7.mstatus_ff/genblock.dff/genblock.dffs/dout_reg[13]
set_dont_verify r:/WORK/el2_swerv_wrapper/swerv/dec/tlu/genblk7.mstatus_ff/genblock.dff/genblock.dffs/dout_reg[28]
set_dont_verify r:/WORK/el2_swerv_wrapper/swerv/exu/i_mul/i_bitmanip_ff/genblock.genblock.dff/genblock.dffs/dout_reg[0]
set_dont_verify r:/WORK/el2_swerv_wrapper/swerv/exu/i_mul/i_bitmanip_ff/genblock.genblock.dff/genblock.dffs/dout_reg[10]
set_dont_verify r:/WORK/el2_swerv_wrapper/swerv/exu/i_mul/i_bitmanip_ff/genblock.genblock.dff/genblock.dffs/dout_reg[11]
set_dont_verify r:/WORK/el2_swerv_wrapper/swerv/exu/i_mul/i_bitmanip_ff/genblock.genblock.dff/genblock.dffs/dout_reg[12]
set_dont_verify r:/WORK/el2_swerv_wrapper/swerv/exu/i_mul/i_bitmanip_ff/genblock.genblock.dff/genblock.dffs/dout_reg[13]
set_dont_verify r:/WORK/el2_swerv_wrapper/swerv/exu/i_mul/i_bitmanip_ff/genblock.genblock.dff/genblock.dffs/dout_reg[14]
set_dont_verify r:/WORK/el2_swerv_wrapper/swerv/exu/i_mul/i_bitmanip_ff/genblock.genblock.dff/genblock.dffs/dout_reg[15]
set_dont_verify r:/WORK/el2_swerv_wrapper/swerv/exu/i_mul/i_bitmanip_ff/genblock.genblock.dff/genblock.dffs/dout_reg[16]
set_dont_verify r:/WORK/el2_swerv_wrapper/swerv/exu/i_mul/i_bitmanip_ff/genblock.genblock.dff/genblock.dffs/dout_reg[17]
set_dont_verify r:/WORK/el2_swerv_wrapper/swerv/exu/i_mul/i_bitmanip_ff/genblock.genblock.dff/genblock.dffs/dout_reg[18]
set_dont_verify r:/WORK/el2_swerv_wrapper/swerv/exu/i_mul/i_bitmanip_ff/genblock.genblock.dff/genblock.dffs/dout_reg[19]
set_dont_verify r:/WORK/el2_swerv_wrapper/swerv/exu/i_mul/i_bitmanip_ff/genblock.genblock.dff/genblock.dffs/dout_reg[1]
set_dont_verify r:/WORK/el2_swerv_wrapper/swerv/exu/i_mul/i_bitmanip_ff/genblock.genblock.dff/genblock.dffs/dout_reg[20]
set_dont_verify r:/WORK/el2_swerv_wrapper/swerv/exu/i_mul/i_bitmanip_ff/genblock.genblock.dff/genblock.dffs/dout_reg[21]
set_dont_verify r:/WORK/el2_swerv_wrapper/swerv/exu/i_mul/i_bitmanip_ff/genblock.genblock.dff/genblock.dffs/dout_reg[22]
set_dont_verify r:/WORK/el2_swerv_wrapper/swerv/exu/i_mul/i_bitmanip_ff/genblock.genblock.dff/genblock.dffs/dout_reg[23]
set_dont_verify r:/WORK/el2_swerv_wrapper/swerv/exu/i_mul/i_bitmanip_ff/genblock.genblock.dff/genblock.dffs/dout_reg[24]
set_dont_verify r:/WORK/el2_swerv_wrapper/swerv/exu/i_mul/i_bitmanip_ff/genblock.genblock.dff/genblock.dffs/dout_reg[25]
set_dont_verify r:/WORK/el2_swerv_wrapper/swerv/exu/i_mul/i_bitmanip_ff/genblock.genblock.dff/genblock.dffs/dout_reg[26]
set_dont_verify r:/WORK/el2_swerv_wrapper/swerv/exu/i_mul/i_bitmanip_ff/genblock.genblock.dff/genblock.dffs/dout_reg[27]
set_dont_verify r:/WORK/el2_swerv_wrapper/swerv/exu/i_mul/i_bitmanip_ff/genblock.genblock.dff/genblock.dffs/dout_reg[28]
set_dont_verify r:/WORK/el2_swerv_wrapper/swerv/exu/i_mul/i_bitmanip_ff/genblock.genblock.dff/genblock.dffs/dout_reg[29]
set_dont_verify r:/WORK/el2_swerv_wrapper/swerv/exu/i_mul/i_bitmanip_ff/genblock.genblock.dff/genblock.dffs/dout_reg[2]
set_dont_verify r:/WORK/el2_swerv_wrapper/swerv/exu/i_mul/i_bitmanip_ff/genblock.genblock.dff/genblock.dffs/dout_reg[30]
set_dont_verify r:/WORK/el2_swerv_wrapper/swerv/exu/i_mul/i_bitmanip_ff/genblock.genblock.dff/genblock.dffs/dout_reg[31]
set_dont_verify r:/WORK/el2_swerv_wrapper/swerv/exu/i_mul/i_bitmanip_ff/genblock.genblock.dff/genblock.dffs/dout_reg[32]
set_dont_verify r:/WORK/el2_swerv_wrapper/swerv/exu/i_mul/i_bitmanip_ff/genblock.genblock.dff/genblock.dffs/dout_reg[3]
set_dont_verify r:/WORK/el2_swerv_wrapper/swerv/exu/i_mul/i_bitmanip_ff/genblock.genblock.dff/genblock.dffs/dout_reg[4]
set_dont_verify r:/WORK/el2_swerv_wrapper/swerv/exu/i_mul/i_bitmanip_ff/genblock.genblock.dff/genblock.dffs/dout_reg[5]
set_dont_verify r:/WORK/el2_swerv_wrapper/swerv/exu/i_mul/i_bitmanip_ff/genblock.genblock.dff/genblock.dffs/dout_reg[6]
set_dont_verify r:/WORK/el2_swerv_wrapper/swerv/exu/i_mul/i_bitmanip_ff/genblock.genblock.dff/genblock.dffs/dout_reg[7]
set_dont_verify r:/WORK/el2_swerv_wrapper/swerv/exu/i_mul/i_bitmanip_ff/genblock.genblock.dff/genblock.dffs/dout_reg[8]
set_dont_verify r:/WORK/el2_swerv_wrapper/swerv/exu/i_mul/i_bitmanip_ff/genblock.genblock.dff/genblock.dffs/dout_reg[9]
set_dont_verify r:/WORK/el2_swerv_wrapper/swerv/lsu/bus_intf/bus_buffer/obuf_tag0ff/genblock.dffs/genblock.dffs/dout_reg[2]
set_dont_verify r:/WORK/el2_swerv_wrapper/swerv/lsu/bus_intf/bus_buffer/obuf_tag1ff/genblock.dffs/genblock.dffs/dout_reg[2]
set_dont_verify r:/WORK/el2_swerv_wrapper/swerv/lsu/lsu_lsc_ctl/lsu_pkt_mff/dout_reg[0]
set_dont_verify i:/WORK/quasar_wrapper/core/lsu/lsu_lsc_ctl/_T_139_bits_store_data_bypass_m_reg

5434
verif/LEC/setup_files/Functional_match_1.3.fms Normal file
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712
verif/LEC/setup_files/Input_ports_1.3.fms Normal file
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set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/clk i:/WORK/quasar_wrapper/clock
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/core_id[10] i:/WORK/quasar_wrapper/io_core_id[6]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/core_id[11] i:/WORK/quasar_wrapper/io_core_id[7]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/core_id[12] i:/WORK/quasar_wrapper/io_core_id[8]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/core_id[13] i:/WORK/quasar_wrapper/io_core_id[9]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/core_id[14] i:/WORK/quasar_wrapper/io_core_id[10]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/core_id[15] i:/WORK/quasar_wrapper/io_core_id[11]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/core_id[16] i:/WORK/quasar_wrapper/io_core_id[12]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/core_id[17] i:/WORK/quasar_wrapper/io_core_id[13]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/core_id[18] i:/WORK/quasar_wrapper/io_core_id[14]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/core_id[19] i:/WORK/quasar_wrapper/io_core_id[15]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/core_id[20] i:/WORK/quasar_wrapper/io_core_id[16]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/core_id[21] i:/WORK/quasar_wrapper/io_core_id[17]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/core_id[22] i:/WORK/quasar_wrapper/io_core_id[18]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/core_id[23] i:/WORK/quasar_wrapper/io_core_id[19]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/core_id[24] i:/WORK/quasar_wrapper/io_core_id[20]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/core_id[25] i:/WORK/quasar_wrapper/io_core_id[21]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/core_id[26] i:/WORK/quasar_wrapper/io_core_id[22]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/core_id[27] i:/WORK/quasar_wrapper/io_core_id[23]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/core_id[28] i:/WORK/quasar_wrapper/io_core_id[24]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/core_id[29] i:/WORK/quasar_wrapper/io_core_id[25]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/core_id[30] i:/WORK/quasar_wrapper/io_core_id[26]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/core_id[31] i:/WORK/quasar_wrapper/io_core_id[27]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/core_id[4] i:/WORK/quasar_wrapper/io_core_id[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/core_id[5] i:/WORK/quasar_wrapper/io_core_id[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/core_id[6] i:/WORK/quasar_wrapper/io_core_id[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/core_id[7] i:/WORK/quasar_wrapper/io_core_id[3]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/core_id[8] i:/WORK/quasar_wrapper/io_core_id[4]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/core_id[9] i:/WORK/quasar_wrapper/io_core_id[5]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dbg_bus_clk_en i:/WORK/quasar_wrapper/io_dbg_bus_clk_en
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dbg_rst_l i:/WORK/quasar_wrapper/io_dbg_rst_l
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dccm_ext_in_pkt[0]\[BC1] i:/WORK/quasar_wrapper/io_dccm_ext_in_pkt_BC1_0
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dccm_ext_in_pkt[0]\[BC2] i:/WORK/quasar_wrapper/io_dccm_ext_in_pkt_BC2_0
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dccm_ext_in_pkt[0]\[DS] i:/WORK/quasar_wrapper/io_dccm_ext_in_pkt_DS_0
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dccm_ext_in_pkt[0]\[LS] i:/WORK/quasar_wrapper/io_dccm_ext_in_pkt_LS_0
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dccm_ext_in_pkt[0]\[RME] i:/WORK/quasar_wrapper/io_dccm_ext_in_pkt_RME_0
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dccm_ext_in_pkt[0]\[RM][0] i:/WORK/quasar_wrapper/io_dccm_ext_in_pkt_RM_0[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dccm_ext_in_pkt[0]\[RM][1] i:/WORK/quasar_wrapper/io_dccm_ext_in_pkt_RM_0[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dccm_ext_in_pkt[0]\[RM][2] i:/WORK/quasar_wrapper/io_dccm_ext_in_pkt_RM_0[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dccm_ext_in_pkt[0]\[RM][3] i:/WORK/quasar_wrapper/io_dccm_ext_in_pkt_RM_0[3]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dccm_ext_in_pkt[0]\[SD] i:/WORK/quasar_wrapper/io_dccm_ext_in_pkt_SD_0
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dccm_ext_in_pkt[0]\[TEST1] i:/WORK/quasar_wrapper/io_dccm_ext_in_pkt_TEST1_0
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dccm_ext_in_pkt[0]\[TEST_RNM] i:/WORK/quasar_wrapper/io_dccm_ext_in_pkt_TEST_RNM_0
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dccm_ext_in_pkt[1]\[BC1] i:/WORK/quasar_wrapper/io_dccm_ext_in_pkt_BC1_1
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dccm_ext_in_pkt[1]\[BC2] i:/WORK/quasar_wrapper/io_dccm_ext_in_pkt_BC2_1
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dccm_ext_in_pkt[1]\[DS] i:/WORK/quasar_wrapper/io_dccm_ext_in_pkt_DS_1
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dccm_ext_in_pkt[1]\[LS] i:/WORK/quasar_wrapper/io_dccm_ext_in_pkt_LS_1
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dccm_ext_in_pkt[1]\[RME] i:/WORK/quasar_wrapper/io_dccm_ext_in_pkt_RME_1
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dccm_ext_in_pkt[1]\[RM][0] i:/WORK/quasar_wrapper/io_dccm_ext_in_pkt_RM_1[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dccm_ext_in_pkt[1]\[RM][1] i:/WORK/quasar_wrapper/io_dccm_ext_in_pkt_RM_1[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dccm_ext_in_pkt[1]\[RM][2] i:/WORK/quasar_wrapper/io_dccm_ext_in_pkt_RM_1[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dccm_ext_in_pkt[1]\[RM][3] i:/WORK/quasar_wrapper/io_dccm_ext_in_pkt_RM_1[3]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dccm_ext_in_pkt[1]\[SD] i:/WORK/quasar_wrapper/io_dccm_ext_in_pkt_SD_1
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dccm_ext_in_pkt[1]\[TEST1] i:/WORK/quasar_wrapper/io_dccm_ext_in_pkt_TEST1_1
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dccm_ext_in_pkt[1]\[TEST_RNM] i:/WORK/quasar_wrapper/io_dccm_ext_in_pkt_TEST_RNM_1
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dccm_ext_in_pkt[2]\[BC1] i:/WORK/quasar_wrapper/io_dccm_ext_in_pkt_BC1_2
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dccm_ext_in_pkt[2]\[BC2] i:/WORK/quasar_wrapper/io_dccm_ext_in_pkt_BC2_2
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dccm_ext_in_pkt[2]\[DS] i:/WORK/quasar_wrapper/io_dccm_ext_in_pkt_DS_2
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dccm_ext_in_pkt[2]\[LS] i:/WORK/quasar_wrapper/io_dccm_ext_in_pkt_LS_2
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dccm_ext_in_pkt[2]\[RME] i:/WORK/quasar_wrapper/io_dccm_ext_in_pkt_RME_2
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dccm_ext_in_pkt[2]\[RM][0] i:/WORK/quasar_wrapper/io_dccm_ext_in_pkt_RM_2[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dccm_ext_in_pkt[2]\[RM][1] i:/WORK/quasar_wrapper/io_dccm_ext_in_pkt_RM_2[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dccm_ext_in_pkt[2]\[RM][2] i:/WORK/quasar_wrapper/io_dccm_ext_in_pkt_RM_2[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dccm_ext_in_pkt[2]\[RM][3] i:/WORK/quasar_wrapper/io_dccm_ext_in_pkt_RM_2[3]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dccm_ext_in_pkt[2]\[SD] i:/WORK/quasar_wrapper/io_dccm_ext_in_pkt_SD_2
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dccm_ext_in_pkt[2]\[TEST1] i:/WORK/quasar_wrapper/io_dccm_ext_in_pkt_TEST1_2
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dccm_ext_in_pkt[2]\[TEST_RNM] i:/WORK/quasar_wrapper/io_dccm_ext_in_pkt_TEST_RNM_2
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dccm_ext_in_pkt[3]\[BC1] i:/WORK/quasar_wrapper/io_dccm_ext_in_pkt_BC1_3
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dccm_ext_in_pkt[3]\[BC2] i:/WORK/quasar_wrapper/io_dccm_ext_in_pkt_BC2_3
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dccm_ext_in_pkt[3]\[DS] i:/WORK/quasar_wrapper/io_dccm_ext_in_pkt_DS_3
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dccm_ext_in_pkt[3]\[LS] i:/WORK/quasar_wrapper/io_dccm_ext_in_pkt_LS_3
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dccm_ext_in_pkt[3]\[RME] i:/WORK/quasar_wrapper/io_dccm_ext_in_pkt_RME_3
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dccm_ext_in_pkt[3]\[RM][0] i:/WORK/quasar_wrapper/io_dccm_ext_in_pkt_RM_3[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dccm_ext_in_pkt[3]\[RM][1] i:/WORK/quasar_wrapper/io_dccm_ext_in_pkt_RM_3[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dccm_ext_in_pkt[3]\[RM][2] i:/WORK/quasar_wrapper/io_dccm_ext_in_pkt_RM_3[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dccm_ext_in_pkt[3]\[RM][3] i:/WORK/quasar_wrapper/io_dccm_ext_in_pkt_RM_3[3]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dccm_ext_in_pkt[3]\[SD] i:/WORK/quasar_wrapper/io_dccm_ext_in_pkt_SD_3
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dccm_ext_in_pkt[3]\[TEST1] i:/WORK/quasar_wrapper/io_dccm_ext_in_pkt_TEST1_3
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dccm_ext_in_pkt[3]\[TEST_RNM] i:/WORK/quasar_wrapper/io_dccm_ext_in_pkt_TEST_RNM_3
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_araddr[0] i:/WORK/quasar_wrapper/io_dma_brg_ar_bits_addr[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_araddr[10] i:/WORK/quasar_wrapper/io_dma_brg_ar_bits_addr[10]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_araddr[11] i:/WORK/quasar_wrapper/io_dma_brg_ar_bits_addr[11]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_araddr[12] i:/WORK/quasar_wrapper/io_dma_brg_ar_bits_addr[12]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_araddr[13] i:/WORK/quasar_wrapper/io_dma_brg_ar_bits_addr[13]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_araddr[14] i:/WORK/quasar_wrapper/io_dma_brg_ar_bits_addr[14]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_araddr[15] i:/WORK/quasar_wrapper/io_dma_brg_ar_bits_addr[15]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_araddr[16] i:/WORK/quasar_wrapper/io_dma_brg_ar_bits_addr[16]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_araddr[17] i:/WORK/quasar_wrapper/io_dma_brg_ar_bits_addr[17]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_araddr[18] i:/WORK/quasar_wrapper/io_dma_brg_ar_bits_addr[18]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_araddr[19] i:/WORK/quasar_wrapper/io_dma_brg_ar_bits_addr[19]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_araddr[1] i:/WORK/quasar_wrapper/io_dma_brg_ar_bits_addr[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_araddr[20] i:/WORK/quasar_wrapper/io_dma_brg_ar_bits_addr[20]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_araddr[21] i:/WORK/quasar_wrapper/io_dma_brg_ar_bits_addr[21]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_araddr[22] i:/WORK/quasar_wrapper/io_dma_brg_ar_bits_addr[22]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_araddr[23] i:/WORK/quasar_wrapper/io_dma_brg_ar_bits_addr[23]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_araddr[24] i:/WORK/quasar_wrapper/io_dma_brg_ar_bits_addr[24]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_araddr[25] i:/WORK/quasar_wrapper/io_dma_brg_ar_bits_addr[25]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_araddr[26] i:/WORK/quasar_wrapper/io_dma_brg_ar_bits_addr[26]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_araddr[27] i:/WORK/quasar_wrapper/io_dma_brg_ar_bits_addr[27]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_araddr[28] i:/WORK/quasar_wrapper/io_dma_brg_ar_bits_addr[28]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_araddr[29] i:/WORK/quasar_wrapper/io_dma_brg_ar_bits_addr[29]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_araddr[2] i:/WORK/quasar_wrapper/io_dma_brg_ar_bits_addr[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_araddr[30] i:/WORK/quasar_wrapper/io_dma_brg_ar_bits_addr[30]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_araddr[31] i:/WORK/quasar_wrapper/io_dma_brg_ar_bits_addr[31]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_araddr[3] i:/WORK/quasar_wrapper/io_dma_brg_ar_bits_addr[3]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_araddr[4] i:/WORK/quasar_wrapper/io_dma_brg_ar_bits_addr[4]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_araddr[5] i:/WORK/quasar_wrapper/io_dma_brg_ar_bits_addr[5]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_araddr[6] i:/WORK/quasar_wrapper/io_dma_brg_ar_bits_addr[6]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_araddr[7] i:/WORK/quasar_wrapper/io_dma_brg_ar_bits_addr[7]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_araddr[8] i:/WORK/quasar_wrapper/io_dma_brg_ar_bits_addr[8]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_araddr[9] i:/WORK/quasar_wrapper/io_dma_brg_ar_bits_addr[9]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_arid[0] i:/WORK/quasar_wrapper/io_dma_brg_ar_bits_id
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_arsize[0] i:/WORK/quasar_wrapper/io_dma_brg_ar_bits_size[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_arsize[1] i:/WORK/quasar_wrapper/io_dma_brg_ar_bits_size[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_arsize[2] i:/WORK/quasar_wrapper/io_dma_brg_ar_bits_size[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_arvalid i:/WORK/quasar_wrapper/io_dma_brg_ar_valid
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_awaddr[0] i:/WORK/quasar_wrapper/io_dma_brg_aw_bits_addr[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_awaddr[10] i:/WORK/quasar_wrapper/io_dma_brg_aw_bits_addr[10]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_awaddr[11] i:/WORK/quasar_wrapper/io_dma_brg_aw_bits_addr[11]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_awaddr[12] i:/WORK/quasar_wrapper/io_dma_brg_aw_bits_addr[12]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_awaddr[13] i:/WORK/quasar_wrapper/io_dma_brg_aw_bits_addr[13]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_awaddr[14] i:/WORK/quasar_wrapper/io_dma_brg_aw_bits_addr[14]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_awaddr[15] i:/WORK/quasar_wrapper/io_dma_brg_aw_bits_addr[15]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_awaddr[16] i:/WORK/quasar_wrapper/io_dma_brg_aw_bits_addr[16]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_awaddr[17] i:/WORK/quasar_wrapper/io_dma_brg_aw_bits_addr[17]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_awaddr[18] i:/WORK/quasar_wrapper/io_dma_brg_aw_bits_addr[18]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_awaddr[19] i:/WORK/quasar_wrapper/io_dma_brg_aw_bits_addr[19]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_awaddr[1] i:/WORK/quasar_wrapper/io_dma_brg_aw_bits_addr[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_awaddr[20] i:/WORK/quasar_wrapper/io_dma_brg_aw_bits_addr[20]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_awaddr[21] i:/WORK/quasar_wrapper/io_dma_brg_aw_bits_addr[21]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_awaddr[22] i:/WORK/quasar_wrapper/io_dma_brg_aw_bits_addr[22]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_awaddr[23] i:/WORK/quasar_wrapper/io_dma_brg_aw_bits_addr[23]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_awaddr[24] i:/WORK/quasar_wrapper/io_dma_brg_aw_bits_addr[24]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_awaddr[25] i:/WORK/quasar_wrapper/io_dma_brg_aw_bits_addr[25]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_awaddr[26] i:/WORK/quasar_wrapper/io_dma_brg_aw_bits_addr[26]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_awaddr[27] i:/WORK/quasar_wrapper/io_dma_brg_aw_bits_addr[27]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_awaddr[28] i:/WORK/quasar_wrapper/io_dma_brg_aw_bits_addr[28]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_awaddr[29] i:/WORK/quasar_wrapper/io_dma_brg_aw_bits_addr[29]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_awaddr[2] i:/WORK/quasar_wrapper/io_dma_brg_aw_bits_addr[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_awaddr[30] i:/WORK/quasar_wrapper/io_dma_brg_aw_bits_addr[30]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_awaddr[31] i:/WORK/quasar_wrapper/io_dma_brg_aw_bits_addr[31]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_awaddr[3] i:/WORK/quasar_wrapper/io_dma_brg_aw_bits_addr[3]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_awaddr[4] i:/WORK/quasar_wrapper/io_dma_brg_aw_bits_addr[4]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_awaddr[5] i:/WORK/quasar_wrapper/io_dma_brg_aw_bits_addr[5]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_awaddr[6] i:/WORK/quasar_wrapper/io_dma_brg_aw_bits_addr[6]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_awaddr[7] i:/WORK/quasar_wrapper/io_dma_brg_aw_bits_addr[7]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_awaddr[8] i:/WORK/quasar_wrapper/io_dma_brg_aw_bits_addr[8]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_awaddr[9] i:/WORK/quasar_wrapper/io_dma_brg_aw_bits_addr[9]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_awid[0] i:/WORK/quasar_wrapper/io_dma_brg_aw_bits_id
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_awsize[0] i:/WORK/quasar_wrapper/io_dma_brg_aw_bits_size[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_awsize[1] i:/WORK/quasar_wrapper/io_dma_brg_aw_bits_size[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_awsize[2] i:/WORK/quasar_wrapper/io_dma_brg_aw_bits_size[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_awvalid i:/WORK/quasar_wrapper/io_dma_brg_aw_valid
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_bready i:/WORK/quasar_wrapper/io_dma_brg_b_ready
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_rready i:/WORK/quasar_wrapper/io_dma_brg_r_ready
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_wdata[0] i:/WORK/quasar_wrapper/io_dma_brg_w_bits_data[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_wdata[10] i:/WORK/quasar_wrapper/io_dma_brg_w_bits_data[10]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_wdata[11] i:/WORK/quasar_wrapper/io_dma_brg_w_bits_data[11]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_wdata[12] i:/WORK/quasar_wrapper/io_dma_brg_w_bits_data[12]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_wdata[13] i:/WORK/quasar_wrapper/io_dma_brg_w_bits_data[13]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_wdata[14] i:/WORK/quasar_wrapper/io_dma_brg_w_bits_data[14]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_wdata[15] i:/WORK/quasar_wrapper/io_dma_brg_w_bits_data[15]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_wdata[16] i:/WORK/quasar_wrapper/io_dma_brg_w_bits_data[16]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_wdata[17] i:/WORK/quasar_wrapper/io_dma_brg_w_bits_data[17]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_wdata[18] i:/WORK/quasar_wrapper/io_dma_brg_w_bits_data[18]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_wdata[19] i:/WORK/quasar_wrapper/io_dma_brg_w_bits_data[19]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_wdata[1] i:/WORK/quasar_wrapper/io_dma_brg_w_bits_data[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_wdata[20] i:/WORK/quasar_wrapper/io_dma_brg_w_bits_data[20]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_wdata[21] i:/WORK/quasar_wrapper/io_dma_brg_w_bits_data[21]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_wdata[22] i:/WORK/quasar_wrapper/io_dma_brg_w_bits_data[22]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_wdata[23] i:/WORK/quasar_wrapper/io_dma_brg_w_bits_data[23]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_wdata[24] i:/WORK/quasar_wrapper/io_dma_brg_w_bits_data[24]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_wdata[25] i:/WORK/quasar_wrapper/io_dma_brg_w_bits_data[25]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_wdata[26] i:/WORK/quasar_wrapper/io_dma_brg_w_bits_data[26]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_wdata[27] i:/WORK/quasar_wrapper/io_dma_brg_w_bits_data[27]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_wdata[28] i:/WORK/quasar_wrapper/io_dma_brg_w_bits_data[28]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_wdata[29] i:/WORK/quasar_wrapper/io_dma_brg_w_bits_data[29]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_wdata[2] i:/WORK/quasar_wrapper/io_dma_brg_w_bits_data[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_wdata[30] i:/WORK/quasar_wrapper/io_dma_brg_w_bits_data[30]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_wdata[31] i:/WORK/quasar_wrapper/io_dma_brg_w_bits_data[31]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_wdata[32] i:/WORK/quasar_wrapper/io_dma_brg_w_bits_data[32]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_wdata[33] i:/WORK/quasar_wrapper/io_dma_brg_w_bits_data[33]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_wdata[34] i:/WORK/quasar_wrapper/io_dma_brg_w_bits_data[34]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_wdata[35] i:/WORK/quasar_wrapper/io_dma_brg_w_bits_data[35]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_wdata[36] i:/WORK/quasar_wrapper/io_dma_brg_w_bits_data[36]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_wdata[37] i:/WORK/quasar_wrapper/io_dma_brg_w_bits_data[37]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_wdata[38] i:/WORK/quasar_wrapper/io_dma_brg_w_bits_data[38]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_wdata[39] i:/WORK/quasar_wrapper/io_dma_brg_w_bits_data[39]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_wdata[3] i:/WORK/quasar_wrapper/io_dma_brg_w_bits_data[3]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_wdata[40] i:/WORK/quasar_wrapper/io_dma_brg_w_bits_data[40]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_wdata[41] i:/WORK/quasar_wrapper/io_dma_brg_w_bits_data[41]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_wdata[42] i:/WORK/quasar_wrapper/io_dma_brg_w_bits_data[42]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_wdata[43] i:/WORK/quasar_wrapper/io_dma_brg_w_bits_data[43]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_wdata[44] i:/WORK/quasar_wrapper/io_dma_brg_w_bits_data[44]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_wdata[45] i:/WORK/quasar_wrapper/io_dma_brg_w_bits_data[45]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_wdata[46] i:/WORK/quasar_wrapper/io_dma_brg_w_bits_data[46]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_wdata[47] i:/WORK/quasar_wrapper/io_dma_brg_w_bits_data[47]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_wdata[48] i:/WORK/quasar_wrapper/io_dma_brg_w_bits_data[48]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_wdata[49] i:/WORK/quasar_wrapper/io_dma_brg_w_bits_data[49]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_wdata[4] i:/WORK/quasar_wrapper/io_dma_brg_w_bits_data[4]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_wdata[50] i:/WORK/quasar_wrapper/io_dma_brg_w_bits_data[50]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_wdata[51] i:/WORK/quasar_wrapper/io_dma_brg_w_bits_data[51]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_wdata[52] i:/WORK/quasar_wrapper/io_dma_brg_w_bits_data[52]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_wdata[53] i:/WORK/quasar_wrapper/io_dma_brg_w_bits_data[53]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_wdata[54] i:/WORK/quasar_wrapper/io_dma_brg_w_bits_data[54]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_wdata[55] i:/WORK/quasar_wrapper/io_dma_brg_w_bits_data[55]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_wdata[56] i:/WORK/quasar_wrapper/io_dma_brg_w_bits_data[56]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_wdata[57] i:/WORK/quasar_wrapper/io_dma_brg_w_bits_data[57]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_wdata[58] i:/WORK/quasar_wrapper/io_dma_brg_w_bits_data[58]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_wdata[59] i:/WORK/quasar_wrapper/io_dma_brg_w_bits_data[59]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_wdata[5] i:/WORK/quasar_wrapper/io_dma_brg_w_bits_data[5]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_wdata[60] i:/WORK/quasar_wrapper/io_dma_brg_w_bits_data[60]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_wdata[61] i:/WORK/quasar_wrapper/io_dma_brg_w_bits_data[61]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_wdata[62] i:/WORK/quasar_wrapper/io_dma_brg_w_bits_data[62]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_wdata[63] i:/WORK/quasar_wrapper/io_dma_brg_w_bits_data[63]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_wdata[6] i:/WORK/quasar_wrapper/io_dma_brg_w_bits_data[6]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_wdata[7] i:/WORK/quasar_wrapper/io_dma_brg_w_bits_data[7]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_wdata[8] i:/WORK/quasar_wrapper/io_dma_brg_w_bits_data[8]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_wdata[9] i:/WORK/quasar_wrapper/io_dma_brg_w_bits_data[9]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_wstrb[0] i:/WORK/quasar_wrapper/io_dma_brg_w_bits_strb[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_wstrb[1] i:/WORK/quasar_wrapper/io_dma_brg_w_bits_strb[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_wstrb[2] i:/WORK/quasar_wrapper/io_dma_brg_w_bits_strb[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_wstrb[3] i:/WORK/quasar_wrapper/io_dma_brg_w_bits_strb[3]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_wstrb[4] i:/WORK/quasar_wrapper/io_dma_brg_w_bits_strb[4]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_wstrb[5] i:/WORK/quasar_wrapper/io_dma_brg_w_bits_strb[5]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_wstrb[6] i:/WORK/quasar_wrapper/io_dma_brg_w_bits_strb[6]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_wstrb[7] i:/WORK/quasar_wrapper/io_dma_brg_w_bits_strb[7]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_wvalid i:/WORK/quasar_wrapper/io_dma_brg_w_valid
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_bus_clk_en i:/WORK/quasar_wrapper/io_dma_bus_clk_en
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/extintsrc_req[10] i:/WORK/quasar_wrapper/io_extintsrc_req[9]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/extintsrc_req[11] i:/WORK/quasar_wrapper/io_extintsrc_req[10]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/extintsrc_req[12] i:/WORK/quasar_wrapper/io_extintsrc_req[11]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/extintsrc_req[13] i:/WORK/quasar_wrapper/io_extintsrc_req[12]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/extintsrc_req[14] i:/WORK/quasar_wrapper/io_extintsrc_req[13]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/extintsrc_req[15] i:/WORK/quasar_wrapper/io_extintsrc_req[14]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/extintsrc_req[16] i:/WORK/quasar_wrapper/io_extintsrc_req[15]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/extintsrc_req[17] i:/WORK/quasar_wrapper/io_extintsrc_req[16]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/extintsrc_req[18] i:/WORK/quasar_wrapper/io_extintsrc_req[17]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/extintsrc_req[19] i:/WORK/quasar_wrapper/io_extintsrc_req[18]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/extintsrc_req[1] i:/WORK/quasar_wrapper/io_extintsrc_req[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/extintsrc_req[20] i:/WORK/quasar_wrapper/io_extintsrc_req[19]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/extintsrc_req[21] i:/WORK/quasar_wrapper/io_extintsrc_req[20]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/extintsrc_req[22] i:/WORK/quasar_wrapper/io_extintsrc_req[21]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/extintsrc_req[23] i:/WORK/quasar_wrapper/io_extintsrc_req[22]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/extintsrc_req[24] i:/WORK/quasar_wrapper/io_extintsrc_req[23]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/extintsrc_req[25] i:/WORK/quasar_wrapper/io_extintsrc_req[24]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/extintsrc_req[26] i:/WORK/quasar_wrapper/io_extintsrc_req[25]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/extintsrc_req[27] i:/WORK/quasar_wrapper/io_extintsrc_req[26]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/extintsrc_req[28] i:/WORK/quasar_wrapper/io_extintsrc_req[27]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/extintsrc_req[29] i:/WORK/quasar_wrapper/io_extintsrc_req[28]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/extintsrc_req[2] i:/WORK/quasar_wrapper/io_extintsrc_req[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/extintsrc_req[30] i:/WORK/quasar_wrapper/io_extintsrc_req[29]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/extintsrc_req[31] i:/WORK/quasar_wrapper/io_extintsrc_req[30]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/extintsrc_req[3] i:/WORK/quasar_wrapper/io_extintsrc_req[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/extintsrc_req[4] i:/WORK/quasar_wrapper/io_extintsrc_req[3]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/extintsrc_req[5] i:/WORK/quasar_wrapper/io_extintsrc_req[4]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/extintsrc_req[6] i:/WORK/quasar_wrapper/io_extintsrc_req[5]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/extintsrc_req[7] i:/WORK/quasar_wrapper/io_extintsrc_req[6]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/extintsrc_req[8] i:/WORK/quasar_wrapper/io_extintsrc_req[7]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/extintsrc_req[9] i:/WORK/quasar_wrapper/io_extintsrc_req[8]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/i_cpu_halt_req i:/WORK/quasar_wrapper/io_i_cpu_halt_req
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/i_cpu_run_req i:/WORK/quasar_wrapper/io_i_cpu_run_req
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ic_data_ext_in_pkt[0][0]\[BC1] i:/WORK/quasar_wrapper/io_ic_data_ext_in_pkt_0_BC1_0
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ic_data_ext_in_pkt[0][0]\[BC2] i:/WORK/quasar_wrapper/io_ic_data_ext_in_pkt_0_BC2_0
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ic_data_ext_in_pkt[0][0]\[DS] i:/WORK/quasar_wrapper/io_ic_data_ext_in_pkt_0_DS_0
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ic_data_ext_in_pkt[0][0]\[LS] i:/WORK/quasar_wrapper/io_ic_data_ext_in_pkt_0_LS_0
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ic_data_ext_in_pkt[0][0]\[RME] i:/WORK/quasar_wrapper/io_ic_data_ext_in_pkt_0_RME_0
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ic_data_ext_in_pkt[0][0]\[RM][0] i:/WORK/quasar_wrapper/io_ic_data_ext_in_pkt_0_RM_0[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ic_data_ext_in_pkt[0][0]\[RM][1] i:/WORK/quasar_wrapper/io_ic_data_ext_in_pkt_0_RM_0[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ic_data_ext_in_pkt[0][0]\[RM][2] i:/WORK/quasar_wrapper/io_ic_data_ext_in_pkt_0_RM_0[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ic_data_ext_in_pkt[0][0]\[RM][3] i:/WORK/quasar_wrapper/io_ic_data_ext_in_pkt_0_RM_0[3]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ic_data_ext_in_pkt[0][0]\[SD] i:/WORK/quasar_wrapper/io_ic_data_ext_in_pkt_0_SD_0
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ic_data_ext_in_pkt[0][0]\[TEST1] i:/WORK/quasar_wrapper/io_ic_data_ext_in_pkt_0_TEST1_0
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ic_data_ext_in_pkt[0][0]\[TEST_RNM] i:/WORK/quasar_wrapper/io_ic_data_ext_in_pkt_0_TEST_RNM_0
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ic_data_ext_in_pkt[0][1]\[BC1] i:/WORK/quasar_wrapper/io_ic_data_ext_in_pkt_0_BC1_1
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ic_data_ext_in_pkt[0][1]\[BC2] i:/WORK/quasar_wrapper/io_ic_data_ext_in_pkt_0_BC2_1
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ic_data_ext_in_pkt[0][1]\[DS] i:/WORK/quasar_wrapper/io_ic_data_ext_in_pkt_0_DS_1
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ic_data_ext_in_pkt[0][1]\[LS] i:/WORK/quasar_wrapper/io_ic_data_ext_in_pkt_0_LS_1
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ic_data_ext_in_pkt[0][1]\[RME] i:/WORK/quasar_wrapper/io_ic_data_ext_in_pkt_0_RME_1
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ic_data_ext_in_pkt[0][1]\[RM][0] i:/WORK/quasar_wrapper/io_ic_data_ext_in_pkt_0_RM_1[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ic_data_ext_in_pkt[0][1]\[RM][1] i:/WORK/quasar_wrapper/io_ic_data_ext_in_pkt_0_RM_1[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ic_data_ext_in_pkt[0][1]\[RM][2] i:/WORK/quasar_wrapper/io_ic_data_ext_in_pkt_0_RM_1[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ic_data_ext_in_pkt[0][1]\[RM][3] i:/WORK/quasar_wrapper/io_ic_data_ext_in_pkt_0_RM_1[3]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ic_data_ext_in_pkt[0][1]\[SD] i:/WORK/quasar_wrapper/io_ic_data_ext_in_pkt_0_SD_1
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ic_data_ext_in_pkt[0][1]\[TEST1] i:/WORK/quasar_wrapper/io_ic_data_ext_in_pkt_0_TEST1_1
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ic_data_ext_in_pkt[0][1]\[TEST_RNM] i:/WORK/quasar_wrapper/io_ic_data_ext_in_pkt_0_TEST_RNM_1
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ic_data_ext_in_pkt[1][0]\[BC1] i:/WORK/quasar_wrapper/io_ic_data_ext_in_pkt_1_BC1_0
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ic_data_ext_in_pkt[1][0]\[BC2] i:/WORK/quasar_wrapper/io_ic_data_ext_in_pkt_1_BC2_0
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ic_data_ext_in_pkt[1][0]\[DS] i:/WORK/quasar_wrapper/io_ic_data_ext_in_pkt_1_DS_0
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ic_data_ext_in_pkt[1][0]\[LS] i:/WORK/quasar_wrapper/io_ic_data_ext_in_pkt_1_LS_0
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ic_data_ext_in_pkt[1][0]\[RME] i:/WORK/quasar_wrapper/io_ic_data_ext_in_pkt_1_RME_0
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ic_data_ext_in_pkt[1][0]\[RM][0] i:/WORK/quasar_wrapper/io_ic_data_ext_in_pkt_1_RM_0[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ic_data_ext_in_pkt[1][0]\[RM][1] i:/WORK/quasar_wrapper/io_ic_data_ext_in_pkt_1_RM_0[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ic_data_ext_in_pkt[1][0]\[RM][2] i:/WORK/quasar_wrapper/io_ic_data_ext_in_pkt_1_RM_0[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ic_data_ext_in_pkt[1][0]\[RM][3] i:/WORK/quasar_wrapper/io_ic_data_ext_in_pkt_1_RM_0[3]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ic_data_ext_in_pkt[1][0]\[SD] i:/WORK/quasar_wrapper/io_ic_data_ext_in_pkt_1_SD_0
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ic_data_ext_in_pkt[1][0]\[TEST1] i:/WORK/quasar_wrapper/io_ic_data_ext_in_pkt_1_TEST1_0
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ic_data_ext_in_pkt[1][0]\[TEST_RNM] i:/WORK/quasar_wrapper/io_ic_data_ext_in_pkt_1_TEST_RNM_0
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ic_data_ext_in_pkt[1][1]\[BC1] i:/WORK/quasar_wrapper/io_ic_data_ext_in_pkt_1_BC1_1
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ic_data_ext_in_pkt[1][1]\[BC2] i:/WORK/quasar_wrapper/io_ic_data_ext_in_pkt_1_BC2_1
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ic_data_ext_in_pkt[1][1]\[DS] i:/WORK/quasar_wrapper/io_ic_data_ext_in_pkt_1_DS_1
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ic_data_ext_in_pkt[1][1]\[LS] i:/WORK/quasar_wrapper/io_ic_data_ext_in_pkt_1_LS_1
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ic_data_ext_in_pkt[1][1]\[RME] i:/WORK/quasar_wrapper/io_ic_data_ext_in_pkt_1_RME_1
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ic_data_ext_in_pkt[1][1]\[RM][0] i:/WORK/quasar_wrapper/io_ic_data_ext_in_pkt_1_RM_1[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ic_data_ext_in_pkt[1][1]\[RM][1] i:/WORK/quasar_wrapper/io_ic_data_ext_in_pkt_1_RM_1[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ic_data_ext_in_pkt[1][1]\[RM][2] i:/WORK/quasar_wrapper/io_ic_data_ext_in_pkt_1_RM_1[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ic_data_ext_in_pkt[1][1]\[RM][3] i:/WORK/quasar_wrapper/io_ic_data_ext_in_pkt_1_RM_1[3]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ic_data_ext_in_pkt[1][1]\[SD] i:/WORK/quasar_wrapper/io_ic_data_ext_in_pkt_1_SD_1
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ic_data_ext_in_pkt[1][1]\[TEST1] i:/WORK/quasar_wrapper/io_ic_data_ext_in_pkt_1_TEST1_1
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ic_data_ext_in_pkt[1][1]\[TEST_RNM] i:/WORK/quasar_wrapper/io_ic_data_ext_in_pkt_1_TEST_RNM_1
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ic_tag_ext_in_pkt[0]\[BC1] i:/WORK/quasar_wrapper/io_ic_tag_ext_in_pkt_BC1_0
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ic_tag_ext_in_pkt[0]\[BC2] i:/WORK/quasar_wrapper/io_ic_tag_ext_in_pkt_BC2_0
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ic_tag_ext_in_pkt[0]\[DS] i:/WORK/quasar_wrapper/io_ic_tag_ext_in_pkt_DS_0
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ic_tag_ext_in_pkt[0]\[LS] i:/WORK/quasar_wrapper/io_ic_tag_ext_in_pkt_LS_0
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ic_tag_ext_in_pkt[0]\[RME] i:/WORK/quasar_wrapper/io_ic_tag_ext_in_pkt_RME_0
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ic_tag_ext_in_pkt[0]\[RM][0] i:/WORK/quasar_wrapper/io_ic_tag_ext_in_pkt_RM_0[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ic_tag_ext_in_pkt[0]\[RM][1] i:/WORK/quasar_wrapper/io_ic_tag_ext_in_pkt_RM_1[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ic_tag_ext_in_pkt[0]\[RM][2] i:/WORK/quasar_wrapper/io_ic_tag_ext_in_pkt_RM_0[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ic_tag_ext_in_pkt[0]\[RM][3] i:/WORK/quasar_wrapper/io_ic_tag_ext_in_pkt_RM_0[3]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ic_tag_ext_in_pkt[0]\[SD] i:/WORK/quasar_wrapper/io_ic_tag_ext_in_pkt_SD_0
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ic_tag_ext_in_pkt[0]\[TEST1] i:/WORK/quasar_wrapper/io_ic_tag_ext_in_pkt_TEST1_0
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ic_tag_ext_in_pkt[0]\[TEST_RNM] i:/WORK/quasar_wrapper/io_ic_tag_ext_in_pkt_TEST_RNM_0
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ic_tag_ext_in_pkt[1]\[BC1] i:/WORK/quasar_wrapper/io_ic_tag_ext_in_pkt_BC1_1
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ic_tag_ext_in_pkt[1]\[BC2] i:/WORK/quasar_wrapper/io_ic_tag_ext_in_pkt_BC2_1
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ic_tag_ext_in_pkt[1]\[DS] i:/WORK/quasar_wrapper/io_ic_tag_ext_in_pkt_DS_1
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ic_tag_ext_in_pkt[1]\[LS] i:/WORK/quasar_wrapper/io_ic_tag_ext_in_pkt_LS_1
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ic_tag_ext_in_pkt[1]\[RME] i:/WORK/quasar_wrapper/io_ic_tag_ext_in_pkt_RME_1
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ic_tag_ext_in_pkt[1]\[RM][0] i:/WORK/quasar_wrapper/io_ic_tag_ext_in_pkt_RM_0[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ic_tag_ext_in_pkt[1]\[RM][1] i:/WORK/quasar_wrapper/io_ic_tag_ext_in_pkt_RM_1[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ic_tag_ext_in_pkt[1]\[RM][2] i:/WORK/quasar_wrapper/io_ic_tag_ext_in_pkt_RM_1[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ic_tag_ext_in_pkt[1]\[RM][3] i:/WORK/quasar_wrapper/io_ic_tag_ext_in_pkt_RM_1[3]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ic_tag_ext_in_pkt[1]\[SD] i:/WORK/quasar_wrapper/io_ic_tag_ext_in_pkt_SD_1
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ic_tag_ext_in_pkt[1]\[TEST1] i:/WORK/quasar_wrapper/io_ic_tag_ext_in_pkt_TEST1_1
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ic_tag_ext_in_pkt[1]\[TEST_RNM] i:/WORK/quasar_wrapper/io_ic_tag_ext_in_pkt_TEST_RNM_1
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/iccm_ext_in_pkt[0]\[BC1] i:/WORK/quasar_wrapper/io_iccm_ext_in_pkt_BC1_0
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/iccm_ext_in_pkt[0]\[BC2] i:/WORK/quasar_wrapper/io_iccm_ext_in_pkt_BC1_1
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/iccm_ext_in_pkt[0]\[DS] i:/WORK/quasar_wrapper/io_iccm_ext_in_pkt_BC1_2
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/iccm_ext_in_pkt[0]\[LS] i:/WORK/quasar_wrapper/io_iccm_ext_in_pkt_BC1_3
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/iccm_ext_in_pkt[0]\[RME] i:/WORK/quasar_wrapper/io_iccm_ext_in_pkt_BC2_0
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/iccm_ext_in_pkt[0]\[RM][0] i:/WORK/quasar_wrapper/io_iccm_ext_in_pkt_RM_0[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/iccm_ext_in_pkt[0]\[RM][1] i:/WORK/quasar_wrapper/io_iccm_ext_in_pkt_RM_1[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/iccm_ext_in_pkt[0]\[RM][2] i:/WORK/quasar_wrapper/io_iccm_ext_in_pkt_RM_2[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/iccm_ext_in_pkt[0]\[RM][3] i:/WORK/quasar_wrapper/io_iccm_ext_in_pkt_RM_3[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/iccm_ext_in_pkt[0]\[SD] i:/WORK/quasar_wrapper/io_iccm_ext_in_pkt_BC2_1
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/iccm_ext_in_pkt[0]\[TEST1] i:/WORK/quasar_wrapper/io_iccm_ext_in_pkt_BC2_2
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/iccm_ext_in_pkt[0]\[TEST_RNM] i:/WORK/quasar_wrapper/io_iccm_ext_in_pkt_BC2_3
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/iccm_ext_in_pkt[1]\[BC1] i:/WORK/quasar_wrapper/io_iccm_ext_in_pkt_DS_0
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/iccm_ext_in_pkt[1]\[BC2] i:/WORK/quasar_wrapper/io_iccm_ext_in_pkt_DS_1
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/iccm_ext_in_pkt[1]\[DS] i:/WORK/quasar_wrapper/io_iccm_ext_in_pkt_DS_2
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/iccm_ext_in_pkt[1]\[LS] i:/WORK/quasar_wrapper/io_iccm_ext_in_pkt_DS_3
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/iccm_ext_in_pkt[1]\[RME] i:/WORK/quasar_wrapper/io_iccm_ext_in_pkt_LS_0
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/iccm_ext_in_pkt[1]\[RM][0] i:/WORK/quasar_wrapper/io_iccm_ext_in_pkt_RM_0[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/iccm_ext_in_pkt[1]\[RM][1] i:/WORK/quasar_wrapper/io_iccm_ext_in_pkt_RM_1[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/iccm_ext_in_pkt[1]\[RM][2] i:/WORK/quasar_wrapper/io_iccm_ext_in_pkt_RM_2[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/iccm_ext_in_pkt[1]\[RM][3] i:/WORK/quasar_wrapper/io_iccm_ext_in_pkt_RM_3[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/iccm_ext_in_pkt[1]\[SD] i:/WORK/quasar_wrapper/io_iccm_ext_in_pkt_LS_1
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/iccm_ext_in_pkt[1]\[TEST1] i:/WORK/quasar_wrapper/io_iccm_ext_in_pkt_LS_2
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/iccm_ext_in_pkt[1]\[TEST_RNM] i:/WORK/quasar_wrapper/io_iccm_ext_in_pkt_LS_3
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/iccm_ext_in_pkt[2]\[BC1] i:/WORK/quasar_wrapper/io_iccm_ext_in_pkt_RME_0
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/iccm_ext_in_pkt[2]\[BC2] i:/WORK/quasar_wrapper/io_iccm_ext_in_pkt_RME_1
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/iccm_ext_in_pkt[2]\[DS] i:/WORK/quasar_wrapper/io_iccm_ext_in_pkt_RME_2
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/iccm_ext_in_pkt[2]\[LS] i:/WORK/quasar_wrapper/io_iccm_ext_in_pkt_RME_3
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/iccm_ext_in_pkt[2]\[RME] i:/WORK/quasar_wrapper/io_iccm_ext_in_pkt_RM_0[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/iccm_ext_in_pkt[2]\[RM][0] i:/WORK/quasar_wrapper/io_iccm_ext_in_pkt_RM_0[3]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/iccm_ext_in_pkt[2]\[RM][1] i:/WORK/quasar_wrapper/io_iccm_ext_in_pkt_RM_1[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/iccm_ext_in_pkt[2]\[RM][2] i:/WORK/quasar_wrapper/io_iccm_ext_in_pkt_RM_1[3]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/iccm_ext_in_pkt[2]\[RM][3] i:/WORK/quasar_wrapper/io_iccm_ext_in_pkt_RM_2[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/iccm_ext_in_pkt[2]\[SD] i:/WORK/quasar_wrapper/io_iccm_ext_in_pkt_RM_2[3]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/iccm_ext_in_pkt[2]\[TEST1] i:/WORK/quasar_wrapper/io_iccm_ext_in_pkt_RM_3[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/iccm_ext_in_pkt[2]\[TEST_RNM] i:/WORK/quasar_wrapper/io_iccm_ext_in_pkt_RM_3[3]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/iccm_ext_in_pkt[3]\[BC1] i:/WORK/quasar_wrapper/io_iccm_ext_in_pkt_SD_0
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/iccm_ext_in_pkt[3]\[BC2] i:/WORK/quasar_wrapper/io_iccm_ext_in_pkt_SD_1
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/iccm_ext_in_pkt[3]\[DS] i:/WORK/quasar_wrapper/io_iccm_ext_in_pkt_SD_2
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/iccm_ext_in_pkt[3]\[LS] i:/WORK/quasar_wrapper/io_iccm_ext_in_pkt_SD_3
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/iccm_ext_in_pkt[3]\[RME] i:/WORK/quasar_wrapper/io_iccm_ext_in_pkt_TEST1_0
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/iccm_ext_in_pkt[3]\[RM][0] i:/WORK/quasar_wrapper/io_iccm_ext_in_pkt_TEST1_1
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/iccm_ext_in_pkt[3]\[RM][1] i:/WORK/quasar_wrapper/io_iccm_ext_in_pkt_TEST1_2
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/iccm_ext_in_pkt[3]\[RM][2] i:/WORK/quasar_wrapper/io_iccm_ext_in_pkt_TEST1_3
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/iccm_ext_in_pkt[3]\[RM][3] i:/WORK/quasar_wrapper/io_iccm_ext_in_pkt_TEST_RNM_0
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/iccm_ext_in_pkt[3]\[SD] i:/WORK/quasar_wrapper/io_iccm_ext_in_pkt_TEST_RNM_1
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/iccm_ext_in_pkt[3]\[TEST1] i:/WORK/quasar_wrapper/io_iccm_ext_in_pkt_TEST_RNM_2
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/iccm_ext_in_pkt[3]\[TEST_RNM] i:/WORK/quasar_wrapper/io_iccm_ext_in_pkt_TEST_RNM_3
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_arready i:/WORK/quasar_wrapper/io_ifu_brg_ar_ready
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_rdata[0] i:/WORK/quasar_wrapper/io_ifu_brg_r_bits_data[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_rdata[10] i:/WORK/quasar_wrapper/io_ifu_brg_r_bits_data[10]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_rdata[11] i:/WORK/quasar_wrapper/io_ifu_brg_r_bits_data[11]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_rdata[12] i:/WORK/quasar_wrapper/io_ifu_brg_r_bits_data[12]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_rdata[13] i:/WORK/quasar_wrapper/io_ifu_brg_r_bits_data[13]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_rdata[14] i:/WORK/quasar_wrapper/io_ifu_brg_r_bits_data[14]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_rdata[15] i:/WORK/quasar_wrapper/io_ifu_brg_r_bits_data[15]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_rdata[16] i:/WORK/quasar_wrapper/io_ifu_brg_r_bits_data[16]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_rdata[17] i:/WORK/quasar_wrapper/io_ifu_brg_r_bits_data[17]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_rdata[18] i:/WORK/quasar_wrapper/io_ifu_brg_r_bits_data[18]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_rdata[19] i:/WORK/quasar_wrapper/io_ifu_brg_r_bits_data[19]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_rdata[1] i:/WORK/quasar_wrapper/io_ifu_brg_r_bits_data[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_rdata[20] i:/WORK/quasar_wrapper/io_ifu_brg_r_bits_data[20]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_rdata[21] i:/WORK/quasar_wrapper/io_ifu_brg_r_bits_data[21]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_rdata[22] i:/WORK/quasar_wrapper/io_ifu_brg_r_bits_data[22]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_rdata[23] i:/WORK/quasar_wrapper/io_ifu_brg_r_bits_data[23]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_rdata[24] i:/WORK/quasar_wrapper/io_ifu_brg_r_bits_data[24]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_rdata[25] i:/WORK/quasar_wrapper/io_ifu_brg_r_bits_data[25]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_rdata[26] i:/WORK/quasar_wrapper/io_ifu_brg_r_bits_data[26]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_rdata[27] i:/WORK/quasar_wrapper/io_ifu_brg_r_bits_data[27]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_rdata[28] i:/WORK/quasar_wrapper/io_ifu_brg_r_bits_data[28]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_rdata[29] i:/WORK/quasar_wrapper/io_ifu_brg_r_bits_data[29]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_rdata[2] i:/WORK/quasar_wrapper/io_ifu_brg_r_bits_data[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_rdata[30] i:/WORK/quasar_wrapper/io_ifu_brg_r_bits_data[30]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_rdata[31] i:/WORK/quasar_wrapper/io_ifu_brg_r_bits_data[31]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_rdata[32] i:/WORK/quasar_wrapper/io_ifu_brg_r_bits_data[32]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_rdata[33] i:/WORK/quasar_wrapper/io_ifu_brg_r_bits_data[33]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_rdata[34] i:/WORK/quasar_wrapper/io_ifu_brg_r_bits_data[34]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_rdata[35] i:/WORK/quasar_wrapper/io_ifu_brg_r_bits_data[35]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_rdata[36] i:/WORK/quasar_wrapper/io_ifu_brg_r_bits_data[36]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_rdata[37] i:/WORK/quasar_wrapper/io_ifu_brg_r_bits_data[37]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_rdata[38] i:/WORK/quasar_wrapper/io_ifu_brg_r_bits_data[38]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_rdata[39] i:/WORK/quasar_wrapper/io_ifu_brg_r_bits_data[39]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_rdata[3] i:/WORK/quasar_wrapper/io_ifu_brg_r_bits_data[3]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_rdata[40] i:/WORK/quasar_wrapper/io_ifu_brg_r_bits_data[40]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_rdata[41] i:/WORK/quasar_wrapper/io_ifu_brg_r_bits_data[41]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_rdata[42] i:/WORK/quasar_wrapper/io_ifu_brg_r_bits_data[42]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_rdata[43] i:/WORK/quasar_wrapper/io_ifu_brg_r_bits_data[43]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_rdata[44] i:/WORK/quasar_wrapper/io_ifu_brg_r_bits_data[44]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_rdata[45] i:/WORK/quasar_wrapper/io_ifu_brg_r_bits_data[45]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_rdata[46] i:/WORK/quasar_wrapper/io_ifu_brg_r_bits_data[46]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_rdata[47] i:/WORK/quasar_wrapper/io_ifu_brg_r_bits_data[47]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_rdata[48] i:/WORK/quasar_wrapper/io_ifu_brg_r_bits_data[48]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_rdata[49] i:/WORK/quasar_wrapper/io_ifu_brg_r_bits_data[49]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_rdata[4] i:/WORK/quasar_wrapper/io_ifu_brg_r_bits_data[4]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_rdata[50] i:/WORK/quasar_wrapper/io_ifu_brg_r_bits_data[50]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_rdata[51] i:/WORK/quasar_wrapper/io_ifu_brg_r_bits_data[51]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_rdata[52] i:/WORK/quasar_wrapper/io_ifu_brg_r_bits_data[52]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_rdata[53] i:/WORK/quasar_wrapper/io_ifu_brg_r_bits_data[53]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_rdata[54] i:/WORK/quasar_wrapper/io_ifu_brg_r_bits_data[54]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_rdata[55] i:/WORK/quasar_wrapper/io_ifu_brg_r_bits_data[55]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_rdata[56] i:/WORK/quasar_wrapper/io_ifu_brg_r_bits_data[56]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_rdata[57] i:/WORK/quasar_wrapper/io_ifu_brg_r_bits_data[57]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_rdata[58] i:/WORK/quasar_wrapper/io_ifu_brg_r_bits_data[58]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_rdata[59] i:/WORK/quasar_wrapper/io_ifu_brg_r_bits_data[59]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_rdata[5] i:/WORK/quasar_wrapper/io_ifu_brg_r_bits_data[5]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_rdata[60] i:/WORK/quasar_wrapper/io_ifu_brg_r_bits_data[60]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_rdata[61] i:/WORK/quasar_wrapper/io_ifu_brg_r_bits_data[61]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_rdata[62] i:/WORK/quasar_wrapper/io_ifu_brg_r_bits_data[62]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_rdata[63] i:/WORK/quasar_wrapper/io_ifu_brg_r_bits_data[63]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_rdata[6] i:/WORK/quasar_wrapper/io_ifu_brg_r_bits_data[6]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_rdata[7] i:/WORK/quasar_wrapper/io_ifu_brg_r_bits_data[7]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_rdata[8] i:/WORK/quasar_wrapper/io_ifu_brg_r_bits_data[8]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_rdata[9] i:/WORK/quasar_wrapper/io_ifu_brg_r_bits_data[9]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_rid[0] i:/WORK/quasar_wrapper/io_ifu_brg_r_bits_id[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_rid[1] i:/WORK/quasar_wrapper/io_ifu_brg_r_bits_id[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_rid[2] i:/WORK/quasar_wrapper/io_ifu_brg_r_bits_id[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_rresp[0] i:/WORK/quasar_wrapper/io_ifu_brg_r_bits_resp[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_rresp[1] i:/WORK/quasar_wrapper/io_ifu_brg_r_bits_resp[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_rvalid i:/WORK/quasar_wrapper/io_ifu_brg_r_valid
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_bus_clk_en i:/WORK/quasar_wrapper/io_ifu_bus_clk_en
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/jtag_id[10] i:/WORK/quasar_wrapper/io_jtag_id[9]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/jtag_id[11] i:/WORK/quasar_wrapper/io_jtag_id[10]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/jtag_id[12] i:/WORK/quasar_wrapper/io_jtag_id[11]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/jtag_id[13] i:/WORK/quasar_wrapper/io_jtag_id[12]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/jtag_id[14] i:/WORK/quasar_wrapper/io_jtag_id[13]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/jtag_id[15] i:/WORK/quasar_wrapper/io_jtag_id[14]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/jtag_id[16] i:/WORK/quasar_wrapper/io_jtag_id[15]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/jtag_id[17] i:/WORK/quasar_wrapper/io_jtag_id[16]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/jtag_id[18] i:/WORK/quasar_wrapper/io_jtag_id[17]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/jtag_id[19] i:/WORK/quasar_wrapper/io_jtag_id[18]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/jtag_id[1] i:/WORK/quasar_wrapper/io_jtag_id[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/jtag_id[20] i:/WORK/quasar_wrapper/io_jtag_id[19]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/jtag_id[21] i:/WORK/quasar_wrapper/io_jtag_id[20]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/jtag_id[22] i:/WORK/quasar_wrapper/io_jtag_id[21]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/jtag_id[23] i:/WORK/quasar_wrapper/io_jtag_id[22]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/jtag_id[24] i:/WORK/quasar_wrapper/io_jtag_id[23]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/jtag_id[25] i:/WORK/quasar_wrapper/io_jtag_id[24]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/jtag_id[26] i:/WORK/quasar_wrapper/io_jtag_id[25]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/jtag_id[27] i:/WORK/quasar_wrapper/io_jtag_id[26]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/jtag_id[28] i:/WORK/quasar_wrapper/io_jtag_id[27]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/jtag_id[29] i:/WORK/quasar_wrapper/io_jtag_id[28]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/jtag_id[2] i:/WORK/quasar_wrapper/io_jtag_id[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/jtag_id[30] i:/WORK/quasar_wrapper/io_jtag_id[29]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/jtag_id[31] i:/WORK/quasar_wrapper/io_jtag_id[30]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/jtag_id[3] i:/WORK/quasar_wrapper/io_jtag_id[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/jtag_id[4] i:/WORK/quasar_wrapper/io_jtag_id[3]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/jtag_id[5] i:/WORK/quasar_wrapper/io_jtag_id[4]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/jtag_id[6] i:/WORK/quasar_wrapper/io_jtag_id[5]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/jtag_id[7] i:/WORK/quasar_wrapper/io_jtag_id[6]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/jtag_id[8] i:/WORK/quasar_wrapper/io_jtag_id[7]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/jtag_id[9] i:/WORK/quasar_wrapper/io_jtag_id[8]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/jtag_tck i:/WORK/quasar_wrapper/io_jtag_tck
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/jtag_tdi i:/WORK/quasar_wrapper/io_jtag_tdi
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/jtag_tms i:/WORK/quasar_wrapper/io_jtag_tms
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/jtag_trst_n i:/WORK/quasar_wrapper/io_jtag_trst_n
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_arready i:/WORK/quasar_wrapper/io_lsu_brg_ar_ready
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_awready i:/WORK/quasar_wrapper/io_lsu_brg_aw_ready
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_bid[0] i:/WORK/quasar_wrapper/io_lsu_brg_b_bits_id[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_bid[1] i:/WORK/quasar_wrapper/io_lsu_brg_b_bits_id[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_bid[2] i:/WORK/quasar_wrapper/io_lsu_brg_b_bits_id[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_bresp[0] i:/WORK/quasar_wrapper/io_lsu_brg_b_bits_resp[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_bresp[1] i:/WORK/quasar_wrapper/io_lsu_brg_b_bits_resp[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_bvalid i:/WORK/quasar_wrapper/io_lsu_brg_b_valid
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_rdata[0] i:/WORK/quasar_wrapper/io_lsu_brg_r_bits_data[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_rdata[10] i:/WORK/quasar_wrapper/io_lsu_brg_r_bits_data[10]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_rdata[11] i:/WORK/quasar_wrapper/io_lsu_brg_r_bits_data[11]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_rdata[12] i:/WORK/quasar_wrapper/io_lsu_brg_r_bits_data[12]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_rdata[13] i:/WORK/quasar_wrapper/io_lsu_brg_r_bits_data[13]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_rdata[14] i:/WORK/quasar_wrapper/io_lsu_brg_r_bits_data[14]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_rdata[15] i:/WORK/quasar_wrapper/io_lsu_brg_r_bits_data[15]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_rdata[16] i:/WORK/quasar_wrapper/io_lsu_brg_r_bits_data[16]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_rdata[17] i:/WORK/quasar_wrapper/io_lsu_brg_r_bits_data[17]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_rdata[18] i:/WORK/quasar_wrapper/io_lsu_brg_r_bits_data[18]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_rdata[19] i:/WORK/quasar_wrapper/io_lsu_brg_r_bits_data[19]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_rdata[1] i:/WORK/quasar_wrapper/io_lsu_brg_r_bits_data[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_rdata[20] i:/WORK/quasar_wrapper/io_lsu_brg_r_bits_data[20]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_rdata[21] i:/WORK/quasar_wrapper/io_lsu_brg_r_bits_data[21]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_rdata[22] i:/WORK/quasar_wrapper/io_lsu_brg_r_bits_data[22]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_rdata[23] i:/WORK/quasar_wrapper/io_lsu_brg_r_bits_data[23]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_rdata[24] i:/WORK/quasar_wrapper/io_lsu_brg_r_bits_data[24]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_rdata[25] i:/WORK/quasar_wrapper/io_lsu_brg_r_bits_data[25]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_rdata[26] i:/WORK/quasar_wrapper/io_lsu_brg_r_bits_data[26]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_rdata[27] i:/WORK/quasar_wrapper/io_lsu_brg_r_bits_data[27]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_rdata[28] i:/WORK/quasar_wrapper/io_lsu_brg_r_bits_data[28]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_rdata[29] i:/WORK/quasar_wrapper/io_lsu_brg_r_bits_data[29]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_rdata[2] i:/WORK/quasar_wrapper/io_lsu_brg_r_bits_data[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_rdata[30] i:/WORK/quasar_wrapper/io_lsu_brg_r_bits_data[30]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_rdata[31] i:/WORK/quasar_wrapper/io_lsu_brg_r_bits_data[31]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_rdata[32] i:/WORK/quasar_wrapper/io_lsu_brg_r_bits_data[32]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_rdata[33] i:/WORK/quasar_wrapper/io_lsu_brg_r_bits_data[33]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_rdata[34] i:/WORK/quasar_wrapper/io_lsu_brg_r_bits_data[34]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_rdata[35] i:/WORK/quasar_wrapper/io_lsu_brg_r_bits_data[35]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_rdata[36] i:/WORK/quasar_wrapper/io_lsu_brg_r_bits_data[36]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_rdata[37] i:/WORK/quasar_wrapper/io_lsu_brg_r_bits_data[37]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_rdata[38] i:/WORK/quasar_wrapper/io_lsu_brg_r_bits_data[38]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_rdata[39] i:/WORK/quasar_wrapper/io_lsu_brg_r_bits_data[39]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_rdata[3] i:/WORK/quasar_wrapper/io_lsu_brg_r_bits_data[3]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_rdata[40] i:/WORK/quasar_wrapper/io_lsu_brg_r_bits_data[40]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_rdata[41] i:/WORK/quasar_wrapper/io_lsu_brg_r_bits_data[41]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_rdata[42] i:/WORK/quasar_wrapper/io_lsu_brg_r_bits_data[42]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_rdata[43] i:/WORK/quasar_wrapper/io_lsu_brg_r_bits_data[43]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_rdata[44] i:/WORK/quasar_wrapper/io_lsu_brg_r_bits_data[44]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_rdata[45] i:/WORK/quasar_wrapper/io_lsu_brg_r_bits_data[45]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_rdata[46] i:/WORK/quasar_wrapper/io_lsu_brg_r_bits_data[46]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_rdata[47] i:/WORK/quasar_wrapper/io_lsu_brg_r_bits_data[47]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_rdata[48] i:/WORK/quasar_wrapper/io_lsu_brg_r_bits_data[48]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_rdata[49] i:/WORK/quasar_wrapper/io_lsu_brg_r_bits_data[49]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_rdata[4] i:/WORK/quasar_wrapper/io_lsu_brg_r_bits_data[4]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_rdata[50] i:/WORK/quasar_wrapper/io_lsu_brg_r_bits_data[50]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_rdata[51] i:/WORK/quasar_wrapper/io_lsu_brg_r_bits_data[51]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_rdata[52] i:/WORK/quasar_wrapper/io_lsu_brg_r_bits_data[52]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_rdata[53] i:/WORK/quasar_wrapper/io_lsu_brg_r_bits_data[53]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_rdata[54] i:/WORK/quasar_wrapper/io_lsu_brg_r_bits_data[54]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_rdata[55] i:/WORK/quasar_wrapper/io_lsu_brg_r_bits_data[55]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_rdata[56] i:/WORK/quasar_wrapper/io_lsu_brg_r_bits_data[56]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_rdata[57] i:/WORK/quasar_wrapper/io_lsu_brg_r_bits_data[57]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_rdata[58] i:/WORK/quasar_wrapper/io_lsu_brg_r_bits_data[58]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_rdata[59] i:/WORK/quasar_wrapper/io_lsu_brg_r_bits_data[59]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_rdata[5] i:/WORK/quasar_wrapper/io_lsu_brg_r_bits_data[5]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_rdata[60] i:/WORK/quasar_wrapper/io_lsu_brg_r_bits_data[60]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_rdata[61] i:/WORK/quasar_wrapper/io_lsu_brg_r_bits_data[61]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_rdata[62] i:/WORK/quasar_wrapper/io_lsu_brg_r_bits_data[62]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_rdata[63] i:/WORK/quasar_wrapper/io_lsu_brg_r_bits_data[63]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_rdata[6] i:/WORK/quasar_wrapper/io_lsu_brg_r_bits_data[6]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_rdata[7] i:/WORK/quasar_wrapper/io_lsu_brg_r_bits_data[7]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_rdata[8] i:/WORK/quasar_wrapper/io_lsu_brg_r_bits_data[8]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_rdata[9] i:/WORK/quasar_wrapper/io_lsu_brg_r_bits_data[9]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_rid[0] i:/WORK/quasar_wrapper/io_lsu_brg_r_bits_id[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_rid[1] i:/WORK/quasar_wrapper/io_lsu_brg_r_bits_id[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_rid[2] i:/WORK/quasar_wrapper/io_lsu_brg_r_bits_id[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_rresp[0] i:/WORK/quasar_wrapper/io_lsu_brg_r_bits_resp[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_rresp[1] i:/WORK/quasar_wrapper/io_lsu_brg_r_bits_resp[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_rvalid i:/WORK/quasar_wrapper/io_lsu_brg_r_valid
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_wready i:/WORK/quasar_wrapper/io_lsu_brg_w_ready
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_bus_clk_en i:/WORK/quasar_wrapper/io_lsu_bus_clk_en
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/mpc_debug_halt_req i:/WORK/quasar_wrapper/io_mpc_debug_halt_req
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/mpc_debug_run_req i:/WORK/quasar_wrapper/io_mpc_debug_run_req
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/mpc_reset_run_req i:/WORK/quasar_wrapper/io_mpc_reset_run_req
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/nmi_int i:/WORK/quasar_wrapper/io_nmi_int
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/nmi_vec[10] i:/WORK/quasar_wrapper/io_nmi_vec[9]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/nmi_vec[11] i:/WORK/quasar_wrapper/io_nmi_vec[10]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/nmi_vec[12] i:/WORK/quasar_wrapper/io_nmi_vec[11]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/nmi_vec[13] i:/WORK/quasar_wrapper/io_nmi_vec[12]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/nmi_vec[14] i:/WORK/quasar_wrapper/io_nmi_vec[13]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/nmi_vec[15] i:/WORK/quasar_wrapper/io_nmi_vec[14]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/nmi_vec[16] i:/WORK/quasar_wrapper/io_nmi_vec[15]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/nmi_vec[17] i:/WORK/quasar_wrapper/io_nmi_vec[16]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/nmi_vec[18] i:/WORK/quasar_wrapper/io_nmi_vec[17]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/nmi_vec[19] i:/WORK/quasar_wrapper/io_nmi_vec[18]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/nmi_vec[1] i:/WORK/quasar_wrapper/io_nmi_vec[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/nmi_vec[20] i:/WORK/quasar_wrapper/io_nmi_vec[19]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/nmi_vec[21] i:/WORK/quasar_wrapper/io_nmi_vec[20]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/nmi_vec[22] i:/WORK/quasar_wrapper/io_nmi_vec[21]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/nmi_vec[23] i:/WORK/quasar_wrapper/io_nmi_vec[22]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/nmi_vec[24] i:/WORK/quasar_wrapper/io_nmi_vec[23]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/nmi_vec[25] i:/WORK/quasar_wrapper/io_nmi_vec[24]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/nmi_vec[26] i:/WORK/quasar_wrapper/io_nmi_vec[25]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/nmi_vec[27] i:/WORK/quasar_wrapper/io_nmi_vec[26]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/nmi_vec[28] i:/WORK/quasar_wrapper/io_nmi_vec[27]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/nmi_vec[29] i:/WORK/quasar_wrapper/io_nmi_vec[28]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/nmi_vec[2] i:/WORK/quasar_wrapper/io_nmi_vec[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/nmi_vec[30] i:/WORK/quasar_wrapper/io_nmi_vec[29]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/nmi_vec[31] i:/WORK/quasar_wrapper/io_nmi_vec[30]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/nmi_vec[3] i:/WORK/quasar_wrapper/io_nmi_vec[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/nmi_vec[4] i:/WORK/quasar_wrapper/io_nmi_vec[3]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/nmi_vec[5] i:/WORK/quasar_wrapper/io_nmi_vec[4]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/nmi_vec[6] i:/WORK/quasar_wrapper/io_nmi_vec[5]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/nmi_vec[7] i:/WORK/quasar_wrapper/io_nmi_vec[6]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/nmi_vec[8] i:/WORK/quasar_wrapper/io_nmi_vec[7]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/nmi_vec[9] i:/WORK/quasar_wrapper/io_nmi_vec[8]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/rst_l i:/WORK/quasar_wrapper/reset
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/rst_vec[10] i:/WORK/quasar_wrapper/io_rst_vec[9]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/rst_vec[11] i:/WORK/quasar_wrapper/io_rst_vec[10]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/rst_vec[12] i:/WORK/quasar_wrapper/io_rst_vec[11]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/rst_vec[13] i:/WORK/quasar_wrapper/io_rst_vec[12]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/rst_vec[14] i:/WORK/quasar_wrapper/io_rst_vec[13]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/rst_vec[15] i:/WORK/quasar_wrapper/io_rst_vec[14]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/rst_vec[16] i:/WORK/quasar_wrapper/io_rst_vec[15]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/rst_vec[17] i:/WORK/quasar_wrapper/io_rst_vec[16]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/rst_vec[18] i:/WORK/quasar_wrapper/io_rst_vec[17]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/rst_vec[19] i:/WORK/quasar_wrapper/io_rst_vec[18]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/rst_vec[1] i:/WORK/quasar_wrapper/io_rst_vec[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/rst_vec[20] i:/WORK/quasar_wrapper/io_rst_vec[19]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/rst_vec[21] i:/WORK/quasar_wrapper/io_rst_vec[20]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/rst_vec[22] i:/WORK/quasar_wrapper/io_rst_vec[21]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/rst_vec[23] i:/WORK/quasar_wrapper/io_rst_vec[22]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/rst_vec[24] i:/WORK/quasar_wrapper/io_rst_vec[23]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/rst_vec[25] i:/WORK/quasar_wrapper/io_rst_vec[24]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/rst_vec[26] i:/WORK/quasar_wrapper/io_rst_vec[25]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/rst_vec[27] i:/WORK/quasar_wrapper/io_rst_vec[26]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/rst_vec[28] i:/WORK/quasar_wrapper/io_rst_vec[27]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/rst_vec[29] i:/WORK/quasar_wrapper/io_rst_vec[28]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/rst_vec[2] i:/WORK/quasar_wrapper/io_rst_vec[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/rst_vec[30] i:/WORK/quasar_wrapper/io_rst_vec[29]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/rst_vec[31] i:/WORK/quasar_wrapper/io_rst_vec[30]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/rst_vec[3] i:/WORK/quasar_wrapper/io_rst_vec[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/rst_vec[4] i:/WORK/quasar_wrapper/io_rst_vec[3]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/rst_vec[5] i:/WORK/quasar_wrapper/io_rst_vec[4]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/rst_vec[6] i:/WORK/quasar_wrapper/io_rst_vec[5]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/rst_vec[7] i:/WORK/quasar_wrapper/io_rst_vec[6]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/rst_vec[8] i:/WORK/quasar_wrapper/io_rst_vec[7]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/rst_vec[9] i:/WORK/quasar_wrapper/io_rst_vec[8]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_arready i:/WORK/quasar_wrapper/io_sb_brg_ar_ready
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_awready i:/WORK/quasar_wrapper/io_sb_brg_aw_ready
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_bresp[0] i:/WORK/quasar_wrapper/io_sb_brg_b_bits_resp[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_bresp[1] i:/WORK/quasar_wrapper/io_sb_brg_b_bits_resp[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_bvalid i:/WORK/quasar_wrapper/io_sb_brg_b_valid
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_rdata[0] i:/WORK/quasar_wrapper/io_sb_brg_r_bits_data[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_rdata[10] i:/WORK/quasar_wrapper/io_sb_brg_r_bits_data[10]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_rdata[11] i:/WORK/quasar_wrapper/io_sb_brg_r_bits_data[11]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_rdata[12] i:/WORK/quasar_wrapper/io_sb_brg_r_bits_data[12]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_rdata[13] i:/WORK/quasar_wrapper/io_sb_brg_r_bits_data[13]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_rdata[14] i:/WORK/quasar_wrapper/io_sb_brg_r_bits_data[14]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_rdata[15] i:/WORK/quasar_wrapper/io_sb_brg_r_bits_data[15]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_rdata[16] i:/WORK/quasar_wrapper/io_sb_brg_r_bits_data[16]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_rdata[17] i:/WORK/quasar_wrapper/io_sb_brg_r_bits_data[17]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_rdata[18] i:/WORK/quasar_wrapper/io_sb_brg_r_bits_data[18]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_rdata[19] i:/WORK/quasar_wrapper/io_sb_brg_r_bits_data[19]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_rdata[1] i:/WORK/quasar_wrapper/io_sb_brg_r_bits_data[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_rdata[20] i:/WORK/quasar_wrapper/io_sb_brg_r_bits_data[20]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_rdata[21] i:/WORK/quasar_wrapper/io_sb_brg_r_bits_data[21]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_rdata[22] i:/WORK/quasar_wrapper/io_sb_brg_r_bits_data[22]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_rdata[23] i:/WORK/quasar_wrapper/io_sb_brg_r_bits_data[23]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_rdata[24] i:/WORK/quasar_wrapper/io_sb_brg_r_bits_data[24]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_rdata[25] i:/WORK/quasar_wrapper/io_sb_brg_r_bits_data[25]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_rdata[26] i:/WORK/quasar_wrapper/io_sb_brg_r_bits_data[26]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_rdata[27] i:/WORK/quasar_wrapper/io_sb_brg_r_bits_data[27]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_rdata[28] i:/WORK/quasar_wrapper/io_sb_brg_r_bits_data[28]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_rdata[29] i:/WORK/quasar_wrapper/io_sb_brg_r_bits_data[29]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_rdata[2] i:/WORK/quasar_wrapper/io_sb_brg_r_bits_data[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_rdata[30] i:/WORK/quasar_wrapper/io_sb_brg_r_bits_data[30]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_rdata[31] i:/WORK/quasar_wrapper/io_sb_brg_r_bits_data[31]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_rdata[32] i:/WORK/quasar_wrapper/io_sb_brg_r_bits_data[32]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_rdata[33] i:/WORK/quasar_wrapper/io_sb_brg_r_bits_data[33]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_rdata[34] i:/WORK/quasar_wrapper/io_sb_brg_r_bits_data[34]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_rdata[35] i:/WORK/quasar_wrapper/io_sb_brg_r_bits_data[35]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_rdata[36] i:/WORK/quasar_wrapper/io_sb_brg_r_bits_data[36]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_rdata[37] i:/WORK/quasar_wrapper/io_sb_brg_r_bits_data[37]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_rdata[38] i:/WORK/quasar_wrapper/io_sb_brg_r_bits_data[38]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_rdata[39] i:/WORK/quasar_wrapper/io_sb_brg_r_bits_data[39]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_rdata[3] i:/WORK/quasar_wrapper/io_sb_brg_r_bits_data[3]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_rdata[40] i:/WORK/quasar_wrapper/io_sb_brg_r_bits_data[40]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_rdata[41] i:/WORK/quasar_wrapper/io_sb_brg_r_bits_data[41]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_rdata[42] i:/WORK/quasar_wrapper/io_sb_brg_r_bits_data[42]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_rdata[43] i:/WORK/quasar_wrapper/io_sb_brg_r_bits_data[43]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_rdata[44] i:/WORK/quasar_wrapper/io_sb_brg_r_bits_data[44]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_rdata[45] i:/WORK/quasar_wrapper/io_sb_brg_r_bits_data[45]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_rdata[46] i:/WORK/quasar_wrapper/io_sb_brg_r_bits_data[46]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_rdata[47] i:/WORK/quasar_wrapper/io_sb_brg_r_bits_data[47]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_rdata[48] i:/WORK/quasar_wrapper/io_sb_brg_r_bits_data[48]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_rdata[49] i:/WORK/quasar_wrapper/io_sb_brg_r_bits_data[49]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_rdata[4] i:/WORK/quasar_wrapper/io_sb_brg_r_bits_data[4]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_rdata[50] i:/WORK/quasar_wrapper/io_sb_brg_r_bits_data[50]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_rdata[51] i:/WORK/quasar_wrapper/io_sb_brg_r_bits_data[51]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_rdata[52] i:/WORK/quasar_wrapper/io_sb_brg_r_bits_data[52]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_rdata[53] i:/WORK/quasar_wrapper/io_sb_brg_r_bits_data[53]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_rdata[54] i:/WORK/quasar_wrapper/io_sb_brg_r_bits_data[54]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_rdata[55] i:/WORK/quasar_wrapper/io_sb_brg_r_bits_data[55]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_rdata[56] i:/WORK/quasar_wrapper/io_sb_brg_r_bits_data[56]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_rdata[57] i:/WORK/quasar_wrapper/io_sb_brg_r_bits_data[57]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_rdata[58] i:/WORK/quasar_wrapper/io_sb_brg_r_bits_data[58]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_rdata[59] i:/WORK/quasar_wrapper/io_sb_brg_r_bits_data[59]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_rdata[5] i:/WORK/quasar_wrapper/io_sb_brg_r_bits_data[5]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_rdata[60] i:/WORK/quasar_wrapper/io_sb_brg_r_bits_data[60]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_rdata[61] i:/WORK/quasar_wrapper/io_sb_brg_r_bits_data[61]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_rdata[62] i:/WORK/quasar_wrapper/io_sb_brg_r_bits_data[62]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_rdata[63] i:/WORK/quasar_wrapper/io_sb_brg_r_bits_data[63]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_rdata[6] i:/WORK/quasar_wrapper/io_sb_brg_r_bits_data[6]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_rdata[7] i:/WORK/quasar_wrapper/io_sb_brg_r_bits_data[7]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_rdata[8] i:/WORK/quasar_wrapper/io_sb_brg_r_bits_data[8]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_rdata[9] i:/WORK/quasar_wrapper/io_sb_brg_r_bits_data[9]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_rresp[0] i:/WORK/quasar_wrapper/io_sb_brg_r_bits_resp[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_rresp[1] i:/WORK/quasar_wrapper/io_sb_brg_r_bits_resp[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_rvalid i:/WORK/quasar_wrapper/io_sb_brg_r_valid
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_wready i:/WORK/quasar_wrapper/io_sb_brg_w_ready
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/scan_mode i:/WORK/quasar_wrapper/io_scan_mode
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/soft_int i:/WORK/quasar_wrapper/io_soft_int
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/timer_int i:/WORK/quasar_wrapper/io_timer_int

123
verif/LEC/setup_files/LAT.fms
View File

@ -1,123 +0,0 @@
set_user_match r:/WORK/el2_swerv_wrapper/swerv/dec/decode/csr_rddata_x_ff/genblock.genblock.clkhdr/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/dec/decode/rvclkhdr_1/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/dec/decode/csr_rddata_x_ff/genblock.genblock.clkhdr/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/dec/decode/rvclkhdr_2/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/dec/decode/trap_r_ff/genblock.genblock.clkhdr/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/dec/decode/rvclkhdr_6/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/dec/decode/trap_xff/genblock.genblock.clkhdr/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/dec/decode/rvclkhdr_5/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/dec/tlu/int_timers/mitb0_ff/genblock.genblock.clkhdr/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/dec/tlu/int_timers/rvclkhdr_2/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/dec/tlu/int_timers/mitb1_ff/genblock.genblock.clkhdr/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/dec/tlu/int_timers/rvclkhdr_3/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/dec/tlu/int_timers/mitcnt0_ff/genblock.genblock.clkhdr/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/dec/tlu/int_timers/rvclkhdr/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/dec/tlu/int_timers/mitcnt1_ff/genblock.genblock.clkhdr/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/dec/tlu/int_timers/rvclkhdr_1/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/dec/tlu/mhpmc3_ff/genblock.genblock.clkhdr/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/dec/tlu/csr/rvclkhdr_26/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/dec/tlu/mhpmc3h_ff/genblock.genblock.clkhdr/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/dec/tlu/csr/rvclkhdr_27/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/dec/tlu/mhpmc4_ff/genblock.genblock.clkhdr/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/dec/tlu/csr/rvclkhdr_28/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/dec/tlu/mhpmc4h_ff/genblock.genblock.clkhdr/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/dec/tlu/csr/rvclkhdr_29/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/dec/tlu/mhpmc5_ff/genblock.genblock.clkhdr/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/dec/tlu/csr/rvclkhdr_30/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/dec/tlu/mhpmc5h_ff/genblock.genblock.clkhdr/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/dec/tlu/csr/rvclkhdr_31/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/dec/tlu/mhpmc6h_ff/genblock.genblock.clkhdr/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/dec/tlu/csr/rvclkhdr_33/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/dec/tlu/mscratch_ff/genblock.genblock.clkhdr/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/dec/tlu/csr/rvclkhdr_5/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/dec/tlu/mtdata2_t0_ff/genblock.genblock.clkhdr/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/dec/tlu/csr/rvclkhdr_22/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/dec/tlu/mtdata2_t1_ff/genblock.genblock.clkhdr/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/dec/tlu/csr/rvclkhdr_23/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/dec/tlu/mtdata2_t2_ff/genblock.genblock.clkhdr/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/dec/tlu/csr/rvclkhdr_24/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/dec/tlu/mtdata2_t3_ff/genblock.genblock.clkhdr/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/dec/tlu/csr/rvclkhdr_25/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/aln/brdata0ff/genblock.genblock.clkhdr/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/aln_ctl/rvclkhdr_5/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/aln/brdata1ff/genblock.genblock.clkhdr/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/aln_ctl/rvclkhdr_4/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/aln/brdata2ff/genblock.genblock.clkhdr/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/aln_ctl/rvclkhdr_3/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/aln/f0pcff/genblock.genblock.clkhdr/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/aln_ctl/rvclkhdr_2/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/aln/f1pcff/genblock.genblock.clkhdr/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/aln_ctl/rvclkhdr_1/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/aln/f2pcff/genblock.genblock.clkhdr/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/aln_ctl/rvclkhdr/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/aln/misc0ff/genblock.genblock.clkhdr/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/aln_ctl/rvclkhdr_8/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/aln/misc1ff/genblock.genblock.clkhdr/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/aln_ctl/rvclkhdr_7/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/aln/misc2ff/genblock.genblock.clkhdr/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/aln_ctl/rvclkhdr_6/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/aln/q0ff/genblock.genblock.clkhdr/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/aln_ctl/rvclkhdr_11/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/aln/q1ff/genblock.genblock.clkhdr/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/aln_ctl/rvclkhdr_10/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/aln/q2ff/genblock.genblock.clkhdr/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/aln_ctl/rvclkhdr_9/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/bp/BANKS[0].BHT_CLK_GROUP[0].bht_bank_grp_cgc/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/bp_ctl/rvclkhdr_522/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/bp/BANKS[0].BHT_CLK_GROUP[10].bht_bank_grp_cgc/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/bp_ctl/rvclkhdr_532/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/bp/BANKS[0].BHT_CLK_GROUP[11].bht_bank_grp_cgc/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/bp_ctl/rvclkhdr_533/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/bp/BANKS[0].BHT_CLK_GROUP[12].bht_bank_grp_cgc/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/bp_ctl/rvclkhdr_534/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/bp/BANKS[0].BHT_CLK_GROUP[13].bht_bank_grp_cgc/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/bp_ctl/rvclkhdr_535/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/bp/BANKS[0].BHT_CLK_GROUP[14].bht_bank_grp_cgc/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/bp_ctl/rvclkhdr_536/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/bp/BANKS[0].BHT_CLK_GROUP[15].bht_bank_grp_cgc/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/bp_ctl/rvclkhdr_537/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/bp/BANKS[0].BHT_CLK_GROUP[1].bht_bank_grp_cgc/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/bp_ctl/rvclkhdr_523/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/bp/BANKS[0].BHT_CLK_GROUP[2].bht_bank_grp_cgc/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/bp_ctl/rvclkhdr_524/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/bp/BANKS[0].BHT_CLK_GROUP[3].bht_bank_grp_cgc/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/bp_ctl/rvclkhdr_525/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/bp/BANKS[0].BHT_CLK_GROUP[4].bht_bank_grp_cgc/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/bp_ctl/rvclkhdr_526/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/bp/BANKS[0].BHT_CLK_GROUP[5].bht_bank_grp_cgc/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/bp_ctl/rvclkhdr_527/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/bp/BANKS[0].BHT_CLK_GROUP[6].bht_bank_grp_cgc/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/bp_ctl/rvclkhdr_528/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/bp/BANKS[0].BHT_CLK_GROUP[7].bht_bank_grp_cgc/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/bp_ctl/rvclkhdr_529/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/bp/BANKS[0].BHT_CLK_GROUP[8].bht_bank_grp_cgc/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/bp_ctl/rvclkhdr_530/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/bp/BANKS[0].BHT_CLK_GROUP[9].bht_bank_grp_cgc/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/bp_ctl/rvclkhdr_531/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/bp/BANKS[1].BHT_CLK_GROUP[0].bht_bank_grp_cgc/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/bp_ctl/rvclkhdr_538/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/bp/BANKS[1].BHT_CLK_GROUP[10].bht_bank_grp_cgc/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/bp_ctl/rvclkhdr_548/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/bp/BANKS[1].BHT_CLK_GROUP[11].bht_bank_grp_cgc/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/bp_ctl/rvclkhdr_549/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/bp/BANKS[1].BHT_CLK_GROUP[12].bht_bank_grp_cgc/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/bp_ctl/rvclkhdr_550/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/bp/BANKS[1].BHT_CLK_GROUP[13].bht_bank_grp_cgc/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/bp_ctl/rvclkhdr_551/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/bp/BANKS[1].BHT_CLK_GROUP[14].bht_bank_grp_cgc/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/bp_ctl/rvclkhdr_552/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/bp/BANKS[1].BHT_CLK_GROUP[15].bht_bank_grp_cgc/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/bp_ctl/rvclkhdr_553/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/bp/faddrf_ff/genblock.genblock.clkhdr/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/bp_ctl/rvclkhdr_1/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/bp/retstack[0].rets_ff/genblock.genblock.clkhdr/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/bp_ctl/rvclkhdr_2/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/bp/retstack[1].rets_ff/genblock.genblock.clkhdr/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/bp_ctl/rvclkhdr_3/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/bp/retstack[2].rets_ff/genblock.genblock.clkhdr/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/bp_ctl/rvclkhdr_4/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/bp/retstack[3].rets_ff/genblock.genblock.clkhdr/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/bp_ctl/rvclkhdr_5/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/bp/retstack[4].rets_ff/genblock.genblock.clkhdr/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/bp_ctl/rvclkhdr_6/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/bp/retstack[5].rets_ff/genblock.genblock.clkhdr/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/bp_ctl/rvclkhdr_7/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/bp/retstack[6].rets_ff/genblock.genblock.clkhdr/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/bp_ctl/rvclkhdr_8/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/bp/retstack[7].rets_ff/genblock.genblock.clkhdr/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/bp_ctl/rvclkhdr_9/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/exu/i_mul/i_a_x_ff/genblock.genblock.clkhdr/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/exu/i_mul/rvclkhdr/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/exu/i_mul/i_a_x_ff/genblock.genblock.clkhdr/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/exu/i_mul/rvclkhdr_1/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/exu/i_r_ff0/genblock.genblock.clkhdr/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/exu/rvclkhdr_10/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/exu/i_r_ff0/genblock.genblock.clkhdr/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/exu/rvclkhdr_11/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/exu/i_r_ff0/genblock.genblock.clkhdr/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/exu/rvclkhdr_12/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/exu/i_r_ff1/genblock.genblock.clkhdr/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/exu/rvclkhdr_13/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/exu/i_r_ff1/genblock.genblock.clkhdr/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/exu/rvclkhdr_14/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/exu/i_x_ff/genblock.genblock.clkhdr/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/exu/rvclkhdr_5/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/exu/i_x_ff/genblock.genblock.clkhdr/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/exu/rvclkhdr_6/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/exu/i_x_ff/genblock.genblock.clkhdr/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/exu/rvclkhdr_7/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/exu/i_x_ff/genblock.genblock.clkhdr/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/exu/rvclkhdr_8/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/exu/i_x_ff/genblock.genblock.clkhdr/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/exu/rvclkhdr_9/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/exu/genblk1.i_data_gate_ff/genblock.genblock.clkhdr/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/exu/rvclkhdr_15/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/exu/genblk1.i_data_gate_ff/genblock.genblock.clkhdr/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/exu/rvclkhdr_16/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/exu/genblk1.i_data_gate_ff/genblock.genblock.clkhdr/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/exu/rvclkhdr_17/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/bp/BANKS[1].BHT_CLK_GROUP[9].bht_bank_grp_cgc/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/bp_ctl/rvclkhdr_547/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/bp/BANKS[1].BHT_CLK_GROUP[8].bht_bank_grp_cgc/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/bp_ctl/rvclkhdr_546/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/bp/BANKS[1].BHT_CLK_GROUP[7].bht_bank_grp_cgc/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/bp_ctl/rvclkhdr_545/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/bp/BANKS[1].BHT_CLK_GROUP[6].bht_bank_grp_cgc/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/bp_ctl/rvclkhdr_544/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/bp/BANKS[1].BHT_CLK_GROUP[5].bht_bank_grp_cgc/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/bp_ctl/rvclkhdr_543/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/bp/BANKS[1].BHT_CLK_GROUP[4].bht_bank_grp_cgc/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/bp_ctl/rvclkhdr_542/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/bp/BANKS[1].BHT_CLK_GROUP[3].bht_bank_grp_cgc/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/bp_ctl/rvclkhdr_541/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/bp/BANKS[1].BHT_CLK_GROUP[2].bht_bank_grp_cgc/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/bp_ctl/rvclkhdr_540/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/bp/BANKS[1].BHT_CLK_GROUP[1].bht_bank_grp_cgc/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/bp_ctl/rvclkhdr_539/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/bp/btb_lru_ff/genblock.genblock.clkhdr/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/bp_ctl/rvclkhdr/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/mem_ctl/icache_enabled.CLK_GRP_WAY_STATUS[9].way_status_cgc/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/mem_ctl/rvclkhdr_79/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/mem_ctl/icache_enabled.CLK_GRP_WAY_STATUS[8].way_status_cgc/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/mem_ctl/rvclkhdr_78/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/mem_ctl/icache_enabled.CLK_GRP_WAY_STATUS[7].way_status_cgc/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/mem_ctl/rvclkhdr_77/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/mem_ctl/icache_enabled.CLK_GRP_WAY_STATUS[6].way_status_cgc/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/mem_ctl/rvclkhdr_76/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/mem_ctl/icache_enabled.CLK_GRP_WAY_STATUS[5].way_status_cgc/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/mem_ctl/rvclkhdr_75/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/mem_ctl/icache_enabled.CLK_GRP_WAY_STATUS[4].way_status_cgc/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/mem_ctl/rvclkhdr_74/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/mem_ctl/icache_enabled.CLK_GRP_WAY_STATUS[3].way_status_cgc/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/mem_ctl/rvclkhdr_73/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/mem_ctl/icache_enabled.CLK_GRP_WAY_STATUS[2].way_status_cgc/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/mem_ctl/rvclkhdr_72/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/mem_ctl/icache_enabled.CLK_GRP_WAY_STATUS[1].way_status_cgc/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/mem_ctl/rvclkhdr_71/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/mem_ctl/icache_enabled.CLK_GRP_WAY_STATUS[15].way_status_cgc/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/mem_ctl/rvclkhdr_85/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/mem_ctl/icache_enabled.CLK_GRP_WAY_STATUS[14].way_status_cgc/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/mem_ctl/rvclkhdr_84/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/mem_ctl/icache_enabled.CLK_GRP_WAY_STATUS[13].way_status_cgc/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/mem_ctl/rvclkhdr_83/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/mem_ctl/icache_enabled.CLK_GRP_WAY_STATUS[12].way_status_cgc/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/mem_ctl/rvclkhdr_82/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/mem_ctl/icache_enabled.CLK_GRP_WAY_STATUS[11].way_status_cgc/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/mem_ctl/rvclkhdr_81/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/mem_ctl/icache_enabled.CLK_GRP_WAY_STATUS[10].way_status_cgc/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/mem_ctl/rvclkhdr_80/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/mem_ctl/icache_enabled.CLK_GRP_TAG_VALID[3].way_clken[1].way_status_cgc/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/mem_ctl/rvclkhdr_93/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/mem_ctl/icache_enabled.CLK_GRP_TAG_VALID[3].way_clken[0].way_status_cgc/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/mem_ctl/rvclkhdr_92/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/mem_ctl/icache_enabled.CLK_GRP_TAG_VALID[2].way_clken[1].way_status_cgc/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/mem_ctl/rvclkhdr_91/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/mem_ctl/icache_enabled.CLK_GRP_TAG_VALID[2].way_clken[0].way_status_cgc/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/mem_ctl/rvclkhdr_90/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/mem_ctl/icache_enabled.CLK_GRP_TAG_VALID[1].way_clken[1].way_status_cgc/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/mem_ctl/rvclkhdr_89/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/mem_ctl/icache_enabled.CLK_GRP_TAG_VALID[1].way_clken[0].way_status_cgc/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/mem_ctl/rvclkhdr_88/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/mem_ctl/icache_enabled.CLK_GRP_TAG_VALID[0].way_clken[1].way_status_cgc/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/mem_ctl/rvclkhdr_87/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/mem_ctl/bus_clk/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/mem_ctl/rvclkhdr_69/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/ifc/faddrf1_ff/genblock.genblock.clkhdr/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/ifc_ctl/rvclkhdr/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/mem_ctl/debug_c1_cgc/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/mem_ctl/rvclkhdr_1/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/mem_ctl/fetch_bf_f_c1_cgc/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/mem_ctl/rvclkhdr_2/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/ifu/mem_ctl/icache_enabled.CLK_GRP_TAG_VALID[0].way_clken[0].way_status_cgc/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/ifu/mem_ctl/rvclkhdr_86/clkhdr/en_ff_reg
set_user_match r:/WORK/el2_swerv_wrapper/swerv/lsu/stbuf/GenStBuf[1].stbuf_addrff/genblock.genblock.clkhdr/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/lsu/stbuf/rvclkhdr_2/clkhdr/en_ff_reg -type cell
set_user_match r:/WORK/el2_swerv_wrapper/swerv/lsu/stbuf/GenStBuf[1].stbuf_dataff/genblock.genblock.clkhdr/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/lsu/stbuf/rvclkhdr_3/clkhdr/en_ff_reg -type cell
set_user_match r:/WORK/el2_swerv_wrapper/swerv/lsu/stbuf/GenStBuf[2].stbuf_addrff/genblock.genblock.clkhdr/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/lsu/stbuf/rvclkhdr_4/clkhdr/en_ff_reg -type cell
set_user_match r:/WORK/el2_swerv_wrapper/swerv/lsu/stbuf/GenStBuf[2].stbuf_dataff/genblock.genblock.clkhdr/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/lsu/stbuf/rvclkhdr_5/clkhdr/en_ff_reg -type cell
set_user_match r:/WORK/el2_swerv_wrapper/swerv/lsu/stbuf/GenStBuf[3].stbuf_addrff/genblock.genblock.clkhdr/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/lsu/stbuf/rvclkhdr_6/clkhdr/en_ff_reg -type cell
set_user_match r:/WORK/el2_swerv_wrapper/swerv/lsu/stbuf/GenStBuf[3].stbuf_dataff/genblock.genblock.clkhdr/clkhdr/en_ff_reg i:/WORK/quasar_wrapper/core/lsu/stbuf/rvclkhdr_7/clkhdr/en_ff_reg -type cell

806
verif/LEC/setup_files/Output_ports_1.3.fms Normal file
View File

@ -0,0 +1,806 @@
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/debug_brkpt_status i:/WORK/quasar_wrapper/io_debug_brkpt_status
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dec_tlu_perfcnt0 i:/WORK/quasar_wrapper/io_dec_tlu_perfcnt0
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dec_tlu_perfcnt1 i:/WORK/quasar_wrapper/io_dec_tlu_perfcnt1
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dec_tlu_perfcnt2 i:/WORK/quasar_wrapper/io_dec_tlu_perfcnt2
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dec_tlu_perfcnt3 i:/WORK/quasar_wrapper/io_dec_tlu_perfcnt3
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_arready i:/WORK/quasar_wrapper/io_dma_brg_ar_ready
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_awready i:/WORK/quasar_wrapper/io_dma_brg_aw_ready
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_bid[0] i:/WORK/quasar_wrapper/io_dma_brg_b_bits_id
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_bresp[0] i:/WORK/quasar_wrapper/io_dma_brg_b_bits_resp[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_bresp[1] i:/WORK/quasar_wrapper/io_dma_brg_b_bits_resp[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_bvalid i:/WORK/quasar_wrapper/io_dma_brg_b_valid
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_rdata[0] i:/WORK/quasar_wrapper/io_dma_brg_r_bits_data[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_rdata[10] i:/WORK/quasar_wrapper/io_dma_brg_r_bits_data[10]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_rdata[11] i:/WORK/quasar_wrapper/io_dma_brg_r_bits_data[11]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_rdata[12] i:/WORK/quasar_wrapper/io_dma_brg_r_bits_data[12]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_rdata[13] i:/WORK/quasar_wrapper/io_dma_brg_r_bits_data[13]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_rdata[14] i:/WORK/quasar_wrapper/io_dma_brg_r_bits_data[14]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_rdata[15] i:/WORK/quasar_wrapper/io_dma_brg_r_bits_data[15]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_rdata[16] i:/WORK/quasar_wrapper/io_dma_brg_r_bits_data[16]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_rdata[17] i:/WORK/quasar_wrapper/io_dma_brg_r_bits_data[17]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_rdata[18] i:/WORK/quasar_wrapper/io_dma_brg_r_bits_data[18]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_rdata[19] i:/WORK/quasar_wrapper/io_dma_brg_r_bits_data[19]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_rdata[1] i:/WORK/quasar_wrapper/io_dma_brg_r_bits_data[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_rdata[20] i:/WORK/quasar_wrapper/io_dma_brg_r_bits_data[20]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_rdata[21] i:/WORK/quasar_wrapper/io_dma_brg_r_bits_data[21]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_rdata[22] i:/WORK/quasar_wrapper/io_dma_brg_r_bits_data[22]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_rdata[23] i:/WORK/quasar_wrapper/io_dma_brg_r_bits_data[23]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_rdata[24] i:/WORK/quasar_wrapper/io_dma_brg_r_bits_data[24]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_rdata[25] i:/WORK/quasar_wrapper/io_dma_brg_r_bits_data[25]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_rdata[26] i:/WORK/quasar_wrapper/io_dma_brg_r_bits_data[26]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_rdata[27] i:/WORK/quasar_wrapper/io_dma_brg_r_bits_data[27]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_rdata[28] i:/WORK/quasar_wrapper/io_dma_brg_r_bits_data[28]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_rdata[29] i:/WORK/quasar_wrapper/io_dma_brg_r_bits_data[29]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_rdata[2] i:/WORK/quasar_wrapper/io_dma_brg_r_bits_data[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_rdata[30] i:/WORK/quasar_wrapper/io_dma_brg_r_bits_data[30]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_rdata[31] i:/WORK/quasar_wrapper/io_dma_brg_r_bits_data[31]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_rdata[32] i:/WORK/quasar_wrapper/io_dma_brg_r_bits_data[32]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_rdata[33] i:/WORK/quasar_wrapper/io_dma_brg_r_bits_data[33]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_rdata[34] i:/WORK/quasar_wrapper/io_dma_brg_r_bits_data[34]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_rdata[35] i:/WORK/quasar_wrapper/io_dma_brg_r_bits_data[35]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_rdata[36] i:/WORK/quasar_wrapper/io_dma_brg_r_bits_data[36]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_rdata[37] i:/WORK/quasar_wrapper/io_dma_brg_r_bits_data[37]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_rdata[38] i:/WORK/quasar_wrapper/io_dma_brg_r_bits_data[38]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_rdata[39] i:/WORK/quasar_wrapper/io_dma_brg_r_bits_data[39]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_rdata[3] i:/WORK/quasar_wrapper/io_dma_brg_r_bits_data[3]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_rdata[40] i:/WORK/quasar_wrapper/io_dma_brg_r_bits_data[40]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_rdata[41] i:/WORK/quasar_wrapper/io_dma_brg_r_bits_data[41]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_rdata[42] i:/WORK/quasar_wrapper/io_dma_brg_r_bits_data[42]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_rdata[43] i:/WORK/quasar_wrapper/io_dma_brg_r_bits_data[43]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_rdata[44] i:/WORK/quasar_wrapper/io_dma_brg_r_bits_data[44]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_rdata[45] i:/WORK/quasar_wrapper/io_dma_brg_r_bits_data[45]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_rdata[46] i:/WORK/quasar_wrapper/io_dma_brg_r_bits_data[46]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_rdata[47] i:/WORK/quasar_wrapper/io_dma_brg_r_bits_data[47]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_rdata[48] i:/WORK/quasar_wrapper/io_dma_brg_r_bits_data[48]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_rdata[49] i:/WORK/quasar_wrapper/io_dma_brg_r_bits_data[49]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_rdata[4] i:/WORK/quasar_wrapper/io_dma_brg_r_bits_data[4]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_rdata[50] i:/WORK/quasar_wrapper/io_dma_brg_r_bits_data[50]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_rdata[51] i:/WORK/quasar_wrapper/io_dma_brg_r_bits_data[51]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_rdata[52] i:/WORK/quasar_wrapper/io_dma_brg_r_bits_data[52]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_rdata[53] i:/WORK/quasar_wrapper/io_dma_brg_r_bits_data[53]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_rdata[54] i:/WORK/quasar_wrapper/io_dma_brg_r_bits_data[54]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_rdata[55] i:/WORK/quasar_wrapper/io_dma_brg_r_bits_data[55]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_rdata[56] i:/WORK/quasar_wrapper/io_dma_brg_r_bits_data[56]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_rdata[57] i:/WORK/quasar_wrapper/io_dma_brg_r_bits_data[57]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_rdata[58] i:/WORK/quasar_wrapper/io_dma_brg_r_bits_data[58]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_rdata[59] i:/WORK/quasar_wrapper/io_dma_brg_r_bits_data[59]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_rdata[5] i:/WORK/quasar_wrapper/io_dma_brg_r_bits_data[5]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_rdata[60] i:/WORK/quasar_wrapper/io_dma_brg_r_bits_data[60]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_rdata[61] i:/WORK/quasar_wrapper/io_dma_brg_r_bits_data[61]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_rdata[62] i:/WORK/quasar_wrapper/io_dma_brg_r_bits_data[62]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_rdata[63] i:/WORK/quasar_wrapper/io_dma_brg_r_bits_data[63]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_rdata[6] i:/WORK/quasar_wrapper/io_dma_brg_r_bits_data[6]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_rdata[7] i:/WORK/quasar_wrapper/io_dma_brg_r_bits_data[7]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_rdata[8] i:/WORK/quasar_wrapper/io_dma_brg_r_bits_data[8]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_rdata[9] i:/WORK/quasar_wrapper/io_dma_brg_r_bits_data[9]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_rid[0] i:/WORK/quasar_wrapper/io_dma_brg_r_bits_id
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_rlast i:/WORK/quasar_wrapper/io_dma_brg_r_bits_last
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_rresp[0] i:/WORK/quasar_wrapper/io_dma_brg_r_bits_resp[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_rresp[1] i:/WORK/quasar_wrapper/io_dma_brg_r_bits_resp[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_rvalid i:/WORK/quasar_wrapper/io_dma_brg_r_valid
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/dma_axi_wready i:/WORK/quasar_wrapper/io_dma_brg_w_ready
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_araddr[0] i:/WORK/quasar_wrapper/io_ifu_brg_ar_bits_addr[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_araddr[10] i:/WORK/quasar_wrapper/io_ifu_brg_ar_bits_addr[10]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_araddr[11] i:/WORK/quasar_wrapper/io_ifu_brg_ar_bits_addr[11]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_araddr[12] i:/WORK/quasar_wrapper/io_ifu_brg_ar_bits_addr[12]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_araddr[13] i:/WORK/quasar_wrapper/io_ifu_brg_ar_bits_addr[13]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_araddr[14] i:/WORK/quasar_wrapper/io_ifu_brg_ar_bits_addr[14]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_araddr[15] i:/WORK/quasar_wrapper/io_ifu_brg_ar_bits_addr[15]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_araddr[16] i:/WORK/quasar_wrapper/io_ifu_brg_ar_bits_addr[16]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_araddr[17] i:/WORK/quasar_wrapper/io_ifu_brg_ar_bits_addr[17]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_araddr[18] i:/WORK/quasar_wrapper/io_ifu_brg_ar_bits_addr[18]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_araddr[19] i:/WORK/quasar_wrapper/io_ifu_brg_ar_bits_addr[19]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_araddr[1] i:/WORK/quasar_wrapper/io_ifu_brg_ar_bits_addr[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_araddr[20] i:/WORK/quasar_wrapper/io_ifu_brg_ar_bits_addr[20]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_araddr[21] i:/WORK/quasar_wrapper/io_ifu_brg_ar_bits_addr[21]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_araddr[22] i:/WORK/quasar_wrapper/io_ifu_brg_ar_bits_addr[22]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_araddr[23] i:/WORK/quasar_wrapper/io_ifu_brg_ar_bits_addr[23]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_araddr[24] i:/WORK/quasar_wrapper/io_ifu_brg_ar_bits_addr[24]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_araddr[25] i:/WORK/quasar_wrapper/io_ifu_brg_ar_bits_addr[25]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_araddr[26] i:/WORK/quasar_wrapper/io_ifu_brg_ar_bits_addr[26]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_araddr[27] i:/WORK/quasar_wrapper/io_ifu_brg_ar_bits_addr[27]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_araddr[28] i:/WORK/quasar_wrapper/io_ifu_brg_ar_bits_addr[28]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_araddr[29] i:/WORK/quasar_wrapper/io_ifu_brg_ar_bits_addr[29]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_araddr[2] i:/WORK/quasar_wrapper/io_ifu_brg_ar_bits_addr[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_araddr[30] i:/WORK/quasar_wrapper/io_ifu_brg_ar_bits_addr[30]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_araddr[31] i:/WORK/quasar_wrapper/io_ifu_brg_ar_bits_addr[31]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_araddr[3] i:/WORK/quasar_wrapper/io_ifu_brg_ar_bits_addr[3]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_araddr[4] i:/WORK/quasar_wrapper/io_ifu_brg_ar_bits_addr[4]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_araddr[5] i:/WORK/quasar_wrapper/io_ifu_brg_ar_bits_addr[5]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_araddr[6] i:/WORK/quasar_wrapper/io_ifu_brg_ar_bits_addr[6]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_araddr[7] i:/WORK/quasar_wrapper/io_ifu_brg_ar_bits_addr[7]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_araddr[8] i:/WORK/quasar_wrapper/io_ifu_brg_ar_bits_addr[8]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_araddr[9] i:/WORK/quasar_wrapper/io_ifu_brg_ar_bits_addr[9]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_arburst[0] i:/WORK/quasar_wrapper/io_ifu_brg_ar_bits_burst[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_arburst[1] i:/WORK/quasar_wrapper/io_ifu_brg_ar_bits_burst[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_arcache[0] i:/WORK/quasar_wrapper/io_ifu_brg_ar_bits_cache[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_arcache[1] i:/WORK/quasar_wrapper/io_ifu_brg_ar_bits_cache[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_arcache[2] i:/WORK/quasar_wrapper/io_ifu_brg_ar_bits_cache[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_arcache[3] i:/WORK/quasar_wrapper/io_ifu_brg_ar_bits_cache[3]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_arid[0] i:/WORK/quasar_wrapper/io_ifu_brg_ar_bits_id[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_arid[1] i:/WORK/quasar_wrapper/io_ifu_brg_ar_bits_id[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_arid[2] i:/WORK/quasar_wrapper/io_ifu_brg_ar_bits_id[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_arlen[0] i:/WORK/quasar_wrapper/io_ifu_brg_ar_bits_len[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_arlen[1] i:/WORK/quasar_wrapper/io_ifu_brg_ar_bits_len[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_arlen[2] i:/WORK/quasar_wrapper/io_ifu_brg_ar_bits_len[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_arlen[3] i:/WORK/quasar_wrapper/io_ifu_brg_ar_bits_len[3]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_arlen[4] i:/WORK/quasar_wrapper/io_ifu_brg_ar_bits_len[4]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_arlen[5] i:/WORK/quasar_wrapper/io_ifu_brg_ar_bits_len[5]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_arlen[6] i:/WORK/quasar_wrapper/io_ifu_brg_ar_bits_len[6]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_arlen[7] i:/WORK/quasar_wrapper/io_ifu_brg_ar_bits_len[7]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_arlock i:/WORK/quasar_wrapper/io_ifu_brg_ar_bits_lock
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_arprot[0] i:/WORK/quasar_wrapper/io_ifu_brg_ar_bits_prot[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_arprot[1] i:/WORK/quasar_wrapper/io_ifu_brg_ar_bits_prot[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_arprot[2] i:/WORK/quasar_wrapper/io_ifu_brg_ar_bits_prot[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_arqos[0] i:/WORK/quasar_wrapper/io_ifu_brg_ar_bits_qos[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_arqos[1] i:/WORK/quasar_wrapper/io_ifu_brg_ar_bits_qos[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_arqos[2] i:/WORK/quasar_wrapper/io_ifu_brg_ar_bits_qos[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_arqos[3] i:/WORK/quasar_wrapper/io_ifu_brg_ar_bits_qos[3]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_arregion[0] i:/WORK/quasar_wrapper/io_ifu_brg_ar_bits_region[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_arregion[1] i:/WORK/quasar_wrapper/io_ifu_brg_ar_bits_region[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_arregion[2] i:/WORK/quasar_wrapper/io_ifu_brg_ar_bits_region[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_arregion[3] i:/WORK/quasar_wrapper/io_ifu_brg_ar_bits_region[3]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_arsize[0] i:/WORK/quasar_wrapper/io_ifu_brg_ar_bits_size[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_arsize[1] i:/WORK/quasar_wrapper/io_ifu_brg_ar_bits_size[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_arsize[2] i:/WORK/quasar_wrapper/io_ifu_brg_ar_bits_size[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_arvalid i:/WORK/quasar_wrapper/io_ifu_brg_ar_valid
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_awaddr[0] i:/WORK/quasar_wrapper/io_ifu_brg_aw_bits_addr[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_awaddr[10] i:/WORK/quasar_wrapper/io_ifu_brg_aw_bits_addr[10]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_awaddr[11] i:/WORK/quasar_wrapper/io_ifu_brg_aw_bits_addr[11]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_awaddr[12] i:/WORK/quasar_wrapper/io_ifu_brg_aw_bits_addr[12]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_awaddr[13] i:/WORK/quasar_wrapper/io_ifu_brg_aw_bits_addr[13]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_awaddr[14] i:/WORK/quasar_wrapper/io_ifu_brg_aw_bits_addr[14]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_awaddr[15] i:/WORK/quasar_wrapper/io_ifu_brg_aw_bits_addr[15]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_awaddr[16] i:/WORK/quasar_wrapper/io_ifu_brg_aw_bits_addr[16]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_awaddr[17] i:/WORK/quasar_wrapper/io_ifu_brg_aw_bits_addr[17]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_awaddr[18] i:/WORK/quasar_wrapper/io_ifu_brg_aw_bits_addr[18]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_awaddr[19] i:/WORK/quasar_wrapper/io_ifu_brg_aw_bits_addr[19]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_awaddr[1] i:/WORK/quasar_wrapper/io_ifu_brg_aw_bits_addr[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_awaddr[20] i:/WORK/quasar_wrapper/io_ifu_brg_aw_bits_addr[20]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_awaddr[21] i:/WORK/quasar_wrapper/io_ifu_brg_aw_bits_addr[21]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_awaddr[22] i:/WORK/quasar_wrapper/io_ifu_brg_aw_bits_addr[22]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_awaddr[23] i:/WORK/quasar_wrapper/io_ifu_brg_aw_bits_addr[23]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_awaddr[24] i:/WORK/quasar_wrapper/io_ifu_brg_aw_bits_addr[24]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_awaddr[25] i:/WORK/quasar_wrapper/io_ifu_brg_aw_bits_addr[25]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_awaddr[26] i:/WORK/quasar_wrapper/io_ifu_brg_aw_bits_addr[26]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_awaddr[27] i:/WORK/quasar_wrapper/io_ifu_brg_aw_bits_addr[27]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_awaddr[28] i:/WORK/quasar_wrapper/io_ifu_brg_aw_bits_addr[28]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_awaddr[29] i:/WORK/quasar_wrapper/io_ifu_brg_aw_bits_addr[29]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_awaddr[2] i:/WORK/quasar_wrapper/io_ifu_brg_aw_bits_addr[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_awaddr[30] i:/WORK/quasar_wrapper/io_ifu_brg_aw_bits_addr[30]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_awaddr[31] i:/WORK/quasar_wrapper/io_ifu_brg_aw_bits_addr[31]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_awaddr[3] i:/WORK/quasar_wrapper/io_ifu_brg_aw_bits_addr[3]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_awaddr[4] i:/WORK/quasar_wrapper/io_ifu_brg_aw_bits_addr[4]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_awaddr[5] i:/WORK/quasar_wrapper/io_ifu_brg_aw_bits_addr[5]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_awaddr[6] i:/WORK/quasar_wrapper/io_ifu_brg_aw_bits_addr[6]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_awaddr[7] i:/WORK/quasar_wrapper/io_ifu_brg_aw_bits_addr[7]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_awaddr[8] i:/WORK/quasar_wrapper/io_ifu_brg_aw_bits_addr[8]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_awaddr[9] i:/WORK/quasar_wrapper/io_ifu_brg_aw_bits_addr[9]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_awburst[0] i:/WORK/quasar_wrapper/io_ifu_brg_aw_bits_burst[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_awburst[1] i:/WORK/quasar_wrapper/io_ifu_brg_aw_bits_burst[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_awcache[0] i:/WORK/quasar_wrapper/io_ifu_brg_aw_bits_cache[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_awcache[1] i:/WORK/quasar_wrapper/io_ifu_brg_aw_bits_cache[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_awcache[2] i:/WORK/quasar_wrapper/io_ifu_brg_aw_bits_cache[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_awcache[3] i:/WORK/quasar_wrapper/io_ifu_brg_aw_bits_cache[3]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_awid[0] i:/WORK/quasar_wrapper/io_ifu_brg_aw_bits_id[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_awid[1] i:/WORK/quasar_wrapper/io_ifu_brg_aw_bits_id[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_awid[2] i:/WORK/quasar_wrapper/io_ifu_brg_aw_bits_id[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_awlen[0] i:/WORK/quasar_wrapper/io_ifu_brg_aw_bits_len[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_awlen[1] i:/WORK/quasar_wrapper/io_ifu_brg_aw_bits_len[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_awlen[2] i:/WORK/quasar_wrapper/io_ifu_brg_aw_bits_len[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_awlen[3] i:/WORK/quasar_wrapper/io_ifu_brg_aw_bits_len[3]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_awlen[4] i:/WORK/quasar_wrapper/io_ifu_brg_aw_bits_len[4]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_awlen[5] i:/WORK/quasar_wrapper/io_ifu_brg_aw_bits_len[5]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_awlen[6] i:/WORK/quasar_wrapper/io_ifu_brg_aw_bits_len[6]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_awlen[7] i:/WORK/quasar_wrapper/io_ifu_brg_aw_bits_len[7]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_awlock i:/WORK/quasar_wrapper/io_ifu_brg_aw_bits_lock
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_awprot[0] i:/WORK/quasar_wrapper/io_ifu_brg_aw_bits_prot[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_awprot[1] i:/WORK/quasar_wrapper/io_ifu_brg_aw_bits_prot[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_awprot[2] i:/WORK/quasar_wrapper/io_ifu_brg_aw_bits_prot[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_awqos[0] i:/WORK/quasar_wrapper/io_ifu_brg_aw_bits_qos[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_awqos[1] i:/WORK/quasar_wrapper/io_ifu_brg_aw_bits_qos[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_awqos[2] i:/WORK/quasar_wrapper/io_ifu_brg_aw_bits_qos[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_awqos[3] i:/WORK/quasar_wrapper/io_ifu_brg_aw_bits_qos[3]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_awregion[0] i:/WORK/quasar_wrapper/io_ifu_brg_aw_bits_region[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_awregion[1] i:/WORK/quasar_wrapper/io_ifu_brg_aw_bits_region[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_awregion[2] i:/WORK/quasar_wrapper/io_ifu_brg_aw_bits_region[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_awregion[3] i:/WORK/quasar_wrapper/io_ifu_brg_aw_bits_region[3]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_awsize[0] i:/WORK/quasar_wrapper/io_ifu_brg_aw_bits_size[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_awsize[1] i:/WORK/quasar_wrapper/io_ifu_brg_aw_bits_size[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_awsize[2] i:/WORK/quasar_wrapper/io_ifu_brg_aw_bits_size[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_awvalid i:/WORK/quasar_wrapper/io_ifu_brg_aw_valid
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_bready i:/WORK/quasar_wrapper/io_ifu_brg_b_ready
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_rready i:/WORK/quasar_wrapper/io_ifu_brg_r_ready
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_wdata[0] i:/WORK/quasar_wrapper/io_ifu_brg_w_bits_data[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_wdata[10] i:/WORK/quasar_wrapper/io_ifu_brg_w_bits_data[10]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_wdata[11] i:/WORK/quasar_wrapper/io_ifu_brg_w_bits_data[11]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_wdata[12] i:/WORK/quasar_wrapper/io_ifu_brg_w_bits_data[12]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_wdata[13] i:/WORK/quasar_wrapper/io_ifu_brg_w_bits_data[13]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_wdata[14] i:/WORK/quasar_wrapper/io_ifu_brg_w_bits_data[14]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_wdata[15] i:/WORK/quasar_wrapper/io_ifu_brg_w_bits_data[15]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_wdata[16] i:/WORK/quasar_wrapper/io_ifu_brg_w_bits_data[16]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_wdata[17] i:/WORK/quasar_wrapper/io_ifu_brg_w_bits_data[17]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_wdata[18] i:/WORK/quasar_wrapper/io_ifu_brg_w_bits_data[18]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_wdata[19] i:/WORK/quasar_wrapper/io_ifu_brg_w_bits_data[19]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_wdata[1] i:/WORK/quasar_wrapper/io_ifu_brg_w_bits_data[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_wdata[20] i:/WORK/quasar_wrapper/io_ifu_brg_w_bits_data[20]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_wdata[21] i:/WORK/quasar_wrapper/io_ifu_brg_w_bits_data[21]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_wdata[22] i:/WORK/quasar_wrapper/io_ifu_brg_w_bits_data[22]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_wdata[23] i:/WORK/quasar_wrapper/io_ifu_brg_w_bits_data[23]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_wdata[24] i:/WORK/quasar_wrapper/io_ifu_brg_w_bits_data[24]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_wdata[25] i:/WORK/quasar_wrapper/io_ifu_brg_w_bits_data[25]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_wdata[26] i:/WORK/quasar_wrapper/io_ifu_brg_w_bits_data[26]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_wdata[27] i:/WORK/quasar_wrapper/io_ifu_brg_w_bits_data[27]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_wdata[28] i:/WORK/quasar_wrapper/io_ifu_brg_w_bits_data[28]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_wdata[29] i:/WORK/quasar_wrapper/io_ifu_brg_w_bits_data[29]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_wdata[2] i:/WORK/quasar_wrapper/io_ifu_brg_w_bits_data[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_wdata[30] i:/WORK/quasar_wrapper/io_ifu_brg_w_bits_data[30]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_wdata[31] i:/WORK/quasar_wrapper/io_ifu_brg_w_bits_data[31]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_wdata[32] i:/WORK/quasar_wrapper/io_ifu_brg_w_bits_data[32]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_wdata[33] i:/WORK/quasar_wrapper/io_ifu_brg_w_bits_data[33]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_wdata[34] i:/WORK/quasar_wrapper/io_ifu_brg_w_bits_data[34]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_wdata[35] i:/WORK/quasar_wrapper/io_ifu_brg_w_bits_data[35]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_wdata[36] i:/WORK/quasar_wrapper/io_ifu_brg_w_bits_data[36]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_wdata[37] i:/WORK/quasar_wrapper/io_ifu_brg_w_bits_data[37]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_wdata[38] i:/WORK/quasar_wrapper/io_ifu_brg_w_bits_data[38]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_wdata[39] i:/WORK/quasar_wrapper/io_ifu_brg_w_bits_data[39]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_wdata[3] i:/WORK/quasar_wrapper/io_ifu_brg_w_bits_data[3]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_wdata[40] i:/WORK/quasar_wrapper/io_ifu_brg_w_bits_data[40]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_wdata[41] i:/WORK/quasar_wrapper/io_ifu_brg_w_bits_data[41]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_wdata[42] i:/WORK/quasar_wrapper/io_ifu_brg_w_bits_data[42]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_wdata[43] i:/WORK/quasar_wrapper/io_ifu_brg_w_bits_data[43]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_wdata[44] i:/WORK/quasar_wrapper/io_ifu_brg_w_bits_data[44]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_wdata[45] i:/WORK/quasar_wrapper/io_ifu_brg_w_bits_data[45]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_wdata[46] i:/WORK/quasar_wrapper/io_ifu_brg_w_bits_data[46]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_wdata[47] i:/WORK/quasar_wrapper/io_ifu_brg_w_bits_data[47]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_wdata[48] i:/WORK/quasar_wrapper/io_ifu_brg_w_bits_data[48]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_wdata[49] i:/WORK/quasar_wrapper/io_ifu_brg_w_bits_data[49]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_wdata[4] i:/WORK/quasar_wrapper/io_ifu_brg_w_bits_data[4]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_wdata[50] i:/WORK/quasar_wrapper/io_ifu_brg_w_bits_data[50]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_wdata[51] i:/WORK/quasar_wrapper/io_ifu_brg_w_bits_data[51]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_wdata[52] i:/WORK/quasar_wrapper/io_ifu_brg_w_bits_data[52]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_wdata[53] i:/WORK/quasar_wrapper/io_ifu_brg_w_bits_data[53]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_wdata[54] i:/WORK/quasar_wrapper/io_ifu_brg_w_bits_data[54]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_wdata[55] i:/WORK/quasar_wrapper/io_ifu_brg_w_bits_data[55]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_wdata[56] i:/WORK/quasar_wrapper/io_ifu_brg_w_bits_data[56]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_wdata[57] i:/WORK/quasar_wrapper/io_ifu_brg_w_bits_data[57]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_wdata[58] i:/WORK/quasar_wrapper/io_ifu_brg_w_bits_data[58]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_wdata[59] i:/WORK/quasar_wrapper/io_ifu_brg_w_bits_data[59]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_wdata[5] i:/WORK/quasar_wrapper/io_ifu_brg_w_bits_data[5]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_wdata[60] i:/WORK/quasar_wrapper/io_ifu_brg_w_bits_data[60]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_wdata[61] i:/WORK/quasar_wrapper/io_ifu_brg_w_bits_data[61]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_wdata[62] i:/WORK/quasar_wrapper/io_ifu_brg_w_bits_data[62]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_wdata[63] i:/WORK/quasar_wrapper/io_ifu_brg_w_bits_data[63]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_wdata[6] i:/WORK/quasar_wrapper/io_ifu_brg_w_bits_data[6]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_wdata[7] i:/WORK/quasar_wrapper/io_ifu_brg_w_bits_data[7]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_wdata[8] i:/WORK/quasar_wrapper/io_ifu_brg_w_bits_data[8]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_wdata[9] i:/WORK/quasar_wrapper/io_ifu_brg_w_bits_data[9]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_wlast i:/WORK/quasar_wrapper/io_ifu_brg_w_bits_last
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_wstrb[0] i:/WORK/quasar_wrapper/io_ifu_brg_w_bits_strb[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_wstrb[1] i:/WORK/quasar_wrapper/io_ifu_brg_w_bits_strb[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_wstrb[2] i:/WORK/quasar_wrapper/io_ifu_brg_w_bits_strb[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_wstrb[3] i:/WORK/quasar_wrapper/io_ifu_brg_w_bits_strb[3]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_wstrb[4] i:/WORK/quasar_wrapper/io_ifu_brg_w_bits_strb[4]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_wstrb[5] i:/WORK/quasar_wrapper/io_ifu_brg_w_bits_strb[5]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_wstrb[6] i:/WORK/quasar_wrapper/io_ifu_brg_w_bits_strb[6]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_wstrb[7] i:/WORK/quasar_wrapper/io_ifu_brg_w_bits_strb[7]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/ifu_axi_wvalid i:/WORK/quasar_wrapper/io_ifu_brg_w_valid
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/jtag_tdo i:/WORK/quasar_wrapper/io_jtag_tdo
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_araddr[0] i:/WORK/quasar_wrapper/io_lsu_brg_ar_bits_addr[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_araddr[10] i:/WORK/quasar_wrapper/io_lsu_brg_ar_bits_addr[10]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_araddr[11] i:/WORK/quasar_wrapper/io_lsu_brg_ar_bits_addr[11]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_araddr[12] i:/WORK/quasar_wrapper/io_lsu_brg_ar_bits_addr[12]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_araddr[13] i:/WORK/quasar_wrapper/io_lsu_brg_ar_bits_addr[13]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_araddr[14] i:/WORK/quasar_wrapper/io_lsu_brg_ar_bits_addr[14]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_araddr[15] i:/WORK/quasar_wrapper/io_lsu_brg_ar_bits_addr[15]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_araddr[16] i:/WORK/quasar_wrapper/io_lsu_brg_ar_bits_addr[16]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_araddr[17] i:/WORK/quasar_wrapper/io_lsu_brg_ar_bits_addr[17]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_araddr[18] i:/WORK/quasar_wrapper/io_lsu_brg_ar_bits_addr[18]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_araddr[19] i:/WORK/quasar_wrapper/io_lsu_brg_ar_bits_addr[19]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_araddr[1] i:/WORK/quasar_wrapper/io_lsu_brg_ar_bits_addr[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_araddr[20] i:/WORK/quasar_wrapper/io_lsu_brg_ar_bits_addr[20]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_araddr[21] i:/WORK/quasar_wrapper/io_lsu_brg_ar_bits_addr[21]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_araddr[22] i:/WORK/quasar_wrapper/io_lsu_brg_ar_bits_addr[22]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_araddr[23] i:/WORK/quasar_wrapper/io_lsu_brg_ar_bits_addr[23]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_araddr[24] i:/WORK/quasar_wrapper/io_lsu_brg_ar_bits_addr[24]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_araddr[25] i:/WORK/quasar_wrapper/io_lsu_brg_ar_bits_addr[25]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_araddr[26] i:/WORK/quasar_wrapper/io_lsu_brg_ar_bits_addr[26]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_araddr[27] i:/WORK/quasar_wrapper/io_lsu_brg_ar_bits_addr[27]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_araddr[28] i:/WORK/quasar_wrapper/io_lsu_brg_ar_bits_addr[28]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_araddr[29] i:/WORK/quasar_wrapper/io_lsu_brg_ar_bits_addr[29]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_araddr[2] i:/WORK/quasar_wrapper/io_lsu_brg_ar_bits_addr[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_araddr[30] i:/WORK/quasar_wrapper/io_lsu_brg_ar_bits_addr[30]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_araddr[31] i:/WORK/quasar_wrapper/io_lsu_brg_ar_bits_addr[31]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_araddr[3] i:/WORK/quasar_wrapper/io_lsu_brg_ar_bits_addr[3]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_araddr[4] i:/WORK/quasar_wrapper/io_lsu_brg_ar_bits_addr[4]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_araddr[5] i:/WORK/quasar_wrapper/io_lsu_brg_ar_bits_addr[5]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_araddr[6] i:/WORK/quasar_wrapper/io_lsu_brg_ar_bits_addr[6]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_araddr[7] i:/WORK/quasar_wrapper/io_lsu_brg_ar_bits_addr[7]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_araddr[8] i:/WORK/quasar_wrapper/io_lsu_brg_ar_bits_addr[8]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_araddr[9] i:/WORK/quasar_wrapper/io_lsu_brg_ar_bits_addr[9]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_arburst[0] i:/WORK/quasar_wrapper/io_lsu_brg_ar_bits_burst[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_arburst[1] i:/WORK/quasar_wrapper/io_lsu_brg_ar_bits_burst[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_arcache[0] i:/WORK/quasar_wrapper/io_lsu_brg_ar_bits_cache[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_arcache[1] i:/WORK/quasar_wrapper/io_lsu_brg_ar_bits_cache[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_arcache[2] i:/WORK/quasar_wrapper/io_lsu_brg_ar_bits_cache[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_arcache[3] i:/WORK/quasar_wrapper/io_lsu_brg_ar_bits_cache[3]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_arid[0] i:/WORK/quasar_wrapper/io_lsu_brg_ar_bits_id[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_arid[1] i:/WORK/quasar_wrapper/io_lsu_brg_ar_bits_id[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_arid[2] i:/WORK/quasar_wrapper/io_lsu_brg_ar_bits_id[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_arlen[0] i:/WORK/quasar_wrapper/io_lsu_brg_ar_bits_len[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_arlen[1] i:/WORK/quasar_wrapper/io_lsu_brg_ar_bits_len[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_arlen[2] i:/WORK/quasar_wrapper/io_lsu_brg_ar_bits_len[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_arlen[3] i:/WORK/quasar_wrapper/io_lsu_brg_ar_bits_len[3]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_arlen[4] i:/WORK/quasar_wrapper/io_lsu_brg_ar_bits_len[4]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_arlen[5] i:/WORK/quasar_wrapper/io_lsu_brg_ar_bits_len[5]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_arlen[6] i:/WORK/quasar_wrapper/io_lsu_brg_ar_bits_len[6]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_arlen[7] i:/WORK/quasar_wrapper/io_lsu_brg_ar_bits_len[7]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_arlock i:/WORK/quasar_wrapper/io_lsu_brg_ar_bits_lock
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_arprot[0] i:/WORK/quasar_wrapper/io_lsu_brg_ar_bits_prot[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_arprot[1] i:/WORK/quasar_wrapper/io_lsu_brg_ar_bits_prot[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_arprot[2] i:/WORK/quasar_wrapper/io_lsu_brg_ar_bits_prot[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_arqos[0] i:/WORK/quasar_wrapper/io_lsu_brg_ar_bits_qos[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_arqos[1] i:/WORK/quasar_wrapper/io_lsu_brg_ar_bits_qos[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_arqos[2] i:/WORK/quasar_wrapper/io_lsu_brg_ar_bits_qos[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_arqos[3] i:/WORK/quasar_wrapper/io_lsu_brg_ar_bits_qos[3]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_arregion[0] i:/WORK/quasar_wrapper/io_lsu_brg_ar_bits_region[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_arregion[1] i:/WORK/quasar_wrapper/io_lsu_brg_ar_bits_region[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_arregion[2] i:/WORK/quasar_wrapper/io_lsu_brg_ar_bits_region[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_arregion[3] i:/WORK/quasar_wrapper/io_lsu_brg_ar_bits_region[3]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_arsize[0] i:/WORK/quasar_wrapper/io_lsu_brg_ar_bits_size[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_arsize[1] i:/WORK/quasar_wrapper/io_lsu_brg_ar_bits_size[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_arsize[2] i:/WORK/quasar_wrapper/io_lsu_brg_ar_bits_size[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_arvalid i:/WORK/quasar_wrapper/io_lsu_brg_ar_valid
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_awaddr[0] i:/WORK/quasar_wrapper/io_lsu_brg_aw_bits_addr[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_awaddr[10] i:/WORK/quasar_wrapper/io_lsu_brg_aw_bits_addr[10]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_awaddr[11] i:/WORK/quasar_wrapper/io_lsu_brg_aw_bits_addr[11]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_awaddr[12] i:/WORK/quasar_wrapper/io_lsu_brg_aw_bits_addr[12]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_awaddr[13] i:/WORK/quasar_wrapper/io_lsu_brg_aw_bits_addr[13]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_awaddr[14] i:/WORK/quasar_wrapper/io_lsu_brg_aw_bits_addr[14]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_awaddr[15] i:/WORK/quasar_wrapper/io_lsu_brg_aw_bits_addr[15]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_awaddr[16] i:/WORK/quasar_wrapper/io_lsu_brg_aw_bits_addr[16]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_awaddr[17] i:/WORK/quasar_wrapper/io_lsu_brg_aw_bits_addr[17]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_awaddr[18] i:/WORK/quasar_wrapper/io_lsu_brg_aw_bits_addr[18]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_awaddr[19] i:/WORK/quasar_wrapper/io_lsu_brg_aw_bits_addr[19]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_awaddr[1] i:/WORK/quasar_wrapper/io_lsu_brg_aw_bits_addr[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_awaddr[20] i:/WORK/quasar_wrapper/io_lsu_brg_aw_bits_addr[20]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_awaddr[21] i:/WORK/quasar_wrapper/io_lsu_brg_aw_bits_addr[21]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_awaddr[22] i:/WORK/quasar_wrapper/io_lsu_brg_aw_bits_addr[22]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_awaddr[23] i:/WORK/quasar_wrapper/io_lsu_brg_aw_bits_addr[23]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_awaddr[24] i:/WORK/quasar_wrapper/io_lsu_brg_aw_bits_addr[24]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_awaddr[25] i:/WORK/quasar_wrapper/io_lsu_brg_aw_bits_addr[25]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_awaddr[26] i:/WORK/quasar_wrapper/io_lsu_brg_aw_bits_addr[26]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_awaddr[27] i:/WORK/quasar_wrapper/io_lsu_brg_aw_bits_addr[27]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_awaddr[28] i:/WORK/quasar_wrapper/io_lsu_brg_aw_bits_addr[28]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_awaddr[29] i:/WORK/quasar_wrapper/io_lsu_brg_aw_bits_addr[29]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_awaddr[2] i:/WORK/quasar_wrapper/io_lsu_brg_aw_bits_addr[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_awaddr[30] i:/WORK/quasar_wrapper/io_lsu_brg_aw_bits_addr[30]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_awaddr[31] i:/WORK/quasar_wrapper/io_lsu_brg_aw_bits_addr[31]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_awaddr[3] i:/WORK/quasar_wrapper/io_lsu_brg_aw_bits_addr[3]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_awaddr[4] i:/WORK/quasar_wrapper/io_lsu_brg_aw_bits_addr[4]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_awaddr[5] i:/WORK/quasar_wrapper/io_lsu_brg_aw_bits_addr[5]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_awaddr[6] i:/WORK/quasar_wrapper/io_lsu_brg_aw_bits_addr[6]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_awaddr[7] i:/WORK/quasar_wrapper/io_lsu_brg_aw_bits_addr[7]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_awaddr[8] i:/WORK/quasar_wrapper/io_lsu_brg_aw_bits_addr[8]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_awaddr[9] i:/WORK/quasar_wrapper/io_lsu_brg_aw_bits_addr[9]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_awburst[0] i:/WORK/quasar_wrapper/io_lsu_brg_aw_bits_burst[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_awburst[1] i:/WORK/quasar_wrapper/io_lsu_brg_aw_bits_burst[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_awcache[0] i:/WORK/quasar_wrapper/io_lsu_brg_aw_bits_cache[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_awcache[1] i:/WORK/quasar_wrapper/io_lsu_brg_aw_bits_cache[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_awcache[2] i:/WORK/quasar_wrapper/io_lsu_brg_aw_bits_cache[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_awcache[3] i:/WORK/quasar_wrapper/io_lsu_brg_aw_bits_cache[3]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_awid[0] i:/WORK/quasar_wrapper/io_lsu_brg_aw_bits_id[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_awid[1] i:/WORK/quasar_wrapper/io_lsu_brg_aw_bits_id[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_awid[2] i:/WORK/quasar_wrapper/io_lsu_brg_aw_bits_id[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_awlen[0] i:/WORK/quasar_wrapper/io_lsu_brg_aw_bits_len[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_awlen[1] i:/WORK/quasar_wrapper/io_lsu_brg_aw_bits_len[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_awlen[2] i:/WORK/quasar_wrapper/io_lsu_brg_aw_bits_len[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_awlen[3] i:/WORK/quasar_wrapper/io_lsu_brg_aw_bits_len[3]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_awlen[4] i:/WORK/quasar_wrapper/io_lsu_brg_aw_bits_len[4]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_awlen[5] i:/WORK/quasar_wrapper/io_lsu_brg_aw_bits_len[5]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_awlen[6] i:/WORK/quasar_wrapper/io_lsu_brg_aw_bits_len[6]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_awlen[7] i:/WORK/quasar_wrapper/io_lsu_brg_aw_bits_len[7]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_awlock i:/WORK/quasar_wrapper/io_lsu_brg_aw_bits_lock
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_awprot[0] i:/WORK/quasar_wrapper/io_lsu_brg_aw_bits_prot[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_awprot[1] i:/WORK/quasar_wrapper/io_lsu_brg_aw_bits_prot[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_awprot[2] i:/WORK/quasar_wrapper/io_lsu_brg_aw_bits_prot[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_awqos[0] i:/WORK/quasar_wrapper/io_lsu_brg_aw_bits_qos[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_awqos[1] i:/WORK/quasar_wrapper/io_lsu_brg_aw_bits_qos[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_awqos[2] i:/WORK/quasar_wrapper/io_lsu_brg_aw_bits_qos[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_awqos[3] i:/WORK/quasar_wrapper/io_lsu_brg_aw_bits_qos[3]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_awregion[0] i:/WORK/quasar_wrapper/io_lsu_brg_aw_bits_region[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_awregion[1] i:/WORK/quasar_wrapper/io_lsu_brg_aw_bits_region[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_awregion[2] i:/WORK/quasar_wrapper/io_lsu_brg_aw_bits_region[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_awregion[3] i:/WORK/quasar_wrapper/io_lsu_brg_aw_bits_region[3]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_awsize[0] i:/WORK/quasar_wrapper/io_lsu_brg_aw_bits_size[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_awsize[1] i:/WORK/quasar_wrapper/io_lsu_brg_aw_bits_size[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_awsize[2] i:/WORK/quasar_wrapper/io_lsu_brg_aw_bits_size[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_awvalid i:/WORK/quasar_wrapper/io_lsu_brg_aw_valid
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_bready i:/WORK/quasar_wrapper/io_lsu_brg_b_ready
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_rready i:/WORK/quasar_wrapper/io_lsu_brg_r_ready
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_wdata[0] i:/WORK/quasar_wrapper/io_lsu_brg_w_bits_data[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_wdata[10] i:/WORK/quasar_wrapper/io_lsu_brg_w_bits_data[10]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_wdata[11] i:/WORK/quasar_wrapper/io_lsu_brg_w_bits_data[11]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_wdata[12] i:/WORK/quasar_wrapper/io_lsu_brg_w_bits_data[12]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_wdata[13] i:/WORK/quasar_wrapper/io_lsu_brg_w_bits_data[13]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_wdata[14] i:/WORK/quasar_wrapper/io_lsu_brg_w_bits_data[14]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_wdata[15] i:/WORK/quasar_wrapper/io_lsu_brg_w_bits_data[15]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_wdata[16] i:/WORK/quasar_wrapper/io_lsu_brg_w_bits_data[16]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_wdata[17] i:/WORK/quasar_wrapper/io_lsu_brg_w_bits_data[17]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_wdata[18] i:/WORK/quasar_wrapper/io_lsu_brg_w_bits_data[18]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_wdata[19] i:/WORK/quasar_wrapper/io_lsu_brg_w_bits_data[19]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_wdata[1] i:/WORK/quasar_wrapper/io_lsu_brg_w_bits_data[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_wdata[20] i:/WORK/quasar_wrapper/io_lsu_brg_w_bits_data[20]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_wdata[21] i:/WORK/quasar_wrapper/io_lsu_brg_w_bits_data[21]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_wdata[22] i:/WORK/quasar_wrapper/io_lsu_brg_w_bits_data[22]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_wdata[23] i:/WORK/quasar_wrapper/io_lsu_brg_w_bits_data[23]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_wdata[24] i:/WORK/quasar_wrapper/io_lsu_brg_w_bits_data[24]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_wdata[25] i:/WORK/quasar_wrapper/io_lsu_brg_w_bits_data[25]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_wdata[26] i:/WORK/quasar_wrapper/io_lsu_brg_w_bits_data[26]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_wdata[27] i:/WORK/quasar_wrapper/io_lsu_brg_w_bits_data[27]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_wdata[28] i:/WORK/quasar_wrapper/io_lsu_brg_w_bits_data[28]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_wdata[29] i:/WORK/quasar_wrapper/io_lsu_brg_w_bits_data[29]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_wdata[2] i:/WORK/quasar_wrapper/io_lsu_brg_w_bits_data[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_wdata[30] i:/WORK/quasar_wrapper/io_lsu_brg_w_bits_data[30]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_wdata[31] i:/WORK/quasar_wrapper/io_lsu_brg_w_bits_data[31]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_wdata[32] i:/WORK/quasar_wrapper/io_lsu_brg_w_bits_data[32]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_wdata[33] i:/WORK/quasar_wrapper/io_lsu_brg_w_bits_data[33]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_wdata[34] i:/WORK/quasar_wrapper/io_lsu_brg_w_bits_data[34]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_wdata[35] i:/WORK/quasar_wrapper/io_lsu_brg_w_bits_data[35]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_wdata[36] i:/WORK/quasar_wrapper/io_lsu_brg_w_bits_data[36]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_wdata[37] i:/WORK/quasar_wrapper/io_lsu_brg_w_bits_data[37]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_wdata[38] i:/WORK/quasar_wrapper/io_lsu_brg_w_bits_data[38]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_wdata[39] i:/WORK/quasar_wrapper/io_lsu_brg_w_bits_data[39]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_wdata[3] i:/WORK/quasar_wrapper/io_lsu_brg_w_bits_data[3]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_wdata[40] i:/WORK/quasar_wrapper/io_lsu_brg_w_bits_data[40]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_wdata[41] i:/WORK/quasar_wrapper/io_lsu_brg_w_bits_data[41]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_wdata[42] i:/WORK/quasar_wrapper/io_lsu_brg_w_bits_data[42]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_wdata[43] i:/WORK/quasar_wrapper/io_lsu_brg_w_bits_data[43]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_wdata[44] i:/WORK/quasar_wrapper/io_lsu_brg_w_bits_data[44]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_wdata[45] i:/WORK/quasar_wrapper/io_lsu_brg_w_bits_data[45]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_wdata[46] i:/WORK/quasar_wrapper/io_lsu_brg_w_bits_data[46]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_wdata[47] i:/WORK/quasar_wrapper/io_lsu_brg_w_bits_data[47]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_wdata[48] i:/WORK/quasar_wrapper/io_lsu_brg_w_bits_data[48]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_wdata[49] i:/WORK/quasar_wrapper/io_lsu_brg_w_bits_data[49]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_wdata[4] i:/WORK/quasar_wrapper/io_lsu_brg_w_bits_data[4]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_wdata[50] i:/WORK/quasar_wrapper/io_lsu_brg_w_bits_data[50]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_wdata[51] i:/WORK/quasar_wrapper/io_lsu_brg_w_bits_data[51]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_wdata[52] i:/WORK/quasar_wrapper/io_lsu_brg_w_bits_data[52]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_wdata[53] i:/WORK/quasar_wrapper/io_lsu_brg_w_bits_data[53]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_wdata[54] i:/WORK/quasar_wrapper/io_lsu_brg_w_bits_data[54]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_wdata[55] i:/WORK/quasar_wrapper/io_lsu_brg_w_bits_data[55]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_wdata[56] i:/WORK/quasar_wrapper/io_lsu_brg_w_bits_data[56]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_wdata[57] i:/WORK/quasar_wrapper/io_lsu_brg_w_bits_data[57]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_wdata[58] i:/WORK/quasar_wrapper/io_lsu_brg_w_bits_data[58]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_wdata[59] i:/WORK/quasar_wrapper/io_lsu_brg_w_bits_data[59]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_wdata[5] i:/WORK/quasar_wrapper/io_lsu_brg_w_bits_data[5]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_wdata[60] i:/WORK/quasar_wrapper/io_lsu_brg_w_bits_data[60]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_wdata[61] i:/WORK/quasar_wrapper/io_lsu_brg_w_bits_data[61]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_wdata[62] i:/WORK/quasar_wrapper/io_lsu_brg_w_bits_data[62]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_wdata[63] i:/WORK/quasar_wrapper/io_lsu_brg_w_bits_data[63]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_wdata[6] i:/WORK/quasar_wrapper/io_lsu_brg_w_bits_data[6]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_wdata[7] i:/WORK/quasar_wrapper/io_lsu_brg_w_bits_data[7]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_wdata[8] i:/WORK/quasar_wrapper/io_lsu_brg_w_bits_data[8]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_wdata[9] i:/WORK/quasar_wrapper/io_lsu_brg_w_bits_data[9]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_wlast i:/WORK/quasar_wrapper/io_lsu_brg_w_bits_last
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_wstrb[0] i:/WORK/quasar_wrapper/io_lsu_brg_w_bits_strb[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_wstrb[1] i:/WORK/quasar_wrapper/io_lsu_brg_w_bits_strb[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_wstrb[2] i:/WORK/quasar_wrapper/io_lsu_brg_w_bits_strb[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_wstrb[3] i:/WORK/quasar_wrapper/io_lsu_brg_w_bits_strb[3]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_wstrb[4] i:/WORK/quasar_wrapper/io_lsu_brg_w_bits_strb[4]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_wstrb[5] i:/WORK/quasar_wrapper/io_lsu_brg_w_bits_strb[5]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_wstrb[6] i:/WORK/quasar_wrapper/io_lsu_brg_w_bits_strb[6]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_wstrb[7] i:/WORK/quasar_wrapper/io_lsu_brg_w_bits_strb[7]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/lsu_axi_wvalid i:/WORK/quasar_wrapper/io_lsu_brg_w_valid
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/mpc_debug_halt_ack i:/WORK/quasar_wrapper/io_mpc_debug_halt_ack
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/mpc_debug_run_ack i:/WORK/quasar_wrapper/io_mpc_debug_run_ack
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/o_cpu_halt_ack i:/WORK/quasar_wrapper/io_o_cpu_halt_ack
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/o_cpu_halt_status i:/WORK/quasar_wrapper/io_o_cpu_halt_status
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/o_cpu_run_ack i:/WORK/quasar_wrapper/io_o_cpu_run_ack
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/o_debug_mode_status i:/WORK/quasar_wrapper/io_o_debug_mode_status
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_araddr[0] i:/WORK/quasar_wrapper/io_sb_brg_ar_bits_addr[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_araddr[10] i:/WORK/quasar_wrapper/io_sb_brg_ar_bits_addr[10]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_araddr[11] i:/WORK/quasar_wrapper/io_sb_brg_ar_bits_addr[11]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_araddr[12] i:/WORK/quasar_wrapper/io_sb_brg_ar_bits_addr[12]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_araddr[13] i:/WORK/quasar_wrapper/io_sb_brg_ar_bits_addr[13]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_araddr[14] i:/WORK/quasar_wrapper/io_sb_brg_ar_bits_addr[14]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_araddr[15] i:/WORK/quasar_wrapper/io_sb_brg_ar_bits_addr[15]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_araddr[16] i:/WORK/quasar_wrapper/io_sb_brg_ar_bits_addr[16]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_araddr[17] i:/WORK/quasar_wrapper/io_sb_brg_ar_bits_addr[17]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_araddr[18] i:/WORK/quasar_wrapper/io_sb_brg_ar_bits_addr[18]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_araddr[19] i:/WORK/quasar_wrapper/io_sb_brg_ar_bits_addr[19]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_araddr[1] i:/WORK/quasar_wrapper/io_sb_brg_ar_bits_addr[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_araddr[20] i:/WORK/quasar_wrapper/io_sb_brg_ar_bits_addr[20]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_araddr[21] i:/WORK/quasar_wrapper/io_sb_brg_ar_bits_addr[21]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_araddr[22] i:/WORK/quasar_wrapper/io_sb_brg_ar_bits_addr[22]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_araddr[23] i:/WORK/quasar_wrapper/io_sb_brg_ar_bits_addr[23]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_araddr[24] i:/WORK/quasar_wrapper/io_sb_brg_ar_bits_addr[24]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_araddr[25] i:/WORK/quasar_wrapper/io_sb_brg_ar_bits_addr[25]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_araddr[26] i:/WORK/quasar_wrapper/io_sb_brg_ar_bits_addr[26]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_araddr[27] i:/WORK/quasar_wrapper/io_sb_brg_ar_bits_addr[27]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_araddr[28] i:/WORK/quasar_wrapper/io_sb_brg_ar_bits_addr[28]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_araddr[29] i:/WORK/quasar_wrapper/io_sb_brg_ar_bits_addr[29]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_araddr[2] i:/WORK/quasar_wrapper/io_sb_brg_ar_bits_addr[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_araddr[30] i:/WORK/quasar_wrapper/io_sb_brg_ar_bits_addr[30]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_araddr[31] i:/WORK/quasar_wrapper/io_sb_brg_ar_bits_addr[31]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_araddr[3] i:/WORK/quasar_wrapper/io_sb_brg_ar_bits_addr[3]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_araddr[4] i:/WORK/quasar_wrapper/io_sb_brg_ar_bits_addr[4]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_araddr[5] i:/WORK/quasar_wrapper/io_sb_brg_ar_bits_addr[5]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_araddr[6] i:/WORK/quasar_wrapper/io_sb_brg_ar_bits_addr[6]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_araddr[7] i:/WORK/quasar_wrapper/io_sb_brg_ar_bits_addr[7]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_araddr[8] i:/WORK/quasar_wrapper/io_sb_brg_ar_bits_addr[8]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_araddr[9] i:/WORK/quasar_wrapper/io_sb_brg_ar_bits_addr[9]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_arburst[0] i:/WORK/quasar_wrapper/io_sb_brg_ar_bits_burst[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_arburst[1] i:/WORK/quasar_wrapper/io_sb_brg_ar_bits_burst[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_arcache[0] i:/WORK/quasar_wrapper/io_sb_brg_ar_bits_cache[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_arcache[1] i:/WORK/quasar_wrapper/io_sb_brg_ar_bits_cache[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_arcache[2] i:/WORK/quasar_wrapper/io_sb_brg_ar_bits_cache[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_arcache[3] i:/WORK/quasar_wrapper/io_sb_brg_ar_bits_cache[3]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_arid[0] i:/WORK/quasar_wrapper/io_sb_brg_ar_bits_id
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_arlen[0] i:/WORK/quasar_wrapper/io_sb_brg_ar_bits_len[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_arlen[1] i:/WORK/quasar_wrapper/io_sb_brg_ar_bits_len[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_arlen[2] i:/WORK/quasar_wrapper/io_sb_brg_ar_bits_len[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_arlen[3] i:/WORK/quasar_wrapper/io_sb_brg_ar_bits_len[3]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_arlen[4] i:/WORK/quasar_wrapper/io_sb_brg_ar_bits_len[4]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_arlen[5] i:/WORK/quasar_wrapper/io_sb_brg_ar_bits_len[5]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_arlen[6] i:/WORK/quasar_wrapper/io_sb_brg_ar_bits_len[6]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_arlen[7] i:/WORK/quasar_wrapper/io_sb_brg_ar_bits_len[7]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_arlock i:/WORK/quasar_wrapper/io_sb_brg_ar_bits_lock
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_arprot[0] i:/WORK/quasar_wrapper/io_sb_brg_ar_bits_prot[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_arprot[1] i:/WORK/quasar_wrapper/io_sb_brg_ar_bits_prot[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_arprot[2] i:/WORK/quasar_wrapper/io_sb_brg_ar_bits_prot[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_arqos[0] i:/WORK/quasar_wrapper/io_sb_brg_ar_bits_qos[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_arqos[1] i:/WORK/quasar_wrapper/io_sb_brg_ar_bits_qos[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_arqos[2] i:/WORK/quasar_wrapper/io_sb_brg_ar_bits_qos[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_arqos[3] i:/WORK/quasar_wrapper/io_sb_brg_ar_bits_qos[3]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_arregion[0] i:/WORK/quasar_wrapper/io_sb_brg_ar_bits_region[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_arregion[1] i:/WORK/quasar_wrapper/io_sb_brg_ar_bits_region[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_arregion[2] i:/WORK/quasar_wrapper/io_sb_brg_ar_bits_region[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_arregion[3] i:/WORK/quasar_wrapper/io_sb_brg_ar_bits_region[3]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_arsize[0] i:/WORK/quasar_wrapper/io_sb_brg_ar_bits_size[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_arsize[1] i:/WORK/quasar_wrapper/io_sb_brg_ar_bits_size[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_arsize[2] i:/WORK/quasar_wrapper/io_sb_brg_ar_bits_size[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_arvalid i:/WORK/quasar_wrapper/io_sb_brg_ar_valid
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_awaddr[0] i:/WORK/quasar_wrapper/io_sb_brg_aw_bits_addr[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_awaddr[10] i:/WORK/quasar_wrapper/io_sb_brg_aw_bits_addr[10]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_awaddr[11] i:/WORK/quasar_wrapper/io_sb_brg_aw_bits_addr[11]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_awaddr[12] i:/WORK/quasar_wrapper/io_sb_brg_aw_bits_addr[12]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_awaddr[13] i:/WORK/quasar_wrapper/io_sb_brg_aw_bits_addr[13]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_awaddr[14] i:/WORK/quasar_wrapper/io_sb_brg_aw_bits_addr[14]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_awaddr[15] i:/WORK/quasar_wrapper/io_sb_brg_aw_bits_addr[15]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_awaddr[16] i:/WORK/quasar_wrapper/io_sb_brg_aw_bits_addr[16]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_awaddr[17] i:/WORK/quasar_wrapper/io_sb_brg_aw_bits_addr[17]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_awaddr[18] i:/WORK/quasar_wrapper/io_sb_brg_aw_bits_addr[18]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_awaddr[19] i:/WORK/quasar_wrapper/io_sb_brg_aw_bits_addr[19]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_awaddr[1] i:/WORK/quasar_wrapper/io_sb_brg_aw_bits_addr[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_awaddr[20] i:/WORK/quasar_wrapper/io_sb_brg_aw_bits_addr[20]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_awaddr[21] i:/WORK/quasar_wrapper/io_sb_brg_aw_bits_addr[21]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_awaddr[22] i:/WORK/quasar_wrapper/io_sb_brg_aw_bits_addr[22]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_awaddr[23] i:/WORK/quasar_wrapper/io_sb_brg_aw_bits_addr[23]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_awaddr[24] i:/WORK/quasar_wrapper/io_sb_brg_aw_bits_addr[24]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_awaddr[25] i:/WORK/quasar_wrapper/io_sb_brg_aw_bits_addr[25]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_awaddr[26] i:/WORK/quasar_wrapper/io_sb_brg_aw_bits_addr[26]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_awaddr[27] i:/WORK/quasar_wrapper/io_sb_brg_aw_bits_addr[27]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_awaddr[28] i:/WORK/quasar_wrapper/io_sb_brg_aw_bits_addr[28]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_awaddr[29] i:/WORK/quasar_wrapper/io_sb_brg_aw_bits_addr[29]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_awaddr[2] i:/WORK/quasar_wrapper/io_sb_brg_aw_bits_addr[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_awaddr[30] i:/WORK/quasar_wrapper/io_sb_brg_aw_bits_addr[30]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_awaddr[31] i:/WORK/quasar_wrapper/io_sb_brg_aw_bits_addr[31]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_awaddr[3] i:/WORK/quasar_wrapper/io_sb_brg_aw_bits_addr[3]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_awaddr[4] i:/WORK/quasar_wrapper/io_sb_brg_aw_bits_addr[4]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_awaddr[5] i:/WORK/quasar_wrapper/io_sb_brg_aw_bits_addr[5]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_awaddr[6] i:/WORK/quasar_wrapper/io_sb_brg_aw_bits_addr[6]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_awaddr[7] i:/WORK/quasar_wrapper/io_sb_brg_aw_bits_addr[7]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_awaddr[8] i:/WORK/quasar_wrapper/io_sb_brg_aw_bits_addr[8]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_awaddr[9] i:/WORK/quasar_wrapper/io_sb_brg_aw_bits_addr[9]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_awburst[0] i:/WORK/quasar_wrapper/io_sb_brg_aw_bits_burst[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_awburst[1] i:/WORK/quasar_wrapper/io_sb_brg_aw_bits_burst[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_awcache[0] i:/WORK/quasar_wrapper/io_sb_brg_aw_bits_cache[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_awcache[1] i:/WORK/quasar_wrapper/io_sb_brg_aw_bits_cache[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_awcache[2] i:/WORK/quasar_wrapper/io_sb_brg_aw_bits_cache[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_awcache[3] i:/WORK/quasar_wrapper/io_sb_brg_aw_bits_cache[3]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_awid[0] i:/WORK/quasar_wrapper/io_sb_brg_aw_bits_id
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_awlen[0] i:/WORK/quasar_wrapper/io_sb_brg_aw_bits_len[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_awlen[1] i:/WORK/quasar_wrapper/io_sb_brg_aw_bits_len[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_awlen[2] i:/WORK/quasar_wrapper/io_sb_brg_aw_bits_len[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_awlen[3] i:/WORK/quasar_wrapper/io_sb_brg_aw_bits_len[3]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_awlen[4] i:/WORK/quasar_wrapper/io_sb_brg_aw_bits_len[4]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_awlen[5] i:/WORK/quasar_wrapper/io_sb_brg_aw_bits_len[5]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_awlen[6] i:/WORK/quasar_wrapper/io_sb_brg_aw_bits_len[6]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_awlen[7] i:/WORK/quasar_wrapper/io_sb_brg_aw_bits_len[7]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_awlock i:/WORK/quasar_wrapper/io_sb_brg_aw_bits_lock
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_awprot[0] i:/WORK/quasar_wrapper/io_sb_brg_aw_bits_prot[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_awprot[1] i:/WORK/quasar_wrapper/io_sb_brg_aw_bits_prot[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_awprot[2] i:/WORK/quasar_wrapper/io_sb_brg_aw_bits_prot[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_awqos[0] i:/WORK/quasar_wrapper/io_sb_brg_aw_bits_qos[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_awqos[1] i:/WORK/quasar_wrapper/io_sb_brg_aw_bits_qos[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_awqos[2] i:/WORK/quasar_wrapper/io_sb_brg_aw_bits_qos[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_awqos[3] i:/WORK/quasar_wrapper/io_sb_brg_aw_bits_qos[3]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_awregion[0] i:/WORK/quasar_wrapper/io_sb_brg_aw_bits_region[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_awregion[1] i:/WORK/quasar_wrapper/io_sb_brg_aw_bits_region[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_awregion[2] i:/WORK/quasar_wrapper/io_sb_brg_aw_bits_region[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_awregion[3] i:/WORK/quasar_wrapper/io_sb_brg_aw_bits_region[3]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_awsize[0] i:/WORK/quasar_wrapper/io_sb_brg_aw_bits_size[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_awsize[1] i:/WORK/quasar_wrapper/io_sb_brg_aw_bits_size[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_awsize[2] i:/WORK/quasar_wrapper/io_sb_brg_aw_bits_size[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_awvalid i:/WORK/quasar_wrapper/io_sb_brg_aw_valid
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_bready i:/WORK/quasar_wrapper/io_sb_brg_b_ready
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_rready i:/WORK/quasar_wrapper/io_sb_brg_r_ready
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_wdata[0] i:/WORK/quasar_wrapper/io_sb_brg_w_bits_data[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_wdata[10] i:/WORK/quasar_wrapper/io_sb_brg_w_bits_data[10]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_wdata[11] i:/WORK/quasar_wrapper/io_sb_brg_w_bits_data[11]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_wdata[12] i:/WORK/quasar_wrapper/io_sb_brg_w_bits_data[12]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_wdata[13] i:/WORK/quasar_wrapper/io_sb_brg_w_bits_data[13]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_wdata[14] i:/WORK/quasar_wrapper/io_sb_brg_w_bits_data[14]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_wdata[15] i:/WORK/quasar_wrapper/io_sb_brg_w_bits_data[15]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_wdata[16] i:/WORK/quasar_wrapper/io_sb_brg_w_bits_data[16]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_wdata[17] i:/WORK/quasar_wrapper/io_sb_brg_w_bits_data[17]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_wdata[18] i:/WORK/quasar_wrapper/io_sb_brg_w_bits_data[18]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_wdata[19] i:/WORK/quasar_wrapper/io_sb_brg_w_bits_data[19]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_wdata[1] i:/WORK/quasar_wrapper/io_sb_brg_w_bits_data[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_wdata[20] i:/WORK/quasar_wrapper/io_sb_brg_w_bits_data[20]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_wdata[21] i:/WORK/quasar_wrapper/io_sb_brg_w_bits_data[21]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_wdata[22] i:/WORK/quasar_wrapper/io_sb_brg_w_bits_data[22]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_wdata[23] i:/WORK/quasar_wrapper/io_sb_brg_w_bits_data[23]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_wdata[24] i:/WORK/quasar_wrapper/io_sb_brg_w_bits_data[24]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_wdata[25] i:/WORK/quasar_wrapper/io_sb_brg_w_bits_data[25]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_wdata[26] i:/WORK/quasar_wrapper/io_sb_brg_w_bits_data[26]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_wdata[27] i:/WORK/quasar_wrapper/io_sb_brg_w_bits_data[27]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_wdata[28] i:/WORK/quasar_wrapper/io_sb_brg_w_bits_data[28]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_wdata[29] i:/WORK/quasar_wrapper/io_sb_brg_w_bits_data[29]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_wdata[2] i:/WORK/quasar_wrapper/io_sb_brg_w_bits_data[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_wdata[30] i:/WORK/quasar_wrapper/io_sb_brg_w_bits_data[30]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_wdata[31] i:/WORK/quasar_wrapper/io_sb_brg_w_bits_data[31]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_wdata[32] i:/WORK/quasar_wrapper/io_sb_brg_w_bits_data[32]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_wdata[33] i:/WORK/quasar_wrapper/io_sb_brg_w_bits_data[33]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_wdata[34] i:/WORK/quasar_wrapper/io_sb_brg_w_bits_data[34]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_wdata[35] i:/WORK/quasar_wrapper/io_sb_brg_w_bits_data[35]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_wdata[36] i:/WORK/quasar_wrapper/io_sb_brg_w_bits_data[36]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_wdata[37] i:/WORK/quasar_wrapper/io_sb_brg_w_bits_data[37]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_wdata[38] i:/WORK/quasar_wrapper/io_sb_brg_w_bits_data[38]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_wdata[39] i:/WORK/quasar_wrapper/io_sb_brg_w_bits_data[39]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_wdata[3] i:/WORK/quasar_wrapper/io_sb_brg_w_bits_data[3]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_wdata[40] i:/WORK/quasar_wrapper/io_sb_brg_w_bits_data[40]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_wdata[41] i:/WORK/quasar_wrapper/io_sb_brg_w_bits_data[41]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_wdata[42] i:/WORK/quasar_wrapper/io_sb_brg_w_bits_data[42]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_wdata[43] i:/WORK/quasar_wrapper/io_sb_brg_w_bits_data[43]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_wdata[44] i:/WORK/quasar_wrapper/io_sb_brg_w_bits_data[44]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_wdata[45] i:/WORK/quasar_wrapper/io_sb_brg_w_bits_data[45]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_wdata[46] i:/WORK/quasar_wrapper/io_sb_brg_w_bits_data[46]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_wdata[47] i:/WORK/quasar_wrapper/io_sb_brg_w_bits_data[47]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_wdata[48] i:/WORK/quasar_wrapper/io_sb_brg_w_bits_data[48]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_wdata[49] i:/WORK/quasar_wrapper/io_sb_brg_w_bits_data[49]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_wdata[4] i:/WORK/quasar_wrapper/io_sb_brg_w_bits_data[4]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_wdata[50] i:/WORK/quasar_wrapper/io_sb_brg_w_bits_data[50]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_wdata[51] i:/WORK/quasar_wrapper/io_sb_brg_w_bits_data[51]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_wdata[52] i:/WORK/quasar_wrapper/io_sb_brg_w_bits_data[52]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_wdata[53] i:/WORK/quasar_wrapper/io_sb_brg_w_bits_data[53]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_wdata[54] i:/WORK/quasar_wrapper/io_sb_brg_w_bits_data[54]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_wdata[55] i:/WORK/quasar_wrapper/io_sb_brg_w_bits_data[55]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_wdata[56] i:/WORK/quasar_wrapper/io_sb_brg_w_bits_data[56]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_wdata[57] i:/WORK/quasar_wrapper/io_sb_brg_w_bits_data[57]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_wdata[58] i:/WORK/quasar_wrapper/io_sb_brg_w_bits_data[58]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_wdata[59] i:/WORK/quasar_wrapper/io_sb_brg_w_bits_data[59]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_wdata[5] i:/WORK/quasar_wrapper/io_sb_brg_w_bits_data[5]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_wdata[60] i:/WORK/quasar_wrapper/io_sb_brg_w_bits_data[60]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_wdata[61] i:/WORK/quasar_wrapper/io_sb_brg_w_bits_data[61]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_wdata[62] i:/WORK/quasar_wrapper/io_sb_brg_w_bits_data[62]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_wdata[63] i:/WORK/quasar_wrapper/io_sb_brg_w_bits_data[63]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_wdata[6] i:/WORK/quasar_wrapper/io_sb_brg_w_bits_data[6]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_wdata[7] i:/WORK/quasar_wrapper/io_sb_brg_w_bits_data[7]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_wdata[8] i:/WORK/quasar_wrapper/io_sb_brg_w_bits_data[8]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_wdata[9] i:/WORK/quasar_wrapper/io_sb_brg_w_bits_data[9]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_wlast i:/WORK/quasar_wrapper/io_sb_brg_w_bits_last
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_wstrb[0] i:/WORK/quasar_wrapper/io_sb_brg_w_bits_strb[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_wstrb[1] i:/WORK/quasar_wrapper/io_sb_brg_w_bits_strb[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_wstrb[2] i:/WORK/quasar_wrapper/io_sb_brg_w_bits_strb[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_wstrb[3] i:/WORK/quasar_wrapper/io_sb_brg_w_bits_strb[3]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_wstrb[4] i:/WORK/quasar_wrapper/io_sb_brg_w_bits_strb[4]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_wstrb[5] i:/WORK/quasar_wrapper/io_sb_brg_w_bits_strb[5]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_wstrb[6] i:/WORK/quasar_wrapper/io_sb_brg_w_bits_strb[6]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_wstrb[7] i:/WORK/quasar_wrapper/io_sb_brg_w_bits_strb[7]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/sb_axi_wvalid i:/WORK/quasar_wrapper/io_sb_brg_w_valid
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_address_ip[0] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_address_ip[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_address_ip[10] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_address_ip[10]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_address_ip[11] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_address_ip[11]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_address_ip[12] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_address_ip[12]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_address_ip[13] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_address_ip[13]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_address_ip[14] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_address_ip[14]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_address_ip[15] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_address_ip[15]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_address_ip[16] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_address_ip[16]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_address_ip[17] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_address_ip[17]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_address_ip[18] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_address_ip[18]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_address_ip[19] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_address_ip[19]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_address_ip[1] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_address_ip[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_address_ip[20] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_address_ip[20]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_address_ip[21] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_address_ip[21]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_address_ip[22] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_address_ip[22]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_address_ip[23] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_address_ip[23]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_address_ip[24] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_address_ip[24]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_address_ip[25] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_address_ip[25]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_address_ip[26] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_address_ip[26]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_address_ip[27] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_address_ip[27]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_address_ip[28] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_address_ip[28]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_address_ip[29] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_address_ip[29]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_address_ip[2] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_address_ip[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_address_ip[30] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_address_ip[30]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_address_ip[31] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_address_ip[31]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_address_ip[3] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_address_ip[3]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_address_ip[4] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_address_ip[4]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_address_ip[5] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_address_ip[5]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_address_ip[6] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_address_ip[6]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_address_ip[7] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_address_ip[7]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_address_ip[8] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_address_ip[8]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_address_ip[9] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_address_ip[9]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_ecause_ip[0] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_ecause_ip[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_ecause_ip[1] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_ecause_ip[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_ecause_ip[2] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_ecause_ip[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_ecause_ip[3] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_ecause_ip[3]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_ecause_ip[4] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_ecause_ip[4]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_exception_ip i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_exception_ip
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_insn_ip[0] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_insn_ip[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_insn_ip[10] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_insn_ip[10]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_insn_ip[11] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_insn_ip[11]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_insn_ip[12] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_insn_ip[12]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_insn_ip[13] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_insn_ip[13]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_insn_ip[14] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_insn_ip[14]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_insn_ip[15] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_insn_ip[15]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_insn_ip[16] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_insn_ip[16]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_insn_ip[17] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_insn_ip[17]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_insn_ip[18] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_insn_ip[18]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_insn_ip[19] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_insn_ip[19]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_insn_ip[1] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_insn_ip[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_insn_ip[20] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_insn_ip[20]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_insn_ip[21] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_insn_ip[21]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_insn_ip[22] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_insn_ip[22]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_insn_ip[23] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_insn_ip[23]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_insn_ip[24] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_insn_ip[24]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_insn_ip[25] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_insn_ip[25]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_insn_ip[26] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_insn_ip[26]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_insn_ip[27] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_insn_ip[27]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_insn_ip[28] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_insn_ip[28]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_insn_ip[29] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_insn_ip[29]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_insn_ip[2] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_insn_ip[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_insn_ip[30] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_insn_ip[30]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_insn_ip[31] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_insn_ip[31]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_insn_ip[3] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_insn_ip[3]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_insn_ip[4] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_insn_ip[4]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_insn_ip[5] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_insn_ip[5]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_insn_ip[6] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_insn_ip[6]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_insn_ip[7] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_insn_ip[7]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_insn_ip[8] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_insn_ip[8]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_insn_ip[9] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_insn_ip[9]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_interrupt_ip i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_interrupt_ip
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_tval_ip[0] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_tval_ip[0]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_tval_ip[10] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_tval_ip[10]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_tval_ip[11] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_tval_ip[11]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_tval_ip[12] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_tval_ip[12]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_tval_ip[13] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_tval_ip[13]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_tval_ip[14] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_tval_ip[14]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_tval_ip[15] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_tval_ip[15]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_tval_ip[16] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_tval_ip[16]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_tval_ip[17] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_tval_ip[17]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_tval_ip[18] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_tval_ip[18]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_tval_ip[19] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_tval_ip[19]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_tval_ip[1] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_tval_ip[1]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_tval_ip[20] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_tval_ip[20]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_tval_ip[21] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_tval_ip[21]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_tval_ip[22] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_tval_ip[22]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_tval_ip[23] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_tval_ip[23]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_tval_ip[24] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_tval_ip[24]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_tval_ip[25] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_tval_ip[25]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_tval_ip[26] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_tval_ip[26]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_tval_ip[27] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_tval_ip[27]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_tval_ip[28] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_tval_ip[28]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_tval_ip[29] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_tval_ip[29]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_tval_ip[2] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_tval_ip[2]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_tval_ip[30] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_tval_ip[30]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_tval_ip[31] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_tval_ip[31]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_tval_ip[3] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_tval_ip[3]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_tval_ip[4] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_tval_ip[4]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_tval_ip[5] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_tval_ip[5]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_tval_ip[6] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_tval_ip[6]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_tval_ip[7] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_tval_ip[7]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_tval_ip[8] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_tval_ip[8]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_tval_ip[9] i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_tval_ip[9]
set_user_match -type port -noninverted r:/WORK/el2_swerv_wrapper/trace_rv_i_valid_ip i:/WORK/quasar_wrapper/io_rv_trace_pkt_rv_i_valid_ip

6
verif/LEC/setup_files/constant.fms
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@ -1,6 +0,0 @@
set_constant i:/WORK/quasar_wrapper/core/dec/decode/cam_raw_0_bits_tag_reg[2] 0
set_constant i:/WORK/quasar_wrapper/core/dec/decode/cam_raw_1_bits_tag_reg[2] 0
set_constant i:/WORK/quasar_wrapper/core/dec/decode/cam_raw_2_bits_tag_reg[2] 0
set_constant i:/WORK/quasar_wrapper/core/dec/decode/cam_raw_3_bits_tag_reg[2] 0
set_constant r:/WORK/el2_swerv_wrapper/swerv/lsu/bus_intf/bus_buffer/obuf_tag0ff/genblock.dffs/dout_reg[2] 0
set_constant r:/WORK/el2_swerv_wrapper/swerv/lsu/bus_intf/bus_buffer/obuf_tag1ff/genblock.dffs/dout_reg[2] 0

1369
verif/LEC/setup_files/port.fms
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1
verif/sim/README.md Normal file
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@ -0,0 +1 @@
Directory containing the test files and simulation logs generated at runtime