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axi to ahb update

This commit is contained in:
​Laraib Khan 2020-12-01 16:20:25 +05:00
parent 58343b6532
commit a91a14fd34
12 changed files with 1827 additions and 623 deletions
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34
ahb_to_axi4.anno.json Normal file
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@ -0,0 +1,34 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~ahb_to_axi4|ahb_to_axi4>io_ahb_hreadyout",
"sources":[
"~ahb_to_axi4|ahb_to_axi4>io_ahb_hresp",
"~ahb_to_axi4|ahb_to_axi4>io_axi_awvalid",
"~ahb_to_axi4|ahb_to_axi4>io_axi_awready",
"~ahb_to_axi4|ahb_to_axi4>io_axi_arvalid",
"~ahb_to_axi4|ahb_to_axi4>io_axi_arready"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"ahb_to_axi4.gated_latch",
"resourceId":"/vsrc/gated_latch.v"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"ahb_to_axi4"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

486
ahb_to_axi4.fir Normal file
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@ -0,0 +1,486 @@
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
circuit ahb_to_axi4 :
extmodule gated_latch :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch @[el2_lib.scala 474:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
extmodule gated_latch_1 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_1 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_1 @[el2_lib.scala 474:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
extmodule gated_latch_2 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_2 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_2 @[el2_lib.scala 474:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
extmodule gated_latch_3 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_3 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_3 @[el2_lib.scala 474:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
module ahb_to_axi4 :
input clock : Clock
input reset : AsyncReset
output io : {flip scan_mode : UInt<1>, flip bus_clk_en : UInt<1>, flip clk_override : UInt<1>, flip axi_awready : UInt<1>, flip axi_wready : UInt<1>, flip axi_bvalid : UInt<1>, flip axi_bresp : UInt<2>, flip axi_bid : UInt<0>, flip axi_arready : UInt<1>, flip axi_rvalid : UInt<1>, flip axi_rid : UInt<0>, flip axi_rdata : UInt<64>, flip axi_rresp : UInt<2>, flip ahb_haddr : UInt<32>, flip ahb_hburst : UInt<3>, flip ahb_hmastlock : UInt<1>, flip ahb_hprot : UInt<4>, flip ahb_hsize : UInt<3>, flip ahb_htrans : UInt<2>, flip ahb_hwrite : UInt<1>, flip ahb_hwdata : UInt<64>, flip ahb_hsel : UInt<1>, flip ahb_hreadyin : UInt<1>, axi_awvalid : UInt<1>, axi_awid : UInt<0>, axi_awaddr : UInt<32>, axi_awsize : UInt<3>, axi_awprot : UInt<3>, axi_awlen : UInt<8>, axi_awburst : UInt<2>, axi_wvalid : UInt<1>, axi_wdata : UInt<64>, axi_wstrb : UInt<8>, axi_wlast : UInt<1>, axi_bready : UInt<1>, axi_arvalid : UInt<1>, axi_arid : UInt<0>, axi_araddr : UInt<32>, axi_arsize : UInt<3>, axi_arprot : UInt<3>, axi_arlen : UInt<8>, axi_arburst : UInt<2>, axi_rready : UInt<1>, ahb_hrdata : UInt<64>, ahb_hreadyout : UInt<1>, ahb_hresp : UInt<1>}
wire master_wstrb : UInt<8>
master_wstrb <= UInt<8>("h00")
wire buf_state_en : UInt<1>
buf_state_en <= UInt<1>("h00")
wire buf_read_error_in : UInt<1>
buf_read_error_in <= UInt<1>("h00")
wire buf_read_error : UInt<1>
buf_read_error <= UInt<1>("h00")
wire buf_rdata : UInt<64>
buf_rdata <= UInt<64>("h00")
wire ahb_hready : UInt<1>
ahb_hready <= UInt<1>("h00")
wire ahb_hready_q : UInt<1>
ahb_hready_q <= UInt<1>("h00")
wire ahb_htrans_in : UInt<2>
ahb_htrans_in <= UInt<2>("h00")
wire ahb_htrans_q : UInt<2>
ahb_htrans_q <= UInt<2>("h00")
wire ahb_hsize_q : UInt<3>
ahb_hsize_q <= UInt<3>("h00")
wire ahb_hwrite_q : UInt<1>
ahb_hwrite_q <= UInt<1>("h00")
wire ahb_haddr_q : UInt<32>
ahb_haddr_q <= UInt<32>("h00")
wire ahb_hwdata_q : UInt<64>
ahb_hwdata_q <= UInt<64>("h00")
wire ahb_hresp_q : UInt<1>
ahb_hresp_q <= UInt<1>("h00")
wire ahb_addr_in_iccm : UInt<1>
ahb_addr_in_iccm <= UInt<1>("h00")
wire ahb_addr_in_iccm_region_nc : UInt<1>
ahb_addr_in_iccm_region_nc <= UInt<1>("h00")
wire buf_rdata_en : UInt<1>
buf_rdata_en <= UInt<1>("h00")
wire ahb_bus_addr_clk_en : UInt<1>
ahb_bus_addr_clk_en <= UInt<1>("h00")
wire buf_rdata_clk_en : UInt<1>
buf_rdata_clk_en <= UInt<1>("h00")
wire ahb_clk : Clock @[ahb_to_axi4.scala 84:35]
wire ahb_addr_clk : Clock @[ahb_to_axi4.scala 85:35]
wire buf_rdata_clk : Clock @[ahb_to_axi4.scala 86:35]
wire cmdbuf_wr_en : UInt<1>
cmdbuf_wr_en <= UInt<1>("h00")
wire cmdbuf_rst : UInt<1>
cmdbuf_rst <= UInt<1>("h00")
wire cmdbuf_full : UInt<1>
cmdbuf_full <= UInt<1>("h00")
wire cmdbuf_vld : UInt<1>
cmdbuf_vld <= UInt<1>("h00")
wire cmdbuf_write : UInt<1>
cmdbuf_write <= UInt<1>("h00")
wire cmdbuf_size : UInt<2>
cmdbuf_size <= UInt<2>("h00")
wire cmdbuf_wstrb : UInt<8>
cmdbuf_wstrb <= UInt<8>("h00")
wire cmdbuf_addr : UInt<32>
cmdbuf_addr <= UInt<32>("h00")
wire cmdbuf_wdata : UInt<64>
cmdbuf_wdata <= UInt<64>("h00")
wire bus_clk : Clock @[ahb_to_axi4.scala 98:35]
node _T = bits(ahb_haddr_q, 31, 28) @[el2_lib.scala 496:27]
node ahb_addr_in_dccm_region_nc = eq(_T, UInt<4>("h0f")) @[el2_lib.scala 496:49]
wire ahb_addr_in_dccm : UInt<1> @[el2_lib.scala 497:26]
node _T_1 = bits(ahb_haddr_q, 31, 16) @[el2_lib.scala 501:24]
node _T_2 = eq(_T_1, UInt<16>("h0f004")) @[el2_lib.scala 501:39]
ahb_addr_in_dccm <= _T_2 @[el2_lib.scala 501:16]
ahb_addr_in_iccm <= UInt<1>("h00") @[ahb_to_axi4.scala 109:24]
ahb_addr_in_iccm_region_nc <= UInt<1>("h00") @[ahb_to_axi4.scala 110:34]
node _T_3 = bits(ahb_haddr_q, 31, 28) @[el2_lib.scala 496:27]
node ahb_addr_in_pic_region_nc = eq(_T_3, UInt<4>("h0f")) @[el2_lib.scala 496:49]
wire ahb_addr_in_pic : UInt<1> @[el2_lib.scala 497:26]
node _T_4 = bits(ahb_haddr_q, 31, 15) @[el2_lib.scala 501:24]
node _T_5 = eq(_T_4, UInt<17>("h01e018")) @[el2_lib.scala 501:39]
ahb_addr_in_pic <= _T_5 @[el2_lib.scala 501:16]
wire buf_state : UInt<2>
buf_state <= UInt<2>("h00")
wire buf_nxtstate : UInt<2>
buf_nxtstate <= UInt<2>("h00")
buf_nxtstate <= UInt<2>("h00") @[ahb_to_axi4.scala 119:33]
buf_state_en <= UInt<1>("h00") @[ahb_to_axi4.scala 120:33]
buf_rdata_en <= UInt<1>("h00") @[ahb_to_axi4.scala 121:33]
buf_read_error_in <= UInt<1>("h00") @[ahb_to_axi4.scala 122:33]
cmdbuf_wr_en <= UInt<1>("h00") @[ahb_to_axi4.scala 123:33]
node _T_6 = eq(UInt<2>("h00"), buf_state) @[Conditional.scala 37:30]
when _T_6 : @[Conditional.scala 40:58]
node _T_7 = mux(io.ahb_hwrite, UInt<2>("h01"), UInt<2>("h02")) @[ahb_to_axi4.scala 127:28]
buf_nxtstate <= _T_7 @[ahb_to_axi4.scala 127:22]
node _T_8 = bits(io.ahb_htrans, 1, 1) @[ahb_to_axi4.scala 128:51]
node _T_9 = and(ahb_hready, _T_8) @[ahb_to_axi4.scala 128:36]
node _T_10 = and(_T_9, io.ahb_hsel) @[ahb_to_axi4.scala 128:55]
buf_state_en <= _T_10 @[ahb_to_axi4.scala 128:22]
skip @[Conditional.scala 40:58]
else : @[Conditional.scala 39:67]
node _T_11 = eq(UInt<2>("h01"), buf_state) @[Conditional.scala 37:30]
when _T_11 : @[Conditional.scala 39:67]
node _T_12 = bits(io.ahb_htrans, 1, 0) @[ahb_to_axi4.scala 131:59]
node _T_13 = eq(_T_12, UInt<1>("h00")) @[ahb_to_axi4.scala 131:66]
node _T_14 = or(io.ahb_hresp, _T_13) @[ahb_to_axi4.scala 131:43]
node _T_15 = eq(io.ahb_hsel, UInt<1>("h00")) @[ahb_to_axi4.scala 131:80]
node _T_16 = or(_T_14, _T_15) @[ahb_to_axi4.scala 131:78]
node _T_17 = bits(_T_16, 0, 0) @[ahb_to_axi4.scala 131:94]
node _T_18 = mux(io.ahb_hwrite, UInt<2>("h01"), UInt<2>("h02")) @[ahb_to_axi4.scala 131:111]
node _T_19 = mux(_T_17, UInt<2>("h00"), _T_18) @[ahb_to_axi4.scala 131:28]
buf_nxtstate <= _T_19 @[ahb_to_axi4.scala 131:22]
node _T_20 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 132:26]
node _T_21 = or(_T_20, io.ahb_hresp) @[ahb_to_axi4.scala 132:39]
buf_state_en <= _T_21 @[ahb_to_axi4.scala 132:22]
node _T_22 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 133:25]
node _T_23 = bits(io.ahb_htrans, 1, 0) @[ahb_to_axi4.scala 133:72]
node _T_24 = eq(_T_23, UInt<1>("h01")) @[ahb_to_axi4.scala 133:79]
node _T_25 = and(_T_24, io.ahb_hsel) @[ahb_to_axi4.scala 133:92]
node _T_26 = or(io.ahb_hresp, _T_25) @[ahb_to_axi4.scala 133:55]
node _T_27 = eq(_T_26, UInt<1>("h00")) @[ahb_to_axi4.scala 133:40]
node _T_28 = and(_T_22, _T_27) @[ahb_to_axi4.scala 133:38]
cmdbuf_wr_en <= _T_28 @[ahb_to_axi4.scala 133:22]
skip @[Conditional.scala 39:67]
else : @[Conditional.scala 39:67]
node _T_29 = eq(UInt<2>("h02"), buf_state) @[Conditional.scala 37:30]
when _T_29 : @[Conditional.scala 39:67]
node _T_30 = mux(io.ahb_hresp, UInt<2>("h00"), UInt<2>("h03")) @[ahb_to_axi4.scala 136:28]
buf_nxtstate <= _T_30 @[ahb_to_axi4.scala 136:22]
node _T_31 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 137:26]
node _T_32 = or(_T_31, io.ahb_hresp) @[ahb_to_axi4.scala 137:39]
buf_state_en <= _T_32 @[ahb_to_axi4.scala 137:22]
node _T_33 = eq(io.ahb_hresp, UInt<1>("h00")) @[ahb_to_axi4.scala 138:25]
node _T_34 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 138:41]
node _T_35 = and(_T_33, _T_34) @[ahb_to_axi4.scala 138:39]
cmdbuf_wr_en <= _T_35 @[ahb_to_axi4.scala 138:22]
skip @[Conditional.scala 39:67]
else : @[Conditional.scala 39:67]
node _T_36 = eq(UInt<2>("h03"), buf_state) @[Conditional.scala 37:30]
when _T_36 : @[Conditional.scala 39:67]
buf_nxtstate <= UInt<2>("h00") @[ahb_to_axi4.scala 141:22]
node _T_37 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 142:41]
node _T_38 = and(io.axi_rvalid, _T_37) @[ahb_to_axi4.scala 142:39]
buf_state_en <= _T_38 @[ahb_to_axi4.scala 142:22]
buf_rdata_en <= buf_state_en @[ahb_to_axi4.scala 143:22]
node _T_39 = bits(io.axi_rresp, 1, 0) @[ahb_to_axi4.scala 144:57]
node _T_40 = orr(_T_39) @[ahb_to_axi4.scala 144:64]
node _T_41 = and(buf_state_en, _T_40) @[ahb_to_axi4.scala 144:43]
buf_read_error_in <= _T_41 @[ahb_to_axi4.scala 144:27]
skip @[Conditional.scala 39:67]
node _T_42 = bits(buf_state_en, 0, 0) @[ahb_to_axi4.scala 147:101]
reg _T_43 : UInt, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_42 : @[Reg.scala 28:19]
_T_43 <= buf_nxtstate @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
buf_state <= _T_43 @[ahb_to_axi4.scala 147:33]
node _T_44 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 149:56]
node _T_45 = eq(_T_44, UInt<1>("h00")) @[ahb_to_axi4.scala 149:62]
node _T_46 = bits(_T_45, 0, 0) @[Bitwise.scala 72:15]
node _T_47 = mux(_T_46, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
node _T_48 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 149:94]
node _T_49 = dshl(UInt<1>("h01"), _T_48) @[ahb_to_axi4.scala 149:80]
node _T_50 = and(_T_47, _T_49) @[ahb_to_axi4.scala 149:72]
node _T_51 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 150:56]
node _T_52 = eq(_T_51, UInt<1>("h01")) @[ahb_to_axi4.scala 150:62]
node _T_53 = bits(_T_52, 0, 0) @[Bitwise.scala 72:15]
node _T_54 = mux(_T_53, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
node _T_55 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 150:94]
node _T_56 = dshl(UInt<2>("h03"), _T_55) @[ahb_to_axi4.scala 150:80]
node _T_57 = and(_T_54, _T_56) @[ahb_to_axi4.scala 150:72]
node _T_58 = or(_T_50, _T_57) @[ahb_to_axi4.scala 149:111]
node _T_59 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 151:56]
node _T_60 = eq(_T_59, UInt<2>("h02")) @[ahb_to_axi4.scala 151:62]
node _T_61 = bits(_T_60, 0, 0) @[Bitwise.scala 72:15]
node _T_62 = mux(_T_61, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
node _T_63 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 151:94]
node _T_64 = dshl(UInt<4>("h0f"), _T_63) @[ahb_to_axi4.scala 151:80]
node _T_65 = and(_T_62, _T_64) @[ahb_to_axi4.scala 151:72]
node _T_66 = or(_T_58, _T_65) @[ahb_to_axi4.scala 150:111]
node _T_67 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 152:56]
node _T_68 = eq(_T_67, UInt<2>("h03")) @[ahb_to_axi4.scala 152:62]
node _T_69 = bits(_T_68, 0, 0) @[Bitwise.scala 72:15]
node _T_70 = mux(_T_69, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
node _T_71 = and(_T_70, UInt<8>("h0ff")) @[ahb_to_axi4.scala 152:72]
node _T_72 = or(_T_66, _T_71) @[ahb_to_axi4.scala 151:111]
master_wstrb <= _T_72 @[ahb_to_axi4.scala 149:33]
node _T_73 = eq(ahb_hready_q, UInt<1>("h00")) @[ahb_to_axi4.scala 155:68]
node _T_74 = and(ahb_hresp_q, _T_73) @[ahb_to_axi4.scala 155:66]
node _T_75 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 155:86]
node _T_76 = eq(buf_state, UInt<2>("h00")) @[ahb_to_axi4.scala 155:112]
node _T_77 = or(_T_75, _T_76) @[ahb_to_axi4.scala 155:99]
node _T_78 = eq(buf_state, UInt<2>("h02")) @[ahb_to_axi4.scala 155:137]
node _T_79 = eq(buf_state, UInt<2>("h03")) @[ahb_to_axi4.scala 155:156]
node _T_80 = or(_T_78, _T_79) @[ahb_to_axi4.scala 155:144]
node _T_81 = eq(_T_80, UInt<1>("h00")) @[ahb_to_axi4.scala 155:125]
node _T_82 = and(_T_77, _T_81) @[ahb_to_axi4.scala 155:123]
node _T_83 = eq(buf_read_error, UInt<1>("h00")) @[ahb_to_axi4.scala 155:169]
node _T_84 = and(_T_82, _T_83) @[ahb_to_axi4.scala 155:167]
node _T_85 = mux(io.ahb_hresp, _T_74, _T_84) @[ahb_to_axi4.scala 155:39]
io.ahb_hreadyout <= _T_85 @[ahb_to_axi4.scala 155:33]
node _T_86 = and(io.ahb_hreadyout, io.ahb_hreadyin) @[ahb_to_axi4.scala 156:53]
ahb_hready <= _T_86 @[ahb_to_axi4.scala 156:33]
node _T_87 = bits(io.ahb_hsel, 0, 0) @[Bitwise.scala 72:15]
node _T_88 = mux(_T_87, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
node _T_89 = bits(io.ahb_htrans, 1, 0) @[ahb_to_axi4.scala 157:71]
node _T_90 = and(_T_88, _T_89) @[ahb_to_axi4.scala 157:56]
ahb_htrans_in <= _T_90 @[ahb_to_axi4.scala 157:33]
node _T_91 = bits(buf_rdata, 63, 0) @[ahb_to_axi4.scala 158:45]
io.ahb_hrdata <= _T_91 @[ahb_to_axi4.scala 158:33]
node _T_92 = bits(ahb_htrans_q, 1, 0) @[ahb_to_axi4.scala 159:50]
node _T_93 = neq(_T_92, UInt<1>("h00")) @[ahb_to_axi4.scala 159:56]
node _T_94 = neq(buf_state, UInt<2>("h00")) @[ahb_to_axi4.scala 159:78]
node _T_95 = and(_T_93, _T_94) @[ahb_to_axi4.scala 159:65]
node _T_96 = or(ahb_addr_in_dccm, ahb_addr_in_iccm) @[ahb_to_axi4.scala 160:57]
node _T_97 = eq(_T_96, UInt<1>("h00")) @[ahb_to_axi4.scala 160:38]
node _T_98 = and(ahb_addr_in_dccm, ahb_hwrite_q) @[ahb_to_axi4.scala 161:75]
node _T_99 = or(ahb_addr_in_iccm, _T_98) @[ahb_to_axi4.scala 161:55]
node _T_100 = bits(ahb_hsize_q, 1, 0) @[ahb_to_axi4.scala 161:109]
node _T_101 = eq(_T_100, UInt<2>("h02")) @[ahb_to_axi4.scala 161:115]
node _T_102 = bits(ahb_hsize_q, 1, 0) @[ahb_to_axi4.scala 161:138]
node _T_103 = eq(_T_102, UInt<2>("h03")) @[ahb_to_axi4.scala 161:144]
node _T_104 = or(_T_101, _T_103) @[ahb_to_axi4.scala 161:124]
node _T_105 = eq(_T_104, UInt<1>("h00")) @[ahb_to_axi4.scala 161:95]
node _T_106 = and(_T_99, _T_105) @[ahb_to_axi4.scala 161:93]
node _T_107 = or(_T_97, _T_106) @[ahb_to_axi4.scala 160:78]
node _T_108 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 162:49]
node _T_109 = eq(_T_108, UInt<1>("h01")) @[ahb_to_axi4.scala 162:55]
node _T_110 = bits(ahb_haddr_q, 0, 0) @[ahb_to_axi4.scala 162:77]
node _T_111 = and(_T_109, _T_110) @[ahb_to_axi4.scala 162:64]
node _T_112 = or(_T_107, _T_111) @[ahb_to_axi4.scala 161:155]
node _T_113 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 163:49]
node _T_114 = eq(_T_113, UInt<2>("h02")) @[ahb_to_axi4.scala 163:55]
node _T_115 = bits(ahb_haddr_q, 1, 0) @[ahb_to_axi4.scala 163:78]
node _T_116 = orr(_T_115) @[ahb_to_axi4.scala 163:85]
node _T_117 = and(_T_114, _T_116) @[ahb_to_axi4.scala 163:64]
node _T_118 = or(_T_112, _T_117) @[ahb_to_axi4.scala 162:84]
node _T_119 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 164:49]
node _T_120 = eq(_T_119, UInt<2>("h03")) @[ahb_to_axi4.scala 164:55]
node _T_121 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 164:78]
node _T_122 = orr(_T_121) @[ahb_to_axi4.scala 164:85]
node _T_123 = and(_T_120, _T_122) @[ahb_to_axi4.scala 164:64]
node _T_124 = or(_T_118, _T_123) @[ahb_to_axi4.scala 163:90]
node _T_125 = and(_T_95, _T_124) @[ahb_to_axi4.scala 159:89]
node _T_126 = or(_T_125, buf_read_error) @[ahb_to_axi4.scala 164:92]
node _T_127 = eq(ahb_hready_q, UInt<1>("h00")) @[ahb_to_axi4.scala 166:51]
node _T_128 = and(ahb_hresp_q, _T_127) @[ahb_to_axi4.scala 166:49]
node _T_129 = or(_T_126, _T_128) @[ahb_to_axi4.scala 165:51]
io.ahb_hresp <= _T_129 @[ahb_to_axi4.scala 159:33]
reg _T_130 : UInt, buf_rdata_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 169:68]
_T_130 <= io.axi_rdata @[ahb_to_axi4.scala 169:68]
buf_rdata <= _T_130 @[ahb_to_axi4.scala 169:33]
reg _T_131 : UInt<1>, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 170:62]
_T_131 <= buf_read_error_in @[ahb_to_axi4.scala 170:62]
buf_read_error <= _T_131 @[ahb_to_axi4.scala 170:33]
reg _T_132 : UInt<1>, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 173:62]
_T_132 <= io.ahb_hresp @[ahb_to_axi4.scala 173:62]
ahb_hresp_q <= _T_132 @[ahb_to_axi4.scala 173:33]
reg _T_133 : UInt<1>, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 174:62]
_T_133 <= ahb_hready @[ahb_to_axi4.scala 174:62]
ahb_hready_q <= _T_133 @[ahb_to_axi4.scala 174:33]
reg _T_134 : UInt, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 175:62]
_T_134 <= ahb_htrans_in @[ahb_to_axi4.scala 175:62]
ahb_htrans_q <= _T_134 @[ahb_to_axi4.scala 175:33]
reg _T_135 : UInt, ahb_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 176:67]
_T_135 <= io.ahb_hsize @[ahb_to_axi4.scala 176:67]
ahb_hsize_q <= _T_135 @[ahb_to_axi4.scala 176:33]
reg _T_136 : UInt<1>, ahb_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 177:67]
_T_136 <= io.ahb_hwrite @[ahb_to_axi4.scala 177:67]
ahb_hwrite_q <= _T_136 @[ahb_to_axi4.scala 177:33]
reg _T_137 : UInt, ahb_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 178:67]
_T_137 <= io.ahb_haddr @[ahb_to_axi4.scala 178:67]
ahb_haddr_q <= _T_137 @[ahb_to_axi4.scala 178:33]
node _T_138 = bits(io.ahb_htrans, 1, 1) @[ahb_to_axi4.scala 181:79]
node _T_139 = and(ahb_hready, _T_138) @[ahb_to_axi4.scala 181:64]
node _T_140 = and(io.bus_clk_en, _T_139) @[ahb_to_axi4.scala 181:50]
ahb_bus_addr_clk_en <= _T_140 @[ahb_to_axi4.scala 181:33]
node _T_141 = and(io.bus_clk_en, buf_rdata_en) @[ahb_to_axi4.scala 182:50]
buf_rdata_clk_en <= _T_141 @[ahb_to_axi4.scala 182:33]
inst rvclkhdr of rvclkhdr @[el2_lib.scala 483:22]
rvclkhdr.clock <= clock
rvclkhdr.reset <= reset
rvclkhdr.io.clk <= clock @[el2_lib.scala 484:17]
rvclkhdr.io.en <= io.bus_clk_en @[el2_lib.scala 485:16]
rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23]
ahb_clk <= rvclkhdr.io.l1clk @[ahb_to_axi4.scala 184:33]
inst rvclkhdr_1 of rvclkhdr_1 @[el2_lib.scala 483:22]
rvclkhdr_1.clock <= clock
rvclkhdr_1.reset <= reset
rvclkhdr_1.io.clk <= clock @[el2_lib.scala 484:17]
rvclkhdr_1.io.en <= ahb_bus_addr_clk_en @[el2_lib.scala 485:16]
rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23]
ahb_addr_clk <= rvclkhdr_1.io.l1clk @[ahb_to_axi4.scala 185:33]
inst rvclkhdr_2 of rvclkhdr_2 @[el2_lib.scala 483:22]
rvclkhdr_2.clock <= clock
rvclkhdr_2.reset <= reset
rvclkhdr_2.io.clk <= clock @[el2_lib.scala 484:17]
rvclkhdr_2.io.en <= buf_rdata_clk_en @[el2_lib.scala 485:16]
rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23]
buf_rdata_clk <= rvclkhdr_2.io.l1clk @[ahb_to_axi4.scala 186:33]
node _T_142 = and(io.axi_awvalid, io.axi_awready) @[ahb_to_axi4.scala 188:54]
node _T_143 = and(io.axi_arvalid, io.axi_arready) @[ahb_to_axi4.scala 188:90]
node _T_144 = or(_T_142, _T_143) @[ahb_to_axi4.scala 188:72]
node _T_145 = eq(cmdbuf_wr_en, UInt<1>("h00")) @[ahb_to_axi4.scala 188:111]
node _T_146 = and(_T_144, _T_145) @[ahb_to_axi4.scala 188:109]
node _T_147 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 188:144]
node _T_148 = and(io.ahb_hresp, _T_147) @[ahb_to_axi4.scala 188:142]
node _T_149 = or(_T_146, _T_148) @[ahb_to_axi4.scala 188:126]
cmdbuf_rst <= _T_149 @[ahb_to_axi4.scala 188:33]
node _T_150 = and(io.axi_awvalid, io.axi_awready) @[ahb_to_axi4.scala 189:68]
node _T_151 = and(io.axi_arvalid, io.axi_arready) @[ahb_to_axi4.scala 189:104]
node _T_152 = or(_T_150, _T_151) @[ahb_to_axi4.scala 189:86]
node _T_153 = eq(_T_152, UInt<1>("h00")) @[ahb_to_axi4.scala 189:50]
node _T_154 = and(cmdbuf_vld, _T_153) @[ahb_to_axi4.scala 189:48]
cmdbuf_full <= _T_154 @[ahb_to_axi4.scala 189:33]
node _T_155 = and(UInt<1>("h01"), cmdbuf_rst) @[ahb_to_axi4.scala 193:26]
node _T_156 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 193:87]
reg _T_157 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_156 : @[Reg.scala 28:19]
_T_157 <= _T_155 @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
cmdbuf_vld <= _T_157 @[ahb_to_axi4.scala 192:33]
node _T_158 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 197:57]
reg _T_159 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_158 : @[Reg.scala 28:19]
_T_159 <= ahb_hwrite_q @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
cmdbuf_write <= _T_159 @[ahb_to_axi4.scala 196:33]
node _T_160 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 200:56]
reg _T_161 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_160 : @[Reg.scala 28:19]
_T_161 <= ahb_hsize_q @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
cmdbuf_size <= _T_161 @[ahb_to_axi4.scala 199:33]
node _T_162 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 203:57]
reg _T_163 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_162 : @[Reg.scala 28:19]
_T_163 <= master_wstrb @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
cmdbuf_wstrb <= _T_163 @[ahb_to_axi4.scala 202:33]
node _T_164 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 206:67]
reg _T_165 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_164 : @[Reg.scala 28:19]
_T_165 <= ahb_haddr_q @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
cmdbuf_addr <= _T_165 @[ahb_to_axi4.scala 206:17]
node _T_166 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 207:70]
reg _T_167 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_166 : @[Reg.scala 28:19]
_T_167 <= io.ahb_hwdata @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
cmdbuf_wdata <= _T_167 @[ahb_to_axi4.scala 207:18]
node _T_168 = and(cmdbuf_vld, cmdbuf_write) @[ahb_to_axi4.scala 210:43]
io.axi_awvalid <= _T_168 @[ahb_to_axi4.scala 210:29]
io.axi_awid <= UInt<1>("h00") @[ahb_to_axi4.scala 211:29]
io.axi_awaddr <= cmdbuf_addr @[ahb_to_axi4.scala 212:29]
node _T_169 = bits(cmdbuf_size, 1, 0) @[ahb_to_axi4.scala 213:55]
node _T_170 = cat(UInt<1>("h00"), _T_169) @[Cat.scala 29:58]
io.axi_awsize <= _T_170 @[ahb_to_axi4.scala 213:29]
node _T_171 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
io.axi_awprot <= _T_171 @[ahb_to_axi4.scala 214:29]
node _T_172 = mux(UInt<1>("h00"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
io.axi_awlen <= _T_172 @[ahb_to_axi4.scala 215:29]
io.axi_awburst <= UInt<1>("h01") @[ahb_to_axi4.scala 216:29]
node _T_173 = and(cmdbuf_vld, cmdbuf_write) @[ahb_to_axi4.scala 218:43]
io.axi_wvalid <= _T_173 @[ahb_to_axi4.scala 218:29]
io.axi_wdata <= cmdbuf_wdata @[ahb_to_axi4.scala 219:29]
io.axi_wstrb <= cmdbuf_wstrb @[ahb_to_axi4.scala 220:29]
io.axi_wlast <= UInt<1>("h01") @[ahb_to_axi4.scala 221:29]
io.axi_bready <= UInt<1>("h01") @[ahb_to_axi4.scala 223:29]
node _T_174 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 225:45]
node _T_175 = and(cmdbuf_vld, _T_174) @[ahb_to_axi4.scala 225:43]
io.axi_arvalid <= _T_175 @[ahb_to_axi4.scala 225:29]
io.axi_arid <= UInt<1>("h00") @[ahb_to_axi4.scala 226:29]
io.axi_araddr <= cmdbuf_addr @[ahb_to_axi4.scala 227:29]
node _T_176 = bits(cmdbuf_size, 1, 0) @[ahb_to_axi4.scala 228:55]
node _T_177 = cat(UInt<1>("h00"), _T_176) @[Cat.scala 29:58]
io.axi_arsize <= _T_177 @[ahb_to_axi4.scala 228:29]
node _T_178 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
io.axi_arprot <= _T_178 @[ahb_to_axi4.scala 229:29]
node _T_179 = mux(UInt<1>("h00"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
io.axi_arlen <= _T_179 @[ahb_to_axi4.scala 230:29]
io.axi_arburst <= UInt<1>("h01") @[ahb_to_axi4.scala 231:29]
io.axi_rready <= UInt<1>("h01") @[ahb_to_axi4.scala 233:29]
inst rvclkhdr_3 of rvclkhdr_3 @[el2_lib.scala 483:22]
rvclkhdr_3.clock <= clock
rvclkhdr_3.reset <= reset
rvclkhdr_3.io.clk <= clock @[el2_lib.scala 484:17]
rvclkhdr_3.io.en <= io.bus_clk_en @[el2_lib.scala 485:16]
rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23]
bus_clk <= rvclkhdr_3.io.l1clk @[ahb_to_axi4.scala 236:29]

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module rvclkhdr(
output io_l1clk,
input io_clk,
input io_en,
input io_scan_mode
);
wire clkhdr_Q; // @[el2_lib.scala 474:26]
wire clkhdr_CK; // @[el2_lib.scala 474:26]
wire clkhdr_EN; // @[el2_lib.scala 474:26]
wire clkhdr_SE; // @[el2_lib.scala 474:26]
gated_latch clkhdr ( // @[el2_lib.scala 474:26]
.Q(clkhdr_Q),
.CK(clkhdr_CK),
.EN(clkhdr_EN),
.SE(clkhdr_SE)
);
assign io_l1clk = clkhdr_Q; // @[el2_lib.scala 475:14]
assign clkhdr_CK = io_clk; // @[el2_lib.scala 476:18]
assign clkhdr_EN = io_en; // @[el2_lib.scala 477:18]
assign clkhdr_SE = io_scan_mode; // @[el2_lib.scala 478:18]
endmodule
module ahb_to_axi4(
input clock,
input reset,
input io_scan_mode,
input io_bus_clk_en,
input io_clk_override,
input io_axi_awready,
input io_axi_wready,
input io_axi_bvalid,
input [1:0] io_axi_bresp,
input io_axi_arready,
input io_axi_rvalid,
input [63:0] io_axi_rdata,
input [1:0] io_axi_rresp,
input [31:0] io_ahb_haddr,
input [2:0] io_ahb_hburst,
input io_ahb_hmastlock,
input [3:0] io_ahb_hprot,
input [2:0] io_ahb_hsize,
input [1:0] io_ahb_htrans,
input io_ahb_hwrite,
input [63:0] io_ahb_hwdata,
input io_ahb_hsel,
input io_ahb_hreadyin,
output io_axi_awvalid,
output [31:0] io_axi_awaddr,
output [2:0] io_axi_awsize,
output [2:0] io_axi_awprot,
output [7:0] io_axi_awlen,
output [1:0] io_axi_awburst,
output io_axi_wvalid,
output [63:0] io_axi_wdata,
output [7:0] io_axi_wstrb,
output io_axi_wlast,
output io_axi_bready,
output io_axi_arvalid,
output [31:0] io_axi_araddr,
output [2:0] io_axi_arsize,
output [2:0] io_axi_arprot,
output [7:0] io_axi_arlen,
output [1:0] io_axi_arburst,
output io_axi_rready,
output [63:0] io_ahb_hrdata,
output io_ahb_hreadyout,
output io_ahb_hresp
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
reg [31:0] _RAND_2;
reg [31:0] _RAND_3;
reg [31:0] _RAND_4;
reg [31:0] _RAND_5;
reg [31:0] _RAND_6;
reg [31:0] _RAND_7;
reg [63:0] _RAND_8;
reg [31:0] _RAND_9;
reg [31:0] _RAND_10;
reg [31:0] _RAND_11;
reg [31:0] _RAND_12;
reg [31:0] _RAND_13;
reg [63:0] _RAND_14;
`endif // RANDOMIZE_REG_INIT
wire rvclkhdr_io_l1clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_io_clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_io_en; // @[el2_lib.scala 483:22]
wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 483:22]
wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_1_io_clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_1_io_en; // @[el2_lib.scala 483:22]
wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 483:22]
wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_2_io_clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_2_io_en; // @[el2_lib.scala 483:22]
wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 483:22]
wire rvclkhdr_3_io_l1clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_3_io_clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_3_io_en; // @[el2_lib.scala 483:22]
wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 483:22]
wire ahb_addr_clk = rvclkhdr_1_io_l1clk; // @[ahb_to_axi4.scala 85:35 ahb_to_axi4.scala 185:33]
reg [31:0] ahb_haddr_q; // @[ahb_to_axi4.scala 178:67]
wire ahb_addr_in_dccm = ahb_haddr_q[31:16] == 16'hf004; // @[el2_lib.scala 501:39]
wire ahb_clk = rvclkhdr_io_l1clk; // @[ahb_to_axi4.scala 84:35 ahb_to_axi4.scala 184:33]
reg [1:0] buf_state; // @[Reg.scala 27:20]
wire _T_6 = 2'h0 == buf_state; // @[Conditional.scala 37:30]
wire ahb_hready = io_ahb_hreadyout & io_ahb_hreadyin; // @[ahb_to_axi4.scala 156:53]
wire _T_9 = ahb_hready & io_ahb_htrans[1]; // @[ahb_to_axi4.scala 128:36]
wire _T_10 = _T_9 & io_ahb_hsel; // @[ahb_to_axi4.scala 128:55]
wire _T_11 = 2'h1 == buf_state; // @[Conditional.scala 37:30]
wire _T_13 = io_ahb_htrans == 2'h0; // @[ahb_to_axi4.scala 131:66]
wire _T_14 = io_ahb_hresp | _T_13; // @[ahb_to_axi4.scala 131:43]
wire _T_15 = ~io_ahb_hsel; // @[ahb_to_axi4.scala 131:80]
wire _T_16 = _T_14 | _T_15; // @[ahb_to_axi4.scala 131:78]
wire bus_clk = rvclkhdr_3_io_l1clk; // @[ahb_to_axi4.scala 98:35 ahb_to_axi4.scala 236:29]
reg cmdbuf_vld; // @[Reg.scala 27:20]
wire _T_150 = io_axi_awvalid & io_axi_awready; // @[ahb_to_axi4.scala 189:68]
wire _T_151 = io_axi_arvalid & io_axi_arready; // @[ahb_to_axi4.scala 189:104]
wire _T_152 = _T_150 | _T_151; // @[ahb_to_axi4.scala 189:86]
wire _T_153 = ~_T_152; // @[ahb_to_axi4.scala 189:50]
wire cmdbuf_full = cmdbuf_vld & _T_153; // @[ahb_to_axi4.scala 189:48]
wire _T_20 = ~cmdbuf_full; // @[ahb_to_axi4.scala 132:26]
wire _T_21 = _T_20 | io_ahb_hresp; // @[ahb_to_axi4.scala 132:39]
wire _T_24 = io_ahb_htrans == 2'h1; // @[ahb_to_axi4.scala 133:79]
wire _T_25 = _T_24 & io_ahb_hsel; // @[ahb_to_axi4.scala 133:92]
wire _T_26 = io_ahb_hresp | _T_25; // @[ahb_to_axi4.scala 133:55]
wire _T_27 = ~_T_26; // @[ahb_to_axi4.scala 133:40]
wire _T_28 = _T_20 & _T_27; // @[ahb_to_axi4.scala 133:38]
wire _T_29 = 2'h2 == buf_state; // @[Conditional.scala 37:30]
wire _T_33 = ~io_ahb_hresp; // @[ahb_to_axi4.scala 138:25]
wire _T_35 = _T_33 & _T_20; // @[ahb_to_axi4.scala 138:39]
wire _T_36 = 2'h3 == buf_state; // @[Conditional.scala 37:30]
reg cmdbuf_write; // @[Reg.scala 27:20]
wire _T_37 = ~cmdbuf_write; // @[ahb_to_axi4.scala 142:41]
wire _T_38 = io_axi_rvalid & _T_37; // @[ahb_to_axi4.scala 142:39]
wire _T_40 = |io_axi_rresp; // @[ahb_to_axi4.scala 144:64]
wire _GEN_1 = _T_36 & _T_38; // @[Conditional.scala 39:67]
wire _GEN_5 = _T_29 ? _T_21 : _GEN_1; // @[Conditional.scala 39:67]
wire _GEN_10 = _T_11 ? _T_21 : _GEN_5; // @[Conditional.scala 39:67]
wire buf_state_en = _T_6 ? _T_10 : _GEN_10; // @[Conditional.scala 40:58]
wire _T_41 = buf_state_en & _T_40; // @[ahb_to_axi4.scala 144:43]
wire _GEN_2 = _T_36 & buf_state_en; // @[Conditional.scala 39:67]
wire _GEN_3 = _T_36 & _T_41; // @[Conditional.scala 39:67]
wire _GEN_6 = _T_29 & _T_35; // @[Conditional.scala 39:67]
wire _GEN_7 = _T_29 ? 1'h0 : _GEN_2; // @[Conditional.scala 39:67]
wire _GEN_11 = _T_11 ? _T_28 : _GEN_6; // @[Conditional.scala 39:67]
wire _GEN_12 = _T_11 ? 1'h0 : _GEN_7; // @[Conditional.scala 39:67]
wire cmdbuf_wr_en = _T_6 ? 1'h0 : _GEN_11; // @[Conditional.scala 40:58]
wire buf_rdata_en = _T_6 ? 1'h0 : _GEN_12; // @[Conditional.scala 40:58]
reg [2:0] ahb_hsize_q; // @[ahb_to_axi4.scala 176:67]
wire _T_45 = ahb_hsize_q == 3'h0; // @[ahb_to_axi4.scala 149:62]
wire [7:0] _T_47 = _T_45 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
wire [7:0] _T_49 = 8'h1 << ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 149:80]
wire [7:0] _T_50 = _T_47 & _T_49; // @[ahb_to_axi4.scala 149:72]
wire _T_52 = ahb_hsize_q == 3'h1; // @[ahb_to_axi4.scala 150:62]
wire [7:0] _T_54 = _T_52 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
wire [8:0] _T_56 = 9'h3 << ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 150:80]
wire [8:0] _GEN_26 = {{1'd0}, _T_54}; // @[ahb_to_axi4.scala 150:72]
wire [8:0] _T_57 = _GEN_26 & _T_56; // @[ahb_to_axi4.scala 150:72]
wire [8:0] _GEN_27 = {{1'd0}, _T_50}; // @[ahb_to_axi4.scala 149:111]
wire [8:0] _T_58 = _GEN_27 | _T_57; // @[ahb_to_axi4.scala 149:111]
wire _T_60 = ahb_hsize_q == 3'h2; // @[ahb_to_axi4.scala 151:62]
wire [7:0] _T_62 = _T_60 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
wire [10:0] _T_64 = 11'hf << ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 151:80]
wire [10:0] _GEN_28 = {{3'd0}, _T_62}; // @[ahb_to_axi4.scala 151:72]
wire [10:0] _T_65 = _GEN_28 & _T_64; // @[ahb_to_axi4.scala 151:72]
wire [10:0] _GEN_29 = {{2'd0}, _T_58}; // @[ahb_to_axi4.scala 150:111]
wire [10:0] _T_66 = _GEN_29 | _T_65; // @[ahb_to_axi4.scala 150:111]
wire _T_68 = ahb_hsize_q == 3'h3; // @[ahb_to_axi4.scala 152:62]
wire [7:0] _T_70 = _T_68 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
wire [10:0] _GEN_30 = {{3'd0}, _T_70}; // @[ahb_to_axi4.scala 151:111]
wire [10:0] _T_72 = _T_66 | _GEN_30; // @[ahb_to_axi4.scala 151:111]
reg ahb_hready_q; // @[ahb_to_axi4.scala 174:62]
wire _T_73 = ~ahb_hready_q; // @[ahb_to_axi4.scala 155:68]
reg ahb_hresp_q; // @[ahb_to_axi4.scala 173:62]
wire _T_74 = ahb_hresp_q & _T_73; // @[ahb_to_axi4.scala 155:66]
wire _T_76 = buf_state == 2'h0; // @[ahb_to_axi4.scala 155:112]
wire _T_77 = _T_20 | _T_76; // @[ahb_to_axi4.scala 155:99]
wire _T_78 = buf_state == 2'h2; // @[ahb_to_axi4.scala 155:137]
wire _T_79 = buf_state == 2'h3; // @[ahb_to_axi4.scala 155:156]
wire _T_80 = _T_78 | _T_79; // @[ahb_to_axi4.scala 155:144]
wire _T_81 = ~_T_80; // @[ahb_to_axi4.scala 155:125]
wire _T_82 = _T_77 & _T_81; // @[ahb_to_axi4.scala 155:123]
reg buf_read_error; // @[ahb_to_axi4.scala 170:62]
wire _T_83 = ~buf_read_error; // @[ahb_to_axi4.scala 155:169]
wire _T_84 = _T_82 & _T_83; // @[ahb_to_axi4.scala 155:167]
wire [1:0] _T_88 = io_ahb_hsel ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire buf_rdata_clk = rvclkhdr_2_io_l1clk; // @[ahb_to_axi4.scala 86:35 ahb_to_axi4.scala 186:33]
reg [63:0] buf_rdata; // @[ahb_to_axi4.scala 169:68]
reg [1:0] ahb_htrans_q; // @[ahb_to_axi4.scala 175:62]
wire _T_93 = ahb_htrans_q != 2'h0; // @[ahb_to_axi4.scala 159:56]
wire _T_94 = buf_state != 2'h0; // @[ahb_to_axi4.scala 159:78]
wire _T_95 = _T_93 & _T_94; // @[ahb_to_axi4.scala 159:65]
wire _T_97 = ~ahb_addr_in_dccm; // @[ahb_to_axi4.scala 160:38]
reg ahb_hwrite_q; // @[ahb_to_axi4.scala 177:67]
wire _T_98 = ahb_addr_in_dccm & ahb_hwrite_q; // @[ahb_to_axi4.scala 161:75]
wire _T_101 = ahb_hsize_q[1:0] == 2'h2; // @[ahb_to_axi4.scala 161:115]
wire _T_103 = ahb_hsize_q[1:0] == 2'h3; // @[ahb_to_axi4.scala 161:144]
wire _T_104 = _T_101 | _T_103; // @[ahb_to_axi4.scala 161:124]
wire _T_105 = ~_T_104; // @[ahb_to_axi4.scala 161:95]
wire _T_106 = _T_98 & _T_105; // @[ahb_to_axi4.scala 161:93]
wire _T_107 = _T_97 | _T_106; // @[ahb_to_axi4.scala 160:78]
wire _T_111 = _T_52 & ahb_haddr_q[0]; // @[ahb_to_axi4.scala 162:64]
wire _T_112 = _T_107 | _T_111; // @[ahb_to_axi4.scala 161:155]
wire _T_116 = |ahb_haddr_q[1:0]; // @[ahb_to_axi4.scala 163:85]
wire _T_117 = _T_60 & _T_116; // @[ahb_to_axi4.scala 163:64]
wire _T_118 = _T_112 | _T_117; // @[ahb_to_axi4.scala 162:84]
wire _T_122 = |ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 164:85]
wire _T_123 = _T_68 & _T_122; // @[ahb_to_axi4.scala 164:64]
wire _T_124 = _T_118 | _T_123; // @[ahb_to_axi4.scala 163:90]
wire _T_125 = _T_95 & _T_124; // @[ahb_to_axi4.scala 159:89]
wire _T_126 = _T_125 | buf_read_error; // @[ahb_to_axi4.scala 164:92]
wire _T_145 = ~cmdbuf_wr_en; // @[ahb_to_axi4.scala 188:111]
wire _T_146 = _T_152 & _T_145; // @[ahb_to_axi4.scala 188:109]
wire _T_148 = io_ahb_hresp & _T_37; // @[ahb_to_axi4.scala 188:142]
wire cmdbuf_rst = _T_146 | _T_148; // @[ahb_to_axi4.scala 188:126]
reg [2:0] _T_161; // @[Reg.scala 27:20]
reg [7:0] cmdbuf_wstrb; // @[Reg.scala 27:20]
wire [7:0] master_wstrb = _T_72[7:0]; // @[ahb_to_axi4.scala 149:33]
reg [31:0] cmdbuf_addr; // @[Reg.scala 27:20]
reg [63:0] cmdbuf_wdata; // @[Reg.scala 27:20]
wire [1:0] cmdbuf_size = _T_161[1:0]; // @[ahb_to_axi4.scala 199:33]
rvclkhdr rvclkhdr ( // @[el2_lib.scala 483:22]
.io_l1clk(rvclkhdr_io_l1clk),
.io_clk(rvclkhdr_io_clk),
.io_en(rvclkhdr_io_en),
.io_scan_mode(rvclkhdr_io_scan_mode)
);
rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 483:22]
.io_l1clk(rvclkhdr_1_io_l1clk),
.io_clk(rvclkhdr_1_io_clk),
.io_en(rvclkhdr_1_io_en),
.io_scan_mode(rvclkhdr_1_io_scan_mode)
);
rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 483:22]
.io_l1clk(rvclkhdr_2_io_l1clk),
.io_clk(rvclkhdr_2_io_clk),
.io_en(rvclkhdr_2_io_en),
.io_scan_mode(rvclkhdr_2_io_scan_mode)
);
rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 483:22]
.io_l1clk(rvclkhdr_3_io_l1clk),
.io_clk(rvclkhdr_3_io_clk),
.io_en(rvclkhdr_3_io_en),
.io_scan_mode(rvclkhdr_3_io_scan_mode)
);
assign io_axi_awvalid = cmdbuf_vld & cmdbuf_write; // @[ahb_to_axi4.scala 210:29]
assign io_axi_awaddr = cmdbuf_addr; // @[ahb_to_axi4.scala 212:29]
assign io_axi_awsize = {1'h0,cmdbuf_size}; // @[ahb_to_axi4.scala 213:29]
assign io_axi_awprot = 3'h0; // @[ahb_to_axi4.scala 214:29]
assign io_axi_awlen = 8'h0; // @[ahb_to_axi4.scala 215:29]
assign io_axi_awburst = 2'h1; // @[ahb_to_axi4.scala 216:29]
assign io_axi_wvalid = cmdbuf_vld & cmdbuf_write; // @[ahb_to_axi4.scala 218:29]
assign io_axi_wdata = cmdbuf_wdata; // @[ahb_to_axi4.scala 219:29]
assign io_axi_wstrb = cmdbuf_wstrb; // @[ahb_to_axi4.scala 220:29]
assign io_axi_wlast = 1'h1; // @[ahb_to_axi4.scala 221:29]
assign io_axi_bready = 1'h1; // @[ahb_to_axi4.scala 223:29]
assign io_axi_arvalid = cmdbuf_vld & _T_37; // @[ahb_to_axi4.scala 225:29]
assign io_axi_araddr = cmdbuf_addr; // @[ahb_to_axi4.scala 227:29]
assign io_axi_arsize = {1'h0,cmdbuf_size}; // @[ahb_to_axi4.scala 228:29]
assign io_axi_arprot = 3'h0; // @[ahb_to_axi4.scala 229:29]
assign io_axi_arlen = 8'h0; // @[ahb_to_axi4.scala 230:29]
assign io_axi_arburst = 2'h1; // @[ahb_to_axi4.scala 231:29]
assign io_axi_rready = 1'h1; // @[ahb_to_axi4.scala 233:29]
assign io_ahb_hrdata = buf_rdata; // @[ahb_to_axi4.scala 158:33]
assign io_ahb_hreadyout = io_ahb_hresp ? _T_74 : _T_84; // @[ahb_to_axi4.scala 155:33]
assign io_ahb_hresp = _T_126 | _T_74; // @[ahb_to_axi4.scala 159:33]
assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 484:17]
assign rvclkhdr_io_en = io_bus_clk_en; // @[el2_lib.scala 485:16]
assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 484:17]
assign rvclkhdr_1_io_en = io_bus_clk_en & _T_9; // @[el2_lib.scala 485:16]
assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 484:17]
assign rvclkhdr_2_io_en = io_bus_clk_en & buf_rdata_en; // @[el2_lib.scala 485:16]
assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 484:17]
assign rvclkhdr_3_io_en = io_bus_clk_en; // @[el2_lib.scala 485:16]
assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
ahb_haddr_q = _RAND_0[31:0];
_RAND_1 = {1{`RANDOM}};
buf_state = _RAND_1[1:0];
_RAND_2 = {1{`RANDOM}};
cmdbuf_vld = _RAND_2[0:0];
_RAND_3 = {1{`RANDOM}};
cmdbuf_write = _RAND_3[0:0];
_RAND_4 = {1{`RANDOM}};
ahb_hsize_q = _RAND_4[2:0];
_RAND_5 = {1{`RANDOM}};
ahb_hready_q = _RAND_5[0:0];
_RAND_6 = {1{`RANDOM}};
ahb_hresp_q = _RAND_6[0:0];
_RAND_7 = {1{`RANDOM}};
buf_read_error = _RAND_7[0:0];
_RAND_8 = {2{`RANDOM}};
buf_rdata = _RAND_8[63:0];
_RAND_9 = {1{`RANDOM}};
ahb_htrans_q = _RAND_9[1:0];
_RAND_10 = {1{`RANDOM}};
ahb_hwrite_q = _RAND_10[0:0];
_RAND_11 = {1{`RANDOM}};
_T_161 = _RAND_11[2:0];
_RAND_12 = {1{`RANDOM}};
cmdbuf_wstrb = _RAND_12[7:0];
_RAND_13 = {1{`RANDOM}};
cmdbuf_addr = _RAND_13[31:0];
_RAND_14 = {2{`RANDOM}};
cmdbuf_wdata = _RAND_14[63:0];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
ahb_haddr_q = 32'h0;
end
if (reset) begin
buf_state = 2'h0;
end
if (reset) begin
cmdbuf_vld = 1'h0;
end
if (reset) begin
cmdbuf_write = 1'h0;
end
if (reset) begin
ahb_hsize_q = 3'h0;
end
if (reset) begin
ahb_hready_q = 1'h0;
end
if (reset) begin
ahb_hresp_q = 1'h0;
end
if (reset) begin
buf_read_error = 1'h0;
end
if (reset) begin
buf_rdata = 64'h0;
end
if (reset) begin
ahb_htrans_q = 2'h0;
end
if (reset) begin
ahb_hwrite_q = 1'h0;
end
if (reset) begin
_T_161 = 3'h0;
end
if (reset) begin
cmdbuf_wstrb = 8'h0;
end
if (reset) begin
cmdbuf_addr = 32'h0;
end
if (reset) begin
cmdbuf_wdata = 64'h0;
end
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge ahb_addr_clk or posedge reset) begin
if (reset) begin
ahb_haddr_q <= 32'h0;
end else begin
ahb_haddr_q <= io_ahb_haddr;
end
end
always @(posedge ahb_clk or posedge reset) begin
if (reset) begin
buf_state <= 2'h0;
end else if (buf_state_en) begin
if (_T_6) begin
if (io_ahb_hwrite) begin
buf_state <= 2'h1;
end else begin
buf_state <= 2'h2;
end
end else if (_T_11) begin
if (_T_16) begin
buf_state <= 2'h0;
end else if (io_ahb_hwrite) begin
buf_state <= 2'h1;
end else begin
buf_state <= 2'h2;
end
end else if (_T_29) begin
if (io_ahb_hresp) begin
buf_state <= 2'h0;
end else begin
buf_state <= 2'h3;
end
end else begin
buf_state <= 2'h0;
end
end
end
always @(posedge bus_clk or posedge reset) begin
if (reset) begin
cmdbuf_vld <= 1'h0;
end else if (cmdbuf_wr_en) begin
cmdbuf_vld <= cmdbuf_rst;
end
end
always @(posedge bus_clk or posedge reset) begin
if (reset) begin
cmdbuf_write <= 1'h0;
end else if (cmdbuf_wr_en) begin
cmdbuf_write <= ahb_hwrite_q;
end
end
always @(posedge ahb_addr_clk or posedge reset) begin
if (reset) begin
ahb_hsize_q <= 3'h0;
end else begin
ahb_hsize_q <= io_ahb_hsize;
end
end
always @(posedge ahb_clk or posedge reset) begin
if (reset) begin
ahb_hready_q <= 1'h0;
end else begin
ahb_hready_q <= io_ahb_hreadyout & io_ahb_hreadyin;
end
end
always @(posedge ahb_clk or posedge reset) begin
if (reset) begin
ahb_hresp_q <= 1'h0;
end else begin
ahb_hresp_q <= io_ahb_hresp;
end
end
always @(posedge ahb_clk or posedge reset) begin
if (reset) begin
buf_read_error <= 1'h0;
end else if (_T_6) begin
buf_read_error <= 1'h0;
end else if (_T_11) begin
buf_read_error <= 1'h0;
end else if (_T_29) begin
buf_read_error <= 1'h0;
end else begin
buf_read_error <= _GEN_3;
end
end
always @(posedge buf_rdata_clk or posedge reset) begin
if (reset) begin
buf_rdata <= 64'h0;
end else begin
buf_rdata <= io_axi_rdata;
end
end
always @(posedge ahb_clk or posedge reset) begin
if (reset) begin
ahb_htrans_q <= 2'h0;
end else begin
ahb_htrans_q <= _T_88 & io_ahb_htrans;
end
end
always @(posedge ahb_addr_clk or posedge reset) begin
if (reset) begin
ahb_hwrite_q <= 1'h0;
end else begin
ahb_hwrite_q <= io_ahb_hwrite;
end
end
always @(posedge bus_clk or posedge reset) begin
if (reset) begin
_T_161 <= 3'h0;
end else if (cmdbuf_wr_en) begin
_T_161 <= ahb_hsize_q;
end
end
always @(posedge bus_clk or posedge reset) begin
if (reset) begin
cmdbuf_wstrb <= 8'h0;
end else if (cmdbuf_wr_en) begin
cmdbuf_wstrb <= master_wstrb;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
cmdbuf_addr <= 32'h0;
end else if (cmdbuf_wr_en) begin
cmdbuf_addr <= ahb_haddr_q;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
cmdbuf_wdata <= 64'h0;
end else if (cmdbuf_wr_en) begin
cmdbuf_wdata <= io_ahb_hwdata;
end
end
endmodule

891
axi4_to_ahb.fir
View File

@ -482,7 +482,7 @@ circuit axi4_to_ahb :
rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23]
bus_write_clk <= rvclkhdr_1.io.l1clk @[axi4_to_ahb.scala 222:17] bus_write_clk <= rvclkhdr_1.io.l1clk @[axi4_to_ahb.scala 222:17]
io.ahb_htrans <= UInt<1>("h00") @[axi4_to_ahb.scala 225:17] io.ahb_htrans <= UInt<1>("h00") @[axi4_to_ahb.scala 225:17]
master_ready <= UInt<1>("h01") @[axi4_to_ahb.scala 226:16] master_ready <= UInt<1>("h00") @[axi4_to_ahb.scala 226:16]
buf_state_en <= UInt<1>("h00") @[axi4_to_ahb.scala 227:16] buf_state_en <= UInt<1>("h00") @[axi4_to_ahb.scala 227:16]
buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 228:18] buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 228:18]
buf_data_wr_en <= UInt<1>("h00") @[axi4_to_ahb.scala 230:18] buf_data_wr_en <= UInt<1>("h00") @[axi4_to_ahb.scala 230:18]
@ -514,7 +514,7 @@ circuit axi4_to_ahb :
buf_data_wr_en <= _T_54 @[axi4_to_ahb.scala 250:22] buf_data_wr_en <= _T_54 @[axi4_to_ahb.scala 250:22]
buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 251:27] buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 251:27]
node _T_55 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 253:50] node _T_55 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 253:50]
node _T_56 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 253:92] node _T_56 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 253:89]
node _T_57 = add(UInt<1>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 182:52] node _T_57 = add(UInt<1>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 182:52]
node _T_58 = tail(_T_57, 1) @[axi4_to_ahb.scala 182:52] node _T_58 = tail(_T_57, 1) @[axi4_to_ahb.scala 182:52]
node _T_59 = mux(UInt<1>("h00"), _T_58, UInt<1>("h00")) @[axi4_to_ahb.scala 182:24] node _T_59 = mux(UInt<1>("h00"), _T_58, UInt<1>("h00")) @[axi4_to_ahb.scala 182:24]
@ -550,7 +550,7 @@ circuit axi4_to_ahb :
node _T_89 = mux(_T_68, UInt<2>("h02"), _T_88) @[Mux.scala 98:16] node _T_89 = mux(_T_68, UInt<2>("h02"), _T_88) @[Mux.scala 98:16]
node _T_90 = mux(_T_65, UInt<1>("h01"), _T_89) @[Mux.scala 98:16] node _T_90 = mux(_T_65, UInt<1>("h01"), _T_89) @[Mux.scala 98:16]
node _T_91 = mux(_T_62, UInt<1>("h00"), _T_90) @[Mux.scala 98:16] node _T_91 = mux(_T_62, UInt<1>("h00"), _T_90) @[Mux.scala 98:16]
node _T_92 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 253:141] node _T_92 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 253:138]
node _T_93 = mux(_T_55, _T_91, _T_92) @[axi4_to_ahb.scala 253:30] node _T_93 = mux(_T_55, _T_91, _T_92) @[axi4_to_ahb.scala 253:30]
buf_cmd_byte_ptr <= _T_93 @[axi4_to_ahb.scala 253:24] buf_cmd_byte_ptr <= _T_93 @[axi4_to_ahb.scala 253:24]
bypass_en <= buf_state_en @[axi4_to_ahb.scala 254:17] bypass_en <= buf_state_en @[axi4_to_ahb.scala 254:17]
@ -902,87 +902,86 @@ circuit axi4_to_ahb :
trxn_done <= _T_364 @[axi4_to_ahb.scala 329:17] trxn_done <= _T_364 @[axi4_to_ahb.scala 329:17]
node _T_365 = or(trxn_done, bypass_en) @[axi4_to_ahb.scala 330:40] node _T_365 = or(trxn_done, bypass_en) @[axi4_to_ahb.scala 330:40]
buf_cmd_byte_ptr_en <= _T_365 @[axi4_to_ahb.scala 330:27] buf_cmd_byte_ptr_en <= _T_365 @[axi4_to_ahb.scala 330:27]
node _T_366 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] node _T_366 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 333:76]
node _T_367 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 333:85] node _T_367 = add(UInt<1>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 182:52]
node _T_368 = add(_T_366, UInt<1>("h01")) @[axi4_to_ahb.scala 182:52] node _T_368 = tail(_T_367, 1) @[axi4_to_ahb.scala 182:52]
node _T_369 = tail(_T_368, 1) @[axi4_to_ahb.scala 182:52] node _T_369 = mux(UInt<1>("h00"), _T_368, UInt<1>("h00")) @[axi4_to_ahb.scala 182:24]
node _T_370 = mux(UInt<1>("h00"), _T_369, _T_366) @[axi4_to_ahb.scala 182:24] node _T_370 = bits(_T_366, 0, 0) @[axi4_to_ahb.scala 183:44]
node _T_371 = bits(_T_367, 0, 0) @[axi4_to_ahb.scala 183:44] node _T_371 = geq(UInt<1>("h00"), _T_369) @[axi4_to_ahb.scala 183:62]
node _T_372 = geq(UInt<1>("h00"), _T_370) @[axi4_to_ahb.scala 183:62] node _T_372 = and(_T_370, _T_371) @[axi4_to_ahb.scala 183:48]
node _T_373 = and(_T_371, _T_372) @[axi4_to_ahb.scala 183:48] node _T_373 = bits(_T_366, 1, 1) @[axi4_to_ahb.scala 183:44]
node _T_374 = bits(_T_367, 1, 1) @[axi4_to_ahb.scala 183:44] node _T_374 = geq(UInt<1>("h01"), _T_369) @[axi4_to_ahb.scala 183:62]
node _T_375 = geq(UInt<1>("h01"), _T_370) @[axi4_to_ahb.scala 183:62] node _T_375 = and(_T_373, _T_374) @[axi4_to_ahb.scala 183:48]
node _T_376 = and(_T_374, _T_375) @[axi4_to_ahb.scala 183:48] node _T_376 = bits(_T_366, 2, 2) @[axi4_to_ahb.scala 183:44]
node _T_377 = bits(_T_367, 2, 2) @[axi4_to_ahb.scala 183:44] node _T_377 = geq(UInt<2>("h02"), _T_369) @[axi4_to_ahb.scala 183:62]
node _T_378 = geq(UInt<2>("h02"), _T_370) @[axi4_to_ahb.scala 183:62] node _T_378 = and(_T_376, _T_377) @[axi4_to_ahb.scala 183:48]
node _T_379 = and(_T_377, _T_378) @[axi4_to_ahb.scala 183:48] node _T_379 = bits(_T_366, 3, 3) @[axi4_to_ahb.scala 183:44]
node _T_380 = bits(_T_367, 3, 3) @[axi4_to_ahb.scala 183:44] node _T_380 = geq(UInt<2>("h03"), _T_369) @[axi4_to_ahb.scala 183:62]
node _T_381 = geq(UInt<2>("h03"), _T_370) @[axi4_to_ahb.scala 183:62] node _T_381 = and(_T_379, _T_380) @[axi4_to_ahb.scala 183:48]
node _T_382 = and(_T_380, _T_381) @[axi4_to_ahb.scala 183:48] node _T_382 = bits(_T_366, 4, 4) @[axi4_to_ahb.scala 183:44]
node _T_383 = bits(_T_367, 4, 4) @[axi4_to_ahb.scala 183:44] node _T_383 = geq(UInt<3>("h04"), _T_369) @[axi4_to_ahb.scala 183:62]
node _T_384 = geq(UInt<3>("h04"), _T_370) @[axi4_to_ahb.scala 183:62] node _T_384 = and(_T_382, _T_383) @[axi4_to_ahb.scala 183:48]
node _T_385 = and(_T_383, _T_384) @[axi4_to_ahb.scala 183:48] node _T_385 = bits(_T_366, 5, 5) @[axi4_to_ahb.scala 183:44]
node _T_386 = bits(_T_367, 5, 5) @[axi4_to_ahb.scala 183:44] node _T_386 = geq(UInt<3>("h05"), _T_369) @[axi4_to_ahb.scala 183:62]
node _T_387 = geq(UInt<3>("h05"), _T_370) @[axi4_to_ahb.scala 183:62] node _T_387 = and(_T_385, _T_386) @[axi4_to_ahb.scala 183:48]
node _T_388 = and(_T_386, _T_387) @[axi4_to_ahb.scala 183:48] node _T_388 = bits(_T_366, 6, 6) @[axi4_to_ahb.scala 183:44]
node _T_389 = bits(_T_367, 6, 6) @[axi4_to_ahb.scala 183:44] node _T_389 = geq(UInt<3>("h06"), _T_369) @[axi4_to_ahb.scala 183:62]
node _T_390 = geq(UInt<3>("h06"), _T_370) @[axi4_to_ahb.scala 183:62] node _T_390 = and(_T_388, _T_389) @[axi4_to_ahb.scala 183:48]
node _T_391 = and(_T_389, _T_390) @[axi4_to_ahb.scala 183:48] node _T_391 = bits(_T_366, 7, 7) @[axi4_to_ahb.scala 183:44]
node _T_392 = bits(_T_367, 7, 7) @[axi4_to_ahb.scala 183:44] node _T_392 = geq(UInt<3>("h07"), _T_369) @[axi4_to_ahb.scala 183:62]
node _T_393 = geq(UInt<3>("h07"), _T_370) @[axi4_to_ahb.scala 183:62] node _T_393 = and(_T_391, _T_392) @[axi4_to_ahb.scala 183:48]
node _T_394 = and(_T_392, _T_393) @[axi4_to_ahb.scala 183:48] node _T_394 = mux(_T_393, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 98:16]
node _T_395 = mux(_T_394, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 98:16] node _T_395 = mux(_T_390, UInt<3>("h06"), _T_394) @[Mux.scala 98:16]
node _T_396 = mux(_T_391, UInt<3>("h06"), _T_395) @[Mux.scala 98:16] node _T_396 = mux(_T_387, UInt<3>("h05"), _T_395) @[Mux.scala 98:16]
node _T_397 = mux(_T_388, UInt<3>("h05"), _T_396) @[Mux.scala 98:16] node _T_397 = mux(_T_384, UInt<3>("h04"), _T_396) @[Mux.scala 98:16]
node _T_398 = mux(_T_385, UInt<3>("h04"), _T_397) @[Mux.scala 98:16] node _T_398 = mux(_T_381, UInt<2>("h03"), _T_397) @[Mux.scala 98:16]
node _T_399 = mux(_T_382, UInt<2>("h03"), _T_398) @[Mux.scala 98:16] node _T_399 = mux(_T_378, UInt<2>("h02"), _T_398) @[Mux.scala 98:16]
node _T_400 = mux(_T_379, UInt<2>("h02"), _T_399) @[Mux.scala 98:16] node _T_400 = mux(_T_375, UInt<1>("h01"), _T_399) @[Mux.scala 98:16]
node _T_401 = mux(_T_376, UInt<1>("h01"), _T_400) @[Mux.scala 98:16] node _T_401 = mux(_T_372, UInt<1>("h00"), _T_400) @[Mux.scala 98:16]
node _T_402 = mux(_T_373, UInt<1>("h00"), _T_401) @[Mux.scala 98:16] node _T_402 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 333:142]
node _T_403 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 333:151] node _T_403 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 333:160]
node _T_404 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 333:169] node _T_404 = add(_T_402, UInt<1>("h01")) @[axi4_to_ahb.scala 182:52]
node _T_405 = add(_T_403, UInt<1>("h01")) @[axi4_to_ahb.scala 182:52] node _T_405 = tail(_T_404, 1) @[axi4_to_ahb.scala 182:52]
node _T_406 = tail(_T_405, 1) @[axi4_to_ahb.scala 182:52] node _T_406 = mux(UInt<1>("h01"), _T_405, _T_402) @[axi4_to_ahb.scala 182:24]
node _T_407 = mux(UInt<1>("h01"), _T_406, _T_403) @[axi4_to_ahb.scala 182:24] node _T_407 = bits(_T_403, 0, 0) @[axi4_to_ahb.scala 183:44]
node _T_408 = bits(_T_404, 0, 0) @[axi4_to_ahb.scala 183:44] node _T_408 = geq(UInt<1>("h00"), _T_406) @[axi4_to_ahb.scala 183:62]
node _T_409 = geq(UInt<1>("h00"), _T_407) @[axi4_to_ahb.scala 183:62] node _T_409 = and(_T_407, _T_408) @[axi4_to_ahb.scala 183:48]
node _T_410 = and(_T_408, _T_409) @[axi4_to_ahb.scala 183:48] node _T_410 = bits(_T_403, 1, 1) @[axi4_to_ahb.scala 183:44]
node _T_411 = bits(_T_404, 1, 1) @[axi4_to_ahb.scala 183:44] node _T_411 = geq(UInt<1>("h01"), _T_406) @[axi4_to_ahb.scala 183:62]
node _T_412 = geq(UInt<1>("h01"), _T_407) @[axi4_to_ahb.scala 183:62] node _T_412 = and(_T_410, _T_411) @[axi4_to_ahb.scala 183:48]
node _T_413 = and(_T_411, _T_412) @[axi4_to_ahb.scala 183:48] node _T_413 = bits(_T_403, 2, 2) @[axi4_to_ahb.scala 183:44]
node _T_414 = bits(_T_404, 2, 2) @[axi4_to_ahb.scala 183:44] node _T_414 = geq(UInt<2>("h02"), _T_406) @[axi4_to_ahb.scala 183:62]
node _T_415 = geq(UInt<2>("h02"), _T_407) @[axi4_to_ahb.scala 183:62] node _T_415 = and(_T_413, _T_414) @[axi4_to_ahb.scala 183:48]
node _T_416 = and(_T_414, _T_415) @[axi4_to_ahb.scala 183:48] node _T_416 = bits(_T_403, 3, 3) @[axi4_to_ahb.scala 183:44]
node _T_417 = bits(_T_404, 3, 3) @[axi4_to_ahb.scala 183:44] node _T_417 = geq(UInt<2>("h03"), _T_406) @[axi4_to_ahb.scala 183:62]
node _T_418 = geq(UInt<2>("h03"), _T_407) @[axi4_to_ahb.scala 183:62] node _T_418 = and(_T_416, _T_417) @[axi4_to_ahb.scala 183:48]
node _T_419 = and(_T_417, _T_418) @[axi4_to_ahb.scala 183:48] node _T_419 = bits(_T_403, 4, 4) @[axi4_to_ahb.scala 183:44]
node _T_420 = bits(_T_404, 4, 4) @[axi4_to_ahb.scala 183:44] node _T_420 = geq(UInt<3>("h04"), _T_406) @[axi4_to_ahb.scala 183:62]
node _T_421 = geq(UInt<3>("h04"), _T_407) @[axi4_to_ahb.scala 183:62] node _T_421 = and(_T_419, _T_420) @[axi4_to_ahb.scala 183:48]
node _T_422 = and(_T_420, _T_421) @[axi4_to_ahb.scala 183:48] node _T_422 = bits(_T_403, 5, 5) @[axi4_to_ahb.scala 183:44]
node _T_423 = bits(_T_404, 5, 5) @[axi4_to_ahb.scala 183:44] node _T_423 = geq(UInt<3>("h05"), _T_406) @[axi4_to_ahb.scala 183:62]
node _T_424 = geq(UInt<3>("h05"), _T_407) @[axi4_to_ahb.scala 183:62] node _T_424 = and(_T_422, _T_423) @[axi4_to_ahb.scala 183:48]
node _T_425 = and(_T_423, _T_424) @[axi4_to_ahb.scala 183:48] node _T_425 = bits(_T_403, 6, 6) @[axi4_to_ahb.scala 183:44]
node _T_426 = bits(_T_404, 6, 6) @[axi4_to_ahb.scala 183:44] node _T_426 = geq(UInt<3>("h06"), _T_406) @[axi4_to_ahb.scala 183:62]
node _T_427 = geq(UInt<3>("h06"), _T_407) @[axi4_to_ahb.scala 183:62] node _T_427 = and(_T_425, _T_426) @[axi4_to_ahb.scala 183:48]
node _T_428 = and(_T_426, _T_427) @[axi4_to_ahb.scala 183:48] node _T_428 = bits(_T_403, 7, 7) @[axi4_to_ahb.scala 183:44]
node _T_429 = bits(_T_404, 7, 7) @[axi4_to_ahb.scala 183:44] node _T_429 = geq(UInt<3>("h07"), _T_406) @[axi4_to_ahb.scala 183:62]
node _T_430 = geq(UInt<3>("h07"), _T_407) @[axi4_to_ahb.scala 183:62] node _T_430 = and(_T_428, _T_429) @[axi4_to_ahb.scala 183:48]
node _T_431 = and(_T_429, _T_430) @[axi4_to_ahb.scala 183:48] node _T_431 = mux(_T_430, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 98:16]
node _T_432 = mux(_T_431, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 98:16] node _T_432 = mux(_T_427, UInt<3>("h06"), _T_431) @[Mux.scala 98:16]
node _T_433 = mux(_T_428, UInt<3>("h06"), _T_432) @[Mux.scala 98:16] node _T_433 = mux(_T_424, UInt<3>("h05"), _T_432) @[Mux.scala 98:16]
node _T_434 = mux(_T_425, UInt<3>("h05"), _T_433) @[Mux.scala 98:16] node _T_434 = mux(_T_421, UInt<3>("h04"), _T_433) @[Mux.scala 98:16]
node _T_435 = mux(_T_422, UInt<3>("h04"), _T_434) @[Mux.scala 98:16] node _T_435 = mux(_T_418, UInt<2>("h03"), _T_434) @[Mux.scala 98:16]
node _T_436 = mux(_T_419, UInt<2>("h03"), _T_435) @[Mux.scala 98:16] node _T_436 = mux(_T_415, UInt<2>("h02"), _T_435) @[Mux.scala 98:16]
node _T_437 = mux(_T_416, UInt<2>("h02"), _T_436) @[Mux.scala 98:16] node _T_437 = mux(_T_412, UInt<1>("h01"), _T_436) @[Mux.scala 98:16]
node _T_438 = mux(_T_413, UInt<1>("h01"), _T_437) @[Mux.scala 98:16] node _T_438 = mux(_T_409, UInt<1>("h00"), _T_437) @[Mux.scala 98:16]
node _T_439 = mux(_T_410, UInt<1>("h00"), _T_438) @[Mux.scala 98:16] node _T_439 = mux(trxn_done, _T_438, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 333:97]
node _T_440 = mux(trxn_done, _T_439, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 333:106] node _T_440 = mux(bypass_en, _T_401, _T_439) @[axi4_to_ahb.scala 333:30]
node _T_441 = mux(bypass_en, _T_402, _T_440) @[axi4_to_ahb.scala 333:30] buf_cmd_byte_ptr <= _T_440 @[axi4_to_ahb.scala 333:24]
buf_cmd_byte_ptr <= _T_441 @[axi4_to_ahb.scala 333:24]
skip @[Conditional.scala 39:67] skip @[Conditional.scala 39:67]
else : @[Conditional.scala 39:67] else : @[Conditional.scala 39:67]
node _T_442 = eq(UInt<3>("h05"), buf_state) @[Conditional.scala 37:30] node _T_441 = eq(UInt<3>("h05"), buf_state) @[Conditional.scala 37:30]
when _T_442 : @[Conditional.scala 39:67] when _T_441 : @[Conditional.scala 39:67]
buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 336:20] buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 336:20]
buf_state_en <= slave_ready @[axi4_to_ahb.scala 337:20] buf_state_en <= slave_ready @[axi4_to_ahb.scala 337:20]
slvbuf_error_en <= UInt<1>("h01") @[axi4_to_ahb.scala 338:23] slvbuf_error_en <= UInt<1>("h01") @[axi4_to_ahb.scala 338:23]
@ -990,407 +989,407 @@ circuit axi4_to_ahb :
skip @[Conditional.scala 39:67] skip @[Conditional.scala 39:67]
buf_rst <= UInt<1>("h00") @[axi4_to_ahb.scala 343:11] buf_rst <= UInt<1>("h00") @[axi4_to_ahb.scala 343:11]
cmd_done_rst <= slave_valid_pre @[axi4_to_ahb.scala 344:16] cmd_done_rst <= slave_valid_pre @[axi4_to_ahb.scala 344:16]
node _T_443 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 345:33] node _T_442 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 345:33]
node _T_444 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 345:73] node _T_443 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 345:73]
node _T_445 = eq(_T_444, UInt<1>("h01")) @[axi4_to_ahb.scala 345:80] node _T_444 = eq(_T_443, UInt<1>("h01")) @[axi4_to_ahb.scala 345:80]
node _T_446 = and(buf_aligned_in, _T_445) @[axi4_to_ahb.scala 345:60] node _T_445 = and(buf_aligned_in, _T_444) @[axi4_to_ahb.scala 345:60]
node _T_447 = bits(_T_446, 0, 0) @[axi4_to_ahb.scala 345:100] node _T_446 = bits(_T_445, 0, 0) @[axi4_to_ahb.scala 345:100]
node _T_448 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 345:132] node _T_447 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 345:132]
wire _T_449 : UInt<8> wire _T_448 : UInt<8>
_T_449 <= UInt<8>("h00") _T_448 <= UInt<8>("h00")
node _T_450 = bits(_T_449, 7, 0) @[axi4_to_ahb.scala 174:44] node _T_449 = bits(_T_448, 7, 0) @[axi4_to_ahb.scala 174:44]
node _T_451 = eq(_T_450, UInt<8>("h0ff")) @[axi4_to_ahb.scala 174:51] node _T_450 = eq(_T_449, UInt<8>("h0ff")) @[axi4_to_ahb.scala 174:51]
node _T_452 = bits(_T_449, 7, 0) @[axi4_to_ahb.scala 174:75] node _T_451 = bits(_T_448, 7, 0) @[axi4_to_ahb.scala 174:75]
node _T_453 = eq(_T_452, UInt<4>("h0f")) @[axi4_to_ahb.scala 174:82] node _T_452 = eq(_T_451, UInt<4>("h0f")) @[axi4_to_ahb.scala 174:82]
node _T_454 = or(_T_451, _T_453) @[axi4_to_ahb.scala 174:64] node _T_453 = or(_T_450, _T_452) @[axi4_to_ahb.scala 174:64]
node _T_455 = bits(_T_449, 7, 0) @[axi4_to_ahb.scala 174:106] node _T_454 = bits(_T_448, 7, 0) @[axi4_to_ahb.scala 174:106]
node _T_456 = eq(_T_455, UInt<2>("h03")) @[axi4_to_ahb.scala 174:113] node _T_455 = eq(_T_454, UInt<2>("h03")) @[axi4_to_ahb.scala 174:113]
node _T_457 = or(_T_454, _T_456) @[axi4_to_ahb.scala 174:95] node _T_456 = or(_T_453, _T_455) @[axi4_to_ahb.scala 174:95]
node _T_458 = bits(_T_457, 0, 0) @[Bitwise.scala 72:15] node _T_457 = bits(_T_456, 0, 0) @[Bitwise.scala 72:15]
node _T_459 = mux(_T_458, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] node _T_458 = mux(_T_457, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
node _T_460 = and(UInt<1>("h00"), _T_459) @[axi4_to_ahb.scala 174:24] node _T_459 = and(UInt<1>("h00"), _T_458) @[axi4_to_ahb.scala 174:24]
node _T_461 = bits(_T_449, 7, 0) @[axi4_to_ahb.scala 175:35] node _T_460 = bits(_T_448, 7, 0) @[axi4_to_ahb.scala 175:35]
node _T_462 = eq(_T_461, UInt<4>("h0c")) @[axi4_to_ahb.scala 175:42] node _T_461 = eq(_T_460, UInt<4>("h0c")) @[axi4_to_ahb.scala 175:42]
node _T_463 = bits(_T_462, 0, 0) @[Bitwise.scala 72:15] node _T_462 = bits(_T_461, 0, 0) @[Bitwise.scala 72:15]
node _T_464 = mux(_T_463, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] node _T_463 = mux(_T_462, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
node _T_465 = and(UInt<2>("h02"), _T_464) @[axi4_to_ahb.scala 175:15] node _T_464 = and(UInt<2>("h02"), _T_463) @[axi4_to_ahb.scala 175:15]
node _T_466 = or(_T_460, _T_465) @[axi4_to_ahb.scala 174:128] node _T_465 = or(_T_459, _T_464) @[axi4_to_ahb.scala 174:128]
node _T_467 = bits(_T_449, 7, 0) @[axi4_to_ahb.scala 176:36] node _T_466 = bits(_T_448, 7, 0) @[axi4_to_ahb.scala 176:36]
node _T_468 = eq(_T_467, UInt<8>("h0f0")) @[axi4_to_ahb.scala 176:43] node _T_467 = eq(_T_466, UInt<8>("h0f0")) @[axi4_to_ahb.scala 176:43]
node _T_469 = bits(_T_449, 7, 0) @[axi4_to_ahb.scala 176:67] node _T_468 = bits(_T_448, 7, 0) @[axi4_to_ahb.scala 176:67]
node _T_470 = eq(_T_469, UInt<2>("h03")) @[axi4_to_ahb.scala 176:74] node _T_469 = eq(_T_468, UInt<2>("h03")) @[axi4_to_ahb.scala 176:74]
node _T_471 = or(_T_468, _T_470) @[axi4_to_ahb.scala 176:56] node _T_470 = or(_T_467, _T_469) @[axi4_to_ahb.scala 176:56]
node _T_472 = bits(_T_471, 0, 0) @[Bitwise.scala 72:15] node _T_471 = bits(_T_470, 0, 0) @[Bitwise.scala 72:15]
node _T_473 = mux(_T_472, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] node _T_472 = mux(_T_471, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
node _T_474 = and(UInt<3>("h04"), _T_473) @[axi4_to_ahb.scala 176:15] node _T_473 = and(UInt<3>("h04"), _T_472) @[axi4_to_ahb.scala 176:15]
node _T_475 = bits(_T_449, 7, 0) @[axi4_to_ahb.scala 177:37] node _T_474 = bits(_T_448, 7, 0) @[axi4_to_ahb.scala 177:37]
node _T_476 = eq(_T_475, UInt<8>("h0c0")) @[axi4_to_ahb.scala 177:44] node _T_475 = eq(_T_474, UInt<8>("h0c0")) @[axi4_to_ahb.scala 177:44]
node _T_477 = bits(_T_476, 0, 0) @[Bitwise.scala 72:15] node _T_476 = bits(_T_475, 0, 0) @[Bitwise.scala 72:15]
node _T_478 = mux(_T_477, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] node _T_477 = mux(_T_476, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
node _T_479 = and(UInt<3>("h06"), _T_478) @[axi4_to_ahb.scala 177:17] node _T_478 = and(UInt<3>("h06"), _T_477) @[axi4_to_ahb.scala 177:17]
node _T_480 = or(_T_474, _T_479) @[axi4_to_ahb.scala 176:90] node _T_479 = or(_T_473, _T_478) @[axi4_to_ahb.scala 176:90]
node _T_481 = or(_T_466, _T_480) @[axi4_to_ahb.scala 175:58] node _T_480 = or(_T_465, _T_479) @[axi4_to_ahb.scala 175:58]
node _T_482 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 345:152] node _T_481 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 345:152]
node _T_483 = mux(_T_447, _T_481, _T_482) @[axi4_to_ahb.scala 345:43] node _T_482 = mux(_T_446, _T_480, _T_481) @[axi4_to_ahb.scala 345:43]
node _T_484 = cat(_T_443, _T_483) @[Cat.scala 29:58] node _T_483 = cat(_T_442, _T_482) @[Cat.scala 29:58]
buf_addr_in <= _T_484 @[axi4_to_ahb.scala 345:15] buf_addr_in <= _T_483 @[axi4_to_ahb.scala 345:15]
node _T_485 = bits(master_tag, 0, 0) @[axi4_to_ahb.scala 346:27] node _T_484 = bits(master_tag, 0, 0) @[axi4_to_ahb.scala 346:27]
buf_tag_in <= _T_485 @[axi4_to_ahb.scala 346:14] buf_tag_in <= _T_484 @[axi4_to_ahb.scala 346:14]
node _T_486 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 347:32] node _T_485 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 347:32]
buf_byteen_in <= _T_486 @[axi4_to_ahb.scala 347:17] buf_byteen_in <= _T_485 @[axi4_to_ahb.scala 347:17]
node _T_487 = eq(buf_state, UInt<3>("h03")) @[axi4_to_ahb.scala 348:33] node _T_486 = eq(buf_state, UInt<3>("h03")) @[axi4_to_ahb.scala 348:33]
node _T_488 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 348:59] node _T_487 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 348:59]
node _T_489 = bits(master_wdata, 63, 0) @[axi4_to_ahb.scala 348:80] node _T_488 = bits(master_wdata, 63, 0) @[axi4_to_ahb.scala 348:80]
node _T_490 = mux(_T_487, _T_488, _T_489) @[axi4_to_ahb.scala 348:21] node _T_489 = mux(_T_486, _T_487, _T_488) @[axi4_to_ahb.scala 348:21]
buf_data_in <= _T_490 @[axi4_to_ahb.scala 348:15] buf_data_in <= _T_489 @[axi4_to_ahb.scala 348:15]
node _T_491 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 349:52] node _T_490 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 349:52]
node _T_492 = eq(_T_491, UInt<2>("h03")) @[axi4_to_ahb.scala 349:59] node _T_491 = eq(_T_490, UInt<2>("h03")) @[axi4_to_ahb.scala 349:59]
node _T_493 = and(buf_aligned_in, _T_492) @[axi4_to_ahb.scala 349:38] node _T_492 = and(buf_aligned_in, _T_491) @[axi4_to_ahb.scala 349:38]
node _T_494 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 349:85] node _T_493 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 349:85]
node _T_495 = eq(_T_494, UInt<1>("h01")) @[axi4_to_ahb.scala 349:92] node _T_494 = eq(_T_493, UInt<1>("h01")) @[axi4_to_ahb.scala 349:92]
node _T_496 = and(_T_493, _T_495) @[axi4_to_ahb.scala 349:72] node _T_495 = and(_T_492, _T_494) @[axi4_to_ahb.scala 349:72]
node _T_497 = bits(_T_496, 0, 0) @[axi4_to_ahb.scala 349:112] node _T_496 = bits(_T_495, 0, 0) @[axi4_to_ahb.scala 349:112]
node _T_498 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 349:144] node _T_497 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 349:144]
wire _T_499 : UInt<8> wire _T_498 : UInt<8>
_T_499 <= UInt<8>("h00") _T_498 <= UInt<8>("h00")
node _T_500 = bits(_T_499, 7, 0) @[axi4_to_ahb.scala 166:43] node _T_499 = bits(_T_498, 7, 0) @[axi4_to_ahb.scala 166:42]
node _T_501 = eq(_T_500, UInt<8>("h0ff")) @[axi4_to_ahb.scala 166:50] node _T_500 = eq(_T_499, UInt<8>("h0ff")) @[axi4_to_ahb.scala 166:49]
node _T_502 = bits(_T_501, 0, 0) @[Bitwise.scala 72:15] node _T_501 = bits(_T_500, 0, 0) @[Bitwise.scala 72:15]
node _T_503 = mux(_T_502, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] node _T_502 = mux(_T_501, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
node _T_504 = and(UInt<2>("h03"), _T_503) @[axi4_to_ahb.scala 166:25] node _T_503 = and(UInt<2>("h03"), _T_502) @[axi4_to_ahb.scala 166:25]
node _T_505 = bits(_T_499, 7, 0) @[axi4_to_ahb.scala 167:34] node _T_504 = bits(_T_498, 7, 0) @[axi4_to_ahb.scala 167:35]
node _T_506 = eq(_T_505, UInt<8>("h0f0")) @[axi4_to_ahb.scala 167:41] node _T_505 = eq(_T_504, UInt<8>("h0f0")) @[axi4_to_ahb.scala 167:42]
node _T_507 = bits(_T_499, 7, 0) @[axi4_to_ahb.scala 167:63] node _T_506 = bits(_T_498, 7, 0) @[axi4_to_ahb.scala 167:64]
node _T_508 = eq(_T_507, UInt<4>("h0f")) @[axi4_to_ahb.scala 167:70] node _T_507 = eq(_T_506, UInt<4>("h0f")) @[axi4_to_ahb.scala 167:71]
node _T_509 = or(_T_506, _T_508) @[axi4_to_ahb.scala 167:54] node _T_508 = or(_T_505, _T_507) @[axi4_to_ahb.scala 167:55]
node _T_510 = bits(_T_509, 0, 0) @[Bitwise.scala 72:15] node _T_509 = bits(_T_508, 0, 0) @[Bitwise.scala 72:15]
node _T_511 = mux(_T_510, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] node _T_510 = mux(_T_509, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
node _T_512 = and(UInt<2>("h02"), _T_511) @[axi4_to_ahb.scala 167:16] node _T_511 = and(UInt<2>("h02"), _T_510) @[axi4_to_ahb.scala 167:16]
node _T_513 = or(_T_504, _T_512) @[axi4_to_ahb.scala 166:65] node _T_512 = or(_T_503, _T_511) @[axi4_to_ahb.scala 166:64]
node _T_514 = bits(_T_499, 7, 0) @[axi4_to_ahb.scala 168:34] node _T_513 = bits(_T_498, 7, 0) @[axi4_to_ahb.scala 168:35]
node _T_515 = eq(_T_514, UInt<8>("h0c0")) @[axi4_to_ahb.scala 168:41] node _T_514 = eq(_T_513, UInt<8>("h0c0")) @[axi4_to_ahb.scala 168:42]
node _T_516 = bits(_T_499, 7, 0) @[axi4_to_ahb.scala 168:63] node _T_515 = bits(_T_498, 7, 0) @[axi4_to_ahb.scala 168:64]
node _T_517 = eq(_T_516, UInt<6>("h030")) @[axi4_to_ahb.scala 168:70] node _T_516 = eq(_T_515, UInt<6>("h030")) @[axi4_to_ahb.scala 168:71]
node _T_518 = or(_T_515, _T_517) @[axi4_to_ahb.scala 168:54] node _T_517 = or(_T_514, _T_516) @[axi4_to_ahb.scala 168:55]
node _T_519 = bits(_T_499, 7, 0) @[axi4_to_ahb.scala 168:92] node _T_518 = bits(_T_498, 7, 0) @[axi4_to_ahb.scala 168:93]
node _T_520 = eq(_T_519, UInt<4>("h0c")) @[axi4_to_ahb.scala 168:99] node _T_519 = eq(_T_518, UInt<4>("h0c")) @[axi4_to_ahb.scala 168:100]
node _T_521 = or(_T_518, _T_520) @[axi4_to_ahb.scala 168:83] node _T_520 = or(_T_517, _T_519) @[axi4_to_ahb.scala 168:84]
node _T_522 = bits(_T_499, 7, 0) @[axi4_to_ahb.scala 168:121] node _T_521 = bits(_T_498, 7, 0) @[axi4_to_ahb.scala 168:122]
node _T_523 = eq(_T_522, UInt<2>("h03")) @[axi4_to_ahb.scala 168:128] node _T_522 = eq(_T_521, UInt<2>("h03")) @[axi4_to_ahb.scala 168:129]
node _T_524 = or(_T_521, _T_523) @[axi4_to_ahb.scala 168:112] node _T_523 = or(_T_520, _T_522) @[axi4_to_ahb.scala 168:113]
node _T_525 = bits(_T_524, 0, 0) @[Bitwise.scala 72:15] node _T_524 = bits(_T_523, 0, 0) @[Bitwise.scala 72:15]
node _T_526 = mux(_T_525, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] node _T_525 = mux(_T_524, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
node _T_527 = and(UInt<1>("h01"), _T_526) @[axi4_to_ahb.scala 168:16] node _T_526 = and(UInt<1>("h01"), _T_525) @[axi4_to_ahb.scala 168:16]
node _T_528 = or(_T_513, _T_527) @[axi4_to_ahb.scala 167:86] node _T_527 = or(_T_512, _T_526) @[axi4_to_ahb.scala 167:88]
node _T_529 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 349:164] node _T_528 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 349:164]
node _T_530 = mux(_T_497, _T_528, _T_529) @[axi4_to_ahb.scala 349:21] node _T_529 = mux(_T_496, _T_527, _T_528) @[axi4_to_ahb.scala 349:21]
buf_size_in <= _T_530 @[axi4_to_ahb.scala 349:15] buf_size_in <= _T_529 @[axi4_to_ahb.scala 349:15]
node _T_531 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 350:32] node _T_530 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 350:32]
node _T_532 = eq(_T_531, UInt<1>("h00")) @[axi4_to_ahb.scala 350:39] node _T_531 = eq(_T_530, UInt<1>("h00")) @[axi4_to_ahb.scala 350:39]
node _T_533 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 351:17] node _T_532 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 351:17]
node _T_534 = eq(_T_533, UInt<1>("h00")) @[axi4_to_ahb.scala 351:24] node _T_533 = eq(_T_532, UInt<1>("h00")) @[axi4_to_ahb.scala 351:24]
node _T_535 = or(_T_532, _T_534) @[axi4_to_ahb.scala 350:51] node _T_534 = or(_T_531, _T_533) @[axi4_to_ahb.scala 350:51]
node _T_536 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 351:50] node _T_535 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 351:50]
node _T_537 = eq(_T_536, UInt<1>("h01")) @[axi4_to_ahb.scala 351:57] node _T_536 = eq(_T_535, UInt<1>("h01")) @[axi4_to_ahb.scala 351:57]
node _T_538 = or(_T_535, _T_537) @[axi4_to_ahb.scala 351:36] node _T_537 = or(_T_534, _T_536) @[axi4_to_ahb.scala 351:36]
node _T_539 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 351:84] node _T_538 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 351:84]
node _T_540 = eq(_T_539, UInt<2>("h02")) @[axi4_to_ahb.scala 351:91] node _T_539 = eq(_T_538, UInt<2>("h02")) @[axi4_to_ahb.scala 351:91]
node _T_541 = or(_T_538, _T_540) @[axi4_to_ahb.scala 351:70] node _T_540 = or(_T_537, _T_539) @[axi4_to_ahb.scala 351:70]
node _T_542 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 352:18] node _T_541 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 352:18]
node _T_543 = eq(_T_542, UInt<2>("h03")) @[axi4_to_ahb.scala 352:25] node _T_542 = eq(_T_541, UInt<2>("h03")) @[axi4_to_ahb.scala 352:25]
node _T_544 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 352:55] node _T_543 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 352:55]
node _T_545 = eq(_T_544, UInt<2>("h03")) @[axi4_to_ahb.scala 352:62] node _T_544 = eq(_T_543, UInt<2>("h03")) @[axi4_to_ahb.scala 352:62]
node _T_546 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 352:90] node _T_545 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 352:90]
node _T_547 = eq(_T_546, UInt<4>("h0c")) @[axi4_to_ahb.scala 352:97] node _T_546 = eq(_T_545, UInt<4>("h0c")) @[axi4_to_ahb.scala 352:97]
node _T_548 = or(_T_545, _T_547) @[axi4_to_ahb.scala 352:74] node _T_547 = or(_T_544, _T_546) @[axi4_to_ahb.scala 352:74]
node _T_549 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 352:125] node _T_548 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 352:125]
node _T_550 = eq(_T_549, UInt<6>("h030")) @[axi4_to_ahb.scala 352:132] node _T_549 = eq(_T_548, UInt<6>("h030")) @[axi4_to_ahb.scala 352:132]
node _T_551 = or(_T_548, _T_550) @[axi4_to_ahb.scala 352:109] node _T_550 = or(_T_547, _T_549) @[axi4_to_ahb.scala 352:109]
node _T_552 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 352:161] node _T_551 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 352:161]
node _T_553 = eq(_T_552, UInt<8>("h0c0")) @[axi4_to_ahb.scala 352:168] node _T_552 = eq(_T_551, UInt<8>("h0c0")) @[axi4_to_ahb.scala 352:168]
node _T_554 = or(_T_551, _T_553) @[axi4_to_ahb.scala 352:145] node _T_553 = or(_T_550, _T_552) @[axi4_to_ahb.scala 352:145]
node _T_555 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 353:21] node _T_554 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 353:21]
node _T_556 = eq(_T_555, UInt<4>("h0f")) @[axi4_to_ahb.scala 353:28] node _T_555 = eq(_T_554, UInt<4>("h0f")) @[axi4_to_ahb.scala 353:28]
node _T_557 = or(_T_554, _T_556) @[axi4_to_ahb.scala 352:181] node _T_556 = or(_T_553, _T_555) @[axi4_to_ahb.scala 352:181]
node _T_558 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 353:56] node _T_557 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 353:56]
node _T_559 = eq(_T_558, UInt<8>("h0f0")) @[axi4_to_ahb.scala 353:63] node _T_558 = eq(_T_557, UInt<8>("h0f0")) @[axi4_to_ahb.scala 353:63]
node _T_560 = or(_T_557, _T_559) @[axi4_to_ahb.scala 353:40] node _T_559 = or(_T_556, _T_558) @[axi4_to_ahb.scala 353:40]
node _T_561 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 353:92] node _T_560 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 353:92]
node _T_562 = eq(_T_561, UInt<8>("h0ff")) @[axi4_to_ahb.scala 353:99] node _T_561 = eq(_T_560, UInt<8>("h0ff")) @[axi4_to_ahb.scala 353:99]
node _T_563 = or(_T_560, _T_562) @[axi4_to_ahb.scala 353:76] node _T_562 = or(_T_559, _T_561) @[axi4_to_ahb.scala 353:76]
node _T_564 = and(_T_543, _T_563) @[axi4_to_ahb.scala 352:38] node _T_563 = and(_T_542, _T_562) @[axi4_to_ahb.scala 352:38]
node _T_565 = or(_T_541, _T_564) @[axi4_to_ahb.scala 351:104] node _T_564 = or(_T_540, _T_563) @[axi4_to_ahb.scala 351:104]
buf_aligned_in <= _T_565 @[axi4_to_ahb.scala 350:18] buf_aligned_in <= _T_564 @[axi4_to_ahb.scala 350:18]
node _T_566 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 355:39] node _T_565 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 355:39]
node _T_567 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 355:58] node _T_566 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 355:58]
node _T_568 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 355:83] node _T_567 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 355:83]
node _T_569 = cat(_T_567, _T_568) @[Cat.scala 29:58] node _T_568 = cat(_T_566, _T_567) @[Cat.scala 29:58]
node _T_570 = bits(buf_addr, 31, 3) @[axi4_to_ahb.scala 355:104] node _T_569 = bits(buf_addr, 31, 3) @[axi4_to_ahb.scala 355:104]
node _T_571 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 355:129] node _T_570 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 355:129]
node _T_572 = cat(_T_570, _T_571) @[Cat.scala 29:58] node _T_571 = cat(_T_569, _T_570) @[Cat.scala 29:58]
node _T_573 = mux(_T_566, _T_569, _T_572) @[axi4_to_ahb.scala 355:22] node _T_572 = mux(_T_565, _T_568, _T_571) @[axi4_to_ahb.scala 355:22]
io.ahb_haddr <= _T_573 @[axi4_to_ahb.scala 355:16] io.ahb_haddr <= _T_572 @[axi4_to_ahb.scala 355:16]
node _T_574 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 356:39] node _T_573 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 356:39]
node _T_575 = bits(buf_aligned_in, 0, 0) @[Bitwise.scala 72:15] node _T_574 = bits(buf_aligned_in, 0, 0) @[Bitwise.scala 72:15]
node _T_576 = mux(_T_575, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] node _T_575 = mux(_T_574, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
node _T_577 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 356:93] node _T_576 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 356:90]
node _T_578 = and(_T_576, _T_577) @[axi4_to_ahb.scala 356:80] node _T_577 = and(_T_575, _T_576) @[axi4_to_ahb.scala 356:77]
node _T_579 = cat(UInt<1>("h00"), _T_578) @[Cat.scala 29:58] node _T_578 = cat(UInt<1>("h00"), _T_577) @[Cat.scala 29:58]
node _T_580 = bits(buf_aligned, 0, 0) @[Bitwise.scala 72:15] node _T_579 = bits(buf_aligned, 0, 0) @[Bitwise.scala 72:15]
node _T_581 = mux(_T_580, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] node _T_580 = mux(_T_579, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
node _T_582 = bits(buf_size, 1, 0) @[axi4_to_ahb.scala 356:148] node _T_581 = bits(buf_size, 1, 0) @[axi4_to_ahb.scala 356:145]
node _T_583 = and(_T_581, _T_582) @[axi4_to_ahb.scala 356:138] node _T_582 = and(_T_580, _T_581) @[axi4_to_ahb.scala 356:135]
node _T_584 = cat(UInt<1>("h00"), _T_583) @[Cat.scala 29:58] node _T_583 = cat(UInt<1>("h00"), _T_582) @[Cat.scala 29:58]
node _T_585 = mux(_T_574, _T_579, _T_584) @[axi4_to_ahb.scala 356:22] node _T_584 = mux(_T_573, _T_578, _T_583) @[axi4_to_ahb.scala 356:22]
io.ahb_hsize <= _T_585 @[axi4_to_ahb.scala 356:16] io.ahb_hsize <= _T_584 @[axi4_to_ahb.scala 356:16]
io.ahb_hburst <= UInt<1>("h00") @[axi4_to_ahb.scala 358:17] io.ahb_hburst <= UInt<1>("h00") @[axi4_to_ahb.scala 358:17]
io.ahb_hmastlock <= UInt<1>("h00") @[axi4_to_ahb.scala 359:20] io.ahb_hmastlock <= UInt<1>("h00") @[axi4_to_ahb.scala 359:20]
node _T_586 = bits(io.axi_arprot, 2, 2) @[axi4_to_ahb.scala 360:47] node _T_585 = bits(io.axi_arprot, 2, 2) @[axi4_to_ahb.scala 360:47]
node _T_587 = not(_T_586) @[axi4_to_ahb.scala 360:33] node _T_586 = not(_T_585) @[axi4_to_ahb.scala 360:33]
node _T_588 = cat(UInt<1>("h01"), _T_587) @[Cat.scala 29:58] node _T_587 = cat(UInt<1>("h01"), _T_586) @[Cat.scala 29:58]
io.ahb_hprot <= _T_588 @[axi4_to_ahb.scala 360:16] io.ahb_hprot <= _T_587 @[axi4_to_ahb.scala 360:16]
node _T_589 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 361:40] node _T_588 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 361:40]
node _T_590 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 361:55] node _T_589 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 361:55]
node _T_591 = eq(_T_590, UInt<1>("h01")) @[axi4_to_ahb.scala 361:62] node _T_590 = eq(_T_589, UInt<1>("h01")) @[axi4_to_ahb.scala 361:62]
node _T_592 = mux(_T_589, _T_591, buf_write) @[axi4_to_ahb.scala 361:23] node _T_591 = mux(_T_588, _T_590, buf_write) @[axi4_to_ahb.scala 361:23]
io.ahb_hwrite <= _T_592 @[axi4_to_ahb.scala 361:17] io.ahb_hwrite <= _T_591 @[axi4_to_ahb.scala 361:17]
node _T_593 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 362:28] node _T_592 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 362:28]
io.ahb_hwdata <= _T_593 @[axi4_to_ahb.scala 362:17] io.ahb_hwdata <= _T_592 @[axi4_to_ahb.scala 362:17]
slave_valid <= slave_valid_pre @[axi4_to_ahb.scala 364:15] slave_valid <= slave_valid_pre @[axi4_to_ahb.scala 364:15]
node _T_594 = bits(slvbuf_write, 0, 0) @[axi4_to_ahb.scala 365:43] node _T_593 = bits(slvbuf_write, 0, 0) @[axi4_to_ahb.scala 365:43]
node _T_595 = mux(_T_594, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 365:23] node _T_594 = mux(_T_593, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 365:23]
node _T_596 = bits(slvbuf_error, 0, 0) @[Bitwise.scala 72:15] node _T_595 = bits(slvbuf_error, 0, 0) @[Bitwise.scala 72:15]
node _T_597 = mux(_T_596, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] node _T_596 = mux(_T_595, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
node _T_598 = and(_T_597, UInt<2>("h02")) @[axi4_to_ahb.scala 365:88] node _T_597 = and(_T_596, UInt<2>("h02")) @[axi4_to_ahb.scala 365:88]
node _T_599 = cat(_T_595, _T_598) @[Cat.scala 29:58] node _T_598 = cat(_T_594, _T_597) @[Cat.scala 29:58]
slave_opc <= _T_599 @[axi4_to_ahb.scala 365:13] slave_opc <= _T_598 @[axi4_to_ahb.scala 365:13]
node _T_600 = bits(slvbuf_error, 0, 0) @[axi4_to_ahb.scala 366:41] node _T_599 = bits(slvbuf_error, 0, 0) @[axi4_to_ahb.scala 366:41]
node _T_601 = bits(last_bus_addr, 31, 0) @[axi4_to_ahb.scala 366:66] node _T_600 = bits(last_bus_addr, 31, 0) @[axi4_to_ahb.scala 366:66]
node _T_602 = cat(_T_601, _T_601) @[Cat.scala 29:58] node _T_601 = cat(_T_600, _T_600) @[Cat.scala 29:58]
node _T_603 = eq(buf_state, UInt<3>("h05")) @[axi4_to_ahb.scala 366:91] node _T_602 = eq(buf_state, UInt<3>("h05")) @[axi4_to_ahb.scala 366:91]
node _T_604 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 366:110] node _T_603 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 366:110]
node _T_605 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 366:131] node _T_604 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 366:131]
node _T_606 = mux(_T_603, _T_604, _T_605) @[axi4_to_ahb.scala 366:79] node _T_605 = mux(_T_602, _T_603, _T_604) @[axi4_to_ahb.scala 366:79]
node _T_607 = mux(_T_600, _T_602, _T_606) @[axi4_to_ahb.scala 366:21] node _T_606 = mux(_T_599, _T_601, _T_605) @[axi4_to_ahb.scala 366:21]
slave_rdata <= _T_607 @[axi4_to_ahb.scala 366:15] slave_rdata <= _T_606 @[axi4_to_ahb.scala 366:15]
node _T_608 = bits(slvbuf_tag, 0, 0) @[axi4_to_ahb.scala 367:26] node _T_607 = bits(slvbuf_tag, 0, 0) @[axi4_to_ahb.scala 367:26]
slave_tag <= _T_608 @[axi4_to_ahb.scala 367:13] slave_tag <= _T_607 @[axi4_to_ahb.scala 367:13]
node _T_609 = bits(io.ahb_htrans, 1, 0) @[axi4_to_ahb.scala 369:33] node _T_608 = bits(io.ahb_htrans, 1, 0) @[axi4_to_ahb.scala 369:33]
node _T_610 = neq(_T_609, UInt<1>("h00")) @[axi4_to_ahb.scala 369:40] node _T_609 = neq(_T_608, UInt<1>("h00")) @[axi4_to_ahb.scala 369:40]
node _T_611 = and(_T_610, io.ahb_hready) @[axi4_to_ahb.scala 369:52] node _T_610 = and(_T_609, io.ahb_hready) @[axi4_to_ahb.scala 369:52]
node _T_612 = and(_T_611, io.ahb_hwrite) @[axi4_to_ahb.scala 369:68] node _T_611 = and(_T_610, io.ahb_hwrite) @[axi4_to_ahb.scala 369:68]
last_addr_en <= _T_612 @[axi4_to_ahb.scala 369:16] last_addr_en <= _T_611 @[axi4_to_ahb.scala 369:16]
node _T_613 = and(io.axi_awvalid, io.axi_awready) @[axi4_to_ahb.scala 371:30] node _T_612 = and(io.axi_awvalid, io.axi_awready) @[axi4_to_ahb.scala 371:30]
node _T_614 = and(_T_613, master_ready) @[axi4_to_ahb.scala 371:47] node _T_613 = and(_T_612, master_ready) @[axi4_to_ahb.scala 371:47]
wrbuf_en <= _T_614 @[axi4_to_ahb.scala 371:12] wrbuf_en <= _T_613 @[axi4_to_ahb.scala 371:12]
node _T_615 = and(io.axi_wvalid, io.axi_wready) @[axi4_to_ahb.scala 372:34] node _T_614 = and(io.axi_wvalid, io.axi_wready) @[axi4_to_ahb.scala 372:34]
node _T_616 = and(_T_615, master_ready) @[axi4_to_ahb.scala 372:50] node _T_615 = and(_T_614, master_ready) @[axi4_to_ahb.scala 372:50]
wrbuf_data_en <= _T_616 @[axi4_to_ahb.scala 372:17] wrbuf_data_en <= _T_615 @[axi4_to_ahb.scala 372:17]
node _T_617 = and(master_valid, master_ready) @[axi4_to_ahb.scala 373:34] node _T_616 = and(master_valid, master_ready) @[axi4_to_ahb.scala 373:34]
node _T_618 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 373:62] node _T_617 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 373:62]
node _T_619 = eq(_T_618, UInt<1>("h01")) @[axi4_to_ahb.scala 373:69] node _T_618 = eq(_T_617, UInt<1>("h01")) @[axi4_to_ahb.scala 373:69]
node _T_620 = and(_T_617, _T_619) @[axi4_to_ahb.scala 373:49] node _T_619 = and(_T_616, _T_618) @[axi4_to_ahb.scala 373:49]
wrbuf_cmd_sent <= _T_620 @[axi4_to_ahb.scala 373:18] wrbuf_cmd_sent <= _T_619 @[axi4_to_ahb.scala 373:18]
node _T_621 = eq(wrbuf_en, UInt<1>("h00")) @[axi4_to_ahb.scala 374:33] node _T_620 = eq(wrbuf_en, UInt<1>("h00")) @[axi4_to_ahb.scala 374:33]
node _T_622 = and(wrbuf_cmd_sent, _T_621) @[axi4_to_ahb.scala 374:31] node _T_621 = and(wrbuf_cmd_sent, _T_620) @[axi4_to_ahb.scala 374:31]
wrbuf_rst <= _T_622 @[axi4_to_ahb.scala 374:13] wrbuf_rst <= _T_621 @[axi4_to_ahb.scala 374:13]
node _T_623 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 376:35] node _T_622 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 376:35]
node _T_624 = and(wrbuf_vld, _T_623) @[axi4_to_ahb.scala 376:33] node _T_623 = and(wrbuf_vld, _T_622) @[axi4_to_ahb.scala 376:33]
node _T_625 = eq(_T_624, UInt<1>("h00")) @[axi4_to_ahb.scala 376:21] node _T_624 = eq(_T_623, UInt<1>("h00")) @[axi4_to_ahb.scala 376:21]
node _T_626 = and(_T_625, master_ready) @[axi4_to_ahb.scala 376:52] node _T_625 = and(_T_624, master_ready) @[axi4_to_ahb.scala 376:52]
io.axi_awready <= _T_626 @[axi4_to_ahb.scala 376:18] io.axi_awready <= _T_625 @[axi4_to_ahb.scala 376:18]
node _T_627 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 377:39] node _T_626 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 377:39]
node _T_628 = and(wrbuf_data_vld, _T_627) @[axi4_to_ahb.scala 377:37] node _T_627 = and(wrbuf_data_vld, _T_626) @[axi4_to_ahb.scala 377:37]
node _T_629 = eq(_T_628, UInt<1>("h00")) @[axi4_to_ahb.scala 377:20] node _T_628 = eq(_T_627, UInt<1>("h00")) @[axi4_to_ahb.scala 377:20]
node _T_630 = and(_T_629, master_ready) @[axi4_to_ahb.scala 377:56] node _T_629 = and(_T_628, master_ready) @[axi4_to_ahb.scala 377:56]
io.axi_wready <= _T_630 @[axi4_to_ahb.scala 377:17] io.axi_wready <= _T_629 @[axi4_to_ahb.scala 377:17]
node _T_631 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 378:33] node _T_630 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 378:33]
node _T_632 = eq(_T_631, UInt<1>("h00")) @[axi4_to_ahb.scala 378:21] node _T_631 = eq(_T_630, UInt<1>("h00")) @[axi4_to_ahb.scala 378:21]
node _T_633 = and(_T_632, master_ready) @[axi4_to_ahb.scala 378:51] node _T_632 = and(_T_631, master_ready) @[axi4_to_ahb.scala 378:51]
io.axi_arready <= _T_633 @[axi4_to_ahb.scala 378:18] io.axi_arready <= _T_632 @[axi4_to_ahb.scala 378:18]
io.axi_rlast <= UInt<1>("h01") @[axi4_to_ahb.scala 379:16] io.axi_rlast <= UInt<1>("h01") @[axi4_to_ahb.scala 379:16]
node _T_634 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 382:68] node _T_633 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 382:68]
node _T_635 = mux(_T_634, UInt<1>("h01"), wrbuf_vld) @[axi4_to_ahb.scala 382:52] node _T_634 = mux(_T_633, UInt<1>("h01"), wrbuf_vld) @[axi4_to_ahb.scala 382:52]
node _T_636 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 382:88] node _T_635 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 382:88]
node _T_637 = and(_T_635, _T_636) @[axi4_to_ahb.scala 382:86] node _T_636 = and(_T_634, _T_635) @[axi4_to_ahb.scala 382:86]
reg _T_638 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 382:48] reg _T_637 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 382:48]
_T_638 <= _T_637 @[axi4_to_ahb.scala 382:48] _T_637 <= _T_636 @[axi4_to_ahb.scala 382:48]
wrbuf_vld <= _T_638 @[axi4_to_ahb.scala 382:18] wrbuf_vld <= _T_637 @[axi4_to_ahb.scala 382:18]
node _T_639 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 383:73] node _T_638 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 383:73]
node _T_640 = mux(_T_639, UInt<1>("h01"), wrbuf_data_vld) @[axi4_to_ahb.scala 383:52] node _T_639 = mux(_T_638, UInt<1>("h01"), wrbuf_data_vld) @[axi4_to_ahb.scala 383:52]
node _T_641 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 383:99] node _T_640 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 383:99]
node _T_642 = and(_T_640, _T_641) @[axi4_to_ahb.scala 383:97] node _T_641 = and(_T_639, _T_640) @[axi4_to_ahb.scala 383:97]
reg _T_643 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 383:48] reg _T_642 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 383:48]
_T_643 <= _T_642 @[axi4_to_ahb.scala 383:48] _T_642 <= _T_641 @[axi4_to_ahb.scala 383:48]
wrbuf_data_vld <= _T_643 @[axi4_to_ahb.scala 383:18] wrbuf_data_vld <= _T_642 @[axi4_to_ahb.scala 383:18]
node _T_644 = bits(io.axi_awid, 0, 0) @[axi4_to_ahb.scala 385:57] node _T_643 = bits(io.axi_awid, 0, 0) @[axi4_to_ahb.scala 385:57]
node _T_645 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 385:91] node _T_644 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 385:91]
reg _T_646 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] reg _T_645 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_645 : @[Reg.scala 28:19] when _T_644 : @[Reg.scala 28:19]
_T_646 <= _T_644 @[Reg.scala 28:23] _T_645 <= _T_643 @[Reg.scala 28:23]
skip @[Reg.scala 28:19] skip @[Reg.scala 28:19]
wrbuf_tag <= _T_646 @[axi4_to_ahb.scala 385:13] wrbuf_tag <= _T_645 @[axi4_to_ahb.scala 385:13]
node _T_647 = bits(io.axi_awsize, 2, 0) @[axi4_to_ahb.scala 386:60] node _T_646 = bits(io.axi_awsize, 2, 0) @[axi4_to_ahb.scala 386:60]
node _T_648 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 386:88] node _T_647 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 386:88]
reg _T_649 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] reg _T_648 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_648 : @[Reg.scala 28:19] when _T_647 : @[Reg.scala 28:19]
_T_649 <= _T_647 @[Reg.scala 28:23] _T_648 <= _T_646 @[Reg.scala 28:23]
skip @[Reg.scala 28:19] skip @[Reg.scala 28:19]
wrbuf_size <= _T_649 @[axi4_to_ahb.scala 386:14] wrbuf_size <= _T_648 @[axi4_to_ahb.scala 386:14]
node _T_650 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 388:48] node _T_649 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 388:48]
inst rvclkhdr_2 of rvclkhdr_2 @[el2_lib.scala 508:23] inst rvclkhdr_2 of rvclkhdr_2 @[el2_lib.scala 508:23]
rvclkhdr_2.clock <= clock rvclkhdr_2.clock <= clock
rvclkhdr_2.reset <= reset rvclkhdr_2.reset <= reset
rvclkhdr_2.io.clk <= bus_clk @[el2_lib.scala 510:18] rvclkhdr_2.io.clk <= bus_clk @[el2_lib.scala 510:18]
rvclkhdr_2.io.en <= _T_650 @[el2_lib.scala 511:17] rvclkhdr_2.io.en <= _T_649 @[el2_lib.scala 511:17]
rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
reg _T_651 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] reg _T_650 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
_T_651 <= io.axi_awaddr @[el2_lib.scala 514:16] _T_650 <= io.axi_awaddr @[el2_lib.scala 514:16]
wrbuf_addr <= _T_651 @[axi4_to_ahb.scala 388:14] wrbuf_addr <= _T_650 @[axi4_to_ahb.scala 388:14]
node _T_652 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 389:52] node _T_651 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 389:52]
inst rvclkhdr_3 of rvclkhdr_3 @[el2_lib.scala 508:23] inst rvclkhdr_3 of rvclkhdr_3 @[el2_lib.scala 508:23]
rvclkhdr_3.clock <= clock rvclkhdr_3.clock <= clock
rvclkhdr_3.reset <= reset rvclkhdr_3.reset <= reset
rvclkhdr_3.io.clk <= bus_clk @[el2_lib.scala 510:18] rvclkhdr_3.io.clk <= bus_clk @[el2_lib.scala 510:18]
rvclkhdr_3.io.en <= _T_652 @[el2_lib.scala 511:17] rvclkhdr_3.io.en <= _T_651 @[el2_lib.scala 511:17]
rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
reg _T_653 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] reg _T_652 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
_T_653 <= io.axi_wdata @[el2_lib.scala 514:16] _T_652 <= io.axi_wdata @[el2_lib.scala 514:16]
wrbuf_data <= _T_653 @[axi4_to_ahb.scala 389:14] wrbuf_data <= _T_652 @[axi4_to_ahb.scala 389:14]
node _T_654 = bits(io.axi_wstrb, 7, 0) @[axi4_to_ahb.scala 392:27] node _T_653 = bits(io.axi_wstrb, 7, 0) @[axi4_to_ahb.scala 392:27]
node _T_655 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 392:60] node _T_654 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 392:60]
reg _T_656 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] reg _T_655 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_655 : @[Reg.scala 28:19] when _T_654 : @[Reg.scala 28:19]
_T_656 <= _T_654 @[Reg.scala 28:23] _T_655 <= _T_653 @[Reg.scala 28:23]
skip @[Reg.scala 28:19] skip @[Reg.scala 28:19]
wrbuf_byteen <= _T_656 @[axi4_to_ahb.scala 391:16] wrbuf_byteen <= _T_655 @[axi4_to_ahb.scala 391:16]
node _T_657 = bits(io.ahb_haddr, 31, 0) @[axi4_to_ahb.scala 395:27] node _T_656 = bits(io.ahb_haddr, 31, 0) @[axi4_to_ahb.scala 395:27]
node _T_658 = bits(last_addr_en, 0, 0) @[axi4_to_ahb.scala 395:60] node _T_657 = bits(last_addr_en, 0, 0) @[axi4_to_ahb.scala 395:60]
reg _T_659 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] reg _T_658 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_658 : @[Reg.scala 28:19] when _T_657 : @[Reg.scala 28:19]
_T_659 <= _T_657 @[Reg.scala 28:23] _T_658 <= _T_656 @[Reg.scala 28:23]
skip @[Reg.scala 28:19] skip @[Reg.scala 28:19]
last_bus_addr <= _T_659 @[axi4_to_ahb.scala 394:17] last_bus_addr <= _T_658 @[axi4_to_ahb.scala 394:17]
node _T_660 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 403:50] node _T_659 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 403:50]
reg _T_661 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] reg _T_660 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_660 : @[Reg.scala 28:19] when _T_659 : @[Reg.scala 28:19]
_T_661 <= buf_write_in @[Reg.scala 28:23] _T_660 <= buf_write_in @[Reg.scala 28:23]
skip @[Reg.scala 28:19] skip @[Reg.scala 28:19]
buf_write <= _T_661 @[axi4_to_ahb.scala 402:13] buf_write <= _T_660 @[axi4_to_ahb.scala 402:13]
node _T_662 = bits(buf_tag_in, 0, 0) @[axi4_to_ahb.scala 406:25] node _T_661 = bits(buf_tag_in, 0, 0) @[axi4_to_ahb.scala 406:25]
node _T_663 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 406:60] node _T_662 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 406:60]
reg _T_664 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] reg _T_663 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_663 : @[Reg.scala 28:19] when _T_662 : @[Reg.scala 28:19]
_T_664 <= _T_662 @[Reg.scala 28:23] _T_663 <= _T_661 @[Reg.scala 28:23]
skip @[Reg.scala 28:19] skip @[Reg.scala 28:19]
buf_tag <= _T_664 @[axi4_to_ahb.scala 405:11] buf_tag <= _T_663 @[axi4_to_ahb.scala 405:11]
node _T_665 = bits(buf_addr_in, 31, 0) @[axi4_to_ahb.scala 409:33] node _T_664 = bits(buf_addr_in, 31, 0) @[axi4_to_ahb.scala 409:33]
node _T_666 = and(buf_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 409:52] node _T_665 = and(buf_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 409:52]
node _T_667 = bits(_T_666, 0, 0) @[axi4_to_ahb.scala 409:69] node _T_666 = bits(_T_665, 0, 0) @[axi4_to_ahb.scala 409:69]
inst rvclkhdr_4 of rvclkhdr_4 @[el2_lib.scala 508:23] inst rvclkhdr_4 of rvclkhdr_4 @[el2_lib.scala 508:23]
rvclkhdr_4.clock <= clock rvclkhdr_4.clock <= clock
rvclkhdr_4.reset <= reset rvclkhdr_4.reset <= reset
rvclkhdr_4.io.clk <= clock @[el2_lib.scala 510:18] rvclkhdr_4.io.clk <= clock @[el2_lib.scala 510:18]
rvclkhdr_4.io.en <= _T_667 @[el2_lib.scala 511:17] rvclkhdr_4.io.en <= _T_666 @[el2_lib.scala 511:17]
rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
reg _T_668 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] reg _T_667 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
_T_668 <= _T_665 @[el2_lib.scala 514:16] _T_667 <= _T_664 @[el2_lib.scala 514:16]
buf_addr <= _T_668 @[axi4_to_ahb.scala 409:12] buf_addr <= _T_667 @[axi4_to_ahb.scala 409:12]
node _T_669 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 412:26] node _T_668 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 412:26]
node _T_670 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 412:55] node _T_669 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 412:55]
reg _T_671 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] reg _T_670 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_670 : @[Reg.scala 28:19] when _T_669 : @[Reg.scala 28:19]
_T_671 <= _T_669 @[Reg.scala 28:23] _T_670 <= _T_668 @[Reg.scala 28:23]
skip @[Reg.scala 28:19] skip @[Reg.scala 28:19]
buf_size <= _T_671 @[axi4_to_ahb.scala 411:12] buf_size <= _T_670 @[axi4_to_ahb.scala 411:12]
node _T_672 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 415:52] node _T_671 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 415:52]
reg _T_673 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] reg _T_672 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_672 : @[Reg.scala 28:19] when _T_671 : @[Reg.scala 28:19]
_T_673 <= buf_aligned_in @[Reg.scala 28:23] _T_672 <= buf_aligned_in @[Reg.scala 28:23]
skip @[Reg.scala 28:19] skip @[Reg.scala 28:19]
buf_aligned <= _T_673 @[axi4_to_ahb.scala 414:15] buf_aligned <= _T_672 @[axi4_to_ahb.scala 414:15]
node _T_674 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 418:28] node _T_673 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 418:28]
node _T_675 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 418:57] node _T_674 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 418:57]
reg _T_676 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] reg _T_675 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_675 : @[Reg.scala 28:19] when _T_674 : @[Reg.scala 28:19]
_T_676 <= _T_674 @[Reg.scala 28:23] _T_675 <= _T_673 @[Reg.scala 28:23]
skip @[Reg.scala 28:19] skip @[Reg.scala 28:19]
buf_byteen <= _T_676 @[axi4_to_ahb.scala 417:14] buf_byteen <= _T_675 @[axi4_to_ahb.scala 417:14]
node _T_677 = bits(buf_data_in, 63, 0) @[axi4_to_ahb.scala 421:33] node _T_676 = bits(buf_data_in, 63, 0) @[axi4_to_ahb.scala 421:33]
node _T_678 = and(buf_data_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 421:57] node _T_677 = and(buf_data_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 421:57]
node _T_679 = bits(_T_678, 0, 0) @[axi4_to_ahb.scala 421:80] node _T_678 = bits(_T_677, 0, 0) @[axi4_to_ahb.scala 421:80]
inst rvclkhdr_5 of rvclkhdr_5 @[el2_lib.scala 508:23] inst rvclkhdr_5 of rvclkhdr_5 @[el2_lib.scala 508:23]
rvclkhdr_5.clock <= clock rvclkhdr_5.clock <= clock
rvclkhdr_5.reset <= reset rvclkhdr_5.reset <= reset
rvclkhdr_5.io.clk <= clock @[el2_lib.scala 510:18] rvclkhdr_5.io.clk <= clock @[el2_lib.scala 510:18]
rvclkhdr_5.io.en <= _T_679 @[el2_lib.scala 511:17] rvclkhdr_5.io.en <= _T_678 @[el2_lib.scala 511:17]
rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
reg _T_680 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] reg _T_679 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
_T_680 <= _T_677 @[el2_lib.scala 514:16] _T_679 <= _T_676 @[el2_lib.scala 514:16]
buf_data <= _T_680 @[axi4_to_ahb.scala 421:12] buf_data <= _T_679 @[axi4_to_ahb.scala 421:12]
node _T_681 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 424:50] node _T_680 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 424:50]
reg _T_682 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] reg _T_681 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_681 : @[Reg.scala 28:19] when _T_680 : @[Reg.scala 28:19]
_T_682 <= buf_write @[Reg.scala 28:23] _T_681 <= buf_write @[Reg.scala 28:23]
skip @[Reg.scala 28:19] skip @[Reg.scala 28:19]
slvbuf_write <= _T_682 @[axi4_to_ahb.scala 423:16] slvbuf_write <= _T_681 @[axi4_to_ahb.scala 423:16]
node _T_683 = bits(buf_tag, 0, 0) @[axi4_to_ahb.scala 427:22] node _T_682 = bits(buf_tag, 0, 0) @[axi4_to_ahb.scala 427:22]
node _T_684 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 427:60] node _T_683 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 427:60]
reg _T_685 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] reg _T_684 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_684 : @[Reg.scala 28:19] when _T_683 : @[Reg.scala 28:19]
_T_685 <= _T_683 @[Reg.scala 28:23] _T_684 <= _T_682 @[Reg.scala 28:23]
skip @[Reg.scala 28:19] skip @[Reg.scala 28:19]
slvbuf_tag <= _T_685 @[axi4_to_ahb.scala 426:14] slvbuf_tag <= _T_684 @[axi4_to_ahb.scala 426:14]
node _T_686 = bits(slvbuf_error_en, 0, 0) @[axi4_to_ahb.scala 430:59] node _T_685 = bits(slvbuf_error_en, 0, 0) @[axi4_to_ahb.scala 430:59]
reg _T_687 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] reg _T_686 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_686 : @[Reg.scala 28:19] when _T_685 : @[Reg.scala 28:19]
_T_687 <= slvbuf_error_in @[Reg.scala 28:23] _T_686 <= slvbuf_error_in @[Reg.scala 28:23]
skip @[Reg.scala 28:19] skip @[Reg.scala 28:19]
slvbuf_error <= _T_687 @[axi4_to_ahb.scala 429:16] slvbuf_error <= _T_686 @[axi4_to_ahb.scala 429:16]
node _T_688 = bits(cmd_done, 0, 0) @[axi4_to_ahb.scala 434:32] node _T_687 = bits(cmd_done, 0, 0) @[axi4_to_ahb.scala 434:32]
node _T_689 = mux(_T_688, UInt<1>("h01"), cmd_doneQ) @[axi4_to_ahb.scala 434:16] node _T_688 = mux(_T_687, UInt<1>("h01"), cmd_doneQ) @[axi4_to_ahb.scala 434:16]
node _T_690 = eq(cmd_done_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 434:52] node _T_689 = eq(cmd_done_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 434:52]
node _T_691 = and(_T_689, _T_690) @[axi4_to_ahb.scala 434:50] node _T_690 = and(_T_688, _T_689) @[axi4_to_ahb.scala 434:50]
reg _T_692 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 434:12] reg _T_691 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 434:12]
_T_692 <= _T_691 @[axi4_to_ahb.scala 434:12] _T_691 <= _T_690 @[axi4_to_ahb.scala 434:12]
cmd_doneQ <= _T_692 @[axi4_to_ahb.scala 433:13] cmd_doneQ <= _T_691 @[axi4_to_ahb.scala 433:13]
node _T_693 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 438:31] node _T_692 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 438:31]
node _T_694 = bits(buf_cmd_byte_ptr_en, 0, 0) @[axi4_to_ahb.scala 438:70] node _T_693 = bits(buf_cmd_byte_ptr_en, 0, 0) @[axi4_to_ahb.scala 438:70]
reg _T_695 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] reg _T_694 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_694 : @[Reg.scala 28:19] when _T_693 : @[Reg.scala 28:19]
_T_695 <= _T_693 @[Reg.scala 28:23] _T_694 <= _T_692 @[Reg.scala 28:23]
skip @[Reg.scala 28:19] skip @[Reg.scala 28:19]
buf_cmd_byte_ptrQ <= _T_695 @[axi4_to_ahb.scala 437:21] buf_cmd_byte_ptrQ <= _T_694 @[axi4_to_ahb.scala 437:21]
reg _T_696 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 443:12] reg _T_695 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 443:12]
_T_696 <= io.ahb_hready @[axi4_to_ahb.scala 443:12] _T_695 <= io.ahb_hready @[axi4_to_ahb.scala 443:12]
ahb_hready_q <= _T_696 @[axi4_to_ahb.scala 442:16] ahb_hready_q <= _T_695 @[axi4_to_ahb.scala 442:16]
node _T_697 = bits(io.ahb_htrans, 1, 0) @[axi4_to_ahb.scala 446:26] node _T_696 = bits(io.ahb_htrans, 1, 0) @[axi4_to_ahb.scala 446:26]
reg _T_698 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 446:12] reg _T_697 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 446:12]
_T_698 <= _T_697 @[axi4_to_ahb.scala 446:12] _T_697 <= _T_696 @[axi4_to_ahb.scala 446:12]
ahb_htrans_q <= _T_698 @[axi4_to_ahb.scala 445:16] ahb_htrans_q <= _T_697 @[axi4_to_ahb.scala 445:16]
reg _T_699 : UInt<1>, ahbm_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 449:12] reg _T_698 : UInt<1>, ahbm_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 449:12]
_T_699 <= io.ahb_hwrite @[axi4_to_ahb.scala 449:12] _T_698 <= io.ahb_hwrite @[axi4_to_ahb.scala 449:12]
ahb_hwrite_q <= _T_699 @[axi4_to_ahb.scala 448:16] ahb_hwrite_q <= _T_698 @[axi4_to_ahb.scala 448:16]
reg _T_700 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 452:12] reg _T_699 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 452:12]
_T_700 <= io.ahb_hresp @[axi4_to_ahb.scala 452:12] _T_699 <= io.ahb_hresp @[axi4_to_ahb.scala 452:12]
ahb_hresp_q <= _T_700 @[axi4_to_ahb.scala 451:15] ahb_hresp_q <= _T_699 @[axi4_to_ahb.scala 451:15]
node _T_701 = bits(io.ahb_hrdata, 63, 0) @[axi4_to_ahb.scala 455:26] node _T_700 = bits(io.ahb_hrdata, 63, 0) @[axi4_to_ahb.scala 455:26]
reg _T_702 : UInt, ahbm_data_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 455:12] reg _T_701 : UInt, ahbm_data_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 455:12]
_T_702 <= _T_701 @[axi4_to_ahb.scala 455:12] _T_701 <= _T_700 @[axi4_to_ahb.scala 455:12]
ahb_hrdata_q <= _T_702 @[axi4_to_ahb.scala 454:16] ahb_hrdata_q <= _T_701 @[axi4_to_ahb.scala 454:16]
node _T_703 = or(buf_wr_en, slvbuf_wr_en) @[axi4_to_ahb.scala 458:43] node _T_702 = or(buf_wr_en, slvbuf_wr_en) @[axi4_to_ahb.scala 458:43]
node _T_704 = or(_T_703, io.clk_override) @[axi4_to_ahb.scala 458:58] node _T_703 = or(_T_702, io.clk_override) @[axi4_to_ahb.scala 458:58]
node _T_705 = and(io.bus_clk_en, _T_704) @[axi4_to_ahb.scala 458:30] node _T_704 = and(io.bus_clk_en, _T_703) @[axi4_to_ahb.scala 458:30]
buf_clken <= _T_705 @[axi4_to_ahb.scala 458:13] buf_clken <= _T_704 @[axi4_to_ahb.scala 458:13]
node _T_706 = bits(io.ahb_htrans, 1, 1) @[axi4_to_ahb.scala 459:69] node _T_705 = bits(io.ahb_htrans, 1, 1) @[axi4_to_ahb.scala 459:69]
node _T_707 = and(io.ahb_hready, _T_706) @[axi4_to_ahb.scala 459:54] node _T_706 = and(io.ahb_hready, _T_705) @[axi4_to_ahb.scala 459:54]
node _T_708 = or(_T_707, io.clk_override) @[axi4_to_ahb.scala 459:74] node _T_707 = or(_T_706, io.clk_override) @[axi4_to_ahb.scala 459:74]
node _T_709 = and(io.bus_clk_en, _T_708) @[axi4_to_ahb.scala 459:36] node _T_708 = and(io.bus_clk_en, _T_707) @[axi4_to_ahb.scala 459:36]
ahbm_addr_clken <= _T_709 @[axi4_to_ahb.scala 459:19] ahbm_addr_clken <= _T_708 @[axi4_to_ahb.scala 459:19]
node _T_710 = neq(buf_state, UInt<3>("h00")) @[axi4_to_ahb.scala 460:50] node _T_709 = neq(buf_state, UInt<3>("h00")) @[axi4_to_ahb.scala 460:50]
node _T_711 = or(_T_710, io.clk_override) @[axi4_to_ahb.scala 460:60] node _T_710 = or(_T_709, io.clk_override) @[axi4_to_ahb.scala 460:60]
node _T_712 = and(io.bus_clk_en, _T_711) @[axi4_to_ahb.scala 460:36] node _T_711 = and(io.bus_clk_en, _T_710) @[axi4_to_ahb.scala 460:36]
ahbm_data_clken <= _T_712 @[axi4_to_ahb.scala 460:19] ahbm_data_clken <= _T_711 @[axi4_to_ahb.scala 460:19]
inst rvclkhdr_6 of rvclkhdr_6 @[el2_lib.scala 483:22] inst rvclkhdr_6 of rvclkhdr_6 @[el2_lib.scala 483:22]
rvclkhdr_6.clock <= clock rvclkhdr_6.clock <= clock
rvclkhdr_6.reset <= reset rvclkhdr_6.reset <= reset

184
axi4_to_ahb.v
View File

@ -168,9 +168,9 @@ module axi4_to_ahb(
reg cmd_doneQ; // @[axi4_to_ahb.scala 434:12] reg cmd_doneQ; // @[axi4_to_ahb.scala 434:12]
wire _T_280 = cmd_doneQ & ahb_hready_q; // @[axi4_to_ahb.scala 317:34] wire _T_280 = cmd_doneQ & ahb_hready_q; // @[axi4_to_ahb.scala 317:34]
wire _T_281 = _T_280 | ahb_hresp_q; // @[axi4_to_ahb.scala 317:50] wire _T_281 = _T_280 | ahb_hresp_q; // @[axi4_to_ahb.scala 317:50]
wire _T_442 = 3'h5 == buf_state; // @[Conditional.scala 37:30] wire _T_441 = 3'h5 == buf_state; // @[Conditional.scala 37:30]
wire slave_ready = io_axi_bready & io_axi_rready; // @[axi4_to_ahb.scala 216:32] wire slave_ready = io_axi_bready & io_axi_rready; // @[axi4_to_ahb.scala 216:32]
wire _GEN_1 = _T_442 & slave_ready; // @[Conditional.scala 39:67] wire _GEN_1 = _T_441 & slave_ready; // @[Conditional.scala 39:67]
wire _GEN_3 = _T_279 ? _T_281 : _GEN_1; // @[Conditional.scala 39:67] wire _GEN_3 = _T_279 ? _T_281 : _GEN_1; // @[Conditional.scala 39:67]
wire _GEN_20 = _T_186 ? trxn_done : _GEN_3; // @[Conditional.scala 39:67] wire _GEN_20 = _T_186 ? trxn_done : _GEN_3; // @[Conditional.scala 39:67]
wire _GEN_35 = _T_184 ? _T_154 : _GEN_20; // @[Conditional.scala 39:67] wire _GEN_35 = _T_184 ? _T_154 : _GEN_20; // @[Conditional.scala 39:67]
@ -201,10 +201,10 @@ module axi4_to_ahb(
wire _T_141 = _T_136 & _T_140; // @[axi4_to_ahb.scala 272:53] wire _T_141 = _T_136 & _T_140; // @[axi4_to_ahb.scala 272:53]
wire _T_285 = _T_281 & _T_135; // @[axi4_to_ahb.scala 318:66] wire _T_285 = _T_281 & _T_135; // @[axi4_to_ahb.scala 318:66]
wire _T_286 = _T_285 & slave_ready; // @[axi4_to_ahb.scala 318:81] wire _T_286 = _T_285 & slave_ready; // @[axi4_to_ahb.scala 318:81]
wire _GEN_4 = _T_279 ? _T_286 : 1'h1; // @[Conditional.scala 39:67] wire _GEN_4 = _T_279 & _T_286; // @[Conditional.scala 39:67]
wire _GEN_26 = _T_186 | _GEN_4; // @[Conditional.scala 39:67] wire _GEN_26 = _T_186 ? 1'h0 : _GEN_4; // @[Conditional.scala 39:67]
wire _GEN_45 = _T_184 | _GEN_26; // @[Conditional.scala 39:67] wire _GEN_45 = _T_184 ? 1'h0 : _GEN_26; // @[Conditional.scala 39:67]
wire _GEN_62 = _T_173 | _GEN_45; // @[Conditional.scala 39:67] wire _GEN_62 = _T_173 ? 1'h0 : _GEN_45; // @[Conditional.scala 39:67]
wire _GEN_66 = _T_134 ? _T_141 : _GEN_62; // @[Conditional.scala 39:67] wire _GEN_66 = _T_134 ? _T_141 : _GEN_62; // @[Conditional.scala 39:67]
wire _GEN_86 = _T_99 ? _T_123 : _GEN_66; // @[Conditional.scala 39:67] wire _GEN_86 = _T_99 ? _T_123 : _GEN_66; // @[Conditional.scala 39:67]
wire master_ready = _T_47 | _GEN_86; // @[Conditional.scala 40:58] wire master_ready = _T_47 | _GEN_86; // @[Conditional.scala 40:58]
@ -235,7 +235,7 @@ module axi4_to_ahb(
wire _T_156 = buf_state_en & _T_135; // @[axi4_to_ahb.scala 279:39] wire _T_156 = buf_state_en & _T_135; // @[axi4_to_ahb.scala 279:39]
wire _T_359 = buf_nxtstate != 3'h5; // @[axi4_to_ahb.scala 328:55] wire _T_359 = buf_nxtstate != 3'h5; // @[axi4_to_ahb.scala 328:55]
wire _T_360 = buf_state_en & _T_359; // @[axi4_to_ahb.scala 328:39] wire _T_360 = buf_state_en & _T_359; // @[axi4_to_ahb.scala 328:39]
wire _GEN_14 = _T_279 ? _T_360 : _T_442; // @[Conditional.scala 39:67] wire _GEN_14 = _T_279 ? _T_360 : _T_441; // @[Conditional.scala 39:67]
wire _GEN_33 = _T_186 ? 1'h0 : _GEN_14; // @[Conditional.scala 39:67] wire _GEN_33 = _T_186 ? 1'h0 : _GEN_14; // @[Conditional.scala 39:67]
wire _GEN_49 = _T_184 ? 1'h0 : _GEN_33; // @[Conditional.scala 39:67] wire _GEN_49 = _T_184 ? 1'h0 : _GEN_33; // @[Conditional.scala 39:67]
wire _GEN_52 = _T_173 ? buf_state_en : _GEN_49; // @[Conditional.scala 39:67] wire _GEN_52 = _T_173 ? buf_state_en : _GEN_49; // @[Conditional.scala 39:67]
@ -245,21 +245,21 @@ module axi4_to_ahb(
wire _T_23 = slave_valid_pre & slave_ready; // @[axi4_to_ahb.scala 208:32] wire _T_23 = slave_valid_pre & slave_ready; // @[axi4_to_ahb.scala 208:32]
wire buf_clk = rvclkhdr_6_io_l1clk; // @[axi4_to_ahb.scala 156:21 axi4_to_ahb.scala 463:12] wire buf_clk = rvclkhdr_6_io_l1clk; // @[axi4_to_ahb.scala 156:21 axi4_to_ahb.scala 463:12]
reg slvbuf_write; // @[Reg.scala 27:20] reg slvbuf_write; // @[Reg.scala 27:20]
wire [1:0] _T_595 = slvbuf_write ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 365:23] wire [1:0] _T_594 = slvbuf_write ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 365:23]
reg slvbuf_error; // @[Reg.scala 27:20] reg slvbuf_error; // @[Reg.scala 27:20]
wire [1:0] _T_597 = slvbuf_error ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] wire [1:0] _T_596 = slvbuf_error ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire [1:0] _T_598 = _T_597 & 2'h2; // @[axi4_to_ahb.scala 365:88] wire [1:0] _T_597 = _T_596 & 2'h2; // @[axi4_to_ahb.scala 365:88]
wire [3:0] slave_opc = {_T_595,_T_598}; // @[Cat.scala 29:58] wire [3:0] slave_opc = {_T_594,_T_597}; // @[Cat.scala 29:58]
wire [1:0] _T_28 = slave_opc[1] ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 209:49] wire [1:0] _T_28 = slave_opc[1] ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 209:49]
reg slvbuf_tag; // @[Reg.scala 27:20] reg slvbuf_tag; // @[Reg.scala 27:20]
wire _T_33 = slave_opc[3:2] == 2'h0; // @[axi4_to_ahb.scala 212:65] wire _T_33 = slave_opc[3:2] == 2'h0; // @[axi4_to_ahb.scala 212:65]
reg [31:0] last_bus_addr; // @[Reg.scala 27:20] reg [31:0] last_bus_addr; // @[Reg.scala 27:20]
wire [63:0] _T_602 = {last_bus_addr,last_bus_addr}; // @[Cat.scala 29:58] wire [63:0] _T_601 = {last_bus_addr,last_bus_addr}; // @[Cat.scala 29:58]
wire _T_603 = buf_state == 3'h5; // @[axi4_to_ahb.scala 366:91] wire _T_602 = buf_state == 3'h5; // @[axi4_to_ahb.scala 366:91]
reg [63:0] buf_data; // @[el2_lib.scala 514:16] reg [63:0] buf_data; // @[el2_lib.scala 514:16]
wire ahbm_data_clk = rvclkhdr_9_io_l1clk; // @[axi4_to_ahb.scala 64:27 axi4_to_ahb.scala 466:17] wire ahbm_data_clk = rvclkhdr_9_io_l1clk; // @[axi4_to_ahb.scala 64:27 axi4_to_ahb.scala 466:17]
reg [63:0] ahb_hrdata_q; // @[axi4_to_ahb.scala 455:12] reg [63:0] ahb_hrdata_q; // @[axi4_to_ahb.scala 455:12]
wire [63:0] _T_606 = _T_603 ? buf_data : ahb_hrdata_q; // @[axi4_to_ahb.scala 366:79] wire [63:0] _T_605 = _T_602 ? buf_data : ahb_hrdata_q; // @[axi4_to_ahb.scala 366:79]
wire _T_42 = io_axi_awvalid & io_axi_awready; // @[axi4_to_ahb.scala 219:56] wire _T_42 = io_axi_awvalid & io_axi_awready; // @[axi4_to_ahb.scala 219:56]
wire _T_43 = io_axi_wvalid & io_axi_wready; // @[axi4_to_ahb.scala 219:91] wire _T_43 = io_axi_wvalid & io_axi_wready; // @[axi4_to_ahb.scala 219:91]
wire _T_44 = _T_42 | _T_43; // @[axi4_to_ahb.scala 219:74] wire _T_44 = _T_42 | _T_43; // @[axi4_to_ahb.scala 219:74]
@ -358,9 +358,9 @@ module axi4_to_ahb(
wire [1:0] _T_357 = _T_355 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] wire [1:0] _T_357 = _T_355 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire [1:0] _T_358 = _T_357 & 2'h2; // @[axi4_to_ahb.scala 327:71] wire [1:0] _T_358 = _T_357 & 2'h2; // @[axi4_to_ahb.scala 327:71]
wire _T_365 = trxn_done | bypass_en; // @[axi4_to_ahb.scala 330:40] wire _T_365 = trxn_done | bypass_en; // @[axi4_to_ahb.scala 330:40]
wire [2:0] _T_441 = bypass_en ? _T_91 : _T_229; // @[axi4_to_ahb.scala 333:30] wire [2:0] _T_440 = bypass_en ? _T_91 : _T_229; // @[axi4_to_ahb.scala 333:30]
wire _GEN_6 = _T_279 & ahb_hresp_q; // @[Conditional.scala 39:67] wire _GEN_6 = _T_279 & ahb_hresp_q; // @[Conditional.scala 39:67]
wire _GEN_7 = _T_279 ? buf_state_en : _T_442; // @[Conditional.scala 39:67] wire _GEN_7 = _T_279 ? buf_state_en : _T_441; // @[Conditional.scala 39:67]
wire _GEN_9 = _T_279 & _T_302; // @[Conditional.scala 39:67] wire _GEN_9 = _T_279 & _T_302; // @[Conditional.scala 39:67]
wire _GEN_30 = _T_186 ? 1'h0 : _GEN_9; // @[Conditional.scala 39:67] wire _GEN_30 = _T_186 ? 1'h0 : _GEN_9; // @[Conditional.scala 39:67]
wire _GEN_47 = _T_184 ? 1'h0 : _GEN_30; // @[Conditional.scala 39:67] wire _GEN_47 = _T_184 ? 1'h0 : _GEN_30; // @[Conditional.scala 39:67]
@ -371,7 +371,7 @@ module axi4_to_ahb(
wire _GEN_10 = _T_279 & buf_wr_en; // @[Conditional.scala 39:67] wire _GEN_10 = _T_279 & buf_wr_en; // @[Conditional.scala 39:67]
wire [1:0] _GEN_13 = _T_279 ? _T_358 : 2'h0; // @[Conditional.scala 39:67] wire [1:0] _GEN_13 = _T_279 ? _T_358 : 2'h0; // @[Conditional.scala 39:67]
wire _GEN_16 = _T_279 & _T_365; // @[Conditional.scala 39:67] wire _GEN_16 = _T_279 & _T_365; // @[Conditional.scala 39:67]
wire [2:0] _GEN_17 = _T_279 ? _T_441 : 3'h0; // @[Conditional.scala 39:67] wire [2:0] _GEN_17 = _T_279 ? _T_440 : 3'h0; // @[Conditional.scala 39:67]
wire _GEN_21 = _T_186 ? buf_state_en : _GEN_16; // @[Conditional.scala 39:67] wire _GEN_21 = _T_186 ? buf_state_en : _GEN_16; // @[Conditional.scala 39:67]
wire _GEN_22 = _T_186 & buf_state_en; // @[Conditional.scala 39:67] wire _GEN_22 = _T_186 & buf_state_en; // @[Conditional.scala 39:67]
wire [2:0] _GEN_23 = _T_186 ? _T_229 : _GEN_17; // @[Conditional.scala 39:67] wire [2:0] _GEN_23 = _T_186 ? _T_229 : _GEN_17; // @[Conditional.scala 39:67]
@ -407,72 +407,72 @@ module axi4_to_ahb(
wire [2:0] buf_cmd_byte_ptr = _T_47 ? _T_93 : _GEN_89; // @[Conditional.scala 40:58] wire [2:0] buf_cmd_byte_ptr = _T_47 ? _T_93 : _GEN_89; // @[Conditional.scala 40:58]
wire slvbuf_wr_en = _T_47 ? 1'h0 : _GEN_85; // @[Conditional.scala 40:58] wire slvbuf_wr_en = _T_47 ? 1'h0 : _GEN_85; // @[Conditional.scala 40:58]
wire slvbuf_error_en = _T_47 ? 1'h0 : _GEN_93; // @[Conditional.scala 40:58] wire slvbuf_error_en = _T_47 ? 1'h0 : _GEN_93; // @[Conditional.scala 40:58]
wire _T_534 = master_size[1:0] == 2'h0; // @[axi4_to_ahb.scala 351:24] wire _T_533 = master_size[1:0] == 2'h0; // @[axi4_to_ahb.scala 351:24]
wire _T_535 = _T_101 | _T_534; // @[axi4_to_ahb.scala 350:51] wire _T_534 = _T_101 | _T_533; // @[axi4_to_ahb.scala 350:51]
wire _T_537 = master_size[1:0] == 2'h1; // @[axi4_to_ahb.scala 351:57] wire _T_536 = master_size[1:0] == 2'h1; // @[axi4_to_ahb.scala 351:57]
wire _T_538 = _T_535 | _T_537; // @[axi4_to_ahb.scala 351:36] wire _T_537 = _T_534 | _T_536; // @[axi4_to_ahb.scala 351:36]
wire _T_540 = master_size[1:0] == 2'h2; // @[axi4_to_ahb.scala 351:91] wire _T_539 = master_size[1:0] == 2'h2; // @[axi4_to_ahb.scala 351:91]
wire _T_541 = _T_538 | _T_540; // @[axi4_to_ahb.scala 351:70] wire _T_540 = _T_537 | _T_539; // @[axi4_to_ahb.scala 351:70]
wire _T_543 = master_size[1:0] == 2'h3; // @[axi4_to_ahb.scala 352:25] wire _T_542 = master_size[1:0] == 2'h3; // @[axi4_to_ahb.scala 352:25]
wire _T_545 = wrbuf_byteen == 8'h3; // @[axi4_to_ahb.scala 352:62] wire _T_544 = wrbuf_byteen == 8'h3; // @[axi4_to_ahb.scala 352:62]
wire _T_547 = wrbuf_byteen == 8'hc; // @[axi4_to_ahb.scala 352:97] wire _T_546 = wrbuf_byteen == 8'hc; // @[axi4_to_ahb.scala 352:97]
wire _T_548 = _T_545 | _T_547; // @[axi4_to_ahb.scala 352:74] wire _T_547 = _T_544 | _T_546; // @[axi4_to_ahb.scala 352:74]
wire _T_550 = wrbuf_byteen == 8'h30; // @[axi4_to_ahb.scala 352:132] wire _T_549 = wrbuf_byteen == 8'h30; // @[axi4_to_ahb.scala 352:132]
wire _T_551 = _T_548 | _T_550; // @[axi4_to_ahb.scala 352:109] wire _T_550 = _T_547 | _T_549; // @[axi4_to_ahb.scala 352:109]
wire _T_553 = wrbuf_byteen == 8'hc0; // @[axi4_to_ahb.scala 352:168] wire _T_552 = wrbuf_byteen == 8'hc0; // @[axi4_to_ahb.scala 352:168]
wire _T_554 = _T_551 | _T_553; // @[axi4_to_ahb.scala 352:145] wire _T_553 = _T_550 | _T_552; // @[axi4_to_ahb.scala 352:145]
wire _T_556 = wrbuf_byteen == 8'hf; // @[axi4_to_ahb.scala 353:28] wire _T_555 = wrbuf_byteen == 8'hf; // @[axi4_to_ahb.scala 353:28]
wire _T_557 = _T_554 | _T_556; // @[axi4_to_ahb.scala 352:181] wire _T_556 = _T_553 | _T_555; // @[axi4_to_ahb.scala 352:181]
wire _T_559 = wrbuf_byteen == 8'hf0; // @[axi4_to_ahb.scala 353:63] wire _T_558 = wrbuf_byteen == 8'hf0; // @[axi4_to_ahb.scala 353:63]
wire _T_560 = _T_557 | _T_559; // @[axi4_to_ahb.scala 353:40] wire _T_559 = _T_556 | _T_558; // @[axi4_to_ahb.scala 353:40]
wire _T_562 = wrbuf_byteen == 8'hff; // @[axi4_to_ahb.scala 353:99] wire _T_561 = wrbuf_byteen == 8'hff; // @[axi4_to_ahb.scala 353:99]
wire _T_563 = _T_560 | _T_562; // @[axi4_to_ahb.scala 353:76] wire _T_562 = _T_559 | _T_561; // @[axi4_to_ahb.scala 353:76]
wire _T_564 = _T_543 & _T_563; // @[axi4_to_ahb.scala 352:38] wire _T_563 = _T_542 & _T_562; // @[axi4_to_ahb.scala 352:38]
wire buf_aligned_in = _T_541 | _T_564; // @[axi4_to_ahb.scala 351:104] wire buf_aligned_in = _T_540 | _T_563; // @[axi4_to_ahb.scala 351:104]
wire _T_446 = buf_aligned_in & _T_49; // @[axi4_to_ahb.scala 345:60] wire _T_445 = buf_aligned_in & _T_49; // @[axi4_to_ahb.scala 345:60]
wire [2:0] _T_483 = _T_446 ? 3'h0 : master_addr[2:0]; // @[axi4_to_ahb.scala 345:43] wire [2:0] _T_482 = _T_445 ? 3'h0 : master_addr[2:0]; // @[axi4_to_ahb.scala 345:43]
wire _T_487 = buf_state == 3'h3; // @[axi4_to_ahb.scala 348:33] wire _T_486 = buf_state == 3'h3; // @[axi4_to_ahb.scala 348:33]
wire _T_493 = buf_aligned_in & _T_543; // @[axi4_to_ahb.scala 349:38] wire _T_492 = buf_aligned_in & _T_542; // @[axi4_to_ahb.scala 349:38]
wire _T_496 = _T_493 & _T_49; // @[axi4_to_ahb.scala 349:72] wire _T_495 = _T_492 & _T_49; // @[axi4_to_ahb.scala 349:72]
wire [1:0] _T_530 = _T_496 ? 2'h0 : master_size[1:0]; // @[axi4_to_ahb.scala 349:21] wire [1:0] _T_529 = _T_495 ? 2'h0 : master_size[1:0]; // @[axi4_to_ahb.scala 349:21]
wire [31:0] _T_569 = {master_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58] wire [31:0] _T_568 = {master_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58]
wire [31:0] _T_572 = {buf_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58] wire [31:0] _T_571 = {buf_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58]
wire [1:0] _T_576 = buf_aligned_in ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] wire [1:0] _T_575 = buf_aligned_in ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire [2:0] buf_size_in = {{1'd0}, _T_530}; // @[axi4_to_ahb.scala 349:15] wire [2:0] buf_size_in = {{1'd0}, _T_529}; // @[axi4_to_ahb.scala 349:15]
wire [1:0] _T_578 = _T_576 & buf_size_in[1:0]; // @[axi4_to_ahb.scala 356:80] wire [1:0] _T_577 = _T_575 & buf_size_in[1:0]; // @[axi4_to_ahb.scala 356:77]
wire [2:0] _T_579 = {1'h0,_T_578}; // @[Cat.scala 29:58] wire [2:0] _T_578 = {1'h0,_T_577}; // @[Cat.scala 29:58]
wire [1:0] _T_581 = buf_aligned ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] wire [1:0] _T_580 = buf_aligned ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
reg [1:0] buf_size; // @[Reg.scala 27:20] reg [1:0] buf_size; // @[Reg.scala 27:20]
wire [1:0] _T_583 = _T_581 & buf_size; // @[axi4_to_ahb.scala 356:138] wire [1:0] _T_582 = _T_580 & buf_size; // @[axi4_to_ahb.scala 356:135]
wire [2:0] _T_584 = {1'h0,_T_583}; // @[Cat.scala 29:58] wire [2:0] _T_583 = {1'h0,_T_582}; // @[Cat.scala 29:58]
wire _T_587 = ~io_axi_arprot[2]; // @[axi4_to_ahb.scala 360:33] wire _T_586 = ~io_axi_arprot[2]; // @[axi4_to_ahb.scala 360:33]
wire [1:0] _T_588 = {1'h1,_T_587}; // @[Cat.scala 29:58] wire [1:0] _T_587 = {1'h1,_T_586}; // @[Cat.scala 29:58]
reg buf_write; // @[Reg.scala 27:20] reg buf_write; // @[Reg.scala 27:20]
wire _T_610 = io_ahb_htrans != 2'h0; // @[axi4_to_ahb.scala 369:40] wire _T_609 = io_ahb_htrans != 2'h0; // @[axi4_to_ahb.scala 369:40]
wire _T_611 = _T_610 & io_ahb_hready; // @[axi4_to_ahb.scala 369:52] wire _T_610 = _T_609 & io_ahb_hready; // @[axi4_to_ahb.scala 369:52]
wire last_addr_en = _T_611 & io_ahb_hwrite; // @[axi4_to_ahb.scala 369:68] wire last_addr_en = _T_610 & io_ahb_hwrite; // @[axi4_to_ahb.scala 369:68]
wire wrbuf_en = _T_42 & master_ready; // @[axi4_to_ahb.scala 371:47] wire wrbuf_en = _T_42 & master_ready; // @[axi4_to_ahb.scala 371:47]
wire wrbuf_data_en = _T_43 & master_ready; // @[axi4_to_ahb.scala 372:50] wire wrbuf_data_en = _T_43 & master_ready; // @[axi4_to_ahb.scala 372:50]
wire wrbuf_cmd_sent = _T_147 & _T_49; // @[axi4_to_ahb.scala 373:49] wire wrbuf_cmd_sent = _T_147 & _T_49; // @[axi4_to_ahb.scala 373:49]
wire _T_621 = ~wrbuf_en; // @[axi4_to_ahb.scala 374:33] wire _T_620 = ~wrbuf_en; // @[axi4_to_ahb.scala 374:33]
wire wrbuf_rst = wrbuf_cmd_sent & _T_621; // @[axi4_to_ahb.scala 374:31] wire wrbuf_rst = wrbuf_cmd_sent & _T_620; // @[axi4_to_ahb.scala 374:31]
wire _T_623 = ~wrbuf_cmd_sent; // @[axi4_to_ahb.scala 376:35] wire _T_622 = ~wrbuf_cmd_sent; // @[axi4_to_ahb.scala 376:35]
wire _T_624 = wrbuf_vld & _T_623; // @[axi4_to_ahb.scala 376:33] wire _T_623 = wrbuf_vld & _T_622; // @[axi4_to_ahb.scala 376:33]
wire _T_625 = ~_T_624; // @[axi4_to_ahb.scala 376:21] wire _T_624 = ~_T_623; // @[axi4_to_ahb.scala 376:21]
wire _T_628 = wrbuf_data_vld & _T_623; // @[axi4_to_ahb.scala 377:37] wire _T_627 = wrbuf_data_vld & _T_622; // @[axi4_to_ahb.scala 377:37]
wire _T_629 = ~_T_628; // @[axi4_to_ahb.scala 377:20] wire _T_628 = ~_T_627; // @[axi4_to_ahb.scala 377:20]
wire _T_632 = ~wr_cmd_vld; // @[axi4_to_ahb.scala 378:21] wire _T_631 = ~wr_cmd_vld; // @[axi4_to_ahb.scala 378:21]
wire _T_635 = wrbuf_en | wrbuf_vld; // @[axi4_to_ahb.scala 382:52] wire _T_634 = wrbuf_en | wrbuf_vld; // @[axi4_to_ahb.scala 382:52]
wire _T_636 = ~wrbuf_rst; // @[axi4_to_ahb.scala 382:88] wire _T_635 = ~wrbuf_rst; // @[axi4_to_ahb.scala 382:88]
wire _T_640 = wrbuf_data_en | wrbuf_data_vld; // @[axi4_to_ahb.scala 383:52] wire _T_639 = wrbuf_data_en | wrbuf_data_vld; // @[axi4_to_ahb.scala 383:52]
reg buf_tag; // @[Reg.scala 27:20] reg buf_tag; // @[Reg.scala 27:20]
wire _T_690 = ~slave_valid_pre; // @[axi4_to_ahb.scala 434:52] wire _T_689 = ~slave_valid_pre; // @[axi4_to_ahb.scala 434:52]
wire _T_703 = buf_wr_en | slvbuf_wr_en; // @[axi4_to_ahb.scala 458:43] wire _T_702 = buf_wr_en | slvbuf_wr_en; // @[axi4_to_ahb.scala 458:43]
wire _T_704 = _T_703 | io_clk_override; // @[axi4_to_ahb.scala 458:58] wire _T_703 = _T_702 | io_clk_override; // @[axi4_to_ahb.scala 458:58]
wire _T_707 = io_ahb_hready & io_ahb_htrans[1]; // @[axi4_to_ahb.scala 459:54] wire _T_706 = io_ahb_hready & io_ahb_htrans[1]; // @[axi4_to_ahb.scala 459:54]
wire _T_708 = _T_707 | io_clk_override; // @[axi4_to_ahb.scala 459:74] wire _T_707 = _T_706 | io_clk_override; // @[axi4_to_ahb.scala 459:74]
wire _T_710 = buf_state != 3'h0; // @[axi4_to_ahb.scala 460:50] wire _T_709 = buf_state != 3'h0; // @[axi4_to_ahb.scala 460:50]
wire _T_711 = _T_710 | io_clk_override; // @[axi4_to_ahb.scala 460:60] wire _T_710 = _T_709 | io_clk_override; // @[axi4_to_ahb.scala 460:60]
rvclkhdr rvclkhdr ( // @[el2_lib.scala 483:22] rvclkhdr rvclkhdr ( // @[el2_lib.scala 483:22]
.io_l1clk(rvclkhdr_io_l1clk), .io_l1clk(rvclkhdr_io_l1clk),
.io_clk(rvclkhdr_io_clk), .io_clk(rvclkhdr_io_clk),
@ -533,22 +533,22 @@ module axi4_to_ahb(
.io_en(rvclkhdr_9_io_en), .io_en(rvclkhdr_9_io_en),
.io_scan_mode(rvclkhdr_9_io_scan_mode) .io_scan_mode(rvclkhdr_9_io_scan_mode)
); );
assign io_axi_awready = _T_625 & master_ready; // @[axi4_to_ahb.scala 376:18] assign io_axi_awready = _T_624 & master_ready; // @[axi4_to_ahb.scala 376:18]
assign io_axi_wready = _T_629 & master_ready; // @[axi4_to_ahb.scala 377:17] assign io_axi_wready = _T_628 & master_ready; // @[axi4_to_ahb.scala 377:17]
assign io_axi_bvalid = _T_23 & slave_opc[3]; // @[axi4_to_ahb.scala 208:17] assign io_axi_bvalid = _T_23 & slave_opc[3]; // @[axi4_to_ahb.scala 208:17]
assign io_axi_bresp = slave_opc[0] ? 2'h2 : _T_28; // @[axi4_to_ahb.scala 209:16] assign io_axi_bresp = slave_opc[0] ? 2'h2 : _T_28; // @[axi4_to_ahb.scala 209:16]
assign io_axi_bid = slvbuf_tag; // @[axi4_to_ahb.scala 210:14] assign io_axi_bid = slvbuf_tag; // @[axi4_to_ahb.scala 210:14]
assign io_axi_arready = _T_632 & master_ready; // @[axi4_to_ahb.scala 378:18] assign io_axi_arready = _T_631 & master_ready; // @[axi4_to_ahb.scala 378:18]
assign io_axi_rvalid = _T_23 & _T_33; // @[axi4_to_ahb.scala 212:17] assign io_axi_rvalid = _T_23 & _T_33; // @[axi4_to_ahb.scala 212:17]
assign io_axi_rid = slvbuf_tag; // @[axi4_to_ahb.scala 214:14] assign io_axi_rid = slvbuf_tag; // @[axi4_to_ahb.scala 214:14]
assign io_axi_rdata = slvbuf_error ? _T_602 : _T_606; // @[axi4_to_ahb.scala 215:16] assign io_axi_rdata = slvbuf_error ? _T_601 : _T_605; // @[axi4_to_ahb.scala 215:16]
assign io_axi_rresp = slave_opc[0] ? 2'h2 : _T_28; // @[axi4_to_ahb.scala 213:16] assign io_axi_rresp = slave_opc[0] ? 2'h2 : _T_28; // @[axi4_to_ahb.scala 213:16]
assign io_axi_rlast = 1'h1; // @[axi4_to_ahb.scala 379:16] assign io_axi_rlast = 1'h1; // @[axi4_to_ahb.scala 379:16]
assign io_ahb_haddr = bypass_en ? _T_569 : _T_572; // @[axi4_to_ahb.scala 355:16] assign io_ahb_haddr = bypass_en ? _T_568 : _T_571; // @[axi4_to_ahb.scala 355:16]
assign io_ahb_hburst = 3'h0; // @[axi4_to_ahb.scala 358:17] assign io_ahb_hburst = 3'h0; // @[axi4_to_ahb.scala 358:17]
assign io_ahb_hmastlock = 1'h0; // @[axi4_to_ahb.scala 359:20] assign io_ahb_hmastlock = 1'h0; // @[axi4_to_ahb.scala 359:20]
assign io_ahb_hprot = {{2'd0}, _T_588}; // @[axi4_to_ahb.scala 360:16] assign io_ahb_hprot = {{2'd0}, _T_587}; // @[axi4_to_ahb.scala 360:16]
assign io_ahb_hsize = bypass_en ? _T_579 : _T_584; // @[axi4_to_ahb.scala 356:16] assign io_ahb_hsize = bypass_en ? _T_578 : _T_583; // @[axi4_to_ahb.scala 356:16]
assign io_ahb_htrans = _T_47 ? _T_98 : _GEN_90; // @[axi4_to_ahb.scala 225:17 axi4_to_ahb.scala 256:21 axi4_to_ahb.scala 268:21 axi4_to_ahb.scala 283:21 axi4_to_ahb.scala 293:21 axi4_to_ahb.scala 313:21 axi4_to_ahb.scala 327:21] assign io_ahb_htrans = _T_47 ? _T_98 : _GEN_90; // @[axi4_to_ahb.scala 225:17 axi4_to_ahb.scala 256:21 axi4_to_ahb.scala 268:21 axi4_to_ahb.scala 283:21 axi4_to_ahb.scala 293:21 axi4_to_ahb.scala 313:21 axi4_to_ahb.scala 327:21]
assign io_ahb_hwrite = bypass_en ? _T_49 : buf_write; // @[axi4_to_ahb.scala 361:17] assign io_ahb_hwrite = bypass_en ? _T_49 : buf_write; // @[axi4_to_ahb.scala 361:17]
assign io_ahb_hwdata = buf_data; // @[axi4_to_ahb.scala 362:17] assign io_ahb_hwdata = buf_data; // @[axi4_to_ahb.scala 362:17]
@ -571,16 +571,16 @@ module axi4_to_ahb(
assign rvclkhdr_5_io_en = buf_data_wr_en & io_bus_clk_en; // @[el2_lib.scala 511:17] assign rvclkhdr_5_io_en = buf_data_wr_en & io_bus_clk_en; // @[el2_lib.scala 511:17]
assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
assign rvclkhdr_6_io_clk = clock; // @[el2_lib.scala 484:17] assign rvclkhdr_6_io_clk = clock; // @[el2_lib.scala 484:17]
assign rvclkhdr_6_io_en = io_bus_clk_en & _T_704; // @[el2_lib.scala 485:16] assign rvclkhdr_6_io_en = io_bus_clk_en & _T_703; // @[el2_lib.scala 485:16]
assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
assign rvclkhdr_7_io_clk = clock; // @[el2_lib.scala 484:17] assign rvclkhdr_7_io_clk = clock; // @[el2_lib.scala 484:17]
assign rvclkhdr_7_io_en = io_bus_clk_en; // @[el2_lib.scala 485:16] assign rvclkhdr_7_io_en = io_bus_clk_en; // @[el2_lib.scala 485:16]
assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
assign rvclkhdr_8_io_clk = clock; // @[el2_lib.scala 484:17] assign rvclkhdr_8_io_clk = clock; // @[el2_lib.scala 484:17]
assign rvclkhdr_8_io_en = io_bus_clk_en & _T_708; // @[el2_lib.scala 485:16] assign rvclkhdr_8_io_en = io_bus_clk_en & _T_707; // @[el2_lib.scala 485:16]
assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
assign rvclkhdr_9_io_clk = clock; // @[el2_lib.scala 484:17] assign rvclkhdr_9_io_clk = clock; // @[el2_lib.scala 484:17]
assign rvclkhdr_9_io_en = io_bus_clk_en & _T_711; // @[el2_lib.scala 485:16] assign rvclkhdr_9_io_en = io_bus_clk_en & _T_710; // @[el2_lib.scala 485:16]
assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
`ifdef RANDOMIZE_GARBAGE_ASSIGN `ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE `define RANDOMIZE
@ -765,14 +765,14 @@ end // initial
if (reset) begin if (reset) begin
wrbuf_vld <= 1'h0; wrbuf_vld <= 1'h0;
end else begin end else begin
wrbuf_vld <= _T_635 & _T_636; wrbuf_vld <= _T_634 & _T_635;
end end
end end
always @(posedge bus_clk or posedge reset) begin always @(posedge bus_clk or posedge reset) begin
if (reset) begin if (reset) begin
wrbuf_data_vld <= 1'h0; wrbuf_data_vld <= 1'h0;
end else begin end else begin
wrbuf_data_vld <= _T_640 & _T_636; wrbuf_data_vld <= _T_639 & _T_635;
end end
end end
always @(posedge ahbm_clk or posedge reset) begin always @(posedge ahbm_clk or posedge reset) begin
@ -807,7 +807,7 @@ end // initial
if (reset) begin if (reset) begin
cmd_doneQ <= 1'h0; cmd_doneQ <= 1'h0;
end else begin end else begin
cmd_doneQ <= _T_274 & _T_690; cmd_doneQ <= _T_274 & _T_689;
end end
end end
always @(posedge bus_clk or posedge reset) begin always @(posedge bus_clk or posedge reset) begin
@ -890,7 +890,7 @@ end // initial
always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin
if (reset) begin if (reset) begin
buf_data <= 64'h0; buf_data <= 64'h0;
end else if (_T_487) begin end else if (_T_486) begin
buf_data <= ahb_hrdata_q; buf_data <= ahb_hrdata_q;
end else begin end else begin
buf_data <= wrbuf_data; buf_data <= wrbuf_data;
@ -907,7 +907,7 @@ end // initial
if (reset) begin if (reset) begin
buf_addr <= 32'h0; buf_addr <= 32'h0;
end else begin end else begin
buf_addr <= {master_addr[31:3],_T_483}; buf_addr <= {master_addr[31:3],_T_482};
end end
end end
always @(posedge ahbm_clk or posedge reset) begin always @(posedge ahbm_clk or posedge reset) begin

311
src/main/scala/lib/ahb_to_axi4.scala
View File

@ -1,85 +1,240 @@
package lib package lib
import chisel3._ import chisel3._
import chisel3.util._ import chisel3.util._
import chisel3.experimental.chiselName //import chisel3.experimental.chiselName
@chiselName //@chiselName
class ahb_to_axi4 extends Module with el2_lib with RequireAsyncReset { class ahb_to_axi4 extends Module with el2_lib with RequireAsyncReset {
val TAG = 1 val io = IO(new Bundle {
val io = IO(new Bundle { val scan_mode = Input(Bool())
val scan_mode = Input(Bool()) val bus_clk_en = Input(Bool())
val bus_clk_en = Input(Bool()) val clk_override = Input(Bool())
val clk_override = Input(Bool()) val axi_awready = Input(Bool())
val axi_awready = Input(Bool()) val axi_wready = Input(Bool())
val axi_wready = Input(Bool()) val axi_bvalid = Input(Bool())
val axi_bvalid = Input(Bool()) val axi_bresp = Input(UInt(2.W))
val axi_bresp = Input(UInt(2.W)) val axi_bid = Input(UInt(TAG.W))
val axi_bid = Input(UInt(TAG.W)) val axi_arready = Input(Bool())
val axi_arready = Input(Bool()) val axi_rvalid = Input(Bool())
val axi_rvalid = Input(Bool()) val axi_rid = Input(UInt(TAG.W))
val axi_rid = Input(UInt(TAG.W)) val axi_rdata = Input(UInt(64.W))
val axi_rdata = Input(UInt(64.W)) val axi_rresp = Input(UInt(2.W))
val axi_rresp = Input(UInt(2.W)) val ahb_haddr = Input(UInt(32.W)) // ahb bus address
val ahb_haddr = Input(UInt(32.W)) // ahb bus address val ahb_hburst = Input(UInt(3.W)) // tied to 0
val ahb_hburst = Input(UInt(3.W)) // tied to 0 val ahb_hmastlock = Input(Bool()) // tied to 0
val ahb_hmastlock = Input(Bool()) // tied to 0 val ahb_hprot = Input(UInt(4.W)) // tied to 4'b0011
val ahb_hprot = Input(UInt(4.W)) // tied to 4'b0011 val ahb_hsize = Input(UInt(3.W)) // size of bus transaction (possible values 0 =1 =2 =3)
val ahb_hsize = Input(UInt(3.W)) // size of bus transaction (possible values 0 =1 =2 =3) val ahb_htrans = Input(UInt(2.W)) // Transaction type (possible values 0 =2 only right now)
val ahb_htrans = Input(UInt(2.W)) // Transaction type (possible values 0 =2 only right now) val ahb_hwrite = Input(Bool()) // ahb bus write
val ahb_hwrite = Input(Bool()) // ahb bus write val ahb_hwdata = Input(UInt(64.W)) // ahb bus write data
val ahb_hwdata = Input(UInt(64.W)) // ahb bus write data val ahb_hsel = Input(Bool()) // this slave was selected
val ahb_hsel = Input(Bool()) // this slave was selected val ahb_hreadyin = Input(Bool()) // previous hready was accepted or not
val ahb_hreadyin = Input(Bool()) // previous hready was accepted or not // outputs
// outputs val axi_awvalid = Output(Bool())
val axi_awvalid = Output(Bool()) val axi_awid = Output(UInt(TAG.W))
val axi_awid = Output(UInt(TAG.W)) val axi_awaddr = Output(UInt(32.W))
val axi_awaddr = Output(UInt(32.W)) val axi_awsize = Output(UInt(3.W))
val axi_awsize = Output(UInt(3.W)) val axi_awprot = Output(UInt(3.W))
val axi_awprot = Output(UInt(3.W)) val axi_awlen = Output(UInt(8.W))
val axi_awlen = Output(UInt(8.W)) val axi_awburst = Output(UInt(2.W))
val axi_awburst = Output(UInt(2.W)) val axi_wvalid = Output(Bool())
val axi_wvalid = Output(Bool()) val axi_wdata = Output(UInt(64.W))
val axi_wdata = Output(UInt(64.W)) val axi_wstrb = Output(UInt(8.W))
val axi_wstrb = Output(UInt(8.W)) val axi_wlast = Output(Bool())
val axi_wlast = Output(Bool()) val axi_bready = Output(Bool())
val axi_bready = Output(Bool()) val axi_arvalid = Output(Bool())
val axi_arvalid = Output(Bool()) val axi_arid = Output(UInt(TAG.W))
val axi_arid = Output(UInt(TAG.W)) val axi_araddr = Output(UInt(32.W))
val axi_araddr = Output(UInt(32.W)) val axi_arsize = Output(UInt(3.W))
val axi_arsize = Output(UInt(3.W)) val axi_arprot = Output(UInt(3.W))
val axi_arprot = Output(UInt(3.W)) val axi_arlen = Output(UInt(8.W))
val axi_arlen = Output(UInt(8.W)) val axi_arburst = Output(UInt(2.W))
val axi_arburst = Output(UInt(2.W)) val axi_rready = Output(Bool())
val axi_rready = Output(Bool()) val ahb_hrdata = Output(UInt(64.W)) // ahb bus read data
val ahb_hrdata = Output(UInt(64.W)) // ahb bus read data val ahb_hreadyout = Output(Bool()) // slave ready to accept transaction
val ahb_hreadyout = Output(Bool()) // slave ready to accept transaction val ahb_hresp = Output(Bool()) // slave response (high indicates erro)
val ahb_hresp = Output(Bool()) // slave response (high indicates erro) })
}) val idle:: wr :: rd :: pend :: Nil = Enum(4)
io.axi_awvalid := 0.U val TAG= 1
io.axi_awid := 0.U val master_wstrb = WireInit(0.U(8.W))
io.axi_awaddr := 0.U val buf_state_en = WireInit(false.B)
io.axi_awsize := 0.U
io.axi_awprot := 0.U // Buffer signals (one entry buffer)
io.axi_awlen := 0.U val buf_read_error_in = WireInit(false.B)
io.axi_awburst := 0.U val buf_read_error = WireInit(false.B)
io.axi_wvalid := 0.U val buf_rdata = WireInit(0.U(64.W))
io.axi_wdata := 0.U val ahb_hready = WireInit(Bool(), false.B)
io.axi_wstrb := 0.U val ahb_hready_q = WireInit(Bool(), false.B)
io.axi_wlast := 0.U val ahb_htrans_in = WireInit(0.U(2.W))
io.axi_bready := 0.U val ahb_htrans_q = WireInit(0.U(2.W))
io.axi_arvalid := 0.U val ahb_hsize_q = WireInit(0.U(3.W))
io.axi_arid := 0.U val ahb_hwrite_q = WireInit(Bool(), false.B)
io.axi_araddr := 0.U val ahb_haddr_q = WireInit(0.U(32.W))
io.axi_arsize := 0.U val ahb_hwdata_q = WireInit(0.U(64.W))
io.axi_arprot := 0.U val ahb_hresp_q = WireInit(Bool(), false.B)
io.axi_arlen := 0.U
io.axi_arburst := 0.U //Miscellaneous signals
io.axi_rready := 0.U val ahb_addr_in_iccm = WireInit(Bool(), false.B)
io.ahb_hrdata := 0.U val ahb_addr_in_iccm_region_nc = WireInit(Bool(), false.B)
io.ahb_hreadyout := 0.U
io.ahb_hresp := 0.U // signals needed for the read data coming back from the core and to block any further commands as AHB is a blocking bus
val buf_rdata_en = WireInit(Bool(), false.B)
val ahb_bus_addr_clk_en = WireInit(Bool(), false.B)
val buf_rdata_clk_en = WireInit(Bool(), false.B)
val ahb_clk = Wire(Clock())
val ahb_addr_clk = Wire(Clock())
val buf_rdata_clk = Wire(Clock())
// Command buffer is the holding station where we convert to AXI and send to core
val cmdbuf_wr_en = WireInit(Bool(), false.B)
val cmdbuf_rst = WireInit(Bool(), false.B)
val cmdbuf_full = WireInit(Bool(), false.B)
val cmdbuf_vld = WireInit(Bool(), false.B)
val cmdbuf_write = WireInit(Bool(), false.B)
val cmdbuf_size = WireInit(0.U(2.W))
val cmdbuf_wstrb = WireInit(0.U(8.W))
val cmdbuf_addr = WireInit(0.U(32.W))
val cmdbuf_wdata = WireInit(0.U(64.W))
val bus_clk = Wire(Clock())
// Address check dccm
val (ahb_addr_in_dccm, ahb_addr_in_dccm_region_nc) = rvrangecheck_ch(ahb_haddr_q.asUInt,aslong(DCCM_SADR).asUInt(),DCCM_SIZE)
// Address check iccm
if (ICCM_ENABLE == 1) {
ahb_addr_in_iccm := rvrangecheck_ch(ahb_haddr_q.asUInt, aslong(ICCM_SADR).asUInt(), ICCM_SIZE)._1
ahb_addr_in_iccm_region_nc := rvrangecheck_ch(ahb_haddr_q.asUInt, aslong(ICCM_SADR).asUInt(), ICCM_SIZE)._2
}
else {
ahb_addr_in_iccm := 0.U
ahb_addr_in_iccm_region_nc := 0.U
}
// PIC memory address check
val (ahb_addr_in_pic, ahb_addr_in_pic_region_nc) = rvrangecheck_ch(ahb_haddr_q.asUInt,aslong(PIC_BASE_ADDR).asUInt(),PIC_SIZE)
// FSM to control the bus states and when to block the hready and load the command buffer
val buf_state = WireInit(idle)
val buf_nxtstate = WireInit(idle)
buf_nxtstate := idle
buf_state_en := false.B
buf_rdata_en := false.B // signal to load the buffer when the core sends read data back
buf_read_error_in := false.B // signal indicating that an error came back with the read from the core
cmdbuf_wr_en := false.B // all clear from the gasket to load the buffer with the command for reads, command/dat for writes
switch(buf_state) {
is(idle) {
buf_nxtstate := Mux(io.ahb_hwrite, wr, rd)
buf_state_en := ahb_hready & io.ahb_htrans(1) & io.ahb_hsel // only transition on a valid hrtans
}
is(wr) { // Write command recieved last cycle
buf_nxtstate := Mux((io.ahb_hresp | (io.ahb_htrans(1, 0) === "b0".U) | !io.ahb_hsel).asBool, idle, Mux(io.ahb_hwrite, wr, rd))
buf_state_en := (!cmdbuf_full | io.ahb_hresp)
cmdbuf_wr_en := !cmdbuf_full & !(io.ahb_hresp | ((io.ahb_htrans(1, 0) === "b01".U) & io.ahb_hsel)) // Dont send command to the buffer in case of an error or when the master is not ready with the data now.
}
is(rd) { // Read command recieved last cycle.
buf_nxtstate := Mux(io.ahb_hresp, idle, pend) // If error go to idle, else wait for read data
buf_state_en := (!cmdbuf_full | io.ahb_hresp) // only when command can go, or if its an error
cmdbuf_wr_en := !io.ahb_hresp & !cmdbuf_full // send command only when no error
}
is(pend) { // Read Command has been sent. Waiting on Data.
buf_nxtstate := idle // go back for next command and present data next cycle
buf_state_en := io.axi_rvalid & !cmdbuf_write // read data is back
buf_rdata_en := buf_state_en // buffer the read data coming back from core
buf_read_error_in := buf_state_en & io.axi_rresp(1, 0).orR // buffer error flag if return has Error ( ECC )
}
}
buf_state := withClock(ahb_clk){RegEnable(buf_nxtstate,0.U,buf_state_en.asBool())}
master_wstrb := (Fill(8,ahb_hsize_q(2,0) === 0.U) & (1.U << ahb_haddr_q(2,0)).asUInt()) |
(Fill(8,ahb_hsize_q(2,0) === 1.U) & (3.U << ahb_haddr_q(2,0)).asUInt()) |
(Fill(8,ahb_hsize_q(2,0) === 2.U) & (15.U << ahb_haddr_q(2,0)).asUInt()) |
(Fill(8,ahb_hsize_q(2,0) === 3.U) & 255.U)
// AHB signals
io.ahb_hreadyout := Mux(io.ahb_hresp,(ahb_hresp_q & !ahb_hready_q), ((!cmdbuf_full | (buf_state === idle)) & !(buf_state === rd | buf_state === pend) & !buf_read_error))
ahb_hready := io.ahb_hreadyout & io.ahb_hreadyin
ahb_htrans_in := Fill(2,io.ahb_hsel) & io.ahb_htrans(1,0)
io.ahb_hrdata := buf_rdata(63,0)
io.ahb_hresp := ((ahb_htrans_q(1,0) =/= 0.U) & (buf_state =/= idle) &
((!(ahb_addr_in_dccm | ahb_addr_in_iccm)) | // request not for ICCM or DCCM
((ahb_addr_in_iccm | (ahb_addr_in_dccm & ahb_hwrite_q)) & !((ahb_hsize_q(1,0) === 2.U) | (ahb_hsize_q(1,0) === 3.U))) | // ICCM Rd/Wr OR DCCM Wr not the right size
((ahb_hsize_q(2,0) === 1.U) & ahb_haddr_q(0)) | // HW size but unaligned
((ahb_hsize_q(2,0) === 2.U) & (ahb_haddr_q(1,0)).orR) | // W size but unaligned
((ahb_hsize_q(2,0) === 3.U) & (ahb_haddr_q(2,0)).orR))) | // DW size but unaligned
buf_read_error | // Read ECC error
(ahb_hresp_q & !ahb_hready_q)
// Buffer signals - needed for the read data and ECC error response
buf_rdata := withClock(buf_rdata_clk){RegNext(io.axi_rdata,0.U)}
buf_read_error := withClock(ahb_clk){RegNext(buf_read_error_in,0.U)}
// All the Master signals are captured before presenting it to the command buffer. We check for Hresp before sending it to the cmd buffer.
ahb_hresp_q := withClock(ahb_clk){RegNext(io.ahb_hresp,0.U)}
ahb_hready_q := withClock(ahb_clk){RegNext(ahb_hready,0.U)}
ahb_htrans_q := withClock(ahb_clk){RegNext(ahb_htrans_in,0.U)}
ahb_hsize_q := withClock(ahb_addr_clk){RegNext(io.ahb_hsize,0.U)}
ahb_hwrite_q := withClock(ahb_addr_clk){RegNext(io.ahb_hwrite,0.U)}
ahb_haddr_q := withClock(ahb_addr_clk){RegNext(io.ahb_haddr,0.U)}
// Clock header logic
ahb_bus_addr_clk_en := io.bus_clk_en & (ahb_hready & io.ahb_htrans(1))
buf_rdata_clk_en := io.bus_clk_en & buf_rdata_en;
ahb_clk := rvclkhdr(clock, io.bus_clk_en, io.scan_mode)
ahb_addr_clk := rvclkhdr(clock, ahb_bus_addr_clk_en, io.scan_mode)
buf_rdata_clk := rvclkhdr(clock, buf_rdata_clk_en, io.scan_mode)
cmdbuf_rst := (((io.axi_awvalid & io.axi_awready) | (io.axi_arvalid & io.axi_arready)) & !cmdbuf_wr_en) | (io.ahb_hresp & !cmdbuf_write)
cmdbuf_full := (cmdbuf_vld & !((io.axi_awvalid & io.axi_awready) | (io.axi_arvalid & io.axi_arready)))
//rvdffsc
cmdbuf_vld := withClock(bus_clk) {
RegEnable("b1".U & Fill("b1".U.getWidth, cmdbuf_rst), 0.U, cmdbuf_wr_en.asBool())}
//dffs
cmdbuf_write := withClock(bus_clk) {
RegEnable(ahb_hwrite_q, 0.U, cmdbuf_wr_en.asBool())}
cmdbuf_size := withClock(bus_clk) {
RegEnable(ahb_hsize_q, 0.U, cmdbuf_wr_en.asBool())}
cmdbuf_wstrb := withClock(bus_clk) {
RegEnable(master_wstrb, 0.U, cmdbuf_wr_en.asBool())}
//rvdffe
cmdbuf_addr := RegEnable(ahb_haddr_q, 0.U, cmdbuf_wr_en.asBool())
cmdbuf_wdata := RegEnable(io.ahb_hwdata, 0.U, cmdbuf_wr_en.asBool())
// AXI Write Command Channel
io.axi_awvalid := cmdbuf_vld & cmdbuf_write
io.axi_awid := Fill(TAG, 0.U)
io.axi_awaddr := cmdbuf_addr
io.axi_awsize := Cat("b0".U, cmdbuf_size(1, 0))
io.axi_awprot := Fill(3, 0.U)
io.axi_awlen := Fill(8, 0.U)
io.axi_awburst := "b01".U
// AXI Write Data Channel - This is tied to the command channel as we only write the command buffer once we have the data.
io.axi_wvalid := cmdbuf_vld & cmdbuf_write
io.axi_wdata := cmdbuf_wdata
io.axi_wstrb := cmdbuf_wstrb
io.axi_wlast := "b1".U
// AXI Write Response - Always ready. AHB does not require a write response.
io.axi_bready := "b1".U
// AXI Read Channels
io.axi_arvalid := cmdbuf_vld & !cmdbuf_write
io.axi_arid := Fill(TAG, 0.U)
io.axi_araddr := cmdbuf_addr
io.axi_arsize := Cat("b0".U, cmdbuf_size(1, 0))
io.axi_arprot := Fill(3, 0.U)
io.axi_arlen := Fill(8, 0.U)
io.axi_arburst := "b01".U
// AXI Read Response Channel - Always ready as AHB reads are blocking and the the buffer is available for the read coming back always.
io.axi_rready := true.B
bus_clk := rvclkhdr(clock, io.bus_clk_en, io.scan_mode)
} }
object AHB_main extends App { object AHB_main extends App {
println("Generate Verilog") println("Generate Verilog")
println((new chisel3.stage.ChiselStage).emitVerilog(new ahb_to_axi4())) println((new chisel3.stage.ChiselStage).emitVerilog(new ahb_to_axi4()))}
}

14
src/main/scala/lib/axi4_to_ahb.scala
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@ -163,9 +163,9 @@ class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config
val byteen = WireInit(0.U(8.W)) val byteen = WireInit(0.U(8.W))
val size = ("b11".U & (Fill(2, (byteen(7, 0) === "hff".U))) | val size = ("b11".U & Fill(2, (byteen(7, 0) === "hff".U))) |
("b10".U & (Fill(2, (byteen(7, 0) === "hf0".U) | (byteen(7, 0) === "h0f".U)))) | ("b10".U & (Fill(2, ((byteen(7, 0) === "hf0".U) | (byteen(7, 0) === "h0f".U))))) |
("b01".U & (Fill(2, (byteen(7, 0) === "hc0".U) | (byteen(7, 0) === "h30".U) | (byteen(7, 0) === "h0c".U) | (byteen(7, 0) === "h03".U))))) ("b01".U & (Fill(2, ((byteen(7, 0) === "hc0".U) | (byteen(7, 0) === "h30".U) | (byteen(7, 0) === "h0c".U) | (byteen(7, 0) === "h03".U)))))
size size
} }
@ -223,7 +223,7 @@ class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config
//State machine //State machine
io.ahb_htrans := 0.U io.ahb_htrans := 0.U
master_ready := 1.U master_ready := 0.U
buf_state_en := false.B buf_state_en := false.B
buf_nxtstate := idle buf_nxtstate := idle
//buf_wr_en := 0.U //buf_wr_en := 0.U
@ -250,7 +250,7 @@ class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config
buf_data_wr_en := buf_state_en & (buf_nxtstate === cmd_wr) buf_data_wr_en := buf_state_en & (buf_nxtstate === cmd_wr)
buf_cmd_byte_ptr_en := buf_state_en buf_cmd_byte_ptr_en := buf_state_en
// ---------------------FROM FUNCTION CHECK LATER // ---------------------FROM FUNCTION CHECK LATER
buf_cmd_byte_ptr := Mux(buf_write_in.asBool(), (get_nxtbyte_ptr("b0".U, buf_byteen_in(7, 0), false.B)).asInstanceOf[UInt], master_addr(2, 0)) buf_cmd_byte_ptr := Mux(buf_write_in.asBool(), (get_nxtbyte_ptr(0.U, buf_byteen_in(7, 0), false.B)).asInstanceOf[UInt], master_addr(2, 0))
bypass_en := buf_state_en bypass_en := buf_state_en
rd_bypass_idle := bypass_en & (buf_nxtstate === cmd_rd) rd_bypass_idle := bypass_en & (buf_nxtstate === cmd_rd)
io.ahb_htrans := (Fill(2, bypass_en)) & "b10".U io.ahb_htrans := (Fill(2, bypass_en)) & "b10".U
@ -330,7 +330,7 @@ class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config
buf_cmd_byte_ptr_en := trxn_done | bypass_en buf_cmd_byte_ptr_en := trxn_done | bypass_en
//val tmp_func = get_nxtbyte_ptr(Fill(3,0.U),buf_byteen_in(7,0),false.B) //val tmp_func = get_nxtbyte_ptr(Fill(3,0.U),buf_byteen_in(7,0),false.B)
//val tmp_func2 = get_nxtbyte_ptr(buf_cmd_byte_ptrQ(2,0),buf_byteen(7,0),true.B) //val tmp_func2 = get_nxtbyte_ptr(buf_cmd_byte_ptrQ(2,0),buf_byteen(7,0),true.B)
buf_cmd_byte_ptr := Mux(bypass_en, get_nxtbyte_ptr(Fill(3, 0.U), buf_byteen_in(7, 0), false.B), Mux(trxn_done, get_nxtbyte_ptr(buf_cmd_byte_ptrQ(2, 0), buf_byteen(7, 0), true.B), buf_cmd_byte_ptrQ)) buf_cmd_byte_ptr := Mux(bypass_en, get_nxtbyte_ptr(0.U, buf_byteen_in(7, 0), false.B), Mux(trxn_done, get_nxtbyte_ptr(buf_cmd_byte_ptrQ(2, 0), buf_byteen(7, 0), true.B), buf_cmd_byte_ptrQ))
} }
is(done) { is(done) {
buf_nxtstate := idle buf_nxtstate := idle
@ -353,7 +353,7 @@ class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config
(master_byteen(7, 0) === "hf".U) | (master_byteen(7, 0) === "hf0".U) | (master_byteen(7, 0) === "hff".U))) (master_byteen(7, 0) === "hf".U) | (master_byteen(7, 0) === "hf0".U) | (master_byteen(7, 0) === "hff".U)))
// Generate the ahb signals // Generate the ahb signals
io.ahb_haddr := Mux(bypass_en.asBool(), Cat(master_addr(31, 3), buf_cmd_byte_ptr(2, 0)), Cat(buf_addr(31, 3), buf_cmd_byte_ptr(2, 0))) io.ahb_haddr := Mux(bypass_en.asBool(), Cat(master_addr(31, 3), buf_cmd_byte_ptr(2, 0)), Cat(buf_addr(31, 3), buf_cmd_byte_ptr(2, 0)))
io.ahb_hsize := Mux(bypass_en.asBool(), Cat("b0".U, (Fill(2, buf_aligned_in) & buf_size_in(1, 0))), (Cat("b0".U, (Fill(2, buf_aligned) & buf_size(1, 0))))) io.ahb_hsize := Mux(bypass_en.asBool(), Cat(0.U, (Fill(2, buf_aligned_in) & buf_size_in(1, 0))), (Cat("b0".U, (Fill(2, buf_aligned) & buf_size(1, 0)))))
io.ahb_hburst := "b0".U io.ahb_hburst := "b0".U
io.ahb_hmastlock := "b0".U io.ahb_hmastlock := "b0".U

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target/scala-2.12/classes/lib/AHB_main$.class
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target/scala-2.12/classes/lib/AHB_main$delayedInit$body.class
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target/scala-2.12/classes/lib/ahb_to_axi4$$anon$1.class
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target/scala-2.12/classes/lib/ahb_to_axi4.class
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