diff --git a/dbg.anno.json b/dbg.anno.json
index 02722551..d52e2ddf 100644
--- a/dbg.anno.json
+++ b/dbg.anno.json
@@ -66,6 +66,18 @@
     "target":"dbg.gated_latch",
     "resourceId":"/vsrc/gated_latch.v"
   },
+  {
+    "class":"firrtl.transforms.DontTouchAnnotation",
+    "target":"~dbg|dbg>rst_not"
+  },
+  {
+    "class":"firrtl.transforms.DontTouchAnnotation",
+    "target":"~dbg|dbg>rst_temp"
+  },
+  {
+    "class":"firrtl.transforms.DontTouchAnnotation",
+    "target":"~dbg|dbg>dbg_dm_rst_l"
+  },
   {
     "class":"firrtl.options.TargetDirAnnotation",
     "directory":"."
diff --git a/dbg.fir b/dbg.fir
index c9834437..7e454e1f 100644
--- a/dbg.fir
+++ b/dbg.fir
@@ -14,15 +14,15 @@ circuit dbg :
     input reset : Reset
     output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
     
-    inst clkhdr of gated_latch @[lib.scala 318:26]
+    inst clkhdr of gated_latch @[lib.scala 334:26]
     clkhdr.SE is invalid
     clkhdr.EN is invalid
     clkhdr.CK is invalid
     clkhdr.Q is invalid
-    io.l1clk <= clkhdr.Q @[lib.scala 319:14]
-    clkhdr.CK <= io.clk @[lib.scala 320:18]
-    clkhdr.EN <= io.en @[lib.scala 321:18]
-    clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
+    io.l1clk <= clkhdr.Q @[lib.scala 335:14]
+    clkhdr.CK <= io.clk @[lib.scala 336:18]
+    clkhdr.EN <= io.en @[lib.scala 337:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
     
   extmodule gated_latch_1 : 
     output Q : Clock
@@ -38,15 +38,15 @@ circuit dbg :
     input reset : Reset
     output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
     
-    inst clkhdr of gated_latch_1 @[lib.scala 318:26]
+    inst clkhdr of gated_latch_1 @[lib.scala 334:26]
     clkhdr.SE is invalid
     clkhdr.EN is invalid
     clkhdr.CK is invalid
     clkhdr.Q is invalid
-    io.l1clk <= clkhdr.Q @[lib.scala 319:14]
-    clkhdr.CK <= io.clk @[lib.scala 320:18]
-    clkhdr.EN <= io.en @[lib.scala 321:18]
-    clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
+    io.l1clk <= clkhdr.Q @[lib.scala 335:14]
+    clkhdr.CK <= io.clk @[lib.scala 336:18]
+    clkhdr.EN <= io.en @[lib.scala 337:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
     
   extmodule gated_latch_2 : 
     output Q : Clock
@@ -62,15 +62,15 @@ circuit dbg :
     input reset : Reset
     output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
     
-    inst clkhdr of gated_latch_2 @[lib.scala 318:26]
+    inst clkhdr of gated_latch_2 @[lib.scala 334:26]
     clkhdr.SE is invalid
     clkhdr.EN is invalid
     clkhdr.CK is invalid
     clkhdr.Q is invalid
-    io.l1clk <= clkhdr.Q @[lib.scala 319:14]
-    clkhdr.CK <= io.clk @[lib.scala 320:18]
-    clkhdr.EN <= io.en @[lib.scala 321:18]
-    clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
+    io.l1clk <= clkhdr.Q @[lib.scala 335:14]
+    clkhdr.CK <= io.clk @[lib.scala 336:18]
+    clkhdr.EN <= io.en @[lib.scala 337:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
     
   extmodule gated_latch_3 : 
     output Q : Clock
@@ -86,15 +86,15 @@ circuit dbg :
     input reset : Reset
     output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
     
-    inst clkhdr of gated_latch_3 @[lib.scala 318:26]
+    inst clkhdr of gated_latch_3 @[lib.scala 334:26]
     clkhdr.SE is invalid
     clkhdr.EN is invalid
     clkhdr.CK is invalid
     clkhdr.Q is invalid
-    io.l1clk <= clkhdr.Q @[lib.scala 319:14]
-    clkhdr.CK <= io.clk @[lib.scala 320:18]
-    clkhdr.EN <= io.en @[lib.scala 321:18]
-    clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
+    io.l1clk <= clkhdr.Q @[lib.scala 335:14]
+    clkhdr.CK <= io.clk @[lib.scala 336:18]
+    clkhdr.EN <= io.en @[lib.scala 337:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
     
   extmodule gated_latch_4 : 
     output Q : Clock
@@ -110,15 +110,15 @@ circuit dbg :
     input reset : Reset
     output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
     
-    inst clkhdr of gated_latch_4 @[lib.scala 318:26]
+    inst clkhdr of gated_latch_4 @[lib.scala 334:26]
     clkhdr.SE is invalid
     clkhdr.EN is invalid
     clkhdr.CK is invalid
     clkhdr.Q is invalid
-    io.l1clk <= clkhdr.Q @[lib.scala 319:14]
-    clkhdr.CK <= io.clk @[lib.scala 320:18]
-    clkhdr.EN <= io.en @[lib.scala 321:18]
-    clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
+    io.l1clk <= clkhdr.Q @[lib.scala 335:14]
+    clkhdr.CK <= io.clk @[lib.scala 336:18]
+    clkhdr.EN <= io.en @[lib.scala 337:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
     
   extmodule gated_latch_5 : 
     output Q : Clock
@@ -134,15 +134,15 @@ circuit dbg :
     input reset : Reset
     output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
     
-    inst clkhdr of gated_latch_5 @[lib.scala 318:26]
+    inst clkhdr of gated_latch_5 @[lib.scala 334:26]
     clkhdr.SE is invalid
     clkhdr.EN is invalid
     clkhdr.CK is invalid
     clkhdr.Q is invalid
-    io.l1clk <= clkhdr.Q @[lib.scala 319:14]
-    clkhdr.CK <= io.clk @[lib.scala 320:18]
-    clkhdr.EN <= io.en @[lib.scala 321:18]
-    clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
+    io.l1clk <= clkhdr.Q @[lib.scala 335:14]
+    clkhdr.CK <= io.clk @[lib.scala 336:18]
+    clkhdr.EN <= io.en @[lib.scala 337:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
     
   extmodule gated_latch_6 : 
     output Q : Clock
@@ -158,15 +158,15 @@ circuit dbg :
     input reset : Reset
     output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
     
-    inst clkhdr of gated_latch_6 @[lib.scala 318:26]
+    inst clkhdr of gated_latch_6 @[lib.scala 334:26]
     clkhdr.SE is invalid
     clkhdr.EN is invalid
     clkhdr.CK is invalid
     clkhdr.Q is invalid
-    io.l1clk <= clkhdr.Q @[lib.scala 319:14]
-    clkhdr.CK <= io.clk @[lib.scala 320:18]
-    clkhdr.EN <= io.en @[lib.scala 321:18]
-    clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
+    io.l1clk <= clkhdr.Q @[lib.scala 335:14]
+    clkhdr.CK <= io.clk @[lib.scala 336:18]
+    clkhdr.EN <= io.en @[lib.scala 337:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
     
   extmodule gated_latch_7 : 
     output Q : Clock
@@ -182,15 +182,15 @@ circuit dbg :
     input reset : Reset
     output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
     
-    inst clkhdr of gated_latch_7 @[lib.scala 318:26]
+    inst clkhdr of gated_latch_7 @[lib.scala 334:26]
     clkhdr.SE is invalid
     clkhdr.EN is invalid
     clkhdr.CK is invalid
     clkhdr.Q is invalid
-    io.l1clk <= clkhdr.Q @[lib.scala 319:14]
-    clkhdr.CK <= io.clk @[lib.scala 320:18]
-    clkhdr.EN <= io.en @[lib.scala 321:18]
-    clkhdr.SE <= io.scan_mode @[lib.scala 322:18]
+    io.l1clk <= clkhdr.Q @[lib.scala 335:14]
+    clkhdr.CK <= io.clk @[lib.scala 336:18]
+    clkhdr.EN <= io.en @[lib.scala 337:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
     
   module dbg : 
     input clock : Clock
@@ -262,71 +262,73 @@ circuit dbg :
     node _T_5 = neq(sb_state, UInt<4>("h00")) @[dbg.scala 96:63]
     node _T_6 = or(_T_4, _T_5) @[dbg.scala 96:51]
     node sb_free_clken = or(_T_6, io.clk_override) @[dbg.scala 96:86]
-    inst rvclkhdr of rvclkhdr @[lib.scala 327:22]
+    inst rvclkhdr of rvclkhdr @[lib.scala 343:22]
     rvclkhdr.clock <= clock
     rvclkhdr.reset <= reset
-    rvclkhdr.io.clk <= clock @[lib.scala 328:17]
-    rvclkhdr.io.en <= dbg_free_clken @[lib.scala 329:16]
-    rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 330:23]
-    inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 327:22]
+    rvclkhdr.io.clk <= clock @[lib.scala 344:17]
+    rvclkhdr.io.en <= dbg_free_clken @[lib.scala 345:16]
+    rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 346:23]
+    inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 343:22]
     rvclkhdr_1.clock <= clock
     rvclkhdr_1.reset <= reset
-    rvclkhdr_1.io.clk <= clock @[lib.scala 328:17]
-    rvclkhdr_1.io.en <= sb_free_clken @[lib.scala 329:16]
-    rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 330:23]
-    node _T_7 = bits(io.dbg_rst_l, 0, 0) @[dbg.scala 99:41]
-    node _T_8 = bits(dmcontrol_reg, 0, 0) @[dbg.scala 99:60]
-    node _T_9 = or(_T_8, io.scan_mode) @[dbg.scala 99:64]
-    node dbg_dm_rst_l = and(_T_7, _T_9) @[dbg.scala 99:44]
-    node _T_10 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 100:39]
-    node _T_11 = eq(_T_10, UInt<1>("h00")) @[dbg.scala 100:25]
-    node _T_12 = bits(_T_11, 0, 0) @[dbg.scala 100:50]
-    io.dbg_core_rst_l <= _T_12 @[dbg.scala 100:21]
-    node _T_13 = eq(io.dmi_reg_addr, UInt<6>("h038")) @[dbg.scala 101:36]
-    node _T_14 = and(_T_13, io.dmi_reg_en) @[dbg.scala 101:49]
-    node _T_15 = and(_T_14, io.dmi_reg_wr_en) @[dbg.scala 101:65]
-    node _T_16 = eq(sb_state, UInt<4>("h00")) @[dbg.scala 101:96]
-    node sbcs_wren = and(_T_15, _T_16) @[dbg.scala 101:84]
-    node _T_17 = bits(io.dmi_reg_wdata, 22, 22) @[dbg.scala 102:60]
-    node _T_18 = and(sbcs_wren, _T_17) @[dbg.scala 102:42]
-    node _T_19 = neq(sb_state, UInt<4>("h00")) @[dbg.scala 102:79]
-    node _T_20 = and(_T_19, io.dmi_reg_en) @[dbg.scala 102:102]
-    node _T_21 = eq(io.dmi_reg_addr, UInt<6>("h039")) @[dbg.scala 103:23]
-    node _T_22 = eq(io.dmi_reg_addr, UInt<6>("h03c")) @[dbg.scala 103:55]
-    node _T_23 = or(_T_21, _T_22) @[dbg.scala 103:36]
-    node _T_24 = eq(io.dmi_reg_addr, UInt<6>("h03d")) @[dbg.scala 103:87]
-    node _T_25 = or(_T_23, _T_24) @[dbg.scala 103:68]
-    node _T_26 = and(_T_20, _T_25) @[dbg.scala 102:118]
-    node sbcs_sbbusyerror_wren = or(_T_18, _T_26) @[dbg.scala 102:66]
-    node _T_27 = bits(io.dmi_reg_wdata, 22, 22) @[dbg.scala 105:61]
-    node _T_28 = and(sbcs_wren, _T_27) @[dbg.scala 105:43]
-    node sbcs_sbbusyerror_din = not(_T_28) @[dbg.scala 105:31]
-    node _T_29 = asAsyncReset(dbg_dm_rst_l) @[dbg.scala 106:80]
-    reg temp_sbcs_22 : UInt, rvclkhdr_1.io.l1clk with : (reset => (_T_29, UInt<1>("h00"))) @[Reg.scala 27:20]
+    rvclkhdr_1.io.clk <= clock @[lib.scala 344:17]
+    rvclkhdr_1.io.en <= sb_free_clken @[lib.scala 345:16]
+    rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 346:23]
+    node _T_7 = bits(io.dbg_rst_l, 0, 0) @[dbg.scala 99:42]
+    node _T_8 = bits(dmcontrol_reg, 0, 0) @[dbg.scala 99:61]
+    node _T_9 = or(_T_8, io.scan_mode) @[dbg.scala 99:65]
+    node _T_10 = and(_T_7, _T_9) @[dbg.scala 99:45]
+    node dbg_dm_rst_l = asAsyncReset(_T_10) @[dbg.scala 99:94]
+    node _T_11 = asUInt(dbg_dm_rst_l) @[dbg.scala 101:38]
+    node _T_12 = asUInt(reset) @[dbg.scala 101:55]
+    node _T_13 = and(_T_11, _T_12) @[dbg.scala 101:41]
+    node rst_temp = asAsyncReset(_T_13) @[dbg.scala 101:71]
+    node _T_14 = asUInt(dbg_dm_rst_l) @[dbg.scala 103:32]
+    node _T_15 = eq(_T_14, UInt<1>("h00")) @[dbg.scala 103:18]
+    node rst_not = asAsyncReset(_T_15) @[dbg.scala 103:52]
+    node _T_16 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 105:39]
+    node _T_17 = eq(_T_16, UInt<1>("h00")) @[dbg.scala 105:25]
+    node _T_18 = bits(_T_17, 0, 0) @[dbg.scala 105:50]
+    io.dbg_core_rst_l <= _T_18 @[dbg.scala 105:21]
+    node _T_19 = eq(io.dmi_reg_addr, UInt<6>("h038")) @[dbg.scala 106:36]
+    node _T_20 = and(_T_19, io.dmi_reg_en) @[dbg.scala 106:49]
+    node _T_21 = and(_T_20, io.dmi_reg_wr_en) @[dbg.scala 106:65]
+    node _T_22 = eq(sb_state, UInt<4>("h00")) @[dbg.scala 106:96]
+    node sbcs_wren = and(_T_21, _T_22) @[dbg.scala 106:84]
+    node _T_23 = bits(io.dmi_reg_wdata, 22, 22) @[dbg.scala 107:60]
+    node _T_24 = and(sbcs_wren, _T_23) @[dbg.scala 107:42]
+    node _T_25 = neq(sb_state, UInt<4>("h00")) @[dbg.scala 107:79]
+    node _T_26 = and(_T_25, io.dmi_reg_en) @[dbg.scala 107:102]
+    node _T_27 = eq(io.dmi_reg_addr, UInt<6>("h039")) @[dbg.scala 108:23]
+    node _T_28 = eq(io.dmi_reg_addr, UInt<6>("h03c")) @[dbg.scala 108:55]
+    node _T_29 = or(_T_27, _T_28) @[dbg.scala 108:36]
+    node _T_30 = eq(io.dmi_reg_addr, UInt<6>("h03d")) @[dbg.scala 108:87]
+    node _T_31 = or(_T_29, _T_30) @[dbg.scala 108:68]
+    node _T_32 = and(_T_26, _T_31) @[dbg.scala 107:118]
+    node sbcs_sbbusyerror_wren = or(_T_24, _T_32) @[dbg.scala 107:66]
+    node _T_33 = bits(io.dmi_reg_wdata, 22, 22) @[dbg.scala 110:61]
+    node _T_34 = and(sbcs_wren, _T_33) @[dbg.scala 110:43]
+    node sbcs_sbbusyerror_din = not(_T_34) @[dbg.scala 110:31]
+    reg temp_sbcs_22 : UInt, rvclkhdr_1.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20]
     when sbcs_sbbusyerror_wren : @[Reg.scala 28:19]
       temp_sbcs_22 <= sbcs_sbbusyerror_din @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    node _T_30 = asAsyncReset(dbg_dm_rst_l) @[dbg.scala 110:80]
-    reg temp_sbcs_21 : UInt, rvclkhdr_1.io.l1clk with : (reset => (_T_30, UInt<1>("h00"))) @[Reg.scala 27:20]
+    reg temp_sbcs_21 : UInt, rvclkhdr_1.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20]
     when sbcs_sbbusy_wren : @[Reg.scala 28:19]
       temp_sbcs_21 <= sbcs_sbbusy_din @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    node _T_31 = asAsyncReset(dbg_dm_rst_l) @[dbg.scala 114:80]
-    node _T_32 = bits(io.dmi_reg_wdata, 20, 20) @[dbg.scala 115:31]
-    reg temp_sbcs_20 : UInt, rvclkhdr_1.io.l1clk with : (reset => (_T_31, UInt<1>("h00"))) @[Reg.scala 27:20]
+    node _T_35 = bits(io.dmi_reg_wdata, 20, 20) @[dbg.scala 120:31]
+    reg temp_sbcs_20 : UInt, rvclkhdr_1.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20]
     when sbcs_wren : @[Reg.scala 28:19]
-      temp_sbcs_20 <= _T_32 @[Reg.scala 28:23]
+      temp_sbcs_20 <= _T_35 @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    node _T_33 = asAsyncReset(dbg_dm_rst_l) @[dbg.scala 118:83]
-    node _T_34 = bits(io.dmi_reg_wdata, 19, 15) @[dbg.scala 119:31]
-    reg temp_sbcs_19_15 : UInt, rvclkhdr_1.io.l1clk with : (reset => (_T_33, UInt<1>("h00"))) @[Reg.scala 27:20]
+    node _T_36 = bits(io.dmi_reg_wdata, 19, 15) @[dbg.scala 124:31]
+    reg temp_sbcs_19_15 : UInt, rvclkhdr_1.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20]
     when sbcs_wren : @[Reg.scala 28:19]
-      temp_sbcs_19_15 <= _T_34 @[Reg.scala 28:23]
+      temp_sbcs_19_15 <= _T_36 @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    node _T_35 = eq(dbg_dm_rst_l, UInt<1>("h00")) @[dbg.scala 122:57]
-    node _T_36 = asAsyncReset(_T_35) @[dbg.scala 122:84]
-    node _T_37 = bits(sbcs_sberror_din, 2, 0) @[dbg.scala 123:31]
-    reg temp_sbcs_14_12 : UInt, rvclkhdr_1.io.l1clk with : (reset => (_T_36, UInt<1>("h00"))) @[Reg.scala 27:20]
+    node _T_37 = bits(sbcs_sberror_din, 2, 0) @[dbg.scala 128:31]
+    reg temp_sbcs_14_12 : UInt, rvclkhdr_1.io.l1clk with : (reset => (rst_not, UInt<1>("h00"))) @[Reg.scala 27:20]
     when sbcs_sberror_wren : @[Reg.scala 28:19]
       temp_sbcs_14_12 <= _T_37 @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
@@ -338,961 +340,944 @@ circuit dbg :
     node _T_43 = cat(_T_42, temp_sbcs_22) @[Cat.scala 29:58]
     node _T_44 = cat(_T_43, _T_41) @[Cat.scala 29:58]
     node _T_45 = cat(_T_44, _T_40) @[Cat.scala 29:58]
-    sbcs_reg <= _T_45 @[dbg.scala 125:12]
-    node _T_46 = bits(sbcs_reg, 19, 17) @[dbg.scala 127:33]
-    node _T_47 = eq(_T_46, UInt<3>("h01")) @[dbg.scala 127:42]
-    node _T_48 = bits(sbaddress0_reg, 0, 0) @[dbg.scala 127:77]
-    node _T_49 = and(_T_47, _T_48) @[dbg.scala 127:61]
-    node _T_50 = bits(sbcs_reg, 19, 17) @[dbg.scala 128:14]
-    node _T_51 = eq(_T_50, UInt<3>("h02")) @[dbg.scala 128:23]
-    node _T_52 = bits(sbaddress0_reg, 1, 0) @[dbg.scala 128:58]
-    node _T_53 = orr(_T_52) @[dbg.scala 128:65]
-    node _T_54 = and(_T_51, _T_53) @[dbg.scala 128:42]
-    node _T_55 = or(_T_49, _T_54) @[dbg.scala 127:81]
-    node _T_56 = bits(sbcs_reg, 19, 17) @[dbg.scala 129:14]
-    node _T_57 = eq(_T_56, UInt<3>("h03")) @[dbg.scala 129:23]
-    node _T_58 = bits(sbaddress0_reg, 2, 0) @[dbg.scala 129:58]
-    node _T_59 = orr(_T_58) @[dbg.scala 129:65]
-    node _T_60 = and(_T_57, _T_59) @[dbg.scala 129:42]
-    node sbcs_unaligned = or(_T_55, _T_60) @[dbg.scala 128:69]
-    node sbcs_illegal_size = bits(sbcs_reg, 19, 19) @[dbg.scala 131:35]
-    node _T_61 = bits(sbcs_reg, 19, 17) @[dbg.scala 132:42]
-    node _T_62 = eq(_T_61, UInt<1>("h00")) @[dbg.scala 132:51]
+    sbcs_reg <= _T_45 @[dbg.scala 130:12]
+    node _T_46 = bits(sbcs_reg, 19, 17) @[dbg.scala 132:33]
+    node _T_47 = eq(_T_46, UInt<3>("h01")) @[dbg.scala 132:42]
+    node _T_48 = bits(sbaddress0_reg, 0, 0) @[dbg.scala 132:77]
+    node _T_49 = and(_T_47, _T_48) @[dbg.scala 132:61]
+    node _T_50 = bits(sbcs_reg, 19, 17) @[dbg.scala 133:14]
+    node _T_51 = eq(_T_50, UInt<3>("h02")) @[dbg.scala 133:23]
+    node _T_52 = bits(sbaddress0_reg, 1, 0) @[dbg.scala 133:58]
+    node _T_53 = orr(_T_52) @[dbg.scala 133:65]
+    node _T_54 = and(_T_51, _T_53) @[dbg.scala 133:42]
+    node _T_55 = or(_T_49, _T_54) @[dbg.scala 132:81]
+    node _T_56 = bits(sbcs_reg, 19, 17) @[dbg.scala 134:14]
+    node _T_57 = eq(_T_56, UInt<3>("h03")) @[dbg.scala 134:23]
+    node _T_58 = bits(sbaddress0_reg, 2, 0) @[dbg.scala 134:58]
+    node _T_59 = orr(_T_58) @[dbg.scala 134:65]
+    node _T_60 = and(_T_57, _T_59) @[dbg.scala 134:42]
+    node sbcs_unaligned = or(_T_55, _T_60) @[dbg.scala 133:69]
+    node sbcs_illegal_size = bits(sbcs_reg, 19, 19) @[dbg.scala 136:35]
+    node _T_61 = bits(sbcs_reg, 19, 17) @[dbg.scala 137:42]
+    node _T_62 = eq(_T_61, UInt<1>("h00")) @[dbg.scala 137:51]
     node _T_63 = bits(_T_62, 0, 0) @[Bitwise.scala 72:15]
     node _T_64 = mux(_T_63, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
-    node _T_65 = and(_T_64, UInt<4>("h01")) @[dbg.scala 132:64]
-    node _T_66 = bits(sbcs_reg, 19, 17) @[dbg.scala 132:100]
-    node _T_67 = eq(_T_66, UInt<1>("h01")) @[dbg.scala 132:109]
+    node _T_65 = and(_T_64, UInt<4>("h01")) @[dbg.scala 137:64]
+    node _T_66 = bits(sbcs_reg, 19, 17) @[dbg.scala 137:100]
+    node _T_67 = eq(_T_66, UInt<1>("h01")) @[dbg.scala 137:109]
     node _T_68 = bits(_T_67, 0, 0) @[Bitwise.scala 72:15]
     node _T_69 = mux(_T_68, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
-    node _T_70 = and(_T_69, UInt<4>("h02")) @[dbg.scala 132:122]
-    node _T_71 = or(_T_65, _T_70) @[dbg.scala 132:81]
-    node _T_72 = bits(sbcs_reg, 19, 17) @[dbg.scala 133:22]
-    node _T_73 = eq(_T_72, UInt<2>("h02")) @[dbg.scala 133:31]
+    node _T_70 = and(_T_69, UInt<4>("h02")) @[dbg.scala 137:122]
+    node _T_71 = or(_T_65, _T_70) @[dbg.scala 137:81]
+    node _T_72 = bits(sbcs_reg, 19, 17) @[dbg.scala 138:22]
+    node _T_73 = eq(_T_72, UInt<2>("h02")) @[dbg.scala 138:31]
     node _T_74 = bits(_T_73, 0, 0) @[Bitwise.scala 72:15]
     node _T_75 = mux(_T_74, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
-    node _T_76 = and(_T_75, UInt<4>("h04")) @[dbg.scala 133:44]
-    node _T_77 = or(_T_71, _T_76) @[dbg.scala 132:139]
-    node _T_78 = bits(sbcs_reg, 19, 17) @[dbg.scala 133:80]
-    node _T_79 = eq(_T_78, UInt<2>("h03")) @[dbg.scala 133:89]
+    node _T_76 = and(_T_75, UInt<4>("h04")) @[dbg.scala 138:44]
+    node _T_77 = or(_T_71, _T_76) @[dbg.scala 137:139]
+    node _T_78 = bits(sbcs_reg, 19, 17) @[dbg.scala 138:80]
+    node _T_79 = eq(_T_78, UInt<2>("h03")) @[dbg.scala 138:89]
     node _T_80 = bits(_T_79, 0, 0) @[Bitwise.scala 72:15]
     node _T_81 = mux(_T_80, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
-    node _T_82 = and(_T_81, UInt<4>("h08")) @[dbg.scala 133:102]
-    node sbaddress0_incr = or(_T_77, _T_82) @[dbg.scala 133:61]
-    node _T_83 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 135:41]
-    node _T_84 = eq(io.dmi_reg_addr, UInt<6>("h03c")) @[dbg.scala 135:79]
-    node sbdata0_reg_wren0 = and(_T_83, _T_84) @[dbg.scala 135:60]
-    node _T_85 = eq(sb_state, UInt<4>("h07")) @[dbg.scala 136:37]
-    node _T_86 = and(_T_85, sb_state_en) @[dbg.scala 136:60]
-    node _T_87 = eq(sbcs_sberror_wren, UInt<1>("h00")) @[dbg.scala 136:76]
-    node sbdata0_reg_wren1 = and(_T_86, _T_87) @[dbg.scala 136:74]
-    node sbdata0_reg_wren = or(sbdata0_reg_wren0, sbdata0_reg_wren1) @[dbg.scala 137:44]
-    node _T_88 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 138:41]
-    node _T_89 = eq(io.dmi_reg_addr, UInt<6>("h03d")) @[dbg.scala 138:79]
-    node sbdata1_reg_wren0 = and(_T_88, _T_89) @[dbg.scala 138:60]
-    node _T_90 = eq(sb_state, UInt<4>("h07")) @[dbg.scala 139:37]
-    node _T_91 = and(_T_90, sb_state_en) @[dbg.scala 139:60]
-    node _T_92 = eq(sbcs_sberror_wren, UInt<1>("h00")) @[dbg.scala 139:76]
-    node sbdata1_reg_wren1 = and(_T_91, _T_92) @[dbg.scala 139:74]
-    node sbdata1_reg_wren = or(sbdata1_reg_wren0, sbdata1_reg_wren1) @[dbg.scala 140:44]
+    node _T_82 = and(_T_81, UInt<4>("h08")) @[dbg.scala 138:102]
+    node sbaddress0_incr = or(_T_77, _T_82) @[dbg.scala 138:61]
+    node _T_83 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 140:41]
+    node _T_84 = eq(io.dmi_reg_addr, UInt<6>("h03c")) @[dbg.scala 140:79]
+    node sbdata0_reg_wren0 = and(_T_83, _T_84) @[dbg.scala 140:60]
+    node _T_85 = eq(sb_state, UInt<4>("h07")) @[dbg.scala 141:37]
+    node _T_86 = and(_T_85, sb_state_en) @[dbg.scala 141:60]
+    node _T_87 = eq(sbcs_sberror_wren, UInt<1>("h00")) @[dbg.scala 141:76]
+    node sbdata0_reg_wren1 = and(_T_86, _T_87) @[dbg.scala 141:74]
+    node sbdata0_reg_wren = or(sbdata0_reg_wren0, sbdata0_reg_wren1) @[dbg.scala 142:44]
+    node _T_88 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 143:41]
+    node _T_89 = eq(io.dmi_reg_addr, UInt<6>("h03d")) @[dbg.scala 143:79]
+    node sbdata1_reg_wren0 = and(_T_88, _T_89) @[dbg.scala 143:60]
+    node _T_90 = eq(sb_state, UInt<4>("h07")) @[dbg.scala 144:37]
+    node _T_91 = and(_T_90, sb_state_en) @[dbg.scala 144:60]
+    node _T_92 = eq(sbcs_sberror_wren, UInt<1>("h00")) @[dbg.scala 144:76]
+    node sbdata1_reg_wren1 = and(_T_91, _T_92) @[dbg.scala 144:74]
+    node sbdata1_reg_wren = or(sbdata1_reg_wren0, sbdata1_reg_wren1) @[dbg.scala 145:44]
     node _T_93 = bits(sbdata0_reg_wren0, 0, 0) @[Bitwise.scala 72:15]
     node _T_94 = mux(_T_93, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
-    node _T_95 = and(_T_94, io.dmi_reg_wdata) @[dbg.scala 141:49]
+    node _T_95 = and(_T_94, io.dmi_reg_wdata) @[dbg.scala 146:49]
     node _T_96 = bits(sbdata0_reg_wren1, 0, 0) @[Bitwise.scala 72:15]
     node _T_97 = mux(_T_96, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
-    node _T_98 = bits(sb_bus_rdata, 31, 0) @[dbg.scala 142:47]
-    node _T_99 = and(_T_97, _T_98) @[dbg.scala 142:33]
-    node sbdata0_din = or(_T_95, _T_99) @[dbg.scala 141:68]
+    node _T_98 = bits(sb_bus_rdata, 31, 0) @[dbg.scala 147:47]
+    node _T_99 = and(_T_97, _T_98) @[dbg.scala 147:33]
+    node sbdata0_din = or(_T_95, _T_99) @[dbg.scala 146:68]
     node _T_100 = bits(sbdata1_reg_wren0, 0, 0) @[Bitwise.scala 72:15]
     node _T_101 = mux(_T_100, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
-    node _T_102 = and(_T_101, io.dmi_reg_wdata) @[dbg.scala 144:49]
+    node _T_102 = and(_T_101, io.dmi_reg_wdata) @[dbg.scala 149:49]
     node _T_103 = bits(sbdata1_reg_wren1, 0, 0) @[Bitwise.scala 72:15]
     node _T_104 = mux(_T_103, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
-    node _T_105 = bits(sb_bus_rdata, 63, 32) @[dbg.scala 145:47]
-    node _T_106 = and(_T_104, _T_105) @[dbg.scala 145:33]
-    node sbdata1_din = or(_T_102, _T_106) @[dbg.scala 144:68]
-    node _T_107 = asAsyncReset(dbg_dm_rst_l) @[dbg.scala 147:58]
-    inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 352:23]
+    node _T_105 = bits(sb_bus_rdata, 63, 32) @[dbg.scala 150:47]
+    node _T_106 = and(_T_104, _T_105) @[dbg.scala 150:33]
+    node sbdata1_din = or(_T_102, _T_106) @[dbg.scala 149:68]
+    inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 368:23]
     rvclkhdr_2.clock <= clock
-    rvclkhdr_2.reset <= _T_107
-    rvclkhdr_2.io.clk <= clock @[lib.scala 354:18]
-    rvclkhdr_2.io.en <= sbdata0_reg_wren @[lib.scala 355:17]
-    rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 356:24]
-    reg sbdata0_reg : UInt, rvclkhdr_2.io.l1clk with : (reset => (_T_107, UInt<1>("h00"))) @[lib.scala 358:16]
-    sbdata0_reg <= sbdata0_din @[lib.scala 358:16]
-    node _T_108 = asAsyncReset(dbg_dm_rst_l) @[dbg.scala 151:58]
-    inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 352:23]
+    rvclkhdr_2.reset <= dbg_dm_rst_l
+    rvclkhdr_2.io.clk <= clock @[lib.scala 370:18]
+    rvclkhdr_2.io.en <= sbdata0_reg_wren @[lib.scala 371:17]
+    rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
+    reg sbdata0_reg : UInt, rvclkhdr_2.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[lib.scala 374:16]
+    sbdata0_reg <= sbdata0_din @[lib.scala 374:16]
+    inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 368:23]
     rvclkhdr_3.clock <= clock
-    rvclkhdr_3.reset <= _T_108
-    rvclkhdr_3.io.clk <= clock @[lib.scala 354:18]
-    rvclkhdr_3.io.en <= sbdata1_reg_wren @[lib.scala 355:17]
-    rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 356:24]
-    reg sbdata1_reg : UInt, rvclkhdr_3.io.l1clk with : (reset => (_T_108, UInt<1>("h00"))) @[lib.scala 358:16]
-    sbdata1_reg <= sbdata1_din @[lib.scala 358:16]
-    node _T_109 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 155:44]
-    node _T_110 = eq(io.dmi_reg_addr, UInt<6>("h039")) @[dbg.scala 155:82]
-    node sbaddress0_reg_wren0 = and(_T_109, _T_110) @[dbg.scala 155:63]
-    node sbaddress0_reg_wren = or(sbaddress0_reg_wren0, sbaddress0_reg_wren1) @[dbg.scala 156:50]
-    node _T_111 = bits(sbaddress0_reg_wren0, 0, 0) @[Bitwise.scala 72:15]
-    node _T_112 = mux(_T_111, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
-    node _T_113 = and(_T_112, io.dmi_reg_wdata) @[dbg.scala 157:59]
-    node _T_114 = bits(sbaddress0_reg_wren1, 0, 0) @[Bitwise.scala 72:15]
-    node _T_115 = mux(_T_114, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
-    node _T_116 = cat(UInt<28>("h00"), sbaddress0_incr) @[Cat.scala 29:58]
-    node _T_117 = add(sbaddress0_reg, _T_116) @[dbg.scala 158:54]
-    node _T_118 = tail(_T_117, 1) @[dbg.scala 158:54]
-    node _T_119 = and(_T_115, _T_118) @[dbg.scala 158:36]
-    node sbaddress0_reg_din = or(_T_113, _T_119) @[dbg.scala 157:78]
-    node _T_120 = asAsyncReset(dbg_dm_rst_l) @[dbg.scala 159:58]
-    inst rvclkhdr_4 of rvclkhdr_4 @[lib.scala 352:23]
+    rvclkhdr_3.reset <= dbg_dm_rst_l
+    rvclkhdr_3.io.clk <= clock @[lib.scala 370:18]
+    rvclkhdr_3.io.en <= sbdata1_reg_wren @[lib.scala 371:17]
+    rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
+    reg sbdata1_reg : UInt, rvclkhdr_3.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[lib.scala 374:16]
+    sbdata1_reg <= sbdata1_din @[lib.scala 374:16]
+    node _T_107 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 160:44]
+    node _T_108 = eq(io.dmi_reg_addr, UInt<6>("h039")) @[dbg.scala 160:82]
+    node sbaddress0_reg_wren0 = and(_T_107, _T_108) @[dbg.scala 160:63]
+    node sbaddress0_reg_wren = or(sbaddress0_reg_wren0, sbaddress0_reg_wren1) @[dbg.scala 161:50]
+    node _T_109 = bits(sbaddress0_reg_wren0, 0, 0) @[Bitwise.scala 72:15]
+    node _T_110 = mux(_T_109, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
+    node _T_111 = and(_T_110, io.dmi_reg_wdata) @[dbg.scala 162:59]
+    node _T_112 = bits(sbaddress0_reg_wren1, 0, 0) @[Bitwise.scala 72:15]
+    node _T_113 = mux(_T_112, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
+    node _T_114 = cat(UInt<28>("h00"), sbaddress0_incr) @[Cat.scala 29:58]
+    node _T_115 = add(sbaddress0_reg, _T_114) @[dbg.scala 163:54]
+    node _T_116 = tail(_T_115, 1) @[dbg.scala 163:54]
+    node _T_117 = and(_T_113, _T_116) @[dbg.scala 163:36]
+    node sbaddress0_reg_din = or(_T_111, _T_117) @[dbg.scala 162:78]
+    inst rvclkhdr_4 of rvclkhdr_4 @[lib.scala 368:23]
     rvclkhdr_4.clock <= clock
-    rvclkhdr_4.reset <= _T_120
-    rvclkhdr_4.io.clk <= clock @[lib.scala 354:18]
-    rvclkhdr_4.io.en <= sbaddress0_reg_wren @[lib.scala 355:17]
-    rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 356:24]
-    reg _T_121 : UInt, rvclkhdr_4.io.l1clk with : (reset => (_T_120, UInt<1>("h00"))) @[lib.scala 358:16]
-    _T_121 <= sbaddress0_reg_din @[lib.scala 358:16]
-    sbaddress0_reg <= _T_121 @[dbg.scala 159:18]
-    node _T_122 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 163:43]
-    node _T_123 = eq(io.dmi_reg_addr, UInt<6>("h039")) @[dbg.scala 163:81]
-    node _T_124 = and(_T_122, _T_123) @[dbg.scala 163:62]
-    node _T_125 = bits(sbcs_reg, 20, 20) @[dbg.scala 163:104]
-    node sbreadonaddr_access = and(_T_124, _T_125) @[dbg.scala 163:94]
-    node _T_126 = eq(io.dmi_reg_wr_en, UInt<1>("h00")) @[dbg.scala 164:45]
-    node _T_127 = and(io.dmi_reg_en, _T_126) @[dbg.scala 164:43]
-    node _T_128 = eq(io.dmi_reg_addr, UInt<6>("h03c")) @[dbg.scala 164:82]
-    node _T_129 = and(_T_127, _T_128) @[dbg.scala 164:63]
-    node _T_130 = bits(sbcs_reg, 15, 15) @[dbg.scala 164:105]
-    node sbreadondata_access = and(_T_129, _T_130) @[dbg.scala 164:95]
-    node _T_131 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 165:40]
-    node _T_132 = eq(io.dmi_reg_addr, UInt<6>("h03c")) @[dbg.scala 165:78]
-    node sbdata0wr_access = and(_T_131, _T_132) @[dbg.scala 165:59]
-    node _T_133 = eq(io.dmi_reg_addr, UInt<5>("h010")) @[dbg.scala 166:41]
-    node _T_134 = and(_T_133, io.dmi_reg_en) @[dbg.scala 166:54]
-    node dmcontrol_wren = and(_T_134, io.dmi_reg_wr_en) @[dbg.scala 166:70]
-    node _T_135 = asAsyncReset(dbg_dm_rst_l) @[dbg.scala 167:76]
-    node _T_136 = bits(io.dmi_reg_wdata, 31, 30) @[dbg.scala 169:27]
-    node _T_137 = bits(io.dmi_reg_wdata, 28, 28) @[dbg.scala 169:53]
-    node _T_138 = bits(io.dmi_reg_wdata, 1, 1) @[dbg.scala 169:75]
-    node _T_139 = cat(_T_136, _T_137) @[Cat.scala 29:58]
-    node _T_140 = cat(_T_139, _T_138) @[Cat.scala 29:58]
-    reg dm_temp : UInt, rvclkhdr.io.l1clk with : (reset => (_T_135, UInt<1>("h00"))) @[Reg.scala 27:20]
+    rvclkhdr_4.reset <= dbg_dm_rst_l
+    rvclkhdr_4.io.clk <= clock @[lib.scala 370:18]
+    rvclkhdr_4.io.en <= sbaddress0_reg_wren @[lib.scala 371:17]
+    rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
+    reg _T_118 : UInt, rvclkhdr_4.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[lib.scala 374:16]
+    _T_118 <= sbaddress0_reg_din @[lib.scala 374:16]
+    sbaddress0_reg <= _T_118 @[dbg.scala 164:18]
+    node _T_119 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 168:43]
+    node _T_120 = eq(io.dmi_reg_addr, UInt<6>("h039")) @[dbg.scala 168:81]
+    node _T_121 = and(_T_119, _T_120) @[dbg.scala 168:62]
+    node _T_122 = bits(sbcs_reg, 20, 20) @[dbg.scala 168:104]
+    node sbreadonaddr_access = and(_T_121, _T_122) @[dbg.scala 168:94]
+    node _T_123 = eq(io.dmi_reg_wr_en, UInt<1>("h00")) @[dbg.scala 169:45]
+    node _T_124 = and(io.dmi_reg_en, _T_123) @[dbg.scala 169:43]
+    node _T_125 = eq(io.dmi_reg_addr, UInt<6>("h03c")) @[dbg.scala 169:82]
+    node _T_126 = and(_T_124, _T_125) @[dbg.scala 169:63]
+    node _T_127 = bits(sbcs_reg, 15, 15) @[dbg.scala 169:105]
+    node sbreadondata_access = and(_T_126, _T_127) @[dbg.scala 169:95]
+    node _T_128 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 170:40]
+    node _T_129 = eq(io.dmi_reg_addr, UInt<6>("h03c")) @[dbg.scala 170:78]
+    node sbdata0wr_access = and(_T_128, _T_129) @[dbg.scala 170:59]
+    node _T_130 = eq(io.dmi_reg_addr, UInt<5>("h010")) @[dbg.scala 171:41]
+    node _T_131 = and(_T_130, io.dmi_reg_en) @[dbg.scala 171:54]
+    node dmcontrol_wren = and(_T_131, io.dmi_reg_wr_en) @[dbg.scala 171:70]
+    node _T_132 = bits(io.dmi_reg_wdata, 31, 30) @[dbg.scala 174:27]
+    node _T_133 = bits(io.dmi_reg_wdata, 28, 28) @[dbg.scala 174:53]
+    node _T_134 = bits(io.dmi_reg_wdata, 1, 1) @[dbg.scala 174:75]
+    node _T_135 = cat(_T_132, _T_133) @[Cat.scala 29:58]
+    node _T_136 = cat(_T_135, _T_134) @[Cat.scala 29:58]
+    reg dm_temp : UInt, rvclkhdr.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20]
     when dmcontrol_wren : @[Reg.scala 28:19]
-      dm_temp <= _T_140 @[Reg.scala 28:23]
+      dm_temp <= _T_136 @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    node _T_141 = asAsyncReset(io.dbg_rst_l) @[dbg.scala 173:76]
-    node _T_142 = bits(io.dmi_reg_wdata, 0, 0) @[dbg.scala 174:31]
-    reg dm_temp_0 : UInt, rvclkhdr.io.l1clk with : (reset => (_T_141, UInt<1>("h00"))) @[Reg.scala 27:20]
+    node _T_137 = asAsyncReset(io.dbg_rst_l) @[dbg.scala 178:76]
+    node _T_138 = bits(io.dmi_reg_wdata, 0, 0) @[dbg.scala 179:31]
+    reg dm_temp_0 : UInt, rvclkhdr.io.l1clk with : (reset => (_T_137, UInt<1>("h00"))) @[Reg.scala 27:20]
     when dmcontrol_wren : @[Reg.scala 28:19]
-      dm_temp_0 <= _T_142 @[Reg.scala 28:23]
+      dm_temp_0 <= _T_138 @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    node _T_143 = bits(dm_temp, 3, 2) @[dbg.scala 177:25]
-    node _T_144 = bits(dm_temp, 1, 1) @[dbg.scala 177:45]
-    node _T_145 = bits(dm_temp, 0, 0) @[dbg.scala 177:68]
-    node _T_146 = cat(UInt<26>("h00"), _T_145) @[Cat.scala 29:58]
-    node _T_147 = cat(_T_146, dm_temp_0) @[Cat.scala 29:58]
-    node _T_148 = cat(_T_143, UInt<1>("h00")) @[Cat.scala 29:58]
-    node _T_149 = cat(_T_148, _T_144) @[Cat.scala 29:58]
-    node temp = cat(_T_149, _T_147) @[Cat.scala 29:58]
-    dmcontrol_reg <= temp @[dbg.scala 178:17]
-    node _T_150 = asAsyncReset(dbg_dm_rst_l) @[dbg.scala 180:85]
-    reg dmcontrol_wren_Q : UInt<1>, rvclkhdr.io.l1clk with : (reset => (_T_150, UInt<1>("h00"))) @[dbg.scala 181:12]
-    dmcontrol_wren_Q <= dmcontrol_wren @[dbg.scala 181:12]
-    node _T_151 = bits(dmstatus_havereset, 0, 0) @[Bitwise.scala 72:15]
-    node _T_152 = mux(_T_151, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
-    node _T_153 = bits(dmstatus_resumeack, 0, 0) @[Bitwise.scala 72:15]
-    node _T_154 = mux(_T_153, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
-    node _T_155 = bits(dmstatus_unavail, 0, 0) @[Bitwise.scala 72:15]
-    node _T_156 = mux(_T_155, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
-    node _T_157 = bits(dmstatus_running, 0, 0) @[Bitwise.scala 72:15]
-    node _T_158 = mux(_T_157, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
-    node _T_159 = bits(dmstatus_halted, 0, 0) @[Bitwise.scala 72:15]
-    node _T_160 = mux(_T_159, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
-    node _T_161 = cat(UInt<3>("h00"), UInt<4>("h02")) @[Cat.scala 29:58]
-    node _T_162 = cat(_T_158, _T_160) @[Cat.scala 29:58]
-    node _T_163 = cat(_T_162, UInt<1>("h01")) @[Cat.scala 29:58]
-    node _T_164 = cat(_T_163, _T_161) @[Cat.scala 29:58]
-    node _T_165 = cat(UInt<2>("h00"), _T_156) @[Cat.scala 29:58]
-    node _T_166 = cat(UInt<12>("h00"), _T_152) @[Cat.scala 29:58]
-    node _T_167 = cat(_T_166, _T_154) @[Cat.scala 29:58]
-    node _T_168 = cat(_T_167, _T_165) @[Cat.scala 29:58]
-    node _T_169 = cat(_T_168, _T_164) @[Cat.scala 29:58]
-    dmstatus_reg <= _T_169 @[dbg.scala 184:16]
-    node _T_170 = eq(dbg_state, UInt<3>("h06")) @[dbg.scala 186:44]
-    node _T_171 = and(_T_170, io.dec_tlu_resume_ack) @[dbg.scala 186:66]
-    node _T_172 = bits(dmcontrol_reg, 30, 30) @[dbg.scala 186:127]
-    node _T_173 = eq(_T_172, UInt<1>("h00")) @[dbg.scala 186:113]
-    node _T_174 = and(dmstatus_resumeack, _T_173) @[dbg.scala 186:111]
-    node dmstatus_resumeack_wren = or(_T_171, _T_174) @[dbg.scala 186:90]
-    node _T_175 = eq(dbg_state, UInt<3>("h06")) @[dbg.scala 187:43]
-    node dmstatus_resumeack_din = and(_T_175, io.dec_tlu_resume_ack) @[dbg.scala 187:65]
-    node _T_176 = eq(io.dmi_reg_addr, UInt<5>("h010")) @[dbg.scala 188:50]
-    node _T_177 = bits(io.dmi_reg_wdata, 1, 1) @[dbg.scala 188:81]
-    node _T_178 = and(_T_176, _T_177) @[dbg.scala 188:63]
-    node _T_179 = and(_T_178, io.dmi_reg_en) @[dbg.scala 188:85]
-    node dmstatus_havereset_wren = and(_T_179, io.dmi_reg_wr_en) @[dbg.scala 188:101]
-    node _T_180 = eq(io.dmi_reg_addr, UInt<5>("h010")) @[dbg.scala 189:49]
-    node _T_181 = bits(io.dmi_reg_wdata, 28, 28) @[dbg.scala 189:80]
-    node _T_182 = and(_T_180, _T_181) @[dbg.scala 189:62]
-    node _T_183 = and(_T_182, io.dmi_reg_en) @[dbg.scala 189:85]
-    node dmstatus_havereset_rst = and(_T_183, io.dmi_reg_wr_en) @[dbg.scala 189:101]
-    node temp_rst = asUInt(reset) @[dbg.scala 190:30]
-    node _T_184 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 191:37]
-    node _T_185 = eq(temp_rst, UInt<1>("h00")) @[dbg.scala 191:43]
-    node _T_186 = or(_T_184, _T_185) @[dbg.scala 191:41]
-    node _T_187 = bits(_T_186, 0, 0) @[dbg.scala 191:62]
-    dmstatus_unavail <= _T_187 @[dbg.scala 191:20]
-    node _T_188 = or(dmstatus_unavail, dmstatus_halted) @[dbg.scala 192:42]
-    node _T_189 = not(_T_188) @[dbg.scala 192:23]
-    dmstatus_running <= _T_189 @[dbg.scala 192:20]
-    node _T_190 = asAsyncReset(dbg_dm_rst_l) @[dbg.scala 193:84]
-    reg _T_191 : UInt, rvclkhdr.io.l1clk with : (reset => (_T_190, UInt<1>("h00"))) @[Reg.scala 27:20]
+    node _T_139 = bits(dm_temp, 3, 2) @[dbg.scala 182:25]
+    node _T_140 = bits(dm_temp, 1, 1) @[dbg.scala 182:45]
+    node _T_141 = bits(dm_temp, 0, 0) @[dbg.scala 182:68]
+    node _T_142 = cat(UInt<26>("h00"), _T_141) @[Cat.scala 29:58]
+    node _T_143 = cat(_T_142, dm_temp_0) @[Cat.scala 29:58]
+    node _T_144 = cat(_T_139, UInt<1>("h00")) @[Cat.scala 29:58]
+    node _T_145 = cat(_T_144, _T_140) @[Cat.scala 29:58]
+    node temp = cat(_T_145, _T_143) @[Cat.scala 29:58]
+    dmcontrol_reg <= temp @[dbg.scala 183:17]
+    reg dmcontrol_wren_Q : UInt<1>, rvclkhdr.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[dbg.scala 186:12]
+    dmcontrol_wren_Q <= dmcontrol_wren @[dbg.scala 186:12]
+    node _T_146 = bits(dmstatus_havereset, 0, 0) @[Bitwise.scala 72:15]
+    node _T_147 = mux(_T_146, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
+    node _T_148 = bits(dmstatus_resumeack, 0, 0) @[Bitwise.scala 72:15]
+    node _T_149 = mux(_T_148, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
+    node _T_150 = bits(dmstatus_unavail, 0, 0) @[Bitwise.scala 72:15]
+    node _T_151 = mux(_T_150, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
+    node _T_152 = bits(dmstatus_running, 0, 0) @[Bitwise.scala 72:15]
+    node _T_153 = mux(_T_152, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
+    node _T_154 = bits(dmstatus_halted, 0, 0) @[Bitwise.scala 72:15]
+    node _T_155 = mux(_T_154, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
+    node _T_156 = cat(UInt<3>("h00"), UInt<4>("h02")) @[Cat.scala 29:58]
+    node _T_157 = cat(_T_153, _T_155) @[Cat.scala 29:58]
+    node _T_158 = cat(_T_157, UInt<1>("h01")) @[Cat.scala 29:58]
+    node _T_159 = cat(_T_158, _T_156) @[Cat.scala 29:58]
+    node _T_160 = cat(UInt<2>("h00"), _T_151) @[Cat.scala 29:58]
+    node _T_161 = cat(UInt<12>("h00"), _T_147) @[Cat.scala 29:58]
+    node _T_162 = cat(_T_161, _T_149) @[Cat.scala 29:58]
+    node _T_163 = cat(_T_162, _T_160) @[Cat.scala 29:58]
+    node _T_164 = cat(_T_163, _T_159) @[Cat.scala 29:58]
+    dmstatus_reg <= _T_164 @[dbg.scala 189:16]
+    node _T_165 = eq(dbg_state, UInt<3>("h06")) @[dbg.scala 191:44]
+    node _T_166 = and(_T_165, io.dec_tlu_resume_ack) @[dbg.scala 191:66]
+    node _T_167 = bits(dmcontrol_reg, 30, 30) @[dbg.scala 191:127]
+    node _T_168 = eq(_T_167, UInt<1>("h00")) @[dbg.scala 191:113]
+    node _T_169 = and(dmstatus_resumeack, _T_168) @[dbg.scala 191:111]
+    node dmstatus_resumeack_wren = or(_T_166, _T_169) @[dbg.scala 191:90]
+    node _T_170 = eq(dbg_state, UInt<3>("h06")) @[dbg.scala 192:43]
+    node dmstatus_resumeack_din = and(_T_170, io.dec_tlu_resume_ack) @[dbg.scala 192:65]
+    node _T_171 = eq(io.dmi_reg_addr, UInt<5>("h010")) @[dbg.scala 193:50]
+    node _T_172 = bits(io.dmi_reg_wdata, 1, 1) @[dbg.scala 193:81]
+    node _T_173 = and(_T_171, _T_172) @[dbg.scala 193:63]
+    node _T_174 = and(_T_173, io.dmi_reg_en) @[dbg.scala 193:85]
+    node dmstatus_havereset_wren = and(_T_174, io.dmi_reg_wr_en) @[dbg.scala 193:101]
+    node _T_175 = eq(io.dmi_reg_addr, UInt<5>("h010")) @[dbg.scala 194:49]
+    node _T_176 = bits(io.dmi_reg_wdata, 28, 28) @[dbg.scala 194:80]
+    node _T_177 = and(_T_175, _T_176) @[dbg.scala 194:62]
+    node _T_178 = and(_T_177, io.dmi_reg_en) @[dbg.scala 194:85]
+    node dmstatus_havereset_rst = and(_T_178, io.dmi_reg_wr_en) @[dbg.scala 194:101]
+    node temp_rst = asUInt(reset) @[dbg.scala 195:30]
+    node _T_179 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 196:37]
+    node _T_180 = eq(temp_rst, UInt<1>("h00")) @[dbg.scala 196:43]
+    node _T_181 = or(_T_179, _T_180) @[dbg.scala 196:41]
+    node _T_182 = bits(_T_181, 0, 0) @[dbg.scala 196:62]
+    dmstatus_unavail <= _T_182 @[dbg.scala 196:20]
+    node _T_183 = or(dmstatus_unavail, dmstatus_halted) @[dbg.scala 197:42]
+    node _T_184 = not(_T_183) @[dbg.scala 197:23]
+    dmstatus_running <= _T_184 @[dbg.scala 197:20]
+    reg _T_185 : UInt, rvclkhdr.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20]
     when dmstatus_resumeack_wren : @[Reg.scala 28:19]
-      _T_191 <= dmstatus_resumeack_din @[Reg.scala 28:23]
+      _T_185 <= dmstatus_resumeack_din @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    dmstatus_resumeack <= _T_191 @[dbg.scala 193:22]
-    node _T_192 = asAsyncReset(dbg_dm_rst_l) @[dbg.scala 197:81]
-    node _T_193 = eq(io.dec_tlu_mpc_halted_only, UInt<1>("h00")) @[dbg.scala 198:37]
-    node _T_194 = and(io.dec_tlu_dbg_halted, _T_193) @[dbg.scala 198:35]
-    reg _T_195 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (_T_192, UInt<1>("h00"))) @[dbg.scala 198:12]
-    _T_195 <= _T_194 @[dbg.scala 198:12]
-    dmstatus_halted <= _T_195 @[dbg.scala 197:19]
-    node _T_196 = asAsyncReset(dbg_dm_rst_l) @[dbg.scala 201:84]
-    node _T_197 = mux(dmstatus_havereset_wren, UInt<1>("h01"), dmstatus_havereset) @[dbg.scala 202:16]
-    node _T_198 = eq(dmstatus_havereset_rst, UInt<1>("h00")) @[dbg.scala 202:72]
-    node _T_199 = and(_T_197, _T_198) @[dbg.scala 202:70]
-    reg _T_200 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (_T_196, UInt<1>("h00"))) @[dbg.scala 202:12]
-    _T_200 <= _T_199 @[dbg.scala 202:12]
-    dmstatus_havereset <= _T_200 @[dbg.scala 201:22]
+    dmstatus_resumeack <= _T_185 @[dbg.scala 198:22]
+    node _T_186 = eq(io.dec_tlu_mpc_halted_only, UInt<1>("h00")) @[dbg.scala 203:37]
+    node _T_187 = and(io.dec_tlu_dbg_halted, _T_186) @[dbg.scala 203:35]
+    reg _T_188 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[dbg.scala 203:12]
+    _T_188 <= _T_187 @[dbg.scala 203:12]
+    dmstatus_halted <= _T_188 @[dbg.scala 202:19]
+    node _T_189 = mux(dmstatus_havereset_wren, UInt<1>("h01"), dmstatus_havereset) @[dbg.scala 207:16]
+    node _T_190 = eq(dmstatus_havereset_rst, UInt<1>("h00")) @[dbg.scala 207:72]
+    node _T_191 = and(_T_189, _T_190) @[dbg.scala 207:70]
+    reg _T_192 : UInt<1>, rvclkhdr.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[dbg.scala 207:12]
+    _T_192 <= _T_191 @[dbg.scala 207:12]
+    dmstatus_havereset <= _T_192 @[dbg.scala 206:22]
     node haltsum0_reg = cat(UInt<31>("h00"), dmstatus_halted) @[Cat.scala 29:58]
     wire abstractcs_reg : UInt<32>
     abstractcs_reg <= UInt<32>("h02")
-    node _T_201 = bits(abstractcs_reg, 12, 12) @[dbg.scala 208:45]
-    node _T_202 = and(_T_201, io.dmi_reg_en) @[dbg.scala 208:50]
-    node _T_203 = eq(io.dmi_reg_addr, UInt<5>("h016")) @[dbg.scala 208:106]
-    node _T_204 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[dbg.scala 208:138]
-    node _T_205 = or(_T_203, _T_204) @[dbg.scala 208:119]
-    node _T_206 = and(io.dmi_reg_wr_en, _T_205) @[dbg.scala 208:86]
-    node _T_207 = eq(io.dmi_reg_addr, UInt<3>("h04")) @[dbg.scala 208:171]
-    node _T_208 = or(_T_206, _T_207) @[dbg.scala 208:152]
-    node abstractcs_error_sel0 = and(_T_202, _T_208) @[dbg.scala 208:66]
-    node _T_209 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 209:45]
-    node _T_210 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[dbg.scala 209:83]
-    node _T_211 = and(_T_209, _T_210) @[dbg.scala 209:64]
-    node _T_212 = bits(io.dmi_reg_wdata, 31, 24) @[dbg.scala 209:117]
-    node _T_213 = eq(_T_212, UInt<1>("h00")) @[dbg.scala 209:126]
-    node _T_214 = bits(io.dmi_reg_wdata, 31, 24) @[dbg.scala 209:154]
-    node _T_215 = eq(_T_214, UInt<2>("h02")) @[dbg.scala 209:163]
-    node _T_216 = or(_T_213, _T_215) @[dbg.scala 209:135]
-    node _T_217 = eq(_T_216, UInt<1>("h00")) @[dbg.scala 209:98]
-    node abstractcs_error_sel1 = and(_T_211, _T_217) @[dbg.scala 209:96]
-    node abstractcs_error_sel2 = and(io.core_dbg_cmd_done, io.core_dbg_cmd_fail) @[dbg.scala 210:52]
-    node _T_218 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 211:45]
-    node _T_219 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[dbg.scala 211:83]
-    node _T_220 = and(_T_218, _T_219) @[dbg.scala 211:64]
-    node _T_221 = bits(dmstatus_reg, 9, 9) @[dbg.scala 211:111]
-    node _T_222 = eq(_T_221, UInt<1>("h00")) @[dbg.scala 211:98]
-    node abstractcs_error_sel3 = and(_T_220, _T_222) @[dbg.scala 211:96]
-    node _T_223 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[dbg.scala 212:48]
-    node _T_224 = and(_T_223, io.dmi_reg_en) @[dbg.scala 212:61]
-    node _T_225 = and(_T_224, io.dmi_reg_wr_en) @[dbg.scala 212:77]
-    node _T_226 = bits(io.dmi_reg_wdata, 22, 20) @[dbg.scala 213:23]
-    node _T_227 = neq(_T_226, UInt<3>("h02")) @[dbg.scala 213:32]
-    node _T_228 = bits(io.dmi_reg_wdata, 31, 24) @[dbg.scala 213:71]
-    node _T_229 = eq(_T_228, UInt<2>("h02")) @[dbg.scala 213:80]
-    node _T_230 = bits(data1_reg, 1, 0) @[dbg.scala 213:104]
-    node _T_231 = orr(_T_230) @[dbg.scala 213:111]
-    node _T_232 = and(_T_229, _T_231) @[dbg.scala 213:92]
-    node _T_233 = or(_T_227, _T_232) @[dbg.scala 213:51]
-    node abstractcs_error_sel4 = and(_T_225, _T_233) @[dbg.scala 212:96]
-    node _T_234 = eq(io.dmi_reg_addr, UInt<5>("h016")) @[dbg.scala 215:48]
-    node _T_235 = and(_T_234, io.dmi_reg_en) @[dbg.scala 215:61]
-    node abstractcs_error_sel5 = and(_T_235, io.dmi_reg_wr_en) @[dbg.scala 215:77]
-    node _T_236 = or(abstractcs_error_sel0, abstractcs_error_sel1) @[dbg.scala 216:54]
-    node _T_237 = or(_T_236, abstractcs_error_sel2) @[dbg.scala 216:78]
-    node _T_238 = or(_T_237, abstractcs_error_sel3) @[dbg.scala 216:102]
-    node _T_239 = or(_T_238, abstractcs_error_sel4) @[dbg.scala 216:126]
-    node abstractcs_error_selor = or(_T_239, abstractcs_error_sel5) @[dbg.scala 216:150]
-    node _T_240 = bits(abstractcs_error_sel0, 0, 0) @[Bitwise.scala 72:15]
-    node _T_241 = mux(_T_240, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
-    node _T_242 = and(_T_241, UInt<3>("h01")) @[dbg.scala 217:62]
-    node _T_243 = bits(abstractcs_error_sel1, 0, 0) @[Bitwise.scala 72:15]
+    node _T_193 = bits(abstractcs_reg, 12, 12) @[dbg.scala 213:45]
+    node _T_194 = and(_T_193, io.dmi_reg_en) @[dbg.scala 213:50]
+    node _T_195 = eq(io.dmi_reg_addr, UInt<5>("h016")) @[dbg.scala 213:106]
+    node _T_196 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[dbg.scala 213:138]
+    node _T_197 = or(_T_195, _T_196) @[dbg.scala 213:119]
+    node _T_198 = and(io.dmi_reg_wr_en, _T_197) @[dbg.scala 213:86]
+    node _T_199 = eq(io.dmi_reg_addr, UInt<3>("h04")) @[dbg.scala 213:171]
+    node _T_200 = or(_T_198, _T_199) @[dbg.scala 213:152]
+    node abstractcs_error_sel0 = and(_T_194, _T_200) @[dbg.scala 213:66]
+    node _T_201 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 214:45]
+    node _T_202 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[dbg.scala 214:83]
+    node _T_203 = and(_T_201, _T_202) @[dbg.scala 214:64]
+    node _T_204 = bits(io.dmi_reg_wdata, 31, 24) @[dbg.scala 214:117]
+    node _T_205 = eq(_T_204, UInt<1>("h00")) @[dbg.scala 214:126]
+    node _T_206 = bits(io.dmi_reg_wdata, 31, 24) @[dbg.scala 214:154]
+    node _T_207 = eq(_T_206, UInt<2>("h02")) @[dbg.scala 214:163]
+    node _T_208 = or(_T_205, _T_207) @[dbg.scala 214:135]
+    node _T_209 = eq(_T_208, UInt<1>("h00")) @[dbg.scala 214:98]
+    node abstractcs_error_sel1 = and(_T_203, _T_209) @[dbg.scala 214:96]
+    node abstractcs_error_sel2 = and(io.core_dbg_cmd_done, io.core_dbg_cmd_fail) @[dbg.scala 215:52]
+    node _T_210 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 216:45]
+    node _T_211 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[dbg.scala 216:83]
+    node _T_212 = and(_T_210, _T_211) @[dbg.scala 216:64]
+    node _T_213 = bits(dmstatus_reg, 9, 9) @[dbg.scala 216:111]
+    node _T_214 = eq(_T_213, UInt<1>("h00")) @[dbg.scala 216:98]
+    node abstractcs_error_sel3 = and(_T_212, _T_214) @[dbg.scala 216:96]
+    node _T_215 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[dbg.scala 217:48]
+    node _T_216 = and(_T_215, io.dmi_reg_en) @[dbg.scala 217:61]
+    node _T_217 = and(_T_216, io.dmi_reg_wr_en) @[dbg.scala 217:77]
+    node _T_218 = bits(io.dmi_reg_wdata, 22, 20) @[dbg.scala 218:23]
+    node _T_219 = neq(_T_218, UInt<3>("h02")) @[dbg.scala 218:32]
+    node _T_220 = bits(io.dmi_reg_wdata, 31, 24) @[dbg.scala 218:71]
+    node _T_221 = eq(_T_220, UInt<2>("h02")) @[dbg.scala 218:80]
+    node _T_222 = bits(data1_reg, 1, 0) @[dbg.scala 218:104]
+    node _T_223 = orr(_T_222) @[dbg.scala 218:111]
+    node _T_224 = and(_T_221, _T_223) @[dbg.scala 218:92]
+    node _T_225 = or(_T_219, _T_224) @[dbg.scala 218:51]
+    node abstractcs_error_sel4 = and(_T_217, _T_225) @[dbg.scala 217:96]
+    node _T_226 = eq(io.dmi_reg_addr, UInt<5>("h016")) @[dbg.scala 220:48]
+    node _T_227 = and(_T_226, io.dmi_reg_en) @[dbg.scala 220:61]
+    node abstractcs_error_sel5 = and(_T_227, io.dmi_reg_wr_en) @[dbg.scala 220:77]
+    node _T_228 = or(abstractcs_error_sel0, abstractcs_error_sel1) @[dbg.scala 221:54]
+    node _T_229 = or(_T_228, abstractcs_error_sel2) @[dbg.scala 221:78]
+    node _T_230 = or(_T_229, abstractcs_error_sel3) @[dbg.scala 221:102]
+    node _T_231 = or(_T_230, abstractcs_error_sel4) @[dbg.scala 221:126]
+    node abstractcs_error_selor = or(_T_231, abstractcs_error_sel5) @[dbg.scala 221:150]
+    node _T_232 = bits(abstractcs_error_sel0, 0, 0) @[Bitwise.scala 72:15]
+    node _T_233 = mux(_T_232, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
+    node _T_234 = and(_T_233, UInt<3>("h01")) @[dbg.scala 222:62]
+    node _T_235 = bits(abstractcs_error_sel1, 0, 0) @[Bitwise.scala 72:15]
+    node _T_236 = mux(_T_235, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
+    node _T_237 = and(_T_236, UInt<3>("h02")) @[dbg.scala 223:37]
+    node _T_238 = or(_T_234, _T_237) @[dbg.scala 222:79]
+    node _T_239 = bits(abstractcs_error_sel2, 0, 0) @[Bitwise.scala 72:15]
+    node _T_240 = mux(_T_239, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
+    node _T_241 = and(_T_240, UInt<3>("h03")) @[dbg.scala 224:37]
+    node _T_242 = or(_T_238, _T_241) @[dbg.scala 223:54]
+    node _T_243 = bits(abstractcs_error_sel3, 0, 0) @[Bitwise.scala 72:15]
     node _T_244 = mux(_T_243, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
-    node _T_245 = and(_T_244, UInt<3>("h02")) @[dbg.scala 218:37]
-    node _T_246 = or(_T_242, _T_245) @[dbg.scala 217:79]
-    node _T_247 = bits(abstractcs_error_sel2, 0, 0) @[Bitwise.scala 72:15]
+    node _T_245 = and(_T_244, UInt<3>("h04")) @[dbg.scala 225:37]
+    node _T_246 = or(_T_242, _T_245) @[dbg.scala 224:54]
+    node _T_247 = bits(abstractcs_error_sel4, 0, 0) @[Bitwise.scala 72:15]
     node _T_248 = mux(_T_247, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
-    node _T_249 = and(_T_248, UInt<3>("h03")) @[dbg.scala 219:37]
-    node _T_250 = or(_T_246, _T_249) @[dbg.scala 218:54]
-    node _T_251 = bits(abstractcs_error_sel3, 0, 0) @[Bitwise.scala 72:15]
+    node _T_249 = and(_T_248, UInt<3>("h07")) @[dbg.scala 226:37]
+    node _T_250 = or(_T_246, _T_249) @[dbg.scala 225:54]
+    node _T_251 = bits(abstractcs_error_sel5, 0, 0) @[Bitwise.scala 72:15]
     node _T_252 = mux(_T_251, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
-    node _T_253 = and(_T_252, UInt<3>("h04")) @[dbg.scala 220:37]
-    node _T_254 = or(_T_250, _T_253) @[dbg.scala 219:54]
-    node _T_255 = bits(abstractcs_error_sel4, 0, 0) @[Bitwise.scala 72:15]
-    node _T_256 = mux(_T_255, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
-    node _T_257 = and(_T_256, UInt<3>("h07")) @[dbg.scala 221:37]
-    node _T_258 = or(_T_254, _T_257) @[dbg.scala 220:54]
-    node _T_259 = bits(abstractcs_error_sel5, 0, 0) @[Bitwise.scala 72:15]
-    node _T_260 = mux(_T_259, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
-    node _T_261 = bits(io.dmi_reg_wdata, 10, 8) @[dbg.scala 222:57]
-    node _T_262 = not(_T_261) @[dbg.scala 222:40]
-    node _T_263 = and(_T_260, _T_262) @[dbg.scala 222:37]
-    node _T_264 = bits(abstractcs_reg, 10, 8) @[dbg.scala 222:91]
-    node _T_265 = and(_T_263, _T_264) @[dbg.scala 222:75]
-    node _T_266 = or(_T_258, _T_265) @[dbg.scala 221:54]
-    node _T_267 = not(abstractcs_error_selor) @[dbg.scala 223:15]
-    node _T_268 = bits(_T_267, 0, 0) @[Bitwise.scala 72:15]
-    node _T_269 = mux(_T_268, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
-    node _T_270 = bits(abstractcs_reg, 10, 8) @[dbg.scala 223:66]
-    node _T_271 = and(_T_269, _T_270) @[dbg.scala 223:50]
-    node abstractcs_error_din = or(_T_266, _T_271) @[dbg.scala 222:100]
-    node _T_272 = asAsyncReset(dbg_dm_rst_l) @[dbg.scala 225:80]
-    reg abs_temp_12 : UInt, rvclkhdr.io.l1clk with : (reset => (_T_272, UInt<1>("h00"))) @[Reg.scala 27:20]
+    node _T_253 = bits(io.dmi_reg_wdata, 10, 8) @[dbg.scala 227:57]
+    node _T_254 = not(_T_253) @[dbg.scala 227:40]
+    node _T_255 = and(_T_252, _T_254) @[dbg.scala 227:37]
+    node _T_256 = bits(abstractcs_reg, 10, 8) @[dbg.scala 227:91]
+    node _T_257 = and(_T_255, _T_256) @[dbg.scala 227:75]
+    node _T_258 = or(_T_250, _T_257) @[dbg.scala 226:54]
+    node _T_259 = not(abstractcs_error_selor) @[dbg.scala 228:15]
+    node _T_260 = bits(_T_259, 0, 0) @[Bitwise.scala 72:15]
+    node _T_261 = mux(_T_260, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
+    node _T_262 = bits(abstractcs_reg, 10, 8) @[dbg.scala 228:66]
+    node _T_263 = and(_T_261, _T_262) @[dbg.scala 228:50]
+    node abstractcs_error_din = or(_T_258, _T_263) @[dbg.scala 227:100]
+    reg abs_temp_12 : UInt, rvclkhdr.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20]
     when abstractcs_busy_wren : @[Reg.scala 28:19]
       abs_temp_12 <= abstractcs_busy_din @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    node _T_273 = asAsyncReset(dbg_dm_rst_l) @[dbg.scala 229:82]
-    node _T_274 = bits(abstractcs_error_din, 2, 0) @[dbg.scala 230:33]
-    reg abs_temp_10_8 : UInt, rvclkhdr.io.l1clk with : (reset => (_T_273, UInt<1>("h00"))) @[dbg.scala 230:12]
-    abs_temp_10_8 <= _T_274 @[dbg.scala 230:12]
-    node _T_275 = cat(abs_temp_10_8, UInt<8>("h02")) @[Cat.scala 29:58]
-    node _T_276 = cat(UInt<19>("h00"), abs_temp_12) @[Cat.scala 29:58]
-    node _T_277 = cat(_T_276, UInt<1>("h00")) @[Cat.scala 29:58]
-    node _T_278 = cat(_T_277, _T_275) @[Cat.scala 29:58]
-    abstractcs_reg <= _T_278 @[dbg.scala 233:18]
-    node _T_279 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[dbg.scala 235:39]
-    node _T_280 = and(_T_279, io.dmi_reg_en) @[dbg.scala 235:52]
-    node _T_281 = and(_T_280, io.dmi_reg_wr_en) @[dbg.scala 235:68]
-    node _T_282 = eq(dbg_state, UInt<3>("h02")) @[dbg.scala 235:100]
-    node command_wren = and(_T_281, _T_282) @[dbg.scala 235:87]
-    node _T_283 = bits(io.dmi_reg_wdata, 31, 24) @[dbg.scala 236:41]
-    node _T_284 = bits(io.dmi_reg_wdata, 22, 20) @[dbg.scala 236:77]
-    node _T_285 = bits(io.dmi_reg_wdata, 16, 0) @[dbg.scala 236:113]
-    node _T_286 = cat(UInt<3>("h00"), _T_285) @[Cat.scala 29:58]
-    node _T_287 = cat(_T_283, UInt<1>("h00")) @[Cat.scala 29:58]
-    node _T_288 = cat(_T_287, _T_284) @[Cat.scala 29:58]
-    node command_din = cat(_T_288, _T_286) @[Cat.scala 29:58]
-    node _T_289 = asAsyncReset(dbg_dm_rst_l) @[dbg.scala 237:58]
-    inst rvclkhdr_5 of rvclkhdr_5 @[lib.scala 352:23]
+    node _T_264 = bits(abstractcs_error_din, 2, 0) @[dbg.scala 235:33]
+    reg abs_temp_10_8 : UInt, rvclkhdr.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[dbg.scala 235:12]
+    abs_temp_10_8 <= _T_264 @[dbg.scala 235:12]
+    node _T_265 = cat(abs_temp_10_8, UInt<8>("h02")) @[Cat.scala 29:58]
+    node _T_266 = cat(UInt<19>("h00"), abs_temp_12) @[Cat.scala 29:58]
+    node _T_267 = cat(_T_266, UInt<1>("h00")) @[Cat.scala 29:58]
+    node _T_268 = cat(_T_267, _T_265) @[Cat.scala 29:58]
+    abstractcs_reg <= _T_268 @[dbg.scala 238:18]
+    node _T_269 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[dbg.scala 240:39]
+    node _T_270 = and(_T_269, io.dmi_reg_en) @[dbg.scala 240:52]
+    node _T_271 = and(_T_270, io.dmi_reg_wr_en) @[dbg.scala 240:68]
+    node _T_272 = eq(dbg_state, UInt<3>("h02")) @[dbg.scala 240:100]
+    node command_wren = and(_T_271, _T_272) @[dbg.scala 240:87]
+    node _T_273 = bits(io.dmi_reg_wdata, 31, 24) @[dbg.scala 241:41]
+    node _T_274 = bits(io.dmi_reg_wdata, 22, 20) @[dbg.scala 241:77]
+    node _T_275 = bits(io.dmi_reg_wdata, 16, 0) @[dbg.scala 241:113]
+    node _T_276 = cat(UInt<3>("h00"), _T_275) @[Cat.scala 29:58]
+    node _T_277 = cat(_T_273, UInt<1>("h00")) @[Cat.scala 29:58]
+    node _T_278 = cat(_T_277, _T_274) @[Cat.scala 29:58]
+    node command_din = cat(_T_278, _T_276) @[Cat.scala 29:58]
+    inst rvclkhdr_5 of rvclkhdr_5 @[lib.scala 368:23]
     rvclkhdr_5.clock <= clock
-    rvclkhdr_5.reset <= _T_289
-    rvclkhdr_5.io.clk <= clock @[lib.scala 354:18]
-    rvclkhdr_5.io.en <= command_wren @[lib.scala 355:17]
-    rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 356:24]
-    reg command_reg : UInt, rvclkhdr_5.io.l1clk with : (reset => (_T_289, UInt<1>("h00"))) @[lib.scala 358:16]
-    command_reg <= command_din @[lib.scala 358:16]
-    node _T_290 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 241:39]
-    node _T_291 = eq(io.dmi_reg_addr, UInt<3>("h04")) @[dbg.scala 241:77]
-    node _T_292 = and(_T_290, _T_291) @[dbg.scala 241:58]
-    node _T_293 = eq(dbg_state, UInt<3>("h02")) @[dbg.scala 241:102]
-    node data0_reg_wren0 = and(_T_292, _T_293) @[dbg.scala 241:89]
-    node _T_294 = eq(dbg_state, UInt<3>("h04")) @[dbg.scala 242:59]
-    node _T_295 = and(io.core_dbg_cmd_done, _T_294) @[dbg.scala 242:46]
-    node _T_296 = bits(command_reg, 16, 16) @[dbg.scala 242:95]
-    node _T_297 = eq(_T_296, UInt<1>("h00")) @[dbg.scala 242:83]
-    node data0_reg_wren1 = and(_T_295, _T_297) @[dbg.scala 242:81]
-    node data0_reg_wren = or(data0_reg_wren0, data0_reg_wren1) @[dbg.scala 244:40]
-    node _T_298 = bits(data0_reg_wren0, 0, 0) @[Bitwise.scala 72:15]
-    node _T_299 = mux(_T_298, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
-    node _T_300 = and(_T_299, io.dmi_reg_wdata) @[dbg.scala 245:45]
-    node _T_301 = bits(data0_reg_wren1, 0, 0) @[Bitwise.scala 72:15]
-    node _T_302 = mux(_T_301, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
-    node _T_303 = and(_T_302, io.core_dbg_rddata) @[dbg.scala 245:92]
-    node data0_din = or(_T_300, _T_303) @[dbg.scala 245:64]
-    node _T_304 = asAsyncReset(dbg_dm_rst_l) @[dbg.scala 246:56]
-    inst rvclkhdr_6 of rvclkhdr_6 @[lib.scala 352:23]
+    rvclkhdr_5.reset <= dbg_dm_rst_l
+    rvclkhdr_5.io.clk <= clock @[lib.scala 370:18]
+    rvclkhdr_5.io.en <= command_wren @[lib.scala 371:17]
+    rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
+    reg command_reg : UInt, rvclkhdr_5.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[lib.scala 374:16]
+    command_reg <= command_din @[lib.scala 374:16]
+    node _T_279 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 246:39]
+    node _T_280 = eq(io.dmi_reg_addr, UInt<3>("h04")) @[dbg.scala 246:77]
+    node _T_281 = and(_T_279, _T_280) @[dbg.scala 246:58]
+    node _T_282 = eq(dbg_state, UInt<3>("h02")) @[dbg.scala 246:102]
+    node data0_reg_wren0 = and(_T_281, _T_282) @[dbg.scala 246:89]
+    node _T_283 = eq(dbg_state, UInt<3>("h04")) @[dbg.scala 247:59]
+    node _T_284 = and(io.core_dbg_cmd_done, _T_283) @[dbg.scala 247:46]
+    node _T_285 = bits(command_reg, 16, 16) @[dbg.scala 247:95]
+    node _T_286 = eq(_T_285, UInt<1>("h00")) @[dbg.scala 247:83]
+    node data0_reg_wren1 = and(_T_284, _T_286) @[dbg.scala 247:81]
+    node data0_reg_wren = or(data0_reg_wren0, data0_reg_wren1) @[dbg.scala 249:40]
+    node _T_287 = bits(data0_reg_wren0, 0, 0) @[Bitwise.scala 72:15]
+    node _T_288 = mux(_T_287, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
+    node _T_289 = and(_T_288, io.dmi_reg_wdata) @[dbg.scala 250:45]
+    node _T_290 = bits(data0_reg_wren1, 0, 0) @[Bitwise.scala 72:15]
+    node _T_291 = mux(_T_290, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
+    node _T_292 = and(_T_291, io.core_dbg_rddata) @[dbg.scala 250:92]
+    node data0_din = or(_T_289, _T_292) @[dbg.scala 250:64]
+    inst rvclkhdr_6 of rvclkhdr_6 @[lib.scala 368:23]
     rvclkhdr_6.clock <= clock
-    rvclkhdr_6.reset <= _T_304
-    rvclkhdr_6.io.clk <= clock @[lib.scala 354:18]
-    rvclkhdr_6.io.en <= data0_reg_wren @[lib.scala 355:17]
-    rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 356:24]
-    reg data0_reg : UInt, rvclkhdr_6.io.l1clk with : (reset => (_T_304, UInt<1>("h00"))) @[lib.scala 358:16]
-    data0_reg <= data0_din @[lib.scala 358:16]
-    node _T_305 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 250:39]
-    node _T_306 = eq(io.dmi_reg_addr, UInt<3>("h05")) @[dbg.scala 250:77]
-    node _T_307 = and(_T_305, _T_306) @[dbg.scala 250:58]
-    node _T_308 = eq(dbg_state, UInt<3>("h02")) @[dbg.scala 250:102]
-    node data1_reg_wren = and(_T_307, _T_308) @[dbg.scala 250:89]
-    node _T_309 = bits(data1_reg_wren, 0, 0) @[Bitwise.scala 72:15]
-    node _T_310 = mux(_T_309, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
-    node data1_din = and(_T_310, io.dmi_reg_wdata) @[dbg.scala 251:44]
-    node _T_311 = asAsyncReset(dbg_dm_rst_l) @[dbg.scala 252:53]
-    inst rvclkhdr_7 of rvclkhdr_7 @[lib.scala 352:23]
+    rvclkhdr_6.reset <= dbg_dm_rst_l
+    rvclkhdr_6.io.clk <= clock @[lib.scala 370:18]
+    rvclkhdr_6.io.en <= data0_reg_wren @[lib.scala 371:17]
+    rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
+    reg data0_reg : UInt, rvclkhdr_6.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[lib.scala 374:16]
+    data0_reg <= data0_din @[lib.scala 374:16]
+    node _T_293 = and(io.dmi_reg_en, io.dmi_reg_wr_en) @[dbg.scala 255:39]
+    node _T_294 = eq(io.dmi_reg_addr, UInt<3>("h05")) @[dbg.scala 255:77]
+    node _T_295 = and(_T_293, _T_294) @[dbg.scala 255:58]
+    node _T_296 = eq(dbg_state, UInt<3>("h02")) @[dbg.scala 255:102]
+    node data1_reg_wren = and(_T_295, _T_296) @[dbg.scala 255:89]
+    node _T_297 = bits(data1_reg_wren, 0, 0) @[Bitwise.scala 72:15]
+    node _T_298 = mux(_T_297, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
+    node data1_din = and(_T_298, io.dmi_reg_wdata) @[dbg.scala 256:44]
+    inst rvclkhdr_7 of rvclkhdr_7 @[lib.scala 368:23]
     rvclkhdr_7.clock <= clock
-    rvclkhdr_7.reset <= _T_311
-    rvclkhdr_7.io.clk <= clock @[lib.scala 354:18]
-    rvclkhdr_7.io.en <= data1_reg_wren @[lib.scala 355:17]
-    rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 356:24]
-    reg _T_312 : UInt, rvclkhdr_7.io.l1clk with : (reset => (_T_311, UInt<1>("h00"))) @[lib.scala 358:16]
-    _T_312 <= data1_din @[lib.scala 358:16]
-    data1_reg <= _T_312 @[dbg.scala 252:13]
+    rvclkhdr_7.reset <= dbg_dm_rst_l
+    rvclkhdr_7.io.clk <= clock @[lib.scala 370:18]
+    rvclkhdr_7.io.en <= data1_reg_wren @[lib.scala 371:17]
+    rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
+    reg _T_299 : UInt, rvclkhdr_7.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[lib.scala 374:16]
+    _T_299 <= data1_din @[lib.scala 374:16]
+    data1_reg <= _T_299 @[dbg.scala 257:13]
     wire dbg_nxtstate : UInt<3>
     dbg_nxtstate <= UInt<3>("h00")
-    dbg_nxtstate <= UInt<3>("h00") @[dbg.scala 257:16]
-    dbg_state_en <= UInt<1>("h00") @[dbg.scala 258:16]
-    abstractcs_busy_wren <= UInt<1>("h00") @[dbg.scala 259:24]
-    abstractcs_busy_din <= UInt<1>("h00") @[dbg.scala 260:23]
-    io.dbg_halt_req <= UInt<1>("h00") @[dbg.scala 261:19]
-    io.dbg_resume_req <= UInt<1>("h00") @[dbg.scala 262:21]
-    node _T_313 = eq(UInt<3>("h00"), dbg_state) @[Conditional.scala 37:30]
-    when _T_313 : @[Conditional.scala 40:58]
-      node _T_314 = bits(dmstatus_reg, 9, 9) @[dbg.scala 265:39]
-      node _T_315 = or(_T_314, io.dec_tlu_mpc_halted_only) @[dbg.scala 265:43]
-      node _T_316 = mux(_T_315, UInt<3>("h02"), UInt<3>("h01")) @[dbg.scala 265:26]
-      dbg_nxtstate <= _T_316 @[dbg.scala 265:20]
-      node _T_317 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 266:38]
-      node _T_318 = eq(io.dec_tlu_debug_mode, UInt<1>("h00")) @[dbg.scala 266:45]
-      node _T_319 = and(_T_317, _T_318) @[dbg.scala 266:43]
-      node _T_320 = bits(dmstatus_reg, 9, 9) @[dbg.scala 266:83]
-      node _T_321 = or(_T_319, _T_320) @[dbg.scala 266:69]
-      node _T_322 = or(_T_321, io.dec_tlu_mpc_halted_only) @[dbg.scala 266:87]
-      node _T_323 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 266:133]
-      node _T_324 = eq(_T_323, UInt<1>("h00")) @[dbg.scala 266:119]
-      node _T_325 = and(_T_322, _T_324) @[dbg.scala 266:117]
-      dbg_state_en <= _T_325 @[dbg.scala 266:20]
-      node _T_326 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 267:40]
-      node _T_327 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 267:61]
-      node _T_328 = eq(_T_327, UInt<1>("h00")) @[dbg.scala 267:47]
-      node _T_329 = and(_T_326, _T_328) @[dbg.scala 267:45]
-      node _T_330 = bits(_T_329, 0, 0) @[dbg.scala 267:72]
-      io.dbg_halt_req <= _T_330 @[dbg.scala 267:23]
+    dbg_nxtstate <= UInt<3>("h00") @[dbg.scala 262:16]
+    dbg_state_en <= UInt<1>("h00") @[dbg.scala 263:16]
+    abstractcs_busy_wren <= UInt<1>("h00") @[dbg.scala 264:24]
+    abstractcs_busy_din <= UInt<1>("h00") @[dbg.scala 265:23]
+    io.dbg_halt_req <= UInt<1>("h00") @[dbg.scala 266:19]
+    io.dbg_resume_req <= UInt<1>("h00") @[dbg.scala 267:21]
+    node _T_300 = eq(UInt<3>("h00"), dbg_state) @[Conditional.scala 37:30]
+    when _T_300 : @[Conditional.scala 40:58]
+      node _T_301 = bits(dmstatus_reg, 9, 9) @[dbg.scala 270:39]
+      node _T_302 = or(_T_301, io.dec_tlu_mpc_halted_only) @[dbg.scala 270:43]
+      node _T_303 = mux(_T_302, UInt<3>("h02"), UInt<3>("h01")) @[dbg.scala 270:26]
+      dbg_nxtstate <= _T_303 @[dbg.scala 270:20]
+      node _T_304 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 271:38]
+      node _T_305 = eq(io.dec_tlu_debug_mode, UInt<1>("h00")) @[dbg.scala 271:45]
+      node _T_306 = and(_T_304, _T_305) @[dbg.scala 271:43]
+      node _T_307 = bits(dmstatus_reg, 9, 9) @[dbg.scala 271:83]
+      node _T_308 = or(_T_306, _T_307) @[dbg.scala 271:69]
+      node _T_309 = or(_T_308, io.dec_tlu_mpc_halted_only) @[dbg.scala 271:87]
+      node _T_310 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 271:133]
+      node _T_311 = eq(_T_310, UInt<1>("h00")) @[dbg.scala 271:119]
+      node _T_312 = and(_T_309, _T_311) @[dbg.scala 271:117]
+      dbg_state_en <= _T_312 @[dbg.scala 271:20]
+      node _T_313 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 272:40]
+      node _T_314 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 272:61]
+      node _T_315 = eq(_T_314, UInt<1>("h00")) @[dbg.scala 272:47]
+      node _T_316 = and(_T_313, _T_315) @[dbg.scala 272:45]
+      node _T_317 = bits(_T_316, 0, 0) @[dbg.scala 272:72]
+      io.dbg_halt_req <= _T_317 @[dbg.scala 272:23]
       skip @[Conditional.scala 40:58]
     else : @[Conditional.scala 39:67]
-      node _T_331 = eq(UInt<3>("h01"), dbg_state) @[Conditional.scala 37:30]
-      when _T_331 : @[Conditional.scala 39:67]
-        node _T_332 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 270:40]
-        node _T_333 = mux(_T_332, UInt<3>("h00"), UInt<3>("h02")) @[dbg.scala 270:26]
-        dbg_nxtstate <= _T_333 @[dbg.scala 270:20]
-        node _T_334 = bits(dmstatus_reg, 9, 9) @[dbg.scala 271:35]
-        node _T_335 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 271:54]
-        node _T_336 = or(_T_334, _T_335) @[dbg.scala 271:39]
-        dbg_state_en <= _T_336 @[dbg.scala 271:20]
-        node _T_337 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 272:59]
-        node _T_338 = and(dmcontrol_wren_Q, _T_337) @[dbg.scala 272:44]
-        node _T_339 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 272:81]
-        node _T_340 = not(_T_339) @[dbg.scala 272:67]
-        node _T_341 = and(_T_338, _T_340) @[dbg.scala 272:64]
-        node _T_342 = bits(_T_341, 0, 0) @[dbg.scala 272:102]
-        io.dbg_halt_req <= _T_342 @[dbg.scala 272:23]
+      node _T_318 = eq(UInt<3>("h01"), dbg_state) @[Conditional.scala 37:30]
+      when _T_318 : @[Conditional.scala 39:67]
+        node _T_319 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 275:40]
+        node _T_320 = mux(_T_319, UInt<3>("h00"), UInt<3>("h02")) @[dbg.scala 275:26]
+        dbg_nxtstate <= _T_320 @[dbg.scala 275:20]
+        node _T_321 = bits(dmstatus_reg, 9, 9) @[dbg.scala 276:35]
+        node _T_322 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 276:54]
+        node _T_323 = or(_T_321, _T_322) @[dbg.scala 276:39]
+        dbg_state_en <= _T_323 @[dbg.scala 276:20]
+        node _T_324 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 277:59]
+        node _T_325 = and(dmcontrol_wren_Q, _T_324) @[dbg.scala 277:44]
+        node _T_326 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 277:81]
+        node _T_327 = not(_T_326) @[dbg.scala 277:67]
+        node _T_328 = and(_T_325, _T_327) @[dbg.scala 277:64]
+        node _T_329 = bits(_T_328, 0, 0) @[dbg.scala 277:102]
+        io.dbg_halt_req <= _T_329 @[dbg.scala 277:23]
         skip @[Conditional.scala 39:67]
       else : @[Conditional.scala 39:67]
-        node _T_343 = eq(UInt<3>("h02"), dbg_state) @[Conditional.scala 37:30]
-        when _T_343 : @[Conditional.scala 39:67]
-          node _T_344 = bits(dmstatus_reg, 9, 9) @[dbg.scala 275:39]
-          node _T_345 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 275:59]
-          node _T_346 = eq(_T_345, UInt<1>("h00")) @[dbg.scala 275:45]
-          node _T_347 = and(_T_344, _T_346) @[dbg.scala 275:43]
-          node _T_348 = bits(dmcontrol_reg, 30, 30) @[dbg.scala 276:26]
-          node _T_349 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 276:47]
-          node _T_350 = eq(_T_349, UInt<1>("h00")) @[dbg.scala 276:33]
-          node _T_351 = and(_T_348, _T_350) @[dbg.scala 276:31]
-          node _T_352 = mux(_T_351, UInt<3>("h06"), UInt<3>("h03")) @[dbg.scala 276:12]
-          node _T_353 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 277:26]
-          node _T_354 = mux(_T_353, UInt<3>("h01"), UInt<3>("h00")) @[dbg.scala 277:12]
-          node _T_355 = mux(_T_347, _T_352, _T_354) @[dbg.scala 275:26]
-          dbg_nxtstate <= _T_355 @[dbg.scala 275:20]
-          node _T_356 = bits(dmstatus_reg, 9, 9) @[dbg.scala 278:35]
-          node _T_357 = bits(dmcontrol_reg, 30, 30) @[dbg.scala 278:54]
-          node _T_358 = and(_T_356, _T_357) @[dbg.scala 278:39]
-          node _T_359 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 278:75]
-          node _T_360 = eq(_T_359, UInt<1>("h00")) @[dbg.scala 278:61]
-          node _T_361 = and(_T_358, _T_360) @[dbg.scala 278:59]
-          node _T_362 = and(_T_361, dmcontrol_wren_Q) @[dbg.scala 278:80]
-          node _T_363 = or(_T_362, command_wren) @[dbg.scala 278:99]
-          node _T_364 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 279:22]
-          node _T_365 = or(_T_363, _T_364) @[dbg.scala 278:114]
-          node _T_366 = bits(dmstatus_reg, 9, 9) @[dbg.scala 279:42]
-          node _T_367 = or(_T_366, io.dec_tlu_mpc_halted_only) @[dbg.scala 279:46]
-          node _T_368 = eq(_T_367, UInt<1>("h00")) @[dbg.scala 279:28]
-          node _T_369 = or(_T_365, _T_368) @[dbg.scala 279:26]
-          dbg_state_en <= _T_369 @[dbg.scala 278:20]
-          node _T_370 = eq(dbg_nxtstate, UInt<3>("h03")) @[dbg.scala 280:60]
-          node _T_371 = and(dbg_state_en, _T_370) @[dbg.scala 280:44]
-          abstractcs_busy_wren <= _T_371 @[dbg.scala 280:28]
-          abstractcs_busy_din <= UInt<1>("h01") @[dbg.scala 281:27]
-          node _T_372 = eq(dbg_nxtstate, UInt<3>("h06")) @[dbg.scala 282:58]
-          node _T_373 = and(dbg_state_en, _T_372) @[dbg.scala 282:42]
-          node _T_374 = bits(_T_373, 0, 0) @[dbg.scala 282:87]
-          io.dbg_resume_req <= _T_374 @[dbg.scala 282:25]
-          node _T_375 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 283:59]
-          node _T_376 = and(dmcontrol_wren_Q, _T_375) @[dbg.scala 283:44]
-          node _T_377 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 283:81]
-          node _T_378 = not(_T_377) @[dbg.scala 283:67]
-          node _T_379 = and(_T_376, _T_378) @[dbg.scala 283:64]
-          node _T_380 = bits(_T_379, 0, 0) @[dbg.scala 283:102]
-          io.dbg_halt_req <= _T_380 @[dbg.scala 283:23]
+        node _T_330 = eq(UInt<3>("h02"), dbg_state) @[Conditional.scala 37:30]
+        when _T_330 : @[Conditional.scala 39:67]
+          node _T_331 = bits(dmstatus_reg, 9, 9) @[dbg.scala 280:39]
+          node _T_332 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 280:59]
+          node _T_333 = eq(_T_332, UInt<1>("h00")) @[dbg.scala 280:45]
+          node _T_334 = and(_T_331, _T_333) @[dbg.scala 280:43]
+          node _T_335 = bits(dmcontrol_reg, 30, 30) @[dbg.scala 281:26]
+          node _T_336 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 281:47]
+          node _T_337 = eq(_T_336, UInt<1>("h00")) @[dbg.scala 281:33]
+          node _T_338 = and(_T_335, _T_337) @[dbg.scala 281:31]
+          node _T_339 = mux(_T_338, UInt<3>("h06"), UInt<3>("h03")) @[dbg.scala 281:12]
+          node _T_340 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 282:26]
+          node _T_341 = mux(_T_340, UInt<3>("h01"), UInt<3>("h00")) @[dbg.scala 282:12]
+          node _T_342 = mux(_T_334, _T_339, _T_341) @[dbg.scala 280:26]
+          dbg_nxtstate <= _T_342 @[dbg.scala 280:20]
+          node _T_343 = bits(dmstatus_reg, 9, 9) @[dbg.scala 283:35]
+          node _T_344 = bits(dmcontrol_reg, 30, 30) @[dbg.scala 283:54]
+          node _T_345 = and(_T_343, _T_344) @[dbg.scala 283:39]
+          node _T_346 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 283:75]
+          node _T_347 = eq(_T_346, UInt<1>("h00")) @[dbg.scala 283:61]
+          node _T_348 = and(_T_345, _T_347) @[dbg.scala 283:59]
+          node _T_349 = and(_T_348, dmcontrol_wren_Q) @[dbg.scala 283:80]
+          node _T_350 = or(_T_349, command_wren) @[dbg.scala 283:99]
+          node _T_351 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 284:22]
+          node _T_352 = or(_T_350, _T_351) @[dbg.scala 283:114]
+          node _T_353 = bits(dmstatus_reg, 9, 9) @[dbg.scala 284:42]
+          node _T_354 = or(_T_353, io.dec_tlu_mpc_halted_only) @[dbg.scala 284:46]
+          node _T_355 = eq(_T_354, UInt<1>("h00")) @[dbg.scala 284:28]
+          node _T_356 = or(_T_352, _T_355) @[dbg.scala 284:26]
+          dbg_state_en <= _T_356 @[dbg.scala 283:20]
+          node _T_357 = eq(dbg_nxtstate, UInt<3>("h03")) @[dbg.scala 285:60]
+          node _T_358 = and(dbg_state_en, _T_357) @[dbg.scala 285:44]
+          abstractcs_busy_wren <= _T_358 @[dbg.scala 285:28]
+          abstractcs_busy_din <= UInt<1>("h01") @[dbg.scala 286:27]
+          node _T_359 = eq(dbg_nxtstate, UInt<3>("h06")) @[dbg.scala 287:58]
+          node _T_360 = and(dbg_state_en, _T_359) @[dbg.scala 287:42]
+          node _T_361 = bits(_T_360, 0, 0) @[dbg.scala 287:87]
+          io.dbg_resume_req <= _T_361 @[dbg.scala 287:25]
+          node _T_362 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 288:59]
+          node _T_363 = and(dmcontrol_wren_Q, _T_362) @[dbg.scala 288:44]
+          node _T_364 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 288:81]
+          node _T_365 = not(_T_364) @[dbg.scala 288:67]
+          node _T_366 = and(_T_363, _T_365) @[dbg.scala 288:64]
+          node _T_367 = bits(_T_366, 0, 0) @[dbg.scala 288:102]
+          io.dbg_halt_req <= _T_367 @[dbg.scala 288:23]
           skip @[Conditional.scala 39:67]
         else : @[Conditional.scala 39:67]
-          node _T_381 = eq(UInt<3>("h03"), dbg_state) @[Conditional.scala 37:30]
-          when _T_381 : @[Conditional.scala 39:67]
-            node _T_382 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 286:40]
-            node _T_383 = bits(abstractcs_reg, 10, 8) @[dbg.scala 286:77]
-            node _T_384 = orr(_T_383) @[dbg.scala 286:85]
-            node _T_385 = mux(_T_384, UInt<3>("h05"), UInt<3>("h04")) @[dbg.scala 286:62]
-            node _T_386 = mux(_T_382, UInt<3>("h00"), _T_385) @[dbg.scala 286:26]
-            dbg_nxtstate <= _T_386 @[dbg.scala 286:20]
-            node _T_387 = bits(abstractcs_reg, 10, 8) @[dbg.scala 287:71]
-            node _T_388 = orr(_T_387) @[dbg.scala 287:79]
-            node _T_389 = or(io.dbg_dec.dbg_ib.dbg_cmd_valid, _T_388) @[dbg.scala 287:55]
-            node _T_390 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 287:98]
-            node _T_391 = or(_T_389, _T_390) @[dbg.scala 287:83]
-            dbg_state_en <= _T_391 @[dbg.scala 287:20]
-            node _T_392 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 288:59]
-            node _T_393 = and(dmcontrol_wren_Q, _T_392) @[dbg.scala 288:44]
-            node _T_394 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 288:81]
-            node _T_395 = not(_T_394) @[dbg.scala 288:67]
-            node _T_396 = and(_T_393, _T_395) @[dbg.scala 288:64]
-            node _T_397 = bits(_T_396, 0, 0) @[dbg.scala 288:102]
-            io.dbg_halt_req <= _T_397 @[dbg.scala 288:23]
+          node _T_368 = eq(UInt<3>("h03"), dbg_state) @[Conditional.scala 37:30]
+          when _T_368 : @[Conditional.scala 39:67]
+            node _T_369 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 291:40]
+            node _T_370 = bits(abstractcs_reg, 10, 8) @[dbg.scala 291:77]
+            node _T_371 = orr(_T_370) @[dbg.scala 291:85]
+            node _T_372 = mux(_T_371, UInt<3>("h05"), UInt<3>("h04")) @[dbg.scala 291:62]
+            node _T_373 = mux(_T_369, UInt<3>("h00"), _T_372) @[dbg.scala 291:26]
+            dbg_nxtstate <= _T_373 @[dbg.scala 291:20]
+            node _T_374 = bits(abstractcs_reg, 10, 8) @[dbg.scala 292:71]
+            node _T_375 = orr(_T_374) @[dbg.scala 292:79]
+            node _T_376 = or(io.dbg_dec.dbg_ib.dbg_cmd_valid, _T_375) @[dbg.scala 292:55]
+            node _T_377 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 292:98]
+            node _T_378 = or(_T_376, _T_377) @[dbg.scala 292:83]
+            dbg_state_en <= _T_378 @[dbg.scala 292:20]
+            node _T_379 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 293:59]
+            node _T_380 = and(dmcontrol_wren_Q, _T_379) @[dbg.scala 293:44]
+            node _T_381 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 293:81]
+            node _T_382 = not(_T_381) @[dbg.scala 293:67]
+            node _T_383 = and(_T_380, _T_382) @[dbg.scala 293:64]
+            node _T_384 = bits(_T_383, 0, 0) @[dbg.scala 293:102]
+            io.dbg_halt_req <= _T_384 @[dbg.scala 293:23]
             skip @[Conditional.scala 39:67]
           else : @[Conditional.scala 39:67]
-            node _T_398 = eq(UInt<3>("h04"), dbg_state) @[Conditional.scala 37:30]
-            when _T_398 : @[Conditional.scala 39:67]
-              node _T_399 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 291:40]
-              node _T_400 = mux(_T_399, UInt<3>("h00"), UInt<3>("h05")) @[dbg.scala 291:26]
-              dbg_nxtstate <= _T_400 @[dbg.scala 291:20]
-              node _T_401 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 292:59]
-              node _T_402 = or(io.core_dbg_cmd_done, _T_401) @[dbg.scala 292:44]
-              dbg_state_en <= _T_402 @[dbg.scala 292:20]
-              node _T_403 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 293:59]
-              node _T_404 = and(dmcontrol_wren_Q, _T_403) @[dbg.scala 293:44]
-              node _T_405 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 293:81]
-              node _T_406 = not(_T_405) @[dbg.scala 293:67]
-              node _T_407 = and(_T_404, _T_406) @[dbg.scala 293:64]
-              node _T_408 = bits(_T_407, 0, 0) @[dbg.scala 293:102]
-              io.dbg_halt_req <= _T_408 @[dbg.scala 293:23]
+            node _T_385 = eq(UInt<3>("h04"), dbg_state) @[Conditional.scala 37:30]
+            when _T_385 : @[Conditional.scala 39:67]
+              node _T_386 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 296:40]
+              node _T_387 = mux(_T_386, UInt<3>("h00"), UInt<3>("h05")) @[dbg.scala 296:26]
+              dbg_nxtstate <= _T_387 @[dbg.scala 296:20]
+              node _T_388 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 297:59]
+              node _T_389 = or(io.core_dbg_cmd_done, _T_388) @[dbg.scala 297:44]
+              dbg_state_en <= _T_389 @[dbg.scala 297:20]
+              node _T_390 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 298:59]
+              node _T_391 = and(dmcontrol_wren_Q, _T_390) @[dbg.scala 298:44]
+              node _T_392 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 298:81]
+              node _T_393 = not(_T_392) @[dbg.scala 298:67]
+              node _T_394 = and(_T_391, _T_393) @[dbg.scala 298:64]
+              node _T_395 = bits(_T_394, 0, 0) @[dbg.scala 298:102]
+              io.dbg_halt_req <= _T_395 @[dbg.scala 298:23]
               skip @[Conditional.scala 39:67]
             else : @[Conditional.scala 39:67]
-              node _T_409 = eq(UInt<3>("h05"), dbg_state) @[Conditional.scala 37:30]
-              when _T_409 : @[Conditional.scala 39:67]
-                node _T_410 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 296:40]
-                node _T_411 = mux(_T_410, UInt<3>("h00"), UInt<3>("h02")) @[dbg.scala 296:26]
-                dbg_nxtstate <= _T_411 @[dbg.scala 296:20]
-                dbg_state_en <= UInt<1>("h01") @[dbg.scala 297:20]
-                abstractcs_busy_wren <= dbg_state_en @[dbg.scala 298:28]
-                abstractcs_busy_din <= UInt<1>("h00") @[dbg.scala 299:27]
-                node _T_412 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 300:59]
-                node _T_413 = and(dmcontrol_wren_Q, _T_412) @[dbg.scala 300:44]
-                node _T_414 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 300:81]
-                node _T_415 = not(_T_414) @[dbg.scala 300:67]
-                node _T_416 = and(_T_413, _T_415) @[dbg.scala 300:64]
-                node _T_417 = bits(_T_416, 0, 0) @[dbg.scala 300:102]
-                io.dbg_halt_req <= _T_417 @[dbg.scala 300:23]
+              node _T_396 = eq(UInt<3>("h05"), dbg_state) @[Conditional.scala 37:30]
+              when _T_396 : @[Conditional.scala 39:67]
+                node _T_397 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 301:40]
+                node _T_398 = mux(_T_397, UInt<3>("h00"), UInt<3>("h02")) @[dbg.scala 301:26]
+                dbg_nxtstate <= _T_398 @[dbg.scala 301:20]
+                dbg_state_en <= UInt<1>("h01") @[dbg.scala 302:20]
+                abstractcs_busy_wren <= dbg_state_en @[dbg.scala 303:28]
+                abstractcs_busy_din <= UInt<1>("h00") @[dbg.scala 304:27]
+                node _T_399 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 305:59]
+                node _T_400 = and(dmcontrol_wren_Q, _T_399) @[dbg.scala 305:44]
+                node _T_401 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 305:81]
+                node _T_402 = not(_T_401) @[dbg.scala 305:67]
+                node _T_403 = and(_T_400, _T_402) @[dbg.scala 305:64]
+                node _T_404 = bits(_T_403, 0, 0) @[dbg.scala 305:102]
+                io.dbg_halt_req <= _T_404 @[dbg.scala 305:23]
                 skip @[Conditional.scala 39:67]
               else : @[Conditional.scala 39:67]
-                node _T_418 = eq(UInt<3>("h06"), dbg_state) @[Conditional.scala 37:30]
-                when _T_418 : @[Conditional.scala 39:67]
-                  dbg_nxtstate <= UInt<3>("h00") @[dbg.scala 303:20]
-                  node _T_419 = bits(dmstatus_reg, 17, 17) @[dbg.scala 304:35]
-                  node _T_420 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 304:55]
-                  node _T_421 = or(_T_419, _T_420) @[dbg.scala 304:40]
-                  dbg_state_en <= _T_421 @[dbg.scala 304:20]
-                  node _T_422 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 305:59]
-                  node _T_423 = and(dmcontrol_wren_Q, _T_422) @[dbg.scala 305:44]
-                  node _T_424 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 305:81]
-                  node _T_425 = not(_T_424) @[dbg.scala 305:67]
-                  node _T_426 = and(_T_423, _T_425) @[dbg.scala 305:64]
-                  node _T_427 = bits(_T_426, 0, 0) @[dbg.scala 305:102]
-                  io.dbg_halt_req <= _T_427 @[dbg.scala 305:23]
+                node _T_405 = eq(UInt<3>("h06"), dbg_state) @[Conditional.scala 37:30]
+                when _T_405 : @[Conditional.scala 39:67]
+                  dbg_nxtstate <= UInt<3>("h00") @[dbg.scala 308:20]
+                  node _T_406 = bits(dmstatus_reg, 17, 17) @[dbg.scala 309:35]
+                  node _T_407 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 309:55]
+                  node _T_408 = or(_T_406, _T_407) @[dbg.scala 309:40]
+                  dbg_state_en <= _T_408 @[dbg.scala 309:20]
+                  node _T_409 = bits(dmcontrol_reg, 31, 31) @[dbg.scala 310:59]
+                  node _T_410 = and(dmcontrol_wren_Q, _T_409) @[dbg.scala 310:44]
+                  node _T_411 = bits(dmcontrol_reg, 1, 1) @[dbg.scala 310:81]
+                  node _T_412 = not(_T_411) @[dbg.scala 310:67]
+                  node _T_413 = and(_T_410, _T_412) @[dbg.scala 310:64]
+                  node _T_414 = bits(_T_413, 0, 0) @[dbg.scala 310:102]
+                  io.dbg_halt_req <= _T_414 @[dbg.scala 310:23]
                   skip @[Conditional.scala 39:67]
-    node _T_428 = eq(io.dmi_reg_addr, UInt<3>("h04")) @[dbg.scala 308:52]
-    node _T_429 = bits(_T_428, 0, 0) @[Bitwise.scala 72:15]
-    node _T_430 = mux(_T_429, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
-    node _T_431 = and(_T_430, data0_reg) @[dbg.scala 308:71]
-    node _T_432 = eq(io.dmi_reg_addr, UInt<3>("h05")) @[dbg.scala 308:110]
-    node _T_433 = bits(_T_432, 0, 0) @[Bitwise.scala 72:15]
-    node _T_434 = mux(_T_433, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
-    node _T_435 = and(_T_434, data1_reg) @[dbg.scala 308:122]
-    node _T_436 = or(_T_431, _T_435) @[dbg.scala 308:83]
-    node _T_437 = eq(io.dmi_reg_addr, UInt<5>("h010")) @[dbg.scala 309:30]
-    node _T_438 = bits(_T_437, 0, 0) @[Bitwise.scala 72:15]
-    node _T_439 = mux(_T_438, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
-    node _T_440 = and(_T_439, dmcontrol_reg) @[dbg.scala 309:43]
-    node _T_441 = or(_T_436, _T_440) @[dbg.scala 308:134]
-    node _T_442 = eq(io.dmi_reg_addr, UInt<5>("h011")) @[dbg.scala 309:86]
-    node _T_443 = bits(_T_442, 0, 0) @[Bitwise.scala 72:15]
-    node _T_444 = mux(_T_443, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
-    node _T_445 = and(_T_444, dmstatus_reg) @[dbg.scala 309:99]
-    node _T_446 = or(_T_441, _T_445) @[dbg.scala 309:59]
-    node _T_447 = eq(io.dmi_reg_addr, UInt<5>("h016")) @[dbg.scala 310:30]
-    node _T_448 = bits(_T_447, 0, 0) @[Bitwise.scala 72:15]
-    node _T_449 = mux(_T_448, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
-    node _T_450 = and(_T_449, abstractcs_reg) @[dbg.scala 310:43]
-    node _T_451 = or(_T_446, _T_450) @[dbg.scala 309:114]
-    node _T_452 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[dbg.scala 310:87]
-    node _T_453 = bits(_T_452, 0, 0) @[Bitwise.scala 72:15]
-    node _T_454 = mux(_T_453, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
-    node _T_455 = and(_T_454, command_reg) @[dbg.scala 310:100]
-    node _T_456 = or(_T_451, _T_455) @[dbg.scala 310:60]
-    node _T_457 = eq(io.dmi_reg_addr, UInt<7>("h040")) @[dbg.scala 311:30]
-    node _T_458 = bits(_T_457, 0, 0) @[Bitwise.scala 72:15]
-    node _T_459 = mux(_T_458, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
-    node _T_460 = and(_T_459, haltsum0_reg) @[dbg.scala 311:43]
-    node _T_461 = or(_T_456, _T_460) @[dbg.scala 310:114]
-    node _T_462 = eq(io.dmi_reg_addr, UInt<6>("h038")) @[dbg.scala 311:85]
-    node _T_463 = bits(_T_462, 0, 0) @[Bitwise.scala 72:15]
-    node _T_464 = mux(_T_463, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
-    node _T_465 = and(_T_464, sbcs_reg) @[dbg.scala 311:98]
-    node _T_466 = or(_T_461, _T_465) @[dbg.scala 311:58]
-    node _T_467 = eq(io.dmi_reg_addr, UInt<6>("h039")) @[dbg.scala 312:30]
-    node _T_468 = bits(_T_467, 0, 0) @[Bitwise.scala 72:15]
-    node _T_469 = mux(_T_468, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
-    node _T_470 = and(_T_469, sbaddress0_reg) @[dbg.scala 312:43]
-    node _T_471 = or(_T_466, _T_470) @[dbg.scala 311:109]
-    node _T_472 = eq(io.dmi_reg_addr, UInt<6>("h03c")) @[dbg.scala 312:87]
-    node _T_473 = bits(_T_472, 0, 0) @[Bitwise.scala 72:15]
-    node _T_474 = mux(_T_473, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
-    node _T_475 = and(_T_474, sbdata0_reg) @[dbg.scala 312:100]
-    node _T_476 = or(_T_471, _T_475) @[dbg.scala 312:60]
-    node _T_477 = eq(io.dmi_reg_addr, UInt<6>("h03d")) @[dbg.scala 313:30]
-    node _T_478 = bits(_T_477, 0, 0) @[Bitwise.scala 72:15]
-    node _T_479 = mux(_T_478, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
-    node _T_480 = and(_T_479, sbdata1_reg) @[dbg.scala 313:43]
-    node dmi_reg_rdata_din = or(_T_476, _T_480) @[dbg.scala 312:114]
-    node _T_481 = and(dbg_dm_rst_l, temp_rst) @[dbg.scala 315:62]
-    node _T_482 = asAsyncReset(_T_481) @[dbg.scala 315:86]
-    reg _T_483 : UInt, rvclkhdr.io.l1clk with : (reset => (_T_482, UInt<1>("h00"))) @[Reg.scala 27:20]
+    node _T_415 = eq(io.dmi_reg_addr, UInt<3>("h04")) @[dbg.scala 313:52]
+    node _T_416 = bits(_T_415, 0, 0) @[Bitwise.scala 72:15]
+    node _T_417 = mux(_T_416, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
+    node _T_418 = and(_T_417, data0_reg) @[dbg.scala 313:71]
+    node _T_419 = eq(io.dmi_reg_addr, UInt<3>("h05")) @[dbg.scala 313:110]
+    node _T_420 = bits(_T_419, 0, 0) @[Bitwise.scala 72:15]
+    node _T_421 = mux(_T_420, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
+    node _T_422 = and(_T_421, data1_reg) @[dbg.scala 313:122]
+    node _T_423 = or(_T_418, _T_422) @[dbg.scala 313:83]
+    node _T_424 = eq(io.dmi_reg_addr, UInt<5>("h010")) @[dbg.scala 314:30]
+    node _T_425 = bits(_T_424, 0, 0) @[Bitwise.scala 72:15]
+    node _T_426 = mux(_T_425, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
+    node _T_427 = and(_T_426, dmcontrol_reg) @[dbg.scala 314:43]
+    node _T_428 = or(_T_423, _T_427) @[dbg.scala 313:134]
+    node _T_429 = eq(io.dmi_reg_addr, UInt<5>("h011")) @[dbg.scala 314:86]
+    node _T_430 = bits(_T_429, 0, 0) @[Bitwise.scala 72:15]
+    node _T_431 = mux(_T_430, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
+    node _T_432 = and(_T_431, dmstatus_reg) @[dbg.scala 314:99]
+    node _T_433 = or(_T_428, _T_432) @[dbg.scala 314:59]
+    node _T_434 = eq(io.dmi_reg_addr, UInt<5>("h016")) @[dbg.scala 315:30]
+    node _T_435 = bits(_T_434, 0, 0) @[Bitwise.scala 72:15]
+    node _T_436 = mux(_T_435, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
+    node _T_437 = and(_T_436, abstractcs_reg) @[dbg.scala 315:43]
+    node _T_438 = or(_T_433, _T_437) @[dbg.scala 314:114]
+    node _T_439 = eq(io.dmi_reg_addr, UInt<5>("h017")) @[dbg.scala 315:87]
+    node _T_440 = bits(_T_439, 0, 0) @[Bitwise.scala 72:15]
+    node _T_441 = mux(_T_440, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
+    node _T_442 = and(_T_441, command_reg) @[dbg.scala 315:100]
+    node _T_443 = or(_T_438, _T_442) @[dbg.scala 315:60]
+    node _T_444 = eq(io.dmi_reg_addr, UInt<7>("h040")) @[dbg.scala 316:30]
+    node _T_445 = bits(_T_444, 0, 0) @[Bitwise.scala 72:15]
+    node _T_446 = mux(_T_445, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
+    node _T_447 = and(_T_446, haltsum0_reg) @[dbg.scala 316:43]
+    node _T_448 = or(_T_443, _T_447) @[dbg.scala 315:114]
+    node _T_449 = eq(io.dmi_reg_addr, UInt<6>("h038")) @[dbg.scala 316:85]
+    node _T_450 = bits(_T_449, 0, 0) @[Bitwise.scala 72:15]
+    node _T_451 = mux(_T_450, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
+    node _T_452 = and(_T_451, sbcs_reg) @[dbg.scala 316:98]
+    node _T_453 = or(_T_448, _T_452) @[dbg.scala 316:58]
+    node _T_454 = eq(io.dmi_reg_addr, UInt<6>("h039")) @[dbg.scala 317:30]
+    node _T_455 = bits(_T_454, 0, 0) @[Bitwise.scala 72:15]
+    node _T_456 = mux(_T_455, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
+    node _T_457 = and(_T_456, sbaddress0_reg) @[dbg.scala 317:43]
+    node _T_458 = or(_T_453, _T_457) @[dbg.scala 316:109]
+    node _T_459 = eq(io.dmi_reg_addr, UInt<6>("h03c")) @[dbg.scala 317:87]
+    node _T_460 = bits(_T_459, 0, 0) @[Bitwise.scala 72:15]
+    node _T_461 = mux(_T_460, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
+    node _T_462 = and(_T_461, sbdata0_reg) @[dbg.scala 317:100]
+    node _T_463 = or(_T_458, _T_462) @[dbg.scala 317:60]
+    node _T_464 = eq(io.dmi_reg_addr, UInt<6>("h03d")) @[dbg.scala 318:30]
+    node _T_465 = bits(_T_464, 0, 0) @[Bitwise.scala 72:15]
+    node _T_466 = mux(_T_465, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
+    node _T_467 = and(_T_466, sbdata1_reg) @[dbg.scala 318:43]
+    node dmi_reg_rdata_din = or(_T_463, _T_467) @[dbg.scala 317:114]
+    reg _T_468 : UInt, rvclkhdr.io.l1clk with : (reset => (rst_temp, UInt<1>("h00"))) @[Reg.scala 27:20]
     when dbg_state_en : @[Reg.scala 28:19]
-      _T_483 <= dbg_nxtstate @[Reg.scala 28:23]
+      _T_468 <= dbg_nxtstate @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    dbg_state <= _T_483 @[dbg.scala 315:13]
-    node _T_484 = asAsyncReset(dbg_dm_rst_l) @[dbg.scala 320:82]
-    reg _T_485 : UInt, rvclkhdr.io.l1clk with : (reset => (_T_484, UInt<1>("h00"))) @[Reg.scala 27:20]
+    dbg_state <= _T_468 @[dbg.scala 320:13]
+    reg _T_469 : UInt, rvclkhdr.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20]
     when io.dmi_reg_en : @[Reg.scala 28:19]
-      _T_485 <= dmi_reg_rdata_din @[Reg.scala 28:23]
+      _T_469 <= dmi_reg_rdata_din @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    io.dmi_reg_rdata <= _T_485 @[dbg.scala 320:20]
-    node _T_486 = bits(command_reg, 31, 24) @[dbg.scala 324:53]
-    node _T_487 = eq(_T_486, UInt<2>("h02")) @[dbg.scala 324:62]
-    node _T_488 = bits(data1_reg, 31, 2) @[dbg.scala 324:88]
-    node _T_489 = cat(_T_488, UInt<2>("h00")) @[Cat.scala 29:58]
-    node _T_490 = bits(command_reg, 11, 0) @[dbg.scala 324:138]
-    node _T_491 = cat(UInt<20>("h00"), _T_490) @[Cat.scala 29:58]
-    node _T_492 = mux(_T_487, _T_489, _T_491) @[dbg.scala 324:40]
-    io.dbg_dec.dbg_ib.dbg_cmd_addr <= _T_492 @[dbg.scala 324:34]
-    node _T_493 = bits(data0_reg, 31, 0) @[dbg.scala 325:50]
-    io.dbg_dec.dbg_dctl.dbg_cmd_wrdata <= _T_493 @[dbg.scala 325:38]
-    node _T_494 = eq(dbg_state, UInt<3>("h03")) @[dbg.scala 326:50]
-    node _T_495 = bits(abstractcs_reg, 10, 8) @[dbg.scala 326:91]
-    node _T_496 = orr(_T_495) @[dbg.scala 326:99]
-    node _T_497 = eq(_T_496, UInt<1>("h00")) @[dbg.scala 326:75]
-    node _T_498 = and(_T_494, _T_497) @[dbg.scala 326:73]
-    node _T_499 = and(_T_498, io.dbg_dma_io.dma_dbg_ready) @[dbg.scala 326:104]
-    node _T_500 = bits(_T_499, 0, 0) @[dbg.scala 326:141]
-    io.dbg_dec.dbg_ib.dbg_cmd_valid <= _T_500 @[dbg.scala 326:35]
-    node _T_501 = bits(command_reg, 16, 16) @[dbg.scala 327:49]
-    node _T_502 = bits(_T_501, 0, 0) @[dbg.scala 327:60]
-    io.dbg_dec.dbg_ib.dbg_cmd_write <= _T_502 @[dbg.scala 327:35]
-    node _T_503 = bits(command_reg, 31, 24) @[dbg.scala 328:53]
-    node _T_504 = eq(_T_503, UInt<2>("h02")) @[dbg.scala 328:62]
-    node _T_505 = bits(command_reg, 15, 12) @[dbg.scala 328:113]
-    node _T_506 = eq(_T_505, UInt<1>("h00")) @[dbg.scala 328:122]
-    node _T_507 = cat(UInt<1>("h00"), _T_506) @[Cat.scala 29:58]
-    node _T_508 = mux(_T_504, UInt<2>("h02"), _T_507) @[dbg.scala 328:40]
-    io.dbg_dec.dbg_ib.dbg_cmd_type <= _T_508 @[dbg.scala 328:34]
-    node _T_509 = bits(command_reg, 21, 20) @[dbg.scala 329:33]
-    io.dbg_cmd_size <= _T_509 @[dbg.scala 329:19]
-    node _T_510 = eq(dbg_state, UInt<3>("h03")) @[dbg.scala 330:47]
-    node _T_511 = bits(abstractcs_reg, 10, 8) @[dbg.scala 330:88]
-    node _T_512 = orr(_T_511) @[dbg.scala 330:96]
-    node _T_513 = eq(_T_512, UInt<1>("h00")) @[dbg.scala 330:72]
-    node _T_514 = and(_T_510, _T_513) @[dbg.scala 330:70]
-    node _T_515 = eq(dbg_state, UInt<3>("h04")) @[dbg.scala 330:114]
-    node _T_516 = or(_T_514, _T_515) @[dbg.scala 330:101]
-    node _T_517 = bits(_T_516, 0, 0) @[dbg.scala 330:143]
-    io.dbg_dma_io.dbg_dma_bubble <= _T_517 @[dbg.scala 330:32]
+    io.dmi_reg_rdata <= _T_469 @[dbg.scala 325:20]
+    node _T_470 = bits(command_reg, 31, 24) @[dbg.scala 329:53]
+    node _T_471 = eq(_T_470, UInt<2>("h02")) @[dbg.scala 329:62]
+    node _T_472 = bits(data1_reg, 31, 2) @[dbg.scala 329:88]
+    node _T_473 = cat(_T_472, UInt<2>("h00")) @[Cat.scala 29:58]
+    node _T_474 = bits(command_reg, 11, 0) @[dbg.scala 329:138]
+    node _T_475 = cat(UInt<20>("h00"), _T_474) @[Cat.scala 29:58]
+    node _T_476 = mux(_T_471, _T_473, _T_475) @[dbg.scala 329:40]
+    io.dbg_dec.dbg_ib.dbg_cmd_addr <= _T_476 @[dbg.scala 329:34]
+    node _T_477 = bits(data0_reg, 31, 0) @[dbg.scala 330:50]
+    io.dbg_dec.dbg_dctl.dbg_cmd_wrdata <= _T_477 @[dbg.scala 330:38]
+    node _T_478 = eq(dbg_state, UInt<3>("h03")) @[dbg.scala 331:50]
+    node _T_479 = bits(abstractcs_reg, 10, 8) @[dbg.scala 331:91]
+    node _T_480 = orr(_T_479) @[dbg.scala 331:99]
+    node _T_481 = eq(_T_480, UInt<1>("h00")) @[dbg.scala 331:75]
+    node _T_482 = and(_T_478, _T_481) @[dbg.scala 331:73]
+    node _T_483 = and(_T_482, io.dbg_dma_io.dma_dbg_ready) @[dbg.scala 331:104]
+    node _T_484 = bits(_T_483, 0, 0) @[dbg.scala 331:141]
+    io.dbg_dec.dbg_ib.dbg_cmd_valid <= _T_484 @[dbg.scala 331:35]
+    node _T_485 = bits(command_reg, 16, 16) @[dbg.scala 332:49]
+    node _T_486 = bits(_T_485, 0, 0) @[dbg.scala 332:60]
+    io.dbg_dec.dbg_ib.dbg_cmd_write <= _T_486 @[dbg.scala 332:35]
+    node _T_487 = bits(command_reg, 31, 24) @[dbg.scala 333:53]
+    node _T_488 = eq(_T_487, UInt<2>("h02")) @[dbg.scala 333:62]
+    node _T_489 = bits(command_reg, 15, 12) @[dbg.scala 333:113]
+    node _T_490 = eq(_T_489, UInt<1>("h00")) @[dbg.scala 333:122]
+    node _T_491 = cat(UInt<1>("h00"), _T_490) @[Cat.scala 29:58]
+    node _T_492 = mux(_T_488, UInt<2>("h02"), _T_491) @[dbg.scala 333:40]
+    io.dbg_dec.dbg_ib.dbg_cmd_type <= _T_492 @[dbg.scala 333:34]
+    node _T_493 = bits(command_reg, 21, 20) @[dbg.scala 334:33]
+    io.dbg_cmd_size <= _T_493 @[dbg.scala 334:19]
+    node _T_494 = eq(dbg_state, UInt<3>("h03")) @[dbg.scala 335:47]
+    node _T_495 = bits(abstractcs_reg, 10, 8) @[dbg.scala 335:88]
+    node _T_496 = orr(_T_495) @[dbg.scala 335:96]
+    node _T_497 = eq(_T_496, UInt<1>("h00")) @[dbg.scala 335:72]
+    node _T_498 = and(_T_494, _T_497) @[dbg.scala 335:70]
+    node _T_499 = eq(dbg_state, UInt<3>("h04")) @[dbg.scala 335:114]
+    node _T_500 = or(_T_498, _T_499) @[dbg.scala 335:101]
+    node _T_501 = bits(_T_500, 0, 0) @[dbg.scala 335:143]
+    io.dbg_dma_io.dbg_dma_bubble <= _T_501 @[dbg.scala 335:32]
     wire sb_nxtstate : UInt<4>
     sb_nxtstate <= UInt<4>("h00")
-    sb_nxtstate <= UInt<4>("h00") @[dbg.scala 333:15]
-    sbcs_sbbusy_wren <= UInt<1>("h00") @[dbg.scala 335:20]
-    sbcs_sbbusy_din <= UInt<1>("h00") @[dbg.scala 336:19]
-    sbcs_sberror_wren <= UInt<1>("h00") @[dbg.scala 337:21]
-    sbcs_sberror_din <= UInt<3>("h00") @[dbg.scala 338:20]
-    sbaddress0_reg_wren1 <= UInt<1>("h00") @[dbg.scala 339:24]
-    node _T_518 = eq(UInt<4>("h00"), sb_state) @[Conditional.scala 37:30]
-    when _T_518 : @[Conditional.scala 40:58]
-      node _T_519 = mux(sbdata0wr_access, UInt<4>("h02"), UInt<4>("h01")) @[dbg.scala 342:25]
-      sb_nxtstate <= _T_519 @[dbg.scala 342:19]
-      node _T_520 = or(sbdata0wr_access, sbreadondata_access) @[dbg.scala 343:39]
-      node _T_521 = or(_T_520, sbreadonaddr_access) @[dbg.scala 343:61]
-      sb_state_en <= _T_521 @[dbg.scala 343:19]
-      sbcs_sbbusy_wren <= sb_state_en @[dbg.scala 344:24]
-      sbcs_sbbusy_din <= UInt<1>("h01") @[dbg.scala 345:23]
-      node _T_522 = bits(io.dmi_reg_wdata, 14, 12) @[dbg.scala 346:56]
-      node _T_523 = orr(_T_522) @[dbg.scala 346:65]
-      node _T_524 = and(sbcs_wren, _T_523) @[dbg.scala 346:38]
-      sbcs_sberror_wren <= _T_524 @[dbg.scala 346:25]
-      node _T_525 = bits(io.dmi_reg_wdata, 14, 12) @[dbg.scala 347:44]
-      node _T_526 = not(_T_525) @[dbg.scala 347:27]
-      node _T_527 = bits(sbcs_reg, 14, 12) @[dbg.scala 347:63]
-      node _T_528 = and(_T_526, _T_527) @[dbg.scala 347:53]
-      sbcs_sberror_din <= _T_528 @[dbg.scala 347:24]
+    sb_nxtstate <= UInt<4>("h00") @[dbg.scala 338:15]
+    sbcs_sbbusy_wren <= UInt<1>("h00") @[dbg.scala 340:20]
+    sbcs_sbbusy_din <= UInt<1>("h00") @[dbg.scala 341:19]
+    sbcs_sberror_wren <= UInt<1>("h00") @[dbg.scala 342:21]
+    sbcs_sberror_din <= UInt<3>("h00") @[dbg.scala 343:20]
+    sbaddress0_reg_wren1 <= UInt<1>("h00") @[dbg.scala 344:24]
+    node _T_502 = eq(UInt<4>("h00"), sb_state) @[Conditional.scala 37:30]
+    when _T_502 : @[Conditional.scala 40:58]
+      node _T_503 = mux(sbdata0wr_access, UInt<4>("h02"), UInt<4>("h01")) @[dbg.scala 347:25]
+      sb_nxtstate <= _T_503 @[dbg.scala 347:19]
+      node _T_504 = or(sbdata0wr_access, sbreadondata_access) @[dbg.scala 348:39]
+      node _T_505 = or(_T_504, sbreadonaddr_access) @[dbg.scala 348:61]
+      sb_state_en <= _T_505 @[dbg.scala 348:19]
+      sbcs_sbbusy_wren <= sb_state_en @[dbg.scala 349:24]
+      sbcs_sbbusy_din <= UInt<1>("h01") @[dbg.scala 350:23]
+      node _T_506 = bits(io.dmi_reg_wdata, 14, 12) @[dbg.scala 351:56]
+      node _T_507 = orr(_T_506) @[dbg.scala 351:65]
+      node _T_508 = and(sbcs_wren, _T_507) @[dbg.scala 351:38]
+      sbcs_sberror_wren <= _T_508 @[dbg.scala 351:25]
+      node _T_509 = bits(io.dmi_reg_wdata, 14, 12) @[dbg.scala 352:44]
+      node _T_510 = not(_T_509) @[dbg.scala 352:27]
+      node _T_511 = bits(sbcs_reg, 14, 12) @[dbg.scala 352:63]
+      node _T_512 = and(_T_510, _T_511) @[dbg.scala 352:53]
+      sbcs_sberror_din <= _T_512 @[dbg.scala 352:24]
       skip @[Conditional.scala 40:58]
     else : @[Conditional.scala 39:67]
-      node _T_529 = eq(UInt<4>("h01"), sb_state) @[Conditional.scala 37:30]
-      when _T_529 : @[Conditional.scala 39:67]
-        node _T_530 = or(sbcs_unaligned, sbcs_illegal_size) @[dbg.scala 350:41]
-        node _T_531 = mux(_T_530, UInt<4>("h09"), UInt<4>("h03")) @[dbg.scala 350:25]
-        sb_nxtstate <= _T_531 @[dbg.scala 350:19]
-        node _T_532 = or(io.dbg_bus_clk_en, sbcs_unaligned) @[dbg.scala 351:40]
-        node _T_533 = or(_T_532, sbcs_illegal_size) @[dbg.scala 351:57]
-        sb_state_en <= _T_533 @[dbg.scala 351:19]
-        node _T_534 = or(sbcs_unaligned, sbcs_illegal_size) @[dbg.scala 352:43]
-        sbcs_sberror_wren <= _T_534 @[dbg.scala 352:25]
-        node _T_535 = mux(sbcs_unaligned, UInt<3>("h03"), UInt<3>("h04")) @[dbg.scala 353:30]
-        sbcs_sberror_din <= _T_535 @[dbg.scala 353:24]
+      node _T_513 = eq(UInt<4>("h01"), sb_state) @[Conditional.scala 37:30]
+      when _T_513 : @[Conditional.scala 39:67]
+        node _T_514 = or(sbcs_unaligned, sbcs_illegal_size) @[dbg.scala 355:41]
+        node _T_515 = mux(_T_514, UInt<4>("h09"), UInt<4>("h03")) @[dbg.scala 355:25]
+        sb_nxtstate <= _T_515 @[dbg.scala 355:19]
+        node _T_516 = or(io.dbg_bus_clk_en, sbcs_unaligned) @[dbg.scala 356:40]
+        node _T_517 = or(_T_516, sbcs_illegal_size) @[dbg.scala 356:57]
+        sb_state_en <= _T_517 @[dbg.scala 356:19]
+        node _T_518 = or(sbcs_unaligned, sbcs_illegal_size) @[dbg.scala 357:43]
+        sbcs_sberror_wren <= _T_518 @[dbg.scala 357:25]
+        node _T_519 = mux(sbcs_unaligned, UInt<3>("h03"), UInt<3>("h04")) @[dbg.scala 358:30]
+        sbcs_sberror_din <= _T_519 @[dbg.scala 358:24]
         skip @[Conditional.scala 39:67]
       else : @[Conditional.scala 39:67]
-        node _T_536 = eq(UInt<4>("h02"), sb_state) @[Conditional.scala 37:30]
-        when _T_536 : @[Conditional.scala 39:67]
-          node _T_537 = or(sbcs_unaligned, sbcs_illegal_size) @[dbg.scala 356:41]
-          node _T_538 = mux(_T_537, UInt<4>("h09"), UInt<4>("h04")) @[dbg.scala 356:25]
-          sb_nxtstate <= _T_538 @[dbg.scala 356:19]
-          node _T_539 = or(io.dbg_bus_clk_en, sbcs_unaligned) @[dbg.scala 357:40]
-          node _T_540 = or(_T_539, sbcs_illegal_size) @[dbg.scala 357:57]
-          sb_state_en <= _T_540 @[dbg.scala 357:19]
-          node _T_541 = or(sbcs_unaligned, sbcs_illegal_size) @[dbg.scala 358:43]
-          sbcs_sberror_wren <= _T_541 @[dbg.scala 358:25]
-          node _T_542 = mux(sbcs_unaligned, UInt<3>("h03"), UInt<3>("h04")) @[dbg.scala 359:30]
-          sbcs_sberror_din <= _T_542 @[dbg.scala 359:24]
+        node _T_520 = eq(UInt<4>("h02"), sb_state) @[Conditional.scala 37:30]
+        when _T_520 : @[Conditional.scala 39:67]
+          node _T_521 = or(sbcs_unaligned, sbcs_illegal_size) @[dbg.scala 361:41]
+          node _T_522 = mux(_T_521, UInt<4>("h09"), UInt<4>("h04")) @[dbg.scala 361:25]
+          sb_nxtstate <= _T_522 @[dbg.scala 361:19]
+          node _T_523 = or(io.dbg_bus_clk_en, sbcs_unaligned) @[dbg.scala 362:40]
+          node _T_524 = or(_T_523, sbcs_illegal_size) @[dbg.scala 362:57]
+          sb_state_en <= _T_524 @[dbg.scala 362:19]
+          node _T_525 = or(sbcs_unaligned, sbcs_illegal_size) @[dbg.scala 363:43]
+          sbcs_sberror_wren <= _T_525 @[dbg.scala 363:25]
+          node _T_526 = mux(sbcs_unaligned, UInt<3>("h03"), UInt<3>("h04")) @[dbg.scala 364:30]
+          sbcs_sberror_din <= _T_526 @[dbg.scala 364:24]
           skip @[Conditional.scala 39:67]
         else : @[Conditional.scala 39:67]
-          node _T_543 = eq(UInt<4>("h03"), sb_state) @[Conditional.scala 37:30]
-          when _T_543 : @[Conditional.scala 39:67]
-            sb_nxtstate <= UInt<4>("h07") @[dbg.scala 362:19]
-            node _T_544 = and(sb_bus_cmd_read, io.dbg_bus_clk_en) @[dbg.scala 363:38]
-            sb_state_en <= _T_544 @[dbg.scala 363:19]
+          node _T_527 = eq(UInt<4>("h03"), sb_state) @[Conditional.scala 37:30]
+          when _T_527 : @[Conditional.scala 39:67]
+            sb_nxtstate <= UInt<4>("h07") @[dbg.scala 367:19]
+            node _T_528 = and(sb_bus_cmd_read, io.dbg_bus_clk_en) @[dbg.scala 368:38]
+            sb_state_en <= _T_528 @[dbg.scala 368:19]
             skip @[Conditional.scala 39:67]
           else : @[Conditional.scala 39:67]
-            node _T_545 = eq(UInt<4>("h04"), sb_state) @[Conditional.scala 37:30]
-            when _T_545 : @[Conditional.scala 39:67]
-              node _T_546 = and(sb_bus_cmd_write_addr, sb_bus_cmd_write_data) @[dbg.scala 366:48]
-              node _T_547 = mux(sb_bus_cmd_write_data, UInt<4>("h05"), UInt<4>("h06")) @[dbg.scala 366:95]
-              node _T_548 = mux(_T_546, UInt<4>("h08"), _T_547) @[dbg.scala 366:25]
-              sb_nxtstate <= _T_548 @[dbg.scala 366:19]
-              node _T_549 = or(sb_bus_cmd_write_addr, sb_bus_cmd_write_data) @[dbg.scala 367:45]
-              node _T_550 = and(_T_549, io.dbg_bus_clk_en) @[dbg.scala 367:70]
-              sb_state_en <= _T_550 @[dbg.scala 367:19]
+            node _T_529 = eq(UInt<4>("h04"), sb_state) @[Conditional.scala 37:30]
+            when _T_529 : @[Conditional.scala 39:67]
+              node _T_530 = and(sb_bus_cmd_write_addr, sb_bus_cmd_write_data) @[dbg.scala 371:48]
+              node _T_531 = mux(sb_bus_cmd_write_data, UInt<4>("h05"), UInt<4>("h06")) @[dbg.scala 371:95]
+              node _T_532 = mux(_T_530, UInt<4>("h08"), _T_531) @[dbg.scala 371:25]
+              sb_nxtstate <= _T_532 @[dbg.scala 371:19]
+              node _T_533 = or(sb_bus_cmd_write_addr, sb_bus_cmd_write_data) @[dbg.scala 372:45]
+              node _T_534 = and(_T_533, io.dbg_bus_clk_en) @[dbg.scala 372:70]
+              sb_state_en <= _T_534 @[dbg.scala 372:19]
               skip @[Conditional.scala 39:67]
             else : @[Conditional.scala 39:67]
-              node _T_551 = eq(UInt<4>("h05"), sb_state) @[Conditional.scala 37:30]
-              when _T_551 : @[Conditional.scala 39:67]
-                sb_nxtstate <= UInt<4>("h08") @[dbg.scala 370:19]
-                node _T_552 = and(sb_bus_cmd_write_addr, io.dbg_bus_clk_en) @[dbg.scala 371:44]
-                sb_state_en <= _T_552 @[dbg.scala 371:19]
+              node _T_535 = eq(UInt<4>("h05"), sb_state) @[Conditional.scala 37:30]
+              when _T_535 : @[Conditional.scala 39:67]
+                sb_nxtstate <= UInt<4>("h08") @[dbg.scala 375:19]
+                node _T_536 = and(sb_bus_cmd_write_addr, io.dbg_bus_clk_en) @[dbg.scala 376:44]
+                sb_state_en <= _T_536 @[dbg.scala 376:19]
                 skip @[Conditional.scala 39:67]
               else : @[Conditional.scala 39:67]
-                node _T_553 = eq(UInt<4>("h06"), sb_state) @[Conditional.scala 37:30]
-                when _T_553 : @[Conditional.scala 39:67]
-                  sb_nxtstate <= UInt<4>("h08") @[dbg.scala 374:19]
-                  node _T_554 = and(sb_bus_cmd_write_data, io.dbg_bus_clk_en) @[dbg.scala 375:44]
-                  sb_state_en <= _T_554 @[dbg.scala 375:19]
+                node _T_537 = eq(UInt<4>("h06"), sb_state) @[Conditional.scala 37:30]
+                when _T_537 : @[Conditional.scala 39:67]
+                  sb_nxtstate <= UInt<4>("h08") @[dbg.scala 379:19]
+                  node _T_538 = and(sb_bus_cmd_write_data, io.dbg_bus_clk_en) @[dbg.scala 380:44]
+                  sb_state_en <= _T_538 @[dbg.scala 380:19]
                   skip @[Conditional.scala 39:67]
                 else : @[Conditional.scala 39:67]
-                  node _T_555 = eq(UInt<4>("h07"), sb_state) @[Conditional.scala 37:30]
-                  when _T_555 : @[Conditional.scala 39:67]
-                    sb_nxtstate <= UInt<4>("h09") @[dbg.scala 378:19]
-                    node _T_556 = and(sb_bus_rsp_read, io.dbg_bus_clk_en) @[dbg.scala 379:38]
-                    sb_state_en <= _T_556 @[dbg.scala 379:19]
-                    node _T_557 = and(sb_state_en, sb_bus_rsp_error) @[dbg.scala 380:40]
-                    sbcs_sberror_wren <= _T_557 @[dbg.scala 380:25]
-                    sbcs_sberror_din <= UInt<3>("h02") @[dbg.scala 381:24]
+                  node _T_539 = eq(UInt<4>("h07"), sb_state) @[Conditional.scala 37:30]
+                  when _T_539 : @[Conditional.scala 39:67]
+                    sb_nxtstate <= UInt<4>("h09") @[dbg.scala 383:19]
+                    node _T_540 = and(sb_bus_rsp_read, io.dbg_bus_clk_en) @[dbg.scala 384:38]
+                    sb_state_en <= _T_540 @[dbg.scala 384:19]
+                    node _T_541 = and(sb_state_en, sb_bus_rsp_error) @[dbg.scala 385:40]
+                    sbcs_sberror_wren <= _T_541 @[dbg.scala 385:25]
+                    sbcs_sberror_din <= UInt<3>("h02") @[dbg.scala 386:24]
                     skip @[Conditional.scala 39:67]
                   else : @[Conditional.scala 39:67]
-                    node _T_558 = eq(UInt<4>("h08"), sb_state) @[Conditional.scala 37:30]
-                    when _T_558 : @[Conditional.scala 39:67]
-                      sb_nxtstate <= UInt<4>("h09") @[dbg.scala 384:19]
-                      node _T_559 = and(sb_bus_rsp_write, io.dbg_bus_clk_en) @[dbg.scala 385:39]
-                      sb_state_en <= _T_559 @[dbg.scala 385:19]
-                      node _T_560 = and(sb_state_en, sb_bus_rsp_error) @[dbg.scala 386:40]
-                      sbcs_sberror_wren <= _T_560 @[dbg.scala 386:25]
-                      sbcs_sberror_din <= UInt<3>("h02") @[dbg.scala 387:24]
+                    node _T_542 = eq(UInt<4>("h08"), sb_state) @[Conditional.scala 37:30]
+                    when _T_542 : @[Conditional.scala 39:67]
+                      sb_nxtstate <= UInt<4>("h09") @[dbg.scala 389:19]
+                      node _T_543 = and(sb_bus_rsp_write, io.dbg_bus_clk_en) @[dbg.scala 390:39]
+                      sb_state_en <= _T_543 @[dbg.scala 390:19]
+                      node _T_544 = and(sb_state_en, sb_bus_rsp_error) @[dbg.scala 391:40]
+                      sbcs_sberror_wren <= _T_544 @[dbg.scala 391:25]
+                      sbcs_sberror_din <= UInt<3>("h02") @[dbg.scala 392:24]
                       skip @[Conditional.scala 39:67]
                     else : @[Conditional.scala 39:67]
-                      node _T_561 = eq(UInt<4>("h09"), sb_state) @[Conditional.scala 37:30]
-                      when _T_561 : @[Conditional.scala 39:67]
-                        sb_nxtstate <= UInt<4>("h00") @[dbg.scala 390:19]
-                        sb_state_en <= UInt<1>("h01") @[dbg.scala 391:19]
-                        sbcs_sbbusy_wren <= UInt<1>("h01") @[dbg.scala 392:24]
-                        sbcs_sbbusy_din <= UInt<1>("h00") @[dbg.scala 393:23]
-                        node _T_562 = bits(sbcs_reg, 16, 16) @[dbg.scala 394:39]
-                        sbaddress0_reg_wren1 <= _T_562 @[dbg.scala 394:28]
+                      node _T_545 = eq(UInt<4>("h09"), sb_state) @[Conditional.scala 37:30]
+                      when _T_545 : @[Conditional.scala 39:67]
+                        sb_nxtstate <= UInt<4>("h00") @[dbg.scala 395:19]
+                        sb_state_en <= UInt<1>("h01") @[dbg.scala 396:19]
+                        sbcs_sbbusy_wren <= UInt<1>("h01") @[dbg.scala 397:24]
+                        sbcs_sbbusy_din <= UInt<1>("h00") @[dbg.scala 398:23]
+                        node _T_546 = bits(sbcs_reg, 16, 16) @[dbg.scala 399:39]
+                        sbaddress0_reg_wren1 <= _T_546 @[dbg.scala 399:28]
                         skip @[Conditional.scala 39:67]
-    node _T_563 = asAsyncReset(dbg_dm_rst_l) @[dbg.scala 397:73]
-    reg _T_564 : UInt, rvclkhdr_1.io.l1clk with : (reset => (_T_563, UInt<1>("h00"))) @[Reg.scala 27:20]
+    reg _T_547 : UInt, rvclkhdr_1.io.l1clk with : (reset => (dbg_dm_rst_l, UInt<1>("h00"))) @[Reg.scala 27:20]
     when sb_state_en : @[Reg.scala 28:19]
-      _T_564 <= sb_nxtstate @[Reg.scala 28:23]
+      _T_547 <= sb_nxtstate @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    sb_state <= _T_564 @[dbg.scala 397:12]
-    node _T_565 = and(io.sb_axi.ar.valid, io.sb_axi.ar.ready) @[dbg.scala 401:41]
-    sb_bus_cmd_read <= _T_565 @[dbg.scala 401:19]
-    node _T_566 = and(io.sb_axi.aw.valid, io.sb_axi.aw.ready) @[dbg.scala 402:47]
-    sb_bus_cmd_write_addr <= _T_566 @[dbg.scala 402:25]
-    node _T_567 = and(io.sb_axi.w.valid, io.sb_axi.w.ready) @[dbg.scala 403:46]
-    sb_bus_cmd_write_data <= _T_567 @[dbg.scala 403:25]
-    node _T_568 = and(io.sb_axi.r.valid, io.sb_axi.r.ready) @[dbg.scala 404:40]
-    sb_bus_rsp_read <= _T_568 @[dbg.scala 404:19]
-    node _T_569 = and(io.sb_axi.b.valid, io.sb_axi.b.ready) @[dbg.scala 405:41]
-    sb_bus_rsp_write <= _T_569 @[dbg.scala 405:20]
-    node _T_570 = bits(io.sb_axi.r.bits.resp, 1, 0) @[dbg.scala 406:62]
-    node _T_571 = orr(_T_570) @[dbg.scala 406:69]
-    node _T_572 = and(sb_bus_rsp_read, _T_571) @[dbg.scala 406:39]
-    node _T_573 = bits(io.sb_axi.b.bits.resp, 1, 0) @[dbg.scala 406:115]
-    node _T_574 = orr(_T_573) @[dbg.scala 406:122]
-    node _T_575 = and(sb_bus_rsp_write, _T_574) @[dbg.scala 406:92]
-    node _T_576 = or(_T_572, _T_575) @[dbg.scala 406:73]
-    sb_bus_rsp_error <= _T_576 @[dbg.scala 406:20]
-    node _T_577 = eq(sb_state, UInt<4>("h04")) @[dbg.scala 407:36]
-    node _T_578 = eq(sb_state, UInt<4>("h05")) @[dbg.scala 407:71]
-    node _T_579 = or(_T_577, _T_578) @[dbg.scala 407:59]
-    node _T_580 = bits(_T_579, 0, 0) @[dbg.scala 407:106]
-    io.sb_axi.aw.valid <= _T_580 @[dbg.scala 407:22]
-    io.sb_axi.aw.bits.addr <= sbaddress0_reg @[dbg.scala 408:26]
-    io.sb_axi.aw.bits.id <= UInt<1>("h00") @[dbg.scala 409:24]
-    node _T_581 = bits(sbcs_reg, 19, 17) @[dbg.scala 410:37]
-    io.sb_axi.aw.bits.size <= _T_581 @[dbg.scala 410:26]
-    io.sb_axi.aw.bits.prot <= UInt<1>("h00") @[dbg.scala 411:26]
-    io.sb_axi.aw.bits.cache <= UInt<4>("h0f") @[dbg.scala 412:27]
-    node _T_582 = bits(sbaddress0_reg, 31, 28) @[dbg.scala 413:45]
-    io.sb_axi.aw.bits.region <= _T_582 @[dbg.scala 413:28]
-    io.sb_axi.aw.bits.len <= UInt<1>("h00") @[dbg.scala 414:25]
-    io.sb_axi.aw.bits.burst <= UInt<2>("h01") @[dbg.scala 415:27]
-    io.sb_axi.aw.bits.qos <= UInt<1>("h00") @[dbg.scala 416:25]
-    io.sb_axi.aw.bits.lock <= UInt<1>("h00") @[dbg.scala 417:26]
-    node _T_583 = eq(sb_state, UInt<4>("h04")) @[dbg.scala 418:35]
-    node _T_584 = eq(sb_state, UInt<4>("h06")) @[dbg.scala 418:70]
-    node _T_585 = or(_T_583, _T_584) @[dbg.scala 418:58]
-    node _T_586 = bits(_T_585, 0, 0) @[dbg.scala 418:105]
-    io.sb_axi.w.valid <= _T_586 @[dbg.scala 418:21]
-    node _T_587 = bits(sbcs_reg, 19, 17) @[dbg.scala 419:46]
-    node _T_588 = eq(_T_587, UInt<1>("h00")) @[dbg.scala 419:55]
-    node _T_589 = bits(_T_588, 0, 0) @[Bitwise.scala 72:15]
-    node _T_590 = mux(_T_589, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12]
-    node _T_591 = bits(sbdata0_reg, 7, 0) @[dbg.scala 419:87]
-    node _T_592 = cat(_T_591, _T_591) @[Cat.scala 29:58]
+    sb_state <= _T_547 @[dbg.scala 402:12]
+    node _T_548 = and(io.sb_axi.ar.valid, io.sb_axi.ar.ready) @[dbg.scala 406:41]
+    sb_bus_cmd_read <= _T_548 @[dbg.scala 406:19]
+    node _T_549 = and(io.sb_axi.aw.valid, io.sb_axi.aw.ready) @[dbg.scala 407:47]
+    sb_bus_cmd_write_addr <= _T_549 @[dbg.scala 407:25]
+    node _T_550 = and(io.sb_axi.w.valid, io.sb_axi.w.ready) @[dbg.scala 408:46]
+    sb_bus_cmd_write_data <= _T_550 @[dbg.scala 408:25]
+    node _T_551 = and(io.sb_axi.r.valid, io.sb_axi.r.ready) @[dbg.scala 409:40]
+    sb_bus_rsp_read <= _T_551 @[dbg.scala 409:19]
+    node _T_552 = and(io.sb_axi.b.valid, io.sb_axi.b.ready) @[dbg.scala 410:41]
+    sb_bus_rsp_write <= _T_552 @[dbg.scala 410:20]
+    node _T_553 = bits(io.sb_axi.r.bits.resp, 1, 0) @[dbg.scala 411:62]
+    node _T_554 = orr(_T_553) @[dbg.scala 411:69]
+    node _T_555 = and(sb_bus_rsp_read, _T_554) @[dbg.scala 411:39]
+    node _T_556 = bits(io.sb_axi.b.bits.resp, 1, 0) @[dbg.scala 411:115]
+    node _T_557 = orr(_T_556) @[dbg.scala 411:122]
+    node _T_558 = and(sb_bus_rsp_write, _T_557) @[dbg.scala 411:92]
+    node _T_559 = or(_T_555, _T_558) @[dbg.scala 411:73]
+    sb_bus_rsp_error <= _T_559 @[dbg.scala 411:20]
+    node _T_560 = eq(sb_state, UInt<4>("h04")) @[dbg.scala 412:36]
+    node _T_561 = eq(sb_state, UInt<4>("h05")) @[dbg.scala 412:71]
+    node _T_562 = or(_T_560, _T_561) @[dbg.scala 412:59]
+    node _T_563 = bits(_T_562, 0, 0) @[dbg.scala 412:106]
+    io.sb_axi.aw.valid <= _T_563 @[dbg.scala 412:22]
+    io.sb_axi.aw.bits.addr <= sbaddress0_reg @[dbg.scala 413:26]
+    io.sb_axi.aw.bits.id <= UInt<1>("h00") @[dbg.scala 414:24]
+    node _T_564 = bits(sbcs_reg, 19, 17) @[dbg.scala 415:37]
+    io.sb_axi.aw.bits.size <= _T_564 @[dbg.scala 415:26]
+    io.sb_axi.aw.bits.prot <= UInt<1>("h00") @[dbg.scala 416:26]
+    io.sb_axi.aw.bits.cache <= UInt<4>("h0f") @[dbg.scala 417:27]
+    node _T_565 = bits(sbaddress0_reg, 31, 28) @[dbg.scala 418:45]
+    io.sb_axi.aw.bits.region <= _T_565 @[dbg.scala 418:28]
+    io.sb_axi.aw.bits.len <= UInt<1>("h00") @[dbg.scala 419:25]
+    io.sb_axi.aw.bits.burst <= UInt<2>("h01") @[dbg.scala 420:27]
+    io.sb_axi.aw.bits.qos <= UInt<1>("h00") @[dbg.scala 421:25]
+    io.sb_axi.aw.bits.lock <= UInt<1>("h00") @[dbg.scala 422:26]
+    node _T_566 = eq(sb_state, UInt<4>("h04")) @[dbg.scala 423:35]
+    node _T_567 = eq(sb_state, UInt<4>("h06")) @[dbg.scala 423:70]
+    node _T_568 = or(_T_566, _T_567) @[dbg.scala 423:58]
+    node _T_569 = bits(_T_568, 0, 0) @[dbg.scala 423:105]
+    io.sb_axi.w.valid <= _T_569 @[dbg.scala 423:21]
+    node _T_570 = bits(sbcs_reg, 19, 17) @[dbg.scala 424:46]
+    node _T_571 = eq(_T_570, UInt<1>("h00")) @[dbg.scala 424:55]
+    node _T_572 = bits(_T_571, 0, 0) @[Bitwise.scala 72:15]
+    node _T_573 = mux(_T_572, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12]
+    node _T_574 = bits(sbdata0_reg, 7, 0) @[dbg.scala 424:87]
+    node _T_575 = cat(_T_574, _T_574) @[Cat.scala 29:58]
+    node _T_576 = cat(_T_575, _T_575) @[Cat.scala 29:58]
+    node _T_577 = cat(_T_576, _T_576) @[Cat.scala 29:58]
+    node _T_578 = and(_T_573, _T_577) @[dbg.scala 424:65]
+    node _T_579 = bits(sbcs_reg, 19, 17) @[dbg.scala 424:116]
+    node _T_580 = eq(_T_579, UInt<1>("h01")) @[dbg.scala 424:125]
+    node _T_581 = bits(_T_580, 0, 0) @[Bitwise.scala 72:15]
+    node _T_582 = mux(_T_581, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12]
+    node _T_583 = bits(sbdata0_reg, 15, 0) @[dbg.scala 424:159]
+    node _T_584 = cat(_T_583, _T_583) @[Cat.scala 29:58]
+    node _T_585 = cat(_T_584, _T_584) @[Cat.scala 29:58]
+    node _T_586 = and(_T_582, _T_585) @[dbg.scala 424:138]
+    node _T_587 = or(_T_578, _T_586) @[dbg.scala 424:96]
+    node _T_588 = bits(sbcs_reg, 19, 17) @[dbg.scala 425:23]
+    node _T_589 = eq(_T_588, UInt<2>("h02")) @[dbg.scala 425:32]
+    node _T_590 = bits(_T_589, 0, 0) @[Bitwise.scala 72:15]
+    node _T_591 = mux(_T_590, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12]
+    node _T_592 = bits(sbdata0_reg, 31, 0) @[dbg.scala 425:67]
     node _T_593 = cat(_T_592, _T_592) @[Cat.scala 29:58]
-    node _T_594 = cat(_T_593, _T_593) @[Cat.scala 29:58]
-    node _T_595 = and(_T_590, _T_594) @[dbg.scala 419:65]
-    node _T_596 = bits(sbcs_reg, 19, 17) @[dbg.scala 419:116]
-    node _T_597 = eq(_T_596, UInt<1>("h01")) @[dbg.scala 419:125]
+    node _T_594 = and(_T_591, _T_593) @[dbg.scala 425:45]
+    node _T_595 = or(_T_587, _T_594) @[dbg.scala 424:168]
+    node _T_596 = bits(sbcs_reg, 19, 17) @[dbg.scala 425:97]
+    node _T_597 = eq(_T_596, UInt<2>("h03")) @[dbg.scala 425:106]
     node _T_598 = bits(_T_597, 0, 0) @[Bitwise.scala 72:15]
     node _T_599 = mux(_T_598, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12]
-    node _T_600 = bits(sbdata0_reg, 15, 0) @[dbg.scala 419:159]
-    node _T_601 = cat(_T_600, _T_600) @[Cat.scala 29:58]
-    node _T_602 = cat(_T_601, _T_601) @[Cat.scala 29:58]
-    node _T_603 = and(_T_599, _T_602) @[dbg.scala 419:138]
-    node _T_604 = or(_T_595, _T_603) @[dbg.scala 419:96]
-    node _T_605 = bits(sbcs_reg, 19, 17) @[dbg.scala 420:23]
-    node _T_606 = eq(_T_605, UInt<2>("h02")) @[dbg.scala 420:32]
+    node _T_600 = bits(sbdata1_reg, 31, 0) @[dbg.scala 425:136]
+    node _T_601 = bits(sbdata0_reg, 31, 0) @[dbg.scala 425:156]
+    node _T_602 = cat(_T_600, _T_601) @[Cat.scala 29:58]
+    node _T_603 = and(_T_599, _T_602) @[dbg.scala 425:119]
+    node _T_604 = or(_T_595, _T_603) @[dbg.scala 425:77]
+    io.sb_axi.w.bits.data <= _T_604 @[dbg.scala 424:25]
+    node _T_605 = bits(sbcs_reg, 19, 17) @[dbg.scala 427:45]
+    node _T_606 = eq(_T_605, UInt<1>("h00")) @[dbg.scala 427:54]
     node _T_607 = bits(_T_606, 0, 0) @[Bitwise.scala 72:15]
-    node _T_608 = mux(_T_607, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12]
-    node _T_609 = bits(sbdata0_reg, 31, 0) @[dbg.scala 420:67]
-    node _T_610 = cat(_T_609, _T_609) @[Cat.scala 29:58]
-    node _T_611 = and(_T_608, _T_610) @[dbg.scala 420:45]
-    node _T_612 = or(_T_604, _T_611) @[dbg.scala 419:168]
-    node _T_613 = bits(sbcs_reg, 19, 17) @[dbg.scala 420:97]
-    node _T_614 = eq(_T_613, UInt<2>("h03")) @[dbg.scala 420:106]
-    node _T_615 = bits(_T_614, 0, 0) @[Bitwise.scala 72:15]
-    node _T_616 = mux(_T_615, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12]
-    node _T_617 = bits(sbdata1_reg, 31, 0) @[dbg.scala 420:136]
-    node _T_618 = bits(sbdata0_reg, 31, 0) @[dbg.scala 420:156]
-    node _T_619 = cat(_T_617, _T_618) @[Cat.scala 29:58]
-    node _T_620 = and(_T_616, _T_619) @[dbg.scala 420:119]
-    node _T_621 = or(_T_612, _T_620) @[dbg.scala 420:77]
-    io.sb_axi.w.bits.data <= _T_621 @[dbg.scala 419:25]
-    node _T_622 = bits(sbcs_reg, 19, 17) @[dbg.scala 422:45]
-    node _T_623 = eq(_T_622, UInt<1>("h00")) @[dbg.scala 422:54]
-    node _T_624 = bits(_T_623, 0, 0) @[Bitwise.scala 72:15]
-    node _T_625 = mux(_T_624, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
-    node _T_626 = bits(sbaddress0_reg, 2, 0) @[dbg.scala 422:99]
-    node _T_627 = dshl(UInt<8>("h01"), _T_626) @[dbg.scala 422:82]
-    node _T_628 = and(_T_625, _T_627) @[dbg.scala 422:67]
-    node _T_629 = bits(sbcs_reg, 19, 17) @[dbg.scala 423:22]
-    node _T_630 = eq(_T_629, UInt<1>("h01")) @[dbg.scala 423:31]
-    node _T_631 = bits(_T_630, 0, 0) @[Bitwise.scala 72:15]
-    node _T_632 = mux(_T_631, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
-    node _T_633 = bits(sbaddress0_reg, 2, 1) @[dbg.scala 423:80]
-    node _T_634 = cat(_T_633, UInt<1>("h00")) @[Cat.scala 29:58]
-    node _T_635 = dshl(UInt<8>("h03"), _T_634) @[dbg.scala 423:59]
-    node _T_636 = and(_T_632, _T_635) @[dbg.scala 423:44]
-    node _T_637 = or(_T_628, _T_636) @[dbg.scala 422:107]
-    node _T_638 = bits(sbcs_reg, 19, 17) @[dbg.scala 424:22]
-    node _T_639 = eq(_T_638, UInt<2>("h02")) @[dbg.scala 424:31]
-    node _T_640 = bits(_T_639, 0, 0) @[Bitwise.scala 72:15]
-    node _T_641 = mux(_T_640, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
-    node _T_642 = bits(sbaddress0_reg, 2, 2) @[dbg.scala 424:80]
-    node _T_643 = cat(_T_642, UInt<2>("h00")) @[Cat.scala 29:58]
-    node _T_644 = dshl(UInt<8>("h0f"), _T_643) @[dbg.scala 424:59]
-    node _T_645 = and(_T_641, _T_644) @[dbg.scala 424:44]
-    node _T_646 = or(_T_637, _T_645) @[dbg.scala 423:97]
-    node _T_647 = bits(sbcs_reg, 19, 17) @[dbg.scala 425:22]
-    node _T_648 = eq(_T_647, UInt<2>("h03")) @[dbg.scala 425:31]
-    node _T_649 = bits(_T_648, 0, 0) @[Bitwise.scala 72:15]
-    node _T_650 = mux(_T_649, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
-    node _T_651 = and(_T_650, UInt<8>("h0ff")) @[dbg.scala 425:44]
-    node _T_652 = or(_T_646, _T_651) @[dbg.scala 424:100]
-    io.sb_axi.w.bits.strb <= _T_652 @[dbg.scala 422:25]
-    io.sb_axi.w.bits.last <= UInt<1>("h01") @[dbg.scala 427:25]
-    node _T_653 = eq(sb_state, UInt<4>("h03")) @[dbg.scala 428:35]
-    node _T_654 = bits(_T_653, 0, 0) @[dbg.scala 428:64]
-    io.sb_axi.ar.valid <= _T_654 @[dbg.scala 428:22]
-    io.sb_axi.ar.bits.addr <= sbaddress0_reg @[dbg.scala 429:26]
-    io.sb_axi.ar.bits.id <= UInt<1>("h00") @[dbg.scala 430:24]
-    node _T_655 = bits(sbcs_reg, 19, 17) @[dbg.scala 431:37]
-    io.sb_axi.ar.bits.size <= _T_655 @[dbg.scala 431:26]
-    io.sb_axi.ar.bits.prot <= UInt<1>("h00") @[dbg.scala 432:26]
-    io.sb_axi.ar.bits.cache <= UInt<1>("h00") @[dbg.scala 433:27]
-    node _T_656 = bits(sbaddress0_reg, 31, 28) @[dbg.scala 434:45]
-    io.sb_axi.ar.bits.region <= _T_656 @[dbg.scala 434:28]
-    io.sb_axi.ar.bits.len <= UInt<1>("h00") @[dbg.scala 435:25]
-    io.sb_axi.ar.bits.burst <= UInt<2>("h01") @[dbg.scala 436:27]
-    io.sb_axi.ar.bits.qos <= UInt<1>("h00") @[dbg.scala 437:25]
-    io.sb_axi.ar.bits.lock <= UInt<1>("h00") @[dbg.scala 438:26]
-    io.sb_axi.b.ready <= UInt<1>("h01") @[dbg.scala 439:21]
-    io.sb_axi.r.ready <= UInt<1>("h01") @[dbg.scala 440:21]
-    node _T_657 = bits(sbcs_reg, 19, 17) @[dbg.scala 441:37]
-    node _T_658 = eq(_T_657, UInt<1>("h00")) @[dbg.scala 441:46]
-    node _T_659 = bits(_T_658, 0, 0) @[Bitwise.scala 72:15]
-    node _T_660 = mux(_T_659, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12]
-    node _T_661 = bits(io.sb_axi.r.bits.data, 63, 0) @[dbg.scala 441:84]
-    node _T_662 = bits(sbaddress0_reg, 2, 0) @[dbg.scala 441:115]
-    node _T_663 = mul(UInt<4>("h08"), _T_662) @[dbg.scala 441:99]
-    node _T_664 = dshr(_T_661, _T_663) @[dbg.scala 441:92]
-    node _T_665 = and(_T_664, UInt<64>("h0ff")) @[dbg.scala 441:123]
-    node _T_666 = and(_T_660, _T_665) @[dbg.scala 441:59]
-    node _T_667 = bits(sbcs_reg, 19, 17) @[dbg.scala 442:23]
-    node _T_668 = eq(_T_667, UInt<1>("h01")) @[dbg.scala 442:32]
-    node _T_669 = bits(_T_668, 0, 0) @[Bitwise.scala 72:15]
-    node _T_670 = mux(_T_669, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12]
-    node _T_671 = bits(io.sb_axi.r.bits.data, 63, 0) @[dbg.scala 442:70]
-    node _T_672 = bits(sbaddress0_reg, 2, 1) @[dbg.scala 442:102]
-    node _T_673 = mul(UInt<5>("h010"), _T_672) @[dbg.scala 442:86]
-    node _T_674 = dshr(_T_671, _T_673) @[dbg.scala 442:78]
-    node _T_675 = and(_T_674, UInt<64>("h0ffff")) @[dbg.scala 442:110]
-    node _T_676 = and(_T_670, _T_675) @[dbg.scala 442:45]
-    node _T_677 = or(_T_666, _T_676) @[dbg.scala 441:140]
-    node _T_678 = bits(sbcs_reg, 19, 17) @[dbg.scala 443:23]
-    node _T_679 = eq(_T_678, UInt<2>("h02")) @[dbg.scala 443:32]
-    node _T_680 = bits(_T_679, 0, 0) @[Bitwise.scala 72:15]
-    node _T_681 = mux(_T_680, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12]
-    node _T_682 = bits(io.sb_axi.r.bits.data, 63, 0) @[dbg.scala 443:70]
-    node _T_683 = bits(sbaddress0_reg, 2, 2) @[dbg.scala 443:102]
-    node _T_684 = mul(UInt<6>("h020"), _T_683) @[dbg.scala 443:86]
-    node _T_685 = dshr(_T_682, _T_684) @[dbg.scala 443:78]
-    node _T_686 = and(_T_685, UInt<64>("h0ffffffff")) @[dbg.scala 443:107]
-    node _T_687 = and(_T_681, _T_686) @[dbg.scala 443:45]
-    node _T_688 = or(_T_677, _T_687) @[dbg.scala 442:129]
-    node _T_689 = bits(sbcs_reg, 19, 17) @[dbg.scala 444:23]
-    node _T_690 = eq(_T_689, UInt<2>("h03")) @[dbg.scala 444:32]
-    node _T_691 = bits(_T_690, 0, 0) @[Bitwise.scala 72:15]
-    node _T_692 = mux(_T_691, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12]
-    node _T_693 = bits(io.sb_axi.r.bits.data, 63, 0) @[dbg.scala 444:68]
-    node _T_694 = and(_T_692, _T_693) @[dbg.scala 444:45]
-    node _T_695 = or(_T_688, _T_694) @[dbg.scala 443:131]
-    sb_bus_rdata <= _T_695 @[dbg.scala 441:16]
-    io.dbg_dma.dbg_ib.dbg_cmd_addr <= io.dbg_dec.dbg_ib.dbg_cmd_addr @[dbg.scala 447:39]
-    io.dbg_dma.dbg_dctl.dbg_cmd_wrdata <= io.dbg_dec.dbg_dctl.dbg_cmd_wrdata @[dbg.scala 448:39]
-    io.dbg_dma.dbg_ib.dbg_cmd_valid <= io.dbg_dec.dbg_ib.dbg_cmd_valid @[dbg.scala 449:39]
-    io.dbg_dma.dbg_ib.dbg_cmd_write <= io.dbg_dec.dbg_ib.dbg_cmd_write @[dbg.scala 450:39]
-    io.dbg_dma.dbg_ib.dbg_cmd_type <= io.dbg_dec.dbg_ib.dbg_cmd_type @[dbg.scala 451:39]
+    node _T_608 = mux(_T_607, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
+    node _T_609 = bits(sbaddress0_reg, 2, 0) @[dbg.scala 427:99]
+    node _T_610 = dshl(UInt<8>("h01"), _T_609) @[dbg.scala 427:82]
+    node _T_611 = and(_T_608, _T_610) @[dbg.scala 427:67]
+    node _T_612 = bits(sbcs_reg, 19, 17) @[dbg.scala 428:22]
+    node _T_613 = eq(_T_612, UInt<1>("h01")) @[dbg.scala 428:31]
+    node _T_614 = bits(_T_613, 0, 0) @[Bitwise.scala 72:15]
+    node _T_615 = mux(_T_614, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
+    node _T_616 = bits(sbaddress0_reg, 2, 1) @[dbg.scala 428:80]
+    node _T_617 = cat(_T_616, UInt<1>("h00")) @[Cat.scala 29:58]
+    node _T_618 = dshl(UInt<8>("h03"), _T_617) @[dbg.scala 428:59]
+    node _T_619 = and(_T_615, _T_618) @[dbg.scala 428:44]
+    node _T_620 = or(_T_611, _T_619) @[dbg.scala 427:107]
+    node _T_621 = bits(sbcs_reg, 19, 17) @[dbg.scala 429:22]
+    node _T_622 = eq(_T_621, UInt<2>("h02")) @[dbg.scala 429:31]
+    node _T_623 = bits(_T_622, 0, 0) @[Bitwise.scala 72:15]
+    node _T_624 = mux(_T_623, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
+    node _T_625 = bits(sbaddress0_reg, 2, 2) @[dbg.scala 429:80]
+    node _T_626 = cat(_T_625, UInt<2>("h00")) @[Cat.scala 29:58]
+    node _T_627 = dshl(UInt<8>("h0f"), _T_626) @[dbg.scala 429:59]
+    node _T_628 = and(_T_624, _T_627) @[dbg.scala 429:44]
+    node _T_629 = or(_T_620, _T_628) @[dbg.scala 428:97]
+    node _T_630 = bits(sbcs_reg, 19, 17) @[dbg.scala 430:22]
+    node _T_631 = eq(_T_630, UInt<2>("h03")) @[dbg.scala 430:31]
+    node _T_632 = bits(_T_631, 0, 0) @[Bitwise.scala 72:15]
+    node _T_633 = mux(_T_632, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
+    node _T_634 = and(_T_633, UInt<8>("h0ff")) @[dbg.scala 430:44]
+    node _T_635 = or(_T_629, _T_634) @[dbg.scala 429:100]
+    io.sb_axi.w.bits.strb <= _T_635 @[dbg.scala 427:25]
+    io.sb_axi.w.bits.last <= UInt<1>("h01") @[dbg.scala 432:25]
+    node _T_636 = eq(sb_state, UInt<4>("h03")) @[dbg.scala 433:35]
+    node _T_637 = bits(_T_636, 0, 0) @[dbg.scala 433:64]
+    io.sb_axi.ar.valid <= _T_637 @[dbg.scala 433:22]
+    io.sb_axi.ar.bits.addr <= sbaddress0_reg @[dbg.scala 434:26]
+    io.sb_axi.ar.bits.id <= UInt<1>("h00") @[dbg.scala 435:24]
+    node _T_638 = bits(sbcs_reg, 19, 17) @[dbg.scala 436:37]
+    io.sb_axi.ar.bits.size <= _T_638 @[dbg.scala 436:26]
+    io.sb_axi.ar.bits.prot <= UInt<1>("h00") @[dbg.scala 437:26]
+    io.sb_axi.ar.bits.cache <= UInt<1>("h00") @[dbg.scala 438:27]
+    node _T_639 = bits(sbaddress0_reg, 31, 28) @[dbg.scala 439:45]
+    io.sb_axi.ar.bits.region <= _T_639 @[dbg.scala 439:28]
+    io.sb_axi.ar.bits.len <= UInt<1>("h00") @[dbg.scala 440:25]
+    io.sb_axi.ar.bits.burst <= UInt<2>("h01") @[dbg.scala 441:27]
+    io.sb_axi.ar.bits.qos <= UInt<1>("h00") @[dbg.scala 442:25]
+    io.sb_axi.ar.bits.lock <= UInt<1>("h00") @[dbg.scala 443:26]
+    io.sb_axi.b.ready <= UInt<1>("h01") @[dbg.scala 444:21]
+    io.sb_axi.r.ready <= UInt<1>("h01") @[dbg.scala 445:21]
+    node _T_640 = bits(sbcs_reg, 19, 17) @[dbg.scala 446:37]
+    node _T_641 = eq(_T_640, UInt<1>("h00")) @[dbg.scala 446:46]
+    node _T_642 = bits(_T_641, 0, 0) @[Bitwise.scala 72:15]
+    node _T_643 = mux(_T_642, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12]
+    node _T_644 = bits(io.sb_axi.r.bits.data, 63, 0) @[dbg.scala 446:84]
+    node _T_645 = bits(sbaddress0_reg, 2, 0) @[dbg.scala 446:115]
+    node _T_646 = mul(UInt<4>("h08"), _T_645) @[dbg.scala 446:99]
+    node _T_647 = dshr(_T_644, _T_646) @[dbg.scala 446:92]
+    node _T_648 = and(_T_647, UInt<64>("h0ff")) @[dbg.scala 446:123]
+    node _T_649 = and(_T_643, _T_648) @[dbg.scala 446:59]
+    node _T_650 = bits(sbcs_reg, 19, 17) @[dbg.scala 447:23]
+    node _T_651 = eq(_T_650, UInt<1>("h01")) @[dbg.scala 447:32]
+    node _T_652 = bits(_T_651, 0, 0) @[Bitwise.scala 72:15]
+    node _T_653 = mux(_T_652, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12]
+    node _T_654 = bits(io.sb_axi.r.bits.data, 63, 0) @[dbg.scala 447:70]
+    node _T_655 = bits(sbaddress0_reg, 2, 1) @[dbg.scala 447:102]
+    node _T_656 = mul(UInt<5>("h010"), _T_655) @[dbg.scala 447:86]
+    node _T_657 = dshr(_T_654, _T_656) @[dbg.scala 447:78]
+    node _T_658 = and(_T_657, UInt<64>("h0ffff")) @[dbg.scala 447:110]
+    node _T_659 = and(_T_653, _T_658) @[dbg.scala 447:45]
+    node _T_660 = or(_T_649, _T_659) @[dbg.scala 446:140]
+    node _T_661 = bits(sbcs_reg, 19, 17) @[dbg.scala 448:23]
+    node _T_662 = eq(_T_661, UInt<2>("h02")) @[dbg.scala 448:32]
+    node _T_663 = bits(_T_662, 0, 0) @[Bitwise.scala 72:15]
+    node _T_664 = mux(_T_663, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12]
+    node _T_665 = bits(io.sb_axi.r.bits.data, 63, 0) @[dbg.scala 448:70]
+    node _T_666 = bits(sbaddress0_reg, 2, 2) @[dbg.scala 448:102]
+    node _T_667 = mul(UInt<6>("h020"), _T_666) @[dbg.scala 448:86]
+    node _T_668 = dshr(_T_665, _T_667) @[dbg.scala 448:78]
+    node _T_669 = and(_T_668, UInt<64>("h0ffffffff")) @[dbg.scala 448:107]
+    node _T_670 = and(_T_664, _T_669) @[dbg.scala 448:45]
+    node _T_671 = or(_T_660, _T_670) @[dbg.scala 447:129]
+    node _T_672 = bits(sbcs_reg, 19, 17) @[dbg.scala 449:23]
+    node _T_673 = eq(_T_672, UInt<2>("h03")) @[dbg.scala 449:32]
+    node _T_674 = bits(_T_673, 0, 0) @[Bitwise.scala 72:15]
+    node _T_675 = mux(_T_674, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12]
+    node _T_676 = bits(io.sb_axi.r.bits.data, 63, 0) @[dbg.scala 449:68]
+    node _T_677 = and(_T_675, _T_676) @[dbg.scala 449:45]
+    node _T_678 = or(_T_671, _T_677) @[dbg.scala 448:131]
+    sb_bus_rdata <= _T_678 @[dbg.scala 446:16]
+    io.dbg_dma.dbg_ib.dbg_cmd_addr <= io.dbg_dec.dbg_ib.dbg_cmd_addr @[dbg.scala 452:39]
+    io.dbg_dma.dbg_dctl.dbg_cmd_wrdata <= io.dbg_dec.dbg_dctl.dbg_cmd_wrdata @[dbg.scala 453:39]
+    io.dbg_dma.dbg_ib.dbg_cmd_valid <= io.dbg_dec.dbg_ib.dbg_cmd_valid @[dbg.scala 454:39]
+    io.dbg_dma.dbg_ib.dbg_cmd_write <= io.dbg_dec.dbg_ib.dbg_cmd_write @[dbg.scala 455:39]
+    io.dbg_dma.dbg_ib.dbg_cmd_type <= io.dbg_dec.dbg_ib.dbg_cmd_type @[dbg.scala 456:39]
     
diff --git a/dbg.v b/dbg.v
index bcfa40f7..82f45fbd 100644
--- a/dbg.v
+++ b/dbg.v
@@ -4,20 +4,20 @@ module rvclkhdr(
   input   io_en,
   input   io_scan_mode
 );
-  wire  clkhdr_Q; // @[lib.scala 318:26]
-  wire  clkhdr_CK; // @[lib.scala 318:26]
-  wire  clkhdr_EN; // @[lib.scala 318:26]
-  wire  clkhdr_SE; // @[lib.scala 318:26]
-  gated_latch clkhdr ( // @[lib.scala 318:26]
+  wire  clkhdr_Q; // @[lib.scala 334:26]
+  wire  clkhdr_CK; // @[lib.scala 334:26]
+  wire  clkhdr_EN; // @[lib.scala 334:26]
+  wire  clkhdr_SE; // @[lib.scala 334:26]
+  gated_latch clkhdr ( // @[lib.scala 334:26]
     .Q(clkhdr_Q),
     .CK(clkhdr_CK),
     .EN(clkhdr_EN),
     .SE(clkhdr_SE)
   );
-  assign io_l1clk = clkhdr_Q; // @[lib.scala 319:14]
-  assign clkhdr_CK = io_clk; // @[lib.scala 320:18]
-  assign clkhdr_EN = io_en; // @[lib.scala 321:18]
-  assign clkhdr_SE = io_scan_mode; // @[lib.scala 322:18]
+  assign io_l1clk = clkhdr_Q; // @[lib.scala 335:14]
+  assign clkhdr_CK = io_clk; // @[lib.scala 336:18]
+  assign clkhdr_EN = io_en; // @[lib.scala 337:18]
+  assign clkhdr_SE = io_scan_mode; // @[lib.scala 338:18]
 endmodule
 module dbg(
   input         clock,
@@ -151,609 +151,609 @@ module dbg(
   wire  _T_4 = io_dmi_reg_en | sb_state_en; // @[dbg.scala 96:37]
   wire  _T_5 = sb_state != 4'h0; // @[dbg.scala 96:63]
   wire  _T_6 = _T_4 | _T_5; // @[dbg.scala 96:51]
-  wire  rvclkhdr_io_l1clk; // @[lib.scala 327:22]
-  wire  rvclkhdr_io_clk; // @[lib.scala 327:22]
-  wire  rvclkhdr_io_en; // @[lib.scala 327:22]
-  wire  rvclkhdr_io_scan_mode; // @[lib.scala 327:22]
-  wire  rvclkhdr_1_io_l1clk; // @[lib.scala 327:22]
-  wire  rvclkhdr_1_io_clk; // @[lib.scala 327:22]
-  wire  rvclkhdr_1_io_en; // @[lib.scala 327:22]
-  wire  rvclkhdr_1_io_scan_mode; // @[lib.scala 327:22]
-  wire  _T_9 = dmcontrol_reg[0] | io_scan_mode; // @[dbg.scala 99:64]
-  wire  dbg_dm_rst_l = io_dbg_rst_l & _T_9; // @[dbg.scala 99:44]
-  wire  _T_11 = ~dmcontrol_reg[1]; // @[dbg.scala 100:25]
-  wire  _T_13 = io_dmi_reg_addr == 7'h38; // @[dbg.scala 101:36]
-  wire  _T_14 = _T_13 & io_dmi_reg_en; // @[dbg.scala 101:49]
-  wire  _T_15 = _T_14 & io_dmi_reg_wr_en; // @[dbg.scala 101:65]
-  wire  _T_16 = sb_state == 4'h0; // @[dbg.scala 101:96]
-  wire  sbcs_wren = _T_15 & _T_16; // @[dbg.scala 101:84]
-  wire  _T_18 = sbcs_wren & io_dmi_reg_wdata[22]; // @[dbg.scala 102:42]
-  wire  _T_20 = _T_5 & io_dmi_reg_en; // @[dbg.scala 102:102]
-  wire  _T_21 = io_dmi_reg_addr == 7'h39; // @[dbg.scala 103:23]
-  wire  _T_22 = io_dmi_reg_addr == 7'h3c; // @[dbg.scala 103:55]
-  wire  _T_23 = _T_21 | _T_22; // @[dbg.scala 103:36]
-  wire  _T_24 = io_dmi_reg_addr == 7'h3d; // @[dbg.scala 103:87]
-  wire  _T_25 = _T_23 | _T_24; // @[dbg.scala 103:68]
-  wire  _T_26 = _T_20 & _T_25; // @[dbg.scala 102:118]
-  wire  sbcs_sbbusyerror_wren = _T_18 | _T_26; // @[dbg.scala 102:66]
-  wire  sbcs_sbbusyerror_din = ~_T_18; // @[dbg.scala 105:31]
-  wire  _T_29 = io_dbg_rst_l & _T_9; // @[dbg.scala 106:80]
+  wire  rvclkhdr_io_l1clk; // @[lib.scala 343:22]
+  wire  rvclkhdr_io_clk; // @[lib.scala 343:22]
+  wire  rvclkhdr_io_en; // @[lib.scala 343:22]
+  wire  rvclkhdr_io_scan_mode; // @[lib.scala 343:22]
+  wire  rvclkhdr_1_io_l1clk; // @[lib.scala 343:22]
+  wire  rvclkhdr_1_io_clk; // @[lib.scala 343:22]
+  wire  rvclkhdr_1_io_en; // @[lib.scala 343:22]
+  wire  rvclkhdr_1_io_scan_mode; // @[lib.scala 343:22]
+  wire  _T_9 = dmcontrol_reg[0] | io_scan_mode; // @[dbg.scala 99:65]
+  wire  dbg_dm_rst_l = io_dbg_rst_l & _T_9; // @[dbg.scala 99:94]
+  wire  _T_11 = io_dbg_rst_l & _T_9; // @[dbg.scala 101:38]
+  wire  rst_temp = _T_11 & reset; // @[dbg.scala 101:71]
+  wire  rst_not = ~_T_11; // @[dbg.scala 103:52]
+  wire  _T_17 = ~dmcontrol_reg[1]; // @[dbg.scala 105:25]
+  wire  _T_19 = io_dmi_reg_addr == 7'h38; // @[dbg.scala 106:36]
+  wire  _T_20 = _T_19 & io_dmi_reg_en; // @[dbg.scala 106:49]
+  wire  _T_21 = _T_20 & io_dmi_reg_wr_en; // @[dbg.scala 106:65]
+  wire  _T_22 = sb_state == 4'h0; // @[dbg.scala 106:96]
+  wire  sbcs_wren = _T_21 & _T_22; // @[dbg.scala 106:84]
+  wire  _T_24 = sbcs_wren & io_dmi_reg_wdata[22]; // @[dbg.scala 107:42]
+  wire  _T_26 = _T_5 & io_dmi_reg_en; // @[dbg.scala 107:102]
+  wire  _T_27 = io_dmi_reg_addr == 7'h39; // @[dbg.scala 108:23]
+  wire  _T_28 = io_dmi_reg_addr == 7'h3c; // @[dbg.scala 108:55]
+  wire  _T_29 = _T_27 | _T_28; // @[dbg.scala 108:36]
+  wire  _T_30 = io_dmi_reg_addr == 7'h3d; // @[dbg.scala 108:87]
+  wire  _T_31 = _T_29 | _T_30; // @[dbg.scala 108:68]
+  wire  _T_32 = _T_26 & _T_31; // @[dbg.scala 107:118]
+  wire  sbcs_sbbusyerror_wren = _T_24 | _T_32; // @[dbg.scala 107:66]
+  wire  sbcs_sbbusyerror_din = ~_T_24; // @[dbg.scala 110:31]
   reg  temp_sbcs_22; // @[Reg.scala 27:20]
   reg  temp_sbcs_21; // @[Reg.scala 27:20]
   reg  temp_sbcs_20; // @[Reg.scala 27:20]
   reg [4:0] temp_sbcs_19_15; // @[Reg.scala 27:20]
-  wire  _T_36 = ~dbg_dm_rst_l; // @[dbg.scala 122:84]
   reg [2:0] temp_sbcs_14_12; // @[Reg.scala 27:20]
   wire [19:0] _T_40 = {temp_sbcs_19_15,temp_sbcs_14_12,12'h40f}; // @[Cat.scala 29:58]
   wire [11:0] _T_44 = {9'h40,temp_sbcs_22,temp_sbcs_21,temp_sbcs_20}; // @[Cat.scala 29:58]
-  wire  _T_47 = sbcs_reg[19:17] == 3'h1; // @[dbg.scala 127:42]
-  wire  _T_49 = _T_47 & sbaddress0_reg[0]; // @[dbg.scala 127:61]
-  wire  _T_51 = sbcs_reg[19:17] == 3'h2; // @[dbg.scala 128:23]
-  wire  _T_53 = |sbaddress0_reg[1:0]; // @[dbg.scala 128:65]
-  wire  _T_54 = _T_51 & _T_53; // @[dbg.scala 128:42]
-  wire  _T_55 = _T_49 | _T_54; // @[dbg.scala 127:81]
-  wire  _T_57 = sbcs_reg[19:17] == 3'h3; // @[dbg.scala 129:23]
-  wire  _T_59 = |sbaddress0_reg[2:0]; // @[dbg.scala 129:65]
-  wire  _T_60 = _T_57 & _T_59; // @[dbg.scala 129:42]
-  wire  sbcs_unaligned = _T_55 | _T_60; // @[dbg.scala 128:69]
-  wire  sbcs_illegal_size = sbcs_reg[19]; // @[dbg.scala 131:35]
-  wire  _T_62 = sbcs_reg[19:17] == 3'h0; // @[dbg.scala 132:51]
+  wire  _T_47 = sbcs_reg[19:17] == 3'h1; // @[dbg.scala 132:42]
+  wire  _T_49 = _T_47 & sbaddress0_reg[0]; // @[dbg.scala 132:61]
+  wire  _T_51 = sbcs_reg[19:17] == 3'h2; // @[dbg.scala 133:23]
+  wire  _T_53 = |sbaddress0_reg[1:0]; // @[dbg.scala 133:65]
+  wire  _T_54 = _T_51 & _T_53; // @[dbg.scala 133:42]
+  wire  _T_55 = _T_49 | _T_54; // @[dbg.scala 132:81]
+  wire  _T_57 = sbcs_reg[19:17] == 3'h3; // @[dbg.scala 134:23]
+  wire  _T_59 = |sbaddress0_reg[2:0]; // @[dbg.scala 134:65]
+  wire  _T_60 = _T_57 & _T_59; // @[dbg.scala 134:42]
+  wire  sbcs_unaligned = _T_55 | _T_60; // @[dbg.scala 133:69]
+  wire  sbcs_illegal_size = sbcs_reg[19]; // @[dbg.scala 136:35]
+  wire  _T_62 = sbcs_reg[19:17] == 3'h0; // @[dbg.scala 137:51]
   wire [3:0] _T_64 = _T_62 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
-  wire [3:0] _T_65 = _T_64 & 4'h1; // @[dbg.scala 132:64]
+  wire [3:0] _T_65 = _T_64 & 4'h1; // @[dbg.scala 137:64]
   wire [3:0] _T_69 = _T_47 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
-  wire [3:0] _T_70 = _T_69 & 4'h2; // @[dbg.scala 132:122]
-  wire [3:0] _T_71 = _T_65 | _T_70; // @[dbg.scala 132:81]
+  wire [3:0] _T_70 = _T_69 & 4'h2; // @[dbg.scala 137:122]
+  wire [3:0] _T_71 = _T_65 | _T_70; // @[dbg.scala 137:81]
   wire [3:0] _T_75 = _T_51 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
-  wire [3:0] _T_76 = _T_75 & 4'h4; // @[dbg.scala 133:44]
-  wire [3:0] _T_77 = _T_71 | _T_76; // @[dbg.scala 132:139]
+  wire [3:0] _T_76 = _T_75 & 4'h4; // @[dbg.scala 138:44]
+  wire [3:0] _T_77 = _T_71 | _T_76; // @[dbg.scala 137:139]
   wire [3:0] _T_81 = _T_57 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
-  wire [3:0] _T_82 = _T_81 & 4'h8; // @[dbg.scala 133:102]
-  wire [3:0] sbaddress0_incr = _T_77 | _T_82; // @[dbg.scala 133:61]
-  wire  _T_83 = io_dmi_reg_en & io_dmi_reg_wr_en; // @[dbg.scala 135:41]
-  wire  sbdata0_reg_wren0 = _T_83 & _T_22; // @[dbg.scala 135:60]
-  wire  _T_85 = sb_state == 4'h7; // @[dbg.scala 136:37]
-  wire  _T_86 = _T_85 & sb_state_en; // @[dbg.scala 136:60]
-  wire  _T_87 = ~sbcs_sberror_wren; // @[dbg.scala 136:76]
-  wire  sbdata0_reg_wren1 = _T_86 & _T_87; // @[dbg.scala 136:74]
-  wire  sbdata1_reg_wren0 = _T_83 & _T_24; // @[dbg.scala 138:60]
+  wire [3:0] _T_82 = _T_81 & 4'h8; // @[dbg.scala 138:102]
+  wire [3:0] sbaddress0_incr = _T_77 | _T_82; // @[dbg.scala 138:61]
+  wire  _T_83 = io_dmi_reg_en & io_dmi_reg_wr_en; // @[dbg.scala 140:41]
+  wire  sbdata0_reg_wren0 = _T_83 & _T_28; // @[dbg.scala 140:60]
+  wire  _T_85 = sb_state == 4'h7; // @[dbg.scala 141:37]
+  wire  _T_86 = _T_85 & sb_state_en; // @[dbg.scala 141:60]
+  wire  _T_87 = ~sbcs_sberror_wren; // @[dbg.scala 141:76]
+  wire  sbdata0_reg_wren1 = _T_86 & _T_87; // @[dbg.scala 141:74]
+  wire  sbdata1_reg_wren0 = _T_83 & _T_30; // @[dbg.scala 143:60]
   wire [31:0] _T_94 = sbdata0_reg_wren0 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
-  wire [31:0] _T_95 = _T_94 & io_dmi_reg_wdata; // @[dbg.scala 141:49]
+  wire [31:0] _T_95 = _T_94 & io_dmi_reg_wdata; // @[dbg.scala 146:49]
   wire [31:0] _T_97 = sbdata0_reg_wren1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
-  wire [31:0] _T_99 = _T_97 & sb_bus_rdata[31:0]; // @[dbg.scala 142:33]
+  wire [31:0] _T_99 = _T_97 & sb_bus_rdata[31:0]; // @[dbg.scala 147:33]
   wire [31:0] _T_101 = sbdata1_reg_wren0 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
-  wire [31:0] _T_102 = _T_101 & io_dmi_reg_wdata; // @[dbg.scala 144:49]
-  wire [31:0] _T_106 = _T_97 & sb_bus_rdata[63:32]; // @[dbg.scala 145:33]
-  wire  rvclkhdr_2_io_l1clk; // @[lib.scala 352:23]
-  wire  rvclkhdr_2_io_clk; // @[lib.scala 352:23]
-  wire  rvclkhdr_2_io_en; // @[lib.scala 352:23]
-  wire  rvclkhdr_2_io_scan_mode; // @[lib.scala 352:23]
-  reg [31:0] sbdata0_reg; // @[lib.scala 358:16]
-  wire  rvclkhdr_3_io_l1clk; // @[lib.scala 352:23]
-  wire  rvclkhdr_3_io_clk; // @[lib.scala 352:23]
-  wire  rvclkhdr_3_io_en; // @[lib.scala 352:23]
-  wire  rvclkhdr_3_io_scan_mode; // @[lib.scala 352:23]
-  reg [31:0] sbdata1_reg; // @[lib.scala 358:16]
-  wire  sbaddress0_reg_wren0 = _T_83 & _T_21; // @[dbg.scala 155:63]
-  wire [31:0] _T_112 = sbaddress0_reg_wren0 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
-  wire [31:0] _T_113 = _T_112 & io_dmi_reg_wdata; // @[dbg.scala 157:59]
-  wire [31:0] _T_115 = sbaddress0_reg_wren1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
-  wire [31:0] _T_116 = {28'h0,sbaddress0_incr}; // @[Cat.scala 29:58]
-  wire [31:0] _T_118 = sbaddress0_reg + _T_116; // @[dbg.scala 158:54]
-  wire [31:0] _T_119 = _T_115 & _T_118; // @[dbg.scala 158:36]
-  wire  rvclkhdr_4_io_l1clk; // @[lib.scala 352:23]
-  wire  rvclkhdr_4_io_clk; // @[lib.scala 352:23]
-  wire  rvclkhdr_4_io_en; // @[lib.scala 352:23]
-  wire  rvclkhdr_4_io_scan_mode; // @[lib.scala 352:23]
-  reg [31:0] _T_121; // @[lib.scala 358:16]
-  wire  sbreadonaddr_access = sbaddress0_reg_wren0 & sbcs_reg[20]; // @[dbg.scala 163:94]
-  wire  _T_126 = ~io_dmi_reg_wr_en; // @[dbg.scala 164:45]
-  wire  _T_127 = io_dmi_reg_en & _T_126; // @[dbg.scala 164:43]
-  wire  _T_129 = _T_127 & _T_22; // @[dbg.scala 164:63]
-  wire  sbreadondata_access = _T_129 & sbcs_reg[15]; // @[dbg.scala 164:95]
-  wire  _T_133 = io_dmi_reg_addr == 7'h10; // @[dbg.scala 166:41]
-  wire  _T_134 = _T_133 & io_dmi_reg_en; // @[dbg.scala 166:54]
-  wire  dmcontrol_wren = _T_134 & io_dmi_reg_wr_en; // @[dbg.scala 166:70]
-  wire [3:0] _T_140 = {io_dmi_reg_wdata[31:30],io_dmi_reg_wdata[28],io_dmi_reg_wdata[1]}; // @[Cat.scala 29:58]
+  wire [31:0] _T_102 = _T_101 & io_dmi_reg_wdata; // @[dbg.scala 149:49]
+  wire [31:0] _T_106 = _T_97 & sb_bus_rdata[63:32]; // @[dbg.scala 150:33]
+  wire  rvclkhdr_2_io_l1clk; // @[lib.scala 368:23]
+  wire  rvclkhdr_2_io_clk; // @[lib.scala 368:23]
+  wire  rvclkhdr_2_io_en; // @[lib.scala 368:23]
+  wire  rvclkhdr_2_io_scan_mode; // @[lib.scala 368:23]
+  reg [31:0] sbdata0_reg; // @[lib.scala 374:16]
+  wire  rvclkhdr_3_io_l1clk; // @[lib.scala 368:23]
+  wire  rvclkhdr_3_io_clk; // @[lib.scala 368:23]
+  wire  rvclkhdr_3_io_en; // @[lib.scala 368:23]
+  wire  rvclkhdr_3_io_scan_mode; // @[lib.scala 368:23]
+  reg [31:0] sbdata1_reg; // @[lib.scala 374:16]
+  wire  sbaddress0_reg_wren0 = _T_83 & _T_27; // @[dbg.scala 160:63]
+  wire [31:0] _T_110 = sbaddress0_reg_wren0 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
+  wire [31:0] _T_111 = _T_110 & io_dmi_reg_wdata; // @[dbg.scala 162:59]
+  wire [31:0] _T_113 = sbaddress0_reg_wren1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
+  wire [31:0] _T_114 = {28'h0,sbaddress0_incr}; // @[Cat.scala 29:58]
+  wire [31:0] _T_116 = sbaddress0_reg + _T_114; // @[dbg.scala 163:54]
+  wire [31:0] _T_117 = _T_113 & _T_116; // @[dbg.scala 163:36]
+  wire  rvclkhdr_4_io_l1clk; // @[lib.scala 368:23]
+  wire  rvclkhdr_4_io_clk; // @[lib.scala 368:23]
+  wire  rvclkhdr_4_io_en; // @[lib.scala 368:23]
+  wire  rvclkhdr_4_io_scan_mode; // @[lib.scala 368:23]
+  reg [31:0] _T_118; // @[lib.scala 374:16]
+  wire  sbreadonaddr_access = sbaddress0_reg_wren0 & sbcs_reg[20]; // @[dbg.scala 168:94]
+  wire  _T_123 = ~io_dmi_reg_wr_en; // @[dbg.scala 169:45]
+  wire  _T_124 = io_dmi_reg_en & _T_123; // @[dbg.scala 169:43]
+  wire  _T_126 = _T_124 & _T_28; // @[dbg.scala 169:63]
+  wire  sbreadondata_access = _T_126 & sbcs_reg[15]; // @[dbg.scala 169:95]
+  wire  _T_130 = io_dmi_reg_addr == 7'h10; // @[dbg.scala 171:41]
+  wire  _T_131 = _T_130 & io_dmi_reg_en; // @[dbg.scala 171:54]
+  wire  dmcontrol_wren = _T_131 & io_dmi_reg_wr_en; // @[dbg.scala 171:70]
+  wire [3:0] _T_136 = {io_dmi_reg_wdata[31:30],io_dmi_reg_wdata[28],io_dmi_reg_wdata[1]}; // @[Cat.scala 29:58]
   reg [3:0] dm_temp; // @[Reg.scala 27:20]
   reg  dm_temp_0; // @[Reg.scala 27:20]
-  wire [27:0] _T_147 = {26'h0,dm_temp[0],dm_temp_0}; // @[Cat.scala 29:58]
-  wire [3:0] _T_149 = {dm_temp[3:2],1'h0,dm_temp[1]}; // @[Cat.scala 29:58]
-  reg  dmcontrol_wren_Q; // @[dbg.scala 181:12]
-  wire [1:0] _T_152 = dmstatus_havereset ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
-  wire [1:0] _T_154 = dmstatus_resumeack ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
-  wire [1:0] _T_156 = dmstatus_unavail ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
-  wire [1:0] _T_158 = dmstatus_running ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
-  wire [1:0] _T_160 = dmstatus_halted ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
-  wire [11:0] _T_164 = {_T_158,_T_160,1'h1,7'h2}; // @[Cat.scala 29:58]
-  wire [19:0] _T_168 = {12'h0,_T_152,_T_154,2'h0,_T_156}; // @[Cat.scala 29:58]
-  wire  _T_170 = dbg_state == 3'h6; // @[dbg.scala 186:44]
-  wire  _T_171 = _T_170 & io_dec_tlu_resume_ack; // @[dbg.scala 186:66]
-  wire  _T_173 = ~dmcontrol_reg[30]; // @[dbg.scala 186:113]
-  wire  _T_174 = dmstatus_resumeack & _T_173; // @[dbg.scala 186:111]
-  wire  dmstatus_resumeack_wren = _T_171 | _T_174; // @[dbg.scala 186:90]
-  wire  _T_178 = _T_133 & io_dmi_reg_wdata[1]; // @[dbg.scala 188:63]
-  wire  _T_179 = _T_178 & io_dmi_reg_en; // @[dbg.scala 188:85]
-  wire  dmstatus_havereset_wren = _T_179 & io_dmi_reg_wr_en; // @[dbg.scala 188:101]
-  wire  _T_182 = _T_133 & io_dmi_reg_wdata[28]; // @[dbg.scala 189:62]
-  wire  _T_183 = _T_182 & io_dmi_reg_en; // @[dbg.scala 189:85]
-  wire  dmstatus_havereset_rst = _T_183 & io_dmi_reg_wr_en; // @[dbg.scala 189:101]
-  wire  _T_185 = ~reset; // @[dbg.scala 191:43]
-  wire  _T_188 = dmstatus_unavail | dmstatus_halted; // @[dbg.scala 192:42]
-  reg  _T_191; // @[Reg.scala 27:20]
-  wire  _T_193 = ~io_dec_tlu_mpc_halted_only; // @[dbg.scala 198:37]
-  reg  _T_195; // @[dbg.scala 198:12]
-  wire  _T_197 = dmstatus_havereset_wren | dmstatus_havereset; // @[dbg.scala 202:16]
-  wire  _T_198 = ~dmstatus_havereset_rst; // @[dbg.scala 202:72]
-  reg  _T_200; // @[dbg.scala 202:12]
+  wire [27:0] _T_143 = {26'h0,dm_temp[0],dm_temp_0}; // @[Cat.scala 29:58]
+  wire [3:0] _T_145 = {dm_temp[3:2],1'h0,dm_temp[1]}; // @[Cat.scala 29:58]
+  reg  dmcontrol_wren_Q; // @[dbg.scala 186:12]
+  wire [1:0] _T_147 = dmstatus_havereset ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
+  wire [1:0] _T_149 = dmstatus_resumeack ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
+  wire [1:0] _T_151 = dmstatus_unavail ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
+  wire [1:0] _T_153 = dmstatus_running ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
+  wire [1:0] _T_155 = dmstatus_halted ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
+  wire [11:0] _T_159 = {_T_153,_T_155,1'h1,7'h2}; // @[Cat.scala 29:58]
+  wire [19:0] _T_163 = {12'h0,_T_147,_T_149,2'h0,_T_151}; // @[Cat.scala 29:58]
+  wire  _T_165 = dbg_state == 3'h6; // @[dbg.scala 191:44]
+  wire  _T_166 = _T_165 & io_dec_tlu_resume_ack; // @[dbg.scala 191:66]
+  wire  _T_168 = ~dmcontrol_reg[30]; // @[dbg.scala 191:113]
+  wire  _T_169 = dmstatus_resumeack & _T_168; // @[dbg.scala 191:111]
+  wire  dmstatus_resumeack_wren = _T_166 | _T_169; // @[dbg.scala 191:90]
+  wire  _T_173 = _T_130 & io_dmi_reg_wdata[1]; // @[dbg.scala 193:63]
+  wire  _T_174 = _T_173 & io_dmi_reg_en; // @[dbg.scala 193:85]
+  wire  dmstatus_havereset_wren = _T_174 & io_dmi_reg_wr_en; // @[dbg.scala 193:101]
+  wire  _T_177 = _T_130 & io_dmi_reg_wdata[28]; // @[dbg.scala 194:62]
+  wire  _T_178 = _T_177 & io_dmi_reg_en; // @[dbg.scala 194:85]
+  wire  dmstatus_havereset_rst = _T_178 & io_dmi_reg_wr_en; // @[dbg.scala 194:101]
+  wire  _T_180 = ~reset; // @[dbg.scala 196:43]
+  wire  _T_183 = dmstatus_unavail | dmstatus_halted; // @[dbg.scala 197:42]
+  reg  _T_185; // @[Reg.scala 27:20]
+  wire  _T_186 = ~io_dec_tlu_mpc_halted_only; // @[dbg.scala 203:37]
+  reg  _T_188; // @[dbg.scala 203:12]
+  wire  _T_189 = dmstatus_havereset_wren | dmstatus_havereset; // @[dbg.scala 207:16]
+  wire  _T_190 = ~dmstatus_havereset_rst; // @[dbg.scala 207:72]
+  reg  _T_192; // @[dbg.scala 207:12]
   wire [31:0] haltsum0_reg = {31'h0,dmstatus_halted}; // @[Cat.scala 29:58]
   wire [31:0] abstractcs_reg;
-  wire  _T_202 = abstractcs_reg[12] & io_dmi_reg_en; // @[dbg.scala 208:50]
-  wire  _T_203 = io_dmi_reg_addr == 7'h16; // @[dbg.scala 208:106]
-  wire  _T_204 = io_dmi_reg_addr == 7'h17; // @[dbg.scala 208:138]
-  wire  _T_205 = _T_203 | _T_204; // @[dbg.scala 208:119]
-  wire  _T_206 = io_dmi_reg_wr_en & _T_205; // @[dbg.scala 208:86]
-  wire  _T_207 = io_dmi_reg_addr == 7'h4; // @[dbg.scala 208:171]
-  wire  _T_208 = _T_206 | _T_207; // @[dbg.scala 208:152]
-  wire  abstractcs_error_sel0 = _T_202 & _T_208; // @[dbg.scala 208:66]
-  wire  _T_211 = _T_83 & _T_204; // @[dbg.scala 209:64]
-  wire  _T_213 = io_dmi_reg_wdata[31:24] == 8'h0; // @[dbg.scala 209:126]
-  wire  _T_215 = io_dmi_reg_wdata[31:24] == 8'h2; // @[dbg.scala 209:163]
-  wire  _T_216 = _T_213 | _T_215; // @[dbg.scala 209:135]
-  wire  _T_217 = ~_T_216; // @[dbg.scala 209:98]
-  wire  abstractcs_error_sel1 = _T_211 & _T_217; // @[dbg.scala 209:96]
-  wire  abstractcs_error_sel2 = io_core_dbg_cmd_done & io_core_dbg_cmd_fail; // @[dbg.scala 210:52]
-  wire  _T_222 = ~dmstatus_reg[9]; // @[dbg.scala 211:98]
-  wire  abstractcs_error_sel3 = _T_211 & _T_222; // @[dbg.scala 211:96]
-  wire  _T_224 = _T_204 & io_dmi_reg_en; // @[dbg.scala 212:61]
-  wire  _T_225 = _T_224 & io_dmi_reg_wr_en; // @[dbg.scala 212:77]
-  wire  _T_227 = io_dmi_reg_wdata[22:20] != 3'h2; // @[dbg.scala 213:32]
-  wire  _T_231 = |data1_reg[1:0]; // @[dbg.scala 213:111]
-  wire  _T_232 = _T_215 & _T_231; // @[dbg.scala 213:92]
-  wire  _T_233 = _T_227 | _T_232; // @[dbg.scala 213:51]
-  wire  abstractcs_error_sel4 = _T_225 & _T_233; // @[dbg.scala 212:96]
-  wire  _T_235 = _T_203 & io_dmi_reg_en; // @[dbg.scala 215:61]
-  wire  abstractcs_error_sel5 = _T_235 & io_dmi_reg_wr_en; // @[dbg.scala 215:77]
-  wire  _T_236 = abstractcs_error_sel0 | abstractcs_error_sel1; // @[dbg.scala 216:54]
-  wire  _T_237 = _T_236 | abstractcs_error_sel2; // @[dbg.scala 216:78]
-  wire  _T_238 = _T_237 | abstractcs_error_sel3; // @[dbg.scala 216:102]
-  wire  _T_239 = _T_238 | abstractcs_error_sel4; // @[dbg.scala 216:126]
-  wire  abstractcs_error_selor = _T_239 | abstractcs_error_sel5; // @[dbg.scala 216:150]
-  wire [2:0] _T_241 = abstractcs_error_sel0 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
-  wire [2:0] _T_242 = _T_241 & 3'h1; // @[dbg.scala 217:62]
-  wire [2:0] _T_244 = abstractcs_error_sel1 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
-  wire [2:0] _T_245 = _T_244 & 3'h2; // @[dbg.scala 218:37]
-  wire [2:0] _T_246 = _T_242 | _T_245; // @[dbg.scala 217:79]
-  wire [2:0] _T_248 = abstractcs_error_sel2 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
-  wire [2:0] _T_249 = _T_248 & 3'h3; // @[dbg.scala 219:37]
-  wire [2:0] _T_250 = _T_246 | _T_249; // @[dbg.scala 218:54]
-  wire [2:0] _T_252 = abstractcs_error_sel3 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
-  wire [2:0] _T_253 = _T_252 & 3'h4; // @[dbg.scala 220:37]
-  wire [2:0] _T_254 = _T_250 | _T_253; // @[dbg.scala 219:54]
-  wire [2:0] _T_256 = abstractcs_error_sel4 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
-  wire [2:0] _T_258 = _T_254 | _T_256; // @[dbg.scala 220:54]
-  wire [2:0] _T_260 = abstractcs_error_sel5 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
-  wire [2:0] _T_262 = ~io_dmi_reg_wdata[10:8]; // @[dbg.scala 222:40]
-  wire [2:0] _T_263 = _T_260 & _T_262; // @[dbg.scala 222:37]
-  wire [2:0] _T_265 = _T_263 & abstractcs_reg[10:8]; // @[dbg.scala 222:75]
-  wire [2:0] _T_266 = _T_258 | _T_265; // @[dbg.scala 221:54]
-  wire  _T_267 = ~abstractcs_error_selor; // @[dbg.scala 223:15]
-  wire [2:0] _T_269 = _T_267 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
-  wire [2:0] _T_271 = _T_269 & abstractcs_reg[10:8]; // @[dbg.scala 223:50]
+  wire  _T_194 = abstractcs_reg[12] & io_dmi_reg_en; // @[dbg.scala 213:50]
+  wire  _T_195 = io_dmi_reg_addr == 7'h16; // @[dbg.scala 213:106]
+  wire  _T_196 = io_dmi_reg_addr == 7'h17; // @[dbg.scala 213:138]
+  wire  _T_197 = _T_195 | _T_196; // @[dbg.scala 213:119]
+  wire  _T_198 = io_dmi_reg_wr_en & _T_197; // @[dbg.scala 213:86]
+  wire  _T_199 = io_dmi_reg_addr == 7'h4; // @[dbg.scala 213:171]
+  wire  _T_200 = _T_198 | _T_199; // @[dbg.scala 213:152]
+  wire  abstractcs_error_sel0 = _T_194 & _T_200; // @[dbg.scala 213:66]
+  wire  _T_203 = _T_83 & _T_196; // @[dbg.scala 214:64]
+  wire  _T_205 = io_dmi_reg_wdata[31:24] == 8'h0; // @[dbg.scala 214:126]
+  wire  _T_207 = io_dmi_reg_wdata[31:24] == 8'h2; // @[dbg.scala 214:163]
+  wire  _T_208 = _T_205 | _T_207; // @[dbg.scala 214:135]
+  wire  _T_209 = ~_T_208; // @[dbg.scala 214:98]
+  wire  abstractcs_error_sel1 = _T_203 & _T_209; // @[dbg.scala 214:96]
+  wire  abstractcs_error_sel2 = io_core_dbg_cmd_done & io_core_dbg_cmd_fail; // @[dbg.scala 215:52]
+  wire  _T_214 = ~dmstatus_reg[9]; // @[dbg.scala 216:98]
+  wire  abstractcs_error_sel3 = _T_203 & _T_214; // @[dbg.scala 216:96]
+  wire  _T_216 = _T_196 & io_dmi_reg_en; // @[dbg.scala 217:61]
+  wire  _T_217 = _T_216 & io_dmi_reg_wr_en; // @[dbg.scala 217:77]
+  wire  _T_219 = io_dmi_reg_wdata[22:20] != 3'h2; // @[dbg.scala 218:32]
+  wire  _T_223 = |data1_reg[1:0]; // @[dbg.scala 218:111]
+  wire  _T_224 = _T_207 & _T_223; // @[dbg.scala 218:92]
+  wire  _T_225 = _T_219 | _T_224; // @[dbg.scala 218:51]
+  wire  abstractcs_error_sel4 = _T_217 & _T_225; // @[dbg.scala 217:96]
+  wire  _T_227 = _T_195 & io_dmi_reg_en; // @[dbg.scala 220:61]
+  wire  abstractcs_error_sel5 = _T_227 & io_dmi_reg_wr_en; // @[dbg.scala 220:77]
+  wire  _T_228 = abstractcs_error_sel0 | abstractcs_error_sel1; // @[dbg.scala 221:54]
+  wire  _T_229 = _T_228 | abstractcs_error_sel2; // @[dbg.scala 221:78]
+  wire  _T_230 = _T_229 | abstractcs_error_sel3; // @[dbg.scala 221:102]
+  wire  _T_231 = _T_230 | abstractcs_error_sel4; // @[dbg.scala 221:126]
+  wire  abstractcs_error_selor = _T_231 | abstractcs_error_sel5; // @[dbg.scala 221:150]
+  wire [2:0] _T_233 = abstractcs_error_sel0 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
+  wire [2:0] _T_234 = _T_233 & 3'h1; // @[dbg.scala 222:62]
+  wire [2:0] _T_236 = abstractcs_error_sel1 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
+  wire [2:0] _T_237 = _T_236 & 3'h2; // @[dbg.scala 223:37]
+  wire [2:0] _T_238 = _T_234 | _T_237; // @[dbg.scala 222:79]
+  wire [2:0] _T_240 = abstractcs_error_sel2 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
+  wire [2:0] _T_241 = _T_240 & 3'h3; // @[dbg.scala 224:37]
+  wire [2:0] _T_242 = _T_238 | _T_241; // @[dbg.scala 223:54]
+  wire [2:0] _T_244 = abstractcs_error_sel3 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
+  wire [2:0] _T_245 = _T_244 & 3'h4; // @[dbg.scala 225:37]
+  wire [2:0] _T_246 = _T_242 | _T_245; // @[dbg.scala 224:54]
+  wire [2:0] _T_248 = abstractcs_error_sel4 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
+  wire [2:0] _T_250 = _T_246 | _T_248; // @[dbg.scala 225:54]
+  wire [2:0] _T_252 = abstractcs_error_sel5 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
+  wire [2:0] _T_254 = ~io_dmi_reg_wdata[10:8]; // @[dbg.scala 227:40]
+  wire [2:0] _T_255 = _T_252 & _T_254; // @[dbg.scala 227:37]
+  wire [2:0] _T_257 = _T_255 & abstractcs_reg[10:8]; // @[dbg.scala 227:75]
+  wire [2:0] _T_258 = _T_250 | _T_257; // @[dbg.scala 226:54]
+  wire  _T_259 = ~abstractcs_error_selor; // @[dbg.scala 228:15]
+  wire [2:0] _T_261 = _T_259 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
+  wire [2:0] _T_263 = _T_261 & abstractcs_reg[10:8]; // @[dbg.scala 228:50]
   reg  abs_temp_12; // @[Reg.scala 27:20]
-  reg [2:0] abs_temp_10_8; // @[dbg.scala 230:12]
-  wire [10:0] _T_275 = {abs_temp_10_8,8'h2}; // @[Cat.scala 29:58]
-  wire [20:0] _T_277 = {19'h0,abs_temp_12,1'h0}; // @[Cat.scala 29:58]
-  wire  _T_282 = dbg_state == 3'h2; // @[dbg.scala 235:100]
-  wire  command_wren = _T_225 & _T_282; // @[dbg.scala 235:87]
-  wire [19:0] _T_286 = {3'h0,io_dmi_reg_wdata[16:0]}; // @[Cat.scala 29:58]
-  wire [11:0] _T_288 = {io_dmi_reg_wdata[31:24],1'h0,io_dmi_reg_wdata[22:20]}; // @[Cat.scala 29:58]
-  wire  rvclkhdr_5_io_l1clk; // @[lib.scala 352:23]
-  wire  rvclkhdr_5_io_clk; // @[lib.scala 352:23]
-  wire  rvclkhdr_5_io_en; // @[lib.scala 352:23]
-  wire  rvclkhdr_5_io_scan_mode; // @[lib.scala 352:23]
-  reg [31:0] command_reg; // @[lib.scala 358:16]
-  wire  _T_292 = _T_83 & _T_207; // @[dbg.scala 241:58]
-  wire  data0_reg_wren0 = _T_292 & _T_282; // @[dbg.scala 241:89]
-  wire  _T_294 = dbg_state == 3'h4; // @[dbg.scala 242:59]
-  wire  _T_295 = io_core_dbg_cmd_done & _T_294; // @[dbg.scala 242:46]
-  wire  _T_297 = ~command_reg[16]; // @[dbg.scala 242:83]
-  wire  data0_reg_wren1 = _T_295 & _T_297; // @[dbg.scala 242:81]
-  wire [31:0] _T_299 = data0_reg_wren0 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
-  wire [31:0] _T_300 = _T_299 & io_dmi_reg_wdata; // @[dbg.scala 245:45]
-  wire [31:0] _T_302 = data0_reg_wren1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
-  wire [31:0] _T_303 = _T_302 & io_core_dbg_rddata; // @[dbg.scala 245:92]
-  wire  rvclkhdr_6_io_l1clk; // @[lib.scala 352:23]
-  wire  rvclkhdr_6_io_clk; // @[lib.scala 352:23]
-  wire  rvclkhdr_6_io_en; // @[lib.scala 352:23]
-  wire  rvclkhdr_6_io_scan_mode; // @[lib.scala 352:23]
-  reg [31:0] data0_reg; // @[lib.scala 358:16]
-  wire  _T_306 = io_dmi_reg_addr == 7'h5; // @[dbg.scala 250:77]
-  wire  _T_307 = _T_83 & _T_306; // @[dbg.scala 250:58]
-  wire  data1_reg_wren = _T_307 & _T_282; // @[dbg.scala 250:89]
-  wire [31:0] _T_310 = data1_reg_wren ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
-  wire  rvclkhdr_7_io_l1clk; // @[lib.scala 352:23]
-  wire  rvclkhdr_7_io_clk; // @[lib.scala 352:23]
-  wire  rvclkhdr_7_io_en; // @[lib.scala 352:23]
-  wire  rvclkhdr_7_io_scan_mode; // @[lib.scala 352:23]
-  reg [31:0] _T_312; // @[lib.scala 358:16]
+  reg [2:0] abs_temp_10_8; // @[dbg.scala 235:12]
+  wire [10:0] _T_265 = {abs_temp_10_8,8'h2}; // @[Cat.scala 29:58]
+  wire [20:0] _T_267 = {19'h0,abs_temp_12,1'h0}; // @[Cat.scala 29:58]
+  wire  _T_272 = dbg_state == 3'h2; // @[dbg.scala 240:100]
+  wire  command_wren = _T_217 & _T_272; // @[dbg.scala 240:87]
+  wire [19:0] _T_276 = {3'h0,io_dmi_reg_wdata[16:0]}; // @[Cat.scala 29:58]
+  wire [11:0] _T_278 = {io_dmi_reg_wdata[31:24],1'h0,io_dmi_reg_wdata[22:20]}; // @[Cat.scala 29:58]
+  wire  rvclkhdr_5_io_l1clk; // @[lib.scala 368:23]
+  wire  rvclkhdr_5_io_clk; // @[lib.scala 368:23]
+  wire  rvclkhdr_5_io_en; // @[lib.scala 368:23]
+  wire  rvclkhdr_5_io_scan_mode; // @[lib.scala 368:23]
+  reg [31:0] command_reg; // @[lib.scala 374:16]
+  wire  _T_281 = _T_83 & _T_199; // @[dbg.scala 246:58]
+  wire  data0_reg_wren0 = _T_281 & _T_272; // @[dbg.scala 246:89]
+  wire  _T_283 = dbg_state == 3'h4; // @[dbg.scala 247:59]
+  wire  _T_284 = io_core_dbg_cmd_done & _T_283; // @[dbg.scala 247:46]
+  wire  _T_286 = ~command_reg[16]; // @[dbg.scala 247:83]
+  wire  data0_reg_wren1 = _T_284 & _T_286; // @[dbg.scala 247:81]
+  wire [31:0] _T_288 = data0_reg_wren0 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
+  wire [31:0] _T_289 = _T_288 & io_dmi_reg_wdata; // @[dbg.scala 250:45]
+  wire [31:0] _T_291 = data0_reg_wren1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
+  wire [31:0] _T_292 = _T_291 & io_core_dbg_rddata; // @[dbg.scala 250:92]
+  wire  rvclkhdr_6_io_l1clk; // @[lib.scala 368:23]
+  wire  rvclkhdr_6_io_clk; // @[lib.scala 368:23]
+  wire  rvclkhdr_6_io_en; // @[lib.scala 368:23]
+  wire  rvclkhdr_6_io_scan_mode; // @[lib.scala 368:23]
+  reg [31:0] data0_reg; // @[lib.scala 374:16]
+  wire  _T_294 = io_dmi_reg_addr == 7'h5; // @[dbg.scala 255:77]
+  wire  _T_295 = _T_83 & _T_294; // @[dbg.scala 255:58]
+  wire  data1_reg_wren = _T_295 & _T_272; // @[dbg.scala 255:89]
+  wire [31:0] _T_298 = data1_reg_wren ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
+  wire  rvclkhdr_7_io_l1clk; // @[lib.scala 368:23]
+  wire  rvclkhdr_7_io_clk; // @[lib.scala 368:23]
+  wire  rvclkhdr_7_io_en; // @[lib.scala 368:23]
+  wire  rvclkhdr_7_io_scan_mode; // @[lib.scala 368:23]
+  reg [31:0] _T_299; // @[lib.scala 374:16]
   wire [2:0] dbg_nxtstate;
-  wire  _T_313 = 3'h0 == dbg_state; // @[Conditional.scala 37:30]
-  wire  _T_315 = dmstatus_reg[9] | io_dec_tlu_mpc_halted_only; // @[dbg.scala 265:43]
-  wire [2:0] _T_316 = _T_315 ? 3'h2 : 3'h1; // @[dbg.scala 265:26]
-  wire  _T_318 = ~io_dec_tlu_debug_mode; // @[dbg.scala 266:45]
-  wire  _T_319 = dmcontrol_reg[31] & _T_318; // @[dbg.scala 266:43]
-  wire  _T_321 = _T_319 | dmstatus_reg[9]; // @[dbg.scala 266:69]
-  wire  _T_322 = _T_321 | io_dec_tlu_mpc_halted_only; // @[dbg.scala 266:87]
-  wire  _T_325 = _T_322 & _T_11; // @[dbg.scala 266:117]
-  wire  _T_329 = dmcontrol_reg[31] & _T_11; // @[dbg.scala 267:45]
-  wire  _T_331 = 3'h1 == dbg_state; // @[Conditional.scala 37:30]
-  wire [2:0] _T_333 = dmcontrol_reg[1] ? 3'h0 : 3'h2; // @[dbg.scala 270:26]
-  wire  _T_336 = dmstatus_reg[9] | dmcontrol_reg[1]; // @[dbg.scala 271:39]
-  wire  _T_338 = dmcontrol_wren_Q & dmcontrol_reg[31]; // @[dbg.scala 272:44]
-  wire  _T_341 = _T_338 & _T_11; // @[dbg.scala 272:64]
-  wire  _T_343 = 3'h2 == dbg_state; // @[Conditional.scala 37:30]
-  wire  _T_347 = dmstatus_reg[9] & _T_11; // @[dbg.scala 275:43]
-  wire  _T_350 = ~dmcontrol_reg[31]; // @[dbg.scala 276:33]
-  wire  _T_351 = dmcontrol_reg[30] & _T_350; // @[dbg.scala 276:31]
-  wire [2:0] _T_352 = _T_351 ? 3'h6 : 3'h3; // @[dbg.scala 276:12]
-  wire [2:0] _T_354 = dmcontrol_reg[31] ? 3'h1 : 3'h0; // @[dbg.scala 277:12]
-  wire [2:0] _T_355 = _T_347 ? _T_352 : _T_354; // @[dbg.scala 275:26]
-  wire  _T_358 = dmstatus_reg[9] & dmcontrol_reg[30]; // @[dbg.scala 278:39]
-  wire  _T_361 = _T_358 & _T_350; // @[dbg.scala 278:59]
-  wire  _T_362 = _T_361 & dmcontrol_wren_Q; // @[dbg.scala 278:80]
-  wire  _T_363 = _T_362 | command_wren; // @[dbg.scala 278:99]
-  wire  _T_365 = _T_363 | dmcontrol_reg[1]; // @[dbg.scala 278:114]
-  wire  _T_368 = ~_T_315; // @[dbg.scala 279:28]
-  wire  _T_369 = _T_365 | _T_368; // @[dbg.scala 279:26]
-  wire  _T_370 = dbg_nxtstate == 3'h3; // @[dbg.scala 280:60]
-  wire  _T_371 = dbg_state_en & _T_370; // @[dbg.scala 280:44]
-  wire  _T_372 = dbg_nxtstate == 3'h6; // @[dbg.scala 282:58]
-  wire  _T_373 = dbg_state_en & _T_372; // @[dbg.scala 282:42]
-  wire  _T_381 = 3'h3 == dbg_state; // @[Conditional.scala 37:30]
-  wire  _T_384 = |abstractcs_reg[10:8]; // @[dbg.scala 286:85]
-  wire [2:0] _T_385 = _T_384 ? 3'h5 : 3'h4; // @[dbg.scala 286:62]
-  wire [2:0] _T_386 = dmcontrol_reg[1] ? 3'h0 : _T_385; // @[dbg.scala 286:26]
-  wire  _T_389 = io_dbg_dec_dbg_ib_dbg_cmd_valid | _T_384; // @[dbg.scala 287:55]
-  wire  _T_391 = _T_389 | dmcontrol_reg[1]; // @[dbg.scala 287:83]
-  wire  _T_398 = 3'h4 == dbg_state; // @[Conditional.scala 37:30]
-  wire [2:0] _T_400 = dmcontrol_reg[1] ? 3'h0 : 3'h5; // @[dbg.scala 291:26]
-  wire  _T_402 = io_core_dbg_cmd_done | dmcontrol_reg[1]; // @[dbg.scala 292:44]
-  wire  _T_409 = 3'h5 == dbg_state; // @[Conditional.scala 37:30]
-  wire  _T_418 = 3'h6 == dbg_state; // @[Conditional.scala 37:30]
-  wire  _T_421 = dmstatus_reg[17] | dmcontrol_reg[1]; // @[dbg.scala 304:40]
-  wire  _GEN_10 = _T_418 & _T_421; // @[Conditional.scala 39:67]
-  wire  _GEN_11 = _T_418 & _T_341; // @[Conditional.scala 39:67]
-  wire [2:0] _GEN_12 = _T_409 ? _T_333 : 3'h0; // @[Conditional.scala 39:67]
-  wire  _GEN_13 = _T_409 | _GEN_10; // @[Conditional.scala 39:67]
-  wire  _GEN_14 = _T_409 & dbg_state_en; // @[Conditional.scala 39:67]
-  wire  _GEN_16 = _T_409 ? _T_341 : _GEN_11; // @[Conditional.scala 39:67]
-  wire [2:0] _GEN_17 = _T_398 ? _T_400 : _GEN_12; // @[Conditional.scala 39:67]
-  wire  _GEN_18 = _T_398 ? _T_402 : _GEN_13; // @[Conditional.scala 39:67]
-  wire  _GEN_19 = _T_398 ? _T_341 : _GEN_16; // @[Conditional.scala 39:67]
-  wire  _GEN_20 = _T_398 ? 1'h0 : _GEN_14; // @[Conditional.scala 39:67]
-  wire [2:0] _GEN_22 = _T_381 ? _T_386 : _GEN_17; // @[Conditional.scala 39:67]
-  wire  _GEN_23 = _T_381 ? _T_391 : _GEN_18; // @[Conditional.scala 39:67]
-  wire  _GEN_24 = _T_381 ? _T_341 : _GEN_19; // @[Conditional.scala 39:67]
-  wire  _GEN_25 = _T_381 ? 1'h0 : _GEN_20; // @[Conditional.scala 39:67]
-  wire [2:0] _GEN_27 = _T_343 ? _T_355 : _GEN_22; // @[Conditional.scala 39:67]
-  wire  _GEN_28 = _T_343 ? _T_369 : _GEN_23; // @[Conditional.scala 39:67]
-  wire  _GEN_29 = _T_343 ? _T_371 : _GEN_25; // @[Conditional.scala 39:67]
-  wire  _GEN_31 = _T_343 & _T_373; // @[Conditional.scala 39:67]
-  wire  _GEN_32 = _T_343 ? _T_341 : _GEN_24; // @[Conditional.scala 39:67]
-  wire [2:0] _GEN_33 = _T_331 ? _T_333 : _GEN_27; // @[Conditional.scala 39:67]
-  wire  _GEN_34 = _T_331 ? _T_336 : _GEN_28; // @[Conditional.scala 39:67]
-  wire  _GEN_35 = _T_331 ? _T_341 : _GEN_32; // @[Conditional.scala 39:67]
-  wire  _GEN_36 = _T_331 ? 1'h0 : _GEN_29; // @[Conditional.scala 39:67]
-  wire  _GEN_38 = _T_331 ? 1'h0 : _GEN_31; // @[Conditional.scala 39:67]
-  wire [31:0] _T_430 = _T_207 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
-  wire [31:0] _T_431 = _T_430 & data0_reg; // @[dbg.scala 308:71]
-  wire [31:0] _T_434 = _T_306 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
-  wire [31:0] _T_435 = _T_434 & data1_reg; // @[dbg.scala 308:122]
-  wire [31:0] _T_436 = _T_431 | _T_435; // @[dbg.scala 308:83]
-  wire [31:0] _T_439 = _T_133 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
-  wire [31:0] _T_440 = _T_439 & dmcontrol_reg; // @[dbg.scala 309:43]
-  wire [31:0] _T_441 = _T_436 | _T_440; // @[dbg.scala 308:134]
-  wire  _T_442 = io_dmi_reg_addr == 7'h11; // @[dbg.scala 309:86]
-  wire [31:0] _T_444 = _T_442 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
-  wire [31:0] _T_445 = _T_444 & dmstatus_reg; // @[dbg.scala 309:99]
-  wire [31:0] _T_446 = _T_441 | _T_445; // @[dbg.scala 309:59]
-  wire [31:0] _T_449 = _T_203 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
-  wire [31:0] _T_450 = _T_449 & abstractcs_reg; // @[dbg.scala 310:43]
-  wire [31:0] _T_451 = _T_446 | _T_450; // @[dbg.scala 309:114]
-  wire [31:0] _T_454 = _T_204 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
-  wire [31:0] _T_455 = _T_454 & command_reg; // @[dbg.scala 310:100]
-  wire [31:0] _T_456 = _T_451 | _T_455; // @[dbg.scala 310:60]
-  wire  _T_457 = io_dmi_reg_addr == 7'h40; // @[dbg.scala 311:30]
-  wire [31:0] _T_459 = _T_457 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
-  wire [31:0] _T_460 = _T_459 & haltsum0_reg; // @[dbg.scala 311:43]
-  wire [31:0] _T_461 = _T_456 | _T_460; // @[dbg.scala 310:114]
-  wire [31:0] _T_464 = _T_13 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
-  wire [31:0] _T_465 = _T_464 & sbcs_reg; // @[dbg.scala 311:98]
-  wire [31:0] _T_466 = _T_461 | _T_465; // @[dbg.scala 311:58]
-  wire [31:0] _T_469 = _T_21 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
-  wire [31:0] _T_470 = _T_469 & sbaddress0_reg; // @[dbg.scala 312:43]
-  wire [31:0] _T_471 = _T_466 | _T_470; // @[dbg.scala 311:109]
-  wire [31:0] _T_474 = _T_22 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
-  wire [31:0] _T_475 = _T_474 & sbdata0_reg; // @[dbg.scala 312:100]
-  wire [31:0] _T_476 = _T_471 | _T_475; // @[dbg.scala 312:60]
-  wire [31:0] _T_479 = _T_24 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
-  wire [31:0] _T_480 = _T_479 & sbdata1_reg; // @[dbg.scala 313:43]
-  wire [31:0] dmi_reg_rdata_din = _T_476 | _T_480; // @[dbg.scala 312:114]
-  wire  _T_482 = dbg_dm_rst_l & reset; // @[dbg.scala 315:86]
-  reg [2:0] _T_483; // @[Reg.scala 27:20]
-  reg [31:0] _T_485; // @[Reg.scala 27:20]
-  wire  _T_487 = command_reg[31:24] == 8'h2; // @[dbg.scala 324:62]
-  wire [31:0] _T_489 = {data1_reg[31:2],2'h0}; // @[Cat.scala 29:58]
-  wire [31:0] _T_491 = {20'h0,command_reg[11:0]}; // @[Cat.scala 29:58]
-  wire  _T_494 = dbg_state == 3'h3; // @[dbg.scala 326:50]
-  wire  _T_497 = ~_T_384; // @[dbg.scala 326:75]
-  wire  _T_498 = _T_494 & _T_497; // @[dbg.scala 326:73]
-  wire  _T_506 = command_reg[15:12] == 4'h0; // @[dbg.scala 328:122]
-  wire [1:0] _T_507 = {1'h0,_T_506}; // @[Cat.scala 29:58]
-  wire  _T_518 = 4'h0 == sb_state; // @[Conditional.scala 37:30]
-  wire  _T_520 = sbdata0_reg_wren0 | sbreadondata_access; // @[dbg.scala 343:39]
-  wire  _T_521 = _T_520 | sbreadonaddr_access; // @[dbg.scala 343:61]
-  wire  _T_523 = |io_dmi_reg_wdata[14:12]; // @[dbg.scala 346:65]
-  wire  _T_524 = sbcs_wren & _T_523; // @[dbg.scala 346:38]
-  wire [2:0] _T_526 = ~io_dmi_reg_wdata[14:12]; // @[dbg.scala 347:27]
-  wire [2:0] _T_528 = _T_526 & sbcs_reg[14:12]; // @[dbg.scala 347:53]
-  wire  _T_529 = 4'h1 == sb_state; // @[Conditional.scala 37:30]
-  wire  _T_530 = sbcs_unaligned | sbcs_illegal_size; // @[dbg.scala 350:41]
-  wire  _T_532 = io_dbg_bus_clk_en | sbcs_unaligned; // @[dbg.scala 351:40]
-  wire  _T_533 = _T_532 | sbcs_illegal_size; // @[dbg.scala 351:57]
-  wire  _T_536 = 4'h2 == sb_state; // @[Conditional.scala 37:30]
-  wire  _T_543 = 4'h3 == sb_state; // @[Conditional.scala 37:30]
-  wire  _T_544 = sb_bus_cmd_read & io_dbg_bus_clk_en; // @[dbg.scala 363:38]
-  wire  _T_545 = 4'h4 == sb_state; // @[Conditional.scala 37:30]
-  wire  _T_546 = sb_bus_cmd_write_addr & sb_bus_cmd_write_data; // @[dbg.scala 366:48]
-  wire  _T_549 = sb_bus_cmd_write_addr | sb_bus_cmd_write_data; // @[dbg.scala 367:45]
-  wire  _T_550 = _T_549 & io_dbg_bus_clk_en; // @[dbg.scala 367:70]
-  wire  _T_551 = 4'h5 == sb_state; // @[Conditional.scala 37:30]
-  wire  _T_552 = sb_bus_cmd_write_addr & io_dbg_bus_clk_en; // @[dbg.scala 371:44]
-  wire  _T_553 = 4'h6 == sb_state; // @[Conditional.scala 37:30]
-  wire  _T_554 = sb_bus_cmd_write_data & io_dbg_bus_clk_en; // @[dbg.scala 375:44]
-  wire  _T_555 = 4'h7 == sb_state; // @[Conditional.scala 37:30]
-  wire  _T_556 = sb_bus_rsp_read & io_dbg_bus_clk_en; // @[dbg.scala 379:38]
-  wire  _T_557 = sb_state_en & sb_bus_rsp_error; // @[dbg.scala 380:40]
-  wire  _T_558 = 4'h8 == sb_state; // @[Conditional.scala 37:30]
-  wire  _T_559 = sb_bus_rsp_write & io_dbg_bus_clk_en; // @[dbg.scala 385:39]
-  wire  _T_561 = 4'h9 == sb_state; // @[Conditional.scala 37:30]
-  wire  _GEN_50 = _T_561 & sbcs_reg[16]; // @[Conditional.scala 39:67]
-  wire  _GEN_52 = _T_558 ? _T_559 : _T_561; // @[Conditional.scala 39:67]
-  wire  _GEN_53 = _T_558 & _T_557; // @[Conditional.scala 39:67]
-  wire  _GEN_55 = _T_558 ? 1'h0 : _T_561; // @[Conditional.scala 39:67]
-  wire  _GEN_57 = _T_558 ? 1'h0 : _GEN_50; // @[Conditional.scala 39:67]
-  wire  _GEN_59 = _T_555 ? _T_556 : _GEN_52; // @[Conditional.scala 39:67]
-  wire  _GEN_60 = _T_555 ? _T_557 : _GEN_53; // @[Conditional.scala 39:67]
-  wire  _GEN_62 = _T_555 ? 1'h0 : _GEN_55; // @[Conditional.scala 39:67]
-  wire  _GEN_64 = _T_555 ? 1'h0 : _GEN_57; // @[Conditional.scala 39:67]
-  wire  _GEN_66 = _T_553 ? _T_554 : _GEN_59; // @[Conditional.scala 39:67]
-  wire  _GEN_67 = _T_553 ? 1'h0 : _GEN_60; // @[Conditional.scala 39:67]
-  wire  _GEN_69 = _T_553 ? 1'h0 : _GEN_62; // @[Conditional.scala 39:67]
-  wire  _GEN_71 = _T_553 ? 1'h0 : _GEN_64; // @[Conditional.scala 39:67]
-  wire  _GEN_73 = _T_551 ? _T_552 : _GEN_66; // @[Conditional.scala 39:67]
-  wire  _GEN_74 = _T_551 ? 1'h0 : _GEN_67; // @[Conditional.scala 39:67]
-  wire  _GEN_76 = _T_551 ? 1'h0 : _GEN_69; // @[Conditional.scala 39:67]
-  wire  _GEN_78 = _T_551 ? 1'h0 : _GEN_71; // @[Conditional.scala 39:67]
-  wire  _GEN_80 = _T_545 ? _T_550 : _GEN_73; // @[Conditional.scala 39:67]
-  wire  _GEN_81 = _T_545 ? 1'h0 : _GEN_74; // @[Conditional.scala 39:67]
-  wire  _GEN_83 = _T_545 ? 1'h0 : _GEN_76; // @[Conditional.scala 39:67]
-  wire  _GEN_85 = _T_545 ? 1'h0 : _GEN_78; // @[Conditional.scala 39:67]
-  wire  _GEN_87 = _T_543 ? _T_544 : _GEN_80; // @[Conditional.scala 39:67]
-  wire  _GEN_88 = _T_543 ? 1'h0 : _GEN_81; // @[Conditional.scala 39:67]
-  wire  _GEN_90 = _T_543 ? 1'h0 : _GEN_83; // @[Conditional.scala 39:67]
-  wire  _GEN_92 = _T_543 ? 1'h0 : _GEN_85; // @[Conditional.scala 39:67]
-  wire  _GEN_94 = _T_536 ? _T_533 : _GEN_87; // @[Conditional.scala 39:67]
-  wire  _GEN_95 = _T_536 ? _T_530 : _GEN_88; // @[Conditional.scala 39:67]
-  wire  _GEN_97 = _T_536 ? 1'h0 : _GEN_90; // @[Conditional.scala 39:67]
-  wire  _GEN_99 = _T_536 ? 1'h0 : _GEN_92; // @[Conditional.scala 39:67]
-  wire  _GEN_101 = _T_529 ? _T_533 : _GEN_94; // @[Conditional.scala 39:67]
-  wire  _GEN_102 = _T_529 ? _T_530 : _GEN_95; // @[Conditional.scala 39:67]
-  wire  _GEN_104 = _T_529 ? 1'h0 : _GEN_97; // @[Conditional.scala 39:67]
-  wire  _GEN_106 = _T_529 ? 1'h0 : _GEN_99; // @[Conditional.scala 39:67]
-  reg [3:0] _T_564; // @[Reg.scala 27:20]
-  wire  _T_571 = |io_sb_axi_r_bits_resp; // @[dbg.scala 406:69]
-  wire  _T_572 = sb_bus_rsp_read & _T_571; // @[dbg.scala 406:39]
-  wire  _T_574 = |io_sb_axi_b_bits_resp; // @[dbg.scala 406:122]
-  wire  _T_575 = sb_bus_rsp_write & _T_574; // @[dbg.scala 406:92]
-  wire  _T_577 = sb_state == 4'h4; // @[dbg.scala 407:36]
-  wire  _T_578 = sb_state == 4'h5; // @[dbg.scala 407:71]
-  wire  _T_584 = sb_state == 4'h6; // @[dbg.scala 418:70]
-  wire [63:0] _T_590 = _T_62 ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12]
-  wire [63:0] _T_594 = {sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0]}; // @[Cat.scala 29:58]
-  wire [63:0] _T_595 = _T_590 & _T_594; // @[dbg.scala 419:65]
-  wire [63:0] _T_599 = _T_47 ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12]
-  wire [63:0] _T_602 = {sbdata0_reg[15:0],sbdata0_reg[15:0],sbdata0_reg[15:0],sbdata0_reg[15:0]}; // @[Cat.scala 29:58]
-  wire [63:0] _T_603 = _T_599 & _T_602; // @[dbg.scala 419:138]
-  wire [63:0] _T_604 = _T_595 | _T_603; // @[dbg.scala 419:96]
-  wire [63:0] _T_608 = _T_51 ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12]
-  wire [63:0] _T_610 = {sbdata0_reg,sbdata0_reg}; // @[Cat.scala 29:58]
-  wire [63:0] _T_611 = _T_608 & _T_610; // @[dbg.scala 420:45]
-  wire [63:0] _T_612 = _T_604 | _T_611; // @[dbg.scala 419:168]
-  wire [63:0] _T_616 = _T_57 ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12]
-  wire [63:0] _T_619 = {sbdata1_reg,sbdata0_reg}; // @[Cat.scala 29:58]
-  wire [63:0] _T_620 = _T_616 & _T_619; // @[dbg.scala 420:119]
-  wire [7:0] _T_625 = _T_62 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
-  wire [14:0] _T_627 = 15'h1 << sbaddress0_reg[2:0]; // @[dbg.scala 422:82]
-  wire [14:0] _GEN_115 = {{7'd0}, _T_625}; // @[dbg.scala 422:67]
-  wire [14:0] _T_628 = _GEN_115 & _T_627; // @[dbg.scala 422:67]
-  wire [7:0] _T_632 = _T_47 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
-  wire [2:0] _T_634 = {sbaddress0_reg[2:1],1'h0}; // @[Cat.scala 29:58]
-  wire [14:0] _T_635 = 15'h3 << _T_634; // @[dbg.scala 423:59]
-  wire [14:0] _GEN_116 = {{7'd0}, _T_632}; // @[dbg.scala 423:44]
-  wire [14:0] _T_636 = _GEN_116 & _T_635; // @[dbg.scala 423:44]
-  wire [14:0] _T_637 = _T_628 | _T_636; // @[dbg.scala 422:107]
-  wire [7:0] _T_641 = _T_51 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
-  wire [2:0] _T_643 = {sbaddress0_reg[2],2'h0}; // @[Cat.scala 29:58]
-  wire [14:0] _T_644 = 15'hf << _T_643; // @[dbg.scala 424:59]
-  wire [14:0] _GEN_117 = {{7'd0}, _T_641}; // @[dbg.scala 424:44]
-  wire [14:0] _T_645 = _GEN_117 & _T_644; // @[dbg.scala 424:44]
-  wire [14:0] _T_646 = _T_637 | _T_645; // @[dbg.scala 423:97]
-  wire [7:0] _T_650 = _T_57 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
-  wire [14:0] _GEN_118 = {{7'd0}, _T_650}; // @[dbg.scala 424:100]
-  wire [14:0] _T_652 = _T_646 | _GEN_118; // @[dbg.scala 424:100]
-  wire [3:0] _GEN_119 = {{1'd0}, sbaddress0_reg[2:0]}; // @[dbg.scala 441:99]
-  wire [6:0] _T_663 = 4'h8 * _GEN_119; // @[dbg.scala 441:99]
-  wire [63:0] _T_664 = io_sb_axi_r_bits_data >> _T_663; // @[dbg.scala 441:92]
-  wire [63:0] _T_665 = _T_664 & 64'hff; // @[dbg.scala 441:123]
-  wire [63:0] _T_666 = _T_590 & _T_665; // @[dbg.scala 441:59]
-  wire [4:0] _GEN_120 = {{3'd0}, sbaddress0_reg[2:1]}; // @[dbg.scala 442:86]
-  wire [6:0] _T_673 = 5'h10 * _GEN_120; // @[dbg.scala 442:86]
-  wire [63:0] _T_674 = io_sb_axi_r_bits_data >> _T_673; // @[dbg.scala 442:78]
-  wire [63:0] _T_675 = _T_674 & 64'hffff; // @[dbg.scala 442:110]
-  wire [63:0] _T_676 = _T_599 & _T_675; // @[dbg.scala 442:45]
-  wire [63:0] _T_677 = _T_666 | _T_676; // @[dbg.scala 441:140]
-  wire [5:0] _GEN_121 = {{5'd0}, sbaddress0_reg[2]}; // @[dbg.scala 443:86]
-  wire [6:0] _T_684 = 6'h20 * _GEN_121; // @[dbg.scala 443:86]
-  wire [63:0] _T_685 = io_sb_axi_r_bits_data >> _T_684; // @[dbg.scala 443:78]
-  wire [63:0] _T_686 = _T_685 & 64'hffffffff; // @[dbg.scala 443:107]
-  wire [63:0] _T_687 = _T_608 & _T_686; // @[dbg.scala 443:45]
-  wire [63:0] _T_688 = _T_677 | _T_687; // @[dbg.scala 442:129]
-  wire [63:0] _T_694 = _T_616 & io_sb_axi_r_bits_data; // @[dbg.scala 444:45]
-  rvclkhdr rvclkhdr ( // @[lib.scala 327:22]
+  wire  _T_300 = 3'h0 == dbg_state; // @[Conditional.scala 37:30]
+  wire  _T_302 = dmstatus_reg[9] | io_dec_tlu_mpc_halted_only; // @[dbg.scala 270:43]
+  wire [2:0] _T_303 = _T_302 ? 3'h2 : 3'h1; // @[dbg.scala 270:26]
+  wire  _T_305 = ~io_dec_tlu_debug_mode; // @[dbg.scala 271:45]
+  wire  _T_306 = dmcontrol_reg[31] & _T_305; // @[dbg.scala 271:43]
+  wire  _T_308 = _T_306 | dmstatus_reg[9]; // @[dbg.scala 271:69]
+  wire  _T_309 = _T_308 | io_dec_tlu_mpc_halted_only; // @[dbg.scala 271:87]
+  wire  _T_312 = _T_309 & _T_17; // @[dbg.scala 271:117]
+  wire  _T_316 = dmcontrol_reg[31] & _T_17; // @[dbg.scala 272:45]
+  wire  _T_318 = 3'h1 == dbg_state; // @[Conditional.scala 37:30]
+  wire [2:0] _T_320 = dmcontrol_reg[1] ? 3'h0 : 3'h2; // @[dbg.scala 275:26]
+  wire  _T_323 = dmstatus_reg[9] | dmcontrol_reg[1]; // @[dbg.scala 276:39]
+  wire  _T_325 = dmcontrol_wren_Q & dmcontrol_reg[31]; // @[dbg.scala 277:44]
+  wire  _T_328 = _T_325 & _T_17; // @[dbg.scala 277:64]
+  wire  _T_330 = 3'h2 == dbg_state; // @[Conditional.scala 37:30]
+  wire  _T_334 = dmstatus_reg[9] & _T_17; // @[dbg.scala 280:43]
+  wire  _T_337 = ~dmcontrol_reg[31]; // @[dbg.scala 281:33]
+  wire  _T_338 = dmcontrol_reg[30] & _T_337; // @[dbg.scala 281:31]
+  wire [2:0] _T_339 = _T_338 ? 3'h6 : 3'h3; // @[dbg.scala 281:12]
+  wire [2:0] _T_341 = dmcontrol_reg[31] ? 3'h1 : 3'h0; // @[dbg.scala 282:12]
+  wire [2:0] _T_342 = _T_334 ? _T_339 : _T_341; // @[dbg.scala 280:26]
+  wire  _T_345 = dmstatus_reg[9] & dmcontrol_reg[30]; // @[dbg.scala 283:39]
+  wire  _T_348 = _T_345 & _T_337; // @[dbg.scala 283:59]
+  wire  _T_349 = _T_348 & dmcontrol_wren_Q; // @[dbg.scala 283:80]
+  wire  _T_350 = _T_349 | command_wren; // @[dbg.scala 283:99]
+  wire  _T_352 = _T_350 | dmcontrol_reg[1]; // @[dbg.scala 283:114]
+  wire  _T_355 = ~_T_302; // @[dbg.scala 284:28]
+  wire  _T_356 = _T_352 | _T_355; // @[dbg.scala 284:26]
+  wire  _T_357 = dbg_nxtstate == 3'h3; // @[dbg.scala 285:60]
+  wire  _T_358 = dbg_state_en & _T_357; // @[dbg.scala 285:44]
+  wire  _T_359 = dbg_nxtstate == 3'h6; // @[dbg.scala 287:58]
+  wire  _T_360 = dbg_state_en & _T_359; // @[dbg.scala 287:42]
+  wire  _T_368 = 3'h3 == dbg_state; // @[Conditional.scala 37:30]
+  wire  _T_371 = |abstractcs_reg[10:8]; // @[dbg.scala 291:85]
+  wire [2:0] _T_372 = _T_371 ? 3'h5 : 3'h4; // @[dbg.scala 291:62]
+  wire [2:0] _T_373 = dmcontrol_reg[1] ? 3'h0 : _T_372; // @[dbg.scala 291:26]
+  wire  _T_376 = io_dbg_dec_dbg_ib_dbg_cmd_valid | _T_371; // @[dbg.scala 292:55]
+  wire  _T_378 = _T_376 | dmcontrol_reg[1]; // @[dbg.scala 292:83]
+  wire  _T_385 = 3'h4 == dbg_state; // @[Conditional.scala 37:30]
+  wire [2:0] _T_387 = dmcontrol_reg[1] ? 3'h0 : 3'h5; // @[dbg.scala 296:26]
+  wire  _T_389 = io_core_dbg_cmd_done | dmcontrol_reg[1]; // @[dbg.scala 297:44]
+  wire  _T_396 = 3'h5 == dbg_state; // @[Conditional.scala 37:30]
+  wire  _T_405 = 3'h6 == dbg_state; // @[Conditional.scala 37:30]
+  wire  _T_408 = dmstatus_reg[17] | dmcontrol_reg[1]; // @[dbg.scala 309:40]
+  wire  _GEN_10 = _T_405 & _T_408; // @[Conditional.scala 39:67]
+  wire  _GEN_11 = _T_405 & _T_328; // @[Conditional.scala 39:67]
+  wire [2:0] _GEN_12 = _T_396 ? _T_320 : 3'h0; // @[Conditional.scala 39:67]
+  wire  _GEN_13 = _T_396 | _GEN_10; // @[Conditional.scala 39:67]
+  wire  _GEN_14 = _T_396 & dbg_state_en; // @[Conditional.scala 39:67]
+  wire  _GEN_16 = _T_396 ? _T_328 : _GEN_11; // @[Conditional.scala 39:67]
+  wire [2:0] _GEN_17 = _T_385 ? _T_387 : _GEN_12; // @[Conditional.scala 39:67]
+  wire  _GEN_18 = _T_385 ? _T_389 : _GEN_13; // @[Conditional.scala 39:67]
+  wire  _GEN_19 = _T_385 ? _T_328 : _GEN_16; // @[Conditional.scala 39:67]
+  wire  _GEN_20 = _T_385 ? 1'h0 : _GEN_14; // @[Conditional.scala 39:67]
+  wire [2:0] _GEN_22 = _T_368 ? _T_373 : _GEN_17; // @[Conditional.scala 39:67]
+  wire  _GEN_23 = _T_368 ? _T_378 : _GEN_18; // @[Conditional.scala 39:67]
+  wire  _GEN_24 = _T_368 ? _T_328 : _GEN_19; // @[Conditional.scala 39:67]
+  wire  _GEN_25 = _T_368 ? 1'h0 : _GEN_20; // @[Conditional.scala 39:67]
+  wire [2:0] _GEN_27 = _T_330 ? _T_342 : _GEN_22; // @[Conditional.scala 39:67]
+  wire  _GEN_28 = _T_330 ? _T_356 : _GEN_23; // @[Conditional.scala 39:67]
+  wire  _GEN_29 = _T_330 ? _T_358 : _GEN_25; // @[Conditional.scala 39:67]
+  wire  _GEN_31 = _T_330 & _T_360; // @[Conditional.scala 39:67]
+  wire  _GEN_32 = _T_330 ? _T_328 : _GEN_24; // @[Conditional.scala 39:67]
+  wire [2:0] _GEN_33 = _T_318 ? _T_320 : _GEN_27; // @[Conditional.scala 39:67]
+  wire  _GEN_34 = _T_318 ? _T_323 : _GEN_28; // @[Conditional.scala 39:67]
+  wire  _GEN_35 = _T_318 ? _T_328 : _GEN_32; // @[Conditional.scala 39:67]
+  wire  _GEN_36 = _T_318 ? 1'h0 : _GEN_29; // @[Conditional.scala 39:67]
+  wire  _GEN_38 = _T_318 ? 1'h0 : _GEN_31; // @[Conditional.scala 39:67]
+  wire [31:0] _T_417 = _T_199 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
+  wire [31:0] _T_418 = _T_417 & data0_reg; // @[dbg.scala 313:71]
+  wire [31:0] _T_421 = _T_294 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
+  wire [31:0] _T_422 = _T_421 & data1_reg; // @[dbg.scala 313:122]
+  wire [31:0] _T_423 = _T_418 | _T_422; // @[dbg.scala 313:83]
+  wire [31:0] _T_426 = _T_130 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
+  wire [31:0] _T_427 = _T_426 & dmcontrol_reg; // @[dbg.scala 314:43]
+  wire [31:0] _T_428 = _T_423 | _T_427; // @[dbg.scala 313:134]
+  wire  _T_429 = io_dmi_reg_addr == 7'h11; // @[dbg.scala 314:86]
+  wire [31:0] _T_431 = _T_429 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
+  wire [31:0] _T_432 = _T_431 & dmstatus_reg; // @[dbg.scala 314:99]
+  wire [31:0] _T_433 = _T_428 | _T_432; // @[dbg.scala 314:59]
+  wire [31:0] _T_436 = _T_195 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
+  wire [31:0] _T_437 = _T_436 & abstractcs_reg; // @[dbg.scala 315:43]
+  wire [31:0] _T_438 = _T_433 | _T_437; // @[dbg.scala 314:114]
+  wire [31:0] _T_441 = _T_196 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
+  wire [31:0] _T_442 = _T_441 & command_reg; // @[dbg.scala 315:100]
+  wire [31:0] _T_443 = _T_438 | _T_442; // @[dbg.scala 315:60]
+  wire  _T_444 = io_dmi_reg_addr == 7'h40; // @[dbg.scala 316:30]
+  wire [31:0] _T_446 = _T_444 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
+  wire [31:0] _T_447 = _T_446 & haltsum0_reg; // @[dbg.scala 316:43]
+  wire [31:0] _T_448 = _T_443 | _T_447; // @[dbg.scala 315:114]
+  wire [31:0] _T_451 = _T_19 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
+  wire [31:0] _T_452 = _T_451 & sbcs_reg; // @[dbg.scala 316:98]
+  wire [31:0] _T_453 = _T_448 | _T_452; // @[dbg.scala 316:58]
+  wire [31:0] _T_456 = _T_27 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
+  wire [31:0] _T_457 = _T_456 & sbaddress0_reg; // @[dbg.scala 317:43]
+  wire [31:0] _T_458 = _T_453 | _T_457; // @[dbg.scala 316:109]
+  wire [31:0] _T_461 = _T_28 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
+  wire [31:0] _T_462 = _T_461 & sbdata0_reg; // @[dbg.scala 317:100]
+  wire [31:0] _T_463 = _T_458 | _T_462; // @[dbg.scala 317:60]
+  wire [31:0] _T_466 = _T_30 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
+  wire [31:0] _T_467 = _T_466 & sbdata1_reg; // @[dbg.scala 318:43]
+  wire [31:0] dmi_reg_rdata_din = _T_463 | _T_467; // @[dbg.scala 317:114]
+  reg [2:0] _T_468; // @[Reg.scala 27:20]
+  reg [31:0] _T_469; // @[Reg.scala 27:20]
+  wire  _T_471 = command_reg[31:24] == 8'h2; // @[dbg.scala 329:62]
+  wire [31:0] _T_473 = {data1_reg[31:2],2'h0}; // @[Cat.scala 29:58]
+  wire [31:0] _T_475 = {20'h0,command_reg[11:0]}; // @[Cat.scala 29:58]
+  wire  _T_478 = dbg_state == 3'h3; // @[dbg.scala 331:50]
+  wire  _T_481 = ~_T_371; // @[dbg.scala 331:75]
+  wire  _T_482 = _T_478 & _T_481; // @[dbg.scala 331:73]
+  wire  _T_490 = command_reg[15:12] == 4'h0; // @[dbg.scala 333:122]
+  wire [1:0] _T_491 = {1'h0,_T_490}; // @[Cat.scala 29:58]
+  wire  _T_502 = 4'h0 == sb_state; // @[Conditional.scala 37:30]
+  wire  _T_504 = sbdata0_reg_wren0 | sbreadondata_access; // @[dbg.scala 348:39]
+  wire  _T_505 = _T_504 | sbreadonaddr_access; // @[dbg.scala 348:61]
+  wire  _T_507 = |io_dmi_reg_wdata[14:12]; // @[dbg.scala 351:65]
+  wire  _T_508 = sbcs_wren & _T_507; // @[dbg.scala 351:38]
+  wire [2:0] _T_510 = ~io_dmi_reg_wdata[14:12]; // @[dbg.scala 352:27]
+  wire [2:0] _T_512 = _T_510 & sbcs_reg[14:12]; // @[dbg.scala 352:53]
+  wire  _T_513 = 4'h1 == sb_state; // @[Conditional.scala 37:30]
+  wire  _T_514 = sbcs_unaligned | sbcs_illegal_size; // @[dbg.scala 355:41]
+  wire  _T_516 = io_dbg_bus_clk_en | sbcs_unaligned; // @[dbg.scala 356:40]
+  wire  _T_517 = _T_516 | sbcs_illegal_size; // @[dbg.scala 356:57]
+  wire  _T_520 = 4'h2 == sb_state; // @[Conditional.scala 37:30]
+  wire  _T_527 = 4'h3 == sb_state; // @[Conditional.scala 37:30]
+  wire  _T_528 = sb_bus_cmd_read & io_dbg_bus_clk_en; // @[dbg.scala 368:38]
+  wire  _T_529 = 4'h4 == sb_state; // @[Conditional.scala 37:30]
+  wire  _T_530 = sb_bus_cmd_write_addr & sb_bus_cmd_write_data; // @[dbg.scala 371:48]
+  wire  _T_533 = sb_bus_cmd_write_addr | sb_bus_cmd_write_data; // @[dbg.scala 372:45]
+  wire  _T_534 = _T_533 & io_dbg_bus_clk_en; // @[dbg.scala 372:70]
+  wire  _T_535 = 4'h5 == sb_state; // @[Conditional.scala 37:30]
+  wire  _T_536 = sb_bus_cmd_write_addr & io_dbg_bus_clk_en; // @[dbg.scala 376:44]
+  wire  _T_537 = 4'h6 == sb_state; // @[Conditional.scala 37:30]
+  wire  _T_538 = sb_bus_cmd_write_data & io_dbg_bus_clk_en; // @[dbg.scala 380:44]
+  wire  _T_539 = 4'h7 == sb_state; // @[Conditional.scala 37:30]
+  wire  _T_540 = sb_bus_rsp_read & io_dbg_bus_clk_en; // @[dbg.scala 384:38]
+  wire  _T_541 = sb_state_en & sb_bus_rsp_error; // @[dbg.scala 385:40]
+  wire  _T_542 = 4'h8 == sb_state; // @[Conditional.scala 37:30]
+  wire  _T_543 = sb_bus_rsp_write & io_dbg_bus_clk_en; // @[dbg.scala 390:39]
+  wire  _T_545 = 4'h9 == sb_state; // @[Conditional.scala 37:30]
+  wire  _GEN_50 = _T_545 & sbcs_reg[16]; // @[Conditional.scala 39:67]
+  wire  _GEN_52 = _T_542 ? _T_543 : _T_545; // @[Conditional.scala 39:67]
+  wire  _GEN_53 = _T_542 & _T_541; // @[Conditional.scala 39:67]
+  wire  _GEN_55 = _T_542 ? 1'h0 : _T_545; // @[Conditional.scala 39:67]
+  wire  _GEN_57 = _T_542 ? 1'h0 : _GEN_50; // @[Conditional.scala 39:67]
+  wire  _GEN_59 = _T_539 ? _T_540 : _GEN_52; // @[Conditional.scala 39:67]
+  wire  _GEN_60 = _T_539 ? _T_541 : _GEN_53; // @[Conditional.scala 39:67]
+  wire  _GEN_62 = _T_539 ? 1'h0 : _GEN_55; // @[Conditional.scala 39:67]
+  wire  _GEN_64 = _T_539 ? 1'h0 : _GEN_57; // @[Conditional.scala 39:67]
+  wire  _GEN_66 = _T_537 ? _T_538 : _GEN_59; // @[Conditional.scala 39:67]
+  wire  _GEN_67 = _T_537 ? 1'h0 : _GEN_60; // @[Conditional.scala 39:67]
+  wire  _GEN_69 = _T_537 ? 1'h0 : _GEN_62; // @[Conditional.scala 39:67]
+  wire  _GEN_71 = _T_537 ? 1'h0 : _GEN_64; // @[Conditional.scala 39:67]
+  wire  _GEN_73 = _T_535 ? _T_536 : _GEN_66; // @[Conditional.scala 39:67]
+  wire  _GEN_74 = _T_535 ? 1'h0 : _GEN_67; // @[Conditional.scala 39:67]
+  wire  _GEN_76 = _T_535 ? 1'h0 : _GEN_69; // @[Conditional.scala 39:67]
+  wire  _GEN_78 = _T_535 ? 1'h0 : _GEN_71; // @[Conditional.scala 39:67]
+  wire  _GEN_80 = _T_529 ? _T_534 : _GEN_73; // @[Conditional.scala 39:67]
+  wire  _GEN_81 = _T_529 ? 1'h0 : _GEN_74; // @[Conditional.scala 39:67]
+  wire  _GEN_83 = _T_529 ? 1'h0 : _GEN_76; // @[Conditional.scala 39:67]
+  wire  _GEN_85 = _T_529 ? 1'h0 : _GEN_78; // @[Conditional.scala 39:67]
+  wire  _GEN_87 = _T_527 ? _T_528 : _GEN_80; // @[Conditional.scala 39:67]
+  wire  _GEN_88 = _T_527 ? 1'h0 : _GEN_81; // @[Conditional.scala 39:67]
+  wire  _GEN_90 = _T_527 ? 1'h0 : _GEN_83; // @[Conditional.scala 39:67]
+  wire  _GEN_92 = _T_527 ? 1'h0 : _GEN_85; // @[Conditional.scala 39:67]
+  wire  _GEN_94 = _T_520 ? _T_517 : _GEN_87; // @[Conditional.scala 39:67]
+  wire  _GEN_95 = _T_520 ? _T_514 : _GEN_88; // @[Conditional.scala 39:67]
+  wire  _GEN_97 = _T_520 ? 1'h0 : _GEN_90; // @[Conditional.scala 39:67]
+  wire  _GEN_99 = _T_520 ? 1'h0 : _GEN_92; // @[Conditional.scala 39:67]
+  wire  _GEN_101 = _T_513 ? _T_517 : _GEN_94; // @[Conditional.scala 39:67]
+  wire  _GEN_102 = _T_513 ? _T_514 : _GEN_95; // @[Conditional.scala 39:67]
+  wire  _GEN_104 = _T_513 ? 1'h0 : _GEN_97; // @[Conditional.scala 39:67]
+  wire  _GEN_106 = _T_513 ? 1'h0 : _GEN_99; // @[Conditional.scala 39:67]
+  reg [3:0] _T_547; // @[Reg.scala 27:20]
+  wire  _T_554 = |io_sb_axi_r_bits_resp; // @[dbg.scala 411:69]
+  wire  _T_555 = sb_bus_rsp_read & _T_554; // @[dbg.scala 411:39]
+  wire  _T_557 = |io_sb_axi_b_bits_resp; // @[dbg.scala 411:122]
+  wire  _T_558 = sb_bus_rsp_write & _T_557; // @[dbg.scala 411:92]
+  wire  _T_560 = sb_state == 4'h4; // @[dbg.scala 412:36]
+  wire  _T_561 = sb_state == 4'h5; // @[dbg.scala 412:71]
+  wire  _T_567 = sb_state == 4'h6; // @[dbg.scala 423:70]
+  wire [63:0] _T_573 = _T_62 ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12]
+  wire [63:0] _T_577 = {sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0],sbdata0_reg[7:0]}; // @[Cat.scala 29:58]
+  wire [63:0] _T_578 = _T_573 & _T_577; // @[dbg.scala 424:65]
+  wire [63:0] _T_582 = _T_47 ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12]
+  wire [63:0] _T_585 = {sbdata0_reg[15:0],sbdata0_reg[15:0],sbdata0_reg[15:0],sbdata0_reg[15:0]}; // @[Cat.scala 29:58]
+  wire [63:0] _T_586 = _T_582 & _T_585; // @[dbg.scala 424:138]
+  wire [63:0] _T_587 = _T_578 | _T_586; // @[dbg.scala 424:96]
+  wire [63:0] _T_591 = _T_51 ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12]
+  wire [63:0] _T_593 = {sbdata0_reg,sbdata0_reg}; // @[Cat.scala 29:58]
+  wire [63:0] _T_594 = _T_591 & _T_593; // @[dbg.scala 425:45]
+  wire [63:0] _T_595 = _T_587 | _T_594; // @[dbg.scala 424:168]
+  wire [63:0] _T_599 = _T_57 ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12]
+  wire [63:0] _T_602 = {sbdata1_reg,sbdata0_reg}; // @[Cat.scala 29:58]
+  wire [63:0] _T_603 = _T_599 & _T_602; // @[dbg.scala 425:119]
+  wire [7:0] _T_608 = _T_62 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
+  wire [14:0] _T_610 = 15'h1 << sbaddress0_reg[2:0]; // @[dbg.scala 427:82]
+  wire [14:0] _GEN_115 = {{7'd0}, _T_608}; // @[dbg.scala 427:67]
+  wire [14:0] _T_611 = _GEN_115 & _T_610; // @[dbg.scala 427:67]
+  wire [7:0] _T_615 = _T_47 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
+  wire [2:0] _T_617 = {sbaddress0_reg[2:1],1'h0}; // @[Cat.scala 29:58]
+  wire [14:0] _T_618 = 15'h3 << _T_617; // @[dbg.scala 428:59]
+  wire [14:0] _GEN_116 = {{7'd0}, _T_615}; // @[dbg.scala 428:44]
+  wire [14:0] _T_619 = _GEN_116 & _T_618; // @[dbg.scala 428:44]
+  wire [14:0] _T_620 = _T_611 | _T_619; // @[dbg.scala 427:107]
+  wire [7:0] _T_624 = _T_51 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
+  wire [2:0] _T_626 = {sbaddress0_reg[2],2'h0}; // @[Cat.scala 29:58]
+  wire [14:0] _T_627 = 15'hf << _T_626; // @[dbg.scala 429:59]
+  wire [14:0] _GEN_117 = {{7'd0}, _T_624}; // @[dbg.scala 429:44]
+  wire [14:0] _T_628 = _GEN_117 & _T_627; // @[dbg.scala 429:44]
+  wire [14:0] _T_629 = _T_620 | _T_628; // @[dbg.scala 428:97]
+  wire [7:0] _T_633 = _T_57 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
+  wire [14:0] _GEN_118 = {{7'd0}, _T_633}; // @[dbg.scala 429:100]
+  wire [14:0] _T_635 = _T_629 | _GEN_118; // @[dbg.scala 429:100]
+  wire [3:0] _GEN_119 = {{1'd0}, sbaddress0_reg[2:0]}; // @[dbg.scala 446:99]
+  wire [6:0] _T_646 = 4'h8 * _GEN_119; // @[dbg.scala 446:99]
+  wire [63:0] _T_647 = io_sb_axi_r_bits_data >> _T_646; // @[dbg.scala 446:92]
+  wire [63:0] _T_648 = _T_647 & 64'hff; // @[dbg.scala 446:123]
+  wire [63:0] _T_649 = _T_573 & _T_648; // @[dbg.scala 446:59]
+  wire [4:0] _GEN_120 = {{3'd0}, sbaddress0_reg[2:1]}; // @[dbg.scala 447:86]
+  wire [6:0] _T_656 = 5'h10 * _GEN_120; // @[dbg.scala 447:86]
+  wire [63:0] _T_657 = io_sb_axi_r_bits_data >> _T_656; // @[dbg.scala 447:78]
+  wire [63:0] _T_658 = _T_657 & 64'hffff; // @[dbg.scala 447:110]
+  wire [63:0] _T_659 = _T_582 & _T_658; // @[dbg.scala 447:45]
+  wire [63:0] _T_660 = _T_649 | _T_659; // @[dbg.scala 446:140]
+  wire [5:0] _GEN_121 = {{5'd0}, sbaddress0_reg[2]}; // @[dbg.scala 448:86]
+  wire [6:0] _T_667 = 6'h20 * _GEN_121; // @[dbg.scala 448:86]
+  wire [63:0] _T_668 = io_sb_axi_r_bits_data >> _T_667; // @[dbg.scala 448:78]
+  wire [63:0] _T_669 = _T_668 & 64'hffffffff; // @[dbg.scala 448:107]
+  wire [63:0] _T_670 = _T_591 & _T_669; // @[dbg.scala 448:45]
+  wire [63:0] _T_671 = _T_660 | _T_670; // @[dbg.scala 447:129]
+  wire [63:0] _T_677 = _T_599 & io_sb_axi_r_bits_data; // @[dbg.scala 449:45]
+  rvclkhdr rvclkhdr ( // @[lib.scala 343:22]
     .io_l1clk(rvclkhdr_io_l1clk),
     .io_clk(rvclkhdr_io_clk),
     .io_en(rvclkhdr_io_en),
     .io_scan_mode(rvclkhdr_io_scan_mode)
   );
-  rvclkhdr rvclkhdr_1 ( // @[lib.scala 327:22]
+  rvclkhdr rvclkhdr_1 ( // @[lib.scala 343:22]
     .io_l1clk(rvclkhdr_1_io_l1clk),
     .io_clk(rvclkhdr_1_io_clk),
     .io_en(rvclkhdr_1_io_en),
     .io_scan_mode(rvclkhdr_1_io_scan_mode)
   );
-  rvclkhdr rvclkhdr_2 ( // @[lib.scala 352:23]
+  rvclkhdr rvclkhdr_2 ( // @[lib.scala 368:23]
     .io_l1clk(rvclkhdr_2_io_l1clk),
     .io_clk(rvclkhdr_2_io_clk),
     .io_en(rvclkhdr_2_io_en),
     .io_scan_mode(rvclkhdr_2_io_scan_mode)
   );
-  rvclkhdr rvclkhdr_3 ( // @[lib.scala 352:23]
+  rvclkhdr rvclkhdr_3 ( // @[lib.scala 368:23]
     .io_l1clk(rvclkhdr_3_io_l1clk),
     .io_clk(rvclkhdr_3_io_clk),
     .io_en(rvclkhdr_3_io_en),
     .io_scan_mode(rvclkhdr_3_io_scan_mode)
   );
-  rvclkhdr rvclkhdr_4 ( // @[lib.scala 352:23]
+  rvclkhdr rvclkhdr_4 ( // @[lib.scala 368:23]
     .io_l1clk(rvclkhdr_4_io_l1clk),
     .io_clk(rvclkhdr_4_io_clk),
     .io_en(rvclkhdr_4_io_en),
     .io_scan_mode(rvclkhdr_4_io_scan_mode)
   );
-  rvclkhdr rvclkhdr_5 ( // @[lib.scala 352:23]
+  rvclkhdr rvclkhdr_5 ( // @[lib.scala 368:23]
     .io_l1clk(rvclkhdr_5_io_l1clk),
     .io_clk(rvclkhdr_5_io_clk),
     .io_en(rvclkhdr_5_io_en),
     .io_scan_mode(rvclkhdr_5_io_scan_mode)
   );
-  rvclkhdr rvclkhdr_6 ( // @[lib.scala 352:23]
+  rvclkhdr rvclkhdr_6 ( // @[lib.scala 368:23]
     .io_l1clk(rvclkhdr_6_io_l1clk),
     .io_clk(rvclkhdr_6_io_clk),
     .io_en(rvclkhdr_6_io_en),
     .io_scan_mode(rvclkhdr_6_io_scan_mode)
   );
-  rvclkhdr rvclkhdr_7 ( // @[lib.scala 352:23]
+  rvclkhdr rvclkhdr_7 ( // @[lib.scala 368:23]
     .io_l1clk(rvclkhdr_7_io_l1clk),
     .io_clk(rvclkhdr_7_io_clk),
     .io_en(rvclkhdr_7_io_en),
     .io_scan_mode(rvclkhdr_7_io_scan_mode)
   );
-  assign io_dbg_cmd_size = command_reg[21:20]; // @[dbg.scala 329:19]
-  assign io_dbg_core_rst_l = ~dmcontrol_reg[1]; // @[dbg.scala 100:21]
-  assign io_dbg_halt_req = _T_313 ? _T_329 : _GEN_35; // @[dbg.scala 261:19 dbg.scala 267:23 dbg.scala 272:23 dbg.scala 283:23 dbg.scala 288:23 dbg.scala 293:23 dbg.scala 300:23 dbg.scala 305:23]
-  assign io_dbg_resume_req = _T_313 ? 1'h0 : _GEN_38; // @[dbg.scala 262:21 dbg.scala 282:25]
-  assign io_dmi_reg_rdata = _T_485; // @[dbg.scala 320:20]
-  assign io_sb_axi_aw_valid = _T_577 | _T_578; // @[dbg.scala 407:22]
-  assign io_sb_axi_aw_bits_id = 1'h0; // @[dbg.scala 409:24]
-  assign io_sb_axi_aw_bits_addr = sbaddress0_reg; // @[dbg.scala 408:26]
-  assign io_sb_axi_aw_bits_region = sbaddress0_reg[31:28]; // @[dbg.scala 413:28]
-  assign io_sb_axi_aw_bits_len = 8'h0; // @[dbg.scala 414:25]
-  assign io_sb_axi_aw_bits_size = sbcs_reg[19:17]; // @[dbg.scala 410:26]
-  assign io_sb_axi_aw_bits_burst = 2'h1; // @[dbg.scala 415:27]
-  assign io_sb_axi_aw_bits_lock = 1'h0; // @[dbg.scala 417:26]
-  assign io_sb_axi_aw_bits_cache = 4'hf; // @[dbg.scala 412:27]
-  assign io_sb_axi_aw_bits_prot = 3'h0; // @[dbg.scala 411:26]
-  assign io_sb_axi_aw_bits_qos = 4'h0; // @[dbg.scala 416:25]
-  assign io_sb_axi_w_valid = _T_577 | _T_584; // @[dbg.scala 418:21]
-  assign io_sb_axi_w_bits_data = _T_612 | _T_620; // @[dbg.scala 419:25]
-  assign io_sb_axi_w_bits_strb = _T_652[7:0]; // @[dbg.scala 422:25]
-  assign io_sb_axi_w_bits_last = 1'h1; // @[dbg.scala 427:25]
-  assign io_sb_axi_b_ready = 1'h1; // @[dbg.scala 439:21]
-  assign io_sb_axi_ar_valid = sb_state == 4'h3; // @[dbg.scala 428:22]
-  assign io_sb_axi_ar_bits_id = 1'h0; // @[dbg.scala 430:24]
-  assign io_sb_axi_ar_bits_addr = sbaddress0_reg; // @[dbg.scala 429:26]
-  assign io_sb_axi_ar_bits_region = sbaddress0_reg[31:28]; // @[dbg.scala 434:28]
-  assign io_sb_axi_ar_bits_len = 8'h0; // @[dbg.scala 435:25]
-  assign io_sb_axi_ar_bits_size = sbcs_reg[19:17]; // @[dbg.scala 431:26]
-  assign io_sb_axi_ar_bits_burst = 2'h1; // @[dbg.scala 436:27]
-  assign io_sb_axi_ar_bits_lock = 1'h0; // @[dbg.scala 438:26]
-  assign io_sb_axi_ar_bits_cache = 4'h0; // @[dbg.scala 433:27]
-  assign io_sb_axi_ar_bits_prot = 3'h0; // @[dbg.scala 432:26]
-  assign io_sb_axi_ar_bits_qos = 4'h0; // @[dbg.scala 437:25]
-  assign io_sb_axi_r_ready = 1'h1; // @[dbg.scala 440:21]
-  assign io_dbg_dec_dbg_ib_dbg_cmd_valid = _T_498 & io_dbg_dma_io_dma_dbg_ready; // @[dbg.scala 326:35]
-  assign io_dbg_dec_dbg_ib_dbg_cmd_write = command_reg[16]; // @[dbg.scala 327:35]
-  assign io_dbg_dec_dbg_ib_dbg_cmd_type = _T_487 ? 2'h2 : _T_507; // @[dbg.scala 328:34]
-  assign io_dbg_dec_dbg_ib_dbg_cmd_addr = _T_487 ? _T_489 : _T_491; // @[dbg.scala 324:34]
-  assign io_dbg_dec_dbg_dctl_dbg_cmd_wrdata = data0_reg; // @[dbg.scala 325:38]
-  assign io_dbg_dma_dbg_ib_dbg_cmd_valid = io_dbg_dec_dbg_ib_dbg_cmd_valid; // @[dbg.scala 449:39]
-  assign io_dbg_dma_dbg_ib_dbg_cmd_write = io_dbg_dec_dbg_ib_dbg_cmd_write; // @[dbg.scala 450:39]
-  assign io_dbg_dma_dbg_ib_dbg_cmd_type = io_dbg_dec_dbg_ib_dbg_cmd_type; // @[dbg.scala 451:39]
-  assign io_dbg_dma_dbg_ib_dbg_cmd_addr = io_dbg_dec_dbg_ib_dbg_cmd_addr; // @[dbg.scala 447:39]
-  assign io_dbg_dma_dbg_dctl_dbg_cmd_wrdata = io_dbg_dec_dbg_dctl_dbg_cmd_wrdata; // @[dbg.scala 448:39]
-  assign io_dbg_dma_io_dbg_dma_bubble = _T_498 | _T_294; // @[dbg.scala 330:32]
-  assign dbg_state = _T_483; // @[dbg.scala 315:13]
-  assign dbg_state_en = _T_313 ? _T_325 : _GEN_34; // @[dbg.scala 258:16 dbg.scala 266:20 dbg.scala 271:20 dbg.scala 278:20 dbg.scala 287:20 dbg.scala 292:20 dbg.scala 297:20 dbg.scala 304:20]
-  assign sb_state = _T_564; // @[dbg.scala 397:12]
-  assign sb_state_en = _T_518 ? _T_521 : _GEN_101; // @[dbg.scala 343:19 dbg.scala 351:19 dbg.scala 357:19 dbg.scala 363:19 dbg.scala 367:19 dbg.scala 371:19 dbg.scala 375:19 dbg.scala 379:19 dbg.scala 385:19 dbg.scala 391:19]
-  assign dmcontrol_reg = {_T_149,_T_147}; // @[dbg.scala 178:17]
-  assign sbaddress0_reg = _T_121; // @[dbg.scala 159:18]
-  assign sbcs_sbbusy_wren = _T_518 ? sb_state_en : _GEN_104; // @[dbg.scala 335:20 dbg.scala 344:24 dbg.scala 392:24]
-  assign sbcs_sberror_wren = _T_518 ? _T_524 : _GEN_102; // @[dbg.scala 337:21 dbg.scala 346:25 dbg.scala 352:25 dbg.scala 358:25 dbg.scala 380:25 dbg.scala 386:25]
-  assign sb_bus_rdata = _T_688 | _T_694; // @[dbg.scala 441:16]
-  assign sbaddress0_reg_wren1 = _T_518 ? 1'h0 : _GEN_106; // @[dbg.scala 339:24 dbg.scala 394:28]
-  assign dmstatus_reg = {_T_168,_T_164}; // @[dbg.scala 184:16]
-  assign dmstatus_havereset = _T_200; // @[dbg.scala 201:22]
-  assign dmstatus_resumeack = _T_191; // @[dbg.scala 193:22]
-  assign dmstatus_unavail = dmcontrol_reg[1] | _T_185; // @[dbg.scala 191:20]
-  assign dmstatus_running = ~_T_188; // @[dbg.scala 192:20]
-  assign dmstatus_halted = _T_195; // @[dbg.scala 197:19]
-  assign abstractcs_busy_wren = _T_313 ? 1'h0 : _GEN_36; // @[dbg.scala 259:24 dbg.scala 280:28 dbg.scala 298:28]
-  assign sb_bus_cmd_read = io_sb_axi_ar_valid & io_sb_axi_ar_ready; // @[dbg.scala 401:19]
-  assign sb_bus_cmd_write_addr = io_sb_axi_aw_valid & io_sb_axi_aw_ready; // @[dbg.scala 402:25]
-  assign sb_bus_cmd_write_data = io_sb_axi_w_valid & io_sb_axi_w_ready; // @[dbg.scala 403:25]
-  assign sb_bus_rsp_read = io_sb_axi_r_valid & io_sb_axi_r_ready; // @[dbg.scala 404:19]
-  assign sb_bus_rsp_error = _T_572 | _T_575; // @[dbg.scala 406:20]
-  assign sb_bus_rsp_write = io_sb_axi_b_valid & io_sb_axi_b_ready; // @[dbg.scala 405:20]
-  assign sbcs_sbbusy_din = 4'h0 == sb_state; // @[dbg.scala 336:19 dbg.scala 345:23 dbg.scala 393:23]
-  assign data1_reg = _T_312; // @[dbg.scala 252:13]
-  assign sbcs_reg = {_T_44,_T_40}; // @[dbg.scala 125:12]
-  assign rvclkhdr_io_clk = clock; // @[lib.scala 328:17]
-  assign rvclkhdr_io_en = _T_3 | io_clk_override; // @[lib.scala 329:16]
-  assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 330:23]
-  assign rvclkhdr_1_io_clk = clock; // @[lib.scala 328:17]
-  assign rvclkhdr_1_io_en = _T_6 | io_clk_override; // @[lib.scala 329:16]
-  assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 330:23]
-  assign rvclkhdr_2_io_clk = clock; // @[lib.scala 354:18]
-  assign rvclkhdr_2_io_en = sbdata0_reg_wren0 | sbdata0_reg_wren1; // @[lib.scala 355:17]
-  assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[lib.scala 356:24]
-  assign rvclkhdr_3_io_clk = clock; // @[lib.scala 354:18]
-  assign rvclkhdr_3_io_en = sbdata1_reg_wren0 | sbdata0_reg_wren1; // @[lib.scala 355:17]
-  assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[lib.scala 356:24]
-  assign rvclkhdr_4_io_clk = clock; // @[lib.scala 354:18]
-  assign rvclkhdr_4_io_en = sbaddress0_reg_wren0 | sbaddress0_reg_wren1; // @[lib.scala 355:17]
-  assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[lib.scala 356:24]
-  assign abstractcs_reg = {_T_277,_T_275}; // @[dbg.scala 233:18]
-  assign rvclkhdr_5_io_clk = clock; // @[lib.scala 354:18]
-  assign rvclkhdr_5_io_en = _T_225 & _T_282; // @[lib.scala 355:17]
-  assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[lib.scala 356:24]
-  assign rvclkhdr_6_io_clk = clock; // @[lib.scala 354:18]
-  assign rvclkhdr_6_io_en = data0_reg_wren0 | data0_reg_wren1; // @[lib.scala 355:17]
-  assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[lib.scala 356:24]
-  assign rvclkhdr_7_io_clk = clock; // @[lib.scala 354:18]
-  assign rvclkhdr_7_io_en = _T_307 & _T_282; // @[lib.scala 355:17]
-  assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[lib.scala 356:24]
-  assign dbg_nxtstate = _T_313 ? _T_316 : _GEN_33; // @[dbg.scala 257:16 dbg.scala 265:20 dbg.scala 270:20 dbg.scala 275:20 dbg.scala 286:20 dbg.scala 291:20 dbg.scala 296:20 dbg.scala 303:20]
+  assign io_dbg_cmd_size = command_reg[21:20]; // @[dbg.scala 334:19]
+  assign io_dbg_core_rst_l = ~dmcontrol_reg[1]; // @[dbg.scala 105:21]
+  assign io_dbg_halt_req = _T_300 ? _T_316 : _GEN_35; // @[dbg.scala 266:19 dbg.scala 272:23 dbg.scala 277:23 dbg.scala 288:23 dbg.scala 293:23 dbg.scala 298:23 dbg.scala 305:23 dbg.scala 310:23]
+  assign io_dbg_resume_req = _T_300 ? 1'h0 : _GEN_38; // @[dbg.scala 267:21 dbg.scala 287:25]
+  assign io_dmi_reg_rdata = _T_469; // @[dbg.scala 325:20]
+  assign io_sb_axi_aw_valid = _T_560 | _T_561; // @[dbg.scala 412:22]
+  assign io_sb_axi_aw_bits_id = 1'h0; // @[dbg.scala 414:24]
+  assign io_sb_axi_aw_bits_addr = sbaddress0_reg; // @[dbg.scala 413:26]
+  assign io_sb_axi_aw_bits_region = sbaddress0_reg[31:28]; // @[dbg.scala 418:28]
+  assign io_sb_axi_aw_bits_len = 8'h0; // @[dbg.scala 419:25]
+  assign io_sb_axi_aw_bits_size = sbcs_reg[19:17]; // @[dbg.scala 415:26]
+  assign io_sb_axi_aw_bits_burst = 2'h1; // @[dbg.scala 420:27]
+  assign io_sb_axi_aw_bits_lock = 1'h0; // @[dbg.scala 422:26]
+  assign io_sb_axi_aw_bits_cache = 4'hf; // @[dbg.scala 417:27]
+  assign io_sb_axi_aw_bits_prot = 3'h0; // @[dbg.scala 416:26]
+  assign io_sb_axi_aw_bits_qos = 4'h0; // @[dbg.scala 421:25]
+  assign io_sb_axi_w_valid = _T_560 | _T_567; // @[dbg.scala 423:21]
+  assign io_sb_axi_w_bits_data = _T_595 | _T_603; // @[dbg.scala 424:25]
+  assign io_sb_axi_w_bits_strb = _T_635[7:0]; // @[dbg.scala 427:25]
+  assign io_sb_axi_w_bits_last = 1'h1; // @[dbg.scala 432:25]
+  assign io_sb_axi_b_ready = 1'h1; // @[dbg.scala 444:21]
+  assign io_sb_axi_ar_valid = sb_state == 4'h3; // @[dbg.scala 433:22]
+  assign io_sb_axi_ar_bits_id = 1'h0; // @[dbg.scala 435:24]
+  assign io_sb_axi_ar_bits_addr = sbaddress0_reg; // @[dbg.scala 434:26]
+  assign io_sb_axi_ar_bits_region = sbaddress0_reg[31:28]; // @[dbg.scala 439:28]
+  assign io_sb_axi_ar_bits_len = 8'h0; // @[dbg.scala 440:25]
+  assign io_sb_axi_ar_bits_size = sbcs_reg[19:17]; // @[dbg.scala 436:26]
+  assign io_sb_axi_ar_bits_burst = 2'h1; // @[dbg.scala 441:27]
+  assign io_sb_axi_ar_bits_lock = 1'h0; // @[dbg.scala 443:26]
+  assign io_sb_axi_ar_bits_cache = 4'h0; // @[dbg.scala 438:27]
+  assign io_sb_axi_ar_bits_prot = 3'h0; // @[dbg.scala 437:26]
+  assign io_sb_axi_ar_bits_qos = 4'h0; // @[dbg.scala 442:25]
+  assign io_sb_axi_r_ready = 1'h1; // @[dbg.scala 445:21]
+  assign io_dbg_dec_dbg_ib_dbg_cmd_valid = _T_482 & io_dbg_dma_io_dma_dbg_ready; // @[dbg.scala 331:35]
+  assign io_dbg_dec_dbg_ib_dbg_cmd_write = command_reg[16]; // @[dbg.scala 332:35]
+  assign io_dbg_dec_dbg_ib_dbg_cmd_type = _T_471 ? 2'h2 : _T_491; // @[dbg.scala 333:34]
+  assign io_dbg_dec_dbg_ib_dbg_cmd_addr = _T_471 ? _T_473 : _T_475; // @[dbg.scala 329:34]
+  assign io_dbg_dec_dbg_dctl_dbg_cmd_wrdata = data0_reg; // @[dbg.scala 330:38]
+  assign io_dbg_dma_dbg_ib_dbg_cmd_valid = io_dbg_dec_dbg_ib_dbg_cmd_valid; // @[dbg.scala 454:39]
+  assign io_dbg_dma_dbg_ib_dbg_cmd_write = io_dbg_dec_dbg_ib_dbg_cmd_write; // @[dbg.scala 455:39]
+  assign io_dbg_dma_dbg_ib_dbg_cmd_type = io_dbg_dec_dbg_ib_dbg_cmd_type; // @[dbg.scala 456:39]
+  assign io_dbg_dma_dbg_ib_dbg_cmd_addr = io_dbg_dec_dbg_ib_dbg_cmd_addr; // @[dbg.scala 452:39]
+  assign io_dbg_dma_dbg_dctl_dbg_cmd_wrdata = io_dbg_dec_dbg_dctl_dbg_cmd_wrdata; // @[dbg.scala 453:39]
+  assign io_dbg_dma_io_dbg_dma_bubble = _T_482 | _T_283; // @[dbg.scala 335:32]
+  assign dbg_state = _T_468; // @[dbg.scala 320:13]
+  assign dbg_state_en = _T_300 ? _T_312 : _GEN_34; // @[dbg.scala 263:16 dbg.scala 271:20 dbg.scala 276:20 dbg.scala 283:20 dbg.scala 292:20 dbg.scala 297:20 dbg.scala 302:20 dbg.scala 309:20]
+  assign sb_state = _T_547; // @[dbg.scala 402:12]
+  assign sb_state_en = _T_502 ? _T_505 : _GEN_101; // @[dbg.scala 348:19 dbg.scala 356:19 dbg.scala 362:19 dbg.scala 368:19 dbg.scala 372:19 dbg.scala 376:19 dbg.scala 380:19 dbg.scala 384:19 dbg.scala 390:19 dbg.scala 396:19]
+  assign dmcontrol_reg = {_T_145,_T_143}; // @[dbg.scala 183:17]
+  assign sbaddress0_reg = _T_118; // @[dbg.scala 164:18]
+  assign sbcs_sbbusy_wren = _T_502 ? sb_state_en : _GEN_104; // @[dbg.scala 340:20 dbg.scala 349:24 dbg.scala 397:24]
+  assign sbcs_sberror_wren = _T_502 ? _T_508 : _GEN_102; // @[dbg.scala 342:21 dbg.scala 351:25 dbg.scala 357:25 dbg.scala 363:25 dbg.scala 385:25 dbg.scala 391:25]
+  assign sb_bus_rdata = _T_671 | _T_677; // @[dbg.scala 446:16]
+  assign sbaddress0_reg_wren1 = _T_502 ? 1'h0 : _GEN_106; // @[dbg.scala 344:24 dbg.scala 399:28]
+  assign dmstatus_reg = {_T_163,_T_159}; // @[dbg.scala 189:16]
+  assign dmstatus_havereset = _T_192; // @[dbg.scala 206:22]
+  assign dmstatus_resumeack = _T_185; // @[dbg.scala 198:22]
+  assign dmstatus_unavail = dmcontrol_reg[1] | _T_180; // @[dbg.scala 196:20]
+  assign dmstatus_running = ~_T_183; // @[dbg.scala 197:20]
+  assign dmstatus_halted = _T_188; // @[dbg.scala 202:19]
+  assign abstractcs_busy_wren = _T_300 ? 1'h0 : _GEN_36; // @[dbg.scala 264:24 dbg.scala 285:28 dbg.scala 303:28]
+  assign sb_bus_cmd_read = io_sb_axi_ar_valid & io_sb_axi_ar_ready; // @[dbg.scala 406:19]
+  assign sb_bus_cmd_write_addr = io_sb_axi_aw_valid & io_sb_axi_aw_ready; // @[dbg.scala 407:25]
+  assign sb_bus_cmd_write_data = io_sb_axi_w_valid & io_sb_axi_w_ready; // @[dbg.scala 408:25]
+  assign sb_bus_rsp_read = io_sb_axi_r_valid & io_sb_axi_r_ready; // @[dbg.scala 409:19]
+  assign sb_bus_rsp_error = _T_555 | _T_558; // @[dbg.scala 411:20]
+  assign sb_bus_rsp_write = io_sb_axi_b_valid & io_sb_axi_b_ready; // @[dbg.scala 410:20]
+  assign sbcs_sbbusy_din = 4'h0 == sb_state; // @[dbg.scala 341:19 dbg.scala 350:23 dbg.scala 398:23]
+  assign data1_reg = _T_299; // @[dbg.scala 257:13]
+  assign sbcs_reg = {_T_44,_T_40}; // @[dbg.scala 130:12]
+  assign rvclkhdr_io_clk = clock; // @[lib.scala 344:17]
+  assign rvclkhdr_io_en = _T_3 | io_clk_override; // @[lib.scala 345:16]
+  assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
+  assign rvclkhdr_1_io_clk = clock; // @[lib.scala 344:17]
+  assign rvclkhdr_1_io_en = _T_6 | io_clk_override; // @[lib.scala 345:16]
+  assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
+  assign rvclkhdr_2_io_clk = clock; // @[lib.scala 370:18]
+  assign rvclkhdr_2_io_en = sbdata0_reg_wren0 | sbdata0_reg_wren1; // @[lib.scala 371:17]
+  assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
+  assign rvclkhdr_3_io_clk = clock; // @[lib.scala 370:18]
+  assign rvclkhdr_3_io_en = sbdata1_reg_wren0 | sbdata0_reg_wren1; // @[lib.scala 371:17]
+  assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
+  assign rvclkhdr_4_io_clk = clock; // @[lib.scala 370:18]
+  assign rvclkhdr_4_io_en = sbaddress0_reg_wren0 | sbaddress0_reg_wren1; // @[lib.scala 371:17]
+  assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
+  assign abstractcs_reg = {_T_267,_T_265}; // @[dbg.scala 238:18]
+  assign rvclkhdr_5_io_clk = clock; // @[lib.scala 370:18]
+  assign rvclkhdr_5_io_en = _T_217 & _T_272; // @[lib.scala 371:17]
+  assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
+  assign rvclkhdr_6_io_clk = clock; // @[lib.scala 370:18]
+  assign rvclkhdr_6_io_en = data0_reg_wren0 | data0_reg_wren1; // @[lib.scala 371:17]
+  assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
+  assign rvclkhdr_7_io_clk = clock; // @[lib.scala 370:18]
+  assign rvclkhdr_7_io_en = _T_295 & _T_272; // @[lib.scala 371:17]
+  assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
+  assign dbg_nxtstate = _T_300 ? _T_303 : _GEN_33; // @[dbg.scala 262:16 dbg.scala 270:20 dbg.scala 275:20 dbg.scala 280:20 dbg.scala 291:20 dbg.scala 296:20 dbg.scala 301:20 dbg.scala 308:20]
 `ifdef RANDOMIZE_GARBAGE_ASSIGN
 `define RANDOMIZE
 `endif
@@ -804,7 +804,7 @@ initial begin
   _RAND_6 = {1{`RANDOM}};
   sbdata1_reg = _RAND_6[31:0];
   _RAND_7 = {1{`RANDOM}};
-  _T_121 = _RAND_7[31:0];
+  _T_118 = _RAND_7[31:0];
   _RAND_8 = {1{`RANDOM}};
   dm_temp = _RAND_8[3:0];
   _RAND_9 = {1{`RANDOM}};
@@ -812,11 +812,11 @@ initial begin
   _RAND_10 = {1{`RANDOM}};
   dmcontrol_wren_Q = _RAND_10[0:0];
   _RAND_11 = {1{`RANDOM}};
-  _T_191 = _RAND_11[0:0];
+  _T_185 = _RAND_11[0:0];
   _RAND_12 = {1{`RANDOM}};
-  _T_195 = _RAND_12[0:0];
+  _T_188 = _RAND_12[0:0];
   _RAND_13 = {1{`RANDOM}};
-  _T_200 = _RAND_13[0:0];
+  _T_192 = _RAND_13[0:0];
   _RAND_14 = {1{`RANDOM}};
   abs_temp_12 = _RAND_14[0:0];
   _RAND_15 = {1{`RANDOM}};
@@ -826,79 +826,79 @@ initial begin
   _RAND_17 = {1{`RANDOM}};
   data0_reg = _RAND_17[31:0];
   _RAND_18 = {1{`RANDOM}};
-  _T_312 = _RAND_18[31:0];
+  _T_299 = _RAND_18[31:0];
   _RAND_19 = {1{`RANDOM}};
-  _T_483 = _RAND_19[2:0];
+  _T_468 = _RAND_19[2:0];
   _RAND_20 = {1{`RANDOM}};
-  _T_485 = _RAND_20[31:0];
+  _T_469 = _RAND_20[31:0];
   _RAND_21 = {1{`RANDOM}};
-  _T_564 = _RAND_21[3:0];
+  _T_547 = _RAND_21[3:0];
 `endif // RANDOMIZE_REG_INIT
-  if (_T_29) begin
+  if (dbg_dm_rst_l) begin
     temp_sbcs_22 = 1'h0;
   end
-  if (_T_29) begin
+  if (dbg_dm_rst_l) begin
     temp_sbcs_21 = 1'h0;
   end
-  if (_T_29) begin
+  if (dbg_dm_rst_l) begin
     temp_sbcs_20 = 1'h0;
   end
-  if (_T_29) begin
+  if (dbg_dm_rst_l) begin
     temp_sbcs_19_15 = 5'h0;
   end
-  if (_T_36) begin
+  if (rst_not) begin
     temp_sbcs_14_12 = 3'h0;
   end
-  if (_T_29) begin
+  if (dbg_dm_rst_l) begin
     sbdata0_reg = 32'h0;
   end
-  if (_T_29) begin
+  if (dbg_dm_rst_l) begin
     sbdata1_reg = 32'h0;
   end
-  if (_T_29) begin
-    _T_121 = 32'h0;
+  if (dbg_dm_rst_l) begin
+    _T_118 = 32'h0;
   end
-  if (_T_29) begin
+  if (dbg_dm_rst_l) begin
     dm_temp = 4'h0;
   end
   if (io_dbg_rst_l) begin
     dm_temp_0 = 1'h0;
   end
-  if (_T_29) begin
+  if (dbg_dm_rst_l) begin
     dmcontrol_wren_Q = 1'h0;
   end
-  if (_T_29) begin
-    _T_191 = 1'h0;
+  if (dbg_dm_rst_l) begin
+    _T_185 = 1'h0;
   end
-  if (_T_29) begin
-    _T_195 = 1'h0;
+  if (dbg_dm_rst_l) begin
+    _T_188 = 1'h0;
   end
-  if (_T_29) begin
-    _T_200 = 1'h0;
+  if (dbg_dm_rst_l) begin
+    _T_192 = 1'h0;
   end
-  if (_T_29) begin
+  if (dbg_dm_rst_l) begin
     abs_temp_12 = 1'h0;
   end
-  if (_T_29) begin
+  if (dbg_dm_rst_l) begin
     abs_temp_10_8 = 3'h0;
   end
-  if (_T_29) begin
+  if (dbg_dm_rst_l) begin
     command_reg = 32'h0;
   end
-  if (_T_29) begin
+  if (dbg_dm_rst_l) begin
     data0_reg = 32'h0;
   end
-  if (_T_29) begin
-    _T_312 = 32'h0;
+  if (dbg_dm_rst_l) begin
+    _T_299 = 32'h0;
   end
-  if (_T_482) begin
-    _T_483 = 3'h0;
+  if (rst_temp) begin
+    _T_468 = 3'h0;
   end
-  if (_T_29) begin
-    _T_485 = 32'h0;
+  if (dbg_dm_rst_l) begin
+    _T_469 = 32'h0;
   end
-  if (_T_29) begin
-    _T_564 = 4'h0;
+  if (dbg_dm_rst_l) begin
+    _T_547 = 4'h0;
   end
   `endif // RANDOMIZE
 end // initial
@@ -906,95 +906,95 @@ end // initial
 `FIRRTL_AFTER_INITIAL
 `endif
 `endif // SYNTHESIS
-  always @(posedge rvclkhdr_1_io_l1clk or posedge _T_29) begin
-    if (_T_29) begin
+  always @(posedge rvclkhdr_1_io_l1clk or posedge dbg_dm_rst_l) begin
+    if (dbg_dm_rst_l) begin
       temp_sbcs_22 <= 1'h0;
     end else if (sbcs_sbbusyerror_wren) begin
       temp_sbcs_22 <= sbcs_sbbusyerror_din;
     end
   end
-  always @(posedge rvclkhdr_1_io_l1clk or posedge _T_29) begin
-    if (_T_29) begin
+  always @(posedge rvclkhdr_1_io_l1clk or posedge dbg_dm_rst_l) begin
+    if (dbg_dm_rst_l) begin
       temp_sbcs_21 <= 1'h0;
     end else if (sbcs_sbbusy_wren) begin
       temp_sbcs_21 <= sbcs_sbbusy_din;
     end
   end
-  always @(posedge rvclkhdr_1_io_l1clk or posedge _T_29) begin
-    if (_T_29) begin
+  always @(posedge rvclkhdr_1_io_l1clk or posedge dbg_dm_rst_l) begin
+    if (dbg_dm_rst_l) begin
       temp_sbcs_20 <= 1'h0;
     end else if (sbcs_wren) begin
       temp_sbcs_20 <= io_dmi_reg_wdata[20];
     end
   end
-  always @(posedge rvclkhdr_1_io_l1clk or posedge _T_29) begin
-    if (_T_29) begin
+  always @(posedge rvclkhdr_1_io_l1clk or posedge dbg_dm_rst_l) begin
+    if (dbg_dm_rst_l) begin
       temp_sbcs_19_15 <= 5'h0;
     end else if (sbcs_wren) begin
       temp_sbcs_19_15 <= io_dmi_reg_wdata[19:15];
     end
   end
-  always @(posedge rvclkhdr_1_io_l1clk or posedge _T_36) begin
-    if (_T_36) begin
+  always @(posedge rvclkhdr_1_io_l1clk or posedge rst_not) begin
+    if (rst_not) begin
       temp_sbcs_14_12 <= 3'h0;
     end else if (sbcs_sberror_wren) begin
-      if (_T_518) begin
-        temp_sbcs_14_12 <= _T_528;
+      if (_T_502) begin
+        temp_sbcs_14_12 <= _T_512;
+      end else if (_T_513) begin
+        if (sbcs_unaligned) begin
+          temp_sbcs_14_12 <= 3'h3;
+        end else begin
+          temp_sbcs_14_12 <= 3'h4;
+        end
+      end else if (_T_520) begin
+        if (sbcs_unaligned) begin
+          temp_sbcs_14_12 <= 3'h3;
+        end else begin
+          temp_sbcs_14_12 <= 3'h4;
+        end
+      end else if (_T_527) begin
+        temp_sbcs_14_12 <= 3'h0;
       end else if (_T_529) begin
-        if (sbcs_unaligned) begin
-          temp_sbcs_14_12 <= 3'h3;
-        end else begin
-          temp_sbcs_14_12 <= 3'h4;
-        end
-      end else if (_T_536) begin
-        if (sbcs_unaligned) begin
-          temp_sbcs_14_12 <= 3'h3;
-        end else begin
-          temp_sbcs_14_12 <= 3'h4;
-        end
-      end else if (_T_543) begin
         temp_sbcs_14_12 <= 3'h0;
-      end else if (_T_545) begin
+      end else if (_T_535) begin
         temp_sbcs_14_12 <= 3'h0;
-      end else if (_T_551) begin
+      end else if (_T_537) begin
         temp_sbcs_14_12 <= 3'h0;
-      end else if (_T_553) begin
-        temp_sbcs_14_12 <= 3'h0;
-      end else if (_T_555) begin
+      end else if (_T_539) begin
         temp_sbcs_14_12 <= 3'h2;
-      end else if (_T_558) begin
+      end else if (_T_542) begin
         temp_sbcs_14_12 <= 3'h2;
       end else begin
         temp_sbcs_14_12 <= 3'h0;
       end
     end
   end
-  always @(posedge rvclkhdr_2_io_l1clk or posedge _T_29) begin
-    if (_T_29) begin
+  always @(posedge rvclkhdr_2_io_l1clk or posedge dbg_dm_rst_l) begin
+    if (dbg_dm_rst_l) begin
       sbdata0_reg <= 32'h0;
     end else begin
       sbdata0_reg <= _T_95 | _T_99;
     end
   end
-  always @(posedge rvclkhdr_3_io_l1clk or posedge _T_29) begin
-    if (_T_29) begin
+  always @(posedge rvclkhdr_3_io_l1clk or posedge dbg_dm_rst_l) begin
+    if (dbg_dm_rst_l) begin
       sbdata1_reg <= 32'h0;
     end else begin
       sbdata1_reg <= _T_102 | _T_106;
     end
   end
-  always @(posedge rvclkhdr_4_io_l1clk or posedge _T_29) begin
-    if (_T_29) begin
-      _T_121 <= 32'h0;
+  always @(posedge rvclkhdr_4_io_l1clk or posedge dbg_dm_rst_l) begin
+    if (dbg_dm_rst_l) begin
+      _T_118 <= 32'h0;
     end else begin
-      _T_121 <= _T_113 | _T_119;
+      _T_118 <= _T_111 | _T_117;
     end
   end
-  always @(posedge rvclkhdr_io_l1clk or posedge _T_29) begin
-    if (_T_29) begin
+  always @(posedge rvclkhdr_io_l1clk or posedge dbg_dm_rst_l) begin
+    if (dbg_dm_rst_l) begin
       dm_temp <= 4'h0;
     end else if (dmcontrol_wren) begin
-      dm_temp <= _T_140;
+      dm_temp <= _T_136;
     end
   end
   always @(posedge rvclkhdr_io_l1clk or posedge io_dbg_rst_l) begin
@@ -1004,177 +1004,177 @@ end // initial
       dm_temp_0 <= io_dmi_reg_wdata[0];
     end
   end
-  always @(posedge rvclkhdr_io_l1clk or posedge _T_29) begin
-    if (_T_29) begin
+  always @(posedge rvclkhdr_io_l1clk or posedge dbg_dm_rst_l) begin
+    if (dbg_dm_rst_l) begin
       dmcontrol_wren_Q <= 1'h0;
     end else begin
-      dmcontrol_wren_Q <= _T_134 & io_dmi_reg_wr_en;
+      dmcontrol_wren_Q <= _T_131 & io_dmi_reg_wr_en;
     end
   end
-  always @(posedge rvclkhdr_io_l1clk or posedge _T_29) begin
-    if (_T_29) begin
-      _T_191 <= 1'h0;
+  always @(posedge rvclkhdr_io_l1clk or posedge dbg_dm_rst_l) begin
+    if (dbg_dm_rst_l) begin
+      _T_185 <= 1'h0;
     end else if (dmstatus_resumeack_wren) begin
-      _T_191 <= _T_171;
+      _T_185 <= _T_166;
     end
   end
-  always @(posedge rvclkhdr_io_l1clk or posedge _T_29) begin
-    if (_T_29) begin
-      _T_195 <= 1'h0;
+  always @(posedge rvclkhdr_io_l1clk or posedge dbg_dm_rst_l) begin
+    if (dbg_dm_rst_l) begin
+      _T_188 <= 1'h0;
     end else begin
-      _T_195 <= io_dec_tlu_dbg_halted & _T_193;
+      _T_188 <= io_dec_tlu_dbg_halted & _T_186;
     end
   end
-  always @(posedge rvclkhdr_io_l1clk or posedge _T_29) begin
-    if (_T_29) begin
-      _T_200 <= 1'h0;
+  always @(posedge rvclkhdr_io_l1clk or posedge dbg_dm_rst_l) begin
+    if (dbg_dm_rst_l) begin
+      _T_192 <= 1'h0;
     end else begin
-      _T_200 <= _T_197 & _T_198;
+      _T_192 <= _T_189 & _T_190;
     end
   end
-  always @(posedge rvclkhdr_io_l1clk or posedge _T_29) begin
-    if (_T_29) begin
+  always @(posedge rvclkhdr_io_l1clk or posedge dbg_dm_rst_l) begin
+    if (dbg_dm_rst_l) begin
       abs_temp_12 <= 1'h0;
     end else if (abstractcs_busy_wren) begin
-      if (_T_313) begin
+      if (_T_300) begin
         abs_temp_12 <= 1'h0;
-      end else if (_T_331) begin
+      end else if (_T_318) begin
         abs_temp_12 <= 1'h0;
       end else begin
-        abs_temp_12 <= _T_343;
+        abs_temp_12 <= _T_330;
       end
     end
   end
-  always @(posedge rvclkhdr_io_l1clk or posedge _T_29) begin
-    if (_T_29) begin
+  always @(posedge rvclkhdr_io_l1clk or posedge dbg_dm_rst_l) begin
+    if (dbg_dm_rst_l) begin
       abs_temp_10_8 <= 3'h0;
     end else begin
-      abs_temp_10_8 <= _T_266 | _T_271;
+      abs_temp_10_8 <= _T_258 | _T_263;
     end
   end
-  always @(posedge rvclkhdr_5_io_l1clk or posedge _T_29) begin
-    if (_T_29) begin
+  always @(posedge rvclkhdr_5_io_l1clk or posedge dbg_dm_rst_l) begin
+    if (dbg_dm_rst_l) begin
       command_reg <= 32'h0;
     end else begin
-      command_reg <= {_T_288,_T_286};
+      command_reg <= {_T_278,_T_276};
     end
   end
-  always @(posedge rvclkhdr_6_io_l1clk or posedge _T_29) begin
-    if (_T_29) begin
+  always @(posedge rvclkhdr_6_io_l1clk or posedge dbg_dm_rst_l) begin
+    if (dbg_dm_rst_l) begin
       data0_reg <= 32'h0;
     end else begin
-      data0_reg <= _T_300 | _T_303;
+      data0_reg <= _T_289 | _T_292;
     end
   end
-  always @(posedge rvclkhdr_7_io_l1clk or posedge _T_29) begin
-    if (_T_29) begin
-      _T_312 <= 32'h0;
+  always @(posedge rvclkhdr_7_io_l1clk or posedge dbg_dm_rst_l) begin
+    if (dbg_dm_rst_l) begin
+      _T_299 <= 32'h0;
     end else begin
-      _T_312 <= _T_310 & io_dmi_reg_wdata;
+      _T_299 <= _T_298 & io_dmi_reg_wdata;
     end
   end
-  always @(posedge rvclkhdr_io_l1clk or posedge _T_482) begin
-    if (_T_482) begin
-      _T_483 <= 3'h0;
+  always @(posedge rvclkhdr_io_l1clk or posedge rst_temp) begin
+    if (rst_temp) begin
+      _T_468 <= 3'h0;
     end else if (dbg_state_en) begin
-      if (_T_313) begin
-        if (_T_315) begin
-          _T_483 <= 3'h2;
+      if (_T_300) begin
+        if (_T_302) begin
+          _T_468 <= 3'h2;
         end else begin
-          _T_483 <= 3'h1;
+          _T_468 <= 3'h1;
         end
-      end else if (_T_331) begin
+      end else if (_T_318) begin
         if (dmcontrol_reg[1]) begin
-          _T_483 <= 3'h0;
+          _T_468 <= 3'h0;
         end else begin
-          _T_483 <= 3'h2;
+          _T_468 <= 3'h2;
         end
-      end else if (_T_343) begin
-        if (_T_347) begin
-          if (_T_351) begin
-            _T_483 <= 3'h6;
+      end else if (_T_330) begin
+        if (_T_334) begin
+          if (_T_338) begin
+            _T_468 <= 3'h6;
           end else begin
-            _T_483 <= 3'h3;
+            _T_468 <= 3'h3;
           end
         end else if (dmcontrol_reg[31]) begin
-          _T_483 <= 3'h1;
+          _T_468 <= 3'h1;
         end else begin
-          _T_483 <= 3'h0;
+          _T_468 <= 3'h0;
         end
-      end else if (_T_381) begin
+      end else if (_T_368) begin
         if (dmcontrol_reg[1]) begin
-          _T_483 <= 3'h0;
-        end else if (_T_384) begin
-          _T_483 <= 3'h5;
+          _T_468 <= 3'h0;
+        end else if (_T_371) begin
+          _T_468 <= 3'h5;
         end else begin
-          _T_483 <= 3'h4;
+          _T_468 <= 3'h4;
         end
-      end else if (_T_398) begin
+      end else if (_T_385) begin
         if (dmcontrol_reg[1]) begin
-          _T_483 <= 3'h0;
+          _T_468 <= 3'h0;
         end else begin
-          _T_483 <= 3'h5;
+          _T_468 <= 3'h5;
         end
-      end else if (_T_409) begin
+      end else if (_T_396) begin
         if (dmcontrol_reg[1]) begin
-          _T_483 <= 3'h0;
+          _T_468 <= 3'h0;
         end else begin
-          _T_483 <= 3'h2;
+          _T_468 <= 3'h2;
         end
       end else begin
-        _T_483 <= 3'h0;
+        _T_468 <= 3'h0;
       end
     end
   end
-  always @(posedge rvclkhdr_io_l1clk or posedge _T_29) begin
-    if (_T_29) begin
-      _T_485 <= 32'h0;
+  always @(posedge rvclkhdr_io_l1clk or posedge dbg_dm_rst_l) begin
+    if (dbg_dm_rst_l) begin
+      _T_469 <= 32'h0;
     end else if (io_dmi_reg_en) begin
-      _T_485 <= dmi_reg_rdata_din;
+      _T_469 <= dmi_reg_rdata_din;
     end
   end
-  always @(posedge rvclkhdr_1_io_l1clk or posedge _T_29) begin
-    if (_T_29) begin
-      _T_564 <= 4'h0;
+  always @(posedge rvclkhdr_1_io_l1clk or posedge dbg_dm_rst_l) begin
+    if (dbg_dm_rst_l) begin
+      _T_547 <= 4'h0;
     end else if (sb_state_en) begin
-      if (_T_518) begin
+      if (_T_502) begin
         if (sbdata0_reg_wren0) begin
-          _T_564 <= 4'h2;
+          _T_547 <= 4'h2;
         end else begin
-          _T_564 <= 4'h1;
+          _T_547 <= 4'h1;
         end
+      end else if (_T_513) begin
+        if (_T_514) begin
+          _T_547 <= 4'h9;
+        end else begin
+          _T_547 <= 4'h3;
+        end
+      end else if (_T_520) begin
+        if (_T_514) begin
+          _T_547 <= 4'h9;
+        end else begin
+          _T_547 <= 4'h4;
+        end
+      end else if (_T_527) begin
+        _T_547 <= 4'h7;
       end else if (_T_529) begin
         if (_T_530) begin
-          _T_564 <= 4'h9;
-        end else begin
-          _T_564 <= 4'h3;
-        end
-      end else if (_T_536) begin
-        if (_T_530) begin
-          _T_564 <= 4'h9;
-        end else begin
-          _T_564 <= 4'h4;
-        end
-      end else if (_T_543) begin
-        _T_564 <= 4'h7;
-      end else if (_T_545) begin
-        if (_T_546) begin
-          _T_564 <= 4'h8;
+          _T_547 <= 4'h8;
         end else if (sb_bus_cmd_write_data) begin
-          _T_564 <= 4'h5;
+          _T_547 <= 4'h5;
         end else begin
-          _T_564 <= 4'h6;
+          _T_547 <= 4'h6;
         end
-      end else if (_T_551) begin
-        _T_564 <= 4'h8;
-      end else if (_T_553) begin
-        _T_564 <= 4'h8;
-      end else if (_T_555) begin
-        _T_564 <= 4'h9;
-      end else if (_T_558) begin
-        _T_564 <= 4'h9;
+      end else if (_T_535) begin
+        _T_547 <= 4'h8;
+      end else if (_T_537) begin
+        _T_547 <= 4'h8;
+      end else if (_T_539) begin
+        _T_547 <= 4'h9;
+      end else if (_T_542) begin
+        _T_547 <= 4'h9;
       end else begin
-        _T_564 <= 4'h0;
+        _T_547 <= 4'h0;
       end
     end
   end
diff --git a/firrtl_black_box_resource_files.f b/firrtl_black_box_resource_files.f
index 40eae7ce..d4456bc6 100644
--- a/firrtl_black_box_resource_files.f
+++ b/firrtl_black_box_resource_files.f
@@ -1,3 +1 @@
-/home/waleedbinehsan/Desktop/Quasar/gated_latch.v
-/home/waleedbinehsan/Desktop/Quasar/dmi_wrapper.sv
-/home/waleedbinehsan/Desktop/Quasar/mem.sv
\ No newline at end of file
+/home/waleedbinehsan/Desktop/Quasar/gated_latch.v
\ No newline at end of file
diff --git a/src/main/scala/dbg/dbg.scala b/src/main/scala/dbg/dbg.scala
index a907348f..3b1687b4 100644
--- a/src/main/scala/dbg/dbg.scala
+++ b/src/main/scala/dbg/dbg.scala
@@ -96,30 +96,37 @@ class dbg extends Module with lib with RequireAsyncReset {
   val sb_free_clken = io.dmi_reg_en | sb_state_en | (sb_state =/= sb_state_t.sbidle) | io.clk_override;
   val dbg_free_clk = rvclkhdr(clock, dbg_free_clken, io.scan_mode) // dbg_free_cgc
   val sb_free_clk = rvclkhdr(clock, sb_free_clken, io.scan_mode) // sb_free_cgc
-  val dbg_dm_rst_l = io.dbg_rst_l.asBool() & (dmcontrol_reg(0) | io.scan_mode)
+
+  val dbg_dm_rst_l = (io.dbg_rst_l.asBool() & (dmcontrol_reg(0) | io.scan_mode)).asAsyncReset()
+  dontTouch(dbg_dm_rst_l)
+  val rst_temp = (dbg_dm_rst_l.asBool() & reset.asBool()).asAsyncReset()
+  dontTouch(rst_temp)
+  val rst_not = (!dbg_dm_rst_l.asBool).asAsyncReset()
+  dontTouch(rst_not)
+
   io.dbg_core_rst_l := (!dmcontrol_reg(1)).asBool()
   val sbcs_wren = (io.dmi_reg_addr === "h38".U) & io.dmi_reg_en & io.dmi_reg_wr_en & (sb_state === sb_state_t.sbidle)
   val sbcs_sbbusyerror_wren = (sbcs_wren & io.dmi_reg_wdata(22)) | ((sb_state =/= sb_state_t.sbidle) & io.dmi_reg_en &
     ((io.dmi_reg_addr === "h39".U) | (io.dmi_reg_addr === "h3c".U) | (io.dmi_reg_addr === "h3d".U)))
 
   val sbcs_sbbusyerror_din = (~(sbcs_wren & io.dmi_reg_wdata(22))).asUInt()
-  val temp_sbcs_22 = withClockAndReset(sb_free_clk, (dbg_dm_rst_l).asAsyncReset()) {
+  val temp_sbcs_22 = withClockAndReset(sb_free_clk, dbg_dm_rst_l) {
     RegEnable(sbcs_sbbusyerror_din, 0.U, sbcs_sbbusyerror_wren)
   } // sbcs_sbbusyerror_reg
 
-  val temp_sbcs_21 = withClockAndReset(sb_free_clk, (dbg_dm_rst_l).asAsyncReset()) {
+  val temp_sbcs_21 = withClockAndReset(sb_free_clk, dbg_dm_rst_l) {
     RegEnable(sbcs_sbbusy_din, 0.U, sbcs_sbbusy_wren)
   } // sbcs_sbbusy_reg
 
-  val temp_sbcs_20 = withClockAndReset(sb_free_clk, (dbg_dm_rst_l).asAsyncReset()) {
+  val temp_sbcs_20 = withClockAndReset(sb_free_clk, dbg_dm_rst_l) {
     RegEnable(io.dmi_reg_wdata(20), 0.U, sbcs_wren)
   } // sbcs_sbreadonaddr_reg
 
-  val temp_sbcs_19_15 = withClockAndReset(sb_free_clk, (dbg_dm_rst_l).asAsyncReset()) {
+  val temp_sbcs_19_15 = withClockAndReset(sb_free_clk, dbg_dm_rst_l) {
     RegEnable(io.dmi_reg_wdata(19, 15), 0.U, sbcs_wren)
   } // sbcs_misc_reg
 
-  val temp_sbcs_14_12 = withClockAndReset(sb_free_clk, (!dbg_dm_rst_l).asAsyncReset()) {
+  val temp_sbcs_14_12 = withClockAndReset(sb_free_clk, rst_not) {
     RegEnable(sbcs_sberror_din(2, 0), 0.U, sbcs_sberror_wren)
   } // sbcs_error_reg
   sbcs_reg := Cat(1.U(3.W), 0.U(6.W), temp_sbcs_22, temp_sbcs_21, temp_sbcs_20, temp_sbcs_19_15, temp_sbcs_14_12, "h20".U(7.W), "b01111".U(5.W))
@@ -144,11 +151,11 @@ class dbg extends Module with lib with RequireAsyncReset {
   val sbdata1_din = Fill(32, sbdata1_reg_wren0) & io.dmi_reg_wdata |
     Fill(32, sbdata1_reg_wren1) & sb_bus_rdata(63, 32)
 
-  val sbdata0_reg = withReset((dbg_dm_rst_l).asAsyncReset()) {
+  val sbdata0_reg = withReset(dbg_dm_rst_l) {
     rvdffe(sbdata0_din, sbdata0_reg_wren, clock, io.scan_mode)
   } // dbg_sbdata0_reg
 
-  val sbdata1_reg = withReset((dbg_dm_rst_l).asAsyncReset()) {
+  val sbdata1_reg = withReset(dbg_dm_rst_l) {
     rvdffe(sbdata1_din, sbdata1_reg_wren, clock, io.scan_mode)
   } // dbg_sbdata1_reg
 
@@ -156,7 +163,7 @@ class dbg extends Module with lib with RequireAsyncReset {
   val sbaddress0_reg_wren = sbaddress0_reg_wren0 | sbaddress0_reg_wren1
   val sbaddress0_reg_din = Fill(32, sbaddress0_reg_wren0) & io.dmi_reg_wdata |
     Fill(32, sbaddress0_reg_wren1) & (sbaddress0_reg + Cat(0.U(28.W), sbaddress0_incr))
-  sbaddress0_reg := withReset((dbg_dm_rst_l).asAsyncReset()) {
+  sbaddress0_reg := withReset(dbg_dm_rst_l) {
     rvdffe(sbaddress0_reg_din, sbaddress0_reg_wren, clock, io.scan_mode)
   } // dbg_sbaddress0_reg
 
@@ -164,7 +171,7 @@ class dbg extends Module with lib with RequireAsyncReset {
   val sbreadondata_access = io.dmi_reg_en & !io.dmi_reg_wr_en & (io.dmi_reg_addr === "h3c".U) & sbcs_reg(15)
   val sbdata0wr_access = io.dmi_reg_en & io.dmi_reg_wr_en & (io.dmi_reg_addr === "h3c".U)
   val dmcontrol_wren = (io.dmi_reg_addr === "h10".U) & io.dmi_reg_en & io.dmi_reg_wr_en
-  val dm_temp = withClockAndReset(dbg_free_clk, (dbg_dm_rst_l).asAsyncReset()) {
+  val dm_temp = withClockAndReset(dbg_free_clk, dbg_dm_rst_l) {
     RegEnable(
       Cat(io.dmi_reg_wdata(31, 30), io.dmi_reg_wdata(28), io.dmi_reg_wdata(1)),
       0.U, dmcontrol_wren)
@@ -177,7 +184,7 @@ class dbg extends Module with lib with RequireAsyncReset {
   val temp = Cat(dm_temp(3, 2), 0.U, dm_temp(1), 0.U(26.W), dm_temp(0), dm_temp_0)
   dmcontrol_reg := temp
 
-  val dmcontrol_wren_Q = withClockAndReset(dbg_free_clk, (dbg_dm_rst_l).asAsyncReset()) {
+  val dmcontrol_wren_Q = withClockAndReset(dbg_free_clk, dbg_dm_rst_l) {
     RegNext(dmcontrol_wren, 0.U)
   } // dmcontrol_wrenff
 
@@ -190,15 +197,15 @@ class dbg extends Module with lib with RequireAsyncReset {
   val temp_rst = reset.asBool()
   dmstatus_unavail := (dmcontrol_reg(1) | !(temp_rst)).asBool()
   dmstatus_running := ~(dmstatus_unavail | dmstatus_halted)
-  dmstatus_resumeack := withClockAndReset(dbg_free_clk, (dbg_dm_rst_l).asAsyncReset()) {
+  dmstatus_resumeack := withClockAndReset(dbg_free_clk, dbg_dm_rst_l) {
     RegEnable(dmstatus_resumeack_din, 0.U, dmstatus_resumeack_wren)
   } // dmstatus_resumeack_reg
 
-  dmstatus_halted := withClockAndReset(dbg_free_clk, (dbg_dm_rst_l).asAsyncReset()) {
+  dmstatus_halted := withClockAndReset(dbg_free_clk, dbg_dm_rst_l) {
     RegNext(io.dec_tlu_dbg_halted & !io.dec_tlu_mpc_halted_only, 0.U)
   } // dmstatus_halted_reg
 
-  dmstatus_havereset := withClockAndReset(dbg_free_clk, (dbg_dm_rst_l).asAsyncReset()) {
+  dmstatus_havereset := withClockAndReset(dbg_free_clk, dbg_dm_rst_l) {
     RegNext(Mux(dmstatus_havereset_wren, true.B, dmstatus_havereset) & !dmstatus_havereset_rst, false.B)
   } // dmstatus_havereset_reg
 
@@ -222,11 +229,11 @@ class dbg extends Module with lib with RequireAsyncReset {
     (Fill(3, abstractcs_error_sel5) & (~io.dmi_reg_wdata(10, 8)).asUInt() & abstractcs_reg(10, 8)) |
     (Fill(3, (~abstractcs_error_selor).asUInt()) & abstractcs_reg(10, 8))
 
-  val abs_temp_12 = withClockAndReset(dbg_free_clk, (dbg_dm_rst_l).asAsyncReset()) {
+  val abs_temp_12 = withClockAndReset(dbg_free_clk, dbg_dm_rst_l) {
     RegEnable(abstractcs_busy_din, 0.U, abstractcs_busy_wren)
   } // dmabstractcs_busy_reg
 
-  val abs_temp_10_8 = withClockAndReset(dbg_free_clk, (dbg_dm_rst_l).asAsyncReset()) {
+  val abs_temp_10_8 = withClockAndReset(dbg_free_clk, dbg_dm_rst_l) {
     RegNext(abstractcs_error_din(2, 0), 0.U)
   } // dmabstractcs_error_reg
 
@@ -234,7 +241,7 @@ class dbg extends Module with lib with RequireAsyncReset {
 
   val command_wren = (io.dmi_reg_addr === "h17".U) & io.dmi_reg_en & io.dmi_reg_wr_en & (dbg_state === state_t.halted)
   val command_din = Cat(io.dmi_reg_wdata(31, 24), 0.U(1.W), io.dmi_reg_wdata(22, 20), 0.U(3.W), io.dmi_reg_wdata(16, 0))
-  val command_reg = withReset((dbg_dm_rst_l).asAsyncReset()) {
+  val command_reg = withReset(dbg_dm_rst_l) {
     rvdffe(command_din, command_wren,clock,io.scan_mode)
   } // dmcommand_reg
 
@@ -243,13 +250,13 @@ class dbg extends Module with lib with RequireAsyncReset {
 
   val data0_reg_wren = data0_reg_wren0 | data0_reg_wren1
   val data0_din = Fill(32, data0_reg_wren0) & io.dmi_reg_wdata | Fill(32, data0_reg_wren1) & io.core_dbg_rddata
-  val data0_reg = withReset((dbg_dm_rst_l).asAsyncReset()) {
+  val data0_reg = withReset(dbg_dm_rst_l) {
     rvdffe(data0_din,data0_reg_wren,clock,io.scan_mode)
   } // dbg_data0_reg
 
   val data1_reg_wren = (io.dmi_reg_en & io.dmi_reg_wr_en & (io.dmi_reg_addr === "h5".U) & (dbg_state === state_t.halted))
   val data1_din = Fill(32, data1_reg_wren) & io.dmi_reg_wdata
-  data1_reg := withReset((dbg_dm_rst_l).asAsyncReset()) {
+  data1_reg := withReset(dbg_dm_rst_l) {
     rvdffe(data1_din, data1_reg_wren, clock, io.scan_mode)
   } // dbg_data1_reg
 
@@ -312,12 +319,12 @@ class dbg extends Module with lib with RequireAsyncReset {
     Fill(32, io.dmi_reg_addr === "h39".U) & sbaddress0_reg | Fill(32, io.dmi_reg_addr === "h3c".U) & sbdata0_reg |
     Fill(32, io.dmi_reg_addr === "h3d".U) & sbdata1_reg
 
-  dbg_state := withClockAndReset(dbg_free_clk, (dbg_dm_rst_l & temp_rst).asAsyncReset()) {
+  dbg_state := withClockAndReset(dbg_free_clk, rst_temp) {
     RegEnable(dbg_nxtstate, 0.U, dbg_state_en)
   } // dbg_state_reg
 
 
-  io.dmi_reg_rdata := withClockAndReset(dbg_free_clk, (dbg_dm_rst_l).asAsyncReset()) {
+  io.dmi_reg_rdata := withClockAndReset(dbg_free_clk, dbg_dm_rst_l) {
     RegEnable(dmi_reg_rdata_din, 0.U, io.dmi_reg_en)
   } // dmi_rddata_reg
 
@@ -394,7 +401,7 @@ class dbg extends Module with lib with RequireAsyncReset {
       sbaddress0_reg_wren1 := sbcs_reg(16)
     }}
 
-  sb_state := withClockAndReset(sb_free_clk, (dbg_dm_rst_l).asAsyncReset()) {
+  sb_state := withClockAndReset(sb_free_clk, dbg_dm_rst_l) {
     RegEnable(sb_nxtstate, 0.U, sb_state_en)
   } // sb_state_reg
 
@@ -450,3 +457,6 @@ class dbg extends Module with lib with RequireAsyncReset {
   io.dbg_dma.dbg_ib.dbg_cmd_write     := io.dbg_dec.dbg_ib.dbg_cmd_write
   io.dbg_dma.dbg_ib.dbg_cmd_type      := io.dbg_dec.dbg_ib.dbg_cmd_type
 }
+object db_obj extends App {
+  println((new chisel3.stage.ChiselStage).emitVerilog(new dbg()))
+}
\ No newline at end of file
diff --git a/target/scala-2.12/classes/dbg/db_obj$.class b/target/scala-2.12/classes/dbg/db_obj$.class
new file mode 100644
index 00000000..8110ad6b
Binary files /dev/null and b/target/scala-2.12/classes/dbg/db_obj$.class differ
diff --git a/target/scala-2.12/classes/dbg/db_obj$delayedInit$body.class b/target/scala-2.12/classes/dbg/db_obj$delayedInit$body.class
new file mode 100644
index 00000000..80df1bf3
Binary files /dev/null and b/target/scala-2.12/classes/dbg/db_obj$delayedInit$body.class differ
diff --git a/target/scala-2.12/classes/dbg/db_obj.class b/target/scala-2.12/classes/dbg/db_obj.class
new file mode 100644
index 00000000..96d88f99
Binary files /dev/null and b/target/scala-2.12/classes/dbg/db_obj.class differ
diff --git a/target/scala-2.12/classes/dbg/dbg.class b/target/scala-2.12/classes/dbg/dbg.class
index f0fe16c7..054a293d 100644
Binary files a/target/scala-2.12/classes/dbg/dbg.class and b/target/scala-2.12/classes/dbg/dbg.class differ