Create rvjtag_tap.v
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laraibkhan-lm
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// SPDX-License-Identifier: Apache-2.0
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// Copyright 2019 Western Digital Corporation or it's affiliates.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License
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module rvjtag_tap #(
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parameter AWIDTH = 7
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)
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(
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input trst,
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input tck,
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input tms,
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input tdi,
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output reg tdo,
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output tdoEnable,
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output [31:0] wr_data,
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output [AWIDTH-1:0] wr_addr,
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output wr_en,
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output rd_en,
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input [31:0] rd_data,
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input [1:0] rd_status,
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output reg dmi_reset,
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output reg dmi_hard_reset,
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input [2:0] idle,
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input [1:0] dmi_stat,
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/*
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-- revisionCode : 4'h0;
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-- manufacturersIdCode : 11'h45;
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-- deviceIdCode : 16'h0001;
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-- order MSB .. LSB -> [4 bit version or revision] [16 bit part number] [11 bit manufacturer id] [value of 1'b1 in LSB]
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*/
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input [31:1] jtag_id,
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input [3:0] version
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);
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localparam USER_DR_LENGTH = AWIDTH + 34;
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reg [USER_DR_LENGTH-1:0] sr, nsr, dr;
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///////////////////////////////////////////////////////
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// Tap controller
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///////////////////////////////////////////////////////
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logic[3:0] state, nstate;
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logic [4:0] ir;
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wire jtag_reset;
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wire shift_dr;
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wire pause_dr;
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wire update_dr;
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wire capture_dr;
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wire shift_ir;
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wire pause_ir ;
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wire update_ir ;
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wire capture_ir;
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wire[1:0] dr_en;
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wire devid_sel;
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wire [5:0] abits;
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assign abits = AWIDTH[5:0];
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localparam TEST_LOGIC_RESET_STATE = 0;
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localparam RUN_TEST_IDLE_STATE = 1;
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localparam SELECT_DR_SCAN_STATE = 2;
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localparam CAPTURE_DR_STATE = 3;
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localparam SHIFT_DR_STATE = 4;
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localparam EXIT1_DR_STATE = 5;
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localparam PAUSE_DR_STATE = 6;
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localparam EXIT2_DR_STATE = 7;
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localparam UPDATE_DR_STATE = 8;
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localparam SELECT_IR_SCAN_STATE = 9;
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localparam CAPTURE_IR_STATE = 10;
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localparam SHIFT_IR_STATE = 11;
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localparam EXIT1_IR_STATE = 12;
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localparam PAUSE_IR_STATE = 13;
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localparam EXIT2_IR_STATE = 14;
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localparam UPDATE_IR_STATE = 15;
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always_comb begin
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nstate = state;
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case(state)
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TEST_LOGIC_RESET_STATE: nstate = tms ? TEST_LOGIC_RESET_STATE : RUN_TEST_IDLE_STATE;
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RUN_TEST_IDLE_STATE: nstate = tms ? SELECT_DR_SCAN_STATE : RUN_TEST_IDLE_STATE;
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SELECT_DR_SCAN_STATE: nstate = tms ? SELECT_IR_SCAN_STATE : CAPTURE_DR_STATE;
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CAPTURE_DR_STATE: nstate = tms ? EXIT1_DR_STATE : SHIFT_DR_STATE;
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SHIFT_DR_STATE: nstate = tms ? EXIT1_DR_STATE : SHIFT_DR_STATE;
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EXIT1_DR_STATE: nstate = tms ? UPDATE_DR_STATE : PAUSE_DR_STATE;
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PAUSE_DR_STATE: nstate = tms ? EXIT2_DR_STATE : PAUSE_DR_STATE;
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EXIT2_DR_STATE: nstate = tms ? UPDATE_DR_STATE : SHIFT_DR_STATE;
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UPDATE_DR_STATE: nstate = tms ? SELECT_DR_SCAN_STATE : RUN_TEST_IDLE_STATE;
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SELECT_IR_SCAN_STATE: nstate = tms ? TEST_LOGIC_RESET_STATE : CAPTURE_IR_STATE;
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CAPTURE_IR_STATE: nstate = tms ? EXIT1_IR_STATE : SHIFT_IR_STATE;
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SHIFT_IR_STATE: nstate = tms ? EXIT1_IR_STATE : SHIFT_IR_STATE;
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EXIT1_IR_STATE: nstate = tms ? UPDATE_IR_STATE : PAUSE_IR_STATE;
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PAUSE_IR_STATE: nstate = tms ? EXIT2_IR_STATE : PAUSE_IR_STATE;
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EXIT2_IR_STATE: nstate = tms ? UPDATE_IR_STATE : SHIFT_IR_STATE;
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UPDATE_IR_STATE: nstate = tms ? SELECT_DR_SCAN_STATE : RUN_TEST_IDLE_STATE;
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default: nstate = TEST_LOGIC_RESET_STATE;
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endcase
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end
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always @ (posedge tck or negedge trst) begin
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if(!trst) state <= TEST_LOGIC_RESET_STATE;
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else state <= nstate;
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end
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assign jtag_reset = state == TEST_LOGIC_RESET_STATE;
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assign shift_dr = state == SHIFT_DR_STATE;
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assign pause_dr = state == PAUSE_DR_STATE;
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assign update_dr = state == UPDATE_DR_STATE;
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assign capture_dr = state == CAPTURE_DR_STATE;
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assign shift_ir = state == SHIFT_IR_STATE;
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assign pause_ir = state == PAUSE_IR_STATE;
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assign update_ir = state == UPDATE_IR_STATE;
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assign capture_ir = state == CAPTURE_IR_STATE;
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assign tdoEnable = shift_dr | shift_ir;
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///////////////////////////////////////////////////////
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// IR register
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///////////////////////////////////////////////////////
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always @ (negedge tck or negedge trst) begin
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if (!trst) ir <= 5'b1;
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else begin
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if (jtag_reset) ir <= 5'b1;
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else if (update_ir) ir <= (sr[4:0] == '0) ? 5'h1f :sr[4:0];
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end
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end
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assign devid_sel = ir == 5'b00001;
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assign dr_en[0] = ir == 5'b10000;
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assign dr_en[1] = ir == 5'b10001;
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///////////////////////////////////////////////////////
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// Shift register
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///////////////////////////////////////////////////////
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always @ (posedge tck or negedge trst) begin
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if(!trst)begin
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sr <= '0;
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end
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else begin
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sr <= nsr;
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end
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end
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// SR next value
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always_comb begin
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nsr = sr;
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case(1)
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shift_dr: begin
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case(1)
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dr_en[1]: nsr = {tdi, sr[USER_DR_LENGTH-1:1]};
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dr_en[0],
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devid_sel: nsr = {{USER_DR_LENGTH-32{1'b0}},tdi, sr[31:1]};
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default: nsr = {{USER_DR_LENGTH-1{1'b0}},tdi}; // bypass
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endcase
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end
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capture_dr: begin
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case(1)
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dr_en[0]: nsr = {{USER_DR_LENGTH-15{1'b0}}, idle, dmi_stat, abits, version};
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dr_en[1]: nsr = {{AWIDTH{1'b0}}, rd_data, rd_status};
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devid_sel: nsr = {{USER_DR_LENGTH-32{1'b0}}, jtag_id, 1'b1};
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endcase
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end
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shift_ir: nsr = {{USER_DR_LENGTH-5{1'b0}},tdi, sr[4:1]};
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capture_ir: nsr = {{USER_DR_LENGTH-1{1'b0}},1'b1};
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endcase
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end
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// TDO retiming
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always @ (negedge tck ) tdo <= sr[0];
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// DMI CS register
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always @ (posedge tck or negedge trst) begin
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if(!trst) begin
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dmi_hard_reset <= 1'b0;
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dmi_reset <= 1'b0;
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end
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else if (update_dr & dr_en[0]) begin
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dmi_hard_reset <= sr[17];
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dmi_reset <= sr[16];
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end
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else begin
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dmi_hard_reset <= 1'b0;
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dmi_reset <= 1'b0;
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end
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end
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// DR register
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always @ (posedge tck or negedge trst) begin
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if(!trst)
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dr <= '0;
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else begin
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if (update_dr & dr_en[1])
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dr <= sr;
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else
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dr <= {dr[USER_DR_LENGTH-1:2],2'b0};
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end
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end
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assign {wr_addr, wr_data, wr_en, rd_en} = dr;
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endmodule
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