From ad3359da87f2f6a30473d476ac9d96c471f19e76 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E2=80=8BLaraib=20Khan?= <​laraib.khan@lampromellon.com> Date: Mon, 30 Nov 2020 15:08:22 +0500 Subject: [PATCH] lsu update --- axi4_to_ahb.fir | 2 +- axi4_to_ahb.v | 4 ++-- el2_swerv.fir | 6 +++--- el2_swerv.v | 4 ++-- src/main/scala/lib/axi4_to_ahb.scala | 2 +- .../classes/lib/axi4_to_ahb_IO.class | Bin 9408 -> 9408 bytes 6 files changed, 9 insertions(+), 9 deletions(-) diff --git a/axi4_to_ahb.fir b/axi4_to_ahb.fir index d895ef59..12f43bbe 100644 --- a/axi4_to_ahb.fir +++ b/axi4_to_ahb.fir @@ -147,7 +147,7 @@ circuit axi4_to_ahb : module axi4_to_ahb : input clock : Clock input reset : AsyncReset - output io : {flip scan_mode : UInt<1>, flip bus_clk_en : UInt<1>, flip clk_override : UInt<1>, flip axi_awvalid : UInt<1>, flip axi_awid : UInt<1>, flip axi_awaddr : UInt<32>, flip axi_awsize : UInt<3>, flip axi_awprot : UInt<3>, flip axi_wvalid : UInt<1>, flip axi_wdata : UInt<64>, flip axi_wstrb : UInt<8>, flip axi_wlast : UInt<1>, flip axi_bready : UInt<1>, flip axi_arvalid : UInt<1>, flip axi_arid : UInt<1>, flip axi_araddr : UInt<32>, flip axi_arsize : UInt<3>, flip axi_arprot : UInt<3>, flip axi_rready : UInt<1>, flip ahb_hrdata : UInt<64>, flip ahb_hready : UInt<1>, flip ahb_hresp : UInt<1>, axi_awready : UInt<1>, axi_wready : UInt<1>, axi_bvalid : UInt<1>, axi_bresp : UInt<2>, axi_bid : UInt<1>, axi_arready : UInt<1>, axi_rvalid : UInt<1>, axi_rid : UInt<1>, axi_rdata : UInt<32>, axi_rresp : UInt<2>, axi_rlast : UInt<1>, ahb_haddr : UInt<32>, ahb_hburst : UInt<3>, ahb_hmastlock : UInt<1>, ahb_hprot : UInt<4>, ahb_hsize : UInt<3>, ahb_htrans : UInt<2>, ahb_hwrite : UInt<1>, ahb_hwdata : UInt<64>} + output io : {flip scan_mode : UInt<1>, flip bus_clk_en : UInt<1>, flip clk_override : UInt<1>, flip axi_awvalid : UInt<1>, flip axi_awid : UInt<1>, flip axi_awaddr : UInt<32>, flip axi_awsize : UInt<3>, flip axi_awprot : UInt<3>, flip axi_wvalid : UInt<1>, flip axi_wdata : UInt<64>, flip axi_wstrb : UInt<8>, flip axi_wlast : UInt<1>, flip axi_bready : UInt<1>, flip axi_arvalid : UInt<1>, flip axi_arid : UInt<1>, flip axi_araddr : UInt<32>, flip axi_arsize : UInt<3>, flip axi_arprot : UInt<3>, flip axi_rready : UInt<1>, flip ahb_hrdata : UInt<64>, flip ahb_hready : UInt<1>, flip ahb_hresp : UInt<1>, axi_awready : UInt<1>, axi_wready : UInt<1>, axi_bvalid : UInt<1>, axi_bresp : UInt<2>, axi_bid : UInt<1>, axi_arready : UInt<1>, axi_rvalid : UInt<1>, axi_rid : UInt<1>, axi_rdata : UInt<64>, axi_rresp : UInt<2>, axi_rlast : UInt<1>, ahb_haddr : UInt<32>, ahb_hburst : UInt<3>, ahb_hmastlock : UInt<1>, ahb_hprot : UInt<4>, ahb_hsize : UInt<3>, ahb_htrans : UInt<2>, ahb_hwrite : UInt<1>, ahb_hwdata : UInt<64>} reg state : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[axi4_to_ahb.scala 61:22] reg buf_state : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[axi4_to_ahb.scala 62:26] diff --git a/axi4_to_ahb.v b/axi4_to_ahb.v index 0588d437..2b90ba23 100644 --- a/axi4_to_ahb.v +++ b/axi4_to_ahb.v @@ -52,7 +52,7 @@ module axi4_to_ahb( output io_axi_arready, output io_axi_rvalid, output io_axi_rid, - output [31:0] io_axi_rdata, + output [63:0] io_axi_rdata, output [1:0] io_axi_rresp, output io_axi_rlast, output [31:0] io_ahb_haddr, @@ -230,7 +230,7 @@ module axi4_to_ahb( assign io_axi_arready = ~wr_cmd_vld; // @[axi4_to_ahb.scala 190:18] assign io_axi_rvalid = 1'h0; // @[axi4_to_ahb.scala 207:17] assign io_axi_rid = 1'h0; // @[axi4_to_ahb.scala 209:14] - assign io_axi_rdata = ahb_hrdata_q[31:0]; // @[axi4_to_ahb.scala 210:16] + assign io_axi_rdata = ahb_hrdata_q; // @[axi4_to_ahb.scala 210:16] assign io_axi_rresp = 2'h0; // @[axi4_to_ahb.scala 208:16] assign io_axi_rlast = 1'h1; // @[axi4_to_ahb.scala 191:16] assign io_ahb_haddr = master_valid ? _T_575 : _T_578; // @[axi4_to_ahb.scala 335:16] diff --git a/el2_swerv.fir b/el2_swerv.fir index eeed988f..20452286 100644 --- a/el2_swerv.fir +++ b/el2_swerv.fir @@ -101791,9 +101791,9 @@ circuit el2_swerv : io.lsu_fir_addr <= lsu_lsc_ctl.io.lsu_fir_addr @[el2_lsu.scala 236:49] io.lsu_fir_error <= lsu_lsc_ctl.io.lsu_fir_error @[el2_lsu.scala 237:49] dccm_ctl.io.lsu_c2_m_clk <= clkdomain.io.lsu_c2_m_clk @[el2_lsu.scala 240:46] - dccm_ctl.io.lsu_c2_r_clk <= clkdomain.io.lsu_c2_m_clk @[el2_lsu.scala 241:46] - dccm_ctl.io.lsu_free_c2_clk <= clkdomain.io.lsu_c2_r_clk @[el2_lsu.scala 242:46] - dccm_ctl.io.lsu_c1_r_clk <= clkdomain.io.lsu_free_c2_clk @[el2_lsu.scala 243:46] + dccm_ctl.io.lsu_c2_r_clk <= clkdomain.io.lsu_c2_r_clk @[el2_lsu.scala 241:46] + dccm_ctl.io.lsu_free_c2_clk <= clkdomain.io.lsu_free_c2_clk @[el2_lsu.scala 242:46] + dccm_ctl.io.lsu_c1_r_clk <= clkdomain.io.lsu_c1_r_clk @[el2_lsu.scala 243:46] dccm_ctl.io.lsu_store_c1_r_clk <= clkdomain.io.lsu_store_c1_r_clk @[el2_lsu.scala 244:46] dccm_ctl.io.lsu_pkt_d.bits.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_d.bits.store_data_bypass_m @[el2_lsu.scala 246:46] dccm_ctl.io.lsu_pkt_d.bits.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_d.bits.load_ldst_bypass_d @[el2_lsu.scala 246:46] diff --git a/el2_swerv.v b/el2_swerv.v index 848b1b89..478ed340 100644 --- a/el2_swerv.v +++ b/el2_swerv.v @@ -74364,8 +74364,8 @@ module el2_lsu( assign dccm_ctl_clock = clock; assign dccm_ctl_reset = reset; assign dccm_ctl_io_lsu_c2_m_clk = clkdomain_io_lsu_c2_m_clk; // @[el2_lsu.scala 240:46] - assign dccm_ctl_io_lsu_c2_r_clk = clkdomain_io_lsu_c2_m_clk; // @[el2_lsu.scala 241:46] - assign dccm_ctl_io_lsu_free_c2_clk = clkdomain_io_lsu_c2_r_clk; // @[el2_lsu.scala 242:46] + assign dccm_ctl_io_lsu_c2_r_clk = clkdomain_io_lsu_c2_r_clk; // @[el2_lsu.scala 241:46] + assign dccm_ctl_io_lsu_free_c2_clk = clkdomain_io_lsu_free_c2_clk; // @[el2_lsu.scala 242:46] assign dccm_ctl_io_lsu_store_c1_r_clk = clkdomain_io_lsu_store_c1_r_clk; // @[el2_lsu.scala 244:46] assign dccm_ctl_io_lsu_pkt_d_valid = lsu_lsc_ctl_io_lsu_pkt_d_valid; // @[el2_lsu.scala 246:46] assign dccm_ctl_io_lsu_pkt_d_bits_word = lsu_lsc_ctl_io_lsu_pkt_d_bits_word; // @[el2_lsu.scala 246:46] diff --git a/src/main/scala/lib/axi4_to_ahb.scala b/src/main/scala/lib/axi4_to_ahb.scala index 4484873e..ffe793b1 100644 --- a/src/main/scala/lib/axi4_to_ahb.scala +++ b/src/main/scala/lib/axi4_to_ahb.scala @@ -41,7 +41,7 @@ class axi4_to_ahb_IO extends Bundle with Config { val axi_arready = Output(Bool()) val axi_rvalid = Output(Bool()) val axi_rid = Output(UInt(TAG.W)) // [TAG-1:0] - val axi_rdata = Output(UInt(32.W)) // [63:0] + val axi_rdata = Output(UInt(64.W)) // [63:0] val axi_rresp = Output(UInt(2.W)) // 1:0] val axi_rlast = Output(Bool()) // AHB-Lite signals diff --git a/target/scala-2.12/classes/lib/axi4_to_ahb_IO.class b/target/scala-2.12/classes/lib/axi4_to_ahb_IO.class index fbca4c2acf03e6d7c6649b94e88f7b24c8ac2916..9e8a834093bac20e7a5ec0d0ef2bec40e2e7e363 100644 GIT binary patch delta 16 XcmX@$dBAf+hT`N^N)nqJ6djlWKI{fs delta 16 XcmX@$dBAf+hT`NCiV~X}6djlWKh*|z