bank0 updated updated

el2_ifu_bp_ctl.fir

@@ -11,7 +11,7 @@ circuit el2_ifu_bp_ctl :
     bht_dir_f <= UInt<1>("h00")
     wire dec_tlu_error_wb : UInt<1>
     dec_tlu_error_wb <= UInt<1>("h00")
-    wire btb_error_addr_wb : UInt<7>
+    wire btb_error_addr_wb : UInt<8>
     btb_error_addr_wb <= UInt<1>("h00")
     wire btb_bank0_rd_data_way0_f : UInt<22>
     btb_bank0_rd_data_way0_f <= UInt<1>("h00")
@@ -33,20 +33,20 @@ circuit el2_ifu_bp_ctl :
     dec_tlu_error_wb <= _T_1 @[el2_ifu_bp_ctl.scala 91:20]
     btb_error_addr_wb <= io.exu_i0_br_index_r @[el2_ifu_bp_ctl.scala 92:21]
     dec_tlu_way_wb <= io.dec_tlu_br0_r_pkt.way @[el2_ifu_bp_ctl.scala 93:18]
-    node _T_2 = bits(io.ifc_fetch_addr_f, 8, 1) @[el2_lib.scala 196:12]
+    node _T_2 = bits(io.ifc_fetch_addr_f, 8, 1) @[el2_lib.scala 196:13]
-    node _T_3 = bits(io.ifc_fetch_addr_f, 16, 9) @[el2_lib.scala 196:50]
+    node _T_3 = bits(io.ifc_fetch_addr_f, 16, 9) @[el2_lib.scala 196:51]
-    node _T_4 = xor(_T_2, _T_3) @[el2_lib.scala 196:46]
+    node _T_4 = xor(_T_2, _T_3) @[el2_lib.scala 196:47]
-    node _T_5 = bits(io.ifc_fetch_addr_f, 24, 17) @[el2_lib.scala 196:88]
+    node _T_5 = bits(io.ifc_fetch_addr_f, 24, 17) @[el2_lib.scala 196:89]
-    node btb_rd_addr_f = xor(_T_4, _T_5) @[el2_lib.scala 196:84]
+    node btb_rd_addr_f = xor(_T_4, _T_5) @[el2_lib.scala 196:85]
     node _T_6 = bits(io.ifc_fetch_addr_f, 30, 1) @[el2_ifu_bp_ctl.scala 99:44]
     node _T_7 = add(_T_6, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 99:51]
     node fetch_addr_p1_f = tail(_T_7, 1) @[el2_ifu_bp_ctl.scala 99:51]
     node _T_8 = cat(fetch_addr_p1_f, UInt<1>("h00")) @[Cat.scala 29:58]
-    node _T_9 = bits(_T_8, 8, 1) @[el2_lib.scala 196:12]
+    node _T_9 = bits(_T_8, 8, 1) @[el2_lib.scala 196:13]
-    node _T_10 = bits(_T_8, 16, 9) @[el2_lib.scala 196:50]
+    node _T_10 = bits(_T_8, 16, 9) @[el2_lib.scala 196:51]
-    node _T_11 = xor(_T_9, _T_10) @[el2_lib.scala 196:46]
+    node _T_11 = xor(_T_9, _T_10) @[el2_lib.scala 196:47]
-    node _T_12 = bits(_T_8, 24, 17) @[el2_lib.scala 196:88]
+    node _T_12 = bits(_T_8, 24, 17) @[el2_lib.scala 196:89]
-    node btb_rd_addr_p1_f = xor(_T_11, _T_12) @[el2_lib.scala 196:84]
+    node btb_rd_addr_p1_f = xor(_T_11, _T_12) @[el2_lib.scala 196:85]
     node _T_13 = bits(bht_dir_f, 0, 0) @[el2_ifu_bp_ctl.scala 105:33]
     node _T_14 = not(_T_13) @[el2_ifu_bp_ctl.scala 105:23]
     node _T_15 = bits(bht_dir_f, 0, 0) @[el2_ifu_bp_ctl.scala 105:46]

el2_ifu_bp_ctl.v

@@ -1095,12 +1095,12 @@ module el2_ifu_bp_ctl(
   wire  _T = ~leak_one_f; // @[el2_ifu_bp_ctl.scala 69:46]
   wire  exu_mp_valid = io_exu_mp_pkt_misp & _T; // @[el2_ifu_bp_ctl.scala 69:44]
   wire  dec_tlu_error_wb = io_dec_tlu_br0_r_pkt_br_start_error | io_dec_tlu_br0_r_pkt_br_error; // @[el2_ifu_bp_ctl.scala 91:50]
-  wire [7:0] _T_4 = io_ifc_fetch_addr_f[8:1] ^ io_ifc_fetch_addr_f[16:9]; // @[el2_lib.scala 196:46]
+  wire [7:0] _T_4 = io_ifc_fetch_addr_f[8:1] ^ io_ifc_fetch_addr_f[16:9]; // @[el2_lib.scala 196:47]
-  wire [7:0] btb_rd_addr_f = _T_4 ^ io_ifc_fetch_addr_f[24:17]; // @[el2_lib.scala 196:84]
+  wire [7:0] btb_rd_addr_f = _T_4 ^ io_ifc_fetch_addr_f[24:17]; // @[el2_lib.scala 196:85]
   wire [29:0] fetch_addr_p1_f = io_ifc_fetch_addr_f[30:1] + 30'h1; // @[el2_ifu_bp_ctl.scala 99:51]
   wire [30:0] _T_8 = {fetch_addr_p1_f,1'h0}; // @[Cat.scala 29:58]
-  wire [7:0] _T_11 = _T_8[8:1] ^ _T_8[16:9]; // @[el2_lib.scala 196:46]
+  wire [7:0] _T_11 = _T_8[8:1] ^ _T_8[16:9]; // @[el2_lib.scala 196:47]
-  wire [7:0] btb_rd_addr_p1_f = _T_11 ^ _T_8[24:17]; // @[el2_lib.scala 196:84]
+  wire [7:0] btb_rd_addr_p1_f = _T_11 ^ _T_8[24:17]; // @[el2_lib.scala 196:85]
   wire  _T_143 = ~io_ifc_fetch_addr_f[0]; // @[el2_ifu_bp_ctl.scala 176:40]
   wire  _T_2110 = btb_rd_addr_f == 8'h0; // @[el2_ifu_bp_ctl.scala 367:77]
   reg [21:0] btb_bank0_rd_data_way0_out_0; // @[Reg.scala 27:20]
@@ -2130,9 +2130,7 @@ module el2_ifu_bp_ctl(
   wire  _T_45 = btb_bank0_rd_data_way0_f[21:17] == fetch_rd_tag_f; // @[el2_ifu_bp_ctl.scala 133:97]
   wire  _T_46 = btb_bank0_rd_data_way0_f[0] & _T_45; // @[el2_ifu_bp_ctl.scala 133:55]
   reg  dec_tlu_way_wb_f; // @[el2_ifu_bp_ctl.scala 125:59]
-  wire [6:0] btb_error_addr_wb = io_exu_i0_br_index_r[6:0]; // @[el2_ifu_bp_ctl.scala 92:21]
+  wire  _T_19 = io_exu_i0_br_index_r == btb_rd_addr_f; // @[el2_ifu_bp_ctl.scala 111:72]
-  wire [7:0] _GEN_1034 = {{1'd0}, btb_error_addr_wb}; // @[el2_ifu_bp_ctl.scala 111:72]
-  wire  _T_19 = _GEN_1034 == btb_rd_addr_f; // @[el2_ifu_bp_ctl.scala 111:72]
   wire  branch_error_collision_f = dec_tlu_error_wb & _T_19; // @[el2_ifu_bp_ctl.scala 111:51]
   wire  branch_error_bank_conflict_f = branch_error_collision_f & dec_tlu_error_wb; // @[el2_ifu_bp_ctl.scala 115:63]
   wire  _T_47 = dec_tlu_way_wb_f & branch_error_bank_conflict_f; // @[el2_ifu_bp_ctl.scala 134:22]
@@ -7045,7 +7043,7 @@ module el2_ifu_bp_ctl(
   wire  _T_545 = _T_543 & _T_529; // @[el2_ifu_bp_ctl.scala 342:57]
   wire  _T_546 = io_dec_tlu_br0_r_pkt_way & dec_tlu_error_wb; // @[el2_ifu_bp_ctl.scala 342:98]
   wire  btb_wr_en_way1 = _T_545 | _T_546; // @[el2_ifu_bp_ctl.scala 342:80]
-  wire [7:0] btb_wr_addr = dec_tlu_error_wb ? {{1'd0}, btb_error_addr_wb} : io_exu_mp_index; // @[el2_ifu_bp_ctl.scala 344:24]
+  wire [7:0] btb_wr_addr = dec_tlu_error_wb ? io_exu_i0_br_index_r : io_exu_mp_index; // @[el2_ifu_bp_ctl.scala 344:24]
   wire  middle_of_bank = io_exu_mp_pkt_pc4 ^ io_exu_mp_pkt_boffset; // @[el2_ifu_bp_ctl.scala 345:35]
   wire  _T_548 = ~io_exu_mp_pkt_pcall; // @[el2_ifu_bp_ctl.scala 346:43]
   wire  _T_549 = exu_mp_valid & _T_548; // @[el2_ifu_bp_ctl.scala 346:41]

src/main/scala/ifu/el2_ifu_bp_ctl.scala

@@ -56,7 +56,7 @@ class el2_ifu_bp_ctl extends Module with el2_lib with RequireAsyncReset {
   val leak_one_f = WireInit(Bool(), 0.U)
   val bht_dir_f = WireInit(UInt(2.W), 0.U)
   val dec_tlu_error_wb = WireInit(Bool(), 0.U)
-  val btb_error_addr_wb = WireInit(UInt((BTB_ADDR_HI-BTB_ADDR_LO).W), 0.U)
+  val btb_error_addr_wb = WireInit(UInt((BTB_ADDR_HI-BTB_ADDR_LO+1).W), 0.U)
   val btb_bank0_rd_data_way0_f = WireInit(UInt((TAG_START+1).W), 0.U)
   val btb_bank0_rd_data_way1_f = WireInit(UInt((TAG_START+1).W), 0.U)
   val btb_bank0_rd_data_way0_p1_f = WireInit(UInt((TAG_START+1).W), 0.U)

src/main/scala/lib/el2_lib.scala

@@ -193,7 +193,7 @@ trait el2_lib extends param{
   ///////////////////////////////////////////////////////////////////
   def el2_btb_addr_hash(pc : UInt) =
     if(BTB_FOLD2_INDEX_HASH) pc(BTB_INDEX1_HI-1,BTB_INDEX1_LO-1) ^ pc(BTB_INDEX3_HI-1,BTB_INDEX3_LO-1)
-    else pc(BTB_INDEX1_HI-1,BTB_INDEX1_LO-1) ^ pc(BTB_INDEX2_HI-1,BTB_INDEX2_LO-1) ^ pc(BTB_INDEX3_HI-1,BTB_INDEX3_LO-1)
+    else (pc(BTB_INDEX1_HI-1,BTB_INDEX1_LO-1) ^ pc(BTB_INDEX2_HI-1,BTB_INDEX2_LO-1) ^ pc(BTB_INDEX3_HI-1,BTB_INDEX3_LO-1))
 
   ///////////////////////////////////////////////////////////////////
   def el2_btb_ghr_hash(hashin : UInt, ghr :UInt) =