Quasar top done

src/main/scala/include/bundle.scala

@@ -49,6 +49,17 @@ class ahb_in extends Bundle{
   val hready        = Input(Bool()) // slave ready to accept transaction
   val hresp         = Input(Bool()) // slave response (high indicates erro)
 }
+class ahb_out_dma extends Bundle{
+  val haddr         = Output(UInt(32.W)) // [31:0]  // ahb bus address
+  val hburst        = Output(UInt(3.W)) // [2:0]   // tied to 0
+  val hmastlock     = Output(Bool()) // tied to 0
+  val hprot         = Output(UInt(4.W)) // [3:0]   // tied to 4'b0011
+  val hsize         = Output(UInt(3.W)) // [2:0]   // size of bus transaction (possible values 0,1,2,3)
+  val htrans        = Output(UInt(2.W))
+  val hwrite        = Output(Bool()) // ahb bus write
+  val hwdata        = Output(UInt(64.W)) // [63:0]  // ahb bus write data
+}
+
 class ahb_out extends Bundle{
   val haddr         = Output(UInt(32.W)) // [31:0]  // ahb bus address
   val hburst        = Output(UInt(3.W)) // [2:0]   // tied to 0

src/main/scala/lib/lib.scala

@@ -1,9 +1,21 @@
 package lib
 import chisel3._
 import chisel3.util._
+import include._
 trait lib extends param{
+  implicit def int2boolean(b:Int) = if (b==1) true else false
+  implicit def uint2bool(b:UInt) = b.asBool()
+  implicit def aslong(b:Int) = 0xFFFFFFFFL & b
   def repl(b:Int, a:UInt) = VecInit.tabulate(b)(i => a).reduce(Cat(_,_))
 
+  def bridge_gen(tag: Int, ahb_type: Boolean) = if(BUILD_AXI4) new axi_channels(tag) else ahb_bridge_gen(ahb_type)
+
+  def ahb_bridge_gen(ahb_type: Boolean) = if(ahb_type) new Bundle{
+    val ahb= Flipped(new ahb_channel())
+    val hsel = Input(Bool())
+    val hreadyin = Input(Bool())}
+  else new ahb_channel()
+
   def MEM_CAL : (Int, Int, Int, Int)=
     (ICACHE_WAYPACK, ICACHE_ECC) match{
       case(0,0) => (68, 22, 68, 22)
@@ -14,9 +26,7 @@ trait lib extends param{
   val DATA_MEM_LINE = MEM_CAL
   val Tag_Word = MEM_CAL._4
 
-  implicit def int2boolean(b:Int) = if (b==1) true else false
-  implicit def uint2bool(b:UInt) = b.asBool()
-  implicit def aslong(b:Int) = 0xFFFFFFFFL & b
+
   object rvsyncss {
     def apply(din:UInt,clk:Clock) =withClock(clk){RegNext(withClock(clk){RegNext(din,0.U)},0.U)}
   }

src/main/scala/quasar.scala

@@ -532,6 +532,8 @@ class quasar extends Module with RequireAsyncReset with lib {
     }
   io.dmi_reg_rdata := 0.U
 }
-
+object QUASAR extends App {
+  println((new chisel3.stage.ChiselStage).emitVerilog(new quasar()))
+}
 
 

src/main/scala/quasar_wrapper.scala

@@ -13,29 +13,10 @@ class quasar_wrapper extends Module with lib with RequireAsyncReset {
     val jtag_id = Input(UInt(31.W))
 
     // AXI Signals
-    val lsu_axi = new axi_channels(LSU_BUS_TAG)
-    val ifu_axi = new axi_channels(IFU_BUS_TAG)
-    val sb_axi = new axi_channels(SB_BUS_TAG)
-    val dma_axi = Flipped(new axi_channels(DMA_BUS_TAG))
-
-    // DMA slave
-
-    val dma = new Bundle{
-      val ahb= Flipped(new ahb_channel())
-      val hsel = Input(Bool())
-      val hreadyin = Input(Bool())}
-    //    val dma_haddr = Input(UInt(32.W))
-    //    val dma_hburst = Input(UInt(3.W))
-    //    val dma_hmastlock = Input(Bool())
-    //    val dma_hprot = Input(UInt(4.W))
-    //    val dma_hsize = Input(UInt(3.W))
-    //    val dma_htrans = Input(UInt(2.W))
-    //    val dma_hwrite = Input(Bool())
-    //    val dma_hwdata = Input(UInt(64.W))
-
-    //    val dma_hrdata = Output(UInt(64.W))
-    //    val dma_hreadyout = Output(Bool())
-    //    val dma_hresp = Output(Bool())
+    val lsu_brg = bridge_gen(LSU_BUS_TAG, false)
+    val ifu_brg = bridge_gen(IFU_BUS_TAG, false)
+    val sb_brg = bridge_gen(SB_BUS_TAG, false)
+    val dma_brg = Flipped(bridge_gen(DMA_BUS_TAG, true))
 
     val lsu_bus_clk_en = Input(Bool())
     val ifu_bus_clk_en = Input(Bool())
@@ -82,6 +63,7 @@ class quasar_wrapper extends Module with lib with RequireAsyncReset {
   val mem = Module(new quasar.mem())
   val dmi_wrapper = Module(new dmi_wrapper())
   val swerv = Module(new quasar())
+  swerv.io.scan_mode := io.scan_mode
   dmi_wrapper.io.trst_n := io.jtag_trst_n
   dmi_wrapper.io.tck := io.jtag_tck
   dmi_wrapper.io.tms := io.jtag_tms
@@ -112,20 +94,29 @@ class quasar_wrapper extends Module with lib with RequireAsyncReset {
   swerv.io.ic <> mem.io.ic
   swerv.io.iccm <> mem.io.iccm
 
-  swerv.io.ahb.in      <> 0.U.asTypeOf(swerv.io.ahb.in)
-  swerv.io.lsu_ahb.in  <> 0.U.asTypeOf(swerv.io.lsu_ahb.in)
-  swerv.io.sb_ahb.in   <> 0.U.asTypeOf(swerv.io.sb_ahb.in)
-  io.dma.ahb.in   <> 0.U.asTypeOf(io.dma.ahb.in)
-  //  swerv.io.sb_hready := 0.U
-  //  swerv.io.hrdata := 0.U
-  //  swerv.io.sb_hresp := 0.U
-  //  swerv.io.lsu_hrdata := 0.U
-  //  swerv.io.lsu_hresp := 0.U
-  //  swerv.io.lsu_hready := 0.U
-  //  swerv.io.hready := 0.U
-  //  swerv.io.hresp := 0.U
-  //  swerv.io.sb_hrdata := 0.U
-  swerv.io.scan_mode := io.scan_mode
+
+  if(BUILD_AXI4) {
+    swerv.io.ahb <> 0.U.asTypeOf(swerv.io.ahb.in)
+    swerv.io.lsu_ahb <> 0.U.asTypeOf(swerv.io.lsu_ahb.in)
+    swerv.io.sb_ahb <> 0.U.asTypeOf(swerv.io.sb_ahb.in)
+    swerv.io.dma <> 0.U.asTypeOf(swerv.io.dma)
+
+    swerv.io.lsu_axi <> io.lsu_brg
+    swerv.io.ifu_axi <> io.ifu_brg
+    swerv.io.sb_axi <> io.sb_brg
+    swerv.io.dma_axi <> io.dma_brg
+  }
+  else {
+    swerv.io.ahb <> io.ifu_brg
+    swerv.io.lsu_ahb <> io.lsu_brg
+    swerv.io.sb_ahb <> io.sb_brg
+    swerv.io.dma <> io.dma_brg
+
+    swerv.io.lsu_axi <> 0.U.asTypeOf(swerv.io.lsu_axi)
+    swerv.io.ifu_axi <> 0.U.asTypeOf(swerv.io.ifu_axi)
+    swerv.io.sb_axi <> 0.U.asTypeOf(swerv.io.sb_axi)
+    swerv.io.dma_axi <> 0.U.asTypeOf(swerv.io.lsu_axi)
+  }
   // SweRV Inputs
   swerv.io.dbg_rst_l := io.dbg_rst_l
   swerv.io.rst_vec := io.rst_vec
@@ -142,23 +133,14 @@ class quasar_wrapper extends Module with lib with RequireAsyncReset {
   swerv.io.mpc_debug_run_req := io.mpc_debug_run_req
   swerv.io.mpc_reset_run_req := io.mpc_reset_run_req
 
-  //-------------------------- LSU AXI signals--------------------------
-  // AXI Write Channels
-  swerv.io.lsu_axi <> io.lsu_axi
-  //-------------------------- IFU AXI signals--------------------------
-  // AXI Write Channels
-  swerv.io.ifu_axi <> io.ifu_axi
-  //-------------------------- SB AXI signals--------------------------
-  // AXI Write Channels
-  swerv.io.sb_axi <> io.sb_axi
 
   //-------------------------- DMA AXI signals--------------------------
   // AXI Write Channels
-  swerv.io.dma_axi <> io.dma_axi
+  swerv.io.dma_axi <> io.dma_brg
 
   // DMA Slave
-  swerv.io.dma.hsel := io.dma.hsel
-  swerv.io.dma.ahb.out <> io.dma.ahb.out
+  //swerv.io.dma.hsel := io.dma.hsel
+  //swerv.io.dma.ahb.out <> io.dma.ahb.out
   //  swerv.io.dma_haddr := io.dma_haddr
   //  swerv.io.dma_hburst := io.dma_hburst
   //  swerv.io.dma_hmastlock := io.dma_hmastlock
@@ -167,23 +149,8 @@ class quasar_wrapper extends Module with lib with RequireAsyncReset {
   //  swerv.io.dma_htrans := io.dma_htrans
   //  swerv.io.dma_hwrite := io.dma_hwrite
   //  swerv.io.dma_hwdata := io.dma_hwdata
-  swerv.io.dma.hreadyin := io.dma.hreadyin
+  //swerv.io.dma.hreadyin := io.dma.hreadyin
 
-  swerv.io.lsu_bus_clk_en
-  swerv.io.ifu_bus_clk_en
-  swerv.io.dbg_bus_clk_en
-  swerv.io.dma_bus_clk_en
-
-  swerv.io.dmi_reg_en
-  swerv.io.dmi_reg_addr
-  swerv.io.dmi_reg_wr_en
-  swerv.io.dmi_reg_wdata
-  swerv.io.dmi_hard_reset
-
-  swerv.io.extintsrc_req
-  swerv.io.timer_int
-  swerv.io.soft_int
-  swerv.io.scan_mode
 
   swerv.io.lsu_bus_clk_en := io.lsu_bus_clk_en
   swerv.io.ifu_bus_clk_en := io.ifu_bus_clk_en