EXU Top updated

2021-01-26 09:43:24 +05:00 · 2021-01-26 09:43:24 +05:00 · b17f70b674
parent fd4ab0599d
commit b17f70b674
5 changed files with 237 additions and 165 deletions
--- a/exu.fir
+++ b/exu.fir
@ -45047,34 +45047,100 @@ circuit exu :
    i_mul.clock <= clock
    i_mul.reset <= reset
    i_mul.io.scan_mode <= io.scan_mode @[exu.scala 148:25]
-    i_mul.io.mul_p.bits.bfp <= io.dec_exu.decode_exu.mul_p.bits.bfp @[exu.scala 149:41]
-    i_mul.io.mul_p.bits.crc32c_w <= io.dec_exu.decode_exu.mul_p.bits.crc32c_w @[exu.scala 149:41]
-    i_mul.io.mul_p.bits.crc32c_h <= io.dec_exu.decode_exu.mul_p.bits.crc32c_h @[exu.scala 149:41]
-    i_mul.io.mul_p.bits.crc32c_b <= io.dec_exu.decode_exu.mul_p.bits.crc32c_b @[exu.scala 149:41]
-    i_mul.io.mul_p.bits.crc32_w <= io.dec_exu.decode_exu.mul_p.bits.crc32_w @[exu.scala 149:41]
-    i_mul.io.mul_p.bits.crc32_h <= io.dec_exu.decode_exu.mul_p.bits.crc32_h @[exu.scala 149:41]
-    i_mul.io.mul_p.bits.crc32_b <= io.dec_exu.decode_exu.mul_p.bits.crc32_b @[exu.scala 149:41]
-    i_mul.io.mul_p.bits.unshfl <= io.dec_exu.decode_exu.mul_p.bits.unshfl @[exu.scala 149:41]
-    i_mul.io.mul_p.bits.shfl <= io.dec_exu.decode_exu.mul_p.bits.shfl @[exu.scala 149:41]
-    i_mul.io.mul_p.bits.gorc <= io.dec_exu.decode_exu.mul_p.bits.gorc @[exu.scala 149:41]
-    i_mul.io.mul_p.bits.grev <= io.dec_exu.decode_exu.mul_p.bits.grev @[exu.scala 149:41]
-    i_mul.io.mul_p.bits.clmulr <= io.dec_exu.decode_exu.mul_p.bits.clmulr @[exu.scala 149:41]
-    i_mul.io.mul_p.bits.clmulh <= io.dec_exu.decode_exu.mul_p.bits.clmulh @[exu.scala 149:41]
-    i_mul.io.mul_p.bits.clmul <= io.dec_exu.decode_exu.mul_p.bits.clmul @[exu.scala 149:41]
-    i_mul.io.mul_p.bits.bdep <= io.dec_exu.decode_exu.mul_p.bits.bdep @[exu.scala 149:41]
-    i_mul.io.mul_p.bits.bext <= io.dec_exu.decode_exu.mul_p.bits.bext @[exu.scala 149:41]
-    i_mul.io.mul_p.bits.low <= io.dec_exu.decode_exu.mul_p.bits.low @[exu.scala 149:41]
-    i_mul.io.mul_p.bits.rs2_sign <= io.dec_exu.decode_exu.mul_p.bits.rs2_sign @[exu.scala 149:41]
-    i_mul.io.mul_p.bits.rs1_sign <= io.dec_exu.decode_exu.mul_p.bits.rs1_sign @[exu.scala 149:41]
-    i_mul.io.mul_p.valid <= io.dec_exu.decode_exu.mul_p.valid @[exu.scala 149:41]
-    node _T_160 = bits(io.dec_exu.decode_exu.mul_p.valid, 0, 0) @[Bitwise.scala 72:15]
-    node _T_161 = mux(_T_160, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
-    node _T_162 = and(muldiv_rs1_d, _T_161) @[exu.scala 150:57]
-    i_mul.io.rs1_in <= _T_162 @[exu.scala 150:41]
-    node _T_163 = bits(io.dec_exu.decode_exu.mul_p.valid, 0, 0) @[Bitwise.scala 72:15]
-    node _T_164 = mux(_T_163, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
-    node _T_165 = and(i0_rs2_d, _T_164) @[exu.scala 151:54]
-    i_mul.io.rs2_in <= _T_165 @[exu.scala 151:41]
+    node _T_160 = cat(io.dec_exu.decode_exu.mul_p.bits.crc32c_w, io.dec_exu.decode_exu.mul_p.bits.bfp) @[exu.scala 149:139]
+    node _T_161 = cat(io.dec_exu.decode_exu.mul_p.bits.crc32c_b, io.dec_exu.decode_exu.mul_p.bits.crc32c_h) @[exu.scala 149:139]
+    node _T_162 = cat(_T_161, _T_160) @[exu.scala 149:139]
+    node _T_163 = cat(io.dec_exu.decode_exu.mul_p.bits.crc32_h, io.dec_exu.decode_exu.mul_p.bits.crc32_w) @[exu.scala 149:139]
+    node _T_164 = cat(io.dec_exu.decode_exu.mul_p.bits.shfl, io.dec_exu.decode_exu.mul_p.bits.unshfl) @[exu.scala 149:139]
+    node _T_165 = cat(_T_164, io.dec_exu.decode_exu.mul_p.bits.crc32_b) @[exu.scala 149:139]
+    node _T_166 = cat(_T_165, _T_163) @[exu.scala 149:139]
+    node _T_167 = cat(_T_166, _T_162) @[exu.scala 149:139]
+    node _T_168 = cat(io.dec_exu.decode_exu.mul_p.bits.grev, io.dec_exu.decode_exu.mul_p.bits.gorc) @[exu.scala 149:139]
+    node _T_169 = cat(io.dec_exu.decode_exu.mul_p.bits.clmul, io.dec_exu.decode_exu.mul_p.bits.clmulh) @[exu.scala 149:139]
+    node _T_170 = cat(_T_169, io.dec_exu.decode_exu.mul_p.bits.clmulr) @[exu.scala 149:139]
+    node _T_171 = cat(_T_170, _T_168) @[exu.scala 149:139]
+    node _T_172 = cat(io.dec_exu.decode_exu.mul_p.bits.bext, io.dec_exu.decode_exu.mul_p.bits.bdep) @[exu.scala 149:139]
+    node _T_173 = cat(io.dec_exu.decode_exu.mul_p.bits.rs1_sign, io.dec_exu.decode_exu.mul_p.bits.rs2_sign) @[exu.scala 149:139]
+    node _T_174 = cat(_T_173, io.dec_exu.decode_exu.mul_p.bits.low) @[exu.scala 149:139]
+    node _T_175 = cat(_T_174, _T_172) @[exu.scala 149:139]
+    node _T_176 = cat(_T_175, _T_171) @[exu.scala 149:139]
+    node _T_177 = cat(_T_176, _T_167) @[exu.scala 149:139]
+    node _T_178 = bits(io.dec_exu.decode_exu.mul_p.valid, 0, 0) @[Bitwise.scala 72:15]
+    node _T_179 = mux(_T_178, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
+    node _T_180 = and(_T_177, _T_179) @[exu.scala 149:146]
+    wire _T_181 : UInt<19>[1] @[exu.scala 149:92]
+    _T_181[0] <= _T_180 @[exu.scala 149:92]
+    wire _T_182 : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, gorc : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}} @[exu.scala 149:242]
+    wire _T_183 : UInt<20>
+    _T_183 <= _T_181[0]
+    node _T_184 = bits(_T_183, 0, 0) @[exu.scala 149:242]
+    _T_182.bits.bfp <= _T_184 @[exu.scala 149:242]
+    node _T_185 = bits(_T_183, 1, 1) @[exu.scala 149:242]
+    _T_182.bits.crc32c_w <= _T_185 @[exu.scala 149:242]
+    node _T_186 = bits(_T_183, 2, 2) @[exu.scala 149:242]
+    _T_182.bits.crc32c_h <= _T_186 @[exu.scala 149:242]
+    node _T_187 = bits(_T_183, 3, 3) @[exu.scala 149:242]
+    _T_182.bits.crc32c_b <= _T_187 @[exu.scala 149:242]
+    node _T_188 = bits(_T_183, 4, 4) @[exu.scala 149:242]
+    _T_182.bits.crc32_w <= _T_188 @[exu.scala 149:242]
+    node _T_189 = bits(_T_183, 5, 5) @[exu.scala 149:242]
+    _T_182.bits.crc32_h <= _T_189 @[exu.scala 149:242]
+    node _T_190 = bits(_T_183, 6, 6) @[exu.scala 149:242]
+    _T_182.bits.crc32_b <= _T_190 @[exu.scala 149:242]
+    node _T_191 = bits(_T_183, 7, 7) @[exu.scala 149:242]
+    _T_182.bits.unshfl <= _T_191 @[exu.scala 149:242]
+    node _T_192 = bits(_T_183, 8, 8) @[exu.scala 149:242]
+    _T_182.bits.shfl <= _T_192 @[exu.scala 149:242]
+    node _T_193 = bits(_T_183, 9, 9) @[exu.scala 149:242]
+    _T_182.bits.gorc <= _T_193 @[exu.scala 149:242]
+    node _T_194 = bits(_T_183, 10, 10) @[exu.scala 149:242]
+    _T_182.bits.grev <= _T_194 @[exu.scala 149:242]
+    node _T_195 = bits(_T_183, 11, 11) @[exu.scala 149:242]
+    _T_182.bits.clmulr <= _T_195 @[exu.scala 149:242]
+    node _T_196 = bits(_T_183, 12, 12) @[exu.scala 149:242]
+    _T_182.bits.clmulh <= _T_196 @[exu.scala 149:242]
+    node _T_197 = bits(_T_183, 13, 13) @[exu.scala 149:242]
+    _T_182.bits.clmul <= _T_197 @[exu.scala 149:242]
+    node _T_198 = bits(_T_183, 14, 14) @[exu.scala 149:242]
+    _T_182.bits.bdep <= _T_198 @[exu.scala 149:242]
+    node _T_199 = bits(_T_183, 15, 15) @[exu.scala 149:242]
+    _T_182.bits.bext <= _T_199 @[exu.scala 149:242]
+    node _T_200 = bits(_T_183, 16, 16) @[exu.scala 149:242]
+    _T_182.bits.low <= _T_200 @[exu.scala 149:242]
+    node _T_201 = bits(_T_183, 17, 17) @[exu.scala 149:242]
+    _T_182.bits.rs2_sign <= _T_201 @[exu.scala 149:242]
+    node _T_202 = bits(_T_183, 18, 18) @[exu.scala 149:242]
+    _T_182.bits.rs1_sign <= _T_202 @[exu.scala 149:242]
+    node _T_203 = bits(_T_183, 19, 19) @[exu.scala 149:242]
+    _T_182.valid <= _T_203 @[exu.scala 149:242]
+    i_mul.io.mul_p.bits.bfp <= _T_182.bits.bfp @[exu.scala 149:25]
+    i_mul.io.mul_p.bits.crc32c_w <= _T_182.bits.crc32c_w @[exu.scala 149:25]
+    i_mul.io.mul_p.bits.crc32c_h <= _T_182.bits.crc32c_h @[exu.scala 149:25]
+    i_mul.io.mul_p.bits.crc32c_b <= _T_182.bits.crc32c_b @[exu.scala 149:25]
+    i_mul.io.mul_p.bits.crc32_w <= _T_182.bits.crc32_w @[exu.scala 149:25]
+    i_mul.io.mul_p.bits.crc32_h <= _T_182.bits.crc32_h @[exu.scala 149:25]
+    i_mul.io.mul_p.bits.crc32_b <= _T_182.bits.crc32_b @[exu.scala 149:25]
+    i_mul.io.mul_p.bits.unshfl <= _T_182.bits.unshfl @[exu.scala 149:25]
+    i_mul.io.mul_p.bits.shfl <= _T_182.bits.shfl @[exu.scala 149:25]
+    i_mul.io.mul_p.bits.gorc <= _T_182.bits.gorc @[exu.scala 149:25]
+    i_mul.io.mul_p.bits.grev <= _T_182.bits.grev @[exu.scala 149:25]
+    i_mul.io.mul_p.bits.clmulr <= _T_182.bits.clmulr @[exu.scala 149:25]
+    i_mul.io.mul_p.bits.clmulh <= _T_182.bits.clmulh @[exu.scala 149:25]
+    i_mul.io.mul_p.bits.clmul <= _T_182.bits.clmul @[exu.scala 149:25]
+    i_mul.io.mul_p.bits.bdep <= _T_182.bits.bdep @[exu.scala 149:25]
+    i_mul.io.mul_p.bits.bext <= _T_182.bits.bext @[exu.scala 149:25]
+    i_mul.io.mul_p.bits.low <= _T_182.bits.low @[exu.scala 149:25]
+    i_mul.io.mul_p.bits.rs2_sign <= _T_182.bits.rs2_sign @[exu.scala 149:25]
+    i_mul.io.mul_p.bits.rs1_sign <= _T_182.bits.rs1_sign @[exu.scala 149:25]
+    i_mul.io.mul_p.valid <= _T_182.valid @[exu.scala 149:25]
+    node _T_204 = bits(io.dec_exu.decode_exu.mul_p.valid, 0, 0) @[Bitwise.scala 72:15]
+    node _T_205 = mux(_T_204, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
+    node _T_206 = and(muldiv_rs1_d, _T_205) @[exu.scala 150:57]
+    i_mul.io.rs1_in <= _T_206 @[exu.scala 150:41]
+    node _T_207 = bits(io.dec_exu.decode_exu.mul_p.valid, 0, 0) @[Bitwise.scala 72:15]
+    node _T_208 = mux(_T_207, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
+    node _T_209 = and(i0_rs2_d, _T_208) @[exu.scala 151:54]
+    i_mul.io.rs2_in <= _T_209 @[exu.scala 151:41]
    inst i_div of exu_div_ctl @[exu.scala 154:21]
    i_div.clock <= clock
    i_div.reset <= reset
@ -45087,9 +45153,9 @@ circuit exu :
    i_div.io.divisor <= i0_rs2_d @[exu.scala 158:33]
    io.exu_div_wren <= i_div.io.exu_div_wren @[exu.scala 159:41]
    io.exu_div_result <= i_div.io.exu_div_result @[exu.scala 160:33]
-    node _T_166 = bits(mul_valid_x, 0, 0) @[exu.scala 162:76]
-    node _T_167 = mux(_T_166, i_mul.io.result_x, i_alu.io.result_ff) @[exu.scala 162:63]
-    io.dec_exu.decode_exu.exu_i0_result_x <= _T_167 @[exu.scala 162:57]
+    node _T_210 = bits(mul_valid_x, 0, 0) @[exu.scala 162:76]
+    node _T_211 = mux(_T_210, i_mul.io.result_x, i_alu.io.result_ff) @[exu.scala 162:63]
+    io.dec_exu.decode_exu.exu_i0_result_x <= _T_211 @[exu.scala 162:57]
    i0_predict_newp_d.bits.prett <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.prett @[exu.scala 163:47]
    i0_predict_newp_d.bits.pret <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pret @[exu.scala 163:47]
    i0_predict_newp_d.bits.way <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.way @[exu.scala 163:47]
@ -45104,94 +45170,94 @@ circuit exu :
    i0_predict_newp_d.bits.ataken <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.ataken @[exu.scala 163:47]
    i0_predict_newp_d.bits.misp <= io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.misp @[exu.scala 163:47]
    i0_predict_newp_d.valid <= io.dec_exu.decode_exu.dec_i0_predict_p_d.valid @[exu.scala 163:47]
-    node _T_168 = bits(io.dec_exu.ib_exu.dec_i0_pc_d, 0, 0) @[exu.scala 164:80]
-    i0_predict_newp_d.bits.boffset <= _T_168 @[exu.scala 164:47]
+    node _T_212 = bits(io.dec_exu.ib_exu.dec_i0_pc_d, 0, 0) @[exu.scala 164:80]
+    i0_predict_newp_d.bits.boffset <= _T_212 @[exu.scala 164:47]
    io.dec_exu.tlu_exu.exu_pmu_i0_br_misp <= i0_pp_r.bits.misp @[exu.scala 166:47]
    io.dec_exu.tlu_exu.exu_pmu_i0_br_ataken <= i0_pp_r.bits.ataken @[exu.scala 167:47]
    io.dec_exu.tlu_exu.exu_pmu_i0_pc4 <= i0_pp_r.bits.pc4 @[exu.scala 168:47]
-    node _T_169 = and(i0_predict_p_d.valid, io.dec_exu.dec_alu.dec_i0_alu_decode_d) @[exu.scala 171:54]
-    node _T_170 = eq(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r, UInt<1>("h00")) @[exu.scala 171:97]
-    node _T_171 = and(_T_169, _T_170) @[exu.scala 171:95]
-    i0_valid_d <= _T_171 @[exu.scala 171:28]
-    node _T_172 = and(i0_predict_p_d.bits.ataken, io.dec_exu.dec_alu.dec_i0_alu_decode_d) @[exu.scala 172:59]
-    i0_taken_d <= _T_172 @[exu.scala 172:28]
-    node _T_173 = eq(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r, UInt<1>("h00")) @[exu.scala 178:8]
-    node _T_174 = and(_T_173, i0_valid_d) @[exu.scala 178:50]
-    node _T_175 = bits(_T_174, 0, 0) @[exu.scala 178:64]
-    node _T_176 = bits(ghr_d, 6, 0) @[exu.scala 178:85]
-    node _T_177 = cat(_T_176, i0_taken_d) @[Cat.scala 29:58]
-    node _T_178 = eq(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r, UInt<1>("h00")) @[exu.scala 179:8]
-    node _T_179 = eq(i0_valid_d, UInt<1>("h00")) @[exu.scala 179:52]
-    node _T_180 = and(_T_178, _T_179) @[exu.scala 179:50]
-    node _T_181 = bits(_T_180, 0, 0) @[exu.scala 179:65]
-    node _T_182 = bits(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r, 0, 0) @[exu.scala 180:50]
-    node _T_183 = mux(_T_175, _T_177, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_184 = mux(_T_181, ghr_d, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_185 = mux(_T_182, ghr_x, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_186 = or(_T_183, _T_184) @[Mux.scala 27:72]
-    node _T_187 = or(_T_186, _T_185) @[Mux.scala 27:72]
-    wire _T_188 : UInt @[Mux.scala 27:72]
-    _T_188 <= _T_187 @[Mux.scala 27:72]
-    ghr_d_ns <= _T_188 @[exu.scala 177:14]
-    node _T_189 = eq(i0_valid_x, UInt<1>("h01")) @[exu.scala 184:32]
-    node _T_190 = bits(ghr_x, 6, 0) @[exu.scala 184:50]
-    node _T_191 = cat(_T_190, i0_taken_x) @[Cat.scala 29:58]
-    node _T_192 = mux(_T_189, _T_191, ghr_x) @[exu.scala 184:20]
-    ghr_x_ns <= _T_192 @[exu.scala 184:14]
+    node _T_213 = and(i0_predict_p_d.valid, io.dec_exu.dec_alu.dec_i0_alu_decode_d) @[exu.scala 171:54]
+    node _T_214 = eq(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r, UInt<1>("h00")) @[exu.scala 171:97]
+    node _T_215 = and(_T_213, _T_214) @[exu.scala 171:95]
+    i0_valid_d <= _T_215 @[exu.scala 171:28]
+    node _T_216 = and(i0_predict_p_d.bits.ataken, io.dec_exu.dec_alu.dec_i0_alu_decode_d) @[exu.scala 172:59]
+    i0_taken_d <= _T_216 @[exu.scala 172:28]
+    node _T_217 = eq(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r, UInt<1>("h00")) @[exu.scala 178:8]
+    node _T_218 = and(_T_217, i0_valid_d) @[exu.scala 178:50]
+    node _T_219 = bits(_T_218, 0, 0) @[exu.scala 178:64]
+    node _T_220 = bits(ghr_d, 6, 0) @[exu.scala 178:85]
+    node _T_221 = cat(_T_220, i0_taken_d) @[Cat.scala 29:58]
+    node _T_222 = eq(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r, UInt<1>("h00")) @[exu.scala 179:8]
+    node _T_223 = eq(i0_valid_d, UInt<1>("h00")) @[exu.scala 179:52]
+    node _T_224 = and(_T_222, _T_223) @[exu.scala 179:50]
+    node _T_225 = bits(_T_224, 0, 0) @[exu.scala 179:65]
+    node _T_226 = bits(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r, 0, 0) @[exu.scala 180:50]
+    node _T_227 = mux(_T_219, _T_221, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_228 = mux(_T_225, ghr_d, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_229 = mux(_T_226, ghr_x, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_230 = or(_T_227, _T_228) @[Mux.scala 27:72]
+    node _T_231 = or(_T_230, _T_229) @[Mux.scala 27:72]
+    wire _T_232 : UInt @[Mux.scala 27:72]
+    _T_232 <= _T_231 @[Mux.scala 27:72]
+    ghr_d_ns <= _T_232 @[exu.scala 177:14]
+    node _T_233 = eq(i0_valid_x, UInt<1>("h01")) @[exu.scala 184:32]
+    node _T_234 = bits(ghr_x, 6, 0) @[exu.scala 184:50]
+    node _T_235 = cat(_T_234, i0_taken_x) @[Cat.scala 29:58]
+    node _T_236 = mux(_T_233, _T_235, ghr_x) @[exu.scala 184:20]
+    ghr_x_ns <= _T_236 @[exu.scala 184:14]
    io.dec_exu.tlu_exu.exu_i0_br_valid_r <= i0_pp_r.valid @[exu.scala 186:43]
    io.dec_exu.tlu_exu.exu_i0_br_mp_r <= i0_pp_r.bits.misp @[exu.scala 187:43]
    io.exu_bp.exu_i0_br_way_r <= i0_pp_r.bits.way @[exu.scala 188:43]
-    node _T_193 = bits(i0_pp_r.valid, 0, 0) @[Bitwise.scala 72:15]
-    node _T_194 = mux(_T_193, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
-    node _T_195 = and(_T_194, i0_pp_r.bits.hist) @[exu.scala 189:69]
-    io.dec_exu.tlu_exu.exu_i0_br_hist_r <= _T_195 @[exu.scala 189:43]
+    node _T_237 = bits(i0_pp_r.valid, 0, 0) @[Bitwise.scala 72:15]
+    node _T_238 = mux(_T_237, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
+    node _T_239 = and(_T_238, i0_pp_r.bits.hist) @[exu.scala 189:69]
+    io.dec_exu.tlu_exu.exu_i0_br_hist_r <= _T_239 @[exu.scala 189:43]
    io.dec_exu.tlu_exu.exu_i0_br_error_r <= i0_pp_r.bits.br_error @[exu.scala 190:43]
-    node _T_196 = xor(i0_pp_r.bits.pc4, i0_pp_r.bits.boffset) @[exu.scala 191:63]
-    io.dec_exu.tlu_exu.exu_i0_br_middle_r <= _T_196 @[exu.scala 191:43]
+    node _T_240 = xor(i0_pp_r.bits.pc4, i0_pp_r.bits.boffset) @[exu.scala 191:63]
+    io.dec_exu.tlu_exu.exu_i0_br_middle_r <= _T_240 @[exu.scala 191:43]
    io.dec_exu.tlu_exu.exu_i0_br_start_error_r <= i0_pp_r.bits.br_start_error @[exu.scala 192:48]
-    node _T_197 = bits(predpipe_r, 20, 13) @[exu.scala 193:56]
-    io.exu_bp.exu_i0_br_fghr_r <= _T_197 @[exu.scala 193:43]
-    node _T_198 = bits(predpipe_r, 12, 5) @[exu.scala 194:56]
-    io.dec_exu.tlu_exu.exu_i0_br_index_r <= _T_198 @[exu.scala 194:43]
+    node _T_241 = bits(predpipe_r, 20, 13) @[exu.scala 193:56]
+    io.exu_bp.exu_i0_br_fghr_r <= _T_241 @[exu.scala 193:43]
+    node _T_242 = bits(predpipe_r, 12, 5) @[exu.scala 194:56]
+    io.dec_exu.tlu_exu.exu_i0_br_index_r <= _T_242 @[exu.scala 194:43]
    io.exu_bp.exu_i0_br_index_r <= io.dec_exu.tlu_exu.exu_i0_br_index_r @[exu.scala 195:43]
-    node _T_199 = eq(i0_flush_upper_x, UInt<1>("h01")) @[exu.scala 196:67]
-    wire _T_200 : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}} @[exu.scala 196:104]
-    _T_200.bits.prett <= UInt<31>("h00") @[exu.scala 196:104]
-    _T_200.bits.pret <= UInt<1>("h00") @[exu.scala 196:104]
-    _T_200.bits.way <= UInt<1>("h00") @[exu.scala 196:104]
-    _T_200.bits.pja <= UInt<1>("h00") @[exu.scala 196:104]
-    _T_200.bits.pcall <= UInt<1>("h00") @[exu.scala 196:104]
-    _T_200.bits.br_start_error <= UInt<1>("h00") @[exu.scala 196:104]
-    _T_200.bits.br_error <= UInt<1>("h00") @[exu.scala 196:104]
-    _T_200.bits.toffset <= UInt<12>("h00") @[exu.scala 196:104]
-    _T_200.bits.hist <= UInt<2>("h00") @[exu.scala 196:104]
-    _T_200.bits.pc4 <= UInt<1>("h00") @[exu.scala 196:104]
-    _T_200.bits.boffset <= UInt<1>("h00") @[exu.scala 196:104]
-    _T_200.bits.ataken <= UInt<1>("h00") @[exu.scala 196:104]
-    _T_200.bits.misp <= UInt<1>("h00") @[exu.scala 196:104]
-    _T_200.valid <= UInt<1>("h00") @[exu.scala 196:104]
-    node _T_201 = mux(_T_199, i0_predict_p_x, _T_200) @[exu.scala 196:49]
-    final_predict_mp.bits.prett <= _T_201.bits.prett @[exu.scala 196:43]
-    final_predict_mp.bits.pret <= _T_201.bits.pret @[exu.scala 196:43]
-    final_predict_mp.bits.way <= _T_201.bits.way @[exu.scala 196:43]
-    final_predict_mp.bits.pja <= _T_201.bits.pja @[exu.scala 196:43]
-    final_predict_mp.bits.pcall <= _T_201.bits.pcall @[exu.scala 196:43]
-    final_predict_mp.bits.br_start_error <= _T_201.bits.br_start_error @[exu.scala 196:43]
-    final_predict_mp.bits.br_error <= _T_201.bits.br_error @[exu.scala 196:43]
-    final_predict_mp.bits.toffset <= _T_201.bits.toffset @[exu.scala 196:43]
-    final_predict_mp.bits.hist <= _T_201.bits.hist @[exu.scala 196:43]
-    final_predict_mp.bits.pc4 <= _T_201.bits.pc4 @[exu.scala 196:43]
-    final_predict_mp.bits.boffset <= _T_201.bits.boffset @[exu.scala 196:43]
-    final_predict_mp.bits.ataken <= _T_201.bits.ataken @[exu.scala 196:43]
-    final_predict_mp.bits.misp <= _T_201.bits.misp @[exu.scala 196:43]
-    final_predict_mp.valid <= _T_201.valid @[exu.scala 196:43]
-    node _T_202 = eq(i0_flush_upper_x, UInt<1>("h01")) @[exu.scala 197:66]
-    node final_predpipe_mp = mux(_T_202, predpipe_x, UInt<1>("h00")) @[exu.scala 197:48]
-    node _T_203 = eq(i0_flush_upper_x, UInt<1>("h01")) @[exu.scala 199:67]
-    node _T_204 = eq(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r, UInt<1>("h01")) @[exu.scala 199:120]
-    node _T_205 = eq(_T_204, UInt<1>("h00")) @[exu.scala 199:77]
-    node _T_206 = and(_T_203, _T_205) @[exu.scala 199:75]
-    node after_flush_eghr = mux(_T_206, ghr_d, ghr_x) @[exu.scala 199:48]
+    node _T_243 = eq(i0_flush_upper_x, UInt<1>("h01")) @[exu.scala 196:67]
+    wire _T_244 : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, pcall : UInt<1>, pja : UInt<1>, way : UInt<1>, pret : UInt<1>, prett : UInt<31>}} @[exu.scala 196:104]
+    _T_244.bits.prett <= UInt<31>("h00") @[exu.scala 196:104]
+    _T_244.bits.pret <= UInt<1>("h00") @[exu.scala 196:104]
+    _T_244.bits.way <= UInt<1>("h00") @[exu.scala 196:104]
+    _T_244.bits.pja <= UInt<1>("h00") @[exu.scala 196:104]
+    _T_244.bits.pcall <= UInt<1>("h00") @[exu.scala 196:104]
+    _T_244.bits.br_start_error <= UInt<1>("h00") @[exu.scala 196:104]
+    _T_244.bits.br_error <= UInt<1>("h00") @[exu.scala 196:104]
+    _T_244.bits.toffset <= UInt<12>("h00") @[exu.scala 196:104]
+    _T_244.bits.hist <= UInt<2>("h00") @[exu.scala 196:104]
+    _T_244.bits.pc4 <= UInt<1>("h00") @[exu.scala 196:104]
+    _T_244.bits.boffset <= UInt<1>("h00") @[exu.scala 196:104]
+    _T_244.bits.ataken <= UInt<1>("h00") @[exu.scala 196:104]
+    _T_244.bits.misp <= UInt<1>("h00") @[exu.scala 196:104]
+    _T_244.valid <= UInt<1>("h00") @[exu.scala 196:104]
+    node _T_245 = mux(_T_243, i0_predict_p_x, _T_244) @[exu.scala 196:49]
+    final_predict_mp.bits.prett <= _T_245.bits.prett @[exu.scala 196:43]
+    final_predict_mp.bits.pret <= _T_245.bits.pret @[exu.scala 196:43]
+    final_predict_mp.bits.way <= _T_245.bits.way @[exu.scala 196:43]
+    final_predict_mp.bits.pja <= _T_245.bits.pja @[exu.scala 196:43]
+    final_predict_mp.bits.pcall <= _T_245.bits.pcall @[exu.scala 196:43]
+    final_predict_mp.bits.br_start_error <= _T_245.bits.br_start_error @[exu.scala 196:43]
+    final_predict_mp.bits.br_error <= _T_245.bits.br_error @[exu.scala 196:43]
+    final_predict_mp.bits.toffset <= _T_245.bits.toffset @[exu.scala 196:43]
+    final_predict_mp.bits.hist <= _T_245.bits.hist @[exu.scala 196:43]
+    final_predict_mp.bits.pc4 <= _T_245.bits.pc4 @[exu.scala 196:43]
+    final_predict_mp.bits.boffset <= _T_245.bits.boffset @[exu.scala 196:43]
+    final_predict_mp.bits.ataken <= _T_245.bits.ataken @[exu.scala 196:43]
+    final_predict_mp.bits.misp <= _T_245.bits.misp @[exu.scala 196:43]
+    final_predict_mp.valid <= _T_245.valid @[exu.scala 196:43]
+    node _T_246 = eq(i0_flush_upper_x, UInt<1>("h01")) @[exu.scala 197:66]
+    node final_predpipe_mp = mux(_T_246, predpipe_x, UInt<1>("h00")) @[exu.scala 197:48]
+    node _T_247 = eq(i0_flush_upper_x, UInt<1>("h01")) @[exu.scala 199:67]
+    node _T_248 = eq(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r, UInt<1>("h01")) @[exu.scala 199:120]
+    node _T_249 = eq(_T_248, UInt<1>("h00")) @[exu.scala 199:77]
+    node _T_250 = and(_T_247, _T_249) @[exu.scala 199:75]
+    node after_flush_eghr = mux(_T_250, ghr_d, ghr_x) @[exu.scala 199:48]
    io.exu_bp.exu_mp_pkt.valid <= final_predict_mp.valid @[exu.scala 201:39]
    io.exu_bp.exu_mp_pkt.bits.way <= final_predict_mp.bits.way @[exu.scala 202:39]
    io.exu_bp.exu_mp_pkt.bits.misp <= final_predict_mp.bits.misp @[exu.scala 203:39]
@ -45201,28 +45267,28 @@ circuit exu :
    io.exu_bp.exu_mp_pkt.bits.ataken <= final_predict_mp.bits.ataken @[exu.scala 207:39]
    io.exu_bp.exu_mp_pkt.bits.boffset <= final_predict_mp.bits.boffset @[exu.scala 208:39]
    io.exu_bp.exu_mp_pkt.bits.pc4 <= final_predict_mp.bits.pc4 @[exu.scala 209:39]
-    node _T_207 = bits(final_predict_mp.bits.hist, 1, 0) @[exu.scala 210:68]
-    io.exu_bp.exu_mp_pkt.bits.hist <= _T_207 @[exu.scala 210:39]
-    node _T_208 = bits(final_predict_mp.bits.toffset, 11, 0) @[exu.scala 211:71]
-    io.exu_bp.exu_mp_pkt.bits.toffset <= _T_208 @[exu.scala 211:39]
+    node _T_251 = bits(final_predict_mp.bits.hist, 1, 0) @[exu.scala 210:68]
+    io.exu_bp.exu_mp_pkt.bits.hist <= _T_251 @[exu.scala 210:39]
+    node _T_252 = bits(final_predict_mp.bits.toffset, 11, 0) @[exu.scala 211:71]
+    io.exu_bp.exu_mp_pkt.bits.toffset <= _T_252 @[exu.scala 211:39]
    io.exu_bp.exu_mp_fghr <= after_flush_eghr @[exu.scala 212:39]
-    node _T_209 = bits(final_predpipe_mp, 12, 5) @[exu.scala 213:59]
-    io.exu_bp.exu_mp_index <= _T_209 @[exu.scala 213:39]
-    node _T_210 = bits(final_predpipe_mp, 4, 0) @[exu.scala 214:59]
-    io.exu_bp.exu_mp_btag <= _T_210 @[exu.scala 214:39]
-    node _T_211 = bits(final_predpipe_mp, 20, 13) @[exu.scala 215:59]
-    io.exu_bp.exu_mp_eghr <= _T_211 @[exu.scala 215:39]
-    node _T_212 = bits(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r, 0, 0) @[exu.scala 237:46]
-    node _T_213 = not(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r) @[exu.scala 238:6]
-    node _T_214 = and(_T_213, i0_flush_upper_d) @[exu.scala 238:48]
-    node _T_215 = bits(_T_214, 0, 0) @[exu.scala 238:68]
-    node _T_216 = mux(_T_212, io.dec_exu.tlu_exu.dec_tlu_flush_path_r, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_217 = mux(_T_215, i0_flush_path_d, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_218 = or(_T_216, _T_217) @[Mux.scala 27:72]
-    wire _T_219 : UInt<31> @[Mux.scala 27:72]
-    _T_219 <= _T_218 @[Mux.scala 27:72]
-    io.exu_flush_path_final <= _T_219 @[exu.scala 236:33]
-    node _T_220 = eq(i0_pred_correct_upper_r, UInt<1>("h01")) @[exu.scala 240:79]
-    node _T_221 = mux(_T_220, pred_correct_npc_r, i0_flush_path_upper_r) @[exu.scala 240:55]
-    io.dec_exu.tlu_exu.exu_npc_r <= _T_221 @[exu.scala 240:49]
+    node _T_253 = bits(final_predpipe_mp, 12, 5) @[exu.scala 213:59]
+    io.exu_bp.exu_mp_index <= _T_253 @[exu.scala 213:39]
+    node _T_254 = bits(final_predpipe_mp, 4, 0) @[exu.scala 214:59]
+    io.exu_bp.exu_mp_btag <= _T_254 @[exu.scala 214:39]
+    node _T_255 = bits(final_predpipe_mp, 20, 13) @[exu.scala 215:59]
+    io.exu_bp.exu_mp_eghr <= _T_255 @[exu.scala 215:39]
+    node _T_256 = bits(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r, 0, 0) @[exu.scala 237:46]
+    node _T_257 = not(io.dec_exu.tlu_exu.dec_tlu_flush_lower_r) @[exu.scala 238:6]
+    node _T_258 = and(_T_257, i0_flush_upper_d) @[exu.scala 238:48]
+    node _T_259 = bits(_T_258, 0, 0) @[exu.scala 238:68]
+    node _T_260 = mux(_T_256, io.dec_exu.tlu_exu.dec_tlu_flush_path_r, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_261 = mux(_T_259, i0_flush_path_d, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_262 = or(_T_260, _T_261) @[Mux.scala 27:72]
+    wire _T_263 : UInt<31> @[Mux.scala 27:72]
+    _T_263 <= _T_262 @[Mux.scala 27:72]
+    io.exu_flush_path_final <= _T_263 @[exu.scala 236:33]
+    node _T_264 = eq(i0_pred_correct_upper_r, UInt<1>("h01")) @[exu.scala 240:79]
+    node _T_265 = mux(_T_264, pred_correct_npc_r, i0_flush_path_upper_r) @[exu.scala 240:55]
+    io.dec_exu.tlu_exu.exu_npc_r <= _T_265 @[exu.scala 240:49]
    
--- a/exu.v
+++ b/exu.v
@ -2344,15 +2344,15 @@ module exu(
  reg [7:0] ghr_x; // @[Reg.scala 27:20]
  reg  i0_valid_x; // @[Reg.scala 27:20]
  reg  i0_taken_x; // @[Reg.scala 27:20]
-  wire [7:0] _T_191 = {ghr_x[6:0],i0_taken_x}; // @[Cat.scala 29:58]
+  wire [7:0] _T_235 = {ghr_x[6:0],i0_taken_x}; // @[Cat.scala 29:58]
  reg  i0_pred_correct_upper_x; // @[Reg.scala 27:20]
  wire  i0_pred_correct_upper_d = i_alu_io_pred_correct_out; // @[exu.scala 47:41 exu.scala 145:27]
  reg  i0_flush_upper_x; // @[Reg.scala 27:20]
  wire  i0_flush_upper_d = i_alu_io_flush_upper_out; // @[exu.scala 48:45 exu.scala 141:35]
  wire  i0_taken_d = i0_predict_p_d_bits_ataken & io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[exu.scala 172:59]
-  wire  _T_169 = i0_predict_p_d_valid & io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[exu.scala 171:54]
-  wire  _T_170 = ~io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[exu.scala 171:97]
-  wire  i0_valid_d = _T_169 & _T_170; // @[exu.scala 171:95]
+  wire  _T_213 = i0_predict_p_d_valid & io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[exu.scala 171:54]
+  wire  _T_214 = ~io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[exu.scala 171:97]
+  wire  i0_valid_d = _T_213 & _T_214; // @[exu.scala 171:95]
  reg  i0_pp_r_valid; // @[Reg.scala 27:20]
  reg  i0_pp_r_bits_misp; // @[Reg.scala 27:20]
  reg  i0_pp_r_bits_ataken; // @[Reg.scala 27:20]
@ -2367,16 +2367,16 @@ module exu(
  reg [30:0] i0_flush_path_upper_r; // @[Reg.scala 27:20]
  reg [24:0] pred_temp2; // @[Reg.scala 27:20]
  wire [30:0] _T_31 = {pred_temp2,pred_temp1}; // @[Cat.scala 29:58]
-  wire  _T_174 = _T_170 & i0_valid_d; // @[exu.scala 178:50]
+  wire  _T_218 = _T_214 & i0_valid_d; // @[exu.scala 178:50]
  reg [7:0] ghr_d; // @[Reg.scala 27:20]
-  wire [7:0] _T_177 = {ghr_d[6:0],i0_taken_d}; // @[Cat.scala 29:58]
-  wire [7:0] _T_183 = _T_174 ? _T_177 : 8'h0; // @[Mux.scala 27:72]
-  wire  _T_179 = ~i0_valid_d; // @[exu.scala 179:52]
-  wire  _T_180 = _T_170 & _T_179; // @[exu.scala 179:50]
-  wire [7:0] _T_184 = _T_180 ? ghr_d : 8'h0; // @[Mux.scala 27:72]
-  wire [7:0] _T_186 = _T_183 | _T_184; // @[Mux.scala 27:72]
-  wire [7:0] _T_185 = io_dec_exu_tlu_exu_dec_tlu_flush_lower_r ? ghr_x : 8'h0; // @[Mux.scala 27:72]
-  wire [7:0] ghr_d_ns = _T_186 | _T_185; // @[Mux.scala 27:72]
+  wire [7:0] _T_221 = {ghr_d[6:0],i0_taken_d}; // @[Cat.scala 29:58]
+  wire [7:0] _T_227 = _T_218 ? _T_221 : 8'h0; // @[Mux.scala 27:72]
+  wire  _T_223 = ~i0_valid_d; // @[exu.scala 179:52]
+  wire  _T_224 = _T_214 & _T_223; // @[exu.scala 179:50]
+  wire [7:0] _T_228 = _T_224 ? ghr_d : 8'h0; // @[Mux.scala 27:72]
+  wire [7:0] _T_230 = _T_227 | _T_228; // @[Mux.scala 27:72]
+  wire [7:0] _T_229 = io_dec_exu_tlu_exu_dec_tlu_flush_lower_r ? ghr_x : 8'h0; // @[Mux.scala 27:72]
+  wire [7:0] ghr_d_ns = _T_230 | _T_229; // @[Mux.scala 27:72]
  wire [7:0] _T_33 = ghr_d_ns ^ ghr_d; // @[lib.scala 436:21]
  wire  _T_34 = |_T_33; // @[lib.scala 436:29]
  reg  mul_valid_x; // @[Reg.scala 27:20]
@ -2448,16 +2448,22 @@ module exu(
  wire  _T_153 = _T_87 & io_dec_exu_decode_exu_dec_i0_rs1_en_d; // @[exu.scala 125:26]
  wire [31:0] _T_156 = _T_153 ? io_dec_exu_gpr_exu_gpr_i0_rs1_d : 32'h0; // @[Mux.scala 27:72]
  wire [31:0] muldiv_rs1_d = _T_156 | _T_99; // @[Mux.scala 27:72]
-  wire [31:0] _T_161 = io_dec_exu_decode_exu_mul_p_valid ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
+  wire [9:0] _T_176 = {io_dec_exu_decode_exu_mul_p_bits_rs1_sign,io_dec_exu_decode_exu_mul_p_bits_rs2_sign,io_dec_exu_decode_exu_mul_p_bits_low,io_dec_exu_decode_exu_mul_p_bits_bext,io_dec_exu_decode_exu_mul_p_bits_bdep,io_dec_exu_decode_exu_mul_p_bits_clmul,io_dec_exu_decode_exu_mul_p_bits_clmulh,io_dec_exu_decode_exu_mul_p_bits_clmulr,io_dec_exu_decode_exu_mul_p_bits_grev,io_dec_exu_decode_exu_mul_p_bits_gorc}; // @[exu.scala 149:139]
+  wire [18:0] _T_177 = {_T_176,io_dec_exu_decode_exu_mul_p_bits_shfl,io_dec_exu_decode_exu_mul_p_bits_unshfl,io_dec_exu_decode_exu_mul_p_bits_crc32_b,io_dec_exu_decode_exu_mul_p_bits_crc32_h,io_dec_exu_decode_exu_mul_p_bits_crc32_w,io_dec_exu_decode_exu_mul_p_bits_crc32c_b,io_dec_exu_decode_exu_mul_p_bits_crc32c_h,io_dec_exu_decode_exu_mul_p_bits_crc32c_w,io_dec_exu_decode_exu_mul_p_bits_bfp}; // @[exu.scala 149:139]
+  wire [1:0] _T_179 = io_dec_exu_decode_exu_mul_p_valid ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
+  wire [18:0] _GEN_44 = {{17'd0}, _T_179}; // @[exu.scala 149:146]
+  wire [18:0] _T_180 = _T_177 & _GEN_44; // @[exu.scala 149:146]
+  wire [19:0] _T_183 = {{1'd0}, _T_180};
+  wire [31:0] _T_205 = io_dec_exu_decode_exu_mul_p_valid ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
  wire [31:0] i0_rs2_d = _T_118; // @[Mux.scala 27:72 Mux.scala 27:72]
-  wire [1:0] _T_194 = i0_pp_r_valid ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
+  wire [1:0] _T_238 = i0_pp_r_valid ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
  wire [20:0] final_predpipe_mp = i0_flush_upper_x ? predpipe_x : 21'h0; // @[exu.scala 197:48]
-  wire  _T_206 = i0_flush_upper_x & _T_170; // @[exu.scala 199:75]
-  wire  _T_214 = _T_170 & i0_flush_upper_d; // @[exu.scala 238:48]
-  wire [30:0] _T_216 = io_dec_exu_tlu_exu_dec_tlu_flush_lower_r ? io_dec_exu_tlu_exu_dec_tlu_flush_path_r : 31'h0; // @[Mux.scala 27:72]
-  wire [30:0] _T_217 = _T_214 ? i0_flush_path_d : 31'h0; // @[Mux.scala 27:72]
+  wire  _T_250 = i0_flush_upper_x & _T_214; // @[exu.scala 199:75]
+  wire  _T_258 = _T_214 & i0_flush_upper_d; // @[exu.scala 238:48]
+  wire [30:0] _T_260 = io_dec_exu_tlu_exu_dec_tlu_flush_lower_r ? io_dec_exu_tlu_exu_dec_tlu_flush_path_r : 31'h0; // @[Mux.scala 27:72]
+  wire [30:0] _T_261 = _T_258 ? i0_flush_path_d : 31'h0; // @[Mux.scala 27:72]
  wire [31:0] pred_correct_npc_r = {{1'd0}, _T_31}; // @[exu.scala 46:51 exu.scala 77:45]
-  wire [31:0] _T_221 = i0_pred_correct_upper_r ? pred_correct_npc_r : {{1'd0}, i0_flush_path_upper_r}; // @[exu.scala 240:55]
+  wire [31:0] _T_265 = i0_pred_correct_upper_r ? pred_correct_npc_r : {{1'd0}, i0_flush_path_upper_r}; // @[exu.scala 240:55]
  rvclkhdr rvclkhdr ( // @[lib.scala 399:23]
    .io_l1clk(rvclkhdr_io_l1clk),
    .io_clk(rvclkhdr_io_clk),
@ -2607,7 +2613,7 @@ module exu(
  assign io_dec_exu_dec_alu_exu_i0_pc_x = i_alu_io_dec_alu_exu_i0_pc_x; // @[exu.scala 130:20]
  assign io_dec_exu_decode_exu_exu_i0_result_x = mul_valid_x ? i_mul_io_result_x : i_alu_io_result_ff; // @[exu.scala 162:57]
  assign io_dec_exu_decode_exu_exu_csr_rs1_x = _T_107; // @[exu.scala 104:57]
-  assign io_dec_exu_tlu_exu_exu_i0_br_hist_r = _T_194 & i0_pp_r_bits_hist; // @[exu.scala 189:43]
+  assign io_dec_exu_tlu_exu_exu_i0_br_hist_r = _T_238 & i0_pp_r_bits_hist; // @[exu.scala 189:43]
  assign io_dec_exu_tlu_exu_exu_i0_br_error_r = i0_pp_r_bits_br_error; // @[exu.scala 190:43]
  assign io_dec_exu_tlu_exu_exu_i0_br_start_error_r = i0_pp_r_bits_br_start_error; // @[exu.scala 192:48]
  assign io_dec_exu_tlu_exu_exu_i0_br_index_r = predpipe_r[12:5]; // @[exu.scala 194:43]
@ -2617,7 +2623,7 @@ module exu(
  assign io_dec_exu_tlu_exu_exu_pmu_i0_br_misp = i0_pp_r_bits_misp; // @[exu.scala 166:47]
  assign io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken = i0_pp_r_bits_ataken; // @[exu.scala 167:47]
  assign io_dec_exu_tlu_exu_exu_pmu_i0_pc4 = i0_pp_r_bits_pc4; // @[exu.scala 168:47]
-  assign io_dec_exu_tlu_exu_exu_npc_r = _T_221[30:0]; // @[exu.scala 240:49]
+  assign io_dec_exu_tlu_exu_exu_npc_r = _T_265[30:0]; // @[exu.scala 240:49]
  assign io_exu_bp_exu_i0_br_index_r = io_dec_exu_tlu_exu_exu_i0_br_index_r; // @[exu.scala 195:43]
  assign io_exu_bp_exu_i0_br_fghr_r = predpipe_r[20:13]; // @[exu.scala 193:43]
  assign io_exu_bp_exu_i0_br_way_r = i0_pp_r_bits_way; // @[exu.scala 188:43]
@ -2636,7 +2642,7 @@ module exu(
  assign io_exu_bp_exu_mp_pkt_bits_pret = i0_flush_upper_x & i0_predict_p_x_bits_pret; // @[exu.scala 206:39]
  assign io_exu_bp_exu_mp_pkt_bits_prett = 31'h0; // @[exu.scala 49:57]
  assign io_exu_bp_exu_mp_eghr = final_predpipe_mp[20:13]; // @[exu.scala 215:39]
-  assign io_exu_bp_exu_mp_fghr = _T_206 ? ghr_d : ghr_x; // @[exu.scala 212:39]
+  assign io_exu_bp_exu_mp_fghr = _T_250 ? ghr_d : ghr_x; // @[exu.scala 212:39]
  assign io_exu_bp_exu_mp_index = final_predpipe_mp[12:5]; // @[exu.scala 213:39]
  assign io_exu_bp_exu_mp_btag = final_predpipe_mp[4:0]; // @[exu.scala 214:39]
  assign io_exu_flush_final = i_alu_io_flush_final_out; // @[exu.scala 143:27]
@ -2644,7 +2650,7 @@ module exu(
  assign io_exu_div_wren = i_div_io_exu_div_wren; // @[exu.scala 159:41]
  assign io_lsu_exu_exu_lsu_rs1_d = _T_135 | _T_134; // @[exu.scala 113:27]
  assign io_lsu_exu_exu_lsu_rs2_d = _T_148 | _T_149; // @[exu.scala 119:27]
-  assign io_exu_flush_path_final = _T_216 | _T_217; // @[exu.scala 236:33]
+  assign io_exu_flush_path_final = _T_260 | _T_261; // @[exu.scala 236:33]
  assign rvclkhdr_io_clk = clock; // @[lib.scala 401:18]
  assign rvclkhdr_io_en = x_data_en & io_dec_exu_decode_exu_dec_i0_branch_d; // @[lib.scala 402:17]
  assign rvclkhdr_1_io_clk = clock; // @[lib.scala 401:18]
@ -2725,12 +2731,12 @@ module exu(
  assign i_alu_io_pp_in_bits_prett = io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett; // @[exu.scala 133:45]
  assign i_mul_clock = clock;
  assign i_mul_reset = reset;
-  assign i_mul_io_mul_p_valid = io_dec_exu_decode_exu_mul_p_valid; // @[exu.scala 149:41]
-  assign i_mul_io_mul_p_bits_rs1_sign = io_dec_exu_decode_exu_mul_p_bits_rs1_sign; // @[exu.scala 149:41]
-  assign i_mul_io_mul_p_bits_rs2_sign = io_dec_exu_decode_exu_mul_p_bits_rs2_sign; // @[exu.scala 149:41]
-  assign i_mul_io_mul_p_bits_low = io_dec_exu_decode_exu_mul_p_bits_low; // @[exu.scala 149:41]
-  assign i_mul_io_rs1_in = muldiv_rs1_d & _T_161; // @[exu.scala 150:41]
-  assign i_mul_io_rs2_in = i0_rs2_d & _T_161; // @[exu.scala 151:41]
+  assign i_mul_io_mul_p_valid = _T_183[19]; // @[exu.scala 149:25]
+  assign i_mul_io_mul_p_bits_rs1_sign = _T_183[18]; // @[exu.scala 149:25]
+  assign i_mul_io_mul_p_bits_rs2_sign = _T_183[17]; // @[exu.scala 149:25]
+  assign i_mul_io_mul_p_bits_low = _T_183[16]; // @[exu.scala 149:25]
+  assign i_mul_io_rs1_in = muldiv_rs1_d & _T_205; // @[exu.scala 150:41]
+  assign i_mul_io_rs2_in = i0_rs2_d & _T_205; // @[exu.scala 151:41]
  assign i_div_clock = clock;
  assign i_div_reset = reset;
  assign i_div_io_dividend = _T_156 | _T_99; // @[exu.scala 157:33]
@ -3095,7 +3101,7 @@ end // initial
      ghr_x <= 8'h0;
    end else if (x_ctl_en) begin
      if (i0_valid_x) begin
-        ghr_x <= _T_191;
+        ghr_x <= _T_235;
      end
    end
  end
--- a/src/main/scala/exu/exu.scala
+++ b/src/main/scala/exu/exu.scala
@ -146,7 +146,7 @@ class exu extends Module with lib with RequireAsyncReset{

  val i_mul = Module(new exu_mul_ctl())
  i_mul.io.scan_mode	:= io.scan_mode
-  i_mul.io.mul_p			:= io.dec_exu.decode_exu.mul_p // & Fill(io.dec_exu.decode_exu.mul_p.getWidth,io.dec_exu.decode_exu.mul_p.valid)
+  i_mul.io.mul_p	:= VecInit.tabulate(io.dec_exu.decode_exu.mul_p.getElements.size-1)(i=>io.dec_exu.decode_exu.mul_p.getElements(i).asUInt & Fill(io.dec_exu.decode_exu.mul_p.getElements.size,io.dec_exu.decode_exu.mul_p.valid)).asTypeOf(io.dec_exu.decode_exu.mul_p) //& io.dec_exu.decode_exu.mul_p.valid
  i_mul.io.rs1_in			:= muldiv_rs1_d & Fill(32,io.dec_exu.decode_exu.mul_p.valid)
  i_mul.io.rs2_in			:=  i0_rs2_d & Fill(32,io.dec_exu.decode_exu.mul_p.valid)
  val mul_result_x		=  i_mul.io.result_x
--- a/target/scala-2.12/classes/exu/exu.class
+++ b/target/scala-2.12/classes/exu/exu.class
--- a/target/scala-2.12/classes/exu/exu_main$.class
+++ b/target/scala-2.12/classes/exu/exu_main$.class