diff --git a/design/src/main/scala/lsu/lsu_bus_intf.scala b/design/src/main/scala/lsu/lsu_bus_intf.scala
index 227f23a6..d5525c3f 100644
--- a/design/src/main/scala/lsu/lsu_bus_intf.scala
+++ b/design/src/main/scala/lsu/lsu_bus_intf.scala
@@ -47,7 +47,6 @@ class  lsu_bus_intf extends Module with RequireAsyncReset with lib {
     val lsu_bus_buffer_pend_any       = Output(Bool())
     val lsu_bus_buffer_full_any       = Output(Bool())
     val lsu_bus_buffer_empty_any      = Output(Bool())
-    //val lsu_bus_idle_any              = Output(Bool())
     val bus_read_data_m               = Output(UInt(32.W))
     val lsu_nonblock_load_data        = Output((UInt(32.W)))
     val dctl_busbuff = new dctl_busbuff()
@@ -135,7 +134,6 @@ class  lsu_bus_intf extends Module with RequireAsyncReset with lib {
   io.lsu_bus_buffer_pend_any         := bus_buffer.io.lsu_bus_buffer_pend_any
   io.lsu_bus_buffer_full_any         := bus_buffer.io.lsu_bus_buffer_full_any
   io.lsu_bus_buffer_empty_any        := bus_buffer.io.lsu_bus_buffer_empty_any
-  //io.lsu_bus_idle_any                := bus_buffer.io.lsu_bus_idle_any
   ld_byte_hit_buf_lo                 := bus_buffer.io.ld_byte_hit_buf_lo
   ld_byte_hit_buf_hi                 := bus_buffer.io.ld_byte_hit_buf_hi
   ld_fwddata_buf_lo                  := bus_buffer.io.ld_fwddata_buf_lo
@@ -202,4 +200,4 @@ class  lsu_bus_intf extends Module with RequireAsyncReset with lib {
 }
 object bus_intf extends App {
   println((new chisel3.stage.ChiselStage).emitVerilog(new lsu_bus_intf()))
-}
\ No newline at end of file
+}