This commit is contained in:
waleed-lm 2020-10-29 15:05:48 +05:00
parent eb0a5636fc
commit b328da3cec
8 changed files with 13026 additions and 13222 deletions

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@ -114,13 +114,6 @@
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit" "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit"
] ]
}, },
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_test",
"sources":[
"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dma_mem_wdata"
]
},
{ {
"class":"firrtl.transforms.CombinationalPath", "class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_debug_rd_en", "sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_debug_rd_en",

File diff suppressed because it is too large Load Diff

File diff suppressed because it is too large Load Diff

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@ -126,7 +126,7 @@ class mem_ctl_bundle extends Bundle with el2_lib{
val iccm_buf_correct_ecc = Output(Bool()) val iccm_buf_correct_ecc = Output(Bool())
val iccm_correction_state = Output(Bool()) val iccm_correction_state = Output(Bool())
val scan_mode = Input(Bool()) val scan_mode = Input(Bool())
val test = Output(UInt())
} }
class el2_ifu_mem_ctl extends Module with el2_lib { class el2_ifu_mem_ctl extends Module with el2_lib {
val io = IO(new mem_ctl_bundle) val io = IO(new mem_ctl_bundle)
@ -633,7 +633,7 @@ class el2_ifu_mem_ctl extends Module with el2_lib {
io.iccm_rden := (ifc_dma_access_q_ok & io.dma_iccm_req & !io.dma_mem_write) | (io.ifc_iccm_access_bf & io.ifc_fetch_req_bf) io.iccm_rden := (ifc_dma_access_q_ok & io.dma_iccm_req & !io.dma_mem_write) | (io.ifc_iccm_access_bf & io.ifc_fetch_req_bf)
val iccm_dma_rden = ifc_dma_access_q_ok & io.dma_iccm_req & !io.dma_mem_write val iccm_dma_rden = ifc_dma_access_q_ok & io.dma_iccm_req & !io.dma_mem_write
io.iccm_wr_size := Fill(3, io.dma_iccm_req) & io.dma_mem_sz io.iccm_wr_size := Fill(3, io.dma_iccm_req) & io.dma_mem_sz
io.test := rvecc_encode(io.dma_mem_wdata(31,0))
val dma_mem_ecc = Cat(rvecc_encode(io.dma_mem_wdata(63,32)), rvecc_encode(io.dma_mem_wdata(31,0))) val dma_mem_ecc = Cat(rvecc_encode(io.dma_mem_wdata(63,32)), rvecc_encode(io.dma_mem_wdata(31,0)))
val iccm_ecc_corr_data_ff = WireInit(UInt(39.W), 0.U) val iccm_ecc_corr_data_ff = WireInit(UInt(39.W), 0.U)
io.iccm_wr_data := Mux(iccm_correct_ecc & !(ifc_dma_access_q_ok & io.dma_iccm_req), Fill(2,iccm_ecc_corr_data_ff), io.iccm_wr_data := Mux(iccm_correct_ecc & !(ifc_dma_access_q_ok & io.dma_iccm_req), Fill(2,iccm_ecc_corr_data_ff),
@ -713,8 +713,6 @@ class el2_ifu_mem_ctl extends Module with el2_lib {
val way_status_new = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U) val way_status_new = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U)
val way_status_new_w_debug = Mux(io.ic_debug_wr_en & io.ic_debug_tag_array, val way_status_new_w_debug = Mux(io.ic_debug_wr_en & io.ic_debug_tag_array,
if (ICACHE_STATUS_BITS == 1) io.ic_debug_wr_data(4) else io.ic_debug_wr_data(6, 4), way_status_new) if (ICACHE_STATUS_BITS == 1) io.ic_debug_wr_data(4) else io.ic_debug_wr_data(6, 4), way_status_new)
// io.test := way_status_new_w_debug
val way_status_new_ff = withClock(io.free_clk) { val way_status_new_ff = withClock(io.free_clk) {
RegNext(way_status_new_w_debug, 0.U) RegNext(way_status_new_w_debug, 0.U)
} }