diff --git a/project/target/scala-2.12/sbt-1.0/update/update_cache_2.12/output b/project/target/scala-2.12/sbt-1.0/update/update_cache_2.12/output
index bb80afd9..aeee154c 100644
--- a/project/target/scala-2.12/sbt-1.0/update/update_cache_2.12/output
+++ b/project/target/scala-2.12/sbt-1.0/update/update_cache_2.12/output
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diff --git a/src/main/resources/vsrc/mem.sv b/src/main/resources/vsrc/mem.sv
index a2f38b9f..2addbc79 100644
--- a/src/main/resources/vsrc/mem.sv
+++ b/src/main/resources/vsrc/mem.sv
@@ -51,7 +51,7 @@ module mem
    input [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt_RM_3,
    input [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt_LS,
    input [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt_DS,
-    input [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt_SD,
+   input [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt_SD,
    input [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt_RNM,
    input [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt_BC1,
    input [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt_BC2, 
diff --git a/target/scala-2.12/classes/dbg/dbg.class b/target/scala-2.12/classes/dbg/dbg.class
index f94d6785..38d4fab9 100644
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diff --git a/target/scala-2.12/classes/dec/CSR_IO.class b/target/scala-2.12/classes/dec/CSR_IO.class
index 25e04e4b..8295dc37 100644
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diff --git a/target/scala-2.12/classes/dec/csr_tlu.class b/target/scala-2.12/classes/dec/csr_tlu.class
index d4710377..88ccb0e8 100644
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diff --git a/target/scala-2.12/classes/dec/dec.class b/target/scala-2.12/classes/dec/dec.class
index c63d3dd9..8027ba0a 100644
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diff --git a/target/scala-2.12/classes/dec/dec_IO.class b/target/scala-2.12/classes/dec/dec_IO.class
index f8fe14b3..9cb332e5 100644
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diff --git a/target/scala-2.12/classes/dec/dec_dec_ctl.class b/target/scala-2.12/classes/dec/dec_dec_ctl.class
index 1330a448..527570a1 100644
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diff --git a/target/scala-2.12/classes/dec/dec_decode_ctl.class b/target/scala-2.12/classes/dec/dec_decode_ctl.class
index 9105d3f3..eac8579e 100644
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diff --git a/target/scala-2.12/classes/dec/dec_gpr_ctl.class b/target/scala-2.12/classes/dec/dec_gpr_ctl.class
index b53b434f..b8e48087 100644
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diff --git a/target/scala-2.12/classes/dec/dec_ib_ctl.class b/target/scala-2.12/classes/dec/dec_ib_ctl.class
index 6e18c7b1..dbb38277 100644
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diff --git a/target/scala-2.12/classes/dec/dec_ib_ctl_IO.class b/target/scala-2.12/classes/dec/dec_ib_ctl_IO.class
index 43656d2f..9a42152d 100644
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diff --git a/target/scala-2.12/classes/dec/dec_timer_ctl.class b/target/scala-2.12/classes/dec/dec_timer_ctl.class
index 3b62a7c6..d0aca9f3 100644
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diff --git a/target/scala-2.12/classes/dec/dec_tlu_ctl.class b/target/scala-2.12/classes/dec/dec_tlu_ctl.class
index ab7e2f18..4b807c44 100644
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diff --git a/target/scala-2.12/classes/dec/dec_tlu_ctl_IO.class b/target/scala-2.12/classes/dec/dec_tlu_ctl_IO.class
index c8b29ca7..e55cdc49 100644
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diff --git a/target/scala-2.12/classes/dec/dec_trigger.class b/target/scala-2.12/classes/dec/dec_trigger.class
index 3430b264..2ab4f2a8 100644
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diff --git a/target/scala-2.12/classes/dec/int_exc.class b/target/scala-2.12/classes/dec/int_exc.class
index cb1ea332..40da5f62 100644
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diff --git a/target/scala-2.12/classes/dec/perf_csr.class b/target/scala-2.12/classes/dec/perf_csr.class
index 824582c5..594b9dbc 100644
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diff --git a/target/scala-2.12/classes/dec/perf_mux_and_flops.class b/target/scala-2.12/classes/dec/perf_mux_and_flops.class
index f7d6dc7e..36d2f257 100644
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diff --git a/target/scala-2.12/classes/exu/exu.class b/target/scala-2.12/classes/exu/exu.class
index dcf797ba..ce0453c0 100644
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diff --git a/target/scala-2.12/classes/exu/exu_alu_ctl.class b/target/scala-2.12/classes/exu/exu_alu_ctl.class
index 64ddd362..c094cc14 100644
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diff --git a/target/scala-2.12/classes/exu/exu_div_ctl.class b/target/scala-2.12/classes/exu/exu_div_ctl.class
index c2f88d4a..4aecb6a2 100644
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diff --git a/target/scala-2.12/classes/exu/exu_div_existing_1bit_cheapshortq.class b/target/scala-2.12/classes/exu/exu_div_existing_1bit_cheapshortq.class
index 6f219bcf..a38aa150 100644
Binary files a/target/scala-2.12/classes/exu/exu_div_existing_1bit_cheapshortq.class and b/target/scala-2.12/classes/exu/exu_div_existing_1bit_cheapshortq.class differ
diff --git a/target/scala-2.12/classes/exu/exu_div_new_1bit_fullshortq.class b/target/scala-2.12/classes/exu/exu_div_new_1bit_fullshortq.class
index c650da09..8e404c77 100644
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diff --git a/target/scala-2.12/classes/exu/exu_div_new_2bit_fullshortq.class b/target/scala-2.12/classes/exu/exu_div_new_2bit_fullshortq.class
index e4b77a92..124c2d93 100644
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diff --git a/target/scala-2.12/classes/exu/exu_div_new_3bit_fullshortq.class b/target/scala-2.12/classes/exu/exu_div_new_3bit_fullshortq.class
index 9fa668b8..ebc3c940 100644
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diff --git a/target/scala-2.12/classes/exu/exu_div_new_4bit_fullshortq.class b/target/scala-2.12/classes/exu/exu_div_new_4bit_fullshortq.class
index 0b13a8d9..ce37b66d 100644
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diff --git a/target/scala-2.12/classes/exu/exu_mul_ctl.class b/target/scala-2.12/classes/exu/exu_mul_ctl.class
index 8abc5504..aad37c73 100644
Binary files a/target/scala-2.12/classes/exu/exu_mul_ctl.class and b/target/scala-2.12/classes/exu/exu_mul_ctl.class differ
diff --git a/target/scala-2.12/classes/ifu/ifu_mem_ctl.class b/target/scala-2.12/classes/ifu/ifu_mem_ctl.class
index 5a0c00bb..228f4260 100644
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diff --git a/target/scala-2.12/classes/ifu/mem_ctl_io.class b/target/scala-2.12/classes/ifu/mem_ctl_io.class
index 50dece07..3a483256 100644
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diff --git a/target/scala-2.12/classes/lsu/lsu.class b/target/scala-2.12/classes/lsu/lsu.class
index 7caaea7d..4519a4bb 100644
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diff --git a/target/scala-2.12/classes/lsu/lsu_addrcheck.class b/target/scala-2.12/classes/lsu/lsu_addrcheck.class
index 41d940b1..f46c1cae 100644
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diff --git a/target/scala-2.12/classes/lsu/lsu_bus_buffer.class b/target/scala-2.12/classes/lsu/lsu_bus_buffer.class
index 1bfaf10f..4911d68c 100644
Binary files a/target/scala-2.12/classes/lsu/lsu_bus_buffer.class and b/target/scala-2.12/classes/lsu/lsu_bus_buffer.class differ
diff --git a/target/scala-2.12/classes/lsu/lsu_bus_intf.class b/target/scala-2.12/classes/lsu/lsu_bus_intf.class
index 661d46fc..e5427764 100644
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diff --git a/target/scala-2.12/classes/lsu/lsu_clkdomain.class b/target/scala-2.12/classes/lsu/lsu_clkdomain.class
index f73ab210..76f5e044 100644
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diff --git a/target/scala-2.12/classes/lsu/lsu_dccm_ctl.class b/target/scala-2.12/classes/lsu/lsu_dccm_ctl.class
index 1dd441e1..6c03974e 100644
Binary files a/target/scala-2.12/classes/lsu/lsu_dccm_ctl.class and b/target/scala-2.12/classes/lsu/lsu_dccm_ctl.class differ
diff --git a/target/scala-2.12/classes/lsu/lsu_ecc.class b/target/scala-2.12/classes/lsu/lsu_ecc.class
index acfa8889..39471656 100644
Binary files a/target/scala-2.12/classes/lsu/lsu_ecc.class and b/target/scala-2.12/classes/lsu/lsu_ecc.class differ
diff --git a/target/scala-2.12/classes/lsu/lsu_stbuf.class b/target/scala-2.12/classes/lsu/lsu_stbuf.class
index 5a877f0c..655026b8 100644
Binary files a/target/scala-2.12/classes/lsu/lsu_stbuf.class and b/target/scala-2.12/classes/lsu/lsu_stbuf.class differ
diff --git a/target/scala-2.12/classes/lsu/lsu_trigger.class b/target/scala-2.12/classes/lsu/lsu_trigger.class
index 7534b192..8cfd0802 100644
Binary files a/target/scala-2.12/classes/lsu/lsu_trigger.class and b/target/scala-2.12/classes/lsu/lsu_trigger.class differ
diff --git a/target/scala-2.12/classes/pic_ctrl.class b/target/scala-2.12/classes/pic_ctrl.class
index a33aca73..7e36edc3 100644
Binary files a/target/scala-2.12/classes/pic_ctrl.class and b/target/scala-2.12/classes/pic_ctrl.class differ
diff --git a/target/scala-2.12/classes/vsrc/mem.sv b/target/scala-2.12/classes/vsrc/mem.sv
index a2f38b9f..2addbc79 100644
--- a/target/scala-2.12/classes/vsrc/mem.sv
+++ b/target/scala-2.12/classes/vsrc/mem.sv
@@ -51,7 +51,7 @@ module mem
    input [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt_RM_3,
    input [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt_LS,
    input [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt_DS,
-    input [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt_SD,
+   input [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt_SD,
    input [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt_RNM,
    input [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt_BC1,
    input [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt_BC2, 
diff --git a/target/scala-2.12/quasar_2.12-3.3.0.jar b/target/scala-2.12/quasar_2.12-3.3.0.jar
index 11a558f6..0e7d80d8 100644
Binary files a/target/scala-2.12/quasar_2.12-3.3.0.jar and b/target/scala-2.12/quasar_2.12-3.3.0.jar differ
diff --git a/target/streams/compile/_global/_global/compileOutputs/previous b/target/streams/compile/_global/_global/compileOutputs/previous
index 347cdd37..2801cdbb 100644
--- a/target/streams/compile/_global/_global/compileOutputs/previous
+++ b/target/streams/compile/_global/_global/compileOutputs/previous
@@ -1 +1 @@
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diff --git a/target/streams/compile/_global/_global/compileSourceFileInputs/previous b/target/streams/compile/_global/_global/compileSourceFileInputs/previous
index a780d6d3..b1cb9e3d 100644
--- a/target/streams/compile/_global/_global/compileSourceFileInputs/previous
+++ b/target/streams/compile/_global/_global/compileSourceFileInputs/previous
@@ -1 +1 @@
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\ No newline at end of file
+["sbt.Task[scala.collection.immutable.Map[java.lang.String, scala.collection.Seq[scala.Tuple2[java.nio.file.Path, sbt.nio.FileStamp]]]]",{"2.12.10":{"hashes":[["/home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/pic_ctrl.scala","b3a83a14efc2b76a42f5a92d151d20e1bd5ae760"],["/home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/quasar_wrapper.scala","0c7f7f1acb879e56bdbbdb32fe0b9630707285e0"],["/home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/mem.scala","23d7d56e643e1a416022f38e5d5995629f2b97fb"],["/home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/dma_ctrl.scala","b8e225536e9f01272767e29ea08119dcb30bcd8d"],["/home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/quasar.scala","d3d9da792f621f71cfbb67d06876dc7d9ca08a28"],["/home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/lsu/lsu_addrcheck.scala","163405f917888a3dfc1bfc81f9400432716b2557"],["/home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/lsu/lsu_dccm_ctl.scala","752952b9b1b38cc765fcee9b140fc1906f1093e3"],["/home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/lsu/lsu_bus_intf.scala","23551831d3bcf2dab1a70557482bc2b51a5e4d3e"],["/home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/lsu/lsu.scala","71b68bb227ae4f065e720069a2917466fd107e29"],["/home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/lsu/lsu_lsc_ctl.scala","a5dc3483769aa7cd5f699caf0528aad49feaab92"],["/home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/lsu/lsu_ecc.scala","454229506cdaaa5be4edc30ca5f00e1bbb1dab52"],["/home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/lsu/lsu_stbuf.scala","8ec5a04ee60b3e2b410b9d0d6502424cb63163e2"],["/home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/lsu/lsu_clkdomain.scala","56318d3440b8789f00516707ed275be22baf08ab"],["/home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/lsu/lsu_bus_buffer.scala","eabaf71ae3cdb38ceb5cd2baade885ac432c4e6c"],["/home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/lsu/lsu_trigger.scala","87c6eede45fe856535818e6a3e7c109ca2ca8677"],["/home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/lib/param.scala","90cbd6fd918a44fca6f064b634f3f6bdf40a86c5"],["/home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/lib/lib.scala","84bbb8572c80326829c271444d5660c8416211e7"],["/home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/lib/axi4_to_ahb.scala","08c67f01dd0ee0e389b7100e331ae0c5c14e9273"],["/home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/lib/ahb_to_axi4.scala","5445e534b8e8012105168a357edab9e116506d15"],["/home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/dec/dec_gpr_ctl.scala","a3561b0cb6596ed2b0da8a9f92886d00eedbfa86"],["/home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/dec/dec_dec_ctl.scala","4913c55d3954dcd5657ea07196e741bdafd2ea76"],["/home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/dec/dec_trigger.scala","cb83a19d8b65a41e5dc8a61e2b4198c362c2d912"],["/home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/dec/dec_tlu_ctl.scala","2337e7dd9c7f7247a02fac4c7f1914c23b72bd6e"],["/home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/dec/dec.scala","247a898c5f047868e11499b417d67e9b2b075f11"],["/home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/dec/dec_ib_ctl.scala","e8783f17e67d4511d4ae9388b4f7b2a71d5c787b"],["/home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/dec/dec_decode_ctl.scala","14291d5e8ad2bce64efa77b64e9bb8cff2e1ae48"],["/home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/ifu/ifu_mem_ctl.scala","44004d72aebbf39dc21ed3f0a1412c8103267e50"],["/home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/ifu/ifu_aln_ctl.scala","228420c174c04700bbf88f194b60abe2e6f73d67"],["/home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/ifu/ifu_bp_ctl.scala","c4f5d39c3db1bd26483e4a3432a2138b6678919b"],["/home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/ifu/ifu_ifc_ctl.scala","602754b7f9a7c78748732c9187c4e6f44d3c5139"],["/home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/ifu/ifu.scala","470253c0875a0de1e99906737ad94564d27f162b"],["/home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/ifu/ifu_compress_ctl.scala","be2d9c3a907ea7a8cc3eb487eb2a46b23c32dd25"],["/home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/dmi/dmi_wrapper.scala","619171c0b49373f3aaf18f92aa659d8c05acbdfa"],["/home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/include/bundle.scala","93fee15ef2d3b9b77e507ee0b6be0fa54d56d144"],["/home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/dbg/dbg.scala","b037182721d8153fd31ab2515ac3f7c3b55cf4c1"],["/home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/exu/exu_div_ctl.scala","8cf13bfbcd63c64527ed7d4167bef6d747a1dd76"],["/home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/exu/exu.scala","c1c69499926b9dfe8c5691dcd027aa800c7215c7"],["/home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/exu/exu_alu_ctl.scala","420d5524f7b02604625f57252539e20602ca1cf5"],["/home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/exu/exu_mul_ctl.scala","77ef042e5ea6ddc93da4fe2220717e362f813c1e"]],"lastModifiedTimes":[]}}]
\ No newline at end of file
diff --git a/target/streams/compile/_global/_global/discoveredMainClasses/data b/target/streams/compile/_global/_global/discoveredMainClasses/data
index b3795d8d..b68e726c 100644
--- a/target/streams/compile/_global/_global/discoveredMainClasses/data
+++ b/target/streams/compile/_global/_global/discoveredMainClasses/data
@@ -1 +1 @@
-["lsu.buffer","lsu.bus_intf","lsu.clkdomain","lsu.dccm_ctl","lsu.lsc_ctl","lsu.lsu_main","lsu.stbuf"]
\ No newline at end of file
+["DMA","QUASAR","QUASAR_Wrp","dbg.debug","dec.dec_dec","dec.dec_main","dec.tlu","exu.div_main","exu.exu_main","exu.mul","ifu.ifu_top","lib.axi4_to_ahb","lsu.buffer","lsu.bus_intf","lsu.clkdomain","lsu.dccm_ctl","lsu.lsc_ctl","lsu.lsu_main","lsu.stbuf","pic"]
\ No newline at end of file
diff --git a/target/streams/compile/compile/_global/streams/out b/target/streams/compile/compile/_global/streams/out
index 3c9adbe7..ea5dd370 100644
--- a/target/streams/compile/compile/_global/streams/out
+++ b/target/streams/compile/compile/_global/streams/out
@@ -1,2 +1,10 @@
-[warn] there were 337 feature warnings; re-run with -feature for details
-[warn] one warning found
+[warn] /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/lib/lib.scala:25:5: match may not be exhaustive.
+[warn] It would fail on the following inputs: (0, _), (1, _), (??, _), (_, 0), (_, 1), (_, ??), (_, _)
+[warn]     (ICACHE_WAYPACK, ICACHE_ECC) match{
+[warn]     ^
+[warn] /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/quasar.scala:326:8: Generated class QUASAR differs only in case from quasar.
+[warn]   Such classes will overwrite one another on case-insensitive filesystems.
+[warn] object QUASAR extends App {
+[warn]        ^
+[warn] there were 5450 feature warnings; re-run with -feature for details
+[warn] three warnings found
diff --git a/target/streams/compile/compileIncSetup/_global/streams/inc_compile_2.12.zip b/target/streams/compile/compileIncSetup/_global/streams/inc_compile_2.12.zip
index dfa3e73c..0be83c1e 100644
Binary files a/target/streams/compile/compileIncSetup/_global/streams/inc_compile_2.12.zip and b/target/streams/compile/compileIncSetup/_global/streams/inc_compile_2.12.zip differ
diff --git a/target/streams/compile/compileIncremental/_global/streams/export b/target/streams/compile/compileIncremental/_global/streams/export
index b134593d..9a0d84ef 100644
--- a/target/streams/compile/compileIncremental/_global/streams/export
+++ b/target/streams/compile/compileIncremental/_global/streams/export
@@ -1 +1 @@
-scalac -bootclasspath /home/laraibkhan/.sbt/boot/scala-2.12.10/lib/scala-library.jar -classpath /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar:/home/laraibkhan/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar -Xplugin:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalamacros/paradise_2.12.10/2.1.0/paradise_2.12.10-2.1.0.jar -Xsource:2.11.0 /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/lsu/lsu_bus_buffer.scala
+scalac -bootclasspath /home/laraibkhan/.sbt/boot/scala-2.12.10/lib/scala-library.jar -classpath /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar:/home/laraibkhan/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar -Xplugin:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalamacros/paradise_2.12.10/2.1.0/paradise_2.12.10-2.1.0.jar -Xsource:2.11.0 /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/pic_ctrl.scala /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/quasar_wrapper.scala /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/mem.scala /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/dma_ctrl.scala /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/quasar.scala /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/lsu/lsu_addrcheck.scala /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/lsu/lsu_dccm_ctl.scala /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/lsu/lsu_bus_intf.scala /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/lsu/lsu.scala /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/lsu/lsu_lsc_ctl.scala /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/lsu/lsu_ecc.scala /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/lsu/lsu_stbuf.scala /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/lsu/lsu_clkdomain.scala /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/lsu/lsu_bus_buffer.scala /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/lsu/lsu_trigger.scala /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/lib/param.scala /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/lib/lib.scala /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/lib/axi4_to_ahb.scala /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/lib/ahb_to_axi4.scala /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/dec/dec_gpr_ctl.scala /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/dec/dec_dec_ctl.scala /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/dec/dec_trigger.scala /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/dec/dec_tlu_ctl.scala /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/dec/dec.scala /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/dec/dec_ib_ctl.scala /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/dec/dec_decode_ctl.scala /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/ifu/ifu_mem_ctl.scala /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/ifu/ifu_aln_ctl.scala /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/ifu/ifu_bp_ctl.scala /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/ifu/ifu_ifc_ctl.scala /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/ifu/ifu.scala /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/ifu/ifu_compress_ctl.scala /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/dmi/dmi_wrapper.scala /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/include/bundle.scala /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/dbg/dbg.scala /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/exu/exu_div_ctl.scala /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/exu/exu.scala /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/exu/exu_alu_ctl.scala /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/exu/exu_mul_ctl.scala
diff --git a/target/streams/compile/compileIncremental/_global/streams/out b/target/streams/compile/compileIncremental/_global/streams/out
index 7ef19cc0..db82c7f5 100644
--- a/target/streams/compile/compileIncremental/_global/streams/out
+++ b/target/streams/compile/compileIncremental/_global/streams/out
@@ -1 +1,83 @@
-[debug] No changes
+[debug] 
+[debug] Initial source changes: 
+[debug] 	removed:Set()
+[debug] 	added: Set()
+[debug] 	modified: Set(/home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/ifu/ifu.scala, /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/lib/axi4_to_ahb.scala, /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/lsu/lsu_dccm_ctl.scala, /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/ifu/ifu_compress_ctl.scala, /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/dec/dec_ib_ctl.scala, /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/exu/exu_mul_ctl.scala, /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/pic_ctrl.scala, /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/ifu/ifu_ifc_ctl.scala, /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/mem.scala, /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/ifu/ifu_bp_ctl.scala, /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/dbg/dbg.scala, /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/lib/param.scala, /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/ifu/ifu_aln_ctl.scala, /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/quasar.scala, /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/exu/exu.scala, /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/dec/dec_dec_ctl.scala, /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/dec/dec_decode_ctl.scala, /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/dec/dec.scala, /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/dec/dec_tlu_ctl.scala, /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/include/bundle.scala, /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/lsu/lsu_lsc_ctl.scala, /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/quasar_wrapper.scala, /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/dec/dec_gpr_ctl.scala, /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/dma_ctrl.scala, /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/lib/lib.scala, /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/lib/ahb_to_axi4.scala, /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/exu/exu_div_ctl.scala, /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/lsu/lsu_bus_buffer.scala, /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/lsu/lsu.scala, /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/lsu/lsu_bus_intf.scala, /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/exu/exu_alu_ctl.scala, /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/ifu/ifu_mem_ctl.scala)
+[debug] Invalidated products: Set(/home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lib/param.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lib/lib$rvclkhdr.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dec/dec_dec_ctl.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/buffer$delayedInit$body.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/bus_intf$.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/dec_mem_ctrl.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/br_pkt_t.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lib/axi4_to_ahb.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/ifu/ifu_compress_ctl.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/write_resp.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dec/dec_ib_ctl.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dmi/dmi_wrapper.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dbg/sb_state_t$.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/read_data$.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/ifu/ifu_aln_ctl$$anon$1.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/lsu_trigger$$anon$1.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/lsu_clkdomain$$anon$1.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/ifu/ifu_mem_ctl.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/lsu_exu.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/ahb_in.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/predict_pkt_t.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lib/lib$rvecc_encode$$anon$2.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/bus_intf.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dbg/state_t$.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/tlu_busbuff.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/axi_channels$.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dec/dec_timer_ctl.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/exu/exu_alu_ctl$$anon$1.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/ib_exu.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/dccm_ctl$.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/tlu_dma.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/lsu_main$delayedInit$body.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/dma_mem_ctl.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/lsu_dccm_ctl.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/ccm_ext_in_pkt_t.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/dctl_busbuff.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/lsu_addrcheck.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/lsu.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/lsu_lsc_ctl$$anon$1.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/exu_bp.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/dec_pic.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/axi_channels.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dma_ctrl.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/exu/exu_div_ctl$$anon$1.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lib/lib$rvdffe$.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/exu/exu.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/aln_dec.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/gpr_exu.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dbg/dbg_dma.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lib/ahb_to_axi4$$anon$1.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/write_data.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lib/ahb_to_axi4$$anon$1$$anon$2.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/clkdomain.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/lsu_bus_intf$$anon$1.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/decode_exu.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/dccm_ctl$delayedInit$body.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dmi/dmi_wrapper$$anon$1.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/stbuf$delayedInit$body.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lib/axi4_to_ahb_IO.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dec/dec_trigger.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/cache_debug_pkt_t.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/lsu_pic.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/mem/mem_lsu.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/write_addr$.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lib/lib$rvoclkhdr$.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dbg/sb_state_t.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/lsu_error_pkt_t.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/lsu_bus_buffer$$anon$1.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/mul_pkt_t.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/lsu_stbuf$$anon$1.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/stbuf$.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/lsu_dec.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/lsu_tlu.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/mem/quasar$mem.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/lsu_clkdomain.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/exu/exu_mul_ctl.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dec/CSRs.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/mem/quasar$.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/lsu_pkt_t.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lib/lib$rvclkhdr$$anon$5.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/lsu_bus_buffer.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lib/lib$gated_latch$$anon$4.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/tlu_exu.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dec/dec_tlu_ctl_IO.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/ahb_channel.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/alu_pkt_t.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dec/dec.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/dec_aln.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/lsu_trigger.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lib/lib$$anon$1.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dec/dec_dec_ctl$$anon$1.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/lsu_main.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/dccm_ext_in_pkt_t.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/exu/exu_alu_ctl.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dec/csr_tlu.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/trap_pkt_t.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/ifu/ifu$$anon$1.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/ahb_out_dma.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/mem/Mem_bundle.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/lsu_lsc_ctl.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dbg/dbg$$anon$1.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lib/lib$rvdff_fpga$.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lib/lib$rvclkhdr$.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/stbuf.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/pic_ctrl$$anon$1.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/class_pkt_t.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/exu/exu$$anon$1.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lib/lib.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dec/dec_gpr_ctl_IO.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/ahb_out.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/dma_dccm_ctl.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/iccm_mem.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/dest_pkt_t.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dec/dec_decode_csr_read.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/mem/quasar.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dec/dec_decode_ctl.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/dbg_ib.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/lsu_main$.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/exu_ifu.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lib/lib$rvecc_encode_64$$anon$3.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/lsu_stbuf.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/lsu_bus_intf.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/read_addr$.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lib/lib$rvecc_encode_64.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/exu/exu_div_ctl.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/inst_pkt_t.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dec/dec_ib_ctl_IO.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/dec_tlu_csr_pkt.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/div_pkt_t.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/dec_pkt_t.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dec/dec_decode_csr_read_IO.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/lsu_ecc$$anon$1.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/lsc_ctl.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/buffer.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dma_ctrl$$anon$1.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/write_addr.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/read_data.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dec/CSR_VAL.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/lsu_dccm_ctl$$anon$1.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/inst_pkt_t$.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/dec_dbg.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dbg/dbg.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/lsu_dma.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dec/dec_timer_ctl_IO.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/ifu/ifu_ifc_ctl$$anon$1.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dbg/state_t.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/trace_pkt_t.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/clkdomain$delayedInit$body.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/rets_pkt_t.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/ifu_dma.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/dma_lsc_ctl.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/dctl_dma.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/ifu/ifu_bp_ctl$$anon$1.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/ifu/ifu.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/ifu_dec.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/exu/exu_mul_ctl$$anon$1.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lib/lib$rvdffs_fpga$.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/lsc_ctl$delayedInit$body.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dec/dec_tlu_ctl.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dec/dec_decode_ctl$$anon$1.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/dma_ifc.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/dec_exu.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lib/lib$gated_latch.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lib/ahb_to_axi4.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dmi/dmi_wrapper_module$$anon$2.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/ic_data_ext_in_pkt_t.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/read_addr.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/aln_ib.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/ifu/ifu_compress_ctl$$anon$1.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dmi/dmi_wrapper_module.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/dec_bp.class, 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/home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/dec_dma.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/buffer$.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/ic_tag_ext_in_pkt_t.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/load_cam_pkt_t.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/ifu/mem_ctl_io.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lib/lib$rvecc_encode.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lib/lib$rvsyncss$.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dec/dec_gpr_ctl.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/dec_ifc.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/lsu_ecc.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/br_tlu_pkt_t.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/lsu_addrcheck$$anon$1.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/dec_div.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dec/dec_trigger$$anon$1.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/ic_mem.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/ifu/ifu_bp_ctl.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/pic_ctrl.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dec/CSR_IO.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/mem/blackbox_mem.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/include/dec_alu.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/dec/dec_IO.class, /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lib/axi4_to_ahb$.class)
+[debug] External API changes: API Changes: Set()
+[debug] Modified binary dependencies: Set()
+[debug] Initial directly invalidated classes: Set(include.class_pkt_t, include.dbg_ib, dec.dec, include.dec_alu, exu.exu, dec.dec_decode_ctl, include.lsu_dma, lib.axi4_to_ahb_IO, lib.lib.gated_latch, include.exu_bp, dec.dec_gpr_ctl, mem.quasar, include.dec_aln, lib.param, ifu.ifu, include.aln_ib, include.dctl_dma, include.div_pkt_t, dec.dec_tlu_ctl_IO, include.gpr_exu, include.ahb_out_dma, include.aln_dec, include.lsu_exu, dbg.state_t, dec.dec_ib_ctl_IO, include.lsu_tlu, mem.quasar.mem, exu.exu_div_ctl, include.dccm_ext_in_pkt_t, include.ccm_ext_in_pkt_t, include.inst_pkt_t, lsu.lsu, dec.dec_tlu_ctl, dec.dec_decode_csr_read_IO, lib.ahb_to_axi4, lib.lib.rvecc_encode, lib.axi4_to_ahb, lsu.buffer, lib.lib.rvdffs_fpga, include.tlu_dma, include.lsu_pic, include.dma_lsc_ctl, include.rets_pkt_t, lib.lib.rvecc_encode_64, include.mul_pkt_t, dec.csr_tlu, lsu.lsu_lsc_ctl, include.reg_pkt_t, include.trap_pkt_t, pic_ctrl, include.dma_mem_ctl, include.write_data, include.ic_data_ext_in_pkt_t, dec.CSRs, exu.exu_alu_ctl, lib.lib.rvsyncss, include.tlu_exu, dec.dec_IO, lsu.dccm_ctl, include.ib_exu, include.iccm_mem, lsu.bus_intf, include.lsu_dec, mem.blackbox_mem, include.predict_pkt_t, include.dec_ifc, include.write_addr, include.ifu_dma, include.tlu_busbuff, ifu.mem_ctl_io, include.lsu_error_pkt_t, lsu.lsu_bus_buffer, include.ahb_out, include.trigger_pkt_t, include.write_resp, lib.lib.rvdff_fpga, dec.CSR_IO, include.alu_pkt_t, include.trace_pkt_t, include.br_tlu_pkt_t, lib.lib.rvclkhdr, dec.dec_gpr_ctl_IO, dec.dec_timer_ctl, include.dest_pkt_t, include.dec_exu, lib.lib.rvdffe, include.read_data, include.ahb_in, ifu.ifu_aln_ctl, dbg.dbg, include.dma_dccm_ctl, include.ic_mem, lsu.lsu_bus_intf, dec.dec_ib_ctl, include.br_pkt_t, dec.CSR_VAL, exu.exu_mul_ctl, include.ahb_channel, lsu.lsu_dccm_ctl, include.cache_debug_pkt_t, ifu.ifu_compress_ctl, include.dec_pic, include.exu_ifu, dbg.sb_state_t, include.ic_tag_ext_in_pkt_t, ifu.ifu_bp_ctl, mem.Mem_bundle, lib.lib.rvoclkhdr, include.dctl_busbuff, include.read_addr, include.axi_channels, dec.dec_dec_ctl, mem.mem_lsu, dec.dec_decode_csr_read, include.dec_mem_ctrl, ifu.ifu_mem_ctl, lsu.lsc_ctl, ifu.ifu_ifc_ctl, include.lsu_pkt_t, include.dec_div, include.dec_dma, include.decode_exu, include.dec_pkt_t, dec.dec_timer_ctl_IO, include.dec_dbg, include.load_cam_pkt_t, include.dma_ifc, dbg.dbg_dma, lsu.lsu_main, include.ifu_dec, lib.lib, include.dec_tlu_csr_pkt, dma_ctrl, include.dec_bp, include.dbg_dctl)
+[debug] 
+[debug] Sources indirectly invalidated by:
+[debug] 	product: Set(/home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/ifu/ifu.scala, /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/lib/axi4_to_ahb.scala, /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/lsu/lsu_dccm_ctl.scala, /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/ifu/ifu_compress_ctl.scala, /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/dec/dec_ib_ctl.scala, /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/exu/exu_mul_ctl.scala, /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/pic_ctrl.scala, /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/ifu/ifu_ifc_ctl.scala, /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/mem.scala, /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/ifu/ifu_bp_ctl.scala, /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/dbg/dbg.scala, /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/lib/param.scala, /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/ifu/ifu_aln_ctl.scala, /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/exu/exu.scala, /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/dec/dec_dec_ctl.scala, /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/dec/dec_decode_ctl.scala, /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/dec/dec.scala, /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/dec/dec_tlu_ctl.scala, /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/include/bundle.scala, /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/lsu/lsu_lsc_ctl.scala, /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/lsu/lsu_ecc.scala, /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/dec/dec_trigger.scala, /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/lsu/lsu_clkdomain.scala, /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/dec/dec_gpr_ctl.scala, /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/dma_ctrl.scala, /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/lib/lib.scala, /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/lib/ahb_to_axi4.scala, /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/lsu/lsu_addrcheck.scala, /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/exu/exu_div_ctl.scala, /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/lsu/lsu_bus_buffer.scala, /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/lsu/lsu.scala, /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/dmi/dmi_wrapper.scala, /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/lsu/lsu_bus_intf.scala, /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/exu/exu_alu_ctl.scala, /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/lsu/lsu_stbuf.scala, /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/ifu/ifu_mem_ctl.scala, /home/laraibkhan/Desktop/SweRV-Chislified/src/main/scala/lsu/lsu_trigger.scala)
+[debug] 	binary dep: Set()
+[debug] 	external source: Set()
+[debug] All sources are invalidated.
+[debug] Initial set of included nodes: include.class_pkt_t, include.dbg_ib, dec.dec, include.dec_alu, exu.exu, dec.dec_decode_ctl, include.lsu_dma, lib.axi4_to_ahb_IO, lib.lib.gated_latch, include.exu_bp, dec.dec_gpr_ctl, mem.quasar, include.dec_aln, lib.param, ifu.ifu, include.aln_ib, include.dctl_dma, include.div_pkt_t, dec.dec_tlu_ctl_IO, include.gpr_exu, include.ahb_out_dma, include.aln_dec, include.lsu_exu, dbg.state_t, dec.dec_ib_ctl_IO, include.lsu_tlu, mem.quasar.mem, exu.exu_div_ctl, include.dccm_ext_in_pkt_t, include.ccm_ext_in_pkt_t, include.inst_pkt_t, lsu.lsu, dec.dec_tlu_ctl, dec.dec_decode_csr_read_IO, lib.ahb_to_axi4, lib.lib.rvecc_encode, lib.axi4_to_ahb, lsu.buffer, lib.lib.rvdffs_fpga, include.tlu_dma, include.lsu_pic, include.dma_lsc_ctl, include.rets_pkt_t, lib.lib.rvecc_encode_64, include.mul_pkt_t, dec.csr_tlu, lsu.lsu_lsc_ctl, include.reg_pkt_t, include.trap_pkt_t, pic_ctrl, include.dma_mem_ctl, include.write_data, include.ic_data_ext_in_pkt_t, dec.CSRs, exu.exu_alu_ctl, lib.lib.rvsyncss, include.tlu_exu, dec.dec_IO, lsu.dccm_ctl, include.ib_exu, include.iccm_mem, lsu.bus_intf, include.lsu_dec, mem.blackbox_mem, include.predict_pkt_t, include.dec_ifc, include.write_addr, include.ifu_dma, include.tlu_busbuff, ifu.mem_ctl_io, include.lsu_error_pkt_t, lsu.lsu_bus_buffer, include.ahb_out, include.trigger_pkt_t, include.write_resp, lib.lib.rvdff_fpga, dec.CSR_IO, include.alu_pkt_t, include.trace_pkt_t, include.br_tlu_pkt_t, lib.lib.rvclkhdr, dec.dec_gpr_ctl_IO, dec.dec_timer_ctl, include.dest_pkt_t, include.dec_exu, lib.lib.rvdffe, include.read_data, include.ahb_in, ifu.ifu_aln_ctl, dbg.dbg, include.dma_dccm_ctl, include.ic_mem, lsu.lsu_bus_intf, dec.dec_ib_ctl, include.br_pkt_t, dec.CSR_VAL, exu.exu_mul_ctl, include.ahb_channel, lsu.lsu_dccm_ctl, include.cache_debug_pkt_t, ifu.ifu_compress_ctl, include.dec_pic, include.exu_ifu, dbg.sb_state_t, include.ic_tag_ext_in_pkt_t, ifu.ifu_bp_ctl, mem.Mem_bundle, lib.lib.rvoclkhdr, include.dctl_busbuff, include.read_addr, include.axi_channels, dec.dec_dec_ctl, mem.mem_lsu, dec.dec_decode_csr_read, include.dec_mem_ctrl, ifu.ifu_mem_ctl, lsu.lsc_ctl, ifu.ifu_ifc_ctl, include.lsu_pkt_t, include.dec_div, include.dec_dma, include.decode_exu, include.dec_pkt_t, dec.dec_timer_ctl_IO, include.dec_dbg, include.load_cam_pkt_t, include.dma_ifc, dbg.dbg_dma, lsu.lsu_main, include.ifu_dec, lib.lib, include.dec_tlu_csr_pkt, dma_ctrl, include.dec_bp, include.dbg_dctl
+[debug] Including dec.dec_ib_ctl_IO by lib.param
+[debug] Including lsu.lsu by lib.param
+[debug] Including dec.dec_ib_ctl by lib.param
+[debug] Including lib.lib by lib.param
+[debug] Including lsu.lsu_clkdomain by lib.lib
+[debug] Including lsu.lsu_trigger by lib.lib
+[debug] Including lsu.lsu_addrcheck by lib.lib
+[debug] Including ifu.ifu by lib.lib
+[debug] Including include.aln_ib by lib.lib
+[debug] Including dec.dec_tlu_ctl_IO by lib.lib
+[debug] Including exu.exu_div_ctl by lib.lib
+[debug] Including dec.dec_tlu_ctl by lib.lib
+[debug] Including lib.ahb_to_axi4 by lib.lib
+[debug] Including lib.axi4_to_ahb by lib.lib
+[debug] Including dec.csr_tlu by lib.lib
+[debug] Including lsu.lsu_lsc_ctl by lib.lib
+[debug] Including pic_ctrl by lib.lib
+[debug] Including include.write_data by lib.lib
+[debug] Including exu.exu_alu_ctl by lib.lib
+[debug] Including include.tlu_exu by lib.lib
+[debug] Including dec.dec_IO by lib.lib
+[debug] Including include.iccm_mem by lib.lib
+[debug] Including lsu.lsu_ecc by lib.lib
+[debug] Including mem.blackbox_mem by lib.lib
+[debug] Including include.write_addr by lib.lib
+[debug] Including ifu.mem_ctl_io by lib.lib
+[debug] Including lsu.lsu_bus_buffer by lib.lib
+[debug] Including include.write_resp by lib.lib
+[debug] Including dec.CSR_IO by lib.lib
+[debug] Including dec.dec_timer_ctl by lib.lib
+[debug] Including include.dec_exu by lib.lib
+[debug] Including include.read_data by lib.lib
+[debug] Including ifu.ifu_aln_ctl by lib.lib
+[debug] Including dbg.dbg by lib.lib
+[debug] Including include.ic_mem by lib.lib
+[debug] Including lsu.lsu_bus_intf by lib.lib
+[debug] Including exu.exu_mul_ctl by lib.lib
+[debug] Including dec.dec_trigger by lib.lib
+[debug] Including lsu.lsu_dccm_ctl by lib.lib
+[debug] Including ifu.ifu_compress_ctl by lib.lib
+[debug] Including ifu.ifu_bp_ctl by lib.lib
+[debug] Including mem.Mem_bundle by lib.lib
+[debug] Including include.dctl_busbuff by lib.lib
+[debug] Including include.read_addr by lib.lib
+[debug] Including include.axi_channels by lib.lib
+[debug] Including dec.dec_dec_ctl by lib.lib
+[debug] Including lsu.lsu_stbuf by lib.lib
+[debug] Including mem.mem_lsu by lib.lib
+[debug] Including include.dec_mem_ctrl by lib.lib
+[debug] Including ifu.ifu_mem_ctl by lib.lib
+[debug] Including ifu.ifu_ifc_ctl by lib.lib
+[debug] Including include.decode_exu by lib.lib
+[debug] Including dma_ctrl by lib.lib
+[debug] Recompiling all sources: number of invalidated sources > 50.0% of all sources
+[info] Compiling 39 Scala sources to /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes ...
+[debug] Getting org.scala-sbt:compiler-bridge_2.12:1.3.5:compile for Scala 2.12.10
+[debug] Getting org.scala-sbt:compiler-bridge_2.12:1.3.5:compile for Scala 2.12.10
+[debug] [zinc] Running cached compiler 8ca7f6e for Scala compiler version 2.12.10
+[debug] [zinc] The Scala compiler is invoked with:
+[debug] 	-Xsource:2.11
+[debug] 	-Xplugin:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalamacros/paradise_2.12.10/2.1.0/paradise_2.12.10-2.1.0.jar
+[debug] 	-bootclasspath
+[debug] 	/home/laraibkhan/.sbt/boot/scala-2.12.10/lib/scala-library.jar
+[debug] 	-classpath
+[debug] 	/home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar:/home/laraibkhan/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar
+[debug] Scala compilation took 45.114404424 s
+[debug] Done compiling.
diff --git a/target/streams/compile/copyResources/_global/streams/copy-resources b/target/streams/compile/copyResources/_global/streams/copy-resources
index 5a5c694f..0416e127 100644
--- a/target/streams/compile/copyResources/_global/streams/copy-resources
+++ b/target/streams/compile/copyResources/_global/streams/copy-resources
@@ -1 +1 @@
-[[{"file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/dmi_jtag_to_core_sync.sv":["file:///home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/vsrc/dmi_jtag_to_core_sync.sv"],"file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/mem_lib.sv":["file:///home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/vsrc/mem_lib.sv"],"file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/rvjtag_tap.sv":["file:///home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/vsrc/rvjtag_tap.sv"],"file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/ifu_ic_mem.sv":["file:///home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/vsrc/ifu_ic_mem.sv"],"file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/beh_lib.sv":["file:///home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/vsrc/beh_lib.sv"],"file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/gated_latch.sv":["file:///home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/vsrc/gated_latch.sv"],"file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/mem_mod.sv":["file:///home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/vsrc/mem_mod.sv"],"file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/ifu_iccm_mem.sv":["file:///home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/vsrc/ifu_iccm_mem.sv"],"file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/mem.sv":["file:///home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/vsrc/mem.sv"],"file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/dmi_wrapper.sv":["file:///home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/vsrc/dmi_wrapper.sv"],"file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/lsu_dccm_mem.sv":["file:///home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/vsrc/lsu_dccm_mem.sv"]},{"file:///home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/vsrc/rvjtag_tap.sv":["file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/rvjtag_tap.sv"],"file:///home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/vsrc/ifu_iccm_mem.sv":["file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/ifu_iccm_mem.sv"],"file:///home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/vsrc/ifu_ic_mem.sv":["file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/ifu_ic_mem.sv"],"file:///home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/vsrc/gated_latch.sv":["file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/gated_latch.sv"],"file:///home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/vsrc/mem.sv":["file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/mem.sv"],"file:///home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/vsrc/dmi_jtag_to_core_sync.sv":["file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/dmi_jtag_to_core_sync.sv"],"file:///home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/vsrc/lsu_dccm_mem.sv":["file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/lsu_dccm_mem.sv"],"file:///home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/vsrc/dmi_wrapper.sv":["file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/dmi_wrapper.sv"],"file:///home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/vsrc/beh_lib.sv":["file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/beh_lib.sv"],"file:///home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/vsrc/mem_mod.sv":["file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/mem_mod.sv"],"file:///home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/vsrc/mem_lib.sv":["file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/mem_lib.sv"]}],{"file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/dmi_jtag_to_core_sync.sv":{"file":"file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/dmi_jtag_to_core_sync.sv","lastModified":1608035101000},"file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/mem_lib.sv":{"file":"file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/mem_lib.sv","lastModified":1608035101000},"file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/rvjtag_tap.sv":{"file":"file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/rvjtag_tap.sv","lastModified":1608035101000},"file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/ifu_ic_mem.sv":{"file":"file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/ifu_ic_mem.sv","lastModified":1608035101000},"file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/beh_lib.sv":{"file":"file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/beh_lib.sv","lastModified":1608035101000},"file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/gated_latch.sv":{"file":"file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/gated_latch.sv","lastModified":1608209394840},"file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/mem_mod.sv":{"file":"file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/mem_mod.sv","lastModified":1608039915000},"file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/ifu_iccm_mem.sv":{"file":"file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/ifu_iccm_mem.sv","lastModified":1608035101000},"file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/mem.sv":{"file":"file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/mem.sv","lastModified":1608035101000},"file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/dmi_wrapper.sv":{"file":"file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/dmi_wrapper.sv","lastModified":1608035101000},"file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/lsu_dccm_mem.sv":{"file":"file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/lsu_dccm_mem.sv","lastModified":1608035101000}}]
\ No newline at end of file
+[[{"file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/dmi_jtag_to_core_sync.sv":["file:///home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/vsrc/dmi_jtag_to_core_sync.sv"],"file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/mem_lib.sv":["file:///home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/vsrc/mem_lib.sv"],"file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/rvjtag_tap.sv":["file:///home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/vsrc/rvjtag_tap.sv"],"file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/ifu_ic_mem.sv":["file:///home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/vsrc/ifu_ic_mem.sv"],"file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/beh_lib.sv":["file:///home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/vsrc/beh_lib.sv"],"file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/gated_latch.sv":["file:///home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/vsrc/gated_latch.sv"],"file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/mem_mod.sv":["file:///home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/vsrc/mem_mod.sv"],"file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/ifu_iccm_mem.sv":["file:///home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/vsrc/ifu_iccm_mem.sv"],"file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/mem.sv":["file:///home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/vsrc/mem.sv"],"file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/dmi_wrapper.sv":["file:///home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/vsrc/dmi_wrapper.sv"],"file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/lsu_dccm_mem.sv":["file:///home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/vsrc/lsu_dccm_mem.sv"]},{"file:///home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/vsrc/rvjtag_tap.sv":["file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/rvjtag_tap.sv"],"file:///home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/vsrc/ifu_iccm_mem.sv":["file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/ifu_iccm_mem.sv"],"file:///home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/vsrc/ifu_ic_mem.sv":["file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/ifu_ic_mem.sv"],"file:///home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/vsrc/gated_latch.sv":["file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/gated_latch.sv"],"file:///home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/vsrc/mem.sv":["file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/mem.sv"],"file:///home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/vsrc/dmi_jtag_to_core_sync.sv":["file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/dmi_jtag_to_core_sync.sv"],"file:///home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/vsrc/lsu_dccm_mem.sv":["file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/lsu_dccm_mem.sv"],"file:///home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/vsrc/dmi_wrapper.sv":["file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/dmi_wrapper.sv"],"file:///home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/vsrc/beh_lib.sv":["file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/beh_lib.sv"],"file:///home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/vsrc/mem_mod.sv":["file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/mem_mod.sv"],"file:///home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/vsrc/mem_lib.sv":["file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/mem_lib.sv"]}],{"file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/dmi_jtag_to_core_sync.sv":{"file":"file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/dmi_jtag_to_core_sync.sv","lastModified":1610080107679},"file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/mem_lib.sv":{"file":"file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/mem_lib.sv","lastModified":1613536545753},"file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/rvjtag_tap.sv":{"file":"file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/rvjtag_tap.sv","lastModified":1610080107703},"file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/ifu_ic_mem.sv":{"file":"file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/ifu_ic_mem.sv","lastModified":1614164767004},"file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/beh_lib.sv":{"file":"file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/beh_lib.sv","lastModified":1610080107679},"file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/gated_latch.sv":{"file":"file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/gated_latch.sv","lastModified":1610080107679},"file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/mem_mod.sv":{"file":"file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/mem_mod.sv","lastModified":1613536567125},"file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/ifu_iccm_mem.sv":{"file":"file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/ifu_iccm_mem.sv","lastModified":1614164782672},"file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/mem.sv":{"file":"file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/mem.sv","lastModified":1614165232746},"file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/dmi_wrapper.sv":{"file":"file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/dmi_wrapper.sv","lastModified":1610080107679},"file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/lsu_dccm_mem.sv":{"file":"file:///home/laraibkhan/Desktop/SweRV-Chislified/src/main/resources/vsrc/lsu_dccm_mem.sv","lastModified":1614164749536}}]
\ No newline at end of file
diff --git a/target/streams/compile/packageBin/_global/streams/inputs b/target/streams/compile/packageBin/_global/streams/inputs
index 0a30630b..f1892385 100644
--- a/target/streams/compile/packageBin/_global/streams/inputs
+++ b/target/streams/compile/packageBin/_global/streams/inputs
@@ -1 +1 @@
--1342856941
\ No newline at end of file
+-1402224808
\ No newline at end of file
diff --git a/target/streams/compile/packageBin/_global/streams/out b/target/streams/compile/packageBin/_global/streams/out
index 69fff9f9..7e1a1e97 100644
--- a/target/streams/compile/packageBin/_global/streams/out
+++ b/target/streams/compile/packageBin/_global/streams/out
@@ -1 +1,591 @@
-[debug] Jar uptodate: /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/quasar_2.12-3.3.0.jar
+[debug] Packaging /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/quasar_2.12-3.3.0.jar ...
+[debug] Input file mappings:
+[debug] 	lsu
+[debug] 	  /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu
+[debug] 	lsu/lsu_addrcheck.class
+[debug] 	  /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/lsu_addrcheck.class
+[debug] 	lsu/lsu_dccm_ctl$$anon$1.class
+[debug] 	  /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/lsu_dccm_ctl$$anon$1.class
+[debug] 	lsu/clkdomain$.class
+[debug] 	  /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/clkdomain$.class
+[debug] 	lsu/bus_intf.class
+[debug] 	  /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/bus_intf.class
+[debug] 	lsu/lsu.class
+[debug] 	  /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/lsu.class
+[debug] 	lsu/lsu_bus_buffer$$anon$1.class
+[debug] 	  /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/lsu_bus_buffer$$anon$1.class
+[debug] 	lsu/dccm_ctl.class
+[debug] 	  /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/dccm_ctl.class
+[debug] 	lsu/lsu_trigger.class
+[debug] 	  /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/lsu_trigger.class
+[debug] 	lsu/dccm_ctl$.class
+[debug] 	  /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/dccm_ctl$.class
+[debug] 	lsu/buffer.class
+[debug] 	  /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/buffer.class
+[debug] 	lsu/bus_intf$.class
+[debug] 	  /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/bus_intf$.class
+[debug] 	lsu/stbuf.class
+[debug] 	  /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/stbuf.class
+[debug] 	lsu/lsu_ecc.class
+[debug] 	  /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/lsu_ecc.class
+[debug] 	lsu/buffer$delayedInit$body.class
+[debug] 	  /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/buffer$delayedInit$body.class
+[debug] 	lsu/bus_intf$delayedInit$body.class
+[debug] 	  /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/bus_intf$delayedInit$body.class
+[debug] 	lsu/stbuf$delayedInit$body.class
+[debug] 	  /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/stbuf$delayedInit$body.class
+[debug] 	lsu/lsu_stbuf$$anon$1.class
+[debug] 	  /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/lsu_stbuf$$anon$1.class
+[debug] 	lsu/lsu_main$delayedInit$body.class
+[debug] 	  /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/lsu_main$delayedInit$body.class
+[debug] 	lsu/lsu_bus_intf$$anon$1.class
+[debug] 	  /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/lsu_bus_intf$$anon$1.class
+[debug] 	lsu/stbuf$.class
+[debug] 	  /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/stbuf$.class
+[debug] 	lsu/lsu_main.class
+[debug] 	  /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/lsu_main.class
+[debug] 	lsu/lsu_ecc$$anon$1.class
+[debug] 	  /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/lsu_ecc$$anon$1.class
+[debug] 	lsu/dccm_ctl$delayedInit$body.class
+[debug] 	  /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/dccm_ctl$delayedInit$body.class
+[debug] 	lsu/lsu_bus_buffer.class
+[debug] 	  /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/lsu_bus_buffer.class
+[debug] 	lsu/lsc_ctl.class
+[debug] 	  /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/lsc_ctl.class
+[debug] 	lsu/lsc_ctl$.class
+[debug] 	  /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/lsc_ctl$.class
+[debug] 	lsu/clkdomain.class
+[debug] 	  /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/clkdomain.class
+[debug] 	lsu/buffer$.class
+[debug] 	  /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/buffer$.class
+[debug] 	lsu/lsu_main$.class
+[debug] 	  /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/lsu_main$.class
+[debug] 	lsu/lsu_lsc_ctl.class
+[debug] 	  /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/lsu_lsc_ctl.class
+[debug] 	lsu/lsu_dccm_ctl.class
+[debug] 	  /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/lsu/lsu_dccm_ctl.class
+[debug] 	lsu/lsu_addrcheck$$anon$1.class
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+[debug] 	exu/exu_main$.class
+[debug] 	  /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/exu/exu_main$.class
+[debug] 	exu/exu_div_new_1bit_fullshortq.class
+[debug] 	  /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/exu/exu_div_new_1bit_fullshortq.class
+[debug] 	exu/exu_div_new_2bit_fullshortq.class
+[debug] 	  /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/exu/exu_div_new_2bit_fullshortq.class
+[debug] 	exu/exu_div_new_4bit_fullshortq$$anon$6.class
+[debug] 	  /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/exu/exu_div_new_4bit_fullshortq$$anon$6.class
+[debug] 	exu/exu_div_ctl.class
+[debug] 	  /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/exu/exu_div_ctl.class
+[debug] 	exu/exu_div_new_3bit_fullshortq.class
+[debug] 	  /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/exu/exu_div_new_3bit_fullshortq.class
+[debug] 	exu/div_main.class
+[debug] 	  /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/exu/div_main.class
+[debug] 	exu/exu_div_cls$$anon$7.class
+[debug] 	  /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/exu/exu_div_cls$$anon$7.class
+[debug] 	exu/exu$$anon$1.class
+[debug] 	  /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/exu/exu$$anon$1.class
+[debug] 	exu/exu_div_existing_1bit_cheapshortq$$anon$2.class
+[debug] 	  /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/exu/exu_div_existing_1bit_cheapshortq$$anon$2.class
+[debug] 	exu/exu_alu_ctl.class
+[debug] 	  /home/laraibkhan/Desktop/SweRV-Chislified/target/scala-2.12/classes/exu/exu_alu_ctl.class
+[debug] Done packaging.
diff --git a/target/streams/compile/selectMainClass/_global/streams/out b/target/streams/compile/selectMainClass/_global/streams/out
new file mode 100644
index 00000000..e69de29b