From b4a84e2c474c3b089494602c9f4a85cf3dc444a6 Mon Sep 17 00:00:00 2001 From: waleed-lm Date: Fri, 6 Nov 2020 18:58:23 +0500 Subject: [PATCH] Bus-buffer testing start --- el2_lsu_bus_buffer.anno.json | 175 + el2_lsu_bus_buffer.fir | 6364 +++++++++++++++++ el2_lsu_bus_buffer.v | 4235 +++++++++++ src/main/scala/include/el2_bundle.scala | 26 +- src/main/scala/lsu/el2_lsu_bus_buffer.scala | 880 +-- src/main/scala/lsu/w.scala | 163 - .../chisel-module-template.kotlin_module | Bin 0 -> 16 bytes .../classes/include/el2_lsu_pkt_t.class | Bin 3425 -> 3033 bytes .../scala-2.12/classes/lsu/BusBufmain$.class | Bin 0 -> 3935 bytes .../lsu/BusBufmain$delayedInit$body.class | Bin 0 -> 757 bytes .../scala-2.12/classes/lsu/BusBufmain.class | Bin 0 -> 799 bytes .../classes/lsu/address_checker$.class | Bin 3717 -> 0 bytes .../address_checker$delayedInit$body.class | Bin 770 -> 0 bytes .../classes/lsu/address_checker.class | Bin 808 -> 0 bytes .../lsu/el2_lsu_addrcheck$$anon$1.class | Bin 4027 -> 0 bytes .../classes/lsu/el2_lsu_addrcheck.class | Bin 107895 -> 0 bytes .../lsu/el2_lsu_bus_buffer$$anon$1.class | Bin 0 -> 14886 bytes .../classes/lsu/el2_lsu_bus_buffer.class | Bin 0 -> 491969 bytes 18 files changed, 11228 insertions(+), 615 deletions(-) create mode 100644 el2_lsu_bus_buffer.anno.json create mode 100644 el2_lsu_bus_buffer.fir create mode 100644 el2_lsu_bus_buffer.v delete mode 100644 src/main/scala/lsu/w.scala create mode 100644 target/scala-2.12/classes/META-INF/chisel-module-template.kotlin_module create mode 100644 target/scala-2.12/classes/lsu/BusBufmain$.class create mode 100644 target/scala-2.12/classes/lsu/BusBufmain$delayedInit$body.class create mode 100644 target/scala-2.12/classes/lsu/BusBufmain.class delete mode 100644 target/scala-2.12/classes/lsu/address_checker$.class delete mode 100644 target/scala-2.12/classes/lsu/address_checker$delayedInit$body.class delete mode 100644 target/scala-2.12/classes/lsu/address_checker.class delete mode 100644 target/scala-2.12/classes/lsu/el2_lsu_addrcheck$$anon$1.class delete mode 100644 target/scala-2.12/classes/lsu/el2_lsu_addrcheck.class create mode 100644 target/scala-2.12/classes/lsu/el2_lsu_bus_buffer$$anon$1.class create mode 100644 target/scala-2.12/classes/lsu/el2_lsu_bus_buffer.class diff --git a/el2_lsu_bus_buffer.anno.json b/el2_lsu_bus_buffer.anno.json new file mode 100644 index 00000000..faf1728b --- /dev/null +++ b/el2_lsu_bus_buffer.anno.json @@ -0,0 +1,175 @@ +[ + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ld_fwddata_buf_lo", + "sources":[ + "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_m", + "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ldst_byteen_ext_m", + "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_addr_m" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ld_fwddata_buf_hi", + "sources":[ + "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_m", + "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ldst_byteen_ext_m", + "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_end_addr_m" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_bus_buffer_full_any", + "sources":[ + "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ldst_dual_d", + "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_dec_lsu_valid_raw_d" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_nonblock_load_valid_m", + "sources":[ + "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ld_full_hit_m", + "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_pkt_m_load", + "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_flush_m_up", + "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_m", + "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_pkt_m_valid" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_pmu_bus_trxn", + "sources":[ + "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_arvalid", + "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_arready", + "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_awvalid", + "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_awready", + "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_wvalid", + "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_wready" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ld_byte_hit_buf_hi", + "sources":[ + "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_m", + "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ldst_byteen_ext_m", + "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_end_addr_m" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_imprecise_error_store_any", + "sources":[ + "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_bus_clk_en_q" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_nonblock_load_data_valid", + "sources":[ + "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_nonblock_load_data_error" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_imprecise_error_addr_any", + "sources":[ + "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_imprecise_error_store_any", + "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_nonblock_load_data_tag", + "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_bus_clk_en_q" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_nonblock_load_inv_r", + "sources":[ + "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_commit_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_imprecise_error_load_any", + "sources":[ + "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_nonblock_load_data_error", + "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_imprecise_error_store_any", + "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_bus_clk_en_q" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ld_byte_hit_buf_lo", + "sources":[ + "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_m", + "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ldst_byteen_ext_m", + "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_addr_m" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_pmu_bus_misaligned", + "sources":[ + "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_commit_r", + "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_r", + "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ldst_dual_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_pmu_bus_busy", + "sources":[ + "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_arvalid", + "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_awvalid", + "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_wvalid", + "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_arready", + "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_awready", + "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_wready" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_pmu_bus_error", + "sources":[ + "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_imprecise_error_load_any", + "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_imprecise_error_store_any", + "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_nonblock_load_data_error", + "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_bus_clk_en_q" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_nonblock_load_data", + "sources":[ + "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_nonblock_load_data_tag" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_nonblock_load_tag_m", + "sources":[ + "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ldst_dual_r", + "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_m" + ] + }, + { + "class":"firrtl.EmitCircuitAnnotation", + "emitter":"firrtl.VerilogEmitter" + }, + { + "class":"firrtl.transforms.BlackBoxResourceAnno", + "target":"el2_lsu_bus_buffer.TEC_RV_ICG", + "resourceId":"/vsrc/TEC_RV_ICG.v" + }, + { + "class":"firrtl.options.TargetDirAnnotation", + "directory":"." + }, + { + "class":"firrtl.options.OutputAnnotationFileAnnotation", + "file":"el2_lsu_bus_buffer" + }, + { + "class":"firrtl.transforms.BlackBoxTargetDirAnno", + "targetDir":"." + } +] \ No newline at end of file diff --git a/el2_lsu_bus_buffer.fir b/el2_lsu_bus_buffer.fir new file mode 100644 index 00000000..c30f2efb --- /dev/null +++ b/el2_lsu_bus_buffer.fir @@ -0,0 +1,6364 @@ +;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10 +circuit el2_lsu_bus_buffer : + extmodule TEC_RV_ICG : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG @[el2_lib.scala 452:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 453:14] + clkhdr.CK <= io.clk @[el2_lib.scala 454:18] + clkhdr.EN <= io.en @[el2_lib.scala 455:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 456:18] + + extmodule TEC_RV_ICG_1 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_1 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_1 @[el2_lib.scala 452:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 453:14] + clkhdr.CK <= io.clk @[el2_lib.scala 454:18] + clkhdr.EN <= io.en @[el2_lib.scala 455:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 456:18] + + extmodule TEC_RV_ICG_2 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_2 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_2 @[el2_lib.scala 452:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 453:14] + clkhdr.CK <= io.clk @[el2_lib.scala 454:18] + clkhdr.EN <= io.en @[el2_lib.scala 455:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 456:18] + + extmodule TEC_RV_ICG_3 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_3 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_3 @[el2_lib.scala 452:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 453:14] + clkhdr.CK <= io.clk @[el2_lib.scala 454:18] + clkhdr.EN <= io.en @[el2_lib.scala 455:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 456:18] + + extmodule TEC_RV_ICG_4 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_4 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_4 @[el2_lib.scala 452:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 453:14] + clkhdr.CK <= io.clk @[el2_lib.scala 454:18] + clkhdr.EN <= io.en @[el2_lib.scala 455:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 456:18] + + extmodule TEC_RV_ICG_5 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_5 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_5 @[el2_lib.scala 452:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 453:14] + clkhdr.CK <= io.clk @[el2_lib.scala 454:18] + clkhdr.EN <= io.en @[el2_lib.scala 455:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 456:18] + + extmodule TEC_RV_ICG_6 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_6 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_6 @[el2_lib.scala 452:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 453:14] + clkhdr.CK <= io.clk @[el2_lib.scala 454:18] + clkhdr.EN <= io.en @[el2_lib.scala 455:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 456:18] + + extmodule TEC_RV_ICG_7 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_7 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_7 @[el2_lib.scala 452:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 453:14] + clkhdr.CK <= io.clk @[el2_lib.scala 454:18] + clkhdr.EN <= io.en @[el2_lib.scala 455:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 456:18] + + extmodule TEC_RV_ICG_8 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_8 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_8 @[el2_lib.scala 452:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 453:14] + clkhdr.CK <= io.clk @[el2_lib.scala 454:18] + clkhdr.EN <= io.en @[el2_lib.scala 455:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 456:18] + + extmodule TEC_RV_ICG_9 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_9 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_9 @[el2_lib.scala 452:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 453:14] + clkhdr.CK <= io.clk @[el2_lib.scala 454:18] + clkhdr.EN <= io.en @[el2_lib.scala 455:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 456:18] + + extmodule TEC_RV_ICG_10 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_10 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_10 @[el2_lib.scala 452:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 453:14] + clkhdr.CK <= io.clk @[el2_lib.scala 454:18] + clkhdr.EN <= io.en @[el2_lib.scala 455:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 456:18] + + extmodule TEC_RV_ICG_11 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = TEC_RV_ICG + + + module rvclkhdr_11 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of TEC_RV_ICG_11 @[el2_lib.scala 452:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 453:14] + clkhdr.CK <= io.clk @[el2_lib.scala 454:18] + clkhdr.EN <= io.en @[el2_lib.scala 455:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 456:18] + + module el2_lsu_bus_buffer : + input clock : Clock + input reset : AsyncReset + output io : {flip scan_mode : UInt<1>, flip dec_tlu_external_ldfwd_disable : UInt<1>, flip dec_tlu_wb_coalescing_disable : UInt<1>, flip dec_tlu_sideeffect_posted_disable : UInt<1>, flip dec_tlu_force_halt : UInt<1>, flip lsu_c2_r_clk : Clock, flip lsu_bus_ibuf_c1_clk : Clock, flip lsu_bus_obuf_c1_clk : Clock, flip lsu_bus_buf_c1_clk : Clock, flip lsu_free_c2_clk : Clock, flip lsu_busm_clk : Clock, flip dec_lsu_valid_raw_d : UInt<1>, flip lsu_pkt_m : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip lsu_pkt_r : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip lsu_addr_m : UInt<32>, flip end_addr_m : UInt<32>, flip lsu_addr_r : UInt<32>, flip end_addr_r : UInt<32>, flip store_data_r : UInt<32>, flip no_word_merge_r : UInt<1>, flip no_dword_merge_r : UInt<1>, flip lsu_busreq_m : UInt<1>, flip ld_full_hit_m : UInt<1>, flip flush_m_up : UInt<1>, flip flush_r : UInt<1>, flip lsu_commit_r : UInt<1>, flip is_sideeffects_r : UInt<1>, flip ldst_dual_d : UInt<1>, flip ldst_dual_m : UInt<1>, flip ldst_dual_r : UInt<1>, flip ldst_byteen_ext_m : UInt<8>, flip lsu_axi_awready : UInt<1>, flip lsu_axi_wready : UInt<1>, flip lsu_axi_bvalid : UInt<1>, flip lsu_axi_bresp : UInt<2>, flip lsu_axi_bid : UInt<3>, flip lsu_axi_arready : UInt<1>, flip lsu_axi_rvalid : UInt<1>, flip lsu_axi_rid : UInt<3>, flip lsu_axi_rdata : UInt<64>, flip lsu_axi_rresp : UInt<2>, flip lsu_bus_clk_en : UInt<1>, flip lsu_bus_clk_en_q : UInt<1>, lsu_busreq_r : UInt<1>, lsu_bus_buffer_pend_any : UInt<1>, lsu_bus_buffer_full_any : UInt<1>, lsu_bus_buffer_empty_any : UInt<1>, lsu_bus_idle_any : UInt<1>, ld_byte_hit_buf_lo : UInt<4>, ld_byte_hit_buf_hi : UInt<4>, ld_fwddata_buf_lo : UInt<32>, ld_fwddata_buf_hi : UInt<32>, lsu_imprecise_error_load_any : UInt<1>, lsu_imprecise_error_store_any : UInt<1>, lsu_imprecise_error_addr_any : UInt<32>, lsu_nonblock_load_valid_m : UInt<1>, lsu_nonblock_load_tag_m : UInt<2>, lsu_nonblock_load_inv_r : UInt<1>, lsu_nonblock_load_inv_tag_r : UInt<2>, lsu_nonblock_load_data_valid : UInt<1>, lsu_nonblock_load_data_error : UInt<1>, lsu_nonblock_load_data_tag : UInt<2>, lsu_nonblock_load_data : UInt<32>, lsu_pmu_bus_trxn : UInt<1>, lsu_pmu_bus_misaligned : UInt<1>, lsu_pmu_bus_error : UInt<1>, lsu_pmu_bus_busy : UInt<1>, lsu_axi_awvalid : UInt<1>, lsu_axi_awid : UInt<3>, lsu_axi_awaddr : UInt<32>, lsu_axi_awregion : UInt<4>, lsu_axi_awlen : UInt<8>, lsu_axi_awsize : UInt<3>, lsu_axi_awburst : UInt<2>, lsu_axi_awlock : UInt<1>, lsu_axi_awcache : UInt<4>, lsu_axi_awprot : UInt<3>, lsu_axi_awqos : UInt<4>, lsu_axi_wvalid : UInt<1>, lsu_axi_wdata : UInt<64>, lsu_axi_wstrb : UInt<8>, lsu_axi_wlast : UInt<1>, lsu_axi_bready : UInt<1>, lsu_axi_arvalid : UInt<1>, lsu_axi_arid : UInt<3>, lsu_axi_araddr : UInt<32>, lsu_axi_arregion : UInt<4>, lsu_axi_arlen : UInt<8>, lsu_axi_arsize : UInt<3>, lsu_axi_arburst : UInt<2>, lsu_axi_arlock : UInt<1>, lsu_axi_arcache : UInt<4>, lsu_axi_arprot : UInt<3>, lsu_axi_arqos : UInt<4>, lsu_axi_rready : UInt<1>} + + wire buf_addr : UInt<32>[4] @[el2_lsu_bus_buffer.scala 120:22] + wire buf_state : UInt<3>[4] @[el2_lsu_bus_buffer.scala 121:23] + wire buf_write : UInt<4> + buf_write <= UInt<1>("h00") + node ldst_byteen_hi_m = bits(io.ldst_byteen_ext_m, 7, 4) @[el2_lsu_bus_buffer.scala 125:46] + node ldst_byteen_lo_m = bits(io.ldst_byteen_ext_m, 3, 0) @[el2_lsu_bus_buffer.scala 126:46] + node _T = bits(io.lsu_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 128:66] + node _T_1 = bits(buf_addr[0], 31, 2) @[el2_lsu_bus_buffer.scala 128:89] + node _T_2 = eq(_T, _T_1) @[el2_lsu_bus_buffer.scala 128:74] + node _T_3 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 128:109] + node _T_4 = and(_T_2, _T_3) @[el2_lsu_bus_buffer.scala 128:98] + node _T_5 = neq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 128:129] + node _T_6 = and(_T_4, _T_5) @[el2_lsu_bus_buffer.scala 128:113] + node ld_addr_hitvec_lo_0 = and(_T_6, io.lsu_busreq_m) @[el2_lsu_bus_buffer.scala 128:141] + node _T_7 = bits(io.lsu_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 128:66] + node _T_8 = bits(buf_addr[1], 31, 2) @[el2_lsu_bus_buffer.scala 128:89] + node _T_9 = eq(_T_7, _T_8) @[el2_lsu_bus_buffer.scala 128:74] + node _T_10 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 128:109] + node _T_11 = and(_T_9, _T_10) @[el2_lsu_bus_buffer.scala 128:98] + node _T_12 = neq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 128:129] + node _T_13 = and(_T_11, _T_12) @[el2_lsu_bus_buffer.scala 128:113] + node ld_addr_hitvec_lo_1 = and(_T_13, io.lsu_busreq_m) @[el2_lsu_bus_buffer.scala 128:141] + node _T_14 = bits(io.lsu_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 128:66] + node _T_15 = bits(buf_addr[2], 31, 2) @[el2_lsu_bus_buffer.scala 128:89] + node _T_16 = eq(_T_14, _T_15) @[el2_lsu_bus_buffer.scala 128:74] + node _T_17 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 128:109] + node _T_18 = and(_T_16, _T_17) @[el2_lsu_bus_buffer.scala 128:98] + node _T_19 = neq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 128:129] + node _T_20 = and(_T_18, _T_19) @[el2_lsu_bus_buffer.scala 128:113] + node ld_addr_hitvec_lo_2 = and(_T_20, io.lsu_busreq_m) @[el2_lsu_bus_buffer.scala 128:141] + node _T_21 = bits(io.lsu_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 128:66] + node _T_22 = bits(buf_addr[3], 31, 2) @[el2_lsu_bus_buffer.scala 128:89] + node _T_23 = eq(_T_21, _T_22) @[el2_lsu_bus_buffer.scala 128:74] + node _T_24 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 128:109] + node _T_25 = and(_T_23, _T_24) @[el2_lsu_bus_buffer.scala 128:98] + node _T_26 = neq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 128:129] + node _T_27 = and(_T_25, _T_26) @[el2_lsu_bus_buffer.scala 128:113] + node ld_addr_hitvec_lo_3 = and(_T_27, io.lsu_busreq_m) @[el2_lsu_bus_buffer.scala 128:141] + node _T_28 = bits(io.end_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 129:66] + node _T_29 = bits(buf_addr[0], 31, 2) @[el2_lsu_bus_buffer.scala 129:89] + node _T_30 = eq(_T_28, _T_29) @[el2_lsu_bus_buffer.scala 129:74] + node _T_31 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 129:109] + node _T_32 = and(_T_30, _T_31) @[el2_lsu_bus_buffer.scala 129:98] + node _T_33 = neq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 129:129] + node _T_34 = and(_T_32, _T_33) @[el2_lsu_bus_buffer.scala 129:113] + node ld_addr_hitvec_hi_0 = and(_T_34, io.lsu_busreq_m) @[el2_lsu_bus_buffer.scala 129:141] + node _T_35 = bits(io.end_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 129:66] + node _T_36 = bits(buf_addr[1], 31, 2) @[el2_lsu_bus_buffer.scala 129:89] + node _T_37 = eq(_T_35, _T_36) @[el2_lsu_bus_buffer.scala 129:74] + node _T_38 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 129:109] + node _T_39 = and(_T_37, _T_38) @[el2_lsu_bus_buffer.scala 129:98] + node _T_40 = neq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 129:129] + node _T_41 = and(_T_39, _T_40) @[el2_lsu_bus_buffer.scala 129:113] + node ld_addr_hitvec_hi_1 = and(_T_41, io.lsu_busreq_m) @[el2_lsu_bus_buffer.scala 129:141] + node _T_42 = bits(io.end_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 129:66] + node _T_43 = bits(buf_addr[2], 31, 2) @[el2_lsu_bus_buffer.scala 129:89] + node _T_44 = eq(_T_42, _T_43) @[el2_lsu_bus_buffer.scala 129:74] + node _T_45 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 129:109] + node _T_46 = and(_T_44, _T_45) @[el2_lsu_bus_buffer.scala 129:98] + node _T_47 = neq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 129:129] + node _T_48 = and(_T_46, _T_47) @[el2_lsu_bus_buffer.scala 129:113] + node ld_addr_hitvec_hi_2 = and(_T_48, io.lsu_busreq_m) @[el2_lsu_bus_buffer.scala 129:141] + node _T_49 = bits(io.end_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 129:66] + node _T_50 = bits(buf_addr[3], 31, 2) @[el2_lsu_bus_buffer.scala 129:89] + node _T_51 = eq(_T_49, _T_50) @[el2_lsu_bus_buffer.scala 129:74] + node _T_52 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 129:109] + node _T_53 = and(_T_51, _T_52) @[el2_lsu_bus_buffer.scala 129:98] + node _T_54 = neq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 129:129] + node _T_55 = and(_T_53, _T_54) @[el2_lsu_bus_buffer.scala 129:113] + node ld_addr_hitvec_hi_3 = and(_T_55, io.lsu_busreq_m) @[el2_lsu_bus_buffer.scala 129:141] + wire ld_byte_hitvecfn_lo : UInt<4>[4] @[el2_lsu_bus_buffer.scala 130:33] + wire ld_byte_ibuf_hit_lo : UInt<4> + ld_byte_ibuf_hit_lo <= UInt<1>("h00") + wire ld_byte_hitvecfn_hi : UInt<4>[4] @[el2_lsu_bus_buffer.scala 132:33] + wire ld_byte_ibuf_hit_hi : UInt<4> + ld_byte_ibuf_hit_hi <= UInt<1>("h00") + wire buf_byteen : UInt<4>[4] @[el2_lsu_bus_buffer.scala 134:24] + buf_byteen[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 135:14] + buf_byteen[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 135:14] + buf_byteen[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 135:14] + buf_byteen[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 135:14] + wire buf_nxtstate : UInt<3>[4] @[el2_lsu_bus_buffer.scala 136:26] + buf_nxtstate[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 137:16] + buf_nxtstate[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 137:16] + buf_nxtstate[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 137:16] + buf_nxtstate[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 137:16] + wire buf_wr_en : UInt<1>[4] @[el2_lsu_bus_buffer.scala 138:23] + buf_wr_en[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 139:13] + buf_wr_en[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 139:13] + buf_wr_en[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 139:13] + buf_wr_en[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 139:13] + wire buf_data_en : UInt<1>[4] @[el2_lsu_bus_buffer.scala 140:25] + buf_data_en[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 141:15] + buf_data_en[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 141:15] + buf_data_en[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 141:15] + buf_data_en[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 141:15] + wire buf_state_bus_en : UInt<1>[4] @[el2_lsu_bus_buffer.scala 142:30] + buf_state_bus_en[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 143:20] + buf_state_bus_en[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 143:20] + buf_state_bus_en[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 143:20] + buf_state_bus_en[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 143:20] + wire buf_ldfwd_in : UInt<1>[4] @[el2_lsu_bus_buffer.scala 144:26] + buf_ldfwd_in[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 145:16] + buf_ldfwd_in[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 145:16] + buf_ldfwd_in[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 145:16] + buf_ldfwd_in[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 145:16] + wire buf_ldfwd_en : UInt<1>[4] @[el2_lsu_bus_buffer.scala 146:26] + buf_ldfwd_en[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 147:16] + buf_ldfwd_en[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 147:16] + buf_ldfwd_en[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 147:16] + buf_ldfwd_en[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 147:16] + wire buf_data_in : UInt<4>[4] @[el2_lsu_bus_buffer.scala 148:25] + buf_data_in[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 149:15] + buf_data_in[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 149:15] + buf_data_in[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 149:15] + buf_data_in[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 149:15] + wire buf_ldfwdtag_in : UInt<2>[4] @[el2_lsu_bus_buffer.scala 150:29] + buf_ldfwdtag_in[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 151:19] + buf_ldfwdtag_in[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 151:19] + buf_ldfwdtag_in[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 151:19] + buf_ldfwdtag_in[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 151:19] + wire buf_error_en : UInt<1>[4] @[el2_lsu_bus_buffer.scala 152:26] + buf_error_en[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 153:16] + buf_error_en[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 153:16] + buf_error_en[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 153:16] + buf_error_en[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 153:16] + wire bus_rsp_read_error : UInt<1> + bus_rsp_read_error <= UInt<1>("h00") + wire bus_rsp_rdata : UInt<64> + bus_rsp_rdata <= UInt<1>("h00") + wire bus_rsp_write_error : UInt<1> + bus_rsp_write_error <= UInt<1>("h00") + wire buf_dualtag : UInt<2>[4] @[el2_lsu_bus_buffer.scala 157:25] + buf_dualtag[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 158:15] + buf_dualtag[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 158:15] + buf_dualtag[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 158:15] + buf_dualtag[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 158:15] + wire buf_ldfwd : UInt<4> + buf_ldfwd <= UInt<1>("h00") + wire buf_resp_state_bus_en : UInt<1>[4] @[el2_lsu_bus_buffer.scala 160:35] + buf_resp_state_bus_en[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 161:25] + buf_resp_state_bus_en[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 161:25] + buf_resp_state_bus_en[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 161:25] + buf_resp_state_bus_en[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 161:25] + wire any_done_wait_state : UInt<1> + any_done_wait_state <= UInt<1>("h00") + wire bus_rsp_write : UInt<1> + bus_rsp_write <= UInt<1>("h00") + wire bus_rsp_write_tag : UInt<3> + bus_rsp_write_tag <= UInt<1>("h00") + wire buf_ldfwdtag : UInt<2>[4] @[el2_lsu_bus_buffer.scala 165:26] + buf_ldfwdtag[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 166:16] + buf_ldfwdtag[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 166:16] + buf_ldfwdtag[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 166:16] + buf_ldfwdtag[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 166:16] + wire buf_rst : UInt<1>[4] @[el2_lsu_bus_buffer.scala 167:21] + buf_rst[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 168:11] + buf_rst[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 168:11] + buf_rst[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 168:11] + buf_rst[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 168:11] + wire ibuf_drainvec_vld : UInt<4> + ibuf_drainvec_vld <= UInt<1>("h00") + wire buf_byteen_in : UInt<3>[4] @[el2_lsu_bus_buffer.scala 170:27] + buf_byteen_in[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 171:17] + buf_byteen_in[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 171:17] + buf_byteen_in[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 171:17] + buf_byteen_in[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 171:17] + wire buf_addr_in : UInt<32>[4] @[el2_lsu_bus_buffer.scala 172:25] + buf_addr_in[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 173:15] + buf_addr_in[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 173:15] + buf_addr_in[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 173:15] + buf_addr_in[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 173:15] + wire buf_dual_in : UInt<4> + buf_dual_in <= UInt<1>("h00") + wire buf_samedw_in : UInt<4> + buf_samedw_in <= UInt<1>("h00") + wire buf_nomerge_in : UInt<4> + buf_nomerge_in <= UInt<1>("h00") + wire buf_dualhi_in : UInt<4> + buf_dualhi_in <= UInt<1>("h00") + wire buf_dualtag_in : UInt<2>[4] @[el2_lsu_bus_buffer.scala 178:28] + buf_dualtag_in[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 179:18] + buf_dualtag_in[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 179:18] + buf_dualtag_in[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 179:18] + buf_dualtag_in[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 179:18] + wire buf_sideeffect_in : UInt<4> + buf_sideeffect_in <= UInt<1>("h00") + wire buf_unsign_in : UInt<4> + buf_unsign_in <= UInt<1>("h00") + wire buf_sz_in : UInt<2>[4] @[el2_lsu_bus_buffer.scala 182:23] + buf_sz_in[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 183:13] + buf_sz_in[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 183:13] + buf_sz_in[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 183:13] + buf_sz_in[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 183:13] + wire buf_write_in : UInt<4> + buf_write_in <= UInt<1>("h00") + wire buf_unsign : UInt<4> + buf_unsign <= UInt<1>("h00") + wire buf_error : UInt<4> + buf_error <= UInt<1>("h00") + node _T_56 = orr(ld_byte_hitvecfn_lo[0]) @[el2_lsu_bus_buffer.scala 188:73] + node _T_57 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[el2_lsu_bus_buffer.scala 188:98] + node _T_58 = or(_T_56, _T_57) @[el2_lsu_bus_buffer.scala 188:77] + node _T_59 = orr(ld_byte_hitvecfn_lo[1]) @[el2_lsu_bus_buffer.scala 188:73] + node _T_60 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[el2_lsu_bus_buffer.scala 188:98] + node _T_61 = or(_T_59, _T_60) @[el2_lsu_bus_buffer.scala 188:77] + node _T_62 = orr(ld_byte_hitvecfn_lo[2]) @[el2_lsu_bus_buffer.scala 188:73] + node _T_63 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[el2_lsu_bus_buffer.scala 188:98] + node _T_64 = or(_T_62, _T_63) @[el2_lsu_bus_buffer.scala 188:77] + node _T_65 = orr(ld_byte_hitvecfn_lo[3]) @[el2_lsu_bus_buffer.scala 188:73] + node _T_66 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[el2_lsu_bus_buffer.scala 188:98] + node _T_67 = or(_T_65, _T_66) @[el2_lsu_bus_buffer.scala 188:77] + node _T_68 = cat(_T_67, _T_64) @[Cat.scala 29:58] + node _T_69 = cat(_T_68, _T_61) @[Cat.scala 29:58] + node _T_70 = cat(_T_69, _T_58) @[Cat.scala 29:58] + io.ld_byte_hit_buf_lo <= _T_70 @[el2_lsu_bus_buffer.scala 188:25] + node _T_71 = orr(ld_byte_hitvecfn_hi[0]) @[el2_lsu_bus_buffer.scala 189:73] + node _T_72 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[el2_lsu_bus_buffer.scala 189:98] + node _T_73 = or(_T_71, _T_72) @[el2_lsu_bus_buffer.scala 189:77] + node _T_74 = orr(ld_byte_hitvecfn_hi[1]) @[el2_lsu_bus_buffer.scala 189:73] + node _T_75 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[el2_lsu_bus_buffer.scala 189:98] + node _T_76 = or(_T_74, _T_75) @[el2_lsu_bus_buffer.scala 189:77] + node _T_77 = orr(ld_byte_hitvecfn_hi[2]) @[el2_lsu_bus_buffer.scala 189:73] + node _T_78 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[el2_lsu_bus_buffer.scala 189:98] + node _T_79 = or(_T_77, _T_78) @[el2_lsu_bus_buffer.scala 189:77] + node _T_80 = orr(ld_byte_hitvecfn_hi[3]) @[el2_lsu_bus_buffer.scala 189:73] + node _T_81 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[el2_lsu_bus_buffer.scala 189:98] + node _T_82 = or(_T_80, _T_81) @[el2_lsu_bus_buffer.scala 189:77] + node _T_83 = cat(_T_82, _T_79) @[Cat.scala 29:58] + node _T_84 = cat(_T_83, _T_76) @[Cat.scala 29:58] + node _T_85 = cat(_T_84, _T_73) @[Cat.scala 29:58] + io.ld_byte_hit_buf_hi <= _T_85 @[el2_lsu_bus_buffer.scala 189:25] + node _T_86 = bits(buf_byteen[0], 0, 0) @[el2_lsu_bus_buffer.scala 191:110] + node _T_87 = and(ld_addr_hitvec_lo_0, _T_86) @[el2_lsu_bus_buffer.scala 191:95] + node _T_88 = bits(ldst_byteen_lo_m, 0, 0) @[el2_lsu_bus_buffer.scala 191:132] + node _T_89 = and(_T_87, _T_88) @[el2_lsu_bus_buffer.scala 191:114] + node _T_90 = bits(buf_byteen[1], 0, 0) @[el2_lsu_bus_buffer.scala 191:110] + node _T_91 = and(ld_addr_hitvec_lo_1, _T_90) @[el2_lsu_bus_buffer.scala 191:95] + node _T_92 = bits(ldst_byteen_lo_m, 0, 0) @[el2_lsu_bus_buffer.scala 191:132] + node _T_93 = and(_T_91, _T_92) @[el2_lsu_bus_buffer.scala 191:114] + node _T_94 = bits(buf_byteen[2], 0, 0) @[el2_lsu_bus_buffer.scala 191:110] + node _T_95 = and(ld_addr_hitvec_lo_2, _T_94) @[el2_lsu_bus_buffer.scala 191:95] + node _T_96 = bits(ldst_byteen_lo_m, 0, 0) @[el2_lsu_bus_buffer.scala 191:132] + node _T_97 = and(_T_95, _T_96) @[el2_lsu_bus_buffer.scala 191:114] + node _T_98 = bits(buf_byteen[3], 0, 0) @[el2_lsu_bus_buffer.scala 191:110] + node _T_99 = and(ld_addr_hitvec_lo_3, _T_98) @[el2_lsu_bus_buffer.scala 191:95] + node _T_100 = bits(ldst_byteen_lo_m, 0, 0) @[el2_lsu_bus_buffer.scala 191:132] + node _T_101 = and(_T_99, _T_100) @[el2_lsu_bus_buffer.scala 191:114] + node _T_102 = cat(_T_101, _T_97) @[Cat.scala 29:58] + node _T_103 = cat(_T_102, _T_93) @[Cat.scala 29:58] + node ld_byte_hitvec_lo_0 = cat(_T_103, _T_89) @[Cat.scala 29:58] + node _T_104 = bits(buf_byteen[0], 1, 1) @[el2_lsu_bus_buffer.scala 191:110] + node _T_105 = and(ld_addr_hitvec_lo_0, _T_104) @[el2_lsu_bus_buffer.scala 191:95] + node _T_106 = bits(ldst_byteen_lo_m, 1, 1) @[el2_lsu_bus_buffer.scala 191:132] + node _T_107 = and(_T_105, _T_106) @[el2_lsu_bus_buffer.scala 191:114] + node _T_108 = bits(buf_byteen[1], 1, 1) @[el2_lsu_bus_buffer.scala 191:110] + node _T_109 = and(ld_addr_hitvec_lo_1, _T_108) @[el2_lsu_bus_buffer.scala 191:95] + node _T_110 = bits(ldst_byteen_lo_m, 1, 1) @[el2_lsu_bus_buffer.scala 191:132] + node _T_111 = and(_T_109, _T_110) @[el2_lsu_bus_buffer.scala 191:114] + node _T_112 = bits(buf_byteen[2], 1, 1) @[el2_lsu_bus_buffer.scala 191:110] + node _T_113 = and(ld_addr_hitvec_lo_2, _T_112) @[el2_lsu_bus_buffer.scala 191:95] + node _T_114 = bits(ldst_byteen_lo_m, 1, 1) @[el2_lsu_bus_buffer.scala 191:132] + node _T_115 = and(_T_113, _T_114) @[el2_lsu_bus_buffer.scala 191:114] + node _T_116 = bits(buf_byteen[3], 1, 1) @[el2_lsu_bus_buffer.scala 191:110] + node _T_117 = and(ld_addr_hitvec_lo_3, _T_116) @[el2_lsu_bus_buffer.scala 191:95] + node _T_118 = bits(ldst_byteen_lo_m, 1, 1) @[el2_lsu_bus_buffer.scala 191:132] + node _T_119 = and(_T_117, _T_118) @[el2_lsu_bus_buffer.scala 191:114] + node _T_120 = cat(_T_119, _T_115) @[Cat.scala 29:58] + node _T_121 = cat(_T_120, _T_111) @[Cat.scala 29:58] + node ld_byte_hitvec_lo_1 = cat(_T_121, _T_107) @[Cat.scala 29:58] + node _T_122 = bits(buf_byteen[0], 2, 2) @[el2_lsu_bus_buffer.scala 191:110] + node _T_123 = and(ld_addr_hitvec_lo_0, _T_122) @[el2_lsu_bus_buffer.scala 191:95] + node _T_124 = bits(ldst_byteen_lo_m, 2, 2) @[el2_lsu_bus_buffer.scala 191:132] + node _T_125 = and(_T_123, _T_124) @[el2_lsu_bus_buffer.scala 191:114] + node _T_126 = bits(buf_byteen[1], 2, 2) @[el2_lsu_bus_buffer.scala 191:110] + node _T_127 = and(ld_addr_hitvec_lo_1, _T_126) @[el2_lsu_bus_buffer.scala 191:95] + node _T_128 = bits(ldst_byteen_lo_m, 2, 2) @[el2_lsu_bus_buffer.scala 191:132] + node _T_129 = and(_T_127, _T_128) @[el2_lsu_bus_buffer.scala 191:114] + node _T_130 = bits(buf_byteen[2], 2, 2) @[el2_lsu_bus_buffer.scala 191:110] + node _T_131 = and(ld_addr_hitvec_lo_2, _T_130) @[el2_lsu_bus_buffer.scala 191:95] + node _T_132 = bits(ldst_byteen_lo_m, 2, 2) @[el2_lsu_bus_buffer.scala 191:132] + node _T_133 = and(_T_131, _T_132) @[el2_lsu_bus_buffer.scala 191:114] + node _T_134 = bits(buf_byteen[3], 2, 2) @[el2_lsu_bus_buffer.scala 191:110] + node _T_135 = and(ld_addr_hitvec_lo_3, _T_134) @[el2_lsu_bus_buffer.scala 191:95] + node _T_136 = bits(ldst_byteen_lo_m, 2, 2) @[el2_lsu_bus_buffer.scala 191:132] + node _T_137 = and(_T_135, _T_136) @[el2_lsu_bus_buffer.scala 191:114] + node _T_138 = cat(_T_137, _T_133) @[Cat.scala 29:58] + node _T_139 = cat(_T_138, _T_129) @[Cat.scala 29:58] + node ld_byte_hitvec_lo_2 = cat(_T_139, _T_125) @[Cat.scala 29:58] + node _T_140 = bits(buf_byteen[0], 3, 3) @[el2_lsu_bus_buffer.scala 191:110] + node _T_141 = and(ld_addr_hitvec_lo_0, _T_140) @[el2_lsu_bus_buffer.scala 191:95] + node _T_142 = bits(ldst_byteen_lo_m, 3, 3) @[el2_lsu_bus_buffer.scala 191:132] + node _T_143 = and(_T_141, _T_142) @[el2_lsu_bus_buffer.scala 191:114] + node _T_144 = bits(buf_byteen[1], 3, 3) @[el2_lsu_bus_buffer.scala 191:110] + node _T_145 = and(ld_addr_hitvec_lo_1, _T_144) @[el2_lsu_bus_buffer.scala 191:95] + node _T_146 = bits(ldst_byteen_lo_m, 3, 3) @[el2_lsu_bus_buffer.scala 191:132] + node _T_147 = and(_T_145, _T_146) @[el2_lsu_bus_buffer.scala 191:114] + node _T_148 = bits(buf_byteen[2], 3, 3) @[el2_lsu_bus_buffer.scala 191:110] + node _T_149 = and(ld_addr_hitvec_lo_2, _T_148) @[el2_lsu_bus_buffer.scala 191:95] + node _T_150 = bits(ldst_byteen_lo_m, 3, 3) @[el2_lsu_bus_buffer.scala 191:132] + node _T_151 = and(_T_149, _T_150) @[el2_lsu_bus_buffer.scala 191:114] + node _T_152 = bits(buf_byteen[3], 3, 3) @[el2_lsu_bus_buffer.scala 191:110] + node _T_153 = and(ld_addr_hitvec_lo_3, _T_152) @[el2_lsu_bus_buffer.scala 191:95] + node _T_154 = bits(ldst_byteen_lo_m, 3, 3) @[el2_lsu_bus_buffer.scala 191:132] + node _T_155 = and(_T_153, _T_154) @[el2_lsu_bus_buffer.scala 191:114] + node _T_156 = cat(_T_155, _T_151) @[Cat.scala 29:58] + node _T_157 = cat(_T_156, _T_147) @[Cat.scala 29:58] + node ld_byte_hitvec_lo_3 = cat(_T_157, _T_143) @[Cat.scala 29:58] + node _T_158 = bits(buf_byteen[0], 0, 0) @[el2_lsu_bus_buffer.scala 192:110] + node _T_159 = and(ld_addr_hitvec_hi_0, _T_158) @[el2_lsu_bus_buffer.scala 192:95] + node _T_160 = bits(ldst_byteen_hi_m, 0, 0) @[el2_lsu_bus_buffer.scala 192:132] + node _T_161 = and(_T_159, _T_160) @[el2_lsu_bus_buffer.scala 192:114] + node _T_162 = bits(buf_byteen[1], 0, 0) @[el2_lsu_bus_buffer.scala 192:110] + node _T_163 = and(ld_addr_hitvec_hi_1, _T_162) @[el2_lsu_bus_buffer.scala 192:95] + node _T_164 = bits(ldst_byteen_hi_m, 0, 0) @[el2_lsu_bus_buffer.scala 192:132] + node _T_165 = and(_T_163, _T_164) @[el2_lsu_bus_buffer.scala 192:114] + node _T_166 = bits(buf_byteen[2], 0, 0) @[el2_lsu_bus_buffer.scala 192:110] + node _T_167 = and(ld_addr_hitvec_hi_2, _T_166) @[el2_lsu_bus_buffer.scala 192:95] + node _T_168 = bits(ldst_byteen_hi_m, 0, 0) @[el2_lsu_bus_buffer.scala 192:132] + node _T_169 = and(_T_167, _T_168) @[el2_lsu_bus_buffer.scala 192:114] + node _T_170 = bits(buf_byteen[3], 0, 0) @[el2_lsu_bus_buffer.scala 192:110] + node _T_171 = and(ld_addr_hitvec_hi_3, _T_170) @[el2_lsu_bus_buffer.scala 192:95] + node _T_172 = bits(ldst_byteen_hi_m, 0, 0) @[el2_lsu_bus_buffer.scala 192:132] + node _T_173 = and(_T_171, _T_172) @[el2_lsu_bus_buffer.scala 192:114] + node _T_174 = cat(_T_173, _T_169) @[Cat.scala 29:58] + node _T_175 = cat(_T_174, _T_165) @[Cat.scala 29:58] + node ld_byte_hitvec_hi_0 = cat(_T_175, _T_161) @[Cat.scala 29:58] + node _T_176 = bits(buf_byteen[0], 1, 1) @[el2_lsu_bus_buffer.scala 192:110] + node _T_177 = and(ld_addr_hitvec_hi_0, _T_176) @[el2_lsu_bus_buffer.scala 192:95] + node _T_178 = bits(ldst_byteen_hi_m, 1, 1) @[el2_lsu_bus_buffer.scala 192:132] + node _T_179 = and(_T_177, _T_178) @[el2_lsu_bus_buffer.scala 192:114] + node _T_180 = bits(buf_byteen[1], 1, 1) @[el2_lsu_bus_buffer.scala 192:110] + node _T_181 = and(ld_addr_hitvec_hi_1, _T_180) @[el2_lsu_bus_buffer.scala 192:95] + node _T_182 = bits(ldst_byteen_hi_m, 1, 1) @[el2_lsu_bus_buffer.scala 192:132] + node _T_183 = and(_T_181, _T_182) @[el2_lsu_bus_buffer.scala 192:114] + node _T_184 = bits(buf_byteen[2], 1, 1) @[el2_lsu_bus_buffer.scala 192:110] + node _T_185 = and(ld_addr_hitvec_hi_2, _T_184) @[el2_lsu_bus_buffer.scala 192:95] + node _T_186 = bits(ldst_byteen_hi_m, 1, 1) @[el2_lsu_bus_buffer.scala 192:132] + node _T_187 = and(_T_185, _T_186) @[el2_lsu_bus_buffer.scala 192:114] + node _T_188 = bits(buf_byteen[3], 1, 1) @[el2_lsu_bus_buffer.scala 192:110] + node _T_189 = and(ld_addr_hitvec_hi_3, _T_188) @[el2_lsu_bus_buffer.scala 192:95] + node _T_190 = bits(ldst_byteen_hi_m, 1, 1) @[el2_lsu_bus_buffer.scala 192:132] + node _T_191 = and(_T_189, _T_190) @[el2_lsu_bus_buffer.scala 192:114] + node _T_192 = cat(_T_191, _T_187) @[Cat.scala 29:58] + node _T_193 = cat(_T_192, _T_183) @[Cat.scala 29:58] + node ld_byte_hitvec_hi_1 = cat(_T_193, _T_179) @[Cat.scala 29:58] + node _T_194 = bits(buf_byteen[0], 2, 2) @[el2_lsu_bus_buffer.scala 192:110] + node _T_195 = and(ld_addr_hitvec_hi_0, _T_194) @[el2_lsu_bus_buffer.scala 192:95] + node _T_196 = bits(ldst_byteen_hi_m, 2, 2) @[el2_lsu_bus_buffer.scala 192:132] + node _T_197 = and(_T_195, _T_196) @[el2_lsu_bus_buffer.scala 192:114] + node _T_198 = bits(buf_byteen[1], 2, 2) @[el2_lsu_bus_buffer.scala 192:110] + node _T_199 = and(ld_addr_hitvec_hi_1, _T_198) @[el2_lsu_bus_buffer.scala 192:95] + node _T_200 = bits(ldst_byteen_hi_m, 2, 2) @[el2_lsu_bus_buffer.scala 192:132] + node _T_201 = and(_T_199, _T_200) @[el2_lsu_bus_buffer.scala 192:114] + node _T_202 = bits(buf_byteen[2], 2, 2) @[el2_lsu_bus_buffer.scala 192:110] + node _T_203 = and(ld_addr_hitvec_hi_2, _T_202) @[el2_lsu_bus_buffer.scala 192:95] + node _T_204 = bits(ldst_byteen_hi_m, 2, 2) @[el2_lsu_bus_buffer.scala 192:132] + node _T_205 = and(_T_203, _T_204) @[el2_lsu_bus_buffer.scala 192:114] + node _T_206 = bits(buf_byteen[3], 2, 2) @[el2_lsu_bus_buffer.scala 192:110] + node _T_207 = and(ld_addr_hitvec_hi_3, _T_206) @[el2_lsu_bus_buffer.scala 192:95] + node _T_208 = bits(ldst_byteen_hi_m, 2, 2) @[el2_lsu_bus_buffer.scala 192:132] + node _T_209 = and(_T_207, _T_208) @[el2_lsu_bus_buffer.scala 192:114] + node _T_210 = cat(_T_209, _T_205) @[Cat.scala 29:58] + node _T_211 = cat(_T_210, _T_201) @[Cat.scala 29:58] + node ld_byte_hitvec_hi_2 = cat(_T_211, _T_197) @[Cat.scala 29:58] + node _T_212 = bits(buf_byteen[0], 3, 3) @[el2_lsu_bus_buffer.scala 192:110] + node _T_213 = and(ld_addr_hitvec_hi_0, _T_212) @[el2_lsu_bus_buffer.scala 192:95] + node _T_214 = bits(ldst_byteen_hi_m, 3, 3) @[el2_lsu_bus_buffer.scala 192:132] + node _T_215 = and(_T_213, _T_214) @[el2_lsu_bus_buffer.scala 192:114] + node _T_216 = bits(buf_byteen[1], 3, 3) @[el2_lsu_bus_buffer.scala 192:110] + node _T_217 = and(ld_addr_hitvec_hi_1, _T_216) @[el2_lsu_bus_buffer.scala 192:95] + node _T_218 = bits(ldst_byteen_hi_m, 3, 3) @[el2_lsu_bus_buffer.scala 192:132] + node _T_219 = and(_T_217, _T_218) @[el2_lsu_bus_buffer.scala 192:114] + node _T_220 = bits(buf_byteen[2], 3, 3) @[el2_lsu_bus_buffer.scala 192:110] + node _T_221 = and(ld_addr_hitvec_hi_2, _T_220) @[el2_lsu_bus_buffer.scala 192:95] + node _T_222 = bits(ldst_byteen_hi_m, 3, 3) @[el2_lsu_bus_buffer.scala 192:132] + node _T_223 = and(_T_221, _T_222) @[el2_lsu_bus_buffer.scala 192:114] + node _T_224 = bits(buf_byteen[3], 3, 3) @[el2_lsu_bus_buffer.scala 192:110] + node _T_225 = and(ld_addr_hitvec_hi_3, _T_224) @[el2_lsu_bus_buffer.scala 192:95] + node _T_226 = bits(ldst_byteen_hi_m, 3, 3) @[el2_lsu_bus_buffer.scala 192:132] + node _T_227 = and(_T_225, _T_226) @[el2_lsu_bus_buffer.scala 192:114] + node _T_228 = cat(_T_227, _T_223) @[Cat.scala 29:58] + node _T_229 = cat(_T_228, _T_219) @[Cat.scala 29:58] + node ld_byte_hitvec_hi_3 = cat(_T_229, _T_215) @[Cat.scala 29:58] + wire buf_age_younger : UInt<4>[4] @[el2_lsu_bus_buffer.scala 194:29] + buf_age_younger[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 195:19] + buf_age_younger[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 195:19] + buf_age_younger[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 195:19] + buf_age_younger[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 195:19] + node _T_230 = bits(ld_byte_hitvec_lo_0, 0, 0) @[el2_lsu_bus_buffer.scala 196:93] + node _T_231 = and(ld_byte_hitvec_lo_0, buf_age_younger[0]) @[el2_lsu_bus_buffer.scala 196:122] + node _T_232 = orr(_T_231) @[el2_lsu_bus_buffer.scala 196:144] + node _T_233 = eq(_T_232, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 196:99] + node _T_234 = and(_T_230, _T_233) @[el2_lsu_bus_buffer.scala 196:97] + node _T_235 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[el2_lsu_bus_buffer.scala 196:170] + node _T_236 = eq(_T_235, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 196:150] + node _T_237 = and(_T_234, _T_236) @[el2_lsu_bus_buffer.scala 196:148] + node _T_238 = bits(ld_byte_hitvec_lo_0, 1, 1) @[el2_lsu_bus_buffer.scala 196:93] + node _T_239 = and(ld_byte_hitvec_lo_0, buf_age_younger[1]) @[el2_lsu_bus_buffer.scala 196:122] + node _T_240 = orr(_T_239) @[el2_lsu_bus_buffer.scala 196:144] + node _T_241 = eq(_T_240, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 196:99] + node _T_242 = and(_T_238, _T_241) @[el2_lsu_bus_buffer.scala 196:97] + node _T_243 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[el2_lsu_bus_buffer.scala 196:170] + node _T_244 = eq(_T_243, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 196:150] + node _T_245 = and(_T_242, _T_244) @[el2_lsu_bus_buffer.scala 196:148] + node _T_246 = bits(ld_byte_hitvec_lo_0, 2, 2) @[el2_lsu_bus_buffer.scala 196:93] + node _T_247 = and(ld_byte_hitvec_lo_0, buf_age_younger[2]) @[el2_lsu_bus_buffer.scala 196:122] + node _T_248 = orr(_T_247) @[el2_lsu_bus_buffer.scala 196:144] + node _T_249 = eq(_T_248, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 196:99] + node _T_250 = and(_T_246, _T_249) @[el2_lsu_bus_buffer.scala 196:97] + node _T_251 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[el2_lsu_bus_buffer.scala 196:170] + node _T_252 = eq(_T_251, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 196:150] + node _T_253 = and(_T_250, _T_252) @[el2_lsu_bus_buffer.scala 196:148] + node _T_254 = bits(ld_byte_hitvec_lo_0, 3, 3) @[el2_lsu_bus_buffer.scala 196:93] + node _T_255 = and(ld_byte_hitvec_lo_0, buf_age_younger[3]) @[el2_lsu_bus_buffer.scala 196:122] + node _T_256 = orr(_T_255) @[el2_lsu_bus_buffer.scala 196:144] + node _T_257 = eq(_T_256, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 196:99] + node _T_258 = and(_T_254, _T_257) @[el2_lsu_bus_buffer.scala 196:97] + node _T_259 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[el2_lsu_bus_buffer.scala 196:170] + node _T_260 = eq(_T_259, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 196:150] + node _T_261 = and(_T_258, _T_260) @[el2_lsu_bus_buffer.scala 196:148] + node _T_262 = cat(_T_261, _T_253) @[Cat.scala 29:58] + node _T_263 = cat(_T_262, _T_245) @[Cat.scala 29:58] + node _T_264 = cat(_T_263, _T_237) @[Cat.scala 29:58] + node _T_265 = bits(ld_byte_hitvec_lo_1, 0, 0) @[el2_lsu_bus_buffer.scala 196:93] + node _T_266 = and(ld_byte_hitvec_lo_1, buf_age_younger[0]) @[el2_lsu_bus_buffer.scala 196:122] + node _T_267 = orr(_T_266) @[el2_lsu_bus_buffer.scala 196:144] + node _T_268 = eq(_T_267, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 196:99] + node _T_269 = and(_T_265, _T_268) @[el2_lsu_bus_buffer.scala 196:97] + node _T_270 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[el2_lsu_bus_buffer.scala 196:170] + node _T_271 = eq(_T_270, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 196:150] + node _T_272 = and(_T_269, _T_271) @[el2_lsu_bus_buffer.scala 196:148] + node _T_273 = bits(ld_byte_hitvec_lo_1, 1, 1) @[el2_lsu_bus_buffer.scala 196:93] + node _T_274 = and(ld_byte_hitvec_lo_1, buf_age_younger[1]) @[el2_lsu_bus_buffer.scala 196:122] + node _T_275 = orr(_T_274) @[el2_lsu_bus_buffer.scala 196:144] + node _T_276 = eq(_T_275, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 196:99] + node _T_277 = and(_T_273, _T_276) @[el2_lsu_bus_buffer.scala 196:97] + node _T_278 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[el2_lsu_bus_buffer.scala 196:170] + node _T_279 = eq(_T_278, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 196:150] + node _T_280 = and(_T_277, _T_279) @[el2_lsu_bus_buffer.scala 196:148] + node _T_281 = bits(ld_byte_hitvec_lo_1, 2, 2) @[el2_lsu_bus_buffer.scala 196:93] + node _T_282 = and(ld_byte_hitvec_lo_1, buf_age_younger[2]) @[el2_lsu_bus_buffer.scala 196:122] + node _T_283 = orr(_T_282) @[el2_lsu_bus_buffer.scala 196:144] + node _T_284 = eq(_T_283, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 196:99] + node _T_285 = and(_T_281, _T_284) @[el2_lsu_bus_buffer.scala 196:97] + node _T_286 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[el2_lsu_bus_buffer.scala 196:170] + node _T_287 = eq(_T_286, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 196:150] + node _T_288 = and(_T_285, _T_287) @[el2_lsu_bus_buffer.scala 196:148] + node _T_289 = bits(ld_byte_hitvec_lo_1, 3, 3) @[el2_lsu_bus_buffer.scala 196:93] + node _T_290 = and(ld_byte_hitvec_lo_1, buf_age_younger[3]) @[el2_lsu_bus_buffer.scala 196:122] + node _T_291 = orr(_T_290) @[el2_lsu_bus_buffer.scala 196:144] + node _T_292 = eq(_T_291, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 196:99] + node _T_293 = and(_T_289, _T_292) @[el2_lsu_bus_buffer.scala 196:97] + node _T_294 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[el2_lsu_bus_buffer.scala 196:170] + node _T_295 = eq(_T_294, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 196:150] + node _T_296 = and(_T_293, _T_295) @[el2_lsu_bus_buffer.scala 196:148] + node _T_297 = cat(_T_296, _T_288) @[Cat.scala 29:58] + node _T_298 = cat(_T_297, _T_280) @[Cat.scala 29:58] + node _T_299 = cat(_T_298, _T_272) @[Cat.scala 29:58] + node _T_300 = bits(ld_byte_hitvec_lo_2, 0, 0) @[el2_lsu_bus_buffer.scala 196:93] + node _T_301 = and(ld_byte_hitvec_lo_2, buf_age_younger[0]) @[el2_lsu_bus_buffer.scala 196:122] + node _T_302 = orr(_T_301) @[el2_lsu_bus_buffer.scala 196:144] + node _T_303 = eq(_T_302, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 196:99] + node _T_304 = and(_T_300, _T_303) @[el2_lsu_bus_buffer.scala 196:97] + node _T_305 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[el2_lsu_bus_buffer.scala 196:170] + node _T_306 = eq(_T_305, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 196:150] + node _T_307 = and(_T_304, _T_306) @[el2_lsu_bus_buffer.scala 196:148] + node _T_308 = bits(ld_byte_hitvec_lo_2, 1, 1) @[el2_lsu_bus_buffer.scala 196:93] + node _T_309 = and(ld_byte_hitvec_lo_2, buf_age_younger[1]) @[el2_lsu_bus_buffer.scala 196:122] + node _T_310 = orr(_T_309) @[el2_lsu_bus_buffer.scala 196:144] + node _T_311 = eq(_T_310, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 196:99] + node _T_312 = and(_T_308, _T_311) @[el2_lsu_bus_buffer.scala 196:97] + node _T_313 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[el2_lsu_bus_buffer.scala 196:170] + node _T_314 = eq(_T_313, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 196:150] + node _T_315 = and(_T_312, _T_314) @[el2_lsu_bus_buffer.scala 196:148] + node _T_316 = bits(ld_byte_hitvec_lo_2, 2, 2) @[el2_lsu_bus_buffer.scala 196:93] + node _T_317 = and(ld_byte_hitvec_lo_2, buf_age_younger[2]) @[el2_lsu_bus_buffer.scala 196:122] + node _T_318 = orr(_T_317) @[el2_lsu_bus_buffer.scala 196:144] + node _T_319 = eq(_T_318, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 196:99] + node _T_320 = and(_T_316, _T_319) @[el2_lsu_bus_buffer.scala 196:97] + node _T_321 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[el2_lsu_bus_buffer.scala 196:170] + node _T_322 = eq(_T_321, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 196:150] + node _T_323 = and(_T_320, _T_322) @[el2_lsu_bus_buffer.scala 196:148] + node _T_324 = bits(ld_byte_hitvec_lo_2, 3, 3) @[el2_lsu_bus_buffer.scala 196:93] + node _T_325 = and(ld_byte_hitvec_lo_2, buf_age_younger[3]) @[el2_lsu_bus_buffer.scala 196:122] + node _T_326 = orr(_T_325) @[el2_lsu_bus_buffer.scala 196:144] + node _T_327 = eq(_T_326, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 196:99] + node _T_328 = and(_T_324, _T_327) @[el2_lsu_bus_buffer.scala 196:97] + node _T_329 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[el2_lsu_bus_buffer.scala 196:170] + node _T_330 = eq(_T_329, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 196:150] + node _T_331 = and(_T_328, _T_330) @[el2_lsu_bus_buffer.scala 196:148] + node _T_332 = cat(_T_331, _T_323) @[Cat.scala 29:58] + node _T_333 = cat(_T_332, _T_315) @[Cat.scala 29:58] + node _T_334 = cat(_T_333, _T_307) @[Cat.scala 29:58] + node _T_335 = bits(ld_byte_hitvec_lo_3, 0, 0) @[el2_lsu_bus_buffer.scala 196:93] + node _T_336 = and(ld_byte_hitvec_lo_3, buf_age_younger[0]) @[el2_lsu_bus_buffer.scala 196:122] + node _T_337 = orr(_T_336) @[el2_lsu_bus_buffer.scala 196:144] + node _T_338 = eq(_T_337, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 196:99] + node _T_339 = and(_T_335, _T_338) @[el2_lsu_bus_buffer.scala 196:97] + node _T_340 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[el2_lsu_bus_buffer.scala 196:170] + node _T_341 = eq(_T_340, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 196:150] + node _T_342 = and(_T_339, _T_341) @[el2_lsu_bus_buffer.scala 196:148] + node _T_343 = bits(ld_byte_hitvec_lo_3, 1, 1) @[el2_lsu_bus_buffer.scala 196:93] + node _T_344 = and(ld_byte_hitvec_lo_3, buf_age_younger[1]) @[el2_lsu_bus_buffer.scala 196:122] + node _T_345 = orr(_T_344) @[el2_lsu_bus_buffer.scala 196:144] + node _T_346 = eq(_T_345, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 196:99] + node _T_347 = and(_T_343, _T_346) @[el2_lsu_bus_buffer.scala 196:97] + node _T_348 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[el2_lsu_bus_buffer.scala 196:170] + node _T_349 = eq(_T_348, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 196:150] + node _T_350 = and(_T_347, _T_349) @[el2_lsu_bus_buffer.scala 196:148] + node _T_351 = bits(ld_byte_hitvec_lo_3, 2, 2) @[el2_lsu_bus_buffer.scala 196:93] + node _T_352 = and(ld_byte_hitvec_lo_3, buf_age_younger[2]) @[el2_lsu_bus_buffer.scala 196:122] + node _T_353 = orr(_T_352) @[el2_lsu_bus_buffer.scala 196:144] + node _T_354 = eq(_T_353, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 196:99] + node _T_355 = and(_T_351, _T_354) @[el2_lsu_bus_buffer.scala 196:97] + node _T_356 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[el2_lsu_bus_buffer.scala 196:170] + node _T_357 = eq(_T_356, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 196:150] + node _T_358 = and(_T_355, _T_357) @[el2_lsu_bus_buffer.scala 196:148] + node _T_359 = bits(ld_byte_hitvec_lo_3, 3, 3) @[el2_lsu_bus_buffer.scala 196:93] + node _T_360 = and(ld_byte_hitvec_lo_3, buf_age_younger[3]) @[el2_lsu_bus_buffer.scala 196:122] + node _T_361 = orr(_T_360) @[el2_lsu_bus_buffer.scala 196:144] + node _T_362 = eq(_T_361, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 196:99] + node _T_363 = and(_T_359, _T_362) @[el2_lsu_bus_buffer.scala 196:97] + node _T_364 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[el2_lsu_bus_buffer.scala 196:170] + node _T_365 = eq(_T_364, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 196:150] + node _T_366 = and(_T_363, _T_365) @[el2_lsu_bus_buffer.scala 196:148] + node _T_367 = cat(_T_366, _T_358) @[Cat.scala 29:58] + node _T_368 = cat(_T_367, _T_350) @[Cat.scala 29:58] + node _T_369 = cat(_T_368, _T_342) @[Cat.scala 29:58] + ld_byte_hitvecfn_lo[0] <= _T_264 @[el2_lsu_bus_buffer.scala 196:23] + ld_byte_hitvecfn_lo[1] <= _T_299 @[el2_lsu_bus_buffer.scala 196:23] + ld_byte_hitvecfn_lo[2] <= _T_334 @[el2_lsu_bus_buffer.scala 196:23] + ld_byte_hitvecfn_lo[3] <= _T_369 @[el2_lsu_bus_buffer.scala 196:23] + node _T_370 = bits(ld_byte_hitvec_hi_0, 0, 0) @[el2_lsu_bus_buffer.scala 197:93] + node _T_371 = and(ld_byte_hitvec_hi_0, buf_age_younger[0]) @[el2_lsu_bus_buffer.scala 197:122] + node _T_372 = orr(_T_371) @[el2_lsu_bus_buffer.scala 197:144] + node _T_373 = eq(_T_372, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 197:99] + node _T_374 = and(_T_370, _T_373) @[el2_lsu_bus_buffer.scala 197:97] + node _T_375 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[el2_lsu_bus_buffer.scala 197:170] + node _T_376 = eq(_T_375, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 197:150] + node _T_377 = and(_T_374, _T_376) @[el2_lsu_bus_buffer.scala 197:148] + node _T_378 = bits(ld_byte_hitvec_hi_0, 1, 1) @[el2_lsu_bus_buffer.scala 197:93] + node _T_379 = and(ld_byte_hitvec_hi_0, buf_age_younger[1]) @[el2_lsu_bus_buffer.scala 197:122] + node _T_380 = orr(_T_379) @[el2_lsu_bus_buffer.scala 197:144] + node _T_381 = eq(_T_380, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 197:99] + node _T_382 = and(_T_378, _T_381) @[el2_lsu_bus_buffer.scala 197:97] + node _T_383 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[el2_lsu_bus_buffer.scala 197:170] + node _T_384 = eq(_T_383, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 197:150] + node _T_385 = and(_T_382, _T_384) @[el2_lsu_bus_buffer.scala 197:148] + node _T_386 = bits(ld_byte_hitvec_hi_0, 2, 2) @[el2_lsu_bus_buffer.scala 197:93] + node _T_387 = and(ld_byte_hitvec_hi_0, buf_age_younger[2]) @[el2_lsu_bus_buffer.scala 197:122] + node _T_388 = orr(_T_387) @[el2_lsu_bus_buffer.scala 197:144] + node _T_389 = eq(_T_388, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 197:99] + node _T_390 = and(_T_386, _T_389) @[el2_lsu_bus_buffer.scala 197:97] + node _T_391 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[el2_lsu_bus_buffer.scala 197:170] + node _T_392 = eq(_T_391, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 197:150] + node _T_393 = and(_T_390, _T_392) @[el2_lsu_bus_buffer.scala 197:148] + node _T_394 = bits(ld_byte_hitvec_hi_0, 3, 3) @[el2_lsu_bus_buffer.scala 197:93] + node _T_395 = and(ld_byte_hitvec_hi_0, buf_age_younger[3]) @[el2_lsu_bus_buffer.scala 197:122] + node _T_396 = orr(_T_395) @[el2_lsu_bus_buffer.scala 197:144] + node _T_397 = eq(_T_396, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 197:99] + node _T_398 = and(_T_394, _T_397) @[el2_lsu_bus_buffer.scala 197:97] + node _T_399 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[el2_lsu_bus_buffer.scala 197:170] + node _T_400 = eq(_T_399, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 197:150] + node _T_401 = and(_T_398, _T_400) @[el2_lsu_bus_buffer.scala 197:148] + node _T_402 = cat(_T_401, _T_393) @[Cat.scala 29:58] + node _T_403 = cat(_T_402, _T_385) @[Cat.scala 29:58] + node _T_404 = cat(_T_403, _T_377) @[Cat.scala 29:58] + node _T_405 = bits(ld_byte_hitvec_hi_1, 0, 0) @[el2_lsu_bus_buffer.scala 197:93] + node _T_406 = and(ld_byte_hitvec_hi_1, buf_age_younger[0]) @[el2_lsu_bus_buffer.scala 197:122] + node _T_407 = orr(_T_406) @[el2_lsu_bus_buffer.scala 197:144] + node _T_408 = eq(_T_407, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 197:99] + node _T_409 = and(_T_405, _T_408) @[el2_lsu_bus_buffer.scala 197:97] + node _T_410 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[el2_lsu_bus_buffer.scala 197:170] + node _T_411 = eq(_T_410, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 197:150] + node _T_412 = and(_T_409, _T_411) @[el2_lsu_bus_buffer.scala 197:148] + node _T_413 = bits(ld_byte_hitvec_hi_1, 1, 1) @[el2_lsu_bus_buffer.scala 197:93] + node _T_414 = and(ld_byte_hitvec_hi_1, buf_age_younger[1]) @[el2_lsu_bus_buffer.scala 197:122] + node _T_415 = orr(_T_414) @[el2_lsu_bus_buffer.scala 197:144] + node _T_416 = eq(_T_415, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 197:99] + node _T_417 = and(_T_413, _T_416) @[el2_lsu_bus_buffer.scala 197:97] + node _T_418 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[el2_lsu_bus_buffer.scala 197:170] + node _T_419 = eq(_T_418, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 197:150] + node _T_420 = and(_T_417, _T_419) @[el2_lsu_bus_buffer.scala 197:148] + node _T_421 = bits(ld_byte_hitvec_hi_1, 2, 2) @[el2_lsu_bus_buffer.scala 197:93] + node _T_422 = and(ld_byte_hitvec_hi_1, buf_age_younger[2]) @[el2_lsu_bus_buffer.scala 197:122] + node _T_423 = orr(_T_422) @[el2_lsu_bus_buffer.scala 197:144] + node _T_424 = eq(_T_423, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 197:99] + node _T_425 = and(_T_421, _T_424) @[el2_lsu_bus_buffer.scala 197:97] + node _T_426 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[el2_lsu_bus_buffer.scala 197:170] + node _T_427 = eq(_T_426, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 197:150] + node _T_428 = and(_T_425, _T_427) @[el2_lsu_bus_buffer.scala 197:148] + node _T_429 = bits(ld_byte_hitvec_hi_1, 3, 3) @[el2_lsu_bus_buffer.scala 197:93] + node _T_430 = and(ld_byte_hitvec_hi_1, buf_age_younger[3]) @[el2_lsu_bus_buffer.scala 197:122] + node _T_431 = orr(_T_430) @[el2_lsu_bus_buffer.scala 197:144] + node _T_432 = eq(_T_431, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 197:99] + node _T_433 = and(_T_429, _T_432) @[el2_lsu_bus_buffer.scala 197:97] + node _T_434 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[el2_lsu_bus_buffer.scala 197:170] + node _T_435 = eq(_T_434, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 197:150] + node _T_436 = and(_T_433, _T_435) @[el2_lsu_bus_buffer.scala 197:148] + node _T_437 = cat(_T_436, _T_428) @[Cat.scala 29:58] + node _T_438 = cat(_T_437, _T_420) @[Cat.scala 29:58] + node _T_439 = cat(_T_438, _T_412) @[Cat.scala 29:58] + node _T_440 = bits(ld_byte_hitvec_hi_2, 0, 0) @[el2_lsu_bus_buffer.scala 197:93] + node _T_441 = and(ld_byte_hitvec_hi_2, buf_age_younger[0]) @[el2_lsu_bus_buffer.scala 197:122] + node _T_442 = orr(_T_441) @[el2_lsu_bus_buffer.scala 197:144] + node _T_443 = eq(_T_442, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 197:99] + node _T_444 = and(_T_440, _T_443) @[el2_lsu_bus_buffer.scala 197:97] + node _T_445 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[el2_lsu_bus_buffer.scala 197:170] + node _T_446 = eq(_T_445, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 197:150] + node _T_447 = and(_T_444, _T_446) @[el2_lsu_bus_buffer.scala 197:148] + node _T_448 = bits(ld_byte_hitvec_hi_2, 1, 1) @[el2_lsu_bus_buffer.scala 197:93] + node _T_449 = and(ld_byte_hitvec_hi_2, buf_age_younger[1]) @[el2_lsu_bus_buffer.scala 197:122] + node _T_450 = orr(_T_449) @[el2_lsu_bus_buffer.scala 197:144] + node _T_451 = eq(_T_450, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 197:99] + node _T_452 = and(_T_448, _T_451) @[el2_lsu_bus_buffer.scala 197:97] + node _T_453 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[el2_lsu_bus_buffer.scala 197:170] + node _T_454 = eq(_T_453, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 197:150] + node _T_455 = and(_T_452, _T_454) @[el2_lsu_bus_buffer.scala 197:148] + node _T_456 = bits(ld_byte_hitvec_hi_2, 2, 2) @[el2_lsu_bus_buffer.scala 197:93] + node _T_457 = and(ld_byte_hitvec_hi_2, buf_age_younger[2]) @[el2_lsu_bus_buffer.scala 197:122] + node _T_458 = orr(_T_457) @[el2_lsu_bus_buffer.scala 197:144] + node _T_459 = eq(_T_458, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 197:99] + node _T_460 = and(_T_456, _T_459) @[el2_lsu_bus_buffer.scala 197:97] + node _T_461 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[el2_lsu_bus_buffer.scala 197:170] + node _T_462 = eq(_T_461, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 197:150] + node _T_463 = and(_T_460, _T_462) @[el2_lsu_bus_buffer.scala 197:148] + node _T_464 = bits(ld_byte_hitvec_hi_2, 3, 3) @[el2_lsu_bus_buffer.scala 197:93] + node _T_465 = and(ld_byte_hitvec_hi_2, buf_age_younger[3]) @[el2_lsu_bus_buffer.scala 197:122] + node _T_466 = orr(_T_465) @[el2_lsu_bus_buffer.scala 197:144] + node _T_467 = eq(_T_466, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 197:99] + node _T_468 = and(_T_464, _T_467) @[el2_lsu_bus_buffer.scala 197:97] + node _T_469 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[el2_lsu_bus_buffer.scala 197:170] + node _T_470 = eq(_T_469, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 197:150] + node _T_471 = and(_T_468, _T_470) @[el2_lsu_bus_buffer.scala 197:148] + node _T_472 = cat(_T_471, _T_463) @[Cat.scala 29:58] + node _T_473 = cat(_T_472, _T_455) @[Cat.scala 29:58] + node _T_474 = cat(_T_473, _T_447) @[Cat.scala 29:58] + node _T_475 = bits(ld_byte_hitvec_hi_3, 0, 0) @[el2_lsu_bus_buffer.scala 197:93] + node _T_476 = and(ld_byte_hitvec_hi_3, buf_age_younger[0]) @[el2_lsu_bus_buffer.scala 197:122] + node _T_477 = orr(_T_476) @[el2_lsu_bus_buffer.scala 197:144] + node _T_478 = eq(_T_477, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 197:99] + node _T_479 = and(_T_475, _T_478) @[el2_lsu_bus_buffer.scala 197:97] + node _T_480 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[el2_lsu_bus_buffer.scala 197:170] + node _T_481 = eq(_T_480, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 197:150] + node _T_482 = and(_T_479, _T_481) @[el2_lsu_bus_buffer.scala 197:148] + node _T_483 = bits(ld_byte_hitvec_hi_3, 1, 1) @[el2_lsu_bus_buffer.scala 197:93] + node _T_484 = and(ld_byte_hitvec_hi_3, buf_age_younger[1]) @[el2_lsu_bus_buffer.scala 197:122] + node _T_485 = orr(_T_484) @[el2_lsu_bus_buffer.scala 197:144] + node _T_486 = eq(_T_485, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 197:99] + node _T_487 = and(_T_483, _T_486) @[el2_lsu_bus_buffer.scala 197:97] + node _T_488 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[el2_lsu_bus_buffer.scala 197:170] + node _T_489 = eq(_T_488, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 197:150] + node _T_490 = and(_T_487, _T_489) @[el2_lsu_bus_buffer.scala 197:148] + node _T_491 = bits(ld_byte_hitvec_hi_3, 2, 2) @[el2_lsu_bus_buffer.scala 197:93] + node _T_492 = and(ld_byte_hitvec_hi_3, buf_age_younger[2]) @[el2_lsu_bus_buffer.scala 197:122] + node _T_493 = orr(_T_492) @[el2_lsu_bus_buffer.scala 197:144] + node _T_494 = eq(_T_493, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 197:99] + node _T_495 = and(_T_491, _T_494) @[el2_lsu_bus_buffer.scala 197:97] + node _T_496 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[el2_lsu_bus_buffer.scala 197:170] + node _T_497 = eq(_T_496, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 197:150] + node _T_498 = and(_T_495, _T_497) @[el2_lsu_bus_buffer.scala 197:148] + node _T_499 = bits(ld_byte_hitvec_hi_3, 3, 3) @[el2_lsu_bus_buffer.scala 197:93] + node _T_500 = and(ld_byte_hitvec_hi_3, buf_age_younger[3]) @[el2_lsu_bus_buffer.scala 197:122] + node _T_501 = orr(_T_500) @[el2_lsu_bus_buffer.scala 197:144] + node _T_502 = eq(_T_501, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 197:99] + node _T_503 = and(_T_499, _T_502) @[el2_lsu_bus_buffer.scala 197:97] + node _T_504 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[el2_lsu_bus_buffer.scala 197:170] + node _T_505 = eq(_T_504, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 197:150] + node _T_506 = and(_T_503, _T_505) @[el2_lsu_bus_buffer.scala 197:148] + node _T_507 = cat(_T_506, _T_498) @[Cat.scala 29:58] + node _T_508 = cat(_T_507, _T_490) @[Cat.scala 29:58] + node _T_509 = cat(_T_508, _T_482) @[Cat.scala 29:58] + ld_byte_hitvecfn_hi[0] <= _T_404 @[el2_lsu_bus_buffer.scala 197:23] + ld_byte_hitvecfn_hi[1] <= _T_439 @[el2_lsu_bus_buffer.scala 197:23] + ld_byte_hitvecfn_hi[2] <= _T_474 @[el2_lsu_bus_buffer.scala 197:23] + ld_byte_hitvecfn_hi[3] <= _T_509 @[el2_lsu_bus_buffer.scala 197:23] + wire ibuf_addr : UInt<32> + ibuf_addr <= UInt<1>("h00") + wire ibuf_write : UInt<1> + ibuf_write <= UInt<1>("h00") + wire ibuf_valid : UInt<1> + ibuf_valid <= UInt<1>("h00") + node _T_510 = bits(io.lsu_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 202:43] + node _T_511 = bits(ibuf_addr, 31, 2) @[el2_lsu_bus_buffer.scala 202:64] + node _T_512 = eq(_T_510, _T_511) @[el2_lsu_bus_buffer.scala 202:51] + node _T_513 = and(_T_512, ibuf_write) @[el2_lsu_bus_buffer.scala 202:73] + node _T_514 = and(_T_513, ibuf_valid) @[el2_lsu_bus_buffer.scala 202:86] + node ld_addr_ibuf_hit_lo = and(_T_514, io.lsu_busreq_m) @[el2_lsu_bus_buffer.scala 202:99] + node _T_515 = bits(io.end_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 203:43] + node _T_516 = bits(ibuf_addr, 31, 2) @[el2_lsu_bus_buffer.scala 203:64] + node _T_517 = eq(_T_515, _T_516) @[el2_lsu_bus_buffer.scala 203:51] + node _T_518 = and(_T_517, ibuf_write) @[el2_lsu_bus_buffer.scala 203:73] + node _T_519 = and(_T_518, ibuf_valid) @[el2_lsu_bus_buffer.scala 203:86] + node ld_addr_ibuf_hit_hi = and(_T_519, io.lsu_busreq_m) @[el2_lsu_bus_buffer.scala 203:99] + wire ibuf_byteen : UInt<4> + ibuf_byteen <= UInt<1>("h00") + node _T_520 = bits(ibuf_byteen, 0, 0) @[el2_lsu_bus_buffer.scala 207:61] + node _T_521 = and(ld_addr_ibuf_hit_lo, _T_520) @[el2_lsu_bus_buffer.scala 207:48] + node _T_522 = bits(ldst_byteen_lo_m, 0, 0) @[el2_lsu_bus_buffer.scala 207:83] + node _T_523 = and(_T_521, _T_522) @[el2_lsu_bus_buffer.scala 207:65] + ld_byte_ibuf_hit_lo <= _T_523 @[el2_lsu_bus_buffer.scala 207:25] + node _T_524 = bits(ibuf_byteen, 0, 0) @[el2_lsu_bus_buffer.scala 208:61] + node _T_525 = and(ld_addr_ibuf_hit_hi, _T_524) @[el2_lsu_bus_buffer.scala 208:48] + node _T_526 = bits(ldst_byteen_hi_m, 0, 0) @[el2_lsu_bus_buffer.scala 208:83] + node _T_527 = and(_T_525, _T_526) @[el2_lsu_bus_buffer.scala 208:65] + ld_byte_ibuf_hit_hi <= _T_527 @[el2_lsu_bus_buffer.scala 208:25] + node _T_528 = bits(ibuf_byteen, 1, 1) @[el2_lsu_bus_buffer.scala 207:61] + node _T_529 = and(ld_addr_ibuf_hit_lo, _T_528) @[el2_lsu_bus_buffer.scala 207:48] + node _T_530 = bits(ldst_byteen_lo_m, 1, 1) @[el2_lsu_bus_buffer.scala 207:83] + node _T_531 = and(_T_529, _T_530) @[el2_lsu_bus_buffer.scala 207:65] + ld_byte_ibuf_hit_lo <= _T_531 @[el2_lsu_bus_buffer.scala 207:25] + node _T_532 = bits(ibuf_byteen, 1, 1) @[el2_lsu_bus_buffer.scala 208:61] + node _T_533 = and(ld_addr_ibuf_hit_hi, _T_532) @[el2_lsu_bus_buffer.scala 208:48] + node _T_534 = bits(ldst_byteen_hi_m, 1, 1) @[el2_lsu_bus_buffer.scala 208:83] + node _T_535 = and(_T_533, _T_534) @[el2_lsu_bus_buffer.scala 208:65] + ld_byte_ibuf_hit_hi <= _T_535 @[el2_lsu_bus_buffer.scala 208:25] + node _T_536 = bits(ibuf_byteen, 2, 2) @[el2_lsu_bus_buffer.scala 207:61] + node _T_537 = and(ld_addr_ibuf_hit_lo, _T_536) @[el2_lsu_bus_buffer.scala 207:48] + node _T_538 = bits(ldst_byteen_lo_m, 2, 2) @[el2_lsu_bus_buffer.scala 207:83] + node _T_539 = and(_T_537, _T_538) @[el2_lsu_bus_buffer.scala 207:65] + ld_byte_ibuf_hit_lo <= _T_539 @[el2_lsu_bus_buffer.scala 207:25] + node _T_540 = bits(ibuf_byteen, 2, 2) @[el2_lsu_bus_buffer.scala 208:61] + node _T_541 = and(ld_addr_ibuf_hit_hi, _T_540) @[el2_lsu_bus_buffer.scala 208:48] + node _T_542 = bits(ldst_byteen_hi_m, 2, 2) @[el2_lsu_bus_buffer.scala 208:83] + node _T_543 = and(_T_541, _T_542) @[el2_lsu_bus_buffer.scala 208:65] + ld_byte_ibuf_hit_hi <= _T_543 @[el2_lsu_bus_buffer.scala 208:25] + node _T_544 = bits(ibuf_byteen, 3, 3) @[el2_lsu_bus_buffer.scala 207:61] + node _T_545 = and(ld_addr_ibuf_hit_lo, _T_544) @[el2_lsu_bus_buffer.scala 207:48] + node _T_546 = bits(ldst_byteen_lo_m, 3, 3) @[el2_lsu_bus_buffer.scala 207:83] + node _T_547 = and(_T_545, _T_546) @[el2_lsu_bus_buffer.scala 207:65] + ld_byte_ibuf_hit_lo <= _T_547 @[el2_lsu_bus_buffer.scala 207:25] + node _T_548 = bits(ibuf_byteen, 3, 3) @[el2_lsu_bus_buffer.scala 208:61] + node _T_549 = and(ld_addr_ibuf_hit_hi, _T_548) @[el2_lsu_bus_buffer.scala 208:48] + node _T_550 = bits(ldst_byteen_hi_m, 3, 3) @[el2_lsu_bus_buffer.scala 208:83] + node _T_551 = and(_T_549, _T_550) @[el2_lsu_bus_buffer.scala 208:65] + ld_byte_ibuf_hit_hi <= _T_551 @[el2_lsu_bus_buffer.scala 208:25] + wire buf_data : UInt<32>[4] @[el2_lsu_bus_buffer.scala 210:22] + buf_data[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 211:12] + buf_data[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 211:12] + buf_data[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 211:12] + buf_data[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 211:12] + wire fwd_data : UInt<32> + fwd_data <= UInt<1>("h00") + node _T_552 = bits(ld_byte_hitvecfn_lo[3], 0, 0) @[el2_lsu_bus_buffer.scala 214:86] + node _T_553 = bits(_T_552, 0, 0) @[Bitwise.scala 72:15] + node _T_554 = mux(_T_553, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_555 = bits(buf_data[0], 31, 23) @[el2_lsu_bus_buffer.scala 214:104] + node _T_556 = and(_T_554, _T_555) @[el2_lsu_bus_buffer.scala 214:91] + node _T_557 = bits(ld_byte_hitvecfn_lo[3], 1, 1) @[el2_lsu_bus_buffer.scala 214:86] + node _T_558 = bits(_T_557, 0, 0) @[Bitwise.scala 72:15] + node _T_559 = mux(_T_558, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_560 = bits(buf_data[1], 31, 23) @[el2_lsu_bus_buffer.scala 214:104] + node _T_561 = and(_T_559, _T_560) @[el2_lsu_bus_buffer.scala 214:91] + node _T_562 = bits(ld_byte_hitvecfn_lo[3], 2, 2) @[el2_lsu_bus_buffer.scala 214:86] + node _T_563 = bits(_T_562, 0, 0) @[Bitwise.scala 72:15] + node _T_564 = mux(_T_563, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_565 = bits(buf_data[2], 31, 23) @[el2_lsu_bus_buffer.scala 214:104] + node _T_566 = and(_T_564, _T_565) @[el2_lsu_bus_buffer.scala 214:91] + node _T_567 = bits(ld_byte_hitvecfn_lo[3], 3, 3) @[el2_lsu_bus_buffer.scala 214:86] + node _T_568 = bits(_T_567, 0, 0) @[Bitwise.scala 72:15] + node _T_569 = mux(_T_568, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_570 = bits(buf_data[3], 31, 23) @[el2_lsu_bus_buffer.scala 214:104] + node _T_571 = and(_T_569, _T_570) @[el2_lsu_bus_buffer.scala 214:91] + node _T_572 = or(_T_556, _T_561) @[el2_lsu_bus_buffer.scala 214:123] + node _T_573 = or(_T_572, _T_566) @[el2_lsu_bus_buffer.scala 214:123] + node _T_574 = or(_T_573, _T_571) @[el2_lsu_bus_buffer.scala 214:123] + node _T_575 = bits(ld_byte_hitvecfn_lo[2], 0, 0) @[el2_lsu_bus_buffer.scala 215:60] + node _T_576 = bits(_T_575, 0, 0) @[Bitwise.scala 72:15] + node _T_577 = mux(_T_576, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_578 = bits(buf_data[0], 23, 16) @[el2_lsu_bus_buffer.scala 215:78] + node _T_579 = and(_T_577, _T_578) @[el2_lsu_bus_buffer.scala 215:65] + node _T_580 = bits(ld_byte_hitvecfn_lo[2], 1, 1) @[el2_lsu_bus_buffer.scala 215:60] + node _T_581 = bits(_T_580, 0, 0) @[Bitwise.scala 72:15] + node _T_582 = mux(_T_581, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_583 = bits(buf_data[1], 23, 16) @[el2_lsu_bus_buffer.scala 215:78] + node _T_584 = and(_T_582, _T_583) @[el2_lsu_bus_buffer.scala 215:65] + node _T_585 = bits(ld_byte_hitvecfn_lo[2], 2, 2) @[el2_lsu_bus_buffer.scala 215:60] + node _T_586 = bits(_T_585, 0, 0) @[Bitwise.scala 72:15] + node _T_587 = mux(_T_586, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_588 = bits(buf_data[2], 23, 16) @[el2_lsu_bus_buffer.scala 215:78] + node _T_589 = and(_T_587, _T_588) @[el2_lsu_bus_buffer.scala 215:65] + node _T_590 = bits(ld_byte_hitvecfn_lo[2], 3, 3) @[el2_lsu_bus_buffer.scala 215:60] + node _T_591 = bits(_T_590, 0, 0) @[Bitwise.scala 72:15] + node _T_592 = mux(_T_591, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_593 = bits(buf_data[3], 23, 16) @[el2_lsu_bus_buffer.scala 215:78] + node _T_594 = and(_T_592, _T_593) @[el2_lsu_bus_buffer.scala 215:65] + node _T_595 = or(_T_579, _T_584) @[el2_lsu_bus_buffer.scala 215:97] + node _T_596 = or(_T_595, _T_589) @[el2_lsu_bus_buffer.scala 215:97] + node _T_597 = or(_T_596, _T_594) @[el2_lsu_bus_buffer.scala 215:97] + node _T_598 = bits(ld_byte_hitvecfn_lo[1], 0, 0) @[el2_lsu_bus_buffer.scala 216:60] + node _T_599 = bits(_T_598, 0, 0) @[Bitwise.scala 72:15] + node _T_600 = mux(_T_599, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_601 = bits(buf_data[0], 15, 8) @[el2_lsu_bus_buffer.scala 216:78] + node _T_602 = and(_T_600, _T_601) @[el2_lsu_bus_buffer.scala 216:65] + node _T_603 = bits(ld_byte_hitvecfn_lo[1], 1, 1) @[el2_lsu_bus_buffer.scala 216:60] + node _T_604 = bits(_T_603, 0, 0) @[Bitwise.scala 72:15] + node _T_605 = mux(_T_604, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_606 = bits(buf_data[1], 15, 8) @[el2_lsu_bus_buffer.scala 216:78] + node _T_607 = and(_T_605, _T_606) @[el2_lsu_bus_buffer.scala 216:65] + node _T_608 = bits(ld_byte_hitvecfn_lo[1], 2, 2) @[el2_lsu_bus_buffer.scala 216:60] + node _T_609 = bits(_T_608, 0, 0) @[Bitwise.scala 72:15] + node _T_610 = mux(_T_609, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_611 = bits(buf_data[2], 15, 8) @[el2_lsu_bus_buffer.scala 216:78] + node _T_612 = and(_T_610, _T_611) @[el2_lsu_bus_buffer.scala 216:65] + node _T_613 = bits(ld_byte_hitvecfn_lo[1], 3, 3) @[el2_lsu_bus_buffer.scala 216:60] + node _T_614 = bits(_T_613, 0, 0) @[Bitwise.scala 72:15] + node _T_615 = mux(_T_614, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_616 = bits(buf_data[3], 15, 8) @[el2_lsu_bus_buffer.scala 216:78] + node _T_617 = and(_T_615, _T_616) @[el2_lsu_bus_buffer.scala 216:65] + node _T_618 = or(_T_602, _T_607) @[el2_lsu_bus_buffer.scala 216:96] + node _T_619 = or(_T_618, _T_612) @[el2_lsu_bus_buffer.scala 216:96] + node _T_620 = or(_T_619, _T_617) @[el2_lsu_bus_buffer.scala 216:96] + node _T_621 = bits(ld_byte_hitvecfn_lo[0], 0, 0) @[el2_lsu_bus_buffer.scala 217:60] + node _T_622 = bits(_T_621, 0, 0) @[Bitwise.scala 72:15] + node _T_623 = mux(_T_622, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_624 = bits(buf_data[0], 7, 0) @[el2_lsu_bus_buffer.scala 217:78] + node _T_625 = and(_T_623, _T_624) @[el2_lsu_bus_buffer.scala 217:65] + node _T_626 = bits(ld_byte_hitvecfn_lo[0], 1, 1) @[el2_lsu_bus_buffer.scala 217:60] + node _T_627 = bits(_T_626, 0, 0) @[Bitwise.scala 72:15] + node _T_628 = mux(_T_627, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_629 = bits(buf_data[1], 7, 0) @[el2_lsu_bus_buffer.scala 217:78] + node _T_630 = and(_T_628, _T_629) @[el2_lsu_bus_buffer.scala 217:65] + node _T_631 = bits(ld_byte_hitvecfn_lo[0], 2, 2) @[el2_lsu_bus_buffer.scala 217:60] + node _T_632 = bits(_T_631, 0, 0) @[Bitwise.scala 72:15] + node _T_633 = mux(_T_632, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_634 = bits(buf_data[2], 7, 0) @[el2_lsu_bus_buffer.scala 217:78] + node _T_635 = and(_T_633, _T_634) @[el2_lsu_bus_buffer.scala 217:65] + node _T_636 = bits(ld_byte_hitvecfn_lo[0], 3, 3) @[el2_lsu_bus_buffer.scala 217:60] + node _T_637 = bits(_T_636, 0, 0) @[Bitwise.scala 72:15] + node _T_638 = mux(_T_637, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_639 = bits(buf_data[3], 7, 0) @[el2_lsu_bus_buffer.scala 217:78] + node _T_640 = and(_T_638, _T_639) @[el2_lsu_bus_buffer.scala 217:65] + node _T_641 = or(_T_625, _T_630) @[el2_lsu_bus_buffer.scala 217:95] + node _T_642 = or(_T_641, _T_635) @[el2_lsu_bus_buffer.scala 217:95] + node _T_643 = or(_T_642, _T_640) @[el2_lsu_bus_buffer.scala 217:95] + node _T_644 = cat(_T_620, _T_643) @[Cat.scala 29:58] + node _T_645 = cat(_T_574, _T_597) @[Cat.scala 29:58] + node _T_646 = cat(_T_645, _T_644) @[Cat.scala 29:58] + io.ld_fwddata_buf_lo <= _T_646 @[el2_lsu_bus_buffer.scala 214:24] + node _T_647 = bits(ld_byte_hitvecfn_hi[3], 0, 0) @[el2_lsu_bus_buffer.scala 219:86] + node _T_648 = bits(_T_647, 0, 0) @[Bitwise.scala 72:15] + node _T_649 = mux(_T_648, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_650 = bits(buf_data[0], 31, 23) @[el2_lsu_bus_buffer.scala 219:104] + node _T_651 = and(_T_649, _T_650) @[el2_lsu_bus_buffer.scala 219:91] + node _T_652 = bits(ld_byte_hitvecfn_hi[3], 1, 1) @[el2_lsu_bus_buffer.scala 219:86] + node _T_653 = bits(_T_652, 0, 0) @[Bitwise.scala 72:15] + node _T_654 = mux(_T_653, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_655 = bits(buf_data[1], 31, 23) @[el2_lsu_bus_buffer.scala 219:104] + node _T_656 = and(_T_654, _T_655) @[el2_lsu_bus_buffer.scala 219:91] + node _T_657 = bits(ld_byte_hitvecfn_hi[3], 2, 2) @[el2_lsu_bus_buffer.scala 219:86] + node _T_658 = bits(_T_657, 0, 0) @[Bitwise.scala 72:15] + node _T_659 = mux(_T_658, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_660 = bits(buf_data[2], 31, 23) @[el2_lsu_bus_buffer.scala 219:104] + node _T_661 = and(_T_659, _T_660) @[el2_lsu_bus_buffer.scala 219:91] + node _T_662 = bits(ld_byte_hitvecfn_hi[3], 3, 3) @[el2_lsu_bus_buffer.scala 219:86] + node _T_663 = bits(_T_662, 0, 0) @[Bitwise.scala 72:15] + node _T_664 = mux(_T_663, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_665 = bits(buf_data[3], 31, 23) @[el2_lsu_bus_buffer.scala 219:104] + node _T_666 = and(_T_664, _T_665) @[el2_lsu_bus_buffer.scala 219:91] + node _T_667 = or(_T_651, _T_656) @[el2_lsu_bus_buffer.scala 219:123] + node _T_668 = or(_T_667, _T_661) @[el2_lsu_bus_buffer.scala 219:123] + node _T_669 = or(_T_668, _T_666) @[el2_lsu_bus_buffer.scala 219:123] + node _T_670 = bits(ld_byte_hitvecfn_hi[2], 0, 0) @[el2_lsu_bus_buffer.scala 220:60] + node _T_671 = bits(_T_670, 0, 0) @[Bitwise.scala 72:15] + node _T_672 = mux(_T_671, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_673 = bits(buf_data[0], 23, 16) @[el2_lsu_bus_buffer.scala 220:78] + node _T_674 = and(_T_672, _T_673) @[el2_lsu_bus_buffer.scala 220:65] + node _T_675 = bits(ld_byte_hitvecfn_hi[2], 1, 1) @[el2_lsu_bus_buffer.scala 220:60] + node _T_676 = bits(_T_675, 0, 0) @[Bitwise.scala 72:15] + node _T_677 = mux(_T_676, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_678 = bits(buf_data[1], 23, 16) @[el2_lsu_bus_buffer.scala 220:78] + node _T_679 = and(_T_677, _T_678) @[el2_lsu_bus_buffer.scala 220:65] + node _T_680 = bits(ld_byte_hitvecfn_hi[2], 2, 2) @[el2_lsu_bus_buffer.scala 220:60] + node _T_681 = bits(_T_680, 0, 0) @[Bitwise.scala 72:15] + node _T_682 = mux(_T_681, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_683 = bits(buf_data[2], 23, 16) @[el2_lsu_bus_buffer.scala 220:78] + node _T_684 = and(_T_682, _T_683) @[el2_lsu_bus_buffer.scala 220:65] + node _T_685 = bits(ld_byte_hitvecfn_hi[2], 3, 3) @[el2_lsu_bus_buffer.scala 220:60] + node _T_686 = bits(_T_685, 0, 0) @[Bitwise.scala 72:15] + node _T_687 = mux(_T_686, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_688 = bits(buf_data[3], 23, 16) @[el2_lsu_bus_buffer.scala 220:78] + node _T_689 = and(_T_687, _T_688) @[el2_lsu_bus_buffer.scala 220:65] + node _T_690 = or(_T_674, _T_679) @[el2_lsu_bus_buffer.scala 220:97] + node _T_691 = or(_T_690, _T_684) @[el2_lsu_bus_buffer.scala 220:97] + node _T_692 = or(_T_691, _T_689) @[el2_lsu_bus_buffer.scala 220:97] + node _T_693 = bits(ld_byte_hitvecfn_hi[1], 0, 0) @[el2_lsu_bus_buffer.scala 221:60] + node _T_694 = bits(_T_693, 0, 0) @[Bitwise.scala 72:15] + node _T_695 = mux(_T_694, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_696 = bits(buf_data[0], 15, 8) @[el2_lsu_bus_buffer.scala 221:78] + node _T_697 = and(_T_695, _T_696) @[el2_lsu_bus_buffer.scala 221:65] + node _T_698 = bits(ld_byte_hitvecfn_hi[1], 1, 1) @[el2_lsu_bus_buffer.scala 221:60] + node _T_699 = bits(_T_698, 0, 0) @[Bitwise.scala 72:15] + node _T_700 = mux(_T_699, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_701 = bits(buf_data[1], 15, 8) @[el2_lsu_bus_buffer.scala 221:78] + node _T_702 = and(_T_700, _T_701) @[el2_lsu_bus_buffer.scala 221:65] + node _T_703 = bits(ld_byte_hitvecfn_hi[1], 2, 2) @[el2_lsu_bus_buffer.scala 221:60] + node _T_704 = bits(_T_703, 0, 0) @[Bitwise.scala 72:15] + node _T_705 = mux(_T_704, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_706 = bits(buf_data[2], 15, 8) @[el2_lsu_bus_buffer.scala 221:78] + node _T_707 = and(_T_705, _T_706) @[el2_lsu_bus_buffer.scala 221:65] + node _T_708 = bits(ld_byte_hitvecfn_hi[1], 3, 3) @[el2_lsu_bus_buffer.scala 221:60] + node _T_709 = bits(_T_708, 0, 0) @[Bitwise.scala 72:15] + node _T_710 = mux(_T_709, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_711 = bits(buf_data[3], 15, 8) @[el2_lsu_bus_buffer.scala 221:78] + node _T_712 = and(_T_710, _T_711) @[el2_lsu_bus_buffer.scala 221:65] + node _T_713 = or(_T_697, _T_702) @[el2_lsu_bus_buffer.scala 221:96] + node _T_714 = or(_T_713, _T_707) @[el2_lsu_bus_buffer.scala 221:96] + node _T_715 = or(_T_714, _T_712) @[el2_lsu_bus_buffer.scala 221:96] + node _T_716 = bits(ld_byte_hitvecfn_hi[0], 0, 0) @[el2_lsu_bus_buffer.scala 222:60] + node _T_717 = bits(_T_716, 0, 0) @[Bitwise.scala 72:15] + node _T_718 = mux(_T_717, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_719 = bits(buf_data[0], 7, 0) @[el2_lsu_bus_buffer.scala 222:78] + node _T_720 = and(_T_718, _T_719) @[el2_lsu_bus_buffer.scala 222:65] + node _T_721 = bits(ld_byte_hitvecfn_hi[0], 1, 1) @[el2_lsu_bus_buffer.scala 222:60] + node _T_722 = bits(_T_721, 0, 0) @[Bitwise.scala 72:15] + node _T_723 = mux(_T_722, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_724 = bits(buf_data[1], 7, 0) @[el2_lsu_bus_buffer.scala 222:78] + node _T_725 = and(_T_723, _T_724) @[el2_lsu_bus_buffer.scala 222:65] + node _T_726 = bits(ld_byte_hitvecfn_hi[0], 2, 2) @[el2_lsu_bus_buffer.scala 222:60] + node _T_727 = bits(_T_726, 0, 0) @[Bitwise.scala 72:15] + node _T_728 = mux(_T_727, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_729 = bits(buf_data[2], 7, 0) @[el2_lsu_bus_buffer.scala 222:78] + node _T_730 = and(_T_728, _T_729) @[el2_lsu_bus_buffer.scala 222:65] + node _T_731 = bits(ld_byte_hitvecfn_hi[0], 3, 3) @[el2_lsu_bus_buffer.scala 222:60] + node _T_732 = bits(_T_731, 0, 0) @[Bitwise.scala 72:15] + node _T_733 = mux(_T_732, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_734 = bits(buf_data[3], 7, 0) @[el2_lsu_bus_buffer.scala 222:78] + node _T_735 = and(_T_733, _T_734) @[el2_lsu_bus_buffer.scala 222:65] + node _T_736 = or(_T_720, _T_725) @[el2_lsu_bus_buffer.scala 222:95] + node _T_737 = or(_T_736, _T_730) @[el2_lsu_bus_buffer.scala 222:95] + node _T_738 = or(_T_737, _T_735) @[el2_lsu_bus_buffer.scala 222:95] + node _T_739 = cat(_T_715, _T_738) @[Cat.scala 29:58] + node _T_740 = cat(_T_669, _T_692) @[Cat.scala 29:58] + node _T_741 = cat(_T_740, _T_739) @[Cat.scala 29:58] + io.ld_fwddata_buf_hi <= _T_741 @[el2_lsu_bus_buffer.scala 219:24] + node bus_coalescing_disable = or(io.dec_tlu_wb_coalescing_disable, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 224:65] + node _T_742 = mux(io.lsu_pkt_r.by, UInt<4>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_743 = mux(io.lsu_pkt_r.half, UInt<4>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_744 = mux(io.lsu_pkt_r.word, UInt<4>("h0f"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_745 = or(_T_742, _T_743) @[Mux.scala 27:72] + node _T_746 = or(_T_745, _T_744) @[Mux.scala 27:72] + wire ldst_byteen_r : UInt<4> @[Mux.scala 27:72] + ldst_byteen_r <= _T_746 @[Mux.scala 27:72] + node _T_747 = cat(UInt<4>("h00"), ldst_byteen_r) @[Cat.scala 29:58] + node _T_748 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 228:61] + node byteen = dshl(_T_747, _T_748) @[el2_lsu_bus_buffer.scala 228:45] + node ldst_byteen_hi_r = bits(byteen, 7, 4) @[el2_lsu_bus_buffer.scala 229:32] + node ldst_byteen_lo_r = bits(byteen, 3, 0) @[el2_lsu_bus_buffer.scala 230:32] + node _T_749 = cat(UInt<32>("h00"), io.store_data_r) @[Cat.scala 29:58] + node _T_750 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 231:73] + node _T_751 = mul(UInt<4>("h08"), _T_750) @[el2_lsu_bus_buffer.scala 231:58] + node store_data = dshl(_T_749, _T_751) @[el2_lsu_bus_buffer.scala 231:52] + node store_data_hi_r = bits(store_data, 63, 32) @[el2_lsu_bus_buffer.scala 232:35] + node store_data_lo_r = bits(store_data, 31, 0) @[el2_lsu_bus_buffer.scala 233:35] + node _T_752 = bits(io.lsu_addr_r, 3, 3) @[el2_lsu_bus_buffer.scala 234:36] + node _T_753 = bits(io.end_addr_r, 3, 3) @[el2_lsu_bus_buffer.scala 234:57] + node ldst_samedw_r = eq(_T_752, _T_753) @[el2_lsu_bus_buffer.scala 234:40] + node _T_754 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 235:67] + node _T_755 = eq(_T_754, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 235:74] + node _T_756 = bits(io.lsu_addr_r, 0, 0) @[el2_lsu_bus_buffer.scala 236:40] + node _T_757 = eq(_T_756, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 236:26] + node _T_758 = mux(io.lsu_pkt_r.word, _T_755, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_759 = mux(io.lsu_pkt_r.half, _T_757, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_760 = mux(io.lsu_pkt_r.by, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_761 = or(_T_758, _T_759) @[Mux.scala 27:72] + node _T_762 = or(_T_761, _T_760) @[Mux.scala 27:72] + wire is_aligned_r : UInt<1> @[Mux.scala 27:72] + is_aligned_r <= _T_762 @[Mux.scala 27:72] + node _T_763 = or(io.lsu_pkt_r.load, io.no_word_merge_r) @[el2_lsu_bus_buffer.scala 238:55] + node _T_764 = and(io.lsu_busreq_r, _T_763) @[el2_lsu_bus_buffer.scala 238:34] + node _T_765 = eq(ibuf_valid, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 238:79] + node ibuf_byp = and(_T_764, _T_765) @[el2_lsu_bus_buffer.scala 238:77] + node _T_766 = and(io.lsu_busreq_r, io.lsu_commit_r) @[el2_lsu_bus_buffer.scala 239:36] + node _T_767 = eq(ibuf_byp, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 239:56] + node ibuf_wr_en = and(_T_766, _T_767) @[el2_lsu_bus_buffer.scala 239:54] + wire ibuf_drain_vld : UInt<1> + ibuf_drain_vld <= UInt<1>("h00") + node _T_768 = eq(ibuf_wr_en, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 241:36] + node _T_769 = and(ibuf_drain_vld, _T_768) @[el2_lsu_bus_buffer.scala 241:34] + node ibuf_rst = or(_T_769, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 241:49] + node _T_770 = eq(io.lsu_busreq_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 242:44] + node _T_771 = and(io.lsu_busreq_m, _T_770) @[el2_lsu_bus_buffer.scala 242:42] + node _T_772 = and(_T_771, ibuf_valid) @[el2_lsu_bus_buffer.scala 242:61] + node _T_773 = bits(ibuf_addr, 31, 2) @[el2_lsu_bus_buffer.scala 242:107] + node _T_774 = bits(io.lsu_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 242:132] + node _T_775 = neq(_T_773, _T_774) @[el2_lsu_bus_buffer.scala 242:115] + node _T_776 = or(io.lsu_pkt_m.load, _T_775) @[el2_lsu_bus_buffer.scala 242:95] + node ibuf_force_drain = and(_T_772, _T_776) @[el2_lsu_bus_buffer.scala 242:74] + wire ibuf_sideeffect : UInt<1> + ibuf_sideeffect <= UInt<1>("h00") + wire ibuf_timer : UInt<3> + ibuf_timer <= UInt<1>("h00") + wire ibuf_merge_en : UInt<1> + ibuf_merge_en <= UInt<1>("h00") + wire ibuf_merge_in : UInt<1> + ibuf_merge_in <= UInt<1>("h00") + node _T_777 = eq(ibuf_timer, UInt<3>("h07")) @[el2_lsu_bus_buffer.scala 247:62] + node _T_778 = or(ibuf_wr_en, _T_777) @[el2_lsu_bus_buffer.scala 247:48] + node _T_779 = and(ibuf_merge_en, ibuf_merge_in) @[el2_lsu_bus_buffer.scala 247:98] + node _T_780 = eq(_T_779, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 247:82] + node _T_781 = and(_T_778, _T_780) @[el2_lsu_bus_buffer.scala 247:80] + node _T_782 = or(_T_781, ibuf_byp) @[el2_lsu_bus_buffer.scala 248:5] + node _T_783 = or(_T_782, ibuf_force_drain) @[el2_lsu_bus_buffer.scala 248:16] + node _T_784 = or(_T_783, ibuf_sideeffect) @[el2_lsu_bus_buffer.scala 248:35] + node _T_785 = eq(ibuf_write, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 248:55] + node _T_786 = or(_T_784, _T_785) @[el2_lsu_bus_buffer.scala 248:53] + node _T_787 = or(_T_786, bus_coalescing_disable) @[el2_lsu_bus_buffer.scala 248:67] + node _T_788 = and(ibuf_valid, _T_787) @[el2_lsu_bus_buffer.scala 247:32] + ibuf_drain_vld <= _T_788 @[el2_lsu_bus_buffer.scala 247:18] + wire ibuf_tag : UInt<2> + ibuf_tag <= UInt<1>("h00") + wire WrPtr1_r : UInt<2> + WrPtr1_r <= UInt<1>("h00") + wire WrPtr0_r : UInt<2> + WrPtr0_r <= UInt<1>("h00") + node _T_789 = and(ibuf_merge_en, ibuf_merge_in) @[el2_lsu_bus_buffer.scala 253:39] + node _T_790 = mux(io.ldst_dual_r, WrPtr1_r, WrPtr0_r) @[el2_lsu_bus_buffer.scala 253:69] + node ibuf_tag_in = mux(_T_789, ibuf_tag, _T_790) @[el2_lsu_bus_buffer.scala 253:24] + node ibuf_sz_in = cat(io.lsu_pkt_r.word, io.lsu_pkt_r.half) @[Cat.scala 29:58] + node ibuf_addr_in = mux(io.ldst_dual_r, io.end_addr_r, io.lsu_addr_r) @[el2_lsu_bus_buffer.scala 256:25] + node _T_791 = and(ibuf_merge_en, ibuf_merge_in) @[el2_lsu_bus_buffer.scala 257:42] + node _T_792 = bits(ibuf_byteen, 3, 0) @[el2_lsu_bus_buffer.scala 257:70] + node _T_793 = bits(ldst_byteen_lo_r, 3, 0) @[el2_lsu_bus_buffer.scala 257:95] + node _T_794 = or(_T_792, _T_793) @[el2_lsu_bus_buffer.scala 257:77] + node _T_795 = bits(ldst_byteen_hi_r, 3, 0) @[el2_lsu_bus_buffer.scala 258:41] + node _T_796 = bits(ldst_byteen_lo_r, 3, 0) @[el2_lsu_bus_buffer.scala 258:65] + node _T_797 = mux(io.ldst_dual_r, _T_795, _T_796) @[el2_lsu_bus_buffer.scala 258:8] + node ibuf_byteen_in = mux(_T_791, _T_794, _T_797) @[el2_lsu_bus_buffer.scala 257:27] + wire ibuf_data : UInt<32> + ibuf_data <= UInt<1>("h00") + node _T_798 = and(ibuf_merge_en, ibuf_merge_in) @[el2_lsu_bus_buffer.scala 261:61] + node _T_799 = bits(ldst_byteen_lo_r, 0, 0) @[el2_lsu_bus_buffer.scala 262:25] + node _T_800 = bits(store_data_lo_r, 7, 0) @[el2_lsu_bus_buffer.scala 262:45] + node _T_801 = bits(ibuf_data, 7, 0) @[el2_lsu_bus_buffer.scala 262:76] + node _T_802 = mux(_T_799, _T_800, _T_801) @[el2_lsu_bus_buffer.scala 262:8] + node _T_803 = bits(ibuf_data, 7, 0) @[el2_lsu_bus_buffer.scala 262:108] + node _T_804 = mux(_T_798, _T_802, _T_803) @[el2_lsu_bus_buffer.scala 261:46] + node _T_805 = and(ibuf_merge_en, ibuf_merge_in) @[el2_lsu_bus_buffer.scala 261:61] + node _T_806 = bits(ldst_byteen_lo_r, 1, 1) @[el2_lsu_bus_buffer.scala 262:25] + node _T_807 = bits(store_data_lo_r, 15, 8) @[el2_lsu_bus_buffer.scala 262:45] + node _T_808 = bits(ibuf_data, 15, 8) @[el2_lsu_bus_buffer.scala 262:76] + node _T_809 = mux(_T_806, _T_807, _T_808) @[el2_lsu_bus_buffer.scala 262:8] + node _T_810 = bits(ibuf_data, 15, 8) @[el2_lsu_bus_buffer.scala 262:108] + node _T_811 = mux(_T_805, _T_809, _T_810) @[el2_lsu_bus_buffer.scala 261:46] + node _T_812 = and(ibuf_merge_en, ibuf_merge_in) @[el2_lsu_bus_buffer.scala 261:61] + node _T_813 = bits(ldst_byteen_lo_r, 2, 2) @[el2_lsu_bus_buffer.scala 262:25] + node _T_814 = bits(store_data_lo_r, 23, 16) @[el2_lsu_bus_buffer.scala 262:45] + node _T_815 = bits(ibuf_data, 23, 16) @[el2_lsu_bus_buffer.scala 262:76] + node _T_816 = mux(_T_813, _T_814, _T_815) @[el2_lsu_bus_buffer.scala 262:8] + node _T_817 = bits(ibuf_data, 23, 16) @[el2_lsu_bus_buffer.scala 262:108] + node _T_818 = mux(_T_812, _T_816, _T_817) @[el2_lsu_bus_buffer.scala 261:46] + node _T_819 = and(ibuf_merge_en, ibuf_merge_in) @[el2_lsu_bus_buffer.scala 261:61] + node _T_820 = bits(ldst_byteen_lo_r, 3, 3) @[el2_lsu_bus_buffer.scala 262:25] + node _T_821 = bits(store_data_lo_r, 31, 24) @[el2_lsu_bus_buffer.scala 262:45] + node _T_822 = bits(ibuf_data, 31, 24) @[el2_lsu_bus_buffer.scala 262:76] + node _T_823 = mux(_T_820, _T_821, _T_822) @[el2_lsu_bus_buffer.scala 262:8] + node _T_824 = bits(ibuf_data, 31, 24) @[el2_lsu_bus_buffer.scala 262:108] + node _T_825 = mux(_T_819, _T_823, _T_824) @[el2_lsu_bus_buffer.scala 261:46] + node _T_826 = cat(_T_825, _T_818) @[Cat.scala 29:58] + node _T_827 = cat(_T_826, _T_811) @[Cat.scala 29:58] + node ibuf_data_in = cat(_T_827, _T_804) @[Cat.scala 29:58] + node _T_828 = lt(ibuf_timer, UInt<3>("h07")) @[el2_lsu_bus_buffer.scala 263:59] + node _T_829 = bits(_T_828, 0, 0) @[el2_lsu_bus_buffer.scala 263:79] + node _T_830 = add(ibuf_timer, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 263:93] + node _T_831 = tail(_T_830, 1) @[el2_lsu_bus_buffer.scala 263:93] + node _T_832 = mux(_T_829, _T_831, ibuf_timer) @[el2_lsu_bus_buffer.scala 263:47] + node ibuf_timer_in = mux(ibuf_wr_en, UInt<1>("h00"), _T_832) @[el2_lsu_bus_buffer.scala 263:26] + node _T_833 = and(io.lsu_busreq_r, io.lsu_commit_r) @[el2_lsu_bus_buffer.scala 265:36] + node _T_834 = and(_T_833, io.lsu_pkt_r.store) @[el2_lsu_bus_buffer.scala 265:54] + node _T_835 = and(_T_834, ibuf_valid) @[el2_lsu_bus_buffer.scala 265:75] + node _T_836 = and(_T_835, ibuf_write) @[el2_lsu_bus_buffer.scala 265:88] + node _T_837 = bits(io.lsu_addr_r, 31, 2) @[el2_lsu_bus_buffer.scala 265:117] + node _T_838 = bits(ibuf_addr, 31, 2) @[el2_lsu_bus_buffer.scala 265:137] + node _T_839 = eq(_T_837, _T_838) @[el2_lsu_bus_buffer.scala 265:124] + node _T_840 = and(_T_836, _T_839) @[el2_lsu_bus_buffer.scala 265:101] + node _T_841 = eq(io.is_sideeffects_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 265:147] + node _T_842 = and(_T_840, _T_841) @[el2_lsu_bus_buffer.scala 265:145] + node _T_843 = eq(bus_coalescing_disable, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 265:170] + node _T_844 = and(_T_842, _T_843) @[el2_lsu_bus_buffer.scala 265:168] + ibuf_merge_en <= _T_844 @[el2_lsu_bus_buffer.scala 265:17] + node _T_845 = eq(io.ldst_dual_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 266:20] + ibuf_merge_in <= _T_845 @[el2_lsu_bus_buffer.scala 266:17] + node _T_846 = eq(ibuf_merge_in, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 267:65] + node _T_847 = and(ibuf_merge_en, _T_846) @[el2_lsu_bus_buffer.scala 267:63] + node _T_848 = bits(ibuf_byteen, 0, 0) @[el2_lsu_bus_buffer.scala 267:92] + node _T_849 = bits(ldst_byteen_lo_r, 0, 0) @[el2_lsu_bus_buffer.scala 267:114] + node _T_850 = or(_T_848, _T_849) @[el2_lsu_bus_buffer.scala 267:96] + node _T_851 = bits(ibuf_byteen, 0, 0) @[el2_lsu_bus_buffer.scala 267:130] + node _T_852 = mux(_T_847, _T_850, _T_851) @[el2_lsu_bus_buffer.scala 267:48] + node _T_853 = eq(ibuf_merge_in, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 267:65] + node _T_854 = and(ibuf_merge_en, _T_853) @[el2_lsu_bus_buffer.scala 267:63] + node _T_855 = bits(ibuf_byteen, 1, 1) @[el2_lsu_bus_buffer.scala 267:92] + node _T_856 = bits(ldst_byteen_lo_r, 1, 1) @[el2_lsu_bus_buffer.scala 267:114] + node _T_857 = or(_T_855, _T_856) @[el2_lsu_bus_buffer.scala 267:96] + node _T_858 = bits(ibuf_byteen, 1, 1) @[el2_lsu_bus_buffer.scala 267:130] + node _T_859 = mux(_T_854, _T_857, _T_858) @[el2_lsu_bus_buffer.scala 267:48] + node _T_860 = eq(ibuf_merge_in, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 267:65] + node _T_861 = and(ibuf_merge_en, _T_860) @[el2_lsu_bus_buffer.scala 267:63] + node _T_862 = bits(ibuf_byteen, 2, 2) @[el2_lsu_bus_buffer.scala 267:92] + node _T_863 = bits(ldst_byteen_lo_r, 2, 2) @[el2_lsu_bus_buffer.scala 267:114] + node _T_864 = or(_T_862, _T_863) @[el2_lsu_bus_buffer.scala 267:96] + node _T_865 = bits(ibuf_byteen, 2, 2) @[el2_lsu_bus_buffer.scala 267:130] + node _T_866 = mux(_T_861, _T_864, _T_865) @[el2_lsu_bus_buffer.scala 267:48] + node _T_867 = eq(ibuf_merge_in, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 267:65] + node _T_868 = and(ibuf_merge_en, _T_867) @[el2_lsu_bus_buffer.scala 267:63] + node _T_869 = bits(ibuf_byteen, 3, 3) @[el2_lsu_bus_buffer.scala 267:92] + node _T_870 = bits(ldst_byteen_lo_r, 3, 3) @[el2_lsu_bus_buffer.scala 267:114] + node _T_871 = or(_T_869, _T_870) @[el2_lsu_bus_buffer.scala 267:96] + node _T_872 = bits(ibuf_byteen, 3, 3) @[el2_lsu_bus_buffer.scala 267:130] + node _T_873 = mux(_T_868, _T_871, _T_872) @[el2_lsu_bus_buffer.scala 267:48] + node _T_874 = cat(_T_873, _T_866) @[Cat.scala 29:58] + node _T_875 = cat(_T_874, _T_859) @[Cat.scala 29:58] + node ibuf_byteen_out = cat(_T_875, _T_852) @[Cat.scala 29:58] + node _T_876 = eq(ibuf_merge_in, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 268:62] + node _T_877 = and(ibuf_merge_en, _T_876) @[el2_lsu_bus_buffer.scala 268:60] + node _T_878 = bits(ldst_byteen_lo_r, 0, 0) @[el2_lsu_bus_buffer.scala 268:98] + node _T_879 = bits(store_data_lo_r, 7, 0) @[el2_lsu_bus_buffer.scala 268:118] + node _T_880 = bits(ibuf_data, 7, 0) @[el2_lsu_bus_buffer.scala 268:143] + node _T_881 = mux(_T_878, _T_879, _T_880) @[el2_lsu_bus_buffer.scala 268:81] + node _T_882 = bits(ibuf_data, 7, 0) @[el2_lsu_bus_buffer.scala 268:169] + node _T_883 = mux(_T_877, _T_881, _T_882) @[el2_lsu_bus_buffer.scala 268:45] + node _T_884 = eq(ibuf_merge_in, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 268:62] + node _T_885 = and(ibuf_merge_en, _T_884) @[el2_lsu_bus_buffer.scala 268:60] + node _T_886 = bits(ldst_byteen_lo_r, 1, 1) @[el2_lsu_bus_buffer.scala 268:98] + node _T_887 = bits(store_data_lo_r, 15, 8) @[el2_lsu_bus_buffer.scala 268:118] + node _T_888 = bits(ibuf_data, 15, 8) @[el2_lsu_bus_buffer.scala 268:143] + node _T_889 = mux(_T_886, _T_887, _T_888) @[el2_lsu_bus_buffer.scala 268:81] + node _T_890 = bits(ibuf_data, 15, 8) @[el2_lsu_bus_buffer.scala 268:169] + node _T_891 = mux(_T_885, _T_889, _T_890) @[el2_lsu_bus_buffer.scala 268:45] + node _T_892 = eq(ibuf_merge_in, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 268:62] + node _T_893 = and(ibuf_merge_en, _T_892) @[el2_lsu_bus_buffer.scala 268:60] + node _T_894 = bits(ldst_byteen_lo_r, 2, 2) @[el2_lsu_bus_buffer.scala 268:98] + node _T_895 = bits(store_data_lo_r, 23, 16) @[el2_lsu_bus_buffer.scala 268:118] + node _T_896 = bits(ibuf_data, 23, 16) @[el2_lsu_bus_buffer.scala 268:143] + node _T_897 = mux(_T_894, _T_895, _T_896) @[el2_lsu_bus_buffer.scala 268:81] + node _T_898 = bits(ibuf_data, 23, 16) @[el2_lsu_bus_buffer.scala 268:169] + node _T_899 = mux(_T_893, _T_897, _T_898) @[el2_lsu_bus_buffer.scala 268:45] + node _T_900 = eq(ibuf_merge_in, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 268:62] + node _T_901 = and(ibuf_merge_en, _T_900) @[el2_lsu_bus_buffer.scala 268:60] + node _T_902 = bits(ldst_byteen_lo_r, 3, 3) @[el2_lsu_bus_buffer.scala 268:98] + node _T_903 = bits(store_data_lo_r, 31, 24) @[el2_lsu_bus_buffer.scala 268:118] + node _T_904 = bits(ibuf_data, 31, 24) @[el2_lsu_bus_buffer.scala 268:143] + node _T_905 = mux(_T_902, _T_903, _T_904) @[el2_lsu_bus_buffer.scala 268:81] + node _T_906 = bits(ibuf_data, 31, 24) @[el2_lsu_bus_buffer.scala 268:169] + node _T_907 = mux(_T_901, _T_905, _T_906) @[el2_lsu_bus_buffer.scala 268:45] + node _T_908 = cat(_T_907, _T_899) @[Cat.scala 29:58] + node _T_909 = cat(_T_908, _T_891) @[Cat.scala 29:58] + node ibuf_data_out = cat(_T_909, _T_883) @[Cat.scala 29:58] + node _T_910 = mux(ibuf_wr_en, UInt<1>("h01"), ibuf_valid) @[el2_lsu_bus_buffer.scala 270:28] + node _T_911 = and(_T_910, ibuf_rst) @[el2_lsu_bus_buffer.scala 270:61] + reg _T_912 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 270:24] + _T_912 <= _T_911 @[el2_lsu_bus_buffer.scala 270:24] + ibuf_valid <= _T_912 @[el2_lsu_bus_buffer.scala 270:14] + node _T_913 = asUInt(io.lsu_bus_ibuf_c1_clk) @[el2_lsu_bus_buffer.scala 271:120] + node _T_914 = bits(_T_913, 0, 0) @[el2_lsu_bus_buffer.scala 271:120] + node _T_915 = and(ibuf_wr_en, _T_914) @[el2_lsu_bus_buffer.scala 271:89] + reg _T_916 : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_915 : @[Reg.scala 28:19] + _T_916 <= ibuf_tag_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ibuf_tag <= _T_916 @[el2_lsu_bus_buffer.scala 271:12] + node _T_917 = asUInt(io.lsu_bus_ibuf_c1_clk) @[el2_lsu_bus_buffer.scala 272:131] + node _T_918 = bits(_T_917, 0, 0) @[el2_lsu_bus_buffer.scala 272:131] + node _T_919 = and(ibuf_wr_en, _T_918) @[el2_lsu_bus_buffer.scala 272:100] + reg ibuf_dualtag : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_919 : @[Reg.scala 28:19] + ibuf_dualtag <= WrPtr0_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_920 = asUInt(io.lsu_bus_ibuf_c1_clk) @[el2_lsu_bus_buffer.scala 273:127] + node _T_921 = bits(_T_920, 0, 0) @[el2_lsu_bus_buffer.scala 273:127] + node _T_922 = and(ibuf_wr_en, _T_921) @[el2_lsu_bus_buffer.scala 273:96] + reg ibuf_dual : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_922 : @[Reg.scala 28:19] + ibuf_dual <= io.ldst_dual_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_923 = asUInt(io.lsu_bus_ibuf_c1_clk) @[el2_lsu_bus_buffer.scala 274:128] + node _T_924 = bits(_T_923, 0, 0) @[el2_lsu_bus_buffer.scala 274:128] + node _T_925 = and(ibuf_wr_en, _T_924) @[el2_lsu_bus_buffer.scala 274:97] + reg ibuf_samedw : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_925 : @[Reg.scala 28:19] + ibuf_samedw <= ldst_samedw_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_926 = asUInt(io.lsu_bus_ibuf_c1_clk) @[el2_lsu_bus_buffer.scala 275:135] + node _T_927 = bits(_T_926, 0, 0) @[el2_lsu_bus_buffer.scala 275:135] + node _T_928 = and(ibuf_wr_en, _T_927) @[el2_lsu_bus_buffer.scala 275:104] + reg ibuf_nomerge : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_928 : @[Reg.scala 28:19] + ibuf_nomerge <= io.no_dword_merge_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_929 = asUInt(io.lsu_bus_ibuf_c1_clk) @[el2_lsu_bus_buffer.scala 276:135] + node _T_930 = bits(_T_929, 0, 0) @[el2_lsu_bus_buffer.scala 276:135] + node _T_931 = and(ibuf_wr_en, _T_930) @[el2_lsu_bus_buffer.scala 276:104] + reg _T_932 : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_931 : @[Reg.scala 28:19] + _T_932 <= io.is_sideeffects_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ibuf_sideeffect <= _T_932 @[el2_lsu_bus_buffer.scala 276:19] + node _T_933 = asUInt(io.lsu_bus_ibuf_c1_clk) @[el2_lsu_bus_buffer.scala 277:134] + node _T_934 = bits(_T_933, 0, 0) @[el2_lsu_bus_buffer.scala 277:134] + node _T_935 = and(ibuf_wr_en, _T_934) @[el2_lsu_bus_buffer.scala 277:103] + reg ibuf_unsign : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_935 : @[Reg.scala 28:19] + ibuf_unsign <= io.lsu_pkt_r.unsign @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + reg _T_936 : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + _T_936 <= io.lsu_pkt_r.store @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ibuf_write <= _T_936 @[el2_lsu_bus_buffer.scala 278:14] + reg ibuf_sz : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + ibuf_sz <= ibuf_sz_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + inst rvclkhdr of rvclkhdr @[el2_lib.scala 472:23] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[el2_lib.scala 474:18] + rvclkhdr.io.en <= ibuf_wr_en @[el2_lib.scala 475:17] + rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 476:24] + reg _T_937 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 478:16] + _T_937 <= ibuf_addr_in @[el2_lib.scala 478:16] + ibuf_addr <= _T_937 @[el2_lsu_bus_buffer.scala 280:13] + reg _T_938 : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + _T_938 <= ibuf_byteen_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ibuf_byteen <= _T_938 @[el2_lsu_bus_buffer.scala 281:15] + inst rvclkhdr_1 of rvclkhdr_1 @[el2_lib.scala 472:23] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= clock @[el2_lib.scala 474:18] + rvclkhdr_1.io.en <= ibuf_wr_en @[el2_lib.scala 475:17] + rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 476:24] + reg _T_939 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 478:16] + _T_939 <= ibuf_data_in @[el2_lib.scala 478:16] + ibuf_data <= _T_939 @[el2_lsu_bus_buffer.scala 282:13] + reg _T_940 : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 283:59] + _T_940 <= ibuf_timer_in @[el2_lsu_bus_buffer.scala 283:59] + ibuf_timer <= _T_940 @[el2_lsu_bus_buffer.scala 283:14] + wire buf_numvld_wrcmd_any : UInt<4> + buf_numvld_wrcmd_any <= UInt<1>("h00") + wire buf_numvld_cmd_any : UInt<4> + buf_numvld_cmd_any <= UInt<1>("h00") + wire obuf_wr_timer : UInt<3> + obuf_wr_timer <= UInt<1>("h00") + wire buf_nomerge : UInt<1>[4] @[el2_lsu_bus_buffer.scala 287:25] + buf_nomerge[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 288:15] + buf_nomerge[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 288:15] + buf_nomerge[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 288:15] + buf_nomerge[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 288:15] + wire Cmdptr0 : UInt<2> + Cmdptr0 <= UInt<1>("h00") + wire buf_sideeffect : UInt<4> + buf_sideeffect <= UInt<1>("h00") + wire obuf_force_wr_en : UInt<1> + obuf_force_wr_en <= UInt<1>("h00") + wire obuf_wr_en : UInt<1> + obuf_wr_en <= UInt<1>("h00") + node _T_941 = eq(buf_numvld_wrcmd_any, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 293:43] + node _T_942 = eq(buf_numvld_cmd_any, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 293:72] + node _T_943 = and(_T_941, _T_942) @[el2_lsu_bus_buffer.scala 293:51] + node _T_944 = neq(obuf_wr_timer, UInt<3>("h07")) @[el2_lsu_bus_buffer.scala 293:97] + node _T_945 = and(_T_943, _T_944) @[el2_lsu_bus_buffer.scala 293:80] + node _T_946 = eq(bus_coalescing_disable, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 294:5] + node _T_947 = and(_T_945, _T_946) @[el2_lsu_bus_buffer.scala 293:114] + node _T_948 = eq(Cmdptr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 294:114] + node _T_949 = eq(Cmdptr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 294:114] + node _T_950 = eq(Cmdptr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 294:114] + node _T_951 = eq(Cmdptr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 294:114] + node _T_952 = mux(_T_948, buf_nomerge[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_953 = mux(_T_949, buf_nomerge[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_954 = mux(_T_950, buf_nomerge[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_955 = mux(_T_951, buf_nomerge[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_956 = or(_T_952, _T_953) @[Mux.scala 27:72] + node _T_957 = or(_T_956, _T_954) @[Mux.scala 27:72] + node _T_958 = or(_T_957, _T_955) @[Mux.scala 27:72] + wire _T_959 : UInt<1> @[Mux.scala 27:72] + _T_959 <= _T_958 @[Mux.scala 27:72] + node _T_960 = eq(_T_959, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 294:31] + node _T_961 = and(_T_947, _T_960) @[el2_lsu_bus_buffer.scala 294:29] + node _T_962 = eq(Cmdptr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 295:88] + node _T_963 = bits(buf_sideeffect, 0, 0) @[el2_lsu_bus_buffer.scala 295:111] + node _T_964 = eq(Cmdptr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 295:88] + node _T_965 = bits(buf_sideeffect, 1, 1) @[el2_lsu_bus_buffer.scala 295:111] + node _T_966 = eq(Cmdptr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 295:88] + node _T_967 = bits(buf_sideeffect, 2, 2) @[el2_lsu_bus_buffer.scala 295:111] + node _T_968 = eq(Cmdptr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 295:88] + node _T_969 = bits(buf_sideeffect, 3, 3) @[el2_lsu_bus_buffer.scala 295:111] + node _T_970 = mux(_T_962, _T_963, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_971 = mux(_T_964, _T_965, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_972 = mux(_T_966, _T_967, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_973 = mux(_T_968, _T_969, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_974 = or(_T_970, _T_971) @[Mux.scala 27:72] + node _T_975 = or(_T_974, _T_972) @[Mux.scala 27:72] + node _T_976 = or(_T_975, _T_973) @[Mux.scala 27:72] + wire _T_977 : UInt<1> @[Mux.scala 27:72] + _T_977 <= _T_976 @[Mux.scala 27:72] + node _T_978 = eq(_T_977, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 295:5] + node _T_979 = and(_T_961, _T_978) @[el2_lsu_bus_buffer.scala 294:140] + node _T_980 = eq(obuf_force_wr_en, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 295:119] + node obuf_wr_wait = and(_T_979, _T_980) @[el2_lsu_bus_buffer.scala 295:117] + node _T_981 = orr(buf_numvld_cmd_any) @[el2_lsu_bus_buffer.scala 296:75] + node _T_982 = lt(obuf_wr_timer, UInt<3>("h07")) @[el2_lsu_bus_buffer.scala 296:95] + node _T_983 = and(_T_981, _T_982) @[el2_lsu_bus_buffer.scala 296:79] + node _T_984 = add(obuf_wr_timer, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 296:121] + node _T_985 = tail(_T_984, 1) @[el2_lsu_bus_buffer.scala 296:121] + node _T_986 = mux(_T_983, _T_985, obuf_wr_timer) @[el2_lsu_bus_buffer.scala 296:55] + node obuf_wr_timer_in = mux(obuf_wr_en, UInt<3>("h00"), _T_986) @[el2_lsu_bus_buffer.scala 296:29] + node _T_987 = eq(io.lsu_busreq_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 297:41] + node _T_988 = and(io.lsu_busreq_m, _T_987) @[el2_lsu_bus_buffer.scala 297:39] + node _T_989 = eq(ibuf_valid, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 297:60] + node _T_990 = and(_T_988, _T_989) @[el2_lsu_bus_buffer.scala 297:58] + node _T_991 = eq(buf_numvld_cmd_any, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 297:93] + node _T_992 = and(_T_990, _T_991) @[el2_lsu_bus_buffer.scala 297:72] + node _T_993 = bits(io.lsu_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 297:117] + node _T_994 = eq(Cmdptr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 297:208] + node _T_995 = bits(buf_addr[0], 31, 2) @[el2_lsu_bus_buffer.scala 297:228] + node _T_996 = eq(Cmdptr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 297:208] + node _T_997 = bits(buf_addr[1], 31, 2) @[el2_lsu_bus_buffer.scala 297:228] + node _T_998 = eq(Cmdptr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 297:208] + node _T_999 = bits(buf_addr[2], 31, 2) @[el2_lsu_bus_buffer.scala 297:228] + node _T_1000 = eq(Cmdptr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 297:208] + node _T_1001 = bits(buf_addr[3], 31, 2) @[el2_lsu_bus_buffer.scala 297:228] + node _T_1002 = mux(_T_994, _T_995, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1003 = mux(_T_996, _T_997, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1004 = mux(_T_998, _T_999, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1005 = mux(_T_1000, _T_1001, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1006 = or(_T_1002, _T_1003) @[Mux.scala 27:72] + node _T_1007 = or(_T_1006, _T_1004) @[Mux.scala 27:72] + node _T_1008 = or(_T_1007, _T_1005) @[Mux.scala 27:72] + wire _T_1009 : UInt<30> @[Mux.scala 27:72] + _T_1009 <= _T_1008 @[Mux.scala 27:72] + node _T_1010 = neq(_T_993, _T_1009) @[el2_lsu_bus_buffer.scala 297:123] + node _T_1011 = and(_T_992, _T_1010) @[el2_lsu_bus_buffer.scala 297:101] + obuf_force_wr_en <= _T_1011 @[el2_lsu_bus_buffer.scala 297:20] + wire buf_numvld_pend_any : UInt<4> + buf_numvld_pend_any <= UInt<1>("h00") + node _T_1012 = eq(buf_numvld_pend_any, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 299:53] + node _T_1013 = and(ibuf_byp, _T_1012) @[el2_lsu_bus_buffer.scala 299:31] + node _T_1014 = eq(io.lsu_pkt_r.store, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 299:64] + node _T_1015 = or(_T_1014, io.no_dword_merge_r) @[el2_lsu_bus_buffer.scala 299:84] + node ibuf_buf_byp = and(_T_1013, _T_1015) @[el2_lsu_bus_buffer.scala 299:61] + wire bus_sideeffect_pend : UInt<1> + bus_sideeffect_pend <= UInt<1>("h00") + wire found_cmdptr0 : UInt<1> + found_cmdptr0 <= UInt<1>("h00") + wire buf_cmd_state_bus_en : UInt<1>[4] @[el2_lsu_bus_buffer.scala 302:34] + buf_cmd_state_bus_en[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 303:24] + buf_cmd_state_bus_en[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 303:24] + buf_cmd_state_bus_en[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 303:24] + buf_cmd_state_bus_en[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 303:24] + wire buf_dual : UInt<1>[4] @[el2_lsu_bus_buffer.scala 304:22] + buf_dual[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 305:12] + buf_dual[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 305:12] + buf_dual[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 305:12] + buf_dual[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 305:12] + wire buf_samedw : UInt<1>[4] @[el2_lsu_bus_buffer.scala 306:24] + buf_samedw[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 307:14] + buf_samedw[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 307:14] + buf_samedw[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 307:14] + buf_samedw[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 307:14] + wire found_cmdptr1 : UInt<1> + found_cmdptr1 <= UInt<1>("h00") + wire bus_cmd_ready : UInt<1> + bus_cmd_ready <= UInt<1>("h00") + wire obuf_valid : UInt<1> + obuf_valid <= UInt<1>("h00") + wire obuf_nosend : UInt<1> + obuf_nosend <= UInt<1>("h00") + wire lsu_bus_cntr_overflow : UInt<1> + lsu_bus_cntr_overflow <= UInt<1>("h00") + wire bus_addr_match_pending : UInt<1> + bus_addr_match_pending <= UInt<1>("h00") + node _T_1016 = and(ibuf_buf_byp, io.lsu_commit_r) @[el2_lsu_bus_buffer.scala 314:32] + node _T_1017 = and(io.is_sideeffects_r, bus_sideeffect_pend) @[el2_lsu_bus_buffer.scala 314:74] + node _T_1018 = eq(_T_1017, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 314:52] + node _T_1019 = and(_T_1016, _T_1018) @[el2_lsu_bus_buffer.scala 314:50] + node _T_1020 = eq(Cmdptr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 315:89] + node _T_1021 = eq(Cmdptr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 315:89] + node _T_1022 = eq(Cmdptr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 315:89] + node _T_1023 = eq(Cmdptr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 315:89] + node _T_1024 = mux(_T_1020, buf_state[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1025 = mux(_T_1021, buf_state[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1026 = mux(_T_1022, buf_state[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1027 = mux(_T_1023, buf_state[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1028 = or(_T_1024, _T_1025) @[Mux.scala 27:72] + node _T_1029 = or(_T_1028, _T_1026) @[Mux.scala 27:72] + node _T_1030 = or(_T_1029, _T_1027) @[Mux.scala 27:72] + wire _T_1031 : UInt<3> @[Mux.scala 27:72] + _T_1031 <= _T_1030 @[Mux.scala 27:72] + node _T_1032 = eq(_T_1031, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 315:113] + node _T_1033 = and(_T_1032, found_cmdptr0) @[el2_lsu_bus_buffer.scala 315:124] + node _T_1034 = cat(buf_cmd_state_bus_en[3], buf_cmd_state_bus_en[2]) @[Cat.scala 29:58] + node _T_1035 = cat(_T_1034, buf_cmd_state_bus_en[1]) @[Cat.scala 29:58] + node _T_1036 = cat(_T_1035, buf_cmd_state_bus_en[0]) @[Cat.scala 29:58] + node _T_1037 = eq(Cmdptr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_1038 = bits(_T_1036, 0, 0) @[el2_lsu_bus_buffer.scala 110:129] + node _T_1039 = eq(Cmdptr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_1040 = bits(_T_1036, 1, 1) @[el2_lsu_bus_buffer.scala 110:129] + node _T_1041 = eq(Cmdptr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_1042 = bits(_T_1036, 2, 2) @[el2_lsu_bus_buffer.scala 110:129] + node _T_1043 = eq(Cmdptr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_1044 = bits(_T_1036, 3, 3) @[el2_lsu_bus_buffer.scala 110:129] + node _T_1045 = mux(_T_1037, _T_1038, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1046 = mux(_T_1039, _T_1040, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1047 = mux(_T_1041, _T_1042, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1048 = mux(_T_1043, _T_1044, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1049 = or(_T_1045, _T_1046) @[Mux.scala 27:72] + node _T_1050 = or(_T_1049, _T_1047) @[Mux.scala 27:72] + node _T_1051 = or(_T_1050, _T_1048) @[Mux.scala 27:72] + wire _T_1052 : UInt<1> @[Mux.scala 27:72] + _T_1052 <= _T_1051 @[Mux.scala 27:72] + node _T_1053 = eq(_T_1052, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 316:23] + node _T_1054 = and(_T_1033, _T_1053) @[el2_lsu_bus_buffer.scala 316:21] + node _T_1055 = eq(Cmdptr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_1056 = bits(buf_sideeffect, 0, 0) @[el2_lsu_bus_buffer.scala 110:129] + node _T_1057 = eq(Cmdptr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_1058 = bits(buf_sideeffect, 1, 1) @[el2_lsu_bus_buffer.scala 110:129] + node _T_1059 = eq(Cmdptr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_1060 = bits(buf_sideeffect, 2, 2) @[el2_lsu_bus_buffer.scala 110:129] + node _T_1061 = eq(Cmdptr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_1062 = bits(buf_sideeffect, 3, 3) @[el2_lsu_bus_buffer.scala 110:129] + node _T_1063 = mux(_T_1055, _T_1056, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1064 = mux(_T_1057, _T_1058, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1065 = mux(_T_1059, _T_1060, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1066 = mux(_T_1061, _T_1062, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1067 = or(_T_1063, _T_1064) @[Mux.scala 27:72] + node _T_1068 = or(_T_1067, _T_1065) @[Mux.scala 27:72] + node _T_1069 = or(_T_1068, _T_1066) @[Mux.scala 27:72] + wire _T_1070 : UInt<1> @[Mux.scala 27:72] + _T_1070 <= _T_1069 @[Mux.scala 27:72] + node _T_1071 = and(_T_1070, bus_sideeffect_pend) @[el2_lsu_bus_buffer.scala 316:141] + node _T_1072 = eq(_T_1071, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 316:105] + node _T_1073 = and(_T_1054, _T_1072) @[el2_lsu_bus_buffer.scala 316:103] + node _T_1074 = cat(buf_dual[3], buf_dual[2]) @[Cat.scala 29:58] + node _T_1075 = cat(_T_1074, buf_dual[1]) @[Cat.scala 29:58] + node _T_1076 = cat(_T_1075, buf_dual[0]) @[Cat.scala 29:58] + node _T_1077 = eq(Cmdptr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_1078 = bits(_T_1076, 0, 0) @[el2_lsu_bus_buffer.scala 110:129] + node _T_1079 = eq(Cmdptr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_1080 = bits(_T_1076, 1, 1) @[el2_lsu_bus_buffer.scala 110:129] + node _T_1081 = eq(Cmdptr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_1082 = bits(_T_1076, 2, 2) @[el2_lsu_bus_buffer.scala 110:129] + node _T_1083 = eq(Cmdptr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_1084 = bits(_T_1076, 3, 3) @[el2_lsu_bus_buffer.scala 110:129] + node _T_1085 = mux(_T_1077, _T_1078, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1086 = mux(_T_1079, _T_1080, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1087 = mux(_T_1081, _T_1082, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1088 = mux(_T_1083, _T_1084, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1089 = or(_T_1085, _T_1086) @[Mux.scala 27:72] + node _T_1090 = or(_T_1089, _T_1087) @[Mux.scala 27:72] + node _T_1091 = or(_T_1090, _T_1088) @[Mux.scala 27:72] + wire _T_1092 : UInt<1> @[Mux.scala 27:72] + _T_1092 <= _T_1091 @[Mux.scala 27:72] + node _T_1093 = cat(buf_samedw[3], buf_samedw[2]) @[Cat.scala 29:58] + node _T_1094 = cat(_T_1093, buf_samedw[1]) @[Cat.scala 29:58] + node _T_1095 = cat(_T_1094, buf_samedw[0]) @[Cat.scala 29:58] + node _T_1096 = eq(Cmdptr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_1097 = bits(_T_1095, 0, 0) @[el2_lsu_bus_buffer.scala 110:129] + node _T_1098 = eq(Cmdptr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_1099 = bits(_T_1095, 1, 1) @[el2_lsu_bus_buffer.scala 110:129] + node _T_1100 = eq(Cmdptr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_1101 = bits(_T_1095, 2, 2) @[el2_lsu_bus_buffer.scala 110:129] + node _T_1102 = eq(Cmdptr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_1103 = bits(_T_1095, 3, 3) @[el2_lsu_bus_buffer.scala 110:129] + node _T_1104 = mux(_T_1096, _T_1097, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1105 = mux(_T_1098, _T_1099, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1106 = mux(_T_1100, _T_1101, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1107 = mux(_T_1102, _T_1103, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1108 = or(_T_1104, _T_1105) @[Mux.scala 27:72] + node _T_1109 = or(_T_1108, _T_1106) @[Mux.scala 27:72] + node _T_1110 = or(_T_1109, _T_1107) @[Mux.scala 27:72] + wire _T_1111 : UInt<1> @[Mux.scala 27:72] + _T_1111 <= _T_1110 @[Mux.scala 27:72] + node _T_1112 = and(_T_1092, _T_1111) @[el2_lsu_bus_buffer.scala 317:77] + node _T_1113 = eq(Cmdptr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_1114 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 110:129] + node _T_1115 = eq(Cmdptr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_1116 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 110:129] + node _T_1117 = eq(Cmdptr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_1118 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 110:129] + node _T_1119 = eq(Cmdptr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_1120 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 110:129] + node _T_1121 = mux(_T_1113, _T_1114, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1122 = mux(_T_1115, _T_1116, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1123 = mux(_T_1117, _T_1118, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1124 = mux(_T_1119, _T_1120, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1125 = or(_T_1121, _T_1122) @[Mux.scala 27:72] + node _T_1126 = or(_T_1125, _T_1123) @[Mux.scala 27:72] + node _T_1127 = or(_T_1126, _T_1124) @[Mux.scala 27:72] + wire _T_1128 : UInt<1> @[Mux.scala 27:72] + _T_1128 <= _T_1127 @[Mux.scala 27:72] + node _T_1129 = eq(_T_1128, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 317:150] + node _T_1130 = and(_T_1112, _T_1129) @[el2_lsu_bus_buffer.scala 317:148] + node _T_1131 = eq(_T_1130, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 317:8] + node _T_1132 = or(_T_1131, found_cmdptr1) @[el2_lsu_bus_buffer.scala 317:181] + node _T_1133 = cat(buf_nomerge[3], buf_nomerge[2]) @[Cat.scala 29:58] + node _T_1134 = cat(_T_1133, buf_nomerge[1]) @[Cat.scala 29:58] + node _T_1135 = cat(_T_1134, buf_nomerge[0]) @[Cat.scala 29:58] + node _T_1136 = eq(Cmdptr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_1137 = bits(_T_1135, 0, 0) @[el2_lsu_bus_buffer.scala 110:129] + node _T_1138 = eq(Cmdptr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_1139 = bits(_T_1135, 1, 1) @[el2_lsu_bus_buffer.scala 110:129] + node _T_1140 = eq(Cmdptr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_1141 = bits(_T_1135, 2, 2) @[el2_lsu_bus_buffer.scala 110:129] + node _T_1142 = eq(Cmdptr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_1143 = bits(_T_1135, 3, 3) @[el2_lsu_bus_buffer.scala 110:129] + node _T_1144 = mux(_T_1136, _T_1137, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1145 = mux(_T_1138, _T_1139, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1146 = mux(_T_1140, _T_1141, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1147 = mux(_T_1142, _T_1143, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1148 = or(_T_1144, _T_1145) @[Mux.scala 27:72] + node _T_1149 = or(_T_1148, _T_1146) @[Mux.scala 27:72] + node _T_1150 = or(_T_1149, _T_1147) @[Mux.scala 27:72] + wire _T_1151 : UInt<1> @[Mux.scala 27:72] + _T_1151 <= _T_1150 @[Mux.scala 27:72] + node _T_1152 = or(_T_1132, _T_1151) @[el2_lsu_bus_buffer.scala 317:197] + node _T_1153 = or(_T_1152, obuf_force_wr_en) @[el2_lsu_bus_buffer.scala 317:269] + node _T_1154 = and(_T_1073, _T_1153) @[el2_lsu_bus_buffer.scala 316:164] + node _T_1155 = or(_T_1019, _T_1154) @[el2_lsu_bus_buffer.scala 314:98] + node _T_1156 = eq(obuf_valid, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 318:48] + node _T_1157 = or(bus_cmd_ready, _T_1156) @[el2_lsu_bus_buffer.scala 318:46] + node _T_1158 = or(_T_1157, obuf_nosend) @[el2_lsu_bus_buffer.scala 318:60] + node _T_1159 = and(_T_1155, _T_1158) @[el2_lsu_bus_buffer.scala 318:29] + node _T_1160 = eq(obuf_wr_wait, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 318:77] + node _T_1161 = and(_T_1159, _T_1160) @[el2_lsu_bus_buffer.scala 318:75] + node _T_1162 = eq(lsu_bus_cntr_overflow, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 318:93] + node _T_1163 = and(_T_1161, _T_1162) @[el2_lsu_bus_buffer.scala 318:91] + node _T_1164 = eq(bus_addr_match_pending, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 318:118] + node _T_1165 = and(_T_1163, _T_1164) @[el2_lsu_bus_buffer.scala 318:116] + node _T_1166 = and(_T_1165, io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 318:142] + obuf_wr_en <= _T_1166 @[el2_lsu_bus_buffer.scala 314:14] + wire bus_cmd_sent : UInt<1> + bus_cmd_sent <= UInt<1>("h00") + node _T_1167 = and(obuf_valid, obuf_nosend) @[el2_lsu_bus_buffer.scala 320:47] + node _T_1168 = or(bus_cmd_sent, _T_1167) @[el2_lsu_bus_buffer.scala 320:33] + node _T_1169 = eq(obuf_wr_en, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 320:65] + node _T_1170 = and(_T_1168, _T_1169) @[el2_lsu_bus_buffer.scala 320:63] + node _T_1171 = and(_T_1170, io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 320:77] + node obuf_rst = or(_T_1171, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 320:98] + node _T_1172 = eq(Cmdptr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_1173 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 110:129] + node _T_1174 = eq(Cmdptr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_1175 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 110:129] + node _T_1176 = eq(Cmdptr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_1177 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 110:129] + node _T_1178 = eq(Cmdptr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_1179 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 110:129] + node _T_1180 = mux(_T_1172, _T_1173, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1181 = mux(_T_1174, _T_1175, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1182 = mux(_T_1176, _T_1177, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1183 = mux(_T_1178, _T_1179, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1184 = or(_T_1180, _T_1181) @[Mux.scala 27:72] + node _T_1185 = or(_T_1184, _T_1182) @[Mux.scala 27:72] + node _T_1186 = or(_T_1185, _T_1183) @[Mux.scala 27:72] + wire _T_1187 : UInt<1> @[Mux.scala 27:72] + _T_1187 <= _T_1186 @[Mux.scala 27:72] + node obuf_write_in = mux(ibuf_buf_byp, io.lsu_pkt_r.store, _T_1187) @[el2_lsu_bus_buffer.scala 321:26] + node _T_1188 = eq(Cmdptr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_1189 = bits(buf_sideeffect, 0, 0) @[el2_lsu_bus_buffer.scala 110:129] + node _T_1190 = eq(Cmdptr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_1191 = bits(buf_sideeffect, 1, 1) @[el2_lsu_bus_buffer.scala 110:129] + node _T_1192 = eq(Cmdptr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_1193 = bits(buf_sideeffect, 2, 2) @[el2_lsu_bus_buffer.scala 110:129] + node _T_1194 = eq(Cmdptr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_1195 = bits(buf_sideeffect, 3, 3) @[el2_lsu_bus_buffer.scala 110:129] + node _T_1196 = mux(_T_1188, _T_1189, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1197 = mux(_T_1190, _T_1191, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1198 = mux(_T_1192, _T_1193, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1199 = mux(_T_1194, _T_1195, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1200 = or(_T_1196, _T_1197) @[Mux.scala 27:72] + node _T_1201 = or(_T_1200, _T_1198) @[Mux.scala 27:72] + node _T_1202 = or(_T_1201, _T_1199) @[Mux.scala 27:72] + wire _T_1203 : UInt<1> @[Mux.scala 27:72] + _T_1203 <= _T_1202 @[Mux.scala 27:72] + node obuf_sideeffect_in = mux(ibuf_buf_byp, io.is_sideeffects_r, _T_1203) @[el2_lsu_bus_buffer.scala 322:31] + node _T_1204 = eq(Cmdptr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_1205 = eq(Cmdptr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_1206 = eq(Cmdptr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_1207 = eq(Cmdptr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_1208 = mux(_T_1204, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1209 = mux(_T_1205, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1210 = mux(_T_1206, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1211 = mux(_T_1207, buf_addr[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1212 = or(_T_1208, _T_1209) @[Mux.scala 27:72] + node _T_1213 = or(_T_1212, _T_1210) @[Mux.scala 27:72] + node _T_1214 = or(_T_1213, _T_1211) @[Mux.scala 27:72] + wire _T_1215 : UInt<32> @[Mux.scala 27:72] + _T_1215 <= _T_1214 @[Mux.scala 27:72] + node obuf_addr_in = mux(ibuf_buf_byp, io.lsu_addr_r, _T_1215) @[el2_lsu_bus_buffer.scala 323:25] + wire buf_sz : UInt<2>[4] @[el2_lsu_bus_buffer.scala 324:20] + buf_sz[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 325:10] + buf_sz[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 325:10] + buf_sz[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 325:10] + buf_sz[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 325:10] + node _T_1216 = cat(io.lsu_pkt_r.word, io.lsu_pkt_r.half) @[Cat.scala 29:58] + node _T_1217 = eq(Cmdptr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_1218 = eq(Cmdptr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_1219 = eq(Cmdptr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_1220 = eq(Cmdptr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_1221 = mux(_T_1217, buf_sz[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1222 = mux(_T_1218, buf_sz[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1223 = mux(_T_1219, buf_sz[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1224 = mux(_T_1220, buf_sz[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1225 = or(_T_1221, _T_1222) @[Mux.scala 27:72] + node _T_1226 = or(_T_1225, _T_1223) @[Mux.scala 27:72] + node _T_1227 = or(_T_1226, _T_1224) @[Mux.scala 27:72] + wire _T_1228 : UInt<2> @[Mux.scala 27:72] + _T_1228 <= _T_1227 @[Mux.scala 27:72] + node obuf_sz_in = mux(ibuf_buf_byp, _T_1216, _T_1228) @[el2_lsu_bus_buffer.scala 326:23] + wire obuf_merge_en : UInt<1> + obuf_merge_en <= UInt<1>("h00") + node obuf_tag0_in = mux(ibuf_buf_byp, WrPtr0_r, Cmdptr0) @[el2_lsu_bus_buffer.scala 329:25] + wire Cmdptr1 : UInt<2> + Cmdptr1 <= UInt<1>("h00") + node obuf_tag1_in = mux(ibuf_buf_byp, WrPtr1_r, Cmdptr1) @[el2_lsu_bus_buffer.scala 331:25] + wire obuf_cmd_done : UInt<1> + obuf_cmd_done <= UInt<1>("h00") + wire bus_wcmd_sent : UInt<1> + bus_wcmd_sent <= UInt<1>("h00") + node _T_1229 = or(obuf_wr_en, obuf_rst) @[el2_lsu_bus_buffer.scala 334:39] + node _T_1230 = eq(_T_1229, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 334:26] + node _T_1231 = or(obuf_cmd_done, bus_wcmd_sent) @[el2_lsu_bus_buffer.scala 334:68] + node obuf_cmd_done_in = and(_T_1230, _T_1231) @[el2_lsu_bus_buffer.scala 334:51] + wire obuf_data_done : UInt<1> + obuf_data_done <= UInt<1>("h00") + wire bus_wdata_sent : UInt<1> + bus_wdata_sent <= UInt<1>("h00") + node _T_1232 = or(obuf_wr_en, obuf_rst) @[el2_lsu_bus_buffer.scala 337:40] + node _T_1233 = eq(_T_1232, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 337:27] + node _T_1234 = or(obuf_data_done, bus_wdata_sent) @[el2_lsu_bus_buffer.scala 337:70] + node obuf_data_done_in = and(_T_1233, _T_1234) @[el2_lsu_bus_buffer.scala 337:52] + node _T_1235 = bits(obuf_sz_in, 1, 0) @[el2_lsu_bus_buffer.scala 338:67] + node _T_1236 = eq(_T_1235, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 338:72] + node _T_1237 = bits(obuf_sz_in, 0, 0) @[el2_lsu_bus_buffer.scala 338:92] + node _T_1238 = bits(obuf_addr_in, 0, 0) @[el2_lsu_bus_buffer.scala 338:111] + node _T_1239 = eq(_T_1238, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 338:98] + node _T_1240 = and(_T_1237, _T_1239) @[el2_lsu_bus_buffer.scala 338:96] + node _T_1241 = or(_T_1236, _T_1240) @[el2_lsu_bus_buffer.scala 338:79] + node _T_1242 = bits(obuf_sz_in, 1, 1) @[el2_lsu_bus_buffer.scala 338:129] + node _T_1243 = bits(obuf_addr_in, 1, 0) @[el2_lsu_bus_buffer.scala 338:147] + node _T_1244 = orr(_T_1243) @[el2_lsu_bus_buffer.scala 338:153] + node _T_1245 = eq(_T_1244, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 338:134] + node _T_1246 = and(_T_1242, _T_1245) @[el2_lsu_bus_buffer.scala 338:132] + node _T_1247 = or(_T_1241, _T_1246) @[el2_lsu_bus_buffer.scala 338:116] + node obuf_aligned_in = mux(ibuf_buf_byp, is_aligned_r, _T_1247) @[el2_lsu_bus_buffer.scala 338:28] + wire obuf_nosend_in : UInt<1> + obuf_nosend_in <= UInt<1>("h00") + wire obuf_rdrsp_pend : UInt<1> + obuf_rdrsp_pend <= UInt<1>("h00") + wire bus_rsp_read : UInt<1> + bus_rsp_read <= UInt<1>("h00") + wire bus_rsp_read_tag : UInt<3> + bus_rsp_read_tag <= UInt<1>("h00") + wire obuf_rdrsp_tag : UInt<3> + obuf_rdrsp_tag <= UInt<1>("h00") + wire obuf_write : UInt<1> + obuf_write <= UInt<1>("h00") + node _T_1248 = eq(obuf_nosend_in, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 346:44] + node _T_1249 = and(obuf_wr_en, _T_1248) @[el2_lsu_bus_buffer.scala 346:42] + node _T_1250 = eq(_T_1249, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 346:29] + node _T_1251 = and(_T_1250, obuf_rdrsp_pend) @[el2_lsu_bus_buffer.scala 346:61] + node _T_1252 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[el2_lsu_bus_buffer.scala 346:116] + node _T_1253 = and(bus_rsp_read, _T_1252) @[el2_lsu_bus_buffer.scala 346:96] + node _T_1254 = eq(_T_1253, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 346:81] + node _T_1255 = and(_T_1251, _T_1254) @[el2_lsu_bus_buffer.scala 346:79] + node _T_1256 = eq(obuf_write, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 347:22] + node _T_1257 = and(bus_cmd_sent, _T_1256) @[el2_lsu_bus_buffer.scala 347:20] + node _T_1258 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 347:37] + node _T_1259 = and(_T_1257, _T_1258) @[el2_lsu_bus_buffer.scala 347:35] + node obuf_rdrsp_pend_in = or(_T_1255, _T_1259) @[el2_lsu_bus_buffer.scala 346:138] + wire obuf_tag0 : UInt<3> + obuf_tag0 <= UInt<1>("h00") + node _T_1260 = eq(obuf_write, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 349:46] + node _T_1261 = or(bus_cmd_sent, _T_1260) @[el2_lsu_bus_buffer.scala 349:44] + node obuf_rdrsp_tag_in = mux(_T_1261, obuf_tag0, obuf_rdrsp_tag) @[el2_lsu_bus_buffer.scala 349:30] + wire obuf_addr : UInt<32> + obuf_addr <= UInt<1>("h00") + wire obuf_sideeffect : UInt<1> + obuf_sideeffect <= UInt<1>("h00") + node _T_1262 = bits(obuf_addr_in, 31, 3) @[el2_lsu_bus_buffer.scala 352:34] + node _T_1263 = bits(obuf_addr, 31, 3) @[el2_lsu_bus_buffer.scala 352:52] + node _T_1264 = eq(_T_1262, _T_1263) @[el2_lsu_bus_buffer.scala 352:40] + node _T_1265 = and(_T_1264, obuf_aligned_in) @[el2_lsu_bus_buffer.scala 352:60] + node _T_1266 = eq(obuf_sideeffect, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 352:80] + node _T_1267 = and(_T_1265, _T_1266) @[el2_lsu_bus_buffer.scala 352:78] + node _T_1268 = eq(obuf_write, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 352:99] + node _T_1269 = and(_T_1267, _T_1268) @[el2_lsu_bus_buffer.scala 352:97] + node _T_1270 = eq(obuf_write_in, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 352:113] + node _T_1271 = and(_T_1269, _T_1270) @[el2_lsu_bus_buffer.scala 352:111] + node _T_1272 = eq(io.dec_tlu_external_ldfwd_disable, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 352:130] + node _T_1273 = and(_T_1271, _T_1272) @[el2_lsu_bus_buffer.scala 352:128] + node _T_1274 = eq(obuf_nosend, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 353:20] + node _T_1275 = and(obuf_valid, _T_1274) @[el2_lsu_bus_buffer.scala 353:18] + node _T_1276 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[el2_lsu_bus_buffer.scala 353:90] + node _T_1277 = and(bus_rsp_read, _T_1276) @[el2_lsu_bus_buffer.scala 353:70] + node _T_1278 = eq(_T_1277, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 353:55] + node _T_1279 = and(obuf_rdrsp_pend, _T_1278) @[el2_lsu_bus_buffer.scala 353:53] + node _T_1280 = or(_T_1275, _T_1279) @[el2_lsu_bus_buffer.scala 353:34] + node _T_1281 = and(_T_1273, _T_1280) @[el2_lsu_bus_buffer.scala 352:165] + obuf_nosend_in <= _T_1281 @[el2_lsu_bus_buffer.scala 352:18] + node _T_1282 = bits(io.lsu_addr_r, 2, 2) @[el2_lsu_bus_buffer.scala 354:60] + node _T_1283 = cat(ldst_byteen_lo_r, UInt<4>("h00")) @[Cat.scala 29:58] + node _T_1284 = cat(UInt<4>("h00"), ldst_byteen_lo_r) @[Cat.scala 29:58] + node _T_1285 = mux(_T_1282, _T_1283, _T_1284) @[el2_lsu_bus_buffer.scala 354:46] + node _T_1286 = eq(Cmdptr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_1287 = eq(Cmdptr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_1288 = eq(Cmdptr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_1289 = eq(Cmdptr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_1290 = mux(_T_1286, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1291 = mux(_T_1287, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1292 = mux(_T_1288, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1293 = mux(_T_1289, buf_addr[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1294 = or(_T_1290, _T_1291) @[Mux.scala 27:72] + node _T_1295 = or(_T_1294, _T_1292) @[Mux.scala 27:72] + node _T_1296 = or(_T_1295, _T_1293) @[Mux.scala 27:72] + wire _T_1297 : UInt<32> @[Mux.scala 27:72] + _T_1297 <= _T_1296 @[Mux.scala 27:72] + node _T_1298 = bits(_T_1297, 2, 2) @[el2_lsu_bus_buffer.scala 355:36] + node _T_1299 = bits(_T_1298, 0, 0) @[el2_lsu_bus_buffer.scala 355:46] + node _T_1300 = eq(Cmdptr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_1301 = eq(Cmdptr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_1302 = eq(Cmdptr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_1303 = eq(Cmdptr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_1304 = mux(_T_1300, buf_byteen[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1305 = mux(_T_1301, buf_byteen[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1306 = mux(_T_1302, buf_byteen[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1307 = mux(_T_1303, buf_byteen[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1308 = or(_T_1304, _T_1305) @[Mux.scala 27:72] + node _T_1309 = or(_T_1308, _T_1306) @[Mux.scala 27:72] + node _T_1310 = or(_T_1309, _T_1307) @[Mux.scala 27:72] + wire _T_1311 : UInt<4> @[Mux.scala 27:72] + _T_1311 <= _T_1310 @[Mux.scala 27:72] + node _T_1312 = cat(_T_1311, UInt<4>("h00")) @[Cat.scala 29:58] + node _T_1313 = eq(Cmdptr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_1314 = eq(Cmdptr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_1315 = eq(Cmdptr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_1316 = eq(Cmdptr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_1317 = mux(_T_1313, buf_byteen[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1318 = mux(_T_1314, buf_byteen[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1319 = mux(_T_1315, buf_byteen[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1320 = mux(_T_1316, buf_byteen[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1321 = or(_T_1317, _T_1318) @[Mux.scala 27:72] + node _T_1322 = or(_T_1321, _T_1319) @[Mux.scala 27:72] + node _T_1323 = or(_T_1322, _T_1320) @[Mux.scala 27:72] + wire _T_1324 : UInt<4> @[Mux.scala 27:72] + _T_1324 <= _T_1323 @[Mux.scala 27:72] + node _T_1325 = cat(UInt<4>("h00"), _T_1324) @[Cat.scala 29:58] + node _T_1326 = mux(_T_1299, _T_1312, _T_1325) @[el2_lsu_bus_buffer.scala 355:8] + node obuf_byteen0_in = mux(ibuf_buf_byp, _T_1285, _T_1326) @[el2_lsu_bus_buffer.scala 354:28] + node _T_1327 = bits(io.end_addr_r, 2, 2) @[el2_lsu_bus_buffer.scala 356:60] + node _T_1328 = cat(ldst_byteen_hi_r, UInt<4>("h00")) @[Cat.scala 29:58] + node _T_1329 = cat(UInt<4>("h00"), ldst_byteen_hi_r) @[Cat.scala 29:58] + node _T_1330 = mux(_T_1327, _T_1328, _T_1329) @[el2_lsu_bus_buffer.scala 356:46] + node _T_1331 = eq(Cmdptr1, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_1332 = eq(Cmdptr1, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_1333 = eq(Cmdptr1, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_1334 = eq(Cmdptr1, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_1335 = mux(_T_1331, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1336 = mux(_T_1332, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1337 = mux(_T_1333, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1338 = mux(_T_1334, buf_addr[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1339 = or(_T_1335, _T_1336) @[Mux.scala 27:72] + node _T_1340 = or(_T_1339, _T_1337) @[Mux.scala 27:72] + node _T_1341 = or(_T_1340, _T_1338) @[Mux.scala 27:72] + wire _T_1342 : UInt<32> @[Mux.scala 27:72] + _T_1342 <= _T_1341 @[Mux.scala 27:72] + node _T_1343 = bits(_T_1342, 2, 2) @[el2_lsu_bus_buffer.scala 357:36] + node _T_1344 = bits(_T_1343, 0, 0) @[el2_lsu_bus_buffer.scala 357:46] + node _T_1345 = eq(Cmdptr1, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_1346 = eq(Cmdptr1, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_1347 = eq(Cmdptr1, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_1348 = eq(Cmdptr1, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_1349 = mux(_T_1345, buf_byteen[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1350 = mux(_T_1346, buf_byteen[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1351 = mux(_T_1347, buf_byteen[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1352 = mux(_T_1348, buf_byteen[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1353 = or(_T_1349, _T_1350) @[Mux.scala 27:72] + node _T_1354 = or(_T_1353, _T_1351) @[Mux.scala 27:72] + node _T_1355 = or(_T_1354, _T_1352) @[Mux.scala 27:72] + wire _T_1356 : UInt<4> @[Mux.scala 27:72] + _T_1356 <= _T_1355 @[Mux.scala 27:72] + node _T_1357 = cat(_T_1356, UInt<4>("h00")) @[Cat.scala 29:58] + node _T_1358 = eq(Cmdptr1, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_1359 = eq(Cmdptr1, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_1360 = eq(Cmdptr1, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_1361 = eq(Cmdptr1, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_1362 = mux(_T_1358, buf_byteen[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1363 = mux(_T_1359, buf_byteen[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1364 = mux(_T_1360, buf_byteen[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1365 = mux(_T_1361, buf_byteen[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1366 = or(_T_1362, _T_1363) @[Mux.scala 27:72] + node _T_1367 = or(_T_1366, _T_1364) @[Mux.scala 27:72] + node _T_1368 = or(_T_1367, _T_1365) @[Mux.scala 27:72] + wire _T_1369 : UInt<4> @[Mux.scala 27:72] + _T_1369 <= _T_1368 @[Mux.scala 27:72] + node _T_1370 = cat(UInt<4>("h00"), _T_1369) @[Cat.scala 29:58] + node _T_1371 = mux(_T_1344, _T_1357, _T_1370) @[el2_lsu_bus_buffer.scala 357:8] + node obuf_byteen1_in = mux(ibuf_buf_byp, _T_1330, _T_1371) @[el2_lsu_bus_buffer.scala 356:28] + node _T_1372 = bits(io.lsu_addr_r, 2, 2) @[el2_lsu_bus_buffer.scala 359:58] + node _T_1373 = cat(store_data_lo_r, UInt<32>("h00")) @[Cat.scala 29:58] + node _T_1374 = cat(UInt<32>("h00"), store_data_lo_r) @[Cat.scala 29:58] + node _T_1375 = mux(_T_1372, _T_1373, _T_1374) @[el2_lsu_bus_buffer.scala 359:44] + node _T_1376 = eq(Cmdptr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_1377 = eq(Cmdptr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_1378 = eq(Cmdptr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_1379 = eq(Cmdptr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_1380 = mux(_T_1376, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1381 = mux(_T_1377, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1382 = mux(_T_1378, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1383 = mux(_T_1379, buf_addr[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1384 = or(_T_1380, _T_1381) @[Mux.scala 27:72] + node _T_1385 = or(_T_1384, _T_1382) @[Mux.scala 27:72] + node _T_1386 = or(_T_1385, _T_1383) @[Mux.scala 27:72] + wire _T_1387 : UInt<32> @[Mux.scala 27:72] + _T_1387 <= _T_1386 @[Mux.scala 27:72] + node _T_1388 = bits(_T_1387, 2, 2) @[el2_lsu_bus_buffer.scala 360:36] + node _T_1389 = bits(_T_1388, 0, 0) @[el2_lsu_bus_buffer.scala 360:46] + node _T_1390 = eq(Cmdptr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_1391 = eq(Cmdptr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_1392 = eq(Cmdptr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_1393 = eq(Cmdptr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_1394 = mux(_T_1390, buf_data[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1395 = mux(_T_1391, buf_data[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1396 = mux(_T_1392, buf_data[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1397 = mux(_T_1393, buf_data[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1398 = or(_T_1394, _T_1395) @[Mux.scala 27:72] + node _T_1399 = or(_T_1398, _T_1396) @[Mux.scala 27:72] + node _T_1400 = or(_T_1399, _T_1397) @[Mux.scala 27:72] + wire _T_1401 : UInt<32> @[Mux.scala 27:72] + _T_1401 <= _T_1400 @[Mux.scala 27:72] + node _T_1402 = cat(_T_1401, UInt<32>("h00")) @[Cat.scala 29:58] + node _T_1403 = eq(Cmdptr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_1404 = eq(Cmdptr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_1405 = eq(Cmdptr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_1406 = eq(Cmdptr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_1407 = mux(_T_1403, buf_data[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1408 = mux(_T_1404, buf_data[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1409 = mux(_T_1405, buf_data[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1410 = mux(_T_1406, buf_data[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1411 = or(_T_1407, _T_1408) @[Mux.scala 27:72] + node _T_1412 = or(_T_1411, _T_1409) @[Mux.scala 27:72] + node _T_1413 = or(_T_1412, _T_1410) @[Mux.scala 27:72] + wire _T_1414 : UInt<32> @[Mux.scala 27:72] + _T_1414 <= _T_1413 @[Mux.scala 27:72] + node _T_1415 = cat(UInt<32>("h00"), _T_1414) @[Cat.scala 29:58] + node _T_1416 = mux(_T_1389, _T_1402, _T_1415) @[el2_lsu_bus_buffer.scala 360:8] + node obuf_data0_in = mux(ibuf_buf_byp, _T_1375, _T_1416) @[el2_lsu_bus_buffer.scala 359:26] + node _T_1417 = bits(io.lsu_addr_r, 2, 2) @[el2_lsu_bus_buffer.scala 361:58] + node _T_1418 = cat(store_data_hi_r, UInt<32>("h00")) @[Cat.scala 29:58] + node _T_1419 = cat(UInt<32>("h00"), store_data_hi_r) @[Cat.scala 29:58] + node _T_1420 = mux(_T_1417, _T_1418, _T_1419) @[el2_lsu_bus_buffer.scala 361:44] + node _T_1421 = eq(Cmdptr1, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_1422 = eq(Cmdptr1, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_1423 = eq(Cmdptr1, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_1424 = eq(Cmdptr1, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_1425 = mux(_T_1421, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1426 = mux(_T_1422, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1427 = mux(_T_1423, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1428 = mux(_T_1424, buf_addr[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1429 = or(_T_1425, _T_1426) @[Mux.scala 27:72] + node _T_1430 = or(_T_1429, _T_1427) @[Mux.scala 27:72] + node _T_1431 = or(_T_1430, _T_1428) @[Mux.scala 27:72] + wire _T_1432 : UInt<32> @[Mux.scala 27:72] + _T_1432 <= _T_1431 @[Mux.scala 27:72] + node _T_1433 = bits(_T_1432, 2, 2) @[el2_lsu_bus_buffer.scala 362:36] + node _T_1434 = bits(_T_1433, 0, 0) @[el2_lsu_bus_buffer.scala 362:46] + node _T_1435 = eq(Cmdptr1, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_1436 = eq(Cmdptr1, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_1437 = eq(Cmdptr1, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_1438 = eq(Cmdptr1, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_1439 = mux(_T_1435, buf_data[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1440 = mux(_T_1436, buf_data[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1441 = mux(_T_1437, buf_data[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1442 = mux(_T_1438, buf_data[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1443 = or(_T_1439, _T_1440) @[Mux.scala 27:72] + node _T_1444 = or(_T_1443, _T_1441) @[Mux.scala 27:72] + node _T_1445 = or(_T_1444, _T_1442) @[Mux.scala 27:72] + wire _T_1446 : UInt<32> @[Mux.scala 27:72] + _T_1446 <= _T_1445 @[Mux.scala 27:72] + node _T_1447 = cat(_T_1446, UInt<32>("h00")) @[Cat.scala 29:58] + node _T_1448 = eq(Cmdptr1, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_1449 = eq(Cmdptr1, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_1450 = eq(Cmdptr1, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_1451 = eq(Cmdptr1, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_1452 = mux(_T_1448, buf_data[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1453 = mux(_T_1449, buf_data[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1454 = mux(_T_1450, buf_data[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1455 = mux(_T_1451, buf_data[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1456 = or(_T_1452, _T_1453) @[Mux.scala 27:72] + node _T_1457 = or(_T_1456, _T_1454) @[Mux.scala 27:72] + node _T_1458 = or(_T_1457, _T_1455) @[Mux.scala 27:72] + wire _T_1459 : UInt<32> @[Mux.scala 27:72] + _T_1459 <= _T_1458 @[Mux.scala 27:72] + node _T_1460 = cat(UInt<32>("h00"), _T_1459) @[Cat.scala 29:58] + node _T_1461 = mux(_T_1434, _T_1447, _T_1460) @[el2_lsu_bus_buffer.scala 362:8] + node obuf_data1_in = mux(ibuf_buf_byp, _T_1420, _T_1461) @[el2_lsu_bus_buffer.scala 361:26] + node _T_1462 = bits(obuf_byteen0_in, 0, 0) @[el2_lsu_bus_buffer.scala 363:59] + node _T_1463 = bits(obuf_byteen1_in, 0, 0) @[el2_lsu_bus_buffer.scala 363:97] + node _T_1464 = and(obuf_merge_en, _T_1463) @[el2_lsu_bus_buffer.scala 363:80] + node _T_1465 = or(_T_1462, _T_1464) @[el2_lsu_bus_buffer.scala 363:63] + node _T_1466 = bits(obuf_byteen0_in, 1, 1) @[el2_lsu_bus_buffer.scala 363:59] + node _T_1467 = bits(obuf_byteen1_in, 1, 1) @[el2_lsu_bus_buffer.scala 363:97] + node _T_1468 = and(obuf_merge_en, _T_1467) @[el2_lsu_bus_buffer.scala 363:80] + node _T_1469 = or(_T_1466, _T_1468) @[el2_lsu_bus_buffer.scala 363:63] + node _T_1470 = bits(obuf_byteen0_in, 2, 2) @[el2_lsu_bus_buffer.scala 363:59] + node _T_1471 = bits(obuf_byteen1_in, 2, 2) @[el2_lsu_bus_buffer.scala 363:97] + node _T_1472 = and(obuf_merge_en, _T_1471) @[el2_lsu_bus_buffer.scala 363:80] + node _T_1473 = or(_T_1470, _T_1472) @[el2_lsu_bus_buffer.scala 363:63] + node _T_1474 = bits(obuf_byteen0_in, 3, 3) @[el2_lsu_bus_buffer.scala 363:59] + node _T_1475 = bits(obuf_byteen1_in, 3, 3) @[el2_lsu_bus_buffer.scala 363:97] + node _T_1476 = and(obuf_merge_en, _T_1475) @[el2_lsu_bus_buffer.scala 363:80] + node _T_1477 = or(_T_1474, _T_1476) @[el2_lsu_bus_buffer.scala 363:63] + node _T_1478 = bits(obuf_byteen0_in, 4, 4) @[el2_lsu_bus_buffer.scala 363:59] + node _T_1479 = bits(obuf_byteen1_in, 4, 4) @[el2_lsu_bus_buffer.scala 363:97] + node _T_1480 = and(obuf_merge_en, _T_1479) @[el2_lsu_bus_buffer.scala 363:80] + node _T_1481 = or(_T_1478, _T_1480) @[el2_lsu_bus_buffer.scala 363:63] + node _T_1482 = bits(obuf_byteen0_in, 5, 5) @[el2_lsu_bus_buffer.scala 363:59] + node _T_1483 = bits(obuf_byteen1_in, 5, 5) @[el2_lsu_bus_buffer.scala 363:97] + node _T_1484 = and(obuf_merge_en, _T_1483) @[el2_lsu_bus_buffer.scala 363:80] + node _T_1485 = or(_T_1482, _T_1484) @[el2_lsu_bus_buffer.scala 363:63] + node _T_1486 = bits(obuf_byteen0_in, 6, 6) @[el2_lsu_bus_buffer.scala 363:59] + node _T_1487 = bits(obuf_byteen1_in, 6, 6) @[el2_lsu_bus_buffer.scala 363:97] + node _T_1488 = and(obuf_merge_en, _T_1487) @[el2_lsu_bus_buffer.scala 363:80] + node _T_1489 = or(_T_1486, _T_1488) @[el2_lsu_bus_buffer.scala 363:63] + node _T_1490 = bits(obuf_byteen0_in, 7, 7) @[el2_lsu_bus_buffer.scala 363:59] + node _T_1491 = bits(obuf_byteen1_in, 7, 7) @[el2_lsu_bus_buffer.scala 363:97] + node _T_1492 = and(obuf_merge_en, _T_1491) @[el2_lsu_bus_buffer.scala 363:80] + node _T_1493 = or(_T_1490, _T_1492) @[el2_lsu_bus_buffer.scala 363:63] + node _T_1494 = cat(_T_1493, _T_1489) @[Cat.scala 29:58] + node _T_1495 = cat(_T_1494, _T_1485) @[Cat.scala 29:58] + node _T_1496 = cat(_T_1495, _T_1481) @[Cat.scala 29:58] + node _T_1497 = cat(_T_1496, _T_1477) @[Cat.scala 29:58] + node _T_1498 = cat(_T_1497, _T_1473) @[Cat.scala 29:58] + node _T_1499 = cat(_T_1498, _T_1469) @[Cat.scala 29:58] + node obuf_byteen_in = cat(_T_1499, _T_1465) @[Cat.scala 29:58] + node _T_1500 = bits(obuf_byteen1_in, 0, 0) @[el2_lsu_bus_buffer.scala 364:76] + node _T_1501 = and(obuf_merge_en, _T_1500) @[el2_lsu_bus_buffer.scala 364:59] + node _T_1502 = bits(obuf_data1_in, 7, 0) @[el2_lsu_bus_buffer.scala 364:94] + node _T_1503 = bits(obuf_data1_in, 7, 0) @[el2_lsu_bus_buffer.scala 364:123] + node _T_1504 = mux(_T_1501, _T_1502, _T_1503) @[el2_lsu_bus_buffer.scala 364:44] + node _T_1505 = bits(obuf_byteen1_in, 1, 1) @[el2_lsu_bus_buffer.scala 364:76] + node _T_1506 = and(obuf_merge_en, _T_1505) @[el2_lsu_bus_buffer.scala 364:59] + node _T_1507 = bits(obuf_data1_in, 15, 8) @[el2_lsu_bus_buffer.scala 364:94] + node _T_1508 = bits(obuf_data1_in, 15, 8) @[el2_lsu_bus_buffer.scala 364:123] + node _T_1509 = mux(_T_1506, _T_1507, _T_1508) @[el2_lsu_bus_buffer.scala 364:44] + node _T_1510 = bits(obuf_byteen1_in, 2, 2) @[el2_lsu_bus_buffer.scala 364:76] + node _T_1511 = and(obuf_merge_en, _T_1510) @[el2_lsu_bus_buffer.scala 364:59] + node _T_1512 = bits(obuf_data1_in, 23, 16) @[el2_lsu_bus_buffer.scala 364:94] + node _T_1513 = bits(obuf_data1_in, 23, 16) @[el2_lsu_bus_buffer.scala 364:123] + node _T_1514 = mux(_T_1511, _T_1512, _T_1513) @[el2_lsu_bus_buffer.scala 364:44] + node _T_1515 = bits(obuf_byteen1_in, 3, 3) @[el2_lsu_bus_buffer.scala 364:76] + node _T_1516 = and(obuf_merge_en, _T_1515) @[el2_lsu_bus_buffer.scala 364:59] + node _T_1517 = bits(obuf_data1_in, 31, 24) @[el2_lsu_bus_buffer.scala 364:94] + node _T_1518 = bits(obuf_data1_in, 31, 24) @[el2_lsu_bus_buffer.scala 364:123] + node _T_1519 = mux(_T_1516, _T_1517, _T_1518) @[el2_lsu_bus_buffer.scala 364:44] + node _T_1520 = bits(obuf_byteen1_in, 4, 4) @[el2_lsu_bus_buffer.scala 364:76] + node _T_1521 = and(obuf_merge_en, _T_1520) @[el2_lsu_bus_buffer.scala 364:59] + node _T_1522 = bits(obuf_data1_in, 39, 32) @[el2_lsu_bus_buffer.scala 364:94] + node _T_1523 = bits(obuf_data1_in, 39, 32) @[el2_lsu_bus_buffer.scala 364:123] + node _T_1524 = mux(_T_1521, _T_1522, _T_1523) @[el2_lsu_bus_buffer.scala 364:44] + node _T_1525 = bits(obuf_byteen1_in, 5, 5) @[el2_lsu_bus_buffer.scala 364:76] + node _T_1526 = and(obuf_merge_en, _T_1525) @[el2_lsu_bus_buffer.scala 364:59] + node _T_1527 = bits(obuf_data1_in, 47, 40) @[el2_lsu_bus_buffer.scala 364:94] + node _T_1528 = bits(obuf_data1_in, 47, 40) @[el2_lsu_bus_buffer.scala 364:123] + node _T_1529 = mux(_T_1526, _T_1527, _T_1528) @[el2_lsu_bus_buffer.scala 364:44] + node _T_1530 = bits(obuf_byteen1_in, 6, 6) @[el2_lsu_bus_buffer.scala 364:76] + node _T_1531 = and(obuf_merge_en, _T_1530) @[el2_lsu_bus_buffer.scala 364:59] + node _T_1532 = bits(obuf_data1_in, 55, 48) @[el2_lsu_bus_buffer.scala 364:94] + node _T_1533 = bits(obuf_data1_in, 55, 48) @[el2_lsu_bus_buffer.scala 364:123] + node _T_1534 = mux(_T_1531, _T_1532, _T_1533) @[el2_lsu_bus_buffer.scala 364:44] + node _T_1535 = bits(obuf_byteen1_in, 7, 7) @[el2_lsu_bus_buffer.scala 364:76] + node _T_1536 = and(obuf_merge_en, _T_1535) @[el2_lsu_bus_buffer.scala 364:59] + node _T_1537 = bits(obuf_data1_in, 63, 56) @[el2_lsu_bus_buffer.scala 364:94] + node _T_1538 = bits(obuf_data1_in, 63, 56) @[el2_lsu_bus_buffer.scala 364:123] + node _T_1539 = mux(_T_1536, _T_1537, _T_1538) @[el2_lsu_bus_buffer.scala 364:44] + node _T_1540 = cat(_T_1539, _T_1534) @[Cat.scala 29:58] + node _T_1541 = cat(_T_1540, _T_1529) @[Cat.scala 29:58] + node _T_1542 = cat(_T_1541, _T_1524) @[Cat.scala 29:58] + node _T_1543 = cat(_T_1542, _T_1519) @[Cat.scala 29:58] + node _T_1544 = cat(_T_1543, _T_1514) @[Cat.scala 29:58] + node _T_1545 = cat(_T_1544, _T_1509) @[Cat.scala 29:58] + node obuf_data_in = cat(_T_1545, _T_1504) @[Cat.scala 29:58] + wire buf_dualhi : UInt<1>[4] @[el2_lsu_bus_buffer.scala 365:24] + buf_dualhi[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 366:14] + buf_dualhi[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 366:14] + buf_dualhi[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 366:14] + buf_dualhi[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 366:14] + node _T_1546 = neq(Cmdptr0, Cmdptr1) @[el2_lsu_bus_buffer.scala 367:30] + node _T_1547 = and(_T_1546, found_cmdptr0) @[el2_lsu_bus_buffer.scala 367:43] + node _T_1548 = and(_T_1547, found_cmdptr1) @[el2_lsu_bus_buffer.scala 367:59] + node _T_1549 = eq(Cmdptr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_1550 = eq(Cmdptr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_1551 = eq(Cmdptr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_1552 = eq(Cmdptr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_1553 = mux(_T_1549, buf_state[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1554 = mux(_T_1550, buf_state[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1555 = mux(_T_1551, buf_state[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1556 = mux(_T_1552, buf_state[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1557 = or(_T_1553, _T_1554) @[Mux.scala 27:72] + node _T_1558 = or(_T_1557, _T_1555) @[Mux.scala 27:72] + node _T_1559 = or(_T_1558, _T_1556) @[Mux.scala 27:72] + wire _T_1560 : UInt<3> @[Mux.scala 27:72] + _T_1560 <= _T_1559 @[Mux.scala 27:72] + node _T_1561 = eq(_T_1560, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 367:107] + node _T_1562 = and(_T_1548, _T_1561) @[el2_lsu_bus_buffer.scala 367:75] + node _T_1563 = eq(Cmdptr1, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_1564 = eq(Cmdptr1, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_1565 = eq(Cmdptr1, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_1566 = eq(Cmdptr1, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_1567 = mux(_T_1563, buf_state[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1568 = mux(_T_1564, buf_state[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1569 = mux(_T_1565, buf_state[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1570 = mux(_T_1566, buf_state[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1571 = or(_T_1567, _T_1568) @[Mux.scala 27:72] + node _T_1572 = or(_T_1571, _T_1569) @[Mux.scala 27:72] + node _T_1573 = or(_T_1572, _T_1570) @[Mux.scala 27:72] + wire _T_1574 : UInt<3> @[Mux.scala 27:72] + _T_1574 <= _T_1573 @[Mux.scala 27:72] + node _T_1575 = eq(_T_1574, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 367:150] + node _T_1576 = and(_T_1562, _T_1575) @[el2_lsu_bus_buffer.scala 367:118] + node _T_1577 = cat(buf_cmd_state_bus_en[3], buf_cmd_state_bus_en[2]) @[Cat.scala 29:58] + node _T_1578 = cat(_T_1577, buf_cmd_state_bus_en[1]) @[Cat.scala 29:58] + node _T_1579 = cat(_T_1578, buf_cmd_state_bus_en[0]) @[Cat.scala 29:58] + node _T_1580 = eq(Cmdptr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_1581 = bits(_T_1579, 0, 0) @[el2_lsu_bus_buffer.scala 110:129] + node _T_1582 = eq(Cmdptr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_1583 = bits(_T_1579, 1, 1) @[el2_lsu_bus_buffer.scala 110:129] + node _T_1584 = eq(Cmdptr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_1585 = bits(_T_1579, 2, 2) @[el2_lsu_bus_buffer.scala 110:129] + node _T_1586 = eq(Cmdptr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_1587 = bits(_T_1579, 3, 3) @[el2_lsu_bus_buffer.scala 110:129] + node _T_1588 = mux(_T_1580, _T_1581, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1589 = mux(_T_1582, _T_1583, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1590 = mux(_T_1584, _T_1585, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1591 = mux(_T_1586, _T_1587, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1592 = or(_T_1588, _T_1589) @[Mux.scala 27:72] + node _T_1593 = or(_T_1592, _T_1590) @[Mux.scala 27:72] + node _T_1594 = or(_T_1593, _T_1591) @[Mux.scala 27:72] + wire _T_1595 : UInt<1> @[Mux.scala 27:72] + _T_1595 <= _T_1594 @[Mux.scala 27:72] + node _T_1596 = eq(_T_1595, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 368:3] + node _T_1597 = and(_T_1576, _T_1596) @[el2_lsu_bus_buffer.scala 367:161] + node _T_1598 = eq(Cmdptr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_1599 = bits(buf_sideeffect, 0, 0) @[el2_lsu_bus_buffer.scala 110:129] + node _T_1600 = eq(Cmdptr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_1601 = bits(buf_sideeffect, 1, 1) @[el2_lsu_bus_buffer.scala 110:129] + node _T_1602 = eq(Cmdptr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_1603 = bits(buf_sideeffect, 2, 2) @[el2_lsu_bus_buffer.scala 110:129] + node _T_1604 = eq(Cmdptr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_1605 = bits(buf_sideeffect, 3, 3) @[el2_lsu_bus_buffer.scala 110:129] + node _T_1606 = mux(_T_1598, _T_1599, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1607 = mux(_T_1600, _T_1601, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1608 = mux(_T_1602, _T_1603, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1609 = mux(_T_1604, _T_1605, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1610 = or(_T_1606, _T_1607) @[Mux.scala 27:72] + node _T_1611 = or(_T_1610, _T_1608) @[Mux.scala 27:72] + node _T_1612 = or(_T_1611, _T_1609) @[Mux.scala 27:72] + wire _T_1613 : UInt<1> @[Mux.scala 27:72] + _T_1613 <= _T_1612 @[Mux.scala 27:72] + node _T_1614 = eq(_T_1613, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 368:85] + node _T_1615 = and(_T_1597, _T_1614) @[el2_lsu_bus_buffer.scala 368:83] + node _T_1616 = eq(Cmdptr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_1617 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 110:129] + node _T_1618 = eq(Cmdptr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_1619 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 110:129] + node _T_1620 = eq(Cmdptr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_1621 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 110:129] + node _T_1622 = eq(Cmdptr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_1623 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 110:129] + node _T_1624 = mux(_T_1616, _T_1617, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1625 = mux(_T_1618, _T_1619, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1626 = mux(_T_1620, _T_1621, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1627 = mux(_T_1622, _T_1623, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1628 = or(_T_1624, _T_1625) @[Mux.scala 27:72] + node _T_1629 = or(_T_1628, _T_1626) @[Mux.scala 27:72] + node _T_1630 = or(_T_1629, _T_1627) @[Mux.scala 27:72] + wire _T_1631 : UInt<1> @[Mux.scala 27:72] + _T_1631 <= _T_1630 @[Mux.scala 27:72] + node _T_1632 = eq(Cmdptr1, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_1633 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 110:129] + node _T_1634 = eq(Cmdptr1, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_1635 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 110:129] + node _T_1636 = eq(Cmdptr1, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_1637 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 110:129] + node _T_1638 = eq(Cmdptr1, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_1639 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 110:129] + node _T_1640 = mux(_T_1632, _T_1633, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1641 = mux(_T_1634, _T_1635, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1642 = mux(_T_1636, _T_1637, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1643 = mux(_T_1638, _T_1639, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1644 = or(_T_1640, _T_1641) @[Mux.scala 27:72] + node _T_1645 = or(_T_1644, _T_1642) @[Mux.scala 27:72] + node _T_1646 = or(_T_1645, _T_1643) @[Mux.scala 27:72] + wire _T_1647 : UInt<1> @[Mux.scala 27:72] + _T_1647 <= _T_1646 @[Mux.scala 27:72] + node _T_1648 = and(_T_1631, _T_1647) @[el2_lsu_bus_buffer.scala 369:36] + node _T_1649 = eq(Cmdptr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_1650 = eq(Cmdptr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_1651 = eq(Cmdptr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_1652 = eq(Cmdptr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_1653 = mux(_T_1649, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1654 = mux(_T_1650, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1655 = mux(_T_1651, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1656 = mux(_T_1652, buf_addr[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1657 = or(_T_1653, _T_1654) @[Mux.scala 27:72] + node _T_1658 = or(_T_1657, _T_1655) @[Mux.scala 27:72] + node _T_1659 = or(_T_1658, _T_1656) @[Mux.scala 27:72] + wire _T_1660 : UInt<32> @[Mux.scala 27:72] + _T_1660 <= _T_1659 @[Mux.scala 27:72] + node _T_1661 = bits(_T_1660, 31, 3) @[el2_lsu_bus_buffer.scala 370:33] + node _T_1662 = eq(Cmdptr1, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_1663 = eq(Cmdptr1, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_1664 = eq(Cmdptr1, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_1665 = eq(Cmdptr1, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_1666 = mux(_T_1662, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1667 = mux(_T_1663, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1668 = mux(_T_1664, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1669 = mux(_T_1665, buf_addr[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1670 = or(_T_1666, _T_1667) @[Mux.scala 27:72] + node _T_1671 = or(_T_1670, _T_1668) @[Mux.scala 27:72] + node _T_1672 = or(_T_1671, _T_1669) @[Mux.scala 27:72] + wire _T_1673 : UInt<32> @[Mux.scala 27:72] + _T_1673 <= _T_1672 @[Mux.scala 27:72] + node _T_1674 = bits(_T_1673, 31, 3) @[el2_lsu_bus_buffer.scala 370:69] + node _T_1675 = eq(_T_1661, _T_1674) @[el2_lsu_bus_buffer.scala 370:39] + node _T_1676 = and(_T_1648, _T_1675) @[el2_lsu_bus_buffer.scala 369:67] + node _T_1677 = eq(bus_coalescing_disable, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 370:79] + node _T_1678 = and(_T_1676, _T_1677) @[el2_lsu_bus_buffer.scala 370:77] + node _T_1679 = eq(UInt<1>("h01"), UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 370:105] + node _T_1680 = and(_T_1678, _T_1679) @[el2_lsu_bus_buffer.scala 370:103] + node _T_1681 = eq(Cmdptr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_1682 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 110:129] + node _T_1683 = eq(Cmdptr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_1684 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 110:129] + node _T_1685 = eq(Cmdptr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_1686 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 110:129] + node _T_1687 = eq(Cmdptr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_1688 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 110:129] + node _T_1689 = mux(_T_1681, _T_1682, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1690 = mux(_T_1683, _T_1684, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1691 = mux(_T_1685, _T_1686, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1692 = mux(_T_1687, _T_1688, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1693 = or(_T_1689, _T_1690) @[Mux.scala 27:72] + node _T_1694 = or(_T_1693, _T_1691) @[Mux.scala 27:72] + node _T_1695 = or(_T_1694, _T_1692) @[Mux.scala 27:72] + wire _T_1696 : UInt<1> @[Mux.scala 27:72] + _T_1696 <= _T_1695 @[Mux.scala 27:72] + node _T_1697 = eq(_T_1696, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 371:6] + node _T_1698 = cat(buf_dual[3], buf_dual[2]) @[Cat.scala 29:58] + node _T_1699 = cat(_T_1698, buf_dual[1]) @[Cat.scala 29:58] + node _T_1700 = cat(_T_1699, buf_dual[0]) @[Cat.scala 29:58] + node _T_1701 = eq(Cmdptr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_1702 = bits(_T_1700, 0, 0) @[el2_lsu_bus_buffer.scala 110:129] + node _T_1703 = eq(Cmdptr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_1704 = bits(_T_1700, 1, 1) @[el2_lsu_bus_buffer.scala 110:129] + node _T_1705 = eq(Cmdptr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_1706 = bits(_T_1700, 2, 2) @[el2_lsu_bus_buffer.scala 110:129] + node _T_1707 = eq(Cmdptr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_1708 = bits(_T_1700, 3, 3) @[el2_lsu_bus_buffer.scala 110:129] + node _T_1709 = mux(_T_1701, _T_1702, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1710 = mux(_T_1703, _T_1704, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1711 = mux(_T_1705, _T_1706, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1712 = mux(_T_1707, _T_1708, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1713 = or(_T_1709, _T_1710) @[Mux.scala 27:72] + node _T_1714 = or(_T_1713, _T_1711) @[Mux.scala 27:72] + node _T_1715 = or(_T_1714, _T_1712) @[Mux.scala 27:72] + wire _T_1716 : UInt<1> @[Mux.scala 27:72] + _T_1716 <= _T_1715 @[Mux.scala 27:72] + node _T_1717 = and(_T_1697, _T_1716) @[el2_lsu_bus_buffer.scala 371:36] + node _T_1718 = cat(buf_dualhi[3], buf_dualhi[2]) @[Cat.scala 29:58] + node _T_1719 = cat(_T_1718, buf_dualhi[1]) @[Cat.scala 29:58] + node _T_1720 = cat(_T_1719, buf_dualhi[0]) @[Cat.scala 29:58] + node _T_1721 = eq(Cmdptr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_1722 = bits(_T_1720, 0, 0) @[el2_lsu_bus_buffer.scala 110:129] + node _T_1723 = eq(Cmdptr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_1724 = bits(_T_1720, 1, 1) @[el2_lsu_bus_buffer.scala 110:129] + node _T_1725 = eq(Cmdptr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_1726 = bits(_T_1720, 2, 2) @[el2_lsu_bus_buffer.scala 110:129] + node _T_1727 = eq(Cmdptr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_1728 = bits(_T_1720, 3, 3) @[el2_lsu_bus_buffer.scala 110:129] + node _T_1729 = mux(_T_1721, _T_1722, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1730 = mux(_T_1723, _T_1724, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1731 = mux(_T_1725, _T_1726, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1732 = mux(_T_1727, _T_1728, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1733 = or(_T_1729, _T_1730) @[Mux.scala 27:72] + node _T_1734 = or(_T_1733, _T_1731) @[Mux.scala 27:72] + node _T_1735 = or(_T_1734, _T_1732) @[Mux.scala 27:72] + wire _T_1736 : UInt<1> @[Mux.scala 27:72] + _T_1736 <= _T_1735 @[Mux.scala 27:72] + node _T_1737 = eq(_T_1736, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 371:107] + node _T_1738 = and(_T_1717, _T_1737) @[el2_lsu_bus_buffer.scala 371:105] + node _T_1739 = cat(buf_samedw[3], buf_samedw[2]) @[Cat.scala 29:58] + node _T_1740 = cat(_T_1739, buf_samedw[1]) @[Cat.scala 29:58] + node _T_1741 = cat(_T_1740, buf_samedw[0]) @[Cat.scala 29:58] + node _T_1742 = eq(Cmdptr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_1743 = bits(_T_1741, 0, 0) @[el2_lsu_bus_buffer.scala 110:129] + node _T_1744 = eq(Cmdptr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_1745 = bits(_T_1741, 1, 1) @[el2_lsu_bus_buffer.scala 110:129] + node _T_1746 = eq(Cmdptr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_1747 = bits(_T_1741, 2, 2) @[el2_lsu_bus_buffer.scala 110:129] + node _T_1748 = eq(Cmdptr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_1749 = bits(_T_1741, 3, 3) @[el2_lsu_bus_buffer.scala 110:129] + node _T_1750 = mux(_T_1742, _T_1743, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1751 = mux(_T_1744, _T_1745, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1752 = mux(_T_1746, _T_1747, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1753 = mux(_T_1748, _T_1749, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1754 = or(_T_1750, _T_1751) @[Mux.scala 27:72] + node _T_1755 = or(_T_1754, _T_1752) @[Mux.scala 27:72] + node _T_1756 = or(_T_1755, _T_1753) @[Mux.scala 27:72] + wire _T_1757 : UInt<1> @[Mux.scala 27:72] + _T_1757 <= _T_1756 @[Mux.scala 27:72] + node _T_1758 = and(_T_1738, _T_1757) @[el2_lsu_bus_buffer.scala 371:177] + node _T_1759 = or(_T_1680, _T_1758) @[el2_lsu_bus_buffer.scala 370:126] + node _T_1760 = and(_T_1615, _T_1759) @[el2_lsu_bus_buffer.scala 368:120] + node _T_1761 = and(ibuf_buf_byp, ldst_samedw_r) @[el2_lsu_bus_buffer.scala 372:19] + node _T_1762 = and(_T_1761, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 372:35] + node _T_1763 = or(_T_1760, _T_1762) @[el2_lsu_bus_buffer.scala 371:251] + obuf_merge_en <= _T_1763 @[el2_lsu_bus_buffer.scala 367:17] + reg obuf_wr_enQ : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 374:55] + obuf_wr_enQ <= obuf_wr_en @[el2_lsu_bus_buffer.scala 374:55] + node _T_1764 = mux(obuf_wr_en, UInt<1>("h01"), obuf_valid) @[el2_lsu_bus_buffer.scala 375:55] + node _T_1765 = and(_T_1764, obuf_rst) @[el2_lsu_bus_buffer.scala 375:88] + reg _T_1766 : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 375:51] + _T_1766 <= _T_1765 @[el2_lsu_bus_buffer.scala 375:51] + obuf_valid <= _T_1766 @[el2_lsu_bus_buffer.scala 375:14] + reg _T_1767 : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when obuf_wr_en : @[Reg.scala 28:19] + _T_1767 <= obuf_nosend_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + obuf_nosend <= _T_1767 @[el2_lsu_bus_buffer.scala 376:15] + reg _T_1768 : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 377:54] + _T_1768 <= obuf_cmd_done_in @[el2_lsu_bus_buffer.scala 377:54] + obuf_cmd_done <= _T_1768 @[el2_lsu_bus_buffer.scala 377:17] + reg _T_1769 : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 378:55] + _T_1769 <= obuf_data_done_in @[el2_lsu_bus_buffer.scala 378:55] + obuf_data_done <= _T_1769 @[el2_lsu_bus_buffer.scala 378:18] + reg _T_1770 : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 379:56] + _T_1770 <= obuf_rdrsp_pend_in @[el2_lsu_bus_buffer.scala 379:56] + obuf_rdrsp_pend <= _T_1770 @[el2_lsu_bus_buffer.scala 379:19] + reg _T_1771 : UInt, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 380:55] + _T_1771 <= obuf_rdrsp_tag_in @[el2_lsu_bus_buffer.scala 380:55] + obuf_rdrsp_tag <= _T_1771 @[el2_lsu_bus_buffer.scala 380:18] + reg _T_1772 : UInt, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when obuf_wr_en : @[Reg.scala 28:19] + _T_1772 <= obuf_tag0_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + obuf_tag0 <= _T_1772 @[el2_lsu_bus_buffer.scala 381:13] + reg obuf_tag1 : UInt, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when obuf_wr_en : @[Reg.scala 28:19] + obuf_tag1 <= obuf_tag1_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + reg obuf_merge : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when obuf_wr_en : @[Reg.scala 28:19] + obuf_merge <= obuf_merge_en @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + reg _T_1773 : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when obuf_wr_en : @[Reg.scala 28:19] + _T_1773 <= obuf_write_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + obuf_write <= _T_1773 @[el2_lsu_bus_buffer.scala 384:14] + reg _T_1774 : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when obuf_wr_en : @[Reg.scala 28:19] + _T_1774 <= obuf_sideeffect_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + obuf_sideeffect <= _T_1774 @[el2_lsu_bus_buffer.scala 385:19] + reg obuf_sz : UInt, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when obuf_wr_en : @[Reg.scala 28:19] + obuf_sz <= obuf_sz_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + inst rvclkhdr_2 of rvclkhdr_2 @[el2_lib.scala 472:23] + rvclkhdr_2.clock <= clock + rvclkhdr_2.reset <= reset + rvclkhdr_2.io.clk <= io.lsu_busm_clk @[el2_lib.scala 474:18] + rvclkhdr_2.io.en <= obuf_wr_en @[el2_lib.scala 475:17] + rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 476:24] + reg _T_1775 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 478:16] + _T_1775 <= obuf_addr_in @[el2_lib.scala 478:16] + obuf_addr <= _T_1775 @[el2_lsu_bus_buffer.scala 387:13] + reg obuf_byteen : UInt, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when obuf_wr_en : @[Reg.scala 28:19] + obuf_byteen <= obuf_byteen_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + inst rvclkhdr_3 of rvclkhdr_3 @[el2_lib.scala 472:23] + rvclkhdr_3.clock <= clock + rvclkhdr_3.reset <= reset + rvclkhdr_3.io.clk <= io.lsu_busm_clk @[el2_lib.scala 474:18] + rvclkhdr_3.io.en <= obuf_wr_en @[el2_lib.scala 475:17] + rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 476:24] + reg obuf_data : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 478:16] + obuf_data <= obuf_data_in @[el2_lib.scala 478:16] + reg _T_1776 : UInt, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 390:54] + _T_1776 <= obuf_wr_timer_in @[el2_lsu_bus_buffer.scala 390:54] + obuf_wr_timer <= _T_1776 @[el2_lsu_bus_buffer.scala 390:17] + wire WrPtr0_m : UInt<2> + WrPtr0_m <= UInt<1>("h00") + node _T_1777 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 392:59] + node _T_1778 = eq(ibuf_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 392:97] + node _T_1779 = and(ibuf_valid, _T_1778) @[el2_lsu_bus_buffer.scala 392:86] + node _T_1780 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 393:33] + node _T_1781 = and(io.lsu_busreq_m, _T_1780) @[el2_lsu_bus_buffer.scala 393:22] + node _T_1782 = or(_T_1779, _T_1781) @[el2_lsu_bus_buffer.scala 392:106] + node _T_1783 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 393:72] + node _T_1784 = and(io.ldst_dual_r, _T_1783) @[el2_lsu_bus_buffer.scala 393:60] + node _T_1785 = or(_T_1782, _T_1784) @[el2_lsu_bus_buffer.scala 393:42] + node _T_1786 = eq(_T_1785, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 392:72] + node _T_1787 = and(_T_1777, _T_1786) @[el2_lsu_bus_buffer.scala 392:70] + node _T_1788 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 392:59] + node _T_1789 = eq(ibuf_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 392:97] + node _T_1790 = and(ibuf_valid, _T_1789) @[el2_lsu_bus_buffer.scala 392:86] + node _T_1791 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 393:33] + node _T_1792 = and(io.lsu_busreq_m, _T_1791) @[el2_lsu_bus_buffer.scala 393:22] + node _T_1793 = or(_T_1790, _T_1792) @[el2_lsu_bus_buffer.scala 392:106] + node _T_1794 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 393:72] + node _T_1795 = and(io.ldst_dual_r, _T_1794) @[el2_lsu_bus_buffer.scala 393:60] + node _T_1796 = or(_T_1793, _T_1795) @[el2_lsu_bus_buffer.scala 393:42] + node _T_1797 = eq(_T_1796, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 392:72] + node _T_1798 = and(_T_1788, _T_1797) @[el2_lsu_bus_buffer.scala 392:70] + node _T_1799 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 392:59] + node _T_1800 = eq(ibuf_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 392:97] + node _T_1801 = and(ibuf_valid, _T_1800) @[el2_lsu_bus_buffer.scala 392:86] + node _T_1802 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 393:33] + node _T_1803 = and(io.lsu_busreq_m, _T_1802) @[el2_lsu_bus_buffer.scala 393:22] + node _T_1804 = or(_T_1801, _T_1803) @[el2_lsu_bus_buffer.scala 392:106] + node _T_1805 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 393:72] + node _T_1806 = and(io.ldst_dual_r, _T_1805) @[el2_lsu_bus_buffer.scala 393:60] + node _T_1807 = or(_T_1804, _T_1806) @[el2_lsu_bus_buffer.scala 393:42] + node _T_1808 = eq(_T_1807, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 392:72] + node _T_1809 = and(_T_1799, _T_1808) @[el2_lsu_bus_buffer.scala 392:70] + node _T_1810 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 392:59] + node _T_1811 = eq(ibuf_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 392:97] + node _T_1812 = and(ibuf_valid, _T_1811) @[el2_lsu_bus_buffer.scala 392:86] + node _T_1813 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 393:33] + node _T_1814 = and(io.lsu_busreq_m, _T_1813) @[el2_lsu_bus_buffer.scala 393:22] + node _T_1815 = or(_T_1812, _T_1814) @[el2_lsu_bus_buffer.scala 392:106] + node _T_1816 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 393:72] + node _T_1817 = and(io.ldst_dual_r, _T_1816) @[el2_lsu_bus_buffer.scala 393:60] + node _T_1818 = or(_T_1815, _T_1817) @[el2_lsu_bus_buffer.scala 393:42] + node _T_1819 = eq(_T_1818, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 392:72] + node _T_1820 = and(_T_1810, _T_1819) @[el2_lsu_bus_buffer.scala 392:70] + node _T_1821 = mux(_T_1820, UInt<2>("h03"), UInt<1>("h00")) @[Mux.scala 98:16] + node _T_1822 = mux(_T_1809, UInt<2>("h02"), _T_1821) @[Mux.scala 98:16] + node _T_1823 = mux(_T_1798, UInt<1>("h01"), _T_1822) @[Mux.scala 98:16] + node _T_1824 = mux(_T_1787, UInt<1>("h00"), _T_1823) @[Mux.scala 98:16] + WrPtr0_m <= _T_1824 @[el2_lsu_bus_buffer.scala 394:12] + node _T_1825 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 395:59] + node _T_1826 = eq(ibuf_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 395:97] + node _T_1827 = and(ibuf_valid, _T_1826) @[el2_lsu_bus_buffer.scala 395:86] + node _T_1828 = eq(WrPtr0_m, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 396:33] + node _T_1829 = and(io.lsu_busreq_m, _T_1828) @[el2_lsu_bus_buffer.scala 396:22] + node _T_1830 = or(_T_1827, _T_1829) @[el2_lsu_bus_buffer.scala 395:106] + node _T_1831 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 396:73] + node _T_1832 = and(io.lsu_busreq_r, _T_1831) @[el2_lsu_bus_buffer.scala 396:61] + node _T_1833 = or(_T_1830, _T_1832) @[el2_lsu_bus_buffer.scala 396:42] + node _T_1834 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 396:112] + node _T_1835 = and(io.ldst_dual_r, _T_1834) @[el2_lsu_bus_buffer.scala 396:101] + node _T_1836 = or(_T_1833, _T_1835) @[el2_lsu_bus_buffer.scala 396:83] + node _T_1837 = eq(_T_1836, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 395:72] + node _T_1838 = and(_T_1825, _T_1837) @[el2_lsu_bus_buffer.scala 395:70] + node _T_1839 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 395:59] + node _T_1840 = eq(ibuf_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 395:97] + node _T_1841 = and(ibuf_valid, _T_1840) @[el2_lsu_bus_buffer.scala 395:86] + node _T_1842 = eq(WrPtr0_m, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 396:33] + node _T_1843 = and(io.lsu_busreq_m, _T_1842) @[el2_lsu_bus_buffer.scala 396:22] + node _T_1844 = or(_T_1841, _T_1843) @[el2_lsu_bus_buffer.scala 395:106] + node _T_1845 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 396:73] + node _T_1846 = and(io.lsu_busreq_r, _T_1845) @[el2_lsu_bus_buffer.scala 396:61] + node _T_1847 = or(_T_1844, _T_1846) @[el2_lsu_bus_buffer.scala 396:42] + node _T_1848 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 396:112] + node _T_1849 = and(io.ldst_dual_r, _T_1848) @[el2_lsu_bus_buffer.scala 396:101] + node _T_1850 = or(_T_1847, _T_1849) @[el2_lsu_bus_buffer.scala 396:83] + node _T_1851 = eq(_T_1850, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 395:72] + node _T_1852 = and(_T_1839, _T_1851) @[el2_lsu_bus_buffer.scala 395:70] + node _T_1853 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 395:59] + node _T_1854 = eq(ibuf_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 395:97] + node _T_1855 = and(ibuf_valid, _T_1854) @[el2_lsu_bus_buffer.scala 395:86] + node _T_1856 = eq(WrPtr0_m, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 396:33] + node _T_1857 = and(io.lsu_busreq_m, _T_1856) @[el2_lsu_bus_buffer.scala 396:22] + node _T_1858 = or(_T_1855, _T_1857) @[el2_lsu_bus_buffer.scala 395:106] + node _T_1859 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 396:73] + node _T_1860 = and(io.lsu_busreq_r, _T_1859) @[el2_lsu_bus_buffer.scala 396:61] + node _T_1861 = or(_T_1858, _T_1860) @[el2_lsu_bus_buffer.scala 396:42] + node _T_1862 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 396:112] + node _T_1863 = and(io.ldst_dual_r, _T_1862) @[el2_lsu_bus_buffer.scala 396:101] + node _T_1864 = or(_T_1861, _T_1863) @[el2_lsu_bus_buffer.scala 396:83] + node _T_1865 = eq(_T_1864, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 395:72] + node _T_1866 = and(_T_1853, _T_1865) @[el2_lsu_bus_buffer.scala 395:70] + node _T_1867 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 395:59] + node _T_1868 = eq(ibuf_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 395:97] + node _T_1869 = and(ibuf_valid, _T_1868) @[el2_lsu_bus_buffer.scala 395:86] + node _T_1870 = eq(WrPtr0_m, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 396:33] + node _T_1871 = and(io.lsu_busreq_m, _T_1870) @[el2_lsu_bus_buffer.scala 396:22] + node _T_1872 = or(_T_1869, _T_1871) @[el2_lsu_bus_buffer.scala 395:106] + node _T_1873 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 396:73] + node _T_1874 = and(io.lsu_busreq_r, _T_1873) @[el2_lsu_bus_buffer.scala 396:61] + node _T_1875 = or(_T_1872, _T_1874) @[el2_lsu_bus_buffer.scala 396:42] + node _T_1876 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 396:112] + node _T_1877 = and(io.ldst_dual_r, _T_1876) @[el2_lsu_bus_buffer.scala 396:101] + node _T_1878 = or(_T_1875, _T_1877) @[el2_lsu_bus_buffer.scala 396:83] + node _T_1879 = eq(_T_1878, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 395:72] + node _T_1880 = and(_T_1867, _T_1879) @[el2_lsu_bus_buffer.scala 395:70] + node _T_1881 = mux(_T_1880, UInt<2>("h03"), UInt<1>("h00")) @[Mux.scala 98:16] + node _T_1882 = mux(_T_1866, UInt<2>("h02"), _T_1881) @[Mux.scala 98:16] + node _T_1883 = mux(_T_1852, UInt<1>("h01"), _T_1882) @[Mux.scala 98:16] + node WrPtr1_m = mux(_T_1838, UInt<1>("h00"), _T_1883) @[Mux.scala 98:16] + wire buf_age : UInt<4>[4] @[el2_lsu_bus_buffer.scala 398:21] + buf_age[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 399:11] + buf_age[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 399:11] + buf_age[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 399:11] + buf_age[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 399:11] + node _T_1884 = orr(buf_age[0]) @[el2_lsu_bus_buffer.scala 400:58] + node _T_1885 = eq(_T_1884, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 400:45] + node _T_1886 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 400:78] + node _T_1887 = and(_T_1885, _T_1886) @[el2_lsu_bus_buffer.scala 400:63] + node _T_1888 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 400:90] + node _T_1889 = and(_T_1887, _T_1888) @[el2_lsu_bus_buffer.scala 400:88] + node _T_1890 = orr(buf_age[1]) @[el2_lsu_bus_buffer.scala 400:58] + node _T_1891 = eq(_T_1890, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 400:45] + node _T_1892 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 400:78] + node _T_1893 = and(_T_1891, _T_1892) @[el2_lsu_bus_buffer.scala 400:63] + node _T_1894 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 400:90] + node _T_1895 = and(_T_1893, _T_1894) @[el2_lsu_bus_buffer.scala 400:88] + node _T_1896 = orr(buf_age[2]) @[el2_lsu_bus_buffer.scala 400:58] + node _T_1897 = eq(_T_1896, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 400:45] + node _T_1898 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 400:78] + node _T_1899 = and(_T_1897, _T_1898) @[el2_lsu_bus_buffer.scala 400:63] + node _T_1900 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 400:90] + node _T_1901 = and(_T_1899, _T_1900) @[el2_lsu_bus_buffer.scala 400:88] + node _T_1902 = orr(buf_age[3]) @[el2_lsu_bus_buffer.scala 400:58] + node _T_1903 = eq(_T_1902, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 400:45] + node _T_1904 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 400:78] + node _T_1905 = and(_T_1903, _T_1904) @[el2_lsu_bus_buffer.scala 400:63] + node _T_1906 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 400:90] + node _T_1907 = and(_T_1905, _T_1906) @[el2_lsu_bus_buffer.scala 400:88] + node _T_1908 = cat(_T_1907, _T_1901) @[Cat.scala 29:58] + node _T_1909 = cat(_T_1908, _T_1895) @[Cat.scala 29:58] + node CmdPtr0Dec = cat(_T_1909, _T_1889) @[Cat.scala 29:58] + node _T_1910 = not(CmdPtr0Dec) @[el2_lsu_bus_buffer.scala 401:62] + node _T_1911 = and(buf_age[0], _T_1910) @[el2_lsu_bus_buffer.scala 401:59] + node _T_1912 = orr(_T_1911) @[el2_lsu_bus_buffer.scala 401:76] + node _T_1913 = eq(_T_1912, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 401:45] + node _T_1914 = bits(CmdPtr0Dec, 0, 0) @[el2_lsu_bus_buffer.scala 401:94] + node _T_1915 = eq(_T_1914, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 401:83] + node _T_1916 = and(_T_1913, _T_1915) @[el2_lsu_bus_buffer.scala 401:81] + node _T_1917 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 401:113] + node _T_1918 = and(_T_1916, _T_1917) @[el2_lsu_bus_buffer.scala 401:98] + node _T_1919 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 401:125] + node _T_1920 = and(_T_1918, _T_1919) @[el2_lsu_bus_buffer.scala 401:123] + node _T_1921 = not(CmdPtr0Dec) @[el2_lsu_bus_buffer.scala 401:62] + node _T_1922 = and(buf_age[1], _T_1921) @[el2_lsu_bus_buffer.scala 401:59] + node _T_1923 = orr(_T_1922) @[el2_lsu_bus_buffer.scala 401:76] + node _T_1924 = eq(_T_1923, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 401:45] + node _T_1925 = bits(CmdPtr0Dec, 1, 1) @[el2_lsu_bus_buffer.scala 401:94] + node _T_1926 = eq(_T_1925, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 401:83] + node _T_1927 = and(_T_1924, _T_1926) @[el2_lsu_bus_buffer.scala 401:81] + node _T_1928 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 401:113] + node _T_1929 = and(_T_1927, _T_1928) @[el2_lsu_bus_buffer.scala 401:98] + node _T_1930 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 401:125] + node _T_1931 = and(_T_1929, _T_1930) @[el2_lsu_bus_buffer.scala 401:123] + node _T_1932 = not(CmdPtr0Dec) @[el2_lsu_bus_buffer.scala 401:62] + node _T_1933 = and(buf_age[2], _T_1932) @[el2_lsu_bus_buffer.scala 401:59] + node _T_1934 = orr(_T_1933) @[el2_lsu_bus_buffer.scala 401:76] + node _T_1935 = eq(_T_1934, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 401:45] + node _T_1936 = bits(CmdPtr0Dec, 2, 2) @[el2_lsu_bus_buffer.scala 401:94] + node _T_1937 = eq(_T_1936, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 401:83] + node _T_1938 = and(_T_1935, _T_1937) @[el2_lsu_bus_buffer.scala 401:81] + node _T_1939 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 401:113] + node _T_1940 = and(_T_1938, _T_1939) @[el2_lsu_bus_buffer.scala 401:98] + node _T_1941 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 401:125] + node _T_1942 = and(_T_1940, _T_1941) @[el2_lsu_bus_buffer.scala 401:123] + node _T_1943 = not(CmdPtr0Dec) @[el2_lsu_bus_buffer.scala 401:62] + node _T_1944 = and(buf_age[3], _T_1943) @[el2_lsu_bus_buffer.scala 401:59] + node _T_1945 = orr(_T_1944) @[el2_lsu_bus_buffer.scala 401:76] + node _T_1946 = eq(_T_1945, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 401:45] + node _T_1947 = bits(CmdPtr0Dec, 3, 3) @[el2_lsu_bus_buffer.scala 401:94] + node _T_1948 = eq(_T_1947, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 401:83] + node _T_1949 = and(_T_1946, _T_1948) @[el2_lsu_bus_buffer.scala 401:81] + node _T_1950 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 401:113] + node _T_1951 = and(_T_1949, _T_1950) @[el2_lsu_bus_buffer.scala 401:98] + node _T_1952 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 401:125] + node _T_1953 = and(_T_1951, _T_1952) @[el2_lsu_bus_buffer.scala 401:123] + node _T_1954 = cat(_T_1953, _T_1942) @[Cat.scala 29:58] + node _T_1955 = cat(_T_1954, _T_1931) @[Cat.scala 29:58] + node CmdPtr1Dec = cat(_T_1955, _T_1920) @[Cat.scala 29:58] + wire buf_rsp_pickage : UInt<4>[4] @[el2_lsu_bus_buffer.scala 402:29] + buf_rsp_pickage[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 403:19] + buf_rsp_pickage[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 403:19] + buf_rsp_pickage[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 403:19] + buf_rsp_pickage[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 403:19] + node _T_1956 = orr(buf_rsp_pickage[0]) @[el2_lsu_bus_buffer.scala 404:65] + node _T_1957 = eq(_T_1956, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 404:44] + node _T_1958 = eq(buf_state[0], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 404:85] + node _T_1959 = and(_T_1957, _T_1958) @[el2_lsu_bus_buffer.scala 404:70] + node _T_1960 = orr(buf_rsp_pickage[1]) @[el2_lsu_bus_buffer.scala 404:65] + node _T_1961 = eq(_T_1960, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 404:44] + node _T_1962 = eq(buf_state[1], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 404:85] + node _T_1963 = and(_T_1961, _T_1962) @[el2_lsu_bus_buffer.scala 404:70] + node _T_1964 = orr(buf_rsp_pickage[2]) @[el2_lsu_bus_buffer.scala 404:65] + node _T_1965 = eq(_T_1964, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 404:44] + node _T_1966 = eq(buf_state[2], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 404:85] + node _T_1967 = and(_T_1965, _T_1966) @[el2_lsu_bus_buffer.scala 404:70] + node _T_1968 = orr(buf_rsp_pickage[3]) @[el2_lsu_bus_buffer.scala 404:65] + node _T_1969 = eq(_T_1968, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 404:44] + node _T_1970 = eq(buf_state[3], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 404:85] + node _T_1971 = and(_T_1969, _T_1970) @[el2_lsu_bus_buffer.scala 404:70] + node _T_1972 = cat(_T_1971, _T_1967) @[Cat.scala 29:58] + node _T_1973 = cat(_T_1972, _T_1963) @[Cat.scala 29:58] + node RspPtrDec = cat(_T_1973, _T_1959) @[Cat.scala 29:58] + node _T_1974 = orr(CmdPtr0Dec) @[el2_lsu_bus_buffer.scala 405:31] + found_cmdptr0 <= _T_1974 @[el2_lsu_bus_buffer.scala 405:17] + node _T_1975 = orr(CmdPtr1Dec) @[el2_lsu_bus_buffer.scala 406:31] + found_cmdptr1 <= _T_1975 @[el2_lsu_bus_buffer.scala 406:17] + node _T_1976 = bits(CmdPtr0Dec, 0, 0) @[OneHot.scala 47:40] + node _T_1977 = bits(CmdPtr0Dec, 1, 1) @[OneHot.scala 47:40] + node _T_1978 = bits(CmdPtr0Dec, 2, 2) @[OneHot.scala 47:40] + node _T_1979 = bits(CmdPtr0Dec, 3, 3) @[OneHot.scala 47:40] + node _T_1980 = mux(_T_1978, UInt<2>("h02"), UInt<2>("h03")) @[Mux.scala 47:69] + node _T_1981 = mux(_T_1977, UInt<1>("h01"), _T_1980) @[Mux.scala 47:69] + node CmdPtr0 = mux(_T_1976, UInt<1>("h00"), _T_1981) @[Mux.scala 47:69] + node _T_1982 = bits(CmdPtr1Dec, 0, 0) @[OneHot.scala 47:40] + node _T_1983 = bits(CmdPtr1Dec, 1, 1) @[OneHot.scala 47:40] + node _T_1984 = bits(CmdPtr1Dec, 2, 2) @[OneHot.scala 47:40] + node _T_1985 = bits(CmdPtr1Dec, 3, 3) @[OneHot.scala 47:40] + node _T_1986 = mux(_T_1984, UInt<2>("h02"), UInt<2>("h03")) @[Mux.scala 47:69] + node _T_1987 = mux(_T_1983, UInt<1>("h01"), _T_1986) @[Mux.scala 47:69] + node CmdPtr1 = mux(_T_1982, UInt<1>("h00"), _T_1987) @[Mux.scala 47:69] + node _T_1988 = bits(RspPtrDec, 0, 0) @[OneHot.scala 47:40] + node _T_1989 = bits(RspPtrDec, 1, 1) @[OneHot.scala 47:40] + node _T_1990 = bits(RspPtrDec, 2, 2) @[OneHot.scala 47:40] + node _T_1991 = bits(RspPtrDec, 3, 3) @[OneHot.scala 47:40] + node _T_1992 = mux(_T_1990, UInt<2>("h02"), UInt<2>("h03")) @[Mux.scala 47:69] + node _T_1993 = mux(_T_1989, UInt<1>("h01"), _T_1992) @[Mux.scala 47:69] + node RspPtr = mux(_T_1988, UInt<1>("h00"), _T_1993) @[Mux.scala 47:69] + wire buf_state_en : UInt<1>[4] @[el2_lsu_bus_buffer.scala 411:26] + buf_state_en[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 412:16] + buf_state_en[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 412:16] + buf_state_en[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 412:16] + buf_state_en[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 412:16] + wire buf_rspageQ : UInt<4>[4] @[el2_lsu_bus_buffer.scala 413:25] + buf_rspageQ[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 414:15] + buf_rspageQ[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 414:15] + buf_rspageQ[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 414:15] + buf_rspageQ[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 414:15] + wire buf_rspage_set : UInt<4>[4] @[el2_lsu_bus_buffer.scala 415:28] + buf_rspage_set[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 416:18] + buf_rspage_set[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 416:18] + buf_rspage_set[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 416:18] + buf_rspage_set[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 416:18] + wire buf_rspage_in : UInt<4>[4] @[el2_lsu_bus_buffer.scala 417:27] + buf_rspage_in[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 418:17] + buf_rspage_in[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 418:17] + buf_rspage_in[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 418:17] + buf_rspage_in[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 418:17] + wire buf_rspage : UInt<4>[4] @[el2_lsu_bus_buffer.scala 419:24] + buf_rspage[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 420:14] + buf_rspage[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 420:14] + buf_rspage[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 420:14] + buf_rspage[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 420:14] + node _T_1994 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 422:83] + node _T_1995 = and(_T_1994, buf_state_en[0]) @[el2_lsu_bus_buffer.scala 422:94] + node _T_1996 = eq(buf_state[0], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 423:20] + node _T_1997 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 423:47] + node _T_1998 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 423:59] + node _T_1999 = and(_T_1997, _T_1998) @[el2_lsu_bus_buffer.scala 423:57] + node _T_2000 = or(_T_1996, _T_1999) @[el2_lsu_bus_buffer.scala 423:31] + node _T_2001 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 424:23] + node _T_2002 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 424:53] + node _T_2003 = and(_T_2001, _T_2002) @[el2_lsu_bus_buffer.scala 424:41] + node _T_2004 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 424:83] + node _T_2005 = and(_T_2003, _T_2004) @[el2_lsu_bus_buffer.scala 424:71] + node _T_2006 = eq(ibuf_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 424:104] + node _T_2007 = and(_T_2005, _T_2006) @[el2_lsu_bus_buffer.scala 424:92] + node _T_2008 = or(_T_2000, _T_2007) @[el2_lsu_bus_buffer.scala 423:86] + node _T_2009 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 425:17] + node _T_2010 = and(_T_2009, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 425:35] + node _T_2011 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 425:64] + node _T_2012 = and(_T_2010, _T_2011) @[el2_lsu_bus_buffer.scala 425:52] + node _T_2013 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 425:85] + node _T_2014 = and(_T_2012, _T_2013) @[el2_lsu_bus_buffer.scala 425:73] + node _T_2015 = or(_T_2008, _T_2014) @[el2_lsu_bus_buffer.scala 424:114] + node _T_2016 = and(_T_1995, _T_2015) @[el2_lsu_bus_buffer.scala 422:113] + node _T_2017 = bits(buf_age[0], 0, 0) @[el2_lsu_bus_buffer.scala 425:109] + node _T_2018 = or(_T_2016, _T_2017) @[el2_lsu_bus_buffer.scala 425:97] + node _T_2019 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 422:83] + node _T_2020 = and(_T_2019, buf_state_en[0]) @[el2_lsu_bus_buffer.scala 422:94] + node _T_2021 = eq(buf_state[1], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 423:20] + node _T_2022 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 423:47] + node _T_2023 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 423:59] + node _T_2024 = and(_T_2022, _T_2023) @[el2_lsu_bus_buffer.scala 423:57] + node _T_2025 = or(_T_2021, _T_2024) @[el2_lsu_bus_buffer.scala 423:31] + node _T_2026 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 424:23] + node _T_2027 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 424:53] + node _T_2028 = and(_T_2026, _T_2027) @[el2_lsu_bus_buffer.scala 424:41] + node _T_2029 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 424:83] + node _T_2030 = and(_T_2028, _T_2029) @[el2_lsu_bus_buffer.scala 424:71] + node _T_2031 = eq(ibuf_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 424:104] + node _T_2032 = and(_T_2030, _T_2031) @[el2_lsu_bus_buffer.scala 424:92] + node _T_2033 = or(_T_2025, _T_2032) @[el2_lsu_bus_buffer.scala 423:86] + node _T_2034 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 425:17] + node _T_2035 = and(_T_2034, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 425:35] + node _T_2036 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 425:64] + node _T_2037 = and(_T_2035, _T_2036) @[el2_lsu_bus_buffer.scala 425:52] + node _T_2038 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 425:85] + node _T_2039 = and(_T_2037, _T_2038) @[el2_lsu_bus_buffer.scala 425:73] + node _T_2040 = or(_T_2033, _T_2039) @[el2_lsu_bus_buffer.scala 424:114] + node _T_2041 = and(_T_2020, _T_2040) @[el2_lsu_bus_buffer.scala 422:113] + node _T_2042 = bits(buf_age[0], 1, 1) @[el2_lsu_bus_buffer.scala 425:109] + node _T_2043 = or(_T_2041, _T_2042) @[el2_lsu_bus_buffer.scala 425:97] + node _T_2044 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 422:83] + node _T_2045 = and(_T_2044, buf_state_en[0]) @[el2_lsu_bus_buffer.scala 422:94] + node _T_2046 = eq(buf_state[2], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 423:20] + node _T_2047 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 423:47] + node _T_2048 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 423:59] + node _T_2049 = and(_T_2047, _T_2048) @[el2_lsu_bus_buffer.scala 423:57] + node _T_2050 = or(_T_2046, _T_2049) @[el2_lsu_bus_buffer.scala 423:31] + node _T_2051 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 424:23] + node _T_2052 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 424:53] + node _T_2053 = and(_T_2051, _T_2052) @[el2_lsu_bus_buffer.scala 424:41] + node _T_2054 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 424:83] + node _T_2055 = and(_T_2053, _T_2054) @[el2_lsu_bus_buffer.scala 424:71] + node _T_2056 = eq(ibuf_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 424:104] + node _T_2057 = and(_T_2055, _T_2056) @[el2_lsu_bus_buffer.scala 424:92] + node _T_2058 = or(_T_2050, _T_2057) @[el2_lsu_bus_buffer.scala 423:86] + node _T_2059 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 425:17] + node _T_2060 = and(_T_2059, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 425:35] + node _T_2061 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 425:64] + node _T_2062 = and(_T_2060, _T_2061) @[el2_lsu_bus_buffer.scala 425:52] + node _T_2063 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 425:85] + node _T_2064 = and(_T_2062, _T_2063) @[el2_lsu_bus_buffer.scala 425:73] + node _T_2065 = or(_T_2058, _T_2064) @[el2_lsu_bus_buffer.scala 424:114] + node _T_2066 = and(_T_2045, _T_2065) @[el2_lsu_bus_buffer.scala 422:113] + node _T_2067 = bits(buf_age[0], 2, 2) @[el2_lsu_bus_buffer.scala 425:109] + node _T_2068 = or(_T_2066, _T_2067) @[el2_lsu_bus_buffer.scala 425:97] + node _T_2069 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 422:83] + node _T_2070 = and(_T_2069, buf_state_en[0]) @[el2_lsu_bus_buffer.scala 422:94] + node _T_2071 = eq(buf_state[3], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 423:20] + node _T_2072 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 423:47] + node _T_2073 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 423:59] + node _T_2074 = and(_T_2072, _T_2073) @[el2_lsu_bus_buffer.scala 423:57] + node _T_2075 = or(_T_2071, _T_2074) @[el2_lsu_bus_buffer.scala 423:31] + node _T_2076 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 424:23] + node _T_2077 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 424:53] + node _T_2078 = and(_T_2076, _T_2077) @[el2_lsu_bus_buffer.scala 424:41] + node _T_2079 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 424:83] + node _T_2080 = and(_T_2078, _T_2079) @[el2_lsu_bus_buffer.scala 424:71] + node _T_2081 = eq(ibuf_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 424:104] + node _T_2082 = and(_T_2080, _T_2081) @[el2_lsu_bus_buffer.scala 424:92] + node _T_2083 = or(_T_2075, _T_2082) @[el2_lsu_bus_buffer.scala 423:86] + node _T_2084 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 425:17] + node _T_2085 = and(_T_2084, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 425:35] + node _T_2086 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 425:64] + node _T_2087 = and(_T_2085, _T_2086) @[el2_lsu_bus_buffer.scala 425:52] + node _T_2088 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 425:85] + node _T_2089 = and(_T_2087, _T_2088) @[el2_lsu_bus_buffer.scala 425:73] + node _T_2090 = or(_T_2083, _T_2089) @[el2_lsu_bus_buffer.scala 424:114] + node _T_2091 = and(_T_2070, _T_2090) @[el2_lsu_bus_buffer.scala 422:113] + node _T_2092 = bits(buf_age[0], 3, 3) @[el2_lsu_bus_buffer.scala 425:109] + node _T_2093 = or(_T_2091, _T_2092) @[el2_lsu_bus_buffer.scala 425:97] + node _T_2094 = cat(_T_2093, _T_2068) @[Cat.scala 29:58] + node _T_2095 = cat(_T_2094, _T_2043) @[Cat.scala 29:58] + node buf_age_in_0 = cat(_T_2095, _T_2018) @[Cat.scala 29:58] + node _T_2096 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 422:83] + node _T_2097 = and(_T_2096, buf_state_en[1]) @[el2_lsu_bus_buffer.scala 422:94] + node _T_2098 = eq(buf_state[0], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 423:20] + node _T_2099 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 423:47] + node _T_2100 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 423:59] + node _T_2101 = and(_T_2099, _T_2100) @[el2_lsu_bus_buffer.scala 423:57] + node _T_2102 = or(_T_2098, _T_2101) @[el2_lsu_bus_buffer.scala 423:31] + node _T_2103 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 424:23] + node _T_2104 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 424:53] + node _T_2105 = and(_T_2103, _T_2104) @[el2_lsu_bus_buffer.scala 424:41] + node _T_2106 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 424:83] + node _T_2107 = and(_T_2105, _T_2106) @[el2_lsu_bus_buffer.scala 424:71] + node _T_2108 = eq(ibuf_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 424:104] + node _T_2109 = and(_T_2107, _T_2108) @[el2_lsu_bus_buffer.scala 424:92] + node _T_2110 = or(_T_2102, _T_2109) @[el2_lsu_bus_buffer.scala 423:86] + node _T_2111 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 425:17] + node _T_2112 = and(_T_2111, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 425:35] + node _T_2113 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 425:64] + node _T_2114 = and(_T_2112, _T_2113) @[el2_lsu_bus_buffer.scala 425:52] + node _T_2115 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 425:85] + node _T_2116 = and(_T_2114, _T_2115) @[el2_lsu_bus_buffer.scala 425:73] + node _T_2117 = or(_T_2110, _T_2116) @[el2_lsu_bus_buffer.scala 424:114] + node _T_2118 = and(_T_2097, _T_2117) @[el2_lsu_bus_buffer.scala 422:113] + node _T_2119 = bits(buf_age[1], 0, 0) @[el2_lsu_bus_buffer.scala 425:109] + node _T_2120 = or(_T_2118, _T_2119) @[el2_lsu_bus_buffer.scala 425:97] + node _T_2121 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 422:83] + node _T_2122 = and(_T_2121, buf_state_en[1]) @[el2_lsu_bus_buffer.scala 422:94] + node _T_2123 = eq(buf_state[1], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 423:20] + node _T_2124 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 423:47] + node _T_2125 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 423:59] + node _T_2126 = and(_T_2124, _T_2125) @[el2_lsu_bus_buffer.scala 423:57] + node _T_2127 = or(_T_2123, _T_2126) @[el2_lsu_bus_buffer.scala 423:31] + node _T_2128 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 424:23] + node _T_2129 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 424:53] + node _T_2130 = and(_T_2128, _T_2129) @[el2_lsu_bus_buffer.scala 424:41] + node _T_2131 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 424:83] + node _T_2132 = and(_T_2130, _T_2131) @[el2_lsu_bus_buffer.scala 424:71] + node _T_2133 = eq(ibuf_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 424:104] + node _T_2134 = and(_T_2132, _T_2133) @[el2_lsu_bus_buffer.scala 424:92] + node _T_2135 = or(_T_2127, _T_2134) @[el2_lsu_bus_buffer.scala 423:86] + node _T_2136 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 425:17] + node _T_2137 = and(_T_2136, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 425:35] + node _T_2138 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 425:64] + node _T_2139 = and(_T_2137, _T_2138) @[el2_lsu_bus_buffer.scala 425:52] + node _T_2140 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 425:85] + node _T_2141 = and(_T_2139, _T_2140) @[el2_lsu_bus_buffer.scala 425:73] + node _T_2142 = or(_T_2135, _T_2141) @[el2_lsu_bus_buffer.scala 424:114] + node _T_2143 = and(_T_2122, _T_2142) @[el2_lsu_bus_buffer.scala 422:113] + node _T_2144 = bits(buf_age[1], 1, 1) @[el2_lsu_bus_buffer.scala 425:109] + node _T_2145 = or(_T_2143, _T_2144) @[el2_lsu_bus_buffer.scala 425:97] + node _T_2146 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 422:83] + node _T_2147 = and(_T_2146, buf_state_en[1]) @[el2_lsu_bus_buffer.scala 422:94] + node _T_2148 = eq(buf_state[2], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 423:20] + node _T_2149 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 423:47] + node _T_2150 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 423:59] + node _T_2151 = and(_T_2149, _T_2150) @[el2_lsu_bus_buffer.scala 423:57] + node _T_2152 = or(_T_2148, _T_2151) @[el2_lsu_bus_buffer.scala 423:31] + node _T_2153 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 424:23] + node _T_2154 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 424:53] + node _T_2155 = and(_T_2153, _T_2154) @[el2_lsu_bus_buffer.scala 424:41] + node _T_2156 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 424:83] + node _T_2157 = and(_T_2155, _T_2156) @[el2_lsu_bus_buffer.scala 424:71] + node _T_2158 = eq(ibuf_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 424:104] + node _T_2159 = and(_T_2157, _T_2158) @[el2_lsu_bus_buffer.scala 424:92] + node _T_2160 = or(_T_2152, _T_2159) @[el2_lsu_bus_buffer.scala 423:86] + node _T_2161 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 425:17] + node _T_2162 = and(_T_2161, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 425:35] + node _T_2163 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 425:64] + node _T_2164 = and(_T_2162, _T_2163) @[el2_lsu_bus_buffer.scala 425:52] + node _T_2165 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 425:85] + node _T_2166 = and(_T_2164, _T_2165) @[el2_lsu_bus_buffer.scala 425:73] + node _T_2167 = or(_T_2160, _T_2166) @[el2_lsu_bus_buffer.scala 424:114] + node _T_2168 = and(_T_2147, _T_2167) @[el2_lsu_bus_buffer.scala 422:113] + node _T_2169 = bits(buf_age[1], 2, 2) @[el2_lsu_bus_buffer.scala 425:109] + node _T_2170 = or(_T_2168, _T_2169) @[el2_lsu_bus_buffer.scala 425:97] + node _T_2171 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 422:83] + node _T_2172 = and(_T_2171, buf_state_en[1]) @[el2_lsu_bus_buffer.scala 422:94] + node _T_2173 = eq(buf_state[3], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 423:20] + node _T_2174 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 423:47] + node _T_2175 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 423:59] + node _T_2176 = and(_T_2174, _T_2175) @[el2_lsu_bus_buffer.scala 423:57] + node _T_2177 = or(_T_2173, _T_2176) @[el2_lsu_bus_buffer.scala 423:31] + node _T_2178 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 424:23] + node _T_2179 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 424:53] + node _T_2180 = and(_T_2178, _T_2179) @[el2_lsu_bus_buffer.scala 424:41] + node _T_2181 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 424:83] + node _T_2182 = and(_T_2180, _T_2181) @[el2_lsu_bus_buffer.scala 424:71] + node _T_2183 = eq(ibuf_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 424:104] + node _T_2184 = and(_T_2182, _T_2183) @[el2_lsu_bus_buffer.scala 424:92] + node _T_2185 = or(_T_2177, _T_2184) @[el2_lsu_bus_buffer.scala 423:86] + node _T_2186 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 425:17] + node _T_2187 = and(_T_2186, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 425:35] + node _T_2188 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 425:64] + node _T_2189 = and(_T_2187, _T_2188) @[el2_lsu_bus_buffer.scala 425:52] + node _T_2190 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 425:85] + node _T_2191 = and(_T_2189, _T_2190) @[el2_lsu_bus_buffer.scala 425:73] + node _T_2192 = or(_T_2185, _T_2191) @[el2_lsu_bus_buffer.scala 424:114] + node _T_2193 = and(_T_2172, _T_2192) @[el2_lsu_bus_buffer.scala 422:113] + node _T_2194 = bits(buf_age[1], 3, 3) @[el2_lsu_bus_buffer.scala 425:109] + node _T_2195 = or(_T_2193, _T_2194) @[el2_lsu_bus_buffer.scala 425:97] + node _T_2196 = cat(_T_2195, _T_2170) @[Cat.scala 29:58] + node _T_2197 = cat(_T_2196, _T_2145) @[Cat.scala 29:58] + node buf_age_in_1 = cat(_T_2197, _T_2120) @[Cat.scala 29:58] + node _T_2198 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 422:83] + node _T_2199 = and(_T_2198, buf_state_en[2]) @[el2_lsu_bus_buffer.scala 422:94] + node _T_2200 = eq(buf_state[0], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 423:20] + node _T_2201 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 423:47] + node _T_2202 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 423:59] + node _T_2203 = and(_T_2201, _T_2202) @[el2_lsu_bus_buffer.scala 423:57] + node _T_2204 = or(_T_2200, _T_2203) @[el2_lsu_bus_buffer.scala 423:31] + node _T_2205 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 424:23] + node _T_2206 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 424:53] + node _T_2207 = and(_T_2205, _T_2206) @[el2_lsu_bus_buffer.scala 424:41] + node _T_2208 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 424:83] + node _T_2209 = and(_T_2207, _T_2208) @[el2_lsu_bus_buffer.scala 424:71] + node _T_2210 = eq(ibuf_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 424:104] + node _T_2211 = and(_T_2209, _T_2210) @[el2_lsu_bus_buffer.scala 424:92] + node _T_2212 = or(_T_2204, _T_2211) @[el2_lsu_bus_buffer.scala 423:86] + node _T_2213 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 425:17] + node _T_2214 = and(_T_2213, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 425:35] + node _T_2215 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 425:64] + node _T_2216 = and(_T_2214, _T_2215) @[el2_lsu_bus_buffer.scala 425:52] + node _T_2217 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 425:85] + node _T_2218 = and(_T_2216, _T_2217) @[el2_lsu_bus_buffer.scala 425:73] + node _T_2219 = or(_T_2212, _T_2218) @[el2_lsu_bus_buffer.scala 424:114] + node _T_2220 = and(_T_2199, _T_2219) @[el2_lsu_bus_buffer.scala 422:113] + node _T_2221 = bits(buf_age[2], 0, 0) @[el2_lsu_bus_buffer.scala 425:109] + node _T_2222 = or(_T_2220, _T_2221) @[el2_lsu_bus_buffer.scala 425:97] + node _T_2223 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 422:83] + node _T_2224 = and(_T_2223, buf_state_en[2]) @[el2_lsu_bus_buffer.scala 422:94] + node _T_2225 = eq(buf_state[1], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 423:20] + node _T_2226 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 423:47] + node _T_2227 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 423:59] + node _T_2228 = and(_T_2226, _T_2227) @[el2_lsu_bus_buffer.scala 423:57] + node _T_2229 = or(_T_2225, _T_2228) @[el2_lsu_bus_buffer.scala 423:31] + node _T_2230 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 424:23] + node _T_2231 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 424:53] + node _T_2232 = and(_T_2230, _T_2231) @[el2_lsu_bus_buffer.scala 424:41] + node _T_2233 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 424:83] + node _T_2234 = and(_T_2232, _T_2233) @[el2_lsu_bus_buffer.scala 424:71] + node _T_2235 = eq(ibuf_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 424:104] + node _T_2236 = and(_T_2234, _T_2235) @[el2_lsu_bus_buffer.scala 424:92] + node _T_2237 = or(_T_2229, _T_2236) @[el2_lsu_bus_buffer.scala 423:86] + node _T_2238 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 425:17] + node _T_2239 = and(_T_2238, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 425:35] + node _T_2240 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 425:64] + node _T_2241 = and(_T_2239, _T_2240) @[el2_lsu_bus_buffer.scala 425:52] + node _T_2242 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 425:85] + node _T_2243 = and(_T_2241, _T_2242) @[el2_lsu_bus_buffer.scala 425:73] + node _T_2244 = or(_T_2237, _T_2243) @[el2_lsu_bus_buffer.scala 424:114] + node _T_2245 = and(_T_2224, _T_2244) @[el2_lsu_bus_buffer.scala 422:113] + node _T_2246 = bits(buf_age[2], 1, 1) @[el2_lsu_bus_buffer.scala 425:109] + node _T_2247 = or(_T_2245, _T_2246) @[el2_lsu_bus_buffer.scala 425:97] + node _T_2248 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 422:83] + node _T_2249 = and(_T_2248, buf_state_en[2]) @[el2_lsu_bus_buffer.scala 422:94] + node _T_2250 = eq(buf_state[2], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 423:20] + node _T_2251 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 423:47] + node _T_2252 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 423:59] + node _T_2253 = and(_T_2251, _T_2252) @[el2_lsu_bus_buffer.scala 423:57] + node _T_2254 = or(_T_2250, _T_2253) @[el2_lsu_bus_buffer.scala 423:31] + node _T_2255 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 424:23] + node _T_2256 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 424:53] + node _T_2257 = and(_T_2255, _T_2256) @[el2_lsu_bus_buffer.scala 424:41] + node _T_2258 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 424:83] + node _T_2259 = and(_T_2257, _T_2258) @[el2_lsu_bus_buffer.scala 424:71] + node _T_2260 = eq(ibuf_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 424:104] + node _T_2261 = and(_T_2259, _T_2260) @[el2_lsu_bus_buffer.scala 424:92] + node _T_2262 = or(_T_2254, _T_2261) @[el2_lsu_bus_buffer.scala 423:86] + node _T_2263 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 425:17] + node _T_2264 = and(_T_2263, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 425:35] + node _T_2265 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 425:64] + node _T_2266 = and(_T_2264, _T_2265) @[el2_lsu_bus_buffer.scala 425:52] + node _T_2267 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 425:85] + node _T_2268 = and(_T_2266, _T_2267) @[el2_lsu_bus_buffer.scala 425:73] + node _T_2269 = or(_T_2262, _T_2268) @[el2_lsu_bus_buffer.scala 424:114] + node _T_2270 = and(_T_2249, _T_2269) @[el2_lsu_bus_buffer.scala 422:113] + node _T_2271 = bits(buf_age[2], 2, 2) @[el2_lsu_bus_buffer.scala 425:109] + node _T_2272 = or(_T_2270, _T_2271) @[el2_lsu_bus_buffer.scala 425:97] + node _T_2273 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 422:83] + node _T_2274 = and(_T_2273, buf_state_en[2]) @[el2_lsu_bus_buffer.scala 422:94] + node _T_2275 = eq(buf_state[3], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 423:20] + node _T_2276 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 423:47] + node _T_2277 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 423:59] + node _T_2278 = and(_T_2276, _T_2277) @[el2_lsu_bus_buffer.scala 423:57] + node _T_2279 = or(_T_2275, _T_2278) @[el2_lsu_bus_buffer.scala 423:31] + node _T_2280 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 424:23] + node _T_2281 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 424:53] + node _T_2282 = and(_T_2280, _T_2281) @[el2_lsu_bus_buffer.scala 424:41] + node _T_2283 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 424:83] + node _T_2284 = and(_T_2282, _T_2283) @[el2_lsu_bus_buffer.scala 424:71] + node _T_2285 = eq(ibuf_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 424:104] + node _T_2286 = and(_T_2284, _T_2285) @[el2_lsu_bus_buffer.scala 424:92] + node _T_2287 = or(_T_2279, _T_2286) @[el2_lsu_bus_buffer.scala 423:86] + node _T_2288 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 425:17] + node _T_2289 = and(_T_2288, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 425:35] + node _T_2290 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 425:64] + node _T_2291 = and(_T_2289, _T_2290) @[el2_lsu_bus_buffer.scala 425:52] + node _T_2292 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 425:85] + node _T_2293 = and(_T_2291, _T_2292) @[el2_lsu_bus_buffer.scala 425:73] + node _T_2294 = or(_T_2287, _T_2293) @[el2_lsu_bus_buffer.scala 424:114] + node _T_2295 = and(_T_2274, _T_2294) @[el2_lsu_bus_buffer.scala 422:113] + node _T_2296 = bits(buf_age[2], 3, 3) @[el2_lsu_bus_buffer.scala 425:109] + node _T_2297 = or(_T_2295, _T_2296) @[el2_lsu_bus_buffer.scala 425:97] + node _T_2298 = cat(_T_2297, _T_2272) @[Cat.scala 29:58] + node _T_2299 = cat(_T_2298, _T_2247) @[Cat.scala 29:58] + node buf_age_in_2 = cat(_T_2299, _T_2222) @[Cat.scala 29:58] + node _T_2300 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 422:83] + node _T_2301 = and(_T_2300, buf_state_en[3]) @[el2_lsu_bus_buffer.scala 422:94] + node _T_2302 = eq(buf_state[0], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 423:20] + node _T_2303 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 423:47] + node _T_2304 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 423:59] + node _T_2305 = and(_T_2303, _T_2304) @[el2_lsu_bus_buffer.scala 423:57] + node _T_2306 = or(_T_2302, _T_2305) @[el2_lsu_bus_buffer.scala 423:31] + node _T_2307 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 424:23] + node _T_2308 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 424:53] + node _T_2309 = and(_T_2307, _T_2308) @[el2_lsu_bus_buffer.scala 424:41] + node _T_2310 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 424:83] + node _T_2311 = and(_T_2309, _T_2310) @[el2_lsu_bus_buffer.scala 424:71] + node _T_2312 = eq(ibuf_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 424:104] + node _T_2313 = and(_T_2311, _T_2312) @[el2_lsu_bus_buffer.scala 424:92] + node _T_2314 = or(_T_2306, _T_2313) @[el2_lsu_bus_buffer.scala 423:86] + node _T_2315 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 425:17] + node _T_2316 = and(_T_2315, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 425:35] + node _T_2317 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 425:64] + node _T_2318 = and(_T_2316, _T_2317) @[el2_lsu_bus_buffer.scala 425:52] + node _T_2319 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 425:85] + node _T_2320 = and(_T_2318, _T_2319) @[el2_lsu_bus_buffer.scala 425:73] + node _T_2321 = or(_T_2314, _T_2320) @[el2_lsu_bus_buffer.scala 424:114] + node _T_2322 = and(_T_2301, _T_2321) @[el2_lsu_bus_buffer.scala 422:113] + node _T_2323 = bits(buf_age[3], 0, 0) @[el2_lsu_bus_buffer.scala 425:109] + node _T_2324 = or(_T_2322, _T_2323) @[el2_lsu_bus_buffer.scala 425:97] + node _T_2325 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 422:83] + node _T_2326 = and(_T_2325, buf_state_en[3]) @[el2_lsu_bus_buffer.scala 422:94] + node _T_2327 = eq(buf_state[1], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 423:20] + node _T_2328 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 423:47] + node _T_2329 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 423:59] + node _T_2330 = and(_T_2328, _T_2329) @[el2_lsu_bus_buffer.scala 423:57] + node _T_2331 = or(_T_2327, _T_2330) @[el2_lsu_bus_buffer.scala 423:31] + node _T_2332 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 424:23] + node _T_2333 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 424:53] + node _T_2334 = and(_T_2332, _T_2333) @[el2_lsu_bus_buffer.scala 424:41] + node _T_2335 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 424:83] + node _T_2336 = and(_T_2334, _T_2335) @[el2_lsu_bus_buffer.scala 424:71] + node _T_2337 = eq(ibuf_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 424:104] + node _T_2338 = and(_T_2336, _T_2337) @[el2_lsu_bus_buffer.scala 424:92] + node _T_2339 = or(_T_2331, _T_2338) @[el2_lsu_bus_buffer.scala 423:86] + node _T_2340 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 425:17] + node _T_2341 = and(_T_2340, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 425:35] + node _T_2342 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 425:64] + node _T_2343 = and(_T_2341, _T_2342) @[el2_lsu_bus_buffer.scala 425:52] + node _T_2344 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 425:85] + node _T_2345 = and(_T_2343, _T_2344) @[el2_lsu_bus_buffer.scala 425:73] + node _T_2346 = or(_T_2339, _T_2345) @[el2_lsu_bus_buffer.scala 424:114] + node _T_2347 = and(_T_2326, _T_2346) @[el2_lsu_bus_buffer.scala 422:113] + node _T_2348 = bits(buf_age[3], 1, 1) @[el2_lsu_bus_buffer.scala 425:109] + node _T_2349 = or(_T_2347, _T_2348) @[el2_lsu_bus_buffer.scala 425:97] + node _T_2350 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 422:83] + node _T_2351 = and(_T_2350, buf_state_en[3]) @[el2_lsu_bus_buffer.scala 422:94] + node _T_2352 = eq(buf_state[2], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 423:20] + node _T_2353 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 423:47] + node _T_2354 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 423:59] + node _T_2355 = and(_T_2353, _T_2354) @[el2_lsu_bus_buffer.scala 423:57] + node _T_2356 = or(_T_2352, _T_2355) @[el2_lsu_bus_buffer.scala 423:31] + node _T_2357 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 424:23] + node _T_2358 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 424:53] + node _T_2359 = and(_T_2357, _T_2358) @[el2_lsu_bus_buffer.scala 424:41] + node _T_2360 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 424:83] + node _T_2361 = and(_T_2359, _T_2360) @[el2_lsu_bus_buffer.scala 424:71] + node _T_2362 = eq(ibuf_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 424:104] + node _T_2363 = and(_T_2361, _T_2362) @[el2_lsu_bus_buffer.scala 424:92] + node _T_2364 = or(_T_2356, _T_2363) @[el2_lsu_bus_buffer.scala 423:86] + node _T_2365 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 425:17] + node _T_2366 = and(_T_2365, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 425:35] + node _T_2367 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 425:64] + node _T_2368 = and(_T_2366, _T_2367) @[el2_lsu_bus_buffer.scala 425:52] + node _T_2369 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 425:85] + node _T_2370 = and(_T_2368, _T_2369) @[el2_lsu_bus_buffer.scala 425:73] + node _T_2371 = or(_T_2364, _T_2370) @[el2_lsu_bus_buffer.scala 424:114] + node _T_2372 = and(_T_2351, _T_2371) @[el2_lsu_bus_buffer.scala 422:113] + node _T_2373 = bits(buf_age[3], 2, 2) @[el2_lsu_bus_buffer.scala 425:109] + node _T_2374 = or(_T_2372, _T_2373) @[el2_lsu_bus_buffer.scala 425:97] + node _T_2375 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 422:83] + node _T_2376 = and(_T_2375, buf_state_en[3]) @[el2_lsu_bus_buffer.scala 422:94] + node _T_2377 = eq(buf_state[3], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 423:20] + node _T_2378 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 423:47] + node _T_2379 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 423:59] + node _T_2380 = and(_T_2378, _T_2379) @[el2_lsu_bus_buffer.scala 423:57] + node _T_2381 = or(_T_2377, _T_2380) @[el2_lsu_bus_buffer.scala 423:31] + node _T_2382 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 424:23] + node _T_2383 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 424:53] + node _T_2384 = and(_T_2382, _T_2383) @[el2_lsu_bus_buffer.scala 424:41] + node _T_2385 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 424:83] + node _T_2386 = and(_T_2384, _T_2385) @[el2_lsu_bus_buffer.scala 424:71] + node _T_2387 = eq(ibuf_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 424:104] + node _T_2388 = and(_T_2386, _T_2387) @[el2_lsu_bus_buffer.scala 424:92] + node _T_2389 = or(_T_2381, _T_2388) @[el2_lsu_bus_buffer.scala 423:86] + node _T_2390 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 425:17] + node _T_2391 = and(_T_2390, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 425:35] + node _T_2392 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 425:64] + node _T_2393 = and(_T_2391, _T_2392) @[el2_lsu_bus_buffer.scala 425:52] + node _T_2394 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 425:85] + node _T_2395 = and(_T_2393, _T_2394) @[el2_lsu_bus_buffer.scala 425:73] + node _T_2396 = or(_T_2389, _T_2395) @[el2_lsu_bus_buffer.scala 424:114] + node _T_2397 = and(_T_2376, _T_2396) @[el2_lsu_bus_buffer.scala 422:113] + node _T_2398 = bits(buf_age[3], 3, 3) @[el2_lsu_bus_buffer.scala 425:109] + node _T_2399 = or(_T_2397, _T_2398) @[el2_lsu_bus_buffer.scala 425:97] + node _T_2400 = cat(_T_2399, _T_2374) @[Cat.scala 29:58] + node _T_2401 = cat(_T_2400, _T_2349) @[Cat.scala 29:58] + node buf_age_in_3 = cat(_T_2401, _T_2324) @[Cat.scala 29:58] + wire buf_ageQ : UInt<4>[4] @[el2_lsu_bus_buffer.scala 426:22] + buf_ageQ[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 427:12] + buf_ageQ[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 427:12] + buf_ageQ[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 427:12] + buf_ageQ[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 427:12] + node _T_2402 = bits(buf_ageQ[0], 0, 0) @[el2_lsu_bus_buffer.scala 428:74] + node _T_2403 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 428:94] + node _T_2404 = and(_T_2403, buf_cmd_state_bus_en[0]) @[el2_lsu_bus_buffer.scala 428:104] + node _T_2405 = and(_T_2402, _T_2404) @[el2_lsu_bus_buffer.scala 428:78] + node _T_2406 = bits(buf_ageQ[0], 1, 1) @[el2_lsu_bus_buffer.scala 428:74] + node _T_2407 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 428:94] + node _T_2408 = and(_T_2407, buf_cmd_state_bus_en[1]) @[el2_lsu_bus_buffer.scala 428:104] + node _T_2409 = and(_T_2406, _T_2408) @[el2_lsu_bus_buffer.scala 428:78] + node _T_2410 = bits(buf_ageQ[0], 2, 2) @[el2_lsu_bus_buffer.scala 428:74] + node _T_2411 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 428:94] + node _T_2412 = and(_T_2411, buf_cmd_state_bus_en[2]) @[el2_lsu_bus_buffer.scala 428:104] + node _T_2413 = and(_T_2410, _T_2412) @[el2_lsu_bus_buffer.scala 428:78] + node _T_2414 = bits(buf_ageQ[0], 3, 3) @[el2_lsu_bus_buffer.scala 428:74] + node _T_2415 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 428:94] + node _T_2416 = and(_T_2415, buf_cmd_state_bus_en[3]) @[el2_lsu_bus_buffer.scala 428:104] + node _T_2417 = and(_T_2414, _T_2416) @[el2_lsu_bus_buffer.scala 428:78] + node _T_2418 = cat(_T_2417, _T_2413) @[Cat.scala 29:58] + node _T_2419 = cat(_T_2418, _T_2409) @[Cat.scala 29:58] + node _T_2420 = cat(_T_2419, _T_2405) @[Cat.scala 29:58] + node _T_2421 = bits(buf_ageQ[1], 0, 0) @[el2_lsu_bus_buffer.scala 428:74] + node _T_2422 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 428:94] + node _T_2423 = and(_T_2422, buf_cmd_state_bus_en[0]) @[el2_lsu_bus_buffer.scala 428:104] + node _T_2424 = and(_T_2421, _T_2423) @[el2_lsu_bus_buffer.scala 428:78] + node _T_2425 = bits(buf_ageQ[1], 1, 1) @[el2_lsu_bus_buffer.scala 428:74] + node _T_2426 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 428:94] + node _T_2427 = and(_T_2426, buf_cmd_state_bus_en[1]) @[el2_lsu_bus_buffer.scala 428:104] + node _T_2428 = and(_T_2425, _T_2427) @[el2_lsu_bus_buffer.scala 428:78] + node _T_2429 = bits(buf_ageQ[1], 2, 2) @[el2_lsu_bus_buffer.scala 428:74] + node _T_2430 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 428:94] + node _T_2431 = and(_T_2430, buf_cmd_state_bus_en[2]) @[el2_lsu_bus_buffer.scala 428:104] + node _T_2432 = and(_T_2429, _T_2431) @[el2_lsu_bus_buffer.scala 428:78] + node _T_2433 = bits(buf_ageQ[1], 3, 3) @[el2_lsu_bus_buffer.scala 428:74] + node _T_2434 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 428:94] + node _T_2435 = and(_T_2434, buf_cmd_state_bus_en[3]) @[el2_lsu_bus_buffer.scala 428:104] + node _T_2436 = and(_T_2433, _T_2435) @[el2_lsu_bus_buffer.scala 428:78] + node _T_2437 = cat(_T_2436, _T_2432) @[Cat.scala 29:58] + node _T_2438 = cat(_T_2437, _T_2428) @[Cat.scala 29:58] + node _T_2439 = cat(_T_2438, _T_2424) @[Cat.scala 29:58] + node _T_2440 = bits(buf_ageQ[2], 0, 0) @[el2_lsu_bus_buffer.scala 428:74] + node _T_2441 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 428:94] + node _T_2442 = and(_T_2441, buf_cmd_state_bus_en[0]) @[el2_lsu_bus_buffer.scala 428:104] + node _T_2443 = and(_T_2440, _T_2442) @[el2_lsu_bus_buffer.scala 428:78] + node _T_2444 = bits(buf_ageQ[2], 1, 1) @[el2_lsu_bus_buffer.scala 428:74] + node _T_2445 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 428:94] + node _T_2446 = and(_T_2445, buf_cmd_state_bus_en[1]) @[el2_lsu_bus_buffer.scala 428:104] + node _T_2447 = and(_T_2444, _T_2446) @[el2_lsu_bus_buffer.scala 428:78] + node _T_2448 = bits(buf_ageQ[2], 2, 2) @[el2_lsu_bus_buffer.scala 428:74] + node _T_2449 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 428:94] + node _T_2450 = and(_T_2449, buf_cmd_state_bus_en[2]) @[el2_lsu_bus_buffer.scala 428:104] + node _T_2451 = and(_T_2448, _T_2450) @[el2_lsu_bus_buffer.scala 428:78] + node _T_2452 = bits(buf_ageQ[2], 3, 3) @[el2_lsu_bus_buffer.scala 428:74] + node _T_2453 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 428:94] + node _T_2454 = and(_T_2453, buf_cmd_state_bus_en[3]) @[el2_lsu_bus_buffer.scala 428:104] + node _T_2455 = and(_T_2452, _T_2454) @[el2_lsu_bus_buffer.scala 428:78] + node _T_2456 = cat(_T_2455, _T_2451) @[Cat.scala 29:58] + node _T_2457 = cat(_T_2456, _T_2447) @[Cat.scala 29:58] + node _T_2458 = cat(_T_2457, _T_2443) @[Cat.scala 29:58] + node _T_2459 = bits(buf_ageQ[3], 0, 0) @[el2_lsu_bus_buffer.scala 428:74] + node _T_2460 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 428:94] + node _T_2461 = and(_T_2460, buf_cmd_state_bus_en[0]) @[el2_lsu_bus_buffer.scala 428:104] + node _T_2462 = and(_T_2459, _T_2461) @[el2_lsu_bus_buffer.scala 428:78] + node _T_2463 = bits(buf_ageQ[3], 1, 1) @[el2_lsu_bus_buffer.scala 428:74] + node _T_2464 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 428:94] + node _T_2465 = and(_T_2464, buf_cmd_state_bus_en[1]) @[el2_lsu_bus_buffer.scala 428:104] + node _T_2466 = and(_T_2463, _T_2465) @[el2_lsu_bus_buffer.scala 428:78] + node _T_2467 = bits(buf_ageQ[3], 2, 2) @[el2_lsu_bus_buffer.scala 428:74] + node _T_2468 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 428:94] + node _T_2469 = and(_T_2468, buf_cmd_state_bus_en[2]) @[el2_lsu_bus_buffer.scala 428:104] + node _T_2470 = and(_T_2467, _T_2469) @[el2_lsu_bus_buffer.scala 428:78] + node _T_2471 = bits(buf_ageQ[3], 3, 3) @[el2_lsu_bus_buffer.scala 428:74] + node _T_2472 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 428:94] + node _T_2473 = and(_T_2472, buf_cmd_state_bus_en[3]) @[el2_lsu_bus_buffer.scala 428:104] + node _T_2474 = and(_T_2471, _T_2473) @[el2_lsu_bus_buffer.scala 428:78] + node _T_2475 = cat(_T_2474, _T_2470) @[Cat.scala 29:58] + node _T_2476 = cat(_T_2475, _T_2466) @[Cat.scala 29:58] + node _T_2477 = cat(_T_2476, _T_2462) @[Cat.scala 29:58] + buf_age[0] <= _T_2420 @[el2_lsu_bus_buffer.scala 428:13] + buf_age[1] <= _T_2439 @[el2_lsu_bus_buffer.scala 428:13] + buf_age[2] <= _T_2458 @[el2_lsu_bus_buffer.scala 428:13] + buf_age[3] <= _T_2477 @[el2_lsu_bus_buffer.scala 428:13] + node _T_2478 = eq(UInt<1>("h00"), UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 429:78] + node _T_2479 = bits(buf_age[0], 0, 0) @[el2_lsu_bus_buffer.scala 429:102] + node _T_2480 = eq(_T_2479, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 429:91] + node _T_2481 = neq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 429:121] + node _T_2482 = and(_T_2480, _T_2481) @[el2_lsu_bus_buffer.scala 429:106] + node _T_2483 = mux(_T_2478, UInt<1>("h00"), _T_2482) @[el2_lsu_bus_buffer.scala 429:74] + node _T_2484 = eq(UInt<1>("h00"), UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 429:78] + node _T_2485 = bits(buf_age[0], 1, 1) @[el2_lsu_bus_buffer.scala 429:102] + node _T_2486 = eq(_T_2485, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 429:91] + node _T_2487 = neq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 429:121] + node _T_2488 = and(_T_2486, _T_2487) @[el2_lsu_bus_buffer.scala 429:106] + node _T_2489 = mux(_T_2484, UInt<1>("h00"), _T_2488) @[el2_lsu_bus_buffer.scala 429:74] + node _T_2490 = eq(UInt<1>("h00"), UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 429:78] + node _T_2491 = bits(buf_age[0], 2, 2) @[el2_lsu_bus_buffer.scala 429:102] + node _T_2492 = eq(_T_2491, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 429:91] + node _T_2493 = neq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 429:121] + node _T_2494 = and(_T_2492, _T_2493) @[el2_lsu_bus_buffer.scala 429:106] + node _T_2495 = mux(_T_2490, UInt<1>("h00"), _T_2494) @[el2_lsu_bus_buffer.scala 429:74] + node _T_2496 = eq(UInt<1>("h00"), UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 429:78] + node _T_2497 = bits(buf_age[0], 3, 3) @[el2_lsu_bus_buffer.scala 429:102] + node _T_2498 = eq(_T_2497, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 429:91] + node _T_2499 = neq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 429:121] + node _T_2500 = and(_T_2498, _T_2499) @[el2_lsu_bus_buffer.scala 429:106] + node _T_2501 = mux(_T_2496, UInt<1>("h00"), _T_2500) @[el2_lsu_bus_buffer.scala 429:74] + node _T_2502 = cat(_T_2501, _T_2495) @[Cat.scala 29:58] + node _T_2503 = cat(_T_2502, _T_2489) @[Cat.scala 29:58] + node _T_2504 = cat(_T_2503, _T_2483) @[Cat.scala 29:58] + node _T_2505 = eq(UInt<1>("h01"), UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 429:78] + node _T_2506 = bits(buf_age[1], 0, 0) @[el2_lsu_bus_buffer.scala 429:102] + node _T_2507 = eq(_T_2506, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 429:91] + node _T_2508 = neq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 429:121] + node _T_2509 = and(_T_2507, _T_2508) @[el2_lsu_bus_buffer.scala 429:106] + node _T_2510 = mux(_T_2505, UInt<1>("h00"), _T_2509) @[el2_lsu_bus_buffer.scala 429:74] + node _T_2511 = eq(UInt<1>("h01"), UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 429:78] + node _T_2512 = bits(buf_age[1], 1, 1) @[el2_lsu_bus_buffer.scala 429:102] + node _T_2513 = eq(_T_2512, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 429:91] + node _T_2514 = neq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 429:121] + node _T_2515 = and(_T_2513, _T_2514) @[el2_lsu_bus_buffer.scala 429:106] + node _T_2516 = mux(_T_2511, UInt<1>("h00"), _T_2515) @[el2_lsu_bus_buffer.scala 429:74] + node _T_2517 = eq(UInt<1>("h01"), UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 429:78] + node _T_2518 = bits(buf_age[1], 2, 2) @[el2_lsu_bus_buffer.scala 429:102] + node _T_2519 = eq(_T_2518, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 429:91] + node _T_2520 = neq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 429:121] + node _T_2521 = and(_T_2519, _T_2520) @[el2_lsu_bus_buffer.scala 429:106] + node _T_2522 = mux(_T_2517, UInt<1>("h00"), _T_2521) @[el2_lsu_bus_buffer.scala 429:74] + node _T_2523 = eq(UInt<1>("h01"), UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 429:78] + node _T_2524 = bits(buf_age[1], 3, 3) @[el2_lsu_bus_buffer.scala 429:102] + node _T_2525 = eq(_T_2524, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 429:91] + node _T_2526 = neq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 429:121] + node _T_2527 = and(_T_2525, _T_2526) @[el2_lsu_bus_buffer.scala 429:106] + node _T_2528 = mux(_T_2523, UInt<1>("h00"), _T_2527) @[el2_lsu_bus_buffer.scala 429:74] + node _T_2529 = cat(_T_2528, _T_2522) @[Cat.scala 29:58] + node _T_2530 = cat(_T_2529, _T_2516) @[Cat.scala 29:58] + node _T_2531 = cat(_T_2530, _T_2510) @[Cat.scala 29:58] + node _T_2532 = eq(UInt<2>("h02"), UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 429:78] + node _T_2533 = bits(buf_age[2], 0, 0) @[el2_lsu_bus_buffer.scala 429:102] + node _T_2534 = eq(_T_2533, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 429:91] + node _T_2535 = neq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 429:121] + node _T_2536 = and(_T_2534, _T_2535) @[el2_lsu_bus_buffer.scala 429:106] + node _T_2537 = mux(_T_2532, UInt<1>("h00"), _T_2536) @[el2_lsu_bus_buffer.scala 429:74] + node _T_2538 = eq(UInt<2>("h02"), UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 429:78] + node _T_2539 = bits(buf_age[2], 1, 1) @[el2_lsu_bus_buffer.scala 429:102] + node _T_2540 = eq(_T_2539, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 429:91] + node _T_2541 = neq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 429:121] + node _T_2542 = and(_T_2540, _T_2541) @[el2_lsu_bus_buffer.scala 429:106] + node _T_2543 = mux(_T_2538, UInt<1>("h00"), _T_2542) @[el2_lsu_bus_buffer.scala 429:74] + node _T_2544 = eq(UInt<2>("h02"), UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 429:78] + node _T_2545 = bits(buf_age[2], 2, 2) @[el2_lsu_bus_buffer.scala 429:102] + node _T_2546 = eq(_T_2545, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 429:91] + node _T_2547 = neq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 429:121] + node _T_2548 = and(_T_2546, _T_2547) @[el2_lsu_bus_buffer.scala 429:106] + node _T_2549 = mux(_T_2544, UInt<1>("h00"), _T_2548) @[el2_lsu_bus_buffer.scala 429:74] + node _T_2550 = eq(UInt<2>("h02"), UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 429:78] + node _T_2551 = bits(buf_age[2], 3, 3) @[el2_lsu_bus_buffer.scala 429:102] + node _T_2552 = eq(_T_2551, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 429:91] + node _T_2553 = neq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 429:121] + node _T_2554 = and(_T_2552, _T_2553) @[el2_lsu_bus_buffer.scala 429:106] + node _T_2555 = mux(_T_2550, UInt<1>("h00"), _T_2554) @[el2_lsu_bus_buffer.scala 429:74] + node _T_2556 = cat(_T_2555, _T_2549) @[Cat.scala 29:58] + node _T_2557 = cat(_T_2556, _T_2543) @[Cat.scala 29:58] + node _T_2558 = cat(_T_2557, _T_2537) @[Cat.scala 29:58] + node _T_2559 = eq(UInt<2>("h03"), UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 429:78] + node _T_2560 = bits(buf_age[3], 0, 0) @[el2_lsu_bus_buffer.scala 429:102] + node _T_2561 = eq(_T_2560, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 429:91] + node _T_2562 = neq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 429:121] + node _T_2563 = and(_T_2561, _T_2562) @[el2_lsu_bus_buffer.scala 429:106] + node _T_2564 = mux(_T_2559, UInt<1>("h00"), _T_2563) @[el2_lsu_bus_buffer.scala 429:74] + node _T_2565 = eq(UInt<2>("h03"), UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 429:78] + node _T_2566 = bits(buf_age[3], 1, 1) @[el2_lsu_bus_buffer.scala 429:102] + node _T_2567 = eq(_T_2566, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 429:91] + node _T_2568 = neq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 429:121] + node _T_2569 = and(_T_2567, _T_2568) @[el2_lsu_bus_buffer.scala 429:106] + node _T_2570 = mux(_T_2565, UInt<1>("h00"), _T_2569) @[el2_lsu_bus_buffer.scala 429:74] + node _T_2571 = eq(UInt<2>("h03"), UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 429:78] + node _T_2572 = bits(buf_age[3], 2, 2) @[el2_lsu_bus_buffer.scala 429:102] + node _T_2573 = eq(_T_2572, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 429:91] + node _T_2574 = neq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 429:121] + node _T_2575 = and(_T_2573, _T_2574) @[el2_lsu_bus_buffer.scala 429:106] + node _T_2576 = mux(_T_2571, UInt<1>("h00"), _T_2575) @[el2_lsu_bus_buffer.scala 429:74] + node _T_2577 = eq(UInt<2>("h03"), UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 429:78] + node _T_2578 = bits(buf_age[3], 3, 3) @[el2_lsu_bus_buffer.scala 429:102] + node _T_2579 = eq(_T_2578, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 429:91] + node _T_2580 = neq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 429:121] + node _T_2581 = and(_T_2579, _T_2580) @[el2_lsu_bus_buffer.scala 429:106] + node _T_2582 = mux(_T_2577, UInt<1>("h00"), _T_2581) @[el2_lsu_bus_buffer.scala 429:74] + node _T_2583 = cat(_T_2582, _T_2576) @[Cat.scala 29:58] + node _T_2584 = cat(_T_2583, _T_2570) @[Cat.scala 29:58] + node _T_2585 = cat(_T_2584, _T_2564) @[Cat.scala 29:58] + buf_age_younger[0] <= _T_2504 @[el2_lsu_bus_buffer.scala 429:21] + buf_age_younger[1] <= _T_2531 @[el2_lsu_bus_buffer.scala 429:21] + buf_age_younger[2] <= _T_2558 @[el2_lsu_bus_buffer.scala 429:21] + buf_age_younger[3] <= _T_2585 @[el2_lsu_bus_buffer.scala 429:21] + node _T_2586 = bits(buf_rspageQ[0], 0, 0) @[el2_lsu_bus_buffer.scala 430:85] + node _T_2587 = eq(buf_state[0], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 430:104] + node _T_2588 = and(_T_2586, _T_2587) @[el2_lsu_bus_buffer.scala 430:89] + node _T_2589 = bits(buf_rspageQ[0], 1, 1) @[el2_lsu_bus_buffer.scala 430:85] + node _T_2590 = eq(buf_state[1], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 430:104] + node _T_2591 = and(_T_2589, _T_2590) @[el2_lsu_bus_buffer.scala 430:89] + node _T_2592 = bits(buf_rspageQ[0], 2, 2) @[el2_lsu_bus_buffer.scala 430:85] + node _T_2593 = eq(buf_state[2], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 430:104] + node _T_2594 = and(_T_2592, _T_2593) @[el2_lsu_bus_buffer.scala 430:89] + node _T_2595 = bits(buf_rspageQ[0], 3, 3) @[el2_lsu_bus_buffer.scala 430:85] + node _T_2596 = eq(buf_state[3], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 430:104] + node _T_2597 = and(_T_2595, _T_2596) @[el2_lsu_bus_buffer.scala 430:89] + node _T_2598 = cat(_T_2597, _T_2594) @[Cat.scala 29:58] + node _T_2599 = cat(_T_2598, _T_2591) @[Cat.scala 29:58] + node _T_2600 = cat(_T_2599, _T_2588) @[Cat.scala 29:58] + node _T_2601 = bits(buf_rspageQ[1], 0, 0) @[el2_lsu_bus_buffer.scala 430:85] + node _T_2602 = eq(buf_state[0], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 430:104] + node _T_2603 = and(_T_2601, _T_2602) @[el2_lsu_bus_buffer.scala 430:89] + node _T_2604 = bits(buf_rspageQ[1], 1, 1) @[el2_lsu_bus_buffer.scala 430:85] + node _T_2605 = eq(buf_state[1], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 430:104] + node _T_2606 = and(_T_2604, _T_2605) @[el2_lsu_bus_buffer.scala 430:89] + node _T_2607 = bits(buf_rspageQ[1], 2, 2) @[el2_lsu_bus_buffer.scala 430:85] + node _T_2608 = eq(buf_state[2], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 430:104] + node _T_2609 = and(_T_2607, _T_2608) @[el2_lsu_bus_buffer.scala 430:89] + node _T_2610 = bits(buf_rspageQ[1], 3, 3) @[el2_lsu_bus_buffer.scala 430:85] + node _T_2611 = eq(buf_state[3], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 430:104] + node _T_2612 = and(_T_2610, _T_2611) @[el2_lsu_bus_buffer.scala 430:89] + node _T_2613 = cat(_T_2612, _T_2609) @[Cat.scala 29:58] + node _T_2614 = cat(_T_2613, _T_2606) @[Cat.scala 29:58] + node _T_2615 = cat(_T_2614, _T_2603) @[Cat.scala 29:58] + node _T_2616 = bits(buf_rspageQ[2], 0, 0) @[el2_lsu_bus_buffer.scala 430:85] + node _T_2617 = eq(buf_state[0], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 430:104] + node _T_2618 = and(_T_2616, _T_2617) @[el2_lsu_bus_buffer.scala 430:89] + node _T_2619 = bits(buf_rspageQ[2], 1, 1) @[el2_lsu_bus_buffer.scala 430:85] + node _T_2620 = eq(buf_state[1], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 430:104] + node _T_2621 = and(_T_2619, _T_2620) @[el2_lsu_bus_buffer.scala 430:89] + node _T_2622 = bits(buf_rspageQ[2], 2, 2) @[el2_lsu_bus_buffer.scala 430:85] + node _T_2623 = eq(buf_state[2], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 430:104] + node _T_2624 = and(_T_2622, _T_2623) @[el2_lsu_bus_buffer.scala 430:89] + node _T_2625 = bits(buf_rspageQ[2], 3, 3) @[el2_lsu_bus_buffer.scala 430:85] + node _T_2626 = eq(buf_state[3], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 430:104] + node _T_2627 = and(_T_2625, _T_2626) @[el2_lsu_bus_buffer.scala 430:89] + node _T_2628 = cat(_T_2627, _T_2624) @[Cat.scala 29:58] + node _T_2629 = cat(_T_2628, _T_2621) @[Cat.scala 29:58] + node _T_2630 = cat(_T_2629, _T_2618) @[Cat.scala 29:58] + node _T_2631 = bits(buf_rspageQ[3], 0, 0) @[el2_lsu_bus_buffer.scala 430:85] + node _T_2632 = eq(buf_state[0], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 430:104] + node _T_2633 = and(_T_2631, _T_2632) @[el2_lsu_bus_buffer.scala 430:89] + node _T_2634 = bits(buf_rspageQ[3], 1, 1) @[el2_lsu_bus_buffer.scala 430:85] + node _T_2635 = eq(buf_state[1], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 430:104] + node _T_2636 = and(_T_2634, _T_2635) @[el2_lsu_bus_buffer.scala 430:89] + node _T_2637 = bits(buf_rspageQ[3], 2, 2) @[el2_lsu_bus_buffer.scala 430:85] + node _T_2638 = eq(buf_state[2], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 430:104] + node _T_2639 = and(_T_2637, _T_2638) @[el2_lsu_bus_buffer.scala 430:89] + node _T_2640 = bits(buf_rspageQ[3], 3, 3) @[el2_lsu_bus_buffer.scala 430:85] + node _T_2641 = eq(buf_state[3], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 430:104] + node _T_2642 = and(_T_2640, _T_2641) @[el2_lsu_bus_buffer.scala 430:89] + node _T_2643 = cat(_T_2642, _T_2639) @[Cat.scala 29:58] + node _T_2644 = cat(_T_2643, _T_2636) @[Cat.scala 29:58] + node _T_2645 = cat(_T_2644, _T_2633) @[Cat.scala 29:58] + buf_rsp_pickage[0] <= _T_2600 @[el2_lsu_bus_buffer.scala 430:21] + buf_rsp_pickage[1] <= _T_2615 @[el2_lsu_bus_buffer.scala 430:21] + buf_rsp_pickage[2] <= _T_2630 @[el2_lsu_bus_buffer.scala 430:21] + buf_rsp_pickage[3] <= _T_2645 @[el2_lsu_bus_buffer.scala 430:21] + node _T_2646 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 432:84] + node _T_2647 = and(_T_2646, buf_state_en[0]) @[el2_lsu_bus_buffer.scala 432:95] + node _T_2648 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 433:23] + node _T_2649 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 433:49] + node _T_2650 = or(_T_2648, _T_2649) @[el2_lsu_bus_buffer.scala 433:34] + node _T_2651 = eq(_T_2650, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 433:8] + node _T_2652 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 434:25] + node _T_2653 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 434:55] + node _T_2654 = and(_T_2652, _T_2653) @[el2_lsu_bus_buffer.scala 434:43] + node _T_2655 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 434:84] + node _T_2656 = and(_T_2654, _T_2655) @[el2_lsu_bus_buffer.scala 434:73] + node _T_2657 = eq(ibuf_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 434:103] + node _T_2658 = and(_T_2656, _T_2657) @[el2_lsu_bus_buffer.scala 434:92] + node _T_2659 = or(_T_2651, _T_2658) @[el2_lsu_bus_buffer.scala 433:61] + node _T_2660 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 435:19] + node _T_2661 = and(_T_2660, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 435:37] + node _T_2662 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 435:65] + node _T_2663 = and(_T_2661, _T_2662) @[el2_lsu_bus_buffer.scala 435:54] + node _T_2664 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 435:84] + node _T_2665 = and(_T_2663, _T_2664) @[el2_lsu_bus_buffer.scala 435:73] + node _T_2666 = or(_T_2659, _T_2665) @[el2_lsu_bus_buffer.scala 434:112] + node _T_2667 = and(_T_2647, _T_2666) @[el2_lsu_bus_buffer.scala 432:114] + node _T_2668 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 432:84] + node _T_2669 = and(_T_2668, buf_state_en[0]) @[el2_lsu_bus_buffer.scala 432:95] + node _T_2670 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 433:23] + node _T_2671 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 433:49] + node _T_2672 = or(_T_2670, _T_2671) @[el2_lsu_bus_buffer.scala 433:34] + node _T_2673 = eq(_T_2672, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 433:8] + node _T_2674 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 434:25] + node _T_2675 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 434:55] + node _T_2676 = and(_T_2674, _T_2675) @[el2_lsu_bus_buffer.scala 434:43] + node _T_2677 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 434:84] + node _T_2678 = and(_T_2676, _T_2677) @[el2_lsu_bus_buffer.scala 434:73] + node _T_2679 = eq(ibuf_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 434:103] + node _T_2680 = and(_T_2678, _T_2679) @[el2_lsu_bus_buffer.scala 434:92] + node _T_2681 = or(_T_2673, _T_2680) @[el2_lsu_bus_buffer.scala 433:61] + node _T_2682 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 435:19] + node _T_2683 = and(_T_2682, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 435:37] + node _T_2684 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 435:65] + node _T_2685 = and(_T_2683, _T_2684) @[el2_lsu_bus_buffer.scala 435:54] + node _T_2686 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 435:84] + node _T_2687 = and(_T_2685, _T_2686) @[el2_lsu_bus_buffer.scala 435:73] + node _T_2688 = or(_T_2681, _T_2687) @[el2_lsu_bus_buffer.scala 434:112] + node _T_2689 = and(_T_2669, _T_2688) @[el2_lsu_bus_buffer.scala 432:114] + node _T_2690 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 432:84] + node _T_2691 = and(_T_2690, buf_state_en[0]) @[el2_lsu_bus_buffer.scala 432:95] + node _T_2692 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 433:23] + node _T_2693 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 433:49] + node _T_2694 = or(_T_2692, _T_2693) @[el2_lsu_bus_buffer.scala 433:34] + node _T_2695 = eq(_T_2694, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 433:8] + node _T_2696 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 434:25] + node _T_2697 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 434:55] + node _T_2698 = and(_T_2696, _T_2697) @[el2_lsu_bus_buffer.scala 434:43] + node _T_2699 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 434:84] + node _T_2700 = and(_T_2698, _T_2699) @[el2_lsu_bus_buffer.scala 434:73] + node _T_2701 = eq(ibuf_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 434:103] + node _T_2702 = and(_T_2700, _T_2701) @[el2_lsu_bus_buffer.scala 434:92] + node _T_2703 = or(_T_2695, _T_2702) @[el2_lsu_bus_buffer.scala 433:61] + node _T_2704 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 435:19] + node _T_2705 = and(_T_2704, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 435:37] + node _T_2706 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 435:65] + node _T_2707 = and(_T_2705, _T_2706) @[el2_lsu_bus_buffer.scala 435:54] + node _T_2708 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 435:84] + node _T_2709 = and(_T_2707, _T_2708) @[el2_lsu_bus_buffer.scala 435:73] + node _T_2710 = or(_T_2703, _T_2709) @[el2_lsu_bus_buffer.scala 434:112] + node _T_2711 = and(_T_2691, _T_2710) @[el2_lsu_bus_buffer.scala 432:114] + node _T_2712 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 432:84] + node _T_2713 = and(_T_2712, buf_state_en[0]) @[el2_lsu_bus_buffer.scala 432:95] + node _T_2714 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 433:23] + node _T_2715 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 433:49] + node _T_2716 = or(_T_2714, _T_2715) @[el2_lsu_bus_buffer.scala 433:34] + node _T_2717 = eq(_T_2716, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 433:8] + node _T_2718 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 434:25] + node _T_2719 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 434:55] + node _T_2720 = and(_T_2718, _T_2719) @[el2_lsu_bus_buffer.scala 434:43] + node _T_2721 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 434:84] + node _T_2722 = and(_T_2720, _T_2721) @[el2_lsu_bus_buffer.scala 434:73] + node _T_2723 = eq(ibuf_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 434:103] + node _T_2724 = and(_T_2722, _T_2723) @[el2_lsu_bus_buffer.scala 434:92] + node _T_2725 = or(_T_2717, _T_2724) @[el2_lsu_bus_buffer.scala 433:61] + node _T_2726 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 435:19] + node _T_2727 = and(_T_2726, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 435:37] + node _T_2728 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 435:65] + node _T_2729 = and(_T_2727, _T_2728) @[el2_lsu_bus_buffer.scala 435:54] + node _T_2730 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 435:84] + node _T_2731 = and(_T_2729, _T_2730) @[el2_lsu_bus_buffer.scala 435:73] + node _T_2732 = or(_T_2725, _T_2731) @[el2_lsu_bus_buffer.scala 434:112] + node _T_2733 = and(_T_2713, _T_2732) @[el2_lsu_bus_buffer.scala 432:114] + node _T_2734 = cat(_T_2733, _T_2711) @[Cat.scala 29:58] + node _T_2735 = cat(_T_2734, _T_2689) @[Cat.scala 29:58] + node _T_2736 = cat(_T_2735, _T_2667) @[Cat.scala 29:58] + node _T_2737 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 432:84] + node _T_2738 = and(_T_2737, buf_state_en[1]) @[el2_lsu_bus_buffer.scala 432:95] + node _T_2739 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 433:23] + node _T_2740 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 433:49] + node _T_2741 = or(_T_2739, _T_2740) @[el2_lsu_bus_buffer.scala 433:34] + node _T_2742 = eq(_T_2741, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 433:8] + node _T_2743 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 434:25] + node _T_2744 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 434:55] + node _T_2745 = and(_T_2743, _T_2744) @[el2_lsu_bus_buffer.scala 434:43] + node _T_2746 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 434:84] + node _T_2747 = and(_T_2745, _T_2746) @[el2_lsu_bus_buffer.scala 434:73] + node _T_2748 = eq(ibuf_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 434:103] + node _T_2749 = and(_T_2747, _T_2748) @[el2_lsu_bus_buffer.scala 434:92] + node _T_2750 = or(_T_2742, _T_2749) @[el2_lsu_bus_buffer.scala 433:61] + node _T_2751 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 435:19] + node _T_2752 = and(_T_2751, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 435:37] + node _T_2753 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 435:65] + node _T_2754 = and(_T_2752, _T_2753) @[el2_lsu_bus_buffer.scala 435:54] + node _T_2755 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 435:84] + node _T_2756 = and(_T_2754, _T_2755) @[el2_lsu_bus_buffer.scala 435:73] + node _T_2757 = or(_T_2750, _T_2756) @[el2_lsu_bus_buffer.scala 434:112] + node _T_2758 = and(_T_2738, _T_2757) @[el2_lsu_bus_buffer.scala 432:114] + node _T_2759 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 432:84] + node _T_2760 = and(_T_2759, buf_state_en[1]) @[el2_lsu_bus_buffer.scala 432:95] + node _T_2761 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 433:23] + node _T_2762 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 433:49] + node _T_2763 = or(_T_2761, _T_2762) @[el2_lsu_bus_buffer.scala 433:34] + node _T_2764 = eq(_T_2763, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 433:8] + node _T_2765 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 434:25] + node _T_2766 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 434:55] + node _T_2767 = and(_T_2765, _T_2766) @[el2_lsu_bus_buffer.scala 434:43] + node _T_2768 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 434:84] + node _T_2769 = and(_T_2767, _T_2768) @[el2_lsu_bus_buffer.scala 434:73] + node _T_2770 = eq(ibuf_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 434:103] + node _T_2771 = and(_T_2769, _T_2770) @[el2_lsu_bus_buffer.scala 434:92] + node _T_2772 = or(_T_2764, _T_2771) @[el2_lsu_bus_buffer.scala 433:61] + node _T_2773 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 435:19] + node _T_2774 = and(_T_2773, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 435:37] + node _T_2775 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 435:65] + node _T_2776 = and(_T_2774, _T_2775) @[el2_lsu_bus_buffer.scala 435:54] + node _T_2777 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 435:84] + node _T_2778 = and(_T_2776, _T_2777) @[el2_lsu_bus_buffer.scala 435:73] + node _T_2779 = or(_T_2772, _T_2778) @[el2_lsu_bus_buffer.scala 434:112] + node _T_2780 = and(_T_2760, _T_2779) @[el2_lsu_bus_buffer.scala 432:114] + node _T_2781 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 432:84] + node _T_2782 = and(_T_2781, buf_state_en[1]) @[el2_lsu_bus_buffer.scala 432:95] + node _T_2783 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 433:23] + node _T_2784 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 433:49] + node _T_2785 = or(_T_2783, _T_2784) @[el2_lsu_bus_buffer.scala 433:34] + node _T_2786 = eq(_T_2785, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 433:8] + node _T_2787 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 434:25] + node _T_2788 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 434:55] + node _T_2789 = and(_T_2787, _T_2788) @[el2_lsu_bus_buffer.scala 434:43] + node _T_2790 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 434:84] + node _T_2791 = and(_T_2789, _T_2790) @[el2_lsu_bus_buffer.scala 434:73] + node _T_2792 = eq(ibuf_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 434:103] + node _T_2793 = and(_T_2791, _T_2792) @[el2_lsu_bus_buffer.scala 434:92] + node _T_2794 = or(_T_2786, _T_2793) @[el2_lsu_bus_buffer.scala 433:61] + node _T_2795 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 435:19] + node _T_2796 = and(_T_2795, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 435:37] + node _T_2797 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 435:65] + node _T_2798 = and(_T_2796, _T_2797) @[el2_lsu_bus_buffer.scala 435:54] + node _T_2799 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 435:84] + node _T_2800 = and(_T_2798, _T_2799) @[el2_lsu_bus_buffer.scala 435:73] + node _T_2801 = or(_T_2794, _T_2800) @[el2_lsu_bus_buffer.scala 434:112] + node _T_2802 = and(_T_2782, _T_2801) @[el2_lsu_bus_buffer.scala 432:114] + node _T_2803 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 432:84] + node _T_2804 = and(_T_2803, buf_state_en[1]) @[el2_lsu_bus_buffer.scala 432:95] + node _T_2805 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 433:23] + node _T_2806 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 433:49] + node _T_2807 = or(_T_2805, _T_2806) @[el2_lsu_bus_buffer.scala 433:34] + node _T_2808 = eq(_T_2807, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 433:8] + node _T_2809 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 434:25] + node _T_2810 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 434:55] + node _T_2811 = and(_T_2809, _T_2810) @[el2_lsu_bus_buffer.scala 434:43] + node _T_2812 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 434:84] + node _T_2813 = and(_T_2811, _T_2812) @[el2_lsu_bus_buffer.scala 434:73] + node _T_2814 = eq(ibuf_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 434:103] + node _T_2815 = and(_T_2813, _T_2814) @[el2_lsu_bus_buffer.scala 434:92] + node _T_2816 = or(_T_2808, _T_2815) @[el2_lsu_bus_buffer.scala 433:61] + node _T_2817 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 435:19] + node _T_2818 = and(_T_2817, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 435:37] + node _T_2819 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 435:65] + node _T_2820 = and(_T_2818, _T_2819) @[el2_lsu_bus_buffer.scala 435:54] + node _T_2821 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 435:84] + node _T_2822 = and(_T_2820, _T_2821) @[el2_lsu_bus_buffer.scala 435:73] + node _T_2823 = or(_T_2816, _T_2822) @[el2_lsu_bus_buffer.scala 434:112] + node _T_2824 = and(_T_2804, _T_2823) @[el2_lsu_bus_buffer.scala 432:114] + node _T_2825 = cat(_T_2824, _T_2802) @[Cat.scala 29:58] + node _T_2826 = cat(_T_2825, _T_2780) @[Cat.scala 29:58] + node _T_2827 = cat(_T_2826, _T_2758) @[Cat.scala 29:58] + node _T_2828 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 432:84] + node _T_2829 = and(_T_2828, buf_state_en[2]) @[el2_lsu_bus_buffer.scala 432:95] + node _T_2830 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 433:23] + node _T_2831 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 433:49] + node _T_2832 = or(_T_2830, _T_2831) @[el2_lsu_bus_buffer.scala 433:34] + node _T_2833 = eq(_T_2832, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 433:8] + node _T_2834 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 434:25] + node _T_2835 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 434:55] + node _T_2836 = and(_T_2834, _T_2835) @[el2_lsu_bus_buffer.scala 434:43] + node _T_2837 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 434:84] + node _T_2838 = and(_T_2836, _T_2837) @[el2_lsu_bus_buffer.scala 434:73] + node _T_2839 = eq(ibuf_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 434:103] + node _T_2840 = and(_T_2838, _T_2839) @[el2_lsu_bus_buffer.scala 434:92] + node _T_2841 = or(_T_2833, _T_2840) @[el2_lsu_bus_buffer.scala 433:61] + node _T_2842 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 435:19] + node _T_2843 = and(_T_2842, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 435:37] + node _T_2844 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 435:65] + node _T_2845 = and(_T_2843, _T_2844) @[el2_lsu_bus_buffer.scala 435:54] + node _T_2846 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 435:84] + node _T_2847 = and(_T_2845, _T_2846) @[el2_lsu_bus_buffer.scala 435:73] + node _T_2848 = or(_T_2841, _T_2847) @[el2_lsu_bus_buffer.scala 434:112] + node _T_2849 = and(_T_2829, _T_2848) @[el2_lsu_bus_buffer.scala 432:114] + node _T_2850 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 432:84] + node _T_2851 = and(_T_2850, buf_state_en[2]) @[el2_lsu_bus_buffer.scala 432:95] + node _T_2852 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 433:23] + node _T_2853 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 433:49] + node _T_2854 = or(_T_2852, _T_2853) @[el2_lsu_bus_buffer.scala 433:34] + node _T_2855 = eq(_T_2854, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 433:8] + node _T_2856 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 434:25] + node _T_2857 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 434:55] + node _T_2858 = and(_T_2856, _T_2857) @[el2_lsu_bus_buffer.scala 434:43] + node _T_2859 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 434:84] + node _T_2860 = and(_T_2858, _T_2859) @[el2_lsu_bus_buffer.scala 434:73] + node _T_2861 = eq(ibuf_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 434:103] + node _T_2862 = and(_T_2860, _T_2861) @[el2_lsu_bus_buffer.scala 434:92] + node _T_2863 = or(_T_2855, _T_2862) @[el2_lsu_bus_buffer.scala 433:61] + node _T_2864 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 435:19] + node _T_2865 = and(_T_2864, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 435:37] + node _T_2866 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 435:65] + node _T_2867 = and(_T_2865, _T_2866) @[el2_lsu_bus_buffer.scala 435:54] + node _T_2868 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 435:84] + node _T_2869 = and(_T_2867, _T_2868) @[el2_lsu_bus_buffer.scala 435:73] + node _T_2870 = or(_T_2863, _T_2869) @[el2_lsu_bus_buffer.scala 434:112] + node _T_2871 = and(_T_2851, _T_2870) @[el2_lsu_bus_buffer.scala 432:114] + node _T_2872 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 432:84] + node _T_2873 = and(_T_2872, buf_state_en[2]) @[el2_lsu_bus_buffer.scala 432:95] + node _T_2874 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 433:23] + node _T_2875 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 433:49] + node _T_2876 = or(_T_2874, _T_2875) @[el2_lsu_bus_buffer.scala 433:34] + node _T_2877 = eq(_T_2876, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 433:8] + node _T_2878 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 434:25] + node _T_2879 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 434:55] + node _T_2880 = and(_T_2878, _T_2879) @[el2_lsu_bus_buffer.scala 434:43] + node _T_2881 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 434:84] + node _T_2882 = and(_T_2880, _T_2881) @[el2_lsu_bus_buffer.scala 434:73] + node _T_2883 = eq(ibuf_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 434:103] + node _T_2884 = and(_T_2882, _T_2883) @[el2_lsu_bus_buffer.scala 434:92] + node _T_2885 = or(_T_2877, _T_2884) @[el2_lsu_bus_buffer.scala 433:61] + node _T_2886 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 435:19] + node _T_2887 = and(_T_2886, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 435:37] + node _T_2888 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 435:65] + node _T_2889 = and(_T_2887, _T_2888) @[el2_lsu_bus_buffer.scala 435:54] + node _T_2890 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 435:84] + node _T_2891 = and(_T_2889, _T_2890) @[el2_lsu_bus_buffer.scala 435:73] + node _T_2892 = or(_T_2885, _T_2891) @[el2_lsu_bus_buffer.scala 434:112] + node _T_2893 = and(_T_2873, _T_2892) @[el2_lsu_bus_buffer.scala 432:114] + node _T_2894 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 432:84] + node _T_2895 = and(_T_2894, buf_state_en[2]) @[el2_lsu_bus_buffer.scala 432:95] + node _T_2896 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 433:23] + node _T_2897 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 433:49] + node _T_2898 = or(_T_2896, _T_2897) @[el2_lsu_bus_buffer.scala 433:34] + node _T_2899 = eq(_T_2898, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 433:8] + node _T_2900 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 434:25] + node _T_2901 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 434:55] + node _T_2902 = and(_T_2900, _T_2901) @[el2_lsu_bus_buffer.scala 434:43] + node _T_2903 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 434:84] + node _T_2904 = and(_T_2902, _T_2903) @[el2_lsu_bus_buffer.scala 434:73] + node _T_2905 = eq(ibuf_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 434:103] + node _T_2906 = and(_T_2904, _T_2905) @[el2_lsu_bus_buffer.scala 434:92] + node _T_2907 = or(_T_2899, _T_2906) @[el2_lsu_bus_buffer.scala 433:61] + node _T_2908 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 435:19] + node _T_2909 = and(_T_2908, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 435:37] + node _T_2910 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 435:65] + node _T_2911 = and(_T_2909, _T_2910) @[el2_lsu_bus_buffer.scala 435:54] + node _T_2912 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 435:84] + node _T_2913 = and(_T_2911, _T_2912) @[el2_lsu_bus_buffer.scala 435:73] + node _T_2914 = or(_T_2907, _T_2913) @[el2_lsu_bus_buffer.scala 434:112] + node _T_2915 = and(_T_2895, _T_2914) @[el2_lsu_bus_buffer.scala 432:114] + node _T_2916 = cat(_T_2915, _T_2893) @[Cat.scala 29:58] + node _T_2917 = cat(_T_2916, _T_2871) @[Cat.scala 29:58] + node _T_2918 = cat(_T_2917, _T_2849) @[Cat.scala 29:58] + node _T_2919 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 432:84] + node _T_2920 = and(_T_2919, buf_state_en[3]) @[el2_lsu_bus_buffer.scala 432:95] + node _T_2921 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 433:23] + node _T_2922 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 433:49] + node _T_2923 = or(_T_2921, _T_2922) @[el2_lsu_bus_buffer.scala 433:34] + node _T_2924 = eq(_T_2923, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 433:8] + node _T_2925 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 434:25] + node _T_2926 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 434:55] + node _T_2927 = and(_T_2925, _T_2926) @[el2_lsu_bus_buffer.scala 434:43] + node _T_2928 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 434:84] + node _T_2929 = and(_T_2927, _T_2928) @[el2_lsu_bus_buffer.scala 434:73] + node _T_2930 = eq(ibuf_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 434:103] + node _T_2931 = and(_T_2929, _T_2930) @[el2_lsu_bus_buffer.scala 434:92] + node _T_2932 = or(_T_2924, _T_2931) @[el2_lsu_bus_buffer.scala 433:61] + node _T_2933 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 435:19] + node _T_2934 = and(_T_2933, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 435:37] + node _T_2935 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 435:65] + node _T_2936 = and(_T_2934, _T_2935) @[el2_lsu_bus_buffer.scala 435:54] + node _T_2937 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 435:84] + node _T_2938 = and(_T_2936, _T_2937) @[el2_lsu_bus_buffer.scala 435:73] + node _T_2939 = or(_T_2932, _T_2938) @[el2_lsu_bus_buffer.scala 434:112] + node _T_2940 = and(_T_2920, _T_2939) @[el2_lsu_bus_buffer.scala 432:114] + node _T_2941 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 432:84] + node _T_2942 = and(_T_2941, buf_state_en[3]) @[el2_lsu_bus_buffer.scala 432:95] + node _T_2943 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 433:23] + node _T_2944 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 433:49] + node _T_2945 = or(_T_2943, _T_2944) @[el2_lsu_bus_buffer.scala 433:34] + node _T_2946 = eq(_T_2945, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 433:8] + node _T_2947 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 434:25] + node _T_2948 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 434:55] + node _T_2949 = and(_T_2947, _T_2948) @[el2_lsu_bus_buffer.scala 434:43] + node _T_2950 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 434:84] + node _T_2951 = and(_T_2949, _T_2950) @[el2_lsu_bus_buffer.scala 434:73] + node _T_2952 = eq(ibuf_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 434:103] + node _T_2953 = and(_T_2951, _T_2952) @[el2_lsu_bus_buffer.scala 434:92] + node _T_2954 = or(_T_2946, _T_2953) @[el2_lsu_bus_buffer.scala 433:61] + node _T_2955 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 435:19] + node _T_2956 = and(_T_2955, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 435:37] + node _T_2957 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 435:65] + node _T_2958 = and(_T_2956, _T_2957) @[el2_lsu_bus_buffer.scala 435:54] + node _T_2959 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 435:84] + node _T_2960 = and(_T_2958, _T_2959) @[el2_lsu_bus_buffer.scala 435:73] + node _T_2961 = or(_T_2954, _T_2960) @[el2_lsu_bus_buffer.scala 434:112] + node _T_2962 = and(_T_2942, _T_2961) @[el2_lsu_bus_buffer.scala 432:114] + node _T_2963 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 432:84] + node _T_2964 = and(_T_2963, buf_state_en[3]) @[el2_lsu_bus_buffer.scala 432:95] + node _T_2965 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 433:23] + node _T_2966 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 433:49] + node _T_2967 = or(_T_2965, _T_2966) @[el2_lsu_bus_buffer.scala 433:34] + node _T_2968 = eq(_T_2967, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 433:8] + node _T_2969 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 434:25] + node _T_2970 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 434:55] + node _T_2971 = and(_T_2969, _T_2970) @[el2_lsu_bus_buffer.scala 434:43] + node _T_2972 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 434:84] + node _T_2973 = and(_T_2971, _T_2972) @[el2_lsu_bus_buffer.scala 434:73] + node _T_2974 = eq(ibuf_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 434:103] + node _T_2975 = and(_T_2973, _T_2974) @[el2_lsu_bus_buffer.scala 434:92] + node _T_2976 = or(_T_2968, _T_2975) @[el2_lsu_bus_buffer.scala 433:61] + node _T_2977 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 435:19] + node _T_2978 = and(_T_2977, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 435:37] + node _T_2979 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 435:65] + node _T_2980 = and(_T_2978, _T_2979) @[el2_lsu_bus_buffer.scala 435:54] + node _T_2981 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 435:84] + node _T_2982 = and(_T_2980, _T_2981) @[el2_lsu_bus_buffer.scala 435:73] + node _T_2983 = or(_T_2976, _T_2982) @[el2_lsu_bus_buffer.scala 434:112] + node _T_2984 = and(_T_2964, _T_2983) @[el2_lsu_bus_buffer.scala 432:114] + node _T_2985 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 432:84] + node _T_2986 = and(_T_2985, buf_state_en[3]) @[el2_lsu_bus_buffer.scala 432:95] + node _T_2987 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 433:23] + node _T_2988 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 433:49] + node _T_2989 = or(_T_2987, _T_2988) @[el2_lsu_bus_buffer.scala 433:34] + node _T_2990 = eq(_T_2989, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 433:8] + node _T_2991 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 434:25] + node _T_2992 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 434:55] + node _T_2993 = and(_T_2991, _T_2992) @[el2_lsu_bus_buffer.scala 434:43] + node _T_2994 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 434:84] + node _T_2995 = and(_T_2993, _T_2994) @[el2_lsu_bus_buffer.scala 434:73] + node _T_2996 = eq(ibuf_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 434:103] + node _T_2997 = and(_T_2995, _T_2996) @[el2_lsu_bus_buffer.scala 434:92] + node _T_2998 = or(_T_2990, _T_2997) @[el2_lsu_bus_buffer.scala 433:61] + node _T_2999 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 435:19] + node _T_3000 = and(_T_2999, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 435:37] + node _T_3001 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 435:65] + node _T_3002 = and(_T_3000, _T_3001) @[el2_lsu_bus_buffer.scala 435:54] + node _T_3003 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 435:84] + node _T_3004 = and(_T_3002, _T_3003) @[el2_lsu_bus_buffer.scala 435:73] + node _T_3005 = or(_T_2998, _T_3004) @[el2_lsu_bus_buffer.scala 434:112] + node _T_3006 = and(_T_2986, _T_3005) @[el2_lsu_bus_buffer.scala 432:114] + node _T_3007 = cat(_T_3006, _T_2984) @[Cat.scala 29:58] + node _T_3008 = cat(_T_3007, _T_2962) @[Cat.scala 29:58] + node _T_3009 = cat(_T_3008, _T_2940) @[Cat.scala 29:58] + buf_rspage_set[0] <= _T_2736 @[el2_lsu_bus_buffer.scala 432:20] + buf_rspage_set[1] <= _T_2827 @[el2_lsu_bus_buffer.scala 432:20] + buf_rspage_set[2] <= _T_2918 @[el2_lsu_bus_buffer.scala 432:20] + buf_rspage_set[3] <= _T_3009 @[el2_lsu_bus_buffer.scala 432:20] + node _T_3010 = bits(buf_rspage_set[0], 0, 0) @[el2_lsu_bus_buffer.scala 436:86] + node _T_3011 = bits(buf_rspage[0], 0, 0) @[el2_lsu_bus_buffer.scala 436:105] + node _T_3012 = or(_T_3010, _T_3011) @[el2_lsu_bus_buffer.scala 436:90] + node _T_3013 = bits(buf_rspage_set[0], 1, 1) @[el2_lsu_bus_buffer.scala 436:86] + node _T_3014 = bits(buf_rspage[0], 1, 1) @[el2_lsu_bus_buffer.scala 436:105] + node _T_3015 = or(_T_3013, _T_3014) @[el2_lsu_bus_buffer.scala 436:90] + node _T_3016 = bits(buf_rspage_set[0], 2, 2) @[el2_lsu_bus_buffer.scala 436:86] + node _T_3017 = bits(buf_rspage[0], 2, 2) @[el2_lsu_bus_buffer.scala 436:105] + node _T_3018 = or(_T_3016, _T_3017) @[el2_lsu_bus_buffer.scala 436:90] + node _T_3019 = bits(buf_rspage_set[0], 3, 3) @[el2_lsu_bus_buffer.scala 436:86] + node _T_3020 = bits(buf_rspage[0], 3, 3) @[el2_lsu_bus_buffer.scala 436:105] + node _T_3021 = or(_T_3019, _T_3020) @[el2_lsu_bus_buffer.scala 436:90] + node _T_3022 = cat(_T_3021, _T_3018) @[Cat.scala 29:58] + node _T_3023 = cat(_T_3022, _T_3015) @[Cat.scala 29:58] + node _T_3024 = cat(_T_3023, _T_3012) @[Cat.scala 29:58] + node _T_3025 = bits(buf_rspage_set[1], 0, 0) @[el2_lsu_bus_buffer.scala 436:86] + node _T_3026 = bits(buf_rspage[1], 0, 0) @[el2_lsu_bus_buffer.scala 436:105] + node _T_3027 = or(_T_3025, _T_3026) @[el2_lsu_bus_buffer.scala 436:90] + node _T_3028 = bits(buf_rspage_set[1], 1, 1) @[el2_lsu_bus_buffer.scala 436:86] + node _T_3029 = bits(buf_rspage[1], 1, 1) @[el2_lsu_bus_buffer.scala 436:105] + node _T_3030 = or(_T_3028, _T_3029) @[el2_lsu_bus_buffer.scala 436:90] + node _T_3031 = bits(buf_rspage_set[1], 2, 2) @[el2_lsu_bus_buffer.scala 436:86] + node _T_3032 = bits(buf_rspage[1], 2, 2) @[el2_lsu_bus_buffer.scala 436:105] + node _T_3033 = or(_T_3031, _T_3032) @[el2_lsu_bus_buffer.scala 436:90] + node _T_3034 = bits(buf_rspage_set[1], 3, 3) @[el2_lsu_bus_buffer.scala 436:86] + node _T_3035 = bits(buf_rspage[1], 3, 3) @[el2_lsu_bus_buffer.scala 436:105] + node _T_3036 = or(_T_3034, _T_3035) @[el2_lsu_bus_buffer.scala 436:90] + node _T_3037 = cat(_T_3036, _T_3033) @[Cat.scala 29:58] + node _T_3038 = cat(_T_3037, _T_3030) @[Cat.scala 29:58] + node _T_3039 = cat(_T_3038, _T_3027) @[Cat.scala 29:58] + node _T_3040 = bits(buf_rspage_set[2], 0, 0) @[el2_lsu_bus_buffer.scala 436:86] + node _T_3041 = bits(buf_rspage[2], 0, 0) @[el2_lsu_bus_buffer.scala 436:105] + node _T_3042 = or(_T_3040, _T_3041) @[el2_lsu_bus_buffer.scala 436:90] + node _T_3043 = bits(buf_rspage_set[2], 1, 1) @[el2_lsu_bus_buffer.scala 436:86] + node _T_3044 = bits(buf_rspage[2], 1, 1) @[el2_lsu_bus_buffer.scala 436:105] + node _T_3045 = or(_T_3043, _T_3044) @[el2_lsu_bus_buffer.scala 436:90] + node _T_3046 = bits(buf_rspage_set[2], 2, 2) @[el2_lsu_bus_buffer.scala 436:86] + node _T_3047 = bits(buf_rspage[2], 2, 2) @[el2_lsu_bus_buffer.scala 436:105] + node _T_3048 = or(_T_3046, _T_3047) @[el2_lsu_bus_buffer.scala 436:90] + node _T_3049 = bits(buf_rspage_set[2], 3, 3) @[el2_lsu_bus_buffer.scala 436:86] + node _T_3050 = bits(buf_rspage[2], 3, 3) @[el2_lsu_bus_buffer.scala 436:105] + node _T_3051 = or(_T_3049, _T_3050) @[el2_lsu_bus_buffer.scala 436:90] + node _T_3052 = cat(_T_3051, _T_3048) @[Cat.scala 29:58] + node _T_3053 = cat(_T_3052, _T_3045) @[Cat.scala 29:58] + node _T_3054 = cat(_T_3053, _T_3042) @[Cat.scala 29:58] + node _T_3055 = bits(buf_rspage_set[3], 0, 0) @[el2_lsu_bus_buffer.scala 436:86] + node _T_3056 = bits(buf_rspage[3], 0, 0) @[el2_lsu_bus_buffer.scala 436:105] + node _T_3057 = or(_T_3055, _T_3056) @[el2_lsu_bus_buffer.scala 436:90] + node _T_3058 = bits(buf_rspage_set[3], 1, 1) @[el2_lsu_bus_buffer.scala 436:86] + node _T_3059 = bits(buf_rspage[3], 1, 1) @[el2_lsu_bus_buffer.scala 436:105] + node _T_3060 = or(_T_3058, _T_3059) @[el2_lsu_bus_buffer.scala 436:90] + node _T_3061 = bits(buf_rspage_set[3], 2, 2) @[el2_lsu_bus_buffer.scala 436:86] + node _T_3062 = bits(buf_rspage[3], 2, 2) @[el2_lsu_bus_buffer.scala 436:105] + node _T_3063 = or(_T_3061, _T_3062) @[el2_lsu_bus_buffer.scala 436:90] + node _T_3064 = bits(buf_rspage_set[3], 3, 3) @[el2_lsu_bus_buffer.scala 436:86] + node _T_3065 = bits(buf_rspage[3], 3, 3) @[el2_lsu_bus_buffer.scala 436:105] + node _T_3066 = or(_T_3064, _T_3065) @[el2_lsu_bus_buffer.scala 436:90] + node _T_3067 = cat(_T_3066, _T_3063) @[Cat.scala 29:58] + node _T_3068 = cat(_T_3067, _T_3060) @[Cat.scala 29:58] + node _T_3069 = cat(_T_3068, _T_3057) @[Cat.scala 29:58] + buf_rspage_in[0] <= _T_3024 @[el2_lsu_bus_buffer.scala 436:19] + buf_rspage_in[1] <= _T_3039 @[el2_lsu_bus_buffer.scala 436:19] + buf_rspage_in[2] <= _T_3054 @[el2_lsu_bus_buffer.scala 436:19] + buf_rspage_in[3] <= _T_3069 @[el2_lsu_bus_buffer.scala 436:19] + node _T_3070 = bits(buf_rspageQ[0], 0, 0) @[el2_lsu_bus_buffer.scala 437:80] + node _T_3071 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 437:101] + node _T_3072 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 437:127] + node _T_3073 = or(_T_3071, _T_3072) @[el2_lsu_bus_buffer.scala 437:112] + node _T_3074 = eq(_T_3073, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 437:86] + node _T_3075 = and(_T_3070, _T_3074) @[el2_lsu_bus_buffer.scala 437:84] + node _T_3076 = bits(buf_rspageQ[0], 1, 1) @[el2_lsu_bus_buffer.scala 437:80] + node _T_3077 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 437:101] + node _T_3078 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 437:127] + node _T_3079 = or(_T_3077, _T_3078) @[el2_lsu_bus_buffer.scala 437:112] + node _T_3080 = eq(_T_3079, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 437:86] + node _T_3081 = and(_T_3076, _T_3080) @[el2_lsu_bus_buffer.scala 437:84] + node _T_3082 = bits(buf_rspageQ[0], 2, 2) @[el2_lsu_bus_buffer.scala 437:80] + node _T_3083 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 437:101] + node _T_3084 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 437:127] + node _T_3085 = or(_T_3083, _T_3084) @[el2_lsu_bus_buffer.scala 437:112] + node _T_3086 = eq(_T_3085, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 437:86] + node _T_3087 = and(_T_3082, _T_3086) @[el2_lsu_bus_buffer.scala 437:84] + node _T_3088 = bits(buf_rspageQ[0], 3, 3) @[el2_lsu_bus_buffer.scala 437:80] + node _T_3089 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 437:101] + node _T_3090 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 437:127] + node _T_3091 = or(_T_3089, _T_3090) @[el2_lsu_bus_buffer.scala 437:112] + node _T_3092 = eq(_T_3091, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 437:86] + node _T_3093 = and(_T_3088, _T_3092) @[el2_lsu_bus_buffer.scala 437:84] + node _T_3094 = cat(_T_3093, _T_3087) @[Cat.scala 29:58] + node _T_3095 = cat(_T_3094, _T_3081) @[Cat.scala 29:58] + node _T_3096 = cat(_T_3095, _T_3075) @[Cat.scala 29:58] + node _T_3097 = bits(buf_rspageQ[1], 0, 0) @[el2_lsu_bus_buffer.scala 437:80] + node _T_3098 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 437:101] + node _T_3099 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 437:127] + node _T_3100 = or(_T_3098, _T_3099) @[el2_lsu_bus_buffer.scala 437:112] + node _T_3101 = eq(_T_3100, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 437:86] + node _T_3102 = and(_T_3097, _T_3101) @[el2_lsu_bus_buffer.scala 437:84] + node _T_3103 = bits(buf_rspageQ[1], 1, 1) @[el2_lsu_bus_buffer.scala 437:80] + node _T_3104 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 437:101] + node _T_3105 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 437:127] + node _T_3106 = or(_T_3104, _T_3105) @[el2_lsu_bus_buffer.scala 437:112] + node _T_3107 = eq(_T_3106, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 437:86] + node _T_3108 = and(_T_3103, _T_3107) @[el2_lsu_bus_buffer.scala 437:84] + node _T_3109 = bits(buf_rspageQ[1], 2, 2) @[el2_lsu_bus_buffer.scala 437:80] + node _T_3110 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 437:101] + node _T_3111 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 437:127] + node _T_3112 = or(_T_3110, _T_3111) @[el2_lsu_bus_buffer.scala 437:112] + node _T_3113 = eq(_T_3112, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 437:86] + node _T_3114 = and(_T_3109, _T_3113) @[el2_lsu_bus_buffer.scala 437:84] + node _T_3115 = bits(buf_rspageQ[1], 3, 3) @[el2_lsu_bus_buffer.scala 437:80] + node _T_3116 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 437:101] + node _T_3117 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 437:127] + node _T_3118 = or(_T_3116, _T_3117) @[el2_lsu_bus_buffer.scala 437:112] + node _T_3119 = eq(_T_3118, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 437:86] + node _T_3120 = and(_T_3115, _T_3119) @[el2_lsu_bus_buffer.scala 437:84] + node _T_3121 = cat(_T_3120, _T_3114) @[Cat.scala 29:58] + node _T_3122 = cat(_T_3121, _T_3108) @[Cat.scala 29:58] + node _T_3123 = cat(_T_3122, _T_3102) @[Cat.scala 29:58] + node _T_3124 = bits(buf_rspageQ[2], 0, 0) @[el2_lsu_bus_buffer.scala 437:80] + node _T_3125 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 437:101] + node _T_3126 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 437:127] + node _T_3127 = or(_T_3125, _T_3126) @[el2_lsu_bus_buffer.scala 437:112] + node _T_3128 = eq(_T_3127, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 437:86] + node _T_3129 = and(_T_3124, _T_3128) @[el2_lsu_bus_buffer.scala 437:84] + node _T_3130 = bits(buf_rspageQ[2], 1, 1) @[el2_lsu_bus_buffer.scala 437:80] + node _T_3131 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 437:101] + node _T_3132 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 437:127] + node _T_3133 = or(_T_3131, _T_3132) @[el2_lsu_bus_buffer.scala 437:112] + node _T_3134 = eq(_T_3133, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 437:86] + node _T_3135 = and(_T_3130, _T_3134) @[el2_lsu_bus_buffer.scala 437:84] + node _T_3136 = bits(buf_rspageQ[2], 2, 2) @[el2_lsu_bus_buffer.scala 437:80] + node _T_3137 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 437:101] + node _T_3138 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 437:127] + node _T_3139 = or(_T_3137, _T_3138) @[el2_lsu_bus_buffer.scala 437:112] + node _T_3140 = eq(_T_3139, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 437:86] + node _T_3141 = and(_T_3136, _T_3140) @[el2_lsu_bus_buffer.scala 437:84] + node _T_3142 = bits(buf_rspageQ[2], 3, 3) @[el2_lsu_bus_buffer.scala 437:80] + node _T_3143 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 437:101] + node _T_3144 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 437:127] + node _T_3145 = or(_T_3143, _T_3144) @[el2_lsu_bus_buffer.scala 437:112] + node _T_3146 = eq(_T_3145, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 437:86] + node _T_3147 = and(_T_3142, _T_3146) @[el2_lsu_bus_buffer.scala 437:84] + node _T_3148 = cat(_T_3147, _T_3141) @[Cat.scala 29:58] + node _T_3149 = cat(_T_3148, _T_3135) @[Cat.scala 29:58] + node _T_3150 = cat(_T_3149, _T_3129) @[Cat.scala 29:58] + node _T_3151 = bits(buf_rspageQ[3], 0, 0) @[el2_lsu_bus_buffer.scala 437:80] + node _T_3152 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 437:101] + node _T_3153 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 437:127] + node _T_3154 = or(_T_3152, _T_3153) @[el2_lsu_bus_buffer.scala 437:112] + node _T_3155 = eq(_T_3154, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 437:86] + node _T_3156 = and(_T_3151, _T_3155) @[el2_lsu_bus_buffer.scala 437:84] + node _T_3157 = bits(buf_rspageQ[3], 1, 1) @[el2_lsu_bus_buffer.scala 437:80] + node _T_3158 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 437:101] + node _T_3159 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 437:127] + node _T_3160 = or(_T_3158, _T_3159) @[el2_lsu_bus_buffer.scala 437:112] + node _T_3161 = eq(_T_3160, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 437:86] + node _T_3162 = and(_T_3157, _T_3161) @[el2_lsu_bus_buffer.scala 437:84] + node _T_3163 = bits(buf_rspageQ[3], 2, 2) @[el2_lsu_bus_buffer.scala 437:80] + node _T_3164 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 437:101] + node _T_3165 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 437:127] + node _T_3166 = or(_T_3164, _T_3165) @[el2_lsu_bus_buffer.scala 437:112] + node _T_3167 = eq(_T_3166, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 437:86] + node _T_3168 = and(_T_3163, _T_3167) @[el2_lsu_bus_buffer.scala 437:84] + node _T_3169 = bits(buf_rspageQ[3], 3, 3) @[el2_lsu_bus_buffer.scala 437:80] + node _T_3170 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 437:101] + node _T_3171 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 437:127] + node _T_3172 = or(_T_3170, _T_3171) @[el2_lsu_bus_buffer.scala 437:112] + node _T_3173 = eq(_T_3172, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 437:86] + node _T_3174 = and(_T_3169, _T_3173) @[el2_lsu_bus_buffer.scala 437:84] + node _T_3175 = cat(_T_3174, _T_3168) @[Cat.scala 29:58] + node _T_3176 = cat(_T_3175, _T_3162) @[Cat.scala 29:58] + node _T_3177 = cat(_T_3176, _T_3156) @[Cat.scala 29:58] + buf_rspage[0] <= _T_3096 @[el2_lsu_bus_buffer.scala 437:16] + buf_rspage[1] <= _T_3123 @[el2_lsu_bus_buffer.scala 437:16] + buf_rspage[2] <= _T_3150 @[el2_lsu_bus_buffer.scala 437:16] + buf_rspage[3] <= _T_3177 @[el2_lsu_bus_buffer.scala 437:16] + node _T_3178 = eq(ibuf_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 442:77] + node _T_3179 = and(ibuf_drain_vld, _T_3178) @[el2_lsu_bus_buffer.scala 442:65] + node _T_3180 = eq(ibuf_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 442:77] + node _T_3181 = and(ibuf_drain_vld, _T_3180) @[el2_lsu_bus_buffer.scala 442:65] + node _T_3182 = eq(ibuf_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 442:77] + node _T_3183 = and(ibuf_drain_vld, _T_3182) @[el2_lsu_bus_buffer.scala 442:65] + node _T_3184 = eq(ibuf_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 442:77] + node _T_3185 = and(ibuf_drain_vld, _T_3184) @[el2_lsu_bus_buffer.scala 442:65] + node _T_3186 = cat(_T_3185, _T_3183) @[Cat.scala 29:58] + node _T_3187 = cat(_T_3186, _T_3181) @[Cat.scala 29:58] + node _T_3188 = cat(_T_3187, _T_3179) @[Cat.scala 29:58] + ibuf_drainvec_vld <= _T_3188 @[el2_lsu_bus_buffer.scala 442:23] + node _T_3189 = bits(ibuf_drainvec_vld, 0, 0) @[el2_lsu_bus_buffer.scala 443:66] + node _T_3190 = bits(ibuf_byteen_out, 3, 0) @[el2_lsu_bus_buffer.scala 443:86] + node _T_3191 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 443:106] + node _T_3192 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 443:134] + node _T_3193 = and(_T_3191, _T_3192) @[el2_lsu_bus_buffer.scala 443:123] + node _T_3194 = bits(ldst_byteen_hi_r, 3, 0) @[el2_lsu_bus_buffer.scala 443:159] + node _T_3195 = bits(ldst_byteen_lo_r, 3, 0) @[el2_lsu_bus_buffer.scala 443:182] + node _T_3196 = mux(_T_3193, _T_3194, _T_3195) @[el2_lsu_bus_buffer.scala 443:96] + node _T_3197 = mux(_T_3189, _T_3190, _T_3196) @[el2_lsu_bus_buffer.scala 443:48] + node _T_3198 = bits(ibuf_drainvec_vld, 1, 1) @[el2_lsu_bus_buffer.scala 443:66] + node _T_3199 = bits(ibuf_byteen_out, 3, 0) @[el2_lsu_bus_buffer.scala 443:86] + node _T_3200 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 443:106] + node _T_3201 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 443:134] + node _T_3202 = and(_T_3200, _T_3201) @[el2_lsu_bus_buffer.scala 443:123] + node _T_3203 = bits(ldst_byteen_hi_r, 3, 0) @[el2_lsu_bus_buffer.scala 443:159] + node _T_3204 = bits(ldst_byteen_lo_r, 3, 0) @[el2_lsu_bus_buffer.scala 443:182] + node _T_3205 = mux(_T_3202, _T_3203, _T_3204) @[el2_lsu_bus_buffer.scala 443:96] + node _T_3206 = mux(_T_3198, _T_3199, _T_3205) @[el2_lsu_bus_buffer.scala 443:48] + node _T_3207 = bits(ibuf_drainvec_vld, 2, 2) @[el2_lsu_bus_buffer.scala 443:66] + node _T_3208 = bits(ibuf_byteen_out, 3, 0) @[el2_lsu_bus_buffer.scala 443:86] + node _T_3209 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 443:106] + node _T_3210 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 443:134] + node _T_3211 = and(_T_3209, _T_3210) @[el2_lsu_bus_buffer.scala 443:123] + node _T_3212 = bits(ldst_byteen_hi_r, 3, 0) @[el2_lsu_bus_buffer.scala 443:159] + node _T_3213 = bits(ldst_byteen_lo_r, 3, 0) @[el2_lsu_bus_buffer.scala 443:182] + node _T_3214 = mux(_T_3211, _T_3212, _T_3213) @[el2_lsu_bus_buffer.scala 443:96] + node _T_3215 = mux(_T_3207, _T_3208, _T_3214) @[el2_lsu_bus_buffer.scala 443:48] + node _T_3216 = bits(ibuf_drainvec_vld, 3, 3) @[el2_lsu_bus_buffer.scala 443:66] + node _T_3217 = bits(ibuf_byteen_out, 3, 0) @[el2_lsu_bus_buffer.scala 443:86] + node _T_3218 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 443:106] + node _T_3219 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 443:134] + node _T_3220 = and(_T_3218, _T_3219) @[el2_lsu_bus_buffer.scala 443:123] + node _T_3221 = bits(ldst_byteen_hi_r, 3, 0) @[el2_lsu_bus_buffer.scala 443:159] + node _T_3222 = bits(ldst_byteen_lo_r, 3, 0) @[el2_lsu_bus_buffer.scala 443:182] + node _T_3223 = mux(_T_3220, _T_3221, _T_3222) @[el2_lsu_bus_buffer.scala 443:96] + node _T_3224 = mux(_T_3216, _T_3217, _T_3223) @[el2_lsu_bus_buffer.scala 443:48] + buf_byteen_in[0] <= _T_3197 @[el2_lsu_bus_buffer.scala 443:19] + buf_byteen_in[1] <= _T_3206 @[el2_lsu_bus_buffer.scala 443:19] + buf_byteen_in[2] <= _T_3215 @[el2_lsu_bus_buffer.scala 443:19] + buf_byteen_in[3] <= _T_3224 @[el2_lsu_bus_buffer.scala 443:19] + node _T_3225 = bits(ibuf_drainvec_vld, 0, 0) @[el2_lsu_bus_buffer.scala 444:64] + node _T_3226 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 444:93] + node _T_3227 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 444:121] + node _T_3228 = and(_T_3226, _T_3227) @[el2_lsu_bus_buffer.scala 444:110] + node _T_3229 = mux(_T_3228, io.end_addr_r, io.lsu_addr_r) @[el2_lsu_bus_buffer.scala 444:83] + node _T_3230 = mux(_T_3225, ibuf_addr, _T_3229) @[el2_lsu_bus_buffer.scala 444:46] + node _T_3231 = bits(ibuf_drainvec_vld, 1, 1) @[el2_lsu_bus_buffer.scala 444:64] + node _T_3232 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 444:93] + node _T_3233 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 444:121] + node _T_3234 = and(_T_3232, _T_3233) @[el2_lsu_bus_buffer.scala 444:110] + node _T_3235 = mux(_T_3234, io.end_addr_r, io.lsu_addr_r) @[el2_lsu_bus_buffer.scala 444:83] + node _T_3236 = mux(_T_3231, ibuf_addr, _T_3235) @[el2_lsu_bus_buffer.scala 444:46] + node _T_3237 = bits(ibuf_drainvec_vld, 2, 2) @[el2_lsu_bus_buffer.scala 444:64] + node _T_3238 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 444:93] + node _T_3239 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 444:121] + node _T_3240 = and(_T_3238, _T_3239) @[el2_lsu_bus_buffer.scala 444:110] + node _T_3241 = mux(_T_3240, io.end_addr_r, io.lsu_addr_r) @[el2_lsu_bus_buffer.scala 444:83] + node _T_3242 = mux(_T_3237, ibuf_addr, _T_3241) @[el2_lsu_bus_buffer.scala 444:46] + node _T_3243 = bits(ibuf_drainvec_vld, 3, 3) @[el2_lsu_bus_buffer.scala 444:64] + node _T_3244 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 444:93] + node _T_3245 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 444:121] + node _T_3246 = and(_T_3244, _T_3245) @[el2_lsu_bus_buffer.scala 444:110] + node _T_3247 = mux(_T_3246, io.end_addr_r, io.lsu_addr_r) @[el2_lsu_bus_buffer.scala 444:83] + node _T_3248 = mux(_T_3243, ibuf_addr, _T_3247) @[el2_lsu_bus_buffer.scala 444:46] + buf_addr_in[0] <= _T_3230 @[el2_lsu_bus_buffer.scala 444:17] + buf_addr_in[1] <= _T_3236 @[el2_lsu_bus_buffer.scala 444:17] + buf_addr_in[2] <= _T_3242 @[el2_lsu_bus_buffer.scala 444:17] + buf_addr_in[3] <= _T_3248 @[el2_lsu_bus_buffer.scala 444:17] + node _T_3249 = bits(ibuf_drainvec_vld, 0, 0) @[el2_lsu_bus_buffer.scala 445:65] + node _T_3250 = mux(_T_3249, ibuf_dual, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 445:47] + node _T_3251 = bits(ibuf_drainvec_vld, 1, 1) @[el2_lsu_bus_buffer.scala 445:65] + node _T_3252 = mux(_T_3251, ibuf_dual, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 445:47] + node _T_3253 = bits(ibuf_drainvec_vld, 2, 2) @[el2_lsu_bus_buffer.scala 445:65] + node _T_3254 = mux(_T_3253, ibuf_dual, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 445:47] + node _T_3255 = bits(ibuf_drainvec_vld, 3, 3) @[el2_lsu_bus_buffer.scala 445:65] + node _T_3256 = mux(_T_3255, ibuf_dual, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 445:47] + node _T_3257 = cat(_T_3256, _T_3254) @[Cat.scala 29:58] + node _T_3258 = cat(_T_3257, _T_3252) @[Cat.scala 29:58] + node _T_3259 = cat(_T_3258, _T_3250) @[Cat.scala 29:58] + buf_dual_in <= _T_3259 @[el2_lsu_bus_buffer.scala 445:17] + node _T_3260 = bits(ibuf_drainvec_vld, 0, 0) @[el2_lsu_bus_buffer.scala 446:67] + node _T_3261 = mux(_T_3260, ibuf_samedw, ldst_samedw_r) @[el2_lsu_bus_buffer.scala 446:49] + node _T_3262 = bits(ibuf_drainvec_vld, 1, 1) @[el2_lsu_bus_buffer.scala 446:67] + node _T_3263 = mux(_T_3262, ibuf_samedw, ldst_samedw_r) @[el2_lsu_bus_buffer.scala 446:49] + node _T_3264 = bits(ibuf_drainvec_vld, 2, 2) @[el2_lsu_bus_buffer.scala 446:67] + node _T_3265 = mux(_T_3264, ibuf_samedw, ldst_samedw_r) @[el2_lsu_bus_buffer.scala 446:49] + node _T_3266 = bits(ibuf_drainvec_vld, 3, 3) @[el2_lsu_bus_buffer.scala 446:67] + node _T_3267 = mux(_T_3266, ibuf_samedw, ldst_samedw_r) @[el2_lsu_bus_buffer.scala 446:49] + node _T_3268 = cat(_T_3267, _T_3265) @[Cat.scala 29:58] + node _T_3269 = cat(_T_3268, _T_3263) @[Cat.scala 29:58] + node _T_3270 = cat(_T_3269, _T_3261) @[Cat.scala 29:58] + buf_samedw_in <= _T_3270 @[el2_lsu_bus_buffer.scala 446:19] + node _T_3271 = bits(ibuf_drainvec_vld, 0, 0) @[el2_lsu_bus_buffer.scala 447:68] + node _T_3272 = or(ibuf_nomerge, ibuf_force_drain) @[el2_lsu_bus_buffer.scala 447:86] + node _T_3273 = mux(_T_3271, _T_3272, io.no_dword_merge_r) @[el2_lsu_bus_buffer.scala 447:50] + node _T_3274 = bits(ibuf_drainvec_vld, 1, 1) @[el2_lsu_bus_buffer.scala 447:68] + node _T_3275 = or(ibuf_nomerge, ibuf_force_drain) @[el2_lsu_bus_buffer.scala 447:86] + node _T_3276 = mux(_T_3274, _T_3275, io.no_dword_merge_r) @[el2_lsu_bus_buffer.scala 447:50] + node _T_3277 = bits(ibuf_drainvec_vld, 2, 2) @[el2_lsu_bus_buffer.scala 447:68] + node _T_3278 = or(ibuf_nomerge, ibuf_force_drain) @[el2_lsu_bus_buffer.scala 447:86] + node _T_3279 = mux(_T_3277, _T_3278, io.no_dword_merge_r) @[el2_lsu_bus_buffer.scala 447:50] + node _T_3280 = bits(ibuf_drainvec_vld, 3, 3) @[el2_lsu_bus_buffer.scala 447:68] + node _T_3281 = or(ibuf_nomerge, ibuf_force_drain) @[el2_lsu_bus_buffer.scala 447:86] + node _T_3282 = mux(_T_3280, _T_3281, io.no_dword_merge_r) @[el2_lsu_bus_buffer.scala 447:50] + node _T_3283 = cat(_T_3282, _T_3279) @[Cat.scala 29:58] + node _T_3284 = cat(_T_3283, _T_3276) @[Cat.scala 29:58] + node _T_3285 = cat(_T_3284, _T_3273) @[Cat.scala 29:58] + buf_nomerge_in <= _T_3285 @[el2_lsu_bus_buffer.scala 447:20] + node _T_3286 = bits(ibuf_drainvec_vld, 0, 0) @[el2_lsu_bus_buffer.scala 448:67] + node _T_3287 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 448:92] + node _T_3288 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 448:120] + node _T_3289 = and(_T_3287, _T_3288) @[el2_lsu_bus_buffer.scala 448:109] + node _T_3290 = mux(_T_3286, ibuf_dual, _T_3289) @[el2_lsu_bus_buffer.scala 448:49] + node _T_3291 = bits(ibuf_drainvec_vld, 1, 1) @[el2_lsu_bus_buffer.scala 448:67] + node _T_3292 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 448:92] + node _T_3293 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 448:120] + node _T_3294 = and(_T_3292, _T_3293) @[el2_lsu_bus_buffer.scala 448:109] + node _T_3295 = mux(_T_3291, ibuf_dual, _T_3294) @[el2_lsu_bus_buffer.scala 448:49] + node _T_3296 = bits(ibuf_drainvec_vld, 2, 2) @[el2_lsu_bus_buffer.scala 448:67] + node _T_3297 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 448:92] + node _T_3298 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 448:120] + node _T_3299 = and(_T_3297, _T_3298) @[el2_lsu_bus_buffer.scala 448:109] + node _T_3300 = mux(_T_3296, ibuf_dual, _T_3299) @[el2_lsu_bus_buffer.scala 448:49] + node _T_3301 = bits(ibuf_drainvec_vld, 3, 3) @[el2_lsu_bus_buffer.scala 448:67] + node _T_3302 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 448:92] + node _T_3303 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 448:120] + node _T_3304 = and(_T_3302, _T_3303) @[el2_lsu_bus_buffer.scala 448:109] + node _T_3305 = mux(_T_3301, ibuf_dual, _T_3304) @[el2_lsu_bus_buffer.scala 448:49] + node _T_3306 = cat(_T_3305, _T_3300) @[Cat.scala 29:58] + node _T_3307 = cat(_T_3306, _T_3295) @[Cat.scala 29:58] + node _T_3308 = cat(_T_3307, _T_3290) @[Cat.scala 29:58] + buf_dualhi_in <= _T_3308 @[el2_lsu_bus_buffer.scala 448:19] + node _T_3309 = bits(ibuf_drainvec_vld, 0, 0) @[el2_lsu_bus_buffer.scala 449:67] + node _T_3310 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 449:99] + node _T_3311 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 449:127] + node _T_3312 = and(_T_3310, _T_3311) @[el2_lsu_bus_buffer.scala 449:116] + node _T_3313 = mux(_T_3312, WrPtr0_r, WrPtr1_r) @[el2_lsu_bus_buffer.scala 449:89] + node _T_3314 = mux(_T_3309, ibuf_dualtag, _T_3313) @[el2_lsu_bus_buffer.scala 449:49] + node _T_3315 = bits(ibuf_drainvec_vld, 1, 1) @[el2_lsu_bus_buffer.scala 449:67] + node _T_3316 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 449:99] + node _T_3317 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 449:127] + node _T_3318 = and(_T_3316, _T_3317) @[el2_lsu_bus_buffer.scala 449:116] + node _T_3319 = mux(_T_3318, WrPtr0_r, WrPtr1_r) @[el2_lsu_bus_buffer.scala 449:89] + node _T_3320 = mux(_T_3315, ibuf_dualtag, _T_3319) @[el2_lsu_bus_buffer.scala 449:49] + node _T_3321 = bits(ibuf_drainvec_vld, 2, 2) @[el2_lsu_bus_buffer.scala 449:67] + node _T_3322 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 449:99] + node _T_3323 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 449:127] + node _T_3324 = and(_T_3322, _T_3323) @[el2_lsu_bus_buffer.scala 449:116] + node _T_3325 = mux(_T_3324, WrPtr0_r, WrPtr1_r) @[el2_lsu_bus_buffer.scala 449:89] + node _T_3326 = mux(_T_3321, ibuf_dualtag, _T_3325) @[el2_lsu_bus_buffer.scala 449:49] + node _T_3327 = bits(ibuf_drainvec_vld, 3, 3) @[el2_lsu_bus_buffer.scala 449:67] + node _T_3328 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 449:99] + node _T_3329 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 449:127] + node _T_3330 = and(_T_3328, _T_3329) @[el2_lsu_bus_buffer.scala 449:116] + node _T_3331 = mux(_T_3330, WrPtr0_r, WrPtr1_r) @[el2_lsu_bus_buffer.scala 449:89] + node _T_3332 = mux(_T_3327, ibuf_dualtag, _T_3331) @[el2_lsu_bus_buffer.scala 449:49] + buf_dualtag_in[0] <= _T_3314 @[el2_lsu_bus_buffer.scala 449:20] + buf_dualtag_in[1] <= _T_3320 @[el2_lsu_bus_buffer.scala 449:20] + buf_dualtag_in[2] <= _T_3326 @[el2_lsu_bus_buffer.scala 449:20] + buf_dualtag_in[3] <= _T_3332 @[el2_lsu_bus_buffer.scala 449:20] + node _T_3333 = bits(ibuf_drainvec_vld, 0, 0) @[el2_lsu_bus_buffer.scala 450:71] + node _T_3334 = mux(_T_3333, ibuf_sideeffect, io.is_sideeffects_r) @[el2_lsu_bus_buffer.scala 450:53] + node _T_3335 = bits(ibuf_drainvec_vld, 1, 1) @[el2_lsu_bus_buffer.scala 450:71] + node _T_3336 = mux(_T_3335, ibuf_sideeffect, io.is_sideeffects_r) @[el2_lsu_bus_buffer.scala 450:53] + node _T_3337 = bits(ibuf_drainvec_vld, 2, 2) @[el2_lsu_bus_buffer.scala 450:71] + node _T_3338 = mux(_T_3337, ibuf_sideeffect, io.is_sideeffects_r) @[el2_lsu_bus_buffer.scala 450:53] + node _T_3339 = bits(ibuf_drainvec_vld, 3, 3) @[el2_lsu_bus_buffer.scala 450:71] + node _T_3340 = mux(_T_3339, ibuf_sideeffect, io.is_sideeffects_r) @[el2_lsu_bus_buffer.scala 450:53] + node _T_3341 = cat(_T_3340, _T_3338) @[Cat.scala 29:58] + node _T_3342 = cat(_T_3341, _T_3336) @[Cat.scala 29:58] + node _T_3343 = cat(_T_3342, _T_3334) @[Cat.scala 29:58] + buf_sideeffect_in <= _T_3343 @[el2_lsu_bus_buffer.scala 450:23] + node _T_3344 = bits(ibuf_drainvec_vld, 0, 0) @[el2_lsu_bus_buffer.scala 451:67] + node _T_3345 = mux(_T_3344, ibuf_unsign, io.lsu_pkt_r.unsign) @[el2_lsu_bus_buffer.scala 451:49] + node _T_3346 = bits(ibuf_drainvec_vld, 1, 1) @[el2_lsu_bus_buffer.scala 451:67] + node _T_3347 = mux(_T_3346, ibuf_unsign, io.lsu_pkt_r.unsign) @[el2_lsu_bus_buffer.scala 451:49] + node _T_3348 = bits(ibuf_drainvec_vld, 2, 2) @[el2_lsu_bus_buffer.scala 451:67] + node _T_3349 = mux(_T_3348, ibuf_unsign, io.lsu_pkt_r.unsign) @[el2_lsu_bus_buffer.scala 451:49] + node _T_3350 = bits(ibuf_drainvec_vld, 3, 3) @[el2_lsu_bus_buffer.scala 451:67] + node _T_3351 = mux(_T_3350, ibuf_unsign, io.lsu_pkt_r.unsign) @[el2_lsu_bus_buffer.scala 451:49] + node _T_3352 = cat(_T_3351, _T_3349) @[Cat.scala 29:58] + node _T_3353 = cat(_T_3352, _T_3347) @[Cat.scala 29:58] + node _T_3354 = cat(_T_3353, _T_3345) @[Cat.scala 29:58] + buf_unsign_in <= _T_3354 @[el2_lsu_bus_buffer.scala 451:19] + node _T_3355 = bits(ibuf_drainvec_vld, 0, 0) @[el2_lsu_bus_buffer.scala 452:62] + node _T_3356 = cat(io.lsu_pkt_r.word, io.lsu_pkt_r.half) @[Cat.scala 29:58] + node _T_3357 = mux(_T_3355, ibuf_sz, _T_3356) @[el2_lsu_bus_buffer.scala 452:44] + node _T_3358 = bits(ibuf_drainvec_vld, 1, 1) @[el2_lsu_bus_buffer.scala 452:62] + node _T_3359 = cat(io.lsu_pkt_r.word, io.lsu_pkt_r.half) @[Cat.scala 29:58] + node _T_3360 = mux(_T_3358, ibuf_sz, _T_3359) @[el2_lsu_bus_buffer.scala 452:44] + node _T_3361 = bits(ibuf_drainvec_vld, 2, 2) @[el2_lsu_bus_buffer.scala 452:62] + node _T_3362 = cat(io.lsu_pkt_r.word, io.lsu_pkt_r.half) @[Cat.scala 29:58] + node _T_3363 = mux(_T_3361, ibuf_sz, _T_3362) @[el2_lsu_bus_buffer.scala 452:44] + node _T_3364 = bits(ibuf_drainvec_vld, 3, 3) @[el2_lsu_bus_buffer.scala 452:62] + node _T_3365 = cat(io.lsu_pkt_r.word, io.lsu_pkt_r.half) @[Cat.scala 29:58] + node _T_3366 = mux(_T_3364, ibuf_sz, _T_3365) @[el2_lsu_bus_buffer.scala 452:44] + buf_sz_in[0] <= _T_3357 @[el2_lsu_bus_buffer.scala 452:15] + buf_sz_in[1] <= _T_3360 @[el2_lsu_bus_buffer.scala 452:15] + buf_sz_in[2] <= _T_3363 @[el2_lsu_bus_buffer.scala 452:15] + buf_sz_in[3] <= _T_3366 @[el2_lsu_bus_buffer.scala 452:15] + node _T_3367 = bits(ibuf_drainvec_vld, 0, 0) @[el2_lsu_bus_buffer.scala 453:66] + node _T_3368 = mux(_T_3367, ibuf_write, io.lsu_pkt_r.store) @[el2_lsu_bus_buffer.scala 453:48] + node _T_3369 = bits(ibuf_drainvec_vld, 1, 1) @[el2_lsu_bus_buffer.scala 453:66] + node _T_3370 = mux(_T_3369, ibuf_write, io.lsu_pkt_r.store) @[el2_lsu_bus_buffer.scala 453:48] + node _T_3371 = bits(ibuf_drainvec_vld, 2, 2) @[el2_lsu_bus_buffer.scala 453:66] + node _T_3372 = mux(_T_3371, ibuf_write, io.lsu_pkt_r.store) @[el2_lsu_bus_buffer.scala 453:48] + node _T_3373 = bits(ibuf_drainvec_vld, 3, 3) @[el2_lsu_bus_buffer.scala 453:66] + node _T_3374 = mux(_T_3373, ibuf_write, io.lsu_pkt_r.store) @[el2_lsu_bus_buffer.scala 453:48] + node _T_3375 = cat(_T_3374, _T_3372) @[Cat.scala 29:58] + node _T_3376 = cat(_T_3375, _T_3370) @[Cat.scala 29:58] + node _T_3377 = cat(_T_3376, _T_3368) @[Cat.scala 29:58] + buf_write_in <= _T_3377 @[el2_lsu_bus_buffer.scala 453:18] + node _T_3378 = eq(UInt<3>("h00"), buf_state[0]) @[Conditional.scala 37:30] + when _T_3378 : @[Conditional.scala 40:58] + node _T_3379 = bits(io.lsu_bus_clk_en, 0, 0) @[el2_lsu_bus_buffer.scala 458:56] + node _T_3380 = mux(_T_3379, UInt<3>("h02"), UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 458:31] + buf_nxtstate[0] <= _T_3380 @[el2_lsu_bus_buffer.scala 458:25] + node _T_3381 = and(io.lsu_busreq_r, io.lsu_commit_r) @[el2_lsu_bus_buffer.scala 459:45] + node _T_3382 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 459:77] + node _T_3383 = eq(ibuf_merge_en, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 459:97] + node _T_3384 = and(_T_3382, _T_3383) @[el2_lsu_bus_buffer.scala 459:95] + node _T_3385 = eq(UInt<1>("h00"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 459:117] + node _T_3386 = and(_T_3384, _T_3385) @[el2_lsu_bus_buffer.scala 459:112] + node _T_3387 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 459:144] + node _T_3388 = eq(UInt<1>("h00"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 459:166] + node _T_3389 = and(_T_3387, _T_3388) @[el2_lsu_bus_buffer.scala 459:161] + node _T_3390 = or(_T_3386, _T_3389) @[el2_lsu_bus_buffer.scala 459:132] + node _T_3391 = and(_T_3381, _T_3390) @[el2_lsu_bus_buffer.scala 459:63] + node _T_3392 = eq(UInt<1>("h00"), ibuf_tag) @[el2_lsu_bus_buffer.scala 459:206] + node _T_3393 = and(ibuf_drain_vld, _T_3392) @[el2_lsu_bus_buffer.scala 459:201] + node _T_3394 = or(_T_3391, _T_3393) @[el2_lsu_bus_buffer.scala 459:183] + buf_state_en[0] <= _T_3394 @[el2_lsu_bus_buffer.scala 459:25] + buf_wr_en[0] <= buf_state_en[0] @[el2_lsu_bus_buffer.scala 460:22] + buf_data_en[0] <= buf_state_en[0] @[el2_lsu_bus_buffer.scala 461:24] + node _T_3395 = eq(UInt<1>("h00"), ibuf_tag) @[el2_lsu_bus_buffer.scala 462:52] + node _T_3396 = and(ibuf_drain_vld, _T_3395) @[el2_lsu_bus_buffer.scala 462:47] + node _T_3397 = bits(_T_3396, 0, 0) @[el2_lsu_bus_buffer.scala 462:73] + node _T_3398 = bits(ibuf_data_out, 31, 0) @[el2_lsu_bus_buffer.scala 462:90] + node _T_3399 = bits(store_data_lo_r, 31, 0) @[el2_lsu_bus_buffer.scala 462:114] + node _T_3400 = mux(_T_3397, _T_3398, _T_3399) @[el2_lsu_bus_buffer.scala 462:30] + buf_data_in[0] <= _T_3400 @[el2_lsu_bus_buffer.scala 462:24] + skip @[Conditional.scala 40:58] + else : @[Conditional.scala 39:67] + node _T_3401 = eq(UInt<3>("h01"), buf_state[0]) @[Conditional.scala 37:30] + when _T_3401 : @[Conditional.scala 39:67] + node _T_3402 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 465:60] + node _T_3403 = mux(_T_3402, UInt<3>("h00"), UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 465:31] + buf_nxtstate[0] <= _T_3403 @[el2_lsu_bus_buffer.scala 465:25] + node _T_3404 = or(io.lsu_bus_clk_en, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 466:46] + buf_state_en[0] <= _T_3404 @[el2_lsu_bus_buffer.scala 466:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3405 = eq(UInt<3>("h02"), buf_state[0]) @[Conditional.scala 37:30] + when _T_3405 : @[Conditional.scala 39:67] + node _T_3406 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 469:60] + node _T_3407 = and(obuf_nosend, bus_rsp_read) @[el2_lsu_bus_buffer.scala 469:89] + node _T_3408 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[el2_lsu_bus_buffer.scala 469:124] + node _T_3409 = and(_T_3407, _T_3408) @[el2_lsu_bus_buffer.scala 469:104] + node _T_3410 = mux(_T_3409, UInt<3>("h05"), UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 469:75] + node _T_3411 = mux(_T_3406, UInt<3>("h00"), _T_3410) @[el2_lsu_bus_buffer.scala 469:31] + buf_nxtstate[0] <= _T_3411 @[el2_lsu_bus_buffer.scala 469:25] + node _T_3412 = eq(obuf_tag0, UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:48] + node _T_3413 = eq(obuf_tag1, UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:104] + node _T_3414 = and(obuf_merge, _T_3413) @[el2_lsu_bus_buffer.scala 470:91] + node _T_3415 = or(_T_3412, _T_3414) @[el2_lsu_bus_buffer.scala 470:77] + node _T_3416 = and(_T_3415, obuf_valid) @[el2_lsu_bus_buffer.scala 470:135] + node _T_3417 = and(_T_3416, obuf_wr_enQ) @[el2_lsu_bus_buffer.scala 470:148] + buf_cmd_state_bus_en[0] <= _T_3417 @[el2_lsu_bus_buffer.scala 470:33] + buf_state_bus_en[0] <= buf_cmd_state_bus_en[0] @[el2_lsu_bus_buffer.scala 471:29] + node _T_3418 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 472:49] + node _T_3419 = or(_T_3418, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 472:70] + buf_state_en[0] <= _T_3419 @[el2_lsu_bus_buffer.scala 472:25] + buf_ldfwd_in[0] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 473:25] + node _T_3420 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 474:56] + node _T_3421 = eq(_T_3420, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 474:46] + node _T_3422 = and(buf_state_en[0], _T_3421) @[el2_lsu_bus_buffer.scala 474:44] + node _T_3423 = and(_T_3422, obuf_nosend) @[el2_lsu_bus_buffer.scala 474:60] + node _T_3424 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 474:76] + node _T_3425 = and(_T_3423, _T_3424) @[el2_lsu_bus_buffer.scala 474:74] + buf_ldfwd_en[0] <= _T_3425 @[el2_lsu_bus_buffer.scala 474:25] + node _T_3426 = bits(obuf_rdrsp_tag, 1, 0) @[el2_lsu_bus_buffer.scala 475:46] + buf_ldfwdtag_in[0] <= _T_3426 @[el2_lsu_bus_buffer.scala 475:28] + node _T_3427 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 476:47] + node _T_3428 = and(_T_3427, obuf_nosend) @[el2_lsu_bus_buffer.scala 476:67] + node _T_3429 = and(_T_3428, bus_rsp_read) @[el2_lsu_bus_buffer.scala 476:81] + buf_data_en[0] <= _T_3429 @[el2_lsu_bus_buffer.scala 476:24] + node _T_3430 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 477:48] + node _T_3431 = and(_T_3430, obuf_nosend) @[el2_lsu_bus_buffer.scala 477:68] + node _T_3432 = and(_T_3431, bus_rsp_read_error) @[el2_lsu_bus_buffer.scala 477:82] + buf_error_en[0] <= _T_3432 @[el2_lsu_bus_buffer.scala 477:25] + node _T_3433 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 478:61] + node _T_3434 = bits(buf_addr[0], 2, 2) @[el2_lsu_bus_buffer.scala 478:85] + node _T_3435 = bits(bus_rsp_rdata, 63, 32) @[el2_lsu_bus_buffer.scala 478:103] + node _T_3436 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 478:126] + node _T_3437 = mux(_T_3434, _T_3435, _T_3436) @[el2_lsu_bus_buffer.scala 478:73] + node _T_3438 = mux(buf_error_en[0], _T_3433, _T_3437) @[el2_lsu_bus_buffer.scala 478:30] + buf_data_in[0] <= _T_3438 @[el2_lsu_bus_buffer.scala 478:24] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3439 = eq(UInt<3>("h03"), buf_state[0]) @[Conditional.scala 37:30] + when _T_3439 : @[Conditional.scala 39:67] + node _T_3440 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 481:67] + node _T_3441 = and(UInt<1>("h01"), bus_rsp_write_error) @[el2_lsu_bus_buffer.scala 481:94] + node _T_3442 = eq(_T_3441, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 481:73] + node _T_3443 = and(_T_3440, _T_3442) @[el2_lsu_bus_buffer.scala 481:71] + node _T_3444 = or(io.dec_tlu_force_halt, _T_3443) @[el2_lsu_bus_buffer.scala 481:55] + node _T_3445 = bits(_T_3444, 0, 0) @[el2_lsu_bus_buffer.scala 481:125] + node _T_3446 = eq(buf_samedw[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 482:30] + node _T_3447 = and(buf_dual[0], _T_3446) @[el2_lsu_bus_buffer.scala 482:28] + node _T_3448 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 482:57] + node _T_3449 = eq(_T_3448, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 482:47] + node _T_3450 = and(_T_3447, _T_3449) @[el2_lsu_bus_buffer.scala 482:45] + node _T_3451 = neq(buf_state[buf_dualtag[0]], UInt<3>("h04")) @[el2_lsu_bus_buffer.scala 482:90] + node _T_3452 = and(_T_3450, _T_3451) @[el2_lsu_bus_buffer.scala 482:61] + node _T_3453 = bits(buf_ldfwd, 0, 0) @[el2_lsu_bus_buffer.scala 483:27] + node _T_3454 = or(_T_3453, any_done_wait_state) @[el2_lsu_bus_buffer.scala 483:31] + node _T_3455 = eq(buf_samedw[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 483:70] + node _T_3456 = and(buf_dual[0], _T_3455) @[el2_lsu_bus_buffer.scala 483:68] + node _T_3457 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 483:97] + node _T_3458 = eq(_T_3457, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 483:87] + node _T_3459 = and(_T_3456, _T_3458) @[el2_lsu_bus_buffer.scala 483:85] + node _T_3460 = eq(buf_dualtag[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_3461 = bits(buf_ldfwd, 0, 0) @[el2_lsu_bus_buffer.scala 110:129] + node _T_3462 = eq(buf_dualtag[0], UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_3463 = bits(buf_ldfwd, 1, 1) @[el2_lsu_bus_buffer.scala 110:129] + node _T_3464 = eq(buf_dualtag[0], UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_3465 = bits(buf_ldfwd, 2, 2) @[el2_lsu_bus_buffer.scala 110:129] + node _T_3466 = eq(buf_dualtag[0], UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_3467 = bits(buf_ldfwd, 3, 3) @[el2_lsu_bus_buffer.scala 110:129] + node _T_3468 = mux(_T_3460, _T_3461, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3469 = mux(_T_3462, _T_3463, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3470 = mux(_T_3464, _T_3465, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3471 = mux(_T_3466, _T_3467, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3472 = or(_T_3468, _T_3469) @[Mux.scala 27:72] + node _T_3473 = or(_T_3472, _T_3470) @[Mux.scala 27:72] + node _T_3474 = or(_T_3473, _T_3471) @[Mux.scala 27:72] + wire _T_3475 : UInt<1> @[Mux.scala 27:72] + _T_3475 <= _T_3474 @[Mux.scala 27:72] + node _T_3476 = and(_T_3459, _T_3475) @[el2_lsu_bus_buffer.scala 483:101] + node _T_3477 = eq(buf_state[buf_dualtag[0]], UInt<3>("h04")) @[el2_lsu_bus_buffer.scala 483:167] + node _T_3478 = and(_T_3476, _T_3477) @[el2_lsu_bus_buffer.scala 483:138] + node _T_3479 = and(_T_3478, any_done_wait_state) @[el2_lsu_bus_buffer.scala 483:187] + node _T_3480 = or(_T_3454, _T_3479) @[el2_lsu_bus_buffer.scala 483:53] + node _T_3481 = mux(_T_3480, UInt<3>("h05"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 483:16] + node _T_3482 = mux(_T_3452, UInt<3>("h04"), _T_3481) @[el2_lsu_bus_buffer.scala 482:14] + node _T_3483 = mux(_T_3445, UInt<3>("h00"), _T_3482) @[el2_lsu_bus_buffer.scala 481:31] + buf_nxtstate[0] <= _T_3483 @[el2_lsu_bus_buffer.scala 481:25] + node _T_3484 = eq(bus_rsp_write_tag, UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 484:73] + node _T_3485 = and(bus_rsp_write, _T_3484) @[el2_lsu_bus_buffer.scala 484:52] + node _T_3486 = eq(bus_rsp_read_tag, UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 485:46] + node _T_3487 = bits(buf_ldfwd, 0, 0) @[el2_lsu_bus_buffer.scala 486:23] + node _T_3488 = eq(bus_rsp_read_tag, buf_ldfwdtag[0]) @[el2_lsu_bus_buffer.scala 486:47] + node _T_3489 = and(_T_3487, _T_3488) @[el2_lsu_bus_buffer.scala 486:27] + node _T_3490 = or(_T_3486, _T_3489) @[el2_lsu_bus_buffer.scala 485:77] + node _T_3491 = and(buf_dual[0], buf_dualhi[0]) @[el2_lsu_bus_buffer.scala 487:26] + node _T_3492 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 487:54] + node _T_3493 = not(_T_3492) @[el2_lsu_bus_buffer.scala 487:44] + node _T_3494 = and(_T_3491, _T_3493) @[el2_lsu_bus_buffer.scala 487:42] + node _T_3495 = and(_T_3494, buf_samedw[0]) @[el2_lsu_bus_buffer.scala 487:58] + node _T_3496 = eq(bus_rsp_read_tag, buf_dualtag[0]) @[el2_lsu_bus_buffer.scala 487:94] + node _T_3497 = and(_T_3495, _T_3496) @[el2_lsu_bus_buffer.scala 487:74] + node _T_3498 = or(_T_3490, _T_3497) @[el2_lsu_bus_buffer.scala 486:71] + node _T_3499 = and(bus_rsp_read, _T_3498) @[el2_lsu_bus_buffer.scala 485:25] + node _T_3500 = or(_T_3485, _T_3499) @[el2_lsu_bus_buffer.scala 484:105] + buf_resp_state_bus_en[0] <= _T_3500 @[el2_lsu_bus_buffer.scala 484:34] + buf_state_bus_en[0] <= buf_resp_state_bus_en[0] @[el2_lsu_bus_buffer.scala 488:29] + node _T_3501 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 489:49] + node _T_3502 = or(_T_3501, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 489:70] + buf_state_en[0] <= _T_3502 @[el2_lsu_bus_buffer.scala 489:25] + node _T_3503 = and(buf_state_bus_en[0], bus_rsp_read) @[el2_lsu_bus_buffer.scala 490:47] + node _T_3504 = and(_T_3503, io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 490:62] + buf_data_en[0] <= _T_3504 @[el2_lsu_bus_buffer.scala 490:24] + node _T_3505 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 491:48] + node _T_3506 = eq(bus_rsp_read_tag, UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 491:111] + node _T_3507 = and(bus_rsp_read_error, _T_3506) @[el2_lsu_bus_buffer.scala 491:91] + node _T_3508 = bits(buf_ldfwd, 0, 0) @[el2_lsu_bus_buffer.scala 492:42] + node _T_3509 = and(bus_rsp_read_error, _T_3508) @[el2_lsu_bus_buffer.scala 492:31] + node _T_3510 = eq(bus_rsp_read_tag, buf_ldfwdtag[0]) @[el2_lsu_bus_buffer.scala 492:66] + node _T_3511 = and(_T_3509, _T_3510) @[el2_lsu_bus_buffer.scala 492:46] + node _T_3512 = or(_T_3507, _T_3511) @[el2_lsu_bus_buffer.scala 491:143] + node _T_3513 = and(bus_rsp_write_error, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 493:32] + node _T_3514 = eq(bus_rsp_write_tag, UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 493:74] + node _T_3515 = and(_T_3513, _T_3514) @[el2_lsu_bus_buffer.scala 493:53] + node _T_3516 = or(_T_3512, _T_3515) @[el2_lsu_bus_buffer.scala 492:88] + node _T_3517 = and(_T_3505, _T_3516) @[el2_lsu_bus_buffer.scala 491:68] + buf_error_en[0] <= _T_3517 @[el2_lsu_bus_buffer.scala 491:25] + node _T_3518 = eq(buf_error_en[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 494:50] + node _T_3519 = and(buf_state_en[0], _T_3518) @[el2_lsu_bus_buffer.scala 494:48] + node _T_3520 = bits(buf_addr[0], 2, 2) @[el2_lsu_bus_buffer.scala 494:84] + node _T_3521 = bits(bus_rsp_rdata, 63, 32) @[el2_lsu_bus_buffer.scala 494:102] + node _T_3522 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 494:125] + node _T_3523 = mux(_T_3520, _T_3521, _T_3522) @[el2_lsu_bus_buffer.scala 494:72] + node _T_3524 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 494:148] + node _T_3525 = mux(_T_3519, _T_3523, _T_3524) @[el2_lsu_bus_buffer.scala 494:30] + buf_data_in[0] <= _T_3525 @[el2_lsu_bus_buffer.scala 494:24] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3526 = eq(UInt<3>("h04"), buf_state[0]) @[Conditional.scala 37:30] + when _T_3526 : @[Conditional.scala 39:67] + node _T_3527 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 497:60] + node _T_3528 = bits(buf_ldfwd, 0, 0) @[el2_lsu_bus_buffer.scala 497:86] + node _T_3529 = dshr(buf_ldfwd, buf_dualtag[0]) @[el2_lsu_bus_buffer.scala 497:101] + node _T_3530 = bits(_T_3529, 0, 0) @[el2_lsu_bus_buffer.scala 497:101] + node _T_3531 = or(_T_3528, _T_3530) @[el2_lsu_bus_buffer.scala 497:90] + node _T_3532 = or(_T_3531, any_done_wait_state) @[el2_lsu_bus_buffer.scala 497:118] + node _T_3533 = mux(_T_3532, UInt<3>("h05"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 497:75] + node _T_3534 = mux(_T_3527, UInt<3>("h00"), _T_3533) @[el2_lsu_bus_buffer.scala 497:31] + buf_nxtstate[0] <= _T_3534 @[el2_lsu_bus_buffer.scala 497:25] + node _T_3535 = eq(bus_rsp_read_tag, buf_dualtag[0]) @[el2_lsu_bus_buffer.scala 498:66] + node _T_3536 = dshr(buf_ldfwd, buf_dualtag[0]) @[el2_lsu_bus_buffer.scala 499:21] + node _T_3537 = bits(_T_3536, 0, 0) @[el2_lsu_bus_buffer.scala 499:21] + node _T_3538 = eq(bus_rsp_read_tag, buf_ldfwdtag[buf_dualtag[0]]) @[el2_lsu_bus_buffer.scala 499:58] + node _T_3539 = and(_T_3537, _T_3538) @[el2_lsu_bus_buffer.scala 499:38] + node _T_3540 = or(_T_3535, _T_3539) @[el2_lsu_bus_buffer.scala 498:95] + node _T_3541 = and(bus_rsp_read, _T_3540) @[el2_lsu_bus_buffer.scala 498:45] + buf_state_bus_en[0] <= _T_3541 @[el2_lsu_bus_buffer.scala 498:29] + node _T_3542 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 500:49] + node _T_3543 = or(_T_3542, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 500:70] + buf_state_en[0] <= _T_3543 @[el2_lsu_bus_buffer.scala 500:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3544 = eq(UInt<3>("h05"), buf_state[0]) @[Conditional.scala 37:30] + when _T_3544 : @[Conditional.scala 39:67] + node _T_3545 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 503:60] + node _T_3546 = mux(_T_3545, UInt<3>("h00"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 503:31] + buf_nxtstate[0] <= _T_3546 @[el2_lsu_bus_buffer.scala 503:25] + node _T_3547 = eq(RspPtr, UInt<2>("h00")) @[el2_lsu_bus_buffer.scala 504:37] + node _T_3548 = eq(buf_dualtag[0], RspPtr) @[el2_lsu_bus_buffer.scala 504:98] + node _T_3549 = and(buf_dual[0], _T_3548) @[el2_lsu_bus_buffer.scala 504:80] + node _T_3550 = or(_T_3547, _T_3549) @[el2_lsu_bus_buffer.scala 504:65] + node _T_3551 = or(_T_3550, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 504:112] + buf_state_en[0] <= _T_3551 @[el2_lsu_bus_buffer.scala 504:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3552 = eq(UInt<3>("h06"), buf_state[0]) @[Conditional.scala 37:30] + when _T_3552 : @[Conditional.scala 39:67] + buf_nxtstate[0] <= UInt<3>("h00") @[el2_lsu_bus_buffer.scala 507:25] + buf_rst[0] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 508:20] + buf_state_en[0] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 509:25] + buf_ldfwd_in[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 510:25] + buf_ldfwd_en[0] <= buf_state_en[0] @[el2_lsu_bus_buffer.scala 511:25] + skip @[Conditional.scala 39:67] + node _T_3553 = bits(buf_state_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 514:108] + reg _T_3554 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3553 : @[Reg.scala 28:19] + _T_3554 <= buf_nxtstate[0] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_state[0] <= _T_3554 @[el2_lsu_bus_buffer.scala 514:18] + reg _T_3555 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 515:60] + _T_3555 <= buf_age_in_0 @[el2_lsu_bus_buffer.scala 515:60] + buf_ageQ[0] <= _T_3555 @[el2_lsu_bus_buffer.scala 515:17] + reg _T_3556 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 516:63] + _T_3556 <= buf_rspage_in[0] @[el2_lsu_bus_buffer.scala 516:63] + buf_rspageQ[0] <= _T_3556 @[el2_lsu_bus_buffer.scala 516:20] + node _T_3557 = bits(buf_wr_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 517:109] + reg _T_3558 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3557 : @[Reg.scala 28:19] + _T_3558 <= buf_dualtag_in[0] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dualtag[0] <= _T_3558 @[el2_lsu_bus_buffer.scala 517:20] + node _T_3559 = bits(buf_dual_in, 0, 0) @[el2_lsu_bus_buffer.scala 518:74] + node _T_3560 = bits(buf_wr_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 518:107] + reg _T_3561 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3560 : @[Reg.scala 28:19] + _T_3561 <= _T_3559 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dual[0] <= _T_3561 @[el2_lsu_bus_buffer.scala 518:17] + node _T_3562 = bits(buf_samedw_in, 0, 0) @[el2_lsu_bus_buffer.scala 519:78] + node _T_3563 = bits(buf_wr_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 519:111] + reg _T_3564 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3563 : @[Reg.scala 28:19] + _T_3564 <= _T_3562 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_samedw[0] <= _T_3564 @[el2_lsu_bus_buffer.scala 519:19] + node _T_3565 = bits(buf_nomerge_in, 0, 0) @[el2_lsu_bus_buffer.scala 520:80] + node _T_3566 = bits(buf_wr_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 520:113] + reg _T_3567 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3566 : @[Reg.scala 28:19] + _T_3567 <= _T_3565 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_nomerge[0] <= _T_3567 @[el2_lsu_bus_buffer.scala 520:20] + node _T_3568 = bits(buf_dualhi_in, 0, 0) @[el2_lsu_bus_buffer.scala 521:78] + node _T_3569 = bits(buf_wr_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 521:111] + reg _T_3570 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3569 : @[Reg.scala 28:19] + _T_3570 <= _T_3568 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dualhi[0] <= _T_3570 @[el2_lsu_bus_buffer.scala 521:19] + node _T_3571 = eq(UInt<3>("h00"), buf_state[1]) @[Conditional.scala 37:30] + when _T_3571 : @[Conditional.scala 40:58] + node _T_3572 = bits(io.lsu_bus_clk_en, 0, 0) @[el2_lsu_bus_buffer.scala 458:56] + node _T_3573 = mux(_T_3572, UInt<3>("h02"), UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 458:31] + buf_nxtstate[1] <= _T_3573 @[el2_lsu_bus_buffer.scala 458:25] + node _T_3574 = and(io.lsu_busreq_r, io.lsu_commit_r) @[el2_lsu_bus_buffer.scala 459:45] + node _T_3575 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 459:77] + node _T_3576 = eq(ibuf_merge_en, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 459:97] + node _T_3577 = and(_T_3575, _T_3576) @[el2_lsu_bus_buffer.scala 459:95] + node _T_3578 = eq(UInt<1>("h01"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 459:117] + node _T_3579 = and(_T_3577, _T_3578) @[el2_lsu_bus_buffer.scala 459:112] + node _T_3580 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 459:144] + node _T_3581 = eq(UInt<1>("h01"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 459:166] + node _T_3582 = and(_T_3580, _T_3581) @[el2_lsu_bus_buffer.scala 459:161] + node _T_3583 = or(_T_3579, _T_3582) @[el2_lsu_bus_buffer.scala 459:132] + node _T_3584 = and(_T_3574, _T_3583) @[el2_lsu_bus_buffer.scala 459:63] + node _T_3585 = eq(UInt<1>("h01"), ibuf_tag) @[el2_lsu_bus_buffer.scala 459:206] + node _T_3586 = and(ibuf_drain_vld, _T_3585) @[el2_lsu_bus_buffer.scala 459:201] + node _T_3587 = or(_T_3584, _T_3586) @[el2_lsu_bus_buffer.scala 459:183] + buf_state_en[1] <= _T_3587 @[el2_lsu_bus_buffer.scala 459:25] + buf_wr_en[1] <= buf_state_en[1] @[el2_lsu_bus_buffer.scala 460:22] + buf_data_en[1] <= buf_state_en[1] @[el2_lsu_bus_buffer.scala 461:24] + node _T_3588 = eq(UInt<1>("h01"), ibuf_tag) @[el2_lsu_bus_buffer.scala 462:52] + node _T_3589 = and(ibuf_drain_vld, _T_3588) @[el2_lsu_bus_buffer.scala 462:47] + node _T_3590 = bits(_T_3589, 0, 0) @[el2_lsu_bus_buffer.scala 462:73] + node _T_3591 = bits(ibuf_data_out, 31, 0) @[el2_lsu_bus_buffer.scala 462:90] + node _T_3592 = bits(store_data_lo_r, 31, 0) @[el2_lsu_bus_buffer.scala 462:114] + node _T_3593 = mux(_T_3590, _T_3591, _T_3592) @[el2_lsu_bus_buffer.scala 462:30] + buf_data_in[1] <= _T_3593 @[el2_lsu_bus_buffer.scala 462:24] + skip @[Conditional.scala 40:58] + else : @[Conditional.scala 39:67] + node _T_3594 = eq(UInt<3>("h01"), buf_state[1]) @[Conditional.scala 37:30] + when _T_3594 : @[Conditional.scala 39:67] + node _T_3595 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 465:60] + node _T_3596 = mux(_T_3595, UInt<3>("h00"), UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 465:31] + buf_nxtstate[1] <= _T_3596 @[el2_lsu_bus_buffer.scala 465:25] + node _T_3597 = or(io.lsu_bus_clk_en, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 466:46] + buf_state_en[1] <= _T_3597 @[el2_lsu_bus_buffer.scala 466:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3598 = eq(UInt<3>("h02"), buf_state[1]) @[Conditional.scala 37:30] + when _T_3598 : @[Conditional.scala 39:67] + node _T_3599 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 469:60] + node _T_3600 = and(obuf_nosend, bus_rsp_read) @[el2_lsu_bus_buffer.scala 469:89] + node _T_3601 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[el2_lsu_bus_buffer.scala 469:124] + node _T_3602 = and(_T_3600, _T_3601) @[el2_lsu_bus_buffer.scala 469:104] + node _T_3603 = mux(_T_3602, UInt<3>("h05"), UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 469:75] + node _T_3604 = mux(_T_3599, UInt<3>("h00"), _T_3603) @[el2_lsu_bus_buffer.scala 469:31] + buf_nxtstate[1] <= _T_3604 @[el2_lsu_bus_buffer.scala 469:25] + node _T_3605 = eq(obuf_tag0, UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 470:48] + node _T_3606 = eq(obuf_tag1, UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 470:104] + node _T_3607 = and(obuf_merge, _T_3606) @[el2_lsu_bus_buffer.scala 470:91] + node _T_3608 = or(_T_3605, _T_3607) @[el2_lsu_bus_buffer.scala 470:77] + node _T_3609 = and(_T_3608, obuf_valid) @[el2_lsu_bus_buffer.scala 470:135] + node _T_3610 = and(_T_3609, obuf_wr_enQ) @[el2_lsu_bus_buffer.scala 470:148] + buf_cmd_state_bus_en[1] <= _T_3610 @[el2_lsu_bus_buffer.scala 470:33] + buf_state_bus_en[1] <= buf_cmd_state_bus_en[1] @[el2_lsu_bus_buffer.scala 471:29] + node _T_3611 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 472:49] + node _T_3612 = or(_T_3611, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 472:70] + buf_state_en[1] <= _T_3612 @[el2_lsu_bus_buffer.scala 472:25] + buf_ldfwd_in[1] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 473:25] + node _T_3613 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 474:56] + node _T_3614 = eq(_T_3613, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 474:46] + node _T_3615 = and(buf_state_en[1], _T_3614) @[el2_lsu_bus_buffer.scala 474:44] + node _T_3616 = and(_T_3615, obuf_nosend) @[el2_lsu_bus_buffer.scala 474:60] + node _T_3617 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 474:76] + node _T_3618 = and(_T_3616, _T_3617) @[el2_lsu_bus_buffer.scala 474:74] + buf_ldfwd_en[1] <= _T_3618 @[el2_lsu_bus_buffer.scala 474:25] + node _T_3619 = bits(obuf_rdrsp_tag, 1, 0) @[el2_lsu_bus_buffer.scala 475:46] + buf_ldfwdtag_in[1] <= _T_3619 @[el2_lsu_bus_buffer.scala 475:28] + node _T_3620 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 476:47] + node _T_3621 = and(_T_3620, obuf_nosend) @[el2_lsu_bus_buffer.scala 476:67] + node _T_3622 = and(_T_3621, bus_rsp_read) @[el2_lsu_bus_buffer.scala 476:81] + buf_data_en[1] <= _T_3622 @[el2_lsu_bus_buffer.scala 476:24] + node _T_3623 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 477:48] + node _T_3624 = and(_T_3623, obuf_nosend) @[el2_lsu_bus_buffer.scala 477:68] + node _T_3625 = and(_T_3624, bus_rsp_read_error) @[el2_lsu_bus_buffer.scala 477:82] + buf_error_en[1] <= _T_3625 @[el2_lsu_bus_buffer.scala 477:25] + node _T_3626 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 478:61] + node _T_3627 = bits(buf_addr[1], 2, 2) @[el2_lsu_bus_buffer.scala 478:85] + node _T_3628 = bits(bus_rsp_rdata, 63, 32) @[el2_lsu_bus_buffer.scala 478:103] + node _T_3629 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 478:126] + node _T_3630 = mux(_T_3627, _T_3628, _T_3629) @[el2_lsu_bus_buffer.scala 478:73] + node _T_3631 = mux(buf_error_en[1], _T_3626, _T_3630) @[el2_lsu_bus_buffer.scala 478:30] + buf_data_in[1] <= _T_3631 @[el2_lsu_bus_buffer.scala 478:24] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3632 = eq(UInt<3>("h03"), buf_state[1]) @[Conditional.scala 37:30] + when _T_3632 : @[Conditional.scala 39:67] + node _T_3633 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 481:67] + node _T_3634 = and(UInt<1>("h01"), bus_rsp_write_error) @[el2_lsu_bus_buffer.scala 481:94] + node _T_3635 = eq(_T_3634, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 481:73] + node _T_3636 = and(_T_3633, _T_3635) @[el2_lsu_bus_buffer.scala 481:71] + node _T_3637 = or(io.dec_tlu_force_halt, _T_3636) @[el2_lsu_bus_buffer.scala 481:55] + node _T_3638 = bits(_T_3637, 0, 0) @[el2_lsu_bus_buffer.scala 481:125] + node _T_3639 = eq(buf_samedw[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 482:30] + node _T_3640 = and(buf_dual[1], _T_3639) @[el2_lsu_bus_buffer.scala 482:28] + node _T_3641 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 482:57] + node _T_3642 = eq(_T_3641, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 482:47] + node _T_3643 = and(_T_3640, _T_3642) @[el2_lsu_bus_buffer.scala 482:45] + node _T_3644 = neq(buf_state[buf_dualtag[1]], UInt<3>("h04")) @[el2_lsu_bus_buffer.scala 482:90] + node _T_3645 = and(_T_3643, _T_3644) @[el2_lsu_bus_buffer.scala 482:61] + node _T_3646 = bits(buf_ldfwd, 1, 1) @[el2_lsu_bus_buffer.scala 483:27] + node _T_3647 = or(_T_3646, any_done_wait_state) @[el2_lsu_bus_buffer.scala 483:31] + node _T_3648 = eq(buf_samedw[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 483:70] + node _T_3649 = and(buf_dual[1], _T_3648) @[el2_lsu_bus_buffer.scala 483:68] + node _T_3650 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 483:97] + node _T_3651 = eq(_T_3650, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 483:87] + node _T_3652 = and(_T_3649, _T_3651) @[el2_lsu_bus_buffer.scala 483:85] + node _T_3653 = eq(buf_dualtag[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_3654 = bits(buf_ldfwd, 0, 0) @[el2_lsu_bus_buffer.scala 110:129] + node _T_3655 = eq(buf_dualtag[1], UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_3656 = bits(buf_ldfwd, 1, 1) @[el2_lsu_bus_buffer.scala 110:129] + node _T_3657 = eq(buf_dualtag[1], UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_3658 = bits(buf_ldfwd, 2, 2) @[el2_lsu_bus_buffer.scala 110:129] + node _T_3659 = eq(buf_dualtag[1], UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_3660 = bits(buf_ldfwd, 3, 3) @[el2_lsu_bus_buffer.scala 110:129] + node _T_3661 = mux(_T_3653, _T_3654, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3662 = mux(_T_3655, _T_3656, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3663 = mux(_T_3657, _T_3658, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3664 = mux(_T_3659, _T_3660, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3665 = or(_T_3661, _T_3662) @[Mux.scala 27:72] + node _T_3666 = or(_T_3665, _T_3663) @[Mux.scala 27:72] + node _T_3667 = or(_T_3666, _T_3664) @[Mux.scala 27:72] + wire _T_3668 : UInt<1> @[Mux.scala 27:72] + _T_3668 <= _T_3667 @[Mux.scala 27:72] + node _T_3669 = and(_T_3652, _T_3668) @[el2_lsu_bus_buffer.scala 483:101] + node _T_3670 = eq(buf_state[buf_dualtag[1]], UInt<3>("h04")) @[el2_lsu_bus_buffer.scala 483:167] + node _T_3671 = and(_T_3669, _T_3670) @[el2_lsu_bus_buffer.scala 483:138] + node _T_3672 = and(_T_3671, any_done_wait_state) @[el2_lsu_bus_buffer.scala 483:187] + node _T_3673 = or(_T_3647, _T_3672) @[el2_lsu_bus_buffer.scala 483:53] + node _T_3674 = mux(_T_3673, UInt<3>("h05"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 483:16] + node _T_3675 = mux(_T_3645, UInt<3>("h04"), _T_3674) @[el2_lsu_bus_buffer.scala 482:14] + node _T_3676 = mux(_T_3638, UInt<3>("h00"), _T_3675) @[el2_lsu_bus_buffer.scala 481:31] + buf_nxtstate[1] <= _T_3676 @[el2_lsu_bus_buffer.scala 481:25] + node _T_3677 = eq(bus_rsp_write_tag, UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 484:73] + node _T_3678 = and(bus_rsp_write, _T_3677) @[el2_lsu_bus_buffer.scala 484:52] + node _T_3679 = eq(bus_rsp_read_tag, UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 485:46] + node _T_3680 = bits(buf_ldfwd, 1, 1) @[el2_lsu_bus_buffer.scala 486:23] + node _T_3681 = eq(bus_rsp_read_tag, buf_ldfwdtag[1]) @[el2_lsu_bus_buffer.scala 486:47] + node _T_3682 = and(_T_3680, _T_3681) @[el2_lsu_bus_buffer.scala 486:27] + node _T_3683 = or(_T_3679, _T_3682) @[el2_lsu_bus_buffer.scala 485:77] + node _T_3684 = and(buf_dual[1], buf_dualhi[1]) @[el2_lsu_bus_buffer.scala 487:26] + node _T_3685 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 487:54] + node _T_3686 = not(_T_3685) @[el2_lsu_bus_buffer.scala 487:44] + node _T_3687 = and(_T_3684, _T_3686) @[el2_lsu_bus_buffer.scala 487:42] + node _T_3688 = and(_T_3687, buf_samedw[1]) @[el2_lsu_bus_buffer.scala 487:58] + node _T_3689 = eq(bus_rsp_read_tag, buf_dualtag[1]) @[el2_lsu_bus_buffer.scala 487:94] + node _T_3690 = and(_T_3688, _T_3689) @[el2_lsu_bus_buffer.scala 487:74] + node _T_3691 = or(_T_3683, _T_3690) @[el2_lsu_bus_buffer.scala 486:71] + node _T_3692 = and(bus_rsp_read, _T_3691) @[el2_lsu_bus_buffer.scala 485:25] + node _T_3693 = or(_T_3678, _T_3692) @[el2_lsu_bus_buffer.scala 484:105] + buf_resp_state_bus_en[1] <= _T_3693 @[el2_lsu_bus_buffer.scala 484:34] + buf_state_bus_en[1] <= buf_resp_state_bus_en[1] @[el2_lsu_bus_buffer.scala 488:29] + node _T_3694 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 489:49] + node _T_3695 = or(_T_3694, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 489:70] + buf_state_en[1] <= _T_3695 @[el2_lsu_bus_buffer.scala 489:25] + node _T_3696 = and(buf_state_bus_en[1], bus_rsp_read) @[el2_lsu_bus_buffer.scala 490:47] + node _T_3697 = and(_T_3696, io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 490:62] + buf_data_en[1] <= _T_3697 @[el2_lsu_bus_buffer.scala 490:24] + node _T_3698 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 491:48] + node _T_3699 = eq(bus_rsp_read_tag, UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 491:111] + node _T_3700 = and(bus_rsp_read_error, _T_3699) @[el2_lsu_bus_buffer.scala 491:91] + node _T_3701 = bits(buf_ldfwd, 1, 1) @[el2_lsu_bus_buffer.scala 492:42] + node _T_3702 = and(bus_rsp_read_error, _T_3701) @[el2_lsu_bus_buffer.scala 492:31] + node _T_3703 = eq(bus_rsp_read_tag, buf_ldfwdtag[1]) @[el2_lsu_bus_buffer.scala 492:66] + node _T_3704 = and(_T_3702, _T_3703) @[el2_lsu_bus_buffer.scala 492:46] + node _T_3705 = or(_T_3700, _T_3704) @[el2_lsu_bus_buffer.scala 491:143] + node _T_3706 = and(bus_rsp_write_error, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 493:32] + node _T_3707 = eq(bus_rsp_write_tag, UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 493:74] + node _T_3708 = and(_T_3706, _T_3707) @[el2_lsu_bus_buffer.scala 493:53] + node _T_3709 = or(_T_3705, _T_3708) @[el2_lsu_bus_buffer.scala 492:88] + node _T_3710 = and(_T_3698, _T_3709) @[el2_lsu_bus_buffer.scala 491:68] + buf_error_en[1] <= _T_3710 @[el2_lsu_bus_buffer.scala 491:25] + node _T_3711 = eq(buf_error_en[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 494:50] + node _T_3712 = and(buf_state_en[1], _T_3711) @[el2_lsu_bus_buffer.scala 494:48] + node _T_3713 = bits(buf_addr[1], 2, 2) @[el2_lsu_bus_buffer.scala 494:84] + node _T_3714 = bits(bus_rsp_rdata, 63, 32) @[el2_lsu_bus_buffer.scala 494:102] + node _T_3715 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 494:125] + node _T_3716 = mux(_T_3713, _T_3714, _T_3715) @[el2_lsu_bus_buffer.scala 494:72] + node _T_3717 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 494:148] + node _T_3718 = mux(_T_3712, _T_3716, _T_3717) @[el2_lsu_bus_buffer.scala 494:30] + buf_data_in[1] <= _T_3718 @[el2_lsu_bus_buffer.scala 494:24] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3719 = eq(UInt<3>("h04"), buf_state[1]) @[Conditional.scala 37:30] + when _T_3719 : @[Conditional.scala 39:67] + node _T_3720 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 497:60] + node _T_3721 = bits(buf_ldfwd, 1, 1) @[el2_lsu_bus_buffer.scala 497:86] + node _T_3722 = dshr(buf_ldfwd, buf_dualtag[1]) @[el2_lsu_bus_buffer.scala 497:101] + node _T_3723 = bits(_T_3722, 0, 0) @[el2_lsu_bus_buffer.scala 497:101] + node _T_3724 = or(_T_3721, _T_3723) @[el2_lsu_bus_buffer.scala 497:90] + node _T_3725 = or(_T_3724, any_done_wait_state) @[el2_lsu_bus_buffer.scala 497:118] + node _T_3726 = mux(_T_3725, UInt<3>("h05"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 497:75] + node _T_3727 = mux(_T_3720, UInt<3>("h00"), _T_3726) @[el2_lsu_bus_buffer.scala 497:31] + buf_nxtstate[1] <= _T_3727 @[el2_lsu_bus_buffer.scala 497:25] + node _T_3728 = eq(bus_rsp_read_tag, buf_dualtag[1]) @[el2_lsu_bus_buffer.scala 498:66] + node _T_3729 = dshr(buf_ldfwd, buf_dualtag[1]) @[el2_lsu_bus_buffer.scala 499:21] + node _T_3730 = bits(_T_3729, 0, 0) @[el2_lsu_bus_buffer.scala 499:21] + node _T_3731 = eq(bus_rsp_read_tag, buf_ldfwdtag[buf_dualtag[1]]) @[el2_lsu_bus_buffer.scala 499:58] + node _T_3732 = and(_T_3730, _T_3731) @[el2_lsu_bus_buffer.scala 499:38] + node _T_3733 = or(_T_3728, _T_3732) @[el2_lsu_bus_buffer.scala 498:95] + node _T_3734 = and(bus_rsp_read, _T_3733) @[el2_lsu_bus_buffer.scala 498:45] + buf_state_bus_en[1] <= _T_3734 @[el2_lsu_bus_buffer.scala 498:29] + node _T_3735 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 500:49] + node _T_3736 = or(_T_3735, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 500:70] + buf_state_en[1] <= _T_3736 @[el2_lsu_bus_buffer.scala 500:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3737 = eq(UInt<3>("h05"), buf_state[1]) @[Conditional.scala 37:30] + when _T_3737 : @[Conditional.scala 39:67] + node _T_3738 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 503:60] + node _T_3739 = mux(_T_3738, UInt<3>("h00"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 503:31] + buf_nxtstate[1] <= _T_3739 @[el2_lsu_bus_buffer.scala 503:25] + node _T_3740 = eq(RspPtr, UInt<2>("h01")) @[el2_lsu_bus_buffer.scala 504:37] + node _T_3741 = eq(buf_dualtag[1], RspPtr) @[el2_lsu_bus_buffer.scala 504:98] + node _T_3742 = and(buf_dual[1], _T_3741) @[el2_lsu_bus_buffer.scala 504:80] + node _T_3743 = or(_T_3740, _T_3742) @[el2_lsu_bus_buffer.scala 504:65] + node _T_3744 = or(_T_3743, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 504:112] + buf_state_en[1] <= _T_3744 @[el2_lsu_bus_buffer.scala 504:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3745 = eq(UInt<3>("h06"), buf_state[1]) @[Conditional.scala 37:30] + when _T_3745 : @[Conditional.scala 39:67] + buf_nxtstate[1] <= UInt<3>("h00") @[el2_lsu_bus_buffer.scala 507:25] + buf_rst[1] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 508:20] + buf_state_en[1] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 509:25] + buf_ldfwd_in[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 510:25] + buf_ldfwd_en[1] <= buf_state_en[1] @[el2_lsu_bus_buffer.scala 511:25] + skip @[Conditional.scala 39:67] + node _T_3746 = bits(buf_state_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 514:108] + reg _T_3747 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3746 : @[Reg.scala 28:19] + _T_3747 <= buf_nxtstate[1] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_state[1] <= _T_3747 @[el2_lsu_bus_buffer.scala 514:18] + reg _T_3748 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 515:60] + _T_3748 <= buf_age_in_1 @[el2_lsu_bus_buffer.scala 515:60] + buf_ageQ[1] <= _T_3748 @[el2_lsu_bus_buffer.scala 515:17] + reg _T_3749 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 516:63] + _T_3749 <= buf_rspage_in[1] @[el2_lsu_bus_buffer.scala 516:63] + buf_rspageQ[1] <= _T_3749 @[el2_lsu_bus_buffer.scala 516:20] + node _T_3750 = bits(buf_wr_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 517:109] + reg _T_3751 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3750 : @[Reg.scala 28:19] + _T_3751 <= buf_dualtag_in[1] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dualtag[1] <= _T_3751 @[el2_lsu_bus_buffer.scala 517:20] + node _T_3752 = bits(buf_dual_in, 1, 1) @[el2_lsu_bus_buffer.scala 518:74] + node _T_3753 = bits(buf_wr_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 518:107] + reg _T_3754 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3753 : @[Reg.scala 28:19] + _T_3754 <= _T_3752 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dual[1] <= _T_3754 @[el2_lsu_bus_buffer.scala 518:17] + node _T_3755 = bits(buf_samedw_in, 1, 1) @[el2_lsu_bus_buffer.scala 519:78] + node _T_3756 = bits(buf_wr_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 519:111] + reg _T_3757 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3756 : @[Reg.scala 28:19] + _T_3757 <= _T_3755 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_samedw[1] <= _T_3757 @[el2_lsu_bus_buffer.scala 519:19] + node _T_3758 = bits(buf_nomerge_in, 1, 1) @[el2_lsu_bus_buffer.scala 520:80] + node _T_3759 = bits(buf_wr_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 520:113] + reg _T_3760 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3759 : @[Reg.scala 28:19] + _T_3760 <= _T_3758 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_nomerge[1] <= _T_3760 @[el2_lsu_bus_buffer.scala 520:20] + node _T_3761 = bits(buf_dualhi_in, 1, 1) @[el2_lsu_bus_buffer.scala 521:78] + node _T_3762 = bits(buf_wr_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 521:111] + reg _T_3763 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3762 : @[Reg.scala 28:19] + _T_3763 <= _T_3761 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dualhi[1] <= _T_3763 @[el2_lsu_bus_buffer.scala 521:19] + node _T_3764 = eq(UInt<3>("h00"), buf_state[2]) @[Conditional.scala 37:30] + when _T_3764 : @[Conditional.scala 40:58] + node _T_3765 = bits(io.lsu_bus_clk_en, 0, 0) @[el2_lsu_bus_buffer.scala 458:56] + node _T_3766 = mux(_T_3765, UInt<3>("h02"), UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 458:31] + buf_nxtstate[2] <= _T_3766 @[el2_lsu_bus_buffer.scala 458:25] + node _T_3767 = and(io.lsu_busreq_r, io.lsu_commit_r) @[el2_lsu_bus_buffer.scala 459:45] + node _T_3768 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 459:77] + node _T_3769 = eq(ibuf_merge_en, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 459:97] + node _T_3770 = and(_T_3768, _T_3769) @[el2_lsu_bus_buffer.scala 459:95] + node _T_3771 = eq(UInt<2>("h02"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 459:117] + node _T_3772 = and(_T_3770, _T_3771) @[el2_lsu_bus_buffer.scala 459:112] + node _T_3773 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 459:144] + node _T_3774 = eq(UInt<2>("h02"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 459:166] + node _T_3775 = and(_T_3773, _T_3774) @[el2_lsu_bus_buffer.scala 459:161] + node _T_3776 = or(_T_3772, _T_3775) @[el2_lsu_bus_buffer.scala 459:132] + node _T_3777 = and(_T_3767, _T_3776) @[el2_lsu_bus_buffer.scala 459:63] + node _T_3778 = eq(UInt<2>("h02"), ibuf_tag) @[el2_lsu_bus_buffer.scala 459:206] + node _T_3779 = and(ibuf_drain_vld, _T_3778) @[el2_lsu_bus_buffer.scala 459:201] + node _T_3780 = or(_T_3777, _T_3779) @[el2_lsu_bus_buffer.scala 459:183] + buf_state_en[2] <= _T_3780 @[el2_lsu_bus_buffer.scala 459:25] + buf_wr_en[2] <= buf_state_en[2] @[el2_lsu_bus_buffer.scala 460:22] + buf_data_en[2] <= buf_state_en[2] @[el2_lsu_bus_buffer.scala 461:24] + node _T_3781 = eq(UInt<2>("h02"), ibuf_tag) @[el2_lsu_bus_buffer.scala 462:52] + node _T_3782 = and(ibuf_drain_vld, _T_3781) @[el2_lsu_bus_buffer.scala 462:47] + node _T_3783 = bits(_T_3782, 0, 0) @[el2_lsu_bus_buffer.scala 462:73] + node _T_3784 = bits(ibuf_data_out, 31, 0) @[el2_lsu_bus_buffer.scala 462:90] + node _T_3785 = bits(store_data_lo_r, 31, 0) @[el2_lsu_bus_buffer.scala 462:114] + node _T_3786 = mux(_T_3783, _T_3784, _T_3785) @[el2_lsu_bus_buffer.scala 462:30] + buf_data_in[2] <= _T_3786 @[el2_lsu_bus_buffer.scala 462:24] + skip @[Conditional.scala 40:58] + else : @[Conditional.scala 39:67] + node _T_3787 = eq(UInt<3>("h01"), buf_state[2]) @[Conditional.scala 37:30] + when _T_3787 : @[Conditional.scala 39:67] + node _T_3788 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 465:60] + node _T_3789 = mux(_T_3788, UInt<3>("h00"), UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 465:31] + buf_nxtstate[2] <= _T_3789 @[el2_lsu_bus_buffer.scala 465:25] + node _T_3790 = or(io.lsu_bus_clk_en, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 466:46] + buf_state_en[2] <= _T_3790 @[el2_lsu_bus_buffer.scala 466:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3791 = eq(UInt<3>("h02"), buf_state[2]) @[Conditional.scala 37:30] + when _T_3791 : @[Conditional.scala 39:67] + node _T_3792 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 469:60] + node _T_3793 = and(obuf_nosend, bus_rsp_read) @[el2_lsu_bus_buffer.scala 469:89] + node _T_3794 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[el2_lsu_bus_buffer.scala 469:124] + node _T_3795 = and(_T_3793, _T_3794) @[el2_lsu_bus_buffer.scala 469:104] + node _T_3796 = mux(_T_3795, UInt<3>("h05"), UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 469:75] + node _T_3797 = mux(_T_3792, UInt<3>("h00"), _T_3796) @[el2_lsu_bus_buffer.scala 469:31] + buf_nxtstate[2] <= _T_3797 @[el2_lsu_bus_buffer.scala 469:25] + node _T_3798 = eq(obuf_tag0, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 470:48] + node _T_3799 = eq(obuf_tag1, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 470:104] + node _T_3800 = and(obuf_merge, _T_3799) @[el2_lsu_bus_buffer.scala 470:91] + node _T_3801 = or(_T_3798, _T_3800) @[el2_lsu_bus_buffer.scala 470:77] + node _T_3802 = and(_T_3801, obuf_valid) @[el2_lsu_bus_buffer.scala 470:135] + node _T_3803 = and(_T_3802, obuf_wr_enQ) @[el2_lsu_bus_buffer.scala 470:148] + buf_cmd_state_bus_en[2] <= _T_3803 @[el2_lsu_bus_buffer.scala 470:33] + buf_state_bus_en[2] <= buf_cmd_state_bus_en[2] @[el2_lsu_bus_buffer.scala 471:29] + node _T_3804 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 472:49] + node _T_3805 = or(_T_3804, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 472:70] + buf_state_en[2] <= _T_3805 @[el2_lsu_bus_buffer.scala 472:25] + buf_ldfwd_in[2] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 473:25] + node _T_3806 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 474:56] + node _T_3807 = eq(_T_3806, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 474:46] + node _T_3808 = and(buf_state_en[2], _T_3807) @[el2_lsu_bus_buffer.scala 474:44] + node _T_3809 = and(_T_3808, obuf_nosend) @[el2_lsu_bus_buffer.scala 474:60] + node _T_3810 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 474:76] + node _T_3811 = and(_T_3809, _T_3810) @[el2_lsu_bus_buffer.scala 474:74] + buf_ldfwd_en[2] <= _T_3811 @[el2_lsu_bus_buffer.scala 474:25] + node _T_3812 = bits(obuf_rdrsp_tag, 1, 0) @[el2_lsu_bus_buffer.scala 475:46] + buf_ldfwdtag_in[2] <= _T_3812 @[el2_lsu_bus_buffer.scala 475:28] + node _T_3813 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 476:47] + node _T_3814 = and(_T_3813, obuf_nosend) @[el2_lsu_bus_buffer.scala 476:67] + node _T_3815 = and(_T_3814, bus_rsp_read) @[el2_lsu_bus_buffer.scala 476:81] + buf_data_en[2] <= _T_3815 @[el2_lsu_bus_buffer.scala 476:24] + node _T_3816 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 477:48] + node _T_3817 = and(_T_3816, obuf_nosend) @[el2_lsu_bus_buffer.scala 477:68] + node _T_3818 = and(_T_3817, bus_rsp_read_error) @[el2_lsu_bus_buffer.scala 477:82] + buf_error_en[2] <= _T_3818 @[el2_lsu_bus_buffer.scala 477:25] + node _T_3819 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 478:61] + node _T_3820 = bits(buf_addr[2], 2, 2) @[el2_lsu_bus_buffer.scala 478:85] + node _T_3821 = bits(bus_rsp_rdata, 63, 32) @[el2_lsu_bus_buffer.scala 478:103] + node _T_3822 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 478:126] + node _T_3823 = mux(_T_3820, _T_3821, _T_3822) @[el2_lsu_bus_buffer.scala 478:73] + node _T_3824 = mux(buf_error_en[2], _T_3819, _T_3823) @[el2_lsu_bus_buffer.scala 478:30] + buf_data_in[2] <= _T_3824 @[el2_lsu_bus_buffer.scala 478:24] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3825 = eq(UInt<3>("h03"), buf_state[2]) @[Conditional.scala 37:30] + when _T_3825 : @[Conditional.scala 39:67] + node _T_3826 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 481:67] + node _T_3827 = and(UInt<1>("h01"), bus_rsp_write_error) @[el2_lsu_bus_buffer.scala 481:94] + node _T_3828 = eq(_T_3827, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 481:73] + node _T_3829 = and(_T_3826, _T_3828) @[el2_lsu_bus_buffer.scala 481:71] + node _T_3830 = or(io.dec_tlu_force_halt, _T_3829) @[el2_lsu_bus_buffer.scala 481:55] + node _T_3831 = bits(_T_3830, 0, 0) @[el2_lsu_bus_buffer.scala 481:125] + node _T_3832 = eq(buf_samedw[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 482:30] + node _T_3833 = and(buf_dual[2], _T_3832) @[el2_lsu_bus_buffer.scala 482:28] + node _T_3834 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 482:57] + node _T_3835 = eq(_T_3834, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 482:47] + node _T_3836 = and(_T_3833, _T_3835) @[el2_lsu_bus_buffer.scala 482:45] + node _T_3837 = neq(buf_state[buf_dualtag[2]], UInt<3>("h04")) @[el2_lsu_bus_buffer.scala 482:90] + node _T_3838 = and(_T_3836, _T_3837) @[el2_lsu_bus_buffer.scala 482:61] + node _T_3839 = bits(buf_ldfwd, 2, 2) @[el2_lsu_bus_buffer.scala 483:27] + node _T_3840 = or(_T_3839, any_done_wait_state) @[el2_lsu_bus_buffer.scala 483:31] + node _T_3841 = eq(buf_samedw[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 483:70] + node _T_3842 = and(buf_dual[2], _T_3841) @[el2_lsu_bus_buffer.scala 483:68] + node _T_3843 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 483:97] + node _T_3844 = eq(_T_3843, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 483:87] + node _T_3845 = and(_T_3842, _T_3844) @[el2_lsu_bus_buffer.scala 483:85] + node _T_3846 = eq(buf_dualtag[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_3847 = bits(buf_ldfwd, 0, 0) @[el2_lsu_bus_buffer.scala 110:129] + node _T_3848 = eq(buf_dualtag[2], UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_3849 = bits(buf_ldfwd, 1, 1) @[el2_lsu_bus_buffer.scala 110:129] + node _T_3850 = eq(buf_dualtag[2], UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_3851 = bits(buf_ldfwd, 2, 2) @[el2_lsu_bus_buffer.scala 110:129] + node _T_3852 = eq(buf_dualtag[2], UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_3853 = bits(buf_ldfwd, 3, 3) @[el2_lsu_bus_buffer.scala 110:129] + node _T_3854 = mux(_T_3846, _T_3847, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3855 = mux(_T_3848, _T_3849, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3856 = mux(_T_3850, _T_3851, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3857 = mux(_T_3852, _T_3853, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3858 = or(_T_3854, _T_3855) @[Mux.scala 27:72] + node _T_3859 = or(_T_3858, _T_3856) @[Mux.scala 27:72] + node _T_3860 = or(_T_3859, _T_3857) @[Mux.scala 27:72] + wire _T_3861 : UInt<1> @[Mux.scala 27:72] + _T_3861 <= _T_3860 @[Mux.scala 27:72] + node _T_3862 = and(_T_3845, _T_3861) @[el2_lsu_bus_buffer.scala 483:101] + node _T_3863 = eq(buf_state[buf_dualtag[2]], UInt<3>("h04")) @[el2_lsu_bus_buffer.scala 483:167] + node _T_3864 = and(_T_3862, _T_3863) @[el2_lsu_bus_buffer.scala 483:138] + node _T_3865 = and(_T_3864, any_done_wait_state) @[el2_lsu_bus_buffer.scala 483:187] + node _T_3866 = or(_T_3840, _T_3865) @[el2_lsu_bus_buffer.scala 483:53] + node _T_3867 = mux(_T_3866, UInt<3>("h05"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 483:16] + node _T_3868 = mux(_T_3838, UInt<3>("h04"), _T_3867) @[el2_lsu_bus_buffer.scala 482:14] + node _T_3869 = mux(_T_3831, UInt<3>("h00"), _T_3868) @[el2_lsu_bus_buffer.scala 481:31] + buf_nxtstate[2] <= _T_3869 @[el2_lsu_bus_buffer.scala 481:25] + node _T_3870 = eq(bus_rsp_write_tag, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 484:73] + node _T_3871 = and(bus_rsp_write, _T_3870) @[el2_lsu_bus_buffer.scala 484:52] + node _T_3872 = eq(bus_rsp_read_tag, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 485:46] + node _T_3873 = bits(buf_ldfwd, 2, 2) @[el2_lsu_bus_buffer.scala 486:23] + node _T_3874 = eq(bus_rsp_read_tag, buf_ldfwdtag[2]) @[el2_lsu_bus_buffer.scala 486:47] + node _T_3875 = and(_T_3873, _T_3874) @[el2_lsu_bus_buffer.scala 486:27] + node _T_3876 = or(_T_3872, _T_3875) @[el2_lsu_bus_buffer.scala 485:77] + node _T_3877 = and(buf_dual[2], buf_dualhi[2]) @[el2_lsu_bus_buffer.scala 487:26] + node _T_3878 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 487:54] + node _T_3879 = not(_T_3878) @[el2_lsu_bus_buffer.scala 487:44] + node _T_3880 = and(_T_3877, _T_3879) @[el2_lsu_bus_buffer.scala 487:42] + node _T_3881 = and(_T_3880, buf_samedw[2]) @[el2_lsu_bus_buffer.scala 487:58] + node _T_3882 = eq(bus_rsp_read_tag, buf_dualtag[2]) @[el2_lsu_bus_buffer.scala 487:94] + node _T_3883 = and(_T_3881, _T_3882) @[el2_lsu_bus_buffer.scala 487:74] + node _T_3884 = or(_T_3876, _T_3883) @[el2_lsu_bus_buffer.scala 486:71] + node _T_3885 = and(bus_rsp_read, _T_3884) @[el2_lsu_bus_buffer.scala 485:25] + node _T_3886 = or(_T_3871, _T_3885) @[el2_lsu_bus_buffer.scala 484:105] + buf_resp_state_bus_en[2] <= _T_3886 @[el2_lsu_bus_buffer.scala 484:34] + buf_state_bus_en[2] <= buf_resp_state_bus_en[2] @[el2_lsu_bus_buffer.scala 488:29] + node _T_3887 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 489:49] + node _T_3888 = or(_T_3887, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 489:70] + buf_state_en[2] <= _T_3888 @[el2_lsu_bus_buffer.scala 489:25] + node _T_3889 = and(buf_state_bus_en[2], bus_rsp_read) @[el2_lsu_bus_buffer.scala 490:47] + node _T_3890 = and(_T_3889, io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 490:62] + buf_data_en[2] <= _T_3890 @[el2_lsu_bus_buffer.scala 490:24] + node _T_3891 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 491:48] + node _T_3892 = eq(bus_rsp_read_tag, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 491:111] + node _T_3893 = and(bus_rsp_read_error, _T_3892) @[el2_lsu_bus_buffer.scala 491:91] + node _T_3894 = bits(buf_ldfwd, 2, 2) @[el2_lsu_bus_buffer.scala 492:42] + node _T_3895 = and(bus_rsp_read_error, _T_3894) @[el2_lsu_bus_buffer.scala 492:31] + node _T_3896 = eq(bus_rsp_read_tag, buf_ldfwdtag[2]) @[el2_lsu_bus_buffer.scala 492:66] + node _T_3897 = and(_T_3895, _T_3896) @[el2_lsu_bus_buffer.scala 492:46] + node _T_3898 = or(_T_3893, _T_3897) @[el2_lsu_bus_buffer.scala 491:143] + node _T_3899 = and(bus_rsp_write_error, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 493:32] + node _T_3900 = eq(bus_rsp_write_tag, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 493:74] + node _T_3901 = and(_T_3899, _T_3900) @[el2_lsu_bus_buffer.scala 493:53] + node _T_3902 = or(_T_3898, _T_3901) @[el2_lsu_bus_buffer.scala 492:88] + node _T_3903 = and(_T_3891, _T_3902) @[el2_lsu_bus_buffer.scala 491:68] + buf_error_en[2] <= _T_3903 @[el2_lsu_bus_buffer.scala 491:25] + node _T_3904 = eq(buf_error_en[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 494:50] + node _T_3905 = and(buf_state_en[2], _T_3904) @[el2_lsu_bus_buffer.scala 494:48] + node _T_3906 = bits(buf_addr[2], 2, 2) @[el2_lsu_bus_buffer.scala 494:84] + node _T_3907 = bits(bus_rsp_rdata, 63, 32) @[el2_lsu_bus_buffer.scala 494:102] + node _T_3908 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 494:125] + node _T_3909 = mux(_T_3906, _T_3907, _T_3908) @[el2_lsu_bus_buffer.scala 494:72] + node _T_3910 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 494:148] + node _T_3911 = mux(_T_3905, _T_3909, _T_3910) @[el2_lsu_bus_buffer.scala 494:30] + buf_data_in[2] <= _T_3911 @[el2_lsu_bus_buffer.scala 494:24] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3912 = eq(UInt<3>("h04"), buf_state[2]) @[Conditional.scala 37:30] + when _T_3912 : @[Conditional.scala 39:67] + node _T_3913 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 497:60] + node _T_3914 = bits(buf_ldfwd, 2, 2) @[el2_lsu_bus_buffer.scala 497:86] + node _T_3915 = dshr(buf_ldfwd, buf_dualtag[2]) @[el2_lsu_bus_buffer.scala 497:101] + node _T_3916 = bits(_T_3915, 0, 0) @[el2_lsu_bus_buffer.scala 497:101] + node _T_3917 = or(_T_3914, _T_3916) @[el2_lsu_bus_buffer.scala 497:90] + node _T_3918 = or(_T_3917, any_done_wait_state) @[el2_lsu_bus_buffer.scala 497:118] + node _T_3919 = mux(_T_3918, UInt<3>("h05"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 497:75] + node _T_3920 = mux(_T_3913, UInt<3>("h00"), _T_3919) @[el2_lsu_bus_buffer.scala 497:31] + buf_nxtstate[2] <= _T_3920 @[el2_lsu_bus_buffer.scala 497:25] + node _T_3921 = eq(bus_rsp_read_tag, buf_dualtag[2]) @[el2_lsu_bus_buffer.scala 498:66] + node _T_3922 = dshr(buf_ldfwd, buf_dualtag[2]) @[el2_lsu_bus_buffer.scala 499:21] + node _T_3923 = bits(_T_3922, 0, 0) @[el2_lsu_bus_buffer.scala 499:21] + node _T_3924 = eq(bus_rsp_read_tag, buf_ldfwdtag[buf_dualtag[2]]) @[el2_lsu_bus_buffer.scala 499:58] + node _T_3925 = and(_T_3923, _T_3924) @[el2_lsu_bus_buffer.scala 499:38] + node _T_3926 = or(_T_3921, _T_3925) @[el2_lsu_bus_buffer.scala 498:95] + node _T_3927 = and(bus_rsp_read, _T_3926) @[el2_lsu_bus_buffer.scala 498:45] + buf_state_bus_en[2] <= _T_3927 @[el2_lsu_bus_buffer.scala 498:29] + node _T_3928 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 500:49] + node _T_3929 = or(_T_3928, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 500:70] + buf_state_en[2] <= _T_3929 @[el2_lsu_bus_buffer.scala 500:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3930 = eq(UInt<3>("h05"), buf_state[2]) @[Conditional.scala 37:30] + when _T_3930 : @[Conditional.scala 39:67] + node _T_3931 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 503:60] + node _T_3932 = mux(_T_3931, UInt<3>("h00"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 503:31] + buf_nxtstate[2] <= _T_3932 @[el2_lsu_bus_buffer.scala 503:25] + node _T_3933 = eq(RspPtr, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 504:37] + node _T_3934 = eq(buf_dualtag[2], RspPtr) @[el2_lsu_bus_buffer.scala 504:98] + node _T_3935 = and(buf_dual[2], _T_3934) @[el2_lsu_bus_buffer.scala 504:80] + node _T_3936 = or(_T_3933, _T_3935) @[el2_lsu_bus_buffer.scala 504:65] + node _T_3937 = or(_T_3936, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 504:112] + buf_state_en[2] <= _T_3937 @[el2_lsu_bus_buffer.scala 504:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3938 = eq(UInt<3>("h06"), buf_state[2]) @[Conditional.scala 37:30] + when _T_3938 : @[Conditional.scala 39:67] + buf_nxtstate[2] <= UInt<3>("h00") @[el2_lsu_bus_buffer.scala 507:25] + buf_rst[2] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 508:20] + buf_state_en[2] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 509:25] + buf_ldfwd_in[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 510:25] + buf_ldfwd_en[2] <= buf_state_en[2] @[el2_lsu_bus_buffer.scala 511:25] + skip @[Conditional.scala 39:67] + node _T_3939 = bits(buf_state_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 514:108] + reg _T_3940 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3939 : @[Reg.scala 28:19] + _T_3940 <= buf_nxtstate[2] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_state[2] <= _T_3940 @[el2_lsu_bus_buffer.scala 514:18] + reg _T_3941 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 515:60] + _T_3941 <= buf_age_in_2 @[el2_lsu_bus_buffer.scala 515:60] + buf_ageQ[2] <= _T_3941 @[el2_lsu_bus_buffer.scala 515:17] + reg _T_3942 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 516:63] + _T_3942 <= buf_rspage_in[2] @[el2_lsu_bus_buffer.scala 516:63] + buf_rspageQ[2] <= _T_3942 @[el2_lsu_bus_buffer.scala 516:20] + node _T_3943 = bits(buf_wr_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 517:109] + reg _T_3944 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3943 : @[Reg.scala 28:19] + _T_3944 <= buf_dualtag_in[2] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dualtag[2] <= _T_3944 @[el2_lsu_bus_buffer.scala 517:20] + node _T_3945 = bits(buf_dual_in, 2, 2) @[el2_lsu_bus_buffer.scala 518:74] + node _T_3946 = bits(buf_wr_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 518:107] + reg _T_3947 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3946 : @[Reg.scala 28:19] + _T_3947 <= _T_3945 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dual[2] <= _T_3947 @[el2_lsu_bus_buffer.scala 518:17] + node _T_3948 = bits(buf_samedw_in, 2, 2) @[el2_lsu_bus_buffer.scala 519:78] + node _T_3949 = bits(buf_wr_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 519:111] + reg _T_3950 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3949 : @[Reg.scala 28:19] + _T_3950 <= _T_3948 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_samedw[2] <= _T_3950 @[el2_lsu_bus_buffer.scala 519:19] + node _T_3951 = bits(buf_nomerge_in, 2, 2) @[el2_lsu_bus_buffer.scala 520:80] + node _T_3952 = bits(buf_wr_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 520:113] + reg _T_3953 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3952 : @[Reg.scala 28:19] + _T_3953 <= _T_3951 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_nomerge[2] <= _T_3953 @[el2_lsu_bus_buffer.scala 520:20] + node _T_3954 = bits(buf_dualhi_in, 2, 2) @[el2_lsu_bus_buffer.scala 521:78] + node _T_3955 = bits(buf_wr_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 521:111] + reg _T_3956 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3955 : @[Reg.scala 28:19] + _T_3956 <= _T_3954 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dualhi[2] <= _T_3956 @[el2_lsu_bus_buffer.scala 521:19] + node _T_3957 = eq(UInt<3>("h00"), buf_state[3]) @[Conditional.scala 37:30] + when _T_3957 : @[Conditional.scala 40:58] + node _T_3958 = bits(io.lsu_bus_clk_en, 0, 0) @[el2_lsu_bus_buffer.scala 458:56] + node _T_3959 = mux(_T_3958, UInt<3>("h02"), UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 458:31] + buf_nxtstate[3] <= _T_3959 @[el2_lsu_bus_buffer.scala 458:25] + node _T_3960 = and(io.lsu_busreq_r, io.lsu_commit_r) @[el2_lsu_bus_buffer.scala 459:45] + node _T_3961 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 459:77] + node _T_3962 = eq(ibuf_merge_en, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 459:97] + node _T_3963 = and(_T_3961, _T_3962) @[el2_lsu_bus_buffer.scala 459:95] + node _T_3964 = eq(UInt<2>("h03"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 459:117] + node _T_3965 = and(_T_3963, _T_3964) @[el2_lsu_bus_buffer.scala 459:112] + node _T_3966 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 459:144] + node _T_3967 = eq(UInt<2>("h03"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 459:166] + node _T_3968 = and(_T_3966, _T_3967) @[el2_lsu_bus_buffer.scala 459:161] + node _T_3969 = or(_T_3965, _T_3968) @[el2_lsu_bus_buffer.scala 459:132] + node _T_3970 = and(_T_3960, _T_3969) @[el2_lsu_bus_buffer.scala 459:63] + node _T_3971 = eq(UInt<2>("h03"), ibuf_tag) @[el2_lsu_bus_buffer.scala 459:206] + node _T_3972 = and(ibuf_drain_vld, _T_3971) @[el2_lsu_bus_buffer.scala 459:201] + node _T_3973 = or(_T_3970, _T_3972) @[el2_lsu_bus_buffer.scala 459:183] + buf_state_en[3] <= _T_3973 @[el2_lsu_bus_buffer.scala 459:25] + buf_wr_en[3] <= buf_state_en[3] @[el2_lsu_bus_buffer.scala 460:22] + buf_data_en[3] <= buf_state_en[3] @[el2_lsu_bus_buffer.scala 461:24] + node _T_3974 = eq(UInt<2>("h03"), ibuf_tag) @[el2_lsu_bus_buffer.scala 462:52] + node _T_3975 = and(ibuf_drain_vld, _T_3974) @[el2_lsu_bus_buffer.scala 462:47] + node _T_3976 = bits(_T_3975, 0, 0) @[el2_lsu_bus_buffer.scala 462:73] + node _T_3977 = bits(ibuf_data_out, 31, 0) @[el2_lsu_bus_buffer.scala 462:90] + node _T_3978 = bits(store_data_lo_r, 31, 0) @[el2_lsu_bus_buffer.scala 462:114] + node _T_3979 = mux(_T_3976, _T_3977, _T_3978) @[el2_lsu_bus_buffer.scala 462:30] + buf_data_in[3] <= _T_3979 @[el2_lsu_bus_buffer.scala 462:24] + skip @[Conditional.scala 40:58] + else : @[Conditional.scala 39:67] + node _T_3980 = eq(UInt<3>("h01"), buf_state[3]) @[Conditional.scala 37:30] + when _T_3980 : @[Conditional.scala 39:67] + node _T_3981 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 465:60] + node _T_3982 = mux(_T_3981, UInt<3>("h00"), UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 465:31] + buf_nxtstate[3] <= _T_3982 @[el2_lsu_bus_buffer.scala 465:25] + node _T_3983 = or(io.lsu_bus_clk_en, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 466:46] + buf_state_en[3] <= _T_3983 @[el2_lsu_bus_buffer.scala 466:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3984 = eq(UInt<3>("h02"), buf_state[3]) @[Conditional.scala 37:30] + when _T_3984 : @[Conditional.scala 39:67] + node _T_3985 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 469:60] + node _T_3986 = and(obuf_nosend, bus_rsp_read) @[el2_lsu_bus_buffer.scala 469:89] + node _T_3987 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[el2_lsu_bus_buffer.scala 469:124] + node _T_3988 = and(_T_3986, _T_3987) @[el2_lsu_bus_buffer.scala 469:104] + node _T_3989 = mux(_T_3988, UInt<3>("h05"), UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 469:75] + node _T_3990 = mux(_T_3985, UInt<3>("h00"), _T_3989) @[el2_lsu_bus_buffer.scala 469:31] + buf_nxtstate[3] <= _T_3990 @[el2_lsu_bus_buffer.scala 469:25] + node _T_3991 = eq(obuf_tag0, UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 470:48] + node _T_3992 = eq(obuf_tag1, UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 470:104] + node _T_3993 = and(obuf_merge, _T_3992) @[el2_lsu_bus_buffer.scala 470:91] + node _T_3994 = or(_T_3991, _T_3993) @[el2_lsu_bus_buffer.scala 470:77] + node _T_3995 = and(_T_3994, obuf_valid) @[el2_lsu_bus_buffer.scala 470:135] + node _T_3996 = and(_T_3995, obuf_wr_enQ) @[el2_lsu_bus_buffer.scala 470:148] + buf_cmd_state_bus_en[3] <= _T_3996 @[el2_lsu_bus_buffer.scala 470:33] + buf_state_bus_en[3] <= buf_cmd_state_bus_en[3] @[el2_lsu_bus_buffer.scala 471:29] + node _T_3997 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 472:49] + node _T_3998 = or(_T_3997, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 472:70] + buf_state_en[3] <= _T_3998 @[el2_lsu_bus_buffer.scala 472:25] + buf_ldfwd_in[3] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 473:25] + node _T_3999 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 474:56] + node _T_4000 = eq(_T_3999, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 474:46] + node _T_4001 = and(buf_state_en[3], _T_4000) @[el2_lsu_bus_buffer.scala 474:44] + node _T_4002 = and(_T_4001, obuf_nosend) @[el2_lsu_bus_buffer.scala 474:60] + node _T_4003 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 474:76] + node _T_4004 = and(_T_4002, _T_4003) @[el2_lsu_bus_buffer.scala 474:74] + buf_ldfwd_en[3] <= _T_4004 @[el2_lsu_bus_buffer.scala 474:25] + node _T_4005 = bits(obuf_rdrsp_tag, 1, 0) @[el2_lsu_bus_buffer.scala 475:46] + buf_ldfwdtag_in[3] <= _T_4005 @[el2_lsu_bus_buffer.scala 475:28] + node _T_4006 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 476:47] + node _T_4007 = and(_T_4006, obuf_nosend) @[el2_lsu_bus_buffer.scala 476:67] + node _T_4008 = and(_T_4007, bus_rsp_read) @[el2_lsu_bus_buffer.scala 476:81] + buf_data_en[3] <= _T_4008 @[el2_lsu_bus_buffer.scala 476:24] + node _T_4009 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 477:48] + node _T_4010 = and(_T_4009, obuf_nosend) @[el2_lsu_bus_buffer.scala 477:68] + node _T_4011 = and(_T_4010, bus_rsp_read_error) @[el2_lsu_bus_buffer.scala 477:82] + buf_error_en[3] <= _T_4011 @[el2_lsu_bus_buffer.scala 477:25] + node _T_4012 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 478:61] + node _T_4013 = bits(buf_addr[3], 2, 2) @[el2_lsu_bus_buffer.scala 478:85] + node _T_4014 = bits(bus_rsp_rdata, 63, 32) @[el2_lsu_bus_buffer.scala 478:103] + node _T_4015 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 478:126] + node _T_4016 = mux(_T_4013, _T_4014, _T_4015) @[el2_lsu_bus_buffer.scala 478:73] + node _T_4017 = mux(buf_error_en[3], _T_4012, _T_4016) @[el2_lsu_bus_buffer.scala 478:30] + buf_data_in[3] <= _T_4017 @[el2_lsu_bus_buffer.scala 478:24] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_4018 = eq(UInt<3>("h03"), buf_state[3]) @[Conditional.scala 37:30] + when _T_4018 : @[Conditional.scala 39:67] + node _T_4019 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 481:67] + node _T_4020 = and(UInt<1>("h01"), bus_rsp_write_error) @[el2_lsu_bus_buffer.scala 481:94] + node _T_4021 = eq(_T_4020, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 481:73] + node _T_4022 = and(_T_4019, _T_4021) @[el2_lsu_bus_buffer.scala 481:71] + node _T_4023 = or(io.dec_tlu_force_halt, _T_4022) @[el2_lsu_bus_buffer.scala 481:55] + node _T_4024 = bits(_T_4023, 0, 0) @[el2_lsu_bus_buffer.scala 481:125] + node _T_4025 = eq(buf_samedw[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 482:30] + node _T_4026 = and(buf_dual[3], _T_4025) @[el2_lsu_bus_buffer.scala 482:28] + node _T_4027 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 482:57] + node _T_4028 = eq(_T_4027, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 482:47] + node _T_4029 = and(_T_4026, _T_4028) @[el2_lsu_bus_buffer.scala 482:45] + node _T_4030 = neq(buf_state[buf_dualtag[3]], UInt<3>("h04")) @[el2_lsu_bus_buffer.scala 482:90] + node _T_4031 = and(_T_4029, _T_4030) @[el2_lsu_bus_buffer.scala 482:61] + node _T_4032 = bits(buf_ldfwd, 3, 3) @[el2_lsu_bus_buffer.scala 483:27] + node _T_4033 = or(_T_4032, any_done_wait_state) @[el2_lsu_bus_buffer.scala 483:31] + node _T_4034 = eq(buf_samedw[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 483:70] + node _T_4035 = and(buf_dual[3], _T_4034) @[el2_lsu_bus_buffer.scala 483:68] + node _T_4036 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 483:97] + node _T_4037 = eq(_T_4036, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 483:87] + node _T_4038 = and(_T_4035, _T_4037) @[el2_lsu_bus_buffer.scala 483:85] + node _T_4039 = eq(buf_dualtag[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_4040 = bits(buf_ldfwd, 0, 0) @[el2_lsu_bus_buffer.scala 110:129] + node _T_4041 = eq(buf_dualtag[3], UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_4042 = bits(buf_ldfwd, 1, 1) @[el2_lsu_bus_buffer.scala 110:129] + node _T_4043 = eq(buf_dualtag[3], UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_4044 = bits(buf_ldfwd, 2, 2) @[el2_lsu_bus_buffer.scala 110:129] + node _T_4045 = eq(buf_dualtag[3], UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_4046 = bits(buf_ldfwd, 3, 3) @[el2_lsu_bus_buffer.scala 110:129] + node _T_4047 = mux(_T_4039, _T_4040, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4048 = mux(_T_4041, _T_4042, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4049 = mux(_T_4043, _T_4044, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4050 = mux(_T_4045, _T_4046, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4051 = or(_T_4047, _T_4048) @[Mux.scala 27:72] + node _T_4052 = or(_T_4051, _T_4049) @[Mux.scala 27:72] + node _T_4053 = or(_T_4052, _T_4050) @[Mux.scala 27:72] + wire _T_4054 : UInt<1> @[Mux.scala 27:72] + _T_4054 <= _T_4053 @[Mux.scala 27:72] + node _T_4055 = and(_T_4038, _T_4054) @[el2_lsu_bus_buffer.scala 483:101] + node _T_4056 = eq(buf_state[buf_dualtag[3]], UInt<3>("h04")) @[el2_lsu_bus_buffer.scala 483:167] + node _T_4057 = and(_T_4055, _T_4056) @[el2_lsu_bus_buffer.scala 483:138] + node _T_4058 = and(_T_4057, any_done_wait_state) @[el2_lsu_bus_buffer.scala 483:187] + node _T_4059 = or(_T_4033, _T_4058) @[el2_lsu_bus_buffer.scala 483:53] + node _T_4060 = mux(_T_4059, UInt<3>("h05"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 483:16] + node _T_4061 = mux(_T_4031, UInt<3>("h04"), _T_4060) @[el2_lsu_bus_buffer.scala 482:14] + node _T_4062 = mux(_T_4024, UInt<3>("h00"), _T_4061) @[el2_lsu_bus_buffer.scala 481:31] + buf_nxtstate[3] <= _T_4062 @[el2_lsu_bus_buffer.scala 481:25] + node _T_4063 = eq(bus_rsp_write_tag, UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 484:73] + node _T_4064 = and(bus_rsp_write, _T_4063) @[el2_lsu_bus_buffer.scala 484:52] + node _T_4065 = eq(bus_rsp_read_tag, UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 485:46] + node _T_4066 = bits(buf_ldfwd, 3, 3) @[el2_lsu_bus_buffer.scala 486:23] + node _T_4067 = eq(bus_rsp_read_tag, buf_ldfwdtag[3]) @[el2_lsu_bus_buffer.scala 486:47] + node _T_4068 = and(_T_4066, _T_4067) @[el2_lsu_bus_buffer.scala 486:27] + node _T_4069 = or(_T_4065, _T_4068) @[el2_lsu_bus_buffer.scala 485:77] + node _T_4070 = and(buf_dual[3], buf_dualhi[3]) @[el2_lsu_bus_buffer.scala 487:26] + node _T_4071 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 487:54] + node _T_4072 = not(_T_4071) @[el2_lsu_bus_buffer.scala 487:44] + node _T_4073 = and(_T_4070, _T_4072) @[el2_lsu_bus_buffer.scala 487:42] + node _T_4074 = and(_T_4073, buf_samedw[3]) @[el2_lsu_bus_buffer.scala 487:58] + node _T_4075 = eq(bus_rsp_read_tag, buf_dualtag[3]) @[el2_lsu_bus_buffer.scala 487:94] + node _T_4076 = and(_T_4074, _T_4075) @[el2_lsu_bus_buffer.scala 487:74] + node _T_4077 = or(_T_4069, _T_4076) @[el2_lsu_bus_buffer.scala 486:71] + node _T_4078 = and(bus_rsp_read, _T_4077) @[el2_lsu_bus_buffer.scala 485:25] + node _T_4079 = or(_T_4064, _T_4078) @[el2_lsu_bus_buffer.scala 484:105] + buf_resp_state_bus_en[3] <= _T_4079 @[el2_lsu_bus_buffer.scala 484:34] + buf_state_bus_en[3] <= buf_resp_state_bus_en[3] @[el2_lsu_bus_buffer.scala 488:29] + node _T_4080 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 489:49] + node _T_4081 = or(_T_4080, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 489:70] + buf_state_en[3] <= _T_4081 @[el2_lsu_bus_buffer.scala 489:25] + node _T_4082 = and(buf_state_bus_en[3], bus_rsp_read) @[el2_lsu_bus_buffer.scala 490:47] + node _T_4083 = and(_T_4082, io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 490:62] + buf_data_en[3] <= _T_4083 @[el2_lsu_bus_buffer.scala 490:24] + node _T_4084 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 491:48] + node _T_4085 = eq(bus_rsp_read_tag, UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 491:111] + node _T_4086 = and(bus_rsp_read_error, _T_4085) @[el2_lsu_bus_buffer.scala 491:91] + node _T_4087 = bits(buf_ldfwd, 3, 3) @[el2_lsu_bus_buffer.scala 492:42] + node _T_4088 = and(bus_rsp_read_error, _T_4087) @[el2_lsu_bus_buffer.scala 492:31] + node _T_4089 = eq(bus_rsp_read_tag, buf_ldfwdtag[3]) @[el2_lsu_bus_buffer.scala 492:66] + node _T_4090 = and(_T_4088, _T_4089) @[el2_lsu_bus_buffer.scala 492:46] + node _T_4091 = or(_T_4086, _T_4090) @[el2_lsu_bus_buffer.scala 491:143] + node _T_4092 = and(bus_rsp_write_error, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 493:32] + node _T_4093 = eq(bus_rsp_write_tag, UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 493:74] + node _T_4094 = and(_T_4092, _T_4093) @[el2_lsu_bus_buffer.scala 493:53] + node _T_4095 = or(_T_4091, _T_4094) @[el2_lsu_bus_buffer.scala 492:88] + node _T_4096 = and(_T_4084, _T_4095) @[el2_lsu_bus_buffer.scala 491:68] + buf_error_en[3] <= _T_4096 @[el2_lsu_bus_buffer.scala 491:25] + node _T_4097 = eq(buf_error_en[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 494:50] + node _T_4098 = and(buf_state_en[3], _T_4097) @[el2_lsu_bus_buffer.scala 494:48] + node _T_4099 = bits(buf_addr[3], 2, 2) @[el2_lsu_bus_buffer.scala 494:84] + node _T_4100 = bits(bus_rsp_rdata, 63, 32) @[el2_lsu_bus_buffer.scala 494:102] + node _T_4101 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 494:125] + node _T_4102 = mux(_T_4099, _T_4100, _T_4101) @[el2_lsu_bus_buffer.scala 494:72] + node _T_4103 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 494:148] + node _T_4104 = mux(_T_4098, _T_4102, _T_4103) @[el2_lsu_bus_buffer.scala 494:30] + buf_data_in[3] <= _T_4104 @[el2_lsu_bus_buffer.scala 494:24] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_4105 = eq(UInt<3>("h04"), buf_state[3]) @[Conditional.scala 37:30] + when _T_4105 : @[Conditional.scala 39:67] + node _T_4106 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 497:60] + node _T_4107 = bits(buf_ldfwd, 3, 3) @[el2_lsu_bus_buffer.scala 497:86] + node _T_4108 = dshr(buf_ldfwd, buf_dualtag[3]) @[el2_lsu_bus_buffer.scala 497:101] + node _T_4109 = bits(_T_4108, 0, 0) @[el2_lsu_bus_buffer.scala 497:101] + node _T_4110 = or(_T_4107, _T_4109) @[el2_lsu_bus_buffer.scala 497:90] + node _T_4111 = or(_T_4110, any_done_wait_state) @[el2_lsu_bus_buffer.scala 497:118] + node _T_4112 = mux(_T_4111, UInt<3>("h05"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 497:75] + node _T_4113 = mux(_T_4106, UInt<3>("h00"), _T_4112) @[el2_lsu_bus_buffer.scala 497:31] + buf_nxtstate[3] <= _T_4113 @[el2_lsu_bus_buffer.scala 497:25] + node _T_4114 = eq(bus_rsp_read_tag, buf_dualtag[3]) @[el2_lsu_bus_buffer.scala 498:66] + node _T_4115 = dshr(buf_ldfwd, buf_dualtag[3]) @[el2_lsu_bus_buffer.scala 499:21] + node _T_4116 = bits(_T_4115, 0, 0) @[el2_lsu_bus_buffer.scala 499:21] + node _T_4117 = eq(bus_rsp_read_tag, buf_ldfwdtag[buf_dualtag[3]]) @[el2_lsu_bus_buffer.scala 499:58] + node _T_4118 = and(_T_4116, _T_4117) @[el2_lsu_bus_buffer.scala 499:38] + node _T_4119 = or(_T_4114, _T_4118) @[el2_lsu_bus_buffer.scala 498:95] + node _T_4120 = and(bus_rsp_read, _T_4119) @[el2_lsu_bus_buffer.scala 498:45] + buf_state_bus_en[3] <= _T_4120 @[el2_lsu_bus_buffer.scala 498:29] + node _T_4121 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 500:49] + node _T_4122 = or(_T_4121, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 500:70] + buf_state_en[3] <= _T_4122 @[el2_lsu_bus_buffer.scala 500:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_4123 = eq(UInt<3>("h05"), buf_state[3]) @[Conditional.scala 37:30] + when _T_4123 : @[Conditional.scala 39:67] + node _T_4124 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 503:60] + node _T_4125 = mux(_T_4124, UInt<3>("h00"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 503:31] + buf_nxtstate[3] <= _T_4125 @[el2_lsu_bus_buffer.scala 503:25] + node _T_4126 = eq(RspPtr, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 504:37] + node _T_4127 = eq(buf_dualtag[3], RspPtr) @[el2_lsu_bus_buffer.scala 504:98] + node _T_4128 = and(buf_dual[3], _T_4127) @[el2_lsu_bus_buffer.scala 504:80] + node _T_4129 = or(_T_4126, _T_4128) @[el2_lsu_bus_buffer.scala 504:65] + node _T_4130 = or(_T_4129, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 504:112] + buf_state_en[3] <= _T_4130 @[el2_lsu_bus_buffer.scala 504:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_4131 = eq(UInt<3>("h06"), buf_state[3]) @[Conditional.scala 37:30] + when _T_4131 : @[Conditional.scala 39:67] + buf_nxtstate[3] <= UInt<3>("h00") @[el2_lsu_bus_buffer.scala 507:25] + buf_rst[3] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 508:20] + buf_state_en[3] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 509:25] + buf_ldfwd_in[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 510:25] + buf_ldfwd_en[3] <= buf_state_en[3] @[el2_lsu_bus_buffer.scala 511:25] + skip @[Conditional.scala 39:67] + node _T_4132 = bits(buf_state_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 514:108] + reg _T_4133 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4132 : @[Reg.scala 28:19] + _T_4133 <= buf_nxtstate[3] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_state[3] <= _T_4133 @[el2_lsu_bus_buffer.scala 514:18] + reg _T_4134 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 515:60] + _T_4134 <= buf_age_in_3 @[el2_lsu_bus_buffer.scala 515:60] + buf_ageQ[3] <= _T_4134 @[el2_lsu_bus_buffer.scala 515:17] + reg _T_4135 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 516:63] + _T_4135 <= buf_rspage_in[3] @[el2_lsu_bus_buffer.scala 516:63] + buf_rspageQ[3] <= _T_4135 @[el2_lsu_bus_buffer.scala 516:20] + node _T_4136 = bits(buf_wr_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 517:109] + reg _T_4137 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4136 : @[Reg.scala 28:19] + _T_4137 <= buf_dualtag_in[3] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dualtag[3] <= _T_4137 @[el2_lsu_bus_buffer.scala 517:20] + node _T_4138 = bits(buf_dual_in, 3, 3) @[el2_lsu_bus_buffer.scala 518:74] + node _T_4139 = bits(buf_wr_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 518:107] + reg _T_4140 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4139 : @[Reg.scala 28:19] + _T_4140 <= _T_4138 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dual[3] <= _T_4140 @[el2_lsu_bus_buffer.scala 518:17] + node _T_4141 = bits(buf_samedw_in, 3, 3) @[el2_lsu_bus_buffer.scala 519:78] + node _T_4142 = bits(buf_wr_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 519:111] + reg _T_4143 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4142 : @[Reg.scala 28:19] + _T_4143 <= _T_4141 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_samedw[3] <= _T_4143 @[el2_lsu_bus_buffer.scala 519:19] + node _T_4144 = bits(buf_nomerge_in, 3, 3) @[el2_lsu_bus_buffer.scala 520:80] + node _T_4145 = bits(buf_wr_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 520:113] + reg _T_4146 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4145 : @[Reg.scala 28:19] + _T_4146 <= _T_4144 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_nomerge[3] <= _T_4146 @[el2_lsu_bus_buffer.scala 520:20] + node _T_4147 = bits(buf_dualhi_in, 3, 3) @[el2_lsu_bus_buffer.scala 521:78] + node _T_4148 = bits(buf_wr_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 521:111] + reg _T_4149 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4148 : @[Reg.scala 28:19] + _T_4149 <= _T_4147 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dualhi[3] <= _T_4149 @[el2_lsu_bus_buffer.scala 521:19] + node _T_4150 = bits(buf_ldfwd_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 524:133] + reg _T_4151 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4150 : @[Reg.scala 28:19] + _T_4151 <= buf_ldfwd_in[0] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4152 = bits(buf_ldfwd_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 524:133] + reg _T_4153 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4152 : @[Reg.scala 28:19] + _T_4153 <= buf_ldfwd_in[1] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4154 = bits(buf_ldfwd_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 524:133] + reg _T_4155 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4154 : @[Reg.scala 28:19] + _T_4155 <= buf_ldfwd_in[2] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4156 = bits(buf_ldfwd_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 524:133] + reg _T_4157 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4156 : @[Reg.scala 28:19] + _T_4157 <= buf_ldfwd_in[3] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4158 = cat(_T_4157, _T_4155) @[Cat.scala 29:58] + node _T_4159 = cat(_T_4158, _T_4153) @[Cat.scala 29:58] + node _T_4160 = cat(_T_4159, _T_4151) @[Cat.scala 29:58] + buf_ldfwd <= _T_4160 @[el2_lsu_bus_buffer.scala 524:15] + node _T_4161 = bits(buf_ldfwd_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 525:134] + reg _T_4162 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4161 : @[Reg.scala 28:19] + _T_4162 <= buf_ldfwdtag_in[0] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4163 = bits(buf_ldfwd_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 525:134] + reg _T_4164 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4163 : @[Reg.scala 28:19] + _T_4164 <= buf_ldfwdtag_in[1] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4165 = bits(buf_ldfwd_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 525:134] + reg _T_4166 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4165 : @[Reg.scala 28:19] + _T_4166 <= buf_ldfwdtag_in[2] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4167 = bits(buf_ldfwd_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 525:134] + reg _T_4168 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4167 : @[Reg.scala 28:19] + _T_4168 <= buf_ldfwdtag_in[3] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_ldfwdtag[0] <= _T_4162 @[el2_lsu_bus_buffer.scala 525:18] + buf_ldfwdtag[1] <= _T_4164 @[el2_lsu_bus_buffer.scala 525:18] + buf_ldfwdtag[2] <= _T_4166 @[el2_lsu_bus_buffer.scala 525:18] + buf_ldfwdtag[3] <= _T_4168 @[el2_lsu_bus_buffer.scala 525:18] + node _T_4169 = bits(buf_sideeffect_in, 0, 0) @[el2_lsu_bus_buffer.scala 526:107] + node _T_4170 = bits(buf_wr_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 526:140] + reg _T_4171 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4170 : @[Reg.scala 28:19] + _T_4171 <= _T_4169 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4172 = bits(buf_sideeffect_in, 1, 1) @[el2_lsu_bus_buffer.scala 526:107] + node _T_4173 = bits(buf_wr_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 526:140] + reg _T_4174 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4173 : @[Reg.scala 28:19] + _T_4174 <= _T_4172 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4175 = bits(buf_sideeffect_in, 2, 2) @[el2_lsu_bus_buffer.scala 526:107] + node _T_4176 = bits(buf_wr_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 526:140] + reg _T_4177 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4176 : @[Reg.scala 28:19] + _T_4177 <= _T_4175 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4178 = bits(buf_sideeffect_in, 3, 3) @[el2_lsu_bus_buffer.scala 526:107] + node _T_4179 = bits(buf_wr_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 526:140] + reg _T_4180 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4179 : @[Reg.scala 28:19] + _T_4180 <= _T_4178 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4181 = cat(_T_4180, _T_4177) @[Cat.scala 29:58] + node _T_4182 = cat(_T_4181, _T_4174) @[Cat.scala 29:58] + node _T_4183 = cat(_T_4182, _T_4171) @[Cat.scala 29:58] + buf_sideeffect <= _T_4183 @[el2_lsu_bus_buffer.scala 526:20] + node _T_4184 = bits(buf_unsign_in, 0, 0) @[el2_lsu_bus_buffer.scala 527:99] + node _T_4185 = bits(buf_wr_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 527:132] + reg _T_4186 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4185 : @[Reg.scala 28:19] + _T_4186 <= _T_4184 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4187 = bits(buf_unsign_in, 1, 1) @[el2_lsu_bus_buffer.scala 527:99] + node _T_4188 = bits(buf_wr_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 527:132] + reg _T_4189 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4188 : @[Reg.scala 28:19] + _T_4189 <= _T_4187 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4190 = bits(buf_unsign_in, 2, 2) @[el2_lsu_bus_buffer.scala 527:99] + node _T_4191 = bits(buf_wr_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 527:132] + reg _T_4192 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4191 : @[Reg.scala 28:19] + _T_4192 <= _T_4190 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4193 = bits(buf_unsign_in, 3, 3) @[el2_lsu_bus_buffer.scala 527:99] + node _T_4194 = bits(buf_wr_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 527:132] + reg _T_4195 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4194 : @[Reg.scala 28:19] + _T_4195 <= _T_4193 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4196 = cat(_T_4195, _T_4192) @[Cat.scala 29:58] + node _T_4197 = cat(_T_4196, _T_4189) @[Cat.scala 29:58] + node _T_4198 = cat(_T_4197, _T_4186) @[Cat.scala 29:58] + buf_unsign <= _T_4198 @[el2_lsu_bus_buffer.scala 527:16] + node _T_4199 = bits(buf_write_in, 0, 0) @[el2_lsu_bus_buffer.scala 528:97] + node _T_4200 = bits(buf_wr_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 528:130] + reg _T_4201 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4200 : @[Reg.scala 28:19] + _T_4201 <= _T_4199 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4202 = bits(buf_write_in, 1, 1) @[el2_lsu_bus_buffer.scala 528:97] + node _T_4203 = bits(buf_wr_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 528:130] + reg _T_4204 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4203 : @[Reg.scala 28:19] + _T_4204 <= _T_4202 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4205 = bits(buf_write_in, 2, 2) @[el2_lsu_bus_buffer.scala 528:97] + node _T_4206 = bits(buf_wr_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 528:130] + reg _T_4207 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4206 : @[Reg.scala 28:19] + _T_4207 <= _T_4205 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4208 = bits(buf_write_in, 3, 3) @[el2_lsu_bus_buffer.scala 528:97] + node _T_4209 = bits(buf_wr_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 528:130] + reg _T_4210 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4209 : @[Reg.scala 28:19] + _T_4210 <= _T_4208 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4211 = cat(_T_4210, _T_4207) @[Cat.scala 29:58] + node _T_4212 = cat(_T_4211, _T_4204) @[Cat.scala 29:58] + node _T_4213 = cat(_T_4212, _T_4201) @[Cat.scala 29:58] + buf_write <= _T_4213 @[el2_lsu_bus_buffer.scala 528:15] + node _T_4214 = bits(buf_wr_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 529:119] + reg _T_4215 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4214 : @[Reg.scala 28:19] + _T_4215 <= buf_sz_in[0] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4216 = bits(buf_wr_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 529:119] + reg _T_4217 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4216 : @[Reg.scala 28:19] + _T_4217 <= buf_sz_in[1] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4218 = bits(buf_wr_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 529:119] + reg _T_4219 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4218 : @[Reg.scala 28:19] + _T_4219 <= buf_sz_in[2] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4220 = bits(buf_wr_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 529:119] + reg _T_4221 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4220 : @[Reg.scala 28:19] + _T_4221 <= buf_sz_in[3] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_sz[0] <= _T_4215 @[el2_lsu_bus_buffer.scala 529:12] + buf_sz[1] <= _T_4217 @[el2_lsu_bus_buffer.scala 529:12] + buf_sz[2] <= _T_4219 @[el2_lsu_bus_buffer.scala 529:12] + buf_sz[3] <= _T_4221 @[el2_lsu_bus_buffer.scala 529:12] + node _T_4222 = bits(buf_wr_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 530:82] + inst rvclkhdr_4 of rvclkhdr_4 @[el2_lib.scala 472:23] + rvclkhdr_4.clock <= clock + rvclkhdr_4.reset <= reset + rvclkhdr_4.io.clk <= clock @[el2_lib.scala 474:18] + rvclkhdr_4.io.en <= _T_4222 @[el2_lib.scala 475:17] + rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 476:24] + reg _T_4223 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 478:16] + _T_4223 <= buf_addr_in[0] @[el2_lib.scala 478:16] + node _T_4224 = bits(buf_wr_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 530:82] + inst rvclkhdr_5 of rvclkhdr_5 @[el2_lib.scala 472:23] + rvclkhdr_5.clock <= clock + rvclkhdr_5.reset <= reset + rvclkhdr_5.io.clk <= clock @[el2_lib.scala 474:18] + rvclkhdr_5.io.en <= _T_4224 @[el2_lib.scala 475:17] + rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 476:24] + reg _T_4225 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 478:16] + _T_4225 <= buf_addr_in[1] @[el2_lib.scala 478:16] + node _T_4226 = bits(buf_wr_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 530:82] + inst rvclkhdr_6 of rvclkhdr_6 @[el2_lib.scala 472:23] + rvclkhdr_6.clock <= clock + rvclkhdr_6.reset <= reset + rvclkhdr_6.io.clk <= clock @[el2_lib.scala 474:18] + rvclkhdr_6.io.en <= _T_4226 @[el2_lib.scala 475:17] + rvclkhdr_6.io.scan_mode <= io.scan_mode @[el2_lib.scala 476:24] + reg _T_4227 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 478:16] + _T_4227 <= buf_addr_in[2] @[el2_lib.scala 478:16] + node _T_4228 = bits(buf_wr_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 530:82] + inst rvclkhdr_7 of rvclkhdr_7 @[el2_lib.scala 472:23] + rvclkhdr_7.clock <= clock + rvclkhdr_7.reset <= reset + rvclkhdr_7.io.clk <= clock @[el2_lib.scala 474:18] + rvclkhdr_7.io.en <= _T_4228 @[el2_lib.scala 475:17] + rvclkhdr_7.io.scan_mode <= io.scan_mode @[el2_lib.scala 476:24] + reg _T_4229 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 478:16] + _T_4229 <= buf_addr_in[3] @[el2_lib.scala 478:16] + buf_addr[0] <= _T_4223 @[el2_lsu_bus_buffer.scala 530:14] + buf_addr[1] <= _T_4225 @[el2_lsu_bus_buffer.scala 530:14] + buf_addr[2] <= _T_4227 @[el2_lsu_bus_buffer.scala 530:14] + buf_addr[3] <= _T_4229 @[el2_lsu_bus_buffer.scala 530:14] + node _T_4230 = bits(buf_wr_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 531:127] + reg _T_4231 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4230 : @[Reg.scala 28:19] + _T_4231 <= buf_byteen_in[0] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4232 = bits(buf_wr_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 531:127] + reg _T_4233 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4232 : @[Reg.scala 28:19] + _T_4233 <= buf_byteen_in[1] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4234 = bits(buf_wr_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 531:127] + reg _T_4235 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4234 : @[Reg.scala 28:19] + _T_4235 <= buf_byteen_in[2] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4236 = bits(buf_wr_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 531:127] + reg _T_4237 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4236 : @[Reg.scala 28:19] + _T_4237 <= buf_byteen_in[3] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_byteen[0] <= _T_4231 @[el2_lsu_bus_buffer.scala 531:16] + buf_byteen[1] <= _T_4233 @[el2_lsu_bus_buffer.scala 531:16] + buf_byteen[2] <= _T_4235 @[el2_lsu_bus_buffer.scala 531:16] + buf_byteen[3] <= _T_4237 @[el2_lsu_bus_buffer.scala 531:16] + inst rvclkhdr_8 of rvclkhdr_8 @[el2_lib.scala 472:23] + rvclkhdr_8.clock <= clock + rvclkhdr_8.reset <= reset + rvclkhdr_8.io.clk <= clock @[el2_lib.scala 474:18] + rvclkhdr_8.io.en <= buf_data_en[0] @[el2_lib.scala 475:17] + rvclkhdr_8.io.scan_mode <= io.scan_mode @[el2_lib.scala 476:24] + reg _T_4238 : UInt, rvclkhdr_8.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 478:16] + _T_4238 <= buf_data_in[0] @[el2_lib.scala 478:16] + inst rvclkhdr_9 of rvclkhdr_9 @[el2_lib.scala 472:23] + rvclkhdr_9.clock <= clock + rvclkhdr_9.reset <= reset + rvclkhdr_9.io.clk <= clock @[el2_lib.scala 474:18] + rvclkhdr_9.io.en <= buf_data_en[1] @[el2_lib.scala 475:17] + rvclkhdr_9.io.scan_mode <= io.scan_mode @[el2_lib.scala 476:24] + reg _T_4239 : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 478:16] + _T_4239 <= buf_data_in[1] @[el2_lib.scala 478:16] + inst rvclkhdr_10 of rvclkhdr_10 @[el2_lib.scala 472:23] + rvclkhdr_10.clock <= clock + rvclkhdr_10.reset <= reset + rvclkhdr_10.io.clk <= clock @[el2_lib.scala 474:18] + rvclkhdr_10.io.en <= buf_data_en[2] @[el2_lib.scala 475:17] + rvclkhdr_10.io.scan_mode <= io.scan_mode @[el2_lib.scala 476:24] + reg _T_4240 : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 478:16] + _T_4240 <= buf_data_in[2] @[el2_lib.scala 478:16] + inst rvclkhdr_11 of rvclkhdr_11 @[el2_lib.scala 472:23] + rvclkhdr_11.clock <= clock + rvclkhdr_11.reset <= reset + rvclkhdr_11.io.clk <= clock @[el2_lib.scala 474:18] + rvclkhdr_11.io.en <= buf_data_en[3] @[el2_lib.scala 475:17] + rvclkhdr_11.io.scan_mode <= io.scan_mode @[el2_lib.scala 476:24] + reg _T_4241 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 478:16] + _T_4241 <= buf_data_in[3] @[el2_lib.scala 478:16] + buf_data[0] <= _T_4238 @[el2_lsu_bus_buffer.scala 532:14] + buf_data[1] <= _T_4239 @[el2_lsu_bus_buffer.scala 532:14] + buf_data[2] <= _T_4240 @[el2_lsu_bus_buffer.scala 532:14] + buf_data[3] <= _T_4241 @[el2_lsu_bus_buffer.scala 532:14] + node _T_4242 = bits(buf_error, 0, 0) @[el2_lsu_bus_buffer.scala 533:121] + node _T_4243 = mux(buf_error_en[0], UInt<1>("h01"), _T_4242) @[el2_lsu_bus_buffer.scala 533:86] + node _T_4244 = and(_T_4243, buf_rst[0]) @[el2_lsu_bus_buffer.scala 533:126] + reg _T_4245 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 533:82] + _T_4245 <= _T_4244 @[el2_lsu_bus_buffer.scala 533:82] + node _T_4246 = bits(buf_error, 1, 1) @[el2_lsu_bus_buffer.scala 533:121] + node _T_4247 = mux(buf_error_en[1], UInt<1>("h01"), _T_4246) @[el2_lsu_bus_buffer.scala 533:86] + node _T_4248 = and(_T_4247, buf_rst[1]) @[el2_lsu_bus_buffer.scala 533:126] + reg _T_4249 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 533:82] + _T_4249 <= _T_4248 @[el2_lsu_bus_buffer.scala 533:82] + node _T_4250 = bits(buf_error, 2, 2) @[el2_lsu_bus_buffer.scala 533:121] + node _T_4251 = mux(buf_error_en[2], UInt<1>("h01"), _T_4250) @[el2_lsu_bus_buffer.scala 533:86] + node _T_4252 = and(_T_4251, buf_rst[2]) @[el2_lsu_bus_buffer.scala 533:126] + reg _T_4253 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 533:82] + _T_4253 <= _T_4252 @[el2_lsu_bus_buffer.scala 533:82] + node _T_4254 = bits(buf_error, 3, 3) @[el2_lsu_bus_buffer.scala 533:121] + node _T_4255 = mux(buf_error_en[3], UInt<1>("h01"), _T_4254) @[el2_lsu_bus_buffer.scala 533:86] + node _T_4256 = and(_T_4255, buf_rst[3]) @[el2_lsu_bus_buffer.scala 533:126] + reg _T_4257 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 533:82] + _T_4257 <= _T_4256 @[el2_lsu_bus_buffer.scala 533:82] + node _T_4258 = cat(_T_4257, _T_4253) @[Cat.scala 29:58] + node _T_4259 = cat(_T_4258, _T_4249) @[Cat.scala 29:58] + node _T_4260 = cat(_T_4259, _T_4245) @[Cat.scala 29:58] + buf_error <= _T_4260 @[el2_lsu_bus_buffer.scala 533:15] + node _T_4261 = neq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 535:60] + node _T_4262 = neq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 535:60] + node _T_4263 = neq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 535:60] + node _T_4264 = neq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 535:60] + node _T_4265 = add(_T_4264, _T_4263) @[el2_lsu_bus_buffer.scala 535:96] + node _T_4266 = add(_T_4265, _T_4262) @[el2_lsu_bus_buffer.scala 535:96] + node buf_numvld_any = add(_T_4266, _T_4261) @[el2_lsu_bus_buffer.scala 535:96] + node _T_4267 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 536:60] + node _T_4268 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 536:76] + node _T_4269 = eq(_T_4268, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 536:79] + node _T_4270 = and(_T_4267, _T_4269) @[el2_lsu_bus_buffer.scala 536:64] + node _T_4271 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 536:91] + node _T_4272 = and(_T_4270, _T_4271) @[el2_lsu_bus_buffer.scala 536:89] + node _T_4273 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 536:60] + node _T_4274 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 536:76] + node _T_4275 = eq(_T_4274, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 536:79] + node _T_4276 = and(_T_4273, _T_4275) @[el2_lsu_bus_buffer.scala 536:64] + node _T_4277 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 536:91] + node _T_4278 = and(_T_4276, _T_4277) @[el2_lsu_bus_buffer.scala 536:89] + node _T_4279 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 536:60] + node _T_4280 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 536:76] + node _T_4281 = eq(_T_4280, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 536:79] + node _T_4282 = and(_T_4279, _T_4281) @[el2_lsu_bus_buffer.scala 536:64] + node _T_4283 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 536:91] + node _T_4284 = and(_T_4282, _T_4283) @[el2_lsu_bus_buffer.scala 536:89] + node _T_4285 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 536:60] + node _T_4286 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 536:76] + node _T_4287 = eq(_T_4286, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 536:79] + node _T_4288 = and(_T_4285, _T_4287) @[el2_lsu_bus_buffer.scala 536:64] + node _T_4289 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 536:91] + node _T_4290 = and(_T_4288, _T_4289) @[el2_lsu_bus_buffer.scala 536:89] + node _T_4291 = add(_T_4290, _T_4284) @[el2_lsu_bus_buffer.scala 536:142] + node _T_4292 = add(_T_4291, _T_4278) @[el2_lsu_bus_buffer.scala 536:142] + node _T_4293 = add(_T_4292, _T_4272) @[el2_lsu_bus_buffer.scala 536:142] + buf_numvld_wrcmd_any <= _T_4293 @[el2_lsu_bus_buffer.scala 536:24] + node _T_4294 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 537:60] + node _T_4295 = eq(_T_4294, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 537:63] + node _T_4296 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 537:75] + node _T_4297 = and(_T_4295, _T_4296) @[el2_lsu_bus_buffer.scala 537:73] + node _T_4298 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 537:60] + node _T_4299 = eq(_T_4298, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 537:63] + node _T_4300 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 537:75] + node _T_4301 = and(_T_4299, _T_4300) @[el2_lsu_bus_buffer.scala 537:73] + node _T_4302 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 537:60] + node _T_4303 = eq(_T_4302, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 537:63] + node _T_4304 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 537:75] + node _T_4305 = and(_T_4303, _T_4304) @[el2_lsu_bus_buffer.scala 537:73] + node _T_4306 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 537:60] + node _T_4307 = eq(_T_4306, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 537:63] + node _T_4308 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 537:75] + node _T_4309 = and(_T_4307, _T_4308) @[el2_lsu_bus_buffer.scala 537:73] + node _T_4310 = add(_T_4309, _T_4305) @[el2_lsu_bus_buffer.scala 537:126] + node _T_4311 = add(_T_4310, _T_4301) @[el2_lsu_bus_buffer.scala 537:126] + node _T_4312 = add(_T_4311, _T_4297) @[el2_lsu_bus_buffer.scala 537:126] + buf_numvld_cmd_any <= _T_4312 @[el2_lsu_bus_buffer.scala 537:22] + node _T_4313 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 538:61] + node _T_4314 = eq(_T_4313, UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 538:64] + node _T_4315 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 538:85] + node _T_4316 = eq(_T_4315, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 538:88] + node _T_4317 = or(_T_4314, _T_4316) @[el2_lsu_bus_buffer.scala 538:74] + node _T_4318 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 538:102] + node _T_4319 = and(_T_4317, _T_4318) @[el2_lsu_bus_buffer.scala 538:100] + node _T_4320 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 538:61] + node _T_4321 = eq(_T_4320, UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 538:64] + node _T_4322 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 538:85] + node _T_4323 = eq(_T_4322, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 538:88] + node _T_4324 = or(_T_4321, _T_4323) @[el2_lsu_bus_buffer.scala 538:74] + node _T_4325 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 538:102] + node _T_4326 = and(_T_4324, _T_4325) @[el2_lsu_bus_buffer.scala 538:100] + node _T_4327 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 538:61] + node _T_4328 = eq(_T_4327, UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 538:64] + node _T_4329 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 538:85] + node _T_4330 = eq(_T_4329, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 538:88] + node _T_4331 = or(_T_4328, _T_4330) @[el2_lsu_bus_buffer.scala 538:74] + node _T_4332 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 538:102] + node _T_4333 = and(_T_4331, _T_4332) @[el2_lsu_bus_buffer.scala 538:100] + node _T_4334 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 538:61] + node _T_4335 = eq(_T_4334, UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 538:64] + node _T_4336 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 538:85] + node _T_4337 = eq(_T_4336, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 538:88] + node _T_4338 = or(_T_4335, _T_4337) @[el2_lsu_bus_buffer.scala 538:74] + node _T_4339 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 538:102] + node _T_4340 = and(_T_4338, _T_4339) @[el2_lsu_bus_buffer.scala 538:100] + node _T_4341 = add(_T_4340, _T_4333) @[el2_lsu_bus_buffer.scala 538:153] + node _T_4342 = add(_T_4341, _T_4326) @[el2_lsu_bus_buffer.scala 538:153] + node _T_4343 = add(_T_4342, _T_4319) @[el2_lsu_bus_buffer.scala 538:153] + buf_numvld_pend_any <= _T_4343 @[el2_lsu_bus_buffer.scala 538:23] + node _T_4344 = eq(buf_state[0], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 539:61] + node _T_4345 = eq(buf_state[1], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 539:61] + node _T_4346 = eq(buf_state[2], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 539:61] + node _T_4347 = eq(buf_state[3], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 539:61] + node _T_4348 = or(_T_4347, _T_4346) @[el2_lsu_bus_buffer.scala 539:93] + node _T_4349 = or(_T_4348, _T_4345) @[el2_lsu_bus_buffer.scala 539:93] + node _T_4350 = or(_T_4349, _T_4344) @[el2_lsu_bus_buffer.scala 539:93] + any_done_wait_state <= _T_4350 @[el2_lsu_bus_buffer.scala 539:23] + node _T_4351 = orr(buf_numvld_pend_any) @[el2_lsu_bus_buffer.scala 540:53] + io.lsu_bus_buffer_pend_any <= _T_4351 @[el2_lsu_bus_buffer.scala 540:30] + node _T_4352 = and(io.ldst_dual_d, io.dec_lsu_valid_raw_d) @[el2_lsu_bus_buffer.scala 541:52] + node _T_4353 = geq(buf_numvld_any, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 541:92] + node _T_4354 = eq(buf_numvld_any, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 541:119] + node _T_4355 = mux(_T_4352, _T_4353, _T_4354) @[el2_lsu_bus_buffer.scala 541:36] + io.lsu_bus_buffer_full_any <= _T_4355 @[el2_lsu_bus_buffer.scala 541:30] + node _T_4356 = orr(buf_state[0]) @[el2_lsu_bus_buffer.scala 542:52] + node _T_4357 = orr(buf_state[1]) @[el2_lsu_bus_buffer.scala 542:52] + node _T_4358 = orr(buf_state[2]) @[el2_lsu_bus_buffer.scala 542:52] + node _T_4359 = orr(buf_state[3]) @[el2_lsu_bus_buffer.scala 542:52] + node _T_4360 = or(_T_4356, _T_4357) @[el2_lsu_bus_buffer.scala 542:65] + node _T_4361 = or(_T_4360, _T_4358) @[el2_lsu_bus_buffer.scala 542:65] + node _T_4362 = or(_T_4361, _T_4359) @[el2_lsu_bus_buffer.scala 542:65] + node _T_4363 = eq(_T_4362, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 542:34] + node _T_4364 = eq(ibuf_valid, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 542:72] + node _T_4365 = and(_T_4363, _T_4364) @[el2_lsu_bus_buffer.scala 542:70] + node _T_4366 = eq(obuf_valid, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 542:86] + node _T_4367 = and(_T_4365, _T_4366) @[el2_lsu_bus_buffer.scala 542:84] + io.lsu_bus_buffer_empty_any <= _T_4367 @[el2_lsu_bus_buffer.scala 542:31] + node _T_4368 = and(io.lsu_busreq_m, io.lsu_pkt_m.valid) @[el2_lsu_bus_buffer.scala 544:51] + node _T_4369 = and(_T_4368, io.lsu_pkt_m.load) @[el2_lsu_bus_buffer.scala 544:72] + node _T_4370 = eq(io.flush_m_up, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 544:94] + node _T_4371 = and(_T_4369, _T_4370) @[el2_lsu_bus_buffer.scala 544:92] + node _T_4372 = eq(io.ld_full_hit_m, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 544:111] + node _T_4373 = and(_T_4371, _T_4372) @[el2_lsu_bus_buffer.scala 544:109] + io.lsu_nonblock_load_valid_m <= _T_4373 @[el2_lsu_bus_buffer.scala 544:32] + io.lsu_nonblock_load_tag_m <= WrPtr0_m @[el2_lsu_bus_buffer.scala 545:30] + wire lsu_nonblock_load_valid_r : UInt<1> + lsu_nonblock_load_valid_r <= UInt<1>("h00") + node _T_4374 = eq(io.lsu_commit_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 547:61] + node _T_4375 = and(lsu_nonblock_load_valid_r, _T_4374) @[el2_lsu_bus_buffer.scala 547:59] + io.lsu_nonblock_load_inv_r <= _T_4375 @[el2_lsu_bus_buffer.scala 547:30] + io.lsu_nonblock_load_inv_tag_r <= WrPtr0_r @[el2_lsu_bus_buffer.scala 548:34] + node _T_4376 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 549:80] + node _T_4377 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 549:127] + node _T_4378 = and(UInt<1>("h01"), _T_4377) @[el2_lsu_bus_buffer.scala 549:116] + node _T_4379 = eq(_T_4378, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 549:95] + node _T_4380 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 549:80] + node _T_4381 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 549:127] + node _T_4382 = and(UInt<1>("h01"), _T_4381) @[el2_lsu_bus_buffer.scala 549:116] + node _T_4383 = eq(_T_4382, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 549:95] + node _T_4384 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 549:80] + node _T_4385 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 549:127] + node _T_4386 = and(UInt<1>("h01"), _T_4385) @[el2_lsu_bus_buffer.scala 549:116] + node _T_4387 = eq(_T_4386, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 549:95] + node _T_4388 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 549:80] + node _T_4389 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 549:127] + node _T_4390 = and(UInt<1>("h01"), _T_4389) @[el2_lsu_bus_buffer.scala 549:116] + node _T_4391 = eq(_T_4390, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 549:95] + node _T_4392 = mux(_T_4376, _T_4379, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4393 = mux(_T_4380, _T_4383, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4394 = mux(_T_4384, _T_4387, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4395 = mux(_T_4388, _T_4391, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4396 = or(_T_4392, _T_4393) @[Mux.scala 27:72] + node _T_4397 = or(_T_4396, _T_4394) @[Mux.scala 27:72] + node _T_4398 = or(_T_4397, _T_4395) @[Mux.scala 27:72] + wire lsu_nonblock_load_data_ready : UInt<1> @[Mux.scala 27:72] + lsu_nonblock_load_data_ready <= _T_4398 @[Mux.scala 27:72] + node _T_4399 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 550:80] + node _T_4400 = bits(buf_error, 0, 0) @[el2_lsu_bus_buffer.scala 550:104] + node _T_4401 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 550:120] + node _T_4402 = eq(_T_4401, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 550:110] + node _T_4403 = and(_T_4400, _T_4402) @[el2_lsu_bus_buffer.scala 550:108] + node _T_4404 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 550:80] + node _T_4405 = bits(buf_error, 1, 1) @[el2_lsu_bus_buffer.scala 550:104] + node _T_4406 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 550:120] + node _T_4407 = eq(_T_4406, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 550:110] + node _T_4408 = and(_T_4405, _T_4407) @[el2_lsu_bus_buffer.scala 550:108] + node _T_4409 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 550:80] + node _T_4410 = bits(buf_error, 2, 2) @[el2_lsu_bus_buffer.scala 550:104] + node _T_4411 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 550:120] + node _T_4412 = eq(_T_4411, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 550:110] + node _T_4413 = and(_T_4410, _T_4412) @[el2_lsu_bus_buffer.scala 550:108] + node _T_4414 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 550:80] + node _T_4415 = bits(buf_error, 3, 3) @[el2_lsu_bus_buffer.scala 550:104] + node _T_4416 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 550:120] + node _T_4417 = eq(_T_4416, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 550:110] + node _T_4418 = and(_T_4415, _T_4417) @[el2_lsu_bus_buffer.scala 550:108] + node _T_4419 = mux(_T_4399, _T_4403, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4420 = mux(_T_4404, _T_4408, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4421 = mux(_T_4409, _T_4413, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4422 = mux(_T_4414, _T_4418, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4423 = or(_T_4419, _T_4420) @[Mux.scala 27:72] + node _T_4424 = or(_T_4423, _T_4421) @[Mux.scala 27:72] + node _T_4425 = or(_T_4424, _T_4422) @[Mux.scala 27:72] + wire _T_4426 : UInt<1> @[Mux.scala 27:72] + _T_4426 <= _T_4425 @[Mux.scala 27:72] + io.lsu_nonblock_load_data_error <= _T_4426 @[el2_lsu_bus_buffer.scala 550:35] + node _T_4427 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 551:79] + node _T_4428 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 551:102] + node _T_4429 = eq(_T_4428, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 551:92] + node _T_4430 = and(_T_4427, _T_4429) @[el2_lsu_bus_buffer.scala 551:90] + node _T_4431 = eq(buf_dual[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 551:109] + node _T_4432 = eq(buf_dualhi[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 551:124] + node _T_4433 = or(_T_4431, _T_4432) @[el2_lsu_bus_buffer.scala 551:122] + node _T_4434 = and(_T_4430, _T_4433) @[el2_lsu_bus_buffer.scala 551:106] + node _T_4435 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 551:79] + node _T_4436 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 551:102] + node _T_4437 = eq(_T_4436, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 551:92] + node _T_4438 = and(_T_4435, _T_4437) @[el2_lsu_bus_buffer.scala 551:90] + node _T_4439 = eq(buf_dual[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 551:109] + node _T_4440 = eq(buf_dualhi[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 551:124] + node _T_4441 = or(_T_4439, _T_4440) @[el2_lsu_bus_buffer.scala 551:122] + node _T_4442 = and(_T_4438, _T_4441) @[el2_lsu_bus_buffer.scala 551:106] + node _T_4443 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 551:79] + node _T_4444 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 551:102] + node _T_4445 = eq(_T_4444, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 551:92] + node _T_4446 = and(_T_4443, _T_4445) @[el2_lsu_bus_buffer.scala 551:90] + node _T_4447 = eq(buf_dual[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 551:109] + node _T_4448 = eq(buf_dualhi[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 551:124] + node _T_4449 = or(_T_4447, _T_4448) @[el2_lsu_bus_buffer.scala 551:122] + node _T_4450 = and(_T_4446, _T_4449) @[el2_lsu_bus_buffer.scala 551:106] + node _T_4451 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 551:79] + node _T_4452 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 551:102] + node _T_4453 = eq(_T_4452, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 551:92] + node _T_4454 = and(_T_4451, _T_4453) @[el2_lsu_bus_buffer.scala 551:90] + node _T_4455 = eq(buf_dual[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 551:109] + node _T_4456 = eq(buf_dualhi[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 551:124] + node _T_4457 = or(_T_4455, _T_4456) @[el2_lsu_bus_buffer.scala 551:122] + node _T_4458 = and(_T_4454, _T_4457) @[el2_lsu_bus_buffer.scala 551:106] + node _T_4459 = mux(_T_4434, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4460 = mux(_T_4442, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4461 = mux(_T_4450, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4462 = mux(_T_4458, UInt<2>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4463 = or(_T_4459, _T_4460) @[Mux.scala 27:72] + node _T_4464 = or(_T_4463, _T_4461) @[Mux.scala 27:72] + node _T_4465 = or(_T_4464, _T_4462) @[Mux.scala 27:72] + wire _T_4466 : UInt<2> @[Mux.scala 27:72] + _T_4466 <= _T_4465 @[Mux.scala 27:72] + io.lsu_nonblock_load_data_tag <= _T_4466 @[el2_lsu_bus_buffer.scala 551:33] + node _T_4467 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 552:78] + node _T_4468 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 552:101] + node _T_4469 = eq(_T_4468, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 552:91] + node _T_4470 = and(_T_4467, _T_4469) @[el2_lsu_bus_buffer.scala 552:89] + node _T_4471 = eq(buf_dual[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 552:108] + node _T_4472 = eq(buf_dualhi[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 552:123] + node _T_4473 = or(_T_4471, _T_4472) @[el2_lsu_bus_buffer.scala 552:121] + node _T_4474 = and(_T_4470, _T_4473) @[el2_lsu_bus_buffer.scala 552:105] + node _T_4475 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 552:78] + node _T_4476 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 552:101] + node _T_4477 = eq(_T_4476, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 552:91] + node _T_4478 = and(_T_4475, _T_4477) @[el2_lsu_bus_buffer.scala 552:89] + node _T_4479 = eq(buf_dual[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 552:108] + node _T_4480 = eq(buf_dualhi[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 552:123] + node _T_4481 = or(_T_4479, _T_4480) @[el2_lsu_bus_buffer.scala 552:121] + node _T_4482 = and(_T_4478, _T_4481) @[el2_lsu_bus_buffer.scala 552:105] + node _T_4483 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 552:78] + node _T_4484 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 552:101] + node _T_4485 = eq(_T_4484, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 552:91] + node _T_4486 = and(_T_4483, _T_4485) @[el2_lsu_bus_buffer.scala 552:89] + node _T_4487 = eq(buf_dual[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 552:108] + node _T_4488 = eq(buf_dualhi[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 552:123] + node _T_4489 = or(_T_4487, _T_4488) @[el2_lsu_bus_buffer.scala 552:121] + node _T_4490 = and(_T_4486, _T_4489) @[el2_lsu_bus_buffer.scala 552:105] + node _T_4491 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 552:78] + node _T_4492 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 552:101] + node _T_4493 = eq(_T_4492, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 552:91] + node _T_4494 = and(_T_4491, _T_4493) @[el2_lsu_bus_buffer.scala 552:89] + node _T_4495 = eq(buf_dual[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 552:108] + node _T_4496 = eq(buf_dualhi[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 552:123] + node _T_4497 = or(_T_4495, _T_4496) @[el2_lsu_bus_buffer.scala 552:121] + node _T_4498 = and(_T_4494, _T_4497) @[el2_lsu_bus_buffer.scala 552:105] + node _T_4499 = mux(_T_4474, buf_data[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4500 = mux(_T_4482, buf_data[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4501 = mux(_T_4490, buf_data[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4502 = mux(_T_4498, buf_data[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4503 = or(_T_4499, _T_4500) @[Mux.scala 27:72] + node _T_4504 = or(_T_4503, _T_4501) @[Mux.scala 27:72] + node _T_4505 = or(_T_4504, _T_4502) @[Mux.scala 27:72] + wire lsu_nonblock_load_data_lo : UInt<32> @[Mux.scala 27:72] + lsu_nonblock_load_data_lo <= _T_4505 @[Mux.scala 27:72] + node _T_4506 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 553:78] + node _T_4507 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 553:101] + node _T_4508 = eq(_T_4507, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 553:91] + node _T_4509 = and(_T_4506, _T_4508) @[el2_lsu_bus_buffer.scala 553:89] + node _T_4510 = or(buf_dual[0], buf_dualhi[0]) @[el2_lsu_bus_buffer.scala 553:120] + node _T_4511 = and(_T_4509, _T_4510) @[el2_lsu_bus_buffer.scala 553:105] + node _T_4512 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 553:78] + node _T_4513 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 553:101] + node _T_4514 = eq(_T_4513, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 553:91] + node _T_4515 = and(_T_4512, _T_4514) @[el2_lsu_bus_buffer.scala 553:89] + node _T_4516 = or(buf_dual[1], buf_dualhi[1]) @[el2_lsu_bus_buffer.scala 553:120] + node _T_4517 = and(_T_4515, _T_4516) @[el2_lsu_bus_buffer.scala 553:105] + node _T_4518 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 553:78] + node _T_4519 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 553:101] + node _T_4520 = eq(_T_4519, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 553:91] + node _T_4521 = and(_T_4518, _T_4520) @[el2_lsu_bus_buffer.scala 553:89] + node _T_4522 = or(buf_dual[2], buf_dualhi[2]) @[el2_lsu_bus_buffer.scala 553:120] + node _T_4523 = and(_T_4521, _T_4522) @[el2_lsu_bus_buffer.scala 553:105] + node _T_4524 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 553:78] + node _T_4525 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 553:101] + node _T_4526 = eq(_T_4525, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 553:91] + node _T_4527 = and(_T_4524, _T_4526) @[el2_lsu_bus_buffer.scala 553:89] + node _T_4528 = or(buf_dual[3], buf_dualhi[3]) @[el2_lsu_bus_buffer.scala 553:120] + node _T_4529 = and(_T_4527, _T_4528) @[el2_lsu_bus_buffer.scala 553:105] + node _T_4530 = mux(_T_4511, buf_data[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4531 = mux(_T_4517, buf_data[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4532 = mux(_T_4523, buf_data[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4533 = mux(_T_4529, buf_data[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4534 = or(_T_4530, _T_4531) @[Mux.scala 27:72] + node _T_4535 = or(_T_4534, _T_4532) @[Mux.scala 27:72] + node _T_4536 = or(_T_4535, _T_4533) @[Mux.scala 27:72] + wire lsu_nonblock_load_data_hi : UInt<32> @[Mux.scala 27:72] + lsu_nonblock_load_data_hi <= _T_4536 @[Mux.scala 27:72] + node _T_4537 = eq(io.lsu_nonblock_load_data_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_4538 = eq(io.lsu_nonblock_load_data_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_4539 = eq(io.lsu_nonblock_load_data_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_4540 = eq(io.lsu_nonblock_load_data_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_4541 = mux(_T_4537, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4542 = mux(_T_4538, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4543 = mux(_T_4539, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4544 = mux(_T_4540, buf_addr[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4545 = or(_T_4541, _T_4542) @[Mux.scala 27:72] + node _T_4546 = or(_T_4545, _T_4543) @[Mux.scala 27:72] + node _T_4547 = or(_T_4546, _T_4544) @[Mux.scala 27:72] + wire lsu_nonblock_addr_offset : UInt<32> @[Mux.scala 27:72] + lsu_nonblock_addr_offset <= _T_4547 @[Mux.scala 27:72] + node _T_4548 = eq(io.lsu_nonblock_load_data_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_4549 = eq(io.lsu_nonblock_load_data_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_4550 = eq(io.lsu_nonblock_load_data_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_4551 = eq(io.lsu_nonblock_load_data_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_4552 = mux(_T_4548, buf_sz[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4553 = mux(_T_4549, buf_sz[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4554 = mux(_T_4550, buf_sz[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4555 = mux(_T_4551, buf_sz[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4556 = or(_T_4552, _T_4553) @[Mux.scala 27:72] + node _T_4557 = or(_T_4556, _T_4554) @[Mux.scala 27:72] + node _T_4558 = or(_T_4557, _T_4555) @[Mux.scala 27:72] + wire lsu_nonblock_sz : UInt<2> @[Mux.scala 27:72] + lsu_nonblock_sz <= _T_4558 @[Mux.scala 27:72] + node _T_4559 = eq(io.lsu_nonblock_load_data_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_4560 = bits(buf_unsign, 0, 0) @[el2_lsu_bus_buffer.scala 110:129] + node _T_4561 = eq(io.lsu_nonblock_load_data_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_4562 = bits(buf_unsign, 1, 1) @[el2_lsu_bus_buffer.scala 110:129] + node _T_4563 = eq(io.lsu_nonblock_load_data_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_4564 = bits(buf_unsign, 2, 2) @[el2_lsu_bus_buffer.scala 110:129] + node _T_4565 = eq(io.lsu_nonblock_load_data_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_4566 = bits(buf_unsign, 3, 3) @[el2_lsu_bus_buffer.scala 110:129] + node _T_4567 = mux(_T_4559, _T_4560, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4568 = mux(_T_4561, _T_4562, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4569 = mux(_T_4563, _T_4564, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4570 = mux(_T_4565, _T_4566, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4571 = or(_T_4567, _T_4568) @[Mux.scala 27:72] + node _T_4572 = or(_T_4571, _T_4569) @[Mux.scala 27:72] + node _T_4573 = or(_T_4572, _T_4570) @[Mux.scala 27:72] + wire lsu_nonblock_unsign : UInt<1> @[Mux.scala 27:72] + lsu_nonblock_unsign <= _T_4573 @[Mux.scala 27:72] + node _T_4574 = cat(buf_dual[3], buf_dual[2]) @[Cat.scala 29:58] + node _T_4575 = cat(_T_4574, buf_dual[1]) @[Cat.scala 29:58] + node _T_4576 = cat(_T_4575, buf_dual[0]) @[Cat.scala 29:58] + node _T_4577 = eq(io.lsu_nonblock_load_data_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_4578 = bits(_T_4576, 0, 0) @[el2_lsu_bus_buffer.scala 110:129] + node _T_4579 = eq(io.lsu_nonblock_load_data_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_4580 = bits(_T_4576, 1, 1) @[el2_lsu_bus_buffer.scala 110:129] + node _T_4581 = eq(io.lsu_nonblock_load_data_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_4582 = bits(_T_4576, 2, 2) @[el2_lsu_bus_buffer.scala 110:129] + node _T_4583 = eq(io.lsu_nonblock_load_data_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 110:118] + node _T_4584 = bits(_T_4576, 3, 3) @[el2_lsu_bus_buffer.scala 110:129] + node _T_4585 = mux(_T_4577, _T_4578, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4586 = mux(_T_4579, _T_4580, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4587 = mux(_T_4581, _T_4582, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4588 = mux(_T_4583, _T_4584, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4589 = or(_T_4585, _T_4586) @[Mux.scala 27:72] + node _T_4590 = or(_T_4589, _T_4587) @[Mux.scala 27:72] + node _T_4591 = or(_T_4590, _T_4588) @[Mux.scala 27:72] + wire lsu_nonblock_dual : UInt<1> @[Mux.scala 27:72] + lsu_nonblock_dual <= _T_4591 @[Mux.scala 27:72] + node _T_4592 = cat(lsu_nonblock_load_data_hi, lsu_nonblock_load_data_lo) @[Cat.scala 29:58] + node _T_4593 = mul(lsu_nonblock_addr_offset, UInt<4>("h08")) @[el2_lsu_bus_buffer.scala 558:121] + node lsu_nonblock_data_unalgn = dshr(_T_4592, _T_4593) @[el2_lsu_bus_buffer.scala 558:92] + node _T_4594 = eq(io.lsu_nonblock_load_data_error, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 559:69] + node _T_4595 = and(lsu_nonblock_load_data_ready, _T_4594) @[el2_lsu_bus_buffer.scala 559:67] + io.lsu_nonblock_load_data_valid <= _T_4595 @[el2_lsu_bus_buffer.scala 559:35] + node _T_4596 = eq(lsu_nonblock_sz, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 560:81] + node _T_4597 = and(lsu_nonblock_unsign, _T_4596) @[el2_lsu_bus_buffer.scala 560:63] + node _T_4598 = bits(lsu_nonblock_data_unalgn, 7, 0) @[el2_lsu_bus_buffer.scala 560:131] + node _T_4599 = cat(UInt<24>("h00"), _T_4598) @[Cat.scala 29:58] + node _T_4600 = eq(lsu_nonblock_sz, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 561:45] + node _T_4601 = and(lsu_nonblock_unsign, _T_4600) @[el2_lsu_bus_buffer.scala 561:26] + node _T_4602 = bits(lsu_nonblock_data_unalgn, 15, 0) @[el2_lsu_bus_buffer.scala 561:95] + node _T_4603 = cat(UInt<16>("h00"), _T_4602) @[Cat.scala 29:58] + node _T_4604 = eq(lsu_nonblock_unsign, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 562:6] + node _T_4605 = eq(lsu_nonblock_sz, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 562:45] + node _T_4606 = and(_T_4604, _T_4605) @[el2_lsu_bus_buffer.scala 562:27] + node _T_4607 = bits(lsu_nonblock_data_unalgn, 7, 7) @[el2_lsu_bus_buffer.scala 562:93] + node _T_4608 = bits(_T_4607, 0, 0) @[Bitwise.scala 72:15] + node _T_4609 = mux(_T_4608, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12] + node _T_4610 = bits(lsu_nonblock_data_unalgn, 7, 0) @[el2_lsu_bus_buffer.scala 562:123] + node _T_4611 = cat(_T_4609, _T_4610) @[Cat.scala 29:58] + node _T_4612 = eq(lsu_nonblock_unsign, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 563:6] + node _T_4613 = eq(lsu_nonblock_sz, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 563:45] + node _T_4614 = and(_T_4612, _T_4613) @[el2_lsu_bus_buffer.scala 563:27] + node _T_4615 = bits(lsu_nonblock_data_unalgn, 15, 15) @[el2_lsu_bus_buffer.scala 563:93] + node _T_4616 = bits(_T_4615, 0, 0) @[Bitwise.scala 72:15] + node _T_4617 = mux(_T_4616, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12] + node _T_4618 = bits(lsu_nonblock_data_unalgn, 15, 0) @[el2_lsu_bus_buffer.scala 563:124] + node _T_4619 = cat(_T_4617, _T_4618) @[Cat.scala 29:58] + node _T_4620 = eq(lsu_nonblock_sz, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 564:21] + node _T_4621 = mux(_T_4597, _T_4599, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4622 = mux(_T_4601, _T_4603, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4623 = mux(_T_4606, _T_4611, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4624 = mux(_T_4614, _T_4619, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4625 = mux(_T_4620, lsu_nonblock_data_unalgn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4626 = or(_T_4621, _T_4622) @[Mux.scala 27:72] + node _T_4627 = or(_T_4626, _T_4623) @[Mux.scala 27:72] + node _T_4628 = or(_T_4627, _T_4624) @[Mux.scala 27:72] + node _T_4629 = or(_T_4628, _T_4625) @[Mux.scala 27:72] + wire _T_4630 : UInt<64> @[Mux.scala 27:72] + _T_4630 <= _T_4629 @[Mux.scala 27:72] + io.lsu_nonblock_load_data <= _T_4630 @[el2_lsu_bus_buffer.scala 560:29] + node _T_4631 = eq(buf_state[0], UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 565:68] + node _T_4632 = bits(buf_sideeffect, 0, 0) @[el2_lsu_bus_buffer.scala 565:95] + node _T_4633 = and(_T_4632, io.dec_tlu_sideeffect_posted_disable) @[el2_lsu_bus_buffer.scala 565:99] + node _T_4634 = eq(buf_state[1], UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 565:68] + node _T_4635 = bits(buf_sideeffect, 1, 1) @[el2_lsu_bus_buffer.scala 565:95] + node _T_4636 = and(_T_4635, io.dec_tlu_sideeffect_posted_disable) @[el2_lsu_bus_buffer.scala 565:99] + node _T_4637 = eq(buf_state[2], UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 565:68] + node _T_4638 = bits(buf_sideeffect, 2, 2) @[el2_lsu_bus_buffer.scala 565:95] + node _T_4639 = and(_T_4638, io.dec_tlu_sideeffect_posted_disable) @[el2_lsu_bus_buffer.scala 565:99] + node _T_4640 = eq(buf_state[3], UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 565:68] + node _T_4641 = bits(buf_sideeffect, 3, 3) @[el2_lsu_bus_buffer.scala 565:95] + node _T_4642 = and(_T_4641, io.dec_tlu_sideeffect_posted_disable) @[el2_lsu_bus_buffer.scala 565:99] + node _T_4643 = mux(_T_4631, _T_4633, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4644 = mux(_T_4634, _T_4636, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4645 = mux(_T_4637, _T_4639, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4646 = mux(_T_4640, _T_4642, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4647 = or(_T_4643, _T_4644) @[Mux.scala 27:72] + node _T_4648 = or(_T_4647, _T_4645) @[Mux.scala 27:72] + node _T_4649 = or(_T_4648, _T_4646) @[Mux.scala 27:72] + wire _T_4650 : UInt<1> @[Mux.scala 27:72] + _T_4650 <= _T_4649 @[Mux.scala 27:72] + bus_sideeffect_pend <= _T_4650 @[el2_lsu_bus_buffer.scala 565:23] + node _T_4651 = eq(buf_state[0], UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 566:71] + node _T_4652 = and(UInt<1>("h01"), obuf_valid) @[el2_lsu_bus_buffer.scala 567:25] + node _T_4653 = bits(obuf_addr, 31, 3) @[el2_lsu_bus_buffer.scala 567:50] + node _T_4654 = bits(buf_addr[0], 31, 3) @[el2_lsu_bus_buffer.scala 567:70] + node _T_4655 = eq(_T_4653, _T_4654) @[el2_lsu_bus_buffer.scala 567:56] + node _T_4656 = and(_T_4652, _T_4655) @[el2_lsu_bus_buffer.scala 567:38] + node _T_4657 = eq(obuf_tag0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 567:92] + node _T_4658 = eq(obuf_tag1, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 567:126] + node _T_4659 = and(obuf_merge, _T_4658) @[el2_lsu_bus_buffer.scala 567:114] + node _T_4660 = or(_T_4657, _T_4659) @[el2_lsu_bus_buffer.scala 567:100] + node _T_4661 = eq(_T_4660, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 567:80] + node _T_4662 = and(_T_4656, _T_4661) @[el2_lsu_bus_buffer.scala 567:78] + node _T_4663 = eq(buf_state[1], UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 566:71] + node _T_4664 = and(UInt<1>("h01"), obuf_valid) @[el2_lsu_bus_buffer.scala 567:25] + node _T_4665 = bits(obuf_addr, 31, 3) @[el2_lsu_bus_buffer.scala 567:50] + node _T_4666 = bits(buf_addr[1], 31, 3) @[el2_lsu_bus_buffer.scala 567:70] + node _T_4667 = eq(_T_4665, _T_4666) @[el2_lsu_bus_buffer.scala 567:56] + node _T_4668 = and(_T_4664, _T_4667) @[el2_lsu_bus_buffer.scala 567:38] + node _T_4669 = eq(obuf_tag0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 567:92] + node _T_4670 = eq(obuf_tag1, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 567:126] + node _T_4671 = and(obuf_merge, _T_4670) @[el2_lsu_bus_buffer.scala 567:114] + node _T_4672 = or(_T_4669, _T_4671) @[el2_lsu_bus_buffer.scala 567:100] + node _T_4673 = eq(_T_4672, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 567:80] + node _T_4674 = and(_T_4668, _T_4673) @[el2_lsu_bus_buffer.scala 567:78] + node _T_4675 = eq(buf_state[2], UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 566:71] + node _T_4676 = and(UInt<1>("h01"), obuf_valid) @[el2_lsu_bus_buffer.scala 567:25] + node _T_4677 = bits(obuf_addr, 31, 3) @[el2_lsu_bus_buffer.scala 567:50] + node _T_4678 = bits(buf_addr[2], 31, 3) @[el2_lsu_bus_buffer.scala 567:70] + node _T_4679 = eq(_T_4677, _T_4678) @[el2_lsu_bus_buffer.scala 567:56] + node _T_4680 = and(_T_4676, _T_4679) @[el2_lsu_bus_buffer.scala 567:38] + node _T_4681 = eq(obuf_tag0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 567:92] + node _T_4682 = eq(obuf_tag1, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 567:126] + node _T_4683 = and(obuf_merge, _T_4682) @[el2_lsu_bus_buffer.scala 567:114] + node _T_4684 = or(_T_4681, _T_4683) @[el2_lsu_bus_buffer.scala 567:100] + node _T_4685 = eq(_T_4684, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 567:80] + node _T_4686 = and(_T_4680, _T_4685) @[el2_lsu_bus_buffer.scala 567:78] + node _T_4687 = eq(buf_state[3], UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 566:71] + node _T_4688 = and(UInt<1>("h01"), obuf_valid) @[el2_lsu_bus_buffer.scala 567:25] + node _T_4689 = bits(obuf_addr, 31, 3) @[el2_lsu_bus_buffer.scala 567:50] + node _T_4690 = bits(buf_addr[3], 31, 3) @[el2_lsu_bus_buffer.scala 567:70] + node _T_4691 = eq(_T_4689, _T_4690) @[el2_lsu_bus_buffer.scala 567:56] + node _T_4692 = and(_T_4688, _T_4691) @[el2_lsu_bus_buffer.scala 567:38] + node _T_4693 = eq(obuf_tag0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 567:92] + node _T_4694 = eq(obuf_tag1, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 567:126] + node _T_4695 = and(obuf_merge, _T_4694) @[el2_lsu_bus_buffer.scala 567:114] + node _T_4696 = or(_T_4693, _T_4695) @[el2_lsu_bus_buffer.scala 567:100] + node _T_4697 = eq(_T_4696, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 567:80] + node _T_4698 = and(_T_4692, _T_4697) @[el2_lsu_bus_buffer.scala 567:78] + node _T_4699 = mux(_T_4651, _T_4662, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4700 = mux(_T_4663, _T_4674, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4701 = mux(_T_4675, _T_4686, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4702 = mux(_T_4687, _T_4698, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4703 = or(_T_4699, _T_4700) @[Mux.scala 27:72] + node _T_4704 = or(_T_4703, _T_4701) @[Mux.scala 27:72] + node _T_4705 = or(_T_4704, _T_4702) @[Mux.scala 27:72] + wire _T_4706 : UInt<1> @[Mux.scala 27:72] + _T_4706 <= _T_4705 @[Mux.scala 27:72] + bus_addr_match_pending <= _T_4706 @[el2_lsu_bus_buffer.scala 566:26] + node _T_4707 = or(obuf_cmd_done, obuf_data_done) @[el2_lsu_bus_buffer.scala 569:54] + node _T_4708 = mux(obuf_cmd_done, io.lsu_axi_wready, io.lsu_axi_awready) @[el2_lsu_bus_buffer.scala 569:75] + node _T_4709 = and(io.lsu_axi_awready, io.lsu_axi_awready) @[el2_lsu_bus_buffer.scala 569:150] + node _T_4710 = mux(_T_4707, _T_4708, _T_4709) @[el2_lsu_bus_buffer.scala 569:39] + node _T_4711 = mux(obuf_write, _T_4710, io.lsu_axi_arready) @[el2_lsu_bus_buffer.scala 569:23] + bus_cmd_ready <= _T_4711 @[el2_lsu_bus_buffer.scala 569:17] + node _T_4712 = and(io.lsu_axi_awvalid, io.lsu_axi_awready) @[el2_lsu_bus_buffer.scala 570:39] + bus_wcmd_sent <= _T_4712 @[el2_lsu_bus_buffer.scala 570:17] + node _T_4713 = and(io.lsu_axi_wvalid, io.lsu_axi_wready) @[el2_lsu_bus_buffer.scala 571:39] + bus_wdata_sent <= _T_4713 @[el2_lsu_bus_buffer.scala 571:18] + node _T_4714 = or(obuf_cmd_done, bus_wcmd_sent) @[el2_lsu_bus_buffer.scala 572:35] + node _T_4715 = or(obuf_data_done, bus_wdata_sent) @[el2_lsu_bus_buffer.scala 572:70] + node _T_4716 = and(_T_4714, _T_4715) @[el2_lsu_bus_buffer.scala 572:52] + node _T_4717 = and(io.lsu_axi_arvalid, io.lsu_axi_arready) @[el2_lsu_bus_buffer.scala 572:111] + node _T_4718 = or(_T_4716, _T_4717) @[el2_lsu_bus_buffer.scala 572:89] + bus_cmd_sent <= _T_4718 @[el2_lsu_bus_buffer.scala 572:16] + node _T_4719 = and(io.lsu_axi_rvalid, io.lsu_axi_rready) @[el2_lsu_bus_buffer.scala 573:37] + bus_rsp_read <= _T_4719 @[el2_lsu_bus_buffer.scala 573:16] + node _T_4720 = and(io.lsu_axi_bvalid, io.lsu_axi_bready) @[el2_lsu_bus_buffer.scala 574:38] + bus_rsp_write <= _T_4720 @[el2_lsu_bus_buffer.scala 574:17] + bus_rsp_read_tag <= io.lsu_axi_rid @[el2_lsu_bus_buffer.scala 575:20] + bus_rsp_write_tag <= io.lsu_axi_bid @[el2_lsu_bus_buffer.scala 576:21] + node _T_4721 = neq(io.lsu_axi_bresp, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 577:60] + node _T_4722 = and(bus_rsp_write, _T_4721) @[el2_lsu_bus_buffer.scala 577:40] + bus_rsp_write_error <= _T_4722 @[el2_lsu_bus_buffer.scala 577:23] + node _T_4723 = neq(io.lsu_axi_bresp, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 578:58] + node _T_4724 = and(bus_rsp_read, _T_4723) @[el2_lsu_bus_buffer.scala 578:38] + bus_rsp_read_error <= _T_4724 @[el2_lsu_bus_buffer.scala 578:22] + bus_rsp_rdata <= io.lsu_axi_rdata @[el2_lsu_bus_buffer.scala 579:17] + node _T_4725 = and(obuf_valid, obuf_write) @[el2_lsu_bus_buffer.scala 582:36] + node _T_4726 = eq(obuf_cmd_done, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 582:51] + node _T_4727 = and(_T_4725, _T_4726) @[el2_lsu_bus_buffer.scala 582:49] + node _T_4728 = eq(bus_addr_match_pending, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 582:68] + node _T_4729 = and(_T_4727, _T_4728) @[el2_lsu_bus_buffer.scala 582:66] + io.lsu_axi_awvalid <= _T_4729 @[el2_lsu_bus_buffer.scala 582:22] + io.lsu_axi_awid <= obuf_tag0 @[el2_lsu_bus_buffer.scala 583:19] + node _T_4730 = bits(obuf_addr, 31, 3) @[el2_lsu_bus_buffer.scala 584:69] + node _T_4731 = cat(_T_4730, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_4732 = mux(obuf_sideeffect, obuf_addr, _T_4731) @[el2_lsu_bus_buffer.scala 584:27] + io.lsu_axi_awaddr <= _T_4732 @[el2_lsu_bus_buffer.scala 584:21] + node _T_4733 = cat(UInt<1>("h00"), obuf_sz) @[Cat.scala 29:58] + node _T_4734 = mux(obuf_sideeffect, _T_4733, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 585:27] + io.lsu_axi_awsize <= _T_4734 @[el2_lsu_bus_buffer.scala 585:21] + io.lsu_axi_awprot <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 586:21] + node _T_4735 = mux(obuf_sideeffect, UInt<1>("h00"), UInt<4>("h0f")) @[el2_lsu_bus_buffer.scala 587:28] + io.lsu_axi_awcache <= _T_4735 @[el2_lsu_bus_buffer.scala 587:22] + node _T_4736 = bits(obuf_addr, 31, 28) @[el2_lsu_bus_buffer.scala 588:35] + io.lsu_axi_awregion <= _T_4736 @[el2_lsu_bus_buffer.scala 588:23] + io.lsu_axi_awlen <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 589:20] + io.lsu_axi_awburst <= UInt<2>("h01") @[el2_lsu_bus_buffer.scala 590:22] + io.lsu_axi_awqos <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 591:20] + io.lsu_axi_awlock <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 592:21] + node _T_4737 = and(obuf_valid, obuf_write) @[el2_lsu_bus_buffer.scala 594:35] + node _T_4738 = eq(obuf_data_done, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 594:50] + node _T_4739 = and(_T_4737, _T_4738) @[el2_lsu_bus_buffer.scala 594:48] + node _T_4740 = eq(bus_addr_match_pending, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 594:68] + node _T_4741 = and(_T_4739, _T_4740) @[el2_lsu_bus_buffer.scala 594:66] + io.lsu_axi_wvalid <= _T_4741 @[el2_lsu_bus_buffer.scala 594:21] + node _T_4742 = bits(obuf_write, 0, 0) @[Bitwise.scala 72:15] + node _T_4743 = mux(_T_4742, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_4744 = and(obuf_byteen, _T_4743) @[el2_lsu_bus_buffer.scala 595:35] + io.lsu_axi_wstrb <= _T_4744 @[el2_lsu_bus_buffer.scala 595:20] + io.lsu_axi_wdata <= obuf_data @[el2_lsu_bus_buffer.scala 596:20] + io.lsu_axi_wlast <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 597:20] + node _T_4745 = eq(obuf_write, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 599:38] + node _T_4746 = and(obuf_valid, _T_4745) @[el2_lsu_bus_buffer.scala 599:36] + node _T_4747 = eq(obuf_nosend, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 599:52] + node _T_4748 = and(_T_4746, _T_4747) @[el2_lsu_bus_buffer.scala 599:50] + node _T_4749 = eq(bus_addr_match_pending, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 599:67] + node _T_4750 = and(_T_4748, _T_4749) @[el2_lsu_bus_buffer.scala 599:65] + io.lsu_axi_arvalid <= _T_4750 @[el2_lsu_bus_buffer.scala 599:22] + io.lsu_axi_arid <= obuf_tag0 @[el2_lsu_bus_buffer.scala 600:19] + node _T_4751 = bits(obuf_addr, 31, 3) @[el2_lsu_bus_buffer.scala 601:69] + node _T_4752 = cat(_T_4751, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_4753 = mux(obuf_sideeffect, obuf_addr, _T_4752) @[el2_lsu_bus_buffer.scala 601:27] + io.lsu_axi_araddr <= _T_4753 @[el2_lsu_bus_buffer.scala 601:21] + node _T_4754 = cat(UInt<1>("h00"), obuf_sz) @[Cat.scala 29:58] + node _T_4755 = mux(obuf_sideeffect, _T_4754, UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 602:27] + io.lsu_axi_arsize <= _T_4755 @[el2_lsu_bus_buffer.scala 602:21] + io.lsu_axi_arprot <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 603:21] + node _T_4756 = mux(obuf_sideeffect, UInt<4>("h00"), UInt<4>("h0f")) @[el2_lsu_bus_buffer.scala 604:28] + io.lsu_axi_arcache <= _T_4756 @[el2_lsu_bus_buffer.scala 604:22] + node _T_4757 = bits(obuf_addr, 31, 28) @[el2_lsu_bus_buffer.scala 605:35] + io.lsu_axi_arregion <= _T_4757 @[el2_lsu_bus_buffer.scala 605:23] + io.lsu_axi_arlen <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 606:20] + io.lsu_axi_arburst <= UInt<2>("h01") @[el2_lsu_bus_buffer.scala 607:22] + io.lsu_axi_arqos <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 608:20] + io.lsu_axi_arlock <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 609:21] + io.lsu_axi_bready <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 610:21] + io.lsu_axi_rready <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 611:21] + node _T_4758 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 612:81] + node _T_4759 = bits(buf_error, 0, 0) @[el2_lsu_bus_buffer.scala 612:125] + node _T_4760 = and(io.lsu_bus_clk_en_q, _T_4759) @[el2_lsu_bus_buffer.scala 612:114] + node _T_4761 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 612:140] + node _T_4762 = and(_T_4760, _T_4761) @[el2_lsu_bus_buffer.scala 612:129] + node _T_4763 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 612:81] + node _T_4764 = bits(buf_error, 1, 1) @[el2_lsu_bus_buffer.scala 612:125] + node _T_4765 = and(io.lsu_bus_clk_en_q, _T_4764) @[el2_lsu_bus_buffer.scala 612:114] + node _T_4766 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 612:140] + node _T_4767 = and(_T_4765, _T_4766) @[el2_lsu_bus_buffer.scala 612:129] + node _T_4768 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 612:81] + node _T_4769 = bits(buf_error, 2, 2) @[el2_lsu_bus_buffer.scala 612:125] + node _T_4770 = and(io.lsu_bus_clk_en_q, _T_4769) @[el2_lsu_bus_buffer.scala 612:114] + node _T_4771 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 612:140] + node _T_4772 = and(_T_4770, _T_4771) @[el2_lsu_bus_buffer.scala 612:129] + node _T_4773 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 612:81] + node _T_4774 = bits(buf_error, 3, 3) @[el2_lsu_bus_buffer.scala 612:125] + node _T_4775 = and(io.lsu_bus_clk_en_q, _T_4774) @[el2_lsu_bus_buffer.scala 612:114] + node _T_4776 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 612:140] + node _T_4777 = and(_T_4775, _T_4776) @[el2_lsu_bus_buffer.scala 612:129] + node _T_4778 = mux(_T_4758, _T_4762, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4779 = mux(_T_4763, _T_4767, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4780 = mux(_T_4768, _T_4772, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4781 = mux(_T_4773, _T_4777, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4782 = or(_T_4778, _T_4779) @[Mux.scala 27:72] + node _T_4783 = or(_T_4782, _T_4780) @[Mux.scala 27:72] + node _T_4784 = or(_T_4783, _T_4781) @[Mux.scala 27:72] + wire _T_4785 : UInt<1> @[Mux.scala 27:72] + _T_4785 <= _T_4784 @[Mux.scala 27:72] + io.lsu_imprecise_error_store_any <= _T_4785 @[el2_lsu_bus_buffer.scala 612:36] + node _T_4786 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 613:87] + node _T_4787 = bits(buf_error, 0, 0) @[el2_lsu_bus_buffer.scala 613:109] + node _T_4788 = and(_T_4786, _T_4787) @[el2_lsu_bus_buffer.scala 613:98] + node _T_4789 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 613:124] + node _T_4790 = and(_T_4788, _T_4789) @[el2_lsu_bus_buffer.scala 613:113] + node _T_4791 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 613:87] + node _T_4792 = bits(buf_error, 1, 1) @[el2_lsu_bus_buffer.scala 613:109] + node _T_4793 = and(_T_4791, _T_4792) @[el2_lsu_bus_buffer.scala 613:98] + node _T_4794 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 613:124] + node _T_4795 = and(_T_4793, _T_4794) @[el2_lsu_bus_buffer.scala 613:113] + node _T_4796 = mux(_T_4790, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4797 = mux(_T_4795, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4798 = or(_T_4796, _T_4797) @[Mux.scala 27:72] + wire lsu_imprecise_error_store_tag : UInt<1> @[Mux.scala 27:72] + lsu_imprecise_error_store_tag <= _T_4798 @[Mux.scala 27:72] + node _T_4799 = eq(io.lsu_imprecise_error_store_any, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 615:72] + node _T_4800 = and(io.lsu_nonblock_load_data_error, _T_4799) @[el2_lsu_bus_buffer.scala 615:70] + io.lsu_imprecise_error_load_any <= _T_4800 @[el2_lsu_bus_buffer.scala 615:35] + node _T_4801 = eq(lsu_imprecise_error_store_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_4802 = eq(lsu_imprecise_error_store_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_4803 = mux(_T_4801, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4804 = mux(_T_4802, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4805 = or(_T_4803, _T_4804) @[Mux.scala 27:72] + wire _T_4806 : UInt<32> @[Mux.scala 27:72] + _T_4806 <= _T_4805 @[Mux.scala 27:72] + node _T_4807 = eq(io.lsu_nonblock_load_data_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_4808 = eq(io.lsu_nonblock_load_data_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_4809 = eq(io.lsu_nonblock_load_data_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_4810 = eq(io.lsu_nonblock_load_data_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:123] + node _T_4811 = mux(_T_4807, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4812 = mux(_T_4808, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4813 = mux(_T_4809, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4814 = mux(_T_4810, buf_addr[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4815 = or(_T_4811, _T_4812) @[Mux.scala 27:72] + node _T_4816 = or(_T_4815, _T_4813) @[Mux.scala 27:72] + node _T_4817 = or(_T_4816, _T_4814) @[Mux.scala 27:72] + wire _T_4818 : UInt<32> @[Mux.scala 27:72] + _T_4818 <= _T_4817 @[Mux.scala 27:72] + node _T_4819 = mux(io.lsu_imprecise_error_store_any, _T_4806, _T_4818) @[el2_lsu_bus_buffer.scala 616:41] + io.lsu_imprecise_error_addr_any <= _T_4819 @[el2_lsu_bus_buffer.scala 616:35] + lsu_bus_cntr_overflow <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 617:25] + io.lsu_bus_idle_any <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 619:23] + node _T_4820 = and(io.lsu_axi_awvalid, io.lsu_axi_awready) @[el2_lsu_bus_buffer.scala 622:46] + node _T_4821 = and(io.lsu_axi_wvalid, io.lsu_axi_wready) @[el2_lsu_bus_buffer.scala 622:89] + node _T_4822 = or(_T_4820, _T_4821) @[el2_lsu_bus_buffer.scala 622:68] + node _T_4823 = and(io.lsu_axi_arvalid, io.lsu_axi_arready) @[el2_lsu_bus_buffer.scala 622:132] + node _T_4824 = or(_T_4822, _T_4823) @[el2_lsu_bus_buffer.scala 622:110] + io.lsu_pmu_bus_trxn <= _T_4824 @[el2_lsu_bus_buffer.scala 622:23] + node _T_4825 = and(io.lsu_busreq_r, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 623:48] + node _T_4826 = and(_T_4825, io.lsu_commit_r) @[el2_lsu_bus_buffer.scala 623:65] + io.lsu_pmu_bus_misaligned <= _T_4826 @[el2_lsu_bus_buffer.scala 623:29] + node _T_4827 = or(io.lsu_imprecise_error_load_any, io.lsu_imprecise_error_store_any) @[el2_lsu_bus_buffer.scala 624:59] + io.lsu_pmu_bus_error <= _T_4827 @[el2_lsu_bus_buffer.scala 624:24] + node _T_4828 = eq(io.lsu_axi_awready, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 626:48] + node _T_4829 = and(io.lsu_axi_awvalid, _T_4828) @[el2_lsu_bus_buffer.scala 626:46] + node _T_4830 = eq(io.lsu_axi_wready, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 626:92] + node _T_4831 = and(io.lsu_axi_wvalid, _T_4830) @[el2_lsu_bus_buffer.scala 626:90] + node _T_4832 = or(_T_4829, _T_4831) @[el2_lsu_bus_buffer.scala 626:69] + node _T_4833 = eq(io.lsu_axi_arready, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 626:136] + node _T_4834 = and(io.lsu_axi_arvalid, _T_4833) @[el2_lsu_bus_buffer.scala 626:134] + node _T_4835 = or(_T_4832, _T_4834) @[el2_lsu_bus_buffer.scala 626:112] + io.lsu_pmu_bus_busy <= _T_4835 @[el2_lsu_bus_buffer.scala 626:23] + reg _T_4836 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 628:49] + _T_4836 <= WrPtr0_m @[el2_lsu_bus_buffer.scala 628:49] + WrPtr0_r <= _T_4836 @[el2_lsu_bus_buffer.scala 628:12] + reg _T_4837 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 629:49] + _T_4837 <= WrPtr1_m @[el2_lsu_bus_buffer.scala 629:49] + WrPtr1_r <= _T_4837 @[el2_lsu_bus_buffer.scala 629:12] + node _T_4838 = eq(io.flush_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 630:75] + node _T_4839 = and(io.lsu_busreq_m, _T_4838) @[el2_lsu_bus_buffer.scala 630:73] + node _T_4840 = eq(io.ld_full_hit_m, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 630:89] + node _T_4841 = and(_T_4839, _T_4840) @[el2_lsu_bus_buffer.scala 630:87] + reg _T_4842 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 630:56] + _T_4842 <= _T_4841 @[el2_lsu_bus_buffer.scala 630:56] + io.lsu_busreq_r <= _T_4842 @[el2_lsu_bus_buffer.scala 630:19] + reg _T_4843 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 631:66] + _T_4843 <= io.lsu_nonblock_load_valid_m @[el2_lsu_bus_buffer.scala 631:66] + lsu_nonblock_load_valid_r <= _T_4843 @[el2_lsu_bus_buffer.scala 631:29] + diff --git a/el2_lsu_bus_buffer.v b/el2_lsu_bus_buffer.v new file mode 100644 index 00000000..f077c3ed --- /dev/null +++ b/el2_lsu_bus_buffer.v @@ -0,0 +1,4235 @@ +module rvclkhdr( + output io_l1clk, + input io_clk, + input io_en, + input io_scan_mode +); + wire clkhdr_Q; // @[el2_lib.scala 452:26] + wire clkhdr_CK; // @[el2_lib.scala 452:26] + wire clkhdr_EN; // @[el2_lib.scala 452:26] + wire clkhdr_SE; // @[el2_lib.scala 452:26] + TEC_RV_ICG clkhdr ( // @[el2_lib.scala 452:26] + .Q(clkhdr_Q), + .CK(clkhdr_CK), + .EN(clkhdr_EN), + .SE(clkhdr_SE) + ); + assign io_l1clk = clkhdr_Q; // @[el2_lib.scala 453:14] + assign clkhdr_CK = io_clk; // @[el2_lib.scala 454:18] + assign clkhdr_EN = io_en; // @[el2_lib.scala 455:18] + assign clkhdr_SE = io_scan_mode; // @[el2_lib.scala 456:18] +endmodule +module el2_lsu_bus_buffer( + input clock, + input reset, + input io_scan_mode, + input io_dec_tlu_external_ldfwd_disable, + input io_dec_tlu_wb_coalescing_disable, + input io_dec_tlu_sideeffect_posted_disable, + input io_dec_tlu_force_halt, + input io_lsu_c2_r_clk, + input io_lsu_bus_ibuf_c1_clk, + input io_lsu_bus_obuf_c1_clk, + input io_lsu_bus_buf_c1_clk, + input io_lsu_free_c2_clk, + input io_lsu_busm_clk, + input io_dec_lsu_valid_raw_d, + input io_lsu_pkt_m_fast_int, + input io_lsu_pkt_m_by, + input io_lsu_pkt_m_half, + input io_lsu_pkt_m_word, + input io_lsu_pkt_m_dword, + input io_lsu_pkt_m_load, + input io_lsu_pkt_m_store, + input io_lsu_pkt_m_unsign, + input io_lsu_pkt_m_dma, + input io_lsu_pkt_m_store_data_bypass_d, + input io_lsu_pkt_m_load_ldst_bypass_d, + input io_lsu_pkt_m_store_data_bypass_m, + input io_lsu_pkt_m_valid, + input io_lsu_pkt_r_fast_int, + input io_lsu_pkt_r_by, + input io_lsu_pkt_r_half, + input io_lsu_pkt_r_word, + input io_lsu_pkt_r_dword, + input io_lsu_pkt_r_load, + input io_lsu_pkt_r_store, + input io_lsu_pkt_r_unsign, + input io_lsu_pkt_r_dma, + input io_lsu_pkt_r_store_data_bypass_d, + input io_lsu_pkt_r_load_ldst_bypass_d, + input io_lsu_pkt_r_store_data_bypass_m, + input io_lsu_pkt_r_valid, + input [31:0] io_lsu_addr_m, + input [31:0] io_end_addr_m, + input [31:0] io_lsu_addr_r, + input [31:0] io_end_addr_r, + input [31:0] io_store_data_r, + input io_no_word_merge_r, + input io_no_dword_merge_r, + input io_lsu_busreq_m, + input io_ld_full_hit_m, + input io_flush_m_up, + input io_flush_r, + input io_lsu_commit_r, + input io_is_sideeffects_r, + input io_ldst_dual_d, + input io_ldst_dual_m, + input io_ldst_dual_r, + input [7:0] io_ldst_byteen_ext_m, + input io_lsu_axi_awready, + input io_lsu_axi_wready, + input io_lsu_axi_bvalid, + input [1:0] io_lsu_axi_bresp, + input [2:0] io_lsu_axi_bid, + input io_lsu_axi_arready, + input io_lsu_axi_rvalid, + input [2:0] io_lsu_axi_rid, + input [63:0] io_lsu_axi_rdata, + input [1:0] io_lsu_axi_rresp, + input io_lsu_bus_clk_en, + input io_lsu_bus_clk_en_q, + output io_lsu_busreq_r, + output io_lsu_bus_buffer_pend_any, + output io_lsu_bus_buffer_full_any, + output io_lsu_bus_buffer_empty_any, + output io_lsu_bus_idle_any, + output [3:0] io_ld_byte_hit_buf_lo, + output [3:0] io_ld_byte_hit_buf_hi, + output [31:0] io_ld_fwddata_buf_lo, + output [31:0] io_ld_fwddata_buf_hi, + output io_lsu_imprecise_error_load_any, + output io_lsu_imprecise_error_store_any, + output [31:0] io_lsu_imprecise_error_addr_any, + output io_lsu_nonblock_load_valid_m, + output [1:0] io_lsu_nonblock_load_tag_m, + output io_lsu_nonblock_load_inv_r, + output [1:0] io_lsu_nonblock_load_inv_tag_r, + output io_lsu_nonblock_load_data_valid, + output io_lsu_nonblock_load_data_error, + output [1:0] io_lsu_nonblock_load_data_tag, + output [31:0] io_lsu_nonblock_load_data, + output io_lsu_pmu_bus_trxn, + output io_lsu_pmu_bus_misaligned, + output io_lsu_pmu_bus_error, + output io_lsu_pmu_bus_busy, + output io_lsu_axi_awvalid, + output [2:0] io_lsu_axi_awid, + output [31:0] io_lsu_axi_awaddr, + output [3:0] io_lsu_axi_awregion, + output [7:0] io_lsu_axi_awlen, + output [2:0] io_lsu_axi_awsize, + output [1:0] io_lsu_axi_awburst, + output io_lsu_axi_awlock, + output [3:0] io_lsu_axi_awcache, + output [2:0] io_lsu_axi_awprot, + output [3:0] io_lsu_axi_awqos, + output io_lsu_axi_wvalid, + output [63:0] io_lsu_axi_wdata, + output [7:0] io_lsu_axi_wstrb, + output io_lsu_axi_wlast, + output io_lsu_axi_bready, + output io_lsu_axi_arvalid, + output [2:0] io_lsu_axi_arid, + output [31:0] io_lsu_axi_araddr, + output [3:0] io_lsu_axi_arregion, + output [7:0] io_lsu_axi_arlen, + output [2:0] io_lsu_axi_arsize, + output [1:0] io_lsu_axi_arburst, + output io_lsu_axi_arlock, + output [3:0] io_lsu_axi_arcache, + output [2:0] io_lsu_axi_arprot, + output [3:0] io_lsu_axi_arqos, + output io_lsu_axi_rready +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; + reg [31:0] _RAND_8; + reg [31:0] _RAND_9; + reg [31:0] _RAND_10; + reg [31:0] _RAND_11; + reg [31:0] _RAND_12; + reg [31:0] _RAND_13; + reg [31:0] _RAND_14; + reg [31:0] _RAND_15; + reg [31:0] _RAND_16; + reg [31:0] _RAND_17; + reg [31:0] _RAND_18; + reg [31:0] _RAND_19; + reg [31:0] _RAND_20; + reg [31:0] _RAND_21; + reg [31:0] _RAND_22; + reg [31:0] _RAND_23; + reg [31:0] _RAND_24; + reg [31:0] _RAND_25; + reg [31:0] _RAND_26; + reg [31:0] _RAND_27; + reg [31:0] _RAND_28; + reg [31:0] _RAND_29; + reg [31:0] _RAND_30; + reg [31:0] _RAND_31; + reg [31:0] _RAND_32; + reg [31:0] _RAND_33; + reg [31:0] _RAND_34; + reg [31:0] _RAND_35; + reg [31:0] _RAND_36; + reg [31:0] _RAND_37; + reg [31:0] _RAND_38; + reg [31:0] _RAND_39; + reg [31:0] _RAND_40; + reg [31:0] _RAND_41; + reg [31:0] _RAND_42; + reg [31:0] _RAND_43; + reg [31:0] _RAND_44; + reg [31:0] _RAND_45; + reg [31:0] _RAND_46; + reg [31:0] _RAND_47; + reg [31:0] _RAND_48; + reg [31:0] _RAND_49; + reg [31:0] _RAND_50; + reg [31:0] _RAND_51; + reg [31:0] _RAND_52; + reg [31:0] _RAND_53; + reg [31:0] _RAND_54; + reg [31:0] _RAND_55; + reg [31:0] _RAND_56; + reg [31:0] _RAND_57; + reg [31:0] _RAND_58; + reg [31:0] _RAND_59; + reg [31:0] _RAND_60; + reg [31:0] _RAND_61; + reg [31:0] _RAND_62; + reg [31:0] _RAND_63; + reg [31:0] _RAND_64; + reg [31:0] _RAND_65; + reg [31:0] _RAND_66; + reg [31:0] _RAND_67; + reg [31:0] _RAND_68; + reg [31:0] _RAND_69; + reg [31:0] _RAND_70; + reg [31:0] _RAND_71; + reg [31:0] _RAND_72; + reg [31:0] _RAND_73; + reg [31:0] _RAND_74; + reg [31:0] _RAND_75; + reg [31:0] _RAND_76; + reg [63:0] _RAND_77; + reg [31:0] _RAND_78; + reg [31:0] _RAND_79; + reg [31:0] _RAND_80; + reg [31:0] _RAND_81; + reg [31:0] _RAND_82; + reg [31:0] _RAND_83; + reg [31:0] _RAND_84; + reg [31:0] _RAND_85; + reg [31:0] _RAND_86; + reg [31:0] _RAND_87; + reg [31:0] _RAND_88; + reg [31:0] _RAND_89; + reg [31:0] _RAND_90; + reg [31:0] _RAND_91; + reg [31:0] _RAND_92; + reg [31:0] _RAND_93; + reg [31:0] _RAND_94; + reg [31:0] _RAND_95; + reg [31:0] _RAND_96; + reg [31:0] _RAND_97; + reg [31:0] _RAND_98; + reg [31:0] _RAND_99; + reg [31:0] _RAND_100; + reg [31:0] _RAND_101; + reg [31:0] _RAND_102; + reg [31:0] _RAND_103; +`endif // RANDOMIZE_REG_INIT + wire rvclkhdr_io_l1clk; // @[el2_lib.scala 472:23] + wire rvclkhdr_io_clk; // @[el2_lib.scala 472:23] + wire rvclkhdr_io_en; // @[el2_lib.scala 472:23] + wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 472:23] + wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 472:23] + wire rvclkhdr_1_io_clk; // @[el2_lib.scala 472:23] + wire rvclkhdr_1_io_en; // @[el2_lib.scala 472:23] + wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 472:23] + wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 472:23] + wire rvclkhdr_2_io_clk; // @[el2_lib.scala 472:23] + wire rvclkhdr_2_io_en; // @[el2_lib.scala 472:23] + wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 472:23] + wire rvclkhdr_3_io_l1clk; // @[el2_lib.scala 472:23] + wire rvclkhdr_3_io_clk; // @[el2_lib.scala 472:23] + wire rvclkhdr_3_io_en; // @[el2_lib.scala 472:23] + wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 472:23] + wire rvclkhdr_4_io_l1clk; // @[el2_lib.scala 472:23] + wire rvclkhdr_4_io_clk; // @[el2_lib.scala 472:23] + wire rvclkhdr_4_io_en; // @[el2_lib.scala 472:23] + wire rvclkhdr_4_io_scan_mode; // @[el2_lib.scala 472:23] + wire rvclkhdr_5_io_l1clk; // @[el2_lib.scala 472:23] + wire rvclkhdr_5_io_clk; // @[el2_lib.scala 472:23] + wire rvclkhdr_5_io_en; // @[el2_lib.scala 472:23] + wire rvclkhdr_5_io_scan_mode; // @[el2_lib.scala 472:23] + wire rvclkhdr_6_io_l1clk; // @[el2_lib.scala 472:23] + wire rvclkhdr_6_io_clk; // @[el2_lib.scala 472:23] + wire rvclkhdr_6_io_en; // @[el2_lib.scala 472:23] + wire rvclkhdr_6_io_scan_mode; // @[el2_lib.scala 472:23] + wire rvclkhdr_7_io_l1clk; // @[el2_lib.scala 472:23] + wire rvclkhdr_7_io_clk; // @[el2_lib.scala 472:23] + wire rvclkhdr_7_io_en; // @[el2_lib.scala 472:23] + wire rvclkhdr_7_io_scan_mode; // @[el2_lib.scala 472:23] + wire rvclkhdr_8_io_l1clk; // @[el2_lib.scala 472:23] + wire rvclkhdr_8_io_clk; // @[el2_lib.scala 472:23] + wire rvclkhdr_8_io_en; // @[el2_lib.scala 472:23] + wire rvclkhdr_8_io_scan_mode; // @[el2_lib.scala 472:23] + wire rvclkhdr_9_io_l1clk; // @[el2_lib.scala 472:23] + wire rvclkhdr_9_io_clk; // @[el2_lib.scala 472:23] + wire rvclkhdr_9_io_en; // @[el2_lib.scala 472:23] + wire rvclkhdr_9_io_scan_mode; // @[el2_lib.scala 472:23] + wire rvclkhdr_10_io_l1clk; // @[el2_lib.scala 472:23] + wire rvclkhdr_10_io_clk; // @[el2_lib.scala 472:23] + wire rvclkhdr_10_io_en; // @[el2_lib.scala 472:23] + wire rvclkhdr_10_io_scan_mode; // @[el2_lib.scala 472:23] + wire rvclkhdr_11_io_l1clk; // @[el2_lib.scala 472:23] + wire rvclkhdr_11_io_clk; // @[el2_lib.scala 472:23] + wire rvclkhdr_11_io_en; // @[el2_lib.scala 472:23] + wire rvclkhdr_11_io_scan_mode; // @[el2_lib.scala 472:23] + wire [3:0] ldst_byteen_hi_m = io_ldst_byteen_ext_m[7:4]; // @[el2_lsu_bus_buffer.scala 125:46] + wire [3:0] ldst_byteen_lo_m = io_ldst_byteen_ext_m[3:0]; // @[el2_lsu_bus_buffer.scala 126:46] + reg [31:0] buf_addr_0; // @[el2_lib.scala 478:16] + wire _T_2 = io_lsu_addr_m[31:2] == buf_addr_0[31:2]; // @[el2_lsu_bus_buffer.scala 128:74] + reg _T_4210; // @[Reg.scala 27:20] + reg _T_4207; // @[Reg.scala 27:20] + reg _T_4204; // @[Reg.scala 27:20] + reg _T_4201; // @[Reg.scala 27:20] + wire [3:0] buf_write = {_T_4210,_T_4207,_T_4204,_T_4201}; // @[Cat.scala 29:58] + wire _T_4 = _T_2 & buf_write[0]; // @[el2_lsu_bus_buffer.scala 128:98] + reg [2:0] buf_state_0; // @[Reg.scala 27:20] + wire _T_5 = buf_state_0 != 3'h0; // @[el2_lsu_bus_buffer.scala 128:129] + wire _T_6 = _T_4 & _T_5; // @[el2_lsu_bus_buffer.scala 128:113] + wire ld_addr_hitvec_lo_0 = _T_6 & io_lsu_busreq_m; // @[el2_lsu_bus_buffer.scala 128:141] + reg [31:0] buf_addr_1; // @[el2_lib.scala 478:16] + wire _T_9 = io_lsu_addr_m[31:2] == buf_addr_1[31:2]; // @[el2_lsu_bus_buffer.scala 128:74] + wire _T_11 = _T_9 & buf_write[1]; // @[el2_lsu_bus_buffer.scala 128:98] + reg [2:0] buf_state_1; // @[Reg.scala 27:20] + wire _T_12 = buf_state_1 != 3'h0; // @[el2_lsu_bus_buffer.scala 128:129] + wire _T_13 = _T_11 & _T_12; // @[el2_lsu_bus_buffer.scala 128:113] + wire ld_addr_hitvec_lo_1 = _T_13 & io_lsu_busreq_m; // @[el2_lsu_bus_buffer.scala 128:141] + reg [31:0] buf_addr_2; // @[el2_lib.scala 478:16] + wire _T_16 = io_lsu_addr_m[31:2] == buf_addr_2[31:2]; // @[el2_lsu_bus_buffer.scala 128:74] + wire _T_18 = _T_16 & buf_write[2]; // @[el2_lsu_bus_buffer.scala 128:98] + reg [2:0] buf_state_2; // @[Reg.scala 27:20] + wire _T_19 = buf_state_2 != 3'h0; // @[el2_lsu_bus_buffer.scala 128:129] + wire _T_20 = _T_18 & _T_19; // @[el2_lsu_bus_buffer.scala 128:113] + wire ld_addr_hitvec_lo_2 = _T_20 & io_lsu_busreq_m; // @[el2_lsu_bus_buffer.scala 128:141] + reg [31:0] buf_addr_3; // @[el2_lib.scala 478:16] + wire _T_23 = io_lsu_addr_m[31:2] == buf_addr_3[31:2]; // @[el2_lsu_bus_buffer.scala 128:74] + wire _T_25 = _T_23 & buf_write[3]; // @[el2_lsu_bus_buffer.scala 128:98] + reg [2:0] buf_state_3; // @[Reg.scala 27:20] + wire _T_26 = buf_state_3 != 3'h0; // @[el2_lsu_bus_buffer.scala 128:129] + wire _T_27 = _T_25 & _T_26; // @[el2_lsu_bus_buffer.scala 128:113] + wire ld_addr_hitvec_lo_3 = _T_27 & io_lsu_busreq_m; // @[el2_lsu_bus_buffer.scala 128:141] + wire _T_30 = io_end_addr_m[31:2] == buf_addr_0[31:2]; // @[el2_lsu_bus_buffer.scala 129:74] + wire _T_32 = _T_30 & buf_write[0]; // @[el2_lsu_bus_buffer.scala 129:98] + wire _T_34 = _T_32 & _T_5; // @[el2_lsu_bus_buffer.scala 129:113] + wire ld_addr_hitvec_hi_0 = _T_34 & io_lsu_busreq_m; // @[el2_lsu_bus_buffer.scala 129:141] + wire _T_37 = io_end_addr_m[31:2] == buf_addr_1[31:2]; // @[el2_lsu_bus_buffer.scala 129:74] + wire _T_39 = _T_37 & buf_write[1]; // @[el2_lsu_bus_buffer.scala 129:98] + wire _T_41 = _T_39 & _T_12; // @[el2_lsu_bus_buffer.scala 129:113] + wire ld_addr_hitvec_hi_1 = _T_41 & io_lsu_busreq_m; // @[el2_lsu_bus_buffer.scala 129:141] + wire _T_44 = io_end_addr_m[31:2] == buf_addr_2[31:2]; // @[el2_lsu_bus_buffer.scala 129:74] + wire _T_46 = _T_44 & buf_write[2]; // @[el2_lsu_bus_buffer.scala 129:98] + wire _T_48 = _T_46 & _T_19; // @[el2_lsu_bus_buffer.scala 129:113] + wire ld_addr_hitvec_hi_2 = _T_48 & io_lsu_busreq_m; // @[el2_lsu_bus_buffer.scala 129:141] + wire _T_51 = io_end_addr_m[31:2] == buf_addr_3[31:2]; // @[el2_lsu_bus_buffer.scala 129:74] + wire _T_53 = _T_51 & buf_write[3]; // @[el2_lsu_bus_buffer.scala 129:98] + wire _T_55 = _T_53 & _T_26; // @[el2_lsu_bus_buffer.scala 129:113] + wire ld_addr_hitvec_hi_3 = _T_55 & io_lsu_busreq_m; // @[el2_lsu_bus_buffer.scala 129:141] + reg [2:0] _T_4237; // @[Reg.scala 27:20] + wire [3:0] buf_byteen_3 = {{1'd0}, _T_4237}; // @[el2_lsu_bus_buffer.scala 134:24 el2_lsu_bus_buffer.scala 135:14 el2_lsu_bus_buffer.scala 531:16] + wire _T_99 = ld_addr_hitvec_lo_3 & buf_byteen_3[0]; // @[el2_lsu_bus_buffer.scala 191:95] + wire _T_101 = _T_99 & ldst_byteen_lo_m[0]; // @[el2_lsu_bus_buffer.scala 191:114] + reg [2:0] _T_4235; // @[Reg.scala 27:20] + wire [3:0] buf_byteen_2 = {{1'd0}, _T_4235}; // @[el2_lsu_bus_buffer.scala 134:24 el2_lsu_bus_buffer.scala 135:14 el2_lsu_bus_buffer.scala 531:16] + wire _T_95 = ld_addr_hitvec_lo_2 & buf_byteen_2[0]; // @[el2_lsu_bus_buffer.scala 191:95] + wire _T_97 = _T_95 & ldst_byteen_lo_m[0]; // @[el2_lsu_bus_buffer.scala 191:114] + reg [2:0] _T_4233; // @[Reg.scala 27:20] + wire [3:0] buf_byteen_1 = {{1'd0}, _T_4233}; // @[el2_lsu_bus_buffer.scala 134:24 el2_lsu_bus_buffer.scala 135:14 el2_lsu_bus_buffer.scala 531:16] + wire _T_91 = ld_addr_hitvec_lo_1 & buf_byteen_1[0]; // @[el2_lsu_bus_buffer.scala 191:95] + wire _T_93 = _T_91 & ldst_byteen_lo_m[0]; // @[el2_lsu_bus_buffer.scala 191:114] + reg [2:0] _T_4231; // @[Reg.scala 27:20] + wire [3:0] buf_byteen_0 = {{1'd0}, _T_4231}; // @[el2_lsu_bus_buffer.scala 134:24 el2_lsu_bus_buffer.scala 135:14 el2_lsu_bus_buffer.scala 531:16] + wire _T_87 = ld_addr_hitvec_lo_0 & buf_byteen_0[0]; // @[el2_lsu_bus_buffer.scala 191:95] + wire _T_89 = _T_87 & ldst_byteen_lo_m[0]; // @[el2_lsu_bus_buffer.scala 191:114] + wire [3:0] ld_byte_hitvec_lo_0 = {_T_101,_T_97,_T_93,_T_89}; // @[Cat.scala 29:58] + reg [3:0] buf_ageQ_3; // @[el2_lsu_bus_buffer.scala 515:60] + wire _T_2472 = buf_state_3 == 3'h2; // @[el2_lsu_bus_buffer.scala 428:94] + wire _T_3957 = 3'h0 == buf_state_3; // @[Conditional.scala 37:30] + wire _T_3980 = 3'h1 == buf_state_3; // @[Conditional.scala 37:30] + wire _T_3984 = 3'h2 == buf_state_3; // @[Conditional.scala 37:30] + reg [1:0] _T_1772; // @[Reg.scala 27:20] + wire [2:0] obuf_tag0 = {{1'd0}, _T_1772}; // @[el2_lsu_bus_buffer.scala 381:13] + wire _T_3991 = obuf_tag0 == 3'h3; // @[el2_lsu_bus_buffer.scala 470:48] + reg obuf_merge; // @[Reg.scala 27:20] + reg [1:0] obuf_tag1; // @[Reg.scala 27:20] + wire [2:0] _GEN_350 = {{1'd0}, obuf_tag1}; // @[el2_lsu_bus_buffer.scala 470:104] + wire _T_3992 = _GEN_350 == 3'h3; // @[el2_lsu_bus_buffer.scala 470:104] + wire _T_3993 = obuf_merge & _T_3992; // @[el2_lsu_bus_buffer.scala 470:91] + wire _T_3994 = _T_3991 | _T_3993; // @[el2_lsu_bus_buffer.scala 470:77] + reg obuf_valid; // @[el2_lsu_bus_buffer.scala 375:51] + wire _T_3995 = _T_3994 & obuf_valid; // @[el2_lsu_bus_buffer.scala 470:135] + reg obuf_wr_enQ; // @[el2_lsu_bus_buffer.scala 374:55] + wire _T_3996 = _T_3995 & obuf_wr_enQ; // @[el2_lsu_bus_buffer.scala 470:148] + wire _GEN_280 = _T_3984 & _T_3996; // @[Conditional.scala 39:67] + wire _GEN_293 = _T_3980 ? 1'h0 : _GEN_280; // @[Conditional.scala 39:67] + wire buf_cmd_state_bus_en_3 = _T_3957 ? 1'h0 : _GEN_293; // @[Conditional.scala 40:58] + wire _T_2473 = _T_2472 & buf_cmd_state_bus_en_3; // @[el2_lsu_bus_buffer.scala 428:104] + wire _T_2474 = buf_ageQ_3[3] & _T_2473; // @[el2_lsu_bus_buffer.scala 428:78] + wire _T_2468 = buf_state_2 == 3'h2; // @[el2_lsu_bus_buffer.scala 428:94] + wire _T_3764 = 3'h0 == buf_state_2; // @[Conditional.scala 37:30] + wire _T_3787 = 3'h1 == buf_state_2; // @[Conditional.scala 37:30] + wire _T_3791 = 3'h2 == buf_state_2; // @[Conditional.scala 37:30] + wire _T_3798 = obuf_tag0 == 3'h2; // @[el2_lsu_bus_buffer.scala 470:48] + wire _T_3799 = _GEN_350 == 3'h2; // @[el2_lsu_bus_buffer.scala 470:104] + wire _T_3800 = obuf_merge & _T_3799; // @[el2_lsu_bus_buffer.scala 470:91] + wire _T_3801 = _T_3798 | _T_3800; // @[el2_lsu_bus_buffer.scala 470:77] + wire _T_3802 = _T_3801 & obuf_valid; // @[el2_lsu_bus_buffer.scala 470:135] + wire _T_3803 = _T_3802 & obuf_wr_enQ; // @[el2_lsu_bus_buffer.scala 470:148] + wire _GEN_204 = _T_3791 & _T_3803; // @[Conditional.scala 39:67] + wire _GEN_217 = _T_3787 ? 1'h0 : _GEN_204; // @[Conditional.scala 39:67] + wire buf_cmd_state_bus_en_2 = _T_3764 ? 1'h0 : _GEN_217; // @[Conditional.scala 40:58] + wire _T_2469 = _T_2468 & buf_cmd_state_bus_en_2; // @[el2_lsu_bus_buffer.scala 428:104] + wire _T_2470 = buf_ageQ_3[2] & _T_2469; // @[el2_lsu_bus_buffer.scala 428:78] + wire _T_2464 = buf_state_1 == 3'h2; // @[el2_lsu_bus_buffer.scala 428:94] + wire _T_3571 = 3'h0 == buf_state_1; // @[Conditional.scala 37:30] + wire _T_3594 = 3'h1 == buf_state_1; // @[Conditional.scala 37:30] + wire _T_3598 = 3'h2 == buf_state_1; // @[Conditional.scala 37:30] + wire _T_3605 = obuf_tag0 == 3'h1; // @[el2_lsu_bus_buffer.scala 470:48] + wire _T_3606 = _GEN_350 == 3'h1; // @[el2_lsu_bus_buffer.scala 470:104] + wire _T_3607 = obuf_merge & _T_3606; // @[el2_lsu_bus_buffer.scala 470:91] + wire _T_3608 = _T_3605 | _T_3607; // @[el2_lsu_bus_buffer.scala 470:77] + wire _T_3609 = _T_3608 & obuf_valid; // @[el2_lsu_bus_buffer.scala 470:135] + wire _T_3610 = _T_3609 & obuf_wr_enQ; // @[el2_lsu_bus_buffer.scala 470:148] + wire _GEN_128 = _T_3598 & _T_3610; // @[Conditional.scala 39:67] + wire _GEN_141 = _T_3594 ? 1'h0 : _GEN_128; // @[Conditional.scala 39:67] + wire buf_cmd_state_bus_en_1 = _T_3571 ? 1'h0 : _GEN_141; // @[Conditional.scala 40:58] + wire _T_2465 = _T_2464 & buf_cmd_state_bus_en_1; // @[el2_lsu_bus_buffer.scala 428:104] + wire _T_2466 = buf_ageQ_3[1] & _T_2465; // @[el2_lsu_bus_buffer.scala 428:78] + wire _T_2460 = buf_state_0 == 3'h2; // @[el2_lsu_bus_buffer.scala 428:94] + wire _T_3378 = 3'h0 == buf_state_0; // @[Conditional.scala 37:30] + wire _T_3401 = 3'h1 == buf_state_0; // @[Conditional.scala 37:30] + wire _T_3405 = 3'h2 == buf_state_0; // @[Conditional.scala 37:30] + wire _T_3412 = obuf_tag0 == 3'h0; // @[el2_lsu_bus_buffer.scala 470:48] + wire _T_3413 = _GEN_350 == 3'h0; // @[el2_lsu_bus_buffer.scala 470:104] + wire _T_3414 = obuf_merge & _T_3413; // @[el2_lsu_bus_buffer.scala 470:91] + wire _T_3415 = _T_3412 | _T_3414; // @[el2_lsu_bus_buffer.scala 470:77] + wire _T_3416 = _T_3415 & obuf_valid; // @[el2_lsu_bus_buffer.scala 470:135] + wire _T_3417 = _T_3416 & obuf_wr_enQ; // @[el2_lsu_bus_buffer.scala 470:148] + wire _GEN_52 = _T_3405 & _T_3417; // @[Conditional.scala 39:67] + wire _GEN_65 = _T_3401 ? 1'h0 : _GEN_52; // @[Conditional.scala 39:67] + wire buf_cmd_state_bus_en_0 = _T_3378 ? 1'h0 : _GEN_65; // @[Conditional.scala 40:58] + wire _T_2461 = _T_2460 & buf_cmd_state_bus_en_0; // @[el2_lsu_bus_buffer.scala 428:104] + wire _T_2462 = buf_ageQ_3[0] & _T_2461; // @[el2_lsu_bus_buffer.scala 428:78] + wire [3:0] buf_age_3 = {_T_2474,_T_2470,_T_2466,_T_2462}; // @[Cat.scala 29:58] + wire _T_2573 = ~buf_age_3[2]; // @[el2_lsu_bus_buffer.scala 429:91] + wire _T_2575 = _T_2573 & _T_19; // @[el2_lsu_bus_buffer.scala 429:106] + wire _T_2567 = ~buf_age_3[1]; // @[el2_lsu_bus_buffer.scala 429:91] + wire _T_2569 = _T_2567 & _T_12; // @[el2_lsu_bus_buffer.scala 429:106] + wire _T_2561 = ~buf_age_3[0]; // @[el2_lsu_bus_buffer.scala 429:91] + wire _T_2563 = _T_2561 & _T_5; // @[el2_lsu_bus_buffer.scala 429:106] + wire [3:0] buf_age_younger_3 = {1'h0,_T_2575,_T_2569,_T_2563}; // @[Cat.scala 29:58] + wire [3:0] _T_255 = ld_byte_hitvec_lo_0 & buf_age_younger_3; // @[el2_lsu_bus_buffer.scala 196:122] + wire _T_256 = |_T_255; // @[el2_lsu_bus_buffer.scala 196:144] + wire _T_257 = ~_T_256; // @[el2_lsu_bus_buffer.scala 196:99] + wire _T_258 = ld_byte_hitvec_lo_0[3] & _T_257; // @[el2_lsu_bus_buffer.scala 196:97] + reg [31:0] ibuf_addr; // @[el2_lib.scala 478:16] + wire _T_512 = io_lsu_addr_m[31:2] == ibuf_addr[31:2]; // @[el2_lsu_bus_buffer.scala 202:51] + reg ibuf_write; // @[Reg.scala 27:20] + wire _T_513 = _T_512 & ibuf_write; // @[el2_lsu_bus_buffer.scala 202:73] + reg ibuf_valid; // @[el2_lsu_bus_buffer.scala 270:24] + wire _T_514 = _T_513 & ibuf_valid; // @[el2_lsu_bus_buffer.scala 202:86] + wire ld_addr_ibuf_hit_lo = _T_514 & io_lsu_busreq_m; // @[el2_lsu_bus_buffer.scala 202:99] + reg [3:0] ibuf_byteen; // @[Reg.scala 27:20] + wire _T_545 = ld_addr_ibuf_hit_lo & ibuf_byteen[3]; // @[el2_lsu_bus_buffer.scala 207:48] + wire _T_547 = _T_545 & ldst_byteen_lo_m[3]; // @[el2_lsu_bus_buffer.scala 207:65] + wire [3:0] ld_byte_ibuf_hit_lo = {{3'd0}, _T_547}; // @[el2_lsu_bus_buffer.scala 207:25 el2_lsu_bus_buffer.scala 207:25 el2_lsu_bus_buffer.scala 207:25 el2_lsu_bus_buffer.scala 207:25] + wire _T_260 = ~ld_byte_ibuf_hit_lo[0]; // @[el2_lsu_bus_buffer.scala 196:150] + wire _T_261 = _T_258 & _T_260; // @[el2_lsu_bus_buffer.scala 196:148] + reg [3:0] buf_ageQ_2; // @[el2_lsu_bus_buffer.scala 515:60] + wire _T_2455 = buf_ageQ_2[3] & _T_2473; // @[el2_lsu_bus_buffer.scala 428:78] + wire _T_2451 = buf_ageQ_2[2] & _T_2469; // @[el2_lsu_bus_buffer.scala 428:78] + wire _T_2447 = buf_ageQ_2[1] & _T_2465; // @[el2_lsu_bus_buffer.scala 428:78] + wire _T_2443 = buf_ageQ_2[0] & _T_2461; // @[el2_lsu_bus_buffer.scala 428:78] + wire [3:0] buf_age_2 = {_T_2455,_T_2451,_T_2447,_T_2443}; // @[Cat.scala 29:58] + wire _T_2552 = ~buf_age_2[3]; // @[el2_lsu_bus_buffer.scala 429:91] + wire _T_2554 = _T_2552 & _T_26; // @[el2_lsu_bus_buffer.scala 429:106] + wire _T_2540 = ~buf_age_2[1]; // @[el2_lsu_bus_buffer.scala 429:91] + wire _T_2542 = _T_2540 & _T_12; // @[el2_lsu_bus_buffer.scala 429:106] + wire _T_2534 = ~buf_age_2[0]; // @[el2_lsu_bus_buffer.scala 429:91] + wire _T_2536 = _T_2534 & _T_5; // @[el2_lsu_bus_buffer.scala 429:106] + wire [3:0] buf_age_younger_2 = {_T_2554,1'h0,_T_2542,_T_2536}; // @[Cat.scala 29:58] + wire [3:0] _T_247 = ld_byte_hitvec_lo_0 & buf_age_younger_2; // @[el2_lsu_bus_buffer.scala 196:122] + wire _T_248 = |_T_247; // @[el2_lsu_bus_buffer.scala 196:144] + wire _T_249 = ~_T_248; // @[el2_lsu_bus_buffer.scala 196:99] + wire _T_250 = ld_byte_hitvec_lo_0[2] & _T_249; // @[el2_lsu_bus_buffer.scala 196:97] + wire _T_253 = _T_250 & _T_260; // @[el2_lsu_bus_buffer.scala 196:148] + reg [3:0] buf_ageQ_1; // @[el2_lsu_bus_buffer.scala 515:60] + wire _T_2436 = buf_ageQ_1[3] & _T_2473; // @[el2_lsu_bus_buffer.scala 428:78] + wire _T_2432 = buf_ageQ_1[2] & _T_2469; // @[el2_lsu_bus_buffer.scala 428:78] + wire _T_2428 = buf_ageQ_1[1] & _T_2465; // @[el2_lsu_bus_buffer.scala 428:78] + wire _T_2424 = buf_ageQ_1[0] & _T_2461; // @[el2_lsu_bus_buffer.scala 428:78] + wire [3:0] buf_age_1 = {_T_2436,_T_2432,_T_2428,_T_2424}; // @[Cat.scala 29:58] + wire _T_2525 = ~buf_age_1[3]; // @[el2_lsu_bus_buffer.scala 429:91] + wire _T_2527 = _T_2525 & _T_26; // @[el2_lsu_bus_buffer.scala 429:106] + wire _T_2519 = ~buf_age_1[2]; // @[el2_lsu_bus_buffer.scala 429:91] + wire _T_2521 = _T_2519 & _T_19; // @[el2_lsu_bus_buffer.scala 429:106] + wire _T_2507 = ~buf_age_1[0]; // @[el2_lsu_bus_buffer.scala 429:91] + wire _T_2509 = _T_2507 & _T_5; // @[el2_lsu_bus_buffer.scala 429:106] + wire [3:0] buf_age_younger_1 = {_T_2527,_T_2521,1'h0,_T_2509}; // @[Cat.scala 29:58] + wire [3:0] _T_239 = ld_byte_hitvec_lo_0 & buf_age_younger_1; // @[el2_lsu_bus_buffer.scala 196:122] + wire _T_240 = |_T_239; // @[el2_lsu_bus_buffer.scala 196:144] + wire _T_241 = ~_T_240; // @[el2_lsu_bus_buffer.scala 196:99] + wire _T_242 = ld_byte_hitvec_lo_0[1] & _T_241; // @[el2_lsu_bus_buffer.scala 196:97] + wire _T_245 = _T_242 & _T_260; // @[el2_lsu_bus_buffer.scala 196:148] + reg [3:0] buf_ageQ_0; // @[el2_lsu_bus_buffer.scala 515:60] + wire _T_2417 = buf_ageQ_0[3] & _T_2473; // @[el2_lsu_bus_buffer.scala 428:78] + wire _T_2413 = buf_ageQ_0[2] & _T_2469; // @[el2_lsu_bus_buffer.scala 428:78] + wire _T_2409 = buf_ageQ_0[1] & _T_2465; // @[el2_lsu_bus_buffer.scala 428:78] + wire _T_2405 = buf_ageQ_0[0] & _T_2461; // @[el2_lsu_bus_buffer.scala 428:78] + wire [3:0] buf_age_0 = {_T_2417,_T_2413,_T_2409,_T_2405}; // @[Cat.scala 29:58] + wire _T_2498 = ~buf_age_0[3]; // @[el2_lsu_bus_buffer.scala 429:91] + wire _T_2500 = _T_2498 & _T_26; // @[el2_lsu_bus_buffer.scala 429:106] + wire _T_2492 = ~buf_age_0[2]; // @[el2_lsu_bus_buffer.scala 429:91] + wire _T_2494 = _T_2492 & _T_19; // @[el2_lsu_bus_buffer.scala 429:106] + wire _T_2486 = ~buf_age_0[1]; // @[el2_lsu_bus_buffer.scala 429:91] + wire _T_2488 = _T_2486 & _T_12; // @[el2_lsu_bus_buffer.scala 429:106] + wire [3:0] buf_age_younger_0 = {_T_2500,_T_2494,_T_2488,1'h0}; // @[Cat.scala 29:58] + wire [3:0] _T_231 = ld_byte_hitvec_lo_0 & buf_age_younger_0; // @[el2_lsu_bus_buffer.scala 196:122] + wire _T_232 = |_T_231; // @[el2_lsu_bus_buffer.scala 196:144] + wire _T_233 = ~_T_232; // @[el2_lsu_bus_buffer.scala 196:99] + wire _T_234 = ld_byte_hitvec_lo_0[0] & _T_233; // @[el2_lsu_bus_buffer.scala 196:97] + wire _T_237 = _T_234 & _T_260; // @[el2_lsu_bus_buffer.scala 196:148] + wire [3:0] ld_byte_hitvecfn_lo_0 = {_T_261,_T_253,_T_245,_T_237}; // @[Cat.scala 29:58] + wire _T_56 = |ld_byte_hitvecfn_lo_0; // @[el2_lsu_bus_buffer.scala 188:73] + wire _T_58 = _T_56 | ld_byte_ibuf_hit_lo[0]; // @[el2_lsu_bus_buffer.scala 188:77] + wire _T_117 = ld_addr_hitvec_lo_3 & buf_byteen_3[1]; // @[el2_lsu_bus_buffer.scala 191:95] + wire _T_119 = _T_117 & ldst_byteen_lo_m[1]; // @[el2_lsu_bus_buffer.scala 191:114] + wire _T_113 = ld_addr_hitvec_lo_2 & buf_byteen_2[1]; // @[el2_lsu_bus_buffer.scala 191:95] + wire _T_115 = _T_113 & ldst_byteen_lo_m[1]; // @[el2_lsu_bus_buffer.scala 191:114] + wire _T_109 = ld_addr_hitvec_lo_1 & buf_byteen_1[1]; // @[el2_lsu_bus_buffer.scala 191:95] + wire _T_111 = _T_109 & ldst_byteen_lo_m[1]; // @[el2_lsu_bus_buffer.scala 191:114] + wire _T_105 = ld_addr_hitvec_lo_0 & buf_byteen_0[1]; // @[el2_lsu_bus_buffer.scala 191:95] + wire _T_107 = _T_105 & ldst_byteen_lo_m[1]; // @[el2_lsu_bus_buffer.scala 191:114] + wire [3:0] ld_byte_hitvec_lo_1 = {_T_119,_T_115,_T_111,_T_107}; // @[Cat.scala 29:58] + wire [3:0] _T_290 = ld_byte_hitvec_lo_1 & buf_age_younger_3; // @[el2_lsu_bus_buffer.scala 196:122] + wire _T_291 = |_T_290; // @[el2_lsu_bus_buffer.scala 196:144] + wire _T_292 = ~_T_291; // @[el2_lsu_bus_buffer.scala 196:99] + wire _T_293 = ld_byte_hitvec_lo_1[3] & _T_292; // @[el2_lsu_bus_buffer.scala 196:97] + wire _T_295 = ~ld_byte_ibuf_hit_lo[1]; // @[el2_lsu_bus_buffer.scala 196:150] + wire _T_296 = _T_293 & _T_295; // @[el2_lsu_bus_buffer.scala 196:148] + wire [3:0] _T_282 = ld_byte_hitvec_lo_1 & buf_age_younger_2; // @[el2_lsu_bus_buffer.scala 196:122] + wire _T_283 = |_T_282; // @[el2_lsu_bus_buffer.scala 196:144] + wire _T_284 = ~_T_283; // @[el2_lsu_bus_buffer.scala 196:99] + wire _T_285 = ld_byte_hitvec_lo_1[2] & _T_284; // @[el2_lsu_bus_buffer.scala 196:97] + wire _T_288 = _T_285 & _T_295; // @[el2_lsu_bus_buffer.scala 196:148] + wire [3:0] _T_274 = ld_byte_hitvec_lo_1 & buf_age_younger_1; // @[el2_lsu_bus_buffer.scala 196:122] + wire _T_275 = |_T_274; // @[el2_lsu_bus_buffer.scala 196:144] + wire _T_276 = ~_T_275; // @[el2_lsu_bus_buffer.scala 196:99] + wire _T_277 = ld_byte_hitvec_lo_1[1] & _T_276; // @[el2_lsu_bus_buffer.scala 196:97] + wire _T_280 = _T_277 & _T_295; // @[el2_lsu_bus_buffer.scala 196:148] + wire [3:0] _T_266 = ld_byte_hitvec_lo_1 & buf_age_younger_0; // @[el2_lsu_bus_buffer.scala 196:122] + wire _T_267 = |_T_266; // @[el2_lsu_bus_buffer.scala 196:144] + wire _T_268 = ~_T_267; // @[el2_lsu_bus_buffer.scala 196:99] + wire _T_269 = ld_byte_hitvec_lo_1[0] & _T_268; // @[el2_lsu_bus_buffer.scala 196:97] + wire _T_272 = _T_269 & _T_295; // @[el2_lsu_bus_buffer.scala 196:148] + wire [3:0] ld_byte_hitvecfn_lo_1 = {_T_296,_T_288,_T_280,_T_272}; // @[Cat.scala 29:58] + wire _T_59 = |ld_byte_hitvecfn_lo_1; // @[el2_lsu_bus_buffer.scala 188:73] + wire _T_61 = _T_59 | ld_byte_ibuf_hit_lo[1]; // @[el2_lsu_bus_buffer.scala 188:77] + wire _T_135 = ld_addr_hitvec_lo_3 & buf_byteen_3[2]; // @[el2_lsu_bus_buffer.scala 191:95] + wire _T_137 = _T_135 & ldst_byteen_lo_m[2]; // @[el2_lsu_bus_buffer.scala 191:114] + wire _T_131 = ld_addr_hitvec_lo_2 & buf_byteen_2[2]; // @[el2_lsu_bus_buffer.scala 191:95] + wire _T_133 = _T_131 & ldst_byteen_lo_m[2]; // @[el2_lsu_bus_buffer.scala 191:114] + wire _T_127 = ld_addr_hitvec_lo_1 & buf_byteen_1[2]; // @[el2_lsu_bus_buffer.scala 191:95] + wire _T_129 = _T_127 & ldst_byteen_lo_m[2]; // @[el2_lsu_bus_buffer.scala 191:114] + wire _T_123 = ld_addr_hitvec_lo_0 & buf_byteen_0[2]; // @[el2_lsu_bus_buffer.scala 191:95] + wire _T_125 = _T_123 & ldst_byteen_lo_m[2]; // @[el2_lsu_bus_buffer.scala 191:114] + wire [3:0] ld_byte_hitvec_lo_2 = {_T_137,_T_133,_T_129,_T_125}; // @[Cat.scala 29:58] + wire [3:0] _T_325 = ld_byte_hitvec_lo_2 & buf_age_younger_3; // @[el2_lsu_bus_buffer.scala 196:122] + wire _T_326 = |_T_325; // @[el2_lsu_bus_buffer.scala 196:144] + wire _T_327 = ~_T_326; // @[el2_lsu_bus_buffer.scala 196:99] + wire _T_328 = ld_byte_hitvec_lo_2[3] & _T_327; // @[el2_lsu_bus_buffer.scala 196:97] + wire _T_330 = ~ld_byte_ibuf_hit_lo[2]; // @[el2_lsu_bus_buffer.scala 196:150] + wire _T_331 = _T_328 & _T_330; // @[el2_lsu_bus_buffer.scala 196:148] + wire [3:0] _T_317 = ld_byte_hitvec_lo_2 & buf_age_younger_2; // @[el2_lsu_bus_buffer.scala 196:122] + wire _T_318 = |_T_317; // @[el2_lsu_bus_buffer.scala 196:144] + wire _T_319 = ~_T_318; // @[el2_lsu_bus_buffer.scala 196:99] + wire _T_320 = ld_byte_hitvec_lo_2[2] & _T_319; // @[el2_lsu_bus_buffer.scala 196:97] + wire _T_323 = _T_320 & _T_330; // @[el2_lsu_bus_buffer.scala 196:148] + wire [3:0] _T_309 = ld_byte_hitvec_lo_2 & buf_age_younger_1; // @[el2_lsu_bus_buffer.scala 196:122] + wire _T_310 = |_T_309; // @[el2_lsu_bus_buffer.scala 196:144] + wire _T_311 = ~_T_310; // @[el2_lsu_bus_buffer.scala 196:99] + wire _T_312 = ld_byte_hitvec_lo_2[1] & _T_311; // @[el2_lsu_bus_buffer.scala 196:97] + wire _T_315 = _T_312 & _T_330; // @[el2_lsu_bus_buffer.scala 196:148] + wire [3:0] _T_301 = ld_byte_hitvec_lo_2 & buf_age_younger_0; // @[el2_lsu_bus_buffer.scala 196:122] + wire _T_302 = |_T_301; // @[el2_lsu_bus_buffer.scala 196:144] + wire _T_303 = ~_T_302; // @[el2_lsu_bus_buffer.scala 196:99] + wire _T_304 = ld_byte_hitvec_lo_2[0] & _T_303; // @[el2_lsu_bus_buffer.scala 196:97] + wire _T_307 = _T_304 & _T_330; // @[el2_lsu_bus_buffer.scala 196:148] + wire [3:0] ld_byte_hitvecfn_lo_2 = {_T_331,_T_323,_T_315,_T_307}; // @[Cat.scala 29:58] + wire _T_62 = |ld_byte_hitvecfn_lo_2; // @[el2_lsu_bus_buffer.scala 188:73] + wire _T_64 = _T_62 | ld_byte_ibuf_hit_lo[2]; // @[el2_lsu_bus_buffer.scala 188:77] + wire _T_153 = ld_addr_hitvec_lo_3 & buf_byteen_3[3]; // @[el2_lsu_bus_buffer.scala 191:95] + wire _T_155 = _T_153 & ldst_byteen_lo_m[3]; // @[el2_lsu_bus_buffer.scala 191:114] + wire _T_149 = ld_addr_hitvec_lo_2 & buf_byteen_2[3]; // @[el2_lsu_bus_buffer.scala 191:95] + wire _T_151 = _T_149 & ldst_byteen_lo_m[3]; // @[el2_lsu_bus_buffer.scala 191:114] + wire _T_145 = ld_addr_hitvec_lo_1 & buf_byteen_1[3]; // @[el2_lsu_bus_buffer.scala 191:95] + wire _T_147 = _T_145 & ldst_byteen_lo_m[3]; // @[el2_lsu_bus_buffer.scala 191:114] + wire _T_141 = ld_addr_hitvec_lo_0 & buf_byteen_0[3]; // @[el2_lsu_bus_buffer.scala 191:95] + wire _T_143 = _T_141 & ldst_byteen_lo_m[3]; // @[el2_lsu_bus_buffer.scala 191:114] + wire [3:0] ld_byte_hitvec_lo_3 = {_T_155,_T_151,_T_147,_T_143}; // @[Cat.scala 29:58] + wire [3:0] _T_360 = ld_byte_hitvec_lo_3 & buf_age_younger_3; // @[el2_lsu_bus_buffer.scala 196:122] + wire _T_361 = |_T_360; // @[el2_lsu_bus_buffer.scala 196:144] + wire _T_362 = ~_T_361; // @[el2_lsu_bus_buffer.scala 196:99] + wire _T_363 = ld_byte_hitvec_lo_3[3] & _T_362; // @[el2_lsu_bus_buffer.scala 196:97] + wire _T_365 = ~ld_byte_ibuf_hit_lo[3]; // @[el2_lsu_bus_buffer.scala 196:150] + wire _T_366 = _T_363 & _T_365; // @[el2_lsu_bus_buffer.scala 196:148] + wire [3:0] _T_352 = ld_byte_hitvec_lo_3 & buf_age_younger_2; // @[el2_lsu_bus_buffer.scala 196:122] + wire _T_353 = |_T_352; // @[el2_lsu_bus_buffer.scala 196:144] + wire _T_354 = ~_T_353; // @[el2_lsu_bus_buffer.scala 196:99] + wire _T_355 = ld_byte_hitvec_lo_3[2] & _T_354; // @[el2_lsu_bus_buffer.scala 196:97] + wire _T_358 = _T_355 & _T_365; // @[el2_lsu_bus_buffer.scala 196:148] + wire [3:0] _T_344 = ld_byte_hitvec_lo_3 & buf_age_younger_1; // @[el2_lsu_bus_buffer.scala 196:122] + wire _T_345 = |_T_344; // @[el2_lsu_bus_buffer.scala 196:144] + wire _T_346 = ~_T_345; // @[el2_lsu_bus_buffer.scala 196:99] + wire _T_347 = ld_byte_hitvec_lo_3[1] & _T_346; // @[el2_lsu_bus_buffer.scala 196:97] + wire _T_350 = _T_347 & _T_365; // @[el2_lsu_bus_buffer.scala 196:148] + wire [3:0] _T_336 = ld_byte_hitvec_lo_3 & buf_age_younger_0; // @[el2_lsu_bus_buffer.scala 196:122] + wire _T_337 = |_T_336; // @[el2_lsu_bus_buffer.scala 196:144] + wire _T_338 = ~_T_337; // @[el2_lsu_bus_buffer.scala 196:99] + wire _T_339 = ld_byte_hitvec_lo_3[0] & _T_338; // @[el2_lsu_bus_buffer.scala 196:97] + wire _T_342 = _T_339 & _T_365; // @[el2_lsu_bus_buffer.scala 196:148] + wire [3:0] ld_byte_hitvecfn_lo_3 = {_T_366,_T_358,_T_350,_T_342}; // @[Cat.scala 29:58] + wire _T_65 = |ld_byte_hitvecfn_lo_3; // @[el2_lsu_bus_buffer.scala 188:73] + wire _T_67 = _T_65 | ld_byte_ibuf_hit_lo[3]; // @[el2_lsu_bus_buffer.scala 188:77] + wire [2:0] _T_69 = {_T_67,_T_64,_T_61}; // @[Cat.scala 29:58] + wire _T_171 = ld_addr_hitvec_hi_3 & buf_byteen_3[0]; // @[el2_lsu_bus_buffer.scala 192:95] + wire _T_173 = _T_171 & ldst_byteen_hi_m[0]; // @[el2_lsu_bus_buffer.scala 192:114] + wire _T_167 = ld_addr_hitvec_hi_2 & buf_byteen_2[0]; // @[el2_lsu_bus_buffer.scala 192:95] + wire _T_169 = _T_167 & ldst_byteen_hi_m[0]; // @[el2_lsu_bus_buffer.scala 192:114] + wire _T_163 = ld_addr_hitvec_hi_1 & buf_byteen_1[0]; // @[el2_lsu_bus_buffer.scala 192:95] + wire _T_165 = _T_163 & ldst_byteen_hi_m[0]; // @[el2_lsu_bus_buffer.scala 192:114] + wire _T_159 = ld_addr_hitvec_hi_0 & buf_byteen_0[0]; // @[el2_lsu_bus_buffer.scala 192:95] + wire _T_161 = _T_159 & ldst_byteen_hi_m[0]; // @[el2_lsu_bus_buffer.scala 192:114] + wire [3:0] ld_byte_hitvec_hi_0 = {_T_173,_T_169,_T_165,_T_161}; // @[Cat.scala 29:58] + wire [3:0] _T_395 = ld_byte_hitvec_hi_0 & buf_age_younger_3; // @[el2_lsu_bus_buffer.scala 197:122] + wire _T_396 = |_T_395; // @[el2_lsu_bus_buffer.scala 197:144] + wire _T_397 = ~_T_396; // @[el2_lsu_bus_buffer.scala 197:99] + wire _T_398 = ld_byte_hitvec_hi_0[3] & _T_397; // @[el2_lsu_bus_buffer.scala 197:97] + wire _T_517 = io_end_addr_m[31:2] == ibuf_addr[31:2]; // @[el2_lsu_bus_buffer.scala 203:51] + wire _T_518 = _T_517 & ibuf_write; // @[el2_lsu_bus_buffer.scala 203:73] + wire _T_519 = _T_518 & ibuf_valid; // @[el2_lsu_bus_buffer.scala 203:86] + wire ld_addr_ibuf_hit_hi = _T_519 & io_lsu_busreq_m; // @[el2_lsu_bus_buffer.scala 203:99] + wire _T_549 = ld_addr_ibuf_hit_hi & ibuf_byteen[3]; // @[el2_lsu_bus_buffer.scala 208:48] + wire _T_551 = _T_549 & ldst_byteen_hi_m[3]; // @[el2_lsu_bus_buffer.scala 208:65] + wire [3:0] ld_byte_ibuf_hit_hi = {{3'd0}, _T_551}; // @[el2_lsu_bus_buffer.scala 208:25 el2_lsu_bus_buffer.scala 208:25 el2_lsu_bus_buffer.scala 208:25 el2_lsu_bus_buffer.scala 208:25] + wire _T_400 = ~ld_byte_ibuf_hit_hi[0]; // @[el2_lsu_bus_buffer.scala 197:150] + wire _T_401 = _T_398 & _T_400; // @[el2_lsu_bus_buffer.scala 197:148] + wire [3:0] _T_387 = ld_byte_hitvec_hi_0 & buf_age_younger_2; // @[el2_lsu_bus_buffer.scala 197:122] + wire _T_388 = |_T_387; // @[el2_lsu_bus_buffer.scala 197:144] + wire _T_389 = ~_T_388; // @[el2_lsu_bus_buffer.scala 197:99] + wire _T_390 = ld_byte_hitvec_hi_0[2] & _T_389; // @[el2_lsu_bus_buffer.scala 197:97] + wire _T_393 = _T_390 & _T_400; // @[el2_lsu_bus_buffer.scala 197:148] + wire [3:0] _T_379 = ld_byte_hitvec_hi_0 & buf_age_younger_1; // @[el2_lsu_bus_buffer.scala 197:122] + wire _T_380 = |_T_379; // @[el2_lsu_bus_buffer.scala 197:144] + wire _T_381 = ~_T_380; // @[el2_lsu_bus_buffer.scala 197:99] + wire _T_382 = ld_byte_hitvec_hi_0[1] & _T_381; // @[el2_lsu_bus_buffer.scala 197:97] + wire _T_385 = _T_382 & _T_400; // @[el2_lsu_bus_buffer.scala 197:148] + wire [3:0] _T_371 = ld_byte_hitvec_hi_0 & buf_age_younger_0; // @[el2_lsu_bus_buffer.scala 197:122] + wire _T_372 = |_T_371; // @[el2_lsu_bus_buffer.scala 197:144] + wire _T_373 = ~_T_372; // @[el2_lsu_bus_buffer.scala 197:99] + wire _T_374 = ld_byte_hitvec_hi_0[0] & _T_373; // @[el2_lsu_bus_buffer.scala 197:97] + wire _T_377 = _T_374 & _T_400; // @[el2_lsu_bus_buffer.scala 197:148] + wire [3:0] ld_byte_hitvecfn_hi_0 = {_T_401,_T_393,_T_385,_T_377}; // @[Cat.scala 29:58] + wire _T_71 = |ld_byte_hitvecfn_hi_0; // @[el2_lsu_bus_buffer.scala 189:73] + wire _T_73 = _T_71 | ld_byte_ibuf_hit_hi[0]; // @[el2_lsu_bus_buffer.scala 189:77] + wire _T_189 = ld_addr_hitvec_hi_3 & buf_byteen_3[1]; // @[el2_lsu_bus_buffer.scala 192:95] + wire _T_191 = _T_189 & ldst_byteen_hi_m[1]; // @[el2_lsu_bus_buffer.scala 192:114] + wire _T_185 = ld_addr_hitvec_hi_2 & buf_byteen_2[1]; // @[el2_lsu_bus_buffer.scala 192:95] + wire _T_187 = _T_185 & ldst_byteen_hi_m[1]; // @[el2_lsu_bus_buffer.scala 192:114] + wire _T_181 = ld_addr_hitvec_hi_1 & buf_byteen_1[1]; // @[el2_lsu_bus_buffer.scala 192:95] + wire _T_183 = _T_181 & ldst_byteen_hi_m[1]; // @[el2_lsu_bus_buffer.scala 192:114] + wire _T_177 = ld_addr_hitvec_hi_0 & buf_byteen_0[1]; // @[el2_lsu_bus_buffer.scala 192:95] + wire _T_179 = _T_177 & ldst_byteen_hi_m[1]; // @[el2_lsu_bus_buffer.scala 192:114] + wire [3:0] ld_byte_hitvec_hi_1 = {_T_191,_T_187,_T_183,_T_179}; // @[Cat.scala 29:58] + wire [3:0] _T_430 = ld_byte_hitvec_hi_1 & buf_age_younger_3; // @[el2_lsu_bus_buffer.scala 197:122] + wire _T_431 = |_T_430; // @[el2_lsu_bus_buffer.scala 197:144] + wire _T_432 = ~_T_431; // @[el2_lsu_bus_buffer.scala 197:99] + wire _T_433 = ld_byte_hitvec_hi_1[3] & _T_432; // @[el2_lsu_bus_buffer.scala 197:97] + wire _T_435 = ~ld_byte_ibuf_hit_hi[1]; // @[el2_lsu_bus_buffer.scala 197:150] + wire _T_436 = _T_433 & _T_435; // @[el2_lsu_bus_buffer.scala 197:148] + wire [3:0] _T_422 = ld_byte_hitvec_hi_1 & buf_age_younger_2; // @[el2_lsu_bus_buffer.scala 197:122] + wire _T_423 = |_T_422; // @[el2_lsu_bus_buffer.scala 197:144] + wire _T_424 = ~_T_423; // @[el2_lsu_bus_buffer.scala 197:99] + wire _T_425 = ld_byte_hitvec_hi_1[2] & _T_424; // @[el2_lsu_bus_buffer.scala 197:97] + wire _T_428 = _T_425 & _T_435; // @[el2_lsu_bus_buffer.scala 197:148] + wire [3:0] _T_414 = ld_byte_hitvec_hi_1 & buf_age_younger_1; // @[el2_lsu_bus_buffer.scala 197:122] + wire _T_415 = |_T_414; // @[el2_lsu_bus_buffer.scala 197:144] + wire _T_416 = ~_T_415; // @[el2_lsu_bus_buffer.scala 197:99] + wire _T_417 = ld_byte_hitvec_hi_1[1] & _T_416; // @[el2_lsu_bus_buffer.scala 197:97] + wire _T_420 = _T_417 & _T_435; // @[el2_lsu_bus_buffer.scala 197:148] + wire [3:0] _T_406 = ld_byte_hitvec_hi_1 & buf_age_younger_0; // @[el2_lsu_bus_buffer.scala 197:122] + wire _T_407 = |_T_406; // @[el2_lsu_bus_buffer.scala 197:144] + wire _T_408 = ~_T_407; // @[el2_lsu_bus_buffer.scala 197:99] + wire _T_409 = ld_byte_hitvec_hi_1[0] & _T_408; // @[el2_lsu_bus_buffer.scala 197:97] + wire _T_412 = _T_409 & _T_435; // @[el2_lsu_bus_buffer.scala 197:148] + wire [3:0] ld_byte_hitvecfn_hi_1 = {_T_436,_T_428,_T_420,_T_412}; // @[Cat.scala 29:58] + wire _T_74 = |ld_byte_hitvecfn_hi_1; // @[el2_lsu_bus_buffer.scala 189:73] + wire _T_76 = _T_74 | ld_byte_ibuf_hit_hi[1]; // @[el2_lsu_bus_buffer.scala 189:77] + wire _T_207 = ld_addr_hitvec_hi_3 & buf_byteen_3[2]; // @[el2_lsu_bus_buffer.scala 192:95] + wire _T_209 = _T_207 & ldst_byteen_hi_m[2]; // @[el2_lsu_bus_buffer.scala 192:114] + wire _T_203 = ld_addr_hitvec_hi_2 & buf_byteen_2[2]; // @[el2_lsu_bus_buffer.scala 192:95] + wire _T_205 = _T_203 & ldst_byteen_hi_m[2]; // @[el2_lsu_bus_buffer.scala 192:114] + wire _T_199 = ld_addr_hitvec_hi_1 & buf_byteen_1[2]; // @[el2_lsu_bus_buffer.scala 192:95] + wire _T_201 = _T_199 & ldst_byteen_hi_m[2]; // @[el2_lsu_bus_buffer.scala 192:114] + wire _T_195 = ld_addr_hitvec_hi_0 & buf_byteen_0[2]; // @[el2_lsu_bus_buffer.scala 192:95] + wire _T_197 = _T_195 & ldst_byteen_hi_m[2]; // @[el2_lsu_bus_buffer.scala 192:114] + wire [3:0] ld_byte_hitvec_hi_2 = {_T_209,_T_205,_T_201,_T_197}; // @[Cat.scala 29:58] + wire [3:0] _T_465 = ld_byte_hitvec_hi_2 & buf_age_younger_3; // @[el2_lsu_bus_buffer.scala 197:122] + wire _T_466 = |_T_465; // @[el2_lsu_bus_buffer.scala 197:144] + wire _T_467 = ~_T_466; // @[el2_lsu_bus_buffer.scala 197:99] + wire _T_468 = ld_byte_hitvec_hi_2[3] & _T_467; // @[el2_lsu_bus_buffer.scala 197:97] + wire _T_470 = ~ld_byte_ibuf_hit_hi[2]; // @[el2_lsu_bus_buffer.scala 197:150] + wire _T_471 = _T_468 & _T_470; // @[el2_lsu_bus_buffer.scala 197:148] + wire [3:0] _T_457 = ld_byte_hitvec_hi_2 & buf_age_younger_2; // @[el2_lsu_bus_buffer.scala 197:122] + wire _T_458 = |_T_457; // @[el2_lsu_bus_buffer.scala 197:144] + wire _T_459 = ~_T_458; // @[el2_lsu_bus_buffer.scala 197:99] + wire _T_460 = ld_byte_hitvec_hi_2[2] & _T_459; // @[el2_lsu_bus_buffer.scala 197:97] + wire _T_463 = _T_460 & _T_470; // @[el2_lsu_bus_buffer.scala 197:148] + wire [3:0] _T_449 = ld_byte_hitvec_hi_2 & buf_age_younger_1; // @[el2_lsu_bus_buffer.scala 197:122] + wire _T_450 = |_T_449; // @[el2_lsu_bus_buffer.scala 197:144] + wire _T_451 = ~_T_450; // @[el2_lsu_bus_buffer.scala 197:99] + wire _T_452 = ld_byte_hitvec_hi_2[1] & _T_451; // @[el2_lsu_bus_buffer.scala 197:97] + wire _T_455 = _T_452 & _T_470; // @[el2_lsu_bus_buffer.scala 197:148] + wire [3:0] _T_441 = ld_byte_hitvec_hi_2 & buf_age_younger_0; // @[el2_lsu_bus_buffer.scala 197:122] + wire _T_442 = |_T_441; // @[el2_lsu_bus_buffer.scala 197:144] + wire _T_443 = ~_T_442; // @[el2_lsu_bus_buffer.scala 197:99] + wire _T_444 = ld_byte_hitvec_hi_2[0] & _T_443; // @[el2_lsu_bus_buffer.scala 197:97] + wire _T_447 = _T_444 & _T_470; // @[el2_lsu_bus_buffer.scala 197:148] + wire [3:0] ld_byte_hitvecfn_hi_2 = {_T_471,_T_463,_T_455,_T_447}; // @[Cat.scala 29:58] + wire _T_77 = |ld_byte_hitvecfn_hi_2; // @[el2_lsu_bus_buffer.scala 189:73] + wire _T_79 = _T_77 | ld_byte_ibuf_hit_hi[2]; // @[el2_lsu_bus_buffer.scala 189:77] + wire _T_225 = ld_addr_hitvec_hi_3 & buf_byteen_3[3]; // @[el2_lsu_bus_buffer.scala 192:95] + wire _T_227 = _T_225 & ldst_byteen_hi_m[3]; // @[el2_lsu_bus_buffer.scala 192:114] + wire _T_221 = ld_addr_hitvec_hi_2 & buf_byteen_2[3]; // @[el2_lsu_bus_buffer.scala 192:95] + wire _T_223 = _T_221 & ldst_byteen_hi_m[3]; // @[el2_lsu_bus_buffer.scala 192:114] + wire _T_217 = ld_addr_hitvec_hi_1 & buf_byteen_1[3]; // @[el2_lsu_bus_buffer.scala 192:95] + wire _T_219 = _T_217 & ldst_byteen_hi_m[3]; // @[el2_lsu_bus_buffer.scala 192:114] + wire _T_213 = ld_addr_hitvec_hi_0 & buf_byteen_0[3]; // @[el2_lsu_bus_buffer.scala 192:95] + wire _T_215 = _T_213 & ldst_byteen_hi_m[3]; // @[el2_lsu_bus_buffer.scala 192:114] + wire [3:0] ld_byte_hitvec_hi_3 = {_T_227,_T_223,_T_219,_T_215}; // @[Cat.scala 29:58] + wire [3:0] _T_500 = ld_byte_hitvec_hi_3 & buf_age_younger_3; // @[el2_lsu_bus_buffer.scala 197:122] + wire _T_501 = |_T_500; // @[el2_lsu_bus_buffer.scala 197:144] + wire _T_502 = ~_T_501; // @[el2_lsu_bus_buffer.scala 197:99] + wire _T_503 = ld_byte_hitvec_hi_3[3] & _T_502; // @[el2_lsu_bus_buffer.scala 197:97] + wire _T_505 = ~ld_byte_ibuf_hit_hi[3]; // @[el2_lsu_bus_buffer.scala 197:150] + wire _T_506 = _T_503 & _T_505; // @[el2_lsu_bus_buffer.scala 197:148] + wire [3:0] _T_492 = ld_byte_hitvec_hi_3 & buf_age_younger_2; // @[el2_lsu_bus_buffer.scala 197:122] + wire _T_493 = |_T_492; // @[el2_lsu_bus_buffer.scala 197:144] + wire _T_494 = ~_T_493; // @[el2_lsu_bus_buffer.scala 197:99] + wire _T_495 = ld_byte_hitvec_hi_3[2] & _T_494; // @[el2_lsu_bus_buffer.scala 197:97] + wire _T_498 = _T_495 & _T_505; // @[el2_lsu_bus_buffer.scala 197:148] + wire [3:0] _T_484 = ld_byte_hitvec_hi_3 & buf_age_younger_1; // @[el2_lsu_bus_buffer.scala 197:122] + wire _T_485 = |_T_484; // @[el2_lsu_bus_buffer.scala 197:144] + wire _T_486 = ~_T_485; // @[el2_lsu_bus_buffer.scala 197:99] + wire _T_487 = ld_byte_hitvec_hi_3[1] & _T_486; // @[el2_lsu_bus_buffer.scala 197:97] + wire _T_490 = _T_487 & _T_505; // @[el2_lsu_bus_buffer.scala 197:148] + wire [3:0] _T_476 = ld_byte_hitvec_hi_3 & buf_age_younger_0; // @[el2_lsu_bus_buffer.scala 197:122] + wire _T_477 = |_T_476; // @[el2_lsu_bus_buffer.scala 197:144] + wire _T_478 = ~_T_477; // @[el2_lsu_bus_buffer.scala 197:99] + wire _T_479 = ld_byte_hitvec_hi_3[0] & _T_478; // @[el2_lsu_bus_buffer.scala 197:97] + wire _T_482 = _T_479 & _T_505; // @[el2_lsu_bus_buffer.scala 197:148] + wire [3:0] ld_byte_hitvecfn_hi_3 = {_T_506,_T_498,_T_490,_T_482}; // @[Cat.scala 29:58] + wire _T_80 = |ld_byte_hitvecfn_hi_3; // @[el2_lsu_bus_buffer.scala 189:73] + wire _T_82 = _T_80 | ld_byte_ibuf_hit_hi[3]; // @[el2_lsu_bus_buffer.scala 189:77] + wire [2:0] _T_84 = {_T_82,_T_79,_T_76}; // @[Cat.scala 29:58] + wire [7:0] _T_554 = ld_byte_hitvecfn_lo_3[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + reg [3:0] _T_4238; // @[el2_lib.scala 478:16] + wire [31:0] buf_data_0 = {{28'd0}, _T_4238}; // @[el2_lsu_bus_buffer.scala 210:22 el2_lsu_bus_buffer.scala 211:12 el2_lsu_bus_buffer.scala 532:14] + wire [8:0] _GEN_354 = {{1'd0}, _T_554}; // @[el2_lsu_bus_buffer.scala 214:91] + wire [8:0] _T_556 = _GEN_354 & buf_data_0[31:23]; // @[el2_lsu_bus_buffer.scala 214:91] + wire [7:0] _T_559 = ld_byte_hitvecfn_lo_3[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + reg [3:0] _T_4239; // @[el2_lib.scala 478:16] + wire [31:0] buf_data_1 = {{28'd0}, _T_4239}; // @[el2_lsu_bus_buffer.scala 210:22 el2_lsu_bus_buffer.scala 211:12 el2_lsu_bus_buffer.scala 532:14] + wire [8:0] _GEN_355 = {{1'd0}, _T_559}; // @[el2_lsu_bus_buffer.scala 214:91] + wire [8:0] _T_561 = _GEN_355 & buf_data_1[31:23]; // @[el2_lsu_bus_buffer.scala 214:91] + wire [7:0] _T_564 = ld_byte_hitvecfn_lo_3[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + reg [3:0] _T_4240; // @[el2_lib.scala 478:16] + wire [31:0] buf_data_2 = {{28'd0}, _T_4240}; // @[el2_lsu_bus_buffer.scala 210:22 el2_lsu_bus_buffer.scala 211:12 el2_lsu_bus_buffer.scala 532:14] + wire [8:0] _GEN_356 = {{1'd0}, _T_564}; // @[el2_lsu_bus_buffer.scala 214:91] + wire [8:0] _T_566 = _GEN_356 & buf_data_2[31:23]; // @[el2_lsu_bus_buffer.scala 214:91] + wire [7:0] _T_569 = ld_byte_hitvecfn_lo_3[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + reg [3:0] _T_4241; // @[el2_lib.scala 478:16] + wire [31:0] buf_data_3 = {{28'd0}, _T_4241}; // @[el2_lsu_bus_buffer.scala 210:22 el2_lsu_bus_buffer.scala 211:12 el2_lsu_bus_buffer.scala 532:14] + wire [8:0] _GEN_357 = {{1'd0}, _T_569}; // @[el2_lsu_bus_buffer.scala 214:91] + wire [8:0] _T_571 = _GEN_357 & buf_data_3[31:23]; // @[el2_lsu_bus_buffer.scala 214:91] + wire [8:0] _T_572 = _T_556 | _T_561; // @[el2_lsu_bus_buffer.scala 214:123] + wire [8:0] _T_573 = _T_572 | _T_566; // @[el2_lsu_bus_buffer.scala 214:123] + wire [8:0] _T_574 = _T_573 | _T_571; // @[el2_lsu_bus_buffer.scala 214:123] + wire [7:0] _T_577 = ld_byte_hitvecfn_lo_2[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_579 = _T_577 & buf_data_0[23:16]; // @[el2_lsu_bus_buffer.scala 215:65] + wire [7:0] _T_582 = ld_byte_hitvecfn_lo_2[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_584 = _T_582 & buf_data_1[23:16]; // @[el2_lsu_bus_buffer.scala 215:65] + wire [7:0] _T_587 = ld_byte_hitvecfn_lo_2[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_589 = _T_587 & buf_data_2[23:16]; // @[el2_lsu_bus_buffer.scala 215:65] + wire [7:0] _T_592 = ld_byte_hitvecfn_lo_2[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_594 = _T_592 & buf_data_3[23:16]; // @[el2_lsu_bus_buffer.scala 215:65] + wire [7:0] _T_595 = _T_579 | _T_584; // @[el2_lsu_bus_buffer.scala 215:97] + wire [7:0] _T_596 = _T_595 | _T_589; // @[el2_lsu_bus_buffer.scala 215:97] + wire [7:0] _T_597 = _T_596 | _T_594; // @[el2_lsu_bus_buffer.scala 215:97] + wire [7:0] _T_600 = ld_byte_hitvecfn_lo_1[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_602 = _T_600 & buf_data_0[15:8]; // @[el2_lsu_bus_buffer.scala 216:65] + wire [7:0] _T_605 = ld_byte_hitvecfn_lo_1[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_607 = _T_605 & buf_data_1[15:8]; // @[el2_lsu_bus_buffer.scala 216:65] + wire [7:0] _T_610 = ld_byte_hitvecfn_lo_1[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_612 = _T_610 & buf_data_2[15:8]; // @[el2_lsu_bus_buffer.scala 216:65] + wire [7:0] _T_615 = ld_byte_hitvecfn_lo_1[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_617 = _T_615 & buf_data_3[15:8]; // @[el2_lsu_bus_buffer.scala 216:65] + wire [7:0] _T_618 = _T_602 | _T_607; // @[el2_lsu_bus_buffer.scala 216:96] + wire [7:0] _T_619 = _T_618 | _T_612; // @[el2_lsu_bus_buffer.scala 216:96] + wire [7:0] _T_620 = _T_619 | _T_617; // @[el2_lsu_bus_buffer.scala 216:96] + wire [7:0] _T_623 = ld_byte_hitvecfn_lo_0[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_625 = _T_623 & buf_data_0[7:0]; // @[el2_lsu_bus_buffer.scala 217:65] + wire [7:0] _T_628 = ld_byte_hitvecfn_lo_0[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_630 = _T_628 & buf_data_1[7:0]; // @[el2_lsu_bus_buffer.scala 217:65] + wire [7:0] _T_633 = ld_byte_hitvecfn_lo_0[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_635 = _T_633 & buf_data_2[7:0]; // @[el2_lsu_bus_buffer.scala 217:65] + wire [7:0] _T_638 = ld_byte_hitvecfn_lo_0[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_640 = _T_638 & buf_data_3[7:0]; // @[el2_lsu_bus_buffer.scala 217:65] + wire [7:0] _T_641 = _T_625 | _T_630; // @[el2_lsu_bus_buffer.scala 217:95] + wire [7:0] _T_642 = _T_641 | _T_635; // @[el2_lsu_bus_buffer.scala 217:95] + wire [7:0] _T_643 = _T_642 | _T_640; // @[el2_lsu_bus_buffer.scala 217:95] + wire [32:0] _T_646 = {_T_574,_T_597,_T_620,_T_643}; // @[Cat.scala 29:58] + wire [7:0] _T_649 = ld_byte_hitvecfn_hi_3[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [8:0] _GEN_358 = {{1'd0}, _T_649}; // @[el2_lsu_bus_buffer.scala 219:91] + wire [8:0] _T_651 = _GEN_358 & buf_data_0[31:23]; // @[el2_lsu_bus_buffer.scala 219:91] + wire [7:0] _T_654 = ld_byte_hitvecfn_hi_3[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [8:0] _GEN_359 = {{1'd0}, _T_654}; // @[el2_lsu_bus_buffer.scala 219:91] + wire [8:0] _T_656 = _GEN_359 & buf_data_1[31:23]; // @[el2_lsu_bus_buffer.scala 219:91] + wire [7:0] _T_659 = ld_byte_hitvecfn_hi_3[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [8:0] _GEN_360 = {{1'd0}, _T_659}; // @[el2_lsu_bus_buffer.scala 219:91] + wire [8:0] _T_661 = _GEN_360 & buf_data_2[31:23]; // @[el2_lsu_bus_buffer.scala 219:91] + wire [7:0] _T_664 = ld_byte_hitvecfn_hi_3[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [8:0] _GEN_361 = {{1'd0}, _T_664}; // @[el2_lsu_bus_buffer.scala 219:91] + wire [8:0] _T_666 = _GEN_361 & buf_data_3[31:23]; // @[el2_lsu_bus_buffer.scala 219:91] + wire [8:0] _T_667 = _T_651 | _T_656; // @[el2_lsu_bus_buffer.scala 219:123] + wire [8:0] _T_668 = _T_667 | _T_661; // @[el2_lsu_bus_buffer.scala 219:123] + wire [8:0] _T_669 = _T_668 | _T_666; // @[el2_lsu_bus_buffer.scala 219:123] + wire [7:0] _T_672 = ld_byte_hitvecfn_hi_2[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_674 = _T_672 & buf_data_0[23:16]; // @[el2_lsu_bus_buffer.scala 220:65] + wire [7:0] _T_677 = ld_byte_hitvecfn_hi_2[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_679 = _T_677 & buf_data_1[23:16]; // @[el2_lsu_bus_buffer.scala 220:65] + wire [7:0] _T_682 = ld_byte_hitvecfn_hi_2[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_684 = _T_682 & buf_data_2[23:16]; // @[el2_lsu_bus_buffer.scala 220:65] + wire [7:0] _T_687 = ld_byte_hitvecfn_hi_2[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_689 = _T_687 & buf_data_3[23:16]; // @[el2_lsu_bus_buffer.scala 220:65] + wire [7:0] _T_690 = _T_674 | _T_679; // @[el2_lsu_bus_buffer.scala 220:97] + wire [7:0] _T_691 = _T_690 | _T_684; // @[el2_lsu_bus_buffer.scala 220:97] + wire [7:0] _T_692 = _T_691 | _T_689; // @[el2_lsu_bus_buffer.scala 220:97] + wire [7:0] _T_695 = ld_byte_hitvecfn_hi_1[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_697 = _T_695 & buf_data_0[15:8]; // @[el2_lsu_bus_buffer.scala 221:65] + wire [7:0] _T_700 = ld_byte_hitvecfn_hi_1[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_702 = _T_700 & buf_data_1[15:8]; // @[el2_lsu_bus_buffer.scala 221:65] + wire [7:0] _T_705 = ld_byte_hitvecfn_hi_1[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_707 = _T_705 & buf_data_2[15:8]; // @[el2_lsu_bus_buffer.scala 221:65] + wire [7:0] _T_710 = ld_byte_hitvecfn_hi_1[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_712 = _T_710 & buf_data_3[15:8]; // @[el2_lsu_bus_buffer.scala 221:65] + wire [7:0] _T_713 = _T_697 | _T_702; // @[el2_lsu_bus_buffer.scala 221:96] + wire [7:0] _T_714 = _T_713 | _T_707; // @[el2_lsu_bus_buffer.scala 221:96] + wire [7:0] _T_715 = _T_714 | _T_712; // @[el2_lsu_bus_buffer.scala 221:96] + wire [7:0] _T_718 = ld_byte_hitvecfn_hi_0[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_720 = _T_718 & buf_data_0[7:0]; // @[el2_lsu_bus_buffer.scala 222:65] + wire [7:0] _T_723 = ld_byte_hitvecfn_hi_0[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_725 = _T_723 & buf_data_1[7:0]; // @[el2_lsu_bus_buffer.scala 222:65] + wire [7:0] _T_728 = ld_byte_hitvecfn_hi_0[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_730 = _T_728 & buf_data_2[7:0]; // @[el2_lsu_bus_buffer.scala 222:65] + wire [7:0] _T_733 = ld_byte_hitvecfn_hi_0[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_735 = _T_733 & buf_data_3[7:0]; // @[el2_lsu_bus_buffer.scala 222:65] + wire [7:0] _T_736 = _T_720 | _T_725; // @[el2_lsu_bus_buffer.scala 222:95] + wire [7:0] _T_737 = _T_736 | _T_730; // @[el2_lsu_bus_buffer.scala 222:95] + wire [7:0] _T_738 = _T_737 | _T_735; // @[el2_lsu_bus_buffer.scala 222:95] + wire [32:0] _T_741 = {_T_669,_T_692,_T_715,_T_738}; // @[Cat.scala 29:58] + wire [3:0] _T_742 = io_lsu_pkt_r_by ? 4'h1 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_743 = io_lsu_pkt_r_half ? 4'h3 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_744 = io_lsu_pkt_r_word ? 4'hf : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_745 = _T_742 | _T_743; // @[Mux.scala 27:72] + wire [3:0] ldst_byteen_r = _T_745 | _T_744; // @[Mux.scala 27:72] + wire [7:0] _T_747 = {4'h0,ldst_byteen_r}; // @[Cat.scala 29:58] + wire [10:0] _GEN_362 = {{3'd0}, _T_747}; // @[el2_lsu_bus_buffer.scala 228:45] + wire [10:0] byteen = _GEN_362 << io_lsu_addr_r[1:0]; // @[el2_lsu_bus_buffer.scala 228:45] + wire [3:0] ldst_byteen_hi_r = byteen[7:4]; // @[el2_lsu_bus_buffer.scala 229:32] + wire [3:0] ldst_byteen_lo_r = byteen[3:0]; // @[el2_lsu_bus_buffer.scala 230:32] + wire [63:0] _T_749 = {32'h0,io_store_data_r}; // @[Cat.scala 29:58] + wire [3:0] _GEN_363 = {{2'd0}, io_lsu_addr_r[1:0]}; // @[el2_lsu_bus_buffer.scala 231:58] + wire [5:0] _T_751 = 4'h8 * _GEN_363; // @[el2_lsu_bus_buffer.scala 231:58] + wire [126:0] _GEN_364 = {{63'd0}, _T_749}; // @[el2_lsu_bus_buffer.scala 231:52] + wire [126:0] store_data = _GEN_364 << _T_751; // @[el2_lsu_bus_buffer.scala 231:52] + wire [31:0] store_data_hi_r = store_data[63:32]; // @[el2_lsu_bus_buffer.scala 232:35] + wire [31:0] store_data_lo_r = store_data[31:0]; // @[el2_lsu_bus_buffer.scala 233:35] + wire ldst_samedw_r = io_lsu_addr_r[3] == io_end_addr_r[3]; // @[el2_lsu_bus_buffer.scala 234:40] + wire _T_755 = io_lsu_addr_r[1:0] == 2'h0; // @[el2_lsu_bus_buffer.scala 235:74] + wire _T_757 = ~io_lsu_addr_r[0]; // @[el2_lsu_bus_buffer.scala 236:26] + wire _T_758 = io_lsu_pkt_r_word & _T_755; // @[Mux.scala 27:72] + wire _T_759 = io_lsu_pkt_r_half & _T_757; // @[Mux.scala 27:72] + wire _T_761 = _T_758 | _T_759; // @[Mux.scala 27:72] + wire is_aligned_r = _T_761 | io_lsu_pkt_r_by; // @[Mux.scala 27:72] + wire _T_763 = io_lsu_pkt_r_load | io_no_word_merge_r; // @[el2_lsu_bus_buffer.scala 238:55] + wire _T_764 = io_lsu_busreq_r & _T_763; // @[el2_lsu_bus_buffer.scala 238:34] + wire _T_765 = ~ibuf_valid; // @[el2_lsu_bus_buffer.scala 238:79] + wire ibuf_byp = _T_764 & _T_765; // @[el2_lsu_bus_buffer.scala 238:77] + wire _T_766 = io_lsu_busreq_r & io_lsu_commit_r; // @[el2_lsu_bus_buffer.scala 239:36] + wire _T_767 = ~ibuf_byp; // @[el2_lsu_bus_buffer.scala 239:56] + wire ibuf_wr_en = _T_766 & _T_767; // @[el2_lsu_bus_buffer.scala 239:54] + wire _T_768 = ~ibuf_wr_en; // @[el2_lsu_bus_buffer.scala 241:36] + reg [2:0] ibuf_timer; // @[el2_lsu_bus_buffer.scala 283:59] + wire _T_777 = ibuf_timer == 3'h7; // @[el2_lsu_bus_buffer.scala 247:62] + wire _T_778 = ibuf_wr_en | _T_777; // @[el2_lsu_bus_buffer.scala 247:48] + wire _T_834 = _T_766 & io_lsu_pkt_r_store; // @[el2_lsu_bus_buffer.scala 265:54] + wire _T_835 = _T_834 & ibuf_valid; // @[el2_lsu_bus_buffer.scala 265:75] + wire _T_836 = _T_835 & ibuf_write; // @[el2_lsu_bus_buffer.scala 265:88] + wire _T_839 = io_lsu_addr_r[31:2] == ibuf_addr[31:2]; // @[el2_lsu_bus_buffer.scala 265:124] + wire _T_840 = _T_836 & _T_839; // @[el2_lsu_bus_buffer.scala 265:101] + wire _T_841 = ~io_is_sideeffects_r; // @[el2_lsu_bus_buffer.scala 265:147] + wire _T_842 = _T_840 & _T_841; // @[el2_lsu_bus_buffer.scala 265:145] + wire _T_843 = ~io_dec_tlu_wb_coalescing_disable; // @[el2_lsu_bus_buffer.scala 265:170] + wire ibuf_merge_en = _T_842 & _T_843; // @[el2_lsu_bus_buffer.scala 265:168] + wire ibuf_merge_in = ~io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 266:20] + wire _T_779 = ibuf_merge_en & ibuf_merge_in; // @[el2_lsu_bus_buffer.scala 247:98] + wire _T_780 = ~_T_779; // @[el2_lsu_bus_buffer.scala 247:82] + wire _T_781 = _T_778 & _T_780; // @[el2_lsu_bus_buffer.scala 247:80] + wire _T_782 = _T_781 | ibuf_byp; // @[el2_lsu_bus_buffer.scala 248:5] + wire _T_770 = ~io_lsu_busreq_r; // @[el2_lsu_bus_buffer.scala 242:44] + wire _T_771 = io_lsu_busreq_m & _T_770; // @[el2_lsu_bus_buffer.scala 242:42] + wire _T_772 = _T_771 & ibuf_valid; // @[el2_lsu_bus_buffer.scala 242:61] + wire _T_775 = ibuf_addr[31:2] != io_lsu_addr_m[31:2]; // @[el2_lsu_bus_buffer.scala 242:115] + wire _T_776 = io_lsu_pkt_m_load | _T_775; // @[el2_lsu_bus_buffer.scala 242:95] + wire ibuf_force_drain = _T_772 & _T_776; // @[el2_lsu_bus_buffer.scala 242:74] + wire _T_783 = _T_782 | ibuf_force_drain; // @[el2_lsu_bus_buffer.scala 248:16] + reg ibuf_sideeffect; // @[Reg.scala 27:20] + wire _T_784 = _T_783 | ibuf_sideeffect; // @[el2_lsu_bus_buffer.scala 248:35] + wire _T_785 = ~ibuf_write; // @[el2_lsu_bus_buffer.scala 248:55] + wire _T_786 = _T_784 | _T_785; // @[el2_lsu_bus_buffer.scala 248:53] + wire _T_787 = _T_786 | io_dec_tlu_wb_coalescing_disable; // @[el2_lsu_bus_buffer.scala 248:67] + wire ibuf_drain_vld = ibuf_valid & _T_787; // @[el2_lsu_bus_buffer.scala 247:32] + wire _T_769 = ibuf_drain_vld & _T_768; // @[el2_lsu_bus_buffer.scala 241:34] + wire ibuf_rst = _T_769 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 241:49] + reg [1:0] WrPtr1_r; // @[el2_lsu_bus_buffer.scala 629:49] + reg [1:0] WrPtr0_r; // @[el2_lsu_bus_buffer.scala 628:49] + reg [1:0] ibuf_tag; // @[Reg.scala 27:20] + wire [1:0] ibuf_sz_in = {io_lsu_pkt_r_word,io_lsu_pkt_r_half}; // @[Cat.scala 29:58] + wire [3:0] _T_794 = ibuf_byteen | ldst_byteen_lo_r; // @[el2_lsu_bus_buffer.scala 257:77] + reg [31:0] ibuf_data; // @[el2_lib.scala 478:16] + wire [7:0] _T_802 = ldst_byteen_lo_r[0] ? store_data_lo_r[7:0] : ibuf_data[7:0]; // @[el2_lsu_bus_buffer.scala 262:8] + wire [7:0] _T_804 = _T_779 ? _T_802 : ibuf_data[7:0]; // @[el2_lsu_bus_buffer.scala 261:46] + wire [7:0] _T_809 = ldst_byteen_lo_r[1] ? store_data_lo_r[15:8] : ibuf_data[15:8]; // @[el2_lsu_bus_buffer.scala 262:8] + wire [7:0] _T_811 = _T_779 ? _T_809 : ibuf_data[15:8]; // @[el2_lsu_bus_buffer.scala 261:46] + wire [7:0] _T_816 = ldst_byteen_lo_r[2] ? store_data_lo_r[23:16] : ibuf_data[23:16]; // @[el2_lsu_bus_buffer.scala 262:8] + wire [7:0] _T_818 = _T_779 ? _T_816 : ibuf_data[23:16]; // @[el2_lsu_bus_buffer.scala 261:46] + wire [7:0] _T_823 = ldst_byteen_lo_r[3] ? store_data_lo_r[31:24] : ibuf_data[31:24]; // @[el2_lsu_bus_buffer.scala 262:8] + wire [7:0] _T_825 = _T_779 ? _T_823 : ibuf_data[31:24]; // @[el2_lsu_bus_buffer.scala 261:46] + wire [23:0] _T_827 = {_T_825,_T_818,_T_811}; // @[Cat.scala 29:58] + wire _T_828 = ibuf_timer < 3'h7; // @[el2_lsu_bus_buffer.scala 263:59] + wire [2:0] _T_831 = ibuf_timer + 3'h1; // @[el2_lsu_bus_buffer.scala 263:93] + wire _T_846 = ~ibuf_merge_in; // @[el2_lsu_bus_buffer.scala 267:65] + wire _T_847 = ibuf_merge_en & _T_846; // @[el2_lsu_bus_buffer.scala 267:63] + wire _T_850 = ibuf_byteen[0] | ldst_byteen_lo_r[0]; // @[el2_lsu_bus_buffer.scala 267:96] + wire _T_852 = _T_847 ? _T_850 : ibuf_byteen[0]; // @[el2_lsu_bus_buffer.scala 267:48] + wire _T_857 = ibuf_byteen[1] | ldst_byteen_lo_r[1]; // @[el2_lsu_bus_buffer.scala 267:96] + wire _T_859 = _T_847 ? _T_857 : ibuf_byteen[1]; // @[el2_lsu_bus_buffer.scala 267:48] + wire _T_864 = ibuf_byteen[2] | ldst_byteen_lo_r[2]; // @[el2_lsu_bus_buffer.scala 267:96] + wire _T_866 = _T_847 ? _T_864 : ibuf_byteen[2]; // @[el2_lsu_bus_buffer.scala 267:48] + wire _T_871 = ibuf_byteen[3] | ldst_byteen_lo_r[3]; // @[el2_lsu_bus_buffer.scala 267:96] + wire _T_873 = _T_847 ? _T_871 : ibuf_byteen[3]; // @[el2_lsu_bus_buffer.scala 267:48] + wire [3:0] ibuf_byteen_out = {_T_873,_T_866,_T_859,_T_852}; // @[Cat.scala 29:58] + wire [7:0] _T_883 = _T_847 ? _T_802 : ibuf_data[7:0]; // @[el2_lsu_bus_buffer.scala 268:45] + wire [7:0] _T_891 = _T_847 ? _T_809 : ibuf_data[15:8]; // @[el2_lsu_bus_buffer.scala 268:45] + wire [7:0] _T_899 = _T_847 ? _T_816 : ibuf_data[23:16]; // @[el2_lsu_bus_buffer.scala 268:45] + wire [7:0] _T_907 = _T_847 ? _T_823 : ibuf_data[31:24]; // @[el2_lsu_bus_buffer.scala 268:45] + wire [31:0] ibuf_data_out = {_T_907,_T_899,_T_891,_T_883}; // @[Cat.scala 29:58] + wire _T_910 = ibuf_wr_en | ibuf_valid; // @[el2_lsu_bus_buffer.scala 270:28] + wire _T_915 = ibuf_wr_en & io_lsu_bus_ibuf_c1_clk; // @[el2_lsu_bus_buffer.scala 271:89] + reg [1:0] ibuf_dualtag; // @[Reg.scala 27:20] + reg ibuf_dual; // @[Reg.scala 27:20] + reg ibuf_samedw; // @[Reg.scala 27:20] + reg ibuf_nomerge; // @[Reg.scala 27:20] + reg ibuf_unsign; // @[Reg.scala 27:20] + reg [1:0] ibuf_sz; // @[Reg.scala 27:20] + wire [2:0] _GEN_365 = {{2'd0}, buf_write[3]}; // @[el2_lsu_bus_buffer.scala 536:79] + wire _T_4287 = _GEN_365 == 3'h2; // @[el2_lsu_bus_buffer.scala 536:79] + wire _T_4288 = buf_write[3] & _T_4287; // @[el2_lsu_bus_buffer.scala 536:64] + wire _T_4289 = ~buf_cmd_state_bus_en_3; // @[el2_lsu_bus_buffer.scala 536:91] + wire _T_4290 = _T_4288 & _T_4289; // @[el2_lsu_bus_buffer.scala 536:89] + wire [2:0] _GEN_366 = {{2'd0}, buf_write[2]}; // @[el2_lsu_bus_buffer.scala 536:79] + wire _T_4281 = _GEN_366 == 3'h2; // @[el2_lsu_bus_buffer.scala 536:79] + wire _T_4282 = buf_write[2] & _T_4281; // @[el2_lsu_bus_buffer.scala 536:64] + wire _T_4283 = ~buf_cmd_state_bus_en_2; // @[el2_lsu_bus_buffer.scala 536:91] + wire _T_4284 = _T_4282 & _T_4283; // @[el2_lsu_bus_buffer.scala 536:89] + wire [1:0] _T_4291 = _T_4290 + _T_4284; // @[el2_lsu_bus_buffer.scala 536:142] + wire [2:0] _GEN_367 = {{2'd0}, buf_write[1]}; // @[el2_lsu_bus_buffer.scala 536:79] + wire _T_4275 = _GEN_367 == 3'h2; // @[el2_lsu_bus_buffer.scala 536:79] + wire _T_4276 = buf_write[1] & _T_4275; // @[el2_lsu_bus_buffer.scala 536:64] + wire _T_4277 = ~buf_cmd_state_bus_en_1; // @[el2_lsu_bus_buffer.scala 536:91] + wire _T_4278 = _T_4276 & _T_4277; // @[el2_lsu_bus_buffer.scala 536:89] + wire [1:0] _GEN_368 = {{1'd0}, _T_4278}; // @[el2_lsu_bus_buffer.scala 536:142] + wire [2:0] _T_4292 = _T_4291 + _GEN_368; // @[el2_lsu_bus_buffer.scala 536:142] + wire [2:0] _GEN_369 = {{2'd0}, buf_write[0]}; // @[el2_lsu_bus_buffer.scala 536:79] + wire _T_4269 = _GEN_369 == 3'h2; // @[el2_lsu_bus_buffer.scala 536:79] + wire _T_4270 = buf_write[0] & _T_4269; // @[el2_lsu_bus_buffer.scala 536:64] + wire _T_4271 = ~buf_cmd_state_bus_en_0; // @[el2_lsu_bus_buffer.scala 536:91] + wire _T_4272 = _T_4270 & _T_4271; // @[el2_lsu_bus_buffer.scala 536:89] + wire [2:0] _GEN_370 = {{2'd0}, _T_4272}; // @[el2_lsu_bus_buffer.scala 536:142] + wire [3:0] buf_numvld_wrcmd_any = _T_4292 + _GEN_370; // @[el2_lsu_bus_buffer.scala 536:142] + wire _T_941 = buf_numvld_wrcmd_any == 4'h1; // @[el2_lsu_bus_buffer.scala 293:43] + wire _T_4309 = _T_4287 & _T_4289; // @[el2_lsu_bus_buffer.scala 537:73] + wire _T_4305 = _T_4281 & _T_4283; // @[el2_lsu_bus_buffer.scala 537:73] + wire [1:0] _T_4310 = _T_4309 + _T_4305; // @[el2_lsu_bus_buffer.scala 537:126] + wire _T_4301 = _T_4275 & _T_4277; // @[el2_lsu_bus_buffer.scala 537:73] + wire [1:0] _GEN_374 = {{1'd0}, _T_4301}; // @[el2_lsu_bus_buffer.scala 537:126] + wire [2:0] _T_4311 = _T_4310 + _GEN_374; // @[el2_lsu_bus_buffer.scala 537:126] + wire _T_4297 = _T_4269 & _T_4271; // @[el2_lsu_bus_buffer.scala 537:73] + wire [2:0] _GEN_376 = {{2'd0}, _T_4297}; // @[el2_lsu_bus_buffer.scala 537:126] + wire [3:0] buf_numvld_cmd_any = _T_4311 + _GEN_376; // @[el2_lsu_bus_buffer.scala 537:126] + wire _T_942 = buf_numvld_cmd_any == 4'h1; // @[el2_lsu_bus_buffer.scala 293:72] + wire _T_943 = _T_941 & _T_942; // @[el2_lsu_bus_buffer.scala 293:51] + reg [2:0] obuf_wr_timer; // @[el2_lsu_bus_buffer.scala 390:54] + wire _T_944 = obuf_wr_timer != 3'h7; // @[el2_lsu_bus_buffer.scala 293:97] + wire _T_945 = _T_943 & _T_944; // @[el2_lsu_bus_buffer.scala 293:80] + wire _T_947 = _T_945 & _T_843; // @[el2_lsu_bus_buffer.scala 293:114] + reg buf_nomerge_0; // @[Reg.scala 27:20] + wire _T_960 = ~buf_nomerge_0; // @[el2_lsu_bus_buffer.scala 294:31] + wire _T_961 = _T_947 & _T_960; // @[el2_lsu_bus_buffer.scala 294:29] + reg _T_4180; // @[Reg.scala 27:20] + reg _T_4177; // @[Reg.scala 27:20] + reg _T_4174; // @[Reg.scala 27:20] + reg _T_4171; // @[Reg.scala 27:20] + wire [3:0] buf_sideeffect = {_T_4180,_T_4177,_T_4174,_T_4171}; // @[Cat.scala 29:58] + wire _T_978 = ~buf_sideeffect[0]; // @[el2_lsu_bus_buffer.scala 295:5] + wire _T_979 = _T_961 & _T_978; // @[el2_lsu_bus_buffer.scala 294:140] + wire _T_990 = _T_771 & _T_765; // @[el2_lsu_bus_buffer.scala 297:58] + wire _T_992 = _T_990 & _T_942; // @[el2_lsu_bus_buffer.scala 297:72] + wire _T_1010 = io_lsu_addr_m[31:2] != buf_addr_0[31:2]; // @[el2_lsu_bus_buffer.scala 297:123] + wire obuf_force_wr_en = _T_992 & _T_1010; // @[el2_lsu_bus_buffer.scala 297:101] + wire _T_980 = ~obuf_force_wr_en; // @[el2_lsu_bus_buffer.scala 295:119] + wire obuf_wr_wait = _T_979 & _T_980; // @[el2_lsu_bus_buffer.scala 295:117] + wire _T_981 = |buf_numvld_cmd_any; // @[el2_lsu_bus_buffer.scala 296:75] + wire _T_982 = obuf_wr_timer < 3'h7; // @[el2_lsu_bus_buffer.scala 296:95] + wire _T_983 = _T_981 & _T_982; // @[el2_lsu_bus_buffer.scala 296:79] + wire [2:0] _T_985 = obuf_wr_timer + 3'h1; // @[el2_lsu_bus_buffer.scala 296:121] + wire _T_4335 = _GEN_365 == 3'h1; // @[el2_lsu_bus_buffer.scala 538:64] + wire _T_4338 = _T_4335 | _T_4287; // @[el2_lsu_bus_buffer.scala 538:74] + wire _T_4340 = _T_4338 & _T_4289; // @[el2_lsu_bus_buffer.scala 538:100] + wire _T_4328 = _GEN_366 == 3'h1; // @[el2_lsu_bus_buffer.scala 538:64] + wire _T_4331 = _T_4328 | _T_4281; // @[el2_lsu_bus_buffer.scala 538:74] + wire _T_4333 = _T_4331 & _T_4283; // @[el2_lsu_bus_buffer.scala 538:100] + wire [1:0] _T_4341 = _T_4340 + _T_4333; // @[el2_lsu_bus_buffer.scala 538:153] + wire _T_4321 = _GEN_367 == 3'h1; // @[el2_lsu_bus_buffer.scala 538:64] + wire _T_4324 = _T_4321 | _T_4275; // @[el2_lsu_bus_buffer.scala 538:74] + wire _T_4326 = _T_4324 & _T_4277; // @[el2_lsu_bus_buffer.scala 538:100] + wire [1:0] _GEN_383 = {{1'd0}, _T_4326}; // @[el2_lsu_bus_buffer.scala 538:153] + wire [2:0] _T_4342 = _T_4341 + _GEN_383; // @[el2_lsu_bus_buffer.scala 538:153] + wire _T_4314 = _GEN_369 == 3'h1; // @[el2_lsu_bus_buffer.scala 538:64] + wire _T_4317 = _T_4314 | _T_4269; // @[el2_lsu_bus_buffer.scala 538:74] + wire _T_4319 = _T_4317 & _T_4271; // @[el2_lsu_bus_buffer.scala 538:100] + wire [2:0] _GEN_386 = {{2'd0}, _T_4319}; // @[el2_lsu_bus_buffer.scala 538:153] + wire [3:0] buf_numvld_pend_any = _T_4342 + _GEN_386; // @[el2_lsu_bus_buffer.scala 538:153] + wire _T_1012 = buf_numvld_pend_any == 4'h0; // @[el2_lsu_bus_buffer.scala 299:53] + wire _T_1013 = ibuf_byp & _T_1012; // @[el2_lsu_bus_buffer.scala 299:31] + wire _T_1014 = ~io_lsu_pkt_r_store; // @[el2_lsu_bus_buffer.scala 299:64] + wire _T_1015 = _T_1014 | io_no_dword_merge_r; // @[el2_lsu_bus_buffer.scala 299:84] + wire ibuf_buf_byp = _T_1013 & _T_1015; // @[el2_lsu_bus_buffer.scala 299:61] + wire _T_1016 = ibuf_buf_byp & io_lsu_commit_r; // @[el2_lsu_bus_buffer.scala 314:32] + wire _T_4631 = buf_state_0 == 3'h3; // @[el2_lsu_bus_buffer.scala 565:68] + wire _T_4633 = buf_sideeffect[0] & io_dec_tlu_sideeffect_posted_disable; // @[el2_lsu_bus_buffer.scala 565:99] + wire _T_4643 = _T_4631 & _T_4633; // @[Mux.scala 27:72] + wire _T_4634 = buf_state_1 == 3'h3; // @[el2_lsu_bus_buffer.scala 565:68] + wire _T_4636 = buf_sideeffect[1] & io_dec_tlu_sideeffect_posted_disable; // @[el2_lsu_bus_buffer.scala 565:99] + wire _T_4644 = _T_4634 & _T_4636; // @[Mux.scala 27:72] + wire _T_4647 = _T_4643 | _T_4644; // @[Mux.scala 27:72] + wire _T_4637 = buf_state_2 == 3'h3; // @[el2_lsu_bus_buffer.scala 565:68] + wire _T_4639 = buf_sideeffect[2] & io_dec_tlu_sideeffect_posted_disable; // @[el2_lsu_bus_buffer.scala 565:99] + wire _T_4645 = _T_4637 & _T_4639; // @[Mux.scala 27:72] + wire _T_4648 = _T_4647 | _T_4645; // @[Mux.scala 27:72] + wire _T_4640 = buf_state_3 == 3'h3; // @[el2_lsu_bus_buffer.scala 565:68] + wire _T_4642 = buf_sideeffect[3] & io_dec_tlu_sideeffect_posted_disable; // @[el2_lsu_bus_buffer.scala 565:99] + wire _T_4646 = _T_4640 & _T_4642; // @[Mux.scala 27:72] + wire bus_sideeffect_pend = _T_4648 | _T_4646; // @[Mux.scala 27:72] + wire _T_1017 = io_is_sideeffects_r & bus_sideeffect_pend; // @[el2_lsu_bus_buffer.scala 314:74] + wire _T_1018 = ~_T_1017; // @[el2_lsu_bus_buffer.scala 314:52] + wire _T_1019 = _T_1016 & _T_1018; // @[el2_lsu_bus_buffer.scala 314:50] + reg buf_dual_3; // @[Reg.scala 27:20] + reg buf_dual_2; // @[Reg.scala 27:20] + reg buf_dual_1; // @[Reg.scala 27:20] + reg buf_dual_0; // @[Reg.scala 27:20] + reg buf_samedw_3; // @[Reg.scala 27:20] + reg buf_samedw_2; // @[Reg.scala 27:20] + reg buf_samedw_1; // @[Reg.scala 27:20] + reg buf_samedw_0; // @[Reg.scala 27:20] + wire _T_1129 = ~buf_write[0]; // @[el2_lsu_bus_buffer.scala 317:150] + reg obuf_write; // @[Reg.scala 27:20] + reg obuf_cmd_done; // @[el2_lsu_bus_buffer.scala 377:54] + reg obuf_data_done; // @[el2_lsu_bus_buffer.scala 378:55] + wire _T_4707 = obuf_cmd_done | obuf_data_done; // @[el2_lsu_bus_buffer.scala 569:54] + wire _T_4708 = obuf_cmd_done ? io_lsu_axi_wready : io_lsu_axi_awready; // @[el2_lsu_bus_buffer.scala 569:75] + wire _T_4710 = _T_4707 ? _T_4708 : io_lsu_axi_awready; // @[el2_lsu_bus_buffer.scala 569:39] + wire bus_cmd_ready = obuf_write ? _T_4710 : io_lsu_axi_arready; // @[el2_lsu_bus_buffer.scala 569:23] + wire _T_1156 = ~obuf_valid; // @[el2_lsu_bus_buffer.scala 318:48] + wire _T_1157 = bus_cmd_ready | _T_1156; // @[el2_lsu_bus_buffer.scala 318:46] + reg obuf_nosend; // @[Reg.scala 27:20] + wire _T_1158 = _T_1157 | obuf_nosend; // @[el2_lsu_bus_buffer.scala 318:60] + wire _T_1159 = _T_1019 & _T_1158; // @[el2_lsu_bus_buffer.scala 318:29] + wire _T_1160 = ~obuf_wr_wait; // @[el2_lsu_bus_buffer.scala 318:77] + wire _T_1161 = _T_1159 & _T_1160; // @[el2_lsu_bus_buffer.scala 318:75] + reg [31:0] obuf_addr; // @[el2_lib.scala 478:16] + wire _T_4655 = obuf_addr[31:3] == buf_addr_0[31:3]; // @[el2_lsu_bus_buffer.scala 567:56] + wire _T_4656 = obuf_valid & _T_4655; // @[el2_lsu_bus_buffer.scala 567:38] + wire _T_4658 = obuf_tag1 == 2'h0; // @[el2_lsu_bus_buffer.scala 567:126] + wire _T_4659 = obuf_merge & _T_4658; // @[el2_lsu_bus_buffer.scala 567:114] + wire _T_4660 = _T_3412 | _T_4659; // @[el2_lsu_bus_buffer.scala 567:100] + wire _T_4661 = ~_T_4660; // @[el2_lsu_bus_buffer.scala 567:80] + wire _T_4662 = _T_4656 & _T_4661; // @[el2_lsu_bus_buffer.scala 567:78] + wire _T_4699 = _T_4631 & _T_4662; // @[Mux.scala 27:72] + wire _T_4667 = obuf_addr[31:3] == buf_addr_1[31:3]; // @[el2_lsu_bus_buffer.scala 567:56] + wire _T_4668 = obuf_valid & _T_4667; // @[el2_lsu_bus_buffer.scala 567:38] + wire _T_4670 = obuf_tag1 == 2'h1; // @[el2_lsu_bus_buffer.scala 567:126] + wire _T_4671 = obuf_merge & _T_4670; // @[el2_lsu_bus_buffer.scala 567:114] + wire _T_4672 = _T_3605 | _T_4671; // @[el2_lsu_bus_buffer.scala 567:100] + wire _T_4673 = ~_T_4672; // @[el2_lsu_bus_buffer.scala 567:80] + wire _T_4674 = _T_4668 & _T_4673; // @[el2_lsu_bus_buffer.scala 567:78] + wire _T_4700 = _T_4634 & _T_4674; // @[Mux.scala 27:72] + wire _T_4703 = _T_4699 | _T_4700; // @[Mux.scala 27:72] + wire _T_4679 = obuf_addr[31:3] == buf_addr_2[31:3]; // @[el2_lsu_bus_buffer.scala 567:56] + wire _T_4680 = obuf_valid & _T_4679; // @[el2_lsu_bus_buffer.scala 567:38] + wire _T_4682 = obuf_tag1 == 2'h2; // @[el2_lsu_bus_buffer.scala 567:126] + wire _T_4683 = obuf_merge & _T_4682; // @[el2_lsu_bus_buffer.scala 567:114] + wire _T_4684 = _T_3798 | _T_4683; // @[el2_lsu_bus_buffer.scala 567:100] + wire _T_4685 = ~_T_4684; // @[el2_lsu_bus_buffer.scala 567:80] + wire _T_4686 = _T_4680 & _T_4685; // @[el2_lsu_bus_buffer.scala 567:78] + wire _T_4701 = _T_4637 & _T_4686; // @[Mux.scala 27:72] + wire _T_4704 = _T_4703 | _T_4701; // @[Mux.scala 27:72] + wire _T_4691 = obuf_addr[31:3] == buf_addr_3[31:3]; // @[el2_lsu_bus_buffer.scala 567:56] + wire _T_4692 = obuf_valid & _T_4691; // @[el2_lsu_bus_buffer.scala 567:38] + wire _T_4694 = obuf_tag1 == 2'h3; // @[el2_lsu_bus_buffer.scala 567:126] + wire _T_4695 = obuf_merge & _T_4694; // @[el2_lsu_bus_buffer.scala 567:114] + wire _T_4696 = _T_3991 | _T_4695; // @[el2_lsu_bus_buffer.scala 567:100] + wire _T_4697 = ~_T_4696; // @[el2_lsu_bus_buffer.scala 567:80] + wire _T_4698 = _T_4692 & _T_4697; // @[el2_lsu_bus_buffer.scala 567:78] + wire _T_4702 = _T_4640 & _T_4698; // @[Mux.scala 27:72] + wire bus_addr_match_pending = _T_4704 | _T_4702; // @[Mux.scala 27:72] + wire _T_1164 = ~bus_addr_match_pending; // @[el2_lsu_bus_buffer.scala 318:118] + wire _T_1165 = _T_1161 & _T_1164; // @[el2_lsu_bus_buffer.scala 318:116] + wire obuf_wr_en = _T_1165 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 318:142] + wire _T_1167 = obuf_valid & obuf_nosend; // @[el2_lsu_bus_buffer.scala 320:47] + wire bus_wcmd_sent = io_lsu_axi_awvalid & io_lsu_axi_awready; // @[el2_lsu_bus_buffer.scala 570:39] + wire _T_4714 = obuf_cmd_done | bus_wcmd_sent; // @[el2_lsu_bus_buffer.scala 572:35] + wire bus_wdata_sent = io_lsu_axi_wvalid & io_lsu_axi_wready; // @[el2_lsu_bus_buffer.scala 571:39] + wire _T_4715 = obuf_data_done | bus_wdata_sent; // @[el2_lsu_bus_buffer.scala 572:70] + wire _T_4716 = _T_4714 & _T_4715; // @[el2_lsu_bus_buffer.scala 572:52] + wire _T_4717 = io_lsu_axi_arvalid & io_lsu_axi_arready; // @[el2_lsu_bus_buffer.scala 572:111] + wire bus_cmd_sent = _T_4716 | _T_4717; // @[el2_lsu_bus_buffer.scala 572:89] + wire _T_1168 = bus_cmd_sent | _T_1167; // @[el2_lsu_bus_buffer.scala 320:33] + wire _T_1169 = ~obuf_wr_en; // @[el2_lsu_bus_buffer.scala 320:65] + wire _T_1170 = _T_1168 & _T_1169; // @[el2_lsu_bus_buffer.scala 320:63] + wire _T_1171 = _T_1170 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 320:77] + wire obuf_rst = _T_1171 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 320:98] + wire obuf_write_in = ibuf_buf_byp ? io_lsu_pkt_r_store : buf_write[0]; // @[el2_lsu_bus_buffer.scala 321:26] + wire [31:0] obuf_addr_in = ibuf_buf_byp ? io_lsu_addr_r : buf_addr_0; // @[el2_lsu_bus_buffer.scala 323:25] + reg [1:0] buf_sz_0; // @[Reg.scala 27:20] + reg [1:0] buf_sz_1; // @[Reg.scala 27:20] + reg [1:0] buf_sz_2; // @[Reg.scala 27:20] + reg [1:0] buf_sz_3; // @[Reg.scala 27:20] + wire [1:0] obuf_sz_in = ibuf_buf_byp ? ibuf_sz_in : buf_sz_0; // @[el2_lsu_bus_buffer.scala 326:23] + wire _T_1229 = obuf_wr_en | obuf_rst; // @[el2_lsu_bus_buffer.scala 334:39] + wire _T_1230 = ~_T_1229; // @[el2_lsu_bus_buffer.scala 334:26] + wire _T_1236 = obuf_sz_in == 2'h0; // @[el2_lsu_bus_buffer.scala 338:72] + wire _T_1239 = ~obuf_addr_in[0]; // @[el2_lsu_bus_buffer.scala 338:98] + wire _T_1240 = obuf_sz_in[0] & _T_1239; // @[el2_lsu_bus_buffer.scala 338:96] + wire _T_1241 = _T_1236 | _T_1240; // @[el2_lsu_bus_buffer.scala 338:79] + wire _T_1244 = |obuf_addr_in[1:0]; // @[el2_lsu_bus_buffer.scala 338:153] + wire _T_1245 = ~_T_1244; // @[el2_lsu_bus_buffer.scala 338:134] + wire _T_1246 = obuf_sz_in[1] & _T_1245; // @[el2_lsu_bus_buffer.scala 338:132] + wire _T_1247 = _T_1241 | _T_1246; // @[el2_lsu_bus_buffer.scala 338:116] + wire obuf_aligned_in = ibuf_buf_byp ? is_aligned_r : _T_1247; // @[el2_lsu_bus_buffer.scala 338:28] + wire _T_1264 = obuf_addr_in[31:3] == obuf_addr[31:3]; // @[el2_lsu_bus_buffer.scala 352:40] + wire _T_1265 = _T_1264 & obuf_aligned_in; // @[el2_lsu_bus_buffer.scala 352:60] + reg obuf_sideeffect; // @[Reg.scala 27:20] + wire _T_1266 = ~obuf_sideeffect; // @[el2_lsu_bus_buffer.scala 352:80] + wire _T_1267 = _T_1265 & _T_1266; // @[el2_lsu_bus_buffer.scala 352:78] + wire _T_1268 = ~obuf_write; // @[el2_lsu_bus_buffer.scala 352:99] + wire _T_1269 = _T_1267 & _T_1268; // @[el2_lsu_bus_buffer.scala 352:97] + wire _T_1270 = ~obuf_write_in; // @[el2_lsu_bus_buffer.scala 352:113] + wire _T_1271 = _T_1269 & _T_1270; // @[el2_lsu_bus_buffer.scala 352:111] + wire _T_1272 = ~io_dec_tlu_external_ldfwd_disable; // @[el2_lsu_bus_buffer.scala 352:130] + wire _T_1273 = _T_1271 & _T_1272; // @[el2_lsu_bus_buffer.scala 352:128] + wire _T_1274 = ~obuf_nosend; // @[el2_lsu_bus_buffer.scala 353:20] + wire _T_1275 = obuf_valid & _T_1274; // @[el2_lsu_bus_buffer.scala 353:18] + reg obuf_rdrsp_pend; // @[el2_lsu_bus_buffer.scala 379:56] + wire bus_rsp_read = io_lsu_axi_rvalid & io_lsu_axi_rready; // @[el2_lsu_bus_buffer.scala 573:37] + reg [2:0] obuf_rdrsp_tag; // @[el2_lsu_bus_buffer.scala 380:55] + wire _T_1276 = io_lsu_axi_rid == obuf_rdrsp_tag; // @[el2_lsu_bus_buffer.scala 353:90] + wire _T_1277 = bus_rsp_read & _T_1276; // @[el2_lsu_bus_buffer.scala 353:70] + wire _T_1278 = ~_T_1277; // @[el2_lsu_bus_buffer.scala 353:55] + wire _T_1279 = obuf_rdrsp_pend & _T_1278; // @[el2_lsu_bus_buffer.scala 353:53] + wire _T_1280 = _T_1275 | _T_1279; // @[el2_lsu_bus_buffer.scala 353:34] + wire obuf_nosend_in = _T_1273 & _T_1280; // @[el2_lsu_bus_buffer.scala 352:165] + wire _T_1248 = ~obuf_nosend_in; // @[el2_lsu_bus_buffer.scala 346:44] + wire _T_1249 = obuf_wr_en & _T_1248; // @[el2_lsu_bus_buffer.scala 346:42] + wire _T_1250 = ~_T_1249; // @[el2_lsu_bus_buffer.scala 346:29] + wire _T_1251 = _T_1250 & obuf_rdrsp_pend; // @[el2_lsu_bus_buffer.scala 346:61] + wire _T_1255 = _T_1251 & _T_1278; // @[el2_lsu_bus_buffer.scala 346:79] + wire _T_1257 = bus_cmd_sent & _T_1268; // @[el2_lsu_bus_buffer.scala 347:20] + wire _T_1258 = ~io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 347:37] + wire _T_1259 = _T_1257 & _T_1258; // @[el2_lsu_bus_buffer.scala 347:35] + wire _T_1261 = bus_cmd_sent | _T_1268; // @[el2_lsu_bus_buffer.scala 349:44] + wire [7:0] _T_1283 = {ldst_byteen_lo_r,4'h0}; // @[Cat.scala 29:58] + wire [7:0] _T_1284 = {4'h0,ldst_byteen_lo_r}; // @[Cat.scala 29:58] + wire [7:0] _T_1285 = io_lsu_addr_r[2] ? _T_1283 : _T_1284; // @[el2_lsu_bus_buffer.scala 354:46] + wire [7:0] _T_1312 = {buf_byteen_0,4'h0}; // @[Cat.scala 29:58] + wire [7:0] _T_1325 = {4'h0,buf_byteen_0}; // @[Cat.scala 29:58] + wire [7:0] _T_1326 = buf_addr_0[2] ? _T_1312 : _T_1325; // @[el2_lsu_bus_buffer.scala 355:8] + wire [7:0] obuf_byteen0_in = ibuf_buf_byp ? _T_1285 : _T_1326; // @[el2_lsu_bus_buffer.scala 354:28] + wire [7:0] _T_1328 = {ldst_byteen_hi_r,4'h0}; // @[Cat.scala 29:58] + wire [7:0] _T_1329 = {4'h0,ldst_byteen_hi_r}; // @[Cat.scala 29:58] + wire [7:0] _T_1330 = io_end_addr_r[2] ? _T_1328 : _T_1329; // @[el2_lsu_bus_buffer.scala 356:46] + wire [7:0] obuf_byteen1_in = ibuf_buf_byp ? _T_1330 : _T_1326; // @[el2_lsu_bus_buffer.scala 356:28] + wire [63:0] _T_1402 = {buf_data_0,32'h0}; // @[Cat.scala 29:58] + wire [63:0] _T_1415 = {32'h0,buf_data_0}; // @[Cat.scala 29:58] + wire [63:0] _T_1416 = buf_addr_0[2] ? _T_1402 : _T_1415; // @[el2_lsu_bus_buffer.scala 360:8] + wire [63:0] _T_1418 = {store_data_hi_r,32'h0}; // @[Cat.scala 29:58] + wire [63:0] _T_1419 = {32'h0,store_data_hi_r}; // @[Cat.scala 29:58] + wire [63:0] _T_1420 = io_lsu_addr_r[2] ? _T_1418 : _T_1419; // @[el2_lsu_bus_buffer.scala 361:44] + wire [63:0] obuf_data1_in = ibuf_buf_byp ? _T_1420 : _T_1416; // @[el2_lsu_bus_buffer.scala 361:26] + reg buf_dualhi_3; // @[Reg.scala 27:20] + reg buf_dualhi_2; // @[Reg.scala 27:20] + reg buf_dualhi_1; // @[Reg.scala 27:20] + reg buf_dualhi_0; // @[Reg.scala 27:20] + wire _T_1761 = ibuf_buf_byp & ldst_samedw_r; // @[el2_lsu_bus_buffer.scala 372:19] + wire obuf_merge_en = _T_1761 & io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 372:35] + wire _T_1464 = obuf_merge_en & obuf_byteen1_in[0]; // @[el2_lsu_bus_buffer.scala 363:80] + wire _T_1465 = obuf_byteen0_in[0] | _T_1464; // @[el2_lsu_bus_buffer.scala 363:63] + wire _T_1468 = obuf_merge_en & obuf_byteen1_in[1]; // @[el2_lsu_bus_buffer.scala 363:80] + wire _T_1469 = obuf_byteen0_in[1] | _T_1468; // @[el2_lsu_bus_buffer.scala 363:63] + wire _T_1472 = obuf_merge_en & obuf_byteen1_in[2]; // @[el2_lsu_bus_buffer.scala 363:80] + wire _T_1473 = obuf_byteen0_in[2] | _T_1472; // @[el2_lsu_bus_buffer.scala 363:63] + wire _T_1476 = obuf_merge_en & obuf_byteen1_in[3]; // @[el2_lsu_bus_buffer.scala 363:80] + wire _T_1477 = obuf_byteen0_in[3] | _T_1476; // @[el2_lsu_bus_buffer.scala 363:63] + wire _T_1480 = obuf_merge_en & obuf_byteen1_in[4]; // @[el2_lsu_bus_buffer.scala 363:80] + wire _T_1481 = obuf_byteen0_in[4] | _T_1480; // @[el2_lsu_bus_buffer.scala 363:63] + wire _T_1484 = obuf_merge_en & obuf_byteen1_in[5]; // @[el2_lsu_bus_buffer.scala 363:80] + wire _T_1485 = obuf_byteen0_in[5] | _T_1484; // @[el2_lsu_bus_buffer.scala 363:63] + wire _T_1488 = obuf_merge_en & obuf_byteen1_in[6]; // @[el2_lsu_bus_buffer.scala 363:80] + wire _T_1489 = obuf_byteen0_in[6] | _T_1488; // @[el2_lsu_bus_buffer.scala 363:63] + wire _T_1492 = obuf_merge_en & obuf_byteen1_in[7]; // @[el2_lsu_bus_buffer.scala 363:80] + wire _T_1493 = obuf_byteen0_in[7] | _T_1492; // @[el2_lsu_bus_buffer.scala 363:63] + wire [7:0] obuf_byteen_in = {_T_1493,_T_1489,_T_1485,_T_1481,_T_1477,_T_1473,_T_1469,_T_1465}; // @[Cat.scala 29:58] + wire [7:0] _T_1504 = _T_1464 ? obuf_data1_in[7:0] : obuf_data1_in[7:0]; // @[el2_lsu_bus_buffer.scala 364:44] + wire [7:0] _T_1509 = _T_1468 ? obuf_data1_in[15:8] : obuf_data1_in[15:8]; // @[el2_lsu_bus_buffer.scala 364:44] + wire [7:0] _T_1514 = _T_1472 ? obuf_data1_in[23:16] : obuf_data1_in[23:16]; // @[el2_lsu_bus_buffer.scala 364:44] + wire [7:0] _T_1519 = _T_1476 ? obuf_data1_in[31:24] : obuf_data1_in[31:24]; // @[el2_lsu_bus_buffer.scala 364:44] + wire [7:0] _T_1524 = _T_1480 ? obuf_data1_in[39:32] : obuf_data1_in[39:32]; // @[el2_lsu_bus_buffer.scala 364:44] + wire [7:0] _T_1529 = _T_1484 ? obuf_data1_in[47:40] : obuf_data1_in[47:40]; // @[el2_lsu_bus_buffer.scala 364:44] + wire [7:0] _T_1534 = _T_1488 ? obuf_data1_in[55:48] : obuf_data1_in[55:48]; // @[el2_lsu_bus_buffer.scala 364:44] + wire [7:0] _T_1539 = _T_1492 ? obuf_data1_in[63:56] : obuf_data1_in[63:56]; // @[el2_lsu_bus_buffer.scala 364:44] + wire [55:0] _T_1545 = {_T_1539,_T_1534,_T_1529,_T_1524,_T_1519,_T_1514,_T_1509}; // @[Cat.scala 29:58] + wire _T_1764 = obuf_wr_en | obuf_valid; // @[el2_lsu_bus_buffer.scala 375:55] + reg [1:0] obuf_sz; // @[Reg.scala 27:20] + reg [7:0] obuf_byteen; // @[Reg.scala 27:20] + reg [63:0] obuf_data; // @[el2_lib.scala 478:16] + wire _T_1777 = buf_state_0 == 3'h0; // @[el2_lsu_bus_buffer.scala 392:59] + wire _T_1778 = ibuf_tag == 2'h0; // @[el2_lsu_bus_buffer.scala 392:97] + wire _T_1779 = ibuf_valid & _T_1778; // @[el2_lsu_bus_buffer.scala 392:86] + wire _T_1780 = WrPtr0_r == 2'h0; // @[el2_lsu_bus_buffer.scala 393:33] + wire _T_1781 = io_lsu_busreq_m & _T_1780; // @[el2_lsu_bus_buffer.scala 393:22] + wire _T_1782 = _T_1779 | _T_1781; // @[el2_lsu_bus_buffer.scala 392:106] + wire _T_1783 = WrPtr1_r == 2'h0; // @[el2_lsu_bus_buffer.scala 393:72] + wire _T_1784 = io_ldst_dual_r & _T_1783; // @[el2_lsu_bus_buffer.scala 393:60] + wire _T_1785 = _T_1782 | _T_1784; // @[el2_lsu_bus_buffer.scala 393:42] + wire _T_1786 = ~_T_1785; // @[el2_lsu_bus_buffer.scala 392:72] + wire _T_1787 = _T_1777 & _T_1786; // @[el2_lsu_bus_buffer.scala 392:70] + wire _T_1788 = buf_state_1 == 3'h0; // @[el2_lsu_bus_buffer.scala 392:59] + wire _T_1789 = ibuf_tag == 2'h1; // @[el2_lsu_bus_buffer.scala 392:97] + wire _T_1790 = ibuf_valid & _T_1789; // @[el2_lsu_bus_buffer.scala 392:86] + wire _T_1791 = WrPtr0_r == 2'h1; // @[el2_lsu_bus_buffer.scala 393:33] + wire _T_1792 = io_lsu_busreq_m & _T_1791; // @[el2_lsu_bus_buffer.scala 393:22] + wire _T_1793 = _T_1790 | _T_1792; // @[el2_lsu_bus_buffer.scala 392:106] + wire _T_1794 = WrPtr1_r == 2'h1; // @[el2_lsu_bus_buffer.scala 393:72] + wire _T_1795 = io_ldst_dual_r & _T_1794; // @[el2_lsu_bus_buffer.scala 393:60] + wire _T_1796 = _T_1793 | _T_1795; // @[el2_lsu_bus_buffer.scala 393:42] + wire _T_1797 = ~_T_1796; // @[el2_lsu_bus_buffer.scala 392:72] + wire _T_1798 = _T_1788 & _T_1797; // @[el2_lsu_bus_buffer.scala 392:70] + wire _T_1799 = buf_state_2 == 3'h0; // @[el2_lsu_bus_buffer.scala 392:59] + wire _T_1800 = ibuf_tag == 2'h2; // @[el2_lsu_bus_buffer.scala 392:97] + wire _T_1801 = ibuf_valid & _T_1800; // @[el2_lsu_bus_buffer.scala 392:86] + wire _T_1802 = WrPtr0_r == 2'h2; // @[el2_lsu_bus_buffer.scala 393:33] + wire _T_1803 = io_lsu_busreq_m & _T_1802; // @[el2_lsu_bus_buffer.scala 393:22] + wire _T_1804 = _T_1801 | _T_1803; // @[el2_lsu_bus_buffer.scala 392:106] + wire _T_1805 = WrPtr1_r == 2'h2; // @[el2_lsu_bus_buffer.scala 393:72] + wire _T_1806 = io_ldst_dual_r & _T_1805; // @[el2_lsu_bus_buffer.scala 393:60] + wire _T_1807 = _T_1804 | _T_1806; // @[el2_lsu_bus_buffer.scala 393:42] + wire _T_1808 = ~_T_1807; // @[el2_lsu_bus_buffer.scala 392:72] + wire _T_1809 = _T_1799 & _T_1808; // @[el2_lsu_bus_buffer.scala 392:70] + wire _T_1810 = buf_state_3 == 3'h0; // @[el2_lsu_bus_buffer.scala 392:59] + wire _T_1811 = ibuf_tag == 2'h3; // @[el2_lsu_bus_buffer.scala 392:97] + wire _T_1812 = ibuf_valid & _T_1811; // @[el2_lsu_bus_buffer.scala 392:86] + wire _T_1813 = WrPtr0_r == 2'h3; // @[el2_lsu_bus_buffer.scala 393:33] + wire _T_1814 = io_lsu_busreq_m & _T_1813; // @[el2_lsu_bus_buffer.scala 393:22] + wire _T_1815 = _T_1812 | _T_1814; // @[el2_lsu_bus_buffer.scala 392:106] + wire _T_1816 = WrPtr1_r == 2'h3; // @[el2_lsu_bus_buffer.scala 393:72] + wire _T_1817 = io_ldst_dual_r & _T_1816; // @[el2_lsu_bus_buffer.scala 393:60] + wire _T_1818 = _T_1815 | _T_1817; // @[el2_lsu_bus_buffer.scala 393:42] + wire _T_1819 = ~_T_1818; // @[el2_lsu_bus_buffer.scala 392:72] + wire _T_1820 = _T_1810 & _T_1819; // @[el2_lsu_bus_buffer.scala 392:70] + wire [1:0] _T_1821 = _T_1820 ? 2'h3 : 2'h0; // @[Mux.scala 98:16] + wire [1:0] _T_1822 = _T_1809 ? 2'h2 : _T_1821; // @[Mux.scala 98:16] + wire [1:0] _T_1823 = _T_1798 ? 2'h1 : _T_1822; // @[Mux.scala 98:16] + wire [1:0] WrPtr0_m = _T_1787 ? 2'h0 : _T_1823; // @[Mux.scala 98:16] + wire _T_1828 = WrPtr0_m == 2'h0; // @[el2_lsu_bus_buffer.scala 396:33] + wire _T_1829 = io_lsu_busreq_m & _T_1828; // @[el2_lsu_bus_buffer.scala 396:22] + wire _T_1830 = _T_1779 | _T_1829; // @[el2_lsu_bus_buffer.scala 395:106] + wire _T_1832 = io_lsu_busreq_r & _T_1780; // @[el2_lsu_bus_buffer.scala 396:61] + wire _T_1833 = _T_1830 | _T_1832; // @[el2_lsu_bus_buffer.scala 396:42] + wire _T_1836 = _T_1833 | _T_1784; // @[el2_lsu_bus_buffer.scala 396:83] + wire _T_1837 = ~_T_1836; // @[el2_lsu_bus_buffer.scala 395:72] + wire _T_1838 = _T_1777 & _T_1837; // @[el2_lsu_bus_buffer.scala 395:70] + wire _T_1842 = WrPtr0_m == 2'h1; // @[el2_lsu_bus_buffer.scala 396:33] + wire _T_1843 = io_lsu_busreq_m & _T_1842; // @[el2_lsu_bus_buffer.scala 396:22] + wire _T_1844 = _T_1790 | _T_1843; // @[el2_lsu_bus_buffer.scala 395:106] + wire _T_1846 = io_lsu_busreq_r & _T_1791; // @[el2_lsu_bus_buffer.scala 396:61] + wire _T_1847 = _T_1844 | _T_1846; // @[el2_lsu_bus_buffer.scala 396:42] + wire _T_1850 = _T_1847 | _T_1795; // @[el2_lsu_bus_buffer.scala 396:83] + wire _T_1851 = ~_T_1850; // @[el2_lsu_bus_buffer.scala 395:72] + wire _T_1852 = _T_1788 & _T_1851; // @[el2_lsu_bus_buffer.scala 395:70] + wire _T_1856 = WrPtr0_m == 2'h2; // @[el2_lsu_bus_buffer.scala 396:33] + wire _T_1857 = io_lsu_busreq_m & _T_1856; // @[el2_lsu_bus_buffer.scala 396:22] + wire _T_1858 = _T_1801 | _T_1857; // @[el2_lsu_bus_buffer.scala 395:106] + wire _T_1860 = io_lsu_busreq_r & _T_1802; // @[el2_lsu_bus_buffer.scala 396:61] + wire _T_1861 = _T_1858 | _T_1860; // @[el2_lsu_bus_buffer.scala 396:42] + wire _T_1864 = _T_1861 | _T_1806; // @[el2_lsu_bus_buffer.scala 396:83] + wire _T_1865 = ~_T_1864; // @[el2_lsu_bus_buffer.scala 395:72] + wire _T_1866 = _T_1799 & _T_1865; // @[el2_lsu_bus_buffer.scala 395:70] + wire _T_1870 = WrPtr0_m == 2'h3; // @[el2_lsu_bus_buffer.scala 396:33] + wire _T_1871 = io_lsu_busreq_m & _T_1870; // @[el2_lsu_bus_buffer.scala 396:22] + wire _T_1872 = _T_1812 | _T_1871; // @[el2_lsu_bus_buffer.scala 395:106] + wire _T_1874 = io_lsu_busreq_r & _T_1813; // @[el2_lsu_bus_buffer.scala 396:61] + wire _T_1875 = _T_1872 | _T_1874; // @[el2_lsu_bus_buffer.scala 396:42] + wire _T_1878 = _T_1875 | _T_1817; // @[el2_lsu_bus_buffer.scala 396:83] + wire _T_1879 = ~_T_1878; // @[el2_lsu_bus_buffer.scala 395:72] + wire _T_1880 = _T_1810 & _T_1879; // @[el2_lsu_bus_buffer.scala 395:70] + reg [3:0] buf_rspageQ_0; // @[el2_lsu_bus_buffer.scala 516:63] + wire _T_2596 = buf_state_3 == 3'h5; // @[el2_lsu_bus_buffer.scala 430:104] + wire _T_2597 = buf_rspageQ_0[3] & _T_2596; // @[el2_lsu_bus_buffer.scala 430:89] + wire _T_2593 = buf_state_2 == 3'h5; // @[el2_lsu_bus_buffer.scala 430:104] + wire _T_2594 = buf_rspageQ_0[2] & _T_2593; // @[el2_lsu_bus_buffer.scala 430:89] + wire _T_2590 = buf_state_1 == 3'h5; // @[el2_lsu_bus_buffer.scala 430:104] + wire _T_2591 = buf_rspageQ_0[1] & _T_2590; // @[el2_lsu_bus_buffer.scala 430:89] + wire _T_2587 = buf_state_0 == 3'h5; // @[el2_lsu_bus_buffer.scala 430:104] + wire _T_2588 = buf_rspageQ_0[0] & _T_2587; // @[el2_lsu_bus_buffer.scala 430:89] + wire [3:0] buf_rsp_pickage_0 = {_T_2597,_T_2594,_T_2591,_T_2588}; // @[Cat.scala 29:58] + wire _T_1956 = |buf_rsp_pickage_0; // @[el2_lsu_bus_buffer.scala 404:65] + wire _T_1957 = ~_T_1956; // @[el2_lsu_bus_buffer.scala 404:44] + wire _T_1959 = _T_1957 & _T_2587; // @[el2_lsu_bus_buffer.scala 404:70] + reg [3:0] buf_rspageQ_1; // @[el2_lsu_bus_buffer.scala 516:63] + wire _T_2612 = buf_rspageQ_1[3] & _T_2596; // @[el2_lsu_bus_buffer.scala 430:89] + wire _T_2609 = buf_rspageQ_1[2] & _T_2593; // @[el2_lsu_bus_buffer.scala 430:89] + wire _T_2606 = buf_rspageQ_1[1] & _T_2590; // @[el2_lsu_bus_buffer.scala 430:89] + wire _T_2603 = buf_rspageQ_1[0] & _T_2587; // @[el2_lsu_bus_buffer.scala 430:89] + wire [3:0] buf_rsp_pickage_1 = {_T_2612,_T_2609,_T_2606,_T_2603}; // @[Cat.scala 29:58] + wire _T_1960 = |buf_rsp_pickage_1; // @[el2_lsu_bus_buffer.scala 404:65] + wire _T_1961 = ~_T_1960; // @[el2_lsu_bus_buffer.scala 404:44] + wire _T_1963 = _T_1961 & _T_2590; // @[el2_lsu_bus_buffer.scala 404:70] + reg [3:0] buf_rspageQ_2; // @[el2_lsu_bus_buffer.scala 516:63] + wire _T_2627 = buf_rspageQ_2[3] & _T_2596; // @[el2_lsu_bus_buffer.scala 430:89] + wire _T_2624 = buf_rspageQ_2[2] & _T_2593; // @[el2_lsu_bus_buffer.scala 430:89] + wire _T_2621 = buf_rspageQ_2[1] & _T_2590; // @[el2_lsu_bus_buffer.scala 430:89] + wire _T_2618 = buf_rspageQ_2[0] & _T_2587; // @[el2_lsu_bus_buffer.scala 430:89] + wire [3:0] buf_rsp_pickage_2 = {_T_2627,_T_2624,_T_2621,_T_2618}; // @[Cat.scala 29:58] + wire _T_1964 = |buf_rsp_pickage_2; // @[el2_lsu_bus_buffer.scala 404:65] + wire _T_1965 = ~_T_1964; // @[el2_lsu_bus_buffer.scala 404:44] + wire _T_1967 = _T_1965 & _T_2593; // @[el2_lsu_bus_buffer.scala 404:70] + reg [3:0] buf_rspageQ_3; // @[el2_lsu_bus_buffer.scala 516:63] + wire _T_2642 = buf_rspageQ_3[3] & _T_2596; // @[el2_lsu_bus_buffer.scala 430:89] + wire _T_2639 = buf_rspageQ_3[2] & _T_2593; // @[el2_lsu_bus_buffer.scala 430:89] + wire _T_2636 = buf_rspageQ_3[1] & _T_2590; // @[el2_lsu_bus_buffer.scala 430:89] + wire _T_2633 = buf_rspageQ_3[0] & _T_2587; // @[el2_lsu_bus_buffer.scala 430:89] + wire [3:0] buf_rsp_pickage_3 = {_T_2642,_T_2639,_T_2636,_T_2633}; // @[Cat.scala 29:58] + wire _T_1968 = |buf_rsp_pickage_3; // @[el2_lsu_bus_buffer.scala 404:65] + wire _T_1969 = ~_T_1968; // @[el2_lsu_bus_buffer.scala 404:44] + wire _T_1971 = _T_1969 & _T_2596; // @[el2_lsu_bus_buffer.scala 404:70] + wire [3:0] RspPtrDec = {_T_1971,_T_1967,_T_1963,_T_1959}; // @[Cat.scala 29:58] + wire [1:0] _T_1992 = RspPtrDec[2] ? 2'h2 : 2'h3; // @[Mux.scala 47:69] + wire [1:0] _T_1993 = RspPtrDec[1] ? 2'h1 : _T_1992; // @[Mux.scala 47:69] + wire [1:0] RspPtr = RspPtrDec[0] ? 2'h0 : _T_1993; // @[Mux.scala 47:69] + wire _T_3382 = ibuf_byp | io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 459:77] + wire _T_3383 = ~ibuf_merge_en; // @[el2_lsu_bus_buffer.scala 459:97] + wire _T_3384 = _T_3382 & _T_3383; // @[el2_lsu_bus_buffer.scala 459:95] + wire _T_3385 = 2'h0 == WrPtr0_r; // @[el2_lsu_bus_buffer.scala 459:117] + wire _T_3386 = _T_3384 & _T_3385; // @[el2_lsu_bus_buffer.scala 459:112] + wire _T_3387 = ibuf_byp & io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 459:144] + wire _T_3388 = 2'h0 == WrPtr1_r; // @[el2_lsu_bus_buffer.scala 459:166] + wire _T_3389 = _T_3387 & _T_3388; // @[el2_lsu_bus_buffer.scala 459:161] + wire _T_3390 = _T_3386 | _T_3389; // @[el2_lsu_bus_buffer.scala 459:132] + wire _T_3391 = _T_766 & _T_3390; // @[el2_lsu_bus_buffer.scala 459:63] + wire _T_3392 = 2'h0 == ibuf_tag; // @[el2_lsu_bus_buffer.scala 459:206] + wire _T_3393 = ibuf_drain_vld & _T_3392; // @[el2_lsu_bus_buffer.scala 459:201] + wire _T_3394 = _T_3391 | _T_3393; // @[el2_lsu_bus_buffer.scala 459:183] + wire _T_3404 = io_lsu_bus_clk_en | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 466:46] + wire _T_3439 = 3'h3 == buf_state_0; // @[Conditional.scala 37:30] + wire bus_rsp_write = io_lsu_axi_bvalid & io_lsu_axi_bready; // @[el2_lsu_bus_buffer.scala 574:38] + wire _T_3484 = io_lsu_axi_bid == 3'h0; // @[el2_lsu_bus_buffer.scala 484:73] + wire _T_3485 = bus_rsp_write & _T_3484; // @[el2_lsu_bus_buffer.scala 484:52] + wire _T_3486 = io_lsu_axi_rid == 3'h0; // @[el2_lsu_bus_buffer.scala 485:46] + reg _T_4157; // @[Reg.scala 27:20] + reg _T_4155; // @[Reg.scala 27:20] + reg _T_4153; // @[Reg.scala 27:20] + reg _T_4151; // @[Reg.scala 27:20] + wire [3:0] buf_ldfwd = {_T_4157,_T_4155,_T_4153,_T_4151}; // @[Cat.scala 29:58] + reg [1:0] buf_ldfwdtag_0; // @[Reg.scala 27:20] + wire [2:0] _GEN_387 = {{1'd0}, buf_ldfwdtag_0}; // @[el2_lsu_bus_buffer.scala 486:47] + wire _T_3488 = io_lsu_axi_rid == _GEN_387; // @[el2_lsu_bus_buffer.scala 486:47] + wire _T_3489 = buf_ldfwd[0] & _T_3488; // @[el2_lsu_bus_buffer.scala 486:27] + wire _T_3490 = _T_3486 | _T_3489; // @[el2_lsu_bus_buffer.scala 485:77] + wire _T_3491 = buf_dual_0 & buf_dualhi_0; // @[el2_lsu_bus_buffer.scala 487:26] + wire _T_3494 = _T_3491 & _T_1129; // @[el2_lsu_bus_buffer.scala 487:42] + wire _T_3495 = _T_3494 & buf_samedw_0; // @[el2_lsu_bus_buffer.scala 487:58] + reg [1:0] buf_dualtag_0; // @[Reg.scala 27:20] + wire [2:0] _GEN_388 = {{1'd0}, buf_dualtag_0}; // @[el2_lsu_bus_buffer.scala 487:94] + wire _T_3496 = io_lsu_axi_rid == _GEN_388; // @[el2_lsu_bus_buffer.scala 487:94] + wire _T_3497 = _T_3495 & _T_3496; // @[el2_lsu_bus_buffer.scala 487:74] + wire _T_3498 = _T_3490 | _T_3497; // @[el2_lsu_bus_buffer.scala 486:71] + wire _T_3499 = bus_rsp_read & _T_3498; // @[el2_lsu_bus_buffer.scala 485:25] + wire _T_3500 = _T_3485 | _T_3499; // @[el2_lsu_bus_buffer.scala 484:105] + wire _GEN_42 = _T_3439 & _T_3500; // @[Conditional.scala 39:67] + wire _GEN_61 = _T_3405 ? 1'h0 : _GEN_42; // @[Conditional.scala 39:67] + wire _GEN_73 = _T_3401 ? 1'h0 : _GEN_61; // @[Conditional.scala 39:67] + wire buf_resp_state_bus_en_0 = _T_3378 ? 1'h0 : _GEN_73; // @[Conditional.scala 40:58] + wire _T_3526 = 3'h4 == buf_state_0; // @[Conditional.scala 37:30] + wire [3:0] _T_3536 = buf_ldfwd >> buf_dualtag_0; // @[el2_lsu_bus_buffer.scala 499:21] + reg [1:0] buf_ldfwdtag_3; // @[Reg.scala 27:20] + reg [1:0] buf_ldfwdtag_2; // @[Reg.scala 27:20] + reg [1:0] buf_ldfwdtag_1; // @[Reg.scala 27:20] + wire [1:0] _GEN_23 = 2'h1 == buf_dualtag_0 ? buf_ldfwdtag_1 : buf_ldfwdtag_0; // @[el2_lsu_bus_buffer.scala 499:58] + wire [1:0] _GEN_24 = 2'h2 == buf_dualtag_0 ? buf_ldfwdtag_2 : _GEN_23; // @[el2_lsu_bus_buffer.scala 499:58] + wire [1:0] _GEN_25 = 2'h3 == buf_dualtag_0 ? buf_ldfwdtag_3 : _GEN_24; // @[el2_lsu_bus_buffer.scala 499:58] + wire [2:0] _GEN_390 = {{1'd0}, _GEN_25}; // @[el2_lsu_bus_buffer.scala 499:58] + wire _T_3538 = io_lsu_axi_rid == _GEN_390; // @[el2_lsu_bus_buffer.scala 499:58] + wire _T_3539 = _T_3536[0] & _T_3538; // @[el2_lsu_bus_buffer.scala 499:38] + wire _T_3540 = _T_3496 | _T_3539; // @[el2_lsu_bus_buffer.scala 498:95] + wire _T_3541 = bus_rsp_read & _T_3540; // @[el2_lsu_bus_buffer.scala 498:45] + wire _GEN_36 = _T_3526 & _T_3541; // @[Conditional.scala 39:67] + wire _GEN_43 = _T_3439 ? buf_resp_state_bus_en_0 : _GEN_36; // @[Conditional.scala 39:67] + wire _GEN_53 = _T_3405 ? buf_cmd_state_bus_en_0 : _GEN_43; // @[Conditional.scala 39:67] + wire _GEN_66 = _T_3401 ? 1'h0 : _GEN_53; // @[Conditional.scala 39:67] + wire buf_state_bus_en_0 = _T_3378 ? 1'h0 : _GEN_66; // @[Conditional.scala 40:58] + wire _T_3418 = buf_state_bus_en_0 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 472:49] + wire _T_3419 = _T_3418 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 472:70] + wire _T_3544 = 3'h5 == buf_state_0; // @[Conditional.scala 37:30] + wire _T_3547 = RspPtr == 2'h0; // @[el2_lsu_bus_buffer.scala 504:37] + wire _T_3548 = buf_dualtag_0 == RspPtr; // @[el2_lsu_bus_buffer.scala 504:98] + wire _T_3549 = buf_dual_0 & _T_3548; // @[el2_lsu_bus_buffer.scala 504:80] + wire _T_3550 = _T_3547 | _T_3549; // @[el2_lsu_bus_buffer.scala 504:65] + wire _T_3551 = _T_3550 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 504:112] + wire _T_3552 = 3'h6 == buf_state_0; // @[Conditional.scala 37:30] + wire _GEN_31 = _T_3544 ? _T_3551 : _T_3552; // @[Conditional.scala 39:67] + wire _GEN_37 = _T_3526 ? _T_3419 : _GEN_31; // @[Conditional.scala 39:67] + wire _GEN_44 = _T_3439 ? _T_3419 : _GEN_37; // @[Conditional.scala 39:67] + wire _GEN_54 = _T_3405 ? _T_3419 : _GEN_44; // @[Conditional.scala 39:67] + wire _GEN_64 = _T_3401 ? _T_3404 : _GEN_54; // @[Conditional.scala 39:67] + wire buf_state_en_0 = _T_3378 ? _T_3394 : _GEN_64; // @[Conditional.scala 40:58] + wire _T_1995 = _T_1777 & buf_state_en_0; // @[el2_lsu_bus_buffer.scala 422:94] + wire _T_1996 = buf_state_0 == 3'h1; // @[el2_lsu_bus_buffer.scala 423:20] + wire _T_1999 = _T_2460 & _T_4271; // @[el2_lsu_bus_buffer.scala 423:57] + wire _T_2000 = _T_1996 | _T_1999; // @[el2_lsu_bus_buffer.scala 423:31] + wire _T_2001 = ibuf_drain_vld & io_lsu_busreq_r; // @[el2_lsu_bus_buffer.scala 424:23] + wire _T_2003 = _T_2001 & _T_3382; // @[el2_lsu_bus_buffer.scala 424:41] + wire _T_2005 = _T_2003 & _T_1780; // @[el2_lsu_bus_buffer.scala 424:71] + wire _T_2007 = _T_2005 & _T_1778; // @[el2_lsu_bus_buffer.scala 424:92] + wire _T_2008 = _T_2000 | _T_2007; // @[el2_lsu_bus_buffer.scala 423:86] + wire _T_2009 = ibuf_byp & io_lsu_busreq_r; // @[el2_lsu_bus_buffer.scala 425:17] + wire _T_2010 = _T_2009 & io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 425:35] + wire _T_2012 = _T_2010 & _T_1783; // @[el2_lsu_bus_buffer.scala 425:52] + wire _T_2014 = _T_2012 & _T_1780; // @[el2_lsu_bus_buffer.scala 425:73] + wire _T_2015 = _T_2008 | _T_2014; // @[el2_lsu_bus_buffer.scala 424:114] + wire _T_2016 = _T_1995 & _T_2015; // @[el2_lsu_bus_buffer.scala 422:113] + wire _T_2018 = _T_2016 | buf_age_0[0]; // @[el2_lsu_bus_buffer.scala 425:97] + wire _T_2021 = buf_state_1 == 3'h1; // @[el2_lsu_bus_buffer.scala 423:20] + wire _T_2024 = _T_2464 & _T_4277; // @[el2_lsu_bus_buffer.scala 423:57] + wire _T_2025 = _T_2021 | _T_2024; // @[el2_lsu_bus_buffer.scala 423:31] + wire _T_2032 = _T_2005 & _T_1789; // @[el2_lsu_bus_buffer.scala 424:92] + wire _T_2033 = _T_2025 | _T_2032; // @[el2_lsu_bus_buffer.scala 423:86] + wire _T_2039 = _T_2012 & _T_1791; // @[el2_lsu_bus_buffer.scala 425:73] + wire _T_2040 = _T_2033 | _T_2039; // @[el2_lsu_bus_buffer.scala 424:114] + wire _T_2041 = _T_1995 & _T_2040; // @[el2_lsu_bus_buffer.scala 422:113] + wire _T_2043 = _T_2041 | buf_age_0[1]; // @[el2_lsu_bus_buffer.scala 425:97] + wire _T_2046 = buf_state_2 == 3'h1; // @[el2_lsu_bus_buffer.scala 423:20] + wire _T_2049 = _T_2468 & _T_4283; // @[el2_lsu_bus_buffer.scala 423:57] + wire _T_2050 = _T_2046 | _T_2049; // @[el2_lsu_bus_buffer.scala 423:31] + wire _T_2057 = _T_2005 & _T_1800; // @[el2_lsu_bus_buffer.scala 424:92] + wire _T_2058 = _T_2050 | _T_2057; // @[el2_lsu_bus_buffer.scala 423:86] + wire _T_2064 = _T_2012 & _T_1802; // @[el2_lsu_bus_buffer.scala 425:73] + wire _T_2065 = _T_2058 | _T_2064; // @[el2_lsu_bus_buffer.scala 424:114] + wire _T_2066 = _T_1995 & _T_2065; // @[el2_lsu_bus_buffer.scala 422:113] + wire _T_2068 = _T_2066 | buf_age_0[2]; // @[el2_lsu_bus_buffer.scala 425:97] + wire _T_2071 = buf_state_3 == 3'h1; // @[el2_lsu_bus_buffer.scala 423:20] + wire _T_2074 = _T_2472 & _T_4289; // @[el2_lsu_bus_buffer.scala 423:57] + wire _T_2075 = _T_2071 | _T_2074; // @[el2_lsu_bus_buffer.scala 423:31] + wire _T_2082 = _T_2005 & _T_1811; // @[el2_lsu_bus_buffer.scala 424:92] + wire _T_2083 = _T_2075 | _T_2082; // @[el2_lsu_bus_buffer.scala 423:86] + wire _T_2089 = _T_2012 & _T_1813; // @[el2_lsu_bus_buffer.scala 425:73] + wire _T_2090 = _T_2083 | _T_2089; // @[el2_lsu_bus_buffer.scala 424:114] + wire _T_2091 = _T_1995 & _T_2090; // @[el2_lsu_bus_buffer.scala 422:113] + wire _T_2093 = _T_2091 | buf_age_0[3]; // @[el2_lsu_bus_buffer.scala 425:97] + wire [2:0] _T_2095 = {_T_2093,_T_2068,_T_2043}; // @[Cat.scala 29:58] + wire _T_3578 = 2'h1 == WrPtr0_r; // @[el2_lsu_bus_buffer.scala 459:117] + wire _T_3579 = _T_3384 & _T_3578; // @[el2_lsu_bus_buffer.scala 459:112] + wire _T_3581 = 2'h1 == WrPtr1_r; // @[el2_lsu_bus_buffer.scala 459:166] + wire _T_3582 = _T_3387 & _T_3581; // @[el2_lsu_bus_buffer.scala 459:161] + wire _T_3583 = _T_3579 | _T_3582; // @[el2_lsu_bus_buffer.scala 459:132] + wire _T_3584 = _T_766 & _T_3583; // @[el2_lsu_bus_buffer.scala 459:63] + wire _T_3585 = 2'h1 == ibuf_tag; // @[el2_lsu_bus_buffer.scala 459:206] + wire _T_3586 = ibuf_drain_vld & _T_3585; // @[el2_lsu_bus_buffer.scala 459:201] + wire _T_3587 = _T_3584 | _T_3586; // @[el2_lsu_bus_buffer.scala 459:183] + wire _T_3632 = 3'h3 == buf_state_1; // @[Conditional.scala 37:30] + wire _T_3677 = io_lsu_axi_bid == 3'h1; // @[el2_lsu_bus_buffer.scala 484:73] + wire _T_3678 = bus_rsp_write & _T_3677; // @[el2_lsu_bus_buffer.scala 484:52] + wire _T_3679 = io_lsu_axi_rid == 3'h1; // @[el2_lsu_bus_buffer.scala 485:46] + wire [2:0] _GEN_391 = {{1'd0}, buf_ldfwdtag_1}; // @[el2_lsu_bus_buffer.scala 486:47] + wire _T_3681 = io_lsu_axi_rid == _GEN_391; // @[el2_lsu_bus_buffer.scala 486:47] + wire _T_3682 = buf_ldfwd[1] & _T_3681; // @[el2_lsu_bus_buffer.scala 486:27] + wire _T_3683 = _T_3679 | _T_3682; // @[el2_lsu_bus_buffer.scala 485:77] + wire _T_3684 = buf_dual_1 & buf_dualhi_1; // @[el2_lsu_bus_buffer.scala 487:26] + wire _T_3686 = ~buf_write[1]; // @[el2_lsu_bus_buffer.scala 487:44] + wire _T_3687 = _T_3684 & _T_3686; // @[el2_lsu_bus_buffer.scala 487:42] + wire _T_3688 = _T_3687 & buf_samedw_1; // @[el2_lsu_bus_buffer.scala 487:58] + reg [1:0] buf_dualtag_1; // @[Reg.scala 27:20] + wire [2:0] _GEN_392 = {{1'd0}, buf_dualtag_1}; // @[el2_lsu_bus_buffer.scala 487:94] + wire _T_3689 = io_lsu_axi_rid == _GEN_392; // @[el2_lsu_bus_buffer.scala 487:94] + wire _T_3690 = _T_3688 & _T_3689; // @[el2_lsu_bus_buffer.scala 487:74] + wire _T_3691 = _T_3683 | _T_3690; // @[el2_lsu_bus_buffer.scala 486:71] + wire _T_3692 = bus_rsp_read & _T_3691; // @[el2_lsu_bus_buffer.scala 485:25] + wire _T_3693 = _T_3678 | _T_3692; // @[el2_lsu_bus_buffer.scala 484:105] + wire _GEN_118 = _T_3632 & _T_3693; // @[Conditional.scala 39:67] + wire _GEN_137 = _T_3598 ? 1'h0 : _GEN_118; // @[Conditional.scala 39:67] + wire _GEN_149 = _T_3594 ? 1'h0 : _GEN_137; // @[Conditional.scala 39:67] + wire buf_resp_state_bus_en_1 = _T_3571 ? 1'h0 : _GEN_149; // @[Conditional.scala 40:58] + wire _T_3719 = 3'h4 == buf_state_1; // @[Conditional.scala 37:30] + wire [3:0] _T_3729 = buf_ldfwd >> buf_dualtag_1; // @[el2_lsu_bus_buffer.scala 499:21] + wire [1:0] _GEN_99 = 2'h1 == buf_dualtag_1 ? buf_ldfwdtag_1 : buf_ldfwdtag_0; // @[el2_lsu_bus_buffer.scala 499:58] + wire [1:0] _GEN_100 = 2'h2 == buf_dualtag_1 ? buf_ldfwdtag_2 : _GEN_99; // @[el2_lsu_bus_buffer.scala 499:58] + wire [1:0] _GEN_101 = 2'h3 == buf_dualtag_1 ? buf_ldfwdtag_3 : _GEN_100; // @[el2_lsu_bus_buffer.scala 499:58] + wire [2:0] _GEN_394 = {{1'd0}, _GEN_101}; // @[el2_lsu_bus_buffer.scala 499:58] + wire _T_3731 = io_lsu_axi_rid == _GEN_394; // @[el2_lsu_bus_buffer.scala 499:58] + wire _T_3732 = _T_3729[0] & _T_3731; // @[el2_lsu_bus_buffer.scala 499:38] + wire _T_3733 = _T_3689 | _T_3732; // @[el2_lsu_bus_buffer.scala 498:95] + wire _T_3734 = bus_rsp_read & _T_3733; // @[el2_lsu_bus_buffer.scala 498:45] + wire _GEN_112 = _T_3719 & _T_3734; // @[Conditional.scala 39:67] + wire _GEN_119 = _T_3632 ? buf_resp_state_bus_en_1 : _GEN_112; // @[Conditional.scala 39:67] + wire _GEN_129 = _T_3598 ? buf_cmd_state_bus_en_1 : _GEN_119; // @[Conditional.scala 39:67] + wire _GEN_142 = _T_3594 ? 1'h0 : _GEN_129; // @[Conditional.scala 39:67] + wire buf_state_bus_en_1 = _T_3571 ? 1'h0 : _GEN_142; // @[Conditional.scala 40:58] + wire _T_3611 = buf_state_bus_en_1 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 472:49] + wire _T_3612 = _T_3611 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 472:70] + wire _T_3737 = 3'h5 == buf_state_1; // @[Conditional.scala 37:30] + wire _T_3740 = RspPtr == 2'h1; // @[el2_lsu_bus_buffer.scala 504:37] + wire _T_3741 = buf_dualtag_1 == RspPtr; // @[el2_lsu_bus_buffer.scala 504:98] + wire _T_3742 = buf_dual_1 & _T_3741; // @[el2_lsu_bus_buffer.scala 504:80] + wire _T_3743 = _T_3740 | _T_3742; // @[el2_lsu_bus_buffer.scala 504:65] + wire _T_3744 = _T_3743 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 504:112] + wire _T_3745 = 3'h6 == buf_state_1; // @[Conditional.scala 37:30] + wire _GEN_107 = _T_3737 ? _T_3744 : _T_3745; // @[Conditional.scala 39:67] + wire _GEN_113 = _T_3719 ? _T_3612 : _GEN_107; // @[Conditional.scala 39:67] + wire _GEN_120 = _T_3632 ? _T_3612 : _GEN_113; // @[Conditional.scala 39:67] + wire _GEN_130 = _T_3598 ? _T_3612 : _GEN_120; // @[Conditional.scala 39:67] + wire _GEN_140 = _T_3594 ? _T_3404 : _GEN_130; // @[Conditional.scala 39:67] + wire buf_state_en_1 = _T_3571 ? _T_3587 : _GEN_140; // @[Conditional.scala 40:58] + wire _T_2097 = _T_1788 & buf_state_en_1; // @[el2_lsu_bus_buffer.scala 422:94] + wire _T_2107 = _T_2003 & _T_1791; // @[el2_lsu_bus_buffer.scala 424:71] + wire _T_2109 = _T_2107 & _T_1778; // @[el2_lsu_bus_buffer.scala 424:92] + wire _T_2110 = _T_2000 | _T_2109; // @[el2_lsu_bus_buffer.scala 423:86] + wire _T_2114 = _T_2010 & _T_1794; // @[el2_lsu_bus_buffer.scala 425:52] + wire _T_2116 = _T_2114 & _T_1780; // @[el2_lsu_bus_buffer.scala 425:73] + wire _T_2117 = _T_2110 | _T_2116; // @[el2_lsu_bus_buffer.scala 424:114] + wire _T_2118 = _T_2097 & _T_2117; // @[el2_lsu_bus_buffer.scala 422:113] + wire _T_2120 = _T_2118 | buf_age_1[0]; // @[el2_lsu_bus_buffer.scala 425:97] + wire _T_2134 = _T_2107 & _T_1789; // @[el2_lsu_bus_buffer.scala 424:92] + wire _T_2135 = _T_2025 | _T_2134; // @[el2_lsu_bus_buffer.scala 423:86] + wire _T_2141 = _T_2114 & _T_1791; // @[el2_lsu_bus_buffer.scala 425:73] + wire _T_2142 = _T_2135 | _T_2141; // @[el2_lsu_bus_buffer.scala 424:114] + wire _T_2143 = _T_2097 & _T_2142; // @[el2_lsu_bus_buffer.scala 422:113] + wire _T_2145 = _T_2143 | buf_age_1[1]; // @[el2_lsu_bus_buffer.scala 425:97] + wire _T_2159 = _T_2107 & _T_1800; // @[el2_lsu_bus_buffer.scala 424:92] + wire _T_2160 = _T_2050 | _T_2159; // @[el2_lsu_bus_buffer.scala 423:86] + wire _T_2166 = _T_2114 & _T_1802; // @[el2_lsu_bus_buffer.scala 425:73] + wire _T_2167 = _T_2160 | _T_2166; // @[el2_lsu_bus_buffer.scala 424:114] + wire _T_2168 = _T_2097 & _T_2167; // @[el2_lsu_bus_buffer.scala 422:113] + wire _T_2170 = _T_2168 | buf_age_1[2]; // @[el2_lsu_bus_buffer.scala 425:97] + wire _T_2184 = _T_2107 & _T_1811; // @[el2_lsu_bus_buffer.scala 424:92] + wire _T_2185 = _T_2075 | _T_2184; // @[el2_lsu_bus_buffer.scala 423:86] + wire _T_2191 = _T_2114 & _T_1813; // @[el2_lsu_bus_buffer.scala 425:73] + wire _T_2192 = _T_2185 | _T_2191; // @[el2_lsu_bus_buffer.scala 424:114] + wire _T_2193 = _T_2097 & _T_2192; // @[el2_lsu_bus_buffer.scala 422:113] + wire _T_2195 = _T_2193 | buf_age_1[3]; // @[el2_lsu_bus_buffer.scala 425:97] + wire [2:0] _T_2197 = {_T_2195,_T_2170,_T_2145}; // @[Cat.scala 29:58] + wire _T_3771 = 2'h2 == WrPtr0_r; // @[el2_lsu_bus_buffer.scala 459:117] + wire _T_3772 = _T_3384 & _T_3771; // @[el2_lsu_bus_buffer.scala 459:112] + wire _T_3774 = 2'h2 == WrPtr1_r; // @[el2_lsu_bus_buffer.scala 459:166] + wire _T_3775 = _T_3387 & _T_3774; // @[el2_lsu_bus_buffer.scala 459:161] + wire _T_3776 = _T_3772 | _T_3775; // @[el2_lsu_bus_buffer.scala 459:132] + wire _T_3777 = _T_766 & _T_3776; // @[el2_lsu_bus_buffer.scala 459:63] + wire _T_3778 = 2'h2 == ibuf_tag; // @[el2_lsu_bus_buffer.scala 459:206] + wire _T_3779 = ibuf_drain_vld & _T_3778; // @[el2_lsu_bus_buffer.scala 459:201] + wire _T_3780 = _T_3777 | _T_3779; // @[el2_lsu_bus_buffer.scala 459:183] + wire _T_3825 = 3'h3 == buf_state_2; // @[Conditional.scala 37:30] + wire _T_3870 = io_lsu_axi_bid == 3'h2; // @[el2_lsu_bus_buffer.scala 484:73] + wire _T_3871 = bus_rsp_write & _T_3870; // @[el2_lsu_bus_buffer.scala 484:52] + wire _T_3872 = io_lsu_axi_rid == 3'h2; // @[el2_lsu_bus_buffer.scala 485:46] + wire [2:0] _GEN_395 = {{1'd0}, buf_ldfwdtag_2}; // @[el2_lsu_bus_buffer.scala 486:47] + wire _T_3874 = io_lsu_axi_rid == _GEN_395; // @[el2_lsu_bus_buffer.scala 486:47] + wire _T_3875 = buf_ldfwd[2] & _T_3874; // @[el2_lsu_bus_buffer.scala 486:27] + wire _T_3876 = _T_3872 | _T_3875; // @[el2_lsu_bus_buffer.scala 485:77] + wire _T_3877 = buf_dual_2 & buf_dualhi_2; // @[el2_lsu_bus_buffer.scala 487:26] + wire _T_3879 = ~buf_write[2]; // @[el2_lsu_bus_buffer.scala 487:44] + wire _T_3880 = _T_3877 & _T_3879; // @[el2_lsu_bus_buffer.scala 487:42] + wire _T_3881 = _T_3880 & buf_samedw_2; // @[el2_lsu_bus_buffer.scala 487:58] + reg [1:0] buf_dualtag_2; // @[Reg.scala 27:20] + wire [2:0] _GEN_396 = {{1'd0}, buf_dualtag_2}; // @[el2_lsu_bus_buffer.scala 487:94] + wire _T_3882 = io_lsu_axi_rid == _GEN_396; // @[el2_lsu_bus_buffer.scala 487:94] + wire _T_3883 = _T_3881 & _T_3882; // @[el2_lsu_bus_buffer.scala 487:74] + wire _T_3884 = _T_3876 | _T_3883; // @[el2_lsu_bus_buffer.scala 486:71] + wire _T_3885 = bus_rsp_read & _T_3884; // @[el2_lsu_bus_buffer.scala 485:25] + wire _T_3886 = _T_3871 | _T_3885; // @[el2_lsu_bus_buffer.scala 484:105] + wire _GEN_194 = _T_3825 & _T_3886; // @[Conditional.scala 39:67] + wire _GEN_213 = _T_3791 ? 1'h0 : _GEN_194; // @[Conditional.scala 39:67] + wire _GEN_225 = _T_3787 ? 1'h0 : _GEN_213; // @[Conditional.scala 39:67] + wire buf_resp_state_bus_en_2 = _T_3764 ? 1'h0 : _GEN_225; // @[Conditional.scala 40:58] + wire _T_3912 = 3'h4 == buf_state_2; // @[Conditional.scala 37:30] + wire [3:0] _T_3922 = buf_ldfwd >> buf_dualtag_2; // @[el2_lsu_bus_buffer.scala 499:21] + wire [1:0] _GEN_175 = 2'h1 == buf_dualtag_2 ? buf_ldfwdtag_1 : buf_ldfwdtag_0; // @[el2_lsu_bus_buffer.scala 499:58] + wire [1:0] _GEN_176 = 2'h2 == buf_dualtag_2 ? buf_ldfwdtag_2 : _GEN_175; // @[el2_lsu_bus_buffer.scala 499:58] + wire [1:0] _GEN_177 = 2'h3 == buf_dualtag_2 ? buf_ldfwdtag_3 : _GEN_176; // @[el2_lsu_bus_buffer.scala 499:58] + wire [2:0] _GEN_398 = {{1'd0}, _GEN_177}; // @[el2_lsu_bus_buffer.scala 499:58] + wire _T_3924 = io_lsu_axi_rid == _GEN_398; // @[el2_lsu_bus_buffer.scala 499:58] + wire _T_3925 = _T_3922[0] & _T_3924; // @[el2_lsu_bus_buffer.scala 499:38] + wire _T_3926 = _T_3882 | _T_3925; // @[el2_lsu_bus_buffer.scala 498:95] + wire _T_3927 = bus_rsp_read & _T_3926; // @[el2_lsu_bus_buffer.scala 498:45] + wire _GEN_188 = _T_3912 & _T_3927; // @[Conditional.scala 39:67] + wire _GEN_195 = _T_3825 ? buf_resp_state_bus_en_2 : _GEN_188; // @[Conditional.scala 39:67] + wire _GEN_205 = _T_3791 ? buf_cmd_state_bus_en_2 : _GEN_195; // @[Conditional.scala 39:67] + wire _GEN_218 = _T_3787 ? 1'h0 : _GEN_205; // @[Conditional.scala 39:67] + wire buf_state_bus_en_2 = _T_3764 ? 1'h0 : _GEN_218; // @[Conditional.scala 40:58] + wire _T_3804 = buf_state_bus_en_2 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 472:49] + wire _T_3805 = _T_3804 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 472:70] + wire _T_3930 = 3'h5 == buf_state_2; // @[Conditional.scala 37:30] + wire _T_3933 = RspPtr == 2'h2; // @[el2_lsu_bus_buffer.scala 504:37] + wire _T_3934 = buf_dualtag_2 == RspPtr; // @[el2_lsu_bus_buffer.scala 504:98] + wire _T_3935 = buf_dual_2 & _T_3934; // @[el2_lsu_bus_buffer.scala 504:80] + wire _T_3936 = _T_3933 | _T_3935; // @[el2_lsu_bus_buffer.scala 504:65] + wire _T_3937 = _T_3936 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 504:112] + wire _T_3938 = 3'h6 == buf_state_2; // @[Conditional.scala 37:30] + wire _GEN_183 = _T_3930 ? _T_3937 : _T_3938; // @[Conditional.scala 39:67] + wire _GEN_189 = _T_3912 ? _T_3805 : _GEN_183; // @[Conditional.scala 39:67] + wire _GEN_196 = _T_3825 ? _T_3805 : _GEN_189; // @[Conditional.scala 39:67] + wire _GEN_206 = _T_3791 ? _T_3805 : _GEN_196; // @[Conditional.scala 39:67] + wire _GEN_216 = _T_3787 ? _T_3404 : _GEN_206; // @[Conditional.scala 39:67] + wire buf_state_en_2 = _T_3764 ? _T_3780 : _GEN_216; // @[Conditional.scala 40:58] + wire _T_2199 = _T_1799 & buf_state_en_2; // @[el2_lsu_bus_buffer.scala 422:94] + wire _T_2209 = _T_2003 & _T_1802; // @[el2_lsu_bus_buffer.scala 424:71] + wire _T_2211 = _T_2209 & _T_1778; // @[el2_lsu_bus_buffer.scala 424:92] + wire _T_2212 = _T_2000 | _T_2211; // @[el2_lsu_bus_buffer.scala 423:86] + wire _T_2216 = _T_2010 & _T_1805; // @[el2_lsu_bus_buffer.scala 425:52] + wire _T_2218 = _T_2216 & _T_1780; // @[el2_lsu_bus_buffer.scala 425:73] + wire _T_2219 = _T_2212 | _T_2218; // @[el2_lsu_bus_buffer.scala 424:114] + wire _T_2220 = _T_2199 & _T_2219; // @[el2_lsu_bus_buffer.scala 422:113] + wire _T_2222 = _T_2220 | buf_age_2[0]; // @[el2_lsu_bus_buffer.scala 425:97] + wire _T_2236 = _T_2209 & _T_1789; // @[el2_lsu_bus_buffer.scala 424:92] + wire _T_2237 = _T_2025 | _T_2236; // @[el2_lsu_bus_buffer.scala 423:86] + wire _T_2243 = _T_2216 & _T_1791; // @[el2_lsu_bus_buffer.scala 425:73] + wire _T_2244 = _T_2237 | _T_2243; // @[el2_lsu_bus_buffer.scala 424:114] + wire _T_2245 = _T_2199 & _T_2244; // @[el2_lsu_bus_buffer.scala 422:113] + wire _T_2247 = _T_2245 | buf_age_2[1]; // @[el2_lsu_bus_buffer.scala 425:97] + wire _T_2261 = _T_2209 & _T_1800; // @[el2_lsu_bus_buffer.scala 424:92] + wire _T_2262 = _T_2050 | _T_2261; // @[el2_lsu_bus_buffer.scala 423:86] + wire _T_2268 = _T_2216 & _T_1802; // @[el2_lsu_bus_buffer.scala 425:73] + wire _T_2269 = _T_2262 | _T_2268; // @[el2_lsu_bus_buffer.scala 424:114] + wire _T_2270 = _T_2199 & _T_2269; // @[el2_lsu_bus_buffer.scala 422:113] + wire _T_2272 = _T_2270 | buf_age_2[2]; // @[el2_lsu_bus_buffer.scala 425:97] + wire _T_2286 = _T_2209 & _T_1811; // @[el2_lsu_bus_buffer.scala 424:92] + wire _T_2287 = _T_2075 | _T_2286; // @[el2_lsu_bus_buffer.scala 423:86] + wire _T_2293 = _T_2216 & _T_1813; // @[el2_lsu_bus_buffer.scala 425:73] + wire _T_2294 = _T_2287 | _T_2293; // @[el2_lsu_bus_buffer.scala 424:114] + wire _T_2295 = _T_2199 & _T_2294; // @[el2_lsu_bus_buffer.scala 422:113] + wire _T_2297 = _T_2295 | buf_age_2[3]; // @[el2_lsu_bus_buffer.scala 425:97] + wire [2:0] _T_2299 = {_T_2297,_T_2272,_T_2247}; // @[Cat.scala 29:58] + wire _T_3964 = 2'h3 == WrPtr0_r; // @[el2_lsu_bus_buffer.scala 459:117] + wire _T_3965 = _T_3384 & _T_3964; // @[el2_lsu_bus_buffer.scala 459:112] + wire _T_3967 = 2'h3 == WrPtr1_r; // @[el2_lsu_bus_buffer.scala 459:166] + wire _T_3968 = _T_3387 & _T_3967; // @[el2_lsu_bus_buffer.scala 459:161] + wire _T_3969 = _T_3965 | _T_3968; // @[el2_lsu_bus_buffer.scala 459:132] + wire _T_3970 = _T_766 & _T_3969; // @[el2_lsu_bus_buffer.scala 459:63] + wire _T_3971 = 2'h3 == ibuf_tag; // @[el2_lsu_bus_buffer.scala 459:206] + wire _T_3972 = ibuf_drain_vld & _T_3971; // @[el2_lsu_bus_buffer.scala 459:201] + wire _T_3973 = _T_3970 | _T_3972; // @[el2_lsu_bus_buffer.scala 459:183] + wire _T_4018 = 3'h3 == buf_state_3; // @[Conditional.scala 37:30] + wire _T_4063 = io_lsu_axi_bid == 3'h3; // @[el2_lsu_bus_buffer.scala 484:73] + wire _T_4064 = bus_rsp_write & _T_4063; // @[el2_lsu_bus_buffer.scala 484:52] + wire _T_4065 = io_lsu_axi_rid == 3'h3; // @[el2_lsu_bus_buffer.scala 485:46] + wire [2:0] _GEN_399 = {{1'd0}, buf_ldfwdtag_3}; // @[el2_lsu_bus_buffer.scala 486:47] + wire _T_4067 = io_lsu_axi_rid == _GEN_399; // @[el2_lsu_bus_buffer.scala 486:47] + wire _T_4068 = buf_ldfwd[3] & _T_4067; // @[el2_lsu_bus_buffer.scala 486:27] + wire _T_4069 = _T_4065 | _T_4068; // @[el2_lsu_bus_buffer.scala 485:77] + wire _T_4070 = buf_dual_3 & buf_dualhi_3; // @[el2_lsu_bus_buffer.scala 487:26] + wire _T_4072 = ~buf_write[3]; // @[el2_lsu_bus_buffer.scala 487:44] + wire _T_4073 = _T_4070 & _T_4072; // @[el2_lsu_bus_buffer.scala 487:42] + wire _T_4074 = _T_4073 & buf_samedw_3; // @[el2_lsu_bus_buffer.scala 487:58] + reg [1:0] buf_dualtag_3; // @[Reg.scala 27:20] + wire [2:0] _GEN_400 = {{1'd0}, buf_dualtag_3}; // @[el2_lsu_bus_buffer.scala 487:94] + wire _T_4075 = io_lsu_axi_rid == _GEN_400; // @[el2_lsu_bus_buffer.scala 487:94] + wire _T_4076 = _T_4074 & _T_4075; // @[el2_lsu_bus_buffer.scala 487:74] + wire _T_4077 = _T_4069 | _T_4076; // @[el2_lsu_bus_buffer.scala 486:71] + wire _T_4078 = bus_rsp_read & _T_4077; // @[el2_lsu_bus_buffer.scala 485:25] + wire _T_4079 = _T_4064 | _T_4078; // @[el2_lsu_bus_buffer.scala 484:105] + wire _GEN_270 = _T_4018 & _T_4079; // @[Conditional.scala 39:67] + wire _GEN_289 = _T_3984 ? 1'h0 : _GEN_270; // @[Conditional.scala 39:67] + wire _GEN_301 = _T_3980 ? 1'h0 : _GEN_289; // @[Conditional.scala 39:67] + wire buf_resp_state_bus_en_3 = _T_3957 ? 1'h0 : _GEN_301; // @[Conditional.scala 40:58] + wire _T_4105 = 3'h4 == buf_state_3; // @[Conditional.scala 37:30] + wire [3:0] _T_4115 = buf_ldfwd >> buf_dualtag_3; // @[el2_lsu_bus_buffer.scala 499:21] + wire [1:0] _GEN_251 = 2'h1 == buf_dualtag_3 ? buf_ldfwdtag_1 : buf_ldfwdtag_0; // @[el2_lsu_bus_buffer.scala 499:58] + wire [1:0] _GEN_252 = 2'h2 == buf_dualtag_3 ? buf_ldfwdtag_2 : _GEN_251; // @[el2_lsu_bus_buffer.scala 499:58] + wire [1:0] _GEN_253 = 2'h3 == buf_dualtag_3 ? buf_ldfwdtag_3 : _GEN_252; // @[el2_lsu_bus_buffer.scala 499:58] + wire [2:0] _GEN_402 = {{1'd0}, _GEN_253}; // @[el2_lsu_bus_buffer.scala 499:58] + wire _T_4117 = io_lsu_axi_rid == _GEN_402; // @[el2_lsu_bus_buffer.scala 499:58] + wire _T_4118 = _T_4115[0] & _T_4117; // @[el2_lsu_bus_buffer.scala 499:38] + wire _T_4119 = _T_4075 | _T_4118; // @[el2_lsu_bus_buffer.scala 498:95] + wire _T_4120 = bus_rsp_read & _T_4119; // @[el2_lsu_bus_buffer.scala 498:45] + wire _GEN_264 = _T_4105 & _T_4120; // @[Conditional.scala 39:67] + wire _GEN_271 = _T_4018 ? buf_resp_state_bus_en_3 : _GEN_264; // @[Conditional.scala 39:67] + wire _GEN_281 = _T_3984 ? buf_cmd_state_bus_en_3 : _GEN_271; // @[Conditional.scala 39:67] + wire _GEN_294 = _T_3980 ? 1'h0 : _GEN_281; // @[Conditional.scala 39:67] + wire buf_state_bus_en_3 = _T_3957 ? 1'h0 : _GEN_294; // @[Conditional.scala 40:58] + wire _T_3997 = buf_state_bus_en_3 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 472:49] + wire _T_3998 = _T_3997 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 472:70] + wire _T_4123 = 3'h5 == buf_state_3; // @[Conditional.scala 37:30] + wire _T_4126 = RspPtr == 2'h3; // @[el2_lsu_bus_buffer.scala 504:37] + wire _T_4127 = buf_dualtag_3 == RspPtr; // @[el2_lsu_bus_buffer.scala 504:98] + wire _T_4128 = buf_dual_3 & _T_4127; // @[el2_lsu_bus_buffer.scala 504:80] + wire _T_4129 = _T_4126 | _T_4128; // @[el2_lsu_bus_buffer.scala 504:65] + wire _T_4130 = _T_4129 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 504:112] + wire _T_4131 = 3'h6 == buf_state_3; // @[Conditional.scala 37:30] + wire _GEN_259 = _T_4123 ? _T_4130 : _T_4131; // @[Conditional.scala 39:67] + wire _GEN_265 = _T_4105 ? _T_3998 : _GEN_259; // @[Conditional.scala 39:67] + wire _GEN_272 = _T_4018 ? _T_3998 : _GEN_265; // @[Conditional.scala 39:67] + wire _GEN_282 = _T_3984 ? _T_3998 : _GEN_272; // @[Conditional.scala 39:67] + wire _GEN_292 = _T_3980 ? _T_3404 : _GEN_282; // @[Conditional.scala 39:67] + wire buf_state_en_3 = _T_3957 ? _T_3973 : _GEN_292; // @[Conditional.scala 40:58] + wire _T_2301 = _T_1810 & buf_state_en_3; // @[el2_lsu_bus_buffer.scala 422:94] + wire _T_2311 = _T_2003 & _T_1813; // @[el2_lsu_bus_buffer.scala 424:71] + wire _T_2313 = _T_2311 & _T_1778; // @[el2_lsu_bus_buffer.scala 424:92] + wire _T_2314 = _T_2000 | _T_2313; // @[el2_lsu_bus_buffer.scala 423:86] + wire _T_2318 = _T_2010 & _T_1816; // @[el2_lsu_bus_buffer.scala 425:52] + wire _T_2320 = _T_2318 & _T_1780; // @[el2_lsu_bus_buffer.scala 425:73] + wire _T_2321 = _T_2314 | _T_2320; // @[el2_lsu_bus_buffer.scala 424:114] + wire _T_2322 = _T_2301 & _T_2321; // @[el2_lsu_bus_buffer.scala 422:113] + wire _T_2324 = _T_2322 | buf_age_3[0]; // @[el2_lsu_bus_buffer.scala 425:97] + wire _T_2338 = _T_2311 & _T_1789; // @[el2_lsu_bus_buffer.scala 424:92] + wire _T_2339 = _T_2025 | _T_2338; // @[el2_lsu_bus_buffer.scala 423:86] + wire _T_2345 = _T_2318 & _T_1791; // @[el2_lsu_bus_buffer.scala 425:73] + wire _T_2346 = _T_2339 | _T_2345; // @[el2_lsu_bus_buffer.scala 424:114] + wire _T_2347 = _T_2301 & _T_2346; // @[el2_lsu_bus_buffer.scala 422:113] + wire _T_2349 = _T_2347 | buf_age_3[1]; // @[el2_lsu_bus_buffer.scala 425:97] + wire _T_2363 = _T_2311 & _T_1800; // @[el2_lsu_bus_buffer.scala 424:92] + wire _T_2364 = _T_2050 | _T_2363; // @[el2_lsu_bus_buffer.scala 423:86] + wire _T_2370 = _T_2318 & _T_1802; // @[el2_lsu_bus_buffer.scala 425:73] + wire _T_2371 = _T_2364 | _T_2370; // @[el2_lsu_bus_buffer.scala 424:114] + wire _T_2372 = _T_2301 & _T_2371; // @[el2_lsu_bus_buffer.scala 422:113] + wire _T_2374 = _T_2372 | buf_age_3[2]; // @[el2_lsu_bus_buffer.scala 425:97] + wire _T_2388 = _T_2311 & _T_1811; // @[el2_lsu_bus_buffer.scala 424:92] + wire _T_2389 = _T_2075 | _T_2388; // @[el2_lsu_bus_buffer.scala 423:86] + wire _T_2395 = _T_2318 & _T_1813; // @[el2_lsu_bus_buffer.scala 425:73] + wire _T_2396 = _T_2389 | _T_2395; // @[el2_lsu_bus_buffer.scala 424:114] + wire _T_2397 = _T_2301 & _T_2396; // @[el2_lsu_bus_buffer.scala 422:113] + wire _T_2399 = _T_2397 | buf_age_3[3]; // @[el2_lsu_bus_buffer.scala 425:97] + wire [2:0] _T_2401 = {_T_2399,_T_2374,_T_2349}; // @[Cat.scala 29:58] + wire _T_2649 = buf_state_0 == 3'h6; // @[el2_lsu_bus_buffer.scala 433:49] + wire _T_2650 = _T_1777 | _T_2649; // @[el2_lsu_bus_buffer.scala 433:34] + wire _T_2651 = ~_T_2650; // @[el2_lsu_bus_buffer.scala 433:8] + wire _T_2659 = _T_2651 | _T_2007; // @[el2_lsu_bus_buffer.scala 433:61] + wire _T_2666 = _T_2659 | _T_2014; // @[el2_lsu_bus_buffer.scala 434:112] + wire _T_2667 = _T_1995 & _T_2666; // @[el2_lsu_bus_buffer.scala 432:114] + wire _T_2671 = buf_state_1 == 3'h6; // @[el2_lsu_bus_buffer.scala 433:49] + wire _T_2672 = _T_1788 | _T_2671; // @[el2_lsu_bus_buffer.scala 433:34] + wire _T_2673 = ~_T_2672; // @[el2_lsu_bus_buffer.scala 433:8] + wire _T_2681 = _T_2673 | _T_2032; // @[el2_lsu_bus_buffer.scala 433:61] + wire _T_2688 = _T_2681 | _T_2039; // @[el2_lsu_bus_buffer.scala 434:112] + wire _T_2689 = _T_1995 & _T_2688; // @[el2_lsu_bus_buffer.scala 432:114] + wire _T_2693 = buf_state_2 == 3'h6; // @[el2_lsu_bus_buffer.scala 433:49] + wire _T_2694 = _T_1799 | _T_2693; // @[el2_lsu_bus_buffer.scala 433:34] + wire _T_2695 = ~_T_2694; // @[el2_lsu_bus_buffer.scala 433:8] + wire _T_2703 = _T_2695 | _T_2057; // @[el2_lsu_bus_buffer.scala 433:61] + wire _T_2710 = _T_2703 | _T_2064; // @[el2_lsu_bus_buffer.scala 434:112] + wire _T_2711 = _T_1995 & _T_2710; // @[el2_lsu_bus_buffer.scala 432:114] + wire _T_2715 = buf_state_3 == 3'h6; // @[el2_lsu_bus_buffer.scala 433:49] + wire _T_2716 = _T_1810 | _T_2715; // @[el2_lsu_bus_buffer.scala 433:34] + wire _T_2717 = ~_T_2716; // @[el2_lsu_bus_buffer.scala 433:8] + wire _T_2725 = _T_2717 | _T_2082; // @[el2_lsu_bus_buffer.scala 433:61] + wire _T_2732 = _T_2725 | _T_2089; // @[el2_lsu_bus_buffer.scala 434:112] + wire _T_2733 = _T_1995 & _T_2732; // @[el2_lsu_bus_buffer.scala 432:114] + wire [3:0] buf_rspage_set_0 = {_T_2733,_T_2711,_T_2689,_T_2667}; // @[Cat.scala 29:58] + wire _T_2750 = _T_2651 | _T_2109; // @[el2_lsu_bus_buffer.scala 433:61] + wire _T_2757 = _T_2750 | _T_2116; // @[el2_lsu_bus_buffer.scala 434:112] + wire _T_2758 = _T_2097 & _T_2757; // @[el2_lsu_bus_buffer.scala 432:114] + wire _T_2772 = _T_2673 | _T_2134; // @[el2_lsu_bus_buffer.scala 433:61] + wire _T_2779 = _T_2772 | _T_2141; // @[el2_lsu_bus_buffer.scala 434:112] + wire _T_2780 = _T_2097 & _T_2779; // @[el2_lsu_bus_buffer.scala 432:114] + wire _T_2794 = _T_2695 | _T_2159; // @[el2_lsu_bus_buffer.scala 433:61] + wire _T_2801 = _T_2794 | _T_2166; // @[el2_lsu_bus_buffer.scala 434:112] + wire _T_2802 = _T_2097 & _T_2801; // @[el2_lsu_bus_buffer.scala 432:114] + wire _T_2816 = _T_2717 | _T_2184; // @[el2_lsu_bus_buffer.scala 433:61] + wire _T_2823 = _T_2816 | _T_2191; // @[el2_lsu_bus_buffer.scala 434:112] + wire _T_2824 = _T_2097 & _T_2823; // @[el2_lsu_bus_buffer.scala 432:114] + wire [3:0] buf_rspage_set_1 = {_T_2824,_T_2802,_T_2780,_T_2758}; // @[Cat.scala 29:58] + wire _T_2841 = _T_2651 | _T_2211; // @[el2_lsu_bus_buffer.scala 433:61] + wire _T_2848 = _T_2841 | _T_2218; // @[el2_lsu_bus_buffer.scala 434:112] + wire _T_2849 = _T_2199 & _T_2848; // @[el2_lsu_bus_buffer.scala 432:114] + wire _T_2863 = _T_2673 | _T_2236; // @[el2_lsu_bus_buffer.scala 433:61] + wire _T_2870 = _T_2863 | _T_2243; // @[el2_lsu_bus_buffer.scala 434:112] + wire _T_2871 = _T_2199 & _T_2870; // @[el2_lsu_bus_buffer.scala 432:114] + wire _T_2885 = _T_2695 | _T_2261; // @[el2_lsu_bus_buffer.scala 433:61] + wire _T_2892 = _T_2885 | _T_2268; // @[el2_lsu_bus_buffer.scala 434:112] + wire _T_2893 = _T_2199 & _T_2892; // @[el2_lsu_bus_buffer.scala 432:114] + wire _T_2907 = _T_2717 | _T_2286; // @[el2_lsu_bus_buffer.scala 433:61] + wire _T_2914 = _T_2907 | _T_2293; // @[el2_lsu_bus_buffer.scala 434:112] + wire _T_2915 = _T_2199 & _T_2914; // @[el2_lsu_bus_buffer.scala 432:114] + wire [3:0] buf_rspage_set_2 = {_T_2915,_T_2893,_T_2871,_T_2849}; // @[Cat.scala 29:58] + wire _T_2932 = _T_2651 | _T_2313; // @[el2_lsu_bus_buffer.scala 433:61] + wire _T_2939 = _T_2932 | _T_2320; // @[el2_lsu_bus_buffer.scala 434:112] + wire _T_2940 = _T_2301 & _T_2939; // @[el2_lsu_bus_buffer.scala 432:114] + wire _T_2954 = _T_2673 | _T_2338; // @[el2_lsu_bus_buffer.scala 433:61] + wire _T_2961 = _T_2954 | _T_2345; // @[el2_lsu_bus_buffer.scala 434:112] + wire _T_2962 = _T_2301 & _T_2961; // @[el2_lsu_bus_buffer.scala 432:114] + wire _T_2976 = _T_2695 | _T_2363; // @[el2_lsu_bus_buffer.scala 433:61] + wire _T_2983 = _T_2976 | _T_2370; // @[el2_lsu_bus_buffer.scala 434:112] + wire _T_2984 = _T_2301 & _T_2983; // @[el2_lsu_bus_buffer.scala 432:114] + wire _T_2998 = _T_2717 | _T_2388; // @[el2_lsu_bus_buffer.scala 433:61] + wire _T_3005 = _T_2998 | _T_2395; // @[el2_lsu_bus_buffer.scala 434:112] + wire _T_3006 = _T_2301 & _T_3005; // @[el2_lsu_bus_buffer.scala 432:114] + wire [3:0] buf_rspage_set_3 = {_T_3006,_T_2984,_T_2962,_T_2940}; // @[Cat.scala 29:58] + wire _T_3091 = _T_2715 | _T_1810; // @[el2_lsu_bus_buffer.scala 437:112] + wire _T_3092 = ~_T_3091; // @[el2_lsu_bus_buffer.scala 437:86] + wire _T_3093 = buf_rspageQ_0[3] & _T_3092; // @[el2_lsu_bus_buffer.scala 437:84] + wire _T_3085 = _T_2693 | _T_1799; // @[el2_lsu_bus_buffer.scala 437:112] + wire _T_3086 = ~_T_3085; // @[el2_lsu_bus_buffer.scala 437:86] + wire _T_3087 = buf_rspageQ_0[2] & _T_3086; // @[el2_lsu_bus_buffer.scala 437:84] + wire _T_3079 = _T_2671 | _T_1788; // @[el2_lsu_bus_buffer.scala 437:112] + wire _T_3080 = ~_T_3079; // @[el2_lsu_bus_buffer.scala 437:86] + wire _T_3081 = buf_rspageQ_0[1] & _T_3080; // @[el2_lsu_bus_buffer.scala 437:84] + wire _T_3073 = _T_2649 | _T_1777; // @[el2_lsu_bus_buffer.scala 437:112] + wire _T_3074 = ~_T_3073; // @[el2_lsu_bus_buffer.scala 437:86] + wire _T_3075 = buf_rspageQ_0[0] & _T_3074; // @[el2_lsu_bus_buffer.scala 437:84] + wire [3:0] buf_rspage_0 = {_T_3093,_T_3087,_T_3081,_T_3075}; // @[Cat.scala 29:58] + wire _T_3012 = buf_rspage_set_0[0] | buf_rspage_0[0]; // @[el2_lsu_bus_buffer.scala 436:90] + wire _T_3015 = buf_rspage_set_0[1] | buf_rspage_0[1]; // @[el2_lsu_bus_buffer.scala 436:90] + wire _T_3018 = buf_rspage_set_0[2] | buf_rspage_0[2]; // @[el2_lsu_bus_buffer.scala 436:90] + wire _T_3021 = buf_rspage_set_0[3] | buf_rspage_0[3]; // @[el2_lsu_bus_buffer.scala 436:90] + wire [2:0] _T_3023 = {_T_3021,_T_3018,_T_3015}; // @[Cat.scala 29:58] + wire _T_3120 = buf_rspageQ_1[3] & _T_3092; // @[el2_lsu_bus_buffer.scala 437:84] + wire _T_3114 = buf_rspageQ_1[2] & _T_3086; // @[el2_lsu_bus_buffer.scala 437:84] + wire _T_3108 = buf_rspageQ_1[1] & _T_3080; // @[el2_lsu_bus_buffer.scala 437:84] + wire _T_3102 = buf_rspageQ_1[0] & _T_3074; // @[el2_lsu_bus_buffer.scala 437:84] + wire [3:0] buf_rspage_1 = {_T_3120,_T_3114,_T_3108,_T_3102}; // @[Cat.scala 29:58] + wire _T_3027 = buf_rspage_set_1[0] | buf_rspage_1[0]; // @[el2_lsu_bus_buffer.scala 436:90] + wire _T_3030 = buf_rspage_set_1[1] | buf_rspage_1[1]; // @[el2_lsu_bus_buffer.scala 436:90] + wire _T_3033 = buf_rspage_set_1[2] | buf_rspage_1[2]; // @[el2_lsu_bus_buffer.scala 436:90] + wire _T_3036 = buf_rspage_set_1[3] | buf_rspage_1[3]; // @[el2_lsu_bus_buffer.scala 436:90] + wire [2:0] _T_3038 = {_T_3036,_T_3033,_T_3030}; // @[Cat.scala 29:58] + wire _T_3147 = buf_rspageQ_2[3] & _T_3092; // @[el2_lsu_bus_buffer.scala 437:84] + wire _T_3141 = buf_rspageQ_2[2] & _T_3086; // @[el2_lsu_bus_buffer.scala 437:84] + wire _T_3135 = buf_rspageQ_2[1] & _T_3080; // @[el2_lsu_bus_buffer.scala 437:84] + wire _T_3129 = buf_rspageQ_2[0] & _T_3074; // @[el2_lsu_bus_buffer.scala 437:84] + wire [3:0] buf_rspage_2 = {_T_3147,_T_3141,_T_3135,_T_3129}; // @[Cat.scala 29:58] + wire _T_3042 = buf_rspage_set_2[0] | buf_rspage_2[0]; // @[el2_lsu_bus_buffer.scala 436:90] + wire _T_3045 = buf_rspage_set_2[1] | buf_rspage_2[1]; // @[el2_lsu_bus_buffer.scala 436:90] + wire _T_3048 = buf_rspage_set_2[2] | buf_rspage_2[2]; // @[el2_lsu_bus_buffer.scala 436:90] + wire _T_3051 = buf_rspage_set_2[3] | buf_rspage_2[3]; // @[el2_lsu_bus_buffer.scala 436:90] + wire [2:0] _T_3053 = {_T_3051,_T_3048,_T_3045}; // @[Cat.scala 29:58] + wire _T_3174 = buf_rspageQ_3[3] & _T_3092; // @[el2_lsu_bus_buffer.scala 437:84] + wire _T_3168 = buf_rspageQ_3[2] & _T_3086; // @[el2_lsu_bus_buffer.scala 437:84] + wire _T_3162 = buf_rspageQ_3[1] & _T_3080; // @[el2_lsu_bus_buffer.scala 437:84] + wire _T_3156 = buf_rspageQ_3[0] & _T_3074; // @[el2_lsu_bus_buffer.scala 437:84] + wire [3:0] buf_rspage_3 = {_T_3174,_T_3168,_T_3162,_T_3156}; // @[Cat.scala 29:58] + wire _T_3057 = buf_rspage_set_3[0] | buf_rspage_3[0]; // @[el2_lsu_bus_buffer.scala 436:90] + wire _T_3060 = buf_rspage_set_3[1] | buf_rspage_3[1]; // @[el2_lsu_bus_buffer.scala 436:90] + wire _T_3063 = buf_rspage_set_3[2] | buf_rspage_3[2]; // @[el2_lsu_bus_buffer.scala 436:90] + wire _T_3066 = buf_rspage_set_3[3] | buf_rspage_3[3]; // @[el2_lsu_bus_buffer.scala 436:90] + wire [2:0] _T_3068 = {_T_3066,_T_3063,_T_3060}; // @[Cat.scala 29:58] + wire _T_3179 = ibuf_drain_vld & _T_1778; // @[el2_lsu_bus_buffer.scala 442:65] + wire _T_3181 = ibuf_drain_vld & _T_1789; // @[el2_lsu_bus_buffer.scala 442:65] + wire _T_3183 = ibuf_drain_vld & _T_1800; // @[el2_lsu_bus_buffer.scala 442:65] + wire _T_3185 = ibuf_drain_vld & _T_1811; // @[el2_lsu_bus_buffer.scala 442:65] + wire [3:0] ibuf_drainvec_vld = {_T_3185,_T_3183,_T_3181,_T_3179}; // @[Cat.scala 29:58] + wire _T_3193 = _T_3387 & _T_1783; // @[el2_lsu_bus_buffer.scala 443:123] + wire [3:0] _T_3196 = _T_3193 ? ldst_byteen_hi_r : ldst_byteen_lo_r; // @[el2_lsu_bus_buffer.scala 443:96] + wire [3:0] _T_3197 = ibuf_drainvec_vld[0] ? ibuf_byteen_out : _T_3196; // @[el2_lsu_bus_buffer.scala 443:48] + wire _T_3202 = _T_3387 & _T_1794; // @[el2_lsu_bus_buffer.scala 443:123] + wire [3:0] _T_3205 = _T_3202 ? ldst_byteen_hi_r : ldst_byteen_lo_r; // @[el2_lsu_bus_buffer.scala 443:96] + wire [3:0] _T_3206 = ibuf_drainvec_vld[1] ? ibuf_byteen_out : _T_3205; // @[el2_lsu_bus_buffer.scala 443:48] + wire _T_3211 = _T_3387 & _T_1805; // @[el2_lsu_bus_buffer.scala 443:123] + wire [3:0] _T_3214 = _T_3211 ? ldst_byteen_hi_r : ldst_byteen_lo_r; // @[el2_lsu_bus_buffer.scala 443:96] + wire [3:0] _T_3215 = ibuf_drainvec_vld[2] ? ibuf_byteen_out : _T_3214; // @[el2_lsu_bus_buffer.scala 443:48] + wire _T_3220 = _T_3387 & _T_1816; // @[el2_lsu_bus_buffer.scala 443:123] + wire [3:0] _T_3223 = _T_3220 ? ldst_byteen_hi_r : ldst_byteen_lo_r; // @[el2_lsu_bus_buffer.scala 443:96] + wire [3:0] _T_3224 = ibuf_drainvec_vld[3] ? ibuf_byteen_out : _T_3223; // @[el2_lsu_bus_buffer.scala 443:48] + wire _T_3250 = ibuf_drainvec_vld[0] ? ibuf_dual : io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 445:47] + wire _T_3252 = ibuf_drainvec_vld[1] ? ibuf_dual : io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 445:47] + wire _T_3254 = ibuf_drainvec_vld[2] ? ibuf_dual : io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 445:47] + wire _T_3256 = ibuf_drainvec_vld[3] ? ibuf_dual : io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 445:47] + wire [3:0] buf_dual_in = {_T_3256,_T_3254,_T_3252,_T_3250}; // @[Cat.scala 29:58] + wire _T_3261 = ibuf_drainvec_vld[0] ? ibuf_samedw : ldst_samedw_r; // @[el2_lsu_bus_buffer.scala 446:49] + wire _T_3263 = ibuf_drainvec_vld[1] ? ibuf_samedw : ldst_samedw_r; // @[el2_lsu_bus_buffer.scala 446:49] + wire _T_3265 = ibuf_drainvec_vld[2] ? ibuf_samedw : ldst_samedw_r; // @[el2_lsu_bus_buffer.scala 446:49] + wire _T_3267 = ibuf_drainvec_vld[3] ? ibuf_samedw : ldst_samedw_r; // @[el2_lsu_bus_buffer.scala 446:49] + wire [3:0] buf_samedw_in = {_T_3267,_T_3265,_T_3263,_T_3261}; // @[Cat.scala 29:58] + wire _T_3272 = ibuf_nomerge | ibuf_force_drain; // @[el2_lsu_bus_buffer.scala 447:86] + wire _T_3273 = ibuf_drainvec_vld[0] ? _T_3272 : io_no_dword_merge_r; // @[el2_lsu_bus_buffer.scala 447:50] + wire _T_3276 = ibuf_drainvec_vld[1] ? _T_3272 : io_no_dword_merge_r; // @[el2_lsu_bus_buffer.scala 447:50] + wire _T_3279 = ibuf_drainvec_vld[2] ? _T_3272 : io_no_dword_merge_r; // @[el2_lsu_bus_buffer.scala 447:50] + wire _T_3282 = ibuf_drainvec_vld[3] ? _T_3272 : io_no_dword_merge_r; // @[el2_lsu_bus_buffer.scala 447:50] + wire [3:0] buf_nomerge_in = {_T_3282,_T_3279,_T_3276,_T_3273}; // @[Cat.scala 29:58] + wire _T_3290 = ibuf_drainvec_vld[0] ? ibuf_dual : _T_3193; // @[el2_lsu_bus_buffer.scala 448:49] + wire _T_3295 = ibuf_drainvec_vld[1] ? ibuf_dual : _T_3202; // @[el2_lsu_bus_buffer.scala 448:49] + wire _T_3300 = ibuf_drainvec_vld[2] ? ibuf_dual : _T_3211; // @[el2_lsu_bus_buffer.scala 448:49] + wire _T_3305 = ibuf_drainvec_vld[3] ? ibuf_dual : _T_3220; // @[el2_lsu_bus_buffer.scala 448:49] + wire [3:0] buf_dualhi_in = {_T_3305,_T_3300,_T_3295,_T_3290}; // @[Cat.scala 29:58] + wire _T_3334 = ibuf_drainvec_vld[0] ? ibuf_sideeffect : io_is_sideeffects_r; // @[el2_lsu_bus_buffer.scala 450:53] + wire _T_3336 = ibuf_drainvec_vld[1] ? ibuf_sideeffect : io_is_sideeffects_r; // @[el2_lsu_bus_buffer.scala 450:53] + wire _T_3338 = ibuf_drainvec_vld[2] ? ibuf_sideeffect : io_is_sideeffects_r; // @[el2_lsu_bus_buffer.scala 450:53] + wire _T_3340 = ibuf_drainvec_vld[3] ? ibuf_sideeffect : io_is_sideeffects_r; // @[el2_lsu_bus_buffer.scala 450:53] + wire [3:0] buf_sideeffect_in = {_T_3340,_T_3338,_T_3336,_T_3334}; // @[Cat.scala 29:58] + wire _T_3345 = ibuf_drainvec_vld[0] ? ibuf_unsign : io_lsu_pkt_r_unsign; // @[el2_lsu_bus_buffer.scala 451:49] + wire _T_3347 = ibuf_drainvec_vld[1] ? ibuf_unsign : io_lsu_pkt_r_unsign; // @[el2_lsu_bus_buffer.scala 451:49] + wire _T_3349 = ibuf_drainvec_vld[2] ? ibuf_unsign : io_lsu_pkt_r_unsign; // @[el2_lsu_bus_buffer.scala 451:49] + wire _T_3351 = ibuf_drainvec_vld[3] ? ibuf_unsign : io_lsu_pkt_r_unsign; // @[el2_lsu_bus_buffer.scala 451:49] + wire [3:0] buf_unsign_in = {_T_3351,_T_3349,_T_3347,_T_3345}; // @[Cat.scala 29:58] + wire _T_3368 = ibuf_drainvec_vld[0] ? ibuf_write : io_lsu_pkt_r_store; // @[el2_lsu_bus_buffer.scala 453:48] + wire _T_3370 = ibuf_drainvec_vld[1] ? ibuf_write : io_lsu_pkt_r_store; // @[el2_lsu_bus_buffer.scala 453:48] + wire _T_3372 = ibuf_drainvec_vld[2] ? ibuf_write : io_lsu_pkt_r_store; // @[el2_lsu_bus_buffer.scala 453:48] + wire _T_3374 = ibuf_drainvec_vld[3] ? ibuf_write : io_lsu_pkt_r_store; // @[el2_lsu_bus_buffer.scala 453:48] + wire [3:0] buf_write_in = {_T_3374,_T_3372,_T_3370,_T_3368}; // @[Cat.scala 29:58] + wire [31:0] _T_3400 = _T_3393 ? ibuf_data_out : store_data_lo_r; // @[el2_lsu_bus_buffer.scala 462:30] + wire _T_3407 = obuf_nosend & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 469:89] + wire _T_3409 = _T_3407 & _T_1276; // @[el2_lsu_bus_buffer.scala 469:104] + wire _T_3422 = buf_state_en_0 & _T_1129; // @[el2_lsu_bus_buffer.scala 474:44] + wire _T_3423 = _T_3422 & obuf_nosend; // @[el2_lsu_bus_buffer.scala 474:60] + wire _T_3425 = _T_3423 & _T_1258; // @[el2_lsu_bus_buffer.scala 474:74] + wire _T_3428 = _T_3418 & obuf_nosend; // @[el2_lsu_bus_buffer.scala 476:67] + wire _T_3429 = _T_3428 & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 476:81] + wire _T_4723 = io_lsu_axi_bresp != 2'h0; // @[el2_lsu_bus_buffer.scala 578:58] + wire bus_rsp_read_error = bus_rsp_read & _T_4723; // @[el2_lsu_bus_buffer.scala 578:38] + wire _T_3432 = _T_3428 & bus_rsp_read_error; // @[el2_lsu_bus_buffer.scala 477:82] + wire [31:0] _T_3437 = buf_addr_0[2] ? io_lsu_axi_rdata[63:32] : io_lsu_axi_rdata[31:0]; // @[el2_lsu_bus_buffer.scala 478:73] + wire _T_3507 = bus_rsp_read_error & _T_3486; // @[el2_lsu_bus_buffer.scala 491:91] + wire _T_3509 = bus_rsp_read_error & buf_ldfwd[0]; // @[el2_lsu_bus_buffer.scala 492:31] + wire _T_3511 = _T_3509 & _T_3488; // @[el2_lsu_bus_buffer.scala 492:46] + wire _T_3512 = _T_3507 | _T_3511; // @[el2_lsu_bus_buffer.scala 491:143] + wire bus_rsp_write_error = bus_rsp_write & _T_4723; // @[el2_lsu_bus_buffer.scala 577:40] + wire _T_3515 = bus_rsp_write_error & _T_3484; // @[el2_lsu_bus_buffer.scala 493:53] + wire _T_3516 = _T_3512 | _T_3515; // @[el2_lsu_bus_buffer.scala 492:88] + wire _T_3517 = _T_3418 & _T_3516; // @[el2_lsu_bus_buffer.scala 491:68] + wire _GEN_46 = _T_3439 & _T_3517; // @[Conditional.scala 39:67] + wire _GEN_59 = _T_3405 ? _T_3432 : _GEN_46; // @[Conditional.scala 39:67] + wire _GEN_71 = _T_3401 ? 1'h0 : _GEN_59; // @[Conditional.scala 39:67] + wire buf_error_en_0 = _T_3378 ? 1'h0 : _GEN_71; // @[Conditional.scala 40:58] + wire [31:0] _T_3438 = buf_error_en_0 ? io_lsu_axi_rdata[31:0] : _T_3437; // @[el2_lsu_bus_buffer.scala 478:30] + wire _T_3442 = ~bus_rsp_write_error; // @[el2_lsu_bus_buffer.scala 481:73] + wire _T_3443 = buf_write[0] & _T_3442; // @[el2_lsu_bus_buffer.scala 481:71] + wire _T_3444 = io_dec_tlu_force_halt | _T_3443; // @[el2_lsu_bus_buffer.scala 481:55] + wire _T_3446 = ~buf_samedw_0; // @[el2_lsu_bus_buffer.scala 482:30] + wire _T_3447 = buf_dual_0 & _T_3446; // @[el2_lsu_bus_buffer.scala 482:28] + wire _T_3450 = _T_3447 & _T_1129; // @[el2_lsu_bus_buffer.scala 482:45] + wire [2:0] _GEN_19 = 2'h1 == buf_dualtag_0 ? buf_state_1 : buf_state_0; // @[el2_lsu_bus_buffer.scala 482:90] + wire [2:0] _GEN_20 = 2'h2 == buf_dualtag_0 ? buf_state_2 : _GEN_19; // @[el2_lsu_bus_buffer.scala 482:90] + wire [2:0] _GEN_21 = 2'h3 == buf_dualtag_0 ? buf_state_3 : _GEN_20; // @[el2_lsu_bus_buffer.scala 482:90] + wire _T_3451 = _GEN_21 != 3'h4; // @[el2_lsu_bus_buffer.scala 482:90] + wire _T_3452 = _T_3450 & _T_3451; // @[el2_lsu_bus_buffer.scala 482:61] + wire _T_4348 = _T_2596 | _T_2593; // @[el2_lsu_bus_buffer.scala 539:93] + wire _T_4349 = _T_4348 | _T_2590; // @[el2_lsu_bus_buffer.scala 539:93] + wire any_done_wait_state = _T_4349 | _T_2587; // @[el2_lsu_bus_buffer.scala 539:93] + wire _T_3454 = buf_ldfwd[0] | any_done_wait_state; // @[el2_lsu_bus_buffer.scala 483:31] + wire _T_3460 = buf_dualtag_0 == 2'h0; // @[el2_lsu_bus_buffer.scala 110:118] + wire _T_3462 = buf_dualtag_0 == 2'h1; // @[el2_lsu_bus_buffer.scala 110:118] + wire _T_3464 = buf_dualtag_0 == 2'h2; // @[el2_lsu_bus_buffer.scala 110:118] + wire _T_3466 = buf_dualtag_0 == 2'h3; // @[el2_lsu_bus_buffer.scala 110:118] + wire _T_3468 = _T_3460 & buf_ldfwd[0]; // @[Mux.scala 27:72] + wire _T_3469 = _T_3462 & buf_ldfwd[1]; // @[Mux.scala 27:72] + wire _T_3470 = _T_3464 & buf_ldfwd[2]; // @[Mux.scala 27:72] + wire _T_3471 = _T_3466 & buf_ldfwd[3]; // @[Mux.scala 27:72] + wire _T_3472 = _T_3468 | _T_3469; // @[Mux.scala 27:72] + wire _T_3473 = _T_3472 | _T_3470; // @[Mux.scala 27:72] + wire _T_3474 = _T_3473 | _T_3471; // @[Mux.scala 27:72] + wire _T_3476 = _T_3450 & _T_3474; // @[el2_lsu_bus_buffer.scala 483:101] + wire _T_3477 = _GEN_21 == 3'h4; // @[el2_lsu_bus_buffer.scala 483:167] + wire _T_3478 = _T_3476 & _T_3477; // @[el2_lsu_bus_buffer.scala 483:138] + wire _T_3479 = _T_3478 & any_done_wait_state; // @[el2_lsu_bus_buffer.scala 483:187] + wire _T_3480 = _T_3454 | _T_3479; // @[el2_lsu_bus_buffer.scala 483:53] + wire _T_3503 = buf_state_bus_en_0 & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 490:47] + wire _T_3504 = _T_3503 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 490:62] + wire _T_3518 = ~buf_error_en_0; // @[el2_lsu_bus_buffer.scala 494:50] + wire _T_3519 = buf_state_en_0 & _T_3518; // @[el2_lsu_bus_buffer.scala 494:48] + wire [31:0] _T_3525 = _T_3519 ? _T_3437 : io_lsu_axi_rdata[31:0]; // @[el2_lsu_bus_buffer.scala 494:30] + wire _T_3531 = buf_ldfwd[0] | _T_3536[0]; // @[el2_lsu_bus_buffer.scala 497:90] + wire _T_3532 = _T_3531 | any_done_wait_state; // @[el2_lsu_bus_buffer.scala 497:118] + wire _GEN_29 = _T_3552 & buf_state_en_0; // @[Conditional.scala 39:67] + wire _GEN_32 = _T_3544 ? 1'h0 : _T_3552; // @[Conditional.scala 39:67] + wire _GEN_34 = _T_3544 ? 1'h0 : _GEN_29; // @[Conditional.scala 39:67] + wire _GEN_38 = _T_3526 ? 1'h0 : _GEN_32; // @[Conditional.scala 39:67] + wire _GEN_40 = _T_3526 ? 1'h0 : _GEN_34; // @[Conditional.scala 39:67] + wire _GEN_45 = _T_3439 & _T_3504; // @[Conditional.scala 39:67] + wire [31:0] _GEN_47 = _T_3439 ? _T_3525 : 32'h0; // @[Conditional.scala 39:67] + wire _GEN_48 = _T_3439 ? 1'h0 : _GEN_38; // @[Conditional.scala 39:67] + wire _GEN_50 = _T_3439 ? 1'h0 : _GEN_40; // @[Conditional.scala 39:67] + wire _GEN_56 = _T_3405 ? _T_3425 : _GEN_50; // @[Conditional.scala 39:67] + wire _GEN_58 = _T_3405 ? _T_3429 : _GEN_45; // @[Conditional.scala 39:67] + wire [31:0] _GEN_60 = _T_3405 ? _T_3438 : _GEN_47; // @[Conditional.scala 39:67] + wire _GEN_62 = _T_3405 ? 1'h0 : _GEN_48; // @[Conditional.scala 39:67] + wire _GEN_68 = _T_3401 ? 1'h0 : _GEN_56; // @[Conditional.scala 39:67] + wire _GEN_70 = _T_3401 ? 1'h0 : _GEN_58; // @[Conditional.scala 39:67] + wire [31:0] _GEN_72 = _T_3401 ? 32'h0 : _GEN_60; // @[Conditional.scala 39:67] + wire _GEN_74 = _T_3401 ? 1'h0 : _GEN_62; // @[Conditional.scala 39:67] + wire buf_wr_en_0 = _T_3378 & buf_state_en_0; // @[Conditional.scala 40:58] + wire [31:0] _GEN_79 = _T_3378 ? _T_3400 : _GEN_72; // @[Conditional.scala 40:58] + wire buf_ldfwd_en_0 = _T_3378 ? 1'h0 : _GEN_68; // @[Conditional.scala 40:58] + wire buf_rst_0 = _T_3378 ? 1'h0 : _GEN_74; // @[Conditional.scala 40:58] + wire [31:0] _T_3593 = _T_3586 ? ibuf_data_out : store_data_lo_r; // @[el2_lsu_bus_buffer.scala 462:30] + wire _T_3615 = buf_state_en_1 & _T_3686; // @[el2_lsu_bus_buffer.scala 474:44] + wire _T_3616 = _T_3615 & obuf_nosend; // @[el2_lsu_bus_buffer.scala 474:60] + wire _T_3618 = _T_3616 & _T_1258; // @[el2_lsu_bus_buffer.scala 474:74] + wire _T_3621 = _T_3611 & obuf_nosend; // @[el2_lsu_bus_buffer.scala 476:67] + wire _T_3622 = _T_3621 & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 476:81] + wire _T_3625 = _T_3621 & bus_rsp_read_error; // @[el2_lsu_bus_buffer.scala 477:82] + wire [31:0] _T_3630 = buf_addr_1[2] ? io_lsu_axi_rdata[63:32] : io_lsu_axi_rdata[31:0]; // @[el2_lsu_bus_buffer.scala 478:73] + wire _T_3700 = bus_rsp_read_error & _T_3679; // @[el2_lsu_bus_buffer.scala 491:91] + wire _T_3702 = bus_rsp_read_error & buf_ldfwd[1]; // @[el2_lsu_bus_buffer.scala 492:31] + wire _T_3704 = _T_3702 & _T_3681; // @[el2_lsu_bus_buffer.scala 492:46] + wire _T_3705 = _T_3700 | _T_3704; // @[el2_lsu_bus_buffer.scala 491:143] + wire _T_3708 = bus_rsp_write_error & _T_3677; // @[el2_lsu_bus_buffer.scala 493:53] + wire _T_3709 = _T_3705 | _T_3708; // @[el2_lsu_bus_buffer.scala 492:88] + wire _T_3710 = _T_3611 & _T_3709; // @[el2_lsu_bus_buffer.scala 491:68] + wire _GEN_122 = _T_3632 & _T_3710; // @[Conditional.scala 39:67] + wire _GEN_135 = _T_3598 ? _T_3625 : _GEN_122; // @[Conditional.scala 39:67] + wire _GEN_147 = _T_3594 ? 1'h0 : _GEN_135; // @[Conditional.scala 39:67] + wire buf_error_en_1 = _T_3571 ? 1'h0 : _GEN_147; // @[Conditional.scala 40:58] + wire [31:0] _T_3631 = buf_error_en_1 ? io_lsu_axi_rdata[31:0] : _T_3630; // @[el2_lsu_bus_buffer.scala 478:30] + wire _T_3636 = buf_write[1] & _T_3442; // @[el2_lsu_bus_buffer.scala 481:71] + wire _T_3637 = io_dec_tlu_force_halt | _T_3636; // @[el2_lsu_bus_buffer.scala 481:55] + wire _T_3639 = ~buf_samedw_1; // @[el2_lsu_bus_buffer.scala 482:30] + wire _T_3640 = buf_dual_1 & _T_3639; // @[el2_lsu_bus_buffer.scala 482:28] + wire _T_3643 = _T_3640 & _T_3686; // @[el2_lsu_bus_buffer.scala 482:45] + wire [2:0] _GEN_95 = 2'h1 == buf_dualtag_1 ? buf_state_1 : buf_state_0; // @[el2_lsu_bus_buffer.scala 482:90] + wire [2:0] _GEN_96 = 2'h2 == buf_dualtag_1 ? buf_state_2 : _GEN_95; // @[el2_lsu_bus_buffer.scala 482:90] + wire [2:0] _GEN_97 = 2'h3 == buf_dualtag_1 ? buf_state_3 : _GEN_96; // @[el2_lsu_bus_buffer.scala 482:90] + wire _T_3644 = _GEN_97 != 3'h4; // @[el2_lsu_bus_buffer.scala 482:90] + wire _T_3645 = _T_3643 & _T_3644; // @[el2_lsu_bus_buffer.scala 482:61] + wire _T_3647 = buf_ldfwd[1] | any_done_wait_state; // @[el2_lsu_bus_buffer.scala 483:31] + wire _T_3653 = buf_dualtag_1 == 2'h0; // @[el2_lsu_bus_buffer.scala 110:118] + wire _T_3655 = buf_dualtag_1 == 2'h1; // @[el2_lsu_bus_buffer.scala 110:118] + wire _T_3657 = buf_dualtag_1 == 2'h2; // @[el2_lsu_bus_buffer.scala 110:118] + wire _T_3659 = buf_dualtag_1 == 2'h3; // @[el2_lsu_bus_buffer.scala 110:118] + wire _T_3661 = _T_3653 & buf_ldfwd[0]; // @[Mux.scala 27:72] + wire _T_3662 = _T_3655 & buf_ldfwd[1]; // @[Mux.scala 27:72] + wire _T_3663 = _T_3657 & buf_ldfwd[2]; // @[Mux.scala 27:72] + wire _T_3664 = _T_3659 & buf_ldfwd[3]; // @[Mux.scala 27:72] + wire _T_3665 = _T_3661 | _T_3662; // @[Mux.scala 27:72] + wire _T_3666 = _T_3665 | _T_3663; // @[Mux.scala 27:72] + wire _T_3667 = _T_3666 | _T_3664; // @[Mux.scala 27:72] + wire _T_3669 = _T_3643 & _T_3667; // @[el2_lsu_bus_buffer.scala 483:101] + wire _T_3670 = _GEN_97 == 3'h4; // @[el2_lsu_bus_buffer.scala 483:167] + wire _T_3671 = _T_3669 & _T_3670; // @[el2_lsu_bus_buffer.scala 483:138] + wire _T_3672 = _T_3671 & any_done_wait_state; // @[el2_lsu_bus_buffer.scala 483:187] + wire _T_3673 = _T_3647 | _T_3672; // @[el2_lsu_bus_buffer.scala 483:53] + wire _T_3696 = buf_state_bus_en_1 & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 490:47] + wire _T_3697 = _T_3696 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 490:62] + wire _T_3711 = ~buf_error_en_1; // @[el2_lsu_bus_buffer.scala 494:50] + wire _T_3712 = buf_state_en_1 & _T_3711; // @[el2_lsu_bus_buffer.scala 494:48] + wire [31:0] _T_3718 = _T_3712 ? _T_3630 : io_lsu_axi_rdata[31:0]; // @[el2_lsu_bus_buffer.scala 494:30] + wire _T_3724 = buf_ldfwd[1] | _T_3729[0]; // @[el2_lsu_bus_buffer.scala 497:90] + wire _T_3725 = _T_3724 | any_done_wait_state; // @[el2_lsu_bus_buffer.scala 497:118] + wire _GEN_105 = _T_3745 & buf_state_en_1; // @[Conditional.scala 39:67] + wire _GEN_108 = _T_3737 ? 1'h0 : _T_3745; // @[Conditional.scala 39:67] + wire _GEN_110 = _T_3737 ? 1'h0 : _GEN_105; // @[Conditional.scala 39:67] + wire _GEN_114 = _T_3719 ? 1'h0 : _GEN_108; // @[Conditional.scala 39:67] + wire _GEN_116 = _T_3719 ? 1'h0 : _GEN_110; // @[Conditional.scala 39:67] + wire _GEN_121 = _T_3632 & _T_3697; // @[Conditional.scala 39:67] + wire [31:0] _GEN_123 = _T_3632 ? _T_3718 : 32'h0; // @[Conditional.scala 39:67] + wire _GEN_124 = _T_3632 ? 1'h0 : _GEN_114; // @[Conditional.scala 39:67] + wire _GEN_126 = _T_3632 ? 1'h0 : _GEN_116; // @[Conditional.scala 39:67] + wire _GEN_132 = _T_3598 ? _T_3618 : _GEN_126; // @[Conditional.scala 39:67] + wire _GEN_134 = _T_3598 ? _T_3622 : _GEN_121; // @[Conditional.scala 39:67] + wire [31:0] _GEN_136 = _T_3598 ? _T_3631 : _GEN_123; // @[Conditional.scala 39:67] + wire _GEN_138 = _T_3598 ? 1'h0 : _GEN_124; // @[Conditional.scala 39:67] + wire _GEN_144 = _T_3594 ? 1'h0 : _GEN_132; // @[Conditional.scala 39:67] + wire _GEN_146 = _T_3594 ? 1'h0 : _GEN_134; // @[Conditional.scala 39:67] + wire [31:0] _GEN_148 = _T_3594 ? 32'h0 : _GEN_136; // @[Conditional.scala 39:67] + wire _GEN_150 = _T_3594 ? 1'h0 : _GEN_138; // @[Conditional.scala 39:67] + wire buf_wr_en_1 = _T_3571 & buf_state_en_1; // @[Conditional.scala 40:58] + wire [31:0] _GEN_155 = _T_3571 ? _T_3593 : _GEN_148; // @[Conditional.scala 40:58] + wire buf_ldfwd_en_1 = _T_3571 ? 1'h0 : _GEN_144; // @[Conditional.scala 40:58] + wire buf_rst_1 = _T_3571 ? 1'h0 : _GEN_150; // @[Conditional.scala 40:58] + wire [31:0] _T_3786 = _T_3779 ? ibuf_data_out : store_data_lo_r; // @[el2_lsu_bus_buffer.scala 462:30] + wire _T_3808 = buf_state_en_2 & _T_3879; // @[el2_lsu_bus_buffer.scala 474:44] + wire _T_3809 = _T_3808 & obuf_nosend; // @[el2_lsu_bus_buffer.scala 474:60] + wire _T_3811 = _T_3809 & _T_1258; // @[el2_lsu_bus_buffer.scala 474:74] + wire _T_3814 = _T_3804 & obuf_nosend; // @[el2_lsu_bus_buffer.scala 476:67] + wire _T_3815 = _T_3814 & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 476:81] + wire _T_3818 = _T_3814 & bus_rsp_read_error; // @[el2_lsu_bus_buffer.scala 477:82] + wire [31:0] _T_3823 = buf_addr_2[2] ? io_lsu_axi_rdata[63:32] : io_lsu_axi_rdata[31:0]; // @[el2_lsu_bus_buffer.scala 478:73] + wire _T_3893 = bus_rsp_read_error & _T_3872; // @[el2_lsu_bus_buffer.scala 491:91] + wire _T_3895 = bus_rsp_read_error & buf_ldfwd[2]; // @[el2_lsu_bus_buffer.scala 492:31] + wire _T_3897 = _T_3895 & _T_3874; // @[el2_lsu_bus_buffer.scala 492:46] + wire _T_3898 = _T_3893 | _T_3897; // @[el2_lsu_bus_buffer.scala 491:143] + wire _T_3901 = bus_rsp_write_error & _T_3870; // @[el2_lsu_bus_buffer.scala 493:53] + wire _T_3902 = _T_3898 | _T_3901; // @[el2_lsu_bus_buffer.scala 492:88] + wire _T_3903 = _T_3804 & _T_3902; // @[el2_lsu_bus_buffer.scala 491:68] + wire _GEN_198 = _T_3825 & _T_3903; // @[Conditional.scala 39:67] + wire _GEN_211 = _T_3791 ? _T_3818 : _GEN_198; // @[Conditional.scala 39:67] + wire _GEN_223 = _T_3787 ? 1'h0 : _GEN_211; // @[Conditional.scala 39:67] + wire buf_error_en_2 = _T_3764 ? 1'h0 : _GEN_223; // @[Conditional.scala 40:58] + wire [31:0] _T_3824 = buf_error_en_2 ? io_lsu_axi_rdata[31:0] : _T_3823; // @[el2_lsu_bus_buffer.scala 478:30] + wire _T_3829 = buf_write[2] & _T_3442; // @[el2_lsu_bus_buffer.scala 481:71] + wire _T_3830 = io_dec_tlu_force_halt | _T_3829; // @[el2_lsu_bus_buffer.scala 481:55] + wire _T_3832 = ~buf_samedw_2; // @[el2_lsu_bus_buffer.scala 482:30] + wire _T_3833 = buf_dual_2 & _T_3832; // @[el2_lsu_bus_buffer.scala 482:28] + wire _T_3836 = _T_3833 & _T_3879; // @[el2_lsu_bus_buffer.scala 482:45] + wire [2:0] _GEN_171 = 2'h1 == buf_dualtag_2 ? buf_state_1 : buf_state_0; // @[el2_lsu_bus_buffer.scala 482:90] + wire [2:0] _GEN_172 = 2'h2 == buf_dualtag_2 ? buf_state_2 : _GEN_171; // @[el2_lsu_bus_buffer.scala 482:90] + wire [2:0] _GEN_173 = 2'h3 == buf_dualtag_2 ? buf_state_3 : _GEN_172; // @[el2_lsu_bus_buffer.scala 482:90] + wire _T_3837 = _GEN_173 != 3'h4; // @[el2_lsu_bus_buffer.scala 482:90] + wire _T_3838 = _T_3836 & _T_3837; // @[el2_lsu_bus_buffer.scala 482:61] + wire _T_3840 = buf_ldfwd[2] | any_done_wait_state; // @[el2_lsu_bus_buffer.scala 483:31] + wire _T_3846 = buf_dualtag_2 == 2'h0; // @[el2_lsu_bus_buffer.scala 110:118] + wire _T_3848 = buf_dualtag_2 == 2'h1; // @[el2_lsu_bus_buffer.scala 110:118] + wire _T_3850 = buf_dualtag_2 == 2'h2; // @[el2_lsu_bus_buffer.scala 110:118] + wire _T_3852 = buf_dualtag_2 == 2'h3; // @[el2_lsu_bus_buffer.scala 110:118] + wire _T_3854 = _T_3846 & buf_ldfwd[0]; // @[Mux.scala 27:72] + wire _T_3855 = _T_3848 & buf_ldfwd[1]; // @[Mux.scala 27:72] + wire _T_3856 = _T_3850 & buf_ldfwd[2]; // @[Mux.scala 27:72] + wire _T_3857 = _T_3852 & buf_ldfwd[3]; // @[Mux.scala 27:72] + wire _T_3858 = _T_3854 | _T_3855; // @[Mux.scala 27:72] + wire _T_3859 = _T_3858 | _T_3856; // @[Mux.scala 27:72] + wire _T_3860 = _T_3859 | _T_3857; // @[Mux.scala 27:72] + wire _T_3862 = _T_3836 & _T_3860; // @[el2_lsu_bus_buffer.scala 483:101] + wire _T_3863 = _GEN_173 == 3'h4; // @[el2_lsu_bus_buffer.scala 483:167] + wire _T_3864 = _T_3862 & _T_3863; // @[el2_lsu_bus_buffer.scala 483:138] + wire _T_3865 = _T_3864 & any_done_wait_state; // @[el2_lsu_bus_buffer.scala 483:187] + wire _T_3866 = _T_3840 | _T_3865; // @[el2_lsu_bus_buffer.scala 483:53] + wire _T_3889 = buf_state_bus_en_2 & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 490:47] + wire _T_3890 = _T_3889 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 490:62] + wire _T_3904 = ~buf_error_en_2; // @[el2_lsu_bus_buffer.scala 494:50] + wire _T_3905 = buf_state_en_2 & _T_3904; // @[el2_lsu_bus_buffer.scala 494:48] + wire [31:0] _T_3911 = _T_3905 ? _T_3823 : io_lsu_axi_rdata[31:0]; // @[el2_lsu_bus_buffer.scala 494:30] + wire _T_3917 = buf_ldfwd[2] | _T_3922[0]; // @[el2_lsu_bus_buffer.scala 497:90] + wire _T_3918 = _T_3917 | any_done_wait_state; // @[el2_lsu_bus_buffer.scala 497:118] + wire _GEN_181 = _T_3938 & buf_state_en_2; // @[Conditional.scala 39:67] + wire _GEN_184 = _T_3930 ? 1'h0 : _T_3938; // @[Conditional.scala 39:67] + wire _GEN_186 = _T_3930 ? 1'h0 : _GEN_181; // @[Conditional.scala 39:67] + wire _GEN_190 = _T_3912 ? 1'h0 : _GEN_184; // @[Conditional.scala 39:67] + wire _GEN_192 = _T_3912 ? 1'h0 : _GEN_186; // @[Conditional.scala 39:67] + wire _GEN_197 = _T_3825 & _T_3890; // @[Conditional.scala 39:67] + wire [31:0] _GEN_199 = _T_3825 ? _T_3911 : 32'h0; // @[Conditional.scala 39:67] + wire _GEN_200 = _T_3825 ? 1'h0 : _GEN_190; // @[Conditional.scala 39:67] + wire _GEN_202 = _T_3825 ? 1'h0 : _GEN_192; // @[Conditional.scala 39:67] + wire _GEN_208 = _T_3791 ? _T_3811 : _GEN_202; // @[Conditional.scala 39:67] + wire _GEN_210 = _T_3791 ? _T_3815 : _GEN_197; // @[Conditional.scala 39:67] + wire [31:0] _GEN_212 = _T_3791 ? _T_3824 : _GEN_199; // @[Conditional.scala 39:67] + wire _GEN_214 = _T_3791 ? 1'h0 : _GEN_200; // @[Conditional.scala 39:67] + wire _GEN_220 = _T_3787 ? 1'h0 : _GEN_208; // @[Conditional.scala 39:67] + wire _GEN_222 = _T_3787 ? 1'h0 : _GEN_210; // @[Conditional.scala 39:67] + wire [31:0] _GEN_224 = _T_3787 ? 32'h0 : _GEN_212; // @[Conditional.scala 39:67] + wire _GEN_226 = _T_3787 ? 1'h0 : _GEN_214; // @[Conditional.scala 39:67] + wire buf_wr_en_2 = _T_3764 & buf_state_en_2; // @[Conditional.scala 40:58] + wire [31:0] _GEN_231 = _T_3764 ? _T_3786 : _GEN_224; // @[Conditional.scala 40:58] + wire buf_ldfwd_en_2 = _T_3764 ? 1'h0 : _GEN_220; // @[Conditional.scala 40:58] + wire buf_rst_2 = _T_3764 ? 1'h0 : _GEN_226; // @[Conditional.scala 40:58] + wire [31:0] _T_3979 = _T_3972 ? ibuf_data_out : store_data_lo_r; // @[el2_lsu_bus_buffer.scala 462:30] + wire _T_4001 = buf_state_en_3 & _T_4072; // @[el2_lsu_bus_buffer.scala 474:44] + wire _T_4002 = _T_4001 & obuf_nosend; // @[el2_lsu_bus_buffer.scala 474:60] + wire _T_4004 = _T_4002 & _T_1258; // @[el2_lsu_bus_buffer.scala 474:74] + wire _T_4007 = _T_3997 & obuf_nosend; // @[el2_lsu_bus_buffer.scala 476:67] + wire _T_4008 = _T_4007 & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 476:81] + wire _T_4011 = _T_4007 & bus_rsp_read_error; // @[el2_lsu_bus_buffer.scala 477:82] + wire [31:0] _T_4016 = buf_addr_3[2] ? io_lsu_axi_rdata[63:32] : io_lsu_axi_rdata[31:0]; // @[el2_lsu_bus_buffer.scala 478:73] + wire _T_4086 = bus_rsp_read_error & _T_4065; // @[el2_lsu_bus_buffer.scala 491:91] + wire _T_4088 = bus_rsp_read_error & buf_ldfwd[3]; // @[el2_lsu_bus_buffer.scala 492:31] + wire _T_4090 = _T_4088 & _T_4067; // @[el2_lsu_bus_buffer.scala 492:46] + wire _T_4091 = _T_4086 | _T_4090; // @[el2_lsu_bus_buffer.scala 491:143] + wire _T_4094 = bus_rsp_write_error & _T_4063; // @[el2_lsu_bus_buffer.scala 493:53] + wire _T_4095 = _T_4091 | _T_4094; // @[el2_lsu_bus_buffer.scala 492:88] + wire _T_4096 = _T_3997 & _T_4095; // @[el2_lsu_bus_buffer.scala 491:68] + wire _GEN_274 = _T_4018 & _T_4096; // @[Conditional.scala 39:67] + wire _GEN_287 = _T_3984 ? _T_4011 : _GEN_274; // @[Conditional.scala 39:67] + wire _GEN_299 = _T_3980 ? 1'h0 : _GEN_287; // @[Conditional.scala 39:67] + wire buf_error_en_3 = _T_3957 ? 1'h0 : _GEN_299; // @[Conditional.scala 40:58] + wire [31:0] _T_4017 = buf_error_en_3 ? io_lsu_axi_rdata[31:0] : _T_4016; // @[el2_lsu_bus_buffer.scala 478:30] + wire _T_4022 = buf_write[3] & _T_3442; // @[el2_lsu_bus_buffer.scala 481:71] + wire _T_4023 = io_dec_tlu_force_halt | _T_4022; // @[el2_lsu_bus_buffer.scala 481:55] + wire _T_4025 = ~buf_samedw_3; // @[el2_lsu_bus_buffer.scala 482:30] + wire _T_4026 = buf_dual_3 & _T_4025; // @[el2_lsu_bus_buffer.scala 482:28] + wire _T_4029 = _T_4026 & _T_4072; // @[el2_lsu_bus_buffer.scala 482:45] + wire [2:0] _GEN_247 = 2'h1 == buf_dualtag_3 ? buf_state_1 : buf_state_0; // @[el2_lsu_bus_buffer.scala 482:90] + wire [2:0] _GEN_248 = 2'h2 == buf_dualtag_3 ? buf_state_2 : _GEN_247; // @[el2_lsu_bus_buffer.scala 482:90] + wire [2:0] _GEN_249 = 2'h3 == buf_dualtag_3 ? buf_state_3 : _GEN_248; // @[el2_lsu_bus_buffer.scala 482:90] + wire _T_4030 = _GEN_249 != 3'h4; // @[el2_lsu_bus_buffer.scala 482:90] + wire _T_4031 = _T_4029 & _T_4030; // @[el2_lsu_bus_buffer.scala 482:61] + wire _T_4033 = buf_ldfwd[3] | any_done_wait_state; // @[el2_lsu_bus_buffer.scala 483:31] + wire _T_4039 = buf_dualtag_3 == 2'h0; // @[el2_lsu_bus_buffer.scala 110:118] + wire _T_4041 = buf_dualtag_3 == 2'h1; // @[el2_lsu_bus_buffer.scala 110:118] + wire _T_4043 = buf_dualtag_3 == 2'h2; // @[el2_lsu_bus_buffer.scala 110:118] + wire _T_4045 = buf_dualtag_3 == 2'h3; // @[el2_lsu_bus_buffer.scala 110:118] + wire _T_4047 = _T_4039 & buf_ldfwd[0]; // @[Mux.scala 27:72] + wire _T_4048 = _T_4041 & buf_ldfwd[1]; // @[Mux.scala 27:72] + wire _T_4049 = _T_4043 & buf_ldfwd[2]; // @[Mux.scala 27:72] + wire _T_4050 = _T_4045 & buf_ldfwd[3]; // @[Mux.scala 27:72] + wire _T_4051 = _T_4047 | _T_4048; // @[Mux.scala 27:72] + wire _T_4052 = _T_4051 | _T_4049; // @[Mux.scala 27:72] + wire _T_4053 = _T_4052 | _T_4050; // @[Mux.scala 27:72] + wire _T_4055 = _T_4029 & _T_4053; // @[el2_lsu_bus_buffer.scala 483:101] + wire _T_4056 = _GEN_249 == 3'h4; // @[el2_lsu_bus_buffer.scala 483:167] + wire _T_4057 = _T_4055 & _T_4056; // @[el2_lsu_bus_buffer.scala 483:138] + wire _T_4058 = _T_4057 & any_done_wait_state; // @[el2_lsu_bus_buffer.scala 483:187] + wire _T_4059 = _T_4033 | _T_4058; // @[el2_lsu_bus_buffer.scala 483:53] + wire _T_4082 = buf_state_bus_en_3 & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 490:47] + wire _T_4083 = _T_4082 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 490:62] + wire _T_4097 = ~buf_error_en_3; // @[el2_lsu_bus_buffer.scala 494:50] + wire _T_4098 = buf_state_en_3 & _T_4097; // @[el2_lsu_bus_buffer.scala 494:48] + wire [31:0] _T_4104 = _T_4098 ? _T_4016 : io_lsu_axi_rdata[31:0]; // @[el2_lsu_bus_buffer.scala 494:30] + wire _T_4110 = buf_ldfwd[3] | _T_4115[0]; // @[el2_lsu_bus_buffer.scala 497:90] + wire _T_4111 = _T_4110 | any_done_wait_state; // @[el2_lsu_bus_buffer.scala 497:118] + wire _GEN_257 = _T_4131 & buf_state_en_3; // @[Conditional.scala 39:67] + wire _GEN_260 = _T_4123 ? 1'h0 : _T_4131; // @[Conditional.scala 39:67] + wire _GEN_262 = _T_4123 ? 1'h0 : _GEN_257; // @[Conditional.scala 39:67] + wire _GEN_266 = _T_4105 ? 1'h0 : _GEN_260; // @[Conditional.scala 39:67] + wire _GEN_268 = _T_4105 ? 1'h0 : _GEN_262; // @[Conditional.scala 39:67] + wire _GEN_273 = _T_4018 & _T_4083; // @[Conditional.scala 39:67] + wire [31:0] _GEN_275 = _T_4018 ? _T_4104 : 32'h0; // @[Conditional.scala 39:67] + wire _GEN_276 = _T_4018 ? 1'h0 : _GEN_266; // @[Conditional.scala 39:67] + wire _GEN_278 = _T_4018 ? 1'h0 : _GEN_268; // @[Conditional.scala 39:67] + wire _GEN_284 = _T_3984 ? _T_4004 : _GEN_278; // @[Conditional.scala 39:67] + wire _GEN_286 = _T_3984 ? _T_4008 : _GEN_273; // @[Conditional.scala 39:67] + wire [31:0] _GEN_288 = _T_3984 ? _T_4017 : _GEN_275; // @[Conditional.scala 39:67] + wire _GEN_290 = _T_3984 ? 1'h0 : _GEN_276; // @[Conditional.scala 39:67] + wire _GEN_296 = _T_3980 ? 1'h0 : _GEN_284; // @[Conditional.scala 39:67] + wire _GEN_298 = _T_3980 ? 1'h0 : _GEN_286; // @[Conditional.scala 39:67] + wire [31:0] _GEN_300 = _T_3980 ? 32'h0 : _GEN_288; // @[Conditional.scala 39:67] + wire _GEN_302 = _T_3980 ? 1'h0 : _GEN_290; // @[Conditional.scala 39:67] + wire buf_wr_en_3 = _T_3957 & buf_state_en_3; // @[Conditional.scala 40:58] + wire [31:0] _GEN_307 = _T_3957 ? _T_3979 : _GEN_300; // @[Conditional.scala 40:58] + wire buf_ldfwd_en_3 = _T_3957 ? 1'h0 : _GEN_296; // @[Conditional.scala 40:58] + wire buf_rst_3 = _T_3957 ? 1'h0 : _GEN_302; // @[Conditional.scala 40:58] + reg _T_4186; // @[Reg.scala 27:20] + reg _T_4189; // @[Reg.scala 27:20] + reg _T_4192; // @[Reg.scala 27:20] + reg _T_4195; // @[Reg.scala 27:20] + wire [3:0] buf_unsign = {_T_4195,_T_4192,_T_4189,_T_4186}; // @[Cat.scala 29:58] + wire [2:0] buf_byteen_in_0 = _T_3197[2:0]; // @[el2_lsu_bus_buffer.scala 170:27 el2_lsu_bus_buffer.scala 171:17 el2_lsu_bus_buffer.scala 443:19] + wire [2:0] buf_byteen_in_1 = _T_3206[2:0]; // @[el2_lsu_bus_buffer.scala 170:27 el2_lsu_bus_buffer.scala 171:17 el2_lsu_bus_buffer.scala 443:19] + wire [2:0] buf_byteen_in_2 = _T_3215[2:0]; // @[el2_lsu_bus_buffer.scala 170:27 el2_lsu_bus_buffer.scala 171:17 el2_lsu_bus_buffer.scala 443:19] + wire [2:0] buf_byteen_in_3 = _T_3224[2:0]; // @[el2_lsu_bus_buffer.scala 170:27 el2_lsu_bus_buffer.scala 171:17 el2_lsu_bus_buffer.scala 443:19] + reg _T_4257; // @[el2_lsu_bus_buffer.scala 533:82] + reg _T_4253; // @[el2_lsu_bus_buffer.scala 533:82] + reg _T_4249; // @[el2_lsu_bus_buffer.scala 533:82] + reg _T_4245; // @[el2_lsu_bus_buffer.scala 533:82] + wire [3:0] buf_error = {_T_4257,_T_4253,_T_4249,_T_4245}; // @[Cat.scala 29:58] + wire _T_4243 = buf_error_en_0 | buf_error[0]; // @[el2_lsu_bus_buffer.scala 533:86] + wire _T_4247 = buf_error_en_1 | buf_error[1]; // @[el2_lsu_bus_buffer.scala 533:86] + wire _T_4251 = buf_error_en_2 | buf_error[2]; // @[el2_lsu_bus_buffer.scala 533:86] + wire _T_4255 = buf_error_en_3 | buf_error[3]; // @[el2_lsu_bus_buffer.scala 533:86] + wire [1:0] _T_4265 = _T_26 + _T_19; // @[el2_lsu_bus_buffer.scala 535:96] + wire [1:0] _GEN_407 = {{1'd0}, _T_12}; // @[el2_lsu_bus_buffer.scala 535:96] + wire [2:0] _T_4266 = _T_4265 + _GEN_407; // @[el2_lsu_bus_buffer.scala 535:96] + wire [2:0] _GEN_408 = {{2'd0}, _T_5}; // @[el2_lsu_bus_buffer.scala 535:96] + wire [3:0] buf_numvld_any = _T_4266 + _GEN_408; // @[el2_lsu_bus_buffer.scala 535:96] + wire _T_4352 = io_ldst_dual_d & io_dec_lsu_valid_raw_d; // @[el2_lsu_bus_buffer.scala 541:52] + wire _T_4353 = buf_numvld_any >= 4'h3; // @[el2_lsu_bus_buffer.scala 541:92] + wire _T_4354 = buf_numvld_any == 4'h3; // @[el2_lsu_bus_buffer.scala 541:119] + wire _T_4356 = |buf_state_0; // @[el2_lsu_bus_buffer.scala 542:52] + wire _T_4357 = |buf_state_1; // @[el2_lsu_bus_buffer.scala 542:52] + wire _T_4358 = |buf_state_2; // @[el2_lsu_bus_buffer.scala 542:52] + wire _T_4359 = |buf_state_3; // @[el2_lsu_bus_buffer.scala 542:52] + wire _T_4360 = _T_4356 | _T_4357; // @[el2_lsu_bus_buffer.scala 542:65] + wire _T_4361 = _T_4360 | _T_4358; // @[el2_lsu_bus_buffer.scala 542:65] + wire _T_4362 = _T_4361 | _T_4359; // @[el2_lsu_bus_buffer.scala 542:65] + wire _T_4363 = ~_T_4362; // @[el2_lsu_bus_buffer.scala 542:34] + wire _T_4365 = _T_4363 & _T_765; // @[el2_lsu_bus_buffer.scala 542:70] + wire _T_4368 = io_lsu_busreq_m & io_lsu_pkt_m_valid; // @[el2_lsu_bus_buffer.scala 544:51] + wire _T_4369 = _T_4368 & io_lsu_pkt_m_load; // @[el2_lsu_bus_buffer.scala 544:72] + wire _T_4370 = ~io_flush_m_up; // @[el2_lsu_bus_buffer.scala 544:94] + wire _T_4371 = _T_4369 & _T_4370; // @[el2_lsu_bus_buffer.scala 544:92] + wire _T_4372 = ~io_ld_full_hit_m; // @[el2_lsu_bus_buffer.scala 544:111] + wire _T_4374 = ~io_lsu_commit_r; // @[el2_lsu_bus_buffer.scala 547:61] + reg lsu_nonblock_load_valid_r; // @[el2_lsu_bus_buffer.scala 631:66] + wire _T_4392 = _T_2649 & _T_1129; // @[Mux.scala 27:72] + wire _T_4393 = _T_2671 & _T_3686; // @[Mux.scala 27:72] + wire _T_4394 = _T_2693 & _T_3879; // @[Mux.scala 27:72] + wire _T_4395 = _T_2715 & _T_4072; // @[Mux.scala 27:72] + wire _T_4396 = _T_4392 | _T_4393; // @[Mux.scala 27:72] + wire _T_4397 = _T_4396 | _T_4394; // @[Mux.scala 27:72] + wire lsu_nonblock_load_data_ready = _T_4397 | _T_4395; // @[Mux.scala 27:72] + wire _T_4403 = buf_error[0] & _T_1129; // @[el2_lsu_bus_buffer.scala 550:108] + wire _T_4408 = buf_error[1] & _T_3686; // @[el2_lsu_bus_buffer.scala 550:108] + wire _T_4413 = buf_error[2] & _T_3879; // @[el2_lsu_bus_buffer.scala 550:108] + wire _T_4418 = buf_error[3] & _T_4072; // @[el2_lsu_bus_buffer.scala 550:108] + wire _T_4419 = _T_2649 & _T_4403; // @[Mux.scala 27:72] + wire _T_4420 = _T_2671 & _T_4408; // @[Mux.scala 27:72] + wire _T_4421 = _T_2693 & _T_4413; // @[Mux.scala 27:72] + wire _T_4422 = _T_2715 & _T_4418; // @[Mux.scala 27:72] + wire _T_4423 = _T_4419 | _T_4420; // @[Mux.scala 27:72] + wire _T_4424 = _T_4423 | _T_4421; // @[Mux.scala 27:72] + wire _T_4431 = ~buf_dual_0; // @[el2_lsu_bus_buffer.scala 551:109] + wire _T_4432 = ~buf_dualhi_0; // @[el2_lsu_bus_buffer.scala 551:124] + wire _T_4433 = _T_4431 | _T_4432; // @[el2_lsu_bus_buffer.scala 551:122] + wire _T_4434 = _T_4392 & _T_4433; // @[el2_lsu_bus_buffer.scala 551:106] + wire _T_4439 = ~buf_dual_1; // @[el2_lsu_bus_buffer.scala 551:109] + wire _T_4440 = ~buf_dualhi_1; // @[el2_lsu_bus_buffer.scala 551:124] + wire _T_4441 = _T_4439 | _T_4440; // @[el2_lsu_bus_buffer.scala 551:122] + wire _T_4442 = _T_4393 & _T_4441; // @[el2_lsu_bus_buffer.scala 551:106] + wire _T_4447 = ~buf_dual_2; // @[el2_lsu_bus_buffer.scala 551:109] + wire _T_4448 = ~buf_dualhi_2; // @[el2_lsu_bus_buffer.scala 551:124] + wire _T_4449 = _T_4447 | _T_4448; // @[el2_lsu_bus_buffer.scala 551:122] + wire _T_4450 = _T_4394 & _T_4449; // @[el2_lsu_bus_buffer.scala 551:106] + wire _T_4455 = ~buf_dual_3; // @[el2_lsu_bus_buffer.scala 551:109] + wire _T_4456 = ~buf_dualhi_3; // @[el2_lsu_bus_buffer.scala 551:124] + wire _T_4457 = _T_4455 | _T_4456; // @[el2_lsu_bus_buffer.scala 551:122] + wire _T_4458 = _T_4395 & _T_4457; // @[el2_lsu_bus_buffer.scala 551:106] + wire [1:0] _T_4461 = _T_4450 ? 2'h2 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_4462 = _T_4458 ? 2'h3 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _GEN_409 = {{1'd0}, _T_4442}; // @[Mux.scala 27:72] + wire [1:0] _T_4464 = _GEN_409 | _T_4461; // @[Mux.scala 27:72] + wire [31:0] _T_4499 = _T_4434 ? buf_data_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4500 = _T_4442 ? buf_data_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4501 = _T_4450 ? buf_data_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4502 = _T_4458 ? buf_data_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4503 = _T_4499 | _T_4500; // @[Mux.scala 27:72] + wire [31:0] _T_4504 = _T_4503 | _T_4501; // @[Mux.scala 27:72] + wire [31:0] lsu_nonblock_load_data_lo = _T_4504 | _T_4502; // @[Mux.scala 27:72] + wire _T_4510 = buf_dual_0 | buf_dualhi_0; // @[el2_lsu_bus_buffer.scala 553:120] + wire _T_4511 = _T_4392 & _T_4510; // @[el2_lsu_bus_buffer.scala 553:105] + wire _T_4516 = buf_dual_1 | buf_dualhi_1; // @[el2_lsu_bus_buffer.scala 553:120] + wire _T_4517 = _T_4393 & _T_4516; // @[el2_lsu_bus_buffer.scala 553:105] + wire _T_4522 = buf_dual_2 | buf_dualhi_2; // @[el2_lsu_bus_buffer.scala 553:120] + wire _T_4523 = _T_4394 & _T_4522; // @[el2_lsu_bus_buffer.scala 553:105] + wire _T_4528 = buf_dual_3 | buf_dualhi_3; // @[el2_lsu_bus_buffer.scala 553:120] + wire _T_4529 = _T_4395 & _T_4528; // @[el2_lsu_bus_buffer.scala 553:105] + wire [31:0] _T_4530 = _T_4511 ? buf_data_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4531 = _T_4517 ? buf_data_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4532 = _T_4523 ? buf_data_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4533 = _T_4529 ? buf_data_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4534 = _T_4530 | _T_4531; // @[Mux.scala 27:72] + wire [31:0] _T_4535 = _T_4534 | _T_4532; // @[Mux.scala 27:72] + wire [31:0] lsu_nonblock_load_data_hi = _T_4535 | _T_4533; // @[Mux.scala 27:72] + wire _T_4537 = io_lsu_nonblock_load_data_tag == 2'h0; // @[el2_lsu_bus_buffer.scala 111:123] + wire _T_4538 = io_lsu_nonblock_load_data_tag == 2'h1; // @[el2_lsu_bus_buffer.scala 111:123] + wire _T_4539 = io_lsu_nonblock_load_data_tag == 2'h2; // @[el2_lsu_bus_buffer.scala 111:123] + wire _T_4540 = io_lsu_nonblock_load_data_tag == 2'h3; // @[el2_lsu_bus_buffer.scala 111:123] + wire [31:0] _T_4541 = _T_4537 ? buf_addr_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4542 = _T_4538 ? buf_addr_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4543 = _T_4539 ? buf_addr_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4544 = _T_4540 ? buf_addr_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4545 = _T_4541 | _T_4542; // @[Mux.scala 27:72] + wire [31:0] _T_4546 = _T_4545 | _T_4543; // @[Mux.scala 27:72] + wire [31:0] lsu_nonblock_addr_offset = _T_4546 | _T_4544; // @[Mux.scala 27:72] + wire [1:0] _T_4552 = _T_4537 ? buf_sz_0 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_4553 = _T_4538 ? buf_sz_1 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_4554 = _T_4539 ? buf_sz_2 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_4555 = _T_4540 ? buf_sz_3 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_4556 = _T_4552 | _T_4553; // @[Mux.scala 27:72] + wire [1:0] _T_4557 = _T_4556 | _T_4554; // @[Mux.scala 27:72] + wire [1:0] lsu_nonblock_sz = _T_4557 | _T_4555; // @[Mux.scala 27:72] + wire _T_4567 = _T_4537 & buf_unsign[0]; // @[Mux.scala 27:72] + wire _T_4568 = _T_4538 & buf_unsign[1]; // @[Mux.scala 27:72] + wire _T_4569 = _T_4539 & buf_unsign[2]; // @[Mux.scala 27:72] + wire _T_4570 = _T_4540 & buf_unsign[3]; // @[Mux.scala 27:72] + wire _T_4571 = _T_4567 | _T_4568; // @[Mux.scala 27:72] + wire _T_4572 = _T_4571 | _T_4569; // @[Mux.scala 27:72] + wire lsu_nonblock_unsign = _T_4572 | _T_4570; // @[Mux.scala 27:72] + wire [63:0] _T_4592 = {lsu_nonblock_load_data_hi,lsu_nonblock_load_data_lo}; // @[Cat.scala 29:58] + wire [35:0] _T_4593 = lsu_nonblock_addr_offset * 32'h8; // @[el2_lsu_bus_buffer.scala 558:121] + wire [63:0] lsu_nonblock_data_unalgn = _T_4592 >> _T_4593; // @[el2_lsu_bus_buffer.scala 558:92] + wire _T_4594 = ~io_lsu_nonblock_load_data_error; // @[el2_lsu_bus_buffer.scala 559:69] + wire _T_4596 = lsu_nonblock_sz == 2'h0; // @[el2_lsu_bus_buffer.scala 560:81] + wire _T_4597 = lsu_nonblock_unsign & _T_4596; // @[el2_lsu_bus_buffer.scala 560:63] + wire [31:0] _T_4599 = {24'h0,lsu_nonblock_data_unalgn[7:0]}; // @[Cat.scala 29:58] + wire _T_4600 = lsu_nonblock_sz == 2'h1; // @[el2_lsu_bus_buffer.scala 561:45] + wire _T_4601 = lsu_nonblock_unsign & _T_4600; // @[el2_lsu_bus_buffer.scala 561:26] + wire [31:0] _T_4603 = {16'h0,lsu_nonblock_data_unalgn[15:0]}; // @[Cat.scala 29:58] + wire _T_4604 = ~lsu_nonblock_unsign; // @[el2_lsu_bus_buffer.scala 562:6] + wire _T_4606 = _T_4604 & _T_4596; // @[el2_lsu_bus_buffer.scala 562:27] + wire [23:0] _T_4609 = lsu_nonblock_data_unalgn[7] ? 24'hffffff : 24'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_4611 = {_T_4609,lsu_nonblock_data_unalgn[7:0]}; // @[Cat.scala 29:58] + wire _T_4614 = _T_4604 & _T_4600; // @[el2_lsu_bus_buffer.scala 563:27] + wire [15:0] _T_4617 = lsu_nonblock_data_unalgn[15] ? 16'hffff : 16'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_4619 = {_T_4617,lsu_nonblock_data_unalgn[15:0]}; // @[Cat.scala 29:58] + wire _T_4620 = lsu_nonblock_sz == 2'h2; // @[el2_lsu_bus_buffer.scala 564:21] + wire [31:0] _T_4621 = _T_4597 ? _T_4599 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4622 = _T_4601 ? _T_4603 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4623 = _T_4606 ? _T_4611 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4624 = _T_4614 ? _T_4619 : 32'h0; // @[Mux.scala 27:72] + wire [63:0] _T_4625 = _T_4620 ? lsu_nonblock_data_unalgn : 64'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4626 = _T_4621 | _T_4622; // @[Mux.scala 27:72] + wire [31:0] _T_4627 = _T_4626 | _T_4623; // @[Mux.scala 27:72] + wire [31:0] _T_4628 = _T_4627 | _T_4624; // @[Mux.scala 27:72] + wire [63:0] _GEN_410 = {{32'd0}, _T_4628}; // @[Mux.scala 27:72] + wire [63:0] _T_4629 = _GEN_410 | _T_4625; // @[Mux.scala 27:72] + wire _T_4725 = obuf_valid & obuf_write; // @[el2_lsu_bus_buffer.scala 582:36] + wire _T_4726 = ~obuf_cmd_done; // @[el2_lsu_bus_buffer.scala 582:51] + wire _T_4727 = _T_4725 & _T_4726; // @[el2_lsu_bus_buffer.scala 582:49] + wire [31:0] _T_4731 = {obuf_addr[31:3],3'h0}; // @[Cat.scala 29:58] + wire [2:0] _T_4733 = {1'h0,obuf_sz}; // @[Cat.scala 29:58] + wire _T_4738 = ~obuf_data_done; // @[el2_lsu_bus_buffer.scala 594:50] + wire _T_4739 = _T_4725 & _T_4738; // @[el2_lsu_bus_buffer.scala 594:48] + wire [7:0] _T_4743 = obuf_write ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire _T_4746 = obuf_valid & _T_1268; // @[el2_lsu_bus_buffer.scala 599:36] + wire _T_4748 = _T_4746 & _T_1274; // @[el2_lsu_bus_buffer.scala 599:50] + wire _T_4760 = io_lsu_bus_clk_en_q & buf_error[0]; // @[el2_lsu_bus_buffer.scala 612:114] + wire _T_4762 = _T_4760 & buf_write[0]; // @[el2_lsu_bus_buffer.scala 612:129] + wire _T_4765 = io_lsu_bus_clk_en_q & buf_error[1]; // @[el2_lsu_bus_buffer.scala 612:114] + wire _T_4767 = _T_4765 & buf_write[1]; // @[el2_lsu_bus_buffer.scala 612:129] + wire _T_4770 = io_lsu_bus_clk_en_q & buf_error[2]; // @[el2_lsu_bus_buffer.scala 612:114] + wire _T_4772 = _T_4770 & buf_write[2]; // @[el2_lsu_bus_buffer.scala 612:129] + wire _T_4775 = io_lsu_bus_clk_en_q & buf_error[3]; // @[el2_lsu_bus_buffer.scala 612:114] + wire _T_4777 = _T_4775 & buf_write[3]; // @[el2_lsu_bus_buffer.scala 612:129] + wire _T_4778 = _T_2649 & _T_4762; // @[Mux.scala 27:72] + wire _T_4779 = _T_2671 & _T_4767; // @[Mux.scala 27:72] + wire _T_4780 = _T_2693 & _T_4772; // @[Mux.scala 27:72] + wire _T_4781 = _T_2715 & _T_4777; // @[Mux.scala 27:72] + wire _T_4782 = _T_4778 | _T_4779; // @[Mux.scala 27:72] + wire _T_4783 = _T_4782 | _T_4780; // @[Mux.scala 27:72] + wire _T_4793 = _T_2671 & buf_error[1]; // @[el2_lsu_bus_buffer.scala 613:98] + wire lsu_imprecise_error_store_tag = _T_4793 & buf_write[1]; // @[el2_lsu_bus_buffer.scala 613:113] + wire _T_4799 = ~io_lsu_imprecise_error_store_any; // @[el2_lsu_bus_buffer.scala 615:72] + wire _T_4801 = ~lsu_imprecise_error_store_tag; // @[el2_lsu_bus_buffer.scala 111:123] + wire [31:0] _T_4803 = _T_4801 ? buf_addr_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4804 = lsu_imprecise_error_store_tag ? buf_addr_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4805 = _T_4803 | _T_4804; // @[Mux.scala 27:72] + wire _T_4822 = bus_wcmd_sent | bus_wdata_sent; // @[el2_lsu_bus_buffer.scala 622:68] + wire _T_4825 = io_lsu_busreq_r & io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 623:48] + wire _T_4828 = ~io_lsu_axi_awready; // @[el2_lsu_bus_buffer.scala 626:48] + wire _T_4829 = io_lsu_axi_awvalid & _T_4828; // @[el2_lsu_bus_buffer.scala 626:46] + wire _T_4830 = ~io_lsu_axi_wready; // @[el2_lsu_bus_buffer.scala 626:92] + wire _T_4831 = io_lsu_axi_wvalid & _T_4830; // @[el2_lsu_bus_buffer.scala 626:90] + wire _T_4832 = _T_4829 | _T_4831; // @[el2_lsu_bus_buffer.scala 626:69] + wire _T_4833 = ~io_lsu_axi_arready; // @[el2_lsu_bus_buffer.scala 626:136] + wire _T_4834 = io_lsu_axi_arvalid & _T_4833; // @[el2_lsu_bus_buffer.scala 626:134] + wire _T_4838 = ~io_flush_r; // @[el2_lsu_bus_buffer.scala 630:75] + wire _T_4839 = io_lsu_busreq_m & _T_4838; // @[el2_lsu_bus_buffer.scala 630:73] + reg _T_4842; // @[el2_lsu_bus_buffer.scala 630:56] + rvclkhdr rvclkhdr ( // @[el2_lib.scala 472:23] + .io_l1clk(rvclkhdr_io_l1clk), + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en), + .io_scan_mode(rvclkhdr_io_scan_mode) + ); + rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 472:23] + .io_l1clk(rvclkhdr_1_io_l1clk), + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en), + .io_scan_mode(rvclkhdr_1_io_scan_mode) + ); + rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 472:23] + .io_l1clk(rvclkhdr_2_io_l1clk), + .io_clk(rvclkhdr_2_io_clk), + .io_en(rvclkhdr_2_io_en), + .io_scan_mode(rvclkhdr_2_io_scan_mode) + ); + rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 472:23] + .io_l1clk(rvclkhdr_3_io_l1clk), + .io_clk(rvclkhdr_3_io_clk), + .io_en(rvclkhdr_3_io_en), + .io_scan_mode(rvclkhdr_3_io_scan_mode) + ); + rvclkhdr rvclkhdr_4 ( // @[el2_lib.scala 472:23] + .io_l1clk(rvclkhdr_4_io_l1clk), + .io_clk(rvclkhdr_4_io_clk), + .io_en(rvclkhdr_4_io_en), + .io_scan_mode(rvclkhdr_4_io_scan_mode) + ); + rvclkhdr rvclkhdr_5 ( // @[el2_lib.scala 472:23] + .io_l1clk(rvclkhdr_5_io_l1clk), + .io_clk(rvclkhdr_5_io_clk), + .io_en(rvclkhdr_5_io_en), + .io_scan_mode(rvclkhdr_5_io_scan_mode) + ); + rvclkhdr rvclkhdr_6 ( // @[el2_lib.scala 472:23] + .io_l1clk(rvclkhdr_6_io_l1clk), + .io_clk(rvclkhdr_6_io_clk), + .io_en(rvclkhdr_6_io_en), + .io_scan_mode(rvclkhdr_6_io_scan_mode) + ); + rvclkhdr rvclkhdr_7 ( // @[el2_lib.scala 472:23] + .io_l1clk(rvclkhdr_7_io_l1clk), + .io_clk(rvclkhdr_7_io_clk), + .io_en(rvclkhdr_7_io_en), + .io_scan_mode(rvclkhdr_7_io_scan_mode) + ); + rvclkhdr rvclkhdr_8 ( // @[el2_lib.scala 472:23] + .io_l1clk(rvclkhdr_8_io_l1clk), + .io_clk(rvclkhdr_8_io_clk), + .io_en(rvclkhdr_8_io_en), + .io_scan_mode(rvclkhdr_8_io_scan_mode) + ); + rvclkhdr rvclkhdr_9 ( // @[el2_lib.scala 472:23] + .io_l1clk(rvclkhdr_9_io_l1clk), + .io_clk(rvclkhdr_9_io_clk), + .io_en(rvclkhdr_9_io_en), + .io_scan_mode(rvclkhdr_9_io_scan_mode) + ); + rvclkhdr rvclkhdr_10 ( // @[el2_lib.scala 472:23] + .io_l1clk(rvclkhdr_10_io_l1clk), + .io_clk(rvclkhdr_10_io_clk), + .io_en(rvclkhdr_10_io_en), + .io_scan_mode(rvclkhdr_10_io_scan_mode) + ); + rvclkhdr rvclkhdr_11 ( // @[el2_lib.scala 472:23] + .io_l1clk(rvclkhdr_11_io_l1clk), + .io_clk(rvclkhdr_11_io_clk), + .io_en(rvclkhdr_11_io_en), + .io_scan_mode(rvclkhdr_11_io_scan_mode) + ); + assign io_lsu_busreq_r = _T_4842; // @[el2_lsu_bus_buffer.scala 630:19] + assign io_lsu_bus_buffer_pend_any = |buf_numvld_pend_any; // @[el2_lsu_bus_buffer.scala 540:30] + assign io_lsu_bus_buffer_full_any = _T_4352 ? _T_4353 : _T_4354; // @[el2_lsu_bus_buffer.scala 541:30] + assign io_lsu_bus_buffer_empty_any = _T_4365 & _T_1156; // @[el2_lsu_bus_buffer.scala 542:31] + assign io_lsu_bus_idle_any = 1'h1; // @[el2_lsu_bus_buffer.scala 619:23] + assign io_ld_byte_hit_buf_lo = {_T_69,_T_58}; // @[el2_lsu_bus_buffer.scala 188:25] + assign io_ld_byte_hit_buf_hi = {_T_84,_T_73}; // @[el2_lsu_bus_buffer.scala 189:25] + assign io_ld_fwddata_buf_lo = _T_646[31:0]; // @[el2_lsu_bus_buffer.scala 214:24] + assign io_ld_fwddata_buf_hi = _T_741[31:0]; // @[el2_lsu_bus_buffer.scala 219:24] + assign io_lsu_imprecise_error_load_any = io_lsu_nonblock_load_data_error & _T_4799; // @[el2_lsu_bus_buffer.scala 615:35] + assign io_lsu_imprecise_error_store_any = _T_4783 | _T_4781; // @[el2_lsu_bus_buffer.scala 612:36] + assign io_lsu_imprecise_error_addr_any = io_lsu_imprecise_error_store_any ? _T_4805 : lsu_nonblock_addr_offset; // @[el2_lsu_bus_buffer.scala 616:35] + assign io_lsu_nonblock_load_valid_m = _T_4371 & _T_4372; // @[el2_lsu_bus_buffer.scala 544:32] + assign io_lsu_nonblock_load_tag_m = _T_1787 ? 2'h0 : _T_1823; // @[el2_lsu_bus_buffer.scala 545:30] + assign io_lsu_nonblock_load_inv_r = lsu_nonblock_load_valid_r & _T_4374; // @[el2_lsu_bus_buffer.scala 547:30] + assign io_lsu_nonblock_load_inv_tag_r = WrPtr0_r; // @[el2_lsu_bus_buffer.scala 548:34] + assign io_lsu_nonblock_load_data_valid = lsu_nonblock_load_data_ready & _T_4594; // @[el2_lsu_bus_buffer.scala 559:35] + assign io_lsu_nonblock_load_data_error = _T_4424 | _T_4422; // @[el2_lsu_bus_buffer.scala 550:35] + assign io_lsu_nonblock_load_data_tag = _T_4464 | _T_4462; // @[el2_lsu_bus_buffer.scala 551:33] + assign io_lsu_nonblock_load_data = _T_4629[31:0]; // @[el2_lsu_bus_buffer.scala 560:29] + assign io_lsu_pmu_bus_trxn = _T_4822 | _T_4717; // @[el2_lsu_bus_buffer.scala 622:23] + assign io_lsu_pmu_bus_misaligned = _T_4825 & io_lsu_commit_r; // @[el2_lsu_bus_buffer.scala 623:29] + assign io_lsu_pmu_bus_error = io_lsu_imprecise_error_load_any | io_lsu_imprecise_error_store_any; // @[el2_lsu_bus_buffer.scala 624:24] + assign io_lsu_pmu_bus_busy = _T_4832 | _T_4834; // @[el2_lsu_bus_buffer.scala 626:23] + assign io_lsu_axi_awvalid = _T_4727 & _T_1164; // @[el2_lsu_bus_buffer.scala 582:22] + assign io_lsu_axi_awid = {{1'd0}, _T_1772}; // @[el2_lsu_bus_buffer.scala 583:19] + assign io_lsu_axi_awaddr = obuf_sideeffect ? obuf_addr : _T_4731; // @[el2_lsu_bus_buffer.scala 584:21] + assign io_lsu_axi_awregion = obuf_addr[31:28]; // @[el2_lsu_bus_buffer.scala 588:23] + assign io_lsu_axi_awlen = 8'h0; // @[el2_lsu_bus_buffer.scala 589:20] + assign io_lsu_axi_awsize = obuf_sideeffect ? _T_4733 : 3'h2; // @[el2_lsu_bus_buffer.scala 585:21] + assign io_lsu_axi_awburst = 2'h1; // @[el2_lsu_bus_buffer.scala 590:22] + assign io_lsu_axi_awlock = 1'h0; // @[el2_lsu_bus_buffer.scala 592:21] + assign io_lsu_axi_awcache = obuf_sideeffect ? 4'h0 : 4'hf; // @[el2_lsu_bus_buffer.scala 587:22] + assign io_lsu_axi_awprot = 3'h0; // @[el2_lsu_bus_buffer.scala 586:21] + assign io_lsu_axi_awqos = 4'h0; // @[el2_lsu_bus_buffer.scala 591:20] + assign io_lsu_axi_wvalid = _T_4739 & _T_1164; // @[el2_lsu_bus_buffer.scala 594:21] + assign io_lsu_axi_wdata = obuf_data; // @[el2_lsu_bus_buffer.scala 596:20] + assign io_lsu_axi_wstrb = obuf_byteen & _T_4743; // @[el2_lsu_bus_buffer.scala 595:20] + assign io_lsu_axi_wlast = 1'h1; // @[el2_lsu_bus_buffer.scala 597:20] + assign io_lsu_axi_bready = 1'h1; // @[el2_lsu_bus_buffer.scala 610:21] + assign io_lsu_axi_arvalid = _T_4748 & _T_1164; // @[el2_lsu_bus_buffer.scala 599:22] + assign io_lsu_axi_arid = {{1'd0}, _T_1772}; // @[el2_lsu_bus_buffer.scala 600:19] + assign io_lsu_axi_araddr = obuf_sideeffect ? obuf_addr : _T_4731; // @[el2_lsu_bus_buffer.scala 601:21] + assign io_lsu_axi_arregion = obuf_addr[31:28]; // @[el2_lsu_bus_buffer.scala 605:23] + assign io_lsu_axi_arlen = 8'h0; // @[el2_lsu_bus_buffer.scala 606:20] + assign io_lsu_axi_arsize = obuf_sideeffect ? _T_4733 : 3'h3; // @[el2_lsu_bus_buffer.scala 602:21] + assign io_lsu_axi_arburst = 2'h1; // @[el2_lsu_bus_buffer.scala 607:22] + assign io_lsu_axi_arlock = 1'h0; // @[el2_lsu_bus_buffer.scala 609:21] + assign io_lsu_axi_arcache = obuf_sideeffect ? 4'h0 : 4'hf; // @[el2_lsu_bus_buffer.scala 604:22] + assign io_lsu_axi_arprot = 3'h0; // @[el2_lsu_bus_buffer.scala 603:21] + assign io_lsu_axi_arqos = 4'h0; // @[el2_lsu_bus_buffer.scala 608:20] + assign io_lsu_axi_rready = 1'h1; // @[el2_lsu_bus_buffer.scala 611:21] + assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 474:18] + assign rvclkhdr_io_en = _T_766 & _T_767; // @[el2_lib.scala 475:17] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 476:24] + assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 474:18] + assign rvclkhdr_1_io_en = _T_766 & _T_767; // @[el2_lib.scala 475:17] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 476:24] + assign rvclkhdr_2_io_clk = io_lsu_busm_clk; // @[el2_lib.scala 474:18] + assign rvclkhdr_2_io_en = _T_1165 & io_lsu_bus_clk_en; // @[el2_lib.scala 475:17] + assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 476:24] + assign rvclkhdr_3_io_clk = io_lsu_busm_clk; // @[el2_lib.scala 474:18] + assign rvclkhdr_3_io_en = _T_1165 & io_lsu_bus_clk_en; // @[el2_lib.scala 475:17] + assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 476:24] + assign rvclkhdr_4_io_clk = clock; // @[el2_lib.scala 474:18] + assign rvclkhdr_4_io_en = _T_3378 & buf_state_en_0; // @[el2_lib.scala 475:17] + assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[el2_lib.scala 476:24] + assign rvclkhdr_5_io_clk = clock; // @[el2_lib.scala 474:18] + assign rvclkhdr_5_io_en = _T_3571 & buf_state_en_1; // @[el2_lib.scala 475:17] + assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[el2_lib.scala 476:24] + assign rvclkhdr_6_io_clk = clock; // @[el2_lib.scala 474:18] + assign rvclkhdr_6_io_en = _T_3764 & buf_state_en_2; // @[el2_lib.scala 475:17] + assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[el2_lib.scala 476:24] + assign rvclkhdr_7_io_clk = clock; // @[el2_lib.scala 474:18] + assign rvclkhdr_7_io_en = _T_3957 & buf_state_en_3; // @[el2_lib.scala 475:17] + assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[el2_lib.scala 476:24] + assign rvclkhdr_8_io_clk = clock; // @[el2_lib.scala 474:18] + assign rvclkhdr_8_io_en = _T_3378 ? buf_state_en_0 : _GEN_70; // @[el2_lib.scala 475:17] + assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[el2_lib.scala 476:24] + assign rvclkhdr_9_io_clk = clock; // @[el2_lib.scala 474:18] + assign rvclkhdr_9_io_en = _T_3571 ? buf_state_en_1 : _GEN_146; // @[el2_lib.scala 475:17] + assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[el2_lib.scala 476:24] + assign rvclkhdr_10_io_clk = clock; // @[el2_lib.scala 474:18] + assign rvclkhdr_10_io_en = _T_3764 ? buf_state_en_2 : _GEN_222; // @[el2_lib.scala 475:17] + assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[el2_lib.scala 476:24] + assign rvclkhdr_11_io_clk = clock; // @[el2_lib.scala 474:18] + assign rvclkhdr_11_io_en = _T_3957 ? buf_state_en_3 : _GEN_298; // @[el2_lib.scala 475:17] + assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[el2_lib.scala 476:24] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + buf_addr_0 = _RAND_0[31:0]; + _RAND_1 = {1{`RANDOM}}; + _T_4210 = _RAND_1[0:0]; + _RAND_2 = {1{`RANDOM}}; + _T_4207 = _RAND_2[0:0]; + _RAND_3 = {1{`RANDOM}}; + _T_4204 = _RAND_3[0:0]; + _RAND_4 = {1{`RANDOM}}; + _T_4201 = _RAND_4[0:0]; + _RAND_5 = {1{`RANDOM}}; + buf_state_0 = _RAND_5[2:0]; + _RAND_6 = {1{`RANDOM}}; + buf_addr_1 = _RAND_6[31:0]; + _RAND_7 = {1{`RANDOM}}; + buf_state_1 = _RAND_7[2:0]; + _RAND_8 = {1{`RANDOM}}; + buf_addr_2 = _RAND_8[31:0]; + _RAND_9 = {1{`RANDOM}}; + buf_state_2 = _RAND_9[2:0]; + _RAND_10 = {1{`RANDOM}}; + buf_addr_3 = _RAND_10[31:0]; + _RAND_11 = {1{`RANDOM}}; + buf_state_3 = _RAND_11[2:0]; + _RAND_12 = {1{`RANDOM}}; + _T_4237 = _RAND_12[2:0]; + _RAND_13 = {1{`RANDOM}}; + _T_4235 = _RAND_13[2:0]; + _RAND_14 = {1{`RANDOM}}; + _T_4233 = _RAND_14[2:0]; + _RAND_15 = {1{`RANDOM}}; + _T_4231 = _RAND_15[2:0]; + _RAND_16 = {1{`RANDOM}}; + buf_ageQ_3 = _RAND_16[3:0]; + _RAND_17 = {1{`RANDOM}}; + _T_1772 = _RAND_17[1:0]; + _RAND_18 = {1{`RANDOM}}; + obuf_merge = _RAND_18[0:0]; + _RAND_19 = {1{`RANDOM}}; + obuf_tag1 = _RAND_19[1:0]; + _RAND_20 = {1{`RANDOM}}; + obuf_valid = _RAND_20[0:0]; + _RAND_21 = {1{`RANDOM}}; + obuf_wr_enQ = _RAND_21[0:0]; + _RAND_22 = {1{`RANDOM}}; + ibuf_addr = _RAND_22[31:0]; + _RAND_23 = {1{`RANDOM}}; + ibuf_write = _RAND_23[0:0]; + _RAND_24 = {1{`RANDOM}}; + ibuf_valid = _RAND_24[0:0]; + _RAND_25 = {1{`RANDOM}}; + ibuf_byteen = _RAND_25[3:0]; + _RAND_26 = {1{`RANDOM}}; + buf_ageQ_2 = _RAND_26[3:0]; + _RAND_27 = {1{`RANDOM}}; + buf_ageQ_1 = _RAND_27[3:0]; + _RAND_28 = {1{`RANDOM}}; + buf_ageQ_0 = _RAND_28[3:0]; + _RAND_29 = {1{`RANDOM}}; + _T_4238 = _RAND_29[3:0]; + _RAND_30 = {1{`RANDOM}}; + _T_4239 = _RAND_30[3:0]; + _RAND_31 = {1{`RANDOM}}; + _T_4240 = _RAND_31[3:0]; + _RAND_32 = {1{`RANDOM}}; + _T_4241 = _RAND_32[3:0]; + _RAND_33 = {1{`RANDOM}}; + ibuf_timer = _RAND_33[2:0]; + _RAND_34 = {1{`RANDOM}}; + ibuf_sideeffect = _RAND_34[0:0]; + _RAND_35 = {1{`RANDOM}}; + WrPtr1_r = _RAND_35[1:0]; + _RAND_36 = {1{`RANDOM}}; + WrPtr0_r = _RAND_36[1:0]; + _RAND_37 = {1{`RANDOM}}; + ibuf_tag = _RAND_37[1:0]; + _RAND_38 = {1{`RANDOM}}; + ibuf_data = _RAND_38[31:0]; + _RAND_39 = {1{`RANDOM}}; + ibuf_dualtag = _RAND_39[1:0]; + _RAND_40 = {1{`RANDOM}}; + ibuf_dual = _RAND_40[0:0]; + _RAND_41 = {1{`RANDOM}}; + ibuf_samedw = _RAND_41[0:0]; + _RAND_42 = {1{`RANDOM}}; + ibuf_nomerge = _RAND_42[0:0]; + _RAND_43 = {1{`RANDOM}}; + ibuf_unsign = _RAND_43[0:0]; + _RAND_44 = {1{`RANDOM}}; + ibuf_sz = _RAND_44[1:0]; + _RAND_45 = {1{`RANDOM}}; + obuf_wr_timer = _RAND_45[2:0]; + _RAND_46 = {1{`RANDOM}}; + buf_nomerge_0 = _RAND_46[0:0]; + _RAND_47 = {1{`RANDOM}}; + _T_4180 = _RAND_47[0:0]; + _RAND_48 = {1{`RANDOM}}; + _T_4177 = _RAND_48[0:0]; + _RAND_49 = {1{`RANDOM}}; + _T_4174 = _RAND_49[0:0]; + _RAND_50 = {1{`RANDOM}}; + _T_4171 = _RAND_50[0:0]; + _RAND_51 = {1{`RANDOM}}; + buf_dual_3 = _RAND_51[0:0]; + _RAND_52 = {1{`RANDOM}}; + buf_dual_2 = _RAND_52[0:0]; + _RAND_53 = {1{`RANDOM}}; + buf_dual_1 = _RAND_53[0:0]; + _RAND_54 = {1{`RANDOM}}; + buf_dual_0 = _RAND_54[0:0]; + _RAND_55 = {1{`RANDOM}}; + buf_samedw_3 = _RAND_55[0:0]; + _RAND_56 = {1{`RANDOM}}; + buf_samedw_2 = _RAND_56[0:0]; + _RAND_57 = {1{`RANDOM}}; + buf_samedw_1 = _RAND_57[0:0]; + _RAND_58 = {1{`RANDOM}}; + buf_samedw_0 = _RAND_58[0:0]; + _RAND_59 = {1{`RANDOM}}; + obuf_write = _RAND_59[0:0]; + _RAND_60 = {1{`RANDOM}}; + obuf_cmd_done = _RAND_60[0:0]; + _RAND_61 = {1{`RANDOM}}; + obuf_data_done = _RAND_61[0:0]; + _RAND_62 = {1{`RANDOM}}; + obuf_nosend = _RAND_62[0:0]; + _RAND_63 = {1{`RANDOM}}; + obuf_addr = _RAND_63[31:0]; + _RAND_64 = {1{`RANDOM}}; + buf_sz_0 = _RAND_64[1:0]; + _RAND_65 = {1{`RANDOM}}; + buf_sz_1 = _RAND_65[1:0]; + _RAND_66 = {1{`RANDOM}}; + buf_sz_2 = _RAND_66[1:0]; + _RAND_67 = {1{`RANDOM}}; + buf_sz_3 = _RAND_67[1:0]; + _RAND_68 = {1{`RANDOM}}; + obuf_sideeffect = _RAND_68[0:0]; + _RAND_69 = {1{`RANDOM}}; + obuf_rdrsp_pend = _RAND_69[0:0]; + _RAND_70 = {1{`RANDOM}}; + obuf_rdrsp_tag = _RAND_70[2:0]; + _RAND_71 = {1{`RANDOM}}; + buf_dualhi_3 = _RAND_71[0:0]; + _RAND_72 = {1{`RANDOM}}; + buf_dualhi_2 = _RAND_72[0:0]; + _RAND_73 = {1{`RANDOM}}; + buf_dualhi_1 = _RAND_73[0:0]; + _RAND_74 = {1{`RANDOM}}; + buf_dualhi_0 = _RAND_74[0:0]; + _RAND_75 = {1{`RANDOM}}; + obuf_sz = _RAND_75[1:0]; + _RAND_76 = {1{`RANDOM}}; + obuf_byteen = _RAND_76[7:0]; + _RAND_77 = {2{`RANDOM}}; + obuf_data = _RAND_77[63:0]; + _RAND_78 = {1{`RANDOM}}; + buf_rspageQ_0 = _RAND_78[3:0]; + _RAND_79 = {1{`RANDOM}}; + buf_rspageQ_1 = _RAND_79[3:0]; + _RAND_80 = {1{`RANDOM}}; + buf_rspageQ_2 = _RAND_80[3:0]; + _RAND_81 = {1{`RANDOM}}; + buf_rspageQ_3 = _RAND_81[3:0]; + _RAND_82 = {1{`RANDOM}}; + _T_4157 = _RAND_82[0:0]; + _RAND_83 = {1{`RANDOM}}; + _T_4155 = _RAND_83[0:0]; + _RAND_84 = {1{`RANDOM}}; + _T_4153 = _RAND_84[0:0]; + _RAND_85 = {1{`RANDOM}}; + _T_4151 = _RAND_85[0:0]; + _RAND_86 = {1{`RANDOM}}; + buf_ldfwdtag_0 = _RAND_86[1:0]; + _RAND_87 = {1{`RANDOM}}; + buf_dualtag_0 = _RAND_87[1:0]; + _RAND_88 = {1{`RANDOM}}; + buf_ldfwdtag_3 = _RAND_88[1:0]; + _RAND_89 = {1{`RANDOM}}; + buf_ldfwdtag_2 = _RAND_89[1:0]; + _RAND_90 = {1{`RANDOM}}; + buf_ldfwdtag_1 = _RAND_90[1:0]; + _RAND_91 = {1{`RANDOM}}; + buf_dualtag_1 = _RAND_91[1:0]; + _RAND_92 = {1{`RANDOM}}; + buf_dualtag_2 = _RAND_92[1:0]; + _RAND_93 = {1{`RANDOM}}; + buf_dualtag_3 = _RAND_93[1:0]; + _RAND_94 = {1{`RANDOM}}; + _T_4186 = _RAND_94[0:0]; + _RAND_95 = {1{`RANDOM}}; + _T_4189 = _RAND_95[0:0]; + _RAND_96 = {1{`RANDOM}}; + _T_4192 = _RAND_96[0:0]; + _RAND_97 = {1{`RANDOM}}; + _T_4195 = _RAND_97[0:0]; + _RAND_98 = {1{`RANDOM}}; + _T_4257 = _RAND_98[0:0]; + _RAND_99 = {1{`RANDOM}}; + _T_4253 = _RAND_99[0:0]; + _RAND_100 = {1{`RANDOM}}; + _T_4249 = _RAND_100[0:0]; + _RAND_101 = {1{`RANDOM}}; + _T_4245 = _RAND_101[0:0]; + _RAND_102 = {1{`RANDOM}}; + lsu_nonblock_load_valid_r = _RAND_102[0:0]; + _RAND_103 = {1{`RANDOM}}; + _T_4842 = _RAND_103[0:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + buf_addr_0 = 32'h0; + end + if (reset) begin + _T_4210 = 1'h0; + end + if (reset) begin + _T_4207 = 1'h0; + end + if (reset) begin + _T_4204 = 1'h0; + end + if (reset) begin + _T_4201 = 1'h0; + end + if (reset) begin + buf_state_0 = 3'h0; + end + if (reset) begin + buf_addr_1 = 32'h0; + end + if (reset) begin + buf_state_1 = 3'h0; + end + if (reset) begin + buf_addr_2 = 32'h0; + end + if (reset) begin + buf_state_2 = 3'h0; + end + if (reset) begin + buf_addr_3 = 32'h0; + end + if (reset) begin + buf_state_3 = 3'h0; + end + if (reset) begin + _T_4237 = 3'h0; + end + if (reset) begin + _T_4235 = 3'h0; + end + if (reset) begin + _T_4233 = 3'h0; + end + if (reset) begin + _T_4231 = 3'h0; + end + if (reset) begin + buf_ageQ_3 = 4'h0; + end + if (reset) begin + _T_1772 = 2'h0; + end + if (reset) begin + obuf_merge = 1'h0; + end + if (reset) begin + obuf_tag1 = 2'h0; + end + if (reset) begin + obuf_valid = 1'h0; + end + if (reset) begin + obuf_wr_enQ = 1'h0; + end + if (reset) begin + ibuf_addr = 32'h0; + end + if (reset) begin + ibuf_write = 1'h0; + end + if (reset) begin + ibuf_valid = 1'h0; + end + if (reset) begin + ibuf_byteen = 4'h0; + end + if (reset) begin + buf_ageQ_2 = 4'h0; + end + if (reset) begin + buf_ageQ_1 = 4'h0; + end + if (reset) begin + buf_ageQ_0 = 4'h0; + end + if (reset) begin + _T_4238 = 4'h0; + end + if (reset) begin + _T_4239 = 4'h0; + end + if (reset) begin + _T_4240 = 4'h0; + end + if (reset) begin + _T_4241 = 4'h0; + end + if (reset) begin + ibuf_timer = 3'h0; + end + if (reset) begin + ibuf_sideeffect = 1'h0; + end + if (reset) begin + WrPtr1_r = 2'h0; + end + if (reset) begin + WrPtr0_r = 2'h0; + end + if (reset) begin + ibuf_tag = 2'h0; + end + if (reset) begin + ibuf_data = 32'h0; + end + if (reset) begin + ibuf_dualtag = 2'h0; + end + if (reset) begin + ibuf_dual = 1'h0; + end + if (reset) begin + ibuf_samedw = 1'h0; + end + if (reset) begin + ibuf_nomerge = 1'h0; + end + if (reset) begin + ibuf_unsign = 1'h0; + end + if (reset) begin + ibuf_sz = 2'h0; + end + if (reset) begin + obuf_wr_timer = 3'h0; + end + if (reset) begin + buf_nomerge_0 = 1'h0; + end + if (reset) begin + _T_4180 = 1'h0; + end + if (reset) begin + _T_4177 = 1'h0; + end + if (reset) begin + _T_4174 = 1'h0; + end + if (reset) begin + _T_4171 = 1'h0; + end + if (reset) begin + buf_dual_3 = 1'h0; + end + if (reset) begin + buf_dual_2 = 1'h0; + end + if (reset) begin + buf_dual_1 = 1'h0; + end + if (reset) begin + buf_dual_0 = 1'h0; + end + if (reset) begin + buf_samedw_3 = 1'h0; + end + if (reset) begin + buf_samedw_2 = 1'h0; + end + if (reset) begin + buf_samedw_1 = 1'h0; + end + if (reset) begin + buf_samedw_0 = 1'h0; + end + if (reset) begin + obuf_write = 1'h0; + end + if (reset) begin + obuf_cmd_done = 1'h0; + end + if (reset) begin + obuf_data_done = 1'h0; + end + if (reset) begin + obuf_nosend = 1'h0; + end + if (reset) begin + obuf_addr = 32'h0; + end + if (reset) begin + buf_sz_0 = 2'h0; + end + if (reset) begin + buf_sz_1 = 2'h0; + end + if (reset) begin + buf_sz_2 = 2'h0; + end + if (reset) begin + buf_sz_3 = 2'h0; + end + if (reset) begin + obuf_sideeffect = 1'h0; + end + if (reset) begin + obuf_rdrsp_pend = 1'h0; + end + if (reset) begin + obuf_rdrsp_tag = 3'h0; + end + if (reset) begin + buf_dualhi_3 = 1'h0; + end + if (reset) begin + buf_dualhi_2 = 1'h0; + end + if (reset) begin + buf_dualhi_1 = 1'h0; + end + if (reset) begin + buf_dualhi_0 = 1'h0; + end + if (reset) begin + obuf_sz = 2'h0; + end + if (reset) begin + obuf_byteen = 8'h0; + end + if (reset) begin + obuf_data = 64'h0; + end + if (reset) begin + buf_rspageQ_0 = 4'h0; + end + if (reset) begin + buf_rspageQ_1 = 4'h0; + end + if (reset) begin + buf_rspageQ_2 = 4'h0; + end + if (reset) begin + buf_rspageQ_3 = 4'h0; + end + if (reset) begin + _T_4157 = 1'h0; + end + if (reset) begin + _T_4155 = 1'h0; + end + if (reset) begin + _T_4153 = 1'h0; + end + if (reset) begin + _T_4151 = 1'h0; + end + if (reset) begin + buf_ldfwdtag_0 = 2'h0; + end + if (reset) begin + buf_dualtag_0 = 2'h0; + end + if (reset) begin + buf_ldfwdtag_3 = 2'h0; + end + if (reset) begin + buf_ldfwdtag_2 = 2'h0; + end + if (reset) begin + buf_ldfwdtag_1 = 2'h0; + end + if (reset) begin + buf_dualtag_1 = 2'h0; + end + if (reset) begin + buf_dualtag_2 = 2'h0; + end + if (reset) begin + buf_dualtag_3 = 2'h0; + end + if (reset) begin + _T_4186 = 1'h0; + end + if (reset) begin + _T_4189 = 1'h0; + end + if (reset) begin + _T_4192 = 1'h0; + end + if (reset) begin + _T_4195 = 1'h0; + end + if (reset) begin + _T_4257 = 1'h0; + end + if (reset) begin + _T_4253 = 1'h0; + end + if (reset) begin + _T_4249 = 1'h0; + end + if (reset) begin + _T_4245 = 1'h0; + end + if (reset) begin + lsu_nonblock_load_valid_r = 1'h0; + end + if (reset) begin + _T_4842 = 1'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin + if (reset) begin + buf_addr_0 <= 32'h0; + end else if (ibuf_drainvec_vld[0]) begin + buf_addr_0 <= ibuf_addr; + end else if (_T_3193) begin + buf_addr_0 <= io_end_addr_r; + end else begin + buf_addr_0 <= io_lsu_addr_r; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4210 <= 1'h0; + end else if (buf_wr_en_3) begin + _T_4210 <= buf_write_in[3]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4207 <= 1'h0; + end else if (buf_wr_en_2) begin + _T_4207 <= buf_write_in[2]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4204 <= 1'h0; + end else if (buf_wr_en_1) begin + _T_4204 <= buf_write_in[1]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4201 <= 1'h0; + end else if (buf_wr_en_0) begin + _T_4201 <= buf_write_in[0]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_state_0 <= 3'h0; + end else if (buf_state_en_0) begin + if (_T_3378) begin + if (io_lsu_bus_clk_en) begin + buf_state_0 <= 3'h2; + end else begin + buf_state_0 <= 3'h1; + end + end else if (_T_3401) begin + if (io_dec_tlu_force_halt) begin + buf_state_0 <= 3'h0; + end else begin + buf_state_0 <= 3'h2; + end + end else if (_T_3405) begin + if (io_dec_tlu_force_halt) begin + buf_state_0 <= 3'h0; + end else if (_T_3409) begin + buf_state_0 <= 3'h5; + end else begin + buf_state_0 <= 3'h3; + end + end else if (_T_3439) begin + if (_T_3444) begin + buf_state_0 <= 3'h0; + end else if (_T_3452) begin + buf_state_0 <= 3'h4; + end else if (_T_3480) begin + buf_state_0 <= 3'h5; + end else begin + buf_state_0 <= 3'h6; + end + end else if (_T_3526) begin + if (io_dec_tlu_force_halt) begin + buf_state_0 <= 3'h0; + end else if (_T_3532) begin + buf_state_0 <= 3'h5; + end else begin + buf_state_0 <= 3'h6; + end + end else if (_T_3544) begin + if (io_dec_tlu_force_halt) begin + buf_state_0 <= 3'h0; + end else begin + buf_state_0 <= 3'h6; + end + end else begin + buf_state_0 <= 3'h0; + end + end + end + always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin + if (reset) begin + buf_addr_1 <= 32'h0; + end else if (ibuf_drainvec_vld[1]) begin + buf_addr_1 <= ibuf_addr; + end else if (_T_3202) begin + buf_addr_1 <= io_end_addr_r; + end else begin + buf_addr_1 <= io_lsu_addr_r; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_state_1 <= 3'h0; + end else if (buf_state_en_1) begin + if (_T_3571) begin + if (io_lsu_bus_clk_en) begin + buf_state_1 <= 3'h2; + end else begin + buf_state_1 <= 3'h1; + end + end else if (_T_3594) begin + if (io_dec_tlu_force_halt) begin + buf_state_1 <= 3'h0; + end else begin + buf_state_1 <= 3'h2; + end + end else if (_T_3598) begin + if (io_dec_tlu_force_halt) begin + buf_state_1 <= 3'h0; + end else if (_T_3409) begin + buf_state_1 <= 3'h5; + end else begin + buf_state_1 <= 3'h3; + end + end else if (_T_3632) begin + if (_T_3637) begin + buf_state_1 <= 3'h0; + end else if (_T_3645) begin + buf_state_1 <= 3'h4; + end else if (_T_3673) begin + buf_state_1 <= 3'h5; + end else begin + buf_state_1 <= 3'h6; + end + end else if (_T_3719) begin + if (io_dec_tlu_force_halt) begin + buf_state_1 <= 3'h0; + end else if (_T_3725) begin + buf_state_1 <= 3'h5; + end else begin + buf_state_1 <= 3'h6; + end + end else if (_T_3737) begin + if (io_dec_tlu_force_halt) begin + buf_state_1 <= 3'h0; + end else begin + buf_state_1 <= 3'h6; + end + end else begin + buf_state_1 <= 3'h0; + end + end + end + always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin + if (reset) begin + buf_addr_2 <= 32'h0; + end else if (ibuf_drainvec_vld[2]) begin + buf_addr_2 <= ibuf_addr; + end else if (_T_3211) begin + buf_addr_2 <= io_end_addr_r; + end else begin + buf_addr_2 <= io_lsu_addr_r; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_state_2 <= 3'h0; + end else if (buf_state_en_2) begin + if (_T_3764) begin + if (io_lsu_bus_clk_en) begin + buf_state_2 <= 3'h2; + end else begin + buf_state_2 <= 3'h1; + end + end else if (_T_3787) begin + if (io_dec_tlu_force_halt) begin + buf_state_2 <= 3'h0; + end else begin + buf_state_2 <= 3'h2; + end + end else if (_T_3791) begin + if (io_dec_tlu_force_halt) begin + buf_state_2 <= 3'h0; + end else if (_T_3409) begin + buf_state_2 <= 3'h5; + end else begin + buf_state_2 <= 3'h3; + end + end else if (_T_3825) begin + if (_T_3830) begin + buf_state_2 <= 3'h0; + end else if (_T_3838) begin + buf_state_2 <= 3'h4; + end else if (_T_3866) begin + buf_state_2 <= 3'h5; + end else begin + buf_state_2 <= 3'h6; + end + end else if (_T_3912) begin + if (io_dec_tlu_force_halt) begin + buf_state_2 <= 3'h0; + end else if (_T_3918) begin + buf_state_2 <= 3'h5; + end else begin + buf_state_2 <= 3'h6; + end + end else if (_T_3930) begin + if (io_dec_tlu_force_halt) begin + buf_state_2 <= 3'h0; + end else begin + buf_state_2 <= 3'h6; + end + end else begin + buf_state_2 <= 3'h0; + end + end + end + always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin + if (reset) begin + buf_addr_3 <= 32'h0; + end else if (ibuf_drainvec_vld[3]) begin + buf_addr_3 <= ibuf_addr; + end else if (_T_3220) begin + buf_addr_3 <= io_end_addr_r; + end else begin + buf_addr_3 <= io_lsu_addr_r; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_state_3 <= 3'h0; + end else if (buf_state_en_3) begin + if (_T_3957) begin + if (io_lsu_bus_clk_en) begin + buf_state_3 <= 3'h2; + end else begin + buf_state_3 <= 3'h1; + end + end else if (_T_3980) begin + if (io_dec_tlu_force_halt) begin + buf_state_3 <= 3'h0; + end else begin + buf_state_3 <= 3'h2; + end + end else if (_T_3984) begin + if (io_dec_tlu_force_halt) begin + buf_state_3 <= 3'h0; + end else if (_T_3409) begin + buf_state_3 <= 3'h5; + end else begin + buf_state_3 <= 3'h3; + end + end else if (_T_4018) begin + if (_T_4023) begin + buf_state_3 <= 3'h0; + end else if (_T_4031) begin + buf_state_3 <= 3'h4; + end else if (_T_4059) begin + buf_state_3 <= 3'h5; + end else begin + buf_state_3 <= 3'h6; + end + end else if (_T_4105) begin + if (io_dec_tlu_force_halt) begin + buf_state_3 <= 3'h0; + end else if (_T_4111) begin + buf_state_3 <= 3'h5; + end else begin + buf_state_3 <= 3'h6; + end + end else if (_T_4123) begin + if (io_dec_tlu_force_halt) begin + buf_state_3 <= 3'h0; + end else begin + buf_state_3 <= 3'h6; + end + end else begin + buf_state_3 <= 3'h0; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4237 <= 3'h0; + end else if (buf_wr_en_3) begin + _T_4237 <= buf_byteen_in_3; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4235 <= 3'h0; + end else if (buf_wr_en_2) begin + _T_4235 <= buf_byteen_in_2; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4233 <= 3'h0; + end else if (buf_wr_en_1) begin + _T_4233 <= buf_byteen_in_1; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4231 <= 3'h0; + end else if (buf_wr_en_0) begin + _T_4231 <= buf_byteen_in_0; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_ageQ_3 <= 4'h0; + end else begin + buf_ageQ_3 <= {_T_2401,_T_2324}; + end + end + always @(posedge io_lsu_busm_clk or posedge reset) begin + if (reset) begin + _T_1772 <= 2'h0; + end else if (obuf_wr_en) begin + if (ibuf_buf_byp) begin + _T_1772 <= WrPtr0_r; + end else begin + _T_1772 <= 2'h0; + end + end + end + always @(posedge io_lsu_busm_clk or posedge reset) begin + if (reset) begin + obuf_merge <= 1'h0; + end else if (obuf_wr_en) begin + obuf_merge <= obuf_merge_en; + end + end + always @(posedge io_lsu_busm_clk or posedge reset) begin + if (reset) begin + obuf_tag1 <= 2'h0; + end else if (obuf_wr_en) begin + if (ibuf_buf_byp) begin + obuf_tag1 <= WrPtr1_r; + end else begin + obuf_tag1 <= 2'h0; + end + end + end + always @(posedge io_lsu_busm_clk or posedge reset) begin + if (reset) begin + obuf_valid <= 1'h0; + end else begin + obuf_valid <= _T_1764 & obuf_rst; + end + end + always @(posedge io_lsu_busm_clk or posedge reset) begin + if (reset) begin + obuf_wr_enQ <= 1'h0; + end else begin + obuf_wr_enQ <= _T_1165 & io_lsu_bus_clk_en; + end + end + always @(posedge rvclkhdr_io_l1clk or posedge reset) begin + if (reset) begin + ibuf_addr <= 32'h0; + end else if (io_ldst_dual_r) begin + ibuf_addr <= io_end_addr_r; + end else begin + ibuf_addr <= io_lsu_addr_r; + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_write <= 1'h0; + end else if (ibuf_wr_en) begin + ibuf_write <= io_lsu_pkt_r_store; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + ibuf_valid <= 1'h0; + end else begin + ibuf_valid <= _T_910 & ibuf_rst; + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_byteen <= 4'h0; + end else if (ibuf_wr_en) begin + if (_T_779) begin + ibuf_byteen <= _T_794; + end else if (io_ldst_dual_r) begin + ibuf_byteen <= ldst_byteen_hi_r; + end else begin + ibuf_byteen <= ldst_byteen_lo_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_ageQ_2 <= 4'h0; + end else begin + buf_ageQ_2 <= {_T_2299,_T_2222}; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_ageQ_1 <= 4'h0; + end else begin + buf_ageQ_1 <= {_T_2197,_T_2120}; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_ageQ_0 <= 4'h0; + end else begin + buf_ageQ_0 <= {_T_2095,_T_2018}; + end + end + always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin + if (reset) begin + _T_4238 <= 4'h0; + end else begin + _T_4238 <= _GEN_79[3:0]; + end + end + always @(posedge rvclkhdr_9_io_l1clk or posedge reset) begin + if (reset) begin + _T_4239 <= 4'h0; + end else begin + _T_4239 <= _GEN_155[3:0]; + end + end + always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin + if (reset) begin + _T_4240 <= 4'h0; + end else begin + _T_4240 <= _GEN_231[3:0]; + end + end + always @(posedge rvclkhdr_11_io_l1clk or posedge reset) begin + if (reset) begin + _T_4241 <= 4'h0; + end else begin + _T_4241 <= _GEN_307[3:0]; + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_timer <= 3'h0; + end else if (ibuf_wr_en) begin + ibuf_timer <= 3'h0; + end else if (_T_828) begin + ibuf_timer <= _T_831; + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_sideeffect <= 1'h0; + end else if (_T_915) begin + ibuf_sideeffect <= io_is_sideeffects_r; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + WrPtr1_r <= 2'h0; + end else if (_T_1838) begin + WrPtr1_r <= 2'h0; + end else if (_T_1852) begin + WrPtr1_r <= 2'h1; + end else if (_T_1866) begin + WrPtr1_r <= 2'h2; + end else if (_T_1880) begin + WrPtr1_r <= 2'h3; + end else begin + WrPtr1_r <= 2'h0; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + WrPtr0_r <= 2'h0; + end else if (_T_1787) begin + WrPtr0_r <= 2'h0; + end else if (_T_1798) begin + WrPtr0_r <= 2'h1; + end else if (_T_1809) begin + WrPtr0_r <= 2'h2; + end else if (_T_1820) begin + WrPtr0_r <= 2'h3; + end else begin + WrPtr0_r <= 2'h0; + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_tag <= 2'h0; + end else if (_T_915) begin + if (!(_T_779)) begin + if (io_ldst_dual_r) begin + ibuf_tag <= WrPtr1_r; + end else begin + ibuf_tag <= WrPtr0_r; + end + end + end + end + always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin + if (reset) begin + ibuf_data <= 32'h0; + end else begin + ibuf_data <= {_T_827,_T_804}; + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_dualtag <= 2'h0; + end else if (_T_915) begin + ibuf_dualtag <= WrPtr0_r; + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_dual <= 1'h0; + end else if (_T_915) begin + ibuf_dual <= io_ldst_dual_r; + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_samedw <= 1'h0; + end else if (_T_915) begin + ibuf_samedw <= ldst_samedw_r; + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_nomerge <= 1'h0; + end else if (_T_915) begin + ibuf_nomerge <= io_no_dword_merge_r; + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_unsign <= 1'h0; + end else if (_T_915) begin + ibuf_unsign <= io_lsu_pkt_r_unsign; + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_sz <= 2'h0; + end else if (ibuf_wr_en) begin + ibuf_sz <= ibuf_sz_in; + end + end + always @(posedge io_lsu_busm_clk or posedge reset) begin + if (reset) begin + obuf_wr_timer <= 3'h0; + end else if (obuf_wr_en) begin + obuf_wr_timer <= 3'h0; + end else if (_T_983) begin + obuf_wr_timer <= _T_985; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_nomerge_0 <= 1'h0; + end else if (buf_wr_en_0) begin + buf_nomerge_0 <= buf_nomerge_in[0]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4180 <= 1'h0; + end else if (buf_wr_en_3) begin + _T_4180 <= buf_sideeffect_in[3]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4177 <= 1'h0; + end else if (buf_wr_en_2) begin + _T_4177 <= buf_sideeffect_in[2]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4174 <= 1'h0; + end else if (buf_wr_en_1) begin + _T_4174 <= buf_sideeffect_in[1]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4171 <= 1'h0; + end else if (buf_wr_en_0) begin + _T_4171 <= buf_sideeffect_in[0]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dual_3 <= 1'h0; + end else if (buf_wr_en_3) begin + buf_dual_3 <= buf_dual_in[3]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dual_2 <= 1'h0; + end else if (buf_wr_en_2) begin + buf_dual_2 <= buf_dual_in[2]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dual_1 <= 1'h0; + end else if (buf_wr_en_1) begin + buf_dual_1 <= buf_dual_in[1]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dual_0 <= 1'h0; + end else if (buf_wr_en_0) begin + buf_dual_0 <= buf_dual_in[0]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_samedw_3 <= 1'h0; + end else if (buf_wr_en_3) begin + buf_samedw_3 <= buf_samedw_in[3]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_samedw_2 <= 1'h0; + end else if (buf_wr_en_2) begin + buf_samedw_2 <= buf_samedw_in[2]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_samedw_1 <= 1'h0; + end else if (buf_wr_en_1) begin + buf_samedw_1 <= buf_samedw_in[1]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_samedw_0 <= 1'h0; + end else if (buf_wr_en_0) begin + buf_samedw_0 <= buf_samedw_in[0]; + end + end + always @(posedge io_lsu_busm_clk or posedge reset) begin + if (reset) begin + obuf_write <= 1'h0; + end else if (obuf_wr_en) begin + if (ibuf_buf_byp) begin + obuf_write <= io_lsu_pkt_r_store; + end else begin + obuf_write <= buf_write[0]; + end + end + end + always @(posedge io_lsu_busm_clk or posedge reset) begin + if (reset) begin + obuf_cmd_done <= 1'h0; + end else begin + obuf_cmd_done <= _T_1230 & _T_4714; + end + end + always @(posedge io_lsu_busm_clk or posedge reset) begin + if (reset) begin + obuf_data_done <= 1'h0; + end else begin + obuf_data_done <= _T_1230 & _T_4715; + end + end + always @(posedge io_lsu_busm_clk or posedge reset) begin + if (reset) begin + obuf_nosend <= 1'h0; + end else if (obuf_wr_en) begin + obuf_nosend <= obuf_nosend_in; + end + end + always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin + if (reset) begin + obuf_addr <= 32'h0; + end else if (ibuf_buf_byp) begin + obuf_addr <= io_lsu_addr_r; + end else begin + obuf_addr <= buf_addr_0; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_sz_0 <= 2'h0; + end else if (buf_wr_en_0) begin + if (ibuf_drainvec_vld[0]) begin + buf_sz_0 <= ibuf_sz; + end else begin + buf_sz_0 <= ibuf_sz_in; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_sz_1 <= 2'h0; + end else if (buf_wr_en_1) begin + if (ibuf_drainvec_vld[1]) begin + buf_sz_1 <= ibuf_sz; + end else begin + buf_sz_1 <= ibuf_sz_in; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_sz_2 <= 2'h0; + end else if (buf_wr_en_2) begin + if (ibuf_drainvec_vld[2]) begin + buf_sz_2 <= ibuf_sz; + end else begin + buf_sz_2 <= ibuf_sz_in; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_sz_3 <= 2'h0; + end else if (buf_wr_en_3) begin + if (ibuf_drainvec_vld[3]) begin + buf_sz_3 <= ibuf_sz; + end else begin + buf_sz_3 <= ibuf_sz_in; + end + end + end + always @(posedge io_lsu_busm_clk or posedge reset) begin + if (reset) begin + obuf_sideeffect <= 1'h0; + end else if (obuf_wr_en) begin + if (ibuf_buf_byp) begin + obuf_sideeffect <= io_is_sideeffects_r; + end else begin + obuf_sideeffect <= buf_sideeffect[0]; + end + end + end + always @(posedge io_lsu_busm_clk or posedge reset) begin + if (reset) begin + obuf_rdrsp_pend <= 1'h0; + end else begin + obuf_rdrsp_pend <= _T_1255 | _T_1259; + end + end + always @(posedge io_lsu_busm_clk or posedge reset) begin + if (reset) begin + obuf_rdrsp_tag <= 3'h0; + end else if (_T_1261) begin + obuf_rdrsp_tag <= obuf_tag0; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dualhi_3 <= 1'h0; + end else if (buf_wr_en_3) begin + buf_dualhi_3 <= buf_dualhi_in[3]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dualhi_2 <= 1'h0; + end else if (buf_wr_en_2) begin + buf_dualhi_2 <= buf_dualhi_in[2]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dualhi_1 <= 1'h0; + end else if (buf_wr_en_1) begin + buf_dualhi_1 <= buf_dualhi_in[1]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dualhi_0 <= 1'h0; + end else if (buf_wr_en_0) begin + buf_dualhi_0 <= buf_dualhi_in[0]; + end + end + always @(posedge io_lsu_busm_clk or posedge reset) begin + if (reset) begin + obuf_sz <= 2'h0; + end else if (obuf_wr_en) begin + if (ibuf_buf_byp) begin + obuf_sz <= ibuf_sz_in; + end else begin + obuf_sz <= buf_sz_0; + end + end + end + always @(posedge io_lsu_busm_clk or posedge reset) begin + if (reset) begin + obuf_byteen <= 8'h0; + end else if (obuf_wr_en) begin + obuf_byteen <= obuf_byteen_in; + end + end + always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin + if (reset) begin + obuf_data <= 64'h0; + end else begin + obuf_data <= {_T_1545,_T_1504}; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_rspageQ_0 <= 4'h0; + end else begin + buf_rspageQ_0 <= {_T_3023,_T_3012}; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_rspageQ_1 <= 4'h0; + end else begin + buf_rspageQ_1 <= {_T_3038,_T_3027}; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_rspageQ_2 <= 4'h0; + end else begin + buf_rspageQ_2 <= {_T_3053,_T_3042}; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_rspageQ_3 <= 4'h0; + end else begin + buf_rspageQ_3 <= {_T_3068,_T_3057}; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4157 <= 1'h0; + end else if (buf_ldfwd_en_3) begin + if (_T_3957) begin + _T_4157 <= 1'h0; + end else if (_T_3980) begin + _T_4157 <= 1'h0; + end else begin + _T_4157 <= _T_3984; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4155 <= 1'h0; + end else if (buf_ldfwd_en_2) begin + if (_T_3764) begin + _T_4155 <= 1'h0; + end else if (_T_3787) begin + _T_4155 <= 1'h0; + end else begin + _T_4155 <= _T_3791; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4153 <= 1'h0; + end else if (buf_ldfwd_en_1) begin + if (_T_3571) begin + _T_4153 <= 1'h0; + end else if (_T_3594) begin + _T_4153 <= 1'h0; + end else begin + _T_4153 <= _T_3598; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4151 <= 1'h0; + end else if (buf_ldfwd_en_0) begin + if (_T_3378) begin + _T_4151 <= 1'h0; + end else if (_T_3401) begin + _T_4151 <= 1'h0; + end else begin + _T_4151 <= _T_3405; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_ldfwdtag_0 <= 2'h0; + end else if (buf_ldfwd_en_0) begin + if (_T_3378) begin + buf_ldfwdtag_0 <= 2'h0; + end else if (_T_3401) begin + buf_ldfwdtag_0 <= 2'h0; + end else if (_T_3405) begin + buf_ldfwdtag_0 <= obuf_rdrsp_tag[1:0]; + end else begin + buf_ldfwdtag_0 <= 2'h0; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dualtag_0 <= 2'h0; + end else if (buf_wr_en_0) begin + if (ibuf_drainvec_vld[0]) begin + buf_dualtag_0 <= ibuf_dualtag; + end else if (_T_3193) begin + buf_dualtag_0 <= WrPtr0_r; + end else begin + buf_dualtag_0 <= WrPtr1_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_ldfwdtag_3 <= 2'h0; + end else if (buf_ldfwd_en_3) begin + if (_T_3957) begin + buf_ldfwdtag_3 <= 2'h0; + end else if (_T_3980) begin + buf_ldfwdtag_3 <= 2'h0; + end else if (_T_3984) begin + buf_ldfwdtag_3 <= obuf_rdrsp_tag[1:0]; + end else begin + buf_ldfwdtag_3 <= 2'h0; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_ldfwdtag_2 <= 2'h0; + end else if (buf_ldfwd_en_2) begin + if (_T_3764) begin + buf_ldfwdtag_2 <= 2'h0; + end else if (_T_3787) begin + buf_ldfwdtag_2 <= 2'h0; + end else if (_T_3791) begin + buf_ldfwdtag_2 <= obuf_rdrsp_tag[1:0]; + end else begin + buf_ldfwdtag_2 <= 2'h0; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_ldfwdtag_1 <= 2'h0; + end else if (buf_ldfwd_en_1) begin + if (_T_3571) begin + buf_ldfwdtag_1 <= 2'h0; + end else if (_T_3594) begin + buf_ldfwdtag_1 <= 2'h0; + end else if (_T_3598) begin + buf_ldfwdtag_1 <= obuf_rdrsp_tag[1:0]; + end else begin + buf_ldfwdtag_1 <= 2'h0; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dualtag_1 <= 2'h0; + end else if (buf_wr_en_1) begin + if (ibuf_drainvec_vld[1]) begin + buf_dualtag_1 <= ibuf_dualtag; + end else if (_T_3202) begin + buf_dualtag_1 <= WrPtr0_r; + end else begin + buf_dualtag_1 <= WrPtr1_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dualtag_2 <= 2'h0; + end else if (buf_wr_en_2) begin + if (ibuf_drainvec_vld[2]) begin + buf_dualtag_2 <= ibuf_dualtag; + end else if (_T_3211) begin + buf_dualtag_2 <= WrPtr0_r; + end else begin + buf_dualtag_2 <= WrPtr1_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dualtag_3 <= 2'h0; + end else if (buf_wr_en_3) begin + if (ibuf_drainvec_vld[3]) begin + buf_dualtag_3 <= ibuf_dualtag; + end else if (_T_3220) begin + buf_dualtag_3 <= WrPtr0_r; + end else begin + buf_dualtag_3 <= WrPtr1_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4186 <= 1'h0; + end else if (buf_wr_en_0) begin + _T_4186 <= buf_unsign_in[0]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4189 <= 1'h0; + end else if (buf_wr_en_1) begin + _T_4189 <= buf_unsign_in[1]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4192 <= 1'h0; + end else if (buf_wr_en_2) begin + _T_4192 <= buf_unsign_in[2]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4195 <= 1'h0; + end else if (buf_wr_en_3) begin + _T_4195 <= buf_unsign_in[3]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4257 <= 1'h0; + end else begin + _T_4257 <= _T_4255 & buf_rst_3; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4253 <= 1'h0; + end else begin + _T_4253 <= _T_4251 & buf_rst_2; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4249 <= 1'h0; + end else begin + _T_4249 <= _T_4247 & buf_rst_1; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4245 <= 1'h0; + end else begin + _T_4245 <= _T_4243 & buf_rst_0; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + lsu_nonblock_load_valid_r <= 1'h0; + end else begin + lsu_nonblock_load_valid_r <= io_lsu_nonblock_load_valid_m; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + _T_4842 <= 1'h0; + end else begin + _T_4842 <= _T_4839 & _T_4372; + end + end +endmodule diff --git a/src/main/scala/include/el2_bundle.scala b/src/main/scala/include/el2_bundle.scala index 0fca8cec..ce98a498 100644 --- a/src/main/scala/include/el2_bundle.scala +++ b/src/main/scala/include/el2_bundle.scala @@ -169,19 +169,19 @@ class el2_alu_pkt_t extends Bundle { } class el2_lsu_pkt_t extends Bundle { - val fast_int = UInt(1.W) - val by = UInt(1.W) - val half = UInt(1.W) - val word = UInt(1.W) - val dword = UInt(1.W) // for dma - val load = UInt(1.W) - val store = UInt(1.W) - val unsign = UInt(1.W) - val dma = UInt(1.W) // dma pkt - val store_data_bypass_d = UInt(1.W) - val load_ldst_bypass_d = UInt(1.W) - val store_data_bypass_m = UInt(1.W) - val valid = UInt(1.W) + val fast_int = Bool() + val by = Bool() + val half = Bool() + val word = Bool() + val dword = Bool() // for dma + val load = Bool() + val store = Bool() + val unsign = Bool() + val dma = Bool() // dma pkt + val store_data_bypass_d = Bool() + val load_ldst_bypass_d = Bool() + val store_data_bypass_m = Bool() + val valid = Bool() } class el2_lsu_error_pkt_t extends Bundle { diff --git a/src/main/scala/lsu/el2_lsu_bus_buffer.scala b/src/main/scala/lsu/el2_lsu_bus_buffer.scala index f90e33ca..e2ee3ebf 100644 --- a/src/main/scala/lsu/el2_lsu_bus_buffer.scala +++ b/src/main/scala/lsu/el2_lsu_bus_buffer.scala @@ -1,9 +1,8 @@ -/* package lsu +package lsu import chisel3._ import chisel3.util._ import lib._ import include._ -import snapshot._ import chisel3.experimental.{ChiselEnum, chiselName} import chisel3.util.ImplicitConversions.intToUInt @@ -108,6 +107,8 @@ class el2_lsu_bus_buffer extends Module with RequireAsyncReset with el2_lib { val lsu_axi_rready = Output(Bool()) }) + def indexing(in : UInt, index : UInt) = Mux1H((0 until math.pow(2, index.getWidth).asInstanceOf[Int]).map(i=>(index===i.U)->in(i))) + def indexing(in : Vec[UInt], index : UInt) = Mux1H((0 until math.pow(2, index.getWidth).asInstanceOf[Int]).map(i=>(index===i.U)->in(i))) val DEPTH = LSU_NUM_NBLOAD val DEPTH_LOG2 = LSU_NUM_NBLOAD_WIDTH @@ -127,20 +128,73 @@ class el2_lsu_bus_buffer extends Module with RequireAsyncReset with el2_lib { val ld_addr_hitvec_lo = (0 until DEPTH).map(i => (io.lsu_addr_m(31, 2) === buf_addr(i)(31, 2)) & buf_write(i) & (buf_state(i) =/= idle_C) & io.lsu_busreq_m) val ld_addr_hitvec_hi = (0 until DEPTH).map(i => (io.end_addr_m(31, 2) === buf_addr(i)(31, 2)) & buf_write(i) & (buf_state(i) =/= idle_C) & io.lsu_busreq_m) val ld_byte_hitvecfn_lo = Wire(Vec(4, UInt(DEPTH.W))) - val ld_byte_ibuf_hit_lo = WireInit(UInt(4.W)) + val ld_byte_ibuf_hit_lo = WireInit(UInt(4.W), 0.U) val ld_byte_hitvecfn_hi = Wire(Vec(4, UInt(DEPTH.W))) - val ld_byte_ibuf_hit_hi = WireInit(UInt(4.W)) + val ld_byte_ibuf_hit_hi = WireInit(UInt(4.W), 0.U) val buf_byteen = Wire(Vec(DEPTH, UInt(4.W))) + buf_byteen := buf_byteen.map(i=>0.U) + val buf_nxtstate = Wire(Vec(DEPTH, UInt(3.W))) + buf_nxtstate := buf_nxtstate.map(i=>0.U) + val buf_wr_en = Wire(Vec(DEPTH, Bool())) + buf_wr_en := buf_wr_en.map(i=> false.B) + val buf_data_en = Wire(Vec(DEPTH, Bool())) + buf_data_en := buf_data_en.map(i=> false.B) + val buf_state_bus_en = Wire(Vec(DEPTH, Bool())) + buf_state_bus_en := buf_state_bus_en.map(i=> false.B) + val buf_ldfwd_in = Wire(Vec(DEPTH, Bool())) + buf_ldfwd_in := buf_ldfwd_in.map(i=> false.B) + val buf_ldfwd_en = Wire(Vec(DEPTH, Bool())) + buf_ldfwd_en := buf_ldfwd_en.map(i=> false.B) + val buf_data_in = Wire(Vec(DEPTH, UInt(DEPTH.W))) + buf_data_in := buf_data_in.map(i=> 0.U) + val buf_ldfwdtag_in = Wire(Vec(DEPTH, UInt(DEPTH_LOG2.W))) + buf_ldfwdtag_in := buf_ldfwdtag_in.map(i=> 0.U) + val buf_error_en = Wire(Vec(DEPTH, Bool())) + buf_error_en := buf_error_en.map(i=> false.B) + val bus_rsp_read_error = WireInit(Bool(), false.B) + val bus_rsp_rdata = WireInit(UInt(64.W), 0.U) + val bus_rsp_write_error = WireInit(Bool(), false.B) + val buf_dualtag = Wire(Vec(DEPTH, UInt(DEPTH_LOG2.W))) + buf_dualtag := buf_dualtag.map(i=> 0.U) + val buf_ldfwd = WireInit(UInt(DEPTH.W), 0.U) + val buf_resp_state_bus_en = Wire(Vec(DEPTH, Bool())) + buf_resp_state_bus_en := buf_resp_state_bus_en.map(i=> false.B) + val any_done_wait_state = WireInit(Bool(), false.B) + val bus_rsp_write = WireInit(Bool(), false.B) + val bus_rsp_write_tag = WireInit(UInt(LSU_BUS_TAG.W), 0.U) + val buf_ldfwdtag = Wire(Vec(DEPTH, UInt(DEPTH_LOG2.W))) + buf_ldfwdtag := buf_ldfwdtag.map(i=> 0.U) + val buf_rst = Wire(Vec(DEPTH, Bool())) + buf_rst := buf_rst.map(i=> false.B) + val ibuf_drainvec_vld = WireInit(UInt(DEPTH.W), 0.U) + val buf_byteen_in = Wire(Vec(DEPTH, UInt(3.W))) + buf_byteen_in := buf_byteen_in.map(i=> 0.U) + val buf_addr_in = Wire(Vec(DEPTH, UInt(32.W))) + buf_addr_in := buf_addr_in.map(i=> 0.U) + val buf_dual_in = WireInit(UInt(DEPTH.W), 0.U) + val buf_samedw_in = WireInit(UInt(DEPTH.W), 0.U) + val buf_nomerge_in = WireInit(UInt(DEPTH.W), 0.U) + val buf_dualhi_in = WireInit(UInt(DEPTH.W), 0.U) + val buf_dualtag_in = Wire(Vec(DEPTH, UInt(DEPTH_LOG2.W))) + buf_dualtag_in := buf_dualtag_in.map(i=> 0.U) + val buf_sideeffect_in = WireInit(UInt(DEPTH.W), 0.U) + val buf_unsign_in = WireInit(UInt(DEPTH.W), 0.U) + val buf_sz_in = Wire(Vec(DEPTH, UInt(2.W))) + buf_sz_in := buf_sz_in.map(i=> 0.U) + val buf_write_in = WireInit(UInt(DEPTH.W), 0.U) + val buf_unsign = WireInit(UInt(DEPTH.W), 0.U) + val buf_error = WireInit(UInt(DEPTH.W), 0.U) - io.ld_byte_hit_buf_lo := (0 until 4).map(i => ld_byte_hitvecfn_lo(i).orR | ld_byte_ibuf_hit_lo(i)).reverse.reduce(Cat(_, _)) - io.ld_byte_hit_buf_hi := (0 until 4).map(i => ld_byte_hitvecfn_hi(i).orR | ld_byte_ibuf_hit_hi(i)).reverse.reduce(Cat(_, _)) + io.ld_byte_hit_buf_lo := (0 until 4).map(i => (ld_byte_hitvecfn_lo(i).orR | ld_byte_ibuf_hit_lo(i)).asUInt).reverse.reduce(Cat(_, _)) + io.ld_byte_hit_buf_hi := (0 until 4).map(i => (ld_byte_hitvecfn_hi(i).orR | ld_byte_ibuf_hit_hi(i)).asUInt).reverse.reduce(Cat(_, _)) - val ld_byte_hitvec_lo = (0 until 4).map(j => (0 until DEPTH).map(i => ld_addr_hitvec_lo(i) & buf_byteen(i)(j) & ldst_byteen_lo_m(j)).reverse.reduce(Cat(_, _))) - val ld_byte_hitvec_hi = (0 until 4).map(j => (0 until DEPTH).map(i => ld_addr_hitvec_hi(i) & buf_byteen(i)(j) & ldst_byteen_hi_m(j)).reverse.reduce(Cat(_, _))) + val ld_byte_hitvec_lo = (0 until 4).map(j => (0 until DEPTH).map(i => (ld_addr_hitvec_lo(i) & buf_byteen(i)(j) & ldst_byteen_lo_m(j)).asUInt).reverse.reduce(Cat(_, _))) + val ld_byte_hitvec_hi = (0 until 4).map(j => (0 until DEPTH).map(i => (ld_addr_hitvec_hi(i) & buf_byteen(i)(j) & ldst_byteen_hi_m(j)).asUInt).reverse.reduce(Cat(_, _))) val buf_age_younger = Wire(Vec(DEPTH, UInt(DEPTH.W))) - ld_byte_hitvecfn_lo := (0 until 4).map(j => (0 until DEPTH).map(i => ld_byte_hitvec_lo(j)(i) & !(ld_byte_hitvec_lo(j) & buf_age_younger(i)).orR & !ld_byte_ibuf_hit_lo(j)).reverse.reduce(Cat(_, _))) - ld_byte_hitvecfn_hi := (0 until 4).map(j => (0 until DEPTH).map(i => ld_byte_hitvec_hi(j)(i) & !(ld_byte_hitvec_hi(j) & buf_age_younger(i)).orR & !ld_byte_ibuf_hit_hi(j)).reverse.reduce(Cat(_, _))) + buf_age_younger := buf_age_younger.map(i=> 0.U) + ld_byte_hitvecfn_lo := (0 until 4).map(j => (0 until DEPTH).map(i => (ld_byte_hitvec_lo(j)(i) & !(ld_byte_hitvec_lo(j) & buf_age_younger(i)).orR & !ld_byte_ibuf_hit_lo(j)).asUInt).reverse.reduce(Cat(_, _))) + ld_byte_hitvecfn_hi := (0 until 4).map(j => (0 until DEPTH).map(i => (ld_byte_hitvec_hi(j)(i) & !(ld_byte_hitvec_hi(j) & buf_age_younger(i)).orR & !ld_byte_ibuf_hit_hi(j)).asUInt).reverse.reduce(Cat(_, _))) val ibuf_addr = WireInit(UInt(32.W), 0.U) val ibuf_write = WireInit(Bool(), false.B) @@ -154,8 +208,8 @@ class el2_lsu_bus_buffer extends Module with RequireAsyncReset with el2_lib { ld_byte_ibuf_hit_hi := ld_addr_ibuf_hit_hi & ibuf_byteen(i) & ldst_byteen_hi_m(i) } val buf_data = Wire(Vec(DEPTH, UInt(32.W))) - - val fwd_data = WireInit(UInt(32.W)) + buf_data := buf_data.map(i=> 0.U) + val fwd_data = WireInit(UInt(32.W), 0.U) io.ld_fwddata_buf_lo := Cat((0 until DEPTH).map(i => Fill(8, ld_byte_hitvecfn_lo(3)(i)) & buf_data(i)(31, 23)).reduce(_ | _), (0 until DEPTH).map(i => Fill(8, ld_byte_hitvecfn_lo(2)(i)) & buf_data(i)(23, 16)).reduce(_ | _), @@ -190,7 +244,7 @@ class el2_lsu_bus_buffer extends Module with RequireAsyncReset with el2_lib { val ibuf_timer = WireInit(UInt(TIMER_LOG2.W), 0.U) val ibuf_merge_en = WireInit(Bool(), false.B) val ibuf_merge_in = WireInit(Bool(), false.B) - val ibuf_drain_vld = ibuf_valid & (((ibuf_wr_en | (ibuf_timer === TIMER_MAX.U)) & !(ibuf_merge_en & ibuf_merge_in)) + ibuf_drain_vld := ibuf_valid & (((ibuf_wr_en | (ibuf_timer === TIMER_MAX.U)) & !(ibuf_merge_en & ibuf_merge_in)) | ibuf_byp | ibuf_force_drain | ibuf_sideeffect | !ibuf_write | bus_coalescing_disable) val ibuf_tag = WireInit(UInt(DEPTH_LOG2.W), 0.U) val WrPtr1_r = WireInit(UInt(DEPTH_LOG2.W), 0.U) @@ -206,430 +260,378 @@ class el2_lsu_bus_buffer extends Module with RequireAsyncReset with el2_lib { val ibuf_data_in = (0 until 4).map(i => Mux(ibuf_merge_en & ibuf_merge_in, Mux(ldst_byteen_lo_r(i), store_data_lo_r((8 * i) + 7, 8 * i), ibuf_data((8 * i) + 7, 8 * i)), ibuf_data((8 * i) + 7, 8 * i))).reverse.reduce(Cat(_, _)) + val ibuf_timer_in = Mux(ibuf_wr_en, 0.U, Mux((ibuf_timer(Mux(ld_byte_ibuf_hit_lo(i),ibuf_data(i*8+7,i*8),Mux1H((0 until DEPTH).map(j =>(ld_byte_hitvecfn_lo(i)(j)) -> buf_data(j)(i*8+7,i*8)))))).reverse.reduce(Cat(_,_)) -//// io.ld_fwddata_buf_hi := (0 until 4).map(i =>(Mux(ld_byte_ibuf_hit_hi(i),ibuf_data(i*8+7,i*8),Mux1H((0 until DEPTH).map(j =>(ld_byte_hitvecfn_hi(i)(j)) -> buf_data(j)(i*8+7,i*8)))))).reverse.reduce(Cat(_,_)) -//// -//// ///////////////////////////////////////////////////////////////////////////// -//// bus_coalescing_disable := io.dec_tlu_wb_coalescing_disable | pt.BUILD_AHB_LITE -//// ldst_byteen_r := Mux1H(Seq( -//// io.lsu_pkt_r.word.asBool -> 15.U(4.W), -//// io.lsu_pkt_r.half.asBool -> 3.U(4.W), -//// io.lsu_pkt_r.by.asBool -> 1.U(4.W) -//// )) -//// val ldst_byteen_extended_r = Cat(Fill(4,0.U),ldst_byteen_r(3,0)) << io.lsu_addr_r(1,0) -//// val store_data_extended_r = Cat(Fill(32,0.U),io.store_data_r(31,0)) << (8.U*io.lsu_addr_r(1,0)) -//// ldst_byteen_hi_r := ldst_byteen_extended_r(7,4) -//// ldst_byteen_lo_r := ldst_byteen_extended_r(3,0) -//// store_data_hi_r := store_data_extended_r(63,32) -//// store_data_lo_r := store_data_extended_r(31, 0) -//// ldst_samedw_r := io.lsu_addr_r(3) === io.end_addr_r(3) -//// is_aligned_r := Mux1H(Seq( -//// io.lsu_pkt_r.by.asBool -> true.B, -//// io.lsu_pkt_r.half.asBool -> (io.lsu_addr_r(0).asUInt === 0.U), -//// io.lsu_pkt_r.word.asBool -> (io.lsu_addr_r(1,0).asUInt === 0.U) -//// )) -//// //////////////////////////////////////////////////////////////////////////// -//// ibuf_byp := (io.lsu_busreq_r & (io.lsu_pkt_r.load | io.no_word_merge_r) & !ibuf_valid).asBool -//// ibuf_wr_en := (io.lsu_busreq_r & io.lsu_commit_r & !ibuf_byp).asBool -//// ibuf_rst := ((ibuf_drain_vld & !ibuf_wr_en) | io.dec_tlu_force_halt).asBool -//// ibuf_force_drain := (io.lsu_busreq_m & !io.lsu_busreq_r & ibuf_valid & (io.lsu_pkt_m.load | (ibuf_addr(31,2) =/= io.lsu_addr_m(31,2)))).asBool -//// ibuf_drain_vld := ibuf_valid & (((ibuf_wr_en | (ibuf_timer === (TIMER_MAX.asUInt(TIMER_LOG2.W)))) & !(ibuf_merge_en & ibuf_merge_in)) | -//// ibuf_byp | ibuf_force_drain | ibuf_sideeffect | !ibuf_write | bus_coalescing_disable) -//// ibuf_tag_in := Mux((ibuf_merge_en & ibuf_merge_in), ibuf_tag(DEPTH_LOG2-1,0),Mux(io.ldst_dual_r,WrPtr1_r,WrPtr0_r)) -//// ibuf_dualtag_in := WrPtr0_r(DEPTH_LOG2-1,0) -//// ibuf_sz_in := Cat(io.lsu_pkt_r.word,io.lsu_pkt_r.half) -//// ibuf_addr_in := Mux(io.ldst_dual_r,io.end_addr_r,io.lsu_addr_r) -//// ibuf_byteen_in := Mux(ibuf_merge_en & ibuf_merge_in, ibuf_byteen(3,0) | ldst_byteen_lo_r(3,0), Mux(io.ldst_dual_r, ldst_byteen_hi_r(3,0), ldst_byteen_lo_r(3,0))) -//// ibuf_data_in := (0 until 4).map(i =>(Mux((ibuf_merge_en & ibuf_merge_in),Mux(ldst_byteen_lo_r(i),store_data_lo_r((8*i)+7,(8*i)) , ibuf_data((8*i)+7,(8*i))),Mux(io.ldst_dual_r, store_data_hi_r((8*i)+7,(8*i)), store_data_lo_r((8*i)+7,(8*i)))))).reverse.reduce(Cat(_,_)) -//// ibuf_timer_in := Mux(ibuf_wr_en, 0.U, Mux(ibuf_timer < (TIMER_MAX.asUInt(TIMER_LOG2.W)), ibuf_timer+1.U, ibuf_timer)) -//// ibuf_byteen_out := (0 until 4).map(i =>(Mux((ibuf_merge_en & ~ibuf_merge_in),ibuf_byteen(i) | ldst_byteen_lo_r(i), ibuf_byteen(i))).asUInt).reverse.reduce(Cat(_,_)) -//// ibuf_data_out := (0 until 4).map(i =>(Mux((ibuf_merge_en & ~ibuf_merge_in),Mux(ldst_byteen_lo_r(i),store_data_lo_r((8*i)+7,(8*i)) , ibuf_data((8*i)+7,(8*i))),ibuf_data(i*8+7,i*8)))).reverse.reduce(Cat(_,_)) -//// ibuf_merge_en := io.lsu_busreq_r & io.lsu_commit_r & io.lsu_pkt_r.store & ibuf_valid & ibuf_write & io.lsu_addr_r(31,2)===ibuf_addr(31,2) & ~io.is_sideeffects_r & ~bus_coalescing_disable -//// ibuf_merge_in := ~io.ldst_dual_r.asUInt() -//// -//// withClock(io.lsu_free_c2_clk){ -//// ibuf_valid := RegNext(Mux(ibuf_wr_en.asBool(),1.U ,ibuf_valid) & !ibuf_rst, false.B) -//// ibuf_timer := RegNext(ibuf_timer_in ,init = 0.U) -//// } -//// withClock(io.lsu_bus_ibuf_c1_clk) { -//// ibuf_dual := RegEnable(io.ldst_dual_r ,init = 0.U, ibuf_wr_en) -//// ibuf_samedw := RegEnable(ldst_samedw_r ,init = 0.U, ibuf_wr_en) -//// ibuf_nomerge := RegEnable(io.no_dword_merge_r ,init = 0.U, ibuf_wr_en) -//// ibuf_sideeffect := RegEnable(io.is_sideeffects_r ,init = 0.U, ibuf_wr_en) -//// ibuf_unsign := RegEnable(io.lsu_pkt_r.unsign ,init = 0.U, ibuf_wr_en) -//// ibuf_write := RegEnable(io.lsu_pkt_r.store ,init = 0.U, ibuf_wr_en) -//// ibuf_sz := RegEnable(ibuf_sz_in(1, 0) ,init = 0.U, ibuf_wr_en) -//// ibuf_byteen := RegEnable(ibuf_byteen_in ,init = 0.U, ibuf_wr_en) -//// ibuf_addr := RegEnable(ibuf_addr_in(31, 0) ,init = 0.U, ibuf_wr_en) -//// ibuf_data := RegEnable(ibuf_data_in(31, 0) ,init = 0.U, ibuf_wr_en) -//// ibuf_tag := RegEnable(ibuf_tag_in ,init = 0.U, ibuf_wr_en) -//// ibuf_dualtag := RegEnable(ibuf_dualtag_in ,init = 0.U, ibuf_wr_en) -//// } -//// /////////////////////////////////////////////////////////////////////////////////////// -//// -//// ibuf_buf_byp := (ibuf_byp & (buf_numvld_pend_any(3,0) === 0.U) & (~io.lsu_pkt_r.store | io.no_dword_merge_r)) -//// obuf_force_wr_en := io.lsu_busreq_m & ~io.lsu_busreq_r & ~ibuf_valid & (buf_numvld_cmd_any(3,0) === 1.U(4.W)) & (io.lsu_addr_m(31,2) =/= buf_addr(CmdPtr0)(31,2)) -//// obuf_wr_wait := (buf_numvld_wrcmd_any(3,0) === 1.U(4.W)) & (buf_numvld_cmd_any(3,0) === 1.U(4.W)) & (obuf_wr_timer =/= (TIMER_MAX.asUInt(TIMER_LOG2.W))) & -//// ~bus_coalescing_disable & ~buf_nomerge(CmdPtr0) & ~buf_sideeffect(CmdPtr0) & ~obuf_force_wr_en -//// obuf_wr_en := ((ibuf_buf_byp & io.lsu_commit_r & ~(io.is_sideeffects_r & bus_sideeffect_pend)) | -//// ((buf_state(CmdPtr0) === cmd_C) & found_cmdptr0 & ~buf_cmd_state_bus_en(CmdPtr0) & ~(buf_sideeffect(CmdPtr0) & bus_sideeffect_pend) & -//// (~(buf_dual(CmdPtr0) & buf_samedw(CmdPtr0) & ~buf_write(CmdPtr0)) | found_cmdptr1 | buf_nomerge(CmdPtr0) | obuf_force_wr_en))) & -//// (bus_cmd_ready | ~obuf_valid | obuf_nosend) & ~obuf_wr_wait & ~lsu_bus_cntr_overflow & ~bus_addr_match_pending & io.lsu_bus_clk_en -//// obuf_rst := ((bus_cmd_sent | (obuf_valid & obuf_nosend)) & ~obuf_wr_en & io.lsu_bus_clk_en) | io.dec_tlu_force_halt -//// obuf_write_in := Mux(ibuf_buf_byp, io.lsu_pkt_r.store, buf_write(CmdPtr0)) -//// obuf_nosend_in := (obuf_addr_in(31,3) === obuf_addr(31,3)) & obuf_aligned_in & ~obuf_sideeffect & ~obuf_write & ~obuf_write_in & ~io.dec_tlu_external_ldfwd_disable & -//// ((obuf_valid & ~obuf_nosend) | (obuf_rdrsp_pend & ~(bus_rsp_read & (bus_rsp_read_tag === obuf_rdrsp_tag)))) -//// obuf_rdrsp_pend_in := (~(obuf_wr_en & ~obuf_nosend_in) & obuf_rdrsp_pend & ~(bus_rsp_read & (bus_rsp_read_tag === obuf_rdrsp_tag))) | ((bus_cmd_sent & ~obuf_write) & ~io.dec_tlu_force_halt) -//// obuf_sideeffect_in := Mux(ibuf_buf_byp, io.is_sideeffects_r, buf_sideeffect(CmdPtr0)) -//// obuf_aligned_in := Mux(ibuf_buf_byp, is_aligned_r, (obuf_sz_in(1,0) === 0.U(2.W) | (obuf_sz_in(0) & ~obuf_addr_in(0)) | (obuf_sz_in(1) & ~(obuf_addr_in(1,0).orR)))) -//// obuf_addr_in := Mux(ibuf_buf_byp, io.lsu_addr_r, buf_addr(CmdPtr0)) -//// obuf_data_in := (0 until 8).map(i =>(Mux((obuf_merge_en & obuf_byteen1_in(i)),obuf_data1_in((8*i)+7,(8*i)), obuf_data0_in((8*i)+7,(8*i)))).asUInt).reverse.reduce(Cat(_,_)) -//// obuf_sz_in := Mux(ibuf_buf_byp, Cat(io.lsu_pkt_r.word,io.lsu_pkt_r.half), buf_sz(CmdPtr0)) -//// obuf_byteen_in := (0 until 8).map(i =>(obuf_byteen0_in(i) | (obuf_merge_en & obuf_byteen1_in(i))).asUInt).reverse.reduce(Cat(_,_)) -//// obuf_merge_in := obuf_merge_en -//// obuf_cmd_done_in := ~(obuf_wr_en | obuf_rst) & (obuf_cmd_done | bus_wcmd_sent ) -//// obuf_data_done_in := ~(obuf_wr_en | obuf_rst) & (obuf_data_done | bus_wdata_sent) -//// obuf_tag0_in := Mux(ibuf_buf_byp, WrPtr0_r, CmdPtr0) -//// obuf_tag1_in := Mux(ibuf_buf_byp, WrPtr1_r, CmdPtr0) -//// obuf_rdrsp_tag_in := Mux((bus_cmd_sent & ~obuf_write), obuf_tag0(pt1.LSU_BUS_TAG-1,0), obuf_rdrsp_tag(pt1.LSU_BUS_TAG-1,0)) -//// -//// obuf_merge_en := ((CmdPtr0 =/= CmdPtr1) & found_cmdptr0 & found_cmdptr1 & (buf_state(CmdPtr0) === cmd_C) & (buf_state(CmdPtr1) === cmd_C) & -//// ~buf_cmd_state_bus_en(CmdPtr0) & ~buf_sideeffect(CmdPtr0) & -//// ((buf_write(CmdPtr0) & buf_write(CmdPtr1) & (buf_addr(CmdPtr0)(31,3) === buf_addr(CmdPtr1)(31,3)) & ~bus_coalescing_disable & ~pt.BUILD_AXI_NATIVE) | -//// (~buf_write(CmdPtr0) & buf_dual(CmdPtr0) & ~buf_dualhi(CmdPtr0) & buf_samedw(CmdPtr0)))) | -//// (ibuf_buf_byp & ldst_samedw_r & io.ldst_dual_r) -//// obuf_wr_timer_in := Mux(obuf_wr_en, 0.U, Mux(((buf_numvld_cmd_any > 0.U(4.W)) & (obuf_wr_timer < TIMER_MAX.asUInt(TIMER_LOG2.W))), (obuf_wr_timer + 1.U), obuf_wr_timer)) -//// obuf_byteen0_in := Mux(ibuf_buf_byp, Mux(io.lsu_addr_r(2), Cat(ldst_byteen_lo_r(3,0),0.U(4.W)), Cat(0.U(4.W),ldst_byteen_lo_r(3,0))), Mux(buf_addr(CmdPtr0)(2), Cat(buf_byteen(CmdPtr0),0.U(4.W)), Cat(0.U(4.W),buf_byteen(CmdPtr0)))) -//// obuf_byteen1_in := Mux(ibuf_buf_byp, Mux(io.end_addr_r(2), Cat(ldst_byteen_hi_r(3,0),0.U(4.W)), Cat(0.U(4.W),ldst_byteen_hi_r(3,0))), Mux(buf_addr(CmdPtr1)(2), Cat(buf_byteen(CmdPtr1),0.U(4.W)), Cat(0.U(4.W),buf_byteen(CmdPtr1)))) -//// obuf_data0_in := Mux(ibuf_buf_byp, Mux(io.lsu_addr_r(2), Cat(store_data_lo_r(31,0),0.U(32.W)), Cat(0.U(32.W),store_data_lo_r(31,0))), Mux(buf_addr(CmdPtr0)(2), Cat(buf_data(CmdPtr0), 0.U(32.W)), Cat(0.U(32.W), buf_data(CmdPtr0)))) -//// obuf_data1_in := Mux(ibuf_buf_byp, Mux(io.lsu_addr_r(2), Cat(store_data_hi_r(31,0),0.U(32.W)), Cat(0.U(32.W),store_data_hi_r(31,0))), Mux(buf_addr(CmdPtr1)(2), Cat(buf_data(CmdPtr1), 0.U(32.W)), Cat(0.U(32.W), buf_data(CmdPtr1)))) -//// -//// obuf_addr := RegEnable(obuf_addr_in , init = 0.U, obuf_wr_en) -//// obuf_data := RegEnable(obuf_data_in , init = 0.U, obuf_wr_en) -//// withClock(io.lsu_busm_clk){ -//// obuf_rdrsp_pend := RegNext(obuf_rdrsp_pend_in , init = 0.U) -//// obuf_rdrsp_tag := RegNext(obuf_rdrsp_tag_in , init = 0.U) -//// obuf_cmd_done := RegNext(obuf_cmd_done_in , init = 0.U) -//// obuf_data_done := RegNext(obuf_data_done_in , init = 0.U) -//// obuf_wr_timer := RegNext(obuf_wr_timer_in , init = 0.U) -//// obuf_wr_enQ := RegNext(obuf_wr_en , init = 0.U) -//// } -//// withClock(io.lsu_free_c2_clk){ -//// obuf_valid := RegNext(Mux(obuf_wr_en.asBool(),1.U ,obuf_valid) & !obuf_rst, false.B) -//// obuf_nosend := RegEnable(obuf_nosend_in , init = 0.U, obuf_wr_en) -//// } -//// withClock(io.lsu_bus_obuf_c1_clk){ -//// obuf_write := RegEnable(obuf_write_in , init = 0.U, obuf_wr_en) -//// obuf_sideeffect := RegEnable(obuf_sideeffect_in , init = 0.U, obuf_wr_en) -//// obuf_sz := RegEnable(obuf_sz_in , init = 0.U, obuf_wr_en) -//// obuf_byteen := RegEnable(obuf_byteen_in , init = 0.U, obuf_wr_en) -//// obuf_merge := RegEnable(obuf_merge_in , init = 0.U, obuf_wr_en) -//// obuf_tag0 := RegEnable(obuf_tag0_in , init = 0.U, obuf_wr_en) -//// obuf_tag1 := RegEnable(obuf_tag1_in , init = 0.U, obuf_wr_en) -//// } -//// //////////////////////////////////////////////////////////////////////////////////// -//// -//// // WrPtr0_m := PriorityMux((0 until DEPTH).map(i =>(((buf_state(i)===IDLE.U) & !((ibuf_valid & (ibuf_tag====i.U)) | (io.lsu_busreq_r & ((WrPtr0_r === i) | (io.ldst_dual_r & (WrPtr1_r === i)))))).asBool -> i.asUInt(DEPTH_LOG2.W)))) -//// val test_seq = (0 until DEPTH).map(i=>((buf_state(i)===idle_C) & !((ibuf_valid & ibuf_tag===i.U) | -//// (io.lsu_busreq_r & ((WrPtr0_r===i.U) | (io.ldst_dual_r & (WrPtr1_r===i.U)))))).asBool() -> i.U) -//// WrPtr0_m := MuxCase(0.U, test_seq) -//// val test_seq2 = (0 until DEPTH).map(i=>((buf_state(i) === idle_C) & !((ibuf_valid & (ibuf_tag === i.U)) | -//// (io.lsu_busreq_m & (WrPtr0_m === i.U)) | (io.lsu_busreq_r & (WrPtr0_r === i.U) | -//// (io.ldst_dual_r & (WrPtr1_r === i.U))))).asBool -> i.U) -//// WrPtr1_m := MuxCase(0.U, test_seq2) -//// -//// for { -//// i <- 0 until DEPTH -//// j <- 0 until DEPTH -//// }{ -//// CmdPtr0Dec(i) := ~(buf_age(i).asUInt.orR()) & (buf_state(i) === cmd_C) & ~buf_cmd_state_bus_en(i) -//// CmdPtr1Dec(i) := ~((buf_age(i).asUInt & ~CmdPtr0Dec.asUInt).orR()) & ~CmdPtr0Dec(i) & (buf_state(i) === cmd_C) & ~buf_cmd_state_bus_en(i) -//// RspPtrDec(i) := ~(buf_rsp_pickage(i).asUInt.orR()) & (buf_state(i) === done_wait_C) -//// -//// buf_age_in(i)(j) := (((buf_state(i) === idle_C) & buf_state_en(i)) & -//// (((buf_state(j) === wait_C) | ((buf_state(j) === cmd_C) & ~buf_cmd_state_bus_en(j))) | -//// (ibuf_drain_vld & io.lsu_busreq_r & (ibuf_byp | io.ldst_dual_r) & (i === WrPtr0_r) & (j === ibuf_tag)) | -//// (ibuf_byp & io.lsu_busreq_r & io.ldst_dual_r & (i === WrPtr1_r) & (j === WrPtr0_r)))) | buf_age(i)(j) -//// -//// buf_age(i)(j) := buf_ageQ(i)(j) & ~((buf_state(j) === cmd_C) & buf_cmd_state_bus_en(j)) -//// buf_age_younger(i)(j) := Mux(i.asUInt(DEPTH_LOG2.W) === j.asUInt(DEPTH_LOG2.W), 0.U, (~buf_age(i)(j) & (buf_state(j) =/= idle_C))) -//// -//// buf_rspage_set(i)(j) := ((buf_state(i) === idle_C) & buf_state_en(i)) & (~((buf_state(j) === idle_C) | (buf_state(j) === done_C)) | -//// (ibuf_drain_vld & io.lsu_busreq_r & (ibuf_byp | io.ldst_dual_r) & (i === WrPtr0_r) & (j === ibuf_tag)) | -//// (ibuf_byp & io.lsu_busreq_r & io.ldst_dual_r & (i === WrPtr1_r) & (j === WrPtr0_r))) -//// buf_rspage_in(i)(j) := buf_rspage_set(i)(j) | buf_rspage(i)(j) -//// buf_rspage(i)(j) := buf_rspageQ(i)(j) & ~((buf_state(j) === done_C) | (buf_state(j) === idle_C)) -//// buf_rsp_pickage(i)(j) := buf_rspageQ(i)(j) & (buf_state(j) === done_wait_C) -//// } -//// -//// CmdPtr0 := PriorityEncoderOH(CmdPtr0Dec.asUInt) -//// CmdPtr1 := PriorityEncoderOH(CmdPtr1Dec.asUInt) -//// RspPtr := PriorityEncoderOH(RspPtrDec.asUInt) -//// found_cmdptr0 := CmdPtr0Dec.reduce(_|_) -//// found_cmdptr1 := CmdPtr1Dec.reduce(_|_) -//// -//// ////////////////////////// FSM /////////////////////////////////////// -//// for (i <- 0 until DEPTH){ -//// buf_nxtstate(i) := idle_C -//// buf_state_en(i) := 0.U -//// buf_cmd_state_bus_en(i) := 0.U -//// buf_resp_state_bus_en(i) := 0.U -//// buf_state_bus_en(i) := 0.U -//// buf_wr_en(i) := 0.U -//// buf_data_in(i) := 0.U -//// buf_data_en(i) := 0.U -//// buf_error_en(i) := 0.U -//// buf_rst(i) := 0.U -//// buf_ldfwd_en(i) := 0.U -//// buf_ldfwd_in(i) := 0.U -//// buf_ldfwdtag_in(i) := 0.U -//// -//// ibuf_drainvec_vld(i) := (ibuf_drain_vld & (i === ibuf_tag)) -//// buf_byteen_in(i) := Mux(ibuf_drainvec_vld(i), ibuf_byteen_out(3,0), Mux((ibuf_byp & io.ldst_dual_r & (i === WrPtr1_r)).asBool(), ldst_byteen_hi_r(3, 0), ldst_byteen_lo_r(3, 0))) -//// buf_addr_in(i) := Mux(ibuf_drainvec_vld(i), ibuf_addr(31,0), Mux((ibuf_byp & io.ldst_dual_r & (i === WrPtr1_r)).asBool(), io.end_addr_r(31, 0), io.lsu_addr_r(31, 0))) -//// buf_dual_in(i) := Mux(ibuf_drainvec_vld(i), ibuf_dual, io.ldst_dual_r) -//// buf_samedw_in(i) := Mux(ibuf_drainvec_vld(i), ibuf_samedw, ldst_samedw_r) -//// buf_nomerge_in(i) := Mux(ibuf_drainvec_vld(i), (ibuf_nomerge | ibuf_force_drain), io.no_dword_merge_r) -//// buf_dualhi_in(i) := Mux(ibuf_drainvec_vld(i), ibuf_dual, (ibuf_byp & io.ldst_dual_r & (i === WrPtr1_r))) -//// buf_dualtag_in(i) := Mux(ibuf_drainvec_vld(i), ibuf_dualtag, Mux((ibuf_byp & io.ldst_dual_r & (i === WrPtr1_r)).asBool(), WrPtr0_r, WrPtr1_r)) -//// buf_sideeffect_in(i) := Mux(ibuf_drainvec_vld(i), ibuf_sideeffect, io.is_sideeffects_r) -//// buf_unsign_in(i) := Mux(ibuf_drainvec_vld(i), ibuf_unsign, io.lsu_pkt_r.unsign) -//// buf_sz_in(i) := Mux(ibuf_drainvec_vld(i), ibuf_sz, Cat(io.lsu_pkt_r.word, io.lsu_pkt_r.half)) -//// buf_write_in(i) := Mux(ibuf_drainvec_vld(i), ibuf_write, io.lsu_pkt_r.store) -//// -//// // Buffer entry state machine -//// switch (buf_state(i)){ -//// is (idle_C) { -//// buf_nxtstate(i) := Mux(io.lsu_bus_clk_en.asBool(), cmd_C, wait_C) -//// buf_state_en(i) := (io.lsu_busreq_r & io.lsu_commit_r & (((ibuf_byp | io.ldst_dual_r) & !ibuf_merge_en & (i === WrPtr0_r)) | (ibuf_byp & io.ldst_dual_r & (i === WrPtr1_r)))) | (ibuf_drain_vld & (i === ibuf_tag)) -//// buf_wr_en(i) := buf_state_en(i) -//// buf_data_en(i) := buf_state_en(i) -//// buf_data_in(i) := Mux((ibuf_drain_vld & (i === ibuf_tag)).asBool(), ibuf_data_out(31, 0), store_data_lo_r(31, 0)) -//// } -//// is (wait_C) { -//// buf_nxtstate(i) := Mux(io.dec_tlu_force_halt.asBool(), idle_C, cmd_C) -//// buf_state_en(i) := io.lsu_bus_clk_en | io.dec_tlu_force_halt -//// } -//// is (cmd_C) { -//// buf_nxtstate(i) := Mux(io.dec_tlu_force_halt.asBool(), idle_C, Mux((obuf_nosend & bus_rsp_read & (bus_rsp_read_tag === obuf_rdrsp_tag)), done_wait_C, resp_C)) -//// buf_cmd_state_bus_en(i) := ((obuf_tag0 === i.asUInt(pt1.LSU_BUS_TAG.W)) | (obuf_merge & (obuf_tag1 === i.asUInt(pt1.LSU_BUS_TAG.W)))) & obuf_valid & obuf_wr_enQ -//// buf_state_bus_en(i) := buf_cmd_state_bus_en(i) -//// buf_state_en(i) := (buf_state_bus_en(i) & io.lsu_bus_clk_en) | io.dec_tlu_force_halt -//// buf_ldfwd_in(i) := 1.U(1.W) -//// buf_ldfwd_en(i) := buf_state_en(i) & !buf_write(i) & obuf_nosend & !io.dec_tlu_force_halt -//// buf_ldfwdtag_in(i) := (obuf_rdrsp_tag(pt1.LSU_BUS_TAG - 2,0)).asUInt -//// buf_data_en(i) := buf_state_bus_en(i) & io.lsu_bus_clk_en & obuf_nosend & bus_rsp_read -//// buf_error_en(i) := buf_state_bus_en(i) & io.lsu_bus_clk_en & obuf_nosend & bus_rsp_read_error -//// buf_data_in(i) := Mux(buf_error_en(i), bus_rsp_rdata(31,0), Mux(buf_addr(i)(2), bus_rsp_rdata(63, 32), bus_rsp_rdata(31, 0))) -//// } -//// is (resp_C){ -//// buf_nxtstate(i) := Mux((io.dec_tlu_force_halt | (buf_write(i) & ~(pt.BUILD_AXI_NATIVE & bus_rsp_write_error))).asBool(), idle_C, -//// Mux((buf_dual(i) & ~ buf_samedw(i) & ~ buf_write(i) &(buf_state(buf_dualtag(i)) =/= done_partial_C)), done_partial_C, -//// Mux((buf_ldfwd(i) | any_done_wait_state | (buf_dual(i) & ~ buf_samedw(i) & ~ buf_write(i) & buf_ldfwd(buf_dualtag(i)) & (buf_state(buf_dualtag(i)) === done_partial_C) & any_done_wait_state)), done_wait_C, done_C))) -//// buf_resp_state_bus_en(i):= (bus_rsp_write & (bus_rsp_write_tag === (i.asUInt(pt1.LSU_BUS_TAG.W)))) | -//// (bus_rsp_read & ((bus_rsp_read_tag === (i.asUInt(pt1.LSU_BUS_TAG.W))) | -//// (buf_ldfwd(i) & (bus_rsp_read_tag === (buf_ldfwdtag(i)))) | -//// (buf_dual(i) & buf_dualhi(i) & ~buf_write(i) & buf_samedw(i) & (bus_rsp_read_tag === (buf_dualtag(i)))))) -//// buf_state_bus_en(i) := buf_resp_state_bus_en(i) -//// buf_state_en(i) := (buf_state_bus_en(i) & io.lsu_bus_clk_en) | io.dec_tlu_force_halt -//// buf_data_en(i) := buf_state_bus_en(i) & bus_rsp_read & io.lsu_bus_clk_en -//// buf_error_en(i) := buf_state_bus_en(i) & io.lsu_bus_clk_en & ((bus_rsp_read_error & (bus_rsp_read_tag === (i.asUInt(pt1.LSU_BUS_TAG.W))) ) | -//// (bus_rsp_read_error & buf_ldfwd(i) & (bus_rsp_read_tag === buf_ldfwdtag(i))) | -//// (bus_rsp_write_error & pt.BUILD_AXI_NATIVE & (bus_rsp_write_tag === i.asUInt(pt1.LSU_BUS_TAG.W)))) -//// buf_data_in(i) := Mux((buf_state_en(i) & !buf_error_en(i)), Mux(buf_addr(i)(2), bus_rsp_rdata(63, 32), bus_rsp_rdata(31, 0)), bus_rsp_rdata(31, 0)) -//// } -//// is (done_partial_C){ // Other part of dual load hasn't returned -//// buf_nxtstate(i) := Mux(io.dec_tlu_force_halt.asBool(), idle_C, Mux((buf_ldfwd(i) | buf_ldfwd(buf_dualtag(i)) | any_done_wait_state), done_wait_C, done_C)) -//// buf_state_bus_en(i) := bus_rsp_read & ((bus_rsp_read_tag === buf_dualtag(i).asUInt()) | -//// (buf_ldfwd(buf_dualtag(i)) & (bus_rsp_read_tag === buf_ldfwdtag(buf_dualtag(i)).asUInt()))) -//// buf_state_en(i) := (buf_state_bus_en(i) & io.lsu_bus_clk_en) | io.dec_tlu_force_halt -//// } -//// is (done_wait_C) { // WAIT state if there are multiple outstanding nb returns -//// buf_nxtstate(i) := Mux(io.dec_tlu_force_halt.asBool(), idle_C, done_C) -//// buf_state_en(i) := ((RspPtr === i.asUInt(DEPTH_LOG2.W)) |(buf_dual(i) & (buf_dualtag(i) === RspPtr))) | io.dec_tlu_force_halt -//// } -//// is (done_C) { -//// buf_nxtstate(i) := idle_C -//// buf_rst(i) := 1.U -//// buf_state_en(i) := 1.U -//// buf_ldfwd_in(i) := 0.U -//// buf_ldfwd_en(i) := buf_state_en(i) -//// } -//// } -//// -//// buf_byteen(i) := RegEnable(buf_byteen_in(i) , init = 0.U ,buf_wr_en(i)) -//// buf_data(i) := RegEnable(buf_data_in(i) , init = 0.U ,buf_data_en(i)) -//// withClock(io.lsu_bus_buf_c1_clk){ -//// buf_state(i) := RegEnable(buf_nxtstate(i) , init = idle_C ,buf_state_en(i)) -//// buf_dualtag(i) := RegEnable(buf_dualtag_in(i) , init = 0.U ,buf_wr_en(i)) -//// buf_dual(i) := RegEnable(buf_dual_in(i) , init = 0.U ,buf_wr_en(i)) -//// buf_samedw(i) := RegEnable(buf_samedw_in(i) , init = 0.U ,buf_wr_en(i)) -//// buf_nomerge(i) := RegEnable(buf_nomerge_in(i) , init = 0.U ,buf_wr_en(i)) -//// buf_dualhi(i) := RegEnable(buf_dualhi_in(i) , init = 0.U ,buf_wr_en(i)) -//// buf_sideeffect(i) := RegEnable(buf_sideeffect_in(i) , init = 0.U ,buf_wr_en(i)) -//// buf_unsign(i) := RegEnable(buf_unsign_in(i) , init = 0.U ,buf_wr_en(i)) -//// buf_write(i) := RegEnable(buf_write_in(i) , init = 0.U ,buf_wr_en(i)) -//// buf_sz(i) := RegEnable(buf_sz_in(i) , init = 0.U ,buf_wr_en(i)) -//// buf_addr(i) := RegEnable(buf_addr_in(i) , init = 0.U ,buf_wr_en(i)) -//// buf_ldfwd(i) := RegEnable(buf_ldfwd_in(i) , init = 0.U ,buf_ldfwd_en(i)) -//// buf_ldfwdtag(i) := RegEnable(buf_ldfwdtag_in(i) , init = 0.U ,buf_ldfwd_en(i)) -//// buf_error(i) := RegEnable(~buf_rst(i) , init = 0.U ,(buf_error_en(i)|buf_rst(i)).asBool) -//// buf_ageQ(i) := RegNext(buf_age_in(i) , init = VecInit((0 until 4).map(i=>false.B))) -//// buf_rspageQ(i) := RegNext(buf_rspage_in(i) , init = VecInit((0 until 4).map(i=>false.B))) -//// } -//// } -//// -//// ////////////////////////////////////////////////////////////////////////////////// -//// buf_numvld_any := (io.lsu_busreq_m << io.ldst_dual_m) + (io.lsu_busreq_r << io.ldst_dual_r) + ibuf_valid + -//// {for(i <- 0 until DEPTH) yield ( buf_state(i) =/= idle_C).asUInt }.reduce(_+_) -//// buf_numvld_wrcmd_any := {for(i <- 0 until DEPTH) yield (( buf_state(i) === cmd_C) & ~buf_cmd_state_bus_en(i) & buf_write(i)).asUInt }.reduce(_+_) -//// buf_numvld_cmd_any := {for(i <- 0 until DEPTH) yield (( buf_state(i) === cmd_C) & ~buf_cmd_state_bus_en(i)).asUInt }.reduce(_+_) -//// buf_numvld_pend_any := {for(i <- 0 until DEPTH) yield (((buf_state(i) === cmd_C) & ~buf_cmd_state_bus_en(i)) | (buf_state(i) === wait_C)).asUInt }.reduce(_+_) -//// any_done_wait_state := {for(i <- 0 until DEPTH) yield buf_state(i) === done_wait_C }.reduce(_|_) -//// -//// io.lsu_bus_buffer_pend_any := buf_numvld_pend_any =/= 0.U -//// io.lsu_bus_buffer_full_any := Mux((io.ldst_dual_d & io.dec_lsu_valid_raw_d),buf_numvld_any(3,0) >= (DEPTH-1).asUInt(4.W), buf_numvld_any(3,0) === DEPTH.asUInt(4.W)) -//// io.lsu_bus_buffer_empty_any := ~((0 until DEPTH).map(i =>(buf_state(i)).asUInt).reduce(_|_)) & ~ibuf_valid & ~obuf_valid -//// -//// io.lsu_nonblock_load_valid_m := io.lsu_busreq_m & io.lsu_pkt_m.valid & io.lsu_pkt_m.load & ~io.flush_m_up & ~ io.ld_full_hit_m -//// io.lsu_nonblock_load_tag_m := WrPtr0_m(DEPTH_LOG2-1,0) -//// io.lsu_nonblock_load_inv_r := lsu_nonblock_load_valid_r & ~io.lsu_commit_r -//// io.lsu_nonblock_load_inv_tag_r := WrPtr0_r(DEPTH_LOG2-1,0) -//// -//// lsu_nonblock_load_data_ready := Mux1H((0 until DEPTH).map(i =>(buf_state(i) === done_C) -> ~(pt.BUILD_AXI_NATIVE & buf_write(i)))) -//// io.lsu_nonblock_load_data_error := Mux1H((0 until DEPTH).map(i =>(buf_state(i) === done_C & ~buf_write(i)) -> (buf_error(i)))) -//// io.lsu_nonblock_load_data_tag := Mux1H((0 until DEPTH).map(i =>(buf_state(i) === done_C & (~buf_dual(i) | ~buf_dualhi(i)) & ~buf_write(i)) -> intToUInt(i))) -//// lsu_nonblock_load_data_lo := Mux1H((0 until DEPTH).map(i =>(buf_state(i) === done_C & ~buf_write(i) & (~buf_dual(i) | ~buf_dualhi(i))) -> buf_data(i))) -//// lsu_nonblock_load_data_hi := Mux1H((0 until DEPTH).map(i =>(buf_state(i) === done_C & ~buf_write(i) & ( buf_dual(i) & buf_dualhi(i))) -> buf_data(i))) -//// -//// lsu_nonblock_addr_offset := buf_addr(io.lsu_nonblock_load_data_tag)(1,0) -//// lsu_nonblock_sz := buf_sz(io.lsu_nonblock_load_data_tag)(1,0) -//// lsu_nonblock_unsign := buf_unsign(io.lsu_nonblock_load_data_tag) -//// lsu_nonblock_dual := buf_dual(io.lsu_nonblock_load_data_tag) -//// lsu_nonblock_data_unalgn := (Cat(lsu_nonblock_load_data_hi(31,0), lsu_nonblock_load_data_lo(31,0)) >> 8*lsu_nonblock_addr_offset(1,0))(31,0) -//// io.lsu_nonblock_load_data_valid := lsu_nonblock_load_data_ready & ~io.lsu_nonblock_load_data_error -//// io.lsu_nonblock_load_data := Mux1H(Seq( -//// (lsu_nonblock_unsign & lsu_nonblock_sz === 0.U) -> Cat(Fill(24,0.U(1.W)),lsu_nonblock_data_unalgn(7,0)), -//// (lsu_nonblock_unsign & lsu_nonblock_sz === 1.U) -> Cat(Fill(16,0.U(1.W)),lsu_nonblock_data_unalgn(15,0)), -//// (~lsu_nonblock_unsign & lsu_nonblock_sz === 0.U) -> Cat(Fill(24,lsu_nonblock_data_unalgn(7)),lsu_nonblock_data_unalgn(7,0)), -//// (~lsu_nonblock_unsign & lsu_nonblock_sz === 1.U) -> Cat(Fill(16,lsu_nonblock_data_unalgn(15)),lsu_nonblock_data_unalgn(15,0)), -//// (lsu_nonblock_unsign & lsu_nonblock_sz === 2.U) -> lsu_nonblock_data_unalgn(31,0) -//// )) -//// bus_sideeffect_pend := Mux(obuf_valid,obuf_sideeffect & io.dec_tlu_sideeffect_posted_disable,Mux1H((0 until DEPTH).map(i =>(buf_state(i) === resp_C) -> (buf_sideeffect(i) & io.dec_tlu_sideeffect_posted_disable)))) -//// bus_addr_match_pending := Mux1H((0 until DEPTH).map(i =>(pt.BUILD_AXI_NATIVE & obuf_valid & (obuf_addr(31,3) === buf_addr(i)(31,3))).asBool -> ((buf_state(i) === resp_C) & ~((obuf_tag0 === intToUInt(i)) | (obuf_merge & (obuf_tag1 === intToUInt(i))))))) -//// -//// bus_cmd_ready := Mux(obuf_write, Mux((obuf_cmd_done | obuf_data_done), Mux(obuf_cmd_done, io.lsu_axi_wready, io.lsu_axi_awready), (io.lsu_axi_awready & io.lsu_axi_wready)), io.lsu_axi_arready) -//// bus_wcmd_sent := io.lsu_axi_awvalid & io.lsu_axi_awready -//// bus_wdata_sent := io.lsu_axi_wvalid & io.lsu_axi_wready -//// bus_cmd_sent := ((obuf_cmd_done | bus_wcmd_sent) & (obuf_data_done | bus_wdata_sent)) | (io.lsu_axi_arvalid & io.lsu_axi_arready) -//// -//// bus_rsp_read := io.lsu_axi_rvalid & io.lsu_axi_rready -//// bus_rsp_write := io.lsu_axi_bvalid & io.lsu_axi_bready -//// bus_rsp_read_tag := io.lsu_axi_rid(pt1.LSU_BUS_TAG-1,0) -//// bus_rsp_write_tag := io.lsu_axi_bid(pt1.LSU_BUS_TAG-1,0) -//// bus_rsp_write_error := bus_rsp_write & (io.lsu_axi_bresp(1,0) =/= 0.U(2.W)) -//// bus_rsp_read_error := bus_rsp_read & (io.lsu_axi_rresp(1,0) =/= 0.U(2.W)) -//// bus_rsp_rdata := io.lsu_axi_rdata(63,0) -//// ////////////////////////////////////////////////////////////////////////////////// -//// lsu_axi_rdata_q := RegEnable(io.lsu_axi_rdata, init = 0.U, io.lsu_axi_rvalid&io.lsu_bus_clk_en) -//// withClock(io.lsu_c2_r_clk){ -//// io.lsu_busreq_r := RegNext((io.lsu_busreq_m & !io.flush_r & !io.ld_full_hit_m), 0.U) -//// WrPtr0_r := RegNext(WrPtr0_m, init = 0.U) -//// WrPtr1_r := RegNext(WrPtr1_m, init = 0.U) -//// lsu_nonblock_load_valid_r := RegNext(io.lsu_nonblock_load_valid_m, init = 0.U) -//// } -//// withClock(io.lsu_busm_clk){ -//// lsu_axi_awvalid_q := RegNext(io.lsu_axi_awvalid, init = 0.U) -//// lsu_axi_awready_q := RegNext(io.lsu_axi_awready, init = 0.U) -//// lsu_axi_wvalid_q := RegNext(io.lsu_axi_wvalid, init = 0.U) -//// lsu_axi_wready_q := RegNext(io.lsu_axi_wready, init = 0.U) -//// lsu_axi_arvalid_q := RegNext(io.lsu_axi_arvalid, init = 0.U) -//// lsu_axi_arready_q := RegNext(io.lsu_axi_arready, init = 0.U) -//// lsu_axi_bvalid_q := RegNext(io.lsu_axi_bvalid, init = 0.U) -//// lsu_axi_bready_q := RegNext(io.lsu_axi_bready, init = 0.U) -//// lsu_axi_rvalid_q := RegNext(io.lsu_axi_rvalid, init = 0.U) -//// lsu_axi_rready_q := RegNext(io.lsu_axi_rready, init = 0.U) -//// lsu_axi_bid_q := RegNext(io.lsu_axi_bid, init = 0.U) -//// lsu_axi_rid_q := RegNext(io.lsu_axi_rid, init = 0.U) -//// lsu_axi_bresp_q := RegNext(io.lsu_axi_bresp, init = 0.U) -//// lsu_axi_rresp_q := RegNext(io.lsu_axi_rresp, init = 0.U) -//// } -//// /////////////////////////////////////////////////////////////////////////////////// -//// -//// io.ld_fwddata_buf_lo := 0.U -//// io.ld_fwddata_buf_hi := 0.U -//// -//// lsu_imprecise_error_store_tag := Mux1H((0 until DEPTH).map(i =>(((buf_state(i) === done_C) & buf_error(i) & buf_write(i)) -> intToUInt(i)))) -//// io.lsu_imprecise_error_load_any := io.lsu_nonblock_load_data_error & ~io.lsu_imprecise_error_store_any -//// io.lsu_imprecise_error_store_any := {for(i <- 0 until DEPTH) yield io.lsu_bus_clk_en_q & (buf_state(i) === done_C) & buf_error(i) & buf_write(i)}.reduce(_|_) -//// io.lsu_imprecise_error_addr_any := Mux(io.lsu_imprecise_error_store_any, buf_addr(lsu_imprecise_error_store_tag), buf_addr(io.lsu_nonblock_load_data_tag)) -//// -//// bus_pend_trxnQ := 0.U(8.W) -//// bus_pend_trxn := 0.U(8.W) -//// bus_pend_trxn_ns := 0.U(8.W) -//// lsu_bus_cntr_overflow := 0.U(1.W) -//// io.lsu_bus_idle_any := true.B -//// -//// io.lsu_pmu_bus_trxn := (io.lsu_axi_awvalid & io.lsu_axi_awready) | (io.lsu_axi_wvalid & io.lsu_axi_wready) | (io.lsu_axi_arvalid & io.lsu_axi_arready) -//// io.lsu_pmu_bus_misaligned := io.lsu_busreq_r & io.ldst_dual_r & io.lsu_commit_r -//// io.lsu_pmu_bus_error := io.lsu_imprecise_error_load_any | io.lsu_imprecise_error_store_any -//// io.lsu_pmu_bus_busy := (io.lsu_axi_awvalid & ~io.lsu_axi_awready | (io.lsu_axi_wvalid & ~io.lsu_axi_wready) | (io.lsu_axi_arvalid & ~io.lsu_axi_arready)) -//// -//// io.lsu_axi_awvalid := obuf_valid & obuf_write & ~obuf_cmd_done & ~bus_addr_match_pending -//// io.lsu_axi_awid := obuf_tag0.asUInt -//// io.lsu_axi_awaddr := Mux(obuf_sideeffect, obuf_addr,Cat(obuf_addr(31,3),0.U(3.W))) -//// io.lsu_axi_awregion := obuf_addr(31,28) -//// io.lsu_axi_awlen := 0.U(8.W) -//// io.lsu_axi_awsize := Mux(obuf_sideeffect, Cat(false.B,obuf_sz),3.U(3.W)) -//// io.lsu_axi_awburst := 1.U(2.W) -//// io.lsu_axi_awlock := 0.U -//// io.lsu_axi_awcache := Mux(obuf_sideeffect, 0.U(4.W),15.U(4.W)) -//// io.lsu_axi_awprot := 0.U(3.W) -//// io.lsu_axi_awqos := 0.U(4.W) -//// -//// io.lsu_axi_wvalid := obuf_valid & obuf_write & ~obuf_data_done & ~bus_addr_match_pending -//// io.lsu_axi_wdata := obuf_data -//// io.lsu_axi_wstrb := obuf_byteen & Fill(8,obuf_write) -//// io.lsu_axi_wlast := 1.U -//// -//// io.lsu_axi_arvalid := obuf_valid & ~obuf_write & ~obuf_nosend & ~bus_addr_match_pending -//// io.lsu_axi_arid := obuf_tag0.asUInt -//// io.lsu_axi_araddr := io.lsu_axi_awaddr -//// io.lsu_axi_arregion := obuf_addr(31,28) -//// io.lsu_axi_arlen := 0.U(8.W) -//// io.lsu_axi_arsize := io.lsu_axi_awsize -//// io.lsu_axi_arburst := 1.U(2.W) -//// io.lsu_axi_arlock := 0.U -//// io.lsu_axi_arcache := io.lsu_axi_awcache -//// io.lsu_axi_arprot := 0.U -//// io.lsu_axi_arqos := 0.U -//// -//// io.lsu_axi_bready := 1.U -//// io.lsu_axi_rready := 1.U -//// -//// -////} -////object BusBufmain extends App{ -//// println("Generate Verilog") -//// println((new chisel3.stage.ChiselStage).emitVerilog((new el2_lsu_bus_buffer()))) -////} + ibuf_merge_en := io.lsu_busreq_r & io.lsu_commit_r & io.lsu_pkt_r.store & ibuf_valid & ibuf_write & (io.lsu_addr_r(31,2) === ibuf_addr(31,2)) & !io.is_sideeffects_r & !bus_coalescing_disable + ibuf_merge_in := !io.ldst_dual_r + val ibuf_byteen_out = (0 until 4).map(i=>(Mux(ibuf_merge_en & !ibuf_merge_in, ibuf_byteen(i) | ldst_byteen_lo_r(i), ibuf_byteen(i))).asUInt).reverse.reduce(Cat(_,_)) + val ibuf_data_out = (0 until 4).map(i=>Mux(ibuf_merge_en & !ibuf_merge_in, Mux(ldst_byteen_lo_r(i), store_data_lo_r((8*i)+7, 8*i), ibuf_data((8*i)+7, 8*i)), ibuf_data((8*i)+7, 8*i))).reverse.reduce(Cat(_,_)) + + ibuf_valid := RegNext(Mux(ibuf_wr_en, true.B, ibuf_valid) & ibuf_rst, false.B) + ibuf_tag := withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(ibuf_tag_in, 0.U, ibuf_wr_en & io.lsu_bus_ibuf_c1_clk.asBool())} + val ibuf_dualtag = withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(ibuf_dualtag_in, 0.U, ibuf_wr_en & io.lsu_bus_ibuf_c1_clk.asBool())} + val ibuf_dual = withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(io.ldst_dual_r, 0.U, ibuf_wr_en & io.lsu_bus_ibuf_c1_clk.asBool())} + val ibuf_samedw = withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(ldst_samedw_r, 0.U, ibuf_wr_en & io.lsu_bus_ibuf_c1_clk.asBool())} + val ibuf_nomerge = withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(io.no_dword_merge_r, 0.U, ibuf_wr_en & io.lsu_bus_ibuf_c1_clk.asBool())} + ibuf_sideeffect := withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(io.is_sideeffects_r, 0.U, ibuf_wr_en & io.lsu_bus_ibuf_c1_clk.asBool())} + val ibuf_unsign = withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(io.lsu_pkt_r.unsign, 0.U, ibuf_wr_en & io.lsu_bus_ibuf_c1_clk.asBool())} + ibuf_write := withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(io.lsu_pkt_r.store, 0.U, ibuf_wr_en)} + val ibuf_sz = withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(ibuf_sz_in, 0.U, ibuf_wr_en)} + ibuf_addr := rvdffe(ibuf_addr_in, ibuf_wr_en, clock, io.scan_mode) + ibuf_byteen := withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(ibuf_byteen_in, 0.U, ibuf_wr_en)} + ibuf_data := rvdffe(ibuf_data_in, ibuf_wr_en, clock, io.scan_mode) + ibuf_timer := withClock(io.lsu_bus_ibuf_c1_clk) {RegNext(ibuf_timer_in, 0.U)} + val buf_numvld_wrcmd_any = WireInit(UInt(4.W), 0.U) + val buf_numvld_cmd_any = WireInit(UInt(4.W), 0.U) + val obuf_wr_timer = WireInit(UInt(TIMER_LOG2.W), 0.U) + val buf_nomerge = Wire(Vec(DEPTH, Bool())) + buf_nomerge := buf_nomerge.map(i=> false.B) + val Cmdptr0 = WireInit(UInt(LSU_NUM_NBLOAD_WIDTH.W), 0.U) + val buf_sideeffect = WireInit(UInt(LSU_NUM_NBLOAD.W), 0.U) + val obuf_force_wr_en = WireInit(Bool(), false.B) + val obuf_wr_en = WireInit(Bool(), false.B) + val obuf_wr_wait = (buf_numvld_wrcmd_any===1.U) & (buf_numvld_cmd_any===1.U) & (obuf_wr_timer =/= TIMER_MAX.U) & + !bus_coalescing_disable & !Mux1H((0 until math.pow(2,LSU_NUM_NBLOAD_WIDTH).asInstanceOf[Int]).map(i=>(Cmdptr0===i.U)->buf_nomerge(i))) & + !Mux1H((0 until math.pow(2,LSU_NUM_NBLOAD_WIDTH).asInstanceOf[Int]).map(i=>(Cmdptr0===i.U)->buf_sideeffect(i))) & !obuf_force_wr_en + val obuf_wr_timer_in = Mux(obuf_wr_en, 0.U(3.W), Mux(buf_numvld_cmd_any.orR & (obuf_wr_timer(Cmdptr0===i.U)->buf_addr(i)(31,2)))) + val buf_numvld_pend_any = WireInit(UInt(4.W), 0.U) + val ibuf_buf_byp = ibuf_byp & (buf_numvld_pend_any===0.U) & (!io.lsu_pkt_r.store | io.no_dword_merge_r) + val bus_sideeffect_pend = WireInit(Bool(), false.B) + val found_cmdptr0 = WireInit(Bool(), false.B) + val buf_cmd_state_bus_en = Wire(Vec(DEPTH, Bool())) + buf_cmd_state_bus_en := buf_cmd_state_bus_en.map(i=> false.B) + val buf_dual = Wire(Vec(DEPTH, Bool())) + buf_dual := buf_dual.map(i=> false.B) + val buf_samedw = Wire(Vec(DEPTH, Bool())) + buf_samedw := buf_samedw.map(i=> false.B) + val found_cmdptr1 = WireInit(Bool(), false.B) + val bus_cmd_ready = WireInit(Bool(), false.B) + val obuf_valid = WireInit(Bool(), false.B) + val obuf_nosend = WireInit(Bool(), false.B) + val lsu_bus_cntr_overflow = WireInit(Bool(), false.B) + val bus_addr_match_pending = WireInit(Bool(), false.B) + obuf_wr_en := ((ibuf_buf_byp & io.lsu_commit_r & !(io.is_sideeffects_r & bus_sideeffect_pend)) | + ((Mux1H((0 until math.pow(2,LSU_NUM_NBLOAD_WIDTH).asInstanceOf[Int]).map(i=>(Cmdptr0===1.U)->buf_state(i))) === cmd_C) & + found_cmdptr0 & !indexing(buf_cmd_state_bus_en.map(_.asUInt).reverse.reduce(Cat(_,_)), Cmdptr0) & !(indexing(buf_sideeffect, Cmdptr0) & bus_sideeffect_pend) & + (!(indexing(buf_dual.map(_.asUInt).reverse.reduce(Cat(_,_)), Cmdptr0) & indexing(buf_samedw.map(_.asUInt).reverse.reduce(Cat(_,_)), Cmdptr0) & !indexing(buf_write, Cmdptr0)) | found_cmdptr1 | indexing(buf_nomerge.map(_.asUInt).reverse.reduce(Cat(_,_)), Cmdptr0) | + obuf_force_wr_en))) & (bus_cmd_ready | !obuf_valid | obuf_nosend) & !obuf_wr_wait & !lsu_bus_cntr_overflow & !bus_addr_match_pending & io.lsu_bus_clk_en + val bus_cmd_sent = WireInit(Bool(), false.B) + val obuf_rst = ((bus_cmd_sent | (obuf_valid & obuf_nosend)) & !obuf_wr_en & io.lsu_bus_clk_en) | io.dec_tlu_force_halt + val obuf_write_in = Mux(ibuf_buf_byp, io.lsu_pkt_r.store, indexing(buf_write, Cmdptr0)) + val obuf_sideeffect_in = Mux(ibuf_buf_byp, io.is_sideeffects_r, indexing(buf_sideeffect, Cmdptr0)) + val obuf_addr_in = Mux(ibuf_buf_byp, io.lsu_addr_r, indexing(buf_addr, Cmdptr0)) + val buf_sz = Wire(Vec(DEPTH, UInt(2.W))) + buf_sz := buf_sz.map(i=> 0.U) + val obuf_sz_in = Mux(ibuf_buf_byp, Cat(io.lsu_pkt_r.word, io.lsu_pkt_r.half), indexing(buf_sz, Cmdptr0)) + val obuf_merge_en = WireInit(Bool(), false.B) + val obuf_merge_in = obuf_merge_en + val obuf_tag0_in = Mux(ibuf_buf_byp, WrPtr0_r, Cmdptr0) + val Cmdptr1 = WireInit(UInt(DEPTH_LOG2.W), 0.U) + val obuf_tag1_in = Mux(ibuf_buf_byp, WrPtr1_r, Cmdptr1) + val obuf_cmd_done = WireInit(Bool(), false.B) + val bus_wcmd_sent = WireInit(Bool(), false.B) + val obuf_cmd_done_in = !(obuf_wr_en | obuf_rst) & (obuf_cmd_done | bus_wcmd_sent) + val obuf_data_done = WireInit(Bool(), false.B) + val bus_wdata_sent = WireInit(Bool(), false.B) + val obuf_data_done_in = !(obuf_wr_en | obuf_rst) & (obuf_data_done | bus_wdata_sent) + val obuf_aligned_in = Mux(ibuf_buf_byp, is_aligned_r, obuf_sz_in(1,0)===0.U | (obuf_sz_in(0) & !obuf_addr_in(0)) | (obuf_sz_in(1)&(!obuf_addr_in(1,0).orR))) + + val obuf_nosend_in = WireInit(Bool(), false.B) + val obuf_rdrsp_pend = WireInit(Bool(), false.B) + val bus_rsp_read = WireInit(Bool(), false.B) + val bus_rsp_read_tag = WireInit(UInt(LSU_BUS_TAG.W), 0.U) + val obuf_rdrsp_tag = WireInit(UInt(LSU_BUS_TAG.W), 0.U) + val obuf_write = WireInit(Bool(), false.B) + val obuf_rdrsp_pend_in = (!(obuf_wr_en & !obuf_nosend_in) & obuf_rdrsp_pend & !(bus_rsp_read & (bus_rsp_read_tag === obuf_rdrsp_tag))) | + ((bus_cmd_sent & !obuf_write) & !io.dec_tlu_force_halt) + val obuf_tag0 = WireInit(UInt(LSU_BUS_TAG.W), 0.U) + val obuf_rdrsp_tag_in = Mux(bus_cmd_sent | !obuf_write, obuf_tag0, obuf_rdrsp_tag) + val obuf_addr = WireInit(UInt(32.W), 0.U) + val obuf_sideeffect = WireInit(Bool(), false.B) + obuf_nosend_in := (obuf_addr_in(31,3)===obuf_addr(31,3)) & obuf_aligned_in & !obuf_sideeffect & !obuf_write & !obuf_write_in & !io.dec_tlu_external_ldfwd_disable & + ((obuf_valid & !obuf_nosend) | (obuf_rdrsp_pend & !(bus_rsp_read & (bus_rsp_read_tag === obuf_rdrsp_tag)))) + val obuf_byteen0_in = Mux(ibuf_buf_byp, Mux(io.lsu_addr_r(2), Cat(ldst_byteen_lo_r, 0.U(4.W)), Cat(0.U(4.W), ldst_byteen_lo_r)), + Mux(indexing(buf_addr, Cmdptr0)(2).asBool(), Cat(indexing(buf_byteen, Cmdptr0), 0.U(4.W)), Cat(0.U(4.W),indexing(buf_byteen, Cmdptr0)))) + val obuf_byteen1_in = Mux(ibuf_buf_byp, Mux(io.end_addr_r(2), Cat(ldst_byteen_hi_r, 0.U(4.W)), Cat(0.U(4.W), ldst_byteen_hi_r)), + Mux(indexing(buf_addr, Cmdptr1)(2).asBool(), Cat(indexing(buf_byteen, Cmdptr1), 0.U(4.W)), Cat(0.U(4.W),indexing(buf_byteen, Cmdptr1)))) + + val obuf_data0_in = Mux(ibuf_buf_byp, Mux(io.lsu_addr_r(2), Cat(store_data_lo_r, 0.U(32.W)), Cat(0.U(32.W), store_data_lo_r)), + Mux(indexing(buf_addr, Cmdptr0)(2).asBool(), Cat(indexing(buf_data, Cmdptr0), 0.U(32.W)), Cat(0.U(32.W),indexing(buf_data, Cmdptr0)))) + val obuf_data1_in = Mux(ibuf_buf_byp, Mux(io.lsu_addr_r(2), Cat(store_data_hi_r, 0.U(32.W)), Cat(0.U(32.W), store_data_hi_r)), + Mux(indexing(buf_addr, Cmdptr1)(2).asBool(), Cat(indexing(buf_data, Cmdptr1), 0.U(32.W)), Cat(0.U(32.W),indexing(buf_data, Cmdptr1)))) + val obuf_byteen_in = (0 until 8).map(i=>(obuf_byteen0_in(i) | (obuf_merge_en & obuf_byteen1_in(i))).asUInt).reverse.reduce(Cat(_,_)) + val obuf_data_in = (0 until 8).map(i=>Mux(obuf_merge_en & obuf_byteen1_in(i), obuf_data1_in((8*i)+7, 8*i), obuf_data1_in((8*i)+7, 8*i))).reverse.reduce(Cat(_,_)) + val buf_dualhi = Wire(Vec(DEPTH, Bool())) + buf_dualhi := buf_dualhi.map(i=> false.B) + obuf_merge_en := ((Cmdptr0 =/= Cmdptr1) & found_cmdptr0 & found_cmdptr1 & (indexing(buf_state, Cmdptr0) === cmd_C) & (indexing(buf_state, Cmdptr1) === cmd_C) & + !indexing(buf_cmd_state_bus_en.map(_.asUInt).reverse.reduce(Cat(_,_)), Cmdptr0) & !indexing(buf_sideeffect, Cmdptr0) & + ((indexing(buf_write, Cmdptr0) & indexing(buf_write, Cmdptr1) & + (indexing(buf_addr, Cmdptr0)(31,3)===indexing(buf_addr, Cmdptr1)(31,3)) & !bus_coalescing_disable & !BUILD_AXI_NATIVE.B) | + (!indexing(buf_write, Cmdptr0) & indexing(buf_dual.map(_.asUInt).reverse.reduce(Cat(_,_)), Cmdptr0) & !indexing(buf_dualhi.map(_.asUInt).reverse.reduce(Cat(_,_)), Cmdptr0) & indexing(buf_samedw.map(_.asUInt).reverse.reduce(Cat(_,_)), Cmdptr0)))) | + (ibuf_buf_byp & ldst_samedw_r & io.ldst_dual_r) + + val obuf_wr_enQ = withClock(io.lsu_busm_clk){RegNext(obuf_wr_en, false.B)} + obuf_valid := withClock(io.lsu_busm_clk){RegNext(Mux(obuf_wr_en, true.B, obuf_valid) & obuf_rst, false.B)} + obuf_nosend := withClock(io.lsu_busm_clk){RegEnable(obuf_nosend_in, false.B, obuf_wr_en)} + obuf_cmd_done := withClock(io.lsu_busm_clk){RegNext(obuf_cmd_done_in, false.B)} + obuf_data_done := withClock(io.lsu_busm_clk){RegNext(obuf_data_done_in, false.B)} + obuf_rdrsp_pend := withClock(io.lsu_busm_clk){RegNext(obuf_rdrsp_pend_in, false.B)} + obuf_rdrsp_tag := withClock(io.lsu_busm_clk){RegNext(obuf_rdrsp_tag_in, 0.U)} + obuf_tag0 := withClock(io.lsu_busm_clk){RegEnable(obuf_tag0_in, 0.U, obuf_wr_en)} + val obuf_tag1 = withClock(io.lsu_busm_clk){RegEnable(obuf_tag1_in, 0.U, obuf_wr_en)} + val obuf_merge = withClock(io.lsu_busm_clk){RegEnable(obuf_merge_in, false.B, obuf_wr_en)} + obuf_write := withClock(io.lsu_busm_clk){RegEnable(obuf_write_in, false.B, obuf_wr_en)} + obuf_sideeffect := withClock(io.lsu_busm_clk){RegEnable(obuf_sideeffect_in, false.B, obuf_wr_en)} + val obuf_sz = withClock(io.lsu_busm_clk){RegEnable(obuf_sz_in, 0.U, obuf_wr_en)} + obuf_addr := rvdffe(obuf_addr_in, obuf_wr_en, io.lsu_busm_clk, io.scan_mode) + val obuf_byteen = withClock(io.lsu_busm_clk){RegEnable(obuf_byteen_in, 0.U, obuf_wr_en)} + val obuf_data = rvdffe(obuf_data_in, obuf_wr_en, io.lsu_busm_clk, io.scan_mode) + obuf_wr_timer := withClock(io.lsu_busm_clk){RegNext(obuf_wr_timer_in, 0.U)} + val WrPtr0_m = WireInit(UInt(DEPTH_LOG2.W), 0.U) + val found_array1 = (0 until DEPTH).map(i=>((buf_state(i)===idle_C) & !((ibuf_valid & (ibuf_tag===i.U)) | + (io.lsu_busreq_m & (WrPtr0_r===i.U)) | (io.ldst_dual_r & (WrPtr1_r === i.U))))->i.U) + WrPtr0_m := MuxCase(0.U, found_array1) + val found_array2 = (0 until DEPTH).map(i=>((buf_state(i)===idle_C) & !((ibuf_valid & (ibuf_tag===i.U)) | + (io.lsu_busreq_m & (WrPtr0_m===i.U)) | (io.lsu_busreq_r & (WrPtr0_r === i.U)) | (io.ldst_dual_r & (WrPtr1_r===i.U))))->i.U) + val WrPtr1_m = MuxCase(0.U, found_array2) + val buf_age = Wire(Vec(DEPTH, UInt(DEPTH.W))) + buf_age := buf_age.map(i=> 0.U) + val CmdPtr0Dec = (0 until DEPTH).map(i=> (!(buf_age(i).orR) & (buf_state(i)===cmd_C) & !buf_cmd_state_bus_en(i)).asUInt).reverse.reduce(Cat(_,_)) + val CmdPtr1Dec = (0 until DEPTH).map(i=> (!((buf_age(i) & (~CmdPtr0Dec)).orR) & !CmdPtr0Dec(i) & (buf_state(i)===cmd_C) & !buf_cmd_state_bus_en(i)).asUInt).reverse.reduce(Cat(_,_)) + val buf_rsp_pickage = Wire(Vec(DEPTH, UInt(DEPTH.W))) + buf_rsp_pickage := buf_rsp_pickage.map(i=> 0.U) + val RspPtrDec = (0 until DEPTH).map(i=> (!(buf_rsp_pickage(i).orR) & (buf_state(i)===done_wait_C)).asUInt).reverse.reduce(Cat(_,_)) + found_cmdptr0 := CmdPtr0Dec.orR + found_cmdptr1 := CmdPtr1Dec.orR + + val CmdPtr0 = PriorityEncoder(CmdPtr0Dec) + val CmdPtr1 = PriorityEncoder(CmdPtr1Dec) + val RspPtr = PriorityEncoder(RspPtrDec) + val buf_state_en = Wire(Vec(DEPTH, Bool())) + buf_state_en := buf_state_en.map(i=> false.B) + val buf_rspageQ = Wire(Vec(DEPTH, UInt(DEPTH.W))) + buf_rspageQ := buf_rspageQ.map(i=> 0.U) + val buf_rspage_set = Wire(Vec(DEPTH, UInt(DEPTH.W))) + buf_rspage_set := buf_rspage_set.map(i=> 0.U) + val buf_rspage_in = Wire(Vec(DEPTH, UInt(DEPTH.W))) + buf_rspage_in := buf_rspage_in.map(i=> 0.U) + val buf_rspage = Wire(Vec(DEPTH, UInt(DEPTH.W))) + buf_rspage := buf_rspage.map(i=> 0.U) + + val buf_age_in = (0 until DEPTH).map(i=>(0 until DEPTH).map(j=> ((((buf_state(i)===idle_C) & buf_state_en(i)) & + (((buf_state(j)===wait_C) | ((buf_state(j)===cmd_C) & !buf_cmd_state_bus_en(j))) | + (ibuf_drain_vld & io.lsu_busreq_r & (ibuf_byp | io.ldst_dual_r) & (WrPtr0_r === i.U) & (ibuf_tag === j.U)) | + (ibuf_byp & io.lsu_busreq_r & io.ldst_dual_r & (WrPtr1_r === i.U) & (WrPtr0_r === j.U)))) | buf_age(i)(j)).asUInt).reverse.reduce(Cat(_,_))) + val buf_ageQ = Wire(Vec(DEPTH, UInt(DEPTH.W))) + buf_ageQ := buf_ageQ.map(i=> 0.U) + buf_age := (0 until DEPTH).map(i=>(0 until DEPTH).map(j=>(buf_ageQ(i)(j) & ((buf_state(j)===cmd_C) & buf_cmd_state_bus_en(j))).asUInt).reverse.reduce(Cat(_,_))) + buf_age_younger := (0 until DEPTH).map(i=>(0 until DEPTH).map(j=>(Mux(i.U===j.U, 0.U, !buf_age(i)(j) & (buf_state(j)=/=idle_C))).asUInt).reverse.reduce(Cat(_,_))) + buf_rsp_pickage := (0 until DEPTH).map(i=>(0 until DEPTH).map(j=>(buf_rspageQ(i)(j) & (buf_state(j)===done_wait_C)).asUInt).reverse.reduce(Cat(_,_))) + + buf_rspage_set := (0 until DEPTH).map(i=>(0 until DEPTH).map(j=>(((buf_state(i)===idle_C) & buf_state_en(i)) & + (!((buf_state(j)===idle_C) | (buf_state(j)===done_C)) | + (ibuf_drain_vld & io.lsu_busreq_r & (ibuf_byp | io.ldst_dual_r) & (WrPtr0_r===i.U) & (ibuf_tag===j.U)) | + (ibuf_byp & io.lsu_busreq_r & io.ldst_dual_r & (WrPtr1_r===i.U) & (WrPtr0_r===j.U)))).asUInt).reverse.reduce(Cat(_,_))) + buf_rspage_in := (0 until DEPTH).map(i=>(0 until DEPTH).map(j=>(buf_rspage_set(i)(j) | buf_rspage(i)(j)).asUInt).reverse.reduce(Cat(_,_))) + buf_rspage := (0 until DEPTH).map(i=>(0 until DEPTH).map(j=>(buf_rspageQ(i)(j) & !((buf_state(j)===done_C) | (buf_state(j)===idle_C))).asUInt).reverse.reduce(Cat(_,_))) + + + + + ibuf_drainvec_vld := (0 until DEPTH).map(i=>(ibuf_drain_vld & (ibuf_tag === i.U)).asUInt).reverse.reduce(Cat(_,_)) + buf_byteen_in := (0 until DEPTH).map(i=>Mux(ibuf_drainvec_vld(i), ibuf_byteen_out(3,0), Mux(ibuf_byp & io.ldst_dual_r & (WrPtr1_r===i.U), ldst_byteen_hi_r(3,0), ldst_byteen_lo_r(3,0)))) + buf_addr_in := (0 until DEPTH).map(i=>Mux(ibuf_drainvec_vld(i), ibuf_addr, Mux(ibuf_byp & io.ldst_dual_r & (WrPtr1_r===i.U), io.end_addr_r, io.lsu_addr_r))) + buf_dual_in := (0 until DEPTH).map(i=>(Mux(ibuf_drainvec_vld(i), ibuf_dual, io.ldst_dual_r)).asUInt).reverse.reduce(Cat(_,_)) + buf_samedw_in := (0 until DEPTH).map(i=>(Mux(ibuf_drainvec_vld(i), ibuf_samedw, ldst_samedw_r)).asUInt).reverse.reduce(Cat(_,_)) + buf_nomerge_in := (0 until DEPTH).map(i=>(Mux(ibuf_drainvec_vld(i), ibuf_nomerge | ibuf_force_drain, io.no_dword_merge_r)).asUInt).reverse.reduce(Cat(_,_)) + buf_dualhi_in := (0 until DEPTH).map(i=>(Mux(ibuf_drainvec_vld(i), ibuf_dual ,ibuf_byp & io.ldst_dual_r & (WrPtr1_r===i.U))).asUInt).reverse.reduce(Cat(_,_)) + buf_dualtag_in := (0 until DEPTH).map(i=>Mux(ibuf_drainvec_vld(i), ibuf_dualtag, Mux(ibuf_byp & io.ldst_dual_r & (WrPtr1_r===i.U), WrPtr0_r, WrPtr1_r))) + buf_sideeffect_in := (0 until DEPTH).map(i=>(Mux(ibuf_drainvec_vld(i), ibuf_sideeffect, io.is_sideeffects_r)).asUInt).reverse.reduce(Cat(_,_)) + buf_unsign_in := (0 until DEPTH).map(i=>(Mux(ibuf_drainvec_vld(i), ibuf_unsign, io.lsu_pkt_r.unsign)).asUInt).reverse.reduce(Cat(_,_)) + buf_sz_in := (0 until DEPTH).map(i=>Mux(ibuf_drainvec_vld(i), ibuf_sz, Cat(io.lsu_pkt_r.word, io.lsu_pkt_r.half))) + buf_write_in := (0 until DEPTH).map(i=>(Mux(ibuf_drainvec_vld(i), ibuf_write, io.lsu_pkt_r.store)).asUInt).reverse.reduce(Cat(_,_)) + + for(i<- 0 until DEPTH) { + switch(buf_state(i)) { + is(idle_C) { + buf_nxtstate(i) := Mux(io.lsu_bus_clk_en.asBool(), cmd_C, wait_C) + buf_state_en(i) := (io.lsu_busreq_r & io.lsu_commit_r & (((ibuf_byp | io.ldst_dual_r) & !ibuf_merge_en & (i === WrPtr0_r)) | (ibuf_byp & io.ldst_dual_r & (i === WrPtr1_r)))) | (ibuf_drain_vld & (i === ibuf_tag)) + buf_wr_en(i) := buf_state_en(i) + buf_data_en(i) := buf_state_en(i) + buf_data_in(i) := Mux((ibuf_drain_vld & (i === ibuf_tag)).asBool(), ibuf_data_out(31, 0), store_data_lo_r(31, 0)) + } + is(wait_C) { + buf_nxtstate(i) := Mux(io.dec_tlu_force_halt.asBool(), idle_C, cmd_C) + buf_state_en(i) := io.lsu_bus_clk_en | io.dec_tlu_force_halt + } + is(cmd_C) { + buf_nxtstate(i) := Mux(io.dec_tlu_force_halt.asBool(), idle_C, Mux((obuf_nosend & bus_rsp_read & (bus_rsp_read_tag === obuf_rdrsp_tag)), done_wait_C, resp_C)) + buf_cmd_state_bus_en(i) := ((obuf_tag0 === i.asUInt(LSU_BUS_TAG.W)) | (obuf_merge & (obuf_tag1 === i.asUInt(LSU_BUS_TAG.W)))) & obuf_valid & obuf_wr_enQ + buf_state_bus_en(i) := buf_cmd_state_bus_en(i) + buf_state_en(i) := (buf_state_bus_en(i) & io.lsu_bus_clk_en) | io.dec_tlu_force_halt + buf_ldfwd_in(i) := true.B + buf_ldfwd_en(i) := buf_state_en(i) & !buf_write(i) & obuf_nosend & !io.dec_tlu_force_halt + buf_ldfwdtag_in(i) := (obuf_rdrsp_tag(LSU_BUS_TAG - 2, 0)).asUInt + buf_data_en(i) := buf_state_bus_en(i) & io.lsu_bus_clk_en & obuf_nosend & bus_rsp_read + buf_error_en(i) := buf_state_bus_en(i) & io.lsu_bus_clk_en & obuf_nosend & bus_rsp_read_error + buf_data_in(i) := Mux(buf_error_en(i), bus_rsp_rdata(31, 0), Mux(buf_addr(i)(2), bus_rsp_rdata(63, 32), bus_rsp_rdata(31, 0))) + } + is(resp_C) { + buf_nxtstate(i) := Mux((io.dec_tlu_force_halt | (buf_write(i) & !(BUILD_AXI_NATIVE.B & bus_rsp_write_error))).asBool(), idle_C, + Mux((buf_dual(i) & !buf_samedw(i) & !buf_write(i) & (buf_state(buf_dualtag(i)) =/= done_partial_C)), done_partial_C, + Mux((buf_ldfwd(i) | any_done_wait_state | (buf_dual(i) & !buf_samedw(i) & !buf_write(i) & indexing(buf_ldfwd,buf_dualtag(i)) & (buf_state(buf_dualtag(i)) === done_partial_C) & any_done_wait_state)), done_wait_C, done_C))) + buf_resp_state_bus_en(i) := (bus_rsp_write & (bus_rsp_write_tag === (i.asUInt(LSU_BUS_TAG.W)))) | + (bus_rsp_read & ((bus_rsp_read_tag === (i.asUInt(LSU_BUS_TAG.W))) | + (buf_ldfwd(i) & (bus_rsp_read_tag === (buf_ldfwdtag(i)))) | + (buf_dual(i) & buf_dualhi(i) & ~buf_write(i) & buf_samedw(i) & (bus_rsp_read_tag === (buf_dualtag(i)))))) + buf_state_bus_en(i) := buf_resp_state_bus_en(i) + buf_state_en(i) := (buf_state_bus_en(i) & io.lsu_bus_clk_en) | io.dec_tlu_force_halt + buf_data_en(i) := buf_state_bus_en(i) & bus_rsp_read & io.lsu_bus_clk_en + buf_error_en(i) := buf_state_bus_en(i) & io.lsu_bus_clk_en & ((bus_rsp_read_error & (bus_rsp_read_tag === (i.asUInt(LSU_BUS_TAG.W)))) | + (bus_rsp_read_error & buf_ldfwd(i) & (bus_rsp_read_tag === buf_ldfwdtag(i))) | + (bus_rsp_write_error & BUILD_AXI_NATIVE.B & (bus_rsp_write_tag === i.asUInt(LSU_BUS_TAG.W)))) + buf_data_in(i) := Mux((buf_state_en(i) & !buf_error_en(i)), Mux(buf_addr(i)(2), bus_rsp_rdata(63, 32), bus_rsp_rdata(31, 0)), bus_rsp_rdata(31, 0)) + } + is(done_partial_C) { // Other part of dual load hasn't returned + buf_nxtstate(i) := Mux(io.dec_tlu_force_halt.asBool(), idle_C, Mux((buf_ldfwd(i) | buf_ldfwd(buf_dualtag(i)) | any_done_wait_state), done_wait_C, done_C)) + buf_state_bus_en(i) := bus_rsp_read & ((bus_rsp_read_tag === buf_dualtag(i).asUInt()) | + (buf_ldfwd(buf_dualtag(i)) & (bus_rsp_read_tag === buf_ldfwdtag(buf_dualtag(i)).asUInt()))) + buf_state_en(i) := (buf_state_bus_en(i) & io.lsu_bus_clk_en) | io.dec_tlu_force_halt + } + is(done_wait_C) { // WAIT state if there are multiple outstanding nb returns + buf_nxtstate(i) := Mux(io.dec_tlu_force_halt.asBool(), idle_C, done_C) + buf_state_en(i) := ((RspPtr === i.asUInt(DEPTH_LOG2.W)) | (buf_dual(i) & (buf_dualtag(i) === RspPtr))) | io.dec_tlu_force_halt + } + is(done_C) { + buf_nxtstate(i) := idle_C + buf_rst(i) := 1.U + buf_state_en(i) := 1.U + buf_ldfwd_in(i) := false.B + buf_ldfwd_en(i) := buf_state_en(i) + } + } + buf_state(i) := withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_nxtstate(i), 0.U, buf_state_en(i).asBool())} + buf_ageQ(i) := withClock(io.lsu_bus_buf_c1_clk){RegNext(buf_age_in(i), 0.U)} + buf_rspageQ(i) := withClock(io.lsu_bus_buf_c1_clk){RegNext(buf_rspage_in(i), 0.U)} + buf_dualtag(i) := withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_dualtag_in(i), 0.U, buf_wr_en(i).asBool())} + buf_dual(i) := withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_dual_in(i), false.B, buf_wr_en(i).asBool())} + buf_samedw(i) := withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_samedw_in(i), false.B, buf_wr_en(i).asBool())} + buf_nomerge(i) := withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_nomerge_in(i), false.B, buf_wr_en(i).asBool())} + buf_dualhi(i) := withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_dualhi_in(i), false.B, buf_wr_en(i).asBool())} + } + + buf_ldfwd := (0 until DEPTH).map(i=>(withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_ldfwd_in(i), false.B, buf_ldfwd_en(i).asBool())}).asUInt()).reverse.reduce(Cat(_,_)) + buf_ldfwdtag := (0 until DEPTH).map(i=>withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_ldfwdtag_in(i), 0.U, buf_ldfwd_en(i).asBool())}) + buf_sideeffect := (0 until DEPTH).map(i=>(withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_sideeffect_in(i), false.B, buf_wr_en(i).asBool())}).asUInt()).reverse.reduce(Cat(_,_)) + buf_unsign := (0 until DEPTH).map(i=>(withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_unsign_in(i), false.B, buf_wr_en(i).asBool())}).asUInt()).reverse.reduce(Cat(_,_)) + buf_write := (0 until DEPTH).map(i=>(withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_write_in(i), false.B, buf_wr_en(i).asBool())}).asUInt()).reverse.reduce(Cat(_,_)) + buf_sz := (0 until DEPTH).map(i=>withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_sz_in(i), 0.U, buf_wr_en(i).asBool())}) + buf_addr := (0 until DEPTH).map(i=>rvdffe(buf_addr_in(i), buf_wr_en(i).asBool(), clock, io.scan_mode)) + buf_byteen := (0 until DEPTH).map(i=>withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_byteen_in(i), 0.U, buf_wr_en(i).asBool())}) + buf_data := (0 until DEPTH).map(i=>rvdffe(buf_data_in(i), buf_data_en(i), clock, io.scan_mode)) + buf_error := (0 until DEPTH).map(i=>(withClock(io.lsu_bus_buf_c1_clk){RegNext(Mux(buf_error_en(i), true.B, buf_error(i)) & buf_rst(i), false.B)}).asUInt()).reverse.reduce(Cat(_,_)) + + val buf_numvld_any = (0 until DEPTH).map(i=>(buf_state(i)=/=idle_C).asUInt).reverse.reduce(_ +& _) + buf_numvld_wrcmd_any := (0 until DEPTH).map(i=>(buf_write(i) & (buf_write(i)===cmd_C) & !buf_cmd_state_bus_en(i)).asUInt).reverse.reduce(_ +& _) + buf_numvld_cmd_any := (0 until DEPTH).map(i=>((buf_write(i)===cmd_C) & !buf_cmd_state_bus_en(i)).asUInt).reverse.reduce(_ +& _) + buf_numvld_pend_any := (0 until DEPTH).map(i=>(((buf_write(i)===wait_C)|(buf_write(i)===cmd_C)) & !buf_cmd_state_bus_en(i)).asUInt).reverse.reduce(_ +& _) + any_done_wait_state := (0 until DEPTH).map(i=>buf_state(i)===done_wait_C).reverse.reduce(_|_) + io.lsu_bus_buffer_pend_any := buf_numvld_pend_any.orR + io.lsu_bus_buffer_full_any := Mux(io.ldst_dual_d & io.dec_lsu_valid_raw_d, buf_numvld_any>=(DEPTH-1), buf_numvld_any===(DEPTH-1)) + io.lsu_bus_buffer_empty_any := !(buf_state.map(_.orR).reduce(_|_)) & !ibuf_valid & !obuf_valid + + io.lsu_nonblock_load_valid_m := io.lsu_busreq_m & io.lsu_pkt_m.valid & io.lsu_pkt_m.load & !io.flush_m_up & !io.ld_full_hit_m + io.lsu_nonblock_load_tag_m := WrPtr0_m + val lsu_nonblock_load_valid_r = WireInit(Bool(), false.B) + io.lsu_nonblock_load_inv_r := lsu_nonblock_load_valid_r & !io.lsu_commit_r + io.lsu_nonblock_load_inv_tag_r := WrPtr0_r + val lsu_nonblock_load_data_ready = Mux1H((0 until DEPTH).map(i=>(buf_state(i)===done_C) -> (!(BUILD_AXI_NATIVE.B & buf_write(i))))) + io.lsu_nonblock_load_data_error := Mux1H((0 until DEPTH).map(i=>(buf_state(i)===done_C) -> (buf_error(i) & !buf_write(i)))) + io.lsu_nonblock_load_data_tag := Mux1H((0 until DEPTH).map(i=>((buf_state(i)===done_C) & !buf_write(i) & (!buf_dual(i) | !buf_dualhi(i))) -> i.U)) + val lsu_nonblock_load_data_lo = Mux1H((0 until DEPTH).map(i=>((buf_state(i)===done_C) & !buf_write(i) & (!buf_dual(i) | !buf_dualhi(i))) -> buf_data(i))) + val lsu_nonblock_load_data_hi = Mux1H((0 until DEPTH).map(i=>((buf_state(i)===done_C) & !buf_write(i) & (buf_dual(i) | buf_dualhi(i))) -> buf_data(i))) + val lsu_nonblock_addr_offset = indexing(buf_addr, io.lsu_nonblock_load_data_tag) + val lsu_nonblock_sz = indexing(buf_sz, io.lsu_nonblock_load_data_tag) + val lsu_nonblock_unsign = indexing(buf_unsign, io.lsu_nonblock_load_data_tag) + val lsu_nonblock_dual = indexing(buf_dual.map(_.asUInt).reverse.reduce(Cat(_,_)), io.lsu_nonblock_load_data_tag) + val lsu_nonblock_data_unalgn = Cat(lsu_nonblock_load_data_hi, lsu_nonblock_load_data_lo) >> (lsu_nonblock_addr_offset * 8.U) + io.lsu_nonblock_load_data_valid := lsu_nonblock_load_data_ready & !io.lsu_nonblock_load_data_error + io.lsu_nonblock_load_data := Mux1H(Seq((lsu_nonblock_unsign & (lsu_nonblock_sz===0.U)) -> Cat(0.U(24.W),lsu_nonblock_data_unalgn(7,0)), + (lsu_nonblock_unsign & (lsu_nonblock_sz===1.U)) -> Cat(0.U(16.W),lsu_nonblock_data_unalgn(15,0)), + (!lsu_nonblock_unsign & (lsu_nonblock_sz===0.U)) -> Cat(Fill(24,lsu_nonblock_data_unalgn(7)), lsu_nonblock_data_unalgn(7,0)), + (!lsu_nonblock_unsign & (lsu_nonblock_sz===1.U)) -> Cat(Fill(16,lsu_nonblock_data_unalgn(15)), lsu_nonblock_data_unalgn(15,0)), + (lsu_nonblock_sz===2.U) -> lsu_nonblock_data_unalgn)) + bus_sideeffect_pend := Mux1H((0 until DEPTH).map(i=>(buf_state(i)===resp_C)->(buf_sideeffect(i) & io.dec_tlu_sideeffect_posted_disable))) + bus_addr_match_pending := Mux1H((0 until DEPTH).map(i=>(buf_state(i)===resp_C)-> + (BUILD_AXI_NATIVE.B & obuf_valid & (obuf_addr(31,3)===buf_addr(i)(31,3)) & !((obuf_tag0===i.U) | (obuf_merge & (obuf_tag1===i.U)))))) + + bus_cmd_ready := Mux(obuf_write, Mux(obuf_cmd_done | obuf_data_done, Mux(obuf_cmd_done, io.lsu_axi_wready, io.lsu_axi_awready), io.lsu_axi_awready & io.lsu_axi_awready), io.lsu_axi_arready) + bus_wcmd_sent := io.lsu_axi_awvalid & io.lsu_axi_awready + bus_wdata_sent := io.lsu_axi_wvalid & io.lsu_axi_wready + bus_cmd_sent := ((obuf_cmd_done | bus_wcmd_sent) & (obuf_data_done | bus_wdata_sent)) | (io.lsu_axi_arvalid & io.lsu_axi_arready) + bus_rsp_read := io.lsu_axi_rvalid & io.lsu_axi_rready + bus_rsp_write := io.lsu_axi_bvalid & io.lsu_axi_bready + bus_rsp_read_tag := io.lsu_axi_rid + bus_rsp_write_tag := io.lsu_axi_bid + bus_rsp_write_error := bus_rsp_write & (io.lsu_axi_bresp =/= 0.U) + bus_rsp_read_error := bus_rsp_read & (io.lsu_axi_bresp =/= 0.U) + bus_rsp_rdata := io.lsu_axi_rdata + + // AXI Command signals + io.lsu_axi_awvalid := obuf_valid & obuf_write & !obuf_cmd_done & !bus_addr_match_pending + io.lsu_axi_awid := obuf_tag0 + io.lsu_axi_awaddr := Mux(obuf_sideeffect, obuf_addr, Cat(obuf_addr(31,3), 0.U(3.W))) + io.lsu_axi_awsize := Mux(obuf_sideeffect, Cat(0.U, obuf_sz), 2.U(3.W)) + io.lsu_axi_awprot := 0.U + io.lsu_axi_awcache := Mux(obuf_sideeffect, 0.U, 15.U) + io.lsu_axi_awregion := obuf_addr(31,28) + io.lsu_axi_awlen := 0.U + io.lsu_axi_awburst := 1.U(2.W) + io.lsu_axi_awqos := 0.U + io.lsu_axi_awlock := 0.U + + io.lsu_axi_wvalid := obuf_valid & obuf_write & !obuf_data_done & !bus_addr_match_pending + io.lsu_axi_wstrb := obuf_byteen & Fill(8, obuf_write) + io.lsu_axi_wdata := obuf_data + io.lsu_axi_wlast := 1.U + + io.lsu_axi_arvalid := obuf_valid & !obuf_write & !obuf_nosend & !bus_addr_match_pending + io.lsu_axi_arid := obuf_tag0 + io.lsu_axi_araddr := Mux(obuf_sideeffect, obuf_addr, Cat(obuf_addr(31,3),0.U(3.W))) + io.lsu_axi_arsize := Mux(obuf_sideeffect, Cat(0.U, obuf_sz), 3.U(3.W)) + io.lsu_axi_arprot := 0.U + io.lsu_axi_arcache := Mux(obuf_sideeffect, 0.U(4.W), 15.U) + io.lsu_axi_arregion := obuf_addr(31,28) + io.lsu_axi_arlen := 0.U + io.lsu_axi_arburst := 1.U(2.W) + io.lsu_axi_arqos := 0.U + io.lsu_axi_arlock := 0.U + io.lsu_axi_bready := 1.U + io.lsu_axi_rready := 1.U + io.lsu_imprecise_error_store_any := Mux1H((0 until DEPTH).map(i=>(buf_state(i)===done_C)->(io.lsu_bus_clk_en_q & buf_error(i) & buf_write(i)))) + val lsu_imprecise_error_store_tag = Mux1H((0 until DEPTH_LOG2).map(i=>((buf_state(i)===done_C) & buf_error(i) & buf_write(i))->i.U)) + + io.lsu_imprecise_error_load_any := io.lsu_nonblock_load_data_error & !io.lsu_imprecise_error_store_any + io.lsu_imprecise_error_addr_any := Mux(io.lsu_imprecise_error_store_any, indexing(buf_addr, lsu_imprecise_error_store_tag), indexing(buf_addr, io.lsu_nonblock_load_data_tag)) + lsu_bus_cntr_overflow := 0.U + + io.lsu_bus_idle_any := 1.U + + // PMU signals + io.lsu_pmu_bus_trxn := (io.lsu_axi_awvalid & io.lsu_axi_awready) | (io.lsu_axi_wvalid & io.lsu_axi_wready) | (io.lsu_axi_arvalid & io.lsu_axi_arready) + io.lsu_pmu_bus_misaligned := io.lsu_busreq_r & io.ldst_dual_r & io.lsu_commit_r + io.lsu_pmu_bus_error := io.lsu_imprecise_error_load_any | io.lsu_imprecise_error_store_any + + io.lsu_pmu_bus_busy := (io.lsu_axi_awvalid & !io.lsu_axi_awready) | (io.lsu_axi_wvalid & !io.lsu_axi_wready) | (io.lsu_axi_arvalid & !io.lsu_axi_arready) + + WrPtr0_r := withClock(io.lsu_c2_r_clk){RegNext(WrPtr0_m, 0.U)} + WrPtr1_r := withClock(io.lsu_c2_r_clk){RegNext(WrPtr1_m, 0.U)} + io.lsu_busreq_r := withClock(io.lsu_c2_r_clk){RegNext(io.lsu_busreq_m & !io.flush_r & !io.ld_full_hit_m, false.B)} + lsu_nonblock_load_valid_r := withClock(io.lsu_c2_r_clk){RegNext(io.lsu_nonblock_load_valid_m, false.B)} +} + +object BusBufmain extends App{ + println("Generate Verilog") + println((new chisel3.stage.ChiselStage).emitVerilog((new el2_lsu_bus_buffer()))) +} diff --git a/src/main/scala/lsu/w.scala b/src/main/scala/lsu/w.scala deleted file mode 100644 index 161cbc7f..00000000 --- a/src/main/scala/lsu/w.scala +++ /dev/null @@ -1,163 +0,0 @@ -package lsu - -import include._ -import lib._ -import snapshot._ - -import chisel3._ -import chisel3.util._ -import chisel3.iotesters.{ChiselFlatSpec, Driver, PeekPokeTester} -import chisel3.experimental.ChiselEnum -import chisel3.experimental.{withClock, withReset, withClockAndReset} -import chisel3.experimental.BundleLiterals._ -import chisel3.tester._ -import chisel3.tester.RawTester.test -import chisel3.util.HasBlackBoxResource -import chisel3.experimental.chiselName -@chiselName -class el2_lsu_addrcheck extends Module with RequireAsyncReset with el2_lib { - val io = IO(new Bundle{ - val lsu_c2_m_clk = Input(Clock()) - - val start_addr_d = Input(UInt(32.W)) - val end_addr_d = Input(UInt(32.W)) - val lsu_pkt_d = Input(new el2_lsu_pkt_t) - val dec_tlu_mrac_ff = Input(UInt(32.W)) - val rs1_region_d = Input(UInt(4.W)) - val rs1_d = Input(UInt(32.W)) - - - val is_sideeffects_m = Output(UInt(1.W)) - val addr_in_dccm_d = Output(UInt(1.W)) - val addr_in_pic_d = Output(UInt(1.W)) - val addr_external_d = Output(UInt(1.W)) - val access_fault_d = Output(UInt(1.W)) - val misaligned_fault_d = Output(UInt(1.W)) - val exc_mscause_d = Output(UInt(4.W)) - val fir_dccm_access_error_d = Output(UInt(1.W)) - val fir_nondccm_access_error_d = Output(UInt(1.W)) - val scan_mode = Input(UInt(1.W))}) - - val start_addr_in_dccm_d = WireInit(0.U(1.W)) - val start_addr_in_dccm_region_d = WireInit(0.U(1.W)) - val end_addr_in_dccm_d = WireInit(0.U(1.W)) - val end_addr_in_dccm_region_d = WireInit(0.U(1.W)) - - //DCCM check - // Start address check - if(DCCM_ENABLE==1){ // Gen_dccm_enable - val start_addr_dccm_rangecheck = Module(new rvrangecheck(DCCM_SADR,DCCM_SIZE)) - start_addr_dccm_rangecheck.io.addr := io.start_addr_d - start_addr_in_dccm_d := start_addr_dccm_rangecheck.io.in_range - start_addr_in_dccm_region_d := start_addr_dccm_rangecheck.io.in_region - - // End address check - val end_addr_dccm_rangecheck = Module(new rvrangecheck(DCCM_SADR,DCCM_SIZE)) - end_addr_dccm_rangecheck.io.addr := io.end_addr_d - end_addr_in_dccm_d := end_addr_dccm_rangecheck.io.in_range - end_addr_in_dccm_region_d := end_addr_dccm_rangecheck.io.in_region - } - else{ //Gen_dccm_disable - start_addr_in_dccm_d := 0.U - start_addr_in_dccm_region_d := 0.U - end_addr_in_dccm_d := 0.U - end_addr_in_dccm_region_d := 0.U - } - - val addr_in_iccm = WireInit(0.U(1.W)) - if(ICCM_ENABLE == 1){ //check_iccm - addr_in_iccm := (io.start_addr_d(31,28) === pt.ICCM_REGION) - } - else{ - addr_in_iccm := 1.U - } - - - //PIC memory check - //start address check - val start_addr_pic_rangecheck = Module(new rvrangecheck(PIC_BASE_ADDR,PIC_SIZE)) - start_addr_pic_rangecheck.io.addr := io.start_addr_d(31,0) - val start_addr_in_pic_d = start_addr_pic_rangecheck.io.in_range - val start_addr_in_pic_region_d = start_addr_pic_rangecheck.io.in_region - - //End address check - val end_addr_pic_rangecheck = Module(new rvrangecheck(PIC_BASE_ADDR,PIC_SIZE)) - end_addr_pic_rangecheck.io.addr := io.end_addr_d(31,0) - val end_addr_in_pic_d = end_addr_pic_rangecheck.io.in_range - val end_addr_in_pic_region_d = end_addr_pic_rangecheck.io.in_region - - val start_addr_dccm_or_pic = start_addr_in_dccm_region_d | start_addr_in_pic_region_d - val base_reg_dccm_or_pic = (io.rs1_region_d(3,0) === DCCM_REGION.U) | (io.rs1_region_d(3,0) === PIC_REGION.U) //base region - io.addr_in_dccm_d := (start_addr_in_dccm_d & end_addr_in_dccm_d) - io.addr_in_pic_d := (start_addr_in_pic_d & end_addr_in_pic_d) - - io.addr_external_d := ~(start_addr_in_dccm_region_d | start_addr_in_pic_region_d); //if start address does not belong to dccm/pic - val csr_idx = Cat(io.start_addr_d(31,28),1.U) - val is_sideeffects_d = io.dec_tlu_mrac_ff(csr_idx) & ~(start_addr_in_dccm_region_d | start_addr_in_pic_region_d | addr_in_iccm) & io.lsu_pkt_d.valid & (io.lsu_pkt_d.store | io.lsu_pkt_d.load) //every region has the 2 LSB indicating ( 1: sideeffects/no_side effects, and 0: cacheable ). Ignored in internal regions - val is_aligned_d = (io.lsu_pkt_d.word & (io.start_addr_d(1,0) === 0.U)) | (io.lsu_pkt_d.half & (io.start_addr_d(0) === 0.U)) | io.lsu_pkt_d.by - - - val non_dccm_access_ok = (~(Cat(DATA_ACCESS_ENABLE0.B, DATA_ACCESS_ENABLE1.B, DATA_ACCESS_ENABLE2.B, DATA_ACCESS_ENABLE3.B, - DATA_ACCESS_ENABLE4.B, DATA_ACCESS_ENABLE5.B, DATA_ACCESS_ENABLE6.B, DATA_ACCESS_ENABLE7.B)).orR) | - (((DATA_ACCESS_ENABLE0.B & ((io.start_addr_d(31,0) | DATA_ACCESS_MASK0.U)) === (DATA_ACCESS_ADDR0.U | DATA_ACCESS_MASK0.U)) | //0111 - (DATA_ACCESS_ENABLE1.B & ((io.start_addr_d(31,0) | DATA_ACCESS_MASK1.U)) === (DATA_ACCESS_ADDR1.U | DATA_ACCESS_MASK1.U)) | //1111 - (DATA_ACCESS_ENABLE2.B & ((io.start_addr_d(31,0) | DATA_ACCESS_MASK2.U)) === (DATA_ACCESS_ADDR2.U | DATA_ACCESS_MASK2.U)) | //1011 - (DATA_ACCESS_ENABLE3.B & ((io.start_addr_d(31,0) | DATA_ACCESS_MASK3.U)) === (DATA_ACCESS_ADDR3.U | DATA_ACCESS_MASK3.U)) | //1000 - (DATA_ACCESS_ENABLE4.B & ((io.start_addr_d(31,0) | DATA_ACCESS_MASK4.U)) === (DATA_ACCESS_ADDR4.U | DATA_ACCESS_MASK4.U)) | - (DATA_ACCESS_ENABLE5.B & ((io.start_addr_d(31,0) | DATA_ACCESS_MASK5.U)) === (DATA_ACCESS_ADDR5.U | DATA_ACCESS_MASK5.U)) | - (DATA_ACCESS_ENABLE6.B & ((io.start_addr_d(31,0) | DATA_ACCESS_MASK6.U)) === (DATA_ACCESS_ADDR6.U | DATA_ACCESS_MASK6.U)) | - (DATA_ACCESS_ENABLE7.B & ((io.start_addr_d(31,0) | DATA_ACCESS_MASK7.U)) === (DATA_ACCESS_ADDR7.U | DATA_ACCESS_MASK7.U))) - & - ((DATA_ACCESS_ENABLE0.B & ((io.end_addr_d(31,0) | DATA_ACCESS_MASK0.U)) === (DATA_ACCESS_ADDR0.U | DATA_ACCESS_MASK0.U)) | - (DATA_ACCESS_ENABLE1.B & ((io.end_addr_d(31,0) | DATA_ACCESS_MASK1.U)) === (DATA_ACCESS_ADDR1.U | DATA_ACCESS_MASK1.U)) | - (DATA_ACCESS_ENABLE2.B & ((io.end_addr_d(31,0) | DATA_ACCESS_MASK2.U)) === (DATA_ACCESS_ADDR2.U | DATA_ACCESS_MASK2.U)) | - (DATA_ACCESS_ENABLE3.B & ((io.end_addr_d(31,0) | DATA_ACCESS_MASK3.U)) === (DATA_ACCESS_ADDR3.U | DATA_ACCESS_MASK3.U)) | - (DATA_ACCESS_ENABLE4.B & ((io.end_addr_d(31,0) | DATA_ACCESS_MASK4.U)) === (DATA_ACCESS_ADDR4.U | DATA_ACCESS_MASK4.U)) | - (DATA_ACCESS_ENABLE5.B & ((io.end_addr_d(31,0) | DATA_ACCESS_MASK5.U)) === (DATA_ACCESS_ADDR5.U | DATA_ACCESS_MASK5.U)) | - (DATA_ACCESS_ENABLE6.B & ((io.end_addr_d(31,0) | DATA_ACCESS_MASK6.U)) === (DATA_ACCESS_ADDR6.U | DATA_ACCESS_MASK6.U)) | - (DATA_ACCESS_ENABLE7.B & ((io.end_addr_d(31,0) | DATA_ACCESS_MASK7.U)) === (DATA_ACCESS_ADDR7.U | DATA_ACCESS_MASK7.U)))) - - val regpred_access_fault_d = (start_addr_dccm_or_pic ^ base_reg_dccm_or_pic) - val picm_access_fault_d = (io.addr_in_pic_d & ((io.start_addr_d(1,0) =/= 0.U(2.W)) | ~io.lsu_pkt_d.word)) - - val unmapped_access_fault_d = WireInit(1.U(1.W)) - val mpu_access_fault_d = WireInit(1.U(1.W)) - if(DCCM_REGION == PIC_REGION){ - unmapped_access_fault_d := ((start_addr_in_dccm_region_d & ~(start_addr_in_dccm_d | start_addr_in_pic_d)) | - // 0. Addr in dccm/pic region but not in dccm/pic offset - (end_addr_in_dccm_region_d & ~(end_addr_in_dccm_d | end_addr_in_pic_d)) | - // 0. Addr in dccm/pic region but not in dccm/pic offset - (start_addr_in_dccm_d & end_addr_in_pic_d) | - // 0. DCCM -> PIC cross when DCCM/PIC in same region - (start_addr_in_pic_d & end_addr_in_dccm_d)) - // 0. DCCM -> PIC cross when DCCM/PIC in same region - mpu_access_fault_d := (~start_addr_in_dccm_region_d & ~non_dccm_access_ok) - // 3. Address is not in a populated non-dccm region - } - - else{ - unmapped_access_fault_d := ((start_addr_in_dccm_region_d & ~start_addr_in_dccm_d) | (end_addr_in_dccm_region_d & ~end_addr_in_dccm_d) | - (start_addr_in_pic_region_d & ~start_addr_in_pic_d) | (end_addr_in_pic_region_d & ~end_addr_in_pic_d)) - mpu_access_fault_d := (~start_addr_in_pic_region_d & ~start_addr_in_dccm_region_d & ~non_dccm_access_ok); - // 3. Address is not in a populated non-dccm region - } - - //check width of access_fault_mscause_d - io.access_fault_d := (unmapped_access_fault_d | mpu_access_fault_d | picm_access_fault_d | regpred_access_fault_d) & io.lsu_pkt_d.valid & ~io.lsu_pkt_d.dma - val access_fault_mscause_d = Mux(unmapped_access_fault_d.asBool,2.U(4.W), Mux(mpu_access_fault_d.asBool,3.U(4.W), Mux(regpred_access_fault_d.asBool,5.U(4.W), Mux(picm_access_fault_d.asBool,6.U(4.W),0.U(4.W))))) - val regcross_misaligned_fault_d = (io.start_addr_d(31,28) =/= io.end_addr_d(31,28)) - val sideeffect_misaligned_fault_d = (is_sideeffects_d & ~ is_aligned_d) - io.misaligned_fault_d := (regcross_misaligned_fault_d | (sideeffect_misaligned_fault_d & io.addr_external_d)) & io.lsu_pkt_d.valid & ~io.lsu_pkt_d.dma - val misaligned_fault_mscause_d = Mux(regcross_misaligned_fault_d,2.U(4.W),Mux(sideeffect_misaligned_fault_d.asBool,1.U(4.W),0.U(4.W))) - io.exc_mscause_d := Mux(io.misaligned_fault_d.asBool, misaligned_fault_mscause_d(3,0), access_fault_mscause_d(3,0)) - io.fir_dccm_access_error_d := ((start_addr_in_dccm_region_d & ~start_addr_in_dccm_d)|(end_addr_in_dccm_region_d & ~end_addr_in_dccm_d)) & io.lsu_pkt_d.valid & io.lsu_pkt_d.fast_int - io.fir_nondccm_access_error_d := ~(start_addr_in_dccm_region_d & end_addr_in_dccm_region_d) & io.lsu_pkt_d.valid & io.lsu_pkt_d.fast_int - - withClock(io.lsu_c2_m_clk){io.is_sideeffects_m := RegNext(is_sideeffects_d,0.U)} //TBD for clock and reset -} -//println(chisel3.Driver.emitVerilog(new el2_lsu_addrcheck)) - -object address_checker extends App{ - println("Generate Verilog") - chisel3.Driver.execute(args, ()=> new el2_lsu_addrcheck) -} diff --git a/target/scala-2.12/classes/META-INF/chisel-module-template.kotlin_module b/target/scala-2.12/classes/META-INF/chisel-module-template.kotlin_module new file mode 100644 index 0000000000000000000000000000000000000000..a49347afef10a9b5f95305e1058ba36adec7d6dd GIT binary patch literal 16 RcmZQzU|?ooU|@t|0RRA102TlM literal 0 HcmV?d00001 diff --git a/target/scala-2.12/classes/include/el2_lsu_pkt_t.class b/target/scala-2.12/classes/include/el2_lsu_pkt_t.class index fe470766d2b222d3e15eb95cc4f7274fb6a7ffe0..dc50cae8fb1f4d0d4f8c797550240880a1e78b57 100644 GIT binary patch literal 3033 zcmaKt-B#0B6vy{TnwFH5nj(}^Km$do4%D_FLJ>@>Lbbpkii5&*(l$UeB&AIiT&}s8 z>+wm(ZxLN{F%K{=GjA|!b`lz;E6mN=|MT%XXXj+^eg6LU&%Xd*93B(sQna$#sK^Of zO%>I8qgZ`v6b&B`0v+WYr7o-KM7E(-RM`hKfivc^lGPupmnBsqFi@~Wq9$*ta@k0% zn!~Hgwk8>knw%lPlnxBJPN+jK8BU92AxK0azQ>RpSrMj^UQ!}{TB5U5goyO;iZ|y; z5!RRINtg}fDbgj-V|;(aBPKO>eF>TKYAK(YcC?AnLBrY4(G~`yquKKk~L8RL9-aS%ce{em0lgnAdwU?eqb= zCq%DR*4JVW@te*vgr##NbRo(_h6YI|6%5=AYn$oa?O|S$S<1((8S{aSG!@vpvpp8g z%*B~JuJ0yMMhOvmytIAqW%p8FrkkFi21T~V&s^^vBGh2DnBw^CqokqydUv~HfTtL? z&?Ax53y~4XSY&dW?h?a+zHx!(r}mfn(^UKB%ZtHYo@(c3tbV|@I4?aPi{O0nWjJ8Y zFUIzlHqjs33UnmCqis&?Y^NIB< z<$9Kz)Hkol^oskq$naThBPq|NVw1t2zgxd(`SHtosBb~kc%pIn-WuW>L7cl_XiyXK8Izvx7;S$-|D5QHWCgHpAs9&qp@2!0${ z!QYkBD;O$4{9W==W49#N?n@;VM?wW1%m12GQ_TMHAeYxPxn^Ysz60Q2)f=_4d>eC! zK;&LSGn8Fk21Z;g7Cx)D=#*!k=8>K39066+U!@`(5G5R`|0kJm3mXwZccP z@HtmF(+Yoah0nXf*IVJQuJA0(VT7BB@egK#nHaAweS}*_kpBV&RLe(j?=uWJ>Y}6K zj=JoqQAZ^lm2_0vQ4@}ubkvliGLE|b0UfdvbQTL3z#rg;*O=9Bu=>A+5qJkFcn>r1 z0W0W7taG2>5gbAVK7$5Fun%A0H~0#_Blj(_UmYhl18cZr2>176$_KzKnmqPdcxau< zz)xt~@lwp<;HyI$tmD8Pyrd2+#B*R327HIpKoTN52TVAWkdTt#II=B3iIBh+Ieqzh z(TC_mv^kQ5W_bZ{|*3y@D!m%H%rE5 zSxah0x?of{3+qqqf*k-vXezDhRm~VkW;V^Tp#^|PIO4b!-FaWNq#7#1i78h}RZ(ZbjAP{o}*)aY&=IWG^c>2~_4EiH{c8_z7=vf9QP z`Iq8`+;OSAxDdZjXF4jN$Y(Knx-wG`aaG{OK zmA;O#@q~~g|6|x8=uzYciz|0tADihMJH`)jU5eNi6t1*)W9Hms{*DyMJV@F4Pq$Z^ zPDD6CoN7}s{YnvJ?28Sr@GVMfsB=)}BO@7^S&6Z zr(U;)ob~DWi+4`eb(0*R0}znf1%cg{73tPsb*#&e7%Z zsB|m2*k7ty}xKADm_lwOS2;NOkf5 zxBxUFG&8_dlQrbJT6(IkXz_bF(~bwA2_am!6o4aCVD9?99c#GdinT`2yViZZY_A5O znTql(#ba==8Ld1jjvXK!OvVHYCAGPaBrt zl&6hIAbT3^(dB7ZBU#{LI0P{qF{~%q^JrV8#-BfpPZtr{7VjpBI`M1E2LGoWj z!25Jv`_4@?)+(lIB$xF{#Ws>I?+Nh`mV$5;@=X*a2Z zAjIx$nzp{CE$CI95Q=G9w(7PO3hzFoIn$tBa^|u{rCNJhiGCb?34jnpoq8ZG>X6-) zM0HmZ(OpS2cO{YBl|*q@62VzkzIyO`Cb)wM?ym=b zV1hfD;B-CsBNKd_2_CEmZ!y6qnBa@`;7?5ONhbJGJ@_*de2NJktp|T$f@LQ7ay@vP z3GQNouhxUVGQr(U@U?pIHzrtt3^AMv12?EFsW32nb_*u9Vd^W)l6Gec?)$dk!8SbF zhT<1E&9I$i*v>O-eGFSa!|02~JGcq&;Q@RA6F$Pvum!)sC-@aU!*}=sf5JBW1z+KB_=Zh{+ifiv-f1lYEK|gG z;3=j=9npDzBGeB>YWNX)D@0gvcNbulWFvhZr%eT_&;U9aCh2oE(c6{*w?)xw9|!t1 opuuT(^y5H-Q^(YEX>f{?egkN5*hVLy!J!WAPs0<6#|r@e0tf1mNdN!< diff --git a/target/scala-2.12/classes/lsu/BusBufmain$.class b/target/scala-2.12/classes/lsu/BusBufmain$.class new file mode 100644 index 0000000000000000000000000000000000000000..9d831a82b239d57d995b2095939c79e974608ba3 GIT binary patch literal 3935 zcmbtX33n4!7`-oD(uP1o3#A2=qJySE8K59b5TPw-F)SLW;#Q~0OBtBXgvkUb;D(C( ziu?KtJjVr!ho0jP@JD&PZ)VaAZNQvkdpgOy`QG>Lci;W)oBsXJt-k&!$(I? zZx%KI)XG~gB&zTjEtg&p)&NmacCk#4Rwf$6^YXff8_RMLi z4?7oR@dOvo?&YsQ$DV?vueKn(o?twB*M(}NAmYEzF%*g!g5 zoJ?dJg(h(i?p=a*tYc2^lu4qN6s2X%$l@3w2&|}On1`QLkn}~vcdJUxXq|M5GXlv- zb^=^i%cB4;B#J8~@co5aJ|q*l^> z+7Bhsg;Xcm-kQX6bgOUMNJm63zOW`Vd6p9{Xj=pxOb><-|4TS0nv1M)I$v>Zps{q4 z=)npFbT=hj2Rc!ao+n)*y{%IMpJcBHh1^onOpNqxk>qs>jpIG#=*uW+wm)pcVF)1+`BiTxN> zZt+Z4JDyEpxP|5)R~K4+cTh>5xD3m@sGKd17X|LCX9_JmXG~8P4H~&oG76sK&crc6 z(={wFGA3{}TFYJBKO4asns8*~wu#4Q$}$^m)fz>MCyW@Dl{Y;}`VCAb@G=T4y2$o7 z%4LhL(=*?1^Aclh2~*wV;}o|-PMco1OBy%Vs9K)J#y^d|Khxh{7 z*W5D*9jz}B$NPNYnRFbl;<-jy;97&F8oku~A6eff`ruvZHuT~1h{iv}M+tm@kE!ub zcr03ei$=;w;xoM04S~;DP2QZc4X^6*wWc+AyXnfAwmeduo|Nu!)%mo8oWqyAaf5Ea z`*1KZD$A}c(7)J7si5j(hHFeq9wyXUa?GZ^jaWvdB6*w0J5{$J51J}rYPiN>Fptl> z^6EWu%;u|&9J5R8iZ*`)Te#P)1l!JQrxF}nvRfU#{EVri*T3h<#+Wbsv6YPJL@!ox z;bF|19X0>khaX982FW6V)%;Jb~PBgh_CrQ83bUxzdoH1 z_Y;rGzMIi86`k4mCk9pW#j|^Zh;X*bya5?z4Df3BhO>Zg`PasynWYJA#6z64Xo1bm zF0h8gh+4`ue#$O#88D(Vbx`ni4E@4o7eiiH@bU(1UB~w3*m|T>KF?goaM$ECI^+&6`5Iric)CR(s>H;`>U zWnIYoBB@jT>c9^7Z-A)PPsbcaPu|1DaTeAQUdp>$H$L=mf9otfhSec2Q{2QZp(Az~de{-$n6n$JQN=l~-N*jh zK~2Z_4?`Eu^GOSPB!LTZMW6fo=_KO9NA+;_$oj= zBo?ql;-e5}(k#Fd3(uW>-@XHQh`R#oQJS^8S=!BpBN=KpP?4Odpr=FQ zdT}tRKoFGrGLr2i(c;}Ycl9aUcblVTLI?P6%N{*x#v9j2Y zc?~Br32inta~20LWg{wU)qxEWuXoSb{kdCtpoPQU;7`V9bf;4Xob?FU*j@SDMSN-akQLLfb% z=Tx()V`@jk2^(=4L;@Sk-abY2=`iq7#$)DH{Smb(fz9^(p?PdPn+S_K76)6t&sWxzyizT^&4jSEWjZk|+FKijWqD z^OCAI#NxRbyMOlJZEbS$GMAw(B_q{lonk|di*=<#Pqv4HNLwX)vY3?o_2b?nQ&p(C zB?{TRlFKNCx{&;EU{>?`^NLhQrb{7b0&C?r?cbcc+_M~0uk2Cm;pO3M3(&00m+(eBB@rH<(Rl%y{8goItkxYis*~Gvb!(Je;@G z{&7FO+HT-*Ys$2yd%=tz*3h3Vh8()aECE?q4f|~1P1yw-1!2i9ryjNv%awx!+=P4x zxP`P@uEFrmhm4=O#xeEilyT-EQ|0<<1Y*1Fy~jqBGXssT8+aqOZ`qibd$ky)Z~4~H zW(~)2ISu<^h3M7sp#}mh;eQ4o;u3HTXm6sGMNLpgzd+{RC9Hf7A#fW-!W}^xp~wYO z{{zk~z;_TVz#6EiuT$6OsmKzmhp8(F2|pS8TteZ~+z_FNS^x>QP{$D(L6LokLJ1wB G1n?6TuBs6L literal 0 HcmV?d00001 diff --git a/target/scala-2.12/classes/lsu/address_checker$.class b/target/scala-2.12/classes/lsu/address_checker$.class deleted file mode 100644 index fddeed12d664e5864ae19ba8a7fe11143629227a..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 3717 zcmbtWX>$`t5PjoIwh%rspg_QY2(m~JXCTNS-~%v-BM6%i0?t|*+l$w`Vzn|hImtop zlN?_YzNac7U?`}{56F*7<<0KOT3aedRguek%=YxW?tcAd{{H95UjX*wXMr_Fp_tTi zIa?MAW7#R0otAbi1R>CVU7OXChGtGC&y8P~Sto>gftEs6GqmKfd_IImfzZue?tsAd zvbk=~TGKLlMmkeg?xbes3|WY!Eo-{SNzDSARyGYGEYRfHbA>bK21n9EF@d$|YFJYO zt#VFgi;ixY8Ar1n0db1(U0g8&jm5?^d$J(VbtPS1Ipf&6Imy{w0Ylx?odGK+8BW>@ zG;0|KW2f)rOwrNC4Vg^q1*g9_F(GZv&eUSp=Nla_ny#zer2)HWI{J)E_FHo@H^RkJ zNBAeu+?O>JmLmf7@!nCUqtAVfU_I7_QHQ8NgBMhHytistjp{SA))V&^XC_kBOe1&} zn^vI-o9WY;(wV4LIcaF~GB->Jq)5rbBK(wsl&lzDDJnIiVcg2i3q%6m32<}Cj{>+n zQCum4=deTJiwksAe5cnLO*hGoc$GA$RU6fJuCpb$PF33oUcfH3QqoQPsR-K8-ok9} zji3Xa>S;gI5#WnUtg)E9!3lG*Jpw!8y*|YMBF;!{mZh97=DsvgojMV8VT}TMm=rDp z9VzD4R21ol+2aGRDMTmGA)HwW1PxyYfLjObE0U* zOnEcL%0!t`B@xotJI4E%k~LS-*iqe8KZGz4#-Qq^?LH}o%v|2mO(#bC*m7NDfmgdJ zNuIZ5PEJrLPYAU675B$d5v;~=3r<3*&bI0jkU9S=y7 zC$lc)&*EH|9?sKymMtlbeaS&vpLMnQg6e~1qwb;?Tadv>1RJnXX~ZSfy1kYD+i^L9 zW9U~lSK6BJMmzfJxgUhog~H$Ig_t2=&CqWt%?m*j*jg4(U*Xf*%y>?t&TA7|*0JpQ z5VEX`W;lT{fjhwb; zg+a^b4eC+XVka(=kG9t_-N}3ytd`d_+!ThYX-tJA^)41?z%AWSspl@pLeX&O+k_Qn zsq$eoAgbuns#=!9+vK(x#j3T`G_Gn>1B;kd%5+meF|%UF4oa$0*$^05G+uqjRGPXT zZ-sFSZ%42d+Y}StWg=oZS@5eaz1kAW!79}&aYN=jvs4wDQQ18rm6Xae9V{;q!UsH1 zj9ZpdaBM9vaJR}*)lL!rhbT*ElrTT17Sq)8E$t% z;B!Wk(I-vKDcWR9gLjf>OY5dQTbvn}_C?i8Y_PP&L)56o{^Gko7#@^)TV^R0Im(6? z^?A+KW+a81)QAk5RFVNhD-Ed1eLQhfm2+#cC zz6hl{zCn_AWzv{H!8d%4cm~+wu1{^jHsVp<57W9%StoWrMz3;S zIeV>V;m=l{wgE{C1(}hERe#+H*fK)AbysW>( z4D{jU#U$55Z6{5M%@47!c3i4de%%zV4jjQNbhNB)50R?fWtqrF1FqYnY76x1*F)6m z*ZdTNmmgtBMJ)oHy+eUVDNWU;#HSm9e$DN%$4b zxJSheQa|dGw@#hteHa67W72Wr5$wdDaM(X{iKn=AnFH@E;Jvcr%3ksvwukXPZu<^Z zrz)hO#1ni0sIb@)_@37=KeS*K8!?Kze6K?YKk&YhPdf3wj;pwaF}#U!{$InVw7-fU uX>n9gj8yW3g6{UcP}y;tn8E{|lGtrjN^BG$Rk^X?kV_7s$|>*@z2IL$Ms)rF diff --git a/target/scala-2.12/classes/lsu/address_checker$delayedInit$body.class b/target/scala-2.12/classes/lsu/address_checker$delayedInit$body.class deleted file mode 100644 index 217cee434ec3b3c6690c16f30b41db8dc9857f00..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 770 zcmZ`%+iuf95Iy5uOwzPTOGzoWmey2hD`6_ZQxFm$Dn)V%QrfmhL z0K`S&0UnX~D8#Ir7ozau**Ts$bI#8G{`36@fcw}XIB}M{A`DZRWiNxF49;chgfbQr z8TM499X|;tHi)p11tJ!1nkyZRr2E*|#*H)U z=73P@?4CBTgk~L!Xc5-__3|WnC&LqVYh#5_J~`?g6V|=|6tT8dT&dwQ+FY!MQAXIA zYjXA;*>v?`#B&}oeP?b<*9g64gqCrG>7OQ{Bs9H9$)kMa%k)_IF(WHp!s|E{X=L&# zxH!-vIPZ(`G;j5#9wy-nk&2PzWw6ltAj#7}9!7?wIWQ~jshHV&>Q%x!DG(g+#h3Ys z@Eo%TK3Q1CCDa(X#n}Un#BpKoGZwyL`4iSY6h#~StroxDW0TK~i!xlrI%mYrt}~UP z=yS9Q+c*A;ipUzn@Bn2~9 zcvMzFCp+4^&3(3_H~!mxd|~;>6V3@Y8vZG_`@~Uya(>-`Z;y4Dfg4eun+Pd>%B@jE*%K_FR&u5K zOoutR6#)t)aKpDby>*+5Bj4U*0XyM>2c%iMd`g65lfMtR#RRu0>G`9;;#-bOh57FJ zRra0G8Mxf^JYTS=A2B2@egv$51Tp$>05X|CHc-Am*$hRbnD`EvduNdS7D3=PO@%yy zG(kxVm0khPpM&oZSb`iBDPES&PD)87u}7s@f1lGCb z%7E<-W=XSVF6Ud5wl$Sbn_kgNZ;L|+EU_k?vh8jkI9Ty=t{uk$f%ugzWy^F;ffd>X z;#ep!SOtz=ExC^61S7>l$#L!RQs5N5a(Z@m#5K$1I2H+X{68*^q`)!_n4760OQtnt zPT1+Q881l3u~?ubG8IRQK(m@}&{)Og{bGU8GsW{xE|`p?m1dYdCSXXDS%cX^)^ew) zV63WP#4TD=!xSh7rXMJ)W^-JiCLpzPK52Wo+H69uR+n?AT~ppu1-AIpl{8oW;2W&fq+?oDO`) z3Iv84Y&-{06RTY70-j8At)~Rm^w(6+7Ug*ioWL_lG~puMv3j74SE|UkewJ5UgNB1@ zla~@OVKo4h4-r7ussqA71(--6k4c7)St_~L3|z*>Bu5z5L-oBKG6QqCrY^eE+Jq95 zOB9mag~vFnZd)mgqa-7|I#$g%Dif)__z5fl-8&T(iK8OWdJj^8t|ah0t_t+_XX=qt zU3+%sqWp5akfi*J0)kiB-Ef1B7e@a8Bh?Sw0hRxVcnL2ju?(*W4Ac#x7q07{3AxL7 zEy*Lj&SX_RlAMX-O=fIu+{N*hz=Hnp_TNt8Cf;et;Nz7by#Du?C~D@I8CBN!Ac6Ps zVUi8a-!@0AFprF=WYfanw~to}mu&xxdC8@Zw2l>7-Oic5Bl|Ohsbh99S0-sV?8B^joIWi}X2x@=F5~5kbT>7EZA>st ztjJ5zDzhB9R+*<1WtLKuc}P)aAw`*k6lDfdl=(+dW*=&6|G4<{!z#@EO~MYH&F|CvSuTcn}YHyoNq@h+abjm_aia0}N`UDLQejaR4fMuW_a+t_*^GJ{g)SKPdC2k$nZZ{Ehv z`#|ri%f#o{#O}JtoEsgc%tyB%57TtdG9TXs&$4%Zk^S?F9GG8ZWPXv+`9+S@Mea3B zc%n>QWUfOWonPb_Md%=U)6rFEy78ZCW#u^E8Q?$3XG$-t;Sm;-DORN$e6jz)_xN9| zg#VyJEJLRlLYKIJZgCww;(PRp-;ox7V|{E9HpDigFDBQLnsek!-} zv3in^Fl-TAi4Air-&e9>W#Na0Y?wX-ANp(<&U~fIhP9TjdTbZ`DqxqzfS=~FVbH2# JD)23J;6D`-Y`y>h diff --git a/target/scala-2.12/classes/lsu/el2_lsu_addrcheck.class b/target/scala-2.12/classes/lsu/el2_lsu_addrcheck.class deleted file mode 100644 index f34046633a5fa52e5b8302a719ee4a22ab212d74..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 107895 zcmeEv2YejG_5bW@_fBOc-$};yy33ZETx2y%mW_=p$+m3CO>!^tSvtwG)vV$I#`F%M zh8{wI0HIgWTS7?)O^^`MDPi_s!~Q473FlGPZ_g^16e~ZNbLgygDkbYi;QW^!9ZJ=P5+raiBNYqoiH$QS_>2 zMIBS7>{+xrdzhlD8!Pr?4_7MGEIr#u(wY>-QymztCs(WfbpHgU*>6^Rm1*UA?Syjw z>SU(3dPs$)9-}B}esz9|U)Ph$^UHO0ZRMWqfL|$3niLq4q^pY+X1~`zCS|U!tX5Jt zRw@&+vlLyMl#)GGPfi-HDo14}?ek}+wCc(ZB{gYU@{UF2Q)&I>WA)UeiE6f)U7;jR zS)@z|45zsM)oFT4(mXETJz=hYkD+9%S^3FoMR~rG;;r_V&r2Dir)!jN`-E!$>U74} zpHJ;pvij6@+2wwJMz|eqp>`B&;dYD;wWB-S4l|jz!#^Q=EN@3(EZToOt1qbsJhQXI z?eiwt?VFYoZeOLbk!Q0@K*>fv@w3AJM^?@!tv2U0`*F)hq@iN$wP%Ct1bH)U=z`f)17T~vNF_*8Q_ z>!)?0c5Du}W6v-iG z3~$|fbmx*~(}6S3ua}QnH=%r5T2ggdzOtpbF)Jl|*z$6%dE>HU7tb11pr-Fx)-r3< zyoJ;Bxti~Qv?HhR^0 zx&A=g2F1J8(>8p?mZCIWnSYd0Q4IZ|J7<|Csd`G=#k!t#Z>KQFF zN0l~j9@e{LMR9c>L~t zZDvW^bX`e?es@-ie}8p(Qsu@4qf0U>w7!+8>^f4-+ME%!W9DtI$jq72Iihe_(nf89 zQa?Xc56qvWESkP->zc|v=x zyzSNNQUbmz^~n>H(ps}|ouuh{x<9a}xN}LtjHNR-VH6pXl2TsoWgXG6b>8;CtepME zSX{Wn=T4ym!EVoi@|l|owzn3{*gs=**^VWL3R}_!FDy?HfzBS7QL&Q)xB0+)D#{|BO+k+XItF?=wb%=aLXlKXU{EC2wR|XGOum z#gyk%o9EmV;1%|^94Z`+!0m&>lnH^foory-retlNJbFa>mg1dThvn?6*_6L`;~H*1 z+qN&B=Iz=zyQ3w;Sl_v|knzf2V)HUu>Xsc`+`h4(W1(ks$;?em#opRu{1X|t!*T?T&Bn0Y&bYpj4@R8!JE zqHM?3u`^28K)2418&!&y?b({Oqr80P#MD6c%CU~$J*!>qrSVg> zb<_1b{Nc&lTmV01i{)x+wu=vV8(WK;7KZ$1iY-X>a) z6;}&}vUW^QNvTe*Qfrg;Ez8f&9=}xg`};aZm#EWY=$Gqr^V`QDJ~JyvC=~_0Xz!Br zaeg&=9GN&gyQ;W%;fk6iGdC5s)D9cHq;u=+AdRbzt+RJ*oIJl})<|5ph$~ka{aCSu z#ygA09ZNE1l)$cQy~o_at`mAaZOCt0GHi5d=Y~?mN&bYqO+|Zx7$@xO*B&osmK$iV zHZ>3RRKTu%YuWZ%&y1xR+b9oHMLdPahmpqmA)_%sd$PrHHFeL#v85dqi?j{thy#mP zOU1gTCAcxD`D=UE&obxkS&kb3#+~Mt6$hJVZk*TNdT63|l9JjHSQjN99;hnWv-?n5 z#5joSe6iKO5k)(87v$`pv8Al3V%_Ks?WiYDx5hJz@8%VwhtJ$r)=bBTfVZr9Wya9` z9cZU${G6!_fj>r1>D+?xa1JIEX34IVWiytvTlLWRnpf-SuMH);T0Bj|J4Ti^SBJ)F zBhciyU&O*GE{?``wxcBe@7Z`(D6k&{s`huawKlf)R&=&^wYCLUcJ;P)cJ$=9ixq8w zo*pkr$74WzJ1-fckSu|*LUL@&u0Z4NKua*Exx2G{QDM{!yVFZXDkLLh#$*b~7S&eM z+0o*tZj3_w)XpVV$fR9?y@9;8Kt~H6&-Qli4(8Pcdv|s=Ee&)uwFP@}YC1c2_jP&6 zcuLn8t;^F%Ac`*FQmeakrv2FLxrtTasnWT`EP!WCNR%>c*4nk=vp76T&vO*LR zeKPFnfzot_WEJt0DSQCU$q96HcI4!H$t)ms1ln6WS}Hp69J;?Zr#;Zv-I~0P;(x*zbwG-VJvRl+gy#@Kup58!rFM9xPXzgfdYHVz8XhM&L zG}i(JdZPq--N6>bI91OKb~Hs{m{G#80j|%cZdze0D#YWo1HG%Yv7sB?8)OgUz^H6l_L1{&t5h54(qn-YL8cLaKZ4N&B6 zw8ddx(yJ8Yy^TF+d((b&NNZ0+Pis>!h%jpG?V)WjAPThMeL%2@c^1*Y;R20~!JeLm z&fN+bhB~^sp1xp;?d*MzLWZ*lWbcYvcVKL= zeugP@t$`wzuJto?)2#u*);uZ#m5mky1E%I#IqWVQnaJ$68X~_wmPPG@+moI5p zyt1YeO$e1a+E7}iKNU1ouc)lrz(`nXOpwpoz|5>NttebBi1@vr!Toz-#P5ad_hecv zXOOXIZFNm$L;2E02%LJfHPsSqs4l|g6)H5WD6g+xhu+5i5<^q-rVkTocN(%b5c)9v1oZ%G&aVMQaz^gF-4V z*ELk*qBZOSje1%K)2(a3WsRY2ad}-mF5dd8HEY(cs&80RRaw2JssdLSe(e&Z$HLe_Zv#_g;qXWEV^=TO`i+&C2R zOx22bo@WuCTD^EJ;@gU6yI{q$U1ag>uU>(8c8}#zGCJ-=>d|p0QdTIC(QzkIkB&Q$ zGCJ-=%IG-ml!eFfXek}Xqos5lkCuX`KnkV;DILe75$HG`Ev4hQQ%c89I*v!mBK=AA zBK=8ak^ZEzNPkjUq(7-F(w|gD`PHl}uWYDa*|4^*s$o^l+B$IY*3_*nz$k~w0CM5D zu?tq**hLmM8MH)Wbj2cyh`GF55E|vFxDJydexqQeddJA?U$L@*$2(2w016hXsw)}_ zDmGTsppZ@ri^{>4PVq1|V`YZMe!@`Puzuy5N{kxJ&b~C59v>c6c3WjGe<1 z_;}`2$9$W;)tEQUA+bMha(zr{llIf+)}d3KO4h{PNB$45ANX{?yRW0SwLO?u*W2CK zi0`3+wu(SoTOHnMc*zI23-0Lb?Ct684sgO>`CRXKH0OPXS&D5(lwKt(=!wkIn? zaBt`ebO+jlcyB|t$g?0+HWiOwSl`^+6ezlB|i#En>#90-JmNs(H+PJ}_hTa1; zB`b^E*7(`7MlRaA)UA!8rHx#)_FT6%ik3EVS+q0x^<)ph@OQd1wop#C;s#lP0m8{; zfU<3XtiS*r?=nEyHb7QjfSz_4plll;D=7&4hH{P`-D`!O5hhwWi7+VDqu|>-^ZDDK`M8p;?+XlkeDnPh6gOQeP17Rc;Mnn=V zTLv^6?Sn#uhO-7*whe?)Q%Ix6F;3C4Z6FMhLUg&yARGzVniUvC^mI|Ur)gGT5Yf{`;hv^hfk8x1 z7lnJ8W(5WjJzW&;X_^%nMD%n~xTk4WU=Y#MMd6;N*=U2}h@PfptEXvJU=Y#M#o?Z& zS%E=BPZx)Knq~zC=*|q+Mul#|USHqoP`JM8wPqM-0sh3=kG0DPMfmWfL*$st8dw zA}EI=YK}0X<{&&=9t%ef{Yk(eB68-0BZp?A4N4Fm2A%da7BsXs;B#iOI^10+)v$Vr zX0`5MSDQk{O|5pXA(-Ya;uXmb{0rbk2{pjGiy2d$Uqt7{H#gLA>i9I0tl}YC>&1F~ z_L)|+q@O-f(+|rP$WUX!T+ag|BZu*Y7PsnEN9|Fj&UjgikkEiL|2|9t@&|p3dfG>^H$HijWYxD>?Wo z`jqKdGNX|3Q8u%nQZKPISfa0qG*xkd0B4IGs^-b33?-Qew^YoCG` zY%GWHW}_$84x%RnRYo|$P&?Hw+An)p?}xjffzA`?MH=cUNYF36ykGi4>YN}`mkde9 zDk45Yb%o#t8GIseLp`7#OB;C{eY3cm?N!5Qj+>u7%7*u_p+}M}6)?yTM@ZCeH+=OG zm>cQ|>WOK@qn>1tRb+JvQPoor<5QEiZ)AH%4!d^**^?#t@xWpW5tPHZ2tfK~J zvaMDeAdZm_F3*wqS|jHc$$`yovmFoxq@SVIn5 zs9>*vYsd*A82wXStKQ~KTc?oCZrR5;TcPOLLTdH`InGL(S`B}b&AcP8H^>&A`?^84 z^4v|VPc|838)=|Exy2yc`7gH_B*1fb7-R>}-DQwQp1a2&O+0s>L4w@2-yqFg_Mkyp zxa?tr?BudX4bsYUj~iqc&pm07-8}bAgS7G7(*|khxn~X1!E@g>NGHd8-XL8(_kuz8 z@Z3uV>E?Q`u+}UyNDt|yt$EELeLVMlgY4zG9~fjG&;8IK`+4ri206fUKQ+j)Joj^h z9LICNG{`|-)2|J3JkPypkV8E8mO)P7x!)V)M4tPjK~CbiKN;j?p8K;wPT{$~8st=t z{5OM~#&ho*;}xlsnWg6GB<E`d6?%K4Dtxi1q|{iw`erTV>}l$$m9Ii7K1#& zbFBt>lK;BfAWv~wyFtFmqomUy-{P`826>w2dJOUm&-EGPS)SWxkmtC?0fT&-=Z-VT zcX;l2gFMf3Cm7_rJa>{oUf{V?4Duq+oo0}icfyU-xt?pA~RlILzW$gg-r~834DvhPACDO1_gwavLH@vVPZ;EnJol7A-sZV)8RSnq_l!Z_;koAw z@@Jm=jzRvybKf<{UwQ6DgS^XgFB{}xJorExe~i8ijcx9lDXof7*&Q>LEHDKP4t#FF^)Q2P{WnS#n1|C2pd6HOdqzT zwo=@dQl-e2=7>l^F|;I`bC0VQZou>yXpsxJ0AiORkf+h=tUu8kuMKkAg@{|uWETrhHJ4r>Ku9160Vwi824K1IR6`E%eQjKmUrcp zE&s|XTOO8EwtOt7Y%2aU%|_jVtSaqG(DV3Xs!~o6T*8!IF{(H%eQ}6TSd5< z=(c6=5~;4_I-*&WtwUE4b1h*fh4-6qrCEY7i?I!b8;F`=?WibVyHmKDsPiqg(54lx zDT+C#ragf;oSr>{5Di>TJl-$tmCj*EvJEkuq-f~0LFtYd*Ss?xEL9F)!Ev~sV*}D*tEStH z9I+E8da0&6bmH_iRkkB6&gE!rZsIJ(dh|Z#zTb(v+19gzLF^w}%iR#s_|CS2gs(qw z7X!{2)iITIGlmRIfbi?>5qt8SWNce*o#T*aCf=T&Mw|XF{=v4rEri4?E~X5 z!XC7A;@_1VyT&+_a9oVsOeU`yXY%RXK1B!dIFrvv)i{&SNYyx#&q&oclg~)iIFrvv z)i@7NPSwLcJVh(Vd3cIej`Q#ot!(*MICwc?fpd=Y@Dz<4=iw<@InKjVv~rw>C#N!f z9*Fbs6sam1zZ6w6eyOTt{8ClP_@%0n@k>=DR$rVMzZqy!1t}60gcxxrs5zQoAJ1)7J=#`(n5i>qeXn$sWPR`q5tjfZ-x>&5k zn>ty4iiRb@-cQa<)cNi$pUSc`p`OIDTd;B@9wTis_H|HZ_Om@NKGu=kRT+l;`km zYA(;6#J95Ia(ACgWRNm4j{==)kojEobb}ntb7vZ40sr-EgDm8-a}9C~&wa@tfDN8r?SWJ>S-U@# zOrt6p?0l@|zK)!Z;6A$egRXBBF8kywN}OxYu&hPT;cG>Gk$vaYuz=uF^)$*C3kWXb zxo^T^YBgQ%0G3auYENj-L{h*)W`1TD<>c5C={{sCCm)~aI3_;0y~A_g#pkn7b3*$J zBMl=f#6swiG24t+`_sctwD*8k5`d(|yXS_6GVktj70tdo`@`_wbFN;|`Cn7Czi98`7&|PY2~}WggpSFxPVvJfWNPoF!s2}_m0oLT|DctQ(Ef=v zL^kKp_}J6g*WDOw?P%`It7F-k)(%`f|4Jsx7pf+ZO8S$Q?(DY|6s+o4H@Go zL$8iq?b#vHF|=qabu~p-aBwv7(5f1-Ms<#3@Q7h3IP7qqq3gOQ6AOf z=^5x^jAt_)7u#X4Upk`g=?k>MZd90AWYg&ArDvrQO&^Lb$)O`Lmi0N7lna*if!8p7 zIM(p#Bj~nA-09eNO|L!@0|p<%nShSq&>WqnkJ85=r`?A&hWa?iF_j_DR34y*6gKiB z3hR1tdS#AR&qgSRdNQ6Wi>rw#`UD-^)4KY4c3Q_G8v10dI~DRNm;)e3RDBv9u3t_i zdHQs$Ev?2OIF81${taJyyu0<8`YdXhmrO9A&$6$C5TUroD|&UM-8sqdLy*N!T)aPJ~TaP~}P>pWFj(*35L#35LcHmwPE{#%sE`|oZ3`-p14kql( zO$;TY_4!o)XvEoiT*waKP&2VLrMtH+&$7@L>c^y#QF^&T^1{(2Rt`IqPpPzj=oJ{M z^h!*XY;QXGd-cT%*%n4UQWx>kRDFqFolJ_7$(&?Tl1xgmN=^L+?Q4X^NcYJai#qoQ zd#sZ+y!vX~D|U45ukWN&FdVK*SIcg4_M9b0SJdhCsrnjyt!+__lQ&!FBK={sXTtX= zOAd?m`UYx&MeQE^1&Kf#rma)rhmL)F++^sR^)1wRE7l*|zU6O6JDx2zr}Jg4eCnMBcXEv9q#tis8g z!DhG`&k{o{153sny+1|Yrysz+jMjF3BrrV%X0p>0c2_#uXwP)?ev7Efl2vEQrXQ6;&lv%xxxrq^CP9ByDJRzlZx)I>t^#u?n-g}`YKcJ$&erYyoy zs66@*?5F6brXu)GqZeHGxLLLVF1#}&SwDkLu1HqW9}qQvDPdBlj@O z5GR=A@c+98XI8_j->W}J=(LQ|K(7w(4>q+$2Q<)@5?@cCUc$U^qp##-3hO(0T z@;O6U!*ky;l(jtf-DEP~P&V+wOUdMDLwk{<4FK)cOiX%!wgAuG9PM>O+02#SFqCaP z_aj3I@Z3+5$wEVE;)S0llVkAo&U+M(5?<<`9RZB$j{DZf>>8^tf1|%iUGv*yQf??M zoX+pDY??hc>VGtpHZJ=UmUeO(o;bpBhWnLQ|Er59^ZCc#g}>4Nma4z2zn4rF8A>PT z^bgBZf%Yy#|3BW4e;G8Q~uN58i^XoQD|70rsm$#fSaWTwzko| zQLDnUgoMW^?q84Q(cxc@2lq<*;_O3hc@+U%FrH*Q^oCp&lGCfklbYg5@uV5bAR@ zq#wih;Tc0a6#aENSHUsrN40h|w)HgyLw_xc9)Qy8^-RFS$6m}6nhZ}4P&^YolMLk? zZZ-wK^;7a}z-Z8CqY&}jmVywaH6wfi#JLS|nj~mKYcx9N~ zsyhxCp2eKSl4P@;dR$?|1@J$iux)>aSt|YPR7zxp*LJ7{KFOFJiDkXcBhiD z+CQ=Fh9h*)(S!~+o-RYVp5u38s|)|N7n^c;Zm*%-$ba3B?Jrz*EH>)!+(AS62LJUC zw#0DRiP*fub0-_hZTwff!9A19@CJ83&z)%~ck*BH2KOv3!_?#e&tYnE5C8Q7Y^UL} zi?H#B=Pogn`}wbzVv7xzU5?E_Ja?s`Jjj2&+E5kQ>-p1Z+N zp5wV24dr>ByV+1)ggLwSXp z-ESzb@!SKL?OM};rq;cf5*VI`*zMZ$u%W!pbsnYH0&Y=wx>}Y@mgDU*uMfMfmh;@x zcpuGceikpfx$N79@{F~?gMF+E=;`Khqz$?Hvb?iH- zVMQ-7RKoPUs-fyUrx|K8&*83_+#KlX#a`WB!oLI|6un+QUO& zp+3S;hjAWwd6jO*2{ZP3NBh+C4DBWQx=8ho8{+Yfrw_w;cWJO^rkwW1bvZp<>=?^f z-x=I55$LmWY2LEX6PASlIupG)nMB85+98=Xi7;KS7xzrZy`9msZ|)&5*D0&^Gozw< zr=@zQdUJ7kw*@;|dUqP$8JHI86TCAOLXy3Cco?Oxr|^{8+`1okbmzmU{Yq+`;m!9J z;0=@)Ul@E{otV4e1lA7gEt^8tIgPBULmd{nFyg)_6SDUfd*@K9CAjn9=Fi?|B2~bG z<&i2yRvsxmEt1KRDtK4M@<MJ294}EW^n^KHqFm_lalAyi(6ixq ziE^Q*y|EI_sPt4fUZPy+k!`$0xzIz{c!_eMC#>-jbyE7kZKyFHtV^m@rb6JyeUAC>MHS7Aw(=N{_?hCCY`Kb;V1R3q7=omnau{A{8%D zF7&u5UZPy+SyH@2xzK~6c!_eMr# zNNu32o<0K7w~P3Mx1z6o2aaRrlFS->$ZcDPqi1N@68d<H5j;gX41tLEXBGCmSR-}OR=VcrC3qHQmm(7DV9yJ z6pJQUiX{^)#exZzVz~rMu~>qoSSrC%tcqYM)mLS7|n(7rlSkNhHfHU&#@lmtt01_aVf zdNu+}aWVo+aV`Q&aUKFow_9bLg}}-<34x_J2Z5zH1%ahF1A(PD0fD7B|A3`9{eY!7 z`+%i5`GBQ3_kg8sR*EwZSQ#fCuoUMVuoR~quoPzFHK_hLz&v0w%|~1uVs>1uVsx1uQ++Y6s3MU}cJ2UvQOmEz<9R>rvlEXAnEEmrJN%g(`}^@hu%D#R)jfDFdKuD#80qPw(aeVxosgR8x&2CV?TlxMKI5)? zl#JXg#W%fQ8QQOm>{rItPS2guuS{4!<1QE^d0)YQ(+HkDGriEU7^a2~{pqwINa~;*nY@PijzszS2c%RfyE;c%<-M z_lSDRO{y+Lsy-emd}5X*HK;&ef#w#Fm1O`g=C22VGsh7hUk@kj;aNewEd*10^jBSfk(9w{t%knO%f#ngHi zsbGjyb39U5_8?2Dbujn7O)gTqLZo)bBZYMrpCGCB5UGxMq&nqE?HP=xHoH949U|2e zj}+E>$a-q;U`TCok=hp`wLcyyEHjZMb=+V`ZF7-27$S9iJW_|`Neyb2(BL9PwaZ27 z_7JH%;*q-Z2$S0FB6U}Y)ZOt&VHMsH^;DaS)V(26_r)WH#eYYXRJ)5*e~8or@kn9K zp)9FEJt23xNIeuH^>92=SpIlKNp-nMJsKkQSUggXA7N5^T%?`|k$N&7si%%Gscsjk zZ-z*HD;_DVPd%dD*W)7fOo-I8@kn8*>=7l^>mv2-5UKCPBZXDFN0d~bi_~{Rq+Wux+Nc}z@DXh|$CH3}T z0{v2#r~VWo^-eref0idTsCS-jQhy1N`fEH=*ry=tsX<+RZc={>k$Nv4DQube1WElp zMCu>$NMY-SEUAADCZ;ZT#ncBOQXj@6gCgl&2%8W+}o2ouRQbR+ej*3SLJFFy0sUrr{eXfOqsu?0RGBzni z9i@)8NL68lAzi)b%^fx4L3ILMm#8|HA^JnX0Tp$knuFhIZVVPe(q)QXbu5;Gt85u! ziVCq00v}P-Nh;PUvh|U9P^7AQ?t|)dF}}eSI6hxau1*2S40WajQies3blIaPclv{B zff!{N*9funsI$OLv6e`pKzS94A?G9jSt5okO8|17I^Sw|xPPXje-?=`=`vAw|Im#B zynhxr`{!u%&jRL$iWoI4m92qpE#NiK%>|(ds6-7_tcGf_TWZ7=M0Xym!0tT2qVsBF zkX|jujCKnP2<9rflOaSJp`or|HLOwVur8M_>s^h7w^+|hQgX+QF|`NPP2xIoiAI$| zL6@Sg#oA`-m=tv#E)v=?Dav%zrdfeq&)Srp1VtZIeE5;JZL_+?>he{9q@c;U(`U?l zP;HD?adN2QWOb|6BgyJE+Bk}!HelmMl3n3eRJaZQ8d!x*;{Mqwt}eQNg0woje}W9M zRo!KIZ;R!Pdo7IX`l~zDok*c;MM;)1}b|7avayP5ouffCz zWgpahP@vB25w~rxn1oc@_Nn{D{c}(Z$^*mMKX%KKLoG|@EwlT_(GIi$XNbbTG!&g9 z=*i;RTq7vLZ91D`~&gE_qRo!@jgpw9{oMZG}1Pyl!_2fP%37yp-lm#LQv0I%eL zUjg8i|0Uox>Q}AscigV-S5LiL=&-1$!y^9BZYuR!>&jv)`xW(T>UCE1g`r2?ubv?f zjr+9=l57_C?hR7COSTA&ZhZSw;zx*ZWh-3keqRgu;xePjCTraeoW4|RcQQ#obfK9 z@l$ffyM@Nzk~3}-8b2dv+%7bJPR_VPX#5>H<4$2ee^<`9OKAL}obeu^@yl|?-NH5x z$Qk40p3oSkvU{VB+s*fG7v3i#Zmje;AA#}fa>h9AM_~MhoG}gq5*YtT&KPF}35^D}nKE<&1GAmcaOT za>h7DOJMv5Ib)o>B`|(l&KQSv35?&7GsgK|0^`5P8RJMWf$_U?#yHC>WE{Sp-;)ax z9MmN+{=1wp&hZi$|5MHw$9xHl|0QRPQ@{kqAIcfykT8Mqf8>mDhFG+568@IF#A69P zVoYGH${C+48uXJixga@DXzYe95@dZL-L(Ui{N{7518UT|rjQGjhD$8-zD^Rjhyk_!kSme8Q&u` zUL|LIuh4jnobi1^<9a#c`-R5qDyiLydVWIJM zIpar!#yjMU@%IA+6PhMDdpDSlPAT<7xobjtd z;|t`BUlST%Bxn3Rq46bh#@`njUn*z(y3qJ?IpZG)gXBuNAbCS*e6^hM4~53p$Ql1g zXnd`l@sEYZ*U1_GL}+}2obgYE#y83t|4e9nvz+nIg+X$QT#)=iXndQT@h^qOcgPw4 zN@#qSobj)P#`nk>|3+whpPccVLgRipd?%J81g3xK)x@A{8<8!e-}gkA_2&Mh#`NK0OUW#SI=+cA)~JG{}V(0HUY?gi6MWN z0OSW^$Uh_i`Jou{?F1nIErxt20m%P|A^(y9D*;GN4EbRKkh&Q1KM6p3gpf%j0Z6YHQcVCdSvWOF(&Ql{rv_Sz z7}ApfWU3f4IRVHtF=T22kcJr2NB}ZjI1(jg$U{cn&a@0MOP@SsRF4l4LuMub=@UZ^ zO#sp_h8&gvWTqH$L;{dmV#tvRKn@i{j!ppbC^6*N1R#frLw&qFWK^gR7qgro4;dBe zBgBw72|$`+$jJ#njub;qO#pI~7&12j$kAfR83{m+5kt;O0CKDta&`ichW1($W;kI z=7}NKBmg;E3|XH5WWE@3T>_8=V#o~%Ko*LFXp=l-R1g)3S#FVsj0&P+G32%cAm@l7 zwYhq5Q+aj2gy z4;gih*N7p{O#rf14Ed!5AXkVXFGv7#r5N&}1Rz(5AumY)aQ~A`Mva&CV#uo#fLtqvye0w2bz;bC6M$SVhP*BT$PHr18xnxrD2BW-0mw~a$eR;@ z+$;|DTjU|5#>*{Y$lDTt+$x5=BLT>5V#vD^fNT&$-je|2b}{6A2|xzKko^fj?hr#h zm;hv>81mr+Ae+R`J&(#mMm_fg#Vj9}hm5*uG=w2K5?b%~sDrLg8p<&3L@#+S<(FBTfJ1F;X^RZE0zzFMy4rNWx8ku$Cq z8ec1Cyi90(ot*Jo5i( zzjYJwO#c?P87a^lPDVqQpIDzxl0GEEy+p0_;*T462k?W39pvjgyMDZNc73LLNz5v7 zem$*nGOhBV`_+p-wkofRStU-mr&Ug)RX%*bdgaGcrO(tJ(H;%$Gtrnge2-{PY|QP~ zp2ELxJ)k`s*+Kd2&&yaR{cDfWKQCkLanv63`2hLce+^l3ILL3ugnS+>Ul6cdaX82q z|7*zl!$H2Jy=?jNIg-Nu_(c%x?x~sHul?Xb?T6Eo9@Bo@ul@Wcl2SXPU;FhFPik*I zsl9cN_BOQMxkvk3Qor{1e(nDr(LUIirG4lpSNrBapnY_YuJ!B5{d$^1Uf_@qp^>hW zp=7u=U`0CqOu9ky z6zyI+JkO~mN0IXgDQn2(>>kjM%6(8b@oy~tjfZqnzdrSTtv5HfU(ZG0=516S&}a1P zv$OR4hxC#p@}&0K{n|eEGg{uS&$HT(1kGL0uP^G?tE?9Lruk+$8oVq^Uv6Q%dB1k7 zBt~u|Mok#wpd`lhNQ~Mr#vw_J8Ic$(!WbvQTdN+_*J%&xn;z7+U7@y8_uZp6=02?V z5ps`ytnHC}-wb%9UqAGuej>znjG%aOzkd3Y+7ns&nHKI7h(G--8gV~(P(NozI0#qF z3^ff85OWB_xWOFa!0?&AXpFfo4C=HSIfmc# zGmM)}zXK!F%#6k;b7R~@E(6T@QR9#AXkU(_k68yrD=mmpx-MF2VU*I1(MrceD1lTi zv<@>gRQSd@NMdOCM)-0%84$NRE+_JJ2ySQHmStu!cim}bIovhW9BR8uzuPy?H`;N< zRrw~xzT)n?M}Meaf5fFeGq(B@c1TqDG9BzMx`|As4AE*_h>lxd|44>fF9_?9cu zSFo;)J1jhHNBaHRX{hX38tg}zM=@`F+dRtQjbY|6+Z)Gxbdt@lld-3C6?en0Hfb3ptD)Td+2F|767S(QIEvmI4VFeii@ z^RuvH&a-{WOedNXndvXgi4M~oGbd#F%dqMBw&^8s%C8+^v5`$|Vua~iS^Dq77#CU? zxIIlWC$YN!U`}$>J=vTb_LRpNe4Bi;<2VWz8Cbo|uQLa?O};s?t)5_)!4z`}Bl3

#)VD=Y-%JxTn;$&rNit_T+BeIb#5L40Pbt%&4rx<+4v7RV23z-wL%|eG0ip(PB1kc1LJrnyqlbx7; za#l=G{R0MCY!)-nsb;YQbdEX42|AsrmY5|>b*5S3P%Sk}ovO3l_1_n}erK3&_mgX4 zYkrXBu^+_n5OsMtEasYX8KXjTu7gpTS>|LkhmoIW&SR>j<~)b$d~-fi#lx+Bx8@v> z1HP)*gy=YEJpenJ8}KcUZQ>jR1Mw~p-YrL)M>D!*=Ftwi3(N)1mL1Jnw$NP2RFOJV zk1>x4x6IwJgE3ip7Kt0?Cnv_Xsc^YqS4>6y1DE33*ou4tS8kTGc2$|>j&?0F7dc(9 z)QRaQXU74}@>GY%mMd8hVT@yUG|%#W&x(G}YJmB?kLmBS!3hIO9T(Sa)VSJOyR7r_ zdb{l5<&AdP%gdYXaxyP(waY%spurM^20%x1g1#LwTjObTC^p3#$9&;`=ImH*EHklVZF7eePB3+F@Q@VlH7`Jzy?zcy+0{G?rI)N_h3SD6j66 z@apkSuZkcfy}DD@t2<@A+9KmsYXo9mtv0KfS5Gjj9bR2#E{o;WRtc}36y?=c39p{w z^r{F#(yOhqUTu~2>P{K2TH`qL>T+{A^Xh5la)(!I%$itU-6i4GGork@OTw#XIlU@^ zko4*UmLK-7VqO^POH5K}dRa zx2#up%X)Q}j90BW1@r1kb0zcYh2~0!S67*Sg9?hga8_Yhrn|UBatZM0vGc!mC#~y()r`^lH1TSKDR1 z+9u;w=Pb0&tYcpNidpCIYQ0$>%d4G-e?=ykg?7e!6C^ha?exWYsBz9hJAJETPlKGZ z&`$OtKz8mher=Of08&WU}U2m>uUj3T6-r>~^=7v~a-6P@E=qcnL39lYz7P?2) zt9xXE!AGOu25ZghBclesCDSGy&=8a;*VmhkFfW})4(UhS6k zYPYOc_sDqFISbuvZf0Kny1Cim)h*_hSYGXs@M`oFvPZ(Jhna=;$a=L$)~h|TUhS6g zs&f{))!fRwdXu@;;ni*Cwpd>6mGElx6tY*stB09|_R4y-SJtb&vR>_x@v3tc+F&*? zuYSX9aCmjQxjmLw`y{*?J%#L(@akb^p?$Jm?UVItpR8AVWxVQ~g$B$3^Xjc;z~R*$ z=8jli-7DeM=qco039lYz7P?o~t9xa=x>we#eTVUCc(%~t^TxcbdG-xjvE|@NJ4+`Qt9cIO`7ZIq8Y8!>{FE0_?>*bTJFs9=)#b zIM+&~Wm%pl!x+~|VjPUbcq)u>13ocgai#v3Yt{P^KHsuFQPMBlA30if$hSVG3v}nh z$RXb`F%?}-J>-l1iIRRK)NjPU>p;oz!5bfh;)Jx52i2rYvtmr(z2T-&%?U9zU0;t5 z`MP2&(r>l!nw##)zA>>a93Q4AiTGcp=(m68S_3~hRT}%`xY+jB_(KfOUY3BhY@TOO zPQY^{qtH*zkqSdM_THF% z>WpxT-5XQW8CX;^-sOdE_%;4Hu17yP*EcyPwwuMdaV~@i7JhPGOi;QQ!Sfybb6t<; z`eLu!iKMYHHn!_hIM;V{Y|Xbq(QuAC8o-Rk>#v<%b>3m()g9gE#aZ3rZp(S`7-H;l zUkB&;w#96Z$8{Z?7jH3$y?zLt6xnhtAZj&R+1>BEW~<}wx69mR-;L>7I(o5qo^g8U zqIk14YVo35JI*bfYQOB(j(vZn(FE4J&E1UkfVtbjy3K5J-m@KROZ?;_U+k;TT3ga? zwlmPz%ytK8huPr-eci=0Uf{dC{vuqgF?&-F_t8bZqo8JwrhIYXJ)R%aK5*82ahzp- zo}aPV5Stiy!;>Ng;_AeUeN8bbF%T>`r?ZPl5La(q>?aq*N5PtN5sE89fbvj$6kjwM zzN*DdFf?WM6JXvD8}pagBI5Sw{{Kcf_6K}VG%{T;8e>L5m9sp*3Qw$V49}=L%}y4O zzcD)<0oi4C+1F;|S~fqq#8(`%F8w}s?d&o4Fx20gdmO0UW_LW)6>(6VUc4mE2J^bVyFceB}v4I}9x8u#@nd%4T@eb8P<{?{EzuW1I%i}E`{SdMI zALrt2Ke^mjAKQ6&UhpcB`mw{xwnGSWKS=i+f_c?l3KfyeKHrtzIp5SQq ziROuRv+2djR>Gd|Z2lF#MX@V&J+WO8XL=ugc64LMxhq6q$D3fdF*n5IYt3&?GEZWj z(9M$^o;cY&*?E<^<~LXP$(LfIVr~ilo?@QDP`&0U4%Ac4Qyr+@R2Nl0xjqhRs5h^0 zZ56`)E7W$Hc^a$DFi&&TcDi|bRBztstn$h@z3Co8uZ;76;_)&LXP9R&4jJYd4i0CU zXF6K!T!ZWGc*Cv8G{cG6Wz*JuOUL)!D&i`szxoc@OXW2Arf5Kode;Mw8n@$5zV70(@> zyR`xDDDMn!9?}YLy>~s*e(!VM=aK$3Sxwfpf#mk&L&+y0{dA6VD)7PZ0MfzI$ zZ_?jF`k#y;8JXHZ#_bu8XFP@Ujf~%CysZrkxogN%L!QW^v}?%xY~Q z>zu5sv%abg4E^QMcZa^O4Gb$8wsaWk8-CvKYleSK8yNBH5$}!ohc+;B?#N{$Yqfz< z=a0H})b-lH=toAsF#2U}V61=agt747xR!DI#~r5)jDKwWOXCN$feBd?awbgC1}3&n zJa*#o+Ca_|Ij`irrVUKKd-69YKZEp#lm9UJPujqg)+xtM!SAzLX6>H^`@AuEv-0wh zcITavce*xEkW?_V06UQjHWutEXx9b`*A=!D?m~Kc;bnzaY6C@TQC1Q9sc3!C&Z6Dg zK=DBFuZrJ9`r(}PIX-P*&fiM366{wl`FCkXsb3o?tt)LRZ9)1}>8qvi*j7m zdga_(=iZ?Wl%?mx$q<9QEY>zJD;C$ZhroVj3atjZ2$BT@kWYa`4)Cd ze?-cN*KOc568r?iH!Z`IXhWxQjGsdQ#}h*g;AqqmR@FF?5m(b$>)|y+O`k`6hlO=Q z%V~$&H;-gW!8@yvw+K};4qM;pVG$pYi$5aWWGE}(*az4DoOQ(32w@&)Vdi{9n#eFA zA`V2bcHP^3G$M|ktxF^EaC)Ks*+oVk2GR*DqsuNCy^sY}0U0fU?yNyp-&so^87okEs(pl|bY@LoOAUT7m-N|6E_D&W(WbzdTp zT)WdeDXh~Dl7f$!xRd;mz;<2>ACjUYz~0${BZY5wgEeoeA#;vUL!6B{l66EhXaXrc zf(>#u>PXkarp|PFfEg~IScdy6DruC5D@7J_T-a zy6V%yCx*LLd`jHqblIngQw+DQ`V_g%>AFuFuNdxI^C@$m(}kZ#ZZX_g|0#5%)0LlA zenNLnB zdGjVN=h&X#{u%PT)BB$_-m!aN$7ieuoW1Z_-23(lVSEVn^}|LMD1>ucm0WanqNL!6!RS#O8^p#dGk9=kqB zdi{eW?IU86U7ztDvU`ay%(&tuynCQt8?-p^qN+MUR6*Hg&e&uJU&cG6q; z=edm06_aDMO~kJ?kP7Vrq}Py2?M_mquO>_N zy~M8{M^@-}A$^>z^wbl-XCqnVISJ_{WVPo}q%V_tuSWddOtRK{Gt%3!#`*h5e@E6Q z`-nezBH5S>yW|$KDdjriPq~Y1P90CSq+UR_rA;ILv{|Gf?RupBWPAF<#Gn2m2@Ls& z_*YJ890GKw7d^kmjuYWarQuNXyWdNb6DmB0GoWkX^%9k=EhIlHDV2 zB)dkuLfXs^$?lPpN&BcZq;1qe(mDEO(lzFLq;t%F$ewYzq-$I~=^lR~*)#qY(v$r< z>7GDH@5C9TXW}~2mvb`d&AE;2o%9Cjo2-(K$J2^P@LZn|M$4|Y59GZFuIW(=9oH*?Xq`xC4=Z+*N=2ntZbN3>DEjg6?06Bg7 z7IMz??c|&pi^#b%u0i@8a_-EP{l}0khisVs3}iKs9py=atQN8n z`kx?M0oicRUdUELHqx^lvQ?0op1UDi4cTbVRgkTLY?L<-vO37ddQHgcAsgde57}DC z#(T>lTL;-V@AHtYhiroPKFBsemYu9awh^)%@1G&t1lh#olOWp++2rKikZpl%Qc5ah zTOpg8{2pZ6Ae)jx@fsk@O`&+(A)A(323Y{I8L2st?SO20>Mf8pLN+V)63Ch$o0+y8 zvLIx$(~2Q$hAc1b706m3D@c17vYn9S8{dbl6|y4Z3CMOqR+yd(*>1?@qz{Fx4YK0& zwUD(#R+_#LvJS{f(%*ut6SA`O0m!-_o12jd*&fK|r+)}pH)QiNo`S3gvIQBpLe>k} z(HU<;)(6=!8LvaO7qW#zo`!56WQ&H}0oi`Y%Kc*?I{;aw-wWBXkX2+>Lv|cwi!S5F`CqY&-jQZtd$d(WP8f2$H zwqp1>kev!y?TCLsb{b@>M*I@8(;-_qvKF#4AX_uC1hO+BTRrM}$j*YSe$;u8oef#t z=$9co2eNgeAA;;$$kvXf*UWj4Z5T_hnJ+=Me%x`8oe$ZjaY4u~fNbOV0mv?dY|HpZ zAiD^%%@d|Tb}?kzCio${1hTCYkB98bkZqsX0@mb{mcRFO(L)MYk1=$UdwHFMB?CX$q6)2G12w7)AJ7hOO)?Kh3vYR2> zQ@9JVZ$Q>tSP$7Pko6Q^3E8cX?JYbNvfCi*E287Z?U3y+qT|LLknJnl4cVQL9b2>( zvb!KVQ2ZujcSClt_+`lMf$X?BKFIEc>`?K)AiEE;<4e4d-4EG`bN&ihKV&DA`XPG& zvXe_bfb2oYPAYAI>>3dmOSe z=H3C>6Of%f_j1UdgzT)cY{;I1?A)@n|JTNyM@3nMaU6f<&igtnWf*B1grTTO8m8oe zh+Cqlh(VTxqA0Q}D!ElsW}1eY8ih;lWl@@@Q5I&26lN(F#^QqFzT>V@R?pYdUmXu; zKKFO;ecn6F%$fIn&-`(9tWd|YMM8#|rY1nd%fq$9RiyihmFRWdTO9hQTZrjiiMvHM z-r1|Hj%%N`(c&R>MK71)u4VQ02Ebh!YTHO#A8mcL_0zVow*Jyo0(7RixJe6Lu%)(v z+P2cRwYEWb)~%-(VZEaecUPIVo;vQK56?{9ey&^xCW=dc)N@F!Jzfv1wG-_mJK0XL z)AW(_-`L{2j1}Hxtn`0lbzFWfe|8^wI@EL4?jm&;d+60^73&@8r;VVkEkiLd*pa8Zq@hxnl`yG5wcRQ(&_hkpE z2!4Pcp_qxC@DuEUpWzqS4SS%3;=S-I{06144}OO-D5tmrDq%kyfP-)ds^BoiN1z&x z!ZA1wC*UNUQcN>G(9^t_GmM>ub8sFmz(uHmOK=&kz*V>g*C7V_Ta!gPK@V%8=i5i)=M$V%?dHA%xZC#Lj_dAe&+#k z9wZ%tDmV;BpqkmEq+_Jxq!VxwPQht7183nJb?4y%Tx6`qc}bj?;R;-ZYj7QIz)iTt z5r04}{0V=-ZTK7hQ7qA7%K-+QV1W&Fzy)sllfG6Ao_p(Y|(tY3s_27Q+h6kWN zG@$rFQbTA24?$z_0bh6+{NNGrhbGVz0-za7HHQ{-ABC0>2#-N4W?PdUhahMJPe5B} zM@ca0NoWrppd%BVAcSsb2&LPF6vkW9mDCNoLl5Z5#8c1Bsk@jWu4RH(#{~x;NyeIQl~rM8hB$46zUg@sI#X5D4jz z0WZQ7$bxAw6S83*EPx=$fm~Pu%U~s}fwhna>tF)}!zRdwEl>d4U^^5+G3-T$Oq|qe5=cVg z5JCtcB%}eFP@puW5KOFu03ke^2103|DWz!&G);k|G*AjOr3wGJSG%*iIz#R6^PDsH zoZr27?!7Z-?(EUCZ$9}H5iR8pGEGV6dK%pHVh7S`>&fANd%Nq^)x|T}Ox>agG1IU_ zXDa8Wmo#kZ$t2Tmgvy!54Q3YP67h7LX^dQDgsPYp7pmHNp*x*Qr1G1yUEQg)ySF=^ z%4TwP15Y=nMi!wt&8F)jG?Zz$Ws1;nrb=xW zxYnjj9$YP4v|7@sLe=eFwhLYdvxig3d}oA4W9$Z&F-0*-8K*0obYW~R^uTYl5j7^= zgp*JAIPQhK>t*6;C!K8XO*+X`F5Z>~F}dK-+vX&)@wA&uq%s|WeOkeuOC?v@qZ`p}V$F5+*X8%icRC+Wr;?5r?{$(GFTbSwY~JZ&8rz)8 zB+@-ex42?`Lms^=dU;GSpNJ=uo{t1W>`xjzV{Rr{v<9v|SG3?nn2b&~OX+`;Ma zOxEemdP%3t^*UU?qy{C)fklPu@!WHM(?ioqr@begb~;nK_p$bLPp;GHa(cR%BId+z z$?t9=+tmdxzur{N2_`S+7Y#`#b9pD(gXMq$DLF$UC1>y)p*`C!=3O`AuOYu1dfej| zQck?rbK}X27!y4}C>d1Hrib3|x<7>QX!G10dOM_eo>gn?rayrX2sIW7oN8Q0)s@F=v5i>EM%=eq*x1Z|j_S^)X zr;h7+Sr4_wu^#>IO_t1N8EU(T>vgWp<9!?t?Kc00HPxCM32Q))$v|5^-l1=)!Bi@9 z-XGzKvc>0M)twnwqrU$B`42PeYi61-xNc3OauYwS3o*+^Pf~Z6Ss8in0v3uNYn(z+ z7oL*oR7b|ek{eNK=x=oZkEMh$50-Lof6w*pXl@sO=@##mc&|Uy{Y$fOJ9Qvvl`Q9Y zZ`xnIB}^`L9iG}Ht+e%cIXrGlT>R-8;F5?ZI{o0_Ux8_;+slF}-bL}=bJ<*pL!s+M zhh8&Y!Few4wUt!Ri?~|a3EbuS!4UMba32Swp>O1%Po6y*cof*9;aQ{M*`whN8V%1L z4R6qBc=l*`14pCqOsc7$T?}G6yeb+;EjHR;DOzH*&nQ}Iw9hJ9X0*>KT5hx} zidGoyaYZYQ_IX9CjP?aZt4+IKQq*Y5zN~1C(Y~T+t^ikgh}Pl|RL?VlCx zGTOf=YBu%#SkZ2y{i~uqM*BBKdyV$*iuM`eXNvY4?NvnwjP*YhwV1O1RCLgk{Zdh@ zDf=%)hfLXjD>`h-eyiw+(f&u#QDgmIMaPWxe~OM9>syLWXpLFXNu!l3I%Tv^_(XyX;7j5blx8RIuu z(OFY=jiR*CrYY(&))|U2Mw_W9YqV<>bsN9giq08rt|HH9^A+Wc)}SbFv_*<~jJ8D4 zc~i?WMZKnMg`x{aTczlt(Ha$9XZ+SORjo;7Qu%cVfAt~HhQ`^4;8vII!5cc$HHA0$ zkPS_QH{oS(_ueh7&0Fi3rWGGaA^weuxA4{|Z{}@ir6upB5_nQCFS(^dKw7N@yzaA(V*Q>1s{u{;p2ECEVS#l z7vYm7eb*0Q^xY}#yD8NDibwf0xB30KJqFExMJ-gOy&~L>9iaHojc_MZdA%95Gcisv zqW9o2&|5^^R#%ipvj0w7XrVAn5yqQ!ZSndF#TxRWe2x*IX4E$YQLNxGa7&5hJC=K5 z@ITLl;h||IizSsY`^bj&l;`Es4SHjW7B29`7>(iUm>PnKke!3}O)x^*n(zr*mWCM z>>FFMJ=jQZ!)FYbTl|k8O_?;BYs$1^%TTFH5IoDM0$*Jms`cMPpw;^C7Fy!XLQA|? zXoz^o<0 zvX%(SS|TKCiGZvn!m*YJ##$m2Yl%RtCBm?l2*O$-1Z#-^tR=#)mI%IDBJ^sBz^f&~ zu9gV8S|a3XiGZsm!mXAFwpt?8YKcIrCBm$h2(nrt#A=BEt0lrK&<;Z?fT`B0N!qZ?WNFB0NciZ?)m! zB0O1yFWGR72v4Egg#o+6hDV6-R1v<@hHFK5nh4)z!y`p_x(MHG!=prah6vwd!=pvG zPK58Z;V~jSQ=F>%Y zggb_`5c|M1;49@bfmjRD`#R z*Zh4OUM9lZMEC_8UM|AhMfe9cyi$aBi0}_>c$Ek@iSUayyjp~JittM|+$h4kMEFNG zyhenZ#d-dT4X+j9-6H(54X+d7JtF*y4X+pBy(0Wm8{Qzo`@{kJxead=;r$}~nhkFf z;R9l~e__L$MYu(5`E?uKBEkp7mVaf#TSd54Z28wVyiJ4;i7o%ehPR6_z6S~~uD`S4 z9U^>0gx|2?CJ{a=cKi1>yihLN|mNZVEHp5@xtH%y7vV5`FBJG~RKA?g%s78D_XE%y4&@;hr$Vy~Z$j zNbd6uU*Ocy$2ncn-_#X)Ak^}psVsY$^EFfZxVMk5@8cUw=yzP9k6eY%Ls#MR(W~(J z*j4y^!uSjxfKP@Q9tksiD$MZdFvFu^hRb1w$HEMKVTLEd3{Qp`zGw`38mmL5@u@KQ z=`h1r!wg>!nyUyHUVJ~y z@B$3)8u+}rLqD&65N7ycnBm1R!%Ja?9~pzc3L=9p8r{IX{FDFR<>kOdcqEu=UbzaN zpBkUi+tduj&%+F_T}7?G2!me_U@W-zgk1lx!th^T75rDpKc%rsRK_*BVr&9#Bc z;2Yf3GRn9NTBAHBV8ePjE^rC!!Gypitd>b(J(v=(!XwOde`<+O*g#DWYoIR7Fe}VZ zA2jzz7QvjrD|8Xe3w*)`W7INzcO+Y4WFS2d>2jR%QT5!pvn9OO({dVQ`ridTDFg-m8EEU+08Vg>_Mt4 zdyHn5Jx8<3UZHEt-lF>QaWuPp5zQ%YrMcx9npb{_=9fQ23(CJn4dp+hg%xGAsA3{5 zuGmORDqLDxaXT%mc$k(~JV`4nzDKJnUZd5OmDE@{h1OKAptY69XkFzEw7&9T+EDoo z+F1D#ZL0h&ZLXR~TdJ1Q)~aK)ttv;`s~(^oRhOx$>RYt4>X)=DGMbtr3ut#_JMD>_ zroEAiv@dcG?TJ%NWzL}0xf1Hk1KSRf=U!~*G3OW(3 zr<2iUIu&)viQY)3qxVxh`Xy?M{+JT63QET6$&Kxz_E?5GVwb2h_6Vh7&(WFK>vVQV zl!oXX%owvv>CcnFeuXz;Y?<%D3{^63tf_%`KThUgLjwp?hP+Hn)CkCtkfR{SK#qmP zh6n#f@Vz)zPy~55AAnYd8t#MsGBcg_w@8cx_3L#?4*qb(*N`HEBvb!@gaSrRIS%;A znUNQc1AfJ2|4%h=T zl6Y~z=L1ICFAmt+GSYdWVYkRg1ji}1_>5Fw9Po{Tu}Goedl(}@83%kyWTZ6XfX`fv zRAp%Ra>PhG$0BFvR$^rN-_FP%hlZb!7}@1G;0H8D?l}&~&|&11Lqoa^BmEx-qzEwb z(Q!cX4vb_ziu!x$#K9}Xht?TG68Hm#lJzwJ literal 0 HcmV?d00001 diff --git a/target/scala-2.12/classes/lsu/el2_lsu_bus_buffer.class b/target/scala-2.12/classes/lsu/el2_lsu_bus_buffer.class new file mode 100644 index 0000000000000000000000000000000000000000..48a5b9d504b465bb8a36f3e8952cd900cf169e4d GIT binary patch literal 491969 zcmb?^3w%{eb@!f=@8-tJZ3(wQ5_d*4kEEtJd0wwN|Zt+jnihzQ3;zzyF%GAG7zFQOmLpZ|@XV-Q4nOYi=%;!Qaf}>N5VDnaM3hEFr9& zQ@8TVxw-b%d|@TGRLIV?4&-LDQ}+jp)2nm2h*c)621jHhx44>L%B7d@7p6vX%ej?^ zRUxdzTz-nO2D^RtEQ%IZ?CTUZs7 z_g8Yu;^areqUqplwx{RuNLeVk7^{dzmP6_4bkB+Ey$!LLm=y7{hK5*KMR{FFB&vIQ zdci*yXMTSi{N2nSs@{2Eyh8Mf#EzcDrpa0nD?4y3+*=Wz7S)y2yG3}WDLtIrB$`6C z2aZL+zpL>VHU4uNKe^eHf2i>nHGU|h>94ls%Oc@$NW`nNX;oef}T@(0GL z9osa1^)`=xSkp7C_*}0}jbB~wm3v&{4{Q8qZ2dhbH@QRUZ>U7Mmo@&P#=mOw$ zXU`2y|DxivJ(IfpPEUSDmsfn2zpcyf^5hE|e^KKv+58pQv-p^jKd>40Kd14Nk9+)w z8h_E_M?yBvpeLIYu6!h{@fS6I+~%VlvdNHZXQWEwFKYZ6O;57S(_hE@@h)E88|NCI{XFw+KhNVr`FX{U z+J2t+i|pr_Z~J-0XFtz;+t0JS^5@LA{XENSeA~~nyz=KPZ~J+c*Z7*BU)213)b{f% z@A?0z?dMs)=g*^>pI_AceAM>yEU)}I+hhBA*01qxKhN@>KaXmDesNLb+kT$ql|N_w zwx4JH8ejACi<+O0+J2tpJ^vrI{XFaU{CU*&^I^;*i|pss{1w&w{G#UPqne*z)ckzZ z_Va|dMfURwZ&BOND?a;q=G%Ur<&{5YzUJo_H9sG<{XE<6`SYml=UKnvvmV>evwpQc zX1?v`SzhDYeqObMy>6!YH2Tnx>@mU|IhO5=M~@f|Eyo}xm?@-vpt@lk81vZ zk=NBMulfH)&HqO=|G&uVYL?gh|01uenQ!}lw#SJ~EHUGb;`TwZx|Jfep=h=SS|Fb-Xk`sOJ9{c|FheX#RhZ*YnKR{Qn}a=b5kh|3zNUGhg%ni%HMV zM{WPl?^Zzm1|HqzfN{bq`4o}Ch zUX5L6zo+;k8vmxZeik*}Iy~mYDKOr}h~lg99=oN>dwx4Mr}0NL{sQyKZ-^S@pIOg} zF0c5Et9u&1M)_yvKhXFi8vhr*NlU0v4w^HR^8ipCIpR6=Sk&e#gOuZDgQUhE(fFG+ zevMk7v-}o~KceyLnNJ%DQKKBR+DOD2b$P{SJ&!Y=9E7M*4w~(6X1)T@i08Ot`!#-z z=eT1nnw}AF;U2RCC9L0DpvSa8i5SuNTA)PKcnkEH9VlUYJjWe-Mz=>T&>85bbbGvo zd+e;nudy9>TEu6@&pmghFwuSU^yS8T1LNJZgLPZ>_oRDvmsMsvT5p8J6FWt+`dm+Y z{8Clta{4HfW8zP6U zbw|7JC>BGYpAU8GAl+Er8MUn$g z94spIos1dpL@~NwxMwmxxaU1Th*?|w^mfHmQSU7o)Jf?lhysAZX!IlZRq;p zQ<<*jE0vFR@4Xgoe4^M`n|dnNa3EGuRvxW7eF=7+CcE-Y&7sO;a_rEK&RclCpKk)% z_OA4`Ztp7grUqc=-tu@nIr-#x$L)z-jjKbA-7||L1G%aj?aPDV#<7D!7JH8l%oeWh zUYHnZiEQ3gTj;IYaRNiOy0+YM@1DQ& z@TtgV*gX-RUXzXOv&EVRXAWNLnmnCqiS+dL+=z77QXsYbP&nUn@M`L2KGkw>ZddAN z-wD}w=xW#WXxH&IdG*LjZ+v>JvMgNwOx5b%hNfN-xt6G|xY|B_a%6g}c%|!he_hM$ zAfEFN%kC9+cF*)b+_SAPk(?T@JJmFa5Yw)Bq#ps`v9kWAvH9_~)$z*@X675arq4g@ z-B#Jy9ot&DvtxLR3Jmuj6p{Ja%MXqY4z?|yteWni_8jPGN-hre%mQck=bP%w5|vYH zh4G`vH|XU{$0^^wgEzWvj>cPV&0k5SD1Q~~zT((jE0bl{yY8Nhw{#Y-bWYvb{^01r z!M5q~Lu6-%V`r|cpT_G`AHeWvf>6qU0E-1W`ZcTE-_ z?xB9U>-0+@+@GfLoITWhujP88ERrej$u>P*e(z{?GWl4zEOJLKHtpz~9>3f?M&sqV zs=@tDr_^{My^CWb56)~t{U18@zb30gRR5mqeZ~5&*w*TbB)5B0Lz4(oed;Q=w=bVO z+Ok_43h|W_{;Q zHHCJExqU@%sO-Rj*{Z8;ll?VY?hWj$NW|J3xLpu;7pJ;bGv``>yX0!`!&)kDlhYoD z!uPX<>uvWk=bG1AuD35=sC%#v^{d!j>EcrKUhllwf8)Uuo36GM&YwFzhIWNrTT?c^ z@=r0o2q(+u&pfycd{jK?%In=L!w>JQwd^`Z z_4V|o%V)6~&+uP-pC-z+Hx;eWK{kQ$_?D?wZPVSdgFMm2b z-#^rRPhRbw94CB~^)`9-jHj!vcCDVQX{oQg-d3nS&~zYY<8Sz~kmEItXN&dicY9M@ z?m4^MSR__m*4Vz1e^|Q>{$XZ9`3aRjujSuN_-$!;`u552@%^n=ley*H!|Ceto}by7 zY`jvulDt3qu-i=^Hm29kwl;L!?x*|%oL@|e&<;0$?Gvq6yB1-8eunK&C)2RsDL+2Y z2mezs>9yOU!g2Uiec?)SIaeq94n77Po!{<`uXK6G%AJRaNZYlx<@xaRwkr75*r=Tj zoMp?r^wAo^XQPMDBWnClF789S5e~`j3r4$9Z)Nv^TVA_wa>hORpTd>)BI?zzrB?^j zPoAOjA9wuESXt8XKU=OGoM>A{{#f4AU+?CJpM&3BKH1Zv#?!Dle+nQ-(dKQ?>* z+=Cg+&+{k4E88}sJ>#xlNQiRBFV?5-4sLJ3cy2FbM+VUUozGFfXytqM@56kBam?lJ z_1dpL3xAe+E?@T`d}s%)M-H#a>zx=cmyUS;CO+TK_`5m0uUV~EPVOEcd=Gm5CDsE! zfqAQWTjhk8wCO0e{yuKz`|xXJ@vD{PgJ2a^N9#d$#Vu<-wg@3%Q4h zzRK-gj{KN6Zu^z|#EF$BDzA4=k3F1PJJisAQ{fbTi~4)c8wcFq*E@@+Qx7`kueHr* z!p&>)M)KClqg2mBp55Hv#Z1?hzQXm?oL#@$6IX4&WA``4e^T{#*Mr%ihK_~4Ll4dr zt|xOR_pQtp>$@i}u;0yi_HzA#_V$OH>*wo_Pmb?vrhdyllKhqS<=lxa)P7T5`wbi0 zgZ0B68h=;4@pq8?Mt$ePM0}do0XN67UYW0_{-^dh?6pT)_2c3-dtHz}cj^}T`wV6A2RxSIEsU-SAUt@*Wk?3cQ@J~VG0Q}rRgR5yPknd?{c zYPXlp_2u+kT{9QH&X0i0pp*}XgF^&k6v)qjH%M{?B%4jh>B z{D7KQcs|}zPwO&@QYJ*NI?Y3N$Y43Yj?Q~CQYOteq-&q%R*M`!N*B=&3D6Ol;fsr!2;x5hSYJv}9o zq9R;TT|LxT5luXm5)GoatZZvP=F#^12O63VH0|CNo@_ccTz$Sg9ojly*4xu_IMKcP zKvP*+_-5tmo~&q@>Dzs5c$m_ww^lcW_MB-N>AlpO?mgU8eW3q|$;PURtp}TX(!CvJ zTN^qLHgrtZRv(D%pWIOv*}L4=D#}kMdiI3l{UQ;oD?5`IZ5w=SSM8Q;nbNZ=FYZ5^ z6Y*hjdGAo-Tq4VV%W9j-o;tUquJ&%r#isGH15I^LUfeT!@@S$$LeGJHcP{l`a`dpA zttTlSt4%fa!>-+XD#F!U)5EB5EP*)5?od3o_28vsRVZ@ca{1XqR~ti>d)2&ts%&R} zU*+}on~_jFo4t|5dU(gyY|rsYtYeSH`bD_!X!F|Ku!yL?)zzWO{+5nS6K%*>ePw>< zF_kZLwX=BsVOjm)&hFb-haNqUj^;95Sl>@1m-G8%U*XE`rm}-gYeOif7#`>=UfCUL zsD3bub;Z42tPAEyFF!*s%fTMegZReDaC6__M4~Lw5wCWicUFgLW3>P4TJ0Ta*_JND zdgkGdv#kx?GwF){Cfd&x&kgjoUKI&im(1a>zkI@LVd@=$)hr`p2q(4N=K8*e}(+CS_iG2 zucCPt_D0Gln|7zd&sIHs8Tgpq3cMVgY!B7$of|u}tDE-cPlS4UXA@)brpfWn`SH5O zzSe7r)T+!>V3o!)AWEqJi{GEswOUwd|nw?cG*&gVrTY zW_~E1#C}7y<2>!FuC{axs`iv=GrznxOZLYH&bD4{yRFubuovsYZ6a*sNA`*^?dR?O zlSzdKmA}21uE?r>pO|d!+;k(kdOn=@KZk7m+}LujWqW5`#nwwv9`D=lKgD|QUYKZ` znLs_1-Wu80I*#Ws>s9L%tnTo%MLxu$iB( z7+3w(e_8fb!S1r8sz>flcpCk1xT$QfSFeNIU)*k?_;4@ziF3*?t>nYaSFkU^IuGqB zq{0jB-%buS*H_*EJ`p!X|HHo6?4eAX@>6r{_muxA8#eRP6~GhXPPw6S#Lvi|$SiQO za`Iebw0PzC@+jhjd($zuUD*G$t@iGcO|VawQ|o#Muj4g`v9H1U*T$>+9EvZdRlOR| zwu%Z>kK)d5_?!MG2!H+OwEGK^QmUoqwwVTySkz4 z)K7=k2F9OWJzuwiagBC3sM=Ne3p|G!lwVc;tZt~WI<$?RIle&oD;bXzr#L?g+*B#t zPb3THYmVQe{5#n%PhP8QUMm8R>54@jhbQL71}6^B&^XAdaj?90h~qn|oE>gCr?wRc z$H(0MM_jt?HpV5j_pFM8G}8VBkiK%4!X+YN43x83)j1DU+7YDs(o5^b*^B4!1@?>E2~r<B%jIt-K?76X} z9&zKFqg`^?|6E?n^U_nd3KK_eO@tZWce)zu3xq$`%j1mo@_2-w3i``=%s)@Xa6VE| z9zIj|bl-4V)Q;D%AB4Z`yKn<>+SCKWpT6H#^ThBz*;K0U$nA8+ebq0B@2|CFI`2*( z&fhA4-|g6UTy4L(e4^!60dWV+r`1F5JS-9%cO`tFe!WLXp2v51oaMMZn#!;YA)NAl zS4hSu?<4mjj_b^4%%?aU_QxV&$5yr4!eGv zA^!yCGukiFdI9B$lqOH>qJ5kCg?@h0YX???QqSay(cRy>D!82)M}_j@iE z#(tpw_y3eluGO-=oIf|z97Ve`|7z!QU)_TWy6X95m z!vFRMPZY<22jzFGLyvJenxBzkkFs}1J@ywfh_7{2?y3%LWx3VSqZnW5Ft2lN96{U~ z>$g*C{9Hb?z3Ud{NBEbhO1Ikm;ruzdGJy7LJy(9_!bHQ(oXaow_&XIp$?Zydpf{Z5cC*(N@E3MFA`b2NU%S0j z+}f2JX1Sq@YCf>Xq4J*?cRUVxy-a?&O7*Mr?Dd~BK46Dku7i8E?&1F9acY-G>yU=( zP=nq7gkzeI?DkW*R`cBvZom9KnvbZSi*`K+aBhclC9K=B+%L|&c^B*TP!sEQ>{_@p z;`ZMewH`asf_a+zkIyxpAKQffckHp(F|Iw{x`yqcbr0qj#s{4PU>(Z+v7`Rr_4ZuR z>5n0tYi@79N8?A~vg-laeGBVd|FfIlnSX5g%PSqN*A8P|KIZgOyNM7S$Cqi}NAcmZOKM&%-Z^?0>y5U1xvDv&CyUD%k81tZ)pBKM7uM|#Kir_! z$rG37W;bD9;ON0RYEjvZb+}aHKxQW!X`PJmT;F{gxQ^~kt9AZN;d;kRZdc1TUPn9Y z1@uqP?m~Z0^ZrePA{IH?9NDz13n!_(&d|Uo{vACFB>t9fBIbFOiW>UXjZ>+;j; zoX|e6WWNG`>Dr0)VrU!ZyO+Z_B^+ne`6Ke*kk}WAD&I5u-7W|6d+KSOL+c*99L$$( z${+Ch$lp%cx)pBMaFeh7Tz)8?w*4Z_gHy{ra@hY&`zl)hYW2oB;rXs+?5m7?S|`qC zE>pQFr(HJ`D}<7!{S z>*(vr)xO;i!mZmob2wk$mR0S}`}b?%=FZA%+#h(Kp^5f6*e9uWh5TyS5&v_#BF#8N z9JV!G!S%qrrHvzJ{ppUQ)*aon&c-?-uH*yj-fdaN`_a}N?K9`MA0C@;z_|wPS5K*S zvDaC^tN$7L%4xla^{%7_9YW*yE9CSTzudh}4?tF&*2dArXy{7hI zM>xMbpM@8>zL+nISchtMoxwgZsm2l8btA zRQpMqclI#;DBqd+#!kCGSU=AXdng_jdW_|G-9>RU-sh~Gyus&Tv+xJ4w9grOa95pE zKHPC-u#xtG+-|gf!~SexqK@}Ds(sZtiB@i!%Wc8=?1e6@zf_!n^W(jQwL#1;j2D(0 zxZb$}f1&12+rDCENS!~@dSj8>vG(jB#S7HAq^Ra{yK=NYmOPGVf5iLV`mUMY8nr*t zo+%zj0X8UtBTPQ#F*|Z-~ z{R#hyctd#H@!vE)n#%fp^5hRy{hr|VU+$-UeEl)_1GFR7A+^jWy<2R(3UBF(*piyR z&f$Fs#6|3VXK1fa5ARPgPsADTv|o}<+-}MbG&%O`^OYzam#&;0pH%p_p?Lal42UPSv|4Yy~WQ|+^p>+7tCXr0D- z^mUqusPV*jr~SJB8SSIuvugc_xL?+rFY=>Uzi@l;e7q-|b^4RyHzU}W@-y&pa8M)| ze`t5i4|ad?y4t}3`;(@!os5Io+fuOp9s4&U&c^w9e~37nvfJK&!N0KIwbz?kdsT<3 zCu*Y!tUo9|%^m|IbrnsgalX(ym3Zt_L%5kqZgf&T%n)INyUm8du7 z5uT4Yu49*D$93# zo*&``?z*ad-E(<5_YgbOdn>{B7*zavY7OIk`}*m<+YX5;^}b!9v2$u1=gM^M(o63% zQoI}QjqDYb{&e0q-W}S0c;)~BMyh2HOT%e&I` zJe_;cdmf&gvwvzb^C@0O@6~AUSx`LEe!tLrPlMjyf?r4m+E2~jSGw_DD&ipNK>c_g zM|?6le}Vk6>YwvtRXe+8`t~(mvE%Xg=5}^38^Sx(L^^+EH6VSsWjP-u+Dt5MRRkuP%JbjBi3PDN3l$oOte0`l$*}YG^dxAififR z43=yi(lem5 za!WJWDZ1MtlrN$S-F!W()Yx?A#i`TJUOX!-(J!pHqB8>*`cg=^*gtrB1T|KFGlS_X z5MY`G%I=XVRraMC7grbNave|@&O>pgmr@)f3CNVPmd&qFO2yRtH2n=P<(3ze=yb7= z%PeGS`--(s0uVcnK?ZB9_u>Fi2YNpGenrA1x-LJE}bx#^j; z=}g}LNU2_SO58-*mF!A())UWRAT25VHFTxS5@58H%T8w$Ux%Ku3TSbq$S|~_^Q=(d zWaFY&vvVlRMu{pK1Ch*7X!Td6He0x#@vv&QmRp*Qv1)&5O1swx>M^1USYAPwt4^6- z%ECDUX?N$QmHAHBs5VfB(m3#*reU^vLg8re?0jx|O+8o9bD=n&Tbj*z0wfN!Qxhuz zdUjeE=0Zb$I+ufQoLccRtrnJXTaJ3>;q;uMRaLklNuRfT@TCu;|Mt*u z2Xs&yL0F*$vv1~pakVg;gPVw{)?}9vSG3(H{BSormq+{3;Nj+^s_TQt&!sXFN{cg2 zlt*GrMG4SM)=`H~6|_Rqq z4=|aMbq;6X@@zCfLgtqr+HM>*sH)V1!XN{X1(yh)n^oFOacK&M z5K2+5VtI&hw5{ZUI#gOEGXQCX>(7*(m8)S89b0;KWhtp_Q)C;F+~f{CxilTHZ2Pi} zMpc?SIJhd@%#2)>&iy1^nnA7}mDTE*OS1D8S5bL3oibbiE&tZY4q*muK>N9IgG)=<62n$XQW0=`4v$9CswWW;R%*rX)10AcG-udZ; zm8CX&eCwUFS!LuNM0VSS(Uui zxqxh{u(FgX-o?^ruDFH^%4o1Eyv%1;rfw-aF=*91g;7kVT-g$#d4M1ki6&1=+odin|F(hOWv-#?owLx67Jm zJa?j#uCi3AEDFn<2NS_^W=%1;#?^iam1~pYIX;By$$GezHIb!hnw7cJF++HhG!Ugf zX4JrEC7eew97L)`8n>^fQ56$YmQd4R(p0pYT}!9-hlf(>UI#fG9^2fuEW;eVQK>;# zf;)?zIh~Exd<%DqYC&olg7k5nu;1r(^Plc z?#GZ-CDVRky);@>)ce#bpHZBdQFYqnOCkqS>*F|+NVShks0*r9maO8I#aUo;CyD3h z7nX8UxPp;a!0^Geyint>@>Kd_Ix~2BFf-6UbQ*1~@AD1=5?6eT;{)DS{lesJEE~K3 zXB!W5p#*7n_#u+WYN!btj~-whhdAS3Y8&Zzm%gWbIA=da`yhWGn5>z9YFc zpjAZzAeZPldohzfb!sGYwqJi5xPbCh+Q>+HJY#R7tBBKg7Q*S#vl-x6Tm^(3=4k&_ zG-Q+>nN0Lt?9r7wPpq7tbmf&K-E%SBmpOA`;1sIhKC`wh^h`;qO#jfS(^r%cwwPih zRUK3|`PJJ6e0n7dV3(fU8P5E7Pcqob;A;1|R>10SthA`914!fQA1U`>hK z5d#k)ni9DV3_#t+(?jW=fzzM)odJx?>H zUI*d@+mm>~_9R}gJ&6}=PvQmJlX$`QBp&RmI@Q}dnCVFmozL|2UmV5szzjuiVtV}I z>C9OFDGF6FN7-+4Si$MuUPmOMGI7@cX6osTo`ZGpIN>r`$IvA<1V*rqk<)$s7ls^@ zM$@N8Tv`ohR;28(jjud4n9lTEI^#HnI6seO`Y~vw^FXMlGL-CS2E!Vz?M!;~A_nip z(<397p1qhEIen^sV8Qv*K~{>P72a5Vu9qZC(YPE~~K<{hekrSufR5 z+MI!*%qU!~W2EXu7>btKWJ?eW)uVp3ITwZoP+KRkG8z_*QO=fTFa^QiD#-9H38`+a!{ zkNi$hj{HuL*KXjE-wDc*-wE=_?*w_|$910P$4j~7$4j~7$4j}e)4+wL1}^#WQVrzC zOS$C7buRf%^5a2XusumG*q+1-wkPp|?Mb{~dlE0$p2Q>j1}>yeWiDRGTpB%{d3NB^ zC~S!gj9yB?%V9A9%EOKGVB^MlRJf_4C&K7Z4{1bL#LsZOJh4ZyDB_7iJzdm1Z}rfH z4C9^tk^_Ym&-V9bQoZB719+&Uhn_U7r6nHLX6jjKQ%P{enXwBar{FbIK4)ksId%_9 z?&5`u=>c-w=s8m1K0B>YHF6q@zKa;~_EITEX4_*ZVbk0car=o|!ai_0-3R@rF%8ww z<>h={*35s<#s~LnYi)I!*?mCcIQN~iJQlTE_Up;^a(%P-Ih+LYzHn)^K*65Y(Uqmu zDO`@8o$Jlc&5dF&9uYr}`ERmV#L2)?c0pLL(aYZ8JWt;aKrI3+I>(ps;{Ao(#)-Q5 zc2>v0ZYh3Id@L@0L415uSo{(Wo3aZFbBGKzqtY)_J7oTZ_>~&V5}(BB>P)^cEybtB zM@ZYR3TsCoJDu!}tQIb!rJ5t+*MRlG3#Tp(oNlHwk_}{0%CC#xh>6dN-vq8`AI8zA zsQ4V_1Dt{(c#nfSYKCRiS=Y4Aa$rfKk7tQ8YxW9$t-12f>1+|ar`U6=v)cObF594TsKN40M zT0mHRx+1QqR`dUk=06dCO0Dx%tPs$aw~Euf*{NGO43*u%jwwMn#z%znKz#f9<&(P$ zv^=ubdn~`b5%D*s(F@Nk2?2a9f2b_OC#o3%aA)Aa0QF!ppiy3_Ojz}9%6 zM6c&b)KDV2*IR->!Hs|d4+-r?B(w*RK+lfJMkKTckU-B)1|t&M14y7}Cxa0Q?Exgv zvy;Jyg!TXu=-J6&L_&K23H0n_Fe2e_015PLXCSh)Uk(S5K+jGFBN7gydv&bQvy;Kt z^M}!$RnBydX&mP((a^(y60i43++b#)_YZr$PoyCOx>&ixsp9-RUQz<$ULGjZ!^2@C z9u5caK+jH1jd(a5zym!y8H{*1j83na#>+P=bE_FXC%=W)W1^wg22AyELRk#84dCRk zhZ7=8GaL!vgr03vi8N#g;N*yh6Cw>60ysJ1;e<#-26Vg*tRo&Kh%{sfVB&~}2_g*{ z(9OOQJOmsuBH%~>0rc#&k`Vz%0tldICxa0IN6?)7!mx6KTj0=;@7!mx6KTj0 z=;@uDkl83H}s;q^3;r5QQ{Jx$McPZMd#fbNVTf>g-h zd^#5m{hPl^onFTiX~-Yw_)f3mi8N#gbbP1R@kAOj1UkOc>v$p!8PK~;&YbG)Tr&&B zfxi)h>uQyV6!vec^Q*gjFu$=YCP0X27`G4)O32NA<~cm(1^^; ztuEif8m6o^P@D&$P9uam2|{?sZ)SCFPQ7nBA1$j7=E&<7~trCRT8c>Lr5A*Hh20X-i0jv2vsEC4=wb_zCv?-&qPqrDqUUkJr( zH_@^u10{Q)q%4LS0C^>fZsnt8tpPct! zfW@B&3^xyGQy$>Op9c`@>!Kt^hBcf-M43u=Lgs|B=43vlEw84NcMXj2|Q$)5)d zHxFo29>B(*2Mjll8BWC$45CeWg2+f}$ROI3 zCy0!sh76)jd4kADYRDkklm}hyZvzbnNiz6e#tVqrrj_P354g{dqJTP~g;* zCx`oZsDA80-5C;@Mb;~j1fI_DJax@%JqN$u94k(Q3mSe^N1y23t zXgHumLpc;M_2nUkQx4IlJV6{#Jk`x(#sNi8{pDylphQzSK^#!n)Gf!10}7P-%h7N^ ziKcRbIG|9eTaFnA6esnUqv3!OP2~h}K(SM|95W6m6zVTW!vQ6l$_e6t!lQ0EW*ksJ z)K?BMoIFGu%AuI3KaYk3N;KsO;(+3$ZaHQgP-N6!j)ntDG?f#?0YyvQa?CiO_^7`e z4F{BHDkq2o3ZJ^=m~lV>Q-3)c4k*!7P7ntaId#i1*X^O&(h;Z=V*8dfOLR1VMLjhTn zmLPg44(nQLMh`_^{nl#ep+r+TLG(~G)-A`39*V#E%h8ZQiKcRb$e@_4TaFnS6ovJd zqalM54dqZE)|ZDEPB}!I@&u7V(O5T+85tCR^_Qa|gAz^UpsW3PG#pTT)|4lR0}9K! zwwZB25mtXW8V)GYR89~F6km1AG2?(Ds{V2`98jXEoFEP;u98h4?&11#^MMbwcacjipW^zmF$FlT;?`S!Gee5?v0}16c837yw z6{_&EQivY|`W0#jqF|~?AwZ(NdN&;{UkobIAVq;xlM{#c=Z& z!Ix@tz~}$jEPhFf6NK_N1QmMVQ#nl)0h|?TuzyX~c> zs>nZVjh4SFsM7;&s?7-6R9gVFis1sm4BB8|H>Cx36>YFR7}!k_!zsrc*iBLF*4Ld{ zU{@uY$^q=wYkB3GqU9e6YSoZx4*jMmy6d+@1EV?go1*A$ow>K7<@n8lU!Mk4b67Y< zkze&LSN2{WH-gYr7}4@i1@&myG>3{)DpX8%k)Euh=(9mZ8XV1`;uJ-L{gu$*W)2mn zC>rd~1BMF&Gu$W|tbQP`3|_Kp{>6YIEqL#%pdt;Jl*0hBU{EW&c^QYz>O$$a0DT$-WlUBFie#WG~R=ReZ@V{A)o)8V1eb<`hMj z{e^3IqeN5TK$2T=r|f?T>e1k44ne0V;_T_MQSk3UJsJclgUKF(po9NOZi@;ls7HgP zIaHlep=wtT+fz{y(4&Q~RR)7S6s=A;dY1Cj(TaFbiH1m$HYouBT_uyG1iw)5^%MoQ z9f+C(+$oA-S2~tV(oJa5iY-Ak8bZx6?-Yf&{Y7iek`hh!1AA`KOEjZJD;k4pG<=%F z;3%R zq7_tGpCS#Rl*3Rl3Z|=fc${fx7MCeTE1nK&(qL+izo#hN?qVgoHivhbD|&)zG?T8IV{|V~v|>1@ zN5iu@oS&lTy}t??dMVLVHagU;!Ww?{IT@`O5313?YmV@zD4_4D;Zcm=8u+czuuJj= zYbdVoslmm)=oef!LqTksg*N$MNo}~T#`2#1SD!Tvz@`K zf{HZknhz>cbQa-aH@l>q!RrHRw6hB(Z?K1sDzqMBXYjp2J(}003?@AQsIQml48s`% z=JSjc9bfqKXh@|*Q#kcTFi^_@Yj8jLBs z$yk8WUqKDA=0lMbooV>>jT=9 z2e9y$qhW>)PE2_K5fzJYdSD)x)$$dw(TXnx^=WuAAEcy$2Pul-*lj*YNzu89&u;A? zMI{>S4j!bWh~bt4+LQ+{Q1|3Hb>)Ct#a{%A*PvrQUrEt%ir-`nI+SQCJ_sE;Q*liO zZOQ|5_y!1K-*A}!7%W`_6rI4BGz9@gCoOL2WLS06e|acnamtfc68gnzP_$}FjK*>G?dP9m-r(58}u zc%cImH;)-FbPVFRR>O<=j3h+|9sWETGR&tSDLVA<=h2WsiRDYV1)Lx~w!hzhIp_iZ zBW~)O#D7^_xcZYadsKr6@DyXMZ@^mMET0C{4!2^2C#l>&CR9M`H^?* zgPS%YbT?&h8oQ~@?#(XhK2y4!@@jzfjlG`IE*bUP>93!2!;Ec*3_lUxPZh#ue=}8L za%GZk*Ua3?F5kk76#Ma3Rj@U$>#EqrGvA;H@H=vy|rXl8F=u06vF>h(g0y9hc0q0g9^LrZs;@Zpr4 zZQ?RM7g z7qCu-$HG^r2gc!lmhR4Hm+#;kFzOa=VRdZ?6}M-Voh862CtdI&)PrbMdZLcN4Y7J5 zFc?=3=?1%M)n^9Qc`_9#!#BfOstOz+Iw?0bh2PUp;m3Qx?leINE#)!Mr!(CDbj>)Y z;E-I2pMA7?8w?D1A7Op-H%OI-5ksl#G?M$Bh7dJ;nCec=5Lu=l`{m$s>;~a#qbDx? z4|>92PM{HFxENlbepyt#?{z_jwv{wi-JSvm{j$RSvg(SnflB-lA*rk?fuvoQtL}dY zK9h18z8`*$D)~Gbc>c~vPF);bhdI!3wrRR0S@Gc#qP7SuNO}kv$t|wtaj};tY0NIe zFAjfG!U~69B1N6p7PCU(mjdJa5A;jXU_C?6FGms1z0CNDBFxZ+n08~c6x+oP%J53e zOiqU8x##ZVZit1|l^lIu2#PPu@OOm2GY+{|DaCw=vq>?hG~<4?MzNC=zfLK(*}7sG zegmugE?|?dg2wv>C6@9n&{FIYkCD1J((ml}BT;^3-^a?nUs(H4)n=L&=`USMj#nfz z&Fb1y=PvC`a}Hpv-tW6VyZgXpVO{g{zJZGt(%xh=?V^3vHd|G`zaQ-_9_NmHn-on< zy|^RZQar)bd!^XV)cd74z|>Dk@g(Q{fD}(L z?}JjbFz>@s9Aw@{q&URXN2O?G>KCMFW9nm4B$@gpDN;;*LW*{#J}Jdv*7s>CjxhBZ zDULGrSt&YL?l)9z&PmZJj!|tsCq)-ipO>PWsV_)zoT)EL@ibFkmf{3cUyZ?-pGWF+DoMP%Pr8v#hUrTX@slSz?kEy?t;w)4DN8;;T%D#V; zxC>iR|18CMrv6om0jB=16oX9tyA(rA{ihTcnEJXD&nhY+q!?E9kCaIJ6qfAAl zxX4sYic3r-q`0hXiBw84#=K2ZTw$tOigBiDrMSw}Rw=GAwM~laOf^U`!PE{ZZZNe| ziVSOhOp2S#Ymy?%)E<1rl&QT^OfmI@6w^!{kRr#_Q&P+@bx?{~rdp-A#Z*#?JX7sb z+-B;C6nB{FkYbLhV^YjB1s76atDcsk$ka(G7C1F6#UfL^QYcgdo0sBS86`z2zKwZ{QoMqxWhq|C z)T$KU&eWO|-@!TVOYxmdJuk(pn0k>EuV(7SQoM$#mq_tird}$=>zI0(6t8FMTcvmd zYkq|k-^J9oOYz-IeWw)P!_=##_+F-7E5#d`dc72HV(Po3_&%n-M~d%f&2NaTH;@wPrNQxil{`grb-ow0~lj0|s`gtkd%hWGQ z@jj+LF2(zq`eiA8lBr*j;-{GUloUVB)UQhM0j7RUil1TX*QNL%Q@<(2hnV`D6dz{l z^SCRMCJc2QsW+3UPag2+5O~JeP-x%+3#nPrq-n(ccmfOVU8hLzn+nc6b(N;HJsXJA z^}H5-sUx&uO-U$N(`J)V5OhEAz_xEF=2hUSb+iRP2eGkIbx}Bd zCE}69oGPzpqS8j+lz0Sf^r?wQ5Th?pJd&8B&Diy5Wv}Ioi1U5Mf(uluryzt`4qvxm znI}xW;K*e7qZb=V`oD$2lKTxh)pAn5R-Hx5_n)Id@hCZxkFGrR=%Ve9E^4>fqu6@n z(X}3ZbkPnLeewmG_cVXqGu< zDY8d*=d*}uk`8=(0%KXIRWMZ8_hZ=|9CXrd5<9L*FD| zDPt#jU$0@ILk5_w^HCelV5)}weU_B^)(wl9I^Py^KY_!NCd}!Q&I00vC1_ z-eB`os(FLWQ>pL26qv4F{?(Fe)+BVR0Ia%qmt#xBi~ zqA62N5GKD*Lge=Ot7$A}TIU7iv=yvr3Lt6w8*8l6G&dC@qQg?UrmdRBX%h*SM(a!ZCU$+2ao&i8*{ zj^#`_Bp!sTf+NF-TF59KVHXjDebL1-4)1lDNTdsYk6bCmqFb%K)b;`IQ0vMqNHy40(O&f5>h*F>B| z^)`>NLiBb@h02a^#W{(tg{SV5jZY zUz;1rPu)WEAvb>RQXlx@nUkm#e0wbV$|&xLsAL7tF6E|kGsuTGEjHQtY@QN-O)UEA z=xcGs1S&g*&;KpZJ8SgLK);N>KKh0@Qt?7XEi1!&T(?>m&{Fv3I#hlSRm6~@6u&VR z{od%C!p~UzKfDy>GzRruB>IEsT71!NEI+++OGbYv{IYoT%~4#wP_|H9L$~ceb?U$= z8GT#yhvU%mcD&d_A26J2rW>jX%lI)N-hJG+zrWvkIcTalH-}G@BcU}vKfk(?#dqvl zN9e`6ZW(I9nD$X5;3z{Xm%jjoNUfcXBTk0 zIlYDF_Mricrc$`2?AQ2Y^v9#`!5c8qpV$uIhQ^H0KLX>16GwAP z`RrW&IjV3Z`T=P2zE@{|NO2%LKRKNp%&lZG`0zdW`;q7e@p>Me(^>W<=-{%|8 z;vK%Z+;a0kv3O^7LI05BqkQ*K|1hDU$xFWW82xbcXXDWiML&X;!3Qi`H*9F9|Ie%z zRPQGNzE4DdzQz*KUqE+r8yUgTPktpgJ(^ntls|?;78}YhB&^W=OR?z3qrXg`&K7!B z^K;W@mWuPjIsji*QY2m&MITMI_G+R4<*!6P8HbWj3Fi}?#)1`uBhg>Qz?i3xa}GFW zdKG@e5)Cky(O-*xHXi*<^w;t3Rf*mG@Yal~-&F4>uPcC0lR9Jj6yDBMJ@C0W{Mc_} z*e(lcw(i&%~T3T1x##(7zV|%tr>pJtcNo#_64br;7ydBcY zFokbKtlJiDi8opHacNC5wOd+KOf^eunyG!#$}zQHS~E;NDXm$iTBLQ0sYCvbR)t6_ zZ{4O!C8c$TjRk_{n0G{4^PIIqS_Mu$Caog#&>#ye_q4PYnK~)0C6-G|YnkPGrM1G; zX=$x;YM-?3GOu4+YfPP&);&%gl-7NwE=cP+riP{UJX536dcZj@N$W+-84Gx0BOBn#u(s~(FGtzoFmwQWE-^yj&me#j% zyUa=J6-*VR^-87|r1kAgElKM;ILC^#zLT}wmDa16cTZZcX1V92^%~|qkk)INdMK^e zG4)N-dOcI$EUh;%^)1r+E~Z{Ct?y>)+obh9tnZc5`d;RJhqT_vyjMx!kJlOua!`Kfu&?OX~-j`d(?hnYFx0T0g|R@0ZqFnEF9!y_HjcNLp`W>aEiHVWxgq zT5o6SN2K*5OubWD?_lc3r1egw-Yu;kW$HcB`Z1>7E3J1i^?qr+o2j3Y){isw0cpL5 zsSir)Cz$%MwBF0qN2K*WramgI_cQei()vlJJ|?Z7V(OQq_0vp!LRueS>XXv?8Kyoh ztq*cUX5|QI`8%Y5hD?Uy{}@aO&?# z>lc~&eQAA+sXvs~$GNmWmewyZ^{3MMWv2d2TAyIKzmV3iF!fi``Xp0-Bdt#{^)+dI znyJ5+)~_=457PP!Q~xBbUt{WDr1e>*{!LoH&eZ>t)^D(-{~@j4%|Uoo#uT7S({N?L!z)M07;EmKFO^);qCrS*4AbxG^*Rjb91 zOY8rzz7x{=2TpxPTK~wr9%=m(^G-?YpP4!%t$$(athD}>Dg1(I?9rz)eHjv%-2AJl z6W!$D{!RI{IDGN{V+y|b-??1);{V`!z!(1~^WcmBiz)cxuX8G1nzfjBO=2TN3yS!J z6d|VY(rg)1cxkqrbKs@f3Z`;WgqfO^BEl42nvF7rmu6#Z6<(T+GY>D#CRiU{nw8v= zcxkqhDZDgW#i@8{b`w*0X?8PH&r4Cw)QhC3;T(8rww5WpG`odU@zU&8rd~$BBk-0o z`~wdeeo^=#7I*P)^M^}D@B^czX*BB7(N#+RcKr0=c)pNdIYCph{u>Sa7(vFrGybZ$ zm5RR_`+09UdGXd#aZN4rgWqNZg z{)6!!64qXXE=nY3usK7};bL(hPkWj%KXAyek#8* zcVEWe6MYwAD)FCqq>}nkXe9nVtmqu8PTylyz4$#%elB-mfg&Eu&5`&|;@2QW`kH&uCH3EIM3=zH7{=(hjRF-glF}s9_;pux* zIR*Pj{ELWUIVN-HI1>Ld#}ySw(M|xjr_w?0SK_}PkN;l$52W~6@ey*Ie*|yiiE;Bs z;(vls!qF-9qvW7K_X`BJ>|T`dug3o@F8((D=eA|p)#V)jG|kiKdSQ&Kzl{G?JpQHl zU+ZCv{K|49{wC zuc=;4U@ahkyMtPfzaWUPb+1@l&CVg8zz9$@{;mt{Tlwas6#vKt#-#W+rVuRl51=0|c|Ja(+B3aE(|xC+3txHKZHXT2%ze?3BZU?dJD zS~004ur;`*hC>2vq{iiBc1b1?dltUZfD^vU&SQEeJkmO zxCTH2s)?b9e=+CnZcEJ@L(?LuJ+IWZR^1w z|0VHOnmVx2t-|E6TF5Tl&oocsU|c5NPP59F6WH|z>VV-|ey^GC`KLc6Gc?^nzRew* zw5mxR@mlTO+-g6LCVEee6`@vpC%4-Bz*PVM=CO(t+HR?~qgTI|i|BYZ%(WT-34y7BwYaA!0 z=H4^;xj9VAzm1E{T%)`MH7oy4Eb;lo7cl6Ep}J|_2>=i6u^T19Kni& zLHCCxk`M{x#ps|+HssKYf%KA999_vxIRF{@16%}hl&tCK(rk#*Duw=(G!I>d?bkuK zT9YWFjqc_Tq$44~;WnV5K^al2Kzd2d>0)RS<(ktq_<fRZQb>}Bs=tLPMAcuf5G@f^|8Az@ z6xP5V@yGbFQdrM<@K)ox-S9gSkN8I6hUuFF!5 zMN2K*4^~`Vq4ruo(bi-CK{wa?^{7U-wXBz9XJ&BFZT5k#Mvv}a*VP1;EU2*4w`#y>u0E zL_X>4EU25MY{9%CpOOcCH+uPd+5e=_;Z=isP<%o{&Epasg!^20yNtgq73Z)RM$vyxef$VsSSc`2t+WjQ5tGPH;D%~C-CH5UXTL|?PvrxK7KX_KLSoR8ki zT*ixNIVl%d=OX1rA97w0HGy`2j@tYkjDWkrHaUW{ALX?BC2434_ap&hWe9H&Vx-_j zPwynbVXGnXFeYClUyP$)R`?QO&3S&#k8A(aH^{SLT)Z?66Y!d-zvt=NcyDwR$>Fap zW!AEJ<-j%!TJTcdc~!{z5LfLLIA>NTY|=q8T2?#oR6L#_>42 zqW9q7n0fErAg5hVvMEGv?5&{P6^zK^w|Kv4RmEVrI(mOcY#v^TST}CWaNG$zyuPwC>t<@ z3(vhegEChbrbWf0%;_BAvp&Lo_**5V;T5S*a@yzd5(QIVD3QX;0Dr(~c-JvtFJ7(s z5~qD7nAVAi;#WAWWUbx_jD3~Ua1i3x*$KDs=Zua&D@nsn_w$_gm-?iv+6Gg3lEC`~ z7Wf-XJbs8fv!wOgT=d_SsK+Mpvz+!1C24rG?AJN%pYMNxI9Ssb8A>s)PKG*|swaIw zJL>}xq79LHA|gclB7Q1?JY6g9^;7Ts^s_5VZKrZm)LQ?cW{^s(DbI1)SW|wSdHZOi zis*tdE00^cvJ<0_oMcccX&3OHtQM=yO&3S3{cl z@e2&v=|Qqgok*3l!FUz2pAE*Vkl)8Z?3bY~h5%lLd?WJ)W$0<QO$UZzF~ z4p7Z-01=`sFh79^(Jq&tK!j+s%TK;u)T~4vG>`4$$(0-H0{%|d8ECn^h+Jh>#c?Vp zH-#&wYODm}IF%DBj#D`U)@+R>OXE0nD|?_d0SL5ON{TqQ8Unuo31EdRM%C#L><^@) zrrvO*#n7>%ZnUX#nXO!bNvkzhC0SWyEAN4Izs9OESP7)Srgj=KAUC@Wp$-k{!?9!t zj~4nQMZg}PdrB%;Mn47XeZ=dJpXPdh0G0fi8mpG-{XVYuhr#;U8f%NG-Y5fEW5U2mL`e1T933gBEsr7JiZ~{1nXjbd9x@Ec_+5@YlflY>icCu#h&bu&@*c zcF>l-=0Vl~H34gA^Bb@x>HgG8R(^r4`CSzK#TsiHS@Suz=J&w*N{v--vc^yh4Q;RvA@a#T&m&{kaT{FoOOP??f{X?`DK3vZN3~L{Jfy3g612e=kFqIQu`y z&=scsNronv`WI4!c4I{#LKLgzClDd}=psKEs)O0-y4PHF28PbUa`AmiYZcya3*@##sPvf-%3X?lIs$z^=f=+&en3q&Rn;<-W9w?ky8qAI zdjLpLv;X7SdULzEyVy(y)Oehtm9$@lsb{z`lq% z0~QIg4`WP0q~KgR*T}zOa`JnoHN6=a#7xu|ykA_374>0~l6KC2DpGyiv3r0u3C)cC zuzHF@nT5kp16u3Phrs;vXz&V@&6cNW!x(K3OC-VRm^X+9uf^C98oVB3L&0G(InBvu zO1lX!P1qvFR#(xlG9Q+q>&RASEXO8}@-NEGAD%w~rb=NVsP7myOOfJ0hbwaVqw+_` zpyU`DoP$&@repv%V?1og!PrFDa)YtSutrB4!nOnK$xE5;z?iWYAQEJA4w!;SkWDmT z3L-%^yMQTXO>6-HQyOD|dDXedX9f)}#MmqvybWV8Llk7c1Bq~m1limHrXUhzlK?!$ zBB{OAk_PWYF$-YB09wN>;7X6N+rX6`+ja-I(qn89>;=OZtd@R?v3ub3UG5u@zXUqP z?V0HIfC9Dm9m97OgO~3S`Afm~DgS<$nmrTx+vVvhC+mg|A2)8o$VLK@|6u+@F;X{w z8MG$pNaNaosz+7MY>OUVp8p8A6X!n)p7+?q$H5yP8}TG~=wsefu;mJScohxajp|uV zgZE-=Eo{TWtLtDJ7RENv;8MK05w>Ar-ewwn5c9UchAhn6N`nt$9=K@?$J$}eF)paF!nL?N|tvWSE@{9^#A3Pv9KB*>~=A5J!&MD{(D>vn%#!k3|xk?>KILPi>a7L`4PeH!`=}>t?i#8?Q?Qj!A zGL?xb?qDf6D^}2@;A}fOhvuIX-wt<)Zl(~$B*T8X7UV6 zav#Tzl^9jth`B5s-{_R2(^g|41DY_PV4y>46bu4`X1`x{V#anztjlANzcDD?3lfJE zl(SaAd)9T>gkjKx;SMP)7)0~uV;1v&KRexRKR@tbzi}f+>aqm|{4X zWgUW9FvU;+Qw)c&tooRBIb>bokV9D;O0kQR&F(M;jzBmAb`0edOoex@GkSLG%a)Kc z6awzk3$D&Bm{tIbQ_`UXjCUAcCvGMw> z2j>948*S^yD!J7)2ASIm<~gKx!Oe;%C#RCMCU>8td!>PZ1u-DCkOp@msat75BP0b= z5Ct#=aah64H24Nyyo(kz#fyvK;yn&IoL$_77w@A5E%4&~aPa|$)L|F*;KgOM;P}|v ztgXx8;v;r$V~5mb*Z1M|Cul)yyuJdiKjn}k*v0qoVg)T|hZont#kCGOl3n}|FRrHr zC*ehKZYluhrlXiTf^6{!hhFx$VZSYlDfYNw)0CKEj~g~C$5Sj4WRr84f=H0fe_;wD zK{gGBDToBwTok6#pBd~O5MIwUBPu*hK0)Gd(Sp~J_}f5yw?mHR#M#^yiiJqZkjq|H zBH;4FX2W=x{+QqkNH8G^B~rmnY4CHb`XgHKK6ce7Q1zz{IR>jvKCal$x2B?jO&H|D z*US|-u78tW20q=s!WzD(1z%y~euNr+a!5U_A=xXMxia=L#Tx~x<{>CKl?3!2BLRyq zS0agj(#ybm7jB2J2`%`GldyvYQ9I<2`bZ*a4D8oqQ)_@OBMApc6gs2Nun!C&8x2xUI2BD!K)Y-Wt6PZdv;nI7$F3sSm^k zGnW{3lO~Qh)NW`W%gQ&R!QZf6u+MIlj|=rZmVYtJp;8Q5$)`TQnEF`}*k(6_&6zgz zO^{9LA@%fofZhAdOyJdK67p`9-aPmu`x{BNrS|ctoc5rc6CH9aDkpjGvuV3j<-m*Q ze~9kF$Rq~_&D0*B^anEVDm5L=1>R0l#hpMyK@@iywNF8FIUUIKc1R;6lN@Z=++7Nq z4O!e=z?^vqrd7Fa&ejn|PaHLg?NA$i30suScuklc8#|aBHl4{gFOD4voA_V@6tyql zZjE;TbPi47dw}gZOyvfe;j)sl({E}vj;5mEuHz`U#KZKvP%}iaF@={Fw+&lKOck7d z$Fuv-wQW$f$`mu?Nl}SVHd|0ksf683F6Rwy^_8aVlEEeuQ?a5i*;*uP3!4u-O3n?z zyIg-bk!ujU17VNhK=|1~=BxnQD~Ir&O%;}IxXeIZ&fj`@xO?${#n?_T#nap^Z3uTh z6ODjMT@LAK#e{9JMK#{$^xi(cISobd27wo^Ae*_yn_p8D?)uO1Mw^wc-j*~JLpe7v zIbbO$2O>u+YKAS#||DJY#?ybds=$5rPRnO^$c07Fl{Dmy$r9%)5V;ZW3V!+`&$mWrGQ5LCLITEMN zA+YV*_Jc7JwjTlj9QOt;Rf-X7eo3((wI8;Z!_Ow#kHC~4oFxheq9eaFD;UHOIV2*MI|JCew6P3;%# z7i0GG_DdFl&+gd7(McFADr>gDz%hpQtM(3t*a<(>g=}88$VnFI0H;@BdY45yLXAmP z@o%<~V=ipkv3xi<$=iEiaY{a@)r;)A#@?H2zhm!%uMs#d5n}IJq?7CGhyyyqBM2mY z;Ql(QyuhV=lxu%ze+t!TwEYB91xKA}|RQ?B9$g3NXjE2<%D>_HRxTg_u)hkyBYt3z{g!oP#U^uVBIc zEoq`A=G3xC50-NrO&p3jwJicmInoXMO!yVqx;cqDFfS!<1fIuwE^$O|qHf|yxPj!g zOV8(8u1nl3bnE=CgZNvH>*My@oRMjj7YHDtg(=5^(P6A;1>jn=R7+hS-5-hh< z`OtwAM>4G>j!&Eb>lX=le=kaoPVN#pi8irBTY8N}`q0o}{JEDn(IS0m2pz2x9W8Q( z^2U>XPD66hpF8tscnqcAFqKao{z69+T@ok5Qzy~2AesQ1^xj6vA$9`nlKtwvej8S*@!A5Fwo&}q9$pti? zh&Ev4VJ0zgz8!6#+y0344{%7+#6WnROB>O;xlR*J42H*a`k?13!ta~%+{BQ?&{$%K z^#ZI|uroM|(!|2%(453Y0djV7o26@dl?gbSM-aw5AhnZ}R8+~**7t3ys=xl=4yf`EkvSWY09)A-R?0=#e% z;DytHmAJx!*&uQijUR*8-h^v!Iiw@IHq|22EHa&j(El_6TlZAAwInSZq9={F<~}-!k01+<7VR7d8pq-o1#c}Xji#ZhWPRt5lbN@V>+@_#|CC+xE@3~Su%7_=vqQSF+y810usU}9j^IB4{HH^@G4Qn( zxsJx~L{0x!5CtDKatgmmCUR0VUd{@nMFg*xbhsEhFW6GvB>o_bOI)dX{ZgxN-Z+mA~)F4B{aT`uK+l;KpxDH z<;mrdZU2A@4cVN1`z!Ncl~>Nl9nFG`MD zm7_SkAvtxNx^U>QbA(0a(D>_Im(J0^@EC{mWLA444YkLnG)&c1vr6|trxEI^F(8{b zRo*cFS}^P4r1^N%O{) zR&xeQ>Ibkh9dag<^c_k%2eQs}$XV%3n!7Z40pj~Z;QWN?4c?{6v53DI3XgNh`3(OT;wM7ZB!^tUG=aXI4xFyn zoVyb^FeKgt@6)=6X5Ad;O3+yPLl_>K{K@4^&2_GFrl}thO>>;9X{aY^{91S=9&`zH zX27G34t8e3DRJDb!-0G5bS!cM4fVy?jr@ct9TQj#Ov^sGe01N+GaT59s53VPbmm!P zE}X^6Cr+FNG;}5kzXk4GaDA@}N3f6Qf2eaCpNVvCx5zv=vK0Y~EO1XG^J(ZDgxy0! z{V}!#_ixr^E1l!1vlPMiTLj#379bdovs-8pn2#BRkVj~!9Al4JA=^4WY-Hvzms`%gkA85tz|IzcOb%4WZ+g^9+1}vWYwDY(lMWrXlp(a<*9H zb{d+Fb#9}fYcck`MeeZ3oisEP(=S_O5e?18#10y|5o52>&^(O2K|{A->@ADjWfAZn z>cl_uojn#=Y>|5`axa`Li>(GXl#X~2+)!@f-XG3~>`a7LE!eyP`!dK<8oC|DeQv?7 zS@Hl4EyDEIG_)9F-&*8B8d`#hA86=)jQvDI4`J*Vi#$X_%Q5l01$!0A!|?Ge9~tWA z?aKT5Z@e%5ft%o8hxCX0f;#-ZC=3)t3xf_B5T9<5rjUbVzeI(klL!WA#666@1(AjRR?9&1>g}58O&srp)7b}6v7i@ z2$Ka{-xl%SD{M$Zn~-fIN)M)oz)MMC6DSFjtmYpZd~La~xkJheThP!Jly@AZ%~2ja zF$&>{F|@FSMINW2ZFs#MrLFP$iE#ZShg`_6KS4t;;PuXwcERf>!}YEX8OE-|4fQf! z?@nnCyxtS8pXQL^?D`5C+JV>mP}&c#p8?nV!D*t5-0OJpY)bp%#dG1}c@7!Dz;KVg zh1UmAIts53g6pt%Vk86a#*0HKoro7<1TTaUd=vw(gj16FT~auThW28~F*Nip#xACG z3S!0sW`aXTgFvzz0h4Ly11xq44SkHU%P74J0dUGp;gt>dhgN#GMK)OE85;Tw zm9vC~zQh=eH{W3Ffz&5{i^?Z%;X^2T8Hj$^A>-M5BKQPuM0GqyL*Jteu)d!#w!$Kt zEV9`m&st;)rSnkN;80Kq4h0jKuAigyX3X6Hxz9LcBFo)M>3qz67IL>ZWD?8WW|8d{ zfwB1oi@a!&m*9YDY}m^*^ea~QDh>UCv7K<}G+uo@tx1)yLxpc*liq@Ab~$7+)7G;H z+e7I>dJEJ4Ubwi=rqBgb5(6o{4M&3aA@>7^Tmml%^iC}JF=Tz>kV{#qyRg*fkoAQ_ zE@P$c!BSsC);A8hoRwOFrM`!(9~^Q8lp_42Hdy#GrT1g`U*Y0!4!M$*e-O+630Z$R zT;{Z;Z9G2uzQ^XOZ_U@__|zzu@mnK8EA9 z5e0kJKE_x#8ZJU|r&{C_3tWIA4~kscI~=OjwZASUwMmQ zz$}6Ra~gXtt>6|>1h2eB@X9-#J(s>s8z%TOj&0zs6m>Cw#1)ML+<1pv%|xw1QIjBR zvO}(6qQ0}p_mr;V_hJ!vbQOU|*R{+L*K^w}f=QJkm{hrrWj%xNYar`dhskYgQqN;4m|H1=xs}--!7OUL{*I@_Kt?c?wG<+&v|A5jT z@H)(%6v6DtZA^Giy!aWVKjXzO;Nq7Kxt(1+9WQ=E>2Fx`cX080hupy=|4hU9p;81f z{HiGWm4@*{q3Cx?|3nOoW<@ZX-N`V&P_Q|62yD@RG>qGoiUTw}fY(zTvIqzmjEN|v z|8N1tRzb8l*CC6TfZyE4@7l5qo1~@j7w7R&zc?Ro1rE83J;;8CZ@T1cH(w-!^NKnS z91klH#f9vfPJ4~bs1_IJ78ezlz!~%0QMmXZ#V-)&_0zt^*eq)0Y<6{342Er&zb7U@dqoltsbKy-1){Y*N} z{1tbDtWzBF07!@LY^Z=)Q!%_c9jtU=uW`f2j2k}TlFp+Cj~N2zWakw30==uOkMXSRPMn+!Y%4w^21WZ>fq)eVQus9DOwO^upFI$!dF}Y9T6_WU z?eCBW;SDDcp?U356)*)-3{xNvvD_%lI}vkX;4g-Oe;Lcop?N1^?kLC|?U09Au0``Y zU@na8#W1ojS3BLc!`Wp`lTe$J0W!rQkAO7=a;-p&=3Ruc;N`g(UY;LKpL0B+a))X0 zG?X$O3SaGz$I|BUFpi%&*Ftx`W7gCt3y_3N;j#T^(wvtOWz5l7dhl9UFl|(X1W+l-vg!Z zb;wF)rXS!<08gW0cp9x@b5tn}Z{pJFLnr`Vxr^bIyFyo8<&;+OqgeVeDE+uYR_jW; z8omNcKLw>%I%Exy%a0&Ac%T)-18uF2oSeI-#p_VOdMLfYAx|>_aTKr#vNk(pokoCb z*1h;S6tERaZ*$0cCZH4rz_YIyo_!m10$loi1qHkcrFS^w87AOR6!1D^z2T6JIsq>I z?m_|J4O|S~z?(E0YwFVPUMvld&tiCdZf4ar#_HaOtPdRWtgbqj)qjivK7rDoI%EqI z&Q?(eLs?TWzG;^8XHz?p+DE*y7wrcn`bKN$$5K#;Z5yh|&v5i%CCRX>!PHmROsk)fhNFu6B}DgO469O zsI>QzgHTirz?C`VRS;!cDC%IyI>aG6G|XF8D!=3~6mU3{uH%rMOu#`X;7G_i$|0}m z1XP-9Nj(%$A4)fH$m^P>x2&|y5?pF1f#+@sJa^yFm9DhSlIAG81(a^-kT-RuD-E&a z1S}1Y;u3fizojc(+2*kQ%Owzfi!tRjO!y$Xvb32~akH@(T=ya6P8vuPA@(z=MM+ukogRCTV#I!(0GF-@qkth$y4)e}G65q{06d{f;0gVnPJm1O zBe{b>2|T$=;K}_y6EMae%S;%SBTB~E_E?8}z`kdO@^{^mNi;kHV^e5&EXFRS;fWZ# z9DXbaZva?+UeGb z!*elqCk@ZX*j-kD(lGAvErAWTlz&W@ETQ4Mu)tCpz6WD4AJs^{33|KYRvH=3Q>k0l|T>_tbCGffT33N;tceR#)%Vf%^c)aV*UX3`I z+A4vmtxwtg)Zjq8nagh_>Gdc9J{L>ibMZ4qI^RHuvUptbEDC|o$`bgj{G16Xpy9`{ z<xF5e=_HX`jMRTcHtrPQy5r zUILRSI0;_zHT;YfUi}t++6u*g4?kmtu^-br#&xg%j2ig`TJWnwzS0bI$Ge8yKd>}> zk(R(0>DR3LpGSuO((o%hR!V3X=f6vXG>kLdrC}PzY3Ngobg7uJj-p31eOvh0}4^Pso(kq7j@}D?Nlp z3Nf!XjU0rr!)XMM>MX5GBegN_NE)ewv7>1OXG==!(MUtgYXCpi#L%G$IURV$< z9p;d4n2o_(18f=?3P0n`1}zWAb~yl)jzB3RLCPqHe9P|LVj97H_N5oo$RkK)JdNP} zTso0PR$$&_8d;4oSf?&VMP5cDxRzFW1&wULt5?y;vlyF3Bik`{HI2N8v1@5WnD`7D z*@=0xXygry&8CrE7@I>QdoXqrjo`{m={y?2#h23gG=hsSr3+~UR~kxhrID`@aXXEC zhp{_pM40_uH1ZqfEv6A+_V?1rKbUtPjS`IAPop7>JxHTbj4h*ZFcH5MmQ#BkpAIU0 z6g2plL%xFvs;Ia-zz6BQcTmcCf}68Nl_z6`7W?A#gLHUN*aj&~vsj34loDyq zj~(|U(wrYViddvMKXziUNOOMd%wUn`{Mb3bBF*`+jZ7lV`LRP0MVj+tdyqt$^JDvp zFwJ72CTug2NOOK{Q;|q>e(Y>Jk>>o^MjVmm{Mh++BF*`+L&QXy^JB+|i8SZO4iXb- z&W{}>CeoZAJ1+{;EEa0Q&VLeV&X1jbBhs87J1;<_IX`yzjYxBT>_8=v=KR>9NFvSo zvEz(Hn)72P6^S(G$IciMY0i%w^n+;@3pHV>o^sWc+Z`LSbWM4Izs2hE5y=f`#zW18?{tE=KR>^R*~lX*r6IC&H1roHAI^8WBWZtn)743y+xYyWBa{Dn)72@ zGBM3!p(bntrATvrY}dC)bAD{!w@7n-Y{#NVbAD{gwn%e+Y;U4SbAD`NqDXUoY~Qg+ zbAD_KqDXUoYy%;tSuE6q?R6Dt&W~+K6=}|oZR!(g&X4U86=}|oZI=^i&W~+-6KT$m zZ8j5W&W~+36KT$mZ8#HY&W~*-!!(P9ny|-(NOOMdfg#eIAA4koH0Q@28Y0d4v8RPd zbAIf>A<~>5dvu62=f@r%BF*`+$A?HWeofi-c%J4lNGJL67^IW@cns1>emn;0BtIU5 zbdn#BK|0Bg#~_{L$77IA^5Zc`C;9PMsHuE@@ED{eKYoH>Q~CVhF}N=Iu^6N!KNf?u z~Fu^6N!KNf?u{$Jjy|ABwSCX?z~WZm03(7`v0k*JJE1 z8h-<0i)s8rjNMD)pJMDj8vhbw_tW^d7<-V$f5g}_8vhkz%W3>ij6F)@|6&ZBU5YXG zB&9Vl_7tTv=uD<7@OGJlvDK8$#n@U(7hnwBT?Eq&l&(VTMw&

Smgkz}Oa=cNkvX zO7j|EY&*?siLn=G-T;ifMDxaB>=l|f9b-Fa-h7O`M)Ou;>W3o95v` zJ2m#uypJ(&FU|W7WBX~IXzzP8-@?2PXnsD%KBD<$82g0gAC9rlX#O!6`-0{-!`N3e zzb(eTq4~Wq_8l#F6JtNn0?{)+(E?HLFSOu4y!sop3o!NvwGYMEU(`MtWB*XQ4aWYX zc4r-Y7 z$H1|D*^g?mEziS8m-n1FYEbz&k>hlSA0!{yZy;zJN{CDw`S)UnK$OGJy^jZ%mu{m+ zmyhE=I$jRRSf4Qy#|^|DwbSj3lt9k+gx+@L-Q3X~)C%?p!cEVN;V9_hl%olLs&u$u@^5#gyK>@LC{BJ3%`(?~B8C~E-NAUPfC@12tF zBg*v^;TaIp+%8c`5nli~I{x^82Tx2e{G$p}s*W>A@-KAt~wd zl=M(nnzj4Fl=LuHn$3Jf&S%mXNxIlypMR8&a0Z34GlgwKoc1rfd|!k0w&vIt)h;j1FtA;O)4-)pXV z*!}Xl$bUnWdsBpOiTqt6d|QOO#q~WRd`EDHe zMgAuu{8Z$BCc@7}_=ULsrAU7z!mma6jR?OL;ddhZ-qn8A&p!w`KZ@%=iS*AR{fh{H z72$6p{M~hb{{eFTOiBMG%Kh!CkLmj#k^ip<|5LBSDi42N1p*=riZCR?u&X@q4@6vP zkROPqq;pczR!Tb8#T&-0KrH2YT+~ZZFM&J}=8OCS5!xb5h!A#kvFAddP=rMyzgUDN zfzsr2GH?)-tHGb&9Rg*6ntXDPFz1ea02JoN`$RN z*hYkHMc7V+?L~N^2u~97I*72N2s??evk1G0@MIBo6=63a=M)j1D#Gp}>>b zI7Nh)i11PoUM9lJ1?~!wzEXr&iEye2r-^dYMR>Kyzea@Diu~(DdWPt?nIb()gx8C3 zwg_(!<>rX+MiJg5!nq=xC&HUWIA4Sdgq(#UyhVh!itsiO-Y&vBM0lqN7YR9ciSTX_ zE*9ZEBD`0GOGJ2|2$u>u_lxiW5k4rwheWtcgb#~wxdRWSC-)B$i2TAHjFH%35llsLEscDL)ewCzt^CI=TIVoS7Qc3+GN&V?X>MwIr|M<{U zpg_^ozmn8{9;Db0TbmlXFH*LfR4|Yv6%2Zj0#6@9Qo)EHO(hgkQAsMtiM%*_a4%BeOk1s* zQc2a7q>k_+b)+#Vf0`;$GNs;!zTOg4QpZbDCwP%+ zWlqYMrXEtdueBuA#*0*2b5g!ErIKnVNwxPPb)q>bUz%E`XzCJ&-pR4-E9%}M#Psizc8^^l}`dXYNK zoRlw3sib;IQm1>7>RrvG)+w6mBT4o3A_d!pOby+arq(N@`bkn}dXa*iOQxjG@$>9c zNu4W6o##agwoaLn>YqKS0g}`}FH*2~%aoL_?%SYr-(X2b)FdxblmAaiO_8K7@gj9;HIv$^XzDUa>T)kq zSD2H!%Fl@YqC#q_BsI;8)O2%FzTT%^Qb=7bNnPVb3XUK!HS`&NG^LW7DM`)pB6Ynv zDPJSHN@}(wb%Pfv*z#MV_S1c@DK<4b~6ysl}4iJzk{l zH7Dh(`&3d(B&qwnNG+{qQtv35x?hrdz>5@|b6`3o`0BoW3aN)AsbyZI9Ll6uaI)YfVy^_!xpZIaY>FH+A}GpXMdQZGnSFM5%B$(+(;B^6Of zy)8-Y_96u*G*v69s6y%;NoubbseRQ`gY9^Jd zkoriH`q+yU9Aa0kHboUupGs1nd6D|Onn~p;q`r`(zVssXRW*~!S4e#=Nqyr*%G`H2 z=xan*oKJ(_NmAc?k@}&UHKjVA{wPWPWc@m>s(B&krqgH$MJPRf_26i2~ONRkSB zk%}0T3g!5*sTOXVf}cGQdmKW!UZi5?q^KWKLljbZl2pDIsRCnCzI^h6lN3_6B$eYI>2XWlri4Kcprr-FK)YRojcyVdkXj z_#j2DP)JGN;gFZ_F#8dA)9&*{>Pm%_^c@a)`3|#Rk~Sq(-;bsg2b@p?*?kSYy6;$X zQjPtPQhZ%PO(dzNUZk2Clk&G~O<6+@HJ7AXc#&#pPRft#H&IC)CrKUeMd}1|QoeSr zDa*B?R+3a}FH&vHN%_*0N~*0S)y|7ldt*|ell&O^E@epQAW3!fBGt*9R2M&__9~>L zM{LN;BbNPIwCOl?svlDCE2O$hP4)27R8M14zIKBUWx*(Pnk3cBixm8FoS~-tk@`^4 zRBuVDj~A)F)lBLmh1406R6j3LXPT4h@5iP-R!E&CNuBLQ>KtQIq4WHZ`b;5pz9e;l z7peZnq=LRQrIH#TNe%QOHK>|NDeHZq!IIPvFH+^^r2IHE6P1+ohz)sp#Ij#|uhtq}EA zDd`a#^74ocRkKGd`9{%{^oR|4dBldQ;1TP`rILKBkdhv;Auo^EP&IqRrjU{zu^}&y z*pRtLZ0IUKj~P`{Q{~_}&1>+SZayUV>b~!k?z>u&y2gvtwdSP!c*GKw)OC{73@=hM z%}M$3OCX8|M`)HLb-fp<*~X-N&E%0EmF~MilA7a1>PBNyzINB9kh)2dn(IYso-wJ= zd_Q-es;LE%)Iu*(w-}T1H^HHjx>b_8&5P9S#-x00BPahTHg$(2b*C4pMdqY@y(Rpo zkh)8fy4#D?;{Q`p_efIrdXZXUPRf^)JW(`tpCq-^i`4z*r2M?22UJoINKy}ak$T9S zl%JQp6jIA1sfWEtEjK6StNRrHsn8>m)T3Uc9y2H9=PeDL-!s zDWq0NQcro2T4_$o&p4GrYLz5a;YDh-IVoR;u6ExVNouVZsi)0J`PvDol3FK8t@k3e z!JL$@yDz2;p3g{98@)(vGA8Bks3*nOCA3+Rde)27mTD%Y__~CilcctKk=jK!jqdyPp2{dk%M4pK<%lce^0 zk%AwZHJpg`H=@^2NWCXXz3)W|e)HClls`?CDWpD>q(1T@1wX%QNXnn4YAU2Yk)%HL zA_cz$Y)Z<{!gk;oh1BPgl-Fsxp)ZX|`I>b}A@!9c^|hC#zA+}{Yl0(%)VGqAoK%sUN*a{bWwc_Ax(|Lh5Hp>K89kznYWs^@-I=(bR8})bC!T{xB!y z>%&1MC4GlOUcSSjD)jB)?qI%>#(_(b=Z%W zbzp!(N_ts`y}Yc$=3dsm9B=}I6jBGv?mNV*`wlhlK40_b%65WqZAt1dFH(n_lkznr zT&QTOjwDsri_{U-Olr77>PSiIC@)e+o0IZ2y*NQ3b&Moc&x=%jV^ZOUe%?HljThl# zC8atJ%;mS4f>GNuA_HszWuCQa1C1 zJ4#ZWyhwGfW>U&#o^TgQ>SQlcU8|YYRZ91DlcY}ZB6VstlbWiK>Mlw3@FLZ-nn_Jl zNS!80_3|QhdNq@pu8@+R`(ZE7{jj;`zQ1wmYK4^a+z)$s?uV=3x$kQpT_q(w_rqSE z`(bm>eSey|M$wc!%R20JmUY}OD#*5Uo#-x1t4yTa1PLi78MQY~%DXCeK)b(DZW*d_V&+%jE zYWLkJN!{c{YOXOUe}_1zq~=LdH+zwqZ%it@(2u4LQ|>-_LUY*bgyyjM3C-a<{E(`n zkh)W9YLSO!)IG+e!b|*Us;;7``y{EQUZn0fC-tBoQb#JJ z20w=0NFgPChr?dJ!(nsZ;jphE zK_w-9hr?dJ!(nsZ;qX>Jnrf_QYMbo7?OxsYym|M%=!et^3aOVQsh7P-y<$#kNA{$o zM{L;3BQ|XA5gYy=kdhv;VK0x^u(?O<|ALhChz)yr#D>j1V#Dub-+gJKkcf0~o}J9|>ndok?gy%;w4UW^3%kWySKBf+GmA|Ve=MZ(6KibS&~l_N=6 zUZir(NyYt;YVWqGi1f*ec=_Z-%zg4AejJ*ECn}^8Qd5qXrV7n9RqRJoil1ksM3O4? zB6UzTlT!RVBQ+$cGA~j!%}E{XM^hb@?mI-1I@F6)ZDUelU#~8TpJ(JSN$PMfQgw_; zMUL>Jsgo5=Nl&wgm#108+|w*l&kw1t3aR>1Qw_W{)zDm1jr@@6rjTkZNj32z)zqAn zpS|tDQxsAyB&n8Oq>eKub%GyFovM(M{!gB z=!aAfg_Qh-`-s;s+(*oR;XcyU52>CCDd`my@$w3an0p09diWuAnnJ3l?7q{yy04dc z_x1Kes+U5lk0jOCi_{s$q{6vyn^LQ49&M7(@mBIdp> z5kIcq!M+Nq0a8-~y)-q*TvJ2**wh&csd7nbs28aVjY;|YLOxR=HB6Ek?nUY%V^Wck zel&HKLTZ#GHQI~R7;{n=`yq9IyGXSDKTW>W9>Mil(MXQq#RiU2RV4T0f-DS4c?@j)<2BN5tHNBXYeT zQWq$sW=l=o;H9ZK=9;?652^kNskxHWJTFo=o0D4LhtvRt)Iv$>7B5n_nv=TS52=9) zsXHX8JH1FPGAHG0eoEQ37P(83y4#D?Vq;QaU(<_&6;0hEN!{y3YKbwa$WlMur);H* z$X||*c>Qv8#Qc||Bg_1dQnu1X9+sL~?xm?mj5XzN4Ot~6Jvbs>9vl&K4-S9br;>U? zYU)WZO|3B2RAi-}?i;2U`YK7P!i&^ub5gzxT_q(?e~WmX{uVJm{mq|OkVHpO)J8wuH$v&YO_J1RFH+B%lX}h%snH6lt&-F>FH+l$N%@P2%> zzSfXcQqqGX;^n~+se%WGuek)3)T>fcJG?Zt(_B-&){s?FuSrs`dy#s>oRqIMWR=vL zlGIyXq;{E;^0kJnl6qT`+U-SZk1?spUOz*^7-dM1XPQO4&NPddpK0dn{HdTyN}g#J z@jBBiQiU_k{A{>SAtlc=i+G)B7BN55%%4NEswsJ^mU1N`MN~ReO)3y`{}-MO85ODHTA2P zrhYTll)twGm6Y^#iFodPxgIcz2> zy@H}%UO`cFuONSUC0Av5PwMigDV0>Q zH1rZLLoYQpbbq9jV|k(nNm4a3lL|!3qBX^Fter^+{v#x(Ud;w;qK7>J(O_94_zPnh z{H;6^9*RT{kJf=a7OO>0u1w(kCE1O3yM>!Cx28csH? zp`)y!le>nFP(vqPLsz|8PSsbC-g&%&Waoic=)CS3NcYmqOjipx2(FeMZqi^H(H^{p z)1$pfsH`CrIh{n{Kd|b0haOxbye4{%zK(h%%nC`>=SKSmPT;D~jh+EF3A?v)qy3<^ zurTaCyiIwbXkV!H4EWcN*L-gDJkjO7KqM1t)vMp2;hN}RuZk^Mu@yaE^oSL`fHjUu zi1sHJL3`NU2^F3Xm0bY;`tu5h==*1wzPj}ODQDFs`=^|X93Ex0G3}ivv=?J-VCoyE z7u%fcI3`;Wi;fhnh(%citQE27D2Opd#-gJkmQ>^jUU?!65E}~HP|St`%uvSb+crs0 z!l-SNqf_+#bGcq98iu=nk}b1j%PeeJvVUCdfHqtay%O}xl<6Kpr|WA|MoCcE12GN<(SpwV3Bt+rR2f$M8)UTX$!psjhG8MvXg<_%`xW3}LoX5dCz@Mbe`V=Z`#8MuiS zywwccR14m225zPWzhDM#uI=ZS%)l+Q;8)DREw$hsX5izrZGO!Re0=nEIfe!KvoQjX zn>QcTJ||KhtbtZq@GdiOYb|)U8MuuW{Eiv8tron`4BSo&e%B1#UJHKT41A&%{Gl26 zB&~&gY-S`KwBS$8z#X;V&&|M{wBRqzz@4?=ug$<+wBT>ez$a_L-9XN-WfqQAeK{N2_xzaWFX~9RD zfd^~BN1K6%Xu9qDEx4%}c(@ka+zfn?7TnSdJVFaT z-V8ia3vOiw9;F4hF$0g*-jeOiz+<%F6V1S5wX{2!fiKpAJDGvUX~A90z~i;xu4do~ zTJR}m;E7socQ*r1($?J53_Mv2?qvp^q6POh17D&A_ca4wss;Bm17D^EpJfKVT-#OW zn1Qd*)_k5B_)0DK0yFScTJQif@Kh~$kQsQIR$)WTz|*zhp=RK#wX}zsfv?emFERsP ztED~C41Aro=Fw*08QM>yv1Xq}Gqp93Gpl))7CgZWe7zPt$qYPO3!Y*IzCo+7OU)EE zM+?5(41A*&e5D!qCM|fX8F;Q1JlzaDPYb@r41BW|e4QD1z7{;w47@;VB-fi6$wDpo z1~c$2TJVi#;9Irexn|(owBVb~z_)9`3(UZGXu-Fbf$!9UZ!-fg(i+JfW=3+C7QDy| ze76>Sw;6b`7JQEx_#Q2Ii5d7_EqJLJc!?JLfEoBcE%+fb@KUXjJZxqp_iMqAn1LVA zf*&&jKd1#iVFrFk3tnLcUZw@FGy^}Z1y`7Xmutam%)pOm!B3lkAJx8xtv3TdrmguI zGw|bD@Fp|x6I$@IX5c5a;OET1E41KkX5go^;OEW2E4APk&A_X);Frz76veEkAI|Rxz1Q*I?IpsEH@a7OlSFtUgX9sM1HClxj74wpXo(z$wK7k zdXZbR5c!2(BH4}x#UDB62ffH$S%~~mFLHMlB7f40d?yQ$KkG&A%R=NY zdXevDA@Wzf$oI1l`I}zkhgpdHU4Qp{Y%VhGo#+p}$WOBn`KMmw=UIsSOE2=vEJXgT z7x{G-BLC5g{5A`b|LR44pM}W(^df)sFVZ4LYLF8)7Mb>HVCCvXMzatZ(~GpS z5E<8tjAbE`>P6BlMCNHnqMUqVk!i22R=%F4Z7edq#|!i#oh(G!dXYt0h)n23mSiE) z(ThAN3z3C-k!4wkEYgdtm4(P+y~snd5Lu!(_1eZF(@nip&+>3%k?E#>kX~fnEJW7O zi##$5k!5<3M`t0jre0*dEJW7Qi)@gE$b*__e$wK52`oXQ8vB>nn?MS`I6SEL`l)m8|j76r8 zmq+VGcFIEJF?x|*vJhEMFS2VEBJ1l#o|1*g2KpZFZY(n0h#Kly_B0lm-s8vWMfS=< zWFx)E-dTujtQXlg3z1FqBKu__vZ-F=Sy_l|rZ=KqTCag~&GghL1EB znXb#WdX}S&MW#2roqkehtg*Fd}@`fx#_Rx#GF$d-kpWWetMDjWFhiQy~rh5h&)R#a%mPK z&(@24APbS_=tVx1g~)UDrv9+8$n^2@JiW+AvJiQ`UgTq0h`c~A@`)@&_ScJCk%hBmw zPg|P_Sz&FfuwJaNc5bp>udv=~SYhqiWbLi2J|7R_CNVOav=^t^vlE)5o|`|?H-{>lv8K@0xI4BSx*{>}{CNelkL41BWnqsF>_ zuIwuJk0qp>*Gal*!M~b;Ptk&ZHv^xl1^;OV?yd#@Z3gb41^;UX?x_Rk5;O2=xdAbj zxQ>U;4I6;V8nF8%mz~GjTPq}5H6eYp&9DrF0E50-aLf#Rh89fC!2NRbGzzp0z(Rrf zK>uv55T|NF&e8Tlk+~4omFH@8QDPtjz~^Zh9Ap4?8PoY%24x09fWZY?2DJ>pE(ZOz zLJp~#kO5jD8GbNE83P5AL!mi?v_k5bGhspoYlR$9H6cT^LXN7MkaDe%W2z=(s8&dQ zb0N&kFVqTYST!NTv_cx03t_!8JhyTBvog1-fe-+X(B3P}&A=nIHMcYakJ7gNcmuHO zMjNfA-^xG;w0(@0K^p_G>joRE)j>N0A;92bE%-z;@HlPTJD7pTYunz*0PNEK1g(%R z=0ceHPSiG|tAP*zPtr0t#Q^MT#$>IK?o|^qMca&?211}2muSHmeq>1*>H&PI7Tnvc z=F7C;zGmRdwTkO!0Cs8r3N3@P41_@2uhfFiF#}(vrGK6Q*hPP;mca!ELV*4>EqH(# zc)Aum$P9e7_I?$Kgj}cXh2iEx*wc81Ru>}-gaCM^b`&0E2A-t_ zk1+#ZuLWOh2A-`2k2eF~pjFsJGw>X3mzm5xxo(^rwG1vXV{ntU?U$K>=W1)d!VEl5 z3%<$>e6toj%?vzW3%=S6yg&=S)(pH*3!Y&HzC{b3Wd^=g+t2)m%nta2Xyi6+&2!9Z zzFk}MO=jRbwBUJW;5)To{#$DYZu257c%fO%cWJ@5nt|`uf^RniFV=R|oo3*Bv^C#l z2EJDdc1;R<%``62(!STM=KHkZ`^>;gwcz{B!1rsx51N4=(1MqlfgjX@mz#kf(t;l~ z125BpA2$O(tOY-5241cOKV=4fL@w5mv_d|qnvktpA)i%E$TqDmzAz91H_Ub|_$xE; z^IGsXX5bgJ;P1@9FKWR*n1Nr?f`2jtzpMrSVg`Oi3;xXv{HhlGhZ%T>7W|hPc&B!d z_{R+Vn%2huGXT5h7GBpehy@IUfQ`SQYkMqY27Xfuj+lYp($dZ`1Mkv;bIrhSYr%0d z@NR9J^UT0|wBQ0W@H<*?!VJ7u3obMR@6&>d&A|J$;8HX2yV|a*VFrFrTXRh_@cUZu z!DiqOwBSR{z#nSce3%*dBQ3a&8Tex@?IX;5HnSnpm(muuv{FxS9-wgb@7TnMb z{Drp7jm*GbYHMy{2L4J5Ze|AlS_^Jr2L471KF$pMtrmQO8TdObxV0Jhd)=cp*46;* zda?aM+u!XCgutWrM=kx6%)mcsYwltZHL)Y#v#?$Bj_YK53ARl9`zrEP}clJ(zOvo%?=cD*6~qh(;SbPYQAR|_^=vi?s? z-(<`NGS*xOQ*2yoAL9&!0GMi@ z2NTS|d0Ox!GjP6^_7pR4ffjtJ8Q9i>FE;}xwBRevz>Zd7Q_aAITJUr;aFLewHD=&q zE%-VEuzgbWir9=aPs@tfEF&;!8@pZuzQF)YoahbFIRab`duW2-H($Hn+1;P5w=z0= zJ1MBQjx;^H-s;%gRngh?w>(Iq^|!zeH3Xn!DX9fzLuJRp-#ilfo0R5|V5gke&6!q` zYl|&8PIN)WD(7RB4Oo@)S4HRl&#JsLW0iMcm5o@H3syz%_}^4%*N82Q-6EXtm%~=2 z5U6R?ir6C9{8Vp6?A}@xv85HU2O+gCw(RV}*u(Z{d(!IIqZP3yHpNyz_KMi*ir6}y z+)xqQToHS&el2(D1eun(`12L9m(|`6kGa&*sZV=iv4d?>^8AGYE=N5aa642N zmE;Z}xKonc6?+>=1}_1UQ9=S+>Q%&U=+U4e_WqjKhYdm-Vjow;K7Wwp_H0-Y`+DOh zYw@PoxAvitO1&n?RJ%iF>OX+IpK1bi9qw!ooLa*vnM-bl8h)v%79W+l`15MXL77Yb z0fPVH)UCx3{YL?M8B-kg<0Xxhspn$vI&Nqct`TMmj|XdnrN-l}A~hnY^S!W_Pm!1) zb38;o0Yg%R6p_-{JAsLT>jJZ4?}$OC6AAwZqfiKjoj^`(AAvvbbk2!={9j-Mi6k?V z7yctTYGyFU+6#rt8o^C~D@#+k?X`ncDT&5I@i5#fVNxp|A?=`sS;UG*AukdbPY#Rc zKpyOE3~Y(*j@DuK5yaT-gTJhi8;tF?#jO*!ysR=FGqcKRKCN<^ZEBU%>?&F1G~3iF zr`bNOa+og(d`RBkn^ zB5lrrq}8g5w3`kj?cl0Nn|B~-hg3z{`~yilv?_hNFhyFLh19N!v|A4(?Xaq}^!5~K zX%=#LRk+=qA}y_@b*jSc-V|wR-0D_^+XE@m(zqQ_6>bluNK4~(WL3B=Pmz|!?Wn3q zd-Ookj;@Ndrw%0Tn5sxyeIRM|;`PP&_6;17z`nTF)~kp&6fbA)ccb-ow~Vhw@g@Lj zro1Yy_j=SSuZrvK9+?HVR4H7Txn!%<(Re*?dkHow`EEqkW_mYj9c?W%(F5Mkm?mnh zhjMdurgb-uw^=Ns&*=zK%fbbh*jox5wQ5$`Q^-p8%;-k|e7T<3k`XJGFJ znt+|N58$7`WY4O#HhzAPz*hhy`oniH`jKV!)leDTBwse%*a zn#|>u8)TzBE_2C06b=b8D`U}k+8wfy_ZEJJ|0M5_pW^-4*8@`#zgOgEIDALIrR2B7 zVE=uG_2QjbBR)j-UAepOhCtty^S&D@@0ZcgbL`G+Re5p?D0Vm;*HW+M)A8}{qfg=! z*T$y=$fo$EPsgu@Q7t}$_4DG?LBdU?l~h5i_=QXb;?`v!P>{iH-I-c5ntebs+GK1- zn+{|~a}+b$WNt>AjLisyR>h1qWiX>znayaHG@~2+n-SKVG^3lO8O?Q@(M@1Rb9vv* zGc==HGMUjGna#*e#lVd2tjaTd3s5l&MiR zG~Fd{ric9BOjvL7W?Ck1ria}((=xc39_BaGa>JVm#@osxwA^Fz%FH*Dn~K5Bv`TCK zYxL&7^+4vI#AP)9t;XiR)!h8I8k_&t1DU`2N(dZG%^!-Inm-gZHGe2t74zSk!Tc*S zn}3Bg|F!_oZI}jW;TB}6$A6%7T+%3Z1=-T zLlCBa?}vfA8T@+z{=KBUE$pz{W*mxQ%2>F=Zk)Mf`rGUdyHDogDS}VRT=EaG0F@v+ z>>5x^EIh?`KudbTzt_@Qw9~jnI}g+%^~GwZaf^1^MlIT@wy5$zMc!#-2YH?B6#rk?x-Xh*O&|AbC(xi8x9g!s~;=64NRNgSE`7+vN_siIk@c|X_cL2Cg zu20#e?x+1Odss$n><6{vxfx5wm!`hW@2XTFS&~#B#4;?0?3d%kKw|L^i-z^;tF>od zJB+98t8v%fF#fI>LmI~4bB`hK!Wi-%A45L$P&lklrG1LNZMVs+id2P{+P1qPZ`(aH zVpWB|?P1O73V*w53jgRp3V++<>6Wf=ckK=1A4`RQ;#T;_pzu$)!awy;I4l#UDSUTT z6kcFkZiVkQR`~8JDSUU;6#m(P6u#RYkkK&G74ELRVf=Hc@Gsm7{~Q$l1y}f&QsHlj zA?02k{n!@)~Md3Lix4!on>w8a?^u5QW?|bEla&M*)<*NhfdymKGeY(EgwKt4^ zE%p74Ti;)UzQ5u6{#NQcZ3yqF8^ZTyF@*0m9>Vw9RT;wfx)g3OgnxG+h41xn|43K3 zyY`0h@1??ja4Y%{ce@?{jN*j21EE?2h#VuRT{$G zwKt6aE%p76Ti<_!zW?F+{x_-bz%r80zvf1*prLvdGy?x}Tu;0}#OurF4+Q19zy1PI z{sof3tM7S`AGfWV!|a>^EO1v9wHs!9NuU&f`5A%TJ%DNzR_2lkn1S@HWn^Y7b=MNH zkIh_?)l&IE!4Gy1L`aK3G|)Z}skEWMsN`z^#PlB))R8t+)wRSxw6Z2rgBA*VsX>ce z_5#^9WWa(1EtdAOl*GBcjLl##aj%=kJ-Hc(+wC)IiO;YqlL}D$yv)U!S*cbS_gaQ< zPZfY*k9X6SsZ#-gc!Es#AmX-zxW`-o1v}WQ6i$$t8Re!;;0EHA9T*rZO=WB*Qz`Lp zDz2KqR7$0(9OO2YQZSW+xT(~Trt*pyT5iu^D%5V5xxtF5P>mEyj{}FIH z1V4{Tr`(84M{;QG9BVQEzv`G9DBwN8mdqQFC~XSvjzLm`)S}J6-H|Ps&&S?Lx+KE# z3=GoErIzxAmKLCvT4vPJ@djG56Xa?`HQDx%j3r~$pe9>U(+N^dt%RBu=+x9&s%avq zDFWJD$<-uHr)|1Yti79P`*bZbr+ToplNw4}i=!{N&e{_8RT-5-6>Cd)JdrBZ7=+2h zQc?!ib^_crr%J0kn>mS>Nh@PM;{QQ2lU5jHRtGNQ1b#n87-pq$<|ujGKxuoOfhM@- zn}ggkFwhQM^EqIk9l7RDB^K=jd0}!qIfQnGJa*5n)b&Oe*&8WF+cjO?;?_PTy?@ef zZ3q1J4Ylofd`VVn+tT{{LUCwotL!-qLFONUQBDt@aFIwX1Yi+wVZ#aaL8k;~b;zC^GMkqW|~1 zqe$tFb7gm&C%fZ(*&P>nbw_{M9hZo^V~u)u3{3A1I(QQuTtSDX4>Mv^A7<1e#R+nq z;SEyk;p132&{WD= zM_R+MK2r3^8r=;tD%m6Cad--_(Z8MABV#i5$T+n}DqpUWk2~Cec?5g8I^bijaRzuC+k_lPcXTvEag?APgO0Q_$ishUuq)0 z#(~6NCdHo#FAI!)!xeNYyeUtw6rWrR57e|J)HUb2DmdE* zYP+PdEjFpn_H+iFiEsU6npoHAA$DL^(CeWAu4nVA#nIKz(70AN4PjQv5=DaW|lbCqn*Rhil| zuPO%E=s*T|b5*1@IgqsZRgu>0K++b-p3~nPuuPG9bF}u_87VrB@0Zo|Lu*$*7~C8S z=`G^c?FYLY*uc|(ZE=ueO&gC1o%Fe`HZEl}ptrh43P`Xo-`o7pM4)Wpkwy7NKVVyf z-r=5!fF0qG!D_nm01azvAD+>`(;L=SY1krn!xr)C?(*L-l$~tY-ExX$vAbb+L&FyH zn(jGZ!-o5A*uCzC-OH<6^1o`>eX?Oo-3_}B8n%?zbiZuanZgtsDyG;rK|b`^vWD~l zcgr5&^*#8%YS}}wWz0=Bxl4dP1T6yxS+K>2tKgUw=<7iyIWWRwu&pRC!ZpZ!ARjg# zWO~@F@ZZz!nrhIeWKXYj_w-ZH(<^yTuaa}>%?ahpF9avO)Ac>l&b$_;_+AD^dUYoF zUeeVWmfJ?!7i8=xK1H4xnAy)wogp7-H^^LtZt8kuW!D8rvg;t0VdZR%|E_b@1doZe zvg?>Lue?duLf3&CFWjW-s`Avw14}CRV5Gegua|?F{<%8VK02e`(jPx#U1LH6y1_k` zZQ$ge@vkP7oqYUklxo`KR?|jM(W;I(c%@;_x*PT^uWpO~hN0|a z!=953+v;xEbI`D@yrylkVfx3gmc1Zb_M*FGFF?y) zyV(KSHrdrSv1F(&O6`$tOPN6V|JZvDIH_vp-`l;q zcf0rY_U<4^??rk)I?|*HA_$6tf(R%eB3-eIf^-2Jy(0<-oNyFDv0_EBEH*?%0a36a z7XFjGHhJ$QyT|AE{VjYy@7pDtOeQmv$z(E_9JKobJl|$+9vA7xA@H6Kln*WN4px0^ zgSS{UUTY9zIO9=&o~-&r)ZZbG{wBl}jR~>(`%Ki|=N|n{)EdPY-^5t`eIfD~9bx^k zJ*7p@NzU=1z!u$OG$~epUs?S*#N(*lpCukH@V6rHp5k##1pb?Nz~2@N{0WOY4(z|P zxnp7P67I>dz@HR>|2`h@x5onig9!Xj@qpK}^hkW0KZ|IuYZ@j>7I9pxy)zc}XGGwC zi-)y$#{&Pm1>T`p&f4IuiEyt|vABkFFY3=ru>=*vq2y@CZe zB<|O8#5M6nSRl$!Va+rM=L%Tq+JXUbVl2QpU4(N7A$%v!;+r)5hW37~st_i>p`D_M zd*|*B10C84VZv!sV6Qzq=I`?8!Gj&pT(HL2()CoUPcYNlEa~_|+*&3;0{1-mg|wr>H&E`+X_u6yMdV zo<)mhtJ|R@1@*jOYn0+aJuldBB_*im1-o1+6EyOI`EE4#g7D3IFBlA)GcREn%)Asx z@L4A2%$xcj%)F^_&%CMe&b)|t=4IP##*=zl+%s=l+%s=#{4=kJbmj@P#WYEp8h++Y zlLsv$NAxu5%wyUjiNK|nPqzjMNkU;h$t2lM?kLt4)3lM|S;%R)Y1$xhO-{p2liV5Q zwZ+u9wZ+szY74(pTlhl0Qogd5)>y72{V%iz)iucw#RMwmL&f|v^^NNXiO!h{I%g{A zoN1tQrh?9y=G&o8^+(icY~AhwYJuvUVsL2eSE$ap01l0PD%Cl~p)66QI;RAbCHTrh zSxG2M_N7BvDJX-*++W7jL-0+YhYFJ~PIczlbLJKcma$xhx9b_V)XpHK<=9PGF42ZM zQ_B?!UK-Ax0X4+|rD>~Rve?;HgB7s0nJK$-!Oeo164x#@HiDHrN6=R|f?#DH5$O&X zDTbNaXdz6uTV^H`6Xq0BJDaSAZvs|VId@kE>PaENs-`O=SPi){pjd+faAgE9G{wMo zr7i}(%18|0D;Ib;OX6h@4ami9?zfuURp~D_Da&S(qhpL-U^QSu%ym z1)9&2L}oKvS0v%HWa(Hr37;j4OczP`EbUgIH1ZNYOL7sBH#%p9mH9%TZV}gWaWWD2 zRW?N&z6nIU&bf;?>Ip==t|j92u!z?M5wFKYynbPh!RDZSnAb5_uz@*Y)H3>nQNDp$ z(#S*W%$41A;U>#m$!UgDZ$i#7`p^AGVK`Xmq5N9`pVhswYVryQQbCt&&Tz8(U1X~nFhGOMI4Yn){w8akGTq}92 z!a!RZ3tH>KKwBOQ+C^qkq~sdlxlU7*#9KHsfJ?fru9WEE0QFb2)2G=%EUznNYM#0u zel?PZLHiE4;VLalDCo2|+>oB`hqk_D01(5tk@V(^@yze+15tVvxN z!HzJBX?nP7u(MaVDujUZx6D>+MT8)kebtqM)Kk~Pp63#hi1s{eCqy3+a6_#xgv#$o zR%=y+HCg|Hz29o7=wP<5*4oQ^pbjx$pffsZwJctmTftY$ZX!AuC`n#J8K_g6?InTQ zJxDU5b_z+ccbIsDYqYR*guuU4lFIh1JxMBp7$5-=#Bx%IB45}Vt);jfN3%6rJ#kHH z^-#WhaAi&0E8rTLcYx!{YDthNFRd$ORvpD!-%s(m57jl2hXT@YGFPZ64vyh5StG+4 z&c74XQR*G)-Qc}@L48k+2BQ9Y{Yg@~(c(`;^*>0Kbb zB*F0H8P2>eN|N;xz9__(CfbekcIqG{g=>e~x_@zWda)94HO2tEf8~HMhazmoAye5( zWw^RZ9ip!GE9xqLRdr3mJau)#ZgpkCQFRSl;zlZIK$Vo>Ww3EiP;XL727AHA-LFQW ztT&V;se55Fe>s#T`a3{bA1F)l*MYLWP?qd}1j^|Bg@FHVD5LimQt4V~8cd0|1l#DD zHNa@Py1Pp|*@+ByhIO6S6gi(@{^zJSKciS!!OlLH`6Jo}P^Pj47YW zncxk&d@5($@_B07C7;q{%)zlD`JCt_pZcLR zMkNl}oMcJU3JAUfX;KG6Xa;htdoEn-WenT{t&N9AM2pCJO|nhn7LoO`#7E34XBo)6 zIlf*SFI^A@ExNZ_qC5HAMOW|F6y4h`(Y*tU?(HDDcQDbtGfvUHPb9ii#iEN*i9>X!S)%JR z6d_!I3C{3RgilHgEvF*nd=yX0bQ)&^J}J9@!0EInWs>QN_Inbkw7sTWD0_ns8Y*qC zTP_~7EEgD+IOO7SQ!bJo*0=2m zpVFnyaB{&{{8pN}LF*~h6T)r#21)uN-IFTNN*iT6RL8b`G2Rw!)M`u6jr5 z8?_W6OzOGgcHm3n+JWcE(j(D51-}Dd9^Vc;PZA5r?x!b>Nhr9uH$Q#vqYMyVOy3zNex+!6RnwKzD-H@;yWBNwhujo)$ZOdSc?FcMV>{#-u=9O_?T{l-ww~^geZNE5lWd0!?ttJ^Y=_(p z$~Ndb*Fw&>pW|@rnhg*An;%wEZ1=F z2720TE!XlL@;1?Oz0+&C)_2GoV26y+iDSv$WiHvuS;Lg0o6J34rrc&p*bp`4g3o!k zl3eiPHXNHZ@o_spdpFD8qjA}Bn~@#2#}o`@Pw*MTj@#oF47fmI2*%!X7Yw~$Q!wZ~ z4*EY5d;tpv+~$A+Di|+Xf+63UzA6%oH@yTy-{N3Y;t-0rOrcO`!ks<3HSGcH^|bG| zNN(3T?R(Cw+9Hcf;_WfsY}_Krcf>DETO>hJyg+S{i8gnVzeToeahr`TVP%?d?R7g) zw%Agt_AsSX?GfB>>_U6ErF6d~rEj0RlZ1r3bK-z5`NvfJy1QaZ2eyk(7QS zmQsvL98&tJh061wx_mIVW`UH#*_9|Zxj^!494|QqGV_Pya)H*n5KJy$OxB4#%Ve@L zOXR*hbna}$J(1vN7F!Qvwtfa|Jb~Zf4R1i~7Dqe_1?uR1k2AjlAtrrx5@Y1XypEd4+iPZA$e1YZCnNNv_s-d;>Br)#9U!M3;XK8kKO^yiy%!PxKF0# znnA-qdj}2EdRTaNNRGE%!m}fGdSSoPTIsIz1mQWQ`qd=Z^b}L8sWmKN+Cal|dlpWZ z;*0C|kixS{sX_$lCOgF#5)g8dyn{(H4aw~Zl6;y;ax0MJU#KLjNwCj217(TIcd*a+ z70MFS8c_BdlqIW0q3m}kgOFTxz9sSVMG|kP$*u?XRRXMB8@(icr)(7hi4Q4MCUn&q z@_C9nFAh5;5hyNkkUhsro#?94MCk~5jG~I3IIB8UBwZxDPp~<_5q_toLf}j| zRf>labQPj(Gzkjdyj4gj@!S_my?4X@2_=~eWhfaflu)ce0a)pw6jNC#FBs`8W_z)2 zmv)g*zXvGm0&qo*3oF_saWlGjvrA$;Q{M3D!getN>qDGv5p%YPm}%!uOxzO*rCY=d zVq&HPF@ublA(NQuwZ=U7)QgzUXl>-g)PSIwSnoX}u{+WZp;?m^$EtWjD7}Lh`fheDfI9=r2IgMYQB_W!# zoBof42<9|o?uG(7ZHif(ehCgcLF1{dy*Rx)*0ceQhYiM1aZmp7v1z-dUR|-lxLcCO znP1>{OCoc4Z{qI4%yM|hR-6)Em!%d;SEaipOSPy9?kRXax9z%tc`Onuvay!sHgkbnlUzg1WTSo>*c? zmv__D)0cO)Pbj2mhs0}-wa9~Y6{^I<3#_Y9WkbBWS>n}ABwkf4rc14+XJvt!bm^^z z^nZ0vZu3^tvzj;xl~R@q#d%h{S-4nGr_Z@tO^%eR&sqefR#OejYN{E()l}=;=d0ek zIbUmA^R*71ueD*m)?xFtuEn~B#zGId(dp)&cP~5_YrfV;tZV3Iot1kR&5P$^i8{6$ zp3{a2x%a2qy!xxyRNGSSHL|$Z*x;U#(;Sx6&7$d$d+yxRdpEh)#Nr;k9bq0>gqi^N z;9dkQ-pwrTZGgoa_BhHuFYfJ?-11^JZ;QON)`)?vL<|hI0iGo6OgY#GLs^XhN;C3;HGE}T(|^Q(c#KuvX1&nng8xS<}f*I;M`%P`z=4|Rk8!1MAs(wO=?(sWOG35ZBXCL+y1V|HR9 za;K6K>I`Lx$_+}HP!}kp+sJ*U7KLwuMfwtpnbN8Fd<;)t2u=j7y=PAmC(}n^UOXSe zJH;u|=Oyt!f2tzYA1pSfB8}AbD|GuwBXy}$IgY8=``o7@elD4WF1My)A3PN=hpE_y zO~t~h`~*(bT@$!sP)CWGC7 z0Btguq@X(t>}G@49h7~NLjxM=k)DW2x=$8)&mAP~lf)Iko*{I@1^Jypp_ zcD|D4YA{MjVLm13>sm>1O&VEjk@diy)xZT!lT&O`_9`#J=RxJT@-2A9Ypbo* zwh#)`+}F+5!!#(=(n{d0QdVM6_>;jY4LfvdN-T`Slz=yPbi1Q4j&RnAbqObx-iI+W zT$rEc4l({-fQucIM(8~B$>es8A`L31tZimC{*Irc3E;D5GacElufDTZ*J_jwyX<4S{AMMM-(lTlyY~ zL;4QHls;x%hUP;T590;$fW+%W&5Y2a@b@_1Vvm-Ej z@_`+Qd;T2Yr4%M2%N7H@FEOs`zz6(mS$=3`erRoe=t(@_cO|c^lZ}e*8Xa!k{-8l==(m7{T1FSU0jG* zBh(HqH+b%%q+2Z9zQlj9zd~@7HZwX7^U5J0v88%2@fr2Qqy_3n$v3GVGrM>?n5on*e$BFrU#E7lzc|>yZ&16~p9FUC zo767$Lkh&uThuQ0Lkh&uergvdyZ~iyLs@FV1}J+6%2E=KL)if+OG|tg%HD;tK+^M2 z_8yc4lb(XI_n{0Nr716(Hg(F2BAfaH)20qDR5EF!jH_V6cz9P2dfL=9C2@dXh7ZZq z>r1-X_>q~0KlBNn$cJQ^062frA<4YtllLByosBwRHWX?F-nn*2l0z;up6*=ry~828 z1nBDVu>O@>+&`1(3x09`j4hkqZfj;(@GSUDmKW(IO!3boD<@CK&tkZm1HXdYd|{8$ zuvr5eb_aImhrR-@68wIY?^|;DMd52U6LN+vY)5r^ALs1B!`cPnR`gVyI~h1E*&9)( zcPIuk4@)dyo|%VZEYptpbXekF=gr!~vcP=KtUWAQV}YPB+T-wNax*{l9p=ViNhBT< z#zITN;jpqw%qq^~3RNEvSEVKq&(*N9T~eJNmN@2t-EW1xcaXc!b6C@auwBN%XId!! z%7-Mv$R9c#a+znR47>9Opap$?0RFjLwpssNqDuKa_UAIcI5V7~%SYqr@(anfg82vd ziTtJP9y^`L)Z=p6Ry~$c{-s2_@k9GkrYpEr;)@vW1FR>`=s0nQyhpTRLOJkIVsa<-j{viZ^3|sWJH8#BZGOOgJLl!eW?TN)~l~ss4h^ z57EkrVScVjZf)8pRG+hFDUnA;-?@SWvWaKO-dBb5-24%r=jQ9UJvSLje4d-HCF>UQ z+lLTEB*>qL~$s;W3q>cxwYNo% zo>QvF!paPxc45}nC;Ad*Y#i{s{YEP-Y{~`_&m#DZO!aVs`bH8O$vc{lOWvsFmDDk* zMQEv%W3D-9yJD<_uco*=5=5PlMD+9K=?STz>mfJavxO~if^*!QklYid_oCg7n-h}E zT%L}b6OxS=@3=W3d9Q(4Pz)db$o+)OdG7=t?-BY5UK^n!^wi<0lT#t~E_HY6TdD5^ zqJd$7NrB1m`BmVTz;Bj|r&uA5&{O;TZ(Kae(*MlGqm2GjTs+JrbDcuKC38q^qkiVw ztR7D6sD73>Ry~xsL;XCdq54Hq6ZpGb{W3XI{UW)kdL(7O`en)<^^25a>gTD|)vr=7 zQ@;+BSC0nXP>-e6gTGbk@$|v!vGm#MH^HXr@!)mpvEXX;1U`(JM%dGJ!w1HllpI~?hw)xp z?30p9M=bsoZzHkNJ}KElW<>a!5-$PWmvj5QliC>JV&J`rJ6V_m)RU4$li!z}bm?m2 zfG_kg;7r$6FI)MPWW^8OhRJeDx(Wk$5#_(vvV|1Nh#0t?=J9j;axg02OB@tD(%(zo zN8z^u-)j|xSn{jvDM?TvzsjDHda$fj_Eez^_l)fL4EG=6H{6TFXSn|mpW*%kFNi4K z#D9bTRzKW|_wVw*;oonrH_Gfn#GCkg|4-H%rswq_sgvr%>M3}|?0er4^_2fo^#>e& zl2H`&sIHd@=uw~lcF?W#rJ+RsP|&UPrJ)4>ekh|a4JG?`KpA~$2*OVi%9;8$p`1wH zmNfOP?|BG*qA@E!!Zh*Fx25CIw?D_!w@z=<&vEOXpLv!8AR`btqb%N^WR&*|-Z(AG zpGJc>kR#O8VO8@1G`fLuTJ|yvXHK7%B-7z1`f174aH`tvFo=wb@y*H8l7L~f^*zm# zb0dT`8HaW1Om&I6+?qLk>FtR)Bem3tg_=1i=;~((x;o9Io=PqpE@kLf%OL0~gIz6C zmxF{?p;E6-2MMoArJf3_DdFmmA_=c%O1PQ<(OL8+z&=yL>7jg3DXJ<@#}|07R*0fHM!6btKM0@-bNUX4{4HLmGbIu zN>}xFWt{qlvQ$0GXsX{3LYGQJw5nlVDpBqMgN@RvdtSP2fZ?pfZ1(XN5qv)F2H^r1 z>d&5VcD{V-^C1koo7_~oi!iKdVK@}5LyBPocncetRr`W%Y5jZ(O`Kt&X;RJSXNt+- zSo%G%jda|t_xTYT4JoN=y5C*j^3~Gxo zsBdAwvnrz@j{(R!i#B(#Dp7LPS;VSDgkc=4Y7}_ScqaV`Lzu=fVamwGCtAKFO%mfn zk5-MTA{a=L~T8K$2xCy<-m~S>i$y4J5g618FWA zNK0-YDYE4&_CQi3uVRP>l2W*Vv=R;EB5ok5{~1S8&w(SUg&Rm4b8$-A35!!Eyad^5 zdq%rHurTS_mNPo!Wpn`}BtN5jen#)7Gy2jctLg;>8P_UGe#T(1f;!ND4Kx2$f&OcR z@vqP#`mdYKe;uX&f`s^byIlG&$bzr`Ycc)TWcIJ#c^UWgHWA3ncmTc{xoI+{xoyDo zYP-{`(Z+LV<9VQdEtTifGGR5q%OrbZ!2oIA2F+ODY1deAA*;0muAjYcgW6%g+$}D+$t-&@qHp>%wxsBykQ*W)8ts?yGzp<-zYLPWqWvtm z+g)%|Ty$VZi6*`p(HPvFL_=`HB+SFzj$4pe0jbt@cD~B;18OnFFe(%omE!Fy62N|AG_z% zEnd^ts_%M#){G@{{lMb2taj%Zhi0`GUgI(Q7gpf$2>v;7Xck@>GI%()EoMa?&u}cb z7sIA2g?)HPkl+gM!saILfw?E1e z*#10Ew?FD-Q1$}d^s6nP>_xiiSJy+?OHh`o&WEy>p)AFh2xYH8S(^GSlUaG`dKcMiYGVzMr14 z-&&&YHLSlL`c}dWj+ScmtB{R7GEp(s?sClZKWl5@e2yz;#bBy zmI)1yL$iDLR~yPm&moiXu4KK7>UxNKvBU>h&k|y-C!R=AiYUcQ6{A$5nSP2%RE#f~ z%?~DLEC;YpA0)l!UJT^qAn?Wy*cZ?E5O_oPLsy%;fo}rde00wD+>PFiloJ^roA=x^ zK0)`~p;&_gN@6>=t3wJ{fWEy`1LNLH3WBm+pQ3F_P#^_|oKkRzq4=341sj2;H2Xq5 zUJ5>!NWoX86wr(?|1oQI%uUvQZL#*K!Py2qQUf*<`;4I^iWY+}o zcd<5IAz4mjk&Pche6g-&D&sSbJNa^)@x@9fst9K1NeN$mH2H!Ycs{^-!GC*p>Vq^{ z_>;xLpW~mMr_X(MViJ>#U#!`A2G7o4V0NBiB>q(-EPrsqk|9fz6hKv=X8CoG!e;4BW!qRDdQiG)S-78WhtAuLcpN0JdsSUk>_ z&3%oQ?IkRL_4NO?u;_y{g(b%lmLl;BOVM)|7EEHI(d>})e?%*Wg@xvbEXGKDfkk58 zJE@h7%R3p?#tO+PTK2<82#|MDEAAA6;ta!57KYx-zE(z}F)Els@TV;MI_4&4D_Web z6!)^PRklX+BjnJhM$Cw+`5MH$YZp?2>lYQg{J@!#3v)C?LaSx_f3!MolCUg4`C5HS zh%U;NU~`&zgjo{Ht0kswVzN>*Ib{(|ot0h<_Rz@2&1Af!6uDYS(i$*|bXJOM4GoHn zuneIQ0z*h^WKqN+flcC)z=$NpqeucH0tsyFl)%PJ0-IVG3M8<(o7|QfYW=55ppLmI zffrd4*d~4nY-^2XpRt*0t4m;r#q;SB$ii#c-62k{+Pepe<*J-gN2$-tRsD05t1L^d z>VsT$VB;(ca&@sW&bF3ZwH3)#M{^m3RO0Du!?hnye)KpZ7Lp6Y1N%9_ybPvw;g-j2 zS+;o`%j(OPgdwHVbd}}_CGF5YriOOnd!TUmY?=0!pEjGR0K?x$564{l>TD#~`z;df z*E%@`yAu=au9heWjIm4H{I&$UrzzOnn8M2A!Uf?^+E?p?H0OYxKMwZQnwdW?_P$y> z_xy1_Ok$#0`QtR4KMsmDD4-@xUyH;GjPu8VrpunqH14S#UlB=M2KSOH)NC)Lv+J!J zUlAl111-52D4IG~Smwt71L^8jt6?@5(Zp|LX#Jf>wz&7|+LeY$QeEqZO_D2tT>Tiy z2ACvMN9)hb&@?~%wKQK*3884{pR0OjA+>0AF3}GF?hzwSRMv~EDU1uaGfO&7Z}|iaWR<0kO!W@M3SCPyGFn^A_>*xV%U8|cBc*BJb;>m zgba4Gjo55cj##t!h=^^2Ew%|}F_A1lZm!|pt83R=vv>&R+V#M(A&hH7Ev_vyW-%DL zj%is;lBI!7%MN%p6q8Ig$~718%Y?Lb&-r4K>k|B&FQ$pZAXtzu%c0|#^Ti~04S3-x zrVSLM%?VF2*~?y2S@|50m}|Ytr9{#Rp!f z*KTCuGu*V^AV;tsw*wbo(aXj`{C2hP0+}G~ajr)f*pyIWKYON)&_){JF@kw?f#gA> zv<9-?t7|tYL)iwsx;6^FnMv=USc3v;K-{d2HhS*`=DG@%FRY4ZMM=rE*tFWt&P%eP zr|WRETPPP;p1njB{z1DN6Kk*~rGb#%{pqI=)wQwKV8`LXj)k7bvEIk0Ptgaf1|Z1Q z2ZMb#FYp))m*+jc2komM3xe5`AJ_|)G@M#kNgo_)qJm`q2yQTBuUC*h5y02HS~xS( zR^aE?9`Mp8SY*1;Ak*oXWU3g8Ot1;$cR&?o>EPTpRz=zC9ULJm zN}lK9(mwbqO5zj)zjzR`A|m8zYl%E9QgRb5LeijWkT-Q!OhQ(YScmlbxI?}wNi;t% zUzH@!rtoB`B+1UoE*%;{(m3CTuaYE?FjyI8h;d)s(MX&;kYBedX%oaUkKbYkM1~4$ zQl`=g3$7m;$?L)4N;ZepStf_!n_wB6WO4X8gTpgoa=5ZA8qLk&$`T`v=Wu0-<bzg6PoFZhnkdCB>Xsz{VA&xV*R8^ICU9fmPVv^%jedI$7!C+q1hOUT;7Sv_^yKkFf6TxwKbec7#QYL-AI z`x%_avA*Ok8Qrj$(Vf~oZm%5k!eSGozU(MiUpZA}4BQ@=V)<*?dxBFW{@R3Or6IWg z={W#81n~RnGfq*5+!S!u-pib|w}3u!izITq)@R+Tql=uC@|)wF5hGE_mK;)ljn8<<(e2iTTPeoegE$owph3 z%^AP1fzsO7(AIRmzNWasH-S|#)f89taaeWe{iYHg;>zV~@(q-w^3)ZAHNzhi%y5^D zK2Va9fVVvcYBHv{%+`Ujz##|ZuyTi3s!UzeUg@Ruv2;yU8cx?oqHFwyuHh8TKugi| z0Yx*NDVlbmXlCe&MlE4-4!#LEH`C%=1H)eM#pK)|NoF%@@jLcSgCvGFPq{&|i;6T! z4VPHYH%Jp3<4(XgNjV}nu?N|cL52MLN#$U{Q{bC`q_fgX8q0ofaMe%`MRj(?DwxgA zu(&IEzR~O^GCIR@UGN&sde_(e>U!_Sx=)`102jqqZ}C|}kUNzaBbyFh=ayqwYHY-FIJfkJsOa&v)!^}` zW}p~WDEZ1ZOF`UE?|~Ond|=qwQQwKyzu_T{TUj)JaRsarR>iIcA;PE(V!&_JO_sCD z%}Nsb1-EdP+pSQv!x$zi9Y6*kqE~wi^p6j|7uOyK{i7<)loV|tlqD!tm6F;bDDx}Z zplmUeB`M34GTIU-qi<~(QQ5p$FEzzX*$K4q!!+v5i`jBdF*B}FrWMIgD`uS(k7fB8 zc#1p2UMuJk%`qs9Mn9H~zBHglN58@v{Yo}^K-V={6*cf+(u3gDtgiT{HdKnL`HHgp zL{%NHr?oXzw`%L*FAx4UgWZ06e#%{2QbyBYnEa~SmHK_EKCNxb*LFs)2qS){2 zNE-c}UL4YY57KWZ>5U)u`xFwQztgKe`tK0nO@D_wI_&pBBuszLB$>wV5&G?9ZWhU6 zzqck?^!IF%ZTy}?zn#o2lBfMdisWl&9#)EP*M93m5=b%$kRZgFMM%!m+S$&ll=7>T zqN|kbRZ8Y6C1aJ6zDh}jYZ7odXM0%fbK%qBglDR42`A~q-5gHJ52r@L0Y*ol)0UJU z&@aJAIAs6w6Z$0_31`~BoJPN7N5VPwFK5s%BoZ!W|MDC9r9>oL(*ETS^h=pYxUBU{ zs=|KB3s=eu!?&~{dEx4?;%KFfL=!VPrTf&E)j z6Fgxjxj>I+sUl4n7U=OTNu^l~pc~qtbz%di`Qauy$`pAEvTM=QCUAW;kAz#;G)U2@ zLl>B$q$pir!mUVAw7?KT^c8RsTologlkM$?cB?ES+sR0{wcSm??xq+i#=2=kilJ^U zAmBfu>lp1O2|XL2-4>&lwstS+I?+=e1SI|WDf1XzQr1>22zOH;1@H^`DX-+Gycr2! zqBlwFyCs!{>gDHoG`Wmx(#vj=iCCNL!2nZhD|fQo7bX);-a?!$ey$@7%TGd`vv_g2(J;4ccGWep>>*@04^getSsVmHPC0RO`lxX@HjQU zSgVBCWRGaERt}Ye(5|yb)D%W@ivAUZA%lUZ&@SN!VyHK{z$|t0XoJn8=J7CjnNvzO z+5lQ|0Q5O*y$Kht=|R)w907o)c{WX3yJ#xb3M&LNa)on7Zn6p728c^D8=fu*KP@2e zO0OA-wi_IiS8?31nY@anSTyGqFnOzuLpvIZPX7wRI|Mka*3yuS@Jx2;Z4VN!aguna zP2vuoB=)eC)^c38$F`Q66EHT@F#wiuN7$J+p??M8X9Z(hhZAvlXk9u!_jWFq)FcYn`@s3i;ejvniGD+$p?m zQ|d|(ci6FLB@4pu2`Kfn*G{1jl-kNEUJxtYV@F*_saF-6QrkGT1GEopO7$-^v;vM~ z04-`mqv6TZa*LDV%$4yWDUMtjB}fU=l>yFN%d?Q2&pZ*I0VPdO#O}0Pwxx|zmECC* z3c_D1%C@xoSRy@(Ydf$)q7RcprzJ^A*6CNIBijV2FTx;z%< z7aii68MMW77$@ukd;2BFY{@j8vtaz+7!QD#od7Zn3;@6g27n1{X;PXBY-X60Mgm)g zlraSs{EDS;?tkSKts2-Yf>@4|aGwJ*XFD3S6gJ>e?E`3W%o2MnsE6&~3`6aUg>Y$L zX3)pi?j@}alea7>%V-fHWf3jPk#agM4)RwDq5o?o5F?pcHokLmgvr=yxjGVQ~Q)LUFCqbyv;%&e&Q;IM>{R3r1uzseswuuAS4q>ZkW?igOVfD;xXf9;zA%Y|pFzD5=sk32Avti1jOZy~v zHEHW?axrcKddPL$klEGQqz7uUJFQKAT8I3!P8R###SUy^nXgKKM4&Z$lB$R{)d++r z=*J{N+VpXD-p}kj25qi!HoVSkD5MSKzqFS&$_Ge+sar9$i6?DFJDZF{P299O=%5W< zB$@DBNFX!=2sDA%!BuIw)d>V>81WGFI(XIm%t`u$#n+@yHob(ryPi68h%=8pWmue1}3PU_n8|RkV=o*1qM812ktV?)g$#7TJuRggjRi0 zU*{Y>0Zc$AfMMlx*>x}+atSr73m44HM>=@!`Nv_?2xL@vT3pjwrUpbde+z{0YXv_ZAolD75;IPG*?LTa8V$C*VWkO+D? ziY}SbO?IN5dfnOq-&l{A34ebn@a$QMRHp~}ES2WCSq?kr0L0pLC(@uf&2{UJI?6}cD?Dm z1psplDg`^jb(l&R-;}#Y4qU@#QQg6zhlsuP|)*zDky3OW? zY&Q2KJy|DjlAfrO%gAMRCydR#NH11zKk0?)^(MWodN?RpIVE{nmkZ2=npGvz>GVFF zk{L<*X83Y)Im7fFayi1Z59z}&HEdOw$}a!PDM{8+c2{OvZeP-u!G4$YMX;|RSLjq= z(PO;R=9DZwC3lksC~>op5?me~s42OsjjydjP01Pp)8ai_DCWmAExzZRlQ1nzS2j$G zhdBWHc}8Z`^3vOjoHf0FaQfB`+DiOU4w}Hb_oL&~AoD|eJdei%;3p@5k8A*oKt?)J z0i?4WOlbW*)yzZsEnhtCf0n(ni*FezKTBQ;rFl5g6X6eqABLgDHA1Q2?j=FZ9>SWu z^7&bEFUhThPp62%0?MIGOp4R&G+3aqX>FX6NjWXCQ7Jh>oTKuzY$?T8#sIGTVfxI& zJkA$MMu=(9SraeQ85mR%mFy zI-wo0p{>xNrTe`E`F9rI;Vl_V=o0jYa;N29Nv>pC_G@w_(z5+XKWnXl8^%Gny%0X~!*4zcY`EH#V$tB=e{}uvKhew8Kc|F}rw;K3=%LOAW)T$W;vOZ^%^$ z?W@VvXyFO90gS12-@@~{aKrDNq^L402zSWTx?pqX`LdO-`U--v&jvht|8Yj zP^ZW>2-LOYT1+*lH;@cu^?o1&QN2NAkX~;QJhH-2yN+DP>itBnL-hue!FD}FeN|xx zYEpt42WWK1x!y+IrSeoYhDngNk8?yoeeq>gx^SnbI_ry@41eZww?fMDZMbcP1d!GZfYYJ<-Se7i=VC$+Yl5SIIi>`}d z;twT5shCDWWGE8TVPqHb?Xxq;Qw$PK98jpRnV9-jEAl06UA>i}^$8O|VPlHmyA z2r_~})J^jAQ9RHFLV~cx0-s5$sgf&*v^Hl(K<&$=umRzbWF$j4i;P4F-$ZWGN#M5g z0jM~aVZh@wS4|Bo_Y2YBCv>Xp3N1D-0gFLGmSs9Y zt0=i+$QZ_}T4W63)mSoC*A?tRxPnLnJ&&*b9-Nwik8#u9&5{wLnPA7R-W5AFcZiG2Brm>fWS;76FD#!8DQGjV0Lm~CXq=DOgl0Ofw`63 z%7N)aX8@Y{v=|XNpU?!8v9GLC~m>xEmJ!}_dkmh!BJA=}b+>W5!LGIw7 zT+X1N=l9es98P3zaSWJuk~^Dc512lFZev#V{)o@1)ofO0pvn?V^s?nY4V zA@^`l2DvcHamW^%mIlmw$-NBbU~(^lc^|otgUQ}I1VOmL#_V|zQPAS_B3%UHpQt}T z&oQ1mg-l@}N0KQB7(C0}RqA@&JM~mB0Zi_^S03 z)&-FgsZco{3C1v@DAw-AzL~ZXDtxSJ!U3vP5i*-SiS$Uwr_5 z!MOlz5oeN_Yzdqx|8P!&ixrk~Hk%x4ud2GO|$mRyb z^2D0{PsE!3RU|n_d0i{by=k2is8#UAYtw{A>#Ecms_M9-7+G%%=|N*j3w8x*eae{p zd~k_cO>#oQbE}#}0~$Zluz)OJKsS*E z2xS9qWDU+JwhhP{oXG?RR{Fjnh1nfZdvOg-5XOh}g0MgX9`6Tpi$fMfB9Qv;3`U@n_CEWupXlSjqC zpdq&_0RZNuN&xU}JQy_Mu5tqa6n%3t9srG5v>DozyY|Q+8F{yC$qh0DFc3-^r$?VdX&~^|@FIwW%ZlwG*Ae5}1Gv)p18eL^042Y?_Di08JkHCEE#bEKY9?qSy-7T90WgHs5)0zm8W4d$vGrl<0C(En1_`u zLckCU0%(KB;};QGewULatUNCR?%0tv3#&m%b&NL1)N)}}o*uc9NFEqqe&j5S5vO}r zo6DkwaKH=HtRcjL!Vb;HNH>>l25|fsz%3z!OO3xQm4_=iE_dMDNe&kW9|IQR!&F{8 zn@f_}Gko!lN`N~?h=mjGXkkqX7gnN$WFcKQvXaR{v~DaSi|loSqm}IWF?6Pti%k&6 zEHv~b)v&q}c^h#z4h(Yr-i0V-@x!DuNthvtR3B?|=f*1}Za(zyk)r6hQPCv;26 zD`y6w7n8+|(CK6`BJ>in#GBA9rGSfi^UTx(~Z9=-RKWF_l8 zi>ySwuObkaugAkf@DDK0TtTtGwwCMz*=b=UE8CW{UtL|VCaYQ3MaXK@^%}B9@0!IO z!KkTu_dtFY!ChYzGqxxTT{Qh&?;34aXw02EU4+_(+Z@=NhBkO(4&L{y3-oc(%@gS8 ztP=FEAPY`#JvUEnwE*Y}(|9#5l;b z<|hS11eBVUBqlBv9xrDS5`%XkBhbhRGpaeElYdHmL^WWA*loh>A0 zciAN=&aUb%3A`b0SmgQ6ADRWc6U7b*`VCNm) zee*|@S4gh+@S3D=Sb0E50=lQ_VoP5oPJH8;T30&4(6hSQlc9Y+ydxw?_ z%o-puxq0<9Al{pa>HyifJANr0YL*pKkK0TDp;w5jF1Kva{$AG-4aWri0BOi0c}yDm zk~}00o5&_z8fe@F=Rv(jGSMI{1a)_$r-JP2X>yF+0(_XU4VhEzyKOWJmORN$dMc`o zjO=S9YMQB1>H>rDnZ6}%2-nK)uW;LmYbD);#?!$c6LpYqcoYElYUm98E6AEGI6NATk9#5F z49-ocB7m(0cK|U$vUyBXoPj$dWOo?g^qP;v7$LbF4W>2NQNJ3x$r(;GLXts;_o9rD zgqmA@Fd209A&XUUb|OCBXPrR2QWp0#6N*>Lx=$KWGBQbMNAVk#5n*MCuqwmC^R#uO zcA2mh-@!=jQejPctN+g85dm*C8;{n zL4{k>Y?S1Dis$xCl7kAMgX8w`D483d^X!b0#t*^u@usI^w@Sc^K9hd0|Uf6Dy=m=i0ZkMS zr0rz8ZX`L9sjH*ocDddhR(=(to7TXZfg`-Gxf>TjcaR+nxn*PrLT)G7$&fRytY)p! zZ~A7fHWpVnUugl9c-Op6x{K^$P}Y)N2+A|$84k*muIr>@@mfi5kwcW5f!J=cn}OUw zb|a8`$Q};lW*5kD_~s-9nN`~a`7C*sfy^h*B9PCK=QxlBE|B9L^vlm`WP;pF_A-z= z$X*2UdGb655(4DmUOK*fJ;C9~$zD!=`K)&h%ISFG)?^#vuP~6WlUESPePka8a=#1Yt&Tg%EWF7; z^HuUHgZU156~TOsyvD(VuxNV8Kg)hJCD00#B}7RXU|uJ$GcX6q>j=yn`f_9KvQ zleamL$6X-raBvn6_8syLgL#6ygJ2#Y2RN9gjKO|y8^>*_GavqdbXjyRLtF{ys&~n| z4BU_8T?Fnu@*V<5>%C9jXZ3z2@1uGjkPlcr*PZ#hBwUY@C_KfTL5VFByHiqya`H;fP_K^<}ypPC72p%26$K+#HFM)iF>U}~!;f4^& zwsRE)E`}9gw#m&;$)~J+GWis>KSbb?uYK7+JI%$-d$Bh0xIzzaKH0AY8e3q9&akxk zeQZBw2B$TTWZS8N0-f}UVC}wOC#b(fkR66q*4#NovW*BscnBu|H_U?BdD%tmo~q_& zll<)BR)-JZYdj{x9$nCAI=c%aCkpMtc*e`oM|tQYl3l@;NaKAjv|ZCr2GRRr7EaT- z*e`qUHr??GUA7SjNB3@UY7{I-{|d6JVw=N$CP$s&^$MNGP-~*0;@6R~;lT$zolCYE z@C1U|OURYRA~?+~IL&PW8E2?=7=2F!>B#Bl{t8GcbLwGvT^*#a{r0j0k z{+kycqz_xxmNXoW>fFZoF7;IONJwU*=$6~zjD4uA7S4vgqE2Y`j*a%$* z$UyvYa7IBkJk8-LN1m^gBBF>9TEvCL*c4jCd2@h5gKdPa2V~%cIk=}FoBE+VUe{I^ zV^hZz?6?qG!bNS`2rc2x?*Snr84YFGP*C#q=wCthNC84iu{0J6p=BH;Y=o9M{94&J z*%X4L0KwD}*i|2=4&0*)`*?X3=cdd(8^VYaI=6gF2dS*N5$t->k zigXeI?PdUt%D#QvY2h2?u%nL9~x~Bto&1d8@>TbyyOFl#H zmc!(*>8_zk&mmWiee&chE{W8$caTu6BzVychl=s6;pgOY*4udUIqK~T@`c?SyOart zeM!D#RVR`!QPm^lh*_0pVTF2Mk*`?2Tgg|b-q+-7yB87-Gp3v&XBZMo$QgvhujE&gFmx*CEMs+lBfqh_E68uC?(gJxvo1fW%Sp0)@kA^q zjd!sKP|iUBDpY@vKNwD{$R7x&v*avC#1sogd3?tU77N{EnBujJa{EsGUD6yg#~aXZ z45i85TvgdiRE6R26#ZslkpaJ{P@RTi)z-|j1#Ks= zw(x&6WSr4C0R{$%DZzwznSSF2od_j~=Acs+LG*AW$IN&Iz$Tf%=yiMsED0JUF<`IK zZyc~>C`onzdrfy!(NW!I0?R34084=eDGb;f^cx2(6-rVOu+VproHq?%AVjyDz#vv6 z=N%x4y;|Bab~$ils@qs8i;OM<05-t7jM8shmuXOv=IHXE-Q}IEOLj3J=Oa+z=KHxh zpV+aMFy#-yff5A&IkWNlYG~ty3Xgk-6>5sra?a>n)59-hU&;8!-UMN6Zg>TNU|4LLr;5OD+-bWJmZlQr*aCsl%GZu&RIIa z$?rOn6s#`lB$PsT(JCG)A2aOr5%tL{}cv;bo_;GJ`Q4syl2_=8^U$y)h3p>1kO@sTMZgZ9+QQTKeG{A%QHcVW-3D9N^4@JNYMrm;=4u^#0Bh#Ur<8e=&e_##kJ z#00Nz;Q*ncP+F9=pq5Ngt_6V-Vz=NBl15_VyNtfZk|z5iOrMZ5~KuH<9U!z4?C@srcP=ll_*PIOiN)xAKIaA*Fno9g9T;wg(6yGD)_uwGrqeD@7%p%z`Ku7aP1IWsHQQGYM?$>Bh14?VK7If;@;9As#lA3l4jA?V065HFk zh%jyLoL@942%~8&fL)9AOXqzpuHV{FQd{qrdPuAlqlNPfDD;y7tq!!P!=O=}P=|w7 z7fR}SKx>K5>Zzwa^a=c#l&lA>>M@9Pw%6kz)`yb%CPdh9c%^6ZwUXV)g;ms6tgU2O z7i>>sE9WX5dIia71Hh>P!9fd|S)z{c-rVj*s`P@ks`oPp=x>Y6SQ+ zVz^R`(1^peF_bhmaYekp2ul(>tD~!YF4WFtkf^4}9pq|>HS5~rLw^feb7;|=L8JPtIR~u;l(ev+>84ySaKk;oToTR% zCB6=lT{=rp;=JQ;Kd@pN#%Y}}MLS3~2khFcHMkB~30Q+`2?J=!21k`d#`@y8vA)<7>(+o-YlbydpshKqFM^Vb5Z0E;vMABf z6J{G|*M`BQYP1apvn`agMKGDg-V13%@GgO0#<}O|6zl4{g;FO^Ic^8twqqz!J=~5% zsXdgmw^5=ZrXhoG#4~|xsLdm5z zPpjq^xhM~uL@AVDy5q-U?xhl%rCAAWe3yF4Ku_qWC&PiNfu0-=mqE#891iWRPJ4Pn z>jf=(F=%ua_2QuQhLYYk_d%lQ9Kcd~nJ3K4q21*SCY?o>b1?frNgo@gmqhiJSUJ3m z^p0UgaB1Ovy(POSC)_%c)!u1E^p-fVop4)8;98vO?Ws@t0_FNLs#5LIm!s+xP;v$4 zJF+4!_p~CegcesaXjE@p$wBJ}CH-t@F|CL`f3_9TC+_vQkLNVK3I=c$8yr<&S8;>8 z8cMEq4K7YA0#3E)8sKe3^o<+qzMfe32h932tf?yL&tW|PN(LaT-B!dEo-nV0cGobN zR5e_~!Mqkqu0=38D*{GoC$WNmc-a$I#%)hr=_%0z0fB)GIjU&}a>xyWl0i0dUiL&k zi55lnL_be^;yQqT9qXHFr0cl82SdqVyKfl1b9KJTQ}105?XG7q>3qDNgE<6BhHx;c zE(OpY_Qchm)EWv9hBD}Meh%fJ4}+3n9CRnf{XH?h0ovWbVA5%E0|)a)D7jIGDX=F7 zc#7O`Xg8d}q(VEKgE<09MsP5lE6O#VFh@eWkqjmk+L0X0o1o+-Da>m?T6VL>)WoxME8d^L9;wA11LzwD}~i z(XCK&t2HG0tRRhtC^88m9E|S_#BEURHU@%y<3LP?-zJ;=ve*c`i9c7`AO#^HAd{C0;qM7Ak#PPk#7>hVr!cPE3%zHu<`g5U14 zVH#N64W)Op7VI0>;vV?z9*f*}lL-5-}b_+~`5ixd{Y;w(m_VXBQ z_Kkx*AAXxJf*qHoKf-y4%=%maa2K#X**C7whvBz}%|0!fJp!eVuomna*Wyw5?NPIZ zMYG4C^fA_gedAg@4!=Eax4<+TDG4S-vM>_I=Ue`kg#dRU>yv%s`dkFREi(JG#>G#0 z3ixe>g#`Q-p{+h8R}FuRu7*I8q1{$?+(s zP79_O87_cjPXN+SumQ1e+0l`&2SM9wlB_+|jGnE~HTzj45~K*<&k_+A(Au~>s zz9akYK(uI?qIHVa4@60I(www{&)H-dSs92HTUhL=VtIjR@g~JP7w;B`mgrsL`Vzwe z(URjz-d}PWe4Z_(m5KzSrMi^5s?-4Ze6-XPrJf2zOV=rVQR#MpXqjPUCY6~CpDW7b zm)RDGmi@ZynXr(C#_&ikZRJk7m(efGPOP4PPpUcW`F8?%qzE%FS@?Qj^ z75Y{fR$(}NZmsZgg;(M8(+Vdm{1Av%OsiPDVk!7MRmoo|DG;qxtWvc~H3HGfqbuK2 zc?x`fQ2A)(ZvxROYL(0?+3>lp%8n|}1fo@ws}`+#K_FW5#+tX)ydw~;RlZjJT8-fI z@>)Y`-2k7%&@~z~}e16KW?1qIF8tsZpnPAX;y4y#w{$htK2ney^_t zqV=2C?^eGDe16+NY2Xh;8@$rsV1thX(T2MkzR_@hAli6n9k89zjQHtethY-m!1kl zdv@%3MbE3?^QE32^!zXoz3igPdS2E$5bf2iSN~qu!slJR=JuK&i1z=e|B3!51JQxe zfyV}(2t=>@>bhU9`z;V1k~XCH5a7?S8pB!)YaNK*c-f8D-8du=9W!Cf)G^Zo(XmCw zRvudoKKqRwKK3T~+%R^}*u8=1IRCh;aYf*>*SNvshQjBXaRuXc!sl<}gX6V8bbPn* z{l`Q95yn69>xpM3f*ei?Pbxd90(^F#bj_qef#`#~AAIY9eOl6o}54HskRbK&P26&HP{{&}HU#v(#A$f#|HFv#QLx5I%35 zb=xeEt69&^dVAKpf#~e!v%Agi0iXM4AD;bXAUdb_oa^Vn{F!stoVjxV&$&hBR-OxV znEUYDC+BVqL?23jsLVs<1JQZvyqtL;C-b__yLR4n@cHPx4f8eyqVq%Z%gqNq&;Mfn znfZYKf(sVZT2L20w=H;m!CQgo!eR?+E(Crr?7VQm!h!I)ZsG2Q&%x(M3r{VCdA4Zq zqDhM;!{=vcwO-bHSzq`Zz3l#F)8O;?a&QOY<)}kd}95c^#FJMnI|)z%nU@I?E2)jPXZmETK?3wr*^>SsSU{+0)gm; zH#U5};Yc95@t%#3Y}w&Z-vhvwxn)J4@9>t+p=}bcKAH7<>(fe*ZIl$#q(i4 zcaV*NrHKuOLDTEjoiDk+Q)$=Yw{%m9mjdN=Ba3IWJ}3dH2VhX6DXJ*y=Dxj;=x z419i8xk|a<&%_tw{HFs(cx%rpCH`!@P2AfjQ^MS!l=^RUz;)tVt(5t1bz*izrRTre z3F3{`=4~iv#!$rVtjav|FaHxR;qKA zD*vmYn!{x}MU5!c{+Au|oflQA|F1hY5uiHg|D|&z;L2@E&Hs<_V;cOwA&|yK4!Z1~ zsSW8r=yKOqsr~;&9ZaGBS0v)0Qr-VgDq%|fzatWxTGN&K|KHTY z6#GjcV=YCC=(JO7!3_Kpw+nQ*=lW-EHU2UP(aj!gpp(;D&>b>WS~tUgfF`J`+DhZU z3f-`X{iTpfH0Vc(r%PKCrO983YM63=ImEE(&{1jjSEC!I-Cq(pOVR1ur^l2Qe?<~v zGX7-|jJ?uUP+I*}sf#K6mqt=T<-q4`(V41T^jD@bru1JPQ3^F$exuNMpmUl+x+%L~l&R1heID zKM-A|0I@S zw*BJ!WViF`J{67KarQ1pa0ka zntBxum?Km0oVtb`ziQ9|!`in{ z8TN1DJ?8(vZs0!iII5I#2EefrnxflyvW!hgV&(*gh66M3F8u- zThEIQFFII!&J)KWKAs{p`Me0ZMF@-0c>;Nek%uTXQ|>q~O5UP`#pyhe1mZ-A#5UxX zEq&K{c@oPLmZ|fElE{>&s=DXAXvswji`RK##SkyI>bmc|e8rY8EMw;h7Ke;^sIrdA z{pUq3K2gKscAjW)iW?qq5x-{7sSE~A{NH;1Uv^}bST86UzJ(sf8sX8|A8(Y5iJOR~vk zv&kkaB*7)P6^9^2gS)r5LveR2?(XjHu5GCsr4&jFv`~RUOADn6l<#>G7M7d4@5e&$ zX@5L3^S`rac4y8xbMNlmji+y_$$UuP)cfahF;n^H!~3VFkE#hx1Rv#uy6-x<{nu+M ziP_3k6US9O-BnF$BDpIk)%}Iv_}@yw*Ma;}h`GvZ6VGcsJy%U^B6=<-*7Iu#<;8sE zw~6bwp1!LlH<5i;=f9?$0v{bE-XF1~dG#-T4%~Ows|kKYPT`SG^8n zAEW1U;_v<8&O1M)y

t;|&1MAW)P4n1g_mZ;A8xLjm!p`uwBix*s49sxCIFsCfKQ z;Taif0iHl)Z~@#G!goI0PjXFcR?+ZeqQNsF)FM2gh~Of`e^?dwSAjHtu~o&xlZyw> zm{1Gx1Y?2=aqmS1&ZuxVm=-0rs{nbj0pb}XYB8R0ko=E8*{K5M$p?yOu&4!j3WCLJ zz@!wrRlqzQ0pl4oYEhn&pz#(s=Hz0p3Y@1Wa6E%YEzDCCJX{#R+kfZg_BXPoiTx^c zp03dG3?H>PPg(fHhfw@q)4u&yg*qYB~;6-Q5J z9C^l)TBN5mmJ-I(TPmKO-gxqiDYZ~faZDwQtG88LJ>7BT8Cz$I_Eo`V z_*li=vlVxqv8NXA8H+tGp8Mxw?);(RPgMv$dm-obS+EGtf^ z5PkMT)H6)gf<6af$_4em=kNaFd(-&yZYNc=J|EHQ8L?_npOc8?q8k3S?vmnb6}Zn& z;CcqHTG;0(c)75;GvrutT7~ZO6}q0`s}}b;3*Y!XIR4v(A}3FwZ+}fUmH0*l^79wS zp24gZ_&E$_E^t6xH6`)=GS* z;`#ZFXLn4;#wG8T;s>?Z&-Y^AyWnZXd9~or|AM<0{gwz&3(m=S5&k6!2rkY)m=OOl z)lVwUUyNnFG#F&(fw}6d;FVgQWKX{$iFxt?+*L86M30O{Gt~B#ajG(902#F z{Hh$_#d83+6YxY|Ilv3F`E%jj|1_Qm#GmzFQAyzLytwD*MJZ)K&{s?Z$_YGz<3(9~ z_v?&%7vT2i?UlsuDj&SK`G79r&I!s9Uf`TSN4PgH{Gsx~i=7udbAxh*7d$uU^FufB zm&y++KX~Q{m2FCP30WQ zIXs=i?I3*jQaOh@)421|hTBQ*J?pro@`uVFZrAWE`EFLtnq^EElA|au($*dI!C}+`6jA|zgp7@M%h67#jV zGmdf^m2vJX76c+zZZ=kveGHvHj0)`m8Mjh(tC`rZFj0t&ZJV+L!~M@ zo>`x$Zl|vJ-{hzvld6oRGM29y%Ba6PYbl3PS?i&*R-A+BGuQ3k4T+YKDrc#jWt4*+ zgt_yUaw?U#5+`qA9ur(7B6ro;olGlSKssHsjcLGxmrV?19 zCono5{tDimOUU*zjml#xkNvNF^f1TVxlB2k%4Lrvm(e*rPRi1$WTukY!z8T#@3HQL zrW{Qrv`3cE=!BjpY5&M*mDf~W`~Py&!yb3%Hsx$8w>{F_rq6HDGNa0GD!)B!{<@#X zyK|g!IF;ibd5)t)`rUrB?e>SB(`9Cr>Qt(`pH!6?ecb6zIh{&(k0ssFX+7SL%c_!{ zN_L5n$nMvMJK-tEQwi^}B|JK(=lgZ-WpHI^K%8`{LKThXM z?6K}Rv*;yjD`!^DoY)Tbxb59_=n}H7a%knykJ|ws#dvp}I#$+KPOY5!Q8?L?uzAO^ zWqJ9Ea%|<;Pr?Zw)tGmj8@E$7RL-rO`%yXCld^l)!H>ws%E6U`KPg9il;hrY^3}4b za&qP5kJ8zmr0u(o9xIzGM^}#iB%Se5kA2tKC&`w|*_E?DYKME$_U}4;C)rv#ymI&_ z?U0XS{JTycE88lkS5E&pobG8D3mPqSe}82~y#mtjg6Zb};f;MZ~c#bnt}?H5lbH$7=LP~#h~``s(< zOmct<4&zBu&hz5Vi~FQX1&2DRQYTe9ABa1-3dXeHVm!Ybr1p;&H&3cP()-%G_Yf5z zy8NM>#=FzJP;QNVU1Vm_DFl-?w#lZ!jug z)CQwITDcD&@Vu9$svNEM8Q=1a%Fi$Ee7W};6*TveXH=lPxPjui_MZDqv>dDU8|4?_C5QzZ`-h)&CsXa(t0zH5a=q`n($jNFedbpINQu>QKf835L z-u~&BsVb0OTt`qz;NjQaeQu`$=>hh2<$w?GfX~YudfYoYU2RIrFP;~_ep0W)y)mg^ zQX7+c)8Qd~!1Imps&b~Jr1JXnG_HG(QUUdl`RRFb3iVnZJh^)AQ?2D}wNE|x zR4O-AbLZ&;p6{B^Re`0P!_zrb{o(wlSCp%&b1dZpcYMI}osGrn zB=N<}wQ7%j^y}_ESyVx$vhSVjs{$`^1JC0fkELoeOWe6tzN+Ta(+AuenhG?vp{Wh+ z5&D4VJ0X4Ka<#9iJnWf=RXy?j!M(SsV0(mlO*wAjJMObMr=I&;v|Oq7H{}-3q8mSJ z&)L1lsen^^oVtE{3_hUyA)BRgwc6^`R`;xJ8_(+Vb#Hen=pI9=dsdx9J@3R#$oF2_ ztyTM7;!dw}S2dsi%Lm+ho(ep*=c!A)$LIsPOTEK#z1sRzs{UW8S{+M#|8Q@AD)=5_ z>Qj!K_>TN6&S?^UODA+>+)oWxlN;6kr`+OMbmM3JIlK2j6@Y3FRF{BHzz00{!SZsm z+6UD>_^j_K&+7B%UKszkFEYukDiBp5KC6!WJUnmriKz<2CvZ~oJUEbg4T+P$<36Lm z^G3~fwJ#>lv?}*h^Z1}X;NBZmFsi*#y=n7=eE@IZd>#Km#&uCLDyI+@O*teVmk1(6ciV>zsC>My4 zrcY5G6QcrB3Ufd zG4Lmpm&GJ=4q-MI5tGdwP<9nl%v(?%5>w4rQ2r^V1(g!!pz30J&`^{k#f+e1D9?$R z7P~N8BE&39J(R7)Y|BiP^TZs>2PjXAxxtwC;LKuPa9xz`#Qfl$DBl(fg8xK$T`aWb z7iMdDvB)|a2Fj z+7V@cu_|;u$}M7b=r6)-6Jm|60?K+~tqpc<6T~{(NtEZs`mhLL4oe|6gyH#ywHF)1 zR-oK1Hicai=I{WqIlLsw+G0yM<}ZAc*cy)c3;$7Uv!@YedtR~K-U;PUvBUlm%CE#u zheenjHnGbAe{wVuyB+W!$2zgcaUSI#VxO~}*zf#Cn4RB?gDxq|E{8bef)Bb%i#J`9 zQ7#m3xsHg#NrT1PNy`ay(#qo9q$5zy7Vjl}7v)#t{RsF_L^AO~WFKLU949`E!W=~1 z6dxzcC(Ox8iBFO>K-pLvO|}N*F7bIXtZA~#;#l&G!kj#xIG%jAIFbA#@n!N`;$(_K z;&_Vc;_DRK#i<}#n&mZ?kT&9Z&QAT@_TVMRcUc9)fDkvs!PJ0>Ob*) zYS>P_U;L2zvM{HS;>R?24QWb?^J!y+Ic)=RA?-Mn3&l@qkD&ZcTuirBnA5!@E~TF% zevYm#eu-Wv%+XuKcHI$)+ z5XXhKOIsnVL7^KmtZ*)2E?i267w&~}jIn{9}bi||*=9u)-83R9zX(e4TyHOsH zNn@@GgrSTmQddS6StFy0N|~%^EnzNNUnVaKe<`|5rYL#}<*zbju`I$|tf)*?3^}CO zSed%mK9q0BG{tTRbMa7_ws-}U4Q0CG$RWiS$n?eGv&FxW(J!Bo8A@1WbcuW@56O%r zQ_Bn`E23N~%q4foOr`!6=F)*ObJ=FXT(-5$QWk4hc8km!i`Nu;LuM<7amy8z*~_&@ zIZ);(hu2i@Bbl?@O<^vt$z0_zujQ-Bm&y-8IYQ622+ylgep$Cs7nHBddW{aEJSyuq z7Q)=vE*muICtqn=Q#NQiP?(!emajI&dN%z=Hf+{Sn467|jhdlBAc|V zA)B_EB%8GQT$o#ZDVw!EAe*<@E1R{sAk1y9%NA|V%9icU$QJD_!rVTkZ2g)^w&~z6 zTX)DU%pJVTonDjeJHZb+ZIQ2a`T^zNvO{OAW9PE6W9MG7Q|ErN zQ=v0OL=d3MMRxoBv1VIG=WE*?4v z<#@SdC}M5sTXN|zn=lVcDVGhain5kmF|0evk#fzjV<^wbwXfUdy4P#S^{-Es8(u#m zHw_P!+lE(>+lP;rdxoEtdq<>}`$jaD`$ue*2Sx_SgCk#&hemFcZ;ZSw-yBs^zBOuw zJUr?P`S$3{^4-y;wBXS*HS6f(TF96zTIiU8nr+NcEo^L<7CyF`W*<9IbBz5&bB;?Z z%;Pd@Nyp)}j%%kyj60x3jt|$O#<$Xvjo+gspO8sQF>!>Ja?+bx>M0*-X{O>eOm%8$ zry{ASSd)6b&3re&Ft zLzrij(6Y|xhjN0JZN_^jzt*zPj1lIURkR#4ac(s8w3c($W-Zt3ceR)1%+hkt-J#`~ zcTCGWKeLu=ehDq#{1ICI`5$V979Q6MFB+`HEY6}8Su##5x-`F5Z0WaJ@nt!*mzVX| zN-WQ&m0W&GE43nvR(53_Eq3KHt=y_1TKUxlv%SoHh-qQx}~GmaLYxl z(bi&GZuw;HYz&-t9@uHH49Tm4 zodL_7yb#zoV3|_12m2N*Yl_-nXTh?h90zs|EPKkHVBdjdOJxW99xP|dn_xeH_@PdQdI;y50)#{Mz9NDc~Z>=`w1*}>at)L!Sbcf1$GH6Z<;}1KZ6xW(-!O(u>5Iu zgIxwIlx8W|uV4k!-URy%EGF%Fuq$AN(^Uhz3RW~-VX)u9ilqAk>>60{bl-se0ah%1 zIwhtCRU4 zSO{4C%&Wmd!Rlp624(|$C5t~;7+8axL%_np8s=;dW(RvUS3xibSmRu2!JJ@?a=ixT z0&AM94p>sKCb=+w5fNa`b7B4>BEg#F`UWfttYxnE!IFWscqsrZIauplSHMz$waWbx zSW2+Axs!pV0&A1^OR&^n?eo3~mIka{J^_{%tV7<5VCleK%U1&|Jy@rFMZluLI_6IT zmI16wzF)vHf_2V+1}qa;xBTycWd`e7;3!xYupR~Wfn^2jUT7d#Hn3iW+JI#T>sg5X za)9+I#C|!!dKZoa%LUf2a1yYW!1@+$0+t(WK;a5tdBFM?UI~^LY*69JVEMoX7UsI; z2OCnD>sA14a17!%q9E9?7{qTxA+Vt_Bf$!T4Ug#p76bNr%-3K=z(&Tr4OSFvL=pN+ zF|g4^=r6^=MiuD|_A=PmBF(@`fQ>1_IV}k`z6j^E6xg_;X~9Z^O)MG=Rt9WB=?q|H z!6uisfyIJNDqRJv9N5&-1;NULO(}!i6j1?edKu)Vh>Bp-VsnF40-G6|9IP_fj99*o zDqyo?`8ukC&8oN_tQy$diZj8ggUzXU3#`8z*s40s!J2@rty3ASDcG7iGr^jHt*j<{HLrt(wV7q!w0P764w`Xs#E?|3lWd-XBw!fDXtQ*+AUR}VtgB|Sk3Rn-Y1HBG| z^#psP*9Nd&V264q1?vs=R&NQ`2kgz>?ZEniz1_POSU<4Cz4wFl2Ya{oO0WT7@AR>O z4Fr3?_rG9+z~1Y_`5O%OVIR)l5U>yW>;xMM_Hm!ZV8g&Z>hmAi>tLVuxd1jC?32FO z8zV-5ebyIyW5h_XBYipdqrg7z%efy7cC_y$urXj?^!);CEZDJrg~7&wo#>YyY&_WU ze$BupfSv4D32Y+Rm;LB}lfb_2NB^4)_EkUZDG^h^PWQu}5-}C*RR3tOX<*;<4+WbJ zcBX$zuo+-y`&R{<3HI&yV_>tuz8il4Y&O`r30%uLU_VUYTFwRgenJPZd0^)!)CHRl z_Tz-uwpj#6?6CMrIc>Vg8nIIplVW;$uw7tDrU!!U2GeFlg6#qGpMDc;FPPtqR$%+U z0%lYI+Ye@%u@&q9n0dxbu!CTMGc$l40<+8v0(%22Xy#3@H^Hnk&w{-L7Cb8t*kQ2H zSxLd(1`C<>8Q42uVY9Y_y$fbrkQ?khF#7@**!y7N3tE7E0Onj!4(vlP$AY)OJ_1X+ zU?tecV6Fv!fPDfMx!@$&r(h8a2Z0>{OSZ5%*k@o-3;zW>3YKEw8L-d6k}t{zb_^`l zA{*EjU?~?Z13M0uX3;3H6JV(q9S8doEZw3#U?;)SELO5MY{qaYD=L8f1{Sj-2iO&`!Yg}%T?H$;vH{rdU`19Q2D=7U zeB~;zKfsEuS`79lScz4`!Tth!d39Z|zrjkajsg1ztmNvoVE=-ZSv?W#I#}s7#lUWW z#jZ&Ub`z}Znmu6uft6pg0PGf6xwV+*NC8%H4dyvgf>l`i8kh!Fd2KbYBw&@+9s=_N ztGad>m_JyRbq+8SSoO7kg9U(9TmLdxAXv@y>A}okHP+*`MFxS@UXRxnX#uOXAsj3i ztnT_h!K`3)HXvpqL%`~9K+Hsjg4Nr&56lMk%Em=tVPFk51%ZWwHQaa^%ntVIrt@G9 zu*RD{1apEl+B_f31=e))5U`|RO*UTvivVlB`3tZ}ux48(fJK3|+|m^+8CZ+093wec z>n$831z4-CjlfcZwcT10EEQOrt$co|!P;--^GgHPZkr7(Em()G*TB+&y|%3dSbDHd z+sc7OgLT}t3oHXzmu>UFGJIFAST?X; z+dl)#4%Tx=DzF@2eRd=P%L&$d$9}L}VEuM1273vt?~bcrxxohPI1ZKvtpCn@V0pm? z?TiG=2R3l$7hw6phV0x8Rsd}9uFPNs!G`U!f)xTAy6Y9N!eGO96$gs}dwthK?>uWO=YDdysP?D}YVkgPapt5p3Gt z++dZ!X6|)?RR)`}cLi7#u-SXZfK>&Xwf9S~YG8Bs?gOh1HfJAwqXyXgz4VQmVDt73 z1gizMa9=a9+F%RzAzww-0b9He`6{w5*rI*NSCRF=mhMBoimVT|WPcm524KtgR|0zl zY}x)fV6TF$+&>VkA=ruo$R&}Dz*ZkXE{SXmw(3BCuqI$@4>SR53by88Ww2&o>kqyJ z)*Niz!8Kqlz&0M70M-(013o?rj%)?C`5^LDWNWZZhv)}wz_uQuAG8JAa%c)zJFxAC zdV;kF+a|=J%ciuZba?+EGH`w12BAe|$ER`SL=yauPvx>?&9=+-*{;YQo6yqud7Ur` z3GK-DEJW(~UO_YQ2>uroGz&Ez4+@$c*%Oa=33Y1{bg z?iuLQI|CgN)r_uzsMoy$rO&`#?L~ z16iATA84pdELr1n>LlGb zVsP9zuJ}$t?hIs(%cL?clbW?4_;h?04Xf_e@)W)0A--8Y9d^dcbDpNRyw5kwKY6u0 zLvMM%Z6_)+UM;WETmITN%Z66 zvTTp^YI%#^vc)&c>AYIrrnemIo8_tYX@&|g$(|ohs)2ro=^p@kVv=W>ZcsUn! z4)JRF6TRj5ORM{~Ji@ExBYMm6*HZUwd8}8_86 zAJpw|dLIT>&}wdbNB`Z~1_4vvJs~DyJ@<7=;$FX}D7>6_*6y;}ZRZ}~0XEdS!w@@2hcFISr0=Gpso_iuX3UamB~S-$1< zIbYRT)_gn5b$P!!zNWWq^=Y16R5?el8crMH~Px7m2ptK|s2W#8U~a9#6i zIZAIipKs6kAFq~^>n-Q^$#T+GUM;88TW;Z-<@R1Jr`B6;>5Ju{s5DV&g^c_7+l~)> z`5|^dmOW8fMO@y;=iX7df!YbH2oW|BhHszRg){D3s}U$8(N2akIm(nMQ=v?Q65qHG z=}|_b%qTL8Ea-{*gg1gTf?uQy4Yw2$p zWEp&i4UT`TWx7GX*#`YK8uZ(0(C?5zzrzXpSz9FRXKiE9uctx3z6Sk981x%s&~K(e zzqtneb{X{BXVC9MgMObH^!v)7-x*y$Q|K$9jqtB=-1;66Y`4?3JL=k9b?u(Ic3)k4 zphr7U9tfQnI?3%5sKHOb<{GfY25hAPTOYdNj=c@H?QJt)dkoki19sAYoi`ZwTEc!d zKLh44VCfUuvz0JlHT91TTo+a$tdjfnq81mUVYLicqp-$z`Zd1Yud4y;A2#4lzX7-V z4K-jR4cIsXHras9Fc^2P0b6A7*i{DoHW>8VVbE`{LBBT)`n_YoJ~d#+4cOU)aTfN2 zF3ylg!+tjC_nSe#KlJ_Z*y{;dxJ>w5!c7MKEIMWiPZpjsJlUO?$8!tMVqhz`?s3TH z;rSCj-|!fNe#H&?l{V;C&Y)jqgMQTw`qeY&_o_j^rUw058uV*t(66IGzitNodKvV) zm9U>ZNy2{ieH16JOERWo394Ol}1*1~|bGhjUo z*dRR%TxU1PLH3ym&qeI>4A@!&wkKhJupcyFhYi>X1AC|KXWY3IwYYO2`#Jp@;dT6I z(C?x_zsm;wt{U|F+o0c#g#8?;6UMp2!0#Ofe(&g>(El904aOLlaIPFf6Fxu32!qFt zG3YnJpx+dOelraE%`xb=K;KUuaIDbpvtS126^^Y2{dOC$g9hwv1NNcb$1(0_2JD0Z zJ7Zw)2LpD=fL$@LcOxNl2I*PgI;Sn6-#b$qu*?a4&6y*i4>@z|*8^h|H0W2vpkGOY zF=7oKThZXLO%nR4v!#K(b_T4I0qbtS`skkvUfUppeyly6rHn4ZVpx>JY{oXa`_n|?*BL@AB8T31;?}yiMM$hn^ z4RW^gyg|Q924noD?}srGoYP^9e{_$fK6-(}K04(D$!{W%_)&ET;P zgU2Q_=$Fc%UwVUnnGE`6*Z0G7NpLO+R=}WN5d&62&oBpN492Zs(65R?zghKXKF zXwa{zLBCc8{n{Dy>!iO%!|Ukg>h3;YKrQZC&Nb3C>JA$fe-7aqXVA~!e8#mkVIFqv zF<=J`*xLr|^Mw1S>x98;`^(_5Hxja>Z4FpQJ(CBLZq)BPVA~DY{)Bs5(ziTWR3>p1 z?_hn0cc%v7ou}EBjh3yJLzctV7S=Y_p4PtB5!Nx*nbx`1UDkcp53QeCzp|deJ0k5u zJBD@*?HSrPbRgcZm>aq{bYyjEDFu&!bK z!-j^93>z0VIc!GQ+^|JqtHL&f?Fic&_D0w{VV{N_4?7$7L)gz@zlHq~c0F8%o5C%) z3d<6nJ3N1QOnC9|(&6R8D~DGPuNVGmc+>Ef;qAgZhIb3^6@JT}#Gc%q+MdCl#h%9= zV=rkhZ?9&rYj0?8VQ**eVIO24X`gAIXJ2dIV?Ss=Y(HT?Z9j+e%Zv8Q_N(^4?Kd2$ z9qk+)9o-$h9RnRh9U~lL91|Q<95Wnq919#P9P1rh9lIR|9dA26bbRJG;W*>?!EwoP z#c{(K>-^Ap#Cgnl(s{;t&UxN>$@!b}59dG5n=Z{|a#>t9m&29J zmCBXgmC2RemD^RoRm4@oRmN4pRmD}yRnOJX)zsC>)y~xkQ8E${u-3KJwa0bP^|tGC z*9q5Ot{X|)CheGXW76$O_a}WTD!&k}Po?miXia0uDxJ7JOIkCVVx%=2o4BV+T643R zpH18dC9N@RHenNYFG*`DOKr)oj7V!k9I!RO0T(``lD1daPXv#WyiZM9!&t+8Wir@_ zF1#002D{M3@*kSvxam^{hoc!B$)mWRQU*t{855jR2Ir+zrj(`hpfrXAO%IwO`7J3K z^l{K9l3!zzmcXDBlDFc^pyRCJc7JJ^45PelTv|rq>GI1#(lUXAx8ebOVlFMUcmQ8d zl9uK;V4H-en-p(tOWVNU8PYbGYyg-GA1g>(f7bBPg|ziy4Ik-9OPDE}w4|{(q;(KF zTc^UZ6L&O8>p0F3z8NB|lXzeo58#F*X`Rml_$G(6Zsvh^c>wnlN$UX~z&9_X^)L=t z(!#R!IFI6mEen~_#dG4FGcA^zwR z638ZQPLY;$c)B4LvJf)dRw6@^vKhrD?gfz{sn|@*CT`%6A(>gj4Hq&b7Z2oN6L(3- zkiuwM(&L$i6eYv`4Kkz}YnZB0DA{R_b`A%4V}T6i425zwcsGCyy~Hkm zv&$_qe2y82J zR*(nEu!)bBrL78U_$XLfGSO%Sn&L#*n(_cXZ{E#tl>i?X&Z|g zKLnDt$p{?V6w37A&!i;_MhnCDOQdZHo8d5TVTfBQ@c_OaA}!U~oXZ1i!T2Q!X_*Hn zwBWmM(z1$2_wfKH+p?Vp@Le@&+06rXEU4ujF6~ho_?-PXYZk7Ng=@sG8A!`_Z2rh* z2{zBOd67-r&@U~Q*i1%Km&t0A{YrL~P24{(Ex)t*C!4sHS6cpJ^ItY`r@FLUM>9AD z^F|$rB{@t5cVM$Or5|Mk8N=Sra1Nf#<`l|Q$}}Fp?Z+~BI`V-f1=%bbor`AheAX7R zwuH6itgU2i4PJEcUUuHchoxlg01v#uE^o2+4r}kR_91H@vvv$i5qy$zii?tpR=#2L z9OVZ--3yc}Y+j?>MAMoY{jB*Y#W0X1u34PTmnkJEB`NJFT`@VlO;lRjGoj$ic+%Pl zgIkC40PgaX*8V(zFVD%~e>oagpEpX&;4OTT+u6k3%`$iwo0s`C{$jsNlp}18(BmqjabA;L)C}^`i8q^r7^n^rQ4=mjSE|qzs}ArVQbMp_E~4zD^m=<_OkC za)w5+HkvYqGL|xq2gXw-P$p6)Q6^KSP^MC*vGa7w49ZN(EXr)k9LikEJa(Q>SwLAx zSwvY(SwdM#S;o%GDJv)|DXS=}DQhTeDeEAn^jzBYd@&oyHc~cGHdD4xwo{5cuF%$E6QO?Z<_jzwSKI1V68u8D4T6q>&RM5)>=@yQCd@WQTpO2PRY<^ z2jw7TJEbv?cB0&Z$UureC4gdri0+iPDSh~eJ(K~I8f48O(vP*zD1#_Ncyu7837a)p z8%+6-v+*wFBg#ZddmcE;T3gCFHoLI)8l@|nZ?JZfa*8sUtOBJ9r4pqw#FXEZO_*>3 zBurUZ%MB5KbDsaDyvfJDLz%!wjHIlh93q=d8OP>o%6iHg%38_>%3OBo!P+LuM#>7x zd>&XtSxnhNHjlNiQ*XJv$LmA7?V<^Mf97cJS)82s6key$l)S^tG)TT_OOrp%hV@(T83x#R1X^99p zLHUw$lJZr+*COB)Yo{q^DBn=NrJUu_bF6*G+V`yeK>3k!o^pZm6Xhc168rs3`Gs!hbD*SXlq3{Cia*6f z37`aG@IW&qh+?4xQ>?TS!dfWBMhT;YQ|uH6#Yu6ob5hnKD3O#XN-9b+N^(jHN=iy< zN*YR9N;*n-pxDVmSqq_9*$k$Hu^En1e z-%@^{e86XjFNHL|0WA1Pl@u2N1=-eZ@2lq-~-WCtkw+5DdJ2}JId`-Bz( zNm80po>GNUol=WZm(qaJn9_{W5~A5zYeQ*I=}759=}zfI=}Q?v8A=%r(Oj&JqKu_X zpiHLBpvp)7}J$yi%OSxebK*-Y6+*-6<$*-tq{c?+VYWbGZw`;?C;pHhxe zzMyTuau%YcW9@s&dCEn~FO=UXzf=CC{6o1xxdqWOK>Rd{KP8Z2p@dMvC=N;mY`NWwgSqae4esQ_fL-pm06>xE_92DSuG@rNpg5 zQPlkXC}s-h-k;9uA3>ob`KP9Ek^MQ@{@Eeg%dGJQ`t#}fbDsT6P|8v`vHsO4wJG%| zano6fwPuvoly;O(6o!F+AId<=Fbb#6e>_BsGdhLMnUr~yg_I?fm6UZ9&Y%Al%1(&J z2=(7X*-v?s@-F2A3g^%N2<3Ciamq=ER*5ybw?Ez6pPubc&-VYB@+*Zi>HimnGwFX5 zqE&_9=Z_#sC?*Q$)WkV8(VtE9XH!y${2ijzpm2sX&X5*2L!2C~C8Z68zNU4gbb-jf zS>s%3y(oPt11Li&bUkehC2rQ}aN2Z;yw2Jz%3R6<%3{hg3g=H-Ls?JRMA=H=i_vya zc2o9I4pKOi+S?R*qV^$$GpTVVHNJd})2YQx=PA~{p`4@8C$$TdOO&`sxx!i?ZTgPG|Dtu bn#SP~Vj6di>696i@{p(kxIZ_EzYzZiYX