From b54d20ce233320947a5fc48c3ce62b97e616bb6c Mon Sep 17 00:00:00 2001 From: aashirahsan-lm <72972600+aashirahsan-lm@users.noreply.github.com> Date: Thu, 3 Dec 2020 11:38:27 +0500 Subject: [PATCH] Update README.md --- README.md | 31 +++++++++++++++++-------------- 1 file changed, 17 insertions(+), 14 deletions(-) diff --git a/README.md b/README.md index 18f33012..b69d8243 100644 --- a/README.md +++ b/README.md @@ -1,16 +1,16 @@ -# EL2 SweRV RISC-V Core Chiselified Version from LAMPRO MELLON +# Quasar RISC-V Core from LAMPRO MELLON -This repository contains the SweRV-EL2 Core design in CHISEL +This repository contains the Quasar Core design in CHISEL. ## Background -Enter here +Quasar is Chiselified version of EL2 SweRV RISC-V Core. ## Directory Structure - ├── project # - │ ├── project # - │ └── target # + ├── project + │ ├── project + │ └── target ├── src │ ├── main │ ├── resource @@ -28,17 +28,17 @@ Enter here │ ├── el2_dma_ctrl.scala # │ ├── el2_pic_ctl.scala # │ └── el2_swerv.scala # - │ └── test # - │ └── scala # - │ └── lib # - ├── Docs # Spec. Document + │ └── test + │ └── scala + │ └── lib + ├── Docs # spec. document ├── rtl # Chisel generated verilog │ ├── ***** # │ └── ***** # - ├── target # - │ ├── scala-2.12 # - │ └── streams # - ├── test_run_dir # + ├── target + │ ├── scala-2.12 + │ └── streams + ├── test_run_dir └── build.sbt # Scala-based DSL @@ -56,6 +56,9 @@ installed so that it can be used to prepare RISCV binaries to run. 3. Determine your configuration {optional} 4. Run make with tools/Makefile +## Release Notes for this version +Please see [release notes](release-notes.md) for changes and bug fixes in this version of Quasar. + ### Configurations This script derives the following consistent set of include files :