Predictor Updated

2020-10-07 17:20:33 +05:00 · 2020-10-07 17:20:33 +05:00 · b5e114bfc4
parent c4b3b528f5
commit b5e114bfc4
4 changed files with 9606 additions and 8454 deletions
--- a/el2_ifu_bp_ctl.fir
+++ b/el2_ifu_bp_ctl.fir
--- a/el2_ifu_bp_ctl.v
+++ b/el2_ifu_bp_ctl.v
--- a/src/main/scala/ifu/el2_ifu_bp_ctl.scala
+++ b/src/main/scala/ifu/el2_ifu_bp_ctl.scala
@ -389,7 +389,7 @@ class el2_ifu_bp_ctl extends Module with el2_lib with RequireAsyncReset {

  val bht_bank_rd_data_out = Wire(Vec(2, Vec(BHT_ARRAY_DEPTH, UInt(2.W))))
  for(i<-0 until 2; k<-0 until BHT_ARRAY_DEPTH/NUM_BHT_LOOP; j<-0 until NUM_BHT_LOOP){
-    bht_bank_rd_data_out(i)((16*k)+j) := RegEnable(bht_bank_wr_data(i)(k)(j), 0.U, bht_bank_sel(i)(k)(j))
+    bht_bank_rd_data_out(i)((16*k)+j) := RegEnable(bht_bank_wr_data(i)(k)(j), 0.U, bht_bank_sel(i)(k)(j)&bht_bank_clken(i)(k))
  }

  bht_bank0_rd_data_f := Mux1H((0 until BHT_ARRAY_DEPTH).map(i=>(bht_rd_addr_f(BHT_ADDR_HI-BHT_ADDR_LO,0)===i.U).asBool->bht_bank_rd_data_out(0)(i)))
--- a/target/scala-2.12/classes/ifu/el2_ifu_bp_ctl.class
+++ b/target/scala-2.12/classes/ifu/el2_ifu_bp_ctl.class