colin
/
quasar
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Predictor Updated

This commit is contained in:
waleed-lm 2020-10-07 17:20:33 +05:00
parent c4b3b528f5
commit b5e114bfc4
4 changed files with 9606 additions and 8454 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12300
el2_ifu_bp_ctl.fir
View File

File diff suppressed because it is too large Load Diff

5754
el2_ifu_bp_ctl.v
View File

File diff suppressed because it is too large Load Diff

6
src/main/scala/ifu/el2_ifu_bp_ctl.scala
View File

@ -38,7 +38,7 @@ class el2_ifu_bp_ctl extends Module with el2_lib with RequireAsyncReset {
val ifu_bp_pc4_f = Output(UInt(2.W))
val ifu_bp_valid_f = Output(UInt(2.W))
val ifu_bp_poffset_f = Output(UInt(12.W))
//val test = Output(UInt())
// val test = Output(UInt())
})
val TAG_START = 16+BTB_BTAG_SIZE
@ -389,13 +389,13 @@ class el2_ifu_bp_ctl extends Module with el2_lib with RequireAsyncReset {
val bht_bank_rd_data_out = Wire(Vec(2, Vec(BHT_ARRAY_DEPTH, UInt(2.W))))
for(i<-0 until 2; k<-0 until BHT_ARRAY_DEPTH/NUM_BHT_LOOP; j<-0 until NUM_BHT_LOOP){
bht_bank_rd_data_out(i)((16*k)+j) := RegEnable(bht_bank_wr_data(i)(k)(j), 0.U, bht_bank_sel(i)(k)(j))
bht_bank_rd_data_out(i)((16*k)+j) := RegEnable(bht_bank_wr_data(i)(k)(j), 0.U, bht_bank_sel(i)(k)(j)&bht_bank_clken(i)(k))
}
bht_bank0_rd_data_f := Mux1H((0 until BHT_ARRAY_DEPTH).map(i=>(bht_rd_addr_f(BHT_ADDR_HI-BHT_ADDR_LO,0)===i.U).asBool->bht_bank_rd_data_out(0)(i)))
bht_bank1_rd_data_f := Mux1H((0 until BHT_ARRAY_DEPTH).map(i=>(bht_rd_addr_f(BHT_ADDR_HI-BHT_ADDR_LO,0)===i.U).asBool->bht_bank_rd_data_out(1)(i)))
bht_bank0_rd_data_p1_f := Mux1H((0 until BHT_ARRAY_DEPTH).map(i=>(bht_rd_addr_p1_f(BHT_ADDR_HI-BHT_ADDR_LO,0)===i.U).asBool->bht_bank_rd_data_out(1)(i)))
// io.test := bht_rd_addr_f
//io.test := bht_rd_addr_f
}
object ifu_bp extends App {

BIN
target/scala-2.12/classes/ifu/el2_ifu_bp_ctl.class
View File

Binary file not shown.