Read fixed
This commit is contained in:
waleed-lm
parent
cf4947cc71
commit
b5feb45884
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@ -111,242 +111,217 @@ circuit el2_ifu_iccm_mem :
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node _T_79 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 39:112]
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node _T_80 = mux(_T_77, _T_78, _T_79) @[el2_ifu_iccm_mem.scala 39:8]
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node addr_bank_3 = mux(_T_74, _T_75, _T_80) @[el2_ifu_iccm_mem.scala 38:55]
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cmem iccm_mem : UInt<39>[4][4096] @[el2_ifu_iccm_mem.scala 41:21]
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node _T_81 = and(iccm_clken_0, wren_bank_0) @[el2_ifu_iccm_mem.scala 43:68]
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node _T_82 = and(iccm_clken_1, wren_bank_1) @[el2_ifu_iccm_mem.scala 43:68]
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node _T_83 = and(iccm_clken_2, wren_bank_2) @[el2_ifu_iccm_mem.scala 43:68]
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node _T_84 = and(iccm_clken_3, wren_bank_3) @[el2_ifu_iccm_mem.scala 43:68]
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wire write_vec : UInt<1>[4] @[el2_ifu_iccm_mem.scala 43:51]
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write_vec[0] <= _T_81 @[el2_ifu_iccm_mem.scala 43:51]
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write_vec[1] <= _T_82 @[el2_ifu_iccm_mem.scala 43:51]
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write_vec[2] <= _T_83 @[el2_ifu_iccm_mem.scala 43:51]
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write_vec[3] <= _T_84 @[el2_ifu_iccm_mem.scala 43:51]
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node _T_85 = eq(wren_bank_0, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 44:72]
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node _T_86 = and(iccm_clken_0, _T_85) @[el2_ifu_iccm_mem.scala 44:70]
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node _T_87 = eq(wren_bank_1, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 44:72]
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node _T_88 = and(iccm_clken_1, _T_87) @[el2_ifu_iccm_mem.scala 44:70]
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node _T_89 = eq(wren_bank_2, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 44:72]
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node _T_90 = and(iccm_clken_2, _T_89) @[el2_ifu_iccm_mem.scala 44:70]
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node _T_91 = eq(wren_bank_3, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 44:72]
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node _T_92 = and(iccm_clken_3, _T_91) @[el2_ifu_iccm_mem.scala 44:70]
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wire read_enable : UInt<1>[4] @[el2_ifu_iccm_mem.scala 44:53]
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read_enable[0] <= _T_86 @[el2_ifu_iccm_mem.scala 44:53]
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read_enable[1] <= _T_88 @[el2_ifu_iccm_mem.scala 44:53]
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read_enable[2] <= _T_90 @[el2_ifu_iccm_mem.scala 44:53]
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read_enable[3] <= _T_92 @[el2_ifu_iccm_mem.scala 44:53]
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wire iccm_bank_dout : UInt<39>[4] @[el2_ifu_iccm_mem.scala 46:28]
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node _T_93 = bits(write_vec[0], 0, 0) @[el2_ifu_iccm_mem.scala 49:53]
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when _T_93 : @[el2_ifu_iccm_mem.scala 49:60]
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infer mport _T_94 = iccm_mem[addr_bank_0], clock @[el2_ifu_iccm_mem.scala 49:69]
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_T_94[0] <= iccm_bank_wr_data[0] @[el2_ifu_iccm_mem.scala 49:87]
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skip @[el2_ifu_iccm_mem.scala 49:60]
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node _T_95 = bits(write_vec[1], 0, 0) @[el2_ifu_iccm_mem.scala 49:53]
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when _T_95 : @[el2_ifu_iccm_mem.scala 49:60]
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infer mport _T_96 = iccm_mem[addr_bank_1], clock @[el2_ifu_iccm_mem.scala 49:69]
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_T_96[1] <= iccm_bank_wr_data[1] @[el2_ifu_iccm_mem.scala 49:87]
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skip @[el2_ifu_iccm_mem.scala 49:60]
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node _T_97 = bits(write_vec[2], 0, 0) @[el2_ifu_iccm_mem.scala 49:53]
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when _T_97 : @[el2_ifu_iccm_mem.scala 49:60]
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infer mport _T_98 = iccm_mem[addr_bank_2], clock @[el2_ifu_iccm_mem.scala 49:69]
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_T_98[2] <= iccm_bank_wr_data[2] @[el2_ifu_iccm_mem.scala 49:87]
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skip @[el2_ifu_iccm_mem.scala 49:60]
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node _T_99 = bits(write_vec[3], 0, 0) @[el2_ifu_iccm_mem.scala 49:53]
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when _T_99 : @[el2_ifu_iccm_mem.scala 49:60]
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infer mport _T_100 = iccm_mem[addr_bank_3], clock @[el2_ifu_iccm_mem.scala 49:69]
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_T_100[3] <= iccm_bank_wr_data[3] @[el2_ifu_iccm_mem.scala 49:87]
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skip @[el2_ifu_iccm_mem.scala 49:60]
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infer mport _T_101 = iccm_mem[addr_bank_0], clock @[el2_ifu_iccm_mem.scala 51:68]
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reg _T_102 : UInt<39>[4], clock @[el2_ifu_iccm_mem.scala 51:59]
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_T_102[0] <= _T_101[0] @[el2_ifu_iccm_mem.scala 51:59]
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_T_102[1] <= _T_101[1] @[el2_ifu_iccm_mem.scala 51:59]
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_T_102[2] <= _T_101[2] @[el2_ifu_iccm_mem.scala 51:59]
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_T_102[3] <= _T_101[3] @[el2_ifu_iccm_mem.scala 51:59]
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iccm_bank_dout[0] <= _T_102[0] @[el2_ifu_iccm_mem.scala 51:49]
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iccm_bank_dout[1] <= _T_102[1] @[el2_ifu_iccm_mem.scala 51:49]
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iccm_bank_dout[2] <= _T_102[2] @[el2_ifu_iccm_mem.scala 51:49]
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iccm_bank_dout[3] <= _T_102[3] @[el2_ifu_iccm_mem.scala 51:49]
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infer mport _T_103 = iccm_mem[addr_bank_1], clock @[el2_ifu_iccm_mem.scala 51:68]
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reg _T_104 : UInt<39>[4], clock @[el2_ifu_iccm_mem.scala 51:59]
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_T_104[0] <= _T_103[0] @[el2_ifu_iccm_mem.scala 51:59]
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_T_104[1] <= _T_103[1] @[el2_ifu_iccm_mem.scala 51:59]
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_T_104[2] <= _T_103[2] @[el2_ifu_iccm_mem.scala 51:59]
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_T_104[3] <= _T_103[3] @[el2_ifu_iccm_mem.scala 51:59]
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iccm_bank_dout[0] <= _T_104[0] @[el2_ifu_iccm_mem.scala 51:49]
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iccm_bank_dout[1] <= _T_104[1] @[el2_ifu_iccm_mem.scala 51:49]
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iccm_bank_dout[2] <= _T_104[2] @[el2_ifu_iccm_mem.scala 51:49]
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iccm_bank_dout[3] <= _T_104[3] @[el2_ifu_iccm_mem.scala 51:49]
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infer mport _T_105 = iccm_mem[addr_bank_2], clock @[el2_ifu_iccm_mem.scala 51:68]
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reg _T_106 : UInt<39>[4], clock @[el2_ifu_iccm_mem.scala 51:59]
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_T_106[0] <= _T_105[0] @[el2_ifu_iccm_mem.scala 51:59]
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_T_106[1] <= _T_105[1] @[el2_ifu_iccm_mem.scala 51:59]
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_T_106[2] <= _T_105[2] @[el2_ifu_iccm_mem.scala 51:59]
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_T_106[3] <= _T_105[3] @[el2_ifu_iccm_mem.scala 51:59]
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iccm_bank_dout[0] <= _T_106[0] @[el2_ifu_iccm_mem.scala 51:49]
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iccm_bank_dout[1] <= _T_106[1] @[el2_ifu_iccm_mem.scala 51:49]
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iccm_bank_dout[2] <= _T_106[2] @[el2_ifu_iccm_mem.scala 51:49]
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iccm_bank_dout[3] <= _T_106[3] @[el2_ifu_iccm_mem.scala 51:49]
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infer mport _T_107 = iccm_mem[addr_bank_3], clock @[el2_ifu_iccm_mem.scala 51:68]
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reg _T_108 : UInt<39>[4], clock @[el2_ifu_iccm_mem.scala 51:59]
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_T_108[0] <= _T_107[0] @[el2_ifu_iccm_mem.scala 51:59]
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_T_108[1] <= _T_107[1] @[el2_ifu_iccm_mem.scala 51:59]
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_T_108[2] <= _T_107[2] @[el2_ifu_iccm_mem.scala 51:59]
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_T_108[3] <= _T_107[3] @[el2_ifu_iccm_mem.scala 51:59]
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iccm_bank_dout[0] <= _T_108[0] @[el2_ifu_iccm_mem.scala 51:49]
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iccm_bank_dout[1] <= _T_108[1] @[el2_ifu_iccm_mem.scala 51:49]
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iccm_bank_dout[2] <= _T_108[2] @[el2_ifu_iccm_mem.scala 51:49]
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iccm_bank_dout[3] <= _T_108[3] @[el2_ifu_iccm_mem.scala 51:49]
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io.iccm_bank_addr[0] <= addr_bank_0 @[el2_ifu_iccm_mem.scala 56:21]
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io.iccm_bank_addr[1] <= addr_bank_1 @[el2_ifu_iccm_mem.scala 56:21]
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io.iccm_bank_addr[2] <= addr_bank_2 @[el2_ifu_iccm_mem.scala 56:21]
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io.iccm_bank_addr[3] <= addr_bank_3 @[el2_ifu_iccm_mem.scala 56:21]
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cmem _T_81 : UInt<39>[4096] @[el2_ifu_iccm_mem.scala 42:51]
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cmem _T_82 : UInt<39>[4096] @[el2_ifu_iccm_mem.scala 42:51]
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cmem _T_83 : UInt<39>[4096] @[el2_ifu_iccm_mem.scala 42:51]
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cmem _T_84 : UInt<39>[4096] @[el2_ifu_iccm_mem.scala 42:51]
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node _T_85 = and(iccm_clken_0, wren_bank_0) @[el2_ifu_iccm_mem.scala 46:68]
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node _T_86 = and(iccm_clken_1, wren_bank_1) @[el2_ifu_iccm_mem.scala 46:68]
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node _T_87 = and(iccm_clken_2, wren_bank_2) @[el2_ifu_iccm_mem.scala 46:68]
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node _T_88 = and(iccm_clken_3, wren_bank_3) @[el2_ifu_iccm_mem.scala 46:68]
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wire write_vec : UInt<1>[4] @[el2_ifu_iccm_mem.scala 46:51]
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write_vec[0] <= _T_85 @[el2_ifu_iccm_mem.scala 46:51]
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write_vec[1] <= _T_86 @[el2_ifu_iccm_mem.scala 46:51]
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write_vec[2] <= _T_87 @[el2_ifu_iccm_mem.scala 46:51]
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write_vec[3] <= _T_88 @[el2_ifu_iccm_mem.scala 46:51]
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node _T_89 = eq(wren_bank_0, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 47:72]
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node _T_90 = and(iccm_clken_0, _T_89) @[el2_ifu_iccm_mem.scala 47:70]
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node _T_91 = eq(wren_bank_1, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 47:72]
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node _T_92 = and(iccm_clken_1, _T_91) @[el2_ifu_iccm_mem.scala 47:70]
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node _T_93 = eq(wren_bank_2, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 47:72]
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node _T_94 = and(iccm_clken_2, _T_93) @[el2_ifu_iccm_mem.scala 47:70]
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node _T_95 = eq(wren_bank_3, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 47:72]
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node _T_96 = and(iccm_clken_3, _T_95) @[el2_ifu_iccm_mem.scala 47:70]
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wire read_enable : UInt<1>[4] @[el2_ifu_iccm_mem.scala 47:53]
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read_enable[0] <= _T_90 @[el2_ifu_iccm_mem.scala 47:53]
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read_enable[1] <= _T_92 @[el2_ifu_iccm_mem.scala 47:53]
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read_enable[2] <= _T_94 @[el2_ifu_iccm_mem.scala 47:53]
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read_enable[3] <= _T_96 @[el2_ifu_iccm_mem.scala 47:53]
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wire iccm_bank_dout : UInt<39>[4] @[el2_ifu_iccm_mem.scala 49:28]
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when write_vec[0] : @[el2_ifu_iccm_mem.scala 53:54]
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infer mport _T_97 = _T_81[addr_bank_0], clock @[el2_ifu_iccm_mem.scala 53:66]
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_T_97 <= iccm_bank_wr_data[0] @[el2_ifu_iccm_mem.scala 53:81]
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skip @[el2_ifu_iccm_mem.scala 53:54]
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when write_vec[1] : @[el2_ifu_iccm_mem.scala 53:54]
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infer mport _T_98 = _T_82[addr_bank_1], clock @[el2_ifu_iccm_mem.scala 53:66]
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_T_98 <= iccm_bank_wr_data[1] @[el2_ifu_iccm_mem.scala 53:81]
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skip @[el2_ifu_iccm_mem.scala 53:54]
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when write_vec[2] : @[el2_ifu_iccm_mem.scala 53:54]
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infer mport _T_99 = _T_83[addr_bank_2], clock @[el2_ifu_iccm_mem.scala 53:66]
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_T_99 <= iccm_bank_wr_data[2] @[el2_ifu_iccm_mem.scala 53:81]
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skip @[el2_ifu_iccm_mem.scala 53:54]
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when write_vec[3] : @[el2_ifu_iccm_mem.scala 53:54]
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infer mport _T_100 = _T_84[addr_bank_3], clock @[el2_ifu_iccm_mem.scala 53:66]
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_T_100 <= iccm_bank_wr_data[3] @[el2_ifu_iccm_mem.scala 53:81]
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skip @[el2_ifu_iccm_mem.scala 53:54]
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read mport _T_101 = _T_81[addr_bank_0], clock @[el2_ifu_iccm_mem.scala 55:80]
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reg _T_102 : UInt, clock @[el2_ifu_iccm_mem.scala 55:63]
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_T_102 <= _T_101 @[el2_ifu_iccm_mem.scala 55:63]
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iccm_bank_dout[0] <= _T_102 @[el2_ifu_iccm_mem.scala 55:53]
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read mport _T_103 = _T_82[addr_bank_1], clock @[el2_ifu_iccm_mem.scala 55:80]
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reg _T_104 : UInt, clock @[el2_ifu_iccm_mem.scala 55:63]
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_T_104 <= _T_103 @[el2_ifu_iccm_mem.scala 55:63]
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iccm_bank_dout[1] <= _T_104 @[el2_ifu_iccm_mem.scala 55:53]
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read mport _T_105 = _T_83[addr_bank_2], clock @[el2_ifu_iccm_mem.scala 55:80]
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reg _T_106 : UInt, clock @[el2_ifu_iccm_mem.scala 55:63]
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_T_106 <= _T_105 @[el2_ifu_iccm_mem.scala 55:63]
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iccm_bank_dout[2] <= _T_106 @[el2_ifu_iccm_mem.scala 55:53]
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read mport _T_107 = _T_84[addr_bank_3], clock @[el2_ifu_iccm_mem.scala 55:80]
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reg _T_108 : UInt, clock @[el2_ifu_iccm_mem.scala 55:63]
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_T_108 <= _T_107 @[el2_ifu_iccm_mem.scala 55:63]
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iccm_bank_dout[3] <= _T_108 @[el2_ifu_iccm_mem.scala 55:53]
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io.iccm_bank_addr[0] <= addr_bank_0 @[el2_ifu_iccm_mem.scala 60:21]
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io.iccm_bank_addr[1] <= addr_bank_1 @[el2_ifu_iccm_mem.scala 60:21]
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io.iccm_bank_addr[2] <= addr_bank_2 @[el2_ifu_iccm_mem.scala 60:21]
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io.iccm_bank_addr[3] <= addr_bank_3 @[el2_ifu_iccm_mem.scala 60:21]
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wire redundant_valid : UInt<2>
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redundant_valid <= UInt<1>("h00")
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wire redundant_address : UInt<14>[2] @[el2_ifu_iccm_mem.scala 62:31]
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redundant_address[0] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 63:21]
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redundant_address[1] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 63:21]
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node _T_109 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 65:67]
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node _T_110 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 65:90]
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node _T_111 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 65:128]
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node _T_112 = eq(_T_110, _T_111) @[el2_ifu_iccm_mem.scala 65:105]
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node _T_113 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 65:163]
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node _T_114 = eq(_T_113, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 65:169]
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node _T_115 = and(_T_112, _T_114) @[el2_ifu_iccm_mem.scala 65:145]
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node _T_116 = and(_T_109, _T_115) @[el2_ifu_iccm_mem.scala 65:71]
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node _T_117 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 66:22]
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node _T_118 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 66:60]
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node _T_119 = eq(_T_117, _T_118) @[el2_ifu_iccm_mem.scala 66:37]
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node _T_120 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 66:93]
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node _T_121 = eq(_T_120, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 66:99]
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node _T_122 = and(_T_119, _T_121) @[el2_ifu_iccm_mem.scala 66:77]
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node _T_123 = or(_T_116, _T_122) @[el2_ifu_iccm_mem.scala 65:179]
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node _T_124 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 65:67]
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node _T_125 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 65:90]
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node _T_126 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 65:128]
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node _T_127 = eq(_T_125, _T_126) @[el2_ifu_iccm_mem.scala 65:105]
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node _T_128 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 65:163]
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node _T_129 = eq(_T_128, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 65:169]
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node _T_130 = and(_T_127, _T_129) @[el2_ifu_iccm_mem.scala 65:145]
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node _T_131 = and(_T_124, _T_130) @[el2_ifu_iccm_mem.scala 65:71]
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node _T_132 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 66:22]
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node _T_133 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 66:60]
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node _T_134 = eq(_T_132, _T_133) @[el2_ifu_iccm_mem.scala 66:37]
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node _T_135 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 66:93]
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node _T_136 = eq(_T_135, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 66:99]
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node _T_137 = and(_T_134, _T_136) @[el2_ifu_iccm_mem.scala 66:77]
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node _T_138 = or(_T_131, _T_137) @[el2_ifu_iccm_mem.scala 65:179]
|
||||
node _T_139 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 65:67]
|
||||
node _T_140 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 65:90]
|
||||
node _T_141 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 65:128]
|
||||
node _T_142 = eq(_T_140, _T_141) @[el2_ifu_iccm_mem.scala 65:105]
|
||||
node _T_143 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 65:163]
|
||||
node _T_144 = eq(_T_143, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 65:169]
|
||||
node _T_145 = and(_T_142, _T_144) @[el2_ifu_iccm_mem.scala 65:145]
|
||||
node _T_146 = and(_T_139, _T_145) @[el2_ifu_iccm_mem.scala 65:71]
|
||||
node _T_147 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 66:22]
|
||||
node _T_148 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 66:60]
|
||||
node _T_149 = eq(_T_147, _T_148) @[el2_ifu_iccm_mem.scala 66:37]
|
||||
node _T_150 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 66:93]
|
||||
node _T_151 = eq(_T_150, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 66:99]
|
||||
node _T_152 = and(_T_149, _T_151) @[el2_ifu_iccm_mem.scala 66:77]
|
||||
node _T_153 = or(_T_146, _T_152) @[el2_ifu_iccm_mem.scala 65:179]
|
||||
node _T_154 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 65:67]
|
||||
node _T_155 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 65:90]
|
||||
node _T_156 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 65:128]
|
||||
node _T_157 = eq(_T_155, _T_156) @[el2_ifu_iccm_mem.scala 65:105]
|
||||
node _T_158 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 65:163]
|
||||
node _T_159 = eq(_T_158, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 65:169]
|
||||
node _T_160 = and(_T_157, _T_159) @[el2_ifu_iccm_mem.scala 65:145]
|
||||
node _T_161 = and(_T_154, _T_160) @[el2_ifu_iccm_mem.scala 65:71]
|
||||
node _T_162 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 66:22]
|
||||
node _T_163 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 66:60]
|
||||
node _T_164 = eq(_T_162, _T_163) @[el2_ifu_iccm_mem.scala 66:37]
|
||||
node _T_165 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 66:93]
|
||||
node _T_166 = eq(_T_165, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 66:99]
|
||||
node _T_167 = and(_T_164, _T_166) @[el2_ifu_iccm_mem.scala 66:77]
|
||||
node _T_168 = or(_T_161, _T_167) @[el2_ifu_iccm_mem.scala 65:179]
|
||||
wire redundant_address : UInt<14>[2] @[el2_ifu_iccm_mem.scala 66:31]
|
||||
redundant_address[0] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 67:21]
|
||||
redundant_address[1] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 67:21]
|
||||
node _T_109 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 69:67]
|
||||
node _T_110 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 69:90]
|
||||
node _T_111 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 69:128]
|
||||
node _T_112 = eq(_T_110, _T_111) @[el2_ifu_iccm_mem.scala 69:105]
|
||||
node _T_113 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 69:163]
|
||||
node _T_114 = eq(_T_113, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 69:169]
|
||||
node _T_115 = and(_T_112, _T_114) @[el2_ifu_iccm_mem.scala 69:145]
|
||||
node _T_116 = and(_T_109, _T_115) @[el2_ifu_iccm_mem.scala 69:71]
|
||||
node _T_117 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 70:22]
|
||||
node _T_118 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 70:60]
|
||||
node _T_119 = eq(_T_117, _T_118) @[el2_ifu_iccm_mem.scala 70:37]
|
||||
node _T_120 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 70:93]
|
||||
node _T_121 = eq(_T_120, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 70:99]
|
||||
node _T_122 = and(_T_119, _T_121) @[el2_ifu_iccm_mem.scala 70:77]
|
||||
node _T_123 = or(_T_116, _T_122) @[el2_ifu_iccm_mem.scala 69:179]
|
||||
node _T_124 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 69:67]
|
||||
node _T_125 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 69:90]
|
||||
node _T_126 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 69:128]
|
||||
node _T_127 = eq(_T_125, _T_126) @[el2_ifu_iccm_mem.scala 69:105]
|
||||
node _T_128 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 69:163]
|
||||
node _T_129 = eq(_T_128, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 69:169]
|
||||
node _T_130 = and(_T_127, _T_129) @[el2_ifu_iccm_mem.scala 69:145]
|
||||
node _T_131 = and(_T_124, _T_130) @[el2_ifu_iccm_mem.scala 69:71]
|
||||
node _T_132 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 70:22]
|
||||
node _T_133 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 70:60]
|
||||
node _T_134 = eq(_T_132, _T_133) @[el2_ifu_iccm_mem.scala 70:37]
|
||||
node _T_135 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 70:93]
|
||||
node _T_136 = eq(_T_135, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 70:99]
|
||||
node _T_137 = and(_T_134, _T_136) @[el2_ifu_iccm_mem.scala 70:77]
|
||||
node _T_138 = or(_T_131, _T_137) @[el2_ifu_iccm_mem.scala 69:179]
|
||||
node _T_139 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 69:67]
|
||||
node _T_140 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 69:90]
|
||||
node _T_141 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 69:128]
|
||||
node _T_142 = eq(_T_140, _T_141) @[el2_ifu_iccm_mem.scala 69:105]
|
||||
node _T_143 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 69:163]
|
||||
node _T_144 = eq(_T_143, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 69:169]
|
||||
node _T_145 = and(_T_142, _T_144) @[el2_ifu_iccm_mem.scala 69:145]
|
||||
node _T_146 = and(_T_139, _T_145) @[el2_ifu_iccm_mem.scala 69:71]
|
||||
node _T_147 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 70:22]
|
||||
node _T_148 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 70:60]
|
||||
node _T_149 = eq(_T_147, _T_148) @[el2_ifu_iccm_mem.scala 70:37]
|
||||
node _T_150 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 70:93]
|
||||
node _T_151 = eq(_T_150, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 70:99]
|
||||
node _T_152 = and(_T_149, _T_151) @[el2_ifu_iccm_mem.scala 70:77]
|
||||
node _T_153 = or(_T_146, _T_152) @[el2_ifu_iccm_mem.scala 69:179]
|
||||
node _T_154 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 69:67]
|
||||
node _T_155 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 69:90]
|
||||
node _T_156 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 69:128]
|
||||
node _T_157 = eq(_T_155, _T_156) @[el2_ifu_iccm_mem.scala 69:105]
|
||||
node _T_158 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 69:163]
|
||||
node _T_159 = eq(_T_158, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 69:169]
|
||||
node _T_160 = and(_T_157, _T_159) @[el2_ifu_iccm_mem.scala 69:145]
|
||||
node _T_161 = and(_T_154, _T_160) @[el2_ifu_iccm_mem.scala 69:71]
|
||||
node _T_162 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 70:22]
|
||||
node _T_163 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 70:60]
|
||||
node _T_164 = eq(_T_162, _T_163) @[el2_ifu_iccm_mem.scala 70:37]
|
||||
node _T_165 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 70:93]
|
||||
node _T_166 = eq(_T_165, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 70:99]
|
||||
node _T_167 = and(_T_164, _T_166) @[el2_ifu_iccm_mem.scala 70:77]
|
||||
node _T_168 = or(_T_161, _T_167) @[el2_ifu_iccm_mem.scala 69:179]
|
||||
node _T_169 = cat(_T_168, _T_153) @[Cat.scala 29:58]
|
||||
node _T_170 = cat(_T_169, _T_138) @[Cat.scala 29:58]
|
||||
node sel_red1 = cat(_T_170, _T_123) @[Cat.scala 29:58]
|
||||
node _T_171 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 67:67]
|
||||
node _T_172 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 67:90]
|
||||
node _T_173 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 67:128]
|
||||
node _T_174 = eq(_T_172, _T_173) @[el2_ifu_iccm_mem.scala 67:105]
|
||||
node _T_175 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 67:163]
|
||||
node _T_176 = eq(_T_175, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 67:169]
|
||||
node _T_177 = and(_T_174, _T_176) @[el2_ifu_iccm_mem.scala 67:145]
|
||||
node _T_178 = and(_T_171, _T_177) @[el2_ifu_iccm_mem.scala 67:71]
|
||||
node _T_179 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 68:22]
|
||||
node _T_180 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 68:60]
|
||||
node _T_181 = eq(_T_179, _T_180) @[el2_ifu_iccm_mem.scala 68:37]
|
||||
node _T_182 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 68:93]
|
||||
node _T_183 = eq(_T_182, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 68:99]
|
||||
node _T_184 = and(_T_181, _T_183) @[el2_ifu_iccm_mem.scala 68:77]
|
||||
node _T_185 = or(_T_178, _T_184) @[el2_ifu_iccm_mem.scala 67:179]
|
||||
node _T_186 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 67:67]
|
||||
node _T_187 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 67:90]
|
||||
node _T_188 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 67:128]
|
||||
node _T_189 = eq(_T_187, _T_188) @[el2_ifu_iccm_mem.scala 67:105]
|
||||
node _T_190 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 67:163]
|
||||
node _T_191 = eq(_T_190, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 67:169]
|
||||
node _T_192 = and(_T_189, _T_191) @[el2_ifu_iccm_mem.scala 67:145]
|
||||
node _T_193 = and(_T_186, _T_192) @[el2_ifu_iccm_mem.scala 67:71]
|
||||
node _T_194 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 68:22]
|
||||
node _T_195 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 68:60]
|
||||
node _T_196 = eq(_T_194, _T_195) @[el2_ifu_iccm_mem.scala 68:37]
|
||||
node _T_197 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 68:93]
|
||||
node _T_198 = eq(_T_197, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 68:99]
|
||||
node _T_199 = and(_T_196, _T_198) @[el2_ifu_iccm_mem.scala 68:77]
|
||||
node _T_200 = or(_T_193, _T_199) @[el2_ifu_iccm_mem.scala 67:179]
|
||||
node _T_201 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 67:67]
|
||||
node _T_202 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 67:90]
|
||||
node _T_203 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 67:128]
|
||||
node _T_204 = eq(_T_202, _T_203) @[el2_ifu_iccm_mem.scala 67:105]
|
||||
node _T_205 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 67:163]
|
||||
node _T_206 = eq(_T_205, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 67:169]
|
||||
node _T_207 = and(_T_204, _T_206) @[el2_ifu_iccm_mem.scala 67:145]
|
||||
node _T_208 = and(_T_201, _T_207) @[el2_ifu_iccm_mem.scala 67:71]
|
||||
node _T_209 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 68:22]
|
||||
node _T_210 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 68:60]
|
||||
node _T_211 = eq(_T_209, _T_210) @[el2_ifu_iccm_mem.scala 68:37]
|
||||
node _T_212 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 68:93]
|
||||
node _T_213 = eq(_T_212, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 68:99]
|
||||
node _T_214 = and(_T_211, _T_213) @[el2_ifu_iccm_mem.scala 68:77]
|
||||
node _T_215 = or(_T_208, _T_214) @[el2_ifu_iccm_mem.scala 67:179]
|
||||
node _T_216 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 67:67]
|
||||
node _T_217 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 67:90]
|
||||
node _T_218 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 67:128]
|
||||
node _T_219 = eq(_T_217, _T_218) @[el2_ifu_iccm_mem.scala 67:105]
|
||||
node _T_220 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 67:163]
|
||||
node _T_221 = eq(_T_220, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 67:169]
|
||||
node _T_222 = and(_T_219, _T_221) @[el2_ifu_iccm_mem.scala 67:145]
|
||||
node _T_223 = and(_T_216, _T_222) @[el2_ifu_iccm_mem.scala 67:71]
|
||||
node _T_224 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 68:22]
|
||||
node _T_225 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 68:60]
|
||||
node _T_226 = eq(_T_224, _T_225) @[el2_ifu_iccm_mem.scala 68:37]
|
||||
node _T_227 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 68:93]
|
||||
node _T_228 = eq(_T_227, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 68:99]
|
||||
node _T_229 = and(_T_226, _T_228) @[el2_ifu_iccm_mem.scala 68:77]
|
||||
node _T_230 = or(_T_223, _T_229) @[el2_ifu_iccm_mem.scala 67:179]
|
||||
node _T_171 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 71:67]
|
||||
node _T_172 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 71:90]
|
||||
node _T_173 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 71:128]
|
||||
node _T_174 = eq(_T_172, _T_173) @[el2_ifu_iccm_mem.scala 71:105]
|
||||
node _T_175 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 71:163]
|
||||
node _T_176 = eq(_T_175, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 71:169]
|
||||
node _T_177 = and(_T_174, _T_176) @[el2_ifu_iccm_mem.scala 71:145]
|
||||
node _T_178 = and(_T_171, _T_177) @[el2_ifu_iccm_mem.scala 71:71]
|
||||
node _T_179 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 72:22]
|
||||
node _T_180 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 72:60]
|
||||
node _T_181 = eq(_T_179, _T_180) @[el2_ifu_iccm_mem.scala 72:37]
|
||||
node _T_182 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 72:93]
|
||||
node _T_183 = eq(_T_182, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 72:99]
|
||||
node _T_184 = and(_T_181, _T_183) @[el2_ifu_iccm_mem.scala 72:77]
|
||||
node _T_185 = or(_T_178, _T_184) @[el2_ifu_iccm_mem.scala 71:179]
|
||||
node _T_186 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 71:67]
|
||||
node _T_187 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 71:90]
|
||||
node _T_188 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 71:128]
|
||||
node _T_189 = eq(_T_187, _T_188) @[el2_ifu_iccm_mem.scala 71:105]
|
||||
node _T_190 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 71:163]
|
||||
node _T_191 = eq(_T_190, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 71:169]
|
||||
node _T_192 = and(_T_189, _T_191) @[el2_ifu_iccm_mem.scala 71:145]
|
||||
node _T_193 = and(_T_186, _T_192) @[el2_ifu_iccm_mem.scala 71:71]
|
||||
node _T_194 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 72:22]
|
||||
node _T_195 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 72:60]
|
||||
node _T_196 = eq(_T_194, _T_195) @[el2_ifu_iccm_mem.scala 72:37]
|
||||
node _T_197 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 72:93]
|
||||
node _T_198 = eq(_T_197, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 72:99]
|
||||
node _T_199 = and(_T_196, _T_198) @[el2_ifu_iccm_mem.scala 72:77]
|
||||
node _T_200 = or(_T_193, _T_199) @[el2_ifu_iccm_mem.scala 71:179]
|
||||
node _T_201 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 71:67]
|
||||
node _T_202 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 71:90]
|
||||
node _T_203 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 71:128]
|
||||
node _T_204 = eq(_T_202, _T_203) @[el2_ifu_iccm_mem.scala 71:105]
|
||||
node _T_205 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 71:163]
|
||||
node _T_206 = eq(_T_205, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 71:169]
|
||||
node _T_207 = and(_T_204, _T_206) @[el2_ifu_iccm_mem.scala 71:145]
|
||||
node _T_208 = and(_T_201, _T_207) @[el2_ifu_iccm_mem.scala 71:71]
|
||||
node _T_209 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 72:22]
|
||||
node _T_210 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 72:60]
|
||||
node _T_211 = eq(_T_209, _T_210) @[el2_ifu_iccm_mem.scala 72:37]
|
||||
node _T_212 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 72:93]
|
||||
node _T_213 = eq(_T_212, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 72:99]
|
||||
node _T_214 = and(_T_211, _T_213) @[el2_ifu_iccm_mem.scala 72:77]
|
||||
node _T_215 = or(_T_208, _T_214) @[el2_ifu_iccm_mem.scala 71:179]
|
||||
node _T_216 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 71:67]
|
||||
node _T_217 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 71:90]
|
||||
node _T_218 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 71:128]
|
||||
node _T_219 = eq(_T_217, _T_218) @[el2_ifu_iccm_mem.scala 71:105]
|
||||
node _T_220 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 71:163]
|
||||
node _T_221 = eq(_T_220, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 71:169]
|
||||
node _T_222 = and(_T_219, _T_221) @[el2_ifu_iccm_mem.scala 71:145]
|
||||
node _T_223 = and(_T_216, _T_222) @[el2_ifu_iccm_mem.scala 71:71]
|
||||
node _T_224 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 72:22]
|
||||
node _T_225 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 72:60]
|
||||
node _T_226 = eq(_T_224, _T_225) @[el2_ifu_iccm_mem.scala 72:37]
|
||||
node _T_227 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 72:93]
|
||||
node _T_228 = eq(_T_227, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 72:99]
|
||||
node _T_229 = and(_T_226, _T_228) @[el2_ifu_iccm_mem.scala 72:77]
|
||||
node _T_230 = or(_T_223, _T_229) @[el2_ifu_iccm_mem.scala 71:179]
|
||||
node _T_231 = cat(_T_230, _T_215) @[Cat.scala 29:58]
|
||||
node _T_232 = cat(_T_231, _T_200) @[Cat.scala 29:58]
|
||||
node sel_red0 = cat(_T_232, _T_185) @[Cat.scala 29:58]
|
||||
reg sel_red0_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 70:27]
|
||||
sel_red0_q <= sel_red0 @[el2_ifu_iccm_mem.scala 70:27]
|
||||
reg sel_red1_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 71:27]
|
||||
sel_red1_q <= sel_red1 @[el2_ifu_iccm_mem.scala 71:27]
|
||||
wire redundant_data : UInt<39>[2] @[el2_ifu_iccm_mem.scala 72:28]
|
||||
redundant_data[0] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 73:18]
|
||||
redundant_data[1] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 73:18]
|
||||
node _T_233 = bits(sel_red1_q, 0, 0) @[el2_ifu_iccm_mem.scala 75:47]
|
||||
node _T_234 = bits(_T_233, 0, 0) @[el2_ifu_iccm_mem.scala 75:51]
|
||||
node _T_235 = bits(sel_red0_q, 0, 0) @[el2_ifu_iccm_mem.scala 76:47]
|
||||
node _T_236 = bits(_T_235, 0, 0) @[el2_ifu_iccm_mem.scala 76:51]
|
||||
node _T_237 = bits(sel_red0_q, 0, 0) @[el2_ifu_iccm_mem.scala 77:47]
|
||||
node _T_238 = not(_T_237) @[el2_ifu_iccm_mem.scala 77:36]
|
||||
node _T_239 = bits(sel_red1_q, 0, 0) @[el2_ifu_iccm_mem.scala 77:64]
|
||||
node _T_240 = not(_T_239) @[el2_ifu_iccm_mem.scala 77:53]
|
||||
node _T_241 = and(_T_238, _T_240) @[el2_ifu_iccm_mem.scala 77:51]
|
||||
node _T_242 = bits(_T_241, 0, 0) @[el2_ifu_iccm_mem.scala 77:69]
|
||||
reg sel_red0_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 74:27]
|
||||
sel_red0_q <= sel_red0 @[el2_ifu_iccm_mem.scala 74:27]
|
||||
reg sel_red1_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 75:27]
|
||||
sel_red1_q <= sel_red1 @[el2_ifu_iccm_mem.scala 75:27]
|
||||
wire redundant_data : UInt<39>[2] @[el2_ifu_iccm_mem.scala 76:28]
|
||||
redundant_data[0] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 77:18]
|
||||
redundant_data[1] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 77:18]
|
||||
node _T_233 = bits(sel_red1_q, 0, 0) @[el2_ifu_iccm_mem.scala 79:47]
|
||||
node _T_234 = bits(_T_233, 0, 0) @[el2_ifu_iccm_mem.scala 79:51]
|
||||
node _T_235 = bits(sel_red0_q, 0, 0) @[el2_ifu_iccm_mem.scala 80:47]
|
||||
node _T_236 = bits(_T_235, 0, 0) @[el2_ifu_iccm_mem.scala 80:51]
|
||||
node _T_237 = bits(sel_red0_q, 0, 0) @[el2_ifu_iccm_mem.scala 81:47]
|
||||
node _T_238 = not(_T_237) @[el2_ifu_iccm_mem.scala 81:36]
|
||||
node _T_239 = bits(sel_red1_q, 0, 0) @[el2_ifu_iccm_mem.scala 81:64]
|
||||
node _T_240 = not(_T_239) @[el2_ifu_iccm_mem.scala 81:53]
|
||||
node _T_241 = and(_T_238, _T_240) @[el2_ifu_iccm_mem.scala 81:51]
|
||||
node _T_242 = bits(_T_241, 0, 0) @[el2_ifu_iccm_mem.scala 81:69]
|
||||
node _T_243 = mux(_T_234, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_244 = mux(_T_236, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_245 = mux(_T_242, iccm_bank_dout[0], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
|
|
@ -354,16 +329,16 @@ circuit el2_ifu_iccm_mem :
|
|||
node _T_247 = or(_T_246, _T_245) @[Mux.scala 27:72]
|
||||
wire iccm_bank_dout_fn_0 : UInt<39> @[Mux.scala 27:72]
|
||||
iccm_bank_dout_fn_0 <= _T_247 @[Mux.scala 27:72]
|
||||
node _T_248 = bits(sel_red1_q, 1, 1) @[el2_ifu_iccm_mem.scala 75:47]
|
||||
node _T_249 = bits(_T_248, 0, 0) @[el2_ifu_iccm_mem.scala 75:51]
|
||||
node _T_250 = bits(sel_red0_q, 1, 1) @[el2_ifu_iccm_mem.scala 76:47]
|
||||
node _T_251 = bits(_T_250, 0, 0) @[el2_ifu_iccm_mem.scala 76:51]
|
||||
node _T_252 = bits(sel_red0_q, 1, 1) @[el2_ifu_iccm_mem.scala 77:47]
|
||||
node _T_253 = not(_T_252) @[el2_ifu_iccm_mem.scala 77:36]
|
||||
node _T_254 = bits(sel_red1_q, 1, 1) @[el2_ifu_iccm_mem.scala 77:64]
|
||||
node _T_255 = not(_T_254) @[el2_ifu_iccm_mem.scala 77:53]
|
||||
node _T_256 = and(_T_253, _T_255) @[el2_ifu_iccm_mem.scala 77:51]
|
||||
node _T_257 = bits(_T_256, 0, 0) @[el2_ifu_iccm_mem.scala 77:69]
|
||||
node _T_248 = bits(sel_red1_q, 1, 1) @[el2_ifu_iccm_mem.scala 79:47]
|
||||
node _T_249 = bits(_T_248, 0, 0) @[el2_ifu_iccm_mem.scala 79:51]
|
||||
node _T_250 = bits(sel_red0_q, 1, 1) @[el2_ifu_iccm_mem.scala 80:47]
|
||||
node _T_251 = bits(_T_250, 0, 0) @[el2_ifu_iccm_mem.scala 80:51]
|
||||
node _T_252 = bits(sel_red0_q, 1, 1) @[el2_ifu_iccm_mem.scala 81:47]
|
||||
node _T_253 = not(_T_252) @[el2_ifu_iccm_mem.scala 81:36]
|
||||
node _T_254 = bits(sel_red1_q, 1, 1) @[el2_ifu_iccm_mem.scala 81:64]
|
||||
node _T_255 = not(_T_254) @[el2_ifu_iccm_mem.scala 81:53]
|
||||
node _T_256 = and(_T_253, _T_255) @[el2_ifu_iccm_mem.scala 81:51]
|
||||
node _T_257 = bits(_T_256, 0, 0) @[el2_ifu_iccm_mem.scala 81:69]
|
||||
node _T_258 = mux(_T_249, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_259 = mux(_T_251, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_260 = mux(_T_257, iccm_bank_dout[1], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
|
|
@ -371,16 +346,16 @@ circuit el2_ifu_iccm_mem :
|
|||
node _T_262 = or(_T_261, _T_260) @[Mux.scala 27:72]
|
||||
wire iccm_bank_dout_fn_1 : UInt<39> @[Mux.scala 27:72]
|
||||
iccm_bank_dout_fn_1 <= _T_262 @[Mux.scala 27:72]
|
||||
node _T_263 = bits(sel_red1_q, 2, 2) @[el2_ifu_iccm_mem.scala 75:47]
|
||||
node _T_264 = bits(_T_263, 0, 0) @[el2_ifu_iccm_mem.scala 75:51]
|
||||
node _T_265 = bits(sel_red0_q, 2, 2) @[el2_ifu_iccm_mem.scala 76:47]
|
||||
node _T_266 = bits(_T_265, 0, 0) @[el2_ifu_iccm_mem.scala 76:51]
|
||||
node _T_267 = bits(sel_red0_q, 2, 2) @[el2_ifu_iccm_mem.scala 77:47]
|
||||
node _T_268 = not(_T_267) @[el2_ifu_iccm_mem.scala 77:36]
|
||||
node _T_269 = bits(sel_red1_q, 2, 2) @[el2_ifu_iccm_mem.scala 77:64]
|
||||
node _T_270 = not(_T_269) @[el2_ifu_iccm_mem.scala 77:53]
|
||||
node _T_271 = and(_T_268, _T_270) @[el2_ifu_iccm_mem.scala 77:51]
|
||||
node _T_272 = bits(_T_271, 0, 0) @[el2_ifu_iccm_mem.scala 77:69]
|
||||
node _T_263 = bits(sel_red1_q, 2, 2) @[el2_ifu_iccm_mem.scala 79:47]
|
||||
node _T_264 = bits(_T_263, 0, 0) @[el2_ifu_iccm_mem.scala 79:51]
|
||||
node _T_265 = bits(sel_red0_q, 2, 2) @[el2_ifu_iccm_mem.scala 80:47]
|
||||
node _T_266 = bits(_T_265, 0, 0) @[el2_ifu_iccm_mem.scala 80:51]
|
||||
node _T_267 = bits(sel_red0_q, 2, 2) @[el2_ifu_iccm_mem.scala 81:47]
|
||||
node _T_268 = not(_T_267) @[el2_ifu_iccm_mem.scala 81:36]
|
||||
node _T_269 = bits(sel_red1_q, 2, 2) @[el2_ifu_iccm_mem.scala 81:64]
|
||||
node _T_270 = not(_T_269) @[el2_ifu_iccm_mem.scala 81:53]
|
||||
node _T_271 = and(_T_268, _T_270) @[el2_ifu_iccm_mem.scala 81:51]
|
||||
node _T_272 = bits(_T_271, 0, 0) @[el2_ifu_iccm_mem.scala 81:69]
|
||||
node _T_273 = mux(_T_264, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_274 = mux(_T_266, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_275 = mux(_T_272, iccm_bank_dout[2], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
|
|
@ -388,16 +363,16 @@ circuit el2_ifu_iccm_mem :
|
|||
node _T_277 = or(_T_276, _T_275) @[Mux.scala 27:72]
|
||||
wire iccm_bank_dout_fn_2 : UInt<39> @[Mux.scala 27:72]
|
||||
iccm_bank_dout_fn_2 <= _T_277 @[Mux.scala 27:72]
|
||||
node _T_278 = bits(sel_red1_q, 3, 3) @[el2_ifu_iccm_mem.scala 75:47]
|
||||
node _T_279 = bits(_T_278, 0, 0) @[el2_ifu_iccm_mem.scala 75:51]
|
||||
node _T_280 = bits(sel_red0_q, 3, 3) @[el2_ifu_iccm_mem.scala 76:47]
|
||||
node _T_281 = bits(_T_280, 0, 0) @[el2_ifu_iccm_mem.scala 76:51]
|
||||
node _T_282 = bits(sel_red0_q, 3, 3) @[el2_ifu_iccm_mem.scala 77:47]
|
||||
node _T_283 = not(_T_282) @[el2_ifu_iccm_mem.scala 77:36]
|
||||
node _T_284 = bits(sel_red1_q, 3, 3) @[el2_ifu_iccm_mem.scala 77:64]
|
||||
node _T_285 = not(_T_284) @[el2_ifu_iccm_mem.scala 77:53]
|
||||
node _T_286 = and(_T_283, _T_285) @[el2_ifu_iccm_mem.scala 77:51]
|
||||
node _T_287 = bits(_T_286, 0, 0) @[el2_ifu_iccm_mem.scala 77:69]
|
||||
node _T_278 = bits(sel_red1_q, 3, 3) @[el2_ifu_iccm_mem.scala 79:47]
|
||||
node _T_279 = bits(_T_278, 0, 0) @[el2_ifu_iccm_mem.scala 79:51]
|
||||
node _T_280 = bits(sel_red0_q, 3, 3) @[el2_ifu_iccm_mem.scala 80:47]
|
||||
node _T_281 = bits(_T_280, 0, 0) @[el2_ifu_iccm_mem.scala 80:51]
|
||||
node _T_282 = bits(sel_red0_q, 3, 3) @[el2_ifu_iccm_mem.scala 81:47]
|
||||
node _T_283 = not(_T_282) @[el2_ifu_iccm_mem.scala 81:36]
|
||||
node _T_284 = bits(sel_red1_q, 3, 3) @[el2_ifu_iccm_mem.scala 81:64]
|
||||
node _T_285 = not(_T_284) @[el2_ifu_iccm_mem.scala 81:53]
|
||||
node _T_286 = and(_T_283, _T_285) @[el2_ifu_iccm_mem.scala 81:51]
|
||||
node _T_287 = bits(_T_286, 0, 0) @[el2_ifu_iccm_mem.scala 81:69]
|
||||
node _T_288 = mux(_T_279, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_289 = mux(_T_281, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_290 = mux(_T_287, iccm_bank_dout[3], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
|
|
@ -407,38 +382,38 @@ circuit el2_ifu_iccm_mem :
|
|||
iccm_bank_dout_fn_3 <= _T_292 @[Mux.scala 27:72]
|
||||
wire redundant_lru : UInt<1>
|
||||
redundant_lru <= UInt<1>("h00")
|
||||
node _T_293 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 79:20]
|
||||
node r0_addr_en = and(_T_293, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 79:35]
|
||||
node r1_addr_en = and(redundant_lru, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 80:35]
|
||||
node _T_294 = orr(sel_red0) @[el2_ifu_iccm_mem.scala 81:63]
|
||||
node _T_295 = orr(sel_red1) @[el2_ifu_iccm_mem.scala 81:78]
|
||||
node _T_296 = or(_T_294, _T_295) @[el2_ifu_iccm_mem.scala 81:67]
|
||||
node _T_297 = and(_T_296, io.iccm_rden) @[el2_ifu_iccm_mem.scala 81:83]
|
||||
node _T_298 = and(_T_297, io.iccm_correction_state) @[el2_ifu_iccm_mem.scala 81:98]
|
||||
node redundant_lru_en = or(io.iccm_buf_correct_ecc, _T_298) @[el2_ifu_iccm_mem.scala 81:50]
|
||||
node _T_299 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 82:55]
|
||||
node _T_300 = orr(sel_red0) @[el2_ifu_iccm_mem.scala 82:84]
|
||||
node _T_301 = mux(_T_300, UInt<1>("h01"), UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 82:74]
|
||||
node redundant_lru_in = mux(io.iccm_buf_correct_ecc, _T_299, _T_301) @[el2_ifu_iccm_mem.scala 82:29]
|
||||
node _T_293 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 83:20]
|
||||
node r0_addr_en = and(_T_293, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 83:35]
|
||||
node r1_addr_en = and(redundant_lru, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 84:35]
|
||||
node _T_294 = orr(sel_red0) @[el2_ifu_iccm_mem.scala 85:63]
|
||||
node _T_295 = orr(sel_red1) @[el2_ifu_iccm_mem.scala 85:78]
|
||||
node _T_296 = or(_T_294, _T_295) @[el2_ifu_iccm_mem.scala 85:67]
|
||||
node _T_297 = and(_T_296, io.iccm_rden) @[el2_ifu_iccm_mem.scala 85:83]
|
||||
node _T_298 = and(_T_297, io.iccm_correction_state) @[el2_ifu_iccm_mem.scala 85:98]
|
||||
node redundant_lru_en = or(io.iccm_buf_correct_ecc, _T_298) @[el2_ifu_iccm_mem.scala 85:50]
|
||||
node _T_299 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 86:55]
|
||||
node _T_300 = orr(sel_red0) @[el2_ifu_iccm_mem.scala 86:84]
|
||||
node _T_301 = mux(_T_300, UInt<1>("h01"), UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 86:74]
|
||||
node redundant_lru_in = mux(io.iccm_buf_correct_ecc, _T_299, _T_301) @[el2_ifu_iccm_mem.scala 86:29]
|
||||
reg _T_302 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when redundant_lru_en : @[Reg.scala 28:19]
|
||||
_T_302 <= redundant_lru_in @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
redundant_lru <= _T_302 @[el2_ifu_iccm_mem.scala 83:17]
|
||||
node _T_303 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 84:52]
|
||||
redundant_lru <= _T_302 @[el2_ifu_iccm_mem.scala 87:17]
|
||||
node _T_303 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 88:52]
|
||||
reg _T_304 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when r0_addr_en : @[Reg.scala 28:19]
|
||||
_T_304 <= _T_303 @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
redundant_address[0] <= _T_304 @[el2_ifu_iccm_mem.scala 84:24]
|
||||
node _T_305 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 85:52]
|
||||
node _T_306 = bits(r1_addr_en, 0, 0) @[el2_ifu_iccm_mem.scala 85:85]
|
||||
redundant_address[0] <= _T_304 @[el2_ifu_iccm_mem.scala 88:24]
|
||||
node _T_305 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 89:52]
|
||||
node _T_306 = bits(r1_addr_en, 0, 0) @[el2_ifu_iccm_mem.scala 89:85]
|
||||
reg _T_307 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when _T_306 : @[Reg.scala 28:19]
|
||||
_T_307 <= _T_305 @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
redundant_address[1] <= _T_307 @[el2_ifu_iccm_mem.scala 85:24]
|
||||
node _T_308 = bits(r1_addr_en, 0, 0) @[el2_ifu_iccm_mem.scala 86:57]
|
||||
redundant_address[1] <= _T_307 @[el2_ifu_iccm_mem.scala 89:24]
|
||||
node _T_308 = bits(r1_addr_en, 0, 0) @[el2_ifu_iccm_mem.scala 90:57]
|
||||
reg _T_309 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when _T_308 : @[Reg.scala 28:19]
|
||||
_T_309 <= UInt<1>("h01") @[Reg.scala 28:23]
|
||||
|
|
@ -448,89 +423,89 @@ circuit el2_ifu_iccm_mem :
|
|||
_T_310 <= UInt<1>("h01") @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
node _T_311 = cat(_T_309, _T_310) @[Cat.scala 29:58]
|
||||
redundant_valid <= _T_311 @[el2_ifu_iccm_mem.scala 86:19]
|
||||
node _T_312 = bits(io.iccm_rw_addr, 14, 2) @[el2_ifu_iccm_mem.scala 88:45]
|
||||
node _T_313 = bits(redundant_address[0], 13, 1) @[el2_ifu_iccm_mem.scala 88:85]
|
||||
node _T_314 = eq(_T_312, _T_313) @[el2_ifu_iccm_mem.scala 88:61]
|
||||
node _T_315 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 89:22]
|
||||
node _T_316 = bits(redundant_address[0], 0, 0) @[el2_ifu_iccm_mem.scala 89:48]
|
||||
node _T_317 = and(_T_315, _T_316) @[el2_ifu_iccm_mem.scala 89:26]
|
||||
node _T_318 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 89:70]
|
||||
node _T_319 = eq(_T_318, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 89:75]
|
||||
node _T_320 = or(_T_317, _T_319) @[el2_ifu_iccm_mem.scala 89:52]
|
||||
node _T_321 = and(_T_314, _T_320) @[el2_ifu_iccm_mem.scala 88:102]
|
||||
node _T_322 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 89:101]
|
||||
node _T_323 = and(_T_321, _T_322) @[el2_ifu_iccm_mem.scala 89:84]
|
||||
node _T_324 = and(_T_323, io.iccm_wren) @[el2_ifu_iccm_mem.scala 89:105]
|
||||
node _T_325 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 90:6]
|
||||
node _T_326 = and(_T_325, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 90:21]
|
||||
node redundant_data0_en = or(_T_324, _T_326) @[el2_ifu_iccm_mem.scala 89:121]
|
||||
node _T_327 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 91:49]
|
||||
node _T_328 = bits(redundant_address[0], 0, 0) @[el2_ifu_iccm_mem.scala 91:73]
|
||||
node _T_329 = and(_T_327, _T_328) @[el2_ifu_iccm_mem.scala 91:52]
|
||||
node _T_330 = bits(redundant_address[0], 0, 0) @[el2_ifu_iccm_mem.scala 91:100]
|
||||
node _T_331 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 91:122]
|
||||
node _T_332 = eq(_T_331, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 91:127]
|
||||
node _T_333 = and(_T_330, _T_332) @[el2_ifu_iccm_mem.scala 91:104]
|
||||
node _T_334 = or(_T_329, _T_333) @[el2_ifu_iccm_mem.scala 91:78]
|
||||
node _T_335 = bits(_T_334, 0, 0) @[el2_ifu_iccm_mem.scala 91:137]
|
||||
node _T_336 = bits(io.iccm_wr_data, 77, 39) @[el2_ifu_iccm_mem.scala 92:20]
|
||||
node _T_337 = bits(io.iccm_wr_data, 38, 0) @[el2_ifu_iccm_mem.scala 92:44]
|
||||
node redundant_data0_in = mux(_T_335, _T_336, _T_337) @[el2_ifu_iccm_mem.scala 91:31]
|
||||
node _T_338 = bits(redundant_data0_en, 0, 0) @[el2_ifu_iccm_mem.scala 93:78]
|
||||
redundant_valid <= _T_311 @[el2_ifu_iccm_mem.scala 90:19]
|
||||
node _T_312 = bits(io.iccm_rw_addr, 14, 2) @[el2_ifu_iccm_mem.scala 92:45]
|
||||
node _T_313 = bits(redundant_address[0], 13, 1) @[el2_ifu_iccm_mem.scala 92:85]
|
||||
node _T_314 = eq(_T_312, _T_313) @[el2_ifu_iccm_mem.scala 92:61]
|
||||
node _T_315 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 93:22]
|
||||
node _T_316 = bits(redundant_address[0], 0, 0) @[el2_ifu_iccm_mem.scala 93:48]
|
||||
node _T_317 = and(_T_315, _T_316) @[el2_ifu_iccm_mem.scala 93:26]
|
||||
node _T_318 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 93:70]
|
||||
node _T_319 = eq(_T_318, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 93:75]
|
||||
node _T_320 = or(_T_317, _T_319) @[el2_ifu_iccm_mem.scala 93:52]
|
||||
node _T_321 = and(_T_314, _T_320) @[el2_ifu_iccm_mem.scala 92:102]
|
||||
node _T_322 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 93:101]
|
||||
node _T_323 = and(_T_321, _T_322) @[el2_ifu_iccm_mem.scala 93:84]
|
||||
node _T_324 = and(_T_323, io.iccm_wren) @[el2_ifu_iccm_mem.scala 93:105]
|
||||
node _T_325 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 94:6]
|
||||
node _T_326 = and(_T_325, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 94:21]
|
||||
node redundant_data0_en = or(_T_324, _T_326) @[el2_ifu_iccm_mem.scala 93:121]
|
||||
node _T_327 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 95:49]
|
||||
node _T_328 = bits(redundant_address[0], 0, 0) @[el2_ifu_iccm_mem.scala 95:73]
|
||||
node _T_329 = and(_T_327, _T_328) @[el2_ifu_iccm_mem.scala 95:52]
|
||||
node _T_330 = bits(redundant_address[0], 0, 0) @[el2_ifu_iccm_mem.scala 95:100]
|
||||
node _T_331 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 95:122]
|
||||
node _T_332 = eq(_T_331, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 95:127]
|
||||
node _T_333 = and(_T_330, _T_332) @[el2_ifu_iccm_mem.scala 95:104]
|
||||
node _T_334 = or(_T_329, _T_333) @[el2_ifu_iccm_mem.scala 95:78]
|
||||
node _T_335 = bits(_T_334, 0, 0) @[el2_ifu_iccm_mem.scala 95:137]
|
||||
node _T_336 = bits(io.iccm_wr_data, 77, 39) @[el2_ifu_iccm_mem.scala 96:20]
|
||||
node _T_337 = bits(io.iccm_wr_data, 38, 0) @[el2_ifu_iccm_mem.scala 96:44]
|
||||
node redundant_data0_in = mux(_T_335, _T_336, _T_337) @[el2_ifu_iccm_mem.scala 95:31]
|
||||
node _T_338 = bits(redundant_data0_en, 0, 0) @[el2_ifu_iccm_mem.scala 97:78]
|
||||
reg _T_339 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when _T_338 : @[Reg.scala 28:19]
|
||||
_T_339 <= redundant_data0_in @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
redundant_data[0] <= _T_339 @[el2_ifu_iccm_mem.scala 93:21]
|
||||
node _T_340 = bits(io.iccm_rw_addr, 14, 2) @[el2_ifu_iccm_mem.scala 95:45]
|
||||
node _T_341 = bits(redundant_address[1], 13, 1) @[el2_ifu_iccm_mem.scala 95:85]
|
||||
node _T_342 = eq(_T_340, _T_341) @[el2_ifu_iccm_mem.scala 95:61]
|
||||
node _T_343 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 96:22]
|
||||
node _T_344 = bits(redundant_address[1], 0, 0) @[el2_ifu_iccm_mem.scala 96:48]
|
||||
node _T_345 = and(_T_343, _T_344) @[el2_ifu_iccm_mem.scala 96:26]
|
||||
node _T_346 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 96:70]
|
||||
node _T_347 = eq(_T_346, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 96:75]
|
||||
node _T_348 = or(_T_345, _T_347) @[el2_ifu_iccm_mem.scala 96:52]
|
||||
node _T_349 = and(_T_342, _T_348) @[el2_ifu_iccm_mem.scala 95:102]
|
||||
node _T_350 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 96:101]
|
||||
node _T_351 = and(_T_349, _T_350) @[el2_ifu_iccm_mem.scala 96:84]
|
||||
node _T_352 = and(_T_351, io.iccm_wren) @[el2_ifu_iccm_mem.scala 96:105]
|
||||
node _T_353 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 97:6]
|
||||
node _T_354 = and(_T_353, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 97:21]
|
||||
node redundant_data1_en = or(_T_352, _T_354) @[el2_ifu_iccm_mem.scala 96:121]
|
||||
node _T_355 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 98:49]
|
||||
node _T_356 = bits(redundant_address[1], 0, 0) @[el2_ifu_iccm_mem.scala 98:73]
|
||||
node _T_357 = and(_T_355, _T_356) @[el2_ifu_iccm_mem.scala 98:52]
|
||||
node _T_358 = bits(redundant_address[1], 0, 0) @[el2_ifu_iccm_mem.scala 98:100]
|
||||
node _T_359 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 98:122]
|
||||
node _T_360 = eq(_T_359, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 98:127]
|
||||
node _T_361 = and(_T_358, _T_360) @[el2_ifu_iccm_mem.scala 98:104]
|
||||
node _T_362 = or(_T_357, _T_361) @[el2_ifu_iccm_mem.scala 98:78]
|
||||
node _T_363 = bits(_T_362, 0, 0) @[el2_ifu_iccm_mem.scala 98:137]
|
||||
node _T_364 = bits(io.iccm_wr_data, 77, 39) @[el2_ifu_iccm_mem.scala 99:20]
|
||||
node _T_365 = bits(io.iccm_wr_data, 38, 0) @[el2_ifu_iccm_mem.scala 99:44]
|
||||
node redundant_data1_in = mux(_T_363, _T_364, _T_365) @[el2_ifu_iccm_mem.scala 98:31]
|
||||
node _T_366 = bits(redundant_data1_en, 0, 0) @[el2_ifu_iccm_mem.scala 100:78]
|
||||
redundant_data[0] <= _T_339 @[el2_ifu_iccm_mem.scala 97:21]
|
||||
node _T_340 = bits(io.iccm_rw_addr, 14, 2) @[el2_ifu_iccm_mem.scala 99:45]
|
||||
node _T_341 = bits(redundant_address[1], 13, 1) @[el2_ifu_iccm_mem.scala 99:85]
|
||||
node _T_342 = eq(_T_340, _T_341) @[el2_ifu_iccm_mem.scala 99:61]
|
||||
node _T_343 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 100:22]
|
||||
node _T_344 = bits(redundant_address[1], 0, 0) @[el2_ifu_iccm_mem.scala 100:48]
|
||||
node _T_345 = and(_T_343, _T_344) @[el2_ifu_iccm_mem.scala 100:26]
|
||||
node _T_346 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 100:70]
|
||||
node _T_347 = eq(_T_346, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 100:75]
|
||||
node _T_348 = or(_T_345, _T_347) @[el2_ifu_iccm_mem.scala 100:52]
|
||||
node _T_349 = and(_T_342, _T_348) @[el2_ifu_iccm_mem.scala 99:102]
|
||||
node _T_350 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 100:101]
|
||||
node _T_351 = and(_T_349, _T_350) @[el2_ifu_iccm_mem.scala 100:84]
|
||||
node _T_352 = and(_T_351, io.iccm_wren) @[el2_ifu_iccm_mem.scala 100:105]
|
||||
node _T_353 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 101:6]
|
||||
node _T_354 = and(_T_353, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 101:21]
|
||||
node redundant_data1_en = or(_T_352, _T_354) @[el2_ifu_iccm_mem.scala 100:121]
|
||||
node _T_355 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 102:49]
|
||||
node _T_356 = bits(redundant_address[1], 0, 0) @[el2_ifu_iccm_mem.scala 102:73]
|
||||
node _T_357 = and(_T_355, _T_356) @[el2_ifu_iccm_mem.scala 102:52]
|
||||
node _T_358 = bits(redundant_address[1], 0, 0) @[el2_ifu_iccm_mem.scala 102:100]
|
||||
node _T_359 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 102:122]
|
||||
node _T_360 = eq(_T_359, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 102:127]
|
||||
node _T_361 = and(_T_358, _T_360) @[el2_ifu_iccm_mem.scala 102:104]
|
||||
node _T_362 = or(_T_357, _T_361) @[el2_ifu_iccm_mem.scala 102:78]
|
||||
node _T_363 = bits(_T_362, 0, 0) @[el2_ifu_iccm_mem.scala 102:137]
|
||||
node _T_364 = bits(io.iccm_wr_data, 77, 39) @[el2_ifu_iccm_mem.scala 103:20]
|
||||
node _T_365 = bits(io.iccm_wr_data, 38, 0) @[el2_ifu_iccm_mem.scala 103:44]
|
||||
node redundant_data1_in = mux(_T_363, _T_364, _T_365) @[el2_ifu_iccm_mem.scala 102:31]
|
||||
node _T_366 = bits(redundant_data1_en, 0, 0) @[el2_ifu_iccm_mem.scala 104:78]
|
||||
reg _T_367 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when _T_366 : @[Reg.scala 28:19]
|
||||
_T_367 <= redundant_data1_in @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
redundant_data[1] <= _T_367 @[el2_ifu_iccm_mem.scala 100:21]
|
||||
node _T_368 = bits(io.iccm_rw_addr, 2, 0) @[el2_ifu_iccm_mem.scala 102:50]
|
||||
reg iccm_rd_addr_lo_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 102:34]
|
||||
iccm_rd_addr_lo_q <= _T_368 @[el2_ifu_iccm_mem.scala 102:34]
|
||||
node _T_369 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 103:48]
|
||||
reg iccm_rd_addr_hi_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 103:34]
|
||||
iccm_rd_addr_hi_q <= _T_369 @[el2_ifu_iccm_mem.scala 103:34]
|
||||
node _T_370 = eq(iccm_rd_addr_hi_q, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 105:86]
|
||||
node _T_371 = bits(iccm_bank_dout_fn_0, 31, 0) @[el2_ifu_iccm_mem.scala 105:115]
|
||||
node _T_372 = eq(iccm_rd_addr_hi_q, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 105:86]
|
||||
node _T_373 = bits(iccm_bank_dout_fn_1, 31, 0) @[el2_ifu_iccm_mem.scala 105:115]
|
||||
node _T_374 = eq(iccm_rd_addr_hi_q, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 105:86]
|
||||
node _T_375 = bits(iccm_bank_dout_fn_2, 31, 0) @[el2_ifu_iccm_mem.scala 105:115]
|
||||
node _T_376 = eq(iccm_rd_addr_hi_q, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 105:86]
|
||||
node _T_377 = bits(iccm_bank_dout_fn_3, 31, 0) @[el2_ifu_iccm_mem.scala 105:115]
|
||||
redundant_data[1] <= _T_367 @[el2_ifu_iccm_mem.scala 104:21]
|
||||
node _T_368 = bits(io.iccm_rw_addr, 2, 0) @[el2_ifu_iccm_mem.scala 106:50]
|
||||
reg iccm_rd_addr_lo_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 106:34]
|
||||
iccm_rd_addr_lo_q <= _T_368 @[el2_ifu_iccm_mem.scala 106:34]
|
||||
node _T_369 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 107:48]
|
||||
reg iccm_rd_addr_hi_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 107:34]
|
||||
iccm_rd_addr_hi_q <= _T_369 @[el2_ifu_iccm_mem.scala 107:34]
|
||||
node _T_370 = eq(iccm_rd_addr_hi_q, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 109:86]
|
||||
node _T_371 = bits(iccm_bank_dout_fn_0, 31, 0) @[el2_ifu_iccm_mem.scala 109:115]
|
||||
node _T_372 = eq(iccm_rd_addr_hi_q, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 109:86]
|
||||
node _T_373 = bits(iccm_bank_dout_fn_1, 31, 0) @[el2_ifu_iccm_mem.scala 109:115]
|
||||
node _T_374 = eq(iccm_rd_addr_hi_q, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 109:86]
|
||||
node _T_375 = bits(iccm_bank_dout_fn_2, 31, 0) @[el2_ifu_iccm_mem.scala 109:115]
|
||||
node _T_376 = eq(iccm_rd_addr_hi_q, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 109:86]
|
||||
node _T_377 = bits(iccm_bank_dout_fn_3, 31, 0) @[el2_ifu_iccm_mem.scala 109:115]
|
||||
node _T_378 = mux(_T_370, _T_371, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_379 = mux(_T_372, _T_373, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_380 = mux(_T_374, _T_375, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
|
|
@ -540,18 +515,18 @@ circuit el2_ifu_iccm_mem :
|
|||
node _T_384 = or(_T_383, _T_381) @[Mux.scala 27:72]
|
||||
wire _T_385 : UInt<32> @[Mux.scala 27:72]
|
||||
_T_385 <= _T_384 @[Mux.scala 27:72]
|
||||
node _T_386 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 106:59]
|
||||
node _T_387 = eq(_T_386, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 106:77]
|
||||
node _T_388 = bits(iccm_bank_dout_fn_0, 31, 0) @[el2_ifu_iccm_mem.scala 106:106]
|
||||
node _T_389 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 106:59]
|
||||
node _T_390 = eq(_T_389, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 106:77]
|
||||
node _T_391 = bits(iccm_bank_dout_fn_1, 31, 0) @[el2_ifu_iccm_mem.scala 106:106]
|
||||
node _T_392 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 106:59]
|
||||
node _T_393 = eq(_T_392, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 106:77]
|
||||
node _T_394 = bits(iccm_bank_dout_fn_2, 31, 0) @[el2_ifu_iccm_mem.scala 106:106]
|
||||
node _T_395 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 106:59]
|
||||
node _T_396 = eq(_T_395, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 106:77]
|
||||
node _T_397 = bits(iccm_bank_dout_fn_3, 31, 0) @[el2_ifu_iccm_mem.scala 106:106]
|
||||
node _T_386 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 110:59]
|
||||
node _T_387 = eq(_T_386, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 110:77]
|
||||
node _T_388 = bits(iccm_bank_dout_fn_0, 31, 0) @[el2_ifu_iccm_mem.scala 110:106]
|
||||
node _T_389 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 110:59]
|
||||
node _T_390 = eq(_T_389, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 110:77]
|
||||
node _T_391 = bits(iccm_bank_dout_fn_1, 31, 0) @[el2_ifu_iccm_mem.scala 110:106]
|
||||
node _T_392 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 110:59]
|
||||
node _T_393 = eq(_T_392, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 110:77]
|
||||
node _T_394 = bits(iccm_bank_dout_fn_2, 31, 0) @[el2_ifu_iccm_mem.scala 110:106]
|
||||
node _T_395 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 110:59]
|
||||
node _T_396 = eq(_T_395, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 110:77]
|
||||
node _T_397 = bits(iccm_bank_dout_fn_3, 31, 0) @[el2_ifu_iccm_mem.scala 110:106]
|
||||
node _T_398 = mux(_T_387, _T_388, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_399 = mux(_T_390, _T_391, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_400 = mux(_T_393, _T_394, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
|
|
@ -562,17 +537,17 @@ circuit el2_ifu_iccm_mem :
|
|||
wire _T_405 : UInt<32> @[Mux.scala 27:72]
|
||||
_T_405 <= _T_404 @[Mux.scala 27:72]
|
||||
node iccm_rd_data_pre = cat(_T_385, _T_405) @[Cat.scala 29:58]
|
||||
node _T_406 = bits(iccm_rd_addr_lo_q, 0, 0) @[el2_ifu_iccm_mem.scala 107:43]
|
||||
node _T_407 = bits(_T_406, 0, 0) @[el2_ifu_iccm_mem.scala 107:53]
|
||||
node _T_406 = bits(iccm_rd_addr_lo_q, 0, 0) @[el2_ifu_iccm_mem.scala 111:43]
|
||||
node _T_407 = bits(_T_406, 0, 0) @[el2_ifu_iccm_mem.scala 111:53]
|
||||
node _T_408 = mux(UInt<1>("h00"), UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_409 = bits(iccm_rd_data_pre, 63, 16) @[el2_ifu_iccm_mem.scala 107:89]
|
||||
node _T_409 = bits(iccm_rd_data_pre, 63, 16) @[el2_ifu_iccm_mem.scala 111:89]
|
||||
node _T_410 = cat(_T_408, _T_409) @[Cat.scala 29:58]
|
||||
node _T_411 = mux(_T_407, _T_410, iccm_rd_data_pre) @[el2_ifu_iccm_mem.scala 107:25]
|
||||
io.iccm_rd_data <= _T_411 @[el2_ifu_iccm_mem.scala 107:19]
|
||||
node _T_412 = eq(iccm_rd_addr_hi_q, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 108:85]
|
||||
node _T_413 = eq(iccm_rd_addr_hi_q, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 108:85]
|
||||
node _T_414 = eq(iccm_rd_addr_hi_q, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 108:85]
|
||||
node _T_415 = eq(iccm_rd_addr_hi_q, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 108:85]
|
||||
node _T_411 = mux(_T_407, _T_410, iccm_rd_data_pre) @[el2_ifu_iccm_mem.scala 111:25]
|
||||
io.iccm_rd_data <= _T_411 @[el2_ifu_iccm_mem.scala 111:19]
|
||||
node _T_412 = eq(iccm_rd_addr_hi_q, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 112:85]
|
||||
node _T_413 = eq(iccm_rd_addr_hi_q, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 112:85]
|
||||
node _T_414 = eq(iccm_rd_addr_hi_q, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 112:85]
|
||||
node _T_415 = eq(iccm_rd_addr_hi_q, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 112:85]
|
||||
node _T_416 = mux(_T_412, iccm_bank_dout_fn_0, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_417 = mux(_T_413, iccm_bank_dout_fn_1, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_418 = mux(_T_414, iccm_bank_dout_fn_2, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
|
|
@ -582,14 +557,14 @@ circuit el2_ifu_iccm_mem :
|
|||
node _T_422 = or(_T_421, _T_419) @[Mux.scala 27:72]
|
||||
wire _T_423 : UInt<39> @[Mux.scala 27:72]
|
||||
_T_423 <= _T_422 @[Mux.scala 27:72]
|
||||
node _T_424 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 109:61]
|
||||
node _T_425 = eq(_T_424, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 109:79]
|
||||
node _T_426 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 109:61]
|
||||
node _T_427 = eq(_T_426, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 109:79]
|
||||
node _T_428 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 109:61]
|
||||
node _T_429 = eq(_T_428, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 109:79]
|
||||
node _T_430 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 109:61]
|
||||
node _T_431 = eq(_T_430, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 109:79]
|
||||
node _T_424 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 113:61]
|
||||
node _T_425 = eq(_T_424, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 113:79]
|
||||
node _T_426 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 113:61]
|
||||
node _T_427 = eq(_T_426, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 113:79]
|
||||
node _T_428 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 113:61]
|
||||
node _T_429 = eq(_T_428, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 113:79]
|
||||
node _T_430 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 113:61]
|
||||
node _T_431 = eq(_T_430, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 113:79]
|
||||
node _T_432 = mux(_T_425, iccm_bank_dout_fn_0, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_433 = mux(_T_427, iccm_bank_dout_fn_1, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_434 = mux(_T_429, iccm_bank_dout_fn_2, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
|
|
@ -600,5 +575,5 @@ circuit el2_ifu_iccm_mem :
|
|||
wire _T_439 : UInt<39> @[Mux.scala 27:72]
|
||||
_T_439 <= _T_438 @[Mux.scala 27:72]
|
||||
node _T_440 = cat(_T_423, _T_439) @[Cat.scala 29:58]
|
||||
io.iccm_rd_data_ecc <= _T_440 @[el2_ifu_iccm_mem.scala 108:23]
|
||||
io.iccm_rd_data_ecc <= _T_440 @[el2_ifu_iccm_mem.scala 112:23]
|
||||
|
||||
|
|
|
|||
|
|
@ -40,110 +40,38 @@ module el2_ifu_iccm_mem(
|
|||
reg [31:0] _RAND_17;
|
||||
reg [31:0] _RAND_18;
|
||||
`endif // RANDOMIZE_REG_INIT
|
||||
reg [38:0] iccm_mem_0 [0:4095]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_0__T_101_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_0__T_101_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_0__T_103_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_0__T_103_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_0__T_105_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_0__T_105_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_0__T_107_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_0__T_107_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_0__T_94_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_0__T_94_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire iccm_mem_0__T_94_mask; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire iccm_mem_0__T_94_en; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_0__T_96_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_0__T_96_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire iccm_mem_0__T_96_mask; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire iccm_mem_0__T_96_en; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_0__T_98_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_0__T_98_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire iccm_mem_0__T_98_mask; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire iccm_mem_0__T_98_en; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_0__T_100_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_0__T_100_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire iccm_mem_0__T_100_mask; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire iccm_mem_0__T_100_en; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
reg [38:0] iccm_mem_1 [0:4095]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_1__T_101_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_1__T_101_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_1__T_103_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_1__T_103_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_1__T_105_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_1__T_105_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_1__T_107_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_1__T_107_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_1__T_94_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_1__T_94_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire iccm_mem_1__T_94_mask; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire iccm_mem_1__T_94_en; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_1__T_96_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_1__T_96_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire iccm_mem_1__T_96_mask; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire iccm_mem_1__T_96_en; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_1__T_98_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_1__T_98_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire iccm_mem_1__T_98_mask; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire iccm_mem_1__T_98_en; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_1__T_100_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_1__T_100_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire iccm_mem_1__T_100_mask; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire iccm_mem_1__T_100_en; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
reg [38:0] iccm_mem_2 [0:4095]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_2__T_101_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_2__T_101_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_2__T_103_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_2__T_103_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_2__T_105_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_2__T_105_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_2__T_107_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_2__T_107_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_2__T_94_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_2__T_94_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire iccm_mem_2__T_94_mask; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire iccm_mem_2__T_94_en; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_2__T_96_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_2__T_96_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire iccm_mem_2__T_96_mask; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire iccm_mem_2__T_96_en; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_2__T_98_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_2__T_98_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire iccm_mem_2__T_98_mask; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire iccm_mem_2__T_98_en; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_2__T_100_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_2__T_100_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire iccm_mem_2__T_100_mask; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire iccm_mem_2__T_100_en; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
reg [38:0] iccm_mem_3 [0:4095]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_3__T_101_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_3__T_101_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_3__T_103_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_3__T_103_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_3__T_105_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_3__T_105_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_3__T_107_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_3__T_107_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_3__T_94_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_3__T_94_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire iccm_mem_3__T_94_mask; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire iccm_mem_3__T_94_en; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_3__T_96_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_3__T_96_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire iccm_mem_3__T_96_mask; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire iccm_mem_3__T_96_en; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_3__T_98_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_3__T_98_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire iccm_mem_3__T_98_mask; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire iccm_mem_3__T_98_en; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [38:0] iccm_mem_3__T_100_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire [11:0] iccm_mem_3__T_100_addr; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire iccm_mem_3__T_100_mask; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
wire iccm_mem_3__T_100_en; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
reg [38:0] _T_81 [0:4095]; // @[el2_ifu_iccm_mem.scala 42:51]
|
||||
wire [38:0] _T_81__T_101_data; // @[el2_ifu_iccm_mem.scala 42:51]
|
||||
wire [11:0] _T_81__T_101_addr; // @[el2_ifu_iccm_mem.scala 42:51]
|
||||
wire [38:0] _T_81__T_97_data; // @[el2_ifu_iccm_mem.scala 42:51]
|
||||
wire [11:0] _T_81__T_97_addr; // @[el2_ifu_iccm_mem.scala 42:51]
|
||||
wire _T_81__T_97_mask; // @[el2_ifu_iccm_mem.scala 42:51]
|
||||
wire _T_81__T_97_en; // @[el2_ifu_iccm_mem.scala 42:51]
|
||||
reg [38:0] _T_82 [0:4095]; // @[el2_ifu_iccm_mem.scala 42:51]
|
||||
wire [38:0] _T_82__T_103_data; // @[el2_ifu_iccm_mem.scala 42:51]
|
||||
wire [11:0] _T_82__T_103_addr; // @[el2_ifu_iccm_mem.scala 42:51]
|
||||
wire [38:0] _T_82__T_98_data; // @[el2_ifu_iccm_mem.scala 42:51]
|
||||
wire [11:0] _T_82__T_98_addr; // @[el2_ifu_iccm_mem.scala 42:51]
|
||||
wire _T_82__T_98_mask; // @[el2_ifu_iccm_mem.scala 42:51]
|
||||
wire _T_82__T_98_en; // @[el2_ifu_iccm_mem.scala 42:51]
|
||||
reg [38:0] _T_83 [0:4095]; // @[el2_ifu_iccm_mem.scala 42:51]
|
||||
wire [38:0] _T_83__T_105_data; // @[el2_ifu_iccm_mem.scala 42:51]
|
||||
wire [11:0] _T_83__T_105_addr; // @[el2_ifu_iccm_mem.scala 42:51]
|
||||
wire [38:0] _T_83__T_99_data; // @[el2_ifu_iccm_mem.scala 42:51]
|
||||
wire [11:0] _T_83__T_99_addr; // @[el2_ifu_iccm_mem.scala 42:51]
|
||||
wire _T_83__T_99_mask; // @[el2_ifu_iccm_mem.scala 42:51]
|
||||
wire _T_83__T_99_en; // @[el2_ifu_iccm_mem.scala 42:51]
|
||||
reg [38:0] _T_84 [0:4095]; // @[el2_ifu_iccm_mem.scala 42:51]
|
||||
wire [38:0] _T_84__T_107_data; // @[el2_ifu_iccm_mem.scala 42:51]
|
||||
wire [11:0] _T_84__T_107_addr; // @[el2_ifu_iccm_mem.scala 42:51]
|
||||
wire [38:0] _T_84__T_100_data; // @[el2_ifu_iccm_mem.scala 42:51]
|
||||
wire [11:0] _T_84__T_100_addr; // @[el2_ifu_iccm_mem.scala 42:51]
|
||||
wire _T_84__T_100_mask; // @[el2_ifu_iccm_mem.scala 42:51]
|
||||
wire _T_84__T_100_en; // @[el2_ifu_iccm_mem.scala 42:51]
|
||||
wire _T_1 = io_iccm_wr_size[1:0] == 2'h3; // @[el2_ifu_iccm_mem.scala 24:43]
|
||||
wire [1:0] addr_inc = _T_1 ? 2'h2 : 2'h1; // @[el2_ifu_iccm_mem.scala 24:21]
|
||||
wire [14:0] _GEN_31 = {{13'd0}, addr_inc}; // @[el2_ifu_iccm_mem.scala 25:54]
|
||||
wire [14:0] addr_bank_inc = io_iccm_rw_addr + _GEN_31; // @[el2_ifu_iccm_mem.scala 25:54]
|
||||
wire [14:0] _GEN_27 = {{13'd0}, addr_inc}; // @[el2_ifu_iccm_mem.scala 25:54]
|
||||
wire [14:0] addr_bank_inc = io_iccm_rw_addr + _GEN_27; // @[el2_ifu_iccm_mem.scala 25:54]
|
||||
wire [38:0] iccm_bank_wr_data_0 = io_iccm_wr_data[38:0]; // @[el2_ifu_iccm_mem.scala 29:50]
|
||||
wire [38:0] iccm_bank_wr_data_1 = io_iccm_wr_data[77:39]; // @[el2_ifu_iccm_mem.scala 30:54]
|
||||
wire _T_10 = io_iccm_rw_addr[2:1] == 2'h0; // @[el2_ifu_iccm_mem.scala 33:100]
|
||||
|
|
@ -182,58 +110,58 @@ module el2_ifu_iccm_mem(
|
|||
wire [11:0] _T_66 = _T_17 ? addr_bank_inc[14:3] : io_iccm_rw_addr[14:3]; // @[el2_ifu_iccm_mem.scala 39:8]
|
||||
wire [11:0] _T_73 = _T_22 ? addr_bank_inc[14:3] : io_iccm_rw_addr[14:3]; // @[el2_ifu_iccm_mem.scala 39:8]
|
||||
wire [11:0] _T_80 = _T_27 ? addr_bank_inc[14:3] : io_iccm_rw_addr[14:3]; // @[el2_ifu_iccm_mem.scala 39:8]
|
||||
reg [38:0] iccm_bank_dout_0; // @[el2_ifu_iccm_mem.scala 51:59]
|
||||
reg [38:0] iccm_bank_dout_1; // @[el2_ifu_iccm_mem.scala 51:59]
|
||||
reg [38:0] iccm_bank_dout_2; // @[el2_ifu_iccm_mem.scala 51:59]
|
||||
reg [38:0] iccm_bank_dout_3; // @[el2_ifu_iccm_mem.scala 51:59]
|
||||
reg [38:0] iccm_bank_dout_0; // @[el2_ifu_iccm_mem.scala 55:63]
|
||||
reg [38:0] iccm_bank_dout_1; // @[el2_ifu_iccm_mem.scala 55:63]
|
||||
reg [38:0] iccm_bank_dout_2; // @[el2_ifu_iccm_mem.scala 55:63]
|
||||
reg [38:0] iccm_bank_dout_3; // @[el2_ifu_iccm_mem.scala 55:63]
|
||||
reg _T_309; // @[Reg.scala 27:20]
|
||||
reg _T_310; // @[Reg.scala 27:20]
|
||||
wire [1:0] redundant_valid = {_T_309,_T_310}; // @[Cat.scala 29:58]
|
||||
reg [13:0] redundant_address_1; // @[Reg.scala 27:20]
|
||||
wire _T_112 = io_iccm_rw_addr[14:1] == redundant_address_1; // @[el2_ifu_iccm_mem.scala 65:105]
|
||||
wire _T_115 = _T_112 & _T_10; // @[el2_ifu_iccm_mem.scala 65:145]
|
||||
wire _T_116 = redundant_valid[1] & _T_115; // @[el2_ifu_iccm_mem.scala 65:71]
|
||||
wire _T_119 = addr_bank_inc[14:1] == redundant_address_1; // @[el2_ifu_iccm_mem.scala 66:37]
|
||||
wire _T_122 = _T_119 & _T_12; // @[el2_ifu_iccm_mem.scala 66:77]
|
||||
wire _T_123 = _T_116 | _T_122; // @[el2_ifu_iccm_mem.scala 65:179]
|
||||
wire _T_130 = _T_112 & _T_15; // @[el2_ifu_iccm_mem.scala 65:145]
|
||||
wire _T_131 = redundant_valid[1] & _T_130; // @[el2_ifu_iccm_mem.scala 65:71]
|
||||
wire _T_137 = _T_119 & _T_17; // @[el2_ifu_iccm_mem.scala 66:77]
|
||||
wire _T_138 = _T_131 | _T_137; // @[el2_ifu_iccm_mem.scala 65:179]
|
||||
wire _T_145 = _T_112 & _T_20; // @[el2_ifu_iccm_mem.scala 65:145]
|
||||
wire _T_146 = redundant_valid[1] & _T_145; // @[el2_ifu_iccm_mem.scala 65:71]
|
||||
wire _T_152 = _T_119 & _T_22; // @[el2_ifu_iccm_mem.scala 66:77]
|
||||
wire _T_153 = _T_146 | _T_152; // @[el2_ifu_iccm_mem.scala 65:179]
|
||||
wire _T_160 = _T_112 & _T_25; // @[el2_ifu_iccm_mem.scala 65:145]
|
||||
wire _T_161 = redundant_valid[1] & _T_160; // @[el2_ifu_iccm_mem.scala 65:71]
|
||||
wire _T_167 = _T_119 & _T_27; // @[el2_ifu_iccm_mem.scala 66:77]
|
||||
wire _T_168 = _T_161 | _T_167; // @[el2_ifu_iccm_mem.scala 65:179]
|
||||
wire _T_112 = io_iccm_rw_addr[14:1] == redundant_address_1; // @[el2_ifu_iccm_mem.scala 69:105]
|
||||
wire _T_115 = _T_112 & _T_10; // @[el2_ifu_iccm_mem.scala 69:145]
|
||||
wire _T_116 = redundant_valid[1] & _T_115; // @[el2_ifu_iccm_mem.scala 69:71]
|
||||
wire _T_119 = addr_bank_inc[14:1] == redundant_address_1; // @[el2_ifu_iccm_mem.scala 70:37]
|
||||
wire _T_122 = _T_119 & _T_12; // @[el2_ifu_iccm_mem.scala 70:77]
|
||||
wire _T_123 = _T_116 | _T_122; // @[el2_ifu_iccm_mem.scala 69:179]
|
||||
wire _T_130 = _T_112 & _T_15; // @[el2_ifu_iccm_mem.scala 69:145]
|
||||
wire _T_131 = redundant_valid[1] & _T_130; // @[el2_ifu_iccm_mem.scala 69:71]
|
||||
wire _T_137 = _T_119 & _T_17; // @[el2_ifu_iccm_mem.scala 70:77]
|
||||
wire _T_138 = _T_131 | _T_137; // @[el2_ifu_iccm_mem.scala 69:179]
|
||||
wire _T_145 = _T_112 & _T_20; // @[el2_ifu_iccm_mem.scala 69:145]
|
||||
wire _T_146 = redundant_valid[1] & _T_145; // @[el2_ifu_iccm_mem.scala 69:71]
|
||||
wire _T_152 = _T_119 & _T_22; // @[el2_ifu_iccm_mem.scala 70:77]
|
||||
wire _T_153 = _T_146 | _T_152; // @[el2_ifu_iccm_mem.scala 69:179]
|
||||
wire _T_160 = _T_112 & _T_25; // @[el2_ifu_iccm_mem.scala 69:145]
|
||||
wire _T_161 = redundant_valid[1] & _T_160; // @[el2_ifu_iccm_mem.scala 69:71]
|
||||
wire _T_167 = _T_119 & _T_27; // @[el2_ifu_iccm_mem.scala 70:77]
|
||||
wire _T_168 = _T_161 | _T_167; // @[el2_ifu_iccm_mem.scala 69:179]
|
||||
wire [3:0] sel_red1 = {_T_168,_T_153,_T_138,_T_123}; // @[Cat.scala 29:58]
|
||||
reg [13:0] redundant_address_0; // @[Reg.scala 27:20]
|
||||
wire _T_174 = io_iccm_rw_addr[14:1] == redundant_address_0; // @[el2_ifu_iccm_mem.scala 67:105]
|
||||
wire _T_177 = _T_174 & _T_10; // @[el2_ifu_iccm_mem.scala 67:145]
|
||||
wire _T_178 = redundant_valid[0] & _T_177; // @[el2_ifu_iccm_mem.scala 67:71]
|
||||
wire _T_181 = addr_bank_inc[14:1] == redundant_address_0; // @[el2_ifu_iccm_mem.scala 68:37]
|
||||
wire _T_184 = _T_181 & _T_12; // @[el2_ifu_iccm_mem.scala 68:77]
|
||||
wire _T_185 = _T_178 | _T_184; // @[el2_ifu_iccm_mem.scala 67:179]
|
||||
wire _T_192 = _T_174 & _T_15; // @[el2_ifu_iccm_mem.scala 67:145]
|
||||
wire _T_193 = redundant_valid[0] & _T_192; // @[el2_ifu_iccm_mem.scala 67:71]
|
||||
wire _T_199 = _T_181 & _T_17; // @[el2_ifu_iccm_mem.scala 68:77]
|
||||
wire _T_200 = _T_193 | _T_199; // @[el2_ifu_iccm_mem.scala 67:179]
|
||||
wire _T_207 = _T_174 & _T_20; // @[el2_ifu_iccm_mem.scala 67:145]
|
||||
wire _T_208 = redundant_valid[0] & _T_207; // @[el2_ifu_iccm_mem.scala 67:71]
|
||||
wire _T_214 = _T_181 & _T_22; // @[el2_ifu_iccm_mem.scala 68:77]
|
||||
wire _T_215 = _T_208 | _T_214; // @[el2_ifu_iccm_mem.scala 67:179]
|
||||
wire _T_222 = _T_174 & _T_25; // @[el2_ifu_iccm_mem.scala 67:145]
|
||||
wire _T_223 = redundant_valid[0] & _T_222; // @[el2_ifu_iccm_mem.scala 67:71]
|
||||
wire _T_229 = _T_181 & _T_27; // @[el2_ifu_iccm_mem.scala 68:77]
|
||||
wire _T_230 = _T_223 | _T_229; // @[el2_ifu_iccm_mem.scala 67:179]
|
||||
wire _T_174 = io_iccm_rw_addr[14:1] == redundant_address_0; // @[el2_ifu_iccm_mem.scala 71:105]
|
||||
wire _T_177 = _T_174 & _T_10; // @[el2_ifu_iccm_mem.scala 71:145]
|
||||
wire _T_178 = redundant_valid[0] & _T_177; // @[el2_ifu_iccm_mem.scala 71:71]
|
||||
wire _T_181 = addr_bank_inc[14:1] == redundant_address_0; // @[el2_ifu_iccm_mem.scala 72:37]
|
||||
wire _T_184 = _T_181 & _T_12; // @[el2_ifu_iccm_mem.scala 72:77]
|
||||
wire _T_185 = _T_178 | _T_184; // @[el2_ifu_iccm_mem.scala 71:179]
|
||||
wire _T_192 = _T_174 & _T_15; // @[el2_ifu_iccm_mem.scala 71:145]
|
||||
wire _T_193 = redundant_valid[0] & _T_192; // @[el2_ifu_iccm_mem.scala 71:71]
|
||||
wire _T_199 = _T_181 & _T_17; // @[el2_ifu_iccm_mem.scala 72:77]
|
||||
wire _T_200 = _T_193 | _T_199; // @[el2_ifu_iccm_mem.scala 71:179]
|
||||
wire _T_207 = _T_174 & _T_20; // @[el2_ifu_iccm_mem.scala 71:145]
|
||||
wire _T_208 = redundant_valid[0] & _T_207; // @[el2_ifu_iccm_mem.scala 71:71]
|
||||
wire _T_214 = _T_181 & _T_22; // @[el2_ifu_iccm_mem.scala 72:77]
|
||||
wire _T_215 = _T_208 | _T_214; // @[el2_ifu_iccm_mem.scala 71:179]
|
||||
wire _T_222 = _T_174 & _T_25; // @[el2_ifu_iccm_mem.scala 71:145]
|
||||
wire _T_223 = redundant_valid[0] & _T_222; // @[el2_ifu_iccm_mem.scala 71:71]
|
||||
wire _T_229 = _T_181 & _T_27; // @[el2_ifu_iccm_mem.scala 72:77]
|
||||
wire _T_230 = _T_223 | _T_229; // @[el2_ifu_iccm_mem.scala 71:179]
|
||||
wire [3:0] sel_red0 = {_T_230,_T_215,_T_200,_T_185}; // @[Cat.scala 29:58]
|
||||
reg [3:0] sel_red0_q; // @[el2_ifu_iccm_mem.scala 70:27]
|
||||
reg [3:0] sel_red1_q; // @[el2_ifu_iccm_mem.scala 71:27]
|
||||
wire _T_238 = ~sel_red0_q[0]; // @[el2_ifu_iccm_mem.scala 77:36]
|
||||
wire _T_240 = ~sel_red1_q[0]; // @[el2_ifu_iccm_mem.scala 77:53]
|
||||
wire _T_241 = _T_238 & _T_240; // @[el2_ifu_iccm_mem.scala 77:51]
|
||||
reg [3:0] sel_red0_q; // @[el2_ifu_iccm_mem.scala 74:27]
|
||||
reg [3:0] sel_red1_q; // @[el2_ifu_iccm_mem.scala 75:27]
|
||||
wire _T_238 = ~sel_red0_q[0]; // @[el2_ifu_iccm_mem.scala 81:36]
|
||||
wire _T_240 = ~sel_red1_q[0]; // @[el2_ifu_iccm_mem.scala 81:53]
|
||||
wire _T_241 = _T_238 & _T_240; // @[el2_ifu_iccm_mem.scala 81:51]
|
||||
reg [38:0] redundant_data_1; // @[Reg.scala 27:20]
|
||||
wire [38:0] _T_243 = sel_red1_q[0] ? redundant_data_1 : 39'h0; // @[Mux.scala 27:72]
|
||||
reg [38:0] redundant_data_0; // @[Reg.scala 27:20]
|
||||
|
|
@ -241,66 +169,66 @@ module el2_ifu_iccm_mem(
|
|||
wire [38:0] _T_245 = _T_241 ? iccm_bank_dout_0 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_246 = _T_243 | _T_244; // @[Mux.scala 27:72]
|
||||
wire [38:0] iccm_bank_dout_fn_0 = _T_246 | _T_245; // @[Mux.scala 27:72]
|
||||
wire _T_253 = ~sel_red0_q[1]; // @[el2_ifu_iccm_mem.scala 77:36]
|
||||
wire _T_255 = ~sel_red1_q[1]; // @[el2_ifu_iccm_mem.scala 77:53]
|
||||
wire _T_256 = _T_253 & _T_255; // @[el2_ifu_iccm_mem.scala 77:51]
|
||||
wire _T_253 = ~sel_red0_q[1]; // @[el2_ifu_iccm_mem.scala 81:36]
|
||||
wire _T_255 = ~sel_red1_q[1]; // @[el2_ifu_iccm_mem.scala 81:53]
|
||||
wire _T_256 = _T_253 & _T_255; // @[el2_ifu_iccm_mem.scala 81:51]
|
||||
wire [38:0] _T_258 = sel_red1_q[1] ? redundant_data_1 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_259 = sel_red0_q[1] ? redundant_data_0 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_260 = _T_256 ? iccm_bank_dout_1 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_261 = _T_258 | _T_259; // @[Mux.scala 27:72]
|
||||
wire [38:0] iccm_bank_dout_fn_1 = _T_261 | _T_260; // @[Mux.scala 27:72]
|
||||
wire _T_268 = ~sel_red0_q[2]; // @[el2_ifu_iccm_mem.scala 77:36]
|
||||
wire _T_270 = ~sel_red1_q[2]; // @[el2_ifu_iccm_mem.scala 77:53]
|
||||
wire _T_271 = _T_268 & _T_270; // @[el2_ifu_iccm_mem.scala 77:51]
|
||||
wire _T_268 = ~sel_red0_q[2]; // @[el2_ifu_iccm_mem.scala 81:36]
|
||||
wire _T_270 = ~sel_red1_q[2]; // @[el2_ifu_iccm_mem.scala 81:53]
|
||||
wire _T_271 = _T_268 & _T_270; // @[el2_ifu_iccm_mem.scala 81:51]
|
||||
wire [38:0] _T_273 = sel_red1_q[2] ? redundant_data_1 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_274 = sel_red0_q[2] ? redundant_data_0 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_275 = _T_271 ? iccm_bank_dout_2 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_276 = _T_273 | _T_274; // @[Mux.scala 27:72]
|
||||
wire [38:0] iccm_bank_dout_fn_2 = _T_276 | _T_275; // @[Mux.scala 27:72]
|
||||
wire _T_283 = ~sel_red0_q[3]; // @[el2_ifu_iccm_mem.scala 77:36]
|
||||
wire _T_285 = ~sel_red1_q[3]; // @[el2_ifu_iccm_mem.scala 77:53]
|
||||
wire _T_286 = _T_283 & _T_285; // @[el2_ifu_iccm_mem.scala 77:51]
|
||||
wire _T_283 = ~sel_red0_q[3]; // @[el2_ifu_iccm_mem.scala 81:36]
|
||||
wire _T_285 = ~sel_red1_q[3]; // @[el2_ifu_iccm_mem.scala 81:53]
|
||||
wire _T_286 = _T_283 & _T_285; // @[el2_ifu_iccm_mem.scala 81:51]
|
||||
wire [38:0] _T_288 = sel_red1_q[3] ? redundant_data_1 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_289 = sel_red0_q[3] ? redundant_data_0 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_290 = _T_286 ? iccm_bank_dout_3 : 39'h0; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_291 = _T_288 | _T_289; // @[Mux.scala 27:72]
|
||||
wire [38:0] iccm_bank_dout_fn_3 = _T_291 | _T_290; // @[Mux.scala 27:72]
|
||||
reg redundant_lru; // @[Reg.scala 27:20]
|
||||
wire _T_293 = ~redundant_lru; // @[el2_ifu_iccm_mem.scala 79:20]
|
||||
wire r0_addr_en = _T_293 & io_iccm_buf_correct_ecc; // @[el2_ifu_iccm_mem.scala 79:35]
|
||||
wire r1_addr_en = redundant_lru & io_iccm_buf_correct_ecc; // @[el2_ifu_iccm_mem.scala 80:35]
|
||||
wire _T_294 = |sel_red0; // @[el2_ifu_iccm_mem.scala 81:63]
|
||||
wire _T_295 = |sel_red1; // @[el2_ifu_iccm_mem.scala 81:78]
|
||||
wire _T_296 = _T_294 | _T_295; // @[el2_ifu_iccm_mem.scala 81:67]
|
||||
wire _T_297 = _T_296 & io_iccm_rden; // @[el2_ifu_iccm_mem.scala 81:83]
|
||||
wire _T_298 = _T_297 & io_iccm_correction_state; // @[el2_ifu_iccm_mem.scala 81:98]
|
||||
wire redundant_lru_en = io_iccm_buf_correct_ecc | _T_298; // @[el2_ifu_iccm_mem.scala 81:50]
|
||||
wire _GEN_27 = r1_addr_en | _T_309; // @[Reg.scala 28:19]
|
||||
wire _GEN_28 = r0_addr_en | _T_310; // @[Reg.scala 28:19]
|
||||
wire _T_314 = io_iccm_rw_addr[14:2] == redundant_address_0[13:1]; // @[el2_ifu_iccm_mem.scala 88:61]
|
||||
wire _T_317 = io_iccm_rw_addr[1] & redundant_address_0[0]; // @[el2_ifu_iccm_mem.scala 89:26]
|
||||
wire _T_320 = _T_317 | _T_1; // @[el2_ifu_iccm_mem.scala 89:52]
|
||||
wire _T_321 = _T_314 & _T_320; // @[el2_ifu_iccm_mem.scala 88:102]
|
||||
wire _T_323 = _T_321 & redundant_valid[0]; // @[el2_ifu_iccm_mem.scala 89:84]
|
||||
wire _T_324 = _T_323 & io_iccm_wren; // @[el2_ifu_iccm_mem.scala 89:105]
|
||||
wire redundant_data0_en = _T_324 | r0_addr_en; // @[el2_ifu_iccm_mem.scala 89:121]
|
||||
wire _T_333 = redundant_address_0[0] & _T_1; // @[el2_ifu_iccm_mem.scala 91:104]
|
||||
wire _T_334 = _T_317 | _T_333; // @[el2_ifu_iccm_mem.scala 91:78]
|
||||
wire _T_342 = io_iccm_rw_addr[14:2] == redundant_address_1[13:1]; // @[el2_ifu_iccm_mem.scala 95:61]
|
||||
wire _T_345 = io_iccm_rw_addr[1] & redundant_address_1[0]; // @[el2_ifu_iccm_mem.scala 96:26]
|
||||
wire _T_348 = _T_345 | _T_1; // @[el2_ifu_iccm_mem.scala 96:52]
|
||||
wire _T_349 = _T_342 & _T_348; // @[el2_ifu_iccm_mem.scala 95:102]
|
||||
wire _T_351 = _T_349 & redundant_valid[1]; // @[el2_ifu_iccm_mem.scala 96:84]
|
||||
wire _T_352 = _T_351 & io_iccm_wren; // @[el2_ifu_iccm_mem.scala 96:105]
|
||||
wire redundant_data1_en = _T_352 | r0_addr_en; // @[el2_ifu_iccm_mem.scala 96:121]
|
||||
wire _T_361 = redundant_address_1[0] & _T_1; // @[el2_ifu_iccm_mem.scala 98:104]
|
||||
wire _T_362 = _T_345 | _T_361; // @[el2_ifu_iccm_mem.scala 98:78]
|
||||
reg [2:0] iccm_rd_addr_lo_q; // @[el2_ifu_iccm_mem.scala 102:34]
|
||||
reg [1:0] iccm_rd_addr_hi_q; // @[el2_ifu_iccm_mem.scala 103:34]
|
||||
wire _T_370 = iccm_rd_addr_hi_q == 2'h0; // @[el2_ifu_iccm_mem.scala 105:86]
|
||||
wire _T_372 = iccm_rd_addr_hi_q == 2'h1; // @[el2_ifu_iccm_mem.scala 105:86]
|
||||
wire _T_374 = iccm_rd_addr_hi_q == 2'h2; // @[el2_ifu_iccm_mem.scala 105:86]
|
||||
wire _T_376 = iccm_rd_addr_hi_q == 2'h3; // @[el2_ifu_iccm_mem.scala 105:86]
|
||||
wire _T_293 = ~redundant_lru; // @[el2_ifu_iccm_mem.scala 83:20]
|
||||
wire r0_addr_en = _T_293 & io_iccm_buf_correct_ecc; // @[el2_ifu_iccm_mem.scala 83:35]
|
||||
wire r1_addr_en = redundant_lru & io_iccm_buf_correct_ecc; // @[el2_ifu_iccm_mem.scala 84:35]
|
||||
wire _T_294 = |sel_red0; // @[el2_ifu_iccm_mem.scala 85:63]
|
||||
wire _T_295 = |sel_red1; // @[el2_ifu_iccm_mem.scala 85:78]
|
||||
wire _T_296 = _T_294 | _T_295; // @[el2_ifu_iccm_mem.scala 85:67]
|
||||
wire _T_297 = _T_296 & io_iccm_rden; // @[el2_ifu_iccm_mem.scala 85:83]
|
||||
wire _T_298 = _T_297 & io_iccm_correction_state; // @[el2_ifu_iccm_mem.scala 85:98]
|
||||
wire redundant_lru_en = io_iccm_buf_correct_ecc | _T_298; // @[el2_ifu_iccm_mem.scala 85:50]
|
||||
wire _GEN_23 = r1_addr_en | _T_309; // @[Reg.scala 28:19]
|
||||
wire _GEN_24 = r0_addr_en | _T_310; // @[Reg.scala 28:19]
|
||||
wire _T_314 = io_iccm_rw_addr[14:2] == redundant_address_0[13:1]; // @[el2_ifu_iccm_mem.scala 92:61]
|
||||
wire _T_317 = io_iccm_rw_addr[1] & redundant_address_0[0]; // @[el2_ifu_iccm_mem.scala 93:26]
|
||||
wire _T_320 = _T_317 | _T_1; // @[el2_ifu_iccm_mem.scala 93:52]
|
||||
wire _T_321 = _T_314 & _T_320; // @[el2_ifu_iccm_mem.scala 92:102]
|
||||
wire _T_323 = _T_321 & redundant_valid[0]; // @[el2_ifu_iccm_mem.scala 93:84]
|
||||
wire _T_324 = _T_323 & io_iccm_wren; // @[el2_ifu_iccm_mem.scala 93:105]
|
||||
wire redundant_data0_en = _T_324 | r0_addr_en; // @[el2_ifu_iccm_mem.scala 93:121]
|
||||
wire _T_333 = redundant_address_0[0] & _T_1; // @[el2_ifu_iccm_mem.scala 95:104]
|
||||
wire _T_334 = _T_317 | _T_333; // @[el2_ifu_iccm_mem.scala 95:78]
|
||||
wire _T_342 = io_iccm_rw_addr[14:2] == redundant_address_1[13:1]; // @[el2_ifu_iccm_mem.scala 99:61]
|
||||
wire _T_345 = io_iccm_rw_addr[1] & redundant_address_1[0]; // @[el2_ifu_iccm_mem.scala 100:26]
|
||||
wire _T_348 = _T_345 | _T_1; // @[el2_ifu_iccm_mem.scala 100:52]
|
||||
wire _T_349 = _T_342 & _T_348; // @[el2_ifu_iccm_mem.scala 99:102]
|
||||
wire _T_351 = _T_349 & redundant_valid[1]; // @[el2_ifu_iccm_mem.scala 100:84]
|
||||
wire _T_352 = _T_351 & io_iccm_wren; // @[el2_ifu_iccm_mem.scala 100:105]
|
||||
wire redundant_data1_en = _T_352 | r0_addr_en; // @[el2_ifu_iccm_mem.scala 100:121]
|
||||
wire _T_361 = redundant_address_1[0] & _T_1; // @[el2_ifu_iccm_mem.scala 102:104]
|
||||
wire _T_362 = _T_345 | _T_361; // @[el2_ifu_iccm_mem.scala 102:78]
|
||||
reg [2:0] iccm_rd_addr_lo_q; // @[el2_ifu_iccm_mem.scala 106:34]
|
||||
reg [1:0] iccm_rd_addr_hi_q; // @[el2_ifu_iccm_mem.scala 107:34]
|
||||
wire _T_370 = iccm_rd_addr_hi_q == 2'h0; // @[el2_ifu_iccm_mem.scala 109:86]
|
||||
wire _T_372 = iccm_rd_addr_hi_q == 2'h1; // @[el2_ifu_iccm_mem.scala 109:86]
|
||||
wire _T_374 = iccm_rd_addr_hi_q == 2'h2; // @[el2_ifu_iccm_mem.scala 109:86]
|
||||
wire _T_376 = iccm_rd_addr_hi_q == 2'h3; // @[el2_ifu_iccm_mem.scala 109:86]
|
||||
wire [31:0] _T_378 = _T_370 ? iccm_bank_dout_fn_0[31:0] : 32'h0; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_379 = _T_372 ? iccm_bank_dout_fn_1[31:0] : 32'h0; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_380 = _T_374 ? iccm_bank_dout_fn_2[31:0] : 32'h0; // @[Mux.scala 27:72]
|
||||
|
|
@ -308,10 +236,10 @@ module el2_ifu_iccm_mem(
|
|||
wire [31:0] _T_382 = _T_378 | _T_379; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_383 = _T_382 | _T_380; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_384 = _T_383 | _T_381; // @[Mux.scala 27:72]
|
||||
wire _T_387 = iccm_rd_addr_lo_q[1:0] == 2'h0; // @[el2_ifu_iccm_mem.scala 106:77]
|
||||
wire _T_390 = iccm_rd_addr_lo_q[1:0] == 2'h1; // @[el2_ifu_iccm_mem.scala 106:77]
|
||||
wire _T_393 = iccm_rd_addr_lo_q[1:0] == 2'h2; // @[el2_ifu_iccm_mem.scala 106:77]
|
||||
wire _T_396 = iccm_rd_addr_lo_q[1:0] == 2'h3; // @[el2_ifu_iccm_mem.scala 106:77]
|
||||
wire _T_387 = iccm_rd_addr_lo_q[1:0] == 2'h0; // @[el2_ifu_iccm_mem.scala 110:77]
|
||||
wire _T_390 = iccm_rd_addr_lo_q[1:0] == 2'h1; // @[el2_ifu_iccm_mem.scala 110:77]
|
||||
wire _T_393 = iccm_rd_addr_lo_q[1:0] == 2'h2; // @[el2_ifu_iccm_mem.scala 110:77]
|
||||
wire _T_396 = iccm_rd_addr_lo_q[1:0] == 2'h3; // @[el2_ifu_iccm_mem.scala 110:77]
|
||||
wire [31:0] _T_398 = _T_387 ? iccm_bank_dout_fn_0[31:0] : 32'h0; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_399 = _T_390 ? iccm_bank_dout_fn_1[31:0] : 32'h0; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_400 = _T_393 ? iccm_bank_dout_fn_2[31:0] : 32'h0; // @[Mux.scala 27:72]
|
||||
|
|
@ -335,108 +263,36 @@ module el2_ifu_iccm_mem(
|
|||
wire [38:0] _T_436 = _T_432 | _T_433; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_437 = _T_436 | _T_434; // @[Mux.scala 27:72]
|
||||
wire [38:0] _T_438 = _T_437 | _T_435; // @[Mux.scala 27:72]
|
||||
assign iccm_mem_0__T_101_addr = wren_bank_0 ? io_iccm_rw_addr[14:3] : _T_59;
|
||||
assign iccm_mem_0__T_101_data = iccm_mem_0[iccm_mem_0__T_101_addr]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
assign iccm_mem_0__T_103_addr = wren_bank_1 ? io_iccm_rw_addr[14:3] : _T_66;
|
||||
assign iccm_mem_0__T_103_data = iccm_mem_0[iccm_mem_0__T_103_addr]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
assign iccm_mem_0__T_105_addr = wren_bank_2 ? io_iccm_rw_addr[14:3] : _T_73;
|
||||
assign iccm_mem_0__T_105_data = iccm_mem_0[iccm_mem_0__T_105_addr]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
assign iccm_mem_0__T_107_addr = wren_bank_3 ? io_iccm_rw_addr[14:3] : _T_80;
|
||||
assign iccm_mem_0__T_107_data = iccm_mem_0[iccm_mem_0__T_107_addr]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
assign iccm_mem_0__T_94_data = io_iccm_wr_data[38:0];
|
||||
assign iccm_mem_0__T_94_addr = wren_bank_0 ? io_iccm_rw_addr[14:3] : _T_59;
|
||||
assign iccm_mem_0__T_94_mask = 1'h1;
|
||||
assign iccm_mem_0__T_94_en = iccm_clken_0 & wren_bank_0;
|
||||
assign iccm_mem_0__T_96_data = 39'h0;
|
||||
assign iccm_mem_0__T_96_addr = wren_bank_1 ? io_iccm_rw_addr[14:3] : _T_66;
|
||||
assign iccm_mem_0__T_96_mask = 1'h0;
|
||||
assign iccm_mem_0__T_96_en = iccm_clken_1 & wren_bank_1;
|
||||
assign iccm_mem_0__T_98_data = 39'h0;
|
||||
assign iccm_mem_0__T_98_addr = wren_bank_2 ? io_iccm_rw_addr[14:3] : _T_73;
|
||||
assign iccm_mem_0__T_98_mask = 1'h0;
|
||||
assign iccm_mem_0__T_98_en = iccm_clken_2 & wren_bank_2;
|
||||
assign iccm_mem_0__T_100_data = 39'h0;
|
||||
assign iccm_mem_0__T_100_addr = wren_bank_3 ? io_iccm_rw_addr[14:3] : _T_80;
|
||||
assign iccm_mem_0__T_100_mask = 1'h0;
|
||||
assign iccm_mem_0__T_100_en = iccm_clken_3 & wren_bank_3;
|
||||
assign iccm_mem_1__T_101_addr = wren_bank_0 ? io_iccm_rw_addr[14:3] : _T_59;
|
||||
assign iccm_mem_1__T_101_data = iccm_mem_1[iccm_mem_1__T_101_addr]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
assign iccm_mem_1__T_103_addr = wren_bank_1 ? io_iccm_rw_addr[14:3] : _T_66;
|
||||
assign iccm_mem_1__T_103_data = iccm_mem_1[iccm_mem_1__T_103_addr]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
assign iccm_mem_1__T_105_addr = wren_bank_2 ? io_iccm_rw_addr[14:3] : _T_73;
|
||||
assign iccm_mem_1__T_105_data = iccm_mem_1[iccm_mem_1__T_105_addr]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
assign iccm_mem_1__T_107_addr = wren_bank_3 ? io_iccm_rw_addr[14:3] : _T_80;
|
||||
assign iccm_mem_1__T_107_data = iccm_mem_1[iccm_mem_1__T_107_addr]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
assign iccm_mem_1__T_94_data = 39'h0;
|
||||
assign iccm_mem_1__T_94_addr = wren_bank_0 ? io_iccm_rw_addr[14:3] : _T_59;
|
||||
assign iccm_mem_1__T_94_mask = 1'h0;
|
||||
assign iccm_mem_1__T_94_en = iccm_clken_0 & wren_bank_0;
|
||||
assign iccm_mem_1__T_96_data = io_iccm_wr_data[77:39];
|
||||
assign iccm_mem_1__T_96_addr = wren_bank_1 ? io_iccm_rw_addr[14:3] : _T_66;
|
||||
assign iccm_mem_1__T_96_mask = 1'h1;
|
||||
assign iccm_mem_1__T_96_en = iccm_clken_1 & wren_bank_1;
|
||||
assign iccm_mem_1__T_98_data = 39'h0;
|
||||
assign iccm_mem_1__T_98_addr = wren_bank_2 ? io_iccm_rw_addr[14:3] : _T_73;
|
||||
assign iccm_mem_1__T_98_mask = 1'h0;
|
||||
assign iccm_mem_1__T_98_en = iccm_clken_2 & wren_bank_2;
|
||||
assign iccm_mem_1__T_100_data = 39'h0;
|
||||
assign iccm_mem_1__T_100_addr = wren_bank_3 ? io_iccm_rw_addr[14:3] : _T_80;
|
||||
assign iccm_mem_1__T_100_mask = 1'h0;
|
||||
assign iccm_mem_1__T_100_en = iccm_clken_3 & wren_bank_3;
|
||||
assign iccm_mem_2__T_101_addr = wren_bank_0 ? io_iccm_rw_addr[14:3] : _T_59;
|
||||
assign iccm_mem_2__T_101_data = iccm_mem_2[iccm_mem_2__T_101_addr]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
assign iccm_mem_2__T_103_addr = wren_bank_1 ? io_iccm_rw_addr[14:3] : _T_66;
|
||||
assign iccm_mem_2__T_103_data = iccm_mem_2[iccm_mem_2__T_103_addr]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
assign iccm_mem_2__T_105_addr = wren_bank_2 ? io_iccm_rw_addr[14:3] : _T_73;
|
||||
assign iccm_mem_2__T_105_data = iccm_mem_2[iccm_mem_2__T_105_addr]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
assign iccm_mem_2__T_107_addr = wren_bank_3 ? io_iccm_rw_addr[14:3] : _T_80;
|
||||
assign iccm_mem_2__T_107_data = iccm_mem_2[iccm_mem_2__T_107_addr]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
assign iccm_mem_2__T_94_data = 39'h0;
|
||||
assign iccm_mem_2__T_94_addr = wren_bank_0 ? io_iccm_rw_addr[14:3] : _T_59;
|
||||
assign iccm_mem_2__T_94_mask = 1'h0;
|
||||
assign iccm_mem_2__T_94_en = iccm_clken_0 & wren_bank_0;
|
||||
assign iccm_mem_2__T_96_data = 39'h0;
|
||||
assign iccm_mem_2__T_96_addr = wren_bank_1 ? io_iccm_rw_addr[14:3] : _T_66;
|
||||
assign iccm_mem_2__T_96_mask = 1'h0;
|
||||
assign iccm_mem_2__T_96_en = iccm_clken_1 & wren_bank_1;
|
||||
assign iccm_mem_2__T_98_data = io_iccm_wr_data[38:0];
|
||||
assign iccm_mem_2__T_98_addr = wren_bank_2 ? io_iccm_rw_addr[14:3] : _T_73;
|
||||
assign iccm_mem_2__T_98_mask = 1'h1;
|
||||
assign iccm_mem_2__T_98_en = iccm_clken_2 & wren_bank_2;
|
||||
assign iccm_mem_2__T_100_data = 39'h0;
|
||||
assign iccm_mem_2__T_100_addr = wren_bank_3 ? io_iccm_rw_addr[14:3] : _T_80;
|
||||
assign iccm_mem_2__T_100_mask = 1'h0;
|
||||
assign iccm_mem_2__T_100_en = iccm_clken_3 & wren_bank_3;
|
||||
assign iccm_mem_3__T_101_addr = wren_bank_0 ? io_iccm_rw_addr[14:3] : _T_59;
|
||||
assign iccm_mem_3__T_101_data = iccm_mem_3[iccm_mem_3__T_101_addr]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
assign iccm_mem_3__T_103_addr = wren_bank_1 ? io_iccm_rw_addr[14:3] : _T_66;
|
||||
assign iccm_mem_3__T_103_data = iccm_mem_3[iccm_mem_3__T_103_addr]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
assign iccm_mem_3__T_105_addr = wren_bank_2 ? io_iccm_rw_addr[14:3] : _T_73;
|
||||
assign iccm_mem_3__T_105_data = iccm_mem_3[iccm_mem_3__T_105_addr]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
assign iccm_mem_3__T_107_addr = wren_bank_3 ? io_iccm_rw_addr[14:3] : _T_80;
|
||||
assign iccm_mem_3__T_107_data = iccm_mem_3[iccm_mem_3__T_107_addr]; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
assign iccm_mem_3__T_94_data = 39'h0;
|
||||
assign iccm_mem_3__T_94_addr = wren_bank_0 ? io_iccm_rw_addr[14:3] : _T_59;
|
||||
assign iccm_mem_3__T_94_mask = 1'h0;
|
||||
assign iccm_mem_3__T_94_en = iccm_clken_0 & wren_bank_0;
|
||||
assign iccm_mem_3__T_96_data = 39'h0;
|
||||
assign iccm_mem_3__T_96_addr = wren_bank_1 ? io_iccm_rw_addr[14:3] : _T_66;
|
||||
assign iccm_mem_3__T_96_mask = 1'h0;
|
||||
assign iccm_mem_3__T_96_en = iccm_clken_1 & wren_bank_1;
|
||||
assign iccm_mem_3__T_98_data = 39'h0;
|
||||
assign iccm_mem_3__T_98_addr = wren_bank_2 ? io_iccm_rw_addr[14:3] : _T_73;
|
||||
assign iccm_mem_3__T_98_mask = 1'h0;
|
||||
assign iccm_mem_3__T_98_en = iccm_clken_2 & wren_bank_2;
|
||||
assign iccm_mem_3__T_100_data = io_iccm_wr_data[77:39];
|
||||
assign iccm_mem_3__T_100_addr = wren_bank_3 ? io_iccm_rw_addr[14:3] : _T_80;
|
||||
assign iccm_mem_3__T_100_mask = 1'h1;
|
||||
assign iccm_mem_3__T_100_en = iccm_clken_3 & wren_bank_3;
|
||||
assign io_iccm_rd_data = iccm_rd_addr_lo_q[0] ? _T_410 : iccm_rd_data_pre; // @[el2_ifu_iccm_mem.scala 22:19 el2_ifu_iccm_mem.scala 107:19]
|
||||
assign io_iccm_rd_data_ecc = {_T_422,_T_438}; // @[el2_ifu_iccm_mem.scala 23:23 el2_ifu_iccm_mem.scala 108:23]
|
||||
assign io_iccm_bank_addr_0 = wren_bank_0 ? io_iccm_rw_addr[14:3] : _T_59; // @[el2_ifu_iccm_mem.scala 56:21]
|
||||
assign io_iccm_bank_addr_1 = wren_bank_1 ? io_iccm_rw_addr[14:3] : _T_66; // @[el2_ifu_iccm_mem.scala 56:21]
|
||||
assign io_iccm_bank_addr_2 = wren_bank_2 ? io_iccm_rw_addr[14:3] : _T_73; // @[el2_ifu_iccm_mem.scala 56:21]
|
||||
assign io_iccm_bank_addr_3 = wren_bank_3 ? io_iccm_rw_addr[14:3] : _T_80; // @[el2_ifu_iccm_mem.scala 56:21]
|
||||
assign _T_81__T_101_addr = wren_bank_0 ? io_iccm_rw_addr[14:3] : _T_59;
|
||||
assign _T_81__T_101_data = _T_81[_T_81__T_101_addr]; // @[el2_ifu_iccm_mem.scala 42:51]
|
||||
assign _T_81__T_97_data = io_iccm_wr_data[38:0];
|
||||
assign _T_81__T_97_addr = wren_bank_0 ? io_iccm_rw_addr[14:3] : _T_59;
|
||||
assign _T_81__T_97_mask = 1'h1;
|
||||
assign _T_81__T_97_en = iccm_clken_0 & wren_bank_0;
|
||||
assign _T_82__T_103_addr = wren_bank_1 ? io_iccm_rw_addr[14:3] : _T_66;
|
||||
assign _T_82__T_103_data = _T_82[_T_82__T_103_addr]; // @[el2_ifu_iccm_mem.scala 42:51]
|
||||
assign _T_82__T_98_data = io_iccm_wr_data[77:39];
|
||||
assign _T_82__T_98_addr = wren_bank_1 ? io_iccm_rw_addr[14:3] : _T_66;
|
||||
assign _T_82__T_98_mask = 1'h1;
|
||||
assign _T_82__T_98_en = iccm_clken_1 & wren_bank_1;
|
||||
assign _T_83__T_105_addr = wren_bank_2 ? io_iccm_rw_addr[14:3] : _T_73;
|
||||
assign _T_83__T_105_data = _T_83[_T_83__T_105_addr]; // @[el2_ifu_iccm_mem.scala 42:51]
|
||||
assign _T_83__T_99_data = io_iccm_wr_data[38:0];
|
||||
assign _T_83__T_99_addr = wren_bank_2 ? io_iccm_rw_addr[14:3] : _T_73;
|
||||
assign _T_83__T_99_mask = 1'h1;
|
||||
assign _T_83__T_99_en = iccm_clken_2 & wren_bank_2;
|
||||
assign _T_84__T_107_addr = wren_bank_3 ? io_iccm_rw_addr[14:3] : _T_80;
|
||||
assign _T_84__T_107_data = _T_84[_T_84__T_107_addr]; // @[el2_ifu_iccm_mem.scala 42:51]
|
||||
assign _T_84__T_100_data = io_iccm_wr_data[77:39];
|
||||
assign _T_84__T_100_addr = wren_bank_3 ? io_iccm_rw_addr[14:3] : _T_80;
|
||||
assign _T_84__T_100_mask = 1'h1;
|
||||
assign _T_84__T_100_en = iccm_clken_3 & wren_bank_3;
|
||||
assign io_iccm_rd_data = iccm_rd_addr_lo_q[0] ? _T_410 : iccm_rd_data_pre; // @[el2_ifu_iccm_mem.scala 22:19 el2_ifu_iccm_mem.scala 111:19]
|
||||
assign io_iccm_rd_data_ecc = {_T_422,_T_438}; // @[el2_ifu_iccm_mem.scala 23:23 el2_ifu_iccm_mem.scala 112:23]
|
||||
assign io_iccm_bank_addr_0 = wren_bank_0 ? io_iccm_rw_addr[14:3] : _T_59; // @[el2_ifu_iccm_mem.scala 60:21]
|
||||
assign io_iccm_bank_addr_1 = wren_bank_1 ? io_iccm_rw_addr[14:3] : _T_66; // @[el2_ifu_iccm_mem.scala 60:21]
|
||||
assign io_iccm_bank_addr_2 = wren_bank_2 ? io_iccm_rw_addr[14:3] : _T_73; // @[el2_ifu_iccm_mem.scala 60:21]
|
||||
assign io_iccm_bank_addr_3 = wren_bank_3 ? io_iccm_rw_addr[14:3] : _T_80; // @[el2_ifu_iccm_mem.scala 60:21]
|
||||
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
||||
`define RANDOMIZE
|
||||
`endif
|
||||
|
|
@ -474,16 +330,16 @@ initial begin
|
|||
`ifdef RANDOMIZE_MEM_INIT
|
||||
_RAND_0 = {2{`RANDOM}};
|
||||
for (initvar = 0; initvar < 4096; initvar = initvar+1)
|
||||
iccm_mem_0[initvar] = _RAND_0[38:0];
|
||||
_T_81[initvar] = _RAND_0[38:0];
|
||||
_RAND_1 = {2{`RANDOM}};
|
||||
for (initvar = 0; initvar < 4096; initvar = initvar+1)
|
||||
iccm_mem_1[initvar] = _RAND_1[38:0];
|
||||
_T_82[initvar] = _RAND_1[38:0];
|
||||
_RAND_2 = {2{`RANDOM}};
|
||||
for (initvar = 0; initvar < 4096; initvar = initvar+1)
|
||||
iccm_mem_2[initvar] = _RAND_2[38:0];
|
||||
_T_83[initvar] = _RAND_2[38:0];
|
||||
_RAND_3 = {2{`RANDOM}};
|
||||
for (initvar = 0; initvar < 4096; initvar = initvar+1)
|
||||
iccm_mem_3[initvar] = _RAND_3[38:0];
|
||||
_T_84[initvar] = _RAND_3[38:0];
|
||||
`endif // RANDOMIZE_MEM_INIT
|
||||
`ifdef RANDOMIZE_REG_INIT
|
||||
_RAND_4 = {2{`RANDOM}};
|
||||
|
|
@ -524,67 +380,31 @@ end // initial
|
|||
`endif
|
||||
`endif // SYNTHESIS
|
||||
always @(posedge clock) begin
|
||||
if(iccm_mem_0__T_94_en & iccm_mem_0__T_94_mask) begin
|
||||
iccm_mem_0[iccm_mem_0__T_94_addr] <= iccm_mem_0__T_94_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
if(_T_81__T_97_en & _T_81__T_97_mask) begin
|
||||
_T_81[_T_81__T_97_addr] <= _T_81__T_97_data; // @[el2_ifu_iccm_mem.scala 42:51]
|
||||
end
|
||||
if(iccm_mem_0__T_96_en & iccm_mem_0__T_96_mask) begin
|
||||
iccm_mem_0[iccm_mem_0__T_96_addr] <= iccm_mem_0__T_96_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
if(_T_82__T_98_en & _T_82__T_98_mask) begin
|
||||
_T_82[_T_82__T_98_addr] <= _T_82__T_98_data; // @[el2_ifu_iccm_mem.scala 42:51]
|
||||
end
|
||||
if(iccm_mem_0__T_98_en & iccm_mem_0__T_98_mask) begin
|
||||
iccm_mem_0[iccm_mem_0__T_98_addr] <= iccm_mem_0__T_98_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
if(_T_83__T_99_en & _T_83__T_99_mask) begin
|
||||
_T_83[_T_83__T_99_addr] <= _T_83__T_99_data; // @[el2_ifu_iccm_mem.scala 42:51]
|
||||
end
|
||||
if(iccm_mem_0__T_100_en & iccm_mem_0__T_100_mask) begin
|
||||
iccm_mem_0[iccm_mem_0__T_100_addr] <= iccm_mem_0__T_100_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
if(_T_84__T_100_en & _T_84__T_100_mask) begin
|
||||
_T_84[_T_84__T_100_addr] <= _T_84__T_100_data; // @[el2_ifu_iccm_mem.scala 42:51]
|
||||
end
|
||||
if(iccm_mem_1__T_94_en & iccm_mem_1__T_94_mask) begin
|
||||
iccm_mem_1[iccm_mem_1__T_94_addr] <= iccm_mem_1__T_94_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
end
|
||||
if(iccm_mem_1__T_96_en & iccm_mem_1__T_96_mask) begin
|
||||
iccm_mem_1[iccm_mem_1__T_96_addr] <= iccm_mem_1__T_96_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
end
|
||||
if(iccm_mem_1__T_98_en & iccm_mem_1__T_98_mask) begin
|
||||
iccm_mem_1[iccm_mem_1__T_98_addr] <= iccm_mem_1__T_98_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
end
|
||||
if(iccm_mem_1__T_100_en & iccm_mem_1__T_100_mask) begin
|
||||
iccm_mem_1[iccm_mem_1__T_100_addr] <= iccm_mem_1__T_100_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
end
|
||||
if(iccm_mem_2__T_94_en & iccm_mem_2__T_94_mask) begin
|
||||
iccm_mem_2[iccm_mem_2__T_94_addr] <= iccm_mem_2__T_94_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
end
|
||||
if(iccm_mem_2__T_96_en & iccm_mem_2__T_96_mask) begin
|
||||
iccm_mem_2[iccm_mem_2__T_96_addr] <= iccm_mem_2__T_96_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
end
|
||||
if(iccm_mem_2__T_98_en & iccm_mem_2__T_98_mask) begin
|
||||
iccm_mem_2[iccm_mem_2__T_98_addr] <= iccm_mem_2__T_98_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
end
|
||||
if(iccm_mem_2__T_100_en & iccm_mem_2__T_100_mask) begin
|
||||
iccm_mem_2[iccm_mem_2__T_100_addr] <= iccm_mem_2__T_100_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
end
|
||||
if(iccm_mem_3__T_94_en & iccm_mem_3__T_94_mask) begin
|
||||
iccm_mem_3[iccm_mem_3__T_94_addr] <= iccm_mem_3__T_94_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
end
|
||||
if(iccm_mem_3__T_96_en & iccm_mem_3__T_96_mask) begin
|
||||
iccm_mem_3[iccm_mem_3__T_96_addr] <= iccm_mem_3__T_96_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
end
|
||||
if(iccm_mem_3__T_98_en & iccm_mem_3__T_98_mask) begin
|
||||
iccm_mem_3[iccm_mem_3__T_98_addr] <= iccm_mem_3__T_98_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
end
|
||||
if(iccm_mem_3__T_100_en & iccm_mem_3__T_100_mask) begin
|
||||
iccm_mem_3[iccm_mem_3__T_100_addr] <= iccm_mem_3__T_100_data; // @[el2_ifu_iccm_mem.scala 41:21]
|
||||
end
|
||||
iccm_bank_dout_0 <= iccm_mem_0__T_107_data;
|
||||
iccm_bank_dout_1 <= iccm_mem_1__T_107_data;
|
||||
iccm_bank_dout_2 <= iccm_mem_2__T_107_data;
|
||||
iccm_bank_dout_3 <= iccm_mem_3__T_107_data;
|
||||
iccm_bank_dout_0 <= _T_81__T_101_data;
|
||||
iccm_bank_dout_1 <= _T_82__T_103_data;
|
||||
iccm_bank_dout_2 <= _T_83__T_105_data;
|
||||
iccm_bank_dout_3 <= _T_84__T_107_data;
|
||||
if (reset) begin
|
||||
_T_309 <= 1'h0;
|
||||
end else begin
|
||||
_T_309 <= _GEN_27;
|
||||
_T_309 <= _GEN_23;
|
||||
end
|
||||
if (reset) begin
|
||||
_T_310 <= 1'h0;
|
||||
end else begin
|
||||
_T_310 <= _GEN_28;
|
||||
_T_310 <= _GEN_24;
|
||||
end
|
||||
if (reset) begin
|
||||
redundant_address_1 <= 14'h0;
|
||||
|
|
|
|||
|
|
@ -38,7 +38,10 @@ class el2_ifu_iccm_mem extends Module with el2_lib {
|
|||
val addr_bank = (0 until ICCM_NUM_BANKS).map(i=> Mux(wren_bank(i).asBool, io.iccm_rw_addr(ICCM_BITS-2, ICCM_BANK_INDEX_LO-1),
|
||||
Mux((addr_bank_inc(ICCM_BANK_HI-1,1)===i.U),addr_bank_inc(ICCM_BITS-2,ICCM_BANK_INDEX_LO-1),io.iccm_rw_addr(ICCM_BITS-2,ICCM_BANK_INDEX_LO-1))))
|
||||
|
||||
val iccm_mem = Mem(pow(2, ICCM_INDEX_BITS).intValue, Vec(ICCM_NUM_BANKS, UInt(39.W)))
|
||||
val iccm_mem = new Array[Mem[UInt]](ICCM_NUM_BANKS)
|
||||
for(i<-0 until ICCM_NUM_BANKS) iccm_mem(i) = Mem(pow(2, ICCM_INDEX_BITS).intValue, UInt(39.W))
|
||||
//val iccm_mem = VecInit.tabulate(ICCM_NUM_BANKS)(i=>Mem(pow(2, ICCM_INDEX_BITS).intValue, UInt(39.W))))
|
||||
//val iccm_mem = Mem(pow(2, ICCM_INDEX_BITS).intValue, Vec(ICCM_NUM_BANKS, UInt(39.W)))
|
||||
|
||||
val write_vec = VecInit.tabulate(ICCM_NUM_BANKS)(i=>iccm_clken(i)&wren_bank(i))
|
||||
val read_enable = VecInit.tabulate(ICCM_NUM_BANKS)(i=>iccm_clken(i)&(!wren_bank(i)))
|
||||
|
|
@ -46,9 +49,10 @@ class el2_ifu_iccm_mem extends Module with el2_lib {
|
|||
val iccm_bank_dout = Wire(Vec(ICCM_NUM_BANKS, UInt(39.W)))
|
||||
//val inter = Wire(Vec(ICCM_NUM_BANKS, UInt(39.W)))
|
||||
|
||||
for(i<-0 until ICCM_NUM_BANKS) when(write_vec(i).asBool){iccm_mem(addr_bank(i))(i) :=iccm_bank_wr_data(i)}
|
||||
|
||||
for(i<-0 until ICCM_NUM_BANKS) iccm_bank_dout := RegNext(iccm_mem(addr_bank(i)))
|
||||
for(i<-0 until ICCM_NUM_BANKS) when(write_vec(i)) {iccm_mem(i)(addr_bank(i)) := iccm_bank_wr_data(i)}
|
||||
|
||||
for(i<-0 until ICCM_NUM_BANKS) {iccm_bank_dout(i) := RegNext(iccm_mem(i).read(addr_bank(i)))}
|
||||
//(0 until ICCM_NUM_BANKS).map(i=> )
|
||||
|
||||
// iccm_bank_dout(i) := RegNext(inter(i))
|
||||
|
|
|
|||
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Reference in New Issue