IMC DONE
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el2_ifu_mem_ctl.fir
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el2_ifu_mem_ctl.fir
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el2_ifu_mem_ctl.v
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el2_ifu_mem_ctl.v
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@ -730,7 +730,7 @@ class el2_ifu_mem_ctl extends Module with el2_lib {
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io.test_way_status_out := test_way_status_out
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io.test_way_status_out := test_way_status_out
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val test_way_status_clken = (0 until ICACHE_TAG_DEPTH/8).map(i=>way_status_clken(i).asUInt()).reverse.reduce(Cat(_,_))
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val test_way_status_clken = (0 until ICACHE_TAG_DEPTH/8).map(i=>way_status_clken(i).asUInt()).reverse.reduce(Cat(_,_))
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io.test_way_status_clken := test_way_status_clken
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io.test_way_status_clken := test_way_status_clken
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way_status := (0 until ICACHE_TAG_DEPTH).map(i => Fill(ICACHE_INDEX_HI - ICACHE_TAG_INDEX_LO, ifu_ic_rw_int_addr_ff === i.U) & way_status_out(i)).reverse.reduce(Cat(_, _))
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way_status := Mux1H((0 until ICACHE_TAG_DEPTH).map(i=>(ifu_ic_rw_int_addr_ff === i.U) -> way_status_out(i)))
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val ifu_ic_rw_int_addr_w_debug = Mux((io.ic_debug_rd_en | io.ic_debug_wr_en) & io.ic_debug_tag_array,
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val ifu_ic_rw_int_addr_w_debug = Mux((io.ic_debug_rd_en | io.ic_debug_wr_en) & io.ic_debug_tag_array,
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io.ic_debug_addr(ICACHE_INDEX_HI - 3, ICACHE_TAG_INDEX_LO - 3), ifu_ic_rw_int_addr(ICACHE_INDEX_HI - 1, ICACHE_TAG_INDEX_LO - 1))
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io.ic_debug_addr(ICACHE_INDEX_HI - 3, ICACHE_TAG_INDEX_LO - 3), ifu_ic_rw_int_addr(ICACHE_INDEX_HI - 1, ICACHE_TAG_INDEX_LO - 1))
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ifu_ic_rw_int_addr_ff := withClock(io.free_clk) {
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ifu_ic_rw_int_addr_ff := withClock(io.free_clk) {
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