braddr updated
This commit is contained in:
waleed-lm
parent
1a16fe4178
commit
b90d9e6739
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@ -3,6 +3,9 @@
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~EL2_IC_TAG|EL2_IC_TAG>io_test",
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"sources":[
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"~EL2_IC_TAG|EL2_IC_TAG>io_ic_debug_wr_en",
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"~EL2_IC_TAG|EL2_IC_TAG>io_ic_debug_tag_array",
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"~EL2_IC_TAG|EL2_IC_TAG>io_ic_debug_wr_data",
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"~EL2_IC_TAG|EL2_IC_TAG>io_ic_rw_addr"
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]
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},
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@ -5,42 +5,42 @@ circuit EL2_IC_TAG :
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input reset : UInt<1>
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output io : {flip clk_override : UInt<1>, flip dec_tlu_core_ecc_disable : UInt<1>, flip ic_rw_addr : UInt<29>, flip ic_wr_en : UInt<2>, flip ic_tag_valid : UInt<2>, flip ic_rd_en : UInt<1>, flip ic_debug_addr : UInt<10>, flip ic_debug_rd_en : UInt<1>, flip ic_debug_wr_en : UInt<1>, flip ic_debug_tag_array : UInt<1>, flip ic_debug_way : UInt<2>, ictag_debug_rd_data : UInt<26>, flip ic_debug_wr_data : UInt<71>, ic_rd_hit : UInt<2>, ic_tag_perr : UInt<1>, flip scan_mode : UInt<1>, test : UInt}
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io.ictag_debug_rd_data <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 65:26]
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io.ic_rd_hit <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 66:16]
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io.ic_tag_perr <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 67:18]
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io.ictag_debug_rd_data <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 64:26]
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io.ic_rd_hit <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 65:16]
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io.ic_tag_perr <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 66:18]
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wire ic_debug_wr_way_en : UInt<2>
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ic_debug_wr_way_en <= UInt<1>("h00")
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wire ic_debug_rd_way_en : UInt<2>
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ic_debug_rd_way_en <= UInt<1>("h00")
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node _T = bits(io.ic_rw_addr, 2, 1) @[el2_ifu_ic_mem.scala 70:70]
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node _T_1 = eq(_T, UInt<1>("h01")) @[el2_ifu_ic_mem.scala 70:95]
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node _T = bits(io.ic_rw_addr, 2, 1) @[el2_ifu_ic_mem.scala 71:70]
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node _T_1 = eq(_T, UInt<1>("h01")) @[el2_ifu_ic_mem.scala 71:95]
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node _T_2 = bits(_T_1, 0, 0) @[Bitwise.scala 72:15]
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node _T_3 = mux(_T_2, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
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node ic_tag_wren = and(io.ic_wr_en, _T_3) @[el2_ifu_ic_mem.scala 70:33]
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node _T_4 = or(io.ic_rd_en, io.clk_override) @[el2_ifu_ic_mem.scala 71:55]
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node ic_tag_wren = and(io.ic_wr_en, _T_3) @[el2_ifu_ic_mem.scala 71:33]
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node _T_4 = or(io.ic_rd_en, io.clk_override) @[el2_ifu_ic_mem.scala 72:55]
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node _T_5 = bits(_T_4, 0, 0) @[Bitwise.scala 72:15]
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node _T_6 = mux(_T_5, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
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node _T_7 = or(_T_6, io.ic_wr_en) @[el2_ifu_ic_mem.scala 71:73]
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node _T_8 = or(_T_7, ic_debug_wr_way_en) @[el2_ifu_ic_mem.scala 71:87]
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node ic_tag_clken = or(_T_8, ic_debug_rd_way_en) @[el2_ifu_ic_mem.scala 71:108]
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reg ic_rd_en_ff : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ic_mem.scala 73:28]
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ic_rd_en_ff <= io.ic_rd_en @[el2_ifu_ic_mem.scala 73:28]
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node _T_9 = bits(io.ic_rw_addr, 18, 0) @[el2_ifu_ic_mem.scala 74:44]
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reg ic_rw_addr_ff : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ic_mem.scala 74:30]
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ic_rw_addr_ff <= _T_9 @[el2_ifu_ic_mem.scala 74:30]
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node _T_10 = and(io.ic_debug_rd_en, io.ic_debug_tag_array) @[el2_ifu_ic_mem.scala 78:65]
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node _T_7 = or(_T_6, io.ic_wr_en) @[el2_ifu_ic_mem.scala 72:73]
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node _T_8 = or(_T_7, ic_debug_wr_way_en) @[el2_ifu_ic_mem.scala 72:87]
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node ic_tag_clken = or(_T_8, ic_debug_rd_way_en) @[el2_ifu_ic_mem.scala 72:108]
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reg ic_rd_en_ff : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ic_mem.scala 74:28]
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ic_rd_en_ff <= io.ic_rd_en @[el2_ifu_ic_mem.scala 74:28]
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node _T_9 = bits(io.ic_rw_addr, 18, 0) @[el2_ifu_ic_mem.scala 75:44]
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reg ic_rw_addr_ff : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ic_mem.scala 75:30]
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ic_rw_addr_ff <= _T_9 @[el2_ifu_ic_mem.scala 75:30]
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node _T_10 = and(io.ic_debug_rd_en, io.ic_debug_tag_array) @[el2_ifu_ic_mem.scala 79:65]
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node _T_11 = bits(_T_10, 0, 0) @[Bitwise.scala 72:15]
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node _T_12 = mux(_T_11, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
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node _T_13 = and(_T_12, io.ic_debug_way) @[el2_ifu_ic_mem.scala 78:90]
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ic_debug_rd_way_en <= _T_13 @[el2_ifu_ic_mem.scala 78:22]
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node _T_14 = and(io.ic_debug_wr_en, io.ic_debug_tag_array) @[el2_ifu_ic_mem.scala 79:65]
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node _T_13 = and(_T_12, io.ic_debug_way) @[el2_ifu_ic_mem.scala 79:90]
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ic_debug_rd_way_en <= _T_13 @[el2_ifu_ic_mem.scala 79:22]
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node _T_14 = and(io.ic_debug_wr_en, io.ic_debug_tag_array) @[el2_ifu_ic_mem.scala 80:65]
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node _T_15 = bits(_T_14, 0, 0) @[Bitwise.scala 72:15]
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node _T_16 = mux(_T_15, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
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node _T_17 = and(_T_16, io.ic_debug_way) @[el2_ifu_ic_mem.scala 79:90]
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ic_debug_wr_way_en <= _T_17 @[el2_ifu_ic_mem.scala 79:22]
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node ic_tag_wren_q = or(ic_tag_wren, ic_debug_wr_way_en) @[el2_ifu_ic_mem.scala 81:35]
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node _T_17 = and(_T_16, io.ic_debug_way) @[el2_ifu_ic_mem.scala 80:90]
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ic_debug_wr_way_en <= _T_17 @[el2_ifu_ic_mem.scala 80:22]
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node ic_tag_wren_q = or(ic_tag_wren, ic_debug_wr_way_en) @[el2_ifu_ic_mem.scala 82:35]
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node _T_18 = mux(UInt<1>("h00"), UInt<13>("h01fff"), UInt<13>("h00")) @[Bitwise.scala 72:12]
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node _T_19 = bits(io.ic_rw_addr, 28, 10) @[el2_ifu_ic_mem.scala 83:74]
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node _T_19 = bits(io.ic_rw_addr, 28, 10) @[el2_ifu_ic_mem.scala 84:89]
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node _T_20 = cat(_T_18, _T_19) @[Cat.scala 29:58]
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wire _T_21 : UInt<1>[18] @[el2_lib.scala 235:18]
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wire _T_22 : UInt<1>[18] @[el2_lib.scala 236:18]
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@ -327,14 +327,17 @@ circuit EL2_IC_TAG :
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node _T_213 = xorr(_T_211) @[el2_lib.scala 254:23]
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node _T_214 = xor(_T_212, _T_213) @[el2_lib.scala 254:18]
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node ic_tag_ecc = cat(_T_214, _T_211) @[Cat.scala 29:58]
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node _T_215 = and(io.ic_debug_wr_en, io.ic_debug_tag_array) @[el2_ifu_ic_mem.scala 85:47]
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node _T_216 = bits(_T_215, 0, 0) @[el2_ifu_ic_mem.scala 85:72]
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node _T_217 = bits(io.ic_debug_wr_data, 68, 64) @[el2_ifu_ic_mem.scala 85:103]
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node _T_218 = bits(io.ic_debug_wr_data, 31, 11) @[el2_ifu_ic_mem.scala 85:131]
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node _T_219 = cat(_T_217, _T_218) @[Cat.scala 29:58]
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node _T_220 = bits(ic_tag_ecc, 4, 0) @[el2_ifu_ic_mem.scala 86:19]
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node _T_221 = bits(io.ic_rw_addr, 28, 10) @[el2_ifu_ic_mem.scala 86:38]
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node _T_222 = cat(_T_220, _T_221) @[Cat.scala 29:58]
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node ic_tag_wr_data = mux(_T_216, _T_219, _T_222) @[el2_ifu_ic_mem.scala 85:27]
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io.test <= io.ic_rw_addr @[el2_ifu_ic_mem.scala 87:11]
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node _T_215 = mux(UInt<1>("h00"), UInt<13>("h01fff"), UInt<13>("h00")) @[Bitwise.scala 72:12]
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node _T_216 = bits(io.ic_rw_addr, 28, 10) @[el2_ifu_ic_mem.scala 86:96]
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node _T_217 = cat(_T_215, _T_216) @[Cat.scala 29:58]
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node ic_tag_parity = xorr(_T_217) @[el2_lib.scala 193:13]
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node _T_218 = and(io.ic_debug_wr_en, io.ic_debug_tag_array) @[el2_ifu_ic_mem.scala 90:30]
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node _T_219 = bits(io.ic_debug_wr_data, 68, 64) @[el2_ifu_ic_mem.scala 90:93]
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node _T_220 = bits(io.ic_debug_wr_data, 31, 11) @[el2_ifu_ic_mem.scala 90:150]
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node _T_221 = cat(_T_219, _T_220) @[Cat.scala 29:58]
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node _T_222 = bits(ic_tag_ecc, 4, 0) @[el2_ifu_ic_mem.scala 91:38]
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node _T_223 = mux(UInt<1>("h00"), UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
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node _T_224 = cat(_T_222, _T_223) @[Cat.scala 29:58]
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node ic_tag_wr_data = mux(_T_218, _T_221, _T_224) @[el2_ifu_ic_mem.scala 90:11]
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io.test <= ic_tag_wr_data @[el2_ifu_ic_mem.scala 93:11]
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35
EL2_IC_TAG.v
35
EL2_IC_TAG.v
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@ -17,10 +17,35 @@ module EL2_IC_TAG(
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output [1:0] io_ic_rd_hit,
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output io_ic_tag_perr,
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input io_scan_mode,
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output [28:0] io_test
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output [25:0] io_test
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);
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assign io_ictag_debug_rd_data = 26'h0; // @[el2_ifu_ic_mem.scala 65:26]
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assign io_ic_rd_hit = 2'h0; // @[el2_ifu_ic_mem.scala 66:16]
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assign io_ic_tag_perr = 1'h0; // @[el2_ifu_ic_mem.scala 67:18]
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assign io_test = io_ic_rw_addr; // @[el2_ifu_ic_mem.scala 87:11]
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wire _T_14 = io_ic_debug_wr_en & io_ic_debug_tag_array; // @[el2_ifu_ic_mem.scala 80:65]
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wire [31:0] _T_20 = {13'h0,io_ic_rw_addr[28:10]}; // @[Cat.scala 29:58]
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wire [8:0] _T_124 = {_T_20[16],_T_20[14],_T_20[12],_T_20[10],_T_20[8],_T_20[6],_T_20[5],_T_20[3],_T_20[1]}; // @[el2_lib.scala 253:22]
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wire [17:0] _T_133 = {_T_20[31],_T_20[30],_T_20[28],_T_20[27],_T_20[25],_T_20[23],_T_20[21],_T_20[20],_T_20[18],_T_124}; // @[el2_lib.scala 253:22]
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wire _T_134 = ^_T_133; // @[el2_lib.scala 253:29]
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wire [8:0] _T_142 = {_T_20[15],_T_20[14],_T_20[11],_T_20[10],_T_20[7],_T_20[6],_T_20[4],_T_20[3],_T_20[0]}; // @[el2_lib.scala 253:39]
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wire [17:0] _T_151 = {_T_20[31],_T_20[29],_T_20[28],_T_20[26],_T_20[25],_T_20[22],_T_20[21],_T_20[19],_T_20[18],_T_142}; // @[el2_lib.scala 253:39]
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wire _T_152 = ^_T_151; // @[el2_lib.scala 253:46]
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wire [8:0] _T_160 = {_T_20[15],_T_20[14],_T_20[9],_T_20[8],_T_20[7],_T_20[6],_T_20[2],_T_20[1],_T_20[0]}; // @[el2_lib.scala 253:56]
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wire [17:0] _T_169 = {_T_20[30],_T_20[29],_T_20[28],_T_20[24],_T_20[23],_T_20[22],_T_20[21],_T_20[17],_T_20[16],_T_160}; // @[el2_lib.scala 253:56]
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wire _T_170 = ^_T_169; // @[el2_lib.scala 253:63]
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wire [6:0] _T_176 = {_T_20[12],_T_20[11],_T_20[10],_T_20[9],_T_20[8],_T_20[7],_T_20[6]}; // @[el2_lib.scala 253:73]
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wire [14:0] _T_184 = {_T_20[27],_T_20[26],_T_20[25],_T_20[24],_T_20[23],_T_20[22],_T_20[21],_T_20[13],_T_176}; // @[el2_lib.scala 253:73]
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wire _T_185 = ^_T_184; // @[el2_lib.scala 253:80]
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wire [14:0] _T_199 = {_T_20[20],_T_20[19],_T_20[18],_T_20[17],_T_20[16],_T_20[15],_T_20[14],_T_20[13],_T_176}; // @[el2_lib.scala 253:90]
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wire _T_200 = ^_T_199; // @[el2_lib.scala 253:97]
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wire [5:0] _T_205 = {_T_20[5],_T_20[4],_T_20[3],_T_20[2],_T_20[1],_T_20[0]}; // @[el2_lib.scala 253:107]
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wire _T_206 = ^_T_205; // @[el2_lib.scala 253:114]
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wire [5:0] _T_211 = {_T_134,_T_152,_T_170,_T_185,_T_200,_T_206}; // @[Cat.scala 29:58]
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wire _T_212 = ^_T_20; // @[el2_lib.scala 254:13]
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wire _T_213 = ^_T_211; // @[el2_lib.scala 254:23]
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wire _T_214 = _T_212 ^ _T_213; // @[el2_lib.scala 254:18]
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wire [6:0] ic_tag_ecc = {_T_214,_T_134,_T_152,_T_170,_T_185,_T_200,_T_206}; // @[Cat.scala 29:58]
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wire [25:0] _T_221 = {io_ic_debug_wr_data[68:64],io_ic_debug_wr_data[31:11]}; // @[Cat.scala 29:58]
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wire [6:0] _T_224 = {ic_tag_ecc[4:0],2'h0}; // @[Cat.scala 29:58]
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assign io_ictag_debug_rd_data = 26'h0; // @[el2_ifu_ic_mem.scala 64:26]
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assign io_ic_rd_hit = 2'h0; // @[el2_ifu_ic_mem.scala 65:16]
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assign io_ic_tag_perr = 1'h0; // @[el2_ifu_ic_mem.scala 66:18]
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assign io_test = _T_14 ? _T_221 : {{19'd0}, _T_224}; // @[el2_ifu_ic_mem.scala 93:11]
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endmodule
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@ -48,7 +48,7 @@ class EL2_IC_TAG extends Module with el2_lib with param {
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val ic_wr_en = Input(UInt(ICACHE_NUM_WAYS.W))
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val ic_tag_valid = Input(UInt(ICACHE_NUM_WAYS.W))
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val ic_rd_en = Input(Bool())
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val ic_debug_addr = Input(UInt((ICACHE_INDEX_HI-2).W))
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val ic_debug_addr = Input(UInt((ICACHE_INDEX_HI-2).W)) // 12-2 = 10-bit value
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val ic_debug_rd_en = Input(Bool())
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val ic_debug_wr_en = Input(Bool())
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val ic_debug_tag_array = Input(Bool())
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@ -59,7 +59,6 @@ class EL2_IC_TAG extends Module with el2_lib with param {
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val ic_tag_perr = Output(Bool())
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val scan_mode = Input(Bool())
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val test = Output(UInt())
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})
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io.ictag_debug_rd_data := 0.U
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@ -67,6 +66,8 @@ class EL2_IC_TAG extends Module with el2_lib with param {
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io.ic_tag_perr := 0.U
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val ic_debug_wr_way_en = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U)
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val ic_debug_rd_way_en = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U)
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val ic_tag_wren = io.ic_wr_en & Fill(ICACHE_NUM_WAYS, io.ic_rw_addr(ICACHE_BEAT_ADDR_HI-3,1)=== Fill(ICACHE_NUM_WAYS-1, 1.U))
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val ic_tag_clken = Fill(ICACHE_NUM_WAYS, io.ic_rd_en|io.clk_override) | io.ic_wr_en | ic_debug_wr_way_en | ic_debug_rd_way_en
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@ -80,11 +81,19 @@ class EL2_IC_TAG extends Module with el2_lib with param {
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val ic_tag_wren_q = ic_tag_wren | ic_debug_wr_way_en
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val ic_tag_ecc = rvecc_encode(Cat(Fill(ICACHE_TAG_LO,0.U),io.ic_rw_addr(31-3, ICACHE_TAG_LO-3)))
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val ic_tag_ecc = if(ICACHE_ECC) rvecc_encode(Cat(Fill(ICACHE_TAG_LO,0.U),io.ic_rw_addr(31-3, ICACHE_TAG_LO-3))) else 0.U
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val ic_tag_parity = if(ICACHE_ECC) rveven_paritygen(Cat(Fill(ICACHE_TAG_LO,0.U),io.ic_rw_addr(31-3, ICACHE_TAG_LO-3))) else 0.U
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val ic_tag_wr_data = if(ICACHE_TAG_LO==11) Mux(io.ic_debug_wr_en & io.ic_debug_tag_array, Cat(if(ICACHE_ECC) io.ic_debug_wr_data(68,64) else io.ic_debug_wr_data(64), io.ic_debug_wr_data(31,11)),
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Cat(if(ICACHE_ECC) ic_tag_ecc(4,0) else ic_tag_parity, io.ic_rw_addr(31-3,ICACHE_TAG_LO-3)))
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else Mux(io.ic_debug_wr_en & io.ic_debug_tag_array, Cat(if(ICACHE_ECC) io.ic_debug_wr_data(68,64) else io.ic_debug_wr_data(64), io.ic_debug_wr_data(31,11)),
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Cat(if(ICACHE_ECC) Cat(ic_tag_ecc(4,0), Fill(PAD_BITS,0.U)) else Cat(ic_tag_parity,Fill(PAD_BITS,0.U), io.ic_rw_addr(31-3,ICACHE_TAG_LO-3))))
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io.test := ic_tag_wr_data
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val ic_tag_wr_data = Mux((io.ic_debug_wr_en & io.ic_debug_tag_array).asBool, Cat(io.ic_debug_wr_data(68,64), io.ic_debug_wr_data(31,11)),
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Cat(ic_tag_ecc(4,0),io.ic_rw_addr(31-3,ICACHE_TAG_LO-3)))
|
||||
io.test := io.ic_rw_addr
|
||||
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -191,11 +191,11 @@ trait el2_lib extends param{
|
|||
|
||||
def rveven_paritygen(data_in : UInt) =
|
||||
data_in.xorR.asUInt
|
||||
|
||||
//rvbradder(Cat(pc, 0.U), Cat(offset, 0.U))
|
||||
def rvbradder (pc:UInt, offset:UInt) = {
|
||||
val dout_lower = pc(12,1) +& offset(12,1)
|
||||
val pc_inc = pc(31,13)+1.U
|
||||
val pc_dec = pc(31,13)+1.U
|
||||
val pc_dec = pc(31,13)-1.U
|
||||
val sign = offset(12)
|
||||
Cat(Mux1H(Seq((sign ^ !dout_lower(dout_lower.getWidth-1)).asBool -> pc(31,13),
|
||||
(!sign & dout_lower(dout_lower.getWidth-1)).asBool -> pc_inc,
|
||||
|
|
|
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Reference in New Issue