Bus Buffer Update

aes.anno.json

@@ -0,0 +1,25 @@
+[
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~aes|aes>io_byteOut",
+    "sources":[
+      "~aes|aes>io_byteIn"
+    ]
+  },
+  {
+    "class":"firrtl.EmitCircuitAnnotation",
+    "emitter":"firrtl.VerilogEmitter"
+  },
+  {
+    "class":"firrtl.options.TargetDirAnnotation",
+    "directory":"."
+  },
+  {
+    "class":"firrtl.options.OutputAnnotationFileAnnotation",
+    "file":"aes"
+  },
+  {
+    "class":"firrtl.transforms.BlackBoxTargetDirAnno",
+    "targetDir":"."
+  }
+]

aes.fir

@@ -0,0 +1,14 @@
+;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
+circuit aes : 
+  module aes : 
+    input clock : Clock
+    input reset : UInt<1>
+    output io : {flip byteIn : UInt<8>, byteOut : UInt<8>}
+    
+    node _T = dshl(io.byteIn, UInt<2>("h03")) @[cipher.scala 16:16]
+    node _T_1 = sub(UInt<4>("h08"), UInt<2>("h03")) @[cipher.scala 16:39]
+    node _T_2 = tail(_T_1, 1) @[cipher.scala 16:39]
+    node _T_3 = dshr(io.byteIn, _T_2) @[cipher.scala 16:31]
+    node z = or(_T, _T_3) @[cipher.scala 16:26]
+    io.byteOut <= z @[cipher.scala 21:14]
+    

aes.v

@@ -0,0 +1,13 @@
+module aes(
+  input        clock,
+  input        reset,
+  input  [7:0] io_byteIn,
+  output [7:0] io_byteOut
+);
+  wire [10:0] _T = {io_byteIn, 3'h0}; // @[cipher.scala 16:16]
+  wire [3:0] _T_2 = 4'h8 - 4'h3; // @[cipher.scala 16:39]
+  wire [7:0] _T_3 = io_byteIn >> _T_2; // @[cipher.scala 16:31]
+  wire [10:0] _GEN_0 = {{3'd0}, _T_3}; // @[cipher.scala 16:26]
+  wire [10:0] z = _T | _GEN_0; // @[cipher.scala 16:26]
+  assign io_byteOut = z[7:0]; // @[cipher.scala 21:14]
+endmodule

src/main/scala/lsu/cipher.scala

@@ -6,25 +6,31 @@
 //
 //
 //@chiselName
-//class aes extends Module{
+//class aes extends Module {
-//  val io = IO (new Bundle {
+//  val io = IO(new Bundle {
 //    val byteIn = Input(UInt(8.W))
 //    val byteOut = Output(UInt(8.W))
 //  })
-//  def ROTL(x:Int,shift:Int) ={
+//
-//    val y = (x << shift) | (x >> (8 - shift))
+//  def ROTL(x: UInt, shift: UInt):UInt = {
+//    val y = (x << shift) | (x >> (8.U - shift))
 //    y
 //  }
-//  io.byteOut := ROTL(io.byteIn,3)
+//
-//  object aes extends App {
+//  def xformed(q:Int) = {
+//     q ^ ROTL(q, 1) ^ ROTL(q, 2) ^ ROTL(q, 3) ^ ROTL(q, 4)
+//
+//    }
+//
+//    sbox[p] := (0 until 255).map( i => )
+//
+//}
+//object aes extends App {
 //    println((new chisel3.stage.ChiselStage).emitVerilog(new aes()))
 //  }
-//// def aes_sbox () ={
-////
-////}
-///*#define ROTL8(x,shift) ((uint8_t) ((x) << (shift)) | ((x) >> (8 - (shift))))
 //
-//void initialize_aes_sbox(uint8_t sbox[256]) {
+//
+///*void initialize_aes_sbox(uint8_t sbox[256]) {
 //  uint8_t p = 1, q = 1;
 //
 //  /* loop invariant: p * q == 1 in the Galois field */
@@ -46,4 +52,3 @@
 //
 //  /* 0 is a special case since it has no inverse */
 //  sbox[0] = 0x63;*/
-//}