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Branch predictor done

This commit is contained in:
waleed-lm 2020-09-30 11:57:37 +05:00
parent ffdead1101
commit b9b47d9ba7
36 changed files with 539 additions and 4992 deletions
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16
EL2_IC_DATA.anno.json
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@ -1,20 +1,4 @@
[ [
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_rd_data",
"sources":[
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_rd_hit"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~EL2_IC_DATA|EL2_IC_DATA>io_ic_rd_data",
"sources":[
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_sel_premux_data",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_premux_data",
"~EL2_IC_DATA|EL2_IC_DATA>io_ic_rd_hit"
]
},
{ {
"class":"firrtl.EmitCircuitAnnotation", "class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter" "emitter":"firrtl.VerilogEmitter"

3662
EL2_IC_DATA.fir
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File diff suppressed because it is too large Load Diff

668
EL2_IC_DATA.v
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@ -1,9 +1,8 @@
module EL2_IC_DATA( module EL2_IC_DATA(
input clock, input clock,
input reset, input reset,
input io_rst_l,
input io_clk_override, input io_clk_override,
input [12:0] io_ic_rw_addr, input [11:0] io_ic_rw_addr,
input [1:0] io_ic_wr_en, input [1:0] io_ic_wr_en,
input io_ic_rd_en, input io_ic_rd_en,
input [70:0] io_ic_wr_data_0, input [70:0] io_ic_wr_data_0,
@ -13,7 +12,7 @@ module EL2_IC_DATA(
output [70:0] io_ic_debug_rd_data, output [70:0] io_ic_debug_rd_data,
output [1:0] io_ic_parerr, output [1:0] io_ic_parerr,
output [1:0] io_ic_eccerr, output [1:0] io_ic_eccerr,
input [12:0] io_ic_debug_addr, input [8:0] io_ic_debug_addr,
input io_ic_debug_rd_en, input io_ic_debug_rd_en,
input io_ic_debug_wr_en, input io_ic_debug_wr_en,
input io_ic_debug_tag_array, input io_ic_debug_tag_array,
@ -21,663 +20,10 @@ module EL2_IC_DATA(
input [63:0] io_ic_premux_data, input [63:0] io_ic_premux_data,
input io_ic_sel_premux_data, input io_ic_sel_premux_data,
input [1:0] io_ic_rd_hit, input [1:0] io_ic_rd_hit,
input io_scan_mode, input io_scan_mode
output io_test_port2,
output [70:0] io_test_port_0_0,
output [70:0] io_test_port_0_1,
output [70:0] io_test_port_1_0,
output [70:0] io_test_port_1_1
); );
`ifdef RANDOMIZE_MEM_INIT assign io_ic_rd_data = 64'h0; // @[el2_ifu_ic_mem.scala 194:17]
reg [95:0] _RAND_0; assign io_ic_debug_rd_data = 71'h0; // @[el2_ifu_ic_mem.scala 195:23]
reg [95:0] _RAND_5; assign io_ic_parerr = 2'h0; // @[el2_ifu_ic_mem.scala 196:16]
reg [95:0] _RAND_10; assign io_ic_eccerr = 2'h0; // @[el2_ifu_ic_mem.scala 197:16]
reg [95:0] _RAND_15;
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_1;
reg [31:0] _RAND_2;
reg [31:0] _RAND_3;
reg [31:0] _RAND_4;
reg [31:0] _RAND_6;
reg [31:0] _RAND_7;
reg [31:0] _RAND_8;
reg [31:0] _RAND_9;
reg [31:0] _RAND_11;
reg [31:0] _RAND_12;
reg [31:0] _RAND_13;
reg [31:0] _RAND_14;
reg [31:0] _RAND_16;
reg [31:0] _RAND_17;
reg [31:0] _RAND_18;
reg [31:0] _RAND_19;
reg [31:0] _RAND_20;
reg [31:0] _RAND_21;
reg [31:0] _RAND_22;
`endif // RANDOMIZE_REG_INIT
reg [70:0] data_mem_0_0 [0:511]; // @[el2_ifu_ic_mem.scala 230:29]
wire [70:0] data_mem_0_0__T_137_data; // @[el2_ifu_ic_mem.scala 230:29]
wire [8:0] data_mem_0_0__T_137_addr; // @[el2_ifu_ic_mem.scala 230:29]
wire [70:0] data_mem_0_0__T_144_data; // @[el2_ifu_ic_mem.scala 230:29]
wire [8:0] data_mem_0_0__T_144_addr; // @[el2_ifu_ic_mem.scala 230:29]
wire [70:0] data_mem_0_0__T_151_data; // @[el2_ifu_ic_mem.scala 230:29]
wire [8:0] data_mem_0_0__T_151_addr; // @[el2_ifu_ic_mem.scala 230:29]
wire [70:0] data_mem_0_0__T_158_data; // @[el2_ifu_ic_mem.scala 230:29]
wire [8:0] data_mem_0_0__T_158_addr; // @[el2_ifu_ic_mem.scala 230:29]
wire [70:0] data_mem_0_0__T_130_data; // @[el2_ifu_ic_mem.scala 230:29]
wire [8:0] data_mem_0_0__T_130_addr; // @[el2_ifu_ic_mem.scala 230:29]
wire data_mem_0_0__T_130_mask; // @[el2_ifu_ic_mem.scala 230:29]
wire data_mem_0_0__T_130_en; // @[el2_ifu_ic_mem.scala 230:29]
wire [70:0] data_mem_0_0__T_135_data; // @[el2_ifu_ic_mem.scala 230:29]
wire [8:0] data_mem_0_0__T_135_addr; // @[el2_ifu_ic_mem.scala 230:29]
wire data_mem_0_0__T_135_mask; // @[el2_ifu_ic_mem.scala 230:29]
wire data_mem_0_0__T_135_en; // @[el2_ifu_ic_mem.scala 230:29]
wire [70:0] data_mem_0_0__T_142_data; // @[el2_ifu_ic_mem.scala 230:29]
wire [8:0] data_mem_0_0__T_142_addr; // @[el2_ifu_ic_mem.scala 230:29]
wire data_mem_0_0__T_142_mask; // @[el2_ifu_ic_mem.scala 230:29]
wire data_mem_0_0__T_142_en; // @[el2_ifu_ic_mem.scala 230:29]
wire [70:0] data_mem_0_0__T_149_data; // @[el2_ifu_ic_mem.scala 230:29]
wire [8:0] data_mem_0_0__T_149_addr; // @[el2_ifu_ic_mem.scala 230:29]
wire data_mem_0_0__T_149_mask; // @[el2_ifu_ic_mem.scala 230:29]
wire data_mem_0_0__T_149_en; // @[el2_ifu_ic_mem.scala 230:29]
wire [70:0] data_mem_0_0__T_156_data; // @[el2_ifu_ic_mem.scala 230:29]
wire [8:0] data_mem_0_0__T_156_addr; // @[el2_ifu_ic_mem.scala 230:29]
wire data_mem_0_0__T_156_mask; // @[el2_ifu_ic_mem.scala 230:29]
wire data_mem_0_0__T_156_en; // @[el2_ifu_ic_mem.scala 230:29]
reg [8:0] data_mem_0_0__T_137_addr_pipe_0;
reg [8:0] data_mem_0_0__T_144_addr_pipe_0;
reg [8:0] data_mem_0_0__T_151_addr_pipe_0;
reg [8:0] data_mem_0_0__T_158_addr_pipe_0;
reg [70:0] data_mem_0_1 [0:511]; // @[el2_ifu_ic_mem.scala 230:29]
wire [70:0] data_mem_0_1__T_137_data; // @[el2_ifu_ic_mem.scala 230:29]
wire [8:0] data_mem_0_1__T_137_addr; // @[el2_ifu_ic_mem.scala 230:29]
wire [70:0] data_mem_0_1__T_144_data; // @[el2_ifu_ic_mem.scala 230:29]
wire [8:0] data_mem_0_1__T_144_addr; // @[el2_ifu_ic_mem.scala 230:29]
wire [70:0] data_mem_0_1__T_151_data; // @[el2_ifu_ic_mem.scala 230:29]
wire [8:0] data_mem_0_1__T_151_addr; // @[el2_ifu_ic_mem.scala 230:29]
wire [70:0] data_mem_0_1__T_158_data; // @[el2_ifu_ic_mem.scala 230:29]
wire [8:0] data_mem_0_1__T_158_addr; // @[el2_ifu_ic_mem.scala 230:29]
wire [70:0] data_mem_0_1__T_130_data; // @[el2_ifu_ic_mem.scala 230:29]
wire [8:0] data_mem_0_1__T_130_addr; // @[el2_ifu_ic_mem.scala 230:29]
wire data_mem_0_1__T_130_mask; // @[el2_ifu_ic_mem.scala 230:29]
wire data_mem_0_1__T_130_en; // @[el2_ifu_ic_mem.scala 230:29]
wire [70:0] data_mem_0_1__T_135_data; // @[el2_ifu_ic_mem.scala 230:29]
wire [8:0] data_mem_0_1__T_135_addr; // @[el2_ifu_ic_mem.scala 230:29]
wire data_mem_0_1__T_135_mask; // @[el2_ifu_ic_mem.scala 230:29]
wire data_mem_0_1__T_135_en; // @[el2_ifu_ic_mem.scala 230:29]
wire [70:0] data_mem_0_1__T_142_data; // @[el2_ifu_ic_mem.scala 230:29]
wire [8:0] data_mem_0_1__T_142_addr; // @[el2_ifu_ic_mem.scala 230:29]
wire data_mem_0_1__T_142_mask; // @[el2_ifu_ic_mem.scala 230:29]
wire data_mem_0_1__T_142_en; // @[el2_ifu_ic_mem.scala 230:29]
wire [70:0] data_mem_0_1__T_149_data; // @[el2_ifu_ic_mem.scala 230:29]
wire [8:0] data_mem_0_1__T_149_addr; // @[el2_ifu_ic_mem.scala 230:29]
wire data_mem_0_1__T_149_mask; // @[el2_ifu_ic_mem.scala 230:29]
wire data_mem_0_1__T_149_en; // @[el2_ifu_ic_mem.scala 230:29]
wire [70:0] data_mem_0_1__T_156_data; // @[el2_ifu_ic_mem.scala 230:29]
wire [8:0] data_mem_0_1__T_156_addr; // @[el2_ifu_ic_mem.scala 230:29]
wire data_mem_0_1__T_156_mask; // @[el2_ifu_ic_mem.scala 230:29]
wire data_mem_0_1__T_156_en; // @[el2_ifu_ic_mem.scala 230:29]
reg [8:0] data_mem_0_1__T_137_addr_pipe_0;
reg [8:0] data_mem_0_1__T_144_addr_pipe_0;
reg [8:0] data_mem_0_1__T_151_addr_pipe_0;
reg [8:0] data_mem_0_1__T_158_addr_pipe_0;
reg [70:0] data_mem_1_0 [0:511]; // @[el2_ifu_ic_mem.scala 230:29]
wire [70:0] data_mem_1_0__T_137_data; // @[el2_ifu_ic_mem.scala 230:29]
wire [8:0] data_mem_1_0__T_137_addr; // @[el2_ifu_ic_mem.scala 230:29]
wire [70:0] data_mem_1_0__T_144_data; // @[el2_ifu_ic_mem.scala 230:29]
wire [8:0] data_mem_1_0__T_144_addr; // @[el2_ifu_ic_mem.scala 230:29]
wire [70:0] data_mem_1_0__T_151_data; // @[el2_ifu_ic_mem.scala 230:29]
wire [8:0] data_mem_1_0__T_151_addr; // @[el2_ifu_ic_mem.scala 230:29]
wire [70:0] data_mem_1_0__T_158_data; // @[el2_ifu_ic_mem.scala 230:29]
wire [8:0] data_mem_1_0__T_158_addr; // @[el2_ifu_ic_mem.scala 230:29]
wire [70:0] data_mem_1_0__T_130_data; // @[el2_ifu_ic_mem.scala 230:29]
wire [8:0] data_mem_1_0__T_130_addr; // @[el2_ifu_ic_mem.scala 230:29]
wire data_mem_1_0__T_130_mask; // @[el2_ifu_ic_mem.scala 230:29]
wire data_mem_1_0__T_130_en; // @[el2_ifu_ic_mem.scala 230:29]
wire [70:0] data_mem_1_0__T_135_data; // @[el2_ifu_ic_mem.scala 230:29]
wire [8:0] data_mem_1_0__T_135_addr; // @[el2_ifu_ic_mem.scala 230:29]
wire data_mem_1_0__T_135_mask; // @[el2_ifu_ic_mem.scala 230:29]
wire data_mem_1_0__T_135_en; // @[el2_ifu_ic_mem.scala 230:29]
wire [70:0] data_mem_1_0__T_142_data; // @[el2_ifu_ic_mem.scala 230:29]
wire [8:0] data_mem_1_0__T_142_addr; // @[el2_ifu_ic_mem.scala 230:29]
wire data_mem_1_0__T_142_mask; // @[el2_ifu_ic_mem.scala 230:29]
wire data_mem_1_0__T_142_en; // @[el2_ifu_ic_mem.scala 230:29]
wire [70:0] data_mem_1_0__T_149_data; // @[el2_ifu_ic_mem.scala 230:29]
wire [8:0] data_mem_1_0__T_149_addr; // @[el2_ifu_ic_mem.scala 230:29]
wire data_mem_1_0__T_149_mask; // @[el2_ifu_ic_mem.scala 230:29]
wire data_mem_1_0__T_149_en; // @[el2_ifu_ic_mem.scala 230:29]
wire [70:0] data_mem_1_0__T_156_data; // @[el2_ifu_ic_mem.scala 230:29]
wire [8:0] data_mem_1_0__T_156_addr; // @[el2_ifu_ic_mem.scala 230:29]
wire data_mem_1_0__T_156_mask; // @[el2_ifu_ic_mem.scala 230:29]
wire data_mem_1_0__T_156_en; // @[el2_ifu_ic_mem.scala 230:29]
reg [8:0] data_mem_1_0__T_137_addr_pipe_0;
reg [8:0] data_mem_1_0__T_144_addr_pipe_0;
reg [8:0] data_mem_1_0__T_151_addr_pipe_0;
reg [8:0] data_mem_1_0__T_158_addr_pipe_0;
reg [70:0] data_mem_1_1 [0:511]; // @[el2_ifu_ic_mem.scala 230:29]
wire [70:0] data_mem_1_1__T_137_data; // @[el2_ifu_ic_mem.scala 230:29]
wire [8:0] data_mem_1_1__T_137_addr; // @[el2_ifu_ic_mem.scala 230:29]
wire [70:0] data_mem_1_1__T_144_data; // @[el2_ifu_ic_mem.scala 230:29]
wire [8:0] data_mem_1_1__T_144_addr; // @[el2_ifu_ic_mem.scala 230:29]
wire [70:0] data_mem_1_1__T_151_data; // @[el2_ifu_ic_mem.scala 230:29]
wire [8:0] data_mem_1_1__T_151_addr; // @[el2_ifu_ic_mem.scala 230:29]
wire [70:0] data_mem_1_1__T_158_data; // @[el2_ifu_ic_mem.scala 230:29]
wire [8:0] data_mem_1_1__T_158_addr; // @[el2_ifu_ic_mem.scala 230:29]
wire [70:0] data_mem_1_1__T_130_data; // @[el2_ifu_ic_mem.scala 230:29]
wire [8:0] data_mem_1_1__T_130_addr; // @[el2_ifu_ic_mem.scala 230:29]
wire data_mem_1_1__T_130_mask; // @[el2_ifu_ic_mem.scala 230:29]
wire data_mem_1_1__T_130_en; // @[el2_ifu_ic_mem.scala 230:29]
wire [70:0] data_mem_1_1__T_135_data; // @[el2_ifu_ic_mem.scala 230:29]
wire [8:0] data_mem_1_1__T_135_addr; // @[el2_ifu_ic_mem.scala 230:29]
wire data_mem_1_1__T_135_mask; // @[el2_ifu_ic_mem.scala 230:29]
wire data_mem_1_1__T_135_en; // @[el2_ifu_ic_mem.scala 230:29]
wire [70:0] data_mem_1_1__T_142_data; // @[el2_ifu_ic_mem.scala 230:29]
wire [8:0] data_mem_1_1__T_142_addr; // @[el2_ifu_ic_mem.scala 230:29]
wire data_mem_1_1__T_142_mask; // @[el2_ifu_ic_mem.scala 230:29]
wire data_mem_1_1__T_142_en; // @[el2_ifu_ic_mem.scala 230:29]
wire [70:0] data_mem_1_1__T_149_data; // @[el2_ifu_ic_mem.scala 230:29]
wire [8:0] data_mem_1_1__T_149_addr; // @[el2_ifu_ic_mem.scala 230:29]
wire data_mem_1_1__T_149_mask; // @[el2_ifu_ic_mem.scala 230:29]
wire data_mem_1_1__T_149_en; // @[el2_ifu_ic_mem.scala 230:29]
wire [70:0] data_mem_1_1__T_156_data; // @[el2_ifu_ic_mem.scala 230:29]
wire [8:0] data_mem_1_1__T_156_addr; // @[el2_ifu_ic_mem.scala 230:29]
wire data_mem_1_1__T_156_mask; // @[el2_ifu_ic_mem.scala 230:29]
wire data_mem_1_1__T_156_en; // @[el2_ifu_ic_mem.scala 230:29]
reg [8:0] data_mem_1_1__T_137_addr_pipe_0;
reg [8:0] data_mem_1_1__T_144_addr_pipe_0;
reg [8:0] data_mem_1_1__T_151_addr_pipe_0;
reg [8:0] data_mem_1_1__T_158_addr_pipe_0;
wire _T = ~io_ic_debug_tag_array; // @[el2_ifu_ic_mem.scala 195:70]
wire _T_1 = io_ic_debug_rd_en & _T; // @[el2_ifu_ic_mem.scala 195:68]
wire [1:0] _T_3 = {_T_1,_T_1}; // @[Cat.scala 29:58]
wire [1:0] ic_debug_rd_way_en = _T_3 & io_ic_debug_way; // @[el2_ifu_ic_mem.scala 195:94]
wire _T_5 = io_ic_debug_wr_en & _T; // @[el2_ifu_ic_mem.scala 196:68]
wire [1:0] _T_7 = {_T_5,_T_5}; // @[Cat.scala 29:58]
wire [1:0] ic_debug_wr_way_en = _T_7 & io_ic_debug_way; // @[el2_ifu_ic_mem.scala 196:94]
wire _T_9 = ~io_ic_debug_addr[3]; // @[el2_ifu_ic_mem.scala 198:107]
wire [1:0] _T_11 = {_T_9,_T_9}; // @[Cat.scala 29:58]
wire [1:0] _T_12 = ic_debug_wr_way_en & _T_11; // @[el2_ifu_ic_mem.scala 198:36]
wire [1:0] _T_13 = io_ic_wr_en | _T_12; // @[el2_ifu_ic_mem.scala 198:16]
wire [1:0] _T_17 = {io_ic_debug_addr[3],io_ic_debug_addr[3]}; // @[Cat.scala 29:58]
wire [1:0] _T_18 = ic_debug_wr_way_en & _T_17; // @[el2_ifu_ic_mem.scala 198:36]
wire [1:0] _T_19 = io_ic_wr_en | _T_18; // @[el2_ifu_ic_mem.scala 198:16]
wire _T_23 = _T_9 & io_ic_debug_wr_en; // @[el2_ifu_ic_mem.scala 200:66]
wire [70:0] _T_25 = _T_23 ? io_ic_debug_wr_data : io_ic_wr_data_0; // @[el2_ifu_ic_mem.scala 200:8]
wire _T_28 = io_ic_debug_addr[3] & io_ic_debug_wr_en; // @[el2_ifu_ic_mem.scala 200:66]
wire [70:0] _T_30 = _T_28 ? io_ic_debug_wr_data : io_ic_wr_data_1; // @[el2_ifu_ic_mem.scala 200:8]
wire _T_32 = io_ic_debug_rd_en | io_ic_debug_wr_en; // @[el2_ifu_ic_mem.scala 201:49]
wire [11:0] _T_35 = {io_ic_debug_addr[12:3],2'h0}; // @[Cat.scala 29:58]
wire [11:0] _T_37 = _T_32 ? _T_35 : io_ic_rw_addr[12:1]; // @[el2_ifu_ic_mem.scala 201:29]
wire [12:0] ic_rw_addr_q = {_T_37,1'h0}; // @[Cat.scala 29:58]
wire _T_38 = io_ic_rd_en | io_ic_debug_rd_en; // @[el2_ifu_ic_mem.scala 202:44]
wire _T_39 = |io_ic_wr_en; // @[el2_ifu_ic_mem.scala 202:82]
wire _T_40 = ~_T_39; // @[el2_ifu_ic_mem.scala 202:68]
wire ic_rd_en_with_debug = _T_38 & _T_40; // @[el2_ifu_ic_mem.scala 202:66]
wire _T_43 = ~ic_rw_addr_q[3]; // @[el2_ifu_ic_mem.scala 204:15]
wire _T_47 = ic_rw_addr_q[2:1] == 2'h3; // @[el2_ifu_ic_mem.scala 205:55]
wire _T_48 = ic_rw_addr_q[3] & _T_47; // @[el2_ifu_ic_mem.scala 205:36]
wire _T_58 = _T_43 & _T_47; // @[el2_ifu_ic_mem.scala 207:37]
wire _T_95 = ic_rw_addr_q[3] | _T_58; // @[Mux.scala 27:72]
wire ic_b_rden_0 = _T_95 & ic_rd_en_with_debug; // @[el2_ifu_ic_mem.scala 207:107]
wire [1:0] _T_99 = {ic_b_rden_0,ic_b_rden_0}; // @[Cat.scala 29:58]
wire [1:0] _GEN_24 = {{1'd0}, io_clk_override}; // @[el2_ifu_ic_mem.scala 210:62]
wire [1:0] _T_100 = _T_99 | _GEN_24; // @[el2_ifu_ic_mem.scala 210:62]
wire [1:0] _T_101 = _T_100 | _T_19; // @[el2_ifu_ic_mem.scala 210:80]
wire [1:0] _T_105 = _T_100 | _T_13; // @[el2_ifu_ic_mem.scala 212:82]
wire [1:0] _T_106 = _T_105 | _T_101; // @[el2_ifu_ic_mem.scala 212:101]
wire [8:0] ic_rw_addr_q_inc = ic_rw_addr_q[12:4] + 9'h1; // @[el2_ifu_ic_mem.scala 215:77]
wire _T_113 = _T_48 & ic_rd_en_with_debug; // @[el2_ifu_ic_mem.scala 216:82]
wire ic_rw_addr_wrap = _T_113 & _T_40; // @[el2_ifu_ic_mem.scala 216:104]
reg [12:0] ic_rw_addr_ff; // @[el2_ifu_ic_mem.scala 219:30]
reg [1:0] ic_debug_rd_way_en_ff; // @[el2_ifu_ic_mem.scala 221:38]
reg ic_debug_rd_en_ff; // @[el2_ifu_ic_mem.scala 222:34]
wire _T_122 = ~ic_rw_addr_wrap; // @[el2_ifu_ic_mem.scala 226:31]
wire [8:0] _T_126 = {ic_rw_addr_q[12:6],ic_rw_addr_q_inc[5:4]}; // @[Cat.scala 29:58]
wire [8:0] _T_127 = _T_122 ? ic_rw_addr_q[12:4] : _T_126; // @[el2_ifu_ic_mem.scala 226:30]
wire [12:0] ic_rw_addr_bank_q_0 = {{4'd0}, _T_127}; // @[el2_ifu_ic_mem.scala 225:31 el2_ifu_ic_mem.scala 226:24]
wire [12:0] ic_rw_addr_bank_q_1 = {{4'd0}, ic_rw_addr_q[12:4]}; // @[el2_ifu_ic_mem.scala 225:31 el2_ifu_ic_mem.scala 227:24]
wire _T_160 = ~ic_rw_addr_ff[3]; // @[el2_ifu_ic_mem.scala 244:71]
wire [9:0] _T_170 = {_T_160,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160}; // @[Cat.scala 29:58]
wire [18:0] _T_179 = {_T_170,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160}; // @[Cat.scala 29:58]
wire [27:0] _T_188 = {_T_179,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160}; // @[Cat.scala 29:58]
wire [36:0] _T_197 = {_T_188,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160}; // @[Cat.scala 29:58]
wire [45:0] _T_206 = {_T_197,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160}; // @[Cat.scala 29:58]
wire [54:0] _T_215 = {_T_206,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160}; // @[Cat.scala 29:58]
wire [63:0] _T_224 = {_T_215,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160}; // @[Cat.scala 29:58]
wire [70:0] _T_231 = {_T_224,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160}; // @[Cat.scala 29:58]
wire [70:0] wb_dout_0_0 = data_mem_0_0__T_137_data; // @[el2_ifu_ic_mem.scala 232:21 el2_ifu_ic_mem.scala 235:19 el2_ifu_ic_mem.scala 239:19]
wire [70:0] _T_232 = _T_231 & wb_dout_0_0; // @[el2_ifu_ic_mem.scala 244:78]
wire [9:0] _T_244 = {ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3]}; // @[Cat.scala 29:58]
wire [18:0] _T_253 = {_T_244,ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3]}; // @[Cat.scala 29:58]
wire [27:0] _T_262 = {_T_253,ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3]}; // @[Cat.scala 29:58]
wire [36:0] _T_271 = {_T_262,ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3]}; // @[Cat.scala 29:58]
wire [45:0] _T_280 = {_T_271,ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3]}; // @[Cat.scala 29:58]
wire [54:0] _T_289 = {_T_280,ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3]}; // @[Cat.scala 29:58]
wire [63:0] _T_298 = {_T_289,ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3]}; // @[Cat.scala 29:58]
wire [70:0] _T_305 = {_T_298,ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3]}; // @[Cat.scala 29:58]
wire [70:0] wb_dout_0_1 = data_mem_0_1__T_144_data; // @[el2_ifu_ic_mem.scala 232:21 el2_ifu_ic_mem.scala 235:19 el2_ifu_ic_mem.scala 239:19]
wire [70:0] _T_306 = _T_305 & wb_dout_0_1; // @[el2_ifu_ic_mem.scala 244:78]
wire [70:0] wb_dout_way_pre_lower_0 = _T_232 | _T_306; // @[el2_ifu_ic_mem.scala 244:102]
wire [70:0] wb_dout_1_0 = data_mem_1_0__T_151_data; // @[el2_ifu_ic_mem.scala 232:21 el2_ifu_ic_mem.scala 235:19 el2_ifu_ic_mem.scala 239:19]
wire [70:0] _T_380 = _T_231 & wb_dout_1_0; // @[el2_ifu_ic_mem.scala 244:78]
wire [70:0] wb_dout_1_1 = data_mem_1_1__T_158_data; // @[el2_ifu_ic_mem.scala 232:21 el2_ifu_ic_mem.scala 235:19 el2_ifu_ic_mem.scala 239:19]
wire [70:0] _T_454 = _T_305 & wb_dout_1_1; // @[el2_ifu_ic_mem.scala 244:78]
wire [70:0] wb_dout_way_pre_lower_1 = _T_380 | _T_454; // @[el2_ifu_ic_mem.scala 244:102]
wire _T_457 = 1'h0 - 1'h1; // @[el2_ifu_ic_mem.scala 248:77]
wire _T_458 = ic_rw_addr_ff[3] == _T_457; // @[el2_ifu_ic_mem.scala 248:71]
wire [9:0] _T_468 = {_T_458,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458}; // @[Cat.scala 29:58]
wire [18:0] _T_477 = {_T_468,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458}; // @[Cat.scala 29:58]
wire [27:0] _T_486 = {_T_477,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458}; // @[Cat.scala 29:58]
wire [36:0] _T_495 = {_T_486,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458}; // @[Cat.scala 29:58]
wire [45:0] _T_504 = {_T_495,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458}; // @[Cat.scala 29:58]
wire [54:0] _T_513 = {_T_504,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458}; // @[Cat.scala 29:58]
wire [63:0] _T_522 = {_T_513,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458}; // @[Cat.scala 29:58]
wire [70:0] _T_529 = {_T_522,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458}; // @[Cat.scala 29:58]
wire [70:0] _T_530 = _T_529 & wb_dout_0_0; // @[el2_ifu_ic_mem.scala 248:82]
wire [70:0] _T_606 = _T_231 & wb_dout_0_1; // @[el2_ifu_ic_mem.scala 248:82]
wire [70:0] wb_dout_way_pre_upper_0 = _T_530 | _T_606; // @[el2_ifu_ic_mem.scala 248:106]
wire [70:0] _T_682 = _T_529 & wb_dout_1_0; // @[el2_ifu_ic_mem.scala 248:82]
wire [70:0] _T_758 = _T_231 & wb_dout_1_1; // @[el2_ifu_ic_mem.scala 248:82]
wire [70:0] wb_dout_way_pre_upper_1 = _T_682 | _T_758; // @[el2_ifu_ic_mem.scala 248:106]
wire [141:0] wb_dout_way_pre_0 = {wb_dout_way_pre_upper_0,wb_dout_way_pre_lower_0}; // @[Cat.scala 29:58]
wire [141:0] wb_dout_way_pre_1 = {wb_dout_way_pre_upper_1,wb_dout_way_pre_lower_1}; // @[Cat.scala 29:58]
wire _T_760 = ic_rw_addr_ff[2:1] == 2'h0; // @[el2_ifu_ic_mem.scala 254:36]
wire [9:0] _T_770 = {_T_760,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760}; // @[Cat.scala 29:58]
wire [18:0] _T_779 = {_T_770,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760}; // @[Cat.scala 29:58]
wire [27:0] _T_788 = {_T_779,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760}; // @[Cat.scala 29:58]
wire [36:0] _T_797 = {_T_788,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760}; // @[Cat.scala 29:58]
wire [45:0] _T_806 = {_T_797,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760}; // @[Cat.scala 29:58]
wire [54:0] _T_815 = {_T_806,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760}; // @[Cat.scala 29:58]
wire [63:0] _T_824 = {_T_815,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760}; // @[Cat.scala 29:58]
wire [63:0] _T_826 = _T_824 & wb_dout_way_pre_0[63:0]; // @[el2_ifu_ic_mem.scala 254:44]
wire _T_828 = ic_rw_addr_ff[2:1] == 2'h1; // @[el2_ifu_ic_mem.scala 255:36]
wire [9:0] _T_838 = {_T_828,_T_828,_T_828,_T_828,_T_828,_T_828,_T_828,_T_828,_T_828,_T_828}; // @[Cat.scala 29:58]
wire [18:0] _T_847 = {_T_838,_T_828,_T_828,_T_828,_T_828,_T_828,_T_828,_T_828,_T_828,_T_828}; // @[Cat.scala 29:58]
wire [27:0] _T_856 = {_T_847,_T_828,_T_828,_T_828,_T_828,_T_828,_T_828,_T_828,_T_828,_T_828}; // @[Cat.scala 29:58]
wire [36:0] _T_865 = {_T_856,_T_828,_T_828,_T_828,_T_828,_T_828,_T_828,_T_828,_T_828,_T_828}; // @[Cat.scala 29:58]
wire [45:0] _T_874 = {_T_865,_T_828,_T_828,_T_828,_T_828,_T_828,_T_828,_T_828,_T_828,_T_828}; // @[Cat.scala 29:58]
wire [54:0] _T_883 = {_T_874,_T_828,_T_828,_T_828,_T_828,_T_828,_T_828,_T_828,_T_828,_T_828}; // @[Cat.scala 29:58]
wire [63:0] _T_892 = {_T_883,_T_828,_T_828,_T_828,_T_828,_T_828,_T_828,_T_828,_T_828,_T_828}; // @[Cat.scala 29:58]
wire [63:0] _T_895 = {wb_dout_way_pre_0[86:71],wb_dout_way_pre_0[63:16]}; // @[Cat.scala 29:58]
wire [63:0] _T_896 = _T_892 & _T_895; // @[el2_ifu_ic_mem.scala 255:44]
wire [63:0] _T_897 = _T_826 | _T_896; // @[el2_ifu_ic_mem.scala 254:71]
wire _T_899 = ic_rw_addr_ff[2:1] == 2'h2; // @[el2_ifu_ic_mem.scala 256:36]
wire [9:0] _T_909 = {_T_899,_T_899,_T_899,_T_899,_T_899,_T_899,_T_899,_T_899,_T_899,_T_899}; // @[Cat.scala 29:58]
wire [18:0] _T_918 = {_T_909,_T_899,_T_899,_T_899,_T_899,_T_899,_T_899,_T_899,_T_899,_T_899}; // @[Cat.scala 29:58]
wire [27:0] _T_927 = {_T_918,_T_899,_T_899,_T_899,_T_899,_T_899,_T_899,_T_899,_T_899,_T_899}; // @[Cat.scala 29:58]
wire [36:0] _T_936 = {_T_927,_T_899,_T_899,_T_899,_T_899,_T_899,_T_899,_T_899,_T_899,_T_899}; // @[Cat.scala 29:58]
wire [45:0] _T_945 = {_T_936,_T_899,_T_899,_T_899,_T_899,_T_899,_T_899,_T_899,_T_899,_T_899}; // @[Cat.scala 29:58]
wire [54:0] _T_954 = {_T_945,_T_899,_T_899,_T_899,_T_899,_T_899,_T_899,_T_899,_T_899,_T_899}; // @[Cat.scala 29:58]
wire [63:0] _T_963 = {_T_954,_T_899,_T_899,_T_899,_T_899,_T_899,_T_899,_T_899,_T_899,_T_899}; // @[Cat.scala 29:58]
wire [63:0] _T_966 = {wb_dout_way_pre_0[102:71],wb_dout_way_pre_0[63:32]}; // @[Cat.scala 29:58]
wire [63:0] _T_967 = _T_963 & _T_966; // @[el2_ifu_ic_mem.scala 256:44]
wire [63:0] _T_968 = _T_897 | _T_967; // @[el2_ifu_ic_mem.scala 255:122]
wire _T_970 = ic_rw_addr_ff[2:1] == 2'h3; // @[el2_ifu_ic_mem.scala 257:36]
wire [9:0] _T_980 = {_T_970,_T_970,_T_970,_T_970,_T_970,_T_970,_T_970,_T_970,_T_970,_T_970}; // @[Cat.scala 29:58]
wire [18:0] _T_989 = {_T_980,_T_970,_T_970,_T_970,_T_970,_T_970,_T_970,_T_970,_T_970,_T_970}; // @[Cat.scala 29:58]
wire [27:0] _T_998 = {_T_989,_T_970,_T_970,_T_970,_T_970,_T_970,_T_970,_T_970,_T_970,_T_970}; // @[Cat.scala 29:58]
wire [36:0] _T_1007 = {_T_998,_T_970,_T_970,_T_970,_T_970,_T_970,_T_970,_T_970,_T_970,_T_970}; // @[Cat.scala 29:58]
wire [45:0] _T_1016 = {_T_1007,_T_970,_T_970,_T_970,_T_970,_T_970,_T_970,_T_970,_T_970,_T_970}; // @[Cat.scala 29:58]
wire [54:0] _T_1025 = {_T_1016,_T_970,_T_970,_T_970,_T_970,_T_970,_T_970,_T_970,_T_970,_T_970}; // @[Cat.scala 29:58]
wire [63:0] _T_1034 = {_T_1025,_T_970,_T_970,_T_970,_T_970,_T_970,_T_970,_T_970,_T_970,_T_970}; // @[Cat.scala 29:58]
wire [63:0] _T_1037 = {wb_dout_way_pre_0[118:71],wb_dout_way_pre_0[63:48]}; // @[Cat.scala 29:58]
wire [63:0] _T_1038 = _T_1034 & _T_1037; // @[el2_ifu_ic_mem.scala 257:44]
wire [63:0] wb_dout_way_0 = _T_968 | _T_1038; // @[el2_ifu_ic_mem.scala 256:122]
wire [63:0] _T_1106 = _T_824 & wb_dout_way_pre_1[63:0]; // @[el2_ifu_ic_mem.scala 254:44]
wire [63:0] _T_1175 = {wb_dout_way_pre_1[86:71],wb_dout_way_pre_1[63:16]}; // @[Cat.scala 29:58]
wire [63:0] _T_1176 = _T_892 & _T_1175; // @[el2_ifu_ic_mem.scala 255:44]
wire [63:0] _T_1177 = _T_1106 | _T_1176; // @[el2_ifu_ic_mem.scala 254:71]
wire [63:0] _T_1246 = {wb_dout_way_pre_1[102:71],wb_dout_way_pre_1[63:32]}; // @[Cat.scala 29:58]
wire [63:0] _T_1247 = _T_963 & _T_1246; // @[el2_ifu_ic_mem.scala 256:44]
wire [63:0] _T_1248 = _T_1177 | _T_1247; // @[el2_ifu_ic_mem.scala 255:122]
wire [63:0] _T_1317 = {wb_dout_way_pre_1[118:71],wb_dout_way_pre_1[63:48]}; // @[Cat.scala 29:58]
wire [63:0] _T_1318 = _T_1034 & _T_1317; // @[el2_ifu_ic_mem.scala 257:44]
wire [63:0] wb_dout_way_1 = _T_1248 | _T_1318; // @[el2_ifu_ic_mem.scala 256:122]
wire [1:0] ic_rd_hit_q = ic_debug_rd_en_ff ? ic_debug_rd_way_en_ff : io_ic_rd_hit; // @[el2_ifu_ic_mem.scala 260:24]
wire [63:0] wb_dout_way_with_premux_0 = io_ic_sel_premux_data ? io_ic_premux_data : wb_dout_way_0; // @[el2_ifu_ic_mem.scala 261:52]
wire [63:0] wb_dout_way_with_premux_1 = io_ic_sel_premux_data ? io_ic_premux_data : wb_dout_way_1; // @[el2_ifu_ic_mem.scala 261:52]
wire _T_1321 = ic_rd_hit_q[0] | io_ic_sel_premux_data; // @[el2_ifu_ic_mem.scala 267:79]
wire _T_1323 = ic_rd_hit_q[1] | io_ic_sel_premux_data; // @[el2_ifu_ic_mem.scala 267:79]
wire [9:0] _T_1333 = {_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321}; // @[Cat.scala 29:58]
wire [18:0] _T_1342 = {_T_1333,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321}; // @[Cat.scala 29:58]
wire [27:0] _T_1351 = {_T_1342,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321}; // @[Cat.scala 29:58]
wire [36:0] _T_1360 = {_T_1351,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321}; // @[Cat.scala 29:58]
wire [45:0] _T_1369 = {_T_1360,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321}; // @[Cat.scala 29:58]
wire [54:0] _T_1378 = {_T_1369,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321}; // @[Cat.scala 29:58]
wire [63:0] _T_1387 = {_T_1378,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321}; // @[Cat.scala 29:58]
wire [63:0] _T_1388 = _T_1387 & wb_dout_way_with_premux_0; // @[el2_lib.scala 190:94]
wire [9:0] _T_1398 = {_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323}; // @[Cat.scala 29:58]
wire [18:0] _T_1407 = {_T_1398,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323}; // @[Cat.scala 29:58]
wire [27:0] _T_1416 = {_T_1407,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323}; // @[Cat.scala 29:58]
wire [36:0] _T_1425 = {_T_1416,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323}; // @[Cat.scala 29:58]
wire [45:0] _T_1434 = {_T_1425,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323}; // @[Cat.scala 29:58]
wire [54:0] _T_1443 = {_T_1434,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323}; // @[Cat.scala 29:58]
wire [63:0] _T_1452 = {_T_1443,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323}; // @[Cat.scala 29:58]
wire [63:0] _T_1453 = _T_1452 & wb_dout_way_with_premux_1; // @[el2_lib.scala 190:94]
wire [9:0] _T_1468 = {ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0]}; // @[Cat.scala 29:58]
wire [18:0] _T_1477 = {_T_1468,ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0]}; // @[Cat.scala 29:58]
wire [27:0] _T_1486 = {_T_1477,ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0]}; // @[Cat.scala 29:58]
wire [36:0] _T_1495 = {_T_1486,ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0]}; // @[Cat.scala 29:58]
wire [45:0] _T_1504 = {_T_1495,ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0]}; // @[Cat.scala 29:58]
wire [54:0] _T_1513 = {_T_1504,ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0]}; // @[Cat.scala 29:58]
wire [63:0] _T_1522 = {_T_1513,ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0]}; // @[Cat.scala 29:58]
wire [70:0] _T_1529 = {_T_1522,ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0]}; // @[Cat.scala 29:58]
wire [70:0] _T_1530 = _T_1529 & wb_dout_way_pre_0[70:0]; // @[el2_lib.scala 190:94]
wire [9:0] _T_1540 = {ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1]}; // @[Cat.scala 29:58]
wire [18:0] _T_1549 = {_T_1540,ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1]}; // @[Cat.scala 29:58]
wire [27:0] _T_1558 = {_T_1549,ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1]}; // @[Cat.scala 29:58]
wire [36:0] _T_1567 = {_T_1558,ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1]}; // @[Cat.scala 29:58]
wire [45:0] _T_1576 = {_T_1567,ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1]}; // @[Cat.scala 29:58]
wire [54:0] _T_1585 = {_T_1576,ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1]}; // @[Cat.scala 29:58]
wire [63:0] _T_1594 = {_T_1585,ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1]}; // @[Cat.scala 29:58]
wire [70:0] _T_1601 = {_T_1594,ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1]}; // @[Cat.scala 29:58]
wire [70:0] _T_1602 = _T_1601 & wb_dout_way_pre_1[70:0]; // @[el2_lib.scala 190:94]
assign data_mem_0_0__T_137_addr = data_mem_0_0__T_137_addr_pipe_0;
assign data_mem_0_0__T_137_data = data_mem_0_0[data_mem_0_0__T_137_addr]; // @[el2_ifu_ic_mem.scala 230:29]
assign data_mem_0_0__T_144_addr = data_mem_0_0__T_144_addr_pipe_0;
assign data_mem_0_0__T_144_data = data_mem_0_0[data_mem_0_0__T_144_addr]; // @[el2_ifu_ic_mem.scala 230:29]
assign data_mem_0_0__T_151_addr = data_mem_0_0__T_151_addr_pipe_0;
assign data_mem_0_0__T_151_data = data_mem_0_0[data_mem_0_0__T_151_addr]; // @[el2_ifu_ic_mem.scala 230:29]
assign data_mem_0_0__T_158_addr = data_mem_0_0__T_158_addr_pipe_0;
assign data_mem_0_0__T_158_data = data_mem_0_0[data_mem_0_0__T_158_addr]; // @[el2_ifu_ic_mem.scala 230:29]
assign data_mem_0_0__T_130_data = _T_28 ? io_ic_debug_wr_data : io_ic_wr_data_1;
assign data_mem_0_0__T_130_addr = ic_rw_addr_bank_q_0[12:4];
assign data_mem_0_0__T_130_mask = 1'h1;
assign data_mem_0_0__T_130_en = 1'h1;
assign data_mem_0_0__T_135_data = _T_28 ? io_ic_debug_wr_data : io_ic_wr_data_1;
assign data_mem_0_0__T_135_addr = ic_rw_addr_bank_q_0[12:4];
assign data_mem_0_0__T_135_mask = 1'h1;
assign data_mem_0_0__T_135_en = _T_30[0] & _T_101[0];
assign data_mem_0_0__T_142_data = 71'h0;
assign data_mem_0_0__T_142_addr = ic_rw_addr_bank_q_1[12:4];
assign data_mem_0_0__T_142_mask = 1'h0;
assign data_mem_0_0__T_142_en = _T_30[1] & _T_101[1];
assign data_mem_0_0__T_149_data = 71'h0;
assign data_mem_0_0__T_149_addr = ic_rw_addr_bank_q_0[12:4];
assign data_mem_0_0__T_149_mask = 1'h0;
assign data_mem_0_0__T_149_en = _T_25[0] & _T_106[0];
assign data_mem_0_0__T_156_data = 71'h0;
assign data_mem_0_0__T_156_addr = ic_rw_addr_bank_q_1[12:4];
assign data_mem_0_0__T_156_mask = 1'h0;
assign data_mem_0_0__T_156_en = _T_25[1] & _T_106[1];
assign data_mem_0_1__T_137_addr = data_mem_0_1__T_137_addr_pipe_0;
assign data_mem_0_1__T_137_data = data_mem_0_1[data_mem_0_1__T_137_addr]; // @[el2_ifu_ic_mem.scala 230:29]
assign data_mem_0_1__T_144_addr = data_mem_0_1__T_144_addr_pipe_0;
assign data_mem_0_1__T_144_data = data_mem_0_1[data_mem_0_1__T_144_addr]; // @[el2_ifu_ic_mem.scala 230:29]
assign data_mem_0_1__T_151_addr = data_mem_0_1__T_151_addr_pipe_0;
assign data_mem_0_1__T_151_data = data_mem_0_1[data_mem_0_1__T_151_addr]; // @[el2_ifu_ic_mem.scala 230:29]
assign data_mem_0_1__T_158_addr = data_mem_0_1__T_158_addr_pipe_0;
assign data_mem_0_1__T_158_data = data_mem_0_1[data_mem_0_1__T_158_addr]; // @[el2_ifu_ic_mem.scala 230:29]
assign data_mem_0_1__T_130_data = 71'h0;
assign data_mem_0_1__T_130_addr = ic_rw_addr_bank_q_0[12:4];
assign data_mem_0_1__T_130_mask = 1'h0;
assign data_mem_0_1__T_130_en = 1'h1;
assign data_mem_0_1__T_135_data = 71'h0;
assign data_mem_0_1__T_135_addr = ic_rw_addr_bank_q_0[12:4];
assign data_mem_0_1__T_135_mask = 1'h0;
assign data_mem_0_1__T_135_en = _T_30[0] & _T_101[0];
assign data_mem_0_1__T_142_data = 71'h0;
assign data_mem_0_1__T_142_addr = ic_rw_addr_bank_q_1[12:4];
assign data_mem_0_1__T_142_mask = 1'h0;
assign data_mem_0_1__T_142_en = _T_30[1] & _T_101[1];
assign data_mem_0_1__T_149_data = _T_28 ? io_ic_debug_wr_data : io_ic_wr_data_1;
assign data_mem_0_1__T_149_addr = ic_rw_addr_bank_q_0[12:4];
assign data_mem_0_1__T_149_mask = 1'h1;
assign data_mem_0_1__T_149_en = _T_25[0] & _T_106[0];
assign data_mem_0_1__T_156_data = 71'h0;
assign data_mem_0_1__T_156_addr = ic_rw_addr_bank_q_1[12:4];
assign data_mem_0_1__T_156_mask = 1'h0;
assign data_mem_0_1__T_156_en = _T_25[1] & _T_106[1];
assign data_mem_1_0__T_137_addr = data_mem_1_0__T_137_addr_pipe_0;
assign data_mem_1_0__T_137_data = data_mem_1_0[data_mem_1_0__T_137_addr]; // @[el2_ifu_ic_mem.scala 230:29]
assign data_mem_1_0__T_144_addr = data_mem_1_0__T_144_addr_pipe_0;
assign data_mem_1_0__T_144_data = data_mem_1_0[data_mem_1_0__T_144_addr]; // @[el2_ifu_ic_mem.scala 230:29]
assign data_mem_1_0__T_151_addr = data_mem_1_0__T_151_addr_pipe_0;
assign data_mem_1_0__T_151_data = data_mem_1_0[data_mem_1_0__T_151_addr]; // @[el2_ifu_ic_mem.scala 230:29]
assign data_mem_1_0__T_158_addr = data_mem_1_0__T_158_addr_pipe_0;
assign data_mem_1_0__T_158_data = data_mem_1_0[data_mem_1_0__T_158_addr]; // @[el2_ifu_ic_mem.scala 230:29]
assign data_mem_1_0__T_130_data = 71'h0;
assign data_mem_1_0__T_130_addr = ic_rw_addr_bank_q_0[12:4];
assign data_mem_1_0__T_130_mask = 1'h0;
assign data_mem_1_0__T_130_en = 1'h1;
assign data_mem_1_0__T_135_data = 71'h0;
assign data_mem_1_0__T_135_addr = ic_rw_addr_bank_q_0[12:4];
assign data_mem_1_0__T_135_mask = 1'h0;
assign data_mem_1_0__T_135_en = _T_30[0] & _T_101[0];
assign data_mem_1_0__T_142_data = _T_23 ? io_ic_debug_wr_data : io_ic_wr_data_0;
assign data_mem_1_0__T_142_addr = ic_rw_addr_bank_q_1[12:4];
assign data_mem_1_0__T_142_mask = 1'h1;
assign data_mem_1_0__T_142_en = _T_30[1] & _T_101[1];
assign data_mem_1_0__T_149_data = 71'h0;
assign data_mem_1_0__T_149_addr = ic_rw_addr_bank_q_0[12:4];
assign data_mem_1_0__T_149_mask = 1'h0;
assign data_mem_1_0__T_149_en = _T_25[0] & _T_106[0];
assign data_mem_1_0__T_156_data = 71'h0;
assign data_mem_1_0__T_156_addr = ic_rw_addr_bank_q_1[12:4];
assign data_mem_1_0__T_156_mask = 1'h0;
assign data_mem_1_0__T_156_en = _T_25[1] & _T_106[1];
assign data_mem_1_1__T_137_addr = data_mem_1_1__T_137_addr_pipe_0;
assign data_mem_1_1__T_137_data = data_mem_1_1[data_mem_1_1__T_137_addr]; // @[el2_ifu_ic_mem.scala 230:29]
assign data_mem_1_1__T_144_addr = data_mem_1_1__T_144_addr_pipe_0;
assign data_mem_1_1__T_144_data = data_mem_1_1[data_mem_1_1__T_144_addr]; // @[el2_ifu_ic_mem.scala 230:29]
assign data_mem_1_1__T_151_addr = data_mem_1_1__T_151_addr_pipe_0;
assign data_mem_1_1__T_151_data = data_mem_1_1[data_mem_1_1__T_151_addr]; // @[el2_ifu_ic_mem.scala 230:29]
assign data_mem_1_1__T_158_addr = data_mem_1_1__T_158_addr_pipe_0;
assign data_mem_1_1__T_158_data = data_mem_1_1[data_mem_1_1__T_158_addr]; // @[el2_ifu_ic_mem.scala 230:29]
assign data_mem_1_1__T_130_data = 71'h0;
assign data_mem_1_1__T_130_addr = ic_rw_addr_bank_q_0[12:4];
assign data_mem_1_1__T_130_mask = 1'h0;
assign data_mem_1_1__T_130_en = 1'h1;
assign data_mem_1_1__T_135_data = 71'h0;
assign data_mem_1_1__T_135_addr = ic_rw_addr_bank_q_0[12:4];
assign data_mem_1_1__T_135_mask = 1'h0;
assign data_mem_1_1__T_135_en = _T_30[0] & _T_101[0];
assign data_mem_1_1__T_142_data = 71'h0;
assign data_mem_1_1__T_142_addr = ic_rw_addr_bank_q_1[12:4];
assign data_mem_1_1__T_142_mask = 1'h0;
assign data_mem_1_1__T_142_en = _T_30[1] & _T_101[1];
assign data_mem_1_1__T_149_data = 71'h0;
assign data_mem_1_1__T_149_addr = ic_rw_addr_bank_q_0[12:4];
assign data_mem_1_1__T_149_mask = 1'h0;
assign data_mem_1_1__T_149_en = _T_25[0] & _T_106[0];
assign data_mem_1_1__T_156_data = _T_23 ? io_ic_debug_wr_data : io_ic_wr_data_0;
assign data_mem_1_1__T_156_addr = ic_rw_addr_bank_q_1[12:4];
assign data_mem_1_1__T_156_mask = 1'h1;
assign data_mem_1_1__T_156_en = _T_25[1] & _T_106[1];
assign io_ic_rd_data = _T_1388 | _T_1453; // @[el2_ifu_ic_mem.scala 267:17]
assign io_ic_debug_rd_data = _T_1530 | _T_1602; // @[el2_ifu_ic_mem.scala 263:23 el2_ifu_ic_mem.scala 269:23]
assign io_ic_parerr = 2'h0; // @[el2_ifu_ic_mem.scala 264:16]
assign io_ic_eccerr = 2'h0; // @[el2_ifu_ic_mem.scala 265:16]
assign io_test_port2 = 1'h0; // @[el2_ifu_ic_mem.scala 273:17]
assign io_test_port_0_0 = data_mem_0_0__T_137_data; // @[el2_ifu_ic_mem.scala 274:16]
assign io_test_port_0_1 = data_mem_0_1__T_144_data; // @[el2_ifu_ic_mem.scala 274:16]
assign io_test_port_1_0 = data_mem_1_0__T_151_data; // @[el2_ifu_ic_mem.scala 274:16]
assign io_test_port_1_1 = data_mem_1_1__T_158_data; // @[el2_ifu_ic_mem.scala 274:16]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_MEM_INIT
_RAND_0 = {3{`RANDOM}};
for (initvar = 0; initvar < 512; initvar = initvar+1)
data_mem_0_0[initvar] = _RAND_0[70:0];
_RAND_5 = {3{`RANDOM}};
for (initvar = 0; initvar < 512; initvar = initvar+1)
data_mem_0_1[initvar] = _RAND_5[70:0];
_RAND_10 = {3{`RANDOM}};
for (initvar = 0; initvar < 512; initvar = initvar+1)
data_mem_1_0[initvar] = _RAND_10[70:0];
_RAND_15 = {3{`RANDOM}};
for (initvar = 0; initvar < 512; initvar = initvar+1)
data_mem_1_1[initvar] = _RAND_15[70:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
data_mem_0_0__T_137_addr_pipe_0 = _RAND_1[8:0];
_RAND_2 = {1{`RANDOM}};
data_mem_0_0__T_144_addr_pipe_0 = _RAND_2[8:0];
_RAND_3 = {1{`RANDOM}};
data_mem_0_0__T_151_addr_pipe_0 = _RAND_3[8:0];
_RAND_4 = {1{`RANDOM}};
data_mem_0_0__T_158_addr_pipe_0 = _RAND_4[8:0];
_RAND_6 = {1{`RANDOM}};
data_mem_0_1__T_137_addr_pipe_0 = _RAND_6[8:0];
_RAND_7 = {1{`RANDOM}};
data_mem_0_1__T_144_addr_pipe_0 = _RAND_7[8:0];
_RAND_8 = {1{`RANDOM}};
data_mem_0_1__T_151_addr_pipe_0 = _RAND_8[8:0];
_RAND_9 = {1{`RANDOM}};
data_mem_0_1__T_158_addr_pipe_0 = _RAND_9[8:0];
_RAND_11 = {1{`RANDOM}};
data_mem_1_0__T_137_addr_pipe_0 = _RAND_11[8:0];
_RAND_12 = {1{`RANDOM}};
data_mem_1_0__T_144_addr_pipe_0 = _RAND_12[8:0];
_RAND_13 = {1{`RANDOM}};
data_mem_1_0__T_151_addr_pipe_0 = _RAND_13[8:0];
_RAND_14 = {1{`RANDOM}};
data_mem_1_0__T_158_addr_pipe_0 = _RAND_14[8:0];
_RAND_16 = {1{`RANDOM}};
data_mem_1_1__T_137_addr_pipe_0 = _RAND_16[8:0];
_RAND_17 = {1{`RANDOM}};
data_mem_1_1__T_144_addr_pipe_0 = _RAND_17[8:0];
_RAND_18 = {1{`RANDOM}};
data_mem_1_1__T_151_addr_pipe_0 = _RAND_18[8:0];
_RAND_19 = {1{`RANDOM}};
data_mem_1_1__T_158_addr_pipe_0 = _RAND_19[8:0];
_RAND_20 = {1{`RANDOM}};
ic_rw_addr_ff = _RAND_20[12:0];
_RAND_21 = {1{`RANDOM}};
ic_debug_rd_way_en_ff = _RAND_21[1:0];
_RAND_22 = {1{`RANDOM}};
ic_debug_rd_en_ff = _RAND_22[0:0];
`endif // RANDOMIZE_REG_INIT
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge clock) begin
if(data_mem_0_0__T_130_en & data_mem_0_0__T_130_mask) begin
data_mem_0_0[data_mem_0_0__T_130_addr] <= data_mem_0_0__T_130_data; // @[el2_ifu_ic_mem.scala 230:29]
end
if(data_mem_0_0__T_135_en & data_mem_0_0__T_135_mask) begin
data_mem_0_0[data_mem_0_0__T_135_addr] <= data_mem_0_0__T_135_data; // @[el2_ifu_ic_mem.scala 230:29]
end
if(data_mem_0_0__T_142_en & data_mem_0_0__T_142_mask) begin
data_mem_0_0[data_mem_0_0__T_142_addr] <= data_mem_0_0__T_142_data; // @[el2_ifu_ic_mem.scala 230:29]
end
if(data_mem_0_0__T_149_en & data_mem_0_0__T_149_mask) begin
data_mem_0_0[data_mem_0_0__T_149_addr] <= data_mem_0_0__T_149_data; // @[el2_ifu_ic_mem.scala 230:29]
end
if(data_mem_0_0__T_156_en & data_mem_0_0__T_156_mask) begin
data_mem_0_0[data_mem_0_0__T_156_addr] <= data_mem_0_0__T_156_data; // @[el2_ifu_ic_mem.scala 230:29]
end
data_mem_0_0__T_137_addr_pipe_0 <= ic_rw_addr_bank_q_0[12:4];
data_mem_0_0__T_144_addr_pipe_0 <= ic_rw_addr_bank_q_1[12:4];
data_mem_0_0__T_151_addr_pipe_0 <= ic_rw_addr_bank_q_0[12:4];
data_mem_0_0__T_158_addr_pipe_0 <= ic_rw_addr_bank_q_1[12:4];
if(data_mem_0_1__T_130_en & data_mem_0_1__T_130_mask) begin
data_mem_0_1[data_mem_0_1__T_130_addr] <= data_mem_0_1__T_130_data; // @[el2_ifu_ic_mem.scala 230:29]
end
if(data_mem_0_1__T_135_en & data_mem_0_1__T_135_mask) begin
data_mem_0_1[data_mem_0_1__T_135_addr] <= data_mem_0_1__T_135_data; // @[el2_ifu_ic_mem.scala 230:29]
end
if(data_mem_0_1__T_142_en & data_mem_0_1__T_142_mask) begin
data_mem_0_1[data_mem_0_1__T_142_addr] <= data_mem_0_1__T_142_data; // @[el2_ifu_ic_mem.scala 230:29]
end
if(data_mem_0_1__T_149_en & data_mem_0_1__T_149_mask) begin
data_mem_0_1[data_mem_0_1__T_149_addr] <= data_mem_0_1__T_149_data; // @[el2_ifu_ic_mem.scala 230:29]
end
if(data_mem_0_1__T_156_en & data_mem_0_1__T_156_mask) begin
data_mem_0_1[data_mem_0_1__T_156_addr] <= data_mem_0_1__T_156_data; // @[el2_ifu_ic_mem.scala 230:29]
end
data_mem_0_1__T_137_addr_pipe_0 <= ic_rw_addr_bank_q_0[12:4];
data_mem_0_1__T_144_addr_pipe_0 <= ic_rw_addr_bank_q_1[12:4];
data_mem_0_1__T_151_addr_pipe_0 <= ic_rw_addr_bank_q_0[12:4];
data_mem_0_1__T_158_addr_pipe_0 <= ic_rw_addr_bank_q_1[12:4];
if(data_mem_1_0__T_130_en & data_mem_1_0__T_130_mask) begin
data_mem_1_0[data_mem_1_0__T_130_addr] <= data_mem_1_0__T_130_data; // @[el2_ifu_ic_mem.scala 230:29]
end
if(data_mem_1_0__T_135_en & data_mem_1_0__T_135_mask) begin
data_mem_1_0[data_mem_1_0__T_135_addr] <= data_mem_1_0__T_135_data; // @[el2_ifu_ic_mem.scala 230:29]
end
if(data_mem_1_0__T_142_en & data_mem_1_0__T_142_mask) begin
data_mem_1_0[data_mem_1_0__T_142_addr] <= data_mem_1_0__T_142_data; // @[el2_ifu_ic_mem.scala 230:29]
end
if(data_mem_1_0__T_149_en & data_mem_1_0__T_149_mask) begin
data_mem_1_0[data_mem_1_0__T_149_addr] <= data_mem_1_0__T_149_data; // @[el2_ifu_ic_mem.scala 230:29]
end
if(data_mem_1_0__T_156_en & data_mem_1_0__T_156_mask) begin
data_mem_1_0[data_mem_1_0__T_156_addr] <= data_mem_1_0__T_156_data; // @[el2_ifu_ic_mem.scala 230:29]
end
data_mem_1_0__T_137_addr_pipe_0 <= ic_rw_addr_bank_q_0[12:4];
data_mem_1_0__T_144_addr_pipe_0 <= ic_rw_addr_bank_q_1[12:4];
data_mem_1_0__T_151_addr_pipe_0 <= ic_rw_addr_bank_q_0[12:4];
data_mem_1_0__T_158_addr_pipe_0 <= ic_rw_addr_bank_q_1[12:4];
if(data_mem_1_1__T_130_en & data_mem_1_1__T_130_mask) begin
data_mem_1_1[data_mem_1_1__T_130_addr] <= data_mem_1_1__T_130_data; // @[el2_ifu_ic_mem.scala 230:29]
end
if(data_mem_1_1__T_135_en & data_mem_1_1__T_135_mask) begin
data_mem_1_1[data_mem_1_1__T_135_addr] <= data_mem_1_1__T_135_data; // @[el2_ifu_ic_mem.scala 230:29]
end
if(data_mem_1_1__T_142_en & data_mem_1_1__T_142_mask) begin
data_mem_1_1[data_mem_1_1__T_142_addr] <= data_mem_1_1__T_142_data; // @[el2_ifu_ic_mem.scala 230:29]
end
if(data_mem_1_1__T_149_en & data_mem_1_1__T_149_mask) begin
data_mem_1_1[data_mem_1_1__T_149_addr] <= data_mem_1_1__T_149_data; // @[el2_ifu_ic_mem.scala 230:29]
end
if(data_mem_1_1__T_156_en & data_mem_1_1__T_156_mask) begin
data_mem_1_1[data_mem_1_1__T_156_addr] <= data_mem_1_1__T_156_data; // @[el2_ifu_ic_mem.scala 230:29]
end
data_mem_1_1__T_137_addr_pipe_0 <= ic_rw_addr_bank_q_0[12:4];
data_mem_1_1__T_144_addr_pipe_0 <= ic_rw_addr_bank_q_1[12:4];
data_mem_1_1__T_151_addr_pipe_0 <= ic_rw_addr_bank_q_0[12:4];
data_mem_1_1__T_158_addr_pipe_0 <= ic_rw_addr_bank_q_1[12:4];
if (reset) begin
ic_rw_addr_ff <= 13'h0;
end else begin
ic_rw_addr_ff <= ic_rw_addr_q;
end
if (reset) begin
ic_debug_rd_way_en_ff <= 2'h0;
end else begin
ic_debug_rd_way_en_ff <= ic_debug_rd_way_en;
end
if (reset) begin
ic_debug_rd_en_ff <= 1'h0;
end else begin
ic_debug_rd_en_ff <= io_ic_debug_rd_en;
end
end
endmodule endmodule

26
el2_ifu_ifc_ctrl.anno.json
View File

@ -21,15 +21,6 @@
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_req_f" "~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_req_f"
] ]
}, },
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_miss_f",
"sources":[
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_req_f",
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_exu_flush_final",
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ic_hit_f"
]
},
{ {
"class":"firrtl.transforms.CombinationalPath", "class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_pmu_fetch_stall", "sink":"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_pmu_fetch_stall",
@ -85,9 +76,8 @@
}, },
{ {
"class":"firrtl.transforms.CombinationalPath", "class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_uncacheable_bf", "sink":"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_region_acc_fault_bf",
"sources":[ "sources":[
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_dec_tlu_mrac_ff",
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_addr_bf", "~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_addr_bf",
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_bp_btb_target_f", "~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_bp_btb_target_f",
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_exu_flush_path_final", "~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_exu_flush_path_final",
@ -100,13 +90,17 @@
}, },
{ {
"class":"firrtl.transforms.CombinationalPath", "class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_mb_empty_mod", "sink":"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_uncacheable_bf",
"sources":[ "sources":[
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_ic_mb_empty", "~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_dec_tlu_mrac_ff",
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_addr_bf",
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_bp_btb_target_f",
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_exu_flush_path_final",
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_addr_f",
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ic_hit_f",
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_exu_flush_final", "~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_exu_flush_final",
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ic_dma_active", "~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_bp_hit_taken_f",
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_req_f", "~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_req_f"
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ic_hit_f"
] ]
}, },
{ {

385
el2_ifu_ifc_ctrl.fir
View File

@ -3,10 +3,8 @@ circuit el2_ifu_ifc_ctrl :
module el2_ifu_ifc_ctrl : module el2_ifu_ifc_ctrl :
input clock : Clock input clock : Clock
input reset : UInt<1> input reset : UInt<1>
output io : {flip free_clk : UInt<1>, flip active_clk : UInt<1>, flip rst_l : UInt<1>, flip scan_mode : UInt<1>, flip ic_hit_f : UInt<1>, flip ifu_ic_mb_empty : UInt<1>, flip ifu_fb_consume1 : UInt<1>, flip ifu_fb_consume2 : UInt<1>, flip dec_tlu_flush_noredir_wb : UInt<1>, flip exu_flush_final : UInt<1>, flip exu_flush_path_final : UInt<31>, flip ifu_bp_hit_taken_f : UInt<1>, flip ifu_bp_btb_target_f : UInt<31>, flip ic_dma_active : UInt<1>, flip ic_write_stall : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip dec_tlu_mrac_ff : UInt<32>, ifc_fetch_addr_f : UInt<31>, ifc_fetch_addr_bf : UInt<31>, ifc_fetch_req_f : UInt<1>, ifu_pmu_fetch_stall : UInt<1>, ifc_fetch_uncacheable_bf : UInt<1>, ifc_fetch_req_bf : UInt<1>, ifc_fetch_req_bf_raw : UInt<1>, ifc_iccm_access_bf : UInt<1>, ifc_region_acc_fault_bf : UInt<1>, ifc_dma_access_ok : UInt<1>, mb_empty_mod : UInt<1>, miss_f : UInt<1>} output io : {flip active_clk : UInt<1>, flip scan_mode : UInt<1>, flip ic_hit_f : UInt<1>, flip ifu_ic_mb_empty : UInt<1>, flip ifu_fb_consume1 : UInt<1>, flip ifu_fb_consume2 : UInt<1>, flip dec_tlu_flush_noredir_wb : UInt<1>, flip exu_flush_final : UInt<1>, flip exu_flush_path_final : UInt<31>, flip ifu_bp_hit_taken_f : UInt<1>, flip ifu_bp_btb_target_f : UInt<31>, flip ic_dma_active : UInt<1>, flip ic_write_stall : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip dec_tlu_mrac_ff : UInt<32>, ifc_fetch_addr_f : UInt<31>, ifc_fetch_addr_bf : UInt<31>, ifc_fetch_req_f : UInt<1>, ifu_pmu_fetch_stall : UInt<1>, ifc_fetch_uncacheable_bf : UInt<1>, ifc_fetch_req_bf : UInt<1>, ifc_fetch_req_bf_raw : UInt<1>, ifc_iccm_access_bf : UInt<1>, ifc_region_acc_fault_bf : UInt<1>, ifc_dma_access_ok : UInt<1>}
io.ifc_region_acc_fault_bf <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 41:30]
io.ifc_dma_access_ok <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 42:24]
wire fetch_addr_bf : UInt<32> wire fetch_addr_bf : UInt<32>
fetch_addr_bf <= UInt<1>("h00") fetch_addr_bf <= UInt<1>("h00")
wire fetch_addr_next : UInt<32> wire fetch_addr_next : UInt<32>
@ -47,31 +45,31 @@ circuit el2_ifu_ifc_ctrl :
state <= UInt<1>("h00") state <= UInt<1>("h00")
wire dma_iccm_stall_any_f : UInt<1> wire dma_iccm_stall_any_f : UInt<1>
dma_iccm_stall_any_f <= UInt<1>("h00") dma_iccm_stall_any_f <= UInt<1>("h00")
node dma_stall = or(io.ic_dma_active, dma_iccm_stall_any_f) @[el2_ifu_ifc_ctrl.scala 66:36] node dma_stall = or(io.ic_dma_active, dma_iccm_stall_any_f) @[el2_ifu_ifc_ctrl.scala 60:36]
reg _T : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 67:34] reg _T : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 61:34]
_T <= io.dma_iccm_stall_any @[el2_ifu_ifc_ctrl.scala 67:34] _T <= io.dma_iccm_stall_any @[el2_ifu_ifc_ctrl.scala 61:34]
dma_iccm_stall_any_f <= _T @[el2_ifu_ifc_ctrl.scala 67:24] dma_iccm_stall_any_f <= _T @[el2_ifu_ifc_ctrl.scala 61:24]
reg _T_1 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 69:20] reg _T_1 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 63:20]
_T_1 <= miss_f @[el2_ifu_ifc_ctrl.scala 69:20] _T_1 <= miss_f @[el2_ifu_ifc_ctrl.scala 63:20]
miss_a <= _T_1 @[el2_ifu_ifc_ctrl.scala 69:10] miss_a <= _T_1 @[el2_ifu_ifc_ctrl.scala 63:10]
node _T_2 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 71:26] node _T_2 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 65:26]
node _T_3 = eq(io.ifc_fetch_req_f, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 71:49] node _T_3 = eq(io.ifc_fetch_req_f, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 65:49]
node _T_4 = eq(io.ic_hit_f, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 71:71] node _T_4 = eq(io.ic_hit_f, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 65:71]
node _T_5 = or(_T_3, _T_4) @[el2_ifu_ifc_ctrl.scala 71:69] node _T_5 = or(_T_3, _T_4) @[el2_ifu_ifc_ctrl.scala 65:69]
node sel_last_addr_bf = and(_T_2, _T_5) @[el2_ifu_ifc_ctrl.scala 71:46] node sel_last_addr_bf = and(_T_2, _T_5) @[el2_ifu_ifc_ctrl.scala 65:46]
node _T_6 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 72:26] node _T_6 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 66:26]
node _T_7 = and(_T_6, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 72:46] node _T_7 = and(_T_6, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 66:46]
node _T_8 = and(_T_7, io.ifu_bp_hit_taken_f) @[el2_ifu_ifc_ctrl.scala 72:67] node _T_8 = and(_T_7, io.ifu_bp_hit_taken_f) @[el2_ifu_ifc_ctrl.scala 66:67]
node sel_btb_addr_bf = and(_T_8, io.ic_hit_f) @[el2_ifu_ifc_ctrl.scala 72:92] node sel_btb_addr_bf = and(_T_8, io.ic_hit_f) @[el2_ifu_ifc_ctrl.scala 66:92]
node _T_9 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 73:26] node _T_9 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 67:26]
node _T_10 = and(_T_9, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 73:46] node _T_10 = and(_T_9, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 67:46]
node _T_11 = eq(io.ifu_bp_hit_taken_f, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 73:69] node _T_11 = eq(io.ifu_bp_hit_taken_f, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 67:69]
node _T_12 = and(_T_10, _T_11) @[el2_ifu_ifc_ctrl.scala 73:67] node _T_12 = and(_T_10, _T_11) @[el2_ifu_ifc_ctrl.scala 67:67]
node sel_next_addr_bf = and(_T_12, io.ic_hit_f) @[el2_ifu_ifc_ctrl.scala 73:92] node sel_next_addr_bf = and(_T_12, io.ic_hit_f) @[el2_ifu_ifc_ctrl.scala 67:92]
node _T_13 = bits(io.exu_flush_final, 0, 0) @[el2_ifu_ifc_ctrl.scala 76:56] node _T_13 = bits(io.exu_flush_final, 0, 0) @[el2_ifu_ifc_ctrl.scala 70:56]
node _T_14 = bits(sel_last_addr_bf, 0, 0) @[el2_ifu_ifc_ctrl.scala 77:46] node _T_14 = bits(sel_last_addr_bf, 0, 0) @[el2_ifu_ifc_ctrl.scala 71:46]
node _T_15 = bits(sel_btb_addr_bf, 0, 0) @[el2_ifu_ifc_ctrl.scala 78:45] node _T_15 = bits(sel_btb_addr_bf, 0, 0) @[el2_ifu_ifc_ctrl.scala 72:45]
node _T_16 = bits(sel_next_addr_bf, 0, 0) @[el2_ifu_ifc_ctrl.scala 79:46] node _T_16 = bits(sel_next_addr_bf, 0, 0) @[el2_ifu_ifc_ctrl.scala 73:46]
node _T_17 = mux(_T_13, io.exu_flush_path_final, UInt<1>("h00")) @[Mux.scala 27:72] node _T_17 = mux(_T_13, io.exu_flush_path_final, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_18 = mux(_T_14, io.ifc_fetch_addr_f, UInt<1>("h00")) @[Mux.scala 27:72] node _T_18 = mux(_T_14, io.ifc_fetch_addr_f, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_19 = mux(_T_15, io.ifu_bp_btb_target_f, UInt<1>("h00")) @[Mux.scala 27:72] node _T_19 = mux(_T_15, io.ifu_bp_btb_target_f, UInt<1>("h00")) @[Mux.scala 27:72]
@ -81,120 +79,118 @@ circuit el2_ifu_ifc_ctrl :
node _T_23 = or(_T_22, _T_20) @[Mux.scala 27:72] node _T_23 = or(_T_22, _T_20) @[Mux.scala 27:72]
wire _T_24 : UInt<32> @[Mux.scala 27:72] wire _T_24 : UInt<32> @[Mux.scala 27:72]
_T_24 <= _T_23 @[Mux.scala 27:72] _T_24 <= _T_23 @[Mux.scala 27:72]
io.ifc_fetch_addr_bf <= _T_24 @[el2_ifu_ifc_ctrl.scala 76:24] io.ifc_fetch_addr_bf <= _T_24 @[el2_ifu_ifc_ctrl.scala 70:24]
line_wrap <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 83:13] line_wrap <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 77:13]
node _T_25 = bits(line_wrap, 0, 0) @[el2_ifu_ifc_ctrl.scala 84:47] node _T_25 = bits(line_wrap, 0, 0) @[el2_ifu_ifc_ctrl.scala 78:47]
node _T_26 = bits(io.ifc_fetch_addr_f, 0, 0) @[el2_ifu_ifc_ctrl.scala 84:75] node _T_26 = bits(io.ifc_fetch_addr_f, 0, 0) @[el2_ifu_ifc_ctrl.scala 78:75]
node fetch_addr_next_1 = mux(_T_25, UInt<1>("h00"), _T_26) @[el2_ifu_ifc_ctrl.scala 84:30] node fetch_addr_next_1 = mux(_T_25, UInt<1>("h00"), _T_26) @[el2_ifu_ifc_ctrl.scala 78:30]
node _T_27 = bits(io.ifc_fetch_addr_f, 30, 1) @[el2_ifu_ifc_ctrl.scala 85:45] node _T_27 = bits(io.ifc_fetch_addr_f, 30, 1) @[el2_ifu_ifc_ctrl.scala 79:45]
node _T_28 = add(_T_27, UInt<1>("h01")) @[el2_ifu_ifc_ctrl.scala 85:51] node _T_28 = add(_T_27, UInt<1>("h01")) @[el2_ifu_ifc_ctrl.scala 79:51]
node _T_29 = tail(_T_28, 1) @[el2_ifu_ifc_ctrl.scala 85:51] node _T_29 = tail(_T_28, 1) @[el2_ifu_ifc_ctrl.scala 79:51]
node _T_30 = cat(_T_29, UInt<1>("h00")) @[Cat.scala 29:58] node _T_30 = cat(_T_29, UInt<1>("h00")) @[Cat.scala 29:58]
fetch_addr_next <= _T_30 @[el2_ifu_ifc_ctrl.scala 85:19] fetch_addr_next <= _T_30 @[el2_ifu_ifc_ctrl.scala 79:19]
node _T_31 = not(idle) @[el2_ifu_ifc_ctrl.scala 88:30] node _T_31 = not(idle) @[el2_ifu_ifc_ctrl.scala 82:30]
io.ifc_fetch_req_bf_raw <= _T_31 @[el2_ifu_ifc_ctrl.scala 88:27] io.ifc_fetch_req_bf_raw <= _T_31 @[el2_ifu_ifc_ctrl.scala 82:27]
node _T_32 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctrl.scala 90:91] node _T_32 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctrl.scala 84:91]
node _T_33 = eq(_T_32, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 90:70] node _T_33 = eq(_T_32, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 84:70]
node _T_34 = and(fb_full_f_ns, _T_33) @[el2_ifu_ifc_ctrl.scala 90:68] node _T_34 = and(fb_full_f_ns, _T_33) @[el2_ifu_ifc_ctrl.scala 84:68]
node _T_35 = eq(_T_34, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 90:53] node _T_35 = eq(_T_34, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 84:53]
node _T_36 = and(io.ifc_fetch_req_bf_raw, _T_35) @[el2_ifu_ifc_ctrl.scala 90:51] node _T_36 = and(io.ifc_fetch_req_bf_raw, _T_35) @[el2_ifu_ifc_ctrl.scala 84:51]
node _T_37 = eq(dma_stall, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 91:5] node _T_37 = eq(dma_stall, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 85:5]
node _T_38 = and(_T_36, _T_37) @[el2_ifu_ifc_ctrl.scala 90:114] node _T_38 = and(_T_36, _T_37) @[el2_ifu_ifc_ctrl.scala 84:114]
node _T_39 = eq(io.ic_write_stall, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 91:18] node _T_39 = eq(io.ic_write_stall, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 85:18]
node _T_40 = and(_T_38, _T_39) @[el2_ifu_ifc_ctrl.scala 91:16] node _T_40 = and(_T_38, _T_39) @[el2_ifu_ifc_ctrl.scala 85:16]
node _T_41 = eq(io.dec_tlu_flush_noredir_wb, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 91:39] node _T_41 = eq(io.dec_tlu_flush_noredir_wb, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 85:39]
node _T_42 = and(_T_40, _T_41) @[el2_ifu_ifc_ctrl.scala 91:37] node _T_42 = and(_T_40, _T_41) @[el2_ifu_ifc_ctrl.scala 85:37]
io.ifc_fetch_req_bf <= _T_42 @[el2_ifu_ifc_ctrl.scala 90:23] io.ifc_fetch_req_bf <= _T_42 @[el2_ifu_ifc_ctrl.scala 84:23]
node _T_43 = or(io.exu_flush_final, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 93:37] node _T_43 = or(io.exu_flush_final, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 87:37]
fetch_bf_en <= _T_43 @[el2_ifu_ifc_ctrl.scala 93:15] fetch_bf_en <= _T_43 @[el2_ifu_ifc_ctrl.scala 87:15]
node _T_44 = eq(io.ic_hit_f, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 95:34] node _T_44 = eq(io.ic_hit_f, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 89:34]
node _T_45 = and(io.ifc_fetch_req_f, _T_44) @[el2_ifu_ifc_ctrl.scala 95:32] node _T_45 = and(io.ifc_fetch_req_f, _T_44) @[el2_ifu_ifc_ctrl.scala 89:32]
node _T_46 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 95:49] node _T_46 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 89:49]
node _T_47 = and(_T_45, _T_46) @[el2_ifu_ifc_ctrl.scala 95:47] node _T_47 = and(_T_45, _T_46) @[el2_ifu_ifc_ctrl.scala 89:47]
miss_f <= _T_47 @[el2_ifu_ifc_ctrl.scala 95:10] miss_f <= _T_47 @[el2_ifu_ifc_ctrl.scala 89:10]
io.miss_f <= miss_f @[el2_ifu_ifc_ctrl.scala 96:13] node _T_48 = or(io.ifu_ic_mb_empty, io.exu_flush_final) @[el2_ifu_ifc_ctrl.scala 91:39]
node _T_48 = or(io.ifu_ic_mb_empty, io.exu_flush_final) @[el2_ifu_ifc_ctrl.scala 97:39] node _T_49 = eq(dma_stall, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 91:63]
node _T_49 = eq(dma_stall, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 97:63] node _T_50 = and(_T_48, _T_49) @[el2_ifu_ifc_ctrl.scala 91:61]
node _T_50 = and(_T_48, _T_49) @[el2_ifu_ifc_ctrl.scala 97:61] node _T_51 = eq(miss_f, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 91:76]
node _T_51 = eq(miss_f, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 97:76] node _T_52 = and(_T_50, _T_51) @[el2_ifu_ifc_ctrl.scala 91:74]
node _T_52 = and(_T_50, _T_51) @[el2_ifu_ifc_ctrl.scala 97:74] node _T_53 = eq(miss_a, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 91:86]
node _T_53 = eq(miss_a, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 97:86] node _T_54 = and(_T_52, _T_53) @[el2_ifu_ifc_ctrl.scala 91:84]
node _T_54 = and(_T_52, _T_53) @[el2_ifu_ifc_ctrl.scala 97:84] mb_empty_mod <= _T_54 @[el2_ifu_ifc_ctrl.scala 91:16]
mb_empty_mod <= _T_54 @[el2_ifu_ifc_ctrl.scala 97:16] node _T_55 = and(io.exu_flush_final, io.dec_tlu_flush_noredir_wb) @[el2_ifu_ifc_ctrl.scala 93:35]
io.mb_empty_mod <= mb_empty_mod @[el2_ifu_ifc_ctrl.scala 98:19] goto_idle <= _T_55 @[el2_ifu_ifc_ctrl.scala 93:13]
node _T_55 = and(io.exu_flush_final, io.dec_tlu_flush_noredir_wb) @[el2_ifu_ifc_ctrl.scala 99:35] node _T_56 = eq(io.dec_tlu_flush_noredir_wb, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 95:38]
goto_idle <= _T_55 @[el2_ifu_ifc_ctrl.scala 99:13] node _T_57 = and(io.exu_flush_final, _T_56) @[el2_ifu_ifc_ctrl.scala 95:36]
node _T_56 = eq(io.dec_tlu_flush_noredir_wb, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 101:38] node _T_58 = and(_T_57, idle) @[el2_ifu_ifc_ctrl.scala 95:67]
node _T_57 = and(io.exu_flush_final, _T_56) @[el2_ifu_ifc_ctrl.scala 101:36] leave_idle <= _T_58 @[el2_ifu_ifc_ctrl.scala 95:14]
node _T_58 = and(_T_57, idle) @[el2_ifu_ifc_ctrl.scala 101:67] node _T_59 = bits(state, 1, 1) @[el2_ifu_ifc_ctrl.scala 97:29]
leave_idle <= _T_58 @[el2_ifu_ifc_ctrl.scala 101:14] node _T_60 = eq(_T_59, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 97:23]
node _T_59 = bits(state, 1, 1) @[el2_ifu_ifc_ctrl.scala 103:29] node _T_61 = bits(state, 0, 0) @[el2_ifu_ifc_ctrl.scala 97:40]
node _T_60 = eq(_T_59, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 103:23] node _T_62 = and(_T_60, _T_61) @[el2_ifu_ifc_ctrl.scala 97:33]
node _T_61 = bits(state, 0, 0) @[el2_ifu_ifc_ctrl.scala 103:40] node _T_63 = and(_T_62, miss_f) @[el2_ifu_ifc_ctrl.scala 97:44]
node _T_62 = and(_T_60, _T_61) @[el2_ifu_ifc_ctrl.scala 103:33] node _T_64 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 97:55]
node _T_63 = and(_T_62, miss_f) @[el2_ifu_ifc_ctrl.scala 103:44] node _T_65 = and(_T_63, _T_64) @[el2_ifu_ifc_ctrl.scala 97:53]
node _T_64 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 103:55] node _T_66 = bits(state, 1, 1) @[el2_ifu_ifc_ctrl.scala 98:11]
node _T_65 = and(_T_63, _T_64) @[el2_ifu_ifc_ctrl.scala 103:53] node _T_67 = eq(mb_empty_mod, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 98:17]
node _T_66 = bits(state, 1, 1) @[el2_ifu_ifc_ctrl.scala 104:11] node _T_68 = and(_T_66, _T_67) @[el2_ifu_ifc_ctrl.scala 98:15]
node _T_67 = eq(mb_empty_mod, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 104:17] node _T_69 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 98:33]
node _T_68 = and(_T_66, _T_67) @[el2_ifu_ifc_ctrl.scala 104:15] node _T_70 = and(_T_68, _T_69) @[el2_ifu_ifc_ctrl.scala 98:31]
node _T_69 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 104:33] node next_state_1 = or(_T_65, _T_70) @[el2_ifu_ifc_ctrl.scala 97:67]
node _T_70 = and(_T_68, _T_69) @[el2_ifu_ifc_ctrl.scala 104:31] node _T_71 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 100:23]
node next_state_1 = or(_T_65, _T_70) @[el2_ifu_ifc_ctrl.scala 103:67] node _T_72 = and(_T_71, leave_idle) @[el2_ifu_ifc_ctrl.scala 100:34]
node _T_71 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 106:23] node _T_73 = bits(state, 0, 0) @[el2_ifu_ifc_ctrl.scala 100:56]
node _T_72 = and(_T_71, leave_idle) @[el2_ifu_ifc_ctrl.scala 106:34] node _T_74 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 100:62]
node _T_73 = bits(state, 0, 0) @[el2_ifu_ifc_ctrl.scala 106:56] node _T_75 = and(_T_73, _T_74) @[el2_ifu_ifc_ctrl.scala 100:60]
node _T_74 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 106:62] node next_state_0 = or(_T_72, _T_75) @[el2_ifu_ifc_ctrl.scala 100:48]
node _T_75 = and(_T_73, _T_74) @[el2_ifu_ifc_ctrl.scala 106:60]
node next_state_0 = or(_T_72, _T_75) @[el2_ifu_ifc_ctrl.scala 106:48]
node _T_76 = cat(next_state_1, next_state_0) @[Cat.scala 29:58] node _T_76 = cat(next_state_1, next_state_0) @[Cat.scala 29:58]
reg _T_77 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 108:19] reg _T_77 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 102:19]
_T_77 <= _T_76 @[el2_ifu_ifc_ctrl.scala 108:19] _T_77 <= _T_76 @[el2_ifu_ifc_ctrl.scala 102:19]
state <= _T_77 @[el2_ifu_ifc_ctrl.scala 108:9] state <= _T_77 @[el2_ifu_ifc_ctrl.scala 102:9]
flush_fb <= io.exu_flush_final @[el2_ifu_ifc_ctrl.scala 110:12] flush_fb <= io.exu_flush_final @[el2_ifu_ifc_ctrl.scala 104:12]
node _T_78 = eq(io.ifu_fb_consume2, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 112:38] node _T_78 = eq(io.ifu_fb_consume2, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 106:38]
node _T_79 = and(io.ifu_fb_consume1, _T_78) @[el2_ifu_ifc_ctrl.scala 112:36] node _T_79 = and(io.ifu_fb_consume1, _T_78) @[el2_ifu_ifc_ctrl.scala 106:36]
node _T_80 = eq(io.ifc_fetch_req_f, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 112:61] node _T_80 = eq(io.ifc_fetch_req_f, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 106:61]
node _T_81 = or(_T_80, miss_f) @[el2_ifu_ifc_ctrl.scala 112:81] node _T_81 = or(_T_80, miss_f) @[el2_ifu_ifc_ctrl.scala 106:81]
node _T_82 = and(_T_79, _T_81) @[el2_ifu_ifc_ctrl.scala 112:58] node _T_82 = and(_T_79, _T_81) @[el2_ifu_ifc_ctrl.scala 106:58]
node _T_83 = and(io.ifu_fb_consume2, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 113:25] node _T_83 = and(io.ifu_fb_consume2, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 107:25]
node _T_84 = or(_T_82, _T_83) @[el2_ifu_ifc_ctrl.scala 112:92] node _T_84 = or(_T_82, _T_83) @[el2_ifu_ifc_ctrl.scala 106:92]
fb_right <= _T_84 @[el2_ifu_ifc_ctrl.scala 112:12] fb_right <= _T_84 @[el2_ifu_ifc_ctrl.scala 106:12]
node _T_85 = not(io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 115:39] node _T_85 = not(io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 109:39]
node _T_86 = or(_T_85, miss_f) @[el2_ifu_ifc_ctrl.scala 115:59] node _T_86 = or(_T_85, miss_f) @[el2_ifu_ifc_ctrl.scala 109:59]
node _T_87 = and(io.ifu_fb_consume2, _T_86) @[el2_ifu_ifc_ctrl.scala 115:36] node _T_87 = and(io.ifu_fb_consume2, _T_86) @[el2_ifu_ifc_ctrl.scala 109:36]
fb_right2 <= _T_87 @[el2_ifu_ifc_ctrl.scala 115:13] fb_right2 <= _T_87 @[el2_ifu_ifc_ctrl.scala 109:13]
node _T_88 = or(io.ifu_fb_consume1, io.ifu_fb_consume2) @[el2_ifu_ifc_ctrl.scala 116:56] node _T_88 = or(io.ifu_fb_consume1, io.ifu_fb_consume2) @[el2_ifu_ifc_ctrl.scala 110:56]
node _T_89 = eq(_T_88, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 116:35] node _T_89 = eq(_T_88, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 110:35]
node _T_90 = and(io.ifc_fetch_req_f, _T_89) @[el2_ifu_ifc_ctrl.scala 116:33] node _T_90 = and(io.ifc_fetch_req_f, _T_89) @[el2_ifu_ifc_ctrl.scala 110:33]
node _T_91 = eq(miss_f, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 116:80] node _T_91 = eq(miss_f, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 110:80]
node _T_92 = and(_T_90, _T_91) @[el2_ifu_ifc_ctrl.scala 116:78] node _T_92 = and(_T_90, _T_91) @[el2_ifu_ifc_ctrl.scala 110:78]
fb_left <= _T_92 @[el2_ifu_ifc_ctrl.scala 116:11] fb_left <= _T_92 @[el2_ifu_ifc_ctrl.scala 110:11]
node _T_93 = bits(flush_fb, 0, 0) @[el2_ifu_ifc_ctrl.scala 118:37] node _T_93 = bits(flush_fb, 0, 0) @[el2_ifu_ifc_ctrl.scala 112:37]
node _T_94 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 119:6] node _T_94 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 113:6]
node _T_95 = and(_T_94, fb_right) @[el2_ifu_ifc_ctrl.scala 119:16] node _T_95 = and(_T_94, fb_right) @[el2_ifu_ifc_ctrl.scala 113:16]
node _T_96 = bits(_T_95, 0, 0) @[el2_ifu_ifc_ctrl.scala 119:28] node _T_96 = bits(_T_95, 0, 0) @[el2_ifu_ifc_ctrl.scala 113:28]
node _T_97 = bits(fb_write_f, 3, 1) @[el2_ifu_ifc_ctrl.scala 119:62] node _T_97 = bits(fb_write_f, 3, 1) @[el2_ifu_ifc_ctrl.scala 113:62]
node _T_98 = cat(UInt<1>("h00"), _T_97) @[Cat.scala 29:58] node _T_98 = cat(UInt<1>("h00"), _T_97) @[Cat.scala 29:58]
node _T_99 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 120:6] node _T_99 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 114:6]
node _T_100 = and(_T_99, fb_right2) @[el2_ifu_ifc_ctrl.scala 120:16] node _T_100 = and(_T_99, fb_right2) @[el2_ifu_ifc_ctrl.scala 114:16]
node _T_101 = bits(_T_100, 0, 0) @[el2_ifu_ifc_ctrl.scala 120:29] node _T_101 = bits(_T_100, 0, 0) @[el2_ifu_ifc_ctrl.scala 114:29]
node _T_102 = bits(fb_write_f, 3, 2) @[el2_ifu_ifc_ctrl.scala 120:63] node _T_102 = bits(fb_write_f, 3, 2) @[el2_ifu_ifc_ctrl.scala 114:63]
node _T_103 = cat(UInt<2>("h00"), _T_102) @[Cat.scala 29:58] node _T_103 = cat(UInt<2>("h00"), _T_102) @[Cat.scala 29:58]
node _T_104 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 121:6] node _T_104 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 115:6]
node _T_105 = and(_T_104, fb_left) @[el2_ifu_ifc_ctrl.scala 121:16] node _T_105 = and(_T_104, fb_left) @[el2_ifu_ifc_ctrl.scala 115:16]
node _T_106 = bits(_T_105, 0, 0) @[el2_ifu_ifc_ctrl.scala 121:27] node _T_106 = bits(_T_105, 0, 0) @[el2_ifu_ifc_ctrl.scala 115:27]
node _T_107 = bits(fb_write_f, 2, 0) @[el2_ifu_ifc_ctrl.scala 121:51] node _T_107 = bits(fb_write_f, 2, 0) @[el2_ifu_ifc_ctrl.scala 115:51]
node _T_108 = cat(_T_107, UInt<1>("h00")) @[Cat.scala 29:58] node _T_108 = cat(_T_107, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_109 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 122:6] node _T_109 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 116:6]
node _T_110 = eq(fb_right, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 122:18] node _T_110 = eq(fb_right, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 116:18]
node _T_111 = and(_T_109, _T_110) @[el2_ifu_ifc_ctrl.scala 122:16] node _T_111 = and(_T_109, _T_110) @[el2_ifu_ifc_ctrl.scala 116:16]
node _T_112 = eq(fb_right2, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 122:30] node _T_112 = eq(fb_right2, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 116:30]
node _T_113 = and(_T_111, _T_112) @[el2_ifu_ifc_ctrl.scala 122:28] node _T_113 = and(_T_111, _T_112) @[el2_ifu_ifc_ctrl.scala 116:28]
node _T_114 = eq(fb_left, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 122:43] node _T_114 = eq(fb_left, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 116:43]
node _T_115 = and(_T_113, _T_114) @[el2_ifu_ifc_ctrl.scala 122:41] node _T_115 = and(_T_113, _T_114) @[el2_ifu_ifc_ctrl.scala 116:41]
node _T_116 = bits(_T_115, 0, 0) @[el2_ifu_ifc_ctrl.scala 122:53] node _T_116 = bits(_T_115, 0, 0) @[el2_ifu_ifc_ctrl.scala 116:53]
node _T_117 = bits(fb_write_f, 3, 0) @[el2_ifu_ifc_ctrl.scala 122:73] node _T_117 = bits(fb_write_f, 3, 0) @[el2_ifu_ifc_ctrl.scala 116:73]
node _T_118 = mux(_T_93, UInt<4>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_118 = mux(_T_93, UInt<4>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_119 = mux(_T_96, _T_98, UInt<1>("h00")) @[Mux.scala 27:72] node _T_119 = mux(_T_96, _T_98, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_120 = mux(_T_101, _T_103, UInt<1>("h00")) @[Mux.scala 27:72] node _T_120 = mux(_T_101, _T_103, UInt<1>("h00")) @[Mux.scala 27:72]
@ -206,62 +202,65 @@ circuit el2_ifu_ifc_ctrl :
node _T_126 = or(_T_125, _T_122) @[Mux.scala 27:72] node _T_126 = or(_T_125, _T_122) @[Mux.scala 27:72]
wire _T_127 : UInt<4> @[Mux.scala 27:72] wire _T_127 : UInt<4> @[Mux.scala 27:72]
_T_127 <= _T_126 @[Mux.scala 27:72] _T_127 <= _T_126 @[Mux.scala 27:72]
fb_write_ns <= _T_127 @[el2_ifu_ifc_ctrl.scala 118:15] fb_write_ns <= _T_127 @[el2_ifu_ifc_ctrl.scala 112:15]
node _T_128 = bits(fb_write_ns, 3, 3) @[el2_ifu_ifc_ctrl.scala 125:38] node _T_128 = bits(fb_write_ns, 3, 3) @[el2_ifu_ifc_ctrl.scala 119:38]
reg _T_129 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 125:26] reg _T_129 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 119:26]
_T_129 <= _T_128 @[el2_ifu_ifc_ctrl.scala 125:26] _T_129 <= _T_128 @[el2_ifu_ifc_ctrl.scala 119:26]
fb_full_f_ns <= _T_129 @[el2_ifu_ifc_ctrl.scala 125:16] fb_full_f_ns <= _T_129 @[el2_ifu_ifc_ctrl.scala 119:16]
node _T_130 = eq(state, UInt<2>("h00")) @[el2_ifu_ifc_ctrl.scala 127:17] node _T_130 = eq(state, UInt<2>("h00")) @[el2_ifu_ifc_ctrl.scala 121:17]
idle <= _T_130 @[el2_ifu_ifc_ctrl.scala 127:8] idle <= _T_130 @[el2_ifu_ifc_ctrl.scala 121:8]
node _T_131 = eq(state, UInt<2>("h03")) @[el2_ifu_ifc_ctrl.scala 128:16] node _T_131 = eq(state, UInt<2>("h03")) @[el2_ifu_ifc_ctrl.scala 122:16]
wfm <= _T_131 @[el2_ifu_ifc_ctrl.scala 128:7] wfm <= _T_131 @[el2_ifu_ifc_ctrl.scala 122:7]
node _T_132 = bits(fb_write_ns, 3, 3) @[el2_ifu_ifc_ctrl.scala 130:30] node _T_132 = bits(fb_write_ns, 3, 3) @[el2_ifu_ifc_ctrl.scala 124:30]
fb_full_f_ns <= _T_132 @[el2_ifu_ifc_ctrl.scala 130:16] fb_full_f_ns <= _T_132 @[el2_ifu_ifc_ctrl.scala 124:16]
reg fb_full_f : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 131:26] reg fb_full_f : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 125:26]
fb_full_f <= fb_full_f_ns @[el2_ifu_ifc_ctrl.scala 131:26] fb_full_f <= fb_full_f_ns @[el2_ifu_ifc_ctrl.scala 125:26]
reg _T_133 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 132:24] reg _T_133 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 126:24]
_T_133 <= fb_write_ns @[el2_ifu_ifc_ctrl.scala 132:24] _T_133 <= fb_write_ns @[el2_ifu_ifc_ctrl.scala 126:24]
fb_write_f <= _T_133 @[el2_ifu_ifc_ctrl.scala 132:14] fb_write_f <= _T_133 @[el2_ifu_ifc_ctrl.scala 126:14]
node _T_134 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctrl.scala 135:40] node _T_134 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctrl.scala 129:40]
node _T_135 = or(_T_134, io.exu_flush_final) @[el2_ifu_ifc_ctrl.scala 135:61] node _T_135 = or(_T_134, io.exu_flush_final) @[el2_ifu_ifc_ctrl.scala 129:61]
node _T_136 = eq(_T_135, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 135:19] node _T_136 = eq(_T_135, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 129:19]
node _T_137 = and(fb_full_f, _T_136) @[el2_ifu_ifc_ctrl.scala 135:17] node _T_137 = and(fb_full_f, _T_136) @[el2_ifu_ifc_ctrl.scala 129:17]
node _T_138 = or(_T_137, dma_stall) @[el2_ifu_ifc_ctrl.scala 135:84] node _T_138 = or(_T_137, dma_stall) @[el2_ifu_ifc_ctrl.scala 129:84]
node _T_139 = and(io.ifc_fetch_req_bf_raw, _T_138) @[el2_ifu_ifc_ctrl.scala 134:60] node _T_139 = and(io.ifc_fetch_req_bf_raw, _T_138) @[el2_ifu_ifc_ctrl.scala 128:60]
node _T_140 = or(wfm, _T_139) @[el2_ifu_ifc_ctrl.scala 134:33] node _T_140 = or(wfm, _T_139) @[el2_ifu_ifc_ctrl.scala 128:33]
io.ifu_pmu_fetch_stall <= _T_140 @[el2_ifu_ifc_ctrl.scala 134:26] io.ifu_pmu_fetch_stall <= _T_140 @[el2_ifu_ifc_ctrl.scala 128:26]
node _T_141 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58] node _T_141 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_142 = bits(_T_141, 31, 28) @[el2_lib.scala 214:25] node _T_142 = bits(_T_141, 31, 28) @[el2_lib.scala 211:25]
node iccm_acc_in_region_bf = eq(_T_142, UInt<4>("h0e")) @[el2_lib.scala 214:47] node iccm_acc_in_region_bf = eq(_T_142, UInt<4>("h0e")) @[el2_lib.scala 211:47]
node _T_143 = bits(_T_141, 31, 16) @[el2_lib.scala 217:14] node _T_143 = bits(_T_141, 31, 16) @[el2_lib.scala 214:14]
node iccm_acc_in_range_bf = eq(_T_143, UInt<16>("h0ee00")) @[el2_lib.scala 217:29] node iccm_acc_in_range_bf = eq(_T_143, UInt<16>("h0ee00")) @[el2_lib.scala 214:29]
io.ifc_iccm_access_bf <= iccm_acc_in_range_bf @[el2_ifu_ifc_ctrl.scala 140:25] io.ifc_iccm_access_bf <= iccm_acc_in_range_bf @[el2_ifu_ifc_ctrl.scala 134:25]
node _T_144 = eq(io.ifc_iccm_access_bf, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 141:30] node _T_144 = eq(io.ifc_iccm_access_bf, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 135:30]
node _T_145 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctrl.scala 142:39] node _T_145 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctrl.scala 136:39]
node _T_146 = eq(_T_145, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 142:18] node _T_146 = eq(_T_145, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 136:18]
node _T_147 = and(fb_full_f, _T_146) @[el2_ifu_ifc_ctrl.scala 142:16] node _T_147 = and(fb_full_f, _T_146) @[el2_ifu_ifc_ctrl.scala 136:16]
node _T_148 = or(_T_144, _T_147) @[el2_ifu_ifc_ctrl.scala 141:53] node _T_148 = or(_T_144, _T_147) @[el2_ifu_ifc_ctrl.scala 135:53]
node _T_149 = eq(io.ifc_fetch_req_bf, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 143:13] node _T_149 = eq(io.ifc_fetch_req_bf, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 137:13]
node _T_150 = and(wfm, _T_149) @[el2_ifu_ifc_ctrl.scala 143:11] node _T_150 = and(wfm, _T_149) @[el2_ifu_ifc_ctrl.scala 137:11]
node _T_151 = or(_T_148, _T_150) @[el2_ifu_ifc_ctrl.scala 142:62] node _T_151 = or(_T_148, _T_150) @[el2_ifu_ifc_ctrl.scala 136:62]
node _T_152 = or(_T_151, idle) @[el2_ifu_ifc_ctrl.scala 143:35] node _T_152 = or(_T_151, idle) @[el2_ifu_ifc_ctrl.scala 137:35]
node _T_153 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 143:46] node _T_153 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 137:46]
node _T_154 = and(_T_152, _T_153) @[el2_ifu_ifc_ctrl.scala 143:44] node _T_154 = and(_T_152, _T_153) @[el2_ifu_ifc_ctrl.scala 137:44]
node _T_155 = or(_T_154, dma_iccm_stall_any_f) @[el2_ifu_ifc_ctrl.scala 143:67] node _T_155 = or(_T_154, dma_iccm_stall_any_f) @[el2_ifu_ifc_ctrl.scala 137:67]
io.ifc_dma_access_ok <= _T_155 @[el2_ifu_ifc_ctrl.scala 141:24] io.ifc_dma_access_ok <= _T_155 @[el2_ifu_ifc_ctrl.scala 135:24]
node _T_156 = bits(io.ifc_fetch_addr_bf, 30, 27) @[el2_ifu_ifc_ctrl.scala 145:78] node _T_156 = not(iccm_acc_in_range_bf) @[el2_ifu_ifc_ctrl.scala 139:33]
node _T_157 = cat(_T_156, UInt<1>("h00")) @[Cat.scala 29:58] node _T_157 = and(_T_156, iccm_acc_in_region_bf) @[el2_ifu_ifc_ctrl.scala 139:55]
node _T_158 = dshr(io.dec_tlu_mrac_ff, _T_157) @[el2_ifu_ifc_ctrl.scala 145:53] io.ifc_region_acc_fault_bf <= _T_157 @[el2_ifu_ifc_ctrl.scala 139:30]
node _T_159 = bits(_T_158, 0, 0) @[el2_ifu_ifc_ctrl.scala 145:53] node _T_158 = bits(io.ifc_fetch_addr_bf, 30, 27) @[el2_ifu_ifc_ctrl.scala 140:78]
node _T_160 = not(_T_159) @[el2_ifu_ifc_ctrl.scala 145:34] node _T_159 = cat(_T_158, UInt<1>("h00")) @[Cat.scala 29:58]
io.ifc_fetch_uncacheable_bf <= _T_160 @[el2_ifu_ifc_ctrl.scala 145:31] node _T_160 = dshr(io.dec_tlu_mrac_ff, _T_159) @[el2_ifu_ifc_ctrl.scala 140:53]
reg _T_161 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 147:32] node _T_161 = bits(_T_160, 0, 0) @[el2_ifu_ifc_ctrl.scala 140:53]
_T_161 <= io.ifc_fetch_req_bf @[el2_ifu_ifc_ctrl.scala 147:32] node _T_162 = not(_T_161) @[el2_ifu_ifc_ctrl.scala 140:34]
io.ifc_fetch_req_f <= _T_161 @[el2_ifu_ifc_ctrl.scala 147:22] io.ifc_fetch_uncacheable_bf <= _T_162 @[el2_ifu_ifc_ctrl.scala 140:31]
node _T_162 = or(io.exu_flush_final, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 149:88] reg _T_163 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 142:32]
reg _T_163 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] _T_163 <= io.ifc_fetch_req_bf @[el2_ifu_ifc_ctrl.scala 142:32]
when _T_162 : @[Reg.scala 28:19] io.ifc_fetch_req_f <= _T_163 @[el2_ifu_ifc_ctrl.scala 142:22]
_T_163 <= io.ifc_fetch_addr_bf @[Reg.scala 28:23] node _T_164 = or(io.exu_flush_final, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 144:88]
reg _T_165 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_164 : @[Reg.scala 28:19]
_T_165 <= io.ifc_fetch_addr_bf @[Reg.scala 28:23]
skip @[Reg.scala 28:19] skip @[Reg.scala 28:19]
io.ifc_fetch_addr_f <= _T_163 @[el2_ifu_ifc_ctrl.scala 149:23] io.ifc_fetch_addr_f <= _T_165 @[el2_ifu_ifc_ctrl.scala 144:23]

229
el2_ifu_ifc_ctrl.v
View File

@ -1,9 +1,7 @@
module el2_ifu_ifc_ctrl( module el2_ifu_ifc_ctrl(
input clock, input clock,
input reset, input reset,
input io_free_clk,
input io_active_clk, input io_active_clk,
input io_rst_l,
input io_scan_mode, input io_scan_mode,
input io_ic_hit_f, input io_ic_hit_f,
input io_ifu_ic_mb_empty, input io_ifu_ic_mb_empty,
@ -27,9 +25,7 @@ module el2_ifu_ifc_ctrl(
output io_ifc_fetch_req_bf_raw, output io_ifc_fetch_req_bf_raw,
output io_ifc_iccm_access_bf, output io_ifc_iccm_access_bf,
output io_ifc_region_acc_fault_bf, output io_ifc_region_acc_fault_bf,
output io_ifc_dma_access_ok, output io_ifc_dma_access_ok
output io_mb_empty_mod,
output io_miss_f
); );
`ifdef RANDOMIZE_REG_INIT `ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0; reg [31:0] _RAND_0;
@ -40,134 +36,135 @@ module el2_ifu_ifc_ctrl(
reg [31:0] _RAND_5; reg [31:0] _RAND_5;
reg [31:0] _RAND_6; reg [31:0] _RAND_6;
`endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE_REG_INIT
reg dma_iccm_stall_any_f; // @[el2_ifu_ifc_ctrl.scala 67:34] reg dma_iccm_stall_any_f; // @[el2_ifu_ifc_ctrl.scala 61:34]
wire dma_stall = io_ic_dma_active | dma_iccm_stall_any_f; // @[el2_ifu_ifc_ctrl.scala 66:36] wire dma_stall = io_ic_dma_active | dma_iccm_stall_any_f; // @[el2_ifu_ifc_ctrl.scala 60:36]
reg miss_a; // @[el2_ifu_ifc_ctrl.scala 69:20] reg miss_a; // @[el2_ifu_ifc_ctrl.scala 63:20]
wire _T_2 = ~io_exu_flush_final; // @[el2_ifu_ifc_ctrl.scala 71:26] wire _T_2 = ~io_exu_flush_final; // @[el2_ifu_ifc_ctrl.scala 65:26]
wire _T_3 = ~io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctrl.scala 71:49] wire _T_3 = ~io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctrl.scala 65:49]
wire _T_4 = ~io_ic_hit_f; // @[el2_ifu_ifc_ctrl.scala 71:71] wire _T_4 = ~io_ic_hit_f; // @[el2_ifu_ifc_ctrl.scala 65:71]
wire _T_5 = _T_3 | _T_4; // @[el2_ifu_ifc_ctrl.scala 71:69] wire _T_5 = _T_3 | _T_4; // @[el2_ifu_ifc_ctrl.scala 65:69]
wire sel_last_addr_bf = _T_2 & _T_5; // @[el2_ifu_ifc_ctrl.scala 71:46] wire sel_last_addr_bf = _T_2 & _T_5; // @[el2_ifu_ifc_ctrl.scala 65:46]
wire _T_7 = _T_2 & io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctrl.scala 72:46] wire _T_7 = _T_2 & io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctrl.scala 66:46]
wire _T_8 = _T_7 & io_ifu_bp_hit_taken_f; // @[el2_ifu_ifc_ctrl.scala 72:67] wire _T_8 = _T_7 & io_ifu_bp_hit_taken_f; // @[el2_ifu_ifc_ctrl.scala 66:67]
wire sel_btb_addr_bf = _T_8 & io_ic_hit_f; // @[el2_ifu_ifc_ctrl.scala 72:92] wire sel_btb_addr_bf = _T_8 & io_ic_hit_f; // @[el2_ifu_ifc_ctrl.scala 66:92]
wire _T_11 = ~io_ifu_bp_hit_taken_f; // @[el2_ifu_ifc_ctrl.scala 73:69] wire _T_11 = ~io_ifu_bp_hit_taken_f; // @[el2_ifu_ifc_ctrl.scala 67:69]
wire _T_12 = _T_7 & _T_11; // @[el2_ifu_ifc_ctrl.scala 73:67] wire _T_12 = _T_7 & _T_11; // @[el2_ifu_ifc_ctrl.scala 67:67]
wire sel_next_addr_bf = _T_12 & io_ic_hit_f; // @[el2_ifu_ifc_ctrl.scala 73:92] wire sel_next_addr_bf = _T_12 & io_ic_hit_f; // @[el2_ifu_ifc_ctrl.scala 67:92]
wire [30:0] _T_17 = io_exu_flush_final ? io_exu_flush_path_final : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_17 = io_exu_flush_final ? io_exu_flush_path_final : 31'h0; // @[Mux.scala 27:72]
wire [30:0] _T_18 = sel_last_addr_bf ? io_ifc_fetch_addr_f : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_18 = sel_last_addr_bf ? io_ifc_fetch_addr_f : 31'h0; // @[Mux.scala 27:72]
wire [30:0] _T_19 = sel_btb_addr_bf ? io_ifu_bp_btb_target_f : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_19 = sel_btb_addr_bf ? io_ifu_bp_btb_target_f : 31'h0; // @[Mux.scala 27:72]
wire [29:0] _T_29 = io_ifc_fetch_addr_f[30:1] + 30'h1; // @[el2_ifu_ifc_ctrl.scala 85:51] wire [29:0] _T_29 = io_ifc_fetch_addr_f[30:1] + 30'h1; // @[el2_ifu_ifc_ctrl.scala 79:51]
wire [30:0] _T_30 = {_T_29,1'h0}; // @[Cat.scala 29:58] wire [30:0] _T_30 = {_T_29,1'h0}; // @[Cat.scala 29:58]
wire [31:0] fetch_addr_next = {{1'd0}, _T_30}; // @[el2_ifu_ifc_ctrl.scala 85:19] wire [31:0] fetch_addr_next = {{1'd0}, _T_30}; // @[el2_ifu_ifc_ctrl.scala 79:19]
wire [31:0] _T_20 = sel_next_addr_bf ? fetch_addr_next : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_20 = sel_next_addr_bf ? fetch_addr_next : 32'h0; // @[Mux.scala 27:72]
wire [30:0] _T_21 = _T_17 | _T_18; // @[Mux.scala 27:72] wire [30:0] _T_21 = _T_17 | _T_18; // @[Mux.scala 27:72]
wire [30:0] _T_22 = _T_21 | _T_19; // @[Mux.scala 27:72] wire [30:0] _T_22 = _T_21 | _T_19; // @[Mux.scala 27:72]
wire [31:0] _GEN_1 = {{1'd0}, _T_22}; // @[Mux.scala 27:72] wire [31:0] _GEN_1 = {{1'd0}, _T_22}; // @[Mux.scala 27:72]
wire [31:0] _T_23 = _GEN_1 | _T_20; // @[Mux.scala 27:72] wire [31:0] _T_23 = _GEN_1 | _T_20; // @[Mux.scala 27:72]
reg [1:0] state; // @[el2_ifu_ifc_ctrl.scala 108:19] reg [1:0] state; // @[el2_ifu_ifc_ctrl.scala 102:19]
wire idle = state == 2'h0; // @[el2_ifu_ifc_ctrl.scala 127:17] wire idle = state == 2'h0; // @[el2_ifu_ifc_ctrl.scala 121:17]
wire _T_32 = io_ifu_fb_consume2 | io_ifu_fb_consume1; // @[el2_ifu_ifc_ctrl.scala 90:91] wire _T_32 = io_ifu_fb_consume2 | io_ifu_fb_consume1; // @[el2_ifu_ifc_ctrl.scala 84:91]
wire _T_33 = ~_T_32; // @[el2_ifu_ifc_ctrl.scala 90:70] wire _T_33 = ~_T_32; // @[el2_ifu_ifc_ctrl.scala 84:70]
wire [3:0] _T_118 = io_exu_flush_final ? 4'h1 : 4'h0; // @[Mux.scala 27:72] wire [3:0] _T_118 = io_exu_flush_final ? 4'h1 : 4'h0; // @[Mux.scala 27:72]
wire _T_78 = ~io_ifu_fb_consume2; // @[el2_ifu_ifc_ctrl.scala 112:38] wire _T_78 = ~io_ifu_fb_consume2; // @[el2_ifu_ifc_ctrl.scala 106:38]
wire _T_79 = io_ifu_fb_consume1 & _T_78; // @[el2_ifu_ifc_ctrl.scala 112:36] wire _T_79 = io_ifu_fb_consume1 & _T_78; // @[el2_ifu_ifc_ctrl.scala 106:36]
wire _T_45 = io_ifc_fetch_req_f & _T_4; // @[el2_ifu_ifc_ctrl.scala 95:32] wire _T_45 = io_ifc_fetch_req_f & _T_4; // @[el2_ifu_ifc_ctrl.scala 89:32]
wire miss_f = _T_45 & _T_2; // @[el2_ifu_ifc_ctrl.scala 95:47] wire miss_f = _T_45 & _T_2; // @[el2_ifu_ifc_ctrl.scala 89:47]
wire _T_81 = _T_3 | miss_f; // @[el2_ifu_ifc_ctrl.scala 112:81] wire _T_81 = _T_3 | miss_f; // @[el2_ifu_ifc_ctrl.scala 106:81]
wire _T_82 = _T_79 & _T_81; // @[el2_ifu_ifc_ctrl.scala 112:58] wire _T_82 = _T_79 & _T_81; // @[el2_ifu_ifc_ctrl.scala 106:58]
wire _T_83 = io_ifu_fb_consume2 & io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctrl.scala 113:25] wire _T_83 = io_ifu_fb_consume2 & io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctrl.scala 107:25]
wire fb_right = _T_82 | _T_83; // @[el2_ifu_ifc_ctrl.scala 112:92] wire fb_right = _T_82 | _T_83; // @[el2_ifu_ifc_ctrl.scala 106:92]
wire _T_95 = _T_2 & fb_right; // @[el2_ifu_ifc_ctrl.scala 119:16] wire _T_95 = _T_2 & fb_right; // @[el2_ifu_ifc_ctrl.scala 113:16]
reg [3:0] fb_write_f; // @[el2_ifu_ifc_ctrl.scala 132:24] reg [3:0] fb_write_f; // @[el2_ifu_ifc_ctrl.scala 126:24]
wire [3:0] _T_98 = {1'h0,fb_write_f[3:1]}; // @[Cat.scala 29:58] wire [3:0] _T_98 = {1'h0,fb_write_f[3:1]}; // @[Cat.scala 29:58]
wire [3:0] _T_119 = _T_95 ? _T_98 : 4'h0; // @[Mux.scala 27:72] wire [3:0] _T_119 = _T_95 ? _T_98 : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_123 = _T_118 | _T_119; // @[Mux.scala 27:72] wire [3:0] _T_123 = _T_118 | _T_119; // @[Mux.scala 27:72]
wire fb_right2 = io_ifu_fb_consume2 & _T_81; // @[el2_ifu_ifc_ctrl.scala 115:36] wire fb_right2 = io_ifu_fb_consume2 & _T_81; // @[el2_ifu_ifc_ctrl.scala 109:36]
wire _T_100 = _T_2 & fb_right2; // @[el2_ifu_ifc_ctrl.scala 120:16] wire _T_100 = _T_2 & fb_right2; // @[el2_ifu_ifc_ctrl.scala 114:16]
wire [3:0] _T_103 = {2'h0,fb_write_f[3:2]}; // @[Cat.scala 29:58] wire [3:0] _T_103 = {2'h0,fb_write_f[3:2]}; // @[Cat.scala 29:58]
wire [3:0] _T_120 = _T_100 ? _T_103 : 4'h0; // @[Mux.scala 27:72] wire [3:0] _T_120 = _T_100 ? _T_103 : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_124 = _T_123 | _T_120; // @[Mux.scala 27:72] wire [3:0] _T_124 = _T_123 | _T_120; // @[Mux.scala 27:72]
wire _T_88 = io_ifu_fb_consume1 | io_ifu_fb_consume2; // @[el2_ifu_ifc_ctrl.scala 116:56] wire _T_88 = io_ifu_fb_consume1 | io_ifu_fb_consume2; // @[el2_ifu_ifc_ctrl.scala 110:56]
wire _T_89 = ~_T_88; // @[el2_ifu_ifc_ctrl.scala 116:35] wire _T_89 = ~_T_88; // @[el2_ifu_ifc_ctrl.scala 110:35]
wire _T_90 = io_ifc_fetch_req_f & _T_89; // @[el2_ifu_ifc_ctrl.scala 116:33] wire _T_90 = io_ifc_fetch_req_f & _T_89; // @[el2_ifu_ifc_ctrl.scala 110:33]
wire _T_91 = ~miss_f; // @[el2_ifu_ifc_ctrl.scala 116:80] wire _T_91 = ~miss_f; // @[el2_ifu_ifc_ctrl.scala 110:80]
wire fb_left = _T_90 & _T_91; // @[el2_ifu_ifc_ctrl.scala 116:78] wire fb_left = _T_90 & _T_91; // @[el2_ifu_ifc_ctrl.scala 110:78]
wire _T_105 = _T_2 & fb_left; // @[el2_ifu_ifc_ctrl.scala 121:16] wire _T_105 = _T_2 & fb_left; // @[el2_ifu_ifc_ctrl.scala 115:16]
wire [3:0] _T_108 = {fb_write_f[2:0],1'h0}; // @[Cat.scala 29:58] wire [3:0] _T_108 = {fb_write_f[2:0],1'h0}; // @[Cat.scala 29:58]
wire [3:0] _T_121 = _T_105 ? _T_108 : 4'h0; // @[Mux.scala 27:72] wire [3:0] _T_121 = _T_105 ? _T_108 : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_125 = _T_124 | _T_121; // @[Mux.scala 27:72] wire [3:0] _T_125 = _T_124 | _T_121; // @[Mux.scala 27:72]
wire _T_110 = ~fb_right; // @[el2_ifu_ifc_ctrl.scala 122:18] wire _T_110 = ~fb_right; // @[el2_ifu_ifc_ctrl.scala 116:18]
wire _T_111 = _T_2 & _T_110; // @[el2_ifu_ifc_ctrl.scala 122:16] wire _T_111 = _T_2 & _T_110; // @[el2_ifu_ifc_ctrl.scala 116:16]
wire _T_112 = ~fb_right2; // @[el2_ifu_ifc_ctrl.scala 122:30] wire _T_112 = ~fb_right2; // @[el2_ifu_ifc_ctrl.scala 116:30]
wire _T_113 = _T_111 & _T_112; // @[el2_ifu_ifc_ctrl.scala 122:28] wire _T_113 = _T_111 & _T_112; // @[el2_ifu_ifc_ctrl.scala 116:28]
wire _T_114 = ~fb_left; // @[el2_ifu_ifc_ctrl.scala 122:43] wire _T_114 = ~fb_left; // @[el2_ifu_ifc_ctrl.scala 116:43]
wire _T_115 = _T_113 & _T_114; // @[el2_ifu_ifc_ctrl.scala 122:41] wire _T_115 = _T_113 & _T_114; // @[el2_ifu_ifc_ctrl.scala 116:41]
wire [3:0] _T_122 = _T_115 ? fb_write_f : 4'h0; // @[Mux.scala 27:72] wire [3:0] _T_122 = _T_115 ? fb_write_f : 4'h0; // @[Mux.scala 27:72]
wire [3:0] fb_write_ns = _T_125 | _T_122; // @[Mux.scala 27:72] wire [3:0] fb_write_ns = _T_125 | _T_122; // @[Mux.scala 27:72]
wire fb_full_f_ns = fb_write_ns[3]; // @[el2_ifu_ifc_ctrl.scala 130:30] wire fb_full_f_ns = fb_write_ns[3]; // @[el2_ifu_ifc_ctrl.scala 124:30]
wire _T_34 = fb_full_f_ns & _T_33; // @[el2_ifu_ifc_ctrl.scala 90:68] wire _T_34 = fb_full_f_ns & _T_33; // @[el2_ifu_ifc_ctrl.scala 84:68]
wire _T_35 = ~_T_34; // @[el2_ifu_ifc_ctrl.scala 90:53] wire _T_35 = ~_T_34; // @[el2_ifu_ifc_ctrl.scala 84:53]
wire _T_36 = io_ifc_fetch_req_bf_raw & _T_35; // @[el2_ifu_ifc_ctrl.scala 90:51] wire _T_36 = io_ifc_fetch_req_bf_raw & _T_35; // @[el2_ifu_ifc_ctrl.scala 84:51]
wire _T_37 = ~dma_stall; // @[el2_ifu_ifc_ctrl.scala 91:5] wire _T_37 = ~dma_stall; // @[el2_ifu_ifc_ctrl.scala 85:5]
wire _T_38 = _T_36 & _T_37; // @[el2_ifu_ifc_ctrl.scala 90:114] wire _T_38 = _T_36 & _T_37; // @[el2_ifu_ifc_ctrl.scala 84:114]
wire _T_39 = ~io_ic_write_stall; // @[el2_ifu_ifc_ctrl.scala 91:18] wire _T_39 = ~io_ic_write_stall; // @[el2_ifu_ifc_ctrl.scala 85:18]
wire _T_40 = _T_38 & _T_39; // @[el2_ifu_ifc_ctrl.scala 91:16] wire _T_40 = _T_38 & _T_39; // @[el2_ifu_ifc_ctrl.scala 85:16]
wire _T_41 = ~io_dec_tlu_flush_noredir_wb; // @[el2_ifu_ifc_ctrl.scala 91:39] wire _T_41 = ~io_dec_tlu_flush_noredir_wb; // @[el2_ifu_ifc_ctrl.scala 85:39]
wire fetch_bf_en = io_exu_flush_final | io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctrl.scala 93:37] wire fetch_bf_en = io_exu_flush_final | io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctrl.scala 87:37]
wire _T_48 = io_ifu_ic_mb_empty | io_exu_flush_final; // @[el2_ifu_ifc_ctrl.scala 97:39] wire _T_48 = io_ifu_ic_mb_empty | io_exu_flush_final; // @[el2_ifu_ifc_ctrl.scala 91:39]
wire _T_50 = _T_48 & _T_37; // @[el2_ifu_ifc_ctrl.scala 97:61] wire _T_50 = _T_48 & _T_37; // @[el2_ifu_ifc_ctrl.scala 91:61]
wire _T_52 = _T_50 & _T_91; // @[el2_ifu_ifc_ctrl.scala 97:74] wire _T_52 = _T_50 & _T_91; // @[el2_ifu_ifc_ctrl.scala 91:74]
wire _T_53 = ~miss_a; // @[el2_ifu_ifc_ctrl.scala 97:86] wire _T_53 = ~miss_a; // @[el2_ifu_ifc_ctrl.scala 91:86]
wire mb_empty_mod = _T_52 & _T_53; // @[el2_ifu_ifc_ctrl.scala 97:84] wire mb_empty_mod = _T_52 & _T_53; // @[el2_ifu_ifc_ctrl.scala 91:84]
wire goto_idle = io_exu_flush_final & io_dec_tlu_flush_noredir_wb; // @[el2_ifu_ifc_ctrl.scala 99:35] wire goto_idle = io_exu_flush_final & io_dec_tlu_flush_noredir_wb; // @[el2_ifu_ifc_ctrl.scala 93:35]
wire _T_57 = io_exu_flush_final & _T_41; // @[el2_ifu_ifc_ctrl.scala 101:36] wire _T_57 = io_exu_flush_final & _T_41; // @[el2_ifu_ifc_ctrl.scala 95:36]
wire leave_idle = _T_57 & idle; // @[el2_ifu_ifc_ctrl.scala 101:67] wire leave_idle = _T_57 & idle; // @[el2_ifu_ifc_ctrl.scala 95:67]
wire _T_60 = ~state[1]; // @[el2_ifu_ifc_ctrl.scala 103:23] wire _T_60 = ~state[1]; // @[el2_ifu_ifc_ctrl.scala 97:23]
wire _T_62 = _T_60 & state[0]; // @[el2_ifu_ifc_ctrl.scala 103:33] wire _T_62 = _T_60 & state[0]; // @[el2_ifu_ifc_ctrl.scala 97:33]
wire _T_63 = _T_62 & miss_f; // @[el2_ifu_ifc_ctrl.scala 103:44] wire _T_63 = _T_62 & miss_f; // @[el2_ifu_ifc_ctrl.scala 97:44]
wire _T_64 = ~goto_idle; // @[el2_ifu_ifc_ctrl.scala 103:55] wire _T_64 = ~goto_idle; // @[el2_ifu_ifc_ctrl.scala 97:55]
wire _T_65 = _T_63 & _T_64; // @[el2_ifu_ifc_ctrl.scala 103:53] wire _T_65 = _T_63 & _T_64; // @[el2_ifu_ifc_ctrl.scala 97:53]
wire _T_67 = ~mb_empty_mod; // @[el2_ifu_ifc_ctrl.scala 104:17] wire _T_67 = ~mb_empty_mod; // @[el2_ifu_ifc_ctrl.scala 98:17]
wire _T_68 = state[1] & _T_67; // @[el2_ifu_ifc_ctrl.scala 104:15] wire _T_68 = state[1] & _T_67; // @[el2_ifu_ifc_ctrl.scala 98:15]
wire _T_70 = _T_68 & _T_64; // @[el2_ifu_ifc_ctrl.scala 104:31] wire _T_70 = _T_68 & _T_64; // @[el2_ifu_ifc_ctrl.scala 98:31]
wire next_state_1 = _T_65 | _T_70; // @[el2_ifu_ifc_ctrl.scala 103:67] wire next_state_1 = _T_65 | _T_70; // @[el2_ifu_ifc_ctrl.scala 97:67]
wire _T_72 = _T_64 & leave_idle; // @[el2_ifu_ifc_ctrl.scala 106:34] wire _T_72 = _T_64 & leave_idle; // @[el2_ifu_ifc_ctrl.scala 100:34]
wire _T_75 = state[0] & _T_64; // @[el2_ifu_ifc_ctrl.scala 106:60] wire _T_75 = state[0] & _T_64; // @[el2_ifu_ifc_ctrl.scala 100:60]
wire next_state_0 = _T_72 | _T_75; // @[el2_ifu_ifc_ctrl.scala 106:48] wire next_state_0 = _T_72 | _T_75; // @[el2_ifu_ifc_ctrl.scala 100:48]
wire [1:0] _T_76 = {next_state_1,next_state_0}; // @[Cat.scala 29:58] wire [1:0] _T_76 = {next_state_1,next_state_0}; // @[Cat.scala 29:58]
wire wfm = state == 2'h3; // @[el2_ifu_ifc_ctrl.scala 128:16] wire wfm = state == 2'h3; // @[el2_ifu_ifc_ctrl.scala 122:16]
reg fb_full_f; // @[el2_ifu_ifc_ctrl.scala 131:26] reg fb_full_f; // @[el2_ifu_ifc_ctrl.scala 125:26]
wire _T_135 = _T_32 | io_exu_flush_final; // @[el2_ifu_ifc_ctrl.scala 135:61] wire _T_135 = _T_32 | io_exu_flush_final; // @[el2_ifu_ifc_ctrl.scala 129:61]
wire _T_136 = ~_T_135; // @[el2_ifu_ifc_ctrl.scala 135:19] wire _T_136 = ~_T_135; // @[el2_ifu_ifc_ctrl.scala 129:19]
wire _T_137 = fb_full_f & _T_136; // @[el2_ifu_ifc_ctrl.scala 135:17] wire _T_137 = fb_full_f & _T_136; // @[el2_ifu_ifc_ctrl.scala 129:17]
wire _T_138 = _T_137 | dma_stall; // @[el2_ifu_ifc_ctrl.scala 135:84] wire _T_138 = _T_137 | dma_stall; // @[el2_ifu_ifc_ctrl.scala 129:84]
wire _T_139 = io_ifc_fetch_req_bf_raw & _T_138; // @[el2_ifu_ifc_ctrl.scala 134:60] wire _T_139 = io_ifc_fetch_req_bf_raw & _T_138; // @[el2_ifu_ifc_ctrl.scala 128:60]
wire [31:0] _T_141 = {io_ifc_fetch_addr_bf,1'h0}; // @[Cat.scala 29:58] wire [31:0] _T_141 = {io_ifc_fetch_addr_bf,1'h0}; // @[Cat.scala 29:58]
wire _T_144 = ~io_ifc_iccm_access_bf; // @[el2_ifu_ifc_ctrl.scala 141:30] wire iccm_acc_in_region_bf = _T_141[31:28] == 4'he; // @[el2_lib.scala 211:47]
wire _T_147 = fb_full_f & _T_33; // @[el2_ifu_ifc_ctrl.scala 142:16] wire iccm_acc_in_range_bf = _T_141[31:16] == 16'hee00; // @[el2_lib.scala 214:29]
wire _T_148 = _T_144 | _T_147; // @[el2_ifu_ifc_ctrl.scala 141:53] wire _T_144 = ~io_ifc_iccm_access_bf; // @[el2_ifu_ifc_ctrl.scala 135:30]
wire _T_149 = ~io_ifc_fetch_req_bf; // @[el2_ifu_ifc_ctrl.scala 143:13] wire _T_147 = fb_full_f & _T_33; // @[el2_ifu_ifc_ctrl.scala 136:16]
wire _T_150 = wfm & _T_149; // @[el2_ifu_ifc_ctrl.scala 143:11] wire _T_148 = _T_144 | _T_147; // @[el2_ifu_ifc_ctrl.scala 135:53]
wire _T_151 = _T_148 | _T_150; // @[el2_ifu_ifc_ctrl.scala 142:62] wire _T_149 = ~io_ifc_fetch_req_bf; // @[el2_ifu_ifc_ctrl.scala 137:13]
wire _T_152 = _T_151 | idle; // @[el2_ifu_ifc_ctrl.scala 143:35] wire _T_150 = wfm & _T_149; // @[el2_ifu_ifc_ctrl.scala 137:11]
wire _T_154 = _T_152 & _T_2; // @[el2_ifu_ifc_ctrl.scala 143:44] wire _T_151 = _T_148 | _T_150; // @[el2_ifu_ifc_ctrl.scala 136:62]
wire [4:0] _T_157 = {io_ifc_fetch_addr_bf[30:27],1'h0}; // @[Cat.scala 29:58] wire _T_152 = _T_151 | idle; // @[el2_ifu_ifc_ctrl.scala 137:35]
wire [31:0] _T_158 = io_dec_tlu_mrac_ff >> _T_157; // @[el2_ifu_ifc_ctrl.scala 145:53] wire _T_154 = _T_152 & _T_2; // @[el2_ifu_ifc_ctrl.scala 137:44]
reg _T_161; // @[el2_ifu_ifc_ctrl.scala 147:32] wire _T_156 = ~iccm_acc_in_range_bf; // @[el2_ifu_ifc_ctrl.scala 139:33]
reg [30:0] _T_163; // @[Reg.scala 27:20] wire [4:0] _T_159 = {io_ifc_fetch_addr_bf[30:27],1'h0}; // @[Cat.scala 29:58]
assign io_ifc_fetch_addr_f = _T_163; // @[el2_ifu_ifc_ctrl.scala 149:23] wire [31:0] _T_160 = io_dec_tlu_mrac_ff >> _T_159; // @[el2_ifu_ifc_ctrl.scala 140:53]
assign io_ifc_fetch_addr_bf = _T_23[30:0]; // @[el2_ifu_ifc_ctrl.scala 76:24] reg _T_163; // @[el2_ifu_ifc_ctrl.scala 142:32]
assign io_ifc_fetch_req_f = _T_161; // @[el2_ifu_ifc_ctrl.scala 147:22] reg [30:0] _T_165; // @[Reg.scala 27:20]
assign io_ifu_pmu_fetch_stall = wfm | _T_139; // @[el2_ifu_ifc_ctrl.scala 134:26] assign io_ifc_fetch_addr_f = _T_165; // @[el2_ifu_ifc_ctrl.scala 144:23]
assign io_ifc_fetch_uncacheable_bf = ~_T_158[0]; // @[el2_ifu_ifc_ctrl.scala 145:31] assign io_ifc_fetch_addr_bf = _T_23[30:0]; // @[el2_ifu_ifc_ctrl.scala 70:24]
assign io_ifc_fetch_req_bf = _T_40 & _T_41; // @[el2_ifu_ifc_ctrl.scala 90:23] assign io_ifc_fetch_req_f = _T_163; // @[el2_ifu_ifc_ctrl.scala 142:22]
assign io_ifc_fetch_req_bf_raw = ~idle; // @[el2_ifu_ifc_ctrl.scala 88:27] assign io_ifu_pmu_fetch_stall = wfm | _T_139; // @[el2_ifu_ifc_ctrl.scala 128:26]
assign io_ifc_iccm_access_bf = _T_141[31:16] == 16'hee00; // @[el2_ifu_ifc_ctrl.scala 140:25] assign io_ifc_fetch_uncacheable_bf = ~_T_160[0]; // @[el2_ifu_ifc_ctrl.scala 140:31]
assign io_ifc_region_acc_fault_bf = 1'h0; // @[el2_ifu_ifc_ctrl.scala 41:30] assign io_ifc_fetch_req_bf = _T_40 & _T_41; // @[el2_ifu_ifc_ctrl.scala 84:23]
assign io_ifc_dma_access_ok = _T_154 | dma_iccm_stall_any_f; // @[el2_ifu_ifc_ctrl.scala 42:24 el2_ifu_ifc_ctrl.scala 141:24] assign io_ifc_fetch_req_bf_raw = ~idle; // @[el2_ifu_ifc_ctrl.scala 82:27]
assign io_mb_empty_mod = _T_52 & _T_53; // @[el2_ifu_ifc_ctrl.scala 98:19] assign io_ifc_iccm_access_bf = _T_141[31:16] == 16'hee00; // @[el2_ifu_ifc_ctrl.scala 134:25]
assign io_miss_f = _T_45 & _T_2; // @[el2_ifu_ifc_ctrl.scala 96:13] assign io_ifc_region_acc_fault_bf = _T_156 & iccm_acc_in_region_bf; // @[el2_ifu_ifc_ctrl.scala 139:30]
assign io_ifc_dma_access_ok = _T_154 | dma_iccm_stall_any_f; // @[el2_ifu_ifc_ctrl.scala 135:24]
`ifdef RANDOMIZE_GARBAGE_ASSIGN `ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE `define RANDOMIZE
`endif `endif
@ -214,9 +211,9 @@ initial begin
_RAND_4 = {1{`RANDOM}}; _RAND_4 = {1{`RANDOM}};
fb_full_f = _RAND_4[0:0]; fb_full_f = _RAND_4[0:0];
_RAND_5 = {1{`RANDOM}}; _RAND_5 = {1{`RANDOM}};
_T_161 = _RAND_5[0:0]; _T_163 = _RAND_5[0:0];
_RAND_6 = {1{`RANDOM}}; _RAND_6 = {1{`RANDOM}};
_T_163 = _RAND_6[30:0]; _T_165 = _RAND_6[30:0];
`endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE_REG_INIT
`endif // RANDOMIZE `endif // RANDOMIZE
end // initial end // initial
@ -251,14 +248,14 @@ end // initial
fb_full_f <= fb_full_f_ns; fb_full_f <= fb_full_f_ns;
end end
if (reset) begin if (reset) begin
_T_161 <= 1'h0; _T_163 <= 1'h0;
end else begin end else begin
_T_161 <= io_ifc_fetch_req_bf; _T_163 <= io_ifc_fetch_req_bf;
end end
if (reset) begin if (reset) begin
_T_163 <= 31'h0; _T_165 <= 31'h0;
end else if (fetch_bf_en) begin end else if (fetch_bf_en) begin
_T_163 <= io_ifc_fetch_addr_bf; _T_165 <= io_ifc_fetch_addr_bf;
end end
end end
endmodule endmodule

1
src/main/scala/ifu/el2_ifu_bp_ctl.scala
View File

@ -381,7 +381,6 @@ class el2_ifu_bp_ctl extends Module with el2_lib {
bht_bank0_rd_data_f := Mux1H((0 until BHT_ARRAY_DEPTH).map(i=>(bht_rd_addr_f(BHT_ADDR_HI-BHT_ADDR_LO,0)===i.U).asBool->bht_bank_rd_data_out(0)(i))) bht_bank0_rd_data_f := Mux1H((0 until BHT_ARRAY_DEPTH).map(i=>(bht_rd_addr_f(BHT_ADDR_HI-BHT_ADDR_LO,0)===i.U).asBool->bht_bank_rd_data_out(0)(i)))
bht_bank1_rd_data_f := Mux1H((0 until BHT_ARRAY_DEPTH).map(i=>(bht_rd_addr_f(BHT_ADDR_HI-BHT_ADDR_LO,0)===i.U).asBool->bht_bank_rd_data_out(1)(i))) bht_bank1_rd_data_f := Mux1H((0 until BHT_ARRAY_DEPTH).map(i=>(bht_rd_addr_f(BHT_ADDR_HI-BHT_ADDR_LO,0)===i.U).asBool->bht_bank_rd_data_out(1)(i)))
bht_bank0_rd_data_p1_f := Mux1H((0 until BHT_ARRAY_DEPTH).map(i=>(bht_rd_addr_p1_f(BHT_ADDR_HI-BHT_ADDR_LO,0)===i.U).asBool->bht_bank_rd_data_out(1)(i))) bht_bank0_rd_data_p1_f := Mux1H((0 until BHT_ARRAY_DEPTH).map(i=>(bht_rd_addr_p1_f(BHT_ADDR_HI-BHT_ADDR_LO,0)===i.U).asBool->bht_bank_rd_data_out(1)(i)))
} }
object ifu_bp extends App { object ifu_bp extends App {

264
src/main/scala/ifu/el2_ifu_compress_ctl.scala
View File

@ -14,24 +14,28 @@ class el2_ifu_compress_ctl extends Module {
out := (0 until 32).map(i=> 0.U.asBool) out := (0 until 32).map(i=> 0.U.asBool)
out(30) := pat(List(15, -14, -13, 10, -6, -5, 0)) | pat(List(15, -14, -13, -11, 10, 0)) out(30) := pat(List(15, -14, -13, 10, -6, -5, 0)) | pat(List(15, -14, -13, -11, 10, 0))
out(20) := pat(List(-14, 12, -11, -10, -9, -8, -7, -6, -5, -4, -3, -2, 1)) out(20) := pat(List(-14, 12, -11, -10, -9, -8, -7, -6, -5, -4, -3, -2, 1))
out(14) := pat(List(15, -14, -13, -11, 0)) | pat(List(15, -14, -13, -10, 0)) | pat(List(15, -14, -13, 6, 0)) |
pat(List(15, -14, -13, 5, 0)) out(14) := pat(List(15, -14, -13, -11, 0)) | pat(List(15, -14, -13, -10, 0)) | pat(List(15, -14, -13, 6, 0)) | pat(List(15, -14, -13, 5, 0))
out(13) := pat(List(15, -14, -13, 11, -10, 0)) | pat(List(15, -14, -13, 11, 6, 0)) | (io.din(14)&(!io.din(0))) out(13) := pat(List(15, -14, -13, 11, -10, 0)) | pat(List(15, -14, -13, 11, 6, 0)) | (io.din(14)&(!io.din(0)))
out(12) := pat(List(15, -14, -13, 6, 5, 0)) | pat(List(15, -14, -13, -11, 0)) | pat(List(15, -14, -13, -10, 0)) | out(12) := pat(List(15, -14, -13, 6, 5, 0)) | pat(List(15, -14, -13, -11, 0)) | pat(List(15, -14, -13, -10, 0)) |
pat(List(-15, -14, 1)) | pat(List(15, 14, 13)) pat(List(-15, -14, 1)) | pat(List(15, 14, 13))
out(6) := (pat(List(15, -14, -6, -5, -4, -3, -2)) & !io.din(0)) | pat(List(-14, 13)) | pat(List(15, 14, 0)) out(6) := (pat(List(15, -14, -6, -5, -4, -3, -2)) & !io.din(0)) | pat(List(-14, 13)) | pat(List(15, 14, 0))
out(5) := (io.din(15)&(!io.din(0))) | pat(List(15, 11, 10)) | pat(List(13, -8)) | pat(List(13, 7)) | out(5) := (io.din(15)&(!io.din(0))) | pat(List(15, 11, 10)) | pat(List(13, -8)) | pat(List(13, 7)) |
pat(List(13, 9)) | pat(List(13, 10)) | pat(List(13, 11)) | pat(List(-14, 13)) | pat(List(15, 14)) pat(List(13, 9)) | pat(List(13, 10)) | pat(List(13, 11)) | pat(List(-14, 13)) | pat(List(15, 14))
out(4) := (pat(List(-14, -11, -10, -9, -8, -7))&(!io.din(0))) | (pat(List(-15, -14))&(!io.din(0))) | out(4) := (pat(List(-14, -11, -10, -9, -8, -7))&(!io.din(0))) | (pat(List(-15, -14))&(!io.din(0))) |
(pat(List(-14, 6))&(!io.din(0))) | pat(List(-15, 14, 0)) | (pat(List(-14, 5))&(!io.din(0))) | (pat(List(-14, 6))&(!io.din(0))) | pat(List(-15, 14, 0)) | (pat(List(-14, 5))&(!io.din(0))) |
(pat(List(-14, 4))&(!io.din(0))) | (pat(List(-14, 3))&(!io.din(0))) | (pat(List(-14, 2))&(!io.din(0))) | (pat(List(-14, 4))&(!io.din(0))) | (pat(List(-14, 3))&(!io.din(0))) | (pat(List(-14, 2))&(!io.din(0))) |
pat(List(-14, -13, 0)) pat(List(-14, -13, 0))
out(3) := pat(List(-14, 13)) out(3) := pat(List(-14, 13))
out(2) := pat(List(-14, 12, 11, -6, -5, -4, -3, -2, 1)) | pat(List(-14, 12, 10, -6, -5, -4, -3, -2, 1)) | out(2) := pat(List(-14, 12, 11, -6, -5, -4, -3, -2, 1)) | pat(List(-14, 12, 10, -6, -5, -4, -3, -2, 1)) |
pat(List(-14, 12, 9, -6, -5, -4, -3, -2, 1)) | pat(List(-14, 12, 8, -6,-5,-4, -3, -2,1)) | pat(List(-14, 12, 9, -6, -5, -4, -3, -2, 1)) | pat(List(-14, 12, 8, -6,-5,-4, -3, -2,1)) |
pat(List(-14, 12, 7, -6, -5, -4, -3, -2,1)) | (pat(List(15, -14,-12, -6, -5, -4, -3, -2))&(!io.din(0))) | pat(List(-14, 12, 7, -6, -5, -4, -3, -2,1)) | (pat(List(15, -14,-12, -6, -5, -4, -3, -2))&(!io.din(0))) |
@ -39,6 +43,7 @@ class el2_ifu_compress_ctl extends Module {
pat(List(-15,13,11)) | pat(List(-14,13)) pat(List(-15,13,11)) | pat(List(-14,13))
out(1) := 1.U.asBool out(1) := 1.U.asBool
out(0) := 1.U.asBool out(0) := 1.U.asBool
val rs2d = io.din(6,2) val rs2d = io.din(6,2)
@ -62,29 +67,41 @@ class el2_ifu_compress_ctl extends Module {
val rdprs1 = pat(List(15,-13,0)) | pat(List(15,14,0)) | (pat(List(14,-1))&(!io.din(0))) val rdprs1 = pat(List(15,-13,0)) | pat(List(15,14,0)) | (pat(List(14,-1))&(!io.din(0)))
val rs2prs2 = pat(List(15,-14,-13,11,10,0)) | (pat(List(15,-1))&(!io.din(0))) val rs2prs2 = pat(List(15,-14,-13,11,10,0)) | (pat(List(15,-1))&(!io.din(0)))
val rs2prd = pat(List(-15,-1))&(!io.din(0)) val rs2prd = pat(List(-15,-1))&(!io.din(0))
val uimm9_2 = pat(List(-14,-1))&(!io.din(0)) val uimm9_2 = pat(List(-14,-1))&(!io.din(0))
val ulwimm6_2 = pat(List(-15,14,-1))&(!io.din(0)) val ulwimm6_2 = pat(List(-15,14,-1))&(!io.din(0))
val ulwspimm7_2 = pat(List(-15,14,1)) val ulwspimm7_2 = pat(List(-15,14,1))
val rdeq2 = pat(List(-15,14,13,-11,-10,-9,8,-7)) val rdeq2 = pat(List(-15,14,13,-11,-10,-9,8,-7))
val rdeq1 = pat(List(-14,12,11,-6,-5,-4,-3,-2,1)) | pat(List(-14,12,10,-6,-5,-4,-3,-2,1)) | val rdeq1 = pat(List(-14,12,11,-6,-5,-4,-3,-2,1)) | pat(List(-14,12,10,-6,-5,-4,-3,-2,1)) |
pat(List(-14,12,9,-6,-5,-4,-3,-2,1)) | pat(List(-14,12,8,-6,-5,-4,-3,-2,1)) | pat(List(-14,12,9,-6,-5,-4,-3,-2,1)) | pat(List(-14,12,8,-6,-5,-4,-3,-2,1)) |
pat(List(-14,12,7,-6,-5,-4,-3,-2,1)) | pat(List(-15,-14,13)) pat(List(-14,12,7,-6,-5,-4,-3,-2,1)) | pat(List(-15,-14,13))
val rs1eq2 = pat(List(-15,14,13,-11,-10,-9,8,-7)) | pat(List(14,1)) | (pat(List(-14,-1))&(!io.din(0))) val rs1eq2 = pat(List(-15,14,13,-11,-10,-9,8,-7)) | pat(List(14,1)) | (pat(List(-14,-1))&(!io.din(0)))
val sbroffset8_1 = pat(List(15,14,0)) val sbroffset8_1 = pat(List(15,14,0))
val simm9_4 = pat(List(-15,14,13,-11,-10,-9,8,-7)) val simm9_4 = pat(List(-15,14,13,-11,-10,-9,8,-7))
val simm5_0 = pat(List(-14,-13,11,-10,0)) | pat(List(-15,-13,0)) val simm5_0 = pat(List(-14,-13,11,-10,0)) | pat(List(-15,-13,0))
val sjaloffset11_1 = pat(List(-14,13)) val sjaloffset11_1 = pat(List(-14,13))
val sluimm17_12 = pat(List(-15,14,13,7)) |
pat(List(-15,14,13,-8)) | val sluimm17_12 = pat(List(-15,14,13,7)) | pat(List(-15,14,13,-8)) | pat(List(-15,14,13,9)) | pat(List(-15,14,13,10)) | pat(List(-15,14,13,11))
pat(List(-15,14,13,9)) |
pat(List(-15,14,13,10)) |
pat(List(-15,14,13,11))
val uimm5_0 = pat(List(15,-14,-13,-11,0)) | pat(List(-15,-14,1)) val uimm5_0 = pat(List(15,-14,-13,-11,0)) | pat(List(-15,-14,1))
val uswimm6_2 = pat(List(15,-1))&(!io.din(0)) val uswimm6_2 = pat(List(15,-1))&(!io.din(0))
val uswspimm7_2 = pat(List(15,14,1)) val uswspimm7_2 = pat(List(15,14,1))
val l1_6 = Cat(out(6),out(5),out(4),out(3),out(2),out(1),out(0)).asUInt() val l1_6 = Cat(out(6),out(5),out(4),out(3),out(2),out(1),out(0)).asUInt()
val l1_11 = Cat(out(11),out(10),out(9),out(8),out(7)).asUInt | Mux1H(Seq(rdrd.asBool->rdd, val l1_11 = Cat(out(11),out(10),out(9),out(8),out(7)).asUInt | Mux1H(Seq(rdrd.asBool->rdd,
rdprd.asBool->rdpd, rs2prd.asBool->rs2pd, rdeq1.asBool->1.U(5.W), rdeq2.asBool->2.U(5.W))) rdprd.asBool->rdpd, rs2prd.asBool->rs2pd, rdeq1.asBool->1.U(5.W), rdeq2.asBool->2.U(5.W)))
@ -95,7 +112,9 @@ class el2_ifu_compress_ctl extends Module {
val l1_24 = Cat(out(24),out(23),out(22),out(21),out(20)).asUInt | Mux1H(Seq(rs2rs2.asBool->rs2d, val l1_24 = Cat(out(24),out(23),out(22),out(21),out(20)).asUInt | Mux1H(Seq(rs2rs2.asBool->rs2d,
rs2prs2.asBool->rs2pd)) rs2prs2.asBool->rs2pd))
val l1_31 = Cat(out(31),out(30),out(29),out(28),out(27),out(26),out(25)).asUInt val l1_31 = Cat(out(31),out(30),out(29),out(28),out(27),out(26),out(25)).asUInt
val l1 = Cat(l1_31,l1_24,l1_19,l1_14,l1_11,l1_6) val l1 = Cat(l1_31,l1_24,l1_19,l1_14,l1_11,l1_6)
val simm5d = Cat(io.din(12), io.din(6,2)) val simm5d = Cat(io.din(12), io.din(6,2))
@ -127,13 +146,16 @@ class el2_ifu_compress_ctl extends Module {
val sbr8d = Cat(io.din(12),io.din(6),io.din(5),io.din(2),io.din(11),io.din(10),io.din(4),io.din(3),0.U) val sbr8d = Cat(io.din(12),io.din(6),io.din(5),io.din(2),io.din(11),io.din(10),io.din(4),io.din(3),0.U)
val uswimm6d = Cat(io.din(5), io.din(12,10), io.din(6), 0.U(2.W)) val uswimm6d = Cat(io.din(5), io.din(12,10), io.din(6), 0.U(2.W))
val uswspimm7d = Cat(io.din(8,7),io.din(12,9), 0.U(2.W)) val uswspimm7d = Cat(io.din(8,7),io.din(12,9), 0.U(2.W))
val l3_31 = l2(31,25) | Mux1H(Seq(sbroffset8_1.asBool->Cat(Fill(4,sbr8d(8)),sbr8d(7,5)), val l3_31 = l2(31,25) | Mux1H(Seq(sbroffset8_1.asBool->Cat(Fill(4,sbr8d(8)),sbr8d(7,5)),
uswimm6_2.asBool->Cat(0.U(5.W),uswimm6d(6,5)), uswimm6_2.asBool->Cat(0.U(5.W),uswimm6d(6,5)), uswspimm7_2.asBool->Cat(0.U(4.W),uswspimm7d(7,5))))
uswspimm7_2.asBool->Cat(0.U(4.W),uswspimm7d(7,5))))
val l3_24 = l2(24,12) val l3_24 = l2(24,12)
val l3_11 = l2(11,7) | Mux1H(Seq(sbroffset8_1.asBool->Cat(sbr8d(4,1), sbr8d(8)), val l3_11 = l2(11,7) | Mux1H(Seq(sbroffset8_1.asBool->Cat(sbr8d(4,1), sbr8d(8)),
uswimm6_2.asBool->uswimm6d(4,0), uswimm6_2.asBool->uswimm6d(4,0),
uswspimm7_2.asBool->uswspimm7d(4,0))) uswspimm7_2.asBool->uswspimm7d(4,0)))
val l3 = Cat(l3_31, l3_24, l3_11, l2(6,0)) val l3 = Cat(l3_31, l3_24, l3_11, l2(6,0))
val legal = (pat(List(-13,-12,11,1))&(!io.din(0))) | (pat(List(-13,-12,6,1))&(!io.din(0))) | val legal = (pat(List(-13,-12,11,1))&(!io.din(0))) | (pat(List(-13,-12,6,1))&(!io.din(0))) |
@ -150,228 +172,6 @@ class el2_ifu_compress_ctl extends Module {
io.dout:= l3 & Fill(32, legal) io.dout:= l3 & Fill(32, legal)
} }
//class ExpandedInstruction extends Bundle {
// val bits = UInt(32.W)
// val rd = UInt(5.W)
// val rs1 = UInt(5.W)
// val rs2 = UInt(5.W)
// val rs3 = UInt(5.W)
//}
//
//class RVCDecoder(x: UInt, xLen: Int) {
// def inst(bits: UInt, rd: UInt = x(11,7), rs1: UInt = x(19,15), rs2: UInt = x(24,20), rs3: UInt = x(31,27)) = {
// val res = Wire(new ExpandedInstruction)
// res.bits := bits
// res.rd := rd
// res.rs1 := rs1
// res.rs2 := rs2
// res.rs3 := rs3
// res
// }
//
// def rs1p = Cat(1.U(2.W), x(9,7))
// def rs2p = Cat(1.U(2.W), x(4,2))
// def rs2 = x(6,2)
// def rd = x(11,7)
// def addi4spnImm = Cat(x(10,7), x(12,11), x(5), x(6), 0.U(2.W))
// def lwImm = Cat(x(5), x(12,10), x(6), 0.U(2.W))
// def ldImm = Cat(x(6,5), x(12,10), 0.U(3.W))
// def lwspImm = Cat(x(3,2), x(12), x(6,4), 0.U(2.W))
// def ldspImm = Cat(x(4,2), x(12), x(6,5), 0.U(3.W))
// def swspImm = Cat(x(8,7), x(12,9), 0.U(2.W))
// def sdspImm = Cat(x(9,7), x(12,10), 0.U(3.W))
// def luiImm = Cat(Fill(15, x(12)), x(6,2), 0.U(12.W))
// def addi16spImm = Cat(Fill(3, x(12)), x(4,3), x(5), x(2), x(6), 0.U(4.W))
// def addiImm = Cat(Fill(7, x(12)), x(6,2))
// def jImm = Cat(Fill(10, x(12)), x(8), x(10,9), x(6), x(7), x(2), x(11), x(5,3), 0.U(1.W))
// def bImm = Cat(Fill(5, x(12)), x(6,5), x(2), x(11,10), x(4,3), 0.U(1.W))
// def shamt = Cat(x(12), x(6,2))
// def x0 = 0.U(5.W)
// def ra = 1.U(5.W)
// def sp = 2.U(5.W)
//
// def q0 = {
// def addi4spn = {
// val opc = Mux(x(12,5).orR, 0x13.U(7.W), 0x1F.U(7.W))
// inst(Cat(addi4spnImm, sp, 0.U(3.W), rs2p, opc), rs2p, sp, rs2p)
// }
// def ld = inst(Cat(ldImm, rs1p, 3.U(3.W), rs2p, 0x03.U(7.W)), rs2p, rs1p, rs2p)
// def lw = inst(Cat(lwImm, rs1p, 2.U(3.W), rs2p, 0x03.U(7.W)), rs2p, rs1p, rs2p)
// def fld = inst(Cat(ldImm, rs1p, 3.U(3.W), rs2p, 0x07.U(7.W)), rs2p, rs1p, rs2p)
// def flw = {
// if (xLen == 32) inst(Cat(lwImm, rs1p, 2.U(3.W), rs2p, 0x07.U(7.W)), rs2p, rs1p, rs2p)
// else ld
// }
// def unimp = inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x3F.U(7.W)), rs2p, rs1p, rs2p)
// def sd = inst(Cat(ldImm >> 5, rs2p, rs1p, 3.U(3.W), ldImm(4,0), 0x23.U(7.W)), rs2p, rs1p, rs2p)
// def sw = inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x23.U(7.W)), rs2p, rs1p, rs2p)
// def fsd = inst(Cat(ldImm >> 5, rs2p, rs1p, 3.U(3.W), ldImm(4,0), 0x27.U(7.W)), rs2p, rs1p, rs2p)
// def fsw = {
// if (xLen == 32) inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x27.U(7.W)), rs2p, rs1p, rs2p)
// else sd
// }
// Seq(addi4spn, fld, lw, flw, unimp, fsd, sw, fsw)
// }
//
// def q1 = {
// def addi = inst(Cat(addiImm, rd, 0.U(3.W), rd, 0x13.U(7.W)), rd, rd, rs2p)
// def addiw = {
// val opc = Mux(rd.orR, 0x1B.U(7.W), 0x1F.U(7.W))
// inst(Cat(addiImm, rd, 0.U(3.W), rd, opc), rd, rd, rs2p)
// }
// def jal = {
// if (xLen == 32) inst(Cat(jImm(20), jImm(10,1), jImm(11), jImm(19,12), ra, 0x6F.U(7.W)), ra, rd, rs2p)
// else addiw
// }
// def li = inst(Cat(addiImm, x0, 0.U(3.W), rd, 0x13.U(7.W)), rd, x0, rs2p)
// def addi16sp = {
// val opc = Mux(addiImm.orR, 0x13.U(7.W), 0x1F.U(7.W))
// inst(Cat(addi16spImm, rd, 0.U(3.W), rd, opc), rd, rd, rs2p)
// }
// def lui = {
// val opc = Mux(addiImm.orR, 0x37.U(7.W), 0x3F.U(7.W))
// val me = inst(Cat(luiImm(31,12), rd, opc), rd, rd, rs2p)
// Mux(rd === x0 || rd === sp, addi16sp, me)
// }
// def j = inst(Cat(jImm(20), jImm(10,1), jImm(11), jImm(19,12), x0, 0x6F.U(7.W)), x0, rs1p, rs2p)
// def beqz = inst(Cat(bImm(12), bImm(10,5), x0, rs1p, 0.U(3.W), bImm(4,1), bImm(11), 0x63.U(7.W)), rs1p, rs1p, x0)
// def bnez = inst(Cat(bImm(12), bImm(10,5), x0, rs1p, 1.U(3.W), bImm(4,1), bImm(11), 0x63.U(7.W)), x0, rs1p, x0)
// def arith = {
// def srli = Cat(shamt, rs1p, 5.U(3.W), rs1p, 0x13.U(7.W))
// def srai = srli | (1 << 30).U
// def andi = Cat(addiImm, rs1p, 7.U(3.W), rs1p, 0x13.U(7.W))
// def rtype = {
// val funct = VecInit(0.U, 4.U, 6.U, 7.U, 0.U, 0.U, 2.U, 3.U)(Cat(x(12), x(6,5)))
// val sub = Mux(x(6,5) === 0.U, (1 << 30).U, 0.U)
// val opc = Mux(x(12), 0x3B.U(7.W), 0x33.U(7.W))
// Cat(rs2p, rs1p, funct, rs1p, opc) | sub
// }
// inst(VecInit(srli, srai, andi, rtype)(x(11,10)), rs1p, rs1p, rs2p)
// }
// Seq(addi, jal, li, lui, arith, j, beqz, bnez)
// }
//
// def q2 = {
// val load_opc = Mux(rd.orR, 0x03.U(7.W), 0x1F.U(7.W))
// def slli = inst(Cat(shamt, rd, 1.U(3.W), rd, 0x13.U(7.W)), rd, rd, rs2)
// def ldsp = inst(Cat(ldspImm, sp, 3.U(3.W), rd, load_opc), rd, sp, rs2)
// def lwsp = inst(Cat(lwspImm, sp, 2.U(3.W), rd, load_opc), rd, sp, rs2)
// def fldsp = inst(Cat(ldspImm, sp, 3.U(3.W), rd, 0x07.U(7.W)), rd, sp, rs2)
// def flwsp = {
// if (xLen == 32) inst(Cat(lwspImm, sp, 2.U(3.W), rd, 0x07.U(7.W)), rd, sp, rs2)
// else ldsp
// }
// def sdsp = inst(Cat(sdspImm >> 5, rs2, sp, 3.U(3.W), sdspImm(4,0), 0x23.U(7.W)), rd, sp, rs2)
// def swsp = inst(Cat(swspImm >> 5, rs2, sp, 2.U(3.W), swspImm(4,0), 0x23.U(7.W)), rd, sp, rs2)
// def fsdsp = inst(Cat(sdspImm >> 5, rs2, sp, 3.U(3.W), sdspImm(4,0), 0x27.U(7.W)), rd, sp, rs2)
// def fswsp = {
// if (xLen == 32) inst(Cat(swspImm >> 5, rs2, sp, 2.U(3.W), swspImm(4,0), 0x27.U(7.W)), rd, sp, rs2)
// else sdsp
// }
// def jalr = {
// val mv = inst(Cat(rs2, x0, 0.U(3.W), rd, 0x33.U(7.W)), rd, x0, rs2)
// val add = inst(Cat(rs2, rd, 0.U(3.W), rd, 0x33.U(7.W)), rd, rd, rs2)
// val jr = Cat(rs2, rd, 0.U(3.W), x0, 0x67.U(7.W))
// val reserved = Cat(jr >> 7, 0x1F.U(7.W))
// val jr_reserved = inst(Mux(rd.orR, jr, reserved), x0, rd, rs2)
// val jr_mv = Mux(rs2.orR, mv, jr_reserved)
// val jalr = Cat(rs2, rd, 0.U(3.W), ra, 0x67.U(7.W))
// val ebreak = Cat(jr >> 7, 0x73.U(7.W)) | (1 << 20).U
// val jalr_ebreak = inst(Mux(rd.orR, jalr, ebreak), ra, rd, rs2)
// val jalr_add = Mux(rs2.orR, add, jalr_ebreak)
// Mux(x(12), jalr_add, jr_mv)
// }
// Seq(slli, fldsp, lwsp, flwsp, jalr, fsdsp, swsp, fswsp)
// }
//
// def q3 = Seq.fill(8)(passthrough)
//
// def passthrough = inst(x)
//
// def decode = {
// val s = VecInit(q0 ++ q1 ++ q2 ++ q3)
// s(Cat(x(1,0), x(15,13)))
// }
//
//
//
// def changed_q0 = {
// def addi4spn = {
// val opc = Mux(x(12,5).orR, 0x13.U(7.W), 0x1F.U(7.W))
// inst(Cat(addi4spnImm, sp, 0.U(3.W), rs2p, opc), rs2p, sp, rs2p)
// }
// def ld = inst(Cat(ldImm, rs1p, 3.U(3.W), rs2p, 0x03.U(7.W)), rs2p, rs1p, rs2p)
// def lw = inst(Cat(lwImm, rs1p, 2.U(3.W), rs2p, 0x03.U(7.W)), rs2p, rs1p, rs2p)
// def fld = inst(Cat(ldImm, rs1p, 3.U(3.W), rs2p, 0x07.U(7.W)), rs2p, rs1p, rs2p)
// def flw = {
// if (xLen == 32) inst(Cat(lwImm, rs1p, 2.U(3.W), rs2p, 0x07.U(7.W)), rs2p, rs1p, rs2p)
// else ld
// }
// def unimp = inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x3F.U(7.W)), rs2p, rs1p, rs2p)
// def sd = inst(Cat(ldImm >> 5, rs2p, rs1p, 3.U(3.W), ldImm(4,0), 0x23.U(7.W)), rs2p, rs1p, rs2p)
// def sw = inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x23.U(7.W)), rs2p, rs1p, rs2p)
// def fsd = inst(Cat(ldImm >> 5, rs2p, rs1p, 3.U(3.W), ldImm(4,0), 0x27.U(7.W)), rs2p, rs1p, rs2p)
// def fsw = {
// if (xLen == 32) inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x27.U(7.W)), rs2p, rs1p, rs2p)
// else sd
// }
// addi4spn
// }
//
// def ret_q0 = VecInit(q0)
// def ret_q1 = q1
// def ret_q2 = q2
// def ret_q3 = q3
//}
//
//class el2_ifu_compress_ctl( val XLen: Int, val usingCompressed: Boolean) extends Module {
// val io = IO(new Bundle {
// val din = Input(UInt(32.W))
// val dout = Output(new ExpandedInstruction)
// //val rvc = Output(Bool())
// //val legal = Output(Bool())
// //val waleed_out = Output(UInt(32.W))
// //val q1_Out = Output(new ExpandedInstruction)
// //val q2_Out = Output(new ExpandedInstruction)
// //val q3_Out = Output(new ExpandedInstruction)
// })
// if (usingCompressed) {
// val rvc = io.din(1,0) =/= 3.U
// val inst = new RVCDecoder(io.din, XLen)
// val decoded = inst.decode
// io.dout := inst.decode
// //io.out.rd := 0.U
// //io.out.rs1 := 0.U
// //io.out.rs2 := 0.U
// //io.out.rs3 := 0.U
// /*io.legal := (!io.in(13))&(!io.in(12))&(io.in(11))&io.in(1)&(!io.in(0)) |
// (!io.in(13))&(!io.in(12))&(io.in(6))&io.in(1)&(!io.in(0)) |
// (!io.in(15))&(!io.in(13))&io.in(11)(!io.in(1)) |
// (!io.in(13))&(!io.in(12))&io.in(5)&io.in(1)&(!io.in(0)) |
// (!io.in(13))&(!io.in(12))&io.in(10)&(!io.in(1))&io.in(0) |
// (!io.in(15))&(!io.in(13))&io.in(6)&(!io.in(1)) | io.in(15)&(!io.in(12))&(!io.in(1))&io.in(0) |
// (!io.in(13))&(!io.in(12))&io.in(9)&io.in(1)&(!io.in(0)) |
// (!io.in(12))&io.in(6)&(!io.in(1))&io.in(0) |
// (!io.in(15))&(!io.in(13))&io.in(5)&(!io.in(1)) |
// (!io.in(13))&(!io.in(12))&io.in(8)&io.in(1)&(!io.in(0)) |
// (!io.in(12))&io.in(5)&(!io.in(1))&io.in(0) |
// (!io.in(15))&(!io.in(13))&io.in(10)&(!io.in(1)) | (!io.in(13))&(!io.in(12))&io.in(7)&io.in(1)&(!io.in(0)) |
// io.in(12)&io.in(11)&(!io.in(10))&(!io.in(1))&io.in(0) | (!io.in(15))&(!io.in(13))&io.in(9)&(!io.in(1)) |
// (!io.in(13))&(!io.in(12))&io.in(4)&io.in(1)&(!io.in(0)) | io.in(13)&io.in(12)&(!io.in(1))&io.in(0) |
// (!io.in(15))&(!io.in(13))&io.in(8)&(!io.in(1)) | (!io.in(13))&(!io.in(12))&io.in(3)&io.in(1)&(!io.in(0)) |
// io.in(13)&io.in(4)&(!io.in(1))&io.in(0) | (!io.in(13))&(!io.in(12))&io.in(2)&io.in(1)&(!io.in(0)) |
// (!io.in(15))&(!io.in(13))&io.in(7)&(!io.in(1)) | io.in(13)&io.in(3)&(!io.in(1))&io.in(0) |
// io.in(13)&io.in(2)&(!io.in(1))&io.in(0) | io.in(14)&(!io.in(13))&(!io.in(1)) |
// (!io.in(14))&(!io.in(12))&(!io.in(1))&io.in(0) | io.in(15)&(!io.in(13))&io.in(12)&io.in(1)&(!io.in(0)) |
// (!io.in(15))&(!io.in(13))&(!io.in(12))&io.in(1)&(!io.in(0)) | (!io.in(15))&(!io.in(13))&io.in(12)&(!io.in(1)) |
// io.in(14)&(!io.in(13))&(!io.in(0))
// io.waleed_out := Mux(io.legal,io.out.bits,0.U)*/
// } else {
// //io.rvc := false.B
// io.dout := new RVCDecoder(io.din, XLen).passthrough
// }
//}
object ifu_compress extends App { object ifu_compress extends App {
println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_compress_ctl())) println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_compress_ctl()))
} }

218
src/main/scala/ifu/el2_ifu_ic_mem.scala
View File

@ -5,8 +5,6 @@ import chisel3.util._
class el2_ifu_ic_mem extends Module with param{ class el2_ifu_ic_mem extends Module with param{
val io = IO(new Bundle{ val io = IO(new Bundle{
val clk = Input(Bool())
val rst_l = Input(Bool())
val clk_override = Input(Bool()) val clk_override = Input(Bool())
val dec_tlu_core_ecc_disable = Input(Bool()) val dec_tlu_core_ecc_disable = Input(Bool())
val ic_rw_addr = Input(UInt(31.W)) val ic_rw_addr = Input(UInt(31.W))
@ -67,7 +65,7 @@ class EL2_IC_TAG extends Module with el2_lib with param {
val ic_tag_wren = io.ic_wr_en & repl(ICACHE_NUM_WAYS, io.ic_rw_addr(ICACHE_BEAT_ADDR_HI,4)=== val ic_tag_wren = io.ic_wr_en & repl(ICACHE_NUM_WAYS, io.ic_rw_addr(ICACHE_BEAT_ADDR_HI,4)===
repl(ICACHE_NUM_WAYS-1, 1.U)) repl(ICACHE_NUM_WAYS-1, 1.U))
val ic_debug_rd_way_en = repl(ICACHE_NUM_WAYS, io.ic_debug_rd_en & io.ic_debug_tag_array) & io.ic_debug_way val ic_debug_rd_way_en = Fill(ICACHE_NUM_WAYS, io.ic_debug_rd_en & io.ic_debug_tag_array) & io.ic_debug_way
val ic_debug_wr_way_en = repl(ICACHE_NUM_WAYS, io.ic_debug_wr_en & io.ic_debug_tag_array) & io.ic_debug_way val ic_debug_wr_way_en = repl(ICACHE_NUM_WAYS, io.ic_debug_wr_en & io.ic_debug_tag_array) & io.ic_debug_way
val ic_tag_clken = repl(ICACHE_NUM_WAYS,io.ic_rd_en | io.clk_override) | io.ic_wr_en | ic_debug_wr_way_en | val ic_tag_clken = repl(ICACHE_NUM_WAYS,io.ic_rd_en | io.clk_override) | io.ic_wr_en | ic_debug_wr_way_en |
ic_debug_rd_way_en ic_debug_rd_way_en
@ -169,118 +167,122 @@ class EL2_IC_TAG extends Module with el2_lib with param {
class EL2_IC_DATA extends Module with el2_lib { class EL2_IC_DATA extends Module with el2_lib {
val io = IO (new Bundle{ val io = IO (new Bundle{
val rst_l = Input(UInt(1.W)) val clk_override = Input(Bool())
val clk_override = Input(UInt(1.W)) val ic_rw_addr = Input(UInt(ICACHE_INDEX_HI.W))
val ic_rw_addr = Input(UInt((ICACHE_INDEX_HI+1).W)) val ic_wr_en = Input(UInt(ICACHE_NUM_WAYS.W))
val ic_wr_en = Input(UInt(ICACHE_NUM_WAYS.W)) val ic_rd_en = Input(Bool())
val ic_rd_en = Input(UInt(1.W)) val ic_wr_data = Input(Vec(ICACHE_NUM_WAYS, UInt(71.W)))
val ic_wr_data = Input(Vec(ICACHE_NUM_WAYS, UInt(71.W))) val ic_rd_data = Output(UInt(64.W))
val ic_rd_data = Output(UInt(64.W)) val ic_debug_wr_data = Input(UInt(71.W))
val ic_debug_wr_data = Input(UInt(71.W)) val ic_debug_rd_data = Output(UInt(71.W))
val ic_debug_rd_data = Output(UInt(71.W)) val ic_parerr = Output(UInt(ICACHE_NUM_WAYS.W))
val ic_parerr = Output(UInt(ICACHE_NUM_WAYS.W)) val ic_eccerr = Output(UInt(ICACHE_BANKS_WAY.W))
val ic_eccerr = Output(UInt(ICACHE_BANKS_WAY.W)) val ic_debug_addr = Input(UInt((ICACHE_INDEX_HI-3).W))
val ic_debug_addr = Input(UInt((ICACHE_INDEX_HI+1).W)) val ic_debug_rd_en = Input(Bool())
val ic_debug_rd_en = Input(UInt(1.W)) val ic_debug_wr_en = Input(Bool())
val ic_debug_wr_en = Input(UInt(1.W)) val ic_debug_tag_array = Input(Bool())
val ic_debug_tag_array = Input(UInt(1.W)) val ic_debug_way = Input(UInt(ICACHE_NUM_WAYS.W))
val ic_debug_way = Input(UInt(ICACHE_NUM_WAYS.W)) val ic_premux_data = Input(UInt(64.W))
val ic_premux_data = Input(UInt(64.W)) val ic_sel_premux_data = Input(Bool())
val ic_sel_premux_data = Input(Bool()) val ic_rd_hit = Input(UInt(ICACHE_NUM_WAYS.W))
val ic_rd_hit = Input(UInt(ICACHE_NUM_WAYS.W)) val scan_mode = Input(UInt(1.W))
val scan_mode = Input(UInt(1.W))
val test_port2 = Output(UInt()) val test = Output(Vec(ICACHE_BANKS_WAY, UInt()))
val test_port = Output(Vec(ICACHE_BANKS_WAY, Vec(ICACHE_NUM_WAYS, UInt(71.W)))) // val test_port = Output(Vec(ICACHE_BANKS_WAY, Vec(ICACHE_NUM_WAYS, UInt(71.W))))
}) })
val ic_debug_rd_way_en = repl(ICACHE_NUM_WAYS, io.ic_debug_rd_en & ~io.ic_debug_tag_array) & io.ic_debug_way
val ic_debug_wr_way_en = repl(ICACHE_NUM_WAYS, io.ic_debug_wr_en & ~io.ic_debug_tag_array) & io.ic_debug_way
val ic_b_sb_wren = VecInit.tabulate(ICACHE_NUM_WAYS)(i=>
io.ic_wr_en|ic_debug_wr_way_en & repl(ICACHE_NUM_WAYS, io.ic_debug_addr(ICACHE_BANK_HI,ICACHE_BANK_LO)===i.U)).reverse
val ic_sb_wr_data = VecInit.tabulate(ICACHE_NUM_WAYS)(i=>
Mux(((io.ic_debug_addr(ICACHE_BANK_HI,ICACHE_BANK_LO)===i.U) & io.ic_debug_wr_en).asBool, io.ic_debug_wr_data, io.ic_wr_data(i))).reverse
val ic_rw_addr_q = Cat(Mux((io.ic_debug_rd_en | io.ic_debug_wr_en).asBool, Cat(io.ic_debug_addr(ICACHE_INDEX_HI,3),0.U(2.W)), io.ic_rw_addr(ICACHE_INDEX_HI,1)), 0.U(1.W))
val ic_rd_en_with_debug = (io.ic_rd_en | io.ic_debug_rd_en ) & ~(io.ic_wr_en.orR)
val ic_b_rden = (VecInit.tabulate(ICACHE_BANKS_WAY)(i=>
Mux1H(Seq(~ic_rw_addr_q(ICACHE_BANK_HI).asBool -> (i.U === 0.U),
(ic_rw_addr_q(ICACHE_BANK_HI)&(ic_rw_addr_q(2,1)===3.U)).asBool -> (i.U === 0.U),
ic_rw_addr_q(ICACHE_BANK_HI).asBool -> (i.U === 1.U),
(~ic_rw_addr_q(ICACHE_BANK_HI)&(ic_rw_addr_q(2,1)===3.U)).asBool -> (i.U === 1.U))))).reverse.map(_ & ic_rd_en_with_debug)
//val ic_b_sb_rden = ic_b_rden.map(repl(ICACHE_NUM_WAYS, _))
val ic_bank_way_clken = new Array[UInt](ICACHE_NUM_WAYS)
ic_bank_way_clken(0) = (repl(ICACHE_NUM_WAYS,ic_b_rden(0)) | io.clk_override | ic_b_sb_wren(0))
for(i<-1 until ICACHE_NUM_WAYS){
ic_bank_way_clken(i) = (repl(ICACHE_NUM_WAYS,ic_b_rden(0)) | io.clk_override | ic_b_sb_wren(i)) | ic_bank_way_clken(i-1)
}
// TODO: AS it is being used at only one place replace
val ic_rw_addr_q_inc = ic_rw_addr_q(ICACHE_TAG_LO-1,ICACHE_DATA_INDEX_LO) + 1.U
val ic_rw_addr_wrap = ic_rw_addr_q(ICACHE_BANK_HI) & (ic_rw_addr_q(2,1)===3.U) & ic_rd_en_with_debug & ~(io.ic_wr_en.orR)
// All flops rw-address
// rd-enable as it is a sync mem
val ic_rw_addr_ff = RegNext(ic_rw_addr_q, init = 0.U)
val ic_b_rden_ff = RegNext(ic_b_rden.reverse.reduce(Cat(_,_)), init = 0.U)
val ic_debug_rd_way_en_ff = RegNext(ic_debug_rd_way_en, init = 0.U)
val ic_debug_rd_en_ff = RegNext(io.ic_debug_rd_en, init = 0.U)
val ic_cacheline_wrap_ff = ic_rw_addr_ff(ICACHE_TAG_INDEX_LO-1,ICACHE_BANK_LO) === repl(ICACHE_TAG_INDEX_LO - ICACHE_BANK_LO, 1.U)
val ic_rw_addr_bank_q = Wire(Vec(ICACHE_BANKS_WAY,UInt((ICACHE_INDEX_HI+1).W)))
ic_rw_addr_bank_q(0) := Mux(~ic_rw_addr_wrap.asBool, ic_rw_addr_q(ICACHE_INDEX_HI,ICACHE_DATA_INDEX_LO), Cat(ic_rw_addr_q(ICACHE_INDEX_HI, ICACHE_TAG_INDEX_LO), ic_rw_addr_q_inc(ICACHE_TAG_INDEX_LO-1, ICACHE_DATA_INDEX_LO)))
ic_rw_addr_bank_q(1) := ic_rw_addr_q(ICACHE_INDEX_HI, ICACHE_DATA_INDEX_LO)
val (data_mem_word, tag_mem_word, ecc_offset) = DATA_MEM_LINE
// Making a memory with Location=ICACHE_DATA_DEPTH banks and ways
val data_mem = SyncReadMem(ICACHE_DATA_DEPTH, Vec(ICACHE_BANKS_WAY,Vec(ICACHE_NUM_WAYS, UInt(data_mem_word.W))))
data_mem(ic_rw_addr_bank_q(0)(ICACHE_INDEX_HI,ICACHE_DATA_INDEX_LO))(0)(0):= ic_sb_wr_data(0)
val wb_dout = Wire(Vec(ICACHE_NUM_WAYS, Vec(ICACHE_BANKS_WAY, UInt(data_mem_word.W))))
// Initializing the wire
wb_dout.indices.foreach { i => wb_dout(i).indices.foreach{ j=>
wb_dout(i)(j) := 0.U
when(ic_sb_wr_data(i)(j) & ic_bank_way_clken(i)(j)){
data_mem(ic_rw_addr_bank_q(j)(ICACHE_INDEX_HI,ICACHE_DATA_INDEX_LO))(j)(i) := ic_sb_wr_data(j)
}
wb_dout(i)(j) := data_mem(ic_rw_addr_bank_q(j)(ICACHE_INDEX_HI,ICACHE_DATA_INDEX_LO))(i)(j)
}
}
val wb_dout_way_pre_lower = (0 until ICACHE_NUM_WAYS).map(i=>
(0 until ICACHE_BANKS_WAY).map(j=>
repl(data_mem_word,ic_rw_addr_ff(ICACHE_BANK_HI, ICACHE_BANK_LO)===j.U)&wb_dout(i)(j)).reduce(_|_))
val wb_dout_way_pre_upper = (0 until ICACHE_NUM_WAYS).map(i=>
(0 until ICACHE_BANKS_WAY).map(j=>
repl(data_mem_word,ic_rw_addr_ff(ICACHE_BANK_HI, ICACHE_BANK_LO)===j.U-1.U)&wb_dout(i)(j)).reduce(_|_))
val wb_dout_way_pre = (0 until ICACHE_NUM_WAYS).map(i=>Cat(wb_dout_way_pre_upper(i),wb_dout_way_pre_lower(i)))
// TODO: Put an assertion here
val wb_dout_way = (0 until ICACHE_NUM_WAYS).map(i=>
repl(64 ,ic_rw_addr_ff(2,1)===0.U) & wb_dout_way_pre(i)(63,0) |
repl(64 ,ic_rw_addr_ff(2,1)===1.U) & Cat(wb_dout_way_pre(i)(ecc_offset+15,ecc_offset),wb_dout_way_pre(i)(63,16)) |
repl(64 ,ic_rw_addr_ff(2,1)===2.U) & Cat(wb_dout_way_pre(i)(ecc_offset+31,ecc_offset),wb_dout_way_pre(i)(63,32)) |
repl(64 ,ic_rw_addr_ff(2,1)===3.U) & Cat(wb_dout_way_pre(i)(ecc_offset+47,ecc_offset),wb_dout_way_pre(i)(63,48))
)
// ic_rw_addr_ff(ICACHE_BANK_HI,ICACHE_BANK_LO)===1.U -> wb_dout(1)(0)))
val ic_rd_hit_q = Mux(ic_debug_rd_en_ff===1.U, ic_debug_rd_way_en_ff, io.ic_rd_hit) ;
val wb_dout_way_with_premux = wb_dout_way.map(Mux(io.ic_sel_premux_data, io.ic_premux_data, _))
io.ic_rd_data := 0.U
io.ic_debug_rd_data := 0.U io.ic_debug_rd_data := 0.U
io.ic_parerr := 0.U io.ic_parerr := 0.U
io.ic_eccerr := 0.U io.ic_eccerr := 0.U
val ic_debug_rd_way_en = Fill(ICACHE_NUM_WAYS, io.ic_debug_rd_en & !io.ic_debug_tag_array) & io.ic_debug_way
val ic_debug_wr_way_en = repl(ICACHE_NUM_WAYS, io.ic_debug_wr_en & !io.ic_debug_tag_array) & io.ic_debug_way
io.ic_rd_data := Mux1H_LM((0 until ICACHE_NUM_WAYS).map(i => ic_rd_hit_q(i) | io.ic_sel_premux_data), val ic_bank_wr_data = WireInit(UInt(71.W))
(0 until ICACHE_NUM_WAYS).map(wb_dout_way_with_premux(_))) val ic_rw_addr_q = WireInit(UInt(ICACHE_INDEX_HI.W), 0.U)
io.ic_debug_rd_data := Mux1H_LM((0 until ICACHE_NUM_WAYS).map(i => ic_rd_hit_q(i)), val ic_rd_en_with_debug = WireInit(Bool(), 0.U)
(0 until ICACHE_NUM_WAYS).map(wb_dout_way_pre(_)(data_mem_word-1,0)))
val wb_dout_ecc = Mux1H_LM((0 until ICACHE_NUM_WAYS).map(i => ic_rd_hit_q(i)),
(0 until ICACHE_NUM_WAYS).map(wb_dout_way_pre(_)))
io.test_port2 := 0.U//inter2//wb_dout_way_pre
io.test_port := wb_dout
//data_mem(ic_rw_addr_bank_q)(ICACHE_BANK_HI,ICACHE_BANK_LO)(ic_debug_rd_way_en) val ic_b_sb_wren = (0 until ICACHE_NUM_WAYS).map(i=>
//ic_memory.write(io.ic_rw_addr, io.ic_wr_data, io.mask) io.ic_wr_en | ic_debug_wr_way_en & Fill(ICACHE_NUM_WAYS, io.ic_debug_addr(ICACHE_BANK_HI-3,ICACHE_BANK_LO-3)===i.U))
//io.ic_debug_rd_data := 0.U //val ic_debug_sel_sb = (0 until ICACHE_NUM_WAYS).map(i=> (io.ic_debug_addr(ICACHE_BANK_HI-3,ICACHE_BANK_LO-3)===i.U).asBool).reverse.reduce(Cat(_,_))
//io.ic_rd_data := 0.U //val ic_sb_wr_data = (0 until ICACHE_NUM_WAYS).map(i=> Mux((ic_debug_sel_sb(i)&io.ic_debug_wr_en).asBool, io.ic_debug_wr_data, ic_bank_wr_data(i)))
//io.ic_eccerr := 0.U val ic_b_rden = VecInit.tabulate(ICACHE_BANKS_WAY)(i=>
//io.ic_parerr := 0.U Mux1H(Seq(!ic_rw_addr_q(ICACHE_BANK_HI-1).asBool -> (i.U === 0.U),
//val (a,b) = DATA_MEM_LINE (ic_rw_addr_q(ICACHE_BANK_HI-1)).asBool -> ((ic_rw_addr_q(1,0)===3.U)&(i.U===0.U)),
//println(s"${DATA_MEM_LINE._2}") ic_rw_addr_q(ICACHE_BANK_HI-1).asBool -> (i.U === 1.U),
(!ic_rw_addr_q(ICACHE_BANK_HI-1)).asBool -> ((ic_rw_addr_q(1,0)===3.U)&(i.U === 1.U)))) & ic_rd_en_with_debug)
val ic_b_sb_rden = ic_b_rden.map(Fill(ICACHE_NUM_WAYS, _))
// val ic_bank_way_clken = (0 until ICACHE_BANKS_WAY).map(i=>(0 until ICACHE_NUM_WAYS).map(j=>
// ic_b_sb_rden(i)(j) | io.clk_override | ic_b_sb_wren(i)(j)).reduce(Cat(_,_)))
// val ic_bank_way_clken = new Array[UInt](ICACHE_NUM_WAYS)
// ic_bank_way_clken(0) = (repl(ICACHE_NUM_WAYS,ic_b_rden(0)) | io.clk_override | ic_b_sb_wren(0))
// for(i<-1 until ICACHE_NUM_WAYS){
// ic_bank_way_clken(i) = (repl(ICACHE_NUM_WAYS,ic_b_rden(0)) | io.clk_override | ic_b_sb_wren(i)) | ic_bank_way_clken(i-1)
// }
// // TODO: AS it is being used at only one place replace
// val ic_rw_addr_q_inc = ic_rw_addr_q(ICACHE_TAG_LO-1,ICACHE_DATA_INDEX_LO) + 1.U
// val ic_rw_addr_wrap = ic_rw_addr_q(ICACHE_BANK_HI) & (ic_rw_addr_q(2,1)===3.U) & ic_rd_en_with_debug & ~(io.ic_wr_en.orR)
// // All flops rw-address
// // rd-enable as it is a sync mem
// val ic_rw_addr_ff = RegNext(ic_rw_addr_q, init = 0.U)
// val ic_b_rden_ff = RegNext(ic_b_rden.reverse.reduce(Cat(_,_)), init = 0.U)
// val ic_debug_rd_way_en_ff = RegNext(ic_debug_rd_way_en, init = 0.U)
// val ic_debug_rd_en_ff = RegNext(io.ic_debug_rd_en, init = 0.U)
// val ic_cacheline_wrap_ff = ic_rw_addr_ff(ICACHE_TAG_INDEX_LO-1,ICACHE_BANK_LO) === repl(ICACHE_TAG_INDEX_LO - ICACHE_BANK_LO, 1.U)
//
// val ic_rw_addr_bank_q = Wire(Vec(ICACHE_BANKS_WAY,UInt((ICACHE_INDEX_HI+1).W)))
// ic_rw_addr_bank_q(0) := Mux(~ic_rw_addr_wrap.asBool, ic_rw_addr_q(ICACHE_INDEX_HI,ICACHE_DATA_INDEX_LO), Cat(ic_rw_addr_q(ICACHE_INDEX_HI, ICACHE_TAG_INDEX_LO), ic_rw_addr_q_inc(ICACHE_TAG_INDEX_LO-1, ICACHE_DATA_INDEX_LO)))
// ic_rw_addr_bank_q(1) := ic_rw_addr_q(ICACHE_INDEX_HI, ICACHE_DATA_INDEX_LO)
// val (data_mem_word, tag_mem_word, ecc_offset) = DATA_MEM_LINE
// // Making a memory with Location=ICACHE_DATA_DEPTH banks and ways
// val data_mem = SyncReadMem(ICACHE_DATA_DEPTH, Vec(ICACHE_BANKS_WAY,Vec(ICACHE_NUM_WAYS, UInt(data_mem_word.W))))
// data_mem(ic_rw_addr_bank_q(0)(ICACHE_INDEX_HI,ICACHE_DATA_INDEX_LO))(0)(0):= ic_sb_wr_data(0)
// val wb_dout = Wire(Vec(ICACHE_NUM_WAYS, Vec(ICACHE_BANKS_WAY, UInt(data_mem_word.W))))
// // Initializing the wire
// wb_dout.indices.foreach { i => wb_dout(i).indices.foreach{ j=>
// wb_dout(i)(j) := 0.U
// when(ic_sb_wr_data(i)(j) & ic_bank_way_clken(i)(j)){
// data_mem(ic_rw_addr_bank_q(j)(ICACHE_INDEX_HI,ICACHE_DATA_INDEX_LO))(j)(i) := ic_sb_wr_data(j)
// }
// wb_dout(i)(j) := data_mem(ic_rw_addr_bank_q(j)(ICACHE_INDEX_HI,ICACHE_DATA_INDEX_LO))(i)(j)
// }
// }
// val wb_dout_way_pre_lower = (0 until ICACHE_NUM_WAYS).map(i=>
// (0 until ICACHE_BANKS_WAY).map(j=>
// repl(data_mem_word,ic_rw_addr_ff(ICACHE_BANK_HI, ICACHE_BANK_LO)===j.U)&wb_dout(i)(j)).reduce(_|_))
//
// val wb_dout_way_pre_upper = (0 until ICACHE_NUM_WAYS).map(i=>
// (0 until ICACHE_BANKS_WAY).map(j=>
// repl(data_mem_word,ic_rw_addr_ff(ICACHE_BANK_HI, ICACHE_BANK_LO)===j.U-1.U)&wb_dout(i)(j)).reduce(_|_))
//
// val wb_dout_way_pre = (0 until ICACHE_NUM_WAYS).map(i=>Cat(wb_dout_way_pre_upper(i),wb_dout_way_pre_lower(i)))
//
// // TODO: Put an assertion here
// val wb_dout_way = (0 until ICACHE_NUM_WAYS).map(i=>
// repl(64 ,ic_rw_addr_ff(2,1)===0.U) & wb_dout_way_pre(i)(63,0) |
// repl(64 ,ic_rw_addr_ff(2,1)===1.U) & Cat(wb_dout_way_pre(i)(ecc_offset+15,ecc_offset),wb_dout_way_pre(i)(63,16)) |
// repl(64 ,ic_rw_addr_ff(2,1)===2.U) & Cat(wb_dout_way_pre(i)(ecc_offset+31,ecc_offset),wb_dout_way_pre(i)(63,32)) |
// repl(64 ,ic_rw_addr_ff(2,1)===3.U) & Cat(wb_dout_way_pre(i)(ecc_offset+47,ecc_offset),wb_dout_way_pre(i)(63,48))
// )
// // ic_rw_addr_ff(ICACHE_BANK_HI,ICACHE_BANK_LO)===1.U -> wb_dout(1)(0)))
// val ic_rd_hit_q = Mux(ic_debug_rd_en_ff===1.U, ic_debug_rd_way_en_ff, io.ic_rd_hit) ;
// val wb_dout_way_with_premux = wb_dout_way.map(Mux(io.ic_sel_premux_data, io.ic_premux_data, _))
//
// io.ic_debug_rd_data := 0.U
// io.ic_parerr := 0.U
// io.ic_eccerr := 0.U
//
// io.ic_rd_data := Mux1H_LM((0 until ICACHE_NUM_WAYS).map(i => ic_rd_hit_q(i) | io.ic_sel_premux_data),
// (0 until ICACHE_NUM_WAYS).map(wb_dout_way_with_premux(_)))
// io.ic_debug_rd_data := Mux1H_LM((0 until ICACHE_NUM_WAYS).map(i => ic_rd_hit_q(i)),
// (0 until ICACHE_NUM_WAYS).map(wb_dout_way_pre(_)(data_mem_word-1,0)))
// val wb_dout_ecc = Mux1H_LM((0 until ICACHE_NUM_WAYS).map(i => ic_rd_hit_q(i)),
// (0 until ICACHE_NUM_WAYS).map(wb_dout_way_pre(_)))
// io.test_port2 := 0.U//inter2//wb_dout_way_pre
// io.test_port := wb_dout
} }
object ifu_ic extends App { object ifu_ic extends App {

11
src/main/scala/ifu/el2_ifu_ifc_ctrl.scala
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@ -5,9 +5,7 @@ import chisel3.util._
class el2_ifu_ifc_ctrl extends Module with el2_lib { class el2_ifu_ifc_ctrl extends Module with el2_lib {
val io = IO(new Bundle{ val io = IO(new Bundle{
val free_clk = Input(Bool())
val active_clk = Input(Bool()) val active_clk = Input(Bool())
val rst_l = Input(Bool())
val scan_mode = Input(Bool()) val scan_mode = Input(Bool())
val ic_hit_f = Input(Bool()) val ic_hit_f = Input(Bool())
val ifu_ic_mb_empty = Input(Bool()) val ifu_ic_mb_empty = Input(Bool())
@ -34,12 +32,8 @@ val io = IO(new Bundle{
val ifc_iccm_access_bf = Output(Bool()) val ifc_iccm_access_bf = Output(Bool())
val ifc_region_acc_fault_bf = Output(Bool()) val ifc_region_acc_fault_bf = Output(Bool())
val ifc_dma_access_ok = Output(Bool()) val ifc_dma_access_ok = Output(Bool())
val mb_empty_mod = Output(Bool())
val miss_f = Output(Bool())
}) })
io.ifc_region_acc_fault_bf := 0.U
io.ifc_dma_access_ok := 0.U
val fetch_addr_bf = WireInit(UInt(32.W), init = 0.U) val fetch_addr_bf = WireInit(UInt(32.W), init = 0.U)
val fetch_addr_next = WireInit(UInt(32.W), init = 0.U) val fetch_addr_next = WireInit(UInt(32.W), init = 0.U)
val fb_write_ns = WireInit(UInt(4.W), init = 0.U) val fb_write_ns = WireInit(UInt(4.W), init = 0.U)
@ -93,9 +87,9 @@ val io = IO(new Bundle{
fetch_bf_en := io.exu_flush_final | io.ifc_fetch_req_f fetch_bf_en := io.exu_flush_final | io.ifc_fetch_req_f
miss_f := io.ifc_fetch_req_f & !io.ic_hit_f & !io.exu_flush_final miss_f := io.ifc_fetch_req_f & !io.ic_hit_f & !io.exu_flush_final
io.miss_f := miss_f
mb_empty_mod := (io.ifu_ic_mb_empty | io.exu_flush_final) & !dma_stall & !miss_f & !miss_a mb_empty_mod := (io.ifu_ic_mb_empty | io.exu_flush_final) & !dma_stall & !miss_f & !miss_a
io.mb_empty_mod := mb_empty_mod
goto_idle := io.exu_flush_final & io.dec_tlu_flush_noredir_wb goto_idle := io.exu_flush_final & io.dec_tlu_flush_noredir_wb
leave_idle := io.exu_flush_final & !io.dec_tlu_flush_noredir_wb & idle leave_idle := io.exu_flush_final & !io.dec_tlu_flush_noredir_wb & idle
@ -142,6 +136,7 @@ val io = IO(new Bundle{
(fb_full_f & !(io.ifu_fb_consume2 | io.ifu_fb_consume1)) | (fb_full_f & !(io.ifu_fb_consume2 | io.ifu_fb_consume1)) |
(wfm & !io.ifc_fetch_req_bf) | idle ) & !io.exu_flush_final) | dma_iccm_stall_any_f (wfm & !io.ifc_fetch_req_bf) | idle ) & !io.exu_flush_final) | dma_iccm_stall_any_f
io.ifc_region_acc_fault_bf := ~iccm_acc_in_range_bf & iccm_acc_in_region_bf
io.ifc_fetch_uncacheable_bf := ~io.dec_tlu_mrac_ff(Cat(io.ifc_fetch_addr_bf(30,27), 0.U)) io.ifc_fetch_uncacheable_bf := ~io.dec_tlu_mrac_ff(Cat(io.ifc_fetch_addr_bf(30,27), 0.U))
io.ifc_fetch_req_f := RegNext(io.ifc_fetch_req_bf, init=0.U) io.ifc_fetch_req_f := RegNext(io.ifc_fetch_req_bf, init=0.U)

51
src/main/scala/lib/el2_lib.scala
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@ -33,14 +33,14 @@ trait param {
val DATA_ACCESS_ADDR5 = 0x00000000 //.U(32.W) val DATA_ACCESS_ADDR5 = 0x00000000 //.U(32.W)
val DATA_ACCESS_ADDR6 = 0x00000000 //.U(32.W) val DATA_ACCESS_ADDR6 = 0x00000000 //.U(32.W)
val DATA_ACCESS_ADDR7 = 0x00000000 //.U(32.W) val DATA_ACCESS_ADDR7 = 0x00000000 //.U(32.W)
val DATA_ACCESS_ENABLE0 = 0x1 //.U(1.W) val DATA_ACCESS_ENABLE0 = true //.U(1.W)
val DATA_ACCESS_ENABLE1 = 0x1 //.U(1.W) val DATA_ACCESS_ENABLE1 = true //.U(1.W)
val DATA_ACCESS_ENABLE2 = 0x1 //.U(1.W) val DATA_ACCESS_ENABLE2 = true //.U(1.W)
val DATA_ACCESS_ENABLE3 = 0x1 //.U(1.W) val DATA_ACCESS_ENABLE3 = true //.U(1.W)
val DATA_ACCESS_ENABLE4 = 0x0 //.U(1.W) val DATA_ACCESS_ENABLE4 = false //.U(1.W)
val DATA_ACCESS_ENABLE5 = 0x0 //.U(1.W) val DATA_ACCESS_ENABLE5 = false //.U(1.W)
val DATA_ACCESS_ENABLE6 = 0x0 //.U(1.W) val DATA_ACCESS_ENABLE6 = false //.U(1.W)
val DATA_ACCESS_ENABLE7 = 0x0 //.U(1.W) val DATA_ACCESS_ENABLE7 = false //.U(1.W)
val DATA_ACCESS_MASK0 = 0x7FFFFFFF //.U(32.W) val DATA_ACCESS_MASK0 = 0x7FFFFFFF //.U(32.W)
val DATA_ACCESS_MASK1 = 0x3FFFFFFF //.U(32.W) val DATA_ACCESS_MASK1 = 0x3FFFFFFF //.U(32.W)
val DATA_ACCESS_MASK2 = 0x1FFFFFFF //.U(32.W) val DATA_ACCESS_MASK2 = 0x1FFFFFFF //.U(32.W)
@ -49,21 +49,21 @@ trait param {
val DATA_ACCESS_MASK5 = 0xFFFFFFFF //.U(32.W) val DATA_ACCESS_MASK5 = 0xFFFFFFFF //.U(32.W)
val DATA_ACCESS_MASK6 = 0xFFFFFFFF //.U(32.W) val DATA_ACCESS_MASK6 = 0xFFFFFFFF //.U(32.W)
val DATA_ACCESS_MASK7 = 0xFFFFFFFF //.U(32.W) val DATA_ACCESS_MASK7 = 0xFFFFFFFF //.U(32.W)
val DCCM_BANK_BITS = 0x2 //.U(3.W) val DCCM_BANK_BITS = 2 //.U(3.W)
val DCCM_BITS = 0x10 //.U(5.W) val DCCM_BITS = 16 //.U(5.W)
val DCCM_BYTE_WIDTH = 0x4 //.U(3.W) val DCCM_BYTE_WIDTH = 4 //.U(3.W)
val DCCM_DATA_WIDTH = 0x20 //.U(6.W) val DCCM_DATA_WIDTH = 32 //.U(6.W)
val DCCM_ECC_WIDTH = 0x7 //.U(3.W) val DCCM_ECC_WIDTH = 7 //.U(3.W)
val DCCM_ENABLE = 0x1 //.U(1.W) val DCCM_ENABLE = true //.U(1.W)
val DCCM_FDATA_WIDTH = 0x27 //.U(6.W) val DCCM_FDATA_WIDTH = 0x27 //.U(6.W)
val DCCM_INDEX_BITS = 0xC //.U(4.W) val DCCM_INDEX_BITS = 0xC //.U(4.W)
val DCCM_NUM_BANKS = 0x04 //.U(5.W) val DCCM_NUM_BANKS = 0x04 //.U(5.W)
val DCCM_REGION = 0xF //.U(4.W) val DCCM_REGION = 15 //.U(4.W)
val DCCM_SADR = 0xF0040000 val DCCM_SADR = 0xF0040000
val DCCM_SIZE = 0x040 val DCCM_SIZE = 0x040
val DCCM_WIDTH_BITS = 0x2 //.U(2.W) val DCCM_WIDTH_BITS = 2 //.U(2.W)
val DMA_BUF_DEPTH = 0x5 //.U(3.W) val DMA_BUF_DEPTH = 5 //.U(3.W)
val DMA_BUS_ID = 0x1 //.U(1.W) val DMA_BUS_ID = true //.U(1.W)
val DMA_BUS_PRTY = 0x2 //.U(2.W) val DMA_BUS_PRTY = 0x2 //.U(2.W)
val DMA_BUS_TAG = 0x1 //.U(4.W) val DMA_BUS_TAG = 0x1 //.U(4.W)
val FAST_INTERRUPT_REDIRECT= 0x1 //.U(1.W) val FAST_INTERRUPT_REDIRECT= 0x1 //.U(1.W)
@ -94,11 +94,11 @@ trait param {
val ICACHE_TAG_LO = 13 val ICACHE_TAG_LO = 13
val ICACHE_WAYPACK = false val ICACHE_WAYPACK = false
val ICCM_BANK_BITS = 2 val ICCM_BANK_BITS = 2
val ICCM_BANK_HI = 0x03 //.U(5.W) val ICCM_BANK_HI = 3 //.U(5.W)
val ICCM_BANK_INDEX_LO = 0x04 //.U(5.W) val ICCM_BANK_INDEX_LO = 4 //.U(5.W)
val ICCM_BITS = 0x10 //.U(5.W) val ICCM_BITS = 16 //.U(5.W)
val ICCM_ENABLE = true //.U(1.W) val ICCM_ENABLE = true //.U(1.W)
val ICCM_ICACHE = 0x1 //.U(1.W) val ICCM_ICACHE = true //.U(1.W)
val ICCM_INDEX_BITS = 0xC //.U(4.W) val ICCM_INDEX_BITS = 0xC //.U(4.W)
val ICCM_NUM_BANKS = 0x04 //.U(5.W) val ICCM_NUM_BANKS = 0x04 //.U(5.W)
val ICCM_ONLY = 0x0 //.U(1.W) val ICCM_ONLY = 0x0 //.U(1.W)
@ -155,7 +155,9 @@ trait param {
val SB_BUS_PRTY = 0x2 //.U(2.W) val SB_BUS_PRTY = 0x2 //.U(2.W)
val SB_BUS_TAG = 0x1 //.U(4.W) val SB_BUS_TAG = 0x1 //.U(4.W)
val TIMER_LEGAL_EN = 0x1 //.U(1.W) val TIMER_LEGAL_EN = 0x1 //.U(1.W)
}
trait el2_lib extends param{
// Configuration Methods // Configuration Methods
def MEM_CAL : (Int, Int, Int)= def MEM_CAL : (Int, Int, Int)=
(ICACHE_WAYPACK, ICACHE_ECC) match{ (ICACHE_WAYPACK, ICACHE_ECC) match{
@ -164,13 +166,8 @@ trait param {
case(true,false) => (68*ICACHE_NUM_WAYS,22*ICACHE_NUM_WAYS, 68) case(true,false) => (68*ICACHE_NUM_WAYS,22*ICACHE_NUM_WAYS, 68)
case(true,true) => (71*ICACHE_NUM_WAYS,26*ICACHE_NUM_WAYS, 71) case(true,true) => (71*ICACHE_NUM_WAYS,26*ICACHE_NUM_WAYS, 71)
} }
val DATA_MEM_LINE = MEM_CAL val DATA_MEM_LINE = MEM_CAL
}
trait el2_lib extends param{
def el2_btb_tag_hash(pc : UInt) = def el2_btb_tag_hash(pc : UInt) =
VecInit.tabulate(3)(i => pc(BTB_ADDR_HI+((i+1)*(BTB_BTAG_SIZE)),BTB_ADDR_HI+(i*BTB_BTAG_SIZE)+1)).reduce(_^_) VecInit.tabulate(3)(i => pc(BTB_ADDR_HI+((i+1)*(BTB_BTAG_SIZE)),BTB_ADDR_HI+(i*BTB_BTAG_SIZE)+1)).reduce(_^_)

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