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​Laraib Khan 2021-01-27 13:04:31 +05:00
parent f23f878f60
commit b9cdbac350
53 changed files with 1 additions and 593637 deletions
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34
ahb_to_axi4.anno.json
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@ -1,34 +0,0 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~ahb_to_axi4|ahb_to_axi4>io_ahb_sig_in_hready",
"sources":[
"~ahb_to_axi4|ahb_to_axi4>io_ahb_sig_in_hresp",
"~ahb_to_axi4|ahb_to_axi4>io_axi_aw_valid",
"~ahb_to_axi4|ahb_to_axi4>io_axi_aw_ready",
"~ahb_to_axi4|ahb_to_axi4>io_axi_ar_valid",
"~ahb_to_axi4|ahb_to_axi4>io_axi_ar_ready"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"ahb_to_axi4.gated_latch",
"resourceId":"/vsrc/gated_latch.sv"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"ahb_to_axi4"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

469
ahb_to_axi4.fir
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@ -1,469 +0,0 @@
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
circuit ahb_to_axi4 :
extmodule gated_latch :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch @[lib.scala 334:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
clkhdr.CK <= io.clk @[lib.scala 336:18]
clkhdr.EN <= io.en @[lib.scala 337:18]
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
extmodule gated_latch_1 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_1 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_1 @[lib.scala 334:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
clkhdr.CK <= io.clk @[lib.scala 336:18]
clkhdr.EN <= io.en @[lib.scala 337:18]
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
module ahb_to_axi4 :
input clock : Clock
input reset : AsyncReset
output io : {flip scan_mode : UInt<1>, flip bus_clk_en : UInt<1>, flip clk_override : UInt<1>, axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, ahb : {flip sig : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, flip hsel : UInt<1>, flip hreadyin : UInt<1>}}
wire _T : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[ahb_to_axi4.scala 20:25]
_T.r.bits.last <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25]
_T.r.bits.resp <= UInt<2>("h00") @[ahb_to_axi4.scala 20:25]
_T.r.bits.data <= UInt<64>("h00") @[ahb_to_axi4.scala 20:25]
_T.r.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25]
_T.r.valid <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25]
_T.r.ready <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25]
_T.ar.bits.qos <= UInt<4>("h00") @[ahb_to_axi4.scala 20:25]
_T.ar.bits.prot <= UInt<3>("h00") @[ahb_to_axi4.scala 20:25]
_T.ar.bits.cache <= UInt<4>("h00") @[ahb_to_axi4.scala 20:25]
_T.ar.bits.lock <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25]
_T.ar.bits.burst <= UInt<2>("h00") @[ahb_to_axi4.scala 20:25]
_T.ar.bits.size <= UInt<3>("h00") @[ahb_to_axi4.scala 20:25]
_T.ar.bits.len <= UInt<8>("h00") @[ahb_to_axi4.scala 20:25]
_T.ar.bits.region <= UInt<4>("h00") @[ahb_to_axi4.scala 20:25]
_T.ar.bits.addr <= UInt<32>("h00") @[ahb_to_axi4.scala 20:25]
_T.ar.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25]
_T.ar.valid <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25]
_T.ar.ready <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25]
_T.b.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25]
_T.b.bits.resp <= UInt<2>("h00") @[ahb_to_axi4.scala 20:25]
_T.b.valid <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25]
_T.b.ready <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25]
_T.w.bits.last <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25]
_T.w.bits.strb <= UInt<8>("h00") @[ahb_to_axi4.scala 20:25]
_T.w.bits.data <= UInt<64>("h00") @[ahb_to_axi4.scala 20:25]
_T.w.valid <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25]
_T.w.ready <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25]
_T.aw.bits.qos <= UInt<4>("h00") @[ahb_to_axi4.scala 20:25]
_T.aw.bits.prot <= UInt<3>("h00") @[ahb_to_axi4.scala 20:25]
_T.aw.bits.cache <= UInt<4>("h00") @[ahb_to_axi4.scala 20:25]
_T.aw.bits.lock <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25]
_T.aw.bits.burst <= UInt<2>("h00") @[ahb_to_axi4.scala 20:25]
_T.aw.bits.size <= UInt<3>("h00") @[ahb_to_axi4.scala 20:25]
_T.aw.bits.len <= UInt<8>("h00") @[ahb_to_axi4.scala 20:25]
_T.aw.bits.region <= UInt<4>("h00") @[ahb_to_axi4.scala 20:25]
_T.aw.bits.addr <= UInt<32>("h00") @[ahb_to_axi4.scala 20:25]
_T.aw.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25]
_T.aw.valid <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25]
_T.aw.ready <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25]
_T.r.bits.last <= io.axi.r.bits.last @[ahb_to_axi4.scala 20:10]
_T.r.bits.resp <= io.axi.r.bits.resp @[ahb_to_axi4.scala 20:10]
_T.r.bits.data <= io.axi.r.bits.data @[ahb_to_axi4.scala 20:10]
_T.r.bits.id <= io.axi.r.bits.id @[ahb_to_axi4.scala 20:10]
_T.r.valid <= io.axi.r.valid @[ahb_to_axi4.scala 20:10]
io.axi.r.ready <= _T.r.ready @[ahb_to_axi4.scala 20:10]
io.axi.ar.bits.qos <= _T.ar.bits.qos @[ahb_to_axi4.scala 20:10]
io.axi.ar.bits.prot <= _T.ar.bits.prot @[ahb_to_axi4.scala 20:10]
io.axi.ar.bits.cache <= _T.ar.bits.cache @[ahb_to_axi4.scala 20:10]
io.axi.ar.bits.lock <= _T.ar.bits.lock @[ahb_to_axi4.scala 20:10]
io.axi.ar.bits.burst <= _T.ar.bits.burst @[ahb_to_axi4.scala 20:10]
io.axi.ar.bits.size <= _T.ar.bits.size @[ahb_to_axi4.scala 20:10]
io.axi.ar.bits.len <= _T.ar.bits.len @[ahb_to_axi4.scala 20:10]
io.axi.ar.bits.region <= _T.ar.bits.region @[ahb_to_axi4.scala 20:10]
io.axi.ar.bits.addr <= _T.ar.bits.addr @[ahb_to_axi4.scala 20:10]
io.axi.ar.bits.id <= _T.ar.bits.id @[ahb_to_axi4.scala 20:10]
io.axi.ar.valid <= _T.ar.valid @[ahb_to_axi4.scala 20:10]
_T.ar.ready <= io.axi.ar.ready @[ahb_to_axi4.scala 20:10]
_T.b.bits.id <= io.axi.b.bits.id @[ahb_to_axi4.scala 20:10]
_T.b.bits.resp <= io.axi.b.bits.resp @[ahb_to_axi4.scala 20:10]
_T.b.valid <= io.axi.b.valid @[ahb_to_axi4.scala 20:10]
io.axi.b.ready <= _T.b.ready @[ahb_to_axi4.scala 20:10]
io.axi.w.bits.last <= _T.w.bits.last @[ahb_to_axi4.scala 20:10]
io.axi.w.bits.strb <= _T.w.bits.strb @[ahb_to_axi4.scala 20:10]
io.axi.w.bits.data <= _T.w.bits.data @[ahb_to_axi4.scala 20:10]
io.axi.w.valid <= _T.w.valid @[ahb_to_axi4.scala 20:10]
_T.w.ready <= io.axi.w.ready @[ahb_to_axi4.scala 20:10]
io.axi.aw.bits.qos <= _T.aw.bits.qos @[ahb_to_axi4.scala 20:10]
io.axi.aw.bits.prot <= _T.aw.bits.prot @[ahb_to_axi4.scala 20:10]
io.axi.aw.bits.cache <= _T.aw.bits.cache @[ahb_to_axi4.scala 20:10]
io.axi.aw.bits.lock <= _T.aw.bits.lock @[ahb_to_axi4.scala 20:10]
io.axi.aw.bits.burst <= _T.aw.bits.burst @[ahb_to_axi4.scala 20:10]
io.axi.aw.bits.size <= _T.aw.bits.size @[ahb_to_axi4.scala 20:10]
io.axi.aw.bits.len <= _T.aw.bits.len @[ahb_to_axi4.scala 20:10]
io.axi.aw.bits.region <= _T.aw.bits.region @[ahb_to_axi4.scala 20:10]
io.axi.aw.bits.addr <= _T.aw.bits.addr @[ahb_to_axi4.scala 20:10]
io.axi.aw.bits.id <= _T.aw.bits.id @[ahb_to_axi4.scala 20:10]
io.axi.aw.valid <= _T.aw.valid @[ahb_to_axi4.scala 20:10]
_T.aw.ready <= io.axi.aw.ready @[ahb_to_axi4.scala 20:10]
wire master_wstrb : UInt<8>
master_wstrb <= UInt<8>("h00")
wire buf_state_en : UInt<1>
buf_state_en <= UInt<1>("h00")
wire buf_read_error_in : UInt<1>
buf_read_error_in <= UInt<1>("h00")
node ahb_hready = and(io.ahb.sig.in.hready, io.ahb.hreadyin) @[ahb_to_axi4.scala 27:50]
node _T_1 = bits(io.ahb.hsel, 0, 0) @[Bitwise.scala 72:15]
node _T_2 = mux(_T_1, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
node _T_3 = bits(io.ahb.sig.out.htrans, 1, 0) @[ahb_to_axi4.scala 28:72]
node ahb_htrans_in = and(_T_2, _T_3) @[ahb_to_axi4.scala 28:49]
wire ahb_hwdata_q : UInt<64>
ahb_hwdata_q <= UInt<64>("h00")
wire buf_rdata_en : UInt<1>
buf_rdata_en <= UInt<1>("h00")
wire bus_clk : Clock @[ahb_to_axi4.scala 33:33]
wire ahb_addr_clk : Clock @[ahb_to_axi4.scala 34:33]
wire buf_rdata_clk : Clock @[ahb_to_axi4.scala 35:33]
node _T_4 = bits(io.ahb.sig.out.htrans, 1, 1) @[ahb_to_axi4.scala 36:80]
node _T_5 = and(ahb_hready, _T_4) @[ahb_to_axi4.scala 36:57]
node ahb_addr_clk_en = and(io.bus_clk_en, _T_5) @[ahb_to_axi4.scala 36:43]
node buf_rdata_clk_en = and(io.bus_clk_en, buf_rdata_en) @[ahb_to_axi4.scala 37:43]
node _T_6 = asClock(UInt<1>("h00")) @[ahb_to_axi4.scala 40:33]
bus_clk <= _T_6 @[ahb_to_axi4.scala 40:19]
node _T_7 = asClock(UInt<1>("h00")) @[ahb_to_axi4.scala 41:33]
ahb_addr_clk <= _T_7 @[ahb_to_axi4.scala 41:19]
node _T_8 = asClock(UInt<1>("h00")) @[ahb_to_axi4.scala 42:33]
buf_rdata_clk <= _T_8 @[ahb_to_axi4.scala 42:19]
reg buf_read_error : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when io.bus_clk_en : @[Reg.scala 28:19]
buf_read_error <= buf_read_error_in @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
reg buf_rdata : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when buf_rdata_clk_en : @[Reg.scala 28:19]
buf_rdata <= io.axi.r.bits.data @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
reg ahb_hresp_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when io.bus_clk_en : @[Reg.scala 28:19]
ahb_hresp_q <= io.ahb.sig.in.hresp @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
reg ahb_hsize_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when ahb_addr_clk_en : @[Reg.scala 28:19]
ahb_hsize_q <= io.ahb.sig.out.hsize @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
reg ahb_hwrite_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when ahb_addr_clk_en : @[Reg.scala 28:19]
ahb_hwrite_q <= io.ahb.sig.out.hwrite @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
reg ahb_haddr_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when ahb_addr_clk_en : @[Reg.scala 28:19]
ahb_haddr_q <= io.ahb.sig.out.haddr @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
reg ahb_hready_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when io.bus_clk_en : @[Reg.scala 28:19]
ahb_hready_q <= ahb_hready @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
reg ahb_htrans_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when io.bus_clk_en : @[Reg.scala 28:19]
ahb_htrans_q <= ahb_htrans_in @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
wire cmdbuf_wr_en : UInt<1>
cmdbuf_wr_en <= UInt<1>("h00")
node _T_9 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 60:70]
node _T_10 = and(io.bus_clk_en, _T_9) @[lib.scala 383:57]
reg cmdbuf_write : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_10 : @[Reg.scala 28:19]
cmdbuf_write <= ahb_hwrite_q @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
node _T_11 = and(io.axi.aw.valid, io.axi.aw.ready) @[ahb_to_axi4.scala 61:44]
node _T_12 = and(io.axi.ar.valid, io.axi.ar.ready) @[ahb_to_axi4.scala 61:82]
node _T_13 = or(_T_11, _T_12) @[ahb_to_axi4.scala 61:63]
node _T_14 = eq(cmdbuf_wr_en, UInt<1>("h00")) @[ahb_to_axi4.scala 61:104]
node _T_15 = and(_T_13, _T_14) @[ahb_to_axi4.scala 61:102]
node _T_16 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 61:144]
node _T_17 = and(io.ahb.sig.in.hresp, _T_16) @[ahb_to_axi4.scala 61:142]
node cmdbuf_rst = or(_T_15, _T_17) @[ahb_to_axi4.scala 61:119]
node _T_18 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 62:64]
wire cmdbuf_vld : UInt @[lib.scala 389:21]
node _T_19 = eq(cmdbuf_rst, UInt<1>("h00")) @[lib.scala 391:73]
node _T_20 = and(UInt<1>("h01"), _T_19) @[lib.scala 391:53]
node _T_21 = or(_T_18, cmdbuf_rst) @[lib.scala 391:92]
node _T_22 = and(_T_21, io.bus_clk_en) @[lib.scala 391:99]
node _T_23 = bits(_T_22, 0, 0) @[lib.scala 8:44]
reg _T_24 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_23 : @[Reg.scala 28:19]
_T_24 <= _T_20 @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
cmdbuf_vld <= _T_24 @[lib.scala 391:14]
node _T_25 = and(io.axi.aw.valid, io.axi.aw.ready) @[ahb_to_axi4.scala 63:58]
node _T_26 = and(io.axi.ar.valid, io.axi.ar.ready) @[ahb_to_axi4.scala 63:96]
node _T_27 = or(_T_25, _T_26) @[ahb_to_axi4.scala 63:77]
node _T_28 = eq(_T_27, UInt<1>("h00")) @[ahb_to_axi4.scala 63:39]
node cmdbuf_full = and(cmdbuf_vld, _T_28) @[ahb_to_axi4.scala 63:37]
node _T_29 = bits(ahb_hsize_q, 1, 0) @[ahb_to_axi4.scala 64:48]
node _T_30 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 64:74]
node _T_31 = and(io.bus_clk_en, _T_30) @[lib.scala 383:57]
reg cmdbuf_size : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_31 : @[Reg.scala 28:19]
cmdbuf_size <= _T_29 @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
node _T_32 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 65:70]
node _T_33 = and(io.bus_clk_en, _T_32) @[lib.scala 383:57]
reg cmdbuf_wstrb : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_33 : @[Reg.scala 28:19]
cmdbuf_wstrb <= master_wstrb @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
node _T_34 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 66:64]
node _T_35 = and(_T_34, io.bus_clk_en) @[ahb_to_axi4.scala 66:66]
inst rvclkhdr of rvclkhdr @[lib.scala 399:23]
rvclkhdr.clock <= clock
rvclkhdr.reset <= reset
rvclkhdr.io.clk <= clock @[lib.scala 401:18]
rvclkhdr.io.en <= _T_35 @[lib.scala 402:17]
rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24]
reg cmdbuf_addr : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_35 : @[Reg.scala 28:19]
cmdbuf_addr <= ahb_haddr_q @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
node _T_36 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 67:74]
node _T_37 = and(_T_36, io.bus_clk_en) @[ahb_to_axi4.scala 67:76]
inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 399:23]
rvclkhdr_1.clock <= clock
rvclkhdr_1.reset <= reset
rvclkhdr_1.io.clk <= clock @[lib.scala 401:18]
rvclkhdr_1.io.en <= _T_37 @[lib.scala 402:17]
rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24]
reg cmdbuf_wdata : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_37 : @[Reg.scala 28:19]
cmdbuf_wdata <= io.ahb.sig.out.hwdata @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
node _T_38 = bits(ahb_haddr_q, 31, 28) @[lib.scala 84:25]
node ahb_addr_in_dccm_region_nc = eq(_T_38, UInt<4>("h0f")) @[lib.scala 84:47]
node _T_39 = bits(ahb_haddr_q, 31, 16) @[lib.scala 87:14]
node ahb_addr_in_dccm = eq(_T_39, UInt<16>("h0f004")) @[lib.scala 87:29]
node _T_40 = bits(ahb_haddr_q, 31, 28) @[lib.scala 84:25]
node ahb_addr_in_iccm_region_nc = eq(_T_40, UInt<4>("h0e")) @[lib.scala 84:47]
node _T_41 = bits(ahb_haddr_q, 31, 16) @[lib.scala 87:14]
node ahb_addr_in_iccm = eq(_T_41, UInt<16>("h0ee00")) @[lib.scala 87:29]
node _T_42 = bits(ahb_haddr_q, 31, 28) @[lib.scala 84:25]
node ahb_addr_in_pic_region_nc = eq(_T_42, UInt<4>("h0f")) @[lib.scala 84:47]
node _T_43 = bits(ahb_haddr_q, 31, 15) @[lib.scala 87:14]
node ahb_addr_in_pic = eq(_T_43, UInt<17>("h01e018")) @[lib.scala 87:29]
wire buf_state : UInt<2>
buf_state <= UInt<2>("h00")
wire buf_nxtstate : UInt<2>
buf_nxtstate <= UInt<2>("h00")
buf_nxtstate <= UInt<2>("h00") @[ahb_to_axi4.scala 76:31]
buf_state_en <= UInt<1>("h00") @[ahb_to_axi4.scala 77:31]
buf_rdata_en <= UInt<1>("h00") @[ahb_to_axi4.scala 78:31]
buf_read_error_in <= UInt<1>("h00") @[ahb_to_axi4.scala 79:31]
cmdbuf_wr_en <= UInt<1>("h00") @[ahb_to_axi4.scala 80:31]
node _T_44 = eq(UInt<2>("h00"), buf_state) @[Conditional.scala 37:30]
when _T_44 : @[Conditional.scala 40:58]
node _T_45 = mux(io.ahb.sig.out.hwrite, UInt<2>("h01"), UInt<2>("h02")) @[ahb_to_axi4.scala 84:26]
buf_nxtstate <= _T_45 @[ahb_to_axi4.scala 84:20]
node _T_46 = bits(io.ahb.sig.out.htrans, 1, 1) @[ahb_to_axi4.scala 85:57]
node _T_47 = and(ahb_hready, _T_46) @[ahb_to_axi4.scala 85:34]
node _T_48 = and(_T_47, io.ahb.hsel) @[ahb_to_axi4.scala 85:61]
buf_state_en <= _T_48 @[ahb_to_axi4.scala 85:20]
skip @[Conditional.scala 40:58]
else : @[Conditional.scala 39:67]
node _T_49 = eq(UInt<2>("h01"), buf_state) @[Conditional.scala 37:30]
when _T_49 : @[Conditional.scala 39:67]
node _T_50 = bits(io.ahb.sig.out.htrans, 1, 0) @[ahb_to_axi4.scala 88:72]
node _T_51 = eq(_T_50, UInt<1>("h00")) @[ahb_to_axi4.scala 88:79]
node _T_52 = or(io.ahb.sig.in.hresp, _T_51) @[ahb_to_axi4.scala 88:48]
node _T_53 = eq(io.ahb.hsel, UInt<1>("h00")) @[ahb_to_axi4.scala 88:93]
node _T_54 = or(_T_52, _T_53) @[ahb_to_axi4.scala 88:91]
node _T_55 = bits(_T_54, 0, 0) @[ahb_to_axi4.scala 88:107]
node _T_56 = mux(io.ahb.sig.out.hwrite, UInt<2>("h01"), UInt<2>("h02")) @[ahb_to_axi4.scala 88:124]
node _T_57 = mux(_T_55, UInt<2>("h00"), _T_56) @[ahb_to_axi4.scala 88:26]
buf_nxtstate <= _T_57 @[ahb_to_axi4.scala 88:20]
node _T_58 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 89:24]
node _T_59 = or(_T_58, io.ahb.sig.in.hresp) @[ahb_to_axi4.scala 89:37]
buf_state_en <= _T_59 @[ahb_to_axi4.scala 89:20]
node _T_60 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 90:23]
node _T_61 = bits(io.ahb.sig.out.htrans, 1, 0) @[ahb_to_axi4.scala 90:85]
node _T_62 = eq(_T_61, UInt<2>("h01")) @[ahb_to_axi4.scala 90:92]
node _T_63 = and(_T_62, io.ahb.hsel) @[ahb_to_axi4.scala 90:110]
node _T_64 = or(io.ahb.sig.in.hresp, _T_63) @[ahb_to_axi4.scala 90:60]
node _T_65 = eq(_T_64, UInt<1>("h00")) @[ahb_to_axi4.scala 90:38]
node _T_66 = and(_T_60, _T_65) @[ahb_to_axi4.scala 90:36]
cmdbuf_wr_en <= _T_66 @[ahb_to_axi4.scala 90:20]
skip @[Conditional.scala 39:67]
else : @[Conditional.scala 39:67]
node _T_67 = eq(UInt<2>("h02"), buf_state) @[Conditional.scala 37:30]
when _T_67 : @[Conditional.scala 39:67]
node _T_68 = mux(io.ahb.sig.in.hresp, UInt<2>("h00"), UInt<2>("h03")) @[ahb_to_axi4.scala 93:26]
buf_nxtstate <= _T_68 @[ahb_to_axi4.scala 93:20]
node _T_69 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 94:24]
node _T_70 = or(_T_69, io.ahb.sig.in.hresp) @[ahb_to_axi4.scala 94:37]
buf_state_en <= _T_70 @[ahb_to_axi4.scala 94:20]
node _T_71 = eq(io.ahb.sig.in.hresp, UInt<1>("h00")) @[ahb_to_axi4.scala 95:23]
node _T_72 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 95:46]
node _T_73 = and(_T_71, _T_72) @[ahb_to_axi4.scala 95:44]
cmdbuf_wr_en <= _T_73 @[ahb_to_axi4.scala 95:20]
skip @[Conditional.scala 39:67]
else : @[Conditional.scala 39:67]
node _T_74 = eq(UInt<2>("h03"), buf_state) @[Conditional.scala 37:30]
when _T_74 : @[Conditional.scala 39:67]
buf_nxtstate <= UInt<2>("h00") @[ahb_to_axi4.scala 98:20]
node _T_75 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 99:40]
node _T_76 = and(io.axi.r.valid, _T_75) @[ahb_to_axi4.scala 99:38]
buf_state_en <= _T_76 @[ahb_to_axi4.scala 99:20]
buf_rdata_en <= buf_state_en @[ahb_to_axi4.scala 100:20]
node _T_77 = bits(io.axi.r.bits.resp, 1, 0) @[ahb_to_axi4.scala 101:61]
node _T_78 = orr(_T_77) @[ahb_to_axi4.scala 101:68]
node _T_79 = and(buf_state_en, _T_78) @[ahb_to_axi4.scala 101:41]
buf_read_error_in <= _T_79 @[ahb_to_axi4.scala 101:25]
skip @[Conditional.scala 39:67]
node _T_80 = bits(buf_state_en, 0, 0) @[ahb_to_axi4.scala 104:78]
node _T_81 = and(io.bus_clk_en, _T_80) @[lib.scala 383:57]
reg _T_82 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_81 : @[Reg.scala 28:19]
_T_82 <= buf_nxtstate @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
buf_state <= _T_82 @[ahb_to_axi4.scala 104:31]
node _T_83 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 106:54]
node _T_84 = eq(_T_83, UInt<1>("h00")) @[ahb_to_axi4.scala 106:60]
node _T_85 = bits(_T_84, 0, 0) @[Bitwise.scala 72:15]
node _T_86 = mux(_T_85, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
node _T_87 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 106:92]
node _T_88 = dshl(UInt<1>("h01"), _T_87) @[ahb_to_axi4.scala 106:78]
node _T_89 = and(_T_86, _T_88) @[ahb_to_axi4.scala 106:70]
node _T_90 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 107:24]
node _T_91 = eq(_T_90, UInt<1>("h01")) @[ahb_to_axi4.scala 107:30]
node _T_92 = bits(_T_91, 0, 0) @[Bitwise.scala 72:15]
node _T_93 = mux(_T_92, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
node _T_94 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 107:62]
node _T_95 = dshl(UInt<2>("h03"), _T_94) @[ahb_to_axi4.scala 107:48]
node _T_96 = and(_T_93, _T_95) @[ahb_to_axi4.scala 107:40]
node _T_97 = or(_T_89, _T_96) @[ahb_to_axi4.scala 106:109]
node _T_98 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 108:24]
node _T_99 = eq(_T_98, UInt<2>("h02")) @[ahb_to_axi4.scala 108:30]
node _T_100 = bits(_T_99, 0, 0) @[Bitwise.scala 72:15]
node _T_101 = mux(_T_100, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
node _T_102 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 108:62]
node _T_103 = dshl(UInt<4>("h0f"), _T_102) @[ahb_to_axi4.scala 108:48]
node _T_104 = and(_T_101, _T_103) @[ahb_to_axi4.scala 108:40]
node _T_105 = or(_T_97, _T_104) @[ahb_to_axi4.scala 107:79]
node _T_106 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 109:24]
node _T_107 = eq(_T_106, UInt<2>("h03")) @[ahb_to_axi4.scala 109:30]
node _T_108 = bits(_T_107, 0, 0) @[Bitwise.scala 72:15]
node _T_109 = mux(_T_108, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
node _T_110 = and(_T_109, UInt<8>("h0ff")) @[ahb_to_axi4.scala 109:40]
node _T_111 = or(_T_105, _T_110) @[ahb_to_axi4.scala 108:79]
master_wstrb <= _T_111 @[ahb_to_axi4.scala 106:31]
node _T_112 = eq(ahb_hready_q, UInt<1>("h00")) @[ahb_to_axi4.scala 112:80]
node _T_113 = and(ahb_hresp_q, _T_112) @[ahb_to_axi4.scala 112:78]
node _T_114 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 112:98]
node _T_115 = eq(buf_state, UInt<2>("h00")) @[ahb_to_axi4.scala 112:124]
node _T_116 = or(_T_114, _T_115) @[ahb_to_axi4.scala 112:111]
node _T_117 = eq(buf_state, UInt<2>("h02")) @[ahb_to_axi4.scala 112:149]
node _T_118 = eq(buf_state, UInt<2>("h03")) @[ahb_to_axi4.scala 112:168]
node _T_119 = or(_T_117, _T_118) @[ahb_to_axi4.scala 112:156]
node _T_120 = eq(_T_119, UInt<1>("h00")) @[ahb_to_axi4.scala 112:137]
node _T_121 = and(_T_116, _T_120) @[ahb_to_axi4.scala 112:135]
node _T_122 = eq(buf_read_error, UInt<1>("h00")) @[ahb_to_axi4.scala 112:181]
node _T_123 = and(_T_121, _T_122) @[ahb_to_axi4.scala 112:179]
node _T_124 = mux(io.ahb.sig.in.hresp, _T_113, _T_123) @[ahb_to_axi4.scala 112:44]
io.ahb.sig.in.hready <= _T_124 @[ahb_to_axi4.scala 112:38]
node _T_125 = bits(buf_rdata, 63, 0) @[ahb_to_axi4.scala 113:50]
io.ahb.sig.in.hrdata <= _T_125 @[ahb_to_axi4.scala 113:38]
node _T_126 = bits(ahb_htrans_q, 1, 0) @[ahb_to_axi4.scala 114:55]
node _T_127 = neq(_T_126, UInt<1>("h00")) @[ahb_to_axi4.scala 114:61]
node _T_128 = neq(buf_state, UInt<2>("h00")) @[ahb_to_axi4.scala 114:83]
node _T_129 = and(_T_127, _T_128) @[ahb_to_axi4.scala 114:70]
node _T_130 = or(ahb_addr_in_dccm, ahb_addr_in_iccm) @[ahb_to_axi4.scala 115:26]
node _T_131 = eq(_T_130, UInt<1>("h00")) @[ahb_to_axi4.scala 115:7]
node _T_132 = and(ahb_addr_in_dccm, ahb_hwrite_q) @[ahb_to_axi4.scala 116:46]
node _T_133 = or(ahb_addr_in_iccm, _T_132) @[ahb_to_axi4.scala 116:26]
node _T_134 = bits(ahb_hsize_q, 1, 0) @[ahb_to_axi4.scala 116:80]
node _T_135 = eq(_T_134, UInt<2>("h02")) @[ahb_to_axi4.scala 116:86]
node _T_136 = bits(ahb_hsize_q, 1, 0) @[ahb_to_axi4.scala 116:109]
node _T_137 = eq(_T_136, UInt<2>("h03")) @[ahb_to_axi4.scala 116:115]
node _T_138 = or(_T_135, _T_137) @[ahb_to_axi4.scala 116:95]
node _T_139 = eq(_T_138, UInt<1>("h00")) @[ahb_to_axi4.scala 116:66]
node _T_140 = and(_T_133, _T_139) @[ahb_to_axi4.scala 116:64]
node _T_141 = or(_T_131, _T_140) @[ahb_to_axi4.scala 115:47]
node _T_142 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 117:20]
node _T_143 = eq(_T_142, UInt<1>("h01")) @[ahb_to_axi4.scala 117:26]
node _T_144 = bits(ahb_haddr_q, 0, 0) @[ahb_to_axi4.scala 117:48]
node _T_145 = and(_T_143, _T_144) @[ahb_to_axi4.scala 117:35]
node _T_146 = or(_T_141, _T_145) @[ahb_to_axi4.scala 116:126]
node _T_147 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 118:20]
node _T_148 = eq(_T_147, UInt<2>("h02")) @[ahb_to_axi4.scala 118:26]
node _T_149 = bits(ahb_haddr_q, 1, 0) @[ahb_to_axi4.scala 118:49]
node _T_150 = orr(_T_149) @[ahb_to_axi4.scala 118:56]
node _T_151 = and(_T_148, _T_150) @[ahb_to_axi4.scala 118:35]
node _T_152 = or(_T_146, _T_151) @[ahb_to_axi4.scala 117:55]
node _T_153 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 119:20]
node _T_154 = eq(_T_153, UInt<2>("h03")) @[ahb_to_axi4.scala 119:26]
node _T_155 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 119:49]
node _T_156 = orr(_T_155) @[ahb_to_axi4.scala 119:56]
node _T_157 = and(_T_154, _T_156) @[ahb_to_axi4.scala 119:35]
node _T_158 = or(_T_152, _T_157) @[ahb_to_axi4.scala 118:61]
node _T_159 = and(_T_129, _T_158) @[ahb_to_axi4.scala 114:94]
node _T_160 = or(_T_159, buf_read_error) @[ahb_to_axi4.scala 119:63]
node _T_161 = eq(ahb_hready_q, UInt<1>("h00")) @[ahb_to_axi4.scala 121:20]
node _T_162 = and(ahb_hresp_q, _T_161) @[ahb_to_axi4.scala 121:18]
node _T_163 = or(_T_160, _T_162) @[ahb_to_axi4.scala 120:20]
io.ahb.sig.in.hresp <= _T_163 @[ahb_to_axi4.scala 114:38]
node _T_164 = and(cmdbuf_vld, cmdbuf_write) @[ahb_to_axi4.scala 124:47]
io.axi.aw.valid <= _T_164 @[ahb_to_axi4.scala 124:33]
io.axi.aw.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 125:33]
io.axi.aw.bits.addr <= cmdbuf_addr @[ahb_to_axi4.scala 126:33]
node _T_165 = bits(cmdbuf_size, 1, 0) @[ahb_to_axi4.scala 127:59]
node _T_166 = cat(UInt<1>("h00"), _T_165) @[Cat.scala 29:58]
io.axi.aw.bits.size <= _T_166 @[ahb_to_axi4.scala 127:33]
node _T_167 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
io.axi.aw.bits.prot <= _T_167 @[ahb_to_axi4.scala 128:33]
node _T_168 = mux(UInt<1>("h00"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
io.axi.aw.bits.len <= _T_168 @[ahb_to_axi4.scala 129:33]
io.axi.aw.bits.burst <= UInt<2>("h01") @[ahb_to_axi4.scala 130:33]
node _T_169 = and(cmdbuf_vld, cmdbuf_write) @[ahb_to_axi4.scala 132:47]
io.axi.w.valid <= _T_169 @[ahb_to_axi4.scala 132:33]
io.axi.w.bits.data <= cmdbuf_wdata @[ahb_to_axi4.scala 133:33]
io.axi.w.bits.strb <= cmdbuf_wstrb @[ahb_to_axi4.scala 134:33]
io.axi.w.bits.last <= UInt<1>("h01") @[ahb_to_axi4.scala 135:33]
io.axi.b.ready <= UInt<1>("h01") @[ahb_to_axi4.scala 137:33]
node _T_170 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 139:49]
node _T_171 = and(cmdbuf_vld, _T_170) @[ahb_to_axi4.scala 139:47]
io.axi.ar.valid <= _T_171 @[ahb_to_axi4.scala 139:33]
io.axi.ar.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 140:33]
io.axi.ar.bits.addr <= cmdbuf_addr @[ahb_to_axi4.scala 141:33]
node _T_172 = bits(cmdbuf_size, 1, 0) @[ahb_to_axi4.scala 142:59]
node _T_173 = cat(UInt<1>("h00"), _T_172) @[Cat.scala 29:58]
io.axi.ar.bits.size <= _T_173 @[ahb_to_axi4.scala 142:33]
node _T_174 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
io.axi.ar.bits.prot <= _T_174 @[ahb_to_axi4.scala 143:33]
node _T_175 = mux(UInt<1>("h00"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
io.axi.ar.bits.len <= _T_175 @[ahb_to_axi4.scala 144:33]
io.axi.ar.bits.burst <= UInt<2>("h01") @[ahb_to_axi4.scala 145:33]
io.axi.r.ready <= UInt<1>("h01") @[ahb_to_axi4.scala 147:28]

523
ahb_to_axi4.v
View File

@ -1,523 +0,0 @@
module rvclkhdr(
input io_clk,
input io_en
);
wire clkhdr_Q; // @[lib.scala 334:26]
wire clkhdr_CK; // @[lib.scala 334:26]
wire clkhdr_EN; // @[lib.scala 334:26]
wire clkhdr_SE; // @[lib.scala 334:26]
gated_latch clkhdr ( // @[lib.scala 334:26]
.Q(clkhdr_Q),
.CK(clkhdr_CK),
.EN(clkhdr_EN),
.SE(clkhdr_SE)
);
assign clkhdr_CK = io_clk; // @[lib.scala 336:18]
assign clkhdr_EN = io_en; // @[lib.scala 337:18]
assign clkhdr_SE = 1'h0; // @[lib.scala 338:18]
endmodule
module ahb_to_axi4(
input clock,
input reset,
input io_scan_mode,
input io_bus_clk_en,
input io_clk_override,
input io_axi_aw_ready,
output io_axi_aw_valid,
output io_axi_aw_bits_id,
output [31:0] io_axi_aw_bits_addr,
output [3:0] io_axi_aw_bits_region,
output [7:0] io_axi_aw_bits_len,
output [2:0] io_axi_aw_bits_size,
output [1:0] io_axi_aw_bits_burst,
output io_axi_aw_bits_lock,
output [3:0] io_axi_aw_bits_cache,
output [2:0] io_axi_aw_bits_prot,
output [3:0] io_axi_aw_bits_qos,
input io_axi_w_ready,
output io_axi_w_valid,
output [63:0] io_axi_w_bits_data,
output [7:0] io_axi_w_bits_strb,
output io_axi_w_bits_last,
output io_axi_b_ready,
input io_axi_b_valid,
input [1:0] io_axi_b_bits_resp,
input io_axi_b_bits_id,
input io_axi_ar_ready,
output io_axi_ar_valid,
output io_axi_ar_bits_id,
output [31:0] io_axi_ar_bits_addr,
output [3:0] io_axi_ar_bits_region,
output [7:0] io_axi_ar_bits_len,
output [2:0] io_axi_ar_bits_size,
output [1:0] io_axi_ar_bits_burst,
output io_axi_ar_bits_lock,
output [3:0] io_axi_ar_bits_cache,
output [2:0] io_axi_ar_bits_prot,
output [3:0] io_axi_ar_bits_qos,
output io_axi_r_ready,
input io_axi_r_valid,
input io_axi_r_bits_id,
input [63:0] io_axi_r_bits_data,
input [1:0] io_axi_r_bits_resp,
input io_axi_r_bits_last,
output [63:0] io_ahb_sig_in_hrdata,
output io_ahb_sig_in_hready,
output io_ahb_sig_in_hresp,
input [31:0] io_ahb_sig_out_haddr,
input [2:0] io_ahb_sig_out_hburst,
input io_ahb_sig_out_hmastlock,
input [3:0] io_ahb_sig_out_hprot,
input [2:0] io_ahb_sig_out_hsize,
input [1:0] io_ahb_sig_out_htrans,
input io_ahb_sig_out_hwrite,
input [63:0] io_ahb_sig_out_hwdata,
input io_ahb_hsel,
input io_ahb_hreadyin
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
reg [31:0] _RAND_2;
reg [31:0] _RAND_3;
reg [63:0] _RAND_4;
reg [31:0] _RAND_5;
reg [31:0] _RAND_6;
reg [31:0] _RAND_7;
reg [31:0] _RAND_8;
reg [31:0] _RAND_9;
reg [31:0] _RAND_10;
reg [31:0] _RAND_11;
reg [31:0] _RAND_12;
reg [31:0] _RAND_13;
reg [63:0] _RAND_14;
`endif // RANDOMIZE_REG_INIT
wire rvclkhdr_io_clk; // @[lib.scala 399:23]
wire rvclkhdr_io_en; // @[lib.scala 399:23]
wire rvclkhdr_1_io_clk; // @[lib.scala 399:23]
wire rvclkhdr_1_io_en; // @[lib.scala 399:23]
wire ahb_hready = io_ahb_sig_in_hready & io_ahb_hreadyin; // @[ahb_to_axi4.scala 27:50]
wire [1:0] _T_2 = io_ahb_hsel ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire [1:0] ahb_htrans_in = _T_2 & io_ahb_sig_out_htrans; // @[ahb_to_axi4.scala 28:49]
wire _T_5 = ahb_hready & io_ahb_sig_out_htrans[1]; // @[ahb_to_axi4.scala 36:57]
wire ahb_addr_clk_en = io_bus_clk_en & _T_5; // @[ahb_to_axi4.scala 36:43]
reg [1:0] buf_state; // @[Reg.scala 27:20]
wire _T_44 = 2'h0 == buf_state; // @[Conditional.scala 37:30]
wire _T_49 = 2'h1 == buf_state; // @[Conditional.scala 37:30]
wire _T_67 = 2'h2 == buf_state; // @[Conditional.scala 37:30]
wire _T_74 = 2'h3 == buf_state; // @[Conditional.scala 37:30]
wire _T_48 = _T_5 & io_ahb_hsel; // @[ahb_to_axi4.scala 85:61]
reg cmdbuf_vld; // @[Reg.scala 27:20]
wire _T_25 = io_axi_aw_valid & io_axi_aw_ready; // @[ahb_to_axi4.scala 63:58]
wire _T_26 = io_axi_ar_valid & io_axi_ar_ready; // @[ahb_to_axi4.scala 63:96]
wire _T_27 = _T_25 | _T_26; // @[ahb_to_axi4.scala 63:77]
wire _T_28 = ~_T_27; // @[ahb_to_axi4.scala 63:39]
wire cmdbuf_full = cmdbuf_vld & _T_28; // @[ahb_to_axi4.scala 63:37]
wire _T_58 = ~cmdbuf_full; // @[ahb_to_axi4.scala 89:24]
wire _T_59 = _T_58 | io_ahb_sig_in_hresp; // @[ahb_to_axi4.scala 89:37]
reg cmdbuf_write; // @[Reg.scala 27:20]
wire _T_75 = ~cmdbuf_write; // @[ahb_to_axi4.scala 99:40]
wire _T_76 = io_axi_r_valid & _T_75; // @[ahb_to_axi4.scala 99:38]
wire _GEN_15 = _T_74 & _T_76; // @[Conditional.scala 39:67]
wire _GEN_19 = _T_67 ? _T_59 : _GEN_15; // @[Conditional.scala 39:67]
wire _GEN_24 = _T_49 ? _T_59 : _GEN_19; // @[Conditional.scala 39:67]
wire buf_state_en = _T_44 ? _T_48 : _GEN_24; // @[Conditional.scala 40:58]
wire _GEN_16 = _T_74 & buf_state_en; // @[Conditional.scala 39:67]
wire _GEN_21 = _T_67 ? 1'h0 : _GEN_16; // @[Conditional.scala 39:67]
wire _GEN_26 = _T_49 ? 1'h0 : _GEN_21; // @[Conditional.scala 39:67]
wire buf_rdata_en = _T_44 ? 1'h0 : _GEN_26; // @[Conditional.scala 40:58]
wire buf_rdata_clk_en = io_bus_clk_en & buf_rdata_en; // @[ahb_to_axi4.scala 37:43]
reg buf_read_error; // @[Reg.scala 27:20]
wire _T_78 = |io_axi_r_bits_resp; // @[ahb_to_axi4.scala 101:68]
wire _T_79 = buf_state_en & _T_78; // @[ahb_to_axi4.scala 101:41]
wire _GEN_17 = _T_74 & _T_79; // @[Conditional.scala 39:67]
reg [63:0] buf_rdata; // @[Reg.scala 27:20]
reg ahb_hresp_q; // @[Reg.scala 27:20]
reg [2:0] ahb_hsize_q; // @[Reg.scala 27:20]
reg ahb_hwrite_q; // @[Reg.scala 27:20]
reg [31:0] ahb_haddr_q; // @[Reg.scala 27:20]
reg ahb_hready_q; // @[Reg.scala 27:20]
reg [1:0] ahb_htrans_q; // @[Reg.scala 27:20]
wire _T_62 = io_ahb_sig_out_htrans == 2'h1; // @[ahb_to_axi4.scala 90:92]
wire _T_63 = _T_62 & io_ahb_hsel; // @[ahb_to_axi4.scala 90:110]
wire _T_64 = io_ahb_sig_in_hresp | _T_63; // @[ahb_to_axi4.scala 90:60]
wire _T_65 = ~_T_64; // @[ahb_to_axi4.scala 90:38]
wire _T_66 = _T_58 & _T_65; // @[ahb_to_axi4.scala 90:36]
wire _T_71 = ~io_ahb_sig_in_hresp; // @[ahb_to_axi4.scala 95:23]
wire _T_73 = _T_71 & _T_58; // @[ahb_to_axi4.scala 95:44]
wire _GEN_20 = _T_67 & _T_73; // @[Conditional.scala 39:67]
wire _GEN_25 = _T_49 ? _T_66 : _GEN_20; // @[Conditional.scala 39:67]
wire cmdbuf_wr_en = _T_44 ? 1'h0 : _GEN_25; // @[Conditional.scala 40:58]
wire _T_10 = io_bus_clk_en & cmdbuf_wr_en; // @[lib.scala 383:57]
wire _T_14 = ~cmdbuf_wr_en; // @[ahb_to_axi4.scala 61:104]
wire _T_15 = _T_27 & _T_14; // @[ahb_to_axi4.scala 61:102]
wire _T_17 = io_ahb_sig_in_hresp & _T_75; // @[ahb_to_axi4.scala 61:142]
wire cmdbuf_rst = _T_15 | _T_17; // @[ahb_to_axi4.scala 61:119]
wire _T_19 = ~cmdbuf_rst; // @[lib.scala 391:73]
wire _T_21 = cmdbuf_wr_en | cmdbuf_rst; // @[lib.scala 391:92]
wire _T_22 = _T_21 & io_bus_clk_en; // @[lib.scala 391:99]
reg [1:0] cmdbuf_size; // @[Reg.scala 27:20]
reg [7:0] cmdbuf_wstrb; // @[Reg.scala 27:20]
wire _T_84 = ahb_hsize_q == 3'h0; // @[ahb_to_axi4.scala 106:60]
wire [7:0] _T_86 = _T_84 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
wire [7:0] _T_88 = 8'h1 << ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 106:78]
wire [7:0] _T_89 = _T_86 & _T_88; // @[ahb_to_axi4.scala 106:70]
wire _T_91 = ahb_hsize_q == 3'h1; // @[ahb_to_axi4.scala 107:30]
wire [7:0] _T_93 = _T_91 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
wire [8:0] _T_95 = 9'h3 << ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 107:48]
wire [8:0] _GEN_34 = {{1'd0}, _T_93}; // @[ahb_to_axi4.scala 107:40]
wire [8:0] _T_96 = _GEN_34 & _T_95; // @[ahb_to_axi4.scala 107:40]
wire [8:0] _GEN_35 = {{1'd0}, _T_89}; // @[ahb_to_axi4.scala 106:109]
wire [8:0] _T_97 = _GEN_35 | _T_96; // @[ahb_to_axi4.scala 106:109]
wire _T_99 = ahb_hsize_q == 3'h2; // @[ahb_to_axi4.scala 108:30]
wire [7:0] _T_101 = _T_99 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
wire [10:0] _T_103 = 11'hf << ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 108:48]
wire [10:0] _GEN_36 = {{3'd0}, _T_101}; // @[ahb_to_axi4.scala 108:40]
wire [10:0] _T_104 = _GEN_36 & _T_103; // @[ahb_to_axi4.scala 108:40]
wire [10:0] _GEN_37 = {{2'd0}, _T_97}; // @[ahb_to_axi4.scala 107:79]
wire [10:0] _T_105 = _GEN_37 | _T_104; // @[ahb_to_axi4.scala 107:79]
wire _T_107 = ahb_hsize_q == 3'h3; // @[ahb_to_axi4.scala 109:30]
wire [7:0] _T_109 = _T_107 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
wire [10:0] _GEN_38 = {{3'd0}, _T_109}; // @[ahb_to_axi4.scala 108:79]
wire [10:0] _T_111 = _T_105 | _GEN_38; // @[ahb_to_axi4.scala 108:79]
wire [7:0] master_wstrb = _T_111[7:0]; // @[ahb_to_axi4.scala 106:31]
wire _T_35 = cmdbuf_wr_en & io_bus_clk_en; // @[ahb_to_axi4.scala 66:66]
reg [31:0] cmdbuf_addr; // @[Reg.scala 27:20]
reg [63:0] cmdbuf_wdata; // @[Reg.scala 27:20]
wire ahb_addr_in_dccm = ahb_haddr_q[31:16] == 16'hf004; // @[lib.scala 87:29]
wire ahb_addr_in_iccm = ahb_haddr_q[31:16] == 16'hee00; // @[lib.scala 87:29]
wire _T_51 = io_ahb_sig_out_htrans == 2'h0; // @[ahb_to_axi4.scala 88:79]
wire _T_52 = io_ahb_sig_in_hresp | _T_51; // @[ahb_to_axi4.scala 88:48]
wire _T_53 = ~io_ahb_hsel; // @[ahb_to_axi4.scala 88:93]
wire _T_54 = _T_52 | _T_53; // @[ahb_to_axi4.scala 88:91]
wire _T_81 = io_bus_clk_en & buf_state_en; // @[lib.scala 383:57]
wire _T_112 = ~ahb_hready_q; // @[ahb_to_axi4.scala 112:80]
wire _T_113 = ahb_hresp_q & _T_112; // @[ahb_to_axi4.scala 112:78]
wire _T_115 = buf_state == 2'h0; // @[ahb_to_axi4.scala 112:124]
wire _T_116 = _T_58 | _T_115; // @[ahb_to_axi4.scala 112:111]
wire _T_117 = buf_state == 2'h2; // @[ahb_to_axi4.scala 112:149]
wire _T_118 = buf_state == 2'h3; // @[ahb_to_axi4.scala 112:168]
wire _T_119 = _T_117 | _T_118; // @[ahb_to_axi4.scala 112:156]
wire _T_120 = ~_T_119; // @[ahb_to_axi4.scala 112:137]
wire _T_121 = _T_116 & _T_120; // @[ahb_to_axi4.scala 112:135]
wire _T_122 = ~buf_read_error; // @[ahb_to_axi4.scala 112:181]
wire _T_123 = _T_121 & _T_122; // @[ahb_to_axi4.scala 112:179]
wire _T_127 = ahb_htrans_q != 2'h0; // @[ahb_to_axi4.scala 114:61]
wire _T_128 = buf_state != 2'h0; // @[ahb_to_axi4.scala 114:83]
wire _T_129 = _T_127 & _T_128; // @[ahb_to_axi4.scala 114:70]
wire _T_130 = ahb_addr_in_dccm | ahb_addr_in_iccm; // @[ahb_to_axi4.scala 115:26]
wire _T_131 = ~_T_130; // @[ahb_to_axi4.scala 115:7]
wire _T_132 = ahb_addr_in_dccm & ahb_hwrite_q; // @[ahb_to_axi4.scala 116:46]
wire _T_133 = ahb_addr_in_iccm | _T_132; // @[ahb_to_axi4.scala 116:26]
wire _T_135 = ahb_hsize_q[1:0] == 2'h2; // @[ahb_to_axi4.scala 116:86]
wire _T_137 = ahb_hsize_q[1:0] == 2'h3; // @[ahb_to_axi4.scala 116:115]
wire _T_138 = _T_135 | _T_137; // @[ahb_to_axi4.scala 116:95]
wire _T_139 = ~_T_138; // @[ahb_to_axi4.scala 116:66]
wire _T_140 = _T_133 & _T_139; // @[ahb_to_axi4.scala 116:64]
wire _T_141 = _T_131 | _T_140; // @[ahb_to_axi4.scala 115:47]
wire _T_145 = _T_91 & ahb_haddr_q[0]; // @[ahb_to_axi4.scala 117:35]
wire _T_146 = _T_141 | _T_145; // @[ahb_to_axi4.scala 116:126]
wire _T_150 = |ahb_haddr_q[1:0]; // @[ahb_to_axi4.scala 118:56]
wire _T_151 = _T_99 & _T_150; // @[ahb_to_axi4.scala 118:35]
wire _T_152 = _T_146 | _T_151; // @[ahb_to_axi4.scala 117:55]
wire _T_156 = |ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 119:56]
wire _T_157 = _T_107 & _T_156; // @[ahb_to_axi4.scala 119:35]
wire _T_158 = _T_152 | _T_157; // @[ahb_to_axi4.scala 118:61]
wire _T_159 = _T_129 & _T_158; // @[ahb_to_axi4.scala 114:94]
wire _T_160 = _T_159 | buf_read_error; // @[ahb_to_axi4.scala 119:63]
rvclkhdr rvclkhdr ( // @[lib.scala 399:23]
.io_clk(rvclkhdr_io_clk),
.io_en(rvclkhdr_io_en)
);
rvclkhdr rvclkhdr_1 ( // @[lib.scala 399:23]
.io_clk(rvclkhdr_1_io_clk),
.io_en(rvclkhdr_1_io_en)
);
assign io_axi_aw_valid = cmdbuf_vld & cmdbuf_write; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 124:33]
assign io_axi_aw_bits_id = 1'h0; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 125:33]
assign io_axi_aw_bits_addr = cmdbuf_addr; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 126:33]
assign io_axi_aw_bits_region = 4'h0; // @[ahb_to_axi4.scala 20:10]
assign io_axi_aw_bits_len = 8'h0; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 129:33]
assign io_axi_aw_bits_size = {1'h0,cmdbuf_size}; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 127:33]
assign io_axi_aw_bits_burst = 2'h1; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 130:33]
assign io_axi_aw_bits_lock = 1'h0; // @[ahb_to_axi4.scala 20:10]
assign io_axi_aw_bits_cache = 4'h0; // @[ahb_to_axi4.scala 20:10]
assign io_axi_aw_bits_prot = 3'h0; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 128:33]
assign io_axi_aw_bits_qos = 4'h0; // @[ahb_to_axi4.scala 20:10]
assign io_axi_w_valid = cmdbuf_vld & cmdbuf_write; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 132:33]
assign io_axi_w_bits_data = cmdbuf_wdata; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 133:33]
assign io_axi_w_bits_strb = cmdbuf_wstrb; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 134:33]
assign io_axi_w_bits_last = 1'h1; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 135:33]
assign io_axi_b_ready = 1'h1; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 137:33]
assign io_axi_ar_valid = cmdbuf_vld & _T_75; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 139:33]
assign io_axi_ar_bits_id = 1'h0; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 140:33]
assign io_axi_ar_bits_addr = cmdbuf_addr; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 141:33]
assign io_axi_ar_bits_region = 4'h0; // @[ahb_to_axi4.scala 20:10]
assign io_axi_ar_bits_len = 8'h0; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 144:33]
assign io_axi_ar_bits_size = {1'h0,cmdbuf_size}; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 142:33]
assign io_axi_ar_bits_burst = 2'h1; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 145:33]
assign io_axi_ar_bits_lock = 1'h0; // @[ahb_to_axi4.scala 20:10]
assign io_axi_ar_bits_cache = 4'h0; // @[ahb_to_axi4.scala 20:10]
assign io_axi_ar_bits_prot = 3'h0; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 143:33]
assign io_axi_ar_bits_qos = 4'h0; // @[ahb_to_axi4.scala 20:10]
assign io_axi_r_ready = 1'h1; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 147:28]
assign io_ahb_sig_in_hrdata = buf_rdata; // @[ahb_to_axi4.scala 113:38]
assign io_ahb_sig_in_hready = io_ahb_sig_in_hresp ? _T_113 : _T_123; // @[ahb_to_axi4.scala 112:38]
assign io_ahb_sig_in_hresp = _T_160 | _T_113; // @[ahb_to_axi4.scala 114:38]
assign rvclkhdr_io_clk = clock; // @[lib.scala 401:18]
assign rvclkhdr_io_en = cmdbuf_wr_en & io_bus_clk_en; // @[lib.scala 402:17]
assign rvclkhdr_1_io_clk = clock; // @[lib.scala 401:18]
assign rvclkhdr_1_io_en = cmdbuf_wr_en & io_bus_clk_en; // @[lib.scala 402:17]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
buf_state = _RAND_0[1:0];
_RAND_1 = {1{`RANDOM}};
cmdbuf_vld = _RAND_1[0:0];
_RAND_2 = {1{`RANDOM}};
cmdbuf_write = _RAND_2[0:0];
_RAND_3 = {1{`RANDOM}};
buf_read_error = _RAND_3[0:0];
_RAND_4 = {2{`RANDOM}};
buf_rdata = _RAND_4[63:0];
_RAND_5 = {1{`RANDOM}};
ahb_hresp_q = _RAND_5[0:0];
_RAND_6 = {1{`RANDOM}};
ahb_hsize_q = _RAND_6[2:0];
_RAND_7 = {1{`RANDOM}};
ahb_hwrite_q = _RAND_7[0:0];
_RAND_8 = {1{`RANDOM}};
ahb_haddr_q = _RAND_8[31:0];
_RAND_9 = {1{`RANDOM}};
ahb_hready_q = _RAND_9[0:0];
_RAND_10 = {1{`RANDOM}};
ahb_htrans_q = _RAND_10[1:0];
_RAND_11 = {1{`RANDOM}};
cmdbuf_size = _RAND_11[1:0];
_RAND_12 = {1{`RANDOM}};
cmdbuf_wstrb = _RAND_12[7:0];
_RAND_13 = {1{`RANDOM}};
cmdbuf_addr = _RAND_13[31:0];
_RAND_14 = {2{`RANDOM}};
cmdbuf_wdata = _RAND_14[63:0];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
buf_state = 2'h0;
end
if (reset) begin
cmdbuf_vld = 1'h0;
end
if (reset) begin
cmdbuf_write = 1'h0;
end
if (reset) begin
buf_read_error = 1'h0;
end
if (reset) begin
buf_rdata = 64'h0;
end
if (reset) begin
ahb_hresp_q = 1'h0;
end
if (reset) begin
ahb_hsize_q = 3'h0;
end
if (reset) begin
ahb_hwrite_q = 1'h0;
end
if (reset) begin
ahb_haddr_q = 32'h0;
end
if (reset) begin
ahb_hready_q = 1'h0;
end
if (reset) begin
ahb_htrans_q = 2'h0;
end
if (reset) begin
cmdbuf_size = 2'h0;
end
if (reset) begin
cmdbuf_wstrb = 8'h0;
end
if (reset) begin
cmdbuf_addr = 32'h0;
end
if (reset) begin
cmdbuf_wdata = 64'h0;
end
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge clock or posedge reset) begin
if (reset) begin
buf_state <= 2'h0;
end else if (_T_81) begin
if (_T_44) begin
if (io_ahb_sig_out_hwrite) begin
buf_state <= 2'h1;
end else begin
buf_state <= 2'h2;
end
end else if (_T_49) begin
if (_T_54) begin
buf_state <= 2'h0;
end else if (io_ahb_sig_out_hwrite) begin
buf_state <= 2'h1;
end else begin
buf_state <= 2'h2;
end
end else if (_T_67) begin
if (io_ahb_sig_in_hresp) begin
buf_state <= 2'h0;
end else begin
buf_state <= 2'h3;
end
end else begin
buf_state <= 2'h0;
end
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
cmdbuf_vld <= 1'h0;
end else if (_T_22) begin
cmdbuf_vld <= _T_19;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
cmdbuf_write <= 1'h0;
end else if (_T_10) begin
cmdbuf_write <= ahb_hwrite_q;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
buf_read_error <= 1'h0;
end else if (io_bus_clk_en) begin
if (_T_44) begin
buf_read_error <= 1'h0;
end else if (_T_49) begin
buf_read_error <= 1'h0;
end else if (_T_67) begin
buf_read_error <= 1'h0;
end else begin
buf_read_error <= _GEN_17;
end
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
buf_rdata <= 64'h0;
end else if (buf_rdata_clk_en) begin
buf_rdata <= io_axi_r_bits_data;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
ahb_hresp_q <= 1'h0;
end else if (io_bus_clk_en) begin
ahb_hresp_q <= io_ahb_sig_in_hresp;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
ahb_hsize_q <= 3'h0;
end else if (ahb_addr_clk_en) begin
ahb_hsize_q <= io_ahb_sig_out_hsize;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
ahb_hwrite_q <= 1'h0;
end else if (ahb_addr_clk_en) begin
ahb_hwrite_q <= io_ahb_sig_out_hwrite;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
ahb_haddr_q <= 32'h0;
end else if (ahb_addr_clk_en) begin
ahb_haddr_q <= io_ahb_sig_out_haddr;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
ahb_hready_q <= 1'h0;
end else if (io_bus_clk_en) begin
ahb_hready_q <= ahb_hready;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
ahb_htrans_q <= 2'h0;
end else if (io_bus_clk_en) begin
ahb_htrans_q <= ahb_htrans_in;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
cmdbuf_size <= 2'h0;
end else if (_T_10) begin
cmdbuf_size <= ahb_hsize_q[1:0];
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
cmdbuf_wstrb <= 8'h0;
end else if (_T_10) begin
cmdbuf_wstrb <= master_wstrb;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
cmdbuf_addr <= 32'h0;
end else if (_T_35) begin
cmdbuf_addr <= ahb_haddr_q;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
cmdbuf_wdata <= 64'h0;
end else if (_T_35) begin
cmdbuf_wdata <= io_ahb_sig_out_hwdata;
end
end
endmodule

114
axi4_to_ahb.anno.json
View File

@ -1,114 +0,0 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_out_haddr",
"sources":[
"~axi4_to_ahb|axi4_to_ahb>io_ahb_out_htrans",
"~axi4_to_ahb|axi4_to_ahb>io_axi_ar_bits_addr",
"~axi4_to_ahb|axi4_to_ahb>io_axi_ar_valid",
"~axi4_to_ahb|axi4_to_ahb>io_axi_b_ready",
"~axi4_to_ahb|axi4_to_ahb>io_axi_r_ready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_w_ready",
"sources":[
"~axi4_to_ahb|axi4_to_ahb>io_axi_ar_valid",
"~axi4_to_ahb|axi4_to_ahb>io_axi_b_ready",
"~axi4_to_ahb|axi4_to_ahb>io_axi_r_ready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_out_hprot",
"sources":[
"~axi4_to_ahb|axi4_to_ahb>io_axi_ar_bits_prot"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_aw_ready",
"sources":[
"~axi4_to_ahb|axi4_to_ahb>io_axi_ar_valid",
"~axi4_to_ahb|axi4_to_ahb>io_axi_b_ready",
"~axi4_to_ahb|axi4_to_ahb>io_axi_r_ready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_b_valid",
"sources":[
"~axi4_to_ahb|axi4_to_ahb>io_axi_b_ready",
"~axi4_to_ahb|axi4_to_ahb>io_axi_r_ready",
"~axi4_to_ahb|axi4_to_ahb>io_axi_ar_valid"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_out_hsize",
"sources":[
"~axi4_to_ahb|axi4_to_ahb>io_axi_ar_valid",
"~axi4_to_ahb|axi4_to_ahb>io_axi_ar_bits_size",
"~axi4_to_ahb|axi4_to_ahb>io_axi_b_ready",
"~axi4_to_ahb|axi4_to_ahb>io_axi_r_ready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_out_hwrite",
"sources":[
"~axi4_to_ahb|axi4_to_ahb>io_axi_ar_valid",
"~axi4_to_ahb|axi4_to_ahb>io_axi_b_ready",
"~axi4_to_ahb|axi4_to_ahb>io_axi_r_ready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_out_htrans",
"sources":[
"~axi4_to_ahb|axi4_to_ahb>io_axi_ar_valid",
"~axi4_to_ahb|axi4_to_ahb>io_axi_b_ready",
"~axi4_to_ahb|axi4_to_ahb>io_axi_r_ready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_r_valid",
"sources":[
"~axi4_to_ahb|axi4_to_ahb>io_axi_b_ready",
"~axi4_to_ahb|axi4_to_ahb>io_axi_r_ready",
"~axi4_to_ahb|axi4_to_ahb>io_axi_ar_valid"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_ar_ready",
"sources":[
"~axi4_to_ahb|axi4_to_ahb>io_axi_ar_valid",
"~axi4_to_ahb|axi4_to_ahb>io_axi_b_ready",
"~axi4_to_ahb|axi4_to_ahb>io_axi_r_ready"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"axi4_to_ahb.gated_latch",
"resourceId":"/vsrc/gated_latch.sv"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"axi4_to_ahb"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

1273
axi4_to_ahb.fir
View File

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1036
axi4_to_ahb.v
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File diff suppressed because it is too large Load Diff

683
dec_dec_ctl.anno.json
View File

@ -1,683 +0,0 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~dec_dec_ctl|dec_dec_ctl>io_out_unshfl",
"sources":[
"~dec_dec_ctl|dec_dec_ctl>io_ins"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
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"sources":[
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]
},
{
"class":"firrtl.transforms.CombinationalPath",
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"sources":[
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]
},
{
"class":"firrtl.transforms.CombinationalPath",
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"sources":[
"~dec_dec_ctl|dec_dec_ctl>io_ins"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
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"sources":[
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]
},
{
"class":"firrtl.transforms.CombinationalPath",
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"sources":[
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]
},
{
"class":"firrtl.transforms.CombinationalPath",
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"sources":[
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]
},
{
"class":"firrtl.transforms.CombinationalPath",
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"sources":[
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]
},
{
"class":"firrtl.transforms.CombinationalPath",
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"sources":[
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]
},
{
"class":"firrtl.transforms.CombinationalPath",
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]
},
{
"class":"firrtl.transforms.CombinationalPath",
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]
},
{
"class":"firrtl.transforms.CombinationalPath",
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]
},
{
"class":"firrtl.transforms.CombinationalPath",
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]
},
{
"class":"firrtl.transforms.CombinationalPath",
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"~dec_dec_ctl|dec_dec_ctl>io_ins"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
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]
},
{
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]
},
{
"class":"firrtl.transforms.CombinationalPath",
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]
},
{
"class":"firrtl.transforms.CombinationalPath",
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]
},
{
"class":"firrtl.transforms.CombinationalPath",
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]
},
{
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]
},
{
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]
},
{
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]
},
{
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]
},
{
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]
},
{
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]
},
{
"class":"firrtl.transforms.CombinationalPath",
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]
},
{
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]
},
{
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]
},
{
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]
},
{
"class":"firrtl.transforms.CombinationalPath",
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},
{
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},
{
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]
},
{
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]
},
{
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]
},
{
"class":"firrtl.transforms.CombinationalPath",
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]
},
{
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]
},
{
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]
},
{
"class":"firrtl.transforms.CombinationalPath",
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]
},
{
"class":"firrtl.transforms.CombinationalPath",
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]
},
{
"class":"firrtl.transforms.CombinationalPath",
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},
{
"class":"firrtl.transforms.CombinationalPath",
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]
},
{
"class":"firrtl.transforms.CombinationalPath",
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]
},
{
"class":"firrtl.transforms.CombinationalPath",
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},
{
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]
},
{
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]
},
{
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]
},
{
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]
},
{
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]
},
{
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},
{
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{
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},
{
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},
{
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]
},
{
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},
{
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]
},
{
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]
},
{
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]
},
{
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]
},
{
"class":"firrtl.transforms.CombinationalPath",
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]
},
{
"class":"firrtl.transforms.CombinationalPath",
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"sources":[
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]
},
{
"class":"firrtl.transforms.CombinationalPath",
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"sources":[
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]
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dec_gpr_ctl.anno.json
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@ -1,37 +0,0 @@
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dec_ib_ctl.anno.json
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@ -1,198 +0,0 @@
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73
dec_ib_ctl.fir
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@ -1,73 +0,0 @@
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
circuit dec_ib_ctl :
module dec_ib_ctl :
input clock : Clock
input reset : UInt<1>
output io : {flip ifu_ib : {ifu_i0_icaf : UInt<1>, ifu_i0_icaf_type : UInt<2>, ifu_i0_icaf_second : UInt<1>, ifu_i0_dbecc : UInt<1>, ifu_i0_bp_index : UInt<8>, ifu_i0_bp_fghr : UInt<8>, ifu_i0_bp_btag : UInt<5>, ifu_i0_valid : UInt<1>, ifu_i0_instr : UInt<32>, ifu_i0_pc : UInt<31>, ifu_i0_pc4 : UInt<1>, i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}}, flip ib_exu : {flip dec_i0_pc_d : UInt<31>, flip dec_debug_wdata_rs1_d : UInt<1>}, dbg_ib : {flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>}, dec_debug_valid_d : UInt<1>, dec_ib0_valid_d : UInt<1>, dec_i0_icaf_type_d : UInt<2>, dec_i0_instr_d : UInt<32>, dec_i0_pc4_d : UInt<1>, dec_i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}, dec_i0_bp_index : UInt<8>, dec_i0_bp_fghr : UInt<8>, dec_i0_bp_btag : UInt<5>, flip ifu_i0_fa_index : UInt<9>, dec_i0_bp_fa_index : UInt<9>, dec_i0_icaf_d : UInt<1>, dec_i0_icaf_second_d : UInt<1>, dec_i0_dbecc_d : UInt<1>, dec_debug_fence_d : UInt<1>}
io.dec_i0_icaf_second_d <= io.ifu_ib.ifu_i0_icaf_second @[dec_ib_ctl.scala 34:35]
io.dec_i0_dbecc_d <= io.ifu_ib.ifu_i0_dbecc @[dec_ib_ctl.scala 35:31]
io.dec_i0_icaf_d <= io.ifu_ib.ifu_i0_icaf @[dec_ib_ctl.scala 36:31]
io.ib_exu.dec_i0_pc_d <= io.ifu_ib.ifu_i0_pc @[dec_ib_ctl.scala 37:31]
io.dec_i0_pc4_d <= io.ifu_ib.ifu_i0_pc4 @[dec_ib_ctl.scala 38:31]
io.dec_i0_icaf_type_d <= io.ifu_ib.ifu_i0_icaf_type @[dec_ib_ctl.scala 39:31]
io.dec_i0_brp.bits.ret <= io.ifu_ib.i0_brp.bits.ret @[dec_ib_ctl.scala 40:31]
io.dec_i0_brp.bits.way <= io.ifu_ib.i0_brp.bits.way @[dec_ib_ctl.scala 40:31]
io.dec_i0_brp.bits.prett <= io.ifu_ib.i0_brp.bits.prett @[dec_ib_ctl.scala 40:31]
io.dec_i0_brp.bits.bank <= io.ifu_ib.i0_brp.bits.bank @[dec_ib_ctl.scala 40:31]
io.dec_i0_brp.bits.br_start_error <= io.ifu_ib.i0_brp.bits.br_start_error @[dec_ib_ctl.scala 40:31]
io.dec_i0_brp.bits.br_error <= io.ifu_ib.i0_brp.bits.br_error @[dec_ib_ctl.scala 40:31]
io.dec_i0_brp.bits.hist <= io.ifu_ib.i0_brp.bits.hist @[dec_ib_ctl.scala 40:31]
io.dec_i0_brp.bits.toffset <= io.ifu_ib.i0_brp.bits.toffset @[dec_ib_ctl.scala 40:31]
io.dec_i0_brp.valid <= io.ifu_ib.i0_brp.valid @[dec_ib_ctl.scala 40:31]
io.dec_i0_bp_index <= io.ifu_ib.ifu_i0_bp_index @[dec_ib_ctl.scala 41:31]
io.dec_i0_bp_fghr <= io.ifu_ib.ifu_i0_bp_fghr @[dec_ib_ctl.scala 42:31]
io.dec_i0_bp_btag <= io.ifu_ib.ifu_i0_bp_btag @[dec_ib_ctl.scala 43:31]
io.dec_i0_bp_fa_index <= io.ifu_i0_fa_index @[dec_ib_ctl.scala 44:25]
node _T = neq(io.dbg_ib.dbg_cmd_type, UInt<2>("h02")) @[dec_ib_ctl.scala 58:74]
node debug_valid = and(io.dbg_ib.dbg_cmd_valid, _T) @[dec_ib_ctl.scala 58:48]
node _T_1 = eq(io.dbg_ib.dbg_cmd_write, UInt<1>("h00")) @[dec_ib_ctl.scala 59:38]
node debug_read = and(debug_valid, _T_1) @[dec_ib_ctl.scala 59:36]
node debug_write = and(debug_valid, io.dbg_ib.dbg_cmd_write) @[dec_ib_ctl.scala 60:36]
io.dec_debug_valid_d <= debug_valid @[dec_ib_ctl.scala 61:24]
node _T_2 = eq(io.dbg_ib.dbg_cmd_type, UInt<1>("h00")) @[dec_ib_ctl.scala 62:62]
node debug_read_gpr = and(debug_read, _T_2) @[dec_ib_ctl.scala 62:37]
node _T_3 = eq(io.dbg_ib.dbg_cmd_type, UInt<1>("h00")) @[dec_ib_ctl.scala 63:62]
node debug_write_gpr = and(debug_write, _T_3) @[dec_ib_ctl.scala 63:37]
node _T_4 = eq(io.dbg_ib.dbg_cmd_type, UInt<1>("h01")) @[dec_ib_ctl.scala 64:62]
node debug_read_csr = and(debug_read, _T_4) @[dec_ib_ctl.scala 64:37]
node _T_5 = eq(io.dbg_ib.dbg_cmd_type, UInt<1>("h01")) @[dec_ib_ctl.scala 65:62]
node debug_write_csr = and(debug_write, _T_5) @[dec_ib_ctl.scala 65:37]
node dreg = bits(io.dbg_ib.dbg_cmd_addr, 4, 0) @[dec_ib_ctl.scala 67:47]
node dcsr = bits(io.dbg_ib.dbg_cmd_addr, 11, 0) @[dec_ib_ctl.scala 68:47]
node _T_6 = bits(debug_read_gpr, 0, 0) @[dec_ib_ctl.scala 71:20]
node _T_7 = mux(UInt<1>("h00"), UInt<12>("h0fff"), UInt<12>("h00")) @[Bitwise.scala 72:12]
node _T_8 = cat(_T_7, dreg) @[Cat.scala 29:58]
node _T_9 = cat(_T_8, UInt<15>("h06033")) @[Cat.scala 29:58]
node _T_10 = bits(debug_write_gpr, 0, 0) @[dec_ib_ctl.scala 72:21]
node _T_11 = cat(UInt<20>("h06"), dreg) @[Cat.scala 29:58]
node _T_12 = cat(_T_11, UInt<7>("h033")) @[Cat.scala 29:58]
node _T_13 = bits(debug_read_csr, 0, 0) @[dec_ib_ctl.scala 73:20]
node _T_14 = cat(dcsr, UInt<20>("h02073")) @[Cat.scala 29:58]
node _T_15 = bits(debug_write_csr, 0, 0) @[dec_ib_ctl.scala 74:21]
node _T_16 = cat(dcsr, UInt<20>("h01073")) @[Cat.scala 29:58]
node _T_17 = mux(_T_6, _T_9, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_18 = mux(_T_10, _T_12, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_19 = mux(_T_13, _T_14, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_20 = mux(_T_15, _T_16, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_21 = or(_T_17, _T_18) @[Mux.scala 27:72]
node _T_22 = or(_T_21, _T_19) @[Mux.scala 27:72]
node _T_23 = or(_T_22, _T_20) @[Mux.scala 27:72]
wire ib0_debug_in : UInt<32> @[Mux.scala 27:72]
ib0_debug_in <= _T_23 @[Mux.scala 27:72]
node _T_24 = or(debug_write_gpr, debug_write_csr) @[dec_ib_ctl.scala 78:54]
io.ib_exu.dec_debug_wdata_rs1_d <= _T_24 @[dec_ib_ctl.scala 78:35]
node _T_25 = eq(dcsr, UInt<11>("h07c4")) @[dec_ib_ctl.scala 81:51]
node _T_26 = and(debug_write_csr, _T_25) @[dec_ib_ctl.scala 81:43]
io.dec_debug_fence_d <= _T_26 @[dec_ib_ctl.scala 81:24]
node _T_27 = or(io.ifu_ib.ifu_i0_valid, debug_valid) @[dec_ib_ctl.scala 83:48]
io.dec_ib0_valid_d <= _T_27 @[dec_ib_ctl.scala 83:22]
node _T_28 = bits(debug_valid, 0, 0) @[dec_ib_ctl.scala 84:41]
node _T_29 = mux(_T_28, ib0_debug_in, io.ifu_ib.ifu_i0_instr) @[dec_ib_ctl.scala 84:28]
io.dec_i0_instr_d <= _T_29 @[dec_ib_ctl.scala 84:22]

103
dec_ib_ctl.v
View File

@ -1,103 +0,0 @@
module dec_ib_ctl(
input clock,
input reset,
input io_ifu_ib_ifu_i0_icaf,
input [1:0] io_ifu_ib_ifu_i0_icaf_type,
input io_ifu_ib_ifu_i0_icaf_second,
input io_ifu_ib_ifu_i0_dbecc,
input [7:0] io_ifu_ib_ifu_i0_bp_index,
input [7:0] io_ifu_ib_ifu_i0_bp_fghr,
input [4:0] io_ifu_ib_ifu_i0_bp_btag,
input io_ifu_ib_ifu_i0_valid,
input [31:0] io_ifu_ib_ifu_i0_instr,
input [30:0] io_ifu_ib_ifu_i0_pc,
input io_ifu_ib_ifu_i0_pc4,
input io_ifu_ib_i0_brp_valid,
input [11:0] io_ifu_ib_i0_brp_bits_toffset,
input [1:0] io_ifu_ib_i0_brp_bits_hist,
input io_ifu_ib_i0_brp_bits_br_error,
input io_ifu_ib_i0_brp_bits_br_start_error,
input io_ifu_ib_i0_brp_bits_bank,
input [30:0] io_ifu_ib_i0_brp_bits_prett,
input io_ifu_ib_i0_brp_bits_way,
input io_ifu_ib_i0_brp_bits_ret,
output [30:0] io_ib_exu_dec_i0_pc_d,
output io_ib_exu_dec_debug_wdata_rs1_d,
input io_dbg_ib_dbg_cmd_valid,
input io_dbg_ib_dbg_cmd_write,
input [1:0] io_dbg_ib_dbg_cmd_type,
input [31:0] io_dbg_ib_dbg_cmd_addr,
output io_dec_debug_valid_d,
output io_dec_ib0_valid_d,
output [1:0] io_dec_i0_icaf_type_d,
output [31:0] io_dec_i0_instr_d,
output io_dec_i0_pc4_d,
output io_dec_i0_brp_valid,
output [11:0] io_dec_i0_brp_bits_toffset,
output [1:0] io_dec_i0_brp_bits_hist,
output io_dec_i0_brp_bits_br_error,
output io_dec_i0_brp_bits_br_start_error,
output io_dec_i0_brp_bits_bank,
output [30:0] io_dec_i0_brp_bits_prett,
output io_dec_i0_brp_bits_way,
output io_dec_i0_brp_bits_ret,
output [7:0] io_dec_i0_bp_index,
output [7:0] io_dec_i0_bp_fghr,
output [4:0] io_dec_i0_bp_btag,
input [8:0] io_ifu_i0_fa_index,
output [8:0] io_dec_i0_bp_fa_index,
output io_dec_i0_icaf_d,
output io_dec_i0_icaf_second_d,
output io_dec_i0_dbecc_d,
output io_dec_debug_fence_d
);
wire _T = io_dbg_ib_dbg_cmd_type != 2'h2; // @[dec_ib_ctl.scala 58:74]
wire debug_valid = io_dbg_ib_dbg_cmd_valid & _T; // @[dec_ib_ctl.scala 58:48]
wire _T_1 = ~io_dbg_ib_dbg_cmd_write; // @[dec_ib_ctl.scala 59:38]
wire debug_read = debug_valid & _T_1; // @[dec_ib_ctl.scala 59:36]
wire debug_write = debug_valid & io_dbg_ib_dbg_cmd_write; // @[dec_ib_ctl.scala 60:36]
wire _T_2 = io_dbg_ib_dbg_cmd_type == 2'h0; // @[dec_ib_ctl.scala 62:62]
wire debug_read_gpr = debug_read & _T_2; // @[dec_ib_ctl.scala 62:37]
wire debug_write_gpr = debug_write & _T_2; // @[dec_ib_ctl.scala 63:37]
wire _T_4 = io_dbg_ib_dbg_cmd_type == 2'h1; // @[dec_ib_ctl.scala 64:62]
wire debug_read_csr = debug_read & _T_4; // @[dec_ib_ctl.scala 64:37]
wire debug_write_csr = debug_write & _T_4; // @[dec_ib_ctl.scala 65:37]
wire [4:0] dreg = io_dbg_ib_dbg_cmd_addr[4:0]; // @[dec_ib_ctl.scala 67:47]
wire [11:0] dcsr = io_dbg_ib_dbg_cmd_addr[11:0]; // @[dec_ib_ctl.scala 68:47]
wire [31:0] _T_9 = {12'h0,dreg,15'h6033}; // @[Cat.scala 29:58]
wire [31:0] _T_12 = {20'h6,dreg,7'h33}; // @[Cat.scala 29:58]
wire [31:0] _T_14 = {dcsr,20'h2073}; // @[Cat.scala 29:58]
wire [31:0] _T_16 = {dcsr,20'h1073}; // @[Cat.scala 29:58]
wire [31:0] _T_17 = debug_read_gpr ? _T_9 : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_18 = debug_write_gpr ? _T_12 : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_19 = debug_read_csr ? _T_14 : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_20 = debug_write_csr ? _T_16 : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_21 = _T_17 | _T_18; // @[Mux.scala 27:72]
wire [31:0] _T_22 = _T_21 | _T_19; // @[Mux.scala 27:72]
wire [31:0] ib0_debug_in = _T_22 | _T_20; // @[Mux.scala 27:72]
wire _T_25 = dcsr == 12'h7c4; // @[dec_ib_ctl.scala 81:51]
assign io_ib_exu_dec_i0_pc_d = io_ifu_ib_ifu_i0_pc; // @[dec_ib_ctl.scala 37:31]
assign io_ib_exu_dec_debug_wdata_rs1_d = debug_write_gpr | debug_write_csr; // @[dec_ib_ctl.scala 78:35]
assign io_dec_debug_valid_d = io_dbg_ib_dbg_cmd_valid & _T; // @[dec_ib_ctl.scala 61:24]
assign io_dec_ib0_valid_d = io_ifu_ib_ifu_i0_valid | debug_valid; // @[dec_ib_ctl.scala 83:22]
assign io_dec_i0_icaf_type_d = io_ifu_ib_ifu_i0_icaf_type; // @[dec_ib_ctl.scala 39:31]
assign io_dec_i0_instr_d = debug_valid ? ib0_debug_in : io_ifu_ib_ifu_i0_instr; // @[dec_ib_ctl.scala 84:22]
assign io_dec_i0_pc4_d = io_ifu_ib_ifu_i0_pc4; // @[dec_ib_ctl.scala 38:31]
assign io_dec_i0_brp_valid = io_ifu_ib_i0_brp_valid; // @[dec_ib_ctl.scala 40:31]
assign io_dec_i0_brp_bits_toffset = io_ifu_ib_i0_brp_bits_toffset; // @[dec_ib_ctl.scala 40:31]
assign io_dec_i0_brp_bits_hist = io_ifu_ib_i0_brp_bits_hist; // @[dec_ib_ctl.scala 40:31]
assign io_dec_i0_brp_bits_br_error = io_ifu_ib_i0_brp_bits_br_error; // @[dec_ib_ctl.scala 40:31]
assign io_dec_i0_brp_bits_br_start_error = io_ifu_ib_i0_brp_bits_br_start_error; // @[dec_ib_ctl.scala 40:31]
assign io_dec_i0_brp_bits_bank = io_ifu_ib_i0_brp_bits_bank; // @[dec_ib_ctl.scala 40:31]
assign io_dec_i0_brp_bits_prett = io_ifu_ib_i0_brp_bits_prett; // @[dec_ib_ctl.scala 40:31]
assign io_dec_i0_brp_bits_way = io_ifu_ib_i0_brp_bits_way; // @[dec_ib_ctl.scala 40:31]
assign io_dec_i0_brp_bits_ret = io_ifu_ib_i0_brp_bits_ret; // @[dec_ib_ctl.scala 40:31]
assign io_dec_i0_bp_index = io_ifu_ib_ifu_i0_bp_index; // @[dec_ib_ctl.scala 41:31]
assign io_dec_i0_bp_fghr = io_ifu_ib_ifu_i0_bp_fghr; // @[dec_ib_ctl.scala 42:31]
assign io_dec_i0_bp_btag = io_ifu_ib_ifu_i0_bp_btag; // @[dec_ib_ctl.scala 43:31]
assign io_dec_i0_bp_fa_index = io_ifu_i0_fa_index; // @[dec_ib_ctl.scala 44:25]
assign io_dec_i0_icaf_d = io_ifu_ib_ifu_i0_icaf; // @[dec_ib_ctl.scala 36:31]
assign io_dec_i0_icaf_second_d = io_ifu_ib_ifu_i0_icaf_second; // @[dec_ib_ctl.scala 34:35]
assign io_dec_i0_dbecc_d = io_ifu_ib_ifu_i0_dbecc; // @[dec_ib_ctl.scala 35:31]
assign io_dec_debug_fence_d = debug_write_csr & _T_25; // @[dec_ib_ctl.scala 81:24]
endmodule

523
dec_tlu_ctl.anno.json
View File

@ -1,523 +0,0 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_flush_pause_r",
"sources":[
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_fastint_stall_any",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_stall_int_ff",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_i0_valid_r",
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_fir_error",
"~dec_tlu_ctl|dec_tlu_ctl>io_mpc_reset_run_req",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_dbg_halted",
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_wrdata_r",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_wraddr_r",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_wen_r",
"~dec_tlu_ctl|dec_tlu_ctl>io_dbg_halt_req",
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type",
"~dec_tlu_ctl|dec_tlu_ctl>io_o_cpu_halt_status",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_fence_i",
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_valid",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_flush_lower_wb",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_icaf",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_legal",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_pic_mhwakeup",
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_error_r",
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_start_error_r",
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_load_any",
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_store_any",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_pause_state",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_debug_mode",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_div_active",
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_mem_ifu_miss_state_idle",
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_idle_any"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_bp_dec_tlu_br0_r_pkt_bits_hist",
"sources":[
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_hist_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_dec_tlu_flush_path_r",
"sources":[
"~dec_tlu_ctl|dec_tlu_ctl>io_rst_vec",
"~dec_tlu_ctl|dec_tlu_ctl>io_mpc_reset_run_req",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_i0_pc_r",
"~dec_tlu_ctl|dec_tlu_ctl>io_nmi_vec",
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_fir_addr",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_i0_valid_r",
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_fir_error",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_dbg_halted",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_stall_int_ff",
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_fastint_stall_any",
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_bits_exc_type",
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type",
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error",
"~dec_tlu_ctl|dec_tlu_ctl>io_dbg_halt_req",
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_npc_r",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_wrdata_r",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_wraddr_r",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_wen_r",
"~dec_tlu_ctl|dec_tlu_ctl>io_o_cpu_halt_status",
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_valid",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_fence_i",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_flush_lower_wb",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_icaf",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_legal",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_pic_mhwakeup",
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_error_r",
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_start_error_r",
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_load_any",
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_store_any",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_pause_state",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_debug_mode",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_div_active",
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_mem_ifu_miss_state_idle",
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_idle_any"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_wr_pause_r",
"sources":[
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_wraddr_r",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_wen_r",
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_fastint_stall_any",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_stall_int_ff",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_i0_valid_r",
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_fir_error",
"~dec_tlu_ctl|dec_tlu_ctl>io_mpc_reset_run_req",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_dbg_halted",
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_wrdata_r",
"~dec_tlu_ctl|dec_tlu_ctl>io_dbg_halt_req",
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type",
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_error_r",
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_start_error_r",
"~dec_tlu_ctl|dec_tlu_ctl>io_o_cpu_halt_status",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_fence_i",
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_valid",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_flush_lower_wb",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_icaf",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_legal",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_pic_mhwakeup",
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_load_any",
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_store_any",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_pause_state",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_debug_mode",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_div_active",
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_mem_ifu_miss_state_idle",
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_idle_any"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_rddata_d",
"sources":[
"~dec_tlu_ctl|dec_tlu_ctl>io_core_id",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_rdaddr_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~dec_tlu_ctl|dec_tlu_ctl>io_dec_dbg_cmd_done",
"sources":[
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_i0_valid_r",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_dbg_halted"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_bp_dec_tlu_br0_r_pkt_bits_way",
"sources":[
"~dec_tlu_ctl|dec_tlu_ctl>io_exu_i0_br_way_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_perfcnt2",
"sources":[
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_dbg_halted"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_flush_extint",
"sources":[
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_fastint_stall_any",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_stall_int_ff",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_i0_valid_r",
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_fir_error",
"~dec_tlu_ctl|dec_tlu_ctl>io_mpc_reset_run_req",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_dbg_halted",
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_wrdata_r",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_wraddr_r",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_wen_r",
"~dec_tlu_ctl|dec_tlu_ctl>io_dbg_halt_req",
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type",
"~dec_tlu_ctl|dec_tlu_ctl>io_o_cpu_halt_status",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_fence_i",
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_valid",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_flush_lower_wb",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_icaf",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_legal",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_pic_mhwakeup",
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_error_r",
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_start_error_r",
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_load_any",
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_store_any",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_pause_state",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_debug_mode",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_div_active",
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_mem_ifu_miss_state_idle",
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_idle_any"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_perfcnt1",
"sources":[
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_dbg_halted"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_presync_d",
"sources":[
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_any_unq_d",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_wen_unq_d",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_rdaddr_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_mem_dec_tlu_i0_commit_cmt",
"sources":[
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_dbg_halted",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_i0_valid_r",
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_valid",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_icaf",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_flush_lower_wb",
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error",
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_error_r",
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_start_error_r",
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger",
"~dec_tlu_ctl|dec_tlu_ctl>io_dbg_halt_req"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_bp_dec_tlu_flush_leak_one_wb",
"sources":[
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_ifc_dec_tlu_flush_noredir_wb",
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_dec_tlu_flush_lower_r",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_resume_ack",
"~dec_tlu_ctl|dec_tlu_ctl>io_mpc_reset_run_req",
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_fastint_stall_any",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_stall_int_ff",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_i0_valid_r",
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_fir_error",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_dbg_halted",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_flush_pause_r",
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error",
"~dec_tlu_ctl|dec_tlu_ctl>io_dbg_halt_req",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_wrdata_r",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_wraddr_r",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_wen_r",
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type",
"~dec_tlu_ctl|dec_tlu_ctl>io_o_cpu_halt_status",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_fence_i",
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_valid",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_flush_lower_wb",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_icaf",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_legal",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_pic_mhwakeup",
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_error_r",
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_start_error_r",
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_load_any",
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_store_any",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_pause_state",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_debug_mode",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_div_active",
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_mem_ifu_miss_state_idle",
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_idle_any"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_perfcnt0",
"sources":[
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_dbg_halted"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_error",
"sources":[
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_error_r",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_i0_valid_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_postsync_d",
"sources":[
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_any_unq_d",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_rdaddr_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_legal_d",
"sources":[
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_any_unq_d",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_wen_unq_d",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_rdaddr_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~dec_tlu_ctl|dec_tlu_ctl>io_dec_dbg_cmd_fail",
"sources":[
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_dbg_cmd_done",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_i0_valid_r",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_dbg_halted",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_legal",
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error",
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_error_r",
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_start_error_r",
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_flush_lower_wb",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger",
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_valid",
"~dec_tlu_ctl|dec_tlu_ctl>io_dbg_halt_req",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_icaf"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_mem_dec_tlu_fence_i_wb",
"sources":[
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_fence_i",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_i0_valid_r",
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error",
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_error_r",
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_start_error_r",
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_flush_lower_wb",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_dbg_halted",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger",
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_valid",
"~dec_tlu_ctl|dec_tlu_ctl>io_dbg_halt_req",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_icaf"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_mem_dec_tlu_flush_err_wb",
"sources":[
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_dec_tlu_flush_lower_r",
"~dec_tlu_ctl|dec_tlu_ctl>io_mpc_reset_run_req",
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_fastint_stall_any",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_stall_int_ff",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_i0_valid_r",
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_fir_error",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_dbg_halted",
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_wrdata_r",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_wraddr_r",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_wen_r",
"~dec_tlu_ctl|dec_tlu_ctl>io_dbg_halt_req",
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type",
"~dec_tlu_ctl|dec_tlu_ctl>io_o_cpu_halt_status",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_fence_i",
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_valid",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_flush_lower_wb",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_icaf",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_legal",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_pic_mhwakeup",
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_error_r",
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_start_error_r",
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_load_any",
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_store_any",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_pause_state",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_debug_mode",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_div_active",
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_mem_ifu_miss_state_idle",
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_idle_any"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_core_empty",
"sources":[
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_div_active",
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_mem_ifu_miss_state_idle",
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_idle_any",
"~dec_tlu_ctl|dec_tlu_ctl>io_mpc_reset_run_req",
"~dec_tlu_ctl|dec_tlu_ctl>io_dbg_halt_req"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
"sources":[
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_start_error_r",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_i0_valid_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_bp_dec_tlu_br0_r_pkt_valid",
"sources":[
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_valid_r",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_i0_valid_r",
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_mp_r",
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_pmu_i0_br_ataken"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_dec_tlu_flush_lower_r",
"sources":[
"~dec_tlu_ctl|dec_tlu_ctl>io_mpc_reset_run_req",
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_fastint_stall_any",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_stall_int_ff",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_i0_valid_r",
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_fir_error",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_dbg_halted",
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_wrdata_r",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_wraddr_r",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_wen_r",
"~dec_tlu_ctl|dec_tlu_ctl>io_dbg_halt_req",
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type",
"~dec_tlu_ctl|dec_tlu_ctl>io_o_cpu_halt_status",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_fence_i",
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_valid",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_flush_lower_wb",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_icaf",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_legal",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_pic_mhwakeup",
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_error_r",
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_start_error_r",
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_load_any",
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_store_any",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_pause_state",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_debug_mode",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_div_active",
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_mem_ifu_miss_state_idle",
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_idle_any"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_bp_dec_tlu_br0_r_pkt_bits_middle",
"sources":[
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_middle_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_ifc_dec_tlu_flush_noredir_wb",
"sources":[
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_flush_pause_r",
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_fastint_stall_any",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_stall_int_ff",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_i0_valid_r",
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_fir_error",
"~dec_tlu_ctl|dec_tlu_ctl>io_mpc_reset_run_req",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_dbg_halted",
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_bits_single_ecc_error",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_wrdata_r",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_wraddr_r",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_csr_wen_r",
"~dec_tlu_ctl|dec_tlu_ctl>io_dbg_halt_req",
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_bits_inst_type",
"~dec_tlu_ctl|dec_tlu_ctl>io_o_cpu_halt_status",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_fence_i",
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_error_pkt_r_valid",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_flush_lower_wb",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_icaf",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_legal",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_pic_mhwakeup",
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_error_r",
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_exu_exu_i0_br_start_error_r",
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_load_any",
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_busbuff_lsu_imprecise_error_store_any",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_pause_state",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_debug_mode",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger",
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_div_active",
"~dec_tlu_ctl|dec_tlu_ctl>io_tlu_mem_ifu_miss_state_idle",
"~dec_tlu_ctl|dec_tlu_ctl>io_lsu_idle_any"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_perfcnt3",
"sources":[
"~dec_tlu_ctl|dec_tlu_ctl>io_dec_tlu_dbg_halted"
]
},
{
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"~dec_tlu_ctl|dec_tlu_ctl>io_dbg_halt_req"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"dec_tlu_ctl.gated_latch",
"resourceId":"/vsrc/gated_latch.sv"
},
{
"class":"firrtl.options.TargetDirAnnotation",
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},
{
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"file":"dec_tlu_ctl"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

9684
dec_tlu_ctl.fir
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8413
dec_tlu_ctl.v
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244
exu_alu_ctl.anno.json
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@ -1,244 +0,0 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~exu_alu_ctl|exu_alu_ctl>io_predict_p_out_valid",
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"~exu_alu_ctl|exu_alu_ctl>io_pp_in_valid"
]
},
{
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"~exu_alu_ctl|exu_alu_ctl>io_dec_tlu_flush_lower_r",
"~exu_alu_ctl|exu_alu_ctl>io_pp_in_bits_pret",
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"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_predict_nt",
"~exu_alu_ctl|exu_alu_ctl>io_pp_in_bits_prett",
"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_bge",
"~exu_alu_ctl|exu_alu_ctl>io_pp_in_bits_pja",
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"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_jal",
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]
},
{
"class":"firrtl.transforms.CombinationalPath",
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]
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]
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"sources":[
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"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_beq",
"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_bne",
"~exu_alu_ctl|exu_alu_ctl>io_a_in",
"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_unsign",
"~exu_alu_ctl|exu_alu_ctl>io_b_in",
"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_sub"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~exu_alu_ctl|exu_alu_ctl>io_predict_p_out_bits_pja",
"sources":[
"~exu_alu_ctl|exu_alu_ctl>io_pp_in_bits_pja"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~exu_alu_ctl|exu_alu_ctl>io_predict_p_out_bits_pc4",
"sources":[
"~exu_alu_ctl|exu_alu_ctl>io_pp_in_bits_pc4"
]
},
{
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"sources":[
"~exu_alu_ctl|exu_alu_ctl>io_pp_in_bits_pret",
"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_bge",
"~exu_alu_ctl|exu_alu_ctl>io_pp_in_bits_pja",
"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_blt",
"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_jal",
"~exu_alu_ctl|exu_alu_ctl>io_pp_in_bits_pcall",
"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_beq",
"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_bne",
"~exu_alu_ctl|exu_alu_ctl>io_a_in",
"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_unsign",
"~exu_alu_ctl|exu_alu_ctl>io_b_in",
"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_sub"
]
},
{
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]
},
{
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]
},
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"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_bge",
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"~exu_alu_ctl|exu_alu_ctl>io_a_in",
"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_unsign",
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"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_sub"
]
},
{
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]
},
{
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"sources":[
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]
},
{
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]
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"~exu_alu_ctl|exu_alu_ctl>io_dec_alu_dec_i0_alu_decode_d",
"~exu_alu_ctl|exu_alu_ctl>io_flush_upper_x",
"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_jal",
"~exu_alu_ctl|exu_alu_ctl>io_pp_in_bits_pret",
"~exu_alu_ctl|exu_alu_ctl>io_pp_in_bits_prett",
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"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_bge",
"~exu_alu_ctl|exu_alu_ctl>io_pp_in_bits_pja",
"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_sub",
"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_blt",
"~exu_alu_ctl|exu_alu_ctl>io_pp_in_bits_pcall",
"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_beq",
"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_bne",
"~exu_alu_ctl|exu_alu_ctl>io_a_in",
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]
},
{
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]
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{
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"~exu_alu_ctl|exu_alu_ctl>io_dec_alu_dec_i0_alu_decode_d",
"~exu_alu_ctl|exu_alu_ctl>io_flush_upper_x",
"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_jal",
"~exu_alu_ctl|exu_alu_ctl>io_pp_in_bits_pret",
"~exu_alu_ctl|exu_alu_ctl>io_pp_in_bits_prett",
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"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_blt",
"~exu_alu_ctl|exu_alu_ctl>io_pp_in_bits_pcall",
"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_beq",
"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_bne",
"~exu_alu_ctl|exu_alu_ctl>io_a_in",
"~exu_alu_ctl|exu_alu_ctl>io_i0_ap_unsign",
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]
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{
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},
{
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"target":"exu_alu_ctl.gated_latch",
"resourceId":"/vsrc/gated_latch.sv"
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{
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"directory":"."
},
{
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},
{
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"targetDir":"."
}
]

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exu_alu_ctl.fir
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exu_alu_ctl.v
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@ -1,582 +0,0 @@
module rvclkhdr(
input io_clk,
input io_en
);
wire clkhdr_Q; // @[lib.scala 334:26]
wire clkhdr_CK; // @[lib.scala 334:26]
wire clkhdr_EN; // @[lib.scala 334:26]
wire clkhdr_SE; // @[lib.scala 334:26]
gated_latch clkhdr ( // @[lib.scala 334:26]
.Q(clkhdr_Q),
.CK(clkhdr_CK),
.EN(clkhdr_EN),
.SE(clkhdr_SE)
);
assign clkhdr_CK = io_clk; // @[lib.scala 336:18]
assign clkhdr_EN = io_en; // @[lib.scala 337:18]
assign clkhdr_SE = 1'h0; // @[lib.scala 338:18]
endmodule
module exu_alu_ctl(
input clock,
input reset,
input io_dec_alu_dec_i0_alu_decode_d,
input io_dec_alu_dec_csr_ren_d,
input [11:0] io_dec_alu_dec_i0_br_immed_d,
output [30:0] io_dec_alu_exu_i0_pc_x,
input [31:0] io_csr_rddata_in,
input [30:0] io_dec_i0_pc_d,
input io_scan_mode,
input io_flush_upper_x,
input io_dec_tlu_flush_lower_r,
input io_enable,
input io_i0_ap_clz,
input io_i0_ap_ctz,
input io_i0_ap_pcnt,
input io_i0_ap_sext_b,
input io_i0_ap_sext_h,
input io_i0_ap_slo,
input io_i0_ap_sro,
input io_i0_ap_min,
input io_i0_ap_max,
input io_i0_ap_pack,
input io_i0_ap_packu,
input io_i0_ap_packh,
input io_i0_ap_rol,
input io_i0_ap_ror,
input io_i0_ap_grev,
input io_i0_ap_gorc,
input io_i0_ap_zbb,
input io_i0_ap_sbset,
input io_i0_ap_sbclr,
input io_i0_ap_sbinv,
input io_i0_ap_sbext,
input io_i0_ap_sh1add,
input io_i0_ap_sh2add,
input io_i0_ap_sh3add,
input io_i0_ap_zba,
input io_i0_ap_land,
input io_i0_ap_lor,
input io_i0_ap_lxor,
input io_i0_ap_sll,
input io_i0_ap_srl,
input io_i0_ap_sra,
input io_i0_ap_beq,
input io_i0_ap_bne,
input io_i0_ap_blt,
input io_i0_ap_bge,
input io_i0_ap_add,
input io_i0_ap_sub,
input io_i0_ap_slt,
input io_i0_ap_unsign,
input io_i0_ap_jal,
input io_i0_ap_predict_t,
input io_i0_ap_predict_nt,
input io_i0_ap_csr_write,
input io_i0_ap_csr_imm,
input [31:0] io_a_in,
input [31:0] io_b_in,
input io_pp_in_valid,
input io_pp_in_bits_misp,
input io_pp_in_bits_ataken,
input io_pp_in_bits_boffset,
input io_pp_in_bits_pc4,
input [1:0] io_pp_in_bits_hist,
input [11:0] io_pp_in_bits_toffset,
input io_pp_in_bits_br_error,
input io_pp_in_bits_br_start_error,
input [30:0] io_pp_in_bits_prett,
input io_pp_in_bits_pcall,
input io_pp_in_bits_pret,
input io_pp_in_bits_pja,
input io_pp_in_bits_way,
output [31:0] io_result_ff,
output io_flush_upper_out,
output io_flush_final_out,
output [30:0] io_flush_path_out,
output io_pred_correct_out,
output io_predict_p_out_valid,
output io_predict_p_out_bits_misp,
output io_predict_p_out_bits_ataken,
output io_predict_p_out_bits_boffset,
output io_predict_p_out_bits_pc4,
output [1:0] io_predict_p_out_bits_hist,
output [11:0] io_predict_p_out_bits_toffset,
output io_predict_p_out_bits_br_error,
output io_predict_p_out_bits_br_start_error,
output [30:0] io_predict_p_out_bits_prett,
output io_predict_p_out_bits_pcall,
output io_predict_p_out_bits_pret,
output io_predict_p_out_bits_pja,
output io_predict_p_out_bits_way
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
`endif // RANDOMIZE_REG_INIT
wire rvclkhdr_io_clk; // @[lib.scala 399:23]
wire rvclkhdr_io_en; // @[lib.scala 399:23]
wire _T_1 = io_b_in[4:0] == 5'h1f; // @[exu_alu_ctl.scala 87:55]
wire ap_rev = io_i0_ap_grev & _T_1; // @[exu_alu_ctl.scala 87:39]
wire _T_4 = io_b_in[4:0] == 5'h18; // @[exu_alu_ctl.scala 88:55]
wire ap_rev8 = io_i0_ap_grev & _T_4; // @[exu_alu_ctl.scala 88:39]
wire _T_7 = io_b_in[4:0] == 5'h7; // @[exu_alu_ctl.scala 89:55]
wire ap_orc_b = io_i0_ap_gorc & _T_7; // @[exu_alu_ctl.scala 89:39]
wire _T_10 = io_b_in[4:0] == 5'h10; // @[exu_alu_ctl.scala 90:55]
wire ap_orc16 = io_i0_ap_gorc & _T_10; // @[exu_alu_ctl.scala 90:39]
reg [30:0] _T_14; // @[Reg.scala 27:20]
wire _T_15 = io_enable & io_dec_alu_dec_i0_alu_decode_d; // @[exu_alu_ctl.scala 135:43]
reg [31:0] _T_18; // @[Reg.scala 27:20]
wire [31:0] _T_153 = io_csr_rddata_in; // @[Mux.scala 27:72]
wire [32:0] _T_151 = {{1{_T_153[31]}},_T_153}; // @[Mux.scala 27:72 Mux.scala 27:72]
wire [32:0] _T_172 = io_dec_alu_dec_csr_ren_d ? $signed(_T_151) : $signed(33'sh0); // @[Mux.scala 27:72]
wire _T_94 = ~io_i0_ap_zbb; // @[exu_alu_ctl.scala 160:22]
wire _T_95 = io_i0_ap_land & _T_94; // @[exu_alu_ctl.scala 160:20]
wire [32:0] _T_98 = {1'h0,io_a_in}; // @[Cat.scala 29:58]
wire [32:0] _T_99 = {1'h0,io_a_in}; // @[exu_alu_ctl.scala 160:67]
wire [31:0] _T_100 = io_b_in; // @[exu_alu_ctl.scala 160:85]
wire [32:0] _GEN_2 = {{1{_T_100[31]}},_T_100}; // @[exu_alu_ctl.scala 160:74]
wire [32:0] _T_156 = $signed(_T_99) & $signed(_GEN_2); // @[Mux.scala 27:72]
wire [32:0] _T_173 = _T_95 ? $signed(_T_156) : $signed(33'sh0); // @[Mux.scala 27:72]
wire [32:0] _T_180 = $signed(_T_172) | $signed(_T_173); // @[Mux.scala 27:72]
wire _T_104 = io_i0_ap_lor & _T_94; // @[exu_alu_ctl.scala 161:20]
wire [32:0] _T_159 = $signed(_T_99) | $signed(_GEN_2); // @[Mux.scala 27:72]
wire [32:0] _T_174 = _T_104 ? $signed(_T_159) : $signed(33'sh0); // @[Mux.scala 27:72]
wire [32:0] _T_182 = $signed(_T_180) | $signed(_T_174); // @[Mux.scala 27:72]
wire _T_113 = io_i0_ap_lxor & _T_94; // @[exu_alu_ctl.scala 162:20]
wire [32:0] _T_162 = $signed(_T_99) ^ $signed(_GEN_2); // @[Mux.scala 27:72]
wire [32:0] _T_175 = _T_113 ? $signed(_T_162) : $signed(33'sh0); // @[Mux.scala 27:72]
wire [32:0] _T_184 = $signed(_T_182) | $signed(_T_175); // @[Mux.scala 27:72]
wire _T_121 = io_i0_ap_land & io_i0_ap_zbb; // @[exu_alu_ctl.scala 163:20]
wire [31:0] _T_128 = ~io_b_in; // @[exu_alu_ctl.scala 163:76]
wire [32:0] _GEN_5 = {{1{_T_128[31]}},_T_128}; // @[exu_alu_ctl.scala 163:74]
wire [32:0] _T_165 = $signed(_T_99) & $signed(_GEN_5); // @[Mux.scala 27:72]
wire [32:0] _T_176 = _T_121 ? $signed(_T_165) : $signed(33'sh0); // @[Mux.scala 27:72]
wire [32:0] _T_186 = $signed(_T_184) | $signed(_T_176); // @[Mux.scala 27:72]
wire _T_131 = io_i0_ap_lor & io_i0_ap_zbb; // @[exu_alu_ctl.scala 164:20]
wire [32:0] _T_168 = $signed(_T_99) | $signed(_GEN_5); // @[Mux.scala 27:72]
wire [32:0] _T_177 = _T_131 ? $signed(_T_168) : $signed(33'sh0); // @[Mux.scala 27:72]
wire [32:0] _T_188 = $signed(_T_186) | $signed(_T_177); // @[Mux.scala 27:72]
wire _T_141 = io_i0_ap_lxor & io_i0_ap_zbb; // @[exu_alu_ctl.scala 165:20]
wire [32:0] _T_171 = $signed(_T_99) ^ $signed(_GEN_5); // @[Mux.scala 27:72]
wire [32:0] _T_178 = _T_141 ? $signed(_T_171) : $signed(33'sh0); // @[Mux.scala 27:72]
wire [32:0] lout = $signed(_T_188) | $signed(_T_178); // @[Mux.scala 27:72]
wire _T_836 = io_i0_ap_sll | io_i0_ap_srl; // @[exu_alu_ctl.scala 293:44]
wire _T_837 = _T_836 | io_i0_ap_sra; // @[exu_alu_ctl.scala 293:59]
wire _T_840 = _T_837 | io_i0_ap_rol; // @[exu_alu_ctl.scala 293:92]
wire sel_shift = _T_840 | io_i0_ap_ror; // @[exu_alu_ctl.scala 293:101]
wire [31:0] _T_887 = sel_shift ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
wire [30:0] _T_345 = io_a_in[31] ? 31'h7fffffff : 31'h0; // @[Bitwise.scala 72:12]
wire [30:0] _T_352 = io_i0_ap_sra ? _T_345 : 31'h0; // @[Mux.scala 27:72]
wire [30:0] _T_353 = io_i0_ap_sll ? io_a_in[30:0] : 31'h0; // @[Mux.scala 27:72]
wire [30:0] _T_358 = _T_352 | _T_353; // @[Mux.scala 27:72]
wire [30:0] _T_354 = io_i0_ap_rol ? io_a_in[30:0] : 31'h0; // @[Mux.scala 27:72]
wire [30:0] _T_359 = _T_358 | _T_354; // @[Mux.scala 27:72]
wire [30:0] _T_355 = io_i0_ap_ror ? io_a_in[30:0] : 31'h0; // @[Mux.scala 27:72]
wire [30:0] _T_360 = _T_359 | _T_355; // @[Mux.scala 27:72]
wire [62:0] shift_extend = {_T_360,io_a_in}; // @[Cat.scala 29:58]
wire [5:0] _T_195 = {1'h0,io_b_in[4:0]}; // @[Cat.scala 29:58]
wire [5:0] _T_197 = 6'h20 - _T_195; // @[exu_alu_ctl.scala 179:41]
wire [5:0] _T_218 = io_i0_ap_sll ? _T_197 : 6'h0; // @[Mux.scala 27:72]
wire [5:0] _T_219 = io_i0_ap_srl ? _T_195 : 6'h0; // @[Mux.scala 27:72]
wire [5:0] _T_226 = _T_218 | _T_219; // @[Mux.scala 27:72]
wire [5:0] _T_220 = io_i0_ap_sra ? _T_195 : 6'h0; // @[Mux.scala 27:72]
wire [5:0] _T_227 = _T_226 | _T_220; // @[Mux.scala 27:72]
wire [5:0] _T_221 = io_i0_ap_rol ? _T_197 : 6'h0; // @[Mux.scala 27:72]
wire [5:0] _T_228 = _T_227 | _T_221; // @[Mux.scala 27:72]
wire [5:0] _T_222 = io_i0_ap_ror ? _T_195 : 6'h0; // @[Mux.scala 27:72]
wire [5:0] _T_229 = _T_228 | _T_222; // @[Mux.scala 27:72]
wire [5:0] _T_225 = io_i0_ap_sbext ? _T_195 : 6'h0; // @[Mux.scala 27:72]
wire [5:0] shift_amount = _T_229 | _T_225; // @[Mux.scala 27:72]
wire [62:0] shift_long = shift_extend >> shift_amount[4:0]; // @[exu_alu_ctl.scala 202:32]
wire [4:0] _T_238 = {io_i0_ap_sll,io_i0_ap_sll,io_i0_ap_sll,io_i0_ap_sll,io_i0_ap_sll}; // @[Cat.scala 29:58]
wire [4:0] _T_240 = _T_238 & io_b_in[4:0]; // @[exu_alu_ctl.scala 189:73]
wire [62:0] _T_241 = 63'hffffffff << _T_240; // @[exu_alu_ctl.scala 189:39]
wire [31:0] shift_mask = _T_241[31:0]; // @[exu_alu_ctl.scala 189:14]
wire [31:0] sout = shift_long[31:0] & shift_mask; // @[exu_alu_ctl.scala 204:34]
wire [31:0] _T_889 = _T_887 & sout; // @[exu_alu_ctl.scala 304:56]
wire [31:0] _T_890 = lout[31:0] | _T_889; // @[exu_alu_ctl.scala 304:31]
wire _T_841 = io_i0_ap_add | io_i0_ap_sub; // @[exu_alu_ctl.scala 294:44]
wire _T_843 = ~io_i0_ap_slt; // @[exu_alu_ctl.scala 294:71]
wire _T_844 = _T_841 & _T_843; // @[exu_alu_ctl.scala 294:69]
wire _T_845 = ~io_i0_ap_min; // @[exu_alu_ctl.scala 294:87]
wire _T_846 = _T_844 & _T_845; // @[exu_alu_ctl.scala 294:85]
wire _T_847 = ~io_i0_ap_max; // @[exu_alu_ctl.scala 294:97]
wire sel_adder = _T_846 & _T_847; // @[exu_alu_ctl.scala 294:95]
wire [31:0] _T_892 = sel_adder ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
wire [32:0] _T_57 = {1'h0,io_a_in}; // @[Cat.scala 29:58]
wire [31:0] _T_58 = ~io_b_in; // @[exu_alu_ctl.scala 146:74]
wire [32:0] _T_59 = {1'h0,_T_58}; // @[Cat.scala 29:58]
wire [32:0] _T_61 = _T_57 + _T_59; // @[exu_alu_ctl.scala 146:59]
wire [32:0] _T_62 = {32'h0,io_i0_ap_sub}; // @[Cat.scala 29:58]
wire [32:0] _T_64 = _T_61 + _T_62; // @[exu_alu_ctl.scala 146:84]
wire [32:0] _T_67 = {1'h0,io_b_in}; // @[Cat.scala 29:58]
wire [32:0] _T_69 = _T_98 + _T_67; // @[exu_alu_ctl.scala 146:139]
wire [32:0] _T_72 = _T_69 + _T_62; // @[exu_alu_ctl.scala 146:164]
wire [32:0] aout = io_i0_ap_sub ? _T_64 : _T_72; // @[exu_alu_ctl.scala 146:14]
wire [31:0] _T_894 = _T_892 & aout[31:0]; // @[exu_alu_ctl.scala 305:28]
wire [31:0] _T_895 = _T_890 | _T_894; // @[exu_alu_ctl.scala 304:71]
wire _T_848 = io_i0_ap_jal | io_pp_in_bits_pcall; // @[exu_alu_ctl.scala 295:44]
wire _T_849 = _T_848 | io_pp_in_bits_pja; // @[exu_alu_ctl.scala 295:66]
wire sel_pc = _T_849 | io_pp_in_bits_pret; // @[exu_alu_ctl.scala 295:86]
wire [31:0] _T_897 = sel_pc ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
wire [12:0] _T_853 = {io_dec_alu_dec_i0_br_immed_d,1'h0}; // @[Cat.scala 29:58]
wire [31:0] _T_852 = {io_dec_i0_pc_d,1'h0}; // @[Cat.scala 29:58]
wire [12:0] _T_856 = _T_852[12:1] + _T_853[12:1]; // @[lib.scala 68:31]
wire _T_865 = ~_T_856[12]; // @[lib.scala 72:28]
wire _T_866 = _T_853[12] ^ _T_865; // @[lib.scala 72:26]
wire [18:0] _T_877 = _T_866 ? _T_852[31:13] : 19'h0; // @[Mux.scala 27:72]
wire _T_869 = ~_T_853[12]; // @[lib.scala 73:20]
wire _T_871 = _T_869 & _T_856[12]; // @[lib.scala 73:26]
wire [18:0] _T_859 = _T_852[31:13] + 19'h1; // @[lib.scala 69:27]
wire [18:0] _T_878 = _T_871 ? _T_859 : 19'h0; // @[Mux.scala 27:72]
wire [18:0] _T_880 = _T_877 | _T_878; // @[Mux.scala 27:72]
wire _T_875 = _T_853[12] & _T_865; // @[lib.scala 74:26]
wire [18:0] _T_862 = _T_852[31:13] - 19'h1; // @[lib.scala 70:27]
wire [18:0] _T_879 = _T_875 ? _T_862 : 19'h0; // @[Mux.scala 27:72]
wire [18:0] _T_881 = _T_880 | _T_879; // @[Mux.scala 27:72]
wire [31:0] pcout = {_T_881,_T_856[11:0],1'h0}; // @[Cat.scala 29:58]
wire [31:0] _T_898 = _T_897 & pcout; // @[exu_alu_ctl.scala 306:28]
wire [31:0] _T_899 = _T_895 | _T_898; // @[exu_alu_ctl.scala 305:43]
wire [31:0] _T_901 = io_i0_ap_csr_write ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
wire [31:0] _T_902 = io_i0_ap_csr_imm ? $signed(io_b_in) : $signed(io_a_in); // @[exu_alu_ctl.scala 307:51]
wire [31:0] _T_903 = _T_901 & _T_902; // @[exu_alu_ctl.scala 307:34]
wire [31:0] _T_904 = _T_899 | _T_903; // @[exu_alu_ctl.scala 306:41]
wire _T_88 = ~io_i0_ap_unsign; // @[exu_alu_ctl.scala 154:30]
wire neg = aout[31]; // @[exu_alu_ctl.scala 153:34]
wire _T_75 = ~io_a_in[31]; // @[exu_alu_ctl.scala 149:14]
wire [31:0] bm = io_i0_ap_sub ? _T_58 : io_b_in; // @[exu_alu_ctl.scala 143:17]
wire _T_77 = ~bm[31]; // @[exu_alu_ctl.scala 149:29]
wire _T_78 = _T_75 & _T_77; // @[exu_alu_ctl.scala 149:27]
wire _T_80 = _T_78 & neg; // @[exu_alu_ctl.scala 149:37]
wire _T_83 = io_a_in[31] & bm[31]; // @[exu_alu_ctl.scala 149:66]
wire _T_85 = ~neg; // @[exu_alu_ctl.scala 149:78]
wire _T_86 = _T_83 & _T_85; // @[exu_alu_ctl.scala 149:76]
wire ov = _T_80 | _T_86; // @[exu_alu_ctl.scala 149:50]
wire _T_89 = neg ^ ov; // @[exu_alu_ctl.scala 154:54]
wire _T_90 = _T_88 & _T_89; // @[exu_alu_ctl.scala 154:47]
wire cout = aout[32]; // @[exu_alu_ctl.scala 147:18]
wire _T_91 = ~cout; // @[exu_alu_ctl.scala 154:84]
wire _T_92 = io_i0_ap_unsign & _T_91; // @[exu_alu_ctl.scala 154:82]
wire lt = _T_90 | _T_92; // @[exu_alu_ctl.scala 154:61]
wire slt_one = io_i0_ap_slt & lt; // @[exu_alu_ctl.scala 298:43]
wire [31:0] _T_905 = {31'h0,slt_one}; // @[Cat.scala 29:58]
wire [31:0] _T_906 = _T_904 | _T_905; // @[exu_alu_ctl.scala 307:59]
wire [31:0] _T_908 = io_i0_ap_sbext ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
wire [31:0] _T_910 = {31'h0,sout[0]}; // @[Cat.scala 29:58]
wire [31:0] _T_911 = _T_908 & _T_910; // @[exu_alu_ctl.scala 309:28]
wire [31:0] _T_912 = _T_906 | _T_911; // @[exu_alu_ctl.scala 308:56]
wire _T_547 = io_i0_ap_clz | io_i0_ap_ctz; // @[exu_alu_ctl.scala 221:52]
wire [5:0] _T_549 = _T_547 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12]
wire [31:0] _T_445 = io_i0_ap_clz ? $signed(io_a_in) : $signed(32'sh0); // @[Mux.scala 27:72]
wire [9:0] _T_416 = {io_a_in[0],io_a_in[1],io_a_in[2],io_a_in[3],io_a_in[4],io_a_in[5],io_a_in[6],io_a_in[7],io_a_in[8],io_a_in[9]}; // @[Cat.scala 29:58]
wire [18:0] _T_425 = {_T_416,io_a_in[10],io_a_in[11],io_a_in[12],io_a_in[13],io_a_in[14],io_a_in[15],io_a_in[16],io_a_in[17],io_a_in[18]}; // @[Cat.scala 29:58]
wire [27:0] _T_434 = {_T_425,io_a_in[19],io_a_in[20],io_a_in[21],io_a_in[22],io_a_in[23],io_a_in[24],io_a_in[25],io_a_in[26],io_a_in[27]}; // @[Cat.scala 29:58]
wire [31:0] bitmanip_a_reverse_ff = {_T_434,io_a_in[28],io_a_in[29],io_a_in[30],io_a_in[31]}; // @[Cat.scala 29:58]
wire [31:0] _T_444 = {_T_434,io_a_in[28],io_a_in[29],io_a_in[30],io_a_in[31]}; // @[Mux.scala 27:72]
wire [31:0] _T_446 = io_i0_ap_ctz ? $signed(_T_444) : $signed(32'sh0); // @[Mux.scala 27:72]
wire [31:0] bitmanip_lzd_in = $signed(_T_445) | $signed(_T_446); // @[Mux.scala 27:72]
wire [31:0] _T_451 = $signed(_T_445) | $signed(_T_446); // @[exu_alu_ctl.scala 219:75]
wire _T_452 = _T_451 == 32'h0; // @[exu_alu_ctl.scala 219:81]
wire _T_454 = bitmanip_lzd_in[31:1] == 31'h0; // @[exu_alu_ctl.scala 219:81]
wire _T_456 = bitmanip_lzd_in[31:2] == 30'h0; // @[exu_alu_ctl.scala 219:81]
wire _T_458 = bitmanip_lzd_in[31:3] == 29'h0; // @[exu_alu_ctl.scala 219:81]
wire _T_460 = bitmanip_lzd_in[31:4] == 28'h0; // @[exu_alu_ctl.scala 219:81]
wire _T_462 = bitmanip_lzd_in[31:5] == 27'h0; // @[exu_alu_ctl.scala 219:81]
wire _T_464 = bitmanip_lzd_in[31:6] == 26'h0; // @[exu_alu_ctl.scala 219:81]
wire _T_466 = bitmanip_lzd_in[31:7] == 25'h0; // @[exu_alu_ctl.scala 219:81]
wire _T_468 = bitmanip_lzd_in[31:8] == 24'h0; // @[exu_alu_ctl.scala 219:81]
wire _T_470 = bitmanip_lzd_in[31:9] == 23'h0; // @[exu_alu_ctl.scala 219:81]
wire _T_472 = bitmanip_lzd_in[31:10] == 22'h0; // @[exu_alu_ctl.scala 219:81]
wire _T_474 = bitmanip_lzd_in[31:11] == 21'h0; // @[exu_alu_ctl.scala 219:81]
wire _T_476 = bitmanip_lzd_in[31:12] == 20'h0; // @[exu_alu_ctl.scala 219:81]
wire _T_478 = bitmanip_lzd_in[31:13] == 19'h0; // @[exu_alu_ctl.scala 219:81]
wire _T_480 = bitmanip_lzd_in[31:14] == 18'h0; // @[exu_alu_ctl.scala 219:81]
wire _T_482 = bitmanip_lzd_in[31:15] == 17'h0; // @[exu_alu_ctl.scala 219:81]
wire _T_484 = bitmanip_lzd_in[31:16] == 16'h0; // @[exu_alu_ctl.scala 219:81]
wire _T_486 = bitmanip_lzd_in[31:17] == 15'h0; // @[exu_alu_ctl.scala 219:81]
wire _T_488 = bitmanip_lzd_in[31:18] == 14'h0; // @[exu_alu_ctl.scala 219:81]
wire _T_490 = bitmanip_lzd_in[31:19] == 13'h0; // @[exu_alu_ctl.scala 219:81]
wire _T_492 = bitmanip_lzd_in[31:20] == 12'h0; // @[exu_alu_ctl.scala 219:81]
wire _T_494 = bitmanip_lzd_in[31:21] == 11'h0; // @[exu_alu_ctl.scala 219:81]
wire _T_496 = bitmanip_lzd_in[31:22] == 10'h0; // @[exu_alu_ctl.scala 219:81]
wire _T_498 = bitmanip_lzd_in[31:23] == 9'h0; // @[exu_alu_ctl.scala 219:81]
wire _T_500 = bitmanip_lzd_in[31:24] == 8'h0; // @[exu_alu_ctl.scala 219:81]
wire _T_502 = bitmanip_lzd_in[31:25] == 7'h0; // @[exu_alu_ctl.scala 219:81]
wire _T_504 = bitmanip_lzd_in[31:26] == 6'h0; // @[exu_alu_ctl.scala 219:81]
wire _T_506 = bitmanip_lzd_in[31:27] == 5'h0; // @[exu_alu_ctl.scala 219:81]
wire _T_508 = bitmanip_lzd_in[31:28] == 4'h0; // @[exu_alu_ctl.scala 219:81]
wire _T_510 = bitmanip_lzd_in[31:29] == 3'h0; // @[exu_alu_ctl.scala 219:81]
wire _T_512 = bitmanip_lzd_in[31:30] == 2'h0; // @[exu_alu_ctl.scala 219:81]
wire _T_514 = ~bitmanip_lzd_in[31]; // @[exu_alu_ctl.scala 219:81]
wire [1:0] _T_516 = _T_512 ? 2'h2 : {{1'd0}, _T_514}; // @[Mux.scala 98:16]
wire [1:0] _T_517 = _T_510 ? 2'h3 : _T_516; // @[Mux.scala 98:16]
wire [2:0] _T_518 = _T_508 ? 3'h4 : {{1'd0}, _T_517}; // @[Mux.scala 98:16]
wire [2:0] _T_519 = _T_506 ? 3'h5 : _T_518; // @[Mux.scala 98:16]
wire [2:0] _T_520 = _T_504 ? 3'h6 : _T_519; // @[Mux.scala 98:16]
wire [2:0] _T_521 = _T_502 ? 3'h7 : _T_520; // @[Mux.scala 98:16]
wire [3:0] _T_522 = _T_500 ? 4'h8 : {{1'd0}, _T_521}; // @[Mux.scala 98:16]
wire [3:0] _T_523 = _T_498 ? 4'h9 : _T_522; // @[Mux.scala 98:16]
wire [3:0] _T_524 = _T_496 ? 4'ha : _T_523; // @[Mux.scala 98:16]
wire [3:0] _T_525 = _T_494 ? 4'hb : _T_524; // @[Mux.scala 98:16]
wire [3:0] _T_526 = _T_492 ? 4'hc : _T_525; // @[Mux.scala 98:16]
wire [3:0] _T_527 = _T_490 ? 4'hd : _T_526; // @[Mux.scala 98:16]
wire [3:0] _T_528 = _T_488 ? 4'he : _T_527; // @[Mux.scala 98:16]
wire [3:0] _T_529 = _T_486 ? 4'hf : _T_528; // @[Mux.scala 98:16]
wire [4:0] _T_530 = _T_484 ? 5'h10 : {{1'd0}, _T_529}; // @[Mux.scala 98:16]
wire [4:0] _T_531 = _T_482 ? 5'h11 : _T_530; // @[Mux.scala 98:16]
wire [4:0] _T_532 = _T_480 ? 5'h12 : _T_531; // @[Mux.scala 98:16]
wire [4:0] _T_533 = _T_478 ? 5'h13 : _T_532; // @[Mux.scala 98:16]
wire [4:0] _T_534 = _T_476 ? 5'h14 : _T_533; // @[Mux.scala 98:16]
wire [4:0] _T_535 = _T_474 ? 5'h15 : _T_534; // @[Mux.scala 98:16]
wire [4:0] _T_536 = _T_472 ? 5'h16 : _T_535; // @[Mux.scala 98:16]
wire [4:0] _T_537 = _T_470 ? 5'h17 : _T_536; // @[Mux.scala 98:16]
wire [4:0] _T_538 = _T_468 ? 5'h18 : _T_537; // @[Mux.scala 98:16]
wire [4:0] _T_539 = _T_466 ? 5'h19 : _T_538; // @[Mux.scala 98:16]
wire [4:0] _T_540 = _T_464 ? 5'h1a : _T_539; // @[Mux.scala 98:16]
wire [4:0] _T_541 = _T_462 ? 5'h1b : _T_540; // @[Mux.scala 98:16]
wire [4:0] _T_542 = _T_460 ? 5'h1c : _T_541; // @[Mux.scala 98:16]
wire [4:0] _T_543 = _T_458 ? 5'h1d : _T_542; // @[Mux.scala 98:16]
wire [4:0] _T_544 = _T_456 ? 5'h1e : _T_543; // @[Mux.scala 98:16]
wire [4:0] _T_545 = _T_454 ? 5'h1f : _T_544; // @[Mux.scala 98:16]
wire [5:0] bitmanip_dw_lzd_enc = _T_452 ? 6'h20 : {{1'd0}, _T_545}; // @[Mux.scala 98:16]
wire [5:0] _GEN_8 = {{5'd0}, bitmanip_dw_lzd_enc[5]}; // @[exu_alu_ctl.scala 221:62]
wire [5:0] _T_551 = _T_549 & _GEN_8; // @[exu_alu_ctl.scala 221:62]
wire _T_553 = ~bitmanip_dw_lzd_enc[5]; // @[exu_alu_ctl.scala 221:96]
wire [4:0] _T_555 = _T_553 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12]
wire [4:0] _T_557 = _T_555 & bitmanip_dw_lzd_enc[4:0]; // @[exu_alu_ctl.scala 221:121]
wire [10:0] bitmanip_clz_ctz_result = {_T_551,_T_557}; // @[Cat.scala 29:58]
wire [31:0] _T_914 = {26'h0,bitmanip_clz_ctz_result[5:0]}; // @[Cat.scala 29:58]
wire [31:0] _T_915 = _T_912 | _T_914; // @[exu_alu_ctl.scala 309:56]
wire [5:0] _T_559 = io_i0_ap_pcnt ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12]
wire [1:0] _T_592 = io_a_in[0] + io_a_in[1]; // @[Bitwise.scala 47:55]
wire [1:0] _T_594 = io_a_in[2] + io_a_in[3]; // @[Bitwise.scala 47:55]
wire [2:0] _T_596 = _T_592 + _T_594; // @[Bitwise.scala 47:55]
wire [1:0] _T_598 = io_a_in[4] + io_a_in[5]; // @[Bitwise.scala 47:55]
wire [1:0] _T_600 = io_a_in[6] + io_a_in[7]; // @[Bitwise.scala 47:55]
wire [2:0] _T_602 = _T_598 + _T_600; // @[Bitwise.scala 47:55]
wire [3:0] _T_604 = _T_596 + _T_602; // @[Bitwise.scala 47:55]
wire [1:0] _T_606 = io_a_in[8] + io_a_in[9]; // @[Bitwise.scala 47:55]
wire [1:0] _T_608 = io_a_in[10] + io_a_in[11]; // @[Bitwise.scala 47:55]
wire [2:0] _T_610 = _T_606 + _T_608; // @[Bitwise.scala 47:55]
wire [1:0] _T_612 = io_a_in[12] + io_a_in[13]; // @[Bitwise.scala 47:55]
wire [1:0] _T_614 = io_a_in[14] + io_a_in[15]; // @[Bitwise.scala 47:55]
wire [2:0] _T_616 = _T_612 + _T_614; // @[Bitwise.scala 47:55]
wire [3:0] _T_618 = _T_610 + _T_616; // @[Bitwise.scala 47:55]
wire [4:0] _T_620 = _T_604 + _T_618; // @[Bitwise.scala 47:55]
wire [1:0] _T_622 = io_a_in[16] + io_a_in[17]; // @[Bitwise.scala 47:55]
wire [1:0] _T_624 = io_a_in[18] + io_a_in[19]; // @[Bitwise.scala 47:55]
wire [2:0] _T_626 = _T_622 + _T_624; // @[Bitwise.scala 47:55]
wire [1:0] _T_628 = io_a_in[20] + io_a_in[21]; // @[Bitwise.scala 47:55]
wire [1:0] _T_630 = io_a_in[22] + io_a_in[23]; // @[Bitwise.scala 47:55]
wire [2:0] _T_632 = _T_628 + _T_630; // @[Bitwise.scala 47:55]
wire [3:0] _T_634 = _T_626 + _T_632; // @[Bitwise.scala 47:55]
wire [1:0] _T_636 = io_a_in[24] + io_a_in[25]; // @[Bitwise.scala 47:55]
wire [1:0] _T_638 = io_a_in[26] + io_a_in[27]; // @[Bitwise.scala 47:55]
wire [2:0] _T_640 = _T_636 + _T_638; // @[Bitwise.scala 47:55]
wire [1:0] _T_642 = io_a_in[28] + io_a_in[29]; // @[Bitwise.scala 47:55]
wire [1:0] _T_644 = io_a_in[30] + io_a_in[31]; // @[Bitwise.scala 47:55]
wire [2:0] _T_646 = _T_642 + _T_644; // @[Bitwise.scala 47:55]
wire [3:0] _T_648 = _T_640 + _T_646; // @[Bitwise.scala 47:55]
wire [4:0] _T_650 = _T_634 + _T_648; // @[Bitwise.scala 47:55]
wire [5:0] _T_652 = _T_620 + _T_650; // @[Bitwise.scala 47:55]
wire [5:0] bitmanip_pcnt_result = _T_559 & _T_652; // @[exu_alu_ctl.scala 224:50]
wire [31:0] _T_917 = {26'h0,bitmanip_pcnt_result}; // @[Cat.scala 29:58]
wire [31:0] _T_918 = _T_915 | _T_917; // @[exu_alu_ctl.scala 310:52]
wire [23:0] _T_656 = io_a_in[7] ? 24'hffffff : 24'h0; // @[Bitwise.scala 72:12]
wire [31:0] _T_658 = {_T_656,io_a_in[7:0]}; // @[Cat.scala 29:58]
wire [31:0] _T_664 = io_i0_ap_sext_b ? _T_658 : 32'h0; // @[Mux.scala 27:72]
wire [15:0] _T_661 = io_a_in[15] ? 16'hffff : 16'h0; // @[Bitwise.scala 72:12]
wire [31:0] _T_663 = {_T_661,io_a_in[15:0]}; // @[Cat.scala 29:58]
wire [31:0] _T_665 = io_i0_ap_sext_h ? _T_663 : 32'h0; // @[Mux.scala 27:72]
wire [31:0] bitmanip_sext_result = _T_664 | _T_665; // @[Mux.scala 27:72]
wire [31:0] _T_920 = _T_918 | bitmanip_sext_result; // @[exu_alu_ctl.scala 311:52]
wire bitmanip_minmax_sel = io_i0_ap_min | io_i0_ap_max; // @[exu_alu_ctl.scala 233:46]
wire ge = ~lt; // @[exu_alu_ctl.scala 155:29]
wire bitmanip_minmax_sel_a = ge ^ io_i0_ap_min; // @[exu_alu_ctl.scala 235:43]
wire _T_667 = bitmanip_minmax_sel & bitmanip_minmax_sel_a; // @[exu_alu_ctl.scala 238:26]
wire [31:0] _T_677 = _T_667 ? $signed(io_a_in) : $signed(32'sh0); // @[Mux.scala 27:72]
wire _T_668 = ~bitmanip_minmax_sel_a; // @[exu_alu_ctl.scala 239:28]
wire _T_669 = bitmanip_minmax_sel & _T_668; // @[exu_alu_ctl.scala 239:26]
wire [31:0] _T_678 = _T_669 ? $signed(io_b_in) : $signed(32'sh0); // @[Mux.scala 27:72]
wire [31:0] _T_921 = $signed(_T_677) | $signed(_T_678); // @[exu_alu_ctl.scala 313:27]
wire [31:0] _T_922 = _T_920 | _T_921; // @[exu_alu_ctl.scala 312:35]
wire [31:0] _T_684 = io_i0_ap_pack ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
wire [31:0] _T_687 = {io_b_in[15:0],io_a_in[15:0]}; // @[Cat.scala 29:58]
wire [31:0] bitmanip_pack_result = _T_684 & _T_687; // @[exu_alu_ctl.scala 244:50]
wire [31:0] _T_924 = _T_922 | bitmanip_pack_result; // @[exu_alu_ctl.scala 313:35]
wire [31:0] _T_689 = io_i0_ap_packu ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
wire [31:0] _T_692 = {io_b_in[31:16],io_a_in[31:16]}; // @[Cat.scala 29:58]
wire [31:0] bitmanip_packu_result = _T_689 & _T_692; // @[exu_alu_ctl.scala 245:50]
wire [31:0] _T_926 = _T_924 | bitmanip_packu_result; // @[exu_alu_ctl.scala 314:35]
wire [31:0] _T_694 = io_i0_ap_packh ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
wire [31:0] _T_698 = {16'h0,io_b_in[7:0],io_a_in[7:0]}; // @[Cat.scala 29:58]
wire [31:0] bitmanip_packh_result = _T_694 & _T_698; // @[exu_alu_ctl.scala 246:50]
wire [31:0] _T_928 = _T_926 | bitmanip_packh_result; // @[exu_alu_ctl.scala 315:35]
wire [31:0] _T_700 = ap_rev ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
wire [31:0] bitmanip_rev_result = _T_700 & bitmanip_a_reverse_ff; // @[exu_alu_ctl.scala 252:48]
wire [31:0] _T_930 = _T_928 | bitmanip_rev_result; // @[exu_alu_ctl.scala 316:35]
wire [31:0] _T_765 = ap_rev8 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
wire [31:0] _T_772 = {io_a_in[7:0],io_a_in[15:8],io_a_in[23:16],io_a_in[31:24]}; // @[Cat.scala 29:58]
wire [31:0] bitmanip_rev8_result = _T_765 & _T_772; // @[exu_alu_ctl.scala 254:50]
wire [31:0] _T_932 = _T_930 | bitmanip_rev8_result; // @[exu_alu_ctl.scala 317:35]
wire [31:0] _T_774 = ap_orc_b ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
wire _T_788 = |io_a_in[31:24]; // @[exu_alu_ctl.scala 279:117]
wire [7:0] _T_790 = _T_788 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
wire _T_784 = |io_a_in[23:16]; // @[exu_alu_ctl.scala 279:117]
wire [7:0] _T_786 = _T_784 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
wire _T_780 = |io_a_in[15:8]; // @[exu_alu_ctl.scala 279:117]
wire [7:0] _T_782 = _T_780 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
wire _T_776 = |io_a_in[7:0]; // @[exu_alu_ctl.scala 279:117]
wire [7:0] _T_778 = _T_776 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
wire [31:0] _T_793 = {_T_790,_T_786,_T_782,_T_778}; // @[Cat.scala 29:58]
wire [31:0] bitmanip_orc_b_result = _T_774 & _T_793; // @[exu_alu_ctl.scala 279:50]
wire [31:0] _T_934 = _T_932 | bitmanip_orc_b_result; // @[exu_alu_ctl.scala 318:35]
wire [31:0] _T_795 = ap_orc16 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
wire [15:0] _T_798 = io_a_in[31:16] | io_a_in[15:0]; // @[exu_alu_ctl.scala 281:71]
wire [31:0] _T_802 = {_T_798,_T_798}; // @[Cat.scala 29:58]
wire [31:0] bitmanip_orc16_result = _T_795 & _T_802; // @[exu_alu_ctl.scala 281:50]
wire [31:0] _T_936 = _T_934 | bitmanip_orc16_result; // @[exu_alu_ctl.scala 319:35]
wire [62:0] bitmanip_sb_1hot = 63'h1 << io_b_in[4:0]; // @[exu_alu_ctl.scala 285:53]
wire [31:0] _T_805 = bitmanip_sb_1hot[31:0]; // @[exu_alu_ctl.scala 288:53]
wire [31:0] _T_820 = $signed(io_a_in) | $signed(_T_805); // @[Mux.scala 27:72]
wire [31:0] _T_827 = io_i0_ap_sbset ? $signed(_T_820) : $signed(32'sh0); // @[Mux.scala 27:72]
wire [31:0] _T_811 = ~_T_805; // @[exu_alu_ctl.scala 289:29]
wire [31:0] _T_823 = $signed(io_a_in) & $signed(_T_811); // @[Mux.scala 27:72]
wire [31:0] _T_828 = io_i0_ap_sbclr ? $signed(_T_823) : $signed(32'sh0); // @[Mux.scala 27:72]
wire [31:0] _T_831 = $signed(_T_827) | $signed(_T_828); // @[Mux.scala 27:72]
wire [31:0] _T_826 = $signed(io_a_in) ^ $signed(_T_805); // @[Mux.scala 27:72]
wire [31:0] _T_829 = io_i0_ap_sbinv ? $signed(_T_826) : $signed(32'sh0); // @[Mux.scala 27:72]
wire [31:0] _T_937 = $signed(_T_831) | $signed(_T_829); // @[exu_alu_ctl.scala 321:21]
wire [31:0] result = _T_936 | _T_937; // @[exu_alu_ctl.scala 320:35]
wire eq = $signed(io_a_in) == $signed(io_b_in); // @[exu_alu_ctl.scala 151:38]
wire ne = ~eq; // @[exu_alu_ctl.scala 152:29]
wire _T_941 = io_i0_ap_beq & eq; // @[exu_alu_ctl.scala 335:43]
wire _T_942 = io_i0_ap_bne & ne; // @[exu_alu_ctl.scala 335:65]
wire _T_943 = _T_941 | _T_942; // @[exu_alu_ctl.scala 335:49]
wire _T_944 = io_i0_ap_blt & lt; // @[exu_alu_ctl.scala 335:94]
wire _T_945 = _T_943 | _T_944; // @[exu_alu_ctl.scala 335:78]
wire _T_946 = io_i0_ap_bge & ge; // @[exu_alu_ctl.scala 335:116]
wire _T_947 = _T_945 | _T_946; // @[exu_alu_ctl.scala 335:100]
wire actual_taken = _T_947 | sel_pc; // @[exu_alu_ctl.scala 335:122]
wire _T_948 = io_dec_alu_dec_i0_alu_decode_d & io_i0_ap_predict_nt; // @[exu_alu_ctl.scala 340:61]
wire _T_949 = ~actual_taken; // @[exu_alu_ctl.scala 340:85]
wire _T_950 = _T_948 & _T_949; // @[exu_alu_ctl.scala 340:83]
wire _T_951 = ~sel_pc; // @[exu_alu_ctl.scala 340:101]
wire _T_952 = _T_950 & _T_951; // @[exu_alu_ctl.scala 340:99]
wire _T_953 = io_dec_alu_dec_i0_alu_decode_d & io_i0_ap_predict_t; // @[exu_alu_ctl.scala 340:145]
wire _T_954 = _T_953 & actual_taken; // @[exu_alu_ctl.scala 340:167]
wire _T_956 = _T_954 & _T_951; // @[exu_alu_ctl.scala 340:183]
wire _T_963 = io_i0_ap_predict_t & _T_949; // @[exu_alu_ctl.scala 345:48]
wire _T_964 = io_i0_ap_predict_nt & actual_taken; // @[exu_alu_ctl.scala 345:88]
wire cond_mispredict = _T_963 | _T_964; // @[exu_alu_ctl.scala 345:65]
wire _T_966 = io_pp_in_bits_prett != aout[31:1]; // @[exu_alu_ctl.scala 348:72]
wire target_mispredict = io_pp_in_bits_pret & _T_966; // @[exu_alu_ctl.scala 348:49]
wire _T_967 = io_i0_ap_jal | cond_mispredict; // @[exu_alu_ctl.scala 350:45]
wire _T_968 = _T_967 | target_mispredict; // @[exu_alu_ctl.scala 350:63]
wire _T_969 = _T_968 & io_dec_alu_dec_i0_alu_decode_d; // @[exu_alu_ctl.scala 350:84]
wire _T_970 = ~io_flush_upper_x; // @[exu_alu_ctl.scala 350:119]
wire _T_971 = _T_969 & _T_970; // @[exu_alu_ctl.scala 350:117]
wire _T_972 = ~io_dec_tlu_flush_lower_r; // @[exu_alu_ctl.scala 350:141]
wire _T_982 = io_pp_in_bits_hist[1] & io_pp_in_bits_hist[0]; // @[exu_alu_ctl.scala 355:44]
wire _T_984 = ~io_pp_in_bits_hist[0]; // @[exu_alu_ctl.scala 355:73]
wire _T_985 = _T_984 & actual_taken; // @[exu_alu_ctl.scala 355:96]
wire _T_986 = _T_982 | _T_985; // @[exu_alu_ctl.scala 355:70]
wire _T_988 = ~io_pp_in_bits_hist[1]; // @[exu_alu_ctl.scala 356:6]
wire _T_990 = _T_988 & _T_949; // @[exu_alu_ctl.scala 356:29]
wire _T_992 = io_pp_in_bits_hist[1] & actual_taken; // @[exu_alu_ctl.scala 356:72]
wire _T_993 = _T_990 | _T_992; // @[exu_alu_ctl.scala 356:47]
wire _T_997 = _T_970 & _T_972; // @[exu_alu_ctl.scala 359:56]
wire _T_998 = cond_mispredict | target_mispredict; // @[exu_alu_ctl.scala 359:103]
rvclkhdr rvclkhdr ( // @[lib.scala 399:23]
.io_clk(rvclkhdr_io_clk),
.io_en(rvclkhdr_io_en)
);
assign io_dec_alu_exu_i0_pc_x = _T_14; // @[exu_alu_ctl.scala 133:26]
assign io_result_ff = _T_18; // @[exu_alu_ctl.scala 135:16]
assign io_flush_upper_out = _T_971 & _T_972; // @[exu_alu_ctl.scala 350:26]
assign io_flush_final_out = _T_971 | io_dec_tlu_flush_lower_r; // @[exu_alu_ctl.scala 351:26]
assign io_flush_path_out = sel_pc ? aout[31:1] : pcout[31:1]; // @[exu_alu_ctl.scala 342:22]
assign io_pred_correct_out = _T_952 | _T_956; // @[exu_alu_ctl.scala 340:26]
assign io_predict_p_out_valid = io_pp_in_valid; // @[exu_alu_ctl.scala 358:30]
assign io_predict_p_out_bits_misp = _T_997 & _T_998; // @[exu_alu_ctl.scala 358:30 exu_alu_ctl.scala 359:35]
assign io_predict_p_out_bits_ataken = _T_947 | sel_pc; // @[exu_alu_ctl.scala 358:30 exu_alu_ctl.scala 360:35]
assign io_predict_p_out_bits_boffset = io_pp_in_bits_boffset; // @[exu_alu_ctl.scala 358:30]
assign io_predict_p_out_bits_pc4 = io_pp_in_bits_pc4; // @[exu_alu_ctl.scala 358:30]
assign io_predict_p_out_bits_hist = {_T_986,_T_993}; // @[exu_alu_ctl.scala 358:30 exu_alu_ctl.scala 361:35]
assign io_predict_p_out_bits_toffset = io_pp_in_bits_toffset; // @[exu_alu_ctl.scala 358:30]
assign io_predict_p_out_bits_br_error = io_pp_in_bits_br_error; // @[exu_alu_ctl.scala 358:30]
assign io_predict_p_out_bits_br_start_error = io_pp_in_bits_br_start_error; // @[exu_alu_ctl.scala 358:30]
assign io_predict_p_out_bits_prett = io_pp_in_bits_prett; // @[exu_alu_ctl.scala 358:30]
assign io_predict_p_out_bits_pcall = io_pp_in_bits_pcall; // @[exu_alu_ctl.scala 358:30]
assign io_predict_p_out_bits_pret = io_pp_in_bits_pret; // @[exu_alu_ctl.scala 358:30]
assign io_predict_p_out_bits_pja = io_pp_in_bits_pja; // @[exu_alu_ctl.scala 358:30]
assign io_predict_p_out_bits_way = io_pp_in_bits_way; // @[exu_alu_ctl.scala 358:30]
assign rvclkhdr_io_clk = clock; // @[lib.scala 401:18]
assign rvclkhdr_io_en = io_enable & io_dec_alu_dec_i0_alu_decode_d; // @[lib.scala 402:17]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
_T_14 = _RAND_0[30:0];
_RAND_1 = {1{`RANDOM}};
_T_18 = _RAND_1[31:0];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
_T_14 = 31'h0;
end
if (reset) begin
_T_18 = 32'h0;
end
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge clock or posedge reset) begin
if (reset) begin
_T_14 <= 31'h0;
end else if (io_enable) begin
_T_14 <= io_dec_i0_pc_d;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
_T_18 <= 32'h0;
end else if (_T_15) begin
_T_18 <= result;
end
end
endmodule

38
exu_div_ctl.anno.json
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@ -1,38 +0,0 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~exu_div_ctl|exu_div_ctl>io_exu_div_wren",
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"~exu_div_ctl|exu_div_ctl>io_dec_div_dec_div_cancel"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~exu_div_ctl|exu_div_ctl>io_exu_div_result",
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"~exu_div_ctl|exu_div_ctl>io_exu_div_wren",
"~exu_div_ctl|exu_div_ctl>io_dec_div_dec_div_cancel"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"exu_div_ctl.gated_latch",
"resourceId":"/vsrc/gated_latch.sv"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"exu_div_ctl"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

2835
exu_div_ctl.fir
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1243
exu_div_ctl.v
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23
exu_mul_ctl.anno.json
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@ -1,23 +0,0 @@
[
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"exu_mul_ctl.gated_latch",
"resourceId":"/vsrc/gated_latch.sv"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"exu_mul_ctl"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

40178
exu_mul_ctl.fir
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188
exu_mul_ctl.v
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@ -1,188 +0,0 @@
module rvclkhdr(
input io_clk,
input io_en
);
wire clkhdr_Q; // @[lib.scala 334:26]
wire clkhdr_CK; // @[lib.scala 334:26]
wire clkhdr_EN; // @[lib.scala 334:26]
wire clkhdr_SE; // @[lib.scala 334:26]
gated_latch clkhdr ( // @[lib.scala 334:26]
.Q(clkhdr_Q),
.CK(clkhdr_CK),
.EN(clkhdr_EN),
.SE(clkhdr_SE)
);
assign clkhdr_CK = io_clk; // @[lib.scala 336:18]
assign clkhdr_EN = io_en; // @[lib.scala 337:18]
assign clkhdr_SE = 1'h0; // @[lib.scala 338:18]
endmodule
module exu_mul_ctl(
input clock,
input reset,
input io_scan_mode,
input io_mul_p_valid,
input io_mul_p_bits_rs1_sign,
input io_mul_p_bits_rs2_sign,
input io_mul_p_bits_low,
input io_mul_p_bits_bext,
input io_mul_p_bits_bdep,
input io_mul_p_bits_clmul,
input io_mul_p_bits_clmulh,
input io_mul_p_bits_clmulr,
input io_mul_p_bits_grev,
input io_mul_p_bits_gorc,
input io_mul_p_bits_shfl,
input io_mul_p_bits_unshfl,
input io_mul_p_bits_crc32_b,
input io_mul_p_bits_crc32_h,
input io_mul_p_bits_crc32_w,
input io_mul_p_bits_crc32c_b,
input io_mul_p_bits_crc32c_h,
input io_mul_p_bits_crc32c_w,
input io_mul_p_bits_bfp,
input [31:0] io_rs1_in,
input [31:0] io_rs2_in,
output [31:0] io_result_x
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [63:0] _RAND_1;
reg [63:0] _RAND_2;
`endif // RANDOMIZE_REG_INIT
wire rvclkhdr_io_clk; // @[lib.scala 399:23]
wire rvclkhdr_io_en; // @[lib.scala 399:23]
wire rvclkhdr_1_io_clk; // @[lib.scala 426:23]
wire rvclkhdr_1_io_en; // @[lib.scala 426:23]
wire rvclkhdr_2_io_clk; // @[lib.scala 426:23]
wire rvclkhdr_2_io_en; // @[lib.scala 426:23]
wire rvclkhdr_3_io_clk; // @[lib.scala 399:23]
wire rvclkhdr_3_io_en; // @[lib.scala 399:23]
wire rvclkhdr_4_io_clk; // @[lib.scala 399:23]
wire rvclkhdr_4_io_en; // @[lib.scala 399:23]
wire _T_1 = io_mul_p_bits_rs1_sign & io_rs1_in[31]; // @[exu_mul_ctl.scala 123:44]
wire [32:0] rs1_ext_in = {_T_1,io_rs1_in}; // @[exu_mul_ctl.scala 123:71]
wire _T_5 = io_mul_p_bits_rs2_sign & io_rs2_in[31]; // @[exu_mul_ctl.scala 124:44]
wire [32:0] rs2_ext_in = {_T_5,io_rs2_in}; // @[exu_mul_ctl.scala 124:71]
reg low_x; // @[Reg.scala 27:20]
reg [32:0] rs1_x; // @[Reg.scala 27:20]
reg [32:0] rs2_x; // @[Reg.scala 27:20]
wire [65:0] prod_x = $signed(rs1_x) * $signed(rs2_x); // @[exu_mul_ctl.scala 130:20]
wire _T_39758 = ~low_x; // @[exu_mul_ctl.scala 388:46]
wire [7:0] _T_39762 = {_T_39758,_T_39758,_T_39758,_T_39758,_T_39758,_T_39758,_T_39758,_T_39758}; // @[Cat.scala 29:58]
wire [15:0] _T_39763 = {_T_39758,_T_39758,_T_39758,_T_39758,_T_39758,_T_39758,_T_39758,_T_39758,_T_39762}; // @[Cat.scala 29:58]
wire [31:0] _T_39764 = {_T_39758,_T_39758,_T_39758,_T_39758,_T_39758,_T_39758,_T_39758,_T_39758,_T_39762,_T_39763}; // @[Cat.scala 29:58]
wire [31:0] _T_39766 = _T_39764 & prod_x[63:32]; // @[exu_mul_ctl.scala 388:54]
wire [7:0] _T_39771 = {low_x,low_x,low_x,low_x,low_x,low_x,low_x,low_x}; // @[Cat.scala 29:58]
wire [15:0] _T_39772 = {low_x,low_x,low_x,low_x,low_x,low_x,low_x,low_x,_T_39771}; // @[Cat.scala 29:58]
wire [31:0] _T_39773 = {low_x,low_x,low_x,low_x,low_x,low_x,low_x,low_x,_T_39771,_T_39772}; // @[Cat.scala 29:58]
wire [31:0] _T_39775 = _T_39773 & prod_x[31:0]; // @[exu_mul_ctl.scala 389:40]
rvclkhdr rvclkhdr ( // @[lib.scala 399:23]
.io_clk(rvclkhdr_io_clk),
.io_en(rvclkhdr_io_en)
);
rvclkhdr rvclkhdr_1 ( // @[lib.scala 426:23]
.io_clk(rvclkhdr_1_io_clk),
.io_en(rvclkhdr_1_io_en)
);
rvclkhdr rvclkhdr_2 ( // @[lib.scala 426:23]
.io_clk(rvclkhdr_2_io_clk),
.io_en(rvclkhdr_2_io_en)
);
rvclkhdr rvclkhdr_3 ( // @[lib.scala 399:23]
.io_clk(rvclkhdr_3_io_clk),
.io_en(rvclkhdr_3_io_en)
);
rvclkhdr rvclkhdr_4 ( // @[lib.scala 399:23]
.io_clk(rvclkhdr_4_io_clk),
.io_en(rvclkhdr_4_io_en)
);
assign io_result_x = _T_39766 | _T_39775; // @[exu_mul_ctl.scala 388:15]
assign rvclkhdr_io_clk = clock; // @[lib.scala 401:18]
assign rvclkhdr_io_en = io_mul_p_valid; // @[lib.scala 402:17]
assign rvclkhdr_1_io_clk = clock; // @[lib.scala 428:18]
assign rvclkhdr_1_io_en = io_mul_p_valid; // @[lib.scala 429:17]
assign rvclkhdr_2_io_clk = clock; // @[lib.scala 428:18]
assign rvclkhdr_2_io_en = io_mul_p_valid; // @[lib.scala 429:17]
assign rvclkhdr_3_io_clk = clock; // @[lib.scala 401:18]
assign rvclkhdr_3_io_en = io_mul_p_valid; // @[lib.scala 402:17]
assign rvclkhdr_4_io_clk = clock; // @[lib.scala 401:18]
assign rvclkhdr_4_io_en = io_mul_p_valid; // @[lib.scala 402:17]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
low_x = _RAND_0[0:0];
_RAND_1 = {2{`RANDOM}};
rs1_x = _RAND_1[32:0];
_RAND_2 = {2{`RANDOM}};
rs2_x = _RAND_2[32:0];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
low_x = 1'h0;
end
if (reset) begin
rs1_x = 33'sh0;
end
if (reset) begin
rs2_x = 33'sh0;
end
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge clock or posedge reset) begin
if (reset) begin
low_x <= 1'h0;
end else if (io_mul_p_valid) begin
low_x <= io_mul_p_bits_low;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
rs1_x <= 33'sh0;
end else if (io_mul_p_valid) begin
rs1_x <= rs1_ext_in;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
rs2_x <= 33'sh0;
end else if (io_mul_p_valid) begin
rs2_x <= rs2_ext_in;
end
end
endmodule

165
ifu_bp_ctl.anno.json
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@ -1,165 +0,0 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_inst_mask_f",
"sources":[
"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_hit_taken_f",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_bpred_disable",
"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_req_f",
"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_flush_leak_one_wb",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_way",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
"~ifu_bp_ctl|ifu_bp_ctl>io_exu_bp_exu_i0_br_index_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_hist0_f",
"sources":[
"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_bpred_disable",
"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_req_f",
"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_flush_leak_one_wb",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_way",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
"~ifu_bp_ctl|ifu_bp_ctl>io_exu_bp_exu_i0_br_index_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
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"sources":[
"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f",
"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_req_f",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_flush_leak_one_wb",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_way",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
"~ifu_bp_ctl|ifu_bp_ctl>io_exu_bp_exu_i0_br_index_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
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]
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]
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]
},
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]
},
{
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_way",
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]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"ifu_bp_ctl.gated_latch",
"resourceId":"/vsrc/gated_latch.sv"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"ifu_bp_ctl"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

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ifu_bp_ctl.fir
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ifu_bp_ctl.v
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122
ifu_ifc_ctl.anno.json
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@ -1,122 +0,0 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifc_dma_access_ok",
"sources":[
"~ifu_ifc_ctl|ifu_ifc_ctl>io_exu_flush_final",
"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifc_iccm_access_bf",
"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifc_fetch_req_bf",
"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifu_fb_consume2",
"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifu_fb_consume1",
"~ifu_ifc_ctl|ifu_ifc_ctl>io_dec_ifc_dec_tlu_flush_noredir_wb",
"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifc_fetch_addr_bf",
"~ifu_ifc_ctl|ifu_ifc_ctl>io_ic_write_stall",
"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifc_fetch_req_bf_raw",
"~ifu_ifc_ctl|ifu_ifc_ctl>io_ic_dma_active",
"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifu_bp_btb_target_f",
"~ifu_ifc_ctl|ifu_ifc_ctl>io_exu_flush_path_final",
"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifc_fetch_addr_f",
"~ifu_ifc_ctl|ifu_ifc_ctl>io_ic_hit_f",
"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifu_bp_hit_taken_f",
"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifc_fetch_req_f"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~ifu_ifc_ctl|ifu_ifc_ctl>io_dec_ifc_ifu_pmu_fetch_stall",
"sources":[
"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifc_fetch_req_bf_raw",
"~ifu_ifc_ctl|ifu_ifc_ctl>io_ic_dma_active",
"~ifu_ifc_ctl|ifu_ifc_ctl>io_exu_flush_final",
"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifu_fb_consume2",
"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifu_fb_consume1"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifc_fetch_req_bf",
"sources":[
"~ifu_ifc_ctl|ifu_ifc_ctl>io_dec_ifc_dec_tlu_flush_noredir_wb",
"~ifu_ifc_ctl|ifu_ifc_ctl>io_ic_write_stall",
"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifc_fetch_req_bf_raw",
"~ifu_ifc_ctl|ifu_ifc_ctl>io_ic_dma_active",
"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifu_fb_consume2",
"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifu_fb_consume1",
"~ifu_ifc_ctl|ifu_ifc_ctl>io_exu_flush_final",
"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifc_fetch_req_f",
"~ifu_ifc_ctl|ifu_ifc_ctl>io_ic_hit_f"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifc_fetch_addr_bf",
"sources":[
"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifu_bp_btb_target_f",
"~ifu_ifc_ctl|ifu_ifc_ctl>io_exu_flush_path_final",
"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifc_fetch_addr_f",
"~ifu_ifc_ctl|ifu_ifc_ctl>io_ic_hit_f",
"~ifu_ifc_ctl|ifu_ifc_ctl>io_exu_flush_final",
"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifu_bp_hit_taken_f",
"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifc_fetch_req_f"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifc_iccm_access_bf",
"sources":[
"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifc_fetch_addr_bf",
"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifu_bp_btb_target_f",
"~ifu_ifc_ctl|ifu_ifc_ctl>io_exu_flush_path_final",
"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifc_fetch_addr_f",
"~ifu_ifc_ctl|ifu_ifc_ctl>io_ic_hit_f",
"~ifu_ifc_ctl|ifu_ifc_ctl>io_exu_flush_final",
"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifu_bp_hit_taken_f",
"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifc_fetch_req_f"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifc_fetch_uncacheable_bf",
"sources":[
"~ifu_ifc_ctl|ifu_ifc_ctl>io_dec_ifc_dec_tlu_mrac_ff",
"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifc_fetch_addr_bf",
"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifu_bp_btb_target_f",
"~ifu_ifc_ctl|ifu_ifc_ctl>io_exu_flush_path_final",
"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifc_fetch_addr_f",
"~ifu_ifc_ctl|ifu_ifc_ctl>io_ic_hit_f",
"~ifu_ifc_ctl|ifu_ifc_ctl>io_exu_flush_final",
"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifu_bp_hit_taken_f",
"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifc_fetch_req_f"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifc_region_acc_fault_bf",
"sources":[
"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifc_fetch_addr_bf",
"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifu_bp_btb_target_f",
"~ifu_ifc_ctl|ifu_ifc_ctl>io_exu_flush_path_final",
"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifc_fetch_addr_f",
"~ifu_ifc_ctl|ifu_ifc_ctl>io_ic_hit_f",
"~ifu_ifc_ctl|ifu_ifc_ctl>io_exu_flush_final",
"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifu_bp_hit_taken_f",
"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifc_fetch_req_f"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"ifu_ifc_ctl"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

311
ifu_ifc_ctl.fir
View File

@ -1,311 +0,0 @@
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
circuit ifu_ifc_ctl :
module ifu_ifc_ctl :
input clock : Clock
input reset : AsyncReset
output io : {flip exu_flush_final : UInt<1>, flip exu_flush_path_final : UInt<31>, flip free_l2clk : Clock, flip scan_mode : UInt<1>, flip ic_hit_f : UInt<1>, flip ifu_ic_mb_empty : UInt<1>, flip ifu_fb_consume1 : UInt<1>, flip ifu_fb_consume2 : UInt<1>, flip ifu_bp_hit_taken_f : UInt<1>, flip ifu_bp_btb_target_f : UInt<31>, flip ic_dma_active : UInt<1>, flip ic_write_stall : UInt<1>, dec_ifc : {flip dec_tlu_flush_noredir_wb : UInt<1>, flip dec_tlu_mrac_ff : UInt<32>, ifu_pmu_fetch_stall : UInt<1>}, dma_ifc : {flip dma_iccm_stall_any : UInt<1>}, ifc_fetch_addr_f : UInt<31>, ifc_fetch_addr_bf : UInt<31>, ifc_fetch_req_f : UInt<1>, ifc_fetch_uncacheable_bf : UInt<1>, ifc_fetch_req_bf : UInt<1>, ifc_fetch_req_bf_raw : UInt<1>, ifc_iccm_access_bf : UInt<1>, ifc_region_acc_fault_bf : UInt<1>, ifc_dma_access_ok : UInt<1>}
wire fetch_addr_bf : UInt<31>
fetch_addr_bf <= UInt<1>("h00")
wire fetch_addr_next_0 : UInt<1>
fetch_addr_next_0 <= UInt<1>("h00")
wire fetch_addr_next : UInt<31>
fetch_addr_next <= UInt<1>("h00")
wire fb_write_ns : UInt<4>
fb_write_ns <= UInt<1>("h00")
wire fb_write_f : UInt<4>
fb_write_f <= UInt<1>("h00")
wire fb_full_f_ns : UInt<1>
fb_full_f_ns <= UInt<1>("h00")
wire fb_right : UInt<1>
fb_right <= UInt<1>("h00")
wire fb_right2 : UInt<1>
fb_right2 <= UInt<1>("h00")
wire fb_left : UInt<1>
fb_left <= UInt<1>("h00")
wire wfm : UInt<1>
wfm <= UInt<1>("h00")
wire idle : UInt<1>
idle <= UInt<1>("h00")
wire miss_f : UInt<1>
miss_f <= UInt<1>("h00")
wire miss_a : UInt<1>
miss_a <= UInt<1>("h00")
wire flush_fb : UInt<1>
flush_fb <= UInt<1>("h00")
wire mb_empty_mod : UInt<1>
mb_empty_mod <= UInt<1>("h00")
wire goto_idle : UInt<1>
goto_idle <= UInt<1>("h00")
wire leave_idle : UInt<1>
leave_idle <= UInt<1>("h00")
wire fetch_bf_en : UInt<1>
fetch_bf_en <= UInt<1>("h00")
wire line_wrap : UInt<1>
line_wrap <= UInt<1>("h00")
wire state : UInt<2>
state <= UInt<1>("h00")
wire dma_iccm_stall_any_f : UInt<1>
dma_iccm_stall_any_f <= UInt<1>("h00")
node dma_stall = or(io.ic_dma_active, dma_iccm_stall_any_f) @[ifu_ifc_ctl.scala 62:36]
wire _T : UInt<1>
_T <= UInt<1>("h00")
node _T_1 = xor(io.dma_ifc.dma_iccm_stall_any, _T) @[lib.scala 458:21]
node _T_2 = orr(_T_1) @[lib.scala 458:29]
reg _T_3 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_2 : @[Reg.scala 28:19]
_T_3 <= io.dma_ifc.dma_iccm_stall_any @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
_T <= _T_3 @[lib.scala 461:16]
dma_iccm_stall_any_f <= _T @[ifu_ifc_ctl.scala 64:24]
wire _T_4 : UInt
_T_4 <= UInt<1>("h00")
node _T_5 = xor(miss_f, _T_4) @[lib.scala 436:21]
node _T_6 = orr(_T_5) @[lib.scala 436:29]
reg _T_7 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_6 : @[Reg.scala 28:19]
_T_7 <= miss_f @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
_T_4 <= _T_7 @[lib.scala 439:16]
miss_a <= _T_4 @[ifu_ifc_ctl.scala 65:10]
node _T_8 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_ifc_ctl.scala 67:30]
node _T_9 = eq(io.ifc_fetch_req_f, UInt<1>("h00")) @[ifu_ifc_ctl.scala 67:53]
node _T_10 = eq(io.ic_hit_f, UInt<1>("h00")) @[ifu_ifc_ctl.scala 67:75]
node _T_11 = or(_T_9, _T_10) @[ifu_ifc_ctl.scala 67:73]
node _T_12 = and(_T_8, _T_11) @[ifu_ifc_ctl.scala 67:50]
node _T_13 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_ifc_ctl.scala 68:29]
node _T_14 = and(_T_13, io.ifc_fetch_req_f) @[ifu_ifc_ctl.scala 68:49]
node _T_15 = and(_T_14, io.ifu_bp_hit_taken_f) @[ifu_ifc_ctl.scala 68:70]
node _T_16 = and(_T_15, io.ic_hit_f) @[ifu_ifc_ctl.scala 68:94]
node _T_17 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_ifc_ctl.scala 69:30]
node _T_18 = and(_T_17, io.ifc_fetch_req_f) @[ifu_ifc_ctl.scala 69:50]
node _T_19 = eq(io.ifu_bp_hit_taken_f, UInt<1>("h00")) @[ifu_ifc_ctl.scala 69:73]
node _T_20 = and(_T_18, _T_19) @[ifu_ifc_ctl.scala 69:71]
node _T_21 = and(_T_20, io.ic_hit_f) @[ifu_ifc_ctl.scala 69:96]
node _T_22 = bits(io.exu_flush_final, 0, 0) @[ifu_ifc_ctl.scala 71:57]
node _T_23 = bits(_T_12, 0, 0) @[ifu_ifc_ctl.scala 72:23]
node _T_24 = bits(_T_16, 0, 0) @[ifu_ifc_ctl.scala 73:22]
node _T_25 = bits(_T_21, 0, 0) @[ifu_ifc_ctl.scala 74:23]
node _T_26 = mux(_T_22, io.exu_flush_path_final, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_27 = mux(_T_23, io.ifc_fetch_addr_f, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_28 = mux(_T_24, io.ifu_bp_btb_target_f, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_29 = mux(_T_25, fetch_addr_next, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_30 = or(_T_26, _T_27) @[Mux.scala 27:72]
node _T_31 = or(_T_30, _T_28) @[Mux.scala 27:72]
node _T_32 = or(_T_31, _T_29) @[Mux.scala 27:72]
wire _T_33 : UInt<31> @[Mux.scala 27:72]
_T_33 <= _T_32 @[Mux.scala 27:72]
io.ifc_fetch_addr_bf <= _T_33 @[ifu_ifc_ctl.scala 71:25]
node _T_34 = bits(io.ifc_fetch_addr_f, 30, 1) @[ifu_ifc_ctl.scala 84:42]
node _T_35 = add(_T_34, UInt<1>("h01")) @[ifu_ifc_ctl.scala 84:48]
node address_upper = tail(_T_35, 1) @[ifu_ifc_ctl.scala 84:48]
node _T_36 = bits(address_upper, 4, 4) @[ifu_ifc_ctl.scala 85:39]
node _T_37 = bits(io.ifc_fetch_addr_f, 5, 5) @[ifu_ifc_ctl.scala 85:84]
node _T_38 = xor(_T_36, _T_37) @[ifu_ifc_ctl.scala 85:63]
node _T_39 = eq(_T_38, UInt<1>("h00")) @[ifu_ifc_ctl.scala 85:24]
node _T_40 = bits(io.ifc_fetch_addr_f, 0, 0) @[ifu_ifc_ctl.scala 85:130]
node _T_41 = and(_T_39, _T_40) @[ifu_ifc_ctl.scala 85:109]
fetch_addr_next_0 <= _T_41 @[ifu_ifc_ctl.scala 85:21]
node _T_42 = cat(address_upper, fetch_addr_next_0) @[Cat.scala 29:58]
fetch_addr_next <= _T_42 @[ifu_ifc_ctl.scala 88:19]
node _T_43 = not(idle) @[ifu_ifc_ctl.scala 90:30]
io.ifc_fetch_req_bf_raw <= _T_43 @[ifu_ifc_ctl.scala 90:27]
node _T_44 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[ifu_ifc_ctl.scala 92:91]
node _T_45 = eq(_T_44, UInt<1>("h00")) @[ifu_ifc_ctl.scala 92:70]
node _T_46 = and(fb_full_f_ns, _T_45) @[ifu_ifc_ctl.scala 92:68]
node _T_47 = eq(_T_46, UInt<1>("h00")) @[ifu_ifc_ctl.scala 92:53]
node _T_48 = and(io.ifc_fetch_req_bf_raw, _T_47) @[ifu_ifc_ctl.scala 92:51]
node _T_49 = eq(dma_stall, UInt<1>("h00")) @[ifu_ifc_ctl.scala 93:5]
node _T_50 = and(_T_48, _T_49) @[ifu_ifc_ctl.scala 92:114]
node _T_51 = eq(io.ic_write_stall, UInt<1>("h00")) @[ifu_ifc_ctl.scala 93:18]
node _T_52 = and(_T_50, _T_51) @[ifu_ifc_ctl.scala 93:16]
node _T_53 = eq(io.dec_ifc.dec_tlu_flush_noredir_wb, UInt<1>("h00")) @[ifu_ifc_ctl.scala 93:39]
node _T_54 = and(_T_52, _T_53) @[ifu_ifc_ctl.scala 93:37]
io.ifc_fetch_req_bf <= _T_54 @[ifu_ifc_ctl.scala 92:23]
node _T_55 = or(io.exu_flush_final, io.ifc_fetch_req_f) @[ifu_ifc_ctl.scala 95:37]
fetch_bf_en <= _T_55 @[ifu_ifc_ctl.scala 95:15]
node _T_56 = eq(io.ic_hit_f, UInt<1>("h00")) @[ifu_ifc_ctl.scala 97:34]
node _T_57 = and(io.ifc_fetch_req_f, _T_56) @[ifu_ifc_ctl.scala 97:32]
node _T_58 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_ifc_ctl.scala 97:49]
node _T_59 = and(_T_57, _T_58) @[ifu_ifc_ctl.scala 97:47]
miss_f <= _T_59 @[ifu_ifc_ctl.scala 97:10]
node _T_60 = or(io.ifu_ic_mb_empty, io.exu_flush_final) @[ifu_ifc_ctl.scala 99:39]
node _T_61 = eq(dma_stall, UInt<1>("h00")) @[ifu_ifc_ctl.scala 99:63]
node _T_62 = and(_T_60, _T_61) @[ifu_ifc_ctl.scala 99:61]
node _T_63 = eq(miss_f, UInt<1>("h00")) @[ifu_ifc_ctl.scala 99:76]
node _T_64 = and(_T_62, _T_63) @[ifu_ifc_ctl.scala 99:74]
node _T_65 = eq(miss_a, UInt<1>("h00")) @[ifu_ifc_ctl.scala 99:86]
node _T_66 = and(_T_64, _T_65) @[ifu_ifc_ctl.scala 99:84]
mb_empty_mod <= _T_66 @[ifu_ifc_ctl.scala 99:16]
node _T_67 = and(io.exu_flush_final, io.dec_ifc.dec_tlu_flush_noredir_wb) @[ifu_ifc_ctl.scala 101:35]
goto_idle <= _T_67 @[ifu_ifc_ctl.scala 101:13]
node _T_68 = eq(io.dec_ifc.dec_tlu_flush_noredir_wb, UInt<1>("h00")) @[ifu_ifc_ctl.scala 103:38]
node _T_69 = and(io.exu_flush_final, _T_68) @[ifu_ifc_ctl.scala 103:36]
node _T_70 = and(_T_69, idle) @[ifu_ifc_ctl.scala 103:75]
leave_idle <= _T_70 @[ifu_ifc_ctl.scala 103:14]
node _T_71 = bits(state, 1, 1) @[ifu_ifc_ctl.scala 105:29]
node _T_72 = eq(_T_71, UInt<1>("h00")) @[ifu_ifc_ctl.scala 105:23]
node _T_73 = bits(state, 0, 0) @[ifu_ifc_ctl.scala 105:40]
node _T_74 = and(_T_72, _T_73) @[ifu_ifc_ctl.scala 105:33]
node _T_75 = and(_T_74, miss_f) @[ifu_ifc_ctl.scala 105:44]
node _T_76 = eq(goto_idle, UInt<1>("h00")) @[ifu_ifc_ctl.scala 105:55]
node _T_77 = and(_T_75, _T_76) @[ifu_ifc_ctl.scala 105:53]
node _T_78 = bits(state, 1, 1) @[ifu_ifc_ctl.scala 106:11]
node _T_79 = eq(mb_empty_mod, UInt<1>("h00")) @[ifu_ifc_ctl.scala 106:17]
node _T_80 = and(_T_78, _T_79) @[ifu_ifc_ctl.scala 106:15]
node _T_81 = eq(goto_idle, UInt<1>("h00")) @[ifu_ifc_ctl.scala 106:33]
node _T_82 = and(_T_80, _T_81) @[ifu_ifc_ctl.scala 106:31]
node next_state_1 = or(_T_77, _T_82) @[ifu_ifc_ctl.scala 105:67]
node _T_83 = eq(goto_idle, UInt<1>("h00")) @[ifu_ifc_ctl.scala 108:23]
node _T_84 = and(_T_83, leave_idle) @[ifu_ifc_ctl.scala 108:34]
node _T_85 = bits(state, 0, 0) @[ifu_ifc_ctl.scala 108:56]
node _T_86 = eq(goto_idle, UInt<1>("h00")) @[ifu_ifc_ctl.scala 108:62]
node _T_87 = and(_T_85, _T_86) @[ifu_ifc_ctl.scala 108:60]
node next_state_0 = or(_T_84, _T_87) @[ifu_ifc_ctl.scala 108:48]
node _T_88 = cat(next_state_1, next_state_0) @[Cat.scala 29:58]
wire _T_89 : UInt
_T_89 <= UInt<1>("h00")
node _T_90 = xor(_T_88, _T_89) @[lib.scala 436:21]
node _T_91 = orr(_T_90) @[lib.scala 436:29]
reg _T_92 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_91 : @[Reg.scala 28:19]
_T_92 <= _T_88 @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
_T_89 <= _T_92 @[lib.scala 439:16]
state <= _T_89 @[ifu_ifc_ctl.scala 110:9]
flush_fb <= io.exu_flush_final @[ifu_ifc_ctl.scala 112:12]
node _T_93 = eq(io.ifu_fb_consume2, UInt<1>("h00")) @[ifu_ifc_ctl.scala 115:38]
node _T_94 = and(io.ifu_fb_consume1, _T_93) @[ifu_ifc_ctl.scala 115:36]
node _T_95 = eq(io.ifc_fetch_req_f, UInt<1>("h00")) @[ifu_ifc_ctl.scala 115:61]
node _T_96 = or(_T_95, miss_f) @[ifu_ifc_ctl.scala 115:81]
node _T_97 = and(_T_94, _T_96) @[ifu_ifc_ctl.scala 115:58]
node _T_98 = and(io.ifu_fb_consume2, io.ifc_fetch_req_f) @[ifu_ifc_ctl.scala 116:25]
node _T_99 = or(_T_97, _T_98) @[ifu_ifc_ctl.scala 115:92]
fb_right <= _T_99 @[ifu_ifc_ctl.scala 115:12]
node _T_100 = not(io.ifc_fetch_req_f) @[ifu_ifc_ctl.scala 118:39]
node _T_101 = or(_T_100, miss_f) @[ifu_ifc_ctl.scala 118:59]
node _T_102 = and(io.ifu_fb_consume2, _T_101) @[ifu_ifc_ctl.scala 118:36]
fb_right2 <= _T_102 @[ifu_ifc_ctl.scala 118:13]
node _T_103 = or(io.ifu_fb_consume1, io.ifu_fb_consume2) @[ifu_ifc_ctl.scala 119:56]
node _T_104 = eq(_T_103, UInt<1>("h00")) @[ifu_ifc_ctl.scala 119:35]
node _T_105 = and(io.ifc_fetch_req_f, _T_104) @[ifu_ifc_ctl.scala 119:33]
node _T_106 = eq(miss_f, UInt<1>("h00")) @[ifu_ifc_ctl.scala 119:80]
node _T_107 = and(_T_105, _T_106) @[ifu_ifc_ctl.scala 119:78]
fb_left <= _T_107 @[ifu_ifc_ctl.scala 119:11]
node _T_108 = bits(flush_fb, 0, 0) @[ifu_ifc_ctl.scala 122:37]
node _T_109 = eq(flush_fb, UInt<1>("h00")) @[ifu_ifc_ctl.scala 123:6]
node _T_110 = and(_T_109, fb_right) @[ifu_ifc_ctl.scala 123:16]
node _T_111 = bits(_T_110, 0, 0) @[ifu_ifc_ctl.scala 123:28]
node _T_112 = bits(fb_write_f, 3, 1) @[ifu_ifc_ctl.scala 123:62]
node _T_113 = cat(UInt<1>("h00"), _T_112) @[Cat.scala 29:58]
node _T_114 = eq(flush_fb, UInt<1>("h00")) @[ifu_ifc_ctl.scala 124:6]
node _T_115 = and(_T_114, fb_right2) @[ifu_ifc_ctl.scala 124:16]
node _T_116 = bits(_T_115, 0, 0) @[ifu_ifc_ctl.scala 124:29]
node _T_117 = bits(fb_write_f, 3, 2) @[ifu_ifc_ctl.scala 124:63]
node _T_118 = cat(UInt<2>("h00"), _T_117) @[Cat.scala 29:58]
node _T_119 = eq(flush_fb, UInt<1>("h00")) @[ifu_ifc_ctl.scala 125:6]
node _T_120 = and(_T_119, fb_left) @[ifu_ifc_ctl.scala 125:16]
node _T_121 = bits(_T_120, 0, 0) @[ifu_ifc_ctl.scala 125:27]
node _T_122 = bits(fb_write_f, 2, 0) @[ifu_ifc_ctl.scala 125:51]
node _T_123 = cat(_T_122, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_124 = eq(flush_fb, UInt<1>("h00")) @[ifu_ifc_ctl.scala 126:6]
node _T_125 = eq(fb_right, UInt<1>("h00")) @[ifu_ifc_ctl.scala 126:18]
node _T_126 = and(_T_124, _T_125) @[ifu_ifc_ctl.scala 126:16]
node _T_127 = eq(fb_right2, UInt<1>("h00")) @[ifu_ifc_ctl.scala 126:30]
node _T_128 = and(_T_126, _T_127) @[ifu_ifc_ctl.scala 126:28]
node _T_129 = eq(fb_left, UInt<1>("h00")) @[ifu_ifc_ctl.scala 126:43]
node _T_130 = and(_T_128, _T_129) @[ifu_ifc_ctl.scala 126:41]
node _T_131 = bits(_T_130, 0, 0) @[ifu_ifc_ctl.scala 126:53]
node _T_132 = bits(fb_write_f, 3, 0) @[ifu_ifc_ctl.scala 126:73]
node _T_133 = mux(_T_108, UInt<4>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_134 = mux(_T_111, _T_113, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_135 = mux(_T_116, _T_118, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_136 = mux(_T_121, _T_123, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_137 = mux(_T_131, _T_132, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_138 = or(_T_133, _T_134) @[Mux.scala 27:72]
node _T_139 = or(_T_138, _T_135) @[Mux.scala 27:72]
node _T_140 = or(_T_139, _T_136) @[Mux.scala 27:72]
node _T_141 = or(_T_140, _T_137) @[Mux.scala 27:72]
wire _T_142 : UInt<4> @[Mux.scala 27:72]
_T_142 <= _T_141 @[Mux.scala 27:72]
fb_write_ns <= _T_142 @[ifu_ifc_ctl.scala 122:15]
node _T_143 = eq(state, UInt<2>("h00")) @[ifu_ifc_ctl.scala 129:17]
idle <= _T_143 @[ifu_ifc_ctl.scala 129:8]
node _T_144 = eq(state, UInt<2>("h03")) @[ifu_ifc_ctl.scala 130:16]
wfm <= _T_144 @[ifu_ifc_ctl.scala 130:7]
node _T_145 = bits(fb_write_ns, 3, 3) @[ifu_ifc_ctl.scala 132:30]
fb_full_f_ns <= _T_145 @[ifu_ifc_ctl.scala 132:16]
wire fb_full_f : UInt
fb_full_f <= UInt<1>("h00")
node _T_146 = xor(fb_full_f_ns, fb_full_f) @[lib.scala 436:21]
node _T_147 = orr(_T_146) @[lib.scala 436:29]
reg _T_148 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_147 : @[Reg.scala 28:19]
_T_148 <= fb_full_f_ns @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
fb_full_f <= _T_148 @[lib.scala 439:16]
wire _T_149 : UInt
_T_149 <= UInt<1>("h00")
node _T_150 = xor(fb_write_ns, _T_149) @[lib.scala 436:21]
node _T_151 = orr(_T_150) @[lib.scala 436:29]
reg _T_152 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_151 : @[Reg.scala 28:19]
_T_152 <= fb_write_ns @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
_T_149 <= _T_152 @[lib.scala 439:16]
fb_write_f <= _T_149 @[ifu_ifc_ctl.scala 134:16]
node _T_153 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[ifu_ifc_ctl.scala 137:40]
node _T_154 = or(_T_153, io.exu_flush_final) @[ifu_ifc_ctl.scala 137:61]
node _T_155 = eq(_T_154, UInt<1>("h00")) @[ifu_ifc_ctl.scala 137:19]
node _T_156 = and(fb_full_f, _T_155) @[ifu_ifc_ctl.scala 137:17]
node _T_157 = or(_T_156, dma_stall) @[ifu_ifc_ctl.scala 137:84]
node _T_158 = and(io.ifc_fetch_req_bf_raw, _T_157) @[ifu_ifc_ctl.scala 136:68]
node _T_159 = or(wfm, _T_158) @[ifu_ifc_ctl.scala 136:41]
io.dec_ifc.ifu_pmu_fetch_stall <= _T_159 @[ifu_ifc_ctl.scala 136:34]
node _T_160 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_161 = bits(_T_160, 31, 28) @[lib.scala 84:25]
node iccm_acc_in_region_bf = eq(_T_161, UInt<4>("h0e")) @[lib.scala 84:47]
node _T_162 = bits(_T_160, 31, 16) @[lib.scala 87:14]
node iccm_acc_in_range_bf = eq(_T_162, UInt<16>("h0ee00")) @[lib.scala 87:29]
io.ifc_iccm_access_bf <= iccm_acc_in_range_bf @[ifu_ifc_ctl.scala 142:25]
node _T_163 = eq(io.ifc_iccm_access_bf, UInt<1>("h00")) @[ifu_ifc_ctl.scala 143:30]
node _T_164 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[ifu_ifc_ctl.scala 144:39]
node _T_165 = eq(_T_164, UInt<1>("h00")) @[ifu_ifc_ctl.scala 144:18]
node _T_166 = and(fb_full_f, _T_165) @[ifu_ifc_ctl.scala 144:16]
node _T_167 = or(_T_163, _T_166) @[ifu_ifc_ctl.scala 143:53]
node _T_168 = eq(io.ifc_fetch_req_bf, UInt<1>("h00")) @[ifu_ifc_ctl.scala 145:13]
node _T_169 = and(wfm, _T_168) @[ifu_ifc_ctl.scala 145:11]
node _T_170 = or(_T_167, _T_169) @[ifu_ifc_ctl.scala 144:62]
node _T_171 = or(_T_170, idle) @[ifu_ifc_ctl.scala 145:35]
node _T_172 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_ifc_ctl.scala 145:46]
node _T_173 = and(_T_171, _T_172) @[ifu_ifc_ctl.scala 145:44]
node _T_174 = or(_T_173, dma_iccm_stall_any_f) @[ifu_ifc_ctl.scala 145:67]
io.ifc_dma_access_ok <= _T_174 @[ifu_ifc_ctl.scala 143:24]
node _T_175 = eq(iccm_acc_in_range_bf, UInt<1>("h00")) @[ifu_ifc_ctl.scala 147:33]
node _T_176 = and(_T_175, iccm_acc_in_region_bf) @[ifu_ifc_ctl.scala 147:55]
io.ifc_region_acc_fault_bf <= _T_176 @[ifu_ifc_ctl.scala 147:30]
node _T_177 = bits(io.ifc_fetch_addr_bf, 30, 27) @[ifu_ifc_ctl.scala 148:86]
node _T_178 = cat(_T_177, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_179 = dshr(io.dec_ifc.dec_tlu_mrac_ff, _T_178) @[ifu_ifc_ctl.scala 148:61]
node _T_180 = bits(_T_179, 0, 0) @[ifu_ifc_ctl.scala 148:61]
node _T_181 = not(_T_180) @[ifu_ifc_ctl.scala 148:34]
io.ifc_fetch_uncacheable_bf <= _T_181 @[ifu_ifc_ctl.scala 148:31]
wire _T_182 : UInt<1>
_T_182 <= UInt<1>("h00")
node _T_183 = xor(io.ifc_fetch_req_bf, _T_182) @[lib.scala 458:21]
node _T_184 = orr(_T_183) @[lib.scala 458:29]
reg _T_185 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_184 : @[Reg.scala 28:19]
_T_185 <= io.ifc_fetch_req_bf @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
_T_182 <= _T_185 @[lib.scala 461:16]
io.ifc_fetch_req_f <= _T_182 @[ifu_ifc_ctl.scala 150:22]
node _T_186 = or(io.exu_flush_final, io.ifc_fetch_req_f) @[ifu_ifc_ctl.scala 152:76]
wire _T_187 : UInt<31> @[lib.scala 593:38]
_T_187 <= UInt<1>("h00") @[lib.scala 593:38]
reg _T_188 : UInt, clock with : (reset => (reset, _T_187)) @[Reg.scala 27:20]
when _T_186 : @[Reg.scala 28:19]
_T_188 <= io.ifc_fetch_addr_bf @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
io.ifc_fetch_addr_f <= _T_188 @[ifu_ifc_ctl.scala 152:23]

306
ifu_ifc_ctl.v
View File

@ -1,306 +0,0 @@
module ifu_ifc_ctl(
input clock,
input reset,
input io_exu_flush_final,
input [30:0] io_exu_flush_path_final,
input io_free_l2clk,
input io_scan_mode,
input io_ic_hit_f,
input io_ifu_ic_mb_empty,
input io_ifu_fb_consume1,
input io_ifu_fb_consume2,
input io_ifu_bp_hit_taken_f,
input [30:0] io_ifu_bp_btb_target_f,
input io_ic_dma_active,
input io_ic_write_stall,
input io_dec_ifc_dec_tlu_flush_noredir_wb,
input [31:0] io_dec_ifc_dec_tlu_mrac_ff,
output io_dec_ifc_ifu_pmu_fetch_stall,
input io_dma_ifc_dma_iccm_stall_any,
output [30:0] io_ifc_fetch_addr_f,
output [30:0] io_ifc_fetch_addr_bf,
output io_ifc_fetch_req_f,
output io_ifc_fetch_uncacheable_bf,
output io_ifc_fetch_req_bf,
output io_ifc_fetch_req_bf_raw,
output io_ifc_iccm_access_bf,
output io_ifc_region_acc_fault_bf,
output io_ifc_dma_access_ok
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
reg [31:0] _RAND_2;
reg [31:0] _RAND_3;
reg [31:0] _RAND_4;
reg [31:0] _RAND_5;
reg [31:0] _RAND_6;
`endif // RANDOMIZE_REG_INIT
reg dma_iccm_stall_any_f; // @[Reg.scala 27:20]
wire dma_stall = io_ic_dma_active | dma_iccm_stall_any_f; // @[ifu_ifc_ctl.scala 62:36]
wire _T_1 = io_dma_ifc_dma_iccm_stall_any ^ dma_iccm_stall_any_f; // @[lib.scala 458:21]
wire _T_2 = |_T_1; // @[lib.scala 458:29]
wire _T_56 = ~io_ic_hit_f; // @[ifu_ifc_ctl.scala 97:34]
wire _T_57 = io_ifc_fetch_req_f & _T_56; // @[ifu_ifc_ctl.scala 97:32]
wire _T_58 = ~io_exu_flush_final; // @[ifu_ifc_ctl.scala 97:49]
wire miss_f = _T_57 & _T_58; // @[ifu_ifc_ctl.scala 97:47]
reg miss_a; // @[Reg.scala 27:20]
wire _T_5 = miss_f ^ miss_a; // @[lib.scala 436:21]
wire _T_6 = |_T_5; // @[lib.scala 436:29]
wire _T_9 = ~io_ifc_fetch_req_f; // @[ifu_ifc_ctl.scala 67:53]
wire _T_11 = _T_9 | _T_56; // @[ifu_ifc_ctl.scala 67:73]
wire _T_12 = _T_58 & _T_11; // @[ifu_ifc_ctl.scala 67:50]
wire _T_14 = _T_58 & io_ifc_fetch_req_f; // @[ifu_ifc_ctl.scala 68:49]
wire _T_15 = _T_14 & io_ifu_bp_hit_taken_f; // @[ifu_ifc_ctl.scala 68:70]
wire _T_16 = _T_15 & io_ic_hit_f; // @[ifu_ifc_ctl.scala 68:94]
wire _T_19 = ~io_ifu_bp_hit_taken_f; // @[ifu_ifc_ctl.scala 69:73]
wire _T_20 = _T_14 & _T_19; // @[ifu_ifc_ctl.scala 69:71]
wire _T_21 = _T_20 & io_ic_hit_f; // @[ifu_ifc_ctl.scala 69:96]
wire [30:0] _T_26 = io_exu_flush_final ? io_exu_flush_path_final : 31'h0; // @[Mux.scala 27:72]
wire [30:0] _T_27 = _T_12 ? io_ifc_fetch_addr_f : 31'h0; // @[Mux.scala 27:72]
wire [30:0] _T_28 = _T_16 ? io_ifu_bp_btb_target_f : 31'h0; // @[Mux.scala 27:72]
wire [29:0] address_upper = io_ifc_fetch_addr_f[30:1] + 30'h1; // @[ifu_ifc_ctl.scala 84:48]
wire _T_38 = address_upper[4] ^ io_ifc_fetch_addr_f[5]; // @[ifu_ifc_ctl.scala 85:63]
wire _T_39 = ~_T_38; // @[ifu_ifc_ctl.scala 85:24]
wire fetch_addr_next_0 = _T_39 & io_ifc_fetch_addr_f[0]; // @[ifu_ifc_ctl.scala 85:109]
wire [30:0] fetch_addr_next = {address_upper,fetch_addr_next_0}; // @[Cat.scala 29:58]
wire [30:0] _T_29 = _T_21 ? fetch_addr_next : 31'h0; // @[Mux.scala 27:72]
wire [30:0] _T_30 = _T_26 | _T_27; // @[Mux.scala 27:72]
wire [30:0] _T_31 = _T_30 | _T_28; // @[Mux.scala 27:72]
reg [1:0] state; // @[Reg.scala 27:20]
wire idle = state == 2'h0; // @[ifu_ifc_ctl.scala 129:17]
wire _T_44 = io_ifu_fb_consume2 | io_ifu_fb_consume1; // @[ifu_ifc_ctl.scala 92:91]
wire _T_45 = ~_T_44; // @[ifu_ifc_ctl.scala 92:70]
wire [3:0] _T_133 = io_exu_flush_final ? 4'h1 : 4'h0; // @[Mux.scala 27:72]
wire _T_93 = ~io_ifu_fb_consume2; // @[ifu_ifc_ctl.scala 115:38]
wire _T_94 = io_ifu_fb_consume1 & _T_93; // @[ifu_ifc_ctl.scala 115:36]
wire _T_96 = _T_9 | miss_f; // @[ifu_ifc_ctl.scala 115:81]
wire _T_97 = _T_94 & _T_96; // @[ifu_ifc_ctl.scala 115:58]
wire _T_98 = io_ifu_fb_consume2 & io_ifc_fetch_req_f; // @[ifu_ifc_ctl.scala 116:25]
wire fb_right = _T_97 | _T_98; // @[ifu_ifc_ctl.scala 115:92]
wire _T_110 = _T_58 & fb_right; // @[ifu_ifc_ctl.scala 123:16]
reg [3:0] fb_write_f; // @[Reg.scala 27:20]
wire [3:0] _T_113 = {1'h0,fb_write_f[3:1]}; // @[Cat.scala 29:58]
wire [3:0] _T_134 = _T_110 ? _T_113 : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_138 = _T_133 | _T_134; // @[Mux.scala 27:72]
wire fb_right2 = io_ifu_fb_consume2 & _T_96; // @[ifu_ifc_ctl.scala 118:36]
wire _T_115 = _T_58 & fb_right2; // @[ifu_ifc_ctl.scala 124:16]
wire [3:0] _T_118 = {2'h0,fb_write_f[3:2]}; // @[Cat.scala 29:58]
wire [3:0] _T_135 = _T_115 ? _T_118 : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_139 = _T_138 | _T_135; // @[Mux.scala 27:72]
wire _T_103 = io_ifu_fb_consume1 | io_ifu_fb_consume2; // @[ifu_ifc_ctl.scala 119:56]
wire _T_104 = ~_T_103; // @[ifu_ifc_ctl.scala 119:35]
wire _T_105 = io_ifc_fetch_req_f & _T_104; // @[ifu_ifc_ctl.scala 119:33]
wire _T_106 = ~miss_f; // @[ifu_ifc_ctl.scala 119:80]
wire fb_left = _T_105 & _T_106; // @[ifu_ifc_ctl.scala 119:78]
wire _T_120 = _T_58 & fb_left; // @[ifu_ifc_ctl.scala 125:16]
wire [3:0] _T_123 = {fb_write_f[2:0],1'h0}; // @[Cat.scala 29:58]
wire [3:0] _T_136 = _T_120 ? _T_123 : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_140 = _T_139 | _T_136; // @[Mux.scala 27:72]
wire _T_125 = ~fb_right; // @[ifu_ifc_ctl.scala 126:18]
wire _T_126 = _T_58 & _T_125; // @[ifu_ifc_ctl.scala 126:16]
wire _T_127 = ~fb_right2; // @[ifu_ifc_ctl.scala 126:30]
wire _T_128 = _T_126 & _T_127; // @[ifu_ifc_ctl.scala 126:28]
wire _T_129 = ~fb_left; // @[ifu_ifc_ctl.scala 126:43]
wire _T_130 = _T_128 & _T_129; // @[ifu_ifc_ctl.scala 126:41]
wire [3:0] _T_137 = _T_130 ? fb_write_f : 4'h0; // @[Mux.scala 27:72]
wire [3:0] fb_write_ns = _T_140 | _T_137; // @[Mux.scala 27:72]
wire fb_full_f_ns = fb_write_ns[3]; // @[ifu_ifc_ctl.scala 132:30]
wire _T_46 = fb_full_f_ns & _T_45; // @[ifu_ifc_ctl.scala 92:68]
wire _T_47 = ~_T_46; // @[ifu_ifc_ctl.scala 92:53]
wire _T_48 = io_ifc_fetch_req_bf_raw & _T_47; // @[ifu_ifc_ctl.scala 92:51]
wire _T_49 = ~dma_stall; // @[ifu_ifc_ctl.scala 93:5]
wire _T_50 = _T_48 & _T_49; // @[ifu_ifc_ctl.scala 92:114]
wire _T_51 = ~io_ic_write_stall; // @[ifu_ifc_ctl.scala 93:18]
wire _T_52 = _T_50 & _T_51; // @[ifu_ifc_ctl.scala 93:16]
wire _T_53 = ~io_dec_ifc_dec_tlu_flush_noredir_wb; // @[ifu_ifc_ctl.scala 93:39]
wire fetch_bf_en = io_exu_flush_final | io_ifc_fetch_req_f; // @[ifu_ifc_ctl.scala 95:37]
wire _T_60 = io_ifu_ic_mb_empty | io_exu_flush_final; // @[ifu_ifc_ctl.scala 99:39]
wire _T_62 = _T_60 & _T_49; // @[ifu_ifc_ctl.scala 99:61]
wire _T_64 = _T_62 & _T_106; // @[ifu_ifc_ctl.scala 99:74]
wire _T_65 = ~miss_a; // @[ifu_ifc_ctl.scala 99:86]
wire mb_empty_mod = _T_64 & _T_65; // @[ifu_ifc_ctl.scala 99:84]
wire goto_idle = io_exu_flush_final & io_dec_ifc_dec_tlu_flush_noredir_wb; // @[ifu_ifc_ctl.scala 101:35]
wire _T_69 = io_exu_flush_final & _T_53; // @[ifu_ifc_ctl.scala 103:36]
wire leave_idle = _T_69 & idle; // @[ifu_ifc_ctl.scala 103:75]
wire _T_72 = ~state[1]; // @[ifu_ifc_ctl.scala 105:23]
wire _T_74 = _T_72 & state[0]; // @[ifu_ifc_ctl.scala 105:33]
wire _T_75 = _T_74 & miss_f; // @[ifu_ifc_ctl.scala 105:44]
wire _T_76 = ~goto_idle; // @[ifu_ifc_ctl.scala 105:55]
wire _T_77 = _T_75 & _T_76; // @[ifu_ifc_ctl.scala 105:53]
wire _T_79 = ~mb_empty_mod; // @[ifu_ifc_ctl.scala 106:17]
wire _T_80 = state[1] & _T_79; // @[ifu_ifc_ctl.scala 106:15]
wire _T_82 = _T_80 & _T_76; // @[ifu_ifc_ctl.scala 106:31]
wire next_state_1 = _T_77 | _T_82; // @[ifu_ifc_ctl.scala 105:67]
wire _T_84 = _T_76 & leave_idle; // @[ifu_ifc_ctl.scala 108:34]
wire _T_87 = state[0] & _T_76; // @[ifu_ifc_ctl.scala 108:60]
wire next_state_0 = _T_84 | _T_87; // @[ifu_ifc_ctl.scala 108:48]
wire [1:0] _T_88 = {next_state_1,next_state_0}; // @[Cat.scala 29:58]
wire [1:0] _T_90 = _T_88 ^ state; // @[lib.scala 436:21]
wire _T_91 = |_T_90; // @[lib.scala 436:29]
wire wfm = state == 2'h3; // @[ifu_ifc_ctl.scala 130:16]
reg fb_full_f; // @[Reg.scala 27:20]
wire _T_146 = fb_full_f_ns ^ fb_full_f; // @[lib.scala 436:21]
wire _T_147 = |_T_146; // @[lib.scala 436:29]
wire [3:0] _T_150 = fb_write_ns ^ fb_write_f; // @[lib.scala 436:21]
wire _T_151 = |_T_150; // @[lib.scala 436:29]
wire _T_154 = _T_44 | io_exu_flush_final; // @[ifu_ifc_ctl.scala 137:61]
wire _T_155 = ~_T_154; // @[ifu_ifc_ctl.scala 137:19]
wire _T_156 = fb_full_f & _T_155; // @[ifu_ifc_ctl.scala 137:17]
wire _T_157 = _T_156 | dma_stall; // @[ifu_ifc_ctl.scala 137:84]
wire _T_158 = io_ifc_fetch_req_bf_raw & _T_157; // @[ifu_ifc_ctl.scala 136:68]
wire [31:0] _T_160 = {io_ifc_fetch_addr_bf,1'h0}; // @[Cat.scala 29:58]
wire iccm_acc_in_region_bf = _T_160[31:28] == 4'he; // @[lib.scala 84:47]
wire iccm_acc_in_range_bf = _T_160[31:16] == 16'hee00; // @[lib.scala 87:29]
wire _T_163 = ~io_ifc_iccm_access_bf; // @[ifu_ifc_ctl.scala 143:30]
wire _T_166 = fb_full_f & _T_45; // @[ifu_ifc_ctl.scala 144:16]
wire _T_167 = _T_163 | _T_166; // @[ifu_ifc_ctl.scala 143:53]
wire _T_168 = ~io_ifc_fetch_req_bf; // @[ifu_ifc_ctl.scala 145:13]
wire _T_169 = wfm & _T_168; // @[ifu_ifc_ctl.scala 145:11]
wire _T_170 = _T_167 | _T_169; // @[ifu_ifc_ctl.scala 144:62]
wire _T_171 = _T_170 | idle; // @[ifu_ifc_ctl.scala 145:35]
wire _T_173 = _T_171 & _T_58; // @[ifu_ifc_ctl.scala 145:44]
wire _T_175 = ~iccm_acc_in_range_bf; // @[ifu_ifc_ctl.scala 147:33]
wire [4:0] _T_178 = {io_ifc_fetch_addr_bf[30:27],1'h0}; // @[Cat.scala 29:58]
wire [31:0] _T_179 = io_dec_ifc_dec_tlu_mrac_ff >> _T_178; // @[ifu_ifc_ctl.scala 148:61]
reg _T_185; // @[Reg.scala 27:20]
wire _T_183 = io_ifc_fetch_req_bf ^ _T_185; // @[lib.scala 458:21]
wire _T_184 = |_T_183; // @[lib.scala 458:29]
reg [30:0] _T_188; // @[Reg.scala 27:20]
assign io_dec_ifc_ifu_pmu_fetch_stall = wfm | _T_158; // @[ifu_ifc_ctl.scala 136:34]
assign io_ifc_fetch_addr_f = _T_188; // @[ifu_ifc_ctl.scala 152:23]
assign io_ifc_fetch_addr_bf = _T_31 | _T_29; // @[ifu_ifc_ctl.scala 71:25]
assign io_ifc_fetch_req_f = _T_185; // @[ifu_ifc_ctl.scala 150:22]
assign io_ifc_fetch_uncacheable_bf = ~_T_179[0]; // @[ifu_ifc_ctl.scala 148:31]
assign io_ifc_fetch_req_bf = _T_52 & _T_53; // @[ifu_ifc_ctl.scala 92:23]
assign io_ifc_fetch_req_bf_raw = ~idle; // @[ifu_ifc_ctl.scala 90:27]
assign io_ifc_iccm_access_bf = _T_160[31:16] == 16'hee00; // @[ifu_ifc_ctl.scala 142:25]
assign io_ifc_region_acc_fault_bf = _T_175 & iccm_acc_in_region_bf; // @[ifu_ifc_ctl.scala 147:30]
assign io_ifc_dma_access_ok = _T_173 | dma_iccm_stall_any_f; // @[ifu_ifc_ctl.scala 143:24]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
dma_iccm_stall_any_f = _RAND_0[0:0];
_RAND_1 = {1{`RANDOM}};
miss_a = _RAND_1[0:0];
_RAND_2 = {1{`RANDOM}};
state = _RAND_2[1:0];
_RAND_3 = {1{`RANDOM}};
fb_write_f = _RAND_3[3:0];
_RAND_4 = {1{`RANDOM}};
fb_full_f = _RAND_4[0:0];
_RAND_5 = {1{`RANDOM}};
_T_185 = _RAND_5[0:0];
_RAND_6 = {1{`RANDOM}};
_T_188 = _RAND_6[30:0];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
dma_iccm_stall_any_f = 1'h0;
end
if (reset) begin
miss_a = 1'h0;
end
if (reset) begin
state = 2'h0;
end
if (reset) begin
fb_write_f = 4'h0;
end
if (reset) begin
fb_full_f = 1'h0;
end
if (reset) begin
_T_185 = 1'h0;
end
if (reset) begin
_T_188 = 31'h0;
end
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge io_free_l2clk or posedge reset) begin
if (reset) begin
dma_iccm_stall_any_f <= 1'h0;
end else if (_T_2) begin
dma_iccm_stall_any_f <= io_dma_ifc_dma_iccm_stall_any;
end
end
always @(posedge io_free_l2clk or posedge reset) begin
if (reset) begin
miss_a <= 1'h0;
end else if (_T_6) begin
miss_a <= miss_f;
end
end
always @(posedge io_free_l2clk or posedge reset) begin
if (reset) begin
state <= 2'h0;
end else if (_T_91) begin
state <= _T_88;
end
end
always @(posedge io_free_l2clk or posedge reset) begin
if (reset) begin
fb_write_f <= 4'h0;
end else if (_T_151) begin
fb_write_f <= fb_write_ns;
end
end
always @(posedge io_free_l2clk or posedge reset) begin
if (reset) begin
fb_full_f <= 1'h0;
end else if (_T_147) begin
fb_full_f <= fb_full_f_ns;
end
end
always @(posedge io_free_l2clk or posedge reset) begin
if (reset) begin
_T_185 <= 1'h0;
end else if (_T_184) begin
_T_185 <= io_ifc_fetch_req_bf;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
_T_188 <= 31'h0;
end else if (fetch_bf_en) begin
_T_188 <= io_ifc_fetch_addr_bf;
end
end
endmodule

466
lsu.anno.json
View File

@ -1,466 +0,0 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn",
"sources":[
"~lsu|lsu>io_axi_ar_ready",
"~lsu|lsu>io_axi_aw_ready",
"~lsu|lsu>io_axi_w_ready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata",
"sources":[
"~lsu|lsu>io_dec_tlu_core_ecc_disable",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_single_ecc_error_incr",
"sources":[
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
"~lsu|lsu>io_dec_tlu_core_ecc_disable",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_dccm_rd_addr_hi",
"sources":[
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_dma_dccm_ready",
"sources":[
"~lsu|lsu>io_dec_lsu_valid_raw_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_dccm_wr_data_hi",
"sources":[
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_dword",
"~lsu|lsu>io_lsu_p_bits_half",
"~lsu|lsu>io_lsu_p_bits_word",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_wdata"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_dccm_wren",
"sources":[
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_dword",
"~lsu|lsu>io_lsu_p_bits_half",
"~lsu|lsu>io_lsu_p_bits_word",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~lsu|lsu>io_lsu_p_valid",
"~lsu|lsu>io_dec_tlu_flush_lower_r",
"~lsu|lsu>io_lsu_p_bits_fast_int",
"~lsu|lsu>io_lsu_p_bits_load",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~lsu|lsu>io_lsu_p_bits_store"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_dccm_wr_addr_hi",
"sources":[
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_dword",
"~lsu|lsu>io_lsu_p_bits_half",
"~lsu|lsu>io_lsu_p_bits_word"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy",
"sources":[
"~lsu|lsu>io_axi_ar_ready",
"~lsu|lsu>io_axi_aw_ready",
"~lsu|lsu>io_axi_w_ready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_pic_picm_rden",
"sources":[
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_dword",
"~lsu|lsu>io_lsu_p_bits_half",
"~lsu|lsu>io_lsu_p_bits_word",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~lsu|lsu>io_lsu_p_valid",
"~lsu|lsu>io_dec_tlu_flush_lower_r",
"~lsu|lsu>io_lsu_p_bits_fast_int",
"~lsu|lsu>io_lsu_p_bits_load",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_dccm_rd_addr_lo",
"sources":[
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_dccm_wr_addr_lo",
"sources":[
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu|lsu>io_lsu_p_bits_dword",
"~lsu|lsu>io_lsu_p_bits_half",
"~lsu|lsu>io_lsu_p_bits_word"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_fir_addr",
"sources":[
"~lsu|lsu>io_dec_tlu_core_ecc_disable",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_pic_picm_rdaddr",
"sources":[
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_pic_picm_wr_data",
"sources":[
"~lsu|lsu>io_lsu_dma_dma_dccm_ctl_dma_mem_wdata",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~lsu|lsu>io_dec_tlu_core_ecc_disable",
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_dword",
"~lsu|lsu>io_lsu_p_bits_half",
"~lsu|lsu>io_lsu_p_bits_word",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~lsu|lsu>io_lsu_p_valid",
"~lsu|lsu>io_dec_tlu_flush_lower_r",
"~lsu|lsu>io_lsu_p_bits_fast_int",
"~lsu|lsu>io_lsu_p_bits_load",
"~lsu|lsu>io_lsu_p_bits_store",
"~lsu|lsu>io_dccm_rd_data_lo"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_trigger_match_m",
"sources":[
"~lsu|lsu>io_trigger_pkt_any_0_store",
"~lsu|lsu>io_trigger_pkt_any_1_store",
"~lsu|lsu>io_trigger_pkt_any_3_m",
"~lsu|lsu>io_trigger_pkt_any_0_load",
"~lsu|lsu>io_trigger_pkt_any_0_select",
"~lsu|lsu>io_trigger_pkt_any_3_store",
"~lsu|lsu>io_trigger_pkt_any_2_store",
"~lsu|lsu>io_trigger_pkt_any_1_load",
"~lsu|lsu>io_trigger_pkt_any_1_select",
"~lsu|lsu>io_trigger_pkt_any_2_m",
"~lsu|lsu>io_trigger_pkt_any_3_load",
"~lsu|lsu>io_trigger_pkt_any_3_select",
"~lsu|lsu>io_trigger_pkt_any_2_load",
"~lsu|lsu>io_trigger_pkt_any_2_select",
"~lsu|lsu>io_trigger_pkt_any_0_m",
"~lsu|lsu>io_trigger_pkt_any_1_m",
"~lsu|lsu>io_trigger_pkt_any_0_tdata2",
"~lsu|lsu>io_trigger_pkt_any_0_match_pkt",
"~lsu|lsu>io_trigger_pkt_any_1_tdata2",
"~lsu|lsu>io_trigger_pkt_any_1_match_pkt",
"~lsu|lsu>io_trigger_pkt_any_3_tdata2",
"~lsu|lsu>io_trigger_pkt_any_3_match_pkt",
"~lsu|lsu>io_trigger_pkt_any_2_tdata2",
"~lsu|lsu>io_trigger_pkt_any_2_match_pkt",
"~lsu|lsu>io_lsu_pic_picm_rd_data"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_pic_picm_wren",
"sources":[
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_dword",
"~lsu|lsu>io_lsu_p_bits_half",
"~lsu|lsu>io_lsu_p_bits_word",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_result_corr_r",
"sources":[
"~lsu|lsu>io_dec_tlu_core_ecc_disable",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_store_stall_any",
"sources":[
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_dec_tlu_flush_lower_r",
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_fastint_stall_any",
"sources":[
"~lsu|lsu>io_dec_tlu_core_ecc_disable",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_pic_picm_wraddr",
"sources":[
"~lsu|lsu>io_lsu_dma_dma_dccm_ctl_dma_mem_addr",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_dword",
"~lsu|lsu>io_lsu_p_bits_half",
"~lsu|lsu>io_lsu_p_bits_word",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_fir_error",
"sources":[
"~lsu|lsu>io_dec_tlu_core_ecc_disable",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_dccm_rden",
"sources":[
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_dword",
"~lsu|lsu>io_lsu_p_bits_half",
"~lsu|lsu>io_lsu_p_bits_word",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~lsu|lsu>io_lsu_p_valid",
"~lsu|lsu>io_dec_tlu_flush_lower_r",
"~lsu|lsu>io_lsu_p_bits_fast_int",
"~lsu|lsu>io_lsu_p_bits_load",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~lsu|lsu>io_lsu_p_bits_store"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_pic_picm_mken",
"sources":[
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_dword",
"~lsu|lsu>io_lsu_p_bits_half",
"~lsu|lsu>io_lsu_p_bits_word",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~lsu|lsu>io_lsu_p_valid",
"~lsu|lsu>io_dec_tlu_flush_lower_r",
"~lsu|lsu>io_lsu_p_bits_fast_int",
"~lsu|lsu>io_lsu_p_bits_store",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned",
"sources":[
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error",
"sources":[
"~lsu|lsu>io_dec_tlu_core_ecc_disable",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_error_pkt_r_bits_single_ecc_error",
"sources":[
"~lsu|lsu>io_dec_tlu_core_ecc_disable",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r",
"sources":[
"~lsu|lsu>io_dec_tlu_i0_kill_writeb_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_error_pkt_r_valid",
"sources":[
"~lsu|lsu>io_dec_tlu_core_ecc_disable",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_load_stall_any",
"sources":[
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_dec_tlu_flush_lower_r",
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_dccm_wr_data_lo",
"sources":[
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
"~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
"~lsu|lsu>io_dec_lsu_valid_raw_d",
"~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu|lsu>io_dec_lsu_offset_d",
"~lsu|lsu>io_lsu_p_bits_dword",
"~lsu|lsu>io_lsu_p_bits_half",
"~lsu|lsu>io_lsu_p_bits_word",
"~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_wdata"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_error_pkt_r_bits_mscause",
"sources":[
"~lsu|lsu>io_dec_tlu_core_ecc_disable",
"~lsu|lsu>io_dccm_rd_data_hi",
"~lsu|lsu>io_dccm_rd_data_lo"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu|lsu>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m",
"sources":[
"~lsu|lsu>io_dec_tlu_flush_lower_r",
"~lsu|lsu>io_dec_tlu_force_halt"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"lsu.gated_latch",
"resourceId":"/vsrc/gated_latch.sv"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"lsu"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

16496
lsu.fir
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File diff suppressed because it is too large Load Diff

11429
lsu.v
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File diff suppressed because it is too large Load Diff

393
lsu_dccm_ctl.anno.json
View File

@ -1,393 +0,0 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_wren",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_ld_single_ecc_error_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_wen",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_stbuf_commit_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_reqvld_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_dccm_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_valid",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_load",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_store",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_addr_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_end_addr_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_word",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_dword"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_stbuf_commit_any",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_reqvld_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_ld_single_ecc_error_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_dccm_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_wen",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_valid",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_load",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_store",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_addr_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_end_addr_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_word",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_dword"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_store_datafn_lo_r",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_data_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_stbuf_commit_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_lo_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_dccm_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_reqvld_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_addr_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_store_data_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_store",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_ld_single_ecc_error_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_dccm_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_wen",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_valid",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_word",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_load",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_by",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_half",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_store",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_end_addr_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_word",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_dword"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_wr_data_lo",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_ld_single_ecc_error_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_wen",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_ecc_lo_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_lo_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_ecc_hi_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_hi_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_wdata_ecc_lo",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_wdata_lo",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_ecc_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_data_any"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pic_picm_wr_data",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_pic_wen",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_ctl_dma_mem_wdata",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_store_datafn_lo_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_data_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_stbuf_commit_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_lo_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_dccm_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_reqvld_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_addr_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_store_data_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_store",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_ld_single_ecc_error_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_dccm_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_wen",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_valid",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_word",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_load",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_by",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_half",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_store",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_end_addr_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_word",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_dword"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pic_picm_wren",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_pic_wen",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_commit_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_pic_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_valid",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_store"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_wr_addr_hi",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_ld_single_ecc_error_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_wen",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_end_addr_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_addr_any"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_picm_mask_data_m",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pic_picm_rd_data"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_data_ecc_lo_m",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_rd_data_lo"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_rdata_lo_m",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_rd_data_lo"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pic_picm_rden",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_pic_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_valid",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_load"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_rdata_hi_m",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_rd_data_hi"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_store_datafn_hi_r",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_data_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_stbuf_commit_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_hi_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_dccm_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_reqvld_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_addr_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_store_data_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_store",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_ld_single_ecc_error_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_dccm_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_wen",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_valid",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_word",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_load",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_by",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_half",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_store",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_end_addr_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_word",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_dword"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_data_ecc_hi_m",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_rd_data_hi"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_ld_data_r",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_pic_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_dccm_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_rdata_hi_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_rdata_lo_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_store_data_lo_r",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_lo_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_store_data_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_store",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_word",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_by",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_half"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_rden",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_dccm_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_valid",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_load",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_store",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_word",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_dword",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pic_picm_wraddr",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_pic_wen",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_ctl_dma_mem_addr",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_wr_data_hi",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_ld_single_ecc_error_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_wen",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_ecc_hi_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_hi_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_ecc_lo_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_lo_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_wdata_ecc_hi",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_wdata_hi",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_ecc_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_data_any"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
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"~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_hi_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_store_data_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_store",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_word",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_by",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_half"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_rd_addr_lo",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pic_picm_mken",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_pic_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_valid",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_store"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_ctl_dccm_dma_rdata",
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"~lsu_dccm_ctl|lsu_dccm_ctl>io_ldst_dual_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_pic_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_dccm_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_hi_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_lo_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_wr_addr_lo",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_ld_single_ecc_error_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_wen",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_addr_any"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pic_picm_rdaddr",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_ctl_dccm_dma_ecc_error",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_double_ecc_error_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_ld_data_corr_r",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_pic_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_dccm_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_hi_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_lo_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_rd_addr_hi",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_end_addr_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_ld_single_ecc_error_r",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_double_ecc_error_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_load",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_single_ecc_error_lo_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_raw_fwd_lo_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_single_ecc_error_hi_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_raw_fwd_hi_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_ctl_dccm_dma_rvalid",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_dma",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_valid",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_load"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"lsu_dccm_ctl.gated_latch",
"resourceId":"/vsrc/gated_latch.sv"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"lsu_dccm_ctl"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

2435
lsu_dccm_ctl.fir
View File

File diff suppressed because it is too large Load Diff

1436
lsu_dccm_ctl.v
View File

File diff suppressed because it is too large Load Diff

372
lsu_lsc_ctl.anno.json
View File

@ -1,372 +0,0 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_store_data_m",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_result_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_picm_mask_data_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_store_data_bypass_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_addr_in_pic_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_word",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_ld_data_r",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_half",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_by",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_unsign"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_word",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_word",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_sz"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_load_ldst_bypass_d",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_fast_int",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_fast_int",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_addr_d",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_result_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_load_ldst_bypass_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_exu_exu_lsu_rs1_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_addr",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_offset_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_word",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_ld_data_r",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_half",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_by",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_unsign"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_end_addr_r",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_ldst_dual_r",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_addr_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_store",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_store",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_write"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_half",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_half",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_sz"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_fir_addr",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_ld_data_corr_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_end_addr_m",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_ldst_dual_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_addr_m"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_error_pkt_r_bits_mscause",
"sources":[
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]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_store_data_bypass_d",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_store_data_bypass_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_dma",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_dma",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_end_addr_d",
"sources":[
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"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_load_ldst_bypass_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_exu_exu_lsu_rs1_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_addr",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_word",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_ld_data_r",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_offset_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_half",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_by",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_unsign",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_dword",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_half",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_word",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_dword",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_half",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_word",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_sz"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_stack",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_stack",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_valid",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_dccm_req",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_valid",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_flush_m_up",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_fast_int"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_commit_r",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_dma",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_valid",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_flush_r",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_store",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_load"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_unsign",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_unsign",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_error_pkt_r_bits_addr",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_addr_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_fir_error",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_fast_int",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_double_ecc_error_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_error_pkt_r_bits_inst_type",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_store"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_result_m",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_word",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_ld_data_r",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_half",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_by",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_unsign"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_addr_in_dccm_d",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_result_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_load_ldst_bypass_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_exu_exu_lsu_rs1_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_addr",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_offset_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_word",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_ld_data_r",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_half",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_by",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_unsign",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_dword",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_half",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_word",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_dword",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_half",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_word",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_sz"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_error_pkt_r_valid",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_fast_int",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_valid",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_dma",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_double_ecc_error_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_load",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_load",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_write"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_single_ecc_error_incr",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_valid",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_single_ecc_error_r",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_commit_r",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_dma",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_double_ecc_error_r",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_flush_r",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_store",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_load"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_dword",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_dword",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_sz"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_by",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_by",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_sz"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_store_data_bypass_m",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_store_data_bypass_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_addr_in_pic_d",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_result_m",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_load_ldst_bypass_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_exu_exu_lsu_rs1_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_addr",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_load_ldst_bypass_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_offset_d",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_word",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_ld_data_r",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_half",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_by",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_unsign",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_dword",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_half",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_word",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_dword",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_half",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_word",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_sz"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_error_pkt_r_bits_single_ecc_error",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_single_ecc_error_r",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_dma",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_error_pkt_r_valid",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_fast_int",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_valid",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_double_ecc_error_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_result_corr_r",
"sources":[
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_word",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_ld_data_corr_r",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_half",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_by",
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_unsign"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"lsu_lsc_ctl.gated_latch",
"resourceId":"/vsrc/gated_latch.sv"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"lsu_lsc_ctl"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

926
lsu_lsc_ctl.fir
View File

@ -1,926 +0,0 @@
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
circuit lsu_lsc_ctl :
module lsu_addrcheck :
input clock : Clock
input reset : AsyncReset
output io : {flip lsu_c2_m_clk : Clock, flip start_addr_d : UInt<32>, flip end_addr_d : UInt<32>, flip lsu_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip dec_tlu_mrac_ff : UInt<32>, flip rs1_region_d : UInt<4>, flip rs1_d : UInt<32>, is_sideeffects_m : UInt<1>, addr_in_dccm_d : UInt<1>, addr_in_pic_d : UInt<1>, addr_external_d : UInt<1>, access_fault_d : UInt<1>, misaligned_fault_d : UInt<1>, exc_mscause_d : UInt<4>, fir_dccm_access_error_d : UInt<1>, fir_nondccm_access_error_d : UInt<1>, flip scan_mode : UInt<1>}
node _T = bits(io.start_addr_d, 31, 28) @[lib.scala 365:27]
node start_addr_in_dccm_region_d = eq(_T, UInt<4>("h0f")) @[lib.scala 365:49]
wire start_addr_in_dccm_d : UInt<1> @[lib.scala 366:26]
node _T_1 = bits(io.start_addr_d, 31, 16) @[lib.scala 370:24]
node _T_2 = eq(_T_1, UInt<16>("h0f004")) @[lib.scala 370:39]
start_addr_in_dccm_d <= _T_2 @[lib.scala 370:16]
node _T_3 = bits(io.end_addr_d, 31, 28) @[lib.scala 365:27]
node end_addr_in_dccm_region_d = eq(_T_3, UInt<4>("h0f")) @[lib.scala 365:49]
wire end_addr_in_dccm_d : UInt<1> @[lib.scala 366:26]
node _T_4 = bits(io.end_addr_d, 31, 16) @[lib.scala 370:24]
node _T_5 = eq(_T_4, UInt<16>("h0f004")) @[lib.scala 370:39]
end_addr_in_dccm_d <= _T_5 @[lib.scala 370:16]
wire addr_in_iccm : UInt<1>
addr_in_iccm <= UInt<1>("h00")
node _T_6 = bits(io.start_addr_d, 31, 28) @[lsu_addrcheck.scala 42:37]
node _T_7 = eq(_T_6, UInt<4>("h0e")) @[lsu_addrcheck.scala 42:45]
addr_in_iccm <= _T_7 @[lsu_addrcheck.scala 42:18]
node _T_8 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 50:89]
node _T_9 = bits(_T_8, 31, 28) @[lib.scala 365:27]
node start_addr_in_pic_region_d = eq(_T_9, UInt<4>("h0f")) @[lib.scala 365:49]
wire start_addr_in_pic_d : UInt<1> @[lib.scala 366:26]
node _T_10 = bits(_T_8, 31, 15) @[lib.scala 370:24]
node _T_11 = eq(_T_10, UInt<17>("h01e018")) @[lib.scala 370:39]
start_addr_in_pic_d <= _T_11 @[lib.scala 370:16]
node _T_12 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 52:83]
node _T_13 = bits(_T_12, 31, 28) @[lib.scala 365:27]
node end_addr_in_pic_region_d = eq(_T_13, UInt<4>("h0f")) @[lib.scala 365:49]
wire end_addr_in_pic_d : UInt<1> @[lib.scala 366:26]
node _T_14 = bits(_T_12, 31, 15) @[lib.scala 370:24]
node _T_15 = eq(_T_14, UInt<17>("h01e018")) @[lib.scala 370:39]
end_addr_in_pic_d <= _T_15 @[lib.scala 370:16]
node start_addr_dccm_or_pic = or(start_addr_in_dccm_region_d, start_addr_in_pic_region_d) @[lsu_addrcheck.scala 54:60]
node _T_16 = bits(io.rs1_region_d, 3, 0) @[lsu_addrcheck.scala 55:49]
node _T_17 = eq(_T_16, UInt<4>("h0f")) @[lsu_addrcheck.scala 55:55]
node _T_18 = and(_T_17, UInt<1>("h01")) @[lsu_addrcheck.scala 55:74]
node _T_19 = bits(io.rs1_region_d, 3, 0) @[lsu_addrcheck.scala 55:109]
node _T_20 = eq(_T_19, UInt<4>("h0f")) @[lsu_addrcheck.scala 55:115]
node base_reg_dccm_or_pic = or(_T_18, _T_20) @[lsu_addrcheck.scala 55:91]
node _T_21 = and(start_addr_in_dccm_d, end_addr_in_dccm_d) @[lsu_addrcheck.scala 56:57]
io.addr_in_dccm_d <= _T_21 @[lsu_addrcheck.scala 56:32]
node _T_22 = and(start_addr_in_pic_d, end_addr_in_pic_d) @[lsu_addrcheck.scala 57:56]
io.addr_in_pic_d <= _T_22 @[lsu_addrcheck.scala 57:32]
node _T_23 = or(start_addr_in_dccm_region_d, start_addr_in_pic_region_d) @[lsu_addrcheck.scala 59:63]
node _T_24 = not(_T_23) @[lsu_addrcheck.scala 59:33]
io.addr_external_d <= _T_24 @[lsu_addrcheck.scala 59:30]
node _T_25 = bits(io.start_addr_d, 31, 28) @[lsu_addrcheck.scala 60:51]
node csr_idx = cat(_T_25, UInt<1>("h01")) @[Cat.scala 29:58]
node _T_26 = dshr(io.dec_tlu_mrac_ff, csr_idx) @[lsu_addrcheck.scala 61:50]
node _T_27 = bits(_T_26, 0, 0) @[lsu_addrcheck.scala 61:50]
node _T_28 = or(start_addr_in_dccm_region_d, start_addr_in_pic_region_d) @[lsu_addrcheck.scala 61:92]
node _T_29 = or(_T_28, addr_in_iccm) @[lsu_addrcheck.scala 61:121]
node _T_30 = eq(_T_29, UInt<1>("h00")) @[lsu_addrcheck.scala 61:62]
node _T_31 = and(_T_27, _T_30) @[lsu_addrcheck.scala 61:60]
node _T_32 = and(_T_31, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 61:137]
node _T_33 = or(io.lsu_pkt_d.bits.store, io.lsu_pkt_d.bits.load) @[lsu_addrcheck.scala 61:185]
node is_sideeffects_d = and(_T_32, _T_33) @[lsu_addrcheck.scala 61:158]
node _T_34 = bits(io.start_addr_d, 1, 0) @[lsu_addrcheck.scala 62:74]
node _T_35 = eq(_T_34, UInt<1>("h00")) @[lsu_addrcheck.scala 62:80]
node _T_36 = and(io.lsu_pkt_d.bits.word, _T_35) @[lsu_addrcheck.scala 62:56]
node _T_37 = bits(io.start_addr_d, 0, 0) @[lsu_addrcheck.scala 62:134]
node _T_38 = eq(_T_37, UInt<1>("h00")) @[lsu_addrcheck.scala 62:138]
node _T_39 = and(io.lsu_pkt_d.bits.half, _T_38) @[lsu_addrcheck.scala 62:116]
node _T_40 = or(_T_36, _T_39) @[lsu_addrcheck.scala 62:90]
node is_aligned_d = or(_T_40, io.lsu_pkt_d.bits.by) @[lsu_addrcheck.scala 62:148]
node _T_41 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58]
node _T_42 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58]
node _T_43 = cat(_T_42, _T_41) @[Cat.scala 29:58]
node _T_44 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 29:58]
node _T_45 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 29:58]
node _T_46 = cat(_T_45, _T_44) @[Cat.scala 29:58]
node _T_47 = cat(_T_46, _T_43) @[Cat.scala 29:58]
node _T_48 = orr(_T_47) @[lsu_addrcheck.scala 66:99]
node _T_49 = eq(_T_48, UInt<1>("h00")) @[lsu_addrcheck.scala 65:33]
node _T_50 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 67:49]
node _T_51 = or(_T_50, UInt<31>("h07fffffff")) @[lsu_addrcheck.scala 67:56]
node _T_52 = or(UInt<1>("h00"), UInt<31>("h07fffffff")) @[lsu_addrcheck.scala 67:121]
node _T_53 = eq(_T_51, _T_52) @[lsu_addrcheck.scala 67:88]
node _T_54 = and(UInt<1>("h01"), _T_53) @[lsu_addrcheck.scala 67:30]
node _T_55 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 68:49]
node _T_56 = or(_T_55, UInt<30>("h03fffffff")) @[lsu_addrcheck.scala 68:56]
node _T_57 = or(UInt<32>("h0c0000000"), UInt<30>("h03fffffff")) @[lsu_addrcheck.scala 68:121]
node _T_58 = eq(_T_56, _T_57) @[lsu_addrcheck.scala 68:88]
node _T_59 = and(UInt<1>("h01"), _T_58) @[lsu_addrcheck.scala 68:30]
node _T_60 = or(_T_54, _T_59) @[lsu_addrcheck.scala 67:153]
node _T_61 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 69:49]
node _T_62 = or(_T_61, UInt<29>("h01fffffff")) @[lsu_addrcheck.scala 69:56]
node _T_63 = or(UInt<32>("h0a0000000"), UInt<29>("h01fffffff")) @[lsu_addrcheck.scala 69:121]
node _T_64 = eq(_T_62, _T_63) @[lsu_addrcheck.scala 69:88]
node _T_65 = and(UInt<1>("h01"), _T_64) @[lsu_addrcheck.scala 69:30]
node _T_66 = or(_T_60, _T_65) @[lsu_addrcheck.scala 68:153]
node _T_67 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 70:49]
node _T_68 = or(_T_67, UInt<28>("h0fffffff")) @[lsu_addrcheck.scala 70:56]
node _T_69 = or(UInt<32>("h080000000"), UInt<28>("h0fffffff")) @[lsu_addrcheck.scala 70:121]
node _T_70 = eq(_T_68, _T_69) @[lsu_addrcheck.scala 70:88]
node _T_71 = and(UInt<1>("h01"), _T_70) @[lsu_addrcheck.scala 70:30]
node _T_72 = or(_T_66, _T_71) @[lsu_addrcheck.scala 69:153]
node _T_73 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 71:49]
node _T_74 = or(_T_73, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 71:56]
node _T_75 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 71:121]
node _T_76 = eq(_T_74, _T_75) @[lsu_addrcheck.scala 71:88]
node _T_77 = and(UInt<1>("h00"), _T_76) @[lsu_addrcheck.scala 71:30]
node _T_78 = or(_T_72, _T_77) @[lsu_addrcheck.scala 70:153]
node _T_79 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 72:49]
node _T_80 = or(_T_79, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 72:56]
node _T_81 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 72:121]
node _T_82 = eq(_T_80, _T_81) @[lsu_addrcheck.scala 72:88]
node _T_83 = and(UInt<1>("h00"), _T_82) @[lsu_addrcheck.scala 72:30]
node _T_84 = or(_T_78, _T_83) @[lsu_addrcheck.scala 71:153]
node _T_85 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 73:49]
node _T_86 = or(_T_85, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 73:56]
node _T_87 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 73:121]
node _T_88 = eq(_T_86, _T_87) @[lsu_addrcheck.scala 73:88]
node _T_89 = and(UInt<1>("h00"), _T_88) @[lsu_addrcheck.scala 73:30]
node _T_90 = or(_T_84, _T_89) @[lsu_addrcheck.scala 72:153]
node _T_91 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 74:49]
node _T_92 = or(_T_91, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 74:56]
node _T_93 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 74:121]
node _T_94 = eq(_T_92, _T_93) @[lsu_addrcheck.scala 74:88]
node _T_95 = and(UInt<1>("h00"), _T_94) @[lsu_addrcheck.scala 74:30]
node _T_96 = or(_T_90, _T_95) @[lsu_addrcheck.scala 73:153]
node _T_97 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 76:48]
node _T_98 = or(_T_97, UInt<31>("h07fffffff")) @[lsu_addrcheck.scala 76:57]
node _T_99 = or(UInt<1>("h00"), UInt<31>("h07fffffff")) @[lsu_addrcheck.scala 76:122]
node _T_100 = eq(_T_98, _T_99) @[lsu_addrcheck.scala 76:89]
node _T_101 = and(UInt<1>("h01"), _T_100) @[lsu_addrcheck.scala 76:31]
node _T_102 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 77:49]
node _T_103 = or(_T_102, UInt<30>("h03fffffff")) @[lsu_addrcheck.scala 77:58]
node _T_104 = or(UInt<32>("h0c0000000"), UInt<30>("h03fffffff")) @[lsu_addrcheck.scala 77:123]
node _T_105 = eq(_T_103, _T_104) @[lsu_addrcheck.scala 77:90]
node _T_106 = and(UInt<1>("h01"), _T_105) @[lsu_addrcheck.scala 77:32]
node _T_107 = or(_T_101, _T_106) @[lsu_addrcheck.scala 76:154]
node _T_108 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 78:49]
node _T_109 = or(_T_108, UInt<29>("h01fffffff")) @[lsu_addrcheck.scala 78:58]
node _T_110 = or(UInt<32>("h0a0000000"), UInt<29>("h01fffffff")) @[lsu_addrcheck.scala 78:123]
node _T_111 = eq(_T_109, _T_110) @[lsu_addrcheck.scala 78:90]
node _T_112 = and(UInt<1>("h01"), _T_111) @[lsu_addrcheck.scala 78:32]
node _T_113 = or(_T_107, _T_112) @[lsu_addrcheck.scala 77:155]
node _T_114 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 79:49]
node _T_115 = or(_T_114, UInt<28>("h0fffffff")) @[lsu_addrcheck.scala 79:58]
node _T_116 = or(UInt<32>("h080000000"), UInt<28>("h0fffffff")) @[lsu_addrcheck.scala 79:123]
node _T_117 = eq(_T_115, _T_116) @[lsu_addrcheck.scala 79:90]
node _T_118 = and(UInt<1>("h01"), _T_117) @[lsu_addrcheck.scala 79:32]
node _T_119 = or(_T_113, _T_118) @[lsu_addrcheck.scala 78:155]
node _T_120 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 80:49]
node _T_121 = or(_T_120, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 80:58]
node _T_122 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 80:123]
node _T_123 = eq(_T_121, _T_122) @[lsu_addrcheck.scala 80:90]
node _T_124 = and(UInt<1>("h00"), _T_123) @[lsu_addrcheck.scala 80:32]
node _T_125 = or(_T_119, _T_124) @[lsu_addrcheck.scala 79:155]
node _T_126 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 81:49]
node _T_127 = or(_T_126, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 81:58]
node _T_128 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 81:123]
node _T_129 = eq(_T_127, _T_128) @[lsu_addrcheck.scala 81:90]
node _T_130 = and(UInt<1>("h00"), _T_129) @[lsu_addrcheck.scala 81:32]
node _T_131 = or(_T_125, _T_130) @[lsu_addrcheck.scala 80:155]
node _T_132 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 82:49]
node _T_133 = or(_T_132, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 82:58]
node _T_134 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 82:123]
node _T_135 = eq(_T_133, _T_134) @[lsu_addrcheck.scala 82:90]
node _T_136 = and(UInt<1>("h00"), _T_135) @[lsu_addrcheck.scala 82:32]
node _T_137 = or(_T_131, _T_136) @[lsu_addrcheck.scala 81:155]
node _T_138 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 83:49]
node _T_139 = or(_T_138, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 83:58]
node _T_140 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 83:123]
node _T_141 = eq(_T_139, _T_140) @[lsu_addrcheck.scala 83:90]
node _T_142 = and(UInt<1>("h00"), _T_141) @[lsu_addrcheck.scala 83:32]
node _T_143 = or(_T_137, _T_142) @[lsu_addrcheck.scala 82:155]
node _T_144 = and(_T_96, _T_143) @[lsu_addrcheck.scala 75:7]
node non_dccm_access_ok = or(_T_49, _T_144) @[lsu_addrcheck.scala 66:104]
node regpred_access_fault_d = xor(start_addr_dccm_or_pic, base_reg_dccm_or_pic) @[lsu_addrcheck.scala 85:57]
node _T_145 = bits(io.start_addr_d, 1, 0) @[lsu_addrcheck.scala 86:70]
node _T_146 = neq(_T_145, UInt<2>("h00")) @[lsu_addrcheck.scala 86:76]
node _T_147 = eq(io.lsu_pkt_d.bits.word, UInt<1>("h00")) @[lsu_addrcheck.scala 86:92]
node _T_148 = or(_T_146, _T_147) @[lsu_addrcheck.scala 86:90]
node picm_access_fault_d = and(io.addr_in_pic_d, _T_148) @[lsu_addrcheck.scala 86:51]
wire unmapped_access_fault_d : UInt<1>
unmapped_access_fault_d <= UInt<1>("h01")
wire mpu_access_fault_d : UInt<1>
mpu_access_fault_d <= UInt<1>("h01")
node _T_149 = or(start_addr_in_dccm_d, start_addr_in_pic_d) @[lsu_addrcheck.scala 91:87]
node _T_150 = eq(_T_149, UInt<1>("h00")) @[lsu_addrcheck.scala 91:64]
node _T_151 = and(start_addr_in_dccm_region_d, _T_150) @[lsu_addrcheck.scala 91:62]
node _T_152 = or(end_addr_in_dccm_d, end_addr_in_pic_d) @[lsu_addrcheck.scala 93:57]
node _T_153 = eq(_T_152, UInt<1>("h00")) @[lsu_addrcheck.scala 93:36]
node _T_154 = and(end_addr_in_dccm_region_d, _T_153) @[lsu_addrcheck.scala 93:34]
node _T_155 = or(_T_151, _T_154) @[lsu_addrcheck.scala 91:112]
node _T_156 = and(start_addr_in_dccm_d, end_addr_in_pic_d) @[lsu_addrcheck.scala 95:29]
node _T_157 = or(_T_155, _T_156) @[lsu_addrcheck.scala 93:85]
node _T_158 = and(start_addr_in_pic_d, end_addr_in_dccm_d) @[lsu_addrcheck.scala 97:29]
node _T_159 = or(_T_157, _T_158) @[lsu_addrcheck.scala 95:85]
unmapped_access_fault_d <= _T_159 @[lsu_addrcheck.scala 91:29]
node _T_160 = eq(start_addr_in_dccm_region_d, UInt<1>("h00")) @[lsu_addrcheck.scala 99:33]
node _T_161 = eq(non_dccm_access_ok, UInt<1>("h00")) @[lsu_addrcheck.scala 99:64]
node _T_162 = and(_T_160, _T_161) @[lsu_addrcheck.scala 99:62]
mpu_access_fault_d <= _T_162 @[lsu_addrcheck.scala 99:29]
node _T_163 = or(unmapped_access_fault_d, mpu_access_fault_d) @[lsu_addrcheck.scala 111:49]
node _T_164 = or(_T_163, picm_access_fault_d) @[lsu_addrcheck.scala 111:70]
node _T_165 = or(_T_164, regpred_access_fault_d) @[lsu_addrcheck.scala 111:92]
node _T_166 = and(_T_165, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 111:118]
node _T_167 = eq(io.lsu_pkt_d.bits.dma, UInt<1>("h00")) @[lsu_addrcheck.scala 111:141]
node _T_168 = and(_T_166, _T_167) @[lsu_addrcheck.scala 111:139]
io.access_fault_d <= _T_168 @[lsu_addrcheck.scala 111:21]
node _T_169 = bits(unmapped_access_fault_d, 0, 0) @[lsu_addrcheck.scala 112:60]
node _T_170 = bits(mpu_access_fault_d, 0, 0) @[lsu_addrcheck.scala 112:100]
node _T_171 = bits(regpred_access_fault_d, 0, 0) @[lsu_addrcheck.scala 112:144]
node _T_172 = bits(picm_access_fault_d, 0, 0) @[lsu_addrcheck.scala 112:185]
node _T_173 = mux(_T_172, UInt<4>("h06"), UInt<4>("h00")) @[lsu_addrcheck.scala 112:164]
node _T_174 = mux(_T_171, UInt<4>("h05"), _T_173) @[lsu_addrcheck.scala 112:120]
node _T_175 = mux(_T_170, UInt<4>("h03"), _T_174) @[lsu_addrcheck.scala 112:80]
node access_fault_mscause_d = mux(_T_169, UInt<4>("h02"), _T_175) @[lsu_addrcheck.scala 112:35]
node _T_176 = bits(io.start_addr_d, 31, 28) @[lsu_addrcheck.scala 113:53]
node _T_177 = bits(io.end_addr_d, 31, 28) @[lsu_addrcheck.scala 113:78]
node regcross_misaligned_fault_d = neq(_T_176, _T_177) @[lsu_addrcheck.scala 113:61]
node _T_178 = eq(is_aligned_d, UInt<1>("h00")) @[lsu_addrcheck.scala 114:59]
node sideeffect_misaligned_fault_d = and(is_sideeffects_d, _T_178) @[lsu_addrcheck.scala 114:57]
node _T_179 = and(sideeffect_misaligned_fault_d, io.addr_external_d) @[lsu_addrcheck.scala 115:90]
node _T_180 = or(regcross_misaligned_fault_d, _T_179) @[lsu_addrcheck.scala 115:57]
node _T_181 = and(_T_180, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 115:113]
node _T_182 = eq(io.lsu_pkt_d.bits.dma, UInt<1>("h00")) @[lsu_addrcheck.scala 115:136]
node _T_183 = and(_T_181, _T_182) @[lsu_addrcheck.scala 115:134]
io.misaligned_fault_d <= _T_183 @[lsu_addrcheck.scala 115:25]
node _T_184 = bits(sideeffect_misaligned_fault_d, 0, 0) @[lsu_addrcheck.scala 116:111]
node _T_185 = mux(_T_184, UInt<4>("h01"), UInt<4>("h00")) @[lsu_addrcheck.scala 116:80]
node misaligned_fault_mscause_d = mux(regcross_misaligned_fault_d, UInt<4>("h02"), _T_185) @[lsu_addrcheck.scala 116:39]
node _T_186 = bits(io.misaligned_fault_d, 0, 0) @[lsu_addrcheck.scala 117:50]
node _T_187 = bits(misaligned_fault_mscause_d, 3, 0) @[lsu_addrcheck.scala 117:84]
node _T_188 = bits(access_fault_mscause_d, 3, 0) @[lsu_addrcheck.scala 117:113]
node _T_189 = mux(_T_186, _T_187, _T_188) @[lsu_addrcheck.scala 117:27]
io.exc_mscause_d <= _T_189 @[lsu_addrcheck.scala 117:21]
node _T_190 = eq(start_addr_in_dccm_d, UInt<1>("h00")) @[lsu_addrcheck.scala 118:66]
node _T_191 = and(start_addr_in_dccm_region_d, _T_190) @[lsu_addrcheck.scala 118:64]
node _T_192 = eq(end_addr_in_dccm_d, UInt<1>("h00")) @[lsu_addrcheck.scala 118:120]
node _T_193 = and(end_addr_in_dccm_region_d, _T_192) @[lsu_addrcheck.scala 118:118]
node _T_194 = or(_T_191, _T_193) @[lsu_addrcheck.scala 118:88]
node _T_195 = and(_T_194, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 118:142]
node _T_196 = and(_T_195, io.lsu_pkt_d.bits.fast_int) @[lsu_addrcheck.scala 118:163]
io.fir_dccm_access_error_d <= _T_196 @[lsu_addrcheck.scala 118:31]
node _T_197 = and(start_addr_in_dccm_region_d, end_addr_in_dccm_region_d) @[lsu_addrcheck.scala 119:66]
node _T_198 = eq(_T_197, UInt<1>("h00")) @[lsu_addrcheck.scala 119:36]
node _T_199 = and(_T_198, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 119:95]
node _T_200 = and(_T_199, io.lsu_pkt_d.bits.fast_int) @[lsu_addrcheck.scala 119:116]
io.fir_nondccm_access_error_d <= _T_200 @[lsu_addrcheck.scala 119:33]
reg _T_201 : UInt<1>, io.lsu_c2_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_addrcheck.scala 121:60]
_T_201 <= is_sideeffects_d @[lsu_addrcheck.scala 121:60]
io.is_sideeffects_m <= _T_201 @[lsu_addrcheck.scala 121:50]
extmodule gated_latch :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch @[lib.scala 334:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
clkhdr.CK <= io.clk @[lib.scala 336:18]
clkhdr.EN <= io.en @[lib.scala 337:18]
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
extmodule gated_latch_1 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_1 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_1 @[lib.scala 334:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
clkhdr.CK <= io.clk @[lib.scala 336:18]
clkhdr.EN <= io.en @[lib.scala 337:18]
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
extmodule gated_latch_2 :
output Q : Clock
input CK : Clock
input EN : UInt<1>
input SE : UInt<1>
defname = gated_latch
module rvclkhdr_2 :
input clock : Clock
input reset : Reset
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
inst clkhdr of gated_latch_2 @[lib.scala 334:26]
clkhdr.SE is invalid
clkhdr.EN is invalid
clkhdr.CK is invalid
clkhdr.Q is invalid
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
clkhdr.CK <= io.clk @[lib.scala 336:18]
clkhdr.EN <= io.en @[lib.scala 337:18]
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
module lsu_lsc_ctl :
input clock : Clock
input reset : AsyncReset
output io : {flip clk_override : UInt<1>, flip lsu_c1_m_clk : Clock, flip lsu_c1_r_clk : Clock, flip lsu_c2_m_clk : Clock, flip lsu_c2_r_clk : Clock, flip lsu_store_c1_m_clk : Clock, flip lsu_ld_data_r : UInt<32>, flip lsu_ld_data_corr_r : UInt<32>, flip lsu_single_ecc_error_r : UInt<1>, flip lsu_double_ecc_error_r : UInt<1>, flip lsu_ld_data_m : UInt<32>, flip lsu_single_ecc_error_m : UInt<1>, flip lsu_double_ecc_error_m : UInt<1>, flip flush_m_up : UInt<1>, flip flush_r : UInt<1>, flip ldst_dual_d : UInt<1>, flip ldst_dual_m : UInt<1>, flip ldst_dual_r : UInt<1>, lsu_exu : {flip exu_lsu_rs1_d : UInt<32>, flip exu_lsu_rs2_d : UInt<32>}, flip lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip dec_lsu_valid_raw_d : UInt<1>, flip dec_lsu_offset_d : UInt<12>, flip picm_mask_data_m : UInt<32>, flip bus_read_data_m : UInt<32>, lsu_result_m : UInt<32>, lsu_result_corr_r : UInt<32>, lsu_addr_d : UInt<32>, lsu_addr_m : UInt<32>, lsu_addr_r : UInt<32>, end_addr_d : UInt<32>, end_addr_m : UInt<32>, end_addr_r : UInt<32>, store_data_m : UInt<32>, flip dec_tlu_mrac_ff : UInt<32>, lsu_exc_m : UInt<1>, is_sideeffects_m : UInt<1>, lsu_commit_r : UInt<1>, lsu_single_ecc_error_incr : UInt<1>, lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, lsu_fir_addr : UInt<31>, lsu_fir_error : UInt<2>, addr_in_dccm_d : UInt<1>, addr_in_dccm_m : UInt<1>, addr_in_dccm_r : UInt<1>, addr_in_pic_d : UInt<1>, addr_in_pic_m : UInt<1>, addr_in_pic_r : UInt<1>, addr_external_m : UInt<1>, dma_lsc_ctl : {flip dma_dccm_req : UInt<1>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_write : UInt<1>, flip dma_mem_wdata : UInt<64>}, lsu_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, lsu_pkt_r : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip scan_mode : UInt<1>}
wire end_addr_pre_m : UInt<29>
end_addr_pre_m <= UInt<29>("h00")
wire end_addr_pre_r : UInt<29>
end_addr_pre_r <= UInt<29>("h00")
wire dma_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 93:29]
wire lsu_pkt_m_in : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 94:29]
wire lsu_pkt_r_in : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 95:29]
wire lsu_error_pkt_m : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}} @[lsu_lsc_ctl.scala 96:29]
wire _T : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}} @[lsu_lsc_ctl.scala 97:37]
_T.bits.addr <= UInt<32>("h00") @[lsu_lsc_ctl.scala 97:37]
_T.bits.mscause <= UInt<4>("h00") @[lsu_lsc_ctl.scala 97:37]
_T.bits.exc_type <= UInt<1>("h00") @[lsu_lsc_ctl.scala 97:37]
_T.bits.inst_type <= UInt<1>("h00") @[lsu_lsc_ctl.scala 97:37]
_T.bits.single_ecc_error <= UInt<1>("h00") @[lsu_lsc_ctl.scala 97:37]
_T.valid <= UInt<1>("h00") @[lsu_lsc_ctl.scala 97:37]
lsu_error_pkt_m.bits.addr <= _T.bits.addr @[lsu_lsc_ctl.scala 97:20]
lsu_error_pkt_m.bits.mscause <= _T.bits.mscause @[lsu_lsc_ctl.scala 97:20]
lsu_error_pkt_m.bits.exc_type <= _T.bits.exc_type @[lsu_lsc_ctl.scala 97:20]
lsu_error_pkt_m.bits.inst_type <= _T.bits.inst_type @[lsu_lsc_ctl.scala 97:20]
lsu_error_pkt_m.bits.single_ecc_error <= _T.bits.single_ecc_error @[lsu_lsc_ctl.scala 97:20]
lsu_error_pkt_m.valid <= _T.valid @[lsu_lsc_ctl.scala 97:20]
node _T_1 = bits(io.dec_lsu_valid_raw_d, 0, 0) @[lsu_lsc_ctl.scala 100:52]
node lsu_rs1_d = mux(_T_1, io.lsu_exu.exu_lsu_rs1_d, io.dma_lsc_ctl.dma_mem_addr) @[lsu_lsc_ctl.scala 100:28]
node _T_2 = bits(io.dec_lsu_offset_d, 11, 0) @[lsu_lsc_ctl.scala 101:44]
node _T_3 = bits(io.dec_lsu_valid_raw_d, 0, 0) @[Bitwise.scala 72:15]
node _T_4 = mux(_T_3, UInt<12>("h0fff"), UInt<12>("h00")) @[Bitwise.scala 72:12]
node lsu_offset_d = and(_T_2, _T_4) @[lsu_lsc_ctl.scala 101:51]
node _T_5 = bits(io.lsu_pkt_d.bits.load_ldst_bypass_d, 0, 0) @[lsu_lsc_ctl.scala 104:66]
node rs1_d = mux(_T_5, io.lsu_result_m, lsu_rs1_d) @[lsu_lsc_ctl.scala 104:28]
node _T_6 = bits(rs1_d, 11, 0) @[lib.scala 92:31]
node _T_7 = cat(UInt<1>("h00"), _T_6) @[Cat.scala 29:58]
node _T_8 = bits(lsu_offset_d, 11, 0) @[lib.scala 92:60]
node _T_9 = cat(UInt<1>("h00"), _T_8) @[Cat.scala 29:58]
node _T_10 = add(_T_7, _T_9) @[lib.scala 92:39]
node _T_11 = tail(_T_10, 1) @[lib.scala 92:39]
node _T_12 = bits(lsu_offset_d, 11, 11) @[lib.scala 93:41]
node _T_13 = bits(_T_11, 12, 12) @[lib.scala 93:50]
node _T_14 = xor(_T_12, _T_13) @[lib.scala 93:46]
node _T_15 = not(_T_14) @[lib.scala 93:33]
node _T_16 = bits(_T_15, 0, 0) @[Bitwise.scala 72:15]
node _T_17 = mux(_T_16, UInt<20>("h0fffff"), UInt<20>("h00")) @[Bitwise.scala 72:12]
node _T_18 = bits(rs1_d, 31, 12) @[lib.scala 93:63]
node _T_19 = and(_T_17, _T_18) @[lib.scala 93:58]
node _T_20 = bits(lsu_offset_d, 11, 11) @[lib.scala 94:25]
node _T_21 = not(_T_20) @[lib.scala 94:18]
node _T_22 = bits(_T_11, 12, 12) @[lib.scala 94:34]
node _T_23 = and(_T_21, _T_22) @[lib.scala 94:30]
node _T_24 = bits(_T_23, 0, 0) @[Bitwise.scala 72:15]
node _T_25 = mux(_T_24, UInt<20>("h0fffff"), UInt<20>("h00")) @[Bitwise.scala 72:12]
node _T_26 = bits(rs1_d, 31, 12) @[lib.scala 94:47]
node _T_27 = add(_T_26, UInt<1>("h01")) @[lib.scala 94:54]
node _T_28 = tail(_T_27, 1) @[lib.scala 94:54]
node _T_29 = and(_T_25, _T_28) @[lib.scala 94:41]
node _T_30 = or(_T_19, _T_29) @[lib.scala 93:72]
node _T_31 = bits(lsu_offset_d, 11, 11) @[lib.scala 95:24]
node _T_32 = bits(_T_11, 12, 12) @[lib.scala 95:34]
node _T_33 = not(_T_32) @[lib.scala 95:31]
node _T_34 = and(_T_31, _T_33) @[lib.scala 95:29]
node _T_35 = bits(_T_34, 0, 0) @[Bitwise.scala 72:15]
node _T_36 = mux(_T_35, UInt<20>("h0fffff"), UInt<20>("h00")) @[Bitwise.scala 72:12]
node _T_37 = bits(rs1_d, 31, 12) @[lib.scala 95:47]
node _T_38 = sub(_T_37, UInt<1>("h01")) @[lib.scala 95:54]
node _T_39 = tail(_T_38, 1) @[lib.scala 95:54]
node _T_40 = and(_T_36, _T_39) @[lib.scala 95:41]
node _T_41 = or(_T_30, _T_40) @[lib.scala 94:61]
node _T_42 = bits(_T_11, 11, 0) @[lib.scala 96:22]
node full_addr_d = cat(_T_41, _T_42) @[Cat.scala 29:58]
node _T_43 = bits(io.lsu_pkt_d.bits.half, 0, 0) @[Bitwise.scala 72:15]
node _T_44 = mux(_T_43, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
node _T_45 = and(_T_44, UInt<3>("h01")) @[lsu_lsc_ctl.scala 109:58]
node _T_46 = bits(io.lsu_pkt_d.bits.word, 0, 0) @[Bitwise.scala 72:15]
node _T_47 = mux(_T_46, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
node _T_48 = and(_T_47, UInt<3>("h03")) @[lsu_lsc_ctl.scala 110:40]
node _T_49 = or(_T_45, _T_48) @[lsu_lsc_ctl.scala 109:70]
node _T_50 = bits(io.lsu_pkt_d.bits.dword, 0, 0) @[Bitwise.scala 72:15]
node _T_51 = mux(_T_50, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
node _T_52 = and(_T_51, UInt<3>("h07")) @[lsu_lsc_ctl.scala 111:40]
node addr_offset_d = or(_T_49, _T_52) @[lsu_lsc_ctl.scala 110:52]
node _T_53 = bits(lsu_offset_d, 11, 11) @[lsu_lsc_ctl.scala 113:39]
node _T_54 = bits(lsu_offset_d, 11, 0) @[lsu_lsc_ctl.scala 113:52]
node _T_55 = cat(_T_53, _T_54) @[Cat.scala 29:58]
node _T_56 = mux(UInt<1>("h00"), UInt<9>("h01ff"), UInt<9>("h00")) @[Bitwise.scala 72:12]
node _T_57 = bits(addr_offset_d, 2, 0) @[lsu_lsc_ctl.scala 113:91]
node _T_58 = cat(_T_56, _T_57) @[Cat.scala 29:58]
node _T_59 = add(_T_55, _T_58) @[lsu_lsc_ctl.scala 113:60]
node end_addr_offset_d = tail(_T_59, 1) @[lsu_lsc_ctl.scala 113:60]
node _T_60 = bits(rs1_d, 31, 0) @[lsu_lsc_ctl.scala 114:32]
node _T_61 = bits(end_addr_offset_d, 12, 12) @[lsu_lsc_ctl.scala 114:70]
node _T_62 = bits(_T_61, 0, 0) @[Bitwise.scala 72:15]
node _T_63 = mux(_T_62, UInt<19>("h07ffff"), UInt<19>("h00")) @[Bitwise.scala 72:12]
node _T_64 = bits(end_addr_offset_d, 12, 0) @[lsu_lsc_ctl.scala 114:93]
node _T_65 = cat(_T_63, _T_64) @[Cat.scala 29:58]
node _T_66 = add(_T_60, _T_65) @[lsu_lsc_ctl.scala 114:39]
node full_end_addr_d = tail(_T_66, 1) @[lsu_lsc_ctl.scala 114:39]
io.end_addr_d <= full_end_addr_d @[lsu_lsc_ctl.scala 115:24]
inst addrcheck of lsu_addrcheck @[lsu_lsc_ctl.scala 118:25]
addrcheck.clock <= clock
addrcheck.reset <= reset
addrcheck.io.lsu_c2_m_clk <= io.lsu_c2_m_clk @[lsu_lsc_ctl.scala 120:42]
addrcheck.io.start_addr_d <= full_addr_d @[lsu_lsc_ctl.scala 122:42]
addrcheck.io.end_addr_d <= full_end_addr_d @[lsu_lsc_ctl.scala 123:42]
addrcheck.io.lsu_pkt_d.bits.store_data_bypass_m <= io.lsu_pkt_d.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 124:42]
addrcheck.io.lsu_pkt_d.bits.load_ldst_bypass_d <= io.lsu_pkt_d.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 124:42]
addrcheck.io.lsu_pkt_d.bits.store_data_bypass_d <= io.lsu_pkt_d.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 124:42]
addrcheck.io.lsu_pkt_d.bits.dma <= io.lsu_pkt_d.bits.dma @[lsu_lsc_ctl.scala 124:42]
addrcheck.io.lsu_pkt_d.bits.unsign <= io.lsu_pkt_d.bits.unsign @[lsu_lsc_ctl.scala 124:42]
addrcheck.io.lsu_pkt_d.bits.store <= io.lsu_pkt_d.bits.store @[lsu_lsc_ctl.scala 124:42]
addrcheck.io.lsu_pkt_d.bits.load <= io.lsu_pkt_d.bits.load @[lsu_lsc_ctl.scala 124:42]
addrcheck.io.lsu_pkt_d.bits.dword <= io.lsu_pkt_d.bits.dword @[lsu_lsc_ctl.scala 124:42]
addrcheck.io.lsu_pkt_d.bits.word <= io.lsu_pkt_d.bits.word @[lsu_lsc_ctl.scala 124:42]
addrcheck.io.lsu_pkt_d.bits.half <= io.lsu_pkt_d.bits.half @[lsu_lsc_ctl.scala 124:42]
addrcheck.io.lsu_pkt_d.bits.by <= io.lsu_pkt_d.bits.by @[lsu_lsc_ctl.scala 124:42]
addrcheck.io.lsu_pkt_d.bits.stack <= io.lsu_pkt_d.bits.stack @[lsu_lsc_ctl.scala 124:42]
addrcheck.io.lsu_pkt_d.bits.fast_int <= io.lsu_pkt_d.bits.fast_int @[lsu_lsc_ctl.scala 124:42]
addrcheck.io.lsu_pkt_d.valid <= io.lsu_pkt_d.valid @[lsu_lsc_ctl.scala 124:42]
addrcheck.io.dec_tlu_mrac_ff <= io.dec_tlu_mrac_ff @[lsu_lsc_ctl.scala 125:42]
node _T_67 = bits(rs1_d, 31, 28) @[lsu_lsc_ctl.scala 126:50]
addrcheck.io.rs1_region_d <= _T_67 @[lsu_lsc_ctl.scala 126:42]
addrcheck.io.rs1_d <= rs1_d @[lsu_lsc_ctl.scala 127:42]
io.is_sideeffects_m <= addrcheck.io.is_sideeffects_m @[lsu_lsc_ctl.scala 128:42]
io.addr_in_dccm_d <= addrcheck.io.addr_in_dccm_d @[lsu_lsc_ctl.scala 129:42]
io.addr_in_pic_d <= addrcheck.io.addr_in_pic_d @[lsu_lsc_ctl.scala 130:42]
addrcheck.io.scan_mode <= io.scan_mode @[lsu_lsc_ctl.scala 137:42]
wire exc_mscause_r : UInt<4>
exc_mscause_r <= UInt<4>("h00")
wire fir_dccm_access_error_r : UInt<1>
fir_dccm_access_error_r <= UInt<1>("h00")
wire fir_nondccm_access_error_r : UInt<1>
fir_nondccm_access_error_r <= UInt<1>("h00")
wire access_fault_r : UInt<1>
access_fault_r <= UInt<1>("h00")
wire misaligned_fault_r : UInt<1>
misaligned_fault_r <= UInt<1>("h00")
wire lsu_fir_error_m : UInt<2>
lsu_fir_error_m <= UInt<2>("h00")
wire fir_dccm_access_error_m : UInt<1>
fir_dccm_access_error_m <= UInt<1>("h00")
wire fir_nondccm_access_error_m : UInt<1>
fir_nondccm_access_error_m <= UInt<1>("h00")
reg access_fault_m : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 149:75]
access_fault_m <= addrcheck.io.access_fault_d @[lsu_lsc_ctl.scala 149:75]
reg misaligned_fault_m : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 150:75]
misaligned_fault_m <= addrcheck.io.misaligned_fault_d @[lsu_lsc_ctl.scala 150:75]
reg exc_mscause_m : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 151:75]
exc_mscause_m <= addrcheck.io.exc_mscause_d @[lsu_lsc_ctl.scala 151:75]
reg _T_68 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 152:75]
_T_68 <= addrcheck.io.fir_dccm_access_error_d @[lsu_lsc_ctl.scala 152:75]
fir_dccm_access_error_m <= _T_68 @[lsu_lsc_ctl.scala 152:38]
reg _T_69 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 153:75]
_T_69 <= addrcheck.io.fir_nondccm_access_error_d @[lsu_lsc_ctl.scala 153:75]
fir_nondccm_access_error_m <= _T_69 @[lsu_lsc_ctl.scala 153:38]
node _T_70 = or(access_fault_m, misaligned_fault_m) @[lsu_lsc_ctl.scala 155:34]
io.lsu_exc_m <= _T_70 @[lsu_lsc_ctl.scala 155:16]
node _T_71 = eq(io.lsu_double_ecc_error_r, UInt<1>("h00")) @[lsu_lsc_ctl.scala 156:64]
node _T_72 = and(io.lsu_single_ecc_error_r, _T_71) @[lsu_lsc_ctl.scala 156:62]
node _T_73 = or(io.lsu_commit_r, io.lsu_pkt_r.bits.dma) @[lsu_lsc_ctl.scala 156:111]
node _T_74 = and(_T_72, _T_73) @[lsu_lsc_ctl.scala 156:92]
node _T_75 = and(_T_74, io.lsu_pkt_r.valid) @[lsu_lsc_ctl.scala 156:136]
io.lsu_single_ecc_error_incr <= _T_75 @[lsu_lsc_ctl.scala 156:32]
node _T_76 = or(access_fault_r, misaligned_fault_r) @[lsu_lsc_ctl.scala 160:49]
node _T_77 = or(_T_76, io.lsu_double_ecc_error_r) @[lsu_lsc_ctl.scala 160:70]
node _T_78 = and(_T_77, io.lsu_pkt_r.valid) @[lsu_lsc_ctl.scala 160:99]
node _T_79 = eq(io.lsu_pkt_r.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 160:122]
node _T_80 = and(_T_78, _T_79) @[lsu_lsc_ctl.scala 160:120]
node _T_81 = eq(io.lsu_pkt_r.bits.fast_int, UInt<1>("h00")) @[lsu_lsc_ctl.scala 160:147]
node _T_82 = and(_T_80, _T_81) @[lsu_lsc_ctl.scala 160:145]
io.lsu_error_pkt_r.valid <= _T_82 @[lsu_lsc_ctl.scala 160:30]
node _T_83 = eq(io.lsu_error_pkt_r.valid, UInt<1>("h00")) @[lsu_lsc_ctl.scala 161:77]
node _T_84 = and(io.lsu_single_ecc_error_r, _T_83) @[lsu_lsc_ctl.scala 161:75]
node _T_85 = eq(io.lsu_pkt_r.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 161:105]
node _T_86 = and(_T_84, _T_85) @[lsu_lsc_ctl.scala 161:103]
io.lsu_error_pkt_r.bits.single_ecc_error <= _T_86 @[lsu_lsc_ctl.scala 161:46]
io.lsu_error_pkt_r.bits.inst_type <= io.lsu_pkt_r.bits.store @[lsu_lsc_ctl.scala 162:39]
node _T_87 = not(misaligned_fault_r) @[lsu_lsc_ctl.scala 163:42]
io.lsu_error_pkt_r.bits.exc_type <= _T_87 @[lsu_lsc_ctl.scala 163:39]
node _T_88 = eq(misaligned_fault_r, UInt<1>("h00")) @[lsu_lsc_ctl.scala 164:75]
node _T_89 = and(io.lsu_double_ecc_error_r, _T_88) @[lsu_lsc_ctl.scala 164:73]
node _T_90 = eq(access_fault_r, UInt<1>("h00")) @[lsu_lsc_ctl.scala 164:97]
node _T_91 = and(_T_89, _T_90) @[lsu_lsc_ctl.scala 164:95]
node _T_92 = bits(_T_91, 0, 0) @[lsu_lsc_ctl.scala 164:114]
node _T_93 = bits(exc_mscause_r, 3, 0) @[lsu_lsc_ctl.scala 164:144]
node _T_94 = mux(_T_92, UInt<4>("h01"), _T_93) @[lsu_lsc_ctl.scala 164:45]
io.lsu_error_pkt_r.bits.mscause <= _T_94 @[lsu_lsc_ctl.scala 164:39]
node _T_95 = bits(io.lsu_addr_r, 31, 0) @[lsu_lsc_ctl.scala 165:55]
io.lsu_error_pkt_r.bits.addr <= _T_95 @[lsu_lsc_ctl.scala 165:39]
node _T_96 = bits(fir_nondccm_access_error_r, 0, 0) @[lsu_lsc_ctl.scala 166:68]
node _T_97 = bits(fir_dccm_access_error_r, 0, 0) @[lsu_lsc_ctl.scala 166:113]
node _T_98 = and(io.lsu_pkt_r.bits.fast_int, io.lsu_double_ecc_error_r) @[lsu_lsc_ctl.scala 166:162]
node _T_99 = bits(_T_98, 0, 0) @[lsu_lsc_ctl.scala 166:191]
node _T_100 = mux(_T_99, UInt<2>("h01"), UInt<2>("h00")) @[lsu_lsc_ctl.scala 166:133]
node _T_101 = mux(_T_97, UInt<2>("h02"), _T_100) @[lsu_lsc_ctl.scala 166:88]
node _T_102 = mux(_T_96, UInt<2>("h03"), _T_101) @[lsu_lsc_ctl.scala 166:40]
io.lsu_fir_error <= _T_102 @[lsu_lsc_ctl.scala 166:34]
reg _T_103 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 168:71]
_T_103 <= access_fault_m @[lsu_lsc_ctl.scala 168:71]
access_fault_r <= _T_103 @[lsu_lsc_ctl.scala 168:34]
reg _T_104 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 169:71]
_T_104 <= exc_mscause_m @[lsu_lsc_ctl.scala 169:71]
exc_mscause_r <= _T_104 @[lsu_lsc_ctl.scala 169:34]
reg _T_105 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 170:71]
_T_105 <= fir_dccm_access_error_m @[lsu_lsc_ctl.scala 170:71]
fir_dccm_access_error_r <= _T_105 @[lsu_lsc_ctl.scala 170:34]
reg _T_106 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 171:71]
_T_106 <= fir_nondccm_access_error_m @[lsu_lsc_ctl.scala 171:71]
fir_nondccm_access_error_r <= _T_106 @[lsu_lsc_ctl.scala 171:34]
reg _T_107 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 172:71]
_T_107 <= misaligned_fault_m @[lsu_lsc_ctl.scala 172:71]
misaligned_fault_r <= _T_107 @[lsu_lsc_ctl.scala 172:34]
dma_pkt_d.bits.unsign <= UInt<1>("h00") @[lsu_lsc_ctl.scala 190:27]
dma_pkt_d.bits.stack <= UInt<1>("h00") @[lsu_lsc_ctl.scala 191:26]
dma_pkt_d.bits.fast_int <= UInt<1>("h00") @[lsu_lsc_ctl.scala 192:27]
dma_pkt_d.valid <= io.dma_lsc_ctl.dma_dccm_req @[lsu_lsc_ctl.scala 193:22]
dma_pkt_d.bits.dma <= UInt<1>("h01") @[lsu_lsc_ctl.scala 194:27]
dma_pkt_d.bits.store <= io.dma_lsc_ctl.dma_mem_write @[lsu_lsc_ctl.scala 195:27]
node _T_108 = not(io.dma_lsc_ctl.dma_mem_write) @[lsu_lsc_ctl.scala 196:30]
dma_pkt_d.bits.load <= _T_108 @[lsu_lsc_ctl.scala 196:27]
node _T_109 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 197:56]
node _T_110 = eq(_T_109, UInt<3>("h00")) @[lsu_lsc_ctl.scala 197:62]
dma_pkt_d.bits.by <= _T_110 @[lsu_lsc_ctl.scala 197:27]
node _T_111 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 198:56]
node _T_112 = eq(_T_111, UInt<3>("h01")) @[lsu_lsc_ctl.scala 198:62]
dma_pkt_d.bits.half <= _T_112 @[lsu_lsc_ctl.scala 198:27]
node _T_113 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 199:56]
node _T_114 = eq(_T_113, UInt<3>("h02")) @[lsu_lsc_ctl.scala 199:62]
dma_pkt_d.bits.word <= _T_114 @[lsu_lsc_ctl.scala 199:27]
node _T_115 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 200:56]
node _T_116 = eq(_T_115, UInt<3>("h03")) @[lsu_lsc_ctl.scala 200:62]
dma_pkt_d.bits.dword <= _T_116 @[lsu_lsc_ctl.scala 200:27]
dma_pkt_d.bits.store_data_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 201:39]
dma_pkt_d.bits.load_ldst_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 202:39]
dma_pkt_d.bits.store_data_bypass_m <= UInt<1>("h00") @[lsu_lsc_ctl.scala 203:39]
wire lsu_ld_datafn_r : UInt<32>
lsu_ld_datafn_r <= UInt<32>("h00")
wire lsu_ld_datafn_corr_r : UInt<32>
lsu_ld_datafn_corr_r <= UInt<32>("h00")
wire lsu_ld_datafn_m : UInt<32>
lsu_ld_datafn_m <= UInt<32>("h00")
node _T_117 = bits(io.dec_lsu_valid_raw_d, 0, 0) @[lsu_lsc_ctl.scala 209:50]
node _T_118 = mux(_T_117, io.lsu_p, dma_pkt_d) @[lsu_lsc_ctl.scala 209:26]
io.lsu_pkt_d.bits.store_data_bypass_m <= _T_118.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 209:20]
io.lsu_pkt_d.bits.load_ldst_bypass_d <= _T_118.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 209:20]
io.lsu_pkt_d.bits.store_data_bypass_d <= _T_118.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 209:20]
io.lsu_pkt_d.bits.dma <= _T_118.bits.dma @[lsu_lsc_ctl.scala 209:20]
io.lsu_pkt_d.bits.unsign <= _T_118.bits.unsign @[lsu_lsc_ctl.scala 209:20]
io.lsu_pkt_d.bits.store <= _T_118.bits.store @[lsu_lsc_ctl.scala 209:20]
io.lsu_pkt_d.bits.load <= _T_118.bits.load @[lsu_lsc_ctl.scala 209:20]
io.lsu_pkt_d.bits.dword <= _T_118.bits.dword @[lsu_lsc_ctl.scala 209:20]
io.lsu_pkt_d.bits.word <= _T_118.bits.word @[lsu_lsc_ctl.scala 209:20]
io.lsu_pkt_d.bits.half <= _T_118.bits.half @[lsu_lsc_ctl.scala 209:20]
io.lsu_pkt_d.bits.by <= _T_118.bits.by @[lsu_lsc_ctl.scala 209:20]
io.lsu_pkt_d.bits.stack <= _T_118.bits.stack @[lsu_lsc_ctl.scala 209:20]
io.lsu_pkt_d.bits.fast_int <= _T_118.bits.fast_int @[lsu_lsc_ctl.scala 209:20]
io.lsu_pkt_d.valid <= _T_118.valid @[lsu_lsc_ctl.scala 209:20]
lsu_pkt_m_in.bits.store_data_bypass_m <= io.lsu_pkt_d.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 210:20]
lsu_pkt_m_in.bits.load_ldst_bypass_d <= io.lsu_pkt_d.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 210:20]
lsu_pkt_m_in.bits.store_data_bypass_d <= io.lsu_pkt_d.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 210:20]
lsu_pkt_m_in.bits.dma <= io.lsu_pkt_d.bits.dma @[lsu_lsc_ctl.scala 210:20]
lsu_pkt_m_in.bits.unsign <= io.lsu_pkt_d.bits.unsign @[lsu_lsc_ctl.scala 210:20]
lsu_pkt_m_in.bits.store <= io.lsu_pkt_d.bits.store @[lsu_lsc_ctl.scala 210:20]
lsu_pkt_m_in.bits.load <= io.lsu_pkt_d.bits.load @[lsu_lsc_ctl.scala 210:20]
lsu_pkt_m_in.bits.dword <= io.lsu_pkt_d.bits.dword @[lsu_lsc_ctl.scala 210:20]
lsu_pkt_m_in.bits.word <= io.lsu_pkt_d.bits.word @[lsu_lsc_ctl.scala 210:20]
lsu_pkt_m_in.bits.half <= io.lsu_pkt_d.bits.half @[lsu_lsc_ctl.scala 210:20]
lsu_pkt_m_in.bits.by <= io.lsu_pkt_d.bits.by @[lsu_lsc_ctl.scala 210:20]
lsu_pkt_m_in.bits.stack <= io.lsu_pkt_d.bits.stack @[lsu_lsc_ctl.scala 210:20]
lsu_pkt_m_in.bits.fast_int <= io.lsu_pkt_d.bits.fast_int @[lsu_lsc_ctl.scala 210:20]
lsu_pkt_m_in.valid <= io.lsu_pkt_d.valid @[lsu_lsc_ctl.scala 210:20]
lsu_pkt_r_in.bits.store_data_bypass_m <= io.lsu_pkt_m.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 211:20]
lsu_pkt_r_in.bits.load_ldst_bypass_d <= io.lsu_pkt_m.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 211:20]
lsu_pkt_r_in.bits.store_data_bypass_d <= io.lsu_pkt_m.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 211:20]
lsu_pkt_r_in.bits.dma <= io.lsu_pkt_m.bits.dma @[lsu_lsc_ctl.scala 211:20]
lsu_pkt_r_in.bits.unsign <= io.lsu_pkt_m.bits.unsign @[lsu_lsc_ctl.scala 211:20]
lsu_pkt_r_in.bits.store <= io.lsu_pkt_m.bits.store @[lsu_lsc_ctl.scala 211:20]
lsu_pkt_r_in.bits.load <= io.lsu_pkt_m.bits.load @[lsu_lsc_ctl.scala 211:20]
lsu_pkt_r_in.bits.dword <= io.lsu_pkt_m.bits.dword @[lsu_lsc_ctl.scala 211:20]
lsu_pkt_r_in.bits.word <= io.lsu_pkt_m.bits.word @[lsu_lsc_ctl.scala 211:20]
lsu_pkt_r_in.bits.half <= io.lsu_pkt_m.bits.half @[lsu_lsc_ctl.scala 211:20]
lsu_pkt_r_in.bits.by <= io.lsu_pkt_m.bits.by @[lsu_lsc_ctl.scala 211:20]
lsu_pkt_r_in.bits.stack <= io.lsu_pkt_m.bits.stack @[lsu_lsc_ctl.scala 211:20]
lsu_pkt_r_in.bits.fast_int <= io.lsu_pkt_m.bits.fast_int @[lsu_lsc_ctl.scala 211:20]
lsu_pkt_r_in.valid <= io.lsu_pkt_m.valid @[lsu_lsc_ctl.scala 211:20]
node _T_119 = eq(io.lsu_p.bits.fast_int, UInt<1>("h00")) @[lsu_lsc_ctl.scala 213:64]
node _T_120 = and(io.flush_m_up, _T_119) @[lsu_lsc_ctl.scala 213:61]
node _T_121 = eq(_T_120, UInt<1>("h00")) @[lsu_lsc_ctl.scala 213:45]
node _T_122 = and(io.lsu_p.valid, _T_121) @[lsu_lsc_ctl.scala 213:43]
node _T_123 = or(_T_122, io.dma_lsc_ctl.dma_dccm_req) @[lsu_lsc_ctl.scala 213:90]
io.lsu_pkt_d.valid <= _T_123 @[lsu_lsc_ctl.scala 213:24]
node _T_124 = eq(io.lsu_pkt_d.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 214:68]
node _T_125 = and(io.flush_m_up, _T_124) @[lsu_lsc_ctl.scala 214:65]
node _T_126 = eq(_T_125, UInt<1>("h00")) @[lsu_lsc_ctl.scala 214:49]
node _T_127 = and(io.lsu_pkt_d.valid, _T_126) @[lsu_lsc_ctl.scala 214:47]
lsu_pkt_m_in.valid <= _T_127 @[lsu_lsc_ctl.scala 214:24]
node _T_128 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 215:68]
node _T_129 = and(io.flush_m_up, _T_128) @[lsu_lsc_ctl.scala 215:65]
node _T_130 = eq(_T_129, UInt<1>("h00")) @[lsu_lsc_ctl.scala 215:49]
node _T_131 = and(io.lsu_pkt_m.valid, _T_130) @[lsu_lsc_ctl.scala 215:47]
lsu_pkt_r_in.valid <= _T_131 @[lsu_lsc_ctl.scala 215:24]
wire _T_132 : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 217:91]
_T_132.bits.store_data_bypass_m <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
_T_132.bits.load_ldst_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
_T_132.bits.store_data_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
_T_132.bits.dma <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
_T_132.bits.unsign <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
_T_132.bits.store <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
_T_132.bits.load <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
_T_132.bits.dword <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
_T_132.bits.word <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
_T_132.bits.half <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
_T_132.bits.by <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
_T_132.bits.stack <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
_T_132.bits.fast_int <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
_T_132.valid <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
reg _T_133 : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, io.lsu_c1_m_clk with : (reset => (reset, _T_132)) @[lsu_lsc_ctl.scala 217:65]
_T_133.bits.store_data_bypass_m <= lsu_pkt_m_in.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 217:65]
_T_133.bits.load_ldst_bypass_d <= lsu_pkt_m_in.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 217:65]
_T_133.bits.store_data_bypass_d <= lsu_pkt_m_in.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 217:65]
_T_133.bits.dma <= lsu_pkt_m_in.bits.dma @[lsu_lsc_ctl.scala 217:65]
_T_133.bits.unsign <= lsu_pkt_m_in.bits.unsign @[lsu_lsc_ctl.scala 217:65]
_T_133.bits.store <= lsu_pkt_m_in.bits.store @[lsu_lsc_ctl.scala 217:65]
_T_133.bits.load <= lsu_pkt_m_in.bits.load @[lsu_lsc_ctl.scala 217:65]
_T_133.bits.dword <= lsu_pkt_m_in.bits.dword @[lsu_lsc_ctl.scala 217:65]
_T_133.bits.word <= lsu_pkt_m_in.bits.word @[lsu_lsc_ctl.scala 217:65]
_T_133.bits.half <= lsu_pkt_m_in.bits.half @[lsu_lsc_ctl.scala 217:65]
_T_133.bits.by <= lsu_pkt_m_in.bits.by @[lsu_lsc_ctl.scala 217:65]
_T_133.bits.stack <= lsu_pkt_m_in.bits.stack @[lsu_lsc_ctl.scala 217:65]
_T_133.bits.fast_int <= lsu_pkt_m_in.bits.fast_int @[lsu_lsc_ctl.scala 217:65]
_T_133.valid <= lsu_pkt_m_in.valid @[lsu_lsc_ctl.scala 217:65]
io.lsu_pkt_m.bits.store_data_bypass_m <= _T_133.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 217:28]
io.lsu_pkt_m.bits.load_ldst_bypass_d <= _T_133.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 217:28]
io.lsu_pkt_m.bits.store_data_bypass_d <= _T_133.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 217:28]
io.lsu_pkt_m.bits.dma <= _T_133.bits.dma @[lsu_lsc_ctl.scala 217:28]
io.lsu_pkt_m.bits.unsign <= _T_133.bits.unsign @[lsu_lsc_ctl.scala 217:28]
io.lsu_pkt_m.bits.store <= _T_133.bits.store @[lsu_lsc_ctl.scala 217:28]
io.lsu_pkt_m.bits.load <= _T_133.bits.load @[lsu_lsc_ctl.scala 217:28]
io.lsu_pkt_m.bits.dword <= _T_133.bits.dword @[lsu_lsc_ctl.scala 217:28]
io.lsu_pkt_m.bits.word <= _T_133.bits.word @[lsu_lsc_ctl.scala 217:28]
io.lsu_pkt_m.bits.half <= _T_133.bits.half @[lsu_lsc_ctl.scala 217:28]
io.lsu_pkt_m.bits.by <= _T_133.bits.by @[lsu_lsc_ctl.scala 217:28]
io.lsu_pkt_m.bits.stack <= _T_133.bits.stack @[lsu_lsc_ctl.scala 217:28]
io.lsu_pkt_m.bits.fast_int <= _T_133.bits.fast_int @[lsu_lsc_ctl.scala 217:28]
io.lsu_pkt_m.valid <= _T_133.valid @[lsu_lsc_ctl.scala 217:28]
wire _T_134 : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 218:91]
_T_134.bits.store_data_bypass_m <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91]
_T_134.bits.load_ldst_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91]
_T_134.bits.store_data_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91]
_T_134.bits.dma <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91]
_T_134.bits.unsign <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91]
_T_134.bits.store <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91]
_T_134.bits.load <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91]
_T_134.bits.dword <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91]
_T_134.bits.word <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91]
_T_134.bits.half <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91]
_T_134.bits.by <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91]
_T_134.bits.stack <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91]
_T_134.bits.fast_int <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91]
_T_134.valid <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91]
reg _T_135 : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, io.lsu_c1_r_clk with : (reset => (reset, _T_134)) @[lsu_lsc_ctl.scala 218:65]
_T_135.bits.store_data_bypass_m <= lsu_pkt_r_in.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 218:65]
_T_135.bits.load_ldst_bypass_d <= lsu_pkt_r_in.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 218:65]
_T_135.bits.store_data_bypass_d <= lsu_pkt_r_in.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 218:65]
_T_135.bits.dma <= lsu_pkt_r_in.bits.dma @[lsu_lsc_ctl.scala 218:65]
_T_135.bits.unsign <= lsu_pkt_r_in.bits.unsign @[lsu_lsc_ctl.scala 218:65]
_T_135.bits.store <= lsu_pkt_r_in.bits.store @[lsu_lsc_ctl.scala 218:65]
_T_135.bits.load <= lsu_pkt_r_in.bits.load @[lsu_lsc_ctl.scala 218:65]
_T_135.bits.dword <= lsu_pkt_r_in.bits.dword @[lsu_lsc_ctl.scala 218:65]
_T_135.bits.word <= lsu_pkt_r_in.bits.word @[lsu_lsc_ctl.scala 218:65]
_T_135.bits.half <= lsu_pkt_r_in.bits.half @[lsu_lsc_ctl.scala 218:65]
_T_135.bits.by <= lsu_pkt_r_in.bits.by @[lsu_lsc_ctl.scala 218:65]
_T_135.bits.stack <= lsu_pkt_r_in.bits.stack @[lsu_lsc_ctl.scala 218:65]
_T_135.bits.fast_int <= lsu_pkt_r_in.bits.fast_int @[lsu_lsc_ctl.scala 218:65]
_T_135.valid <= lsu_pkt_r_in.valid @[lsu_lsc_ctl.scala 218:65]
io.lsu_pkt_r.bits.store_data_bypass_m <= _T_135.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 218:28]
io.lsu_pkt_r.bits.load_ldst_bypass_d <= _T_135.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 218:28]
io.lsu_pkt_r.bits.store_data_bypass_d <= _T_135.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 218:28]
io.lsu_pkt_r.bits.dma <= _T_135.bits.dma @[lsu_lsc_ctl.scala 218:28]
io.lsu_pkt_r.bits.unsign <= _T_135.bits.unsign @[lsu_lsc_ctl.scala 218:28]
io.lsu_pkt_r.bits.store <= _T_135.bits.store @[lsu_lsc_ctl.scala 218:28]
io.lsu_pkt_r.bits.load <= _T_135.bits.load @[lsu_lsc_ctl.scala 218:28]
io.lsu_pkt_r.bits.dword <= _T_135.bits.dword @[lsu_lsc_ctl.scala 218:28]
io.lsu_pkt_r.bits.word <= _T_135.bits.word @[lsu_lsc_ctl.scala 218:28]
io.lsu_pkt_r.bits.half <= _T_135.bits.half @[lsu_lsc_ctl.scala 218:28]
io.lsu_pkt_r.bits.by <= _T_135.bits.by @[lsu_lsc_ctl.scala 218:28]
io.lsu_pkt_r.bits.stack <= _T_135.bits.stack @[lsu_lsc_ctl.scala 218:28]
io.lsu_pkt_r.bits.fast_int <= _T_135.bits.fast_int @[lsu_lsc_ctl.scala 218:28]
io.lsu_pkt_r.valid <= _T_135.valid @[lsu_lsc_ctl.scala 218:28]
reg _T_136 : UInt<1>, io.lsu_c2_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 219:65]
_T_136 <= lsu_pkt_m_in.valid @[lsu_lsc_ctl.scala 219:65]
io.lsu_pkt_m.valid <= _T_136 @[lsu_lsc_ctl.scala 219:28]
reg _T_137 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 220:65]
_T_137 <= lsu_pkt_r_in.valid @[lsu_lsc_ctl.scala 220:65]
io.lsu_pkt_r.valid <= _T_137 @[lsu_lsc_ctl.scala 220:28]
node _T_138 = bits(io.dma_lsc_ctl.dma_mem_wdata, 63, 0) @[lsu_lsc_ctl.scala 222:59]
node _T_139 = bits(io.dma_lsc_ctl.dma_mem_addr, 2, 0) @[lsu_lsc_ctl.scala 222:100]
node _T_140 = cat(_T_139, UInt<3>("h00")) @[Cat.scala 29:58]
node dma_mem_wdata_shifted = dshr(_T_138, _T_140) @[lsu_lsc_ctl.scala 222:66]
node _T_141 = bits(io.dma_lsc_ctl.dma_dccm_req, 0, 0) @[lsu_lsc_ctl.scala 223:63]
node _T_142 = bits(dma_mem_wdata_shifted, 31, 0) @[lsu_lsc_ctl.scala 223:91]
node _T_143 = bits(io.lsu_exu.exu_lsu_rs2_d, 31, 0) @[lsu_lsc_ctl.scala 223:122]
node store_data_d = mux(_T_141, _T_142, _T_143) @[lsu_lsc_ctl.scala 223:34]
node _T_144 = bits(io.lsu_pkt_d.bits.store_data_bypass_d, 0, 0) @[lsu_lsc_ctl.scala 224:73]
node _T_145 = bits(io.lsu_result_m, 31, 0) @[lsu_lsc_ctl.scala 224:95]
node _T_146 = bits(store_data_d, 31, 0) @[lsu_lsc_ctl.scala 224:114]
node store_data_m_in = mux(_T_144, _T_145, _T_146) @[lsu_lsc_ctl.scala 224:34]
reg store_data_pre_m : UInt, io.lsu_store_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 226:72]
store_data_pre_m <= store_data_m_in @[lsu_lsc_ctl.scala 226:72]
reg _T_147 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 227:62]
_T_147 <= io.lsu_addr_d @[lsu_lsc_ctl.scala 227:62]
io.lsu_addr_m <= _T_147 @[lsu_lsc_ctl.scala 227:24]
reg _T_148 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 228:62]
_T_148 <= io.lsu_addr_m @[lsu_lsc_ctl.scala 228:62]
io.lsu_addr_r <= _T_148 @[lsu_lsc_ctl.scala 228:24]
node _T_149 = bits(io.ldst_dual_m, 0, 0) @[lib.scala 8:44]
node _T_150 = bits(io.lsu_addr_m, 31, 3) @[lsu_lsc_ctl.scala 229:71]
node _T_151 = mux(_T_149, end_addr_pre_m, _T_150) @[lsu_lsc_ctl.scala 229:27]
node _T_152 = bits(io.end_addr_d, 2, 0) @[lsu_lsc_ctl.scala 229:128]
reg _T_153 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 229:114]
_T_153 <= _T_152 @[lsu_lsc_ctl.scala 229:114]
node _T_154 = cat(_T_151, _T_153) @[Cat.scala 29:58]
io.end_addr_m <= _T_154 @[lsu_lsc_ctl.scala 229:17]
node _T_155 = bits(io.ldst_dual_r, 0, 0) @[lib.scala 8:44]
node _T_156 = bits(io.lsu_addr_r, 31, 3) @[lsu_lsc_ctl.scala 230:71]
node _T_157 = mux(_T_155, end_addr_pre_r, _T_156) @[lsu_lsc_ctl.scala 230:27]
node _T_158 = bits(io.end_addr_m, 2, 0) @[lsu_lsc_ctl.scala 230:128]
reg _T_159 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 230:114]
_T_159 <= _T_158 @[lsu_lsc_ctl.scala 230:114]
node _T_160 = cat(_T_157, _T_159) @[Cat.scala 29:58]
io.end_addr_r <= _T_160 @[lsu_lsc_ctl.scala 230:17]
node _T_161 = bits(io.end_addr_d, 31, 3) @[lsu_lsc_ctl.scala 231:41]
node _T_162 = and(io.lsu_pkt_d.valid, io.ldst_dual_d) @[lsu_lsc_ctl.scala 231:69]
node _T_163 = or(_T_162, io.clk_override) @[lsu_lsc_ctl.scala 231:87]
node _T_164 = bits(_T_163, 0, 0) @[lib.scala 8:44]
node _T_165 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44]
inst rvclkhdr of rvclkhdr @[lib.scala 390:23]
rvclkhdr.clock <= clock
rvclkhdr.reset <= reset
rvclkhdr.io.clk <= clock @[lib.scala 392:18]
rvclkhdr.io.en <= _T_164 @[lib.scala 393:17]
rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
reg _T_166 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_164 : @[Reg.scala 28:19]
_T_166 <= _T_161 @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
end_addr_pre_m <= _T_166 @[lsu_lsc_ctl.scala 231:18]
node _T_167 = bits(io.end_addr_m, 31, 3) @[lsu_lsc_ctl.scala 232:41]
node _T_168 = and(io.lsu_pkt_m.valid, io.ldst_dual_m) @[lsu_lsc_ctl.scala 232:69]
node _T_169 = or(_T_168, io.clk_override) @[lsu_lsc_ctl.scala 232:87]
node _T_170 = bits(_T_169, 0, 0) @[lib.scala 8:44]
node _T_171 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44]
inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 390:23]
rvclkhdr_1.clock <= clock
rvclkhdr_1.reset <= reset
rvclkhdr_1.io.clk <= clock @[lib.scala 392:18]
rvclkhdr_1.io.en <= _T_170 @[lib.scala 393:17]
rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
reg _T_172 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_170 : @[Reg.scala 28:19]
_T_172 <= _T_167 @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
end_addr_pre_r <= _T_172 @[lsu_lsc_ctl.scala 232:18]
reg _T_173 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 233:62]
_T_173 <= io.addr_in_dccm_d @[lsu_lsc_ctl.scala 233:62]
io.addr_in_dccm_m <= _T_173 @[lsu_lsc_ctl.scala 233:24]
reg _T_174 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 234:62]
_T_174 <= io.addr_in_dccm_m @[lsu_lsc_ctl.scala 234:62]
io.addr_in_dccm_r <= _T_174 @[lsu_lsc_ctl.scala 234:24]
reg _T_175 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 235:62]
_T_175 <= io.addr_in_pic_d @[lsu_lsc_ctl.scala 235:62]
io.addr_in_pic_m <= _T_175 @[lsu_lsc_ctl.scala 235:24]
reg _T_176 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 236:62]
_T_176 <= io.addr_in_pic_m @[lsu_lsc_ctl.scala 236:62]
io.addr_in_pic_r <= _T_176 @[lsu_lsc_ctl.scala 236:24]
reg _T_177 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 237:62]
_T_177 <= addrcheck.io.addr_external_d @[lsu_lsc_ctl.scala 237:62]
io.addr_external_m <= _T_177 @[lsu_lsc_ctl.scala 237:24]
reg addr_external_r : UInt<1>, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 238:66]
addr_external_r <= io.addr_external_m @[lsu_lsc_ctl.scala 238:66]
node _T_178 = or(io.addr_external_m, io.clk_override) @[lsu_lsc_ctl.scala 239:77]
node _T_179 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44]
inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 390:23]
rvclkhdr_2.clock <= clock
rvclkhdr_2.reset <= reset
rvclkhdr_2.io.clk <= clock @[lib.scala 392:18]
rvclkhdr_2.io.en <= _T_178 @[lib.scala 393:17]
rvclkhdr_2.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
reg bus_read_data_r : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_178 : @[Reg.scala 28:19]
bus_read_data_r <= io.bus_read_data_m @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
node _T_180 = bits(io.lsu_ld_data_corr_r, 31, 1) @[lsu_lsc_ctl.scala 242:52]
io.lsu_fir_addr <= _T_180 @[lsu_lsc_ctl.scala 242:28]
io.lsu_addr_d <= full_addr_d @[lsu_lsc_ctl.scala 244:28]
node _T_181 = or(io.lsu_pkt_r.bits.store, io.lsu_pkt_r.bits.load) @[lsu_lsc_ctl.scala 246:68]
node _T_182 = and(io.lsu_pkt_r.valid, _T_181) @[lsu_lsc_ctl.scala 246:41]
node _T_183 = eq(io.flush_r, UInt<1>("h00")) @[lsu_lsc_ctl.scala 246:96]
node _T_184 = and(_T_182, _T_183) @[lsu_lsc_ctl.scala 246:94]
node _T_185 = eq(io.lsu_pkt_r.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 246:110]
node _T_186 = and(_T_184, _T_185) @[lsu_lsc_ctl.scala 246:108]
io.lsu_commit_r <= _T_186 @[lsu_lsc_ctl.scala 246:19]
node _T_187 = bits(io.picm_mask_data_m, 31, 0) @[lsu_lsc_ctl.scala 247:52]
node _T_188 = eq(io.addr_in_pic_m, UInt<1>("h00")) @[lsu_lsc_ctl.scala 247:69]
node _T_189 = bits(_T_188, 0, 0) @[Bitwise.scala 72:15]
node _T_190 = mux(_T_189, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
node _T_191 = or(_T_187, _T_190) @[lsu_lsc_ctl.scala 247:59]
node _T_192 = bits(io.lsu_pkt_m.bits.store_data_bypass_m, 0, 0) @[lsu_lsc_ctl.scala 247:133]
node _T_193 = mux(_T_192, io.lsu_result_m, store_data_pre_m) @[lsu_lsc_ctl.scala 247:94]
node _T_194 = and(_T_191, _T_193) @[lsu_lsc_ctl.scala 247:89]
io.store_data_m <= _T_194 @[lsu_lsc_ctl.scala 247:29]
node _T_195 = bits(addr_external_r, 0, 0) @[lib.scala 8:44]
node _T_196 = mux(_T_195, bus_read_data_r, io.lsu_ld_data_r) @[lsu_lsc_ctl.scala 251:33]
lsu_ld_datafn_r <= _T_196 @[lsu_lsc_ctl.scala 251:27]
node _T_197 = bits(addr_external_r, 0, 0) @[lib.scala 8:44]
node _T_198 = mux(_T_197, bus_read_data_r, io.lsu_ld_data_corr_r) @[lsu_lsc_ctl.scala 252:33]
lsu_ld_datafn_corr_r <= _T_198 @[lsu_lsc_ctl.scala 252:27]
node _T_199 = and(io.lsu_pkt_r.bits.unsign, io.lsu_pkt_r.bits.by) @[lsu_lsc_ctl.scala 254:66]
node _T_200 = bits(_T_199, 0, 0) @[Bitwise.scala 72:15]
node _T_201 = mux(_T_200, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
node _T_202 = bits(lsu_ld_datafn_r, 7, 0) @[lsu_lsc_ctl.scala 254:125]
node _T_203 = cat(UInt<24>("h00"), _T_202) @[Cat.scala 29:58]
node _T_204 = and(_T_201, _T_203) @[lsu_lsc_ctl.scala 254:94]
node _T_205 = and(io.lsu_pkt_r.bits.unsign, io.lsu_pkt_r.bits.half) @[lsu_lsc_ctl.scala 255:43]
node _T_206 = bits(_T_205, 0, 0) @[Bitwise.scala 72:15]
node _T_207 = mux(_T_206, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
node _T_208 = bits(lsu_ld_datafn_r, 15, 0) @[lsu_lsc_ctl.scala 255:102]
node _T_209 = cat(UInt<16>("h00"), _T_208) @[Cat.scala 29:58]
node _T_210 = and(_T_207, _T_209) @[lsu_lsc_ctl.scala 255:71]
node _T_211 = or(_T_204, _T_210) @[lsu_lsc_ctl.scala 254:133]
node _T_212 = eq(io.lsu_pkt_r.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 256:17]
node _T_213 = and(_T_212, io.lsu_pkt_r.bits.by) @[lsu_lsc_ctl.scala 256:43]
node _T_214 = bits(_T_213, 0, 0) @[Bitwise.scala 72:15]
node _T_215 = mux(_T_214, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
node _T_216 = bits(lsu_ld_datafn_r, 7, 7) @[lsu_lsc_ctl.scala 256:102]
node _T_217 = bits(_T_216, 0, 0) @[Bitwise.scala 72:15]
node _T_218 = mux(_T_217, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12]
node _T_219 = bits(lsu_ld_datafn_r, 7, 0) @[lsu_lsc_ctl.scala 256:125]
node _T_220 = cat(_T_218, _T_219) @[Cat.scala 29:58]
node _T_221 = and(_T_215, _T_220) @[lsu_lsc_ctl.scala 256:71]
node _T_222 = or(_T_211, _T_221) @[lsu_lsc_ctl.scala 255:114]
node _T_223 = eq(io.lsu_pkt_r.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 257:17]
node _T_224 = and(_T_223, io.lsu_pkt_r.bits.half) @[lsu_lsc_ctl.scala 257:43]
node _T_225 = bits(_T_224, 0, 0) @[Bitwise.scala 72:15]
node _T_226 = mux(_T_225, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
node _T_227 = bits(lsu_ld_datafn_r, 15, 15) @[lsu_lsc_ctl.scala 257:101]
node _T_228 = bits(_T_227, 0, 0) @[Bitwise.scala 72:15]
node _T_229 = mux(_T_228, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12]
node _T_230 = bits(lsu_ld_datafn_r, 15, 0) @[lsu_lsc_ctl.scala 257:125]
node _T_231 = cat(_T_229, _T_230) @[Cat.scala 29:58]
node _T_232 = and(_T_226, _T_231) @[lsu_lsc_ctl.scala 257:71]
node _T_233 = or(_T_222, _T_232) @[lsu_lsc_ctl.scala 256:134]
node _T_234 = bits(io.lsu_pkt_r.bits.word, 0, 0) @[Bitwise.scala 72:15]
node _T_235 = mux(_T_234, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
node _T_236 = bits(lsu_ld_datafn_r, 31, 0) @[lsu_lsc_ctl.scala 258:60]
node _T_237 = and(_T_235, _T_236) @[lsu_lsc_ctl.scala 258:43]
node _T_238 = or(_T_233, _T_237) @[lsu_lsc_ctl.scala 257:134]
io.lsu_result_m <= _T_238 @[lsu_lsc_ctl.scala 254:27]
node _T_239 = and(io.lsu_pkt_r.bits.unsign, io.lsu_pkt_r.bits.by) @[lsu_lsc_ctl.scala 260:66]
node _T_240 = bits(_T_239, 0, 0) @[Bitwise.scala 72:15]
node _T_241 = mux(_T_240, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
node _T_242 = bits(lsu_ld_datafn_corr_r, 7, 0) @[lsu_lsc_ctl.scala 260:130]
node _T_243 = cat(UInt<24>("h00"), _T_242) @[Cat.scala 29:58]
node _T_244 = and(_T_241, _T_243) @[lsu_lsc_ctl.scala 260:94]
node _T_245 = and(io.lsu_pkt_r.bits.unsign, io.lsu_pkt_r.bits.half) @[lsu_lsc_ctl.scala 261:43]
node _T_246 = bits(_T_245, 0, 0) @[Bitwise.scala 72:15]
node _T_247 = mux(_T_246, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
node _T_248 = bits(lsu_ld_datafn_corr_r, 15, 0) @[lsu_lsc_ctl.scala 261:107]
node _T_249 = cat(UInt<16>("h00"), _T_248) @[Cat.scala 29:58]
node _T_250 = and(_T_247, _T_249) @[lsu_lsc_ctl.scala 261:71]
node _T_251 = or(_T_244, _T_250) @[lsu_lsc_ctl.scala 260:138]
node _T_252 = eq(io.lsu_pkt_r.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 262:17]
node _T_253 = and(_T_252, io.lsu_pkt_r.bits.by) @[lsu_lsc_ctl.scala 262:43]
node _T_254 = bits(_T_253, 0, 0) @[Bitwise.scala 72:15]
node _T_255 = mux(_T_254, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
node _T_256 = bits(lsu_ld_datafn_corr_r, 7, 7) @[lsu_lsc_ctl.scala 262:107]
node _T_257 = bits(_T_256, 0, 0) @[Bitwise.scala 72:15]
node _T_258 = mux(_T_257, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12]
node _T_259 = bits(lsu_ld_datafn_corr_r, 7, 0) @[lsu_lsc_ctl.scala 262:135]
node _T_260 = cat(_T_258, _T_259) @[Cat.scala 29:58]
node _T_261 = and(_T_255, _T_260) @[lsu_lsc_ctl.scala 262:71]
node _T_262 = or(_T_251, _T_261) @[lsu_lsc_ctl.scala 261:119]
node _T_263 = eq(io.lsu_pkt_r.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 263:17]
node _T_264 = and(_T_263, io.lsu_pkt_r.bits.half) @[lsu_lsc_ctl.scala 263:43]
node _T_265 = bits(_T_264, 0, 0) @[Bitwise.scala 72:15]
node _T_266 = mux(_T_265, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
node _T_267 = bits(lsu_ld_datafn_corr_r, 15, 15) @[lsu_lsc_ctl.scala 263:106]
node _T_268 = bits(_T_267, 0, 0) @[Bitwise.scala 72:15]
node _T_269 = mux(_T_268, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12]
node _T_270 = bits(lsu_ld_datafn_corr_r, 15, 0) @[lsu_lsc_ctl.scala 263:135]
node _T_271 = cat(_T_269, _T_270) @[Cat.scala 29:58]
node _T_272 = and(_T_266, _T_271) @[lsu_lsc_ctl.scala 263:71]
node _T_273 = or(_T_262, _T_272) @[lsu_lsc_ctl.scala 262:144]
node _T_274 = bits(io.lsu_pkt_r.bits.word, 0, 0) @[Bitwise.scala 72:15]
node _T_275 = mux(_T_274, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
node _T_276 = bits(lsu_ld_datafn_corr_r, 31, 0) @[lsu_lsc_ctl.scala 264:65]
node _T_277 = and(_T_275, _T_276) @[lsu_lsc_ctl.scala 264:43]
node _T_278 = or(_T_273, _T_277) @[lsu_lsc_ctl.scala 263:144]
io.lsu_result_corr_r <= _T_278 @[lsu_lsc_ctl.scala 260:27]

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src/main/scala/dec/dec.scala
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@ -86,7 +86,7 @@ class dec_IO extends Bundle with lib {
val dec_tlu_perfcnt3 = Output(Bool()) // toggles when slot0 perf counter 3 has an event inc
val dec_tlu_flush_lower_wb = Output(Bool())
val dec_lsu_valid_raw_d = Output(Bool())
val trace_rv_trace_pkt = (new trace_pkt_t) // trace packet
val trace_rv_trace_pkt = Output(new trace_pkt_t) // trace packet
// clock gating overrides from mcgc
val dec_tlu_misc_clk_override = Output(Bool()) // override misc clock domain gating

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target/scala-2.12/classes/dec/dec_IO.class
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