diff --git a/el2_ifu_mem_ctl.anno.json b/el2_ifu_mem_ctl.anno.json index 99d2b59f..4bb7d3ef 100644 --- a/el2_ifu_mem_ctl.anno.json +++ b/el2_ifu_mem_ctl.anno.json @@ -300,6 +300,13 @@ "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_data" ] }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rw_addr", + "sources":[ + "~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifc_fetch_addr_bf" + ] + }, { "class":"firrtl.transforms.CombinationalPath", "sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_debug_wr_data", diff --git a/el2_ifu_mem_ctl.fir b/el2_ifu_mem_ctl.fir index 68a2a5b8..03c705e5 100644 --- a/el2_ifu_mem_ctl.fir +++ b/el2_ifu_mem_ctl.fir @@ -95,209 +95,209 @@ circuit el2_ifu_mem_ctl : node _T_11 = or(_T_10, err_stop_fetch) @[el2_ifu_mem_ctl.scala 187:112] node _T_12 = or(_T_11, io.dec_tlu_flush_err_wb) @[el2_ifu_mem_ctl.scala 187:129] io.ic_dma_active <= _T_12 @[el2_ifu_mem_ctl.scala 187:20] - node _T_13 = and(ifu_bus_rsp_valid, bus_ifu_bus_clk_en) @[el2_ifu_mem_ctl.scala 188:44] - node _T_14 = and(_T_13, ifu_bus_rsp_ready) @[el2_ifu_mem_ctl.scala 188:65] - node _T_15 = andr(bus_new_data_beat_count) @[el2_ifu_mem_ctl.scala 188:111] - node _T_16 = and(_T_14, _T_15) @[el2_ifu_mem_ctl.scala 188:85] - node _T_17 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 189:5] - node _T_18 = and(_T_16, _T_17) @[el2_ifu_mem_ctl.scala 188:116] - node _T_19 = eq(miss_state, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 189:41] - node _T_20 = eq(miss_nxtstate, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 189:73] - node _T_21 = or(_T_19, _T_20) @[el2_ifu_mem_ctl.scala 189:57] - node _T_22 = and(_T_18, _T_21) @[el2_ifu_mem_ctl.scala 189:26] - node _T_23 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 189:93] - node scnd_miss_req_in = and(_T_22, _T_23) @[el2_ifu_mem_ctl.scala 189:91] - node ifu_bp_hit_taken_q_f = and(io.ifu_bp_hit_taken_f, io.ic_hit_f) @[el2_ifu_mem_ctl.scala 191:52] + node _T_13 = and(ifu_bus_rsp_valid, bus_ifu_bus_clk_en) @[el2_ifu_mem_ctl.scala 189:44] + node _T_14 = and(_T_13, ifu_bus_rsp_ready) @[el2_ifu_mem_ctl.scala 189:65] + node _T_15 = andr(bus_new_data_beat_count) @[el2_ifu_mem_ctl.scala 189:112] + node _T_16 = and(_T_14, _T_15) @[el2_ifu_mem_ctl.scala 189:85] + node _T_17 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 190:5] + node _T_18 = and(_T_16, _T_17) @[el2_ifu_mem_ctl.scala 189:118] + node _T_19 = eq(miss_state, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 190:41] + node _T_20 = eq(miss_nxtstate, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 190:73] + node _T_21 = or(_T_19, _T_20) @[el2_ifu_mem_ctl.scala 190:57] + node _T_22 = and(_T_18, _T_21) @[el2_ifu_mem_ctl.scala 190:26] + node _T_23 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 190:93] + node scnd_miss_req_in = and(_T_22, _T_23) @[el2_ifu_mem_ctl.scala 190:91] + node ifu_bp_hit_taken_q_f = and(io.ifu_bp_hit_taken_f, io.ic_hit_f) @[el2_ifu_mem_ctl.scala 192:52] node _T_24 = eq(UInt<3>("h00"), miss_state) @[Conditional.scala 37:30] when _T_24 : @[Conditional.scala 40:58] - node _T_25 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 195:45] - node _T_26 = and(ic_act_miss_f, _T_25) @[el2_ifu_mem_ctl.scala 195:43] - node _T_27 = bits(_T_26, 0, 0) @[el2_ifu_mem_ctl.scala 195:66] - node _T_28 = mux(_T_27, UInt<3>("h01"), UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 195:27] - miss_nxtstate <= _T_28 @[el2_ifu_mem_ctl.scala 195:21] - node _T_29 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 196:40] - node _T_30 = and(ic_act_miss_f, _T_29) @[el2_ifu_mem_ctl.scala 196:38] - miss_state_en <= _T_30 @[el2_ifu_mem_ctl.scala 196:21] + node _T_25 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 196:45] + node _T_26 = and(ic_act_miss_f, _T_25) @[el2_ifu_mem_ctl.scala 196:43] + node _T_27 = bits(_T_26, 0, 0) @[el2_ifu_mem_ctl.scala 196:66] + node _T_28 = mux(_T_27, UInt<3>("h01"), UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 196:27] + miss_nxtstate <= _T_28 @[el2_ifu_mem_ctl.scala 196:21] + node _T_29 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 197:40] + node _T_30 = and(ic_act_miss_f, _T_29) @[el2_ifu_mem_ctl.scala 197:38] + miss_state_en <= _T_30 @[el2_ifu_mem_ctl.scala 197:21] skip @[Conditional.scala 40:58] else : @[Conditional.scala 39:67] node _T_31 = eq(UInt<3>("h01"), miss_state) @[Conditional.scala 37:30] when _T_31 : @[Conditional.scala 39:67] - node _T_32 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 199:113] - node _T_33 = or(last_data_recieved_ff, _T_32) @[el2_ifu_mem_ctl.scala 199:93] - node _T_34 = and(ic_byp_hit_f, _T_33) @[el2_ifu_mem_ctl.scala 199:67] - node _T_35 = and(_T_34, uncacheable_miss_ff) @[el2_ifu_mem_ctl.scala 199:127] - node _T_36 = or(io.dec_tlu_force_halt, _T_35) @[el2_ifu_mem_ctl.scala 199:51] - node _T_37 = bits(_T_36, 0, 0) @[el2_ifu_mem_ctl.scala 199:152] - node _T_38 = eq(last_data_recieved_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 200:30] - node _T_39 = and(ic_byp_hit_f, _T_38) @[el2_ifu_mem_ctl.scala 200:27] - node _T_40 = and(_T_39, uncacheable_miss_ff) @[el2_ifu_mem_ctl.scala 200:53] - node _T_41 = bits(_T_40, 0, 0) @[el2_ifu_mem_ctl.scala 200:77] - node _T_42 = eq(ic_byp_hit_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 201:16] - node _T_43 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 201:32] - node _T_44 = and(_T_42, _T_43) @[el2_ifu_mem_ctl.scala 201:30] - node _T_45 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 201:72] - node _T_46 = and(_T_44, _T_45) @[el2_ifu_mem_ctl.scala 201:52] - node _T_47 = and(_T_46, uncacheable_miss_ff) @[el2_ifu_mem_ctl.scala 201:85] - node _T_48 = bits(_T_47, 0, 0) @[el2_ifu_mem_ctl.scala 201:109] - node _T_49 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 202:36] - node _T_50 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 202:51] - node _T_51 = and(_T_49, _T_50) @[el2_ifu_mem_ctl.scala 202:49] - node _T_52 = bits(_T_51, 0, 0) @[el2_ifu_mem_ctl.scala 202:73] - node _T_53 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 203:35] - node _T_54 = and(ic_byp_hit_f, _T_53) @[el2_ifu_mem_ctl.scala 203:33] - node _T_55 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 203:76] - node _T_56 = eq(_T_55, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 203:57] - node _T_57 = and(_T_54, _T_56) @[el2_ifu_mem_ctl.scala 203:55] - node _T_58 = eq(ifu_bp_hit_taken_q_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 203:91] - node _T_59 = and(_T_57, _T_58) @[el2_ifu_mem_ctl.scala 203:89] - node _T_60 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 203:115] - node _T_61 = and(_T_59, _T_60) @[el2_ifu_mem_ctl.scala 203:113] - node _T_62 = bits(_T_61, 0, 0) @[el2_ifu_mem_ctl.scala 203:137] - node _T_63 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 204:41] - node _T_64 = and(bus_ifu_wr_en_ff, _T_63) @[el2_ifu_mem_ctl.scala 204:39] - node _T_65 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 204:82] - node _T_66 = eq(_T_65, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 204:63] - node _T_67 = and(_T_64, _T_66) @[el2_ifu_mem_ctl.scala 204:61] - node _T_68 = eq(ifu_bp_hit_taken_q_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 204:97] - node _T_69 = and(_T_67, _T_68) @[el2_ifu_mem_ctl.scala 204:95] - node _T_70 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 204:121] - node _T_71 = and(_T_69, _T_70) @[el2_ifu_mem_ctl.scala 204:119] - node _T_72 = bits(_T_71, 0, 0) @[el2_ifu_mem_ctl.scala 204:143] - node _T_73 = eq(ic_byp_hit_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 205:22] - node _T_74 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 205:40] - node _T_75 = and(_T_73, _T_74) @[el2_ifu_mem_ctl.scala 205:37] - node _T_76 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 205:81] - node _T_77 = and(_T_75, _T_76) @[el2_ifu_mem_ctl.scala 205:60] - node _T_78 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 205:102] - node _T_79 = and(_T_77, _T_78) @[el2_ifu_mem_ctl.scala 205:100] - node _T_80 = bits(_T_79, 0, 0) @[el2_ifu_mem_ctl.scala 205:124] - node _T_81 = or(io.exu_flush_final, ifu_bp_hit_taken_q_f) @[el2_ifu_mem_ctl.scala 206:44] - node _T_82 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 206:89] - node _T_83 = eq(_T_82, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 206:70] - node _T_84 = and(_T_81, _T_83) @[el2_ifu_mem_ctl.scala 206:68] - node _T_85 = bits(_T_84, 0, 0) @[el2_ifu_mem_ctl.scala 206:103] - node _T_86 = mux(_T_85, UInt<3>("h02"), UInt<3>("h00")) @[el2_ifu_mem_ctl.scala 206:22] - node _T_87 = mux(_T_80, UInt<3>("h00"), _T_86) @[el2_ifu_mem_ctl.scala 205:20] - node _T_88 = mux(_T_72, UInt<3>("h06"), _T_87) @[el2_ifu_mem_ctl.scala 204:20] - node _T_89 = mux(_T_62, UInt<3>("h06"), _T_88) @[el2_ifu_mem_ctl.scala 203:18] - node _T_90 = mux(_T_52, UInt<3>("h00"), _T_89) @[el2_ifu_mem_ctl.scala 202:16] - node _T_91 = mux(_T_48, UInt<3>("h04"), _T_90) @[el2_ifu_mem_ctl.scala 201:14] - node _T_92 = mux(_T_41, UInt<3>("h03"), _T_91) @[el2_ifu_mem_ctl.scala 200:12] - node _T_93 = mux(_T_37, UInt<3>("h00"), _T_92) @[el2_ifu_mem_ctl.scala 199:27] - miss_nxtstate <= _T_93 @[el2_ifu_mem_ctl.scala 199:21] - node _T_94 = or(io.dec_tlu_force_halt, io.exu_flush_final) @[el2_ifu_mem_ctl.scala 207:46] - node _T_95 = or(_T_94, ic_byp_hit_f) @[el2_ifu_mem_ctl.scala 207:67] - node _T_96 = or(_T_95, ifu_bp_hit_taken_q_f) @[el2_ifu_mem_ctl.scala 207:82] - node _T_97 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 207:125] - node _T_98 = or(_T_96, _T_97) @[el2_ifu_mem_ctl.scala 207:105] - node _T_99 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 207:160] - node _T_100 = and(bus_ifu_wr_en_ff, _T_99) @[el2_ifu_mem_ctl.scala 207:158] - node _T_101 = or(_T_98, _T_100) @[el2_ifu_mem_ctl.scala 207:138] - miss_state_en <= _T_101 @[el2_ifu_mem_ctl.scala 207:21] + node _T_32 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 200:113] + node _T_33 = or(last_data_recieved_ff, _T_32) @[el2_ifu_mem_ctl.scala 200:93] + node _T_34 = and(ic_byp_hit_f, _T_33) @[el2_ifu_mem_ctl.scala 200:67] + node _T_35 = and(_T_34, uncacheable_miss_ff) @[el2_ifu_mem_ctl.scala 200:127] + node _T_36 = or(io.dec_tlu_force_halt, _T_35) @[el2_ifu_mem_ctl.scala 200:51] + node _T_37 = bits(_T_36, 0, 0) @[el2_ifu_mem_ctl.scala 200:152] + node _T_38 = eq(last_data_recieved_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 201:30] + node _T_39 = and(ic_byp_hit_f, _T_38) @[el2_ifu_mem_ctl.scala 201:27] + node _T_40 = and(_T_39, uncacheable_miss_ff) @[el2_ifu_mem_ctl.scala 201:53] + node _T_41 = bits(_T_40, 0, 0) @[el2_ifu_mem_ctl.scala 201:77] + node _T_42 = eq(ic_byp_hit_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 202:16] + node _T_43 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 202:32] + node _T_44 = and(_T_42, _T_43) @[el2_ifu_mem_ctl.scala 202:30] + node _T_45 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 202:72] + node _T_46 = and(_T_44, _T_45) @[el2_ifu_mem_ctl.scala 202:52] + node _T_47 = and(_T_46, uncacheable_miss_ff) @[el2_ifu_mem_ctl.scala 202:85] + node _T_48 = bits(_T_47, 0, 0) @[el2_ifu_mem_ctl.scala 202:109] + node _T_49 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 203:36] + node _T_50 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 203:51] + node _T_51 = and(_T_49, _T_50) @[el2_ifu_mem_ctl.scala 203:49] + node _T_52 = bits(_T_51, 0, 0) @[el2_ifu_mem_ctl.scala 203:73] + node _T_53 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 204:35] + node _T_54 = and(ic_byp_hit_f, _T_53) @[el2_ifu_mem_ctl.scala 204:33] + node _T_55 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 204:76] + node _T_56 = eq(_T_55, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 204:57] + node _T_57 = and(_T_54, _T_56) @[el2_ifu_mem_ctl.scala 204:55] + node _T_58 = eq(ifu_bp_hit_taken_q_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 204:91] + node _T_59 = and(_T_57, _T_58) @[el2_ifu_mem_ctl.scala 204:89] + node _T_60 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 204:115] + node _T_61 = and(_T_59, _T_60) @[el2_ifu_mem_ctl.scala 204:113] + node _T_62 = bits(_T_61, 0, 0) @[el2_ifu_mem_ctl.scala 204:137] + node _T_63 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 205:41] + node _T_64 = and(bus_ifu_wr_en_ff, _T_63) @[el2_ifu_mem_ctl.scala 205:39] + node _T_65 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 205:82] + node _T_66 = eq(_T_65, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 205:63] + node _T_67 = and(_T_64, _T_66) @[el2_ifu_mem_ctl.scala 205:61] + node _T_68 = eq(ifu_bp_hit_taken_q_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 205:97] + node _T_69 = and(_T_67, _T_68) @[el2_ifu_mem_ctl.scala 205:95] + node _T_70 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 205:121] + node _T_71 = and(_T_69, _T_70) @[el2_ifu_mem_ctl.scala 205:119] + node _T_72 = bits(_T_71, 0, 0) @[el2_ifu_mem_ctl.scala 205:143] + node _T_73 = eq(ic_byp_hit_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 206:22] + node _T_74 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 206:40] + node _T_75 = and(_T_73, _T_74) @[el2_ifu_mem_ctl.scala 206:37] + node _T_76 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 206:81] + node _T_77 = and(_T_75, _T_76) @[el2_ifu_mem_ctl.scala 206:60] + node _T_78 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 206:102] + node _T_79 = and(_T_77, _T_78) @[el2_ifu_mem_ctl.scala 206:100] + node _T_80 = bits(_T_79, 0, 0) @[el2_ifu_mem_ctl.scala 206:124] + node _T_81 = or(io.exu_flush_final, ifu_bp_hit_taken_q_f) @[el2_ifu_mem_ctl.scala 207:44] + node _T_82 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 207:89] + node _T_83 = eq(_T_82, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 207:70] + node _T_84 = and(_T_81, _T_83) @[el2_ifu_mem_ctl.scala 207:68] + node _T_85 = bits(_T_84, 0, 0) @[el2_ifu_mem_ctl.scala 207:103] + node _T_86 = mux(_T_85, UInt<3>("h02"), UInt<3>("h00")) @[el2_ifu_mem_ctl.scala 207:22] + node _T_87 = mux(_T_80, UInt<3>("h00"), _T_86) @[el2_ifu_mem_ctl.scala 206:20] + node _T_88 = mux(_T_72, UInt<3>("h06"), _T_87) @[el2_ifu_mem_ctl.scala 205:20] + node _T_89 = mux(_T_62, UInt<3>("h06"), _T_88) @[el2_ifu_mem_ctl.scala 204:18] + node _T_90 = mux(_T_52, UInt<3>("h00"), _T_89) @[el2_ifu_mem_ctl.scala 203:16] + node _T_91 = mux(_T_48, UInt<3>("h04"), _T_90) @[el2_ifu_mem_ctl.scala 202:14] + node _T_92 = mux(_T_41, UInt<3>("h03"), _T_91) @[el2_ifu_mem_ctl.scala 201:12] + node _T_93 = mux(_T_37, UInt<3>("h00"), _T_92) @[el2_ifu_mem_ctl.scala 200:27] + miss_nxtstate <= _T_93 @[el2_ifu_mem_ctl.scala 200:21] + node _T_94 = or(io.dec_tlu_force_halt, io.exu_flush_final) @[el2_ifu_mem_ctl.scala 208:46] + node _T_95 = or(_T_94, ic_byp_hit_f) @[el2_ifu_mem_ctl.scala 208:67] + node _T_96 = or(_T_95, ifu_bp_hit_taken_q_f) @[el2_ifu_mem_ctl.scala 208:82] + node _T_97 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 208:125] + node _T_98 = or(_T_96, _T_97) @[el2_ifu_mem_ctl.scala 208:105] + node _T_99 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 208:160] + node _T_100 = and(bus_ifu_wr_en_ff, _T_99) @[el2_ifu_mem_ctl.scala 208:158] + node _T_101 = or(_T_98, _T_100) @[el2_ifu_mem_ctl.scala 208:138] + miss_state_en <= _T_101 @[el2_ifu_mem_ctl.scala 208:21] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_102 = eq(UInt<3>("h04"), miss_state) @[Conditional.scala 37:30] when _T_102 : @[Conditional.scala 39:67] - miss_nxtstate <= UInt<3>("h00") @[el2_ifu_mem_ctl.scala 210:21] - node _T_103 = or(io.exu_flush_final, flush_final_f) @[el2_ifu_mem_ctl.scala 211:43] - node _T_104 = or(_T_103, ic_byp_hit_f) @[el2_ifu_mem_ctl.scala 211:59] - node _T_105 = or(_T_104, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 211:74] - miss_state_en <= _T_105 @[el2_ifu_mem_ctl.scala 211:21] + miss_nxtstate <= UInt<3>("h00") @[el2_ifu_mem_ctl.scala 211:21] + node _T_103 = or(io.exu_flush_final, flush_final_f) @[el2_ifu_mem_ctl.scala 212:43] + node _T_104 = or(_T_103, ic_byp_hit_f) @[el2_ifu_mem_ctl.scala 212:59] + node _T_105 = or(_T_104, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 212:74] + miss_state_en <= _T_105 @[el2_ifu_mem_ctl.scala 212:21] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_106 = eq(UInt<3>("h06"), miss_state) @[Conditional.scala 37:30] when _T_106 : @[Conditional.scala 39:67] - node _T_107 = or(io.exu_flush_final, ifu_bp_hit_taken_q_f) @[el2_ifu_mem_ctl.scala 214:49] - node _T_108 = or(_T_107, stream_eol_f) @[el2_ifu_mem_ctl.scala 214:72] - node _T_109 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 214:108] - node _T_110 = eq(_T_109, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 214:89] - node _T_111 = and(_T_108, _T_110) @[el2_ifu_mem_ctl.scala 214:87] - node _T_112 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 214:124] - node _T_113 = and(_T_111, _T_112) @[el2_ifu_mem_ctl.scala 214:122] - node _T_114 = bits(_T_113, 0, 0) @[el2_ifu_mem_ctl.scala 214:148] - node _T_115 = mux(_T_114, UInt<3>("h02"), UInt<3>("h00")) @[el2_ifu_mem_ctl.scala 214:27] - miss_nxtstate <= _T_115 @[el2_ifu_mem_ctl.scala 214:21] - node _T_116 = or(io.exu_flush_final, ifu_bp_hit_taken_q_f) @[el2_ifu_mem_ctl.scala 215:43] - node _T_117 = or(_T_116, stream_eol_f) @[el2_ifu_mem_ctl.scala 215:67] - node _T_118 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 215:105] - node _T_119 = or(_T_117, _T_118) @[el2_ifu_mem_ctl.scala 215:84] - node _T_120 = or(_T_119, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 215:118] - miss_state_en <= _T_120 @[el2_ifu_mem_ctl.scala 215:21] + node _T_107 = or(io.exu_flush_final, ifu_bp_hit_taken_q_f) @[el2_ifu_mem_ctl.scala 215:49] + node _T_108 = or(_T_107, stream_eol_f) @[el2_ifu_mem_ctl.scala 215:72] + node _T_109 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 215:108] + node _T_110 = eq(_T_109, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 215:89] + node _T_111 = and(_T_108, _T_110) @[el2_ifu_mem_ctl.scala 215:87] + node _T_112 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 215:124] + node _T_113 = and(_T_111, _T_112) @[el2_ifu_mem_ctl.scala 215:122] + node _T_114 = bits(_T_113, 0, 0) @[el2_ifu_mem_ctl.scala 215:148] + node _T_115 = mux(_T_114, UInt<3>("h02"), UInt<3>("h00")) @[el2_ifu_mem_ctl.scala 215:27] + miss_nxtstate <= _T_115 @[el2_ifu_mem_ctl.scala 215:21] + node _T_116 = or(io.exu_flush_final, ifu_bp_hit_taken_q_f) @[el2_ifu_mem_ctl.scala 216:43] + node _T_117 = or(_T_116, stream_eol_f) @[el2_ifu_mem_ctl.scala 216:67] + node _T_118 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 216:105] + node _T_119 = or(_T_117, _T_118) @[el2_ifu_mem_ctl.scala 216:84] + node _T_120 = or(_T_119, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 216:118] + miss_state_en <= _T_120 @[el2_ifu_mem_ctl.scala 216:21] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_121 = eq(UInt<3>("h03"), miss_state) @[Conditional.scala 37:30] when _T_121 : @[Conditional.scala 39:67] - node _T_122 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 218:69] - node _T_123 = eq(_T_122, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 218:50] - node _T_124 = and(io.exu_flush_final, _T_123) @[el2_ifu_mem_ctl.scala 218:48] - node _T_125 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 218:84] - node _T_126 = and(_T_124, _T_125) @[el2_ifu_mem_ctl.scala 218:82] - node _T_127 = bits(_T_126, 0, 0) @[el2_ifu_mem_ctl.scala 218:108] - node _T_128 = mux(_T_127, UInt<3>("h02"), UInt<3>("h00")) @[el2_ifu_mem_ctl.scala 218:27] - miss_nxtstate <= _T_128 @[el2_ifu_mem_ctl.scala 218:21] - node _T_129 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 219:63] - node _T_130 = or(io.exu_flush_final, _T_129) @[el2_ifu_mem_ctl.scala 219:43] - node _T_131 = or(_T_130, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 219:76] - miss_state_en <= _T_131 @[el2_ifu_mem_ctl.scala 219:21] + node _T_122 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 219:69] + node _T_123 = eq(_T_122, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 219:50] + node _T_124 = and(io.exu_flush_final, _T_123) @[el2_ifu_mem_ctl.scala 219:48] + node _T_125 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 219:84] + node _T_126 = and(_T_124, _T_125) @[el2_ifu_mem_ctl.scala 219:82] + node _T_127 = bits(_T_126, 0, 0) @[el2_ifu_mem_ctl.scala 219:108] + node _T_128 = mux(_T_127, UInt<3>("h02"), UInt<3>("h00")) @[el2_ifu_mem_ctl.scala 219:27] + miss_nxtstate <= _T_128 @[el2_ifu_mem_ctl.scala 219:21] + node _T_129 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 220:63] + node _T_130 = or(io.exu_flush_final, _T_129) @[el2_ifu_mem_ctl.scala 220:43] + node _T_131 = or(_T_130, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 220:76] + miss_state_en <= _T_131 @[el2_ifu_mem_ctl.scala 220:21] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_132 = eq(UInt<3>("h02"), miss_state) @[Conditional.scala 37:30] when _T_132 : @[Conditional.scala 39:67] - node _T_133 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 222:71] - node _T_134 = eq(_T_133, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 222:52] - node _T_135 = and(ic_miss_under_miss_f, _T_134) @[el2_ifu_mem_ctl.scala 222:50] - node _T_136 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 222:86] - node _T_137 = and(_T_135, _T_136) @[el2_ifu_mem_ctl.scala 222:84] - node _T_138 = bits(_T_137, 0, 0) @[el2_ifu_mem_ctl.scala 222:110] - node _T_139 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 223:56] - node _T_140 = eq(_T_139, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 223:37] - node _T_141 = and(ic_ignore_2nd_miss_f, _T_140) @[el2_ifu_mem_ctl.scala 223:35] - node _T_142 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 223:71] - node _T_143 = and(_T_141, _T_142) @[el2_ifu_mem_ctl.scala 223:69] - node _T_144 = bits(_T_143, 0, 0) @[el2_ifu_mem_ctl.scala 223:95] - node _T_145 = mux(_T_144, UInt<3>("h07"), UInt<3>("h00")) @[el2_ifu_mem_ctl.scala 223:12] - node _T_146 = mux(_T_138, UInt<3>("h05"), _T_145) @[el2_ifu_mem_ctl.scala 222:27] - miss_nxtstate <= _T_146 @[el2_ifu_mem_ctl.scala 222:21] - node _T_147 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 224:42] - node _T_148 = or(_T_147, ic_miss_under_miss_f) @[el2_ifu_mem_ctl.scala 224:55] - node _T_149 = or(_T_148, ic_ignore_2nd_miss_f) @[el2_ifu_mem_ctl.scala 224:78] - node _T_150 = or(_T_149, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 224:101] - miss_state_en <= _T_150 @[el2_ifu_mem_ctl.scala 224:21] + node _T_133 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 223:71] + node _T_134 = eq(_T_133, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 223:52] + node _T_135 = and(ic_miss_under_miss_f, _T_134) @[el2_ifu_mem_ctl.scala 223:50] + node _T_136 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 223:86] + node _T_137 = and(_T_135, _T_136) @[el2_ifu_mem_ctl.scala 223:84] + node _T_138 = bits(_T_137, 0, 0) @[el2_ifu_mem_ctl.scala 223:110] + node _T_139 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 224:56] + node _T_140 = eq(_T_139, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 224:37] + node _T_141 = and(ic_ignore_2nd_miss_f, _T_140) @[el2_ifu_mem_ctl.scala 224:35] + node _T_142 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 224:71] + node _T_143 = and(_T_141, _T_142) @[el2_ifu_mem_ctl.scala 224:69] + node _T_144 = bits(_T_143, 0, 0) @[el2_ifu_mem_ctl.scala 224:95] + node _T_145 = mux(_T_144, UInt<3>("h07"), UInt<3>("h00")) @[el2_ifu_mem_ctl.scala 224:12] + node _T_146 = mux(_T_138, UInt<3>("h05"), _T_145) @[el2_ifu_mem_ctl.scala 223:27] + miss_nxtstate <= _T_146 @[el2_ifu_mem_ctl.scala 223:21] + node _T_147 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 225:42] + node _T_148 = or(_T_147, ic_miss_under_miss_f) @[el2_ifu_mem_ctl.scala 225:55] + node _T_149 = or(_T_148, ic_ignore_2nd_miss_f) @[el2_ifu_mem_ctl.scala 225:78] + node _T_150 = or(_T_149, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 225:101] + miss_state_en <= _T_150 @[el2_ifu_mem_ctl.scala 225:21] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_151 = eq(UInt<3>("h05"), miss_state) @[Conditional.scala 37:30] when _T_151 : @[Conditional.scala 39:67] - node _T_152 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 228:31] - node _T_153 = bits(_T_152, 0, 0) @[el2_ifu_mem_ctl.scala 228:44] - node _T_154 = mux(_T_153, UInt<3>("h00"), UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 228:12] - node _T_155 = mux(io.exu_flush_final, _T_154, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 227:62] - node _T_156 = mux(io.dec_tlu_force_halt, UInt<3>("h00"), _T_155) @[el2_ifu_mem_ctl.scala 227:27] - miss_nxtstate <= _T_156 @[el2_ifu_mem_ctl.scala 227:21] - node _T_157 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 229:42] - node _T_158 = or(_T_157, io.exu_flush_final) @[el2_ifu_mem_ctl.scala 229:55] - node _T_159 = or(_T_158, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 229:76] - miss_state_en <= _T_159 @[el2_ifu_mem_ctl.scala 229:21] + node _T_152 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 229:31] + node _T_153 = bits(_T_152, 0, 0) @[el2_ifu_mem_ctl.scala 229:44] + node _T_154 = mux(_T_153, UInt<3>("h00"), UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 229:12] + node _T_155 = mux(io.exu_flush_final, _T_154, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 228:62] + node _T_156 = mux(io.dec_tlu_force_halt, UInt<3>("h00"), _T_155) @[el2_ifu_mem_ctl.scala 228:27] + miss_nxtstate <= _T_156 @[el2_ifu_mem_ctl.scala 228:21] + node _T_157 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 230:42] + node _T_158 = or(_T_157, io.exu_flush_final) @[el2_ifu_mem_ctl.scala 230:55] + node _T_159 = or(_T_158, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 230:76] + miss_state_en <= _T_159 @[el2_ifu_mem_ctl.scala 230:21] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_160 = eq(UInt<3>("h07"), miss_state) @[Conditional.scala 37:30] when _T_160 : @[Conditional.scala 39:67] - node _T_161 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 233:31] - node _T_162 = bits(_T_161, 0, 0) @[el2_ifu_mem_ctl.scala 233:44] - node _T_163 = mux(_T_162, UInt<3>("h00"), UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 233:12] - node _T_164 = mux(io.exu_flush_final, _T_163, UInt<3>("h00")) @[el2_ifu_mem_ctl.scala 232:62] - node _T_165 = mux(io.dec_tlu_force_halt, UInt<3>("h00"), _T_164) @[el2_ifu_mem_ctl.scala 232:27] - miss_nxtstate <= _T_165 @[el2_ifu_mem_ctl.scala 232:21] - node _T_166 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 234:42] - node _T_167 = or(_T_166, io.exu_flush_final) @[el2_ifu_mem_ctl.scala 234:55] - node _T_168 = or(_T_167, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 234:76] - miss_state_en <= _T_168 @[el2_ifu_mem_ctl.scala 234:21] + node _T_161 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 234:31] + node _T_162 = bits(_T_161, 0, 0) @[el2_ifu_mem_ctl.scala 234:44] + node _T_163 = mux(_T_162, UInt<3>("h00"), UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 234:12] + node _T_164 = mux(io.exu_flush_final, _T_163, UInt<3>("h00")) @[el2_ifu_mem_ctl.scala 233:62] + node _T_165 = mux(io.dec_tlu_force_halt, UInt<3>("h00"), _T_164) @[el2_ifu_mem_ctl.scala 233:27] + miss_nxtstate <= _T_165 @[el2_ifu_mem_ctl.scala 233:21] + node _T_166 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 235:42] + node _T_167 = or(_T_166, io.exu_flush_final) @[el2_ifu_mem_ctl.scala 235:55] + node _T_168 = or(_T_167, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 235:76] + miss_state_en <= _T_168 @[el2_ifu_mem_ctl.scala 235:21] skip @[Conditional.scala 39:67] - node _T_169 = bits(miss_state_en, 0, 0) @[el2_ifu_mem_ctl.scala 237:61] + node _T_169 = bits(miss_state_en, 0, 0) @[el2_ifu_mem_ctl.scala 238:61] reg _T_170 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_169 : @[Reg.scala 28:19] _T_170 <= miss_nxtstate @[Reg.scala 28:23] skip @[Reg.scala 28:19] - miss_state <= _T_170 @[el2_ifu_mem_ctl.scala 237:14] + miss_state <= _T_170 @[el2_ifu_mem_ctl.scala 238:14] wire crit_byp_hit_f : UInt<1> crit_byp_hit_f <= UInt<1>("h00") wire way_status_mb_scnd_ff : UInt<1> @@ -318,294 +318,294 @@ circuit el2_ifu_mem_ctl : bus_rd_addr_count <= UInt<1>("h00") wire ifu_bus_rid_ff : UInt<3> ifu_bus_rid_ff <= UInt<1>("h00") - node _T_171 = neq(miss_state, UInt<3>("h00")) @[el2_ifu_mem_ctl.scala 248:30] - miss_pending <= _T_171 @[el2_ifu_mem_ctl.scala 248:16] - node _T_172 = eq(miss_state, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 249:39] - node _T_173 = eq(miss_state, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 249:73] - node _T_174 = eq(flush_final_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 249:95] - node _T_175 = and(_T_173, _T_174) @[el2_ifu_mem_ctl.scala 249:93] - node crit_wd_byp_ok_ff = or(_T_172, _T_175) @[el2_ifu_mem_ctl.scala 249:58] - node _T_176 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 250:57] - node _T_177 = eq(_T_176, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 250:38] - node _T_178 = and(miss_pending, _T_177) @[el2_ifu_mem_ctl.scala 250:36] - node _T_179 = eq(miss_state, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 250:86] - node _T_180 = and(_T_179, io.exu_flush_final) @[el2_ifu_mem_ctl.scala 250:106] - node _T_181 = eq(_T_180, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 250:72] - node _T_182 = and(_T_178, _T_181) @[el2_ifu_mem_ctl.scala 250:70] - node _T_183 = eq(miss_state, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 251:37] - node _T_184 = and(_T_183, crit_byp_hit_f) @[el2_ifu_mem_ctl.scala 251:57] - node _T_185 = eq(_T_184, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 251:23] - node _T_186 = and(_T_182, _T_185) @[el2_ifu_mem_ctl.scala 250:128] - node _T_187 = or(_T_186, ic_act_miss_f) @[el2_ifu_mem_ctl.scala 251:77] - node _T_188 = eq(miss_nxtstate, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 252:36] - node _T_189 = and(miss_pending, _T_188) @[el2_ifu_mem_ctl.scala 252:19] - node sel_hold_imb = or(_T_187, _T_189) @[el2_ifu_mem_ctl.scala 251:93] - node _T_190 = eq(miss_state, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 254:40] - node _T_191 = or(_T_190, ic_miss_under_miss_f) @[el2_ifu_mem_ctl.scala 254:57] - node _T_192 = eq(flush_final_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 254:83] - node sel_hold_imb_scnd = and(_T_191, _T_192) @[el2_ifu_mem_ctl.scala 254:81] - node _T_193 = eq(miss_state, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 255:46] - node way_status_mb_scnd_in = mux(_T_193, way_status_mb_scnd_ff, way_status) @[el2_ifu_mem_ctl.scala 255:34] - node _T_194 = eq(miss_state, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 257:40] - node _T_195 = eq(reset_all_tags, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 257:96] + node _T_171 = neq(miss_state, UInt<3>("h00")) @[el2_ifu_mem_ctl.scala 249:30] + miss_pending <= _T_171 @[el2_ifu_mem_ctl.scala 249:16] + node _T_172 = eq(miss_state, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 250:39] + node _T_173 = eq(miss_state, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 250:73] + node _T_174 = eq(flush_final_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 250:95] + node _T_175 = and(_T_173, _T_174) @[el2_ifu_mem_ctl.scala 250:93] + node crit_wd_byp_ok_ff = or(_T_172, _T_175) @[el2_ifu_mem_ctl.scala 250:58] + node _T_176 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 251:57] + node _T_177 = eq(_T_176, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 251:38] + node _T_178 = and(miss_pending, _T_177) @[el2_ifu_mem_ctl.scala 251:36] + node _T_179 = eq(miss_state, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 251:86] + node _T_180 = and(_T_179, io.exu_flush_final) @[el2_ifu_mem_ctl.scala 251:106] + node _T_181 = eq(_T_180, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 251:72] + node _T_182 = and(_T_178, _T_181) @[el2_ifu_mem_ctl.scala 251:70] + node _T_183 = eq(miss_state, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 252:37] + node _T_184 = and(_T_183, crit_byp_hit_f) @[el2_ifu_mem_ctl.scala 252:57] + node _T_185 = eq(_T_184, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 252:23] + node _T_186 = and(_T_182, _T_185) @[el2_ifu_mem_ctl.scala 251:128] + node _T_187 = or(_T_186, ic_act_miss_f) @[el2_ifu_mem_ctl.scala 252:77] + node _T_188 = eq(miss_nxtstate, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 253:36] + node _T_189 = and(miss_pending, _T_188) @[el2_ifu_mem_ctl.scala 253:19] + node sel_hold_imb = or(_T_187, _T_189) @[el2_ifu_mem_ctl.scala 252:93] + node _T_190 = eq(miss_state, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 255:40] + node _T_191 = or(_T_190, ic_miss_under_miss_f) @[el2_ifu_mem_ctl.scala 255:57] + node _T_192 = eq(flush_final_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 255:83] + node sel_hold_imb_scnd = and(_T_191, _T_192) @[el2_ifu_mem_ctl.scala 255:81] + node _T_193 = eq(miss_state, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 256:46] + node way_status_mb_scnd_in = mux(_T_193, way_status_mb_scnd_ff, way_status) @[el2_ifu_mem_ctl.scala 256:34] + node _T_194 = eq(miss_state, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 258:40] + node _T_195 = eq(reset_all_tags, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 258:96] node _T_196 = bits(_T_195, 0, 0) @[Bitwise.scala 72:15] node _T_197 = mux(_T_196, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_198 = and(_T_197, ic_tag_valid) @[el2_ifu_mem_ctl.scala 257:113] - node tagv_mb_scnd_in = mux(_T_194, tagv_mb_scnd_ff, _T_198) @[el2_ifu_mem_ctl.scala 257:28] - node _T_199 = bits(sel_hold_imb_scnd, 0, 0) @[el2_ifu_mem_ctl.scala 258:56] - node uncacheable_miss_scnd_in = mux(_T_199, uncacheable_miss_scnd_ff, io.ifc_fetch_uncacheable_bf) @[el2_ifu_mem_ctl.scala 258:37] - reg _T_200 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 259:38] - _T_200 <= uncacheable_miss_scnd_in @[el2_ifu_mem_ctl.scala 259:38] - uncacheable_miss_scnd_ff <= _T_200 @[el2_ifu_mem_ctl.scala 259:28] - node _T_201 = bits(sel_hold_imb_scnd, 0, 0) @[el2_ifu_mem_ctl.scala 260:43] - node imb_scnd_in = mux(_T_201, imb_scnd_ff, io.ifc_fetch_addr_bf) @[el2_ifu_mem_ctl.scala 260:24] - reg _T_202 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 261:25] - _T_202 <= imb_scnd_in @[el2_ifu_mem_ctl.scala 261:25] - imb_scnd_ff <= _T_202 @[el2_ifu_mem_ctl.scala 261:15] - reg _T_203 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 262:35] - _T_203 <= way_status_mb_scnd_in @[el2_ifu_mem_ctl.scala 262:35] - way_status_mb_scnd_ff <= _T_203 @[el2_ifu_mem_ctl.scala 262:25] - reg _T_204 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 263:29] - _T_204 <= tagv_mb_scnd_in @[el2_ifu_mem_ctl.scala 263:29] - tagv_mb_scnd_ff <= _T_204 @[el2_ifu_mem_ctl.scala 263:19] + node _T_198 = and(_T_197, ic_tag_valid) @[el2_ifu_mem_ctl.scala 258:113] + node tagv_mb_scnd_in = mux(_T_194, tagv_mb_scnd_ff, _T_198) @[el2_ifu_mem_ctl.scala 258:28] + node _T_199 = bits(sel_hold_imb_scnd, 0, 0) @[el2_ifu_mem_ctl.scala 259:56] + node uncacheable_miss_scnd_in = mux(_T_199, uncacheable_miss_scnd_ff, io.ifc_fetch_uncacheable_bf) @[el2_ifu_mem_ctl.scala 259:37] + reg _T_200 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 260:38] + _T_200 <= uncacheable_miss_scnd_in @[el2_ifu_mem_ctl.scala 260:38] + uncacheable_miss_scnd_ff <= _T_200 @[el2_ifu_mem_ctl.scala 260:28] + node _T_201 = bits(sel_hold_imb_scnd, 0, 0) @[el2_ifu_mem_ctl.scala 261:43] + node imb_scnd_in = mux(_T_201, imb_scnd_ff, io.ifc_fetch_addr_bf) @[el2_ifu_mem_ctl.scala 261:24] + reg _T_202 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 262:25] + _T_202 <= imb_scnd_in @[el2_ifu_mem_ctl.scala 262:25] + imb_scnd_ff <= _T_202 @[el2_ifu_mem_ctl.scala 262:15] + reg _T_203 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 263:35] + _T_203 <= way_status_mb_scnd_in @[el2_ifu_mem_ctl.scala 263:35] + way_status_mb_scnd_ff <= _T_203 @[el2_ifu_mem_ctl.scala 263:25] + reg _T_204 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 264:29] + _T_204 <= tagv_mb_scnd_in @[el2_ifu_mem_ctl.scala 264:29] + tagv_mb_scnd_ff <= _T_204 @[el2_ifu_mem_ctl.scala 264:19] node _T_205 = bits(bus_ifu_wr_en_ff, 0, 0) @[Bitwise.scala 72:15] node _T_206 = mux(_T_205, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node ic_wr_addr_bits_hi_3 = and(ifu_bus_rid_ff, _T_206) @[el2_ifu_mem_ctl.scala 266:45] + node ic_wr_addr_bits_hi_3 = and(ifu_bus_rid_ff, _T_206) @[el2_ifu_mem_ctl.scala 267:45] wire ifc_iccm_access_f : UInt<1> ifc_iccm_access_f <= UInt<1>("h00") wire ifc_region_acc_fault_final_f : UInt<1> ifc_region_acc_fault_final_f <= UInt<1>("h00") - node _T_207 = eq(ifc_iccm_access_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 269:48] - node _T_208 = and(ifc_fetch_req_f, _T_207) @[el2_ifu_mem_ctl.scala 269:46] - node _T_209 = eq(ifc_region_acc_fault_final_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 269:69] - node fetch_req_icache_f = and(_T_208, _T_209) @[el2_ifu_mem_ctl.scala 269:67] - node fetch_req_iccm_f = and(ifc_fetch_req_f, ifc_iccm_access_f) @[el2_ifu_mem_ctl.scala 270:46] - node _T_210 = eq(miss_pending, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 271:45] - node _T_211 = eq(miss_state, UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 271:73] - node _T_212 = or(_T_210, _T_211) @[el2_ifu_mem_ctl.scala 271:59] - node _T_213 = eq(miss_state, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 271:105] - node _T_214 = or(_T_212, _T_213) @[el2_ifu_mem_ctl.scala 271:91] - node ic_iccm_hit_f = and(fetch_req_iccm_f, _T_214) @[el2_ifu_mem_ctl.scala 271:41] + node _T_207 = eq(ifc_iccm_access_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 270:48] + node _T_208 = and(ifc_fetch_req_f, _T_207) @[el2_ifu_mem_ctl.scala 270:46] + node _T_209 = eq(ifc_region_acc_fault_final_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 270:69] + node fetch_req_icache_f = and(_T_208, _T_209) @[el2_ifu_mem_ctl.scala 270:67] + node fetch_req_iccm_f = and(ifc_fetch_req_f, ifc_iccm_access_f) @[el2_ifu_mem_ctl.scala 271:46] + node _T_210 = eq(miss_pending, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 272:45] + node _T_211 = eq(miss_state, UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 272:73] + node _T_212 = or(_T_210, _T_211) @[el2_ifu_mem_ctl.scala 272:59] + node _T_213 = eq(miss_state, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 272:105] + node _T_214 = or(_T_212, _T_213) @[el2_ifu_mem_ctl.scala 272:91] + node ic_iccm_hit_f = and(fetch_req_iccm_f, _T_214) @[el2_ifu_mem_ctl.scala 272:41] wire stream_hit_f : UInt<1> stream_hit_f <= UInt<1>("h00") - node _T_215 = or(crit_byp_hit_f, stream_hit_f) @[el2_ifu_mem_ctl.scala 273:35] - node _T_216 = and(_T_215, fetch_req_icache_f) @[el2_ifu_mem_ctl.scala 273:52] - node _T_217 = and(_T_216, miss_pending) @[el2_ifu_mem_ctl.scala 273:73] - ic_byp_hit_f <= _T_217 @[el2_ifu_mem_ctl.scala 273:16] + node _T_215 = or(crit_byp_hit_f, stream_hit_f) @[el2_ifu_mem_ctl.scala 274:35] + node _T_216 = and(_T_215, fetch_req_icache_f) @[el2_ifu_mem_ctl.scala 274:52] + node _T_217 = and(_T_216, miss_pending) @[el2_ifu_mem_ctl.scala 274:73] + ic_byp_hit_f <= _T_217 @[el2_ifu_mem_ctl.scala 274:16] wire sel_mb_addr_ff : UInt<1> sel_mb_addr_ff <= UInt<1>("h00") wire imb_ff : UInt<31> imb_ff <= UInt<1>("h00") wire ifu_fetch_addr_int_f : UInt<31> ifu_fetch_addr_int_f <= UInt<1>("h00") - node _T_218 = orr(io.ic_rd_hit) @[el2_ifu_mem_ctl.scala 277:35] - node _T_219 = and(_T_218, fetch_req_icache_f) @[el2_ifu_mem_ctl.scala 277:39] - node _T_220 = eq(reset_all_tags, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 277:62] - node _T_221 = and(_T_219, _T_220) @[el2_ifu_mem_ctl.scala 277:60] - node _T_222 = eq(miss_pending, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 277:81] - node _T_223 = eq(miss_state, UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 277:108] - node _T_224 = or(_T_222, _T_223) @[el2_ifu_mem_ctl.scala 277:95] - node _T_225 = and(_T_221, _T_224) @[el2_ifu_mem_ctl.scala 277:78] - node _T_226 = eq(sel_mb_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 277:128] - node ic_act_hit_f = and(_T_225, _T_226) @[el2_ifu_mem_ctl.scala 277:126] - node _T_227 = orr(io.ic_rd_hit) @[el2_ifu_mem_ctl.scala 278:37] - node _T_228 = eq(_T_227, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 278:23] - node _T_229 = or(_T_228, reset_all_tags) @[el2_ifu_mem_ctl.scala 278:41] - node _T_230 = and(_T_229, fetch_req_icache_f) @[el2_ifu_mem_ctl.scala 278:59] - node _T_231 = eq(miss_pending, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 278:82] - node _T_232 = and(_T_230, _T_231) @[el2_ifu_mem_ctl.scala 278:80] - node _T_233 = or(_T_232, scnd_miss_req) @[el2_ifu_mem_ctl.scala 278:97] - node _T_234 = eq(ifc_region_acc_fault_final_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 278:116] - node _T_235 = and(_T_233, _T_234) @[el2_ifu_mem_ctl.scala 278:114] - ic_act_miss_f <= _T_235 @[el2_ifu_mem_ctl.scala 278:17] - node _T_236 = eq(io.ic_rd_hit, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 279:28] - node _T_237 = or(_T_236, reset_all_tags) @[el2_ifu_mem_ctl.scala 279:42] - node _T_238 = and(_T_237, fetch_req_icache_f) @[el2_ifu_mem_ctl.scala 279:60] - node _T_239 = eq(miss_state, UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 279:94] - node _T_240 = and(_T_238, _T_239) @[el2_ifu_mem_ctl.scala 279:81] - node _T_241 = bits(imb_ff, 30, 5) @[el2_ifu_mem_ctl.scala 280:12] - node _T_242 = bits(ifu_fetch_addr_int_f, 30, 5) @[el2_ifu_mem_ctl.scala 280:63] - node _T_243 = neq(_T_241, _T_242) @[el2_ifu_mem_ctl.scala 280:39] - node _T_244 = and(_T_240, _T_243) @[el2_ifu_mem_ctl.scala 279:111] - node _T_245 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 280:93] - node _T_246 = and(_T_244, _T_245) @[el2_ifu_mem_ctl.scala 280:91] - node _T_247 = eq(sel_mb_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 280:116] - node _T_248 = and(_T_246, _T_247) @[el2_ifu_mem_ctl.scala 280:114] - node _T_249 = eq(ifc_region_acc_fault_final_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 280:134] - node _T_250 = and(_T_248, _T_249) @[el2_ifu_mem_ctl.scala 280:132] - ic_miss_under_miss_f <= _T_250 @[el2_ifu_mem_ctl.scala 279:24] - node _T_251 = orr(io.ic_rd_hit) @[el2_ifu_mem_ctl.scala 281:42] - node _T_252 = eq(_T_251, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 281:28] - node _T_253 = or(_T_252, reset_all_tags) @[el2_ifu_mem_ctl.scala 281:46] - node _T_254 = and(_T_253, fetch_req_icache_f) @[el2_ifu_mem_ctl.scala 281:64] - node _T_255 = eq(miss_state, UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 281:99] - node _T_256 = and(_T_254, _T_255) @[el2_ifu_mem_ctl.scala 281:85] - node _T_257 = bits(imb_ff, 30, 5) @[el2_ifu_mem_ctl.scala 282:13] - node _T_258 = bits(ifu_fetch_addr_int_f, 30, 5) @[el2_ifu_mem_ctl.scala 282:62] - node _T_259 = eq(_T_257, _T_258) @[el2_ifu_mem_ctl.scala 282:39] - node _T_260 = or(_T_259, uncacheable_miss_ff) @[el2_ifu_mem_ctl.scala 282:91] - node _T_261 = and(_T_256, _T_260) @[el2_ifu_mem_ctl.scala 281:117] - ic_ignore_2nd_miss_f <= _T_261 @[el2_ifu_mem_ctl.scala 281:24] - node _T_262 = or(ic_act_hit_f, ic_byp_hit_f) @[el2_ifu_mem_ctl.scala 284:31] - node _T_263 = or(_T_262, ic_iccm_hit_f) @[el2_ifu_mem_ctl.scala 284:46] - node _T_264 = and(ifc_region_acc_fault_final_f, ifc_fetch_req_f) @[el2_ifu_mem_ctl.scala 284:94] - node _T_265 = or(_T_263, _T_264) @[el2_ifu_mem_ctl.scala 284:62] - io.ic_hit_f <= _T_265 @[el2_ifu_mem_ctl.scala 284:15] - node _T_266 = bits(scnd_miss_req, 0, 0) @[el2_ifu_mem_ctl.scala 285:47] - node _T_267 = bits(sel_hold_imb, 0, 0) @[el2_ifu_mem_ctl.scala 285:98] - node _T_268 = mux(_T_267, uncacheable_miss_ff, io.ifc_fetch_uncacheable_bf) @[el2_ifu_mem_ctl.scala 285:84] - node uncacheable_miss_in = mux(_T_266, uncacheable_miss_scnd_ff, _T_268) @[el2_ifu_mem_ctl.scala 285:32] - node _T_269 = bits(scnd_miss_req, 0, 0) @[el2_ifu_mem_ctl.scala 286:34] - node _T_270 = bits(sel_hold_imb, 0, 0) @[el2_ifu_mem_ctl.scala 286:72] - node _T_271 = mux(_T_270, imb_ff, io.ifc_fetch_addr_bf) @[el2_ifu_mem_ctl.scala 286:58] - node imb_in = mux(_T_269, imb_scnd_ff, _T_271) @[el2_ifu_mem_ctl.scala 286:19] + node _T_218 = orr(io.ic_rd_hit) @[el2_ifu_mem_ctl.scala 278:35] + node _T_219 = and(_T_218, fetch_req_icache_f) @[el2_ifu_mem_ctl.scala 278:39] + node _T_220 = eq(reset_all_tags, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 278:62] + node _T_221 = and(_T_219, _T_220) @[el2_ifu_mem_ctl.scala 278:60] + node _T_222 = eq(miss_pending, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 278:81] + node _T_223 = eq(miss_state, UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 278:108] + node _T_224 = or(_T_222, _T_223) @[el2_ifu_mem_ctl.scala 278:95] + node _T_225 = and(_T_221, _T_224) @[el2_ifu_mem_ctl.scala 278:78] + node _T_226 = eq(sel_mb_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 278:128] + node ic_act_hit_f = and(_T_225, _T_226) @[el2_ifu_mem_ctl.scala 278:126] + node _T_227 = orr(io.ic_rd_hit) @[el2_ifu_mem_ctl.scala 279:37] + node _T_228 = eq(_T_227, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 279:23] + node _T_229 = or(_T_228, reset_all_tags) @[el2_ifu_mem_ctl.scala 279:41] + node _T_230 = and(_T_229, fetch_req_icache_f) @[el2_ifu_mem_ctl.scala 279:59] + node _T_231 = eq(miss_pending, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 279:82] + node _T_232 = and(_T_230, _T_231) @[el2_ifu_mem_ctl.scala 279:80] + node _T_233 = or(_T_232, scnd_miss_req) @[el2_ifu_mem_ctl.scala 279:97] + node _T_234 = eq(ifc_region_acc_fault_final_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 279:116] + node _T_235 = and(_T_233, _T_234) @[el2_ifu_mem_ctl.scala 279:114] + ic_act_miss_f <= _T_235 @[el2_ifu_mem_ctl.scala 279:17] + node _T_236 = eq(io.ic_rd_hit, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 280:28] + node _T_237 = or(_T_236, reset_all_tags) @[el2_ifu_mem_ctl.scala 280:42] + node _T_238 = and(_T_237, fetch_req_icache_f) @[el2_ifu_mem_ctl.scala 280:60] + node _T_239 = eq(miss_state, UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 280:94] + node _T_240 = and(_T_238, _T_239) @[el2_ifu_mem_ctl.scala 280:81] + node _T_241 = bits(imb_ff, 30, 5) @[el2_ifu_mem_ctl.scala 281:12] + node _T_242 = bits(ifu_fetch_addr_int_f, 30, 5) @[el2_ifu_mem_ctl.scala 281:63] + node _T_243 = neq(_T_241, _T_242) @[el2_ifu_mem_ctl.scala 281:39] + node _T_244 = and(_T_240, _T_243) @[el2_ifu_mem_ctl.scala 280:111] + node _T_245 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 281:93] + node _T_246 = and(_T_244, _T_245) @[el2_ifu_mem_ctl.scala 281:91] + node _T_247 = eq(sel_mb_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 281:116] + node _T_248 = and(_T_246, _T_247) @[el2_ifu_mem_ctl.scala 281:114] + node _T_249 = eq(ifc_region_acc_fault_final_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 281:134] + node _T_250 = and(_T_248, _T_249) @[el2_ifu_mem_ctl.scala 281:132] + ic_miss_under_miss_f <= _T_250 @[el2_ifu_mem_ctl.scala 280:24] + node _T_251 = orr(io.ic_rd_hit) @[el2_ifu_mem_ctl.scala 282:42] + node _T_252 = eq(_T_251, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 282:28] + node _T_253 = or(_T_252, reset_all_tags) @[el2_ifu_mem_ctl.scala 282:46] + node _T_254 = and(_T_253, fetch_req_icache_f) @[el2_ifu_mem_ctl.scala 282:64] + node _T_255 = eq(miss_state, UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 282:99] + node _T_256 = and(_T_254, _T_255) @[el2_ifu_mem_ctl.scala 282:85] + node _T_257 = bits(imb_ff, 30, 5) @[el2_ifu_mem_ctl.scala 283:13] + node _T_258 = bits(ifu_fetch_addr_int_f, 30, 5) @[el2_ifu_mem_ctl.scala 283:62] + node _T_259 = eq(_T_257, _T_258) @[el2_ifu_mem_ctl.scala 283:39] + node _T_260 = or(_T_259, uncacheable_miss_ff) @[el2_ifu_mem_ctl.scala 283:91] + node _T_261 = and(_T_256, _T_260) @[el2_ifu_mem_ctl.scala 282:117] + ic_ignore_2nd_miss_f <= _T_261 @[el2_ifu_mem_ctl.scala 282:24] + node _T_262 = or(ic_act_hit_f, ic_byp_hit_f) @[el2_ifu_mem_ctl.scala 285:31] + node _T_263 = or(_T_262, ic_iccm_hit_f) @[el2_ifu_mem_ctl.scala 285:46] + node _T_264 = and(ifc_region_acc_fault_final_f, ifc_fetch_req_f) @[el2_ifu_mem_ctl.scala 285:94] + node _T_265 = or(_T_263, _T_264) @[el2_ifu_mem_ctl.scala 285:62] + io.ic_hit_f <= _T_265 @[el2_ifu_mem_ctl.scala 285:15] + node _T_266 = bits(scnd_miss_req, 0, 0) @[el2_ifu_mem_ctl.scala 286:47] + node _T_267 = bits(sel_hold_imb, 0, 0) @[el2_ifu_mem_ctl.scala 286:98] + node _T_268 = mux(_T_267, uncacheable_miss_ff, io.ifc_fetch_uncacheable_bf) @[el2_ifu_mem_ctl.scala 286:84] + node uncacheable_miss_in = mux(_T_266, uncacheable_miss_scnd_ff, _T_268) @[el2_ifu_mem_ctl.scala 286:32] + node _T_269 = bits(scnd_miss_req, 0, 0) @[el2_ifu_mem_ctl.scala 287:34] + node _T_270 = bits(sel_hold_imb, 0, 0) @[el2_ifu_mem_ctl.scala 287:72] + node _T_271 = mux(_T_270, imb_ff, io.ifc_fetch_addr_bf) @[el2_ifu_mem_ctl.scala 287:58] + node imb_in = mux(_T_269, imb_scnd_ff, _T_271) @[el2_ifu_mem_ctl.scala 287:19] wire ifu_wr_cumulative_err_data : UInt<1> ifu_wr_cumulative_err_data <= UInt<1>("h00") - node _T_272 = bits(imb_ff, 12, 6) @[el2_ifu_mem_ctl.scala 288:38] - node _T_273 = bits(imb_scnd_ff, 12, 6) @[el2_ifu_mem_ctl.scala 288:89] - node _T_274 = eq(_T_272, _T_273) @[el2_ifu_mem_ctl.scala 288:75] - node _T_275 = and(_T_274, scnd_miss_req) @[el2_ifu_mem_ctl.scala 288:127] - node _T_276 = eq(ifu_wr_cumulative_err_data, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 288:145] - node scnd_miss_index_match = and(_T_275, _T_276) @[el2_ifu_mem_ctl.scala 288:143] + node _T_272 = bits(imb_ff, 12, 6) @[el2_ifu_mem_ctl.scala 289:38] + node _T_273 = bits(imb_scnd_ff, 12, 6) @[el2_ifu_mem_ctl.scala 289:89] + node _T_274 = eq(_T_272, _T_273) @[el2_ifu_mem_ctl.scala 289:75] + node _T_275 = and(_T_274, scnd_miss_req) @[el2_ifu_mem_ctl.scala 289:127] + node _T_276 = eq(ifu_wr_cumulative_err_data, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 289:145] + node scnd_miss_index_match = and(_T_275, _T_276) @[el2_ifu_mem_ctl.scala 289:143] wire way_status_mb_ff : UInt<1> way_status_mb_ff <= UInt<1>("h00") wire way_status_rep_new : UInt<1> way_status_rep_new <= UInt<1>("h00") - node _T_277 = eq(scnd_miss_index_match, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 291:47] - node _T_278 = and(scnd_miss_req, _T_277) @[el2_ifu_mem_ctl.scala 291:45] - node _T_279 = bits(_T_278, 0, 0) @[el2_ifu_mem_ctl.scala 291:71] - node _T_280 = and(scnd_miss_req, scnd_miss_index_match) @[el2_ifu_mem_ctl.scala 292:26] - node _T_281 = bits(_T_280, 0, 0) @[el2_ifu_mem_ctl.scala 292:52] - node _T_282 = bits(miss_pending, 0, 0) @[el2_ifu_mem_ctl.scala 293:26] - node _T_283 = mux(_T_282, way_status_mb_ff, way_status) @[el2_ifu_mem_ctl.scala 293:12] - node _T_284 = mux(_T_281, way_status_rep_new, _T_283) @[el2_ifu_mem_ctl.scala 292:10] - node way_status_mb_in = mux(_T_279, way_status_mb_scnd_ff, _T_284) @[el2_ifu_mem_ctl.scala 291:29] - wire replace_way_mb_any : UInt<1>[2] @[el2_ifu_mem_ctl.scala 294:32] + node _T_277 = eq(scnd_miss_index_match, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 292:47] + node _T_278 = and(scnd_miss_req, _T_277) @[el2_ifu_mem_ctl.scala 292:45] + node _T_279 = bits(_T_278, 0, 0) @[el2_ifu_mem_ctl.scala 292:71] + node _T_280 = and(scnd_miss_req, scnd_miss_index_match) @[el2_ifu_mem_ctl.scala 293:26] + node _T_281 = bits(_T_280, 0, 0) @[el2_ifu_mem_ctl.scala 293:52] + node _T_282 = bits(miss_pending, 0, 0) @[el2_ifu_mem_ctl.scala 294:26] + node _T_283 = mux(_T_282, way_status_mb_ff, way_status) @[el2_ifu_mem_ctl.scala 294:12] + node _T_284 = mux(_T_281, way_status_rep_new, _T_283) @[el2_ifu_mem_ctl.scala 293:10] + node way_status_mb_in = mux(_T_279, way_status_mb_scnd_ff, _T_284) @[el2_ifu_mem_ctl.scala 292:29] + wire replace_way_mb_any : UInt<1>[2] @[el2_ifu_mem_ctl.scala 295:32] wire tagv_mb_ff : UInt<2> tagv_mb_ff <= UInt<1>("h00") - node _T_285 = bits(scnd_miss_req, 0, 0) @[el2_ifu_mem_ctl.scala 296:38] + node _T_285 = bits(scnd_miss_req, 0, 0) @[el2_ifu_mem_ctl.scala 297:38] node _T_286 = bits(scnd_miss_index_match, 0, 0) @[Bitwise.scala 72:15] node _T_287 = mux(_T_286, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] node _T_288 = cat(replace_way_mb_any[1], replace_way_mb_any[0]) @[Cat.scala 29:58] - node _T_289 = and(_T_287, _T_288) @[el2_ifu_mem_ctl.scala 296:110] - node _T_290 = or(tagv_mb_scnd_ff, _T_289) @[el2_ifu_mem_ctl.scala 296:62] - node _T_291 = bits(miss_pending, 0, 0) @[el2_ifu_mem_ctl.scala 297:20] - node _T_292 = eq(reset_all_tags, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 297:77] + node _T_289 = and(_T_287, _T_288) @[el2_ifu_mem_ctl.scala 297:110] + node _T_290 = or(tagv_mb_scnd_ff, _T_289) @[el2_ifu_mem_ctl.scala 297:62] + node _T_291 = bits(miss_pending, 0, 0) @[el2_ifu_mem_ctl.scala 298:20] + node _T_292 = eq(reset_all_tags, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 298:77] node _T_293 = bits(_T_292, 0, 0) @[Bitwise.scala 72:15] node _T_294 = mux(_T_293, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_295 = and(ic_tag_valid, _T_294) @[el2_ifu_mem_ctl.scala 297:53] - node _T_296 = mux(_T_291, tagv_mb_ff, _T_295) @[el2_ifu_mem_ctl.scala 297:6] - node tagv_mb_in = mux(_T_285, _T_290, _T_296) @[el2_ifu_mem_ctl.scala 296:23] + node _T_295 = and(ic_tag_valid, _T_294) @[el2_ifu_mem_ctl.scala 298:53] + node _T_296 = mux(_T_291, tagv_mb_ff, _T_295) @[el2_ifu_mem_ctl.scala 298:6] + node tagv_mb_in = mux(_T_285, _T_290, _T_296) @[el2_ifu_mem_ctl.scala 297:23] wire scnd_miss_req_q : UInt<1> scnd_miss_req_q <= UInt<1>("h00") wire reset_ic_ff : UInt<1> reset_ic_ff <= UInt<1>("h00") - node _T_297 = eq(scnd_miss_req_q, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 300:36] - node _T_298 = and(miss_pending, _T_297) @[el2_ifu_mem_ctl.scala 300:34] - node _T_299 = or(reset_all_tags, reset_ic_ff) @[el2_ifu_mem_ctl.scala 300:72] - node reset_ic_in = and(_T_298, _T_299) @[el2_ifu_mem_ctl.scala 300:53] - reg _T_300 : UInt, clock @[el2_ifu_mem_ctl.scala 301:25] - _T_300 <= reset_ic_in @[el2_ifu_mem_ctl.scala 301:25] - reset_ic_ff <= _T_300 @[el2_ifu_mem_ctl.scala 301:15] - reg fetch_uncacheable_ff : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 302:37] - fetch_uncacheable_ff <= io.ifc_fetch_uncacheable_bf @[el2_ifu_mem_ctl.scala 302:37] - reg _T_301 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 303:34] - _T_301 <= io.ifc_fetch_addr_bf @[el2_ifu_mem_ctl.scala 303:34] - ifu_fetch_addr_int_f <= _T_301 @[el2_ifu_mem_ctl.scala 303:24] - reg _T_302 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 305:33] - _T_302 <= uncacheable_miss_in @[el2_ifu_mem_ctl.scala 305:33] - uncacheable_miss_ff <= _T_302 @[el2_ifu_mem_ctl.scala 305:23] - reg _T_303 : UInt, clock @[el2_ifu_mem_ctl.scala 306:20] - _T_303 <= imb_in @[el2_ifu_mem_ctl.scala 306:20] - imb_ff <= _T_303 @[el2_ifu_mem_ctl.scala 306:10] + node _T_297 = eq(scnd_miss_req_q, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 301:36] + node _T_298 = and(miss_pending, _T_297) @[el2_ifu_mem_ctl.scala 301:34] + node _T_299 = or(reset_all_tags, reset_ic_ff) @[el2_ifu_mem_ctl.scala 301:72] + node reset_ic_in = and(_T_298, _T_299) @[el2_ifu_mem_ctl.scala 301:53] + reg _T_300 : UInt, clock @[el2_ifu_mem_ctl.scala 302:25] + _T_300 <= reset_ic_in @[el2_ifu_mem_ctl.scala 302:25] + reset_ic_ff <= _T_300 @[el2_ifu_mem_ctl.scala 302:15] + reg fetch_uncacheable_ff : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 303:37] + fetch_uncacheable_ff <= io.ifc_fetch_uncacheable_bf @[el2_ifu_mem_ctl.scala 303:37] + reg _T_301 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 304:34] + _T_301 <= io.ifc_fetch_addr_bf @[el2_ifu_mem_ctl.scala 304:34] + ifu_fetch_addr_int_f <= _T_301 @[el2_ifu_mem_ctl.scala 304:24] + reg _T_302 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 306:33] + _T_302 <= uncacheable_miss_in @[el2_ifu_mem_ctl.scala 306:33] + uncacheable_miss_ff <= _T_302 @[el2_ifu_mem_ctl.scala 306:23] + reg _T_303 : UInt, clock @[el2_ifu_mem_ctl.scala 307:20] + _T_303 <= imb_in @[el2_ifu_mem_ctl.scala 307:20] + imb_ff <= _T_303 @[el2_ifu_mem_ctl.scala 307:10] wire miss_addr : UInt<26> miss_addr <= UInt<1>("h00") - node _T_304 = eq(miss_pending, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 308:26] - node _T_305 = bits(imb_ff, 30, 5) @[el2_ifu_mem_ctl.scala 308:47] - node _T_306 = bits(scnd_miss_req_q, 0, 0) @[el2_ifu_mem_ctl.scala 309:25] - node _T_307 = bits(imb_scnd_ff, 30, 5) @[el2_ifu_mem_ctl.scala 309:44] - node _T_308 = mux(_T_306, _T_307, miss_addr) @[el2_ifu_mem_ctl.scala 309:8] - node miss_addr_in = mux(_T_304, _T_305, _T_308) @[el2_ifu_mem_ctl.scala 308:25] - reg _T_309 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 310:23] - _T_309 <= miss_addr_in @[el2_ifu_mem_ctl.scala 310:23] - miss_addr <= _T_309 @[el2_ifu_mem_ctl.scala 310:13] - reg _T_310 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 311:30] - _T_310 <= way_status_mb_in @[el2_ifu_mem_ctl.scala 311:30] - way_status_mb_ff <= _T_310 @[el2_ifu_mem_ctl.scala 311:20] - reg _T_311 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 312:24] - _T_311 <= tagv_mb_in @[el2_ifu_mem_ctl.scala 312:24] - tagv_mb_ff <= _T_311 @[el2_ifu_mem_ctl.scala 312:14] + node _T_304 = eq(miss_pending, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 309:26] + node _T_305 = bits(imb_ff, 30, 5) @[el2_ifu_mem_ctl.scala 309:47] + node _T_306 = bits(scnd_miss_req_q, 0, 0) @[el2_ifu_mem_ctl.scala 310:25] + node _T_307 = bits(imb_scnd_ff, 30, 5) @[el2_ifu_mem_ctl.scala 310:44] + node _T_308 = mux(_T_306, _T_307, miss_addr) @[el2_ifu_mem_ctl.scala 310:8] + node miss_addr_in = mux(_T_304, _T_305, _T_308) @[el2_ifu_mem_ctl.scala 309:25] + reg _T_309 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 311:23] + _T_309 <= miss_addr_in @[el2_ifu_mem_ctl.scala 311:23] + miss_addr <= _T_309 @[el2_ifu_mem_ctl.scala 311:13] + reg _T_310 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 312:30] + _T_310 <= way_status_mb_in @[el2_ifu_mem_ctl.scala 312:30] + way_status_mb_ff <= _T_310 @[el2_ifu_mem_ctl.scala 312:20] + reg _T_311 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 313:24] + _T_311 <= tagv_mb_in @[el2_ifu_mem_ctl.scala 313:24] + tagv_mb_ff <= _T_311 @[el2_ifu_mem_ctl.scala 313:14] wire stream_miss_f : UInt<1> stream_miss_f <= UInt<1>("h00") - node _T_312 = eq(miss_state, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 314:68] - node _T_313 = and(_T_312, flush_final_f) @[el2_ifu_mem_ctl.scala 314:87] - node _T_314 = eq(_T_313, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 314:55] - node _T_315 = and(io.ifc_fetch_req_bf, _T_314) @[el2_ifu_mem_ctl.scala 314:53] - node _T_316 = eq(stream_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 314:106] - node ifc_fetch_req_qual_bf = and(_T_315, _T_316) @[el2_ifu_mem_ctl.scala 314:104] - reg ifc_fetch_req_f_raw : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 315:36] - ifc_fetch_req_f_raw <= ifc_fetch_req_qual_bf @[el2_ifu_mem_ctl.scala 315:36] - node _T_317 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 316:44] - node _T_318 = and(ifc_fetch_req_f_raw, _T_317) @[el2_ifu_mem_ctl.scala 316:42] - ifc_fetch_req_f <= _T_318 @[el2_ifu_mem_ctl.scala 316:19] - reg _T_319 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 317:31] - _T_319 <= io.ifc_iccm_access_bf @[el2_ifu_mem_ctl.scala 317:31] - ifc_iccm_access_f <= _T_319 @[el2_ifu_mem_ctl.scala 317:21] + node _T_312 = eq(miss_state, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 315:68] + node _T_313 = and(_T_312, flush_final_f) @[el2_ifu_mem_ctl.scala 315:87] + node _T_314 = eq(_T_313, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 315:55] + node _T_315 = and(io.ifc_fetch_req_bf, _T_314) @[el2_ifu_mem_ctl.scala 315:53] + node _T_316 = eq(stream_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 315:106] + node ifc_fetch_req_qual_bf = and(_T_315, _T_316) @[el2_ifu_mem_ctl.scala 315:104] + reg ifc_fetch_req_f_raw : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 316:36] + ifc_fetch_req_f_raw <= ifc_fetch_req_qual_bf @[el2_ifu_mem_ctl.scala 316:36] + node _T_317 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 317:44] + node _T_318 = and(ifc_fetch_req_f_raw, _T_317) @[el2_ifu_mem_ctl.scala 317:42] + ifc_fetch_req_f <= _T_318 @[el2_ifu_mem_ctl.scala 317:19] + reg _T_319 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 318:31] + _T_319 <= io.ifc_iccm_access_bf @[el2_ifu_mem_ctl.scala 318:31] + ifc_iccm_access_f <= _T_319 @[el2_ifu_mem_ctl.scala 318:21] wire ifc_region_acc_fault_final_bf : UInt<1> ifc_region_acc_fault_final_bf <= UInt<1>("h00") - reg _T_320 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 319:42] - _T_320 <= ifc_region_acc_fault_final_bf @[el2_ifu_mem_ctl.scala 319:42] - ifc_region_acc_fault_final_f <= _T_320 @[el2_ifu_mem_ctl.scala 319:32] - reg ifc_region_acc_fault_f : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 320:39] - ifc_region_acc_fault_f <= io.ifc_region_acc_fault_bf @[el2_ifu_mem_ctl.scala 320:39] + reg _T_320 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 320:42] + _T_320 <= ifc_region_acc_fault_final_bf @[el2_ifu_mem_ctl.scala 320:42] + ifc_region_acc_fault_final_f <= _T_320 @[el2_ifu_mem_ctl.scala 320:32] + reg ifc_region_acc_fault_f : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 321:39] + ifc_region_acc_fault_f <= io.ifc_region_acc_fault_bf @[el2_ifu_mem_ctl.scala 321:39] node ifu_ic_req_addr_f = cat(miss_addr, bus_rd_addr_count) @[Cat.scala 29:58] - node _T_321 = eq(miss_state, UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 322:38] - node _T_322 = eq(miss_state, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 322:68] - node _T_323 = or(_T_321, _T_322) @[el2_ifu_mem_ctl.scala 322:55] - node _T_324 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 322:103] - node _T_325 = eq(_T_324, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 322:84] - node _T_326 = and(_T_323, _T_325) @[el2_ifu_mem_ctl.scala 322:82] - node _T_327 = eq(miss_pending, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 322:119] - node _T_328 = or(_T_326, _T_327) @[el2_ifu_mem_ctl.scala 322:117] - io.ifu_ic_mb_empty <= _T_328 @[el2_ifu_mem_ctl.scala 322:22] - node _T_329 = eq(miss_state, UInt<3>("h00")) @[el2_ifu_mem_ctl.scala 323:40] - io.ifu_miss_state_idle <= _T_329 @[el2_ifu_mem_ctl.scala 323:26] + node _T_321 = eq(miss_state, UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 323:38] + node _T_322 = eq(miss_state, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 323:68] + node _T_323 = or(_T_321, _T_322) @[el2_ifu_mem_ctl.scala 323:55] + node _T_324 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 323:103] + node _T_325 = eq(_T_324, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 323:84] + node _T_326 = and(_T_323, _T_325) @[el2_ifu_mem_ctl.scala 323:82] + node _T_327 = eq(miss_pending, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 323:119] + node _T_328 = or(_T_326, _T_327) @[el2_ifu_mem_ctl.scala 323:117] + io.ifu_ic_mb_empty <= _T_328 @[el2_ifu_mem_ctl.scala 323:22] + node _T_329 = eq(miss_state, UInt<3>("h00")) @[el2_ifu_mem_ctl.scala 324:40] + io.ifu_miss_state_idle <= _T_329 @[el2_ifu_mem_ctl.scala 324:26] wire write_ic_16_bytes : UInt<1> write_ic_16_bytes <= UInt<1>("h00") wire reset_tag_valid_for_miss : UInt<1> reset_tag_valid_for_miss <= UInt<1>("h00") - node _T_330 = and(miss_pending, write_ic_16_bytes) @[el2_ifu_mem_ctl.scala 326:35] - node _T_331 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 326:57] - node _T_332 = and(_T_330, _T_331) @[el2_ifu_mem_ctl.scala 326:55] - node sel_mb_addr = or(_T_332, reset_tag_valid_for_miss) @[el2_ifu_mem_ctl.scala 326:79] - node _T_333 = bits(sel_mb_addr, 0, 0) @[el2_ifu_mem_ctl.scala 327:50] - node _T_334 = bits(imb_ff, 30, 5) @[el2_ifu_mem_ctl.scala 327:68] - node _T_335 = bits(imb_ff, 1, 0) @[el2_ifu_mem_ctl.scala 327:124] + node _T_330 = and(miss_pending, write_ic_16_bytes) @[el2_ifu_mem_ctl.scala 327:35] + node _T_331 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 327:57] + node _T_332 = and(_T_330, _T_331) @[el2_ifu_mem_ctl.scala 327:55] + node sel_mb_addr = or(_T_332, reset_tag_valid_for_miss) @[el2_ifu_mem_ctl.scala 327:79] + node _T_333 = bits(sel_mb_addr, 0, 0) @[el2_ifu_mem_ctl.scala 328:50] + node _T_334 = bits(imb_ff, 30, 5) @[el2_ifu_mem_ctl.scala 328:68] + node _T_335 = bits(imb_ff, 1, 0) @[el2_ifu_mem_ctl.scala 328:124] node _T_336 = cat(_T_334, ic_wr_addr_bits_hi_3) @[Cat.scala 29:58] node _T_337 = cat(_T_336, _T_335) @[Cat.scala 29:58] - node _T_338 = bits(sel_mb_addr, 0, 0) @[el2_ifu_mem_ctl.scala 328:50] - node _T_339 = eq(_T_338, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 328:37] + node _T_338 = bits(sel_mb_addr, 0, 0) @[el2_ifu_mem_ctl.scala 329:50] + node _T_339 = eq(_T_338, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 329:37] node _T_340 = mux(_T_333, _T_337, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_341 = mux(_T_339, ifu_fetch_addr_int_f, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_341 = mux(_T_339, io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Mux.scala 27:72] node _T_342 = or(_T_340, _T_341) @[Mux.scala 27:72] wire ifu_ic_rw_int_addr : UInt<31> @[Mux.scala 27:72] ifu_ic_rw_int_addr <= _T_342 @[Mux.scala 27:72] wire bus_ifu_wr_en_ff_q : UInt<1> bus_ifu_wr_en_ff_q <= UInt<1>("h00") - node _T_343 = and(miss_pending, write_ic_16_bytes) @[el2_ifu_mem_ctl.scala 330:41] - node _T_344 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 330:63] - node _T_345 = and(_T_343, _T_344) @[el2_ifu_mem_ctl.scala 330:61] - node _T_346 = and(_T_345, last_beat) @[el2_ifu_mem_ctl.scala 330:84] - node sel_mb_status_addr = and(_T_346, bus_ifu_wr_en_ff_q) @[el2_ifu_mem_ctl.scala 330:96] - node _T_347 = bits(imb_ff, 30, 5) @[el2_ifu_mem_ctl.scala 331:62] - node _T_348 = bits(imb_ff, 1, 0) @[el2_ifu_mem_ctl.scala 331:116] + node _T_343 = and(miss_pending, write_ic_16_bytes) @[el2_ifu_mem_ctl.scala 331:41] + node _T_344 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 331:63] + node _T_345 = and(_T_343, _T_344) @[el2_ifu_mem_ctl.scala 331:61] + node _T_346 = and(_T_345, last_beat) @[el2_ifu_mem_ctl.scala 331:84] + node sel_mb_status_addr = and(_T_346, bus_ifu_wr_en_ff_q) @[el2_ifu_mem_ctl.scala 331:96] + node _T_347 = bits(imb_ff, 30, 5) @[el2_ifu_mem_ctl.scala 332:62] + node _T_348 = bits(imb_ff, 1, 0) @[el2_ifu_mem_ctl.scala 332:116] node _T_349 = cat(_T_347, ic_wr_addr_bits_hi_3) @[Cat.scala 29:58] node _T_350 = cat(_T_349, _T_348) @[Cat.scala 29:58] - node ifu_status_wr_addr = mux(sel_mb_status_addr, _T_350, ifu_fetch_addr_int_f) @[el2_ifu_mem_ctl.scala 331:31] - io.ic_rw_addr <= ifu_ic_rw_int_addr @[el2_ifu_mem_ctl.scala 332:17] - reg _T_351 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 333:51] - _T_351 <= sel_mb_addr @[el2_ifu_mem_ctl.scala 333:51] - sel_mb_addr_ff <= _T_351 @[el2_ifu_mem_ctl.scala 333:18] + node ifu_status_wr_addr = mux(sel_mb_status_addr, _T_350, ifu_fetch_addr_int_f) @[el2_ifu_mem_ctl.scala 332:31] + io.ic_rw_addr <= ifu_ic_rw_int_addr @[el2_ifu_mem_ctl.scala 333:17] + reg _T_351 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 334:51] + _T_351 <= sel_mb_addr @[el2_ifu_mem_ctl.scala 334:51] + sel_mb_addr_ff <= _T_351 @[el2_ifu_mem_ctl.scala 334:18] wire ifu_bus_rdata_ff : UInt<64> ifu_bus_rdata_ff <= UInt<1>("h00") wire ic_miss_buff_half : UInt<64> @@ -1868,24 +1868,24 @@ circuit el2_ifu_mem_ctl : node ic_miss_buff_ecc = cat(_T_1195, _T_1192) @[Cat.scala 29:58] wire ic_wr_16bytes_data : UInt<142> ic_wr_16bytes_data <= UInt<1>("h00") - node _T_1196 = bits(ic_wr_16bytes_data, 70, 0) @[el2_ifu_mem_ctl.scala 339:72] - node _T_1197 = bits(ic_wr_16bytes_data, 141, 71) @[el2_ifu_mem_ctl.scala 339:72] - io.ic_wr_data[0] <= _T_1196 @[el2_ifu_mem_ctl.scala 339:17] - io.ic_wr_data[1] <= _T_1197 @[el2_ifu_mem_ctl.scala 339:17] - io.ic_debug_wr_data <= io.dec_tlu_ic_diag_pkt.icache_wrdata @[el2_ifu_mem_ctl.scala 340:23] + node _T_1196 = bits(ic_wr_16bytes_data, 70, 0) @[el2_ifu_mem_ctl.scala 340:72] + node _T_1197 = bits(ic_wr_16bytes_data, 141, 71) @[el2_ifu_mem_ctl.scala 340:72] + io.ic_wr_data[0] <= _T_1196 @[el2_ifu_mem_ctl.scala 340:17] + io.ic_wr_data[1] <= _T_1197 @[el2_ifu_mem_ctl.scala 340:17] + io.ic_debug_wr_data <= io.dec_tlu_ic_diag_pkt.icache_wrdata @[el2_ifu_mem_ctl.scala 341:23] wire ic_rd_parity_final_err : UInt<1> ic_rd_parity_final_err <= UInt<1>("h00") - node _T_1198 = orr(io.ic_eccerr) @[el2_ifu_mem_ctl.scala 342:56] - node _T_1199 = and(_T_1198, ic_act_hit_f) @[el2_ifu_mem_ctl.scala 342:83] - node _T_1200 = or(_T_1199, ic_rd_parity_final_err) @[el2_ifu_mem_ctl.scala 342:99] - io.ic_error_start <= _T_1200 @[el2_ifu_mem_ctl.scala 342:21] + node _T_1198 = orr(io.ic_eccerr) @[el2_ifu_mem_ctl.scala 343:56] + node _T_1199 = and(_T_1198, ic_act_hit_f) @[el2_ifu_mem_ctl.scala 343:83] + node _T_1200 = or(_T_1199, ic_rd_parity_final_err) @[el2_ifu_mem_ctl.scala 343:99] + io.ic_error_start <= _T_1200 @[el2_ifu_mem_ctl.scala 343:21] wire ic_debug_tag_val_rd_out : UInt<1> ic_debug_tag_val_rd_out <= UInt<1>("h00") wire ic_debug_ict_array_sel_ff : UInt<1> ic_debug_ict_array_sel_ff <= UInt<1>("h00") - node _T_1201 = bits(ic_debug_ict_array_sel_ff, 0, 0) @[el2_ifu_mem_ctl.scala 345:63] - node _T_1202 = bits(io.ictag_debug_rd_data, 25, 21) @[el2_ifu_mem_ctl.scala 345:121] - node _T_1203 = bits(io.ictag_debug_rd_data, 20, 0) @[el2_ifu_mem_ctl.scala 345:161] + node _T_1201 = bits(ic_debug_ict_array_sel_ff, 0, 0) @[el2_ifu_mem_ctl.scala 346:63] + node _T_1202 = bits(io.ictag_debug_rd_data, 25, 21) @[el2_ifu_mem_ctl.scala 346:121] + node _T_1203 = bits(io.ictag_debug_rd_data, 20, 0) @[el2_ifu_mem_ctl.scala 346:161] node _T_1204 = cat(UInt<3>("h00"), ic_debug_tag_val_rd_out) @[Cat.scala 29:58] node _T_1205 = cat(UInt<1>("h00"), way_status) @[Cat.scala 29:58] node _T_1206 = cat(_T_1205, _T_1204) @[Cat.scala 29:58] @@ -1893,273 +1893,273 @@ circuit el2_ifu_mem_ctl : node _T_1208 = cat(UInt<2>("h00"), _T_1202) @[Cat.scala 29:58] node _T_1209 = cat(_T_1208, _T_1207) @[Cat.scala 29:58] node _T_1210 = cat(_T_1209, _T_1206) @[Cat.scala 29:58] - node ifu_ic_debug_rd_data_in = mux(_T_1201, _T_1210, io.ic_debug_rd_data) @[el2_ifu_mem_ctl.scala 345:36] - reg _T_1211 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 348:37] - _T_1211 <= ifu_ic_debug_rd_data_in @[el2_ifu_mem_ctl.scala 348:37] - io.ifu_ic_debug_rd_data <= _T_1211 @[el2_ifu_mem_ctl.scala 348:27] - node _T_1212 = bits(ifu_bus_rdata_ff, 15, 0) @[el2_ifu_mem_ctl.scala 349:74] + node ifu_ic_debug_rd_data_in = mux(_T_1201, _T_1210, io.ic_debug_rd_data) @[el2_ifu_mem_ctl.scala 346:36] + reg _T_1211 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 349:37] + _T_1211 <= ifu_ic_debug_rd_data_in @[el2_ifu_mem_ctl.scala 349:37] + io.ifu_ic_debug_rd_data <= _T_1211 @[el2_ifu_mem_ctl.scala 349:27] + node _T_1212 = bits(ifu_bus_rdata_ff, 15, 0) @[el2_ifu_mem_ctl.scala 350:74] node _T_1213 = xorr(_T_1212) @[el2_lib.scala 208:13] - node _T_1214 = bits(ifu_bus_rdata_ff, 31, 16) @[el2_ifu_mem_ctl.scala 349:74] + node _T_1214 = bits(ifu_bus_rdata_ff, 31, 16) @[el2_ifu_mem_ctl.scala 350:74] node _T_1215 = xorr(_T_1214) @[el2_lib.scala 208:13] - node _T_1216 = bits(ifu_bus_rdata_ff, 47, 32) @[el2_ifu_mem_ctl.scala 349:74] + node _T_1216 = bits(ifu_bus_rdata_ff, 47, 32) @[el2_ifu_mem_ctl.scala 350:74] node _T_1217 = xorr(_T_1216) @[el2_lib.scala 208:13] - node _T_1218 = bits(ifu_bus_rdata_ff, 63, 48) @[el2_ifu_mem_ctl.scala 349:74] + node _T_1218 = bits(ifu_bus_rdata_ff, 63, 48) @[el2_ifu_mem_ctl.scala 350:74] node _T_1219 = xorr(_T_1218) @[el2_lib.scala 208:13] node _T_1220 = cat(_T_1219, _T_1217) @[Cat.scala 29:58] node _T_1221 = cat(_T_1220, _T_1215) @[Cat.scala 29:58] node ic_wr_parity = cat(_T_1221, _T_1213) @[Cat.scala 29:58] - node _T_1222 = bits(ic_miss_buff_half, 15, 0) @[el2_ifu_mem_ctl.scala 350:82] + node _T_1222 = bits(ic_miss_buff_half, 15, 0) @[el2_ifu_mem_ctl.scala 351:82] node _T_1223 = xorr(_T_1222) @[el2_lib.scala 208:13] - node _T_1224 = bits(ic_miss_buff_half, 31, 16) @[el2_ifu_mem_ctl.scala 350:82] + node _T_1224 = bits(ic_miss_buff_half, 31, 16) @[el2_ifu_mem_ctl.scala 351:82] node _T_1225 = xorr(_T_1224) @[el2_lib.scala 208:13] - node _T_1226 = bits(ic_miss_buff_half, 47, 32) @[el2_ifu_mem_ctl.scala 350:82] + node _T_1226 = bits(ic_miss_buff_half, 47, 32) @[el2_ifu_mem_ctl.scala 351:82] node _T_1227 = xorr(_T_1226) @[el2_lib.scala 208:13] - node _T_1228 = bits(ic_miss_buff_half, 63, 48) @[el2_ifu_mem_ctl.scala 350:82] + node _T_1228 = bits(ic_miss_buff_half, 63, 48) @[el2_ifu_mem_ctl.scala 351:82] node _T_1229 = xorr(_T_1228) @[el2_lib.scala 208:13] node _T_1230 = cat(_T_1229, _T_1227) @[Cat.scala 29:58] node _T_1231 = cat(_T_1230, _T_1225) @[Cat.scala 29:58] node ic_miss_buff_parity = cat(_T_1231, _T_1223) @[Cat.scala 29:58] - node _T_1232 = bits(ifu_bus_rid_ff, 0, 0) @[el2_ifu_mem_ctl.scala 352:43] - node _T_1233 = bits(_T_1232, 0, 0) @[el2_ifu_mem_ctl.scala 352:47] - node _T_1234 = bits(ifu_bus_rdata_ff, 63, 0) @[el2_ifu_mem_ctl.scala 352:117] - node _T_1235 = bits(ic_miss_buff_half, 63, 0) @[el2_ifu_mem_ctl.scala 352:201] + node _T_1232 = bits(ifu_bus_rid_ff, 0, 0) @[el2_ifu_mem_ctl.scala 353:43] + node _T_1233 = bits(_T_1232, 0, 0) @[el2_ifu_mem_ctl.scala 353:47] + node _T_1234 = bits(ifu_bus_rdata_ff, 63, 0) @[el2_ifu_mem_ctl.scala 353:117] + node _T_1235 = bits(ic_miss_buff_half, 63, 0) @[el2_ifu_mem_ctl.scala 353:201] node _T_1236 = cat(ic_miss_buff_ecc, _T_1235) @[Cat.scala 29:58] node _T_1237 = cat(ic_wr_ecc, _T_1234) @[Cat.scala 29:58] node _T_1238 = cat(_T_1237, _T_1236) @[Cat.scala 29:58] node _T_1239 = cat(ic_wr_ecc, ifu_bus_rdata_ff) @[Cat.scala 29:58] node _T_1240 = cat(ic_miss_buff_ecc, ic_miss_buff_half) @[Cat.scala 29:58] node _T_1241 = cat(_T_1240, _T_1239) @[Cat.scala 29:58] - node _T_1242 = mux(_T_1233, _T_1238, _T_1241) @[el2_ifu_mem_ctl.scala 352:28] - ic_wr_16bytes_data <= _T_1242 @[el2_ifu_mem_ctl.scala 352:22] + node _T_1242 = mux(_T_1233, _T_1238, _T_1241) @[el2_ifu_mem_ctl.scala 353:28] + ic_wr_16bytes_data <= _T_1242 @[el2_ifu_mem_ctl.scala 353:22] wire bus_ifu_wr_data_error_ff : UInt<1> bus_ifu_wr_data_error_ff <= UInt<1>("h00") wire ifu_wr_data_comb_err_ff : UInt<1> ifu_wr_data_comb_err_ff <= UInt<1>("h00") wire reset_beat_cnt : UInt<1> reset_beat_cnt <= UInt<1>("h00") - node _T_1243 = or(bus_ifu_wr_data_error_ff, ifu_wr_data_comb_err_ff) @[el2_ifu_mem_ctl.scala 358:53] - node _T_1244 = eq(reset_beat_cnt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 358:82] - node ifu_wr_cumulative_err = and(_T_1243, _T_1244) @[el2_ifu_mem_ctl.scala 358:80] - node _T_1245 = or(bus_ifu_wr_data_error_ff, ifu_wr_data_comb_err_ff) @[el2_ifu_mem_ctl.scala 359:55] - ifu_wr_cumulative_err_data <= _T_1245 @[el2_ifu_mem_ctl.scala 359:30] - reg _T_1246 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 360:61] - _T_1246 <= ifu_wr_cumulative_err @[el2_ifu_mem_ctl.scala 360:61] - ifu_wr_data_comb_err_ff <= _T_1246 @[el2_ifu_mem_ctl.scala 360:27] + node _T_1243 = or(bus_ifu_wr_data_error_ff, ifu_wr_data_comb_err_ff) @[el2_ifu_mem_ctl.scala 359:53] + node _T_1244 = eq(reset_beat_cnt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 359:82] + node ifu_wr_cumulative_err = and(_T_1243, _T_1244) @[el2_ifu_mem_ctl.scala 359:80] + node _T_1245 = or(bus_ifu_wr_data_error_ff, ifu_wr_data_comb_err_ff) @[el2_ifu_mem_ctl.scala 360:55] + ifu_wr_cumulative_err_data <= _T_1245 @[el2_ifu_mem_ctl.scala 360:30] + reg _T_1246 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 361:61] + _T_1246 <= ifu_wr_cumulative_err @[el2_ifu_mem_ctl.scala 361:61] + ifu_wr_data_comb_err_ff <= _T_1246 @[el2_ifu_mem_ctl.scala 361:27] wire ic_crit_wd_rdy : UInt<1> ic_crit_wd_rdy <= UInt<1>("h00") wire ifu_byp_data_err_new : UInt<1> ifu_byp_data_err_new <= UInt<1>("h00") - node _T_1247 = eq(miss_state, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 363:51] - node _T_1248 = or(ic_crit_wd_rdy, _T_1247) @[el2_ifu_mem_ctl.scala 363:38] - node _T_1249 = eq(miss_state, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 363:77] - node _T_1250 = or(_T_1248, _T_1249) @[el2_ifu_mem_ctl.scala 363:64] - node _T_1251 = eq(ifu_byp_data_err_new, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 363:98] - node sel_byp_data = and(_T_1250, _T_1251) @[el2_ifu_mem_ctl.scala 363:96] - node _T_1252 = eq(miss_state, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 364:51] - node _T_1253 = or(ic_crit_wd_rdy, _T_1252) @[el2_ifu_mem_ctl.scala 364:38] - node _T_1254 = eq(miss_state, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 364:77] - node _T_1255 = or(_T_1253, _T_1254) @[el2_ifu_mem_ctl.scala 364:64] - node _T_1256 = eq(_T_1255, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 364:21] - node _T_1257 = eq(fetch_req_iccm_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 364:98] - node sel_ic_data = and(_T_1256, _T_1257) @[el2_ifu_mem_ctl.scala 364:96] + node _T_1247 = eq(miss_state, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 364:51] + node _T_1248 = or(ic_crit_wd_rdy, _T_1247) @[el2_ifu_mem_ctl.scala 364:38] + node _T_1249 = eq(miss_state, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 364:77] + node _T_1250 = or(_T_1248, _T_1249) @[el2_ifu_mem_ctl.scala 364:64] + node _T_1251 = eq(ifu_byp_data_err_new, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 364:98] + node sel_byp_data = and(_T_1250, _T_1251) @[el2_ifu_mem_ctl.scala 364:96] + node _T_1252 = eq(miss_state, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 365:51] + node _T_1253 = or(ic_crit_wd_rdy, _T_1252) @[el2_ifu_mem_ctl.scala 365:38] + node _T_1254 = eq(miss_state, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 365:77] + node _T_1255 = or(_T_1253, _T_1254) @[el2_ifu_mem_ctl.scala 365:64] + node _T_1256 = eq(_T_1255, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 365:21] + node _T_1257 = eq(fetch_req_iccm_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 365:98] + node sel_ic_data = and(_T_1256, _T_1257) @[el2_ifu_mem_ctl.scala 365:96] wire ic_byp_data_only_new : UInt<80> ic_byp_data_only_new <= UInt<1>("h00") - node _T_1258 = or(fetch_req_iccm_f, sel_ic_data) @[el2_ifu_mem_ctl.scala 368:81] - node _T_1259 = or(sel_byp_data, _T_1258) @[el2_ifu_mem_ctl.scala 368:47] - node _T_1260 = bits(_T_1259, 0, 0) @[el2_ifu_mem_ctl.scala 368:140] + node _T_1258 = or(fetch_req_iccm_f, sel_ic_data) @[el2_ifu_mem_ctl.scala 369:81] + node _T_1259 = or(sel_byp_data, _T_1258) @[el2_ifu_mem_ctl.scala 369:47] + node _T_1260 = bits(_T_1259, 0, 0) @[el2_ifu_mem_ctl.scala 369:140] node _T_1261 = bits(fetch_req_iccm_f, 0, 0) @[Bitwise.scala 72:15] node _T_1262 = mux(_T_1261, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12] - node _T_1263 = and(_T_1262, io.iccm_rd_data) @[el2_ifu_mem_ctl.scala 370:64] + node _T_1263 = and(_T_1262, io.iccm_rd_data) @[el2_ifu_mem_ctl.scala 371:64] node _T_1264 = bits(sel_byp_data, 0, 0) @[Bitwise.scala 72:15] node _T_1265 = mux(_T_1264, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12] - node _T_1266 = and(_T_1265, ic_byp_data_only_new) @[el2_ifu_mem_ctl.scala 370:109] - node ic_premux_data = or(_T_1263, _T_1266) @[el2_ifu_mem_ctl.scala 370:83] - node ic_sel_premux_data = or(fetch_req_iccm_f, sel_byp_data) @[el2_ifu_mem_ctl.scala 372:58] - io.ic_premux_data <= ic_premux_data @[el2_ifu_mem_ctl.scala 373:21] - io.ic_sel_premux_data <= ic_sel_premux_data @[el2_ifu_mem_ctl.scala 374:25] - node ifc_bus_acc_fault_f = and(ic_byp_hit_f, ifu_byp_data_err_new) @[el2_ifu_mem_ctl.scala 375:42] - io.ic_data_f <= io.ic_rd_data @[el2_ifu_mem_ctl.scala 376:16] - node _T_1267 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 377:40] - node fetch_req_f_qual = and(io.ic_hit_f, _T_1267) @[el2_ifu_mem_ctl.scala 377:38] + node _T_1266 = and(_T_1265, ic_byp_data_only_new) @[el2_ifu_mem_ctl.scala 371:109] + node ic_premux_data = or(_T_1263, _T_1266) @[el2_ifu_mem_ctl.scala 371:83] + node ic_sel_premux_data = or(fetch_req_iccm_f, sel_byp_data) @[el2_ifu_mem_ctl.scala 373:58] + io.ic_premux_data <= ic_premux_data @[el2_ifu_mem_ctl.scala 374:21] + io.ic_sel_premux_data <= ic_sel_premux_data @[el2_ifu_mem_ctl.scala 375:25] + node ifc_bus_acc_fault_f = and(ic_byp_hit_f, ifu_byp_data_err_new) @[el2_ifu_mem_ctl.scala 376:42] + io.ic_data_f <= io.ic_rd_data @[el2_ifu_mem_ctl.scala 377:16] + node _T_1267 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 378:40] + node fetch_req_f_qual = and(io.ic_hit_f, _T_1267) @[el2_ifu_mem_ctl.scala 378:38] wire ifc_region_acc_fault_memory_f : UInt<1> ifc_region_acc_fault_memory_f <= UInt<1>("h00") - node _T_1268 = or(ifc_region_acc_fault_final_f, ifc_bus_acc_fault_f) @[el2_ifu_mem_ctl.scala 379:57] - node _T_1269 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 379:82] - node _T_1270 = and(_T_1268, _T_1269) @[el2_ifu_mem_ctl.scala 379:80] - io.ic_access_fault_f <= _T_1270 @[el2_ifu_mem_ctl.scala 379:24] - node _T_1271 = bits(io.iccm_rd_ecc_double_err, 0, 0) @[el2_ifu_mem_ctl.scala 380:62] - node _T_1272 = bits(ifc_region_acc_fault_f, 0, 0) @[el2_ifu_mem_ctl.scala 381:32] - node _T_1273 = bits(ifc_region_acc_fault_memory_f, 0, 0) @[el2_ifu_mem_ctl.scala 382:47] - node _T_1274 = mux(_T_1273, UInt<2>("h03"), UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 382:10] - node _T_1275 = mux(_T_1272, UInt<2>("h02"), _T_1274) @[el2_ifu_mem_ctl.scala 381:8] - node _T_1276 = mux(_T_1271, UInt<1>("h01"), _T_1275) @[el2_ifu_mem_ctl.scala 380:35] - io.ic_access_fault_type_f <= _T_1276 @[el2_ifu_mem_ctl.scala 380:29] + node _T_1268 = or(ifc_region_acc_fault_final_f, ifc_bus_acc_fault_f) @[el2_ifu_mem_ctl.scala 380:57] + node _T_1269 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 380:82] + node _T_1270 = and(_T_1268, _T_1269) @[el2_ifu_mem_ctl.scala 380:80] + io.ic_access_fault_f <= _T_1270 @[el2_ifu_mem_ctl.scala 380:24] + node _T_1271 = bits(io.iccm_rd_ecc_double_err, 0, 0) @[el2_ifu_mem_ctl.scala 381:62] + node _T_1272 = bits(ifc_region_acc_fault_f, 0, 0) @[el2_ifu_mem_ctl.scala 382:32] + node _T_1273 = bits(ifc_region_acc_fault_memory_f, 0, 0) @[el2_ifu_mem_ctl.scala 383:47] + node _T_1274 = mux(_T_1273, UInt<2>("h03"), UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 383:10] + node _T_1275 = mux(_T_1272, UInt<2>("h02"), _T_1274) @[el2_ifu_mem_ctl.scala 382:8] + node _T_1276 = mux(_T_1271, UInt<1>("h01"), _T_1275) @[el2_ifu_mem_ctl.scala 381:35] + io.ic_access_fault_type_f <= _T_1276 @[el2_ifu_mem_ctl.scala 381:29] wire ifu_bp_inst_mask_f : UInt<1> ifu_bp_inst_mask_f <= UInt<1>("h00") - node _T_1277 = and(fetch_req_f_qual, ifu_bp_inst_mask_f) @[el2_ifu_mem_ctl.scala 384:45] + node _T_1277 = and(fetch_req_f_qual, ifu_bp_inst_mask_f) @[el2_ifu_mem_ctl.scala 385:45] node _T_1278 = mux(UInt<1>("h01"), UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] - node _T_1279 = eq(ifu_fetch_addr_int_f, _T_1278) @[el2_ifu_mem_ctl.scala 384:77] - node _T_1280 = eq(_T_1279, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 384:68] - node _T_1281 = and(_T_1277, _T_1280) @[el2_ifu_mem_ctl.scala 384:66] - node _T_1282 = neq(err_stop_state, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 384:128] - node _T_1283 = and(_T_1281, _T_1282) @[el2_ifu_mem_ctl.scala 384:111] + node _T_1279 = eq(ifu_fetch_addr_int_f, _T_1278) @[el2_ifu_mem_ctl.scala 385:77] + node _T_1280 = eq(_T_1279, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 385:68] + node _T_1281 = and(_T_1277, _T_1280) @[el2_ifu_mem_ctl.scala 385:66] + node _T_1282 = neq(err_stop_state, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 385:128] + node _T_1283 = and(_T_1281, _T_1282) @[el2_ifu_mem_ctl.scala 385:111] node _T_1284 = cat(_T_1283, fetch_req_f_qual) @[Cat.scala 29:58] - io.ic_fetch_val_f <= _T_1284 @[el2_ifu_mem_ctl.scala 384:21] - node _T_1285 = bits(io.ic_data_f, 1, 0) @[el2_ifu_mem_ctl.scala 385:36] - node two_byte_instr = neq(_T_1285, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 385:42] + io.ic_fetch_val_f <= _T_1284 @[el2_ifu_mem_ctl.scala 385:21] + node _T_1285 = bits(io.ic_data_f, 1, 0) @[el2_ifu_mem_ctl.scala 386:36] + node two_byte_instr = neq(_T_1285, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 386:42] wire ic_miss_buff_data_in : UInt<64> ic_miss_buff_data_in <= UInt<1>("h00") wire ifu_bus_rsp_tag : UInt<3> ifu_bus_rsp_tag <= UInt<1>("h00") wire bus_ifu_wr_en : UInt<1> bus_ifu_wr_en <= UInt<1>("h00") - node _T_1286 = eq(ifu_bus_rsp_tag, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 391:91] - node write_fill_data_0 = and(bus_ifu_wr_en, _T_1286) @[el2_ifu_mem_ctl.scala 391:73] - node _T_1287 = eq(ifu_bus_rsp_tag, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 391:91] - node write_fill_data_1 = and(bus_ifu_wr_en, _T_1287) @[el2_ifu_mem_ctl.scala 391:73] - node _T_1288 = eq(ifu_bus_rsp_tag, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 391:91] - node write_fill_data_2 = and(bus_ifu_wr_en, _T_1288) @[el2_ifu_mem_ctl.scala 391:73] - node _T_1289 = eq(ifu_bus_rsp_tag, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 391:91] - node write_fill_data_3 = and(bus_ifu_wr_en, _T_1289) @[el2_ifu_mem_ctl.scala 391:73] - node _T_1290 = eq(ifu_bus_rsp_tag, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 391:91] - node write_fill_data_4 = and(bus_ifu_wr_en, _T_1290) @[el2_ifu_mem_ctl.scala 391:73] - node _T_1291 = eq(ifu_bus_rsp_tag, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 391:91] - node write_fill_data_5 = and(bus_ifu_wr_en, _T_1291) @[el2_ifu_mem_ctl.scala 391:73] - node _T_1292 = eq(ifu_bus_rsp_tag, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 391:91] - node write_fill_data_6 = and(bus_ifu_wr_en, _T_1292) @[el2_ifu_mem_ctl.scala 391:73] - node _T_1293 = eq(ifu_bus_rsp_tag, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 391:91] - node write_fill_data_7 = and(bus_ifu_wr_en, _T_1293) @[el2_ifu_mem_ctl.scala 391:73] - wire ic_miss_buff_data : UInt<32>[16] @[el2_ifu_mem_ctl.scala 392:31] - node _T_1294 = bits(write_fill_data_0, 0, 0) @[el2_ifu_mem_ctl.scala 394:91] + node _T_1286 = eq(ifu_bus_rsp_tag, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 392:91] + node write_fill_data_0 = and(bus_ifu_wr_en, _T_1286) @[el2_ifu_mem_ctl.scala 392:73] + node _T_1287 = eq(ifu_bus_rsp_tag, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 392:91] + node write_fill_data_1 = and(bus_ifu_wr_en, _T_1287) @[el2_ifu_mem_ctl.scala 392:73] + node _T_1288 = eq(ifu_bus_rsp_tag, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 392:91] + node write_fill_data_2 = and(bus_ifu_wr_en, _T_1288) @[el2_ifu_mem_ctl.scala 392:73] + node _T_1289 = eq(ifu_bus_rsp_tag, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 392:91] + node write_fill_data_3 = and(bus_ifu_wr_en, _T_1289) @[el2_ifu_mem_ctl.scala 392:73] + node _T_1290 = eq(ifu_bus_rsp_tag, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 392:91] + node write_fill_data_4 = and(bus_ifu_wr_en, _T_1290) @[el2_ifu_mem_ctl.scala 392:73] + node _T_1291 = eq(ifu_bus_rsp_tag, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 392:91] + node write_fill_data_5 = and(bus_ifu_wr_en, _T_1291) @[el2_ifu_mem_ctl.scala 392:73] + node _T_1292 = eq(ifu_bus_rsp_tag, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 392:91] + node write_fill_data_6 = and(bus_ifu_wr_en, _T_1292) @[el2_ifu_mem_ctl.scala 392:73] + node _T_1293 = eq(ifu_bus_rsp_tag, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 392:91] + node write_fill_data_7 = and(bus_ifu_wr_en, _T_1293) @[el2_ifu_mem_ctl.scala 392:73] + wire ic_miss_buff_data : UInt<32>[16] @[el2_ifu_mem_ctl.scala 393:31] + node _T_1294 = bits(write_fill_data_0, 0, 0) @[el2_ifu_mem_ctl.scala 395:91] reg _T_1295 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_1294 : @[Reg.scala 28:19] _T_1295 <= ic_miss_buff_data_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_miss_buff_data[0] <= _T_1295 @[el2_ifu_mem_ctl.scala 394:26] - node _T_1296 = bits(write_fill_data_0, 0, 0) @[el2_ifu_mem_ctl.scala 395:93] + ic_miss_buff_data[0] <= _T_1295 @[el2_ifu_mem_ctl.scala 395:26] + node _T_1296 = bits(write_fill_data_0, 0, 0) @[el2_ifu_mem_ctl.scala 396:93] reg _T_1297 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_1296 : @[Reg.scala 28:19] _T_1297 <= ic_miss_buff_data_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_miss_buff_data[1] <= _T_1297 @[el2_ifu_mem_ctl.scala 395:28] - node _T_1298 = bits(write_fill_data_1, 0, 0) @[el2_ifu_mem_ctl.scala 394:91] + ic_miss_buff_data[1] <= _T_1297 @[el2_ifu_mem_ctl.scala 396:28] + node _T_1298 = bits(write_fill_data_1, 0, 0) @[el2_ifu_mem_ctl.scala 395:91] reg _T_1299 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_1298 : @[Reg.scala 28:19] _T_1299 <= ic_miss_buff_data_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_miss_buff_data[2] <= _T_1299 @[el2_ifu_mem_ctl.scala 394:26] - node _T_1300 = bits(write_fill_data_1, 0, 0) @[el2_ifu_mem_ctl.scala 395:93] + ic_miss_buff_data[2] <= _T_1299 @[el2_ifu_mem_ctl.scala 395:26] + node _T_1300 = bits(write_fill_data_1, 0, 0) @[el2_ifu_mem_ctl.scala 396:93] reg _T_1301 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_1300 : @[Reg.scala 28:19] _T_1301 <= ic_miss_buff_data_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_miss_buff_data[3] <= _T_1301 @[el2_ifu_mem_ctl.scala 395:28] - node _T_1302 = bits(write_fill_data_2, 0, 0) @[el2_ifu_mem_ctl.scala 394:91] + ic_miss_buff_data[3] <= _T_1301 @[el2_ifu_mem_ctl.scala 396:28] + node _T_1302 = bits(write_fill_data_2, 0, 0) @[el2_ifu_mem_ctl.scala 395:91] reg _T_1303 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_1302 : @[Reg.scala 28:19] _T_1303 <= ic_miss_buff_data_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_miss_buff_data[4] <= _T_1303 @[el2_ifu_mem_ctl.scala 394:26] - node _T_1304 = bits(write_fill_data_2, 0, 0) @[el2_ifu_mem_ctl.scala 395:93] + ic_miss_buff_data[4] <= _T_1303 @[el2_ifu_mem_ctl.scala 395:26] + node _T_1304 = bits(write_fill_data_2, 0, 0) @[el2_ifu_mem_ctl.scala 396:93] reg _T_1305 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_1304 : @[Reg.scala 28:19] _T_1305 <= ic_miss_buff_data_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_miss_buff_data[5] <= _T_1305 @[el2_ifu_mem_ctl.scala 395:28] - node _T_1306 = bits(write_fill_data_3, 0, 0) @[el2_ifu_mem_ctl.scala 394:91] + ic_miss_buff_data[5] <= _T_1305 @[el2_ifu_mem_ctl.scala 396:28] + node _T_1306 = bits(write_fill_data_3, 0, 0) @[el2_ifu_mem_ctl.scala 395:91] reg _T_1307 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_1306 : @[Reg.scala 28:19] _T_1307 <= ic_miss_buff_data_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_miss_buff_data[6] <= _T_1307 @[el2_ifu_mem_ctl.scala 394:26] - node _T_1308 = bits(write_fill_data_3, 0, 0) @[el2_ifu_mem_ctl.scala 395:93] + ic_miss_buff_data[6] <= _T_1307 @[el2_ifu_mem_ctl.scala 395:26] + node _T_1308 = bits(write_fill_data_3, 0, 0) @[el2_ifu_mem_ctl.scala 396:93] reg _T_1309 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_1308 : @[Reg.scala 28:19] _T_1309 <= ic_miss_buff_data_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_miss_buff_data[7] <= _T_1309 @[el2_ifu_mem_ctl.scala 395:28] - node _T_1310 = bits(write_fill_data_4, 0, 0) @[el2_ifu_mem_ctl.scala 394:91] + ic_miss_buff_data[7] <= _T_1309 @[el2_ifu_mem_ctl.scala 396:28] + node _T_1310 = bits(write_fill_data_4, 0, 0) @[el2_ifu_mem_ctl.scala 395:91] reg _T_1311 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_1310 : @[Reg.scala 28:19] _T_1311 <= ic_miss_buff_data_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_miss_buff_data[8] <= _T_1311 @[el2_ifu_mem_ctl.scala 394:26] - node _T_1312 = bits(write_fill_data_4, 0, 0) @[el2_ifu_mem_ctl.scala 395:93] + ic_miss_buff_data[8] <= _T_1311 @[el2_ifu_mem_ctl.scala 395:26] + node _T_1312 = bits(write_fill_data_4, 0, 0) @[el2_ifu_mem_ctl.scala 396:93] reg _T_1313 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_1312 : @[Reg.scala 28:19] _T_1313 <= ic_miss_buff_data_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_miss_buff_data[9] <= _T_1313 @[el2_ifu_mem_ctl.scala 395:28] - node _T_1314 = bits(write_fill_data_5, 0, 0) @[el2_ifu_mem_ctl.scala 394:91] + ic_miss_buff_data[9] <= _T_1313 @[el2_ifu_mem_ctl.scala 396:28] + node _T_1314 = bits(write_fill_data_5, 0, 0) @[el2_ifu_mem_ctl.scala 395:91] reg _T_1315 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_1314 : @[Reg.scala 28:19] _T_1315 <= ic_miss_buff_data_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_miss_buff_data[10] <= _T_1315 @[el2_ifu_mem_ctl.scala 394:26] - node _T_1316 = bits(write_fill_data_5, 0, 0) @[el2_ifu_mem_ctl.scala 395:93] + ic_miss_buff_data[10] <= _T_1315 @[el2_ifu_mem_ctl.scala 395:26] + node _T_1316 = bits(write_fill_data_5, 0, 0) @[el2_ifu_mem_ctl.scala 396:93] reg _T_1317 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_1316 : @[Reg.scala 28:19] _T_1317 <= ic_miss_buff_data_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_miss_buff_data[11] <= _T_1317 @[el2_ifu_mem_ctl.scala 395:28] - node _T_1318 = bits(write_fill_data_6, 0, 0) @[el2_ifu_mem_ctl.scala 394:91] + ic_miss_buff_data[11] <= _T_1317 @[el2_ifu_mem_ctl.scala 396:28] + node _T_1318 = bits(write_fill_data_6, 0, 0) @[el2_ifu_mem_ctl.scala 395:91] reg _T_1319 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_1318 : @[Reg.scala 28:19] _T_1319 <= ic_miss_buff_data_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_miss_buff_data[12] <= _T_1319 @[el2_ifu_mem_ctl.scala 394:26] - node _T_1320 = bits(write_fill_data_6, 0, 0) @[el2_ifu_mem_ctl.scala 395:93] + ic_miss_buff_data[12] <= _T_1319 @[el2_ifu_mem_ctl.scala 395:26] + node _T_1320 = bits(write_fill_data_6, 0, 0) @[el2_ifu_mem_ctl.scala 396:93] reg _T_1321 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_1320 : @[Reg.scala 28:19] _T_1321 <= ic_miss_buff_data_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_miss_buff_data[13] <= _T_1321 @[el2_ifu_mem_ctl.scala 395:28] - node _T_1322 = bits(write_fill_data_7, 0, 0) @[el2_ifu_mem_ctl.scala 394:91] + ic_miss_buff_data[13] <= _T_1321 @[el2_ifu_mem_ctl.scala 396:28] + node _T_1322 = bits(write_fill_data_7, 0, 0) @[el2_ifu_mem_ctl.scala 395:91] reg _T_1323 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_1322 : @[Reg.scala 28:19] _T_1323 <= ic_miss_buff_data_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_miss_buff_data[14] <= _T_1323 @[el2_ifu_mem_ctl.scala 394:26] - node _T_1324 = bits(write_fill_data_7, 0, 0) @[el2_ifu_mem_ctl.scala 395:93] + ic_miss_buff_data[14] <= _T_1323 @[el2_ifu_mem_ctl.scala 395:26] + node _T_1324 = bits(write_fill_data_7, 0, 0) @[el2_ifu_mem_ctl.scala 396:93] reg _T_1325 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_1324 : @[Reg.scala 28:19] _T_1325 <= ic_miss_buff_data_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_miss_buff_data[15] <= _T_1325 @[el2_ifu_mem_ctl.scala 395:28] + ic_miss_buff_data[15] <= _T_1325 @[el2_ifu_mem_ctl.scala 396:28] wire ic_miss_buff_data_valid : UInt<8> ic_miss_buff_data_valid <= UInt<1>("h00") - node _T_1326 = bits(ic_miss_buff_data_valid, 0, 0) @[el2_ifu_mem_ctl.scala 397:113] - node _T_1327 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 397:118] - node _T_1328 = and(_T_1326, _T_1327) @[el2_ifu_mem_ctl.scala 397:116] - node ic_miss_buff_data_valid_in_0 = or(write_fill_data_0, _T_1328) @[el2_ifu_mem_ctl.scala 397:88] - node _T_1329 = bits(ic_miss_buff_data_valid, 1, 1) @[el2_ifu_mem_ctl.scala 397:113] - node _T_1330 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 397:118] - node _T_1331 = and(_T_1329, _T_1330) @[el2_ifu_mem_ctl.scala 397:116] - node ic_miss_buff_data_valid_in_1 = or(write_fill_data_1, _T_1331) @[el2_ifu_mem_ctl.scala 397:88] - node _T_1332 = bits(ic_miss_buff_data_valid, 2, 2) @[el2_ifu_mem_ctl.scala 397:113] - node _T_1333 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 397:118] - node _T_1334 = and(_T_1332, _T_1333) @[el2_ifu_mem_ctl.scala 397:116] - node ic_miss_buff_data_valid_in_2 = or(write_fill_data_2, _T_1334) @[el2_ifu_mem_ctl.scala 397:88] - node _T_1335 = bits(ic_miss_buff_data_valid, 3, 3) @[el2_ifu_mem_ctl.scala 397:113] - node _T_1336 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 397:118] - node _T_1337 = and(_T_1335, _T_1336) @[el2_ifu_mem_ctl.scala 397:116] - node ic_miss_buff_data_valid_in_3 = or(write_fill_data_3, _T_1337) @[el2_ifu_mem_ctl.scala 397:88] - node _T_1338 = bits(ic_miss_buff_data_valid, 4, 4) @[el2_ifu_mem_ctl.scala 397:113] - node _T_1339 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 397:118] - node _T_1340 = and(_T_1338, _T_1339) @[el2_ifu_mem_ctl.scala 397:116] - node ic_miss_buff_data_valid_in_4 = or(write_fill_data_4, _T_1340) @[el2_ifu_mem_ctl.scala 397:88] - node _T_1341 = bits(ic_miss_buff_data_valid, 5, 5) @[el2_ifu_mem_ctl.scala 397:113] - node _T_1342 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 397:118] - node _T_1343 = and(_T_1341, _T_1342) @[el2_ifu_mem_ctl.scala 397:116] - node ic_miss_buff_data_valid_in_5 = or(write_fill_data_5, _T_1343) @[el2_ifu_mem_ctl.scala 397:88] - node _T_1344 = bits(ic_miss_buff_data_valid, 6, 6) @[el2_ifu_mem_ctl.scala 397:113] - node _T_1345 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 397:118] - node _T_1346 = and(_T_1344, _T_1345) @[el2_ifu_mem_ctl.scala 397:116] - node ic_miss_buff_data_valid_in_6 = or(write_fill_data_6, _T_1346) @[el2_ifu_mem_ctl.scala 397:88] - node _T_1347 = bits(ic_miss_buff_data_valid, 7, 7) @[el2_ifu_mem_ctl.scala 397:113] - node _T_1348 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 397:118] - node _T_1349 = and(_T_1347, _T_1348) @[el2_ifu_mem_ctl.scala 397:116] - node ic_miss_buff_data_valid_in_7 = or(write_fill_data_7, _T_1349) @[el2_ifu_mem_ctl.scala 397:88] + node _T_1326 = bits(ic_miss_buff_data_valid, 0, 0) @[el2_ifu_mem_ctl.scala 398:113] + node _T_1327 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 398:118] + node _T_1328 = and(_T_1326, _T_1327) @[el2_ifu_mem_ctl.scala 398:116] + node ic_miss_buff_data_valid_in_0 = or(write_fill_data_0, _T_1328) @[el2_ifu_mem_ctl.scala 398:88] + node _T_1329 = bits(ic_miss_buff_data_valid, 1, 1) @[el2_ifu_mem_ctl.scala 398:113] + node _T_1330 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 398:118] + node _T_1331 = and(_T_1329, _T_1330) @[el2_ifu_mem_ctl.scala 398:116] + node ic_miss_buff_data_valid_in_1 = or(write_fill_data_1, _T_1331) @[el2_ifu_mem_ctl.scala 398:88] + node _T_1332 = bits(ic_miss_buff_data_valid, 2, 2) @[el2_ifu_mem_ctl.scala 398:113] + node _T_1333 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 398:118] + node _T_1334 = and(_T_1332, _T_1333) @[el2_ifu_mem_ctl.scala 398:116] + node ic_miss_buff_data_valid_in_2 = or(write_fill_data_2, _T_1334) @[el2_ifu_mem_ctl.scala 398:88] + node _T_1335 = bits(ic_miss_buff_data_valid, 3, 3) @[el2_ifu_mem_ctl.scala 398:113] + node _T_1336 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 398:118] + node _T_1337 = and(_T_1335, _T_1336) @[el2_ifu_mem_ctl.scala 398:116] + node ic_miss_buff_data_valid_in_3 = or(write_fill_data_3, _T_1337) @[el2_ifu_mem_ctl.scala 398:88] + node _T_1338 = bits(ic_miss_buff_data_valid, 4, 4) @[el2_ifu_mem_ctl.scala 398:113] + node _T_1339 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 398:118] + node _T_1340 = and(_T_1338, _T_1339) @[el2_ifu_mem_ctl.scala 398:116] + node ic_miss_buff_data_valid_in_4 = or(write_fill_data_4, _T_1340) @[el2_ifu_mem_ctl.scala 398:88] + node _T_1341 = bits(ic_miss_buff_data_valid, 5, 5) @[el2_ifu_mem_ctl.scala 398:113] + node _T_1342 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 398:118] + node _T_1343 = and(_T_1341, _T_1342) @[el2_ifu_mem_ctl.scala 398:116] + node ic_miss_buff_data_valid_in_5 = or(write_fill_data_5, _T_1343) @[el2_ifu_mem_ctl.scala 398:88] + node _T_1344 = bits(ic_miss_buff_data_valid, 6, 6) @[el2_ifu_mem_ctl.scala 398:113] + node _T_1345 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 398:118] + node _T_1346 = and(_T_1344, _T_1345) @[el2_ifu_mem_ctl.scala 398:116] + node ic_miss_buff_data_valid_in_6 = or(write_fill_data_6, _T_1346) @[el2_ifu_mem_ctl.scala 398:88] + node _T_1347 = bits(ic_miss_buff_data_valid, 7, 7) @[el2_ifu_mem_ctl.scala 398:113] + node _T_1348 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 398:118] + node _T_1349 = and(_T_1347, _T_1348) @[el2_ifu_mem_ctl.scala 398:116] + node ic_miss_buff_data_valid_in_7 = or(write_fill_data_7, _T_1349) @[el2_ifu_mem_ctl.scala 398:88] node _T_1350 = cat(ic_miss_buff_data_valid_in_7, ic_miss_buff_data_valid_in_6) @[Cat.scala 29:58] node _T_1351 = cat(_T_1350, ic_miss_buff_data_valid_in_5) @[Cat.scala 29:58] node _T_1352 = cat(_T_1351, ic_miss_buff_data_valid_in_4) @[Cat.scala 29:58] @@ -2167,53 +2167,53 @@ circuit el2_ifu_mem_ctl : node _T_1354 = cat(_T_1353, ic_miss_buff_data_valid_in_2) @[Cat.scala 29:58] node _T_1355 = cat(_T_1354, ic_miss_buff_data_valid_in_1) @[Cat.scala 29:58] node _T_1356 = cat(_T_1355, ic_miss_buff_data_valid_in_0) @[Cat.scala 29:58] - reg _T_1357 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 398:60] - _T_1357 <= _T_1356 @[el2_ifu_mem_ctl.scala 398:60] - ic_miss_buff_data_valid <= _T_1357 @[el2_ifu_mem_ctl.scala 398:27] + reg _T_1357 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 399:60] + _T_1357 <= _T_1356 @[el2_ifu_mem_ctl.scala 399:60] + ic_miss_buff_data_valid <= _T_1357 @[el2_ifu_mem_ctl.scala 399:27] wire bus_ifu_wr_data_error : UInt<1> bus_ifu_wr_data_error <= UInt<1>("h00") wire ic_miss_buff_data_error : UInt<8> ic_miss_buff_data_error <= UInt<1>("h00") - node _T_1358 = bits(write_fill_data_0, 0, 0) @[el2_ifu_mem_ctl.scala 401:92] - node _T_1359 = bits(ic_miss_buff_data_error, 0, 0) @[el2_ifu_mem_ctl.scala 402:28] - node _T_1360 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 402:34] - node _T_1361 = and(_T_1359, _T_1360) @[el2_ifu_mem_ctl.scala 402:32] - node ic_miss_buff_data_error_in_0 = mux(_T_1358, bus_ifu_wr_data_error, _T_1361) @[el2_ifu_mem_ctl.scala 401:72] - node _T_1362 = bits(write_fill_data_1, 0, 0) @[el2_ifu_mem_ctl.scala 401:92] - node _T_1363 = bits(ic_miss_buff_data_error, 1, 1) @[el2_ifu_mem_ctl.scala 402:28] - node _T_1364 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 402:34] - node _T_1365 = and(_T_1363, _T_1364) @[el2_ifu_mem_ctl.scala 402:32] - node ic_miss_buff_data_error_in_1 = mux(_T_1362, bus_ifu_wr_data_error, _T_1365) @[el2_ifu_mem_ctl.scala 401:72] - node _T_1366 = bits(write_fill_data_2, 0, 0) @[el2_ifu_mem_ctl.scala 401:92] - node _T_1367 = bits(ic_miss_buff_data_error, 2, 2) @[el2_ifu_mem_ctl.scala 402:28] - node _T_1368 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 402:34] - node _T_1369 = and(_T_1367, _T_1368) @[el2_ifu_mem_ctl.scala 402:32] - node ic_miss_buff_data_error_in_2 = mux(_T_1366, bus_ifu_wr_data_error, _T_1369) @[el2_ifu_mem_ctl.scala 401:72] - node _T_1370 = bits(write_fill_data_3, 0, 0) @[el2_ifu_mem_ctl.scala 401:92] - node _T_1371 = bits(ic_miss_buff_data_error, 3, 3) @[el2_ifu_mem_ctl.scala 402:28] - node _T_1372 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 402:34] - node _T_1373 = and(_T_1371, _T_1372) @[el2_ifu_mem_ctl.scala 402:32] - node ic_miss_buff_data_error_in_3 = mux(_T_1370, bus_ifu_wr_data_error, _T_1373) @[el2_ifu_mem_ctl.scala 401:72] - node _T_1374 = bits(write_fill_data_4, 0, 0) @[el2_ifu_mem_ctl.scala 401:92] - node _T_1375 = bits(ic_miss_buff_data_error, 4, 4) @[el2_ifu_mem_ctl.scala 402:28] - node _T_1376 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 402:34] - node _T_1377 = and(_T_1375, _T_1376) @[el2_ifu_mem_ctl.scala 402:32] - node ic_miss_buff_data_error_in_4 = mux(_T_1374, bus_ifu_wr_data_error, _T_1377) @[el2_ifu_mem_ctl.scala 401:72] - node _T_1378 = bits(write_fill_data_5, 0, 0) @[el2_ifu_mem_ctl.scala 401:92] - node _T_1379 = bits(ic_miss_buff_data_error, 5, 5) @[el2_ifu_mem_ctl.scala 402:28] - node _T_1380 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 402:34] - node _T_1381 = and(_T_1379, _T_1380) @[el2_ifu_mem_ctl.scala 402:32] - node ic_miss_buff_data_error_in_5 = mux(_T_1378, bus_ifu_wr_data_error, _T_1381) @[el2_ifu_mem_ctl.scala 401:72] - node _T_1382 = bits(write_fill_data_6, 0, 0) @[el2_ifu_mem_ctl.scala 401:92] - node _T_1383 = bits(ic_miss_buff_data_error, 6, 6) @[el2_ifu_mem_ctl.scala 402:28] - node _T_1384 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 402:34] - node _T_1385 = and(_T_1383, _T_1384) @[el2_ifu_mem_ctl.scala 402:32] - node ic_miss_buff_data_error_in_6 = mux(_T_1382, bus_ifu_wr_data_error, _T_1385) @[el2_ifu_mem_ctl.scala 401:72] - node _T_1386 = bits(write_fill_data_7, 0, 0) @[el2_ifu_mem_ctl.scala 401:92] - node _T_1387 = bits(ic_miss_buff_data_error, 7, 7) @[el2_ifu_mem_ctl.scala 402:28] - node _T_1388 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 402:34] - node _T_1389 = and(_T_1387, _T_1388) @[el2_ifu_mem_ctl.scala 402:32] - node ic_miss_buff_data_error_in_7 = mux(_T_1386, bus_ifu_wr_data_error, _T_1389) @[el2_ifu_mem_ctl.scala 401:72] + node _T_1358 = bits(write_fill_data_0, 0, 0) @[el2_ifu_mem_ctl.scala 402:92] + node _T_1359 = bits(ic_miss_buff_data_error, 0, 0) @[el2_ifu_mem_ctl.scala 403:28] + node _T_1360 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 403:34] + node _T_1361 = and(_T_1359, _T_1360) @[el2_ifu_mem_ctl.scala 403:32] + node ic_miss_buff_data_error_in_0 = mux(_T_1358, bus_ifu_wr_data_error, _T_1361) @[el2_ifu_mem_ctl.scala 402:72] + node _T_1362 = bits(write_fill_data_1, 0, 0) @[el2_ifu_mem_ctl.scala 402:92] + node _T_1363 = bits(ic_miss_buff_data_error, 1, 1) @[el2_ifu_mem_ctl.scala 403:28] + node _T_1364 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 403:34] + node _T_1365 = and(_T_1363, _T_1364) @[el2_ifu_mem_ctl.scala 403:32] + node ic_miss_buff_data_error_in_1 = mux(_T_1362, bus_ifu_wr_data_error, _T_1365) @[el2_ifu_mem_ctl.scala 402:72] + node _T_1366 = bits(write_fill_data_2, 0, 0) @[el2_ifu_mem_ctl.scala 402:92] + node _T_1367 = bits(ic_miss_buff_data_error, 2, 2) @[el2_ifu_mem_ctl.scala 403:28] + node _T_1368 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 403:34] + node _T_1369 = and(_T_1367, _T_1368) @[el2_ifu_mem_ctl.scala 403:32] + node ic_miss_buff_data_error_in_2 = mux(_T_1366, bus_ifu_wr_data_error, _T_1369) @[el2_ifu_mem_ctl.scala 402:72] + node _T_1370 = bits(write_fill_data_3, 0, 0) @[el2_ifu_mem_ctl.scala 402:92] + node _T_1371 = bits(ic_miss_buff_data_error, 3, 3) @[el2_ifu_mem_ctl.scala 403:28] + node _T_1372 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 403:34] + node _T_1373 = and(_T_1371, _T_1372) @[el2_ifu_mem_ctl.scala 403:32] + node ic_miss_buff_data_error_in_3 = mux(_T_1370, bus_ifu_wr_data_error, _T_1373) @[el2_ifu_mem_ctl.scala 402:72] + node _T_1374 = bits(write_fill_data_4, 0, 0) @[el2_ifu_mem_ctl.scala 402:92] + node _T_1375 = bits(ic_miss_buff_data_error, 4, 4) @[el2_ifu_mem_ctl.scala 403:28] + node _T_1376 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 403:34] + node _T_1377 = and(_T_1375, _T_1376) @[el2_ifu_mem_ctl.scala 403:32] + node ic_miss_buff_data_error_in_4 = mux(_T_1374, bus_ifu_wr_data_error, _T_1377) @[el2_ifu_mem_ctl.scala 402:72] + node _T_1378 = bits(write_fill_data_5, 0, 0) @[el2_ifu_mem_ctl.scala 402:92] + node _T_1379 = bits(ic_miss_buff_data_error, 5, 5) @[el2_ifu_mem_ctl.scala 403:28] + node _T_1380 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 403:34] + node _T_1381 = and(_T_1379, _T_1380) @[el2_ifu_mem_ctl.scala 403:32] + node ic_miss_buff_data_error_in_5 = mux(_T_1378, bus_ifu_wr_data_error, _T_1381) @[el2_ifu_mem_ctl.scala 402:72] + node _T_1382 = bits(write_fill_data_6, 0, 0) @[el2_ifu_mem_ctl.scala 402:92] + node _T_1383 = bits(ic_miss_buff_data_error, 6, 6) @[el2_ifu_mem_ctl.scala 403:28] + node _T_1384 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 403:34] + node _T_1385 = and(_T_1383, _T_1384) @[el2_ifu_mem_ctl.scala 403:32] + node ic_miss_buff_data_error_in_6 = mux(_T_1382, bus_ifu_wr_data_error, _T_1385) @[el2_ifu_mem_ctl.scala 402:72] + node _T_1386 = bits(write_fill_data_7, 0, 0) @[el2_ifu_mem_ctl.scala 402:92] + node _T_1387 = bits(ic_miss_buff_data_error, 7, 7) @[el2_ifu_mem_ctl.scala 403:28] + node _T_1388 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 403:34] + node _T_1389 = and(_T_1387, _T_1388) @[el2_ifu_mem_ctl.scala 403:32] + node ic_miss_buff_data_error_in_7 = mux(_T_1386, bus_ifu_wr_data_error, _T_1389) @[el2_ifu_mem_ctl.scala 402:72] node _T_1390 = cat(ic_miss_buff_data_error_in_7, ic_miss_buff_data_error_in_6) @[Cat.scala 29:58] node _T_1391 = cat(_T_1390, ic_miss_buff_data_error_in_5) @[Cat.scala 29:58] node _T_1392 = cat(_T_1391, ic_miss_buff_data_error_in_4) @[Cat.scala 29:58] @@ -2221,37 +2221,37 @@ circuit el2_ifu_mem_ctl : node _T_1394 = cat(_T_1393, ic_miss_buff_data_error_in_2) @[Cat.scala 29:58] node _T_1395 = cat(_T_1394, ic_miss_buff_data_error_in_1) @[Cat.scala 29:58] node _T_1396 = cat(_T_1395, ic_miss_buff_data_error_in_0) @[Cat.scala 29:58] - reg _T_1397 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 403:60] - _T_1397 <= _T_1396 @[el2_ifu_mem_ctl.scala 403:60] - ic_miss_buff_data_error <= _T_1397 @[el2_ifu_mem_ctl.scala 403:27] - node bypass_index = bits(imb_ff, 4, 0) @[el2_ifu_mem_ctl.scala 406:28] - node _T_1398 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 407:42] - node _T_1399 = add(_T_1398, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 407:70] - node bypass_index_5_3_inc = tail(_T_1399, 1) @[el2_ifu_mem_ctl.scala 407:70] - node _T_1400 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 408:87] - node _T_1401 = eq(_T_1400, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 408:114] - node _T_1402 = bits(_T_1401, 0, 0) @[el2_ifu_mem_ctl.scala 408:122] - node _T_1403 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 408:87] - node _T_1404 = eq(_T_1403, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 408:114] - node _T_1405 = bits(_T_1404, 0, 0) @[el2_ifu_mem_ctl.scala 408:122] - node _T_1406 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 408:87] - node _T_1407 = eq(_T_1406, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 408:114] - node _T_1408 = bits(_T_1407, 0, 0) @[el2_ifu_mem_ctl.scala 408:122] - node _T_1409 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 408:87] - node _T_1410 = eq(_T_1409, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 408:114] - node _T_1411 = bits(_T_1410, 0, 0) @[el2_ifu_mem_ctl.scala 408:122] - node _T_1412 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 408:87] - node _T_1413 = eq(_T_1412, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 408:114] - node _T_1414 = bits(_T_1413, 0, 0) @[el2_ifu_mem_ctl.scala 408:122] - node _T_1415 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 408:87] - node _T_1416 = eq(_T_1415, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 408:114] - node _T_1417 = bits(_T_1416, 0, 0) @[el2_ifu_mem_ctl.scala 408:122] - node _T_1418 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 408:87] - node _T_1419 = eq(_T_1418, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 408:114] - node _T_1420 = bits(_T_1419, 0, 0) @[el2_ifu_mem_ctl.scala 408:122] - node _T_1421 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 408:87] - node _T_1422 = eq(_T_1421, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 408:114] - node _T_1423 = bits(_T_1422, 0, 0) @[el2_ifu_mem_ctl.scala 408:122] + reg _T_1397 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 404:60] + _T_1397 <= _T_1396 @[el2_ifu_mem_ctl.scala 404:60] + ic_miss_buff_data_error <= _T_1397 @[el2_ifu_mem_ctl.scala 404:27] + node bypass_index = bits(imb_ff, 4, 0) @[el2_ifu_mem_ctl.scala 407:28] + node _T_1398 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 408:42] + node _T_1399 = add(_T_1398, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 408:70] + node bypass_index_5_3_inc = tail(_T_1399, 1) @[el2_ifu_mem_ctl.scala 408:70] + node _T_1400 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 409:87] + node _T_1401 = eq(_T_1400, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 409:114] + node _T_1402 = bits(_T_1401, 0, 0) @[el2_ifu_mem_ctl.scala 409:122] + node _T_1403 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 409:87] + node _T_1404 = eq(_T_1403, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 409:114] + node _T_1405 = bits(_T_1404, 0, 0) @[el2_ifu_mem_ctl.scala 409:122] + node _T_1406 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 409:87] + node _T_1407 = eq(_T_1406, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 409:114] + node _T_1408 = bits(_T_1407, 0, 0) @[el2_ifu_mem_ctl.scala 409:122] + node _T_1409 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 409:87] + node _T_1410 = eq(_T_1409, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 409:114] + node _T_1411 = bits(_T_1410, 0, 0) @[el2_ifu_mem_ctl.scala 409:122] + node _T_1412 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 409:87] + node _T_1413 = eq(_T_1412, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 409:114] + node _T_1414 = bits(_T_1413, 0, 0) @[el2_ifu_mem_ctl.scala 409:122] + node _T_1415 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 409:87] + node _T_1416 = eq(_T_1415, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 409:114] + node _T_1417 = bits(_T_1416, 0, 0) @[el2_ifu_mem_ctl.scala 409:122] + node _T_1418 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 409:87] + node _T_1419 = eq(_T_1418, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 409:114] + node _T_1420 = bits(_T_1419, 0, 0) @[el2_ifu_mem_ctl.scala 409:122] + node _T_1421 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 409:87] + node _T_1422 = eq(_T_1421, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 409:114] + node _T_1423 = bits(_T_1422, 0, 0) @[el2_ifu_mem_ctl.scala 409:122] node _T_1424 = mux(_T_1402, ic_miss_buff_data_valid_in_0, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1425 = mux(_T_1405, ic_miss_buff_data_valid_in_1, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1426 = mux(_T_1408, ic_miss_buff_data_valid_in_2, UInt<1>("h00")) @[Mux.scala 27:72] @@ -2269,44 +2269,44 @@ circuit el2_ifu_mem_ctl : node _T_1438 = or(_T_1437, _T_1431) @[Mux.scala 27:72] wire bypass_valid_value_check : UInt<1> @[Mux.scala 27:72] bypass_valid_value_check <= _T_1438 @[Mux.scala 27:72] - node _T_1439 = bits(bypass_index, 1, 1) @[el2_ifu_mem_ctl.scala 409:71] - node _T_1440 = eq(_T_1439, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 409:58] - node _T_1441 = and(bypass_valid_value_check, _T_1440) @[el2_ifu_mem_ctl.scala 409:56] - node _T_1442 = bits(bypass_index, 0, 0) @[el2_ifu_mem_ctl.scala 409:90] - node _T_1443 = eq(_T_1442, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 409:77] - node _T_1444 = and(_T_1441, _T_1443) @[el2_ifu_mem_ctl.scala 409:75] - node _T_1445 = bits(bypass_index, 1, 1) @[el2_ifu_mem_ctl.scala 410:71] - node _T_1446 = eq(_T_1445, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 410:58] - node _T_1447 = and(bypass_valid_value_check, _T_1446) @[el2_ifu_mem_ctl.scala 410:56] - node _T_1448 = bits(bypass_index, 0, 0) @[el2_ifu_mem_ctl.scala 410:89] - node _T_1449 = and(_T_1447, _T_1448) @[el2_ifu_mem_ctl.scala 410:75] - node _T_1450 = or(_T_1444, _T_1449) @[el2_ifu_mem_ctl.scala 409:95] - node _T_1451 = bits(bypass_index, 1, 1) @[el2_ifu_mem_ctl.scala 411:70] - node _T_1452 = and(bypass_valid_value_check, _T_1451) @[el2_ifu_mem_ctl.scala 411:56] - node _T_1453 = bits(bypass_index, 0, 0) @[el2_ifu_mem_ctl.scala 411:89] - node _T_1454 = eq(_T_1453, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 411:76] - node _T_1455 = and(_T_1452, _T_1454) @[el2_ifu_mem_ctl.scala 411:74] - node _T_1456 = or(_T_1450, _T_1455) @[el2_ifu_mem_ctl.scala 410:94] - node _T_1457 = bits(bypass_index, 1, 1) @[el2_ifu_mem_ctl.scala 412:47] - node _T_1458 = and(bypass_valid_value_check, _T_1457) @[el2_ifu_mem_ctl.scala 412:33] - node _T_1459 = bits(bypass_index, 0, 0) @[el2_ifu_mem_ctl.scala 412:65] - node _T_1460 = and(_T_1458, _T_1459) @[el2_ifu_mem_ctl.scala 412:51] - node _T_1461 = eq(bypass_index_5_3_inc, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 412:132] - node _T_1462 = bits(_T_1461, 0, 0) @[el2_ifu_mem_ctl.scala 412:140] - node _T_1463 = eq(bypass_index_5_3_inc, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 412:132] - node _T_1464 = bits(_T_1463, 0, 0) @[el2_ifu_mem_ctl.scala 412:140] - node _T_1465 = eq(bypass_index_5_3_inc, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 412:132] - node _T_1466 = bits(_T_1465, 0, 0) @[el2_ifu_mem_ctl.scala 412:140] - node _T_1467 = eq(bypass_index_5_3_inc, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 412:132] - node _T_1468 = bits(_T_1467, 0, 0) @[el2_ifu_mem_ctl.scala 412:140] - node _T_1469 = eq(bypass_index_5_3_inc, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 412:132] - node _T_1470 = bits(_T_1469, 0, 0) @[el2_ifu_mem_ctl.scala 412:140] - node _T_1471 = eq(bypass_index_5_3_inc, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 412:132] - node _T_1472 = bits(_T_1471, 0, 0) @[el2_ifu_mem_ctl.scala 412:140] - node _T_1473 = eq(bypass_index_5_3_inc, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 412:132] - node _T_1474 = bits(_T_1473, 0, 0) @[el2_ifu_mem_ctl.scala 412:140] - node _T_1475 = eq(bypass_index_5_3_inc, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 412:132] - node _T_1476 = bits(_T_1475, 0, 0) @[el2_ifu_mem_ctl.scala 412:140] + node _T_1439 = bits(bypass_index, 1, 1) @[el2_ifu_mem_ctl.scala 410:71] + node _T_1440 = eq(_T_1439, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 410:58] + node _T_1441 = and(bypass_valid_value_check, _T_1440) @[el2_ifu_mem_ctl.scala 410:56] + node _T_1442 = bits(bypass_index, 0, 0) @[el2_ifu_mem_ctl.scala 410:90] + node _T_1443 = eq(_T_1442, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 410:77] + node _T_1444 = and(_T_1441, _T_1443) @[el2_ifu_mem_ctl.scala 410:75] + node _T_1445 = bits(bypass_index, 1, 1) @[el2_ifu_mem_ctl.scala 411:71] + node _T_1446 = eq(_T_1445, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 411:58] + node _T_1447 = and(bypass_valid_value_check, _T_1446) @[el2_ifu_mem_ctl.scala 411:56] + node _T_1448 = bits(bypass_index, 0, 0) @[el2_ifu_mem_ctl.scala 411:89] + node _T_1449 = and(_T_1447, _T_1448) @[el2_ifu_mem_ctl.scala 411:75] + node _T_1450 = or(_T_1444, _T_1449) @[el2_ifu_mem_ctl.scala 410:95] + node _T_1451 = bits(bypass_index, 1, 1) @[el2_ifu_mem_ctl.scala 412:70] + node _T_1452 = and(bypass_valid_value_check, _T_1451) @[el2_ifu_mem_ctl.scala 412:56] + node _T_1453 = bits(bypass_index, 0, 0) @[el2_ifu_mem_ctl.scala 412:89] + node _T_1454 = eq(_T_1453, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 412:76] + node _T_1455 = and(_T_1452, _T_1454) @[el2_ifu_mem_ctl.scala 412:74] + node _T_1456 = or(_T_1450, _T_1455) @[el2_ifu_mem_ctl.scala 411:94] + node _T_1457 = bits(bypass_index, 1, 1) @[el2_ifu_mem_ctl.scala 413:47] + node _T_1458 = and(bypass_valid_value_check, _T_1457) @[el2_ifu_mem_ctl.scala 413:33] + node _T_1459 = bits(bypass_index, 0, 0) @[el2_ifu_mem_ctl.scala 413:65] + node _T_1460 = and(_T_1458, _T_1459) @[el2_ifu_mem_ctl.scala 413:51] + node _T_1461 = eq(bypass_index_5_3_inc, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 413:132] + node _T_1462 = bits(_T_1461, 0, 0) @[el2_ifu_mem_ctl.scala 413:140] + node _T_1463 = eq(bypass_index_5_3_inc, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 413:132] + node _T_1464 = bits(_T_1463, 0, 0) @[el2_ifu_mem_ctl.scala 413:140] + node _T_1465 = eq(bypass_index_5_3_inc, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 413:132] + node _T_1466 = bits(_T_1465, 0, 0) @[el2_ifu_mem_ctl.scala 413:140] + node _T_1467 = eq(bypass_index_5_3_inc, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 413:132] + node _T_1468 = bits(_T_1467, 0, 0) @[el2_ifu_mem_ctl.scala 413:140] + node _T_1469 = eq(bypass_index_5_3_inc, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 413:132] + node _T_1470 = bits(_T_1469, 0, 0) @[el2_ifu_mem_ctl.scala 413:140] + node _T_1471 = eq(bypass_index_5_3_inc, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 413:132] + node _T_1472 = bits(_T_1471, 0, 0) @[el2_ifu_mem_ctl.scala 413:140] + node _T_1473 = eq(bypass_index_5_3_inc, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 413:132] + node _T_1474 = bits(_T_1473, 0, 0) @[el2_ifu_mem_ctl.scala 413:140] + node _T_1475 = eq(bypass_index_5_3_inc, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 413:132] + node _T_1476 = bits(_T_1475, 0, 0) @[el2_ifu_mem_ctl.scala 413:140] node _T_1477 = mux(_T_1462, ic_miss_buff_data_valid_in_0, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1478 = mux(_T_1464, ic_miss_buff_data_valid_in_1, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1479 = mux(_T_1466, ic_miss_buff_data_valid_in_2, UInt<1>("h00")) @[Mux.scala 27:72] @@ -2324,79 +2324,79 @@ circuit el2_ifu_mem_ctl : node _T_1491 = or(_T_1490, _T_1484) @[Mux.scala 27:72] wire _T_1492 : UInt<1> @[Mux.scala 27:72] _T_1492 <= _T_1491 @[Mux.scala 27:72] - node _T_1493 = and(_T_1460, _T_1492) @[el2_ifu_mem_ctl.scala 412:69] - node _T_1494 = or(_T_1456, _T_1493) @[el2_ifu_mem_ctl.scala 411:94] - node _T_1495 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 413:70] + node _T_1493 = and(_T_1460, _T_1492) @[el2_ifu_mem_ctl.scala 413:69] + node _T_1494 = or(_T_1456, _T_1493) @[el2_ifu_mem_ctl.scala 412:94] + node _T_1495 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 414:70] node _T_1496 = mux(UInt<1>("h01"), UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] - node _T_1497 = eq(_T_1495, _T_1496) @[el2_ifu_mem_ctl.scala 413:95] - node _T_1498 = and(bypass_valid_value_check, _T_1497) @[el2_ifu_mem_ctl.scala 413:56] - node bypass_data_ready_in = or(_T_1494, _T_1498) @[el2_ifu_mem_ctl.scala 412:181] + node _T_1497 = eq(_T_1495, _T_1496) @[el2_ifu_mem_ctl.scala 414:95] + node _T_1498 = and(bypass_valid_value_check, _T_1497) @[el2_ifu_mem_ctl.scala 414:56] + node bypass_data_ready_in = or(_T_1494, _T_1498) @[el2_ifu_mem_ctl.scala 413:181] wire ic_crit_wd_rdy_new_ff : UInt<1> ic_crit_wd_rdy_new_ff <= UInt<1>("h00") - node _T_1499 = and(bypass_data_ready_in, crit_wd_byp_ok_ff) @[el2_ifu_mem_ctl.scala 417:53] - node _T_1500 = and(_T_1499, uncacheable_miss_ff) @[el2_ifu_mem_ctl.scala 417:73] - node _T_1501 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 417:98] - node _T_1502 = and(_T_1500, _T_1501) @[el2_ifu_mem_ctl.scala 417:96] - node _T_1503 = eq(ifu_bp_hit_taken_q_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 417:120] - node _T_1504 = and(_T_1502, _T_1503) @[el2_ifu_mem_ctl.scala 417:118] - node _T_1505 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 418:75] - node _T_1506 = and(crit_wd_byp_ok_ff, _T_1505) @[el2_ifu_mem_ctl.scala 418:73] - node _T_1507 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 418:98] - node _T_1508 = and(_T_1506, _T_1507) @[el2_ifu_mem_ctl.scala 418:96] - node _T_1509 = eq(ifu_bp_hit_taken_q_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 418:120] - node _T_1510 = and(_T_1508, _T_1509) @[el2_ifu_mem_ctl.scala 418:118] - node _T_1511 = or(_T_1504, _T_1510) @[el2_ifu_mem_ctl.scala 417:143] - node _T_1512 = and(ic_crit_wd_rdy_new_ff, crit_wd_byp_ok_ff) @[el2_ifu_mem_ctl.scala 419:54] - node _T_1513 = eq(fetch_req_icache_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 419:76] - node _T_1514 = and(_T_1512, _T_1513) @[el2_ifu_mem_ctl.scala 419:74] - node _T_1515 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 419:98] - node _T_1516 = and(_T_1514, _T_1515) @[el2_ifu_mem_ctl.scala 419:96] - node ic_crit_wd_rdy_new_in = or(_T_1511, _T_1516) @[el2_ifu_mem_ctl.scala 418:143] - reg _T_1517 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 420:58] - _T_1517 <= ic_crit_wd_rdy_new_in @[el2_ifu_mem_ctl.scala 420:58] - ic_crit_wd_rdy_new_ff <= _T_1517 @[el2_ifu_mem_ctl.scala 420:25] - node byp_fetch_index = bits(ifu_fetch_addr_int_f, 4, 0) @[el2_ifu_mem_ctl.scala 421:45] - node _T_1518 = bits(ifu_fetch_addr_int_f, 4, 2) @[el2_ifu_mem_ctl.scala 422:51] + node _T_1499 = and(bypass_data_ready_in, crit_wd_byp_ok_ff) @[el2_ifu_mem_ctl.scala 418:53] + node _T_1500 = and(_T_1499, uncacheable_miss_ff) @[el2_ifu_mem_ctl.scala 418:73] + node _T_1501 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 418:98] + node _T_1502 = and(_T_1500, _T_1501) @[el2_ifu_mem_ctl.scala 418:96] + node _T_1503 = eq(ifu_bp_hit_taken_q_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 418:120] + node _T_1504 = and(_T_1502, _T_1503) @[el2_ifu_mem_ctl.scala 418:118] + node _T_1505 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 419:75] + node _T_1506 = and(crit_wd_byp_ok_ff, _T_1505) @[el2_ifu_mem_ctl.scala 419:73] + node _T_1507 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 419:98] + node _T_1508 = and(_T_1506, _T_1507) @[el2_ifu_mem_ctl.scala 419:96] + node _T_1509 = eq(ifu_bp_hit_taken_q_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 419:120] + node _T_1510 = and(_T_1508, _T_1509) @[el2_ifu_mem_ctl.scala 419:118] + node _T_1511 = or(_T_1504, _T_1510) @[el2_ifu_mem_ctl.scala 418:143] + node _T_1512 = and(ic_crit_wd_rdy_new_ff, crit_wd_byp_ok_ff) @[el2_ifu_mem_ctl.scala 420:54] + node _T_1513 = eq(fetch_req_icache_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 420:76] + node _T_1514 = and(_T_1512, _T_1513) @[el2_ifu_mem_ctl.scala 420:74] + node _T_1515 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 420:98] + node _T_1516 = and(_T_1514, _T_1515) @[el2_ifu_mem_ctl.scala 420:96] + node ic_crit_wd_rdy_new_in = or(_T_1511, _T_1516) @[el2_ifu_mem_ctl.scala 419:143] + reg _T_1517 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 421:58] + _T_1517 <= ic_crit_wd_rdy_new_in @[el2_ifu_mem_ctl.scala 421:58] + ic_crit_wd_rdy_new_ff <= _T_1517 @[el2_ifu_mem_ctl.scala 421:25] + node byp_fetch_index = bits(ifu_fetch_addr_int_f, 4, 0) @[el2_ifu_mem_ctl.scala 422:45] + node _T_1518 = bits(ifu_fetch_addr_int_f, 4, 2) @[el2_ifu_mem_ctl.scala 423:51] node byp_fetch_index_0 = cat(_T_1518, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_1519 = bits(ifu_fetch_addr_int_f, 4, 2) @[el2_ifu_mem_ctl.scala 423:51] + node _T_1519 = bits(ifu_fetch_addr_int_f, 4, 2) @[el2_ifu_mem_ctl.scala 424:51] node byp_fetch_index_1 = cat(_T_1519, UInt<1>("h01")) @[Cat.scala 29:58] - node _T_1520 = bits(ifu_fetch_addr_int_f, 4, 2) @[el2_ifu_mem_ctl.scala 424:49] - node _T_1521 = add(_T_1520, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 424:75] - node byp_fetch_index_inc = tail(_T_1521, 1) @[el2_ifu_mem_ctl.scala 424:75] + node _T_1520 = bits(ifu_fetch_addr_int_f, 4, 2) @[el2_ifu_mem_ctl.scala 425:49] + node _T_1521 = add(_T_1520, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 425:75] + node byp_fetch_index_inc = tail(_T_1521, 1) @[el2_ifu_mem_ctl.scala 425:75] node byp_fetch_index_inc_0 = cat(byp_fetch_index_inc, UInt<1>("h00")) @[Cat.scala 29:58] node byp_fetch_index_inc_1 = cat(byp_fetch_index_inc, UInt<1>("h01")) @[Cat.scala 29:58] - node _T_1522 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 427:93] - node _T_1523 = eq(_T_1522, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 427:118] - node _T_1524 = bits(_T_1523, 0, 0) @[el2_ifu_mem_ctl.scala 427:126] - node _T_1525 = bits(ic_miss_buff_data_error, 0, 0) @[el2_ifu_mem_ctl.scala 427:157] - node _T_1526 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 427:93] - node _T_1527 = eq(_T_1526, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 427:118] - node _T_1528 = bits(_T_1527, 0, 0) @[el2_ifu_mem_ctl.scala 427:126] - node _T_1529 = bits(ic_miss_buff_data_error, 1, 1) @[el2_ifu_mem_ctl.scala 427:157] - node _T_1530 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 427:93] - node _T_1531 = eq(_T_1530, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 427:118] - node _T_1532 = bits(_T_1531, 0, 0) @[el2_ifu_mem_ctl.scala 427:126] - node _T_1533 = bits(ic_miss_buff_data_error, 2, 2) @[el2_ifu_mem_ctl.scala 427:157] - node _T_1534 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 427:93] - node _T_1535 = eq(_T_1534, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 427:118] - node _T_1536 = bits(_T_1535, 0, 0) @[el2_ifu_mem_ctl.scala 427:126] - node _T_1537 = bits(ic_miss_buff_data_error, 3, 3) @[el2_ifu_mem_ctl.scala 427:157] - node _T_1538 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 427:93] - node _T_1539 = eq(_T_1538, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 427:118] - node _T_1540 = bits(_T_1539, 0, 0) @[el2_ifu_mem_ctl.scala 427:126] - node _T_1541 = bits(ic_miss_buff_data_error, 4, 4) @[el2_ifu_mem_ctl.scala 427:157] - node _T_1542 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 427:93] - node _T_1543 = eq(_T_1542, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 427:118] - node _T_1544 = bits(_T_1543, 0, 0) @[el2_ifu_mem_ctl.scala 427:126] - node _T_1545 = bits(ic_miss_buff_data_error, 5, 5) @[el2_ifu_mem_ctl.scala 427:157] - node _T_1546 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 427:93] - node _T_1547 = eq(_T_1546, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 427:118] - node _T_1548 = bits(_T_1547, 0, 0) @[el2_ifu_mem_ctl.scala 427:126] - node _T_1549 = bits(ic_miss_buff_data_error, 6, 6) @[el2_ifu_mem_ctl.scala 427:157] - node _T_1550 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 427:93] - node _T_1551 = eq(_T_1550, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 427:118] - node _T_1552 = bits(_T_1551, 0, 0) @[el2_ifu_mem_ctl.scala 427:126] - node _T_1553 = bits(ic_miss_buff_data_error, 7, 7) @[el2_ifu_mem_ctl.scala 427:157] + node _T_1522 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 428:93] + node _T_1523 = eq(_T_1522, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 428:118] + node _T_1524 = bits(_T_1523, 0, 0) @[el2_ifu_mem_ctl.scala 428:126] + node _T_1525 = bits(ic_miss_buff_data_error, 0, 0) @[el2_ifu_mem_ctl.scala 428:157] + node _T_1526 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 428:93] + node _T_1527 = eq(_T_1526, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 428:118] + node _T_1528 = bits(_T_1527, 0, 0) @[el2_ifu_mem_ctl.scala 428:126] + node _T_1529 = bits(ic_miss_buff_data_error, 1, 1) @[el2_ifu_mem_ctl.scala 428:157] + node _T_1530 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 428:93] + node _T_1531 = eq(_T_1530, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 428:118] + node _T_1532 = bits(_T_1531, 0, 0) @[el2_ifu_mem_ctl.scala 428:126] + node _T_1533 = bits(ic_miss_buff_data_error, 2, 2) @[el2_ifu_mem_ctl.scala 428:157] + node _T_1534 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 428:93] + node _T_1535 = eq(_T_1534, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 428:118] + node _T_1536 = bits(_T_1535, 0, 0) @[el2_ifu_mem_ctl.scala 428:126] + node _T_1537 = bits(ic_miss_buff_data_error, 3, 3) @[el2_ifu_mem_ctl.scala 428:157] + node _T_1538 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 428:93] + node _T_1539 = eq(_T_1538, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 428:118] + node _T_1540 = bits(_T_1539, 0, 0) @[el2_ifu_mem_ctl.scala 428:126] + node _T_1541 = bits(ic_miss_buff_data_error, 4, 4) @[el2_ifu_mem_ctl.scala 428:157] + node _T_1542 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 428:93] + node _T_1543 = eq(_T_1542, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 428:118] + node _T_1544 = bits(_T_1543, 0, 0) @[el2_ifu_mem_ctl.scala 428:126] + node _T_1545 = bits(ic_miss_buff_data_error, 5, 5) @[el2_ifu_mem_ctl.scala 428:157] + node _T_1546 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 428:93] + node _T_1547 = eq(_T_1546, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 428:118] + node _T_1548 = bits(_T_1547, 0, 0) @[el2_ifu_mem_ctl.scala 428:126] + node _T_1549 = bits(ic_miss_buff_data_error, 6, 6) @[el2_ifu_mem_ctl.scala 428:157] + node _T_1550 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 428:93] + node _T_1551 = eq(_T_1550, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 428:118] + node _T_1552 = bits(_T_1551, 0, 0) @[el2_ifu_mem_ctl.scala 428:126] + node _T_1553 = bits(ic_miss_buff_data_error, 7, 7) @[el2_ifu_mem_ctl.scala 428:157] node _T_1554 = mux(_T_1524, _T_1525, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1555 = mux(_T_1528, _T_1529, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1556 = mux(_T_1532, _T_1533, UInt<1>("h00")) @[Mux.scala 27:72] @@ -2414,30 +2414,30 @@ circuit el2_ifu_mem_ctl : node _T_1568 = or(_T_1567, _T_1561) @[Mux.scala 27:72] wire ic_miss_buff_data_error_bypass : UInt<1> @[Mux.scala 27:72] ic_miss_buff_data_error_bypass <= _T_1568 @[Mux.scala 27:72] - node _T_1569 = eq(byp_fetch_index_inc, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 428:104] - node _T_1570 = bits(_T_1569, 0, 0) @[el2_ifu_mem_ctl.scala 428:112] - node _T_1571 = bits(ic_miss_buff_data_error, 0, 0) @[el2_ifu_mem_ctl.scala 428:143] - node _T_1572 = eq(byp_fetch_index_inc, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 428:104] - node _T_1573 = bits(_T_1572, 0, 0) @[el2_ifu_mem_ctl.scala 428:112] - node _T_1574 = bits(ic_miss_buff_data_error, 1, 1) @[el2_ifu_mem_ctl.scala 428:143] - node _T_1575 = eq(byp_fetch_index_inc, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 428:104] - node _T_1576 = bits(_T_1575, 0, 0) @[el2_ifu_mem_ctl.scala 428:112] - node _T_1577 = bits(ic_miss_buff_data_error, 2, 2) @[el2_ifu_mem_ctl.scala 428:143] - node _T_1578 = eq(byp_fetch_index_inc, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 428:104] - node _T_1579 = bits(_T_1578, 0, 0) @[el2_ifu_mem_ctl.scala 428:112] - node _T_1580 = bits(ic_miss_buff_data_error, 3, 3) @[el2_ifu_mem_ctl.scala 428:143] - node _T_1581 = eq(byp_fetch_index_inc, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 428:104] - node _T_1582 = bits(_T_1581, 0, 0) @[el2_ifu_mem_ctl.scala 428:112] - node _T_1583 = bits(ic_miss_buff_data_error, 4, 4) @[el2_ifu_mem_ctl.scala 428:143] - node _T_1584 = eq(byp_fetch_index_inc, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 428:104] - node _T_1585 = bits(_T_1584, 0, 0) @[el2_ifu_mem_ctl.scala 428:112] - node _T_1586 = bits(ic_miss_buff_data_error, 5, 5) @[el2_ifu_mem_ctl.scala 428:143] - node _T_1587 = eq(byp_fetch_index_inc, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 428:104] - node _T_1588 = bits(_T_1587, 0, 0) @[el2_ifu_mem_ctl.scala 428:112] - node _T_1589 = bits(ic_miss_buff_data_error, 6, 6) @[el2_ifu_mem_ctl.scala 428:143] - node _T_1590 = eq(byp_fetch_index_inc, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 428:104] - node _T_1591 = bits(_T_1590, 0, 0) @[el2_ifu_mem_ctl.scala 428:112] - node _T_1592 = bits(ic_miss_buff_data_error, 7, 7) @[el2_ifu_mem_ctl.scala 428:143] + node _T_1569 = eq(byp_fetch_index_inc, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 429:104] + node _T_1570 = bits(_T_1569, 0, 0) @[el2_ifu_mem_ctl.scala 429:112] + node _T_1571 = bits(ic_miss_buff_data_error, 0, 0) @[el2_ifu_mem_ctl.scala 429:143] + node _T_1572 = eq(byp_fetch_index_inc, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 429:104] + node _T_1573 = bits(_T_1572, 0, 0) @[el2_ifu_mem_ctl.scala 429:112] + node _T_1574 = bits(ic_miss_buff_data_error, 1, 1) @[el2_ifu_mem_ctl.scala 429:143] + node _T_1575 = eq(byp_fetch_index_inc, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 429:104] + node _T_1576 = bits(_T_1575, 0, 0) @[el2_ifu_mem_ctl.scala 429:112] + node _T_1577 = bits(ic_miss_buff_data_error, 2, 2) @[el2_ifu_mem_ctl.scala 429:143] + node _T_1578 = eq(byp_fetch_index_inc, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 429:104] + node _T_1579 = bits(_T_1578, 0, 0) @[el2_ifu_mem_ctl.scala 429:112] + node _T_1580 = bits(ic_miss_buff_data_error, 3, 3) @[el2_ifu_mem_ctl.scala 429:143] + node _T_1581 = eq(byp_fetch_index_inc, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 429:104] + node _T_1582 = bits(_T_1581, 0, 0) @[el2_ifu_mem_ctl.scala 429:112] + node _T_1583 = bits(ic_miss_buff_data_error, 4, 4) @[el2_ifu_mem_ctl.scala 429:143] + node _T_1584 = eq(byp_fetch_index_inc, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 429:104] + node _T_1585 = bits(_T_1584, 0, 0) @[el2_ifu_mem_ctl.scala 429:112] + node _T_1586 = bits(ic_miss_buff_data_error, 5, 5) @[el2_ifu_mem_ctl.scala 429:143] + node _T_1587 = eq(byp_fetch_index_inc, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 429:104] + node _T_1588 = bits(_T_1587, 0, 0) @[el2_ifu_mem_ctl.scala 429:112] + node _T_1589 = bits(ic_miss_buff_data_error, 6, 6) @[el2_ifu_mem_ctl.scala 429:143] + node _T_1590 = eq(byp_fetch_index_inc, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 429:104] + node _T_1591 = bits(_T_1590, 0, 0) @[el2_ifu_mem_ctl.scala 429:112] + node _T_1592 = bits(ic_miss_buff_data_error, 7, 7) @[el2_ifu_mem_ctl.scala 429:143] node _T_1593 = mux(_T_1570, _T_1571, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1594 = mux(_T_1573, _T_1574, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1595 = mux(_T_1576, _T_1577, UInt<1>("h00")) @[Mux.scala 27:72] @@ -2455,67 +2455,67 @@ circuit el2_ifu_mem_ctl : node _T_1607 = or(_T_1606, _T_1600) @[Mux.scala 27:72] wire ic_miss_buff_data_error_bypass_inc : UInt<1> @[Mux.scala 27:72] ic_miss_buff_data_error_bypass_inc <= _T_1607 @[Mux.scala 27:72] - node _T_1608 = bits(ifu_fetch_addr_int_f, 1, 1) @[el2_ifu_mem_ctl.scala 431:28] - node _T_1609 = bits(ifu_fetch_addr_int_f, 0, 0) @[el2_ifu_mem_ctl.scala 431:52] - node _T_1610 = and(_T_1608, _T_1609) @[el2_ifu_mem_ctl.scala 431:31] - when _T_1610 : @[el2_ifu_mem_ctl.scala 431:56] - ifu_byp_data_err_new <= ic_miss_buff_data_error_bypass @[el2_ifu_mem_ctl.scala 432:26] - skip @[el2_ifu_mem_ctl.scala 431:56] - else : @[el2_ifu_mem_ctl.scala 433:5] - node _T_1611 = or(ic_miss_buff_data_error_bypass, ic_miss_buff_data_error_bypass_inc) @[el2_ifu_mem_ctl.scala 433:70] - ifu_byp_data_err_new <= _T_1611 @[el2_ifu_mem_ctl.scala 433:36] - skip @[el2_ifu_mem_ctl.scala 433:5] - node _T_1612 = bits(ifu_fetch_addr_int_f, 0, 0) @[el2_ifu_mem_ctl.scala 435:59] - node _T_1613 = bits(_T_1612, 0, 0) @[el2_ifu_mem_ctl.scala 435:63] - node _T_1614 = eq(_T_1613, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 435:38] - node _T_1615 = eq(byp_fetch_index_inc_0, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 436:73] - node _T_1616 = bits(_T_1615, 0, 0) @[el2_ifu_mem_ctl.scala 436:81] - node _T_1617 = bits(ic_miss_buff_data[0], 15, 0) @[el2_ifu_mem_ctl.scala 436:109] - node _T_1618 = eq(byp_fetch_index_inc_0, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 436:73] - node _T_1619 = bits(_T_1618, 0, 0) @[el2_ifu_mem_ctl.scala 436:81] - node _T_1620 = bits(ic_miss_buff_data[1], 15, 0) @[el2_ifu_mem_ctl.scala 436:109] - node _T_1621 = eq(byp_fetch_index_inc_0, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 436:73] - node _T_1622 = bits(_T_1621, 0, 0) @[el2_ifu_mem_ctl.scala 436:81] - node _T_1623 = bits(ic_miss_buff_data[2], 15, 0) @[el2_ifu_mem_ctl.scala 436:109] - node _T_1624 = eq(byp_fetch_index_inc_0, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 436:73] - node _T_1625 = bits(_T_1624, 0, 0) @[el2_ifu_mem_ctl.scala 436:81] - node _T_1626 = bits(ic_miss_buff_data[3], 15, 0) @[el2_ifu_mem_ctl.scala 436:109] - node _T_1627 = eq(byp_fetch_index_inc_0, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 436:73] - node _T_1628 = bits(_T_1627, 0, 0) @[el2_ifu_mem_ctl.scala 436:81] - node _T_1629 = bits(ic_miss_buff_data[4], 15, 0) @[el2_ifu_mem_ctl.scala 436:109] - node _T_1630 = eq(byp_fetch_index_inc_0, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 436:73] - node _T_1631 = bits(_T_1630, 0, 0) @[el2_ifu_mem_ctl.scala 436:81] - node _T_1632 = bits(ic_miss_buff_data[5], 15, 0) @[el2_ifu_mem_ctl.scala 436:109] - node _T_1633 = eq(byp_fetch_index_inc_0, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 436:73] - node _T_1634 = bits(_T_1633, 0, 0) @[el2_ifu_mem_ctl.scala 436:81] - node _T_1635 = bits(ic_miss_buff_data[6], 15, 0) @[el2_ifu_mem_ctl.scala 436:109] - node _T_1636 = eq(byp_fetch_index_inc_0, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 436:73] - node _T_1637 = bits(_T_1636, 0, 0) @[el2_ifu_mem_ctl.scala 436:81] - node _T_1638 = bits(ic_miss_buff_data[7], 15, 0) @[el2_ifu_mem_ctl.scala 436:109] - node _T_1639 = eq(byp_fetch_index_inc_0, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 436:73] - node _T_1640 = bits(_T_1639, 0, 0) @[el2_ifu_mem_ctl.scala 436:81] - node _T_1641 = bits(ic_miss_buff_data[8], 15, 0) @[el2_ifu_mem_ctl.scala 436:109] - node _T_1642 = eq(byp_fetch_index_inc_0, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 436:73] - node _T_1643 = bits(_T_1642, 0, 0) @[el2_ifu_mem_ctl.scala 436:81] - node _T_1644 = bits(ic_miss_buff_data[9], 15, 0) @[el2_ifu_mem_ctl.scala 436:109] - node _T_1645 = eq(byp_fetch_index_inc_0, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 436:73] - node _T_1646 = bits(_T_1645, 0, 0) @[el2_ifu_mem_ctl.scala 436:81] - node _T_1647 = bits(ic_miss_buff_data[10], 15, 0) @[el2_ifu_mem_ctl.scala 436:109] - node _T_1648 = eq(byp_fetch_index_inc_0, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 436:73] - node _T_1649 = bits(_T_1648, 0, 0) @[el2_ifu_mem_ctl.scala 436:81] - node _T_1650 = bits(ic_miss_buff_data[11], 15, 0) @[el2_ifu_mem_ctl.scala 436:109] - node _T_1651 = eq(byp_fetch_index_inc_0, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 436:73] - node _T_1652 = bits(_T_1651, 0, 0) @[el2_ifu_mem_ctl.scala 436:81] - node _T_1653 = bits(ic_miss_buff_data[12], 15, 0) @[el2_ifu_mem_ctl.scala 436:109] - node _T_1654 = eq(byp_fetch_index_inc_0, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 436:73] - node _T_1655 = bits(_T_1654, 0, 0) @[el2_ifu_mem_ctl.scala 436:81] - node _T_1656 = bits(ic_miss_buff_data[13], 15, 0) @[el2_ifu_mem_ctl.scala 436:109] - node _T_1657 = eq(byp_fetch_index_inc_0, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 436:73] - node _T_1658 = bits(_T_1657, 0, 0) @[el2_ifu_mem_ctl.scala 436:81] - node _T_1659 = bits(ic_miss_buff_data[14], 15, 0) @[el2_ifu_mem_ctl.scala 436:109] - node _T_1660 = eq(byp_fetch_index_inc_0, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 436:73] - node _T_1661 = bits(_T_1660, 0, 0) @[el2_ifu_mem_ctl.scala 436:81] - node _T_1662 = bits(ic_miss_buff_data[15], 15, 0) @[el2_ifu_mem_ctl.scala 436:109] + node _T_1608 = bits(ifu_fetch_addr_int_f, 1, 1) @[el2_ifu_mem_ctl.scala 432:28] + node _T_1609 = bits(ifu_fetch_addr_int_f, 0, 0) @[el2_ifu_mem_ctl.scala 432:52] + node _T_1610 = and(_T_1608, _T_1609) @[el2_ifu_mem_ctl.scala 432:31] + when _T_1610 : @[el2_ifu_mem_ctl.scala 432:56] + ifu_byp_data_err_new <= ic_miss_buff_data_error_bypass @[el2_ifu_mem_ctl.scala 433:26] + skip @[el2_ifu_mem_ctl.scala 432:56] + else : @[el2_ifu_mem_ctl.scala 434:5] + node _T_1611 = or(ic_miss_buff_data_error_bypass, ic_miss_buff_data_error_bypass_inc) @[el2_ifu_mem_ctl.scala 434:70] + ifu_byp_data_err_new <= _T_1611 @[el2_ifu_mem_ctl.scala 434:36] + skip @[el2_ifu_mem_ctl.scala 434:5] + node _T_1612 = bits(ifu_fetch_addr_int_f, 0, 0) @[el2_ifu_mem_ctl.scala 436:59] + node _T_1613 = bits(_T_1612, 0, 0) @[el2_ifu_mem_ctl.scala 436:63] + node _T_1614 = eq(_T_1613, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 436:38] + node _T_1615 = eq(byp_fetch_index_inc_0, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 437:73] + node _T_1616 = bits(_T_1615, 0, 0) @[el2_ifu_mem_ctl.scala 437:81] + node _T_1617 = bits(ic_miss_buff_data[0], 15, 0) @[el2_ifu_mem_ctl.scala 437:109] + node _T_1618 = eq(byp_fetch_index_inc_0, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 437:73] + node _T_1619 = bits(_T_1618, 0, 0) @[el2_ifu_mem_ctl.scala 437:81] + node _T_1620 = bits(ic_miss_buff_data[1], 15, 0) @[el2_ifu_mem_ctl.scala 437:109] + node _T_1621 = eq(byp_fetch_index_inc_0, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 437:73] + node _T_1622 = bits(_T_1621, 0, 0) @[el2_ifu_mem_ctl.scala 437:81] + node _T_1623 = bits(ic_miss_buff_data[2], 15, 0) @[el2_ifu_mem_ctl.scala 437:109] + node _T_1624 = eq(byp_fetch_index_inc_0, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 437:73] + node _T_1625 = bits(_T_1624, 0, 0) @[el2_ifu_mem_ctl.scala 437:81] + node _T_1626 = bits(ic_miss_buff_data[3], 15, 0) @[el2_ifu_mem_ctl.scala 437:109] + node _T_1627 = eq(byp_fetch_index_inc_0, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 437:73] + node _T_1628 = bits(_T_1627, 0, 0) @[el2_ifu_mem_ctl.scala 437:81] + node _T_1629 = bits(ic_miss_buff_data[4], 15, 0) @[el2_ifu_mem_ctl.scala 437:109] + node _T_1630 = eq(byp_fetch_index_inc_0, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 437:73] + node _T_1631 = bits(_T_1630, 0, 0) @[el2_ifu_mem_ctl.scala 437:81] + node _T_1632 = bits(ic_miss_buff_data[5], 15, 0) @[el2_ifu_mem_ctl.scala 437:109] + node _T_1633 = eq(byp_fetch_index_inc_0, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 437:73] + node _T_1634 = bits(_T_1633, 0, 0) @[el2_ifu_mem_ctl.scala 437:81] + node _T_1635 = bits(ic_miss_buff_data[6], 15, 0) @[el2_ifu_mem_ctl.scala 437:109] + node _T_1636 = eq(byp_fetch_index_inc_0, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 437:73] + node _T_1637 = bits(_T_1636, 0, 0) @[el2_ifu_mem_ctl.scala 437:81] + node _T_1638 = bits(ic_miss_buff_data[7], 15, 0) @[el2_ifu_mem_ctl.scala 437:109] + node _T_1639 = eq(byp_fetch_index_inc_0, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 437:73] + node _T_1640 = bits(_T_1639, 0, 0) @[el2_ifu_mem_ctl.scala 437:81] + node _T_1641 = bits(ic_miss_buff_data[8], 15, 0) @[el2_ifu_mem_ctl.scala 437:109] + node _T_1642 = eq(byp_fetch_index_inc_0, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 437:73] + node _T_1643 = bits(_T_1642, 0, 0) @[el2_ifu_mem_ctl.scala 437:81] + node _T_1644 = bits(ic_miss_buff_data[9], 15, 0) @[el2_ifu_mem_ctl.scala 437:109] + node _T_1645 = eq(byp_fetch_index_inc_0, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 437:73] + node _T_1646 = bits(_T_1645, 0, 0) @[el2_ifu_mem_ctl.scala 437:81] + node _T_1647 = bits(ic_miss_buff_data[10], 15, 0) @[el2_ifu_mem_ctl.scala 437:109] + node _T_1648 = eq(byp_fetch_index_inc_0, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 437:73] + node _T_1649 = bits(_T_1648, 0, 0) @[el2_ifu_mem_ctl.scala 437:81] + node _T_1650 = bits(ic_miss_buff_data[11], 15, 0) @[el2_ifu_mem_ctl.scala 437:109] + node _T_1651 = eq(byp_fetch_index_inc_0, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 437:73] + node _T_1652 = bits(_T_1651, 0, 0) @[el2_ifu_mem_ctl.scala 437:81] + node _T_1653 = bits(ic_miss_buff_data[12], 15, 0) @[el2_ifu_mem_ctl.scala 437:109] + node _T_1654 = eq(byp_fetch_index_inc_0, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 437:73] + node _T_1655 = bits(_T_1654, 0, 0) @[el2_ifu_mem_ctl.scala 437:81] + node _T_1656 = bits(ic_miss_buff_data[13], 15, 0) @[el2_ifu_mem_ctl.scala 437:109] + node _T_1657 = eq(byp_fetch_index_inc_0, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 437:73] + node _T_1658 = bits(_T_1657, 0, 0) @[el2_ifu_mem_ctl.scala 437:81] + node _T_1659 = bits(ic_miss_buff_data[14], 15, 0) @[el2_ifu_mem_ctl.scala 437:109] + node _T_1660 = eq(byp_fetch_index_inc_0, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 437:73] + node _T_1661 = bits(_T_1660, 0, 0) @[el2_ifu_mem_ctl.scala 437:81] + node _T_1662 = bits(ic_miss_buff_data[15], 15, 0) @[el2_ifu_mem_ctl.scala 437:109] node _T_1663 = mux(_T_1616, _T_1617, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1664 = mux(_T_1619, _T_1620, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1665 = mux(_T_1622, _T_1623, UInt<1>("h00")) @[Mux.scala 27:72] @@ -2549,54 +2549,54 @@ circuit el2_ifu_mem_ctl : node _T_1693 = or(_T_1692, _T_1678) @[Mux.scala 27:72] wire _T_1694 : UInt<16> @[Mux.scala 27:72] _T_1694 <= _T_1693 @[Mux.scala 27:72] - node _T_1695 = eq(byp_fetch_index_1, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 436:179] - node _T_1696 = bits(_T_1695, 0, 0) @[el2_ifu_mem_ctl.scala 436:187] - node _T_1697 = bits(ic_miss_buff_data[0], 31, 0) @[el2_ifu_mem_ctl.scala 436:215] - node _T_1698 = eq(byp_fetch_index_1, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 436:179] - node _T_1699 = bits(_T_1698, 0, 0) @[el2_ifu_mem_ctl.scala 436:187] - node _T_1700 = bits(ic_miss_buff_data[1], 31, 0) @[el2_ifu_mem_ctl.scala 436:215] - node _T_1701 = eq(byp_fetch_index_1, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 436:179] - node _T_1702 = bits(_T_1701, 0, 0) @[el2_ifu_mem_ctl.scala 436:187] - node _T_1703 = bits(ic_miss_buff_data[2], 31, 0) @[el2_ifu_mem_ctl.scala 436:215] - node _T_1704 = eq(byp_fetch_index_1, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 436:179] - node _T_1705 = bits(_T_1704, 0, 0) @[el2_ifu_mem_ctl.scala 436:187] - node _T_1706 = bits(ic_miss_buff_data[3], 31, 0) @[el2_ifu_mem_ctl.scala 436:215] - node _T_1707 = eq(byp_fetch_index_1, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 436:179] - node _T_1708 = bits(_T_1707, 0, 0) @[el2_ifu_mem_ctl.scala 436:187] - node _T_1709 = bits(ic_miss_buff_data[4], 31, 0) @[el2_ifu_mem_ctl.scala 436:215] - node _T_1710 = eq(byp_fetch_index_1, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 436:179] - node _T_1711 = bits(_T_1710, 0, 0) @[el2_ifu_mem_ctl.scala 436:187] - node _T_1712 = bits(ic_miss_buff_data[5], 31, 0) @[el2_ifu_mem_ctl.scala 436:215] - node _T_1713 = eq(byp_fetch_index_1, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 436:179] - node _T_1714 = bits(_T_1713, 0, 0) @[el2_ifu_mem_ctl.scala 436:187] - node _T_1715 = bits(ic_miss_buff_data[6], 31, 0) @[el2_ifu_mem_ctl.scala 436:215] - node _T_1716 = eq(byp_fetch_index_1, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 436:179] - node _T_1717 = bits(_T_1716, 0, 0) @[el2_ifu_mem_ctl.scala 436:187] - node _T_1718 = bits(ic_miss_buff_data[7], 31, 0) @[el2_ifu_mem_ctl.scala 436:215] - node _T_1719 = eq(byp_fetch_index_1, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 436:179] - node _T_1720 = bits(_T_1719, 0, 0) @[el2_ifu_mem_ctl.scala 436:187] - node _T_1721 = bits(ic_miss_buff_data[8], 31, 0) @[el2_ifu_mem_ctl.scala 436:215] - node _T_1722 = eq(byp_fetch_index_1, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 436:179] - node _T_1723 = bits(_T_1722, 0, 0) @[el2_ifu_mem_ctl.scala 436:187] - node _T_1724 = bits(ic_miss_buff_data[9], 31, 0) @[el2_ifu_mem_ctl.scala 436:215] - node _T_1725 = eq(byp_fetch_index_1, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 436:179] - node _T_1726 = bits(_T_1725, 0, 0) @[el2_ifu_mem_ctl.scala 436:187] - node _T_1727 = bits(ic_miss_buff_data[10], 31, 0) @[el2_ifu_mem_ctl.scala 436:215] - node _T_1728 = eq(byp_fetch_index_1, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 436:179] - node _T_1729 = bits(_T_1728, 0, 0) @[el2_ifu_mem_ctl.scala 436:187] - node _T_1730 = bits(ic_miss_buff_data[11], 31, 0) @[el2_ifu_mem_ctl.scala 436:215] - node _T_1731 = eq(byp_fetch_index_1, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 436:179] - node _T_1732 = bits(_T_1731, 0, 0) @[el2_ifu_mem_ctl.scala 436:187] - node _T_1733 = bits(ic_miss_buff_data[12], 31, 0) @[el2_ifu_mem_ctl.scala 436:215] - node _T_1734 = eq(byp_fetch_index_1, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 436:179] - node _T_1735 = bits(_T_1734, 0, 0) @[el2_ifu_mem_ctl.scala 436:187] - node _T_1736 = bits(ic_miss_buff_data[13], 31, 0) @[el2_ifu_mem_ctl.scala 436:215] - node _T_1737 = eq(byp_fetch_index_1, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 436:179] - node _T_1738 = bits(_T_1737, 0, 0) @[el2_ifu_mem_ctl.scala 436:187] - node _T_1739 = bits(ic_miss_buff_data[14], 31, 0) @[el2_ifu_mem_ctl.scala 436:215] - node _T_1740 = eq(byp_fetch_index_1, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 436:179] - node _T_1741 = bits(_T_1740, 0, 0) @[el2_ifu_mem_ctl.scala 436:187] - node _T_1742 = bits(ic_miss_buff_data[15], 31, 0) @[el2_ifu_mem_ctl.scala 436:215] + node _T_1695 = eq(byp_fetch_index_1, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 437:179] + node _T_1696 = bits(_T_1695, 0, 0) @[el2_ifu_mem_ctl.scala 437:187] + node _T_1697 = bits(ic_miss_buff_data[0], 31, 0) @[el2_ifu_mem_ctl.scala 437:215] + node _T_1698 = eq(byp_fetch_index_1, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 437:179] + node _T_1699 = bits(_T_1698, 0, 0) @[el2_ifu_mem_ctl.scala 437:187] + node _T_1700 = bits(ic_miss_buff_data[1], 31, 0) @[el2_ifu_mem_ctl.scala 437:215] + node _T_1701 = eq(byp_fetch_index_1, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 437:179] + node _T_1702 = bits(_T_1701, 0, 0) @[el2_ifu_mem_ctl.scala 437:187] + node _T_1703 = bits(ic_miss_buff_data[2], 31, 0) @[el2_ifu_mem_ctl.scala 437:215] + node _T_1704 = eq(byp_fetch_index_1, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 437:179] + node _T_1705 = bits(_T_1704, 0, 0) @[el2_ifu_mem_ctl.scala 437:187] + node _T_1706 = bits(ic_miss_buff_data[3], 31, 0) @[el2_ifu_mem_ctl.scala 437:215] + node _T_1707 = eq(byp_fetch_index_1, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 437:179] + node _T_1708 = bits(_T_1707, 0, 0) @[el2_ifu_mem_ctl.scala 437:187] + node _T_1709 = bits(ic_miss_buff_data[4], 31, 0) @[el2_ifu_mem_ctl.scala 437:215] + node _T_1710 = eq(byp_fetch_index_1, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 437:179] + node _T_1711 = bits(_T_1710, 0, 0) @[el2_ifu_mem_ctl.scala 437:187] + node _T_1712 = bits(ic_miss_buff_data[5], 31, 0) @[el2_ifu_mem_ctl.scala 437:215] + node _T_1713 = eq(byp_fetch_index_1, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 437:179] + node _T_1714 = bits(_T_1713, 0, 0) @[el2_ifu_mem_ctl.scala 437:187] + node _T_1715 = bits(ic_miss_buff_data[6], 31, 0) @[el2_ifu_mem_ctl.scala 437:215] + node _T_1716 = eq(byp_fetch_index_1, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 437:179] + node _T_1717 = bits(_T_1716, 0, 0) @[el2_ifu_mem_ctl.scala 437:187] + node _T_1718 = bits(ic_miss_buff_data[7], 31, 0) @[el2_ifu_mem_ctl.scala 437:215] + node _T_1719 = eq(byp_fetch_index_1, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 437:179] + node _T_1720 = bits(_T_1719, 0, 0) @[el2_ifu_mem_ctl.scala 437:187] + node _T_1721 = bits(ic_miss_buff_data[8], 31, 0) @[el2_ifu_mem_ctl.scala 437:215] + node _T_1722 = eq(byp_fetch_index_1, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 437:179] + node _T_1723 = bits(_T_1722, 0, 0) @[el2_ifu_mem_ctl.scala 437:187] + node _T_1724 = bits(ic_miss_buff_data[9], 31, 0) @[el2_ifu_mem_ctl.scala 437:215] + node _T_1725 = eq(byp_fetch_index_1, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 437:179] + node _T_1726 = bits(_T_1725, 0, 0) @[el2_ifu_mem_ctl.scala 437:187] + node _T_1727 = bits(ic_miss_buff_data[10], 31, 0) @[el2_ifu_mem_ctl.scala 437:215] + node _T_1728 = eq(byp_fetch_index_1, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 437:179] + node _T_1729 = bits(_T_1728, 0, 0) @[el2_ifu_mem_ctl.scala 437:187] + node _T_1730 = bits(ic_miss_buff_data[11], 31, 0) @[el2_ifu_mem_ctl.scala 437:215] + node _T_1731 = eq(byp_fetch_index_1, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 437:179] + node _T_1732 = bits(_T_1731, 0, 0) @[el2_ifu_mem_ctl.scala 437:187] + node _T_1733 = bits(ic_miss_buff_data[12], 31, 0) @[el2_ifu_mem_ctl.scala 437:215] + node _T_1734 = eq(byp_fetch_index_1, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 437:179] + node _T_1735 = bits(_T_1734, 0, 0) @[el2_ifu_mem_ctl.scala 437:187] + node _T_1736 = bits(ic_miss_buff_data[13], 31, 0) @[el2_ifu_mem_ctl.scala 437:215] + node _T_1737 = eq(byp_fetch_index_1, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 437:179] + node _T_1738 = bits(_T_1737, 0, 0) @[el2_ifu_mem_ctl.scala 437:187] + node _T_1739 = bits(ic_miss_buff_data[14], 31, 0) @[el2_ifu_mem_ctl.scala 437:215] + node _T_1740 = eq(byp_fetch_index_1, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 437:179] + node _T_1741 = bits(_T_1740, 0, 0) @[el2_ifu_mem_ctl.scala 437:187] + node _T_1742 = bits(ic_miss_buff_data[15], 31, 0) @[el2_ifu_mem_ctl.scala 437:215] node _T_1743 = mux(_T_1696, _T_1697, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1744 = mux(_T_1699, _T_1700, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1745 = mux(_T_1702, _T_1703, UInt<1>("h00")) @[Mux.scala 27:72] @@ -2630,54 +2630,54 @@ circuit el2_ifu_mem_ctl : node _T_1773 = or(_T_1772, _T_1758) @[Mux.scala 27:72] wire _T_1774 : UInt<32> @[Mux.scala 27:72] _T_1774 <= _T_1773 @[Mux.scala 27:72] - node _T_1775 = eq(byp_fetch_index_0, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 436:285] - node _T_1776 = bits(_T_1775, 0, 0) @[el2_ifu_mem_ctl.scala 436:293] - node _T_1777 = bits(ic_miss_buff_data[0], 31, 0) @[el2_ifu_mem_ctl.scala 436:321] - node _T_1778 = eq(byp_fetch_index_0, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 436:285] - node _T_1779 = bits(_T_1778, 0, 0) @[el2_ifu_mem_ctl.scala 436:293] - node _T_1780 = bits(ic_miss_buff_data[1], 31, 0) @[el2_ifu_mem_ctl.scala 436:321] - node _T_1781 = eq(byp_fetch_index_0, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 436:285] - node _T_1782 = bits(_T_1781, 0, 0) @[el2_ifu_mem_ctl.scala 436:293] - node _T_1783 = bits(ic_miss_buff_data[2], 31, 0) @[el2_ifu_mem_ctl.scala 436:321] - node _T_1784 = eq(byp_fetch_index_0, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 436:285] - node _T_1785 = bits(_T_1784, 0, 0) @[el2_ifu_mem_ctl.scala 436:293] - node _T_1786 = bits(ic_miss_buff_data[3], 31, 0) @[el2_ifu_mem_ctl.scala 436:321] - node _T_1787 = eq(byp_fetch_index_0, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 436:285] - node _T_1788 = bits(_T_1787, 0, 0) @[el2_ifu_mem_ctl.scala 436:293] - node _T_1789 = bits(ic_miss_buff_data[4], 31, 0) @[el2_ifu_mem_ctl.scala 436:321] - node _T_1790 = eq(byp_fetch_index_0, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 436:285] - node _T_1791 = bits(_T_1790, 0, 0) @[el2_ifu_mem_ctl.scala 436:293] - node _T_1792 = bits(ic_miss_buff_data[5], 31, 0) @[el2_ifu_mem_ctl.scala 436:321] - node _T_1793 = eq(byp_fetch_index_0, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 436:285] - node _T_1794 = bits(_T_1793, 0, 0) @[el2_ifu_mem_ctl.scala 436:293] - node _T_1795 = bits(ic_miss_buff_data[6], 31, 0) @[el2_ifu_mem_ctl.scala 436:321] - node _T_1796 = eq(byp_fetch_index_0, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 436:285] - node _T_1797 = bits(_T_1796, 0, 0) @[el2_ifu_mem_ctl.scala 436:293] - node _T_1798 = bits(ic_miss_buff_data[7], 31, 0) @[el2_ifu_mem_ctl.scala 436:321] - node _T_1799 = eq(byp_fetch_index_0, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 436:285] - node _T_1800 = bits(_T_1799, 0, 0) @[el2_ifu_mem_ctl.scala 436:293] - node _T_1801 = bits(ic_miss_buff_data[8], 31, 0) @[el2_ifu_mem_ctl.scala 436:321] - node _T_1802 = eq(byp_fetch_index_0, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 436:285] - node _T_1803 = bits(_T_1802, 0, 0) @[el2_ifu_mem_ctl.scala 436:293] - node _T_1804 = bits(ic_miss_buff_data[9], 31, 0) @[el2_ifu_mem_ctl.scala 436:321] - node _T_1805 = eq(byp_fetch_index_0, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 436:285] - node _T_1806 = bits(_T_1805, 0, 0) @[el2_ifu_mem_ctl.scala 436:293] - node _T_1807 = bits(ic_miss_buff_data[10], 31, 0) @[el2_ifu_mem_ctl.scala 436:321] - node _T_1808 = eq(byp_fetch_index_0, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 436:285] - node _T_1809 = bits(_T_1808, 0, 0) @[el2_ifu_mem_ctl.scala 436:293] - node _T_1810 = bits(ic_miss_buff_data[11], 31, 0) @[el2_ifu_mem_ctl.scala 436:321] - node _T_1811 = eq(byp_fetch_index_0, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 436:285] - node _T_1812 = bits(_T_1811, 0, 0) @[el2_ifu_mem_ctl.scala 436:293] - node _T_1813 = bits(ic_miss_buff_data[12], 31, 0) @[el2_ifu_mem_ctl.scala 436:321] - node _T_1814 = eq(byp_fetch_index_0, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 436:285] - node _T_1815 = bits(_T_1814, 0, 0) @[el2_ifu_mem_ctl.scala 436:293] - node _T_1816 = bits(ic_miss_buff_data[13], 31, 0) @[el2_ifu_mem_ctl.scala 436:321] - node _T_1817 = eq(byp_fetch_index_0, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 436:285] - node _T_1818 = bits(_T_1817, 0, 0) @[el2_ifu_mem_ctl.scala 436:293] - node _T_1819 = bits(ic_miss_buff_data[14], 31, 0) @[el2_ifu_mem_ctl.scala 436:321] - node _T_1820 = eq(byp_fetch_index_0, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 436:285] - node _T_1821 = bits(_T_1820, 0, 0) @[el2_ifu_mem_ctl.scala 436:293] - node _T_1822 = bits(ic_miss_buff_data[15], 31, 0) @[el2_ifu_mem_ctl.scala 436:321] + node _T_1775 = eq(byp_fetch_index_0, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 437:285] + node _T_1776 = bits(_T_1775, 0, 0) @[el2_ifu_mem_ctl.scala 437:293] + node _T_1777 = bits(ic_miss_buff_data[0], 31, 0) @[el2_ifu_mem_ctl.scala 437:321] + node _T_1778 = eq(byp_fetch_index_0, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 437:285] + node _T_1779 = bits(_T_1778, 0, 0) @[el2_ifu_mem_ctl.scala 437:293] + node _T_1780 = bits(ic_miss_buff_data[1], 31, 0) @[el2_ifu_mem_ctl.scala 437:321] + node _T_1781 = eq(byp_fetch_index_0, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 437:285] + node _T_1782 = bits(_T_1781, 0, 0) @[el2_ifu_mem_ctl.scala 437:293] + node _T_1783 = bits(ic_miss_buff_data[2], 31, 0) @[el2_ifu_mem_ctl.scala 437:321] + node _T_1784 = eq(byp_fetch_index_0, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 437:285] + node _T_1785 = bits(_T_1784, 0, 0) @[el2_ifu_mem_ctl.scala 437:293] + node _T_1786 = bits(ic_miss_buff_data[3], 31, 0) @[el2_ifu_mem_ctl.scala 437:321] + node _T_1787 = eq(byp_fetch_index_0, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 437:285] + node _T_1788 = bits(_T_1787, 0, 0) @[el2_ifu_mem_ctl.scala 437:293] + node _T_1789 = bits(ic_miss_buff_data[4], 31, 0) @[el2_ifu_mem_ctl.scala 437:321] + node _T_1790 = eq(byp_fetch_index_0, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 437:285] + node _T_1791 = bits(_T_1790, 0, 0) @[el2_ifu_mem_ctl.scala 437:293] + node _T_1792 = bits(ic_miss_buff_data[5], 31, 0) @[el2_ifu_mem_ctl.scala 437:321] + node _T_1793 = eq(byp_fetch_index_0, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 437:285] + node _T_1794 = bits(_T_1793, 0, 0) @[el2_ifu_mem_ctl.scala 437:293] + node _T_1795 = bits(ic_miss_buff_data[6], 31, 0) @[el2_ifu_mem_ctl.scala 437:321] + node _T_1796 = eq(byp_fetch_index_0, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 437:285] + node _T_1797 = bits(_T_1796, 0, 0) @[el2_ifu_mem_ctl.scala 437:293] + node _T_1798 = bits(ic_miss_buff_data[7], 31, 0) @[el2_ifu_mem_ctl.scala 437:321] + node _T_1799 = eq(byp_fetch_index_0, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 437:285] + node _T_1800 = bits(_T_1799, 0, 0) @[el2_ifu_mem_ctl.scala 437:293] + node _T_1801 = bits(ic_miss_buff_data[8], 31, 0) @[el2_ifu_mem_ctl.scala 437:321] + node _T_1802 = eq(byp_fetch_index_0, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 437:285] + node _T_1803 = bits(_T_1802, 0, 0) @[el2_ifu_mem_ctl.scala 437:293] + node _T_1804 = bits(ic_miss_buff_data[9], 31, 0) @[el2_ifu_mem_ctl.scala 437:321] + node _T_1805 = eq(byp_fetch_index_0, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 437:285] + node _T_1806 = bits(_T_1805, 0, 0) @[el2_ifu_mem_ctl.scala 437:293] + node _T_1807 = bits(ic_miss_buff_data[10], 31, 0) @[el2_ifu_mem_ctl.scala 437:321] + node _T_1808 = eq(byp_fetch_index_0, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 437:285] + node _T_1809 = bits(_T_1808, 0, 0) @[el2_ifu_mem_ctl.scala 437:293] + node _T_1810 = bits(ic_miss_buff_data[11], 31, 0) @[el2_ifu_mem_ctl.scala 437:321] + node _T_1811 = eq(byp_fetch_index_0, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 437:285] + node _T_1812 = bits(_T_1811, 0, 0) @[el2_ifu_mem_ctl.scala 437:293] + node _T_1813 = bits(ic_miss_buff_data[12], 31, 0) @[el2_ifu_mem_ctl.scala 437:321] + node _T_1814 = eq(byp_fetch_index_0, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 437:285] + node _T_1815 = bits(_T_1814, 0, 0) @[el2_ifu_mem_ctl.scala 437:293] + node _T_1816 = bits(ic_miss_buff_data[13], 31, 0) @[el2_ifu_mem_ctl.scala 437:321] + node _T_1817 = eq(byp_fetch_index_0, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 437:285] + node _T_1818 = bits(_T_1817, 0, 0) @[el2_ifu_mem_ctl.scala 437:293] + node _T_1819 = bits(ic_miss_buff_data[14], 31, 0) @[el2_ifu_mem_ctl.scala 437:321] + node _T_1820 = eq(byp_fetch_index_0, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 437:285] + node _T_1821 = bits(_T_1820, 0, 0) @[el2_ifu_mem_ctl.scala 437:293] + node _T_1822 = bits(ic_miss_buff_data[15], 31, 0) @[el2_ifu_mem_ctl.scala 437:321] node _T_1823 = mux(_T_1776, _T_1777, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1824 = mux(_T_1779, _T_1780, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1825 = mux(_T_1782, _T_1783, UInt<1>("h00")) @[Mux.scala 27:72] @@ -2713,54 +2713,54 @@ circuit el2_ifu_mem_ctl : _T_1854 <= _T_1853 @[Mux.scala 27:72] node _T_1855 = cat(_T_1694, _T_1774) @[Cat.scala 29:58] node _T_1856 = cat(_T_1855, _T_1854) @[Cat.scala 29:58] - node _T_1857 = eq(byp_fetch_index_inc_1, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 437:73] - node _T_1858 = bits(_T_1857, 0, 0) @[el2_ifu_mem_ctl.scala 437:81] - node _T_1859 = bits(ic_miss_buff_data[0], 15, 0) @[el2_ifu_mem_ctl.scala 437:109] - node _T_1860 = eq(byp_fetch_index_inc_1, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 437:73] - node _T_1861 = bits(_T_1860, 0, 0) @[el2_ifu_mem_ctl.scala 437:81] - node _T_1862 = bits(ic_miss_buff_data[1], 15, 0) @[el2_ifu_mem_ctl.scala 437:109] - node _T_1863 = eq(byp_fetch_index_inc_1, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 437:73] - node _T_1864 = bits(_T_1863, 0, 0) @[el2_ifu_mem_ctl.scala 437:81] - node _T_1865 = bits(ic_miss_buff_data[2], 15, 0) @[el2_ifu_mem_ctl.scala 437:109] - node _T_1866 = eq(byp_fetch_index_inc_1, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 437:73] - node _T_1867 = bits(_T_1866, 0, 0) @[el2_ifu_mem_ctl.scala 437:81] - node _T_1868 = bits(ic_miss_buff_data[3], 15, 0) @[el2_ifu_mem_ctl.scala 437:109] - node _T_1869 = eq(byp_fetch_index_inc_1, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 437:73] - node _T_1870 = bits(_T_1869, 0, 0) @[el2_ifu_mem_ctl.scala 437:81] - node _T_1871 = bits(ic_miss_buff_data[4], 15, 0) @[el2_ifu_mem_ctl.scala 437:109] - node _T_1872 = eq(byp_fetch_index_inc_1, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 437:73] - node _T_1873 = bits(_T_1872, 0, 0) @[el2_ifu_mem_ctl.scala 437:81] - node _T_1874 = bits(ic_miss_buff_data[5], 15, 0) @[el2_ifu_mem_ctl.scala 437:109] - node _T_1875 = eq(byp_fetch_index_inc_1, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 437:73] - node _T_1876 = bits(_T_1875, 0, 0) @[el2_ifu_mem_ctl.scala 437:81] - node _T_1877 = bits(ic_miss_buff_data[6], 15, 0) @[el2_ifu_mem_ctl.scala 437:109] - node _T_1878 = eq(byp_fetch_index_inc_1, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 437:73] - node _T_1879 = bits(_T_1878, 0, 0) @[el2_ifu_mem_ctl.scala 437:81] - node _T_1880 = bits(ic_miss_buff_data[7], 15, 0) @[el2_ifu_mem_ctl.scala 437:109] - node _T_1881 = eq(byp_fetch_index_inc_1, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 437:73] - node _T_1882 = bits(_T_1881, 0, 0) @[el2_ifu_mem_ctl.scala 437:81] - node _T_1883 = bits(ic_miss_buff_data[8], 15, 0) @[el2_ifu_mem_ctl.scala 437:109] - node _T_1884 = eq(byp_fetch_index_inc_1, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 437:73] - node _T_1885 = bits(_T_1884, 0, 0) @[el2_ifu_mem_ctl.scala 437:81] - node _T_1886 = bits(ic_miss_buff_data[9], 15, 0) @[el2_ifu_mem_ctl.scala 437:109] - node _T_1887 = eq(byp_fetch_index_inc_1, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 437:73] - node _T_1888 = bits(_T_1887, 0, 0) @[el2_ifu_mem_ctl.scala 437:81] - node _T_1889 = bits(ic_miss_buff_data[10], 15, 0) @[el2_ifu_mem_ctl.scala 437:109] - node _T_1890 = eq(byp_fetch_index_inc_1, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 437:73] - node _T_1891 = bits(_T_1890, 0, 0) @[el2_ifu_mem_ctl.scala 437:81] - node _T_1892 = bits(ic_miss_buff_data[11], 15, 0) @[el2_ifu_mem_ctl.scala 437:109] - node _T_1893 = eq(byp_fetch_index_inc_1, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 437:73] - node _T_1894 = bits(_T_1893, 0, 0) @[el2_ifu_mem_ctl.scala 437:81] - node _T_1895 = bits(ic_miss_buff_data[12], 15, 0) @[el2_ifu_mem_ctl.scala 437:109] - node _T_1896 = eq(byp_fetch_index_inc_1, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 437:73] - node _T_1897 = bits(_T_1896, 0, 0) @[el2_ifu_mem_ctl.scala 437:81] - node _T_1898 = bits(ic_miss_buff_data[13], 15, 0) @[el2_ifu_mem_ctl.scala 437:109] - node _T_1899 = eq(byp_fetch_index_inc_1, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 437:73] - node _T_1900 = bits(_T_1899, 0, 0) @[el2_ifu_mem_ctl.scala 437:81] - node _T_1901 = bits(ic_miss_buff_data[14], 15, 0) @[el2_ifu_mem_ctl.scala 437:109] - node _T_1902 = eq(byp_fetch_index_inc_1, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 437:73] - node _T_1903 = bits(_T_1902, 0, 0) @[el2_ifu_mem_ctl.scala 437:81] - node _T_1904 = bits(ic_miss_buff_data[15], 15, 0) @[el2_ifu_mem_ctl.scala 437:109] + node _T_1857 = eq(byp_fetch_index_inc_1, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 438:73] + node _T_1858 = bits(_T_1857, 0, 0) @[el2_ifu_mem_ctl.scala 438:81] + node _T_1859 = bits(ic_miss_buff_data[0], 15, 0) @[el2_ifu_mem_ctl.scala 438:109] + node _T_1860 = eq(byp_fetch_index_inc_1, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 438:73] + node _T_1861 = bits(_T_1860, 0, 0) @[el2_ifu_mem_ctl.scala 438:81] + node _T_1862 = bits(ic_miss_buff_data[1], 15, 0) @[el2_ifu_mem_ctl.scala 438:109] + node _T_1863 = eq(byp_fetch_index_inc_1, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 438:73] + node _T_1864 = bits(_T_1863, 0, 0) @[el2_ifu_mem_ctl.scala 438:81] + node _T_1865 = bits(ic_miss_buff_data[2], 15, 0) @[el2_ifu_mem_ctl.scala 438:109] + node _T_1866 = eq(byp_fetch_index_inc_1, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 438:73] + node _T_1867 = bits(_T_1866, 0, 0) @[el2_ifu_mem_ctl.scala 438:81] + node _T_1868 = bits(ic_miss_buff_data[3], 15, 0) @[el2_ifu_mem_ctl.scala 438:109] + node _T_1869 = eq(byp_fetch_index_inc_1, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 438:73] + node _T_1870 = bits(_T_1869, 0, 0) @[el2_ifu_mem_ctl.scala 438:81] + node _T_1871 = bits(ic_miss_buff_data[4], 15, 0) @[el2_ifu_mem_ctl.scala 438:109] + node _T_1872 = eq(byp_fetch_index_inc_1, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 438:73] + node _T_1873 = bits(_T_1872, 0, 0) @[el2_ifu_mem_ctl.scala 438:81] + node _T_1874 = bits(ic_miss_buff_data[5], 15, 0) @[el2_ifu_mem_ctl.scala 438:109] + node _T_1875 = eq(byp_fetch_index_inc_1, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 438:73] + node _T_1876 = bits(_T_1875, 0, 0) @[el2_ifu_mem_ctl.scala 438:81] + node _T_1877 = bits(ic_miss_buff_data[6], 15, 0) @[el2_ifu_mem_ctl.scala 438:109] + node _T_1878 = eq(byp_fetch_index_inc_1, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 438:73] + node _T_1879 = bits(_T_1878, 0, 0) @[el2_ifu_mem_ctl.scala 438:81] + node _T_1880 = bits(ic_miss_buff_data[7], 15, 0) @[el2_ifu_mem_ctl.scala 438:109] + node _T_1881 = eq(byp_fetch_index_inc_1, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 438:73] + node _T_1882 = bits(_T_1881, 0, 0) @[el2_ifu_mem_ctl.scala 438:81] + node _T_1883 = bits(ic_miss_buff_data[8], 15, 0) @[el2_ifu_mem_ctl.scala 438:109] + node _T_1884 = eq(byp_fetch_index_inc_1, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 438:73] + node _T_1885 = bits(_T_1884, 0, 0) @[el2_ifu_mem_ctl.scala 438:81] + node _T_1886 = bits(ic_miss_buff_data[9], 15, 0) @[el2_ifu_mem_ctl.scala 438:109] + node _T_1887 = eq(byp_fetch_index_inc_1, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 438:73] + node _T_1888 = bits(_T_1887, 0, 0) @[el2_ifu_mem_ctl.scala 438:81] + node _T_1889 = bits(ic_miss_buff_data[10], 15, 0) @[el2_ifu_mem_ctl.scala 438:109] + node _T_1890 = eq(byp_fetch_index_inc_1, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 438:73] + node _T_1891 = bits(_T_1890, 0, 0) @[el2_ifu_mem_ctl.scala 438:81] + node _T_1892 = bits(ic_miss_buff_data[11], 15, 0) @[el2_ifu_mem_ctl.scala 438:109] + node _T_1893 = eq(byp_fetch_index_inc_1, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 438:73] + node _T_1894 = bits(_T_1893, 0, 0) @[el2_ifu_mem_ctl.scala 438:81] + node _T_1895 = bits(ic_miss_buff_data[12], 15, 0) @[el2_ifu_mem_ctl.scala 438:109] + node _T_1896 = eq(byp_fetch_index_inc_1, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 438:73] + node _T_1897 = bits(_T_1896, 0, 0) @[el2_ifu_mem_ctl.scala 438:81] + node _T_1898 = bits(ic_miss_buff_data[13], 15, 0) @[el2_ifu_mem_ctl.scala 438:109] + node _T_1899 = eq(byp_fetch_index_inc_1, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 438:73] + node _T_1900 = bits(_T_1899, 0, 0) @[el2_ifu_mem_ctl.scala 438:81] + node _T_1901 = bits(ic_miss_buff_data[14], 15, 0) @[el2_ifu_mem_ctl.scala 438:109] + node _T_1902 = eq(byp_fetch_index_inc_1, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 438:73] + node _T_1903 = bits(_T_1902, 0, 0) @[el2_ifu_mem_ctl.scala 438:81] + node _T_1904 = bits(ic_miss_buff_data[15], 15, 0) @[el2_ifu_mem_ctl.scala 438:109] node _T_1905 = mux(_T_1858, _T_1859, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1906 = mux(_T_1861, _T_1862, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1907 = mux(_T_1864, _T_1865, UInt<1>("h00")) @[Mux.scala 27:72] @@ -2794,54 +2794,54 @@ circuit el2_ifu_mem_ctl : node _T_1935 = or(_T_1934, _T_1920) @[Mux.scala 27:72] wire _T_1936 : UInt<16> @[Mux.scala 27:72] _T_1936 <= _T_1935 @[Mux.scala 27:72] - node _T_1937 = eq(byp_fetch_index_inc_0, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 437:183] - node _T_1938 = bits(_T_1937, 0, 0) @[el2_ifu_mem_ctl.scala 437:191] - node _T_1939 = bits(ic_miss_buff_data[0], 31, 0) @[el2_ifu_mem_ctl.scala 437:219] - node _T_1940 = eq(byp_fetch_index_inc_0, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 437:183] - node _T_1941 = bits(_T_1940, 0, 0) @[el2_ifu_mem_ctl.scala 437:191] - node _T_1942 = bits(ic_miss_buff_data[1], 31, 0) @[el2_ifu_mem_ctl.scala 437:219] - node _T_1943 = eq(byp_fetch_index_inc_0, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 437:183] - node _T_1944 = bits(_T_1943, 0, 0) @[el2_ifu_mem_ctl.scala 437:191] - node _T_1945 = bits(ic_miss_buff_data[2], 31, 0) @[el2_ifu_mem_ctl.scala 437:219] - node _T_1946 = eq(byp_fetch_index_inc_0, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 437:183] - node _T_1947 = bits(_T_1946, 0, 0) @[el2_ifu_mem_ctl.scala 437:191] - node _T_1948 = bits(ic_miss_buff_data[3], 31, 0) @[el2_ifu_mem_ctl.scala 437:219] - node _T_1949 = eq(byp_fetch_index_inc_0, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 437:183] - node _T_1950 = bits(_T_1949, 0, 0) @[el2_ifu_mem_ctl.scala 437:191] - node _T_1951 = bits(ic_miss_buff_data[4], 31, 0) @[el2_ifu_mem_ctl.scala 437:219] - node _T_1952 = eq(byp_fetch_index_inc_0, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 437:183] - node _T_1953 = bits(_T_1952, 0, 0) @[el2_ifu_mem_ctl.scala 437:191] - node _T_1954 = bits(ic_miss_buff_data[5], 31, 0) @[el2_ifu_mem_ctl.scala 437:219] - node _T_1955 = eq(byp_fetch_index_inc_0, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 437:183] - node _T_1956 = bits(_T_1955, 0, 0) @[el2_ifu_mem_ctl.scala 437:191] - node _T_1957 = bits(ic_miss_buff_data[6], 31, 0) @[el2_ifu_mem_ctl.scala 437:219] - node _T_1958 = eq(byp_fetch_index_inc_0, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 437:183] - node _T_1959 = bits(_T_1958, 0, 0) @[el2_ifu_mem_ctl.scala 437:191] - node _T_1960 = bits(ic_miss_buff_data[7], 31, 0) @[el2_ifu_mem_ctl.scala 437:219] - node _T_1961 = eq(byp_fetch_index_inc_0, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 437:183] - node _T_1962 = bits(_T_1961, 0, 0) @[el2_ifu_mem_ctl.scala 437:191] - node _T_1963 = bits(ic_miss_buff_data[8], 31, 0) @[el2_ifu_mem_ctl.scala 437:219] - node _T_1964 = eq(byp_fetch_index_inc_0, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 437:183] - node _T_1965 = bits(_T_1964, 0, 0) @[el2_ifu_mem_ctl.scala 437:191] - node _T_1966 = bits(ic_miss_buff_data[9], 31, 0) @[el2_ifu_mem_ctl.scala 437:219] - node _T_1967 = eq(byp_fetch_index_inc_0, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 437:183] - node _T_1968 = bits(_T_1967, 0, 0) @[el2_ifu_mem_ctl.scala 437:191] - node _T_1969 = bits(ic_miss_buff_data[10], 31, 0) @[el2_ifu_mem_ctl.scala 437:219] - node _T_1970 = eq(byp_fetch_index_inc_0, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 437:183] - node _T_1971 = bits(_T_1970, 0, 0) @[el2_ifu_mem_ctl.scala 437:191] - node _T_1972 = bits(ic_miss_buff_data[11], 31, 0) @[el2_ifu_mem_ctl.scala 437:219] - node _T_1973 = eq(byp_fetch_index_inc_0, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 437:183] - node _T_1974 = bits(_T_1973, 0, 0) @[el2_ifu_mem_ctl.scala 437:191] - node _T_1975 = bits(ic_miss_buff_data[12], 31, 0) @[el2_ifu_mem_ctl.scala 437:219] - node _T_1976 = eq(byp_fetch_index_inc_0, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 437:183] - node _T_1977 = bits(_T_1976, 0, 0) @[el2_ifu_mem_ctl.scala 437:191] - node _T_1978 = bits(ic_miss_buff_data[13], 31, 0) @[el2_ifu_mem_ctl.scala 437:219] - node _T_1979 = eq(byp_fetch_index_inc_0, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 437:183] - node _T_1980 = bits(_T_1979, 0, 0) @[el2_ifu_mem_ctl.scala 437:191] - node _T_1981 = bits(ic_miss_buff_data[14], 31, 0) @[el2_ifu_mem_ctl.scala 437:219] - node _T_1982 = eq(byp_fetch_index_inc_0, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 437:183] - node _T_1983 = bits(_T_1982, 0, 0) @[el2_ifu_mem_ctl.scala 437:191] - node _T_1984 = bits(ic_miss_buff_data[15], 31, 0) @[el2_ifu_mem_ctl.scala 437:219] + node _T_1937 = eq(byp_fetch_index_inc_0, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 438:183] + node _T_1938 = bits(_T_1937, 0, 0) @[el2_ifu_mem_ctl.scala 438:191] + node _T_1939 = bits(ic_miss_buff_data[0], 31, 0) @[el2_ifu_mem_ctl.scala 438:219] + node _T_1940 = eq(byp_fetch_index_inc_0, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 438:183] + node _T_1941 = bits(_T_1940, 0, 0) @[el2_ifu_mem_ctl.scala 438:191] + node _T_1942 = bits(ic_miss_buff_data[1], 31, 0) @[el2_ifu_mem_ctl.scala 438:219] + node _T_1943 = eq(byp_fetch_index_inc_0, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 438:183] + node _T_1944 = bits(_T_1943, 0, 0) @[el2_ifu_mem_ctl.scala 438:191] + node _T_1945 = bits(ic_miss_buff_data[2], 31, 0) @[el2_ifu_mem_ctl.scala 438:219] + node _T_1946 = eq(byp_fetch_index_inc_0, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 438:183] + node _T_1947 = bits(_T_1946, 0, 0) @[el2_ifu_mem_ctl.scala 438:191] + node _T_1948 = bits(ic_miss_buff_data[3], 31, 0) @[el2_ifu_mem_ctl.scala 438:219] + node _T_1949 = eq(byp_fetch_index_inc_0, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 438:183] + node _T_1950 = bits(_T_1949, 0, 0) @[el2_ifu_mem_ctl.scala 438:191] + node _T_1951 = bits(ic_miss_buff_data[4], 31, 0) @[el2_ifu_mem_ctl.scala 438:219] + node _T_1952 = eq(byp_fetch_index_inc_0, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 438:183] + node _T_1953 = bits(_T_1952, 0, 0) @[el2_ifu_mem_ctl.scala 438:191] + node _T_1954 = bits(ic_miss_buff_data[5], 31, 0) @[el2_ifu_mem_ctl.scala 438:219] + node _T_1955 = eq(byp_fetch_index_inc_0, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 438:183] + node _T_1956 = bits(_T_1955, 0, 0) @[el2_ifu_mem_ctl.scala 438:191] + node _T_1957 = bits(ic_miss_buff_data[6], 31, 0) @[el2_ifu_mem_ctl.scala 438:219] + node _T_1958 = eq(byp_fetch_index_inc_0, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 438:183] + node _T_1959 = bits(_T_1958, 0, 0) @[el2_ifu_mem_ctl.scala 438:191] + node _T_1960 = bits(ic_miss_buff_data[7], 31, 0) @[el2_ifu_mem_ctl.scala 438:219] + node _T_1961 = eq(byp_fetch_index_inc_0, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 438:183] + node _T_1962 = bits(_T_1961, 0, 0) @[el2_ifu_mem_ctl.scala 438:191] + node _T_1963 = bits(ic_miss_buff_data[8], 31, 0) @[el2_ifu_mem_ctl.scala 438:219] + node _T_1964 = eq(byp_fetch_index_inc_0, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 438:183] + node _T_1965 = bits(_T_1964, 0, 0) @[el2_ifu_mem_ctl.scala 438:191] + node _T_1966 = bits(ic_miss_buff_data[9], 31, 0) @[el2_ifu_mem_ctl.scala 438:219] + node _T_1967 = eq(byp_fetch_index_inc_0, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 438:183] + node _T_1968 = bits(_T_1967, 0, 0) @[el2_ifu_mem_ctl.scala 438:191] + node _T_1969 = bits(ic_miss_buff_data[10], 31, 0) @[el2_ifu_mem_ctl.scala 438:219] + node _T_1970 = eq(byp_fetch_index_inc_0, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 438:183] + node _T_1971 = bits(_T_1970, 0, 0) @[el2_ifu_mem_ctl.scala 438:191] + node _T_1972 = bits(ic_miss_buff_data[11], 31, 0) @[el2_ifu_mem_ctl.scala 438:219] + node _T_1973 = eq(byp_fetch_index_inc_0, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 438:183] + node _T_1974 = bits(_T_1973, 0, 0) @[el2_ifu_mem_ctl.scala 438:191] + node _T_1975 = bits(ic_miss_buff_data[12], 31, 0) @[el2_ifu_mem_ctl.scala 438:219] + node _T_1976 = eq(byp_fetch_index_inc_0, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 438:183] + node _T_1977 = bits(_T_1976, 0, 0) @[el2_ifu_mem_ctl.scala 438:191] + node _T_1978 = bits(ic_miss_buff_data[13], 31, 0) @[el2_ifu_mem_ctl.scala 438:219] + node _T_1979 = eq(byp_fetch_index_inc_0, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 438:183] + node _T_1980 = bits(_T_1979, 0, 0) @[el2_ifu_mem_ctl.scala 438:191] + node _T_1981 = bits(ic_miss_buff_data[14], 31, 0) @[el2_ifu_mem_ctl.scala 438:219] + node _T_1982 = eq(byp_fetch_index_inc_0, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 438:183] + node _T_1983 = bits(_T_1982, 0, 0) @[el2_ifu_mem_ctl.scala 438:191] + node _T_1984 = bits(ic_miss_buff_data[15], 31, 0) @[el2_ifu_mem_ctl.scala 438:219] node _T_1985 = mux(_T_1938, _T_1939, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1986 = mux(_T_1941, _T_1942, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1987 = mux(_T_1944, _T_1945, UInt<1>("h00")) @[Mux.scala 27:72] @@ -2875,54 +2875,54 @@ circuit el2_ifu_mem_ctl : node _T_2015 = or(_T_2014, _T_2000) @[Mux.scala 27:72] wire _T_2016 : UInt<32> @[Mux.scala 27:72] _T_2016 <= _T_2015 @[Mux.scala 27:72] - node _T_2017 = eq(byp_fetch_index_1, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 437:289] - node _T_2018 = bits(_T_2017, 0, 0) @[el2_ifu_mem_ctl.scala 437:297] - node _T_2019 = bits(ic_miss_buff_data[0], 31, 0) @[el2_ifu_mem_ctl.scala 437:325] - node _T_2020 = eq(byp_fetch_index_1, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 437:289] - node _T_2021 = bits(_T_2020, 0, 0) @[el2_ifu_mem_ctl.scala 437:297] - node _T_2022 = bits(ic_miss_buff_data[1], 31, 0) @[el2_ifu_mem_ctl.scala 437:325] - node _T_2023 = eq(byp_fetch_index_1, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 437:289] - node _T_2024 = bits(_T_2023, 0, 0) @[el2_ifu_mem_ctl.scala 437:297] - node _T_2025 = bits(ic_miss_buff_data[2], 31, 0) @[el2_ifu_mem_ctl.scala 437:325] - node _T_2026 = eq(byp_fetch_index_1, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 437:289] - node _T_2027 = bits(_T_2026, 0, 0) @[el2_ifu_mem_ctl.scala 437:297] - node _T_2028 = bits(ic_miss_buff_data[3], 31, 0) @[el2_ifu_mem_ctl.scala 437:325] - node _T_2029 = eq(byp_fetch_index_1, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 437:289] - node _T_2030 = bits(_T_2029, 0, 0) @[el2_ifu_mem_ctl.scala 437:297] - node _T_2031 = bits(ic_miss_buff_data[4], 31, 0) @[el2_ifu_mem_ctl.scala 437:325] - node _T_2032 = eq(byp_fetch_index_1, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 437:289] - node _T_2033 = bits(_T_2032, 0, 0) @[el2_ifu_mem_ctl.scala 437:297] - node _T_2034 = bits(ic_miss_buff_data[5], 31, 0) @[el2_ifu_mem_ctl.scala 437:325] - node _T_2035 = eq(byp_fetch_index_1, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 437:289] - node _T_2036 = bits(_T_2035, 0, 0) @[el2_ifu_mem_ctl.scala 437:297] - node _T_2037 = bits(ic_miss_buff_data[6], 31, 0) @[el2_ifu_mem_ctl.scala 437:325] - node _T_2038 = eq(byp_fetch_index_1, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 437:289] - node _T_2039 = bits(_T_2038, 0, 0) @[el2_ifu_mem_ctl.scala 437:297] - node _T_2040 = bits(ic_miss_buff_data[7], 31, 0) @[el2_ifu_mem_ctl.scala 437:325] - node _T_2041 = eq(byp_fetch_index_1, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 437:289] - node _T_2042 = bits(_T_2041, 0, 0) @[el2_ifu_mem_ctl.scala 437:297] - node _T_2043 = bits(ic_miss_buff_data[8], 31, 0) @[el2_ifu_mem_ctl.scala 437:325] - node _T_2044 = eq(byp_fetch_index_1, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 437:289] - node _T_2045 = bits(_T_2044, 0, 0) @[el2_ifu_mem_ctl.scala 437:297] - node _T_2046 = bits(ic_miss_buff_data[9], 31, 0) @[el2_ifu_mem_ctl.scala 437:325] - node _T_2047 = eq(byp_fetch_index_1, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 437:289] - node _T_2048 = bits(_T_2047, 0, 0) @[el2_ifu_mem_ctl.scala 437:297] - node _T_2049 = bits(ic_miss_buff_data[10], 31, 0) @[el2_ifu_mem_ctl.scala 437:325] - node _T_2050 = eq(byp_fetch_index_1, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 437:289] - node _T_2051 = bits(_T_2050, 0, 0) @[el2_ifu_mem_ctl.scala 437:297] - node _T_2052 = bits(ic_miss_buff_data[11], 31, 0) @[el2_ifu_mem_ctl.scala 437:325] - node _T_2053 = eq(byp_fetch_index_1, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 437:289] - node _T_2054 = bits(_T_2053, 0, 0) @[el2_ifu_mem_ctl.scala 437:297] - node _T_2055 = bits(ic_miss_buff_data[12], 31, 0) @[el2_ifu_mem_ctl.scala 437:325] - node _T_2056 = eq(byp_fetch_index_1, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 437:289] - node _T_2057 = bits(_T_2056, 0, 0) @[el2_ifu_mem_ctl.scala 437:297] - node _T_2058 = bits(ic_miss_buff_data[13], 31, 0) @[el2_ifu_mem_ctl.scala 437:325] - node _T_2059 = eq(byp_fetch_index_1, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 437:289] - node _T_2060 = bits(_T_2059, 0, 0) @[el2_ifu_mem_ctl.scala 437:297] - node _T_2061 = bits(ic_miss_buff_data[14], 31, 0) @[el2_ifu_mem_ctl.scala 437:325] - node _T_2062 = eq(byp_fetch_index_1, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 437:289] - node _T_2063 = bits(_T_2062, 0, 0) @[el2_ifu_mem_ctl.scala 437:297] - node _T_2064 = bits(ic_miss_buff_data[15], 31, 0) @[el2_ifu_mem_ctl.scala 437:325] + node _T_2017 = eq(byp_fetch_index_1, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 438:289] + node _T_2018 = bits(_T_2017, 0, 0) @[el2_ifu_mem_ctl.scala 438:297] + node _T_2019 = bits(ic_miss_buff_data[0], 31, 0) @[el2_ifu_mem_ctl.scala 438:325] + node _T_2020 = eq(byp_fetch_index_1, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 438:289] + node _T_2021 = bits(_T_2020, 0, 0) @[el2_ifu_mem_ctl.scala 438:297] + node _T_2022 = bits(ic_miss_buff_data[1], 31, 0) @[el2_ifu_mem_ctl.scala 438:325] + node _T_2023 = eq(byp_fetch_index_1, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 438:289] + node _T_2024 = bits(_T_2023, 0, 0) @[el2_ifu_mem_ctl.scala 438:297] + node _T_2025 = bits(ic_miss_buff_data[2], 31, 0) @[el2_ifu_mem_ctl.scala 438:325] + node _T_2026 = eq(byp_fetch_index_1, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 438:289] + node _T_2027 = bits(_T_2026, 0, 0) @[el2_ifu_mem_ctl.scala 438:297] + node _T_2028 = bits(ic_miss_buff_data[3], 31, 0) @[el2_ifu_mem_ctl.scala 438:325] + node _T_2029 = eq(byp_fetch_index_1, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 438:289] + node _T_2030 = bits(_T_2029, 0, 0) @[el2_ifu_mem_ctl.scala 438:297] + node _T_2031 = bits(ic_miss_buff_data[4], 31, 0) @[el2_ifu_mem_ctl.scala 438:325] + node _T_2032 = eq(byp_fetch_index_1, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 438:289] + node _T_2033 = bits(_T_2032, 0, 0) @[el2_ifu_mem_ctl.scala 438:297] + node _T_2034 = bits(ic_miss_buff_data[5], 31, 0) @[el2_ifu_mem_ctl.scala 438:325] + node _T_2035 = eq(byp_fetch_index_1, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 438:289] + node _T_2036 = bits(_T_2035, 0, 0) @[el2_ifu_mem_ctl.scala 438:297] + node _T_2037 = bits(ic_miss_buff_data[6], 31, 0) @[el2_ifu_mem_ctl.scala 438:325] + node _T_2038 = eq(byp_fetch_index_1, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 438:289] + node _T_2039 = bits(_T_2038, 0, 0) @[el2_ifu_mem_ctl.scala 438:297] + node _T_2040 = bits(ic_miss_buff_data[7], 31, 0) @[el2_ifu_mem_ctl.scala 438:325] + node _T_2041 = eq(byp_fetch_index_1, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 438:289] + node _T_2042 = bits(_T_2041, 0, 0) @[el2_ifu_mem_ctl.scala 438:297] + node _T_2043 = bits(ic_miss_buff_data[8], 31, 0) @[el2_ifu_mem_ctl.scala 438:325] + node _T_2044 = eq(byp_fetch_index_1, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 438:289] + node _T_2045 = bits(_T_2044, 0, 0) @[el2_ifu_mem_ctl.scala 438:297] + node _T_2046 = bits(ic_miss_buff_data[9], 31, 0) @[el2_ifu_mem_ctl.scala 438:325] + node _T_2047 = eq(byp_fetch_index_1, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 438:289] + node _T_2048 = bits(_T_2047, 0, 0) @[el2_ifu_mem_ctl.scala 438:297] + node _T_2049 = bits(ic_miss_buff_data[10], 31, 0) @[el2_ifu_mem_ctl.scala 438:325] + node _T_2050 = eq(byp_fetch_index_1, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 438:289] + node _T_2051 = bits(_T_2050, 0, 0) @[el2_ifu_mem_ctl.scala 438:297] + node _T_2052 = bits(ic_miss_buff_data[11], 31, 0) @[el2_ifu_mem_ctl.scala 438:325] + node _T_2053 = eq(byp_fetch_index_1, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 438:289] + node _T_2054 = bits(_T_2053, 0, 0) @[el2_ifu_mem_ctl.scala 438:297] + node _T_2055 = bits(ic_miss_buff_data[12], 31, 0) @[el2_ifu_mem_ctl.scala 438:325] + node _T_2056 = eq(byp_fetch_index_1, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 438:289] + node _T_2057 = bits(_T_2056, 0, 0) @[el2_ifu_mem_ctl.scala 438:297] + node _T_2058 = bits(ic_miss_buff_data[13], 31, 0) @[el2_ifu_mem_ctl.scala 438:325] + node _T_2059 = eq(byp_fetch_index_1, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 438:289] + node _T_2060 = bits(_T_2059, 0, 0) @[el2_ifu_mem_ctl.scala 438:297] + node _T_2061 = bits(ic_miss_buff_data[14], 31, 0) @[el2_ifu_mem_ctl.scala 438:325] + node _T_2062 = eq(byp_fetch_index_1, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 438:289] + node _T_2063 = bits(_T_2062, 0, 0) @[el2_ifu_mem_ctl.scala 438:297] + node _T_2064 = bits(ic_miss_buff_data[15], 31, 0) @[el2_ifu_mem_ctl.scala 438:325] node _T_2065 = mux(_T_2018, _T_2019, UInt<1>("h00")) @[Mux.scala 27:72] node _T_2066 = mux(_T_2021, _T_2022, UInt<1>("h00")) @[Mux.scala 27:72] node _T_2067 = mux(_T_2024, _T_2025, UInt<1>("h00")) @[Mux.scala 27:72] @@ -2958,49 +2958,49 @@ circuit el2_ifu_mem_ctl : _T_2096 <= _T_2095 @[Mux.scala 27:72] node _T_2097 = cat(_T_1936, _T_2016) @[Cat.scala 29:58] node _T_2098 = cat(_T_2097, _T_2096) @[Cat.scala 29:58] - node ic_byp_data_only_pre_new = mux(_T_1614, _T_1856, _T_2098) @[el2_ifu_mem_ctl.scala 435:37] - node _T_2099 = bits(ifu_fetch_addr_int_f, 0, 0) @[el2_ifu_mem_ctl.scala 439:52] - node _T_2100 = bits(_T_2099, 0, 0) @[el2_ifu_mem_ctl.scala 439:62] - node _T_2101 = eq(_T_2100, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 439:31] - node _T_2102 = bits(ic_byp_data_only_pre_new, 79, 16) @[el2_ifu_mem_ctl.scala 439:128] + node ic_byp_data_only_pre_new = mux(_T_1614, _T_1856, _T_2098) @[el2_ifu_mem_ctl.scala 436:37] + node _T_2099 = bits(ifu_fetch_addr_int_f, 0, 0) @[el2_ifu_mem_ctl.scala 440:52] + node _T_2100 = bits(_T_2099, 0, 0) @[el2_ifu_mem_ctl.scala 440:62] + node _T_2101 = eq(_T_2100, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 440:31] + node _T_2102 = bits(ic_byp_data_only_pre_new, 79, 16) @[el2_ifu_mem_ctl.scala 440:128] node _T_2103 = cat(UInt<16>("h00"), _T_2102) @[Cat.scala 29:58] - node _T_2104 = mux(_T_2101, ic_byp_data_only_pre_new, _T_2103) @[el2_ifu_mem_ctl.scala 439:30] - ic_byp_data_only_new <= _T_2104 @[el2_ifu_mem_ctl.scala 439:24] - node _T_2105 = bits(imb_ff, 5, 5) @[el2_ifu_mem_ctl.scala 441:27] - node _T_2106 = bits(ifu_fetch_addr_int_f, 6, 6) @[el2_ifu_mem_ctl.scala 441:75] - node miss_wrap_f = neq(_T_2105, _T_2106) @[el2_ifu_mem_ctl.scala 441:51] - node _T_2107 = bits(byp_fetch_index, 4, 2) @[el2_ifu_mem_ctl.scala 442:102] - node _T_2108 = eq(_T_2107, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 442:127] - node _T_2109 = bits(_T_2108, 0, 0) @[el2_ifu_mem_ctl.scala 442:135] - node _T_2110 = bits(ic_miss_buff_data_valid, 0, 0) @[el2_ifu_mem_ctl.scala 442:166] - node _T_2111 = bits(byp_fetch_index, 4, 2) @[el2_ifu_mem_ctl.scala 442:102] - node _T_2112 = eq(_T_2111, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 442:127] - node _T_2113 = bits(_T_2112, 0, 0) @[el2_ifu_mem_ctl.scala 442:135] - node _T_2114 = bits(ic_miss_buff_data_valid, 1, 1) @[el2_ifu_mem_ctl.scala 442:166] - node _T_2115 = bits(byp_fetch_index, 4, 2) @[el2_ifu_mem_ctl.scala 442:102] - node _T_2116 = eq(_T_2115, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 442:127] - node _T_2117 = bits(_T_2116, 0, 0) @[el2_ifu_mem_ctl.scala 442:135] - node _T_2118 = bits(ic_miss_buff_data_valid, 2, 2) @[el2_ifu_mem_ctl.scala 442:166] - node _T_2119 = bits(byp_fetch_index, 4, 2) @[el2_ifu_mem_ctl.scala 442:102] - node _T_2120 = eq(_T_2119, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 442:127] - node _T_2121 = bits(_T_2120, 0, 0) @[el2_ifu_mem_ctl.scala 442:135] - node _T_2122 = bits(ic_miss_buff_data_valid, 3, 3) @[el2_ifu_mem_ctl.scala 442:166] - node _T_2123 = bits(byp_fetch_index, 4, 2) @[el2_ifu_mem_ctl.scala 442:102] - node _T_2124 = eq(_T_2123, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 442:127] - node _T_2125 = bits(_T_2124, 0, 0) @[el2_ifu_mem_ctl.scala 442:135] - node _T_2126 = bits(ic_miss_buff_data_valid, 4, 4) @[el2_ifu_mem_ctl.scala 442:166] - node _T_2127 = bits(byp_fetch_index, 4, 2) @[el2_ifu_mem_ctl.scala 442:102] - node _T_2128 = eq(_T_2127, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 442:127] - node _T_2129 = bits(_T_2128, 0, 0) @[el2_ifu_mem_ctl.scala 442:135] - node _T_2130 = bits(ic_miss_buff_data_valid, 5, 5) @[el2_ifu_mem_ctl.scala 442:166] - node _T_2131 = bits(byp_fetch_index, 4, 2) @[el2_ifu_mem_ctl.scala 442:102] - node _T_2132 = eq(_T_2131, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 442:127] - node _T_2133 = bits(_T_2132, 0, 0) @[el2_ifu_mem_ctl.scala 442:135] - node _T_2134 = bits(ic_miss_buff_data_valid, 6, 6) @[el2_ifu_mem_ctl.scala 442:166] - node _T_2135 = bits(byp_fetch_index, 4, 2) @[el2_ifu_mem_ctl.scala 442:102] - node _T_2136 = eq(_T_2135, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 442:127] - node _T_2137 = bits(_T_2136, 0, 0) @[el2_ifu_mem_ctl.scala 442:135] - node _T_2138 = bits(ic_miss_buff_data_valid, 7, 7) @[el2_ifu_mem_ctl.scala 442:166] + node _T_2104 = mux(_T_2101, ic_byp_data_only_pre_new, _T_2103) @[el2_ifu_mem_ctl.scala 440:30] + ic_byp_data_only_new <= _T_2104 @[el2_ifu_mem_ctl.scala 440:24] + node _T_2105 = bits(imb_ff, 5, 5) @[el2_ifu_mem_ctl.scala 442:27] + node _T_2106 = bits(ifu_fetch_addr_int_f, 6, 6) @[el2_ifu_mem_ctl.scala 442:75] + node miss_wrap_f = neq(_T_2105, _T_2106) @[el2_ifu_mem_ctl.scala 442:51] + node _T_2107 = bits(byp_fetch_index, 4, 2) @[el2_ifu_mem_ctl.scala 443:102] + node _T_2108 = eq(_T_2107, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 443:127] + node _T_2109 = bits(_T_2108, 0, 0) @[el2_ifu_mem_ctl.scala 443:135] + node _T_2110 = bits(ic_miss_buff_data_valid, 0, 0) @[el2_ifu_mem_ctl.scala 443:166] + node _T_2111 = bits(byp_fetch_index, 4, 2) @[el2_ifu_mem_ctl.scala 443:102] + node _T_2112 = eq(_T_2111, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 443:127] + node _T_2113 = bits(_T_2112, 0, 0) @[el2_ifu_mem_ctl.scala 443:135] + node _T_2114 = bits(ic_miss_buff_data_valid, 1, 1) @[el2_ifu_mem_ctl.scala 443:166] + node _T_2115 = bits(byp_fetch_index, 4, 2) @[el2_ifu_mem_ctl.scala 443:102] + node _T_2116 = eq(_T_2115, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 443:127] + node _T_2117 = bits(_T_2116, 0, 0) @[el2_ifu_mem_ctl.scala 443:135] + node _T_2118 = bits(ic_miss_buff_data_valid, 2, 2) @[el2_ifu_mem_ctl.scala 443:166] + node _T_2119 = bits(byp_fetch_index, 4, 2) @[el2_ifu_mem_ctl.scala 443:102] + node _T_2120 = eq(_T_2119, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 443:127] + node _T_2121 = bits(_T_2120, 0, 0) @[el2_ifu_mem_ctl.scala 443:135] + node _T_2122 = bits(ic_miss_buff_data_valid, 3, 3) @[el2_ifu_mem_ctl.scala 443:166] + node _T_2123 = bits(byp_fetch_index, 4, 2) @[el2_ifu_mem_ctl.scala 443:102] + node _T_2124 = eq(_T_2123, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 443:127] + node _T_2125 = bits(_T_2124, 0, 0) @[el2_ifu_mem_ctl.scala 443:135] + node _T_2126 = bits(ic_miss_buff_data_valid, 4, 4) @[el2_ifu_mem_ctl.scala 443:166] + node _T_2127 = bits(byp_fetch_index, 4, 2) @[el2_ifu_mem_ctl.scala 443:102] + node _T_2128 = eq(_T_2127, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 443:127] + node _T_2129 = bits(_T_2128, 0, 0) @[el2_ifu_mem_ctl.scala 443:135] + node _T_2130 = bits(ic_miss_buff_data_valid, 5, 5) @[el2_ifu_mem_ctl.scala 443:166] + node _T_2131 = bits(byp_fetch_index, 4, 2) @[el2_ifu_mem_ctl.scala 443:102] + node _T_2132 = eq(_T_2131, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 443:127] + node _T_2133 = bits(_T_2132, 0, 0) @[el2_ifu_mem_ctl.scala 443:135] + node _T_2134 = bits(ic_miss_buff_data_valid, 6, 6) @[el2_ifu_mem_ctl.scala 443:166] + node _T_2135 = bits(byp_fetch_index, 4, 2) @[el2_ifu_mem_ctl.scala 443:102] + node _T_2136 = eq(_T_2135, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 443:127] + node _T_2137 = bits(_T_2136, 0, 0) @[el2_ifu_mem_ctl.scala 443:135] + node _T_2138 = bits(ic_miss_buff_data_valid, 7, 7) @[el2_ifu_mem_ctl.scala 443:166] node _T_2139 = mux(_T_2109, _T_2110, UInt<1>("h00")) @[Mux.scala 27:72] node _T_2140 = mux(_T_2113, _T_2114, UInt<1>("h00")) @[Mux.scala 27:72] node _T_2141 = mux(_T_2117, _T_2118, UInt<1>("h00")) @[Mux.scala 27:72] @@ -3018,30 +3018,30 @@ circuit el2_ifu_mem_ctl : node _T_2153 = or(_T_2152, _T_2146) @[Mux.scala 27:72] wire ic_miss_buff_data_valid_bypass_index : UInt<1> @[Mux.scala 27:72] ic_miss_buff_data_valid_bypass_index <= _T_2153 @[Mux.scala 27:72] - node _T_2154 = eq(byp_fetch_index_inc, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 443:110] - node _T_2155 = bits(_T_2154, 0, 0) @[el2_ifu_mem_ctl.scala 443:118] - node _T_2156 = bits(ic_miss_buff_data_valid, 0, 0) @[el2_ifu_mem_ctl.scala 443:149] - node _T_2157 = eq(byp_fetch_index_inc, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 443:110] - node _T_2158 = bits(_T_2157, 0, 0) @[el2_ifu_mem_ctl.scala 443:118] - node _T_2159 = bits(ic_miss_buff_data_valid, 1, 1) @[el2_ifu_mem_ctl.scala 443:149] - node _T_2160 = eq(byp_fetch_index_inc, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 443:110] - node _T_2161 = bits(_T_2160, 0, 0) @[el2_ifu_mem_ctl.scala 443:118] - node _T_2162 = bits(ic_miss_buff_data_valid, 2, 2) @[el2_ifu_mem_ctl.scala 443:149] - node _T_2163 = eq(byp_fetch_index_inc, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 443:110] - node _T_2164 = bits(_T_2163, 0, 0) @[el2_ifu_mem_ctl.scala 443:118] - node _T_2165 = bits(ic_miss_buff_data_valid, 3, 3) @[el2_ifu_mem_ctl.scala 443:149] - node _T_2166 = eq(byp_fetch_index_inc, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 443:110] - node _T_2167 = bits(_T_2166, 0, 0) @[el2_ifu_mem_ctl.scala 443:118] - node _T_2168 = bits(ic_miss_buff_data_valid, 4, 4) @[el2_ifu_mem_ctl.scala 443:149] - node _T_2169 = eq(byp_fetch_index_inc, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 443:110] - node _T_2170 = bits(_T_2169, 0, 0) @[el2_ifu_mem_ctl.scala 443:118] - node _T_2171 = bits(ic_miss_buff_data_valid, 5, 5) @[el2_ifu_mem_ctl.scala 443:149] - node _T_2172 = eq(byp_fetch_index_inc, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 443:110] - node _T_2173 = bits(_T_2172, 0, 0) @[el2_ifu_mem_ctl.scala 443:118] - node _T_2174 = bits(ic_miss_buff_data_valid, 6, 6) @[el2_ifu_mem_ctl.scala 443:149] - node _T_2175 = eq(byp_fetch_index_inc, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 443:110] - node _T_2176 = bits(_T_2175, 0, 0) @[el2_ifu_mem_ctl.scala 443:118] - node _T_2177 = bits(ic_miss_buff_data_valid, 7, 7) @[el2_ifu_mem_ctl.scala 443:149] + node _T_2154 = eq(byp_fetch_index_inc, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 444:110] + node _T_2155 = bits(_T_2154, 0, 0) @[el2_ifu_mem_ctl.scala 444:118] + node _T_2156 = bits(ic_miss_buff_data_valid, 0, 0) @[el2_ifu_mem_ctl.scala 444:149] + node _T_2157 = eq(byp_fetch_index_inc, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 444:110] + node _T_2158 = bits(_T_2157, 0, 0) @[el2_ifu_mem_ctl.scala 444:118] + node _T_2159 = bits(ic_miss_buff_data_valid, 1, 1) @[el2_ifu_mem_ctl.scala 444:149] + node _T_2160 = eq(byp_fetch_index_inc, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 444:110] + node _T_2161 = bits(_T_2160, 0, 0) @[el2_ifu_mem_ctl.scala 444:118] + node _T_2162 = bits(ic_miss_buff_data_valid, 2, 2) @[el2_ifu_mem_ctl.scala 444:149] + node _T_2163 = eq(byp_fetch_index_inc, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 444:110] + node _T_2164 = bits(_T_2163, 0, 0) @[el2_ifu_mem_ctl.scala 444:118] + node _T_2165 = bits(ic_miss_buff_data_valid, 3, 3) @[el2_ifu_mem_ctl.scala 444:149] + node _T_2166 = eq(byp_fetch_index_inc, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 444:110] + node _T_2167 = bits(_T_2166, 0, 0) @[el2_ifu_mem_ctl.scala 444:118] + node _T_2168 = bits(ic_miss_buff_data_valid, 4, 4) @[el2_ifu_mem_ctl.scala 444:149] + node _T_2169 = eq(byp_fetch_index_inc, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 444:110] + node _T_2170 = bits(_T_2169, 0, 0) @[el2_ifu_mem_ctl.scala 444:118] + node _T_2171 = bits(ic_miss_buff_data_valid, 5, 5) @[el2_ifu_mem_ctl.scala 444:149] + node _T_2172 = eq(byp_fetch_index_inc, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 444:110] + node _T_2173 = bits(_T_2172, 0, 0) @[el2_ifu_mem_ctl.scala 444:118] + node _T_2174 = bits(ic_miss_buff_data_valid, 6, 6) @[el2_ifu_mem_ctl.scala 444:149] + node _T_2175 = eq(byp_fetch_index_inc, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 444:110] + node _T_2176 = bits(_T_2175, 0, 0) @[el2_ifu_mem_ctl.scala 444:118] + node _T_2177 = bits(ic_miss_buff_data_valid, 7, 7) @[el2_ifu_mem_ctl.scala 444:149] node _T_2178 = mux(_T_2155, _T_2156, UInt<1>("h00")) @[Mux.scala 27:72] node _T_2179 = mux(_T_2158, _T_2159, UInt<1>("h00")) @[Mux.scala 27:72] node _T_2180 = mux(_T_2161, _T_2162, UInt<1>("h00")) @[Mux.scala 27:72] @@ -3059,86 +3059,86 @@ circuit el2_ifu_mem_ctl : node _T_2192 = or(_T_2191, _T_2185) @[Mux.scala 27:72] wire ic_miss_buff_data_valid_inc_bypass_index : UInt<1> @[Mux.scala 27:72] ic_miss_buff_data_valid_inc_bypass_index <= _T_2192 @[Mux.scala 27:72] - node _T_2193 = bits(byp_fetch_index, 1, 1) @[el2_ifu_mem_ctl.scala 444:85] - node _T_2194 = eq(_T_2193, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 444:69] - node _T_2195 = and(ic_miss_buff_data_valid_bypass_index, _T_2194) @[el2_ifu_mem_ctl.scala 444:67] - node _T_2196 = bits(byp_fetch_index, 0, 0) @[el2_ifu_mem_ctl.scala 444:107] - node _T_2197 = eq(_T_2196, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 444:91] - node _T_2198 = and(_T_2195, _T_2197) @[el2_ifu_mem_ctl.scala 444:89] - node _T_2199 = bits(byp_fetch_index, 1, 1) @[el2_ifu_mem_ctl.scala 445:61] - node _T_2200 = eq(_T_2199, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 445:45] - node _T_2201 = and(ic_miss_buff_data_valid_bypass_index, _T_2200) @[el2_ifu_mem_ctl.scala 445:43] - node _T_2202 = bits(byp_fetch_index, 0, 0) @[el2_ifu_mem_ctl.scala 445:83] - node _T_2203 = and(_T_2201, _T_2202) @[el2_ifu_mem_ctl.scala 445:65] - node _T_2204 = or(_T_2198, _T_2203) @[el2_ifu_mem_ctl.scala 444:112] - node _T_2205 = bits(byp_fetch_index, 1, 1) @[el2_ifu_mem_ctl.scala 446:61] - node _T_2206 = and(ic_miss_buff_data_valid_bypass_index, _T_2205) @[el2_ifu_mem_ctl.scala 446:43] - node _T_2207 = bits(byp_fetch_index, 0, 0) @[el2_ifu_mem_ctl.scala 446:83] - node _T_2208 = eq(_T_2207, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 446:67] - node _T_2209 = and(_T_2206, _T_2208) @[el2_ifu_mem_ctl.scala 446:65] - node _T_2210 = or(_T_2204, _T_2209) @[el2_ifu_mem_ctl.scala 445:88] - node _T_2211 = bits(byp_fetch_index, 1, 1) @[el2_ifu_mem_ctl.scala 447:61] - node _T_2212 = and(ic_miss_buff_data_valid_bypass_index, _T_2211) @[el2_ifu_mem_ctl.scala 447:43] - node _T_2213 = bits(byp_fetch_index, 0, 0) @[el2_ifu_mem_ctl.scala 447:83] - node _T_2214 = and(_T_2212, _T_2213) @[el2_ifu_mem_ctl.scala 447:65] - node _T_2215 = and(_T_2214, ic_miss_buff_data_valid_inc_bypass_index) @[el2_ifu_mem_ctl.scala 447:87] - node _T_2216 = or(_T_2210, _T_2215) @[el2_ifu_mem_ctl.scala 446:88] - node _T_2217 = bits(byp_fetch_index, 4, 2) @[el2_ifu_mem_ctl.scala 448:61] + node _T_2193 = bits(byp_fetch_index, 1, 1) @[el2_ifu_mem_ctl.scala 445:85] + node _T_2194 = eq(_T_2193, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 445:69] + node _T_2195 = and(ic_miss_buff_data_valid_bypass_index, _T_2194) @[el2_ifu_mem_ctl.scala 445:67] + node _T_2196 = bits(byp_fetch_index, 0, 0) @[el2_ifu_mem_ctl.scala 445:107] + node _T_2197 = eq(_T_2196, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 445:91] + node _T_2198 = and(_T_2195, _T_2197) @[el2_ifu_mem_ctl.scala 445:89] + node _T_2199 = bits(byp_fetch_index, 1, 1) @[el2_ifu_mem_ctl.scala 446:61] + node _T_2200 = eq(_T_2199, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 446:45] + node _T_2201 = and(ic_miss_buff_data_valid_bypass_index, _T_2200) @[el2_ifu_mem_ctl.scala 446:43] + node _T_2202 = bits(byp_fetch_index, 0, 0) @[el2_ifu_mem_ctl.scala 446:83] + node _T_2203 = and(_T_2201, _T_2202) @[el2_ifu_mem_ctl.scala 446:65] + node _T_2204 = or(_T_2198, _T_2203) @[el2_ifu_mem_ctl.scala 445:112] + node _T_2205 = bits(byp_fetch_index, 1, 1) @[el2_ifu_mem_ctl.scala 447:61] + node _T_2206 = and(ic_miss_buff_data_valid_bypass_index, _T_2205) @[el2_ifu_mem_ctl.scala 447:43] + node _T_2207 = bits(byp_fetch_index, 0, 0) @[el2_ifu_mem_ctl.scala 447:83] + node _T_2208 = eq(_T_2207, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 447:67] + node _T_2209 = and(_T_2206, _T_2208) @[el2_ifu_mem_ctl.scala 447:65] + node _T_2210 = or(_T_2204, _T_2209) @[el2_ifu_mem_ctl.scala 446:88] + node _T_2211 = bits(byp_fetch_index, 1, 1) @[el2_ifu_mem_ctl.scala 448:61] + node _T_2212 = and(ic_miss_buff_data_valid_bypass_index, _T_2211) @[el2_ifu_mem_ctl.scala 448:43] + node _T_2213 = bits(byp_fetch_index, 0, 0) @[el2_ifu_mem_ctl.scala 448:83] + node _T_2214 = and(_T_2212, _T_2213) @[el2_ifu_mem_ctl.scala 448:65] + node _T_2215 = and(_T_2214, ic_miss_buff_data_valid_inc_bypass_index) @[el2_ifu_mem_ctl.scala 448:87] + node _T_2216 = or(_T_2210, _T_2215) @[el2_ifu_mem_ctl.scala 447:88] + node _T_2217 = bits(byp_fetch_index, 4, 2) @[el2_ifu_mem_ctl.scala 449:61] node _T_2218 = mux(UInt<1>("h01"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_2219 = eq(_T_2217, _T_2218) @[el2_ifu_mem_ctl.scala 448:87] - node _T_2220 = and(ic_miss_buff_data_valid_bypass_index, _T_2219) @[el2_ifu_mem_ctl.scala 448:43] - node miss_buff_hit_unq_f = or(_T_2216, _T_2220) @[el2_ifu_mem_ctl.scala 447:131] - node _T_2221 = eq(miss_state, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 450:30] - node _T_2222 = eq(miss_wrap_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 450:68] - node _T_2223 = and(miss_buff_hit_unq_f, _T_2222) @[el2_ifu_mem_ctl.scala 450:66] - node _T_2224 = and(_T_2221, _T_2223) @[el2_ifu_mem_ctl.scala 450:43] - stream_hit_f <= _T_2224 @[el2_ifu_mem_ctl.scala 450:16] - node _T_2225 = eq(miss_state, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 451:31] - node _T_2226 = eq(miss_wrap_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 451:70] - node _T_2227 = and(miss_buff_hit_unq_f, _T_2226) @[el2_ifu_mem_ctl.scala 451:68] - node _T_2228 = eq(_T_2227, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 451:46] - node _T_2229 = and(_T_2225, _T_2228) @[el2_ifu_mem_ctl.scala 451:44] - node _T_2230 = and(_T_2229, ifc_fetch_req_f) @[el2_ifu_mem_ctl.scala 451:84] - stream_miss_f <= _T_2230 @[el2_ifu_mem_ctl.scala 451:17] - node _T_2231 = bits(byp_fetch_index, 4, 1) @[el2_ifu_mem_ctl.scala 452:35] + node _T_2219 = eq(_T_2217, _T_2218) @[el2_ifu_mem_ctl.scala 449:87] + node _T_2220 = and(ic_miss_buff_data_valid_bypass_index, _T_2219) @[el2_ifu_mem_ctl.scala 449:43] + node miss_buff_hit_unq_f = or(_T_2216, _T_2220) @[el2_ifu_mem_ctl.scala 448:131] + node _T_2221 = eq(miss_state, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 451:30] + node _T_2222 = eq(miss_wrap_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 451:68] + node _T_2223 = and(miss_buff_hit_unq_f, _T_2222) @[el2_ifu_mem_ctl.scala 451:66] + node _T_2224 = and(_T_2221, _T_2223) @[el2_ifu_mem_ctl.scala 451:43] + stream_hit_f <= _T_2224 @[el2_ifu_mem_ctl.scala 451:16] + node _T_2225 = eq(miss_state, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 452:31] + node _T_2226 = eq(miss_wrap_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 452:70] + node _T_2227 = and(miss_buff_hit_unq_f, _T_2226) @[el2_ifu_mem_ctl.scala 452:68] + node _T_2228 = eq(_T_2227, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 452:46] + node _T_2229 = and(_T_2225, _T_2228) @[el2_ifu_mem_ctl.scala 452:44] + node _T_2230 = and(_T_2229, ifc_fetch_req_f) @[el2_ifu_mem_ctl.scala 452:84] + stream_miss_f <= _T_2230 @[el2_ifu_mem_ctl.scala 452:17] + node _T_2231 = bits(byp_fetch_index, 4, 1) @[el2_ifu_mem_ctl.scala 453:35] node _T_2232 = mux(UInt<1>("h01"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_2233 = eq(_T_2231, _T_2232) @[el2_ifu_mem_ctl.scala 452:60] - node _T_2234 = and(_T_2233, ifc_fetch_req_f) @[el2_ifu_mem_ctl.scala 452:92] - node _T_2235 = and(_T_2234, stream_hit_f) @[el2_ifu_mem_ctl.scala 452:110] - stream_eol_f <= _T_2235 @[el2_ifu_mem_ctl.scala 452:16] - node _T_2236 = eq(miss_state, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 453:55] - node _T_2237 = eq(miss_state, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 453:87] - node _T_2238 = or(_T_2236, _T_2237) @[el2_ifu_mem_ctl.scala 453:74] - node _T_2239 = and(miss_buff_hit_unq_f, _T_2238) @[el2_ifu_mem_ctl.scala 453:41] - crit_byp_hit_f <= _T_2239 @[el2_ifu_mem_ctl.scala 453:18] - node _T_2240 = bits(ifu_bus_rid_ff, 2, 1) @[el2_ifu_mem_ctl.scala 456:37] - node _T_2241 = bits(ifu_bus_rid_ff, 0, 0) @[el2_ifu_mem_ctl.scala 456:70] - node _T_2242 = eq(_T_2241, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 456:55] + node _T_2233 = eq(_T_2231, _T_2232) @[el2_ifu_mem_ctl.scala 453:60] + node _T_2234 = and(_T_2233, ifc_fetch_req_f) @[el2_ifu_mem_ctl.scala 453:92] + node _T_2235 = and(_T_2234, stream_hit_f) @[el2_ifu_mem_ctl.scala 453:110] + stream_eol_f <= _T_2235 @[el2_ifu_mem_ctl.scala 453:16] + node _T_2236 = eq(miss_state, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 454:55] + node _T_2237 = eq(miss_state, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 454:87] + node _T_2238 = or(_T_2236, _T_2237) @[el2_ifu_mem_ctl.scala 454:74] + node _T_2239 = and(miss_buff_hit_unq_f, _T_2238) @[el2_ifu_mem_ctl.scala 454:41] + crit_byp_hit_f <= _T_2239 @[el2_ifu_mem_ctl.scala 454:18] + node _T_2240 = bits(ifu_bus_rid_ff, 2, 1) @[el2_ifu_mem_ctl.scala 457:37] + node _T_2241 = bits(ifu_bus_rid_ff, 0, 0) @[el2_ifu_mem_ctl.scala 457:70] + node _T_2242 = eq(_T_2241, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 457:55] node other_tag = cat(_T_2240, _T_2242) @[Cat.scala 29:58] - node _T_2243 = eq(other_tag, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 457:81] - node _T_2244 = bits(_T_2243, 0, 0) @[el2_ifu_mem_ctl.scala 457:89] - node _T_2245 = bits(ic_miss_buff_data_valid, 0, 0) @[el2_ifu_mem_ctl.scala 457:120] - node _T_2246 = eq(other_tag, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 457:81] - node _T_2247 = bits(_T_2246, 0, 0) @[el2_ifu_mem_ctl.scala 457:89] - node _T_2248 = bits(ic_miss_buff_data_valid, 1, 1) @[el2_ifu_mem_ctl.scala 457:120] - node _T_2249 = eq(other_tag, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 457:81] - node _T_2250 = bits(_T_2249, 0, 0) @[el2_ifu_mem_ctl.scala 457:89] - node _T_2251 = bits(ic_miss_buff_data_valid, 2, 2) @[el2_ifu_mem_ctl.scala 457:120] - node _T_2252 = eq(other_tag, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 457:81] - node _T_2253 = bits(_T_2252, 0, 0) @[el2_ifu_mem_ctl.scala 457:89] - node _T_2254 = bits(ic_miss_buff_data_valid, 3, 3) @[el2_ifu_mem_ctl.scala 457:120] - node _T_2255 = eq(other_tag, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 457:81] - node _T_2256 = bits(_T_2255, 0, 0) @[el2_ifu_mem_ctl.scala 457:89] - node _T_2257 = bits(ic_miss_buff_data_valid, 4, 4) @[el2_ifu_mem_ctl.scala 457:120] - node _T_2258 = eq(other_tag, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 457:81] - node _T_2259 = bits(_T_2258, 0, 0) @[el2_ifu_mem_ctl.scala 457:89] - node _T_2260 = bits(ic_miss_buff_data_valid, 5, 5) @[el2_ifu_mem_ctl.scala 457:120] - node _T_2261 = eq(other_tag, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 457:81] - node _T_2262 = bits(_T_2261, 0, 0) @[el2_ifu_mem_ctl.scala 457:89] - node _T_2263 = bits(ic_miss_buff_data_valid, 6, 6) @[el2_ifu_mem_ctl.scala 457:120] - node _T_2264 = eq(other_tag, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 457:81] - node _T_2265 = bits(_T_2264, 0, 0) @[el2_ifu_mem_ctl.scala 457:89] - node _T_2266 = bits(ic_miss_buff_data_valid, 7, 7) @[el2_ifu_mem_ctl.scala 457:120] + node _T_2243 = eq(other_tag, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 458:81] + node _T_2244 = bits(_T_2243, 0, 0) @[el2_ifu_mem_ctl.scala 458:89] + node _T_2245 = bits(ic_miss_buff_data_valid, 0, 0) @[el2_ifu_mem_ctl.scala 458:120] + node _T_2246 = eq(other_tag, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 458:81] + node _T_2247 = bits(_T_2246, 0, 0) @[el2_ifu_mem_ctl.scala 458:89] + node _T_2248 = bits(ic_miss_buff_data_valid, 1, 1) @[el2_ifu_mem_ctl.scala 458:120] + node _T_2249 = eq(other_tag, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 458:81] + node _T_2250 = bits(_T_2249, 0, 0) @[el2_ifu_mem_ctl.scala 458:89] + node _T_2251 = bits(ic_miss_buff_data_valid, 2, 2) @[el2_ifu_mem_ctl.scala 458:120] + node _T_2252 = eq(other_tag, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 458:81] + node _T_2253 = bits(_T_2252, 0, 0) @[el2_ifu_mem_ctl.scala 458:89] + node _T_2254 = bits(ic_miss_buff_data_valid, 3, 3) @[el2_ifu_mem_ctl.scala 458:120] + node _T_2255 = eq(other_tag, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 458:81] + node _T_2256 = bits(_T_2255, 0, 0) @[el2_ifu_mem_ctl.scala 458:89] + node _T_2257 = bits(ic_miss_buff_data_valid, 4, 4) @[el2_ifu_mem_ctl.scala 458:120] + node _T_2258 = eq(other_tag, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 458:81] + node _T_2259 = bits(_T_2258, 0, 0) @[el2_ifu_mem_ctl.scala 458:89] + node _T_2260 = bits(ic_miss_buff_data_valid, 5, 5) @[el2_ifu_mem_ctl.scala 458:120] + node _T_2261 = eq(other_tag, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 458:81] + node _T_2262 = bits(_T_2261, 0, 0) @[el2_ifu_mem_ctl.scala 458:89] + node _T_2263 = bits(ic_miss_buff_data_valid, 6, 6) @[el2_ifu_mem_ctl.scala 458:120] + node _T_2264 = eq(other_tag, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 458:81] + node _T_2265 = bits(_T_2264, 0, 0) @[el2_ifu_mem_ctl.scala 458:89] + node _T_2266 = bits(ic_miss_buff_data_valid, 7, 7) @[el2_ifu_mem_ctl.scala 458:120] node _T_2267 = mux(_T_2244, _T_2245, UInt<1>("h00")) @[Mux.scala 27:72] node _T_2268 = mux(_T_2247, _T_2248, UInt<1>("h00")) @[Mux.scala 27:72] node _T_2269 = mux(_T_2250, _T_2251, UInt<1>("h00")) @[Mux.scala 27:72] @@ -3156,56 +3156,56 @@ circuit el2_ifu_mem_ctl : node _T_2281 = or(_T_2280, _T_2274) @[Mux.scala 27:72] wire second_half_available : UInt<1> @[Mux.scala 27:72] second_half_available <= _T_2281 @[Mux.scala 27:72] - node _T_2282 = and(second_half_available, bus_ifu_wr_en_ff) @[el2_ifu_mem_ctl.scala 458:46] - write_ic_16_bytes <= _T_2282 @[el2_ifu_mem_ctl.scala 458:21] + node _T_2282 = and(second_half_available, bus_ifu_wr_en_ff) @[el2_ifu_mem_ctl.scala 459:46] + write_ic_16_bytes <= _T_2282 @[el2_ifu_mem_ctl.scala 459:21] node _T_2283 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58] - node _T_2284 = eq(_T_2283, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 459:89] - node _T_2285 = bits(_T_2284, 0, 0) @[el2_ifu_mem_ctl.scala 459:97] + node _T_2284 = eq(_T_2283, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 460:89] + node _T_2285 = bits(_T_2284, 0, 0) @[el2_ifu_mem_ctl.scala 460:97] node _T_2286 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58] - node _T_2287 = eq(_T_2286, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 459:89] - node _T_2288 = bits(_T_2287, 0, 0) @[el2_ifu_mem_ctl.scala 459:97] + node _T_2287 = eq(_T_2286, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 460:89] + node _T_2288 = bits(_T_2287, 0, 0) @[el2_ifu_mem_ctl.scala 460:97] node _T_2289 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58] - node _T_2290 = eq(_T_2289, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 459:89] - node _T_2291 = bits(_T_2290, 0, 0) @[el2_ifu_mem_ctl.scala 459:97] + node _T_2290 = eq(_T_2289, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 460:89] + node _T_2291 = bits(_T_2290, 0, 0) @[el2_ifu_mem_ctl.scala 460:97] node _T_2292 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58] - node _T_2293 = eq(_T_2292, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 459:89] - node _T_2294 = bits(_T_2293, 0, 0) @[el2_ifu_mem_ctl.scala 459:97] + node _T_2293 = eq(_T_2292, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 460:89] + node _T_2294 = bits(_T_2293, 0, 0) @[el2_ifu_mem_ctl.scala 460:97] node _T_2295 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58] - node _T_2296 = eq(_T_2295, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 459:89] - node _T_2297 = bits(_T_2296, 0, 0) @[el2_ifu_mem_ctl.scala 459:97] + node _T_2296 = eq(_T_2295, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 460:89] + node _T_2297 = bits(_T_2296, 0, 0) @[el2_ifu_mem_ctl.scala 460:97] node _T_2298 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58] - node _T_2299 = eq(_T_2298, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 459:89] - node _T_2300 = bits(_T_2299, 0, 0) @[el2_ifu_mem_ctl.scala 459:97] + node _T_2299 = eq(_T_2298, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 460:89] + node _T_2300 = bits(_T_2299, 0, 0) @[el2_ifu_mem_ctl.scala 460:97] node _T_2301 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58] - node _T_2302 = eq(_T_2301, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 459:89] - node _T_2303 = bits(_T_2302, 0, 0) @[el2_ifu_mem_ctl.scala 459:97] + node _T_2302 = eq(_T_2301, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 460:89] + node _T_2303 = bits(_T_2302, 0, 0) @[el2_ifu_mem_ctl.scala 460:97] node _T_2304 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58] - node _T_2305 = eq(_T_2304, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 459:89] - node _T_2306 = bits(_T_2305, 0, 0) @[el2_ifu_mem_ctl.scala 459:97] + node _T_2305 = eq(_T_2304, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 460:89] + node _T_2306 = bits(_T_2305, 0, 0) @[el2_ifu_mem_ctl.scala 460:97] node _T_2307 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58] - node _T_2308 = eq(_T_2307, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 459:89] - node _T_2309 = bits(_T_2308, 0, 0) @[el2_ifu_mem_ctl.scala 459:97] + node _T_2308 = eq(_T_2307, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 460:89] + node _T_2309 = bits(_T_2308, 0, 0) @[el2_ifu_mem_ctl.scala 460:97] node _T_2310 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58] - node _T_2311 = eq(_T_2310, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 459:89] - node _T_2312 = bits(_T_2311, 0, 0) @[el2_ifu_mem_ctl.scala 459:97] + node _T_2311 = eq(_T_2310, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 460:89] + node _T_2312 = bits(_T_2311, 0, 0) @[el2_ifu_mem_ctl.scala 460:97] node _T_2313 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58] - node _T_2314 = eq(_T_2313, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 459:89] - node _T_2315 = bits(_T_2314, 0, 0) @[el2_ifu_mem_ctl.scala 459:97] + node _T_2314 = eq(_T_2313, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 460:89] + node _T_2315 = bits(_T_2314, 0, 0) @[el2_ifu_mem_ctl.scala 460:97] node _T_2316 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58] - node _T_2317 = eq(_T_2316, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 459:89] - node _T_2318 = bits(_T_2317, 0, 0) @[el2_ifu_mem_ctl.scala 459:97] + node _T_2317 = eq(_T_2316, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 460:89] + node _T_2318 = bits(_T_2317, 0, 0) @[el2_ifu_mem_ctl.scala 460:97] node _T_2319 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58] - node _T_2320 = eq(_T_2319, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 459:89] - node _T_2321 = bits(_T_2320, 0, 0) @[el2_ifu_mem_ctl.scala 459:97] + node _T_2320 = eq(_T_2319, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 460:89] + node _T_2321 = bits(_T_2320, 0, 0) @[el2_ifu_mem_ctl.scala 460:97] node _T_2322 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58] - node _T_2323 = eq(_T_2322, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 459:89] - node _T_2324 = bits(_T_2323, 0, 0) @[el2_ifu_mem_ctl.scala 459:97] + node _T_2323 = eq(_T_2322, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 460:89] + node _T_2324 = bits(_T_2323, 0, 0) @[el2_ifu_mem_ctl.scala 460:97] node _T_2325 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58] - node _T_2326 = eq(_T_2325, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 459:89] - node _T_2327 = bits(_T_2326, 0, 0) @[el2_ifu_mem_ctl.scala 459:97] + node _T_2326 = eq(_T_2325, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 460:89] + node _T_2327 = bits(_T_2326, 0, 0) @[el2_ifu_mem_ctl.scala 460:97] node _T_2328 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58] - node _T_2329 = eq(_T_2328, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 459:89] - node _T_2330 = bits(_T_2329, 0, 0) @[el2_ifu_mem_ctl.scala 459:97] + node _T_2329 = eq(_T_2328, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 460:89] + node _T_2330 = bits(_T_2329, 0, 0) @[el2_ifu_mem_ctl.scala 460:97] node _T_2331 = mux(_T_2285, ic_miss_buff_data[0], UInt<1>("h00")) @[Mux.scala 27:72] node _T_2332 = mux(_T_2288, ic_miss_buff_data[1], UInt<1>("h00")) @[Mux.scala 27:72] node _T_2333 = mux(_T_2291, ic_miss_buff_data[2], UInt<1>("h00")) @[Mux.scala 27:72] @@ -3240,29 +3240,29 @@ circuit el2_ifu_mem_ctl : wire _T_2362 : UInt<32> @[Mux.scala 27:72] _T_2362 <= _T_2361 @[Mux.scala 27:72] node _T_2363 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2364 = eq(_T_2363, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 460:64] - node _T_2365 = bits(_T_2364, 0, 0) @[el2_ifu_mem_ctl.scala 460:72] + node _T_2364 = eq(_T_2363, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 461:64] + node _T_2365 = bits(_T_2364, 0, 0) @[el2_ifu_mem_ctl.scala 461:72] node _T_2366 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2367 = eq(_T_2366, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 460:64] - node _T_2368 = bits(_T_2367, 0, 0) @[el2_ifu_mem_ctl.scala 460:72] + node _T_2367 = eq(_T_2366, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 461:64] + node _T_2368 = bits(_T_2367, 0, 0) @[el2_ifu_mem_ctl.scala 461:72] node _T_2369 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2370 = eq(_T_2369, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 460:64] - node _T_2371 = bits(_T_2370, 0, 0) @[el2_ifu_mem_ctl.scala 460:72] + node _T_2370 = eq(_T_2369, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 461:64] + node _T_2371 = bits(_T_2370, 0, 0) @[el2_ifu_mem_ctl.scala 461:72] node _T_2372 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2373 = eq(_T_2372, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 460:64] - node _T_2374 = bits(_T_2373, 0, 0) @[el2_ifu_mem_ctl.scala 460:72] + node _T_2373 = eq(_T_2372, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 461:64] + node _T_2374 = bits(_T_2373, 0, 0) @[el2_ifu_mem_ctl.scala 461:72] node _T_2375 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2376 = eq(_T_2375, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 460:64] - node _T_2377 = bits(_T_2376, 0, 0) @[el2_ifu_mem_ctl.scala 460:72] + node _T_2376 = eq(_T_2375, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 461:64] + node _T_2377 = bits(_T_2376, 0, 0) @[el2_ifu_mem_ctl.scala 461:72] node _T_2378 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2379 = eq(_T_2378, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 460:64] - node _T_2380 = bits(_T_2379, 0, 0) @[el2_ifu_mem_ctl.scala 460:72] + node _T_2379 = eq(_T_2378, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 461:64] + node _T_2380 = bits(_T_2379, 0, 0) @[el2_ifu_mem_ctl.scala 461:72] node _T_2381 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2382 = eq(_T_2381, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 460:64] - node _T_2383 = bits(_T_2382, 0, 0) @[el2_ifu_mem_ctl.scala 460:72] + node _T_2382 = eq(_T_2381, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 461:64] + node _T_2383 = bits(_T_2382, 0, 0) @[el2_ifu_mem_ctl.scala 461:72] node _T_2384 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2385 = eq(_T_2384, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 460:64] - node _T_2386 = bits(_T_2385, 0, 0) @[el2_ifu_mem_ctl.scala 460:72] + node _T_2385 = eq(_T_2384, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 461:64] + node _T_2386 = bits(_T_2385, 0, 0) @[el2_ifu_mem_ctl.scala 461:72] node _T_2387 = mux(_T_2365, ic_miss_buff_data[0], UInt<1>("h00")) @[Mux.scala 27:72] node _T_2388 = mux(_T_2368, ic_miss_buff_data[1], UInt<1>("h00")) @[Mux.scala 27:72] node _T_2389 = mux(_T_2371, ic_miss_buff_data[2], UInt<1>("h00")) @[Mux.scala 27:72] @@ -3281,12 +3281,12 @@ circuit el2_ifu_mem_ctl : wire _T_2402 : UInt<32> @[Mux.scala 27:72] _T_2402 <= _T_2401 @[Mux.scala 27:72] node _T_2403 = cat(_T_2362, _T_2402) @[Cat.scala 29:58] - ic_miss_buff_half <= _T_2403 @[el2_ifu_mem_ctl.scala 459:21] - node _T_2404 = and(io.ic_tag_perr, sel_ic_data) @[el2_ifu_mem_ctl.scala 462:44] - node _T_2405 = or(ifc_region_acc_fault_final_f, ifc_bus_acc_fault_f) @[el2_ifu_mem_ctl.scala 462:91] - node _T_2406 = eq(_T_2405, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 462:60] - node _T_2407 = and(_T_2404, _T_2406) @[el2_ifu_mem_ctl.scala 462:58] - ic_rd_parity_final_err <= _T_2407 @[el2_ifu_mem_ctl.scala 462:26] + ic_miss_buff_half <= _T_2403 @[el2_ifu_mem_ctl.scala 460:21] + node _T_2404 = and(io.ic_tag_perr, sel_ic_data) @[el2_ifu_mem_ctl.scala 463:44] + node _T_2405 = or(ifc_region_acc_fault_final_f, ifc_bus_acc_fault_f) @[el2_ifu_mem_ctl.scala 463:91] + node _T_2406 = eq(_T_2405, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 463:60] + node _T_2407 = and(_T_2404, _T_2406) @[el2_ifu_mem_ctl.scala 463:58] + ic_rd_parity_final_err <= _T_2407 @[el2_ifu_mem_ctl.scala 463:26] wire ifu_ic_rw_int_addr_ff : UInt<6> ifu_ic_rw_int_addr_ff <= UInt<1>("h00") wire perr_sb_write_status : UInt<1> @@ -3299,16 +3299,16 @@ circuit el2_ifu_mem_ctl : perr_sel_invalidate <= UInt<1>("h00") node _T_2408 = bits(perr_sel_invalidate, 0, 0) @[Bitwise.scala 72:15] node perr_err_inv_way = mux(_T_2408, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_2409 = eq(perr_state, UInt<3>("h03")) @[el2_ifu_mem_ctl.scala 469:34] - iccm_correct_ecc <= _T_2409 @[el2_ifu_mem_ctl.scala 469:20] - node dma_sb_err_state = eq(perr_state, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 470:37] - wire dma_sb_err_state_ff : UInt<1> @[el2_ifu_mem_ctl.scala 471:33] - node _T_2410 = eq(dma_sb_err_state_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 472:49] - node _T_2411 = and(iccm_correct_ecc, _T_2410) @[el2_ifu_mem_ctl.scala 472:47] - io.iccm_buf_correct_ecc <= _T_2411 @[el2_ifu_mem_ctl.scala 472:27] - reg _T_2412 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 473:58] - _T_2412 <= dma_sb_err_state @[el2_ifu_mem_ctl.scala 473:58] - dma_sb_err_state_ff <= _T_2412 @[el2_ifu_mem_ctl.scala 473:23] + node _T_2409 = eq(perr_state, UInt<3>("h03")) @[el2_ifu_mem_ctl.scala 470:34] + iccm_correct_ecc <= _T_2409 @[el2_ifu_mem_ctl.scala 470:20] + node dma_sb_err_state = eq(perr_state, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 471:37] + wire dma_sb_err_state_ff : UInt<1> @[el2_ifu_mem_ctl.scala 472:33] + node _T_2410 = eq(dma_sb_err_state_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 473:49] + node _T_2411 = and(iccm_correct_ecc, _T_2410) @[el2_ifu_mem_ctl.scala 473:47] + io.iccm_buf_correct_ecc <= _T_2411 @[el2_ifu_mem_ctl.scala 473:27] + reg _T_2412 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 474:58] + _T_2412 <= dma_sb_err_state @[el2_ifu_mem_ctl.scala 474:58] + dma_sb_err_state_ff <= _T_2412 @[el2_ifu_mem_ctl.scala 474:23] wire perr_nxtstate : UInt<3> perr_nxtstate <= UInt<1>("h00") wire perr_state_en : UInt<1> @@ -3317,165 +3317,165 @@ circuit el2_ifu_mem_ctl : iccm_error_start <= UInt<1>("h00") node _T_2413 = eq(UInt<3>("h00"), perr_state) @[Conditional.scala 37:30] when _T_2413 : @[Conditional.scala 40:58] - node _T_2414 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 481:89] - node _T_2415 = and(io.ic_error_start, _T_2414) @[el2_ifu_mem_ctl.scala 481:87] - node _T_2416 = bits(_T_2415, 0, 0) @[el2_ifu_mem_ctl.scala 481:110] - node _T_2417 = mux(_T_2416, UInt<3>("h01"), UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 481:67] - node _T_2418 = mux(io.iccm_dma_sb_error, UInt<3>("h04"), _T_2417) @[el2_ifu_mem_ctl.scala 481:27] - perr_nxtstate <= _T_2418 @[el2_ifu_mem_ctl.scala 481:21] - node _T_2419 = or(iccm_error_start, io.ic_error_start) @[el2_ifu_mem_ctl.scala 482:44] - node _T_2420 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 482:67] - node _T_2421 = and(_T_2419, _T_2420) @[el2_ifu_mem_ctl.scala 482:65] - node _T_2422 = or(_T_2421, io.iccm_dma_sb_error) @[el2_ifu_mem_ctl.scala 482:88] - node _T_2423 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 482:114] - node _T_2424 = and(_T_2422, _T_2423) @[el2_ifu_mem_ctl.scala 482:112] - perr_state_en <= _T_2424 @[el2_ifu_mem_ctl.scala 482:21] - perr_sb_write_status <= perr_state_en @[el2_ifu_mem_ctl.scala 483:28] + node _T_2414 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 482:89] + node _T_2415 = and(io.ic_error_start, _T_2414) @[el2_ifu_mem_ctl.scala 482:87] + node _T_2416 = bits(_T_2415, 0, 0) @[el2_ifu_mem_ctl.scala 482:110] + node _T_2417 = mux(_T_2416, UInt<3>("h01"), UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 482:67] + node _T_2418 = mux(io.iccm_dma_sb_error, UInt<3>("h04"), _T_2417) @[el2_ifu_mem_ctl.scala 482:27] + perr_nxtstate <= _T_2418 @[el2_ifu_mem_ctl.scala 482:21] + node _T_2419 = or(iccm_error_start, io.ic_error_start) @[el2_ifu_mem_ctl.scala 483:44] + node _T_2420 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 483:67] + node _T_2421 = and(_T_2419, _T_2420) @[el2_ifu_mem_ctl.scala 483:65] + node _T_2422 = or(_T_2421, io.iccm_dma_sb_error) @[el2_ifu_mem_ctl.scala 483:88] + node _T_2423 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 483:114] + node _T_2424 = and(_T_2422, _T_2423) @[el2_ifu_mem_ctl.scala 483:112] + perr_state_en <= _T_2424 @[el2_ifu_mem_ctl.scala 483:21] + perr_sb_write_status <= perr_state_en @[el2_ifu_mem_ctl.scala 484:28] skip @[Conditional.scala 40:58] else : @[Conditional.scala 39:67] node _T_2425 = eq(UInt<3>("h01"), perr_state) @[Conditional.scala 37:30] when _T_2425 : @[Conditional.scala 39:67] - perr_nxtstate <= UInt<3>("h00") @[el2_ifu_mem_ctl.scala 486:21] - node _T_2426 = or(io.dec_tlu_flush_lower_wb, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 487:50] - perr_state_en <= _T_2426 @[el2_ifu_mem_ctl.scala 487:21] - node _T_2427 = and(io.dec_tlu_flush_lower_wb, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 488:56] - perr_sel_invalidate <= _T_2427 @[el2_ifu_mem_ctl.scala 488:27] + perr_nxtstate <= UInt<3>("h00") @[el2_ifu_mem_ctl.scala 487:21] + node _T_2426 = or(io.dec_tlu_flush_lower_wb, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 488:50] + perr_state_en <= _T_2426 @[el2_ifu_mem_ctl.scala 488:21] + node _T_2427 = and(io.dec_tlu_flush_lower_wb, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 489:56] + perr_sel_invalidate <= _T_2427 @[el2_ifu_mem_ctl.scala 489:27] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_2428 = eq(UInt<3>("h02"), perr_state) @[Conditional.scala 37:30] when _T_2428 : @[Conditional.scala 39:67] - node _T_2429 = and(io.dec_tlu_flush_err_wb, io.dec_tlu_flush_lower_wb) @[el2_ifu_mem_ctl.scala 491:54] - node _T_2430 = or(_T_2429, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 491:84] - node _T_2431 = bits(_T_2430, 0, 0) @[el2_ifu_mem_ctl.scala 491:115] - node _T_2432 = mux(_T_2431, UInt<3>("h00"), UInt<3>("h03")) @[el2_ifu_mem_ctl.scala 491:27] - perr_nxtstate <= _T_2432 @[el2_ifu_mem_ctl.scala 491:21] - node _T_2433 = or(io.dec_tlu_flush_lower_wb, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 492:50] - perr_state_en <= _T_2433 @[el2_ifu_mem_ctl.scala 492:21] + node _T_2429 = and(io.dec_tlu_flush_err_wb, io.dec_tlu_flush_lower_wb) @[el2_ifu_mem_ctl.scala 492:54] + node _T_2430 = or(_T_2429, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 492:84] + node _T_2431 = bits(_T_2430, 0, 0) @[el2_ifu_mem_ctl.scala 492:115] + node _T_2432 = mux(_T_2431, UInt<3>("h00"), UInt<3>("h03")) @[el2_ifu_mem_ctl.scala 492:27] + perr_nxtstate <= _T_2432 @[el2_ifu_mem_ctl.scala 492:21] + node _T_2433 = or(io.dec_tlu_flush_lower_wb, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 493:50] + perr_state_en <= _T_2433 @[el2_ifu_mem_ctl.scala 493:21] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_2434 = eq(UInt<3>("h04"), perr_state) @[Conditional.scala 37:30] when _T_2434 : @[Conditional.scala 39:67] - node _T_2435 = mux(io.dec_tlu_force_halt, UInt<3>("h00"), UInt<3>("h03")) @[el2_ifu_mem_ctl.scala 495:27] - perr_nxtstate <= _T_2435 @[el2_ifu_mem_ctl.scala 495:21] - perr_state_en <= UInt<1>("h01") @[el2_ifu_mem_ctl.scala 496:21] + node _T_2435 = mux(io.dec_tlu_force_halt, UInt<3>("h00"), UInt<3>("h03")) @[el2_ifu_mem_ctl.scala 496:27] + perr_nxtstate <= _T_2435 @[el2_ifu_mem_ctl.scala 496:21] + perr_state_en <= UInt<1>("h01") @[el2_ifu_mem_ctl.scala 497:21] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_2436 = eq(UInt<3>("h03"), perr_state) @[Conditional.scala 37:30] when _T_2436 : @[Conditional.scala 39:67] - perr_nxtstate <= UInt<3>("h00") @[el2_ifu_mem_ctl.scala 499:21] - perr_state_en <= UInt<1>("h01") @[el2_ifu_mem_ctl.scala 500:21] + perr_nxtstate <= UInt<3>("h00") @[el2_ifu_mem_ctl.scala 500:21] + perr_state_en <= UInt<1>("h01") @[el2_ifu_mem_ctl.scala 501:21] skip @[Conditional.scala 39:67] reg _T_2437 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when perr_state_en : @[Reg.scala 28:19] _T_2437 <= perr_nxtstate @[Reg.scala 28:23] skip @[Reg.scala 28:19] - perr_state <= _T_2437 @[el2_ifu_mem_ctl.scala 503:14] + perr_state <= _T_2437 @[el2_ifu_mem_ctl.scala 504:14] wire err_stop_nxtstate : UInt<2> err_stop_nxtstate <= UInt<1>("h00") wire err_stop_state_en : UInt<1> err_stop_state_en <= UInt<1>("h00") - io.iccm_correction_state <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 507:28] + io.iccm_correction_state <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 508:28] node _T_2438 = eq(UInt<2>("h00"), err_stop_state) @[Conditional.scala 37:30] when _T_2438 : @[Conditional.scala 40:58] - err_stop_nxtstate <= UInt<2>("h01") @[el2_ifu_mem_ctl.scala 511:25] - node _T_2439 = eq(perr_state, UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 512:66] - node _T_2440 = and(io.dec_tlu_flush_err_wb, _T_2439) @[el2_ifu_mem_ctl.scala 512:52] - node _T_2441 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 512:83] - node _T_2442 = and(_T_2440, _T_2441) @[el2_ifu_mem_ctl.scala 512:81] - err_stop_state_en <= _T_2442 @[el2_ifu_mem_ctl.scala 512:25] + err_stop_nxtstate <= UInt<2>("h01") @[el2_ifu_mem_ctl.scala 512:25] + node _T_2439 = eq(perr_state, UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 513:66] + node _T_2440 = and(io.dec_tlu_flush_err_wb, _T_2439) @[el2_ifu_mem_ctl.scala 513:52] + node _T_2441 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 513:83] + node _T_2442 = and(_T_2440, _T_2441) @[el2_ifu_mem_ctl.scala 513:81] + err_stop_state_en <= _T_2442 @[el2_ifu_mem_ctl.scala 513:25] skip @[Conditional.scala 40:58] else : @[Conditional.scala 39:67] node _T_2443 = eq(UInt<2>("h01"), err_stop_state) @[Conditional.scala 37:30] when _T_2443 : @[Conditional.scala 39:67] - node _T_2444 = or(io.dec_tlu_flush_lower_wb, io.dec_tlu_i0_commit_cmt) @[el2_ifu_mem_ctl.scala 515:59] - node _T_2445 = or(_T_2444, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 515:86] - node _T_2446 = bits(_T_2445, 0, 0) @[el2_ifu_mem_ctl.scala 515:117] - node _T_2447 = eq(io.ifu_fetch_val, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 516:31] - node _T_2448 = bits(io.ifu_fetch_val, 0, 0) @[el2_ifu_mem_ctl.scala 516:56] - node _T_2449 = and(_T_2448, two_byte_instr) @[el2_ifu_mem_ctl.scala 516:59] - node _T_2450 = or(_T_2447, _T_2449) @[el2_ifu_mem_ctl.scala 516:38] - node _T_2451 = bits(_T_2450, 0, 0) @[el2_ifu_mem_ctl.scala 516:83] - node _T_2452 = bits(io.ifu_fetch_val, 0, 0) @[el2_ifu_mem_ctl.scala 517:31] - node _T_2453 = bits(_T_2452, 0, 0) @[el2_ifu_mem_ctl.scala 517:41] - node _T_2454 = mux(_T_2453, UInt<2>("h02"), UInt<2>("h01")) @[el2_ifu_mem_ctl.scala 517:14] - node _T_2455 = mux(_T_2451, UInt<2>("h03"), _T_2454) @[el2_ifu_mem_ctl.scala 516:12] - node _T_2456 = mux(_T_2446, UInt<2>("h00"), _T_2455) @[el2_ifu_mem_ctl.scala 515:31] - err_stop_nxtstate <= _T_2456 @[el2_ifu_mem_ctl.scala 515:25] - node _T_2457 = or(io.dec_tlu_flush_lower_wb, io.dec_tlu_i0_commit_cmt) @[el2_ifu_mem_ctl.scala 518:54] - node _T_2458 = bits(io.ifu_fetch_val, 0, 0) @[el2_ifu_mem_ctl.scala 518:99] - node _T_2459 = or(_T_2457, _T_2458) @[el2_ifu_mem_ctl.scala 518:81] - node _T_2460 = or(_T_2459, ifu_bp_hit_taken_q_f) @[el2_ifu_mem_ctl.scala 518:103] - node _T_2461 = or(_T_2460, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 518:126] - err_stop_state_en <= _T_2461 @[el2_ifu_mem_ctl.scala 518:25] - node _T_2462 = bits(io.ifu_fetch_val, 1, 0) @[el2_ifu_mem_ctl.scala 519:43] - node _T_2463 = eq(_T_2462, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 519:48] - node _T_2464 = bits(io.ifu_fetch_val, 0, 0) @[el2_ifu_mem_ctl.scala 519:75] - node _T_2465 = and(_T_2464, two_byte_instr) @[el2_ifu_mem_ctl.scala 519:79] - node _T_2466 = or(_T_2463, _T_2465) @[el2_ifu_mem_ctl.scala 519:56] - node _T_2467 = or(io.exu_flush_final, io.dec_tlu_i0_commit_cmt) @[el2_ifu_mem_ctl.scala 519:122] - node _T_2468 = eq(_T_2467, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 519:101] - node _T_2469 = and(_T_2466, _T_2468) @[el2_ifu_mem_ctl.scala 519:99] - err_stop_fetch <= _T_2469 @[el2_ifu_mem_ctl.scala 519:22] - io.iccm_correction_state <= UInt<1>("h01") @[el2_ifu_mem_ctl.scala 520:32] + node _T_2444 = or(io.dec_tlu_flush_lower_wb, io.dec_tlu_i0_commit_cmt) @[el2_ifu_mem_ctl.scala 516:59] + node _T_2445 = or(_T_2444, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 516:86] + node _T_2446 = bits(_T_2445, 0, 0) @[el2_ifu_mem_ctl.scala 516:117] + node _T_2447 = eq(io.ifu_fetch_val, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 517:31] + node _T_2448 = bits(io.ifu_fetch_val, 0, 0) @[el2_ifu_mem_ctl.scala 517:56] + node _T_2449 = and(_T_2448, two_byte_instr) @[el2_ifu_mem_ctl.scala 517:59] + node _T_2450 = or(_T_2447, _T_2449) @[el2_ifu_mem_ctl.scala 517:38] + node _T_2451 = bits(_T_2450, 0, 0) @[el2_ifu_mem_ctl.scala 517:83] + node _T_2452 = bits(io.ifu_fetch_val, 0, 0) @[el2_ifu_mem_ctl.scala 518:31] + node _T_2453 = bits(_T_2452, 0, 0) @[el2_ifu_mem_ctl.scala 518:41] + node _T_2454 = mux(_T_2453, UInt<2>("h02"), UInt<2>("h01")) @[el2_ifu_mem_ctl.scala 518:14] + node _T_2455 = mux(_T_2451, UInt<2>("h03"), _T_2454) @[el2_ifu_mem_ctl.scala 517:12] + node _T_2456 = mux(_T_2446, UInt<2>("h00"), _T_2455) @[el2_ifu_mem_ctl.scala 516:31] + err_stop_nxtstate <= _T_2456 @[el2_ifu_mem_ctl.scala 516:25] + node _T_2457 = or(io.dec_tlu_flush_lower_wb, io.dec_tlu_i0_commit_cmt) @[el2_ifu_mem_ctl.scala 519:54] + node _T_2458 = bits(io.ifu_fetch_val, 0, 0) @[el2_ifu_mem_ctl.scala 519:99] + node _T_2459 = or(_T_2457, _T_2458) @[el2_ifu_mem_ctl.scala 519:81] + node _T_2460 = or(_T_2459, ifu_bp_hit_taken_q_f) @[el2_ifu_mem_ctl.scala 519:103] + node _T_2461 = or(_T_2460, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 519:126] + err_stop_state_en <= _T_2461 @[el2_ifu_mem_ctl.scala 519:25] + node _T_2462 = bits(io.ifu_fetch_val, 1, 0) @[el2_ifu_mem_ctl.scala 520:43] + node _T_2463 = eq(_T_2462, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 520:48] + node _T_2464 = bits(io.ifu_fetch_val, 0, 0) @[el2_ifu_mem_ctl.scala 520:75] + node _T_2465 = and(_T_2464, two_byte_instr) @[el2_ifu_mem_ctl.scala 520:79] + node _T_2466 = or(_T_2463, _T_2465) @[el2_ifu_mem_ctl.scala 520:56] + node _T_2467 = or(io.exu_flush_final, io.dec_tlu_i0_commit_cmt) @[el2_ifu_mem_ctl.scala 520:122] + node _T_2468 = eq(_T_2467, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 520:101] + node _T_2469 = and(_T_2466, _T_2468) @[el2_ifu_mem_ctl.scala 520:99] + err_stop_fetch <= _T_2469 @[el2_ifu_mem_ctl.scala 520:22] + io.iccm_correction_state <= UInt<1>("h01") @[el2_ifu_mem_ctl.scala 521:32] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_2470 = eq(UInt<2>("h02"), err_stop_state) @[Conditional.scala 37:30] when _T_2470 : @[Conditional.scala 39:67] - node _T_2471 = or(io.dec_tlu_flush_lower_wb, io.dec_tlu_i0_commit_cmt) @[el2_ifu_mem_ctl.scala 523:59] - node _T_2472 = or(_T_2471, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 523:86] - node _T_2473 = bits(_T_2472, 0, 0) @[el2_ifu_mem_ctl.scala 523:111] - node _T_2474 = bits(io.ifu_fetch_val, 0, 0) @[el2_ifu_mem_ctl.scala 524:46] - node _T_2475 = bits(_T_2474, 0, 0) @[el2_ifu_mem_ctl.scala 524:50] - node _T_2476 = mux(_T_2475, UInt<2>("h03"), UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 524:29] - node _T_2477 = mux(_T_2473, UInt<2>("h00"), _T_2476) @[el2_ifu_mem_ctl.scala 523:31] - err_stop_nxtstate <= _T_2477 @[el2_ifu_mem_ctl.scala 523:25] - node _T_2478 = or(io.dec_tlu_flush_lower_wb, io.dec_tlu_i0_commit_cmt) @[el2_ifu_mem_ctl.scala 525:54] - node _T_2479 = bits(io.ifu_fetch_val, 0, 0) @[el2_ifu_mem_ctl.scala 525:99] - node _T_2480 = or(_T_2478, _T_2479) @[el2_ifu_mem_ctl.scala 525:81] - node _T_2481 = or(_T_2480, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 525:103] - err_stop_state_en <= _T_2481 @[el2_ifu_mem_ctl.scala 525:25] - node _T_2482 = bits(io.ifu_fetch_val, 0, 0) @[el2_ifu_mem_ctl.scala 526:41] - node _T_2483 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 526:47] - node _T_2484 = and(_T_2482, _T_2483) @[el2_ifu_mem_ctl.scala 526:45] - node _T_2485 = eq(io.dec_tlu_i0_commit_cmt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 526:69] - node _T_2486 = and(_T_2484, _T_2485) @[el2_ifu_mem_ctl.scala 526:67] - err_stop_fetch <= _T_2486 @[el2_ifu_mem_ctl.scala 526:22] - io.iccm_correction_state <= UInt<1>("h01") @[el2_ifu_mem_ctl.scala 527:32] + node _T_2471 = or(io.dec_tlu_flush_lower_wb, io.dec_tlu_i0_commit_cmt) @[el2_ifu_mem_ctl.scala 524:59] + node _T_2472 = or(_T_2471, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 524:86] + node _T_2473 = bits(_T_2472, 0, 0) @[el2_ifu_mem_ctl.scala 524:111] + node _T_2474 = bits(io.ifu_fetch_val, 0, 0) @[el2_ifu_mem_ctl.scala 525:46] + node _T_2475 = bits(_T_2474, 0, 0) @[el2_ifu_mem_ctl.scala 525:50] + node _T_2476 = mux(_T_2475, UInt<2>("h03"), UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 525:29] + node _T_2477 = mux(_T_2473, UInt<2>("h00"), _T_2476) @[el2_ifu_mem_ctl.scala 524:31] + err_stop_nxtstate <= _T_2477 @[el2_ifu_mem_ctl.scala 524:25] + node _T_2478 = or(io.dec_tlu_flush_lower_wb, io.dec_tlu_i0_commit_cmt) @[el2_ifu_mem_ctl.scala 526:54] + node _T_2479 = bits(io.ifu_fetch_val, 0, 0) @[el2_ifu_mem_ctl.scala 526:99] + node _T_2480 = or(_T_2478, _T_2479) @[el2_ifu_mem_ctl.scala 526:81] + node _T_2481 = or(_T_2480, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 526:103] + err_stop_state_en <= _T_2481 @[el2_ifu_mem_ctl.scala 526:25] + node _T_2482 = bits(io.ifu_fetch_val, 0, 0) @[el2_ifu_mem_ctl.scala 527:41] + node _T_2483 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 527:47] + node _T_2484 = and(_T_2482, _T_2483) @[el2_ifu_mem_ctl.scala 527:45] + node _T_2485 = eq(io.dec_tlu_i0_commit_cmt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 527:69] + node _T_2486 = and(_T_2484, _T_2485) @[el2_ifu_mem_ctl.scala 527:67] + err_stop_fetch <= _T_2486 @[el2_ifu_mem_ctl.scala 527:22] + io.iccm_correction_state <= UInt<1>("h01") @[el2_ifu_mem_ctl.scala 528:32] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_2487 = eq(UInt<2>("h03"), err_stop_state) @[Conditional.scala 37:30] when _T_2487 : @[Conditional.scala 39:67] - node _T_2488 = eq(io.dec_tlu_flush_err_wb, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 530:62] - node _T_2489 = and(io.dec_tlu_flush_lower_wb, _T_2488) @[el2_ifu_mem_ctl.scala 530:60] - node _T_2490 = or(_T_2489, io.dec_tlu_i0_commit_cmt) @[el2_ifu_mem_ctl.scala 530:88] - node _T_2491 = or(_T_2490, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 530:115] - node _T_2492 = bits(_T_2491, 0, 0) @[el2_ifu_mem_ctl.scala 530:140] - node _T_2493 = bits(io.dec_tlu_flush_err_wb, 0, 0) @[el2_ifu_mem_ctl.scala 531:60] - node _T_2494 = mux(_T_2493, UInt<2>("h01"), UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 531:29] - node _T_2495 = mux(_T_2492, UInt<2>("h00"), _T_2494) @[el2_ifu_mem_ctl.scala 530:31] - err_stop_nxtstate <= _T_2495 @[el2_ifu_mem_ctl.scala 530:25] - node _T_2496 = or(io.dec_tlu_flush_lower_wb, io.dec_tlu_i0_commit_cmt) @[el2_ifu_mem_ctl.scala 532:54] - node _T_2497 = or(_T_2496, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 532:81] - err_stop_state_en <= _T_2497 @[el2_ifu_mem_ctl.scala 532:25] - err_stop_fetch <= UInt<1>("h01") @[el2_ifu_mem_ctl.scala 533:22] - io.iccm_correction_state <= UInt<1>("h01") @[el2_ifu_mem_ctl.scala 534:32] + node _T_2488 = eq(io.dec_tlu_flush_err_wb, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 531:62] + node _T_2489 = and(io.dec_tlu_flush_lower_wb, _T_2488) @[el2_ifu_mem_ctl.scala 531:60] + node _T_2490 = or(_T_2489, io.dec_tlu_i0_commit_cmt) @[el2_ifu_mem_ctl.scala 531:88] + node _T_2491 = or(_T_2490, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 531:115] + node _T_2492 = bits(_T_2491, 0, 0) @[el2_ifu_mem_ctl.scala 531:140] + node _T_2493 = bits(io.dec_tlu_flush_err_wb, 0, 0) @[el2_ifu_mem_ctl.scala 532:60] + node _T_2494 = mux(_T_2493, UInt<2>("h01"), UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 532:29] + node _T_2495 = mux(_T_2492, UInt<2>("h00"), _T_2494) @[el2_ifu_mem_ctl.scala 531:31] + err_stop_nxtstate <= _T_2495 @[el2_ifu_mem_ctl.scala 531:25] + node _T_2496 = or(io.dec_tlu_flush_lower_wb, io.dec_tlu_i0_commit_cmt) @[el2_ifu_mem_ctl.scala 533:54] + node _T_2497 = or(_T_2496, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 533:81] + err_stop_state_en <= _T_2497 @[el2_ifu_mem_ctl.scala 533:25] + err_stop_fetch <= UInt<1>("h01") @[el2_ifu_mem_ctl.scala 534:22] + io.iccm_correction_state <= UInt<1>("h01") @[el2_ifu_mem_ctl.scala 535:32] skip @[Conditional.scala 39:67] reg _T_2498 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when err_stop_state_en : @[Reg.scala 28:19] _T_2498 <= err_stop_nxtstate @[Reg.scala 28:23] skip @[Reg.scala 28:19] - err_stop_state <= _T_2498 @[el2_ifu_mem_ctl.scala 537:18] - bus_ifu_bus_clk_en <= io.ifu_bus_clk_en @[el2_ifu_mem_ctl.scala 538:22] - reg bus_ifu_bus_clk_en_ff : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 539:61] - bus_ifu_bus_clk_en_ff <= bus_ifu_bus_clk_en @[el2_ifu_mem_ctl.scala 539:61] - reg _T_2499 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 540:52] - _T_2499 <= scnd_miss_req_in @[el2_ifu_mem_ctl.scala 540:52] - scnd_miss_req_q <= _T_2499 @[el2_ifu_mem_ctl.scala 540:19] - reg scnd_miss_req_ff2 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 541:57] - scnd_miss_req_ff2 <= scnd_miss_req @[el2_ifu_mem_ctl.scala 541:57] - node _T_2500 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 542:39] - node _T_2501 = and(scnd_miss_req_q, _T_2500) @[el2_ifu_mem_ctl.scala 542:36] - scnd_miss_req <= _T_2501 @[el2_ifu_mem_ctl.scala 542:17] + err_stop_state <= _T_2498 @[el2_ifu_mem_ctl.scala 538:18] + bus_ifu_bus_clk_en <= io.ifu_bus_clk_en @[el2_ifu_mem_ctl.scala 539:22] + reg bus_ifu_bus_clk_en_ff : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 540:61] + bus_ifu_bus_clk_en_ff <= bus_ifu_bus_clk_en @[el2_ifu_mem_ctl.scala 540:61] + reg _T_2499 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 541:52] + _T_2499 <= scnd_miss_req_in @[el2_ifu_mem_ctl.scala 541:52] + scnd_miss_req_q <= _T_2499 @[el2_ifu_mem_ctl.scala 541:19] + reg scnd_miss_req_ff2 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 542:57] + scnd_miss_req_ff2 <= scnd_miss_req @[el2_ifu_mem_ctl.scala 542:57] + node _T_2500 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 543:39] + node _T_2501 = and(scnd_miss_req_q, _T_2500) @[el2_ifu_mem_ctl.scala 543:36] + scnd_miss_req <= _T_2501 @[el2_ifu_mem_ctl.scala 543:17] wire bus_cmd_req_hold : UInt<1> bus_cmd_req_hold <= UInt<1>("h00") wire ifu_bus_cmd_valid : UInt<1> @@ -3484,49 +3484,49 @@ circuit el2_ifu_mem_ctl : bus_cmd_beat_count <= UInt<1>("h00") wire ifu_bus_cmd_ready : UInt<1> ifu_bus_cmd_ready <= UInt<1>("h00") - node _T_2502 = or(ic_act_miss_f, bus_cmd_req_hold) @[el2_ifu_mem_ctl.scala 547:45] - node _T_2503 = or(_T_2502, ifu_bus_cmd_valid) @[el2_ifu_mem_ctl.scala 547:64] - node _T_2504 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 547:87] - node _T_2505 = and(_T_2503, _T_2504) @[el2_ifu_mem_ctl.scala 547:85] + node _T_2502 = or(ic_act_miss_f, bus_cmd_req_hold) @[el2_ifu_mem_ctl.scala 548:45] + node _T_2503 = or(_T_2502, ifu_bus_cmd_valid) @[el2_ifu_mem_ctl.scala 548:64] + node _T_2504 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 548:87] + node _T_2505 = and(_T_2503, _T_2504) @[el2_ifu_mem_ctl.scala 548:85] node _T_2506 = mux(UInt<1>("h01"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_2507 = eq(bus_cmd_beat_count, _T_2506) @[el2_ifu_mem_ctl.scala 547:133] - node _T_2508 = and(_T_2507, ifu_bus_cmd_valid) @[el2_ifu_mem_ctl.scala 547:164] - node _T_2509 = and(_T_2508, ifu_bus_cmd_ready) @[el2_ifu_mem_ctl.scala 547:184] - node _T_2510 = and(_T_2509, miss_pending) @[el2_ifu_mem_ctl.scala 547:204] - node _T_2511 = eq(_T_2510, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 547:112] - node ifc_bus_ic_req_ff_in = and(_T_2505, _T_2511) @[el2_ifu_mem_ctl.scala 547:110] - node _T_2512 = or(bus_ifu_bus_clk_en, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 548:80] + node _T_2507 = eq(bus_cmd_beat_count, _T_2506) @[el2_ifu_mem_ctl.scala 548:133] + node _T_2508 = and(_T_2507, ifu_bus_cmd_valid) @[el2_ifu_mem_ctl.scala 548:164] + node _T_2509 = and(_T_2508, ifu_bus_cmd_ready) @[el2_ifu_mem_ctl.scala 548:184] + node _T_2510 = and(_T_2509, miss_pending) @[el2_ifu_mem_ctl.scala 548:204] + node _T_2511 = eq(_T_2510, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 548:112] + node ifc_bus_ic_req_ff_in = and(_T_2505, _T_2511) @[el2_ifu_mem_ctl.scala 548:110] + node _T_2512 = or(bus_ifu_bus_clk_en, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 549:80] reg _T_2513 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_2512 : @[Reg.scala 28:19] _T_2513 <= ifc_bus_ic_req_ff_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ifu_bus_cmd_valid <= _T_2513 @[el2_ifu_mem_ctl.scala 548:21] + ifu_bus_cmd_valid <= _T_2513 @[el2_ifu_mem_ctl.scala 549:21] wire bus_cmd_sent : UInt<1> bus_cmd_sent <= UInt<1>("h00") - node _T_2514 = or(ic_act_miss_f, bus_cmd_req_hold) @[el2_ifu_mem_ctl.scala 550:39] - node _T_2515 = eq(bus_cmd_sent, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 550:61] - node _T_2516 = and(_T_2514, _T_2515) @[el2_ifu_mem_ctl.scala 550:59] - node _T_2517 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 550:77] - node bus_cmd_req_in = and(_T_2516, _T_2517) @[el2_ifu_mem_ctl.scala 550:75] - reg _T_2518 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 551:49] - _T_2518 <= bus_cmd_req_in @[el2_ifu_mem_ctl.scala 551:49] - bus_cmd_sent <= _T_2518 @[el2_ifu_mem_ctl.scala 551:16] - io.ifu_axi_arvalid <= ifu_bus_cmd_valid @[el2_ifu_mem_ctl.scala 553:22] + node _T_2514 = or(ic_act_miss_f, bus_cmd_req_hold) @[el2_ifu_mem_ctl.scala 551:39] + node _T_2515 = eq(bus_cmd_sent, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 551:61] + node _T_2516 = and(_T_2514, _T_2515) @[el2_ifu_mem_ctl.scala 551:59] + node _T_2517 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 551:77] + node bus_cmd_req_in = and(_T_2516, _T_2517) @[el2_ifu_mem_ctl.scala 551:75] + reg _T_2518 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 552:49] + _T_2518 <= bus_cmd_req_in @[el2_ifu_mem_ctl.scala 552:49] + bus_cmd_sent <= _T_2518 @[el2_ifu_mem_ctl.scala 552:16] + io.ifu_axi_arvalid <= ifu_bus_cmd_valid @[el2_ifu_mem_ctl.scala 554:22] node _T_2519 = bits(ifu_bus_cmd_valid, 0, 0) @[Bitwise.scala 72:15] node _T_2520 = mux(_T_2519, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_2521 = and(bus_rd_addr_count, _T_2520) @[el2_ifu_mem_ctl.scala 554:40] - io.ifu_axi_arid <= _T_2521 @[el2_ifu_mem_ctl.scala 554:19] + node _T_2521 = and(bus_rd_addr_count, _T_2520) @[el2_ifu_mem_ctl.scala 555:40] + io.ifu_axi_arid <= _T_2521 @[el2_ifu_mem_ctl.scala 555:19] node _T_2522 = cat(ifu_ic_req_addr_f, UInt<3>("h00")) @[Cat.scala 29:58] node _T_2523 = bits(ifu_bus_cmd_valid, 0, 0) @[Bitwise.scala 72:15] node _T_2524 = mux(_T_2523, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_2525 = and(_T_2522, _T_2524) @[el2_ifu_mem_ctl.scala 555:57] - io.ifu_axi_araddr <= _T_2525 @[el2_ifu_mem_ctl.scala 555:21] - io.ifu_axi_arsize <= UInt<3>("h03") @[el2_ifu_mem_ctl.scala 556:21] - io.ifu_axi_arcache <= UInt<4>("h0f") @[el2_ifu_mem_ctl.scala 557:22] - node _T_2526 = bits(ifu_ic_req_addr_f, 28, 25) @[el2_ifu_mem_ctl.scala 558:43] - io.ifu_axi_arregion <= _T_2526 @[el2_ifu_mem_ctl.scala 558:23] - io.ifu_axi_arburst <= UInt<1>("h01") @[el2_ifu_mem_ctl.scala 559:22] - io.ifu_axi_rready <= UInt<1>("h01") @[el2_ifu_mem_ctl.scala 560:21] + node _T_2525 = and(_T_2522, _T_2524) @[el2_ifu_mem_ctl.scala 556:57] + io.ifu_axi_araddr <= _T_2525 @[el2_ifu_mem_ctl.scala 556:21] + io.ifu_axi_arsize <= UInt<3>("h03") @[el2_ifu_mem_ctl.scala 557:21] + io.ifu_axi_arcache <= UInt<4>("h0f") @[el2_ifu_mem_ctl.scala 558:22] + node _T_2526 = bits(ifu_ic_req_addr_f, 28, 25) @[el2_ifu_mem_ctl.scala 559:43] + io.ifu_axi_arregion <= _T_2526 @[el2_ifu_mem_ctl.scala 559:23] + io.ifu_axi_arburst <= UInt<1>("h01") @[el2_ifu_mem_ctl.scala 560:22] + io.ifu_axi_rready <= UInt<1>("h01") @[el2_ifu_mem_ctl.scala 561:21] reg ifu_bus_arready_unq_ff : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bus_ifu_bus_clk_en : @[Reg.scala 28:19] ifu_bus_arready_unq_ff <= io.ifu_axi_arready @[Reg.scala 28:23] @@ -3547,42 +3547,42 @@ circuit el2_ifu_mem_ctl : when bus_ifu_bus_clk_en : @[Reg.scala 28:19] _T_2527 <= io.ifu_axi_rdata @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ifu_bus_rdata_ff <= _T_2527 @[el2_ifu_mem_ctl.scala 570:20] + ifu_bus_rdata_ff <= _T_2527 @[el2_ifu_mem_ctl.scala 571:20] reg _T_2528 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bus_ifu_bus_clk_en : @[Reg.scala 28:19] _T_2528 <= io.ifu_axi_rid @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ifu_bus_rid_ff <= _T_2528 @[el2_ifu_mem_ctl.scala 571:18] - ifu_bus_cmd_ready <= io.ifu_axi_arready @[el2_ifu_mem_ctl.scala 572:21] - ifu_bus_rsp_valid <= io.ifu_axi_rvalid @[el2_ifu_mem_ctl.scala 573:21] - ifu_bus_rsp_ready <= io.ifu_axi_rready @[el2_ifu_mem_ctl.scala 574:21] - ifu_bus_rsp_tag <= io.ifu_axi_rid @[el2_ifu_mem_ctl.scala 575:19] - ic_miss_buff_data_in <= io.ifu_axi_rdata @[el2_ifu_mem_ctl.scala 576:21] - node ifu_bus_rvalid = and(ifu_bus_rsp_valid, bus_ifu_bus_clk_en) @[el2_ifu_mem_ctl.scala 578:42] - node ifu_bus_arready = and(io.ifu_axi_arready, bus_ifu_bus_clk_en) @[el2_ifu_mem_ctl.scala 579:45] - node ifu_bus_arready_ff = and(ifu_bus_arready_unq_ff, bus_ifu_bus_clk_en_ff) @[el2_ifu_mem_ctl.scala 580:51] - node ifu_bus_rvalid_ff = and(ifu_bus_rvalid_unq_ff, bus_ifu_bus_clk_en_ff) @[el2_ifu_mem_ctl.scala 581:49] - node _T_2529 = and(io.ifu_axi_arvalid, ifu_bus_arready) @[el2_ifu_mem_ctl.scala 582:35] - node _T_2530 = and(_T_2529, miss_pending) @[el2_ifu_mem_ctl.scala 582:53] - node _T_2531 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 582:70] - node _T_2532 = and(_T_2530, _T_2531) @[el2_ifu_mem_ctl.scala 582:68] - bus_cmd_sent <= _T_2532 @[el2_ifu_mem_ctl.scala 582:16] + ifu_bus_rid_ff <= _T_2528 @[el2_ifu_mem_ctl.scala 572:18] + ifu_bus_cmd_ready <= io.ifu_axi_arready @[el2_ifu_mem_ctl.scala 573:21] + ifu_bus_rsp_valid <= io.ifu_axi_rvalid @[el2_ifu_mem_ctl.scala 574:21] + ifu_bus_rsp_ready <= io.ifu_axi_rready @[el2_ifu_mem_ctl.scala 575:21] + ifu_bus_rsp_tag <= io.ifu_axi_rid @[el2_ifu_mem_ctl.scala 576:19] + ic_miss_buff_data_in <= io.ifu_axi_rdata @[el2_ifu_mem_ctl.scala 577:21] + node ifu_bus_rvalid = and(ifu_bus_rsp_valid, bus_ifu_bus_clk_en) @[el2_ifu_mem_ctl.scala 579:42] + node ifu_bus_arready = and(io.ifu_axi_arready, bus_ifu_bus_clk_en) @[el2_ifu_mem_ctl.scala 580:45] + node ifu_bus_arready_ff = and(ifu_bus_arready_unq_ff, bus_ifu_bus_clk_en_ff) @[el2_ifu_mem_ctl.scala 581:51] + node ifu_bus_rvalid_ff = and(ifu_bus_rvalid_unq_ff, bus_ifu_bus_clk_en_ff) @[el2_ifu_mem_ctl.scala 582:49] + node _T_2529 = and(io.ifu_axi_arvalid, ifu_bus_arready) @[el2_ifu_mem_ctl.scala 583:35] + node _T_2530 = and(_T_2529, miss_pending) @[el2_ifu_mem_ctl.scala 583:53] + node _T_2531 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 583:70] + node _T_2532 = and(_T_2530, _T_2531) @[el2_ifu_mem_ctl.scala 583:68] + bus_cmd_sent <= _T_2532 @[el2_ifu_mem_ctl.scala 583:16] wire bus_last_data_beat : UInt<1> bus_last_data_beat <= UInt<1>("h00") - node _T_2533 = eq(bus_last_data_beat, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 584:50] - node _T_2534 = and(bus_ifu_wr_en_ff, _T_2533) @[el2_ifu_mem_ctl.scala 584:48] - node _T_2535 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 584:72] - node bus_inc_data_beat_cnt = and(_T_2534, _T_2535) @[el2_ifu_mem_ctl.scala 584:70] - node _T_2536 = and(bus_ifu_wr_en_ff, bus_last_data_beat) @[el2_ifu_mem_ctl.scala 585:68] - node _T_2537 = or(ic_act_miss_f, _T_2536) @[el2_ifu_mem_ctl.scala 585:48] - node bus_reset_data_beat_cnt = or(_T_2537, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 585:91] - node _T_2538 = eq(bus_inc_data_beat_cnt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 586:32] - node _T_2539 = eq(bus_reset_data_beat_cnt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 586:57] - node bus_hold_data_beat_cnt = and(_T_2538, _T_2539) @[el2_ifu_mem_ctl.scala 586:55] + node _T_2533 = eq(bus_last_data_beat, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 585:50] + node _T_2534 = and(bus_ifu_wr_en_ff, _T_2533) @[el2_ifu_mem_ctl.scala 585:48] + node _T_2535 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 585:72] + node bus_inc_data_beat_cnt = and(_T_2534, _T_2535) @[el2_ifu_mem_ctl.scala 585:70] + node _T_2536 = and(bus_ifu_wr_en_ff, bus_last_data_beat) @[el2_ifu_mem_ctl.scala 586:68] + node _T_2537 = or(ic_act_miss_f, _T_2536) @[el2_ifu_mem_ctl.scala 586:48] + node bus_reset_data_beat_cnt = or(_T_2537, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 586:91] + node _T_2538 = eq(bus_inc_data_beat_cnt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 587:32] + node _T_2539 = eq(bus_reset_data_beat_cnt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 587:57] + node bus_hold_data_beat_cnt = and(_T_2538, _T_2539) @[el2_ifu_mem_ctl.scala 587:55] wire bus_data_beat_count : UInt<3> bus_data_beat_count <= UInt<1>("h00") - node _T_2540 = add(bus_data_beat_count, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 588:115] - node _T_2541 = tail(_T_2540, 1) @[el2_ifu_mem_ctl.scala 588:115] + node _T_2540 = add(bus_data_beat_count, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 589:115] + node _T_2541 = tail(_T_2540, 1) @[el2_ifu_mem_ctl.scala 589:115] node _T_2542 = mux(bus_reset_data_beat_cnt, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_2543 = mux(bus_inc_data_beat_cnt, _T_2541, UInt<1>("h00")) @[Mux.scala 27:72] node _T_2544 = mux(bus_hold_data_beat_cnt, bus_data_beat_count, UInt<1>("h00")) @[Mux.scala 27:72] @@ -3590,52 +3590,52 @@ circuit el2_ifu_mem_ctl : node _T_2546 = or(_T_2545, _T_2544) @[Mux.scala 27:72] wire _T_2547 : UInt<3> @[Mux.scala 27:72] _T_2547 <= _T_2546 @[Mux.scala 27:72] - bus_new_data_beat_count <= _T_2547 @[el2_ifu_mem_ctl.scala 588:27] - reg _T_2548 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 589:56] - _T_2548 <= bus_new_data_beat_count @[el2_ifu_mem_ctl.scala 589:56] - bus_data_beat_count <= _T_2548 @[el2_ifu_mem_ctl.scala 589:23] - node _T_2549 = and(bus_ifu_wr_en_ff, bus_last_data_beat) @[el2_ifu_mem_ctl.scala 590:49] - node _T_2550 = eq(scnd_miss_req, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 590:73] - node _T_2551 = and(_T_2549, _T_2550) @[el2_ifu_mem_ctl.scala 590:71] - node _T_2552 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 590:116] - node _T_2553 = and(last_data_recieved_ff, _T_2552) @[el2_ifu_mem_ctl.scala 590:114] - node last_data_recieved_in = or(_T_2551, _T_2553) @[el2_ifu_mem_ctl.scala 590:89] - reg _T_2554 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 591:58] - _T_2554 <= last_data_recieved_in @[el2_ifu_mem_ctl.scala 591:58] - last_data_recieved_ff <= _T_2554 @[el2_ifu_mem_ctl.scala 591:25] - node _T_2555 = eq(miss_pending, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 593:35] - node _T_2556 = bits(imb_ff, 4, 2) @[el2_ifu_mem_ctl.scala 593:56] - node _T_2557 = bits(imb_scnd_ff, 4, 2) @[el2_ifu_mem_ctl.scala 594:39] - node _T_2558 = add(bus_rd_addr_count, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 595:45] - node _T_2559 = tail(_T_2558, 1) @[el2_ifu_mem_ctl.scala 595:45] - node _T_2560 = mux(bus_cmd_sent, _T_2559, bus_rd_addr_count) @[el2_ifu_mem_ctl.scala 595:12] - node _T_2561 = mux(scnd_miss_req_q, _T_2557, _T_2560) @[el2_ifu_mem_ctl.scala 594:10] - node bus_new_rd_addr_count = mux(_T_2555, _T_2556, _T_2561) @[el2_ifu_mem_ctl.scala 593:34] - node _T_2562 = or(bus_ifu_bus_clk_en, ic_act_miss_f) @[el2_ifu_mem_ctl.scala 596:81] - node _T_2563 = or(_T_2562, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 596:97] + bus_new_data_beat_count <= _T_2547 @[el2_ifu_mem_ctl.scala 589:27] + reg _T_2548 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 590:56] + _T_2548 <= bus_new_data_beat_count @[el2_ifu_mem_ctl.scala 590:56] + bus_data_beat_count <= _T_2548 @[el2_ifu_mem_ctl.scala 590:23] + node _T_2549 = and(bus_ifu_wr_en_ff, bus_last_data_beat) @[el2_ifu_mem_ctl.scala 591:49] + node _T_2550 = eq(scnd_miss_req, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 591:73] + node _T_2551 = and(_T_2549, _T_2550) @[el2_ifu_mem_ctl.scala 591:71] + node _T_2552 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 591:116] + node _T_2553 = and(last_data_recieved_ff, _T_2552) @[el2_ifu_mem_ctl.scala 591:114] + node last_data_recieved_in = or(_T_2551, _T_2553) @[el2_ifu_mem_ctl.scala 591:89] + reg _T_2554 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 592:58] + _T_2554 <= last_data_recieved_in @[el2_ifu_mem_ctl.scala 592:58] + last_data_recieved_ff <= _T_2554 @[el2_ifu_mem_ctl.scala 592:25] + node _T_2555 = eq(miss_pending, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 594:35] + node _T_2556 = bits(imb_ff, 4, 2) @[el2_ifu_mem_ctl.scala 594:56] + node _T_2557 = bits(imb_scnd_ff, 4, 2) @[el2_ifu_mem_ctl.scala 595:39] + node _T_2558 = add(bus_rd_addr_count, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 596:45] + node _T_2559 = tail(_T_2558, 1) @[el2_ifu_mem_ctl.scala 596:45] + node _T_2560 = mux(bus_cmd_sent, _T_2559, bus_rd_addr_count) @[el2_ifu_mem_ctl.scala 596:12] + node _T_2561 = mux(scnd_miss_req_q, _T_2557, _T_2560) @[el2_ifu_mem_ctl.scala 595:10] + node bus_new_rd_addr_count = mux(_T_2555, _T_2556, _T_2561) @[el2_ifu_mem_ctl.scala 594:34] + node _T_2562 = or(bus_ifu_bus_clk_en, ic_act_miss_f) @[el2_ifu_mem_ctl.scala 597:81] + node _T_2563 = or(_T_2562, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 597:97] reg _T_2564 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_2563 : @[Reg.scala 28:19] _T_2564 <= bus_new_rd_addr_count @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bus_rd_addr_count <= _T_2564 @[el2_ifu_mem_ctl.scala 596:21] - node _T_2565 = and(ifu_bus_cmd_valid, ifu_bus_cmd_ready) @[el2_ifu_mem_ctl.scala 598:48] - node _T_2566 = and(_T_2565, miss_pending) @[el2_ifu_mem_ctl.scala 598:68] - node _T_2567 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 598:85] - node bus_inc_cmd_beat_cnt = and(_T_2566, _T_2567) @[el2_ifu_mem_ctl.scala 598:83] - node _T_2568 = eq(uncacheable_miss_in, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 599:51] - node _T_2569 = and(ic_act_miss_f, _T_2568) @[el2_ifu_mem_ctl.scala 599:49] - node bus_reset_cmd_beat_cnt_0 = or(_T_2569, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 599:73] - node bus_reset_cmd_beat_cnt_secondlast = and(ic_act_miss_f, uncacheable_miss_in) @[el2_ifu_mem_ctl.scala 600:57] - node _T_2570 = eq(bus_inc_cmd_beat_cnt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 601:31] - node _T_2571 = or(ic_act_miss_f, scnd_miss_req) @[el2_ifu_mem_ctl.scala 601:71] - node _T_2572 = or(_T_2571, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 601:87] - node _T_2573 = eq(_T_2572, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 601:55] - node bus_hold_cmd_beat_cnt = and(_T_2570, _T_2573) @[el2_ifu_mem_ctl.scala 601:53] - node _T_2574 = or(bus_inc_cmd_beat_cnt, ic_act_miss_f) @[el2_ifu_mem_ctl.scala 602:46] - node bus_cmd_beat_en = or(_T_2574, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 602:62] - node _T_2575 = bits(bus_reset_cmd_beat_cnt_secondlast, 0, 0) @[el2_ifu_mem_ctl.scala 603:107] - node _T_2576 = add(bus_cmd_beat_count, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 604:46] - node _T_2577 = tail(_T_2576, 1) @[el2_ifu_mem_ctl.scala 604:46] + bus_rd_addr_count <= _T_2564 @[el2_ifu_mem_ctl.scala 597:21] + node _T_2565 = and(ifu_bus_cmd_valid, ifu_bus_cmd_ready) @[el2_ifu_mem_ctl.scala 599:48] + node _T_2566 = and(_T_2565, miss_pending) @[el2_ifu_mem_ctl.scala 599:68] + node _T_2567 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 599:85] + node bus_inc_cmd_beat_cnt = and(_T_2566, _T_2567) @[el2_ifu_mem_ctl.scala 599:83] + node _T_2568 = eq(uncacheable_miss_in, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 600:51] + node _T_2569 = and(ic_act_miss_f, _T_2568) @[el2_ifu_mem_ctl.scala 600:49] + node bus_reset_cmd_beat_cnt_0 = or(_T_2569, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 600:73] + node bus_reset_cmd_beat_cnt_secondlast = and(ic_act_miss_f, uncacheable_miss_in) @[el2_ifu_mem_ctl.scala 601:57] + node _T_2570 = eq(bus_inc_cmd_beat_cnt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 602:31] + node _T_2571 = or(ic_act_miss_f, scnd_miss_req) @[el2_ifu_mem_ctl.scala 602:71] + node _T_2572 = or(_T_2571, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 602:87] + node _T_2573 = eq(_T_2572, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 602:55] + node bus_hold_cmd_beat_cnt = and(_T_2570, _T_2573) @[el2_ifu_mem_ctl.scala 602:53] + node _T_2574 = or(bus_inc_cmd_beat_cnt, ic_act_miss_f) @[el2_ifu_mem_ctl.scala 603:46] + node bus_cmd_beat_en = or(_T_2574, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 603:62] + node _T_2575 = bits(bus_reset_cmd_beat_cnt_secondlast, 0, 0) @[el2_ifu_mem_ctl.scala 604:107] + node _T_2576 = add(bus_cmd_beat_count, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 605:46] + node _T_2577 = tail(_T_2576, 1) @[el2_ifu_mem_ctl.scala 605:46] node _T_2578 = mux(bus_reset_cmd_beat_cnt_0, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_2579 = mux(_T_2575, UInt<3>("h06"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_2580 = mux(bus_inc_cmd_beat_cnt, _T_2577, UInt<1>("h00")) @[Mux.scala 27:72] @@ -3645,91 +3645,91 @@ circuit el2_ifu_mem_ctl : node _T_2584 = or(_T_2583, _T_2581) @[Mux.scala 27:72] wire bus_new_cmd_beat_count : UInt<3> @[Mux.scala 27:72] bus_new_cmd_beat_count <= _T_2584 @[Mux.scala 27:72] - node _T_2585 = or(bus_ifu_bus_clk_en, ic_act_miss_f) @[el2_ifu_mem_ctl.scala 605:84] - node _T_2586 = or(_T_2585, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 605:100] - node _T_2587 = and(_T_2586, bus_cmd_beat_en) @[el2_ifu_mem_ctl.scala 605:125] + node _T_2585 = or(bus_ifu_bus_clk_en, ic_act_miss_f) @[el2_ifu_mem_ctl.scala 606:84] + node _T_2586 = or(_T_2585, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 606:100] + node _T_2587 = and(_T_2586, bus_cmd_beat_en) @[el2_ifu_mem_ctl.scala 606:125] reg _T_2588 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_2587 : @[Reg.scala 28:19] _T_2588 <= bus_new_cmd_beat_count @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bus_cmd_beat_count <= _T_2588 @[el2_ifu_mem_ctl.scala 605:22] - node _T_2589 = eq(bus_data_beat_count, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 606:69] - node _T_2590 = andr(bus_data_beat_count) @[el2_ifu_mem_ctl.scala 606:101] - node _T_2591 = mux(uncacheable_miss_ff, _T_2589, _T_2590) @[el2_ifu_mem_ctl.scala 606:28] - bus_last_data_beat <= _T_2591 @[el2_ifu_mem_ctl.scala 606:22] - node _T_2592 = and(ifu_bus_rvalid, miss_pending) @[el2_ifu_mem_ctl.scala 607:35] - bus_ifu_wr_en <= _T_2592 @[el2_ifu_mem_ctl.scala 607:17] - node _T_2593 = and(ifu_bus_rvalid_ff, miss_pending) @[el2_ifu_mem_ctl.scala 608:41] - bus_ifu_wr_en_ff <= _T_2593 @[el2_ifu_mem_ctl.scala 608:20] - node _T_2594 = and(ifu_bus_rvalid_ff, miss_pending) @[el2_ifu_mem_ctl.scala 609:44] - node _T_2595 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 609:61] - node _T_2596 = and(_T_2594, _T_2595) @[el2_ifu_mem_ctl.scala 609:59] - node _T_2597 = orr(ifu_bus_rresp_ff) @[el2_ifu_mem_ctl.scala 609:103] - node _T_2598 = eq(_T_2597, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 609:84] - node _T_2599 = and(_T_2596, _T_2598) @[el2_ifu_mem_ctl.scala 609:82] - node _T_2600 = and(_T_2599, write_ic_16_bytes) @[el2_ifu_mem_ctl.scala 609:108] - bus_ifu_wr_en_ff_q <= _T_2600 @[el2_ifu_mem_ctl.scala 609:22] - node _T_2601 = and(ifu_bus_rvalid_ff, miss_pending) @[el2_ifu_mem_ctl.scala 610:51] - node _T_2602 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 610:68] - node bus_ifu_wr_en_ff_wo_err = and(_T_2601, _T_2602) @[el2_ifu_mem_ctl.scala 610:66] - reg ic_act_miss_f_delayed : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 611:61] - ic_act_miss_f_delayed <= ic_act_miss_f @[el2_ifu_mem_ctl.scala 611:61] - node _T_2603 = eq(miss_state, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 612:66] - node _T_2604 = and(ic_act_miss_f_delayed, _T_2603) @[el2_ifu_mem_ctl.scala 612:53] - node _T_2605 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 612:86] - node _T_2606 = and(_T_2604, _T_2605) @[el2_ifu_mem_ctl.scala 612:84] - reset_tag_valid_for_miss <= _T_2606 @[el2_ifu_mem_ctl.scala 612:28] - node _T_2607 = orr(io.ifu_axi_rresp) @[el2_ifu_mem_ctl.scala 613:47] - node _T_2608 = and(_T_2607, ifu_bus_rvalid) @[el2_ifu_mem_ctl.scala 613:50] - node _T_2609 = and(_T_2608, miss_pending) @[el2_ifu_mem_ctl.scala 613:68] - bus_ifu_wr_data_error <= _T_2609 @[el2_ifu_mem_ctl.scala 613:25] - node _T_2610 = orr(ifu_bus_rresp_ff) @[el2_ifu_mem_ctl.scala 614:48] - node _T_2611 = and(_T_2610, ifu_bus_rvalid_ff) @[el2_ifu_mem_ctl.scala 614:52] - node _T_2612 = and(_T_2611, miss_pending) @[el2_ifu_mem_ctl.scala 614:73] - bus_ifu_wr_data_error_ff <= _T_2612 @[el2_ifu_mem_ctl.scala 614:28] + bus_cmd_beat_count <= _T_2588 @[el2_ifu_mem_ctl.scala 606:22] + node _T_2589 = eq(bus_data_beat_count, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 607:69] + node _T_2590 = andr(bus_data_beat_count) @[el2_ifu_mem_ctl.scala 607:101] + node _T_2591 = mux(uncacheable_miss_ff, _T_2589, _T_2590) @[el2_ifu_mem_ctl.scala 607:28] + bus_last_data_beat <= _T_2591 @[el2_ifu_mem_ctl.scala 607:22] + node _T_2592 = and(ifu_bus_rvalid, miss_pending) @[el2_ifu_mem_ctl.scala 608:35] + bus_ifu_wr_en <= _T_2592 @[el2_ifu_mem_ctl.scala 608:17] + node _T_2593 = and(ifu_bus_rvalid_ff, miss_pending) @[el2_ifu_mem_ctl.scala 609:41] + bus_ifu_wr_en_ff <= _T_2593 @[el2_ifu_mem_ctl.scala 609:20] + node _T_2594 = and(ifu_bus_rvalid_ff, miss_pending) @[el2_ifu_mem_ctl.scala 610:44] + node _T_2595 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 610:61] + node _T_2596 = and(_T_2594, _T_2595) @[el2_ifu_mem_ctl.scala 610:59] + node _T_2597 = orr(ifu_bus_rresp_ff) @[el2_ifu_mem_ctl.scala 610:103] + node _T_2598 = eq(_T_2597, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 610:84] + node _T_2599 = and(_T_2596, _T_2598) @[el2_ifu_mem_ctl.scala 610:82] + node _T_2600 = and(_T_2599, write_ic_16_bytes) @[el2_ifu_mem_ctl.scala 610:108] + bus_ifu_wr_en_ff_q <= _T_2600 @[el2_ifu_mem_ctl.scala 610:22] + node _T_2601 = and(ifu_bus_rvalid_ff, miss_pending) @[el2_ifu_mem_ctl.scala 611:51] + node _T_2602 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 611:68] + node bus_ifu_wr_en_ff_wo_err = and(_T_2601, _T_2602) @[el2_ifu_mem_ctl.scala 611:66] + reg ic_act_miss_f_delayed : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 612:61] + ic_act_miss_f_delayed <= ic_act_miss_f @[el2_ifu_mem_ctl.scala 612:61] + node _T_2603 = eq(miss_state, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 613:66] + node _T_2604 = and(ic_act_miss_f_delayed, _T_2603) @[el2_ifu_mem_ctl.scala 613:53] + node _T_2605 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 613:86] + node _T_2606 = and(_T_2604, _T_2605) @[el2_ifu_mem_ctl.scala 613:84] + reset_tag_valid_for_miss <= _T_2606 @[el2_ifu_mem_ctl.scala 613:28] + node _T_2607 = orr(io.ifu_axi_rresp) @[el2_ifu_mem_ctl.scala 614:47] + node _T_2608 = and(_T_2607, ifu_bus_rvalid) @[el2_ifu_mem_ctl.scala 614:50] + node _T_2609 = and(_T_2608, miss_pending) @[el2_ifu_mem_ctl.scala 614:68] + bus_ifu_wr_data_error <= _T_2609 @[el2_ifu_mem_ctl.scala 614:25] + node _T_2610 = orr(ifu_bus_rresp_ff) @[el2_ifu_mem_ctl.scala 615:48] + node _T_2611 = and(_T_2610, ifu_bus_rvalid_ff) @[el2_ifu_mem_ctl.scala 615:52] + node _T_2612 = and(_T_2611, miss_pending) @[el2_ifu_mem_ctl.scala 615:73] + bus_ifu_wr_data_error_ff <= _T_2612 @[el2_ifu_mem_ctl.scala 615:28] wire ifc_dma_access_ok_d : UInt<1> ifc_dma_access_ok_d <= UInt<1>("h00") - reg ifc_dma_access_ok_prev : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 616:62] - ifc_dma_access_ok_prev <= ifc_dma_access_ok_d @[el2_ifu_mem_ctl.scala 616:62] - node _T_2613 = or(ic_crit_wd_rdy_new_in, ic_crit_wd_rdy_new_ff) @[el2_ifu_mem_ctl.scala 617:43] - ic_crit_wd_rdy <= _T_2613 @[el2_ifu_mem_ctl.scala 617:18] - node _T_2614 = and(bus_last_data_beat, bus_ifu_wr_en_ff) @[el2_ifu_mem_ctl.scala 618:35] - last_beat <= _T_2614 @[el2_ifu_mem_ctl.scala 618:13] - reset_beat_cnt <= bus_reset_data_beat_cnt @[el2_ifu_mem_ctl.scala 619:18] - node _T_2615 = eq(iccm_correct_ecc, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 621:50] - node _T_2616 = and(io.ifc_dma_access_ok, _T_2615) @[el2_ifu_mem_ctl.scala 621:47] - node _T_2617 = eq(io.iccm_dma_sb_error, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 621:70] - node _T_2618 = and(_T_2616, _T_2617) @[el2_ifu_mem_ctl.scala 621:68] - ifc_dma_access_ok_d <= _T_2618 @[el2_ifu_mem_ctl.scala 621:23] - node _T_2619 = eq(iccm_correct_ecc, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 622:54] - node _T_2620 = and(io.ifc_dma_access_ok, _T_2619) @[el2_ifu_mem_ctl.scala 622:51] - node _T_2621 = and(_T_2620, ifc_dma_access_ok_prev) @[el2_ifu_mem_ctl.scala 622:72] - node _T_2622 = eq(perr_state, UInt<3>("h00")) @[el2_ifu_mem_ctl.scala 622:111] - node _T_2623 = and(_T_2621, _T_2622) @[el2_ifu_mem_ctl.scala 622:97] - node _T_2624 = eq(io.iccm_dma_sb_error, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 622:129] - node ifc_dma_access_q_ok = and(_T_2623, _T_2624) @[el2_ifu_mem_ctl.scala 622:127] - io.iccm_ready <= ifc_dma_access_q_ok @[el2_ifu_mem_ctl.scala 623:17] - reg _T_2625 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 624:51] - _T_2625 <= io.dma_iccm_req @[el2_ifu_mem_ctl.scala 624:51] - dma_iccm_req_f <= _T_2625 @[el2_ifu_mem_ctl.scala 624:18] - node _T_2626 = and(ifc_dma_access_q_ok, io.dma_iccm_req) @[el2_ifu_mem_ctl.scala 625:40] - node _T_2627 = and(_T_2626, io.dma_mem_write) @[el2_ifu_mem_ctl.scala 625:58] - node _T_2628 = or(_T_2627, iccm_correct_ecc) @[el2_ifu_mem_ctl.scala 625:79] - io.iccm_wren <= _T_2628 @[el2_ifu_mem_ctl.scala 625:16] - node _T_2629 = and(ifc_dma_access_q_ok, io.dma_iccm_req) @[el2_ifu_mem_ctl.scala 626:40] - node _T_2630 = eq(io.dma_mem_write, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 626:60] - node _T_2631 = and(_T_2629, _T_2630) @[el2_ifu_mem_ctl.scala 626:58] - node _T_2632 = and(io.ifc_iccm_access_bf, io.ifc_fetch_req_bf) @[el2_ifu_mem_ctl.scala 626:104] - node _T_2633 = or(_T_2631, _T_2632) @[el2_ifu_mem_ctl.scala 626:79] - io.iccm_rden <= _T_2633 @[el2_ifu_mem_ctl.scala 626:16] - node _T_2634 = and(ifc_dma_access_q_ok, io.dma_iccm_req) @[el2_ifu_mem_ctl.scala 627:43] - node _T_2635 = eq(io.dma_mem_write, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 627:63] - node iccm_dma_rden = and(_T_2634, _T_2635) @[el2_ifu_mem_ctl.scala 627:61] + reg ifc_dma_access_ok_prev : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 617:62] + ifc_dma_access_ok_prev <= ifc_dma_access_ok_d @[el2_ifu_mem_ctl.scala 617:62] + node _T_2613 = or(ic_crit_wd_rdy_new_in, ic_crit_wd_rdy_new_ff) @[el2_ifu_mem_ctl.scala 618:43] + ic_crit_wd_rdy <= _T_2613 @[el2_ifu_mem_ctl.scala 618:18] + node _T_2614 = and(bus_last_data_beat, bus_ifu_wr_en_ff) @[el2_ifu_mem_ctl.scala 619:35] + last_beat <= _T_2614 @[el2_ifu_mem_ctl.scala 619:13] + reset_beat_cnt <= bus_reset_data_beat_cnt @[el2_ifu_mem_ctl.scala 620:18] + node _T_2615 = eq(iccm_correct_ecc, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 622:50] + node _T_2616 = and(io.ifc_dma_access_ok, _T_2615) @[el2_ifu_mem_ctl.scala 622:47] + node _T_2617 = eq(io.iccm_dma_sb_error, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 622:70] + node _T_2618 = and(_T_2616, _T_2617) @[el2_ifu_mem_ctl.scala 622:68] + ifc_dma_access_ok_d <= _T_2618 @[el2_ifu_mem_ctl.scala 622:23] + node _T_2619 = eq(iccm_correct_ecc, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 623:54] + node _T_2620 = and(io.ifc_dma_access_ok, _T_2619) @[el2_ifu_mem_ctl.scala 623:51] + node _T_2621 = and(_T_2620, ifc_dma_access_ok_prev) @[el2_ifu_mem_ctl.scala 623:72] + node _T_2622 = eq(perr_state, UInt<3>("h00")) @[el2_ifu_mem_ctl.scala 623:111] + node _T_2623 = and(_T_2621, _T_2622) @[el2_ifu_mem_ctl.scala 623:97] + node _T_2624 = eq(io.iccm_dma_sb_error, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 623:129] + node ifc_dma_access_q_ok = and(_T_2623, _T_2624) @[el2_ifu_mem_ctl.scala 623:127] + io.iccm_ready <= ifc_dma_access_q_ok @[el2_ifu_mem_ctl.scala 624:17] + reg _T_2625 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 625:51] + _T_2625 <= io.dma_iccm_req @[el2_ifu_mem_ctl.scala 625:51] + dma_iccm_req_f <= _T_2625 @[el2_ifu_mem_ctl.scala 625:18] + node _T_2626 = and(ifc_dma_access_q_ok, io.dma_iccm_req) @[el2_ifu_mem_ctl.scala 626:40] + node _T_2627 = and(_T_2626, io.dma_mem_write) @[el2_ifu_mem_ctl.scala 626:58] + node _T_2628 = or(_T_2627, iccm_correct_ecc) @[el2_ifu_mem_ctl.scala 626:79] + io.iccm_wren <= _T_2628 @[el2_ifu_mem_ctl.scala 626:16] + node _T_2629 = and(ifc_dma_access_q_ok, io.dma_iccm_req) @[el2_ifu_mem_ctl.scala 627:40] + node _T_2630 = eq(io.dma_mem_write, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 627:60] + node _T_2631 = and(_T_2629, _T_2630) @[el2_ifu_mem_ctl.scala 627:58] + node _T_2632 = and(io.ifc_iccm_access_bf, io.ifc_fetch_req_bf) @[el2_ifu_mem_ctl.scala 627:104] + node _T_2633 = or(_T_2631, _T_2632) @[el2_ifu_mem_ctl.scala 627:79] + io.iccm_rden <= _T_2633 @[el2_ifu_mem_ctl.scala 627:16] + node _T_2634 = and(ifc_dma_access_q_ok, io.dma_iccm_req) @[el2_ifu_mem_ctl.scala 628:43] + node _T_2635 = eq(io.dma_mem_write, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 628:63] + node iccm_dma_rden = and(_T_2634, _T_2635) @[el2_ifu_mem_ctl.scala 628:61] node _T_2636 = bits(io.dma_iccm_req, 0, 0) @[Bitwise.scala 72:15] node _T_2637 = mux(_T_2636, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_2638 = and(_T_2637, io.dma_mem_sz) @[el2_ifu_mem_ctl.scala 628:47] - io.iccm_wr_size <= _T_2638 @[el2_ifu_mem_ctl.scala 628:19] - node _T_2639 = bits(io.dma_mem_wdata, 63, 32) @[el2_ifu_mem_ctl.scala 629:54] + node _T_2638 = and(_T_2637, io.dma_mem_sz) @[el2_ifu_mem_ctl.scala 629:47] + io.iccm_wr_size <= _T_2638 @[el2_ifu_mem_ctl.scala 629:19] + node _T_2639 = bits(io.dma_mem_wdata, 63, 32) @[el2_ifu_mem_ctl.scala 630:54] wire _T_2640 : UInt<1>[18] @[el2_lib.scala 250:18] wire _T_2641 : UInt<1>[18] @[el2_lib.scala 251:18] wire _T_2642 : UInt<1>[18] @[el2_lib.scala 252:18] @@ -4015,7 +4015,7 @@ circuit el2_ifu_mem_ctl : node _T_2832 = xorr(_T_2830) @[el2_lib.scala 269:23] node _T_2833 = xor(_T_2831, _T_2832) @[el2_lib.scala 269:18] node _T_2834 = cat(_T_2833, _T_2830) @[Cat.scala 29:58] - node _T_2835 = bits(io.dma_mem_wdata, 31, 0) @[el2_ifu_mem_ctl.scala 629:93] + node _T_2835 = bits(io.dma_mem_wdata, 31, 0) @[el2_ifu_mem_ctl.scala 630:93] wire _T_2836 : UInt<1>[18] @[el2_lib.scala 250:18] wire _T_2837 : UInt<1>[18] @[el2_lib.scala 251:18] wire _T_2838 : UInt<1>[18] @[el2_lib.scala 252:18] @@ -4304,87 +4304,87 @@ circuit el2_ifu_mem_ctl : node dma_mem_ecc = cat(_T_2834, _T_3030) @[Cat.scala 29:58] wire iccm_ecc_corr_data_ff : UInt<39> iccm_ecc_corr_data_ff <= UInt<1>("h00") - node _T_3031 = and(ifc_dma_access_q_ok, io.dma_iccm_req) @[el2_ifu_mem_ctl.scala 631:67] - node _T_3032 = eq(_T_3031, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 631:45] - node _T_3033 = and(iccm_correct_ecc, _T_3032) @[el2_ifu_mem_ctl.scala 631:43] + node _T_3031 = and(ifc_dma_access_q_ok, io.dma_iccm_req) @[el2_ifu_mem_ctl.scala 632:67] + node _T_3032 = eq(_T_3031, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 632:45] + node _T_3033 = and(iccm_correct_ecc, _T_3032) @[el2_ifu_mem_ctl.scala 632:43] node _T_3034 = cat(iccm_ecc_corr_data_ff, iccm_ecc_corr_data_ff) @[Cat.scala 29:58] - node _T_3035 = bits(dma_mem_ecc, 13, 7) @[el2_ifu_mem_ctl.scala 632:20] - node _T_3036 = bits(io.dma_mem_wdata, 63, 32) @[el2_ifu_mem_ctl.scala 632:43] - node _T_3037 = bits(dma_mem_ecc, 6, 0) @[el2_ifu_mem_ctl.scala 632:63] - node _T_3038 = bits(io.dma_mem_wdata, 31, 0) @[el2_ifu_mem_ctl.scala 632:86] + node _T_3035 = bits(dma_mem_ecc, 13, 7) @[el2_ifu_mem_ctl.scala 633:20] + node _T_3036 = bits(io.dma_mem_wdata, 63, 32) @[el2_ifu_mem_ctl.scala 633:43] + node _T_3037 = bits(dma_mem_ecc, 6, 0) @[el2_ifu_mem_ctl.scala 633:63] + node _T_3038 = bits(io.dma_mem_wdata, 31, 0) @[el2_ifu_mem_ctl.scala 633:86] node _T_3039 = cat(_T_3037, _T_3038) @[Cat.scala 29:58] node _T_3040 = cat(_T_3035, _T_3036) @[Cat.scala 29:58] node _T_3041 = cat(_T_3040, _T_3039) @[Cat.scala 29:58] - node _T_3042 = mux(_T_3033, _T_3034, _T_3041) @[el2_ifu_mem_ctl.scala 631:25] - io.iccm_wr_data <= _T_3042 @[el2_ifu_mem_ctl.scala 631:19] - wire iccm_corrected_data : UInt<32>[2] @[el2_ifu_mem_ctl.scala 633:33] - iccm_corrected_data[0] <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 634:26] - iccm_corrected_data[1] <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 635:26] + node _T_3042 = mux(_T_3033, _T_3034, _T_3041) @[el2_ifu_mem_ctl.scala 632:25] + io.iccm_wr_data <= _T_3042 @[el2_ifu_mem_ctl.scala 632:19] + wire iccm_corrected_data : UInt<32>[2] @[el2_ifu_mem_ctl.scala 634:33] + iccm_corrected_data[0] <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 635:26] + iccm_corrected_data[1] <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 636:26] wire dma_mem_addr_ff : UInt<2> dma_mem_addr_ff <= UInt<1>("h00") - node _T_3043 = bits(dma_mem_addr_ff, 0, 0) @[el2_ifu_mem_ctl.scala 637:51] - node _T_3044 = bits(_T_3043, 0, 0) @[el2_ifu_mem_ctl.scala 637:55] - node iccm_dma_rdata_1_muxed = mux(_T_3044, iccm_corrected_data[0], iccm_corrected_data[1]) @[el2_ifu_mem_ctl.scala 637:35] + node _T_3043 = bits(dma_mem_addr_ff, 0, 0) @[el2_ifu_mem_ctl.scala 638:51] + node _T_3044 = bits(_T_3043, 0, 0) @[el2_ifu_mem_ctl.scala 638:55] + node iccm_dma_rdata_1_muxed = mux(_T_3044, iccm_corrected_data[0], iccm_corrected_data[1]) @[el2_ifu_mem_ctl.scala 638:35] wire iccm_double_ecc_error : UInt<2> iccm_double_ecc_error <= UInt<1>("h00") - node iccm_dma_ecc_error_in = orr(iccm_double_ecc_error) @[el2_ifu_mem_ctl.scala 639:53] + node iccm_dma_ecc_error_in = orr(iccm_double_ecc_error) @[el2_ifu_mem_ctl.scala 640:53] node _T_3045 = cat(io.dma_mem_addr, io.dma_mem_addr) @[Cat.scala 29:58] node _T_3046 = cat(iccm_dma_rdata_1_muxed, iccm_corrected_data[0]) @[Cat.scala 29:58] - node iccm_dma_rdata_in = mux(iccm_dma_ecc_error_in, _T_3045, _T_3046) @[el2_ifu_mem_ctl.scala 640:30] - reg dma_mem_tag_ff : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 641:54] - dma_mem_tag_ff <= io.dma_mem_tag @[el2_ifu_mem_ctl.scala 641:54] - reg iccm_dma_rtag : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 642:69] - iccm_dma_rtag <= dma_mem_tag_ff @[el2_ifu_mem_ctl.scala 642:69] - io.iccm_dma_rtag <= iccm_dma_rtag @[el2_ifu_mem_ctl.scala 643:20] - node _T_3047 = bits(io.dma_mem_addr, 3, 2) @[el2_ifu_mem_ctl.scala 645:69] - reg _T_3048 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 645:53] - _T_3048 <= _T_3047 @[el2_ifu_mem_ctl.scala 645:53] - dma_mem_addr_ff <= _T_3048 @[el2_ifu_mem_ctl.scala 645:19] - reg iccm_dma_rvalid_in : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 646:59] - iccm_dma_rvalid_in <= iccm_dma_rden @[el2_ifu_mem_ctl.scala 646:59] - reg iccm_dma_rvalid : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 647:71] - iccm_dma_rvalid <= iccm_dma_rvalid_in @[el2_ifu_mem_ctl.scala 647:71] - io.iccm_dma_rvalid <= iccm_dma_rvalid @[el2_ifu_mem_ctl.scala 648:22] - reg iccm_dma_ecc_error : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 649:74] - iccm_dma_ecc_error <= iccm_dma_ecc_error_in @[el2_ifu_mem_ctl.scala 649:74] - io.iccm_dma_ecc_error <= iccm_dma_ecc_error_in @[el2_ifu_mem_ctl.scala 650:25] - reg iccm_dma_rdata : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 651:70] - iccm_dma_rdata <= iccm_dma_rdata_in @[el2_ifu_mem_ctl.scala 651:70] - io.iccm_dma_rdata <= iccm_dma_rdata @[el2_ifu_mem_ctl.scala 652:21] + node iccm_dma_rdata_in = mux(iccm_dma_ecc_error_in, _T_3045, _T_3046) @[el2_ifu_mem_ctl.scala 641:30] + reg dma_mem_tag_ff : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 642:54] + dma_mem_tag_ff <= io.dma_mem_tag @[el2_ifu_mem_ctl.scala 642:54] + reg iccm_dma_rtag : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 643:69] + iccm_dma_rtag <= dma_mem_tag_ff @[el2_ifu_mem_ctl.scala 643:69] + io.iccm_dma_rtag <= iccm_dma_rtag @[el2_ifu_mem_ctl.scala 644:20] + node _T_3047 = bits(io.dma_mem_addr, 3, 2) @[el2_ifu_mem_ctl.scala 646:69] + reg _T_3048 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 646:53] + _T_3048 <= _T_3047 @[el2_ifu_mem_ctl.scala 646:53] + dma_mem_addr_ff <= _T_3048 @[el2_ifu_mem_ctl.scala 646:19] + reg iccm_dma_rvalid_in : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 647:59] + iccm_dma_rvalid_in <= iccm_dma_rden @[el2_ifu_mem_ctl.scala 647:59] + reg iccm_dma_rvalid : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 648:71] + iccm_dma_rvalid <= iccm_dma_rvalid_in @[el2_ifu_mem_ctl.scala 648:71] + io.iccm_dma_rvalid <= iccm_dma_rvalid @[el2_ifu_mem_ctl.scala 649:22] + reg iccm_dma_ecc_error : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 650:74] + iccm_dma_ecc_error <= iccm_dma_ecc_error_in @[el2_ifu_mem_ctl.scala 650:74] + io.iccm_dma_ecc_error <= iccm_dma_ecc_error_in @[el2_ifu_mem_ctl.scala 651:25] + reg iccm_dma_rdata : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 652:70] + iccm_dma_rdata <= iccm_dma_rdata_in @[el2_ifu_mem_ctl.scala 652:70] + io.iccm_dma_rdata <= iccm_dma_rdata @[el2_ifu_mem_ctl.scala 653:21] wire iccm_ecc_corr_index_ff : UInt<14> iccm_ecc_corr_index_ff <= UInt<1>("h00") - node _T_3049 = and(ifc_dma_access_q_ok, io.dma_iccm_req) @[el2_ifu_mem_ctl.scala 654:46] - node _T_3050 = eq(iccm_correct_ecc, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 654:67] - node _T_3051 = and(_T_3049, _T_3050) @[el2_ifu_mem_ctl.scala 654:65] - node _T_3052 = and(ifc_dma_access_q_ok, io.dma_iccm_req) @[el2_ifu_mem_ctl.scala 655:31] - node _T_3053 = eq(_T_3052, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 655:9] - node _T_3054 = and(_T_3053, iccm_correct_ecc) @[el2_ifu_mem_ctl.scala 655:50] + node _T_3049 = and(ifc_dma_access_q_ok, io.dma_iccm_req) @[el2_ifu_mem_ctl.scala 655:46] + node _T_3050 = eq(iccm_correct_ecc, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 655:67] + node _T_3051 = and(_T_3049, _T_3050) @[el2_ifu_mem_ctl.scala 655:65] + node _T_3052 = and(ifc_dma_access_q_ok, io.dma_iccm_req) @[el2_ifu_mem_ctl.scala 656:31] + node _T_3053 = eq(_T_3052, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 656:9] + node _T_3054 = and(_T_3053, iccm_correct_ecc) @[el2_ifu_mem_ctl.scala 656:50] node _T_3055 = cat(iccm_ecc_corr_index_ff, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_3056 = bits(io.ifc_fetch_addr_bf, 15, 0) @[el2_ifu_mem_ctl.scala 655:124] - node _T_3057 = mux(_T_3054, _T_3055, _T_3056) @[el2_ifu_mem_ctl.scala 655:8] - node _T_3058 = mux(_T_3051, io.dma_mem_addr, _T_3057) @[el2_ifu_mem_ctl.scala 654:25] - io.iccm_rw_addr <= _T_3058 @[el2_ifu_mem_ctl.scala 654:19] + node _T_3056 = bits(io.ifc_fetch_addr_bf, 15, 0) @[el2_ifu_mem_ctl.scala 656:124] + node _T_3057 = mux(_T_3054, _T_3055, _T_3056) @[el2_ifu_mem_ctl.scala 656:8] + node _T_3058 = mux(_T_3051, io.dma_mem_addr, _T_3057) @[el2_ifu_mem_ctl.scala 655:25] + io.iccm_rw_addr <= _T_3058 @[el2_ifu_mem_ctl.scala 655:19] node ic_fetch_val_int_f = cat(UInt<2>("h00"), io.ic_fetch_val_f) @[Cat.scala 29:58] - node _T_3059 = bits(ifu_fetch_addr_int_f, 0, 0) @[el2_ifu_mem_ctl.scala 657:76] - node ic_fetch_val_shift_right = dshl(ic_fetch_val_int_f, _T_3059) @[el2_ifu_mem_ctl.scala 657:53] - node _T_3060 = bits(ic_fetch_val_shift_right, 1, 0) @[el2_ifu_mem_ctl.scala 660:75] - node _T_3061 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 660:93] - node _T_3062 = and(_T_3060, _T_3061) @[el2_ifu_mem_ctl.scala 660:91] - node _T_3063 = and(_T_3062, fetch_req_iccm_f) @[el2_ifu_mem_ctl.scala 660:113] - node _T_3064 = or(_T_3063, iccm_dma_rvalid_in) @[el2_ifu_mem_ctl.scala 660:130] - node _T_3065 = eq(io.dec_tlu_core_ecc_disable, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 660:154] - node _T_3066 = and(_T_3064, _T_3065) @[el2_ifu_mem_ctl.scala 660:152] - node _T_3067 = bits(ic_fetch_val_shift_right, 3, 2) @[el2_ifu_mem_ctl.scala 660:75] - node _T_3068 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 660:93] - node _T_3069 = and(_T_3067, _T_3068) @[el2_ifu_mem_ctl.scala 660:91] - node _T_3070 = and(_T_3069, fetch_req_iccm_f) @[el2_ifu_mem_ctl.scala 660:113] - node _T_3071 = or(_T_3070, iccm_dma_rvalid_in) @[el2_ifu_mem_ctl.scala 660:130] - node _T_3072 = eq(io.dec_tlu_core_ecc_disable, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 660:154] - node _T_3073 = and(_T_3071, _T_3072) @[el2_ifu_mem_ctl.scala 660:152] + node _T_3059 = bits(ifu_fetch_addr_int_f, 0, 0) @[el2_ifu_mem_ctl.scala 658:76] + node ic_fetch_val_shift_right = dshl(ic_fetch_val_int_f, _T_3059) @[el2_ifu_mem_ctl.scala 658:53] + node _T_3060 = bits(ic_fetch_val_shift_right, 1, 0) @[el2_ifu_mem_ctl.scala 661:75] + node _T_3061 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 661:93] + node _T_3062 = and(_T_3060, _T_3061) @[el2_ifu_mem_ctl.scala 661:91] + node _T_3063 = and(_T_3062, fetch_req_iccm_f) @[el2_ifu_mem_ctl.scala 661:113] + node _T_3064 = or(_T_3063, iccm_dma_rvalid_in) @[el2_ifu_mem_ctl.scala 661:130] + node _T_3065 = eq(io.dec_tlu_core_ecc_disable, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 661:154] + node _T_3066 = and(_T_3064, _T_3065) @[el2_ifu_mem_ctl.scala 661:152] + node _T_3067 = bits(ic_fetch_val_shift_right, 3, 2) @[el2_ifu_mem_ctl.scala 661:75] + node _T_3068 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 661:93] + node _T_3069 = and(_T_3067, _T_3068) @[el2_ifu_mem_ctl.scala 661:91] + node _T_3070 = and(_T_3069, fetch_req_iccm_f) @[el2_ifu_mem_ctl.scala 661:113] + node _T_3071 = or(_T_3070, iccm_dma_rvalid_in) @[el2_ifu_mem_ctl.scala 661:130] + node _T_3072 = eq(io.dec_tlu_core_ecc_disable, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 661:154] + node _T_3073 = and(_T_3071, _T_3072) @[el2_ifu_mem_ctl.scala 661:152] node iccm_ecc_word_enable = cat(_T_3073, _T_3066) @[Cat.scala 29:58] - node _T_3074 = bits(iccm_ecc_word_enable, 0, 0) @[el2_ifu_mem_ctl.scala 661:73] - node _T_3075 = bits(io.iccm_rd_data_ecc, 31, 0) @[el2_ifu_mem_ctl.scala 661:93] - node _T_3076 = bits(io.iccm_rd_data_ecc, 38, 32) @[el2_ifu_mem_ctl.scala 661:128] + node _T_3074 = bits(iccm_ecc_word_enable, 0, 0) @[el2_ifu_mem_ctl.scala 662:73] + node _T_3075 = bits(io.iccm_rd_data_ecc, 31, 0) @[el2_ifu_mem_ctl.scala 662:93] + node _T_3076 = bits(io.iccm_rd_data_ecc, 38, 32) @[el2_ifu_mem_ctl.scala 662:128] wire _T_3077 : UInt<1>[18] @[el2_lib.scala 281:18] wire _T_3078 : UInt<1>[18] @[el2_lib.scala 282:18] wire _T_3079 : UInt<1>[18] @[el2_lib.scala 283:18] @@ -4896,9 +4896,9 @@ circuit el2_ifu_mem_ctl : node _T_3456 = cat(_T_3448, _T_3449) @[Cat.scala 29:58] node _T_3457 = cat(_T_3456, _T_3450) @[Cat.scala 29:58] node _T_3458 = cat(_T_3457, _T_3455) @[Cat.scala 29:58] - node _T_3459 = bits(iccm_ecc_word_enable, 1, 1) @[el2_ifu_mem_ctl.scala 661:73] - node _T_3460 = bits(io.iccm_rd_data_ecc, 70, 39) @[el2_ifu_mem_ctl.scala 661:93] - node _T_3461 = bits(io.iccm_rd_data_ecc, 77, 71) @[el2_ifu_mem_ctl.scala 661:128] + node _T_3459 = bits(iccm_ecc_word_enable, 1, 1) @[el2_ifu_mem_ctl.scala 662:73] + node _T_3460 = bits(io.iccm_rd_data_ecc, 70, 39) @[el2_ifu_mem_ctl.scala 662:93] + node _T_3461 = bits(io.iccm_rd_data_ecc, 77, 71) @[el2_ifu_mem_ctl.scala 662:128] wire _T_3462 : UInt<1>[18] @[el2_lib.scala 281:18] wire _T_3463 : UInt<1>[18] @[el2_lib.scala 282:18] wire _T_3464 : UInt<1>[18] @[el2_lib.scala 283:18] @@ -5410,1730 +5410,1730 @@ circuit el2_ifu_mem_ctl : node _T_3841 = cat(_T_3833, _T_3834) @[Cat.scala 29:58] node _T_3842 = cat(_T_3841, _T_3835) @[Cat.scala 29:58] node _T_3843 = cat(_T_3842, _T_3840) @[Cat.scala 29:58] - wire iccm_corrected_ecc : UInt<7>[2] @[el2_ifu_mem_ctl.scala 662:32] - wire _T_3844 : UInt<7>[2] @[el2_ifu_mem_ctl.scala 663:32] - _T_3844[0] <= _T_3458 @[el2_ifu_mem_ctl.scala 663:32] - _T_3844[1] <= _T_3843 @[el2_ifu_mem_ctl.scala 663:32] - iccm_corrected_ecc[0] <= _T_3844[0] @[el2_ifu_mem_ctl.scala 663:22] - iccm_corrected_ecc[1] <= _T_3844[1] @[el2_ifu_mem_ctl.scala 663:22] - wire _T_3845 : UInt<32>[2] @[el2_ifu_mem_ctl.scala 664:33] - _T_3845[0] <= _T_3444 @[el2_ifu_mem_ctl.scala 664:33] - _T_3845[1] <= _T_3829 @[el2_ifu_mem_ctl.scala 664:33] - iccm_corrected_data[0] <= _T_3845[0] @[el2_ifu_mem_ctl.scala 664:23] - iccm_corrected_data[1] <= _T_3845[1] @[el2_ifu_mem_ctl.scala 664:23] + wire iccm_corrected_ecc : UInt<7>[2] @[el2_ifu_mem_ctl.scala 663:32] + wire _T_3844 : UInt<7>[2] @[el2_ifu_mem_ctl.scala 664:32] + _T_3844[0] <= _T_3458 @[el2_ifu_mem_ctl.scala 664:32] + _T_3844[1] <= _T_3843 @[el2_ifu_mem_ctl.scala 664:32] + iccm_corrected_ecc[0] <= _T_3844[0] @[el2_ifu_mem_ctl.scala 664:22] + iccm_corrected_ecc[1] <= _T_3844[1] @[el2_ifu_mem_ctl.scala 664:22] + wire _T_3845 : UInt<32>[2] @[el2_ifu_mem_ctl.scala 665:33] + _T_3845[0] <= _T_3444 @[el2_ifu_mem_ctl.scala 665:33] + _T_3845[1] <= _T_3829 @[el2_ifu_mem_ctl.scala 665:33] + iccm_corrected_data[0] <= _T_3845[0] @[el2_ifu_mem_ctl.scala 665:23] + iccm_corrected_data[1] <= _T_3845[1] @[el2_ifu_mem_ctl.scala 665:23] node _T_3846 = cat(_T_3289, _T_3674) @[Cat.scala 29:58] - iccm_single_ecc_error <= _T_3846 @[el2_ifu_mem_ctl.scala 665:25] + iccm_single_ecc_error <= _T_3846 @[el2_ifu_mem_ctl.scala 666:25] node _T_3847 = cat(_T_3294, _T_3679) @[Cat.scala 29:58] - iccm_double_ecc_error <= _T_3847 @[el2_ifu_mem_ctl.scala 666:25] - node _T_3848 = orr(iccm_single_ecc_error) @[el2_ifu_mem_ctl.scala 667:54] - node _T_3849 = and(_T_3848, ifc_iccm_access_f) @[el2_ifu_mem_ctl.scala 667:58] - node _T_3850 = and(_T_3849, ifc_fetch_req_f) @[el2_ifu_mem_ctl.scala 667:78] - io.iccm_rd_ecc_single_err <= _T_3850 @[el2_ifu_mem_ctl.scala 667:29] - node _T_3851 = orr(iccm_double_ecc_error) @[el2_ifu_mem_ctl.scala 668:54] - node _T_3852 = and(_T_3851, ifc_iccm_access_f) @[el2_ifu_mem_ctl.scala 668:58] - io.iccm_rd_ecc_double_err <= _T_3852 @[el2_ifu_mem_ctl.scala 668:29] - node _T_3853 = bits(iccm_single_ecc_error, 0, 0) @[el2_ifu_mem_ctl.scala 669:60] - node _T_3854 = bits(_T_3853, 0, 0) @[el2_ifu_mem_ctl.scala 669:64] - node iccm_corrected_data_f_mux = mux(_T_3854, iccm_corrected_data[0], iccm_corrected_data[1]) @[el2_ifu_mem_ctl.scala 669:38] - node _T_3855 = bits(iccm_single_ecc_error, 0, 0) @[el2_ifu_mem_ctl.scala 670:59] - node _T_3856 = bits(_T_3855, 0, 0) @[el2_ifu_mem_ctl.scala 670:63] - node iccm_corrected_ecc_f_mux = mux(_T_3856, iccm_corrected_ecc[0], iccm_corrected_ecc[1]) @[el2_ifu_mem_ctl.scala 670:37] + iccm_double_ecc_error <= _T_3847 @[el2_ifu_mem_ctl.scala 667:25] + node _T_3848 = orr(iccm_single_ecc_error) @[el2_ifu_mem_ctl.scala 668:54] + node _T_3849 = and(_T_3848, ifc_iccm_access_f) @[el2_ifu_mem_ctl.scala 668:58] + node _T_3850 = and(_T_3849, ifc_fetch_req_f) @[el2_ifu_mem_ctl.scala 668:78] + io.iccm_rd_ecc_single_err <= _T_3850 @[el2_ifu_mem_ctl.scala 668:29] + node _T_3851 = orr(iccm_double_ecc_error) @[el2_ifu_mem_ctl.scala 669:54] + node _T_3852 = and(_T_3851, ifc_iccm_access_f) @[el2_ifu_mem_ctl.scala 669:58] + io.iccm_rd_ecc_double_err <= _T_3852 @[el2_ifu_mem_ctl.scala 669:29] + node _T_3853 = bits(iccm_single_ecc_error, 0, 0) @[el2_ifu_mem_ctl.scala 670:60] + node _T_3854 = bits(_T_3853, 0, 0) @[el2_ifu_mem_ctl.scala 670:64] + node iccm_corrected_data_f_mux = mux(_T_3854, iccm_corrected_data[0], iccm_corrected_data[1]) @[el2_ifu_mem_ctl.scala 670:38] + node _T_3855 = bits(iccm_single_ecc_error, 0, 0) @[el2_ifu_mem_ctl.scala 671:59] + node _T_3856 = bits(_T_3855, 0, 0) @[el2_ifu_mem_ctl.scala 671:63] + node iccm_corrected_ecc_f_mux = mux(_T_3856, iccm_corrected_ecc[0], iccm_corrected_ecc[1]) @[el2_ifu_mem_ctl.scala 671:37] wire iccm_rd_ecc_single_err_ff : UInt<1> iccm_rd_ecc_single_err_ff <= UInt<1>("h00") - node _T_3857 = eq(iccm_rd_ecc_single_err_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 672:76] - node _T_3858 = and(io.iccm_rd_ecc_single_err, _T_3857) @[el2_ifu_mem_ctl.scala 672:74] - node _T_3859 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 672:106] - node _T_3860 = and(_T_3858, _T_3859) @[el2_ifu_mem_ctl.scala 672:104] - node iccm_ecc_write_status = or(_T_3860, io.iccm_dma_sb_error) @[el2_ifu_mem_ctl.scala 672:127] - node _T_3861 = or(io.iccm_rd_ecc_single_err, iccm_rd_ecc_single_err_ff) @[el2_ifu_mem_ctl.scala 673:67] - node _T_3862 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 673:98] - node iccm_rd_ecc_single_err_hold_in = and(_T_3861, _T_3862) @[el2_ifu_mem_ctl.scala 673:96] - iccm_error_start <= io.iccm_rd_ecc_single_err @[el2_ifu_mem_ctl.scala 674:20] + node _T_3857 = eq(iccm_rd_ecc_single_err_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 673:76] + node _T_3858 = and(io.iccm_rd_ecc_single_err, _T_3857) @[el2_ifu_mem_ctl.scala 673:74] + node _T_3859 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 673:106] + node _T_3860 = and(_T_3858, _T_3859) @[el2_ifu_mem_ctl.scala 673:104] + node iccm_ecc_write_status = or(_T_3860, io.iccm_dma_sb_error) @[el2_ifu_mem_ctl.scala 673:127] + node _T_3861 = or(io.iccm_rd_ecc_single_err, iccm_rd_ecc_single_err_ff) @[el2_ifu_mem_ctl.scala 674:67] + node _T_3862 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 674:98] + node iccm_rd_ecc_single_err_hold_in = and(_T_3861, _T_3862) @[el2_ifu_mem_ctl.scala 674:96] + iccm_error_start <= io.iccm_rd_ecc_single_err @[el2_ifu_mem_ctl.scala 675:20] wire iccm_rw_addr_f : UInt<14> iccm_rw_addr_f <= UInt<1>("h00") - node _T_3863 = bits(iccm_single_ecc_error, 0, 0) @[el2_ifu_mem_ctl.scala 676:57] - node _T_3864 = bits(_T_3863, 0, 0) @[el2_ifu_mem_ctl.scala 676:67] - node _T_3865 = add(iccm_rw_addr_f, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 676:102] - node _T_3866 = tail(_T_3865, 1) @[el2_ifu_mem_ctl.scala 676:102] - node iccm_ecc_corr_index_in = mux(_T_3864, iccm_rw_addr_f, _T_3866) @[el2_ifu_mem_ctl.scala 676:35] - node _T_3867 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_mem_ctl.scala 677:67] - reg _T_3868 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 677:51] - _T_3868 <= _T_3867 @[el2_ifu_mem_ctl.scala 677:51] - iccm_rw_addr_f <= _T_3868 @[el2_ifu_mem_ctl.scala 677:18] - reg _T_3869 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 678:62] - _T_3869 <= iccm_rd_ecc_single_err_hold_in @[el2_ifu_mem_ctl.scala 678:62] - iccm_rd_ecc_single_err_ff <= _T_3869 @[el2_ifu_mem_ctl.scala 678:29] + node _T_3863 = bits(iccm_single_ecc_error, 0, 0) @[el2_ifu_mem_ctl.scala 677:57] + node _T_3864 = bits(_T_3863, 0, 0) @[el2_ifu_mem_ctl.scala 677:67] + node _T_3865 = add(iccm_rw_addr_f, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 677:102] + node _T_3866 = tail(_T_3865, 1) @[el2_ifu_mem_ctl.scala 677:102] + node iccm_ecc_corr_index_in = mux(_T_3864, iccm_rw_addr_f, _T_3866) @[el2_ifu_mem_ctl.scala 677:35] + node _T_3867 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_mem_ctl.scala 678:67] + reg _T_3868 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 678:51] + _T_3868 <= _T_3867 @[el2_ifu_mem_ctl.scala 678:51] + iccm_rw_addr_f <= _T_3868 @[el2_ifu_mem_ctl.scala 678:18] + reg _T_3869 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 679:62] + _T_3869 <= iccm_rd_ecc_single_err_hold_in @[el2_ifu_mem_ctl.scala 679:62] + iccm_rd_ecc_single_err_ff <= _T_3869 @[el2_ifu_mem_ctl.scala 679:29] node _T_3870 = cat(iccm_corrected_ecc_f_mux, iccm_corrected_data_f_mux) @[Cat.scala 29:58] - node _T_3871 = bits(iccm_ecc_write_status, 0, 0) @[el2_ifu_mem_ctl.scala 679:152] + node _T_3871 = bits(iccm_ecc_write_status, 0, 0) @[el2_ifu_mem_ctl.scala 680:152] reg _T_3872 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_3871 : @[Reg.scala 28:19] _T_3872 <= _T_3870 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - iccm_ecc_corr_data_ff <= _T_3872 @[el2_ifu_mem_ctl.scala 679:25] - node _T_3873 = bits(iccm_ecc_write_status, 0, 0) @[el2_ifu_mem_ctl.scala 680:119] + iccm_ecc_corr_data_ff <= _T_3872 @[el2_ifu_mem_ctl.scala 680:25] + node _T_3873 = bits(iccm_ecc_write_status, 0, 0) @[el2_ifu_mem_ctl.scala 681:119] reg _T_3874 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_3873 : @[Reg.scala 28:19] _T_3874 <= iccm_ecc_corr_index_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - iccm_ecc_corr_index_ff <= _T_3874 @[el2_ifu_mem_ctl.scala 680:26] - node _T_3875 = eq(io.ifc_fetch_uncacheable_bf, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 681:41] - node _T_3876 = and(io.ifc_fetch_req_bf, _T_3875) @[el2_ifu_mem_ctl.scala 681:39] - node _T_3877 = eq(io.ifc_iccm_access_bf, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 681:72] - node _T_3878 = and(_T_3876, _T_3877) @[el2_ifu_mem_ctl.scala 681:70] - node _T_3879 = eq(miss_state, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 682:19] - node _T_3880 = eq(miss_state_en, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 682:34] - node _T_3881 = and(_T_3879, _T_3880) @[el2_ifu_mem_ctl.scala 682:32] - node _T_3882 = eq(miss_state, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 683:19] - node _T_3883 = eq(miss_state_en, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 683:39] - node _T_3884 = and(_T_3882, _T_3883) @[el2_ifu_mem_ctl.scala 683:37] - node _T_3885 = or(_T_3881, _T_3884) @[el2_ifu_mem_ctl.scala 682:88] - node _T_3886 = eq(miss_state, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 684:19] - node _T_3887 = eq(miss_state_en, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 684:43] - node _T_3888 = and(_T_3886, _T_3887) @[el2_ifu_mem_ctl.scala 684:41] - node _T_3889 = or(_T_3885, _T_3888) @[el2_ifu_mem_ctl.scala 683:88] - node _T_3890 = eq(miss_state, UInt<3>("h03")) @[el2_ifu_mem_ctl.scala 685:19] - node _T_3891 = eq(miss_state_en, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 685:37] - node _T_3892 = and(_T_3890, _T_3891) @[el2_ifu_mem_ctl.scala 685:35] - node _T_3893 = or(_T_3889, _T_3892) @[el2_ifu_mem_ctl.scala 684:88] - node _T_3894 = eq(miss_state, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 686:19] - node _T_3895 = eq(miss_state_en, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 686:40] - node _T_3896 = and(_T_3894, _T_3895) @[el2_ifu_mem_ctl.scala 686:38] - node _T_3897 = or(_T_3893, _T_3896) @[el2_ifu_mem_ctl.scala 685:88] - node _T_3898 = eq(miss_state, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 687:19] - node _T_3899 = and(_T_3898, miss_state_en) @[el2_ifu_mem_ctl.scala 687:37] - node _T_3900 = eq(miss_nxtstate, UInt<3>("h03")) @[el2_ifu_mem_ctl.scala 687:71] - node _T_3901 = and(_T_3899, _T_3900) @[el2_ifu_mem_ctl.scala 687:54] - node _T_3902 = or(_T_3897, _T_3901) @[el2_ifu_mem_ctl.scala 686:57] - node _T_3903 = eq(_T_3902, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 682:5] - node _T_3904 = and(_T_3878, _T_3903) @[el2_ifu_mem_ctl.scala 681:96] - node _T_3905 = and(io.ifc_fetch_req_bf, io.exu_flush_final) @[el2_ifu_mem_ctl.scala 688:28] - node _T_3906 = eq(io.ifc_fetch_uncacheable_bf, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 688:52] - node _T_3907 = and(_T_3905, _T_3906) @[el2_ifu_mem_ctl.scala 688:50] - node _T_3908 = eq(io.ifc_iccm_access_bf, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 688:83] - node _T_3909 = and(_T_3907, _T_3908) @[el2_ifu_mem_ctl.scala 688:81] - node _T_3910 = or(_T_3904, _T_3909) @[el2_ifu_mem_ctl.scala 687:93] - io.ic_rd_en <= _T_3910 @[el2_ifu_mem_ctl.scala 681:15] + iccm_ecc_corr_index_ff <= _T_3874 @[el2_ifu_mem_ctl.scala 681:26] + node _T_3875 = eq(io.ifc_fetch_uncacheable_bf, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 682:41] + node _T_3876 = and(io.ifc_fetch_req_bf, _T_3875) @[el2_ifu_mem_ctl.scala 682:39] + node _T_3877 = eq(io.ifc_iccm_access_bf, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 682:72] + node _T_3878 = and(_T_3876, _T_3877) @[el2_ifu_mem_ctl.scala 682:70] + node _T_3879 = eq(miss_state, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 683:19] + node _T_3880 = eq(miss_state_en, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 683:34] + node _T_3881 = and(_T_3879, _T_3880) @[el2_ifu_mem_ctl.scala 683:32] + node _T_3882 = eq(miss_state, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 684:19] + node _T_3883 = eq(miss_state_en, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 684:39] + node _T_3884 = and(_T_3882, _T_3883) @[el2_ifu_mem_ctl.scala 684:37] + node _T_3885 = or(_T_3881, _T_3884) @[el2_ifu_mem_ctl.scala 683:88] + node _T_3886 = eq(miss_state, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 685:19] + node _T_3887 = eq(miss_state_en, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 685:43] + node _T_3888 = and(_T_3886, _T_3887) @[el2_ifu_mem_ctl.scala 685:41] + node _T_3889 = or(_T_3885, _T_3888) @[el2_ifu_mem_ctl.scala 684:88] + node _T_3890 = eq(miss_state, UInt<3>("h03")) @[el2_ifu_mem_ctl.scala 686:19] + node _T_3891 = eq(miss_state_en, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 686:37] + node _T_3892 = and(_T_3890, _T_3891) @[el2_ifu_mem_ctl.scala 686:35] + node _T_3893 = or(_T_3889, _T_3892) @[el2_ifu_mem_ctl.scala 685:88] + node _T_3894 = eq(miss_state, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 687:19] + node _T_3895 = eq(miss_state_en, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 687:40] + node _T_3896 = and(_T_3894, _T_3895) @[el2_ifu_mem_ctl.scala 687:38] + node _T_3897 = or(_T_3893, _T_3896) @[el2_ifu_mem_ctl.scala 686:88] + node _T_3898 = eq(miss_state, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 688:19] + node _T_3899 = and(_T_3898, miss_state_en) @[el2_ifu_mem_ctl.scala 688:37] + node _T_3900 = eq(miss_nxtstate, UInt<3>("h03")) @[el2_ifu_mem_ctl.scala 688:71] + node _T_3901 = and(_T_3899, _T_3900) @[el2_ifu_mem_ctl.scala 688:54] + node _T_3902 = or(_T_3897, _T_3901) @[el2_ifu_mem_ctl.scala 687:57] + node _T_3903 = eq(_T_3902, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 683:5] + node _T_3904 = and(_T_3878, _T_3903) @[el2_ifu_mem_ctl.scala 682:96] + node _T_3905 = and(io.ifc_fetch_req_bf, io.exu_flush_final) @[el2_ifu_mem_ctl.scala 689:28] + node _T_3906 = eq(io.ifc_fetch_uncacheable_bf, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 689:52] + node _T_3907 = and(_T_3905, _T_3906) @[el2_ifu_mem_ctl.scala 689:50] + node _T_3908 = eq(io.ifc_iccm_access_bf, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 689:83] + node _T_3909 = and(_T_3907, _T_3908) @[el2_ifu_mem_ctl.scala 689:81] + node _T_3910 = or(_T_3904, _T_3909) @[el2_ifu_mem_ctl.scala 688:93] + io.ic_rd_en <= _T_3910 @[el2_ifu_mem_ctl.scala 682:15] wire bus_ic_wr_en : UInt<1> bus_ic_wr_en <= UInt<1>("h00") node _T_3911 = bits(write_ic_16_bytes, 0, 0) @[Bitwise.scala 72:15] node _T_3912 = mux(_T_3911, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_3913 = and(bus_ic_wr_en, _T_3912) @[el2_ifu_mem_ctl.scala 690:31] - io.ic_wr_en <= _T_3913 @[el2_ifu_mem_ctl.scala 690:15] - node _T_3914 = eq(miss_state, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 691:59] - node _T_3915 = eq(miss_state, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 691:91] - node _T_3916 = or(io.exu_flush_final, ifu_bp_hit_taken_q_f) @[el2_ifu_mem_ctl.scala 691:127] - node _T_3917 = or(_T_3916, stream_eol_f) @[el2_ifu_mem_ctl.scala 691:151] - node _T_3918 = eq(_T_3917, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 691:106] - node _T_3919 = and(_T_3915, _T_3918) @[el2_ifu_mem_ctl.scala 691:104] - node _T_3920 = or(_T_3914, _T_3919) @[el2_ifu_mem_ctl.scala 691:77] - node _T_3921 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 691:191] - node _T_3922 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 691:205] - node _T_3923 = and(_T_3921, _T_3922) @[el2_ifu_mem_ctl.scala 691:203] - node _T_3924 = eq(_T_3923, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 691:172] - node _T_3925 = and(_T_3920, _T_3924) @[el2_ifu_mem_ctl.scala 691:170] - node _T_3926 = eq(_T_3925, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 691:44] - node _T_3927 = and(write_ic_16_bytes, _T_3926) @[el2_ifu_mem_ctl.scala 691:42] - io.ic_write_stall <= _T_3927 @[el2_ifu_mem_ctl.scala 691:21] - reg _T_3928 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 692:53] - _T_3928 <= io.dec_tlu_fence_i_wb @[el2_ifu_mem_ctl.scala 692:53] - reset_all_tags <= _T_3928 @[el2_ifu_mem_ctl.scala 692:18] - node _T_3929 = eq(ifu_wr_cumulative_err_data, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 694:20] - node _T_3930 = or(reset_ic_in, reset_ic_ff) @[el2_ifu_mem_ctl.scala 694:64] - node _T_3931 = eq(_T_3930, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 694:50] - node _T_3932 = and(_T_3929, _T_3931) @[el2_ifu_mem_ctl.scala 694:48] - node _T_3933 = eq(reset_tag_valid_for_miss, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 694:81] - node ic_valid = and(_T_3932, _T_3933) @[el2_ifu_mem_ctl.scala 694:79] - node _T_3934 = or(io.ic_debug_rd_en, io.ic_debug_wr_en) @[el2_ifu_mem_ctl.scala 695:61] - node _T_3935 = and(_T_3934, io.ic_debug_tag_array) @[el2_ifu_mem_ctl.scala 695:82] - node _T_3936 = bits(io.ic_debug_addr, 9, 3) @[el2_ifu_mem_ctl.scala 695:123] - node _T_3937 = bits(ifu_status_wr_addr, 11, 5) @[el2_ifu_mem_ctl.scala 696:25] - node ifu_status_wr_addr_w_debug = mux(_T_3935, _T_3936, _T_3937) @[el2_ifu_mem_ctl.scala 695:41] - reg ifu_status_wr_addr_ff : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 698:14] - ifu_status_wr_addr_ff <= ifu_status_wr_addr_w_debug @[el2_ifu_mem_ctl.scala 698:14] + node _T_3913 = and(bus_ic_wr_en, _T_3912) @[el2_ifu_mem_ctl.scala 691:31] + io.ic_wr_en <= _T_3913 @[el2_ifu_mem_ctl.scala 691:15] + node _T_3914 = eq(miss_state, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 692:59] + node _T_3915 = eq(miss_state, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 692:91] + node _T_3916 = or(io.exu_flush_final, ifu_bp_hit_taken_q_f) @[el2_ifu_mem_ctl.scala 692:127] + node _T_3917 = or(_T_3916, stream_eol_f) @[el2_ifu_mem_ctl.scala 692:151] + node _T_3918 = eq(_T_3917, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 692:106] + node _T_3919 = and(_T_3915, _T_3918) @[el2_ifu_mem_ctl.scala 692:104] + node _T_3920 = or(_T_3914, _T_3919) @[el2_ifu_mem_ctl.scala 692:77] + node _T_3921 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 692:191] + node _T_3922 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 692:205] + node _T_3923 = and(_T_3921, _T_3922) @[el2_ifu_mem_ctl.scala 692:203] + node _T_3924 = eq(_T_3923, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 692:172] + node _T_3925 = and(_T_3920, _T_3924) @[el2_ifu_mem_ctl.scala 692:170] + node _T_3926 = eq(_T_3925, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 692:44] + node _T_3927 = and(write_ic_16_bytes, _T_3926) @[el2_ifu_mem_ctl.scala 692:42] + io.ic_write_stall <= _T_3927 @[el2_ifu_mem_ctl.scala 692:21] + reg _T_3928 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 693:53] + _T_3928 <= io.dec_tlu_fence_i_wb @[el2_ifu_mem_ctl.scala 693:53] + reset_all_tags <= _T_3928 @[el2_ifu_mem_ctl.scala 693:18] + node _T_3929 = eq(ifu_wr_cumulative_err_data, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 695:20] + node _T_3930 = or(reset_ic_in, reset_ic_ff) @[el2_ifu_mem_ctl.scala 695:64] + node _T_3931 = eq(_T_3930, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 695:50] + node _T_3932 = and(_T_3929, _T_3931) @[el2_ifu_mem_ctl.scala 695:48] + node _T_3933 = eq(reset_tag_valid_for_miss, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 695:81] + node ic_valid = and(_T_3932, _T_3933) @[el2_ifu_mem_ctl.scala 695:79] + node _T_3934 = or(io.ic_debug_rd_en, io.ic_debug_wr_en) @[el2_ifu_mem_ctl.scala 696:61] + node _T_3935 = and(_T_3934, io.ic_debug_tag_array) @[el2_ifu_mem_ctl.scala 696:82] + node _T_3936 = bits(io.ic_debug_addr, 9, 3) @[el2_ifu_mem_ctl.scala 696:123] + node _T_3937 = bits(ifu_status_wr_addr, 11, 5) @[el2_ifu_mem_ctl.scala 697:25] + node ifu_status_wr_addr_w_debug = mux(_T_3935, _T_3936, _T_3937) @[el2_ifu_mem_ctl.scala 696:41] + reg ifu_status_wr_addr_ff : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 699:14] + ifu_status_wr_addr_ff <= ifu_status_wr_addr_w_debug @[el2_ifu_mem_ctl.scala 699:14] wire way_status_wr_en : UInt<1> way_status_wr_en <= UInt<1>("h00") - node _T_3938 = and(io.ic_debug_wr_en, io.ic_debug_tag_array) @[el2_ifu_mem_ctl.scala 701:74] - node way_status_wr_en_w_debug = or(way_status_wr_en, _T_3938) @[el2_ifu_mem_ctl.scala 701:53] - reg way_status_wr_en_ff : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 703:14] - way_status_wr_en_ff <= way_status_wr_en_w_debug @[el2_ifu_mem_ctl.scala 703:14] + node _T_3938 = and(io.ic_debug_wr_en, io.ic_debug_tag_array) @[el2_ifu_mem_ctl.scala 702:74] + node way_status_wr_en_w_debug = or(way_status_wr_en, _T_3938) @[el2_ifu_mem_ctl.scala 702:53] + reg way_status_wr_en_ff : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 704:14] + way_status_wr_en_ff <= way_status_wr_en_w_debug @[el2_ifu_mem_ctl.scala 704:14] wire way_status_new : UInt<1> way_status_new <= UInt<1>("h00") - node _T_3939 = and(io.ic_debug_wr_en, io.ic_debug_tag_array) @[el2_ifu_mem_ctl.scala 706:56] - node _T_3940 = bits(io.ic_debug_wr_data, 4, 4) @[el2_ifu_mem_ctl.scala 707:59] - node _T_3941 = bits(io.ic_debug_wr_data, 6, 4) @[el2_ifu_mem_ctl.scala 707:83] - node _T_3942 = mux(UInt<1>("h01"), _T_3940, _T_3941) @[el2_ifu_mem_ctl.scala 707:10] - node way_status_new_w_debug = mux(_T_3939, _T_3942, way_status_new) @[el2_ifu_mem_ctl.scala 706:37] - reg way_status_new_ff : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 709:14] - way_status_new_ff <= way_status_new_w_debug @[el2_ifu_mem_ctl.scala 709:14] - node _T_3943 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 711:89] - node way_status_clken_0 = eq(_T_3943, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 711:132] - node _T_3944 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 711:89] - node way_status_clken_1 = eq(_T_3944, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 711:132] - node _T_3945 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 711:89] - node way_status_clken_2 = eq(_T_3945, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 711:132] - node _T_3946 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 711:89] - node way_status_clken_3 = eq(_T_3946, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 711:132] - node _T_3947 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 711:89] - node way_status_clken_4 = eq(_T_3947, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 711:132] - node _T_3948 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 711:89] - node way_status_clken_5 = eq(_T_3948, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 711:132] - node _T_3949 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 711:89] - node way_status_clken_6 = eq(_T_3949, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 711:132] - node _T_3950 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 711:89] - node way_status_clken_7 = eq(_T_3950, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 711:132] - node _T_3951 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 711:89] - node way_status_clken_8 = eq(_T_3951, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 711:132] - node _T_3952 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 711:89] - node way_status_clken_9 = eq(_T_3952, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 711:132] - node _T_3953 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 711:89] - node way_status_clken_10 = eq(_T_3953, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 711:132] - node _T_3954 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 711:89] - node way_status_clken_11 = eq(_T_3954, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 711:132] - node _T_3955 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 711:89] - node way_status_clken_12 = eq(_T_3955, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 711:132] - node _T_3956 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 711:89] - node way_status_clken_13 = eq(_T_3956, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 711:132] - node _T_3957 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 711:89] - node way_status_clken_14 = eq(_T_3957, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 711:132] - node _T_3958 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 711:89] - node way_status_clken_15 = eq(_T_3958, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 711:132] - wire way_status_out : UInt<1>[128] @[el2_ifu_mem_ctl.scala 713:30] - node _T_3959 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_3960 = and(_T_3959, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_3961 = and(_T_3960, way_status_clken_0) @[el2_ifu_mem_ctl.scala 715:124] + node _T_3939 = and(io.ic_debug_wr_en, io.ic_debug_tag_array) @[el2_ifu_mem_ctl.scala 707:56] + node _T_3940 = bits(io.ic_debug_wr_data, 4, 4) @[el2_ifu_mem_ctl.scala 708:59] + node _T_3941 = bits(io.ic_debug_wr_data, 6, 4) @[el2_ifu_mem_ctl.scala 708:83] + node _T_3942 = mux(UInt<1>("h01"), _T_3940, _T_3941) @[el2_ifu_mem_ctl.scala 708:10] + node way_status_new_w_debug = mux(_T_3939, _T_3942, way_status_new) @[el2_ifu_mem_ctl.scala 707:37] + reg way_status_new_ff : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 710:14] + way_status_new_ff <= way_status_new_w_debug @[el2_ifu_mem_ctl.scala 710:14] + node _T_3943 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 712:89] + node way_status_clken_0 = eq(_T_3943, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 712:132] + node _T_3944 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 712:89] + node way_status_clken_1 = eq(_T_3944, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 712:132] + node _T_3945 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 712:89] + node way_status_clken_2 = eq(_T_3945, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 712:132] + node _T_3946 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 712:89] + node way_status_clken_3 = eq(_T_3946, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 712:132] + node _T_3947 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 712:89] + node way_status_clken_4 = eq(_T_3947, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 712:132] + node _T_3948 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 712:89] + node way_status_clken_5 = eq(_T_3948, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 712:132] + node _T_3949 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 712:89] + node way_status_clken_6 = eq(_T_3949, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 712:132] + node _T_3950 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 712:89] + node way_status_clken_7 = eq(_T_3950, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 712:132] + node _T_3951 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 712:89] + node way_status_clken_8 = eq(_T_3951, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 712:132] + node _T_3952 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 712:89] + node way_status_clken_9 = eq(_T_3952, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 712:132] + node _T_3953 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 712:89] + node way_status_clken_10 = eq(_T_3953, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 712:132] + node _T_3954 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 712:89] + node way_status_clken_11 = eq(_T_3954, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 712:132] + node _T_3955 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 712:89] + node way_status_clken_12 = eq(_T_3955, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 712:132] + node _T_3956 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 712:89] + node way_status_clken_13 = eq(_T_3956, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 712:132] + node _T_3957 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 712:89] + node way_status_clken_14 = eq(_T_3957, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 712:132] + node _T_3958 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 712:89] + node way_status_clken_15 = eq(_T_3958, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 712:132] + wire way_status_out : UInt<1>[128] @[el2_ifu_mem_ctl.scala 714:30] + node _T_3959 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_3960 = and(_T_3959, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_3961 = and(_T_3960, way_status_clken_0) @[el2_ifu_mem_ctl.scala 716:124] reg _T_3962 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_3961 : @[Reg.scala 28:19] _T_3962 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[0] <= _T_3962 @[el2_ifu_mem_ctl.scala 715:33] - node _T_3963 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_3964 = and(_T_3963, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_3965 = and(_T_3964, way_status_clken_0) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[0] <= _T_3962 @[el2_ifu_mem_ctl.scala 716:33] + node _T_3963 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_3964 = and(_T_3963, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_3965 = and(_T_3964, way_status_clken_0) @[el2_ifu_mem_ctl.scala 716:124] reg _T_3966 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_3965 : @[Reg.scala 28:19] _T_3966 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[1] <= _T_3966 @[el2_ifu_mem_ctl.scala 715:33] - node _T_3967 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_3968 = and(_T_3967, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_3969 = and(_T_3968, way_status_clken_0) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[1] <= _T_3966 @[el2_ifu_mem_ctl.scala 716:33] + node _T_3967 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_3968 = and(_T_3967, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_3969 = and(_T_3968, way_status_clken_0) @[el2_ifu_mem_ctl.scala 716:124] reg _T_3970 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_3969 : @[Reg.scala 28:19] _T_3970 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[2] <= _T_3970 @[el2_ifu_mem_ctl.scala 715:33] - node _T_3971 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_3972 = and(_T_3971, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_3973 = and(_T_3972, way_status_clken_0) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[2] <= _T_3970 @[el2_ifu_mem_ctl.scala 716:33] + node _T_3971 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_3972 = and(_T_3971, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_3973 = and(_T_3972, way_status_clken_0) @[el2_ifu_mem_ctl.scala 716:124] reg _T_3974 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_3973 : @[Reg.scala 28:19] _T_3974 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[3] <= _T_3974 @[el2_ifu_mem_ctl.scala 715:33] - node _T_3975 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_3976 = and(_T_3975, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_3977 = and(_T_3976, way_status_clken_0) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[3] <= _T_3974 @[el2_ifu_mem_ctl.scala 716:33] + node _T_3975 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_3976 = and(_T_3975, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_3977 = and(_T_3976, way_status_clken_0) @[el2_ifu_mem_ctl.scala 716:124] reg _T_3978 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_3977 : @[Reg.scala 28:19] _T_3978 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[4] <= _T_3978 @[el2_ifu_mem_ctl.scala 715:33] - node _T_3979 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_3980 = and(_T_3979, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_3981 = and(_T_3980, way_status_clken_0) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[4] <= _T_3978 @[el2_ifu_mem_ctl.scala 716:33] + node _T_3979 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_3980 = and(_T_3979, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_3981 = and(_T_3980, way_status_clken_0) @[el2_ifu_mem_ctl.scala 716:124] reg _T_3982 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_3981 : @[Reg.scala 28:19] _T_3982 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[5] <= _T_3982 @[el2_ifu_mem_ctl.scala 715:33] - node _T_3983 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_3984 = and(_T_3983, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_3985 = and(_T_3984, way_status_clken_0) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[5] <= _T_3982 @[el2_ifu_mem_ctl.scala 716:33] + node _T_3983 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_3984 = and(_T_3983, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_3985 = and(_T_3984, way_status_clken_0) @[el2_ifu_mem_ctl.scala 716:124] reg _T_3986 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_3985 : @[Reg.scala 28:19] _T_3986 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[6] <= _T_3986 @[el2_ifu_mem_ctl.scala 715:33] - node _T_3987 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_3988 = and(_T_3987, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_3989 = and(_T_3988, way_status_clken_0) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[6] <= _T_3986 @[el2_ifu_mem_ctl.scala 716:33] + node _T_3987 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_3988 = and(_T_3987, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_3989 = and(_T_3988, way_status_clken_0) @[el2_ifu_mem_ctl.scala 716:124] reg _T_3990 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_3989 : @[Reg.scala 28:19] _T_3990 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[7] <= _T_3990 @[el2_ifu_mem_ctl.scala 715:33] - node _T_3991 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_3992 = and(_T_3991, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_3993 = and(_T_3992, way_status_clken_1) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[7] <= _T_3990 @[el2_ifu_mem_ctl.scala 716:33] + node _T_3991 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_3992 = and(_T_3991, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_3993 = and(_T_3992, way_status_clken_1) @[el2_ifu_mem_ctl.scala 716:124] reg _T_3994 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_3993 : @[Reg.scala 28:19] _T_3994 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[8] <= _T_3994 @[el2_ifu_mem_ctl.scala 715:33] - node _T_3995 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_3996 = and(_T_3995, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_3997 = and(_T_3996, way_status_clken_1) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[8] <= _T_3994 @[el2_ifu_mem_ctl.scala 716:33] + node _T_3995 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_3996 = and(_T_3995, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_3997 = and(_T_3996, way_status_clken_1) @[el2_ifu_mem_ctl.scala 716:124] reg _T_3998 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_3997 : @[Reg.scala 28:19] _T_3998 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[9] <= _T_3998 @[el2_ifu_mem_ctl.scala 715:33] - node _T_3999 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4000 = and(_T_3999, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4001 = and(_T_4000, way_status_clken_1) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[9] <= _T_3998 @[el2_ifu_mem_ctl.scala 716:33] + node _T_3999 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4000 = and(_T_3999, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4001 = and(_T_4000, way_status_clken_1) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4002 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4001 : @[Reg.scala 28:19] _T_4002 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[10] <= _T_4002 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4003 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4004 = and(_T_4003, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4005 = and(_T_4004, way_status_clken_1) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[10] <= _T_4002 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4003 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4004 = and(_T_4003, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4005 = and(_T_4004, way_status_clken_1) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4006 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4005 : @[Reg.scala 28:19] _T_4006 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[11] <= _T_4006 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4007 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4008 = and(_T_4007, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4009 = and(_T_4008, way_status_clken_1) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[11] <= _T_4006 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4007 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4008 = and(_T_4007, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4009 = and(_T_4008, way_status_clken_1) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4010 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4009 : @[Reg.scala 28:19] _T_4010 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[12] <= _T_4010 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4011 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4012 = and(_T_4011, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4013 = and(_T_4012, way_status_clken_1) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[12] <= _T_4010 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4011 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4012 = and(_T_4011, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4013 = and(_T_4012, way_status_clken_1) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4014 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4013 : @[Reg.scala 28:19] _T_4014 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[13] <= _T_4014 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4015 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4016 = and(_T_4015, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4017 = and(_T_4016, way_status_clken_1) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[13] <= _T_4014 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4015 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4016 = and(_T_4015, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4017 = and(_T_4016, way_status_clken_1) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4018 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4017 : @[Reg.scala 28:19] _T_4018 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[14] <= _T_4018 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4019 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4020 = and(_T_4019, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4021 = and(_T_4020, way_status_clken_1) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[14] <= _T_4018 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4019 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4020 = and(_T_4019, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4021 = and(_T_4020, way_status_clken_1) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4022 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4021 : @[Reg.scala 28:19] _T_4022 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[15] <= _T_4022 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4023 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4024 = and(_T_4023, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4025 = and(_T_4024, way_status_clken_2) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[15] <= _T_4022 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4023 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4024 = and(_T_4023, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4025 = and(_T_4024, way_status_clken_2) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4026 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4025 : @[Reg.scala 28:19] _T_4026 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[16] <= _T_4026 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4027 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4028 = and(_T_4027, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4029 = and(_T_4028, way_status_clken_2) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[16] <= _T_4026 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4027 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4028 = and(_T_4027, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4029 = and(_T_4028, way_status_clken_2) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4030 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4029 : @[Reg.scala 28:19] _T_4030 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[17] <= _T_4030 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4031 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4032 = and(_T_4031, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4033 = and(_T_4032, way_status_clken_2) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[17] <= _T_4030 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4031 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4032 = and(_T_4031, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4033 = and(_T_4032, way_status_clken_2) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4034 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4033 : @[Reg.scala 28:19] _T_4034 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[18] <= _T_4034 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4035 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4036 = and(_T_4035, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4037 = and(_T_4036, way_status_clken_2) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[18] <= _T_4034 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4035 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4036 = and(_T_4035, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4037 = and(_T_4036, way_status_clken_2) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4038 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4037 : @[Reg.scala 28:19] _T_4038 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[19] <= _T_4038 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4039 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4040 = and(_T_4039, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4041 = and(_T_4040, way_status_clken_2) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[19] <= _T_4038 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4039 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4040 = and(_T_4039, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4041 = and(_T_4040, way_status_clken_2) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4042 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4041 : @[Reg.scala 28:19] _T_4042 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[20] <= _T_4042 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4043 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4044 = and(_T_4043, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4045 = and(_T_4044, way_status_clken_2) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[20] <= _T_4042 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4043 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4044 = and(_T_4043, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4045 = and(_T_4044, way_status_clken_2) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4046 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4045 : @[Reg.scala 28:19] _T_4046 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[21] <= _T_4046 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4047 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4048 = and(_T_4047, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4049 = and(_T_4048, way_status_clken_2) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[21] <= _T_4046 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4047 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4048 = and(_T_4047, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4049 = and(_T_4048, way_status_clken_2) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4050 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4049 : @[Reg.scala 28:19] _T_4050 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[22] <= _T_4050 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4051 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4052 = and(_T_4051, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4053 = and(_T_4052, way_status_clken_2) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[22] <= _T_4050 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4051 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4052 = and(_T_4051, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4053 = and(_T_4052, way_status_clken_2) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4054 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4053 : @[Reg.scala 28:19] _T_4054 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[23] <= _T_4054 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4055 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4056 = and(_T_4055, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4057 = and(_T_4056, way_status_clken_3) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[23] <= _T_4054 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4055 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4056 = and(_T_4055, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4057 = and(_T_4056, way_status_clken_3) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4058 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4057 : @[Reg.scala 28:19] _T_4058 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[24] <= _T_4058 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4059 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4060 = and(_T_4059, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4061 = and(_T_4060, way_status_clken_3) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[24] <= _T_4058 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4059 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4060 = and(_T_4059, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4061 = and(_T_4060, way_status_clken_3) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4062 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4061 : @[Reg.scala 28:19] _T_4062 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[25] <= _T_4062 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4063 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4064 = and(_T_4063, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4065 = and(_T_4064, way_status_clken_3) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[25] <= _T_4062 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4063 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4064 = and(_T_4063, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4065 = and(_T_4064, way_status_clken_3) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4066 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4065 : @[Reg.scala 28:19] _T_4066 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[26] <= _T_4066 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4067 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4068 = and(_T_4067, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4069 = and(_T_4068, way_status_clken_3) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[26] <= _T_4066 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4067 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4068 = and(_T_4067, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4069 = and(_T_4068, way_status_clken_3) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4070 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4069 : @[Reg.scala 28:19] _T_4070 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[27] <= _T_4070 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4071 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4072 = and(_T_4071, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4073 = and(_T_4072, way_status_clken_3) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[27] <= _T_4070 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4071 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4072 = and(_T_4071, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4073 = and(_T_4072, way_status_clken_3) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4074 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4073 : @[Reg.scala 28:19] _T_4074 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[28] <= _T_4074 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4075 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4076 = and(_T_4075, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4077 = and(_T_4076, way_status_clken_3) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[28] <= _T_4074 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4075 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4076 = and(_T_4075, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4077 = and(_T_4076, way_status_clken_3) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4078 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4077 : @[Reg.scala 28:19] _T_4078 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[29] <= _T_4078 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4079 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4080 = and(_T_4079, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4081 = and(_T_4080, way_status_clken_3) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[29] <= _T_4078 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4079 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4080 = and(_T_4079, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4081 = and(_T_4080, way_status_clken_3) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4082 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4081 : @[Reg.scala 28:19] _T_4082 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[30] <= _T_4082 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4083 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4084 = and(_T_4083, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4085 = and(_T_4084, way_status_clken_3) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[30] <= _T_4082 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4083 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4084 = and(_T_4083, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4085 = and(_T_4084, way_status_clken_3) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4086 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4085 : @[Reg.scala 28:19] _T_4086 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[31] <= _T_4086 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4087 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4088 = and(_T_4087, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4089 = and(_T_4088, way_status_clken_4) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[31] <= _T_4086 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4087 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4088 = and(_T_4087, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4089 = and(_T_4088, way_status_clken_4) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4090 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4089 : @[Reg.scala 28:19] _T_4090 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[32] <= _T_4090 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4091 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4092 = and(_T_4091, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4093 = and(_T_4092, way_status_clken_4) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[32] <= _T_4090 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4091 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4092 = and(_T_4091, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4093 = and(_T_4092, way_status_clken_4) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4094 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4093 : @[Reg.scala 28:19] _T_4094 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[33] <= _T_4094 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4095 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4096 = and(_T_4095, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4097 = and(_T_4096, way_status_clken_4) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[33] <= _T_4094 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4095 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4096 = and(_T_4095, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4097 = and(_T_4096, way_status_clken_4) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4098 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4097 : @[Reg.scala 28:19] _T_4098 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[34] <= _T_4098 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4099 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4100 = and(_T_4099, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4101 = and(_T_4100, way_status_clken_4) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[34] <= _T_4098 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4099 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4100 = and(_T_4099, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4101 = and(_T_4100, way_status_clken_4) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4102 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4101 : @[Reg.scala 28:19] _T_4102 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[35] <= _T_4102 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4103 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4104 = and(_T_4103, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4105 = and(_T_4104, way_status_clken_4) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[35] <= _T_4102 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4103 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4104 = and(_T_4103, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4105 = and(_T_4104, way_status_clken_4) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4106 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4105 : @[Reg.scala 28:19] _T_4106 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[36] <= _T_4106 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4107 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4108 = and(_T_4107, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4109 = and(_T_4108, way_status_clken_4) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[36] <= _T_4106 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4107 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4108 = and(_T_4107, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4109 = and(_T_4108, way_status_clken_4) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4110 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4109 : @[Reg.scala 28:19] _T_4110 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[37] <= _T_4110 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4111 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4112 = and(_T_4111, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4113 = and(_T_4112, way_status_clken_4) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[37] <= _T_4110 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4111 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4112 = and(_T_4111, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4113 = and(_T_4112, way_status_clken_4) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4114 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4113 : @[Reg.scala 28:19] _T_4114 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[38] <= _T_4114 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4115 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4116 = and(_T_4115, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4117 = and(_T_4116, way_status_clken_4) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[38] <= _T_4114 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4115 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4116 = and(_T_4115, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4117 = and(_T_4116, way_status_clken_4) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4118 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4117 : @[Reg.scala 28:19] _T_4118 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[39] <= _T_4118 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4119 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4120 = and(_T_4119, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4121 = and(_T_4120, way_status_clken_5) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[39] <= _T_4118 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4119 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4120 = and(_T_4119, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4121 = and(_T_4120, way_status_clken_5) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4122 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4121 : @[Reg.scala 28:19] _T_4122 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[40] <= _T_4122 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4123 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4124 = and(_T_4123, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4125 = and(_T_4124, way_status_clken_5) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[40] <= _T_4122 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4123 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4124 = and(_T_4123, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4125 = and(_T_4124, way_status_clken_5) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4126 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4125 : @[Reg.scala 28:19] _T_4126 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[41] <= _T_4126 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4127 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4128 = and(_T_4127, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4129 = and(_T_4128, way_status_clken_5) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[41] <= _T_4126 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4127 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4128 = and(_T_4127, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4129 = and(_T_4128, way_status_clken_5) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4130 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4129 : @[Reg.scala 28:19] _T_4130 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[42] <= _T_4130 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4131 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4132 = and(_T_4131, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4133 = and(_T_4132, way_status_clken_5) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[42] <= _T_4130 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4131 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4132 = and(_T_4131, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4133 = and(_T_4132, way_status_clken_5) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4134 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4133 : @[Reg.scala 28:19] _T_4134 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[43] <= _T_4134 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4135 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4136 = and(_T_4135, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4137 = and(_T_4136, way_status_clken_5) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[43] <= _T_4134 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4135 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4136 = and(_T_4135, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4137 = and(_T_4136, way_status_clken_5) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4138 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4137 : @[Reg.scala 28:19] _T_4138 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[44] <= _T_4138 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4139 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4140 = and(_T_4139, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4141 = and(_T_4140, way_status_clken_5) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[44] <= _T_4138 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4139 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4140 = and(_T_4139, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4141 = and(_T_4140, way_status_clken_5) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4142 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4141 : @[Reg.scala 28:19] _T_4142 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[45] <= _T_4142 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4143 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4144 = and(_T_4143, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4145 = and(_T_4144, way_status_clken_5) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[45] <= _T_4142 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4143 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4144 = and(_T_4143, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4145 = and(_T_4144, way_status_clken_5) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4146 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4145 : @[Reg.scala 28:19] _T_4146 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[46] <= _T_4146 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4147 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4148 = and(_T_4147, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4149 = and(_T_4148, way_status_clken_5) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[46] <= _T_4146 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4147 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4148 = and(_T_4147, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4149 = and(_T_4148, way_status_clken_5) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4150 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4149 : @[Reg.scala 28:19] _T_4150 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[47] <= _T_4150 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4151 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4152 = and(_T_4151, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4153 = and(_T_4152, way_status_clken_6) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[47] <= _T_4150 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4151 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4152 = and(_T_4151, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4153 = and(_T_4152, way_status_clken_6) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4154 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4153 : @[Reg.scala 28:19] _T_4154 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[48] <= _T_4154 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4155 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4156 = and(_T_4155, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4157 = and(_T_4156, way_status_clken_6) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[48] <= _T_4154 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4155 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4156 = and(_T_4155, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4157 = and(_T_4156, way_status_clken_6) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4158 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4157 : @[Reg.scala 28:19] _T_4158 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[49] <= _T_4158 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4159 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4160 = and(_T_4159, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4161 = and(_T_4160, way_status_clken_6) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[49] <= _T_4158 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4159 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4160 = and(_T_4159, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4161 = and(_T_4160, way_status_clken_6) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4162 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4161 : @[Reg.scala 28:19] _T_4162 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[50] <= _T_4162 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4163 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4164 = and(_T_4163, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4165 = and(_T_4164, way_status_clken_6) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[50] <= _T_4162 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4163 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4164 = and(_T_4163, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4165 = and(_T_4164, way_status_clken_6) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4166 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4165 : @[Reg.scala 28:19] _T_4166 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[51] <= _T_4166 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4167 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4168 = and(_T_4167, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4169 = and(_T_4168, way_status_clken_6) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[51] <= _T_4166 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4167 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4168 = and(_T_4167, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4169 = and(_T_4168, way_status_clken_6) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4170 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4169 : @[Reg.scala 28:19] _T_4170 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[52] <= _T_4170 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4171 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4172 = and(_T_4171, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4173 = and(_T_4172, way_status_clken_6) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[52] <= _T_4170 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4171 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4172 = and(_T_4171, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4173 = and(_T_4172, way_status_clken_6) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4174 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4173 : @[Reg.scala 28:19] _T_4174 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[53] <= _T_4174 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4175 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4176 = and(_T_4175, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4177 = and(_T_4176, way_status_clken_6) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[53] <= _T_4174 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4175 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4176 = and(_T_4175, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4177 = and(_T_4176, way_status_clken_6) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4178 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4177 : @[Reg.scala 28:19] _T_4178 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[54] <= _T_4178 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4179 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4180 = and(_T_4179, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4181 = and(_T_4180, way_status_clken_6) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[54] <= _T_4178 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4179 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4180 = and(_T_4179, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4181 = and(_T_4180, way_status_clken_6) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4182 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4181 : @[Reg.scala 28:19] _T_4182 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[55] <= _T_4182 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4183 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4184 = and(_T_4183, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4185 = and(_T_4184, way_status_clken_7) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[55] <= _T_4182 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4183 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4184 = and(_T_4183, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4185 = and(_T_4184, way_status_clken_7) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4186 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4185 : @[Reg.scala 28:19] _T_4186 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[56] <= _T_4186 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4187 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4188 = and(_T_4187, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4189 = and(_T_4188, way_status_clken_7) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[56] <= _T_4186 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4187 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4188 = and(_T_4187, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4189 = and(_T_4188, way_status_clken_7) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4190 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4189 : @[Reg.scala 28:19] _T_4190 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[57] <= _T_4190 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4191 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4192 = and(_T_4191, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4193 = and(_T_4192, way_status_clken_7) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[57] <= _T_4190 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4191 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4192 = and(_T_4191, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4193 = and(_T_4192, way_status_clken_7) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4194 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4193 : @[Reg.scala 28:19] _T_4194 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[58] <= _T_4194 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4195 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4196 = and(_T_4195, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4197 = and(_T_4196, way_status_clken_7) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[58] <= _T_4194 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4195 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4196 = and(_T_4195, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4197 = and(_T_4196, way_status_clken_7) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4198 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4197 : @[Reg.scala 28:19] _T_4198 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[59] <= _T_4198 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4199 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4200 = and(_T_4199, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4201 = and(_T_4200, way_status_clken_7) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[59] <= _T_4198 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4199 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4200 = and(_T_4199, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4201 = and(_T_4200, way_status_clken_7) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4202 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4201 : @[Reg.scala 28:19] _T_4202 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[60] <= _T_4202 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4203 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4204 = and(_T_4203, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4205 = and(_T_4204, way_status_clken_7) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[60] <= _T_4202 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4203 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4204 = and(_T_4203, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4205 = and(_T_4204, way_status_clken_7) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4206 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4205 : @[Reg.scala 28:19] _T_4206 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[61] <= _T_4206 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4207 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4208 = and(_T_4207, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4209 = and(_T_4208, way_status_clken_7) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[61] <= _T_4206 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4207 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4208 = and(_T_4207, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4209 = and(_T_4208, way_status_clken_7) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4210 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4209 : @[Reg.scala 28:19] _T_4210 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[62] <= _T_4210 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4211 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4212 = and(_T_4211, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4213 = and(_T_4212, way_status_clken_7) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[62] <= _T_4210 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4211 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4212 = and(_T_4211, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4213 = and(_T_4212, way_status_clken_7) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4214 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4213 : @[Reg.scala 28:19] _T_4214 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[63] <= _T_4214 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4215 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4216 = and(_T_4215, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4217 = and(_T_4216, way_status_clken_8) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[63] <= _T_4214 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4215 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4216 = and(_T_4215, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4217 = and(_T_4216, way_status_clken_8) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4218 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4217 : @[Reg.scala 28:19] _T_4218 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[64] <= _T_4218 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4219 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4220 = and(_T_4219, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4221 = and(_T_4220, way_status_clken_8) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[64] <= _T_4218 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4219 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4220 = and(_T_4219, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4221 = and(_T_4220, way_status_clken_8) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4222 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4221 : @[Reg.scala 28:19] _T_4222 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[65] <= _T_4222 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4223 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4224 = and(_T_4223, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4225 = and(_T_4224, way_status_clken_8) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[65] <= _T_4222 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4223 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4224 = and(_T_4223, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4225 = and(_T_4224, way_status_clken_8) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4226 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4225 : @[Reg.scala 28:19] _T_4226 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[66] <= _T_4226 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4227 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4228 = and(_T_4227, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4229 = and(_T_4228, way_status_clken_8) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[66] <= _T_4226 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4227 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4228 = and(_T_4227, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4229 = and(_T_4228, way_status_clken_8) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4230 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4229 : @[Reg.scala 28:19] _T_4230 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[67] <= _T_4230 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4231 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4232 = and(_T_4231, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4233 = and(_T_4232, way_status_clken_8) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[67] <= _T_4230 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4231 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4232 = and(_T_4231, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4233 = and(_T_4232, way_status_clken_8) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4234 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4233 : @[Reg.scala 28:19] _T_4234 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[68] <= _T_4234 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4235 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4236 = and(_T_4235, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4237 = and(_T_4236, way_status_clken_8) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[68] <= _T_4234 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4235 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4236 = and(_T_4235, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4237 = and(_T_4236, way_status_clken_8) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4238 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4237 : @[Reg.scala 28:19] _T_4238 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[69] <= _T_4238 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4239 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4240 = and(_T_4239, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4241 = and(_T_4240, way_status_clken_8) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[69] <= _T_4238 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4239 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4240 = and(_T_4239, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4241 = and(_T_4240, way_status_clken_8) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4242 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4241 : @[Reg.scala 28:19] _T_4242 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[70] <= _T_4242 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4243 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4244 = and(_T_4243, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4245 = and(_T_4244, way_status_clken_8) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[70] <= _T_4242 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4243 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4244 = and(_T_4243, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4245 = and(_T_4244, way_status_clken_8) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4246 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4245 : @[Reg.scala 28:19] _T_4246 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[71] <= _T_4246 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4247 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4248 = and(_T_4247, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4249 = and(_T_4248, way_status_clken_9) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[71] <= _T_4246 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4247 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4248 = and(_T_4247, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4249 = and(_T_4248, way_status_clken_9) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4250 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4249 : @[Reg.scala 28:19] _T_4250 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[72] <= _T_4250 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4251 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4252 = and(_T_4251, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4253 = and(_T_4252, way_status_clken_9) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[72] <= _T_4250 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4251 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4252 = and(_T_4251, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4253 = and(_T_4252, way_status_clken_9) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4254 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4253 : @[Reg.scala 28:19] _T_4254 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[73] <= _T_4254 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4255 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4256 = and(_T_4255, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4257 = and(_T_4256, way_status_clken_9) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[73] <= _T_4254 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4255 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4256 = and(_T_4255, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4257 = and(_T_4256, way_status_clken_9) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4258 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4257 : @[Reg.scala 28:19] _T_4258 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[74] <= _T_4258 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4259 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4260 = and(_T_4259, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4261 = and(_T_4260, way_status_clken_9) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[74] <= _T_4258 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4259 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4260 = and(_T_4259, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4261 = and(_T_4260, way_status_clken_9) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4262 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4261 : @[Reg.scala 28:19] _T_4262 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[75] <= _T_4262 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4263 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4264 = and(_T_4263, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4265 = and(_T_4264, way_status_clken_9) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[75] <= _T_4262 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4263 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4264 = and(_T_4263, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4265 = and(_T_4264, way_status_clken_9) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4266 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4265 : @[Reg.scala 28:19] _T_4266 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[76] <= _T_4266 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4267 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4268 = and(_T_4267, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4269 = and(_T_4268, way_status_clken_9) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[76] <= _T_4266 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4267 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4268 = and(_T_4267, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4269 = and(_T_4268, way_status_clken_9) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4270 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4269 : @[Reg.scala 28:19] _T_4270 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[77] <= _T_4270 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4271 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4272 = and(_T_4271, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4273 = and(_T_4272, way_status_clken_9) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[77] <= _T_4270 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4271 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4272 = and(_T_4271, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4273 = and(_T_4272, way_status_clken_9) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4274 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4273 : @[Reg.scala 28:19] _T_4274 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[78] <= _T_4274 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4275 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4276 = and(_T_4275, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4277 = and(_T_4276, way_status_clken_9) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[78] <= _T_4274 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4275 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4276 = and(_T_4275, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4277 = and(_T_4276, way_status_clken_9) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4278 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4277 : @[Reg.scala 28:19] _T_4278 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[79] <= _T_4278 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4279 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4280 = and(_T_4279, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4281 = and(_T_4280, way_status_clken_10) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[79] <= _T_4278 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4279 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4280 = and(_T_4279, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4281 = and(_T_4280, way_status_clken_10) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4282 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4281 : @[Reg.scala 28:19] _T_4282 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[80] <= _T_4282 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4283 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4284 = and(_T_4283, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4285 = and(_T_4284, way_status_clken_10) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[80] <= _T_4282 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4283 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4284 = and(_T_4283, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4285 = and(_T_4284, way_status_clken_10) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4286 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4285 : @[Reg.scala 28:19] _T_4286 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[81] <= _T_4286 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4287 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4288 = and(_T_4287, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4289 = and(_T_4288, way_status_clken_10) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[81] <= _T_4286 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4287 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4288 = and(_T_4287, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4289 = and(_T_4288, way_status_clken_10) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4290 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4289 : @[Reg.scala 28:19] _T_4290 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[82] <= _T_4290 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4291 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4292 = and(_T_4291, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4293 = and(_T_4292, way_status_clken_10) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[82] <= _T_4290 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4291 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4292 = and(_T_4291, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4293 = and(_T_4292, way_status_clken_10) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4294 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4293 : @[Reg.scala 28:19] _T_4294 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[83] <= _T_4294 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4295 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4296 = and(_T_4295, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4297 = and(_T_4296, way_status_clken_10) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[83] <= _T_4294 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4295 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4296 = and(_T_4295, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4297 = and(_T_4296, way_status_clken_10) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4298 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4297 : @[Reg.scala 28:19] _T_4298 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[84] <= _T_4298 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4299 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4300 = and(_T_4299, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4301 = and(_T_4300, way_status_clken_10) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[84] <= _T_4298 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4299 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4300 = and(_T_4299, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4301 = and(_T_4300, way_status_clken_10) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4302 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4301 : @[Reg.scala 28:19] _T_4302 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[85] <= _T_4302 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4303 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4304 = and(_T_4303, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4305 = and(_T_4304, way_status_clken_10) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[85] <= _T_4302 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4303 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4304 = and(_T_4303, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4305 = and(_T_4304, way_status_clken_10) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4306 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4305 : @[Reg.scala 28:19] _T_4306 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[86] <= _T_4306 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4307 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4308 = and(_T_4307, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4309 = and(_T_4308, way_status_clken_10) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[86] <= _T_4306 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4307 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4308 = and(_T_4307, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4309 = and(_T_4308, way_status_clken_10) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4310 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4309 : @[Reg.scala 28:19] _T_4310 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[87] <= _T_4310 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4311 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4312 = and(_T_4311, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4313 = and(_T_4312, way_status_clken_11) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[87] <= _T_4310 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4311 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4312 = and(_T_4311, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4313 = and(_T_4312, way_status_clken_11) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4314 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4313 : @[Reg.scala 28:19] _T_4314 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[88] <= _T_4314 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4315 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4316 = and(_T_4315, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4317 = and(_T_4316, way_status_clken_11) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[88] <= _T_4314 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4315 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4316 = and(_T_4315, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4317 = and(_T_4316, way_status_clken_11) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4318 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4317 : @[Reg.scala 28:19] _T_4318 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[89] <= _T_4318 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4319 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4320 = and(_T_4319, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4321 = and(_T_4320, way_status_clken_11) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[89] <= _T_4318 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4319 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4320 = and(_T_4319, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4321 = and(_T_4320, way_status_clken_11) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4322 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4321 : @[Reg.scala 28:19] _T_4322 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[90] <= _T_4322 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4323 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4324 = and(_T_4323, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4325 = and(_T_4324, way_status_clken_11) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[90] <= _T_4322 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4323 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4324 = and(_T_4323, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4325 = and(_T_4324, way_status_clken_11) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4326 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4325 : @[Reg.scala 28:19] _T_4326 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[91] <= _T_4326 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4327 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4328 = and(_T_4327, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4329 = and(_T_4328, way_status_clken_11) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[91] <= _T_4326 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4327 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4328 = and(_T_4327, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4329 = and(_T_4328, way_status_clken_11) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4330 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4329 : @[Reg.scala 28:19] _T_4330 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[92] <= _T_4330 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4331 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4332 = and(_T_4331, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4333 = and(_T_4332, way_status_clken_11) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[92] <= _T_4330 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4331 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4332 = and(_T_4331, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4333 = and(_T_4332, way_status_clken_11) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4334 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4333 : @[Reg.scala 28:19] _T_4334 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[93] <= _T_4334 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4335 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4336 = and(_T_4335, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4337 = and(_T_4336, way_status_clken_11) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[93] <= _T_4334 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4335 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4336 = and(_T_4335, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4337 = and(_T_4336, way_status_clken_11) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4338 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4337 : @[Reg.scala 28:19] _T_4338 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[94] <= _T_4338 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4339 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4340 = and(_T_4339, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4341 = and(_T_4340, way_status_clken_11) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[94] <= _T_4338 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4339 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4340 = and(_T_4339, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4341 = and(_T_4340, way_status_clken_11) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4342 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4341 : @[Reg.scala 28:19] _T_4342 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[95] <= _T_4342 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4343 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4344 = and(_T_4343, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4345 = and(_T_4344, way_status_clken_12) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[95] <= _T_4342 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4343 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4344 = and(_T_4343, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4345 = and(_T_4344, way_status_clken_12) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4346 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4345 : @[Reg.scala 28:19] _T_4346 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[96] <= _T_4346 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4347 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4348 = and(_T_4347, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4349 = and(_T_4348, way_status_clken_12) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[96] <= _T_4346 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4347 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4348 = and(_T_4347, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4349 = and(_T_4348, way_status_clken_12) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4350 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4349 : @[Reg.scala 28:19] _T_4350 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[97] <= _T_4350 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4351 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4352 = and(_T_4351, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4353 = and(_T_4352, way_status_clken_12) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[97] <= _T_4350 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4351 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4352 = and(_T_4351, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4353 = and(_T_4352, way_status_clken_12) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4354 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4353 : @[Reg.scala 28:19] _T_4354 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[98] <= _T_4354 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4355 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4356 = and(_T_4355, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4357 = and(_T_4356, way_status_clken_12) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[98] <= _T_4354 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4355 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4356 = and(_T_4355, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4357 = and(_T_4356, way_status_clken_12) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4358 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4357 : @[Reg.scala 28:19] _T_4358 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[99] <= _T_4358 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4359 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4360 = and(_T_4359, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4361 = and(_T_4360, way_status_clken_12) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[99] <= _T_4358 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4359 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4360 = and(_T_4359, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4361 = and(_T_4360, way_status_clken_12) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4362 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4361 : @[Reg.scala 28:19] _T_4362 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[100] <= _T_4362 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4363 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4364 = and(_T_4363, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4365 = and(_T_4364, way_status_clken_12) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[100] <= _T_4362 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4363 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4364 = and(_T_4363, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4365 = and(_T_4364, way_status_clken_12) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4366 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4365 : @[Reg.scala 28:19] _T_4366 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[101] <= _T_4366 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4367 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4368 = and(_T_4367, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4369 = and(_T_4368, way_status_clken_12) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[101] <= _T_4366 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4367 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4368 = and(_T_4367, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4369 = and(_T_4368, way_status_clken_12) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4370 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4369 : @[Reg.scala 28:19] _T_4370 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[102] <= _T_4370 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4371 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4372 = and(_T_4371, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4373 = and(_T_4372, way_status_clken_12) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[102] <= _T_4370 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4371 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4372 = and(_T_4371, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4373 = and(_T_4372, way_status_clken_12) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4374 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4373 : @[Reg.scala 28:19] _T_4374 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[103] <= _T_4374 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4375 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4376 = and(_T_4375, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4377 = and(_T_4376, way_status_clken_13) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[103] <= _T_4374 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4375 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4376 = and(_T_4375, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4377 = and(_T_4376, way_status_clken_13) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4378 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4377 : @[Reg.scala 28:19] _T_4378 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[104] <= _T_4378 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4379 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4380 = and(_T_4379, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4381 = and(_T_4380, way_status_clken_13) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[104] <= _T_4378 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4379 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4380 = and(_T_4379, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4381 = and(_T_4380, way_status_clken_13) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4382 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4381 : @[Reg.scala 28:19] _T_4382 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[105] <= _T_4382 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4383 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4384 = and(_T_4383, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4385 = and(_T_4384, way_status_clken_13) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[105] <= _T_4382 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4383 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4384 = and(_T_4383, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4385 = and(_T_4384, way_status_clken_13) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4386 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4385 : @[Reg.scala 28:19] _T_4386 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[106] <= _T_4386 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4387 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4388 = and(_T_4387, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4389 = and(_T_4388, way_status_clken_13) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[106] <= _T_4386 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4387 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4388 = and(_T_4387, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4389 = and(_T_4388, way_status_clken_13) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4390 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4389 : @[Reg.scala 28:19] _T_4390 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[107] <= _T_4390 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4391 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4392 = and(_T_4391, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4393 = and(_T_4392, way_status_clken_13) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[107] <= _T_4390 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4391 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4392 = and(_T_4391, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4393 = and(_T_4392, way_status_clken_13) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4394 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4393 : @[Reg.scala 28:19] _T_4394 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[108] <= _T_4394 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4395 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4396 = and(_T_4395, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4397 = and(_T_4396, way_status_clken_13) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[108] <= _T_4394 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4395 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4396 = and(_T_4395, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4397 = and(_T_4396, way_status_clken_13) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4398 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4397 : @[Reg.scala 28:19] _T_4398 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[109] <= _T_4398 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4399 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4400 = and(_T_4399, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4401 = and(_T_4400, way_status_clken_13) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[109] <= _T_4398 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4399 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4400 = and(_T_4399, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4401 = and(_T_4400, way_status_clken_13) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4402 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4401 : @[Reg.scala 28:19] _T_4402 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[110] <= _T_4402 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4403 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4404 = and(_T_4403, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4405 = and(_T_4404, way_status_clken_13) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[110] <= _T_4402 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4403 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4404 = and(_T_4403, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4405 = and(_T_4404, way_status_clken_13) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4406 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4405 : @[Reg.scala 28:19] _T_4406 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[111] <= _T_4406 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4407 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4408 = and(_T_4407, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4409 = and(_T_4408, way_status_clken_14) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[111] <= _T_4406 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4407 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4408 = and(_T_4407, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4409 = and(_T_4408, way_status_clken_14) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4410 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4409 : @[Reg.scala 28:19] _T_4410 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[112] <= _T_4410 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4411 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4412 = and(_T_4411, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4413 = and(_T_4412, way_status_clken_14) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[112] <= _T_4410 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4411 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4412 = and(_T_4411, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4413 = and(_T_4412, way_status_clken_14) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4414 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4413 : @[Reg.scala 28:19] _T_4414 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[113] <= _T_4414 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4415 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4416 = and(_T_4415, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4417 = and(_T_4416, way_status_clken_14) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[113] <= _T_4414 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4415 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4416 = and(_T_4415, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4417 = and(_T_4416, way_status_clken_14) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4418 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4417 : @[Reg.scala 28:19] _T_4418 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[114] <= _T_4418 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4419 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4420 = and(_T_4419, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4421 = and(_T_4420, way_status_clken_14) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[114] <= _T_4418 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4419 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4420 = and(_T_4419, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4421 = and(_T_4420, way_status_clken_14) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4422 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4421 : @[Reg.scala 28:19] _T_4422 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[115] <= _T_4422 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4423 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4424 = and(_T_4423, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4425 = and(_T_4424, way_status_clken_14) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[115] <= _T_4422 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4423 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4424 = and(_T_4423, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4425 = and(_T_4424, way_status_clken_14) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4426 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4425 : @[Reg.scala 28:19] _T_4426 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[116] <= _T_4426 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4427 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4428 = and(_T_4427, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4429 = and(_T_4428, way_status_clken_14) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[116] <= _T_4426 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4427 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4428 = and(_T_4427, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4429 = and(_T_4428, way_status_clken_14) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4430 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4429 : @[Reg.scala 28:19] _T_4430 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[117] <= _T_4430 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4431 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4432 = and(_T_4431, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4433 = and(_T_4432, way_status_clken_14) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[117] <= _T_4430 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4431 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4432 = and(_T_4431, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4433 = and(_T_4432, way_status_clken_14) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4434 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4433 : @[Reg.scala 28:19] _T_4434 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[118] <= _T_4434 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4435 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4436 = and(_T_4435, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4437 = and(_T_4436, way_status_clken_14) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[118] <= _T_4434 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4435 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4436 = and(_T_4435, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4437 = and(_T_4436, way_status_clken_14) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4438 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4437 : @[Reg.scala 28:19] _T_4438 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[119] <= _T_4438 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4439 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4440 = and(_T_4439, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4441 = and(_T_4440, way_status_clken_15) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[119] <= _T_4438 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4439 = eq(ifu_status_wr_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4440 = and(_T_4439, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4441 = and(_T_4440, way_status_clken_15) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4442 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4441 : @[Reg.scala 28:19] _T_4442 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[120] <= _T_4442 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4443 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4444 = and(_T_4443, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4445 = and(_T_4444, way_status_clken_15) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[120] <= _T_4442 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4443 = eq(ifu_status_wr_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4444 = and(_T_4443, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4445 = and(_T_4444, way_status_clken_15) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4446 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4445 : @[Reg.scala 28:19] _T_4446 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[121] <= _T_4446 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4447 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4448 = and(_T_4447, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4449 = and(_T_4448, way_status_clken_15) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[121] <= _T_4446 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4447 = eq(ifu_status_wr_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4448 = and(_T_4447, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4449 = and(_T_4448, way_status_clken_15) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4450 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4449 : @[Reg.scala 28:19] _T_4450 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[122] <= _T_4450 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4451 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4452 = and(_T_4451, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4453 = and(_T_4452, way_status_clken_15) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[122] <= _T_4450 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4451 = eq(ifu_status_wr_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4452 = and(_T_4451, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4453 = and(_T_4452, way_status_clken_15) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4454 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4453 : @[Reg.scala 28:19] _T_4454 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[123] <= _T_4454 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4455 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4456 = and(_T_4455, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4457 = and(_T_4456, way_status_clken_15) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[123] <= _T_4454 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4455 = eq(ifu_status_wr_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4456 = and(_T_4455, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4457 = and(_T_4456, way_status_clken_15) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4458 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4457 : @[Reg.scala 28:19] _T_4458 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[124] <= _T_4458 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4459 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4460 = and(_T_4459, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4461 = and(_T_4460, way_status_clken_15) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[124] <= _T_4458 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4459 = eq(ifu_status_wr_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4460 = and(_T_4459, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4461 = and(_T_4460, way_status_clken_15) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4462 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4461 : @[Reg.scala 28:19] _T_4462 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[125] <= _T_4462 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4463 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4464 = and(_T_4463, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4465 = and(_T_4464, way_status_clken_15) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[125] <= _T_4462 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4463 = eq(ifu_status_wr_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4464 = and(_T_4463, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4465 = and(_T_4464, way_status_clken_15) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4466 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4465 : @[Reg.scala 28:19] _T_4466 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[126] <= _T_4466 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4467 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 715:93] - node _T_4468 = and(_T_4467, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 715:102] - node _T_4469 = and(_T_4468, way_status_clken_15) @[el2_ifu_mem_ctl.scala 715:124] + way_status_out[126] <= _T_4466 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4467 = eq(ifu_status_wr_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 716:93] + node _T_4468 = and(_T_4467, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 716:102] + node _T_4469 = and(_T_4468, way_status_clken_15) @[el2_ifu_mem_ctl.scala 716:124] reg _T_4470 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4469 : @[Reg.scala 28:19] _T_4470 <= way_status_new_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - way_status_out[127] <= _T_4470 @[el2_ifu_mem_ctl.scala 715:33] - node _T_4471 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 716:121] + way_status_out[127] <= _T_4470 @[el2_ifu_mem_ctl.scala 716:33] + node _T_4471 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4472 = bits(_T_4471, 0, 0) @[Bitwise.scala 72:15] node _T_4473 = mux(_T_4472, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4474 = and(_T_4473, way_status_out[0]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4475 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4474 = and(_T_4473, way_status_out[0]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4475 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4476 = bits(_T_4475, 0, 0) @[Bitwise.scala 72:15] node _T_4477 = mux(_T_4476, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4478 = and(_T_4477, way_status_out[1]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4479 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4478 = and(_T_4477, way_status_out[1]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4479 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4480 = bits(_T_4479, 0, 0) @[Bitwise.scala 72:15] node _T_4481 = mux(_T_4480, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4482 = and(_T_4481, way_status_out[2]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4483 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4482 = and(_T_4481, way_status_out[2]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4483 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4484 = bits(_T_4483, 0, 0) @[Bitwise.scala 72:15] node _T_4485 = mux(_T_4484, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4486 = and(_T_4485, way_status_out[3]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4487 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4486 = and(_T_4485, way_status_out[3]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4487 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4488 = bits(_T_4487, 0, 0) @[Bitwise.scala 72:15] node _T_4489 = mux(_T_4488, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4490 = and(_T_4489, way_status_out[4]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4491 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4490 = and(_T_4489, way_status_out[4]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4491 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4492 = bits(_T_4491, 0, 0) @[Bitwise.scala 72:15] node _T_4493 = mux(_T_4492, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4494 = and(_T_4493, way_status_out[5]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4495 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4494 = and(_T_4493, way_status_out[5]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4495 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4496 = bits(_T_4495, 0, 0) @[Bitwise.scala 72:15] node _T_4497 = mux(_T_4496, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4498 = and(_T_4497, way_status_out[6]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4499 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4498 = and(_T_4497, way_status_out[6]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4499 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4500 = bits(_T_4499, 0, 0) @[Bitwise.scala 72:15] node _T_4501 = mux(_T_4500, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4502 = and(_T_4501, way_status_out[7]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4503 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4502 = and(_T_4501, way_status_out[7]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4503 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4504 = bits(_T_4503, 0, 0) @[Bitwise.scala 72:15] node _T_4505 = mux(_T_4504, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4506 = and(_T_4505, way_status_out[8]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4507 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4506 = and(_T_4505, way_status_out[8]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4507 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4508 = bits(_T_4507, 0, 0) @[Bitwise.scala 72:15] node _T_4509 = mux(_T_4508, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4510 = and(_T_4509, way_status_out[9]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4511 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4510 = and(_T_4509, way_status_out[9]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4511 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4512 = bits(_T_4511, 0, 0) @[Bitwise.scala 72:15] node _T_4513 = mux(_T_4512, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4514 = and(_T_4513, way_status_out[10]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4515 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4514 = and(_T_4513, way_status_out[10]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4515 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4516 = bits(_T_4515, 0, 0) @[Bitwise.scala 72:15] node _T_4517 = mux(_T_4516, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4518 = and(_T_4517, way_status_out[11]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4519 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4518 = and(_T_4517, way_status_out[11]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4519 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4520 = bits(_T_4519, 0, 0) @[Bitwise.scala 72:15] node _T_4521 = mux(_T_4520, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4522 = and(_T_4521, way_status_out[12]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4523 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4522 = and(_T_4521, way_status_out[12]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4523 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4524 = bits(_T_4523, 0, 0) @[Bitwise.scala 72:15] node _T_4525 = mux(_T_4524, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4526 = and(_T_4525, way_status_out[13]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4527 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4526 = and(_T_4525, way_status_out[13]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4527 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4528 = bits(_T_4527, 0, 0) @[Bitwise.scala 72:15] node _T_4529 = mux(_T_4528, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4530 = and(_T_4529, way_status_out[14]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4531 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4530 = and(_T_4529, way_status_out[14]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4531 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4532 = bits(_T_4531, 0, 0) @[Bitwise.scala 72:15] node _T_4533 = mux(_T_4532, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4534 = and(_T_4533, way_status_out[15]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4535 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h010")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4534 = and(_T_4533, way_status_out[15]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4535 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h010")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4536 = bits(_T_4535, 0, 0) @[Bitwise.scala 72:15] node _T_4537 = mux(_T_4536, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4538 = and(_T_4537, way_status_out[16]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4539 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h011")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4538 = and(_T_4537, way_status_out[16]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4539 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h011")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4540 = bits(_T_4539, 0, 0) @[Bitwise.scala 72:15] node _T_4541 = mux(_T_4540, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4542 = and(_T_4541, way_status_out[17]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4543 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h012")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4542 = and(_T_4541, way_status_out[17]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4543 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h012")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4544 = bits(_T_4543, 0, 0) @[Bitwise.scala 72:15] node _T_4545 = mux(_T_4544, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4546 = and(_T_4545, way_status_out[18]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4547 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h013")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4546 = and(_T_4545, way_status_out[18]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4547 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h013")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4548 = bits(_T_4547, 0, 0) @[Bitwise.scala 72:15] node _T_4549 = mux(_T_4548, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4550 = and(_T_4549, way_status_out[19]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4551 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h014")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4550 = and(_T_4549, way_status_out[19]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4551 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h014")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4552 = bits(_T_4551, 0, 0) @[Bitwise.scala 72:15] node _T_4553 = mux(_T_4552, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4554 = and(_T_4553, way_status_out[20]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4555 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h015")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4554 = and(_T_4553, way_status_out[20]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4555 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h015")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4556 = bits(_T_4555, 0, 0) @[Bitwise.scala 72:15] node _T_4557 = mux(_T_4556, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4558 = and(_T_4557, way_status_out[21]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4559 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h016")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4558 = and(_T_4557, way_status_out[21]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4559 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h016")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4560 = bits(_T_4559, 0, 0) @[Bitwise.scala 72:15] node _T_4561 = mux(_T_4560, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4562 = and(_T_4561, way_status_out[22]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4563 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h017")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4562 = and(_T_4561, way_status_out[22]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4563 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h017")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4564 = bits(_T_4563, 0, 0) @[Bitwise.scala 72:15] node _T_4565 = mux(_T_4564, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4566 = and(_T_4565, way_status_out[23]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4567 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h018")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4566 = and(_T_4565, way_status_out[23]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4567 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h018")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4568 = bits(_T_4567, 0, 0) @[Bitwise.scala 72:15] node _T_4569 = mux(_T_4568, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4570 = and(_T_4569, way_status_out[24]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4571 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h019")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4570 = and(_T_4569, way_status_out[24]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4571 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h019")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4572 = bits(_T_4571, 0, 0) @[Bitwise.scala 72:15] node _T_4573 = mux(_T_4572, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4574 = and(_T_4573, way_status_out[25]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4575 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01a")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4574 = and(_T_4573, way_status_out[25]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4575 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01a")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4576 = bits(_T_4575, 0, 0) @[Bitwise.scala 72:15] node _T_4577 = mux(_T_4576, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4578 = and(_T_4577, way_status_out[26]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4579 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01b")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4578 = and(_T_4577, way_status_out[26]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4579 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01b")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4580 = bits(_T_4579, 0, 0) @[Bitwise.scala 72:15] node _T_4581 = mux(_T_4580, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4582 = and(_T_4581, way_status_out[27]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4583 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01c")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4582 = and(_T_4581, way_status_out[27]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4583 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01c")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4584 = bits(_T_4583, 0, 0) @[Bitwise.scala 72:15] node _T_4585 = mux(_T_4584, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4586 = and(_T_4585, way_status_out[28]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4587 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01d")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4586 = and(_T_4585, way_status_out[28]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4587 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01d")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4588 = bits(_T_4587, 0, 0) @[Bitwise.scala 72:15] node _T_4589 = mux(_T_4588, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4590 = and(_T_4589, way_status_out[29]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4591 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01e")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4590 = and(_T_4589, way_status_out[29]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4591 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01e")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4592 = bits(_T_4591, 0, 0) @[Bitwise.scala 72:15] node _T_4593 = mux(_T_4592, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4594 = and(_T_4593, way_status_out[30]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4595 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01f")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4594 = and(_T_4593, way_status_out[30]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4595 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01f")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4596 = bits(_T_4595, 0, 0) @[Bitwise.scala 72:15] node _T_4597 = mux(_T_4596, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4598 = and(_T_4597, way_status_out[31]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4599 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h020")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4598 = and(_T_4597, way_status_out[31]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4599 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h020")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4600 = bits(_T_4599, 0, 0) @[Bitwise.scala 72:15] node _T_4601 = mux(_T_4600, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4602 = and(_T_4601, way_status_out[32]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4603 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h021")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4602 = and(_T_4601, way_status_out[32]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4603 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h021")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4604 = bits(_T_4603, 0, 0) @[Bitwise.scala 72:15] node _T_4605 = mux(_T_4604, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4606 = and(_T_4605, way_status_out[33]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4607 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h022")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4606 = and(_T_4605, way_status_out[33]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4607 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h022")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4608 = bits(_T_4607, 0, 0) @[Bitwise.scala 72:15] node _T_4609 = mux(_T_4608, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4610 = and(_T_4609, way_status_out[34]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4611 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h023")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4610 = and(_T_4609, way_status_out[34]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4611 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h023")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4612 = bits(_T_4611, 0, 0) @[Bitwise.scala 72:15] node _T_4613 = mux(_T_4612, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4614 = and(_T_4613, way_status_out[35]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4615 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h024")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4614 = and(_T_4613, way_status_out[35]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4615 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h024")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4616 = bits(_T_4615, 0, 0) @[Bitwise.scala 72:15] node _T_4617 = mux(_T_4616, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4618 = and(_T_4617, way_status_out[36]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4619 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h025")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4618 = and(_T_4617, way_status_out[36]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4619 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h025")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4620 = bits(_T_4619, 0, 0) @[Bitwise.scala 72:15] node _T_4621 = mux(_T_4620, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4622 = and(_T_4621, way_status_out[37]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4623 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h026")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4622 = and(_T_4621, way_status_out[37]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4623 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h026")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4624 = bits(_T_4623, 0, 0) @[Bitwise.scala 72:15] node _T_4625 = mux(_T_4624, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4626 = and(_T_4625, way_status_out[38]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4627 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h027")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4626 = and(_T_4625, way_status_out[38]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4627 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h027")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4628 = bits(_T_4627, 0, 0) @[Bitwise.scala 72:15] node _T_4629 = mux(_T_4628, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4630 = and(_T_4629, way_status_out[39]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4631 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h028")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4630 = and(_T_4629, way_status_out[39]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4631 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h028")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4632 = bits(_T_4631, 0, 0) @[Bitwise.scala 72:15] node _T_4633 = mux(_T_4632, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4634 = and(_T_4633, way_status_out[40]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4635 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h029")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4634 = and(_T_4633, way_status_out[40]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4635 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h029")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4636 = bits(_T_4635, 0, 0) @[Bitwise.scala 72:15] node _T_4637 = mux(_T_4636, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4638 = and(_T_4637, way_status_out[41]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4639 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02a")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4638 = and(_T_4637, way_status_out[41]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4639 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02a")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4640 = bits(_T_4639, 0, 0) @[Bitwise.scala 72:15] node _T_4641 = mux(_T_4640, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4642 = and(_T_4641, way_status_out[42]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4643 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02b")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4642 = and(_T_4641, way_status_out[42]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4643 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02b")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4644 = bits(_T_4643, 0, 0) @[Bitwise.scala 72:15] node _T_4645 = mux(_T_4644, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4646 = and(_T_4645, way_status_out[43]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4647 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02c")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4646 = and(_T_4645, way_status_out[43]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4647 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02c")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4648 = bits(_T_4647, 0, 0) @[Bitwise.scala 72:15] node _T_4649 = mux(_T_4648, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4650 = and(_T_4649, way_status_out[44]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4651 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02d")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4650 = and(_T_4649, way_status_out[44]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4651 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02d")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4652 = bits(_T_4651, 0, 0) @[Bitwise.scala 72:15] node _T_4653 = mux(_T_4652, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4654 = and(_T_4653, way_status_out[45]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4655 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02e")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4654 = and(_T_4653, way_status_out[45]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4655 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02e")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4656 = bits(_T_4655, 0, 0) @[Bitwise.scala 72:15] node _T_4657 = mux(_T_4656, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4658 = and(_T_4657, way_status_out[46]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4659 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02f")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4658 = and(_T_4657, way_status_out[46]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4659 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02f")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4660 = bits(_T_4659, 0, 0) @[Bitwise.scala 72:15] node _T_4661 = mux(_T_4660, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4662 = and(_T_4661, way_status_out[47]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4663 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h030")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4662 = and(_T_4661, way_status_out[47]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4663 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h030")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4664 = bits(_T_4663, 0, 0) @[Bitwise.scala 72:15] node _T_4665 = mux(_T_4664, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4666 = and(_T_4665, way_status_out[48]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4667 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h031")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4666 = and(_T_4665, way_status_out[48]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4667 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h031")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4668 = bits(_T_4667, 0, 0) @[Bitwise.scala 72:15] node _T_4669 = mux(_T_4668, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4670 = and(_T_4669, way_status_out[49]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4671 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h032")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4670 = and(_T_4669, way_status_out[49]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4671 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h032")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4672 = bits(_T_4671, 0, 0) @[Bitwise.scala 72:15] node _T_4673 = mux(_T_4672, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4674 = and(_T_4673, way_status_out[50]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4675 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h033")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4674 = and(_T_4673, way_status_out[50]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4675 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h033")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4676 = bits(_T_4675, 0, 0) @[Bitwise.scala 72:15] node _T_4677 = mux(_T_4676, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4678 = and(_T_4677, way_status_out[51]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4679 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h034")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4678 = and(_T_4677, way_status_out[51]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4679 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h034")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4680 = bits(_T_4679, 0, 0) @[Bitwise.scala 72:15] node _T_4681 = mux(_T_4680, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4682 = and(_T_4681, way_status_out[52]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4683 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h035")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4682 = and(_T_4681, way_status_out[52]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4683 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h035")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4684 = bits(_T_4683, 0, 0) @[Bitwise.scala 72:15] node _T_4685 = mux(_T_4684, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4686 = and(_T_4685, way_status_out[53]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4687 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h036")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4686 = and(_T_4685, way_status_out[53]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4687 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h036")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4688 = bits(_T_4687, 0, 0) @[Bitwise.scala 72:15] node _T_4689 = mux(_T_4688, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4690 = and(_T_4689, way_status_out[54]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4691 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h037")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4690 = and(_T_4689, way_status_out[54]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4691 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h037")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4692 = bits(_T_4691, 0, 0) @[Bitwise.scala 72:15] node _T_4693 = mux(_T_4692, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4694 = and(_T_4693, way_status_out[55]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4695 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h038")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4694 = and(_T_4693, way_status_out[55]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4695 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h038")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4696 = bits(_T_4695, 0, 0) @[Bitwise.scala 72:15] node _T_4697 = mux(_T_4696, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4698 = and(_T_4697, way_status_out[56]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4699 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h039")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4698 = and(_T_4697, way_status_out[56]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4699 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h039")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4700 = bits(_T_4699, 0, 0) @[Bitwise.scala 72:15] node _T_4701 = mux(_T_4700, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4702 = and(_T_4701, way_status_out[57]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4703 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03a")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4702 = and(_T_4701, way_status_out[57]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4703 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03a")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4704 = bits(_T_4703, 0, 0) @[Bitwise.scala 72:15] node _T_4705 = mux(_T_4704, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4706 = and(_T_4705, way_status_out[58]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4707 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03b")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4706 = and(_T_4705, way_status_out[58]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4707 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03b")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4708 = bits(_T_4707, 0, 0) @[Bitwise.scala 72:15] node _T_4709 = mux(_T_4708, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4710 = and(_T_4709, way_status_out[59]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4711 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03c")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4710 = and(_T_4709, way_status_out[59]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4711 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03c")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4712 = bits(_T_4711, 0, 0) @[Bitwise.scala 72:15] node _T_4713 = mux(_T_4712, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4714 = and(_T_4713, way_status_out[60]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4715 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03d")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4714 = and(_T_4713, way_status_out[60]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4715 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03d")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4716 = bits(_T_4715, 0, 0) @[Bitwise.scala 72:15] node _T_4717 = mux(_T_4716, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4718 = and(_T_4717, way_status_out[61]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4719 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03e")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4718 = and(_T_4717, way_status_out[61]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4719 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03e")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4720 = bits(_T_4719, 0, 0) @[Bitwise.scala 72:15] node _T_4721 = mux(_T_4720, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4722 = and(_T_4721, way_status_out[62]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4723 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03f")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4722 = and(_T_4721, way_status_out[62]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4723 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03f")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4724 = bits(_T_4723, 0, 0) @[Bitwise.scala 72:15] node _T_4725 = mux(_T_4724, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4726 = and(_T_4725, way_status_out[63]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4727 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h040")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4726 = and(_T_4725, way_status_out[63]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4727 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h040")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4728 = bits(_T_4727, 0, 0) @[Bitwise.scala 72:15] node _T_4729 = mux(_T_4728, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4730 = and(_T_4729, way_status_out[64]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4731 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h041")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4730 = and(_T_4729, way_status_out[64]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4731 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h041")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4732 = bits(_T_4731, 0, 0) @[Bitwise.scala 72:15] node _T_4733 = mux(_T_4732, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4734 = and(_T_4733, way_status_out[65]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4735 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h042")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4734 = and(_T_4733, way_status_out[65]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4735 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h042")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4736 = bits(_T_4735, 0, 0) @[Bitwise.scala 72:15] node _T_4737 = mux(_T_4736, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4738 = and(_T_4737, way_status_out[66]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4739 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h043")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4738 = and(_T_4737, way_status_out[66]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4739 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h043")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4740 = bits(_T_4739, 0, 0) @[Bitwise.scala 72:15] node _T_4741 = mux(_T_4740, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4742 = and(_T_4741, way_status_out[67]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4743 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h044")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4742 = and(_T_4741, way_status_out[67]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4743 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h044")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4744 = bits(_T_4743, 0, 0) @[Bitwise.scala 72:15] node _T_4745 = mux(_T_4744, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4746 = and(_T_4745, way_status_out[68]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4747 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h045")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4746 = and(_T_4745, way_status_out[68]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4747 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h045")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4748 = bits(_T_4747, 0, 0) @[Bitwise.scala 72:15] node _T_4749 = mux(_T_4748, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4750 = and(_T_4749, way_status_out[69]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4751 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h046")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4750 = and(_T_4749, way_status_out[69]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4751 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h046")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4752 = bits(_T_4751, 0, 0) @[Bitwise.scala 72:15] node _T_4753 = mux(_T_4752, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4754 = and(_T_4753, way_status_out[70]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4755 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h047")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4754 = and(_T_4753, way_status_out[70]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4755 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h047")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4756 = bits(_T_4755, 0, 0) @[Bitwise.scala 72:15] node _T_4757 = mux(_T_4756, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4758 = and(_T_4757, way_status_out[71]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4759 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h048")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4758 = and(_T_4757, way_status_out[71]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4759 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h048")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4760 = bits(_T_4759, 0, 0) @[Bitwise.scala 72:15] node _T_4761 = mux(_T_4760, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4762 = and(_T_4761, way_status_out[72]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4763 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h049")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4762 = and(_T_4761, way_status_out[72]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4763 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h049")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4764 = bits(_T_4763, 0, 0) @[Bitwise.scala 72:15] node _T_4765 = mux(_T_4764, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4766 = and(_T_4765, way_status_out[73]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4767 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04a")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4766 = and(_T_4765, way_status_out[73]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4767 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04a")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4768 = bits(_T_4767, 0, 0) @[Bitwise.scala 72:15] node _T_4769 = mux(_T_4768, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4770 = and(_T_4769, way_status_out[74]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4771 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04b")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4770 = and(_T_4769, way_status_out[74]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4771 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04b")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4772 = bits(_T_4771, 0, 0) @[Bitwise.scala 72:15] node _T_4773 = mux(_T_4772, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4774 = and(_T_4773, way_status_out[75]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4775 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04c")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4774 = and(_T_4773, way_status_out[75]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4775 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04c")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4776 = bits(_T_4775, 0, 0) @[Bitwise.scala 72:15] node _T_4777 = mux(_T_4776, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4778 = and(_T_4777, way_status_out[76]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4779 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04d")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4778 = and(_T_4777, way_status_out[76]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4779 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04d")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4780 = bits(_T_4779, 0, 0) @[Bitwise.scala 72:15] node _T_4781 = mux(_T_4780, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4782 = and(_T_4781, way_status_out[77]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4783 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04e")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4782 = and(_T_4781, way_status_out[77]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4783 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04e")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4784 = bits(_T_4783, 0, 0) @[Bitwise.scala 72:15] node _T_4785 = mux(_T_4784, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4786 = and(_T_4785, way_status_out[78]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4787 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04f")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4786 = and(_T_4785, way_status_out[78]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4787 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04f")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4788 = bits(_T_4787, 0, 0) @[Bitwise.scala 72:15] node _T_4789 = mux(_T_4788, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4790 = and(_T_4789, way_status_out[79]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4791 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h050")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4790 = and(_T_4789, way_status_out[79]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4791 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h050")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4792 = bits(_T_4791, 0, 0) @[Bitwise.scala 72:15] node _T_4793 = mux(_T_4792, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4794 = and(_T_4793, way_status_out[80]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4795 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h051")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4794 = and(_T_4793, way_status_out[80]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4795 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h051")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4796 = bits(_T_4795, 0, 0) @[Bitwise.scala 72:15] node _T_4797 = mux(_T_4796, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4798 = and(_T_4797, way_status_out[81]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4799 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h052")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4798 = and(_T_4797, way_status_out[81]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4799 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h052")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4800 = bits(_T_4799, 0, 0) @[Bitwise.scala 72:15] node _T_4801 = mux(_T_4800, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4802 = and(_T_4801, way_status_out[82]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4803 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h053")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4802 = and(_T_4801, way_status_out[82]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4803 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h053")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4804 = bits(_T_4803, 0, 0) @[Bitwise.scala 72:15] node _T_4805 = mux(_T_4804, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4806 = and(_T_4805, way_status_out[83]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4807 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h054")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4806 = and(_T_4805, way_status_out[83]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4807 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h054")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4808 = bits(_T_4807, 0, 0) @[Bitwise.scala 72:15] node _T_4809 = mux(_T_4808, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4810 = and(_T_4809, way_status_out[84]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4811 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h055")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4810 = and(_T_4809, way_status_out[84]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4811 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h055")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4812 = bits(_T_4811, 0, 0) @[Bitwise.scala 72:15] node _T_4813 = mux(_T_4812, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4814 = and(_T_4813, way_status_out[85]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4815 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h056")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4814 = and(_T_4813, way_status_out[85]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4815 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h056")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4816 = bits(_T_4815, 0, 0) @[Bitwise.scala 72:15] node _T_4817 = mux(_T_4816, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4818 = and(_T_4817, way_status_out[86]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4819 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h057")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4818 = and(_T_4817, way_status_out[86]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4819 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h057")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4820 = bits(_T_4819, 0, 0) @[Bitwise.scala 72:15] node _T_4821 = mux(_T_4820, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4822 = and(_T_4821, way_status_out[87]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4823 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h058")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4822 = and(_T_4821, way_status_out[87]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4823 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h058")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4824 = bits(_T_4823, 0, 0) @[Bitwise.scala 72:15] node _T_4825 = mux(_T_4824, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4826 = and(_T_4825, way_status_out[88]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4827 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h059")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4826 = and(_T_4825, way_status_out[88]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4827 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h059")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4828 = bits(_T_4827, 0, 0) @[Bitwise.scala 72:15] node _T_4829 = mux(_T_4828, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4830 = and(_T_4829, way_status_out[89]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4831 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05a")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4830 = and(_T_4829, way_status_out[89]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4831 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05a")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4832 = bits(_T_4831, 0, 0) @[Bitwise.scala 72:15] node _T_4833 = mux(_T_4832, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4834 = and(_T_4833, way_status_out[90]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4835 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05b")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4834 = and(_T_4833, way_status_out[90]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4835 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05b")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4836 = bits(_T_4835, 0, 0) @[Bitwise.scala 72:15] node _T_4837 = mux(_T_4836, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4838 = and(_T_4837, way_status_out[91]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4839 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05c")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4838 = and(_T_4837, way_status_out[91]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4839 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05c")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4840 = bits(_T_4839, 0, 0) @[Bitwise.scala 72:15] node _T_4841 = mux(_T_4840, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4842 = and(_T_4841, way_status_out[92]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4843 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05d")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4842 = and(_T_4841, way_status_out[92]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4843 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05d")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4844 = bits(_T_4843, 0, 0) @[Bitwise.scala 72:15] node _T_4845 = mux(_T_4844, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4846 = and(_T_4845, way_status_out[93]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4847 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05e")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4846 = and(_T_4845, way_status_out[93]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4847 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05e")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4848 = bits(_T_4847, 0, 0) @[Bitwise.scala 72:15] node _T_4849 = mux(_T_4848, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4850 = and(_T_4849, way_status_out[94]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4851 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05f")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4850 = and(_T_4849, way_status_out[94]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4851 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05f")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4852 = bits(_T_4851, 0, 0) @[Bitwise.scala 72:15] node _T_4853 = mux(_T_4852, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4854 = and(_T_4853, way_status_out[95]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4855 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h060")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4854 = and(_T_4853, way_status_out[95]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4855 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h060")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4856 = bits(_T_4855, 0, 0) @[Bitwise.scala 72:15] node _T_4857 = mux(_T_4856, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4858 = and(_T_4857, way_status_out[96]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4859 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h061")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4858 = and(_T_4857, way_status_out[96]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4859 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h061")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4860 = bits(_T_4859, 0, 0) @[Bitwise.scala 72:15] node _T_4861 = mux(_T_4860, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4862 = and(_T_4861, way_status_out[97]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4863 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h062")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4862 = and(_T_4861, way_status_out[97]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4863 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h062")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4864 = bits(_T_4863, 0, 0) @[Bitwise.scala 72:15] node _T_4865 = mux(_T_4864, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4866 = and(_T_4865, way_status_out[98]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4867 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h063")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4866 = and(_T_4865, way_status_out[98]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4867 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h063")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4868 = bits(_T_4867, 0, 0) @[Bitwise.scala 72:15] node _T_4869 = mux(_T_4868, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4870 = and(_T_4869, way_status_out[99]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4871 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h064")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4870 = and(_T_4869, way_status_out[99]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4871 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h064")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4872 = bits(_T_4871, 0, 0) @[Bitwise.scala 72:15] node _T_4873 = mux(_T_4872, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4874 = and(_T_4873, way_status_out[100]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4875 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h065")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4874 = and(_T_4873, way_status_out[100]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4875 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h065")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4876 = bits(_T_4875, 0, 0) @[Bitwise.scala 72:15] node _T_4877 = mux(_T_4876, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4878 = and(_T_4877, way_status_out[101]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4879 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h066")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4878 = and(_T_4877, way_status_out[101]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4879 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h066")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4880 = bits(_T_4879, 0, 0) @[Bitwise.scala 72:15] node _T_4881 = mux(_T_4880, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4882 = and(_T_4881, way_status_out[102]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4883 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h067")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4882 = and(_T_4881, way_status_out[102]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4883 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h067")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4884 = bits(_T_4883, 0, 0) @[Bitwise.scala 72:15] node _T_4885 = mux(_T_4884, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4886 = and(_T_4885, way_status_out[103]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4887 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h068")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4886 = and(_T_4885, way_status_out[103]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4887 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h068")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4888 = bits(_T_4887, 0, 0) @[Bitwise.scala 72:15] node _T_4889 = mux(_T_4888, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4890 = and(_T_4889, way_status_out[104]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4891 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h069")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4890 = and(_T_4889, way_status_out[104]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4891 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h069")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4892 = bits(_T_4891, 0, 0) @[Bitwise.scala 72:15] node _T_4893 = mux(_T_4892, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4894 = and(_T_4893, way_status_out[105]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4895 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06a")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4894 = and(_T_4893, way_status_out[105]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4895 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06a")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4896 = bits(_T_4895, 0, 0) @[Bitwise.scala 72:15] node _T_4897 = mux(_T_4896, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4898 = and(_T_4897, way_status_out[106]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4899 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06b")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4898 = and(_T_4897, way_status_out[106]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4899 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06b")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4900 = bits(_T_4899, 0, 0) @[Bitwise.scala 72:15] node _T_4901 = mux(_T_4900, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4902 = and(_T_4901, way_status_out[107]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4903 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06c")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4902 = and(_T_4901, way_status_out[107]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4903 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06c")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4904 = bits(_T_4903, 0, 0) @[Bitwise.scala 72:15] node _T_4905 = mux(_T_4904, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4906 = and(_T_4905, way_status_out[108]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4907 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06d")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4906 = and(_T_4905, way_status_out[108]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4907 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06d")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4908 = bits(_T_4907, 0, 0) @[Bitwise.scala 72:15] node _T_4909 = mux(_T_4908, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4910 = and(_T_4909, way_status_out[109]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4911 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06e")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4910 = and(_T_4909, way_status_out[109]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4911 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06e")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4912 = bits(_T_4911, 0, 0) @[Bitwise.scala 72:15] node _T_4913 = mux(_T_4912, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4914 = and(_T_4913, way_status_out[110]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4915 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06f")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4914 = and(_T_4913, way_status_out[110]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4915 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06f")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4916 = bits(_T_4915, 0, 0) @[Bitwise.scala 72:15] node _T_4917 = mux(_T_4916, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4918 = and(_T_4917, way_status_out[111]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4919 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h070")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4918 = and(_T_4917, way_status_out[111]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4919 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h070")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4920 = bits(_T_4919, 0, 0) @[Bitwise.scala 72:15] node _T_4921 = mux(_T_4920, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4922 = and(_T_4921, way_status_out[112]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4923 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h071")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4922 = and(_T_4921, way_status_out[112]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4923 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h071")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4924 = bits(_T_4923, 0, 0) @[Bitwise.scala 72:15] node _T_4925 = mux(_T_4924, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4926 = and(_T_4925, way_status_out[113]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4927 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h072")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4926 = and(_T_4925, way_status_out[113]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4927 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h072")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4928 = bits(_T_4927, 0, 0) @[Bitwise.scala 72:15] node _T_4929 = mux(_T_4928, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4930 = and(_T_4929, way_status_out[114]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4931 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h073")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4930 = and(_T_4929, way_status_out[114]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4931 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h073")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4932 = bits(_T_4931, 0, 0) @[Bitwise.scala 72:15] node _T_4933 = mux(_T_4932, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4934 = and(_T_4933, way_status_out[115]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4935 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h074")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4934 = and(_T_4933, way_status_out[115]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4935 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h074")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4936 = bits(_T_4935, 0, 0) @[Bitwise.scala 72:15] node _T_4937 = mux(_T_4936, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4938 = and(_T_4937, way_status_out[116]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4939 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h075")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4938 = and(_T_4937, way_status_out[116]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4939 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h075")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4940 = bits(_T_4939, 0, 0) @[Bitwise.scala 72:15] node _T_4941 = mux(_T_4940, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4942 = and(_T_4941, way_status_out[117]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4943 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h076")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4942 = and(_T_4941, way_status_out[117]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4943 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h076")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4944 = bits(_T_4943, 0, 0) @[Bitwise.scala 72:15] node _T_4945 = mux(_T_4944, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4946 = and(_T_4945, way_status_out[118]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4947 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h077")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4946 = and(_T_4945, way_status_out[118]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4947 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h077")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4948 = bits(_T_4947, 0, 0) @[Bitwise.scala 72:15] node _T_4949 = mux(_T_4948, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4950 = and(_T_4949, way_status_out[119]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4951 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h078")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4950 = and(_T_4949, way_status_out[119]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4951 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h078")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4952 = bits(_T_4951, 0, 0) @[Bitwise.scala 72:15] node _T_4953 = mux(_T_4952, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4954 = and(_T_4953, way_status_out[120]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4955 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h079")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4954 = and(_T_4953, way_status_out[120]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4955 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h079")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4956 = bits(_T_4955, 0, 0) @[Bitwise.scala 72:15] node _T_4957 = mux(_T_4956, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4958 = and(_T_4957, way_status_out[121]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4959 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07a")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4958 = and(_T_4957, way_status_out[121]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4959 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07a")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4960 = bits(_T_4959, 0, 0) @[Bitwise.scala 72:15] node _T_4961 = mux(_T_4960, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4962 = and(_T_4961, way_status_out[122]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4963 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07b")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4962 = and(_T_4961, way_status_out[122]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4963 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07b")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4964 = bits(_T_4963, 0, 0) @[Bitwise.scala 72:15] node _T_4965 = mux(_T_4964, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4966 = and(_T_4965, way_status_out[123]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4967 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07c")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4966 = and(_T_4965, way_status_out[123]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4967 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07c")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4968 = bits(_T_4967, 0, 0) @[Bitwise.scala 72:15] node _T_4969 = mux(_T_4968, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4970 = and(_T_4969, way_status_out[124]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4971 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07d")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4970 = and(_T_4969, way_status_out[124]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4971 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07d")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4972 = bits(_T_4971, 0, 0) @[Bitwise.scala 72:15] node _T_4973 = mux(_T_4972, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4974 = and(_T_4973, way_status_out[125]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4975 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07e")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4974 = and(_T_4973, way_status_out[125]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4975 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07e")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4976 = bits(_T_4975, 0, 0) @[Bitwise.scala 72:15] node _T_4977 = mux(_T_4976, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4978 = and(_T_4977, way_status_out[126]) @[el2_ifu_mem_ctl.scala 716:130] - node _T_4979 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07f")) @[el2_ifu_mem_ctl.scala 716:121] + node _T_4978 = and(_T_4977, way_status_out[126]) @[el2_ifu_mem_ctl.scala 717:130] + node _T_4979 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07f")) @[el2_ifu_mem_ctl.scala 717:121] node _T_4980 = bits(_T_4979, 0, 0) @[Bitwise.scala 72:15] node _T_4981 = mux(_T_4980, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] - node _T_4982 = and(_T_4981, way_status_out[127]) @[el2_ifu_mem_ctl.scala 716:130] + node _T_4982 = and(_T_4981, way_status_out[127]) @[el2_ifu_mem_ctl.scala 717:130] node _T_4983 = cat(_T_4982, _T_4978) @[Cat.scala 29:58] node _T_4984 = cat(_T_4983, _T_4974) @[Cat.scala 29:58] node _T_4985 = cat(_T_4984, _T_4970) @[Cat.scala 29:58] @@ -7261,6124 +7261,6124 @@ circuit el2_ifu_mem_ctl : node _T_5107 = cat(_T_5106, _T_4482) @[Cat.scala 29:58] node _T_5108 = cat(_T_5107, _T_4478) @[Cat.scala 29:58] node _T_5109 = cat(_T_5108, _T_4474) @[Cat.scala 29:58] - way_status <= _T_5109 @[el2_ifu_mem_ctl.scala 716:16] - node _T_5110 = or(io.ic_debug_rd_en, io.ic_debug_wr_en) @[el2_ifu_mem_ctl.scala 717:61] - node _T_5111 = and(_T_5110, io.ic_debug_tag_array) @[el2_ifu_mem_ctl.scala 717:82] - node _T_5112 = bits(io.ic_debug_addr, 9, 3) @[el2_ifu_mem_ctl.scala 718:23] - node _T_5113 = bits(ifu_ic_rw_int_addr, 11, 5) @[el2_ifu_mem_ctl.scala 718:89] - node ifu_ic_rw_int_addr_w_debug = mux(_T_5111, _T_5112, _T_5113) @[el2_ifu_mem_ctl.scala 717:41] - reg _T_5114 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 720:14] - _T_5114 <= ifu_ic_rw_int_addr_w_debug @[el2_ifu_mem_ctl.scala 720:14] - ifu_ic_rw_int_addr_ff <= _T_5114 @[el2_ifu_mem_ctl.scala 719:27] + way_status <= _T_5109 @[el2_ifu_mem_ctl.scala 717:16] + node _T_5110 = or(io.ic_debug_rd_en, io.ic_debug_wr_en) @[el2_ifu_mem_ctl.scala 718:61] + node _T_5111 = and(_T_5110, io.ic_debug_tag_array) @[el2_ifu_mem_ctl.scala 718:82] + node _T_5112 = bits(io.ic_debug_addr, 9, 3) @[el2_ifu_mem_ctl.scala 719:23] + node _T_5113 = bits(ifu_ic_rw_int_addr, 11, 5) @[el2_ifu_mem_ctl.scala 719:89] + node ifu_ic_rw_int_addr_w_debug = mux(_T_5111, _T_5112, _T_5113) @[el2_ifu_mem_ctl.scala 718:41] + reg _T_5114 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 721:14] + _T_5114 <= ifu_ic_rw_int_addr_w_debug @[el2_ifu_mem_ctl.scala 721:14] + ifu_ic_rw_int_addr_ff <= _T_5114 @[el2_ifu_mem_ctl.scala 720:27] wire ifu_tag_wren : UInt<2> ifu_tag_wren <= UInt<1>("h00") wire ic_debug_tag_wr_en : UInt<2> ic_debug_tag_wr_en <= UInt<1>("h00") - node ifu_tag_wren_w_debug = or(ifu_tag_wren, ic_debug_tag_wr_en) @[el2_ifu_mem_ctl.scala 724:45] - reg ifu_tag_wren_ff : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 726:14] - ifu_tag_wren_ff <= ifu_tag_wren_w_debug @[el2_ifu_mem_ctl.scala 726:14] - node _T_5115 = and(io.ic_debug_wr_en, io.ic_debug_tag_array) @[el2_ifu_mem_ctl.scala 728:50] - node _T_5116 = bits(io.ic_debug_wr_data, 0, 0) @[el2_ifu_mem_ctl.scala 728:94] - node ic_valid_w_debug = mux(_T_5115, _T_5116, ic_valid) @[el2_ifu_mem_ctl.scala 728:31] - reg ic_valid_ff : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 730:14] - ic_valid_ff <= ic_valid_w_debug @[el2_ifu_mem_ctl.scala 730:14] - node _T_5117 = bits(ifu_ic_rw_int_addr_ff, 5, 4) @[el2_ifu_mem_ctl.scala 734:35] - node _T_5118 = eq(_T_5117, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 734:82] - node _T_5119 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 734:108] - node _T_5120 = and(_T_5118, _T_5119) @[el2_ifu_mem_ctl.scala 734:91] - node _T_5121 = bits(perr_ic_index_ff, 5, 4) @[el2_ifu_mem_ctl.scala 735:27] - node _T_5122 = eq(_T_5121, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 735:74] - node _T_5123 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 735:101] - node _T_5124 = and(_T_5122, _T_5123) @[el2_ifu_mem_ctl.scala 735:83] - node _T_5125 = or(_T_5120, _T_5124) @[el2_ifu_mem_ctl.scala 734:113] - node _T_5126 = or(_T_5125, reset_all_tags) @[el2_ifu_mem_ctl.scala 735:106] - node _T_5127 = bits(ifu_ic_rw_int_addr_ff, 5, 4) @[el2_ifu_mem_ctl.scala 734:35] - node _T_5128 = eq(_T_5127, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 734:82] - node _T_5129 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 734:108] - node _T_5130 = and(_T_5128, _T_5129) @[el2_ifu_mem_ctl.scala 734:91] - node _T_5131 = bits(perr_ic_index_ff, 5, 4) @[el2_ifu_mem_ctl.scala 735:27] - node _T_5132 = eq(_T_5131, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 735:74] - node _T_5133 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 735:101] - node _T_5134 = and(_T_5132, _T_5133) @[el2_ifu_mem_ctl.scala 735:83] - node _T_5135 = or(_T_5130, _T_5134) @[el2_ifu_mem_ctl.scala 734:113] - node _T_5136 = or(_T_5135, reset_all_tags) @[el2_ifu_mem_ctl.scala 735:106] + node ifu_tag_wren_w_debug = or(ifu_tag_wren, ic_debug_tag_wr_en) @[el2_ifu_mem_ctl.scala 725:45] + reg ifu_tag_wren_ff : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 727:14] + ifu_tag_wren_ff <= ifu_tag_wren_w_debug @[el2_ifu_mem_ctl.scala 727:14] + node _T_5115 = and(io.ic_debug_wr_en, io.ic_debug_tag_array) @[el2_ifu_mem_ctl.scala 729:50] + node _T_5116 = bits(io.ic_debug_wr_data, 0, 0) @[el2_ifu_mem_ctl.scala 729:94] + node ic_valid_w_debug = mux(_T_5115, _T_5116, ic_valid) @[el2_ifu_mem_ctl.scala 729:31] + reg ic_valid_ff : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 731:14] + ic_valid_ff <= ic_valid_w_debug @[el2_ifu_mem_ctl.scala 731:14] + node _T_5117 = bits(ifu_ic_rw_int_addr_ff, 5, 4) @[el2_ifu_mem_ctl.scala 735:35] + node _T_5118 = eq(_T_5117, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 735:82] + node _T_5119 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 735:108] + node _T_5120 = and(_T_5118, _T_5119) @[el2_ifu_mem_ctl.scala 735:91] + node _T_5121 = bits(perr_ic_index_ff, 5, 4) @[el2_ifu_mem_ctl.scala 736:27] + node _T_5122 = eq(_T_5121, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 736:74] + node _T_5123 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 736:101] + node _T_5124 = and(_T_5122, _T_5123) @[el2_ifu_mem_ctl.scala 736:83] + node _T_5125 = or(_T_5120, _T_5124) @[el2_ifu_mem_ctl.scala 735:113] + node _T_5126 = or(_T_5125, reset_all_tags) @[el2_ifu_mem_ctl.scala 736:106] + node _T_5127 = bits(ifu_ic_rw_int_addr_ff, 5, 4) @[el2_ifu_mem_ctl.scala 735:35] + node _T_5128 = eq(_T_5127, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 735:82] + node _T_5129 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 735:108] + node _T_5130 = and(_T_5128, _T_5129) @[el2_ifu_mem_ctl.scala 735:91] + node _T_5131 = bits(perr_ic_index_ff, 5, 4) @[el2_ifu_mem_ctl.scala 736:27] + node _T_5132 = eq(_T_5131, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 736:74] + node _T_5133 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 736:101] + node _T_5134 = and(_T_5132, _T_5133) @[el2_ifu_mem_ctl.scala 736:83] + node _T_5135 = or(_T_5130, _T_5134) @[el2_ifu_mem_ctl.scala 735:113] + node _T_5136 = or(_T_5135, reset_all_tags) @[el2_ifu_mem_ctl.scala 736:106] node tag_valid_clken_0 = cat(_T_5126, _T_5136) @[Cat.scala 29:58] - node _T_5137 = bits(ifu_ic_rw_int_addr_ff, 5, 4) @[el2_ifu_mem_ctl.scala 734:35] - node _T_5138 = eq(_T_5137, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 734:82] - node _T_5139 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 734:108] - node _T_5140 = and(_T_5138, _T_5139) @[el2_ifu_mem_ctl.scala 734:91] - node _T_5141 = bits(perr_ic_index_ff, 5, 4) @[el2_ifu_mem_ctl.scala 735:27] - node _T_5142 = eq(_T_5141, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 735:74] - node _T_5143 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 735:101] - node _T_5144 = and(_T_5142, _T_5143) @[el2_ifu_mem_ctl.scala 735:83] - node _T_5145 = or(_T_5140, _T_5144) @[el2_ifu_mem_ctl.scala 734:113] - node _T_5146 = or(_T_5145, reset_all_tags) @[el2_ifu_mem_ctl.scala 735:106] - node _T_5147 = bits(ifu_ic_rw_int_addr_ff, 5, 4) @[el2_ifu_mem_ctl.scala 734:35] - node _T_5148 = eq(_T_5147, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 734:82] - node _T_5149 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 734:108] - node _T_5150 = and(_T_5148, _T_5149) @[el2_ifu_mem_ctl.scala 734:91] - node _T_5151 = bits(perr_ic_index_ff, 5, 4) @[el2_ifu_mem_ctl.scala 735:27] - node _T_5152 = eq(_T_5151, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 735:74] - node _T_5153 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 735:101] - node _T_5154 = and(_T_5152, _T_5153) @[el2_ifu_mem_ctl.scala 735:83] - node _T_5155 = or(_T_5150, _T_5154) @[el2_ifu_mem_ctl.scala 734:113] - node _T_5156 = or(_T_5155, reset_all_tags) @[el2_ifu_mem_ctl.scala 735:106] + node _T_5137 = bits(ifu_ic_rw_int_addr_ff, 5, 4) @[el2_ifu_mem_ctl.scala 735:35] + node _T_5138 = eq(_T_5137, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 735:82] + node _T_5139 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 735:108] + node _T_5140 = and(_T_5138, _T_5139) @[el2_ifu_mem_ctl.scala 735:91] + node _T_5141 = bits(perr_ic_index_ff, 5, 4) @[el2_ifu_mem_ctl.scala 736:27] + node _T_5142 = eq(_T_5141, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 736:74] + node _T_5143 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 736:101] + node _T_5144 = and(_T_5142, _T_5143) @[el2_ifu_mem_ctl.scala 736:83] + node _T_5145 = or(_T_5140, _T_5144) @[el2_ifu_mem_ctl.scala 735:113] + node _T_5146 = or(_T_5145, reset_all_tags) @[el2_ifu_mem_ctl.scala 736:106] + node _T_5147 = bits(ifu_ic_rw_int_addr_ff, 5, 4) @[el2_ifu_mem_ctl.scala 735:35] + node _T_5148 = eq(_T_5147, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 735:82] + node _T_5149 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 735:108] + node _T_5150 = and(_T_5148, _T_5149) @[el2_ifu_mem_ctl.scala 735:91] + node _T_5151 = bits(perr_ic_index_ff, 5, 4) @[el2_ifu_mem_ctl.scala 736:27] + node _T_5152 = eq(_T_5151, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 736:74] + node _T_5153 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 736:101] + node _T_5154 = and(_T_5152, _T_5153) @[el2_ifu_mem_ctl.scala 736:83] + node _T_5155 = or(_T_5150, _T_5154) @[el2_ifu_mem_ctl.scala 735:113] + node _T_5156 = or(_T_5155, reset_all_tags) @[el2_ifu_mem_ctl.scala 736:106] node tag_valid_clken_1 = cat(_T_5146, _T_5156) @[Cat.scala 29:58] - node _T_5157 = bits(ifu_ic_rw_int_addr_ff, 5, 4) @[el2_ifu_mem_ctl.scala 734:35] - node _T_5158 = eq(_T_5157, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 734:82] - node _T_5159 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 734:108] - node _T_5160 = and(_T_5158, _T_5159) @[el2_ifu_mem_ctl.scala 734:91] - node _T_5161 = bits(perr_ic_index_ff, 5, 4) @[el2_ifu_mem_ctl.scala 735:27] - node _T_5162 = eq(_T_5161, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 735:74] - node _T_5163 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 735:101] - node _T_5164 = and(_T_5162, _T_5163) @[el2_ifu_mem_ctl.scala 735:83] - node _T_5165 = or(_T_5160, _T_5164) @[el2_ifu_mem_ctl.scala 734:113] - node _T_5166 = or(_T_5165, reset_all_tags) @[el2_ifu_mem_ctl.scala 735:106] - node _T_5167 = bits(ifu_ic_rw_int_addr_ff, 5, 4) @[el2_ifu_mem_ctl.scala 734:35] - node _T_5168 = eq(_T_5167, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 734:82] - node _T_5169 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 734:108] - node _T_5170 = and(_T_5168, _T_5169) @[el2_ifu_mem_ctl.scala 734:91] - node _T_5171 = bits(perr_ic_index_ff, 5, 4) @[el2_ifu_mem_ctl.scala 735:27] - node _T_5172 = eq(_T_5171, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 735:74] - node _T_5173 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 735:101] - node _T_5174 = and(_T_5172, _T_5173) @[el2_ifu_mem_ctl.scala 735:83] - node _T_5175 = or(_T_5170, _T_5174) @[el2_ifu_mem_ctl.scala 734:113] - node _T_5176 = or(_T_5175, reset_all_tags) @[el2_ifu_mem_ctl.scala 735:106] + node _T_5157 = bits(ifu_ic_rw_int_addr_ff, 5, 4) @[el2_ifu_mem_ctl.scala 735:35] + node _T_5158 = eq(_T_5157, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 735:82] + node _T_5159 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 735:108] + node _T_5160 = and(_T_5158, _T_5159) @[el2_ifu_mem_ctl.scala 735:91] + node _T_5161 = bits(perr_ic_index_ff, 5, 4) @[el2_ifu_mem_ctl.scala 736:27] + node _T_5162 = eq(_T_5161, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 736:74] + node _T_5163 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 736:101] + node _T_5164 = and(_T_5162, _T_5163) @[el2_ifu_mem_ctl.scala 736:83] + node _T_5165 = or(_T_5160, _T_5164) @[el2_ifu_mem_ctl.scala 735:113] + node _T_5166 = or(_T_5165, reset_all_tags) @[el2_ifu_mem_ctl.scala 736:106] + node _T_5167 = bits(ifu_ic_rw_int_addr_ff, 5, 4) @[el2_ifu_mem_ctl.scala 735:35] + node _T_5168 = eq(_T_5167, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 735:82] + node _T_5169 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 735:108] + node _T_5170 = and(_T_5168, _T_5169) @[el2_ifu_mem_ctl.scala 735:91] + node _T_5171 = bits(perr_ic_index_ff, 5, 4) @[el2_ifu_mem_ctl.scala 736:27] + node _T_5172 = eq(_T_5171, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 736:74] + node _T_5173 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 736:101] + node _T_5174 = and(_T_5172, _T_5173) @[el2_ifu_mem_ctl.scala 736:83] + node _T_5175 = or(_T_5170, _T_5174) @[el2_ifu_mem_ctl.scala 735:113] + node _T_5176 = or(_T_5175, reset_all_tags) @[el2_ifu_mem_ctl.scala 736:106] node tag_valid_clken_2 = cat(_T_5166, _T_5176) @[Cat.scala 29:58] - node _T_5177 = bits(ifu_ic_rw_int_addr_ff, 5, 4) @[el2_ifu_mem_ctl.scala 734:35] - node _T_5178 = eq(_T_5177, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 734:82] - node _T_5179 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 734:108] - node _T_5180 = and(_T_5178, _T_5179) @[el2_ifu_mem_ctl.scala 734:91] - node _T_5181 = bits(perr_ic_index_ff, 5, 4) @[el2_ifu_mem_ctl.scala 735:27] - node _T_5182 = eq(_T_5181, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 735:74] - node _T_5183 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 735:101] - node _T_5184 = and(_T_5182, _T_5183) @[el2_ifu_mem_ctl.scala 735:83] - node _T_5185 = or(_T_5180, _T_5184) @[el2_ifu_mem_ctl.scala 734:113] - node _T_5186 = or(_T_5185, reset_all_tags) @[el2_ifu_mem_ctl.scala 735:106] - node _T_5187 = bits(ifu_ic_rw_int_addr_ff, 5, 4) @[el2_ifu_mem_ctl.scala 734:35] - node _T_5188 = eq(_T_5187, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 734:82] - node _T_5189 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 734:108] - node _T_5190 = and(_T_5188, _T_5189) @[el2_ifu_mem_ctl.scala 734:91] - node _T_5191 = bits(perr_ic_index_ff, 5, 4) @[el2_ifu_mem_ctl.scala 735:27] - node _T_5192 = eq(_T_5191, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 735:74] - node _T_5193 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 735:101] - node _T_5194 = and(_T_5192, _T_5193) @[el2_ifu_mem_ctl.scala 735:83] - node _T_5195 = or(_T_5190, _T_5194) @[el2_ifu_mem_ctl.scala 734:113] - node _T_5196 = or(_T_5195, reset_all_tags) @[el2_ifu_mem_ctl.scala 735:106] + node _T_5177 = bits(ifu_ic_rw_int_addr_ff, 5, 4) @[el2_ifu_mem_ctl.scala 735:35] + node _T_5178 = eq(_T_5177, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 735:82] + node _T_5179 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 735:108] + node _T_5180 = and(_T_5178, _T_5179) @[el2_ifu_mem_ctl.scala 735:91] + node _T_5181 = bits(perr_ic_index_ff, 5, 4) @[el2_ifu_mem_ctl.scala 736:27] + node _T_5182 = eq(_T_5181, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 736:74] + node _T_5183 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 736:101] + node _T_5184 = and(_T_5182, _T_5183) @[el2_ifu_mem_ctl.scala 736:83] + node _T_5185 = or(_T_5180, _T_5184) @[el2_ifu_mem_ctl.scala 735:113] + node _T_5186 = or(_T_5185, reset_all_tags) @[el2_ifu_mem_ctl.scala 736:106] + node _T_5187 = bits(ifu_ic_rw_int_addr_ff, 5, 4) @[el2_ifu_mem_ctl.scala 735:35] + node _T_5188 = eq(_T_5187, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 735:82] + node _T_5189 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 735:108] + node _T_5190 = and(_T_5188, _T_5189) @[el2_ifu_mem_ctl.scala 735:91] + node _T_5191 = bits(perr_ic_index_ff, 5, 4) @[el2_ifu_mem_ctl.scala 736:27] + node _T_5192 = eq(_T_5191, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 736:74] + node _T_5193 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 736:101] + node _T_5194 = and(_T_5192, _T_5193) @[el2_ifu_mem_ctl.scala 736:83] + node _T_5195 = or(_T_5190, _T_5194) @[el2_ifu_mem_ctl.scala 735:113] + node _T_5196 = or(_T_5195, reset_all_tags) @[el2_ifu_mem_ctl.scala 736:106] node tag_valid_clken_3 = cat(_T_5186, _T_5196) @[Cat.scala 29:58] - wire ic_tag_valid_out : UInt<1>[128][2] @[el2_ifu_mem_ctl.scala 738:32] - node _T_5197 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_5198 = eq(_T_5197, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_5199 = and(ic_valid_ff, _T_5198) @[el2_ifu_mem_ctl.scala 740:64] - node _T_5200 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_5201 = and(_T_5199, _T_5200) @[el2_ifu_mem_ctl.scala 740:89] - node _T_5202 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_5203 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_5204 = and(_T_5202, _T_5203) @[el2_ifu_mem_ctl.scala 741:58] - node _T_5205 = eq(perr_ic_index_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_5206 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_5207 = and(_T_5205, _T_5206) @[el2_ifu_mem_ctl.scala 741:123] - node _T_5208 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_5209 = and(_T_5207, _T_5208) @[el2_ifu_mem_ctl.scala 741:144] - node _T_5210 = or(_T_5204, _T_5209) @[el2_ifu_mem_ctl.scala 741:80] - node _T_5211 = bits(_T_5210, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + wire ic_tag_valid_out : UInt<1>[128][2] @[el2_ifu_mem_ctl.scala 739:32] + node _T_5197 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_5198 = eq(_T_5197, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_5199 = and(ic_valid_ff, _T_5198) @[el2_ifu_mem_ctl.scala 741:64] + node _T_5200 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_5201 = and(_T_5199, _T_5200) @[el2_ifu_mem_ctl.scala 741:89] + node _T_5202 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_5203 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_5204 = and(_T_5202, _T_5203) @[el2_ifu_mem_ctl.scala 742:58] + node _T_5205 = eq(perr_ic_index_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_5206 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_5207 = and(_T_5205, _T_5206) @[el2_ifu_mem_ctl.scala 742:123] + node _T_5208 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_5209 = and(_T_5207, _T_5208) @[el2_ifu_mem_ctl.scala 742:144] + node _T_5210 = or(_T_5204, _T_5209) @[el2_ifu_mem_ctl.scala 742:80] + node _T_5211 = bits(_T_5210, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_5212 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5211 : @[Reg.scala 28:19] _T_5212 <= _T_5201 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][0] <= _T_5212 @[el2_ifu_mem_ctl.scala 740:39] - node _T_5213 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_5214 = eq(_T_5213, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_5215 = and(ic_valid_ff, _T_5214) @[el2_ifu_mem_ctl.scala 740:64] - node _T_5216 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_5217 = and(_T_5215, _T_5216) @[el2_ifu_mem_ctl.scala 740:89] - node _T_5218 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_5219 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_5220 = and(_T_5218, _T_5219) @[el2_ifu_mem_ctl.scala 741:58] - node _T_5221 = eq(perr_ic_index_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_5222 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_5223 = and(_T_5221, _T_5222) @[el2_ifu_mem_ctl.scala 741:123] - node _T_5224 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_5225 = and(_T_5223, _T_5224) @[el2_ifu_mem_ctl.scala 741:144] - node _T_5226 = or(_T_5220, _T_5225) @[el2_ifu_mem_ctl.scala 741:80] - node _T_5227 = bits(_T_5226, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][0] <= _T_5212 @[el2_ifu_mem_ctl.scala 741:39] + node _T_5213 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_5214 = eq(_T_5213, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_5215 = and(ic_valid_ff, _T_5214) @[el2_ifu_mem_ctl.scala 741:64] + node _T_5216 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_5217 = and(_T_5215, _T_5216) @[el2_ifu_mem_ctl.scala 741:89] + node _T_5218 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_5219 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_5220 = and(_T_5218, _T_5219) @[el2_ifu_mem_ctl.scala 742:58] + node _T_5221 = eq(perr_ic_index_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_5222 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_5223 = and(_T_5221, _T_5222) @[el2_ifu_mem_ctl.scala 742:123] + node _T_5224 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_5225 = and(_T_5223, _T_5224) @[el2_ifu_mem_ctl.scala 742:144] + node _T_5226 = or(_T_5220, _T_5225) @[el2_ifu_mem_ctl.scala 742:80] + node _T_5227 = bits(_T_5226, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_5228 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5227 : @[Reg.scala 28:19] _T_5228 <= _T_5217 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][1] <= _T_5228 @[el2_ifu_mem_ctl.scala 740:39] - node _T_5229 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_5230 = eq(_T_5229, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_5231 = and(ic_valid_ff, _T_5230) @[el2_ifu_mem_ctl.scala 740:64] - node _T_5232 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_5233 = and(_T_5231, _T_5232) @[el2_ifu_mem_ctl.scala 740:89] - node _T_5234 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_5235 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_5236 = and(_T_5234, _T_5235) @[el2_ifu_mem_ctl.scala 741:58] - node _T_5237 = eq(perr_ic_index_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_5238 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_5239 = and(_T_5237, _T_5238) @[el2_ifu_mem_ctl.scala 741:123] - node _T_5240 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_5241 = and(_T_5239, _T_5240) @[el2_ifu_mem_ctl.scala 741:144] - node _T_5242 = or(_T_5236, _T_5241) @[el2_ifu_mem_ctl.scala 741:80] - node _T_5243 = bits(_T_5242, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][1] <= _T_5228 @[el2_ifu_mem_ctl.scala 741:39] + node _T_5229 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_5230 = eq(_T_5229, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_5231 = and(ic_valid_ff, _T_5230) @[el2_ifu_mem_ctl.scala 741:64] + node _T_5232 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_5233 = and(_T_5231, _T_5232) @[el2_ifu_mem_ctl.scala 741:89] + node _T_5234 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_5235 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_5236 = and(_T_5234, _T_5235) @[el2_ifu_mem_ctl.scala 742:58] + node _T_5237 = eq(perr_ic_index_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_5238 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_5239 = and(_T_5237, _T_5238) @[el2_ifu_mem_ctl.scala 742:123] + node _T_5240 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_5241 = and(_T_5239, _T_5240) @[el2_ifu_mem_ctl.scala 742:144] + node _T_5242 = or(_T_5236, _T_5241) @[el2_ifu_mem_ctl.scala 742:80] + node _T_5243 = bits(_T_5242, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_5244 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5243 : @[Reg.scala 28:19] _T_5244 <= _T_5233 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][2] <= _T_5244 @[el2_ifu_mem_ctl.scala 740:39] - node _T_5245 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_5246 = eq(_T_5245, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_5247 = and(ic_valid_ff, _T_5246) @[el2_ifu_mem_ctl.scala 740:64] - node _T_5248 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_5249 = and(_T_5247, _T_5248) @[el2_ifu_mem_ctl.scala 740:89] - node _T_5250 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_5251 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_5252 = and(_T_5250, _T_5251) @[el2_ifu_mem_ctl.scala 741:58] - node _T_5253 = eq(perr_ic_index_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_5254 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_5255 = and(_T_5253, _T_5254) @[el2_ifu_mem_ctl.scala 741:123] - node _T_5256 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_5257 = and(_T_5255, _T_5256) @[el2_ifu_mem_ctl.scala 741:144] - node _T_5258 = or(_T_5252, _T_5257) @[el2_ifu_mem_ctl.scala 741:80] - node _T_5259 = bits(_T_5258, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][2] <= _T_5244 @[el2_ifu_mem_ctl.scala 741:39] + node _T_5245 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_5246 = eq(_T_5245, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_5247 = and(ic_valid_ff, _T_5246) @[el2_ifu_mem_ctl.scala 741:64] + node _T_5248 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_5249 = and(_T_5247, _T_5248) @[el2_ifu_mem_ctl.scala 741:89] + node _T_5250 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_5251 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_5252 = and(_T_5250, _T_5251) @[el2_ifu_mem_ctl.scala 742:58] + node _T_5253 = eq(perr_ic_index_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_5254 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_5255 = and(_T_5253, _T_5254) @[el2_ifu_mem_ctl.scala 742:123] + node _T_5256 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_5257 = and(_T_5255, _T_5256) @[el2_ifu_mem_ctl.scala 742:144] + node _T_5258 = or(_T_5252, _T_5257) @[el2_ifu_mem_ctl.scala 742:80] + node _T_5259 = bits(_T_5258, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_5260 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5259 : @[Reg.scala 28:19] _T_5260 <= _T_5249 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][3] <= _T_5260 @[el2_ifu_mem_ctl.scala 740:39] - node _T_5261 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_5262 = eq(_T_5261, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_5263 = and(ic_valid_ff, _T_5262) @[el2_ifu_mem_ctl.scala 740:64] - node _T_5264 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_5265 = and(_T_5263, _T_5264) @[el2_ifu_mem_ctl.scala 740:89] - node _T_5266 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_5267 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_5268 = and(_T_5266, _T_5267) @[el2_ifu_mem_ctl.scala 741:58] - node _T_5269 = eq(perr_ic_index_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_5270 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_5271 = and(_T_5269, _T_5270) @[el2_ifu_mem_ctl.scala 741:123] - node _T_5272 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_5273 = and(_T_5271, _T_5272) @[el2_ifu_mem_ctl.scala 741:144] - node _T_5274 = or(_T_5268, _T_5273) @[el2_ifu_mem_ctl.scala 741:80] - node _T_5275 = bits(_T_5274, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][3] <= _T_5260 @[el2_ifu_mem_ctl.scala 741:39] + node _T_5261 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_5262 = eq(_T_5261, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_5263 = and(ic_valid_ff, _T_5262) @[el2_ifu_mem_ctl.scala 741:64] + node _T_5264 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_5265 = and(_T_5263, _T_5264) @[el2_ifu_mem_ctl.scala 741:89] + node _T_5266 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_5267 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_5268 = and(_T_5266, _T_5267) @[el2_ifu_mem_ctl.scala 742:58] + node _T_5269 = eq(perr_ic_index_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_5270 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_5271 = and(_T_5269, _T_5270) @[el2_ifu_mem_ctl.scala 742:123] + node _T_5272 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_5273 = and(_T_5271, _T_5272) @[el2_ifu_mem_ctl.scala 742:144] + node _T_5274 = or(_T_5268, _T_5273) @[el2_ifu_mem_ctl.scala 742:80] + node _T_5275 = bits(_T_5274, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_5276 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5275 : @[Reg.scala 28:19] _T_5276 <= _T_5265 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][4] <= _T_5276 @[el2_ifu_mem_ctl.scala 740:39] - node _T_5277 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_5278 = eq(_T_5277, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_5279 = and(ic_valid_ff, _T_5278) @[el2_ifu_mem_ctl.scala 740:64] - node _T_5280 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_5281 = and(_T_5279, _T_5280) @[el2_ifu_mem_ctl.scala 740:89] - node _T_5282 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_5283 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_5284 = and(_T_5282, _T_5283) @[el2_ifu_mem_ctl.scala 741:58] - node _T_5285 = eq(perr_ic_index_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_5286 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_5287 = and(_T_5285, _T_5286) @[el2_ifu_mem_ctl.scala 741:123] - node _T_5288 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_5289 = and(_T_5287, _T_5288) @[el2_ifu_mem_ctl.scala 741:144] - node _T_5290 = or(_T_5284, _T_5289) @[el2_ifu_mem_ctl.scala 741:80] - node _T_5291 = bits(_T_5290, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][4] <= _T_5276 @[el2_ifu_mem_ctl.scala 741:39] + node _T_5277 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_5278 = eq(_T_5277, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_5279 = and(ic_valid_ff, _T_5278) @[el2_ifu_mem_ctl.scala 741:64] + node _T_5280 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_5281 = and(_T_5279, _T_5280) @[el2_ifu_mem_ctl.scala 741:89] + node _T_5282 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_5283 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_5284 = and(_T_5282, _T_5283) @[el2_ifu_mem_ctl.scala 742:58] + node _T_5285 = eq(perr_ic_index_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_5286 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_5287 = and(_T_5285, _T_5286) @[el2_ifu_mem_ctl.scala 742:123] + node _T_5288 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_5289 = and(_T_5287, _T_5288) @[el2_ifu_mem_ctl.scala 742:144] + node _T_5290 = or(_T_5284, _T_5289) @[el2_ifu_mem_ctl.scala 742:80] + node _T_5291 = bits(_T_5290, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_5292 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5291 : @[Reg.scala 28:19] _T_5292 <= _T_5281 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][5] <= _T_5292 @[el2_ifu_mem_ctl.scala 740:39] - node _T_5293 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_5294 = eq(_T_5293, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_5295 = and(ic_valid_ff, _T_5294) @[el2_ifu_mem_ctl.scala 740:64] - node _T_5296 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_5297 = and(_T_5295, _T_5296) @[el2_ifu_mem_ctl.scala 740:89] - node _T_5298 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_5299 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_5300 = and(_T_5298, _T_5299) @[el2_ifu_mem_ctl.scala 741:58] - node _T_5301 = eq(perr_ic_index_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_5302 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_5303 = and(_T_5301, _T_5302) @[el2_ifu_mem_ctl.scala 741:123] - node _T_5304 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_5305 = and(_T_5303, _T_5304) @[el2_ifu_mem_ctl.scala 741:144] - node _T_5306 = or(_T_5300, _T_5305) @[el2_ifu_mem_ctl.scala 741:80] - node _T_5307 = bits(_T_5306, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][5] <= _T_5292 @[el2_ifu_mem_ctl.scala 741:39] + node _T_5293 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_5294 = eq(_T_5293, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_5295 = and(ic_valid_ff, _T_5294) @[el2_ifu_mem_ctl.scala 741:64] + node _T_5296 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_5297 = and(_T_5295, _T_5296) @[el2_ifu_mem_ctl.scala 741:89] + node _T_5298 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_5299 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_5300 = and(_T_5298, _T_5299) @[el2_ifu_mem_ctl.scala 742:58] + node _T_5301 = eq(perr_ic_index_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_5302 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_5303 = and(_T_5301, _T_5302) @[el2_ifu_mem_ctl.scala 742:123] + node _T_5304 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_5305 = and(_T_5303, _T_5304) @[el2_ifu_mem_ctl.scala 742:144] + node _T_5306 = or(_T_5300, _T_5305) @[el2_ifu_mem_ctl.scala 742:80] + node _T_5307 = bits(_T_5306, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_5308 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5307 : @[Reg.scala 28:19] _T_5308 <= _T_5297 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][6] <= _T_5308 @[el2_ifu_mem_ctl.scala 740:39] - node _T_5309 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_5310 = eq(_T_5309, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_5311 = and(ic_valid_ff, _T_5310) @[el2_ifu_mem_ctl.scala 740:64] - node _T_5312 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_5313 = and(_T_5311, _T_5312) @[el2_ifu_mem_ctl.scala 740:89] - node _T_5314 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_5315 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_5316 = and(_T_5314, _T_5315) @[el2_ifu_mem_ctl.scala 741:58] - node _T_5317 = eq(perr_ic_index_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_5318 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_5319 = and(_T_5317, _T_5318) @[el2_ifu_mem_ctl.scala 741:123] - node _T_5320 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_5321 = and(_T_5319, _T_5320) @[el2_ifu_mem_ctl.scala 741:144] - node _T_5322 = or(_T_5316, _T_5321) @[el2_ifu_mem_ctl.scala 741:80] - node _T_5323 = bits(_T_5322, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][6] <= _T_5308 @[el2_ifu_mem_ctl.scala 741:39] + node _T_5309 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_5310 = eq(_T_5309, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_5311 = and(ic_valid_ff, _T_5310) @[el2_ifu_mem_ctl.scala 741:64] + node _T_5312 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_5313 = and(_T_5311, _T_5312) @[el2_ifu_mem_ctl.scala 741:89] + node _T_5314 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_5315 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_5316 = and(_T_5314, _T_5315) @[el2_ifu_mem_ctl.scala 742:58] + node _T_5317 = eq(perr_ic_index_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_5318 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_5319 = and(_T_5317, _T_5318) @[el2_ifu_mem_ctl.scala 742:123] + node _T_5320 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_5321 = and(_T_5319, _T_5320) @[el2_ifu_mem_ctl.scala 742:144] + node _T_5322 = or(_T_5316, _T_5321) @[el2_ifu_mem_ctl.scala 742:80] + node _T_5323 = bits(_T_5322, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_5324 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5323 : @[Reg.scala 28:19] _T_5324 <= _T_5313 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][7] <= _T_5324 @[el2_ifu_mem_ctl.scala 740:39] - node _T_5325 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_5326 = eq(_T_5325, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_5327 = and(ic_valid_ff, _T_5326) @[el2_ifu_mem_ctl.scala 740:64] - node _T_5328 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_5329 = and(_T_5327, _T_5328) @[el2_ifu_mem_ctl.scala 740:89] - node _T_5330 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_5331 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_5332 = and(_T_5330, _T_5331) @[el2_ifu_mem_ctl.scala 741:58] - node _T_5333 = eq(perr_ic_index_ff, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_5334 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_5335 = and(_T_5333, _T_5334) @[el2_ifu_mem_ctl.scala 741:123] - node _T_5336 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_5337 = and(_T_5335, _T_5336) @[el2_ifu_mem_ctl.scala 741:144] - node _T_5338 = or(_T_5332, _T_5337) @[el2_ifu_mem_ctl.scala 741:80] - node _T_5339 = bits(_T_5338, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][7] <= _T_5324 @[el2_ifu_mem_ctl.scala 741:39] + node _T_5325 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_5326 = eq(_T_5325, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_5327 = and(ic_valid_ff, _T_5326) @[el2_ifu_mem_ctl.scala 741:64] + node _T_5328 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_5329 = and(_T_5327, _T_5328) @[el2_ifu_mem_ctl.scala 741:89] + node _T_5330 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_5331 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_5332 = and(_T_5330, _T_5331) @[el2_ifu_mem_ctl.scala 742:58] + node _T_5333 = eq(perr_ic_index_ff, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_5334 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_5335 = and(_T_5333, _T_5334) @[el2_ifu_mem_ctl.scala 742:123] + node _T_5336 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_5337 = and(_T_5335, _T_5336) @[el2_ifu_mem_ctl.scala 742:144] + node _T_5338 = or(_T_5332, _T_5337) @[el2_ifu_mem_ctl.scala 742:80] + node _T_5339 = bits(_T_5338, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_5340 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5339 : @[Reg.scala 28:19] _T_5340 <= _T_5329 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][8] <= _T_5340 @[el2_ifu_mem_ctl.scala 740:39] - node _T_5341 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_5342 = eq(_T_5341, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_5343 = and(ic_valid_ff, _T_5342) @[el2_ifu_mem_ctl.scala 740:64] - node _T_5344 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_5345 = and(_T_5343, _T_5344) @[el2_ifu_mem_ctl.scala 740:89] - node _T_5346 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_5347 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_5348 = and(_T_5346, _T_5347) @[el2_ifu_mem_ctl.scala 741:58] - node _T_5349 = eq(perr_ic_index_ff, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_5350 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_5351 = and(_T_5349, _T_5350) @[el2_ifu_mem_ctl.scala 741:123] - node _T_5352 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_5353 = and(_T_5351, _T_5352) @[el2_ifu_mem_ctl.scala 741:144] - node _T_5354 = or(_T_5348, _T_5353) @[el2_ifu_mem_ctl.scala 741:80] - node _T_5355 = bits(_T_5354, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][8] <= _T_5340 @[el2_ifu_mem_ctl.scala 741:39] + node _T_5341 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_5342 = eq(_T_5341, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_5343 = and(ic_valid_ff, _T_5342) @[el2_ifu_mem_ctl.scala 741:64] + node _T_5344 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_5345 = and(_T_5343, _T_5344) @[el2_ifu_mem_ctl.scala 741:89] + node _T_5346 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_5347 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_5348 = and(_T_5346, _T_5347) @[el2_ifu_mem_ctl.scala 742:58] + node _T_5349 = eq(perr_ic_index_ff, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_5350 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_5351 = and(_T_5349, _T_5350) @[el2_ifu_mem_ctl.scala 742:123] + node _T_5352 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_5353 = and(_T_5351, _T_5352) @[el2_ifu_mem_ctl.scala 742:144] + node _T_5354 = or(_T_5348, _T_5353) @[el2_ifu_mem_ctl.scala 742:80] + node _T_5355 = bits(_T_5354, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_5356 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5355 : @[Reg.scala 28:19] _T_5356 <= _T_5345 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][9] <= _T_5356 @[el2_ifu_mem_ctl.scala 740:39] - node _T_5357 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_5358 = eq(_T_5357, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_5359 = and(ic_valid_ff, _T_5358) @[el2_ifu_mem_ctl.scala 740:64] - node _T_5360 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_5361 = and(_T_5359, _T_5360) @[el2_ifu_mem_ctl.scala 740:89] - node _T_5362 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_5363 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_5364 = and(_T_5362, _T_5363) @[el2_ifu_mem_ctl.scala 741:58] - node _T_5365 = eq(perr_ic_index_ff, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_5366 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_5367 = and(_T_5365, _T_5366) @[el2_ifu_mem_ctl.scala 741:123] - node _T_5368 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_5369 = and(_T_5367, _T_5368) @[el2_ifu_mem_ctl.scala 741:144] - node _T_5370 = or(_T_5364, _T_5369) @[el2_ifu_mem_ctl.scala 741:80] - node _T_5371 = bits(_T_5370, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][9] <= _T_5356 @[el2_ifu_mem_ctl.scala 741:39] + node _T_5357 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_5358 = eq(_T_5357, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_5359 = and(ic_valid_ff, _T_5358) @[el2_ifu_mem_ctl.scala 741:64] + node _T_5360 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_5361 = and(_T_5359, _T_5360) @[el2_ifu_mem_ctl.scala 741:89] + node _T_5362 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_5363 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_5364 = and(_T_5362, _T_5363) @[el2_ifu_mem_ctl.scala 742:58] + node _T_5365 = eq(perr_ic_index_ff, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_5366 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_5367 = and(_T_5365, _T_5366) @[el2_ifu_mem_ctl.scala 742:123] + node _T_5368 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_5369 = and(_T_5367, _T_5368) @[el2_ifu_mem_ctl.scala 742:144] + node _T_5370 = or(_T_5364, _T_5369) @[el2_ifu_mem_ctl.scala 742:80] + node _T_5371 = bits(_T_5370, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_5372 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5371 : @[Reg.scala 28:19] _T_5372 <= _T_5361 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][10] <= _T_5372 @[el2_ifu_mem_ctl.scala 740:39] - node _T_5373 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_5374 = eq(_T_5373, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_5375 = and(ic_valid_ff, _T_5374) @[el2_ifu_mem_ctl.scala 740:64] - node _T_5376 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_5377 = and(_T_5375, _T_5376) @[el2_ifu_mem_ctl.scala 740:89] - node _T_5378 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_5379 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_5380 = and(_T_5378, _T_5379) @[el2_ifu_mem_ctl.scala 741:58] - node _T_5381 = eq(perr_ic_index_ff, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_5382 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_5383 = and(_T_5381, _T_5382) @[el2_ifu_mem_ctl.scala 741:123] - node _T_5384 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_5385 = and(_T_5383, _T_5384) @[el2_ifu_mem_ctl.scala 741:144] - node _T_5386 = or(_T_5380, _T_5385) @[el2_ifu_mem_ctl.scala 741:80] - node _T_5387 = bits(_T_5386, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][10] <= _T_5372 @[el2_ifu_mem_ctl.scala 741:39] + node _T_5373 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_5374 = eq(_T_5373, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_5375 = and(ic_valid_ff, _T_5374) @[el2_ifu_mem_ctl.scala 741:64] + node _T_5376 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_5377 = and(_T_5375, _T_5376) @[el2_ifu_mem_ctl.scala 741:89] + node _T_5378 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_5379 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_5380 = and(_T_5378, _T_5379) @[el2_ifu_mem_ctl.scala 742:58] + node _T_5381 = eq(perr_ic_index_ff, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_5382 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_5383 = and(_T_5381, _T_5382) @[el2_ifu_mem_ctl.scala 742:123] + node _T_5384 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_5385 = and(_T_5383, _T_5384) @[el2_ifu_mem_ctl.scala 742:144] + node _T_5386 = or(_T_5380, _T_5385) @[el2_ifu_mem_ctl.scala 742:80] + node _T_5387 = bits(_T_5386, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_5388 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5387 : @[Reg.scala 28:19] _T_5388 <= _T_5377 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][11] <= _T_5388 @[el2_ifu_mem_ctl.scala 740:39] - node _T_5389 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_5390 = eq(_T_5389, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_5391 = and(ic_valid_ff, _T_5390) @[el2_ifu_mem_ctl.scala 740:64] - node _T_5392 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_5393 = and(_T_5391, _T_5392) @[el2_ifu_mem_ctl.scala 740:89] - node _T_5394 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_5395 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_5396 = and(_T_5394, _T_5395) @[el2_ifu_mem_ctl.scala 741:58] - node _T_5397 = eq(perr_ic_index_ff, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_5398 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_5399 = and(_T_5397, _T_5398) @[el2_ifu_mem_ctl.scala 741:123] - node _T_5400 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_5401 = and(_T_5399, _T_5400) @[el2_ifu_mem_ctl.scala 741:144] - node _T_5402 = or(_T_5396, _T_5401) @[el2_ifu_mem_ctl.scala 741:80] - node _T_5403 = bits(_T_5402, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][11] <= _T_5388 @[el2_ifu_mem_ctl.scala 741:39] + node _T_5389 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_5390 = eq(_T_5389, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_5391 = and(ic_valid_ff, _T_5390) @[el2_ifu_mem_ctl.scala 741:64] + node _T_5392 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_5393 = and(_T_5391, _T_5392) @[el2_ifu_mem_ctl.scala 741:89] + node _T_5394 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_5395 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_5396 = and(_T_5394, _T_5395) @[el2_ifu_mem_ctl.scala 742:58] + node _T_5397 = eq(perr_ic_index_ff, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_5398 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_5399 = and(_T_5397, _T_5398) @[el2_ifu_mem_ctl.scala 742:123] + node _T_5400 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_5401 = and(_T_5399, _T_5400) @[el2_ifu_mem_ctl.scala 742:144] + node _T_5402 = or(_T_5396, _T_5401) @[el2_ifu_mem_ctl.scala 742:80] + node _T_5403 = bits(_T_5402, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_5404 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5403 : @[Reg.scala 28:19] _T_5404 <= _T_5393 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][12] <= _T_5404 @[el2_ifu_mem_ctl.scala 740:39] - node _T_5405 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_5406 = eq(_T_5405, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_5407 = and(ic_valid_ff, _T_5406) @[el2_ifu_mem_ctl.scala 740:64] - node _T_5408 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_5409 = and(_T_5407, _T_5408) @[el2_ifu_mem_ctl.scala 740:89] - node _T_5410 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_5411 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_5412 = and(_T_5410, _T_5411) @[el2_ifu_mem_ctl.scala 741:58] - node _T_5413 = eq(perr_ic_index_ff, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_5414 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_5415 = and(_T_5413, _T_5414) @[el2_ifu_mem_ctl.scala 741:123] - node _T_5416 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_5417 = and(_T_5415, _T_5416) @[el2_ifu_mem_ctl.scala 741:144] - node _T_5418 = or(_T_5412, _T_5417) @[el2_ifu_mem_ctl.scala 741:80] - node _T_5419 = bits(_T_5418, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][12] <= _T_5404 @[el2_ifu_mem_ctl.scala 741:39] + node _T_5405 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_5406 = eq(_T_5405, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_5407 = and(ic_valid_ff, _T_5406) @[el2_ifu_mem_ctl.scala 741:64] + node _T_5408 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_5409 = and(_T_5407, _T_5408) @[el2_ifu_mem_ctl.scala 741:89] + node _T_5410 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_5411 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_5412 = and(_T_5410, _T_5411) @[el2_ifu_mem_ctl.scala 742:58] + node _T_5413 = eq(perr_ic_index_ff, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_5414 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_5415 = and(_T_5413, _T_5414) @[el2_ifu_mem_ctl.scala 742:123] + node _T_5416 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_5417 = and(_T_5415, _T_5416) @[el2_ifu_mem_ctl.scala 742:144] + node _T_5418 = or(_T_5412, _T_5417) @[el2_ifu_mem_ctl.scala 742:80] + node _T_5419 = bits(_T_5418, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_5420 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5419 : @[Reg.scala 28:19] _T_5420 <= _T_5409 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][13] <= _T_5420 @[el2_ifu_mem_ctl.scala 740:39] - node _T_5421 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_5422 = eq(_T_5421, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_5423 = and(ic_valid_ff, _T_5422) @[el2_ifu_mem_ctl.scala 740:64] - node _T_5424 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_5425 = and(_T_5423, _T_5424) @[el2_ifu_mem_ctl.scala 740:89] - node _T_5426 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_5427 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_5428 = and(_T_5426, _T_5427) @[el2_ifu_mem_ctl.scala 741:58] - node _T_5429 = eq(perr_ic_index_ff, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_5430 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_5431 = and(_T_5429, _T_5430) @[el2_ifu_mem_ctl.scala 741:123] - node _T_5432 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_5433 = and(_T_5431, _T_5432) @[el2_ifu_mem_ctl.scala 741:144] - node _T_5434 = or(_T_5428, _T_5433) @[el2_ifu_mem_ctl.scala 741:80] - node _T_5435 = bits(_T_5434, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][13] <= _T_5420 @[el2_ifu_mem_ctl.scala 741:39] + node _T_5421 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_5422 = eq(_T_5421, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_5423 = and(ic_valid_ff, _T_5422) @[el2_ifu_mem_ctl.scala 741:64] + node _T_5424 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_5425 = and(_T_5423, _T_5424) @[el2_ifu_mem_ctl.scala 741:89] + node _T_5426 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_5427 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_5428 = and(_T_5426, _T_5427) @[el2_ifu_mem_ctl.scala 742:58] + node _T_5429 = eq(perr_ic_index_ff, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_5430 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_5431 = and(_T_5429, _T_5430) @[el2_ifu_mem_ctl.scala 742:123] + node _T_5432 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_5433 = and(_T_5431, _T_5432) @[el2_ifu_mem_ctl.scala 742:144] + node _T_5434 = or(_T_5428, _T_5433) @[el2_ifu_mem_ctl.scala 742:80] + node _T_5435 = bits(_T_5434, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_5436 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5435 : @[Reg.scala 28:19] _T_5436 <= _T_5425 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][14] <= _T_5436 @[el2_ifu_mem_ctl.scala 740:39] - node _T_5437 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_5438 = eq(_T_5437, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_5439 = and(ic_valid_ff, _T_5438) @[el2_ifu_mem_ctl.scala 740:64] - node _T_5440 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_5441 = and(_T_5439, _T_5440) @[el2_ifu_mem_ctl.scala 740:89] - node _T_5442 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_5443 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_5444 = and(_T_5442, _T_5443) @[el2_ifu_mem_ctl.scala 741:58] - node _T_5445 = eq(perr_ic_index_ff, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_5446 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_5447 = and(_T_5445, _T_5446) @[el2_ifu_mem_ctl.scala 741:123] - node _T_5448 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_5449 = and(_T_5447, _T_5448) @[el2_ifu_mem_ctl.scala 741:144] - node _T_5450 = or(_T_5444, _T_5449) @[el2_ifu_mem_ctl.scala 741:80] - node _T_5451 = bits(_T_5450, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][14] <= _T_5436 @[el2_ifu_mem_ctl.scala 741:39] + node _T_5437 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_5438 = eq(_T_5437, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_5439 = and(ic_valid_ff, _T_5438) @[el2_ifu_mem_ctl.scala 741:64] + node _T_5440 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_5441 = and(_T_5439, _T_5440) @[el2_ifu_mem_ctl.scala 741:89] + node _T_5442 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_5443 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_5444 = and(_T_5442, _T_5443) @[el2_ifu_mem_ctl.scala 742:58] + node _T_5445 = eq(perr_ic_index_ff, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_5446 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_5447 = and(_T_5445, _T_5446) @[el2_ifu_mem_ctl.scala 742:123] + node _T_5448 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_5449 = and(_T_5447, _T_5448) @[el2_ifu_mem_ctl.scala 742:144] + node _T_5450 = or(_T_5444, _T_5449) @[el2_ifu_mem_ctl.scala 742:80] + node _T_5451 = bits(_T_5450, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_5452 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5451 : @[Reg.scala 28:19] _T_5452 <= _T_5441 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][15] <= _T_5452 @[el2_ifu_mem_ctl.scala 740:39] - node _T_5453 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_5454 = eq(_T_5453, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_5455 = and(ic_valid_ff, _T_5454) @[el2_ifu_mem_ctl.scala 740:64] - node _T_5456 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_5457 = and(_T_5455, _T_5456) @[el2_ifu_mem_ctl.scala 740:89] - node _T_5458 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h010")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_5459 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_5460 = and(_T_5458, _T_5459) @[el2_ifu_mem_ctl.scala 741:58] - node _T_5461 = eq(perr_ic_index_ff, UInt<5>("h010")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_5462 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_5463 = and(_T_5461, _T_5462) @[el2_ifu_mem_ctl.scala 741:123] - node _T_5464 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_5465 = and(_T_5463, _T_5464) @[el2_ifu_mem_ctl.scala 741:144] - node _T_5466 = or(_T_5460, _T_5465) @[el2_ifu_mem_ctl.scala 741:80] - node _T_5467 = bits(_T_5466, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][15] <= _T_5452 @[el2_ifu_mem_ctl.scala 741:39] + node _T_5453 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_5454 = eq(_T_5453, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_5455 = and(ic_valid_ff, _T_5454) @[el2_ifu_mem_ctl.scala 741:64] + node _T_5456 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_5457 = and(_T_5455, _T_5456) @[el2_ifu_mem_ctl.scala 741:89] + node _T_5458 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h010")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_5459 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_5460 = and(_T_5458, _T_5459) @[el2_ifu_mem_ctl.scala 742:58] + node _T_5461 = eq(perr_ic_index_ff, UInt<5>("h010")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_5462 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_5463 = and(_T_5461, _T_5462) @[el2_ifu_mem_ctl.scala 742:123] + node _T_5464 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_5465 = and(_T_5463, _T_5464) @[el2_ifu_mem_ctl.scala 742:144] + node _T_5466 = or(_T_5460, _T_5465) @[el2_ifu_mem_ctl.scala 742:80] + node _T_5467 = bits(_T_5466, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_5468 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5467 : @[Reg.scala 28:19] _T_5468 <= _T_5457 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][16] <= _T_5468 @[el2_ifu_mem_ctl.scala 740:39] - node _T_5469 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_5470 = eq(_T_5469, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_5471 = and(ic_valid_ff, _T_5470) @[el2_ifu_mem_ctl.scala 740:64] - node _T_5472 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_5473 = and(_T_5471, _T_5472) @[el2_ifu_mem_ctl.scala 740:89] - node _T_5474 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h011")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_5475 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_5476 = and(_T_5474, _T_5475) @[el2_ifu_mem_ctl.scala 741:58] - node _T_5477 = eq(perr_ic_index_ff, UInt<5>("h011")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_5478 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_5479 = and(_T_5477, _T_5478) @[el2_ifu_mem_ctl.scala 741:123] - node _T_5480 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_5481 = and(_T_5479, _T_5480) @[el2_ifu_mem_ctl.scala 741:144] - node _T_5482 = or(_T_5476, _T_5481) @[el2_ifu_mem_ctl.scala 741:80] - node _T_5483 = bits(_T_5482, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][16] <= _T_5468 @[el2_ifu_mem_ctl.scala 741:39] + node _T_5469 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_5470 = eq(_T_5469, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_5471 = and(ic_valid_ff, _T_5470) @[el2_ifu_mem_ctl.scala 741:64] + node _T_5472 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_5473 = and(_T_5471, _T_5472) @[el2_ifu_mem_ctl.scala 741:89] + node _T_5474 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h011")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_5475 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_5476 = and(_T_5474, _T_5475) @[el2_ifu_mem_ctl.scala 742:58] + node _T_5477 = eq(perr_ic_index_ff, UInt<5>("h011")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_5478 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_5479 = and(_T_5477, _T_5478) @[el2_ifu_mem_ctl.scala 742:123] + node _T_5480 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_5481 = and(_T_5479, _T_5480) @[el2_ifu_mem_ctl.scala 742:144] + node _T_5482 = or(_T_5476, _T_5481) @[el2_ifu_mem_ctl.scala 742:80] + node _T_5483 = bits(_T_5482, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_5484 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5483 : @[Reg.scala 28:19] _T_5484 <= _T_5473 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][17] <= _T_5484 @[el2_ifu_mem_ctl.scala 740:39] - node _T_5485 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_5486 = eq(_T_5485, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_5487 = and(ic_valid_ff, _T_5486) @[el2_ifu_mem_ctl.scala 740:64] - node _T_5488 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_5489 = and(_T_5487, _T_5488) @[el2_ifu_mem_ctl.scala 740:89] - node _T_5490 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h012")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_5491 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_5492 = and(_T_5490, _T_5491) @[el2_ifu_mem_ctl.scala 741:58] - node _T_5493 = eq(perr_ic_index_ff, UInt<5>("h012")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_5494 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_5495 = and(_T_5493, _T_5494) @[el2_ifu_mem_ctl.scala 741:123] - node _T_5496 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_5497 = and(_T_5495, _T_5496) @[el2_ifu_mem_ctl.scala 741:144] - node _T_5498 = or(_T_5492, _T_5497) @[el2_ifu_mem_ctl.scala 741:80] - node _T_5499 = bits(_T_5498, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][17] <= _T_5484 @[el2_ifu_mem_ctl.scala 741:39] + node _T_5485 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_5486 = eq(_T_5485, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_5487 = and(ic_valid_ff, _T_5486) @[el2_ifu_mem_ctl.scala 741:64] + node _T_5488 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_5489 = and(_T_5487, _T_5488) @[el2_ifu_mem_ctl.scala 741:89] + node _T_5490 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h012")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_5491 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_5492 = and(_T_5490, _T_5491) @[el2_ifu_mem_ctl.scala 742:58] + node _T_5493 = eq(perr_ic_index_ff, UInt<5>("h012")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_5494 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_5495 = and(_T_5493, _T_5494) @[el2_ifu_mem_ctl.scala 742:123] + node _T_5496 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_5497 = and(_T_5495, _T_5496) @[el2_ifu_mem_ctl.scala 742:144] + node _T_5498 = or(_T_5492, _T_5497) @[el2_ifu_mem_ctl.scala 742:80] + node _T_5499 = bits(_T_5498, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_5500 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5499 : @[Reg.scala 28:19] _T_5500 <= _T_5489 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][18] <= _T_5500 @[el2_ifu_mem_ctl.scala 740:39] - node _T_5501 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_5502 = eq(_T_5501, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_5503 = and(ic_valid_ff, _T_5502) @[el2_ifu_mem_ctl.scala 740:64] - node _T_5504 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_5505 = and(_T_5503, _T_5504) @[el2_ifu_mem_ctl.scala 740:89] - node _T_5506 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h013")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_5507 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_5508 = and(_T_5506, _T_5507) @[el2_ifu_mem_ctl.scala 741:58] - node _T_5509 = eq(perr_ic_index_ff, UInt<5>("h013")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_5510 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_5511 = and(_T_5509, _T_5510) @[el2_ifu_mem_ctl.scala 741:123] - node _T_5512 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_5513 = and(_T_5511, _T_5512) @[el2_ifu_mem_ctl.scala 741:144] - node _T_5514 = or(_T_5508, _T_5513) @[el2_ifu_mem_ctl.scala 741:80] - node _T_5515 = bits(_T_5514, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][18] <= _T_5500 @[el2_ifu_mem_ctl.scala 741:39] + node _T_5501 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_5502 = eq(_T_5501, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_5503 = and(ic_valid_ff, _T_5502) @[el2_ifu_mem_ctl.scala 741:64] + node _T_5504 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_5505 = and(_T_5503, _T_5504) @[el2_ifu_mem_ctl.scala 741:89] + node _T_5506 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h013")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_5507 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_5508 = and(_T_5506, _T_5507) @[el2_ifu_mem_ctl.scala 742:58] + node _T_5509 = eq(perr_ic_index_ff, UInt<5>("h013")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_5510 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_5511 = and(_T_5509, _T_5510) @[el2_ifu_mem_ctl.scala 742:123] + node _T_5512 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_5513 = and(_T_5511, _T_5512) @[el2_ifu_mem_ctl.scala 742:144] + node _T_5514 = or(_T_5508, _T_5513) @[el2_ifu_mem_ctl.scala 742:80] + node _T_5515 = bits(_T_5514, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_5516 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5515 : @[Reg.scala 28:19] _T_5516 <= _T_5505 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][19] <= _T_5516 @[el2_ifu_mem_ctl.scala 740:39] - node _T_5517 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_5518 = eq(_T_5517, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_5519 = and(ic_valid_ff, _T_5518) @[el2_ifu_mem_ctl.scala 740:64] - node _T_5520 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_5521 = and(_T_5519, _T_5520) @[el2_ifu_mem_ctl.scala 740:89] - node _T_5522 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h014")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_5523 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_5524 = and(_T_5522, _T_5523) @[el2_ifu_mem_ctl.scala 741:58] - node _T_5525 = eq(perr_ic_index_ff, UInt<5>("h014")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_5526 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_5527 = and(_T_5525, _T_5526) @[el2_ifu_mem_ctl.scala 741:123] - node _T_5528 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_5529 = and(_T_5527, _T_5528) @[el2_ifu_mem_ctl.scala 741:144] - node _T_5530 = or(_T_5524, _T_5529) @[el2_ifu_mem_ctl.scala 741:80] - node _T_5531 = bits(_T_5530, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][19] <= _T_5516 @[el2_ifu_mem_ctl.scala 741:39] + node _T_5517 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_5518 = eq(_T_5517, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_5519 = and(ic_valid_ff, _T_5518) @[el2_ifu_mem_ctl.scala 741:64] + node _T_5520 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_5521 = and(_T_5519, _T_5520) @[el2_ifu_mem_ctl.scala 741:89] + node _T_5522 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h014")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_5523 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_5524 = and(_T_5522, _T_5523) @[el2_ifu_mem_ctl.scala 742:58] + node _T_5525 = eq(perr_ic_index_ff, UInt<5>("h014")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_5526 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_5527 = and(_T_5525, _T_5526) @[el2_ifu_mem_ctl.scala 742:123] + node _T_5528 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_5529 = and(_T_5527, _T_5528) @[el2_ifu_mem_ctl.scala 742:144] + node _T_5530 = or(_T_5524, _T_5529) @[el2_ifu_mem_ctl.scala 742:80] + node _T_5531 = bits(_T_5530, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_5532 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5531 : @[Reg.scala 28:19] _T_5532 <= _T_5521 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][20] <= _T_5532 @[el2_ifu_mem_ctl.scala 740:39] - node _T_5533 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_5534 = eq(_T_5533, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_5535 = and(ic_valid_ff, _T_5534) @[el2_ifu_mem_ctl.scala 740:64] - node _T_5536 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_5537 = and(_T_5535, _T_5536) @[el2_ifu_mem_ctl.scala 740:89] - node _T_5538 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h015")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_5539 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_5540 = and(_T_5538, _T_5539) @[el2_ifu_mem_ctl.scala 741:58] - node _T_5541 = eq(perr_ic_index_ff, UInt<5>("h015")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_5542 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_5543 = and(_T_5541, _T_5542) @[el2_ifu_mem_ctl.scala 741:123] - node _T_5544 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_5545 = and(_T_5543, _T_5544) @[el2_ifu_mem_ctl.scala 741:144] - node _T_5546 = or(_T_5540, _T_5545) @[el2_ifu_mem_ctl.scala 741:80] - node _T_5547 = bits(_T_5546, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][20] <= _T_5532 @[el2_ifu_mem_ctl.scala 741:39] + node _T_5533 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_5534 = eq(_T_5533, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_5535 = and(ic_valid_ff, _T_5534) @[el2_ifu_mem_ctl.scala 741:64] + node _T_5536 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_5537 = and(_T_5535, _T_5536) @[el2_ifu_mem_ctl.scala 741:89] + node _T_5538 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h015")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_5539 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_5540 = and(_T_5538, _T_5539) @[el2_ifu_mem_ctl.scala 742:58] + node _T_5541 = eq(perr_ic_index_ff, UInt<5>("h015")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_5542 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_5543 = and(_T_5541, _T_5542) @[el2_ifu_mem_ctl.scala 742:123] + node _T_5544 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_5545 = and(_T_5543, _T_5544) @[el2_ifu_mem_ctl.scala 742:144] + node _T_5546 = or(_T_5540, _T_5545) @[el2_ifu_mem_ctl.scala 742:80] + node _T_5547 = bits(_T_5546, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_5548 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5547 : @[Reg.scala 28:19] _T_5548 <= _T_5537 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][21] <= _T_5548 @[el2_ifu_mem_ctl.scala 740:39] - node _T_5549 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_5550 = eq(_T_5549, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_5551 = and(ic_valid_ff, _T_5550) @[el2_ifu_mem_ctl.scala 740:64] - node _T_5552 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_5553 = and(_T_5551, _T_5552) @[el2_ifu_mem_ctl.scala 740:89] - node _T_5554 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h016")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_5555 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_5556 = and(_T_5554, _T_5555) @[el2_ifu_mem_ctl.scala 741:58] - node _T_5557 = eq(perr_ic_index_ff, UInt<5>("h016")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_5558 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_5559 = and(_T_5557, _T_5558) @[el2_ifu_mem_ctl.scala 741:123] - node _T_5560 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_5561 = and(_T_5559, _T_5560) @[el2_ifu_mem_ctl.scala 741:144] - node _T_5562 = or(_T_5556, _T_5561) @[el2_ifu_mem_ctl.scala 741:80] - node _T_5563 = bits(_T_5562, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][21] <= _T_5548 @[el2_ifu_mem_ctl.scala 741:39] + node _T_5549 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_5550 = eq(_T_5549, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_5551 = and(ic_valid_ff, _T_5550) @[el2_ifu_mem_ctl.scala 741:64] + node _T_5552 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_5553 = and(_T_5551, _T_5552) @[el2_ifu_mem_ctl.scala 741:89] + node _T_5554 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h016")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_5555 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_5556 = and(_T_5554, _T_5555) @[el2_ifu_mem_ctl.scala 742:58] + node _T_5557 = eq(perr_ic_index_ff, UInt<5>("h016")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_5558 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_5559 = and(_T_5557, _T_5558) @[el2_ifu_mem_ctl.scala 742:123] + node _T_5560 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_5561 = and(_T_5559, _T_5560) @[el2_ifu_mem_ctl.scala 742:144] + node _T_5562 = or(_T_5556, _T_5561) @[el2_ifu_mem_ctl.scala 742:80] + node _T_5563 = bits(_T_5562, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_5564 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5563 : @[Reg.scala 28:19] _T_5564 <= _T_5553 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][22] <= _T_5564 @[el2_ifu_mem_ctl.scala 740:39] - node _T_5565 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_5566 = eq(_T_5565, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_5567 = and(ic_valid_ff, _T_5566) @[el2_ifu_mem_ctl.scala 740:64] - node _T_5568 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_5569 = and(_T_5567, _T_5568) @[el2_ifu_mem_ctl.scala 740:89] - node _T_5570 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h017")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_5571 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_5572 = and(_T_5570, _T_5571) @[el2_ifu_mem_ctl.scala 741:58] - node _T_5573 = eq(perr_ic_index_ff, UInt<5>("h017")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_5574 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_5575 = and(_T_5573, _T_5574) @[el2_ifu_mem_ctl.scala 741:123] - node _T_5576 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_5577 = and(_T_5575, _T_5576) @[el2_ifu_mem_ctl.scala 741:144] - node _T_5578 = or(_T_5572, _T_5577) @[el2_ifu_mem_ctl.scala 741:80] - node _T_5579 = bits(_T_5578, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][22] <= _T_5564 @[el2_ifu_mem_ctl.scala 741:39] + node _T_5565 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_5566 = eq(_T_5565, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_5567 = and(ic_valid_ff, _T_5566) @[el2_ifu_mem_ctl.scala 741:64] + node _T_5568 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_5569 = and(_T_5567, _T_5568) @[el2_ifu_mem_ctl.scala 741:89] + node _T_5570 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h017")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_5571 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_5572 = and(_T_5570, _T_5571) @[el2_ifu_mem_ctl.scala 742:58] + node _T_5573 = eq(perr_ic_index_ff, UInt<5>("h017")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_5574 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_5575 = and(_T_5573, _T_5574) @[el2_ifu_mem_ctl.scala 742:123] + node _T_5576 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_5577 = and(_T_5575, _T_5576) @[el2_ifu_mem_ctl.scala 742:144] + node _T_5578 = or(_T_5572, _T_5577) @[el2_ifu_mem_ctl.scala 742:80] + node _T_5579 = bits(_T_5578, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_5580 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5579 : @[Reg.scala 28:19] _T_5580 <= _T_5569 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][23] <= _T_5580 @[el2_ifu_mem_ctl.scala 740:39] - node _T_5581 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_5582 = eq(_T_5581, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_5583 = and(ic_valid_ff, _T_5582) @[el2_ifu_mem_ctl.scala 740:64] - node _T_5584 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_5585 = and(_T_5583, _T_5584) @[el2_ifu_mem_ctl.scala 740:89] - node _T_5586 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h018")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_5587 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_5588 = and(_T_5586, _T_5587) @[el2_ifu_mem_ctl.scala 741:58] - node _T_5589 = eq(perr_ic_index_ff, UInt<5>("h018")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_5590 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_5591 = and(_T_5589, _T_5590) @[el2_ifu_mem_ctl.scala 741:123] - node _T_5592 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_5593 = and(_T_5591, _T_5592) @[el2_ifu_mem_ctl.scala 741:144] - node _T_5594 = or(_T_5588, _T_5593) @[el2_ifu_mem_ctl.scala 741:80] - node _T_5595 = bits(_T_5594, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][23] <= _T_5580 @[el2_ifu_mem_ctl.scala 741:39] + node _T_5581 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_5582 = eq(_T_5581, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_5583 = and(ic_valid_ff, _T_5582) @[el2_ifu_mem_ctl.scala 741:64] + node _T_5584 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_5585 = and(_T_5583, _T_5584) @[el2_ifu_mem_ctl.scala 741:89] + node _T_5586 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h018")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_5587 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_5588 = and(_T_5586, _T_5587) @[el2_ifu_mem_ctl.scala 742:58] + node _T_5589 = eq(perr_ic_index_ff, UInt<5>("h018")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_5590 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_5591 = and(_T_5589, _T_5590) @[el2_ifu_mem_ctl.scala 742:123] + node _T_5592 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_5593 = and(_T_5591, _T_5592) @[el2_ifu_mem_ctl.scala 742:144] + node _T_5594 = or(_T_5588, _T_5593) @[el2_ifu_mem_ctl.scala 742:80] + node _T_5595 = bits(_T_5594, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_5596 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5595 : @[Reg.scala 28:19] _T_5596 <= _T_5585 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][24] <= _T_5596 @[el2_ifu_mem_ctl.scala 740:39] - node _T_5597 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_5598 = eq(_T_5597, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_5599 = and(ic_valid_ff, _T_5598) @[el2_ifu_mem_ctl.scala 740:64] - node _T_5600 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_5601 = and(_T_5599, _T_5600) @[el2_ifu_mem_ctl.scala 740:89] - node _T_5602 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h019")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_5603 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_5604 = and(_T_5602, _T_5603) @[el2_ifu_mem_ctl.scala 741:58] - node _T_5605 = eq(perr_ic_index_ff, UInt<5>("h019")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_5606 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_5607 = and(_T_5605, _T_5606) @[el2_ifu_mem_ctl.scala 741:123] - node _T_5608 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_5609 = and(_T_5607, _T_5608) @[el2_ifu_mem_ctl.scala 741:144] - node _T_5610 = or(_T_5604, _T_5609) @[el2_ifu_mem_ctl.scala 741:80] - node _T_5611 = bits(_T_5610, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][24] <= _T_5596 @[el2_ifu_mem_ctl.scala 741:39] + node _T_5597 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_5598 = eq(_T_5597, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_5599 = and(ic_valid_ff, _T_5598) @[el2_ifu_mem_ctl.scala 741:64] + node _T_5600 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_5601 = and(_T_5599, _T_5600) @[el2_ifu_mem_ctl.scala 741:89] + node _T_5602 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h019")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_5603 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_5604 = and(_T_5602, _T_5603) @[el2_ifu_mem_ctl.scala 742:58] + node _T_5605 = eq(perr_ic_index_ff, UInt<5>("h019")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_5606 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_5607 = and(_T_5605, _T_5606) @[el2_ifu_mem_ctl.scala 742:123] + node _T_5608 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_5609 = and(_T_5607, _T_5608) @[el2_ifu_mem_ctl.scala 742:144] + node _T_5610 = or(_T_5604, _T_5609) @[el2_ifu_mem_ctl.scala 742:80] + node _T_5611 = bits(_T_5610, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_5612 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5611 : @[Reg.scala 28:19] _T_5612 <= _T_5601 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][25] <= _T_5612 @[el2_ifu_mem_ctl.scala 740:39] - node _T_5613 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_5614 = eq(_T_5613, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_5615 = and(ic_valid_ff, _T_5614) @[el2_ifu_mem_ctl.scala 740:64] - node _T_5616 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_5617 = and(_T_5615, _T_5616) @[el2_ifu_mem_ctl.scala 740:89] - node _T_5618 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01a")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_5619 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_5620 = and(_T_5618, _T_5619) @[el2_ifu_mem_ctl.scala 741:58] - node _T_5621 = eq(perr_ic_index_ff, UInt<5>("h01a")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_5622 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_5623 = and(_T_5621, _T_5622) @[el2_ifu_mem_ctl.scala 741:123] - node _T_5624 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_5625 = and(_T_5623, _T_5624) @[el2_ifu_mem_ctl.scala 741:144] - node _T_5626 = or(_T_5620, _T_5625) @[el2_ifu_mem_ctl.scala 741:80] - node _T_5627 = bits(_T_5626, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][25] <= _T_5612 @[el2_ifu_mem_ctl.scala 741:39] + node _T_5613 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_5614 = eq(_T_5613, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_5615 = and(ic_valid_ff, _T_5614) @[el2_ifu_mem_ctl.scala 741:64] + node _T_5616 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_5617 = and(_T_5615, _T_5616) @[el2_ifu_mem_ctl.scala 741:89] + node _T_5618 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01a")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_5619 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_5620 = and(_T_5618, _T_5619) @[el2_ifu_mem_ctl.scala 742:58] + node _T_5621 = eq(perr_ic_index_ff, UInt<5>("h01a")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_5622 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_5623 = and(_T_5621, _T_5622) @[el2_ifu_mem_ctl.scala 742:123] + node _T_5624 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_5625 = and(_T_5623, _T_5624) @[el2_ifu_mem_ctl.scala 742:144] + node _T_5626 = or(_T_5620, _T_5625) @[el2_ifu_mem_ctl.scala 742:80] + node _T_5627 = bits(_T_5626, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_5628 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5627 : @[Reg.scala 28:19] _T_5628 <= _T_5617 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][26] <= _T_5628 @[el2_ifu_mem_ctl.scala 740:39] - node _T_5629 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_5630 = eq(_T_5629, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_5631 = and(ic_valid_ff, _T_5630) @[el2_ifu_mem_ctl.scala 740:64] - node _T_5632 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_5633 = and(_T_5631, _T_5632) @[el2_ifu_mem_ctl.scala 740:89] - node _T_5634 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01b")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_5635 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_5636 = and(_T_5634, _T_5635) @[el2_ifu_mem_ctl.scala 741:58] - node _T_5637 = eq(perr_ic_index_ff, UInt<5>("h01b")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_5638 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_5639 = and(_T_5637, _T_5638) @[el2_ifu_mem_ctl.scala 741:123] - node _T_5640 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_5641 = and(_T_5639, _T_5640) @[el2_ifu_mem_ctl.scala 741:144] - node _T_5642 = or(_T_5636, _T_5641) @[el2_ifu_mem_ctl.scala 741:80] - node _T_5643 = bits(_T_5642, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][26] <= _T_5628 @[el2_ifu_mem_ctl.scala 741:39] + node _T_5629 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_5630 = eq(_T_5629, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_5631 = and(ic_valid_ff, _T_5630) @[el2_ifu_mem_ctl.scala 741:64] + node _T_5632 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_5633 = and(_T_5631, _T_5632) @[el2_ifu_mem_ctl.scala 741:89] + node _T_5634 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01b")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_5635 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_5636 = and(_T_5634, _T_5635) @[el2_ifu_mem_ctl.scala 742:58] + node _T_5637 = eq(perr_ic_index_ff, UInt<5>("h01b")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_5638 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_5639 = and(_T_5637, _T_5638) @[el2_ifu_mem_ctl.scala 742:123] + node _T_5640 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_5641 = and(_T_5639, _T_5640) @[el2_ifu_mem_ctl.scala 742:144] + node _T_5642 = or(_T_5636, _T_5641) @[el2_ifu_mem_ctl.scala 742:80] + node _T_5643 = bits(_T_5642, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_5644 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5643 : @[Reg.scala 28:19] _T_5644 <= _T_5633 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][27] <= _T_5644 @[el2_ifu_mem_ctl.scala 740:39] - node _T_5645 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_5646 = eq(_T_5645, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_5647 = and(ic_valid_ff, _T_5646) @[el2_ifu_mem_ctl.scala 740:64] - node _T_5648 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_5649 = and(_T_5647, _T_5648) @[el2_ifu_mem_ctl.scala 740:89] - node _T_5650 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01c")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_5651 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_5652 = and(_T_5650, _T_5651) @[el2_ifu_mem_ctl.scala 741:58] - node _T_5653 = eq(perr_ic_index_ff, UInt<5>("h01c")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_5654 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_5655 = and(_T_5653, _T_5654) @[el2_ifu_mem_ctl.scala 741:123] - node _T_5656 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_5657 = and(_T_5655, _T_5656) @[el2_ifu_mem_ctl.scala 741:144] - node _T_5658 = or(_T_5652, _T_5657) @[el2_ifu_mem_ctl.scala 741:80] - node _T_5659 = bits(_T_5658, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][27] <= _T_5644 @[el2_ifu_mem_ctl.scala 741:39] + node _T_5645 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_5646 = eq(_T_5645, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_5647 = and(ic_valid_ff, _T_5646) @[el2_ifu_mem_ctl.scala 741:64] + node _T_5648 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_5649 = and(_T_5647, _T_5648) @[el2_ifu_mem_ctl.scala 741:89] + node _T_5650 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01c")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_5651 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_5652 = and(_T_5650, _T_5651) @[el2_ifu_mem_ctl.scala 742:58] + node _T_5653 = eq(perr_ic_index_ff, UInt<5>("h01c")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_5654 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_5655 = and(_T_5653, _T_5654) @[el2_ifu_mem_ctl.scala 742:123] + node _T_5656 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_5657 = and(_T_5655, _T_5656) @[el2_ifu_mem_ctl.scala 742:144] + node _T_5658 = or(_T_5652, _T_5657) @[el2_ifu_mem_ctl.scala 742:80] + node _T_5659 = bits(_T_5658, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_5660 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5659 : @[Reg.scala 28:19] _T_5660 <= _T_5649 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][28] <= _T_5660 @[el2_ifu_mem_ctl.scala 740:39] - node _T_5661 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_5662 = eq(_T_5661, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_5663 = and(ic_valid_ff, _T_5662) @[el2_ifu_mem_ctl.scala 740:64] - node _T_5664 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_5665 = and(_T_5663, _T_5664) @[el2_ifu_mem_ctl.scala 740:89] - node _T_5666 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01d")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_5667 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_5668 = and(_T_5666, _T_5667) @[el2_ifu_mem_ctl.scala 741:58] - node _T_5669 = eq(perr_ic_index_ff, UInt<5>("h01d")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_5670 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_5671 = and(_T_5669, _T_5670) @[el2_ifu_mem_ctl.scala 741:123] - node _T_5672 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_5673 = and(_T_5671, _T_5672) @[el2_ifu_mem_ctl.scala 741:144] - node _T_5674 = or(_T_5668, _T_5673) @[el2_ifu_mem_ctl.scala 741:80] - node _T_5675 = bits(_T_5674, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][28] <= _T_5660 @[el2_ifu_mem_ctl.scala 741:39] + node _T_5661 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_5662 = eq(_T_5661, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_5663 = and(ic_valid_ff, _T_5662) @[el2_ifu_mem_ctl.scala 741:64] + node _T_5664 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_5665 = and(_T_5663, _T_5664) @[el2_ifu_mem_ctl.scala 741:89] + node _T_5666 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01d")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_5667 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_5668 = and(_T_5666, _T_5667) @[el2_ifu_mem_ctl.scala 742:58] + node _T_5669 = eq(perr_ic_index_ff, UInt<5>("h01d")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_5670 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_5671 = and(_T_5669, _T_5670) @[el2_ifu_mem_ctl.scala 742:123] + node _T_5672 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_5673 = and(_T_5671, _T_5672) @[el2_ifu_mem_ctl.scala 742:144] + node _T_5674 = or(_T_5668, _T_5673) @[el2_ifu_mem_ctl.scala 742:80] + node _T_5675 = bits(_T_5674, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_5676 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5675 : @[Reg.scala 28:19] _T_5676 <= _T_5665 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][29] <= _T_5676 @[el2_ifu_mem_ctl.scala 740:39] - node _T_5677 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_5678 = eq(_T_5677, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_5679 = and(ic_valid_ff, _T_5678) @[el2_ifu_mem_ctl.scala 740:64] - node _T_5680 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_5681 = and(_T_5679, _T_5680) @[el2_ifu_mem_ctl.scala 740:89] - node _T_5682 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01e")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_5683 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_5684 = and(_T_5682, _T_5683) @[el2_ifu_mem_ctl.scala 741:58] - node _T_5685 = eq(perr_ic_index_ff, UInt<5>("h01e")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_5686 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_5687 = and(_T_5685, _T_5686) @[el2_ifu_mem_ctl.scala 741:123] - node _T_5688 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_5689 = and(_T_5687, _T_5688) @[el2_ifu_mem_ctl.scala 741:144] - node _T_5690 = or(_T_5684, _T_5689) @[el2_ifu_mem_ctl.scala 741:80] - node _T_5691 = bits(_T_5690, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][29] <= _T_5676 @[el2_ifu_mem_ctl.scala 741:39] + node _T_5677 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_5678 = eq(_T_5677, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_5679 = and(ic_valid_ff, _T_5678) @[el2_ifu_mem_ctl.scala 741:64] + node _T_5680 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_5681 = and(_T_5679, _T_5680) @[el2_ifu_mem_ctl.scala 741:89] + node _T_5682 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01e")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_5683 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_5684 = and(_T_5682, _T_5683) @[el2_ifu_mem_ctl.scala 742:58] + node _T_5685 = eq(perr_ic_index_ff, UInt<5>("h01e")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_5686 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_5687 = and(_T_5685, _T_5686) @[el2_ifu_mem_ctl.scala 742:123] + node _T_5688 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_5689 = and(_T_5687, _T_5688) @[el2_ifu_mem_ctl.scala 742:144] + node _T_5690 = or(_T_5684, _T_5689) @[el2_ifu_mem_ctl.scala 742:80] + node _T_5691 = bits(_T_5690, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_5692 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5691 : @[Reg.scala 28:19] _T_5692 <= _T_5681 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][30] <= _T_5692 @[el2_ifu_mem_ctl.scala 740:39] - node _T_5693 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_5694 = eq(_T_5693, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_5695 = and(ic_valid_ff, _T_5694) @[el2_ifu_mem_ctl.scala 740:64] - node _T_5696 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_5697 = and(_T_5695, _T_5696) @[el2_ifu_mem_ctl.scala 740:89] - node _T_5698 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01f")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_5699 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_5700 = and(_T_5698, _T_5699) @[el2_ifu_mem_ctl.scala 741:58] - node _T_5701 = eq(perr_ic_index_ff, UInt<5>("h01f")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_5702 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_5703 = and(_T_5701, _T_5702) @[el2_ifu_mem_ctl.scala 741:123] - node _T_5704 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_5705 = and(_T_5703, _T_5704) @[el2_ifu_mem_ctl.scala 741:144] - node _T_5706 = or(_T_5700, _T_5705) @[el2_ifu_mem_ctl.scala 741:80] - node _T_5707 = bits(_T_5706, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][30] <= _T_5692 @[el2_ifu_mem_ctl.scala 741:39] + node _T_5693 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_5694 = eq(_T_5693, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_5695 = and(ic_valid_ff, _T_5694) @[el2_ifu_mem_ctl.scala 741:64] + node _T_5696 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_5697 = and(_T_5695, _T_5696) @[el2_ifu_mem_ctl.scala 741:89] + node _T_5698 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01f")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_5699 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_5700 = and(_T_5698, _T_5699) @[el2_ifu_mem_ctl.scala 742:58] + node _T_5701 = eq(perr_ic_index_ff, UInt<5>("h01f")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_5702 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_5703 = and(_T_5701, _T_5702) @[el2_ifu_mem_ctl.scala 742:123] + node _T_5704 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_5705 = and(_T_5703, _T_5704) @[el2_ifu_mem_ctl.scala 742:144] + node _T_5706 = or(_T_5700, _T_5705) @[el2_ifu_mem_ctl.scala 742:80] + node _T_5707 = bits(_T_5706, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_5708 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5707 : @[Reg.scala 28:19] _T_5708 <= _T_5697 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][31] <= _T_5708 @[el2_ifu_mem_ctl.scala 740:39] - node _T_5709 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_5710 = eq(_T_5709, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_5711 = and(ic_valid_ff, _T_5710) @[el2_ifu_mem_ctl.scala 740:64] - node _T_5712 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_5713 = and(_T_5711, _T_5712) @[el2_ifu_mem_ctl.scala 740:89] - node _T_5714 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_5715 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_5716 = and(_T_5714, _T_5715) @[el2_ifu_mem_ctl.scala 741:58] - node _T_5717 = eq(perr_ic_index_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_5718 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_5719 = and(_T_5717, _T_5718) @[el2_ifu_mem_ctl.scala 741:123] - node _T_5720 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_5721 = and(_T_5719, _T_5720) @[el2_ifu_mem_ctl.scala 741:144] - node _T_5722 = or(_T_5716, _T_5721) @[el2_ifu_mem_ctl.scala 741:80] - node _T_5723 = bits(_T_5722, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][31] <= _T_5708 @[el2_ifu_mem_ctl.scala 741:39] + node _T_5709 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_5710 = eq(_T_5709, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_5711 = and(ic_valid_ff, _T_5710) @[el2_ifu_mem_ctl.scala 741:64] + node _T_5712 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_5713 = and(_T_5711, _T_5712) @[el2_ifu_mem_ctl.scala 741:89] + node _T_5714 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_5715 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_5716 = and(_T_5714, _T_5715) @[el2_ifu_mem_ctl.scala 742:58] + node _T_5717 = eq(perr_ic_index_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_5718 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_5719 = and(_T_5717, _T_5718) @[el2_ifu_mem_ctl.scala 742:123] + node _T_5720 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_5721 = and(_T_5719, _T_5720) @[el2_ifu_mem_ctl.scala 742:144] + node _T_5722 = or(_T_5716, _T_5721) @[el2_ifu_mem_ctl.scala 742:80] + node _T_5723 = bits(_T_5722, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_5724 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5723 : @[Reg.scala 28:19] _T_5724 <= _T_5713 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][0] <= _T_5724 @[el2_ifu_mem_ctl.scala 740:39] - node _T_5725 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_5726 = eq(_T_5725, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_5727 = and(ic_valid_ff, _T_5726) @[el2_ifu_mem_ctl.scala 740:64] - node _T_5728 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_5729 = and(_T_5727, _T_5728) @[el2_ifu_mem_ctl.scala 740:89] - node _T_5730 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_5731 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_5732 = and(_T_5730, _T_5731) @[el2_ifu_mem_ctl.scala 741:58] - node _T_5733 = eq(perr_ic_index_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_5734 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_5735 = and(_T_5733, _T_5734) @[el2_ifu_mem_ctl.scala 741:123] - node _T_5736 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_5737 = and(_T_5735, _T_5736) @[el2_ifu_mem_ctl.scala 741:144] - node _T_5738 = or(_T_5732, _T_5737) @[el2_ifu_mem_ctl.scala 741:80] - node _T_5739 = bits(_T_5738, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][0] <= _T_5724 @[el2_ifu_mem_ctl.scala 741:39] + node _T_5725 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_5726 = eq(_T_5725, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_5727 = and(ic_valid_ff, _T_5726) @[el2_ifu_mem_ctl.scala 741:64] + node _T_5728 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_5729 = and(_T_5727, _T_5728) @[el2_ifu_mem_ctl.scala 741:89] + node _T_5730 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_5731 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_5732 = and(_T_5730, _T_5731) @[el2_ifu_mem_ctl.scala 742:58] + node _T_5733 = eq(perr_ic_index_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_5734 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_5735 = and(_T_5733, _T_5734) @[el2_ifu_mem_ctl.scala 742:123] + node _T_5736 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_5737 = and(_T_5735, _T_5736) @[el2_ifu_mem_ctl.scala 742:144] + node _T_5738 = or(_T_5732, _T_5737) @[el2_ifu_mem_ctl.scala 742:80] + node _T_5739 = bits(_T_5738, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_5740 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5739 : @[Reg.scala 28:19] _T_5740 <= _T_5729 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][1] <= _T_5740 @[el2_ifu_mem_ctl.scala 740:39] - node _T_5741 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_5742 = eq(_T_5741, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_5743 = and(ic_valid_ff, _T_5742) @[el2_ifu_mem_ctl.scala 740:64] - node _T_5744 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_5745 = and(_T_5743, _T_5744) @[el2_ifu_mem_ctl.scala 740:89] - node _T_5746 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_5747 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_5748 = and(_T_5746, _T_5747) @[el2_ifu_mem_ctl.scala 741:58] - node _T_5749 = eq(perr_ic_index_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_5750 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_5751 = and(_T_5749, _T_5750) @[el2_ifu_mem_ctl.scala 741:123] - node _T_5752 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_5753 = and(_T_5751, _T_5752) @[el2_ifu_mem_ctl.scala 741:144] - node _T_5754 = or(_T_5748, _T_5753) @[el2_ifu_mem_ctl.scala 741:80] - node _T_5755 = bits(_T_5754, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][1] <= _T_5740 @[el2_ifu_mem_ctl.scala 741:39] + node _T_5741 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_5742 = eq(_T_5741, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_5743 = and(ic_valid_ff, _T_5742) @[el2_ifu_mem_ctl.scala 741:64] + node _T_5744 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_5745 = and(_T_5743, _T_5744) @[el2_ifu_mem_ctl.scala 741:89] + node _T_5746 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_5747 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_5748 = and(_T_5746, _T_5747) @[el2_ifu_mem_ctl.scala 742:58] + node _T_5749 = eq(perr_ic_index_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_5750 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_5751 = and(_T_5749, _T_5750) @[el2_ifu_mem_ctl.scala 742:123] + node _T_5752 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_5753 = and(_T_5751, _T_5752) @[el2_ifu_mem_ctl.scala 742:144] + node _T_5754 = or(_T_5748, _T_5753) @[el2_ifu_mem_ctl.scala 742:80] + node _T_5755 = bits(_T_5754, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_5756 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5755 : @[Reg.scala 28:19] _T_5756 <= _T_5745 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][2] <= _T_5756 @[el2_ifu_mem_ctl.scala 740:39] - node _T_5757 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_5758 = eq(_T_5757, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_5759 = and(ic_valid_ff, _T_5758) @[el2_ifu_mem_ctl.scala 740:64] - node _T_5760 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_5761 = and(_T_5759, _T_5760) @[el2_ifu_mem_ctl.scala 740:89] - node _T_5762 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_5763 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_5764 = and(_T_5762, _T_5763) @[el2_ifu_mem_ctl.scala 741:58] - node _T_5765 = eq(perr_ic_index_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_5766 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_5767 = and(_T_5765, _T_5766) @[el2_ifu_mem_ctl.scala 741:123] - node _T_5768 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_5769 = and(_T_5767, _T_5768) @[el2_ifu_mem_ctl.scala 741:144] - node _T_5770 = or(_T_5764, _T_5769) @[el2_ifu_mem_ctl.scala 741:80] - node _T_5771 = bits(_T_5770, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][2] <= _T_5756 @[el2_ifu_mem_ctl.scala 741:39] + node _T_5757 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_5758 = eq(_T_5757, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_5759 = and(ic_valid_ff, _T_5758) @[el2_ifu_mem_ctl.scala 741:64] + node _T_5760 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_5761 = and(_T_5759, _T_5760) @[el2_ifu_mem_ctl.scala 741:89] + node _T_5762 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_5763 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_5764 = and(_T_5762, _T_5763) @[el2_ifu_mem_ctl.scala 742:58] + node _T_5765 = eq(perr_ic_index_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_5766 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_5767 = and(_T_5765, _T_5766) @[el2_ifu_mem_ctl.scala 742:123] + node _T_5768 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_5769 = and(_T_5767, _T_5768) @[el2_ifu_mem_ctl.scala 742:144] + node _T_5770 = or(_T_5764, _T_5769) @[el2_ifu_mem_ctl.scala 742:80] + node _T_5771 = bits(_T_5770, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_5772 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5771 : @[Reg.scala 28:19] _T_5772 <= _T_5761 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][3] <= _T_5772 @[el2_ifu_mem_ctl.scala 740:39] - node _T_5773 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_5774 = eq(_T_5773, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_5775 = and(ic_valid_ff, _T_5774) @[el2_ifu_mem_ctl.scala 740:64] - node _T_5776 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_5777 = and(_T_5775, _T_5776) @[el2_ifu_mem_ctl.scala 740:89] - node _T_5778 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_5779 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_5780 = and(_T_5778, _T_5779) @[el2_ifu_mem_ctl.scala 741:58] - node _T_5781 = eq(perr_ic_index_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_5782 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_5783 = and(_T_5781, _T_5782) @[el2_ifu_mem_ctl.scala 741:123] - node _T_5784 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_5785 = and(_T_5783, _T_5784) @[el2_ifu_mem_ctl.scala 741:144] - node _T_5786 = or(_T_5780, _T_5785) @[el2_ifu_mem_ctl.scala 741:80] - node _T_5787 = bits(_T_5786, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][3] <= _T_5772 @[el2_ifu_mem_ctl.scala 741:39] + node _T_5773 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_5774 = eq(_T_5773, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_5775 = and(ic_valid_ff, _T_5774) @[el2_ifu_mem_ctl.scala 741:64] + node _T_5776 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_5777 = and(_T_5775, _T_5776) @[el2_ifu_mem_ctl.scala 741:89] + node _T_5778 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_5779 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_5780 = and(_T_5778, _T_5779) @[el2_ifu_mem_ctl.scala 742:58] + node _T_5781 = eq(perr_ic_index_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_5782 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_5783 = and(_T_5781, _T_5782) @[el2_ifu_mem_ctl.scala 742:123] + node _T_5784 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_5785 = and(_T_5783, _T_5784) @[el2_ifu_mem_ctl.scala 742:144] + node _T_5786 = or(_T_5780, _T_5785) @[el2_ifu_mem_ctl.scala 742:80] + node _T_5787 = bits(_T_5786, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_5788 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5787 : @[Reg.scala 28:19] _T_5788 <= _T_5777 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][4] <= _T_5788 @[el2_ifu_mem_ctl.scala 740:39] - node _T_5789 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_5790 = eq(_T_5789, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_5791 = and(ic_valid_ff, _T_5790) @[el2_ifu_mem_ctl.scala 740:64] - node _T_5792 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_5793 = and(_T_5791, _T_5792) @[el2_ifu_mem_ctl.scala 740:89] - node _T_5794 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_5795 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_5796 = and(_T_5794, _T_5795) @[el2_ifu_mem_ctl.scala 741:58] - node _T_5797 = eq(perr_ic_index_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_5798 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_5799 = and(_T_5797, _T_5798) @[el2_ifu_mem_ctl.scala 741:123] - node _T_5800 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_5801 = and(_T_5799, _T_5800) @[el2_ifu_mem_ctl.scala 741:144] - node _T_5802 = or(_T_5796, _T_5801) @[el2_ifu_mem_ctl.scala 741:80] - node _T_5803 = bits(_T_5802, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][4] <= _T_5788 @[el2_ifu_mem_ctl.scala 741:39] + node _T_5789 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_5790 = eq(_T_5789, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_5791 = and(ic_valid_ff, _T_5790) @[el2_ifu_mem_ctl.scala 741:64] + node _T_5792 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_5793 = and(_T_5791, _T_5792) @[el2_ifu_mem_ctl.scala 741:89] + node _T_5794 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_5795 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_5796 = and(_T_5794, _T_5795) @[el2_ifu_mem_ctl.scala 742:58] + node _T_5797 = eq(perr_ic_index_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_5798 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_5799 = and(_T_5797, _T_5798) @[el2_ifu_mem_ctl.scala 742:123] + node _T_5800 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_5801 = and(_T_5799, _T_5800) @[el2_ifu_mem_ctl.scala 742:144] + node _T_5802 = or(_T_5796, _T_5801) @[el2_ifu_mem_ctl.scala 742:80] + node _T_5803 = bits(_T_5802, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_5804 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5803 : @[Reg.scala 28:19] _T_5804 <= _T_5793 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][5] <= _T_5804 @[el2_ifu_mem_ctl.scala 740:39] - node _T_5805 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_5806 = eq(_T_5805, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_5807 = and(ic_valid_ff, _T_5806) @[el2_ifu_mem_ctl.scala 740:64] - node _T_5808 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_5809 = and(_T_5807, _T_5808) @[el2_ifu_mem_ctl.scala 740:89] - node _T_5810 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_5811 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_5812 = and(_T_5810, _T_5811) @[el2_ifu_mem_ctl.scala 741:58] - node _T_5813 = eq(perr_ic_index_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_5814 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_5815 = and(_T_5813, _T_5814) @[el2_ifu_mem_ctl.scala 741:123] - node _T_5816 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_5817 = and(_T_5815, _T_5816) @[el2_ifu_mem_ctl.scala 741:144] - node _T_5818 = or(_T_5812, _T_5817) @[el2_ifu_mem_ctl.scala 741:80] - node _T_5819 = bits(_T_5818, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][5] <= _T_5804 @[el2_ifu_mem_ctl.scala 741:39] + node _T_5805 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_5806 = eq(_T_5805, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_5807 = and(ic_valid_ff, _T_5806) @[el2_ifu_mem_ctl.scala 741:64] + node _T_5808 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_5809 = and(_T_5807, _T_5808) @[el2_ifu_mem_ctl.scala 741:89] + node _T_5810 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_5811 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_5812 = and(_T_5810, _T_5811) @[el2_ifu_mem_ctl.scala 742:58] + node _T_5813 = eq(perr_ic_index_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_5814 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_5815 = and(_T_5813, _T_5814) @[el2_ifu_mem_ctl.scala 742:123] + node _T_5816 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_5817 = and(_T_5815, _T_5816) @[el2_ifu_mem_ctl.scala 742:144] + node _T_5818 = or(_T_5812, _T_5817) @[el2_ifu_mem_ctl.scala 742:80] + node _T_5819 = bits(_T_5818, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_5820 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5819 : @[Reg.scala 28:19] _T_5820 <= _T_5809 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][6] <= _T_5820 @[el2_ifu_mem_ctl.scala 740:39] - node _T_5821 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_5822 = eq(_T_5821, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_5823 = and(ic_valid_ff, _T_5822) @[el2_ifu_mem_ctl.scala 740:64] - node _T_5824 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_5825 = and(_T_5823, _T_5824) @[el2_ifu_mem_ctl.scala 740:89] - node _T_5826 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_5827 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_5828 = and(_T_5826, _T_5827) @[el2_ifu_mem_ctl.scala 741:58] - node _T_5829 = eq(perr_ic_index_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_5830 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_5831 = and(_T_5829, _T_5830) @[el2_ifu_mem_ctl.scala 741:123] - node _T_5832 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_5833 = and(_T_5831, _T_5832) @[el2_ifu_mem_ctl.scala 741:144] - node _T_5834 = or(_T_5828, _T_5833) @[el2_ifu_mem_ctl.scala 741:80] - node _T_5835 = bits(_T_5834, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][6] <= _T_5820 @[el2_ifu_mem_ctl.scala 741:39] + node _T_5821 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_5822 = eq(_T_5821, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_5823 = and(ic_valid_ff, _T_5822) @[el2_ifu_mem_ctl.scala 741:64] + node _T_5824 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_5825 = and(_T_5823, _T_5824) @[el2_ifu_mem_ctl.scala 741:89] + node _T_5826 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_5827 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_5828 = and(_T_5826, _T_5827) @[el2_ifu_mem_ctl.scala 742:58] + node _T_5829 = eq(perr_ic_index_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_5830 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_5831 = and(_T_5829, _T_5830) @[el2_ifu_mem_ctl.scala 742:123] + node _T_5832 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_5833 = and(_T_5831, _T_5832) @[el2_ifu_mem_ctl.scala 742:144] + node _T_5834 = or(_T_5828, _T_5833) @[el2_ifu_mem_ctl.scala 742:80] + node _T_5835 = bits(_T_5834, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_5836 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5835 : @[Reg.scala 28:19] _T_5836 <= _T_5825 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][7] <= _T_5836 @[el2_ifu_mem_ctl.scala 740:39] - node _T_5837 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_5838 = eq(_T_5837, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_5839 = and(ic_valid_ff, _T_5838) @[el2_ifu_mem_ctl.scala 740:64] - node _T_5840 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_5841 = and(_T_5839, _T_5840) @[el2_ifu_mem_ctl.scala 740:89] - node _T_5842 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_5843 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_5844 = and(_T_5842, _T_5843) @[el2_ifu_mem_ctl.scala 741:58] - node _T_5845 = eq(perr_ic_index_ff, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_5846 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_5847 = and(_T_5845, _T_5846) @[el2_ifu_mem_ctl.scala 741:123] - node _T_5848 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_5849 = and(_T_5847, _T_5848) @[el2_ifu_mem_ctl.scala 741:144] - node _T_5850 = or(_T_5844, _T_5849) @[el2_ifu_mem_ctl.scala 741:80] - node _T_5851 = bits(_T_5850, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][7] <= _T_5836 @[el2_ifu_mem_ctl.scala 741:39] + node _T_5837 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_5838 = eq(_T_5837, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_5839 = and(ic_valid_ff, _T_5838) @[el2_ifu_mem_ctl.scala 741:64] + node _T_5840 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_5841 = and(_T_5839, _T_5840) @[el2_ifu_mem_ctl.scala 741:89] + node _T_5842 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_5843 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_5844 = and(_T_5842, _T_5843) @[el2_ifu_mem_ctl.scala 742:58] + node _T_5845 = eq(perr_ic_index_ff, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_5846 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_5847 = and(_T_5845, _T_5846) @[el2_ifu_mem_ctl.scala 742:123] + node _T_5848 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_5849 = and(_T_5847, _T_5848) @[el2_ifu_mem_ctl.scala 742:144] + node _T_5850 = or(_T_5844, _T_5849) @[el2_ifu_mem_ctl.scala 742:80] + node _T_5851 = bits(_T_5850, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_5852 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5851 : @[Reg.scala 28:19] _T_5852 <= _T_5841 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][8] <= _T_5852 @[el2_ifu_mem_ctl.scala 740:39] - node _T_5853 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_5854 = eq(_T_5853, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_5855 = and(ic_valid_ff, _T_5854) @[el2_ifu_mem_ctl.scala 740:64] - node _T_5856 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_5857 = and(_T_5855, _T_5856) @[el2_ifu_mem_ctl.scala 740:89] - node _T_5858 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_5859 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_5860 = and(_T_5858, _T_5859) @[el2_ifu_mem_ctl.scala 741:58] - node _T_5861 = eq(perr_ic_index_ff, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_5862 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_5863 = and(_T_5861, _T_5862) @[el2_ifu_mem_ctl.scala 741:123] - node _T_5864 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_5865 = and(_T_5863, _T_5864) @[el2_ifu_mem_ctl.scala 741:144] - node _T_5866 = or(_T_5860, _T_5865) @[el2_ifu_mem_ctl.scala 741:80] - node _T_5867 = bits(_T_5866, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][8] <= _T_5852 @[el2_ifu_mem_ctl.scala 741:39] + node _T_5853 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_5854 = eq(_T_5853, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_5855 = and(ic_valid_ff, _T_5854) @[el2_ifu_mem_ctl.scala 741:64] + node _T_5856 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_5857 = and(_T_5855, _T_5856) @[el2_ifu_mem_ctl.scala 741:89] + node _T_5858 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_5859 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_5860 = and(_T_5858, _T_5859) @[el2_ifu_mem_ctl.scala 742:58] + node _T_5861 = eq(perr_ic_index_ff, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_5862 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_5863 = and(_T_5861, _T_5862) @[el2_ifu_mem_ctl.scala 742:123] + node _T_5864 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_5865 = and(_T_5863, _T_5864) @[el2_ifu_mem_ctl.scala 742:144] + node _T_5866 = or(_T_5860, _T_5865) @[el2_ifu_mem_ctl.scala 742:80] + node _T_5867 = bits(_T_5866, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_5868 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5867 : @[Reg.scala 28:19] _T_5868 <= _T_5857 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][9] <= _T_5868 @[el2_ifu_mem_ctl.scala 740:39] - node _T_5869 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_5870 = eq(_T_5869, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_5871 = and(ic_valid_ff, _T_5870) @[el2_ifu_mem_ctl.scala 740:64] - node _T_5872 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_5873 = and(_T_5871, _T_5872) @[el2_ifu_mem_ctl.scala 740:89] - node _T_5874 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_5875 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_5876 = and(_T_5874, _T_5875) @[el2_ifu_mem_ctl.scala 741:58] - node _T_5877 = eq(perr_ic_index_ff, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_5878 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_5879 = and(_T_5877, _T_5878) @[el2_ifu_mem_ctl.scala 741:123] - node _T_5880 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_5881 = and(_T_5879, _T_5880) @[el2_ifu_mem_ctl.scala 741:144] - node _T_5882 = or(_T_5876, _T_5881) @[el2_ifu_mem_ctl.scala 741:80] - node _T_5883 = bits(_T_5882, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][9] <= _T_5868 @[el2_ifu_mem_ctl.scala 741:39] + node _T_5869 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_5870 = eq(_T_5869, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_5871 = and(ic_valid_ff, _T_5870) @[el2_ifu_mem_ctl.scala 741:64] + node _T_5872 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_5873 = and(_T_5871, _T_5872) @[el2_ifu_mem_ctl.scala 741:89] + node _T_5874 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_5875 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_5876 = and(_T_5874, _T_5875) @[el2_ifu_mem_ctl.scala 742:58] + node _T_5877 = eq(perr_ic_index_ff, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_5878 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_5879 = and(_T_5877, _T_5878) @[el2_ifu_mem_ctl.scala 742:123] + node _T_5880 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_5881 = and(_T_5879, _T_5880) @[el2_ifu_mem_ctl.scala 742:144] + node _T_5882 = or(_T_5876, _T_5881) @[el2_ifu_mem_ctl.scala 742:80] + node _T_5883 = bits(_T_5882, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_5884 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5883 : @[Reg.scala 28:19] _T_5884 <= _T_5873 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][10] <= _T_5884 @[el2_ifu_mem_ctl.scala 740:39] - node _T_5885 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_5886 = eq(_T_5885, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_5887 = and(ic_valid_ff, _T_5886) @[el2_ifu_mem_ctl.scala 740:64] - node _T_5888 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_5889 = and(_T_5887, _T_5888) @[el2_ifu_mem_ctl.scala 740:89] - node _T_5890 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_5891 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_5892 = and(_T_5890, _T_5891) @[el2_ifu_mem_ctl.scala 741:58] - node _T_5893 = eq(perr_ic_index_ff, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_5894 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_5895 = and(_T_5893, _T_5894) @[el2_ifu_mem_ctl.scala 741:123] - node _T_5896 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_5897 = and(_T_5895, _T_5896) @[el2_ifu_mem_ctl.scala 741:144] - node _T_5898 = or(_T_5892, _T_5897) @[el2_ifu_mem_ctl.scala 741:80] - node _T_5899 = bits(_T_5898, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][10] <= _T_5884 @[el2_ifu_mem_ctl.scala 741:39] + node _T_5885 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_5886 = eq(_T_5885, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_5887 = and(ic_valid_ff, _T_5886) @[el2_ifu_mem_ctl.scala 741:64] + node _T_5888 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_5889 = and(_T_5887, _T_5888) @[el2_ifu_mem_ctl.scala 741:89] + node _T_5890 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_5891 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_5892 = and(_T_5890, _T_5891) @[el2_ifu_mem_ctl.scala 742:58] + node _T_5893 = eq(perr_ic_index_ff, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_5894 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_5895 = and(_T_5893, _T_5894) @[el2_ifu_mem_ctl.scala 742:123] + node _T_5896 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_5897 = and(_T_5895, _T_5896) @[el2_ifu_mem_ctl.scala 742:144] + node _T_5898 = or(_T_5892, _T_5897) @[el2_ifu_mem_ctl.scala 742:80] + node _T_5899 = bits(_T_5898, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_5900 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5899 : @[Reg.scala 28:19] _T_5900 <= _T_5889 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][11] <= _T_5900 @[el2_ifu_mem_ctl.scala 740:39] - node _T_5901 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_5902 = eq(_T_5901, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_5903 = and(ic_valid_ff, _T_5902) @[el2_ifu_mem_ctl.scala 740:64] - node _T_5904 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_5905 = and(_T_5903, _T_5904) @[el2_ifu_mem_ctl.scala 740:89] - node _T_5906 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_5907 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_5908 = and(_T_5906, _T_5907) @[el2_ifu_mem_ctl.scala 741:58] - node _T_5909 = eq(perr_ic_index_ff, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_5910 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_5911 = and(_T_5909, _T_5910) @[el2_ifu_mem_ctl.scala 741:123] - node _T_5912 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_5913 = and(_T_5911, _T_5912) @[el2_ifu_mem_ctl.scala 741:144] - node _T_5914 = or(_T_5908, _T_5913) @[el2_ifu_mem_ctl.scala 741:80] - node _T_5915 = bits(_T_5914, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][11] <= _T_5900 @[el2_ifu_mem_ctl.scala 741:39] + node _T_5901 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_5902 = eq(_T_5901, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_5903 = and(ic_valid_ff, _T_5902) @[el2_ifu_mem_ctl.scala 741:64] + node _T_5904 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_5905 = and(_T_5903, _T_5904) @[el2_ifu_mem_ctl.scala 741:89] + node _T_5906 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_5907 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_5908 = and(_T_5906, _T_5907) @[el2_ifu_mem_ctl.scala 742:58] + node _T_5909 = eq(perr_ic_index_ff, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_5910 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_5911 = and(_T_5909, _T_5910) @[el2_ifu_mem_ctl.scala 742:123] + node _T_5912 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_5913 = and(_T_5911, _T_5912) @[el2_ifu_mem_ctl.scala 742:144] + node _T_5914 = or(_T_5908, _T_5913) @[el2_ifu_mem_ctl.scala 742:80] + node _T_5915 = bits(_T_5914, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_5916 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5915 : @[Reg.scala 28:19] _T_5916 <= _T_5905 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][12] <= _T_5916 @[el2_ifu_mem_ctl.scala 740:39] - node _T_5917 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_5918 = eq(_T_5917, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_5919 = and(ic_valid_ff, _T_5918) @[el2_ifu_mem_ctl.scala 740:64] - node _T_5920 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_5921 = and(_T_5919, _T_5920) @[el2_ifu_mem_ctl.scala 740:89] - node _T_5922 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_5923 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_5924 = and(_T_5922, _T_5923) @[el2_ifu_mem_ctl.scala 741:58] - node _T_5925 = eq(perr_ic_index_ff, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_5926 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_5927 = and(_T_5925, _T_5926) @[el2_ifu_mem_ctl.scala 741:123] - node _T_5928 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_5929 = and(_T_5927, _T_5928) @[el2_ifu_mem_ctl.scala 741:144] - node _T_5930 = or(_T_5924, _T_5929) @[el2_ifu_mem_ctl.scala 741:80] - node _T_5931 = bits(_T_5930, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][12] <= _T_5916 @[el2_ifu_mem_ctl.scala 741:39] + node _T_5917 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_5918 = eq(_T_5917, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_5919 = and(ic_valid_ff, _T_5918) @[el2_ifu_mem_ctl.scala 741:64] + node _T_5920 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_5921 = and(_T_5919, _T_5920) @[el2_ifu_mem_ctl.scala 741:89] + node _T_5922 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_5923 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_5924 = and(_T_5922, _T_5923) @[el2_ifu_mem_ctl.scala 742:58] + node _T_5925 = eq(perr_ic_index_ff, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_5926 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_5927 = and(_T_5925, _T_5926) @[el2_ifu_mem_ctl.scala 742:123] + node _T_5928 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_5929 = and(_T_5927, _T_5928) @[el2_ifu_mem_ctl.scala 742:144] + node _T_5930 = or(_T_5924, _T_5929) @[el2_ifu_mem_ctl.scala 742:80] + node _T_5931 = bits(_T_5930, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_5932 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5931 : @[Reg.scala 28:19] _T_5932 <= _T_5921 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][13] <= _T_5932 @[el2_ifu_mem_ctl.scala 740:39] - node _T_5933 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_5934 = eq(_T_5933, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_5935 = and(ic_valid_ff, _T_5934) @[el2_ifu_mem_ctl.scala 740:64] - node _T_5936 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_5937 = and(_T_5935, _T_5936) @[el2_ifu_mem_ctl.scala 740:89] - node _T_5938 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_5939 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_5940 = and(_T_5938, _T_5939) @[el2_ifu_mem_ctl.scala 741:58] - node _T_5941 = eq(perr_ic_index_ff, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_5942 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_5943 = and(_T_5941, _T_5942) @[el2_ifu_mem_ctl.scala 741:123] - node _T_5944 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_5945 = and(_T_5943, _T_5944) @[el2_ifu_mem_ctl.scala 741:144] - node _T_5946 = or(_T_5940, _T_5945) @[el2_ifu_mem_ctl.scala 741:80] - node _T_5947 = bits(_T_5946, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][13] <= _T_5932 @[el2_ifu_mem_ctl.scala 741:39] + node _T_5933 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_5934 = eq(_T_5933, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_5935 = and(ic_valid_ff, _T_5934) @[el2_ifu_mem_ctl.scala 741:64] + node _T_5936 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_5937 = and(_T_5935, _T_5936) @[el2_ifu_mem_ctl.scala 741:89] + node _T_5938 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_5939 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_5940 = and(_T_5938, _T_5939) @[el2_ifu_mem_ctl.scala 742:58] + node _T_5941 = eq(perr_ic_index_ff, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_5942 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_5943 = and(_T_5941, _T_5942) @[el2_ifu_mem_ctl.scala 742:123] + node _T_5944 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_5945 = and(_T_5943, _T_5944) @[el2_ifu_mem_ctl.scala 742:144] + node _T_5946 = or(_T_5940, _T_5945) @[el2_ifu_mem_ctl.scala 742:80] + node _T_5947 = bits(_T_5946, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_5948 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5947 : @[Reg.scala 28:19] _T_5948 <= _T_5937 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][14] <= _T_5948 @[el2_ifu_mem_ctl.scala 740:39] - node _T_5949 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_5950 = eq(_T_5949, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_5951 = and(ic_valid_ff, _T_5950) @[el2_ifu_mem_ctl.scala 740:64] - node _T_5952 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_5953 = and(_T_5951, _T_5952) @[el2_ifu_mem_ctl.scala 740:89] - node _T_5954 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_5955 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_5956 = and(_T_5954, _T_5955) @[el2_ifu_mem_ctl.scala 741:58] - node _T_5957 = eq(perr_ic_index_ff, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_5958 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_5959 = and(_T_5957, _T_5958) @[el2_ifu_mem_ctl.scala 741:123] - node _T_5960 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_5961 = and(_T_5959, _T_5960) @[el2_ifu_mem_ctl.scala 741:144] - node _T_5962 = or(_T_5956, _T_5961) @[el2_ifu_mem_ctl.scala 741:80] - node _T_5963 = bits(_T_5962, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][14] <= _T_5948 @[el2_ifu_mem_ctl.scala 741:39] + node _T_5949 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_5950 = eq(_T_5949, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_5951 = and(ic_valid_ff, _T_5950) @[el2_ifu_mem_ctl.scala 741:64] + node _T_5952 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_5953 = and(_T_5951, _T_5952) @[el2_ifu_mem_ctl.scala 741:89] + node _T_5954 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_5955 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_5956 = and(_T_5954, _T_5955) @[el2_ifu_mem_ctl.scala 742:58] + node _T_5957 = eq(perr_ic_index_ff, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_5958 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_5959 = and(_T_5957, _T_5958) @[el2_ifu_mem_ctl.scala 742:123] + node _T_5960 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_5961 = and(_T_5959, _T_5960) @[el2_ifu_mem_ctl.scala 742:144] + node _T_5962 = or(_T_5956, _T_5961) @[el2_ifu_mem_ctl.scala 742:80] + node _T_5963 = bits(_T_5962, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_5964 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5963 : @[Reg.scala 28:19] _T_5964 <= _T_5953 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][15] <= _T_5964 @[el2_ifu_mem_ctl.scala 740:39] - node _T_5965 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_5966 = eq(_T_5965, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_5967 = and(ic_valid_ff, _T_5966) @[el2_ifu_mem_ctl.scala 740:64] - node _T_5968 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_5969 = and(_T_5967, _T_5968) @[el2_ifu_mem_ctl.scala 740:89] - node _T_5970 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h010")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_5971 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_5972 = and(_T_5970, _T_5971) @[el2_ifu_mem_ctl.scala 741:58] - node _T_5973 = eq(perr_ic_index_ff, UInt<5>("h010")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_5974 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_5975 = and(_T_5973, _T_5974) @[el2_ifu_mem_ctl.scala 741:123] - node _T_5976 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_5977 = and(_T_5975, _T_5976) @[el2_ifu_mem_ctl.scala 741:144] - node _T_5978 = or(_T_5972, _T_5977) @[el2_ifu_mem_ctl.scala 741:80] - node _T_5979 = bits(_T_5978, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][15] <= _T_5964 @[el2_ifu_mem_ctl.scala 741:39] + node _T_5965 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_5966 = eq(_T_5965, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_5967 = and(ic_valid_ff, _T_5966) @[el2_ifu_mem_ctl.scala 741:64] + node _T_5968 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_5969 = and(_T_5967, _T_5968) @[el2_ifu_mem_ctl.scala 741:89] + node _T_5970 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h010")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_5971 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_5972 = and(_T_5970, _T_5971) @[el2_ifu_mem_ctl.scala 742:58] + node _T_5973 = eq(perr_ic_index_ff, UInt<5>("h010")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_5974 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_5975 = and(_T_5973, _T_5974) @[el2_ifu_mem_ctl.scala 742:123] + node _T_5976 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_5977 = and(_T_5975, _T_5976) @[el2_ifu_mem_ctl.scala 742:144] + node _T_5978 = or(_T_5972, _T_5977) @[el2_ifu_mem_ctl.scala 742:80] + node _T_5979 = bits(_T_5978, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_5980 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5979 : @[Reg.scala 28:19] _T_5980 <= _T_5969 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][16] <= _T_5980 @[el2_ifu_mem_ctl.scala 740:39] - node _T_5981 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_5982 = eq(_T_5981, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_5983 = and(ic_valid_ff, _T_5982) @[el2_ifu_mem_ctl.scala 740:64] - node _T_5984 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_5985 = and(_T_5983, _T_5984) @[el2_ifu_mem_ctl.scala 740:89] - node _T_5986 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h011")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_5987 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_5988 = and(_T_5986, _T_5987) @[el2_ifu_mem_ctl.scala 741:58] - node _T_5989 = eq(perr_ic_index_ff, UInt<5>("h011")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_5990 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_5991 = and(_T_5989, _T_5990) @[el2_ifu_mem_ctl.scala 741:123] - node _T_5992 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_5993 = and(_T_5991, _T_5992) @[el2_ifu_mem_ctl.scala 741:144] - node _T_5994 = or(_T_5988, _T_5993) @[el2_ifu_mem_ctl.scala 741:80] - node _T_5995 = bits(_T_5994, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][16] <= _T_5980 @[el2_ifu_mem_ctl.scala 741:39] + node _T_5981 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_5982 = eq(_T_5981, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_5983 = and(ic_valid_ff, _T_5982) @[el2_ifu_mem_ctl.scala 741:64] + node _T_5984 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_5985 = and(_T_5983, _T_5984) @[el2_ifu_mem_ctl.scala 741:89] + node _T_5986 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h011")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_5987 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_5988 = and(_T_5986, _T_5987) @[el2_ifu_mem_ctl.scala 742:58] + node _T_5989 = eq(perr_ic_index_ff, UInt<5>("h011")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_5990 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_5991 = and(_T_5989, _T_5990) @[el2_ifu_mem_ctl.scala 742:123] + node _T_5992 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_5993 = and(_T_5991, _T_5992) @[el2_ifu_mem_ctl.scala 742:144] + node _T_5994 = or(_T_5988, _T_5993) @[el2_ifu_mem_ctl.scala 742:80] + node _T_5995 = bits(_T_5994, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_5996 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_5995 : @[Reg.scala 28:19] _T_5996 <= _T_5985 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][17] <= _T_5996 @[el2_ifu_mem_ctl.scala 740:39] - node _T_5997 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_5998 = eq(_T_5997, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_5999 = and(ic_valid_ff, _T_5998) @[el2_ifu_mem_ctl.scala 740:64] - node _T_6000 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_6001 = and(_T_5999, _T_6000) @[el2_ifu_mem_ctl.scala 740:89] - node _T_6002 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h012")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_6003 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_6004 = and(_T_6002, _T_6003) @[el2_ifu_mem_ctl.scala 741:58] - node _T_6005 = eq(perr_ic_index_ff, UInt<5>("h012")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_6006 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_6007 = and(_T_6005, _T_6006) @[el2_ifu_mem_ctl.scala 741:123] - node _T_6008 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_6009 = and(_T_6007, _T_6008) @[el2_ifu_mem_ctl.scala 741:144] - node _T_6010 = or(_T_6004, _T_6009) @[el2_ifu_mem_ctl.scala 741:80] - node _T_6011 = bits(_T_6010, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][17] <= _T_5996 @[el2_ifu_mem_ctl.scala 741:39] + node _T_5997 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_5998 = eq(_T_5997, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_5999 = and(ic_valid_ff, _T_5998) @[el2_ifu_mem_ctl.scala 741:64] + node _T_6000 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_6001 = and(_T_5999, _T_6000) @[el2_ifu_mem_ctl.scala 741:89] + node _T_6002 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h012")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_6003 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_6004 = and(_T_6002, _T_6003) @[el2_ifu_mem_ctl.scala 742:58] + node _T_6005 = eq(perr_ic_index_ff, UInt<5>("h012")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_6006 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_6007 = and(_T_6005, _T_6006) @[el2_ifu_mem_ctl.scala 742:123] + node _T_6008 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_6009 = and(_T_6007, _T_6008) @[el2_ifu_mem_ctl.scala 742:144] + node _T_6010 = or(_T_6004, _T_6009) @[el2_ifu_mem_ctl.scala 742:80] + node _T_6011 = bits(_T_6010, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_6012 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6011 : @[Reg.scala 28:19] _T_6012 <= _T_6001 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][18] <= _T_6012 @[el2_ifu_mem_ctl.scala 740:39] - node _T_6013 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_6014 = eq(_T_6013, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_6015 = and(ic_valid_ff, _T_6014) @[el2_ifu_mem_ctl.scala 740:64] - node _T_6016 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_6017 = and(_T_6015, _T_6016) @[el2_ifu_mem_ctl.scala 740:89] - node _T_6018 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h013")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_6019 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_6020 = and(_T_6018, _T_6019) @[el2_ifu_mem_ctl.scala 741:58] - node _T_6021 = eq(perr_ic_index_ff, UInt<5>("h013")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_6022 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_6023 = and(_T_6021, _T_6022) @[el2_ifu_mem_ctl.scala 741:123] - node _T_6024 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_6025 = and(_T_6023, _T_6024) @[el2_ifu_mem_ctl.scala 741:144] - node _T_6026 = or(_T_6020, _T_6025) @[el2_ifu_mem_ctl.scala 741:80] - node _T_6027 = bits(_T_6026, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][18] <= _T_6012 @[el2_ifu_mem_ctl.scala 741:39] + node _T_6013 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_6014 = eq(_T_6013, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_6015 = and(ic_valid_ff, _T_6014) @[el2_ifu_mem_ctl.scala 741:64] + node _T_6016 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_6017 = and(_T_6015, _T_6016) @[el2_ifu_mem_ctl.scala 741:89] + node _T_6018 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h013")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_6019 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_6020 = and(_T_6018, _T_6019) @[el2_ifu_mem_ctl.scala 742:58] + node _T_6021 = eq(perr_ic_index_ff, UInt<5>("h013")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_6022 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_6023 = and(_T_6021, _T_6022) @[el2_ifu_mem_ctl.scala 742:123] + node _T_6024 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_6025 = and(_T_6023, _T_6024) @[el2_ifu_mem_ctl.scala 742:144] + node _T_6026 = or(_T_6020, _T_6025) @[el2_ifu_mem_ctl.scala 742:80] + node _T_6027 = bits(_T_6026, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_6028 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6027 : @[Reg.scala 28:19] _T_6028 <= _T_6017 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][19] <= _T_6028 @[el2_ifu_mem_ctl.scala 740:39] - node _T_6029 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_6030 = eq(_T_6029, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_6031 = and(ic_valid_ff, _T_6030) @[el2_ifu_mem_ctl.scala 740:64] - node _T_6032 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_6033 = and(_T_6031, _T_6032) @[el2_ifu_mem_ctl.scala 740:89] - node _T_6034 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h014")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_6035 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_6036 = and(_T_6034, _T_6035) @[el2_ifu_mem_ctl.scala 741:58] - node _T_6037 = eq(perr_ic_index_ff, UInt<5>("h014")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_6038 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_6039 = and(_T_6037, _T_6038) @[el2_ifu_mem_ctl.scala 741:123] - node _T_6040 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_6041 = and(_T_6039, _T_6040) @[el2_ifu_mem_ctl.scala 741:144] - node _T_6042 = or(_T_6036, _T_6041) @[el2_ifu_mem_ctl.scala 741:80] - node _T_6043 = bits(_T_6042, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][19] <= _T_6028 @[el2_ifu_mem_ctl.scala 741:39] + node _T_6029 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_6030 = eq(_T_6029, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_6031 = and(ic_valid_ff, _T_6030) @[el2_ifu_mem_ctl.scala 741:64] + node _T_6032 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_6033 = and(_T_6031, _T_6032) @[el2_ifu_mem_ctl.scala 741:89] + node _T_6034 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h014")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_6035 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_6036 = and(_T_6034, _T_6035) @[el2_ifu_mem_ctl.scala 742:58] + node _T_6037 = eq(perr_ic_index_ff, UInt<5>("h014")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_6038 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_6039 = and(_T_6037, _T_6038) @[el2_ifu_mem_ctl.scala 742:123] + node _T_6040 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_6041 = and(_T_6039, _T_6040) @[el2_ifu_mem_ctl.scala 742:144] + node _T_6042 = or(_T_6036, _T_6041) @[el2_ifu_mem_ctl.scala 742:80] + node _T_6043 = bits(_T_6042, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_6044 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6043 : @[Reg.scala 28:19] _T_6044 <= _T_6033 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][20] <= _T_6044 @[el2_ifu_mem_ctl.scala 740:39] - node _T_6045 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_6046 = eq(_T_6045, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_6047 = and(ic_valid_ff, _T_6046) @[el2_ifu_mem_ctl.scala 740:64] - node _T_6048 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_6049 = and(_T_6047, _T_6048) @[el2_ifu_mem_ctl.scala 740:89] - node _T_6050 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h015")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_6051 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_6052 = and(_T_6050, _T_6051) @[el2_ifu_mem_ctl.scala 741:58] - node _T_6053 = eq(perr_ic_index_ff, UInt<5>("h015")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_6054 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_6055 = and(_T_6053, _T_6054) @[el2_ifu_mem_ctl.scala 741:123] - node _T_6056 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_6057 = and(_T_6055, _T_6056) @[el2_ifu_mem_ctl.scala 741:144] - node _T_6058 = or(_T_6052, _T_6057) @[el2_ifu_mem_ctl.scala 741:80] - node _T_6059 = bits(_T_6058, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][20] <= _T_6044 @[el2_ifu_mem_ctl.scala 741:39] + node _T_6045 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_6046 = eq(_T_6045, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_6047 = and(ic_valid_ff, _T_6046) @[el2_ifu_mem_ctl.scala 741:64] + node _T_6048 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_6049 = and(_T_6047, _T_6048) @[el2_ifu_mem_ctl.scala 741:89] + node _T_6050 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h015")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_6051 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_6052 = and(_T_6050, _T_6051) @[el2_ifu_mem_ctl.scala 742:58] + node _T_6053 = eq(perr_ic_index_ff, UInt<5>("h015")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_6054 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_6055 = and(_T_6053, _T_6054) @[el2_ifu_mem_ctl.scala 742:123] + node _T_6056 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_6057 = and(_T_6055, _T_6056) @[el2_ifu_mem_ctl.scala 742:144] + node _T_6058 = or(_T_6052, _T_6057) @[el2_ifu_mem_ctl.scala 742:80] + node _T_6059 = bits(_T_6058, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_6060 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6059 : @[Reg.scala 28:19] _T_6060 <= _T_6049 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][21] <= _T_6060 @[el2_ifu_mem_ctl.scala 740:39] - node _T_6061 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_6062 = eq(_T_6061, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_6063 = and(ic_valid_ff, _T_6062) @[el2_ifu_mem_ctl.scala 740:64] - node _T_6064 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_6065 = and(_T_6063, _T_6064) @[el2_ifu_mem_ctl.scala 740:89] - node _T_6066 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h016")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_6067 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_6068 = and(_T_6066, _T_6067) @[el2_ifu_mem_ctl.scala 741:58] - node _T_6069 = eq(perr_ic_index_ff, UInt<5>("h016")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_6070 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_6071 = and(_T_6069, _T_6070) @[el2_ifu_mem_ctl.scala 741:123] - node _T_6072 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_6073 = and(_T_6071, _T_6072) @[el2_ifu_mem_ctl.scala 741:144] - node _T_6074 = or(_T_6068, _T_6073) @[el2_ifu_mem_ctl.scala 741:80] - node _T_6075 = bits(_T_6074, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][21] <= _T_6060 @[el2_ifu_mem_ctl.scala 741:39] + node _T_6061 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_6062 = eq(_T_6061, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_6063 = and(ic_valid_ff, _T_6062) @[el2_ifu_mem_ctl.scala 741:64] + node _T_6064 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_6065 = and(_T_6063, _T_6064) @[el2_ifu_mem_ctl.scala 741:89] + node _T_6066 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h016")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_6067 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_6068 = and(_T_6066, _T_6067) @[el2_ifu_mem_ctl.scala 742:58] + node _T_6069 = eq(perr_ic_index_ff, UInt<5>("h016")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_6070 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_6071 = and(_T_6069, _T_6070) @[el2_ifu_mem_ctl.scala 742:123] + node _T_6072 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_6073 = and(_T_6071, _T_6072) @[el2_ifu_mem_ctl.scala 742:144] + node _T_6074 = or(_T_6068, _T_6073) @[el2_ifu_mem_ctl.scala 742:80] + node _T_6075 = bits(_T_6074, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_6076 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6075 : @[Reg.scala 28:19] _T_6076 <= _T_6065 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][22] <= _T_6076 @[el2_ifu_mem_ctl.scala 740:39] - node _T_6077 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_6078 = eq(_T_6077, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_6079 = and(ic_valid_ff, _T_6078) @[el2_ifu_mem_ctl.scala 740:64] - node _T_6080 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_6081 = and(_T_6079, _T_6080) @[el2_ifu_mem_ctl.scala 740:89] - node _T_6082 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h017")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_6083 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_6084 = and(_T_6082, _T_6083) @[el2_ifu_mem_ctl.scala 741:58] - node _T_6085 = eq(perr_ic_index_ff, UInt<5>("h017")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_6086 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_6087 = and(_T_6085, _T_6086) @[el2_ifu_mem_ctl.scala 741:123] - node _T_6088 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_6089 = and(_T_6087, _T_6088) @[el2_ifu_mem_ctl.scala 741:144] - node _T_6090 = or(_T_6084, _T_6089) @[el2_ifu_mem_ctl.scala 741:80] - node _T_6091 = bits(_T_6090, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][22] <= _T_6076 @[el2_ifu_mem_ctl.scala 741:39] + node _T_6077 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_6078 = eq(_T_6077, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_6079 = and(ic_valid_ff, _T_6078) @[el2_ifu_mem_ctl.scala 741:64] + node _T_6080 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_6081 = and(_T_6079, _T_6080) @[el2_ifu_mem_ctl.scala 741:89] + node _T_6082 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h017")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_6083 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_6084 = and(_T_6082, _T_6083) @[el2_ifu_mem_ctl.scala 742:58] + node _T_6085 = eq(perr_ic_index_ff, UInt<5>("h017")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_6086 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_6087 = and(_T_6085, _T_6086) @[el2_ifu_mem_ctl.scala 742:123] + node _T_6088 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_6089 = and(_T_6087, _T_6088) @[el2_ifu_mem_ctl.scala 742:144] + node _T_6090 = or(_T_6084, _T_6089) @[el2_ifu_mem_ctl.scala 742:80] + node _T_6091 = bits(_T_6090, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_6092 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6091 : @[Reg.scala 28:19] _T_6092 <= _T_6081 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][23] <= _T_6092 @[el2_ifu_mem_ctl.scala 740:39] - node _T_6093 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_6094 = eq(_T_6093, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_6095 = and(ic_valid_ff, _T_6094) @[el2_ifu_mem_ctl.scala 740:64] - node _T_6096 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_6097 = and(_T_6095, _T_6096) @[el2_ifu_mem_ctl.scala 740:89] - node _T_6098 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h018")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_6099 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_6100 = and(_T_6098, _T_6099) @[el2_ifu_mem_ctl.scala 741:58] - node _T_6101 = eq(perr_ic_index_ff, UInt<5>("h018")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_6102 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_6103 = and(_T_6101, _T_6102) @[el2_ifu_mem_ctl.scala 741:123] - node _T_6104 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_6105 = and(_T_6103, _T_6104) @[el2_ifu_mem_ctl.scala 741:144] - node _T_6106 = or(_T_6100, _T_6105) @[el2_ifu_mem_ctl.scala 741:80] - node _T_6107 = bits(_T_6106, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][23] <= _T_6092 @[el2_ifu_mem_ctl.scala 741:39] + node _T_6093 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_6094 = eq(_T_6093, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_6095 = and(ic_valid_ff, _T_6094) @[el2_ifu_mem_ctl.scala 741:64] + node _T_6096 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_6097 = and(_T_6095, _T_6096) @[el2_ifu_mem_ctl.scala 741:89] + node _T_6098 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h018")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_6099 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_6100 = and(_T_6098, _T_6099) @[el2_ifu_mem_ctl.scala 742:58] + node _T_6101 = eq(perr_ic_index_ff, UInt<5>("h018")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_6102 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_6103 = and(_T_6101, _T_6102) @[el2_ifu_mem_ctl.scala 742:123] + node _T_6104 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_6105 = and(_T_6103, _T_6104) @[el2_ifu_mem_ctl.scala 742:144] + node _T_6106 = or(_T_6100, _T_6105) @[el2_ifu_mem_ctl.scala 742:80] + node _T_6107 = bits(_T_6106, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_6108 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6107 : @[Reg.scala 28:19] _T_6108 <= _T_6097 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][24] <= _T_6108 @[el2_ifu_mem_ctl.scala 740:39] - node _T_6109 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_6110 = eq(_T_6109, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_6111 = and(ic_valid_ff, _T_6110) @[el2_ifu_mem_ctl.scala 740:64] - node _T_6112 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_6113 = and(_T_6111, _T_6112) @[el2_ifu_mem_ctl.scala 740:89] - node _T_6114 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h019")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_6115 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_6116 = and(_T_6114, _T_6115) @[el2_ifu_mem_ctl.scala 741:58] - node _T_6117 = eq(perr_ic_index_ff, UInt<5>("h019")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_6118 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_6119 = and(_T_6117, _T_6118) @[el2_ifu_mem_ctl.scala 741:123] - node _T_6120 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_6121 = and(_T_6119, _T_6120) @[el2_ifu_mem_ctl.scala 741:144] - node _T_6122 = or(_T_6116, _T_6121) @[el2_ifu_mem_ctl.scala 741:80] - node _T_6123 = bits(_T_6122, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][24] <= _T_6108 @[el2_ifu_mem_ctl.scala 741:39] + node _T_6109 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_6110 = eq(_T_6109, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_6111 = and(ic_valid_ff, _T_6110) @[el2_ifu_mem_ctl.scala 741:64] + node _T_6112 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_6113 = and(_T_6111, _T_6112) @[el2_ifu_mem_ctl.scala 741:89] + node _T_6114 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h019")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_6115 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_6116 = and(_T_6114, _T_6115) @[el2_ifu_mem_ctl.scala 742:58] + node _T_6117 = eq(perr_ic_index_ff, UInt<5>("h019")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_6118 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_6119 = and(_T_6117, _T_6118) @[el2_ifu_mem_ctl.scala 742:123] + node _T_6120 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_6121 = and(_T_6119, _T_6120) @[el2_ifu_mem_ctl.scala 742:144] + node _T_6122 = or(_T_6116, _T_6121) @[el2_ifu_mem_ctl.scala 742:80] + node _T_6123 = bits(_T_6122, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_6124 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6123 : @[Reg.scala 28:19] _T_6124 <= _T_6113 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][25] <= _T_6124 @[el2_ifu_mem_ctl.scala 740:39] - node _T_6125 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_6126 = eq(_T_6125, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_6127 = and(ic_valid_ff, _T_6126) @[el2_ifu_mem_ctl.scala 740:64] - node _T_6128 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_6129 = and(_T_6127, _T_6128) @[el2_ifu_mem_ctl.scala 740:89] - node _T_6130 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01a")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_6131 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_6132 = and(_T_6130, _T_6131) @[el2_ifu_mem_ctl.scala 741:58] - node _T_6133 = eq(perr_ic_index_ff, UInt<5>("h01a")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_6134 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_6135 = and(_T_6133, _T_6134) @[el2_ifu_mem_ctl.scala 741:123] - node _T_6136 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_6137 = and(_T_6135, _T_6136) @[el2_ifu_mem_ctl.scala 741:144] - node _T_6138 = or(_T_6132, _T_6137) @[el2_ifu_mem_ctl.scala 741:80] - node _T_6139 = bits(_T_6138, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][25] <= _T_6124 @[el2_ifu_mem_ctl.scala 741:39] + node _T_6125 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_6126 = eq(_T_6125, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_6127 = and(ic_valid_ff, _T_6126) @[el2_ifu_mem_ctl.scala 741:64] + node _T_6128 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_6129 = and(_T_6127, _T_6128) @[el2_ifu_mem_ctl.scala 741:89] + node _T_6130 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01a")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_6131 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_6132 = and(_T_6130, _T_6131) @[el2_ifu_mem_ctl.scala 742:58] + node _T_6133 = eq(perr_ic_index_ff, UInt<5>("h01a")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_6134 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_6135 = and(_T_6133, _T_6134) @[el2_ifu_mem_ctl.scala 742:123] + node _T_6136 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_6137 = and(_T_6135, _T_6136) @[el2_ifu_mem_ctl.scala 742:144] + node _T_6138 = or(_T_6132, _T_6137) @[el2_ifu_mem_ctl.scala 742:80] + node _T_6139 = bits(_T_6138, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_6140 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6139 : @[Reg.scala 28:19] _T_6140 <= _T_6129 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][26] <= _T_6140 @[el2_ifu_mem_ctl.scala 740:39] - node _T_6141 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_6142 = eq(_T_6141, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_6143 = and(ic_valid_ff, _T_6142) @[el2_ifu_mem_ctl.scala 740:64] - node _T_6144 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_6145 = and(_T_6143, _T_6144) @[el2_ifu_mem_ctl.scala 740:89] - node _T_6146 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01b")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_6147 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_6148 = and(_T_6146, _T_6147) @[el2_ifu_mem_ctl.scala 741:58] - node _T_6149 = eq(perr_ic_index_ff, UInt<5>("h01b")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_6150 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_6151 = and(_T_6149, _T_6150) @[el2_ifu_mem_ctl.scala 741:123] - node _T_6152 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_6153 = and(_T_6151, _T_6152) @[el2_ifu_mem_ctl.scala 741:144] - node _T_6154 = or(_T_6148, _T_6153) @[el2_ifu_mem_ctl.scala 741:80] - node _T_6155 = bits(_T_6154, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][26] <= _T_6140 @[el2_ifu_mem_ctl.scala 741:39] + node _T_6141 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_6142 = eq(_T_6141, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_6143 = and(ic_valid_ff, _T_6142) @[el2_ifu_mem_ctl.scala 741:64] + node _T_6144 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_6145 = and(_T_6143, _T_6144) @[el2_ifu_mem_ctl.scala 741:89] + node _T_6146 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01b")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_6147 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_6148 = and(_T_6146, _T_6147) @[el2_ifu_mem_ctl.scala 742:58] + node _T_6149 = eq(perr_ic_index_ff, UInt<5>("h01b")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_6150 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_6151 = and(_T_6149, _T_6150) @[el2_ifu_mem_ctl.scala 742:123] + node _T_6152 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_6153 = and(_T_6151, _T_6152) @[el2_ifu_mem_ctl.scala 742:144] + node _T_6154 = or(_T_6148, _T_6153) @[el2_ifu_mem_ctl.scala 742:80] + node _T_6155 = bits(_T_6154, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_6156 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6155 : @[Reg.scala 28:19] _T_6156 <= _T_6145 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][27] <= _T_6156 @[el2_ifu_mem_ctl.scala 740:39] - node _T_6157 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_6158 = eq(_T_6157, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_6159 = and(ic_valid_ff, _T_6158) @[el2_ifu_mem_ctl.scala 740:64] - node _T_6160 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_6161 = and(_T_6159, _T_6160) @[el2_ifu_mem_ctl.scala 740:89] - node _T_6162 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01c")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_6163 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_6164 = and(_T_6162, _T_6163) @[el2_ifu_mem_ctl.scala 741:58] - node _T_6165 = eq(perr_ic_index_ff, UInt<5>("h01c")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_6166 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_6167 = and(_T_6165, _T_6166) @[el2_ifu_mem_ctl.scala 741:123] - node _T_6168 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_6169 = and(_T_6167, _T_6168) @[el2_ifu_mem_ctl.scala 741:144] - node _T_6170 = or(_T_6164, _T_6169) @[el2_ifu_mem_ctl.scala 741:80] - node _T_6171 = bits(_T_6170, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][27] <= _T_6156 @[el2_ifu_mem_ctl.scala 741:39] + node _T_6157 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_6158 = eq(_T_6157, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_6159 = and(ic_valid_ff, _T_6158) @[el2_ifu_mem_ctl.scala 741:64] + node _T_6160 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_6161 = and(_T_6159, _T_6160) @[el2_ifu_mem_ctl.scala 741:89] + node _T_6162 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01c")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_6163 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_6164 = and(_T_6162, _T_6163) @[el2_ifu_mem_ctl.scala 742:58] + node _T_6165 = eq(perr_ic_index_ff, UInt<5>("h01c")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_6166 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_6167 = and(_T_6165, _T_6166) @[el2_ifu_mem_ctl.scala 742:123] + node _T_6168 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_6169 = and(_T_6167, _T_6168) @[el2_ifu_mem_ctl.scala 742:144] + node _T_6170 = or(_T_6164, _T_6169) @[el2_ifu_mem_ctl.scala 742:80] + node _T_6171 = bits(_T_6170, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_6172 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6171 : @[Reg.scala 28:19] _T_6172 <= _T_6161 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][28] <= _T_6172 @[el2_ifu_mem_ctl.scala 740:39] - node _T_6173 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_6174 = eq(_T_6173, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_6175 = and(ic_valid_ff, _T_6174) @[el2_ifu_mem_ctl.scala 740:64] - node _T_6176 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_6177 = and(_T_6175, _T_6176) @[el2_ifu_mem_ctl.scala 740:89] - node _T_6178 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01d")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_6179 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_6180 = and(_T_6178, _T_6179) @[el2_ifu_mem_ctl.scala 741:58] - node _T_6181 = eq(perr_ic_index_ff, UInt<5>("h01d")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_6182 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_6183 = and(_T_6181, _T_6182) @[el2_ifu_mem_ctl.scala 741:123] - node _T_6184 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_6185 = and(_T_6183, _T_6184) @[el2_ifu_mem_ctl.scala 741:144] - node _T_6186 = or(_T_6180, _T_6185) @[el2_ifu_mem_ctl.scala 741:80] - node _T_6187 = bits(_T_6186, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][28] <= _T_6172 @[el2_ifu_mem_ctl.scala 741:39] + node _T_6173 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_6174 = eq(_T_6173, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_6175 = and(ic_valid_ff, _T_6174) @[el2_ifu_mem_ctl.scala 741:64] + node _T_6176 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_6177 = and(_T_6175, _T_6176) @[el2_ifu_mem_ctl.scala 741:89] + node _T_6178 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01d")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_6179 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_6180 = and(_T_6178, _T_6179) @[el2_ifu_mem_ctl.scala 742:58] + node _T_6181 = eq(perr_ic_index_ff, UInt<5>("h01d")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_6182 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_6183 = and(_T_6181, _T_6182) @[el2_ifu_mem_ctl.scala 742:123] + node _T_6184 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_6185 = and(_T_6183, _T_6184) @[el2_ifu_mem_ctl.scala 742:144] + node _T_6186 = or(_T_6180, _T_6185) @[el2_ifu_mem_ctl.scala 742:80] + node _T_6187 = bits(_T_6186, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_6188 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6187 : @[Reg.scala 28:19] _T_6188 <= _T_6177 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][29] <= _T_6188 @[el2_ifu_mem_ctl.scala 740:39] - node _T_6189 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_6190 = eq(_T_6189, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_6191 = and(ic_valid_ff, _T_6190) @[el2_ifu_mem_ctl.scala 740:64] - node _T_6192 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_6193 = and(_T_6191, _T_6192) @[el2_ifu_mem_ctl.scala 740:89] - node _T_6194 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01e")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_6195 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_6196 = and(_T_6194, _T_6195) @[el2_ifu_mem_ctl.scala 741:58] - node _T_6197 = eq(perr_ic_index_ff, UInt<5>("h01e")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_6198 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_6199 = and(_T_6197, _T_6198) @[el2_ifu_mem_ctl.scala 741:123] - node _T_6200 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_6201 = and(_T_6199, _T_6200) @[el2_ifu_mem_ctl.scala 741:144] - node _T_6202 = or(_T_6196, _T_6201) @[el2_ifu_mem_ctl.scala 741:80] - node _T_6203 = bits(_T_6202, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][29] <= _T_6188 @[el2_ifu_mem_ctl.scala 741:39] + node _T_6189 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_6190 = eq(_T_6189, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_6191 = and(ic_valid_ff, _T_6190) @[el2_ifu_mem_ctl.scala 741:64] + node _T_6192 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_6193 = and(_T_6191, _T_6192) @[el2_ifu_mem_ctl.scala 741:89] + node _T_6194 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01e")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_6195 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_6196 = and(_T_6194, _T_6195) @[el2_ifu_mem_ctl.scala 742:58] + node _T_6197 = eq(perr_ic_index_ff, UInt<5>("h01e")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_6198 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_6199 = and(_T_6197, _T_6198) @[el2_ifu_mem_ctl.scala 742:123] + node _T_6200 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_6201 = and(_T_6199, _T_6200) @[el2_ifu_mem_ctl.scala 742:144] + node _T_6202 = or(_T_6196, _T_6201) @[el2_ifu_mem_ctl.scala 742:80] + node _T_6203 = bits(_T_6202, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_6204 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6203 : @[Reg.scala 28:19] _T_6204 <= _T_6193 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][30] <= _T_6204 @[el2_ifu_mem_ctl.scala 740:39] - node _T_6205 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_6206 = eq(_T_6205, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_6207 = and(ic_valid_ff, _T_6206) @[el2_ifu_mem_ctl.scala 740:64] - node _T_6208 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_6209 = and(_T_6207, _T_6208) @[el2_ifu_mem_ctl.scala 740:89] - node _T_6210 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01f")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_6211 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_6212 = and(_T_6210, _T_6211) @[el2_ifu_mem_ctl.scala 741:58] - node _T_6213 = eq(perr_ic_index_ff, UInt<5>("h01f")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_6214 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_6215 = and(_T_6213, _T_6214) @[el2_ifu_mem_ctl.scala 741:123] - node _T_6216 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_6217 = and(_T_6215, _T_6216) @[el2_ifu_mem_ctl.scala 741:144] - node _T_6218 = or(_T_6212, _T_6217) @[el2_ifu_mem_ctl.scala 741:80] - node _T_6219 = bits(_T_6218, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][30] <= _T_6204 @[el2_ifu_mem_ctl.scala 741:39] + node _T_6205 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_6206 = eq(_T_6205, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_6207 = and(ic_valid_ff, _T_6206) @[el2_ifu_mem_ctl.scala 741:64] + node _T_6208 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_6209 = and(_T_6207, _T_6208) @[el2_ifu_mem_ctl.scala 741:89] + node _T_6210 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01f")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_6211 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_6212 = and(_T_6210, _T_6211) @[el2_ifu_mem_ctl.scala 742:58] + node _T_6213 = eq(perr_ic_index_ff, UInt<5>("h01f")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_6214 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_6215 = and(_T_6213, _T_6214) @[el2_ifu_mem_ctl.scala 742:123] + node _T_6216 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_6217 = and(_T_6215, _T_6216) @[el2_ifu_mem_ctl.scala 742:144] + node _T_6218 = or(_T_6212, _T_6217) @[el2_ifu_mem_ctl.scala 742:80] + node _T_6219 = bits(_T_6218, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_6220 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6219 : @[Reg.scala 28:19] _T_6220 <= _T_6209 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][31] <= _T_6220 @[el2_ifu_mem_ctl.scala 740:39] - node _T_6221 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_6222 = eq(_T_6221, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_6223 = and(ic_valid_ff, _T_6222) @[el2_ifu_mem_ctl.scala 740:64] - node _T_6224 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_6225 = and(_T_6223, _T_6224) @[el2_ifu_mem_ctl.scala 740:89] - node _T_6226 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h020")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_6227 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_6228 = and(_T_6226, _T_6227) @[el2_ifu_mem_ctl.scala 741:58] - node _T_6229 = eq(perr_ic_index_ff, UInt<6>("h020")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_6230 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_6231 = and(_T_6229, _T_6230) @[el2_ifu_mem_ctl.scala 741:123] - node _T_6232 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_6233 = and(_T_6231, _T_6232) @[el2_ifu_mem_ctl.scala 741:144] - node _T_6234 = or(_T_6228, _T_6233) @[el2_ifu_mem_ctl.scala 741:80] - node _T_6235 = bits(_T_6234, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][31] <= _T_6220 @[el2_ifu_mem_ctl.scala 741:39] + node _T_6221 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_6222 = eq(_T_6221, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_6223 = and(ic_valid_ff, _T_6222) @[el2_ifu_mem_ctl.scala 741:64] + node _T_6224 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_6225 = and(_T_6223, _T_6224) @[el2_ifu_mem_ctl.scala 741:89] + node _T_6226 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h020")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_6227 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_6228 = and(_T_6226, _T_6227) @[el2_ifu_mem_ctl.scala 742:58] + node _T_6229 = eq(perr_ic_index_ff, UInt<6>("h020")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_6230 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_6231 = and(_T_6229, _T_6230) @[el2_ifu_mem_ctl.scala 742:123] + node _T_6232 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_6233 = and(_T_6231, _T_6232) @[el2_ifu_mem_ctl.scala 742:144] + node _T_6234 = or(_T_6228, _T_6233) @[el2_ifu_mem_ctl.scala 742:80] + node _T_6235 = bits(_T_6234, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_6236 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6235 : @[Reg.scala 28:19] _T_6236 <= _T_6225 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][32] <= _T_6236 @[el2_ifu_mem_ctl.scala 740:39] - node _T_6237 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_6238 = eq(_T_6237, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_6239 = and(ic_valid_ff, _T_6238) @[el2_ifu_mem_ctl.scala 740:64] - node _T_6240 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_6241 = and(_T_6239, _T_6240) @[el2_ifu_mem_ctl.scala 740:89] - node _T_6242 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h021")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_6243 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_6244 = and(_T_6242, _T_6243) @[el2_ifu_mem_ctl.scala 741:58] - node _T_6245 = eq(perr_ic_index_ff, UInt<6>("h021")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_6246 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_6247 = and(_T_6245, _T_6246) @[el2_ifu_mem_ctl.scala 741:123] - node _T_6248 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_6249 = and(_T_6247, _T_6248) @[el2_ifu_mem_ctl.scala 741:144] - node _T_6250 = or(_T_6244, _T_6249) @[el2_ifu_mem_ctl.scala 741:80] - node _T_6251 = bits(_T_6250, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][32] <= _T_6236 @[el2_ifu_mem_ctl.scala 741:39] + node _T_6237 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_6238 = eq(_T_6237, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_6239 = and(ic_valid_ff, _T_6238) @[el2_ifu_mem_ctl.scala 741:64] + node _T_6240 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_6241 = and(_T_6239, _T_6240) @[el2_ifu_mem_ctl.scala 741:89] + node _T_6242 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h021")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_6243 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_6244 = and(_T_6242, _T_6243) @[el2_ifu_mem_ctl.scala 742:58] + node _T_6245 = eq(perr_ic_index_ff, UInt<6>("h021")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_6246 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_6247 = and(_T_6245, _T_6246) @[el2_ifu_mem_ctl.scala 742:123] + node _T_6248 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_6249 = and(_T_6247, _T_6248) @[el2_ifu_mem_ctl.scala 742:144] + node _T_6250 = or(_T_6244, _T_6249) @[el2_ifu_mem_ctl.scala 742:80] + node _T_6251 = bits(_T_6250, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_6252 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6251 : @[Reg.scala 28:19] _T_6252 <= _T_6241 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][33] <= _T_6252 @[el2_ifu_mem_ctl.scala 740:39] - node _T_6253 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_6254 = eq(_T_6253, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_6255 = and(ic_valid_ff, _T_6254) @[el2_ifu_mem_ctl.scala 740:64] - node _T_6256 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_6257 = and(_T_6255, _T_6256) @[el2_ifu_mem_ctl.scala 740:89] - node _T_6258 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h022")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_6259 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_6260 = and(_T_6258, _T_6259) @[el2_ifu_mem_ctl.scala 741:58] - node _T_6261 = eq(perr_ic_index_ff, UInt<6>("h022")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_6262 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_6263 = and(_T_6261, _T_6262) @[el2_ifu_mem_ctl.scala 741:123] - node _T_6264 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_6265 = and(_T_6263, _T_6264) @[el2_ifu_mem_ctl.scala 741:144] - node _T_6266 = or(_T_6260, _T_6265) @[el2_ifu_mem_ctl.scala 741:80] - node _T_6267 = bits(_T_6266, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][33] <= _T_6252 @[el2_ifu_mem_ctl.scala 741:39] + node _T_6253 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_6254 = eq(_T_6253, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_6255 = and(ic_valid_ff, _T_6254) @[el2_ifu_mem_ctl.scala 741:64] + node _T_6256 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_6257 = and(_T_6255, _T_6256) @[el2_ifu_mem_ctl.scala 741:89] + node _T_6258 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h022")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_6259 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_6260 = and(_T_6258, _T_6259) @[el2_ifu_mem_ctl.scala 742:58] + node _T_6261 = eq(perr_ic_index_ff, UInt<6>("h022")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_6262 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_6263 = and(_T_6261, _T_6262) @[el2_ifu_mem_ctl.scala 742:123] + node _T_6264 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_6265 = and(_T_6263, _T_6264) @[el2_ifu_mem_ctl.scala 742:144] + node _T_6266 = or(_T_6260, _T_6265) @[el2_ifu_mem_ctl.scala 742:80] + node _T_6267 = bits(_T_6266, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_6268 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6267 : @[Reg.scala 28:19] _T_6268 <= _T_6257 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][34] <= _T_6268 @[el2_ifu_mem_ctl.scala 740:39] - node _T_6269 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_6270 = eq(_T_6269, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_6271 = and(ic_valid_ff, _T_6270) @[el2_ifu_mem_ctl.scala 740:64] - node _T_6272 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_6273 = and(_T_6271, _T_6272) @[el2_ifu_mem_ctl.scala 740:89] - node _T_6274 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h023")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_6275 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_6276 = and(_T_6274, _T_6275) @[el2_ifu_mem_ctl.scala 741:58] - node _T_6277 = eq(perr_ic_index_ff, UInt<6>("h023")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_6278 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_6279 = and(_T_6277, _T_6278) @[el2_ifu_mem_ctl.scala 741:123] - node _T_6280 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_6281 = and(_T_6279, _T_6280) @[el2_ifu_mem_ctl.scala 741:144] - node _T_6282 = or(_T_6276, _T_6281) @[el2_ifu_mem_ctl.scala 741:80] - node _T_6283 = bits(_T_6282, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][34] <= _T_6268 @[el2_ifu_mem_ctl.scala 741:39] + node _T_6269 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_6270 = eq(_T_6269, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_6271 = and(ic_valid_ff, _T_6270) @[el2_ifu_mem_ctl.scala 741:64] + node _T_6272 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_6273 = and(_T_6271, _T_6272) @[el2_ifu_mem_ctl.scala 741:89] + node _T_6274 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h023")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_6275 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_6276 = and(_T_6274, _T_6275) @[el2_ifu_mem_ctl.scala 742:58] + node _T_6277 = eq(perr_ic_index_ff, UInt<6>("h023")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_6278 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_6279 = and(_T_6277, _T_6278) @[el2_ifu_mem_ctl.scala 742:123] + node _T_6280 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_6281 = and(_T_6279, _T_6280) @[el2_ifu_mem_ctl.scala 742:144] + node _T_6282 = or(_T_6276, _T_6281) @[el2_ifu_mem_ctl.scala 742:80] + node _T_6283 = bits(_T_6282, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_6284 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6283 : @[Reg.scala 28:19] _T_6284 <= _T_6273 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][35] <= _T_6284 @[el2_ifu_mem_ctl.scala 740:39] - node _T_6285 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_6286 = eq(_T_6285, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_6287 = and(ic_valid_ff, _T_6286) @[el2_ifu_mem_ctl.scala 740:64] - node _T_6288 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_6289 = and(_T_6287, _T_6288) @[el2_ifu_mem_ctl.scala 740:89] - node _T_6290 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h024")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_6291 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_6292 = and(_T_6290, _T_6291) @[el2_ifu_mem_ctl.scala 741:58] - node _T_6293 = eq(perr_ic_index_ff, UInt<6>("h024")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_6294 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_6295 = and(_T_6293, _T_6294) @[el2_ifu_mem_ctl.scala 741:123] - node _T_6296 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_6297 = and(_T_6295, _T_6296) @[el2_ifu_mem_ctl.scala 741:144] - node _T_6298 = or(_T_6292, _T_6297) @[el2_ifu_mem_ctl.scala 741:80] - node _T_6299 = bits(_T_6298, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][35] <= _T_6284 @[el2_ifu_mem_ctl.scala 741:39] + node _T_6285 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_6286 = eq(_T_6285, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_6287 = and(ic_valid_ff, _T_6286) @[el2_ifu_mem_ctl.scala 741:64] + node _T_6288 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_6289 = and(_T_6287, _T_6288) @[el2_ifu_mem_ctl.scala 741:89] + node _T_6290 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h024")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_6291 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_6292 = and(_T_6290, _T_6291) @[el2_ifu_mem_ctl.scala 742:58] + node _T_6293 = eq(perr_ic_index_ff, UInt<6>("h024")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_6294 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_6295 = and(_T_6293, _T_6294) @[el2_ifu_mem_ctl.scala 742:123] + node _T_6296 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_6297 = and(_T_6295, _T_6296) @[el2_ifu_mem_ctl.scala 742:144] + node _T_6298 = or(_T_6292, _T_6297) @[el2_ifu_mem_ctl.scala 742:80] + node _T_6299 = bits(_T_6298, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_6300 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6299 : @[Reg.scala 28:19] _T_6300 <= _T_6289 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][36] <= _T_6300 @[el2_ifu_mem_ctl.scala 740:39] - node _T_6301 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_6302 = eq(_T_6301, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_6303 = and(ic_valid_ff, _T_6302) @[el2_ifu_mem_ctl.scala 740:64] - node _T_6304 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_6305 = and(_T_6303, _T_6304) @[el2_ifu_mem_ctl.scala 740:89] - node _T_6306 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h025")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_6307 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_6308 = and(_T_6306, _T_6307) @[el2_ifu_mem_ctl.scala 741:58] - node _T_6309 = eq(perr_ic_index_ff, UInt<6>("h025")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_6310 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_6311 = and(_T_6309, _T_6310) @[el2_ifu_mem_ctl.scala 741:123] - node _T_6312 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_6313 = and(_T_6311, _T_6312) @[el2_ifu_mem_ctl.scala 741:144] - node _T_6314 = or(_T_6308, _T_6313) @[el2_ifu_mem_ctl.scala 741:80] - node _T_6315 = bits(_T_6314, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][36] <= _T_6300 @[el2_ifu_mem_ctl.scala 741:39] + node _T_6301 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_6302 = eq(_T_6301, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_6303 = and(ic_valid_ff, _T_6302) @[el2_ifu_mem_ctl.scala 741:64] + node _T_6304 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_6305 = and(_T_6303, _T_6304) @[el2_ifu_mem_ctl.scala 741:89] + node _T_6306 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h025")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_6307 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_6308 = and(_T_6306, _T_6307) @[el2_ifu_mem_ctl.scala 742:58] + node _T_6309 = eq(perr_ic_index_ff, UInt<6>("h025")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_6310 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_6311 = and(_T_6309, _T_6310) @[el2_ifu_mem_ctl.scala 742:123] + node _T_6312 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_6313 = and(_T_6311, _T_6312) @[el2_ifu_mem_ctl.scala 742:144] + node _T_6314 = or(_T_6308, _T_6313) @[el2_ifu_mem_ctl.scala 742:80] + node _T_6315 = bits(_T_6314, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_6316 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6315 : @[Reg.scala 28:19] _T_6316 <= _T_6305 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][37] <= _T_6316 @[el2_ifu_mem_ctl.scala 740:39] - node _T_6317 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_6318 = eq(_T_6317, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_6319 = and(ic_valid_ff, _T_6318) @[el2_ifu_mem_ctl.scala 740:64] - node _T_6320 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_6321 = and(_T_6319, _T_6320) @[el2_ifu_mem_ctl.scala 740:89] - node _T_6322 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h026")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_6323 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_6324 = and(_T_6322, _T_6323) @[el2_ifu_mem_ctl.scala 741:58] - node _T_6325 = eq(perr_ic_index_ff, UInt<6>("h026")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_6326 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_6327 = and(_T_6325, _T_6326) @[el2_ifu_mem_ctl.scala 741:123] - node _T_6328 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_6329 = and(_T_6327, _T_6328) @[el2_ifu_mem_ctl.scala 741:144] - node _T_6330 = or(_T_6324, _T_6329) @[el2_ifu_mem_ctl.scala 741:80] - node _T_6331 = bits(_T_6330, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][37] <= _T_6316 @[el2_ifu_mem_ctl.scala 741:39] + node _T_6317 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_6318 = eq(_T_6317, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_6319 = and(ic_valid_ff, _T_6318) @[el2_ifu_mem_ctl.scala 741:64] + node _T_6320 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_6321 = and(_T_6319, _T_6320) @[el2_ifu_mem_ctl.scala 741:89] + node _T_6322 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h026")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_6323 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_6324 = and(_T_6322, _T_6323) @[el2_ifu_mem_ctl.scala 742:58] + node _T_6325 = eq(perr_ic_index_ff, UInt<6>("h026")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_6326 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_6327 = and(_T_6325, _T_6326) @[el2_ifu_mem_ctl.scala 742:123] + node _T_6328 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_6329 = and(_T_6327, _T_6328) @[el2_ifu_mem_ctl.scala 742:144] + node _T_6330 = or(_T_6324, _T_6329) @[el2_ifu_mem_ctl.scala 742:80] + node _T_6331 = bits(_T_6330, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_6332 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6331 : @[Reg.scala 28:19] _T_6332 <= _T_6321 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][38] <= _T_6332 @[el2_ifu_mem_ctl.scala 740:39] - node _T_6333 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_6334 = eq(_T_6333, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_6335 = and(ic_valid_ff, _T_6334) @[el2_ifu_mem_ctl.scala 740:64] - node _T_6336 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_6337 = and(_T_6335, _T_6336) @[el2_ifu_mem_ctl.scala 740:89] - node _T_6338 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h027")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_6339 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_6340 = and(_T_6338, _T_6339) @[el2_ifu_mem_ctl.scala 741:58] - node _T_6341 = eq(perr_ic_index_ff, UInt<6>("h027")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_6342 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_6343 = and(_T_6341, _T_6342) @[el2_ifu_mem_ctl.scala 741:123] - node _T_6344 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_6345 = and(_T_6343, _T_6344) @[el2_ifu_mem_ctl.scala 741:144] - node _T_6346 = or(_T_6340, _T_6345) @[el2_ifu_mem_ctl.scala 741:80] - node _T_6347 = bits(_T_6346, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][38] <= _T_6332 @[el2_ifu_mem_ctl.scala 741:39] + node _T_6333 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_6334 = eq(_T_6333, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_6335 = and(ic_valid_ff, _T_6334) @[el2_ifu_mem_ctl.scala 741:64] + node _T_6336 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_6337 = and(_T_6335, _T_6336) @[el2_ifu_mem_ctl.scala 741:89] + node _T_6338 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h027")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_6339 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_6340 = and(_T_6338, _T_6339) @[el2_ifu_mem_ctl.scala 742:58] + node _T_6341 = eq(perr_ic_index_ff, UInt<6>("h027")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_6342 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_6343 = and(_T_6341, _T_6342) @[el2_ifu_mem_ctl.scala 742:123] + node _T_6344 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_6345 = and(_T_6343, _T_6344) @[el2_ifu_mem_ctl.scala 742:144] + node _T_6346 = or(_T_6340, _T_6345) @[el2_ifu_mem_ctl.scala 742:80] + node _T_6347 = bits(_T_6346, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_6348 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6347 : @[Reg.scala 28:19] _T_6348 <= _T_6337 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][39] <= _T_6348 @[el2_ifu_mem_ctl.scala 740:39] - node _T_6349 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_6350 = eq(_T_6349, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_6351 = and(ic_valid_ff, _T_6350) @[el2_ifu_mem_ctl.scala 740:64] - node _T_6352 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_6353 = and(_T_6351, _T_6352) @[el2_ifu_mem_ctl.scala 740:89] - node _T_6354 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h028")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_6355 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_6356 = and(_T_6354, _T_6355) @[el2_ifu_mem_ctl.scala 741:58] - node _T_6357 = eq(perr_ic_index_ff, UInt<6>("h028")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_6358 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_6359 = and(_T_6357, _T_6358) @[el2_ifu_mem_ctl.scala 741:123] - node _T_6360 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_6361 = and(_T_6359, _T_6360) @[el2_ifu_mem_ctl.scala 741:144] - node _T_6362 = or(_T_6356, _T_6361) @[el2_ifu_mem_ctl.scala 741:80] - node _T_6363 = bits(_T_6362, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][39] <= _T_6348 @[el2_ifu_mem_ctl.scala 741:39] + node _T_6349 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_6350 = eq(_T_6349, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_6351 = and(ic_valid_ff, _T_6350) @[el2_ifu_mem_ctl.scala 741:64] + node _T_6352 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_6353 = and(_T_6351, _T_6352) @[el2_ifu_mem_ctl.scala 741:89] + node _T_6354 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h028")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_6355 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_6356 = and(_T_6354, _T_6355) @[el2_ifu_mem_ctl.scala 742:58] + node _T_6357 = eq(perr_ic_index_ff, UInt<6>("h028")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_6358 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_6359 = and(_T_6357, _T_6358) @[el2_ifu_mem_ctl.scala 742:123] + node _T_6360 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_6361 = and(_T_6359, _T_6360) @[el2_ifu_mem_ctl.scala 742:144] + node _T_6362 = or(_T_6356, _T_6361) @[el2_ifu_mem_ctl.scala 742:80] + node _T_6363 = bits(_T_6362, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_6364 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6363 : @[Reg.scala 28:19] _T_6364 <= _T_6353 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][40] <= _T_6364 @[el2_ifu_mem_ctl.scala 740:39] - node _T_6365 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_6366 = eq(_T_6365, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_6367 = and(ic_valid_ff, _T_6366) @[el2_ifu_mem_ctl.scala 740:64] - node _T_6368 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_6369 = and(_T_6367, _T_6368) @[el2_ifu_mem_ctl.scala 740:89] - node _T_6370 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h029")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_6371 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_6372 = and(_T_6370, _T_6371) @[el2_ifu_mem_ctl.scala 741:58] - node _T_6373 = eq(perr_ic_index_ff, UInt<6>("h029")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_6374 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_6375 = and(_T_6373, _T_6374) @[el2_ifu_mem_ctl.scala 741:123] - node _T_6376 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_6377 = and(_T_6375, _T_6376) @[el2_ifu_mem_ctl.scala 741:144] - node _T_6378 = or(_T_6372, _T_6377) @[el2_ifu_mem_ctl.scala 741:80] - node _T_6379 = bits(_T_6378, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][40] <= _T_6364 @[el2_ifu_mem_ctl.scala 741:39] + node _T_6365 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_6366 = eq(_T_6365, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_6367 = and(ic_valid_ff, _T_6366) @[el2_ifu_mem_ctl.scala 741:64] + node _T_6368 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_6369 = and(_T_6367, _T_6368) @[el2_ifu_mem_ctl.scala 741:89] + node _T_6370 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h029")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_6371 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_6372 = and(_T_6370, _T_6371) @[el2_ifu_mem_ctl.scala 742:58] + node _T_6373 = eq(perr_ic_index_ff, UInt<6>("h029")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_6374 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_6375 = and(_T_6373, _T_6374) @[el2_ifu_mem_ctl.scala 742:123] + node _T_6376 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_6377 = and(_T_6375, _T_6376) @[el2_ifu_mem_ctl.scala 742:144] + node _T_6378 = or(_T_6372, _T_6377) @[el2_ifu_mem_ctl.scala 742:80] + node _T_6379 = bits(_T_6378, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_6380 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6379 : @[Reg.scala 28:19] _T_6380 <= _T_6369 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][41] <= _T_6380 @[el2_ifu_mem_ctl.scala 740:39] - node _T_6381 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_6382 = eq(_T_6381, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_6383 = and(ic_valid_ff, _T_6382) @[el2_ifu_mem_ctl.scala 740:64] - node _T_6384 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_6385 = and(_T_6383, _T_6384) @[el2_ifu_mem_ctl.scala 740:89] - node _T_6386 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02a")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_6387 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_6388 = and(_T_6386, _T_6387) @[el2_ifu_mem_ctl.scala 741:58] - node _T_6389 = eq(perr_ic_index_ff, UInt<6>("h02a")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_6390 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_6391 = and(_T_6389, _T_6390) @[el2_ifu_mem_ctl.scala 741:123] - node _T_6392 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_6393 = and(_T_6391, _T_6392) @[el2_ifu_mem_ctl.scala 741:144] - node _T_6394 = or(_T_6388, _T_6393) @[el2_ifu_mem_ctl.scala 741:80] - node _T_6395 = bits(_T_6394, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][41] <= _T_6380 @[el2_ifu_mem_ctl.scala 741:39] + node _T_6381 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_6382 = eq(_T_6381, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_6383 = and(ic_valid_ff, _T_6382) @[el2_ifu_mem_ctl.scala 741:64] + node _T_6384 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_6385 = and(_T_6383, _T_6384) @[el2_ifu_mem_ctl.scala 741:89] + node _T_6386 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02a")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_6387 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_6388 = and(_T_6386, _T_6387) @[el2_ifu_mem_ctl.scala 742:58] + node _T_6389 = eq(perr_ic_index_ff, UInt<6>("h02a")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_6390 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_6391 = and(_T_6389, _T_6390) @[el2_ifu_mem_ctl.scala 742:123] + node _T_6392 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_6393 = and(_T_6391, _T_6392) @[el2_ifu_mem_ctl.scala 742:144] + node _T_6394 = or(_T_6388, _T_6393) @[el2_ifu_mem_ctl.scala 742:80] + node _T_6395 = bits(_T_6394, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_6396 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6395 : @[Reg.scala 28:19] _T_6396 <= _T_6385 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][42] <= _T_6396 @[el2_ifu_mem_ctl.scala 740:39] - node _T_6397 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_6398 = eq(_T_6397, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_6399 = and(ic_valid_ff, _T_6398) @[el2_ifu_mem_ctl.scala 740:64] - node _T_6400 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_6401 = and(_T_6399, _T_6400) @[el2_ifu_mem_ctl.scala 740:89] - node _T_6402 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02b")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_6403 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_6404 = and(_T_6402, _T_6403) @[el2_ifu_mem_ctl.scala 741:58] - node _T_6405 = eq(perr_ic_index_ff, UInt<6>("h02b")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_6406 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_6407 = and(_T_6405, _T_6406) @[el2_ifu_mem_ctl.scala 741:123] - node _T_6408 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_6409 = and(_T_6407, _T_6408) @[el2_ifu_mem_ctl.scala 741:144] - node _T_6410 = or(_T_6404, _T_6409) @[el2_ifu_mem_ctl.scala 741:80] - node _T_6411 = bits(_T_6410, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][42] <= _T_6396 @[el2_ifu_mem_ctl.scala 741:39] + node _T_6397 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_6398 = eq(_T_6397, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_6399 = and(ic_valid_ff, _T_6398) @[el2_ifu_mem_ctl.scala 741:64] + node _T_6400 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_6401 = and(_T_6399, _T_6400) @[el2_ifu_mem_ctl.scala 741:89] + node _T_6402 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02b")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_6403 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_6404 = and(_T_6402, _T_6403) @[el2_ifu_mem_ctl.scala 742:58] + node _T_6405 = eq(perr_ic_index_ff, UInt<6>("h02b")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_6406 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_6407 = and(_T_6405, _T_6406) @[el2_ifu_mem_ctl.scala 742:123] + node _T_6408 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_6409 = and(_T_6407, _T_6408) @[el2_ifu_mem_ctl.scala 742:144] + node _T_6410 = or(_T_6404, _T_6409) @[el2_ifu_mem_ctl.scala 742:80] + node _T_6411 = bits(_T_6410, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_6412 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6411 : @[Reg.scala 28:19] _T_6412 <= _T_6401 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][43] <= _T_6412 @[el2_ifu_mem_ctl.scala 740:39] - node _T_6413 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_6414 = eq(_T_6413, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_6415 = and(ic_valid_ff, _T_6414) @[el2_ifu_mem_ctl.scala 740:64] - node _T_6416 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_6417 = and(_T_6415, _T_6416) @[el2_ifu_mem_ctl.scala 740:89] - node _T_6418 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02c")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_6419 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_6420 = and(_T_6418, _T_6419) @[el2_ifu_mem_ctl.scala 741:58] - node _T_6421 = eq(perr_ic_index_ff, UInt<6>("h02c")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_6422 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_6423 = and(_T_6421, _T_6422) @[el2_ifu_mem_ctl.scala 741:123] - node _T_6424 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_6425 = and(_T_6423, _T_6424) @[el2_ifu_mem_ctl.scala 741:144] - node _T_6426 = or(_T_6420, _T_6425) @[el2_ifu_mem_ctl.scala 741:80] - node _T_6427 = bits(_T_6426, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][43] <= _T_6412 @[el2_ifu_mem_ctl.scala 741:39] + node _T_6413 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_6414 = eq(_T_6413, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_6415 = and(ic_valid_ff, _T_6414) @[el2_ifu_mem_ctl.scala 741:64] + node _T_6416 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_6417 = and(_T_6415, _T_6416) @[el2_ifu_mem_ctl.scala 741:89] + node _T_6418 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02c")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_6419 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_6420 = and(_T_6418, _T_6419) @[el2_ifu_mem_ctl.scala 742:58] + node _T_6421 = eq(perr_ic_index_ff, UInt<6>("h02c")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_6422 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_6423 = and(_T_6421, _T_6422) @[el2_ifu_mem_ctl.scala 742:123] + node _T_6424 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_6425 = and(_T_6423, _T_6424) @[el2_ifu_mem_ctl.scala 742:144] + node _T_6426 = or(_T_6420, _T_6425) @[el2_ifu_mem_ctl.scala 742:80] + node _T_6427 = bits(_T_6426, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_6428 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6427 : @[Reg.scala 28:19] _T_6428 <= _T_6417 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][44] <= _T_6428 @[el2_ifu_mem_ctl.scala 740:39] - node _T_6429 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_6430 = eq(_T_6429, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_6431 = and(ic_valid_ff, _T_6430) @[el2_ifu_mem_ctl.scala 740:64] - node _T_6432 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_6433 = and(_T_6431, _T_6432) @[el2_ifu_mem_ctl.scala 740:89] - node _T_6434 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02d")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_6435 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_6436 = and(_T_6434, _T_6435) @[el2_ifu_mem_ctl.scala 741:58] - node _T_6437 = eq(perr_ic_index_ff, UInt<6>("h02d")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_6438 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_6439 = and(_T_6437, _T_6438) @[el2_ifu_mem_ctl.scala 741:123] - node _T_6440 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_6441 = and(_T_6439, _T_6440) @[el2_ifu_mem_ctl.scala 741:144] - node _T_6442 = or(_T_6436, _T_6441) @[el2_ifu_mem_ctl.scala 741:80] - node _T_6443 = bits(_T_6442, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][44] <= _T_6428 @[el2_ifu_mem_ctl.scala 741:39] + node _T_6429 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_6430 = eq(_T_6429, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_6431 = and(ic_valid_ff, _T_6430) @[el2_ifu_mem_ctl.scala 741:64] + node _T_6432 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_6433 = and(_T_6431, _T_6432) @[el2_ifu_mem_ctl.scala 741:89] + node _T_6434 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02d")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_6435 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_6436 = and(_T_6434, _T_6435) @[el2_ifu_mem_ctl.scala 742:58] + node _T_6437 = eq(perr_ic_index_ff, UInt<6>("h02d")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_6438 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_6439 = and(_T_6437, _T_6438) @[el2_ifu_mem_ctl.scala 742:123] + node _T_6440 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_6441 = and(_T_6439, _T_6440) @[el2_ifu_mem_ctl.scala 742:144] + node _T_6442 = or(_T_6436, _T_6441) @[el2_ifu_mem_ctl.scala 742:80] + node _T_6443 = bits(_T_6442, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_6444 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6443 : @[Reg.scala 28:19] _T_6444 <= _T_6433 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][45] <= _T_6444 @[el2_ifu_mem_ctl.scala 740:39] - node _T_6445 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_6446 = eq(_T_6445, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_6447 = and(ic_valid_ff, _T_6446) @[el2_ifu_mem_ctl.scala 740:64] - node _T_6448 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_6449 = and(_T_6447, _T_6448) @[el2_ifu_mem_ctl.scala 740:89] - node _T_6450 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02e")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_6451 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_6452 = and(_T_6450, _T_6451) @[el2_ifu_mem_ctl.scala 741:58] - node _T_6453 = eq(perr_ic_index_ff, UInt<6>("h02e")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_6454 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_6455 = and(_T_6453, _T_6454) @[el2_ifu_mem_ctl.scala 741:123] - node _T_6456 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_6457 = and(_T_6455, _T_6456) @[el2_ifu_mem_ctl.scala 741:144] - node _T_6458 = or(_T_6452, _T_6457) @[el2_ifu_mem_ctl.scala 741:80] - node _T_6459 = bits(_T_6458, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][45] <= _T_6444 @[el2_ifu_mem_ctl.scala 741:39] + node _T_6445 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_6446 = eq(_T_6445, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_6447 = and(ic_valid_ff, _T_6446) @[el2_ifu_mem_ctl.scala 741:64] + node _T_6448 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_6449 = and(_T_6447, _T_6448) @[el2_ifu_mem_ctl.scala 741:89] + node _T_6450 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02e")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_6451 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_6452 = and(_T_6450, _T_6451) @[el2_ifu_mem_ctl.scala 742:58] + node _T_6453 = eq(perr_ic_index_ff, UInt<6>("h02e")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_6454 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_6455 = and(_T_6453, _T_6454) @[el2_ifu_mem_ctl.scala 742:123] + node _T_6456 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_6457 = and(_T_6455, _T_6456) @[el2_ifu_mem_ctl.scala 742:144] + node _T_6458 = or(_T_6452, _T_6457) @[el2_ifu_mem_ctl.scala 742:80] + node _T_6459 = bits(_T_6458, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_6460 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6459 : @[Reg.scala 28:19] _T_6460 <= _T_6449 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][46] <= _T_6460 @[el2_ifu_mem_ctl.scala 740:39] - node _T_6461 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_6462 = eq(_T_6461, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_6463 = and(ic_valid_ff, _T_6462) @[el2_ifu_mem_ctl.scala 740:64] - node _T_6464 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_6465 = and(_T_6463, _T_6464) @[el2_ifu_mem_ctl.scala 740:89] - node _T_6466 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02f")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_6467 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_6468 = and(_T_6466, _T_6467) @[el2_ifu_mem_ctl.scala 741:58] - node _T_6469 = eq(perr_ic_index_ff, UInt<6>("h02f")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_6470 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_6471 = and(_T_6469, _T_6470) @[el2_ifu_mem_ctl.scala 741:123] - node _T_6472 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_6473 = and(_T_6471, _T_6472) @[el2_ifu_mem_ctl.scala 741:144] - node _T_6474 = or(_T_6468, _T_6473) @[el2_ifu_mem_ctl.scala 741:80] - node _T_6475 = bits(_T_6474, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][46] <= _T_6460 @[el2_ifu_mem_ctl.scala 741:39] + node _T_6461 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_6462 = eq(_T_6461, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_6463 = and(ic_valid_ff, _T_6462) @[el2_ifu_mem_ctl.scala 741:64] + node _T_6464 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_6465 = and(_T_6463, _T_6464) @[el2_ifu_mem_ctl.scala 741:89] + node _T_6466 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02f")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_6467 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_6468 = and(_T_6466, _T_6467) @[el2_ifu_mem_ctl.scala 742:58] + node _T_6469 = eq(perr_ic_index_ff, UInt<6>("h02f")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_6470 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_6471 = and(_T_6469, _T_6470) @[el2_ifu_mem_ctl.scala 742:123] + node _T_6472 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_6473 = and(_T_6471, _T_6472) @[el2_ifu_mem_ctl.scala 742:144] + node _T_6474 = or(_T_6468, _T_6473) @[el2_ifu_mem_ctl.scala 742:80] + node _T_6475 = bits(_T_6474, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_6476 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6475 : @[Reg.scala 28:19] _T_6476 <= _T_6465 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][47] <= _T_6476 @[el2_ifu_mem_ctl.scala 740:39] - node _T_6477 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_6478 = eq(_T_6477, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_6479 = and(ic_valid_ff, _T_6478) @[el2_ifu_mem_ctl.scala 740:64] - node _T_6480 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_6481 = and(_T_6479, _T_6480) @[el2_ifu_mem_ctl.scala 740:89] - node _T_6482 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h030")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_6483 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_6484 = and(_T_6482, _T_6483) @[el2_ifu_mem_ctl.scala 741:58] - node _T_6485 = eq(perr_ic_index_ff, UInt<6>("h030")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_6486 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_6487 = and(_T_6485, _T_6486) @[el2_ifu_mem_ctl.scala 741:123] - node _T_6488 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_6489 = and(_T_6487, _T_6488) @[el2_ifu_mem_ctl.scala 741:144] - node _T_6490 = or(_T_6484, _T_6489) @[el2_ifu_mem_ctl.scala 741:80] - node _T_6491 = bits(_T_6490, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][47] <= _T_6476 @[el2_ifu_mem_ctl.scala 741:39] + node _T_6477 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_6478 = eq(_T_6477, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_6479 = and(ic_valid_ff, _T_6478) @[el2_ifu_mem_ctl.scala 741:64] + node _T_6480 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_6481 = and(_T_6479, _T_6480) @[el2_ifu_mem_ctl.scala 741:89] + node _T_6482 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h030")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_6483 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_6484 = and(_T_6482, _T_6483) @[el2_ifu_mem_ctl.scala 742:58] + node _T_6485 = eq(perr_ic_index_ff, UInt<6>("h030")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_6486 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_6487 = and(_T_6485, _T_6486) @[el2_ifu_mem_ctl.scala 742:123] + node _T_6488 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_6489 = and(_T_6487, _T_6488) @[el2_ifu_mem_ctl.scala 742:144] + node _T_6490 = or(_T_6484, _T_6489) @[el2_ifu_mem_ctl.scala 742:80] + node _T_6491 = bits(_T_6490, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_6492 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6491 : @[Reg.scala 28:19] _T_6492 <= _T_6481 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][48] <= _T_6492 @[el2_ifu_mem_ctl.scala 740:39] - node _T_6493 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_6494 = eq(_T_6493, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_6495 = and(ic_valid_ff, _T_6494) @[el2_ifu_mem_ctl.scala 740:64] - node _T_6496 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_6497 = and(_T_6495, _T_6496) @[el2_ifu_mem_ctl.scala 740:89] - node _T_6498 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h031")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_6499 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_6500 = and(_T_6498, _T_6499) @[el2_ifu_mem_ctl.scala 741:58] - node _T_6501 = eq(perr_ic_index_ff, UInt<6>("h031")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_6502 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_6503 = and(_T_6501, _T_6502) @[el2_ifu_mem_ctl.scala 741:123] - node _T_6504 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_6505 = and(_T_6503, _T_6504) @[el2_ifu_mem_ctl.scala 741:144] - node _T_6506 = or(_T_6500, _T_6505) @[el2_ifu_mem_ctl.scala 741:80] - node _T_6507 = bits(_T_6506, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][48] <= _T_6492 @[el2_ifu_mem_ctl.scala 741:39] + node _T_6493 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_6494 = eq(_T_6493, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_6495 = and(ic_valid_ff, _T_6494) @[el2_ifu_mem_ctl.scala 741:64] + node _T_6496 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_6497 = and(_T_6495, _T_6496) @[el2_ifu_mem_ctl.scala 741:89] + node _T_6498 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h031")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_6499 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_6500 = and(_T_6498, _T_6499) @[el2_ifu_mem_ctl.scala 742:58] + node _T_6501 = eq(perr_ic_index_ff, UInt<6>("h031")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_6502 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_6503 = and(_T_6501, _T_6502) @[el2_ifu_mem_ctl.scala 742:123] + node _T_6504 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_6505 = and(_T_6503, _T_6504) @[el2_ifu_mem_ctl.scala 742:144] + node _T_6506 = or(_T_6500, _T_6505) @[el2_ifu_mem_ctl.scala 742:80] + node _T_6507 = bits(_T_6506, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_6508 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6507 : @[Reg.scala 28:19] _T_6508 <= _T_6497 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][49] <= _T_6508 @[el2_ifu_mem_ctl.scala 740:39] - node _T_6509 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_6510 = eq(_T_6509, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_6511 = and(ic_valid_ff, _T_6510) @[el2_ifu_mem_ctl.scala 740:64] - node _T_6512 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_6513 = and(_T_6511, _T_6512) @[el2_ifu_mem_ctl.scala 740:89] - node _T_6514 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h032")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_6515 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_6516 = and(_T_6514, _T_6515) @[el2_ifu_mem_ctl.scala 741:58] - node _T_6517 = eq(perr_ic_index_ff, UInt<6>("h032")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_6518 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_6519 = and(_T_6517, _T_6518) @[el2_ifu_mem_ctl.scala 741:123] - node _T_6520 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_6521 = and(_T_6519, _T_6520) @[el2_ifu_mem_ctl.scala 741:144] - node _T_6522 = or(_T_6516, _T_6521) @[el2_ifu_mem_ctl.scala 741:80] - node _T_6523 = bits(_T_6522, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][49] <= _T_6508 @[el2_ifu_mem_ctl.scala 741:39] + node _T_6509 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_6510 = eq(_T_6509, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_6511 = and(ic_valid_ff, _T_6510) @[el2_ifu_mem_ctl.scala 741:64] + node _T_6512 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_6513 = and(_T_6511, _T_6512) @[el2_ifu_mem_ctl.scala 741:89] + node _T_6514 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h032")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_6515 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_6516 = and(_T_6514, _T_6515) @[el2_ifu_mem_ctl.scala 742:58] + node _T_6517 = eq(perr_ic_index_ff, UInt<6>("h032")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_6518 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_6519 = and(_T_6517, _T_6518) @[el2_ifu_mem_ctl.scala 742:123] + node _T_6520 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_6521 = and(_T_6519, _T_6520) @[el2_ifu_mem_ctl.scala 742:144] + node _T_6522 = or(_T_6516, _T_6521) @[el2_ifu_mem_ctl.scala 742:80] + node _T_6523 = bits(_T_6522, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_6524 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6523 : @[Reg.scala 28:19] _T_6524 <= _T_6513 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][50] <= _T_6524 @[el2_ifu_mem_ctl.scala 740:39] - node _T_6525 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_6526 = eq(_T_6525, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_6527 = and(ic_valid_ff, _T_6526) @[el2_ifu_mem_ctl.scala 740:64] - node _T_6528 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_6529 = and(_T_6527, _T_6528) @[el2_ifu_mem_ctl.scala 740:89] - node _T_6530 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h033")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_6531 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_6532 = and(_T_6530, _T_6531) @[el2_ifu_mem_ctl.scala 741:58] - node _T_6533 = eq(perr_ic_index_ff, UInt<6>("h033")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_6534 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_6535 = and(_T_6533, _T_6534) @[el2_ifu_mem_ctl.scala 741:123] - node _T_6536 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_6537 = and(_T_6535, _T_6536) @[el2_ifu_mem_ctl.scala 741:144] - node _T_6538 = or(_T_6532, _T_6537) @[el2_ifu_mem_ctl.scala 741:80] - node _T_6539 = bits(_T_6538, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][50] <= _T_6524 @[el2_ifu_mem_ctl.scala 741:39] + node _T_6525 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_6526 = eq(_T_6525, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_6527 = and(ic_valid_ff, _T_6526) @[el2_ifu_mem_ctl.scala 741:64] + node _T_6528 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_6529 = and(_T_6527, _T_6528) @[el2_ifu_mem_ctl.scala 741:89] + node _T_6530 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h033")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_6531 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_6532 = and(_T_6530, _T_6531) @[el2_ifu_mem_ctl.scala 742:58] + node _T_6533 = eq(perr_ic_index_ff, UInt<6>("h033")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_6534 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_6535 = and(_T_6533, _T_6534) @[el2_ifu_mem_ctl.scala 742:123] + node _T_6536 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_6537 = and(_T_6535, _T_6536) @[el2_ifu_mem_ctl.scala 742:144] + node _T_6538 = or(_T_6532, _T_6537) @[el2_ifu_mem_ctl.scala 742:80] + node _T_6539 = bits(_T_6538, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_6540 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6539 : @[Reg.scala 28:19] _T_6540 <= _T_6529 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][51] <= _T_6540 @[el2_ifu_mem_ctl.scala 740:39] - node _T_6541 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_6542 = eq(_T_6541, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_6543 = and(ic_valid_ff, _T_6542) @[el2_ifu_mem_ctl.scala 740:64] - node _T_6544 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_6545 = and(_T_6543, _T_6544) @[el2_ifu_mem_ctl.scala 740:89] - node _T_6546 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h034")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_6547 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_6548 = and(_T_6546, _T_6547) @[el2_ifu_mem_ctl.scala 741:58] - node _T_6549 = eq(perr_ic_index_ff, UInt<6>("h034")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_6550 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_6551 = and(_T_6549, _T_6550) @[el2_ifu_mem_ctl.scala 741:123] - node _T_6552 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_6553 = and(_T_6551, _T_6552) @[el2_ifu_mem_ctl.scala 741:144] - node _T_6554 = or(_T_6548, _T_6553) @[el2_ifu_mem_ctl.scala 741:80] - node _T_6555 = bits(_T_6554, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][51] <= _T_6540 @[el2_ifu_mem_ctl.scala 741:39] + node _T_6541 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_6542 = eq(_T_6541, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_6543 = and(ic_valid_ff, _T_6542) @[el2_ifu_mem_ctl.scala 741:64] + node _T_6544 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_6545 = and(_T_6543, _T_6544) @[el2_ifu_mem_ctl.scala 741:89] + node _T_6546 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h034")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_6547 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_6548 = and(_T_6546, _T_6547) @[el2_ifu_mem_ctl.scala 742:58] + node _T_6549 = eq(perr_ic_index_ff, UInt<6>("h034")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_6550 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_6551 = and(_T_6549, _T_6550) @[el2_ifu_mem_ctl.scala 742:123] + node _T_6552 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_6553 = and(_T_6551, _T_6552) @[el2_ifu_mem_ctl.scala 742:144] + node _T_6554 = or(_T_6548, _T_6553) @[el2_ifu_mem_ctl.scala 742:80] + node _T_6555 = bits(_T_6554, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_6556 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6555 : @[Reg.scala 28:19] _T_6556 <= _T_6545 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][52] <= _T_6556 @[el2_ifu_mem_ctl.scala 740:39] - node _T_6557 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_6558 = eq(_T_6557, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_6559 = and(ic_valid_ff, _T_6558) @[el2_ifu_mem_ctl.scala 740:64] - node _T_6560 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_6561 = and(_T_6559, _T_6560) @[el2_ifu_mem_ctl.scala 740:89] - node _T_6562 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h035")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_6563 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_6564 = and(_T_6562, _T_6563) @[el2_ifu_mem_ctl.scala 741:58] - node _T_6565 = eq(perr_ic_index_ff, UInt<6>("h035")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_6566 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_6567 = and(_T_6565, _T_6566) @[el2_ifu_mem_ctl.scala 741:123] - node _T_6568 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_6569 = and(_T_6567, _T_6568) @[el2_ifu_mem_ctl.scala 741:144] - node _T_6570 = or(_T_6564, _T_6569) @[el2_ifu_mem_ctl.scala 741:80] - node _T_6571 = bits(_T_6570, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][52] <= _T_6556 @[el2_ifu_mem_ctl.scala 741:39] + node _T_6557 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_6558 = eq(_T_6557, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_6559 = and(ic_valid_ff, _T_6558) @[el2_ifu_mem_ctl.scala 741:64] + node _T_6560 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_6561 = and(_T_6559, _T_6560) @[el2_ifu_mem_ctl.scala 741:89] + node _T_6562 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h035")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_6563 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_6564 = and(_T_6562, _T_6563) @[el2_ifu_mem_ctl.scala 742:58] + node _T_6565 = eq(perr_ic_index_ff, UInt<6>("h035")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_6566 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_6567 = and(_T_6565, _T_6566) @[el2_ifu_mem_ctl.scala 742:123] + node _T_6568 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_6569 = and(_T_6567, _T_6568) @[el2_ifu_mem_ctl.scala 742:144] + node _T_6570 = or(_T_6564, _T_6569) @[el2_ifu_mem_ctl.scala 742:80] + node _T_6571 = bits(_T_6570, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_6572 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6571 : @[Reg.scala 28:19] _T_6572 <= _T_6561 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][53] <= _T_6572 @[el2_ifu_mem_ctl.scala 740:39] - node _T_6573 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_6574 = eq(_T_6573, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_6575 = and(ic_valid_ff, _T_6574) @[el2_ifu_mem_ctl.scala 740:64] - node _T_6576 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_6577 = and(_T_6575, _T_6576) @[el2_ifu_mem_ctl.scala 740:89] - node _T_6578 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h036")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_6579 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_6580 = and(_T_6578, _T_6579) @[el2_ifu_mem_ctl.scala 741:58] - node _T_6581 = eq(perr_ic_index_ff, UInt<6>("h036")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_6582 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_6583 = and(_T_6581, _T_6582) @[el2_ifu_mem_ctl.scala 741:123] - node _T_6584 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_6585 = and(_T_6583, _T_6584) @[el2_ifu_mem_ctl.scala 741:144] - node _T_6586 = or(_T_6580, _T_6585) @[el2_ifu_mem_ctl.scala 741:80] - node _T_6587 = bits(_T_6586, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][53] <= _T_6572 @[el2_ifu_mem_ctl.scala 741:39] + node _T_6573 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_6574 = eq(_T_6573, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_6575 = and(ic_valid_ff, _T_6574) @[el2_ifu_mem_ctl.scala 741:64] + node _T_6576 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_6577 = and(_T_6575, _T_6576) @[el2_ifu_mem_ctl.scala 741:89] + node _T_6578 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h036")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_6579 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_6580 = and(_T_6578, _T_6579) @[el2_ifu_mem_ctl.scala 742:58] + node _T_6581 = eq(perr_ic_index_ff, UInt<6>("h036")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_6582 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_6583 = and(_T_6581, _T_6582) @[el2_ifu_mem_ctl.scala 742:123] + node _T_6584 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_6585 = and(_T_6583, _T_6584) @[el2_ifu_mem_ctl.scala 742:144] + node _T_6586 = or(_T_6580, _T_6585) @[el2_ifu_mem_ctl.scala 742:80] + node _T_6587 = bits(_T_6586, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_6588 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6587 : @[Reg.scala 28:19] _T_6588 <= _T_6577 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][54] <= _T_6588 @[el2_ifu_mem_ctl.scala 740:39] - node _T_6589 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_6590 = eq(_T_6589, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_6591 = and(ic_valid_ff, _T_6590) @[el2_ifu_mem_ctl.scala 740:64] - node _T_6592 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_6593 = and(_T_6591, _T_6592) @[el2_ifu_mem_ctl.scala 740:89] - node _T_6594 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h037")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_6595 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_6596 = and(_T_6594, _T_6595) @[el2_ifu_mem_ctl.scala 741:58] - node _T_6597 = eq(perr_ic_index_ff, UInt<6>("h037")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_6598 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_6599 = and(_T_6597, _T_6598) @[el2_ifu_mem_ctl.scala 741:123] - node _T_6600 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_6601 = and(_T_6599, _T_6600) @[el2_ifu_mem_ctl.scala 741:144] - node _T_6602 = or(_T_6596, _T_6601) @[el2_ifu_mem_ctl.scala 741:80] - node _T_6603 = bits(_T_6602, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][54] <= _T_6588 @[el2_ifu_mem_ctl.scala 741:39] + node _T_6589 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_6590 = eq(_T_6589, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_6591 = and(ic_valid_ff, _T_6590) @[el2_ifu_mem_ctl.scala 741:64] + node _T_6592 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_6593 = and(_T_6591, _T_6592) @[el2_ifu_mem_ctl.scala 741:89] + node _T_6594 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h037")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_6595 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_6596 = and(_T_6594, _T_6595) @[el2_ifu_mem_ctl.scala 742:58] + node _T_6597 = eq(perr_ic_index_ff, UInt<6>("h037")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_6598 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_6599 = and(_T_6597, _T_6598) @[el2_ifu_mem_ctl.scala 742:123] + node _T_6600 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_6601 = and(_T_6599, _T_6600) @[el2_ifu_mem_ctl.scala 742:144] + node _T_6602 = or(_T_6596, _T_6601) @[el2_ifu_mem_ctl.scala 742:80] + node _T_6603 = bits(_T_6602, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_6604 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6603 : @[Reg.scala 28:19] _T_6604 <= _T_6593 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][55] <= _T_6604 @[el2_ifu_mem_ctl.scala 740:39] - node _T_6605 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_6606 = eq(_T_6605, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_6607 = and(ic_valid_ff, _T_6606) @[el2_ifu_mem_ctl.scala 740:64] - node _T_6608 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_6609 = and(_T_6607, _T_6608) @[el2_ifu_mem_ctl.scala 740:89] - node _T_6610 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h038")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_6611 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_6612 = and(_T_6610, _T_6611) @[el2_ifu_mem_ctl.scala 741:58] - node _T_6613 = eq(perr_ic_index_ff, UInt<6>("h038")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_6614 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_6615 = and(_T_6613, _T_6614) @[el2_ifu_mem_ctl.scala 741:123] - node _T_6616 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_6617 = and(_T_6615, _T_6616) @[el2_ifu_mem_ctl.scala 741:144] - node _T_6618 = or(_T_6612, _T_6617) @[el2_ifu_mem_ctl.scala 741:80] - node _T_6619 = bits(_T_6618, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][55] <= _T_6604 @[el2_ifu_mem_ctl.scala 741:39] + node _T_6605 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_6606 = eq(_T_6605, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_6607 = and(ic_valid_ff, _T_6606) @[el2_ifu_mem_ctl.scala 741:64] + node _T_6608 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_6609 = and(_T_6607, _T_6608) @[el2_ifu_mem_ctl.scala 741:89] + node _T_6610 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h038")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_6611 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_6612 = and(_T_6610, _T_6611) @[el2_ifu_mem_ctl.scala 742:58] + node _T_6613 = eq(perr_ic_index_ff, UInt<6>("h038")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_6614 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_6615 = and(_T_6613, _T_6614) @[el2_ifu_mem_ctl.scala 742:123] + node _T_6616 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_6617 = and(_T_6615, _T_6616) @[el2_ifu_mem_ctl.scala 742:144] + node _T_6618 = or(_T_6612, _T_6617) @[el2_ifu_mem_ctl.scala 742:80] + node _T_6619 = bits(_T_6618, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_6620 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6619 : @[Reg.scala 28:19] _T_6620 <= _T_6609 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][56] <= _T_6620 @[el2_ifu_mem_ctl.scala 740:39] - node _T_6621 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_6622 = eq(_T_6621, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_6623 = and(ic_valid_ff, _T_6622) @[el2_ifu_mem_ctl.scala 740:64] - node _T_6624 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_6625 = and(_T_6623, _T_6624) @[el2_ifu_mem_ctl.scala 740:89] - node _T_6626 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h039")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_6627 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_6628 = and(_T_6626, _T_6627) @[el2_ifu_mem_ctl.scala 741:58] - node _T_6629 = eq(perr_ic_index_ff, UInt<6>("h039")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_6630 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_6631 = and(_T_6629, _T_6630) @[el2_ifu_mem_ctl.scala 741:123] - node _T_6632 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_6633 = and(_T_6631, _T_6632) @[el2_ifu_mem_ctl.scala 741:144] - node _T_6634 = or(_T_6628, _T_6633) @[el2_ifu_mem_ctl.scala 741:80] - node _T_6635 = bits(_T_6634, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][56] <= _T_6620 @[el2_ifu_mem_ctl.scala 741:39] + node _T_6621 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_6622 = eq(_T_6621, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_6623 = and(ic_valid_ff, _T_6622) @[el2_ifu_mem_ctl.scala 741:64] + node _T_6624 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_6625 = and(_T_6623, _T_6624) @[el2_ifu_mem_ctl.scala 741:89] + node _T_6626 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h039")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_6627 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_6628 = and(_T_6626, _T_6627) @[el2_ifu_mem_ctl.scala 742:58] + node _T_6629 = eq(perr_ic_index_ff, UInt<6>("h039")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_6630 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_6631 = and(_T_6629, _T_6630) @[el2_ifu_mem_ctl.scala 742:123] + node _T_6632 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_6633 = and(_T_6631, _T_6632) @[el2_ifu_mem_ctl.scala 742:144] + node _T_6634 = or(_T_6628, _T_6633) @[el2_ifu_mem_ctl.scala 742:80] + node _T_6635 = bits(_T_6634, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_6636 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6635 : @[Reg.scala 28:19] _T_6636 <= _T_6625 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][57] <= _T_6636 @[el2_ifu_mem_ctl.scala 740:39] - node _T_6637 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_6638 = eq(_T_6637, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_6639 = and(ic_valid_ff, _T_6638) @[el2_ifu_mem_ctl.scala 740:64] - node _T_6640 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_6641 = and(_T_6639, _T_6640) @[el2_ifu_mem_ctl.scala 740:89] - node _T_6642 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03a")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_6643 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_6644 = and(_T_6642, _T_6643) @[el2_ifu_mem_ctl.scala 741:58] - node _T_6645 = eq(perr_ic_index_ff, UInt<6>("h03a")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_6646 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_6647 = and(_T_6645, _T_6646) @[el2_ifu_mem_ctl.scala 741:123] - node _T_6648 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_6649 = and(_T_6647, _T_6648) @[el2_ifu_mem_ctl.scala 741:144] - node _T_6650 = or(_T_6644, _T_6649) @[el2_ifu_mem_ctl.scala 741:80] - node _T_6651 = bits(_T_6650, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][57] <= _T_6636 @[el2_ifu_mem_ctl.scala 741:39] + node _T_6637 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_6638 = eq(_T_6637, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_6639 = and(ic_valid_ff, _T_6638) @[el2_ifu_mem_ctl.scala 741:64] + node _T_6640 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_6641 = and(_T_6639, _T_6640) @[el2_ifu_mem_ctl.scala 741:89] + node _T_6642 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03a")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_6643 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_6644 = and(_T_6642, _T_6643) @[el2_ifu_mem_ctl.scala 742:58] + node _T_6645 = eq(perr_ic_index_ff, UInt<6>("h03a")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_6646 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_6647 = and(_T_6645, _T_6646) @[el2_ifu_mem_ctl.scala 742:123] + node _T_6648 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_6649 = and(_T_6647, _T_6648) @[el2_ifu_mem_ctl.scala 742:144] + node _T_6650 = or(_T_6644, _T_6649) @[el2_ifu_mem_ctl.scala 742:80] + node _T_6651 = bits(_T_6650, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_6652 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6651 : @[Reg.scala 28:19] _T_6652 <= _T_6641 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][58] <= _T_6652 @[el2_ifu_mem_ctl.scala 740:39] - node _T_6653 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_6654 = eq(_T_6653, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_6655 = and(ic_valid_ff, _T_6654) @[el2_ifu_mem_ctl.scala 740:64] - node _T_6656 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_6657 = and(_T_6655, _T_6656) @[el2_ifu_mem_ctl.scala 740:89] - node _T_6658 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03b")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_6659 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_6660 = and(_T_6658, _T_6659) @[el2_ifu_mem_ctl.scala 741:58] - node _T_6661 = eq(perr_ic_index_ff, UInt<6>("h03b")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_6662 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_6663 = and(_T_6661, _T_6662) @[el2_ifu_mem_ctl.scala 741:123] - node _T_6664 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_6665 = and(_T_6663, _T_6664) @[el2_ifu_mem_ctl.scala 741:144] - node _T_6666 = or(_T_6660, _T_6665) @[el2_ifu_mem_ctl.scala 741:80] - node _T_6667 = bits(_T_6666, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][58] <= _T_6652 @[el2_ifu_mem_ctl.scala 741:39] + node _T_6653 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_6654 = eq(_T_6653, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_6655 = and(ic_valid_ff, _T_6654) @[el2_ifu_mem_ctl.scala 741:64] + node _T_6656 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_6657 = and(_T_6655, _T_6656) @[el2_ifu_mem_ctl.scala 741:89] + node _T_6658 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03b")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_6659 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_6660 = and(_T_6658, _T_6659) @[el2_ifu_mem_ctl.scala 742:58] + node _T_6661 = eq(perr_ic_index_ff, UInt<6>("h03b")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_6662 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_6663 = and(_T_6661, _T_6662) @[el2_ifu_mem_ctl.scala 742:123] + node _T_6664 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_6665 = and(_T_6663, _T_6664) @[el2_ifu_mem_ctl.scala 742:144] + node _T_6666 = or(_T_6660, _T_6665) @[el2_ifu_mem_ctl.scala 742:80] + node _T_6667 = bits(_T_6666, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_6668 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6667 : @[Reg.scala 28:19] _T_6668 <= _T_6657 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][59] <= _T_6668 @[el2_ifu_mem_ctl.scala 740:39] - node _T_6669 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_6670 = eq(_T_6669, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_6671 = and(ic_valid_ff, _T_6670) @[el2_ifu_mem_ctl.scala 740:64] - node _T_6672 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_6673 = and(_T_6671, _T_6672) @[el2_ifu_mem_ctl.scala 740:89] - node _T_6674 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03c")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_6675 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_6676 = and(_T_6674, _T_6675) @[el2_ifu_mem_ctl.scala 741:58] - node _T_6677 = eq(perr_ic_index_ff, UInt<6>("h03c")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_6678 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_6679 = and(_T_6677, _T_6678) @[el2_ifu_mem_ctl.scala 741:123] - node _T_6680 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_6681 = and(_T_6679, _T_6680) @[el2_ifu_mem_ctl.scala 741:144] - node _T_6682 = or(_T_6676, _T_6681) @[el2_ifu_mem_ctl.scala 741:80] - node _T_6683 = bits(_T_6682, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][59] <= _T_6668 @[el2_ifu_mem_ctl.scala 741:39] + node _T_6669 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_6670 = eq(_T_6669, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_6671 = and(ic_valid_ff, _T_6670) @[el2_ifu_mem_ctl.scala 741:64] + node _T_6672 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_6673 = and(_T_6671, _T_6672) @[el2_ifu_mem_ctl.scala 741:89] + node _T_6674 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03c")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_6675 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_6676 = and(_T_6674, _T_6675) @[el2_ifu_mem_ctl.scala 742:58] + node _T_6677 = eq(perr_ic_index_ff, UInt<6>("h03c")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_6678 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_6679 = and(_T_6677, _T_6678) @[el2_ifu_mem_ctl.scala 742:123] + node _T_6680 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_6681 = and(_T_6679, _T_6680) @[el2_ifu_mem_ctl.scala 742:144] + node _T_6682 = or(_T_6676, _T_6681) @[el2_ifu_mem_ctl.scala 742:80] + node _T_6683 = bits(_T_6682, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_6684 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6683 : @[Reg.scala 28:19] _T_6684 <= _T_6673 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][60] <= _T_6684 @[el2_ifu_mem_ctl.scala 740:39] - node _T_6685 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_6686 = eq(_T_6685, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_6687 = and(ic_valid_ff, _T_6686) @[el2_ifu_mem_ctl.scala 740:64] - node _T_6688 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_6689 = and(_T_6687, _T_6688) @[el2_ifu_mem_ctl.scala 740:89] - node _T_6690 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03d")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_6691 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_6692 = and(_T_6690, _T_6691) @[el2_ifu_mem_ctl.scala 741:58] - node _T_6693 = eq(perr_ic_index_ff, UInt<6>("h03d")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_6694 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_6695 = and(_T_6693, _T_6694) @[el2_ifu_mem_ctl.scala 741:123] - node _T_6696 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_6697 = and(_T_6695, _T_6696) @[el2_ifu_mem_ctl.scala 741:144] - node _T_6698 = or(_T_6692, _T_6697) @[el2_ifu_mem_ctl.scala 741:80] - node _T_6699 = bits(_T_6698, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][60] <= _T_6684 @[el2_ifu_mem_ctl.scala 741:39] + node _T_6685 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_6686 = eq(_T_6685, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_6687 = and(ic_valid_ff, _T_6686) @[el2_ifu_mem_ctl.scala 741:64] + node _T_6688 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_6689 = and(_T_6687, _T_6688) @[el2_ifu_mem_ctl.scala 741:89] + node _T_6690 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03d")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_6691 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_6692 = and(_T_6690, _T_6691) @[el2_ifu_mem_ctl.scala 742:58] + node _T_6693 = eq(perr_ic_index_ff, UInt<6>("h03d")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_6694 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_6695 = and(_T_6693, _T_6694) @[el2_ifu_mem_ctl.scala 742:123] + node _T_6696 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_6697 = and(_T_6695, _T_6696) @[el2_ifu_mem_ctl.scala 742:144] + node _T_6698 = or(_T_6692, _T_6697) @[el2_ifu_mem_ctl.scala 742:80] + node _T_6699 = bits(_T_6698, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_6700 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6699 : @[Reg.scala 28:19] _T_6700 <= _T_6689 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][61] <= _T_6700 @[el2_ifu_mem_ctl.scala 740:39] - node _T_6701 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_6702 = eq(_T_6701, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_6703 = and(ic_valid_ff, _T_6702) @[el2_ifu_mem_ctl.scala 740:64] - node _T_6704 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_6705 = and(_T_6703, _T_6704) @[el2_ifu_mem_ctl.scala 740:89] - node _T_6706 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03e")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_6707 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_6708 = and(_T_6706, _T_6707) @[el2_ifu_mem_ctl.scala 741:58] - node _T_6709 = eq(perr_ic_index_ff, UInt<6>("h03e")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_6710 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_6711 = and(_T_6709, _T_6710) @[el2_ifu_mem_ctl.scala 741:123] - node _T_6712 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_6713 = and(_T_6711, _T_6712) @[el2_ifu_mem_ctl.scala 741:144] - node _T_6714 = or(_T_6708, _T_6713) @[el2_ifu_mem_ctl.scala 741:80] - node _T_6715 = bits(_T_6714, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][61] <= _T_6700 @[el2_ifu_mem_ctl.scala 741:39] + node _T_6701 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_6702 = eq(_T_6701, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_6703 = and(ic_valid_ff, _T_6702) @[el2_ifu_mem_ctl.scala 741:64] + node _T_6704 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_6705 = and(_T_6703, _T_6704) @[el2_ifu_mem_ctl.scala 741:89] + node _T_6706 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03e")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_6707 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_6708 = and(_T_6706, _T_6707) @[el2_ifu_mem_ctl.scala 742:58] + node _T_6709 = eq(perr_ic_index_ff, UInt<6>("h03e")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_6710 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_6711 = and(_T_6709, _T_6710) @[el2_ifu_mem_ctl.scala 742:123] + node _T_6712 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_6713 = and(_T_6711, _T_6712) @[el2_ifu_mem_ctl.scala 742:144] + node _T_6714 = or(_T_6708, _T_6713) @[el2_ifu_mem_ctl.scala 742:80] + node _T_6715 = bits(_T_6714, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_6716 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6715 : @[Reg.scala 28:19] _T_6716 <= _T_6705 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][62] <= _T_6716 @[el2_ifu_mem_ctl.scala 740:39] - node _T_6717 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_6718 = eq(_T_6717, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_6719 = and(ic_valid_ff, _T_6718) @[el2_ifu_mem_ctl.scala 740:64] - node _T_6720 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_6721 = and(_T_6719, _T_6720) @[el2_ifu_mem_ctl.scala 740:89] - node _T_6722 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03f")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_6723 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_6724 = and(_T_6722, _T_6723) @[el2_ifu_mem_ctl.scala 741:58] - node _T_6725 = eq(perr_ic_index_ff, UInt<6>("h03f")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_6726 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_6727 = and(_T_6725, _T_6726) @[el2_ifu_mem_ctl.scala 741:123] - node _T_6728 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_6729 = and(_T_6727, _T_6728) @[el2_ifu_mem_ctl.scala 741:144] - node _T_6730 = or(_T_6724, _T_6729) @[el2_ifu_mem_ctl.scala 741:80] - node _T_6731 = bits(_T_6730, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][62] <= _T_6716 @[el2_ifu_mem_ctl.scala 741:39] + node _T_6717 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_6718 = eq(_T_6717, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_6719 = and(ic_valid_ff, _T_6718) @[el2_ifu_mem_ctl.scala 741:64] + node _T_6720 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_6721 = and(_T_6719, _T_6720) @[el2_ifu_mem_ctl.scala 741:89] + node _T_6722 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03f")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_6723 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_6724 = and(_T_6722, _T_6723) @[el2_ifu_mem_ctl.scala 742:58] + node _T_6725 = eq(perr_ic_index_ff, UInt<6>("h03f")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_6726 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_6727 = and(_T_6725, _T_6726) @[el2_ifu_mem_ctl.scala 742:123] + node _T_6728 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_6729 = and(_T_6727, _T_6728) @[el2_ifu_mem_ctl.scala 742:144] + node _T_6730 = or(_T_6724, _T_6729) @[el2_ifu_mem_ctl.scala 742:80] + node _T_6731 = bits(_T_6730, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_6732 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6731 : @[Reg.scala 28:19] _T_6732 <= _T_6721 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][63] <= _T_6732 @[el2_ifu_mem_ctl.scala 740:39] - node _T_6733 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_6734 = eq(_T_6733, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_6735 = and(ic_valid_ff, _T_6734) @[el2_ifu_mem_ctl.scala 740:64] - node _T_6736 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_6737 = and(_T_6735, _T_6736) @[el2_ifu_mem_ctl.scala 740:89] - node _T_6738 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h020")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_6739 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_6740 = and(_T_6738, _T_6739) @[el2_ifu_mem_ctl.scala 741:58] - node _T_6741 = eq(perr_ic_index_ff, UInt<6>("h020")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_6742 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_6743 = and(_T_6741, _T_6742) @[el2_ifu_mem_ctl.scala 741:123] - node _T_6744 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_6745 = and(_T_6743, _T_6744) @[el2_ifu_mem_ctl.scala 741:144] - node _T_6746 = or(_T_6740, _T_6745) @[el2_ifu_mem_ctl.scala 741:80] - node _T_6747 = bits(_T_6746, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][63] <= _T_6732 @[el2_ifu_mem_ctl.scala 741:39] + node _T_6733 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_6734 = eq(_T_6733, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_6735 = and(ic_valid_ff, _T_6734) @[el2_ifu_mem_ctl.scala 741:64] + node _T_6736 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_6737 = and(_T_6735, _T_6736) @[el2_ifu_mem_ctl.scala 741:89] + node _T_6738 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h020")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_6739 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_6740 = and(_T_6738, _T_6739) @[el2_ifu_mem_ctl.scala 742:58] + node _T_6741 = eq(perr_ic_index_ff, UInt<6>("h020")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_6742 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_6743 = and(_T_6741, _T_6742) @[el2_ifu_mem_ctl.scala 742:123] + node _T_6744 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_6745 = and(_T_6743, _T_6744) @[el2_ifu_mem_ctl.scala 742:144] + node _T_6746 = or(_T_6740, _T_6745) @[el2_ifu_mem_ctl.scala 742:80] + node _T_6747 = bits(_T_6746, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_6748 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6747 : @[Reg.scala 28:19] _T_6748 <= _T_6737 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][32] <= _T_6748 @[el2_ifu_mem_ctl.scala 740:39] - node _T_6749 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_6750 = eq(_T_6749, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_6751 = and(ic_valid_ff, _T_6750) @[el2_ifu_mem_ctl.scala 740:64] - node _T_6752 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_6753 = and(_T_6751, _T_6752) @[el2_ifu_mem_ctl.scala 740:89] - node _T_6754 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h021")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_6755 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_6756 = and(_T_6754, _T_6755) @[el2_ifu_mem_ctl.scala 741:58] - node _T_6757 = eq(perr_ic_index_ff, UInt<6>("h021")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_6758 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_6759 = and(_T_6757, _T_6758) @[el2_ifu_mem_ctl.scala 741:123] - node _T_6760 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_6761 = and(_T_6759, _T_6760) @[el2_ifu_mem_ctl.scala 741:144] - node _T_6762 = or(_T_6756, _T_6761) @[el2_ifu_mem_ctl.scala 741:80] - node _T_6763 = bits(_T_6762, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][32] <= _T_6748 @[el2_ifu_mem_ctl.scala 741:39] + node _T_6749 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_6750 = eq(_T_6749, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_6751 = and(ic_valid_ff, _T_6750) @[el2_ifu_mem_ctl.scala 741:64] + node _T_6752 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_6753 = and(_T_6751, _T_6752) @[el2_ifu_mem_ctl.scala 741:89] + node _T_6754 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h021")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_6755 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_6756 = and(_T_6754, _T_6755) @[el2_ifu_mem_ctl.scala 742:58] + node _T_6757 = eq(perr_ic_index_ff, UInt<6>("h021")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_6758 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_6759 = and(_T_6757, _T_6758) @[el2_ifu_mem_ctl.scala 742:123] + node _T_6760 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_6761 = and(_T_6759, _T_6760) @[el2_ifu_mem_ctl.scala 742:144] + node _T_6762 = or(_T_6756, _T_6761) @[el2_ifu_mem_ctl.scala 742:80] + node _T_6763 = bits(_T_6762, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_6764 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6763 : @[Reg.scala 28:19] _T_6764 <= _T_6753 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][33] <= _T_6764 @[el2_ifu_mem_ctl.scala 740:39] - node _T_6765 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_6766 = eq(_T_6765, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_6767 = and(ic_valid_ff, _T_6766) @[el2_ifu_mem_ctl.scala 740:64] - node _T_6768 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_6769 = and(_T_6767, _T_6768) @[el2_ifu_mem_ctl.scala 740:89] - node _T_6770 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h022")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_6771 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_6772 = and(_T_6770, _T_6771) @[el2_ifu_mem_ctl.scala 741:58] - node _T_6773 = eq(perr_ic_index_ff, UInt<6>("h022")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_6774 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_6775 = and(_T_6773, _T_6774) @[el2_ifu_mem_ctl.scala 741:123] - node _T_6776 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_6777 = and(_T_6775, _T_6776) @[el2_ifu_mem_ctl.scala 741:144] - node _T_6778 = or(_T_6772, _T_6777) @[el2_ifu_mem_ctl.scala 741:80] - node _T_6779 = bits(_T_6778, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][33] <= _T_6764 @[el2_ifu_mem_ctl.scala 741:39] + node _T_6765 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_6766 = eq(_T_6765, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_6767 = and(ic_valid_ff, _T_6766) @[el2_ifu_mem_ctl.scala 741:64] + node _T_6768 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_6769 = and(_T_6767, _T_6768) @[el2_ifu_mem_ctl.scala 741:89] + node _T_6770 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h022")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_6771 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_6772 = and(_T_6770, _T_6771) @[el2_ifu_mem_ctl.scala 742:58] + node _T_6773 = eq(perr_ic_index_ff, UInt<6>("h022")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_6774 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_6775 = and(_T_6773, _T_6774) @[el2_ifu_mem_ctl.scala 742:123] + node _T_6776 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_6777 = and(_T_6775, _T_6776) @[el2_ifu_mem_ctl.scala 742:144] + node _T_6778 = or(_T_6772, _T_6777) @[el2_ifu_mem_ctl.scala 742:80] + node _T_6779 = bits(_T_6778, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_6780 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6779 : @[Reg.scala 28:19] _T_6780 <= _T_6769 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][34] <= _T_6780 @[el2_ifu_mem_ctl.scala 740:39] - node _T_6781 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_6782 = eq(_T_6781, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_6783 = and(ic_valid_ff, _T_6782) @[el2_ifu_mem_ctl.scala 740:64] - node _T_6784 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_6785 = and(_T_6783, _T_6784) @[el2_ifu_mem_ctl.scala 740:89] - node _T_6786 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h023")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_6787 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_6788 = and(_T_6786, _T_6787) @[el2_ifu_mem_ctl.scala 741:58] - node _T_6789 = eq(perr_ic_index_ff, UInt<6>("h023")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_6790 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_6791 = and(_T_6789, _T_6790) @[el2_ifu_mem_ctl.scala 741:123] - node _T_6792 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_6793 = and(_T_6791, _T_6792) @[el2_ifu_mem_ctl.scala 741:144] - node _T_6794 = or(_T_6788, _T_6793) @[el2_ifu_mem_ctl.scala 741:80] - node _T_6795 = bits(_T_6794, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][34] <= _T_6780 @[el2_ifu_mem_ctl.scala 741:39] + node _T_6781 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_6782 = eq(_T_6781, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_6783 = and(ic_valid_ff, _T_6782) @[el2_ifu_mem_ctl.scala 741:64] + node _T_6784 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_6785 = and(_T_6783, _T_6784) @[el2_ifu_mem_ctl.scala 741:89] + node _T_6786 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h023")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_6787 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_6788 = and(_T_6786, _T_6787) @[el2_ifu_mem_ctl.scala 742:58] + node _T_6789 = eq(perr_ic_index_ff, UInt<6>("h023")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_6790 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_6791 = and(_T_6789, _T_6790) @[el2_ifu_mem_ctl.scala 742:123] + node _T_6792 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_6793 = and(_T_6791, _T_6792) @[el2_ifu_mem_ctl.scala 742:144] + node _T_6794 = or(_T_6788, _T_6793) @[el2_ifu_mem_ctl.scala 742:80] + node _T_6795 = bits(_T_6794, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_6796 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6795 : @[Reg.scala 28:19] _T_6796 <= _T_6785 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][35] <= _T_6796 @[el2_ifu_mem_ctl.scala 740:39] - node _T_6797 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_6798 = eq(_T_6797, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_6799 = and(ic_valid_ff, _T_6798) @[el2_ifu_mem_ctl.scala 740:64] - node _T_6800 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_6801 = and(_T_6799, _T_6800) @[el2_ifu_mem_ctl.scala 740:89] - node _T_6802 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h024")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_6803 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_6804 = and(_T_6802, _T_6803) @[el2_ifu_mem_ctl.scala 741:58] - node _T_6805 = eq(perr_ic_index_ff, UInt<6>("h024")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_6806 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_6807 = and(_T_6805, _T_6806) @[el2_ifu_mem_ctl.scala 741:123] - node _T_6808 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_6809 = and(_T_6807, _T_6808) @[el2_ifu_mem_ctl.scala 741:144] - node _T_6810 = or(_T_6804, _T_6809) @[el2_ifu_mem_ctl.scala 741:80] - node _T_6811 = bits(_T_6810, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][35] <= _T_6796 @[el2_ifu_mem_ctl.scala 741:39] + node _T_6797 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_6798 = eq(_T_6797, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_6799 = and(ic_valid_ff, _T_6798) @[el2_ifu_mem_ctl.scala 741:64] + node _T_6800 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_6801 = and(_T_6799, _T_6800) @[el2_ifu_mem_ctl.scala 741:89] + node _T_6802 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h024")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_6803 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_6804 = and(_T_6802, _T_6803) @[el2_ifu_mem_ctl.scala 742:58] + node _T_6805 = eq(perr_ic_index_ff, UInt<6>("h024")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_6806 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_6807 = and(_T_6805, _T_6806) @[el2_ifu_mem_ctl.scala 742:123] + node _T_6808 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_6809 = and(_T_6807, _T_6808) @[el2_ifu_mem_ctl.scala 742:144] + node _T_6810 = or(_T_6804, _T_6809) @[el2_ifu_mem_ctl.scala 742:80] + node _T_6811 = bits(_T_6810, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_6812 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6811 : @[Reg.scala 28:19] _T_6812 <= _T_6801 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][36] <= _T_6812 @[el2_ifu_mem_ctl.scala 740:39] - node _T_6813 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_6814 = eq(_T_6813, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_6815 = and(ic_valid_ff, _T_6814) @[el2_ifu_mem_ctl.scala 740:64] - node _T_6816 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_6817 = and(_T_6815, _T_6816) @[el2_ifu_mem_ctl.scala 740:89] - node _T_6818 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h025")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_6819 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_6820 = and(_T_6818, _T_6819) @[el2_ifu_mem_ctl.scala 741:58] - node _T_6821 = eq(perr_ic_index_ff, UInt<6>("h025")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_6822 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_6823 = and(_T_6821, _T_6822) @[el2_ifu_mem_ctl.scala 741:123] - node _T_6824 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_6825 = and(_T_6823, _T_6824) @[el2_ifu_mem_ctl.scala 741:144] - node _T_6826 = or(_T_6820, _T_6825) @[el2_ifu_mem_ctl.scala 741:80] - node _T_6827 = bits(_T_6826, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][36] <= _T_6812 @[el2_ifu_mem_ctl.scala 741:39] + node _T_6813 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_6814 = eq(_T_6813, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_6815 = and(ic_valid_ff, _T_6814) @[el2_ifu_mem_ctl.scala 741:64] + node _T_6816 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_6817 = and(_T_6815, _T_6816) @[el2_ifu_mem_ctl.scala 741:89] + node _T_6818 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h025")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_6819 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_6820 = and(_T_6818, _T_6819) @[el2_ifu_mem_ctl.scala 742:58] + node _T_6821 = eq(perr_ic_index_ff, UInt<6>("h025")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_6822 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_6823 = and(_T_6821, _T_6822) @[el2_ifu_mem_ctl.scala 742:123] + node _T_6824 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_6825 = and(_T_6823, _T_6824) @[el2_ifu_mem_ctl.scala 742:144] + node _T_6826 = or(_T_6820, _T_6825) @[el2_ifu_mem_ctl.scala 742:80] + node _T_6827 = bits(_T_6826, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_6828 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6827 : @[Reg.scala 28:19] _T_6828 <= _T_6817 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][37] <= _T_6828 @[el2_ifu_mem_ctl.scala 740:39] - node _T_6829 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_6830 = eq(_T_6829, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_6831 = and(ic_valid_ff, _T_6830) @[el2_ifu_mem_ctl.scala 740:64] - node _T_6832 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_6833 = and(_T_6831, _T_6832) @[el2_ifu_mem_ctl.scala 740:89] - node _T_6834 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h026")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_6835 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_6836 = and(_T_6834, _T_6835) @[el2_ifu_mem_ctl.scala 741:58] - node _T_6837 = eq(perr_ic_index_ff, UInt<6>("h026")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_6838 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_6839 = and(_T_6837, _T_6838) @[el2_ifu_mem_ctl.scala 741:123] - node _T_6840 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_6841 = and(_T_6839, _T_6840) @[el2_ifu_mem_ctl.scala 741:144] - node _T_6842 = or(_T_6836, _T_6841) @[el2_ifu_mem_ctl.scala 741:80] - node _T_6843 = bits(_T_6842, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][37] <= _T_6828 @[el2_ifu_mem_ctl.scala 741:39] + node _T_6829 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_6830 = eq(_T_6829, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_6831 = and(ic_valid_ff, _T_6830) @[el2_ifu_mem_ctl.scala 741:64] + node _T_6832 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_6833 = and(_T_6831, _T_6832) @[el2_ifu_mem_ctl.scala 741:89] + node _T_6834 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h026")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_6835 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_6836 = and(_T_6834, _T_6835) @[el2_ifu_mem_ctl.scala 742:58] + node _T_6837 = eq(perr_ic_index_ff, UInt<6>("h026")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_6838 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_6839 = and(_T_6837, _T_6838) @[el2_ifu_mem_ctl.scala 742:123] + node _T_6840 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_6841 = and(_T_6839, _T_6840) @[el2_ifu_mem_ctl.scala 742:144] + node _T_6842 = or(_T_6836, _T_6841) @[el2_ifu_mem_ctl.scala 742:80] + node _T_6843 = bits(_T_6842, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_6844 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6843 : @[Reg.scala 28:19] _T_6844 <= _T_6833 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][38] <= _T_6844 @[el2_ifu_mem_ctl.scala 740:39] - node _T_6845 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_6846 = eq(_T_6845, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_6847 = and(ic_valid_ff, _T_6846) @[el2_ifu_mem_ctl.scala 740:64] - node _T_6848 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_6849 = and(_T_6847, _T_6848) @[el2_ifu_mem_ctl.scala 740:89] - node _T_6850 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h027")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_6851 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_6852 = and(_T_6850, _T_6851) @[el2_ifu_mem_ctl.scala 741:58] - node _T_6853 = eq(perr_ic_index_ff, UInt<6>("h027")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_6854 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_6855 = and(_T_6853, _T_6854) @[el2_ifu_mem_ctl.scala 741:123] - node _T_6856 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_6857 = and(_T_6855, _T_6856) @[el2_ifu_mem_ctl.scala 741:144] - node _T_6858 = or(_T_6852, _T_6857) @[el2_ifu_mem_ctl.scala 741:80] - node _T_6859 = bits(_T_6858, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][38] <= _T_6844 @[el2_ifu_mem_ctl.scala 741:39] + node _T_6845 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_6846 = eq(_T_6845, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_6847 = and(ic_valid_ff, _T_6846) @[el2_ifu_mem_ctl.scala 741:64] + node _T_6848 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_6849 = and(_T_6847, _T_6848) @[el2_ifu_mem_ctl.scala 741:89] + node _T_6850 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h027")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_6851 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_6852 = and(_T_6850, _T_6851) @[el2_ifu_mem_ctl.scala 742:58] + node _T_6853 = eq(perr_ic_index_ff, UInt<6>("h027")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_6854 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_6855 = and(_T_6853, _T_6854) @[el2_ifu_mem_ctl.scala 742:123] + node _T_6856 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_6857 = and(_T_6855, _T_6856) @[el2_ifu_mem_ctl.scala 742:144] + node _T_6858 = or(_T_6852, _T_6857) @[el2_ifu_mem_ctl.scala 742:80] + node _T_6859 = bits(_T_6858, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_6860 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6859 : @[Reg.scala 28:19] _T_6860 <= _T_6849 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][39] <= _T_6860 @[el2_ifu_mem_ctl.scala 740:39] - node _T_6861 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_6862 = eq(_T_6861, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_6863 = and(ic_valid_ff, _T_6862) @[el2_ifu_mem_ctl.scala 740:64] - node _T_6864 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_6865 = and(_T_6863, _T_6864) @[el2_ifu_mem_ctl.scala 740:89] - node _T_6866 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h028")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_6867 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_6868 = and(_T_6866, _T_6867) @[el2_ifu_mem_ctl.scala 741:58] - node _T_6869 = eq(perr_ic_index_ff, UInt<6>("h028")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_6870 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_6871 = and(_T_6869, _T_6870) @[el2_ifu_mem_ctl.scala 741:123] - node _T_6872 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_6873 = and(_T_6871, _T_6872) @[el2_ifu_mem_ctl.scala 741:144] - node _T_6874 = or(_T_6868, _T_6873) @[el2_ifu_mem_ctl.scala 741:80] - node _T_6875 = bits(_T_6874, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][39] <= _T_6860 @[el2_ifu_mem_ctl.scala 741:39] + node _T_6861 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_6862 = eq(_T_6861, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_6863 = and(ic_valid_ff, _T_6862) @[el2_ifu_mem_ctl.scala 741:64] + node _T_6864 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_6865 = and(_T_6863, _T_6864) @[el2_ifu_mem_ctl.scala 741:89] + node _T_6866 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h028")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_6867 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_6868 = and(_T_6866, _T_6867) @[el2_ifu_mem_ctl.scala 742:58] + node _T_6869 = eq(perr_ic_index_ff, UInt<6>("h028")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_6870 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_6871 = and(_T_6869, _T_6870) @[el2_ifu_mem_ctl.scala 742:123] + node _T_6872 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_6873 = and(_T_6871, _T_6872) @[el2_ifu_mem_ctl.scala 742:144] + node _T_6874 = or(_T_6868, _T_6873) @[el2_ifu_mem_ctl.scala 742:80] + node _T_6875 = bits(_T_6874, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_6876 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6875 : @[Reg.scala 28:19] _T_6876 <= _T_6865 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][40] <= _T_6876 @[el2_ifu_mem_ctl.scala 740:39] - node _T_6877 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_6878 = eq(_T_6877, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_6879 = and(ic_valid_ff, _T_6878) @[el2_ifu_mem_ctl.scala 740:64] - node _T_6880 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_6881 = and(_T_6879, _T_6880) @[el2_ifu_mem_ctl.scala 740:89] - node _T_6882 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h029")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_6883 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_6884 = and(_T_6882, _T_6883) @[el2_ifu_mem_ctl.scala 741:58] - node _T_6885 = eq(perr_ic_index_ff, UInt<6>("h029")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_6886 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_6887 = and(_T_6885, _T_6886) @[el2_ifu_mem_ctl.scala 741:123] - node _T_6888 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_6889 = and(_T_6887, _T_6888) @[el2_ifu_mem_ctl.scala 741:144] - node _T_6890 = or(_T_6884, _T_6889) @[el2_ifu_mem_ctl.scala 741:80] - node _T_6891 = bits(_T_6890, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][40] <= _T_6876 @[el2_ifu_mem_ctl.scala 741:39] + node _T_6877 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_6878 = eq(_T_6877, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_6879 = and(ic_valid_ff, _T_6878) @[el2_ifu_mem_ctl.scala 741:64] + node _T_6880 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_6881 = and(_T_6879, _T_6880) @[el2_ifu_mem_ctl.scala 741:89] + node _T_6882 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h029")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_6883 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_6884 = and(_T_6882, _T_6883) @[el2_ifu_mem_ctl.scala 742:58] + node _T_6885 = eq(perr_ic_index_ff, UInt<6>("h029")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_6886 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_6887 = and(_T_6885, _T_6886) @[el2_ifu_mem_ctl.scala 742:123] + node _T_6888 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_6889 = and(_T_6887, _T_6888) @[el2_ifu_mem_ctl.scala 742:144] + node _T_6890 = or(_T_6884, _T_6889) @[el2_ifu_mem_ctl.scala 742:80] + node _T_6891 = bits(_T_6890, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_6892 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6891 : @[Reg.scala 28:19] _T_6892 <= _T_6881 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][41] <= _T_6892 @[el2_ifu_mem_ctl.scala 740:39] - node _T_6893 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_6894 = eq(_T_6893, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_6895 = and(ic_valid_ff, _T_6894) @[el2_ifu_mem_ctl.scala 740:64] - node _T_6896 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_6897 = and(_T_6895, _T_6896) @[el2_ifu_mem_ctl.scala 740:89] - node _T_6898 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02a")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_6899 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_6900 = and(_T_6898, _T_6899) @[el2_ifu_mem_ctl.scala 741:58] - node _T_6901 = eq(perr_ic_index_ff, UInt<6>("h02a")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_6902 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_6903 = and(_T_6901, _T_6902) @[el2_ifu_mem_ctl.scala 741:123] - node _T_6904 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_6905 = and(_T_6903, _T_6904) @[el2_ifu_mem_ctl.scala 741:144] - node _T_6906 = or(_T_6900, _T_6905) @[el2_ifu_mem_ctl.scala 741:80] - node _T_6907 = bits(_T_6906, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][41] <= _T_6892 @[el2_ifu_mem_ctl.scala 741:39] + node _T_6893 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_6894 = eq(_T_6893, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_6895 = and(ic_valid_ff, _T_6894) @[el2_ifu_mem_ctl.scala 741:64] + node _T_6896 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_6897 = and(_T_6895, _T_6896) @[el2_ifu_mem_ctl.scala 741:89] + node _T_6898 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02a")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_6899 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_6900 = and(_T_6898, _T_6899) @[el2_ifu_mem_ctl.scala 742:58] + node _T_6901 = eq(perr_ic_index_ff, UInt<6>("h02a")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_6902 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_6903 = and(_T_6901, _T_6902) @[el2_ifu_mem_ctl.scala 742:123] + node _T_6904 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_6905 = and(_T_6903, _T_6904) @[el2_ifu_mem_ctl.scala 742:144] + node _T_6906 = or(_T_6900, _T_6905) @[el2_ifu_mem_ctl.scala 742:80] + node _T_6907 = bits(_T_6906, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_6908 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6907 : @[Reg.scala 28:19] _T_6908 <= _T_6897 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][42] <= _T_6908 @[el2_ifu_mem_ctl.scala 740:39] - node _T_6909 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_6910 = eq(_T_6909, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_6911 = and(ic_valid_ff, _T_6910) @[el2_ifu_mem_ctl.scala 740:64] - node _T_6912 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_6913 = and(_T_6911, _T_6912) @[el2_ifu_mem_ctl.scala 740:89] - node _T_6914 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02b")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_6915 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_6916 = and(_T_6914, _T_6915) @[el2_ifu_mem_ctl.scala 741:58] - node _T_6917 = eq(perr_ic_index_ff, UInt<6>("h02b")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_6918 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_6919 = and(_T_6917, _T_6918) @[el2_ifu_mem_ctl.scala 741:123] - node _T_6920 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_6921 = and(_T_6919, _T_6920) @[el2_ifu_mem_ctl.scala 741:144] - node _T_6922 = or(_T_6916, _T_6921) @[el2_ifu_mem_ctl.scala 741:80] - node _T_6923 = bits(_T_6922, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][42] <= _T_6908 @[el2_ifu_mem_ctl.scala 741:39] + node _T_6909 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_6910 = eq(_T_6909, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_6911 = and(ic_valid_ff, _T_6910) @[el2_ifu_mem_ctl.scala 741:64] + node _T_6912 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_6913 = and(_T_6911, _T_6912) @[el2_ifu_mem_ctl.scala 741:89] + node _T_6914 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02b")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_6915 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_6916 = and(_T_6914, _T_6915) @[el2_ifu_mem_ctl.scala 742:58] + node _T_6917 = eq(perr_ic_index_ff, UInt<6>("h02b")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_6918 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_6919 = and(_T_6917, _T_6918) @[el2_ifu_mem_ctl.scala 742:123] + node _T_6920 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_6921 = and(_T_6919, _T_6920) @[el2_ifu_mem_ctl.scala 742:144] + node _T_6922 = or(_T_6916, _T_6921) @[el2_ifu_mem_ctl.scala 742:80] + node _T_6923 = bits(_T_6922, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_6924 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6923 : @[Reg.scala 28:19] _T_6924 <= _T_6913 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][43] <= _T_6924 @[el2_ifu_mem_ctl.scala 740:39] - node _T_6925 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_6926 = eq(_T_6925, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_6927 = and(ic_valid_ff, _T_6926) @[el2_ifu_mem_ctl.scala 740:64] - node _T_6928 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_6929 = and(_T_6927, _T_6928) @[el2_ifu_mem_ctl.scala 740:89] - node _T_6930 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02c")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_6931 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_6932 = and(_T_6930, _T_6931) @[el2_ifu_mem_ctl.scala 741:58] - node _T_6933 = eq(perr_ic_index_ff, UInt<6>("h02c")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_6934 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_6935 = and(_T_6933, _T_6934) @[el2_ifu_mem_ctl.scala 741:123] - node _T_6936 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_6937 = and(_T_6935, _T_6936) @[el2_ifu_mem_ctl.scala 741:144] - node _T_6938 = or(_T_6932, _T_6937) @[el2_ifu_mem_ctl.scala 741:80] - node _T_6939 = bits(_T_6938, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][43] <= _T_6924 @[el2_ifu_mem_ctl.scala 741:39] + node _T_6925 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_6926 = eq(_T_6925, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_6927 = and(ic_valid_ff, _T_6926) @[el2_ifu_mem_ctl.scala 741:64] + node _T_6928 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_6929 = and(_T_6927, _T_6928) @[el2_ifu_mem_ctl.scala 741:89] + node _T_6930 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02c")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_6931 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_6932 = and(_T_6930, _T_6931) @[el2_ifu_mem_ctl.scala 742:58] + node _T_6933 = eq(perr_ic_index_ff, UInt<6>("h02c")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_6934 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_6935 = and(_T_6933, _T_6934) @[el2_ifu_mem_ctl.scala 742:123] + node _T_6936 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_6937 = and(_T_6935, _T_6936) @[el2_ifu_mem_ctl.scala 742:144] + node _T_6938 = or(_T_6932, _T_6937) @[el2_ifu_mem_ctl.scala 742:80] + node _T_6939 = bits(_T_6938, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_6940 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6939 : @[Reg.scala 28:19] _T_6940 <= _T_6929 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][44] <= _T_6940 @[el2_ifu_mem_ctl.scala 740:39] - node _T_6941 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_6942 = eq(_T_6941, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_6943 = and(ic_valid_ff, _T_6942) @[el2_ifu_mem_ctl.scala 740:64] - node _T_6944 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_6945 = and(_T_6943, _T_6944) @[el2_ifu_mem_ctl.scala 740:89] - node _T_6946 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02d")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_6947 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_6948 = and(_T_6946, _T_6947) @[el2_ifu_mem_ctl.scala 741:58] - node _T_6949 = eq(perr_ic_index_ff, UInt<6>("h02d")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_6950 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_6951 = and(_T_6949, _T_6950) @[el2_ifu_mem_ctl.scala 741:123] - node _T_6952 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_6953 = and(_T_6951, _T_6952) @[el2_ifu_mem_ctl.scala 741:144] - node _T_6954 = or(_T_6948, _T_6953) @[el2_ifu_mem_ctl.scala 741:80] - node _T_6955 = bits(_T_6954, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][44] <= _T_6940 @[el2_ifu_mem_ctl.scala 741:39] + node _T_6941 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_6942 = eq(_T_6941, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_6943 = and(ic_valid_ff, _T_6942) @[el2_ifu_mem_ctl.scala 741:64] + node _T_6944 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_6945 = and(_T_6943, _T_6944) @[el2_ifu_mem_ctl.scala 741:89] + node _T_6946 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02d")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_6947 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_6948 = and(_T_6946, _T_6947) @[el2_ifu_mem_ctl.scala 742:58] + node _T_6949 = eq(perr_ic_index_ff, UInt<6>("h02d")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_6950 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_6951 = and(_T_6949, _T_6950) @[el2_ifu_mem_ctl.scala 742:123] + node _T_6952 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_6953 = and(_T_6951, _T_6952) @[el2_ifu_mem_ctl.scala 742:144] + node _T_6954 = or(_T_6948, _T_6953) @[el2_ifu_mem_ctl.scala 742:80] + node _T_6955 = bits(_T_6954, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_6956 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6955 : @[Reg.scala 28:19] _T_6956 <= _T_6945 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][45] <= _T_6956 @[el2_ifu_mem_ctl.scala 740:39] - node _T_6957 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_6958 = eq(_T_6957, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_6959 = and(ic_valid_ff, _T_6958) @[el2_ifu_mem_ctl.scala 740:64] - node _T_6960 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_6961 = and(_T_6959, _T_6960) @[el2_ifu_mem_ctl.scala 740:89] - node _T_6962 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02e")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_6963 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_6964 = and(_T_6962, _T_6963) @[el2_ifu_mem_ctl.scala 741:58] - node _T_6965 = eq(perr_ic_index_ff, UInt<6>("h02e")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_6966 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_6967 = and(_T_6965, _T_6966) @[el2_ifu_mem_ctl.scala 741:123] - node _T_6968 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_6969 = and(_T_6967, _T_6968) @[el2_ifu_mem_ctl.scala 741:144] - node _T_6970 = or(_T_6964, _T_6969) @[el2_ifu_mem_ctl.scala 741:80] - node _T_6971 = bits(_T_6970, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][45] <= _T_6956 @[el2_ifu_mem_ctl.scala 741:39] + node _T_6957 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_6958 = eq(_T_6957, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_6959 = and(ic_valid_ff, _T_6958) @[el2_ifu_mem_ctl.scala 741:64] + node _T_6960 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_6961 = and(_T_6959, _T_6960) @[el2_ifu_mem_ctl.scala 741:89] + node _T_6962 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02e")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_6963 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_6964 = and(_T_6962, _T_6963) @[el2_ifu_mem_ctl.scala 742:58] + node _T_6965 = eq(perr_ic_index_ff, UInt<6>("h02e")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_6966 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_6967 = and(_T_6965, _T_6966) @[el2_ifu_mem_ctl.scala 742:123] + node _T_6968 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_6969 = and(_T_6967, _T_6968) @[el2_ifu_mem_ctl.scala 742:144] + node _T_6970 = or(_T_6964, _T_6969) @[el2_ifu_mem_ctl.scala 742:80] + node _T_6971 = bits(_T_6970, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_6972 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6971 : @[Reg.scala 28:19] _T_6972 <= _T_6961 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][46] <= _T_6972 @[el2_ifu_mem_ctl.scala 740:39] - node _T_6973 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_6974 = eq(_T_6973, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_6975 = and(ic_valid_ff, _T_6974) @[el2_ifu_mem_ctl.scala 740:64] - node _T_6976 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_6977 = and(_T_6975, _T_6976) @[el2_ifu_mem_ctl.scala 740:89] - node _T_6978 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02f")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_6979 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_6980 = and(_T_6978, _T_6979) @[el2_ifu_mem_ctl.scala 741:58] - node _T_6981 = eq(perr_ic_index_ff, UInt<6>("h02f")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_6982 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_6983 = and(_T_6981, _T_6982) @[el2_ifu_mem_ctl.scala 741:123] - node _T_6984 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_6985 = and(_T_6983, _T_6984) @[el2_ifu_mem_ctl.scala 741:144] - node _T_6986 = or(_T_6980, _T_6985) @[el2_ifu_mem_ctl.scala 741:80] - node _T_6987 = bits(_T_6986, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][46] <= _T_6972 @[el2_ifu_mem_ctl.scala 741:39] + node _T_6973 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_6974 = eq(_T_6973, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_6975 = and(ic_valid_ff, _T_6974) @[el2_ifu_mem_ctl.scala 741:64] + node _T_6976 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_6977 = and(_T_6975, _T_6976) @[el2_ifu_mem_ctl.scala 741:89] + node _T_6978 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02f")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_6979 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_6980 = and(_T_6978, _T_6979) @[el2_ifu_mem_ctl.scala 742:58] + node _T_6981 = eq(perr_ic_index_ff, UInt<6>("h02f")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_6982 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_6983 = and(_T_6981, _T_6982) @[el2_ifu_mem_ctl.scala 742:123] + node _T_6984 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_6985 = and(_T_6983, _T_6984) @[el2_ifu_mem_ctl.scala 742:144] + node _T_6986 = or(_T_6980, _T_6985) @[el2_ifu_mem_ctl.scala 742:80] + node _T_6987 = bits(_T_6986, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_6988 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_6987 : @[Reg.scala 28:19] _T_6988 <= _T_6977 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][47] <= _T_6988 @[el2_ifu_mem_ctl.scala 740:39] - node _T_6989 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_6990 = eq(_T_6989, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_6991 = and(ic_valid_ff, _T_6990) @[el2_ifu_mem_ctl.scala 740:64] - node _T_6992 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_6993 = and(_T_6991, _T_6992) @[el2_ifu_mem_ctl.scala 740:89] - node _T_6994 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h030")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_6995 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_6996 = and(_T_6994, _T_6995) @[el2_ifu_mem_ctl.scala 741:58] - node _T_6997 = eq(perr_ic_index_ff, UInt<6>("h030")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_6998 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_6999 = and(_T_6997, _T_6998) @[el2_ifu_mem_ctl.scala 741:123] - node _T_7000 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_7001 = and(_T_6999, _T_7000) @[el2_ifu_mem_ctl.scala 741:144] - node _T_7002 = or(_T_6996, _T_7001) @[el2_ifu_mem_ctl.scala 741:80] - node _T_7003 = bits(_T_7002, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][47] <= _T_6988 @[el2_ifu_mem_ctl.scala 741:39] + node _T_6989 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_6990 = eq(_T_6989, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_6991 = and(ic_valid_ff, _T_6990) @[el2_ifu_mem_ctl.scala 741:64] + node _T_6992 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_6993 = and(_T_6991, _T_6992) @[el2_ifu_mem_ctl.scala 741:89] + node _T_6994 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h030")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_6995 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_6996 = and(_T_6994, _T_6995) @[el2_ifu_mem_ctl.scala 742:58] + node _T_6997 = eq(perr_ic_index_ff, UInt<6>("h030")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_6998 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_6999 = and(_T_6997, _T_6998) @[el2_ifu_mem_ctl.scala 742:123] + node _T_7000 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_7001 = and(_T_6999, _T_7000) @[el2_ifu_mem_ctl.scala 742:144] + node _T_7002 = or(_T_6996, _T_7001) @[el2_ifu_mem_ctl.scala 742:80] + node _T_7003 = bits(_T_7002, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_7004 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7003 : @[Reg.scala 28:19] _T_7004 <= _T_6993 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][48] <= _T_7004 @[el2_ifu_mem_ctl.scala 740:39] - node _T_7005 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_7006 = eq(_T_7005, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_7007 = and(ic_valid_ff, _T_7006) @[el2_ifu_mem_ctl.scala 740:64] - node _T_7008 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_7009 = and(_T_7007, _T_7008) @[el2_ifu_mem_ctl.scala 740:89] - node _T_7010 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h031")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_7011 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_7012 = and(_T_7010, _T_7011) @[el2_ifu_mem_ctl.scala 741:58] - node _T_7013 = eq(perr_ic_index_ff, UInt<6>("h031")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_7014 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_7015 = and(_T_7013, _T_7014) @[el2_ifu_mem_ctl.scala 741:123] - node _T_7016 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_7017 = and(_T_7015, _T_7016) @[el2_ifu_mem_ctl.scala 741:144] - node _T_7018 = or(_T_7012, _T_7017) @[el2_ifu_mem_ctl.scala 741:80] - node _T_7019 = bits(_T_7018, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][48] <= _T_7004 @[el2_ifu_mem_ctl.scala 741:39] + node _T_7005 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_7006 = eq(_T_7005, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_7007 = and(ic_valid_ff, _T_7006) @[el2_ifu_mem_ctl.scala 741:64] + node _T_7008 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_7009 = and(_T_7007, _T_7008) @[el2_ifu_mem_ctl.scala 741:89] + node _T_7010 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h031")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_7011 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_7012 = and(_T_7010, _T_7011) @[el2_ifu_mem_ctl.scala 742:58] + node _T_7013 = eq(perr_ic_index_ff, UInt<6>("h031")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_7014 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_7015 = and(_T_7013, _T_7014) @[el2_ifu_mem_ctl.scala 742:123] + node _T_7016 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_7017 = and(_T_7015, _T_7016) @[el2_ifu_mem_ctl.scala 742:144] + node _T_7018 = or(_T_7012, _T_7017) @[el2_ifu_mem_ctl.scala 742:80] + node _T_7019 = bits(_T_7018, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_7020 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7019 : @[Reg.scala 28:19] _T_7020 <= _T_7009 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][49] <= _T_7020 @[el2_ifu_mem_ctl.scala 740:39] - node _T_7021 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_7022 = eq(_T_7021, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_7023 = and(ic_valid_ff, _T_7022) @[el2_ifu_mem_ctl.scala 740:64] - node _T_7024 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_7025 = and(_T_7023, _T_7024) @[el2_ifu_mem_ctl.scala 740:89] - node _T_7026 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h032")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_7027 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_7028 = and(_T_7026, _T_7027) @[el2_ifu_mem_ctl.scala 741:58] - node _T_7029 = eq(perr_ic_index_ff, UInt<6>("h032")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_7030 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_7031 = and(_T_7029, _T_7030) @[el2_ifu_mem_ctl.scala 741:123] - node _T_7032 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_7033 = and(_T_7031, _T_7032) @[el2_ifu_mem_ctl.scala 741:144] - node _T_7034 = or(_T_7028, _T_7033) @[el2_ifu_mem_ctl.scala 741:80] - node _T_7035 = bits(_T_7034, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][49] <= _T_7020 @[el2_ifu_mem_ctl.scala 741:39] + node _T_7021 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_7022 = eq(_T_7021, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_7023 = and(ic_valid_ff, _T_7022) @[el2_ifu_mem_ctl.scala 741:64] + node _T_7024 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_7025 = and(_T_7023, _T_7024) @[el2_ifu_mem_ctl.scala 741:89] + node _T_7026 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h032")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_7027 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_7028 = and(_T_7026, _T_7027) @[el2_ifu_mem_ctl.scala 742:58] + node _T_7029 = eq(perr_ic_index_ff, UInt<6>("h032")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_7030 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_7031 = and(_T_7029, _T_7030) @[el2_ifu_mem_ctl.scala 742:123] + node _T_7032 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_7033 = and(_T_7031, _T_7032) @[el2_ifu_mem_ctl.scala 742:144] + node _T_7034 = or(_T_7028, _T_7033) @[el2_ifu_mem_ctl.scala 742:80] + node _T_7035 = bits(_T_7034, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_7036 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7035 : @[Reg.scala 28:19] _T_7036 <= _T_7025 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][50] <= _T_7036 @[el2_ifu_mem_ctl.scala 740:39] - node _T_7037 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_7038 = eq(_T_7037, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_7039 = and(ic_valid_ff, _T_7038) @[el2_ifu_mem_ctl.scala 740:64] - node _T_7040 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_7041 = and(_T_7039, _T_7040) @[el2_ifu_mem_ctl.scala 740:89] - node _T_7042 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h033")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_7043 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_7044 = and(_T_7042, _T_7043) @[el2_ifu_mem_ctl.scala 741:58] - node _T_7045 = eq(perr_ic_index_ff, UInt<6>("h033")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_7046 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_7047 = and(_T_7045, _T_7046) @[el2_ifu_mem_ctl.scala 741:123] - node _T_7048 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_7049 = and(_T_7047, _T_7048) @[el2_ifu_mem_ctl.scala 741:144] - node _T_7050 = or(_T_7044, _T_7049) @[el2_ifu_mem_ctl.scala 741:80] - node _T_7051 = bits(_T_7050, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][50] <= _T_7036 @[el2_ifu_mem_ctl.scala 741:39] + node _T_7037 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_7038 = eq(_T_7037, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_7039 = and(ic_valid_ff, _T_7038) @[el2_ifu_mem_ctl.scala 741:64] + node _T_7040 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_7041 = and(_T_7039, _T_7040) @[el2_ifu_mem_ctl.scala 741:89] + node _T_7042 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h033")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_7043 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_7044 = and(_T_7042, _T_7043) @[el2_ifu_mem_ctl.scala 742:58] + node _T_7045 = eq(perr_ic_index_ff, UInt<6>("h033")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_7046 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_7047 = and(_T_7045, _T_7046) @[el2_ifu_mem_ctl.scala 742:123] + node _T_7048 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_7049 = and(_T_7047, _T_7048) @[el2_ifu_mem_ctl.scala 742:144] + node _T_7050 = or(_T_7044, _T_7049) @[el2_ifu_mem_ctl.scala 742:80] + node _T_7051 = bits(_T_7050, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_7052 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7051 : @[Reg.scala 28:19] _T_7052 <= _T_7041 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][51] <= _T_7052 @[el2_ifu_mem_ctl.scala 740:39] - node _T_7053 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_7054 = eq(_T_7053, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_7055 = and(ic_valid_ff, _T_7054) @[el2_ifu_mem_ctl.scala 740:64] - node _T_7056 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_7057 = and(_T_7055, _T_7056) @[el2_ifu_mem_ctl.scala 740:89] - node _T_7058 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h034")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_7059 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_7060 = and(_T_7058, _T_7059) @[el2_ifu_mem_ctl.scala 741:58] - node _T_7061 = eq(perr_ic_index_ff, UInt<6>("h034")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_7062 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_7063 = and(_T_7061, _T_7062) @[el2_ifu_mem_ctl.scala 741:123] - node _T_7064 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_7065 = and(_T_7063, _T_7064) @[el2_ifu_mem_ctl.scala 741:144] - node _T_7066 = or(_T_7060, _T_7065) @[el2_ifu_mem_ctl.scala 741:80] - node _T_7067 = bits(_T_7066, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][51] <= _T_7052 @[el2_ifu_mem_ctl.scala 741:39] + node _T_7053 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_7054 = eq(_T_7053, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_7055 = and(ic_valid_ff, _T_7054) @[el2_ifu_mem_ctl.scala 741:64] + node _T_7056 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_7057 = and(_T_7055, _T_7056) @[el2_ifu_mem_ctl.scala 741:89] + node _T_7058 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h034")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_7059 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_7060 = and(_T_7058, _T_7059) @[el2_ifu_mem_ctl.scala 742:58] + node _T_7061 = eq(perr_ic_index_ff, UInt<6>("h034")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_7062 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_7063 = and(_T_7061, _T_7062) @[el2_ifu_mem_ctl.scala 742:123] + node _T_7064 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_7065 = and(_T_7063, _T_7064) @[el2_ifu_mem_ctl.scala 742:144] + node _T_7066 = or(_T_7060, _T_7065) @[el2_ifu_mem_ctl.scala 742:80] + node _T_7067 = bits(_T_7066, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_7068 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7067 : @[Reg.scala 28:19] _T_7068 <= _T_7057 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][52] <= _T_7068 @[el2_ifu_mem_ctl.scala 740:39] - node _T_7069 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_7070 = eq(_T_7069, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_7071 = and(ic_valid_ff, _T_7070) @[el2_ifu_mem_ctl.scala 740:64] - node _T_7072 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_7073 = and(_T_7071, _T_7072) @[el2_ifu_mem_ctl.scala 740:89] - node _T_7074 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h035")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_7075 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_7076 = and(_T_7074, _T_7075) @[el2_ifu_mem_ctl.scala 741:58] - node _T_7077 = eq(perr_ic_index_ff, UInt<6>("h035")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_7078 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_7079 = and(_T_7077, _T_7078) @[el2_ifu_mem_ctl.scala 741:123] - node _T_7080 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_7081 = and(_T_7079, _T_7080) @[el2_ifu_mem_ctl.scala 741:144] - node _T_7082 = or(_T_7076, _T_7081) @[el2_ifu_mem_ctl.scala 741:80] - node _T_7083 = bits(_T_7082, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][52] <= _T_7068 @[el2_ifu_mem_ctl.scala 741:39] + node _T_7069 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_7070 = eq(_T_7069, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_7071 = and(ic_valid_ff, _T_7070) @[el2_ifu_mem_ctl.scala 741:64] + node _T_7072 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_7073 = and(_T_7071, _T_7072) @[el2_ifu_mem_ctl.scala 741:89] + node _T_7074 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h035")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_7075 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_7076 = and(_T_7074, _T_7075) @[el2_ifu_mem_ctl.scala 742:58] + node _T_7077 = eq(perr_ic_index_ff, UInt<6>("h035")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_7078 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_7079 = and(_T_7077, _T_7078) @[el2_ifu_mem_ctl.scala 742:123] + node _T_7080 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_7081 = and(_T_7079, _T_7080) @[el2_ifu_mem_ctl.scala 742:144] + node _T_7082 = or(_T_7076, _T_7081) @[el2_ifu_mem_ctl.scala 742:80] + node _T_7083 = bits(_T_7082, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_7084 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7083 : @[Reg.scala 28:19] _T_7084 <= _T_7073 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][53] <= _T_7084 @[el2_ifu_mem_ctl.scala 740:39] - node _T_7085 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_7086 = eq(_T_7085, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_7087 = and(ic_valid_ff, _T_7086) @[el2_ifu_mem_ctl.scala 740:64] - node _T_7088 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_7089 = and(_T_7087, _T_7088) @[el2_ifu_mem_ctl.scala 740:89] - node _T_7090 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h036")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_7091 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_7092 = and(_T_7090, _T_7091) @[el2_ifu_mem_ctl.scala 741:58] - node _T_7093 = eq(perr_ic_index_ff, UInt<6>("h036")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_7094 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_7095 = and(_T_7093, _T_7094) @[el2_ifu_mem_ctl.scala 741:123] - node _T_7096 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_7097 = and(_T_7095, _T_7096) @[el2_ifu_mem_ctl.scala 741:144] - node _T_7098 = or(_T_7092, _T_7097) @[el2_ifu_mem_ctl.scala 741:80] - node _T_7099 = bits(_T_7098, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][53] <= _T_7084 @[el2_ifu_mem_ctl.scala 741:39] + node _T_7085 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_7086 = eq(_T_7085, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_7087 = and(ic_valid_ff, _T_7086) @[el2_ifu_mem_ctl.scala 741:64] + node _T_7088 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_7089 = and(_T_7087, _T_7088) @[el2_ifu_mem_ctl.scala 741:89] + node _T_7090 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h036")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_7091 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_7092 = and(_T_7090, _T_7091) @[el2_ifu_mem_ctl.scala 742:58] + node _T_7093 = eq(perr_ic_index_ff, UInt<6>("h036")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_7094 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_7095 = and(_T_7093, _T_7094) @[el2_ifu_mem_ctl.scala 742:123] + node _T_7096 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_7097 = and(_T_7095, _T_7096) @[el2_ifu_mem_ctl.scala 742:144] + node _T_7098 = or(_T_7092, _T_7097) @[el2_ifu_mem_ctl.scala 742:80] + node _T_7099 = bits(_T_7098, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_7100 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7099 : @[Reg.scala 28:19] _T_7100 <= _T_7089 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][54] <= _T_7100 @[el2_ifu_mem_ctl.scala 740:39] - node _T_7101 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_7102 = eq(_T_7101, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_7103 = and(ic_valid_ff, _T_7102) @[el2_ifu_mem_ctl.scala 740:64] - node _T_7104 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_7105 = and(_T_7103, _T_7104) @[el2_ifu_mem_ctl.scala 740:89] - node _T_7106 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h037")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_7107 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_7108 = and(_T_7106, _T_7107) @[el2_ifu_mem_ctl.scala 741:58] - node _T_7109 = eq(perr_ic_index_ff, UInt<6>("h037")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_7110 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_7111 = and(_T_7109, _T_7110) @[el2_ifu_mem_ctl.scala 741:123] - node _T_7112 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_7113 = and(_T_7111, _T_7112) @[el2_ifu_mem_ctl.scala 741:144] - node _T_7114 = or(_T_7108, _T_7113) @[el2_ifu_mem_ctl.scala 741:80] - node _T_7115 = bits(_T_7114, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][54] <= _T_7100 @[el2_ifu_mem_ctl.scala 741:39] + node _T_7101 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_7102 = eq(_T_7101, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_7103 = and(ic_valid_ff, _T_7102) @[el2_ifu_mem_ctl.scala 741:64] + node _T_7104 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_7105 = and(_T_7103, _T_7104) @[el2_ifu_mem_ctl.scala 741:89] + node _T_7106 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h037")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_7107 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_7108 = and(_T_7106, _T_7107) @[el2_ifu_mem_ctl.scala 742:58] + node _T_7109 = eq(perr_ic_index_ff, UInt<6>("h037")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_7110 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_7111 = and(_T_7109, _T_7110) @[el2_ifu_mem_ctl.scala 742:123] + node _T_7112 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_7113 = and(_T_7111, _T_7112) @[el2_ifu_mem_ctl.scala 742:144] + node _T_7114 = or(_T_7108, _T_7113) @[el2_ifu_mem_ctl.scala 742:80] + node _T_7115 = bits(_T_7114, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_7116 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7115 : @[Reg.scala 28:19] _T_7116 <= _T_7105 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][55] <= _T_7116 @[el2_ifu_mem_ctl.scala 740:39] - node _T_7117 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_7118 = eq(_T_7117, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_7119 = and(ic_valid_ff, _T_7118) @[el2_ifu_mem_ctl.scala 740:64] - node _T_7120 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_7121 = and(_T_7119, _T_7120) @[el2_ifu_mem_ctl.scala 740:89] - node _T_7122 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h038")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_7123 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_7124 = and(_T_7122, _T_7123) @[el2_ifu_mem_ctl.scala 741:58] - node _T_7125 = eq(perr_ic_index_ff, UInt<6>("h038")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_7126 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_7127 = and(_T_7125, _T_7126) @[el2_ifu_mem_ctl.scala 741:123] - node _T_7128 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_7129 = and(_T_7127, _T_7128) @[el2_ifu_mem_ctl.scala 741:144] - node _T_7130 = or(_T_7124, _T_7129) @[el2_ifu_mem_ctl.scala 741:80] - node _T_7131 = bits(_T_7130, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][55] <= _T_7116 @[el2_ifu_mem_ctl.scala 741:39] + node _T_7117 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_7118 = eq(_T_7117, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_7119 = and(ic_valid_ff, _T_7118) @[el2_ifu_mem_ctl.scala 741:64] + node _T_7120 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_7121 = and(_T_7119, _T_7120) @[el2_ifu_mem_ctl.scala 741:89] + node _T_7122 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h038")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_7123 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_7124 = and(_T_7122, _T_7123) @[el2_ifu_mem_ctl.scala 742:58] + node _T_7125 = eq(perr_ic_index_ff, UInt<6>("h038")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_7126 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_7127 = and(_T_7125, _T_7126) @[el2_ifu_mem_ctl.scala 742:123] + node _T_7128 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_7129 = and(_T_7127, _T_7128) @[el2_ifu_mem_ctl.scala 742:144] + node _T_7130 = or(_T_7124, _T_7129) @[el2_ifu_mem_ctl.scala 742:80] + node _T_7131 = bits(_T_7130, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_7132 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7131 : @[Reg.scala 28:19] _T_7132 <= _T_7121 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][56] <= _T_7132 @[el2_ifu_mem_ctl.scala 740:39] - node _T_7133 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_7134 = eq(_T_7133, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_7135 = and(ic_valid_ff, _T_7134) @[el2_ifu_mem_ctl.scala 740:64] - node _T_7136 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_7137 = and(_T_7135, _T_7136) @[el2_ifu_mem_ctl.scala 740:89] - node _T_7138 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h039")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_7139 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_7140 = and(_T_7138, _T_7139) @[el2_ifu_mem_ctl.scala 741:58] - node _T_7141 = eq(perr_ic_index_ff, UInt<6>("h039")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_7142 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_7143 = and(_T_7141, _T_7142) @[el2_ifu_mem_ctl.scala 741:123] - node _T_7144 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_7145 = and(_T_7143, _T_7144) @[el2_ifu_mem_ctl.scala 741:144] - node _T_7146 = or(_T_7140, _T_7145) @[el2_ifu_mem_ctl.scala 741:80] - node _T_7147 = bits(_T_7146, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][56] <= _T_7132 @[el2_ifu_mem_ctl.scala 741:39] + node _T_7133 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_7134 = eq(_T_7133, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_7135 = and(ic_valid_ff, _T_7134) @[el2_ifu_mem_ctl.scala 741:64] + node _T_7136 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_7137 = and(_T_7135, _T_7136) @[el2_ifu_mem_ctl.scala 741:89] + node _T_7138 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h039")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_7139 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_7140 = and(_T_7138, _T_7139) @[el2_ifu_mem_ctl.scala 742:58] + node _T_7141 = eq(perr_ic_index_ff, UInt<6>("h039")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_7142 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_7143 = and(_T_7141, _T_7142) @[el2_ifu_mem_ctl.scala 742:123] + node _T_7144 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_7145 = and(_T_7143, _T_7144) @[el2_ifu_mem_ctl.scala 742:144] + node _T_7146 = or(_T_7140, _T_7145) @[el2_ifu_mem_ctl.scala 742:80] + node _T_7147 = bits(_T_7146, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_7148 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7147 : @[Reg.scala 28:19] _T_7148 <= _T_7137 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][57] <= _T_7148 @[el2_ifu_mem_ctl.scala 740:39] - node _T_7149 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_7150 = eq(_T_7149, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_7151 = and(ic_valid_ff, _T_7150) @[el2_ifu_mem_ctl.scala 740:64] - node _T_7152 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_7153 = and(_T_7151, _T_7152) @[el2_ifu_mem_ctl.scala 740:89] - node _T_7154 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03a")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_7155 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_7156 = and(_T_7154, _T_7155) @[el2_ifu_mem_ctl.scala 741:58] - node _T_7157 = eq(perr_ic_index_ff, UInt<6>("h03a")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_7158 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_7159 = and(_T_7157, _T_7158) @[el2_ifu_mem_ctl.scala 741:123] - node _T_7160 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_7161 = and(_T_7159, _T_7160) @[el2_ifu_mem_ctl.scala 741:144] - node _T_7162 = or(_T_7156, _T_7161) @[el2_ifu_mem_ctl.scala 741:80] - node _T_7163 = bits(_T_7162, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][57] <= _T_7148 @[el2_ifu_mem_ctl.scala 741:39] + node _T_7149 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_7150 = eq(_T_7149, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_7151 = and(ic_valid_ff, _T_7150) @[el2_ifu_mem_ctl.scala 741:64] + node _T_7152 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_7153 = and(_T_7151, _T_7152) @[el2_ifu_mem_ctl.scala 741:89] + node _T_7154 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03a")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_7155 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_7156 = and(_T_7154, _T_7155) @[el2_ifu_mem_ctl.scala 742:58] + node _T_7157 = eq(perr_ic_index_ff, UInt<6>("h03a")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_7158 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_7159 = and(_T_7157, _T_7158) @[el2_ifu_mem_ctl.scala 742:123] + node _T_7160 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_7161 = and(_T_7159, _T_7160) @[el2_ifu_mem_ctl.scala 742:144] + node _T_7162 = or(_T_7156, _T_7161) @[el2_ifu_mem_ctl.scala 742:80] + node _T_7163 = bits(_T_7162, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_7164 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7163 : @[Reg.scala 28:19] _T_7164 <= _T_7153 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][58] <= _T_7164 @[el2_ifu_mem_ctl.scala 740:39] - node _T_7165 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_7166 = eq(_T_7165, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_7167 = and(ic_valid_ff, _T_7166) @[el2_ifu_mem_ctl.scala 740:64] - node _T_7168 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_7169 = and(_T_7167, _T_7168) @[el2_ifu_mem_ctl.scala 740:89] - node _T_7170 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03b")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_7171 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_7172 = and(_T_7170, _T_7171) @[el2_ifu_mem_ctl.scala 741:58] - node _T_7173 = eq(perr_ic_index_ff, UInt<6>("h03b")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_7174 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_7175 = and(_T_7173, _T_7174) @[el2_ifu_mem_ctl.scala 741:123] - node _T_7176 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_7177 = and(_T_7175, _T_7176) @[el2_ifu_mem_ctl.scala 741:144] - node _T_7178 = or(_T_7172, _T_7177) @[el2_ifu_mem_ctl.scala 741:80] - node _T_7179 = bits(_T_7178, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][58] <= _T_7164 @[el2_ifu_mem_ctl.scala 741:39] + node _T_7165 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_7166 = eq(_T_7165, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_7167 = and(ic_valid_ff, _T_7166) @[el2_ifu_mem_ctl.scala 741:64] + node _T_7168 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_7169 = and(_T_7167, _T_7168) @[el2_ifu_mem_ctl.scala 741:89] + node _T_7170 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03b")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_7171 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_7172 = and(_T_7170, _T_7171) @[el2_ifu_mem_ctl.scala 742:58] + node _T_7173 = eq(perr_ic_index_ff, UInt<6>("h03b")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_7174 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_7175 = and(_T_7173, _T_7174) @[el2_ifu_mem_ctl.scala 742:123] + node _T_7176 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_7177 = and(_T_7175, _T_7176) @[el2_ifu_mem_ctl.scala 742:144] + node _T_7178 = or(_T_7172, _T_7177) @[el2_ifu_mem_ctl.scala 742:80] + node _T_7179 = bits(_T_7178, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_7180 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7179 : @[Reg.scala 28:19] _T_7180 <= _T_7169 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][59] <= _T_7180 @[el2_ifu_mem_ctl.scala 740:39] - node _T_7181 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_7182 = eq(_T_7181, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_7183 = and(ic_valid_ff, _T_7182) @[el2_ifu_mem_ctl.scala 740:64] - node _T_7184 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_7185 = and(_T_7183, _T_7184) @[el2_ifu_mem_ctl.scala 740:89] - node _T_7186 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03c")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_7187 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_7188 = and(_T_7186, _T_7187) @[el2_ifu_mem_ctl.scala 741:58] - node _T_7189 = eq(perr_ic_index_ff, UInt<6>("h03c")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_7190 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_7191 = and(_T_7189, _T_7190) @[el2_ifu_mem_ctl.scala 741:123] - node _T_7192 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_7193 = and(_T_7191, _T_7192) @[el2_ifu_mem_ctl.scala 741:144] - node _T_7194 = or(_T_7188, _T_7193) @[el2_ifu_mem_ctl.scala 741:80] - node _T_7195 = bits(_T_7194, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][59] <= _T_7180 @[el2_ifu_mem_ctl.scala 741:39] + node _T_7181 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_7182 = eq(_T_7181, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_7183 = and(ic_valid_ff, _T_7182) @[el2_ifu_mem_ctl.scala 741:64] + node _T_7184 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_7185 = and(_T_7183, _T_7184) @[el2_ifu_mem_ctl.scala 741:89] + node _T_7186 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03c")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_7187 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_7188 = and(_T_7186, _T_7187) @[el2_ifu_mem_ctl.scala 742:58] + node _T_7189 = eq(perr_ic_index_ff, UInt<6>("h03c")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_7190 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_7191 = and(_T_7189, _T_7190) @[el2_ifu_mem_ctl.scala 742:123] + node _T_7192 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_7193 = and(_T_7191, _T_7192) @[el2_ifu_mem_ctl.scala 742:144] + node _T_7194 = or(_T_7188, _T_7193) @[el2_ifu_mem_ctl.scala 742:80] + node _T_7195 = bits(_T_7194, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_7196 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7195 : @[Reg.scala 28:19] _T_7196 <= _T_7185 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][60] <= _T_7196 @[el2_ifu_mem_ctl.scala 740:39] - node _T_7197 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_7198 = eq(_T_7197, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_7199 = and(ic_valid_ff, _T_7198) @[el2_ifu_mem_ctl.scala 740:64] - node _T_7200 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_7201 = and(_T_7199, _T_7200) @[el2_ifu_mem_ctl.scala 740:89] - node _T_7202 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03d")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_7203 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_7204 = and(_T_7202, _T_7203) @[el2_ifu_mem_ctl.scala 741:58] - node _T_7205 = eq(perr_ic_index_ff, UInt<6>("h03d")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_7206 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_7207 = and(_T_7205, _T_7206) @[el2_ifu_mem_ctl.scala 741:123] - node _T_7208 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_7209 = and(_T_7207, _T_7208) @[el2_ifu_mem_ctl.scala 741:144] - node _T_7210 = or(_T_7204, _T_7209) @[el2_ifu_mem_ctl.scala 741:80] - node _T_7211 = bits(_T_7210, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][60] <= _T_7196 @[el2_ifu_mem_ctl.scala 741:39] + node _T_7197 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_7198 = eq(_T_7197, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_7199 = and(ic_valid_ff, _T_7198) @[el2_ifu_mem_ctl.scala 741:64] + node _T_7200 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_7201 = and(_T_7199, _T_7200) @[el2_ifu_mem_ctl.scala 741:89] + node _T_7202 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03d")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_7203 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_7204 = and(_T_7202, _T_7203) @[el2_ifu_mem_ctl.scala 742:58] + node _T_7205 = eq(perr_ic_index_ff, UInt<6>("h03d")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_7206 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_7207 = and(_T_7205, _T_7206) @[el2_ifu_mem_ctl.scala 742:123] + node _T_7208 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_7209 = and(_T_7207, _T_7208) @[el2_ifu_mem_ctl.scala 742:144] + node _T_7210 = or(_T_7204, _T_7209) @[el2_ifu_mem_ctl.scala 742:80] + node _T_7211 = bits(_T_7210, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_7212 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7211 : @[Reg.scala 28:19] _T_7212 <= _T_7201 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][61] <= _T_7212 @[el2_ifu_mem_ctl.scala 740:39] - node _T_7213 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_7214 = eq(_T_7213, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_7215 = and(ic_valid_ff, _T_7214) @[el2_ifu_mem_ctl.scala 740:64] - node _T_7216 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_7217 = and(_T_7215, _T_7216) @[el2_ifu_mem_ctl.scala 740:89] - node _T_7218 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03e")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_7219 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_7220 = and(_T_7218, _T_7219) @[el2_ifu_mem_ctl.scala 741:58] - node _T_7221 = eq(perr_ic_index_ff, UInt<6>("h03e")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_7222 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_7223 = and(_T_7221, _T_7222) @[el2_ifu_mem_ctl.scala 741:123] - node _T_7224 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_7225 = and(_T_7223, _T_7224) @[el2_ifu_mem_ctl.scala 741:144] - node _T_7226 = or(_T_7220, _T_7225) @[el2_ifu_mem_ctl.scala 741:80] - node _T_7227 = bits(_T_7226, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][61] <= _T_7212 @[el2_ifu_mem_ctl.scala 741:39] + node _T_7213 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_7214 = eq(_T_7213, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_7215 = and(ic_valid_ff, _T_7214) @[el2_ifu_mem_ctl.scala 741:64] + node _T_7216 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_7217 = and(_T_7215, _T_7216) @[el2_ifu_mem_ctl.scala 741:89] + node _T_7218 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03e")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_7219 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_7220 = and(_T_7218, _T_7219) @[el2_ifu_mem_ctl.scala 742:58] + node _T_7221 = eq(perr_ic_index_ff, UInt<6>("h03e")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_7222 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_7223 = and(_T_7221, _T_7222) @[el2_ifu_mem_ctl.scala 742:123] + node _T_7224 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_7225 = and(_T_7223, _T_7224) @[el2_ifu_mem_ctl.scala 742:144] + node _T_7226 = or(_T_7220, _T_7225) @[el2_ifu_mem_ctl.scala 742:80] + node _T_7227 = bits(_T_7226, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_7228 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7227 : @[Reg.scala 28:19] _T_7228 <= _T_7217 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][62] <= _T_7228 @[el2_ifu_mem_ctl.scala 740:39] - node _T_7229 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_7230 = eq(_T_7229, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_7231 = and(ic_valid_ff, _T_7230) @[el2_ifu_mem_ctl.scala 740:64] - node _T_7232 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_7233 = and(_T_7231, _T_7232) @[el2_ifu_mem_ctl.scala 740:89] - node _T_7234 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03f")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_7235 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_7236 = and(_T_7234, _T_7235) @[el2_ifu_mem_ctl.scala 741:58] - node _T_7237 = eq(perr_ic_index_ff, UInt<6>("h03f")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_7238 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_7239 = and(_T_7237, _T_7238) @[el2_ifu_mem_ctl.scala 741:123] - node _T_7240 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_7241 = and(_T_7239, _T_7240) @[el2_ifu_mem_ctl.scala 741:144] - node _T_7242 = or(_T_7236, _T_7241) @[el2_ifu_mem_ctl.scala 741:80] - node _T_7243 = bits(_T_7242, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][62] <= _T_7228 @[el2_ifu_mem_ctl.scala 741:39] + node _T_7229 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_7230 = eq(_T_7229, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_7231 = and(ic_valid_ff, _T_7230) @[el2_ifu_mem_ctl.scala 741:64] + node _T_7232 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_7233 = and(_T_7231, _T_7232) @[el2_ifu_mem_ctl.scala 741:89] + node _T_7234 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03f")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_7235 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_7236 = and(_T_7234, _T_7235) @[el2_ifu_mem_ctl.scala 742:58] + node _T_7237 = eq(perr_ic_index_ff, UInt<6>("h03f")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_7238 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_7239 = and(_T_7237, _T_7238) @[el2_ifu_mem_ctl.scala 742:123] + node _T_7240 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_7241 = and(_T_7239, _T_7240) @[el2_ifu_mem_ctl.scala 742:144] + node _T_7242 = or(_T_7236, _T_7241) @[el2_ifu_mem_ctl.scala 742:80] + node _T_7243 = bits(_T_7242, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_7244 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7243 : @[Reg.scala 28:19] _T_7244 <= _T_7233 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][63] <= _T_7244 @[el2_ifu_mem_ctl.scala 740:39] - node _T_7245 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_7246 = eq(_T_7245, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_7247 = and(ic_valid_ff, _T_7246) @[el2_ifu_mem_ctl.scala 740:64] - node _T_7248 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_7249 = and(_T_7247, _T_7248) @[el2_ifu_mem_ctl.scala 740:89] - node _T_7250 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h040")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_7251 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_7252 = and(_T_7250, _T_7251) @[el2_ifu_mem_ctl.scala 741:58] - node _T_7253 = eq(perr_ic_index_ff, UInt<7>("h040")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_7254 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_7255 = and(_T_7253, _T_7254) @[el2_ifu_mem_ctl.scala 741:123] - node _T_7256 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_7257 = and(_T_7255, _T_7256) @[el2_ifu_mem_ctl.scala 741:144] - node _T_7258 = or(_T_7252, _T_7257) @[el2_ifu_mem_ctl.scala 741:80] - node _T_7259 = bits(_T_7258, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][63] <= _T_7244 @[el2_ifu_mem_ctl.scala 741:39] + node _T_7245 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_7246 = eq(_T_7245, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_7247 = and(ic_valid_ff, _T_7246) @[el2_ifu_mem_ctl.scala 741:64] + node _T_7248 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_7249 = and(_T_7247, _T_7248) @[el2_ifu_mem_ctl.scala 741:89] + node _T_7250 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h040")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_7251 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_7252 = and(_T_7250, _T_7251) @[el2_ifu_mem_ctl.scala 742:58] + node _T_7253 = eq(perr_ic_index_ff, UInt<7>("h040")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_7254 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_7255 = and(_T_7253, _T_7254) @[el2_ifu_mem_ctl.scala 742:123] + node _T_7256 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_7257 = and(_T_7255, _T_7256) @[el2_ifu_mem_ctl.scala 742:144] + node _T_7258 = or(_T_7252, _T_7257) @[el2_ifu_mem_ctl.scala 742:80] + node _T_7259 = bits(_T_7258, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_7260 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7259 : @[Reg.scala 28:19] _T_7260 <= _T_7249 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][64] <= _T_7260 @[el2_ifu_mem_ctl.scala 740:39] - node _T_7261 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_7262 = eq(_T_7261, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_7263 = and(ic_valid_ff, _T_7262) @[el2_ifu_mem_ctl.scala 740:64] - node _T_7264 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_7265 = and(_T_7263, _T_7264) @[el2_ifu_mem_ctl.scala 740:89] - node _T_7266 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h041")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_7267 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_7268 = and(_T_7266, _T_7267) @[el2_ifu_mem_ctl.scala 741:58] - node _T_7269 = eq(perr_ic_index_ff, UInt<7>("h041")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_7270 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_7271 = and(_T_7269, _T_7270) @[el2_ifu_mem_ctl.scala 741:123] - node _T_7272 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_7273 = and(_T_7271, _T_7272) @[el2_ifu_mem_ctl.scala 741:144] - node _T_7274 = or(_T_7268, _T_7273) @[el2_ifu_mem_ctl.scala 741:80] - node _T_7275 = bits(_T_7274, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][64] <= _T_7260 @[el2_ifu_mem_ctl.scala 741:39] + node _T_7261 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_7262 = eq(_T_7261, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_7263 = and(ic_valid_ff, _T_7262) @[el2_ifu_mem_ctl.scala 741:64] + node _T_7264 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_7265 = and(_T_7263, _T_7264) @[el2_ifu_mem_ctl.scala 741:89] + node _T_7266 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h041")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_7267 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_7268 = and(_T_7266, _T_7267) @[el2_ifu_mem_ctl.scala 742:58] + node _T_7269 = eq(perr_ic_index_ff, UInt<7>("h041")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_7270 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_7271 = and(_T_7269, _T_7270) @[el2_ifu_mem_ctl.scala 742:123] + node _T_7272 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_7273 = and(_T_7271, _T_7272) @[el2_ifu_mem_ctl.scala 742:144] + node _T_7274 = or(_T_7268, _T_7273) @[el2_ifu_mem_ctl.scala 742:80] + node _T_7275 = bits(_T_7274, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_7276 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7275 : @[Reg.scala 28:19] _T_7276 <= _T_7265 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][65] <= _T_7276 @[el2_ifu_mem_ctl.scala 740:39] - node _T_7277 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_7278 = eq(_T_7277, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_7279 = and(ic_valid_ff, _T_7278) @[el2_ifu_mem_ctl.scala 740:64] - node _T_7280 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_7281 = and(_T_7279, _T_7280) @[el2_ifu_mem_ctl.scala 740:89] - node _T_7282 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h042")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_7283 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_7284 = and(_T_7282, _T_7283) @[el2_ifu_mem_ctl.scala 741:58] - node _T_7285 = eq(perr_ic_index_ff, UInt<7>("h042")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_7286 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_7287 = and(_T_7285, _T_7286) @[el2_ifu_mem_ctl.scala 741:123] - node _T_7288 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_7289 = and(_T_7287, _T_7288) @[el2_ifu_mem_ctl.scala 741:144] - node _T_7290 = or(_T_7284, _T_7289) @[el2_ifu_mem_ctl.scala 741:80] - node _T_7291 = bits(_T_7290, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][65] <= _T_7276 @[el2_ifu_mem_ctl.scala 741:39] + node _T_7277 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_7278 = eq(_T_7277, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_7279 = and(ic_valid_ff, _T_7278) @[el2_ifu_mem_ctl.scala 741:64] + node _T_7280 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_7281 = and(_T_7279, _T_7280) @[el2_ifu_mem_ctl.scala 741:89] + node _T_7282 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h042")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_7283 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_7284 = and(_T_7282, _T_7283) @[el2_ifu_mem_ctl.scala 742:58] + node _T_7285 = eq(perr_ic_index_ff, UInt<7>("h042")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_7286 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_7287 = and(_T_7285, _T_7286) @[el2_ifu_mem_ctl.scala 742:123] + node _T_7288 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_7289 = and(_T_7287, _T_7288) @[el2_ifu_mem_ctl.scala 742:144] + node _T_7290 = or(_T_7284, _T_7289) @[el2_ifu_mem_ctl.scala 742:80] + node _T_7291 = bits(_T_7290, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_7292 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7291 : @[Reg.scala 28:19] _T_7292 <= _T_7281 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][66] <= _T_7292 @[el2_ifu_mem_ctl.scala 740:39] - node _T_7293 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_7294 = eq(_T_7293, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_7295 = and(ic_valid_ff, _T_7294) @[el2_ifu_mem_ctl.scala 740:64] - node _T_7296 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_7297 = and(_T_7295, _T_7296) @[el2_ifu_mem_ctl.scala 740:89] - node _T_7298 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h043")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_7299 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_7300 = and(_T_7298, _T_7299) @[el2_ifu_mem_ctl.scala 741:58] - node _T_7301 = eq(perr_ic_index_ff, UInt<7>("h043")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_7302 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_7303 = and(_T_7301, _T_7302) @[el2_ifu_mem_ctl.scala 741:123] - node _T_7304 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_7305 = and(_T_7303, _T_7304) @[el2_ifu_mem_ctl.scala 741:144] - node _T_7306 = or(_T_7300, _T_7305) @[el2_ifu_mem_ctl.scala 741:80] - node _T_7307 = bits(_T_7306, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][66] <= _T_7292 @[el2_ifu_mem_ctl.scala 741:39] + node _T_7293 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_7294 = eq(_T_7293, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_7295 = and(ic_valid_ff, _T_7294) @[el2_ifu_mem_ctl.scala 741:64] + node _T_7296 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_7297 = and(_T_7295, _T_7296) @[el2_ifu_mem_ctl.scala 741:89] + node _T_7298 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h043")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_7299 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_7300 = and(_T_7298, _T_7299) @[el2_ifu_mem_ctl.scala 742:58] + node _T_7301 = eq(perr_ic_index_ff, UInt<7>("h043")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_7302 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_7303 = and(_T_7301, _T_7302) @[el2_ifu_mem_ctl.scala 742:123] + node _T_7304 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_7305 = and(_T_7303, _T_7304) @[el2_ifu_mem_ctl.scala 742:144] + node _T_7306 = or(_T_7300, _T_7305) @[el2_ifu_mem_ctl.scala 742:80] + node _T_7307 = bits(_T_7306, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_7308 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7307 : @[Reg.scala 28:19] _T_7308 <= _T_7297 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][67] <= _T_7308 @[el2_ifu_mem_ctl.scala 740:39] - node _T_7309 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_7310 = eq(_T_7309, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_7311 = and(ic_valid_ff, _T_7310) @[el2_ifu_mem_ctl.scala 740:64] - node _T_7312 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_7313 = and(_T_7311, _T_7312) @[el2_ifu_mem_ctl.scala 740:89] - node _T_7314 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h044")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_7315 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_7316 = and(_T_7314, _T_7315) @[el2_ifu_mem_ctl.scala 741:58] - node _T_7317 = eq(perr_ic_index_ff, UInt<7>("h044")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_7318 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_7319 = and(_T_7317, _T_7318) @[el2_ifu_mem_ctl.scala 741:123] - node _T_7320 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_7321 = and(_T_7319, _T_7320) @[el2_ifu_mem_ctl.scala 741:144] - node _T_7322 = or(_T_7316, _T_7321) @[el2_ifu_mem_ctl.scala 741:80] - node _T_7323 = bits(_T_7322, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][67] <= _T_7308 @[el2_ifu_mem_ctl.scala 741:39] + node _T_7309 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_7310 = eq(_T_7309, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_7311 = and(ic_valid_ff, _T_7310) @[el2_ifu_mem_ctl.scala 741:64] + node _T_7312 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_7313 = and(_T_7311, _T_7312) @[el2_ifu_mem_ctl.scala 741:89] + node _T_7314 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h044")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_7315 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_7316 = and(_T_7314, _T_7315) @[el2_ifu_mem_ctl.scala 742:58] + node _T_7317 = eq(perr_ic_index_ff, UInt<7>("h044")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_7318 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_7319 = and(_T_7317, _T_7318) @[el2_ifu_mem_ctl.scala 742:123] + node _T_7320 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_7321 = and(_T_7319, _T_7320) @[el2_ifu_mem_ctl.scala 742:144] + node _T_7322 = or(_T_7316, _T_7321) @[el2_ifu_mem_ctl.scala 742:80] + node _T_7323 = bits(_T_7322, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_7324 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7323 : @[Reg.scala 28:19] _T_7324 <= _T_7313 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][68] <= _T_7324 @[el2_ifu_mem_ctl.scala 740:39] - node _T_7325 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_7326 = eq(_T_7325, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_7327 = and(ic_valid_ff, _T_7326) @[el2_ifu_mem_ctl.scala 740:64] - node _T_7328 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_7329 = and(_T_7327, _T_7328) @[el2_ifu_mem_ctl.scala 740:89] - node _T_7330 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h045")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_7331 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_7332 = and(_T_7330, _T_7331) @[el2_ifu_mem_ctl.scala 741:58] - node _T_7333 = eq(perr_ic_index_ff, UInt<7>("h045")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_7334 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_7335 = and(_T_7333, _T_7334) @[el2_ifu_mem_ctl.scala 741:123] - node _T_7336 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_7337 = and(_T_7335, _T_7336) @[el2_ifu_mem_ctl.scala 741:144] - node _T_7338 = or(_T_7332, _T_7337) @[el2_ifu_mem_ctl.scala 741:80] - node _T_7339 = bits(_T_7338, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][68] <= _T_7324 @[el2_ifu_mem_ctl.scala 741:39] + node _T_7325 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_7326 = eq(_T_7325, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_7327 = and(ic_valid_ff, _T_7326) @[el2_ifu_mem_ctl.scala 741:64] + node _T_7328 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_7329 = and(_T_7327, _T_7328) @[el2_ifu_mem_ctl.scala 741:89] + node _T_7330 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h045")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_7331 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_7332 = and(_T_7330, _T_7331) @[el2_ifu_mem_ctl.scala 742:58] + node _T_7333 = eq(perr_ic_index_ff, UInt<7>("h045")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_7334 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_7335 = and(_T_7333, _T_7334) @[el2_ifu_mem_ctl.scala 742:123] + node _T_7336 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_7337 = and(_T_7335, _T_7336) @[el2_ifu_mem_ctl.scala 742:144] + node _T_7338 = or(_T_7332, _T_7337) @[el2_ifu_mem_ctl.scala 742:80] + node _T_7339 = bits(_T_7338, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_7340 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7339 : @[Reg.scala 28:19] _T_7340 <= _T_7329 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][69] <= _T_7340 @[el2_ifu_mem_ctl.scala 740:39] - node _T_7341 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_7342 = eq(_T_7341, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_7343 = and(ic_valid_ff, _T_7342) @[el2_ifu_mem_ctl.scala 740:64] - node _T_7344 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_7345 = and(_T_7343, _T_7344) @[el2_ifu_mem_ctl.scala 740:89] - node _T_7346 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h046")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_7347 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_7348 = and(_T_7346, _T_7347) @[el2_ifu_mem_ctl.scala 741:58] - node _T_7349 = eq(perr_ic_index_ff, UInt<7>("h046")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_7350 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_7351 = and(_T_7349, _T_7350) @[el2_ifu_mem_ctl.scala 741:123] - node _T_7352 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_7353 = and(_T_7351, _T_7352) @[el2_ifu_mem_ctl.scala 741:144] - node _T_7354 = or(_T_7348, _T_7353) @[el2_ifu_mem_ctl.scala 741:80] - node _T_7355 = bits(_T_7354, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][69] <= _T_7340 @[el2_ifu_mem_ctl.scala 741:39] + node _T_7341 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_7342 = eq(_T_7341, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_7343 = and(ic_valid_ff, _T_7342) @[el2_ifu_mem_ctl.scala 741:64] + node _T_7344 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_7345 = and(_T_7343, _T_7344) @[el2_ifu_mem_ctl.scala 741:89] + node _T_7346 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h046")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_7347 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_7348 = and(_T_7346, _T_7347) @[el2_ifu_mem_ctl.scala 742:58] + node _T_7349 = eq(perr_ic_index_ff, UInt<7>("h046")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_7350 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_7351 = and(_T_7349, _T_7350) @[el2_ifu_mem_ctl.scala 742:123] + node _T_7352 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_7353 = and(_T_7351, _T_7352) @[el2_ifu_mem_ctl.scala 742:144] + node _T_7354 = or(_T_7348, _T_7353) @[el2_ifu_mem_ctl.scala 742:80] + node _T_7355 = bits(_T_7354, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_7356 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7355 : @[Reg.scala 28:19] _T_7356 <= _T_7345 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][70] <= _T_7356 @[el2_ifu_mem_ctl.scala 740:39] - node _T_7357 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_7358 = eq(_T_7357, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_7359 = and(ic_valid_ff, _T_7358) @[el2_ifu_mem_ctl.scala 740:64] - node _T_7360 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_7361 = and(_T_7359, _T_7360) @[el2_ifu_mem_ctl.scala 740:89] - node _T_7362 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h047")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_7363 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_7364 = and(_T_7362, _T_7363) @[el2_ifu_mem_ctl.scala 741:58] - node _T_7365 = eq(perr_ic_index_ff, UInt<7>("h047")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_7366 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_7367 = and(_T_7365, _T_7366) @[el2_ifu_mem_ctl.scala 741:123] - node _T_7368 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_7369 = and(_T_7367, _T_7368) @[el2_ifu_mem_ctl.scala 741:144] - node _T_7370 = or(_T_7364, _T_7369) @[el2_ifu_mem_ctl.scala 741:80] - node _T_7371 = bits(_T_7370, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][70] <= _T_7356 @[el2_ifu_mem_ctl.scala 741:39] + node _T_7357 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_7358 = eq(_T_7357, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_7359 = and(ic_valid_ff, _T_7358) @[el2_ifu_mem_ctl.scala 741:64] + node _T_7360 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_7361 = and(_T_7359, _T_7360) @[el2_ifu_mem_ctl.scala 741:89] + node _T_7362 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h047")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_7363 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_7364 = and(_T_7362, _T_7363) @[el2_ifu_mem_ctl.scala 742:58] + node _T_7365 = eq(perr_ic_index_ff, UInt<7>("h047")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_7366 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_7367 = and(_T_7365, _T_7366) @[el2_ifu_mem_ctl.scala 742:123] + node _T_7368 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_7369 = and(_T_7367, _T_7368) @[el2_ifu_mem_ctl.scala 742:144] + node _T_7370 = or(_T_7364, _T_7369) @[el2_ifu_mem_ctl.scala 742:80] + node _T_7371 = bits(_T_7370, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_7372 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7371 : @[Reg.scala 28:19] _T_7372 <= _T_7361 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][71] <= _T_7372 @[el2_ifu_mem_ctl.scala 740:39] - node _T_7373 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_7374 = eq(_T_7373, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_7375 = and(ic_valid_ff, _T_7374) @[el2_ifu_mem_ctl.scala 740:64] - node _T_7376 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_7377 = and(_T_7375, _T_7376) @[el2_ifu_mem_ctl.scala 740:89] - node _T_7378 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h048")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_7379 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_7380 = and(_T_7378, _T_7379) @[el2_ifu_mem_ctl.scala 741:58] - node _T_7381 = eq(perr_ic_index_ff, UInt<7>("h048")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_7382 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_7383 = and(_T_7381, _T_7382) @[el2_ifu_mem_ctl.scala 741:123] - node _T_7384 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_7385 = and(_T_7383, _T_7384) @[el2_ifu_mem_ctl.scala 741:144] - node _T_7386 = or(_T_7380, _T_7385) @[el2_ifu_mem_ctl.scala 741:80] - node _T_7387 = bits(_T_7386, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][71] <= _T_7372 @[el2_ifu_mem_ctl.scala 741:39] + node _T_7373 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_7374 = eq(_T_7373, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_7375 = and(ic_valid_ff, _T_7374) @[el2_ifu_mem_ctl.scala 741:64] + node _T_7376 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_7377 = and(_T_7375, _T_7376) @[el2_ifu_mem_ctl.scala 741:89] + node _T_7378 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h048")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_7379 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_7380 = and(_T_7378, _T_7379) @[el2_ifu_mem_ctl.scala 742:58] + node _T_7381 = eq(perr_ic_index_ff, UInt<7>("h048")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_7382 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_7383 = and(_T_7381, _T_7382) @[el2_ifu_mem_ctl.scala 742:123] + node _T_7384 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_7385 = and(_T_7383, _T_7384) @[el2_ifu_mem_ctl.scala 742:144] + node _T_7386 = or(_T_7380, _T_7385) @[el2_ifu_mem_ctl.scala 742:80] + node _T_7387 = bits(_T_7386, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_7388 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7387 : @[Reg.scala 28:19] _T_7388 <= _T_7377 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][72] <= _T_7388 @[el2_ifu_mem_ctl.scala 740:39] - node _T_7389 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_7390 = eq(_T_7389, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_7391 = and(ic_valid_ff, _T_7390) @[el2_ifu_mem_ctl.scala 740:64] - node _T_7392 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_7393 = and(_T_7391, _T_7392) @[el2_ifu_mem_ctl.scala 740:89] - node _T_7394 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h049")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_7395 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_7396 = and(_T_7394, _T_7395) @[el2_ifu_mem_ctl.scala 741:58] - node _T_7397 = eq(perr_ic_index_ff, UInt<7>("h049")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_7398 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_7399 = and(_T_7397, _T_7398) @[el2_ifu_mem_ctl.scala 741:123] - node _T_7400 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_7401 = and(_T_7399, _T_7400) @[el2_ifu_mem_ctl.scala 741:144] - node _T_7402 = or(_T_7396, _T_7401) @[el2_ifu_mem_ctl.scala 741:80] - node _T_7403 = bits(_T_7402, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][72] <= _T_7388 @[el2_ifu_mem_ctl.scala 741:39] + node _T_7389 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_7390 = eq(_T_7389, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_7391 = and(ic_valid_ff, _T_7390) @[el2_ifu_mem_ctl.scala 741:64] + node _T_7392 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_7393 = and(_T_7391, _T_7392) @[el2_ifu_mem_ctl.scala 741:89] + node _T_7394 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h049")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_7395 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_7396 = and(_T_7394, _T_7395) @[el2_ifu_mem_ctl.scala 742:58] + node _T_7397 = eq(perr_ic_index_ff, UInt<7>("h049")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_7398 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_7399 = and(_T_7397, _T_7398) @[el2_ifu_mem_ctl.scala 742:123] + node _T_7400 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_7401 = and(_T_7399, _T_7400) @[el2_ifu_mem_ctl.scala 742:144] + node _T_7402 = or(_T_7396, _T_7401) @[el2_ifu_mem_ctl.scala 742:80] + node _T_7403 = bits(_T_7402, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_7404 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7403 : @[Reg.scala 28:19] _T_7404 <= _T_7393 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][73] <= _T_7404 @[el2_ifu_mem_ctl.scala 740:39] - node _T_7405 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_7406 = eq(_T_7405, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_7407 = and(ic_valid_ff, _T_7406) @[el2_ifu_mem_ctl.scala 740:64] - node _T_7408 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_7409 = and(_T_7407, _T_7408) @[el2_ifu_mem_ctl.scala 740:89] - node _T_7410 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04a")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_7411 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_7412 = and(_T_7410, _T_7411) @[el2_ifu_mem_ctl.scala 741:58] - node _T_7413 = eq(perr_ic_index_ff, UInt<7>("h04a")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_7414 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_7415 = and(_T_7413, _T_7414) @[el2_ifu_mem_ctl.scala 741:123] - node _T_7416 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_7417 = and(_T_7415, _T_7416) @[el2_ifu_mem_ctl.scala 741:144] - node _T_7418 = or(_T_7412, _T_7417) @[el2_ifu_mem_ctl.scala 741:80] - node _T_7419 = bits(_T_7418, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][73] <= _T_7404 @[el2_ifu_mem_ctl.scala 741:39] + node _T_7405 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_7406 = eq(_T_7405, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_7407 = and(ic_valid_ff, _T_7406) @[el2_ifu_mem_ctl.scala 741:64] + node _T_7408 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_7409 = and(_T_7407, _T_7408) @[el2_ifu_mem_ctl.scala 741:89] + node _T_7410 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04a")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_7411 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_7412 = and(_T_7410, _T_7411) @[el2_ifu_mem_ctl.scala 742:58] + node _T_7413 = eq(perr_ic_index_ff, UInt<7>("h04a")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_7414 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_7415 = and(_T_7413, _T_7414) @[el2_ifu_mem_ctl.scala 742:123] + node _T_7416 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_7417 = and(_T_7415, _T_7416) @[el2_ifu_mem_ctl.scala 742:144] + node _T_7418 = or(_T_7412, _T_7417) @[el2_ifu_mem_ctl.scala 742:80] + node _T_7419 = bits(_T_7418, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_7420 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7419 : @[Reg.scala 28:19] _T_7420 <= _T_7409 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][74] <= _T_7420 @[el2_ifu_mem_ctl.scala 740:39] - node _T_7421 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_7422 = eq(_T_7421, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_7423 = and(ic_valid_ff, _T_7422) @[el2_ifu_mem_ctl.scala 740:64] - node _T_7424 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_7425 = and(_T_7423, _T_7424) @[el2_ifu_mem_ctl.scala 740:89] - node _T_7426 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04b")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_7427 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_7428 = and(_T_7426, _T_7427) @[el2_ifu_mem_ctl.scala 741:58] - node _T_7429 = eq(perr_ic_index_ff, UInt<7>("h04b")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_7430 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_7431 = and(_T_7429, _T_7430) @[el2_ifu_mem_ctl.scala 741:123] - node _T_7432 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_7433 = and(_T_7431, _T_7432) @[el2_ifu_mem_ctl.scala 741:144] - node _T_7434 = or(_T_7428, _T_7433) @[el2_ifu_mem_ctl.scala 741:80] - node _T_7435 = bits(_T_7434, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][74] <= _T_7420 @[el2_ifu_mem_ctl.scala 741:39] + node _T_7421 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_7422 = eq(_T_7421, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_7423 = and(ic_valid_ff, _T_7422) @[el2_ifu_mem_ctl.scala 741:64] + node _T_7424 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_7425 = and(_T_7423, _T_7424) @[el2_ifu_mem_ctl.scala 741:89] + node _T_7426 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04b")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_7427 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_7428 = and(_T_7426, _T_7427) @[el2_ifu_mem_ctl.scala 742:58] + node _T_7429 = eq(perr_ic_index_ff, UInt<7>("h04b")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_7430 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_7431 = and(_T_7429, _T_7430) @[el2_ifu_mem_ctl.scala 742:123] + node _T_7432 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_7433 = and(_T_7431, _T_7432) @[el2_ifu_mem_ctl.scala 742:144] + node _T_7434 = or(_T_7428, _T_7433) @[el2_ifu_mem_ctl.scala 742:80] + node _T_7435 = bits(_T_7434, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_7436 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7435 : @[Reg.scala 28:19] _T_7436 <= _T_7425 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][75] <= _T_7436 @[el2_ifu_mem_ctl.scala 740:39] - node _T_7437 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_7438 = eq(_T_7437, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_7439 = and(ic_valid_ff, _T_7438) @[el2_ifu_mem_ctl.scala 740:64] - node _T_7440 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_7441 = and(_T_7439, _T_7440) @[el2_ifu_mem_ctl.scala 740:89] - node _T_7442 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04c")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_7443 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_7444 = and(_T_7442, _T_7443) @[el2_ifu_mem_ctl.scala 741:58] - node _T_7445 = eq(perr_ic_index_ff, UInt<7>("h04c")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_7446 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_7447 = and(_T_7445, _T_7446) @[el2_ifu_mem_ctl.scala 741:123] - node _T_7448 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_7449 = and(_T_7447, _T_7448) @[el2_ifu_mem_ctl.scala 741:144] - node _T_7450 = or(_T_7444, _T_7449) @[el2_ifu_mem_ctl.scala 741:80] - node _T_7451 = bits(_T_7450, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][75] <= _T_7436 @[el2_ifu_mem_ctl.scala 741:39] + node _T_7437 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_7438 = eq(_T_7437, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_7439 = and(ic_valid_ff, _T_7438) @[el2_ifu_mem_ctl.scala 741:64] + node _T_7440 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_7441 = and(_T_7439, _T_7440) @[el2_ifu_mem_ctl.scala 741:89] + node _T_7442 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04c")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_7443 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_7444 = and(_T_7442, _T_7443) @[el2_ifu_mem_ctl.scala 742:58] + node _T_7445 = eq(perr_ic_index_ff, UInt<7>("h04c")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_7446 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_7447 = and(_T_7445, _T_7446) @[el2_ifu_mem_ctl.scala 742:123] + node _T_7448 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_7449 = and(_T_7447, _T_7448) @[el2_ifu_mem_ctl.scala 742:144] + node _T_7450 = or(_T_7444, _T_7449) @[el2_ifu_mem_ctl.scala 742:80] + node _T_7451 = bits(_T_7450, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_7452 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7451 : @[Reg.scala 28:19] _T_7452 <= _T_7441 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][76] <= _T_7452 @[el2_ifu_mem_ctl.scala 740:39] - node _T_7453 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_7454 = eq(_T_7453, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_7455 = and(ic_valid_ff, _T_7454) @[el2_ifu_mem_ctl.scala 740:64] - node _T_7456 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_7457 = and(_T_7455, _T_7456) @[el2_ifu_mem_ctl.scala 740:89] - node _T_7458 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04d")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_7459 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_7460 = and(_T_7458, _T_7459) @[el2_ifu_mem_ctl.scala 741:58] - node _T_7461 = eq(perr_ic_index_ff, UInt<7>("h04d")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_7462 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_7463 = and(_T_7461, _T_7462) @[el2_ifu_mem_ctl.scala 741:123] - node _T_7464 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_7465 = and(_T_7463, _T_7464) @[el2_ifu_mem_ctl.scala 741:144] - node _T_7466 = or(_T_7460, _T_7465) @[el2_ifu_mem_ctl.scala 741:80] - node _T_7467 = bits(_T_7466, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][76] <= _T_7452 @[el2_ifu_mem_ctl.scala 741:39] + node _T_7453 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_7454 = eq(_T_7453, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_7455 = and(ic_valid_ff, _T_7454) @[el2_ifu_mem_ctl.scala 741:64] + node _T_7456 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_7457 = and(_T_7455, _T_7456) @[el2_ifu_mem_ctl.scala 741:89] + node _T_7458 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04d")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_7459 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_7460 = and(_T_7458, _T_7459) @[el2_ifu_mem_ctl.scala 742:58] + node _T_7461 = eq(perr_ic_index_ff, UInt<7>("h04d")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_7462 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_7463 = and(_T_7461, _T_7462) @[el2_ifu_mem_ctl.scala 742:123] + node _T_7464 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_7465 = and(_T_7463, _T_7464) @[el2_ifu_mem_ctl.scala 742:144] + node _T_7466 = or(_T_7460, _T_7465) @[el2_ifu_mem_ctl.scala 742:80] + node _T_7467 = bits(_T_7466, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_7468 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7467 : @[Reg.scala 28:19] _T_7468 <= _T_7457 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][77] <= _T_7468 @[el2_ifu_mem_ctl.scala 740:39] - node _T_7469 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_7470 = eq(_T_7469, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_7471 = and(ic_valid_ff, _T_7470) @[el2_ifu_mem_ctl.scala 740:64] - node _T_7472 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_7473 = and(_T_7471, _T_7472) @[el2_ifu_mem_ctl.scala 740:89] - node _T_7474 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04e")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_7475 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_7476 = and(_T_7474, _T_7475) @[el2_ifu_mem_ctl.scala 741:58] - node _T_7477 = eq(perr_ic_index_ff, UInt<7>("h04e")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_7478 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_7479 = and(_T_7477, _T_7478) @[el2_ifu_mem_ctl.scala 741:123] - node _T_7480 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_7481 = and(_T_7479, _T_7480) @[el2_ifu_mem_ctl.scala 741:144] - node _T_7482 = or(_T_7476, _T_7481) @[el2_ifu_mem_ctl.scala 741:80] - node _T_7483 = bits(_T_7482, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][77] <= _T_7468 @[el2_ifu_mem_ctl.scala 741:39] + node _T_7469 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_7470 = eq(_T_7469, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_7471 = and(ic_valid_ff, _T_7470) @[el2_ifu_mem_ctl.scala 741:64] + node _T_7472 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_7473 = and(_T_7471, _T_7472) @[el2_ifu_mem_ctl.scala 741:89] + node _T_7474 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04e")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_7475 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_7476 = and(_T_7474, _T_7475) @[el2_ifu_mem_ctl.scala 742:58] + node _T_7477 = eq(perr_ic_index_ff, UInt<7>("h04e")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_7478 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_7479 = and(_T_7477, _T_7478) @[el2_ifu_mem_ctl.scala 742:123] + node _T_7480 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_7481 = and(_T_7479, _T_7480) @[el2_ifu_mem_ctl.scala 742:144] + node _T_7482 = or(_T_7476, _T_7481) @[el2_ifu_mem_ctl.scala 742:80] + node _T_7483 = bits(_T_7482, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_7484 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7483 : @[Reg.scala 28:19] _T_7484 <= _T_7473 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][78] <= _T_7484 @[el2_ifu_mem_ctl.scala 740:39] - node _T_7485 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_7486 = eq(_T_7485, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_7487 = and(ic_valid_ff, _T_7486) @[el2_ifu_mem_ctl.scala 740:64] - node _T_7488 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_7489 = and(_T_7487, _T_7488) @[el2_ifu_mem_ctl.scala 740:89] - node _T_7490 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04f")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_7491 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_7492 = and(_T_7490, _T_7491) @[el2_ifu_mem_ctl.scala 741:58] - node _T_7493 = eq(perr_ic_index_ff, UInt<7>("h04f")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_7494 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_7495 = and(_T_7493, _T_7494) @[el2_ifu_mem_ctl.scala 741:123] - node _T_7496 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_7497 = and(_T_7495, _T_7496) @[el2_ifu_mem_ctl.scala 741:144] - node _T_7498 = or(_T_7492, _T_7497) @[el2_ifu_mem_ctl.scala 741:80] - node _T_7499 = bits(_T_7498, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][78] <= _T_7484 @[el2_ifu_mem_ctl.scala 741:39] + node _T_7485 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_7486 = eq(_T_7485, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_7487 = and(ic_valid_ff, _T_7486) @[el2_ifu_mem_ctl.scala 741:64] + node _T_7488 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_7489 = and(_T_7487, _T_7488) @[el2_ifu_mem_ctl.scala 741:89] + node _T_7490 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04f")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_7491 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_7492 = and(_T_7490, _T_7491) @[el2_ifu_mem_ctl.scala 742:58] + node _T_7493 = eq(perr_ic_index_ff, UInt<7>("h04f")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_7494 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_7495 = and(_T_7493, _T_7494) @[el2_ifu_mem_ctl.scala 742:123] + node _T_7496 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_7497 = and(_T_7495, _T_7496) @[el2_ifu_mem_ctl.scala 742:144] + node _T_7498 = or(_T_7492, _T_7497) @[el2_ifu_mem_ctl.scala 742:80] + node _T_7499 = bits(_T_7498, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_7500 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7499 : @[Reg.scala 28:19] _T_7500 <= _T_7489 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][79] <= _T_7500 @[el2_ifu_mem_ctl.scala 740:39] - node _T_7501 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_7502 = eq(_T_7501, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_7503 = and(ic_valid_ff, _T_7502) @[el2_ifu_mem_ctl.scala 740:64] - node _T_7504 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_7505 = and(_T_7503, _T_7504) @[el2_ifu_mem_ctl.scala 740:89] - node _T_7506 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h050")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_7507 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_7508 = and(_T_7506, _T_7507) @[el2_ifu_mem_ctl.scala 741:58] - node _T_7509 = eq(perr_ic_index_ff, UInt<7>("h050")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_7510 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_7511 = and(_T_7509, _T_7510) @[el2_ifu_mem_ctl.scala 741:123] - node _T_7512 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_7513 = and(_T_7511, _T_7512) @[el2_ifu_mem_ctl.scala 741:144] - node _T_7514 = or(_T_7508, _T_7513) @[el2_ifu_mem_ctl.scala 741:80] - node _T_7515 = bits(_T_7514, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][79] <= _T_7500 @[el2_ifu_mem_ctl.scala 741:39] + node _T_7501 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_7502 = eq(_T_7501, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_7503 = and(ic_valid_ff, _T_7502) @[el2_ifu_mem_ctl.scala 741:64] + node _T_7504 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_7505 = and(_T_7503, _T_7504) @[el2_ifu_mem_ctl.scala 741:89] + node _T_7506 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h050")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_7507 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_7508 = and(_T_7506, _T_7507) @[el2_ifu_mem_ctl.scala 742:58] + node _T_7509 = eq(perr_ic_index_ff, UInt<7>("h050")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_7510 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_7511 = and(_T_7509, _T_7510) @[el2_ifu_mem_ctl.scala 742:123] + node _T_7512 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_7513 = and(_T_7511, _T_7512) @[el2_ifu_mem_ctl.scala 742:144] + node _T_7514 = or(_T_7508, _T_7513) @[el2_ifu_mem_ctl.scala 742:80] + node _T_7515 = bits(_T_7514, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_7516 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7515 : @[Reg.scala 28:19] _T_7516 <= _T_7505 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][80] <= _T_7516 @[el2_ifu_mem_ctl.scala 740:39] - node _T_7517 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_7518 = eq(_T_7517, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_7519 = and(ic_valid_ff, _T_7518) @[el2_ifu_mem_ctl.scala 740:64] - node _T_7520 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_7521 = and(_T_7519, _T_7520) @[el2_ifu_mem_ctl.scala 740:89] - node _T_7522 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h051")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_7523 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_7524 = and(_T_7522, _T_7523) @[el2_ifu_mem_ctl.scala 741:58] - node _T_7525 = eq(perr_ic_index_ff, UInt<7>("h051")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_7526 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_7527 = and(_T_7525, _T_7526) @[el2_ifu_mem_ctl.scala 741:123] - node _T_7528 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_7529 = and(_T_7527, _T_7528) @[el2_ifu_mem_ctl.scala 741:144] - node _T_7530 = or(_T_7524, _T_7529) @[el2_ifu_mem_ctl.scala 741:80] - node _T_7531 = bits(_T_7530, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][80] <= _T_7516 @[el2_ifu_mem_ctl.scala 741:39] + node _T_7517 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_7518 = eq(_T_7517, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_7519 = and(ic_valid_ff, _T_7518) @[el2_ifu_mem_ctl.scala 741:64] + node _T_7520 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_7521 = and(_T_7519, _T_7520) @[el2_ifu_mem_ctl.scala 741:89] + node _T_7522 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h051")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_7523 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_7524 = and(_T_7522, _T_7523) @[el2_ifu_mem_ctl.scala 742:58] + node _T_7525 = eq(perr_ic_index_ff, UInt<7>("h051")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_7526 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_7527 = and(_T_7525, _T_7526) @[el2_ifu_mem_ctl.scala 742:123] + node _T_7528 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_7529 = and(_T_7527, _T_7528) @[el2_ifu_mem_ctl.scala 742:144] + node _T_7530 = or(_T_7524, _T_7529) @[el2_ifu_mem_ctl.scala 742:80] + node _T_7531 = bits(_T_7530, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_7532 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7531 : @[Reg.scala 28:19] _T_7532 <= _T_7521 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][81] <= _T_7532 @[el2_ifu_mem_ctl.scala 740:39] - node _T_7533 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_7534 = eq(_T_7533, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_7535 = and(ic_valid_ff, _T_7534) @[el2_ifu_mem_ctl.scala 740:64] - node _T_7536 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_7537 = and(_T_7535, _T_7536) @[el2_ifu_mem_ctl.scala 740:89] - node _T_7538 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h052")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_7539 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_7540 = and(_T_7538, _T_7539) @[el2_ifu_mem_ctl.scala 741:58] - node _T_7541 = eq(perr_ic_index_ff, UInt<7>("h052")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_7542 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_7543 = and(_T_7541, _T_7542) @[el2_ifu_mem_ctl.scala 741:123] - node _T_7544 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_7545 = and(_T_7543, _T_7544) @[el2_ifu_mem_ctl.scala 741:144] - node _T_7546 = or(_T_7540, _T_7545) @[el2_ifu_mem_ctl.scala 741:80] - node _T_7547 = bits(_T_7546, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][81] <= _T_7532 @[el2_ifu_mem_ctl.scala 741:39] + node _T_7533 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_7534 = eq(_T_7533, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_7535 = and(ic_valid_ff, _T_7534) @[el2_ifu_mem_ctl.scala 741:64] + node _T_7536 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_7537 = and(_T_7535, _T_7536) @[el2_ifu_mem_ctl.scala 741:89] + node _T_7538 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h052")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_7539 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_7540 = and(_T_7538, _T_7539) @[el2_ifu_mem_ctl.scala 742:58] + node _T_7541 = eq(perr_ic_index_ff, UInt<7>("h052")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_7542 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_7543 = and(_T_7541, _T_7542) @[el2_ifu_mem_ctl.scala 742:123] + node _T_7544 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_7545 = and(_T_7543, _T_7544) @[el2_ifu_mem_ctl.scala 742:144] + node _T_7546 = or(_T_7540, _T_7545) @[el2_ifu_mem_ctl.scala 742:80] + node _T_7547 = bits(_T_7546, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_7548 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7547 : @[Reg.scala 28:19] _T_7548 <= _T_7537 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][82] <= _T_7548 @[el2_ifu_mem_ctl.scala 740:39] - node _T_7549 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_7550 = eq(_T_7549, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_7551 = and(ic_valid_ff, _T_7550) @[el2_ifu_mem_ctl.scala 740:64] - node _T_7552 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_7553 = and(_T_7551, _T_7552) @[el2_ifu_mem_ctl.scala 740:89] - node _T_7554 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h053")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_7555 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_7556 = and(_T_7554, _T_7555) @[el2_ifu_mem_ctl.scala 741:58] - node _T_7557 = eq(perr_ic_index_ff, UInt<7>("h053")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_7558 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_7559 = and(_T_7557, _T_7558) @[el2_ifu_mem_ctl.scala 741:123] - node _T_7560 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_7561 = and(_T_7559, _T_7560) @[el2_ifu_mem_ctl.scala 741:144] - node _T_7562 = or(_T_7556, _T_7561) @[el2_ifu_mem_ctl.scala 741:80] - node _T_7563 = bits(_T_7562, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][82] <= _T_7548 @[el2_ifu_mem_ctl.scala 741:39] + node _T_7549 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_7550 = eq(_T_7549, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_7551 = and(ic_valid_ff, _T_7550) @[el2_ifu_mem_ctl.scala 741:64] + node _T_7552 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_7553 = and(_T_7551, _T_7552) @[el2_ifu_mem_ctl.scala 741:89] + node _T_7554 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h053")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_7555 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_7556 = and(_T_7554, _T_7555) @[el2_ifu_mem_ctl.scala 742:58] + node _T_7557 = eq(perr_ic_index_ff, UInt<7>("h053")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_7558 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_7559 = and(_T_7557, _T_7558) @[el2_ifu_mem_ctl.scala 742:123] + node _T_7560 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_7561 = and(_T_7559, _T_7560) @[el2_ifu_mem_ctl.scala 742:144] + node _T_7562 = or(_T_7556, _T_7561) @[el2_ifu_mem_ctl.scala 742:80] + node _T_7563 = bits(_T_7562, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_7564 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7563 : @[Reg.scala 28:19] _T_7564 <= _T_7553 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][83] <= _T_7564 @[el2_ifu_mem_ctl.scala 740:39] - node _T_7565 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_7566 = eq(_T_7565, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_7567 = and(ic_valid_ff, _T_7566) @[el2_ifu_mem_ctl.scala 740:64] - node _T_7568 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_7569 = and(_T_7567, _T_7568) @[el2_ifu_mem_ctl.scala 740:89] - node _T_7570 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h054")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_7571 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_7572 = and(_T_7570, _T_7571) @[el2_ifu_mem_ctl.scala 741:58] - node _T_7573 = eq(perr_ic_index_ff, UInt<7>("h054")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_7574 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_7575 = and(_T_7573, _T_7574) @[el2_ifu_mem_ctl.scala 741:123] - node _T_7576 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_7577 = and(_T_7575, _T_7576) @[el2_ifu_mem_ctl.scala 741:144] - node _T_7578 = or(_T_7572, _T_7577) @[el2_ifu_mem_ctl.scala 741:80] - node _T_7579 = bits(_T_7578, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][83] <= _T_7564 @[el2_ifu_mem_ctl.scala 741:39] + node _T_7565 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_7566 = eq(_T_7565, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_7567 = and(ic_valid_ff, _T_7566) @[el2_ifu_mem_ctl.scala 741:64] + node _T_7568 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_7569 = and(_T_7567, _T_7568) @[el2_ifu_mem_ctl.scala 741:89] + node _T_7570 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h054")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_7571 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_7572 = and(_T_7570, _T_7571) @[el2_ifu_mem_ctl.scala 742:58] + node _T_7573 = eq(perr_ic_index_ff, UInt<7>("h054")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_7574 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_7575 = and(_T_7573, _T_7574) @[el2_ifu_mem_ctl.scala 742:123] + node _T_7576 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_7577 = and(_T_7575, _T_7576) @[el2_ifu_mem_ctl.scala 742:144] + node _T_7578 = or(_T_7572, _T_7577) @[el2_ifu_mem_ctl.scala 742:80] + node _T_7579 = bits(_T_7578, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_7580 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7579 : @[Reg.scala 28:19] _T_7580 <= _T_7569 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][84] <= _T_7580 @[el2_ifu_mem_ctl.scala 740:39] - node _T_7581 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_7582 = eq(_T_7581, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_7583 = and(ic_valid_ff, _T_7582) @[el2_ifu_mem_ctl.scala 740:64] - node _T_7584 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_7585 = and(_T_7583, _T_7584) @[el2_ifu_mem_ctl.scala 740:89] - node _T_7586 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h055")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_7587 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_7588 = and(_T_7586, _T_7587) @[el2_ifu_mem_ctl.scala 741:58] - node _T_7589 = eq(perr_ic_index_ff, UInt<7>("h055")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_7590 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_7591 = and(_T_7589, _T_7590) @[el2_ifu_mem_ctl.scala 741:123] - node _T_7592 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_7593 = and(_T_7591, _T_7592) @[el2_ifu_mem_ctl.scala 741:144] - node _T_7594 = or(_T_7588, _T_7593) @[el2_ifu_mem_ctl.scala 741:80] - node _T_7595 = bits(_T_7594, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][84] <= _T_7580 @[el2_ifu_mem_ctl.scala 741:39] + node _T_7581 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_7582 = eq(_T_7581, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_7583 = and(ic_valid_ff, _T_7582) @[el2_ifu_mem_ctl.scala 741:64] + node _T_7584 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_7585 = and(_T_7583, _T_7584) @[el2_ifu_mem_ctl.scala 741:89] + node _T_7586 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h055")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_7587 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_7588 = and(_T_7586, _T_7587) @[el2_ifu_mem_ctl.scala 742:58] + node _T_7589 = eq(perr_ic_index_ff, UInt<7>("h055")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_7590 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_7591 = and(_T_7589, _T_7590) @[el2_ifu_mem_ctl.scala 742:123] + node _T_7592 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_7593 = and(_T_7591, _T_7592) @[el2_ifu_mem_ctl.scala 742:144] + node _T_7594 = or(_T_7588, _T_7593) @[el2_ifu_mem_ctl.scala 742:80] + node _T_7595 = bits(_T_7594, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_7596 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7595 : @[Reg.scala 28:19] _T_7596 <= _T_7585 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][85] <= _T_7596 @[el2_ifu_mem_ctl.scala 740:39] - node _T_7597 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_7598 = eq(_T_7597, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_7599 = and(ic_valid_ff, _T_7598) @[el2_ifu_mem_ctl.scala 740:64] - node _T_7600 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_7601 = and(_T_7599, _T_7600) @[el2_ifu_mem_ctl.scala 740:89] - node _T_7602 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h056")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_7603 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_7604 = and(_T_7602, _T_7603) @[el2_ifu_mem_ctl.scala 741:58] - node _T_7605 = eq(perr_ic_index_ff, UInt<7>("h056")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_7606 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_7607 = and(_T_7605, _T_7606) @[el2_ifu_mem_ctl.scala 741:123] - node _T_7608 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_7609 = and(_T_7607, _T_7608) @[el2_ifu_mem_ctl.scala 741:144] - node _T_7610 = or(_T_7604, _T_7609) @[el2_ifu_mem_ctl.scala 741:80] - node _T_7611 = bits(_T_7610, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][85] <= _T_7596 @[el2_ifu_mem_ctl.scala 741:39] + node _T_7597 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_7598 = eq(_T_7597, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_7599 = and(ic_valid_ff, _T_7598) @[el2_ifu_mem_ctl.scala 741:64] + node _T_7600 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_7601 = and(_T_7599, _T_7600) @[el2_ifu_mem_ctl.scala 741:89] + node _T_7602 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h056")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_7603 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_7604 = and(_T_7602, _T_7603) @[el2_ifu_mem_ctl.scala 742:58] + node _T_7605 = eq(perr_ic_index_ff, UInt<7>("h056")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_7606 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_7607 = and(_T_7605, _T_7606) @[el2_ifu_mem_ctl.scala 742:123] + node _T_7608 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_7609 = and(_T_7607, _T_7608) @[el2_ifu_mem_ctl.scala 742:144] + node _T_7610 = or(_T_7604, _T_7609) @[el2_ifu_mem_ctl.scala 742:80] + node _T_7611 = bits(_T_7610, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_7612 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7611 : @[Reg.scala 28:19] _T_7612 <= _T_7601 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][86] <= _T_7612 @[el2_ifu_mem_ctl.scala 740:39] - node _T_7613 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_7614 = eq(_T_7613, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_7615 = and(ic_valid_ff, _T_7614) @[el2_ifu_mem_ctl.scala 740:64] - node _T_7616 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_7617 = and(_T_7615, _T_7616) @[el2_ifu_mem_ctl.scala 740:89] - node _T_7618 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h057")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_7619 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_7620 = and(_T_7618, _T_7619) @[el2_ifu_mem_ctl.scala 741:58] - node _T_7621 = eq(perr_ic_index_ff, UInt<7>("h057")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_7622 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_7623 = and(_T_7621, _T_7622) @[el2_ifu_mem_ctl.scala 741:123] - node _T_7624 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_7625 = and(_T_7623, _T_7624) @[el2_ifu_mem_ctl.scala 741:144] - node _T_7626 = or(_T_7620, _T_7625) @[el2_ifu_mem_ctl.scala 741:80] - node _T_7627 = bits(_T_7626, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][86] <= _T_7612 @[el2_ifu_mem_ctl.scala 741:39] + node _T_7613 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_7614 = eq(_T_7613, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_7615 = and(ic_valid_ff, _T_7614) @[el2_ifu_mem_ctl.scala 741:64] + node _T_7616 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_7617 = and(_T_7615, _T_7616) @[el2_ifu_mem_ctl.scala 741:89] + node _T_7618 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h057")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_7619 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_7620 = and(_T_7618, _T_7619) @[el2_ifu_mem_ctl.scala 742:58] + node _T_7621 = eq(perr_ic_index_ff, UInt<7>("h057")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_7622 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_7623 = and(_T_7621, _T_7622) @[el2_ifu_mem_ctl.scala 742:123] + node _T_7624 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_7625 = and(_T_7623, _T_7624) @[el2_ifu_mem_ctl.scala 742:144] + node _T_7626 = or(_T_7620, _T_7625) @[el2_ifu_mem_ctl.scala 742:80] + node _T_7627 = bits(_T_7626, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_7628 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7627 : @[Reg.scala 28:19] _T_7628 <= _T_7617 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][87] <= _T_7628 @[el2_ifu_mem_ctl.scala 740:39] - node _T_7629 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_7630 = eq(_T_7629, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_7631 = and(ic_valid_ff, _T_7630) @[el2_ifu_mem_ctl.scala 740:64] - node _T_7632 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_7633 = and(_T_7631, _T_7632) @[el2_ifu_mem_ctl.scala 740:89] - node _T_7634 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h058")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_7635 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_7636 = and(_T_7634, _T_7635) @[el2_ifu_mem_ctl.scala 741:58] - node _T_7637 = eq(perr_ic_index_ff, UInt<7>("h058")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_7638 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_7639 = and(_T_7637, _T_7638) @[el2_ifu_mem_ctl.scala 741:123] - node _T_7640 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_7641 = and(_T_7639, _T_7640) @[el2_ifu_mem_ctl.scala 741:144] - node _T_7642 = or(_T_7636, _T_7641) @[el2_ifu_mem_ctl.scala 741:80] - node _T_7643 = bits(_T_7642, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][87] <= _T_7628 @[el2_ifu_mem_ctl.scala 741:39] + node _T_7629 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_7630 = eq(_T_7629, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_7631 = and(ic_valid_ff, _T_7630) @[el2_ifu_mem_ctl.scala 741:64] + node _T_7632 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_7633 = and(_T_7631, _T_7632) @[el2_ifu_mem_ctl.scala 741:89] + node _T_7634 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h058")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_7635 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_7636 = and(_T_7634, _T_7635) @[el2_ifu_mem_ctl.scala 742:58] + node _T_7637 = eq(perr_ic_index_ff, UInt<7>("h058")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_7638 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_7639 = and(_T_7637, _T_7638) @[el2_ifu_mem_ctl.scala 742:123] + node _T_7640 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_7641 = and(_T_7639, _T_7640) @[el2_ifu_mem_ctl.scala 742:144] + node _T_7642 = or(_T_7636, _T_7641) @[el2_ifu_mem_ctl.scala 742:80] + node _T_7643 = bits(_T_7642, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_7644 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7643 : @[Reg.scala 28:19] _T_7644 <= _T_7633 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][88] <= _T_7644 @[el2_ifu_mem_ctl.scala 740:39] - node _T_7645 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_7646 = eq(_T_7645, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_7647 = and(ic_valid_ff, _T_7646) @[el2_ifu_mem_ctl.scala 740:64] - node _T_7648 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_7649 = and(_T_7647, _T_7648) @[el2_ifu_mem_ctl.scala 740:89] - node _T_7650 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h059")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_7651 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_7652 = and(_T_7650, _T_7651) @[el2_ifu_mem_ctl.scala 741:58] - node _T_7653 = eq(perr_ic_index_ff, UInt<7>("h059")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_7654 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_7655 = and(_T_7653, _T_7654) @[el2_ifu_mem_ctl.scala 741:123] - node _T_7656 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_7657 = and(_T_7655, _T_7656) @[el2_ifu_mem_ctl.scala 741:144] - node _T_7658 = or(_T_7652, _T_7657) @[el2_ifu_mem_ctl.scala 741:80] - node _T_7659 = bits(_T_7658, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][88] <= _T_7644 @[el2_ifu_mem_ctl.scala 741:39] + node _T_7645 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_7646 = eq(_T_7645, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_7647 = and(ic_valid_ff, _T_7646) @[el2_ifu_mem_ctl.scala 741:64] + node _T_7648 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_7649 = and(_T_7647, _T_7648) @[el2_ifu_mem_ctl.scala 741:89] + node _T_7650 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h059")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_7651 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_7652 = and(_T_7650, _T_7651) @[el2_ifu_mem_ctl.scala 742:58] + node _T_7653 = eq(perr_ic_index_ff, UInt<7>("h059")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_7654 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_7655 = and(_T_7653, _T_7654) @[el2_ifu_mem_ctl.scala 742:123] + node _T_7656 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_7657 = and(_T_7655, _T_7656) @[el2_ifu_mem_ctl.scala 742:144] + node _T_7658 = or(_T_7652, _T_7657) @[el2_ifu_mem_ctl.scala 742:80] + node _T_7659 = bits(_T_7658, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_7660 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7659 : @[Reg.scala 28:19] _T_7660 <= _T_7649 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][89] <= _T_7660 @[el2_ifu_mem_ctl.scala 740:39] - node _T_7661 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_7662 = eq(_T_7661, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_7663 = and(ic_valid_ff, _T_7662) @[el2_ifu_mem_ctl.scala 740:64] - node _T_7664 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_7665 = and(_T_7663, _T_7664) @[el2_ifu_mem_ctl.scala 740:89] - node _T_7666 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05a")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_7667 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_7668 = and(_T_7666, _T_7667) @[el2_ifu_mem_ctl.scala 741:58] - node _T_7669 = eq(perr_ic_index_ff, UInt<7>("h05a")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_7670 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_7671 = and(_T_7669, _T_7670) @[el2_ifu_mem_ctl.scala 741:123] - node _T_7672 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_7673 = and(_T_7671, _T_7672) @[el2_ifu_mem_ctl.scala 741:144] - node _T_7674 = or(_T_7668, _T_7673) @[el2_ifu_mem_ctl.scala 741:80] - node _T_7675 = bits(_T_7674, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][89] <= _T_7660 @[el2_ifu_mem_ctl.scala 741:39] + node _T_7661 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_7662 = eq(_T_7661, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_7663 = and(ic_valid_ff, _T_7662) @[el2_ifu_mem_ctl.scala 741:64] + node _T_7664 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_7665 = and(_T_7663, _T_7664) @[el2_ifu_mem_ctl.scala 741:89] + node _T_7666 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05a")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_7667 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_7668 = and(_T_7666, _T_7667) @[el2_ifu_mem_ctl.scala 742:58] + node _T_7669 = eq(perr_ic_index_ff, UInt<7>("h05a")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_7670 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_7671 = and(_T_7669, _T_7670) @[el2_ifu_mem_ctl.scala 742:123] + node _T_7672 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_7673 = and(_T_7671, _T_7672) @[el2_ifu_mem_ctl.scala 742:144] + node _T_7674 = or(_T_7668, _T_7673) @[el2_ifu_mem_ctl.scala 742:80] + node _T_7675 = bits(_T_7674, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_7676 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7675 : @[Reg.scala 28:19] _T_7676 <= _T_7665 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][90] <= _T_7676 @[el2_ifu_mem_ctl.scala 740:39] - node _T_7677 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_7678 = eq(_T_7677, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_7679 = and(ic_valid_ff, _T_7678) @[el2_ifu_mem_ctl.scala 740:64] - node _T_7680 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_7681 = and(_T_7679, _T_7680) @[el2_ifu_mem_ctl.scala 740:89] - node _T_7682 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05b")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_7683 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_7684 = and(_T_7682, _T_7683) @[el2_ifu_mem_ctl.scala 741:58] - node _T_7685 = eq(perr_ic_index_ff, UInt<7>("h05b")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_7686 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_7687 = and(_T_7685, _T_7686) @[el2_ifu_mem_ctl.scala 741:123] - node _T_7688 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_7689 = and(_T_7687, _T_7688) @[el2_ifu_mem_ctl.scala 741:144] - node _T_7690 = or(_T_7684, _T_7689) @[el2_ifu_mem_ctl.scala 741:80] - node _T_7691 = bits(_T_7690, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][90] <= _T_7676 @[el2_ifu_mem_ctl.scala 741:39] + node _T_7677 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_7678 = eq(_T_7677, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_7679 = and(ic_valid_ff, _T_7678) @[el2_ifu_mem_ctl.scala 741:64] + node _T_7680 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_7681 = and(_T_7679, _T_7680) @[el2_ifu_mem_ctl.scala 741:89] + node _T_7682 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05b")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_7683 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_7684 = and(_T_7682, _T_7683) @[el2_ifu_mem_ctl.scala 742:58] + node _T_7685 = eq(perr_ic_index_ff, UInt<7>("h05b")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_7686 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_7687 = and(_T_7685, _T_7686) @[el2_ifu_mem_ctl.scala 742:123] + node _T_7688 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_7689 = and(_T_7687, _T_7688) @[el2_ifu_mem_ctl.scala 742:144] + node _T_7690 = or(_T_7684, _T_7689) @[el2_ifu_mem_ctl.scala 742:80] + node _T_7691 = bits(_T_7690, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_7692 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7691 : @[Reg.scala 28:19] _T_7692 <= _T_7681 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][91] <= _T_7692 @[el2_ifu_mem_ctl.scala 740:39] - node _T_7693 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_7694 = eq(_T_7693, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_7695 = and(ic_valid_ff, _T_7694) @[el2_ifu_mem_ctl.scala 740:64] - node _T_7696 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_7697 = and(_T_7695, _T_7696) @[el2_ifu_mem_ctl.scala 740:89] - node _T_7698 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05c")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_7699 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_7700 = and(_T_7698, _T_7699) @[el2_ifu_mem_ctl.scala 741:58] - node _T_7701 = eq(perr_ic_index_ff, UInt<7>("h05c")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_7702 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_7703 = and(_T_7701, _T_7702) @[el2_ifu_mem_ctl.scala 741:123] - node _T_7704 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_7705 = and(_T_7703, _T_7704) @[el2_ifu_mem_ctl.scala 741:144] - node _T_7706 = or(_T_7700, _T_7705) @[el2_ifu_mem_ctl.scala 741:80] - node _T_7707 = bits(_T_7706, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][91] <= _T_7692 @[el2_ifu_mem_ctl.scala 741:39] + node _T_7693 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_7694 = eq(_T_7693, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_7695 = and(ic_valid_ff, _T_7694) @[el2_ifu_mem_ctl.scala 741:64] + node _T_7696 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_7697 = and(_T_7695, _T_7696) @[el2_ifu_mem_ctl.scala 741:89] + node _T_7698 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05c")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_7699 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_7700 = and(_T_7698, _T_7699) @[el2_ifu_mem_ctl.scala 742:58] + node _T_7701 = eq(perr_ic_index_ff, UInt<7>("h05c")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_7702 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_7703 = and(_T_7701, _T_7702) @[el2_ifu_mem_ctl.scala 742:123] + node _T_7704 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_7705 = and(_T_7703, _T_7704) @[el2_ifu_mem_ctl.scala 742:144] + node _T_7706 = or(_T_7700, _T_7705) @[el2_ifu_mem_ctl.scala 742:80] + node _T_7707 = bits(_T_7706, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_7708 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7707 : @[Reg.scala 28:19] _T_7708 <= _T_7697 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][92] <= _T_7708 @[el2_ifu_mem_ctl.scala 740:39] - node _T_7709 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_7710 = eq(_T_7709, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_7711 = and(ic_valid_ff, _T_7710) @[el2_ifu_mem_ctl.scala 740:64] - node _T_7712 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_7713 = and(_T_7711, _T_7712) @[el2_ifu_mem_ctl.scala 740:89] - node _T_7714 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05d")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_7715 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_7716 = and(_T_7714, _T_7715) @[el2_ifu_mem_ctl.scala 741:58] - node _T_7717 = eq(perr_ic_index_ff, UInt<7>("h05d")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_7718 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_7719 = and(_T_7717, _T_7718) @[el2_ifu_mem_ctl.scala 741:123] - node _T_7720 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_7721 = and(_T_7719, _T_7720) @[el2_ifu_mem_ctl.scala 741:144] - node _T_7722 = or(_T_7716, _T_7721) @[el2_ifu_mem_ctl.scala 741:80] - node _T_7723 = bits(_T_7722, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][92] <= _T_7708 @[el2_ifu_mem_ctl.scala 741:39] + node _T_7709 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_7710 = eq(_T_7709, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_7711 = and(ic_valid_ff, _T_7710) @[el2_ifu_mem_ctl.scala 741:64] + node _T_7712 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_7713 = and(_T_7711, _T_7712) @[el2_ifu_mem_ctl.scala 741:89] + node _T_7714 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05d")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_7715 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_7716 = and(_T_7714, _T_7715) @[el2_ifu_mem_ctl.scala 742:58] + node _T_7717 = eq(perr_ic_index_ff, UInt<7>("h05d")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_7718 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_7719 = and(_T_7717, _T_7718) @[el2_ifu_mem_ctl.scala 742:123] + node _T_7720 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_7721 = and(_T_7719, _T_7720) @[el2_ifu_mem_ctl.scala 742:144] + node _T_7722 = or(_T_7716, _T_7721) @[el2_ifu_mem_ctl.scala 742:80] + node _T_7723 = bits(_T_7722, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_7724 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7723 : @[Reg.scala 28:19] _T_7724 <= _T_7713 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][93] <= _T_7724 @[el2_ifu_mem_ctl.scala 740:39] - node _T_7725 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_7726 = eq(_T_7725, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_7727 = and(ic_valid_ff, _T_7726) @[el2_ifu_mem_ctl.scala 740:64] - node _T_7728 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_7729 = and(_T_7727, _T_7728) @[el2_ifu_mem_ctl.scala 740:89] - node _T_7730 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05e")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_7731 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_7732 = and(_T_7730, _T_7731) @[el2_ifu_mem_ctl.scala 741:58] - node _T_7733 = eq(perr_ic_index_ff, UInt<7>("h05e")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_7734 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_7735 = and(_T_7733, _T_7734) @[el2_ifu_mem_ctl.scala 741:123] - node _T_7736 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_7737 = and(_T_7735, _T_7736) @[el2_ifu_mem_ctl.scala 741:144] - node _T_7738 = or(_T_7732, _T_7737) @[el2_ifu_mem_ctl.scala 741:80] - node _T_7739 = bits(_T_7738, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][93] <= _T_7724 @[el2_ifu_mem_ctl.scala 741:39] + node _T_7725 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_7726 = eq(_T_7725, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_7727 = and(ic_valid_ff, _T_7726) @[el2_ifu_mem_ctl.scala 741:64] + node _T_7728 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_7729 = and(_T_7727, _T_7728) @[el2_ifu_mem_ctl.scala 741:89] + node _T_7730 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05e")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_7731 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_7732 = and(_T_7730, _T_7731) @[el2_ifu_mem_ctl.scala 742:58] + node _T_7733 = eq(perr_ic_index_ff, UInt<7>("h05e")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_7734 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_7735 = and(_T_7733, _T_7734) @[el2_ifu_mem_ctl.scala 742:123] + node _T_7736 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_7737 = and(_T_7735, _T_7736) @[el2_ifu_mem_ctl.scala 742:144] + node _T_7738 = or(_T_7732, _T_7737) @[el2_ifu_mem_ctl.scala 742:80] + node _T_7739 = bits(_T_7738, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_7740 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7739 : @[Reg.scala 28:19] _T_7740 <= _T_7729 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][94] <= _T_7740 @[el2_ifu_mem_ctl.scala 740:39] - node _T_7741 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_7742 = eq(_T_7741, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_7743 = and(ic_valid_ff, _T_7742) @[el2_ifu_mem_ctl.scala 740:64] - node _T_7744 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_7745 = and(_T_7743, _T_7744) @[el2_ifu_mem_ctl.scala 740:89] - node _T_7746 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05f")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_7747 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_7748 = and(_T_7746, _T_7747) @[el2_ifu_mem_ctl.scala 741:58] - node _T_7749 = eq(perr_ic_index_ff, UInt<7>("h05f")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_7750 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_7751 = and(_T_7749, _T_7750) @[el2_ifu_mem_ctl.scala 741:123] - node _T_7752 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_7753 = and(_T_7751, _T_7752) @[el2_ifu_mem_ctl.scala 741:144] - node _T_7754 = or(_T_7748, _T_7753) @[el2_ifu_mem_ctl.scala 741:80] - node _T_7755 = bits(_T_7754, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][94] <= _T_7740 @[el2_ifu_mem_ctl.scala 741:39] + node _T_7741 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_7742 = eq(_T_7741, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_7743 = and(ic_valid_ff, _T_7742) @[el2_ifu_mem_ctl.scala 741:64] + node _T_7744 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_7745 = and(_T_7743, _T_7744) @[el2_ifu_mem_ctl.scala 741:89] + node _T_7746 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05f")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_7747 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_7748 = and(_T_7746, _T_7747) @[el2_ifu_mem_ctl.scala 742:58] + node _T_7749 = eq(perr_ic_index_ff, UInt<7>("h05f")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_7750 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_7751 = and(_T_7749, _T_7750) @[el2_ifu_mem_ctl.scala 742:123] + node _T_7752 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_7753 = and(_T_7751, _T_7752) @[el2_ifu_mem_ctl.scala 742:144] + node _T_7754 = or(_T_7748, _T_7753) @[el2_ifu_mem_ctl.scala 742:80] + node _T_7755 = bits(_T_7754, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_7756 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7755 : @[Reg.scala 28:19] _T_7756 <= _T_7745 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][95] <= _T_7756 @[el2_ifu_mem_ctl.scala 740:39] - node _T_7757 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_7758 = eq(_T_7757, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_7759 = and(ic_valid_ff, _T_7758) @[el2_ifu_mem_ctl.scala 740:64] - node _T_7760 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_7761 = and(_T_7759, _T_7760) @[el2_ifu_mem_ctl.scala 740:89] - node _T_7762 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h040")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_7763 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_7764 = and(_T_7762, _T_7763) @[el2_ifu_mem_ctl.scala 741:58] - node _T_7765 = eq(perr_ic_index_ff, UInt<7>("h040")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_7766 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_7767 = and(_T_7765, _T_7766) @[el2_ifu_mem_ctl.scala 741:123] - node _T_7768 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_7769 = and(_T_7767, _T_7768) @[el2_ifu_mem_ctl.scala 741:144] - node _T_7770 = or(_T_7764, _T_7769) @[el2_ifu_mem_ctl.scala 741:80] - node _T_7771 = bits(_T_7770, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][95] <= _T_7756 @[el2_ifu_mem_ctl.scala 741:39] + node _T_7757 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_7758 = eq(_T_7757, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_7759 = and(ic_valid_ff, _T_7758) @[el2_ifu_mem_ctl.scala 741:64] + node _T_7760 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_7761 = and(_T_7759, _T_7760) @[el2_ifu_mem_ctl.scala 741:89] + node _T_7762 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h040")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_7763 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_7764 = and(_T_7762, _T_7763) @[el2_ifu_mem_ctl.scala 742:58] + node _T_7765 = eq(perr_ic_index_ff, UInt<7>("h040")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_7766 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_7767 = and(_T_7765, _T_7766) @[el2_ifu_mem_ctl.scala 742:123] + node _T_7768 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_7769 = and(_T_7767, _T_7768) @[el2_ifu_mem_ctl.scala 742:144] + node _T_7770 = or(_T_7764, _T_7769) @[el2_ifu_mem_ctl.scala 742:80] + node _T_7771 = bits(_T_7770, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_7772 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7771 : @[Reg.scala 28:19] _T_7772 <= _T_7761 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][64] <= _T_7772 @[el2_ifu_mem_ctl.scala 740:39] - node _T_7773 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_7774 = eq(_T_7773, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_7775 = and(ic_valid_ff, _T_7774) @[el2_ifu_mem_ctl.scala 740:64] - node _T_7776 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_7777 = and(_T_7775, _T_7776) @[el2_ifu_mem_ctl.scala 740:89] - node _T_7778 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h041")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_7779 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_7780 = and(_T_7778, _T_7779) @[el2_ifu_mem_ctl.scala 741:58] - node _T_7781 = eq(perr_ic_index_ff, UInt<7>("h041")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_7782 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_7783 = and(_T_7781, _T_7782) @[el2_ifu_mem_ctl.scala 741:123] - node _T_7784 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_7785 = and(_T_7783, _T_7784) @[el2_ifu_mem_ctl.scala 741:144] - node _T_7786 = or(_T_7780, _T_7785) @[el2_ifu_mem_ctl.scala 741:80] - node _T_7787 = bits(_T_7786, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][64] <= _T_7772 @[el2_ifu_mem_ctl.scala 741:39] + node _T_7773 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_7774 = eq(_T_7773, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_7775 = and(ic_valid_ff, _T_7774) @[el2_ifu_mem_ctl.scala 741:64] + node _T_7776 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_7777 = and(_T_7775, _T_7776) @[el2_ifu_mem_ctl.scala 741:89] + node _T_7778 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h041")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_7779 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_7780 = and(_T_7778, _T_7779) @[el2_ifu_mem_ctl.scala 742:58] + node _T_7781 = eq(perr_ic_index_ff, UInt<7>("h041")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_7782 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_7783 = and(_T_7781, _T_7782) @[el2_ifu_mem_ctl.scala 742:123] + node _T_7784 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_7785 = and(_T_7783, _T_7784) @[el2_ifu_mem_ctl.scala 742:144] + node _T_7786 = or(_T_7780, _T_7785) @[el2_ifu_mem_ctl.scala 742:80] + node _T_7787 = bits(_T_7786, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_7788 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7787 : @[Reg.scala 28:19] _T_7788 <= _T_7777 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][65] <= _T_7788 @[el2_ifu_mem_ctl.scala 740:39] - node _T_7789 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_7790 = eq(_T_7789, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_7791 = and(ic_valid_ff, _T_7790) @[el2_ifu_mem_ctl.scala 740:64] - node _T_7792 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_7793 = and(_T_7791, _T_7792) @[el2_ifu_mem_ctl.scala 740:89] - node _T_7794 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h042")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_7795 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_7796 = and(_T_7794, _T_7795) @[el2_ifu_mem_ctl.scala 741:58] - node _T_7797 = eq(perr_ic_index_ff, UInt<7>("h042")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_7798 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_7799 = and(_T_7797, _T_7798) @[el2_ifu_mem_ctl.scala 741:123] - node _T_7800 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_7801 = and(_T_7799, _T_7800) @[el2_ifu_mem_ctl.scala 741:144] - node _T_7802 = or(_T_7796, _T_7801) @[el2_ifu_mem_ctl.scala 741:80] - node _T_7803 = bits(_T_7802, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][65] <= _T_7788 @[el2_ifu_mem_ctl.scala 741:39] + node _T_7789 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_7790 = eq(_T_7789, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_7791 = and(ic_valid_ff, _T_7790) @[el2_ifu_mem_ctl.scala 741:64] + node _T_7792 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_7793 = and(_T_7791, _T_7792) @[el2_ifu_mem_ctl.scala 741:89] + node _T_7794 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h042")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_7795 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_7796 = and(_T_7794, _T_7795) @[el2_ifu_mem_ctl.scala 742:58] + node _T_7797 = eq(perr_ic_index_ff, UInt<7>("h042")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_7798 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_7799 = and(_T_7797, _T_7798) @[el2_ifu_mem_ctl.scala 742:123] + node _T_7800 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_7801 = and(_T_7799, _T_7800) @[el2_ifu_mem_ctl.scala 742:144] + node _T_7802 = or(_T_7796, _T_7801) @[el2_ifu_mem_ctl.scala 742:80] + node _T_7803 = bits(_T_7802, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_7804 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7803 : @[Reg.scala 28:19] _T_7804 <= _T_7793 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][66] <= _T_7804 @[el2_ifu_mem_ctl.scala 740:39] - node _T_7805 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_7806 = eq(_T_7805, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_7807 = and(ic_valid_ff, _T_7806) @[el2_ifu_mem_ctl.scala 740:64] - node _T_7808 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_7809 = and(_T_7807, _T_7808) @[el2_ifu_mem_ctl.scala 740:89] - node _T_7810 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h043")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_7811 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_7812 = and(_T_7810, _T_7811) @[el2_ifu_mem_ctl.scala 741:58] - node _T_7813 = eq(perr_ic_index_ff, UInt<7>("h043")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_7814 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_7815 = and(_T_7813, _T_7814) @[el2_ifu_mem_ctl.scala 741:123] - node _T_7816 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_7817 = and(_T_7815, _T_7816) @[el2_ifu_mem_ctl.scala 741:144] - node _T_7818 = or(_T_7812, _T_7817) @[el2_ifu_mem_ctl.scala 741:80] - node _T_7819 = bits(_T_7818, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][66] <= _T_7804 @[el2_ifu_mem_ctl.scala 741:39] + node _T_7805 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_7806 = eq(_T_7805, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_7807 = and(ic_valid_ff, _T_7806) @[el2_ifu_mem_ctl.scala 741:64] + node _T_7808 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_7809 = and(_T_7807, _T_7808) @[el2_ifu_mem_ctl.scala 741:89] + node _T_7810 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h043")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_7811 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_7812 = and(_T_7810, _T_7811) @[el2_ifu_mem_ctl.scala 742:58] + node _T_7813 = eq(perr_ic_index_ff, UInt<7>("h043")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_7814 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_7815 = and(_T_7813, _T_7814) @[el2_ifu_mem_ctl.scala 742:123] + node _T_7816 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_7817 = and(_T_7815, _T_7816) @[el2_ifu_mem_ctl.scala 742:144] + node _T_7818 = or(_T_7812, _T_7817) @[el2_ifu_mem_ctl.scala 742:80] + node _T_7819 = bits(_T_7818, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_7820 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7819 : @[Reg.scala 28:19] _T_7820 <= _T_7809 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][67] <= _T_7820 @[el2_ifu_mem_ctl.scala 740:39] - node _T_7821 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_7822 = eq(_T_7821, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_7823 = and(ic_valid_ff, _T_7822) @[el2_ifu_mem_ctl.scala 740:64] - node _T_7824 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_7825 = and(_T_7823, _T_7824) @[el2_ifu_mem_ctl.scala 740:89] - node _T_7826 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h044")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_7827 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_7828 = and(_T_7826, _T_7827) @[el2_ifu_mem_ctl.scala 741:58] - node _T_7829 = eq(perr_ic_index_ff, UInt<7>("h044")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_7830 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_7831 = and(_T_7829, _T_7830) @[el2_ifu_mem_ctl.scala 741:123] - node _T_7832 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_7833 = and(_T_7831, _T_7832) @[el2_ifu_mem_ctl.scala 741:144] - node _T_7834 = or(_T_7828, _T_7833) @[el2_ifu_mem_ctl.scala 741:80] - node _T_7835 = bits(_T_7834, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][67] <= _T_7820 @[el2_ifu_mem_ctl.scala 741:39] + node _T_7821 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_7822 = eq(_T_7821, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_7823 = and(ic_valid_ff, _T_7822) @[el2_ifu_mem_ctl.scala 741:64] + node _T_7824 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_7825 = and(_T_7823, _T_7824) @[el2_ifu_mem_ctl.scala 741:89] + node _T_7826 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h044")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_7827 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_7828 = and(_T_7826, _T_7827) @[el2_ifu_mem_ctl.scala 742:58] + node _T_7829 = eq(perr_ic_index_ff, UInt<7>("h044")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_7830 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_7831 = and(_T_7829, _T_7830) @[el2_ifu_mem_ctl.scala 742:123] + node _T_7832 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_7833 = and(_T_7831, _T_7832) @[el2_ifu_mem_ctl.scala 742:144] + node _T_7834 = or(_T_7828, _T_7833) @[el2_ifu_mem_ctl.scala 742:80] + node _T_7835 = bits(_T_7834, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_7836 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7835 : @[Reg.scala 28:19] _T_7836 <= _T_7825 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][68] <= _T_7836 @[el2_ifu_mem_ctl.scala 740:39] - node _T_7837 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_7838 = eq(_T_7837, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_7839 = and(ic_valid_ff, _T_7838) @[el2_ifu_mem_ctl.scala 740:64] - node _T_7840 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_7841 = and(_T_7839, _T_7840) @[el2_ifu_mem_ctl.scala 740:89] - node _T_7842 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h045")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_7843 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_7844 = and(_T_7842, _T_7843) @[el2_ifu_mem_ctl.scala 741:58] - node _T_7845 = eq(perr_ic_index_ff, UInt<7>("h045")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_7846 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_7847 = and(_T_7845, _T_7846) @[el2_ifu_mem_ctl.scala 741:123] - node _T_7848 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_7849 = and(_T_7847, _T_7848) @[el2_ifu_mem_ctl.scala 741:144] - node _T_7850 = or(_T_7844, _T_7849) @[el2_ifu_mem_ctl.scala 741:80] - node _T_7851 = bits(_T_7850, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][68] <= _T_7836 @[el2_ifu_mem_ctl.scala 741:39] + node _T_7837 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_7838 = eq(_T_7837, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_7839 = and(ic_valid_ff, _T_7838) @[el2_ifu_mem_ctl.scala 741:64] + node _T_7840 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_7841 = and(_T_7839, _T_7840) @[el2_ifu_mem_ctl.scala 741:89] + node _T_7842 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h045")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_7843 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_7844 = and(_T_7842, _T_7843) @[el2_ifu_mem_ctl.scala 742:58] + node _T_7845 = eq(perr_ic_index_ff, UInt<7>("h045")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_7846 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_7847 = and(_T_7845, _T_7846) @[el2_ifu_mem_ctl.scala 742:123] + node _T_7848 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_7849 = and(_T_7847, _T_7848) @[el2_ifu_mem_ctl.scala 742:144] + node _T_7850 = or(_T_7844, _T_7849) @[el2_ifu_mem_ctl.scala 742:80] + node _T_7851 = bits(_T_7850, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_7852 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7851 : @[Reg.scala 28:19] _T_7852 <= _T_7841 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][69] <= _T_7852 @[el2_ifu_mem_ctl.scala 740:39] - node _T_7853 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_7854 = eq(_T_7853, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_7855 = and(ic_valid_ff, _T_7854) @[el2_ifu_mem_ctl.scala 740:64] - node _T_7856 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_7857 = and(_T_7855, _T_7856) @[el2_ifu_mem_ctl.scala 740:89] - node _T_7858 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h046")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_7859 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_7860 = and(_T_7858, _T_7859) @[el2_ifu_mem_ctl.scala 741:58] - node _T_7861 = eq(perr_ic_index_ff, UInt<7>("h046")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_7862 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_7863 = and(_T_7861, _T_7862) @[el2_ifu_mem_ctl.scala 741:123] - node _T_7864 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_7865 = and(_T_7863, _T_7864) @[el2_ifu_mem_ctl.scala 741:144] - node _T_7866 = or(_T_7860, _T_7865) @[el2_ifu_mem_ctl.scala 741:80] - node _T_7867 = bits(_T_7866, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][69] <= _T_7852 @[el2_ifu_mem_ctl.scala 741:39] + node _T_7853 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_7854 = eq(_T_7853, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_7855 = and(ic_valid_ff, _T_7854) @[el2_ifu_mem_ctl.scala 741:64] + node _T_7856 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_7857 = and(_T_7855, _T_7856) @[el2_ifu_mem_ctl.scala 741:89] + node _T_7858 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h046")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_7859 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_7860 = and(_T_7858, _T_7859) @[el2_ifu_mem_ctl.scala 742:58] + node _T_7861 = eq(perr_ic_index_ff, UInt<7>("h046")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_7862 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_7863 = and(_T_7861, _T_7862) @[el2_ifu_mem_ctl.scala 742:123] + node _T_7864 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_7865 = and(_T_7863, _T_7864) @[el2_ifu_mem_ctl.scala 742:144] + node _T_7866 = or(_T_7860, _T_7865) @[el2_ifu_mem_ctl.scala 742:80] + node _T_7867 = bits(_T_7866, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_7868 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7867 : @[Reg.scala 28:19] _T_7868 <= _T_7857 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][70] <= _T_7868 @[el2_ifu_mem_ctl.scala 740:39] - node _T_7869 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_7870 = eq(_T_7869, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_7871 = and(ic_valid_ff, _T_7870) @[el2_ifu_mem_ctl.scala 740:64] - node _T_7872 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_7873 = and(_T_7871, _T_7872) @[el2_ifu_mem_ctl.scala 740:89] - node _T_7874 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h047")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_7875 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_7876 = and(_T_7874, _T_7875) @[el2_ifu_mem_ctl.scala 741:58] - node _T_7877 = eq(perr_ic_index_ff, UInt<7>("h047")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_7878 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_7879 = and(_T_7877, _T_7878) @[el2_ifu_mem_ctl.scala 741:123] - node _T_7880 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_7881 = and(_T_7879, _T_7880) @[el2_ifu_mem_ctl.scala 741:144] - node _T_7882 = or(_T_7876, _T_7881) @[el2_ifu_mem_ctl.scala 741:80] - node _T_7883 = bits(_T_7882, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][70] <= _T_7868 @[el2_ifu_mem_ctl.scala 741:39] + node _T_7869 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_7870 = eq(_T_7869, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_7871 = and(ic_valid_ff, _T_7870) @[el2_ifu_mem_ctl.scala 741:64] + node _T_7872 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_7873 = and(_T_7871, _T_7872) @[el2_ifu_mem_ctl.scala 741:89] + node _T_7874 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h047")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_7875 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_7876 = and(_T_7874, _T_7875) @[el2_ifu_mem_ctl.scala 742:58] + node _T_7877 = eq(perr_ic_index_ff, UInt<7>("h047")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_7878 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_7879 = and(_T_7877, _T_7878) @[el2_ifu_mem_ctl.scala 742:123] + node _T_7880 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_7881 = and(_T_7879, _T_7880) @[el2_ifu_mem_ctl.scala 742:144] + node _T_7882 = or(_T_7876, _T_7881) @[el2_ifu_mem_ctl.scala 742:80] + node _T_7883 = bits(_T_7882, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_7884 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7883 : @[Reg.scala 28:19] _T_7884 <= _T_7873 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][71] <= _T_7884 @[el2_ifu_mem_ctl.scala 740:39] - node _T_7885 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_7886 = eq(_T_7885, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_7887 = and(ic_valid_ff, _T_7886) @[el2_ifu_mem_ctl.scala 740:64] - node _T_7888 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_7889 = and(_T_7887, _T_7888) @[el2_ifu_mem_ctl.scala 740:89] - node _T_7890 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h048")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_7891 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_7892 = and(_T_7890, _T_7891) @[el2_ifu_mem_ctl.scala 741:58] - node _T_7893 = eq(perr_ic_index_ff, UInt<7>("h048")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_7894 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_7895 = and(_T_7893, _T_7894) @[el2_ifu_mem_ctl.scala 741:123] - node _T_7896 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_7897 = and(_T_7895, _T_7896) @[el2_ifu_mem_ctl.scala 741:144] - node _T_7898 = or(_T_7892, _T_7897) @[el2_ifu_mem_ctl.scala 741:80] - node _T_7899 = bits(_T_7898, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][71] <= _T_7884 @[el2_ifu_mem_ctl.scala 741:39] + node _T_7885 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_7886 = eq(_T_7885, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_7887 = and(ic_valid_ff, _T_7886) @[el2_ifu_mem_ctl.scala 741:64] + node _T_7888 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_7889 = and(_T_7887, _T_7888) @[el2_ifu_mem_ctl.scala 741:89] + node _T_7890 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h048")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_7891 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_7892 = and(_T_7890, _T_7891) @[el2_ifu_mem_ctl.scala 742:58] + node _T_7893 = eq(perr_ic_index_ff, UInt<7>("h048")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_7894 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_7895 = and(_T_7893, _T_7894) @[el2_ifu_mem_ctl.scala 742:123] + node _T_7896 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_7897 = and(_T_7895, _T_7896) @[el2_ifu_mem_ctl.scala 742:144] + node _T_7898 = or(_T_7892, _T_7897) @[el2_ifu_mem_ctl.scala 742:80] + node _T_7899 = bits(_T_7898, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_7900 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7899 : @[Reg.scala 28:19] _T_7900 <= _T_7889 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][72] <= _T_7900 @[el2_ifu_mem_ctl.scala 740:39] - node _T_7901 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_7902 = eq(_T_7901, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_7903 = and(ic_valid_ff, _T_7902) @[el2_ifu_mem_ctl.scala 740:64] - node _T_7904 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_7905 = and(_T_7903, _T_7904) @[el2_ifu_mem_ctl.scala 740:89] - node _T_7906 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h049")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_7907 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_7908 = and(_T_7906, _T_7907) @[el2_ifu_mem_ctl.scala 741:58] - node _T_7909 = eq(perr_ic_index_ff, UInt<7>("h049")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_7910 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_7911 = and(_T_7909, _T_7910) @[el2_ifu_mem_ctl.scala 741:123] - node _T_7912 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_7913 = and(_T_7911, _T_7912) @[el2_ifu_mem_ctl.scala 741:144] - node _T_7914 = or(_T_7908, _T_7913) @[el2_ifu_mem_ctl.scala 741:80] - node _T_7915 = bits(_T_7914, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][72] <= _T_7900 @[el2_ifu_mem_ctl.scala 741:39] + node _T_7901 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_7902 = eq(_T_7901, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_7903 = and(ic_valid_ff, _T_7902) @[el2_ifu_mem_ctl.scala 741:64] + node _T_7904 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_7905 = and(_T_7903, _T_7904) @[el2_ifu_mem_ctl.scala 741:89] + node _T_7906 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h049")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_7907 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_7908 = and(_T_7906, _T_7907) @[el2_ifu_mem_ctl.scala 742:58] + node _T_7909 = eq(perr_ic_index_ff, UInt<7>("h049")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_7910 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_7911 = and(_T_7909, _T_7910) @[el2_ifu_mem_ctl.scala 742:123] + node _T_7912 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_7913 = and(_T_7911, _T_7912) @[el2_ifu_mem_ctl.scala 742:144] + node _T_7914 = or(_T_7908, _T_7913) @[el2_ifu_mem_ctl.scala 742:80] + node _T_7915 = bits(_T_7914, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_7916 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7915 : @[Reg.scala 28:19] _T_7916 <= _T_7905 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][73] <= _T_7916 @[el2_ifu_mem_ctl.scala 740:39] - node _T_7917 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_7918 = eq(_T_7917, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_7919 = and(ic_valid_ff, _T_7918) @[el2_ifu_mem_ctl.scala 740:64] - node _T_7920 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_7921 = and(_T_7919, _T_7920) @[el2_ifu_mem_ctl.scala 740:89] - node _T_7922 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04a")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_7923 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_7924 = and(_T_7922, _T_7923) @[el2_ifu_mem_ctl.scala 741:58] - node _T_7925 = eq(perr_ic_index_ff, UInt<7>("h04a")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_7926 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_7927 = and(_T_7925, _T_7926) @[el2_ifu_mem_ctl.scala 741:123] - node _T_7928 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_7929 = and(_T_7927, _T_7928) @[el2_ifu_mem_ctl.scala 741:144] - node _T_7930 = or(_T_7924, _T_7929) @[el2_ifu_mem_ctl.scala 741:80] - node _T_7931 = bits(_T_7930, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][73] <= _T_7916 @[el2_ifu_mem_ctl.scala 741:39] + node _T_7917 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_7918 = eq(_T_7917, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_7919 = and(ic_valid_ff, _T_7918) @[el2_ifu_mem_ctl.scala 741:64] + node _T_7920 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_7921 = and(_T_7919, _T_7920) @[el2_ifu_mem_ctl.scala 741:89] + node _T_7922 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04a")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_7923 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_7924 = and(_T_7922, _T_7923) @[el2_ifu_mem_ctl.scala 742:58] + node _T_7925 = eq(perr_ic_index_ff, UInt<7>("h04a")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_7926 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_7927 = and(_T_7925, _T_7926) @[el2_ifu_mem_ctl.scala 742:123] + node _T_7928 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_7929 = and(_T_7927, _T_7928) @[el2_ifu_mem_ctl.scala 742:144] + node _T_7930 = or(_T_7924, _T_7929) @[el2_ifu_mem_ctl.scala 742:80] + node _T_7931 = bits(_T_7930, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_7932 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7931 : @[Reg.scala 28:19] _T_7932 <= _T_7921 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][74] <= _T_7932 @[el2_ifu_mem_ctl.scala 740:39] - node _T_7933 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_7934 = eq(_T_7933, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_7935 = and(ic_valid_ff, _T_7934) @[el2_ifu_mem_ctl.scala 740:64] - node _T_7936 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_7937 = and(_T_7935, _T_7936) @[el2_ifu_mem_ctl.scala 740:89] - node _T_7938 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04b")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_7939 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_7940 = and(_T_7938, _T_7939) @[el2_ifu_mem_ctl.scala 741:58] - node _T_7941 = eq(perr_ic_index_ff, UInt<7>("h04b")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_7942 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_7943 = and(_T_7941, _T_7942) @[el2_ifu_mem_ctl.scala 741:123] - node _T_7944 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_7945 = and(_T_7943, _T_7944) @[el2_ifu_mem_ctl.scala 741:144] - node _T_7946 = or(_T_7940, _T_7945) @[el2_ifu_mem_ctl.scala 741:80] - node _T_7947 = bits(_T_7946, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][74] <= _T_7932 @[el2_ifu_mem_ctl.scala 741:39] + node _T_7933 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_7934 = eq(_T_7933, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_7935 = and(ic_valid_ff, _T_7934) @[el2_ifu_mem_ctl.scala 741:64] + node _T_7936 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_7937 = and(_T_7935, _T_7936) @[el2_ifu_mem_ctl.scala 741:89] + node _T_7938 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04b")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_7939 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_7940 = and(_T_7938, _T_7939) @[el2_ifu_mem_ctl.scala 742:58] + node _T_7941 = eq(perr_ic_index_ff, UInt<7>("h04b")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_7942 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_7943 = and(_T_7941, _T_7942) @[el2_ifu_mem_ctl.scala 742:123] + node _T_7944 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_7945 = and(_T_7943, _T_7944) @[el2_ifu_mem_ctl.scala 742:144] + node _T_7946 = or(_T_7940, _T_7945) @[el2_ifu_mem_ctl.scala 742:80] + node _T_7947 = bits(_T_7946, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_7948 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7947 : @[Reg.scala 28:19] _T_7948 <= _T_7937 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][75] <= _T_7948 @[el2_ifu_mem_ctl.scala 740:39] - node _T_7949 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_7950 = eq(_T_7949, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_7951 = and(ic_valid_ff, _T_7950) @[el2_ifu_mem_ctl.scala 740:64] - node _T_7952 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_7953 = and(_T_7951, _T_7952) @[el2_ifu_mem_ctl.scala 740:89] - node _T_7954 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04c")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_7955 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_7956 = and(_T_7954, _T_7955) @[el2_ifu_mem_ctl.scala 741:58] - node _T_7957 = eq(perr_ic_index_ff, UInt<7>("h04c")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_7958 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_7959 = and(_T_7957, _T_7958) @[el2_ifu_mem_ctl.scala 741:123] - node _T_7960 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_7961 = and(_T_7959, _T_7960) @[el2_ifu_mem_ctl.scala 741:144] - node _T_7962 = or(_T_7956, _T_7961) @[el2_ifu_mem_ctl.scala 741:80] - node _T_7963 = bits(_T_7962, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][75] <= _T_7948 @[el2_ifu_mem_ctl.scala 741:39] + node _T_7949 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_7950 = eq(_T_7949, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_7951 = and(ic_valid_ff, _T_7950) @[el2_ifu_mem_ctl.scala 741:64] + node _T_7952 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_7953 = and(_T_7951, _T_7952) @[el2_ifu_mem_ctl.scala 741:89] + node _T_7954 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04c")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_7955 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_7956 = and(_T_7954, _T_7955) @[el2_ifu_mem_ctl.scala 742:58] + node _T_7957 = eq(perr_ic_index_ff, UInt<7>("h04c")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_7958 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_7959 = and(_T_7957, _T_7958) @[el2_ifu_mem_ctl.scala 742:123] + node _T_7960 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_7961 = and(_T_7959, _T_7960) @[el2_ifu_mem_ctl.scala 742:144] + node _T_7962 = or(_T_7956, _T_7961) @[el2_ifu_mem_ctl.scala 742:80] + node _T_7963 = bits(_T_7962, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_7964 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7963 : @[Reg.scala 28:19] _T_7964 <= _T_7953 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][76] <= _T_7964 @[el2_ifu_mem_ctl.scala 740:39] - node _T_7965 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_7966 = eq(_T_7965, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_7967 = and(ic_valid_ff, _T_7966) @[el2_ifu_mem_ctl.scala 740:64] - node _T_7968 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_7969 = and(_T_7967, _T_7968) @[el2_ifu_mem_ctl.scala 740:89] - node _T_7970 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04d")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_7971 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_7972 = and(_T_7970, _T_7971) @[el2_ifu_mem_ctl.scala 741:58] - node _T_7973 = eq(perr_ic_index_ff, UInt<7>("h04d")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_7974 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_7975 = and(_T_7973, _T_7974) @[el2_ifu_mem_ctl.scala 741:123] - node _T_7976 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_7977 = and(_T_7975, _T_7976) @[el2_ifu_mem_ctl.scala 741:144] - node _T_7978 = or(_T_7972, _T_7977) @[el2_ifu_mem_ctl.scala 741:80] - node _T_7979 = bits(_T_7978, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][76] <= _T_7964 @[el2_ifu_mem_ctl.scala 741:39] + node _T_7965 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_7966 = eq(_T_7965, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_7967 = and(ic_valid_ff, _T_7966) @[el2_ifu_mem_ctl.scala 741:64] + node _T_7968 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_7969 = and(_T_7967, _T_7968) @[el2_ifu_mem_ctl.scala 741:89] + node _T_7970 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04d")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_7971 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_7972 = and(_T_7970, _T_7971) @[el2_ifu_mem_ctl.scala 742:58] + node _T_7973 = eq(perr_ic_index_ff, UInt<7>("h04d")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_7974 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_7975 = and(_T_7973, _T_7974) @[el2_ifu_mem_ctl.scala 742:123] + node _T_7976 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_7977 = and(_T_7975, _T_7976) @[el2_ifu_mem_ctl.scala 742:144] + node _T_7978 = or(_T_7972, _T_7977) @[el2_ifu_mem_ctl.scala 742:80] + node _T_7979 = bits(_T_7978, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_7980 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7979 : @[Reg.scala 28:19] _T_7980 <= _T_7969 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][77] <= _T_7980 @[el2_ifu_mem_ctl.scala 740:39] - node _T_7981 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_7982 = eq(_T_7981, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_7983 = and(ic_valid_ff, _T_7982) @[el2_ifu_mem_ctl.scala 740:64] - node _T_7984 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_7985 = and(_T_7983, _T_7984) @[el2_ifu_mem_ctl.scala 740:89] - node _T_7986 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04e")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_7987 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_7988 = and(_T_7986, _T_7987) @[el2_ifu_mem_ctl.scala 741:58] - node _T_7989 = eq(perr_ic_index_ff, UInt<7>("h04e")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_7990 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_7991 = and(_T_7989, _T_7990) @[el2_ifu_mem_ctl.scala 741:123] - node _T_7992 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_7993 = and(_T_7991, _T_7992) @[el2_ifu_mem_ctl.scala 741:144] - node _T_7994 = or(_T_7988, _T_7993) @[el2_ifu_mem_ctl.scala 741:80] - node _T_7995 = bits(_T_7994, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][77] <= _T_7980 @[el2_ifu_mem_ctl.scala 741:39] + node _T_7981 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_7982 = eq(_T_7981, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_7983 = and(ic_valid_ff, _T_7982) @[el2_ifu_mem_ctl.scala 741:64] + node _T_7984 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_7985 = and(_T_7983, _T_7984) @[el2_ifu_mem_ctl.scala 741:89] + node _T_7986 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04e")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_7987 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_7988 = and(_T_7986, _T_7987) @[el2_ifu_mem_ctl.scala 742:58] + node _T_7989 = eq(perr_ic_index_ff, UInt<7>("h04e")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_7990 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_7991 = and(_T_7989, _T_7990) @[el2_ifu_mem_ctl.scala 742:123] + node _T_7992 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_7993 = and(_T_7991, _T_7992) @[el2_ifu_mem_ctl.scala 742:144] + node _T_7994 = or(_T_7988, _T_7993) @[el2_ifu_mem_ctl.scala 742:80] + node _T_7995 = bits(_T_7994, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_7996 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_7995 : @[Reg.scala 28:19] _T_7996 <= _T_7985 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][78] <= _T_7996 @[el2_ifu_mem_ctl.scala 740:39] - node _T_7997 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_7998 = eq(_T_7997, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_7999 = and(ic_valid_ff, _T_7998) @[el2_ifu_mem_ctl.scala 740:64] - node _T_8000 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_8001 = and(_T_7999, _T_8000) @[el2_ifu_mem_ctl.scala 740:89] - node _T_8002 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04f")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_8003 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_8004 = and(_T_8002, _T_8003) @[el2_ifu_mem_ctl.scala 741:58] - node _T_8005 = eq(perr_ic_index_ff, UInt<7>("h04f")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_8006 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_8007 = and(_T_8005, _T_8006) @[el2_ifu_mem_ctl.scala 741:123] - node _T_8008 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_8009 = and(_T_8007, _T_8008) @[el2_ifu_mem_ctl.scala 741:144] - node _T_8010 = or(_T_8004, _T_8009) @[el2_ifu_mem_ctl.scala 741:80] - node _T_8011 = bits(_T_8010, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][78] <= _T_7996 @[el2_ifu_mem_ctl.scala 741:39] + node _T_7997 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_7998 = eq(_T_7997, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_7999 = and(ic_valid_ff, _T_7998) @[el2_ifu_mem_ctl.scala 741:64] + node _T_8000 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_8001 = and(_T_7999, _T_8000) @[el2_ifu_mem_ctl.scala 741:89] + node _T_8002 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04f")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_8003 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_8004 = and(_T_8002, _T_8003) @[el2_ifu_mem_ctl.scala 742:58] + node _T_8005 = eq(perr_ic_index_ff, UInt<7>("h04f")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_8006 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_8007 = and(_T_8005, _T_8006) @[el2_ifu_mem_ctl.scala 742:123] + node _T_8008 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_8009 = and(_T_8007, _T_8008) @[el2_ifu_mem_ctl.scala 742:144] + node _T_8010 = or(_T_8004, _T_8009) @[el2_ifu_mem_ctl.scala 742:80] + node _T_8011 = bits(_T_8010, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_8012 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8011 : @[Reg.scala 28:19] _T_8012 <= _T_8001 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][79] <= _T_8012 @[el2_ifu_mem_ctl.scala 740:39] - node _T_8013 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_8014 = eq(_T_8013, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_8015 = and(ic_valid_ff, _T_8014) @[el2_ifu_mem_ctl.scala 740:64] - node _T_8016 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_8017 = and(_T_8015, _T_8016) @[el2_ifu_mem_ctl.scala 740:89] - node _T_8018 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h050")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_8019 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_8020 = and(_T_8018, _T_8019) @[el2_ifu_mem_ctl.scala 741:58] - node _T_8021 = eq(perr_ic_index_ff, UInt<7>("h050")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_8022 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_8023 = and(_T_8021, _T_8022) @[el2_ifu_mem_ctl.scala 741:123] - node _T_8024 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_8025 = and(_T_8023, _T_8024) @[el2_ifu_mem_ctl.scala 741:144] - node _T_8026 = or(_T_8020, _T_8025) @[el2_ifu_mem_ctl.scala 741:80] - node _T_8027 = bits(_T_8026, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][79] <= _T_8012 @[el2_ifu_mem_ctl.scala 741:39] + node _T_8013 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_8014 = eq(_T_8013, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_8015 = and(ic_valid_ff, _T_8014) @[el2_ifu_mem_ctl.scala 741:64] + node _T_8016 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_8017 = and(_T_8015, _T_8016) @[el2_ifu_mem_ctl.scala 741:89] + node _T_8018 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h050")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_8019 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_8020 = and(_T_8018, _T_8019) @[el2_ifu_mem_ctl.scala 742:58] + node _T_8021 = eq(perr_ic_index_ff, UInt<7>("h050")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_8022 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_8023 = and(_T_8021, _T_8022) @[el2_ifu_mem_ctl.scala 742:123] + node _T_8024 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_8025 = and(_T_8023, _T_8024) @[el2_ifu_mem_ctl.scala 742:144] + node _T_8026 = or(_T_8020, _T_8025) @[el2_ifu_mem_ctl.scala 742:80] + node _T_8027 = bits(_T_8026, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_8028 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8027 : @[Reg.scala 28:19] _T_8028 <= _T_8017 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][80] <= _T_8028 @[el2_ifu_mem_ctl.scala 740:39] - node _T_8029 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_8030 = eq(_T_8029, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_8031 = and(ic_valid_ff, _T_8030) @[el2_ifu_mem_ctl.scala 740:64] - node _T_8032 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_8033 = and(_T_8031, _T_8032) @[el2_ifu_mem_ctl.scala 740:89] - node _T_8034 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h051")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_8035 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_8036 = and(_T_8034, _T_8035) @[el2_ifu_mem_ctl.scala 741:58] - node _T_8037 = eq(perr_ic_index_ff, UInt<7>("h051")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_8038 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_8039 = and(_T_8037, _T_8038) @[el2_ifu_mem_ctl.scala 741:123] - node _T_8040 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_8041 = and(_T_8039, _T_8040) @[el2_ifu_mem_ctl.scala 741:144] - node _T_8042 = or(_T_8036, _T_8041) @[el2_ifu_mem_ctl.scala 741:80] - node _T_8043 = bits(_T_8042, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][80] <= _T_8028 @[el2_ifu_mem_ctl.scala 741:39] + node _T_8029 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_8030 = eq(_T_8029, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_8031 = and(ic_valid_ff, _T_8030) @[el2_ifu_mem_ctl.scala 741:64] + node _T_8032 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_8033 = and(_T_8031, _T_8032) @[el2_ifu_mem_ctl.scala 741:89] + node _T_8034 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h051")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_8035 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_8036 = and(_T_8034, _T_8035) @[el2_ifu_mem_ctl.scala 742:58] + node _T_8037 = eq(perr_ic_index_ff, UInt<7>("h051")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_8038 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_8039 = and(_T_8037, _T_8038) @[el2_ifu_mem_ctl.scala 742:123] + node _T_8040 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_8041 = and(_T_8039, _T_8040) @[el2_ifu_mem_ctl.scala 742:144] + node _T_8042 = or(_T_8036, _T_8041) @[el2_ifu_mem_ctl.scala 742:80] + node _T_8043 = bits(_T_8042, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_8044 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8043 : @[Reg.scala 28:19] _T_8044 <= _T_8033 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][81] <= _T_8044 @[el2_ifu_mem_ctl.scala 740:39] - node _T_8045 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_8046 = eq(_T_8045, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_8047 = and(ic_valid_ff, _T_8046) @[el2_ifu_mem_ctl.scala 740:64] - node _T_8048 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_8049 = and(_T_8047, _T_8048) @[el2_ifu_mem_ctl.scala 740:89] - node _T_8050 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h052")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_8051 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_8052 = and(_T_8050, _T_8051) @[el2_ifu_mem_ctl.scala 741:58] - node _T_8053 = eq(perr_ic_index_ff, UInt<7>("h052")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_8054 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_8055 = and(_T_8053, _T_8054) @[el2_ifu_mem_ctl.scala 741:123] - node _T_8056 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_8057 = and(_T_8055, _T_8056) @[el2_ifu_mem_ctl.scala 741:144] - node _T_8058 = or(_T_8052, _T_8057) @[el2_ifu_mem_ctl.scala 741:80] - node _T_8059 = bits(_T_8058, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][81] <= _T_8044 @[el2_ifu_mem_ctl.scala 741:39] + node _T_8045 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_8046 = eq(_T_8045, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_8047 = and(ic_valid_ff, _T_8046) @[el2_ifu_mem_ctl.scala 741:64] + node _T_8048 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_8049 = and(_T_8047, _T_8048) @[el2_ifu_mem_ctl.scala 741:89] + node _T_8050 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h052")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_8051 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_8052 = and(_T_8050, _T_8051) @[el2_ifu_mem_ctl.scala 742:58] + node _T_8053 = eq(perr_ic_index_ff, UInt<7>("h052")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_8054 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_8055 = and(_T_8053, _T_8054) @[el2_ifu_mem_ctl.scala 742:123] + node _T_8056 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_8057 = and(_T_8055, _T_8056) @[el2_ifu_mem_ctl.scala 742:144] + node _T_8058 = or(_T_8052, _T_8057) @[el2_ifu_mem_ctl.scala 742:80] + node _T_8059 = bits(_T_8058, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_8060 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8059 : @[Reg.scala 28:19] _T_8060 <= _T_8049 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][82] <= _T_8060 @[el2_ifu_mem_ctl.scala 740:39] - node _T_8061 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_8062 = eq(_T_8061, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_8063 = and(ic_valid_ff, _T_8062) @[el2_ifu_mem_ctl.scala 740:64] - node _T_8064 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_8065 = and(_T_8063, _T_8064) @[el2_ifu_mem_ctl.scala 740:89] - node _T_8066 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h053")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_8067 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_8068 = and(_T_8066, _T_8067) @[el2_ifu_mem_ctl.scala 741:58] - node _T_8069 = eq(perr_ic_index_ff, UInt<7>("h053")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_8070 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_8071 = and(_T_8069, _T_8070) @[el2_ifu_mem_ctl.scala 741:123] - node _T_8072 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_8073 = and(_T_8071, _T_8072) @[el2_ifu_mem_ctl.scala 741:144] - node _T_8074 = or(_T_8068, _T_8073) @[el2_ifu_mem_ctl.scala 741:80] - node _T_8075 = bits(_T_8074, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][82] <= _T_8060 @[el2_ifu_mem_ctl.scala 741:39] + node _T_8061 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_8062 = eq(_T_8061, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_8063 = and(ic_valid_ff, _T_8062) @[el2_ifu_mem_ctl.scala 741:64] + node _T_8064 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_8065 = and(_T_8063, _T_8064) @[el2_ifu_mem_ctl.scala 741:89] + node _T_8066 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h053")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_8067 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_8068 = and(_T_8066, _T_8067) @[el2_ifu_mem_ctl.scala 742:58] + node _T_8069 = eq(perr_ic_index_ff, UInt<7>("h053")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_8070 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_8071 = and(_T_8069, _T_8070) @[el2_ifu_mem_ctl.scala 742:123] + node _T_8072 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_8073 = and(_T_8071, _T_8072) @[el2_ifu_mem_ctl.scala 742:144] + node _T_8074 = or(_T_8068, _T_8073) @[el2_ifu_mem_ctl.scala 742:80] + node _T_8075 = bits(_T_8074, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_8076 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8075 : @[Reg.scala 28:19] _T_8076 <= _T_8065 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][83] <= _T_8076 @[el2_ifu_mem_ctl.scala 740:39] - node _T_8077 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_8078 = eq(_T_8077, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_8079 = and(ic_valid_ff, _T_8078) @[el2_ifu_mem_ctl.scala 740:64] - node _T_8080 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_8081 = and(_T_8079, _T_8080) @[el2_ifu_mem_ctl.scala 740:89] - node _T_8082 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h054")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_8083 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_8084 = and(_T_8082, _T_8083) @[el2_ifu_mem_ctl.scala 741:58] - node _T_8085 = eq(perr_ic_index_ff, UInt<7>("h054")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_8086 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_8087 = and(_T_8085, _T_8086) @[el2_ifu_mem_ctl.scala 741:123] - node _T_8088 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_8089 = and(_T_8087, _T_8088) @[el2_ifu_mem_ctl.scala 741:144] - node _T_8090 = or(_T_8084, _T_8089) @[el2_ifu_mem_ctl.scala 741:80] - node _T_8091 = bits(_T_8090, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][83] <= _T_8076 @[el2_ifu_mem_ctl.scala 741:39] + node _T_8077 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_8078 = eq(_T_8077, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_8079 = and(ic_valid_ff, _T_8078) @[el2_ifu_mem_ctl.scala 741:64] + node _T_8080 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_8081 = and(_T_8079, _T_8080) @[el2_ifu_mem_ctl.scala 741:89] + node _T_8082 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h054")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_8083 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_8084 = and(_T_8082, _T_8083) @[el2_ifu_mem_ctl.scala 742:58] + node _T_8085 = eq(perr_ic_index_ff, UInt<7>("h054")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_8086 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_8087 = and(_T_8085, _T_8086) @[el2_ifu_mem_ctl.scala 742:123] + node _T_8088 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_8089 = and(_T_8087, _T_8088) @[el2_ifu_mem_ctl.scala 742:144] + node _T_8090 = or(_T_8084, _T_8089) @[el2_ifu_mem_ctl.scala 742:80] + node _T_8091 = bits(_T_8090, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_8092 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8091 : @[Reg.scala 28:19] _T_8092 <= _T_8081 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][84] <= _T_8092 @[el2_ifu_mem_ctl.scala 740:39] - node _T_8093 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_8094 = eq(_T_8093, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_8095 = and(ic_valid_ff, _T_8094) @[el2_ifu_mem_ctl.scala 740:64] - node _T_8096 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_8097 = and(_T_8095, _T_8096) @[el2_ifu_mem_ctl.scala 740:89] - node _T_8098 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h055")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_8099 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_8100 = and(_T_8098, _T_8099) @[el2_ifu_mem_ctl.scala 741:58] - node _T_8101 = eq(perr_ic_index_ff, UInt<7>("h055")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_8102 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_8103 = and(_T_8101, _T_8102) @[el2_ifu_mem_ctl.scala 741:123] - node _T_8104 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_8105 = and(_T_8103, _T_8104) @[el2_ifu_mem_ctl.scala 741:144] - node _T_8106 = or(_T_8100, _T_8105) @[el2_ifu_mem_ctl.scala 741:80] - node _T_8107 = bits(_T_8106, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][84] <= _T_8092 @[el2_ifu_mem_ctl.scala 741:39] + node _T_8093 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_8094 = eq(_T_8093, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_8095 = and(ic_valid_ff, _T_8094) @[el2_ifu_mem_ctl.scala 741:64] + node _T_8096 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_8097 = and(_T_8095, _T_8096) @[el2_ifu_mem_ctl.scala 741:89] + node _T_8098 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h055")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_8099 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_8100 = and(_T_8098, _T_8099) @[el2_ifu_mem_ctl.scala 742:58] + node _T_8101 = eq(perr_ic_index_ff, UInt<7>("h055")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_8102 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_8103 = and(_T_8101, _T_8102) @[el2_ifu_mem_ctl.scala 742:123] + node _T_8104 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_8105 = and(_T_8103, _T_8104) @[el2_ifu_mem_ctl.scala 742:144] + node _T_8106 = or(_T_8100, _T_8105) @[el2_ifu_mem_ctl.scala 742:80] + node _T_8107 = bits(_T_8106, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_8108 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8107 : @[Reg.scala 28:19] _T_8108 <= _T_8097 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][85] <= _T_8108 @[el2_ifu_mem_ctl.scala 740:39] - node _T_8109 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_8110 = eq(_T_8109, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_8111 = and(ic_valid_ff, _T_8110) @[el2_ifu_mem_ctl.scala 740:64] - node _T_8112 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_8113 = and(_T_8111, _T_8112) @[el2_ifu_mem_ctl.scala 740:89] - node _T_8114 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h056")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_8115 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_8116 = and(_T_8114, _T_8115) @[el2_ifu_mem_ctl.scala 741:58] - node _T_8117 = eq(perr_ic_index_ff, UInt<7>("h056")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_8118 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_8119 = and(_T_8117, _T_8118) @[el2_ifu_mem_ctl.scala 741:123] - node _T_8120 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_8121 = and(_T_8119, _T_8120) @[el2_ifu_mem_ctl.scala 741:144] - node _T_8122 = or(_T_8116, _T_8121) @[el2_ifu_mem_ctl.scala 741:80] - node _T_8123 = bits(_T_8122, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][85] <= _T_8108 @[el2_ifu_mem_ctl.scala 741:39] + node _T_8109 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_8110 = eq(_T_8109, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_8111 = and(ic_valid_ff, _T_8110) @[el2_ifu_mem_ctl.scala 741:64] + node _T_8112 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_8113 = and(_T_8111, _T_8112) @[el2_ifu_mem_ctl.scala 741:89] + node _T_8114 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h056")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_8115 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_8116 = and(_T_8114, _T_8115) @[el2_ifu_mem_ctl.scala 742:58] + node _T_8117 = eq(perr_ic_index_ff, UInt<7>("h056")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_8118 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_8119 = and(_T_8117, _T_8118) @[el2_ifu_mem_ctl.scala 742:123] + node _T_8120 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_8121 = and(_T_8119, _T_8120) @[el2_ifu_mem_ctl.scala 742:144] + node _T_8122 = or(_T_8116, _T_8121) @[el2_ifu_mem_ctl.scala 742:80] + node _T_8123 = bits(_T_8122, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_8124 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8123 : @[Reg.scala 28:19] _T_8124 <= _T_8113 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][86] <= _T_8124 @[el2_ifu_mem_ctl.scala 740:39] - node _T_8125 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_8126 = eq(_T_8125, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_8127 = and(ic_valid_ff, _T_8126) @[el2_ifu_mem_ctl.scala 740:64] - node _T_8128 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_8129 = and(_T_8127, _T_8128) @[el2_ifu_mem_ctl.scala 740:89] - node _T_8130 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h057")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_8131 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_8132 = and(_T_8130, _T_8131) @[el2_ifu_mem_ctl.scala 741:58] - node _T_8133 = eq(perr_ic_index_ff, UInt<7>("h057")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_8134 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_8135 = and(_T_8133, _T_8134) @[el2_ifu_mem_ctl.scala 741:123] - node _T_8136 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_8137 = and(_T_8135, _T_8136) @[el2_ifu_mem_ctl.scala 741:144] - node _T_8138 = or(_T_8132, _T_8137) @[el2_ifu_mem_ctl.scala 741:80] - node _T_8139 = bits(_T_8138, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][86] <= _T_8124 @[el2_ifu_mem_ctl.scala 741:39] + node _T_8125 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_8126 = eq(_T_8125, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_8127 = and(ic_valid_ff, _T_8126) @[el2_ifu_mem_ctl.scala 741:64] + node _T_8128 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_8129 = and(_T_8127, _T_8128) @[el2_ifu_mem_ctl.scala 741:89] + node _T_8130 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h057")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_8131 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_8132 = and(_T_8130, _T_8131) @[el2_ifu_mem_ctl.scala 742:58] + node _T_8133 = eq(perr_ic_index_ff, UInt<7>("h057")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_8134 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_8135 = and(_T_8133, _T_8134) @[el2_ifu_mem_ctl.scala 742:123] + node _T_8136 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_8137 = and(_T_8135, _T_8136) @[el2_ifu_mem_ctl.scala 742:144] + node _T_8138 = or(_T_8132, _T_8137) @[el2_ifu_mem_ctl.scala 742:80] + node _T_8139 = bits(_T_8138, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_8140 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8139 : @[Reg.scala 28:19] _T_8140 <= _T_8129 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][87] <= _T_8140 @[el2_ifu_mem_ctl.scala 740:39] - node _T_8141 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_8142 = eq(_T_8141, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_8143 = and(ic_valid_ff, _T_8142) @[el2_ifu_mem_ctl.scala 740:64] - node _T_8144 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_8145 = and(_T_8143, _T_8144) @[el2_ifu_mem_ctl.scala 740:89] - node _T_8146 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h058")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_8147 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_8148 = and(_T_8146, _T_8147) @[el2_ifu_mem_ctl.scala 741:58] - node _T_8149 = eq(perr_ic_index_ff, UInt<7>("h058")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_8150 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_8151 = and(_T_8149, _T_8150) @[el2_ifu_mem_ctl.scala 741:123] - node _T_8152 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_8153 = and(_T_8151, _T_8152) @[el2_ifu_mem_ctl.scala 741:144] - node _T_8154 = or(_T_8148, _T_8153) @[el2_ifu_mem_ctl.scala 741:80] - node _T_8155 = bits(_T_8154, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][87] <= _T_8140 @[el2_ifu_mem_ctl.scala 741:39] + node _T_8141 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_8142 = eq(_T_8141, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_8143 = and(ic_valid_ff, _T_8142) @[el2_ifu_mem_ctl.scala 741:64] + node _T_8144 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_8145 = and(_T_8143, _T_8144) @[el2_ifu_mem_ctl.scala 741:89] + node _T_8146 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h058")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_8147 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_8148 = and(_T_8146, _T_8147) @[el2_ifu_mem_ctl.scala 742:58] + node _T_8149 = eq(perr_ic_index_ff, UInt<7>("h058")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_8150 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_8151 = and(_T_8149, _T_8150) @[el2_ifu_mem_ctl.scala 742:123] + node _T_8152 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_8153 = and(_T_8151, _T_8152) @[el2_ifu_mem_ctl.scala 742:144] + node _T_8154 = or(_T_8148, _T_8153) @[el2_ifu_mem_ctl.scala 742:80] + node _T_8155 = bits(_T_8154, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_8156 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8155 : @[Reg.scala 28:19] _T_8156 <= _T_8145 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][88] <= _T_8156 @[el2_ifu_mem_ctl.scala 740:39] - node _T_8157 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_8158 = eq(_T_8157, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_8159 = and(ic_valid_ff, _T_8158) @[el2_ifu_mem_ctl.scala 740:64] - node _T_8160 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_8161 = and(_T_8159, _T_8160) @[el2_ifu_mem_ctl.scala 740:89] - node _T_8162 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h059")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_8163 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_8164 = and(_T_8162, _T_8163) @[el2_ifu_mem_ctl.scala 741:58] - node _T_8165 = eq(perr_ic_index_ff, UInt<7>("h059")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_8166 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_8167 = and(_T_8165, _T_8166) @[el2_ifu_mem_ctl.scala 741:123] - node _T_8168 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_8169 = and(_T_8167, _T_8168) @[el2_ifu_mem_ctl.scala 741:144] - node _T_8170 = or(_T_8164, _T_8169) @[el2_ifu_mem_ctl.scala 741:80] - node _T_8171 = bits(_T_8170, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][88] <= _T_8156 @[el2_ifu_mem_ctl.scala 741:39] + node _T_8157 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_8158 = eq(_T_8157, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_8159 = and(ic_valid_ff, _T_8158) @[el2_ifu_mem_ctl.scala 741:64] + node _T_8160 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_8161 = and(_T_8159, _T_8160) @[el2_ifu_mem_ctl.scala 741:89] + node _T_8162 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h059")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_8163 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_8164 = and(_T_8162, _T_8163) @[el2_ifu_mem_ctl.scala 742:58] + node _T_8165 = eq(perr_ic_index_ff, UInt<7>("h059")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_8166 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_8167 = and(_T_8165, _T_8166) @[el2_ifu_mem_ctl.scala 742:123] + node _T_8168 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_8169 = and(_T_8167, _T_8168) @[el2_ifu_mem_ctl.scala 742:144] + node _T_8170 = or(_T_8164, _T_8169) @[el2_ifu_mem_ctl.scala 742:80] + node _T_8171 = bits(_T_8170, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_8172 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8171 : @[Reg.scala 28:19] _T_8172 <= _T_8161 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][89] <= _T_8172 @[el2_ifu_mem_ctl.scala 740:39] - node _T_8173 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_8174 = eq(_T_8173, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_8175 = and(ic_valid_ff, _T_8174) @[el2_ifu_mem_ctl.scala 740:64] - node _T_8176 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_8177 = and(_T_8175, _T_8176) @[el2_ifu_mem_ctl.scala 740:89] - node _T_8178 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05a")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_8179 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_8180 = and(_T_8178, _T_8179) @[el2_ifu_mem_ctl.scala 741:58] - node _T_8181 = eq(perr_ic_index_ff, UInt<7>("h05a")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_8182 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_8183 = and(_T_8181, _T_8182) @[el2_ifu_mem_ctl.scala 741:123] - node _T_8184 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_8185 = and(_T_8183, _T_8184) @[el2_ifu_mem_ctl.scala 741:144] - node _T_8186 = or(_T_8180, _T_8185) @[el2_ifu_mem_ctl.scala 741:80] - node _T_8187 = bits(_T_8186, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][89] <= _T_8172 @[el2_ifu_mem_ctl.scala 741:39] + node _T_8173 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_8174 = eq(_T_8173, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_8175 = and(ic_valid_ff, _T_8174) @[el2_ifu_mem_ctl.scala 741:64] + node _T_8176 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_8177 = and(_T_8175, _T_8176) @[el2_ifu_mem_ctl.scala 741:89] + node _T_8178 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05a")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_8179 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_8180 = and(_T_8178, _T_8179) @[el2_ifu_mem_ctl.scala 742:58] + node _T_8181 = eq(perr_ic_index_ff, UInt<7>("h05a")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_8182 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_8183 = and(_T_8181, _T_8182) @[el2_ifu_mem_ctl.scala 742:123] + node _T_8184 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_8185 = and(_T_8183, _T_8184) @[el2_ifu_mem_ctl.scala 742:144] + node _T_8186 = or(_T_8180, _T_8185) @[el2_ifu_mem_ctl.scala 742:80] + node _T_8187 = bits(_T_8186, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_8188 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8187 : @[Reg.scala 28:19] _T_8188 <= _T_8177 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][90] <= _T_8188 @[el2_ifu_mem_ctl.scala 740:39] - node _T_8189 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_8190 = eq(_T_8189, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_8191 = and(ic_valid_ff, _T_8190) @[el2_ifu_mem_ctl.scala 740:64] - node _T_8192 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_8193 = and(_T_8191, _T_8192) @[el2_ifu_mem_ctl.scala 740:89] - node _T_8194 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05b")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_8195 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_8196 = and(_T_8194, _T_8195) @[el2_ifu_mem_ctl.scala 741:58] - node _T_8197 = eq(perr_ic_index_ff, UInt<7>("h05b")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_8198 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_8199 = and(_T_8197, _T_8198) @[el2_ifu_mem_ctl.scala 741:123] - node _T_8200 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_8201 = and(_T_8199, _T_8200) @[el2_ifu_mem_ctl.scala 741:144] - node _T_8202 = or(_T_8196, _T_8201) @[el2_ifu_mem_ctl.scala 741:80] - node _T_8203 = bits(_T_8202, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][90] <= _T_8188 @[el2_ifu_mem_ctl.scala 741:39] + node _T_8189 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_8190 = eq(_T_8189, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_8191 = and(ic_valid_ff, _T_8190) @[el2_ifu_mem_ctl.scala 741:64] + node _T_8192 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_8193 = and(_T_8191, _T_8192) @[el2_ifu_mem_ctl.scala 741:89] + node _T_8194 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05b")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_8195 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_8196 = and(_T_8194, _T_8195) @[el2_ifu_mem_ctl.scala 742:58] + node _T_8197 = eq(perr_ic_index_ff, UInt<7>("h05b")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_8198 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_8199 = and(_T_8197, _T_8198) @[el2_ifu_mem_ctl.scala 742:123] + node _T_8200 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_8201 = and(_T_8199, _T_8200) @[el2_ifu_mem_ctl.scala 742:144] + node _T_8202 = or(_T_8196, _T_8201) @[el2_ifu_mem_ctl.scala 742:80] + node _T_8203 = bits(_T_8202, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_8204 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8203 : @[Reg.scala 28:19] _T_8204 <= _T_8193 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][91] <= _T_8204 @[el2_ifu_mem_ctl.scala 740:39] - node _T_8205 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_8206 = eq(_T_8205, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_8207 = and(ic_valid_ff, _T_8206) @[el2_ifu_mem_ctl.scala 740:64] - node _T_8208 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_8209 = and(_T_8207, _T_8208) @[el2_ifu_mem_ctl.scala 740:89] - node _T_8210 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05c")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_8211 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_8212 = and(_T_8210, _T_8211) @[el2_ifu_mem_ctl.scala 741:58] - node _T_8213 = eq(perr_ic_index_ff, UInt<7>("h05c")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_8214 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_8215 = and(_T_8213, _T_8214) @[el2_ifu_mem_ctl.scala 741:123] - node _T_8216 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_8217 = and(_T_8215, _T_8216) @[el2_ifu_mem_ctl.scala 741:144] - node _T_8218 = or(_T_8212, _T_8217) @[el2_ifu_mem_ctl.scala 741:80] - node _T_8219 = bits(_T_8218, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][91] <= _T_8204 @[el2_ifu_mem_ctl.scala 741:39] + node _T_8205 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_8206 = eq(_T_8205, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_8207 = and(ic_valid_ff, _T_8206) @[el2_ifu_mem_ctl.scala 741:64] + node _T_8208 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_8209 = and(_T_8207, _T_8208) @[el2_ifu_mem_ctl.scala 741:89] + node _T_8210 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05c")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_8211 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_8212 = and(_T_8210, _T_8211) @[el2_ifu_mem_ctl.scala 742:58] + node _T_8213 = eq(perr_ic_index_ff, UInt<7>("h05c")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_8214 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_8215 = and(_T_8213, _T_8214) @[el2_ifu_mem_ctl.scala 742:123] + node _T_8216 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_8217 = and(_T_8215, _T_8216) @[el2_ifu_mem_ctl.scala 742:144] + node _T_8218 = or(_T_8212, _T_8217) @[el2_ifu_mem_ctl.scala 742:80] + node _T_8219 = bits(_T_8218, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_8220 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8219 : @[Reg.scala 28:19] _T_8220 <= _T_8209 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][92] <= _T_8220 @[el2_ifu_mem_ctl.scala 740:39] - node _T_8221 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_8222 = eq(_T_8221, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_8223 = and(ic_valid_ff, _T_8222) @[el2_ifu_mem_ctl.scala 740:64] - node _T_8224 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_8225 = and(_T_8223, _T_8224) @[el2_ifu_mem_ctl.scala 740:89] - node _T_8226 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05d")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_8227 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_8228 = and(_T_8226, _T_8227) @[el2_ifu_mem_ctl.scala 741:58] - node _T_8229 = eq(perr_ic_index_ff, UInt<7>("h05d")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_8230 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_8231 = and(_T_8229, _T_8230) @[el2_ifu_mem_ctl.scala 741:123] - node _T_8232 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_8233 = and(_T_8231, _T_8232) @[el2_ifu_mem_ctl.scala 741:144] - node _T_8234 = or(_T_8228, _T_8233) @[el2_ifu_mem_ctl.scala 741:80] - node _T_8235 = bits(_T_8234, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][92] <= _T_8220 @[el2_ifu_mem_ctl.scala 741:39] + node _T_8221 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_8222 = eq(_T_8221, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_8223 = and(ic_valid_ff, _T_8222) @[el2_ifu_mem_ctl.scala 741:64] + node _T_8224 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_8225 = and(_T_8223, _T_8224) @[el2_ifu_mem_ctl.scala 741:89] + node _T_8226 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05d")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_8227 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_8228 = and(_T_8226, _T_8227) @[el2_ifu_mem_ctl.scala 742:58] + node _T_8229 = eq(perr_ic_index_ff, UInt<7>("h05d")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_8230 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_8231 = and(_T_8229, _T_8230) @[el2_ifu_mem_ctl.scala 742:123] + node _T_8232 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_8233 = and(_T_8231, _T_8232) @[el2_ifu_mem_ctl.scala 742:144] + node _T_8234 = or(_T_8228, _T_8233) @[el2_ifu_mem_ctl.scala 742:80] + node _T_8235 = bits(_T_8234, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_8236 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8235 : @[Reg.scala 28:19] _T_8236 <= _T_8225 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][93] <= _T_8236 @[el2_ifu_mem_ctl.scala 740:39] - node _T_8237 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_8238 = eq(_T_8237, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_8239 = and(ic_valid_ff, _T_8238) @[el2_ifu_mem_ctl.scala 740:64] - node _T_8240 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_8241 = and(_T_8239, _T_8240) @[el2_ifu_mem_ctl.scala 740:89] - node _T_8242 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05e")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_8243 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_8244 = and(_T_8242, _T_8243) @[el2_ifu_mem_ctl.scala 741:58] - node _T_8245 = eq(perr_ic_index_ff, UInt<7>("h05e")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_8246 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_8247 = and(_T_8245, _T_8246) @[el2_ifu_mem_ctl.scala 741:123] - node _T_8248 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_8249 = and(_T_8247, _T_8248) @[el2_ifu_mem_ctl.scala 741:144] - node _T_8250 = or(_T_8244, _T_8249) @[el2_ifu_mem_ctl.scala 741:80] - node _T_8251 = bits(_T_8250, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][93] <= _T_8236 @[el2_ifu_mem_ctl.scala 741:39] + node _T_8237 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_8238 = eq(_T_8237, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_8239 = and(ic_valid_ff, _T_8238) @[el2_ifu_mem_ctl.scala 741:64] + node _T_8240 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_8241 = and(_T_8239, _T_8240) @[el2_ifu_mem_ctl.scala 741:89] + node _T_8242 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05e")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_8243 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_8244 = and(_T_8242, _T_8243) @[el2_ifu_mem_ctl.scala 742:58] + node _T_8245 = eq(perr_ic_index_ff, UInt<7>("h05e")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_8246 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_8247 = and(_T_8245, _T_8246) @[el2_ifu_mem_ctl.scala 742:123] + node _T_8248 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_8249 = and(_T_8247, _T_8248) @[el2_ifu_mem_ctl.scala 742:144] + node _T_8250 = or(_T_8244, _T_8249) @[el2_ifu_mem_ctl.scala 742:80] + node _T_8251 = bits(_T_8250, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_8252 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8251 : @[Reg.scala 28:19] _T_8252 <= _T_8241 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][94] <= _T_8252 @[el2_ifu_mem_ctl.scala 740:39] - node _T_8253 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_8254 = eq(_T_8253, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_8255 = and(ic_valid_ff, _T_8254) @[el2_ifu_mem_ctl.scala 740:64] - node _T_8256 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_8257 = and(_T_8255, _T_8256) @[el2_ifu_mem_ctl.scala 740:89] - node _T_8258 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05f")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_8259 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_8260 = and(_T_8258, _T_8259) @[el2_ifu_mem_ctl.scala 741:58] - node _T_8261 = eq(perr_ic_index_ff, UInt<7>("h05f")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_8262 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_8263 = and(_T_8261, _T_8262) @[el2_ifu_mem_ctl.scala 741:123] - node _T_8264 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_8265 = and(_T_8263, _T_8264) @[el2_ifu_mem_ctl.scala 741:144] - node _T_8266 = or(_T_8260, _T_8265) @[el2_ifu_mem_ctl.scala 741:80] - node _T_8267 = bits(_T_8266, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][94] <= _T_8252 @[el2_ifu_mem_ctl.scala 741:39] + node _T_8253 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_8254 = eq(_T_8253, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_8255 = and(ic_valid_ff, _T_8254) @[el2_ifu_mem_ctl.scala 741:64] + node _T_8256 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_8257 = and(_T_8255, _T_8256) @[el2_ifu_mem_ctl.scala 741:89] + node _T_8258 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05f")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_8259 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_8260 = and(_T_8258, _T_8259) @[el2_ifu_mem_ctl.scala 742:58] + node _T_8261 = eq(perr_ic_index_ff, UInt<7>("h05f")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_8262 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_8263 = and(_T_8261, _T_8262) @[el2_ifu_mem_ctl.scala 742:123] + node _T_8264 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_8265 = and(_T_8263, _T_8264) @[el2_ifu_mem_ctl.scala 742:144] + node _T_8266 = or(_T_8260, _T_8265) @[el2_ifu_mem_ctl.scala 742:80] + node _T_8267 = bits(_T_8266, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_8268 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8267 : @[Reg.scala 28:19] _T_8268 <= _T_8257 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][95] <= _T_8268 @[el2_ifu_mem_ctl.scala 740:39] - node _T_8269 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_8270 = eq(_T_8269, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_8271 = and(ic_valid_ff, _T_8270) @[el2_ifu_mem_ctl.scala 740:64] - node _T_8272 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_8273 = and(_T_8271, _T_8272) @[el2_ifu_mem_ctl.scala 740:89] - node _T_8274 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h060")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_8275 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_8276 = and(_T_8274, _T_8275) @[el2_ifu_mem_ctl.scala 741:58] - node _T_8277 = eq(perr_ic_index_ff, UInt<7>("h060")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_8278 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_8279 = and(_T_8277, _T_8278) @[el2_ifu_mem_ctl.scala 741:123] - node _T_8280 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_8281 = and(_T_8279, _T_8280) @[el2_ifu_mem_ctl.scala 741:144] - node _T_8282 = or(_T_8276, _T_8281) @[el2_ifu_mem_ctl.scala 741:80] - node _T_8283 = bits(_T_8282, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][95] <= _T_8268 @[el2_ifu_mem_ctl.scala 741:39] + node _T_8269 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_8270 = eq(_T_8269, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_8271 = and(ic_valid_ff, _T_8270) @[el2_ifu_mem_ctl.scala 741:64] + node _T_8272 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_8273 = and(_T_8271, _T_8272) @[el2_ifu_mem_ctl.scala 741:89] + node _T_8274 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h060")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_8275 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_8276 = and(_T_8274, _T_8275) @[el2_ifu_mem_ctl.scala 742:58] + node _T_8277 = eq(perr_ic_index_ff, UInt<7>("h060")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_8278 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_8279 = and(_T_8277, _T_8278) @[el2_ifu_mem_ctl.scala 742:123] + node _T_8280 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_8281 = and(_T_8279, _T_8280) @[el2_ifu_mem_ctl.scala 742:144] + node _T_8282 = or(_T_8276, _T_8281) @[el2_ifu_mem_ctl.scala 742:80] + node _T_8283 = bits(_T_8282, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_8284 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8283 : @[Reg.scala 28:19] _T_8284 <= _T_8273 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][96] <= _T_8284 @[el2_ifu_mem_ctl.scala 740:39] - node _T_8285 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_8286 = eq(_T_8285, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_8287 = and(ic_valid_ff, _T_8286) @[el2_ifu_mem_ctl.scala 740:64] - node _T_8288 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_8289 = and(_T_8287, _T_8288) @[el2_ifu_mem_ctl.scala 740:89] - node _T_8290 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h061")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_8291 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_8292 = and(_T_8290, _T_8291) @[el2_ifu_mem_ctl.scala 741:58] - node _T_8293 = eq(perr_ic_index_ff, UInt<7>("h061")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_8294 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_8295 = and(_T_8293, _T_8294) @[el2_ifu_mem_ctl.scala 741:123] - node _T_8296 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_8297 = and(_T_8295, _T_8296) @[el2_ifu_mem_ctl.scala 741:144] - node _T_8298 = or(_T_8292, _T_8297) @[el2_ifu_mem_ctl.scala 741:80] - node _T_8299 = bits(_T_8298, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][96] <= _T_8284 @[el2_ifu_mem_ctl.scala 741:39] + node _T_8285 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_8286 = eq(_T_8285, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_8287 = and(ic_valid_ff, _T_8286) @[el2_ifu_mem_ctl.scala 741:64] + node _T_8288 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_8289 = and(_T_8287, _T_8288) @[el2_ifu_mem_ctl.scala 741:89] + node _T_8290 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h061")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_8291 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_8292 = and(_T_8290, _T_8291) @[el2_ifu_mem_ctl.scala 742:58] + node _T_8293 = eq(perr_ic_index_ff, UInt<7>("h061")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_8294 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_8295 = and(_T_8293, _T_8294) @[el2_ifu_mem_ctl.scala 742:123] + node _T_8296 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_8297 = and(_T_8295, _T_8296) @[el2_ifu_mem_ctl.scala 742:144] + node _T_8298 = or(_T_8292, _T_8297) @[el2_ifu_mem_ctl.scala 742:80] + node _T_8299 = bits(_T_8298, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_8300 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8299 : @[Reg.scala 28:19] _T_8300 <= _T_8289 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][97] <= _T_8300 @[el2_ifu_mem_ctl.scala 740:39] - node _T_8301 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_8302 = eq(_T_8301, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_8303 = and(ic_valid_ff, _T_8302) @[el2_ifu_mem_ctl.scala 740:64] - node _T_8304 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_8305 = and(_T_8303, _T_8304) @[el2_ifu_mem_ctl.scala 740:89] - node _T_8306 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h062")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_8307 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_8308 = and(_T_8306, _T_8307) @[el2_ifu_mem_ctl.scala 741:58] - node _T_8309 = eq(perr_ic_index_ff, UInt<7>("h062")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_8310 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_8311 = and(_T_8309, _T_8310) @[el2_ifu_mem_ctl.scala 741:123] - node _T_8312 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_8313 = and(_T_8311, _T_8312) @[el2_ifu_mem_ctl.scala 741:144] - node _T_8314 = or(_T_8308, _T_8313) @[el2_ifu_mem_ctl.scala 741:80] - node _T_8315 = bits(_T_8314, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][97] <= _T_8300 @[el2_ifu_mem_ctl.scala 741:39] + node _T_8301 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_8302 = eq(_T_8301, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_8303 = and(ic_valid_ff, _T_8302) @[el2_ifu_mem_ctl.scala 741:64] + node _T_8304 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_8305 = and(_T_8303, _T_8304) @[el2_ifu_mem_ctl.scala 741:89] + node _T_8306 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h062")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_8307 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_8308 = and(_T_8306, _T_8307) @[el2_ifu_mem_ctl.scala 742:58] + node _T_8309 = eq(perr_ic_index_ff, UInt<7>("h062")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_8310 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_8311 = and(_T_8309, _T_8310) @[el2_ifu_mem_ctl.scala 742:123] + node _T_8312 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_8313 = and(_T_8311, _T_8312) @[el2_ifu_mem_ctl.scala 742:144] + node _T_8314 = or(_T_8308, _T_8313) @[el2_ifu_mem_ctl.scala 742:80] + node _T_8315 = bits(_T_8314, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_8316 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8315 : @[Reg.scala 28:19] _T_8316 <= _T_8305 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][98] <= _T_8316 @[el2_ifu_mem_ctl.scala 740:39] - node _T_8317 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_8318 = eq(_T_8317, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_8319 = and(ic_valid_ff, _T_8318) @[el2_ifu_mem_ctl.scala 740:64] - node _T_8320 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_8321 = and(_T_8319, _T_8320) @[el2_ifu_mem_ctl.scala 740:89] - node _T_8322 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h063")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_8323 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_8324 = and(_T_8322, _T_8323) @[el2_ifu_mem_ctl.scala 741:58] - node _T_8325 = eq(perr_ic_index_ff, UInt<7>("h063")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_8326 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_8327 = and(_T_8325, _T_8326) @[el2_ifu_mem_ctl.scala 741:123] - node _T_8328 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_8329 = and(_T_8327, _T_8328) @[el2_ifu_mem_ctl.scala 741:144] - node _T_8330 = or(_T_8324, _T_8329) @[el2_ifu_mem_ctl.scala 741:80] - node _T_8331 = bits(_T_8330, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][98] <= _T_8316 @[el2_ifu_mem_ctl.scala 741:39] + node _T_8317 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_8318 = eq(_T_8317, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_8319 = and(ic_valid_ff, _T_8318) @[el2_ifu_mem_ctl.scala 741:64] + node _T_8320 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_8321 = and(_T_8319, _T_8320) @[el2_ifu_mem_ctl.scala 741:89] + node _T_8322 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h063")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_8323 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_8324 = and(_T_8322, _T_8323) @[el2_ifu_mem_ctl.scala 742:58] + node _T_8325 = eq(perr_ic_index_ff, UInt<7>("h063")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_8326 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_8327 = and(_T_8325, _T_8326) @[el2_ifu_mem_ctl.scala 742:123] + node _T_8328 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_8329 = and(_T_8327, _T_8328) @[el2_ifu_mem_ctl.scala 742:144] + node _T_8330 = or(_T_8324, _T_8329) @[el2_ifu_mem_ctl.scala 742:80] + node _T_8331 = bits(_T_8330, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_8332 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8331 : @[Reg.scala 28:19] _T_8332 <= _T_8321 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][99] <= _T_8332 @[el2_ifu_mem_ctl.scala 740:39] - node _T_8333 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_8334 = eq(_T_8333, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_8335 = and(ic_valid_ff, _T_8334) @[el2_ifu_mem_ctl.scala 740:64] - node _T_8336 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_8337 = and(_T_8335, _T_8336) @[el2_ifu_mem_ctl.scala 740:89] - node _T_8338 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h064")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_8339 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_8340 = and(_T_8338, _T_8339) @[el2_ifu_mem_ctl.scala 741:58] - node _T_8341 = eq(perr_ic_index_ff, UInt<7>("h064")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_8342 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_8343 = and(_T_8341, _T_8342) @[el2_ifu_mem_ctl.scala 741:123] - node _T_8344 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_8345 = and(_T_8343, _T_8344) @[el2_ifu_mem_ctl.scala 741:144] - node _T_8346 = or(_T_8340, _T_8345) @[el2_ifu_mem_ctl.scala 741:80] - node _T_8347 = bits(_T_8346, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][99] <= _T_8332 @[el2_ifu_mem_ctl.scala 741:39] + node _T_8333 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_8334 = eq(_T_8333, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_8335 = and(ic_valid_ff, _T_8334) @[el2_ifu_mem_ctl.scala 741:64] + node _T_8336 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_8337 = and(_T_8335, _T_8336) @[el2_ifu_mem_ctl.scala 741:89] + node _T_8338 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h064")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_8339 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_8340 = and(_T_8338, _T_8339) @[el2_ifu_mem_ctl.scala 742:58] + node _T_8341 = eq(perr_ic_index_ff, UInt<7>("h064")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_8342 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_8343 = and(_T_8341, _T_8342) @[el2_ifu_mem_ctl.scala 742:123] + node _T_8344 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_8345 = and(_T_8343, _T_8344) @[el2_ifu_mem_ctl.scala 742:144] + node _T_8346 = or(_T_8340, _T_8345) @[el2_ifu_mem_ctl.scala 742:80] + node _T_8347 = bits(_T_8346, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_8348 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8347 : @[Reg.scala 28:19] _T_8348 <= _T_8337 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][100] <= _T_8348 @[el2_ifu_mem_ctl.scala 740:39] - node _T_8349 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_8350 = eq(_T_8349, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_8351 = and(ic_valid_ff, _T_8350) @[el2_ifu_mem_ctl.scala 740:64] - node _T_8352 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_8353 = and(_T_8351, _T_8352) @[el2_ifu_mem_ctl.scala 740:89] - node _T_8354 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h065")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_8355 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_8356 = and(_T_8354, _T_8355) @[el2_ifu_mem_ctl.scala 741:58] - node _T_8357 = eq(perr_ic_index_ff, UInt<7>("h065")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_8358 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_8359 = and(_T_8357, _T_8358) @[el2_ifu_mem_ctl.scala 741:123] - node _T_8360 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_8361 = and(_T_8359, _T_8360) @[el2_ifu_mem_ctl.scala 741:144] - node _T_8362 = or(_T_8356, _T_8361) @[el2_ifu_mem_ctl.scala 741:80] - node _T_8363 = bits(_T_8362, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][100] <= _T_8348 @[el2_ifu_mem_ctl.scala 741:39] + node _T_8349 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_8350 = eq(_T_8349, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_8351 = and(ic_valid_ff, _T_8350) @[el2_ifu_mem_ctl.scala 741:64] + node _T_8352 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_8353 = and(_T_8351, _T_8352) @[el2_ifu_mem_ctl.scala 741:89] + node _T_8354 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h065")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_8355 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_8356 = and(_T_8354, _T_8355) @[el2_ifu_mem_ctl.scala 742:58] + node _T_8357 = eq(perr_ic_index_ff, UInt<7>("h065")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_8358 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_8359 = and(_T_8357, _T_8358) @[el2_ifu_mem_ctl.scala 742:123] + node _T_8360 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_8361 = and(_T_8359, _T_8360) @[el2_ifu_mem_ctl.scala 742:144] + node _T_8362 = or(_T_8356, _T_8361) @[el2_ifu_mem_ctl.scala 742:80] + node _T_8363 = bits(_T_8362, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_8364 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8363 : @[Reg.scala 28:19] _T_8364 <= _T_8353 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][101] <= _T_8364 @[el2_ifu_mem_ctl.scala 740:39] - node _T_8365 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_8366 = eq(_T_8365, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_8367 = and(ic_valid_ff, _T_8366) @[el2_ifu_mem_ctl.scala 740:64] - node _T_8368 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_8369 = and(_T_8367, _T_8368) @[el2_ifu_mem_ctl.scala 740:89] - node _T_8370 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h066")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_8371 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_8372 = and(_T_8370, _T_8371) @[el2_ifu_mem_ctl.scala 741:58] - node _T_8373 = eq(perr_ic_index_ff, UInt<7>("h066")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_8374 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_8375 = and(_T_8373, _T_8374) @[el2_ifu_mem_ctl.scala 741:123] - node _T_8376 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_8377 = and(_T_8375, _T_8376) @[el2_ifu_mem_ctl.scala 741:144] - node _T_8378 = or(_T_8372, _T_8377) @[el2_ifu_mem_ctl.scala 741:80] - node _T_8379 = bits(_T_8378, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][101] <= _T_8364 @[el2_ifu_mem_ctl.scala 741:39] + node _T_8365 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_8366 = eq(_T_8365, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_8367 = and(ic_valid_ff, _T_8366) @[el2_ifu_mem_ctl.scala 741:64] + node _T_8368 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_8369 = and(_T_8367, _T_8368) @[el2_ifu_mem_ctl.scala 741:89] + node _T_8370 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h066")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_8371 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_8372 = and(_T_8370, _T_8371) @[el2_ifu_mem_ctl.scala 742:58] + node _T_8373 = eq(perr_ic_index_ff, UInt<7>("h066")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_8374 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_8375 = and(_T_8373, _T_8374) @[el2_ifu_mem_ctl.scala 742:123] + node _T_8376 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_8377 = and(_T_8375, _T_8376) @[el2_ifu_mem_ctl.scala 742:144] + node _T_8378 = or(_T_8372, _T_8377) @[el2_ifu_mem_ctl.scala 742:80] + node _T_8379 = bits(_T_8378, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_8380 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8379 : @[Reg.scala 28:19] _T_8380 <= _T_8369 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][102] <= _T_8380 @[el2_ifu_mem_ctl.scala 740:39] - node _T_8381 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_8382 = eq(_T_8381, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_8383 = and(ic_valid_ff, _T_8382) @[el2_ifu_mem_ctl.scala 740:64] - node _T_8384 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_8385 = and(_T_8383, _T_8384) @[el2_ifu_mem_ctl.scala 740:89] - node _T_8386 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h067")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_8387 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_8388 = and(_T_8386, _T_8387) @[el2_ifu_mem_ctl.scala 741:58] - node _T_8389 = eq(perr_ic_index_ff, UInt<7>("h067")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_8390 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_8391 = and(_T_8389, _T_8390) @[el2_ifu_mem_ctl.scala 741:123] - node _T_8392 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_8393 = and(_T_8391, _T_8392) @[el2_ifu_mem_ctl.scala 741:144] - node _T_8394 = or(_T_8388, _T_8393) @[el2_ifu_mem_ctl.scala 741:80] - node _T_8395 = bits(_T_8394, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][102] <= _T_8380 @[el2_ifu_mem_ctl.scala 741:39] + node _T_8381 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_8382 = eq(_T_8381, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_8383 = and(ic_valid_ff, _T_8382) @[el2_ifu_mem_ctl.scala 741:64] + node _T_8384 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_8385 = and(_T_8383, _T_8384) @[el2_ifu_mem_ctl.scala 741:89] + node _T_8386 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h067")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_8387 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_8388 = and(_T_8386, _T_8387) @[el2_ifu_mem_ctl.scala 742:58] + node _T_8389 = eq(perr_ic_index_ff, UInt<7>("h067")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_8390 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_8391 = and(_T_8389, _T_8390) @[el2_ifu_mem_ctl.scala 742:123] + node _T_8392 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_8393 = and(_T_8391, _T_8392) @[el2_ifu_mem_ctl.scala 742:144] + node _T_8394 = or(_T_8388, _T_8393) @[el2_ifu_mem_ctl.scala 742:80] + node _T_8395 = bits(_T_8394, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_8396 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8395 : @[Reg.scala 28:19] _T_8396 <= _T_8385 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][103] <= _T_8396 @[el2_ifu_mem_ctl.scala 740:39] - node _T_8397 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_8398 = eq(_T_8397, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_8399 = and(ic_valid_ff, _T_8398) @[el2_ifu_mem_ctl.scala 740:64] - node _T_8400 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_8401 = and(_T_8399, _T_8400) @[el2_ifu_mem_ctl.scala 740:89] - node _T_8402 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h068")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_8403 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_8404 = and(_T_8402, _T_8403) @[el2_ifu_mem_ctl.scala 741:58] - node _T_8405 = eq(perr_ic_index_ff, UInt<7>("h068")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_8406 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_8407 = and(_T_8405, _T_8406) @[el2_ifu_mem_ctl.scala 741:123] - node _T_8408 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_8409 = and(_T_8407, _T_8408) @[el2_ifu_mem_ctl.scala 741:144] - node _T_8410 = or(_T_8404, _T_8409) @[el2_ifu_mem_ctl.scala 741:80] - node _T_8411 = bits(_T_8410, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][103] <= _T_8396 @[el2_ifu_mem_ctl.scala 741:39] + node _T_8397 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_8398 = eq(_T_8397, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_8399 = and(ic_valid_ff, _T_8398) @[el2_ifu_mem_ctl.scala 741:64] + node _T_8400 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_8401 = and(_T_8399, _T_8400) @[el2_ifu_mem_ctl.scala 741:89] + node _T_8402 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h068")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_8403 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_8404 = and(_T_8402, _T_8403) @[el2_ifu_mem_ctl.scala 742:58] + node _T_8405 = eq(perr_ic_index_ff, UInt<7>("h068")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_8406 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_8407 = and(_T_8405, _T_8406) @[el2_ifu_mem_ctl.scala 742:123] + node _T_8408 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_8409 = and(_T_8407, _T_8408) @[el2_ifu_mem_ctl.scala 742:144] + node _T_8410 = or(_T_8404, _T_8409) @[el2_ifu_mem_ctl.scala 742:80] + node _T_8411 = bits(_T_8410, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_8412 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8411 : @[Reg.scala 28:19] _T_8412 <= _T_8401 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][104] <= _T_8412 @[el2_ifu_mem_ctl.scala 740:39] - node _T_8413 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_8414 = eq(_T_8413, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_8415 = and(ic_valid_ff, _T_8414) @[el2_ifu_mem_ctl.scala 740:64] - node _T_8416 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_8417 = and(_T_8415, _T_8416) @[el2_ifu_mem_ctl.scala 740:89] - node _T_8418 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h069")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_8419 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_8420 = and(_T_8418, _T_8419) @[el2_ifu_mem_ctl.scala 741:58] - node _T_8421 = eq(perr_ic_index_ff, UInt<7>("h069")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_8422 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_8423 = and(_T_8421, _T_8422) @[el2_ifu_mem_ctl.scala 741:123] - node _T_8424 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_8425 = and(_T_8423, _T_8424) @[el2_ifu_mem_ctl.scala 741:144] - node _T_8426 = or(_T_8420, _T_8425) @[el2_ifu_mem_ctl.scala 741:80] - node _T_8427 = bits(_T_8426, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][104] <= _T_8412 @[el2_ifu_mem_ctl.scala 741:39] + node _T_8413 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_8414 = eq(_T_8413, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_8415 = and(ic_valid_ff, _T_8414) @[el2_ifu_mem_ctl.scala 741:64] + node _T_8416 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_8417 = and(_T_8415, _T_8416) @[el2_ifu_mem_ctl.scala 741:89] + node _T_8418 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h069")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_8419 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_8420 = and(_T_8418, _T_8419) @[el2_ifu_mem_ctl.scala 742:58] + node _T_8421 = eq(perr_ic_index_ff, UInt<7>("h069")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_8422 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_8423 = and(_T_8421, _T_8422) @[el2_ifu_mem_ctl.scala 742:123] + node _T_8424 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_8425 = and(_T_8423, _T_8424) @[el2_ifu_mem_ctl.scala 742:144] + node _T_8426 = or(_T_8420, _T_8425) @[el2_ifu_mem_ctl.scala 742:80] + node _T_8427 = bits(_T_8426, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_8428 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8427 : @[Reg.scala 28:19] _T_8428 <= _T_8417 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][105] <= _T_8428 @[el2_ifu_mem_ctl.scala 740:39] - node _T_8429 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_8430 = eq(_T_8429, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_8431 = and(ic_valid_ff, _T_8430) @[el2_ifu_mem_ctl.scala 740:64] - node _T_8432 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_8433 = and(_T_8431, _T_8432) @[el2_ifu_mem_ctl.scala 740:89] - node _T_8434 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06a")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_8435 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_8436 = and(_T_8434, _T_8435) @[el2_ifu_mem_ctl.scala 741:58] - node _T_8437 = eq(perr_ic_index_ff, UInt<7>("h06a")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_8438 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_8439 = and(_T_8437, _T_8438) @[el2_ifu_mem_ctl.scala 741:123] - node _T_8440 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_8441 = and(_T_8439, _T_8440) @[el2_ifu_mem_ctl.scala 741:144] - node _T_8442 = or(_T_8436, _T_8441) @[el2_ifu_mem_ctl.scala 741:80] - node _T_8443 = bits(_T_8442, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][105] <= _T_8428 @[el2_ifu_mem_ctl.scala 741:39] + node _T_8429 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_8430 = eq(_T_8429, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_8431 = and(ic_valid_ff, _T_8430) @[el2_ifu_mem_ctl.scala 741:64] + node _T_8432 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_8433 = and(_T_8431, _T_8432) @[el2_ifu_mem_ctl.scala 741:89] + node _T_8434 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06a")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_8435 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_8436 = and(_T_8434, _T_8435) @[el2_ifu_mem_ctl.scala 742:58] + node _T_8437 = eq(perr_ic_index_ff, UInt<7>("h06a")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_8438 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_8439 = and(_T_8437, _T_8438) @[el2_ifu_mem_ctl.scala 742:123] + node _T_8440 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_8441 = and(_T_8439, _T_8440) @[el2_ifu_mem_ctl.scala 742:144] + node _T_8442 = or(_T_8436, _T_8441) @[el2_ifu_mem_ctl.scala 742:80] + node _T_8443 = bits(_T_8442, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_8444 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8443 : @[Reg.scala 28:19] _T_8444 <= _T_8433 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][106] <= _T_8444 @[el2_ifu_mem_ctl.scala 740:39] - node _T_8445 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_8446 = eq(_T_8445, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_8447 = and(ic_valid_ff, _T_8446) @[el2_ifu_mem_ctl.scala 740:64] - node _T_8448 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_8449 = and(_T_8447, _T_8448) @[el2_ifu_mem_ctl.scala 740:89] - node _T_8450 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06b")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_8451 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_8452 = and(_T_8450, _T_8451) @[el2_ifu_mem_ctl.scala 741:58] - node _T_8453 = eq(perr_ic_index_ff, UInt<7>("h06b")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_8454 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_8455 = and(_T_8453, _T_8454) @[el2_ifu_mem_ctl.scala 741:123] - node _T_8456 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_8457 = and(_T_8455, _T_8456) @[el2_ifu_mem_ctl.scala 741:144] - node _T_8458 = or(_T_8452, _T_8457) @[el2_ifu_mem_ctl.scala 741:80] - node _T_8459 = bits(_T_8458, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][106] <= _T_8444 @[el2_ifu_mem_ctl.scala 741:39] + node _T_8445 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_8446 = eq(_T_8445, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_8447 = and(ic_valid_ff, _T_8446) @[el2_ifu_mem_ctl.scala 741:64] + node _T_8448 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_8449 = and(_T_8447, _T_8448) @[el2_ifu_mem_ctl.scala 741:89] + node _T_8450 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06b")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_8451 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_8452 = and(_T_8450, _T_8451) @[el2_ifu_mem_ctl.scala 742:58] + node _T_8453 = eq(perr_ic_index_ff, UInt<7>("h06b")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_8454 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_8455 = and(_T_8453, _T_8454) @[el2_ifu_mem_ctl.scala 742:123] + node _T_8456 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_8457 = and(_T_8455, _T_8456) @[el2_ifu_mem_ctl.scala 742:144] + node _T_8458 = or(_T_8452, _T_8457) @[el2_ifu_mem_ctl.scala 742:80] + node _T_8459 = bits(_T_8458, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_8460 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8459 : @[Reg.scala 28:19] _T_8460 <= _T_8449 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][107] <= _T_8460 @[el2_ifu_mem_ctl.scala 740:39] - node _T_8461 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_8462 = eq(_T_8461, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_8463 = and(ic_valid_ff, _T_8462) @[el2_ifu_mem_ctl.scala 740:64] - node _T_8464 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_8465 = and(_T_8463, _T_8464) @[el2_ifu_mem_ctl.scala 740:89] - node _T_8466 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06c")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_8467 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_8468 = and(_T_8466, _T_8467) @[el2_ifu_mem_ctl.scala 741:58] - node _T_8469 = eq(perr_ic_index_ff, UInt<7>("h06c")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_8470 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_8471 = and(_T_8469, _T_8470) @[el2_ifu_mem_ctl.scala 741:123] - node _T_8472 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_8473 = and(_T_8471, _T_8472) @[el2_ifu_mem_ctl.scala 741:144] - node _T_8474 = or(_T_8468, _T_8473) @[el2_ifu_mem_ctl.scala 741:80] - node _T_8475 = bits(_T_8474, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][107] <= _T_8460 @[el2_ifu_mem_ctl.scala 741:39] + node _T_8461 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_8462 = eq(_T_8461, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_8463 = and(ic_valid_ff, _T_8462) @[el2_ifu_mem_ctl.scala 741:64] + node _T_8464 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_8465 = and(_T_8463, _T_8464) @[el2_ifu_mem_ctl.scala 741:89] + node _T_8466 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06c")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_8467 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_8468 = and(_T_8466, _T_8467) @[el2_ifu_mem_ctl.scala 742:58] + node _T_8469 = eq(perr_ic_index_ff, UInt<7>("h06c")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_8470 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_8471 = and(_T_8469, _T_8470) @[el2_ifu_mem_ctl.scala 742:123] + node _T_8472 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_8473 = and(_T_8471, _T_8472) @[el2_ifu_mem_ctl.scala 742:144] + node _T_8474 = or(_T_8468, _T_8473) @[el2_ifu_mem_ctl.scala 742:80] + node _T_8475 = bits(_T_8474, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_8476 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8475 : @[Reg.scala 28:19] _T_8476 <= _T_8465 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][108] <= _T_8476 @[el2_ifu_mem_ctl.scala 740:39] - node _T_8477 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_8478 = eq(_T_8477, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_8479 = and(ic_valid_ff, _T_8478) @[el2_ifu_mem_ctl.scala 740:64] - node _T_8480 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_8481 = and(_T_8479, _T_8480) @[el2_ifu_mem_ctl.scala 740:89] - node _T_8482 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06d")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_8483 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_8484 = and(_T_8482, _T_8483) @[el2_ifu_mem_ctl.scala 741:58] - node _T_8485 = eq(perr_ic_index_ff, UInt<7>("h06d")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_8486 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_8487 = and(_T_8485, _T_8486) @[el2_ifu_mem_ctl.scala 741:123] - node _T_8488 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_8489 = and(_T_8487, _T_8488) @[el2_ifu_mem_ctl.scala 741:144] - node _T_8490 = or(_T_8484, _T_8489) @[el2_ifu_mem_ctl.scala 741:80] - node _T_8491 = bits(_T_8490, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][108] <= _T_8476 @[el2_ifu_mem_ctl.scala 741:39] + node _T_8477 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_8478 = eq(_T_8477, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_8479 = and(ic_valid_ff, _T_8478) @[el2_ifu_mem_ctl.scala 741:64] + node _T_8480 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_8481 = and(_T_8479, _T_8480) @[el2_ifu_mem_ctl.scala 741:89] + node _T_8482 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06d")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_8483 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_8484 = and(_T_8482, _T_8483) @[el2_ifu_mem_ctl.scala 742:58] + node _T_8485 = eq(perr_ic_index_ff, UInt<7>("h06d")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_8486 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_8487 = and(_T_8485, _T_8486) @[el2_ifu_mem_ctl.scala 742:123] + node _T_8488 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_8489 = and(_T_8487, _T_8488) @[el2_ifu_mem_ctl.scala 742:144] + node _T_8490 = or(_T_8484, _T_8489) @[el2_ifu_mem_ctl.scala 742:80] + node _T_8491 = bits(_T_8490, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_8492 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8491 : @[Reg.scala 28:19] _T_8492 <= _T_8481 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][109] <= _T_8492 @[el2_ifu_mem_ctl.scala 740:39] - node _T_8493 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_8494 = eq(_T_8493, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_8495 = and(ic_valid_ff, _T_8494) @[el2_ifu_mem_ctl.scala 740:64] - node _T_8496 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_8497 = and(_T_8495, _T_8496) @[el2_ifu_mem_ctl.scala 740:89] - node _T_8498 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06e")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_8499 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_8500 = and(_T_8498, _T_8499) @[el2_ifu_mem_ctl.scala 741:58] - node _T_8501 = eq(perr_ic_index_ff, UInt<7>("h06e")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_8502 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_8503 = and(_T_8501, _T_8502) @[el2_ifu_mem_ctl.scala 741:123] - node _T_8504 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_8505 = and(_T_8503, _T_8504) @[el2_ifu_mem_ctl.scala 741:144] - node _T_8506 = or(_T_8500, _T_8505) @[el2_ifu_mem_ctl.scala 741:80] - node _T_8507 = bits(_T_8506, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][109] <= _T_8492 @[el2_ifu_mem_ctl.scala 741:39] + node _T_8493 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_8494 = eq(_T_8493, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_8495 = and(ic_valid_ff, _T_8494) @[el2_ifu_mem_ctl.scala 741:64] + node _T_8496 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_8497 = and(_T_8495, _T_8496) @[el2_ifu_mem_ctl.scala 741:89] + node _T_8498 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06e")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_8499 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_8500 = and(_T_8498, _T_8499) @[el2_ifu_mem_ctl.scala 742:58] + node _T_8501 = eq(perr_ic_index_ff, UInt<7>("h06e")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_8502 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_8503 = and(_T_8501, _T_8502) @[el2_ifu_mem_ctl.scala 742:123] + node _T_8504 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_8505 = and(_T_8503, _T_8504) @[el2_ifu_mem_ctl.scala 742:144] + node _T_8506 = or(_T_8500, _T_8505) @[el2_ifu_mem_ctl.scala 742:80] + node _T_8507 = bits(_T_8506, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_8508 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8507 : @[Reg.scala 28:19] _T_8508 <= _T_8497 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][110] <= _T_8508 @[el2_ifu_mem_ctl.scala 740:39] - node _T_8509 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_8510 = eq(_T_8509, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_8511 = and(ic_valid_ff, _T_8510) @[el2_ifu_mem_ctl.scala 740:64] - node _T_8512 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_8513 = and(_T_8511, _T_8512) @[el2_ifu_mem_ctl.scala 740:89] - node _T_8514 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06f")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_8515 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_8516 = and(_T_8514, _T_8515) @[el2_ifu_mem_ctl.scala 741:58] - node _T_8517 = eq(perr_ic_index_ff, UInt<7>("h06f")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_8518 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_8519 = and(_T_8517, _T_8518) @[el2_ifu_mem_ctl.scala 741:123] - node _T_8520 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_8521 = and(_T_8519, _T_8520) @[el2_ifu_mem_ctl.scala 741:144] - node _T_8522 = or(_T_8516, _T_8521) @[el2_ifu_mem_ctl.scala 741:80] - node _T_8523 = bits(_T_8522, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][110] <= _T_8508 @[el2_ifu_mem_ctl.scala 741:39] + node _T_8509 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_8510 = eq(_T_8509, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_8511 = and(ic_valid_ff, _T_8510) @[el2_ifu_mem_ctl.scala 741:64] + node _T_8512 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_8513 = and(_T_8511, _T_8512) @[el2_ifu_mem_ctl.scala 741:89] + node _T_8514 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06f")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_8515 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_8516 = and(_T_8514, _T_8515) @[el2_ifu_mem_ctl.scala 742:58] + node _T_8517 = eq(perr_ic_index_ff, UInt<7>("h06f")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_8518 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_8519 = and(_T_8517, _T_8518) @[el2_ifu_mem_ctl.scala 742:123] + node _T_8520 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_8521 = and(_T_8519, _T_8520) @[el2_ifu_mem_ctl.scala 742:144] + node _T_8522 = or(_T_8516, _T_8521) @[el2_ifu_mem_ctl.scala 742:80] + node _T_8523 = bits(_T_8522, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_8524 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8523 : @[Reg.scala 28:19] _T_8524 <= _T_8513 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][111] <= _T_8524 @[el2_ifu_mem_ctl.scala 740:39] - node _T_8525 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_8526 = eq(_T_8525, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_8527 = and(ic_valid_ff, _T_8526) @[el2_ifu_mem_ctl.scala 740:64] - node _T_8528 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_8529 = and(_T_8527, _T_8528) @[el2_ifu_mem_ctl.scala 740:89] - node _T_8530 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h070")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_8531 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_8532 = and(_T_8530, _T_8531) @[el2_ifu_mem_ctl.scala 741:58] - node _T_8533 = eq(perr_ic_index_ff, UInt<7>("h070")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_8534 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_8535 = and(_T_8533, _T_8534) @[el2_ifu_mem_ctl.scala 741:123] - node _T_8536 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_8537 = and(_T_8535, _T_8536) @[el2_ifu_mem_ctl.scala 741:144] - node _T_8538 = or(_T_8532, _T_8537) @[el2_ifu_mem_ctl.scala 741:80] - node _T_8539 = bits(_T_8538, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][111] <= _T_8524 @[el2_ifu_mem_ctl.scala 741:39] + node _T_8525 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_8526 = eq(_T_8525, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_8527 = and(ic_valid_ff, _T_8526) @[el2_ifu_mem_ctl.scala 741:64] + node _T_8528 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_8529 = and(_T_8527, _T_8528) @[el2_ifu_mem_ctl.scala 741:89] + node _T_8530 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h070")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_8531 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_8532 = and(_T_8530, _T_8531) @[el2_ifu_mem_ctl.scala 742:58] + node _T_8533 = eq(perr_ic_index_ff, UInt<7>("h070")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_8534 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_8535 = and(_T_8533, _T_8534) @[el2_ifu_mem_ctl.scala 742:123] + node _T_8536 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_8537 = and(_T_8535, _T_8536) @[el2_ifu_mem_ctl.scala 742:144] + node _T_8538 = or(_T_8532, _T_8537) @[el2_ifu_mem_ctl.scala 742:80] + node _T_8539 = bits(_T_8538, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_8540 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8539 : @[Reg.scala 28:19] _T_8540 <= _T_8529 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][112] <= _T_8540 @[el2_ifu_mem_ctl.scala 740:39] - node _T_8541 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_8542 = eq(_T_8541, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_8543 = and(ic_valid_ff, _T_8542) @[el2_ifu_mem_ctl.scala 740:64] - node _T_8544 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_8545 = and(_T_8543, _T_8544) @[el2_ifu_mem_ctl.scala 740:89] - node _T_8546 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h071")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_8547 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_8548 = and(_T_8546, _T_8547) @[el2_ifu_mem_ctl.scala 741:58] - node _T_8549 = eq(perr_ic_index_ff, UInt<7>("h071")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_8550 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_8551 = and(_T_8549, _T_8550) @[el2_ifu_mem_ctl.scala 741:123] - node _T_8552 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_8553 = and(_T_8551, _T_8552) @[el2_ifu_mem_ctl.scala 741:144] - node _T_8554 = or(_T_8548, _T_8553) @[el2_ifu_mem_ctl.scala 741:80] - node _T_8555 = bits(_T_8554, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][112] <= _T_8540 @[el2_ifu_mem_ctl.scala 741:39] + node _T_8541 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_8542 = eq(_T_8541, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_8543 = and(ic_valid_ff, _T_8542) @[el2_ifu_mem_ctl.scala 741:64] + node _T_8544 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_8545 = and(_T_8543, _T_8544) @[el2_ifu_mem_ctl.scala 741:89] + node _T_8546 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h071")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_8547 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_8548 = and(_T_8546, _T_8547) @[el2_ifu_mem_ctl.scala 742:58] + node _T_8549 = eq(perr_ic_index_ff, UInt<7>("h071")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_8550 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_8551 = and(_T_8549, _T_8550) @[el2_ifu_mem_ctl.scala 742:123] + node _T_8552 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_8553 = and(_T_8551, _T_8552) @[el2_ifu_mem_ctl.scala 742:144] + node _T_8554 = or(_T_8548, _T_8553) @[el2_ifu_mem_ctl.scala 742:80] + node _T_8555 = bits(_T_8554, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_8556 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8555 : @[Reg.scala 28:19] _T_8556 <= _T_8545 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][113] <= _T_8556 @[el2_ifu_mem_ctl.scala 740:39] - node _T_8557 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_8558 = eq(_T_8557, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_8559 = and(ic_valid_ff, _T_8558) @[el2_ifu_mem_ctl.scala 740:64] - node _T_8560 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_8561 = and(_T_8559, _T_8560) @[el2_ifu_mem_ctl.scala 740:89] - node _T_8562 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h072")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_8563 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_8564 = and(_T_8562, _T_8563) @[el2_ifu_mem_ctl.scala 741:58] - node _T_8565 = eq(perr_ic_index_ff, UInt<7>("h072")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_8566 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_8567 = and(_T_8565, _T_8566) @[el2_ifu_mem_ctl.scala 741:123] - node _T_8568 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_8569 = and(_T_8567, _T_8568) @[el2_ifu_mem_ctl.scala 741:144] - node _T_8570 = or(_T_8564, _T_8569) @[el2_ifu_mem_ctl.scala 741:80] - node _T_8571 = bits(_T_8570, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][113] <= _T_8556 @[el2_ifu_mem_ctl.scala 741:39] + node _T_8557 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_8558 = eq(_T_8557, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_8559 = and(ic_valid_ff, _T_8558) @[el2_ifu_mem_ctl.scala 741:64] + node _T_8560 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_8561 = and(_T_8559, _T_8560) @[el2_ifu_mem_ctl.scala 741:89] + node _T_8562 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h072")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_8563 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_8564 = and(_T_8562, _T_8563) @[el2_ifu_mem_ctl.scala 742:58] + node _T_8565 = eq(perr_ic_index_ff, UInt<7>("h072")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_8566 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_8567 = and(_T_8565, _T_8566) @[el2_ifu_mem_ctl.scala 742:123] + node _T_8568 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_8569 = and(_T_8567, _T_8568) @[el2_ifu_mem_ctl.scala 742:144] + node _T_8570 = or(_T_8564, _T_8569) @[el2_ifu_mem_ctl.scala 742:80] + node _T_8571 = bits(_T_8570, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_8572 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8571 : @[Reg.scala 28:19] _T_8572 <= _T_8561 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][114] <= _T_8572 @[el2_ifu_mem_ctl.scala 740:39] - node _T_8573 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_8574 = eq(_T_8573, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_8575 = and(ic_valid_ff, _T_8574) @[el2_ifu_mem_ctl.scala 740:64] - node _T_8576 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_8577 = and(_T_8575, _T_8576) @[el2_ifu_mem_ctl.scala 740:89] - node _T_8578 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h073")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_8579 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_8580 = and(_T_8578, _T_8579) @[el2_ifu_mem_ctl.scala 741:58] - node _T_8581 = eq(perr_ic_index_ff, UInt<7>("h073")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_8582 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_8583 = and(_T_8581, _T_8582) @[el2_ifu_mem_ctl.scala 741:123] - node _T_8584 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_8585 = and(_T_8583, _T_8584) @[el2_ifu_mem_ctl.scala 741:144] - node _T_8586 = or(_T_8580, _T_8585) @[el2_ifu_mem_ctl.scala 741:80] - node _T_8587 = bits(_T_8586, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][114] <= _T_8572 @[el2_ifu_mem_ctl.scala 741:39] + node _T_8573 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_8574 = eq(_T_8573, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_8575 = and(ic_valid_ff, _T_8574) @[el2_ifu_mem_ctl.scala 741:64] + node _T_8576 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_8577 = and(_T_8575, _T_8576) @[el2_ifu_mem_ctl.scala 741:89] + node _T_8578 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h073")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_8579 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_8580 = and(_T_8578, _T_8579) @[el2_ifu_mem_ctl.scala 742:58] + node _T_8581 = eq(perr_ic_index_ff, UInt<7>("h073")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_8582 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_8583 = and(_T_8581, _T_8582) @[el2_ifu_mem_ctl.scala 742:123] + node _T_8584 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_8585 = and(_T_8583, _T_8584) @[el2_ifu_mem_ctl.scala 742:144] + node _T_8586 = or(_T_8580, _T_8585) @[el2_ifu_mem_ctl.scala 742:80] + node _T_8587 = bits(_T_8586, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_8588 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8587 : @[Reg.scala 28:19] _T_8588 <= _T_8577 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][115] <= _T_8588 @[el2_ifu_mem_ctl.scala 740:39] - node _T_8589 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_8590 = eq(_T_8589, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_8591 = and(ic_valid_ff, _T_8590) @[el2_ifu_mem_ctl.scala 740:64] - node _T_8592 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_8593 = and(_T_8591, _T_8592) @[el2_ifu_mem_ctl.scala 740:89] - node _T_8594 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h074")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_8595 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_8596 = and(_T_8594, _T_8595) @[el2_ifu_mem_ctl.scala 741:58] - node _T_8597 = eq(perr_ic_index_ff, UInt<7>("h074")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_8598 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_8599 = and(_T_8597, _T_8598) @[el2_ifu_mem_ctl.scala 741:123] - node _T_8600 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_8601 = and(_T_8599, _T_8600) @[el2_ifu_mem_ctl.scala 741:144] - node _T_8602 = or(_T_8596, _T_8601) @[el2_ifu_mem_ctl.scala 741:80] - node _T_8603 = bits(_T_8602, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][115] <= _T_8588 @[el2_ifu_mem_ctl.scala 741:39] + node _T_8589 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_8590 = eq(_T_8589, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_8591 = and(ic_valid_ff, _T_8590) @[el2_ifu_mem_ctl.scala 741:64] + node _T_8592 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_8593 = and(_T_8591, _T_8592) @[el2_ifu_mem_ctl.scala 741:89] + node _T_8594 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h074")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_8595 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_8596 = and(_T_8594, _T_8595) @[el2_ifu_mem_ctl.scala 742:58] + node _T_8597 = eq(perr_ic_index_ff, UInt<7>("h074")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_8598 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_8599 = and(_T_8597, _T_8598) @[el2_ifu_mem_ctl.scala 742:123] + node _T_8600 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_8601 = and(_T_8599, _T_8600) @[el2_ifu_mem_ctl.scala 742:144] + node _T_8602 = or(_T_8596, _T_8601) @[el2_ifu_mem_ctl.scala 742:80] + node _T_8603 = bits(_T_8602, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_8604 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8603 : @[Reg.scala 28:19] _T_8604 <= _T_8593 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][116] <= _T_8604 @[el2_ifu_mem_ctl.scala 740:39] - node _T_8605 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_8606 = eq(_T_8605, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_8607 = and(ic_valid_ff, _T_8606) @[el2_ifu_mem_ctl.scala 740:64] - node _T_8608 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_8609 = and(_T_8607, _T_8608) @[el2_ifu_mem_ctl.scala 740:89] - node _T_8610 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h075")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_8611 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_8612 = and(_T_8610, _T_8611) @[el2_ifu_mem_ctl.scala 741:58] - node _T_8613 = eq(perr_ic_index_ff, UInt<7>("h075")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_8614 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_8615 = and(_T_8613, _T_8614) @[el2_ifu_mem_ctl.scala 741:123] - node _T_8616 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_8617 = and(_T_8615, _T_8616) @[el2_ifu_mem_ctl.scala 741:144] - node _T_8618 = or(_T_8612, _T_8617) @[el2_ifu_mem_ctl.scala 741:80] - node _T_8619 = bits(_T_8618, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][116] <= _T_8604 @[el2_ifu_mem_ctl.scala 741:39] + node _T_8605 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_8606 = eq(_T_8605, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_8607 = and(ic_valid_ff, _T_8606) @[el2_ifu_mem_ctl.scala 741:64] + node _T_8608 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_8609 = and(_T_8607, _T_8608) @[el2_ifu_mem_ctl.scala 741:89] + node _T_8610 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h075")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_8611 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_8612 = and(_T_8610, _T_8611) @[el2_ifu_mem_ctl.scala 742:58] + node _T_8613 = eq(perr_ic_index_ff, UInt<7>("h075")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_8614 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_8615 = and(_T_8613, _T_8614) @[el2_ifu_mem_ctl.scala 742:123] + node _T_8616 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_8617 = and(_T_8615, _T_8616) @[el2_ifu_mem_ctl.scala 742:144] + node _T_8618 = or(_T_8612, _T_8617) @[el2_ifu_mem_ctl.scala 742:80] + node _T_8619 = bits(_T_8618, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_8620 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8619 : @[Reg.scala 28:19] _T_8620 <= _T_8609 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][117] <= _T_8620 @[el2_ifu_mem_ctl.scala 740:39] - node _T_8621 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_8622 = eq(_T_8621, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_8623 = and(ic_valid_ff, _T_8622) @[el2_ifu_mem_ctl.scala 740:64] - node _T_8624 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_8625 = and(_T_8623, _T_8624) @[el2_ifu_mem_ctl.scala 740:89] - node _T_8626 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h076")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_8627 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_8628 = and(_T_8626, _T_8627) @[el2_ifu_mem_ctl.scala 741:58] - node _T_8629 = eq(perr_ic_index_ff, UInt<7>("h076")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_8630 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_8631 = and(_T_8629, _T_8630) @[el2_ifu_mem_ctl.scala 741:123] - node _T_8632 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_8633 = and(_T_8631, _T_8632) @[el2_ifu_mem_ctl.scala 741:144] - node _T_8634 = or(_T_8628, _T_8633) @[el2_ifu_mem_ctl.scala 741:80] - node _T_8635 = bits(_T_8634, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][117] <= _T_8620 @[el2_ifu_mem_ctl.scala 741:39] + node _T_8621 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_8622 = eq(_T_8621, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_8623 = and(ic_valid_ff, _T_8622) @[el2_ifu_mem_ctl.scala 741:64] + node _T_8624 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_8625 = and(_T_8623, _T_8624) @[el2_ifu_mem_ctl.scala 741:89] + node _T_8626 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h076")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_8627 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_8628 = and(_T_8626, _T_8627) @[el2_ifu_mem_ctl.scala 742:58] + node _T_8629 = eq(perr_ic_index_ff, UInt<7>("h076")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_8630 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_8631 = and(_T_8629, _T_8630) @[el2_ifu_mem_ctl.scala 742:123] + node _T_8632 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_8633 = and(_T_8631, _T_8632) @[el2_ifu_mem_ctl.scala 742:144] + node _T_8634 = or(_T_8628, _T_8633) @[el2_ifu_mem_ctl.scala 742:80] + node _T_8635 = bits(_T_8634, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_8636 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8635 : @[Reg.scala 28:19] _T_8636 <= _T_8625 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][118] <= _T_8636 @[el2_ifu_mem_ctl.scala 740:39] - node _T_8637 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_8638 = eq(_T_8637, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_8639 = and(ic_valid_ff, _T_8638) @[el2_ifu_mem_ctl.scala 740:64] - node _T_8640 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_8641 = and(_T_8639, _T_8640) @[el2_ifu_mem_ctl.scala 740:89] - node _T_8642 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h077")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_8643 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_8644 = and(_T_8642, _T_8643) @[el2_ifu_mem_ctl.scala 741:58] - node _T_8645 = eq(perr_ic_index_ff, UInt<7>("h077")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_8646 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_8647 = and(_T_8645, _T_8646) @[el2_ifu_mem_ctl.scala 741:123] - node _T_8648 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_8649 = and(_T_8647, _T_8648) @[el2_ifu_mem_ctl.scala 741:144] - node _T_8650 = or(_T_8644, _T_8649) @[el2_ifu_mem_ctl.scala 741:80] - node _T_8651 = bits(_T_8650, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][118] <= _T_8636 @[el2_ifu_mem_ctl.scala 741:39] + node _T_8637 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_8638 = eq(_T_8637, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_8639 = and(ic_valid_ff, _T_8638) @[el2_ifu_mem_ctl.scala 741:64] + node _T_8640 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_8641 = and(_T_8639, _T_8640) @[el2_ifu_mem_ctl.scala 741:89] + node _T_8642 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h077")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_8643 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_8644 = and(_T_8642, _T_8643) @[el2_ifu_mem_ctl.scala 742:58] + node _T_8645 = eq(perr_ic_index_ff, UInt<7>("h077")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_8646 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_8647 = and(_T_8645, _T_8646) @[el2_ifu_mem_ctl.scala 742:123] + node _T_8648 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_8649 = and(_T_8647, _T_8648) @[el2_ifu_mem_ctl.scala 742:144] + node _T_8650 = or(_T_8644, _T_8649) @[el2_ifu_mem_ctl.scala 742:80] + node _T_8651 = bits(_T_8650, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_8652 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8651 : @[Reg.scala 28:19] _T_8652 <= _T_8641 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][119] <= _T_8652 @[el2_ifu_mem_ctl.scala 740:39] - node _T_8653 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_8654 = eq(_T_8653, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_8655 = and(ic_valid_ff, _T_8654) @[el2_ifu_mem_ctl.scala 740:64] - node _T_8656 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_8657 = and(_T_8655, _T_8656) @[el2_ifu_mem_ctl.scala 740:89] - node _T_8658 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h078")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_8659 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_8660 = and(_T_8658, _T_8659) @[el2_ifu_mem_ctl.scala 741:58] - node _T_8661 = eq(perr_ic_index_ff, UInt<7>("h078")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_8662 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_8663 = and(_T_8661, _T_8662) @[el2_ifu_mem_ctl.scala 741:123] - node _T_8664 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_8665 = and(_T_8663, _T_8664) @[el2_ifu_mem_ctl.scala 741:144] - node _T_8666 = or(_T_8660, _T_8665) @[el2_ifu_mem_ctl.scala 741:80] - node _T_8667 = bits(_T_8666, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][119] <= _T_8652 @[el2_ifu_mem_ctl.scala 741:39] + node _T_8653 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_8654 = eq(_T_8653, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_8655 = and(ic_valid_ff, _T_8654) @[el2_ifu_mem_ctl.scala 741:64] + node _T_8656 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_8657 = and(_T_8655, _T_8656) @[el2_ifu_mem_ctl.scala 741:89] + node _T_8658 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h078")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_8659 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_8660 = and(_T_8658, _T_8659) @[el2_ifu_mem_ctl.scala 742:58] + node _T_8661 = eq(perr_ic_index_ff, UInt<7>("h078")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_8662 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_8663 = and(_T_8661, _T_8662) @[el2_ifu_mem_ctl.scala 742:123] + node _T_8664 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_8665 = and(_T_8663, _T_8664) @[el2_ifu_mem_ctl.scala 742:144] + node _T_8666 = or(_T_8660, _T_8665) @[el2_ifu_mem_ctl.scala 742:80] + node _T_8667 = bits(_T_8666, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_8668 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8667 : @[Reg.scala 28:19] _T_8668 <= _T_8657 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][120] <= _T_8668 @[el2_ifu_mem_ctl.scala 740:39] - node _T_8669 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_8670 = eq(_T_8669, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_8671 = and(ic_valid_ff, _T_8670) @[el2_ifu_mem_ctl.scala 740:64] - node _T_8672 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_8673 = and(_T_8671, _T_8672) @[el2_ifu_mem_ctl.scala 740:89] - node _T_8674 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h079")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_8675 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_8676 = and(_T_8674, _T_8675) @[el2_ifu_mem_ctl.scala 741:58] - node _T_8677 = eq(perr_ic_index_ff, UInt<7>("h079")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_8678 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_8679 = and(_T_8677, _T_8678) @[el2_ifu_mem_ctl.scala 741:123] - node _T_8680 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_8681 = and(_T_8679, _T_8680) @[el2_ifu_mem_ctl.scala 741:144] - node _T_8682 = or(_T_8676, _T_8681) @[el2_ifu_mem_ctl.scala 741:80] - node _T_8683 = bits(_T_8682, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][120] <= _T_8668 @[el2_ifu_mem_ctl.scala 741:39] + node _T_8669 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_8670 = eq(_T_8669, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_8671 = and(ic_valid_ff, _T_8670) @[el2_ifu_mem_ctl.scala 741:64] + node _T_8672 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_8673 = and(_T_8671, _T_8672) @[el2_ifu_mem_ctl.scala 741:89] + node _T_8674 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h079")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_8675 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_8676 = and(_T_8674, _T_8675) @[el2_ifu_mem_ctl.scala 742:58] + node _T_8677 = eq(perr_ic_index_ff, UInt<7>("h079")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_8678 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_8679 = and(_T_8677, _T_8678) @[el2_ifu_mem_ctl.scala 742:123] + node _T_8680 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_8681 = and(_T_8679, _T_8680) @[el2_ifu_mem_ctl.scala 742:144] + node _T_8682 = or(_T_8676, _T_8681) @[el2_ifu_mem_ctl.scala 742:80] + node _T_8683 = bits(_T_8682, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_8684 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8683 : @[Reg.scala 28:19] _T_8684 <= _T_8673 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][121] <= _T_8684 @[el2_ifu_mem_ctl.scala 740:39] - node _T_8685 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_8686 = eq(_T_8685, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_8687 = and(ic_valid_ff, _T_8686) @[el2_ifu_mem_ctl.scala 740:64] - node _T_8688 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_8689 = and(_T_8687, _T_8688) @[el2_ifu_mem_ctl.scala 740:89] - node _T_8690 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07a")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_8691 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_8692 = and(_T_8690, _T_8691) @[el2_ifu_mem_ctl.scala 741:58] - node _T_8693 = eq(perr_ic_index_ff, UInt<7>("h07a")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_8694 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_8695 = and(_T_8693, _T_8694) @[el2_ifu_mem_ctl.scala 741:123] - node _T_8696 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_8697 = and(_T_8695, _T_8696) @[el2_ifu_mem_ctl.scala 741:144] - node _T_8698 = or(_T_8692, _T_8697) @[el2_ifu_mem_ctl.scala 741:80] - node _T_8699 = bits(_T_8698, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][121] <= _T_8684 @[el2_ifu_mem_ctl.scala 741:39] + node _T_8685 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_8686 = eq(_T_8685, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_8687 = and(ic_valid_ff, _T_8686) @[el2_ifu_mem_ctl.scala 741:64] + node _T_8688 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_8689 = and(_T_8687, _T_8688) @[el2_ifu_mem_ctl.scala 741:89] + node _T_8690 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07a")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_8691 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_8692 = and(_T_8690, _T_8691) @[el2_ifu_mem_ctl.scala 742:58] + node _T_8693 = eq(perr_ic_index_ff, UInt<7>("h07a")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_8694 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_8695 = and(_T_8693, _T_8694) @[el2_ifu_mem_ctl.scala 742:123] + node _T_8696 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_8697 = and(_T_8695, _T_8696) @[el2_ifu_mem_ctl.scala 742:144] + node _T_8698 = or(_T_8692, _T_8697) @[el2_ifu_mem_ctl.scala 742:80] + node _T_8699 = bits(_T_8698, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_8700 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8699 : @[Reg.scala 28:19] _T_8700 <= _T_8689 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][122] <= _T_8700 @[el2_ifu_mem_ctl.scala 740:39] - node _T_8701 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_8702 = eq(_T_8701, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_8703 = and(ic_valid_ff, _T_8702) @[el2_ifu_mem_ctl.scala 740:64] - node _T_8704 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_8705 = and(_T_8703, _T_8704) @[el2_ifu_mem_ctl.scala 740:89] - node _T_8706 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07b")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_8707 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_8708 = and(_T_8706, _T_8707) @[el2_ifu_mem_ctl.scala 741:58] - node _T_8709 = eq(perr_ic_index_ff, UInt<7>("h07b")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_8710 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_8711 = and(_T_8709, _T_8710) @[el2_ifu_mem_ctl.scala 741:123] - node _T_8712 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_8713 = and(_T_8711, _T_8712) @[el2_ifu_mem_ctl.scala 741:144] - node _T_8714 = or(_T_8708, _T_8713) @[el2_ifu_mem_ctl.scala 741:80] - node _T_8715 = bits(_T_8714, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][122] <= _T_8700 @[el2_ifu_mem_ctl.scala 741:39] + node _T_8701 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_8702 = eq(_T_8701, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_8703 = and(ic_valid_ff, _T_8702) @[el2_ifu_mem_ctl.scala 741:64] + node _T_8704 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_8705 = and(_T_8703, _T_8704) @[el2_ifu_mem_ctl.scala 741:89] + node _T_8706 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07b")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_8707 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_8708 = and(_T_8706, _T_8707) @[el2_ifu_mem_ctl.scala 742:58] + node _T_8709 = eq(perr_ic_index_ff, UInt<7>("h07b")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_8710 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_8711 = and(_T_8709, _T_8710) @[el2_ifu_mem_ctl.scala 742:123] + node _T_8712 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_8713 = and(_T_8711, _T_8712) @[el2_ifu_mem_ctl.scala 742:144] + node _T_8714 = or(_T_8708, _T_8713) @[el2_ifu_mem_ctl.scala 742:80] + node _T_8715 = bits(_T_8714, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_8716 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8715 : @[Reg.scala 28:19] _T_8716 <= _T_8705 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][123] <= _T_8716 @[el2_ifu_mem_ctl.scala 740:39] - node _T_8717 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_8718 = eq(_T_8717, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_8719 = and(ic_valid_ff, _T_8718) @[el2_ifu_mem_ctl.scala 740:64] - node _T_8720 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_8721 = and(_T_8719, _T_8720) @[el2_ifu_mem_ctl.scala 740:89] - node _T_8722 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07c")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_8723 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_8724 = and(_T_8722, _T_8723) @[el2_ifu_mem_ctl.scala 741:58] - node _T_8725 = eq(perr_ic_index_ff, UInt<7>("h07c")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_8726 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_8727 = and(_T_8725, _T_8726) @[el2_ifu_mem_ctl.scala 741:123] - node _T_8728 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_8729 = and(_T_8727, _T_8728) @[el2_ifu_mem_ctl.scala 741:144] - node _T_8730 = or(_T_8724, _T_8729) @[el2_ifu_mem_ctl.scala 741:80] - node _T_8731 = bits(_T_8730, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][123] <= _T_8716 @[el2_ifu_mem_ctl.scala 741:39] + node _T_8717 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_8718 = eq(_T_8717, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_8719 = and(ic_valid_ff, _T_8718) @[el2_ifu_mem_ctl.scala 741:64] + node _T_8720 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_8721 = and(_T_8719, _T_8720) @[el2_ifu_mem_ctl.scala 741:89] + node _T_8722 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07c")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_8723 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_8724 = and(_T_8722, _T_8723) @[el2_ifu_mem_ctl.scala 742:58] + node _T_8725 = eq(perr_ic_index_ff, UInt<7>("h07c")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_8726 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_8727 = and(_T_8725, _T_8726) @[el2_ifu_mem_ctl.scala 742:123] + node _T_8728 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_8729 = and(_T_8727, _T_8728) @[el2_ifu_mem_ctl.scala 742:144] + node _T_8730 = or(_T_8724, _T_8729) @[el2_ifu_mem_ctl.scala 742:80] + node _T_8731 = bits(_T_8730, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_8732 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8731 : @[Reg.scala 28:19] _T_8732 <= _T_8721 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][124] <= _T_8732 @[el2_ifu_mem_ctl.scala 740:39] - node _T_8733 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_8734 = eq(_T_8733, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_8735 = and(ic_valid_ff, _T_8734) @[el2_ifu_mem_ctl.scala 740:64] - node _T_8736 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_8737 = and(_T_8735, _T_8736) @[el2_ifu_mem_ctl.scala 740:89] - node _T_8738 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07d")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_8739 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_8740 = and(_T_8738, _T_8739) @[el2_ifu_mem_ctl.scala 741:58] - node _T_8741 = eq(perr_ic_index_ff, UInt<7>("h07d")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_8742 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_8743 = and(_T_8741, _T_8742) @[el2_ifu_mem_ctl.scala 741:123] - node _T_8744 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_8745 = and(_T_8743, _T_8744) @[el2_ifu_mem_ctl.scala 741:144] - node _T_8746 = or(_T_8740, _T_8745) @[el2_ifu_mem_ctl.scala 741:80] - node _T_8747 = bits(_T_8746, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][124] <= _T_8732 @[el2_ifu_mem_ctl.scala 741:39] + node _T_8733 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_8734 = eq(_T_8733, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_8735 = and(ic_valid_ff, _T_8734) @[el2_ifu_mem_ctl.scala 741:64] + node _T_8736 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_8737 = and(_T_8735, _T_8736) @[el2_ifu_mem_ctl.scala 741:89] + node _T_8738 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07d")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_8739 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_8740 = and(_T_8738, _T_8739) @[el2_ifu_mem_ctl.scala 742:58] + node _T_8741 = eq(perr_ic_index_ff, UInt<7>("h07d")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_8742 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_8743 = and(_T_8741, _T_8742) @[el2_ifu_mem_ctl.scala 742:123] + node _T_8744 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_8745 = and(_T_8743, _T_8744) @[el2_ifu_mem_ctl.scala 742:144] + node _T_8746 = or(_T_8740, _T_8745) @[el2_ifu_mem_ctl.scala 742:80] + node _T_8747 = bits(_T_8746, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_8748 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8747 : @[Reg.scala 28:19] _T_8748 <= _T_8737 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][125] <= _T_8748 @[el2_ifu_mem_ctl.scala 740:39] - node _T_8749 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_8750 = eq(_T_8749, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_8751 = and(ic_valid_ff, _T_8750) @[el2_ifu_mem_ctl.scala 740:64] - node _T_8752 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_8753 = and(_T_8751, _T_8752) @[el2_ifu_mem_ctl.scala 740:89] - node _T_8754 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07e")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_8755 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_8756 = and(_T_8754, _T_8755) @[el2_ifu_mem_ctl.scala 741:58] - node _T_8757 = eq(perr_ic_index_ff, UInt<7>("h07e")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_8758 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_8759 = and(_T_8757, _T_8758) @[el2_ifu_mem_ctl.scala 741:123] - node _T_8760 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_8761 = and(_T_8759, _T_8760) @[el2_ifu_mem_ctl.scala 741:144] - node _T_8762 = or(_T_8756, _T_8761) @[el2_ifu_mem_ctl.scala 741:80] - node _T_8763 = bits(_T_8762, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][125] <= _T_8748 @[el2_ifu_mem_ctl.scala 741:39] + node _T_8749 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_8750 = eq(_T_8749, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_8751 = and(ic_valid_ff, _T_8750) @[el2_ifu_mem_ctl.scala 741:64] + node _T_8752 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_8753 = and(_T_8751, _T_8752) @[el2_ifu_mem_ctl.scala 741:89] + node _T_8754 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07e")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_8755 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_8756 = and(_T_8754, _T_8755) @[el2_ifu_mem_ctl.scala 742:58] + node _T_8757 = eq(perr_ic_index_ff, UInt<7>("h07e")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_8758 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_8759 = and(_T_8757, _T_8758) @[el2_ifu_mem_ctl.scala 742:123] + node _T_8760 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_8761 = and(_T_8759, _T_8760) @[el2_ifu_mem_ctl.scala 742:144] + node _T_8762 = or(_T_8756, _T_8761) @[el2_ifu_mem_ctl.scala 742:80] + node _T_8763 = bits(_T_8762, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_8764 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8763 : @[Reg.scala 28:19] _T_8764 <= _T_8753 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][126] <= _T_8764 @[el2_ifu_mem_ctl.scala 740:39] - node _T_8765 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_8766 = eq(_T_8765, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_8767 = and(ic_valid_ff, _T_8766) @[el2_ifu_mem_ctl.scala 740:64] - node _T_8768 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_8769 = and(_T_8767, _T_8768) @[el2_ifu_mem_ctl.scala 740:89] - node _T_8770 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07f")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_8771 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:75] - node _T_8772 = and(_T_8770, _T_8771) @[el2_ifu_mem_ctl.scala 741:58] - node _T_8773 = eq(perr_ic_index_ff, UInt<7>("h07f")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_8774 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 741:140] - node _T_8775 = and(_T_8773, _T_8774) @[el2_ifu_mem_ctl.scala 741:123] - node _T_8776 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 741:163] - node _T_8777 = and(_T_8775, _T_8776) @[el2_ifu_mem_ctl.scala 741:144] - node _T_8778 = or(_T_8772, _T_8777) @[el2_ifu_mem_ctl.scala 741:80] - node _T_8779 = bits(_T_8778, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][126] <= _T_8764 @[el2_ifu_mem_ctl.scala 741:39] + node _T_8765 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_8766 = eq(_T_8765, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_8767 = and(ic_valid_ff, _T_8766) @[el2_ifu_mem_ctl.scala 741:64] + node _T_8768 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_8769 = and(_T_8767, _T_8768) @[el2_ifu_mem_ctl.scala 741:89] + node _T_8770 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07f")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_8771 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:75] + node _T_8772 = and(_T_8770, _T_8771) @[el2_ifu_mem_ctl.scala 742:58] + node _T_8773 = eq(perr_ic_index_ff, UInt<7>("h07f")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_8774 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:140] + node _T_8775 = and(_T_8773, _T_8774) @[el2_ifu_mem_ctl.scala 742:123] + node _T_8776 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 742:163] + node _T_8777 = and(_T_8775, _T_8776) @[el2_ifu_mem_ctl.scala 742:144] + node _T_8778 = or(_T_8772, _T_8777) @[el2_ifu_mem_ctl.scala 742:80] + node _T_8779 = bits(_T_8778, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_8780 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8779 : @[Reg.scala 28:19] _T_8780 <= _T_8769 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[0][127] <= _T_8780 @[el2_ifu_mem_ctl.scala 740:39] - node _T_8781 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_8782 = eq(_T_8781, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_8783 = and(ic_valid_ff, _T_8782) @[el2_ifu_mem_ctl.scala 740:64] - node _T_8784 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_8785 = and(_T_8783, _T_8784) @[el2_ifu_mem_ctl.scala 740:89] - node _T_8786 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h060")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_8787 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_8788 = and(_T_8786, _T_8787) @[el2_ifu_mem_ctl.scala 741:58] - node _T_8789 = eq(perr_ic_index_ff, UInt<7>("h060")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_8790 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_8791 = and(_T_8789, _T_8790) @[el2_ifu_mem_ctl.scala 741:123] - node _T_8792 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_8793 = and(_T_8791, _T_8792) @[el2_ifu_mem_ctl.scala 741:144] - node _T_8794 = or(_T_8788, _T_8793) @[el2_ifu_mem_ctl.scala 741:80] - node _T_8795 = bits(_T_8794, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[0][127] <= _T_8780 @[el2_ifu_mem_ctl.scala 741:39] + node _T_8781 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_8782 = eq(_T_8781, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_8783 = and(ic_valid_ff, _T_8782) @[el2_ifu_mem_ctl.scala 741:64] + node _T_8784 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_8785 = and(_T_8783, _T_8784) @[el2_ifu_mem_ctl.scala 741:89] + node _T_8786 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h060")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_8787 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_8788 = and(_T_8786, _T_8787) @[el2_ifu_mem_ctl.scala 742:58] + node _T_8789 = eq(perr_ic_index_ff, UInt<7>("h060")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_8790 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_8791 = and(_T_8789, _T_8790) @[el2_ifu_mem_ctl.scala 742:123] + node _T_8792 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_8793 = and(_T_8791, _T_8792) @[el2_ifu_mem_ctl.scala 742:144] + node _T_8794 = or(_T_8788, _T_8793) @[el2_ifu_mem_ctl.scala 742:80] + node _T_8795 = bits(_T_8794, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_8796 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8795 : @[Reg.scala 28:19] _T_8796 <= _T_8785 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][96] <= _T_8796 @[el2_ifu_mem_ctl.scala 740:39] - node _T_8797 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_8798 = eq(_T_8797, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_8799 = and(ic_valid_ff, _T_8798) @[el2_ifu_mem_ctl.scala 740:64] - node _T_8800 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_8801 = and(_T_8799, _T_8800) @[el2_ifu_mem_ctl.scala 740:89] - node _T_8802 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h061")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_8803 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_8804 = and(_T_8802, _T_8803) @[el2_ifu_mem_ctl.scala 741:58] - node _T_8805 = eq(perr_ic_index_ff, UInt<7>("h061")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_8806 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_8807 = and(_T_8805, _T_8806) @[el2_ifu_mem_ctl.scala 741:123] - node _T_8808 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_8809 = and(_T_8807, _T_8808) @[el2_ifu_mem_ctl.scala 741:144] - node _T_8810 = or(_T_8804, _T_8809) @[el2_ifu_mem_ctl.scala 741:80] - node _T_8811 = bits(_T_8810, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][96] <= _T_8796 @[el2_ifu_mem_ctl.scala 741:39] + node _T_8797 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_8798 = eq(_T_8797, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_8799 = and(ic_valid_ff, _T_8798) @[el2_ifu_mem_ctl.scala 741:64] + node _T_8800 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_8801 = and(_T_8799, _T_8800) @[el2_ifu_mem_ctl.scala 741:89] + node _T_8802 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h061")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_8803 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_8804 = and(_T_8802, _T_8803) @[el2_ifu_mem_ctl.scala 742:58] + node _T_8805 = eq(perr_ic_index_ff, UInt<7>("h061")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_8806 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_8807 = and(_T_8805, _T_8806) @[el2_ifu_mem_ctl.scala 742:123] + node _T_8808 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_8809 = and(_T_8807, _T_8808) @[el2_ifu_mem_ctl.scala 742:144] + node _T_8810 = or(_T_8804, _T_8809) @[el2_ifu_mem_ctl.scala 742:80] + node _T_8811 = bits(_T_8810, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_8812 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8811 : @[Reg.scala 28:19] _T_8812 <= _T_8801 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][97] <= _T_8812 @[el2_ifu_mem_ctl.scala 740:39] - node _T_8813 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_8814 = eq(_T_8813, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_8815 = and(ic_valid_ff, _T_8814) @[el2_ifu_mem_ctl.scala 740:64] - node _T_8816 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_8817 = and(_T_8815, _T_8816) @[el2_ifu_mem_ctl.scala 740:89] - node _T_8818 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h062")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_8819 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_8820 = and(_T_8818, _T_8819) @[el2_ifu_mem_ctl.scala 741:58] - node _T_8821 = eq(perr_ic_index_ff, UInt<7>("h062")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_8822 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_8823 = and(_T_8821, _T_8822) @[el2_ifu_mem_ctl.scala 741:123] - node _T_8824 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_8825 = and(_T_8823, _T_8824) @[el2_ifu_mem_ctl.scala 741:144] - node _T_8826 = or(_T_8820, _T_8825) @[el2_ifu_mem_ctl.scala 741:80] - node _T_8827 = bits(_T_8826, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][97] <= _T_8812 @[el2_ifu_mem_ctl.scala 741:39] + node _T_8813 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_8814 = eq(_T_8813, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_8815 = and(ic_valid_ff, _T_8814) @[el2_ifu_mem_ctl.scala 741:64] + node _T_8816 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_8817 = and(_T_8815, _T_8816) @[el2_ifu_mem_ctl.scala 741:89] + node _T_8818 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h062")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_8819 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_8820 = and(_T_8818, _T_8819) @[el2_ifu_mem_ctl.scala 742:58] + node _T_8821 = eq(perr_ic_index_ff, UInt<7>("h062")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_8822 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_8823 = and(_T_8821, _T_8822) @[el2_ifu_mem_ctl.scala 742:123] + node _T_8824 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_8825 = and(_T_8823, _T_8824) @[el2_ifu_mem_ctl.scala 742:144] + node _T_8826 = or(_T_8820, _T_8825) @[el2_ifu_mem_ctl.scala 742:80] + node _T_8827 = bits(_T_8826, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_8828 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8827 : @[Reg.scala 28:19] _T_8828 <= _T_8817 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][98] <= _T_8828 @[el2_ifu_mem_ctl.scala 740:39] - node _T_8829 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_8830 = eq(_T_8829, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_8831 = and(ic_valid_ff, _T_8830) @[el2_ifu_mem_ctl.scala 740:64] - node _T_8832 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_8833 = and(_T_8831, _T_8832) @[el2_ifu_mem_ctl.scala 740:89] - node _T_8834 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h063")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_8835 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_8836 = and(_T_8834, _T_8835) @[el2_ifu_mem_ctl.scala 741:58] - node _T_8837 = eq(perr_ic_index_ff, UInt<7>("h063")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_8838 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_8839 = and(_T_8837, _T_8838) @[el2_ifu_mem_ctl.scala 741:123] - node _T_8840 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_8841 = and(_T_8839, _T_8840) @[el2_ifu_mem_ctl.scala 741:144] - node _T_8842 = or(_T_8836, _T_8841) @[el2_ifu_mem_ctl.scala 741:80] - node _T_8843 = bits(_T_8842, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][98] <= _T_8828 @[el2_ifu_mem_ctl.scala 741:39] + node _T_8829 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_8830 = eq(_T_8829, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_8831 = and(ic_valid_ff, _T_8830) @[el2_ifu_mem_ctl.scala 741:64] + node _T_8832 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_8833 = and(_T_8831, _T_8832) @[el2_ifu_mem_ctl.scala 741:89] + node _T_8834 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h063")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_8835 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_8836 = and(_T_8834, _T_8835) @[el2_ifu_mem_ctl.scala 742:58] + node _T_8837 = eq(perr_ic_index_ff, UInt<7>("h063")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_8838 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_8839 = and(_T_8837, _T_8838) @[el2_ifu_mem_ctl.scala 742:123] + node _T_8840 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_8841 = and(_T_8839, _T_8840) @[el2_ifu_mem_ctl.scala 742:144] + node _T_8842 = or(_T_8836, _T_8841) @[el2_ifu_mem_ctl.scala 742:80] + node _T_8843 = bits(_T_8842, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_8844 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8843 : @[Reg.scala 28:19] _T_8844 <= _T_8833 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][99] <= _T_8844 @[el2_ifu_mem_ctl.scala 740:39] - node _T_8845 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_8846 = eq(_T_8845, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_8847 = and(ic_valid_ff, _T_8846) @[el2_ifu_mem_ctl.scala 740:64] - node _T_8848 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_8849 = and(_T_8847, _T_8848) @[el2_ifu_mem_ctl.scala 740:89] - node _T_8850 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h064")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_8851 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_8852 = and(_T_8850, _T_8851) @[el2_ifu_mem_ctl.scala 741:58] - node _T_8853 = eq(perr_ic_index_ff, UInt<7>("h064")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_8854 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_8855 = and(_T_8853, _T_8854) @[el2_ifu_mem_ctl.scala 741:123] - node _T_8856 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_8857 = and(_T_8855, _T_8856) @[el2_ifu_mem_ctl.scala 741:144] - node _T_8858 = or(_T_8852, _T_8857) @[el2_ifu_mem_ctl.scala 741:80] - node _T_8859 = bits(_T_8858, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][99] <= _T_8844 @[el2_ifu_mem_ctl.scala 741:39] + node _T_8845 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_8846 = eq(_T_8845, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_8847 = and(ic_valid_ff, _T_8846) @[el2_ifu_mem_ctl.scala 741:64] + node _T_8848 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_8849 = and(_T_8847, _T_8848) @[el2_ifu_mem_ctl.scala 741:89] + node _T_8850 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h064")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_8851 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_8852 = and(_T_8850, _T_8851) @[el2_ifu_mem_ctl.scala 742:58] + node _T_8853 = eq(perr_ic_index_ff, UInt<7>("h064")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_8854 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_8855 = and(_T_8853, _T_8854) @[el2_ifu_mem_ctl.scala 742:123] + node _T_8856 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_8857 = and(_T_8855, _T_8856) @[el2_ifu_mem_ctl.scala 742:144] + node _T_8858 = or(_T_8852, _T_8857) @[el2_ifu_mem_ctl.scala 742:80] + node _T_8859 = bits(_T_8858, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_8860 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8859 : @[Reg.scala 28:19] _T_8860 <= _T_8849 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][100] <= _T_8860 @[el2_ifu_mem_ctl.scala 740:39] - node _T_8861 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_8862 = eq(_T_8861, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_8863 = and(ic_valid_ff, _T_8862) @[el2_ifu_mem_ctl.scala 740:64] - node _T_8864 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_8865 = and(_T_8863, _T_8864) @[el2_ifu_mem_ctl.scala 740:89] - node _T_8866 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h065")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_8867 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_8868 = and(_T_8866, _T_8867) @[el2_ifu_mem_ctl.scala 741:58] - node _T_8869 = eq(perr_ic_index_ff, UInt<7>("h065")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_8870 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_8871 = and(_T_8869, _T_8870) @[el2_ifu_mem_ctl.scala 741:123] - node _T_8872 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_8873 = and(_T_8871, _T_8872) @[el2_ifu_mem_ctl.scala 741:144] - node _T_8874 = or(_T_8868, _T_8873) @[el2_ifu_mem_ctl.scala 741:80] - node _T_8875 = bits(_T_8874, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][100] <= _T_8860 @[el2_ifu_mem_ctl.scala 741:39] + node _T_8861 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_8862 = eq(_T_8861, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_8863 = and(ic_valid_ff, _T_8862) @[el2_ifu_mem_ctl.scala 741:64] + node _T_8864 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_8865 = and(_T_8863, _T_8864) @[el2_ifu_mem_ctl.scala 741:89] + node _T_8866 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h065")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_8867 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_8868 = and(_T_8866, _T_8867) @[el2_ifu_mem_ctl.scala 742:58] + node _T_8869 = eq(perr_ic_index_ff, UInt<7>("h065")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_8870 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_8871 = and(_T_8869, _T_8870) @[el2_ifu_mem_ctl.scala 742:123] + node _T_8872 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_8873 = and(_T_8871, _T_8872) @[el2_ifu_mem_ctl.scala 742:144] + node _T_8874 = or(_T_8868, _T_8873) @[el2_ifu_mem_ctl.scala 742:80] + node _T_8875 = bits(_T_8874, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_8876 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8875 : @[Reg.scala 28:19] _T_8876 <= _T_8865 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][101] <= _T_8876 @[el2_ifu_mem_ctl.scala 740:39] - node _T_8877 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_8878 = eq(_T_8877, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_8879 = and(ic_valid_ff, _T_8878) @[el2_ifu_mem_ctl.scala 740:64] - node _T_8880 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_8881 = and(_T_8879, _T_8880) @[el2_ifu_mem_ctl.scala 740:89] - node _T_8882 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h066")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_8883 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_8884 = and(_T_8882, _T_8883) @[el2_ifu_mem_ctl.scala 741:58] - node _T_8885 = eq(perr_ic_index_ff, UInt<7>("h066")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_8886 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_8887 = and(_T_8885, _T_8886) @[el2_ifu_mem_ctl.scala 741:123] - node _T_8888 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_8889 = and(_T_8887, _T_8888) @[el2_ifu_mem_ctl.scala 741:144] - node _T_8890 = or(_T_8884, _T_8889) @[el2_ifu_mem_ctl.scala 741:80] - node _T_8891 = bits(_T_8890, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][101] <= _T_8876 @[el2_ifu_mem_ctl.scala 741:39] + node _T_8877 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_8878 = eq(_T_8877, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_8879 = and(ic_valid_ff, _T_8878) @[el2_ifu_mem_ctl.scala 741:64] + node _T_8880 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_8881 = and(_T_8879, _T_8880) @[el2_ifu_mem_ctl.scala 741:89] + node _T_8882 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h066")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_8883 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_8884 = and(_T_8882, _T_8883) @[el2_ifu_mem_ctl.scala 742:58] + node _T_8885 = eq(perr_ic_index_ff, UInt<7>("h066")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_8886 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_8887 = and(_T_8885, _T_8886) @[el2_ifu_mem_ctl.scala 742:123] + node _T_8888 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_8889 = and(_T_8887, _T_8888) @[el2_ifu_mem_ctl.scala 742:144] + node _T_8890 = or(_T_8884, _T_8889) @[el2_ifu_mem_ctl.scala 742:80] + node _T_8891 = bits(_T_8890, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_8892 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8891 : @[Reg.scala 28:19] _T_8892 <= _T_8881 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][102] <= _T_8892 @[el2_ifu_mem_ctl.scala 740:39] - node _T_8893 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_8894 = eq(_T_8893, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_8895 = and(ic_valid_ff, _T_8894) @[el2_ifu_mem_ctl.scala 740:64] - node _T_8896 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_8897 = and(_T_8895, _T_8896) @[el2_ifu_mem_ctl.scala 740:89] - node _T_8898 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h067")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_8899 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_8900 = and(_T_8898, _T_8899) @[el2_ifu_mem_ctl.scala 741:58] - node _T_8901 = eq(perr_ic_index_ff, UInt<7>("h067")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_8902 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_8903 = and(_T_8901, _T_8902) @[el2_ifu_mem_ctl.scala 741:123] - node _T_8904 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_8905 = and(_T_8903, _T_8904) @[el2_ifu_mem_ctl.scala 741:144] - node _T_8906 = or(_T_8900, _T_8905) @[el2_ifu_mem_ctl.scala 741:80] - node _T_8907 = bits(_T_8906, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][102] <= _T_8892 @[el2_ifu_mem_ctl.scala 741:39] + node _T_8893 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_8894 = eq(_T_8893, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_8895 = and(ic_valid_ff, _T_8894) @[el2_ifu_mem_ctl.scala 741:64] + node _T_8896 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_8897 = and(_T_8895, _T_8896) @[el2_ifu_mem_ctl.scala 741:89] + node _T_8898 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h067")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_8899 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_8900 = and(_T_8898, _T_8899) @[el2_ifu_mem_ctl.scala 742:58] + node _T_8901 = eq(perr_ic_index_ff, UInt<7>("h067")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_8902 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_8903 = and(_T_8901, _T_8902) @[el2_ifu_mem_ctl.scala 742:123] + node _T_8904 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_8905 = and(_T_8903, _T_8904) @[el2_ifu_mem_ctl.scala 742:144] + node _T_8906 = or(_T_8900, _T_8905) @[el2_ifu_mem_ctl.scala 742:80] + node _T_8907 = bits(_T_8906, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_8908 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8907 : @[Reg.scala 28:19] _T_8908 <= _T_8897 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][103] <= _T_8908 @[el2_ifu_mem_ctl.scala 740:39] - node _T_8909 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_8910 = eq(_T_8909, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_8911 = and(ic_valid_ff, _T_8910) @[el2_ifu_mem_ctl.scala 740:64] - node _T_8912 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_8913 = and(_T_8911, _T_8912) @[el2_ifu_mem_ctl.scala 740:89] - node _T_8914 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h068")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_8915 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_8916 = and(_T_8914, _T_8915) @[el2_ifu_mem_ctl.scala 741:58] - node _T_8917 = eq(perr_ic_index_ff, UInt<7>("h068")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_8918 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_8919 = and(_T_8917, _T_8918) @[el2_ifu_mem_ctl.scala 741:123] - node _T_8920 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_8921 = and(_T_8919, _T_8920) @[el2_ifu_mem_ctl.scala 741:144] - node _T_8922 = or(_T_8916, _T_8921) @[el2_ifu_mem_ctl.scala 741:80] - node _T_8923 = bits(_T_8922, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][103] <= _T_8908 @[el2_ifu_mem_ctl.scala 741:39] + node _T_8909 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_8910 = eq(_T_8909, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_8911 = and(ic_valid_ff, _T_8910) @[el2_ifu_mem_ctl.scala 741:64] + node _T_8912 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_8913 = and(_T_8911, _T_8912) @[el2_ifu_mem_ctl.scala 741:89] + node _T_8914 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h068")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_8915 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_8916 = and(_T_8914, _T_8915) @[el2_ifu_mem_ctl.scala 742:58] + node _T_8917 = eq(perr_ic_index_ff, UInt<7>("h068")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_8918 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_8919 = and(_T_8917, _T_8918) @[el2_ifu_mem_ctl.scala 742:123] + node _T_8920 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_8921 = and(_T_8919, _T_8920) @[el2_ifu_mem_ctl.scala 742:144] + node _T_8922 = or(_T_8916, _T_8921) @[el2_ifu_mem_ctl.scala 742:80] + node _T_8923 = bits(_T_8922, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_8924 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8923 : @[Reg.scala 28:19] _T_8924 <= _T_8913 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][104] <= _T_8924 @[el2_ifu_mem_ctl.scala 740:39] - node _T_8925 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_8926 = eq(_T_8925, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_8927 = and(ic_valid_ff, _T_8926) @[el2_ifu_mem_ctl.scala 740:64] - node _T_8928 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_8929 = and(_T_8927, _T_8928) @[el2_ifu_mem_ctl.scala 740:89] - node _T_8930 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h069")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_8931 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_8932 = and(_T_8930, _T_8931) @[el2_ifu_mem_ctl.scala 741:58] - node _T_8933 = eq(perr_ic_index_ff, UInt<7>("h069")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_8934 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_8935 = and(_T_8933, _T_8934) @[el2_ifu_mem_ctl.scala 741:123] - node _T_8936 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_8937 = and(_T_8935, _T_8936) @[el2_ifu_mem_ctl.scala 741:144] - node _T_8938 = or(_T_8932, _T_8937) @[el2_ifu_mem_ctl.scala 741:80] - node _T_8939 = bits(_T_8938, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][104] <= _T_8924 @[el2_ifu_mem_ctl.scala 741:39] + node _T_8925 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_8926 = eq(_T_8925, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_8927 = and(ic_valid_ff, _T_8926) @[el2_ifu_mem_ctl.scala 741:64] + node _T_8928 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_8929 = and(_T_8927, _T_8928) @[el2_ifu_mem_ctl.scala 741:89] + node _T_8930 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h069")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_8931 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_8932 = and(_T_8930, _T_8931) @[el2_ifu_mem_ctl.scala 742:58] + node _T_8933 = eq(perr_ic_index_ff, UInt<7>("h069")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_8934 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_8935 = and(_T_8933, _T_8934) @[el2_ifu_mem_ctl.scala 742:123] + node _T_8936 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_8937 = and(_T_8935, _T_8936) @[el2_ifu_mem_ctl.scala 742:144] + node _T_8938 = or(_T_8932, _T_8937) @[el2_ifu_mem_ctl.scala 742:80] + node _T_8939 = bits(_T_8938, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_8940 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8939 : @[Reg.scala 28:19] _T_8940 <= _T_8929 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][105] <= _T_8940 @[el2_ifu_mem_ctl.scala 740:39] - node _T_8941 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_8942 = eq(_T_8941, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_8943 = and(ic_valid_ff, _T_8942) @[el2_ifu_mem_ctl.scala 740:64] - node _T_8944 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_8945 = and(_T_8943, _T_8944) @[el2_ifu_mem_ctl.scala 740:89] - node _T_8946 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06a")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_8947 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_8948 = and(_T_8946, _T_8947) @[el2_ifu_mem_ctl.scala 741:58] - node _T_8949 = eq(perr_ic_index_ff, UInt<7>("h06a")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_8950 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_8951 = and(_T_8949, _T_8950) @[el2_ifu_mem_ctl.scala 741:123] - node _T_8952 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_8953 = and(_T_8951, _T_8952) @[el2_ifu_mem_ctl.scala 741:144] - node _T_8954 = or(_T_8948, _T_8953) @[el2_ifu_mem_ctl.scala 741:80] - node _T_8955 = bits(_T_8954, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][105] <= _T_8940 @[el2_ifu_mem_ctl.scala 741:39] + node _T_8941 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_8942 = eq(_T_8941, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_8943 = and(ic_valid_ff, _T_8942) @[el2_ifu_mem_ctl.scala 741:64] + node _T_8944 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_8945 = and(_T_8943, _T_8944) @[el2_ifu_mem_ctl.scala 741:89] + node _T_8946 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06a")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_8947 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_8948 = and(_T_8946, _T_8947) @[el2_ifu_mem_ctl.scala 742:58] + node _T_8949 = eq(perr_ic_index_ff, UInt<7>("h06a")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_8950 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_8951 = and(_T_8949, _T_8950) @[el2_ifu_mem_ctl.scala 742:123] + node _T_8952 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_8953 = and(_T_8951, _T_8952) @[el2_ifu_mem_ctl.scala 742:144] + node _T_8954 = or(_T_8948, _T_8953) @[el2_ifu_mem_ctl.scala 742:80] + node _T_8955 = bits(_T_8954, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_8956 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8955 : @[Reg.scala 28:19] _T_8956 <= _T_8945 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][106] <= _T_8956 @[el2_ifu_mem_ctl.scala 740:39] - node _T_8957 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_8958 = eq(_T_8957, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_8959 = and(ic_valid_ff, _T_8958) @[el2_ifu_mem_ctl.scala 740:64] - node _T_8960 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_8961 = and(_T_8959, _T_8960) @[el2_ifu_mem_ctl.scala 740:89] - node _T_8962 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06b")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_8963 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_8964 = and(_T_8962, _T_8963) @[el2_ifu_mem_ctl.scala 741:58] - node _T_8965 = eq(perr_ic_index_ff, UInt<7>("h06b")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_8966 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_8967 = and(_T_8965, _T_8966) @[el2_ifu_mem_ctl.scala 741:123] - node _T_8968 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_8969 = and(_T_8967, _T_8968) @[el2_ifu_mem_ctl.scala 741:144] - node _T_8970 = or(_T_8964, _T_8969) @[el2_ifu_mem_ctl.scala 741:80] - node _T_8971 = bits(_T_8970, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][106] <= _T_8956 @[el2_ifu_mem_ctl.scala 741:39] + node _T_8957 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_8958 = eq(_T_8957, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_8959 = and(ic_valid_ff, _T_8958) @[el2_ifu_mem_ctl.scala 741:64] + node _T_8960 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_8961 = and(_T_8959, _T_8960) @[el2_ifu_mem_ctl.scala 741:89] + node _T_8962 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06b")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_8963 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_8964 = and(_T_8962, _T_8963) @[el2_ifu_mem_ctl.scala 742:58] + node _T_8965 = eq(perr_ic_index_ff, UInt<7>("h06b")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_8966 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_8967 = and(_T_8965, _T_8966) @[el2_ifu_mem_ctl.scala 742:123] + node _T_8968 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_8969 = and(_T_8967, _T_8968) @[el2_ifu_mem_ctl.scala 742:144] + node _T_8970 = or(_T_8964, _T_8969) @[el2_ifu_mem_ctl.scala 742:80] + node _T_8971 = bits(_T_8970, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_8972 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8971 : @[Reg.scala 28:19] _T_8972 <= _T_8961 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][107] <= _T_8972 @[el2_ifu_mem_ctl.scala 740:39] - node _T_8973 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_8974 = eq(_T_8973, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_8975 = and(ic_valid_ff, _T_8974) @[el2_ifu_mem_ctl.scala 740:64] - node _T_8976 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_8977 = and(_T_8975, _T_8976) @[el2_ifu_mem_ctl.scala 740:89] - node _T_8978 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06c")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_8979 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_8980 = and(_T_8978, _T_8979) @[el2_ifu_mem_ctl.scala 741:58] - node _T_8981 = eq(perr_ic_index_ff, UInt<7>("h06c")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_8982 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_8983 = and(_T_8981, _T_8982) @[el2_ifu_mem_ctl.scala 741:123] - node _T_8984 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_8985 = and(_T_8983, _T_8984) @[el2_ifu_mem_ctl.scala 741:144] - node _T_8986 = or(_T_8980, _T_8985) @[el2_ifu_mem_ctl.scala 741:80] - node _T_8987 = bits(_T_8986, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][107] <= _T_8972 @[el2_ifu_mem_ctl.scala 741:39] + node _T_8973 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_8974 = eq(_T_8973, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_8975 = and(ic_valid_ff, _T_8974) @[el2_ifu_mem_ctl.scala 741:64] + node _T_8976 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_8977 = and(_T_8975, _T_8976) @[el2_ifu_mem_ctl.scala 741:89] + node _T_8978 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06c")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_8979 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_8980 = and(_T_8978, _T_8979) @[el2_ifu_mem_ctl.scala 742:58] + node _T_8981 = eq(perr_ic_index_ff, UInt<7>("h06c")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_8982 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_8983 = and(_T_8981, _T_8982) @[el2_ifu_mem_ctl.scala 742:123] + node _T_8984 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_8985 = and(_T_8983, _T_8984) @[el2_ifu_mem_ctl.scala 742:144] + node _T_8986 = or(_T_8980, _T_8985) @[el2_ifu_mem_ctl.scala 742:80] + node _T_8987 = bits(_T_8986, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_8988 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_8987 : @[Reg.scala 28:19] _T_8988 <= _T_8977 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][108] <= _T_8988 @[el2_ifu_mem_ctl.scala 740:39] - node _T_8989 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_8990 = eq(_T_8989, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_8991 = and(ic_valid_ff, _T_8990) @[el2_ifu_mem_ctl.scala 740:64] - node _T_8992 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_8993 = and(_T_8991, _T_8992) @[el2_ifu_mem_ctl.scala 740:89] - node _T_8994 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06d")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_8995 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_8996 = and(_T_8994, _T_8995) @[el2_ifu_mem_ctl.scala 741:58] - node _T_8997 = eq(perr_ic_index_ff, UInt<7>("h06d")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_8998 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_8999 = and(_T_8997, _T_8998) @[el2_ifu_mem_ctl.scala 741:123] - node _T_9000 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_9001 = and(_T_8999, _T_9000) @[el2_ifu_mem_ctl.scala 741:144] - node _T_9002 = or(_T_8996, _T_9001) @[el2_ifu_mem_ctl.scala 741:80] - node _T_9003 = bits(_T_9002, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][108] <= _T_8988 @[el2_ifu_mem_ctl.scala 741:39] + node _T_8989 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_8990 = eq(_T_8989, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_8991 = and(ic_valid_ff, _T_8990) @[el2_ifu_mem_ctl.scala 741:64] + node _T_8992 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_8993 = and(_T_8991, _T_8992) @[el2_ifu_mem_ctl.scala 741:89] + node _T_8994 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06d")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_8995 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_8996 = and(_T_8994, _T_8995) @[el2_ifu_mem_ctl.scala 742:58] + node _T_8997 = eq(perr_ic_index_ff, UInt<7>("h06d")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_8998 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_8999 = and(_T_8997, _T_8998) @[el2_ifu_mem_ctl.scala 742:123] + node _T_9000 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_9001 = and(_T_8999, _T_9000) @[el2_ifu_mem_ctl.scala 742:144] + node _T_9002 = or(_T_8996, _T_9001) @[el2_ifu_mem_ctl.scala 742:80] + node _T_9003 = bits(_T_9002, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_9004 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_9003 : @[Reg.scala 28:19] _T_9004 <= _T_8993 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][109] <= _T_9004 @[el2_ifu_mem_ctl.scala 740:39] - node _T_9005 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_9006 = eq(_T_9005, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_9007 = and(ic_valid_ff, _T_9006) @[el2_ifu_mem_ctl.scala 740:64] - node _T_9008 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_9009 = and(_T_9007, _T_9008) @[el2_ifu_mem_ctl.scala 740:89] - node _T_9010 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06e")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_9011 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_9012 = and(_T_9010, _T_9011) @[el2_ifu_mem_ctl.scala 741:58] - node _T_9013 = eq(perr_ic_index_ff, UInt<7>("h06e")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_9014 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_9015 = and(_T_9013, _T_9014) @[el2_ifu_mem_ctl.scala 741:123] - node _T_9016 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_9017 = and(_T_9015, _T_9016) @[el2_ifu_mem_ctl.scala 741:144] - node _T_9018 = or(_T_9012, _T_9017) @[el2_ifu_mem_ctl.scala 741:80] - node _T_9019 = bits(_T_9018, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][109] <= _T_9004 @[el2_ifu_mem_ctl.scala 741:39] + node _T_9005 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_9006 = eq(_T_9005, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_9007 = and(ic_valid_ff, _T_9006) @[el2_ifu_mem_ctl.scala 741:64] + node _T_9008 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_9009 = and(_T_9007, _T_9008) @[el2_ifu_mem_ctl.scala 741:89] + node _T_9010 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06e")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_9011 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_9012 = and(_T_9010, _T_9011) @[el2_ifu_mem_ctl.scala 742:58] + node _T_9013 = eq(perr_ic_index_ff, UInt<7>("h06e")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_9014 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_9015 = and(_T_9013, _T_9014) @[el2_ifu_mem_ctl.scala 742:123] + node _T_9016 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_9017 = and(_T_9015, _T_9016) @[el2_ifu_mem_ctl.scala 742:144] + node _T_9018 = or(_T_9012, _T_9017) @[el2_ifu_mem_ctl.scala 742:80] + node _T_9019 = bits(_T_9018, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_9020 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_9019 : @[Reg.scala 28:19] _T_9020 <= _T_9009 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][110] <= _T_9020 @[el2_ifu_mem_ctl.scala 740:39] - node _T_9021 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_9022 = eq(_T_9021, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_9023 = and(ic_valid_ff, _T_9022) @[el2_ifu_mem_ctl.scala 740:64] - node _T_9024 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_9025 = and(_T_9023, _T_9024) @[el2_ifu_mem_ctl.scala 740:89] - node _T_9026 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06f")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_9027 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_9028 = and(_T_9026, _T_9027) @[el2_ifu_mem_ctl.scala 741:58] - node _T_9029 = eq(perr_ic_index_ff, UInt<7>("h06f")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_9030 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_9031 = and(_T_9029, _T_9030) @[el2_ifu_mem_ctl.scala 741:123] - node _T_9032 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_9033 = and(_T_9031, _T_9032) @[el2_ifu_mem_ctl.scala 741:144] - node _T_9034 = or(_T_9028, _T_9033) @[el2_ifu_mem_ctl.scala 741:80] - node _T_9035 = bits(_T_9034, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][110] <= _T_9020 @[el2_ifu_mem_ctl.scala 741:39] + node _T_9021 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_9022 = eq(_T_9021, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_9023 = and(ic_valid_ff, _T_9022) @[el2_ifu_mem_ctl.scala 741:64] + node _T_9024 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_9025 = and(_T_9023, _T_9024) @[el2_ifu_mem_ctl.scala 741:89] + node _T_9026 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06f")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_9027 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_9028 = and(_T_9026, _T_9027) @[el2_ifu_mem_ctl.scala 742:58] + node _T_9029 = eq(perr_ic_index_ff, UInt<7>("h06f")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_9030 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_9031 = and(_T_9029, _T_9030) @[el2_ifu_mem_ctl.scala 742:123] + node _T_9032 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_9033 = and(_T_9031, _T_9032) @[el2_ifu_mem_ctl.scala 742:144] + node _T_9034 = or(_T_9028, _T_9033) @[el2_ifu_mem_ctl.scala 742:80] + node _T_9035 = bits(_T_9034, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_9036 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_9035 : @[Reg.scala 28:19] _T_9036 <= _T_9025 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][111] <= _T_9036 @[el2_ifu_mem_ctl.scala 740:39] - node _T_9037 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_9038 = eq(_T_9037, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_9039 = and(ic_valid_ff, _T_9038) @[el2_ifu_mem_ctl.scala 740:64] - node _T_9040 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_9041 = and(_T_9039, _T_9040) @[el2_ifu_mem_ctl.scala 740:89] - node _T_9042 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h070")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_9043 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_9044 = and(_T_9042, _T_9043) @[el2_ifu_mem_ctl.scala 741:58] - node _T_9045 = eq(perr_ic_index_ff, UInt<7>("h070")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_9046 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_9047 = and(_T_9045, _T_9046) @[el2_ifu_mem_ctl.scala 741:123] - node _T_9048 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_9049 = and(_T_9047, _T_9048) @[el2_ifu_mem_ctl.scala 741:144] - node _T_9050 = or(_T_9044, _T_9049) @[el2_ifu_mem_ctl.scala 741:80] - node _T_9051 = bits(_T_9050, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][111] <= _T_9036 @[el2_ifu_mem_ctl.scala 741:39] + node _T_9037 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_9038 = eq(_T_9037, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_9039 = and(ic_valid_ff, _T_9038) @[el2_ifu_mem_ctl.scala 741:64] + node _T_9040 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_9041 = and(_T_9039, _T_9040) @[el2_ifu_mem_ctl.scala 741:89] + node _T_9042 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h070")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_9043 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_9044 = and(_T_9042, _T_9043) @[el2_ifu_mem_ctl.scala 742:58] + node _T_9045 = eq(perr_ic_index_ff, UInt<7>("h070")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_9046 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_9047 = and(_T_9045, _T_9046) @[el2_ifu_mem_ctl.scala 742:123] + node _T_9048 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_9049 = and(_T_9047, _T_9048) @[el2_ifu_mem_ctl.scala 742:144] + node _T_9050 = or(_T_9044, _T_9049) @[el2_ifu_mem_ctl.scala 742:80] + node _T_9051 = bits(_T_9050, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_9052 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_9051 : @[Reg.scala 28:19] _T_9052 <= _T_9041 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][112] <= _T_9052 @[el2_ifu_mem_ctl.scala 740:39] - node _T_9053 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_9054 = eq(_T_9053, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_9055 = and(ic_valid_ff, _T_9054) @[el2_ifu_mem_ctl.scala 740:64] - node _T_9056 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_9057 = and(_T_9055, _T_9056) @[el2_ifu_mem_ctl.scala 740:89] - node _T_9058 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h071")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_9059 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_9060 = and(_T_9058, _T_9059) @[el2_ifu_mem_ctl.scala 741:58] - node _T_9061 = eq(perr_ic_index_ff, UInt<7>("h071")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_9062 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_9063 = and(_T_9061, _T_9062) @[el2_ifu_mem_ctl.scala 741:123] - node _T_9064 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_9065 = and(_T_9063, _T_9064) @[el2_ifu_mem_ctl.scala 741:144] - node _T_9066 = or(_T_9060, _T_9065) @[el2_ifu_mem_ctl.scala 741:80] - node _T_9067 = bits(_T_9066, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][112] <= _T_9052 @[el2_ifu_mem_ctl.scala 741:39] + node _T_9053 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_9054 = eq(_T_9053, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_9055 = and(ic_valid_ff, _T_9054) @[el2_ifu_mem_ctl.scala 741:64] + node _T_9056 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_9057 = and(_T_9055, _T_9056) @[el2_ifu_mem_ctl.scala 741:89] + node _T_9058 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h071")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_9059 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_9060 = and(_T_9058, _T_9059) @[el2_ifu_mem_ctl.scala 742:58] + node _T_9061 = eq(perr_ic_index_ff, UInt<7>("h071")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_9062 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_9063 = and(_T_9061, _T_9062) @[el2_ifu_mem_ctl.scala 742:123] + node _T_9064 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_9065 = and(_T_9063, _T_9064) @[el2_ifu_mem_ctl.scala 742:144] + node _T_9066 = or(_T_9060, _T_9065) @[el2_ifu_mem_ctl.scala 742:80] + node _T_9067 = bits(_T_9066, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_9068 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_9067 : @[Reg.scala 28:19] _T_9068 <= _T_9057 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][113] <= _T_9068 @[el2_ifu_mem_ctl.scala 740:39] - node _T_9069 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_9070 = eq(_T_9069, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_9071 = and(ic_valid_ff, _T_9070) @[el2_ifu_mem_ctl.scala 740:64] - node _T_9072 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_9073 = and(_T_9071, _T_9072) @[el2_ifu_mem_ctl.scala 740:89] - node _T_9074 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h072")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_9075 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_9076 = and(_T_9074, _T_9075) @[el2_ifu_mem_ctl.scala 741:58] - node _T_9077 = eq(perr_ic_index_ff, UInt<7>("h072")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_9078 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_9079 = and(_T_9077, _T_9078) @[el2_ifu_mem_ctl.scala 741:123] - node _T_9080 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_9081 = and(_T_9079, _T_9080) @[el2_ifu_mem_ctl.scala 741:144] - node _T_9082 = or(_T_9076, _T_9081) @[el2_ifu_mem_ctl.scala 741:80] - node _T_9083 = bits(_T_9082, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][113] <= _T_9068 @[el2_ifu_mem_ctl.scala 741:39] + node _T_9069 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_9070 = eq(_T_9069, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_9071 = and(ic_valid_ff, _T_9070) @[el2_ifu_mem_ctl.scala 741:64] + node _T_9072 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_9073 = and(_T_9071, _T_9072) @[el2_ifu_mem_ctl.scala 741:89] + node _T_9074 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h072")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_9075 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_9076 = and(_T_9074, _T_9075) @[el2_ifu_mem_ctl.scala 742:58] + node _T_9077 = eq(perr_ic_index_ff, UInt<7>("h072")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_9078 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_9079 = and(_T_9077, _T_9078) @[el2_ifu_mem_ctl.scala 742:123] + node _T_9080 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_9081 = and(_T_9079, _T_9080) @[el2_ifu_mem_ctl.scala 742:144] + node _T_9082 = or(_T_9076, _T_9081) @[el2_ifu_mem_ctl.scala 742:80] + node _T_9083 = bits(_T_9082, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_9084 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_9083 : @[Reg.scala 28:19] _T_9084 <= _T_9073 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][114] <= _T_9084 @[el2_ifu_mem_ctl.scala 740:39] - node _T_9085 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_9086 = eq(_T_9085, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_9087 = and(ic_valid_ff, _T_9086) @[el2_ifu_mem_ctl.scala 740:64] - node _T_9088 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_9089 = and(_T_9087, _T_9088) @[el2_ifu_mem_ctl.scala 740:89] - node _T_9090 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h073")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_9091 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_9092 = and(_T_9090, _T_9091) @[el2_ifu_mem_ctl.scala 741:58] - node _T_9093 = eq(perr_ic_index_ff, UInt<7>("h073")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_9094 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_9095 = and(_T_9093, _T_9094) @[el2_ifu_mem_ctl.scala 741:123] - node _T_9096 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_9097 = and(_T_9095, _T_9096) @[el2_ifu_mem_ctl.scala 741:144] - node _T_9098 = or(_T_9092, _T_9097) @[el2_ifu_mem_ctl.scala 741:80] - node _T_9099 = bits(_T_9098, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][114] <= _T_9084 @[el2_ifu_mem_ctl.scala 741:39] + node _T_9085 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_9086 = eq(_T_9085, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_9087 = and(ic_valid_ff, _T_9086) @[el2_ifu_mem_ctl.scala 741:64] + node _T_9088 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_9089 = and(_T_9087, _T_9088) @[el2_ifu_mem_ctl.scala 741:89] + node _T_9090 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h073")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_9091 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_9092 = and(_T_9090, _T_9091) @[el2_ifu_mem_ctl.scala 742:58] + node _T_9093 = eq(perr_ic_index_ff, UInt<7>("h073")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_9094 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_9095 = and(_T_9093, _T_9094) @[el2_ifu_mem_ctl.scala 742:123] + node _T_9096 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_9097 = and(_T_9095, _T_9096) @[el2_ifu_mem_ctl.scala 742:144] + node _T_9098 = or(_T_9092, _T_9097) @[el2_ifu_mem_ctl.scala 742:80] + node _T_9099 = bits(_T_9098, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_9100 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_9099 : @[Reg.scala 28:19] _T_9100 <= _T_9089 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][115] <= _T_9100 @[el2_ifu_mem_ctl.scala 740:39] - node _T_9101 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_9102 = eq(_T_9101, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_9103 = and(ic_valid_ff, _T_9102) @[el2_ifu_mem_ctl.scala 740:64] - node _T_9104 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_9105 = and(_T_9103, _T_9104) @[el2_ifu_mem_ctl.scala 740:89] - node _T_9106 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h074")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_9107 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_9108 = and(_T_9106, _T_9107) @[el2_ifu_mem_ctl.scala 741:58] - node _T_9109 = eq(perr_ic_index_ff, UInt<7>("h074")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_9110 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_9111 = and(_T_9109, _T_9110) @[el2_ifu_mem_ctl.scala 741:123] - node _T_9112 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_9113 = and(_T_9111, _T_9112) @[el2_ifu_mem_ctl.scala 741:144] - node _T_9114 = or(_T_9108, _T_9113) @[el2_ifu_mem_ctl.scala 741:80] - node _T_9115 = bits(_T_9114, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][115] <= _T_9100 @[el2_ifu_mem_ctl.scala 741:39] + node _T_9101 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_9102 = eq(_T_9101, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_9103 = and(ic_valid_ff, _T_9102) @[el2_ifu_mem_ctl.scala 741:64] + node _T_9104 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_9105 = and(_T_9103, _T_9104) @[el2_ifu_mem_ctl.scala 741:89] + node _T_9106 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h074")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_9107 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_9108 = and(_T_9106, _T_9107) @[el2_ifu_mem_ctl.scala 742:58] + node _T_9109 = eq(perr_ic_index_ff, UInt<7>("h074")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_9110 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_9111 = and(_T_9109, _T_9110) @[el2_ifu_mem_ctl.scala 742:123] + node _T_9112 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_9113 = and(_T_9111, _T_9112) @[el2_ifu_mem_ctl.scala 742:144] + node _T_9114 = or(_T_9108, _T_9113) @[el2_ifu_mem_ctl.scala 742:80] + node _T_9115 = bits(_T_9114, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_9116 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_9115 : @[Reg.scala 28:19] _T_9116 <= _T_9105 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][116] <= _T_9116 @[el2_ifu_mem_ctl.scala 740:39] - node _T_9117 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_9118 = eq(_T_9117, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_9119 = and(ic_valid_ff, _T_9118) @[el2_ifu_mem_ctl.scala 740:64] - node _T_9120 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_9121 = and(_T_9119, _T_9120) @[el2_ifu_mem_ctl.scala 740:89] - node _T_9122 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h075")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_9123 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_9124 = and(_T_9122, _T_9123) @[el2_ifu_mem_ctl.scala 741:58] - node _T_9125 = eq(perr_ic_index_ff, UInt<7>("h075")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_9126 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_9127 = and(_T_9125, _T_9126) @[el2_ifu_mem_ctl.scala 741:123] - node _T_9128 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_9129 = and(_T_9127, _T_9128) @[el2_ifu_mem_ctl.scala 741:144] - node _T_9130 = or(_T_9124, _T_9129) @[el2_ifu_mem_ctl.scala 741:80] - node _T_9131 = bits(_T_9130, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][116] <= _T_9116 @[el2_ifu_mem_ctl.scala 741:39] + node _T_9117 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_9118 = eq(_T_9117, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_9119 = and(ic_valid_ff, _T_9118) @[el2_ifu_mem_ctl.scala 741:64] + node _T_9120 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_9121 = and(_T_9119, _T_9120) @[el2_ifu_mem_ctl.scala 741:89] + node _T_9122 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h075")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_9123 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_9124 = and(_T_9122, _T_9123) @[el2_ifu_mem_ctl.scala 742:58] + node _T_9125 = eq(perr_ic_index_ff, UInt<7>("h075")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_9126 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_9127 = and(_T_9125, _T_9126) @[el2_ifu_mem_ctl.scala 742:123] + node _T_9128 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_9129 = and(_T_9127, _T_9128) @[el2_ifu_mem_ctl.scala 742:144] + node _T_9130 = or(_T_9124, _T_9129) @[el2_ifu_mem_ctl.scala 742:80] + node _T_9131 = bits(_T_9130, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_9132 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_9131 : @[Reg.scala 28:19] _T_9132 <= _T_9121 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][117] <= _T_9132 @[el2_ifu_mem_ctl.scala 740:39] - node _T_9133 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_9134 = eq(_T_9133, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_9135 = and(ic_valid_ff, _T_9134) @[el2_ifu_mem_ctl.scala 740:64] - node _T_9136 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_9137 = and(_T_9135, _T_9136) @[el2_ifu_mem_ctl.scala 740:89] - node _T_9138 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h076")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_9139 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_9140 = and(_T_9138, _T_9139) @[el2_ifu_mem_ctl.scala 741:58] - node _T_9141 = eq(perr_ic_index_ff, UInt<7>("h076")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_9142 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_9143 = and(_T_9141, _T_9142) @[el2_ifu_mem_ctl.scala 741:123] - node _T_9144 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_9145 = and(_T_9143, _T_9144) @[el2_ifu_mem_ctl.scala 741:144] - node _T_9146 = or(_T_9140, _T_9145) @[el2_ifu_mem_ctl.scala 741:80] - node _T_9147 = bits(_T_9146, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][117] <= _T_9132 @[el2_ifu_mem_ctl.scala 741:39] + node _T_9133 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_9134 = eq(_T_9133, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_9135 = and(ic_valid_ff, _T_9134) @[el2_ifu_mem_ctl.scala 741:64] + node _T_9136 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_9137 = and(_T_9135, _T_9136) @[el2_ifu_mem_ctl.scala 741:89] + node _T_9138 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h076")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_9139 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_9140 = and(_T_9138, _T_9139) @[el2_ifu_mem_ctl.scala 742:58] + node _T_9141 = eq(perr_ic_index_ff, UInt<7>("h076")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_9142 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_9143 = and(_T_9141, _T_9142) @[el2_ifu_mem_ctl.scala 742:123] + node _T_9144 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_9145 = and(_T_9143, _T_9144) @[el2_ifu_mem_ctl.scala 742:144] + node _T_9146 = or(_T_9140, _T_9145) @[el2_ifu_mem_ctl.scala 742:80] + node _T_9147 = bits(_T_9146, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_9148 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_9147 : @[Reg.scala 28:19] _T_9148 <= _T_9137 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][118] <= _T_9148 @[el2_ifu_mem_ctl.scala 740:39] - node _T_9149 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_9150 = eq(_T_9149, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_9151 = and(ic_valid_ff, _T_9150) @[el2_ifu_mem_ctl.scala 740:64] - node _T_9152 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_9153 = and(_T_9151, _T_9152) @[el2_ifu_mem_ctl.scala 740:89] - node _T_9154 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h077")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_9155 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_9156 = and(_T_9154, _T_9155) @[el2_ifu_mem_ctl.scala 741:58] - node _T_9157 = eq(perr_ic_index_ff, UInt<7>("h077")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_9158 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_9159 = and(_T_9157, _T_9158) @[el2_ifu_mem_ctl.scala 741:123] - node _T_9160 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_9161 = and(_T_9159, _T_9160) @[el2_ifu_mem_ctl.scala 741:144] - node _T_9162 = or(_T_9156, _T_9161) @[el2_ifu_mem_ctl.scala 741:80] - node _T_9163 = bits(_T_9162, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][118] <= _T_9148 @[el2_ifu_mem_ctl.scala 741:39] + node _T_9149 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_9150 = eq(_T_9149, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_9151 = and(ic_valid_ff, _T_9150) @[el2_ifu_mem_ctl.scala 741:64] + node _T_9152 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_9153 = and(_T_9151, _T_9152) @[el2_ifu_mem_ctl.scala 741:89] + node _T_9154 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h077")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_9155 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_9156 = and(_T_9154, _T_9155) @[el2_ifu_mem_ctl.scala 742:58] + node _T_9157 = eq(perr_ic_index_ff, UInt<7>("h077")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_9158 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_9159 = and(_T_9157, _T_9158) @[el2_ifu_mem_ctl.scala 742:123] + node _T_9160 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_9161 = and(_T_9159, _T_9160) @[el2_ifu_mem_ctl.scala 742:144] + node _T_9162 = or(_T_9156, _T_9161) @[el2_ifu_mem_ctl.scala 742:80] + node _T_9163 = bits(_T_9162, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_9164 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_9163 : @[Reg.scala 28:19] _T_9164 <= _T_9153 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][119] <= _T_9164 @[el2_ifu_mem_ctl.scala 740:39] - node _T_9165 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_9166 = eq(_T_9165, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_9167 = and(ic_valid_ff, _T_9166) @[el2_ifu_mem_ctl.scala 740:64] - node _T_9168 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_9169 = and(_T_9167, _T_9168) @[el2_ifu_mem_ctl.scala 740:89] - node _T_9170 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h078")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_9171 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_9172 = and(_T_9170, _T_9171) @[el2_ifu_mem_ctl.scala 741:58] - node _T_9173 = eq(perr_ic_index_ff, UInt<7>("h078")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_9174 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_9175 = and(_T_9173, _T_9174) @[el2_ifu_mem_ctl.scala 741:123] - node _T_9176 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_9177 = and(_T_9175, _T_9176) @[el2_ifu_mem_ctl.scala 741:144] - node _T_9178 = or(_T_9172, _T_9177) @[el2_ifu_mem_ctl.scala 741:80] - node _T_9179 = bits(_T_9178, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][119] <= _T_9164 @[el2_ifu_mem_ctl.scala 741:39] + node _T_9165 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_9166 = eq(_T_9165, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_9167 = and(ic_valid_ff, _T_9166) @[el2_ifu_mem_ctl.scala 741:64] + node _T_9168 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_9169 = and(_T_9167, _T_9168) @[el2_ifu_mem_ctl.scala 741:89] + node _T_9170 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h078")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_9171 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_9172 = and(_T_9170, _T_9171) @[el2_ifu_mem_ctl.scala 742:58] + node _T_9173 = eq(perr_ic_index_ff, UInt<7>("h078")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_9174 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_9175 = and(_T_9173, _T_9174) @[el2_ifu_mem_ctl.scala 742:123] + node _T_9176 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_9177 = and(_T_9175, _T_9176) @[el2_ifu_mem_ctl.scala 742:144] + node _T_9178 = or(_T_9172, _T_9177) @[el2_ifu_mem_ctl.scala 742:80] + node _T_9179 = bits(_T_9178, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_9180 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_9179 : @[Reg.scala 28:19] _T_9180 <= _T_9169 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][120] <= _T_9180 @[el2_ifu_mem_ctl.scala 740:39] - node _T_9181 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_9182 = eq(_T_9181, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_9183 = and(ic_valid_ff, _T_9182) @[el2_ifu_mem_ctl.scala 740:64] - node _T_9184 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_9185 = and(_T_9183, _T_9184) @[el2_ifu_mem_ctl.scala 740:89] - node _T_9186 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h079")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_9187 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_9188 = and(_T_9186, _T_9187) @[el2_ifu_mem_ctl.scala 741:58] - node _T_9189 = eq(perr_ic_index_ff, UInt<7>("h079")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_9190 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_9191 = and(_T_9189, _T_9190) @[el2_ifu_mem_ctl.scala 741:123] - node _T_9192 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_9193 = and(_T_9191, _T_9192) @[el2_ifu_mem_ctl.scala 741:144] - node _T_9194 = or(_T_9188, _T_9193) @[el2_ifu_mem_ctl.scala 741:80] - node _T_9195 = bits(_T_9194, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][120] <= _T_9180 @[el2_ifu_mem_ctl.scala 741:39] + node _T_9181 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_9182 = eq(_T_9181, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_9183 = and(ic_valid_ff, _T_9182) @[el2_ifu_mem_ctl.scala 741:64] + node _T_9184 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_9185 = and(_T_9183, _T_9184) @[el2_ifu_mem_ctl.scala 741:89] + node _T_9186 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h079")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_9187 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_9188 = and(_T_9186, _T_9187) @[el2_ifu_mem_ctl.scala 742:58] + node _T_9189 = eq(perr_ic_index_ff, UInt<7>("h079")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_9190 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_9191 = and(_T_9189, _T_9190) @[el2_ifu_mem_ctl.scala 742:123] + node _T_9192 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_9193 = and(_T_9191, _T_9192) @[el2_ifu_mem_ctl.scala 742:144] + node _T_9194 = or(_T_9188, _T_9193) @[el2_ifu_mem_ctl.scala 742:80] + node _T_9195 = bits(_T_9194, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_9196 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_9195 : @[Reg.scala 28:19] _T_9196 <= _T_9185 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][121] <= _T_9196 @[el2_ifu_mem_ctl.scala 740:39] - node _T_9197 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_9198 = eq(_T_9197, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_9199 = and(ic_valid_ff, _T_9198) @[el2_ifu_mem_ctl.scala 740:64] - node _T_9200 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_9201 = and(_T_9199, _T_9200) @[el2_ifu_mem_ctl.scala 740:89] - node _T_9202 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07a")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_9203 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_9204 = and(_T_9202, _T_9203) @[el2_ifu_mem_ctl.scala 741:58] - node _T_9205 = eq(perr_ic_index_ff, UInt<7>("h07a")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_9206 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_9207 = and(_T_9205, _T_9206) @[el2_ifu_mem_ctl.scala 741:123] - node _T_9208 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_9209 = and(_T_9207, _T_9208) @[el2_ifu_mem_ctl.scala 741:144] - node _T_9210 = or(_T_9204, _T_9209) @[el2_ifu_mem_ctl.scala 741:80] - node _T_9211 = bits(_T_9210, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][121] <= _T_9196 @[el2_ifu_mem_ctl.scala 741:39] + node _T_9197 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_9198 = eq(_T_9197, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_9199 = and(ic_valid_ff, _T_9198) @[el2_ifu_mem_ctl.scala 741:64] + node _T_9200 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_9201 = and(_T_9199, _T_9200) @[el2_ifu_mem_ctl.scala 741:89] + node _T_9202 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07a")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_9203 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_9204 = and(_T_9202, _T_9203) @[el2_ifu_mem_ctl.scala 742:58] + node _T_9205 = eq(perr_ic_index_ff, UInt<7>("h07a")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_9206 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_9207 = and(_T_9205, _T_9206) @[el2_ifu_mem_ctl.scala 742:123] + node _T_9208 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_9209 = and(_T_9207, _T_9208) @[el2_ifu_mem_ctl.scala 742:144] + node _T_9210 = or(_T_9204, _T_9209) @[el2_ifu_mem_ctl.scala 742:80] + node _T_9211 = bits(_T_9210, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_9212 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_9211 : @[Reg.scala 28:19] _T_9212 <= _T_9201 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][122] <= _T_9212 @[el2_ifu_mem_ctl.scala 740:39] - node _T_9213 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_9214 = eq(_T_9213, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_9215 = and(ic_valid_ff, _T_9214) @[el2_ifu_mem_ctl.scala 740:64] - node _T_9216 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_9217 = and(_T_9215, _T_9216) @[el2_ifu_mem_ctl.scala 740:89] - node _T_9218 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07b")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_9219 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_9220 = and(_T_9218, _T_9219) @[el2_ifu_mem_ctl.scala 741:58] - node _T_9221 = eq(perr_ic_index_ff, UInt<7>("h07b")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_9222 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_9223 = and(_T_9221, _T_9222) @[el2_ifu_mem_ctl.scala 741:123] - node _T_9224 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_9225 = and(_T_9223, _T_9224) @[el2_ifu_mem_ctl.scala 741:144] - node _T_9226 = or(_T_9220, _T_9225) @[el2_ifu_mem_ctl.scala 741:80] - node _T_9227 = bits(_T_9226, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][122] <= _T_9212 @[el2_ifu_mem_ctl.scala 741:39] + node _T_9213 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_9214 = eq(_T_9213, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_9215 = and(ic_valid_ff, _T_9214) @[el2_ifu_mem_ctl.scala 741:64] + node _T_9216 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_9217 = and(_T_9215, _T_9216) @[el2_ifu_mem_ctl.scala 741:89] + node _T_9218 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07b")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_9219 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_9220 = and(_T_9218, _T_9219) @[el2_ifu_mem_ctl.scala 742:58] + node _T_9221 = eq(perr_ic_index_ff, UInt<7>("h07b")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_9222 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_9223 = and(_T_9221, _T_9222) @[el2_ifu_mem_ctl.scala 742:123] + node _T_9224 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_9225 = and(_T_9223, _T_9224) @[el2_ifu_mem_ctl.scala 742:144] + node _T_9226 = or(_T_9220, _T_9225) @[el2_ifu_mem_ctl.scala 742:80] + node _T_9227 = bits(_T_9226, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_9228 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_9227 : @[Reg.scala 28:19] _T_9228 <= _T_9217 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][123] <= _T_9228 @[el2_ifu_mem_ctl.scala 740:39] - node _T_9229 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_9230 = eq(_T_9229, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_9231 = and(ic_valid_ff, _T_9230) @[el2_ifu_mem_ctl.scala 740:64] - node _T_9232 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_9233 = and(_T_9231, _T_9232) @[el2_ifu_mem_ctl.scala 740:89] - node _T_9234 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07c")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_9235 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_9236 = and(_T_9234, _T_9235) @[el2_ifu_mem_ctl.scala 741:58] - node _T_9237 = eq(perr_ic_index_ff, UInt<7>("h07c")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_9238 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_9239 = and(_T_9237, _T_9238) @[el2_ifu_mem_ctl.scala 741:123] - node _T_9240 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_9241 = and(_T_9239, _T_9240) @[el2_ifu_mem_ctl.scala 741:144] - node _T_9242 = or(_T_9236, _T_9241) @[el2_ifu_mem_ctl.scala 741:80] - node _T_9243 = bits(_T_9242, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][123] <= _T_9228 @[el2_ifu_mem_ctl.scala 741:39] + node _T_9229 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_9230 = eq(_T_9229, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_9231 = and(ic_valid_ff, _T_9230) @[el2_ifu_mem_ctl.scala 741:64] + node _T_9232 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_9233 = and(_T_9231, _T_9232) @[el2_ifu_mem_ctl.scala 741:89] + node _T_9234 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07c")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_9235 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_9236 = and(_T_9234, _T_9235) @[el2_ifu_mem_ctl.scala 742:58] + node _T_9237 = eq(perr_ic_index_ff, UInt<7>("h07c")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_9238 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_9239 = and(_T_9237, _T_9238) @[el2_ifu_mem_ctl.scala 742:123] + node _T_9240 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_9241 = and(_T_9239, _T_9240) @[el2_ifu_mem_ctl.scala 742:144] + node _T_9242 = or(_T_9236, _T_9241) @[el2_ifu_mem_ctl.scala 742:80] + node _T_9243 = bits(_T_9242, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_9244 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_9243 : @[Reg.scala 28:19] _T_9244 <= _T_9233 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][124] <= _T_9244 @[el2_ifu_mem_ctl.scala 740:39] - node _T_9245 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_9246 = eq(_T_9245, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_9247 = and(ic_valid_ff, _T_9246) @[el2_ifu_mem_ctl.scala 740:64] - node _T_9248 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_9249 = and(_T_9247, _T_9248) @[el2_ifu_mem_ctl.scala 740:89] - node _T_9250 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07d")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_9251 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_9252 = and(_T_9250, _T_9251) @[el2_ifu_mem_ctl.scala 741:58] - node _T_9253 = eq(perr_ic_index_ff, UInt<7>("h07d")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_9254 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_9255 = and(_T_9253, _T_9254) @[el2_ifu_mem_ctl.scala 741:123] - node _T_9256 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_9257 = and(_T_9255, _T_9256) @[el2_ifu_mem_ctl.scala 741:144] - node _T_9258 = or(_T_9252, _T_9257) @[el2_ifu_mem_ctl.scala 741:80] - node _T_9259 = bits(_T_9258, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][124] <= _T_9244 @[el2_ifu_mem_ctl.scala 741:39] + node _T_9245 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_9246 = eq(_T_9245, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_9247 = and(ic_valid_ff, _T_9246) @[el2_ifu_mem_ctl.scala 741:64] + node _T_9248 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_9249 = and(_T_9247, _T_9248) @[el2_ifu_mem_ctl.scala 741:89] + node _T_9250 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07d")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_9251 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_9252 = and(_T_9250, _T_9251) @[el2_ifu_mem_ctl.scala 742:58] + node _T_9253 = eq(perr_ic_index_ff, UInt<7>("h07d")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_9254 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_9255 = and(_T_9253, _T_9254) @[el2_ifu_mem_ctl.scala 742:123] + node _T_9256 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_9257 = and(_T_9255, _T_9256) @[el2_ifu_mem_ctl.scala 742:144] + node _T_9258 = or(_T_9252, _T_9257) @[el2_ifu_mem_ctl.scala 742:80] + node _T_9259 = bits(_T_9258, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_9260 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_9259 : @[Reg.scala 28:19] _T_9260 <= _T_9249 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][125] <= _T_9260 @[el2_ifu_mem_ctl.scala 740:39] - node _T_9261 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_9262 = eq(_T_9261, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_9263 = and(ic_valid_ff, _T_9262) @[el2_ifu_mem_ctl.scala 740:64] - node _T_9264 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_9265 = and(_T_9263, _T_9264) @[el2_ifu_mem_ctl.scala 740:89] - node _T_9266 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07e")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_9267 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_9268 = and(_T_9266, _T_9267) @[el2_ifu_mem_ctl.scala 741:58] - node _T_9269 = eq(perr_ic_index_ff, UInt<7>("h07e")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_9270 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_9271 = and(_T_9269, _T_9270) @[el2_ifu_mem_ctl.scala 741:123] - node _T_9272 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_9273 = and(_T_9271, _T_9272) @[el2_ifu_mem_ctl.scala 741:144] - node _T_9274 = or(_T_9268, _T_9273) @[el2_ifu_mem_ctl.scala 741:80] - node _T_9275 = bits(_T_9274, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][125] <= _T_9260 @[el2_ifu_mem_ctl.scala 741:39] + node _T_9261 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_9262 = eq(_T_9261, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_9263 = and(ic_valid_ff, _T_9262) @[el2_ifu_mem_ctl.scala 741:64] + node _T_9264 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_9265 = and(_T_9263, _T_9264) @[el2_ifu_mem_ctl.scala 741:89] + node _T_9266 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07e")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_9267 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_9268 = and(_T_9266, _T_9267) @[el2_ifu_mem_ctl.scala 742:58] + node _T_9269 = eq(perr_ic_index_ff, UInt<7>("h07e")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_9270 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_9271 = and(_T_9269, _T_9270) @[el2_ifu_mem_ctl.scala 742:123] + node _T_9272 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_9273 = and(_T_9271, _T_9272) @[el2_ifu_mem_ctl.scala 742:144] + node _T_9274 = or(_T_9268, _T_9273) @[el2_ifu_mem_ctl.scala 742:80] + node _T_9275 = bits(_T_9274, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_9276 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_9275 : @[Reg.scala 28:19] _T_9276 <= _T_9265 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][126] <= _T_9276 @[el2_ifu_mem_ctl.scala 740:39] - node _T_9277 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 740:82] - node _T_9278 = eq(_T_9277, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:66] - node _T_9279 = and(ic_valid_ff, _T_9278) @[el2_ifu_mem_ctl.scala 740:64] - node _T_9280 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 740:91] - node _T_9281 = and(_T_9279, _T_9280) @[el2_ifu_mem_ctl.scala 740:89] - node _T_9282 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07f")) @[el2_ifu_mem_ctl.scala 741:36] - node _T_9283 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:75] - node _T_9284 = and(_T_9282, _T_9283) @[el2_ifu_mem_ctl.scala 741:58] - node _T_9285 = eq(perr_ic_index_ff, UInt<7>("h07f")) @[el2_ifu_mem_ctl.scala 741:101] - node _T_9286 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 741:140] - node _T_9287 = and(_T_9285, _T_9286) @[el2_ifu_mem_ctl.scala 741:123] - node _T_9288 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 741:163] - node _T_9289 = and(_T_9287, _T_9288) @[el2_ifu_mem_ctl.scala 741:144] - node _T_9290 = or(_T_9284, _T_9289) @[el2_ifu_mem_ctl.scala 741:80] - node _T_9291 = bits(_T_9290, 0, 0) @[el2_ifu_mem_ctl.scala 741:168] + ic_tag_valid_out[1][126] <= _T_9276 @[el2_ifu_mem_ctl.scala 741:39] + node _T_9277 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 741:82] + node _T_9278 = eq(_T_9277, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:66] + node _T_9279 = and(ic_valid_ff, _T_9278) @[el2_ifu_mem_ctl.scala 741:64] + node _T_9280 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 741:91] + node _T_9281 = and(_T_9279, _T_9280) @[el2_ifu_mem_ctl.scala 741:89] + node _T_9282 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07f")) @[el2_ifu_mem_ctl.scala 742:36] + node _T_9283 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:75] + node _T_9284 = and(_T_9282, _T_9283) @[el2_ifu_mem_ctl.scala 742:58] + node _T_9285 = eq(perr_ic_index_ff, UInt<7>("h07f")) @[el2_ifu_mem_ctl.scala 742:101] + node _T_9286 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:140] + node _T_9287 = and(_T_9285, _T_9286) @[el2_ifu_mem_ctl.scala 742:123] + node _T_9288 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 742:163] + node _T_9289 = and(_T_9287, _T_9288) @[el2_ifu_mem_ctl.scala 742:144] + node _T_9290 = or(_T_9284, _T_9289) @[el2_ifu_mem_ctl.scala 742:80] + node _T_9291 = bits(_T_9290, 0, 0) @[el2_ifu_mem_ctl.scala 742:168] reg _T_9292 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_9291 : @[Reg.scala 28:19] _T_9292 <= _T_9281 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_tag_valid_out[1][127] <= _T_9292 @[el2_ifu_mem_ctl.scala 740:39] - node _T_9293 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9294 = mux(_T_9293, UInt<1>("h00"), ic_tag_valid_out[0][0]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9295 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9296 = mux(_T_9295, UInt<1>("h00"), ic_tag_valid_out[0][1]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9297 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9298 = mux(_T_9297, UInt<1>("h00"), ic_tag_valid_out[0][2]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9299 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9300 = mux(_T_9299, UInt<1>("h00"), ic_tag_valid_out[0][3]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9301 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9302 = mux(_T_9301, UInt<1>("h00"), ic_tag_valid_out[0][4]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9303 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9304 = mux(_T_9303, UInt<1>("h00"), ic_tag_valid_out[0][5]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9305 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9306 = mux(_T_9305, UInt<1>("h00"), ic_tag_valid_out[0][6]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9307 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9308 = mux(_T_9307, UInt<1>("h00"), ic_tag_valid_out[0][7]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9309 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9310 = mux(_T_9309, UInt<1>("h00"), ic_tag_valid_out[0][8]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9311 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9312 = mux(_T_9311, UInt<1>("h00"), ic_tag_valid_out[0][9]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9313 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9314 = mux(_T_9313, UInt<1>("h00"), ic_tag_valid_out[0][10]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9315 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9316 = mux(_T_9315, UInt<1>("h00"), ic_tag_valid_out[0][11]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9317 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9318 = mux(_T_9317, UInt<1>("h00"), ic_tag_valid_out[0][12]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9319 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9320 = mux(_T_9319, UInt<1>("h00"), ic_tag_valid_out[0][13]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9321 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9322 = mux(_T_9321, UInt<1>("h00"), ic_tag_valid_out[0][14]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9323 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9324 = mux(_T_9323, UInt<1>("h00"), ic_tag_valid_out[0][15]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9325 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h010")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9326 = mux(_T_9325, UInt<1>("h00"), ic_tag_valid_out[0][16]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9327 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h011")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9328 = mux(_T_9327, UInt<1>("h00"), ic_tag_valid_out[0][17]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9329 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h012")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9330 = mux(_T_9329, UInt<1>("h00"), ic_tag_valid_out[0][18]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9331 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h013")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9332 = mux(_T_9331, UInt<1>("h00"), ic_tag_valid_out[0][19]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9333 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h014")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9334 = mux(_T_9333, UInt<1>("h00"), ic_tag_valid_out[0][20]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9335 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h015")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9336 = mux(_T_9335, UInt<1>("h00"), ic_tag_valid_out[0][21]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9337 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h016")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9338 = mux(_T_9337, UInt<1>("h00"), ic_tag_valid_out[0][22]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9339 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h017")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9340 = mux(_T_9339, UInt<1>("h00"), ic_tag_valid_out[0][23]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9341 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h018")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9342 = mux(_T_9341, UInt<1>("h00"), ic_tag_valid_out[0][24]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9343 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h019")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9344 = mux(_T_9343, UInt<1>("h00"), ic_tag_valid_out[0][25]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9345 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01a")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9346 = mux(_T_9345, UInt<1>("h00"), ic_tag_valid_out[0][26]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9347 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01b")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9348 = mux(_T_9347, UInt<1>("h00"), ic_tag_valid_out[0][27]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9349 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01c")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9350 = mux(_T_9349, UInt<1>("h00"), ic_tag_valid_out[0][28]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9351 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01d")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9352 = mux(_T_9351, UInt<1>("h00"), ic_tag_valid_out[0][29]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9353 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01e")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9354 = mux(_T_9353, UInt<1>("h00"), ic_tag_valid_out[0][30]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9355 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01f")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9356 = mux(_T_9355, UInt<1>("h00"), ic_tag_valid_out[0][31]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9357 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h020")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9358 = mux(_T_9357, UInt<1>("h00"), ic_tag_valid_out[0][32]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9359 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h021")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9360 = mux(_T_9359, UInt<1>("h00"), ic_tag_valid_out[0][33]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9361 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h022")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9362 = mux(_T_9361, UInt<1>("h00"), ic_tag_valid_out[0][34]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9363 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h023")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9364 = mux(_T_9363, UInt<1>("h00"), ic_tag_valid_out[0][35]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9365 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h024")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9366 = mux(_T_9365, UInt<1>("h00"), ic_tag_valid_out[0][36]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9367 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h025")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9368 = mux(_T_9367, UInt<1>("h00"), ic_tag_valid_out[0][37]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9369 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h026")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9370 = mux(_T_9369, UInt<1>("h00"), ic_tag_valid_out[0][38]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9371 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h027")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9372 = mux(_T_9371, UInt<1>("h00"), ic_tag_valid_out[0][39]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9373 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h028")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9374 = mux(_T_9373, UInt<1>("h00"), ic_tag_valid_out[0][40]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9375 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h029")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9376 = mux(_T_9375, UInt<1>("h00"), ic_tag_valid_out[0][41]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9377 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02a")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9378 = mux(_T_9377, UInt<1>("h00"), ic_tag_valid_out[0][42]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9379 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02b")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9380 = mux(_T_9379, UInt<1>("h00"), ic_tag_valid_out[0][43]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9381 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02c")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9382 = mux(_T_9381, UInt<1>("h00"), ic_tag_valid_out[0][44]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9383 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02d")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9384 = mux(_T_9383, UInt<1>("h00"), ic_tag_valid_out[0][45]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9385 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02e")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9386 = mux(_T_9385, UInt<1>("h00"), ic_tag_valid_out[0][46]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9387 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02f")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9388 = mux(_T_9387, UInt<1>("h00"), ic_tag_valid_out[0][47]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9389 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h030")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9390 = mux(_T_9389, UInt<1>("h00"), ic_tag_valid_out[0][48]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9391 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h031")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9392 = mux(_T_9391, UInt<1>("h00"), ic_tag_valid_out[0][49]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9393 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h032")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9394 = mux(_T_9393, UInt<1>("h00"), ic_tag_valid_out[0][50]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9395 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h033")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9396 = mux(_T_9395, UInt<1>("h00"), ic_tag_valid_out[0][51]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9397 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h034")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9398 = mux(_T_9397, UInt<1>("h00"), ic_tag_valid_out[0][52]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9399 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h035")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9400 = mux(_T_9399, UInt<1>("h00"), ic_tag_valid_out[0][53]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9401 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h036")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9402 = mux(_T_9401, UInt<1>("h00"), ic_tag_valid_out[0][54]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9403 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h037")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9404 = mux(_T_9403, UInt<1>("h00"), ic_tag_valid_out[0][55]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9405 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h038")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9406 = mux(_T_9405, UInt<1>("h00"), ic_tag_valid_out[0][56]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9407 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h039")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9408 = mux(_T_9407, UInt<1>("h00"), ic_tag_valid_out[0][57]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9409 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03a")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9410 = mux(_T_9409, UInt<1>("h00"), ic_tag_valid_out[0][58]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9411 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03b")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9412 = mux(_T_9411, UInt<1>("h00"), ic_tag_valid_out[0][59]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9413 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03c")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9414 = mux(_T_9413, UInt<1>("h00"), ic_tag_valid_out[0][60]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9415 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03d")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9416 = mux(_T_9415, UInt<1>("h00"), ic_tag_valid_out[0][61]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9417 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03e")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9418 = mux(_T_9417, UInt<1>("h00"), ic_tag_valid_out[0][62]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9419 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03f")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9420 = mux(_T_9419, UInt<1>("h00"), ic_tag_valid_out[0][63]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9421 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h040")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9422 = mux(_T_9421, UInt<1>("h00"), ic_tag_valid_out[0][64]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9423 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h041")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9424 = mux(_T_9423, UInt<1>("h00"), ic_tag_valid_out[0][65]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9425 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h042")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9426 = mux(_T_9425, UInt<1>("h00"), ic_tag_valid_out[0][66]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9427 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h043")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9428 = mux(_T_9427, UInt<1>("h00"), ic_tag_valid_out[0][67]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9429 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h044")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9430 = mux(_T_9429, UInt<1>("h00"), ic_tag_valid_out[0][68]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9431 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h045")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9432 = mux(_T_9431, UInt<1>("h00"), ic_tag_valid_out[0][69]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9433 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h046")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9434 = mux(_T_9433, UInt<1>("h00"), ic_tag_valid_out[0][70]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9435 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h047")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9436 = mux(_T_9435, UInt<1>("h00"), ic_tag_valid_out[0][71]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9437 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h048")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9438 = mux(_T_9437, UInt<1>("h00"), ic_tag_valid_out[0][72]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9439 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h049")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9440 = mux(_T_9439, UInt<1>("h00"), ic_tag_valid_out[0][73]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9441 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04a")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9442 = mux(_T_9441, UInt<1>("h00"), ic_tag_valid_out[0][74]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9443 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04b")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9444 = mux(_T_9443, UInt<1>("h00"), ic_tag_valid_out[0][75]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9445 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04c")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9446 = mux(_T_9445, UInt<1>("h00"), ic_tag_valid_out[0][76]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9447 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04d")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9448 = mux(_T_9447, UInt<1>("h00"), ic_tag_valid_out[0][77]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9449 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04e")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9450 = mux(_T_9449, UInt<1>("h00"), ic_tag_valid_out[0][78]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9451 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04f")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9452 = mux(_T_9451, UInt<1>("h00"), ic_tag_valid_out[0][79]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9453 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h050")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9454 = mux(_T_9453, UInt<1>("h00"), ic_tag_valid_out[0][80]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9455 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h051")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9456 = mux(_T_9455, UInt<1>("h00"), ic_tag_valid_out[0][81]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9457 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h052")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9458 = mux(_T_9457, UInt<1>("h00"), ic_tag_valid_out[0][82]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9459 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h053")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9460 = mux(_T_9459, UInt<1>("h00"), ic_tag_valid_out[0][83]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9461 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h054")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9462 = mux(_T_9461, UInt<1>("h00"), ic_tag_valid_out[0][84]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9463 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h055")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9464 = mux(_T_9463, UInt<1>("h00"), ic_tag_valid_out[0][85]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9465 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h056")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9466 = mux(_T_9465, UInt<1>("h00"), ic_tag_valid_out[0][86]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9467 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h057")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9468 = mux(_T_9467, UInt<1>("h00"), ic_tag_valid_out[0][87]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9469 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h058")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9470 = mux(_T_9469, UInt<1>("h00"), ic_tag_valid_out[0][88]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9471 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h059")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9472 = mux(_T_9471, UInt<1>("h00"), ic_tag_valid_out[0][89]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9473 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05a")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9474 = mux(_T_9473, UInt<1>("h00"), ic_tag_valid_out[0][90]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9475 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05b")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9476 = mux(_T_9475, UInt<1>("h00"), ic_tag_valid_out[0][91]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9477 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05c")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9478 = mux(_T_9477, UInt<1>("h00"), ic_tag_valid_out[0][92]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9479 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05d")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9480 = mux(_T_9479, UInt<1>("h00"), ic_tag_valid_out[0][93]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9481 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05e")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9482 = mux(_T_9481, UInt<1>("h00"), ic_tag_valid_out[0][94]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9483 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05f")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9484 = mux(_T_9483, UInt<1>("h00"), ic_tag_valid_out[0][95]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9485 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h060")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9486 = mux(_T_9485, UInt<1>("h00"), ic_tag_valid_out[0][96]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9487 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h061")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9488 = mux(_T_9487, UInt<1>("h00"), ic_tag_valid_out[0][97]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9489 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h062")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9490 = mux(_T_9489, UInt<1>("h00"), ic_tag_valid_out[0][98]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9491 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h063")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9492 = mux(_T_9491, UInt<1>("h00"), ic_tag_valid_out[0][99]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9493 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h064")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9494 = mux(_T_9493, UInt<1>("h00"), ic_tag_valid_out[0][100]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9495 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h065")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9496 = mux(_T_9495, UInt<1>("h00"), ic_tag_valid_out[0][101]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9497 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h066")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9498 = mux(_T_9497, UInt<1>("h00"), ic_tag_valid_out[0][102]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9499 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h067")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9500 = mux(_T_9499, UInt<1>("h00"), ic_tag_valid_out[0][103]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9501 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h068")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9502 = mux(_T_9501, UInt<1>("h00"), ic_tag_valid_out[0][104]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9503 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h069")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9504 = mux(_T_9503, UInt<1>("h00"), ic_tag_valid_out[0][105]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9505 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06a")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9506 = mux(_T_9505, UInt<1>("h00"), ic_tag_valid_out[0][106]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9507 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06b")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9508 = mux(_T_9507, UInt<1>("h00"), ic_tag_valid_out[0][107]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9509 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06c")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9510 = mux(_T_9509, UInt<1>("h00"), ic_tag_valid_out[0][108]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9511 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06d")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9512 = mux(_T_9511, UInt<1>("h00"), ic_tag_valid_out[0][109]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9513 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06e")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9514 = mux(_T_9513, UInt<1>("h00"), ic_tag_valid_out[0][110]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9515 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06f")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9516 = mux(_T_9515, UInt<1>("h00"), ic_tag_valid_out[0][111]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9517 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h070")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9518 = mux(_T_9517, UInt<1>("h00"), ic_tag_valid_out[0][112]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9519 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h071")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9520 = mux(_T_9519, UInt<1>("h00"), ic_tag_valid_out[0][113]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9521 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h072")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9522 = mux(_T_9521, UInt<1>("h00"), ic_tag_valid_out[0][114]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9523 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h073")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9524 = mux(_T_9523, UInt<1>("h00"), ic_tag_valid_out[0][115]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9525 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h074")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9526 = mux(_T_9525, UInt<1>("h00"), ic_tag_valid_out[0][116]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9527 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h075")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9528 = mux(_T_9527, UInt<1>("h00"), ic_tag_valid_out[0][117]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9529 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h076")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9530 = mux(_T_9529, UInt<1>("h00"), ic_tag_valid_out[0][118]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9531 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h077")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9532 = mux(_T_9531, UInt<1>("h00"), ic_tag_valid_out[0][119]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9533 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h078")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9534 = mux(_T_9533, UInt<1>("h00"), ic_tag_valid_out[0][120]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9535 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h079")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9536 = mux(_T_9535, UInt<1>("h00"), ic_tag_valid_out[0][121]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9537 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07a")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9538 = mux(_T_9537, UInt<1>("h00"), ic_tag_valid_out[0][122]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9539 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07b")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9540 = mux(_T_9539, UInt<1>("h00"), ic_tag_valid_out[0][123]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9541 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07c")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9542 = mux(_T_9541, UInt<1>("h00"), ic_tag_valid_out[0][124]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9543 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07d")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9544 = mux(_T_9543, UInt<1>("h00"), ic_tag_valid_out[0][125]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9545 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07e")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9546 = mux(_T_9545, UInt<1>("h00"), ic_tag_valid_out[0][126]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9547 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07f")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9548 = mux(_T_9547, UInt<1>("h00"), ic_tag_valid_out[0][127]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9549 = or(_T_9294, _T_9296) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9550 = or(_T_9549, _T_9298) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9551 = or(_T_9550, _T_9300) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9552 = or(_T_9551, _T_9302) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9553 = or(_T_9552, _T_9304) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9554 = or(_T_9553, _T_9306) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9555 = or(_T_9554, _T_9308) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9556 = or(_T_9555, _T_9310) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9557 = or(_T_9556, _T_9312) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9558 = or(_T_9557, _T_9314) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9559 = or(_T_9558, _T_9316) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9560 = or(_T_9559, _T_9318) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9561 = or(_T_9560, _T_9320) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9562 = or(_T_9561, _T_9322) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9563 = or(_T_9562, _T_9324) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9564 = or(_T_9563, _T_9326) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9565 = or(_T_9564, _T_9328) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9566 = or(_T_9565, _T_9330) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9567 = or(_T_9566, _T_9332) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9568 = or(_T_9567, _T_9334) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9569 = or(_T_9568, _T_9336) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9570 = or(_T_9569, _T_9338) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9571 = or(_T_9570, _T_9340) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9572 = or(_T_9571, _T_9342) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9573 = or(_T_9572, _T_9344) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9574 = or(_T_9573, _T_9346) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9575 = or(_T_9574, _T_9348) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9576 = or(_T_9575, _T_9350) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9577 = or(_T_9576, _T_9352) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9578 = or(_T_9577, _T_9354) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9579 = or(_T_9578, _T_9356) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9580 = or(_T_9579, _T_9358) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9581 = or(_T_9580, _T_9360) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9582 = or(_T_9581, _T_9362) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9583 = or(_T_9582, _T_9364) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9584 = or(_T_9583, _T_9366) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9585 = or(_T_9584, _T_9368) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9586 = or(_T_9585, _T_9370) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9587 = or(_T_9586, _T_9372) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9588 = or(_T_9587, _T_9374) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9589 = or(_T_9588, _T_9376) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9590 = or(_T_9589, _T_9378) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9591 = or(_T_9590, _T_9380) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9592 = or(_T_9591, _T_9382) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9593 = or(_T_9592, _T_9384) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9594 = or(_T_9593, _T_9386) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9595 = or(_T_9594, _T_9388) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9596 = or(_T_9595, _T_9390) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9597 = or(_T_9596, _T_9392) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9598 = or(_T_9597, _T_9394) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9599 = or(_T_9598, _T_9396) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9600 = or(_T_9599, _T_9398) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9601 = or(_T_9600, _T_9400) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9602 = or(_T_9601, _T_9402) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9603 = or(_T_9602, _T_9404) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9604 = or(_T_9603, _T_9406) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9605 = or(_T_9604, _T_9408) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9606 = or(_T_9605, _T_9410) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9607 = or(_T_9606, _T_9412) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9608 = or(_T_9607, _T_9414) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9609 = or(_T_9608, _T_9416) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9610 = or(_T_9609, _T_9418) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9611 = or(_T_9610, _T_9420) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9612 = or(_T_9611, _T_9422) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9613 = or(_T_9612, _T_9424) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9614 = or(_T_9613, _T_9426) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9615 = or(_T_9614, _T_9428) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9616 = or(_T_9615, _T_9430) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9617 = or(_T_9616, _T_9432) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9618 = or(_T_9617, _T_9434) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9619 = or(_T_9618, _T_9436) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9620 = or(_T_9619, _T_9438) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9621 = or(_T_9620, _T_9440) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9622 = or(_T_9621, _T_9442) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9623 = or(_T_9622, _T_9444) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9624 = or(_T_9623, _T_9446) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9625 = or(_T_9624, _T_9448) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9626 = or(_T_9625, _T_9450) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9627 = or(_T_9626, _T_9452) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9628 = or(_T_9627, _T_9454) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9629 = or(_T_9628, _T_9456) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9630 = or(_T_9629, _T_9458) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9631 = or(_T_9630, _T_9460) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9632 = or(_T_9631, _T_9462) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9633 = or(_T_9632, _T_9464) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9634 = or(_T_9633, _T_9466) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9635 = or(_T_9634, _T_9468) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9636 = or(_T_9635, _T_9470) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9637 = or(_T_9636, _T_9472) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9638 = or(_T_9637, _T_9474) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9639 = or(_T_9638, _T_9476) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9640 = or(_T_9639, _T_9478) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9641 = or(_T_9640, _T_9480) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9642 = or(_T_9641, _T_9482) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9643 = or(_T_9642, _T_9484) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9644 = or(_T_9643, _T_9486) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9645 = or(_T_9644, _T_9488) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9646 = or(_T_9645, _T_9490) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9647 = or(_T_9646, _T_9492) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9648 = or(_T_9647, _T_9494) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9649 = or(_T_9648, _T_9496) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9650 = or(_T_9649, _T_9498) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9651 = or(_T_9650, _T_9500) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9652 = or(_T_9651, _T_9502) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9653 = or(_T_9652, _T_9504) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9654 = or(_T_9653, _T_9506) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9655 = or(_T_9654, _T_9508) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9656 = or(_T_9655, _T_9510) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9657 = or(_T_9656, _T_9512) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9658 = or(_T_9657, _T_9514) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9659 = or(_T_9658, _T_9516) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9660 = or(_T_9659, _T_9518) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9661 = or(_T_9660, _T_9520) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9662 = or(_T_9661, _T_9522) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9663 = or(_T_9662, _T_9524) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9664 = or(_T_9663, _T_9526) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9665 = or(_T_9664, _T_9528) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9666 = or(_T_9665, _T_9530) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9667 = or(_T_9666, _T_9532) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9668 = or(_T_9667, _T_9534) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9669 = or(_T_9668, _T_9536) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9670 = or(_T_9669, _T_9538) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9671 = or(_T_9670, _T_9540) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9672 = or(_T_9671, _T_9542) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9673 = or(_T_9672, _T_9544) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9674 = or(_T_9673, _T_9546) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9675 = or(_T_9674, _T_9548) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9676 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9677 = mux(_T_9676, UInt<1>("h00"), ic_tag_valid_out[1][0]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9678 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9679 = mux(_T_9678, UInt<1>("h00"), ic_tag_valid_out[1][1]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9680 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9681 = mux(_T_9680, UInt<1>("h00"), ic_tag_valid_out[1][2]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9682 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9683 = mux(_T_9682, UInt<1>("h00"), ic_tag_valid_out[1][3]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9684 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9685 = mux(_T_9684, UInt<1>("h00"), ic_tag_valid_out[1][4]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9686 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9687 = mux(_T_9686, UInt<1>("h00"), ic_tag_valid_out[1][5]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9688 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9689 = mux(_T_9688, UInt<1>("h00"), ic_tag_valid_out[1][6]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9690 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9691 = mux(_T_9690, UInt<1>("h00"), ic_tag_valid_out[1][7]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9692 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9693 = mux(_T_9692, UInt<1>("h00"), ic_tag_valid_out[1][8]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9694 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9695 = mux(_T_9694, UInt<1>("h00"), ic_tag_valid_out[1][9]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9696 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9697 = mux(_T_9696, UInt<1>("h00"), ic_tag_valid_out[1][10]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9698 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9699 = mux(_T_9698, UInt<1>("h00"), ic_tag_valid_out[1][11]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9700 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9701 = mux(_T_9700, UInt<1>("h00"), ic_tag_valid_out[1][12]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9702 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9703 = mux(_T_9702, UInt<1>("h00"), ic_tag_valid_out[1][13]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9704 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9705 = mux(_T_9704, UInt<1>("h00"), ic_tag_valid_out[1][14]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9706 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9707 = mux(_T_9706, UInt<1>("h00"), ic_tag_valid_out[1][15]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9708 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h010")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9709 = mux(_T_9708, UInt<1>("h00"), ic_tag_valid_out[1][16]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9710 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h011")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9711 = mux(_T_9710, UInt<1>("h00"), ic_tag_valid_out[1][17]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9712 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h012")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9713 = mux(_T_9712, UInt<1>("h00"), ic_tag_valid_out[1][18]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9714 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h013")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9715 = mux(_T_9714, UInt<1>("h00"), ic_tag_valid_out[1][19]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9716 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h014")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9717 = mux(_T_9716, UInt<1>("h00"), ic_tag_valid_out[1][20]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9718 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h015")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9719 = mux(_T_9718, UInt<1>("h00"), ic_tag_valid_out[1][21]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9720 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h016")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9721 = mux(_T_9720, UInt<1>("h00"), ic_tag_valid_out[1][22]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9722 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h017")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9723 = mux(_T_9722, UInt<1>("h00"), ic_tag_valid_out[1][23]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9724 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h018")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9725 = mux(_T_9724, UInt<1>("h00"), ic_tag_valid_out[1][24]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9726 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h019")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9727 = mux(_T_9726, UInt<1>("h00"), ic_tag_valid_out[1][25]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9728 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01a")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9729 = mux(_T_9728, UInt<1>("h00"), ic_tag_valid_out[1][26]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9730 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01b")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9731 = mux(_T_9730, UInt<1>("h00"), ic_tag_valid_out[1][27]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9732 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01c")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9733 = mux(_T_9732, UInt<1>("h00"), ic_tag_valid_out[1][28]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9734 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01d")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9735 = mux(_T_9734, UInt<1>("h00"), ic_tag_valid_out[1][29]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9736 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01e")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9737 = mux(_T_9736, UInt<1>("h00"), ic_tag_valid_out[1][30]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9738 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01f")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9739 = mux(_T_9738, UInt<1>("h00"), ic_tag_valid_out[1][31]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9740 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h020")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9741 = mux(_T_9740, UInt<1>("h00"), ic_tag_valid_out[1][32]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9742 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h021")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9743 = mux(_T_9742, UInt<1>("h00"), ic_tag_valid_out[1][33]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9744 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h022")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9745 = mux(_T_9744, UInt<1>("h00"), ic_tag_valid_out[1][34]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9746 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h023")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9747 = mux(_T_9746, UInt<1>("h00"), ic_tag_valid_out[1][35]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9748 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h024")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9749 = mux(_T_9748, UInt<1>("h00"), ic_tag_valid_out[1][36]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9750 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h025")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9751 = mux(_T_9750, UInt<1>("h00"), ic_tag_valid_out[1][37]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9752 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h026")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9753 = mux(_T_9752, UInt<1>("h00"), ic_tag_valid_out[1][38]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9754 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h027")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9755 = mux(_T_9754, UInt<1>("h00"), ic_tag_valid_out[1][39]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9756 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h028")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9757 = mux(_T_9756, UInt<1>("h00"), ic_tag_valid_out[1][40]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9758 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h029")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9759 = mux(_T_9758, UInt<1>("h00"), ic_tag_valid_out[1][41]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9760 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02a")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9761 = mux(_T_9760, UInt<1>("h00"), ic_tag_valid_out[1][42]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9762 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02b")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9763 = mux(_T_9762, UInt<1>("h00"), ic_tag_valid_out[1][43]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9764 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02c")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9765 = mux(_T_9764, UInt<1>("h00"), ic_tag_valid_out[1][44]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9766 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02d")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9767 = mux(_T_9766, UInt<1>("h00"), ic_tag_valid_out[1][45]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9768 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02e")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9769 = mux(_T_9768, UInt<1>("h00"), ic_tag_valid_out[1][46]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9770 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02f")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9771 = mux(_T_9770, UInt<1>("h00"), ic_tag_valid_out[1][47]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9772 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h030")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9773 = mux(_T_9772, UInt<1>("h00"), ic_tag_valid_out[1][48]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9774 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h031")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9775 = mux(_T_9774, UInt<1>("h00"), ic_tag_valid_out[1][49]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9776 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h032")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9777 = mux(_T_9776, UInt<1>("h00"), ic_tag_valid_out[1][50]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9778 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h033")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9779 = mux(_T_9778, UInt<1>("h00"), ic_tag_valid_out[1][51]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9780 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h034")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9781 = mux(_T_9780, UInt<1>("h00"), ic_tag_valid_out[1][52]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9782 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h035")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9783 = mux(_T_9782, UInt<1>("h00"), ic_tag_valid_out[1][53]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9784 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h036")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9785 = mux(_T_9784, UInt<1>("h00"), ic_tag_valid_out[1][54]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9786 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h037")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9787 = mux(_T_9786, UInt<1>("h00"), ic_tag_valid_out[1][55]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9788 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h038")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9789 = mux(_T_9788, UInt<1>("h00"), ic_tag_valid_out[1][56]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9790 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h039")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9791 = mux(_T_9790, UInt<1>("h00"), ic_tag_valid_out[1][57]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9792 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03a")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9793 = mux(_T_9792, UInt<1>("h00"), ic_tag_valid_out[1][58]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9794 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03b")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9795 = mux(_T_9794, UInt<1>("h00"), ic_tag_valid_out[1][59]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9796 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03c")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9797 = mux(_T_9796, UInt<1>("h00"), ic_tag_valid_out[1][60]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9798 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03d")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9799 = mux(_T_9798, UInt<1>("h00"), ic_tag_valid_out[1][61]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9800 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03e")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9801 = mux(_T_9800, UInt<1>("h00"), ic_tag_valid_out[1][62]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9802 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03f")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9803 = mux(_T_9802, UInt<1>("h00"), ic_tag_valid_out[1][63]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9804 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h040")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9805 = mux(_T_9804, UInt<1>("h00"), ic_tag_valid_out[1][64]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9806 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h041")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9807 = mux(_T_9806, UInt<1>("h00"), ic_tag_valid_out[1][65]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9808 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h042")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9809 = mux(_T_9808, UInt<1>("h00"), ic_tag_valid_out[1][66]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9810 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h043")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9811 = mux(_T_9810, UInt<1>("h00"), ic_tag_valid_out[1][67]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9812 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h044")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9813 = mux(_T_9812, UInt<1>("h00"), ic_tag_valid_out[1][68]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9814 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h045")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9815 = mux(_T_9814, UInt<1>("h00"), ic_tag_valid_out[1][69]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9816 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h046")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9817 = mux(_T_9816, UInt<1>("h00"), ic_tag_valid_out[1][70]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9818 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h047")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9819 = mux(_T_9818, UInt<1>("h00"), ic_tag_valid_out[1][71]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9820 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h048")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9821 = mux(_T_9820, UInt<1>("h00"), ic_tag_valid_out[1][72]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9822 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h049")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9823 = mux(_T_9822, UInt<1>("h00"), ic_tag_valid_out[1][73]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9824 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04a")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9825 = mux(_T_9824, UInt<1>("h00"), ic_tag_valid_out[1][74]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9826 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04b")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9827 = mux(_T_9826, UInt<1>("h00"), ic_tag_valid_out[1][75]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9828 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04c")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9829 = mux(_T_9828, UInt<1>("h00"), ic_tag_valid_out[1][76]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9830 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04d")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9831 = mux(_T_9830, UInt<1>("h00"), ic_tag_valid_out[1][77]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9832 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04e")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9833 = mux(_T_9832, UInt<1>("h00"), ic_tag_valid_out[1][78]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9834 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04f")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9835 = mux(_T_9834, UInt<1>("h00"), ic_tag_valid_out[1][79]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9836 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h050")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9837 = mux(_T_9836, UInt<1>("h00"), ic_tag_valid_out[1][80]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9838 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h051")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9839 = mux(_T_9838, UInt<1>("h00"), ic_tag_valid_out[1][81]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9840 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h052")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9841 = mux(_T_9840, UInt<1>("h00"), ic_tag_valid_out[1][82]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9842 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h053")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9843 = mux(_T_9842, UInt<1>("h00"), ic_tag_valid_out[1][83]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9844 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h054")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9845 = mux(_T_9844, UInt<1>("h00"), ic_tag_valid_out[1][84]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9846 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h055")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9847 = mux(_T_9846, UInt<1>("h00"), ic_tag_valid_out[1][85]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9848 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h056")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9849 = mux(_T_9848, UInt<1>("h00"), ic_tag_valid_out[1][86]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9850 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h057")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9851 = mux(_T_9850, UInt<1>("h00"), ic_tag_valid_out[1][87]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9852 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h058")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9853 = mux(_T_9852, UInt<1>("h00"), ic_tag_valid_out[1][88]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9854 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h059")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9855 = mux(_T_9854, UInt<1>("h00"), ic_tag_valid_out[1][89]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9856 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05a")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9857 = mux(_T_9856, UInt<1>("h00"), ic_tag_valid_out[1][90]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9858 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05b")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9859 = mux(_T_9858, UInt<1>("h00"), ic_tag_valid_out[1][91]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9860 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05c")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9861 = mux(_T_9860, UInt<1>("h00"), ic_tag_valid_out[1][92]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9862 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05d")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9863 = mux(_T_9862, UInt<1>("h00"), ic_tag_valid_out[1][93]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9864 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05e")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9865 = mux(_T_9864, UInt<1>("h00"), ic_tag_valid_out[1][94]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9866 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05f")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9867 = mux(_T_9866, UInt<1>("h00"), ic_tag_valid_out[1][95]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9868 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h060")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9869 = mux(_T_9868, UInt<1>("h00"), ic_tag_valid_out[1][96]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9870 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h061")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9871 = mux(_T_9870, UInt<1>("h00"), ic_tag_valid_out[1][97]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9872 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h062")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9873 = mux(_T_9872, UInt<1>("h00"), ic_tag_valid_out[1][98]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9874 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h063")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9875 = mux(_T_9874, UInt<1>("h00"), ic_tag_valid_out[1][99]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9876 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h064")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9877 = mux(_T_9876, UInt<1>("h00"), ic_tag_valid_out[1][100]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9878 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h065")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9879 = mux(_T_9878, UInt<1>("h00"), ic_tag_valid_out[1][101]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9880 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h066")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9881 = mux(_T_9880, UInt<1>("h00"), ic_tag_valid_out[1][102]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9882 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h067")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9883 = mux(_T_9882, UInt<1>("h00"), ic_tag_valid_out[1][103]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9884 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h068")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9885 = mux(_T_9884, UInt<1>("h00"), ic_tag_valid_out[1][104]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9886 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h069")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9887 = mux(_T_9886, UInt<1>("h00"), ic_tag_valid_out[1][105]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9888 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06a")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9889 = mux(_T_9888, UInt<1>("h00"), ic_tag_valid_out[1][106]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9890 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06b")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9891 = mux(_T_9890, UInt<1>("h00"), ic_tag_valid_out[1][107]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9892 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06c")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9893 = mux(_T_9892, UInt<1>("h00"), ic_tag_valid_out[1][108]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9894 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06d")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9895 = mux(_T_9894, UInt<1>("h00"), ic_tag_valid_out[1][109]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9896 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06e")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9897 = mux(_T_9896, UInt<1>("h00"), ic_tag_valid_out[1][110]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9898 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06f")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9899 = mux(_T_9898, UInt<1>("h00"), ic_tag_valid_out[1][111]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9900 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h070")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9901 = mux(_T_9900, UInt<1>("h00"), ic_tag_valid_out[1][112]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9902 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h071")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9903 = mux(_T_9902, UInt<1>("h00"), ic_tag_valid_out[1][113]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9904 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h072")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9905 = mux(_T_9904, UInt<1>("h00"), ic_tag_valid_out[1][114]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9906 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h073")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9907 = mux(_T_9906, UInt<1>("h00"), ic_tag_valid_out[1][115]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9908 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h074")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9909 = mux(_T_9908, UInt<1>("h00"), ic_tag_valid_out[1][116]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9910 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h075")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9911 = mux(_T_9910, UInt<1>("h00"), ic_tag_valid_out[1][117]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9912 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h076")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9913 = mux(_T_9912, UInt<1>("h00"), ic_tag_valid_out[1][118]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9914 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h077")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9915 = mux(_T_9914, UInt<1>("h00"), ic_tag_valid_out[1][119]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9916 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h078")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9917 = mux(_T_9916, UInt<1>("h00"), ic_tag_valid_out[1][120]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9918 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h079")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9919 = mux(_T_9918, UInt<1>("h00"), ic_tag_valid_out[1][121]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9920 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07a")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9921 = mux(_T_9920, UInt<1>("h00"), ic_tag_valid_out[1][122]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9922 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07b")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9923 = mux(_T_9922, UInt<1>("h00"), ic_tag_valid_out[1][123]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9924 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07c")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9925 = mux(_T_9924, UInt<1>("h00"), ic_tag_valid_out[1][124]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9926 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07d")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9927 = mux(_T_9926, UInt<1>("h00"), ic_tag_valid_out[1][125]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9928 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07e")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9929 = mux(_T_9928, UInt<1>("h00"), ic_tag_valid_out[1][126]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9930 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07f")) @[el2_ifu_mem_ctl.scala 744:33] - node _T_9931 = mux(_T_9930, UInt<1>("h00"), ic_tag_valid_out[1][127]) @[el2_ifu_mem_ctl.scala 744:10] - node _T_9932 = or(_T_9677, _T_9679) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9933 = or(_T_9932, _T_9681) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9934 = or(_T_9933, _T_9683) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9935 = or(_T_9934, _T_9685) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9936 = or(_T_9935, _T_9687) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9937 = or(_T_9936, _T_9689) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9938 = or(_T_9937, _T_9691) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9939 = or(_T_9938, _T_9693) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9940 = or(_T_9939, _T_9695) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9941 = or(_T_9940, _T_9697) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9942 = or(_T_9941, _T_9699) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9943 = or(_T_9942, _T_9701) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9944 = or(_T_9943, _T_9703) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9945 = or(_T_9944, _T_9705) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9946 = or(_T_9945, _T_9707) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9947 = or(_T_9946, _T_9709) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9948 = or(_T_9947, _T_9711) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9949 = or(_T_9948, _T_9713) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9950 = or(_T_9949, _T_9715) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9951 = or(_T_9950, _T_9717) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9952 = or(_T_9951, _T_9719) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9953 = or(_T_9952, _T_9721) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9954 = or(_T_9953, _T_9723) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9955 = or(_T_9954, _T_9725) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9956 = or(_T_9955, _T_9727) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9957 = or(_T_9956, _T_9729) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9958 = or(_T_9957, _T_9731) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9959 = or(_T_9958, _T_9733) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9960 = or(_T_9959, _T_9735) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9961 = or(_T_9960, _T_9737) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9962 = or(_T_9961, _T_9739) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9963 = or(_T_9962, _T_9741) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9964 = or(_T_9963, _T_9743) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9965 = or(_T_9964, _T_9745) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9966 = or(_T_9965, _T_9747) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9967 = or(_T_9966, _T_9749) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9968 = or(_T_9967, _T_9751) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9969 = or(_T_9968, _T_9753) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9970 = or(_T_9969, _T_9755) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9971 = or(_T_9970, _T_9757) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9972 = or(_T_9971, _T_9759) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9973 = or(_T_9972, _T_9761) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9974 = or(_T_9973, _T_9763) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9975 = or(_T_9974, _T_9765) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9976 = or(_T_9975, _T_9767) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9977 = or(_T_9976, _T_9769) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9978 = or(_T_9977, _T_9771) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9979 = or(_T_9978, _T_9773) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9980 = or(_T_9979, _T_9775) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9981 = or(_T_9980, _T_9777) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9982 = or(_T_9981, _T_9779) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9983 = or(_T_9982, _T_9781) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9984 = or(_T_9983, _T_9783) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9985 = or(_T_9984, _T_9785) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9986 = or(_T_9985, _T_9787) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9987 = or(_T_9986, _T_9789) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9988 = or(_T_9987, _T_9791) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9989 = or(_T_9988, _T_9793) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9990 = or(_T_9989, _T_9795) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9991 = or(_T_9990, _T_9797) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9992 = or(_T_9991, _T_9799) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9993 = or(_T_9992, _T_9801) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9994 = or(_T_9993, _T_9803) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9995 = or(_T_9994, _T_9805) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9996 = or(_T_9995, _T_9807) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9997 = or(_T_9996, _T_9809) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9998 = or(_T_9997, _T_9811) @[el2_ifu_mem_ctl.scala 744:91] - node _T_9999 = or(_T_9998, _T_9813) @[el2_ifu_mem_ctl.scala 744:91] - node _T_10000 = or(_T_9999, _T_9815) @[el2_ifu_mem_ctl.scala 744:91] - node _T_10001 = or(_T_10000, _T_9817) @[el2_ifu_mem_ctl.scala 744:91] - node _T_10002 = or(_T_10001, _T_9819) @[el2_ifu_mem_ctl.scala 744:91] - node _T_10003 = or(_T_10002, _T_9821) @[el2_ifu_mem_ctl.scala 744:91] - node _T_10004 = or(_T_10003, _T_9823) @[el2_ifu_mem_ctl.scala 744:91] - node _T_10005 = or(_T_10004, _T_9825) @[el2_ifu_mem_ctl.scala 744:91] - node _T_10006 = or(_T_10005, _T_9827) @[el2_ifu_mem_ctl.scala 744:91] - node _T_10007 = or(_T_10006, _T_9829) @[el2_ifu_mem_ctl.scala 744:91] - node _T_10008 = or(_T_10007, _T_9831) @[el2_ifu_mem_ctl.scala 744:91] - node _T_10009 = or(_T_10008, _T_9833) @[el2_ifu_mem_ctl.scala 744:91] - node _T_10010 = or(_T_10009, _T_9835) @[el2_ifu_mem_ctl.scala 744:91] - node _T_10011 = or(_T_10010, _T_9837) @[el2_ifu_mem_ctl.scala 744:91] - node _T_10012 = or(_T_10011, _T_9839) @[el2_ifu_mem_ctl.scala 744:91] - node _T_10013 = or(_T_10012, _T_9841) @[el2_ifu_mem_ctl.scala 744:91] - node _T_10014 = or(_T_10013, _T_9843) @[el2_ifu_mem_ctl.scala 744:91] - node _T_10015 = or(_T_10014, _T_9845) @[el2_ifu_mem_ctl.scala 744:91] - node _T_10016 = or(_T_10015, _T_9847) @[el2_ifu_mem_ctl.scala 744:91] - node _T_10017 = or(_T_10016, _T_9849) @[el2_ifu_mem_ctl.scala 744:91] - node _T_10018 = or(_T_10017, _T_9851) @[el2_ifu_mem_ctl.scala 744:91] - node _T_10019 = or(_T_10018, _T_9853) @[el2_ifu_mem_ctl.scala 744:91] - node _T_10020 = or(_T_10019, _T_9855) @[el2_ifu_mem_ctl.scala 744:91] - node _T_10021 = or(_T_10020, _T_9857) @[el2_ifu_mem_ctl.scala 744:91] - node _T_10022 = or(_T_10021, _T_9859) @[el2_ifu_mem_ctl.scala 744:91] - node _T_10023 = or(_T_10022, _T_9861) @[el2_ifu_mem_ctl.scala 744:91] - node _T_10024 = or(_T_10023, _T_9863) @[el2_ifu_mem_ctl.scala 744:91] - node _T_10025 = or(_T_10024, _T_9865) @[el2_ifu_mem_ctl.scala 744:91] - node _T_10026 = or(_T_10025, _T_9867) @[el2_ifu_mem_ctl.scala 744:91] - node _T_10027 = or(_T_10026, _T_9869) @[el2_ifu_mem_ctl.scala 744:91] - node _T_10028 = or(_T_10027, _T_9871) @[el2_ifu_mem_ctl.scala 744:91] - node _T_10029 = or(_T_10028, _T_9873) @[el2_ifu_mem_ctl.scala 744:91] - node _T_10030 = or(_T_10029, _T_9875) @[el2_ifu_mem_ctl.scala 744:91] - node _T_10031 = or(_T_10030, _T_9877) @[el2_ifu_mem_ctl.scala 744:91] - node _T_10032 = or(_T_10031, _T_9879) @[el2_ifu_mem_ctl.scala 744:91] - node _T_10033 = or(_T_10032, _T_9881) @[el2_ifu_mem_ctl.scala 744:91] - node _T_10034 = or(_T_10033, _T_9883) @[el2_ifu_mem_ctl.scala 744:91] - node _T_10035 = or(_T_10034, _T_9885) @[el2_ifu_mem_ctl.scala 744:91] - node _T_10036 = or(_T_10035, _T_9887) @[el2_ifu_mem_ctl.scala 744:91] - node _T_10037 = or(_T_10036, _T_9889) @[el2_ifu_mem_ctl.scala 744:91] - node _T_10038 = or(_T_10037, _T_9891) @[el2_ifu_mem_ctl.scala 744:91] - node _T_10039 = or(_T_10038, _T_9893) @[el2_ifu_mem_ctl.scala 744:91] - node _T_10040 = or(_T_10039, _T_9895) @[el2_ifu_mem_ctl.scala 744:91] - node _T_10041 = or(_T_10040, _T_9897) @[el2_ifu_mem_ctl.scala 744:91] - node _T_10042 = or(_T_10041, _T_9899) @[el2_ifu_mem_ctl.scala 744:91] - node _T_10043 = or(_T_10042, _T_9901) @[el2_ifu_mem_ctl.scala 744:91] - node _T_10044 = or(_T_10043, _T_9903) @[el2_ifu_mem_ctl.scala 744:91] - node _T_10045 = or(_T_10044, _T_9905) @[el2_ifu_mem_ctl.scala 744:91] - node _T_10046 = or(_T_10045, _T_9907) @[el2_ifu_mem_ctl.scala 744:91] - node _T_10047 = or(_T_10046, _T_9909) @[el2_ifu_mem_ctl.scala 744:91] - node _T_10048 = or(_T_10047, _T_9911) @[el2_ifu_mem_ctl.scala 744:91] - node _T_10049 = or(_T_10048, _T_9913) @[el2_ifu_mem_ctl.scala 744:91] - node _T_10050 = or(_T_10049, _T_9915) @[el2_ifu_mem_ctl.scala 744:91] - node _T_10051 = or(_T_10050, _T_9917) @[el2_ifu_mem_ctl.scala 744:91] - node _T_10052 = or(_T_10051, _T_9919) @[el2_ifu_mem_ctl.scala 744:91] - node _T_10053 = or(_T_10052, _T_9921) @[el2_ifu_mem_ctl.scala 744:91] - node _T_10054 = or(_T_10053, _T_9923) @[el2_ifu_mem_ctl.scala 744:91] - node _T_10055 = or(_T_10054, _T_9925) @[el2_ifu_mem_ctl.scala 744:91] - node _T_10056 = or(_T_10055, _T_9927) @[el2_ifu_mem_ctl.scala 744:91] - node _T_10057 = or(_T_10056, _T_9929) @[el2_ifu_mem_ctl.scala 744:91] - node _T_10058 = or(_T_10057, _T_9931) @[el2_ifu_mem_ctl.scala 744:91] + ic_tag_valid_out[1][127] <= _T_9292 @[el2_ifu_mem_ctl.scala 741:39] + node _T_9293 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9294 = mux(_T_9293, UInt<1>("h00"), ic_tag_valid_out[0][0]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9295 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9296 = mux(_T_9295, UInt<1>("h00"), ic_tag_valid_out[0][1]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9297 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9298 = mux(_T_9297, UInt<1>("h00"), ic_tag_valid_out[0][2]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9299 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9300 = mux(_T_9299, UInt<1>("h00"), ic_tag_valid_out[0][3]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9301 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9302 = mux(_T_9301, UInt<1>("h00"), ic_tag_valid_out[0][4]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9303 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9304 = mux(_T_9303, UInt<1>("h00"), ic_tag_valid_out[0][5]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9305 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9306 = mux(_T_9305, UInt<1>("h00"), ic_tag_valid_out[0][6]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9307 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9308 = mux(_T_9307, UInt<1>("h00"), ic_tag_valid_out[0][7]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9309 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9310 = mux(_T_9309, UInt<1>("h00"), ic_tag_valid_out[0][8]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9311 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9312 = mux(_T_9311, UInt<1>("h00"), ic_tag_valid_out[0][9]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9313 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9314 = mux(_T_9313, UInt<1>("h00"), ic_tag_valid_out[0][10]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9315 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9316 = mux(_T_9315, UInt<1>("h00"), ic_tag_valid_out[0][11]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9317 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9318 = mux(_T_9317, UInt<1>("h00"), ic_tag_valid_out[0][12]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9319 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9320 = mux(_T_9319, UInt<1>("h00"), ic_tag_valid_out[0][13]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9321 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9322 = mux(_T_9321, UInt<1>("h00"), ic_tag_valid_out[0][14]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9323 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9324 = mux(_T_9323, UInt<1>("h00"), ic_tag_valid_out[0][15]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9325 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h010")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9326 = mux(_T_9325, UInt<1>("h00"), ic_tag_valid_out[0][16]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9327 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h011")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9328 = mux(_T_9327, UInt<1>("h00"), ic_tag_valid_out[0][17]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9329 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h012")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9330 = mux(_T_9329, UInt<1>("h00"), ic_tag_valid_out[0][18]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9331 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h013")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9332 = mux(_T_9331, UInt<1>("h00"), ic_tag_valid_out[0][19]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9333 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h014")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9334 = mux(_T_9333, UInt<1>("h00"), ic_tag_valid_out[0][20]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9335 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h015")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9336 = mux(_T_9335, UInt<1>("h00"), ic_tag_valid_out[0][21]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9337 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h016")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9338 = mux(_T_9337, UInt<1>("h00"), ic_tag_valid_out[0][22]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9339 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h017")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9340 = mux(_T_9339, UInt<1>("h00"), ic_tag_valid_out[0][23]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9341 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h018")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9342 = mux(_T_9341, UInt<1>("h00"), ic_tag_valid_out[0][24]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9343 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h019")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9344 = mux(_T_9343, UInt<1>("h00"), ic_tag_valid_out[0][25]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9345 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01a")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9346 = mux(_T_9345, UInt<1>("h00"), ic_tag_valid_out[0][26]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9347 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01b")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9348 = mux(_T_9347, UInt<1>("h00"), ic_tag_valid_out[0][27]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9349 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01c")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9350 = mux(_T_9349, UInt<1>("h00"), ic_tag_valid_out[0][28]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9351 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01d")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9352 = mux(_T_9351, UInt<1>("h00"), ic_tag_valid_out[0][29]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9353 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01e")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9354 = mux(_T_9353, UInt<1>("h00"), ic_tag_valid_out[0][30]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9355 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01f")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9356 = mux(_T_9355, UInt<1>("h00"), ic_tag_valid_out[0][31]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9357 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h020")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9358 = mux(_T_9357, UInt<1>("h00"), ic_tag_valid_out[0][32]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9359 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h021")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9360 = mux(_T_9359, UInt<1>("h00"), ic_tag_valid_out[0][33]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9361 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h022")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9362 = mux(_T_9361, UInt<1>("h00"), ic_tag_valid_out[0][34]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9363 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h023")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9364 = mux(_T_9363, UInt<1>("h00"), ic_tag_valid_out[0][35]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9365 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h024")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9366 = mux(_T_9365, UInt<1>("h00"), ic_tag_valid_out[0][36]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9367 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h025")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9368 = mux(_T_9367, UInt<1>("h00"), ic_tag_valid_out[0][37]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9369 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h026")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9370 = mux(_T_9369, UInt<1>("h00"), ic_tag_valid_out[0][38]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9371 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h027")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9372 = mux(_T_9371, UInt<1>("h00"), ic_tag_valid_out[0][39]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9373 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h028")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9374 = mux(_T_9373, UInt<1>("h00"), ic_tag_valid_out[0][40]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9375 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h029")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9376 = mux(_T_9375, UInt<1>("h00"), ic_tag_valid_out[0][41]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9377 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02a")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9378 = mux(_T_9377, UInt<1>("h00"), ic_tag_valid_out[0][42]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9379 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02b")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9380 = mux(_T_9379, UInt<1>("h00"), ic_tag_valid_out[0][43]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9381 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02c")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9382 = mux(_T_9381, UInt<1>("h00"), ic_tag_valid_out[0][44]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9383 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02d")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9384 = mux(_T_9383, UInt<1>("h00"), ic_tag_valid_out[0][45]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9385 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02e")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9386 = mux(_T_9385, UInt<1>("h00"), ic_tag_valid_out[0][46]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9387 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02f")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9388 = mux(_T_9387, UInt<1>("h00"), ic_tag_valid_out[0][47]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9389 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h030")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9390 = mux(_T_9389, UInt<1>("h00"), ic_tag_valid_out[0][48]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9391 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h031")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9392 = mux(_T_9391, UInt<1>("h00"), ic_tag_valid_out[0][49]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9393 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h032")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9394 = mux(_T_9393, UInt<1>("h00"), ic_tag_valid_out[0][50]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9395 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h033")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9396 = mux(_T_9395, UInt<1>("h00"), ic_tag_valid_out[0][51]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9397 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h034")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9398 = mux(_T_9397, UInt<1>("h00"), ic_tag_valid_out[0][52]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9399 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h035")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9400 = mux(_T_9399, UInt<1>("h00"), ic_tag_valid_out[0][53]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9401 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h036")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9402 = mux(_T_9401, UInt<1>("h00"), ic_tag_valid_out[0][54]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9403 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h037")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9404 = mux(_T_9403, UInt<1>("h00"), ic_tag_valid_out[0][55]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9405 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h038")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9406 = mux(_T_9405, UInt<1>("h00"), ic_tag_valid_out[0][56]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9407 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h039")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9408 = mux(_T_9407, UInt<1>("h00"), ic_tag_valid_out[0][57]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9409 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03a")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9410 = mux(_T_9409, UInt<1>("h00"), ic_tag_valid_out[0][58]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9411 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03b")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9412 = mux(_T_9411, UInt<1>("h00"), ic_tag_valid_out[0][59]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9413 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03c")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9414 = mux(_T_9413, UInt<1>("h00"), ic_tag_valid_out[0][60]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9415 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03d")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9416 = mux(_T_9415, UInt<1>("h00"), ic_tag_valid_out[0][61]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9417 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03e")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9418 = mux(_T_9417, UInt<1>("h00"), ic_tag_valid_out[0][62]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9419 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03f")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9420 = mux(_T_9419, UInt<1>("h00"), ic_tag_valid_out[0][63]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9421 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h040")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9422 = mux(_T_9421, UInt<1>("h00"), ic_tag_valid_out[0][64]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9423 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h041")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9424 = mux(_T_9423, UInt<1>("h00"), ic_tag_valid_out[0][65]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9425 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h042")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9426 = mux(_T_9425, UInt<1>("h00"), ic_tag_valid_out[0][66]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9427 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h043")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9428 = mux(_T_9427, UInt<1>("h00"), ic_tag_valid_out[0][67]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9429 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h044")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9430 = mux(_T_9429, UInt<1>("h00"), ic_tag_valid_out[0][68]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9431 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h045")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9432 = mux(_T_9431, UInt<1>("h00"), ic_tag_valid_out[0][69]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9433 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h046")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9434 = mux(_T_9433, UInt<1>("h00"), ic_tag_valid_out[0][70]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9435 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h047")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9436 = mux(_T_9435, UInt<1>("h00"), ic_tag_valid_out[0][71]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9437 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h048")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9438 = mux(_T_9437, UInt<1>("h00"), ic_tag_valid_out[0][72]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9439 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h049")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9440 = mux(_T_9439, UInt<1>("h00"), ic_tag_valid_out[0][73]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9441 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04a")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9442 = mux(_T_9441, UInt<1>("h00"), ic_tag_valid_out[0][74]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9443 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04b")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9444 = mux(_T_9443, UInt<1>("h00"), ic_tag_valid_out[0][75]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9445 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04c")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9446 = mux(_T_9445, UInt<1>("h00"), ic_tag_valid_out[0][76]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9447 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04d")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9448 = mux(_T_9447, UInt<1>("h00"), ic_tag_valid_out[0][77]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9449 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04e")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9450 = mux(_T_9449, UInt<1>("h00"), ic_tag_valid_out[0][78]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9451 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04f")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9452 = mux(_T_9451, UInt<1>("h00"), ic_tag_valid_out[0][79]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9453 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h050")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9454 = mux(_T_9453, UInt<1>("h00"), ic_tag_valid_out[0][80]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9455 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h051")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9456 = mux(_T_9455, UInt<1>("h00"), ic_tag_valid_out[0][81]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9457 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h052")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9458 = mux(_T_9457, UInt<1>("h00"), ic_tag_valid_out[0][82]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9459 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h053")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9460 = mux(_T_9459, UInt<1>("h00"), ic_tag_valid_out[0][83]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9461 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h054")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9462 = mux(_T_9461, UInt<1>("h00"), ic_tag_valid_out[0][84]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9463 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h055")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9464 = mux(_T_9463, UInt<1>("h00"), ic_tag_valid_out[0][85]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9465 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h056")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9466 = mux(_T_9465, UInt<1>("h00"), ic_tag_valid_out[0][86]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9467 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h057")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9468 = mux(_T_9467, UInt<1>("h00"), ic_tag_valid_out[0][87]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9469 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h058")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9470 = mux(_T_9469, UInt<1>("h00"), ic_tag_valid_out[0][88]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9471 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h059")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9472 = mux(_T_9471, UInt<1>("h00"), ic_tag_valid_out[0][89]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9473 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05a")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9474 = mux(_T_9473, UInt<1>("h00"), ic_tag_valid_out[0][90]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9475 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05b")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9476 = mux(_T_9475, UInt<1>("h00"), ic_tag_valid_out[0][91]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9477 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05c")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9478 = mux(_T_9477, UInt<1>("h00"), ic_tag_valid_out[0][92]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9479 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05d")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9480 = mux(_T_9479, UInt<1>("h00"), ic_tag_valid_out[0][93]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9481 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05e")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9482 = mux(_T_9481, UInt<1>("h00"), ic_tag_valid_out[0][94]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9483 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05f")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9484 = mux(_T_9483, UInt<1>("h00"), ic_tag_valid_out[0][95]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9485 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h060")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9486 = mux(_T_9485, UInt<1>("h00"), ic_tag_valid_out[0][96]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9487 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h061")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9488 = mux(_T_9487, UInt<1>("h00"), ic_tag_valid_out[0][97]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9489 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h062")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9490 = mux(_T_9489, UInt<1>("h00"), ic_tag_valid_out[0][98]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9491 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h063")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9492 = mux(_T_9491, UInt<1>("h00"), ic_tag_valid_out[0][99]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9493 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h064")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9494 = mux(_T_9493, UInt<1>("h00"), ic_tag_valid_out[0][100]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9495 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h065")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9496 = mux(_T_9495, UInt<1>("h00"), ic_tag_valid_out[0][101]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9497 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h066")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9498 = mux(_T_9497, UInt<1>("h00"), ic_tag_valid_out[0][102]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9499 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h067")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9500 = mux(_T_9499, UInt<1>("h00"), ic_tag_valid_out[0][103]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9501 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h068")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9502 = mux(_T_9501, UInt<1>("h00"), ic_tag_valid_out[0][104]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9503 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h069")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9504 = mux(_T_9503, UInt<1>("h00"), ic_tag_valid_out[0][105]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9505 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06a")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9506 = mux(_T_9505, UInt<1>("h00"), ic_tag_valid_out[0][106]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9507 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06b")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9508 = mux(_T_9507, UInt<1>("h00"), ic_tag_valid_out[0][107]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9509 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06c")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9510 = mux(_T_9509, UInt<1>("h00"), ic_tag_valid_out[0][108]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9511 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06d")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9512 = mux(_T_9511, UInt<1>("h00"), ic_tag_valid_out[0][109]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9513 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06e")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9514 = mux(_T_9513, UInt<1>("h00"), ic_tag_valid_out[0][110]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9515 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06f")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9516 = mux(_T_9515, UInt<1>("h00"), ic_tag_valid_out[0][111]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9517 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h070")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9518 = mux(_T_9517, UInt<1>("h00"), ic_tag_valid_out[0][112]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9519 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h071")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9520 = mux(_T_9519, UInt<1>("h00"), ic_tag_valid_out[0][113]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9521 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h072")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9522 = mux(_T_9521, UInt<1>("h00"), ic_tag_valid_out[0][114]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9523 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h073")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9524 = mux(_T_9523, UInt<1>("h00"), ic_tag_valid_out[0][115]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9525 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h074")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9526 = mux(_T_9525, UInt<1>("h00"), ic_tag_valid_out[0][116]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9527 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h075")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9528 = mux(_T_9527, UInt<1>("h00"), ic_tag_valid_out[0][117]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9529 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h076")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9530 = mux(_T_9529, UInt<1>("h00"), ic_tag_valid_out[0][118]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9531 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h077")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9532 = mux(_T_9531, UInt<1>("h00"), ic_tag_valid_out[0][119]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9533 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h078")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9534 = mux(_T_9533, UInt<1>("h00"), ic_tag_valid_out[0][120]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9535 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h079")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9536 = mux(_T_9535, UInt<1>("h00"), ic_tag_valid_out[0][121]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9537 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07a")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9538 = mux(_T_9537, UInt<1>("h00"), ic_tag_valid_out[0][122]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9539 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07b")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9540 = mux(_T_9539, UInt<1>("h00"), ic_tag_valid_out[0][123]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9541 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07c")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9542 = mux(_T_9541, UInt<1>("h00"), ic_tag_valid_out[0][124]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9543 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07d")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9544 = mux(_T_9543, UInt<1>("h00"), ic_tag_valid_out[0][125]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9545 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07e")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9546 = mux(_T_9545, UInt<1>("h00"), ic_tag_valid_out[0][126]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9547 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07f")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9548 = mux(_T_9547, UInt<1>("h00"), ic_tag_valid_out[0][127]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9549 = or(_T_9294, _T_9296) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9550 = or(_T_9549, _T_9298) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9551 = or(_T_9550, _T_9300) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9552 = or(_T_9551, _T_9302) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9553 = or(_T_9552, _T_9304) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9554 = or(_T_9553, _T_9306) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9555 = or(_T_9554, _T_9308) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9556 = or(_T_9555, _T_9310) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9557 = or(_T_9556, _T_9312) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9558 = or(_T_9557, _T_9314) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9559 = or(_T_9558, _T_9316) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9560 = or(_T_9559, _T_9318) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9561 = or(_T_9560, _T_9320) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9562 = or(_T_9561, _T_9322) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9563 = or(_T_9562, _T_9324) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9564 = or(_T_9563, _T_9326) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9565 = or(_T_9564, _T_9328) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9566 = or(_T_9565, _T_9330) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9567 = or(_T_9566, _T_9332) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9568 = or(_T_9567, _T_9334) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9569 = or(_T_9568, _T_9336) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9570 = or(_T_9569, _T_9338) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9571 = or(_T_9570, _T_9340) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9572 = or(_T_9571, _T_9342) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9573 = or(_T_9572, _T_9344) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9574 = or(_T_9573, _T_9346) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9575 = or(_T_9574, _T_9348) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9576 = or(_T_9575, _T_9350) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9577 = or(_T_9576, _T_9352) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9578 = or(_T_9577, _T_9354) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9579 = or(_T_9578, _T_9356) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9580 = or(_T_9579, _T_9358) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9581 = or(_T_9580, _T_9360) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9582 = or(_T_9581, _T_9362) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9583 = or(_T_9582, _T_9364) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9584 = or(_T_9583, _T_9366) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9585 = or(_T_9584, _T_9368) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9586 = or(_T_9585, _T_9370) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9587 = or(_T_9586, _T_9372) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9588 = or(_T_9587, _T_9374) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9589 = or(_T_9588, _T_9376) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9590 = or(_T_9589, _T_9378) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9591 = or(_T_9590, _T_9380) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9592 = or(_T_9591, _T_9382) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9593 = or(_T_9592, _T_9384) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9594 = or(_T_9593, _T_9386) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9595 = or(_T_9594, _T_9388) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9596 = or(_T_9595, _T_9390) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9597 = or(_T_9596, _T_9392) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9598 = or(_T_9597, _T_9394) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9599 = or(_T_9598, _T_9396) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9600 = or(_T_9599, _T_9398) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9601 = or(_T_9600, _T_9400) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9602 = or(_T_9601, _T_9402) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9603 = or(_T_9602, _T_9404) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9604 = or(_T_9603, _T_9406) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9605 = or(_T_9604, _T_9408) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9606 = or(_T_9605, _T_9410) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9607 = or(_T_9606, _T_9412) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9608 = or(_T_9607, _T_9414) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9609 = or(_T_9608, _T_9416) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9610 = or(_T_9609, _T_9418) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9611 = or(_T_9610, _T_9420) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9612 = or(_T_9611, _T_9422) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9613 = or(_T_9612, _T_9424) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9614 = or(_T_9613, _T_9426) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9615 = or(_T_9614, _T_9428) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9616 = or(_T_9615, _T_9430) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9617 = or(_T_9616, _T_9432) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9618 = or(_T_9617, _T_9434) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9619 = or(_T_9618, _T_9436) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9620 = or(_T_9619, _T_9438) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9621 = or(_T_9620, _T_9440) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9622 = or(_T_9621, _T_9442) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9623 = or(_T_9622, _T_9444) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9624 = or(_T_9623, _T_9446) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9625 = or(_T_9624, _T_9448) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9626 = or(_T_9625, _T_9450) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9627 = or(_T_9626, _T_9452) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9628 = or(_T_9627, _T_9454) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9629 = or(_T_9628, _T_9456) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9630 = or(_T_9629, _T_9458) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9631 = or(_T_9630, _T_9460) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9632 = or(_T_9631, _T_9462) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9633 = or(_T_9632, _T_9464) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9634 = or(_T_9633, _T_9466) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9635 = or(_T_9634, _T_9468) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9636 = or(_T_9635, _T_9470) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9637 = or(_T_9636, _T_9472) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9638 = or(_T_9637, _T_9474) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9639 = or(_T_9638, _T_9476) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9640 = or(_T_9639, _T_9478) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9641 = or(_T_9640, _T_9480) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9642 = or(_T_9641, _T_9482) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9643 = or(_T_9642, _T_9484) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9644 = or(_T_9643, _T_9486) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9645 = or(_T_9644, _T_9488) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9646 = or(_T_9645, _T_9490) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9647 = or(_T_9646, _T_9492) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9648 = or(_T_9647, _T_9494) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9649 = or(_T_9648, _T_9496) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9650 = or(_T_9649, _T_9498) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9651 = or(_T_9650, _T_9500) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9652 = or(_T_9651, _T_9502) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9653 = or(_T_9652, _T_9504) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9654 = or(_T_9653, _T_9506) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9655 = or(_T_9654, _T_9508) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9656 = or(_T_9655, _T_9510) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9657 = or(_T_9656, _T_9512) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9658 = or(_T_9657, _T_9514) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9659 = or(_T_9658, _T_9516) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9660 = or(_T_9659, _T_9518) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9661 = or(_T_9660, _T_9520) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9662 = or(_T_9661, _T_9522) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9663 = or(_T_9662, _T_9524) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9664 = or(_T_9663, _T_9526) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9665 = or(_T_9664, _T_9528) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9666 = or(_T_9665, _T_9530) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9667 = or(_T_9666, _T_9532) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9668 = or(_T_9667, _T_9534) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9669 = or(_T_9668, _T_9536) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9670 = or(_T_9669, _T_9538) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9671 = or(_T_9670, _T_9540) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9672 = or(_T_9671, _T_9542) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9673 = or(_T_9672, _T_9544) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9674 = or(_T_9673, _T_9546) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9675 = or(_T_9674, _T_9548) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9676 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9677 = mux(_T_9676, UInt<1>("h00"), ic_tag_valid_out[1][0]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9678 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9679 = mux(_T_9678, UInt<1>("h00"), ic_tag_valid_out[1][1]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9680 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9681 = mux(_T_9680, UInt<1>("h00"), ic_tag_valid_out[1][2]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9682 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9683 = mux(_T_9682, UInt<1>("h00"), ic_tag_valid_out[1][3]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9684 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9685 = mux(_T_9684, UInt<1>("h00"), ic_tag_valid_out[1][4]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9686 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9687 = mux(_T_9686, UInt<1>("h00"), ic_tag_valid_out[1][5]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9688 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9689 = mux(_T_9688, UInt<1>("h00"), ic_tag_valid_out[1][6]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9690 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9691 = mux(_T_9690, UInt<1>("h00"), ic_tag_valid_out[1][7]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9692 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9693 = mux(_T_9692, UInt<1>("h00"), ic_tag_valid_out[1][8]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9694 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9695 = mux(_T_9694, UInt<1>("h00"), ic_tag_valid_out[1][9]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9696 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9697 = mux(_T_9696, UInt<1>("h00"), ic_tag_valid_out[1][10]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9698 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9699 = mux(_T_9698, UInt<1>("h00"), ic_tag_valid_out[1][11]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9700 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9701 = mux(_T_9700, UInt<1>("h00"), ic_tag_valid_out[1][12]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9702 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9703 = mux(_T_9702, UInt<1>("h00"), ic_tag_valid_out[1][13]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9704 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9705 = mux(_T_9704, UInt<1>("h00"), ic_tag_valid_out[1][14]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9706 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9707 = mux(_T_9706, UInt<1>("h00"), ic_tag_valid_out[1][15]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9708 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h010")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9709 = mux(_T_9708, UInt<1>("h00"), ic_tag_valid_out[1][16]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9710 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h011")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9711 = mux(_T_9710, UInt<1>("h00"), ic_tag_valid_out[1][17]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9712 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h012")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9713 = mux(_T_9712, UInt<1>("h00"), ic_tag_valid_out[1][18]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9714 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h013")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9715 = mux(_T_9714, UInt<1>("h00"), ic_tag_valid_out[1][19]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9716 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h014")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9717 = mux(_T_9716, UInt<1>("h00"), ic_tag_valid_out[1][20]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9718 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h015")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9719 = mux(_T_9718, UInt<1>("h00"), ic_tag_valid_out[1][21]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9720 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h016")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9721 = mux(_T_9720, UInt<1>("h00"), ic_tag_valid_out[1][22]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9722 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h017")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9723 = mux(_T_9722, UInt<1>("h00"), ic_tag_valid_out[1][23]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9724 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h018")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9725 = mux(_T_9724, UInt<1>("h00"), ic_tag_valid_out[1][24]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9726 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h019")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9727 = mux(_T_9726, UInt<1>("h00"), ic_tag_valid_out[1][25]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9728 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01a")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9729 = mux(_T_9728, UInt<1>("h00"), ic_tag_valid_out[1][26]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9730 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01b")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9731 = mux(_T_9730, UInt<1>("h00"), ic_tag_valid_out[1][27]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9732 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01c")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9733 = mux(_T_9732, UInt<1>("h00"), ic_tag_valid_out[1][28]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9734 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01d")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9735 = mux(_T_9734, UInt<1>("h00"), ic_tag_valid_out[1][29]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9736 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01e")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9737 = mux(_T_9736, UInt<1>("h00"), ic_tag_valid_out[1][30]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9738 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01f")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9739 = mux(_T_9738, UInt<1>("h00"), ic_tag_valid_out[1][31]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9740 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h020")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9741 = mux(_T_9740, UInt<1>("h00"), ic_tag_valid_out[1][32]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9742 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h021")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9743 = mux(_T_9742, UInt<1>("h00"), ic_tag_valid_out[1][33]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9744 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h022")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9745 = mux(_T_9744, UInt<1>("h00"), ic_tag_valid_out[1][34]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9746 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h023")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9747 = mux(_T_9746, UInt<1>("h00"), ic_tag_valid_out[1][35]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9748 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h024")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9749 = mux(_T_9748, UInt<1>("h00"), ic_tag_valid_out[1][36]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9750 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h025")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9751 = mux(_T_9750, UInt<1>("h00"), ic_tag_valid_out[1][37]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9752 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h026")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9753 = mux(_T_9752, UInt<1>("h00"), ic_tag_valid_out[1][38]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9754 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h027")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9755 = mux(_T_9754, UInt<1>("h00"), ic_tag_valid_out[1][39]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9756 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h028")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9757 = mux(_T_9756, UInt<1>("h00"), ic_tag_valid_out[1][40]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9758 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h029")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9759 = mux(_T_9758, UInt<1>("h00"), ic_tag_valid_out[1][41]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9760 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02a")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9761 = mux(_T_9760, UInt<1>("h00"), ic_tag_valid_out[1][42]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9762 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02b")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9763 = mux(_T_9762, UInt<1>("h00"), ic_tag_valid_out[1][43]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9764 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02c")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9765 = mux(_T_9764, UInt<1>("h00"), ic_tag_valid_out[1][44]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9766 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02d")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9767 = mux(_T_9766, UInt<1>("h00"), ic_tag_valid_out[1][45]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9768 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02e")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9769 = mux(_T_9768, UInt<1>("h00"), ic_tag_valid_out[1][46]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9770 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02f")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9771 = mux(_T_9770, UInt<1>("h00"), ic_tag_valid_out[1][47]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9772 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h030")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9773 = mux(_T_9772, UInt<1>("h00"), ic_tag_valid_out[1][48]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9774 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h031")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9775 = mux(_T_9774, UInt<1>("h00"), ic_tag_valid_out[1][49]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9776 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h032")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9777 = mux(_T_9776, UInt<1>("h00"), ic_tag_valid_out[1][50]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9778 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h033")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9779 = mux(_T_9778, UInt<1>("h00"), ic_tag_valid_out[1][51]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9780 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h034")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9781 = mux(_T_9780, UInt<1>("h00"), ic_tag_valid_out[1][52]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9782 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h035")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9783 = mux(_T_9782, UInt<1>("h00"), ic_tag_valid_out[1][53]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9784 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h036")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9785 = mux(_T_9784, UInt<1>("h00"), ic_tag_valid_out[1][54]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9786 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h037")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9787 = mux(_T_9786, UInt<1>("h00"), ic_tag_valid_out[1][55]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9788 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h038")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9789 = mux(_T_9788, UInt<1>("h00"), ic_tag_valid_out[1][56]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9790 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h039")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9791 = mux(_T_9790, UInt<1>("h00"), ic_tag_valid_out[1][57]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9792 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03a")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9793 = mux(_T_9792, UInt<1>("h00"), ic_tag_valid_out[1][58]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9794 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03b")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9795 = mux(_T_9794, UInt<1>("h00"), ic_tag_valid_out[1][59]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9796 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03c")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9797 = mux(_T_9796, UInt<1>("h00"), ic_tag_valid_out[1][60]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9798 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03d")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9799 = mux(_T_9798, UInt<1>("h00"), ic_tag_valid_out[1][61]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9800 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03e")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9801 = mux(_T_9800, UInt<1>("h00"), ic_tag_valid_out[1][62]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9802 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03f")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9803 = mux(_T_9802, UInt<1>("h00"), ic_tag_valid_out[1][63]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9804 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h040")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9805 = mux(_T_9804, UInt<1>("h00"), ic_tag_valid_out[1][64]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9806 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h041")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9807 = mux(_T_9806, UInt<1>("h00"), ic_tag_valid_out[1][65]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9808 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h042")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9809 = mux(_T_9808, UInt<1>("h00"), ic_tag_valid_out[1][66]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9810 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h043")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9811 = mux(_T_9810, UInt<1>("h00"), ic_tag_valid_out[1][67]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9812 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h044")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9813 = mux(_T_9812, UInt<1>("h00"), ic_tag_valid_out[1][68]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9814 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h045")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9815 = mux(_T_9814, UInt<1>("h00"), ic_tag_valid_out[1][69]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9816 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h046")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9817 = mux(_T_9816, UInt<1>("h00"), ic_tag_valid_out[1][70]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9818 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h047")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9819 = mux(_T_9818, UInt<1>("h00"), ic_tag_valid_out[1][71]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9820 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h048")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9821 = mux(_T_9820, UInt<1>("h00"), ic_tag_valid_out[1][72]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9822 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h049")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9823 = mux(_T_9822, UInt<1>("h00"), ic_tag_valid_out[1][73]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9824 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04a")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9825 = mux(_T_9824, UInt<1>("h00"), ic_tag_valid_out[1][74]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9826 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04b")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9827 = mux(_T_9826, UInt<1>("h00"), ic_tag_valid_out[1][75]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9828 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04c")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9829 = mux(_T_9828, UInt<1>("h00"), ic_tag_valid_out[1][76]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9830 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04d")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9831 = mux(_T_9830, UInt<1>("h00"), ic_tag_valid_out[1][77]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9832 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04e")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9833 = mux(_T_9832, UInt<1>("h00"), ic_tag_valid_out[1][78]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9834 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04f")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9835 = mux(_T_9834, UInt<1>("h00"), ic_tag_valid_out[1][79]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9836 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h050")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9837 = mux(_T_9836, UInt<1>("h00"), ic_tag_valid_out[1][80]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9838 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h051")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9839 = mux(_T_9838, UInt<1>("h00"), ic_tag_valid_out[1][81]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9840 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h052")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9841 = mux(_T_9840, UInt<1>("h00"), ic_tag_valid_out[1][82]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9842 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h053")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9843 = mux(_T_9842, UInt<1>("h00"), ic_tag_valid_out[1][83]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9844 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h054")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9845 = mux(_T_9844, UInt<1>("h00"), ic_tag_valid_out[1][84]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9846 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h055")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9847 = mux(_T_9846, UInt<1>("h00"), ic_tag_valid_out[1][85]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9848 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h056")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9849 = mux(_T_9848, UInt<1>("h00"), ic_tag_valid_out[1][86]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9850 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h057")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9851 = mux(_T_9850, UInt<1>("h00"), ic_tag_valid_out[1][87]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9852 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h058")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9853 = mux(_T_9852, UInt<1>("h00"), ic_tag_valid_out[1][88]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9854 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h059")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9855 = mux(_T_9854, UInt<1>("h00"), ic_tag_valid_out[1][89]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9856 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05a")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9857 = mux(_T_9856, UInt<1>("h00"), ic_tag_valid_out[1][90]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9858 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05b")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9859 = mux(_T_9858, UInt<1>("h00"), ic_tag_valid_out[1][91]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9860 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05c")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9861 = mux(_T_9860, UInt<1>("h00"), ic_tag_valid_out[1][92]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9862 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05d")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9863 = mux(_T_9862, UInt<1>("h00"), ic_tag_valid_out[1][93]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9864 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05e")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9865 = mux(_T_9864, UInt<1>("h00"), ic_tag_valid_out[1][94]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9866 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05f")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9867 = mux(_T_9866, UInt<1>("h00"), ic_tag_valid_out[1][95]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9868 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h060")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9869 = mux(_T_9868, UInt<1>("h00"), ic_tag_valid_out[1][96]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9870 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h061")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9871 = mux(_T_9870, UInt<1>("h00"), ic_tag_valid_out[1][97]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9872 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h062")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9873 = mux(_T_9872, UInt<1>("h00"), ic_tag_valid_out[1][98]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9874 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h063")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9875 = mux(_T_9874, UInt<1>("h00"), ic_tag_valid_out[1][99]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9876 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h064")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9877 = mux(_T_9876, UInt<1>("h00"), ic_tag_valid_out[1][100]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9878 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h065")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9879 = mux(_T_9878, UInt<1>("h00"), ic_tag_valid_out[1][101]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9880 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h066")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9881 = mux(_T_9880, UInt<1>("h00"), ic_tag_valid_out[1][102]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9882 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h067")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9883 = mux(_T_9882, UInt<1>("h00"), ic_tag_valid_out[1][103]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9884 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h068")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9885 = mux(_T_9884, UInt<1>("h00"), ic_tag_valid_out[1][104]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9886 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h069")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9887 = mux(_T_9886, UInt<1>("h00"), ic_tag_valid_out[1][105]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9888 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06a")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9889 = mux(_T_9888, UInt<1>("h00"), ic_tag_valid_out[1][106]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9890 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06b")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9891 = mux(_T_9890, UInt<1>("h00"), ic_tag_valid_out[1][107]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9892 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06c")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9893 = mux(_T_9892, UInt<1>("h00"), ic_tag_valid_out[1][108]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9894 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06d")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9895 = mux(_T_9894, UInt<1>("h00"), ic_tag_valid_out[1][109]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9896 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06e")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9897 = mux(_T_9896, UInt<1>("h00"), ic_tag_valid_out[1][110]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9898 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06f")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9899 = mux(_T_9898, UInt<1>("h00"), ic_tag_valid_out[1][111]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9900 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h070")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9901 = mux(_T_9900, UInt<1>("h00"), ic_tag_valid_out[1][112]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9902 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h071")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9903 = mux(_T_9902, UInt<1>("h00"), ic_tag_valid_out[1][113]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9904 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h072")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9905 = mux(_T_9904, UInt<1>("h00"), ic_tag_valid_out[1][114]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9906 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h073")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9907 = mux(_T_9906, UInt<1>("h00"), ic_tag_valid_out[1][115]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9908 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h074")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9909 = mux(_T_9908, UInt<1>("h00"), ic_tag_valid_out[1][116]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9910 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h075")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9911 = mux(_T_9910, UInt<1>("h00"), ic_tag_valid_out[1][117]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9912 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h076")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9913 = mux(_T_9912, UInt<1>("h00"), ic_tag_valid_out[1][118]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9914 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h077")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9915 = mux(_T_9914, UInt<1>("h00"), ic_tag_valid_out[1][119]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9916 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h078")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9917 = mux(_T_9916, UInt<1>("h00"), ic_tag_valid_out[1][120]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9918 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h079")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9919 = mux(_T_9918, UInt<1>("h00"), ic_tag_valid_out[1][121]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9920 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07a")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9921 = mux(_T_9920, UInt<1>("h00"), ic_tag_valid_out[1][122]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9922 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07b")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9923 = mux(_T_9922, UInt<1>("h00"), ic_tag_valid_out[1][123]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9924 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07c")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9925 = mux(_T_9924, UInt<1>("h00"), ic_tag_valid_out[1][124]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9926 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07d")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9927 = mux(_T_9926, UInt<1>("h00"), ic_tag_valid_out[1][125]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9928 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07e")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9929 = mux(_T_9928, UInt<1>("h00"), ic_tag_valid_out[1][126]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9930 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07f")) @[el2_ifu_mem_ctl.scala 745:33] + node _T_9931 = mux(_T_9930, UInt<1>("h00"), ic_tag_valid_out[1][127]) @[el2_ifu_mem_ctl.scala 745:10] + node _T_9932 = or(_T_9677, _T_9679) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9933 = or(_T_9932, _T_9681) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9934 = or(_T_9933, _T_9683) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9935 = or(_T_9934, _T_9685) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9936 = or(_T_9935, _T_9687) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9937 = or(_T_9936, _T_9689) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9938 = or(_T_9937, _T_9691) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9939 = or(_T_9938, _T_9693) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9940 = or(_T_9939, _T_9695) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9941 = or(_T_9940, _T_9697) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9942 = or(_T_9941, _T_9699) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9943 = or(_T_9942, _T_9701) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9944 = or(_T_9943, _T_9703) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9945 = or(_T_9944, _T_9705) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9946 = or(_T_9945, _T_9707) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9947 = or(_T_9946, _T_9709) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9948 = or(_T_9947, _T_9711) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9949 = or(_T_9948, _T_9713) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9950 = or(_T_9949, _T_9715) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9951 = or(_T_9950, _T_9717) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9952 = or(_T_9951, _T_9719) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9953 = or(_T_9952, _T_9721) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9954 = or(_T_9953, _T_9723) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9955 = or(_T_9954, _T_9725) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9956 = or(_T_9955, _T_9727) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9957 = or(_T_9956, _T_9729) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9958 = or(_T_9957, _T_9731) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9959 = or(_T_9958, _T_9733) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9960 = or(_T_9959, _T_9735) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9961 = or(_T_9960, _T_9737) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9962 = or(_T_9961, _T_9739) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9963 = or(_T_9962, _T_9741) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9964 = or(_T_9963, _T_9743) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9965 = or(_T_9964, _T_9745) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9966 = or(_T_9965, _T_9747) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9967 = or(_T_9966, _T_9749) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9968 = or(_T_9967, _T_9751) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9969 = or(_T_9968, _T_9753) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9970 = or(_T_9969, _T_9755) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9971 = or(_T_9970, _T_9757) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9972 = or(_T_9971, _T_9759) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9973 = or(_T_9972, _T_9761) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9974 = or(_T_9973, _T_9763) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9975 = or(_T_9974, _T_9765) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9976 = or(_T_9975, _T_9767) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9977 = or(_T_9976, _T_9769) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9978 = or(_T_9977, _T_9771) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9979 = or(_T_9978, _T_9773) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9980 = or(_T_9979, _T_9775) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9981 = or(_T_9980, _T_9777) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9982 = or(_T_9981, _T_9779) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9983 = or(_T_9982, _T_9781) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9984 = or(_T_9983, _T_9783) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9985 = or(_T_9984, _T_9785) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9986 = or(_T_9985, _T_9787) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9987 = or(_T_9986, _T_9789) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9988 = or(_T_9987, _T_9791) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9989 = or(_T_9988, _T_9793) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9990 = or(_T_9989, _T_9795) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9991 = or(_T_9990, _T_9797) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9992 = or(_T_9991, _T_9799) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9993 = or(_T_9992, _T_9801) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9994 = or(_T_9993, _T_9803) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9995 = or(_T_9994, _T_9805) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9996 = or(_T_9995, _T_9807) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9997 = or(_T_9996, _T_9809) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9998 = or(_T_9997, _T_9811) @[el2_ifu_mem_ctl.scala 745:91] + node _T_9999 = or(_T_9998, _T_9813) @[el2_ifu_mem_ctl.scala 745:91] + node _T_10000 = or(_T_9999, _T_9815) @[el2_ifu_mem_ctl.scala 745:91] + node _T_10001 = or(_T_10000, _T_9817) @[el2_ifu_mem_ctl.scala 745:91] + node _T_10002 = or(_T_10001, _T_9819) @[el2_ifu_mem_ctl.scala 745:91] + node _T_10003 = or(_T_10002, _T_9821) @[el2_ifu_mem_ctl.scala 745:91] + node _T_10004 = or(_T_10003, _T_9823) @[el2_ifu_mem_ctl.scala 745:91] + node _T_10005 = or(_T_10004, _T_9825) @[el2_ifu_mem_ctl.scala 745:91] + node _T_10006 = or(_T_10005, _T_9827) @[el2_ifu_mem_ctl.scala 745:91] + node _T_10007 = or(_T_10006, _T_9829) @[el2_ifu_mem_ctl.scala 745:91] + node _T_10008 = or(_T_10007, _T_9831) @[el2_ifu_mem_ctl.scala 745:91] + node _T_10009 = or(_T_10008, _T_9833) @[el2_ifu_mem_ctl.scala 745:91] + node _T_10010 = or(_T_10009, _T_9835) @[el2_ifu_mem_ctl.scala 745:91] + node _T_10011 = or(_T_10010, _T_9837) @[el2_ifu_mem_ctl.scala 745:91] + node _T_10012 = or(_T_10011, _T_9839) @[el2_ifu_mem_ctl.scala 745:91] + node _T_10013 = or(_T_10012, _T_9841) @[el2_ifu_mem_ctl.scala 745:91] + node _T_10014 = or(_T_10013, _T_9843) @[el2_ifu_mem_ctl.scala 745:91] + node _T_10015 = or(_T_10014, _T_9845) @[el2_ifu_mem_ctl.scala 745:91] + node _T_10016 = or(_T_10015, _T_9847) @[el2_ifu_mem_ctl.scala 745:91] + node _T_10017 = or(_T_10016, _T_9849) @[el2_ifu_mem_ctl.scala 745:91] + node _T_10018 = or(_T_10017, _T_9851) @[el2_ifu_mem_ctl.scala 745:91] + node _T_10019 = or(_T_10018, _T_9853) @[el2_ifu_mem_ctl.scala 745:91] + node _T_10020 = or(_T_10019, _T_9855) @[el2_ifu_mem_ctl.scala 745:91] + node _T_10021 = or(_T_10020, _T_9857) @[el2_ifu_mem_ctl.scala 745:91] + node _T_10022 = or(_T_10021, _T_9859) @[el2_ifu_mem_ctl.scala 745:91] + node _T_10023 = or(_T_10022, _T_9861) @[el2_ifu_mem_ctl.scala 745:91] + node _T_10024 = or(_T_10023, _T_9863) @[el2_ifu_mem_ctl.scala 745:91] + node _T_10025 = or(_T_10024, _T_9865) @[el2_ifu_mem_ctl.scala 745:91] + node _T_10026 = or(_T_10025, _T_9867) @[el2_ifu_mem_ctl.scala 745:91] + node _T_10027 = or(_T_10026, _T_9869) @[el2_ifu_mem_ctl.scala 745:91] + node _T_10028 = or(_T_10027, _T_9871) @[el2_ifu_mem_ctl.scala 745:91] + node _T_10029 = or(_T_10028, _T_9873) @[el2_ifu_mem_ctl.scala 745:91] + node _T_10030 = or(_T_10029, _T_9875) @[el2_ifu_mem_ctl.scala 745:91] + node _T_10031 = or(_T_10030, _T_9877) @[el2_ifu_mem_ctl.scala 745:91] + node _T_10032 = or(_T_10031, _T_9879) @[el2_ifu_mem_ctl.scala 745:91] + node _T_10033 = or(_T_10032, _T_9881) @[el2_ifu_mem_ctl.scala 745:91] + node _T_10034 = or(_T_10033, _T_9883) @[el2_ifu_mem_ctl.scala 745:91] + node _T_10035 = or(_T_10034, _T_9885) @[el2_ifu_mem_ctl.scala 745:91] + node _T_10036 = or(_T_10035, _T_9887) @[el2_ifu_mem_ctl.scala 745:91] + node _T_10037 = or(_T_10036, _T_9889) @[el2_ifu_mem_ctl.scala 745:91] + node _T_10038 = or(_T_10037, _T_9891) @[el2_ifu_mem_ctl.scala 745:91] + node _T_10039 = or(_T_10038, _T_9893) @[el2_ifu_mem_ctl.scala 745:91] + node _T_10040 = or(_T_10039, _T_9895) @[el2_ifu_mem_ctl.scala 745:91] + node _T_10041 = or(_T_10040, _T_9897) @[el2_ifu_mem_ctl.scala 745:91] + node _T_10042 = or(_T_10041, _T_9899) @[el2_ifu_mem_ctl.scala 745:91] + node _T_10043 = or(_T_10042, _T_9901) @[el2_ifu_mem_ctl.scala 745:91] + node _T_10044 = or(_T_10043, _T_9903) @[el2_ifu_mem_ctl.scala 745:91] + node _T_10045 = or(_T_10044, _T_9905) @[el2_ifu_mem_ctl.scala 745:91] + node _T_10046 = or(_T_10045, _T_9907) @[el2_ifu_mem_ctl.scala 745:91] + node _T_10047 = or(_T_10046, _T_9909) @[el2_ifu_mem_ctl.scala 745:91] + node _T_10048 = or(_T_10047, _T_9911) @[el2_ifu_mem_ctl.scala 745:91] + node _T_10049 = or(_T_10048, _T_9913) @[el2_ifu_mem_ctl.scala 745:91] + node _T_10050 = or(_T_10049, _T_9915) @[el2_ifu_mem_ctl.scala 745:91] + node _T_10051 = or(_T_10050, _T_9917) @[el2_ifu_mem_ctl.scala 745:91] + node _T_10052 = or(_T_10051, _T_9919) @[el2_ifu_mem_ctl.scala 745:91] + node _T_10053 = or(_T_10052, _T_9921) @[el2_ifu_mem_ctl.scala 745:91] + node _T_10054 = or(_T_10053, _T_9923) @[el2_ifu_mem_ctl.scala 745:91] + node _T_10055 = or(_T_10054, _T_9925) @[el2_ifu_mem_ctl.scala 745:91] + node _T_10056 = or(_T_10055, _T_9927) @[el2_ifu_mem_ctl.scala 745:91] + node _T_10057 = or(_T_10056, _T_9929) @[el2_ifu_mem_ctl.scala 745:91] + node _T_10058 = or(_T_10057, _T_9931) @[el2_ifu_mem_ctl.scala 745:91] node ic_tag_valid_unq = cat(_T_10058, _T_9675) @[Cat.scala 29:58] wire way_status_hit_new : UInt<1> way_status_hit_new <= UInt<1>("h00") - node _T_10059 = eq(way_status_mb_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 769:33] - node _T_10060 = bits(tagv_mb_ff, 0, 0) @[el2_ifu_mem_ctl.scala 769:63] - node _T_10061 = and(_T_10059, _T_10060) @[el2_ifu_mem_ctl.scala 769:51] - node _T_10062 = bits(tagv_mb_ff, 1, 1) @[el2_ifu_mem_ctl.scala 769:79] - node _T_10063 = and(_T_10061, _T_10062) @[el2_ifu_mem_ctl.scala 769:67] - node _T_10064 = bits(tagv_mb_ff, 0, 0) @[el2_ifu_mem_ctl.scala 769:97] - node _T_10065 = eq(_T_10064, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 769:86] - node _T_10066 = or(_T_10063, _T_10065) @[el2_ifu_mem_ctl.scala 769:84] - replace_way_mb_any[0] <= _T_10066 @[el2_ifu_mem_ctl.scala 769:29] - node _T_10067 = bits(tagv_mb_ff, 0, 0) @[el2_ifu_mem_ctl.scala 770:62] - node _T_10068 = and(way_status_mb_ff, _T_10067) @[el2_ifu_mem_ctl.scala 770:50] - node _T_10069 = bits(tagv_mb_ff, 1, 1) @[el2_ifu_mem_ctl.scala 770:78] - node _T_10070 = and(_T_10068, _T_10069) @[el2_ifu_mem_ctl.scala 770:66] - node _T_10071 = bits(tagv_mb_ff, 1, 1) @[el2_ifu_mem_ctl.scala 770:96] - node _T_10072 = eq(_T_10071, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 770:85] - node _T_10073 = bits(tagv_mb_ff, 0, 0) @[el2_ifu_mem_ctl.scala 770:112] - node _T_10074 = and(_T_10072, _T_10073) @[el2_ifu_mem_ctl.scala 770:100] - node _T_10075 = or(_T_10070, _T_10074) @[el2_ifu_mem_ctl.scala 770:83] - replace_way_mb_any[1] <= _T_10075 @[el2_ifu_mem_ctl.scala 770:29] - node _T_10076 = bits(io.ic_rd_hit, 0, 0) @[el2_ifu_mem_ctl.scala 771:41] - way_status_hit_new <= _T_10076 @[el2_ifu_mem_ctl.scala 771:26] - way_status_rep_new <= replace_way_mb_any[0] @[el2_ifu_mem_ctl.scala 772:26] - node _T_10077 = and(bus_ifu_wr_en_ff_q, last_beat) @[el2_ifu_mem_ctl.scala 774:47] - node _T_10078 = bits(_T_10077, 0, 0) @[el2_ifu_mem_ctl.scala 774:60] - node _T_10079 = mux(_T_10078, way_status_rep_new, way_status_hit_new) @[el2_ifu_mem_ctl.scala 774:26] - way_status_new <= _T_10079 @[el2_ifu_mem_ctl.scala 774:20] - node _T_10080 = and(bus_ifu_wr_en_ff_q, last_beat) @[el2_ifu_mem_ctl.scala 775:45] - node _T_10081 = or(_T_10080, ic_act_hit_f) @[el2_ifu_mem_ctl.scala 775:58] - way_status_wr_en <= _T_10081 @[el2_ifu_mem_ctl.scala 775:22] - node _T_10082 = and(bus_ifu_wr_en_ff_q, replace_way_mb_any[0]) @[el2_ifu_mem_ctl.scala 776:74] - node bus_wren_0 = and(_T_10082, miss_pending) @[el2_ifu_mem_ctl.scala 776:98] - node _T_10083 = and(bus_ifu_wr_en_ff_q, replace_way_mb_any[1]) @[el2_ifu_mem_ctl.scala 776:74] - node bus_wren_1 = and(_T_10083, miss_pending) @[el2_ifu_mem_ctl.scala 776:98] - node _T_10084 = and(bus_ifu_wr_en_ff_wo_err, replace_way_mb_any[0]) @[el2_ifu_mem_ctl.scala 778:84] - node _T_10085 = and(_T_10084, miss_pending) @[el2_ifu_mem_ctl.scala 778:108] - node bus_wren_last_0 = and(_T_10085, bus_last_data_beat) @[el2_ifu_mem_ctl.scala 778:123] - node _T_10086 = and(bus_ifu_wr_en_ff_wo_err, replace_way_mb_any[1]) @[el2_ifu_mem_ctl.scala 778:84] - node _T_10087 = and(_T_10086, miss_pending) @[el2_ifu_mem_ctl.scala 778:108] - node bus_wren_last_1 = and(_T_10087, bus_last_data_beat) @[el2_ifu_mem_ctl.scala 778:123] - node wren_reset_miss_0 = and(replace_way_mb_any[0], reset_tag_valid_for_miss) @[el2_ifu_mem_ctl.scala 779:84] - node wren_reset_miss_1 = and(replace_way_mb_any[1], reset_tag_valid_for_miss) @[el2_ifu_mem_ctl.scala 779:84] - node _T_10088 = or(bus_wren_last_0, wren_reset_miss_0) @[el2_ifu_mem_ctl.scala 780:73] - node _T_10089 = or(bus_wren_last_1, wren_reset_miss_1) @[el2_ifu_mem_ctl.scala 780:73] + node _T_10059 = eq(way_status_mb_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 770:33] + node _T_10060 = bits(tagv_mb_ff, 0, 0) @[el2_ifu_mem_ctl.scala 770:63] + node _T_10061 = and(_T_10059, _T_10060) @[el2_ifu_mem_ctl.scala 770:51] + node _T_10062 = bits(tagv_mb_ff, 1, 1) @[el2_ifu_mem_ctl.scala 770:79] + node _T_10063 = and(_T_10061, _T_10062) @[el2_ifu_mem_ctl.scala 770:67] + node _T_10064 = bits(tagv_mb_ff, 0, 0) @[el2_ifu_mem_ctl.scala 770:97] + node _T_10065 = eq(_T_10064, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 770:86] + node _T_10066 = or(_T_10063, _T_10065) @[el2_ifu_mem_ctl.scala 770:84] + replace_way_mb_any[0] <= _T_10066 @[el2_ifu_mem_ctl.scala 770:29] + node _T_10067 = bits(tagv_mb_ff, 0, 0) @[el2_ifu_mem_ctl.scala 771:62] + node _T_10068 = and(way_status_mb_ff, _T_10067) @[el2_ifu_mem_ctl.scala 771:50] + node _T_10069 = bits(tagv_mb_ff, 1, 1) @[el2_ifu_mem_ctl.scala 771:78] + node _T_10070 = and(_T_10068, _T_10069) @[el2_ifu_mem_ctl.scala 771:66] + node _T_10071 = bits(tagv_mb_ff, 1, 1) @[el2_ifu_mem_ctl.scala 771:96] + node _T_10072 = eq(_T_10071, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 771:85] + node _T_10073 = bits(tagv_mb_ff, 0, 0) @[el2_ifu_mem_ctl.scala 771:112] + node _T_10074 = and(_T_10072, _T_10073) @[el2_ifu_mem_ctl.scala 771:100] + node _T_10075 = or(_T_10070, _T_10074) @[el2_ifu_mem_ctl.scala 771:83] + replace_way_mb_any[1] <= _T_10075 @[el2_ifu_mem_ctl.scala 771:29] + node _T_10076 = bits(io.ic_rd_hit, 0, 0) @[el2_ifu_mem_ctl.scala 772:41] + way_status_hit_new <= _T_10076 @[el2_ifu_mem_ctl.scala 772:26] + way_status_rep_new <= replace_way_mb_any[0] @[el2_ifu_mem_ctl.scala 773:26] + node _T_10077 = and(bus_ifu_wr_en_ff_q, last_beat) @[el2_ifu_mem_ctl.scala 775:47] + node _T_10078 = bits(_T_10077, 0, 0) @[el2_ifu_mem_ctl.scala 775:60] + node _T_10079 = mux(_T_10078, way_status_rep_new, way_status_hit_new) @[el2_ifu_mem_ctl.scala 775:26] + way_status_new <= _T_10079 @[el2_ifu_mem_ctl.scala 775:20] + node _T_10080 = and(bus_ifu_wr_en_ff_q, last_beat) @[el2_ifu_mem_ctl.scala 776:45] + node _T_10081 = or(_T_10080, ic_act_hit_f) @[el2_ifu_mem_ctl.scala 776:58] + way_status_wr_en <= _T_10081 @[el2_ifu_mem_ctl.scala 776:22] + node _T_10082 = and(bus_ifu_wr_en_ff_q, replace_way_mb_any[0]) @[el2_ifu_mem_ctl.scala 777:74] + node bus_wren_0 = and(_T_10082, miss_pending) @[el2_ifu_mem_ctl.scala 777:98] + node _T_10083 = and(bus_ifu_wr_en_ff_q, replace_way_mb_any[1]) @[el2_ifu_mem_ctl.scala 777:74] + node bus_wren_1 = and(_T_10083, miss_pending) @[el2_ifu_mem_ctl.scala 777:98] + node _T_10084 = and(bus_ifu_wr_en_ff_wo_err, replace_way_mb_any[0]) @[el2_ifu_mem_ctl.scala 779:84] + node _T_10085 = and(_T_10084, miss_pending) @[el2_ifu_mem_ctl.scala 779:108] + node bus_wren_last_0 = and(_T_10085, bus_last_data_beat) @[el2_ifu_mem_ctl.scala 779:123] + node _T_10086 = and(bus_ifu_wr_en_ff_wo_err, replace_way_mb_any[1]) @[el2_ifu_mem_ctl.scala 779:84] + node _T_10087 = and(_T_10086, miss_pending) @[el2_ifu_mem_ctl.scala 779:108] + node bus_wren_last_1 = and(_T_10087, bus_last_data_beat) @[el2_ifu_mem_ctl.scala 779:123] + node wren_reset_miss_0 = and(replace_way_mb_any[0], reset_tag_valid_for_miss) @[el2_ifu_mem_ctl.scala 780:84] + node wren_reset_miss_1 = and(replace_way_mb_any[1], reset_tag_valid_for_miss) @[el2_ifu_mem_ctl.scala 780:84] + node _T_10088 = or(bus_wren_last_0, wren_reset_miss_0) @[el2_ifu_mem_ctl.scala 781:73] + node _T_10089 = or(bus_wren_last_1, wren_reset_miss_1) @[el2_ifu_mem_ctl.scala 781:73] node _T_10090 = cat(_T_10089, _T_10088) @[Cat.scala 29:58] - ifu_tag_wren <= _T_10090 @[el2_ifu_mem_ctl.scala 780:18] - node _T_10091 = eq(fetch_uncacheable_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 795:63] - node _T_10092 = and(_T_10091, ifc_fetch_req_f) @[el2_ifu_mem_ctl.scala 795:85] + ifu_tag_wren <= _T_10090 @[el2_ifu_mem_ctl.scala 781:18] + node _T_10091 = eq(fetch_uncacheable_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 796:63] + node _T_10092 = and(_T_10091, ifc_fetch_req_f) @[el2_ifu_mem_ctl.scala 796:85] node _T_10093 = bits(_T_10092, 0, 0) @[Bitwise.scala 72:15] node _T_10094 = mux(_T_10093, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_10095 = and(ic_tag_valid_unq, _T_10094) @[el2_ifu_mem_ctl.scala 795:39] - io.ic_tag_valid <= _T_10095 @[el2_ifu_mem_ctl.scala 795:19] + node _T_10095 = and(ic_tag_valid_unq, _T_10094) @[el2_ifu_mem_ctl.scala 796:39] + io.ic_tag_valid <= _T_10095 @[el2_ifu_mem_ctl.scala 796:19] wire ic_debug_rd_en_ff : UInt<1> ic_debug_rd_en_ff <= UInt<1>("h00") wire ic_debug_way_ff : UInt<2> ic_debug_way_ff <= UInt<1>("h00") node _T_10096 = bits(ic_debug_rd_en_ff, 0, 0) @[Bitwise.scala 72:15] node _T_10097 = mux(_T_10096, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_10098 = and(ic_debug_way_ff, _T_10097) @[el2_ifu_mem_ctl.scala 798:67] - node _T_10099 = and(ic_tag_valid_unq, _T_10098) @[el2_ifu_mem_ctl.scala 798:48] - node _T_10100 = orr(_T_10099) @[el2_ifu_mem_ctl.scala 798:115] - ic_debug_tag_val_rd_out <= _T_10100 @[el2_ifu_mem_ctl.scala 798:27] - reg _T_10101 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 800:57] - _T_10101 <= ic_act_miss_f @[el2_ifu_mem_ctl.scala 800:57] - io.ifu_pmu_ic_miss <= _T_10101 @[el2_ifu_mem_ctl.scala 800:22] - reg _T_10102 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 801:56] - _T_10102 <= ic_act_hit_f @[el2_ifu_mem_ctl.scala 801:56] - io.ifu_pmu_ic_hit <= _T_10102 @[el2_ifu_mem_ctl.scala 801:21] - reg _T_10103 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 802:59] - _T_10103 <= ifc_bus_acc_fault_f @[el2_ifu_mem_ctl.scala 802:59] - io.ifu_pmu_bus_error <= _T_10103 @[el2_ifu_mem_ctl.scala 802:24] - node _T_10104 = eq(ifu_bus_arready_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 803:80] - node _T_10105 = and(ifu_bus_arvalid_ff, _T_10104) @[el2_ifu_mem_ctl.scala 803:78] - node _T_10106 = and(_T_10105, miss_pending) @[el2_ifu_mem_ctl.scala 803:100] - reg _T_10107 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 803:58] - _T_10107 <= _T_10106 @[el2_ifu_mem_ctl.scala 803:58] - io.ifu_pmu_bus_busy <= _T_10107 @[el2_ifu_mem_ctl.scala 803:23] - reg _T_10108 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 804:58] - _T_10108 <= bus_cmd_sent @[el2_ifu_mem_ctl.scala 804:58] - io.ifu_pmu_bus_trxn <= _T_10108 @[el2_ifu_mem_ctl.scala 804:23] - io.ic_debug_addr <= io.dec_tlu_ic_diag_pkt.icache_dicawics @[el2_ifu_mem_ctl.scala 807:20] - node _T_10109 = bits(io.dec_tlu_ic_diag_pkt.icache_dicawics, 16, 16) @[el2_ifu_mem_ctl.scala 808:66] - io.ic_debug_tag_array <= _T_10109 @[el2_ifu_mem_ctl.scala 808:25] - io.ic_debug_rd_en <= io.dec_tlu_ic_diag_pkt.icache_rd_valid @[el2_ifu_mem_ctl.scala 809:21] - io.ic_debug_wr_en <= io.dec_tlu_ic_diag_pkt.icache_wr_valid @[el2_ifu_mem_ctl.scala 810:21] - node _T_10110 = bits(io.dec_tlu_ic_diag_pkt.icache_dicawics, 15, 14) @[el2_ifu_mem_ctl.scala 811:64] - node _T_10111 = eq(_T_10110, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 811:71] - node _T_10112 = bits(io.dec_tlu_ic_diag_pkt.icache_dicawics, 15, 14) @[el2_ifu_mem_ctl.scala 811:117] - node _T_10113 = eq(_T_10112, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 811:124] - node _T_10114 = bits(io.dec_tlu_ic_diag_pkt.icache_dicawics, 15, 14) @[el2_ifu_mem_ctl.scala 812:43] - node _T_10115 = eq(_T_10114, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 812:50] - node _T_10116 = bits(io.dec_tlu_ic_diag_pkt.icache_dicawics, 15, 14) @[el2_ifu_mem_ctl.scala 812:96] - node _T_10117 = eq(_T_10116, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 812:103] + node _T_10098 = and(ic_debug_way_ff, _T_10097) @[el2_ifu_mem_ctl.scala 799:67] + node _T_10099 = and(ic_tag_valid_unq, _T_10098) @[el2_ifu_mem_ctl.scala 799:48] + node _T_10100 = orr(_T_10099) @[el2_ifu_mem_ctl.scala 799:115] + ic_debug_tag_val_rd_out <= _T_10100 @[el2_ifu_mem_ctl.scala 799:27] + reg _T_10101 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 801:57] + _T_10101 <= ic_act_miss_f @[el2_ifu_mem_ctl.scala 801:57] + io.ifu_pmu_ic_miss <= _T_10101 @[el2_ifu_mem_ctl.scala 801:22] + reg _T_10102 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 802:56] + _T_10102 <= ic_act_hit_f @[el2_ifu_mem_ctl.scala 802:56] + io.ifu_pmu_ic_hit <= _T_10102 @[el2_ifu_mem_ctl.scala 802:21] + reg _T_10103 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 803:59] + _T_10103 <= ifc_bus_acc_fault_f @[el2_ifu_mem_ctl.scala 803:59] + io.ifu_pmu_bus_error <= _T_10103 @[el2_ifu_mem_ctl.scala 803:24] + node _T_10104 = eq(ifu_bus_arready_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 804:80] + node _T_10105 = and(ifu_bus_arvalid_ff, _T_10104) @[el2_ifu_mem_ctl.scala 804:78] + node _T_10106 = and(_T_10105, miss_pending) @[el2_ifu_mem_ctl.scala 804:100] + reg _T_10107 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 804:58] + _T_10107 <= _T_10106 @[el2_ifu_mem_ctl.scala 804:58] + io.ifu_pmu_bus_busy <= _T_10107 @[el2_ifu_mem_ctl.scala 804:23] + reg _T_10108 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 805:58] + _T_10108 <= bus_cmd_sent @[el2_ifu_mem_ctl.scala 805:58] + io.ifu_pmu_bus_trxn <= _T_10108 @[el2_ifu_mem_ctl.scala 805:23] + io.ic_debug_addr <= io.dec_tlu_ic_diag_pkt.icache_dicawics @[el2_ifu_mem_ctl.scala 808:20] + node _T_10109 = bits(io.dec_tlu_ic_diag_pkt.icache_dicawics, 16, 16) @[el2_ifu_mem_ctl.scala 809:66] + io.ic_debug_tag_array <= _T_10109 @[el2_ifu_mem_ctl.scala 809:25] + io.ic_debug_rd_en <= io.dec_tlu_ic_diag_pkt.icache_rd_valid @[el2_ifu_mem_ctl.scala 810:21] + io.ic_debug_wr_en <= io.dec_tlu_ic_diag_pkt.icache_wr_valid @[el2_ifu_mem_ctl.scala 811:21] + node _T_10110 = bits(io.dec_tlu_ic_diag_pkt.icache_dicawics, 15, 14) @[el2_ifu_mem_ctl.scala 812:64] + node _T_10111 = eq(_T_10110, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 812:71] + node _T_10112 = bits(io.dec_tlu_ic_diag_pkt.icache_dicawics, 15, 14) @[el2_ifu_mem_ctl.scala 812:117] + node _T_10113 = eq(_T_10112, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 812:124] + node _T_10114 = bits(io.dec_tlu_ic_diag_pkt.icache_dicawics, 15, 14) @[el2_ifu_mem_ctl.scala 813:43] + node _T_10115 = eq(_T_10114, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 813:50] + node _T_10116 = bits(io.dec_tlu_ic_diag_pkt.icache_dicawics, 15, 14) @[el2_ifu_mem_ctl.scala 813:96] + node _T_10117 = eq(_T_10116, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 813:103] node _T_10118 = cat(_T_10115, _T_10117) @[Cat.scala 29:58] node _T_10119 = cat(_T_10111, _T_10113) @[Cat.scala 29:58] node _T_10120 = cat(_T_10119, _T_10118) @[Cat.scala 29:58] - io.ic_debug_way <= _T_10120 @[el2_ifu_mem_ctl.scala 811:19] - node _T_10121 = and(io.ic_debug_wr_en, io.ic_debug_tag_array) @[el2_ifu_mem_ctl.scala 813:65] + io.ic_debug_way <= _T_10120 @[el2_ifu_mem_ctl.scala 812:19] + node _T_10121 = and(io.ic_debug_wr_en, io.ic_debug_tag_array) @[el2_ifu_mem_ctl.scala 814:65] node _T_10122 = bits(_T_10121, 0, 0) @[Bitwise.scala 72:15] node _T_10123 = mux(_T_10122, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_10124 = and(_T_10123, io.ic_debug_way) @[el2_ifu_mem_ctl.scala 813:90] - ic_debug_tag_wr_en <= _T_10124 @[el2_ifu_mem_ctl.scala 813:22] - node ic_debug_ict_array_sel_in = and(io.ic_debug_rd_en, io.ic_debug_tag_array) @[el2_ifu_mem_ctl.scala 814:53] - node _T_10125 = or(io.ic_debug_rd_en, io.ic_debug_wr_en) @[el2_ifu_mem_ctl.scala 815:72] + node _T_10124 = and(_T_10123, io.ic_debug_way) @[el2_ifu_mem_ctl.scala 814:90] + ic_debug_tag_wr_en <= _T_10124 @[el2_ifu_mem_ctl.scala 814:22] + node ic_debug_ict_array_sel_in = and(io.ic_debug_rd_en, io.ic_debug_tag_array) @[el2_ifu_mem_ctl.scala 815:53] + node _T_10125 = or(io.ic_debug_rd_en, io.ic_debug_wr_en) @[el2_ifu_mem_ctl.scala 816:72] reg _T_10126 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_10125 : @[Reg.scala 28:19] _T_10126 <= io.ic_debug_way @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_debug_way_ff <= _T_10126 @[el2_ifu_mem_ctl.scala 815:19] - node _T_10127 = or(io.ic_debug_rd_en, io.ic_debug_wr_en) @[el2_ifu_mem_ctl.scala 816:92] + ic_debug_way_ff <= _T_10126 @[el2_ifu_mem_ctl.scala 816:19] + node _T_10127 = or(io.ic_debug_rd_en, io.ic_debug_wr_en) @[el2_ifu_mem_ctl.scala 817:92] reg _T_10128 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_10127 : @[Reg.scala 28:19] _T_10128 <= ic_debug_ict_array_sel_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_debug_ict_array_sel_ff <= _T_10128 @[el2_ifu_mem_ctl.scala 816:29] - reg _T_10129 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 817:54] - _T_10129 <= io.ic_debug_rd_en @[el2_ifu_mem_ctl.scala 817:54] - ic_debug_rd_en_ff <= _T_10129 @[el2_ifu_mem_ctl.scala 817:21] - node _T_10130 = bits(ic_debug_rd_en_ff, 0, 0) @[el2_ifu_mem_ctl.scala 818:111] + ic_debug_ict_array_sel_ff <= _T_10128 @[el2_ifu_mem_ctl.scala 817:29] + reg _T_10129 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 818:54] + _T_10129 <= io.ic_debug_rd_en @[el2_ifu_mem_ctl.scala 818:54] + ic_debug_rd_en_ff <= _T_10129 @[el2_ifu_mem_ctl.scala 818:21] + node _T_10130 = bits(ic_debug_rd_en_ff, 0, 0) @[el2_ifu_mem_ctl.scala 819:111] reg _T_10131 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_10130 : @[Reg.scala 28:19] _T_10131 <= ic_debug_rd_en_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - io.ifu_ic_debug_rd_data_valid <= _T_10131 @[el2_ifu_mem_ctl.scala 818:33] + io.ifu_ic_debug_rd_data_valid <= _T_10131 @[el2_ifu_mem_ctl.scala 819:33] node _T_10132 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58] node _T_10133 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58] node _T_10134 = cat(_T_10133, _T_10132) @[Cat.scala 29:58] @@ -13386,62 +13386,62 @@ circuit el2_ifu_mem_ctl : node _T_10136 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 29:58] node _T_10137 = cat(_T_10136, _T_10135) @[Cat.scala 29:58] node _T_10138 = cat(_T_10137, _T_10134) @[Cat.scala 29:58] - node _T_10139 = orr(_T_10138) @[el2_ifu_mem_ctl.scala 819:213] + node _T_10139 = orr(_T_10138) @[el2_ifu_mem_ctl.scala 820:213] node _T_10140 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_10141 = or(_T_10140, UInt<31>("h07fffffff")) @[el2_ifu_mem_ctl.scala 820:62] - node _T_10142 = or(UInt<1>("h00"), UInt<31>("h07fffffff")) @[el2_ifu_mem_ctl.scala 820:110] - node _T_10143 = eq(_T_10141, _T_10142) @[el2_ifu_mem_ctl.scala 820:85] - node _T_10144 = and(UInt<1>("h01"), _T_10143) @[el2_ifu_mem_ctl.scala 820:27] - node _T_10145 = or(_T_10139, _T_10144) @[el2_ifu_mem_ctl.scala 819:216] + node _T_10141 = or(_T_10140, UInt<31>("h07fffffff")) @[el2_ifu_mem_ctl.scala 821:62] + node _T_10142 = or(UInt<1>("h00"), UInt<31>("h07fffffff")) @[el2_ifu_mem_ctl.scala 821:110] + node _T_10143 = eq(_T_10141, _T_10142) @[el2_ifu_mem_ctl.scala 821:85] + node _T_10144 = and(UInt<1>("h01"), _T_10143) @[el2_ifu_mem_ctl.scala 821:27] + node _T_10145 = or(_T_10139, _T_10144) @[el2_ifu_mem_ctl.scala 820:216] node _T_10146 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_10147 = or(_T_10146, UInt<30>("h03fffffff")) @[el2_ifu_mem_ctl.scala 821:62] - node _T_10148 = or(UInt<32>("h0c0000000"), UInt<30>("h03fffffff")) @[el2_ifu_mem_ctl.scala 821:110] - node _T_10149 = eq(_T_10147, _T_10148) @[el2_ifu_mem_ctl.scala 821:85] - node _T_10150 = and(UInt<1>("h01"), _T_10149) @[el2_ifu_mem_ctl.scala 821:27] - node _T_10151 = or(_T_10145, _T_10150) @[el2_ifu_mem_ctl.scala 820:134] + node _T_10147 = or(_T_10146, UInt<30>("h03fffffff")) @[el2_ifu_mem_ctl.scala 822:62] + node _T_10148 = or(UInt<32>("h0c0000000"), UInt<30>("h03fffffff")) @[el2_ifu_mem_ctl.scala 822:110] + node _T_10149 = eq(_T_10147, _T_10148) @[el2_ifu_mem_ctl.scala 822:85] + node _T_10150 = and(UInt<1>("h01"), _T_10149) @[el2_ifu_mem_ctl.scala 822:27] + node _T_10151 = or(_T_10145, _T_10150) @[el2_ifu_mem_ctl.scala 821:134] node _T_10152 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_10153 = or(_T_10152, UInt<29>("h01fffffff")) @[el2_ifu_mem_ctl.scala 822:62] - node _T_10154 = or(UInt<32>("h0a0000000"), UInt<29>("h01fffffff")) @[el2_ifu_mem_ctl.scala 822:110] - node _T_10155 = eq(_T_10153, _T_10154) @[el2_ifu_mem_ctl.scala 822:85] - node _T_10156 = and(UInt<1>("h01"), _T_10155) @[el2_ifu_mem_ctl.scala 822:27] - node _T_10157 = or(_T_10151, _T_10156) @[el2_ifu_mem_ctl.scala 821:134] + node _T_10153 = or(_T_10152, UInt<29>("h01fffffff")) @[el2_ifu_mem_ctl.scala 823:62] + node _T_10154 = or(UInt<32>("h0a0000000"), UInt<29>("h01fffffff")) @[el2_ifu_mem_ctl.scala 823:110] + node _T_10155 = eq(_T_10153, _T_10154) @[el2_ifu_mem_ctl.scala 823:85] + node _T_10156 = and(UInt<1>("h01"), _T_10155) @[el2_ifu_mem_ctl.scala 823:27] + node _T_10157 = or(_T_10151, _T_10156) @[el2_ifu_mem_ctl.scala 822:134] node _T_10158 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_10159 = or(_T_10158, UInt<28>("h0fffffff")) @[el2_ifu_mem_ctl.scala 823:62] - node _T_10160 = or(UInt<32>("h080000000"), UInt<28>("h0fffffff")) @[el2_ifu_mem_ctl.scala 823:110] - node _T_10161 = eq(_T_10159, _T_10160) @[el2_ifu_mem_ctl.scala 823:85] - node _T_10162 = and(UInt<1>("h01"), _T_10161) @[el2_ifu_mem_ctl.scala 823:27] - node _T_10163 = or(_T_10157, _T_10162) @[el2_ifu_mem_ctl.scala 822:134] + node _T_10159 = or(_T_10158, UInt<28>("h0fffffff")) @[el2_ifu_mem_ctl.scala 824:62] + node _T_10160 = or(UInt<32>("h080000000"), UInt<28>("h0fffffff")) @[el2_ifu_mem_ctl.scala 824:110] + node _T_10161 = eq(_T_10159, _T_10160) @[el2_ifu_mem_ctl.scala 824:85] + node _T_10162 = and(UInt<1>("h01"), _T_10161) @[el2_ifu_mem_ctl.scala 824:27] + node _T_10163 = or(_T_10157, _T_10162) @[el2_ifu_mem_ctl.scala 823:134] node _T_10164 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_10165 = or(_T_10164, UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 824:62] - node _T_10166 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 824:110] - node _T_10167 = eq(_T_10165, _T_10166) @[el2_ifu_mem_ctl.scala 824:85] - node _T_10168 = and(UInt<1>("h00"), _T_10167) @[el2_ifu_mem_ctl.scala 824:27] - node _T_10169 = or(_T_10163, _T_10168) @[el2_ifu_mem_ctl.scala 823:134] + node _T_10165 = or(_T_10164, UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 825:62] + node _T_10166 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 825:110] + node _T_10167 = eq(_T_10165, _T_10166) @[el2_ifu_mem_ctl.scala 825:85] + node _T_10168 = and(UInt<1>("h00"), _T_10167) @[el2_ifu_mem_ctl.scala 825:27] + node _T_10169 = or(_T_10163, _T_10168) @[el2_ifu_mem_ctl.scala 824:134] node _T_10170 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_10171 = or(_T_10170, UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 825:62] - node _T_10172 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 825:110] - node _T_10173 = eq(_T_10171, _T_10172) @[el2_ifu_mem_ctl.scala 825:85] - node _T_10174 = and(UInt<1>("h00"), _T_10173) @[el2_ifu_mem_ctl.scala 825:27] - node _T_10175 = or(_T_10169, _T_10174) @[el2_ifu_mem_ctl.scala 824:134] + node _T_10171 = or(_T_10170, UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 826:62] + node _T_10172 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 826:110] + node _T_10173 = eq(_T_10171, _T_10172) @[el2_ifu_mem_ctl.scala 826:85] + node _T_10174 = and(UInt<1>("h00"), _T_10173) @[el2_ifu_mem_ctl.scala 826:27] + node _T_10175 = or(_T_10169, _T_10174) @[el2_ifu_mem_ctl.scala 825:134] node _T_10176 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_10177 = or(_T_10176, UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 826:62] - node _T_10178 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 826:110] - node _T_10179 = eq(_T_10177, _T_10178) @[el2_ifu_mem_ctl.scala 826:85] - node _T_10180 = and(UInt<1>("h00"), _T_10179) @[el2_ifu_mem_ctl.scala 826:27] - node _T_10181 = or(_T_10175, _T_10180) @[el2_ifu_mem_ctl.scala 825:134] + node _T_10177 = or(_T_10176, UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 827:62] + node _T_10178 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 827:110] + node _T_10179 = eq(_T_10177, _T_10178) @[el2_ifu_mem_ctl.scala 827:85] + node _T_10180 = and(UInt<1>("h00"), _T_10179) @[el2_ifu_mem_ctl.scala 827:27] + node _T_10181 = or(_T_10175, _T_10180) @[el2_ifu_mem_ctl.scala 826:134] node _T_10182 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_10183 = or(_T_10182, UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 827:62] - node _T_10184 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 827:110] - node _T_10185 = eq(_T_10183, _T_10184) @[el2_ifu_mem_ctl.scala 827:85] - node _T_10186 = and(UInt<1>("h00"), _T_10185) @[el2_ifu_mem_ctl.scala 827:27] - node ifc_region_acc_okay = or(_T_10181, _T_10186) @[el2_ifu_mem_ctl.scala 826:134] - node _T_10187 = eq(io.ifc_iccm_access_bf, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 828:40] - node _T_10188 = eq(ifc_region_acc_okay, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 828:65] - node _T_10189 = and(_T_10187, _T_10188) @[el2_ifu_mem_ctl.scala 828:63] - node ifc_region_acc_fault_memory_bf = and(_T_10189, io.ifc_fetch_req_bf) @[el2_ifu_mem_ctl.scala 828:86] - node _T_10190 = or(io.ifc_region_acc_fault_bf, ifc_region_acc_fault_memory_bf) @[el2_ifu_mem_ctl.scala 829:63] - ifc_region_acc_fault_final_bf <= _T_10190 @[el2_ifu_mem_ctl.scala 829:33] - reg _T_10191 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 830:66] - _T_10191 <= ifc_region_acc_fault_memory_bf @[el2_ifu_mem_ctl.scala 830:66] - ifc_region_acc_fault_memory_f <= _T_10191 @[el2_ifu_mem_ctl.scala 830:33] + node _T_10183 = or(_T_10182, UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 828:62] + node _T_10184 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 828:110] + node _T_10185 = eq(_T_10183, _T_10184) @[el2_ifu_mem_ctl.scala 828:85] + node _T_10186 = and(UInt<1>("h00"), _T_10185) @[el2_ifu_mem_ctl.scala 828:27] + node ifc_region_acc_okay = or(_T_10181, _T_10186) @[el2_ifu_mem_ctl.scala 827:134] + node _T_10187 = eq(io.ifc_iccm_access_bf, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 829:40] + node _T_10188 = eq(ifc_region_acc_okay, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 829:65] + node _T_10189 = and(_T_10187, _T_10188) @[el2_ifu_mem_ctl.scala 829:63] + node ifc_region_acc_fault_memory_bf = and(_T_10189, io.ifc_fetch_req_bf) @[el2_ifu_mem_ctl.scala 829:86] + node _T_10190 = or(io.ifc_region_acc_fault_bf, ifc_region_acc_fault_memory_bf) @[el2_ifu_mem_ctl.scala 830:63] + ifc_region_acc_fault_final_bf <= _T_10190 @[el2_ifu_mem_ctl.scala 830:33] + reg _T_10191 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 831:66] + _T_10191 <= ifc_region_acc_fault_memory_bf @[el2_ifu_mem_ctl.scala 831:66] + ifc_region_acc_fault_memory_f <= _T_10191 @[el2_ifu_mem_ctl.scala 831:33] diff --git a/el2_ifu_mem_ctl.v b/el2_ifu_mem_ctl.v index 2f93cb65..35f8eb71 100644 --- a/el2_ifu_mem_ctl.v +++ b/el2_ifu_mem_ctl.v @@ -594,34 +594,34 @@ module el2_ifu_mem_ctl( reg [31:0] _RAND_468; `endif // RANDOMIZE_REG_INIT reg flush_final_f; // @[el2_ifu_mem_ctl.scala 180:30] - reg ifc_fetch_req_f_raw; // @[el2_ifu_mem_ctl.scala 315:36] - wire _T_317 = ~io_exu_flush_final; // @[el2_ifu_mem_ctl.scala 316:44] - wire ifc_fetch_req_f = ifc_fetch_req_f_raw & _T_317; // @[el2_ifu_mem_ctl.scala 316:42] + reg ifc_fetch_req_f_raw; // @[el2_ifu_mem_ctl.scala 316:36] + wire _T_317 = ~io_exu_flush_final; // @[el2_ifu_mem_ctl.scala 317:44] + wire ifc_fetch_req_f = ifc_fetch_req_f_raw & _T_317; // @[el2_ifu_mem_ctl.scala 317:42] reg [2:0] miss_state; // @[Reg.scala 27:20] - wire miss_pending = miss_state != 3'h0; // @[el2_ifu_mem_ctl.scala 248:30] - reg scnd_miss_req_q; // @[el2_ifu_mem_ctl.scala 540:52] - wire scnd_miss_req = scnd_miss_req_q & _T_317; // @[el2_ifu_mem_ctl.scala 542:36] + wire miss_pending = miss_state != 3'h0; // @[el2_ifu_mem_ctl.scala 249:30] + reg scnd_miss_req_q; // @[el2_ifu_mem_ctl.scala 541:52] + wire scnd_miss_req = scnd_miss_req_q & _T_317; // @[el2_ifu_mem_ctl.scala 543:36] wire debug_c1_clken = io_ic_debug_rd_en | io_ic_debug_wr_en; // @[el2_ifu_mem_ctl.scala 182:42] wire [3:0] ic_fetch_val_int_f = {2'h0,io_ic_fetch_val_f}; // @[Cat.scala 29:58] - reg [30:0] ifu_fetch_addr_int_f; // @[el2_ifu_mem_ctl.scala 303:34] - wire [4:0] _GEN_463 = {{1'd0}, ic_fetch_val_int_f}; // @[el2_ifu_mem_ctl.scala 657:53] - wire [4:0] ic_fetch_val_shift_right = _GEN_463 << ifu_fetch_addr_int_f[0]; // @[el2_ifu_mem_ctl.scala 657:53] - wire [1:0] _GEN_464 = {{1'd0}, _T_317}; // @[el2_ifu_mem_ctl.scala 660:91] - wire [1:0] _T_3069 = ic_fetch_val_shift_right[3:2] & _GEN_464; // @[el2_ifu_mem_ctl.scala 660:91] - reg ifc_iccm_access_f; // @[el2_ifu_mem_ctl.scala 317:31] - wire fetch_req_iccm_f = ifc_fetch_req_f & ifc_iccm_access_f; // @[el2_ifu_mem_ctl.scala 270:46] - wire [1:0] _GEN_465 = {{1'd0}, fetch_req_iccm_f}; // @[el2_ifu_mem_ctl.scala 660:113] - wire [1:0] _T_3070 = _T_3069 & _GEN_465; // @[el2_ifu_mem_ctl.scala 660:113] - reg iccm_dma_rvalid_in; // @[el2_ifu_mem_ctl.scala 646:59] - wire [1:0] _GEN_466 = {{1'd0}, iccm_dma_rvalid_in}; // @[el2_ifu_mem_ctl.scala 660:130] - wire [1:0] _T_3071 = _T_3070 | _GEN_466; // @[el2_ifu_mem_ctl.scala 660:130] - wire _T_3072 = ~io_dec_tlu_core_ecc_disable; // @[el2_ifu_mem_ctl.scala 660:154] - wire [1:0] _GEN_467 = {{1'd0}, _T_3072}; // @[el2_ifu_mem_ctl.scala 660:152] - wire [1:0] _T_3073 = _T_3071 & _GEN_467; // @[el2_ifu_mem_ctl.scala 660:152] - wire [1:0] _T_3062 = ic_fetch_val_shift_right[1:0] & _GEN_464; // @[el2_ifu_mem_ctl.scala 660:91] - wire [1:0] _T_3063 = _T_3062 & _GEN_465; // @[el2_ifu_mem_ctl.scala 660:113] - wire [1:0] _T_3064 = _T_3063 | _GEN_466; // @[el2_ifu_mem_ctl.scala 660:130] - wire [1:0] _T_3066 = _T_3064 & _GEN_467; // @[el2_ifu_mem_ctl.scala 660:152] + reg [30:0] ifu_fetch_addr_int_f; // @[el2_ifu_mem_ctl.scala 304:34] + wire [4:0] _GEN_463 = {{1'd0}, ic_fetch_val_int_f}; // @[el2_ifu_mem_ctl.scala 658:53] + wire [4:0] ic_fetch_val_shift_right = _GEN_463 << ifu_fetch_addr_int_f[0]; // @[el2_ifu_mem_ctl.scala 658:53] + wire [1:0] _GEN_464 = {{1'd0}, _T_317}; // @[el2_ifu_mem_ctl.scala 661:91] + wire [1:0] _T_3069 = ic_fetch_val_shift_right[3:2] & _GEN_464; // @[el2_ifu_mem_ctl.scala 661:91] + reg ifc_iccm_access_f; // @[el2_ifu_mem_ctl.scala 318:31] + wire fetch_req_iccm_f = ifc_fetch_req_f & ifc_iccm_access_f; // @[el2_ifu_mem_ctl.scala 271:46] + wire [1:0] _GEN_465 = {{1'd0}, fetch_req_iccm_f}; // @[el2_ifu_mem_ctl.scala 661:113] + wire [1:0] _T_3070 = _T_3069 & _GEN_465; // @[el2_ifu_mem_ctl.scala 661:113] + reg iccm_dma_rvalid_in; // @[el2_ifu_mem_ctl.scala 647:59] + wire [1:0] _GEN_466 = {{1'd0}, iccm_dma_rvalid_in}; // @[el2_ifu_mem_ctl.scala 661:130] + wire [1:0] _T_3071 = _T_3070 | _GEN_466; // @[el2_ifu_mem_ctl.scala 661:130] + wire _T_3072 = ~io_dec_tlu_core_ecc_disable; // @[el2_ifu_mem_ctl.scala 661:154] + wire [1:0] _GEN_467 = {{1'd0}, _T_3072}; // @[el2_ifu_mem_ctl.scala 661:152] + wire [1:0] _T_3073 = _T_3071 & _GEN_467; // @[el2_ifu_mem_ctl.scala 661:152] + wire [1:0] _T_3062 = ic_fetch_val_shift_right[1:0] & _GEN_464; // @[el2_ifu_mem_ctl.scala 661:91] + wire [1:0] _T_3063 = _T_3062 & _GEN_465; // @[el2_ifu_mem_ctl.scala 661:113] + wire [1:0] _T_3064 = _T_3063 | _GEN_466; // @[el2_ifu_mem_ctl.scala 661:130] + wire [1:0] _T_3066 = _T_3064 & _GEN_467; // @[el2_ifu_mem_ctl.scala 661:152] wire [3:0] iccm_ecc_word_enable = {_T_3073,_T_3066}; // @[Cat.scala 29:58] wire _T_3173 = ^io_iccm_rd_data_ecc[31:0]; // @[el2_lib.scala 301:30] wire _T_3174 = ^io_iccm_rd_data_ecc[38:32]; // @[el2_lib.scala 301:44] @@ -685,237 +685,237 @@ module el2_ifu_mem_ctl( wire _T_3674 = _T_3672 & _T_3670[6]; // @[el2_lib.scala 302:53] wire [1:0] iccm_single_ecc_error = {_T_3289,_T_3674}; // @[Cat.scala 29:58] wire _T_3 = |iccm_single_ecc_error; // @[el2_ifu_mem_ctl.scala 185:52] - reg dma_iccm_req_f; // @[el2_ifu_mem_ctl.scala 624:51] + reg dma_iccm_req_f; // @[el2_ifu_mem_ctl.scala 625:51] wire _T_6 = io_iccm_rd_ecc_single_err | io_ic_error_start; // @[el2_ifu_mem_ctl.scala 186:57] reg [2:0] perr_state; // @[Reg.scala 27:20] wire _T_7 = perr_state == 3'h4; // @[el2_ifu_mem_ctl.scala 187:54] - wire iccm_correct_ecc = perr_state == 3'h3; // @[el2_ifu_mem_ctl.scala 469:34] + wire iccm_correct_ecc = perr_state == 3'h3; // @[el2_ifu_mem_ctl.scala 470:34] wire _T_8 = iccm_correct_ecc | _T_7; // @[el2_ifu_mem_ctl.scala 187:40] reg [1:0] err_stop_state; // @[Reg.scala 27:20] wire _T_9 = err_stop_state == 2'h3; // @[el2_ifu_mem_ctl.scala 187:90] wire _T_10 = _T_8 | _T_9; // @[el2_ifu_mem_ctl.scala 187:72] wire _T_2438 = 2'h0 == err_stop_state; // @[Conditional.scala 37:30] wire _T_2443 = 2'h1 == err_stop_state; // @[Conditional.scala 37:30] - wire _T_2463 = io_ifu_fetch_val == 2'h3; // @[el2_ifu_mem_ctl.scala 519:48] - wire two_byte_instr = io_ic_data_f[1:0] != 2'h3; // @[el2_ifu_mem_ctl.scala 385:42] - wire _T_2465 = io_ifu_fetch_val[0] & two_byte_instr; // @[el2_ifu_mem_ctl.scala 519:79] - wire _T_2466 = _T_2463 | _T_2465; // @[el2_ifu_mem_ctl.scala 519:56] - wire _T_2467 = io_exu_flush_final | io_dec_tlu_i0_commit_cmt; // @[el2_ifu_mem_ctl.scala 519:122] - wire _T_2468 = ~_T_2467; // @[el2_ifu_mem_ctl.scala 519:101] - wire _T_2469 = _T_2466 & _T_2468; // @[el2_ifu_mem_ctl.scala 519:99] + wire _T_2463 = io_ifu_fetch_val == 2'h3; // @[el2_ifu_mem_ctl.scala 520:48] + wire two_byte_instr = io_ic_data_f[1:0] != 2'h3; // @[el2_ifu_mem_ctl.scala 386:42] + wire _T_2465 = io_ifu_fetch_val[0] & two_byte_instr; // @[el2_ifu_mem_ctl.scala 520:79] + wire _T_2466 = _T_2463 | _T_2465; // @[el2_ifu_mem_ctl.scala 520:56] + wire _T_2467 = io_exu_flush_final | io_dec_tlu_i0_commit_cmt; // @[el2_ifu_mem_ctl.scala 520:122] + wire _T_2468 = ~_T_2467; // @[el2_ifu_mem_ctl.scala 520:101] + wire _T_2469 = _T_2466 & _T_2468; // @[el2_ifu_mem_ctl.scala 520:99] wire _T_2470 = 2'h2 == err_stop_state; // @[Conditional.scala 37:30] - wire _T_2484 = io_ifu_fetch_val[0] & _T_317; // @[el2_ifu_mem_ctl.scala 526:45] - wire _T_2485 = ~io_dec_tlu_i0_commit_cmt; // @[el2_ifu_mem_ctl.scala 526:69] - wire _T_2486 = _T_2484 & _T_2485; // @[el2_ifu_mem_ctl.scala 526:67] + wire _T_2484 = io_ifu_fetch_val[0] & _T_317; // @[el2_ifu_mem_ctl.scala 527:45] + wire _T_2485 = ~io_dec_tlu_i0_commit_cmt; // @[el2_ifu_mem_ctl.scala 527:69] + wire _T_2486 = _T_2484 & _T_2485; // @[el2_ifu_mem_ctl.scala 527:67] wire _T_2487 = 2'h3 == err_stop_state; // @[Conditional.scala 37:30] wire _GEN_54 = _T_2470 ? _T_2486 : _T_2487; // @[Conditional.scala 39:67] wire _GEN_58 = _T_2443 ? _T_2469 : _GEN_54; // @[Conditional.scala 39:67] wire err_stop_fetch = _T_2438 ? 1'h0 : _GEN_58; // @[Conditional.scala 40:58] wire _T_11 = _T_10 | err_stop_fetch; // @[el2_ifu_mem_ctl.scala 187:112] - wire _T_13 = io_ifu_axi_rvalid & io_ifu_bus_clk_en; // @[el2_ifu_mem_ctl.scala 188:44] - wire _T_14 = _T_13 & io_ifu_axi_rready; // @[el2_ifu_mem_ctl.scala 188:65] - wire _T_227 = |io_ic_rd_hit; // @[el2_ifu_mem_ctl.scala 278:37] - wire _T_228 = ~_T_227; // @[el2_ifu_mem_ctl.scala 278:23] - reg reset_all_tags; // @[el2_ifu_mem_ctl.scala 692:53] - wire _T_229 = _T_228 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 278:41] - wire _T_207 = ~ifc_iccm_access_f; // @[el2_ifu_mem_ctl.scala 269:48] - wire _T_208 = ifc_fetch_req_f & _T_207; // @[el2_ifu_mem_ctl.scala 269:46] - reg ifc_region_acc_fault_final_f; // @[el2_ifu_mem_ctl.scala 319:42] - wire _T_209 = ~ifc_region_acc_fault_final_f; // @[el2_ifu_mem_ctl.scala 269:69] - wire fetch_req_icache_f = _T_208 & _T_209; // @[el2_ifu_mem_ctl.scala 269:67] - wire _T_230 = _T_229 & fetch_req_icache_f; // @[el2_ifu_mem_ctl.scala 278:59] - wire _T_231 = ~miss_pending; // @[el2_ifu_mem_ctl.scala 278:82] - wire _T_232 = _T_230 & _T_231; // @[el2_ifu_mem_ctl.scala 278:80] - wire _T_233 = _T_232 | scnd_miss_req; // @[el2_ifu_mem_ctl.scala 278:97] - wire ic_act_miss_f = _T_233 & _T_209; // @[el2_ifu_mem_ctl.scala 278:114] + wire _T_13 = io_ifu_axi_rvalid & io_ifu_bus_clk_en; // @[el2_ifu_mem_ctl.scala 189:44] + wire _T_14 = _T_13 & io_ifu_axi_rready; // @[el2_ifu_mem_ctl.scala 189:65] + wire _T_227 = |io_ic_rd_hit; // @[el2_ifu_mem_ctl.scala 279:37] + wire _T_228 = ~_T_227; // @[el2_ifu_mem_ctl.scala 279:23] + reg reset_all_tags; // @[el2_ifu_mem_ctl.scala 693:53] + wire _T_229 = _T_228 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 279:41] + wire _T_207 = ~ifc_iccm_access_f; // @[el2_ifu_mem_ctl.scala 270:48] + wire _T_208 = ifc_fetch_req_f & _T_207; // @[el2_ifu_mem_ctl.scala 270:46] + reg ifc_region_acc_fault_final_f; // @[el2_ifu_mem_ctl.scala 320:42] + wire _T_209 = ~ifc_region_acc_fault_final_f; // @[el2_ifu_mem_ctl.scala 270:69] + wire fetch_req_icache_f = _T_208 & _T_209; // @[el2_ifu_mem_ctl.scala 270:67] + wire _T_230 = _T_229 & fetch_req_icache_f; // @[el2_ifu_mem_ctl.scala 279:59] + wire _T_231 = ~miss_pending; // @[el2_ifu_mem_ctl.scala 279:82] + wire _T_232 = _T_230 & _T_231; // @[el2_ifu_mem_ctl.scala 279:80] + wire _T_233 = _T_232 | scnd_miss_req; // @[el2_ifu_mem_ctl.scala 279:97] + wire ic_act_miss_f = _T_233 & _T_209; // @[el2_ifu_mem_ctl.scala 279:114] reg ifu_bus_rvalid_unq_ff; // @[Reg.scala 27:20] - reg bus_ifu_bus_clk_en_ff; // @[el2_ifu_mem_ctl.scala 539:61] - wire ifu_bus_rvalid_ff = ifu_bus_rvalid_unq_ff & bus_ifu_bus_clk_en_ff; // @[el2_ifu_mem_ctl.scala 581:49] - wire bus_ifu_wr_en_ff = ifu_bus_rvalid_ff & miss_pending; // @[el2_ifu_mem_ctl.scala 608:41] - reg uncacheable_miss_ff; // @[el2_ifu_mem_ctl.scala 305:33] - reg [2:0] bus_data_beat_count; // @[el2_ifu_mem_ctl.scala 589:56] - wire _T_2589 = bus_data_beat_count == 3'h1; // @[el2_ifu_mem_ctl.scala 606:69] - wire _T_2590 = &bus_data_beat_count; // @[el2_ifu_mem_ctl.scala 606:101] - wire bus_last_data_beat = uncacheable_miss_ff ? _T_2589 : _T_2590; // @[el2_ifu_mem_ctl.scala 606:28] - wire _T_2536 = bus_ifu_wr_en_ff & bus_last_data_beat; // @[el2_ifu_mem_ctl.scala 585:68] - wire _T_2537 = ic_act_miss_f | _T_2536; // @[el2_ifu_mem_ctl.scala 585:48] - wire bus_reset_data_beat_cnt = _T_2537 | io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 585:91] - wire _T_2533 = ~bus_last_data_beat; // @[el2_ifu_mem_ctl.scala 584:50] - wire _T_2534 = bus_ifu_wr_en_ff & _T_2533; // @[el2_ifu_mem_ctl.scala 584:48] - wire _T_2535 = ~io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 584:72] - wire bus_inc_data_beat_cnt = _T_2534 & _T_2535; // @[el2_ifu_mem_ctl.scala 584:70] - wire [2:0] _T_2541 = bus_data_beat_count + 3'h1; // @[el2_ifu_mem_ctl.scala 588:115] + reg bus_ifu_bus_clk_en_ff; // @[el2_ifu_mem_ctl.scala 540:61] + wire ifu_bus_rvalid_ff = ifu_bus_rvalid_unq_ff & bus_ifu_bus_clk_en_ff; // @[el2_ifu_mem_ctl.scala 582:49] + wire bus_ifu_wr_en_ff = ifu_bus_rvalid_ff & miss_pending; // @[el2_ifu_mem_ctl.scala 609:41] + reg uncacheable_miss_ff; // @[el2_ifu_mem_ctl.scala 306:33] + reg [2:0] bus_data_beat_count; // @[el2_ifu_mem_ctl.scala 590:56] + wire _T_2589 = bus_data_beat_count == 3'h1; // @[el2_ifu_mem_ctl.scala 607:69] + wire _T_2590 = &bus_data_beat_count; // @[el2_ifu_mem_ctl.scala 607:101] + wire bus_last_data_beat = uncacheable_miss_ff ? _T_2589 : _T_2590; // @[el2_ifu_mem_ctl.scala 607:28] + wire _T_2536 = bus_ifu_wr_en_ff & bus_last_data_beat; // @[el2_ifu_mem_ctl.scala 586:68] + wire _T_2537 = ic_act_miss_f | _T_2536; // @[el2_ifu_mem_ctl.scala 586:48] + wire bus_reset_data_beat_cnt = _T_2537 | io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 586:91] + wire _T_2533 = ~bus_last_data_beat; // @[el2_ifu_mem_ctl.scala 585:50] + wire _T_2534 = bus_ifu_wr_en_ff & _T_2533; // @[el2_ifu_mem_ctl.scala 585:48] + wire _T_2535 = ~io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 585:72] + wire bus_inc_data_beat_cnt = _T_2534 & _T_2535; // @[el2_ifu_mem_ctl.scala 585:70] + wire [2:0] _T_2541 = bus_data_beat_count + 3'h1; // @[el2_ifu_mem_ctl.scala 589:115] wire [2:0] _T_2543 = bus_inc_data_beat_cnt ? _T_2541 : 3'h0; // @[Mux.scala 27:72] - wire _T_2538 = ~bus_inc_data_beat_cnt; // @[el2_ifu_mem_ctl.scala 586:32] - wire _T_2539 = ~bus_reset_data_beat_cnt; // @[el2_ifu_mem_ctl.scala 586:57] - wire bus_hold_data_beat_cnt = _T_2538 & _T_2539; // @[el2_ifu_mem_ctl.scala 586:55] + wire _T_2538 = ~bus_inc_data_beat_cnt; // @[el2_ifu_mem_ctl.scala 587:32] + wire _T_2539 = ~bus_reset_data_beat_cnt; // @[el2_ifu_mem_ctl.scala 587:57] + wire bus_hold_data_beat_cnt = _T_2538 & _T_2539; // @[el2_ifu_mem_ctl.scala 587:55] wire [2:0] _T_2544 = bus_hold_data_beat_cnt ? bus_data_beat_count : 3'h0; // @[Mux.scala 27:72] wire [2:0] bus_new_data_beat_count = _T_2543 | _T_2544; // @[Mux.scala 27:72] - wire _T_15 = &bus_new_data_beat_count; // @[el2_ifu_mem_ctl.scala 188:111] - wire _T_16 = _T_14 & _T_15; // @[el2_ifu_mem_ctl.scala 188:85] - wire _T_17 = ~uncacheable_miss_ff; // @[el2_ifu_mem_ctl.scala 189:5] - wire _T_18 = _T_16 & _T_17; // @[el2_ifu_mem_ctl.scala 188:116] - wire _T_19 = miss_state == 3'h5; // @[el2_ifu_mem_ctl.scala 189:41] + wire _T_15 = &bus_new_data_beat_count; // @[el2_ifu_mem_ctl.scala 189:112] + wire _T_16 = _T_14 & _T_15; // @[el2_ifu_mem_ctl.scala 189:85] + wire _T_17 = ~uncacheable_miss_ff; // @[el2_ifu_mem_ctl.scala 190:5] + wire _T_18 = _T_16 & _T_17; // @[el2_ifu_mem_ctl.scala 189:118] + wire _T_19 = miss_state == 3'h5; // @[el2_ifu_mem_ctl.scala 190:41] wire _T_24 = 3'h0 == miss_state; // @[Conditional.scala 37:30] - wire _T_26 = ic_act_miss_f & _T_317; // @[el2_ifu_mem_ctl.scala 195:43] - wire [2:0] _T_28 = _T_26 ? 3'h1 : 3'h2; // @[el2_ifu_mem_ctl.scala 195:27] + wire _T_26 = ic_act_miss_f & _T_317; // @[el2_ifu_mem_ctl.scala 196:43] + wire [2:0] _T_28 = _T_26 ? 3'h1 : 3'h2; // @[el2_ifu_mem_ctl.scala 196:27] wire _T_31 = 3'h1 == miss_state; // @[Conditional.scala 37:30] - wire [4:0] byp_fetch_index = ifu_fetch_addr_int_f[4:0]; // @[el2_ifu_mem_ctl.scala 421:45] - wire _T_2108 = byp_fetch_index[4:2] == 3'h0; // @[el2_ifu_mem_ctl.scala 442:127] - reg [7:0] ic_miss_buff_data_valid; // @[el2_ifu_mem_ctl.scala 398:60] + wire [4:0] byp_fetch_index = ifu_fetch_addr_int_f[4:0]; // @[el2_ifu_mem_ctl.scala 422:45] + wire _T_2108 = byp_fetch_index[4:2] == 3'h0; // @[el2_ifu_mem_ctl.scala 443:127] + reg [7:0] ic_miss_buff_data_valid; // @[el2_ifu_mem_ctl.scala 399:60] wire _T_2139 = _T_2108 & ic_miss_buff_data_valid[0]; // @[Mux.scala 27:72] - wire _T_2112 = byp_fetch_index[4:2] == 3'h1; // @[el2_ifu_mem_ctl.scala 442:127] + wire _T_2112 = byp_fetch_index[4:2] == 3'h1; // @[el2_ifu_mem_ctl.scala 443:127] wire _T_2140 = _T_2112 & ic_miss_buff_data_valid[1]; // @[Mux.scala 27:72] wire _T_2147 = _T_2139 | _T_2140; // @[Mux.scala 27:72] - wire _T_2116 = byp_fetch_index[4:2] == 3'h2; // @[el2_ifu_mem_ctl.scala 442:127] + wire _T_2116 = byp_fetch_index[4:2] == 3'h2; // @[el2_ifu_mem_ctl.scala 443:127] wire _T_2141 = _T_2116 & ic_miss_buff_data_valid[2]; // @[Mux.scala 27:72] wire _T_2148 = _T_2147 | _T_2141; // @[Mux.scala 27:72] - wire _T_2120 = byp_fetch_index[4:2] == 3'h3; // @[el2_ifu_mem_ctl.scala 442:127] + wire _T_2120 = byp_fetch_index[4:2] == 3'h3; // @[el2_ifu_mem_ctl.scala 443:127] wire _T_2142 = _T_2120 & ic_miss_buff_data_valid[3]; // @[Mux.scala 27:72] wire _T_2149 = _T_2148 | _T_2142; // @[Mux.scala 27:72] - wire _T_2124 = byp_fetch_index[4:2] == 3'h4; // @[el2_ifu_mem_ctl.scala 442:127] + wire _T_2124 = byp_fetch_index[4:2] == 3'h4; // @[el2_ifu_mem_ctl.scala 443:127] wire _T_2143 = _T_2124 & ic_miss_buff_data_valid[4]; // @[Mux.scala 27:72] wire _T_2150 = _T_2149 | _T_2143; // @[Mux.scala 27:72] - wire _T_2128 = byp_fetch_index[4:2] == 3'h5; // @[el2_ifu_mem_ctl.scala 442:127] + wire _T_2128 = byp_fetch_index[4:2] == 3'h5; // @[el2_ifu_mem_ctl.scala 443:127] wire _T_2144 = _T_2128 & ic_miss_buff_data_valid[5]; // @[Mux.scala 27:72] wire _T_2151 = _T_2150 | _T_2144; // @[Mux.scala 27:72] - wire _T_2132 = byp_fetch_index[4:2] == 3'h6; // @[el2_ifu_mem_ctl.scala 442:127] + wire _T_2132 = byp_fetch_index[4:2] == 3'h6; // @[el2_ifu_mem_ctl.scala 443:127] wire _T_2145 = _T_2132 & ic_miss_buff_data_valid[6]; // @[Mux.scala 27:72] wire _T_2152 = _T_2151 | _T_2145; // @[Mux.scala 27:72] - wire _T_2136 = byp_fetch_index[4:2] == 3'h7; // @[el2_ifu_mem_ctl.scala 442:127] + wire _T_2136 = byp_fetch_index[4:2] == 3'h7; // @[el2_ifu_mem_ctl.scala 443:127] wire _T_2146 = _T_2136 & ic_miss_buff_data_valid[7]; // @[Mux.scala 27:72] wire ic_miss_buff_data_valid_bypass_index = _T_2152 | _T_2146; // @[Mux.scala 27:72] - wire _T_2194 = ~byp_fetch_index[1]; // @[el2_ifu_mem_ctl.scala 444:69] - wire _T_2195 = ic_miss_buff_data_valid_bypass_index & _T_2194; // @[el2_ifu_mem_ctl.scala 444:67] - wire _T_2197 = ~byp_fetch_index[0]; // @[el2_ifu_mem_ctl.scala 444:91] - wire _T_2198 = _T_2195 & _T_2197; // @[el2_ifu_mem_ctl.scala 444:89] - wire _T_2203 = _T_2195 & byp_fetch_index[0]; // @[el2_ifu_mem_ctl.scala 445:65] - wire _T_2204 = _T_2198 | _T_2203; // @[el2_ifu_mem_ctl.scala 444:112] - wire _T_2206 = ic_miss_buff_data_valid_bypass_index & byp_fetch_index[1]; // @[el2_ifu_mem_ctl.scala 446:43] - wire _T_2209 = _T_2206 & _T_2197; // @[el2_ifu_mem_ctl.scala 446:65] - wire _T_2210 = _T_2204 | _T_2209; // @[el2_ifu_mem_ctl.scala 445:88] - wire _T_2214 = _T_2206 & byp_fetch_index[0]; // @[el2_ifu_mem_ctl.scala 447:65] - wire [2:0] byp_fetch_index_inc = ifu_fetch_addr_int_f[4:2] + 3'h1; // @[el2_ifu_mem_ctl.scala 424:75] - wire _T_2154 = byp_fetch_index_inc == 3'h0; // @[el2_ifu_mem_ctl.scala 443:110] + wire _T_2194 = ~byp_fetch_index[1]; // @[el2_ifu_mem_ctl.scala 445:69] + wire _T_2195 = ic_miss_buff_data_valid_bypass_index & _T_2194; // @[el2_ifu_mem_ctl.scala 445:67] + wire _T_2197 = ~byp_fetch_index[0]; // @[el2_ifu_mem_ctl.scala 445:91] + wire _T_2198 = _T_2195 & _T_2197; // @[el2_ifu_mem_ctl.scala 445:89] + wire _T_2203 = _T_2195 & byp_fetch_index[0]; // @[el2_ifu_mem_ctl.scala 446:65] + wire _T_2204 = _T_2198 | _T_2203; // @[el2_ifu_mem_ctl.scala 445:112] + wire _T_2206 = ic_miss_buff_data_valid_bypass_index & byp_fetch_index[1]; // @[el2_ifu_mem_ctl.scala 447:43] + wire _T_2209 = _T_2206 & _T_2197; // @[el2_ifu_mem_ctl.scala 447:65] + wire _T_2210 = _T_2204 | _T_2209; // @[el2_ifu_mem_ctl.scala 446:88] + wire _T_2214 = _T_2206 & byp_fetch_index[0]; // @[el2_ifu_mem_ctl.scala 448:65] + wire [2:0] byp_fetch_index_inc = ifu_fetch_addr_int_f[4:2] + 3'h1; // @[el2_ifu_mem_ctl.scala 425:75] + wire _T_2154 = byp_fetch_index_inc == 3'h0; // @[el2_ifu_mem_ctl.scala 444:110] wire _T_2178 = _T_2154 & ic_miss_buff_data_valid[0]; // @[Mux.scala 27:72] - wire _T_2157 = byp_fetch_index_inc == 3'h1; // @[el2_ifu_mem_ctl.scala 443:110] + wire _T_2157 = byp_fetch_index_inc == 3'h1; // @[el2_ifu_mem_ctl.scala 444:110] wire _T_2179 = _T_2157 & ic_miss_buff_data_valid[1]; // @[Mux.scala 27:72] wire _T_2186 = _T_2178 | _T_2179; // @[Mux.scala 27:72] - wire _T_2160 = byp_fetch_index_inc == 3'h2; // @[el2_ifu_mem_ctl.scala 443:110] + wire _T_2160 = byp_fetch_index_inc == 3'h2; // @[el2_ifu_mem_ctl.scala 444:110] wire _T_2180 = _T_2160 & ic_miss_buff_data_valid[2]; // @[Mux.scala 27:72] wire _T_2187 = _T_2186 | _T_2180; // @[Mux.scala 27:72] - wire _T_2163 = byp_fetch_index_inc == 3'h3; // @[el2_ifu_mem_ctl.scala 443:110] + wire _T_2163 = byp_fetch_index_inc == 3'h3; // @[el2_ifu_mem_ctl.scala 444:110] wire _T_2181 = _T_2163 & ic_miss_buff_data_valid[3]; // @[Mux.scala 27:72] wire _T_2188 = _T_2187 | _T_2181; // @[Mux.scala 27:72] - wire _T_2166 = byp_fetch_index_inc == 3'h4; // @[el2_ifu_mem_ctl.scala 443:110] + wire _T_2166 = byp_fetch_index_inc == 3'h4; // @[el2_ifu_mem_ctl.scala 444:110] wire _T_2182 = _T_2166 & ic_miss_buff_data_valid[4]; // @[Mux.scala 27:72] wire _T_2189 = _T_2188 | _T_2182; // @[Mux.scala 27:72] - wire _T_2169 = byp_fetch_index_inc == 3'h5; // @[el2_ifu_mem_ctl.scala 443:110] + wire _T_2169 = byp_fetch_index_inc == 3'h5; // @[el2_ifu_mem_ctl.scala 444:110] wire _T_2183 = _T_2169 & ic_miss_buff_data_valid[5]; // @[Mux.scala 27:72] wire _T_2190 = _T_2189 | _T_2183; // @[Mux.scala 27:72] - wire _T_2172 = byp_fetch_index_inc == 3'h6; // @[el2_ifu_mem_ctl.scala 443:110] + wire _T_2172 = byp_fetch_index_inc == 3'h6; // @[el2_ifu_mem_ctl.scala 444:110] wire _T_2184 = _T_2172 & ic_miss_buff_data_valid[6]; // @[Mux.scala 27:72] wire _T_2191 = _T_2190 | _T_2184; // @[Mux.scala 27:72] - wire _T_2175 = byp_fetch_index_inc == 3'h7; // @[el2_ifu_mem_ctl.scala 443:110] + wire _T_2175 = byp_fetch_index_inc == 3'h7; // @[el2_ifu_mem_ctl.scala 444:110] wire _T_2185 = _T_2175 & ic_miss_buff_data_valid[7]; // @[Mux.scala 27:72] wire ic_miss_buff_data_valid_inc_bypass_index = _T_2191 | _T_2185; // @[Mux.scala 27:72] - wire _T_2215 = _T_2214 & ic_miss_buff_data_valid_inc_bypass_index; // @[el2_ifu_mem_ctl.scala 447:87] - wire _T_2216 = _T_2210 | _T_2215; // @[el2_ifu_mem_ctl.scala 446:88] - wire _T_2220 = ic_miss_buff_data_valid_bypass_index & _T_2136; // @[el2_ifu_mem_ctl.scala 448:43] - wire miss_buff_hit_unq_f = _T_2216 | _T_2220; // @[el2_ifu_mem_ctl.scala 447:131] - wire _T_2236 = miss_state == 3'h4; // @[el2_ifu_mem_ctl.scala 453:55] - wire _T_2237 = miss_state == 3'h1; // @[el2_ifu_mem_ctl.scala 453:87] - wire _T_2238 = _T_2236 | _T_2237; // @[el2_ifu_mem_ctl.scala 453:74] - wire crit_byp_hit_f = miss_buff_hit_unq_f & _T_2238; // @[el2_ifu_mem_ctl.scala 453:41] - wire _T_2221 = miss_state == 3'h6; // @[el2_ifu_mem_ctl.scala 450:30] - reg [30:0] imb_ff; // @[el2_ifu_mem_ctl.scala 306:20] - wire miss_wrap_f = imb_ff[5] != ifu_fetch_addr_int_f[6]; // @[el2_ifu_mem_ctl.scala 441:51] - wire _T_2222 = ~miss_wrap_f; // @[el2_ifu_mem_ctl.scala 450:68] - wire _T_2223 = miss_buff_hit_unq_f & _T_2222; // @[el2_ifu_mem_ctl.scala 450:66] - wire stream_hit_f = _T_2221 & _T_2223; // @[el2_ifu_mem_ctl.scala 450:43] - wire _T_215 = crit_byp_hit_f | stream_hit_f; // @[el2_ifu_mem_ctl.scala 273:35] - wire _T_216 = _T_215 & fetch_req_icache_f; // @[el2_ifu_mem_ctl.scala 273:52] - wire ic_byp_hit_f = _T_216 & miss_pending; // @[el2_ifu_mem_ctl.scala 273:73] - reg last_data_recieved_ff; // @[el2_ifu_mem_ctl.scala 591:58] - wire last_beat = bus_last_data_beat & bus_ifu_wr_en_ff; // @[el2_ifu_mem_ctl.scala 618:35] - wire _T_32 = bus_ifu_wr_en_ff & last_beat; // @[el2_ifu_mem_ctl.scala 199:113] - wire _T_33 = last_data_recieved_ff | _T_32; // @[el2_ifu_mem_ctl.scala 199:93] - wire _T_34 = ic_byp_hit_f & _T_33; // @[el2_ifu_mem_ctl.scala 199:67] - wire _T_35 = _T_34 & uncacheable_miss_ff; // @[el2_ifu_mem_ctl.scala 199:127] - wire _T_36 = io_dec_tlu_force_halt | _T_35; // @[el2_ifu_mem_ctl.scala 199:51] - wire _T_38 = ~last_data_recieved_ff; // @[el2_ifu_mem_ctl.scala 200:30] - wire _T_39 = ic_byp_hit_f & _T_38; // @[el2_ifu_mem_ctl.scala 200:27] - wire _T_40 = _T_39 & uncacheable_miss_ff; // @[el2_ifu_mem_ctl.scala 200:53] - wire _T_42 = ~ic_byp_hit_f; // @[el2_ifu_mem_ctl.scala 201:16] - wire _T_44 = _T_42 & _T_317; // @[el2_ifu_mem_ctl.scala 201:30] - wire _T_46 = _T_44 & _T_32; // @[el2_ifu_mem_ctl.scala 201:52] - wire _T_47 = _T_46 & uncacheable_miss_ff; // @[el2_ifu_mem_ctl.scala 201:85] - wire _T_51 = _T_32 & _T_17; // @[el2_ifu_mem_ctl.scala 202:49] - wire _T_54 = ic_byp_hit_f & _T_317; // @[el2_ifu_mem_ctl.scala 203:33] - wire _T_56 = ~_T_32; // @[el2_ifu_mem_ctl.scala 203:57] - wire _T_57 = _T_54 & _T_56; // @[el2_ifu_mem_ctl.scala 203:55] - wire ifu_bp_hit_taken_q_f = io_ifu_bp_hit_taken_f & io_ic_hit_f; // @[el2_ifu_mem_ctl.scala 191:52] - wire _T_58 = ~ifu_bp_hit_taken_q_f; // @[el2_ifu_mem_ctl.scala 203:91] - wire _T_59 = _T_57 & _T_58; // @[el2_ifu_mem_ctl.scala 203:89] - wire _T_61 = _T_59 & _T_17; // @[el2_ifu_mem_ctl.scala 203:113] - wire _T_64 = bus_ifu_wr_en_ff & _T_317; // @[el2_ifu_mem_ctl.scala 204:39] - wire _T_67 = _T_64 & _T_56; // @[el2_ifu_mem_ctl.scala 204:61] - wire _T_69 = _T_67 & _T_58; // @[el2_ifu_mem_ctl.scala 204:95] - wire _T_71 = _T_69 & _T_17; // @[el2_ifu_mem_ctl.scala 204:119] - wire _T_79 = _T_46 & _T_17; // @[el2_ifu_mem_ctl.scala 205:100] - wire _T_81 = io_exu_flush_final | ifu_bp_hit_taken_q_f; // @[el2_ifu_mem_ctl.scala 206:44] - wire _T_84 = _T_81 & _T_56; // @[el2_ifu_mem_ctl.scala 206:68] - wire [2:0] _T_86 = _T_84 ? 3'h2 : 3'h0; // @[el2_ifu_mem_ctl.scala 206:22] - wire [2:0] _T_87 = _T_79 ? 3'h0 : _T_86; // @[el2_ifu_mem_ctl.scala 205:20] - wire [2:0] _T_88 = _T_71 ? 3'h6 : _T_87; // @[el2_ifu_mem_ctl.scala 204:20] - wire [2:0] _T_89 = _T_61 ? 3'h6 : _T_88; // @[el2_ifu_mem_ctl.scala 203:18] - wire [2:0] _T_90 = _T_51 ? 3'h0 : _T_89; // @[el2_ifu_mem_ctl.scala 202:16] - wire [2:0] _T_91 = _T_47 ? 3'h4 : _T_90; // @[el2_ifu_mem_ctl.scala 201:14] - wire [2:0] _T_92 = _T_40 ? 3'h3 : _T_91; // @[el2_ifu_mem_ctl.scala 200:12] - wire [2:0] _T_93 = _T_36 ? 3'h0 : _T_92; // @[el2_ifu_mem_ctl.scala 199:27] + wire _T_2215 = _T_2214 & ic_miss_buff_data_valid_inc_bypass_index; // @[el2_ifu_mem_ctl.scala 448:87] + wire _T_2216 = _T_2210 | _T_2215; // @[el2_ifu_mem_ctl.scala 447:88] + wire _T_2220 = ic_miss_buff_data_valid_bypass_index & _T_2136; // @[el2_ifu_mem_ctl.scala 449:43] + wire miss_buff_hit_unq_f = _T_2216 | _T_2220; // @[el2_ifu_mem_ctl.scala 448:131] + wire _T_2236 = miss_state == 3'h4; // @[el2_ifu_mem_ctl.scala 454:55] + wire _T_2237 = miss_state == 3'h1; // @[el2_ifu_mem_ctl.scala 454:87] + wire _T_2238 = _T_2236 | _T_2237; // @[el2_ifu_mem_ctl.scala 454:74] + wire crit_byp_hit_f = miss_buff_hit_unq_f & _T_2238; // @[el2_ifu_mem_ctl.scala 454:41] + wire _T_2221 = miss_state == 3'h6; // @[el2_ifu_mem_ctl.scala 451:30] + reg [30:0] imb_ff; // @[el2_ifu_mem_ctl.scala 307:20] + wire miss_wrap_f = imb_ff[5] != ifu_fetch_addr_int_f[6]; // @[el2_ifu_mem_ctl.scala 442:51] + wire _T_2222 = ~miss_wrap_f; // @[el2_ifu_mem_ctl.scala 451:68] + wire _T_2223 = miss_buff_hit_unq_f & _T_2222; // @[el2_ifu_mem_ctl.scala 451:66] + wire stream_hit_f = _T_2221 & _T_2223; // @[el2_ifu_mem_ctl.scala 451:43] + wire _T_215 = crit_byp_hit_f | stream_hit_f; // @[el2_ifu_mem_ctl.scala 274:35] + wire _T_216 = _T_215 & fetch_req_icache_f; // @[el2_ifu_mem_ctl.scala 274:52] + wire ic_byp_hit_f = _T_216 & miss_pending; // @[el2_ifu_mem_ctl.scala 274:73] + reg last_data_recieved_ff; // @[el2_ifu_mem_ctl.scala 592:58] + wire last_beat = bus_last_data_beat & bus_ifu_wr_en_ff; // @[el2_ifu_mem_ctl.scala 619:35] + wire _T_32 = bus_ifu_wr_en_ff & last_beat; // @[el2_ifu_mem_ctl.scala 200:113] + wire _T_33 = last_data_recieved_ff | _T_32; // @[el2_ifu_mem_ctl.scala 200:93] + wire _T_34 = ic_byp_hit_f & _T_33; // @[el2_ifu_mem_ctl.scala 200:67] + wire _T_35 = _T_34 & uncacheable_miss_ff; // @[el2_ifu_mem_ctl.scala 200:127] + wire _T_36 = io_dec_tlu_force_halt | _T_35; // @[el2_ifu_mem_ctl.scala 200:51] + wire _T_38 = ~last_data_recieved_ff; // @[el2_ifu_mem_ctl.scala 201:30] + wire _T_39 = ic_byp_hit_f & _T_38; // @[el2_ifu_mem_ctl.scala 201:27] + wire _T_40 = _T_39 & uncacheable_miss_ff; // @[el2_ifu_mem_ctl.scala 201:53] + wire _T_42 = ~ic_byp_hit_f; // @[el2_ifu_mem_ctl.scala 202:16] + wire _T_44 = _T_42 & _T_317; // @[el2_ifu_mem_ctl.scala 202:30] + wire _T_46 = _T_44 & _T_32; // @[el2_ifu_mem_ctl.scala 202:52] + wire _T_47 = _T_46 & uncacheable_miss_ff; // @[el2_ifu_mem_ctl.scala 202:85] + wire _T_51 = _T_32 & _T_17; // @[el2_ifu_mem_ctl.scala 203:49] + wire _T_54 = ic_byp_hit_f & _T_317; // @[el2_ifu_mem_ctl.scala 204:33] + wire _T_56 = ~_T_32; // @[el2_ifu_mem_ctl.scala 204:57] + wire _T_57 = _T_54 & _T_56; // @[el2_ifu_mem_ctl.scala 204:55] + wire ifu_bp_hit_taken_q_f = io_ifu_bp_hit_taken_f & io_ic_hit_f; // @[el2_ifu_mem_ctl.scala 192:52] + wire _T_58 = ~ifu_bp_hit_taken_q_f; // @[el2_ifu_mem_ctl.scala 204:91] + wire _T_59 = _T_57 & _T_58; // @[el2_ifu_mem_ctl.scala 204:89] + wire _T_61 = _T_59 & _T_17; // @[el2_ifu_mem_ctl.scala 204:113] + wire _T_64 = bus_ifu_wr_en_ff & _T_317; // @[el2_ifu_mem_ctl.scala 205:39] + wire _T_67 = _T_64 & _T_56; // @[el2_ifu_mem_ctl.scala 205:61] + wire _T_69 = _T_67 & _T_58; // @[el2_ifu_mem_ctl.scala 205:95] + wire _T_71 = _T_69 & _T_17; // @[el2_ifu_mem_ctl.scala 205:119] + wire _T_79 = _T_46 & _T_17; // @[el2_ifu_mem_ctl.scala 206:100] + wire _T_81 = io_exu_flush_final | ifu_bp_hit_taken_q_f; // @[el2_ifu_mem_ctl.scala 207:44] + wire _T_84 = _T_81 & _T_56; // @[el2_ifu_mem_ctl.scala 207:68] + wire [2:0] _T_86 = _T_84 ? 3'h2 : 3'h0; // @[el2_ifu_mem_ctl.scala 207:22] + wire [2:0] _T_87 = _T_79 ? 3'h0 : _T_86; // @[el2_ifu_mem_ctl.scala 206:20] + wire [2:0] _T_88 = _T_71 ? 3'h6 : _T_87; // @[el2_ifu_mem_ctl.scala 205:20] + wire [2:0] _T_89 = _T_61 ? 3'h6 : _T_88; // @[el2_ifu_mem_ctl.scala 204:18] + wire [2:0] _T_90 = _T_51 ? 3'h0 : _T_89; // @[el2_ifu_mem_ctl.scala 203:16] + wire [2:0] _T_91 = _T_47 ? 3'h4 : _T_90; // @[el2_ifu_mem_ctl.scala 202:14] + wire [2:0] _T_92 = _T_40 ? 3'h3 : _T_91; // @[el2_ifu_mem_ctl.scala 201:12] + wire [2:0] _T_93 = _T_36 ? 3'h0 : _T_92; // @[el2_ifu_mem_ctl.scala 200:27] wire _T_102 = 3'h4 == miss_state; // @[Conditional.scala 37:30] wire _T_106 = 3'h6 == miss_state; // @[Conditional.scala 37:30] - wire _T_2233 = byp_fetch_index[4:1] == 4'h7; // @[el2_ifu_mem_ctl.scala 452:60] - wire _T_2234 = _T_2233 & ifc_fetch_req_f; // @[el2_ifu_mem_ctl.scala 452:92] - wire stream_eol_f = _T_2234 & stream_hit_f; // @[el2_ifu_mem_ctl.scala 452:110] - wire _T_108 = _T_81 | stream_eol_f; // @[el2_ifu_mem_ctl.scala 214:72] - wire _T_111 = _T_108 & _T_56; // @[el2_ifu_mem_ctl.scala 214:87] - wire _T_113 = _T_111 & _T_2535; // @[el2_ifu_mem_ctl.scala 214:122] - wire [2:0] _T_115 = _T_113 ? 3'h2 : 3'h0; // @[el2_ifu_mem_ctl.scala 214:27] + wire _T_2233 = byp_fetch_index[4:1] == 4'h7; // @[el2_ifu_mem_ctl.scala 453:60] + wire _T_2234 = _T_2233 & ifc_fetch_req_f; // @[el2_ifu_mem_ctl.scala 453:92] + wire stream_eol_f = _T_2234 & stream_hit_f; // @[el2_ifu_mem_ctl.scala 453:110] + wire _T_108 = _T_81 | stream_eol_f; // @[el2_ifu_mem_ctl.scala 215:72] + wire _T_111 = _T_108 & _T_56; // @[el2_ifu_mem_ctl.scala 215:87] + wire _T_113 = _T_111 & _T_2535; // @[el2_ifu_mem_ctl.scala 215:122] + wire [2:0] _T_115 = _T_113 ? 3'h2 : 3'h0; // @[el2_ifu_mem_ctl.scala 215:27] wire _T_121 = 3'h3 == miss_state; // @[Conditional.scala 37:30] - wire _T_124 = io_exu_flush_final & _T_56; // @[el2_ifu_mem_ctl.scala 218:48] - wire _T_126 = _T_124 & _T_2535; // @[el2_ifu_mem_ctl.scala 218:82] - wire [2:0] _T_128 = _T_126 ? 3'h2 : 3'h0; // @[el2_ifu_mem_ctl.scala 218:27] + wire _T_124 = io_exu_flush_final & _T_56; // @[el2_ifu_mem_ctl.scala 219:48] + wire _T_126 = _T_124 & _T_2535; // @[el2_ifu_mem_ctl.scala 219:82] + wire [2:0] _T_128 = _T_126 ? 3'h2 : 3'h0; // @[el2_ifu_mem_ctl.scala 219:27] wire _T_132 = 3'h2 == miss_state; // @[Conditional.scala 37:30] - wire _T_236 = io_ic_rd_hit == 2'h0; // @[el2_ifu_mem_ctl.scala 279:28] - wire _T_237 = _T_236 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 279:42] - wire _T_238 = _T_237 & fetch_req_icache_f; // @[el2_ifu_mem_ctl.scala 279:60] - wire _T_239 = miss_state == 3'h2; // @[el2_ifu_mem_ctl.scala 279:94] - wire _T_240 = _T_238 & _T_239; // @[el2_ifu_mem_ctl.scala 279:81] - wire _T_243 = imb_ff[30:5] != ifu_fetch_addr_int_f[30:5]; // @[el2_ifu_mem_ctl.scala 280:39] - wire _T_244 = _T_240 & _T_243; // @[el2_ifu_mem_ctl.scala 279:111] - wire _T_246 = _T_244 & _T_17; // @[el2_ifu_mem_ctl.scala 280:91] - reg sel_mb_addr_ff; // @[el2_ifu_mem_ctl.scala 333:51] - wire _T_247 = ~sel_mb_addr_ff; // @[el2_ifu_mem_ctl.scala 280:116] - wire _T_248 = _T_246 & _T_247; // @[el2_ifu_mem_ctl.scala 280:114] - wire ic_miss_under_miss_f = _T_248 & _T_209; // @[el2_ifu_mem_ctl.scala 280:132] - wire _T_135 = ic_miss_under_miss_f & _T_56; // @[el2_ifu_mem_ctl.scala 222:50] - wire _T_137 = _T_135 & _T_2535; // @[el2_ifu_mem_ctl.scala 222:84] - wire _T_256 = _T_230 & _T_239; // @[el2_ifu_mem_ctl.scala 281:85] - wire _T_259 = imb_ff[30:5] == ifu_fetch_addr_int_f[30:5]; // @[el2_ifu_mem_ctl.scala 282:39] - wire _T_260 = _T_259 | uncacheable_miss_ff; // @[el2_ifu_mem_ctl.scala 282:91] - wire ic_ignore_2nd_miss_f = _T_256 & _T_260; // @[el2_ifu_mem_ctl.scala 281:117] - wire _T_141 = ic_ignore_2nd_miss_f & _T_56; // @[el2_ifu_mem_ctl.scala 223:35] - wire _T_143 = _T_141 & _T_2535; // @[el2_ifu_mem_ctl.scala 223:69] - wire [2:0] _T_145 = _T_143 ? 3'h7 : 3'h0; // @[el2_ifu_mem_ctl.scala 223:12] - wire [2:0] _T_146 = _T_137 ? 3'h5 : _T_145; // @[el2_ifu_mem_ctl.scala 222:27] + wire _T_236 = io_ic_rd_hit == 2'h0; // @[el2_ifu_mem_ctl.scala 280:28] + wire _T_237 = _T_236 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 280:42] + wire _T_238 = _T_237 & fetch_req_icache_f; // @[el2_ifu_mem_ctl.scala 280:60] + wire _T_239 = miss_state == 3'h2; // @[el2_ifu_mem_ctl.scala 280:94] + wire _T_240 = _T_238 & _T_239; // @[el2_ifu_mem_ctl.scala 280:81] + wire _T_243 = imb_ff[30:5] != ifu_fetch_addr_int_f[30:5]; // @[el2_ifu_mem_ctl.scala 281:39] + wire _T_244 = _T_240 & _T_243; // @[el2_ifu_mem_ctl.scala 280:111] + wire _T_246 = _T_244 & _T_17; // @[el2_ifu_mem_ctl.scala 281:91] + reg sel_mb_addr_ff; // @[el2_ifu_mem_ctl.scala 334:51] + wire _T_247 = ~sel_mb_addr_ff; // @[el2_ifu_mem_ctl.scala 281:116] + wire _T_248 = _T_246 & _T_247; // @[el2_ifu_mem_ctl.scala 281:114] + wire ic_miss_under_miss_f = _T_248 & _T_209; // @[el2_ifu_mem_ctl.scala 281:132] + wire _T_135 = ic_miss_under_miss_f & _T_56; // @[el2_ifu_mem_ctl.scala 223:50] + wire _T_137 = _T_135 & _T_2535; // @[el2_ifu_mem_ctl.scala 223:84] + wire _T_256 = _T_230 & _T_239; // @[el2_ifu_mem_ctl.scala 282:85] + wire _T_259 = imb_ff[30:5] == ifu_fetch_addr_int_f[30:5]; // @[el2_ifu_mem_ctl.scala 283:39] + wire _T_260 = _T_259 | uncacheable_miss_ff; // @[el2_ifu_mem_ctl.scala 283:91] + wire ic_ignore_2nd_miss_f = _T_256 & _T_260; // @[el2_ifu_mem_ctl.scala 282:117] + wire _T_141 = ic_ignore_2nd_miss_f & _T_56; // @[el2_ifu_mem_ctl.scala 224:35] + wire _T_143 = _T_141 & _T_2535; // @[el2_ifu_mem_ctl.scala 224:69] + wire [2:0] _T_145 = _T_143 ? 3'h7 : 3'h0; // @[el2_ifu_mem_ctl.scala 224:12] + wire [2:0] _T_146 = _T_137 ? 3'h5 : _T_145; // @[el2_ifu_mem_ctl.scala 223:27] wire _T_151 = 3'h5 == miss_state; // @[Conditional.scala 37:30] - wire [2:0] _T_154 = _T_32 ? 3'h0 : 3'h2; // @[el2_ifu_mem_ctl.scala 228:12] - wire [2:0] _T_155 = io_exu_flush_final ? _T_154 : 3'h1; // @[el2_ifu_mem_ctl.scala 227:62] - wire [2:0] _T_156 = io_dec_tlu_force_halt ? 3'h0 : _T_155; // @[el2_ifu_mem_ctl.scala 227:27] + wire [2:0] _T_154 = _T_32 ? 3'h0 : 3'h2; // @[el2_ifu_mem_ctl.scala 229:12] + wire [2:0] _T_155 = io_exu_flush_final ? _T_154 : 3'h1; // @[el2_ifu_mem_ctl.scala 228:62] + wire [2:0] _T_156 = io_dec_tlu_force_halt ? 3'h0 : _T_155; // @[el2_ifu_mem_ctl.scala 228:27] wire _T_160 = 3'h7 == miss_state; // @[Conditional.scala 37:30] - wire [2:0] _T_164 = io_exu_flush_final ? _T_154 : 3'h0; // @[el2_ifu_mem_ctl.scala 232:62] - wire [2:0] _T_165 = io_dec_tlu_force_halt ? 3'h0 : _T_164; // @[el2_ifu_mem_ctl.scala 232:27] + wire [2:0] _T_164 = io_exu_flush_final ? _T_154 : 3'h0; // @[el2_ifu_mem_ctl.scala 233:62] + wire [2:0] _T_165 = io_dec_tlu_force_halt ? 3'h0 : _T_164; // @[el2_ifu_mem_ctl.scala 233:27] wire [2:0] _GEN_0 = _T_160 ? _T_165 : 3'h0; // @[Conditional.scala 39:67] wire [2:0] _GEN_2 = _T_151 ? _T_156 : _GEN_0; // @[Conditional.scala 39:67] wire [2:0] _GEN_4 = _T_132 ? _T_146 : _GEN_2; // @[Conditional.scala 39:67] @@ -924,29 +924,29 @@ module el2_ifu_mem_ctl( wire [2:0] _GEN_10 = _T_102 ? 3'h0 : _GEN_8; // @[Conditional.scala 39:67] wire [2:0] _GEN_12 = _T_31 ? _T_93 : _GEN_10; // @[Conditional.scala 39:67] wire [2:0] miss_nxtstate = _T_24 ? _T_28 : _GEN_12; // @[Conditional.scala 40:58] - wire _T_20 = miss_nxtstate == 3'h5; // @[el2_ifu_mem_ctl.scala 189:73] - wire _T_21 = _T_19 | _T_20; // @[el2_ifu_mem_ctl.scala 189:57] - wire _T_22 = _T_18 & _T_21; // @[el2_ifu_mem_ctl.scala 189:26] - wire scnd_miss_req_in = _T_22 & _T_317; // @[el2_ifu_mem_ctl.scala 189:91] - wire _T_30 = ic_act_miss_f & _T_2535; // @[el2_ifu_mem_ctl.scala 196:38] - wire _T_94 = io_dec_tlu_force_halt | io_exu_flush_final; // @[el2_ifu_mem_ctl.scala 207:46] - wire _T_95 = _T_94 | ic_byp_hit_f; // @[el2_ifu_mem_ctl.scala 207:67] - wire _T_96 = _T_95 | ifu_bp_hit_taken_q_f; // @[el2_ifu_mem_ctl.scala 207:82] - wire _T_98 = _T_96 | _T_32; // @[el2_ifu_mem_ctl.scala 207:105] - wire _T_100 = bus_ifu_wr_en_ff & _T_17; // @[el2_ifu_mem_ctl.scala 207:158] - wire _T_101 = _T_98 | _T_100; // @[el2_ifu_mem_ctl.scala 207:138] - wire _T_103 = io_exu_flush_final | flush_final_f; // @[el2_ifu_mem_ctl.scala 211:43] - wire _T_104 = _T_103 | ic_byp_hit_f; // @[el2_ifu_mem_ctl.scala 211:59] - wire _T_105 = _T_104 | io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 211:74] - wire _T_119 = _T_108 | _T_32; // @[el2_ifu_mem_ctl.scala 215:84] - wire _T_120 = _T_119 | io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 215:118] - wire _T_130 = io_exu_flush_final | _T_32; // @[el2_ifu_mem_ctl.scala 219:43] - wire _T_131 = _T_130 | io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 219:76] - wire _T_148 = _T_32 | ic_miss_under_miss_f; // @[el2_ifu_mem_ctl.scala 224:55] - wire _T_149 = _T_148 | ic_ignore_2nd_miss_f; // @[el2_ifu_mem_ctl.scala 224:78] - wire _T_150 = _T_149 | io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 224:101] - wire _T_158 = _T_32 | io_exu_flush_final; // @[el2_ifu_mem_ctl.scala 229:55] - wire _T_159 = _T_158 | io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 229:76] + wire _T_20 = miss_nxtstate == 3'h5; // @[el2_ifu_mem_ctl.scala 190:73] + wire _T_21 = _T_19 | _T_20; // @[el2_ifu_mem_ctl.scala 190:57] + wire _T_22 = _T_18 & _T_21; // @[el2_ifu_mem_ctl.scala 190:26] + wire scnd_miss_req_in = _T_22 & _T_317; // @[el2_ifu_mem_ctl.scala 190:91] + wire _T_30 = ic_act_miss_f & _T_2535; // @[el2_ifu_mem_ctl.scala 197:38] + wire _T_94 = io_dec_tlu_force_halt | io_exu_flush_final; // @[el2_ifu_mem_ctl.scala 208:46] + wire _T_95 = _T_94 | ic_byp_hit_f; // @[el2_ifu_mem_ctl.scala 208:67] + wire _T_96 = _T_95 | ifu_bp_hit_taken_q_f; // @[el2_ifu_mem_ctl.scala 208:82] + wire _T_98 = _T_96 | _T_32; // @[el2_ifu_mem_ctl.scala 208:105] + wire _T_100 = bus_ifu_wr_en_ff & _T_17; // @[el2_ifu_mem_ctl.scala 208:158] + wire _T_101 = _T_98 | _T_100; // @[el2_ifu_mem_ctl.scala 208:138] + wire _T_103 = io_exu_flush_final | flush_final_f; // @[el2_ifu_mem_ctl.scala 212:43] + wire _T_104 = _T_103 | ic_byp_hit_f; // @[el2_ifu_mem_ctl.scala 212:59] + wire _T_105 = _T_104 | io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 212:74] + wire _T_119 = _T_108 | _T_32; // @[el2_ifu_mem_ctl.scala 216:84] + wire _T_120 = _T_119 | io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 216:118] + wire _T_130 = io_exu_flush_final | _T_32; // @[el2_ifu_mem_ctl.scala 220:43] + wire _T_131 = _T_130 | io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 220:76] + wire _T_148 = _T_32 | ic_miss_under_miss_f; // @[el2_ifu_mem_ctl.scala 225:55] + wire _T_149 = _T_148 | ic_ignore_2nd_miss_f; // @[el2_ifu_mem_ctl.scala 225:78] + wire _T_150 = _T_149 | io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 225:101] + wire _T_158 = _T_32 | io_exu_flush_final; // @[el2_ifu_mem_ctl.scala 230:55] + wire _T_159 = _T_158 | io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 230:76] wire _GEN_1 = _T_160 & _T_159; // @[Conditional.scala 39:67] wire _GEN_3 = _T_151 ? _T_159 : _GEN_1; // @[Conditional.scala 39:67] wire _GEN_5 = _T_132 ? _T_150 : _GEN_3; // @[Conditional.scala 39:67] @@ -955,919 +955,919 @@ module el2_ifu_mem_ctl( wire _GEN_11 = _T_102 ? _T_105 : _GEN_9; // @[Conditional.scala 39:67] wire _GEN_13 = _T_31 ? _T_101 : _GEN_11; // @[Conditional.scala 39:67] wire miss_state_en = _T_24 ? _T_30 : _GEN_13; // @[Conditional.scala 40:58] - wire _T_174 = ~flush_final_f; // @[el2_ifu_mem_ctl.scala 249:95] - wire _T_175 = _T_2236 & _T_174; // @[el2_ifu_mem_ctl.scala 249:93] - wire crit_wd_byp_ok_ff = _T_2237 | _T_175; // @[el2_ifu_mem_ctl.scala 249:58] - wire _T_178 = miss_pending & _T_56; // @[el2_ifu_mem_ctl.scala 250:36] - wire _T_180 = _T_2236 & io_exu_flush_final; // @[el2_ifu_mem_ctl.scala 250:106] - wire _T_181 = ~_T_180; // @[el2_ifu_mem_ctl.scala 250:72] - wire _T_182 = _T_178 & _T_181; // @[el2_ifu_mem_ctl.scala 250:70] - wire _T_184 = _T_2236 & crit_byp_hit_f; // @[el2_ifu_mem_ctl.scala 251:57] - wire _T_185 = ~_T_184; // @[el2_ifu_mem_ctl.scala 251:23] - wire _T_186 = _T_182 & _T_185; // @[el2_ifu_mem_ctl.scala 250:128] - wire _T_187 = _T_186 | ic_act_miss_f; // @[el2_ifu_mem_ctl.scala 251:77] - wire _T_188 = miss_nxtstate == 3'h4; // @[el2_ifu_mem_ctl.scala 252:36] - wire _T_189 = miss_pending & _T_188; // @[el2_ifu_mem_ctl.scala 252:19] - wire sel_hold_imb = _T_187 | _T_189; // @[el2_ifu_mem_ctl.scala 251:93] - wire _T_191 = _T_19 | ic_miss_under_miss_f; // @[el2_ifu_mem_ctl.scala 254:57] - wire sel_hold_imb_scnd = _T_191 & _T_174; // @[el2_ifu_mem_ctl.scala 254:81] - reg way_status_mb_scnd_ff; // @[el2_ifu_mem_ctl.scala 262:35] - reg [6:0] _T_5114; // @[el2_ifu_mem_ctl.scala 720:14] - wire [5:0] ifu_ic_rw_int_addr_ff = _T_5114[5:0]; // @[el2_ifu_mem_ctl.scala 719:27] - wire [6:0] _GEN_472 = {{1'd0}, ifu_ic_rw_int_addr_ff}; // @[el2_ifu_mem_ctl.scala 716:121] - wire _T_4979 = _GEN_472 == 7'h7f; // @[el2_ifu_mem_ctl.scala 716:121] + wire _T_174 = ~flush_final_f; // @[el2_ifu_mem_ctl.scala 250:95] + wire _T_175 = _T_2236 & _T_174; // @[el2_ifu_mem_ctl.scala 250:93] + wire crit_wd_byp_ok_ff = _T_2237 | _T_175; // @[el2_ifu_mem_ctl.scala 250:58] + wire _T_178 = miss_pending & _T_56; // @[el2_ifu_mem_ctl.scala 251:36] + wire _T_180 = _T_2236 & io_exu_flush_final; // @[el2_ifu_mem_ctl.scala 251:106] + wire _T_181 = ~_T_180; // @[el2_ifu_mem_ctl.scala 251:72] + wire _T_182 = _T_178 & _T_181; // @[el2_ifu_mem_ctl.scala 251:70] + wire _T_184 = _T_2236 & crit_byp_hit_f; // @[el2_ifu_mem_ctl.scala 252:57] + wire _T_185 = ~_T_184; // @[el2_ifu_mem_ctl.scala 252:23] + wire _T_186 = _T_182 & _T_185; // @[el2_ifu_mem_ctl.scala 251:128] + wire _T_187 = _T_186 | ic_act_miss_f; // @[el2_ifu_mem_ctl.scala 252:77] + wire _T_188 = miss_nxtstate == 3'h4; // @[el2_ifu_mem_ctl.scala 253:36] + wire _T_189 = miss_pending & _T_188; // @[el2_ifu_mem_ctl.scala 253:19] + wire sel_hold_imb = _T_187 | _T_189; // @[el2_ifu_mem_ctl.scala 252:93] + wire _T_191 = _T_19 | ic_miss_under_miss_f; // @[el2_ifu_mem_ctl.scala 255:57] + wire sel_hold_imb_scnd = _T_191 & _T_174; // @[el2_ifu_mem_ctl.scala 255:81] + reg way_status_mb_scnd_ff; // @[el2_ifu_mem_ctl.scala 263:35] + reg [6:0] _T_5114; // @[el2_ifu_mem_ctl.scala 721:14] + wire [5:0] ifu_ic_rw_int_addr_ff = _T_5114[5:0]; // @[el2_ifu_mem_ctl.scala 720:27] + wire [6:0] _GEN_472 = {{1'd0}, ifu_ic_rw_int_addr_ff}; // @[el2_ifu_mem_ctl.scala 717:121] + wire _T_4979 = _GEN_472 == 7'h7f; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4981 = _T_4979 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4470; // @[Reg.scala 27:20] - wire way_status_out_127 = _T_4470[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_473 = {{5'd0}, way_status_out_127}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4982 = _T_4981 & _GEN_473; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4975 = _GEN_472 == 7'h7e; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_127 = _T_4470[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_473 = {{5'd0}, way_status_out_127}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4982 = _T_4981 & _GEN_473; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4975 = _GEN_472 == 7'h7e; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4977 = _T_4975 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4466; // @[Reg.scala 27:20] - wire way_status_out_126 = _T_4466[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_475 = {{5'd0}, way_status_out_126}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4978 = _T_4977 & _GEN_475; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4971 = _GEN_472 == 7'h7d; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_126 = _T_4466[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_475 = {{5'd0}, way_status_out_126}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4978 = _T_4977 & _GEN_475; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4971 = _GEN_472 == 7'h7d; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4973 = _T_4971 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4462; // @[Reg.scala 27:20] - wire way_status_out_125 = _T_4462[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_477 = {{5'd0}, way_status_out_125}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4974 = _T_4973 & _GEN_477; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4967 = _GEN_472 == 7'h7c; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_125 = _T_4462[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_477 = {{5'd0}, way_status_out_125}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4974 = _T_4973 & _GEN_477; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4967 = _GEN_472 == 7'h7c; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4969 = _T_4967 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4458; // @[Reg.scala 27:20] - wire way_status_out_124 = _T_4458[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_479 = {{5'd0}, way_status_out_124}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4970 = _T_4969 & _GEN_479; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4963 = _GEN_472 == 7'h7b; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_124 = _T_4458[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_479 = {{5'd0}, way_status_out_124}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4970 = _T_4969 & _GEN_479; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4963 = _GEN_472 == 7'h7b; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4965 = _T_4963 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4454; // @[Reg.scala 27:20] - wire way_status_out_123 = _T_4454[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_481 = {{5'd0}, way_status_out_123}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4966 = _T_4965 & _GEN_481; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4959 = _GEN_472 == 7'h7a; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_123 = _T_4454[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_481 = {{5'd0}, way_status_out_123}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4966 = _T_4965 & _GEN_481; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4959 = _GEN_472 == 7'h7a; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4961 = _T_4959 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4450; // @[Reg.scala 27:20] - wire way_status_out_122 = _T_4450[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_483 = {{5'd0}, way_status_out_122}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4962 = _T_4961 & _GEN_483; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4955 = _GEN_472 == 7'h79; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_122 = _T_4450[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_483 = {{5'd0}, way_status_out_122}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4962 = _T_4961 & _GEN_483; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4955 = _GEN_472 == 7'h79; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4957 = _T_4955 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4446; // @[Reg.scala 27:20] - wire way_status_out_121 = _T_4446[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_485 = {{5'd0}, way_status_out_121}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4958 = _T_4957 & _GEN_485; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4951 = _GEN_472 == 7'h78; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_121 = _T_4446[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_485 = {{5'd0}, way_status_out_121}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4958 = _T_4957 & _GEN_485; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4951 = _GEN_472 == 7'h78; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4953 = _T_4951 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4442; // @[Reg.scala 27:20] - wire way_status_out_120 = _T_4442[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_487 = {{5'd0}, way_status_out_120}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4954 = _T_4953 & _GEN_487; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4947 = _GEN_472 == 7'h77; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_120 = _T_4442[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_487 = {{5'd0}, way_status_out_120}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4954 = _T_4953 & _GEN_487; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4947 = _GEN_472 == 7'h77; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4949 = _T_4947 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4438; // @[Reg.scala 27:20] - wire way_status_out_119 = _T_4438[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_489 = {{5'd0}, way_status_out_119}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4950 = _T_4949 & _GEN_489; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4943 = _GEN_472 == 7'h76; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_119 = _T_4438[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_489 = {{5'd0}, way_status_out_119}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4950 = _T_4949 & _GEN_489; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4943 = _GEN_472 == 7'h76; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4945 = _T_4943 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4434; // @[Reg.scala 27:20] - wire way_status_out_118 = _T_4434[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_491 = {{5'd0}, way_status_out_118}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4946 = _T_4945 & _GEN_491; // @[el2_ifu_mem_ctl.scala 716:130] + wire way_status_out_118 = _T_4434[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_491 = {{5'd0}, way_status_out_118}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4946 = _T_4945 & _GEN_491; // @[el2_ifu_mem_ctl.scala 717:130] wire [59:0] _T_4991 = {_T_4982,_T_4978,_T_4974,_T_4970,_T_4966,_T_4962,_T_4958,_T_4954,_T_4950,_T_4946}; // @[Cat.scala 29:58] - wire _T_4939 = _GEN_472 == 7'h75; // @[el2_ifu_mem_ctl.scala 716:121] + wire _T_4939 = _GEN_472 == 7'h75; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4941 = _T_4939 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4430; // @[Reg.scala 27:20] - wire way_status_out_117 = _T_4430[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_493 = {{5'd0}, way_status_out_117}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4942 = _T_4941 & _GEN_493; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4935 = _GEN_472 == 7'h74; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_117 = _T_4430[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_493 = {{5'd0}, way_status_out_117}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4942 = _T_4941 & _GEN_493; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4935 = _GEN_472 == 7'h74; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4937 = _T_4935 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4426; // @[Reg.scala 27:20] - wire way_status_out_116 = _T_4426[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_495 = {{5'd0}, way_status_out_116}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4938 = _T_4937 & _GEN_495; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4931 = _GEN_472 == 7'h73; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_116 = _T_4426[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_495 = {{5'd0}, way_status_out_116}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4938 = _T_4937 & _GEN_495; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4931 = _GEN_472 == 7'h73; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4933 = _T_4931 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4422; // @[Reg.scala 27:20] - wire way_status_out_115 = _T_4422[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_497 = {{5'd0}, way_status_out_115}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4934 = _T_4933 & _GEN_497; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4927 = _GEN_472 == 7'h72; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_115 = _T_4422[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_497 = {{5'd0}, way_status_out_115}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4934 = _T_4933 & _GEN_497; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4927 = _GEN_472 == 7'h72; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4929 = _T_4927 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4418; // @[Reg.scala 27:20] - wire way_status_out_114 = _T_4418[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_499 = {{5'd0}, way_status_out_114}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4930 = _T_4929 & _GEN_499; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4923 = _GEN_472 == 7'h71; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_114 = _T_4418[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_499 = {{5'd0}, way_status_out_114}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4930 = _T_4929 & _GEN_499; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4923 = _GEN_472 == 7'h71; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4925 = _T_4923 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4414; // @[Reg.scala 27:20] - wire way_status_out_113 = _T_4414[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_501 = {{5'd0}, way_status_out_113}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4926 = _T_4925 & _GEN_501; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4919 = _GEN_472 == 7'h70; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_113 = _T_4414[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_501 = {{5'd0}, way_status_out_113}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4926 = _T_4925 & _GEN_501; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4919 = _GEN_472 == 7'h70; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4921 = _T_4919 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4410; // @[Reg.scala 27:20] - wire way_status_out_112 = _T_4410[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_503 = {{5'd0}, way_status_out_112}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4922 = _T_4921 & _GEN_503; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4915 = _GEN_472 == 7'h6f; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_112 = _T_4410[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_503 = {{5'd0}, way_status_out_112}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4922 = _T_4921 & _GEN_503; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4915 = _GEN_472 == 7'h6f; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4917 = _T_4915 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4406; // @[Reg.scala 27:20] - wire way_status_out_111 = _T_4406[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_505 = {{5'd0}, way_status_out_111}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4918 = _T_4917 & _GEN_505; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4911 = _GEN_472 == 7'h6e; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_111 = _T_4406[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_505 = {{5'd0}, way_status_out_111}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4918 = _T_4917 & _GEN_505; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4911 = _GEN_472 == 7'h6e; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4913 = _T_4911 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4402; // @[Reg.scala 27:20] - wire way_status_out_110 = _T_4402[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_507 = {{5'd0}, way_status_out_110}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4914 = _T_4913 & _GEN_507; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4907 = _GEN_472 == 7'h6d; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_110 = _T_4402[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_507 = {{5'd0}, way_status_out_110}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4914 = _T_4913 & _GEN_507; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4907 = _GEN_472 == 7'h6d; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4909 = _T_4907 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4398; // @[Reg.scala 27:20] - wire way_status_out_109 = _T_4398[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_509 = {{5'd0}, way_status_out_109}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4910 = _T_4909 & _GEN_509; // @[el2_ifu_mem_ctl.scala 716:130] + wire way_status_out_109 = _T_4398[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_509 = {{5'd0}, way_status_out_109}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4910 = _T_4909 & _GEN_509; // @[el2_ifu_mem_ctl.scala 717:130] wire [113:0] _T_5000 = {_T_4991,_T_4942,_T_4938,_T_4934,_T_4930,_T_4926,_T_4922,_T_4918,_T_4914,_T_4910}; // @[Cat.scala 29:58] - wire _T_4903 = _GEN_472 == 7'h6c; // @[el2_ifu_mem_ctl.scala 716:121] + wire _T_4903 = _GEN_472 == 7'h6c; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4905 = _T_4903 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4394; // @[Reg.scala 27:20] - wire way_status_out_108 = _T_4394[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_511 = {{5'd0}, way_status_out_108}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4906 = _T_4905 & _GEN_511; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4899 = _GEN_472 == 7'h6b; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_108 = _T_4394[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_511 = {{5'd0}, way_status_out_108}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4906 = _T_4905 & _GEN_511; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4899 = _GEN_472 == 7'h6b; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4901 = _T_4899 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4390; // @[Reg.scala 27:20] - wire way_status_out_107 = _T_4390[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_513 = {{5'd0}, way_status_out_107}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4902 = _T_4901 & _GEN_513; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4895 = _GEN_472 == 7'h6a; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_107 = _T_4390[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_513 = {{5'd0}, way_status_out_107}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4902 = _T_4901 & _GEN_513; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4895 = _GEN_472 == 7'h6a; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4897 = _T_4895 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4386; // @[Reg.scala 27:20] - wire way_status_out_106 = _T_4386[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_515 = {{5'd0}, way_status_out_106}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4898 = _T_4897 & _GEN_515; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4891 = _GEN_472 == 7'h69; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_106 = _T_4386[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_515 = {{5'd0}, way_status_out_106}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4898 = _T_4897 & _GEN_515; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4891 = _GEN_472 == 7'h69; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4893 = _T_4891 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4382; // @[Reg.scala 27:20] - wire way_status_out_105 = _T_4382[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_517 = {{5'd0}, way_status_out_105}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4894 = _T_4893 & _GEN_517; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4887 = _GEN_472 == 7'h68; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_105 = _T_4382[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_517 = {{5'd0}, way_status_out_105}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4894 = _T_4893 & _GEN_517; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4887 = _GEN_472 == 7'h68; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4889 = _T_4887 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4378; // @[Reg.scala 27:20] - wire way_status_out_104 = _T_4378[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_519 = {{5'd0}, way_status_out_104}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4890 = _T_4889 & _GEN_519; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4883 = _GEN_472 == 7'h67; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_104 = _T_4378[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_519 = {{5'd0}, way_status_out_104}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4890 = _T_4889 & _GEN_519; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4883 = _GEN_472 == 7'h67; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4885 = _T_4883 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4374; // @[Reg.scala 27:20] - wire way_status_out_103 = _T_4374[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_521 = {{5'd0}, way_status_out_103}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4886 = _T_4885 & _GEN_521; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4879 = _GEN_472 == 7'h66; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_103 = _T_4374[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_521 = {{5'd0}, way_status_out_103}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4886 = _T_4885 & _GEN_521; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4879 = _GEN_472 == 7'h66; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4881 = _T_4879 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4370; // @[Reg.scala 27:20] - wire way_status_out_102 = _T_4370[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_523 = {{5'd0}, way_status_out_102}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4882 = _T_4881 & _GEN_523; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4875 = _GEN_472 == 7'h65; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_102 = _T_4370[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_523 = {{5'd0}, way_status_out_102}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4882 = _T_4881 & _GEN_523; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4875 = _GEN_472 == 7'h65; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4877 = _T_4875 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4366; // @[Reg.scala 27:20] - wire way_status_out_101 = _T_4366[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_525 = {{5'd0}, way_status_out_101}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4878 = _T_4877 & _GEN_525; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4871 = _GEN_472 == 7'h64; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_101 = _T_4366[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_525 = {{5'd0}, way_status_out_101}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4878 = _T_4877 & _GEN_525; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4871 = _GEN_472 == 7'h64; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4873 = _T_4871 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4362; // @[Reg.scala 27:20] - wire way_status_out_100 = _T_4362[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_527 = {{5'd0}, way_status_out_100}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4874 = _T_4873 & _GEN_527; // @[el2_ifu_mem_ctl.scala 716:130] + wire way_status_out_100 = _T_4362[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_527 = {{5'd0}, way_status_out_100}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4874 = _T_4873 & _GEN_527; // @[el2_ifu_mem_ctl.scala 717:130] wire [167:0] _T_5009 = {_T_5000,_T_4906,_T_4902,_T_4898,_T_4894,_T_4890,_T_4886,_T_4882,_T_4878,_T_4874}; // @[Cat.scala 29:58] - wire _T_4867 = _GEN_472 == 7'h63; // @[el2_ifu_mem_ctl.scala 716:121] + wire _T_4867 = _GEN_472 == 7'h63; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4869 = _T_4867 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4358; // @[Reg.scala 27:20] - wire way_status_out_99 = _T_4358[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_529 = {{5'd0}, way_status_out_99}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4870 = _T_4869 & _GEN_529; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4863 = _GEN_472 == 7'h62; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_99 = _T_4358[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_529 = {{5'd0}, way_status_out_99}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4870 = _T_4869 & _GEN_529; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4863 = _GEN_472 == 7'h62; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4865 = _T_4863 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4354; // @[Reg.scala 27:20] - wire way_status_out_98 = _T_4354[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_531 = {{5'd0}, way_status_out_98}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4866 = _T_4865 & _GEN_531; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4859 = _GEN_472 == 7'h61; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_98 = _T_4354[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_531 = {{5'd0}, way_status_out_98}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4866 = _T_4865 & _GEN_531; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4859 = _GEN_472 == 7'h61; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4861 = _T_4859 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4350; // @[Reg.scala 27:20] - wire way_status_out_97 = _T_4350[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_533 = {{5'd0}, way_status_out_97}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4862 = _T_4861 & _GEN_533; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4855 = _GEN_472 == 7'h60; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_97 = _T_4350[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_533 = {{5'd0}, way_status_out_97}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4862 = _T_4861 & _GEN_533; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4855 = _GEN_472 == 7'h60; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4857 = _T_4855 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4346; // @[Reg.scala 27:20] - wire way_status_out_96 = _T_4346[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_535 = {{5'd0}, way_status_out_96}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4858 = _T_4857 & _GEN_535; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4851 = _GEN_472 == 7'h5f; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_96 = _T_4346[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_535 = {{5'd0}, way_status_out_96}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4858 = _T_4857 & _GEN_535; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4851 = _GEN_472 == 7'h5f; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4853 = _T_4851 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4342; // @[Reg.scala 27:20] - wire way_status_out_95 = _T_4342[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_537 = {{5'd0}, way_status_out_95}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4854 = _T_4853 & _GEN_537; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4847 = _GEN_472 == 7'h5e; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_95 = _T_4342[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_537 = {{5'd0}, way_status_out_95}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4854 = _T_4853 & _GEN_537; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4847 = _GEN_472 == 7'h5e; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4849 = _T_4847 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4338; // @[Reg.scala 27:20] - wire way_status_out_94 = _T_4338[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_539 = {{5'd0}, way_status_out_94}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4850 = _T_4849 & _GEN_539; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4843 = _GEN_472 == 7'h5d; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_94 = _T_4338[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_539 = {{5'd0}, way_status_out_94}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4850 = _T_4849 & _GEN_539; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4843 = _GEN_472 == 7'h5d; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4845 = _T_4843 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4334; // @[Reg.scala 27:20] - wire way_status_out_93 = _T_4334[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_541 = {{5'd0}, way_status_out_93}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4846 = _T_4845 & _GEN_541; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4839 = _GEN_472 == 7'h5c; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_93 = _T_4334[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_541 = {{5'd0}, way_status_out_93}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4846 = _T_4845 & _GEN_541; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4839 = _GEN_472 == 7'h5c; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4841 = _T_4839 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4330; // @[Reg.scala 27:20] - wire way_status_out_92 = _T_4330[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_543 = {{5'd0}, way_status_out_92}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4842 = _T_4841 & _GEN_543; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4835 = _GEN_472 == 7'h5b; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_92 = _T_4330[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_543 = {{5'd0}, way_status_out_92}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4842 = _T_4841 & _GEN_543; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4835 = _GEN_472 == 7'h5b; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4837 = _T_4835 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4326; // @[Reg.scala 27:20] - wire way_status_out_91 = _T_4326[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_545 = {{5'd0}, way_status_out_91}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4838 = _T_4837 & _GEN_545; // @[el2_ifu_mem_ctl.scala 716:130] + wire way_status_out_91 = _T_4326[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_545 = {{5'd0}, way_status_out_91}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4838 = _T_4837 & _GEN_545; // @[el2_ifu_mem_ctl.scala 717:130] wire [221:0] _T_5018 = {_T_5009,_T_4870,_T_4866,_T_4862,_T_4858,_T_4854,_T_4850,_T_4846,_T_4842,_T_4838}; // @[Cat.scala 29:58] - wire _T_4831 = _GEN_472 == 7'h5a; // @[el2_ifu_mem_ctl.scala 716:121] + wire _T_4831 = _GEN_472 == 7'h5a; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4833 = _T_4831 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4322; // @[Reg.scala 27:20] - wire way_status_out_90 = _T_4322[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_547 = {{5'd0}, way_status_out_90}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4834 = _T_4833 & _GEN_547; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4827 = _GEN_472 == 7'h59; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_90 = _T_4322[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_547 = {{5'd0}, way_status_out_90}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4834 = _T_4833 & _GEN_547; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4827 = _GEN_472 == 7'h59; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4829 = _T_4827 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4318; // @[Reg.scala 27:20] - wire way_status_out_89 = _T_4318[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_549 = {{5'd0}, way_status_out_89}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4830 = _T_4829 & _GEN_549; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4823 = _GEN_472 == 7'h58; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_89 = _T_4318[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_549 = {{5'd0}, way_status_out_89}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4830 = _T_4829 & _GEN_549; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4823 = _GEN_472 == 7'h58; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4825 = _T_4823 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4314; // @[Reg.scala 27:20] - wire way_status_out_88 = _T_4314[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_551 = {{5'd0}, way_status_out_88}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4826 = _T_4825 & _GEN_551; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4819 = _GEN_472 == 7'h57; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_88 = _T_4314[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_551 = {{5'd0}, way_status_out_88}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4826 = _T_4825 & _GEN_551; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4819 = _GEN_472 == 7'h57; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4821 = _T_4819 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4310; // @[Reg.scala 27:20] - wire way_status_out_87 = _T_4310[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_553 = {{5'd0}, way_status_out_87}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4822 = _T_4821 & _GEN_553; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4815 = _GEN_472 == 7'h56; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_87 = _T_4310[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_553 = {{5'd0}, way_status_out_87}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4822 = _T_4821 & _GEN_553; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4815 = _GEN_472 == 7'h56; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4817 = _T_4815 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4306; // @[Reg.scala 27:20] - wire way_status_out_86 = _T_4306[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_555 = {{5'd0}, way_status_out_86}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4818 = _T_4817 & _GEN_555; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4811 = _GEN_472 == 7'h55; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_86 = _T_4306[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_555 = {{5'd0}, way_status_out_86}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4818 = _T_4817 & _GEN_555; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4811 = _GEN_472 == 7'h55; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4813 = _T_4811 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4302; // @[Reg.scala 27:20] - wire way_status_out_85 = _T_4302[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_557 = {{5'd0}, way_status_out_85}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4814 = _T_4813 & _GEN_557; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4807 = _GEN_472 == 7'h54; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_85 = _T_4302[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_557 = {{5'd0}, way_status_out_85}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4814 = _T_4813 & _GEN_557; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4807 = _GEN_472 == 7'h54; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4809 = _T_4807 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4298; // @[Reg.scala 27:20] - wire way_status_out_84 = _T_4298[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_559 = {{5'd0}, way_status_out_84}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4810 = _T_4809 & _GEN_559; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4803 = _GEN_472 == 7'h53; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_84 = _T_4298[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_559 = {{5'd0}, way_status_out_84}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4810 = _T_4809 & _GEN_559; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4803 = _GEN_472 == 7'h53; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4805 = _T_4803 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4294; // @[Reg.scala 27:20] - wire way_status_out_83 = _T_4294[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_561 = {{5'd0}, way_status_out_83}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4806 = _T_4805 & _GEN_561; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4799 = _GEN_472 == 7'h52; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_83 = _T_4294[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_561 = {{5'd0}, way_status_out_83}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4806 = _T_4805 & _GEN_561; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4799 = _GEN_472 == 7'h52; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4801 = _T_4799 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4290; // @[Reg.scala 27:20] - wire way_status_out_82 = _T_4290[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_563 = {{5'd0}, way_status_out_82}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4802 = _T_4801 & _GEN_563; // @[el2_ifu_mem_ctl.scala 716:130] + wire way_status_out_82 = _T_4290[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_563 = {{5'd0}, way_status_out_82}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4802 = _T_4801 & _GEN_563; // @[el2_ifu_mem_ctl.scala 717:130] wire [275:0] _T_5027 = {_T_5018,_T_4834,_T_4830,_T_4826,_T_4822,_T_4818,_T_4814,_T_4810,_T_4806,_T_4802}; // @[Cat.scala 29:58] - wire _T_4795 = _GEN_472 == 7'h51; // @[el2_ifu_mem_ctl.scala 716:121] + wire _T_4795 = _GEN_472 == 7'h51; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4797 = _T_4795 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4286; // @[Reg.scala 27:20] - wire way_status_out_81 = _T_4286[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_565 = {{5'd0}, way_status_out_81}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4798 = _T_4797 & _GEN_565; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4791 = _GEN_472 == 7'h50; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_81 = _T_4286[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_565 = {{5'd0}, way_status_out_81}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4798 = _T_4797 & _GEN_565; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4791 = _GEN_472 == 7'h50; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4793 = _T_4791 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4282; // @[Reg.scala 27:20] - wire way_status_out_80 = _T_4282[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_567 = {{5'd0}, way_status_out_80}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4794 = _T_4793 & _GEN_567; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4787 = _GEN_472 == 7'h4f; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_80 = _T_4282[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_567 = {{5'd0}, way_status_out_80}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4794 = _T_4793 & _GEN_567; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4787 = _GEN_472 == 7'h4f; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4789 = _T_4787 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4278; // @[Reg.scala 27:20] - wire way_status_out_79 = _T_4278[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_569 = {{5'd0}, way_status_out_79}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4790 = _T_4789 & _GEN_569; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4783 = _GEN_472 == 7'h4e; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_79 = _T_4278[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_569 = {{5'd0}, way_status_out_79}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4790 = _T_4789 & _GEN_569; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4783 = _GEN_472 == 7'h4e; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4785 = _T_4783 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4274; // @[Reg.scala 27:20] - wire way_status_out_78 = _T_4274[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_571 = {{5'd0}, way_status_out_78}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4786 = _T_4785 & _GEN_571; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4779 = _GEN_472 == 7'h4d; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_78 = _T_4274[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_571 = {{5'd0}, way_status_out_78}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4786 = _T_4785 & _GEN_571; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4779 = _GEN_472 == 7'h4d; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4781 = _T_4779 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4270; // @[Reg.scala 27:20] - wire way_status_out_77 = _T_4270[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_573 = {{5'd0}, way_status_out_77}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4782 = _T_4781 & _GEN_573; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4775 = _GEN_472 == 7'h4c; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_77 = _T_4270[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_573 = {{5'd0}, way_status_out_77}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4782 = _T_4781 & _GEN_573; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4775 = _GEN_472 == 7'h4c; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4777 = _T_4775 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4266; // @[Reg.scala 27:20] - wire way_status_out_76 = _T_4266[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_575 = {{5'd0}, way_status_out_76}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4778 = _T_4777 & _GEN_575; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4771 = _GEN_472 == 7'h4b; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_76 = _T_4266[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_575 = {{5'd0}, way_status_out_76}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4778 = _T_4777 & _GEN_575; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4771 = _GEN_472 == 7'h4b; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4773 = _T_4771 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4262; // @[Reg.scala 27:20] - wire way_status_out_75 = _T_4262[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_577 = {{5'd0}, way_status_out_75}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4774 = _T_4773 & _GEN_577; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4767 = _GEN_472 == 7'h4a; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_75 = _T_4262[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_577 = {{5'd0}, way_status_out_75}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4774 = _T_4773 & _GEN_577; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4767 = _GEN_472 == 7'h4a; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4769 = _T_4767 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4258; // @[Reg.scala 27:20] - wire way_status_out_74 = _T_4258[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_579 = {{5'd0}, way_status_out_74}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4770 = _T_4769 & _GEN_579; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4763 = _GEN_472 == 7'h49; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_74 = _T_4258[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_579 = {{5'd0}, way_status_out_74}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4770 = _T_4769 & _GEN_579; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4763 = _GEN_472 == 7'h49; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4765 = _T_4763 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4254; // @[Reg.scala 27:20] - wire way_status_out_73 = _T_4254[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_581 = {{5'd0}, way_status_out_73}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4766 = _T_4765 & _GEN_581; // @[el2_ifu_mem_ctl.scala 716:130] + wire way_status_out_73 = _T_4254[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_581 = {{5'd0}, way_status_out_73}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4766 = _T_4765 & _GEN_581; // @[el2_ifu_mem_ctl.scala 717:130] wire [329:0] _T_5036 = {_T_5027,_T_4798,_T_4794,_T_4790,_T_4786,_T_4782,_T_4778,_T_4774,_T_4770,_T_4766}; // @[Cat.scala 29:58] - wire _T_4759 = _GEN_472 == 7'h48; // @[el2_ifu_mem_ctl.scala 716:121] + wire _T_4759 = _GEN_472 == 7'h48; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4761 = _T_4759 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4250; // @[Reg.scala 27:20] - wire way_status_out_72 = _T_4250[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_583 = {{5'd0}, way_status_out_72}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4762 = _T_4761 & _GEN_583; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4755 = _GEN_472 == 7'h47; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_72 = _T_4250[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_583 = {{5'd0}, way_status_out_72}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4762 = _T_4761 & _GEN_583; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4755 = _GEN_472 == 7'h47; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4757 = _T_4755 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4246; // @[Reg.scala 27:20] - wire way_status_out_71 = _T_4246[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_585 = {{5'd0}, way_status_out_71}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4758 = _T_4757 & _GEN_585; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4751 = _GEN_472 == 7'h46; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_71 = _T_4246[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_585 = {{5'd0}, way_status_out_71}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4758 = _T_4757 & _GEN_585; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4751 = _GEN_472 == 7'h46; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4753 = _T_4751 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4242; // @[Reg.scala 27:20] - wire way_status_out_70 = _T_4242[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_587 = {{5'd0}, way_status_out_70}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4754 = _T_4753 & _GEN_587; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4747 = _GEN_472 == 7'h45; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_70 = _T_4242[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_587 = {{5'd0}, way_status_out_70}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4754 = _T_4753 & _GEN_587; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4747 = _GEN_472 == 7'h45; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4749 = _T_4747 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4238; // @[Reg.scala 27:20] - wire way_status_out_69 = _T_4238[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_589 = {{5'd0}, way_status_out_69}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4750 = _T_4749 & _GEN_589; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4743 = _GEN_472 == 7'h44; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_69 = _T_4238[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_589 = {{5'd0}, way_status_out_69}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4750 = _T_4749 & _GEN_589; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4743 = _GEN_472 == 7'h44; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4745 = _T_4743 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4234; // @[Reg.scala 27:20] - wire way_status_out_68 = _T_4234[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_591 = {{5'd0}, way_status_out_68}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4746 = _T_4745 & _GEN_591; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4739 = _GEN_472 == 7'h43; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_68 = _T_4234[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_591 = {{5'd0}, way_status_out_68}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4746 = _T_4745 & _GEN_591; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4739 = _GEN_472 == 7'h43; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4741 = _T_4739 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4230; // @[Reg.scala 27:20] - wire way_status_out_67 = _T_4230[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_593 = {{5'd0}, way_status_out_67}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4742 = _T_4741 & _GEN_593; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4735 = _GEN_472 == 7'h42; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_67 = _T_4230[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_593 = {{5'd0}, way_status_out_67}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4742 = _T_4741 & _GEN_593; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4735 = _GEN_472 == 7'h42; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4737 = _T_4735 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4226; // @[Reg.scala 27:20] - wire way_status_out_66 = _T_4226[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_595 = {{5'd0}, way_status_out_66}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4738 = _T_4737 & _GEN_595; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4731 = _GEN_472 == 7'h41; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_66 = _T_4226[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_595 = {{5'd0}, way_status_out_66}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4738 = _T_4737 & _GEN_595; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4731 = _GEN_472 == 7'h41; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4733 = _T_4731 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4222; // @[Reg.scala 27:20] - wire way_status_out_65 = _T_4222[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_597 = {{5'd0}, way_status_out_65}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4734 = _T_4733 & _GEN_597; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4727 = _GEN_472 == 7'h40; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_65 = _T_4222[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_597 = {{5'd0}, way_status_out_65}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4734 = _T_4733 & _GEN_597; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4727 = _GEN_472 == 7'h40; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4729 = _T_4727 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4218; // @[Reg.scala 27:20] - wire way_status_out_64 = _T_4218[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_599 = {{5'd0}, way_status_out_64}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4730 = _T_4729 & _GEN_599; // @[el2_ifu_mem_ctl.scala 716:130] + wire way_status_out_64 = _T_4218[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_599 = {{5'd0}, way_status_out_64}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4730 = _T_4729 & _GEN_599; // @[el2_ifu_mem_ctl.scala 717:130] wire [383:0] _T_5045 = {_T_5036,_T_4762,_T_4758,_T_4754,_T_4750,_T_4746,_T_4742,_T_4738,_T_4734,_T_4730}; // @[Cat.scala 29:58] - wire _T_4723 = ifu_ic_rw_int_addr_ff == 6'h3f; // @[el2_ifu_mem_ctl.scala 716:121] + wire _T_4723 = ifu_ic_rw_int_addr_ff == 6'h3f; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4725 = _T_4723 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4214; // @[Reg.scala 27:20] - wire way_status_out_63 = _T_4214[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_600 = {{5'd0}, way_status_out_63}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4726 = _T_4725 & _GEN_600; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4719 = ifu_ic_rw_int_addr_ff == 6'h3e; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_63 = _T_4214[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_600 = {{5'd0}, way_status_out_63}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4726 = _T_4725 & _GEN_600; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4719 = ifu_ic_rw_int_addr_ff == 6'h3e; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4721 = _T_4719 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4210; // @[Reg.scala 27:20] - wire way_status_out_62 = _T_4210[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_601 = {{5'd0}, way_status_out_62}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4722 = _T_4721 & _GEN_601; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4715 = ifu_ic_rw_int_addr_ff == 6'h3d; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_62 = _T_4210[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_601 = {{5'd0}, way_status_out_62}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4722 = _T_4721 & _GEN_601; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4715 = ifu_ic_rw_int_addr_ff == 6'h3d; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4717 = _T_4715 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4206; // @[Reg.scala 27:20] - wire way_status_out_61 = _T_4206[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_602 = {{5'd0}, way_status_out_61}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4718 = _T_4717 & _GEN_602; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4711 = ifu_ic_rw_int_addr_ff == 6'h3c; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_61 = _T_4206[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_602 = {{5'd0}, way_status_out_61}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4718 = _T_4717 & _GEN_602; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4711 = ifu_ic_rw_int_addr_ff == 6'h3c; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4713 = _T_4711 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4202; // @[Reg.scala 27:20] - wire way_status_out_60 = _T_4202[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_603 = {{5'd0}, way_status_out_60}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4714 = _T_4713 & _GEN_603; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4707 = ifu_ic_rw_int_addr_ff == 6'h3b; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_60 = _T_4202[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_603 = {{5'd0}, way_status_out_60}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4714 = _T_4713 & _GEN_603; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4707 = ifu_ic_rw_int_addr_ff == 6'h3b; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4709 = _T_4707 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4198; // @[Reg.scala 27:20] - wire way_status_out_59 = _T_4198[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_604 = {{5'd0}, way_status_out_59}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4710 = _T_4709 & _GEN_604; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4703 = ifu_ic_rw_int_addr_ff == 6'h3a; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_59 = _T_4198[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_604 = {{5'd0}, way_status_out_59}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4710 = _T_4709 & _GEN_604; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4703 = ifu_ic_rw_int_addr_ff == 6'h3a; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4705 = _T_4703 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4194; // @[Reg.scala 27:20] - wire way_status_out_58 = _T_4194[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_605 = {{5'd0}, way_status_out_58}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4706 = _T_4705 & _GEN_605; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4699 = ifu_ic_rw_int_addr_ff == 6'h39; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_58 = _T_4194[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_605 = {{5'd0}, way_status_out_58}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4706 = _T_4705 & _GEN_605; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4699 = ifu_ic_rw_int_addr_ff == 6'h39; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4701 = _T_4699 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4190; // @[Reg.scala 27:20] - wire way_status_out_57 = _T_4190[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_606 = {{5'd0}, way_status_out_57}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4702 = _T_4701 & _GEN_606; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4695 = ifu_ic_rw_int_addr_ff == 6'h38; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_57 = _T_4190[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_606 = {{5'd0}, way_status_out_57}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4702 = _T_4701 & _GEN_606; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4695 = ifu_ic_rw_int_addr_ff == 6'h38; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4697 = _T_4695 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4186; // @[Reg.scala 27:20] - wire way_status_out_56 = _T_4186[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_607 = {{5'd0}, way_status_out_56}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4698 = _T_4697 & _GEN_607; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4691 = ifu_ic_rw_int_addr_ff == 6'h37; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_56 = _T_4186[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_607 = {{5'd0}, way_status_out_56}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4698 = _T_4697 & _GEN_607; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4691 = ifu_ic_rw_int_addr_ff == 6'h37; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4693 = _T_4691 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4182; // @[Reg.scala 27:20] - wire way_status_out_55 = _T_4182[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_608 = {{5'd0}, way_status_out_55}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4694 = _T_4693 & _GEN_608; // @[el2_ifu_mem_ctl.scala 716:130] + wire way_status_out_55 = _T_4182[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_608 = {{5'd0}, way_status_out_55}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4694 = _T_4693 & _GEN_608; // @[el2_ifu_mem_ctl.scala 717:130] wire [437:0] _T_5054 = {_T_5045,_T_4726,_T_4722,_T_4718,_T_4714,_T_4710,_T_4706,_T_4702,_T_4698,_T_4694}; // @[Cat.scala 29:58] - wire _T_4687 = ifu_ic_rw_int_addr_ff == 6'h36; // @[el2_ifu_mem_ctl.scala 716:121] + wire _T_4687 = ifu_ic_rw_int_addr_ff == 6'h36; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4689 = _T_4687 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4178; // @[Reg.scala 27:20] - wire way_status_out_54 = _T_4178[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_609 = {{5'd0}, way_status_out_54}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4690 = _T_4689 & _GEN_609; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4683 = ifu_ic_rw_int_addr_ff == 6'h35; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_54 = _T_4178[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_609 = {{5'd0}, way_status_out_54}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4690 = _T_4689 & _GEN_609; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4683 = ifu_ic_rw_int_addr_ff == 6'h35; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4685 = _T_4683 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4174; // @[Reg.scala 27:20] - wire way_status_out_53 = _T_4174[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_610 = {{5'd0}, way_status_out_53}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4686 = _T_4685 & _GEN_610; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4679 = ifu_ic_rw_int_addr_ff == 6'h34; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_53 = _T_4174[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_610 = {{5'd0}, way_status_out_53}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4686 = _T_4685 & _GEN_610; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4679 = ifu_ic_rw_int_addr_ff == 6'h34; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4681 = _T_4679 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4170; // @[Reg.scala 27:20] - wire way_status_out_52 = _T_4170[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_611 = {{5'd0}, way_status_out_52}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4682 = _T_4681 & _GEN_611; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4675 = ifu_ic_rw_int_addr_ff == 6'h33; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_52 = _T_4170[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_611 = {{5'd0}, way_status_out_52}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4682 = _T_4681 & _GEN_611; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4675 = ifu_ic_rw_int_addr_ff == 6'h33; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4677 = _T_4675 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4166; // @[Reg.scala 27:20] - wire way_status_out_51 = _T_4166[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_612 = {{5'd0}, way_status_out_51}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4678 = _T_4677 & _GEN_612; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4671 = ifu_ic_rw_int_addr_ff == 6'h32; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_51 = _T_4166[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_612 = {{5'd0}, way_status_out_51}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4678 = _T_4677 & _GEN_612; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4671 = ifu_ic_rw_int_addr_ff == 6'h32; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4673 = _T_4671 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4162; // @[Reg.scala 27:20] - wire way_status_out_50 = _T_4162[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_613 = {{5'd0}, way_status_out_50}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4674 = _T_4673 & _GEN_613; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4667 = ifu_ic_rw_int_addr_ff == 6'h31; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_50 = _T_4162[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_613 = {{5'd0}, way_status_out_50}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4674 = _T_4673 & _GEN_613; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4667 = ifu_ic_rw_int_addr_ff == 6'h31; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4669 = _T_4667 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4158; // @[Reg.scala 27:20] - wire way_status_out_49 = _T_4158[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_614 = {{5'd0}, way_status_out_49}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4670 = _T_4669 & _GEN_614; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4663 = ifu_ic_rw_int_addr_ff == 6'h30; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_49 = _T_4158[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_614 = {{5'd0}, way_status_out_49}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4670 = _T_4669 & _GEN_614; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4663 = ifu_ic_rw_int_addr_ff == 6'h30; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4665 = _T_4663 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4154; // @[Reg.scala 27:20] - wire way_status_out_48 = _T_4154[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_615 = {{5'd0}, way_status_out_48}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4666 = _T_4665 & _GEN_615; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4659 = ifu_ic_rw_int_addr_ff == 6'h2f; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_48 = _T_4154[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_615 = {{5'd0}, way_status_out_48}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4666 = _T_4665 & _GEN_615; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4659 = ifu_ic_rw_int_addr_ff == 6'h2f; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4661 = _T_4659 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4150; // @[Reg.scala 27:20] - wire way_status_out_47 = _T_4150[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_616 = {{5'd0}, way_status_out_47}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4662 = _T_4661 & _GEN_616; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4655 = ifu_ic_rw_int_addr_ff == 6'h2e; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_47 = _T_4150[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_616 = {{5'd0}, way_status_out_47}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4662 = _T_4661 & _GEN_616; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4655 = ifu_ic_rw_int_addr_ff == 6'h2e; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4657 = _T_4655 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4146; // @[Reg.scala 27:20] - wire way_status_out_46 = _T_4146[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_617 = {{5'd0}, way_status_out_46}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4658 = _T_4657 & _GEN_617; // @[el2_ifu_mem_ctl.scala 716:130] + wire way_status_out_46 = _T_4146[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_617 = {{5'd0}, way_status_out_46}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4658 = _T_4657 & _GEN_617; // @[el2_ifu_mem_ctl.scala 717:130] wire [491:0] _T_5063 = {_T_5054,_T_4690,_T_4686,_T_4682,_T_4678,_T_4674,_T_4670,_T_4666,_T_4662,_T_4658}; // @[Cat.scala 29:58] - wire _T_4651 = ifu_ic_rw_int_addr_ff == 6'h2d; // @[el2_ifu_mem_ctl.scala 716:121] + wire _T_4651 = ifu_ic_rw_int_addr_ff == 6'h2d; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4653 = _T_4651 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4142; // @[Reg.scala 27:20] - wire way_status_out_45 = _T_4142[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_618 = {{5'd0}, way_status_out_45}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4654 = _T_4653 & _GEN_618; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4647 = ifu_ic_rw_int_addr_ff == 6'h2c; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_45 = _T_4142[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_618 = {{5'd0}, way_status_out_45}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4654 = _T_4653 & _GEN_618; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4647 = ifu_ic_rw_int_addr_ff == 6'h2c; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4649 = _T_4647 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4138; // @[Reg.scala 27:20] - wire way_status_out_44 = _T_4138[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_619 = {{5'd0}, way_status_out_44}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4650 = _T_4649 & _GEN_619; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4643 = ifu_ic_rw_int_addr_ff == 6'h2b; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_44 = _T_4138[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_619 = {{5'd0}, way_status_out_44}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4650 = _T_4649 & _GEN_619; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4643 = ifu_ic_rw_int_addr_ff == 6'h2b; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4645 = _T_4643 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4134; // @[Reg.scala 27:20] - wire way_status_out_43 = _T_4134[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_620 = {{5'd0}, way_status_out_43}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4646 = _T_4645 & _GEN_620; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4639 = ifu_ic_rw_int_addr_ff == 6'h2a; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_43 = _T_4134[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_620 = {{5'd0}, way_status_out_43}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4646 = _T_4645 & _GEN_620; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4639 = ifu_ic_rw_int_addr_ff == 6'h2a; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4641 = _T_4639 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4130; // @[Reg.scala 27:20] - wire way_status_out_42 = _T_4130[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_621 = {{5'd0}, way_status_out_42}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4642 = _T_4641 & _GEN_621; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4635 = ifu_ic_rw_int_addr_ff == 6'h29; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_42 = _T_4130[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_621 = {{5'd0}, way_status_out_42}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4642 = _T_4641 & _GEN_621; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4635 = ifu_ic_rw_int_addr_ff == 6'h29; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4637 = _T_4635 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4126; // @[Reg.scala 27:20] - wire way_status_out_41 = _T_4126[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_622 = {{5'd0}, way_status_out_41}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4638 = _T_4637 & _GEN_622; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4631 = ifu_ic_rw_int_addr_ff == 6'h28; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_41 = _T_4126[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_622 = {{5'd0}, way_status_out_41}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4638 = _T_4637 & _GEN_622; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4631 = ifu_ic_rw_int_addr_ff == 6'h28; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4633 = _T_4631 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4122; // @[Reg.scala 27:20] - wire way_status_out_40 = _T_4122[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_623 = {{5'd0}, way_status_out_40}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4634 = _T_4633 & _GEN_623; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4627 = ifu_ic_rw_int_addr_ff == 6'h27; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_40 = _T_4122[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_623 = {{5'd0}, way_status_out_40}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4634 = _T_4633 & _GEN_623; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4627 = ifu_ic_rw_int_addr_ff == 6'h27; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4629 = _T_4627 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4118; // @[Reg.scala 27:20] - wire way_status_out_39 = _T_4118[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_624 = {{5'd0}, way_status_out_39}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4630 = _T_4629 & _GEN_624; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4623 = ifu_ic_rw_int_addr_ff == 6'h26; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_39 = _T_4118[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_624 = {{5'd0}, way_status_out_39}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4630 = _T_4629 & _GEN_624; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4623 = ifu_ic_rw_int_addr_ff == 6'h26; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4625 = _T_4623 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4114; // @[Reg.scala 27:20] - wire way_status_out_38 = _T_4114[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_625 = {{5'd0}, way_status_out_38}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4626 = _T_4625 & _GEN_625; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4619 = ifu_ic_rw_int_addr_ff == 6'h25; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_38 = _T_4114[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_625 = {{5'd0}, way_status_out_38}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4626 = _T_4625 & _GEN_625; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4619 = ifu_ic_rw_int_addr_ff == 6'h25; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4621 = _T_4619 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4110; // @[Reg.scala 27:20] - wire way_status_out_37 = _T_4110[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_626 = {{5'd0}, way_status_out_37}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4622 = _T_4621 & _GEN_626; // @[el2_ifu_mem_ctl.scala 716:130] + wire way_status_out_37 = _T_4110[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_626 = {{5'd0}, way_status_out_37}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4622 = _T_4621 & _GEN_626; // @[el2_ifu_mem_ctl.scala 717:130] wire [545:0] _T_5072 = {_T_5063,_T_4654,_T_4650,_T_4646,_T_4642,_T_4638,_T_4634,_T_4630,_T_4626,_T_4622}; // @[Cat.scala 29:58] - wire _T_4615 = ifu_ic_rw_int_addr_ff == 6'h24; // @[el2_ifu_mem_ctl.scala 716:121] + wire _T_4615 = ifu_ic_rw_int_addr_ff == 6'h24; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4617 = _T_4615 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4106; // @[Reg.scala 27:20] - wire way_status_out_36 = _T_4106[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_627 = {{5'd0}, way_status_out_36}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4618 = _T_4617 & _GEN_627; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4611 = ifu_ic_rw_int_addr_ff == 6'h23; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_36 = _T_4106[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_627 = {{5'd0}, way_status_out_36}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4618 = _T_4617 & _GEN_627; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4611 = ifu_ic_rw_int_addr_ff == 6'h23; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4613 = _T_4611 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4102; // @[Reg.scala 27:20] - wire way_status_out_35 = _T_4102[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_628 = {{5'd0}, way_status_out_35}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4614 = _T_4613 & _GEN_628; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4607 = ifu_ic_rw_int_addr_ff == 6'h22; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_35 = _T_4102[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_628 = {{5'd0}, way_status_out_35}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4614 = _T_4613 & _GEN_628; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4607 = ifu_ic_rw_int_addr_ff == 6'h22; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4609 = _T_4607 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4098; // @[Reg.scala 27:20] - wire way_status_out_34 = _T_4098[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_629 = {{5'd0}, way_status_out_34}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4610 = _T_4609 & _GEN_629; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4603 = ifu_ic_rw_int_addr_ff == 6'h21; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_34 = _T_4098[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_629 = {{5'd0}, way_status_out_34}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4610 = _T_4609 & _GEN_629; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4603 = ifu_ic_rw_int_addr_ff == 6'h21; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4605 = _T_4603 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4094; // @[Reg.scala 27:20] - wire way_status_out_33 = _T_4094[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_630 = {{5'd0}, way_status_out_33}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4606 = _T_4605 & _GEN_630; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4599 = ifu_ic_rw_int_addr_ff == 6'h20; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_33 = _T_4094[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_630 = {{5'd0}, way_status_out_33}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4606 = _T_4605 & _GEN_630; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4599 = ifu_ic_rw_int_addr_ff == 6'h20; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4601 = _T_4599 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4090; // @[Reg.scala 27:20] - wire way_status_out_32 = _T_4090[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_631 = {{5'd0}, way_status_out_32}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4602 = _T_4601 & _GEN_631; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4595 = ifu_ic_rw_int_addr_ff == 6'h1f; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_32 = _T_4090[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_631 = {{5'd0}, way_status_out_32}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4602 = _T_4601 & _GEN_631; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4595 = ifu_ic_rw_int_addr_ff == 6'h1f; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4597 = _T_4595 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4086; // @[Reg.scala 27:20] - wire way_status_out_31 = _T_4086[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_632 = {{5'd0}, way_status_out_31}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4598 = _T_4597 & _GEN_632; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4591 = ifu_ic_rw_int_addr_ff == 6'h1e; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_31 = _T_4086[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_632 = {{5'd0}, way_status_out_31}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4598 = _T_4597 & _GEN_632; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4591 = ifu_ic_rw_int_addr_ff == 6'h1e; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4593 = _T_4591 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4082; // @[Reg.scala 27:20] - wire way_status_out_30 = _T_4082[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_633 = {{5'd0}, way_status_out_30}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4594 = _T_4593 & _GEN_633; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4587 = ifu_ic_rw_int_addr_ff == 6'h1d; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_30 = _T_4082[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_633 = {{5'd0}, way_status_out_30}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4594 = _T_4593 & _GEN_633; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4587 = ifu_ic_rw_int_addr_ff == 6'h1d; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4589 = _T_4587 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4078; // @[Reg.scala 27:20] - wire way_status_out_29 = _T_4078[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_634 = {{5'd0}, way_status_out_29}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4590 = _T_4589 & _GEN_634; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4583 = ifu_ic_rw_int_addr_ff == 6'h1c; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_29 = _T_4078[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_634 = {{5'd0}, way_status_out_29}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4590 = _T_4589 & _GEN_634; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4583 = ifu_ic_rw_int_addr_ff == 6'h1c; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4585 = _T_4583 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4074; // @[Reg.scala 27:20] - wire way_status_out_28 = _T_4074[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_635 = {{5'd0}, way_status_out_28}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4586 = _T_4585 & _GEN_635; // @[el2_ifu_mem_ctl.scala 716:130] + wire way_status_out_28 = _T_4074[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_635 = {{5'd0}, way_status_out_28}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4586 = _T_4585 & _GEN_635; // @[el2_ifu_mem_ctl.scala 717:130] wire [599:0] _T_5081 = {_T_5072,_T_4618,_T_4614,_T_4610,_T_4606,_T_4602,_T_4598,_T_4594,_T_4590,_T_4586}; // @[Cat.scala 29:58] - wire _T_4579 = ifu_ic_rw_int_addr_ff == 6'h1b; // @[el2_ifu_mem_ctl.scala 716:121] + wire _T_4579 = ifu_ic_rw_int_addr_ff == 6'h1b; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4581 = _T_4579 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4070; // @[Reg.scala 27:20] - wire way_status_out_27 = _T_4070[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_636 = {{5'd0}, way_status_out_27}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4582 = _T_4581 & _GEN_636; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4575 = ifu_ic_rw_int_addr_ff == 6'h1a; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_27 = _T_4070[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_636 = {{5'd0}, way_status_out_27}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4582 = _T_4581 & _GEN_636; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4575 = ifu_ic_rw_int_addr_ff == 6'h1a; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4577 = _T_4575 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4066; // @[Reg.scala 27:20] - wire way_status_out_26 = _T_4066[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_637 = {{5'd0}, way_status_out_26}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4578 = _T_4577 & _GEN_637; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4571 = ifu_ic_rw_int_addr_ff == 6'h19; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_26 = _T_4066[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_637 = {{5'd0}, way_status_out_26}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4578 = _T_4577 & _GEN_637; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4571 = ifu_ic_rw_int_addr_ff == 6'h19; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4573 = _T_4571 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4062; // @[Reg.scala 27:20] - wire way_status_out_25 = _T_4062[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_638 = {{5'd0}, way_status_out_25}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4574 = _T_4573 & _GEN_638; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4567 = ifu_ic_rw_int_addr_ff == 6'h18; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_25 = _T_4062[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_638 = {{5'd0}, way_status_out_25}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4574 = _T_4573 & _GEN_638; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4567 = ifu_ic_rw_int_addr_ff == 6'h18; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4569 = _T_4567 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4058; // @[Reg.scala 27:20] - wire way_status_out_24 = _T_4058[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_639 = {{5'd0}, way_status_out_24}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4570 = _T_4569 & _GEN_639; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4563 = ifu_ic_rw_int_addr_ff == 6'h17; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_24 = _T_4058[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_639 = {{5'd0}, way_status_out_24}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4570 = _T_4569 & _GEN_639; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4563 = ifu_ic_rw_int_addr_ff == 6'h17; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4565 = _T_4563 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4054; // @[Reg.scala 27:20] - wire way_status_out_23 = _T_4054[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_640 = {{5'd0}, way_status_out_23}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4566 = _T_4565 & _GEN_640; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4559 = ifu_ic_rw_int_addr_ff == 6'h16; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_23 = _T_4054[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_640 = {{5'd0}, way_status_out_23}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4566 = _T_4565 & _GEN_640; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4559 = ifu_ic_rw_int_addr_ff == 6'h16; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4561 = _T_4559 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4050; // @[Reg.scala 27:20] - wire way_status_out_22 = _T_4050[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_641 = {{5'd0}, way_status_out_22}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4562 = _T_4561 & _GEN_641; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4555 = ifu_ic_rw_int_addr_ff == 6'h15; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_22 = _T_4050[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_641 = {{5'd0}, way_status_out_22}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4562 = _T_4561 & _GEN_641; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4555 = ifu_ic_rw_int_addr_ff == 6'h15; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4557 = _T_4555 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4046; // @[Reg.scala 27:20] - wire way_status_out_21 = _T_4046[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_642 = {{5'd0}, way_status_out_21}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4558 = _T_4557 & _GEN_642; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4551 = ifu_ic_rw_int_addr_ff == 6'h14; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_21 = _T_4046[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_642 = {{5'd0}, way_status_out_21}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4558 = _T_4557 & _GEN_642; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4551 = ifu_ic_rw_int_addr_ff == 6'h14; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4553 = _T_4551 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4042; // @[Reg.scala 27:20] - wire way_status_out_20 = _T_4042[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_643 = {{5'd0}, way_status_out_20}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4554 = _T_4553 & _GEN_643; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4547 = ifu_ic_rw_int_addr_ff == 6'h13; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_20 = _T_4042[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_643 = {{5'd0}, way_status_out_20}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4554 = _T_4553 & _GEN_643; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4547 = ifu_ic_rw_int_addr_ff == 6'h13; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4549 = _T_4547 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4038; // @[Reg.scala 27:20] - wire way_status_out_19 = _T_4038[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_644 = {{5'd0}, way_status_out_19}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4550 = _T_4549 & _GEN_644; // @[el2_ifu_mem_ctl.scala 716:130] + wire way_status_out_19 = _T_4038[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_644 = {{5'd0}, way_status_out_19}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4550 = _T_4549 & _GEN_644; // @[el2_ifu_mem_ctl.scala 717:130] wire [653:0] _T_5090 = {_T_5081,_T_4582,_T_4578,_T_4574,_T_4570,_T_4566,_T_4562,_T_4558,_T_4554,_T_4550}; // @[Cat.scala 29:58] - wire _T_4543 = ifu_ic_rw_int_addr_ff == 6'h12; // @[el2_ifu_mem_ctl.scala 716:121] + wire _T_4543 = ifu_ic_rw_int_addr_ff == 6'h12; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4545 = _T_4543 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4034; // @[Reg.scala 27:20] - wire way_status_out_18 = _T_4034[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_645 = {{5'd0}, way_status_out_18}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4546 = _T_4545 & _GEN_645; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4539 = ifu_ic_rw_int_addr_ff == 6'h11; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_18 = _T_4034[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_645 = {{5'd0}, way_status_out_18}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4546 = _T_4545 & _GEN_645; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4539 = ifu_ic_rw_int_addr_ff == 6'h11; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4541 = _T_4539 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4030; // @[Reg.scala 27:20] - wire way_status_out_17 = _T_4030[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_646 = {{5'd0}, way_status_out_17}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4542 = _T_4541 & _GEN_646; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4535 = ifu_ic_rw_int_addr_ff == 6'h10; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_17 = _T_4030[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_646 = {{5'd0}, way_status_out_17}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4542 = _T_4541 & _GEN_646; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4535 = ifu_ic_rw_int_addr_ff == 6'h10; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4537 = _T_4535 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4026; // @[Reg.scala 27:20] - wire way_status_out_16 = _T_4026[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_647 = {{5'd0}, way_status_out_16}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4538 = _T_4537 & _GEN_647; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4531 = ifu_ic_rw_int_addr_ff == 6'hf; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_16 = _T_4026[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_647 = {{5'd0}, way_status_out_16}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4538 = _T_4537 & _GEN_647; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4531 = ifu_ic_rw_int_addr_ff == 6'hf; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4533 = _T_4531 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4022; // @[Reg.scala 27:20] - wire way_status_out_15 = _T_4022[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_648 = {{5'd0}, way_status_out_15}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4534 = _T_4533 & _GEN_648; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4527 = ifu_ic_rw_int_addr_ff == 6'he; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_15 = _T_4022[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_648 = {{5'd0}, way_status_out_15}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4534 = _T_4533 & _GEN_648; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4527 = ifu_ic_rw_int_addr_ff == 6'he; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4529 = _T_4527 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4018; // @[Reg.scala 27:20] - wire way_status_out_14 = _T_4018[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_649 = {{5'd0}, way_status_out_14}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4530 = _T_4529 & _GEN_649; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4523 = ifu_ic_rw_int_addr_ff == 6'hd; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_14 = _T_4018[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_649 = {{5'd0}, way_status_out_14}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4530 = _T_4529 & _GEN_649; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4523 = ifu_ic_rw_int_addr_ff == 6'hd; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4525 = _T_4523 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4014; // @[Reg.scala 27:20] - wire way_status_out_13 = _T_4014[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_650 = {{5'd0}, way_status_out_13}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4526 = _T_4525 & _GEN_650; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4519 = ifu_ic_rw_int_addr_ff == 6'hc; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_13 = _T_4014[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_650 = {{5'd0}, way_status_out_13}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4526 = _T_4525 & _GEN_650; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4519 = ifu_ic_rw_int_addr_ff == 6'hc; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4521 = _T_4519 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4010; // @[Reg.scala 27:20] - wire way_status_out_12 = _T_4010[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_651 = {{5'd0}, way_status_out_12}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4522 = _T_4521 & _GEN_651; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4515 = ifu_ic_rw_int_addr_ff == 6'hb; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_12 = _T_4010[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_651 = {{5'd0}, way_status_out_12}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4522 = _T_4521 & _GEN_651; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4515 = ifu_ic_rw_int_addr_ff == 6'hb; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4517 = _T_4515 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4006; // @[Reg.scala 27:20] - wire way_status_out_11 = _T_4006[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_652 = {{5'd0}, way_status_out_11}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4518 = _T_4517 & _GEN_652; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4511 = ifu_ic_rw_int_addr_ff == 6'ha; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_11 = _T_4006[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_652 = {{5'd0}, way_status_out_11}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4518 = _T_4517 & _GEN_652; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4511 = ifu_ic_rw_int_addr_ff == 6'ha; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4513 = _T_4511 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_4002; // @[Reg.scala 27:20] - wire way_status_out_10 = _T_4002[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_653 = {{5'd0}, way_status_out_10}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4514 = _T_4513 & _GEN_653; // @[el2_ifu_mem_ctl.scala 716:130] + wire way_status_out_10 = _T_4002[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_653 = {{5'd0}, way_status_out_10}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4514 = _T_4513 & _GEN_653; // @[el2_ifu_mem_ctl.scala 717:130] wire [707:0] _T_5099 = {_T_5090,_T_4546,_T_4542,_T_4538,_T_4534,_T_4530,_T_4526,_T_4522,_T_4518,_T_4514}; // @[Cat.scala 29:58] - wire _T_4507 = ifu_ic_rw_int_addr_ff == 6'h9; // @[el2_ifu_mem_ctl.scala 716:121] + wire _T_4507 = ifu_ic_rw_int_addr_ff == 6'h9; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4509 = _T_4507 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_3998; // @[Reg.scala 27:20] - wire way_status_out_9 = _T_3998[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_654 = {{5'd0}, way_status_out_9}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4510 = _T_4509 & _GEN_654; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4503 = ifu_ic_rw_int_addr_ff == 6'h8; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_9 = _T_3998[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_654 = {{5'd0}, way_status_out_9}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4510 = _T_4509 & _GEN_654; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4503 = ifu_ic_rw_int_addr_ff == 6'h8; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4505 = _T_4503 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_3994; // @[Reg.scala 27:20] - wire way_status_out_8 = _T_3994[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_655 = {{5'd0}, way_status_out_8}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4506 = _T_4505 & _GEN_655; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4499 = ifu_ic_rw_int_addr_ff == 6'h7; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_8 = _T_3994[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_655 = {{5'd0}, way_status_out_8}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4506 = _T_4505 & _GEN_655; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4499 = ifu_ic_rw_int_addr_ff == 6'h7; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4501 = _T_4499 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_3990; // @[Reg.scala 27:20] - wire way_status_out_7 = _T_3990[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_656 = {{5'd0}, way_status_out_7}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4502 = _T_4501 & _GEN_656; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4495 = ifu_ic_rw_int_addr_ff == 6'h6; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_7 = _T_3990[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_656 = {{5'd0}, way_status_out_7}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4502 = _T_4501 & _GEN_656; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4495 = ifu_ic_rw_int_addr_ff == 6'h6; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4497 = _T_4495 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_3986; // @[Reg.scala 27:20] - wire way_status_out_6 = _T_3986[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_657 = {{5'd0}, way_status_out_6}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4498 = _T_4497 & _GEN_657; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4491 = ifu_ic_rw_int_addr_ff == 6'h5; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_6 = _T_3986[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_657 = {{5'd0}, way_status_out_6}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4498 = _T_4497 & _GEN_657; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4491 = ifu_ic_rw_int_addr_ff == 6'h5; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4493 = _T_4491 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_3982; // @[Reg.scala 27:20] - wire way_status_out_5 = _T_3982[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_658 = {{5'd0}, way_status_out_5}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4494 = _T_4493 & _GEN_658; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4487 = ifu_ic_rw_int_addr_ff == 6'h4; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_5 = _T_3982[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_658 = {{5'd0}, way_status_out_5}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4494 = _T_4493 & _GEN_658; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4487 = ifu_ic_rw_int_addr_ff == 6'h4; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4489 = _T_4487 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_3978; // @[Reg.scala 27:20] - wire way_status_out_4 = _T_3978[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_659 = {{5'd0}, way_status_out_4}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4490 = _T_4489 & _GEN_659; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4483 = ifu_ic_rw_int_addr_ff == 6'h3; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_4 = _T_3978[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_659 = {{5'd0}, way_status_out_4}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4490 = _T_4489 & _GEN_659; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4483 = ifu_ic_rw_int_addr_ff == 6'h3; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4485 = _T_4483 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_3974; // @[Reg.scala 27:20] - wire way_status_out_3 = _T_3974[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_660 = {{5'd0}, way_status_out_3}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4486 = _T_4485 & _GEN_660; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4479 = ifu_ic_rw_int_addr_ff == 6'h2; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_3 = _T_3974[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_660 = {{5'd0}, way_status_out_3}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4486 = _T_4485 & _GEN_660; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4479 = ifu_ic_rw_int_addr_ff == 6'h2; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4481 = _T_4479 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_3970; // @[Reg.scala 27:20] - wire way_status_out_2 = _T_3970[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_661 = {{5'd0}, way_status_out_2}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4482 = _T_4481 & _GEN_661; // @[el2_ifu_mem_ctl.scala 716:130] - wire _T_4475 = ifu_ic_rw_int_addr_ff == 6'h1; // @[el2_ifu_mem_ctl.scala 716:121] + wire way_status_out_2 = _T_3970[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_661 = {{5'd0}, way_status_out_2}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4482 = _T_4481 & _GEN_661; // @[el2_ifu_mem_ctl.scala 717:130] + wire _T_4475 = ifu_ic_rw_int_addr_ff == 6'h1; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4477 = _T_4475 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_3966; // @[Reg.scala 27:20] - wire way_status_out_1 = _T_3966[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_662 = {{5'd0}, way_status_out_1}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4478 = _T_4477 & _GEN_662; // @[el2_ifu_mem_ctl.scala 716:130] + wire way_status_out_1 = _T_3966[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_662 = {{5'd0}, way_status_out_1}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4478 = _T_4477 & _GEN_662; // @[el2_ifu_mem_ctl.scala 717:130] wire [761:0] _T_5108 = {_T_5099,_T_4510,_T_4506,_T_4502,_T_4498,_T_4494,_T_4490,_T_4486,_T_4482,_T_4478}; // @[Cat.scala 29:58] - wire _T_4471 = ifu_ic_rw_int_addr_ff == 6'h0; // @[el2_ifu_mem_ctl.scala 716:121] + wire _T_4471 = ifu_ic_rw_int_addr_ff == 6'h0; // @[el2_ifu_mem_ctl.scala 717:121] wire [5:0] _T_4473 = _T_4471 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] reg [2:0] _T_3962; // @[Reg.scala 27:20] - wire way_status_out_0 = _T_3962[0]; // @[el2_ifu_mem_ctl.scala 713:30 el2_ifu_mem_ctl.scala 715:33] - wire [5:0] _GEN_663 = {{5'd0}, way_status_out_0}; // @[el2_ifu_mem_ctl.scala 716:130] - wire [5:0] _T_4474 = _T_4473 & _GEN_663; // @[el2_ifu_mem_ctl.scala 716:130] + wire way_status_out_0 = _T_3962[0]; // @[el2_ifu_mem_ctl.scala 714:30 el2_ifu_mem_ctl.scala 716:33] + wire [5:0] _GEN_663 = {{5'd0}, way_status_out_0}; // @[el2_ifu_mem_ctl.scala 717:130] + wire [5:0] _T_4474 = _T_4473 & _GEN_663; // @[el2_ifu_mem_ctl.scala 717:130] wire [767:0] _T_5109 = {_T_5108,_T_4474}; // @[Cat.scala 29:58] - wire way_status = _T_5109[0]; // @[el2_ifu_mem_ctl.scala 716:16] - wire _T_195 = ~reset_all_tags; // @[el2_ifu_mem_ctl.scala 257:96] - reg uncacheable_miss_scnd_ff; // @[el2_ifu_mem_ctl.scala 259:38] - reg [30:0] imb_scnd_ff; // @[el2_ifu_mem_ctl.scala 261:25] + wire way_status = _T_5109[0]; // @[el2_ifu_mem_ctl.scala 717:16] + wire _T_195 = ~reset_all_tags; // @[el2_ifu_mem_ctl.scala 258:96] + reg uncacheable_miss_scnd_ff; // @[el2_ifu_mem_ctl.scala 260:38] + reg [30:0] imb_scnd_ff; // @[el2_ifu_mem_ctl.scala 262:25] wire [2:0] _T_206 = bus_ifu_wr_en_ff ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] reg [2:0] ifu_bus_rid_ff; // @[Reg.scala 27:20] - wire [2:0] ic_wr_addr_bits_hi_3 = ifu_bus_rid_ff & _T_206; // @[el2_ifu_mem_ctl.scala 266:45] - wire _T_212 = _T_231 | _T_239; // @[el2_ifu_mem_ctl.scala 271:59] - wire _T_214 = _T_212 | _T_2221; // @[el2_ifu_mem_ctl.scala 271:91] - wire ic_iccm_hit_f = fetch_req_iccm_f & _T_214; // @[el2_ifu_mem_ctl.scala 271:41] - wire _T_219 = _T_227 & fetch_req_icache_f; // @[el2_ifu_mem_ctl.scala 277:39] - wire _T_221 = _T_219 & _T_195; // @[el2_ifu_mem_ctl.scala 277:60] - wire _T_225 = _T_221 & _T_212; // @[el2_ifu_mem_ctl.scala 277:78] - wire ic_act_hit_f = _T_225 & _T_247; // @[el2_ifu_mem_ctl.scala 277:126] - wire _T_262 = ic_act_hit_f | ic_byp_hit_f; // @[el2_ifu_mem_ctl.scala 284:31] - wire _T_263 = _T_262 | ic_iccm_hit_f; // @[el2_ifu_mem_ctl.scala 284:46] - wire _T_264 = ifc_region_acc_fault_final_f & ifc_fetch_req_f; // @[el2_ifu_mem_ctl.scala 284:94] - wire _T_268 = sel_hold_imb ? uncacheable_miss_ff : io_ifc_fetch_uncacheable_bf; // @[el2_ifu_mem_ctl.scala 285:84] - wire uncacheable_miss_in = scnd_miss_req ? uncacheable_miss_scnd_ff : _T_268; // @[el2_ifu_mem_ctl.scala 285:32] - wire _T_274 = imb_ff[12:6] == imb_scnd_ff[12:6]; // @[el2_ifu_mem_ctl.scala 288:75] - wire _T_275 = _T_274 & scnd_miss_req; // @[el2_ifu_mem_ctl.scala 288:127] + wire [2:0] ic_wr_addr_bits_hi_3 = ifu_bus_rid_ff & _T_206; // @[el2_ifu_mem_ctl.scala 267:45] + wire _T_212 = _T_231 | _T_239; // @[el2_ifu_mem_ctl.scala 272:59] + wire _T_214 = _T_212 | _T_2221; // @[el2_ifu_mem_ctl.scala 272:91] + wire ic_iccm_hit_f = fetch_req_iccm_f & _T_214; // @[el2_ifu_mem_ctl.scala 272:41] + wire _T_219 = _T_227 & fetch_req_icache_f; // @[el2_ifu_mem_ctl.scala 278:39] + wire _T_221 = _T_219 & _T_195; // @[el2_ifu_mem_ctl.scala 278:60] + wire _T_225 = _T_221 & _T_212; // @[el2_ifu_mem_ctl.scala 278:78] + wire ic_act_hit_f = _T_225 & _T_247; // @[el2_ifu_mem_ctl.scala 278:126] + wire _T_262 = ic_act_hit_f | ic_byp_hit_f; // @[el2_ifu_mem_ctl.scala 285:31] + wire _T_263 = _T_262 | ic_iccm_hit_f; // @[el2_ifu_mem_ctl.scala 285:46] + wire _T_264 = ifc_region_acc_fault_final_f & ifc_fetch_req_f; // @[el2_ifu_mem_ctl.scala 285:94] + wire _T_268 = sel_hold_imb ? uncacheable_miss_ff : io_ifc_fetch_uncacheable_bf; // @[el2_ifu_mem_ctl.scala 286:84] + wire uncacheable_miss_in = scnd_miss_req ? uncacheable_miss_scnd_ff : _T_268; // @[el2_ifu_mem_ctl.scala 286:32] + wire _T_274 = imb_ff[12:6] == imb_scnd_ff[12:6]; // @[el2_ifu_mem_ctl.scala 289:75] + wire _T_275 = _T_274 & scnd_miss_req; // @[el2_ifu_mem_ctl.scala 289:127] reg [1:0] ifu_bus_rresp_ff; // @[Reg.scala 27:20] - wire _T_2610 = |ifu_bus_rresp_ff; // @[el2_ifu_mem_ctl.scala 614:48] - wire _T_2611 = _T_2610 & ifu_bus_rvalid_ff; // @[el2_ifu_mem_ctl.scala 614:52] - wire bus_ifu_wr_data_error_ff = _T_2611 & miss_pending; // @[el2_ifu_mem_ctl.scala 614:73] - reg ifu_wr_data_comb_err_ff; // @[el2_ifu_mem_ctl.scala 360:61] - wire ifu_wr_cumulative_err_data = bus_ifu_wr_data_error_ff | ifu_wr_data_comb_err_ff; // @[el2_ifu_mem_ctl.scala 359:55] - wire _T_276 = ~ifu_wr_cumulative_err_data; // @[el2_ifu_mem_ctl.scala 288:145] - wire scnd_miss_index_match = _T_275 & _T_276; // @[el2_ifu_mem_ctl.scala 288:143] - wire _T_277 = ~scnd_miss_index_match; // @[el2_ifu_mem_ctl.scala 291:47] - wire _T_278 = scnd_miss_req & _T_277; // @[el2_ifu_mem_ctl.scala 291:45] - wire _T_280 = scnd_miss_req & scnd_miss_index_match; // @[el2_ifu_mem_ctl.scala 292:26] - reg way_status_mb_ff; // @[el2_ifu_mem_ctl.scala 311:30] - wire _T_10059 = ~way_status_mb_ff; // @[el2_ifu_mem_ctl.scala 769:33] - reg [1:0] tagv_mb_ff; // @[el2_ifu_mem_ctl.scala 312:24] - wire _T_10061 = _T_10059 & tagv_mb_ff[0]; // @[el2_ifu_mem_ctl.scala 769:51] - wire _T_10063 = _T_10061 & tagv_mb_ff[1]; // @[el2_ifu_mem_ctl.scala 769:67] - wire _T_10065 = ~tagv_mb_ff[0]; // @[el2_ifu_mem_ctl.scala 769:86] - wire replace_way_mb_any_0 = _T_10063 | _T_10065; // @[el2_ifu_mem_ctl.scala 769:84] + wire _T_2610 = |ifu_bus_rresp_ff; // @[el2_ifu_mem_ctl.scala 615:48] + wire _T_2611 = _T_2610 & ifu_bus_rvalid_ff; // @[el2_ifu_mem_ctl.scala 615:52] + wire bus_ifu_wr_data_error_ff = _T_2611 & miss_pending; // @[el2_ifu_mem_ctl.scala 615:73] + reg ifu_wr_data_comb_err_ff; // @[el2_ifu_mem_ctl.scala 361:61] + wire ifu_wr_cumulative_err_data = bus_ifu_wr_data_error_ff | ifu_wr_data_comb_err_ff; // @[el2_ifu_mem_ctl.scala 360:55] + wire _T_276 = ~ifu_wr_cumulative_err_data; // @[el2_ifu_mem_ctl.scala 289:145] + wire scnd_miss_index_match = _T_275 & _T_276; // @[el2_ifu_mem_ctl.scala 289:143] + wire _T_277 = ~scnd_miss_index_match; // @[el2_ifu_mem_ctl.scala 292:47] + wire _T_278 = scnd_miss_req & _T_277; // @[el2_ifu_mem_ctl.scala 292:45] + wire _T_280 = scnd_miss_req & scnd_miss_index_match; // @[el2_ifu_mem_ctl.scala 293:26] + reg way_status_mb_ff; // @[el2_ifu_mem_ctl.scala 312:30] + wire _T_10059 = ~way_status_mb_ff; // @[el2_ifu_mem_ctl.scala 770:33] + reg [1:0] tagv_mb_ff; // @[el2_ifu_mem_ctl.scala 313:24] + wire _T_10061 = _T_10059 & tagv_mb_ff[0]; // @[el2_ifu_mem_ctl.scala 770:51] + wire _T_10063 = _T_10061 & tagv_mb_ff[1]; // @[el2_ifu_mem_ctl.scala 770:67] + wire _T_10065 = ~tagv_mb_ff[0]; // @[el2_ifu_mem_ctl.scala 770:86] + wire replace_way_mb_any_0 = _T_10063 | _T_10065; // @[el2_ifu_mem_ctl.scala 770:84] wire [1:0] _T_287 = scnd_miss_index_match ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire _T_10068 = way_status_mb_ff & tagv_mb_ff[0]; // @[el2_ifu_mem_ctl.scala 770:50] - wire _T_10070 = _T_10068 & tagv_mb_ff[1]; // @[el2_ifu_mem_ctl.scala 770:66] - wire _T_10072 = ~tagv_mb_ff[1]; // @[el2_ifu_mem_ctl.scala 770:85] - wire _T_10074 = _T_10072 & tagv_mb_ff[0]; // @[el2_ifu_mem_ctl.scala 770:100] - wire replace_way_mb_any_1 = _T_10070 | _T_10074; // @[el2_ifu_mem_ctl.scala 770:83] + wire _T_10068 = way_status_mb_ff & tagv_mb_ff[0]; // @[el2_ifu_mem_ctl.scala 771:50] + wire _T_10070 = _T_10068 & tagv_mb_ff[1]; // @[el2_ifu_mem_ctl.scala 771:66] + wire _T_10072 = ~tagv_mb_ff[1]; // @[el2_ifu_mem_ctl.scala 771:85] + wire _T_10074 = _T_10072 & tagv_mb_ff[0]; // @[el2_ifu_mem_ctl.scala 771:100] + wire replace_way_mb_any_1 = _T_10070 | _T_10074; // @[el2_ifu_mem_ctl.scala 771:83] wire [1:0] _T_288 = {replace_way_mb_any_1,replace_way_mb_any_0}; // @[Cat.scala 29:58] - wire [1:0] _T_289 = _T_287 & _T_288; // @[el2_ifu_mem_ctl.scala 296:110] - wire _T_297 = ~scnd_miss_req_q; // @[el2_ifu_mem_ctl.scala 300:36] - wire _T_298 = miss_pending & _T_297; // @[el2_ifu_mem_ctl.scala 300:34] - reg reset_ic_ff; // @[el2_ifu_mem_ctl.scala 301:25] - wire _T_299 = reset_all_tags | reset_ic_ff; // @[el2_ifu_mem_ctl.scala 300:72] - wire reset_ic_in = _T_298 & _T_299; // @[el2_ifu_mem_ctl.scala 300:53] - reg fetch_uncacheable_ff; // @[el2_ifu_mem_ctl.scala 302:37] - reg [25:0] miss_addr; // @[el2_ifu_mem_ctl.scala 310:23] - wire _T_313 = _T_2236 & flush_final_f; // @[el2_ifu_mem_ctl.scala 314:87] - wire _T_314 = ~_T_313; // @[el2_ifu_mem_ctl.scala 314:55] - wire _T_315 = io_ifc_fetch_req_bf & _T_314; // @[el2_ifu_mem_ctl.scala 314:53] - wire _T_2228 = ~_T_2223; // @[el2_ifu_mem_ctl.scala 451:46] - wire _T_2229 = _T_2221 & _T_2228; // @[el2_ifu_mem_ctl.scala 451:44] - wire stream_miss_f = _T_2229 & ifc_fetch_req_f; // @[el2_ifu_mem_ctl.scala 451:84] - wire _T_316 = ~stream_miss_f; // @[el2_ifu_mem_ctl.scala 314:106] - wire ifc_fetch_req_qual_bf = _T_315 & _T_316; // @[el2_ifu_mem_ctl.scala 314:104] - reg ifc_region_acc_fault_f; // @[el2_ifu_mem_ctl.scala 320:39] + wire [1:0] _T_289 = _T_287 & _T_288; // @[el2_ifu_mem_ctl.scala 297:110] + wire _T_297 = ~scnd_miss_req_q; // @[el2_ifu_mem_ctl.scala 301:36] + wire _T_298 = miss_pending & _T_297; // @[el2_ifu_mem_ctl.scala 301:34] + reg reset_ic_ff; // @[el2_ifu_mem_ctl.scala 302:25] + wire _T_299 = reset_all_tags | reset_ic_ff; // @[el2_ifu_mem_ctl.scala 301:72] + wire reset_ic_in = _T_298 & _T_299; // @[el2_ifu_mem_ctl.scala 301:53] + reg fetch_uncacheable_ff; // @[el2_ifu_mem_ctl.scala 303:37] + reg [25:0] miss_addr; // @[el2_ifu_mem_ctl.scala 311:23] + wire _T_313 = _T_2236 & flush_final_f; // @[el2_ifu_mem_ctl.scala 315:87] + wire _T_314 = ~_T_313; // @[el2_ifu_mem_ctl.scala 315:55] + wire _T_315 = io_ifc_fetch_req_bf & _T_314; // @[el2_ifu_mem_ctl.scala 315:53] + wire _T_2228 = ~_T_2223; // @[el2_ifu_mem_ctl.scala 452:46] + wire _T_2229 = _T_2221 & _T_2228; // @[el2_ifu_mem_ctl.scala 452:44] + wire stream_miss_f = _T_2229 & ifc_fetch_req_f; // @[el2_ifu_mem_ctl.scala 452:84] + wire _T_316 = ~stream_miss_f; // @[el2_ifu_mem_ctl.scala 315:106] + wire ifc_fetch_req_qual_bf = _T_315 & _T_316; // @[el2_ifu_mem_ctl.scala 315:104] + reg ifc_region_acc_fault_f; // @[el2_ifu_mem_ctl.scala 321:39] reg [2:0] bus_rd_addr_count; // @[Reg.scala 27:20] wire [28:0] ifu_ic_req_addr_f = {miss_addr,bus_rd_addr_count}; // @[Cat.scala 29:58] - wire _T_323 = _T_239 | _T_2221; // @[el2_ifu_mem_ctl.scala 322:55] - wire _T_326 = _T_323 & _T_56; // @[el2_ifu_mem_ctl.scala 322:82] - wire _T_2242 = ~ifu_bus_rid_ff[0]; // @[el2_ifu_mem_ctl.scala 456:55] + wire _T_323 = _T_239 | _T_2221; // @[el2_ifu_mem_ctl.scala 323:55] + wire _T_326 = _T_323 & _T_56; // @[el2_ifu_mem_ctl.scala 323:82] + wire _T_2242 = ~ifu_bus_rid_ff[0]; // @[el2_ifu_mem_ctl.scala 457:55] wire [2:0] other_tag = {ifu_bus_rid_ff[2:1],_T_2242}; // @[Cat.scala 29:58] - wire _T_2243 = other_tag == 3'h0; // @[el2_ifu_mem_ctl.scala 457:81] + wire _T_2243 = other_tag == 3'h0; // @[el2_ifu_mem_ctl.scala 458:81] wire _T_2267 = _T_2243 & ic_miss_buff_data_valid[0]; // @[Mux.scala 27:72] - wire _T_2246 = other_tag == 3'h1; // @[el2_ifu_mem_ctl.scala 457:81] + wire _T_2246 = other_tag == 3'h1; // @[el2_ifu_mem_ctl.scala 458:81] wire _T_2268 = _T_2246 & ic_miss_buff_data_valid[1]; // @[Mux.scala 27:72] wire _T_2275 = _T_2267 | _T_2268; // @[Mux.scala 27:72] - wire _T_2249 = other_tag == 3'h2; // @[el2_ifu_mem_ctl.scala 457:81] + wire _T_2249 = other_tag == 3'h2; // @[el2_ifu_mem_ctl.scala 458:81] wire _T_2269 = _T_2249 & ic_miss_buff_data_valid[2]; // @[Mux.scala 27:72] wire _T_2276 = _T_2275 | _T_2269; // @[Mux.scala 27:72] - wire _T_2252 = other_tag == 3'h3; // @[el2_ifu_mem_ctl.scala 457:81] + wire _T_2252 = other_tag == 3'h3; // @[el2_ifu_mem_ctl.scala 458:81] wire _T_2270 = _T_2252 & ic_miss_buff_data_valid[3]; // @[Mux.scala 27:72] wire _T_2277 = _T_2276 | _T_2270; // @[Mux.scala 27:72] - wire _T_2255 = other_tag == 3'h4; // @[el2_ifu_mem_ctl.scala 457:81] + wire _T_2255 = other_tag == 3'h4; // @[el2_ifu_mem_ctl.scala 458:81] wire _T_2271 = _T_2255 & ic_miss_buff_data_valid[4]; // @[Mux.scala 27:72] wire _T_2278 = _T_2277 | _T_2271; // @[Mux.scala 27:72] - wire _T_2258 = other_tag == 3'h5; // @[el2_ifu_mem_ctl.scala 457:81] + wire _T_2258 = other_tag == 3'h5; // @[el2_ifu_mem_ctl.scala 458:81] wire _T_2272 = _T_2258 & ic_miss_buff_data_valid[5]; // @[Mux.scala 27:72] wire _T_2279 = _T_2278 | _T_2272; // @[Mux.scala 27:72] - wire _T_2261 = other_tag == 3'h6; // @[el2_ifu_mem_ctl.scala 457:81] + wire _T_2261 = other_tag == 3'h6; // @[el2_ifu_mem_ctl.scala 458:81] wire _T_2273 = _T_2261 & ic_miss_buff_data_valid[6]; // @[Mux.scala 27:72] wire _T_2280 = _T_2279 | _T_2273; // @[Mux.scala 27:72] - wire _T_2264 = other_tag == 3'h7; // @[el2_ifu_mem_ctl.scala 457:81] + wire _T_2264 = other_tag == 3'h7; // @[el2_ifu_mem_ctl.scala 458:81] wire _T_2274 = _T_2264 & ic_miss_buff_data_valid[7]; // @[Mux.scala 27:72] wire second_half_available = _T_2280 | _T_2274; // @[Mux.scala 27:72] - wire write_ic_16_bytes = second_half_available & bus_ifu_wr_en_ff; // @[el2_ifu_mem_ctl.scala 458:46] - wire _T_330 = miss_pending & write_ic_16_bytes; // @[el2_ifu_mem_ctl.scala 326:35] - wire _T_332 = _T_330 & _T_17; // @[el2_ifu_mem_ctl.scala 326:55] - reg ic_act_miss_f_delayed; // @[el2_ifu_mem_ctl.scala 611:61] - wire _T_2604 = ic_act_miss_f_delayed & _T_2237; // @[el2_ifu_mem_ctl.scala 612:53] - wire reset_tag_valid_for_miss = _T_2604 & _T_17; // @[el2_ifu_mem_ctl.scala 612:84] - wire sel_mb_addr = _T_332 | reset_tag_valid_for_miss; // @[el2_ifu_mem_ctl.scala 326:79] + wire write_ic_16_bytes = second_half_available & bus_ifu_wr_en_ff; // @[el2_ifu_mem_ctl.scala 459:46] + wire _T_330 = miss_pending & write_ic_16_bytes; // @[el2_ifu_mem_ctl.scala 327:35] + wire _T_332 = _T_330 & _T_17; // @[el2_ifu_mem_ctl.scala 327:55] + reg ic_act_miss_f_delayed; // @[el2_ifu_mem_ctl.scala 612:61] + wire _T_2604 = ic_act_miss_f_delayed & _T_2237; // @[el2_ifu_mem_ctl.scala 613:53] + wire reset_tag_valid_for_miss = _T_2604 & _T_17; // @[el2_ifu_mem_ctl.scala 613:84] + wire sel_mb_addr = _T_332 | reset_tag_valid_for_miss; // @[el2_ifu_mem_ctl.scala 327:79] wire [30:0] _T_337 = {imb_ff[30:5],ic_wr_addr_bits_hi_3,imb_ff[1:0]}; // @[Cat.scala 29:58] - wire _T_339 = ~sel_mb_addr; // @[el2_ifu_mem_ctl.scala 328:37] + wire _T_339 = ~sel_mb_addr; // @[el2_ifu_mem_ctl.scala 329:37] wire [30:0] _T_340 = sel_mb_addr ? _T_337 : 31'h0; // @[Mux.scala 27:72] - wire [30:0] _T_341 = _T_339 ? ifu_fetch_addr_int_f : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_341 = _T_339 ? io_ifc_fetch_addr_bf : 31'h0; // @[Mux.scala 27:72] wire [30:0] ifu_ic_rw_int_addr = _T_340 | _T_341; // @[Mux.scala 27:72] - wire _T_346 = _T_332 & last_beat; // @[el2_ifu_mem_ctl.scala 330:84] - wire _T_2598 = ~_T_2610; // @[el2_ifu_mem_ctl.scala 609:84] - wire _T_2599 = _T_100 & _T_2598; // @[el2_ifu_mem_ctl.scala 609:82] - wire bus_ifu_wr_en_ff_q = _T_2599 & write_ic_16_bytes; // @[el2_ifu_mem_ctl.scala 609:108] - wire sel_mb_status_addr = _T_346 & bus_ifu_wr_en_ff_q; // @[el2_ifu_mem_ctl.scala 330:96] - wire [30:0] ifu_status_wr_addr = sel_mb_status_addr ? _T_337 : ifu_fetch_addr_int_f; // @[el2_ifu_mem_ctl.scala 331:31] + wire _T_346 = _T_332 & last_beat; // @[el2_ifu_mem_ctl.scala 331:84] + wire _T_2598 = ~_T_2610; // @[el2_ifu_mem_ctl.scala 610:84] + wire _T_2599 = _T_100 & _T_2598; // @[el2_ifu_mem_ctl.scala 610:82] + wire bus_ifu_wr_en_ff_q = _T_2599 & write_ic_16_bytes; // @[el2_ifu_mem_ctl.scala 610:108] + wire sel_mb_status_addr = _T_346 & bus_ifu_wr_en_ff_q; // @[el2_ifu_mem_ctl.scala 331:96] + wire [30:0] ifu_status_wr_addr = sel_mb_status_addr ? _T_337 : ifu_fetch_addr_int_f; // @[el2_ifu_mem_ctl.scala 332:31] reg [63:0] ifu_bus_rdata_ff; // @[Reg.scala 27:20] wire [7:0] _T_570 = {ifu_bus_rdata_ff[11],ifu_bus_rdata_ff[10],ifu_bus_rdata_ff[8],ifu_bus_rdata_ff[6],ifu_bus_rdata_ff[4],ifu_bus_rdata_ff[3],ifu_bus_rdata_ff[1],ifu_bus_rdata_ff[0]}; // @[el2_lib.scala 348:27] wire [16:0] _T_579 = {ifu_bus_rdata_ff[28],ifu_bus_rdata_ff[26],ifu_bus_rdata_ff[25],ifu_bus_rdata_ff[23],ifu_bus_rdata_ff[21],ifu_bus_rdata_ff[19],ifu_bus_rdata_ff[17],ifu_bus_rdata_ff[15],ifu_bus_rdata_ff[13],_T_570}; // @[el2_lib.scala 348:27] @@ -1904,107 +1904,107 @@ module el2_ifu_mem_ctl( wire [6:0] _T_767 = {ifu_bus_rdata_ff[63],ifu_bus_rdata_ff[62],ifu_bus_rdata_ff[61],ifu_bus_rdata_ff[60],ifu_bus_rdata_ff[59],ifu_bus_rdata_ff[58],ifu_bus_rdata_ff[57]}; // @[el2_lib.scala 348:129] wire _T_768 = ^_T_767; // @[el2_lib.scala 348:136] wire [3:0] _T_2283 = {ifu_bus_rid_ff[2:1],_T_2242,1'h1}; // @[Cat.scala 29:58] - wire _T_2284 = _T_2283 == 4'h0; // @[el2_ifu_mem_ctl.scala 459:89] + wire _T_2284 = _T_2283 == 4'h0; // @[el2_ifu_mem_ctl.scala 460:89] reg [63:0] _T_1295; // @[Reg.scala 27:20] - wire [31:0] ic_miss_buff_data_0 = _T_1295[31:0]; // @[el2_ifu_mem_ctl.scala 392:31 el2_ifu_mem_ctl.scala 394:26] + wire [31:0] ic_miss_buff_data_0 = _T_1295[31:0]; // @[el2_ifu_mem_ctl.scala 393:31 el2_ifu_mem_ctl.scala 395:26] wire [31:0] _T_2331 = _T_2284 ? ic_miss_buff_data_0 : 32'h0; // @[Mux.scala 27:72] - wire _T_2287 = _T_2283 == 4'h1; // @[el2_ifu_mem_ctl.scala 459:89] + wire _T_2287 = _T_2283 == 4'h1; // @[el2_ifu_mem_ctl.scala 460:89] reg [63:0] _T_1297; // @[Reg.scala 27:20] - wire [31:0] ic_miss_buff_data_1 = _T_1297[31:0]; // @[el2_ifu_mem_ctl.scala 392:31 el2_ifu_mem_ctl.scala 395:28] + wire [31:0] ic_miss_buff_data_1 = _T_1297[31:0]; // @[el2_ifu_mem_ctl.scala 393:31 el2_ifu_mem_ctl.scala 396:28] wire [31:0] _T_2332 = _T_2287 ? ic_miss_buff_data_1 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_2347 = _T_2331 | _T_2332; // @[Mux.scala 27:72] - wire _T_2290 = _T_2283 == 4'h2; // @[el2_ifu_mem_ctl.scala 459:89] + wire _T_2290 = _T_2283 == 4'h2; // @[el2_ifu_mem_ctl.scala 460:89] reg [63:0] _T_1299; // @[Reg.scala 27:20] - wire [31:0] ic_miss_buff_data_2 = _T_1299[31:0]; // @[el2_ifu_mem_ctl.scala 392:31 el2_ifu_mem_ctl.scala 394:26] + wire [31:0] ic_miss_buff_data_2 = _T_1299[31:0]; // @[el2_ifu_mem_ctl.scala 393:31 el2_ifu_mem_ctl.scala 395:26] wire [31:0] _T_2333 = _T_2290 ? ic_miss_buff_data_2 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_2348 = _T_2347 | _T_2333; // @[Mux.scala 27:72] - wire _T_2293 = _T_2283 == 4'h3; // @[el2_ifu_mem_ctl.scala 459:89] + wire _T_2293 = _T_2283 == 4'h3; // @[el2_ifu_mem_ctl.scala 460:89] reg [63:0] _T_1301; // @[Reg.scala 27:20] - wire [31:0] ic_miss_buff_data_3 = _T_1301[31:0]; // @[el2_ifu_mem_ctl.scala 392:31 el2_ifu_mem_ctl.scala 395:28] + wire [31:0] ic_miss_buff_data_3 = _T_1301[31:0]; // @[el2_ifu_mem_ctl.scala 393:31 el2_ifu_mem_ctl.scala 396:28] wire [31:0] _T_2334 = _T_2293 ? ic_miss_buff_data_3 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_2349 = _T_2348 | _T_2334; // @[Mux.scala 27:72] - wire _T_2296 = _T_2283 == 4'h4; // @[el2_ifu_mem_ctl.scala 459:89] + wire _T_2296 = _T_2283 == 4'h4; // @[el2_ifu_mem_ctl.scala 460:89] reg [63:0] _T_1303; // @[Reg.scala 27:20] - wire [31:0] ic_miss_buff_data_4 = _T_1303[31:0]; // @[el2_ifu_mem_ctl.scala 392:31 el2_ifu_mem_ctl.scala 394:26] + wire [31:0] ic_miss_buff_data_4 = _T_1303[31:0]; // @[el2_ifu_mem_ctl.scala 393:31 el2_ifu_mem_ctl.scala 395:26] wire [31:0] _T_2335 = _T_2296 ? ic_miss_buff_data_4 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_2350 = _T_2349 | _T_2335; // @[Mux.scala 27:72] - wire _T_2299 = _T_2283 == 4'h5; // @[el2_ifu_mem_ctl.scala 459:89] + wire _T_2299 = _T_2283 == 4'h5; // @[el2_ifu_mem_ctl.scala 460:89] reg [63:0] _T_1305; // @[Reg.scala 27:20] - wire [31:0] ic_miss_buff_data_5 = _T_1305[31:0]; // @[el2_ifu_mem_ctl.scala 392:31 el2_ifu_mem_ctl.scala 395:28] + wire [31:0] ic_miss_buff_data_5 = _T_1305[31:0]; // @[el2_ifu_mem_ctl.scala 393:31 el2_ifu_mem_ctl.scala 396:28] wire [31:0] _T_2336 = _T_2299 ? ic_miss_buff_data_5 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_2351 = _T_2350 | _T_2336; // @[Mux.scala 27:72] - wire _T_2302 = _T_2283 == 4'h6; // @[el2_ifu_mem_ctl.scala 459:89] + wire _T_2302 = _T_2283 == 4'h6; // @[el2_ifu_mem_ctl.scala 460:89] reg [63:0] _T_1307; // @[Reg.scala 27:20] - wire [31:0] ic_miss_buff_data_6 = _T_1307[31:0]; // @[el2_ifu_mem_ctl.scala 392:31 el2_ifu_mem_ctl.scala 394:26] + wire [31:0] ic_miss_buff_data_6 = _T_1307[31:0]; // @[el2_ifu_mem_ctl.scala 393:31 el2_ifu_mem_ctl.scala 395:26] wire [31:0] _T_2337 = _T_2302 ? ic_miss_buff_data_6 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_2352 = _T_2351 | _T_2337; // @[Mux.scala 27:72] - wire _T_2305 = _T_2283 == 4'h7; // @[el2_ifu_mem_ctl.scala 459:89] + wire _T_2305 = _T_2283 == 4'h7; // @[el2_ifu_mem_ctl.scala 460:89] reg [63:0] _T_1309; // @[Reg.scala 27:20] - wire [31:0] ic_miss_buff_data_7 = _T_1309[31:0]; // @[el2_ifu_mem_ctl.scala 392:31 el2_ifu_mem_ctl.scala 395:28] + wire [31:0] ic_miss_buff_data_7 = _T_1309[31:0]; // @[el2_ifu_mem_ctl.scala 393:31 el2_ifu_mem_ctl.scala 396:28] wire [31:0] _T_2338 = _T_2305 ? ic_miss_buff_data_7 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_2353 = _T_2352 | _T_2338; // @[Mux.scala 27:72] - wire _T_2308 = _T_2283 == 4'h8; // @[el2_ifu_mem_ctl.scala 459:89] + wire _T_2308 = _T_2283 == 4'h8; // @[el2_ifu_mem_ctl.scala 460:89] reg [63:0] _T_1311; // @[Reg.scala 27:20] - wire [31:0] ic_miss_buff_data_8 = _T_1311[31:0]; // @[el2_ifu_mem_ctl.scala 392:31 el2_ifu_mem_ctl.scala 394:26] + wire [31:0] ic_miss_buff_data_8 = _T_1311[31:0]; // @[el2_ifu_mem_ctl.scala 393:31 el2_ifu_mem_ctl.scala 395:26] wire [31:0] _T_2339 = _T_2308 ? ic_miss_buff_data_8 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_2354 = _T_2353 | _T_2339; // @[Mux.scala 27:72] - wire _T_2311 = _T_2283 == 4'h9; // @[el2_ifu_mem_ctl.scala 459:89] + wire _T_2311 = _T_2283 == 4'h9; // @[el2_ifu_mem_ctl.scala 460:89] reg [63:0] _T_1313; // @[Reg.scala 27:20] - wire [31:0] ic_miss_buff_data_9 = _T_1313[31:0]; // @[el2_ifu_mem_ctl.scala 392:31 el2_ifu_mem_ctl.scala 395:28] + wire [31:0] ic_miss_buff_data_9 = _T_1313[31:0]; // @[el2_ifu_mem_ctl.scala 393:31 el2_ifu_mem_ctl.scala 396:28] wire [31:0] _T_2340 = _T_2311 ? ic_miss_buff_data_9 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_2355 = _T_2354 | _T_2340; // @[Mux.scala 27:72] - wire _T_2314 = _T_2283 == 4'ha; // @[el2_ifu_mem_ctl.scala 459:89] + wire _T_2314 = _T_2283 == 4'ha; // @[el2_ifu_mem_ctl.scala 460:89] reg [63:0] _T_1315; // @[Reg.scala 27:20] - wire [31:0] ic_miss_buff_data_10 = _T_1315[31:0]; // @[el2_ifu_mem_ctl.scala 392:31 el2_ifu_mem_ctl.scala 394:26] + wire [31:0] ic_miss_buff_data_10 = _T_1315[31:0]; // @[el2_ifu_mem_ctl.scala 393:31 el2_ifu_mem_ctl.scala 395:26] wire [31:0] _T_2341 = _T_2314 ? ic_miss_buff_data_10 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_2356 = _T_2355 | _T_2341; // @[Mux.scala 27:72] - wire _T_2317 = _T_2283 == 4'hb; // @[el2_ifu_mem_ctl.scala 459:89] + wire _T_2317 = _T_2283 == 4'hb; // @[el2_ifu_mem_ctl.scala 460:89] reg [63:0] _T_1317; // @[Reg.scala 27:20] - wire [31:0] ic_miss_buff_data_11 = _T_1317[31:0]; // @[el2_ifu_mem_ctl.scala 392:31 el2_ifu_mem_ctl.scala 395:28] + wire [31:0] ic_miss_buff_data_11 = _T_1317[31:0]; // @[el2_ifu_mem_ctl.scala 393:31 el2_ifu_mem_ctl.scala 396:28] wire [31:0] _T_2342 = _T_2317 ? ic_miss_buff_data_11 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_2357 = _T_2356 | _T_2342; // @[Mux.scala 27:72] - wire _T_2320 = _T_2283 == 4'hc; // @[el2_ifu_mem_ctl.scala 459:89] + wire _T_2320 = _T_2283 == 4'hc; // @[el2_ifu_mem_ctl.scala 460:89] reg [63:0] _T_1319; // @[Reg.scala 27:20] - wire [31:0] ic_miss_buff_data_12 = _T_1319[31:0]; // @[el2_ifu_mem_ctl.scala 392:31 el2_ifu_mem_ctl.scala 394:26] + wire [31:0] ic_miss_buff_data_12 = _T_1319[31:0]; // @[el2_ifu_mem_ctl.scala 393:31 el2_ifu_mem_ctl.scala 395:26] wire [31:0] _T_2343 = _T_2320 ? ic_miss_buff_data_12 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_2358 = _T_2357 | _T_2343; // @[Mux.scala 27:72] - wire _T_2323 = _T_2283 == 4'hd; // @[el2_ifu_mem_ctl.scala 459:89] + wire _T_2323 = _T_2283 == 4'hd; // @[el2_ifu_mem_ctl.scala 460:89] reg [63:0] _T_1321; // @[Reg.scala 27:20] - wire [31:0] ic_miss_buff_data_13 = _T_1321[31:0]; // @[el2_ifu_mem_ctl.scala 392:31 el2_ifu_mem_ctl.scala 395:28] + wire [31:0] ic_miss_buff_data_13 = _T_1321[31:0]; // @[el2_ifu_mem_ctl.scala 393:31 el2_ifu_mem_ctl.scala 396:28] wire [31:0] _T_2344 = _T_2323 ? ic_miss_buff_data_13 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_2359 = _T_2358 | _T_2344; // @[Mux.scala 27:72] - wire _T_2326 = _T_2283 == 4'he; // @[el2_ifu_mem_ctl.scala 459:89] + wire _T_2326 = _T_2283 == 4'he; // @[el2_ifu_mem_ctl.scala 460:89] reg [63:0] _T_1323; // @[Reg.scala 27:20] - wire [31:0] ic_miss_buff_data_14 = _T_1323[31:0]; // @[el2_ifu_mem_ctl.scala 392:31 el2_ifu_mem_ctl.scala 394:26] + wire [31:0] ic_miss_buff_data_14 = _T_1323[31:0]; // @[el2_ifu_mem_ctl.scala 393:31 el2_ifu_mem_ctl.scala 395:26] wire [31:0] _T_2345 = _T_2326 ? ic_miss_buff_data_14 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_2360 = _T_2359 | _T_2345; // @[Mux.scala 27:72] - wire _T_2329 = _T_2283 == 4'hf; // @[el2_ifu_mem_ctl.scala 459:89] + wire _T_2329 = _T_2283 == 4'hf; // @[el2_ifu_mem_ctl.scala 460:89] reg [63:0] _T_1325; // @[Reg.scala 27:20] - wire [31:0] ic_miss_buff_data_15 = _T_1325[31:0]; // @[el2_ifu_mem_ctl.scala 392:31 el2_ifu_mem_ctl.scala 395:28] + wire [31:0] ic_miss_buff_data_15 = _T_1325[31:0]; // @[el2_ifu_mem_ctl.scala 393:31 el2_ifu_mem_ctl.scala 396:28] wire [31:0] _T_2346 = _T_2329 ? ic_miss_buff_data_15 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_2361 = _T_2360 | _T_2346; // @[Mux.scala 27:72] wire [3:0] _T_2363 = {ifu_bus_rid_ff[2:1],_T_2242,1'h0}; // @[Cat.scala 29:58] - wire _T_2364 = _T_2363 == 4'h0; // @[el2_ifu_mem_ctl.scala 460:64] + wire _T_2364 = _T_2363 == 4'h0; // @[el2_ifu_mem_ctl.scala 461:64] wire [31:0] _T_2387 = _T_2364 ? ic_miss_buff_data_0 : 32'h0; // @[Mux.scala 27:72] - wire _T_2367 = _T_2363 == 4'h1; // @[el2_ifu_mem_ctl.scala 460:64] + wire _T_2367 = _T_2363 == 4'h1; // @[el2_ifu_mem_ctl.scala 461:64] wire [31:0] _T_2388 = _T_2367 ? ic_miss_buff_data_1 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_2395 = _T_2387 | _T_2388; // @[Mux.scala 27:72] - wire _T_2370 = _T_2363 == 4'h2; // @[el2_ifu_mem_ctl.scala 460:64] + wire _T_2370 = _T_2363 == 4'h2; // @[el2_ifu_mem_ctl.scala 461:64] wire [31:0] _T_2389 = _T_2370 ? ic_miss_buff_data_2 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_2396 = _T_2395 | _T_2389; // @[Mux.scala 27:72] - wire _T_2373 = _T_2363 == 4'h3; // @[el2_ifu_mem_ctl.scala 460:64] + wire _T_2373 = _T_2363 == 4'h3; // @[el2_ifu_mem_ctl.scala 461:64] wire [31:0] _T_2390 = _T_2373 ? ic_miss_buff_data_3 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_2397 = _T_2396 | _T_2390; // @[Mux.scala 27:72] - wire _T_2376 = _T_2363 == 4'h4; // @[el2_ifu_mem_ctl.scala 460:64] + wire _T_2376 = _T_2363 == 4'h4; // @[el2_ifu_mem_ctl.scala 461:64] wire [31:0] _T_2391 = _T_2376 ? ic_miss_buff_data_4 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_2398 = _T_2397 | _T_2391; // @[Mux.scala 27:72] - wire _T_2379 = _T_2363 == 4'h5; // @[el2_ifu_mem_ctl.scala 460:64] + wire _T_2379 = _T_2363 == 4'h5; // @[el2_ifu_mem_ctl.scala 461:64] wire [31:0] _T_2392 = _T_2379 ? ic_miss_buff_data_5 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_2399 = _T_2398 | _T_2392; // @[Mux.scala 27:72] - wire _T_2382 = _T_2363 == 4'h6; // @[el2_ifu_mem_ctl.scala 460:64] + wire _T_2382 = _T_2363 == 4'h6; // @[el2_ifu_mem_ctl.scala 461:64] wire [31:0] _T_2393 = _T_2382 ? ic_miss_buff_data_6 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_2400 = _T_2399 | _T_2393; // @[Mux.scala 27:72] - wire _T_2385 = _T_2363 == 4'h7; // @[el2_ifu_mem_ctl.scala 460:64] + wire _T_2385 = _T_2363 == 4'h7; // @[el2_ifu_mem_ctl.scala 461:64] wire [31:0] _T_2394 = _T_2385 ? ic_miss_buff_data_7 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_2401 = _T_2400 | _T_2394; // @[Mux.scala 27:72] wire [63:0] ic_miss_buff_half = {_T_2361,_T_2401}; // @[Cat.scala 29:58] @@ -2046,130 +2046,130 @@ module el2_ifu_mem_ctl( wire [70:0] _T_1236 = {_T_1020,_T_1055,_T_1090,_T_1121,_T_1152,_T_1183,_T_1190,_T_2361,_T_2401}; // @[Cat.scala 29:58] wire [141:0] _T_1238 = {_T_598,_T_633,_T_668,_T_699,_T_730,_T_761,_T_768,ifu_bus_rdata_ff,_T_1236}; // @[Cat.scala 29:58] wire [141:0] _T_1241 = {_T_1020,_T_1055,_T_1090,_T_1121,_T_1152,_T_1183,_T_1190,_T_2361,_T_2401,_T_1237}; // @[Cat.scala 29:58] - wire [141:0] ic_wr_16bytes_data = ifu_bus_rid_ff[0] ? _T_1238 : _T_1241; // @[el2_ifu_mem_ctl.scala 352:28] - wire _T_1198 = |io_ic_eccerr; // @[el2_ifu_mem_ctl.scala 342:56] - wire _T_1199 = _T_1198 & ic_act_hit_f; // @[el2_ifu_mem_ctl.scala 342:83] - wire [4:0] bypass_index = imb_ff[4:0]; // @[el2_ifu_mem_ctl.scala 406:28] - wire _T_1401 = bypass_index[4:2] == 3'h0; // @[el2_ifu_mem_ctl.scala 408:114] - wire bus_ifu_wr_en = _T_13 & miss_pending; // @[el2_ifu_mem_ctl.scala 607:35] - wire _T_1286 = io_ifu_axi_rid == 3'h0; // @[el2_ifu_mem_ctl.scala 391:91] - wire write_fill_data_0 = bus_ifu_wr_en & _T_1286; // @[el2_ifu_mem_ctl.scala 391:73] - wire _T_1327 = ~ic_act_miss_f; // @[el2_ifu_mem_ctl.scala 397:118] - wire _T_1328 = ic_miss_buff_data_valid[0] & _T_1327; // @[el2_ifu_mem_ctl.scala 397:116] - wire ic_miss_buff_data_valid_in_0 = write_fill_data_0 | _T_1328; // @[el2_ifu_mem_ctl.scala 397:88] + wire [141:0] ic_wr_16bytes_data = ifu_bus_rid_ff[0] ? _T_1238 : _T_1241; // @[el2_ifu_mem_ctl.scala 353:28] + wire _T_1198 = |io_ic_eccerr; // @[el2_ifu_mem_ctl.scala 343:56] + wire _T_1199 = _T_1198 & ic_act_hit_f; // @[el2_ifu_mem_ctl.scala 343:83] + wire [4:0] bypass_index = imb_ff[4:0]; // @[el2_ifu_mem_ctl.scala 407:28] + wire _T_1401 = bypass_index[4:2] == 3'h0; // @[el2_ifu_mem_ctl.scala 409:114] + wire bus_ifu_wr_en = _T_13 & miss_pending; // @[el2_ifu_mem_ctl.scala 608:35] + wire _T_1286 = io_ifu_axi_rid == 3'h0; // @[el2_ifu_mem_ctl.scala 392:91] + wire write_fill_data_0 = bus_ifu_wr_en & _T_1286; // @[el2_ifu_mem_ctl.scala 392:73] + wire _T_1327 = ~ic_act_miss_f; // @[el2_ifu_mem_ctl.scala 398:118] + wire _T_1328 = ic_miss_buff_data_valid[0] & _T_1327; // @[el2_ifu_mem_ctl.scala 398:116] + wire ic_miss_buff_data_valid_in_0 = write_fill_data_0 | _T_1328; // @[el2_ifu_mem_ctl.scala 398:88] wire _T_1424 = _T_1401 & ic_miss_buff_data_valid_in_0; // @[Mux.scala 27:72] - wire _T_1404 = bypass_index[4:2] == 3'h1; // @[el2_ifu_mem_ctl.scala 408:114] - wire _T_1287 = io_ifu_axi_rid == 3'h1; // @[el2_ifu_mem_ctl.scala 391:91] - wire write_fill_data_1 = bus_ifu_wr_en & _T_1287; // @[el2_ifu_mem_ctl.scala 391:73] - wire _T_1331 = ic_miss_buff_data_valid[1] & _T_1327; // @[el2_ifu_mem_ctl.scala 397:116] - wire ic_miss_buff_data_valid_in_1 = write_fill_data_1 | _T_1331; // @[el2_ifu_mem_ctl.scala 397:88] + wire _T_1404 = bypass_index[4:2] == 3'h1; // @[el2_ifu_mem_ctl.scala 409:114] + wire _T_1287 = io_ifu_axi_rid == 3'h1; // @[el2_ifu_mem_ctl.scala 392:91] + wire write_fill_data_1 = bus_ifu_wr_en & _T_1287; // @[el2_ifu_mem_ctl.scala 392:73] + wire _T_1331 = ic_miss_buff_data_valid[1] & _T_1327; // @[el2_ifu_mem_ctl.scala 398:116] + wire ic_miss_buff_data_valid_in_1 = write_fill_data_1 | _T_1331; // @[el2_ifu_mem_ctl.scala 398:88] wire _T_1425 = _T_1404 & ic_miss_buff_data_valid_in_1; // @[Mux.scala 27:72] wire _T_1432 = _T_1424 | _T_1425; // @[Mux.scala 27:72] - wire _T_1407 = bypass_index[4:2] == 3'h2; // @[el2_ifu_mem_ctl.scala 408:114] - wire _T_1288 = io_ifu_axi_rid == 3'h2; // @[el2_ifu_mem_ctl.scala 391:91] - wire write_fill_data_2 = bus_ifu_wr_en & _T_1288; // @[el2_ifu_mem_ctl.scala 391:73] - wire _T_1334 = ic_miss_buff_data_valid[2] & _T_1327; // @[el2_ifu_mem_ctl.scala 397:116] - wire ic_miss_buff_data_valid_in_2 = write_fill_data_2 | _T_1334; // @[el2_ifu_mem_ctl.scala 397:88] + wire _T_1407 = bypass_index[4:2] == 3'h2; // @[el2_ifu_mem_ctl.scala 409:114] + wire _T_1288 = io_ifu_axi_rid == 3'h2; // @[el2_ifu_mem_ctl.scala 392:91] + wire write_fill_data_2 = bus_ifu_wr_en & _T_1288; // @[el2_ifu_mem_ctl.scala 392:73] + wire _T_1334 = ic_miss_buff_data_valid[2] & _T_1327; // @[el2_ifu_mem_ctl.scala 398:116] + wire ic_miss_buff_data_valid_in_2 = write_fill_data_2 | _T_1334; // @[el2_ifu_mem_ctl.scala 398:88] wire _T_1426 = _T_1407 & ic_miss_buff_data_valid_in_2; // @[Mux.scala 27:72] wire _T_1433 = _T_1432 | _T_1426; // @[Mux.scala 27:72] - wire _T_1410 = bypass_index[4:2] == 3'h3; // @[el2_ifu_mem_ctl.scala 408:114] - wire _T_1289 = io_ifu_axi_rid == 3'h3; // @[el2_ifu_mem_ctl.scala 391:91] - wire write_fill_data_3 = bus_ifu_wr_en & _T_1289; // @[el2_ifu_mem_ctl.scala 391:73] - wire _T_1337 = ic_miss_buff_data_valid[3] & _T_1327; // @[el2_ifu_mem_ctl.scala 397:116] - wire ic_miss_buff_data_valid_in_3 = write_fill_data_3 | _T_1337; // @[el2_ifu_mem_ctl.scala 397:88] + wire _T_1410 = bypass_index[4:2] == 3'h3; // @[el2_ifu_mem_ctl.scala 409:114] + wire _T_1289 = io_ifu_axi_rid == 3'h3; // @[el2_ifu_mem_ctl.scala 392:91] + wire write_fill_data_3 = bus_ifu_wr_en & _T_1289; // @[el2_ifu_mem_ctl.scala 392:73] + wire _T_1337 = ic_miss_buff_data_valid[3] & _T_1327; // @[el2_ifu_mem_ctl.scala 398:116] + wire ic_miss_buff_data_valid_in_3 = write_fill_data_3 | _T_1337; // @[el2_ifu_mem_ctl.scala 398:88] wire _T_1427 = _T_1410 & ic_miss_buff_data_valid_in_3; // @[Mux.scala 27:72] wire _T_1434 = _T_1433 | _T_1427; // @[Mux.scala 27:72] - wire _T_1413 = bypass_index[4:2] == 3'h4; // @[el2_ifu_mem_ctl.scala 408:114] - wire _T_1290 = io_ifu_axi_rid == 3'h4; // @[el2_ifu_mem_ctl.scala 391:91] - wire write_fill_data_4 = bus_ifu_wr_en & _T_1290; // @[el2_ifu_mem_ctl.scala 391:73] - wire _T_1340 = ic_miss_buff_data_valid[4] & _T_1327; // @[el2_ifu_mem_ctl.scala 397:116] - wire ic_miss_buff_data_valid_in_4 = write_fill_data_4 | _T_1340; // @[el2_ifu_mem_ctl.scala 397:88] + wire _T_1413 = bypass_index[4:2] == 3'h4; // @[el2_ifu_mem_ctl.scala 409:114] + wire _T_1290 = io_ifu_axi_rid == 3'h4; // @[el2_ifu_mem_ctl.scala 392:91] + wire write_fill_data_4 = bus_ifu_wr_en & _T_1290; // @[el2_ifu_mem_ctl.scala 392:73] + wire _T_1340 = ic_miss_buff_data_valid[4] & _T_1327; // @[el2_ifu_mem_ctl.scala 398:116] + wire ic_miss_buff_data_valid_in_4 = write_fill_data_4 | _T_1340; // @[el2_ifu_mem_ctl.scala 398:88] wire _T_1428 = _T_1413 & ic_miss_buff_data_valid_in_4; // @[Mux.scala 27:72] wire _T_1435 = _T_1434 | _T_1428; // @[Mux.scala 27:72] - wire _T_1416 = bypass_index[4:2] == 3'h5; // @[el2_ifu_mem_ctl.scala 408:114] - wire _T_1291 = io_ifu_axi_rid == 3'h5; // @[el2_ifu_mem_ctl.scala 391:91] - wire write_fill_data_5 = bus_ifu_wr_en & _T_1291; // @[el2_ifu_mem_ctl.scala 391:73] - wire _T_1343 = ic_miss_buff_data_valid[5] & _T_1327; // @[el2_ifu_mem_ctl.scala 397:116] - wire ic_miss_buff_data_valid_in_5 = write_fill_data_5 | _T_1343; // @[el2_ifu_mem_ctl.scala 397:88] + wire _T_1416 = bypass_index[4:2] == 3'h5; // @[el2_ifu_mem_ctl.scala 409:114] + wire _T_1291 = io_ifu_axi_rid == 3'h5; // @[el2_ifu_mem_ctl.scala 392:91] + wire write_fill_data_5 = bus_ifu_wr_en & _T_1291; // @[el2_ifu_mem_ctl.scala 392:73] + wire _T_1343 = ic_miss_buff_data_valid[5] & _T_1327; // @[el2_ifu_mem_ctl.scala 398:116] + wire ic_miss_buff_data_valid_in_5 = write_fill_data_5 | _T_1343; // @[el2_ifu_mem_ctl.scala 398:88] wire _T_1429 = _T_1416 & ic_miss_buff_data_valid_in_5; // @[Mux.scala 27:72] wire _T_1436 = _T_1435 | _T_1429; // @[Mux.scala 27:72] - wire _T_1419 = bypass_index[4:2] == 3'h6; // @[el2_ifu_mem_ctl.scala 408:114] - wire _T_1292 = io_ifu_axi_rid == 3'h6; // @[el2_ifu_mem_ctl.scala 391:91] - wire write_fill_data_6 = bus_ifu_wr_en & _T_1292; // @[el2_ifu_mem_ctl.scala 391:73] - wire _T_1346 = ic_miss_buff_data_valid[6] & _T_1327; // @[el2_ifu_mem_ctl.scala 397:116] - wire ic_miss_buff_data_valid_in_6 = write_fill_data_6 | _T_1346; // @[el2_ifu_mem_ctl.scala 397:88] + wire _T_1419 = bypass_index[4:2] == 3'h6; // @[el2_ifu_mem_ctl.scala 409:114] + wire _T_1292 = io_ifu_axi_rid == 3'h6; // @[el2_ifu_mem_ctl.scala 392:91] + wire write_fill_data_6 = bus_ifu_wr_en & _T_1292; // @[el2_ifu_mem_ctl.scala 392:73] + wire _T_1346 = ic_miss_buff_data_valid[6] & _T_1327; // @[el2_ifu_mem_ctl.scala 398:116] + wire ic_miss_buff_data_valid_in_6 = write_fill_data_6 | _T_1346; // @[el2_ifu_mem_ctl.scala 398:88] wire _T_1430 = _T_1419 & ic_miss_buff_data_valid_in_6; // @[Mux.scala 27:72] wire _T_1437 = _T_1436 | _T_1430; // @[Mux.scala 27:72] - wire _T_1422 = bypass_index[4:2] == 3'h7; // @[el2_ifu_mem_ctl.scala 408:114] - wire _T_1293 = io_ifu_axi_rid == 3'h7; // @[el2_ifu_mem_ctl.scala 391:91] - wire write_fill_data_7 = bus_ifu_wr_en & _T_1293; // @[el2_ifu_mem_ctl.scala 391:73] - wire _T_1349 = ic_miss_buff_data_valid[7] & _T_1327; // @[el2_ifu_mem_ctl.scala 397:116] - wire ic_miss_buff_data_valid_in_7 = write_fill_data_7 | _T_1349; // @[el2_ifu_mem_ctl.scala 397:88] + wire _T_1422 = bypass_index[4:2] == 3'h7; // @[el2_ifu_mem_ctl.scala 409:114] + wire _T_1293 = io_ifu_axi_rid == 3'h7; // @[el2_ifu_mem_ctl.scala 392:91] + wire write_fill_data_7 = bus_ifu_wr_en & _T_1293; // @[el2_ifu_mem_ctl.scala 392:73] + wire _T_1349 = ic_miss_buff_data_valid[7] & _T_1327; // @[el2_ifu_mem_ctl.scala 398:116] + wire ic_miss_buff_data_valid_in_7 = write_fill_data_7 | _T_1349; // @[el2_ifu_mem_ctl.scala 398:88] wire _T_1431 = _T_1422 & ic_miss_buff_data_valid_in_7; // @[Mux.scala 27:72] wire bypass_valid_value_check = _T_1437 | _T_1431; // @[Mux.scala 27:72] - wire _T_1440 = ~bypass_index[1]; // @[el2_ifu_mem_ctl.scala 409:58] - wire _T_1441 = bypass_valid_value_check & _T_1440; // @[el2_ifu_mem_ctl.scala 409:56] - wire _T_1443 = ~bypass_index[0]; // @[el2_ifu_mem_ctl.scala 409:77] - wire _T_1444 = _T_1441 & _T_1443; // @[el2_ifu_mem_ctl.scala 409:75] - wire _T_1449 = _T_1441 & bypass_index[0]; // @[el2_ifu_mem_ctl.scala 410:75] - wire _T_1450 = _T_1444 | _T_1449; // @[el2_ifu_mem_ctl.scala 409:95] - wire _T_1452 = bypass_valid_value_check & bypass_index[1]; // @[el2_ifu_mem_ctl.scala 411:56] - wire _T_1455 = _T_1452 & _T_1443; // @[el2_ifu_mem_ctl.scala 411:74] - wire _T_1456 = _T_1450 | _T_1455; // @[el2_ifu_mem_ctl.scala 410:94] - wire _T_1460 = _T_1452 & bypass_index[0]; // @[el2_ifu_mem_ctl.scala 412:51] - wire [2:0] bypass_index_5_3_inc = bypass_index[4:2] + 3'h1; // @[el2_ifu_mem_ctl.scala 407:70] - wire _T_1461 = bypass_index_5_3_inc == 3'h0; // @[el2_ifu_mem_ctl.scala 412:132] + wire _T_1440 = ~bypass_index[1]; // @[el2_ifu_mem_ctl.scala 410:58] + wire _T_1441 = bypass_valid_value_check & _T_1440; // @[el2_ifu_mem_ctl.scala 410:56] + wire _T_1443 = ~bypass_index[0]; // @[el2_ifu_mem_ctl.scala 410:77] + wire _T_1444 = _T_1441 & _T_1443; // @[el2_ifu_mem_ctl.scala 410:75] + wire _T_1449 = _T_1441 & bypass_index[0]; // @[el2_ifu_mem_ctl.scala 411:75] + wire _T_1450 = _T_1444 | _T_1449; // @[el2_ifu_mem_ctl.scala 410:95] + wire _T_1452 = bypass_valid_value_check & bypass_index[1]; // @[el2_ifu_mem_ctl.scala 412:56] + wire _T_1455 = _T_1452 & _T_1443; // @[el2_ifu_mem_ctl.scala 412:74] + wire _T_1456 = _T_1450 | _T_1455; // @[el2_ifu_mem_ctl.scala 411:94] + wire _T_1460 = _T_1452 & bypass_index[0]; // @[el2_ifu_mem_ctl.scala 413:51] + wire [2:0] bypass_index_5_3_inc = bypass_index[4:2] + 3'h1; // @[el2_ifu_mem_ctl.scala 408:70] + wire _T_1461 = bypass_index_5_3_inc == 3'h0; // @[el2_ifu_mem_ctl.scala 413:132] wire _T_1477 = _T_1461 & ic_miss_buff_data_valid_in_0; // @[Mux.scala 27:72] - wire _T_1463 = bypass_index_5_3_inc == 3'h1; // @[el2_ifu_mem_ctl.scala 412:132] + wire _T_1463 = bypass_index_5_3_inc == 3'h1; // @[el2_ifu_mem_ctl.scala 413:132] wire _T_1478 = _T_1463 & ic_miss_buff_data_valid_in_1; // @[Mux.scala 27:72] wire _T_1485 = _T_1477 | _T_1478; // @[Mux.scala 27:72] - wire _T_1465 = bypass_index_5_3_inc == 3'h2; // @[el2_ifu_mem_ctl.scala 412:132] + wire _T_1465 = bypass_index_5_3_inc == 3'h2; // @[el2_ifu_mem_ctl.scala 413:132] wire _T_1479 = _T_1465 & ic_miss_buff_data_valid_in_2; // @[Mux.scala 27:72] wire _T_1486 = _T_1485 | _T_1479; // @[Mux.scala 27:72] - wire _T_1467 = bypass_index_5_3_inc == 3'h3; // @[el2_ifu_mem_ctl.scala 412:132] + wire _T_1467 = bypass_index_5_3_inc == 3'h3; // @[el2_ifu_mem_ctl.scala 413:132] wire _T_1480 = _T_1467 & ic_miss_buff_data_valid_in_3; // @[Mux.scala 27:72] wire _T_1487 = _T_1486 | _T_1480; // @[Mux.scala 27:72] - wire _T_1469 = bypass_index_5_3_inc == 3'h4; // @[el2_ifu_mem_ctl.scala 412:132] + wire _T_1469 = bypass_index_5_3_inc == 3'h4; // @[el2_ifu_mem_ctl.scala 413:132] wire _T_1481 = _T_1469 & ic_miss_buff_data_valid_in_4; // @[Mux.scala 27:72] wire _T_1488 = _T_1487 | _T_1481; // @[Mux.scala 27:72] - wire _T_1471 = bypass_index_5_3_inc == 3'h5; // @[el2_ifu_mem_ctl.scala 412:132] + wire _T_1471 = bypass_index_5_3_inc == 3'h5; // @[el2_ifu_mem_ctl.scala 413:132] wire _T_1482 = _T_1471 & ic_miss_buff_data_valid_in_5; // @[Mux.scala 27:72] wire _T_1489 = _T_1488 | _T_1482; // @[Mux.scala 27:72] - wire _T_1473 = bypass_index_5_3_inc == 3'h6; // @[el2_ifu_mem_ctl.scala 412:132] + wire _T_1473 = bypass_index_5_3_inc == 3'h6; // @[el2_ifu_mem_ctl.scala 413:132] wire _T_1483 = _T_1473 & ic_miss_buff_data_valid_in_6; // @[Mux.scala 27:72] wire _T_1490 = _T_1489 | _T_1483; // @[Mux.scala 27:72] - wire _T_1475 = bypass_index_5_3_inc == 3'h7; // @[el2_ifu_mem_ctl.scala 412:132] + wire _T_1475 = bypass_index_5_3_inc == 3'h7; // @[el2_ifu_mem_ctl.scala 413:132] wire _T_1484 = _T_1475 & ic_miss_buff_data_valid_in_7; // @[Mux.scala 27:72] wire _T_1491 = _T_1490 | _T_1484; // @[Mux.scala 27:72] - wire _T_1493 = _T_1460 & _T_1491; // @[el2_ifu_mem_ctl.scala 412:69] - wire _T_1494 = _T_1456 | _T_1493; // @[el2_ifu_mem_ctl.scala 411:94] - wire [4:0] _GEN_664 = {{2'd0}, bypass_index[4:2]}; // @[el2_ifu_mem_ctl.scala 413:95] - wire _T_1497 = _GEN_664 == 5'h1f; // @[el2_ifu_mem_ctl.scala 413:95] - wire _T_1498 = bypass_valid_value_check & _T_1497; // @[el2_ifu_mem_ctl.scala 413:56] - wire bypass_data_ready_in = _T_1494 | _T_1498; // @[el2_ifu_mem_ctl.scala 412:181] - wire _T_1499 = bypass_data_ready_in & crit_wd_byp_ok_ff; // @[el2_ifu_mem_ctl.scala 417:53] - wire _T_1500 = _T_1499 & uncacheable_miss_ff; // @[el2_ifu_mem_ctl.scala 417:73] - wire _T_1502 = _T_1500 & _T_317; // @[el2_ifu_mem_ctl.scala 417:96] - wire _T_1504 = _T_1502 & _T_58; // @[el2_ifu_mem_ctl.scala 417:118] - wire _T_1506 = crit_wd_byp_ok_ff & _T_17; // @[el2_ifu_mem_ctl.scala 418:73] - wire _T_1508 = _T_1506 & _T_317; // @[el2_ifu_mem_ctl.scala 418:96] - wire _T_1510 = _T_1508 & _T_58; // @[el2_ifu_mem_ctl.scala 418:118] - wire _T_1511 = _T_1504 | _T_1510; // @[el2_ifu_mem_ctl.scala 417:143] - reg ic_crit_wd_rdy_new_ff; // @[el2_ifu_mem_ctl.scala 420:58] - wire _T_1512 = ic_crit_wd_rdy_new_ff & crit_wd_byp_ok_ff; // @[el2_ifu_mem_ctl.scala 419:54] - wire _T_1513 = ~fetch_req_icache_f; // @[el2_ifu_mem_ctl.scala 419:76] - wire _T_1514 = _T_1512 & _T_1513; // @[el2_ifu_mem_ctl.scala 419:74] - wire _T_1516 = _T_1514 & _T_317; // @[el2_ifu_mem_ctl.scala 419:96] - wire ic_crit_wd_rdy_new_in = _T_1511 | _T_1516; // @[el2_ifu_mem_ctl.scala 418:143] - wire ic_crit_wd_rdy = ic_crit_wd_rdy_new_in | ic_crit_wd_rdy_new_ff; // @[el2_ifu_mem_ctl.scala 617:43] - wire _T_1253 = ic_crit_wd_rdy | _T_2221; // @[el2_ifu_mem_ctl.scala 364:38] - wire _T_1255 = _T_1253 | _T_2237; // @[el2_ifu_mem_ctl.scala 364:64] - wire _T_1256 = ~_T_1255; // @[el2_ifu_mem_ctl.scala 364:21] - wire _T_1257 = ~fetch_req_iccm_f; // @[el2_ifu_mem_ctl.scala 364:98] - wire sel_ic_data = _T_1256 & _T_1257; // @[el2_ifu_mem_ctl.scala 364:96] - wire _T_2404 = io_ic_tag_perr & sel_ic_data; // @[el2_ifu_mem_ctl.scala 462:44] - wire _T_1610 = ifu_fetch_addr_int_f[1] & ifu_fetch_addr_int_f[0]; // @[el2_ifu_mem_ctl.scala 431:31] - reg [7:0] ic_miss_buff_data_error; // @[el2_ifu_mem_ctl.scala 403:60] + wire _T_1493 = _T_1460 & _T_1491; // @[el2_ifu_mem_ctl.scala 413:69] + wire _T_1494 = _T_1456 | _T_1493; // @[el2_ifu_mem_ctl.scala 412:94] + wire [4:0] _GEN_664 = {{2'd0}, bypass_index[4:2]}; // @[el2_ifu_mem_ctl.scala 414:95] + wire _T_1497 = _GEN_664 == 5'h1f; // @[el2_ifu_mem_ctl.scala 414:95] + wire _T_1498 = bypass_valid_value_check & _T_1497; // @[el2_ifu_mem_ctl.scala 414:56] + wire bypass_data_ready_in = _T_1494 | _T_1498; // @[el2_ifu_mem_ctl.scala 413:181] + wire _T_1499 = bypass_data_ready_in & crit_wd_byp_ok_ff; // @[el2_ifu_mem_ctl.scala 418:53] + wire _T_1500 = _T_1499 & uncacheable_miss_ff; // @[el2_ifu_mem_ctl.scala 418:73] + wire _T_1502 = _T_1500 & _T_317; // @[el2_ifu_mem_ctl.scala 418:96] + wire _T_1504 = _T_1502 & _T_58; // @[el2_ifu_mem_ctl.scala 418:118] + wire _T_1506 = crit_wd_byp_ok_ff & _T_17; // @[el2_ifu_mem_ctl.scala 419:73] + wire _T_1508 = _T_1506 & _T_317; // @[el2_ifu_mem_ctl.scala 419:96] + wire _T_1510 = _T_1508 & _T_58; // @[el2_ifu_mem_ctl.scala 419:118] + wire _T_1511 = _T_1504 | _T_1510; // @[el2_ifu_mem_ctl.scala 418:143] + reg ic_crit_wd_rdy_new_ff; // @[el2_ifu_mem_ctl.scala 421:58] + wire _T_1512 = ic_crit_wd_rdy_new_ff & crit_wd_byp_ok_ff; // @[el2_ifu_mem_ctl.scala 420:54] + wire _T_1513 = ~fetch_req_icache_f; // @[el2_ifu_mem_ctl.scala 420:76] + wire _T_1514 = _T_1512 & _T_1513; // @[el2_ifu_mem_ctl.scala 420:74] + wire _T_1516 = _T_1514 & _T_317; // @[el2_ifu_mem_ctl.scala 420:96] + wire ic_crit_wd_rdy_new_in = _T_1511 | _T_1516; // @[el2_ifu_mem_ctl.scala 419:143] + wire ic_crit_wd_rdy = ic_crit_wd_rdy_new_in | ic_crit_wd_rdy_new_ff; // @[el2_ifu_mem_ctl.scala 618:43] + wire _T_1253 = ic_crit_wd_rdy | _T_2221; // @[el2_ifu_mem_ctl.scala 365:38] + wire _T_1255 = _T_1253 | _T_2237; // @[el2_ifu_mem_ctl.scala 365:64] + wire _T_1256 = ~_T_1255; // @[el2_ifu_mem_ctl.scala 365:21] + wire _T_1257 = ~fetch_req_iccm_f; // @[el2_ifu_mem_ctl.scala 365:98] + wire sel_ic_data = _T_1256 & _T_1257; // @[el2_ifu_mem_ctl.scala 365:96] + wire _T_2404 = io_ic_tag_perr & sel_ic_data; // @[el2_ifu_mem_ctl.scala 463:44] + wire _T_1610 = ifu_fetch_addr_int_f[1] & ifu_fetch_addr_int_f[0]; // @[el2_ifu_mem_ctl.scala 432:31] + reg [7:0] ic_miss_buff_data_error; // @[el2_ifu_mem_ctl.scala 404:60] wire _T_1554 = _T_1401 & ic_miss_buff_data_error[0]; // @[Mux.scala 27:72] wire _T_1555 = _T_1404 & ic_miss_buff_data_error[1]; // @[Mux.scala 27:72] wire _T_1562 = _T_1554 | _T_1555; // @[Mux.scala 27:72] @@ -2200,986 +2200,986 @@ module el2_ifu_mem_ctl( wire _T_1606 = _T_1605 | _T_1599; // @[Mux.scala 27:72] wire _T_1600 = _T_2175 & ic_miss_buff_data_error[7]; // @[Mux.scala 27:72] wire ic_miss_buff_data_error_bypass_inc = _T_1606 | _T_1600; // @[Mux.scala 27:72] - wire _T_1611 = ic_miss_buff_data_error_bypass | ic_miss_buff_data_error_bypass_inc; // @[el2_ifu_mem_ctl.scala 433:70] - wire ifu_byp_data_err_new = _T_1610 ? ic_miss_buff_data_error_bypass : _T_1611; // @[el2_ifu_mem_ctl.scala 431:56] - wire ifc_bus_acc_fault_f = ic_byp_hit_f & ifu_byp_data_err_new; // @[el2_ifu_mem_ctl.scala 375:42] - wire _T_2405 = ifc_region_acc_fault_final_f | ifc_bus_acc_fault_f; // @[el2_ifu_mem_ctl.scala 462:91] - wire _T_2406 = ~_T_2405; // @[el2_ifu_mem_ctl.scala 462:60] - wire ic_rd_parity_final_err = _T_2404 & _T_2406; // @[el2_ifu_mem_ctl.scala 462:58] + wire _T_1611 = ic_miss_buff_data_error_bypass | ic_miss_buff_data_error_bypass_inc; // @[el2_ifu_mem_ctl.scala 434:70] + wire ifu_byp_data_err_new = _T_1610 ? ic_miss_buff_data_error_bypass : _T_1611; // @[el2_ifu_mem_ctl.scala 432:56] + wire ifc_bus_acc_fault_f = ic_byp_hit_f & ifu_byp_data_err_new; // @[el2_ifu_mem_ctl.scala 376:42] + wire _T_2405 = ifc_region_acc_fault_final_f | ifc_bus_acc_fault_f; // @[el2_ifu_mem_ctl.scala 463:91] + wire _T_2406 = ~_T_2405; // @[el2_ifu_mem_ctl.scala 463:60] + wire ic_rd_parity_final_err = _T_2404 & _T_2406; // @[el2_ifu_mem_ctl.scala 463:58] reg ic_debug_ict_array_sel_ff; // @[Reg.scala 27:20] reg ic_tag_valid_out_1_0; // @[Reg.scala 27:20] - wire _T_9677 = _T_4471 ? 1'h0 : ic_tag_valid_out_1_0; // @[el2_ifu_mem_ctl.scala 744:10] + wire _T_9677 = _T_4471 ? 1'h0 : ic_tag_valid_out_1_0; // @[el2_ifu_mem_ctl.scala 745:10] reg ic_tag_valid_out_1_1; // @[Reg.scala 27:20] - wire _T_9679 = _T_4475 ? 1'h0 : ic_tag_valid_out_1_1; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9932 = _T_9677 | _T_9679; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9679 = _T_4475 ? 1'h0 : ic_tag_valid_out_1_1; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9932 = _T_9677 | _T_9679; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_2; // @[Reg.scala 27:20] - wire _T_9681 = _T_4479 ? 1'h0 : ic_tag_valid_out_1_2; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9933 = _T_9932 | _T_9681; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9681 = _T_4479 ? 1'h0 : ic_tag_valid_out_1_2; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9933 = _T_9932 | _T_9681; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_3; // @[Reg.scala 27:20] - wire _T_9683 = _T_4483 ? 1'h0 : ic_tag_valid_out_1_3; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9934 = _T_9933 | _T_9683; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9683 = _T_4483 ? 1'h0 : ic_tag_valid_out_1_3; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9934 = _T_9933 | _T_9683; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_4; // @[Reg.scala 27:20] - wire _T_9685 = _T_4487 ? 1'h0 : ic_tag_valid_out_1_4; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9935 = _T_9934 | _T_9685; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9685 = _T_4487 ? 1'h0 : ic_tag_valid_out_1_4; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9935 = _T_9934 | _T_9685; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_5; // @[Reg.scala 27:20] - wire _T_9687 = _T_4491 ? 1'h0 : ic_tag_valid_out_1_5; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9936 = _T_9935 | _T_9687; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9687 = _T_4491 ? 1'h0 : ic_tag_valid_out_1_5; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9936 = _T_9935 | _T_9687; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_6; // @[Reg.scala 27:20] - wire _T_9689 = _T_4495 ? 1'h0 : ic_tag_valid_out_1_6; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9937 = _T_9936 | _T_9689; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9689 = _T_4495 ? 1'h0 : ic_tag_valid_out_1_6; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9937 = _T_9936 | _T_9689; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_7; // @[Reg.scala 27:20] - wire _T_9691 = _T_4499 ? 1'h0 : ic_tag_valid_out_1_7; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9938 = _T_9937 | _T_9691; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9691 = _T_4499 ? 1'h0 : ic_tag_valid_out_1_7; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9938 = _T_9937 | _T_9691; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_8; // @[Reg.scala 27:20] - wire _T_9693 = _T_4503 ? 1'h0 : ic_tag_valid_out_1_8; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9939 = _T_9938 | _T_9693; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9693 = _T_4503 ? 1'h0 : ic_tag_valid_out_1_8; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9939 = _T_9938 | _T_9693; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_9; // @[Reg.scala 27:20] - wire _T_9695 = _T_4507 ? 1'h0 : ic_tag_valid_out_1_9; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9940 = _T_9939 | _T_9695; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9695 = _T_4507 ? 1'h0 : ic_tag_valid_out_1_9; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9940 = _T_9939 | _T_9695; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_10; // @[Reg.scala 27:20] - wire _T_9697 = _T_4511 ? 1'h0 : ic_tag_valid_out_1_10; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9941 = _T_9940 | _T_9697; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9697 = _T_4511 ? 1'h0 : ic_tag_valid_out_1_10; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9941 = _T_9940 | _T_9697; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_11; // @[Reg.scala 27:20] - wire _T_9699 = _T_4515 ? 1'h0 : ic_tag_valid_out_1_11; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9942 = _T_9941 | _T_9699; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9699 = _T_4515 ? 1'h0 : ic_tag_valid_out_1_11; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9942 = _T_9941 | _T_9699; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_12; // @[Reg.scala 27:20] - wire _T_9701 = _T_4519 ? 1'h0 : ic_tag_valid_out_1_12; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9943 = _T_9942 | _T_9701; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9701 = _T_4519 ? 1'h0 : ic_tag_valid_out_1_12; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9943 = _T_9942 | _T_9701; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_13; // @[Reg.scala 27:20] - wire _T_9703 = _T_4523 ? 1'h0 : ic_tag_valid_out_1_13; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9944 = _T_9943 | _T_9703; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9703 = _T_4523 ? 1'h0 : ic_tag_valid_out_1_13; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9944 = _T_9943 | _T_9703; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_14; // @[Reg.scala 27:20] - wire _T_9705 = _T_4527 ? 1'h0 : ic_tag_valid_out_1_14; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9945 = _T_9944 | _T_9705; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9705 = _T_4527 ? 1'h0 : ic_tag_valid_out_1_14; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9945 = _T_9944 | _T_9705; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_15; // @[Reg.scala 27:20] - wire _T_9707 = _T_4531 ? 1'h0 : ic_tag_valid_out_1_15; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9946 = _T_9945 | _T_9707; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9707 = _T_4531 ? 1'h0 : ic_tag_valid_out_1_15; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9946 = _T_9945 | _T_9707; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_16; // @[Reg.scala 27:20] - wire _T_9709 = _T_4535 ? 1'h0 : ic_tag_valid_out_1_16; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9947 = _T_9946 | _T_9709; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9709 = _T_4535 ? 1'h0 : ic_tag_valid_out_1_16; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9947 = _T_9946 | _T_9709; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_17; // @[Reg.scala 27:20] - wire _T_9711 = _T_4539 ? 1'h0 : ic_tag_valid_out_1_17; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9948 = _T_9947 | _T_9711; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9711 = _T_4539 ? 1'h0 : ic_tag_valid_out_1_17; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9948 = _T_9947 | _T_9711; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_18; // @[Reg.scala 27:20] - wire _T_9713 = _T_4543 ? 1'h0 : ic_tag_valid_out_1_18; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9949 = _T_9948 | _T_9713; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9713 = _T_4543 ? 1'h0 : ic_tag_valid_out_1_18; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9949 = _T_9948 | _T_9713; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_19; // @[Reg.scala 27:20] - wire _T_9715 = _T_4547 ? 1'h0 : ic_tag_valid_out_1_19; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9950 = _T_9949 | _T_9715; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9715 = _T_4547 ? 1'h0 : ic_tag_valid_out_1_19; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9950 = _T_9949 | _T_9715; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_20; // @[Reg.scala 27:20] - wire _T_9717 = _T_4551 ? 1'h0 : ic_tag_valid_out_1_20; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9951 = _T_9950 | _T_9717; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9717 = _T_4551 ? 1'h0 : ic_tag_valid_out_1_20; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9951 = _T_9950 | _T_9717; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_21; // @[Reg.scala 27:20] - wire _T_9719 = _T_4555 ? 1'h0 : ic_tag_valid_out_1_21; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9952 = _T_9951 | _T_9719; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9719 = _T_4555 ? 1'h0 : ic_tag_valid_out_1_21; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9952 = _T_9951 | _T_9719; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_22; // @[Reg.scala 27:20] - wire _T_9721 = _T_4559 ? 1'h0 : ic_tag_valid_out_1_22; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9953 = _T_9952 | _T_9721; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9721 = _T_4559 ? 1'h0 : ic_tag_valid_out_1_22; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9953 = _T_9952 | _T_9721; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_23; // @[Reg.scala 27:20] - wire _T_9723 = _T_4563 ? 1'h0 : ic_tag_valid_out_1_23; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9954 = _T_9953 | _T_9723; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9723 = _T_4563 ? 1'h0 : ic_tag_valid_out_1_23; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9954 = _T_9953 | _T_9723; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_24; // @[Reg.scala 27:20] - wire _T_9725 = _T_4567 ? 1'h0 : ic_tag_valid_out_1_24; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9955 = _T_9954 | _T_9725; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9725 = _T_4567 ? 1'h0 : ic_tag_valid_out_1_24; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9955 = _T_9954 | _T_9725; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_25; // @[Reg.scala 27:20] - wire _T_9727 = _T_4571 ? 1'h0 : ic_tag_valid_out_1_25; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9956 = _T_9955 | _T_9727; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9727 = _T_4571 ? 1'h0 : ic_tag_valid_out_1_25; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9956 = _T_9955 | _T_9727; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_26; // @[Reg.scala 27:20] - wire _T_9729 = _T_4575 ? 1'h0 : ic_tag_valid_out_1_26; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9957 = _T_9956 | _T_9729; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9729 = _T_4575 ? 1'h0 : ic_tag_valid_out_1_26; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9957 = _T_9956 | _T_9729; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_27; // @[Reg.scala 27:20] - wire _T_9731 = _T_4579 ? 1'h0 : ic_tag_valid_out_1_27; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9958 = _T_9957 | _T_9731; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9731 = _T_4579 ? 1'h0 : ic_tag_valid_out_1_27; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9958 = _T_9957 | _T_9731; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_28; // @[Reg.scala 27:20] - wire _T_9733 = _T_4583 ? 1'h0 : ic_tag_valid_out_1_28; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9959 = _T_9958 | _T_9733; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9733 = _T_4583 ? 1'h0 : ic_tag_valid_out_1_28; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9959 = _T_9958 | _T_9733; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_29; // @[Reg.scala 27:20] - wire _T_9735 = _T_4587 ? 1'h0 : ic_tag_valid_out_1_29; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9960 = _T_9959 | _T_9735; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9735 = _T_4587 ? 1'h0 : ic_tag_valid_out_1_29; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9960 = _T_9959 | _T_9735; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_30; // @[Reg.scala 27:20] - wire _T_9737 = _T_4591 ? 1'h0 : ic_tag_valid_out_1_30; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9961 = _T_9960 | _T_9737; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9737 = _T_4591 ? 1'h0 : ic_tag_valid_out_1_30; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9961 = _T_9960 | _T_9737; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_31; // @[Reg.scala 27:20] - wire _T_9739 = _T_4595 ? 1'h0 : ic_tag_valid_out_1_31; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9962 = _T_9961 | _T_9739; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9739 = _T_4595 ? 1'h0 : ic_tag_valid_out_1_31; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9962 = _T_9961 | _T_9739; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_32; // @[Reg.scala 27:20] - wire _T_9741 = _T_4599 ? 1'h0 : ic_tag_valid_out_1_32; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9963 = _T_9962 | _T_9741; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9741 = _T_4599 ? 1'h0 : ic_tag_valid_out_1_32; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9963 = _T_9962 | _T_9741; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_33; // @[Reg.scala 27:20] - wire _T_9743 = _T_4603 ? 1'h0 : ic_tag_valid_out_1_33; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9964 = _T_9963 | _T_9743; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9743 = _T_4603 ? 1'h0 : ic_tag_valid_out_1_33; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9964 = _T_9963 | _T_9743; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_34; // @[Reg.scala 27:20] - wire _T_9745 = _T_4607 ? 1'h0 : ic_tag_valid_out_1_34; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9965 = _T_9964 | _T_9745; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9745 = _T_4607 ? 1'h0 : ic_tag_valid_out_1_34; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9965 = _T_9964 | _T_9745; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_35; // @[Reg.scala 27:20] - wire _T_9747 = _T_4611 ? 1'h0 : ic_tag_valid_out_1_35; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9966 = _T_9965 | _T_9747; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9747 = _T_4611 ? 1'h0 : ic_tag_valid_out_1_35; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9966 = _T_9965 | _T_9747; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_36; // @[Reg.scala 27:20] - wire _T_9749 = _T_4615 ? 1'h0 : ic_tag_valid_out_1_36; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9967 = _T_9966 | _T_9749; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9749 = _T_4615 ? 1'h0 : ic_tag_valid_out_1_36; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9967 = _T_9966 | _T_9749; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_37; // @[Reg.scala 27:20] - wire _T_9751 = _T_4619 ? 1'h0 : ic_tag_valid_out_1_37; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9968 = _T_9967 | _T_9751; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9751 = _T_4619 ? 1'h0 : ic_tag_valid_out_1_37; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9968 = _T_9967 | _T_9751; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_38; // @[Reg.scala 27:20] - wire _T_9753 = _T_4623 ? 1'h0 : ic_tag_valid_out_1_38; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9969 = _T_9968 | _T_9753; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9753 = _T_4623 ? 1'h0 : ic_tag_valid_out_1_38; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9969 = _T_9968 | _T_9753; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_39; // @[Reg.scala 27:20] - wire _T_9755 = _T_4627 ? 1'h0 : ic_tag_valid_out_1_39; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9970 = _T_9969 | _T_9755; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9755 = _T_4627 ? 1'h0 : ic_tag_valid_out_1_39; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9970 = _T_9969 | _T_9755; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_40; // @[Reg.scala 27:20] - wire _T_9757 = _T_4631 ? 1'h0 : ic_tag_valid_out_1_40; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9971 = _T_9970 | _T_9757; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9757 = _T_4631 ? 1'h0 : ic_tag_valid_out_1_40; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9971 = _T_9970 | _T_9757; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_41; // @[Reg.scala 27:20] - wire _T_9759 = _T_4635 ? 1'h0 : ic_tag_valid_out_1_41; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9972 = _T_9971 | _T_9759; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9759 = _T_4635 ? 1'h0 : ic_tag_valid_out_1_41; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9972 = _T_9971 | _T_9759; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_42; // @[Reg.scala 27:20] - wire _T_9761 = _T_4639 ? 1'h0 : ic_tag_valid_out_1_42; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9973 = _T_9972 | _T_9761; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9761 = _T_4639 ? 1'h0 : ic_tag_valid_out_1_42; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9973 = _T_9972 | _T_9761; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_43; // @[Reg.scala 27:20] - wire _T_9763 = _T_4643 ? 1'h0 : ic_tag_valid_out_1_43; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9974 = _T_9973 | _T_9763; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9763 = _T_4643 ? 1'h0 : ic_tag_valid_out_1_43; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9974 = _T_9973 | _T_9763; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_44; // @[Reg.scala 27:20] - wire _T_9765 = _T_4647 ? 1'h0 : ic_tag_valid_out_1_44; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9975 = _T_9974 | _T_9765; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9765 = _T_4647 ? 1'h0 : ic_tag_valid_out_1_44; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9975 = _T_9974 | _T_9765; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_45; // @[Reg.scala 27:20] - wire _T_9767 = _T_4651 ? 1'h0 : ic_tag_valid_out_1_45; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9976 = _T_9975 | _T_9767; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9767 = _T_4651 ? 1'h0 : ic_tag_valid_out_1_45; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9976 = _T_9975 | _T_9767; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_46; // @[Reg.scala 27:20] - wire _T_9769 = _T_4655 ? 1'h0 : ic_tag_valid_out_1_46; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9977 = _T_9976 | _T_9769; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9769 = _T_4655 ? 1'h0 : ic_tag_valid_out_1_46; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9977 = _T_9976 | _T_9769; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_47; // @[Reg.scala 27:20] - wire _T_9771 = _T_4659 ? 1'h0 : ic_tag_valid_out_1_47; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9978 = _T_9977 | _T_9771; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9771 = _T_4659 ? 1'h0 : ic_tag_valid_out_1_47; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9978 = _T_9977 | _T_9771; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_48; // @[Reg.scala 27:20] - wire _T_9773 = _T_4663 ? 1'h0 : ic_tag_valid_out_1_48; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9979 = _T_9978 | _T_9773; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9773 = _T_4663 ? 1'h0 : ic_tag_valid_out_1_48; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9979 = _T_9978 | _T_9773; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_49; // @[Reg.scala 27:20] - wire _T_9775 = _T_4667 ? 1'h0 : ic_tag_valid_out_1_49; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9980 = _T_9979 | _T_9775; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9775 = _T_4667 ? 1'h0 : ic_tag_valid_out_1_49; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9980 = _T_9979 | _T_9775; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_50; // @[Reg.scala 27:20] - wire _T_9777 = _T_4671 ? 1'h0 : ic_tag_valid_out_1_50; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9981 = _T_9980 | _T_9777; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9777 = _T_4671 ? 1'h0 : ic_tag_valid_out_1_50; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9981 = _T_9980 | _T_9777; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_51; // @[Reg.scala 27:20] - wire _T_9779 = _T_4675 ? 1'h0 : ic_tag_valid_out_1_51; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9982 = _T_9981 | _T_9779; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9779 = _T_4675 ? 1'h0 : ic_tag_valid_out_1_51; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9982 = _T_9981 | _T_9779; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_52; // @[Reg.scala 27:20] - wire _T_9781 = _T_4679 ? 1'h0 : ic_tag_valid_out_1_52; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9983 = _T_9982 | _T_9781; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9781 = _T_4679 ? 1'h0 : ic_tag_valid_out_1_52; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9983 = _T_9982 | _T_9781; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_53; // @[Reg.scala 27:20] - wire _T_9783 = _T_4683 ? 1'h0 : ic_tag_valid_out_1_53; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9984 = _T_9983 | _T_9783; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9783 = _T_4683 ? 1'h0 : ic_tag_valid_out_1_53; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9984 = _T_9983 | _T_9783; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_54; // @[Reg.scala 27:20] - wire _T_9785 = _T_4687 ? 1'h0 : ic_tag_valid_out_1_54; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9985 = _T_9984 | _T_9785; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9785 = _T_4687 ? 1'h0 : ic_tag_valid_out_1_54; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9985 = _T_9984 | _T_9785; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_55; // @[Reg.scala 27:20] - wire _T_9787 = _T_4691 ? 1'h0 : ic_tag_valid_out_1_55; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9986 = _T_9985 | _T_9787; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9787 = _T_4691 ? 1'h0 : ic_tag_valid_out_1_55; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9986 = _T_9985 | _T_9787; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_56; // @[Reg.scala 27:20] - wire _T_9789 = _T_4695 ? 1'h0 : ic_tag_valid_out_1_56; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9987 = _T_9986 | _T_9789; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9789 = _T_4695 ? 1'h0 : ic_tag_valid_out_1_56; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9987 = _T_9986 | _T_9789; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_57; // @[Reg.scala 27:20] - wire _T_9791 = _T_4699 ? 1'h0 : ic_tag_valid_out_1_57; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9988 = _T_9987 | _T_9791; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9791 = _T_4699 ? 1'h0 : ic_tag_valid_out_1_57; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9988 = _T_9987 | _T_9791; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_58; // @[Reg.scala 27:20] - wire _T_9793 = _T_4703 ? 1'h0 : ic_tag_valid_out_1_58; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9989 = _T_9988 | _T_9793; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9793 = _T_4703 ? 1'h0 : ic_tag_valid_out_1_58; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9989 = _T_9988 | _T_9793; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_59; // @[Reg.scala 27:20] - wire _T_9795 = _T_4707 ? 1'h0 : ic_tag_valid_out_1_59; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9990 = _T_9989 | _T_9795; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9795 = _T_4707 ? 1'h0 : ic_tag_valid_out_1_59; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9990 = _T_9989 | _T_9795; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_60; // @[Reg.scala 27:20] - wire _T_9797 = _T_4711 ? 1'h0 : ic_tag_valid_out_1_60; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9991 = _T_9990 | _T_9797; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9797 = _T_4711 ? 1'h0 : ic_tag_valid_out_1_60; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9991 = _T_9990 | _T_9797; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_61; // @[Reg.scala 27:20] - wire _T_9799 = _T_4715 ? 1'h0 : ic_tag_valid_out_1_61; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9992 = _T_9991 | _T_9799; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9799 = _T_4715 ? 1'h0 : ic_tag_valid_out_1_61; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9992 = _T_9991 | _T_9799; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_62; // @[Reg.scala 27:20] - wire _T_9801 = _T_4719 ? 1'h0 : ic_tag_valid_out_1_62; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9993 = _T_9992 | _T_9801; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9801 = _T_4719 ? 1'h0 : ic_tag_valid_out_1_62; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9993 = _T_9992 | _T_9801; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_63; // @[Reg.scala 27:20] - wire _T_9803 = _T_4723 ? 1'h0 : ic_tag_valid_out_1_63; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9994 = _T_9993 | _T_9803; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9803 = _T_4723 ? 1'h0 : ic_tag_valid_out_1_63; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9994 = _T_9993 | _T_9803; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_64; // @[Reg.scala 27:20] - wire _T_9805 = _T_4727 ? 1'h0 : ic_tag_valid_out_1_64; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9995 = _T_9994 | _T_9805; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9805 = _T_4727 ? 1'h0 : ic_tag_valid_out_1_64; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9995 = _T_9994 | _T_9805; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_65; // @[Reg.scala 27:20] - wire _T_9807 = _T_4731 ? 1'h0 : ic_tag_valid_out_1_65; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9996 = _T_9995 | _T_9807; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9807 = _T_4731 ? 1'h0 : ic_tag_valid_out_1_65; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9996 = _T_9995 | _T_9807; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_66; // @[Reg.scala 27:20] - wire _T_9809 = _T_4735 ? 1'h0 : ic_tag_valid_out_1_66; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9997 = _T_9996 | _T_9809; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9809 = _T_4735 ? 1'h0 : ic_tag_valid_out_1_66; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9997 = _T_9996 | _T_9809; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_67; // @[Reg.scala 27:20] - wire _T_9811 = _T_4739 ? 1'h0 : ic_tag_valid_out_1_67; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9998 = _T_9997 | _T_9811; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9811 = _T_4739 ? 1'h0 : ic_tag_valid_out_1_67; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9998 = _T_9997 | _T_9811; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_68; // @[Reg.scala 27:20] - wire _T_9813 = _T_4743 ? 1'h0 : ic_tag_valid_out_1_68; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9999 = _T_9998 | _T_9813; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9813 = _T_4743 ? 1'h0 : ic_tag_valid_out_1_68; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9999 = _T_9998 | _T_9813; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_69; // @[Reg.scala 27:20] - wire _T_9815 = _T_4747 ? 1'h0 : ic_tag_valid_out_1_69; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_10000 = _T_9999 | _T_9815; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9815 = _T_4747 ? 1'h0 : ic_tag_valid_out_1_69; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_10000 = _T_9999 | _T_9815; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_70; // @[Reg.scala 27:20] - wire _T_9817 = _T_4751 ? 1'h0 : ic_tag_valid_out_1_70; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_10001 = _T_10000 | _T_9817; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9817 = _T_4751 ? 1'h0 : ic_tag_valid_out_1_70; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_10001 = _T_10000 | _T_9817; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_71; // @[Reg.scala 27:20] - wire _T_9819 = _T_4755 ? 1'h0 : ic_tag_valid_out_1_71; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_10002 = _T_10001 | _T_9819; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9819 = _T_4755 ? 1'h0 : ic_tag_valid_out_1_71; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_10002 = _T_10001 | _T_9819; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_72; // @[Reg.scala 27:20] - wire _T_9821 = _T_4759 ? 1'h0 : ic_tag_valid_out_1_72; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_10003 = _T_10002 | _T_9821; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9821 = _T_4759 ? 1'h0 : ic_tag_valid_out_1_72; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_10003 = _T_10002 | _T_9821; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_73; // @[Reg.scala 27:20] - wire _T_9823 = _T_4763 ? 1'h0 : ic_tag_valid_out_1_73; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_10004 = _T_10003 | _T_9823; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9823 = _T_4763 ? 1'h0 : ic_tag_valid_out_1_73; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_10004 = _T_10003 | _T_9823; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_74; // @[Reg.scala 27:20] - wire _T_9825 = _T_4767 ? 1'h0 : ic_tag_valid_out_1_74; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_10005 = _T_10004 | _T_9825; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9825 = _T_4767 ? 1'h0 : ic_tag_valid_out_1_74; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_10005 = _T_10004 | _T_9825; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_75; // @[Reg.scala 27:20] - wire _T_9827 = _T_4771 ? 1'h0 : ic_tag_valid_out_1_75; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_10006 = _T_10005 | _T_9827; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9827 = _T_4771 ? 1'h0 : ic_tag_valid_out_1_75; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_10006 = _T_10005 | _T_9827; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_76; // @[Reg.scala 27:20] - wire _T_9829 = _T_4775 ? 1'h0 : ic_tag_valid_out_1_76; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_10007 = _T_10006 | _T_9829; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9829 = _T_4775 ? 1'h0 : ic_tag_valid_out_1_76; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_10007 = _T_10006 | _T_9829; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_77; // @[Reg.scala 27:20] - wire _T_9831 = _T_4779 ? 1'h0 : ic_tag_valid_out_1_77; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_10008 = _T_10007 | _T_9831; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9831 = _T_4779 ? 1'h0 : ic_tag_valid_out_1_77; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_10008 = _T_10007 | _T_9831; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_78; // @[Reg.scala 27:20] - wire _T_9833 = _T_4783 ? 1'h0 : ic_tag_valid_out_1_78; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_10009 = _T_10008 | _T_9833; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9833 = _T_4783 ? 1'h0 : ic_tag_valid_out_1_78; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_10009 = _T_10008 | _T_9833; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_79; // @[Reg.scala 27:20] - wire _T_9835 = _T_4787 ? 1'h0 : ic_tag_valid_out_1_79; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_10010 = _T_10009 | _T_9835; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9835 = _T_4787 ? 1'h0 : ic_tag_valid_out_1_79; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_10010 = _T_10009 | _T_9835; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_80; // @[Reg.scala 27:20] - wire _T_9837 = _T_4791 ? 1'h0 : ic_tag_valid_out_1_80; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_10011 = _T_10010 | _T_9837; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9837 = _T_4791 ? 1'h0 : ic_tag_valid_out_1_80; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_10011 = _T_10010 | _T_9837; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_81; // @[Reg.scala 27:20] - wire _T_9839 = _T_4795 ? 1'h0 : ic_tag_valid_out_1_81; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_10012 = _T_10011 | _T_9839; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9839 = _T_4795 ? 1'h0 : ic_tag_valid_out_1_81; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_10012 = _T_10011 | _T_9839; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_82; // @[Reg.scala 27:20] - wire _T_9841 = _T_4799 ? 1'h0 : ic_tag_valid_out_1_82; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_10013 = _T_10012 | _T_9841; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9841 = _T_4799 ? 1'h0 : ic_tag_valid_out_1_82; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_10013 = _T_10012 | _T_9841; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_83; // @[Reg.scala 27:20] - wire _T_9843 = _T_4803 ? 1'h0 : ic_tag_valid_out_1_83; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_10014 = _T_10013 | _T_9843; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9843 = _T_4803 ? 1'h0 : ic_tag_valid_out_1_83; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_10014 = _T_10013 | _T_9843; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_84; // @[Reg.scala 27:20] - wire _T_9845 = _T_4807 ? 1'h0 : ic_tag_valid_out_1_84; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_10015 = _T_10014 | _T_9845; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9845 = _T_4807 ? 1'h0 : ic_tag_valid_out_1_84; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_10015 = _T_10014 | _T_9845; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_85; // @[Reg.scala 27:20] - wire _T_9847 = _T_4811 ? 1'h0 : ic_tag_valid_out_1_85; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_10016 = _T_10015 | _T_9847; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9847 = _T_4811 ? 1'h0 : ic_tag_valid_out_1_85; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_10016 = _T_10015 | _T_9847; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_86; // @[Reg.scala 27:20] - wire _T_9849 = _T_4815 ? 1'h0 : ic_tag_valid_out_1_86; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_10017 = _T_10016 | _T_9849; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9849 = _T_4815 ? 1'h0 : ic_tag_valid_out_1_86; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_10017 = _T_10016 | _T_9849; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_87; // @[Reg.scala 27:20] - wire _T_9851 = _T_4819 ? 1'h0 : ic_tag_valid_out_1_87; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_10018 = _T_10017 | _T_9851; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9851 = _T_4819 ? 1'h0 : ic_tag_valid_out_1_87; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_10018 = _T_10017 | _T_9851; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_88; // @[Reg.scala 27:20] - wire _T_9853 = _T_4823 ? 1'h0 : ic_tag_valid_out_1_88; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_10019 = _T_10018 | _T_9853; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9853 = _T_4823 ? 1'h0 : ic_tag_valid_out_1_88; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_10019 = _T_10018 | _T_9853; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_89; // @[Reg.scala 27:20] - wire _T_9855 = _T_4827 ? 1'h0 : ic_tag_valid_out_1_89; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_10020 = _T_10019 | _T_9855; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9855 = _T_4827 ? 1'h0 : ic_tag_valid_out_1_89; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_10020 = _T_10019 | _T_9855; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_90; // @[Reg.scala 27:20] - wire _T_9857 = _T_4831 ? 1'h0 : ic_tag_valid_out_1_90; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_10021 = _T_10020 | _T_9857; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9857 = _T_4831 ? 1'h0 : ic_tag_valid_out_1_90; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_10021 = _T_10020 | _T_9857; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_91; // @[Reg.scala 27:20] - wire _T_9859 = _T_4835 ? 1'h0 : ic_tag_valid_out_1_91; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_10022 = _T_10021 | _T_9859; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9859 = _T_4835 ? 1'h0 : ic_tag_valid_out_1_91; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_10022 = _T_10021 | _T_9859; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_92; // @[Reg.scala 27:20] - wire _T_9861 = _T_4839 ? 1'h0 : ic_tag_valid_out_1_92; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_10023 = _T_10022 | _T_9861; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9861 = _T_4839 ? 1'h0 : ic_tag_valid_out_1_92; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_10023 = _T_10022 | _T_9861; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_93; // @[Reg.scala 27:20] - wire _T_9863 = _T_4843 ? 1'h0 : ic_tag_valid_out_1_93; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_10024 = _T_10023 | _T_9863; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9863 = _T_4843 ? 1'h0 : ic_tag_valid_out_1_93; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_10024 = _T_10023 | _T_9863; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_94; // @[Reg.scala 27:20] - wire _T_9865 = _T_4847 ? 1'h0 : ic_tag_valid_out_1_94; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_10025 = _T_10024 | _T_9865; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9865 = _T_4847 ? 1'h0 : ic_tag_valid_out_1_94; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_10025 = _T_10024 | _T_9865; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_95; // @[Reg.scala 27:20] - wire _T_9867 = _T_4851 ? 1'h0 : ic_tag_valid_out_1_95; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_10026 = _T_10025 | _T_9867; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9867 = _T_4851 ? 1'h0 : ic_tag_valid_out_1_95; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_10026 = _T_10025 | _T_9867; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_96; // @[Reg.scala 27:20] - wire _T_9869 = _T_4855 ? 1'h0 : ic_tag_valid_out_1_96; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_10027 = _T_10026 | _T_9869; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9869 = _T_4855 ? 1'h0 : ic_tag_valid_out_1_96; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_10027 = _T_10026 | _T_9869; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_97; // @[Reg.scala 27:20] - wire _T_9871 = _T_4859 ? 1'h0 : ic_tag_valid_out_1_97; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_10028 = _T_10027 | _T_9871; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9871 = _T_4859 ? 1'h0 : ic_tag_valid_out_1_97; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_10028 = _T_10027 | _T_9871; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_98; // @[Reg.scala 27:20] - wire _T_9873 = _T_4863 ? 1'h0 : ic_tag_valid_out_1_98; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_10029 = _T_10028 | _T_9873; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9873 = _T_4863 ? 1'h0 : ic_tag_valid_out_1_98; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_10029 = _T_10028 | _T_9873; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_99; // @[Reg.scala 27:20] - wire _T_9875 = _T_4867 ? 1'h0 : ic_tag_valid_out_1_99; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_10030 = _T_10029 | _T_9875; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9875 = _T_4867 ? 1'h0 : ic_tag_valid_out_1_99; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_10030 = _T_10029 | _T_9875; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_100; // @[Reg.scala 27:20] - wire _T_9877 = _T_4871 ? 1'h0 : ic_tag_valid_out_1_100; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_10031 = _T_10030 | _T_9877; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9877 = _T_4871 ? 1'h0 : ic_tag_valid_out_1_100; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_10031 = _T_10030 | _T_9877; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_101; // @[Reg.scala 27:20] - wire _T_9879 = _T_4875 ? 1'h0 : ic_tag_valid_out_1_101; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_10032 = _T_10031 | _T_9879; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9879 = _T_4875 ? 1'h0 : ic_tag_valid_out_1_101; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_10032 = _T_10031 | _T_9879; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_102; // @[Reg.scala 27:20] - wire _T_9881 = _T_4879 ? 1'h0 : ic_tag_valid_out_1_102; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_10033 = _T_10032 | _T_9881; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9881 = _T_4879 ? 1'h0 : ic_tag_valid_out_1_102; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_10033 = _T_10032 | _T_9881; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_103; // @[Reg.scala 27:20] - wire _T_9883 = _T_4883 ? 1'h0 : ic_tag_valid_out_1_103; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_10034 = _T_10033 | _T_9883; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9883 = _T_4883 ? 1'h0 : ic_tag_valid_out_1_103; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_10034 = _T_10033 | _T_9883; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_104; // @[Reg.scala 27:20] - wire _T_9885 = _T_4887 ? 1'h0 : ic_tag_valid_out_1_104; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_10035 = _T_10034 | _T_9885; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9885 = _T_4887 ? 1'h0 : ic_tag_valid_out_1_104; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_10035 = _T_10034 | _T_9885; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_105; // @[Reg.scala 27:20] - wire _T_9887 = _T_4891 ? 1'h0 : ic_tag_valid_out_1_105; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_10036 = _T_10035 | _T_9887; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9887 = _T_4891 ? 1'h0 : ic_tag_valid_out_1_105; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_10036 = _T_10035 | _T_9887; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_106; // @[Reg.scala 27:20] - wire _T_9889 = _T_4895 ? 1'h0 : ic_tag_valid_out_1_106; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_10037 = _T_10036 | _T_9889; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9889 = _T_4895 ? 1'h0 : ic_tag_valid_out_1_106; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_10037 = _T_10036 | _T_9889; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_107; // @[Reg.scala 27:20] - wire _T_9891 = _T_4899 ? 1'h0 : ic_tag_valid_out_1_107; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_10038 = _T_10037 | _T_9891; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9891 = _T_4899 ? 1'h0 : ic_tag_valid_out_1_107; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_10038 = _T_10037 | _T_9891; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_108; // @[Reg.scala 27:20] - wire _T_9893 = _T_4903 ? 1'h0 : ic_tag_valid_out_1_108; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_10039 = _T_10038 | _T_9893; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9893 = _T_4903 ? 1'h0 : ic_tag_valid_out_1_108; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_10039 = _T_10038 | _T_9893; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_109; // @[Reg.scala 27:20] - wire _T_9895 = _T_4907 ? 1'h0 : ic_tag_valid_out_1_109; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_10040 = _T_10039 | _T_9895; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9895 = _T_4907 ? 1'h0 : ic_tag_valid_out_1_109; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_10040 = _T_10039 | _T_9895; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_110; // @[Reg.scala 27:20] - wire _T_9897 = _T_4911 ? 1'h0 : ic_tag_valid_out_1_110; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_10041 = _T_10040 | _T_9897; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9897 = _T_4911 ? 1'h0 : ic_tag_valid_out_1_110; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_10041 = _T_10040 | _T_9897; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_111; // @[Reg.scala 27:20] - wire _T_9899 = _T_4915 ? 1'h0 : ic_tag_valid_out_1_111; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_10042 = _T_10041 | _T_9899; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9899 = _T_4915 ? 1'h0 : ic_tag_valid_out_1_111; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_10042 = _T_10041 | _T_9899; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_112; // @[Reg.scala 27:20] - wire _T_9901 = _T_4919 ? 1'h0 : ic_tag_valid_out_1_112; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_10043 = _T_10042 | _T_9901; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9901 = _T_4919 ? 1'h0 : ic_tag_valid_out_1_112; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_10043 = _T_10042 | _T_9901; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_113; // @[Reg.scala 27:20] - wire _T_9903 = _T_4923 ? 1'h0 : ic_tag_valid_out_1_113; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_10044 = _T_10043 | _T_9903; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9903 = _T_4923 ? 1'h0 : ic_tag_valid_out_1_113; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_10044 = _T_10043 | _T_9903; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_114; // @[Reg.scala 27:20] - wire _T_9905 = _T_4927 ? 1'h0 : ic_tag_valid_out_1_114; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_10045 = _T_10044 | _T_9905; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9905 = _T_4927 ? 1'h0 : ic_tag_valid_out_1_114; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_10045 = _T_10044 | _T_9905; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_115; // @[Reg.scala 27:20] - wire _T_9907 = _T_4931 ? 1'h0 : ic_tag_valid_out_1_115; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_10046 = _T_10045 | _T_9907; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9907 = _T_4931 ? 1'h0 : ic_tag_valid_out_1_115; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_10046 = _T_10045 | _T_9907; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_116; // @[Reg.scala 27:20] - wire _T_9909 = _T_4935 ? 1'h0 : ic_tag_valid_out_1_116; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_10047 = _T_10046 | _T_9909; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9909 = _T_4935 ? 1'h0 : ic_tag_valid_out_1_116; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_10047 = _T_10046 | _T_9909; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_117; // @[Reg.scala 27:20] - wire _T_9911 = _T_4939 ? 1'h0 : ic_tag_valid_out_1_117; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_10048 = _T_10047 | _T_9911; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9911 = _T_4939 ? 1'h0 : ic_tag_valid_out_1_117; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_10048 = _T_10047 | _T_9911; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_118; // @[Reg.scala 27:20] - wire _T_9913 = _T_4943 ? 1'h0 : ic_tag_valid_out_1_118; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_10049 = _T_10048 | _T_9913; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9913 = _T_4943 ? 1'h0 : ic_tag_valid_out_1_118; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_10049 = _T_10048 | _T_9913; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_119; // @[Reg.scala 27:20] - wire _T_9915 = _T_4947 ? 1'h0 : ic_tag_valid_out_1_119; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_10050 = _T_10049 | _T_9915; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9915 = _T_4947 ? 1'h0 : ic_tag_valid_out_1_119; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_10050 = _T_10049 | _T_9915; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_120; // @[Reg.scala 27:20] - wire _T_9917 = _T_4951 ? 1'h0 : ic_tag_valid_out_1_120; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_10051 = _T_10050 | _T_9917; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9917 = _T_4951 ? 1'h0 : ic_tag_valid_out_1_120; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_10051 = _T_10050 | _T_9917; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_121; // @[Reg.scala 27:20] - wire _T_9919 = _T_4955 ? 1'h0 : ic_tag_valid_out_1_121; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_10052 = _T_10051 | _T_9919; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9919 = _T_4955 ? 1'h0 : ic_tag_valid_out_1_121; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_10052 = _T_10051 | _T_9919; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_122; // @[Reg.scala 27:20] - wire _T_9921 = _T_4959 ? 1'h0 : ic_tag_valid_out_1_122; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_10053 = _T_10052 | _T_9921; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9921 = _T_4959 ? 1'h0 : ic_tag_valid_out_1_122; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_10053 = _T_10052 | _T_9921; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_123; // @[Reg.scala 27:20] - wire _T_9923 = _T_4963 ? 1'h0 : ic_tag_valid_out_1_123; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_10054 = _T_10053 | _T_9923; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9923 = _T_4963 ? 1'h0 : ic_tag_valid_out_1_123; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_10054 = _T_10053 | _T_9923; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_124; // @[Reg.scala 27:20] - wire _T_9925 = _T_4967 ? 1'h0 : ic_tag_valid_out_1_124; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_10055 = _T_10054 | _T_9925; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9925 = _T_4967 ? 1'h0 : ic_tag_valid_out_1_124; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_10055 = _T_10054 | _T_9925; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_125; // @[Reg.scala 27:20] - wire _T_9927 = _T_4971 ? 1'h0 : ic_tag_valid_out_1_125; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_10056 = _T_10055 | _T_9927; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9927 = _T_4971 ? 1'h0 : ic_tag_valid_out_1_125; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_10056 = _T_10055 | _T_9927; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_126; // @[Reg.scala 27:20] - wire _T_9929 = _T_4975 ? 1'h0 : ic_tag_valid_out_1_126; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_10057 = _T_10056 | _T_9929; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9929 = _T_4975 ? 1'h0 : ic_tag_valid_out_1_126; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_10057 = _T_10056 | _T_9929; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_1_127; // @[Reg.scala 27:20] - wire _T_9931 = _T_4979 ? 1'h0 : ic_tag_valid_out_1_127; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_10058 = _T_10057 | _T_9931; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9931 = _T_4979 ? 1'h0 : ic_tag_valid_out_1_127; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_10058 = _T_10057 | _T_9931; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_0; // @[Reg.scala 27:20] - wire _T_9294 = _T_4471 ? 1'h0 : ic_tag_valid_out_0_0; // @[el2_ifu_mem_ctl.scala 744:10] + wire _T_9294 = _T_4471 ? 1'h0 : ic_tag_valid_out_0_0; // @[el2_ifu_mem_ctl.scala 745:10] reg ic_tag_valid_out_0_1; // @[Reg.scala 27:20] - wire _T_9296 = _T_4475 ? 1'h0 : ic_tag_valid_out_0_1; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9549 = _T_9294 | _T_9296; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9296 = _T_4475 ? 1'h0 : ic_tag_valid_out_0_1; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9549 = _T_9294 | _T_9296; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_2; // @[Reg.scala 27:20] - wire _T_9298 = _T_4479 ? 1'h0 : ic_tag_valid_out_0_2; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9550 = _T_9549 | _T_9298; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9298 = _T_4479 ? 1'h0 : ic_tag_valid_out_0_2; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9550 = _T_9549 | _T_9298; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_3; // @[Reg.scala 27:20] - wire _T_9300 = _T_4483 ? 1'h0 : ic_tag_valid_out_0_3; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9551 = _T_9550 | _T_9300; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9300 = _T_4483 ? 1'h0 : ic_tag_valid_out_0_3; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9551 = _T_9550 | _T_9300; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_4; // @[Reg.scala 27:20] - wire _T_9302 = _T_4487 ? 1'h0 : ic_tag_valid_out_0_4; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9552 = _T_9551 | _T_9302; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9302 = _T_4487 ? 1'h0 : ic_tag_valid_out_0_4; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9552 = _T_9551 | _T_9302; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_5; // @[Reg.scala 27:20] - wire _T_9304 = _T_4491 ? 1'h0 : ic_tag_valid_out_0_5; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9553 = _T_9552 | _T_9304; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9304 = _T_4491 ? 1'h0 : ic_tag_valid_out_0_5; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9553 = _T_9552 | _T_9304; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_6; // @[Reg.scala 27:20] - wire _T_9306 = _T_4495 ? 1'h0 : ic_tag_valid_out_0_6; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9554 = _T_9553 | _T_9306; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9306 = _T_4495 ? 1'h0 : ic_tag_valid_out_0_6; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9554 = _T_9553 | _T_9306; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_7; // @[Reg.scala 27:20] - wire _T_9308 = _T_4499 ? 1'h0 : ic_tag_valid_out_0_7; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9555 = _T_9554 | _T_9308; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9308 = _T_4499 ? 1'h0 : ic_tag_valid_out_0_7; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9555 = _T_9554 | _T_9308; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_8; // @[Reg.scala 27:20] - wire _T_9310 = _T_4503 ? 1'h0 : ic_tag_valid_out_0_8; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9556 = _T_9555 | _T_9310; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9310 = _T_4503 ? 1'h0 : ic_tag_valid_out_0_8; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9556 = _T_9555 | _T_9310; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_9; // @[Reg.scala 27:20] - wire _T_9312 = _T_4507 ? 1'h0 : ic_tag_valid_out_0_9; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9557 = _T_9556 | _T_9312; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9312 = _T_4507 ? 1'h0 : ic_tag_valid_out_0_9; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9557 = _T_9556 | _T_9312; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_10; // @[Reg.scala 27:20] - wire _T_9314 = _T_4511 ? 1'h0 : ic_tag_valid_out_0_10; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9558 = _T_9557 | _T_9314; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9314 = _T_4511 ? 1'h0 : ic_tag_valid_out_0_10; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9558 = _T_9557 | _T_9314; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_11; // @[Reg.scala 27:20] - wire _T_9316 = _T_4515 ? 1'h0 : ic_tag_valid_out_0_11; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9559 = _T_9558 | _T_9316; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9316 = _T_4515 ? 1'h0 : ic_tag_valid_out_0_11; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9559 = _T_9558 | _T_9316; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_12; // @[Reg.scala 27:20] - wire _T_9318 = _T_4519 ? 1'h0 : ic_tag_valid_out_0_12; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9560 = _T_9559 | _T_9318; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9318 = _T_4519 ? 1'h0 : ic_tag_valid_out_0_12; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9560 = _T_9559 | _T_9318; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_13; // @[Reg.scala 27:20] - wire _T_9320 = _T_4523 ? 1'h0 : ic_tag_valid_out_0_13; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9561 = _T_9560 | _T_9320; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9320 = _T_4523 ? 1'h0 : ic_tag_valid_out_0_13; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9561 = _T_9560 | _T_9320; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_14; // @[Reg.scala 27:20] - wire _T_9322 = _T_4527 ? 1'h0 : ic_tag_valid_out_0_14; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9562 = _T_9561 | _T_9322; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9322 = _T_4527 ? 1'h0 : ic_tag_valid_out_0_14; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9562 = _T_9561 | _T_9322; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_15; // @[Reg.scala 27:20] - wire _T_9324 = _T_4531 ? 1'h0 : ic_tag_valid_out_0_15; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9563 = _T_9562 | _T_9324; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9324 = _T_4531 ? 1'h0 : ic_tag_valid_out_0_15; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9563 = _T_9562 | _T_9324; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_16; // @[Reg.scala 27:20] - wire _T_9326 = _T_4535 ? 1'h0 : ic_tag_valid_out_0_16; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9564 = _T_9563 | _T_9326; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9326 = _T_4535 ? 1'h0 : ic_tag_valid_out_0_16; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9564 = _T_9563 | _T_9326; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_17; // @[Reg.scala 27:20] - wire _T_9328 = _T_4539 ? 1'h0 : ic_tag_valid_out_0_17; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9565 = _T_9564 | _T_9328; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9328 = _T_4539 ? 1'h0 : ic_tag_valid_out_0_17; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9565 = _T_9564 | _T_9328; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_18; // @[Reg.scala 27:20] - wire _T_9330 = _T_4543 ? 1'h0 : ic_tag_valid_out_0_18; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9566 = _T_9565 | _T_9330; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9330 = _T_4543 ? 1'h0 : ic_tag_valid_out_0_18; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9566 = _T_9565 | _T_9330; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_19; // @[Reg.scala 27:20] - wire _T_9332 = _T_4547 ? 1'h0 : ic_tag_valid_out_0_19; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9567 = _T_9566 | _T_9332; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9332 = _T_4547 ? 1'h0 : ic_tag_valid_out_0_19; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9567 = _T_9566 | _T_9332; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_20; // @[Reg.scala 27:20] - wire _T_9334 = _T_4551 ? 1'h0 : ic_tag_valid_out_0_20; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9568 = _T_9567 | _T_9334; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9334 = _T_4551 ? 1'h0 : ic_tag_valid_out_0_20; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9568 = _T_9567 | _T_9334; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_21; // @[Reg.scala 27:20] - wire _T_9336 = _T_4555 ? 1'h0 : ic_tag_valid_out_0_21; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9569 = _T_9568 | _T_9336; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9336 = _T_4555 ? 1'h0 : ic_tag_valid_out_0_21; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9569 = _T_9568 | _T_9336; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_22; // @[Reg.scala 27:20] - wire _T_9338 = _T_4559 ? 1'h0 : ic_tag_valid_out_0_22; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9570 = _T_9569 | _T_9338; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9338 = _T_4559 ? 1'h0 : ic_tag_valid_out_0_22; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9570 = _T_9569 | _T_9338; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_23; // @[Reg.scala 27:20] - wire _T_9340 = _T_4563 ? 1'h0 : ic_tag_valid_out_0_23; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9571 = _T_9570 | _T_9340; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9340 = _T_4563 ? 1'h0 : ic_tag_valid_out_0_23; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9571 = _T_9570 | _T_9340; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_24; // @[Reg.scala 27:20] - wire _T_9342 = _T_4567 ? 1'h0 : ic_tag_valid_out_0_24; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9572 = _T_9571 | _T_9342; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9342 = _T_4567 ? 1'h0 : ic_tag_valid_out_0_24; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9572 = _T_9571 | _T_9342; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_25; // @[Reg.scala 27:20] - wire _T_9344 = _T_4571 ? 1'h0 : ic_tag_valid_out_0_25; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9573 = _T_9572 | _T_9344; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9344 = _T_4571 ? 1'h0 : ic_tag_valid_out_0_25; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9573 = _T_9572 | _T_9344; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_26; // @[Reg.scala 27:20] - wire _T_9346 = _T_4575 ? 1'h0 : ic_tag_valid_out_0_26; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9574 = _T_9573 | _T_9346; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9346 = _T_4575 ? 1'h0 : ic_tag_valid_out_0_26; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9574 = _T_9573 | _T_9346; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_27; // @[Reg.scala 27:20] - wire _T_9348 = _T_4579 ? 1'h0 : ic_tag_valid_out_0_27; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9575 = _T_9574 | _T_9348; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9348 = _T_4579 ? 1'h0 : ic_tag_valid_out_0_27; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9575 = _T_9574 | _T_9348; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_28; // @[Reg.scala 27:20] - wire _T_9350 = _T_4583 ? 1'h0 : ic_tag_valid_out_0_28; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9576 = _T_9575 | _T_9350; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9350 = _T_4583 ? 1'h0 : ic_tag_valid_out_0_28; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9576 = _T_9575 | _T_9350; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_29; // @[Reg.scala 27:20] - wire _T_9352 = _T_4587 ? 1'h0 : ic_tag_valid_out_0_29; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9577 = _T_9576 | _T_9352; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9352 = _T_4587 ? 1'h0 : ic_tag_valid_out_0_29; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9577 = _T_9576 | _T_9352; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_30; // @[Reg.scala 27:20] - wire _T_9354 = _T_4591 ? 1'h0 : ic_tag_valid_out_0_30; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9578 = _T_9577 | _T_9354; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9354 = _T_4591 ? 1'h0 : ic_tag_valid_out_0_30; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9578 = _T_9577 | _T_9354; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_31; // @[Reg.scala 27:20] - wire _T_9356 = _T_4595 ? 1'h0 : ic_tag_valid_out_0_31; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9579 = _T_9578 | _T_9356; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9356 = _T_4595 ? 1'h0 : ic_tag_valid_out_0_31; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9579 = _T_9578 | _T_9356; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_32; // @[Reg.scala 27:20] - wire _T_9358 = _T_4599 ? 1'h0 : ic_tag_valid_out_0_32; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9580 = _T_9579 | _T_9358; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9358 = _T_4599 ? 1'h0 : ic_tag_valid_out_0_32; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9580 = _T_9579 | _T_9358; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_33; // @[Reg.scala 27:20] - wire _T_9360 = _T_4603 ? 1'h0 : ic_tag_valid_out_0_33; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9581 = _T_9580 | _T_9360; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9360 = _T_4603 ? 1'h0 : ic_tag_valid_out_0_33; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9581 = _T_9580 | _T_9360; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_34; // @[Reg.scala 27:20] - wire _T_9362 = _T_4607 ? 1'h0 : ic_tag_valid_out_0_34; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9582 = _T_9581 | _T_9362; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9362 = _T_4607 ? 1'h0 : ic_tag_valid_out_0_34; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9582 = _T_9581 | _T_9362; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_35; // @[Reg.scala 27:20] - wire _T_9364 = _T_4611 ? 1'h0 : ic_tag_valid_out_0_35; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9583 = _T_9582 | _T_9364; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9364 = _T_4611 ? 1'h0 : ic_tag_valid_out_0_35; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9583 = _T_9582 | _T_9364; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_36; // @[Reg.scala 27:20] - wire _T_9366 = _T_4615 ? 1'h0 : ic_tag_valid_out_0_36; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9584 = _T_9583 | _T_9366; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9366 = _T_4615 ? 1'h0 : ic_tag_valid_out_0_36; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9584 = _T_9583 | _T_9366; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_37; // @[Reg.scala 27:20] - wire _T_9368 = _T_4619 ? 1'h0 : ic_tag_valid_out_0_37; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9585 = _T_9584 | _T_9368; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9368 = _T_4619 ? 1'h0 : ic_tag_valid_out_0_37; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9585 = _T_9584 | _T_9368; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_38; // @[Reg.scala 27:20] - wire _T_9370 = _T_4623 ? 1'h0 : ic_tag_valid_out_0_38; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9586 = _T_9585 | _T_9370; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9370 = _T_4623 ? 1'h0 : ic_tag_valid_out_0_38; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9586 = _T_9585 | _T_9370; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_39; // @[Reg.scala 27:20] - wire _T_9372 = _T_4627 ? 1'h0 : ic_tag_valid_out_0_39; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9587 = _T_9586 | _T_9372; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9372 = _T_4627 ? 1'h0 : ic_tag_valid_out_0_39; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9587 = _T_9586 | _T_9372; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_40; // @[Reg.scala 27:20] - wire _T_9374 = _T_4631 ? 1'h0 : ic_tag_valid_out_0_40; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9588 = _T_9587 | _T_9374; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9374 = _T_4631 ? 1'h0 : ic_tag_valid_out_0_40; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9588 = _T_9587 | _T_9374; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_41; // @[Reg.scala 27:20] - wire _T_9376 = _T_4635 ? 1'h0 : ic_tag_valid_out_0_41; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9589 = _T_9588 | _T_9376; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9376 = _T_4635 ? 1'h0 : ic_tag_valid_out_0_41; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9589 = _T_9588 | _T_9376; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_42; // @[Reg.scala 27:20] - wire _T_9378 = _T_4639 ? 1'h0 : ic_tag_valid_out_0_42; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9590 = _T_9589 | _T_9378; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9378 = _T_4639 ? 1'h0 : ic_tag_valid_out_0_42; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9590 = _T_9589 | _T_9378; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_43; // @[Reg.scala 27:20] - wire _T_9380 = _T_4643 ? 1'h0 : ic_tag_valid_out_0_43; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9591 = _T_9590 | _T_9380; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9380 = _T_4643 ? 1'h0 : ic_tag_valid_out_0_43; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9591 = _T_9590 | _T_9380; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_44; // @[Reg.scala 27:20] - wire _T_9382 = _T_4647 ? 1'h0 : ic_tag_valid_out_0_44; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9592 = _T_9591 | _T_9382; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9382 = _T_4647 ? 1'h0 : ic_tag_valid_out_0_44; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9592 = _T_9591 | _T_9382; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_45; // @[Reg.scala 27:20] - wire _T_9384 = _T_4651 ? 1'h0 : ic_tag_valid_out_0_45; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9593 = _T_9592 | _T_9384; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9384 = _T_4651 ? 1'h0 : ic_tag_valid_out_0_45; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9593 = _T_9592 | _T_9384; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_46; // @[Reg.scala 27:20] - wire _T_9386 = _T_4655 ? 1'h0 : ic_tag_valid_out_0_46; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9594 = _T_9593 | _T_9386; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9386 = _T_4655 ? 1'h0 : ic_tag_valid_out_0_46; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9594 = _T_9593 | _T_9386; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_47; // @[Reg.scala 27:20] - wire _T_9388 = _T_4659 ? 1'h0 : ic_tag_valid_out_0_47; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9595 = _T_9594 | _T_9388; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9388 = _T_4659 ? 1'h0 : ic_tag_valid_out_0_47; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9595 = _T_9594 | _T_9388; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_48; // @[Reg.scala 27:20] - wire _T_9390 = _T_4663 ? 1'h0 : ic_tag_valid_out_0_48; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9596 = _T_9595 | _T_9390; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9390 = _T_4663 ? 1'h0 : ic_tag_valid_out_0_48; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9596 = _T_9595 | _T_9390; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_49; // @[Reg.scala 27:20] - wire _T_9392 = _T_4667 ? 1'h0 : ic_tag_valid_out_0_49; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9597 = _T_9596 | _T_9392; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9392 = _T_4667 ? 1'h0 : ic_tag_valid_out_0_49; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9597 = _T_9596 | _T_9392; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_50; // @[Reg.scala 27:20] - wire _T_9394 = _T_4671 ? 1'h0 : ic_tag_valid_out_0_50; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9598 = _T_9597 | _T_9394; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9394 = _T_4671 ? 1'h0 : ic_tag_valid_out_0_50; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9598 = _T_9597 | _T_9394; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_51; // @[Reg.scala 27:20] - wire _T_9396 = _T_4675 ? 1'h0 : ic_tag_valid_out_0_51; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9599 = _T_9598 | _T_9396; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9396 = _T_4675 ? 1'h0 : ic_tag_valid_out_0_51; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9599 = _T_9598 | _T_9396; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_52; // @[Reg.scala 27:20] - wire _T_9398 = _T_4679 ? 1'h0 : ic_tag_valid_out_0_52; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9600 = _T_9599 | _T_9398; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9398 = _T_4679 ? 1'h0 : ic_tag_valid_out_0_52; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9600 = _T_9599 | _T_9398; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_53; // @[Reg.scala 27:20] - wire _T_9400 = _T_4683 ? 1'h0 : ic_tag_valid_out_0_53; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9601 = _T_9600 | _T_9400; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9400 = _T_4683 ? 1'h0 : ic_tag_valid_out_0_53; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9601 = _T_9600 | _T_9400; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_54; // @[Reg.scala 27:20] - wire _T_9402 = _T_4687 ? 1'h0 : ic_tag_valid_out_0_54; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9602 = _T_9601 | _T_9402; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9402 = _T_4687 ? 1'h0 : ic_tag_valid_out_0_54; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9602 = _T_9601 | _T_9402; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_55; // @[Reg.scala 27:20] - wire _T_9404 = _T_4691 ? 1'h0 : ic_tag_valid_out_0_55; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9603 = _T_9602 | _T_9404; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9404 = _T_4691 ? 1'h0 : ic_tag_valid_out_0_55; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9603 = _T_9602 | _T_9404; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_56; // @[Reg.scala 27:20] - wire _T_9406 = _T_4695 ? 1'h0 : ic_tag_valid_out_0_56; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9604 = _T_9603 | _T_9406; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9406 = _T_4695 ? 1'h0 : ic_tag_valid_out_0_56; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9604 = _T_9603 | _T_9406; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_57; // @[Reg.scala 27:20] - wire _T_9408 = _T_4699 ? 1'h0 : ic_tag_valid_out_0_57; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9605 = _T_9604 | _T_9408; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9408 = _T_4699 ? 1'h0 : ic_tag_valid_out_0_57; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9605 = _T_9604 | _T_9408; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_58; // @[Reg.scala 27:20] - wire _T_9410 = _T_4703 ? 1'h0 : ic_tag_valid_out_0_58; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9606 = _T_9605 | _T_9410; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9410 = _T_4703 ? 1'h0 : ic_tag_valid_out_0_58; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9606 = _T_9605 | _T_9410; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_59; // @[Reg.scala 27:20] - wire _T_9412 = _T_4707 ? 1'h0 : ic_tag_valid_out_0_59; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9607 = _T_9606 | _T_9412; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9412 = _T_4707 ? 1'h0 : ic_tag_valid_out_0_59; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9607 = _T_9606 | _T_9412; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_60; // @[Reg.scala 27:20] - wire _T_9414 = _T_4711 ? 1'h0 : ic_tag_valid_out_0_60; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9608 = _T_9607 | _T_9414; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9414 = _T_4711 ? 1'h0 : ic_tag_valid_out_0_60; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9608 = _T_9607 | _T_9414; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_61; // @[Reg.scala 27:20] - wire _T_9416 = _T_4715 ? 1'h0 : ic_tag_valid_out_0_61; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9609 = _T_9608 | _T_9416; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9416 = _T_4715 ? 1'h0 : ic_tag_valid_out_0_61; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9609 = _T_9608 | _T_9416; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_62; // @[Reg.scala 27:20] - wire _T_9418 = _T_4719 ? 1'h0 : ic_tag_valid_out_0_62; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9610 = _T_9609 | _T_9418; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9418 = _T_4719 ? 1'h0 : ic_tag_valid_out_0_62; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9610 = _T_9609 | _T_9418; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_63; // @[Reg.scala 27:20] - wire _T_9420 = _T_4723 ? 1'h0 : ic_tag_valid_out_0_63; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9611 = _T_9610 | _T_9420; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9420 = _T_4723 ? 1'h0 : ic_tag_valid_out_0_63; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9611 = _T_9610 | _T_9420; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_64; // @[Reg.scala 27:20] - wire _T_9422 = _T_4727 ? 1'h0 : ic_tag_valid_out_0_64; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9612 = _T_9611 | _T_9422; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9422 = _T_4727 ? 1'h0 : ic_tag_valid_out_0_64; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9612 = _T_9611 | _T_9422; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_65; // @[Reg.scala 27:20] - wire _T_9424 = _T_4731 ? 1'h0 : ic_tag_valid_out_0_65; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9613 = _T_9612 | _T_9424; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9424 = _T_4731 ? 1'h0 : ic_tag_valid_out_0_65; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9613 = _T_9612 | _T_9424; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_66; // @[Reg.scala 27:20] - wire _T_9426 = _T_4735 ? 1'h0 : ic_tag_valid_out_0_66; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9614 = _T_9613 | _T_9426; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9426 = _T_4735 ? 1'h0 : ic_tag_valid_out_0_66; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9614 = _T_9613 | _T_9426; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_67; // @[Reg.scala 27:20] - wire _T_9428 = _T_4739 ? 1'h0 : ic_tag_valid_out_0_67; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9615 = _T_9614 | _T_9428; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9428 = _T_4739 ? 1'h0 : ic_tag_valid_out_0_67; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9615 = _T_9614 | _T_9428; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_68; // @[Reg.scala 27:20] - wire _T_9430 = _T_4743 ? 1'h0 : ic_tag_valid_out_0_68; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9616 = _T_9615 | _T_9430; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9430 = _T_4743 ? 1'h0 : ic_tag_valid_out_0_68; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9616 = _T_9615 | _T_9430; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_69; // @[Reg.scala 27:20] - wire _T_9432 = _T_4747 ? 1'h0 : ic_tag_valid_out_0_69; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9617 = _T_9616 | _T_9432; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9432 = _T_4747 ? 1'h0 : ic_tag_valid_out_0_69; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9617 = _T_9616 | _T_9432; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_70; // @[Reg.scala 27:20] - wire _T_9434 = _T_4751 ? 1'h0 : ic_tag_valid_out_0_70; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9618 = _T_9617 | _T_9434; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9434 = _T_4751 ? 1'h0 : ic_tag_valid_out_0_70; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9618 = _T_9617 | _T_9434; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_71; // @[Reg.scala 27:20] - wire _T_9436 = _T_4755 ? 1'h0 : ic_tag_valid_out_0_71; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9619 = _T_9618 | _T_9436; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9436 = _T_4755 ? 1'h0 : ic_tag_valid_out_0_71; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9619 = _T_9618 | _T_9436; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_72; // @[Reg.scala 27:20] - wire _T_9438 = _T_4759 ? 1'h0 : ic_tag_valid_out_0_72; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9620 = _T_9619 | _T_9438; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9438 = _T_4759 ? 1'h0 : ic_tag_valid_out_0_72; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9620 = _T_9619 | _T_9438; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_73; // @[Reg.scala 27:20] - wire _T_9440 = _T_4763 ? 1'h0 : ic_tag_valid_out_0_73; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9621 = _T_9620 | _T_9440; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9440 = _T_4763 ? 1'h0 : ic_tag_valid_out_0_73; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9621 = _T_9620 | _T_9440; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_74; // @[Reg.scala 27:20] - wire _T_9442 = _T_4767 ? 1'h0 : ic_tag_valid_out_0_74; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9622 = _T_9621 | _T_9442; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9442 = _T_4767 ? 1'h0 : ic_tag_valid_out_0_74; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9622 = _T_9621 | _T_9442; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_75; // @[Reg.scala 27:20] - wire _T_9444 = _T_4771 ? 1'h0 : ic_tag_valid_out_0_75; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9623 = _T_9622 | _T_9444; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9444 = _T_4771 ? 1'h0 : ic_tag_valid_out_0_75; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9623 = _T_9622 | _T_9444; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_76; // @[Reg.scala 27:20] - wire _T_9446 = _T_4775 ? 1'h0 : ic_tag_valid_out_0_76; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9624 = _T_9623 | _T_9446; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9446 = _T_4775 ? 1'h0 : ic_tag_valid_out_0_76; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9624 = _T_9623 | _T_9446; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_77; // @[Reg.scala 27:20] - wire _T_9448 = _T_4779 ? 1'h0 : ic_tag_valid_out_0_77; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9625 = _T_9624 | _T_9448; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9448 = _T_4779 ? 1'h0 : ic_tag_valid_out_0_77; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9625 = _T_9624 | _T_9448; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_78; // @[Reg.scala 27:20] - wire _T_9450 = _T_4783 ? 1'h0 : ic_tag_valid_out_0_78; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9626 = _T_9625 | _T_9450; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9450 = _T_4783 ? 1'h0 : ic_tag_valid_out_0_78; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9626 = _T_9625 | _T_9450; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_79; // @[Reg.scala 27:20] - wire _T_9452 = _T_4787 ? 1'h0 : ic_tag_valid_out_0_79; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9627 = _T_9626 | _T_9452; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9452 = _T_4787 ? 1'h0 : ic_tag_valid_out_0_79; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9627 = _T_9626 | _T_9452; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_80; // @[Reg.scala 27:20] - wire _T_9454 = _T_4791 ? 1'h0 : ic_tag_valid_out_0_80; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9628 = _T_9627 | _T_9454; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9454 = _T_4791 ? 1'h0 : ic_tag_valid_out_0_80; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9628 = _T_9627 | _T_9454; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_81; // @[Reg.scala 27:20] - wire _T_9456 = _T_4795 ? 1'h0 : ic_tag_valid_out_0_81; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9629 = _T_9628 | _T_9456; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9456 = _T_4795 ? 1'h0 : ic_tag_valid_out_0_81; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9629 = _T_9628 | _T_9456; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_82; // @[Reg.scala 27:20] - wire _T_9458 = _T_4799 ? 1'h0 : ic_tag_valid_out_0_82; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9630 = _T_9629 | _T_9458; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9458 = _T_4799 ? 1'h0 : ic_tag_valid_out_0_82; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9630 = _T_9629 | _T_9458; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_83; // @[Reg.scala 27:20] - wire _T_9460 = _T_4803 ? 1'h0 : ic_tag_valid_out_0_83; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9631 = _T_9630 | _T_9460; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9460 = _T_4803 ? 1'h0 : ic_tag_valid_out_0_83; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9631 = _T_9630 | _T_9460; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_84; // @[Reg.scala 27:20] - wire _T_9462 = _T_4807 ? 1'h0 : ic_tag_valid_out_0_84; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9632 = _T_9631 | _T_9462; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9462 = _T_4807 ? 1'h0 : ic_tag_valid_out_0_84; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9632 = _T_9631 | _T_9462; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_85; // @[Reg.scala 27:20] - wire _T_9464 = _T_4811 ? 1'h0 : ic_tag_valid_out_0_85; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9633 = _T_9632 | _T_9464; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9464 = _T_4811 ? 1'h0 : ic_tag_valid_out_0_85; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9633 = _T_9632 | _T_9464; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_86; // @[Reg.scala 27:20] - wire _T_9466 = _T_4815 ? 1'h0 : ic_tag_valid_out_0_86; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9634 = _T_9633 | _T_9466; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9466 = _T_4815 ? 1'h0 : ic_tag_valid_out_0_86; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9634 = _T_9633 | _T_9466; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_87; // @[Reg.scala 27:20] - wire _T_9468 = _T_4819 ? 1'h0 : ic_tag_valid_out_0_87; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9635 = _T_9634 | _T_9468; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9468 = _T_4819 ? 1'h0 : ic_tag_valid_out_0_87; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9635 = _T_9634 | _T_9468; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_88; // @[Reg.scala 27:20] - wire _T_9470 = _T_4823 ? 1'h0 : ic_tag_valid_out_0_88; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9636 = _T_9635 | _T_9470; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9470 = _T_4823 ? 1'h0 : ic_tag_valid_out_0_88; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9636 = _T_9635 | _T_9470; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_89; // @[Reg.scala 27:20] - wire _T_9472 = _T_4827 ? 1'h0 : ic_tag_valid_out_0_89; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9637 = _T_9636 | _T_9472; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9472 = _T_4827 ? 1'h0 : ic_tag_valid_out_0_89; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9637 = _T_9636 | _T_9472; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_90; // @[Reg.scala 27:20] - wire _T_9474 = _T_4831 ? 1'h0 : ic_tag_valid_out_0_90; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9638 = _T_9637 | _T_9474; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9474 = _T_4831 ? 1'h0 : ic_tag_valid_out_0_90; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9638 = _T_9637 | _T_9474; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_91; // @[Reg.scala 27:20] - wire _T_9476 = _T_4835 ? 1'h0 : ic_tag_valid_out_0_91; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9639 = _T_9638 | _T_9476; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9476 = _T_4835 ? 1'h0 : ic_tag_valid_out_0_91; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9639 = _T_9638 | _T_9476; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_92; // @[Reg.scala 27:20] - wire _T_9478 = _T_4839 ? 1'h0 : ic_tag_valid_out_0_92; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9640 = _T_9639 | _T_9478; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9478 = _T_4839 ? 1'h0 : ic_tag_valid_out_0_92; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9640 = _T_9639 | _T_9478; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_93; // @[Reg.scala 27:20] - wire _T_9480 = _T_4843 ? 1'h0 : ic_tag_valid_out_0_93; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9641 = _T_9640 | _T_9480; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9480 = _T_4843 ? 1'h0 : ic_tag_valid_out_0_93; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9641 = _T_9640 | _T_9480; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_94; // @[Reg.scala 27:20] - wire _T_9482 = _T_4847 ? 1'h0 : ic_tag_valid_out_0_94; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9642 = _T_9641 | _T_9482; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9482 = _T_4847 ? 1'h0 : ic_tag_valid_out_0_94; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9642 = _T_9641 | _T_9482; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_95; // @[Reg.scala 27:20] - wire _T_9484 = _T_4851 ? 1'h0 : ic_tag_valid_out_0_95; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9643 = _T_9642 | _T_9484; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9484 = _T_4851 ? 1'h0 : ic_tag_valid_out_0_95; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9643 = _T_9642 | _T_9484; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_96; // @[Reg.scala 27:20] - wire _T_9486 = _T_4855 ? 1'h0 : ic_tag_valid_out_0_96; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9644 = _T_9643 | _T_9486; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9486 = _T_4855 ? 1'h0 : ic_tag_valid_out_0_96; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9644 = _T_9643 | _T_9486; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_97; // @[Reg.scala 27:20] - wire _T_9488 = _T_4859 ? 1'h0 : ic_tag_valid_out_0_97; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9645 = _T_9644 | _T_9488; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9488 = _T_4859 ? 1'h0 : ic_tag_valid_out_0_97; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9645 = _T_9644 | _T_9488; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_98; // @[Reg.scala 27:20] - wire _T_9490 = _T_4863 ? 1'h0 : ic_tag_valid_out_0_98; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9646 = _T_9645 | _T_9490; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9490 = _T_4863 ? 1'h0 : ic_tag_valid_out_0_98; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9646 = _T_9645 | _T_9490; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_99; // @[Reg.scala 27:20] - wire _T_9492 = _T_4867 ? 1'h0 : ic_tag_valid_out_0_99; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9647 = _T_9646 | _T_9492; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9492 = _T_4867 ? 1'h0 : ic_tag_valid_out_0_99; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9647 = _T_9646 | _T_9492; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_100; // @[Reg.scala 27:20] - wire _T_9494 = _T_4871 ? 1'h0 : ic_tag_valid_out_0_100; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9648 = _T_9647 | _T_9494; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9494 = _T_4871 ? 1'h0 : ic_tag_valid_out_0_100; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9648 = _T_9647 | _T_9494; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_101; // @[Reg.scala 27:20] - wire _T_9496 = _T_4875 ? 1'h0 : ic_tag_valid_out_0_101; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9649 = _T_9648 | _T_9496; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9496 = _T_4875 ? 1'h0 : ic_tag_valid_out_0_101; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9649 = _T_9648 | _T_9496; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_102; // @[Reg.scala 27:20] - wire _T_9498 = _T_4879 ? 1'h0 : ic_tag_valid_out_0_102; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9650 = _T_9649 | _T_9498; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9498 = _T_4879 ? 1'h0 : ic_tag_valid_out_0_102; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9650 = _T_9649 | _T_9498; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_103; // @[Reg.scala 27:20] - wire _T_9500 = _T_4883 ? 1'h0 : ic_tag_valid_out_0_103; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9651 = _T_9650 | _T_9500; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9500 = _T_4883 ? 1'h0 : ic_tag_valid_out_0_103; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9651 = _T_9650 | _T_9500; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_104; // @[Reg.scala 27:20] - wire _T_9502 = _T_4887 ? 1'h0 : ic_tag_valid_out_0_104; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9652 = _T_9651 | _T_9502; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9502 = _T_4887 ? 1'h0 : ic_tag_valid_out_0_104; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9652 = _T_9651 | _T_9502; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_105; // @[Reg.scala 27:20] - wire _T_9504 = _T_4891 ? 1'h0 : ic_tag_valid_out_0_105; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9653 = _T_9652 | _T_9504; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9504 = _T_4891 ? 1'h0 : ic_tag_valid_out_0_105; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9653 = _T_9652 | _T_9504; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_106; // @[Reg.scala 27:20] - wire _T_9506 = _T_4895 ? 1'h0 : ic_tag_valid_out_0_106; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9654 = _T_9653 | _T_9506; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9506 = _T_4895 ? 1'h0 : ic_tag_valid_out_0_106; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9654 = _T_9653 | _T_9506; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_107; // @[Reg.scala 27:20] - wire _T_9508 = _T_4899 ? 1'h0 : ic_tag_valid_out_0_107; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9655 = _T_9654 | _T_9508; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9508 = _T_4899 ? 1'h0 : ic_tag_valid_out_0_107; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9655 = _T_9654 | _T_9508; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_108; // @[Reg.scala 27:20] - wire _T_9510 = _T_4903 ? 1'h0 : ic_tag_valid_out_0_108; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9656 = _T_9655 | _T_9510; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9510 = _T_4903 ? 1'h0 : ic_tag_valid_out_0_108; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9656 = _T_9655 | _T_9510; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_109; // @[Reg.scala 27:20] - wire _T_9512 = _T_4907 ? 1'h0 : ic_tag_valid_out_0_109; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9657 = _T_9656 | _T_9512; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9512 = _T_4907 ? 1'h0 : ic_tag_valid_out_0_109; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9657 = _T_9656 | _T_9512; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_110; // @[Reg.scala 27:20] - wire _T_9514 = _T_4911 ? 1'h0 : ic_tag_valid_out_0_110; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9658 = _T_9657 | _T_9514; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9514 = _T_4911 ? 1'h0 : ic_tag_valid_out_0_110; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9658 = _T_9657 | _T_9514; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_111; // @[Reg.scala 27:20] - wire _T_9516 = _T_4915 ? 1'h0 : ic_tag_valid_out_0_111; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9659 = _T_9658 | _T_9516; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9516 = _T_4915 ? 1'h0 : ic_tag_valid_out_0_111; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9659 = _T_9658 | _T_9516; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_112; // @[Reg.scala 27:20] - wire _T_9518 = _T_4919 ? 1'h0 : ic_tag_valid_out_0_112; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9660 = _T_9659 | _T_9518; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9518 = _T_4919 ? 1'h0 : ic_tag_valid_out_0_112; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9660 = _T_9659 | _T_9518; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_113; // @[Reg.scala 27:20] - wire _T_9520 = _T_4923 ? 1'h0 : ic_tag_valid_out_0_113; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9661 = _T_9660 | _T_9520; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9520 = _T_4923 ? 1'h0 : ic_tag_valid_out_0_113; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9661 = _T_9660 | _T_9520; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_114; // @[Reg.scala 27:20] - wire _T_9522 = _T_4927 ? 1'h0 : ic_tag_valid_out_0_114; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9662 = _T_9661 | _T_9522; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9522 = _T_4927 ? 1'h0 : ic_tag_valid_out_0_114; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9662 = _T_9661 | _T_9522; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_115; // @[Reg.scala 27:20] - wire _T_9524 = _T_4931 ? 1'h0 : ic_tag_valid_out_0_115; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9663 = _T_9662 | _T_9524; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9524 = _T_4931 ? 1'h0 : ic_tag_valid_out_0_115; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9663 = _T_9662 | _T_9524; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_116; // @[Reg.scala 27:20] - wire _T_9526 = _T_4935 ? 1'h0 : ic_tag_valid_out_0_116; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9664 = _T_9663 | _T_9526; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9526 = _T_4935 ? 1'h0 : ic_tag_valid_out_0_116; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9664 = _T_9663 | _T_9526; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_117; // @[Reg.scala 27:20] - wire _T_9528 = _T_4939 ? 1'h0 : ic_tag_valid_out_0_117; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9665 = _T_9664 | _T_9528; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9528 = _T_4939 ? 1'h0 : ic_tag_valid_out_0_117; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9665 = _T_9664 | _T_9528; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_118; // @[Reg.scala 27:20] - wire _T_9530 = _T_4943 ? 1'h0 : ic_tag_valid_out_0_118; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9666 = _T_9665 | _T_9530; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9530 = _T_4943 ? 1'h0 : ic_tag_valid_out_0_118; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9666 = _T_9665 | _T_9530; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_119; // @[Reg.scala 27:20] - wire _T_9532 = _T_4947 ? 1'h0 : ic_tag_valid_out_0_119; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9667 = _T_9666 | _T_9532; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9532 = _T_4947 ? 1'h0 : ic_tag_valid_out_0_119; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9667 = _T_9666 | _T_9532; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_120; // @[Reg.scala 27:20] - wire _T_9534 = _T_4951 ? 1'h0 : ic_tag_valid_out_0_120; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9668 = _T_9667 | _T_9534; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9534 = _T_4951 ? 1'h0 : ic_tag_valid_out_0_120; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9668 = _T_9667 | _T_9534; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_121; // @[Reg.scala 27:20] - wire _T_9536 = _T_4955 ? 1'h0 : ic_tag_valid_out_0_121; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9669 = _T_9668 | _T_9536; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9536 = _T_4955 ? 1'h0 : ic_tag_valid_out_0_121; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9669 = _T_9668 | _T_9536; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_122; // @[Reg.scala 27:20] - wire _T_9538 = _T_4959 ? 1'h0 : ic_tag_valid_out_0_122; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9670 = _T_9669 | _T_9538; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9538 = _T_4959 ? 1'h0 : ic_tag_valid_out_0_122; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9670 = _T_9669 | _T_9538; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_123; // @[Reg.scala 27:20] - wire _T_9540 = _T_4963 ? 1'h0 : ic_tag_valid_out_0_123; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9671 = _T_9670 | _T_9540; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9540 = _T_4963 ? 1'h0 : ic_tag_valid_out_0_123; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9671 = _T_9670 | _T_9540; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_124; // @[Reg.scala 27:20] - wire _T_9542 = _T_4967 ? 1'h0 : ic_tag_valid_out_0_124; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9672 = _T_9671 | _T_9542; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9542 = _T_4967 ? 1'h0 : ic_tag_valid_out_0_124; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9672 = _T_9671 | _T_9542; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_125; // @[Reg.scala 27:20] - wire _T_9544 = _T_4971 ? 1'h0 : ic_tag_valid_out_0_125; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9673 = _T_9672 | _T_9544; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9544 = _T_4971 ? 1'h0 : ic_tag_valid_out_0_125; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9673 = _T_9672 | _T_9544; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_126; // @[Reg.scala 27:20] - wire _T_9546 = _T_4975 ? 1'h0 : ic_tag_valid_out_0_126; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9674 = _T_9673 | _T_9546; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9546 = _T_4975 ? 1'h0 : ic_tag_valid_out_0_126; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9674 = _T_9673 | _T_9546; // @[el2_ifu_mem_ctl.scala 745:91] reg ic_tag_valid_out_0_127; // @[Reg.scala 27:20] - wire _T_9548 = _T_4979 ? 1'h0 : ic_tag_valid_out_0_127; // @[el2_ifu_mem_ctl.scala 744:10] - wire _T_9675 = _T_9674 | _T_9548; // @[el2_ifu_mem_ctl.scala 744:91] + wire _T_9548 = _T_4979 ? 1'h0 : ic_tag_valid_out_0_127; // @[el2_ifu_mem_ctl.scala 745:10] + wire _T_9675 = _T_9674 | _T_9548; // @[el2_ifu_mem_ctl.scala 745:91] wire [1:0] ic_tag_valid_unq = {_T_10058,_T_9675}; // @[Cat.scala 29:58] reg [1:0] ic_debug_way_ff; // @[Reg.scala 27:20] - reg ic_debug_rd_en_ff; // @[el2_ifu_mem_ctl.scala 817:54] + reg ic_debug_rd_en_ff; // @[el2_ifu_mem_ctl.scala 818:54] wire [1:0] _T_10097 = ic_debug_rd_en_ff ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_10098 = ic_debug_way_ff & _T_10097; // @[el2_ifu_mem_ctl.scala 798:67] - wire [1:0] _T_10099 = ic_tag_valid_unq & _T_10098; // @[el2_ifu_mem_ctl.scala 798:48] - wire ic_debug_tag_val_rd_out = |_T_10099; // @[el2_ifu_mem_ctl.scala 798:115] + wire [1:0] _T_10098 = ic_debug_way_ff & _T_10097; // @[el2_ifu_mem_ctl.scala 799:67] + wire [1:0] _T_10099 = ic_tag_valid_unq & _T_10098; // @[el2_ifu_mem_ctl.scala 799:48] + wire ic_debug_tag_val_rd_out = |_T_10099; // @[el2_ifu_mem_ctl.scala 799:115] wire [65:0] _T_1210 = {2'h0,io_ictag_debug_rd_data[25:21],32'h0,io_ictag_debug_rd_data[20:0],1'h0,way_status,3'h0,ic_debug_tag_val_rd_out}; // @[Cat.scala 29:58] - reg [70:0] _T_1211; // @[el2_ifu_mem_ctl.scala 348:37] - wire ifu_wr_cumulative_err = ifu_wr_cumulative_err_data & _T_2539; // @[el2_ifu_mem_ctl.scala 358:80] - wire _T_1251 = ~ifu_byp_data_err_new; // @[el2_ifu_mem_ctl.scala 363:98] - wire sel_byp_data = _T_1255 & _T_1251; // @[el2_ifu_mem_ctl.scala 363:96] + reg [70:0] _T_1211; // @[el2_ifu_mem_ctl.scala 349:37] + wire ifu_wr_cumulative_err = ifu_wr_cumulative_err_data & _T_2539; // @[el2_ifu_mem_ctl.scala 359:80] + wire _T_1251 = ~ifu_byp_data_err_new; // @[el2_ifu_mem_ctl.scala 364:98] + wire sel_byp_data = _T_1255 & _T_1251; // @[el2_ifu_mem_ctl.scala 364:96] wire [63:0] _T_1262 = fetch_req_iccm_f ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12] - wire [63:0] _T_1263 = _T_1262 & io_iccm_rd_data; // @[el2_ifu_mem_ctl.scala 370:64] + wire [63:0] _T_1263 = _T_1262 & io_iccm_rd_data; // @[el2_ifu_mem_ctl.scala 371:64] wire [63:0] _T_1265 = sel_byp_data ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12] - wire _T_2101 = ~ifu_fetch_addr_int_f[0]; // @[el2_ifu_mem_ctl.scala 439:31] + wire _T_2101 = ~ifu_fetch_addr_int_f[0]; // @[el2_ifu_mem_ctl.scala 440:31] wire [3:0] byp_fetch_index_inc_0 = {byp_fetch_index_inc,1'h0}; // @[Cat.scala 29:58] - wire _T_1615 = byp_fetch_index_inc_0 == 4'h0; // @[el2_ifu_mem_ctl.scala 436:73] + wire _T_1615 = byp_fetch_index_inc_0 == 4'h0; // @[el2_ifu_mem_ctl.scala 437:73] wire [15:0] _T_1663 = _T_1615 ? ic_miss_buff_data_0[15:0] : 16'h0; // @[Mux.scala 27:72] - wire _T_1618 = byp_fetch_index_inc_0 == 4'h1; // @[el2_ifu_mem_ctl.scala 436:73] + wire _T_1618 = byp_fetch_index_inc_0 == 4'h1; // @[el2_ifu_mem_ctl.scala 437:73] wire [15:0] _T_1664 = _T_1618 ? ic_miss_buff_data_1[15:0] : 16'h0; // @[Mux.scala 27:72] wire [15:0] _T_1679 = _T_1663 | _T_1664; // @[Mux.scala 27:72] - wire _T_1621 = byp_fetch_index_inc_0 == 4'h2; // @[el2_ifu_mem_ctl.scala 436:73] + wire _T_1621 = byp_fetch_index_inc_0 == 4'h2; // @[el2_ifu_mem_ctl.scala 437:73] wire [15:0] _T_1665 = _T_1621 ? ic_miss_buff_data_2[15:0] : 16'h0; // @[Mux.scala 27:72] wire [15:0] _T_1680 = _T_1679 | _T_1665; // @[Mux.scala 27:72] - wire _T_1624 = byp_fetch_index_inc_0 == 4'h3; // @[el2_ifu_mem_ctl.scala 436:73] + wire _T_1624 = byp_fetch_index_inc_0 == 4'h3; // @[el2_ifu_mem_ctl.scala 437:73] wire [15:0] _T_1666 = _T_1624 ? ic_miss_buff_data_3[15:0] : 16'h0; // @[Mux.scala 27:72] wire [15:0] _T_1681 = _T_1680 | _T_1666; // @[Mux.scala 27:72] - wire _T_1627 = byp_fetch_index_inc_0 == 4'h4; // @[el2_ifu_mem_ctl.scala 436:73] + wire _T_1627 = byp_fetch_index_inc_0 == 4'h4; // @[el2_ifu_mem_ctl.scala 437:73] wire [15:0] _T_1667 = _T_1627 ? ic_miss_buff_data_4[15:0] : 16'h0; // @[Mux.scala 27:72] wire [15:0] _T_1682 = _T_1681 | _T_1667; // @[Mux.scala 27:72] - wire _T_1630 = byp_fetch_index_inc_0 == 4'h5; // @[el2_ifu_mem_ctl.scala 436:73] + wire _T_1630 = byp_fetch_index_inc_0 == 4'h5; // @[el2_ifu_mem_ctl.scala 437:73] wire [15:0] _T_1668 = _T_1630 ? ic_miss_buff_data_5[15:0] : 16'h0; // @[Mux.scala 27:72] wire [15:0] _T_1683 = _T_1682 | _T_1668; // @[Mux.scala 27:72] - wire _T_1633 = byp_fetch_index_inc_0 == 4'h6; // @[el2_ifu_mem_ctl.scala 436:73] + wire _T_1633 = byp_fetch_index_inc_0 == 4'h6; // @[el2_ifu_mem_ctl.scala 437:73] wire [15:0] _T_1669 = _T_1633 ? ic_miss_buff_data_6[15:0] : 16'h0; // @[Mux.scala 27:72] wire [15:0] _T_1684 = _T_1683 | _T_1669; // @[Mux.scala 27:72] - wire _T_1636 = byp_fetch_index_inc_0 == 4'h7; // @[el2_ifu_mem_ctl.scala 436:73] + wire _T_1636 = byp_fetch_index_inc_0 == 4'h7; // @[el2_ifu_mem_ctl.scala 437:73] wire [15:0] _T_1670 = _T_1636 ? ic_miss_buff_data_7[15:0] : 16'h0; // @[Mux.scala 27:72] wire [15:0] _T_1685 = _T_1684 | _T_1670; // @[Mux.scala 27:72] - wire _T_1639 = byp_fetch_index_inc_0 == 4'h8; // @[el2_ifu_mem_ctl.scala 436:73] + wire _T_1639 = byp_fetch_index_inc_0 == 4'h8; // @[el2_ifu_mem_ctl.scala 437:73] wire [15:0] _T_1671 = _T_1639 ? ic_miss_buff_data_8[15:0] : 16'h0; // @[Mux.scala 27:72] wire [15:0] _T_1686 = _T_1685 | _T_1671; // @[Mux.scala 27:72] - wire _T_1642 = byp_fetch_index_inc_0 == 4'h9; // @[el2_ifu_mem_ctl.scala 436:73] + wire _T_1642 = byp_fetch_index_inc_0 == 4'h9; // @[el2_ifu_mem_ctl.scala 437:73] wire [15:0] _T_1672 = _T_1642 ? ic_miss_buff_data_9[15:0] : 16'h0; // @[Mux.scala 27:72] wire [15:0] _T_1687 = _T_1686 | _T_1672; // @[Mux.scala 27:72] - wire _T_1645 = byp_fetch_index_inc_0 == 4'ha; // @[el2_ifu_mem_ctl.scala 436:73] + wire _T_1645 = byp_fetch_index_inc_0 == 4'ha; // @[el2_ifu_mem_ctl.scala 437:73] wire [15:0] _T_1673 = _T_1645 ? ic_miss_buff_data_10[15:0] : 16'h0; // @[Mux.scala 27:72] wire [15:0] _T_1688 = _T_1687 | _T_1673; // @[Mux.scala 27:72] - wire _T_1648 = byp_fetch_index_inc_0 == 4'hb; // @[el2_ifu_mem_ctl.scala 436:73] + wire _T_1648 = byp_fetch_index_inc_0 == 4'hb; // @[el2_ifu_mem_ctl.scala 437:73] wire [15:0] _T_1674 = _T_1648 ? ic_miss_buff_data_11[15:0] : 16'h0; // @[Mux.scala 27:72] wire [15:0] _T_1689 = _T_1688 | _T_1674; // @[Mux.scala 27:72] - wire _T_1651 = byp_fetch_index_inc_0 == 4'hc; // @[el2_ifu_mem_ctl.scala 436:73] + wire _T_1651 = byp_fetch_index_inc_0 == 4'hc; // @[el2_ifu_mem_ctl.scala 437:73] wire [15:0] _T_1675 = _T_1651 ? ic_miss_buff_data_12[15:0] : 16'h0; // @[Mux.scala 27:72] wire [15:0] _T_1690 = _T_1689 | _T_1675; // @[Mux.scala 27:72] - wire _T_1654 = byp_fetch_index_inc_0 == 4'hd; // @[el2_ifu_mem_ctl.scala 436:73] + wire _T_1654 = byp_fetch_index_inc_0 == 4'hd; // @[el2_ifu_mem_ctl.scala 437:73] wire [15:0] _T_1676 = _T_1654 ? ic_miss_buff_data_13[15:0] : 16'h0; // @[Mux.scala 27:72] wire [15:0] _T_1691 = _T_1690 | _T_1676; // @[Mux.scala 27:72] - wire _T_1657 = byp_fetch_index_inc_0 == 4'he; // @[el2_ifu_mem_ctl.scala 436:73] + wire _T_1657 = byp_fetch_index_inc_0 == 4'he; // @[el2_ifu_mem_ctl.scala 437:73] wire [15:0] _T_1677 = _T_1657 ? ic_miss_buff_data_14[15:0] : 16'h0; // @[Mux.scala 27:72] wire [15:0] _T_1692 = _T_1691 | _T_1677; // @[Mux.scala 27:72] - wire _T_1660 = byp_fetch_index_inc_0 == 4'hf; // @[el2_ifu_mem_ctl.scala 436:73] + wire _T_1660 = byp_fetch_index_inc_0 == 4'hf; // @[el2_ifu_mem_ctl.scala 437:73] wire [15:0] _T_1678 = _T_1660 ? ic_miss_buff_data_15[15:0] : 16'h0; // @[Mux.scala 27:72] wire [15:0] _T_1693 = _T_1692 | _T_1678; // @[Mux.scala 27:72] wire [3:0] byp_fetch_index_1 = {ifu_fetch_addr_int_f[4:2],1'h1}; // @[Cat.scala 29:58] - wire _T_1695 = byp_fetch_index_1 == 4'h0; // @[el2_ifu_mem_ctl.scala 436:179] + wire _T_1695 = byp_fetch_index_1 == 4'h0; // @[el2_ifu_mem_ctl.scala 437:179] wire [31:0] _T_1743 = _T_1695 ? ic_miss_buff_data_0 : 32'h0; // @[Mux.scala 27:72] - wire _T_1698 = byp_fetch_index_1 == 4'h1; // @[el2_ifu_mem_ctl.scala 436:179] + wire _T_1698 = byp_fetch_index_1 == 4'h1; // @[el2_ifu_mem_ctl.scala 437:179] wire [31:0] _T_1744 = _T_1698 ? ic_miss_buff_data_1 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_1759 = _T_1743 | _T_1744; // @[Mux.scala 27:72] - wire _T_1701 = byp_fetch_index_1 == 4'h2; // @[el2_ifu_mem_ctl.scala 436:179] + wire _T_1701 = byp_fetch_index_1 == 4'h2; // @[el2_ifu_mem_ctl.scala 437:179] wire [31:0] _T_1745 = _T_1701 ? ic_miss_buff_data_2 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_1760 = _T_1759 | _T_1745; // @[Mux.scala 27:72] - wire _T_1704 = byp_fetch_index_1 == 4'h3; // @[el2_ifu_mem_ctl.scala 436:179] + wire _T_1704 = byp_fetch_index_1 == 4'h3; // @[el2_ifu_mem_ctl.scala 437:179] wire [31:0] _T_1746 = _T_1704 ? ic_miss_buff_data_3 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_1761 = _T_1760 | _T_1746; // @[Mux.scala 27:72] - wire _T_1707 = byp_fetch_index_1 == 4'h4; // @[el2_ifu_mem_ctl.scala 436:179] + wire _T_1707 = byp_fetch_index_1 == 4'h4; // @[el2_ifu_mem_ctl.scala 437:179] wire [31:0] _T_1747 = _T_1707 ? ic_miss_buff_data_4 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_1762 = _T_1761 | _T_1747; // @[Mux.scala 27:72] - wire _T_1710 = byp_fetch_index_1 == 4'h5; // @[el2_ifu_mem_ctl.scala 436:179] + wire _T_1710 = byp_fetch_index_1 == 4'h5; // @[el2_ifu_mem_ctl.scala 437:179] wire [31:0] _T_1748 = _T_1710 ? ic_miss_buff_data_5 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_1763 = _T_1762 | _T_1748; // @[Mux.scala 27:72] - wire _T_1713 = byp_fetch_index_1 == 4'h6; // @[el2_ifu_mem_ctl.scala 436:179] + wire _T_1713 = byp_fetch_index_1 == 4'h6; // @[el2_ifu_mem_ctl.scala 437:179] wire [31:0] _T_1749 = _T_1713 ? ic_miss_buff_data_6 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_1764 = _T_1763 | _T_1749; // @[Mux.scala 27:72] - wire _T_1716 = byp_fetch_index_1 == 4'h7; // @[el2_ifu_mem_ctl.scala 436:179] + wire _T_1716 = byp_fetch_index_1 == 4'h7; // @[el2_ifu_mem_ctl.scala 437:179] wire [31:0] _T_1750 = _T_1716 ? ic_miss_buff_data_7 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_1765 = _T_1764 | _T_1750; // @[Mux.scala 27:72] - wire _T_1719 = byp_fetch_index_1 == 4'h8; // @[el2_ifu_mem_ctl.scala 436:179] + wire _T_1719 = byp_fetch_index_1 == 4'h8; // @[el2_ifu_mem_ctl.scala 437:179] wire [31:0] _T_1751 = _T_1719 ? ic_miss_buff_data_8 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_1766 = _T_1765 | _T_1751; // @[Mux.scala 27:72] - wire _T_1722 = byp_fetch_index_1 == 4'h9; // @[el2_ifu_mem_ctl.scala 436:179] + wire _T_1722 = byp_fetch_index_1 == 4'h9; // @[el2_ifu_mem_ctl.scala 437:179] wire [31:0] _T_1752 = _T_1722 ? ic_miss_buff_data_9 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_1767 = _T_1766 | _T_1752; // @[Mux.scala 27:72] - wire _T_1725 = byp_fetch_index_1 == 4'ha; // @[el2_ifu_mem_ctl.scala 436:179] + wire _T_1725 = byp_fetch_index_1 == 4'ha; // @[el2_ifu_mem_ctl.scala 437:179] wire [31:0] _T_1753 = _T_1725 ? ic_miss_buff_data_10 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_1768 = _T_1767 | _T_1753; // @[Mux.scala 27:72] - wire _T_1728 = byp_fetch_index_1 == 4'hb; // @[el2_ifu_mem_ctl.scala 436:179] + wire _T_1728 = byp_fetch_index_1 == 4'hb; // @[el2_ifu_mem_ctl.scala 437:179] wire [31:0] _T_1754 = _T_1728 ? ic_miss_buff_data_11 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_1769 = _T_1768 | _T_1754; // @[Mux.scala 27:72] - wire _T_1731 = byp_fetch_index_1 == 4'hc; // @[el2_ifu_mem_ctl.scala 436:179] + wire _T_1731 = byp_fetch_index_1 == 4'hc; // @[el2_ifu_mem_ctl.scala 437:179] wire [31:0] _T_1755 = _T_1731 ? ic_miss_buff_data_12 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_1770 = _T_1769 | _T_1755; // @[Mux.scala 27:72] - wire _T_1734 = byp_fetch_index_1 == 4'hd; // @[el2_ifu_mem_ctl.scala 436:179] + wire _T_1734 = byp_fetch_index_1 == 4'hd; // @[el2_ifu_mem_ctl.scala 437:179] wire [31:0] _T_1756 = _T_1734 ? ic_miss_buff_data_13 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_1771 = _T_1770 | _T_1756; // @[Mux.scala 27:72] - wire _T_1737 = byp_fetch_index_1 == 4'he; // @[el2_ifu_mem_ctl.scala 436:179] + wire _T_1737 = byp_fetch_index_1 == 4'he; // @[el2_ifu_mem_ctl.scala 437:179] wire [31:0] _T_1757 = _T_1737 ? ic_miss_buff_data_14 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_1772 = _T_1771 | _T_1757; // @[Mux.scala 27:72] - wire _T_1740 = byp_fetch_index_1 == 4'hf; // @[el2_ifu_mem_ctl.scala 436:179] + wire _T_1740 = byp_fetch_index_1 == 4'hf; // @[el2_ifu_mem_ctl.scala 437:179] wire [31:0] _T_1758 = _T_1740 ? ic_miss_buff_data_15 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_1773 = _T_1772 | _T_1758; // @[Mux.scala 27:72] wire [3:0] byp_fetch_index_0 = {ifu_fetch_addr_int_f[4:2],1'h0}; // @[Cat.scala 29:58] - wire _T_1775 = byp_fetch_index_0 == 4'h0; // @[el2_ifu_mem_ctl.scala 436:285] + wire _T_1775 = byp_fetch_index_0 == 4'h0; // @[el2_ifu_mem_ctl.scala 437:285] wire [31:0] _T_1823 = _T_1775 ? ic_miss_buff_data_0 : 32'h0; // @[Mux.scala 27:72] - wire _T_1778 = byp_fetch_index_0 == 4'h1; // @[el2_ifu_mem_ctl.scala 436:285] + wire _T_1778 = byp_fetch_index_0 == 4'h1; // @[el2_ifu_mem_ctl.scala 437:285] wire [31:0] _T_1824 = _T_1778 ? ic_miss_buff_data_1 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_1839 = _T_1823 | _T_1824; // @[Mux.scala 27:72] - wire _T_1781 = byp_fetch_index_0 == 4'h2; // @[el2_ifu_mem_ctl.scala 436:285] + wire _T_1781 = byp_fetch_index_0 == 4'h2; // @[el2_ifu_mem_ctl.scala 437:285] wire [31:0] _T_1825 = _T_1781 ? ic_miss_buff_data_2 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_1840 = _T_1839 | _T_1825; // @[Mux.scala 27:72] - wire _T_1784 = byp_fetch_index_0 == 4'h3; // @[el2_ifu_mem_ctl.scala 436:285] + wire _T_1784 = byp_fetch_index_0 == 4'h3; // @[el2_ifu_mem_ctl.scala 437:285] wire [31:0] _T_1826 = _T_1784 ? ic_miss_buff_data_3 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_1841 = _T_1840 | _T_1826; // @[Mux.scala 27:72] - wire _T_1787 = byp_fetch_index_0 == 4'h4; // @[el2_ifu_mem_ctl.scala 436:285] + wire _T_1787 = byp_fetch_index_0 == 4'h4; // @[el2_ifu_mem_ctl.scala 437:285] wire [31:0] _T_1827 = _T_1787 ? ic_miss_buff_data_4 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_1842 = _T_1841 | _T_1827; // @[Mux.scala 27:72] - wire _T_1790 = byp_fetch_index_0 == 4'h5; // @[el2_ifu_mem_ctl.scala 436:285] + wire _T_1790 = byp_fetch_index_0 == 4'h5; // @[el2_ifu_mem_ctl.scala 437:285] wire [31:0] _T_1828 = _T_1790 ? ic_miss_buff_data_5 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_1843 = _T_1842 | _T_1828; // @[Mux.scala 27:72] - wire _T_1793 = byp_fetch_index_0 == 4'h6; // @[el2_ifu_mem_ctl.scala 436:285] + wire _T_1793 = byp_fetch_index_0 == 4'h6; // @[el2_ifu_mem_ctl.scala 437:285] wire [31:0] _T_1829 = _T_1793 ? ic_miss_buff_data_6 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_1844 = _T_1843 | _T_1829; // @[Mux.scala 27:72] - wire _T_1796 = byp_fetch_index_0 == 4'h7; // @[el2_ifu_mem_ctl.scala 436:285] + wire _T_1796 = byp_fetch_index_0 == 4'h7; // @[el2_ifu_mem_ctl.scala 437:285] wire [31:0] _T_1830 = _T_1796 ? ic_miss_buff_data_7 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_1845 = _T_1844 | _T_1830; // @[Mux.scala 27:72] - wire _T_1799 = byp_fetch_index_0 == 4'h8; // @[el2_ifu_mem_ctl.scala 436:285] + wire _T_1799 = byp_fetch_index_0 == 4'h8; // @[el2_ifu_mem_ctl.scala 437:285] wire [31:0] _T_1831 = _T_1799 ? ic_miss_buff_data_8 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_1846 = _T_1845 | _T_1831; // @[Mux.scala 27:72] - wire _T_1802 = byp_fetch_index_0 == 4'h9; // @[el2_ifu_mem_ctl.scala 436:285] + wire _T_1802 = byp_fetch_index_0 == 4'h9; // @[el2_ifu_mem_ctl.scala 437:285] wire [31:0] _T_1832 = _T_1802 ? ic_miss_buff_data_9 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_1847 = _T_1846 | _T_1832; // @[Mux.scala 27:72] - wire _T_1805 = byp_fetch_index_0 == 4'ha; // @[el2_ifu_mem_ctl.scala 436:285] + wire _T_1805 = byp_fetch_index_0 == 4'ha; // @[el2_ifu_mem_ctl.scala 437:285] wire [31:0] _T_1833 = _T_1805 ? ic_miss_buff_data_10 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_1848 = _T_1847 | _T_1833; // @[Mux.scala 27:72] - wire _T_1808 = byp_fetch_index_0 == 4'hb; // @[el2_ifu_mem_ctl.scala 436:285] + wire _T_1808 = byp_fetch_index_0 == 4'hb; // @[el2_ifu_mem_ctl.scala 437:285] wire [31:0] _T_1834 = _T_1808 ? ic_miss_buff_data_11 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_1849 = _T_1848 | _T_1834; // @[Mux.scala 27:72] - wire _T_1811 = byp_fetch_index_0 == 4'hc; // @[el2_ifu_mem_ctl.scala 436:285] + wire _T_1811 = byp_fetch_index_0 == 4'hc; // @[el2_ifu_mem_ctl.scala 437:285] wire [31:0] _T_1835 = _T_1811 ? ic_miss_buff_data_12 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_1850 = _T_1849 | _T_1835; // @[Mux.scala 27:72] - wire _T_1814 = byp_fetch_index_0 == 4'hd; // @[el2_ifu_mem_ctl.scala 436:285] + wire _T_1814 = byp_fetch_index_0 == 4'hd; // @[el2_ifu_mem_ctl.scala 437:285] wire [31:0] _T_1836 = _T_1814 ? ic_miss_buff_data_13 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_1851 = _T_1850 | _T_1836; // @[Mux.scala 27:72] - wire _T_1817 = byp_fetch_index_0 == 4'he; // @[el2_ifu_mem_ctl.scala 436:285] + wire _T_1817 = byp_fetch_index_0 == 4'he; // @[el2_ifu_mem_ctl.scala 437:285] wire [31:0] _T_1837 = _T_1817 ? ic_miss_buff_data_14 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_1852 = _T_1851 | _T_1837; // @[Mux.scala 27:72] - wire _T_1820 = byp_fetch_index_0 == 4'hf; // @[el2_ifu_mem_ctl.scala 436:285] + wire _T_1820 = byp_fetch_index_0 == 4'hf; // @[el2_ifu_mem_ctl.scala 437:285] wire [31:0] _T_1838 = _T_1820 ? ic_miss_buff_data_15 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_1853 = _T_1852 | _T_1838; // @[Mux.scala 27:72] wire [79:0] _T_1856 = {_T_1693,_T_1773,_T_1853}; // @[Cat.scala 29:58] wire [3:0] byp_fetch_index_inc_1 = {byp_fetch_index_inc,1'h1}; // @[Cat.scala 29:58] - wire _T_1857 = byp_fetch_index_inc_1 == 4'h0; // @[el2_ifu_mem_ctl.scala 437:73] + wire _T_1857 = byp_fetch_index_inc_1 == 4'h0; // @[el2_ifu_mem_ctl.scala 438:73] wire [15:0] _T_1905 = _T_1857 ? ic_miss_buff_data_0[15:0] : 16'h0; // @[Mux.scala 27:72] - wire _T_1860 = byp_fetch_index_inc_1 == 4'h1; // @[el2_ifu_mem_ctl.scala 437:73] + wire _T_1860 = byp_fetch_index_inc_1 == 4'h1; // @[el2_ifu_mem_ctl.scala 438:73] wire [15:0] _T_1906 = _T_1860 ? ic_miss_buff_data_1[15:0] : 16'h0; // @[Mux.scala 27:72] wire [15:0] _T_1921 = _T_1905 | _T_1906; // @[Mux.scala 27:72] - wire _T_1863 = byp_fetch_index_inc_1 == 4'h2; // @[el2_ifu_mem_ctl.scala 437:73] + wire _T_1863 = byp_fetch_index_inc_1 == 4'h2; // @[el2_ifu_mem_ctl.scala 438:73] wire [15:0] _T_1907 = _T_1863 ? ic_miss_buff_data_2[15:0] : 16'h0; // @[Mux.scala 27:72] wire [15:0] _T_1922 = _T_1921 | _T_1907; // @[Mux.scala 27:72] - wire _T_1866 = byp_fetch_index_inc_1 == 4'h3; // @[el2_ifu_mem_ctl.scala 437:73] + wire _T_1866 = byp_fetch_index_inc_1 == 4'h3; // @[el2_ifu_mem_ctl.scala 438:73] wire [15:0] _T_1908 = _T_1866 ? ic_miss_buff_data_3[15:0] : 16'h0; // @[Mux.scala 27:72] wire [15:0] _T_1923 = _T_1922 | _T_1908; // @[Mux.scala 27:72] - wire _T_1869 = byp_fetch_index_inc_1 == 4'h4; // @[el2_ifu_mem_ctl.scala 437:73] + wire _T_1869 = byp_fetch_index_inc_1 == 4'h4; // @[el2_ifu_mem_ctl.scala 438:73] wire [15:0] _T_1909 = _T_1869 ? ic_miss_buff_data_4[15:0] : 16'h0; // @[Mux.scala 27:72] wire [15:0] _T_1924 = _T_1923 | _T_1909; // @[Mux.scala 27:72] - wire _T_1872 = byp_fetch_index_inc_1 == 4'h5; // @[el2_ifu_mem_ctl.scala 437:73] + wire _T_1872 = byp_fetch_index_inc_1 == 4'h5; // @[el2_ifu_mem_ctl.scala 438:73] wire [15:0] _T_1910 = _T_1872 ? ic_miss_buff_data_5[15:0] : 16'h0; // @[Mux.scala 27:72] wire [15:0] _T_1925 = _T_1924 | _T_1910; // @[Mux.scala 27:72] - wire _T_1875 = byp_fetch_index_inc_1 == 4'h6; // @[el2_ifu_mem_ctl.scala 437:73] + wire _T_1875 = byp_fetch_index_inc_1 == 4'h6; // @[el2_ifu_mem_ctl.scala 438:73] wire [15:0] _T_1911 = _T_1875 ? ic_miss_buff_data_6[15:0] : 16'h0; // @[Mux.scala 27:72] wire [15:0] _T_1926 = _T_1925 | _T_1911; // @[Mux.scala 27:72] - wire _T_1878 = byp_fetch_index_inc_1 == 4'h7; // @[el2_ifu_mem_ctl.scala 437:73] + wire _T_1878 = byp_fetch_index_inc_1 == 4'h7; // @[el2_ifu_mem_ctl.scala 438:73] wire [15:0] _T_1912 = _T_1878 ? ic_miss_buff_data_7[15:0] : 16'h0; // @[Mux.scala 27:72] wire [15:0] _T_1927 = _T_1926 | _T_1912; // @[Mux.scala 27:72] - wire _T_1881 = byp_fetch_index_inc_1 == 4'h8; // @[el2_ifu_mem_ctl.scala 437:73] + wire _T_1881 = byp_fetch_index_inc_1 == 4'h8; // @[el2_ifu_mem_ctl.scala 438:73] wire [15:0] _T_1913 = _T_1881 ? ic_miss_buff_data_8[15:0] : 16'h0; // @[Mux.scala 27:72] wire [15:0] _T_1928 = _T_1927 | _T_1913; // @[Mux.scala 27:72] - wire _T_1884 = byp_fetch_index_inc_1 == 4'h9; // @[el2_ifu_mem_ctl.scala 437:73] + wire _T_1884 = byp_fetch_index_inc_1 == 4'h9; // @[el2_ifu_mem_ctl.scala 438:73] wire [15:0] _T_1914 = _T_1884 ? ic_miss_buff_data_9[15:0] : 16'h0; // @[Mux.scala 27:72] wire [15:0] _T_1929 = _T_1928 | _T_1914; // @[Mux.scala 27:72] - wire _T_1887 = byp_fetch_index_inc_1 == 4'ha; // @[el2_ifu_mem_ctl.scala 437:73] + wire _T_1887 = byp_fetch_index_inc_1 == 4'ha; // @[el2_ifu_mem_ctl.scala 438:73] wire [15:0] _T_1915 = _T_1887 ? ic_miss_buff_data_10[15:0] : 16'h0; // @[Mux.scala 27:72] wire [15:0] _T_1930 = _T_1929 | _T_1915; // @[Mux.scala 27:72] - wire _T_1890 = byp_fetch_index_inc_1 == 4'hb; // @[el2_ifu_mem_ctl.scala 437:73] + wire _T_1890 = byp_fetch_index_inc_1 == 4'hb; // @[el2_ifu_mem_ctl.scala 438:73] wire [15:0] _T_1916 = _T_1890 ? ic_miss_buff_data_11[15:0] : 16'h0; // @[Mux.scala 27:72] wire [15:0] _T_1931 = _T_1930 | _T_1916; // @[Mux.scala 27:72] - wire _T_1893 = byp_fetch_index_inc_1 == 4'hc; // @[el2_ifu_mem_ctl.scala 437:73] + wire _T_1893 = byp_fetch_index_inc_1 == 4'hc; // @[el2_ifu_mem_ctl.scala 438:73] wire [15:0] _T_1917 = _T_1893 ? ic_miss_buff_data_12[15:0] : 16'h0; // @[Mux.scala 27:72] wire [15:0] _T_1932 = _T_1931 | _T_1917; // @[Mux.scala 27:72] - wire _T_1896 = byp_fetch_index_inc_1 == 4'hd; // @[el2_ifu_mem_ctl.scala 437:73] + wire _T_1896 = byp_fetch_index_inc_1 == 4'hd; // @[el2_ifu_mem_ctl.scala 438:73] wire [15:0] _T_1918 = _T_1896 ? ic_miss_buff_data_13[15:0] : 16'h0; // @[Mux.scala 27:72] wire [15:0] _T_1933 = _T_1932 | _T_1918; // @[Mux.scala 27:72] - wire _T_1899 = byp_fetch_index_inc_1 == 4'he; // @[el2_ifu_mem_ctl.scala 437:73] + wire _T_1899 = byp_fetch_index_inc_1 == 4'he; // @[el2_ifu_mem_ctl.scala 438:73] wire [15:0] _T_1919 = _T_1899 ? ic_miss_buff_data_14[15:0] : 16'h0; // @[Mux.scala 27:72] wire [15:0] _T_1934 = _T_1933 | _T_1919; // @[Mux.scala 27:72] - wire _T_1902 = byp_fetch_index_inc_1 == 4'hf; // @[el2_ifu_mem_ctl.scala 437:73] + wire _T_1902 = byp_fetch_index_inc_1 == 4'hf; // @[el2_ifu_mem_ctl.scala 438:73] wire [15:0] _T_1920 = _T_1902 ? ic_miss_buff_data_15[15:0] : 16'h0; // @[Mux.scala 27:72] wire [15:0] _T_1935 = _T_1934 | _T_1920; // @[Mux.scala 27:72] wire [31:0] _T_1985 = _T_1615 ? ic_miss_buff_data_0 : 32'h0; // @[Mux.scala 27:72] @@ -3214,43 +3214,43 @@ module el2_ifu_mem_ctl( wire [31:0] _T_2000 = _T_1660 ? ic_miss_buff_data_15 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_2015 = _T_2014 | _T_2000; // @[Mux.scala 27:72] wire [79:0] _T_2098 = {_T_1935,_T_2015,_T_1773}; // @[Cat.scala 29:58] - wire [79:0] ic_byp_data_only_pre_new = _T_2101 ? _T_1856 : _T_2098; // @[el2_ifu_mem_ctl.scala 435:37] + wire [79:0] ic_byp_data_only_pre_new = _T_2101 ? _T_1856 : _T_2098; // @[el2_ifu_mem_ctl.scala 436:37] wire [79:0] _T_2103 = {16'h0,ic_byp_data_only_pre_new[79:16]}; // @[Cat.scala 29:58] - wire [79:0] ic_byp_data_only_new = _T_2101 ? ic_byp_data_only_pre_new : _T_2103; // @[el2_ifu_mem_ctl.scala 439:30] - wire [79:0] _GEN_793 = {{16'd0}, _T_1265}; // @[el2_ifu_mem_ctl.scala 370:109] - wire [79:0] _T_1266 = _GEN_793 & ic_byp_data_only_new; // @[el2_ifu_mem_ctl.scala 370:109] - wire [79:0] _GEN_794 = {{16'd0}, _T_1263}; // @[el2_ifu_mem_ctl.scala 370:83] - wire [79:0] ic_premux_data = _GEN_794 | _T_1266; // @[el2_ifu_mem_ctl.scala 370:83] - wire fetch_req_f_qual = io_ic_hit_f & _T_317; // @[el2_ifu_mem_ctl.scala 377:38] - wire [1:0] _T_1275 = ifc_region_acc_fault_f ? 2'h2 : 2'h0; // @[el2_ifu_mem_ctl.scala 381:8] + wire [79:0] ic_byp_data_only_new = _T_2101 ? ic_byp_data_only_pre_new : _T_2103; // @[el2_ifu_mem_ctl.scala 440:30] + wire [79:0] _GEN_793 = {{16'd0}, _T_1265}; // @[el2_ifu_mem_ctl.scala 371:109] + wire [79:0] _T_1266 = _GEN_793 & ic_byp_data_only_new; // @[el2_ifu_mem_ctl.scala 371:109] + wire [79:0] _GEN_794 = {{16'd0}, _T_1263}; // @[el2_ifu_mem_ctl.scala 371:83] + wire [79:0] ic_premux_data = _GEN_794 | _T_1266; // @[el2_ifu_mem_ctl.scala 371:83] + wire fetch_req_f_qual = io_ic_hit_f & _T_317; // @[el2_ifu_mem_ctl.scala 378:38] + wire [1:0] _T_1275 = ifc_region_acc_fault_f ? 2'h2 : 2'h0; // @[el2_ifu_mem_ctl.scala 382:8] wire [7:0] _T_1356 = {ic_miss_buff_data_valid_in_7,ic_miss_buff_data_valid_in_6,ic_miss_buff_data_valid_in_5,ic_miss_buff_data_valid_in_4,ic_miss_buff_data_valid_in_3,ic_miss_buff_data_valid_in_2,ic_miss_buff_data_valid_in_1,ic_miss_buff_data_valid_in_0}; // @[Cat.scala 29:58] - wire _T_1361 = ic_miss_buff_data_error[0] & _T_1327; // @[el2_ifu_mem_ctl.scala 402:32] - wire _T_2607 = |io_ifu_axi_rresp; // @[el2_ifu_mem_ctl.scala 613:47] - wire _T_2608 = _T_2607 & _T_13; // @[el2_ifu_mem_ctl.scala 613:50] - wire bus_ifu_wr_data_error = _T_2608 & miss_pending; // @[el2_ifu_mem_ctl.scala 613:68] - wire ic_miss_buff_data_error_in_0 = write_fill_data_0 ? bus_ifu_wr_data_error : _T_1361; // @[el2_ifu_mem_ctl.scala 401:72] - wire _T_1365 = ic_miss_buff_data_error[1] & _T_1327; // @[el2_ifu_mem_ctl.scala 402:32] - wire ic_miss_buff_data_error_in_1 = write_fill_data_1 ? bus_ifu_wr_data_error : _T_1365; // @[el2_ifu_mem_ctl.scala 401:72] - wire _T_1369 = ic_miss_buff_data_error[2] & _T_1327; // @[el2_ifu_mem_ctl.scala 402:32] - wire ic_miss_buff_data_error_in_2 = write_fill_data_2 ? bus_ifu_wr_data_error : _T_1369; // @[el2_ifu_mem_ctl.scala 401:72] - wire _T_1373 = ic_miss_buff_data_error[3] & _T_1327; // @[el2_ifu_mem_ctl.scala 402:32] - wire ic_miss_buff_data_error_in_3 = write_fill_data_3 ? bus_ifu_wr_data_error : _T_1373; // @[el2_ifu_mem_ctl.scala 401:72] - wire _T_1377 = ic_miss_buff_data_error[4] & _T_1327; // @[el2_ifu_mem_ctl.scala 402:32] - wire ic_miss_buff_data_error_in_4 = write_fill_data_4 ? bus_ifu_wr_data_error : _T_1377; // @[el2_ifu_mem_ctl.scala 401:72] - wire _T_1381 = ic_miss_buff_data_error[5] & _T_1327; // @[el2_ifu_mem_ctl.scala 402:32] - wire ic_miss_buff_data_error_in_5 = write_fill_data_5 ? bus_ifu_wr_data_error : _T_1381; // @[el2_ifu_mem_ctl.scala 401:72] - wire _T_1385 = ic_miss_buff_data_error[6] & _T_1327; // @[el2_ifu_mem_ctl.scala 402:32] - wire ic_miss_buff_data_error_in_6 = write_fill_data_6 ? bus_ifu_wr_data_error : _T_1385; // @[el2_ifu_mem_ctl.scala 401:72] - wire _T_1389 = ic_miss_buff_data_error[7] & _T_1327; // @[el2_ifu_mem_ctl.scala 402:32] - wire ic_miss_buff_data_error_in_7 = write_fill_data_7 ? bus_ifu_wr_data_error : _T_1389; // @[el2_ifu_mem_ctl.scala 401:72] + wire _T_1361 = ic_miss_buff_data_error[0] & _T_1327; // @[el2_ifu_mem_ctl.scala 403:32] + wire _T_2607 = |io_ifu_axi_rresp; // @[el2_ifu_mem_ctl.scala 614:47] + wire _T_2608 = _T_2607 & _T_13; // @[el2_ifu_mem_ctl.scala 614:50] + wire bus_ifu_wr_data_error = _T_2608 & miss_pending; // @[el2_ifu_mem_ctl.scala 614:68] + wire ic_miss_buff_data_error_in_0 = write_fill_data_0 ? bus_ifu_wr_data_error : _T_1361; // @[el2_ifu_mem_ctl.scala 402:72] + wire _T_1365 = ic_miss_buff_data_error[1] & _T_1327; // @[el2_ifu_mem_ctl.scala 403:32] + wire ic_miss_buff_data_error_in_1 = write_fill_data_1 ? bus_ifu_wr_data_error : _T_1365; // @[el2_ifu_mem_ctl.scala 402:72] + wire _T_1369 = ic_miss_buff_data_error[2] & _T_1327; // @[el2_ifu_mem_ctl.scala 403:32] + wire ic_miss_buff_data_error_in_2 = write_fill_data_2 ? bus_ifu_wr_data_error : _T_1369; // @[el2_ifu_mem_ctl.scala 402:72] + wire _T_1373 = ic_miss_buff_data_error[3] & _T_1327; // @[el2_ifu_mem_ctl.scala 403:32] + wire ic_miss_buff_data_error_in_3 = write_fill_data_3 ? bus_ifu_wr_data_error : _T_1373; // @[el2_ifu_mem_ctl.scala 402:72] + wire _T_1377 = ic_miss_buff_data_error[4] & _T_1327; // @[el2_ifu_mem_ctl.scala 403:32] + wire ic_miss_buff_data_error_in_4 = write_fill_data_4 ? bus_ifu_wr_data_error : _T_1377; // @[el2_ifu_mem_ctl.scala 402:72] + wire _T_1381 = ic_miss_buff_data_error[5] & _T_1327; // @[el2_ifu_mem_ctl.scala 403:32] + wire ic_miss_buff_data_error_in_5 = write_fill_data_5 ? bus_ifu_wr_data_error : _T_1381; // @[el2_ifu_mem_ctl.scala 402:72] + wire _T_1385 = ic_miss_buff_data_error[6] & _T_1327; // @[el2_ifu_mem_ctl.scala 403:32] + wire ic_miss_buff_data_error_in_6 = write_fill_data_6 ? bus_ifu_wr_data_error : _T_1385; // @[el2_ifu_mem_ctl.scala 402:72] + wire _T_1389 = ic_miss_buff_data_error[7] & _T_1327; // @[el2_ifu_mem_ctl.scala 403:32] + wire ic_miss_buff_data_error_in_7 = write_fill_data_7 ? bus_ifu_wr_data_error : _T_1389; // @[el2_ifu_mem_ctl.scala 402:72] wire [7:0] _T_1396 = {ic_miss_buff_data_error_in_7,ic_miss_buff_data_error_in_6,ic_miss_buff_data_error_in_5,ic_miss_buff_data_error_in_4,ic_miss_buff_data_error_in_3,ic_miss_buff_data_error_in_2,ic_miss_buff_data_error_in_1,ic_miss_buff_data_error_in_0}; // @[Cat.scala 29:58] reg [5:0] perr_ic_index_ff; // @[Reg.scala 27:20] wire _T_2413 = 3'h0 == perr_state; // @[Conditional.scala 37:30] - wire _T_2421 = _T_6 & _T_317; // @[el2_ifu_mem_ctl.scala 482:65] - wire _T_2422 = _T_2421 | io_iccm_dma_sb_error; // @[el2_ifu_mem_ctl.scala 482:88] - wire _T_2424 = _T_2422 & _T_2535; // @[el2_ifu_mem_ctl.scala 482:112] + wire _T_2421 = _T_6 & _T_317; // @[el2_ifu_mem_ctl.scala 483:65] + wire _T_2422 = _T_2421 | io_iccm_dma_sb_error; // @[el2_ifu_mem_ctl.scala 483:88] + wire _T_2424 = _T_2422 & _T_2535; // @[el2_ifu_mem_ctl.scala 483:112] wire _T_2425 = 3'h1 == perr_state; // @[Conditional.scala 37:30] - wire _T_2426 = io_dec_tlu_flush_lower_wb | io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 487:50] + wire _T_2426 = io_dec_tlu_flush_lower_wb | io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 488:50] wire _T_2428 = 3'h2 == perr_state; // @[Conditional.scala 37:30] wire _T_2434 = 3'h4 == perr_state; // @[Conditional.scala 37:30] wire _T_2436 = 3'h3 == perr_state; // @[Conditional.scala 37:30] @@ -3259,28 +3259,28 @@ module el2_ifu_mem_ctl( wire _GEN_42 = _T_2425 ? _T_2426 : _GEN_40; // @[Conditional.scala 39:67] wire perr_state_en = _T_2413 ? _T_2424 : _GEN_42; // @[Conditional.scala 40:58] wire perr_sb_write_status = _T_2413 & perr_state_en; // @[Conditional.scala 40:58] - wire _T_2427 = io_dec_tlu_flush_lower_wb & io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 488:56] + wire _T_2427 = io_dec_tlu_flush_lower_wb & io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 489:56] wire _GEN_43 = _T_2425 & _T_2427; // @[Conditional.scala 39:67] wire perr_sel_invalidate = _T_2413 ? 1'h0 : _GEN_43; // @[Conditional.scala 40:58] wire [1:0] perr_err_inv_way = perr_sel_invalidate ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - reg dma_sb_err_state_ff; // @[el2_ifu_mem_ctl.scala 473:58] - wire _T_2410 = ~dma_sb_err_state_ff; // @[el2_ifu_mem_ctl.scala 472:49] - wire _T_2415 = io_ic_error_start & _T_317; // @[el2_ifu_mem_ctl.scala 481:87] - wire _T_2429 = io_dec_tlu_flush_err_wb & io_dec_tlu_flush_lower_wb; // @[el2_ifu_mem_ctl.scala 491:54] - wire _T_2430 = _T_2429 | io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 491:84] - wire _T_2439 = perr_state == 3'h2; // @[el2_ifu_mem_ctl.scala 512:66] - wire _T_2440 = io_dec_tlu_flush_err_wb & _T_2439; // @[el2_ifu_mem_ctl.scala 512:52] - wire _T_2442 = _T_2440 & _T_2535; // @[el2_ifu_mem_ctl.scala 512:81] - wire _T_2444 = io_dec_tlu_flush_lower_wb | io_dec_tlu_i0_commit_cmt; // @[el2_ifu_mem_ctl.scala 515:59] - wire _T_2445 = _T_2444 | io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 515:86] - wire _T_2459 = _T_2444 | io_ifu_fetch_val[0]; // @[el2_ifu_mem_ctl.scala 518:81] - wire _T_2460 = _T_2459 | ifu_bp_hit_taken_q_f; // @[el2_ifu_mem_ctl.scala 518:103] - wire _T_2461 = _T_2460 | io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 518:126] - wire _T_2481 = _T_2459 | io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 525:103] - wire _T_2488 = ~io_dec_tlu_flush_err_wb; // @[el2_ifu_mem_ctl.scala 530:62] - wire _T_2489 = io_dec_tlu_flush_lower_wb & _T_2488; // @[el2_ifu_mem_ctl.scala 530:60] - wire _T_2490 = _T_2489 | io_dec_tlu_i0_commit_cmt; // @[el2_ifu_mem_ctl.scala 530:88] - wire _T_2491 = _T_2490 | io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 530:115] + reg dma_sb_err_state_ff; // @[el2_ifu_mem_ctl.scala 474:58] + wire _T_2410 = ~dma_sb_err_state_ff; // @[el2_ifu_mem_ctl.scala 473:49] + wire _T_2415 = io_ic_error_start & _T_317; // @[el2_ifu_mem_ctl.scala 482:87] + wire _T_2429 = io_dec_tlu_flush_err_wb & io_dec_tlu_flush_lower_wb; // @[el2_ifu_mem_ctl.scala 492:54] + wire _T_2430 = _T_2429 | io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 492:84] + wire _T_2439 = perr_state == 3'h2; // @[el2_ifu_mem_ctl.scala 513:66] + wire _T_2440 = io_dec_tlu_flush_err_wb & _T_2439; // @[el2_ifu_mem_ctl.scala 513:52] + wire _T_2442 = _T_2440 & _T_2535; // @[el2_ifu_mem_ctl.scala 513:81] + wire _T_2444 = io_dec_tlu_flush_lower_wb | io_dec_tlu_i0_commit_cmt; // @[el2_ifu_mem_ctl.scala 516:59] + wire _T_2445 = _T_2444 | io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 516:86] + wire _T_2459 = _T_2444 | io_ifu_fetch_val[0]; // @[el2_ifu_mem_ctl.scala 519:81] + wire _T_2460 = _T_2459 | ifu_bp_hit_taken_q_f; // @[el2_ifu_mem_ctl.scala 519:103] + wire _T_2461 = _T_2460 | io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 519:126] + wire _T_2481 = _T_2459 | io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 526:103] + wire _T_2488 = ~io_dec_tlu_flush_err_wb; // @[el2_ifu_mem_ctl.scala 531:62] + wire _T_2489 = io_dec_tlu_flush_lower_wb & _T_2488; // @[el2_ifu_mem_ctl.scala 531:60] + wire _T_2490 = _T_2489 | io_dec_tlu_i0_commit_cmt; // @[el2_ifu_mem_ctl.scala 531:88] + wire _T_2491 = _T_2490 | io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 531:115] wire _GEN_50 = _T_2487 & _T_2445; // @[Conditional.scala 39:67] wire _GEN_53 = _T_2470 ? _T_2481 : _GEN_50; // @[Conditional.scala 39:67] wire _GEN_55 = _T_2470 | _T_2487; // @[Conditional.scala 39:67] @@ -3288,65 +3288,65 @@ module el2_ifu_mem_ctl( wire _GEN_59 = _T_2443 | _GEN_55; // @[Conditional.scala 39:67] wire err_stop_state_en = _T_2438 ? _T_2442 : _GEN_57; // @[Conditional.scala 40:58] reg ifu_bus_cmd_valid; // @[Reg.scala 27:20] - wire _T_2503 = ic_act_miss_f | ifu_bus_cmd_valid; // @[el2_ifu_mem_ctl.scala 547:64] - wire _T_2505 = _T_2503 & _T_2535; // @[el2_ifu_mem_ctl.scala 547:85] + wire _T_2503 = ic_act_miss_f | ifu_bus_cmd_valid; // @[el2_ifu_mem_ctl.scala 548:64] + wire _T_2505 = _T_2503 & _T_2535; // @[el2_ifu_mem_ctl.scala 548:85] reg [2:0] bus_cmd_beat_count; // @[Reg.scala 27:20] - wire _T_2507 = bus_cmd_beat_count == 3'h7; // @[el2_ifu_mem_ctl.scala 547:133] - wire _T_2508 = _T_2507 & ifu_bus_cmd_valid; // @[el2_ifu_mem_ctl.scala 547:164] - wire _T_2509 = _T_2508 & io_ifu_axi_arready; // @[el2_ifu_mem_ctl.scala 547:184] - wire _T_2510 = _T_2509 & miss_pending; // @[el2_ifu_mem_ctl.scala 547:204] - wire _T_2511 = ~_T_2510; // @[el2_ifu_mem_ctl.scala 547:112] - wire ifc_bus_ic_req_ff_in = _T_2505 & _T_2511; // @[el2_ifu_mem_ctl.scala 547:110] - wire _T_2512 = io_ifu_bus_clk_en | io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 548:80] - wire ifu_bus_arready = io_ifu_axi_arready & io_ifu_bus_clk_en; // @[el2_ifu_mem_ctl.scala 579:45] - wire _T_2529 = io_ifu_axi_arvalid & ifu_bus_arready; // @[el2_ifu_mem_ctl.scala 582:35] - wire _T_2530 = _T_2529 & miss_pending; // @[el2_ifu_mem_ctl.scala 582:53] - wire bus_cmd_sent = _T_2530 & _T_2535; // @[el2_ifu_mem_ctl.scala 582:68] + wire _T_2507 = bus_cmd_beat_count == 3'h7; // @[el2_ifu_mem_ctl.scala 548:133] + wire _T_2508 = _T_2507 & ifu_bus_cmd_valid; // @[el2_ifu_mem_ctl.scala 548:164] + wire _T_2509 = _T_2508 & io_ifu_axi_arready; // @[el2_ifu_mem_ctl.scala 548:184] + wire _T_2510 = _T_2509 & miss_pending; // @[el2_ifu_mem_ctl.scala 548:204] + wire _T_2511 = ~_T_2510; // @[el2_ifu_mem_ctl.scala 548:112] + wire ifc_bus_ic_req_ff_in = _T_2505 & _T_2511; // @[el2_ifu_mem_ctl.scala 548:110] + wire _T_2512 = io_ifu_bus_clk_en | io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 549:80] + wire ifu_bus_arready = io_ifu_axi_arready & io_ifu_bus_clk_en; // @[el2_ifu_mem_ctl.scala 580:45] + wire _T_2529 = io_ifu_axi_arvalid & ifu_bus_arready; // @[el2_ifu_mem_ctl.scala 583:35] + wire _T_2530 = _T_2529 & miss_pending; // @[el2_ifu_mem_ctl.scala 583:53] + wire bus_cmd_sent = _T_2530 & _T_2535; // @[el2_ifu_mem_ctl.scala 583:68] wire [2:0] _T_2520 = ifu_bus_cmd_valid ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] wire [31:0] _T_2522 = {miss_addr,bus_rd_addr_count,3'h0}; // @[Cat.scala 29:58] wire [31:0] _T_2524 = ifu_bus_cmd_valid ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] reg ifu_bus_arready_unq_ff; // @[Reg.scala 27:20] reg ifu_bus_arvalid_ff; // @[Reg.scala 27:20] - wire ifu_bus_arready_ff = ifu_bus_arready_unq_ff & bus_ifu_bus_clk_en_ff; // @[el2_ifu_mem_ctl.scala 580:51] - wire _T_2550 = ~scnd_miss_req; // @[el2_ifu_mem_ctl.scala 590:73] - wire _T_2551 = _T_2536 & _T_2550; // @[el2_ifu_mem_ctl.scala 590:71] - wire _T_2553 = last_data_recieved_ff & _T_1327; // @[el2_ifu_mem_ctl.scala 590:114] - wire last_data_recieved_in = _T_2551 | _T_2553; // @[el2_ifu_mem_ctl.scala 590:89] - wire [2:0] _T_2559 = bus_rd_addr_count + 3'h1; // @[el2_ifu_mem_ctl.scala 595:45] - wire _T_2562 = io_ifu_bus_clk_en | ic_act_miss_f; // @[el2_ifu_mem_ctl.scala 596:81] - wire _T_2563 = _T_2562 | io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 596:97] - wire _T_2565 = ifu_bus_cmd_valid & io_ifu_axi_arready; // @[el2_ifu_mem_ctl.scala 598:48] - wire _T_2566 = _T_2565 & miss_pending; // @[el2_ifu_mem_ctl.scala 598:68] - wire bus_inc_cmd_beat_cnt = _T_2566 & _T_2535; // @[el2_ifu_mem_ctl.scala 598:83] - wire bus_reset_cmd_beat_cnt_secondlast = ic_act_miss_f & uncacheable_miss_in; // @[el2_ifu_mem_ctl.scala 600:57] - wire _T_2570 = ~bus_inc_cmd_beat_cnt; // @[el2_ifu_mem_ctl.scala 601:31] - wire _T_2571 = ic_act_miss_f | scnd_miss_req; // @[el2_ifu_mem_ctl.scala 601:71] - wire _T_2572 = _T_2571 | io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 601:87] - wire _T_2573 = ~_T_2572; // @[el2_ifu_mem_ctl.scala 601:55] - wire bus_hold_cmd_beat_cnt = _T_2570 & _T_2573; // @[el2_ifu_mem_ctl.scala 601:53] - wire _T_2574 = bus_inc_cmd_beat_cnt | ic_act_miss_f; // @[el2_ifu_mem_ctl.scala 602:46] - wire bus_cmd_beat_en = _T_2574 | io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 602:62] - wire [2:0] _T_2577 = bus_cmd_beat_count + 3'h1; // @[el2_ifu_mem_ctl.scala 604:46] + wire ifu_bus_arready_ff = ifu_bus_arready_unq_ff & bus_ifu_bus_clk_en_ff; // @[el2_ifu_mem_ctl.scala 581:51] + wire _T_2550 = ~scnd_miss_req; // @[el2_ifu_mem_ctl.scala 591:73] + wire _T_2551 = _T_2536 & _T_2550; // @[el2_ifu_mem_ctl.scala 591:71] + wire _T_2553 = last_data_recieved_ff & _T_1327; // @[el2_ifu_mem_ctl.scala 591:114] + wire last_data_recieved_in = _T_2551 | _T_2553; // @[el2_ifu_mem_ctl.scala 591:89] + wire [2:0] _T_2559 = bus_rd_addr_count + 3'h1; // @[el2_ifu_mem_ctl.scala 596:45] + wire _T_2562 = io_ifu_bus_clk_en | ic_act_miss_f; // @[el2_ifu_mem_ctl.scala 597:81] + wire _T_2563 = _T_2562 | io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 597:97] + wire _T_2565 = ifu_bus_cmd_valid & io_ifu_axi_arready; // @[el2_ifu_mem_ctl.scala 599:48] + wire _T_2566 = _T_2565 & miss_pending; // @[el2_ifu_mem_ctl.scala 599:68] + wire bus_inc_cmd_beat_cnt = _T_2566 & _T_2535; // @[el2_ifu_mem_ctl.scala 599:83] + wire bus_reset_cmd_beat_cnt_secondlast = ic_act_miss_f & uncacheable_miss_in; // @[el2_ifu_mem_ctl.scala 601:57] + wire _T_2570 = ~bus_inc_cmd_beat_cnt; // @[el2_ifu_mem_ctl.scala 602:31] + wire _T_2571 = ic_act_miss_f | scnd_miss_req; // @[el2_ifu_mem_ctl.scala 602:71] + wire _T_2572 = _T_2571 | io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 602:87] + wire _T_2573 = ~_T_2572; // @[el2_ifu_mem_ctl.scala 602:55] + wire bus_hold_cmd_beat_cnt = _T_2570 & _T_2573; // @[el2_ifu_mem_ctl.scala 602:53] + wire _T_2574 = bus_inc_cmd_beat_cnt | ic_act_miss_f; // @[el2_ifu_mem_ctl.scala 603:46] + wire bus_cmd_beat_en = _T_2574 | io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 603:62] + wire [2:0] _T_2577 = bus_cmd_beat_count + 3'h1; // @[el2_ifu_mem_ctl.scala 605:46] wire [2:0] _T_2579 = bus_reset_cmd_beat_cnt_secondlast ? 3'h6 : 3'h0; // @[Mux.scala 27:72] wire [2:0] _T_2580 = bus_inc_cmd_beat_cnt ? _T_2577 : 3'h0; // @[Mux.scala 27:72] wire [2:0] _T_2581 = bus_hold_cmd_beat_cnt ? bus_cmd_beat_count : 3'h0; // @[Mux.scala 27:72] wire [2:0] _T_2583 = _T_2579 | _T_2580; // @[Mux.scala 27:72] wire [2:0] bus_new_cmd_beat_count = _T_2583 | _T_2581; // @[Mux.scala 27:72] - wire _T_2587 = _T_2563 & bus_cmd_beat_en; // @[el2_ifu_mem_ctl.scala 605:125] - reg ifc_dma_access_ok_prev; // @[el2_ifu_mem_ctl.scala 616:62] - wire _T_2615 = ~iccm_correct_ecc; // @[el2_ifu_mem_ctl.scala 621:50] - wire _T_2616 = io_ifc_dma_access_ok & _T_2615; // @[el2_ifu_mem_ctl.scala 621:47] - wire _T_2617 = ~io_iccm_dma_sb_error; // @[el2_ifu_mem_ctl.scala 621:70] - wire ifc_dma_access_ok_d = _T_2616 & _T_2617; // @[el2_ifu_mem_ctl.scala 621:68] - wire _T_2621 = _T_2616 & ifc_dma_access_ok_prev; // @[el2_ifu_mem_ctl.scala 622:72] - wire _T_2622 = perr_state == 3'h0; // @[el2_ifu_mem_ctl.scala 622:111] - wire _T_2623 = _T_2621 & _T_2622; // @[el2_ifu_mem_ctl.scala 622:97] - wire ifc_dma_access_q_ok = _T_2623 & _T_2617; // @[el2_ifu_mem_ctl.scala 622:127] - wire _T_2626 = ifc_dma_access_q_ok & io_dma_iccm_req; // @[el2_ifu_mem_ctl.scala 625:40] - wire _T_2627 = _T_2626 & io_dma_mem_write; // @[el2_ifu_mem_ctl.scala 625:58] - wire _T_2630 = ~io_dma_mem_write; // @[el2_ifu_mem_ctl.scala 626:60] - wire _T_2631 = _T_2626 & _T_2630; // @[el2_ifu_mem_ctl.scala 626:58] - wire _T_2632 = io_ifc_iccm_access_bf & io_ifc_fetch_req_bf; // @[el2_ifu_mem_ctl.scala 626:104] + wire _T_2587 = _T_2563 & bus_cmd_beat_en; // @[el2_ifu_mem_ctl.scala 606:125] + reg ifc_dma_access_ok_prev; // @[el2_ifu_mem_ctl.scala 617:62] + wire _T_2615 = ~iccm_correct_ecc; // @[el2_ifu_mem_ctl.scala 622:50] + wire _T_2616 = io_ifc_dma_access_ok & _T_2615; // @[el2_ifu_mem_ctl.scala 622:47] + wire _T_2617 = ~io_iccm_dma_sb_error; // @[el2_ifu_mem_ctl.scala 622:70] + wire ifc_dma_access_ok_d = _T_2616 & _T_2617; // @[el2_ifu_mem_ctl.scala 622:68] + wire _T_2621 = _T_2616 & ifc_dma_access_ok_prev; // @[el2_ifu_mem_ctl.scala 623:72] + wire _T_2622 = perr_state == 3'h0; // @[el2_ifu_mem_ctl.scala 623:111] + wire _T_2623 = _T_2621 & _T_2622; // @[el2_ifu_mem_ctl.scala 623:97] + wire ifc_dma_access_q_ok = _T_2623 & _T_2617; // @[el2_ifu_mem_ctl.scala 623:127] + wire _T_2626 = ifc_dma_access_q_ok & io_dma_iccm_req; // @[el2_ifu_mem_ctl.scala 626:40] + wire _T_2627 = _T_2626 & io_dma_mem_write; // @[el2_ifu_mem_ctl.scala 626:58] + wire _T_2630 = ~io_dma_mem_write; // @[el2_ifu_mem_ctl.scala 627:60] + wire _T_2631 = _T_2626 & _T_2630; // @[el2_ifu_mem_ctl.scala 627:58] + wire _T_2632 = io_ifc_iccm_access_bf & io_ifc_fetch_req_bf; // @[el2_ifu_mem_ctl.scala 627:104] wire [2:0] _T_2637 = io_dma_iccm_req ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] wire [8:0] _T_2743 = {io_dma_mem_wdata[48],io_dma_mem_wdata[46],io_dma_mem_wdata[44],io_dma_mem_wdata[42],io_dma_mem_wdata[40],io_dma_mem_wdata[38],io_dma_mem_wdata[37],io_dma_mem_wdata[35],io_dma_mem_wdata[33]}; // @[el2_lib.scala 268:22] wire [17:0] _T_2752 = {io_dma_mem_wdata[63],io_dma_mem_wdata[62],io_dma_mem_wdata[60],io_dma_mem_wdata[59],io_dma_mem_wdata[57],io_dma_mem_wdata[55],io_dma_mem_wdata[53],io_dma_mem_wdata[52],io_dma_mem_wdata[50],_T_2743}; // @[el2_lib.scala 268:22] @@ -3390,12 +3390,12 @@ module el2_ifu_mem_ctl( wire _T_3029 = _T_3027 ^ _T_3028; // @[el2_lib.scala 269:18] wire [6:0] _T_3030 = {_T_3029,_T_2949,_T_2967,_T_2985,_T_3000,_T_3015,_T_3021}; // @[Cat.scala 29:58] wire [13:0] dma_mem_ecc = {_T_2833,_T_2753,_T_2771,_T_2789,_T_2804,_T_2819,_T_2825,_T_3030}; // @[Cat.scala 29:58] - wire _T_3032 = ~_T_2626; // @[el2_ifu_mem_ctl.scala 631:45] - wire _T_3033 = iccm_correct_ecc & _T_3032; // @[el2_ifu_mem_ctl.scala 631:43] + wire _T_3032 = ~_T_2626; // @[el2_ifu_mem_ctl.scala 632:45] + wire _T_3033 = iccm_correct_ecc & _T_3032; // @[el2_ifu_mem_ctl.scala 632:43] reg [38:0] iccm_ecc_corr_data_ff; // @[Reg.scala 27:20] wire [77:0] _T_3034 = {iccm_ecc_corr_data_ff,iccm_ecc_corr_data_ff}; // @[Cat.scala 29:58] wire [77:0] _T_3041 = {dma_mem_ecc[13:7],io_dma_mem_wdata[63:32],dma_mem_ecc[6:0],io_dma_mem_wdata[31:0]}; // @[Cat.scala 29:58] - reg [1:0] dma_mem_addr_ff; // @[el2_ifu_mem_ctl.scala 645:53] + reg [1:0] dma_mem_addr_ff; // @[el2_ifu_mem_ctl.scala 646:53] wire _T_3373 = _T_3285[5:0] == 6'h27; // @[el2_lib.scala 307:41] wire _T_3371 = _T_3285[5:0] == 6'h26; // @[el2_lib.scala 307:41] wire _T_3369 = _T_3285[5:0] == 6'h25; // @[el2_lib.scala 307:41] @@ -3494,1494 +3494,1494 @@ module el2_ifu_mem_ctl( wire [38:0] _T_3819 = _T_3818 ^ _T_3779; // @[el2_lib.scala 310:76] wire [38:0] _T_3820 = _T_3674 ? _T_3819 : _T_3779; // @[el2_lib.scala 310:31] wire [31:0] iccm_corrected_data_1 = {_T_3820[37:32],_T_3820[30:16],_T_3820[14:8],_T_3820[6:4],_T_3820[2]}; // @[Cat.scala 29:58] - wire [31:0] iccm_dma_rdata_1_muxed = dma_mem_addr_ff[0] ? iccm_corrected_data_0 : iccm_corrected_data_1; // @[el2_ifu_mem_ctl.scala 637:35] + wire [31:0] iccm_dma_rdata_1_muxed = dma_mem_addr_ff[0] ? iccm_corrected_data_0 : iccm_corrected_data_1; // @[el2_ifu_mem_ctl.scala 638:35] wire _T_3293 = ~_T_3285[6]; // @[el2_lib.scala 303:55] wire _T_3294 = _T_3287 & _T_3293; // @[el2_lib.scala 303:53] wire _T_3678 = ~_T_3670[6]; // @[el2_lib.scala 303:55] wire _T_3679 = _T_3672 & _T_3678; // @[el2_lib.scala 303:53] wire [1:0] iccm_double_ecc_error = {_T_3294,_T_3679}; // @[Cat.scala 29:58] - wire iccm_dma_ecc_error_in = |iccm_double_ecc_error; // @[el2_ifu_mem_ctl.scala 639:53] + wire iccm_dma_ecc_error_in = |iccm_double_ecc_error; // @[el2_ifu_mem_ctl.scala 640:53] wire [63:0] _T_3045 = {io_dma_mem_addr,io_dma_mem_addr}; // @[Cat.scala 29:58] wire [63:0] _T_3046 = {iccm_dma_rdata_1_muxed,_T_3435[37:32],_T_3435[30:16],_T_3435[14:8],_T_3435[6:4],_T_3435[2]}; // @[Cat.scala 29:58] - reg [2:0] dma_mem_tag_ff; // @[el2_ifu_mem_ctl.scala 641:54] - reg [2:0] iccm_dma_rtag; // @[el2_ifu_mem_ctl.scala 642:69] - reg iccm_dma_rvalid; // @[el2_ifu_mem_ctl.scala 647:71] - reg [63:0] iccm_dma_rdata; // @[el2_ifu_mem_ctl.scala 651:70] - wire _T_3051 = _T_2626 & _T_2615; // @[el2_ifu_mem_ctl.scala 654:65] - wire _T_3054 = _T_3032 & iccm_correct_ecc; // @[el2_ifu_mem_ctl.scala 655:50] + reg [2:0] dma_mem_tag_ff; // @[el2_ifu_mem_ctl.scala 642:54] + reg [2:0] iccm_dma_rtag; // @[el2_ifu_mem_ctl.scala 643:69] + reg iccm_dma_rvalid; // @[el2_ifu_mem_ctl.scala 648:71] + reg [63:0] iccm_dma_rdata; // @[el2_ifu_mem_ctl.scala 652:70] + wire _T_3051 = _T_2626 & _T_2615; // @[el2_ifu_mem_ctl.scala 655:65] + wire _T_3054 = _T_3032 & iccm_correct_ecc; // @[el2_ifu_mem_ctl.scala 656:50] reg [13:0] iccm_ecc_corr_index_ff; // @[Reg.scala 27:20] wire [14:0] _T_3055 = {iccm_ecc_corr_index_ff,1'h0}; // @[Cat.scala 29:58] - wire [15:0] _T_3057 = _T_3054 ? {{1'd0}, _T_3055} : io_ifc_fetch_addr_bf[15:0]; // @[el2_ifu_mem_ctl.scala 655:8] - wire [31:0] _T_3058 = _T_3051 ? io_dma_mem_addr : {{16'd0}, _T_3057}; // @[el2_ifu_mem_ctl.scala 654:25] + wire [15:0] _T_3057 = _T_3054 ? {{1'd0}, _T_3055} : io_ifc_fetch_addr_bf[15:0]; // @[el2_ifu_mem_ctl.scala 656:8] + wire [31:0] _T_3058 = _T_3051 ? io_dma_mem_addr : {{16'd0}, _T_3057}; // @[el2_ifu_mem_ctl.scala 655:25] wire _T_3447 = _T_3285 == 7'h40; // @[el2_lib.scala 313:62] wire _T_3448 = _T_3435[38] ^ _T_3447; // @[el2_lib.scala 313:44] wire [6:0] iccm_corrected_ecc_0 = {_T_3448,_T_3435[31],_T_3435[15],_T_3435[7],_T_3435[3],_T_3435[1:0]}; // @[Cat.scala 29:58] wire _T_3832 = _T_3670 == 7'h40; // @[el2_lib.scala 313:62] wire _T_3833 = _T_3820[38] ^ _T_3832; // @[el2_lib.scala 313:44] wire [6:0] iccm_corrected_ecc_1 = {_T_3833,_T_3820[31],_T_3820[15],_T_3820[7],_T_3820[3],_T_3820[1:0]}; // @[Cat.scala 29:58] - wire _T_3849 = _T_3 & ifc_iccm_access_f; // @[el2_ifu_mem_ctl.scala 667:58] - wire [31:0] iccm_corrected_data_f_mux = iccm_single_ecc_error[0] ? iccm_corrected_data_0 : iccm_corrected_data_1; // @[el2_ifu_mem_ctl.scala 669:38] - wire [6:0] iccm_corrected_ecc_f_mux = iccm_single_ecc_error[0] ? iccm_corrected_ecc_0 : iccm_corrected_ecc_1; // @[el2_ifu_mem_ctl.scala 670:37] - reg iccm_rd_ecc_single_err_ff; // @[el2_ifu_mem_ctl.scala 678:62] - wire _T_3857 = ~iccm_rd_ecc_single_err_ff; // @[el2_ifu_mem_ctl.scala 672:76] - wire _T_3858 = io_iccm_rd_ecc_single_err & _T_3857; // @[el2_ifu_mem_ctl.scala 672:74] - wire _T_3860 = _T_3858 & _T_317; // @[el2_ifu_mem_ctl.scala 672:104] - wire iccm_ecc_write_status = _T_3860 | io_iccm_dma_sb_error; // @[el2_ifu_mem_ctl.scala 672:127] - wire _T_3861 = io_iccm_rd_ecc_single_err | iccm_rd_ecc_single_err_ff; // @[el2_ifu_mem_ctl.scala 673:67] - wire iccm_rd_ecc_single_err_hold_in = _T_3861 & _T_317; // @[el2_ifu_mem_ctl.scala 673:96] - reg [13:0] iccm_rw_addr_f; // @[el2_ifu_mem_ctl.scala 677:51] - wire [13:0] _T_3866 = iccm_rw_addr_f + 14'h1; // @[el2_ifu_mem_ctl.scala 676:102] + wire _T_3849 = _T_3 & ifc_iccm_access_f; // @[el2_ifu_mem_ctl.scala 668:58] + wire [31:0] iccm_corrected_data_f_mux = iccm_single_ecc_error[0] ? iccm_corrected_data_0 : iccm_corrected_data_1; // @[el2_ifu_mem_ctl.scala 670:38] + wire [6:0] iccm_corrected_ecc_f_mux = iccm_single_ecc_error[0] ? iccm_corrected_ecc_0 : iccm_corrected_ecc_1; // @[el2_ifu_mem_ctl.scala 671:37] + reg iccm_rd_ecc_single_err_ff; // @[el2_ifu_mem_ctl.scala 679:62] + wire _T_3857 = ~iccm_rd_ecc_single_err_ff; // @[el2_ifu_mem_ctl.scala 673:76] + wire _T_3858 = io_iccm_rd_ecc_single_err & _T_3857; // @[el2_ifu_mem_ctl.scala 673:74] + wire _T_3860 = _T_3858 & _T_317; // @[el2_ifu_mem_ctl.scala 673:104] + wire iccm_ecc_write_status = _T_3860 | io_iccm_dma_sb_error; // @[el2_ifu_mem_ctl.scala 673:127] + wire _T_3861 = io_iccm_rd_ecc_single_err | iccm_rd_ecc_single_err_ff; // @[el2_ifu_mem_ctl.scala 674:67] + wire iccm_rd_ecc_single_err_hold_in = _T_3861 & _T_317; // @[el2_ifu_mem_ctl.scala 674:96] + reg [13:0] iccm_rw_addr_f; // @[el2_ifu_mem_ctl.scala 678:51] + wire [13:0] _T_3866 = iccm_rw_addr_f + 14'h1; // @[el2_ifu_mem_ctl.scala 677:102] wire [38:0] _T_3870 = {iccm_corrected_ecc_f_mux,iccm_corrected_data_f_mux}; // @[Cat.scala 29:58] - wire _T_3875 = ~io_ifc_fetch_uncacheable_bf; // @[el2_ifu_mem_ctl.scala 681:41] - wire _T_3876 = io_ifc_fetch_req_bf & _T_3875; // @[el2_ifu_mem_ctl.scala 681:39] - wire _T_3877 = ~io_ifc_iccm_access_bf; // @[el2_ifu_mem_ctl.scala 681:72] - wire _T_3878 = _T_3876 & _T_3877; // @[el2_ifu_mem_ctl.scala 681:70] - wire _T_3880 = ~miss_state_en; // @[el2_ifu_mem_ctl.scala 682:34] - wire _T_3881 = _T_2221 & _T_3880; // @[el2_ifu_mem_ctl.scala 682:32] - wire _T_3884 = _T_2237 & _T_3880; // @[el2_ifu_mem_ctl.scala 683:37] - wire _T_3885 = _T_3881 | _T_3884; // @[el2_ifu_mem_ctl.scala 682:88] - wire _T_3886 = miss_state == 3'h7; // @[el2_ifu_mem_ctl.scala 684:19] - wire _T_3888 = _T_3886 & _T_3880; // @[el2_ifu_mem_ctl.scala 684:41] - wire _T_3889 = _T_3885 | _T_3888; // @[el2_ifu_mem_ctl.scala 683:88] - wire _T_3890 = miss_state == 3'h3; // @[el2_ifu_mem_ctl.scala 685:19] - wire _T_3892 = _T_3890 & _T_3880; // @[el2_ifu_mem_ctl.scala 685:35] - wire _T_3893 = _T_3889 | _T_3892; // @[el2_ifu_mem_ctl.scala 684:88] - wire _T_3896 = _T_2236 & _T_3880; // @[el2_ifu_mem_ctl.scala 686:38] - wire _T_3897 = _T_3893 | _T_3896; // @[el2_ifu_mem_ctl.scala 685:88] - wire _T_3899 = _T_2237 & miss_state_en; // @[el2_ifu_mem_ctl.scala 687:37] - wire _T_3900 = miss_nxtstate == 3'h3; // @[el2_ifu_mem_ctl.scala 687:71] - wire _T_3901 = _T_3899 & _T_3900; // @[el2_ifu_mem_ctl.scala 687:54] - wire _T_3902 = _T_3897 | _T_3901; // @[el2_ifu_mem_ctl.scala 686:57] - wire _T_3903 = ~_T_3902; // @[el2_ifu_mem_ctl.scala 682:5] - wire _T_3904 = _T_3878 & _T_3903; // @[el2_ifu_mem_ctl.scala 681:96] - wire _T_3905 = io_ifc_fetch_req_bf & io_exu_flush_final; // @[el2_ifu_mem_ctl.scala 688:28] - wire _T_3907 = _T_3905 & _T_3875; // @[el2_ifu_mem_ctl.scala 688:50] - wire _T_3909 = _T_3907 & _T_3877; // @[el2_ifu_mem_ctl.scala 688:81] - wire _T_3918 = ~_T_108; // @[el2_ifu_mem_ctl.scala 691:106] - wire _T_3919 = _T_2221 & _T_3918; // @[el2_ifu_mem_ctl.scala 691:104] - wire _T_3920 = _T_2237 | _T_3919; // @[el2_ifu_mem_ctl.scala 691:77] - wire _T_3924 = ~_T_51; // @[el2_ifu_mem_ctl.scala 691:172] - wire _T_3925 = _T_3920 & _T_3924; // @[el2_ifu_mem_ctl.scala 691:170] - wire _T_3926 = ~_T_3925; // @[el2_ifu_mem_ctl.scala 691:44] - wire _T_3930 = reset_ic_in | reset_ic_ff; // @[el2_ifu_mem_ctl.scala 694:64] - wire _T_3931 = ~_T_3930; // @[el2_ifu_mem_ctl.scala 694:50] - wire _T_3932 = _T_276 & _T_3931; // @[el2_ifu_mem_ctl.scala 694:48] - wire _T_3933 = ~reset_tag_valid_for_miss; // @[el2_ifu_mem_ctl.scala 694:81] - wire ic_valid = _T_3932 & _T_3933; // @[el2_ifu_mem_ctl.scala 694:79] - wire _T_3935 = debug_c1_clken & io_ic_debug_tag_array; // @[el2_ifu_mem_ctl.scala 695:82] - reg [6:0] ifu_status_wr_addr_ff; // @[el2_ifu_mem_ctl.scala 698:14] - wire _T_3938 = io_ic_debug_wr_en & io_ic_debug_tag_array; // @[el2_ifu_mem_ctl.scala 701:74] - wire _T_10080 = bus_ifu_wr_en_ff_q & last_beat; // @[el2_ifu_mem_ctl.scala 775:45] - wire way_status_wr_en = _T_10080 | ic_act_hit_f; // @[el2_ifu_mem_ctl.scala 775:58] - wire way_status_wr_en_w_debug = way_status_wr_en | _T_3938; // @[el2_ifu_mem_ctl.scala 701:53] - reg way_status_wr_en_ff; // @[el2_ifu_mem_ctl.scala 703:14] - wire [2:0] _T_3942 = {{2'd0}, io_ic_debug_wr_data[4]}; // @[el2_ifu_mem_ctl.scala 707:10] - wire way_status_hit_new = io_ic_rd_hit[0]; // @[el2_ifu_mem_ctl.scala 771:41] - wire way_status_new = _T_10080 ? replace_way_mb_any_0 : way_status_hit_new; // @[el2_ifu_mem_ctl.scala 774:26] - reg [2:0] way_status_new_ff; // @[el2_ifu_mem_ctl.scala 709:14] - wire way_status_clken_0 = ifu_status_wr_addr_ff[6:3] == 4'h0; // @[el2_ifu_mem_ctl.scala 711:132] - wire way_status_clken_1 = ifu_status_wr_addr_ff[6:3] == 4'h1; // @[el2_ifu_mem_ctl.scala 711:132] - wire way_status_clken_2 = ifu_status_wr_addr_ff[6:3] == 4'h2; // @[el2_ifu_mem_ctl.scala 711:132] - wire way_status_clken_3 = ifu_status_wr_addr_ff[6:3] == 4'h3; // @[el2_ifu_mem_ctl.scala 711:132] - wire way_status_clken_4 = ifu_status_wr_addr_ff[6:3] == 4'h4; // @[el2_ifu_mem_ctl.scala 711:132] - wire way_status_clken_5 = ifu_status_wr_addr_ff[6:3] == 4'h5; // @[el2_ifu_mem_ctl.scala 711:132] - wire way_status_clken_6 = ifu_status_wr_addr_ff[6:3] == 4'h6; // @[el2_ifu_mem_ctl.scala 711:132] - wire way_status_clken_7 = ifu_status_wr_addr_ff[6:3] == 4'h7; // @[el2_ifu_mem_ctl.scala 711:132] - wire way_status_clken_8 = ifu_status_wr_addr_ff[6:3] == 4'h8; // @[el2_ifu_mem_ctl.scala 711:132] - wire way_status_clken_9 = ifu_status_wr_addr_ff[6:3] == 4'h9; // @[el2_ifu_mem_ctl.scala 711:132] - wire way_status_clken_10 = ifu_status_wr_addr_ff[6:3] == 4'ha; // @[el2_ifu_mem_ctl.scala 711:132] - wire way_status_clken_11 = ifu_status_wr_addr_ff[6:3] == 4'hb; // @[el2_ifu_mem_ctl.scala 711:132] - wire way_status_clken_12 = ifu_status_wr_addr_ff[6:3] == 4'hc; // @[el2_ifu_mem_ctl.scala 711:132] - wire way_status_clken_13 = ifu_status_wr_addr_ff[6:3] == 4'hd; // @[el2_ifu_mem_ctl.scala 711:132] - wire way_status_clken_14 = ifu_status_wr_addr_ff[6:3] == 4'he; // @[el2_ifu_mem_ctl.scala 711:132] - wire way_status_clken_15 = ifu_status_wr_addr_ff[6:3] == 4'hf; // @[el2_ifu_mem_ctl.scala 711:132] - wire _T_3959 = ifu_status_wr_addr_ff == 7'h0; // @[el2_ifu_mem_ctl.scala 715:93] - wire _T_3960 = _T_3959 & way_status_wr_en_ff; // @[el2_ifu_mem_ctl.scala 715:102] - wire _T_3961 = _T_3960 & way_status_clken_0; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_3963 = ifu_status_wr_addr_ff == 7'h1; // @[el2_ifu_mem_ctl.scala 715:93] - wire _T_3964 = _T_3963 & way_status_wr_en_ff; // @[el2_ifu_mem_ctl.scala 715:102] - wire _T_3965 = _T_3964 & way_status_clken_0; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_3967 = ifu_status_wr_addr_ff == 7'h2; // @[el2_ifu_mem_ctl.scala 715:93] - wire _T_3968 = _T_3967 & way_status_wr_en_ff; // @[el2_ifu_mem_ctl.scala 715:102] - wire _T_3969 = _T_3968 & way_status_clken_0; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_3971 = ifu_status_wr_addr_ff == 7'h3; // @[el2_ifu_mem_ctl.scala 715:93] - wire _T_3972 = _T_3971 & way_status_wr_en_ff; // @[el2_ifu_mem_ctl.scala 715:102] - wire _T_3973 = _T_3972 & way_status_clken_0; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_3975 = ifu_status_wr_addr_ff == 7'h4; // @[el2_ifu_mem_ctl.scala 715:93] - wire _T_3976 = _T_3975 & way_status_wr_en_ff; // @[el2_ifu_mem_ctl.scala 715:102] - wire _T_3977 = _T_3976 & way_status_clken_0; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_3979 = ifu_status_wr_addr_ff == 7'h5; // @[el2_ifu_mem_ctl.scala 715:93] - wire _T_3980 = _T_3979 & way_status_wr_en_ff; // @[el2_ifu_mem_ctl.scala 715:102] - wire _T_3981 = _T_3980 & way_status_clken_0; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_3983 = ifu_status_wr_addr_ff == 7'h6; // @[el2_ifu_mem_ctl.scala 715:93] - wire _T_3984 = _T_3983 & way_status_wr_en_ff; // @[el2_ifu_mem_ctl.scala 715:102] - wire _T_3985 = _T_3984 & way_status_clken_0; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_3987 = ifu_status_wr_addr_ff == 7'h7; // @[el2_ifu_mem_ctl.scala 715:93] - wire _T_3988 = _T_3987 & way_status_wr_en_ff; // @[el2_ifu_mem_ctl.scala 715:102] - wire _T_3989 = _T_3988 & way_status_clken_0; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_3993 = _T_3960 & way_status_clken_1; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_3997 = _T_3964 & way_status_clken_1; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4001 = _T_3968 & way_status_clken_1; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4005 = _T_3972 & way_status_clken_1; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4009 = _T_3976 & way_status_clken_1; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4013 = _T_3980 & way_status_clken_1; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4017 = _T_3984 & way_status_clken_1; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4021 = _T_3988 & way_status_clken_1; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4025 = _T_3960 & way_status_clken_2; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4029 = _T_3964 & way_status_clken_2; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4033 = _T_3968 & way_status_clken_2; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4037 = _T_3972 & way_status_clken_2; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4041 = _T_3976 & way_status_clken_2; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4045 = _T_3980 & way_status_clken_2; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4049 = _T_3984 & way_status_clken_2; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4053 = _T_3988 & way_status_clken_2; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4057 = _T_3960 & way_status_clken_3; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4061 = _T_3964 & way_status_clken_3; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4065 = _T_3968 & way_status_clken_3; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4069 = _T_3972 & way_status_clken_3; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4073 = _T_3976 & way_status_clken_3; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4077 = _T_3980 & way_status_clken_3; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4081 = _T_3984 & way_status_clken_3; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4085 = _T_3988 & way_status_clken_3; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4089 = _T_3960 & way_status_clken_4; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4093 = _T_3964 & way_status_clken_4; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4097 = _T_3968 & way_status_clken_4; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4101 = _T_3972 & way_status_clken_4; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4105 = _T_3976 & way_status_clken_4; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4109 = _T_3980 & way_status_clken_4; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4113 = _T_3984 & way_status_clken_4; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4117 = _T_3988 & way_status_clken_4; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4121 = _T_3960 & way_status_clken_5; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4125 = _T_3964 & way_status_clken_5; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4129 = _T_3968 & way_status_clken_5; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4133 = _T_3972 & way_status_clken_5; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4137 = _T_3976 & way_status_clken_5; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4141 = _T_3980 & way_status_clken_5; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4145 = _T_3984 & way_status_clken_5; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4149 = _T_3988 & way_status_clken_5; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4153 = _T_3960 & way_status_clken_6; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4157 = _T_3964 & way_status_clken_6; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4161 = _T_3968 & way_status_clken_6; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4165 = _T_3972 & way_status_clken_6; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4169 = _T_3976 & way_status_clken_6; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4173 = _T_3980 & way_status_clken_6; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4177 = _T_3984 & way_status_clken_6; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4181 = _T_3988 & way_status_clken_6; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4185 = _T_3960 & way_status_clken_7; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4189 = _T_3964 & way_status_clken_7; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4193 = _T_3968 & way_status_clken_7; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4197 = _T_3972 & way_status_clken_7; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4201 = _T_3976 & way_status_clken_7; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4205 = _T_3980 & way_status_clken_7; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4209 = _T_3984 & way_status_clken_7; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4213 = _T_3988 & way_status_clken_7; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4217 = _T_3960 & way_status_clken_8; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4221 = _T_3964 & way_status_clken_8; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4225 = _T_3968 & way_status_clken_8; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4229 = _T_3972 & way_status_clken_8; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4233 = _T_3976 & way_status_clken_8; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4237 = _T_3980 & way_status_clken_8; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4241 = _T_3984 & way_status_clken_8; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4245 = _T_3988 & way_status_clken_8; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4249 = _T_3960 & way_status_clken_9; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4253 = _T_3964 & way_status_clken_9; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4257 = _T_3968 & way_status_clken_9; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4261 = _T_3972 & way_status_clken_9; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4265 = _T_3976 & way_status_clken_9; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4269 = _T_3980 & way_status_clken_9; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4273 = _T_3984 & way_status_clken_9; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4277 = _T_3988 & way_status_clken_9; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4281 = _T_3960 & way_status_clken_10; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4285 = _T_3964 & way_status_clken_10; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4289 = _T_3968 & way_status_clken_10; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4293 = _T_3972 & way_status_clken_10; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4297 = _T_3976 & way_status_clken_10; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4301 = _T_3980 & way_status_clken_10; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4305 = _T_3984 & way_status_clken_10; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4309 = _T_3988 & way_status_clken_10; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4313 = _T_3960 & way_status_clken_11; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4317 = _T_3964 & way_status_clken_11; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4321 = _T_3968 & way_status_clken_11; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4325 = _T_3972 & way_status_clken_11; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4329 = _T_3976 & way_status_clken_11; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4333 = _T_3980 & way_status_clken_11; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4337 = _T_3984 & way_status_clken_11; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4341 = _T_3988 & way_status_clken_11; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4345 = _T_3960 & way_status_clken_12; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4349 = _T_3964 & way_status_clken_12; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4353 = _T_3968 & way_status_clken_12; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4357 = _T_3972 & way_status_clken_12; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4361 = _T_3976 & way_status_clken_12; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4365 = _T_3980 & way_status_clken_12; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4369 = _T_3984 & way_status_clken_12; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4373 = _T_3988 & way_status_clken_12; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4377 = _T_3960 & way_status_clken_13; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4381 = _T_3964 & way_status_clken_13; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4385 = _T_3968 & way_status_clken_13; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4389 = _T_3972 & way_status_clken_13; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4393 = _T_3976 & way_status_clken_13; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4397 = _T_3980 & way_status_clken_13; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4401 = _T_3984 & way_status_clken_13; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4405 = _T_3988 & way_status_clken_13; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4409 = _T_3960 & way_status_clken_14; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4413 = _T_3964 & way_status_clken_14; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4417 = _T_3968 & way_status_clken_14; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4421 = _T_3972 & way_status_clken_14; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4425 = _T_3976 & way_status_clken_14; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4429 = _T_3980 & way_status_clken_14; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4433 = _T_3984 & way_status_clken_14; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4437 = _T_3988 & way_status_clken_14; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4441 = _T_3960 & way_status_clken_15; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4445 = _T_3964 & way_status_clken_15; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4449 = _T_3968 & way_status_clken_15; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4453 = _T_3972 & way_status_clken_15; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4457 = _T_3976 & way_status_clken_15; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4461 = _T_3980 & way_status_clken_15; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4465 = _T_3984 & way_status_clken_15; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_4469 = _T_3988 & way_status_clken_15; // @[el2_ifu_mem_ctl.scala 715:124] - wire _T_10086 = _T_100 & replace_way_mb_any_1; // @[el2_ifu_mem_ctl.scala 778:84] - wire _T_10087 = _T_10086 & miss_pending; // @[el2_ifu_mem_ctl.scala 778:108] - wire bus_wren_last_1 = _T_10087 & bus_last_data_beat; // @[el2_ifu_mem_ctl.scala 778:123] - wire wren_reset_miss_1 = replace_way_mb_any_1 & reset_tag_valid_for_miss; // @[el2_ifu_mem_ctl.scala 779:84] - wire _T_10089 = bus_wren_last_1 | wren_reset_miss_1; // @[el2_ifu_mem_ctl.scala 780:73] - wire _T_10084 = _T_100 & replace_way_mb_any_0; // @[el2_ifu_mem_ctl.scala 778:84] - wire _T_10085 = _T_10084 & miss_pending; // @[el2_ifu_mem_ctl.scala 778:108] - wire bus_wren_last_0 = _T_10085 & bus_last_data_beat; // @[el2_ifu_mem_ctl.scala 778:123] - wire wren_reset_miss_0 = replace_way_mb_any_0 & reset_tag_valid_for_miss; // @[el2_ifu_mem_ctl.scala 779:84] - wire _T_10088 = bus_wren_last_0 | wren_reset_miss_0; // @[el2_ifu_mem_ctl.scala 780:73] + wire _T_3875 = ~io_ifc_fetch_uncacheable_bf; // @[el2_ifu_mem_ctl.scala 682:41] + wire _T_3876 = io_ifc_fetch_req_bf & _T_3875; // @[el2_ifu_mem_ctl.scala 682:39] + wire _T_3877 = ~io_ifc_iccm_access_bf; // @[el2_ifu_mem_ctl.scala 682:72] + wire _T_3878 = _T_3876 & _T_3877; // @[el2_ifu_mem_ctl.scala 682:70] + wire _T_3880 = ~miss_state_en; // @[el2_ifu_mem_ctl.scala 683:34] + wire _T_3881 = _T_2221 & _T_3880; // @[el2_ifu_mem_ctl.scala 683:32] + wire _T_3884 = _T_2237 & _T_3880; // @[el2_ifu_mem_ctl.scala 684:37] + wire _T_3885 = _T_3881 | _T_3884; // @[el2_ifu_mem_ctl.scala 683:88] + wire _T_3886 = miss_state == 3'h7; // @[el2_ifu_mem_ctl.scala 685:19] + wire _T_3888 = _T_3886 & _T_3880; // @[el2_ifu_mem_ctl.scala 685:41] + wire _T_3889 = _T_3885 | _T_3888; // @[el2_ifu_mem_ctl.scala 684:88] + wire _T_3890 = miss_state == 3'h3; // @[el2_ifu_mem_ctl.scala 686:19] + wire _T_3892 = _T_3890 & _T_3880; // @[el2_ifu_mem_ctl.scala 686:35] + wire _T_3893 = _T_3889 | _T_3892; // @[el2_ifu_mem_ctl.scala 685:88] + wire _T_3896 = _T_2236 & _T_3880; // @[el2_ifu_mem_ctl.scala 687:38] + wire _T_3897 = _T_3893 | _T_3896; // @[el2_ifu_mem_ctl.scala 686:88] + wire _T_3899 = _T_2237 & miss_state_en; // @[el2_ifu_mem_ctl.scala 688:37] + wire _T_3900 = miss_nxtstate == 3'h3; // @[el2_ifu_mem_ctl.scala 688:71] + wire _T_3901 = _T_3899 & _T_3900; // @[el2_ifu_mem_ctl.scala 688:54] + wire _T_3902 = _T_3897 | _T_3901; // @[el2_ifu_mem_ctl.scala 687:57] + wire _T_3903 = ~_T_3902; // @[el2_ifu_mem_ctl.scala 683:5] + wire _T_3904 = _T_3878 & _T_3903; // @[el2_ifu_mem_ctl.scala 682:96] + wire _T_3905 = io_ifc_fetch_req_bf & io_exu_flush_final; // @[el2_ifu_mem_ctl.scala 689:28] + wire _T_3907 = _T_3905 & _T_3875; // @[el2_ifu_mem_ctl.scala 689:50] + wire _T_3909 = _T_3907 & _T_3877; // @[el2_ifu_mem_ctl.scala 689:81] + wire _T_3918 = ~_T_108; // @[el2_ifu_mem_ctl.scala 692:106] + wire _T_3919 = _T_2221 & _T_3918; // @[el2_ifu_mem_ctl.scala 692:104] + wire _T_3920 = _T_2237 | _T_3919; // @[el2_ifu_mem_ctl.scala 692:77] + wire _T_3924 = ~_T_51; // @[el2_ifu_mem_ctl.scala 692:172] + wire _T_3925 = _T_3920 & _T_3924; // @[el2_ifu_mem_ctl.scala 692:170] + wire _T_3926 = ~_T_3925; // @[el2_ifu_mem_ctl.scala 692:44] + wire _T_3930 = reset_ic_in | reset_ic_ff; // @[el2_ifu_mem_ctl.scala 695:64] + wire _T_3931 = ~_T_3930; // @[el2_ifu_mem_ctl.scala 695:50] + wire _T_3932 = _T_276 & _T_3931; // @[el2_ifu_mem_ctl.scala 695:48] + wire _T_3933 = ~reset_tag_valid_for_miss; // @[el2_ifu_mem_ctl.scala 695:81] + wire ic_valid = _T_3932 & _T_3933; // @[el2_ifu_mem_ctl.scala 695:79] + wire _T_3935 = debug_c1_clken & io_ic_debug_tag_array; // @[el2_ifu_mem_ctl.scala 696:82] + reg [6:0] ifu_status_wr_addr_ff; // @[el2_ifu_mem_ctl.scala 699:14] + wire _T_3938 = io_ic_debug_wr_en & io_ic_debug_tag_array; // @[el2_ifu_mem_ctl.scala 702:74] + wire _T_10080 = bus_ifu_wr_en_ff_q & last_beat; // @[el2_ifu_mem_ctl.scala 776:45] + wire way_status_wr_en = _T_10080 | ic_act_hit_f; // @[el2_ifu_mem_ctl.scala 776:58] + wire way_status_wr_en_w_debug = way_status_wr_en | _T_3938; // @[el2_ifu_mem_ctl.scala 702:53] + reg way_status_wr_en_ff; // @[el2_ifu_mem_ctl.scala 704:14] + wire [2:0] _T_3942 = {{2'd0}, io_ic_debug_wr_data[4]}; // @[el2_ifu_mem_ctl.scala 708:10] + wire way_status_hit_new = io_ic_rd_hit[0]; // @[el2_ifu_mem_ctl.scala 772:41] + wire way_status_new = _T_10080 ? replace_way_mb_any_0 : way_status_hit_new; // @[el2_ifu_mem_ctl.scala 775:26] + reg [2:0] way_status_new_ff; // @[el2_ifu_mem_ctl.scala 710:14] + wire way_status_clken_0 = ifu_status_wr_addr_ff[6:3] == 4'h0; // @[el2_ifu_mem_ctl.scala 712:132] + wire way_status_clken_1 = ifu_status_wr_addr_ff[6:3] == 4'h1; // @[el2_ifu_mem_ctl.scala 712:132] + wire way_status_clken_2 = ifu_status_wr_addr_ff[6:3] == 4'h2; // @[el2_ifu_mem_ctl.scala 712:132] + wire way_status_clken_3 = ifu_status_wr_addr_ff[6:3] == 4'h3; // @[el2_ifu_mem_ctl.scala 712:132] + wire way_status_clken_4 = ifu_status_wr_addr_ff[6:3] == 4'h4; // @[el2_ifu_mem_ctl.scala 712:132] + wire way_status_clken_5 = ifu_status_wr_addr_ff[6:3] == 4'h5; // @[el2_ifu_mem_ctl.scala 712:132] + wire way_status_clken_6 = ifu_status_wr_addr_ff[6:3] == 4'h6; // @[el2_ifu_mem_ctl.scala 712:132] + wire way_status_clken_7 = ifu_status_wr_addr_ff[6:3] == 4'h7; // @[el2_ifu_mem_ctl.scala 712:132] + wire way_status_clken_8 = ifu_status_wr_addr_ff[6:3] == 4'h8; // @[el2_ifu_mem_ctl.scala 712:132] + wire way_status_clken_9 = ifu_status_wr_addr_ff[6:3] == 4'h9; // @[el2_ifu_mem_ctl.scala 712:132] + wire way_status_clken_10 = ifu_status_wr_addr_ff[6:3] == 4'ha; // @[el2_ifu_mem_ctl.scala 712:132] + wire way_status_clken_11 = ifu_status_wr_addr_ff[6:3] == 4'hb; // @[el2_ifu_mem_ctl.scala 712:132] + wire way_status_clken_12 = ifu_status_wr_addr_ff[6:3] == 4'hc; // @[el2_ifu_mem_ctl.scala 712:132] + wire way_status_clken_13 = ifu_status_wr_addr_ff[6:3] == 4'hd; // @[el2_ifu_mem_ctl.scala 712:132] + wire way_status_clken_14 = ifu_status_wr_addr_ff[6:3] == 4'he; // @[el2_ifu_mem_ctl.scala 712:132] + wire way_status_clken_15 = ifu_status_wr_addr_ff[6:3] == 4'hf; // @[el2_ifu_mem_ctl.scala 712:132] + wire _T_3959 = ifu_status_wr_addr_ff == 7'h0; // @[el2_ifu_mem_ctl.scala 716:93] + wire _T_3960 = _T_3959 & way_status_wr_en_ff; // @[el2_ifu_mem_ctl.scala 716:102] + wire _T_3961 = _T_3960 & way_status_clken_0; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_3963 = ifu_status_wr_addr_ff == 7'h1; // @[el2_ifu_mem_ctl.scala 716:93] + wire _T_3964 = _T_3963 & way_status_wr_en_ff; // @[el2_ifu_mem_ctl.scala 716:102] + wire _T_3965 = _T_3964 & way_status_clken_0; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_3967 = ifu_status_wr_addr_ff == 7'h2; // @[el2_ifu_mem_ctl.scala 716:93] + wire _T_3968 = _T_3967 & way_status_wr_en_ff; // @[el2_ifu_mem_ctl.scala 716:102] + wire _T_3969 = _T_3968 & way_status_clken_0; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_3971 = ifu_status_wr_addr_ff == 7'h3; // @[el2_ifu_mem_ctl.scala 716:93] + wire _T_3972 = _T_3971 & way_status_wr_en_ff; // @[el2_ifu_mem_ctl.scala 716:102] + wire _T_3973 = _T_3972 & way_status_clken_0; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_3975 = ifu_status_wr_addr_ff == 7'h4; // @[el2_ifu_mem_ctl.scala 716:93] + wire _T_3976 = _T_3975 & way_status_wr_en_ff; // @[el2_ifu_mem_ctl.scala 716:102] + wire _T_3977 = _T_3976 & way_status_clken_0; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_3979 = ifu_status_wr_addr_ff == 7'h5; // @[el2_ifu_mem_ctl.scala 716:93] + wire _T_3980 = _T_3979 & way_status_wr_en_ff; // @[el2_ifu_mem_ctl.scala 716:102] + wire _T_3981 = _T_3980 & way_status_clken_0; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_3983 = ifu_status_wr_addr_ff == 7'h6; // @[el2_ifu_mem_ctl.scala 716:93] + wire _T_3984 = _T_3983 & way_status_wr_en_ff; // @[el2_ifu_mem_ctl.scala 716:102] + wire _T_3985 = _T_3984 & way_status_clken_0; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_3987 = ifu_status_wr_addr_ff == 7'h7; // @[el2_ifu_mem_ctl.scala 716:93] + wire _T_3988 = _T_3987 & way_status_wr_en_ff; // @[el2_ifu_mem_ctl.scala 716:102] + wire _T_3989 = _T_3988 & way_status_clken_0; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_3993 = _T_3960 & way_status_clken_1; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_3997 = _T_3964 & way_status_clken_1; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4001 = _T_3968 & way_status_clken_1; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4005 = _T_3972 & way_status_clken_1; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4009 = _T_3976 & way_status_clken_1; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4013 = _T_3980 & way_status_clken_1; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4017 = _T_3984 & way_status_clken_1; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4021 = _T_3988 & way_status_clken_1; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4025 = _T_3960 & way_status_clken_2; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4029 = _T_3964 & way_status_clken_2; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4033 = _T_3968 & way_status_clken_2; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4037 = _T_3972 & way_status_clken_2; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4041 = _T_3976 & way_status_clken_2; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4045 = _T_3980 & way_status_clken_2; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4049 = _T_3984 & way_status_clken_2; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4053 = _T_3988 & way_status_clken_2; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4057 = _T_3960 & way_status_clken_3; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4061 = _T_3964 & way_status_clken_3; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4065 = _T_3968 & way_status_clken_3; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4069 = _T_3972 & way_status_clken_3; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4073 = _T_3976 & way_status_clken_3; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4077 = _T_3980 & way_status_clken_3; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4081 = _T_3984 & way_status_clken_3; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4085 = _T_3988 & way_status_clken_3; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4089 = _T_3960 & way_status_clken_4; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4093 = _T_3964 & way_status_clken_4; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4097 = _T_3968 & way_status_clken_4; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4101 = _T_3972 & way_status_clken_4; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4105 = _T_3976 & way_status_clken_4; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4109 = _T_3980 & way_status_clken_4; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4113 = _T_3984 & way_status_clken_4; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4117 = _T_3988 & way_status_clken_4; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4121 = _T_3960 & way_status_clken_5; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4125 = _T_3964 & way_status_clken_5; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4129 = _T_3968 & way_status_clken_5; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4133 = _T_3972 & way_status_clken_5; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4137 = _T_3976 & way_status_clken_5; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4141 = _T_3980 & way_status_clken_5; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4145 = _T_3984 & way_status_clken_5; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4149 = _T_3988 & way_status_clken_5; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4153 = _T_3960 & way_status_clken_6; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4157 = _T_3964 & way_status_clken_6; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4161 = _T_3968 & way_status_clken_6; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4165 = _T_3972 & way_status_clken_6; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4169 = _T_3976 & way_status_clken_6; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4173 = _T_3980 & way_status_clken_6; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4177 = _T_3984 & way_status_clken_6; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4181 = _T_3988 & way_status_clken_6; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4185 = _T_3960 & way_status_clken_7; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4189 = _T_3964 & way_status_clken_7; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4193 = _T_3968 & way_status_clken_7; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4197 = _T_3972 & way_status_clken_7; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4201 = _T_3976 & way_status_clken_7; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4205 = _T_3980 & way_status_clken_7; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4209 = _T_3984 & way_status_clken_7; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4213 = _T_3988 & way_status_clken_7; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4217 = _T_3960 & way_status_clken_8; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4221 = _T_3964 & way_status_clken_8; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4225 = _T_3968 & way_status_clken_8; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4229 = _T_3972 & way_status_clken_8; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4233 = _T_3976 & way_status_clken_8; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4237 = _T_3980 & way_status_clken_8; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4241 = _T_3984 & way_status_clken_8; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4245 = _T_3988 & way_status_clken_8; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4249 = _T_3960 & way_status_clken_9; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4253 = _T_3964 & way_status_clken_9; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4257 = _T_3968 & way_status_clken_9; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4261 = _T_3972 & way_status_clken_9; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4265 = _T_3976 & way_status_clken_9; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4269 = _T_3980 & way_status_clken_9; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4273 = _T_3984 & way_status_clken_9; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4277 = _T_3988 & way_status_clken_9; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4281 = _T_3960 & way_status_clken_10; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4285 = _T_3964 & way_status_clken_10; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4289 = _T_3968 & way_status_clken_10; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4293 = _T_3972 & way_status_clken_10; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4297 = _T_3976 & way_status_clken_10; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4301 = _T_3980 & way_status_clken_10; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4305 = _T_3984 & way_status_clken_10; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4309 = _T_3988 & way_status_clken_10; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4313 = _T_3960 & way_status_clken_11; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4317 = _T_3964 & way_status_clken_11; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4321 = _T_3968 & way_status_clken_11; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4325 = _T_3972 & way_status_clken_11; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4329 = _T_3976 & way_status_clken_11; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4333 = _T_3980 & way_status_clken_11; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4337 = _T_3984 & way_status_clken_11; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4341 = _T_3988 & way_status_clken_11; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4345 = _T_3960 & way_status_clken_12; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4349 = _T_3964 & way_status_clken_12; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4353 = _T_3968 & way_status_clken_12; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4357 = _T_3972 & way_status_clken_12; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4361 = _T_3976 & way_status_clken_12; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4365 = _T_3980 & way_status_clken_12; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4369 = _T_3984 & way_status_clken_12; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4373 = _T_3988 & way_status_clken_12; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4377 = _T_3960 & way_status_clken_13; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4381 = _T_3964 & way_status_clken_13; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4385 = _T_3968 & way_status_clken_13; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4389 = _T_3972 & way_status_clken_13; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4393 = _T_3976 & way_status_clken_13; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4397 = _T_3980 & way_status_clken_13; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4401 = _T_3984 & way_status_clken_13; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4405 = _T_3988 & way_status_clken_13; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4409 = _T_3960 & way_status_clken_14; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4413 = _T_3964 & way_status_clken_14; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4417 = _T_3968 & way_status_clken_14; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4421 = _T_3972 & way_status_clken_14; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4425 = _T_3976 & way_status_clken_14; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4429 = _T_3980 & way_status_clken_14; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4433 = _T_3984 & way_status_clken_14; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4437 = _T_3988 & way_status_clken_14; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4441 = _T_3960 & way_status_clken_15; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4445 = _T_3964 & way_status_clken_15; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4449 = _T_3968 & way_status_clken_15; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4453 = _T_3972 & way_status_clken_15; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4457 = _T_3976 & way_status_clken_15; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4461 = _T_3980 & way_status_clken_15; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4465 = _T_3984 & way_status_clken_15; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_4469 = _T_3988 & way_status_clken_15; // @[el2_ifu_mem_ctl.scala 716:124] + wire _T_10086 = _T_100 & replace_way_mb_any_1; // @[el2_ifu_mem_ctl.scala 779:84] + wire _T_10087 = _T_10086 & miss_pending; // @[el2_ifu_mem_ctl.scala 779:108] + wire bus_wren_last_1 = _T_10087 & bus_last_data_beat; // @[el2_ifu_mem_ctl.scala 779:123] + wire wren_reset_miss_1 = replace_way_mb_any_1 & reset_tag_valid_for_miss; // @[el2_ifu_mem_ctl.scala 780:84] + wire _T_10089 = bus_wren_last_1 | wren_reset_miss_1; // @[el2_ifu_mem_ctl.scala 781:73] + wire _T_10084 = _T_100 & replace_way_mb_any_0; // @[el2_ifu_mem_ctl.scala 779:84] + wire _T_10085 = _T_10084 & miss_pending; // @[el2_ifu_mem_ctl.scala 779:108] + wire bus_wren_last_0 = _T_10085 & bus_last_data_beat; // @[el2_ifu_mem_ctl.scala 779:123] + wire wren_reset_miss_0 = replace_way_mb_any_0 & reset_tag_valid_for_miss; // @[el2_ifu_mem_ctl.scala 780:84] + wire _T_10088 = bus_wren_last_0 | wren_reset_miss_0; // @[el2_ifu_mem_ctl.scala 781:73] wire [1:0] ifu_tag_wren = {_T_10089,_T_10088}; // @[Cat.scala 29:58] wire [1:0] _T_10123 = _T_3938 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] ic_debug_tag_wr_en = _T_10123 & io_ic_debug_way; // @[el2_ifu_mem_ctl.scala 813:90] - wire [1:0] ifu_tag_wren_w_debug = ifu_tag_wren | ic_debug_tag_wr_en; // @[el2_ifu_mem_ctl.scala 724:45] - reg [1:0] ifu_tag_wren_ff; // @[el2_ifu_mem_ctl.scala 726:14] - reg ic_valid_ff; // @[el2_ifu_mem_ctl.scala 730:14] - wire _T_5118 = ifu_ic_rw_int_addr_ff[5:4] == 2'h0; // @[el2_ifu_mem_ctl.scala 734:82] - wire _T_5120 = _T_5118 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 734:91] - wire _T_5122 = perr_ic_index_ff[5:4] == 2'h0; // @[el2_ifu_mem_ctl.scala 735:74] - wire _T_5124 = _T_5122 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 735:83] - wire _T_5125 = _T_5120 | _T_5124; // @[el2_ifu_mem_ctl.scala 734:113] - wire _T_5126 = _T_5125 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 735:106] - wire _T_5130 = _T_5118 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 734:91] - wire _T_5134 = _T_5122 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 735:83] - wire _T_5135 = _T_5130 | _T_5134; // @[el2_ifu_mem_ctl.scala 734:113] - wire _T_5136 = _T_5135 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 735:106] + wire [1:0] ic_debug_tag_wr_en = _T_10123 & io_ic_debug_way; // @[el2_ifu_mem_ctl.scala 814:90] + wire [1:0] ifu_tag_wren_w_debug = ifu_tag_wren | ic_debug_tag_wr_en; // @[el2_ifu_mem_ctl.scala 725:45] + reg [1:0] ifu_tag_wren_ff; // @[el2_ifu_mem_ctl.scala 727:14] + reg ic_valid_ff; // @[el2_ifu_mem_ctl.scala 731:14] + wire _T_5118 = ifu_ic_rw_int_addr_ff[5:4] == 2'h0; // @[el2_ifu_mem_ctl.scala 735:82] + wire _T_5120 = _T_5118 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 735:91] + wire _T_5122 = perr_ic_index_ff[5:4] == 2'h0; // @[el2_ifu_mem_ctl.scala 736:74] + wire _T_5124 = _T_5122 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 736:83] + wire _T_5125 = _T_5120 | _T_5124; // @[el2_ifu_mem_ctl.scala 735:113] + wire _T_5126 = _T_5125 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 736:106] + wire _T_5130 = _T_5118 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 735:91] + wire _T_5134 = _T_5122 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 736:83] + wire _T_5135 = _T_5130 | _T_5134; // @[el2_ifu_mem_ctl.scala 735:113] + wire _T_5136 = _T_5135 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 736:106] wire [1:0] tag_valid_clken_0 = {_T_5126,_T_5136}; // @[Cat.scala 29:58] - wire _T_5138 = ifu_ic_rw_int_addr_ff[5:4] == 2'h1; // @[el2_ifu_mem_ctl.scala 734:82] - wire _T_5140 = _T_5138 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 734:91] - wire _T_5142 = perr_ic_index_ff[5:4] == 2'h1; // @[el2_ifu_mem_ctl.scala 735:74] - wire _T_5144 = _T_5142 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 735:83] - wire _T_5145 = _T_5140 | _T_5144; // @[el2_ifu_mem_ctl.scala 734:113] - wire _T_5146 = _T_5145 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 735:106] - wire _T_5150 = _T_5138 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 734:91] - wire _T_5154 = _T_5142 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 735:83] - wire _T_5155 = _T_5150 | _T_5154; // @[el2_ifu_mem_ctl.scala 734:113] - wire _T_5156 = _T_5155 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 735:106] + wire _T_5138 = ifu_ic_rw_int_addr_ff[5:4] == 2'h1; // @[el2_ifu_mem_ctl.scala 735:82] + wire _T_5140 = _T_5138 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 735:91] + wire _T_5142 = perr_ic_index_ff[5:4] == 2'h1; // @[el2_ifu_mem_ctl.scala 736:74] + wire _T_5144 = _T_5142 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 736:83] + wire _T_5145 = _T_5140 | _T_5144; // @[el2_ifu_mem_ctl.scala 735:113] + wire _T_5146 = _T_5145 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 736:106] + wire _T_5150 = _T_5138 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 735:91] + wire _T_5154 = _T_5142 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 736:83] + wire _T_5155 = _T_5150 | _T_5154; // @[el2_ifu_mem_ctl.scala 735:113] + wire _T_5156 = _T_5155 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 736:106] wire [1:0] tag_valid_clken_1 = {_T_5146,_T_5156}; // @[Cat.scala 29:58] - wire _T_5158 = ifu_ic_rw_int_addr_ff[5:4] == 2'h2; // @[el2_ifu_mem_ctl.scala 734:82] - wire _T_5160 = _T_5158 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 734:91] - wire _T_5162 = perr_ic_index_ff[5:4] == 2'h2; // @[el2_ifu_mem_ctl.scala 735:74] - wire _T_5164 = _T_5162 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 735:83] - wire _T_5165 = _T_5160 | _T_5164; // @[el2_ifu_mem_ctl.scala 734:113] - wire _T_5166 = _T_5165 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 735:106] - wire _T_5170 = _T_5158 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 734:91] - wire _T_5174 = _T_5162 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 735:83] - wire _T_5175 = _T_5170 | _T_5174; // @[el2_ifu_mem_ctl.scala 734:113] - wire _T_5176 = _T_5175 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 735:106] + wire _T_5158 = ifu_ic_rw_int_addr_ff[5:4] == 2'h2; // @[el2_ifu_mem_ctl.scala 735:82] + wire _T_5160 = _T_5158 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 735:91] + wire _T_5162 = perr_ic_index_ff[5:4] == 2'h2; // @[el2_ifu_mem_ctl.scala 736:74] + wire _T_5164 = _T_5162 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 736:83] + wire _T_5165 = _T_5160 | _T_5164; // @[el2_ifu_mem_ctl.scala 735:113] + wire _T_5166 = _T_5165 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 736:106] + wire _T_5170 = _T_5158 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 735:91] + wire _T_5174 = _T_5162 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 736:83] + wire _T_5175 = _T_5170 | _T_5174; // @[el2_ifu_mem_ctl.scala 735:113] + wire _T_5176 = _T_5175 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 736:106] wire [1:0] tag_valid_clken_2 = {_T_5166,_T_5176}; // @[Cat.scala 29:58] - wire _T_5178 = ifu_ic_rw_int_addr_ff[5:4] == 2'h3; // @[el2_ifu_mem_ctl.scala 734:82] - wire _T_5180 = _T_5178 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 734:91] - wire _T_5182 = perr_ic_index_ff[5:4] == 2'h3; // @[el2_ifu_mem_ctl.scala 735:74] - wire _T_5184 = _T_5182 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 735:83] - wire _T_5185 = _T_5180 | _T_5184; // @[el2_ifu_mem_ctl.scala 734:113] - wire _T_5186 = _T_5185 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 735:106] - wire _T_5190 = _T_5178 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 734:91] - wire _T_5194 = _T_5182 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 735:83] - wire _T_5195 = _T_5190 | _T_5194; // @[el2_ifu_mem_ctl.scala 734:113] - wire _T_5196 = _T_5195 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 735:106] + wire _T_5178 = ifu_ic_rw_int_addr_ff[5:4] == 2'h3; // @[el2_ifu_mem_ctl.scala 735:82] + wire _T_5180 = _T_5178 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 735:91] + wire _T_5182 = perr_ic_index_ff[5:4] == 2'h3; // @[el2_ifu_mem_ctl.scala 736:74] + wire _T_5184 = _T_5182 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 736:83] + wire _T_5185 = _T_5180 | _T_5184; // @[el2_ifu_mem_ctl.scala 735:113] + wire _T_5186 = _T_5185 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 736:106] + wire _T_5190 = _T_5178 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 735:91] + wire _T_5194 = _T_5182 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 736:83] + wire _T_5195 = _T_5190 | _T_5194; // @[el2_ifu_mem_ctl.scala 735:113] + wire _T_5196 = _T_5195 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 736:106] wire [1:0] tag_valid_clken_3 = {_T_5186,_T_5196}; // @[Cat.scala 29:58] - wire _T_5199 = ic_valid_ff & _T_195; // @[el2_ifu_mem_ctl.scala 740:64] - wire _T_5200 = ~perr_sel_invalidate; // @[el2_ifu_mem_ctl.scala 740:91] - wire _T_5201 = _T_5199 & _T_5200; // @[el2_ifu_mem_ctl.scala 740:89] - wire _T_5204 = _T_4471 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_5205 = perr_ic_index_ff == 6'h0; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_5207 = _T_5205 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_5209 = _T_5207 & tag_valid_clken_0[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_5210 = _T_5204 | _T_5209; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_5220 = _T_4475 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_5221 = perr_ic_index_ff == 6'h1; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_5223 = _T_5221 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_5225 = _T_5223 & tag_valid_clken_0[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_5226 = _T_5220 | _T_5225; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_5236 = _T_4479 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_5237 = perr_ic_index_ff == 6'h2; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_5239 = _T_5237 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_5241 = _T_5239 & tag_valid_clken_0[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_5242 = _T_5236 | _T_5241; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_5252 = _T_4483 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_5253 = perr_ic_index_ff == 6'h3; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_5255 = _T_5253 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_5257 = _T_5255 & tag_valid_clken_0[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_5258 = _T_5252 | _T_5257; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_5268 = _T_4487 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_5269 = perr_ic_index_ff == 6'h4; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_5271 = _T_5269 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_5273 = _T_5271 & tag_valid_clken_0[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_5274 = _T_5268 | _T_5273; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_5284 = _T_4491 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_5285 = perr_ic_index_ff == 6'h5; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_5287 = _T_5285 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_5289 = _T_5287 & tag_valid_clken_0[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_5290 = _T_5284 | _T_5289; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_5300 = _T_4495 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_5301 = perr_ic_index_ff == 6'h6; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_5303 = _T_5301 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_5305 = _T_5303 & tag_valid_clken_0[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_5306 = _T_5300 | _T_5305; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_5316 = _T_4499 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_5317 = perr_ic_index_ff == 6'h7; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_5319 = _T_5317 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_5321 = _T_5319 & tag_valid_clken_0[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_5322 = _T_5316 | _T_5321; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_5332 = _T_4503 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_5333 = perr_ic_index_ff == 6'h8; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_5335 = _T_5333 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_5337 = _T_5335 & tag_valid_clken_0[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_5338 = _T_5332 | _T_5337; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_5348 = _T_4507 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_5349 = perr_ic_index_ff == 6'h9; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_5351 = _T_5349 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_5353 = _T_5351 & tag_valid_clken_0[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_5354 = _T_5348 | _T_5353; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_5364 = _T_4511 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_5365 = perr_ic_index_ff == 6'ha; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_5367 = _T_5365 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_5369 = _T_5367 & tag_valid_clken_0[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_5370 = _T_5364 | _T_5369; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_5380 = _T_4515 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_5381 = perr_ic_index_ff == 6'hb; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_5383 = _T_5381 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_5385 = _T_5383 & tag_valid_clken_0[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_5386 = _T_5380 | _T_5385; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_5396 = _T_4519 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_5397 = perr_ic_index_ff == 6'hc; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_5399 = _T_5397 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_5401 = _T_5399 & tag_valid_clken_0[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_5402 = _T_5396 | _T_5401; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_5412 = _T_4523 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_5413 = perr_ic_index_ff == 6'hd; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_5415 = _T_5413 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_5417 = _T_5415 & tag_valid_clken_0[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_5418 = _T_5412 | _T_5417; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_5428 = _T_4527 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_5429 = perr_ic_index_ff == 6'he; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_5431 = _T_5429 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_5433 = _T_5431 & tag_valid_clken_0[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_5434 = _T_5428 | _T_5433; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_5444 = _T_4531 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_5445 = perr_ic_index_ff == 6'hf; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_5447 = _T_5445 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_5449 = _T_5447 & tag_valid_clken_0[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_5450 = _T_5444 | _T_5449; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_5460 = _T_4535 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_5461 = perr_ic_index_ff == 6'h10; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_5463 = _T_5461 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_5465 = _T_5463 & tag_valid_clken_0[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_5466 = _T_5460 | _T_5465; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_5476 = _T_4539 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_5477 = perr_ic_index_ff == 6'h11; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_5479 = _T_5477 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_5481 = _T_5479 & tag_valid_clken_0[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_5482 = _T_5476 | _T_5481; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_5492 = _T_4543 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_5493 = perr_ic_index_ff == 6'h12; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_5495 = _T_5493 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_5497 = _T_5495 & tag_valid_clken_0[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_5498 = _T_5492 | _T_5497; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_5508 = _T_4547 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_5509 = perr_ic_index_ff == 6'h13; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_5511 = _T_5509 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_5513 = _T_5511 & tag_valid_clken_0[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_5514 = _T_5508 | _T_5513; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_5524 = _T_4551 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_5525 = perr_ic_index_ff == 6'h14; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_5527 = _T_5525 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_5529 = _T_5527 & tag_valid_clken_0[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_5530 = _T_5524 | _T_5529; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_5540 = _T_4555 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_5541 = perr_ic_index_ff == 6'h15; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_5543 = _T_5541 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_5545 = _T_5543 & tag_valid_clken_0[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_5546 = _T_5540 | _T_5545; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_5556 = _T_4559 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_5557 = perr_ic_index_ff == 6'h16; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_5559 = _T_5557 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_5561 = _T_5559 & tag_valid_clken_0[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_5562 = _T_5556 | _T_5561; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_5572 = _T_4563 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_5573 = perr_ic_index_ff == 6'h17; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_5575 = _T_5573 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_5577 = _T_5575 & tag_valid_clken_0[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_5578 = _T_5572 | _T_5577; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_5588 = _T_4567 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_5589 = perr_ic_index_ff == 6'h18; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_5591 = _T_5589 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_5593 = _T_5591 & tag_valid_clken_0[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_5594 = _T_5588 | _T_5593; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_5604 = _T_4571 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_5605 = perr_ic_index_ff == 6'h19; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_5607 = _T_5605 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_5609 = _T_5607 & tag_valid_clken_0[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_5610 = _T_5604 | _T_5609; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_5620 = _T_4575 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_5621 = perr_ic_index_ff == 6'h1a; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_5623 = _T_5621 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_5625 = _T_5623 & tag_valid_clken_0[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_5626 = _T_5620 | _T_5625; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_5636 = _T_4579 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_5637 = perr_ic_index_ff == 6'h1b; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_5639 = _T_5637 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_5641 = _T_5639 & tag_valid_clken_0[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_5642 = _T_5636 | _T_5641; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_5652 = _T_4583 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_5653 = perr_ic_index_ff == 6'h1c; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_5655 = _T_5653 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_5657 = _T_5655 & tag_valid_clken_0[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_5658 = _T_5652 | _T_5657; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_5668 = _T_4587 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_5669 = perr_ic_index_ff == 6'h1d; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_5671 = _T_5669 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_5673 = _T_5671 & tag_valid_clken_0[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_5674 = _T_5668 | _T_5673; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_5684 = _T_4591 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_5685 = perr_ic_index_ff == 6'h1e; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_5687 = _T_5685 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_5689 = _T_5687 & tag_valid_clken_0[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_5690 = _T_5684 | _T_5689; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_5700 = _T_4595 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_5701 = perr_ic_index_ff == 6'h1f; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_5703 = _T_5701 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_5705 = _T_5703 & tag_valid_clken_0[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_5706 = _T_5700 | _T_5705; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_5716 = _T_4471 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_5719 = _T_5205 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_5721 = _T_5719 & tag_valid_clken_0[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_5722 = _T_5716 | _T_5721; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_5732 = _T_4475 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_5735 = _T_5221 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_5737 = _T_5735 & tag_valid_clken_0[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_5738 = _T_5732 | _T_5737; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_5748 = _T_4479 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_5751 = _T_5237 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_5753 = _T_5751 & tag_valid_clken_0[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_5754 = _T_5748 | _T_5753; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_5764 = _T_4483 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_5767 = _T_5253 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_5769 = _T_5767 & tag_valid_clken_0[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_5770 = _T_5764 | _T_5769; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_5780 = _T_4487 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_5783 = _T_5269 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_5785 = _T_5783 & tag_valid_clken_0[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_5786 = _T_5780 | _T_5785; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_5796 = _T_4491 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_5799 = _T_5285 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_5801 = _T_5799 & tag_valid_clken_0[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_5802 = _T_5796 | _T_5801; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_5812 = _T_4495 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_5815 = _T_5301 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_5817 = _T_5815 & tag_valid_clken_0[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_5818 = _T_5812 | _T_5817; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_5828 = _T_4499 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_5831 = _T_5317 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_5833 = _T_5831 & tag_valid_clken_0[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_5834 = _T_5828 | _T_5833; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_5844 = _T_4503 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_5847 = _T_5333 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_5849 = _T_5847 & tag_valid_clken_0[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_5850 = _T_5844 | _T_5849; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_5860 = _T_4507 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_5863 = _T_5349 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_5865 = _T_5863 & tag_valid_clken_0[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_5866 = _T_5860 | _T_5865; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_5876 = _T_4511 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_5879 = _T_5365 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_5881 = _T_5879 & tag_valid_clken_0[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_5882 = _T_5876 | _T_5881; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_5892 = _T_4515 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_5895 = _T_5381 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_5897 = _T_5895 & tag_valid_clken_0[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_5898 = _T_5892 | _T_5897; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_5908 = _T_4519 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_5911 = _T_5397 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_5913 = _T_5911 & tag_valid_clken_0[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_5914 = _T_5908 | _T_5913; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_5924 = _T_4523 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_5927 = _T_5413 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_5929 = _T_5927 & tag_valid_clken_0[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_5930 = _T_5924 | _T_5929; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_5940 = _T_4527 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_5943 = _T_5429 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_5945 = _T_5943 & tag_valid_clken_0[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_5946 = _T_5940 | _T_5945; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_5956 = _T_4531 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_5959 = _T_5445 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_5961 = _T_5959 & tag_valid_clken_0[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_5962 = _T_5956 | _T_5961; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_5972 = _T_4535 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_5975 = _T_5461 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_5977 = _T_5975 & tag_valid_clken_0[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_5978 = _T_5972 | _T_5977; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_5988 = _T_4539 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_5991 = _T_5477 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_5993 = _T_5991 & tag_valid_clken_0[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_5994 = _T_5988 | _T_5993; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_6004 = _T_4543 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_6007 = _T_5493 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_6009 = _T_6007 & tag_valid_clken_0[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_6010 = _T_6004 | _T_6009; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_6020 = _T_4547 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_6023 = _T_5509 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_6025 = _T_6023 & tag_valid_clken_0[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_6026 = _T_6020 | _T_6025; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_6036 = _T_4551 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_6039 = _T_5525 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_6041 = _T_6039 & tag_valid_clken_0[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_6042 = _T_6036 | _T_6041; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_6052 = _T_4555 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_6055 = _T_5541 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_6057 = _T_6055 & tag_valid_clken_0[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_6058 = _T_6052 | _T_6057; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_6068 = _T_4559 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_6071 = _T_5557 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_6073 = _T_6071 & tag_valid_clken_0[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_6074 = _T_6068 | _T_6073; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_6084 = _T_4563 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_6087 = _T_5573 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_6089 = _T_6087 & tag_valid_clken_0[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_6090 = _T_6084 | _T_6089; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_6100 = _T_4567 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_6103 = _T_5589 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_6105 = _T_6103 & tag_valid_clken_0[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_6106 = _T_6100 | _T_6105; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_6116 = _T_4571 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_6119 = _T_5605 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_6121 = _T_6119 & tag_valid_clken_0[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_6122 = _T_6116 | _T_6121; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_6132 = _T_4575 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_6135 = _T_5621 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_6137 = _T_6135 & tag_valid_clken_0[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_6138 = _T_6132 | _T_6137; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_6148 = _T_4579 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_6151 = _T_5637 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_6153 = _T_6151 & tag_valid_clken_0[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_6154 = _T_6148 | _T_6153; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_6164 = _T_4583 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_6167 = _T_5653 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_6169 = _T_6167 & tag_valid_clken_0[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_6170 = _T_6164 | _T_6169; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_6180 = _T_4587 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_6183 = _T_5669 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_6185 = _T_6183 & tag_valid_clken_0[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_6186 = _T_6180 | _T_6185; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_6196 = _T_4591 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_6199 = _T_5685 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_6201 = _T_6199 & tag_valid_clken_0[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_6202 = _T_6196 | _T_6201; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_6212 = _T_4595 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_6215 = _T_5701 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_6217 = _T_6215 & tag_valid_clken_0[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_6218 = _T_6212 | _T_6217; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_6228 = _T_4599 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_6229 = perr_ic_index_ff == 6'h20; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_6231 = _T_6229 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_6233 = _T_6231 & tag_valid_clken_1[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_6234 = _T_6228 | _T_6233; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_6244 = _T_4603 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_6245 = perr_ic_index_ff == 6'h21; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_6247 = _T_6245 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_6249 = _T_6247 & tag_valid_clken_1[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_6250 = _T_6244 | _T_6249; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_6260 = _T_4607 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_6261 = perr_ic_index_ff == 6'h22; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_6263 = _T_6261 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_6265 = _T_6263 & tag_valid_clken_1[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_6266 = _T_6260 | _T_6265; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_6276 = _T_4611 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_6277 = perr_ic_index_ff == 6'h23; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_6279 = _T_6277 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_6281 = _T_6279 & tag_valid_clken_1[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_6282 = _T_6276 | _T_6281; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_6292 = _T_4615 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_6293 = perr_ic_index_ff == 6'h24; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_6295 = _T_6293 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_6297 = _T_6295 & tag_valid_clken_1[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_6298 = _T_6292 | _T_6297; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_6308 = _T_4619 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_6309 = perr_ic_index_ff == 6'h25; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_6311 = _T_6309 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_6313 = _T_6311 & tag_valid_clken_1[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_6314 = _T_6308 | _T_6313; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_6324 = _T_4623 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_6325 = perr_ic_index_ff == 6'h26; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_6327 = _T_6325 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_6329 = _T_6327 & tag_valid_clken_1[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_6330 = _T_6324 | _T_6329; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_6340 = _T_4627 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_6341 = perr_ic_index_ff == 6'h27; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_6343 = _T_6341 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_6345 = _T_6343 & tag_valid_clken_1[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_6346 = _T_6340 | _T_6345; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_6356 = _T_4631 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_6357 = perr_ic_index_ff == 6'h28; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_6359 = _T_6357 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_6361 = _T_6359 & tag_valid_clken_1[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_6362 = _T_6356 | _T_6361; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_6372 = _T_4635 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_6373 = perr_ic_index_ff == 6'h29; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_6375 = _T_6373 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_6377 = _T_6375 & tag_valid_clken_1[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_6378 = _T_6372 | _T_6377; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_6388 = _T_4639 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_6389 = perr_ic_index_ff == 6'h2a; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_6391 = _T_6389 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_6393 = _T_6391 & tag_valid_clken_1[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_6394 = _T_6388 | _T_6393; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_6404 = _T_4643 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_6405 = perr_ic_index_ff == 6'h2b; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_6407 = _T_6405 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_6409 = _T_6407 & tag_valid_clken_1[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_6410 = _T_6404 | _T_6409; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_6420 = _T_4647 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_6421 = perr_ic_index_ff == 6'h2c; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_6423 = _T_6421 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_6425 = _T_6423 & tag_valid_clken_1[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_6426 = _T_6420 | _T_6425; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_6436 = _T_4651 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_6437 = perr_ic_index_ff == 6'h2d; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_6439 = _T_6437 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_6441 = _T_6439 & tag_valid_clken_1[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_6442 = _T_6436 | _T_6441; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_6452 = _T_4655 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_6453 = perr_ic_index_ff == 6'h2e; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_6455 = _T_6453 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_6457 = _T_6455 & tag_valid_clken_1[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_6458 = _T_6452 | _T_6457; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_6468 = _T_4659 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_6469 = perr_ic_index_ff == 6'h2f; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_6471 = _T_6469 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_6473 = _T_6471 & tag_valid_clken_1[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_6474 = _T_6468 | _T_6473; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_6484 = _T_4663 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_6485 = perr_ic_index_ff == 6'h30; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_6487 = _T_6485 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_6489 = _T_6487 & tag_valid_clken_1[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_6490 = _T_6484 | _T_6489; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_6500 = _T_4667 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_6501 = perr_ic_index_ff == 6'h31; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_6503 = _T_6501 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_6505 = _T_6503 & tag_valid_clken_1[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_6506 = _T_6500 | _T_6505; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_6516 = _T_4671 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_6517 = perr_ic_index_ff == 6'h32; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_6519 = _T_6517 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_6521 = _T_6519 & tag_valid_clken_1[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_6522 = _T_6516 | _T_6521; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_6532 = _T_4675 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_6533 = perr_ic_index_ff == 6'h33; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_6535 = _T_6533 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_6537 = _T_6535 & tag_valid_clken_1[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_6538 = _T_6532 | _T_6537; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_6548 = _T_4679 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_6549 = perr_ic_index_ff == 6'h34; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_6551 = _T_6549 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_6553 = _T_6551 & tag_valid_clken_1[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_6554 = _T_6548 | _T_6553; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_6564 = _T_4683 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_6565 = perr_ic_index_ff == 6'h35; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_6567 = _T_6565 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_6569 = _T_6567 & tag_valid_clken_1[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_6570 = _T_6564 | _T_6569; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_6580 = _T_4687 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_6581 = perr_ic_index_ff == 6'h36; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_6583 = _T_6581 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_6585 = _T_6583 & tag_valid_clken_1[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_6586 = _T_6580 | _T_6585; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_6596 = _T_4691 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_6597 = perr_ic_index_ff == 6'h37; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_6599 = _T_6597 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_6601 = _T_6599 & tag_valid_clken_1[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_6602 = _T_6596 | _T_6601; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_6612 = _T_4695 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_6613 = perr_ic_index_ff == 6'h38; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_6615 = _T_6613 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_6617 = _T_6615 & tag_valid_clken_1[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_6618 = _T_6612 | _T_6617; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_6628 = _T_4699 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_6629 = perr_ic_index_ff == 6'h39; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_6631 = _T_6629 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_6633 = _T_6631 & tag_valid_clken_1[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_6634 = _T_6628 | _T_6633; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_6644 = _T_4703 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_6645 = perr_ic_index_ff == 6'h3a; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_6647 = _T_6645 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_6649 = _T_6647 & tag_valid_clken_1[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_6650 = _T_6644 | _T_6649; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_6660 = _T_4707 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_6661 = perr_ic_index_ff == 6'h3b; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_6663 = _T_6661 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_6665 = _T_6663 & tag_valid_clken_1[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_6666 = _T_6660 | _T_6665; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_6676 = _T_4711 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_6677 = perr_ic_index_ff == 6'h3c; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_6679 = _T_6677 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_6681 = _T_6679 & tag_valid_clken_1[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_6682 = _T_6676 | _T_6681; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_6692 = _T_4715 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_6693 = perr_ic_index_ff == 6'h3d; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_6695 = _T_6693 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_6697 = _T_6695 & tag_valid_clken_1[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_6698 = _T_6692 | _T_6697; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_6708 = _T_4719 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_6709 = perr_ic_index_ff == 6'h3e; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_6711 = _T_6709 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_6713 = _T_6711 & tag_valid_clken_1[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_6714 = _T_6708 | _T_6713; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_6724 = _T_4723 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_6725 = perr_ic_index_ff == 6'h3f; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_6727 = _T_6725 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_6729 = _T_6727 & tag_valid_clken_1[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_6730 = _T_6724 | _T_6729; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_6740 = _T_4599 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_6743 = _T_6229 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_6745 = _T_6743 & tag_valid_clken_1[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_6746 = _T_6740 | _T_6745; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_6756 = _T_4603 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_6759 = _T_6245 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_6761 = _T_6759 & tag_valid_clken_1[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_6762 = _T_6756 | _T_6761; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_6772 = _T_4607 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_6775 = _T_6261 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_6777 = _T_6775 & tag_valid_clken_1[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_6778 = _T_6772 | _T_6777; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_6788 = _T_4611 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_6791 = _T_6277 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_6793 = _T_6791 & tag_valid_clken_1[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_6794 = _T_6788 | _T_6793; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_6804 = _T_4615 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_6807 = _T_6293 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_6809 = _T_6807 & tag_valid_clken_1[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_6810 = _T_6804 | _T_6809; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_6820 = _T_4619 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_6823 = _T_6309 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_6825 = _T_6823 & tag_valid_clken_1[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_6826 = _T_6820 | _T_6825; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_6836 = _T_4623 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_6839 = _T_6325 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_6841 = _T_6839 & tag_valid_clken_1[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_6842 = _T_6836 | _T_6841; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_6852 = _T_4627 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_6855 = _T_6341 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_6857 = _T_6855 & tag_valid_clken_1[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_6858 = _T_6852 | _T_6857; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_6868 = _T_4631 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_6871 = _T_6357 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_6873 = _T_6871 & tag_valid_clken_1[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_6874 = _T_6868 | _T_6873; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_6884 = _T_4635 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_6887 = _T_6373 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_6889 = _T_6887 & tag_valid_clken_1[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_6890 = _T_6884 | _T_6889; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_6900 = _T_4639 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_6903 = _T_6389 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_6905 = _T_6903 & tag_valid_clken_1[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_6906 = _T_6900 | _T_6905; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_6916 = _T_4643 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_6919 = _T_6405 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_6921 = _T_6919 & tag_valid_clken_1[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_6922 = _T_6916 | _T_6921; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_6932 = _T_4647 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_6935 = _T_6421 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_6937 = _T_6935 & tag_valid_clken_1[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_6938 = _T_6932 | _T_6937; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_6948 = _T_4651 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_6951 = _T_6437 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_6953 = _T_6951 & tag_valid_clken_1[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_6954 = _T_6948 | _T_6953; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_6964 = _T_4655 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_6967 = _T_6453 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_6969 = _T_6967 & tag_valid_clken_1[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_6970 = _T_6964 | _T_6969; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_6980 = _T_4659 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_6983 = _T_6469 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_6985 = _T_6983 & tag_valid_clken_1[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_6986 = _T_6980 | _T_6985; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_6996 = _T_4663 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_6999 = _T_6485 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_7001 = _T_6999 & tag_valid_clken_1[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_7002 = _T_6996 | _T_7001; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_7012 = _T_4667 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_7015 = _T_6501 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_7017 = _T_7015 & tag_valid_clken_1[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_7018 = _T_7012 | _T_7017; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_7028 = _T_4671 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_7031 = _T_6517 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_7033 = _T_7031 & tag_valid_clken_1[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_7034 = _T_7028 | _T_7033; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_7044 = _T_4675 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_7047 = _T_6533 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_7049 = _T_7047 & tag_valid_clken_1[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_7050 = _T_7044 | _T_7049; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_7060 = _T_4679 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_7063 = _T_6549 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_7065 = _T_7063 & tag_valid_clken_1[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_7066 = _T_7060 | _T_7065; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_7076 = _T_4683 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_7079 = _T_6565 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_7081 = _T_7079 & tag_valid_clken_1[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_7082 = _T_7076 | _T_7081; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_7092 = _T_4687 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_7095 = _T_6581 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_7097 = _T_7095 & tag_valid_clken_1[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_7098 = _T_7092 | _T_7097; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_7108 = _T_4691 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_7111 = _T_6597 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_7113 = _T_7111 & tag_valid_clken_1[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_7114 = _T_7108 | _T_7113; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_7124 = _T_4695 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_7127 = _T_6613 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_7129 = _T_7127 & tag_valid_clken_1[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_7130 = _T_7124 | _T_7129; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_7140 = _T_4699 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_7143 = _T_6629 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_7145 = _T_7143 & tag_valid_clken_1[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_7146 = _T_7140 | _T_7145; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_7156 = _T_4703 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_7159 = _T_6645 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_7161 = _T_7159 & tag_valid_clken_1[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_7162 = _T_7156 | _T_7161; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_7172 = _T_4707 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_7175 = _T_6661 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_7177 = _T_7175 & tag_valid_clken_1[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_7178 = _T_7172 | _T_7177; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_7188 = _T_4711 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_7191 = _T_6677 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_7193 = _T_7191 & tag_valid_clken_1[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_7194 = _T_7188 | _T_7193; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_7204 = _T_4715 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_7207 = _T_6693 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_7209 = _T_7207 & tag_valid_clken_1[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_7210 = _T_7204 | _T_7209; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_7220 = _T_4719 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_7223 = _T_6709 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_7225 = _T_7223 & tag_valid_clken_1[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_7226 = _T_7220 | _T_7225; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_7236 = _T_4723 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_7239 = _T_6725 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_7241 = _T_7239 & tag_valid_clken_1[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_7242 = _T_7236 | _T_7241; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_7252 = _T_4727 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire [6:0] _GEN_796 = {{1'd0}, perr_ic_index_ff}; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_7253 = _GEN_796 == 7'h40; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_7255 = _T_7253 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_7257 = _T_7255 & tag_valid_clken_2[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_7258 = _T_7252 | _T_7257; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_7268 = _T_4731 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_7269 = _GEN_796 == 7'h41; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_7271 = _T_7269 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_7273 = _T_7271 & tag_valid_clken_2[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_7274 = _T_7268 | _T_7273; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_7284 = _T_4735 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_7285 = _GEN_796 == 7'h42; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_7287 = _T_7285 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_7289 = _T_7287 & tag_valid_clken_2[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_7290 = _T_7284 | _T_7289; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_7300 = _T_4739 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_7301 = _GEN_796 == 7'h43; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_7303 = _T_7301 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_7305 = _T_7303 & tag_valid_clken_2[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_7306 = _T_7300 | _T_7305; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_7316 = _T_4743 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_7317 = _GEN_796 == 7'h44; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_7319 = _T_7317 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_7321 = _T_7319 & tag_valid_clken_2[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_7322 = _T_7316 | _T_7321; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_7332 = _T_4747 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_7333 = _GEN_796 == 7'h45; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_7335 = _T_7333 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_7337 = _T_7335 & tag_valid_clken_2[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_7338 = _T_7332 | _T_7337; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_7348 = _T_4751 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_7349 = _GEN_796 == 7'h46; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_7351 = _T_7349 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_7353 = _T_7351 & tag_valid_clken_2[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_7354 = _T_7348 | _T_7353; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_7364 = _T_4755 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_7365 = _GEN_796 == 7'h47; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_7367 = _T_7365 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_7369 = _T_7367 & tag_valid_clken_2[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_7370 = _T_7364 | _T_7369; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_7380 = _T_4759 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_7381 = _GEN_796 == 7'h48; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_7383 = _T_7381 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_7385 = _T_7383 & tag_valid_clken_2[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_7386 = _T_7380 | _T_7385; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_7396 = _T_4763 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_7397 = _GEN_796 == 7'h49; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_7399 = _T_7397 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_7401 = _T_7399 & tag_valid_clken_2[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_7402 = _T_7396 | _T_7401; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_7412 = _T_4767 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_7413 = _GEN_796 == 7'h4a; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_7415 = _T_7413 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_7417 = _T_7415 & tag_valid_clken_2[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_7418 = _T_7412 | _T_7417; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_7428 = _T_4771 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_7429 = _GEN_796 == 7'h4b; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_7431 = _T_7429 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_7433 = _T_7431 & tag_valid_clken_2[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_7434 = _T_7428 | _T_7433; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_7444 = _T_4775 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_7445 = _GEN_796 == 7'h4c; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_7447 = _T_7445 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_7449 = _T_7447 & tag_valid_clken_2[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_7450 = _T_7444 | _T_7449; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_7460 = _T_4779 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_7461 = _GEN_796 == 7'h4d; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_7463 = _T_7461 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_7465 = _T_7463 & tag_valid_clken_2[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_7466 = _T_7460 | _T_7465; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_7476 = _T_4783 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_7477 = _GEN_796 == 7'h4e; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_7479 = _T_7477 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_7481 = _T_7479 & tag_valid_clken_2[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_7482 = _T_7476 | _T_7481; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_7492 = _T_4787 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_7493 = _GEN_796 == 7'h4f; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_7495 = _T_7493 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_7497 = _T_7495 & tag_valid_clken_2[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_7498 = _T_7492 | _T_7497; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_7508 = _T_4791 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_7509 = _GEN_796 == 7'h50; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_7511 = _T_7509 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_7513 = _T_7511 & tag_valid_clken_2[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_7514 = _T_7508 | _T_7513; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_7524 = _T_4795 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_7525 = _GEN_796 == 7'h51; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_7527 = _T_7525 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_7529 = _T_7527 & tag_valid_clken_2[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_7530 = _T_7524 | _T_7529; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_7540 = _T_4799 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_7541 = _GEN_796 == 7'h52; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_7543 = _T_7541 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_7545 = _T_7543 & tag_valid_clken_2[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_7546 = _T_7540 | _T_7545; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_7556 = _T_4803 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_7557 = _GEN_796 == 7'h53; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_7559 = _T_7557 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_7561 = _T_7559 & tag_valid_clken_2[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_7562 = _T_7556 | _T_7561; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_7572 = _T_4807 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_7573 = _GEN_796 == 7'h54; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_7575 = _T_7573 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_7577 = _T_7575 & tag_valid_clken_2[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_7578 = _T_7572 | _T_7577; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_7588 = _T_4811 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_7589 = _GEN_796 == 7'h55; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_7591 = _T_7589 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_7593 = _T_7591 & tag_valid_clken_2[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_7594 = _T_7588 | _T_7593; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_7604 = _T_4815 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_7605 = _GEN_796 == 7'h56; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_7607 = _T_7605 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_7609 = _T_7607 & tag_valid_clken_2[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_7610 = _T_7604 | _T_7609; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_7620 = _T_4819 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_7621 = _GEN_796 == 7'h57; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_7623 = _T_7621 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_7625 = _T_7623 & tag_valid_clken_2[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_7626 = _T_7620 | _T_7625; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_7636 = _T_4823 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_7637 = _GEN_796 == 7'h58; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_7639 = _T_7637 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_7641 = _T_7639 & tag_valid_clken_2[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_7642 = _T_7636 | _T_7641; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_7652 = _T_4827 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_7653 = _GEN_796 == 7'h59; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_7655 = _T_7653 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_7657 = _T_7655 & tag_valid_clken_2[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_7658 = _T_7652 | _T_7657; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_7668 = _T_4831 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_7669 = _GEN_796 == 7'h5a; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_7671 = _T_7669 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_7673 = _T_7671 & tag_valid_clken_2[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_7674 = _T_7668 | _T_7673; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_7684 = _T_4835 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_7685 = _GEN_796 == 7'h5b; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_7687 = _T_7685 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_7689 = _T_7687 & tag_valid_clken_2[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_7690 = _T_7684 | _T_7689; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_7700 = _T_4839 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_7701 = _GEN_796 == 7'h5c; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_7703 = _T_7701 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_7705 = _T_7703 & tag_valid_clken_2[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_7706 = _T_7700 | _T_7705; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_7716 = _T_4843 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_7717 = _GEN_796 == 7'h5d; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_7719 = _T_7717 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_7721 = _T_7719 & tag_valid_clken_2[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_7722 = _T_7716 | _T_7721; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_7732 = _T_4847 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_7733 = _GEN_796 == 7'h5e; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_7735 = _T_7733 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_7737 = _T_7735 & tag_valid_clken_2[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_7738 = _T_7732 | _T_7737; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_7748 = _T_4851 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_7749 = _GEN_796 == 7'h5f; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_7751 = _T_7749 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_7753 = _T_7751 & tag_valid_clken_2[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_7754 = _T_7748 | _T_7753; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_7764 = _T_4727 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_7767 = _T_7253 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_7769 = _T_7767 & tag_valid_clken_2[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_7770 = _T_7764 | _T_7769; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_7780 = _T_4731 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_7783 = _T_7269 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_7785 = _T_7783 & tag_valid_clken_2[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_7786 = _T_7780 | _T_7785; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_7796 = _T_4735 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_7799 = _T_7285 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_7801 = _T_7799 & tag_valid_clken_2[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_7802 = _T_7796 | _T_7801; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_7812 = _T_4739 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_7815 = _T_7301 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_7817 = _T_7815 & tag_valid_clken_2[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_7818 = _T_7812 | _T_7817; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_7828 = _T_4743 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_7831 = _T_7317 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_7833 = _T_7831 & tag_valid_clken_2[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_7834 = _T_7828 | _T_7833; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_7844 = _T_4747 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_7847 = _T_7333 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_7849 = _T_7847 & tag_valid_clken_2[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_7850 = _T_7844 | _T_7849; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_7860 = _T_4751 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_7863 = _T_7349 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_7865 = _T_7863 & tag_valid_clken_2[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_7866 = _T_7860 | _T_7865; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_7876 = _T_4755 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_7879 = _T_7365 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_7881 = _T_7879 & tag_valid_clken_2[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_7882 = _T_7876 | _T_7881; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_7892 = _T_4759 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_7895 = _T_7381 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_7897 = _T_7895 & tag_valid_clken_2[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_7898 = _T_7892 | _T_7897; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_7908 = _T_4763 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_7911 = _T_7397 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_7913 = _T_7911 & tag_valid_clken_2[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_7914 = _T_7908 | _T_7913; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_7924 = _T_4767 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_7927 = _T_7413 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_7929 = _T_7927 & tag_valid_clken_2[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_7930 = _T_7924 | _T_7929; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_7940 = _T_4771 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_7943 = _T_7429 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_7945 = _T_7943 & tag_valid_clken_2[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_7946 = _T_7940 | _T_7945; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_7956 = _T_4775 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_7959 = _T_7445 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_7961 = _T_7959 & tag_valid_clken_2[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_7962 = _T_7956 | _T_7961; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_7972 = _T_4779 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_7975 = _T_7461 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_7977 = _T_7975 & tag_valid_clken_2[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_7978 = _T_7972 | _T_7977; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_7988 = _T_4783 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_7991 = _T_7477 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_7993 = _T_7991 & tag_valid_clken_2[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_7994 = _T_7988 | _T_7993; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_8004 = _T_4787 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_8007 = _T_7493 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_8009 = _T_8007 & tag_valid_clken_2[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_8010 = _T_8004 | _T_8009; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_8020 = _T_4791 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_8023 = _T_7509 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_8025 = _T_8023 & tag_valid_clken_2[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_8026 = _T_8020 | _T_8025; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_8036 = _T_4795 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_8039 = _T_7525 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_8041 = _T_8039 & tag_valid_clken_2[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_8042 = _T_8036 | _T_8041; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_8052 = _T_4799 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_8055 = _T_7541 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_8057 = _T_8055 & tag_valid_clken_2[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_8058 = _T_8052 | _T_8057; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_8068 = _T_4803 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_8071 = _T_7557 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_8073 = _T_8071 & tag_valid_clken_2[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_8074 = _T_8068 | _T_8073; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_8084 = _T_4807 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_8087 = _T_7573 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_8089 = _T_8087 & tag_valid_clken_2[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_8090 = _T_8084 | _T_8089; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_8100 = _T_4811 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_8103 = _T_7589 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_8105 = _T_8103 & tag_valid_clken_2[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_8106 = _T_8100 | _T_8105; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_8116 = _T_4815 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_8119 = _T_7605 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_8121 = _T_8119 & tag_valid_clken_2[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_8122 = _T_8116 | _T_8121; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_8132 = _T_4819 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_8135 = _T_7621 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_8137 = _T_8135 & tag_valid_clken_2[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_8138 = _T_8132 | _T_8137; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_8148 = _T_4823 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_8151 = _T_7637 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_8153 = _T_8151 & tag_valid_clken_2[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_8154 = _T_8148 | _T_8153; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_8164 = _T_4827 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_8167 = _T_7653 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_8169 = _T_8167 & tag_valid_clken_2[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_8170 = _T_8164 | _T_8169; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_8180 = _T_4831 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_8183 = _T_7669 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_8185 = _T_8183 & tag_valid_clken_2[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_8186 = _T_8180 | _T_8185; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_8196 = _T_4835 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_8199 = _T_7685 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_8201 = _T_8199 & tag_valid_clken_2[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_8202 = _T_8196 | _T_8201; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_8212 = _T_4839 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_8215 = _T_7701 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_8217 = _T_8215 & tag_valid_clken_2[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_8218 = _T_8212 | _T_8217; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_8228 = _T_4843 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_8231 = _T_7717 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_8233 = _T_8231 & tag_valid_clken_2[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_8234 = _T_8228 | _T_8233; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_8244 = _T_4847 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_8247 = _T_7733 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_8249 = _T_8247 & tag_valid_clken_2[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_8250 = _T_8244 | _T_8249; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_8260 = _T_4851 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_8263 = _T_7749 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_8265 = _T_8263 & tag_valid_clken_2[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_8266 = _T_8260 | _T_8265; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_8276 = _T_4855 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_8277 = _GEN_796 == 7'h60; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_8279 = _T_8277 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_8281 = _T_8279 & tag_valid_clken_3[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_8282 = _T_8276 | _T_8281; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_8292 = _T_4859 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_8293 = _GEN_796 == 7'h61; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_8295 = _T_8293 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_8297 = _T_8295 & tag_valid_clken_3[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_8298 = _T_8292 | _T_8297; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_8308 = _T_4863 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_8309 = _GEN_796 == 7'h62; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_8311 = _T_8309 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_8313 = _T_8311 & tag_valid_clken_3[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_8314 = _T_8308 | _T_8313; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_8324 = _T_4867 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_8325 = _GEN_796 == 7'h63; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_8327 = _T_8325 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_8329 = _T_8327 & tag_valid_clken_3[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_8330 = _T_8324 | _T_8329; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_8340 = _T_4871 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_8341 = _GEN_796 == 7'h64; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_8343 = _T_8341 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_8345 = _T_8343 & tag_valid_clken_3[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_8346 = _T_8340 | _T_8345; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_8356 = _T_4875 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_8357 = _GEN_796 == 7'h65; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_8359 = _T_8357 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_8361 = _T_8359 & tag_valid_clken_3[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_8362 = _T_8356 | _T_8361; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_8372 = _T_4879 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_8373 = _GEN_796 == 7'h66; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_8375 = _T_8373 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_8377 = _T_8375 & tag_valid_clken_3[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_8378 = _T_8372 | _T_8377; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_8388 = _T_4883 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_8389 = _GEN_796 == 7'h67; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_8391 = _T_8389 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_8393 = _T_8391 & tag_valid_clken_3[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_8394 = _T_8388 | _T_8393; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_8404 = _T_4887 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_8405 = _GEN_796 == 7'h68; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_8407 = _T_8405 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_8409 = _T_8407 & tag_valid_clken_3[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_8410 = _T_8404 | _T_8409; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_8420 = _T_4891 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_8421 = _GEN_796 == 7'h69; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_8423 = _T_8421 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_8425 = _T_8423 & tag_valid_clken_3[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_8426 = _T_8420 | _T_8425; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_8436 = _T_4895 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_8437 = _GEN_796 == 7'h6a; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_8439 = _T_8437 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_8441 = _T_8439 & tag_valid_clken_3[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_8442 = _T_8436 | _T_8441; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_8452 = _T_4899 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_8453 = _GEN_796 == 7'h6b; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_8455 = _T_8453 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_8457 = _T_8455 & tag_valid_clken_3[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_8458 = _T_8452 | _T_8457; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_8468 = _T_4903 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_8469 = _GEN_796 == 7'h6c; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_8471 = _T_8469 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_8473 = _T_8471 & tag_valid_clken_3[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_8474 = _T_8468 | _T_8473; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_8484 = _T_4907 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_8485 = _GEN_796 == 7'h6d; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_8487 = _T_8485 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_8489 = _T_8487 & tag_valid_clken_3[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_8490 = _T_8484 | _T_8489; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_8500 = _T_4911 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_8501 = _GEN_796 == 7'h6e; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_8503 = _T_8501 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_8505 = _T_8503 & tag_valid_clken_3[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_8506 = _T_8500 | _T_8505; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_8516 = _T_4915 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_8517 = _GEN_796 == 7'h6f; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_8519 = _T_8517 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_8521 = _T_8519 & tag_valid_clken_3[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_8522 = _T_8516 | _T_8521; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_8532 = _T_4919 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_8533 = _GEN_796 == 7'h70; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_8535 = _T_8533 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_8537 = _T_8535 & tag_valid_clken_3[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_8538 = _T_8532 | _T_8537; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_8548 = _T_4923 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_8549 = _GEN_796 == 7'h71; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_8551 = _T_8549 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_8553 = _T_8551 & tag_valid_clken_3[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_8554 = _T_8548 | _T_8553; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_8564 = _T_4927 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_8565 = _GEN_796 == 7'h72; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_8567 = _T_8565 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_8569 = _T_8567 & tag_valid_clken_3[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_8570 = _T_8564 | _T_8569; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_8580 = _T_4931 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_8581 = _GEN_796 == 7'h73; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_8583 = _T_8581 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_8585 = _T_8583 & tag_valid_clken_3[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_8586 = _T_8580 | _T_8585; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_8596 = _T_4935 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_8597 = _GEN_796 == 7'h74; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_8599 = _T_8597 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_8601 = _T_8599 & tag_valid_clken_3[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_8602 = _T_8596 | _T_8601; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_8612 = _T_4939 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_8613 = _GEN_796 == 7'h75; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_8615 = _T_8613 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_8617 = _T_8615 & tag_valid_clken_3[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_8618 = _T_8612 | _T_8617; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_8628 = _T_4943 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_8629 = _GEN_796 == 7'h76; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_8631 = _T_8629 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_8633 = _T_8631 & tag_valid_clken_3[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_8634 = _T_8628 | _T_8633; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_8644 = _T_4947 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_8645 = _GEN_796 == 7'h77; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_8647 = _T_8645 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_8649 = _T_8647 & tag_valid_clken_3[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_8650 = _T_8644 | _T_8649; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_8660 = _T_4951 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_8661 = _GEN_796 == 7'h78; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_8663 = _T_8661 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_8665 = _T_8663 & tag_valid_clken_3[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_8666 = _T_8660 | _T_8665; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_8676 = _T_4955 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_8677 = _GEN_796 == 7'h79; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_8679 = _T_8677 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_8681 = _T_8679 & tag_valid_clken_3[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_8682 = _T_8676 | _T_8681; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_8692 = _T_4959 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_8693 = _GEN_796 == 7'h7a; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_8695 = _T_8693 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_8697 = _T_8695 & tag_valid_clken_3[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_8698 = _T_8692 | _T_8697; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_8708 = _T_4963 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_8709 = _GEN_796 == 7'h7b; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_8711 = _T_8709 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_8713 = _T_8711 & tag_valid_clken_3[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_8714 = _T_8708 | _T_8713; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_8724 = _T_4967 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_8725 = _GEN_796 == 7'h7c; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_8727 = _T_8725 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_8729 = _T_8727 & tag_valid_clken_3[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_8730 = _T_8724 | _T_8729; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_8740 = _T_4971 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_8741 = _GEN_796 == 7'h7d; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_8743 = _T_8741 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_8745 = _T_8743 & tag_valid_clken_3[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_8746 = _T_8740 | _T_8745; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_8756 = _T_4975 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_8757 = _GEN_796 == 7'h7e; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_8759 = _T_8757 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_8761 = _T_8759 & tag_valid_clken_3[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_8762 = _T_8756 | _T_8761; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_8772 = _T_4979 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_8773 = _GEN_796 == 7'h7f; // @[el2_ifu_mem_ctl.scala 741:101] - wire _T_8775 = _T_8773 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_8777 = _T_8775 & tag_valid_clken_3[0]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_8778 = _T_8772 | _T_8777; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_8788 = _T_4855 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_8791 = _T_8277 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_8793 = _T_8791 & tag_valid_clken_3[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_8794 = _T_8788 | _T_8793; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_8804 = _T_4859 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_8807 = _T_8293 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_8809 = _T_8807 & tag_valid_clken_3[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_8810 = _T_8804 | _T_8809; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_8820 = _T_4863 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_8823 = _T_8309 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_8825 = _T_8823 & tag_valid_clken_3[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_8826 = _T_8820 | _T_8825; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_8836 = _T_4867 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_8839 = _T_8325 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_8841 = _T_8839 & tag_valid_clken_3[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_8842 = _T_8836 | _T_8841; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_8852 = _T_4871 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_8855 = _T_8341 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_8857 = _T_8855 & tag_valid_clken_3[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_8858 = _T_8852 | _T_8857; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_8868 = _T_4875 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_8871 = _T_8357 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_8873 = _T_8871 & tag_valid_clken_3[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_8874 = _T_8868 | _T_8873; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_8884 = _T_4879 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_8887 = _T_8373 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_8889 = _T_8887 & tag_valid_clken_3[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_8890 = _T_8884 | _T_8889; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_8900 = _T_4883 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_8903 = _T_8389 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_8905 = _T_8903 & tag_valid_clken_3[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_8906 = _T_8900 | _T_8905; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_8916 = _T_4887 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_8919 = _T_8405 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_8921 = _T_8919 & tag_valid_clken_3[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_8922 = _T_8916 | _T_8921; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_8932 = _T_4891 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_8935 = _T_8421 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_8937 = _T_8935 & tag_valid_clken_3[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_8938 = _T_8932 | _T_8937; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_8948 = _T_4895 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_8951 = _T_8437 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_8953 = _T_8951 & tag_valid_clken_3[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_8954 = _T_8948 | _T_8953; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_8964 = _T_4899 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_8967 = _T_8453 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_8969 = _T_8967 & tag_valid_clken_3[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_8970 = _T_8964 | _T_8969; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_8980 = _T_4903 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_8983 = _T_8469 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_8985 = _T_8983 & tag_valid_clken_3[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_8986 = _T_8980 | _T_8985; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_8996 = _T_4907 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_8999 = _T_8485 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_9001 = _T_8999 & tag_valid_clken_3[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_9002 = _T_8996 | _T_9001; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_9012 = _T_4911 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_9015 = _T_8501 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_9017 = _T_9015 & tag_valid_clken_3[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_9018 = _T_9012 | _T_9017; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_9028 = _T_4915 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_9031 = _T_8517 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_9033 = _T_9031 & tag_valid_clken_3[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_9034 = _T_9028 | _T_9033; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_9044 = _T_4919 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_9047 = _T_8533 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_9049 = _T_9047 & tag_valid_clken_3[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_9050 = _T_9044 | _T_9049; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_9060 = _T_4923 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_9063 = _T_8549 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_9065 = _T_9063 & tag_valid_clken_3[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_9066 = _T_9060 | _T_9065; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_9076 = _T_4927 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_9079 = _T_8565 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_9081 = _T_9079 & tag_valid_clken_3[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_9082 = _T_9076 | _T_9081; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_9092 = _T_4931 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_9095 = _T_8581 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_9097 = _T_9095 & tag_valid_clken_3[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_9098 = _T_9092 | _T_9097; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_9108 = _T_4935 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_9111 = _T_8597 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_9113 = _T_9111 & tag_valid_clken_3[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_9114 = _T_9108 | _T_9113; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_9124 = _T_4939 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_9127 = _T_8613 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_9129 = _T_9127 & tag_valid_clken_3[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_9130 = _T_9124 | _T_9129; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_9140 = _T_4943 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_9143 = _T_8629 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_9145 = _T_9143 & tag_valid_clken_3[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_9146 = _T_9140 | _T_9145; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_9156 = _T_4947 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_9159 = _T_8645 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_9161 = _T_9159 & tag_valid_clken_3[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_9162 = _T_9156 | _T_9161; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_9172 = _T_4951 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_9175 = _T_8661 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_9177 = _T_9175 & tag_valid_clken_3[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_9178 = _T_9172 | _T_9177; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_9188 = _T_4955 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_9191 = _T_8677 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_9193 = _T_9191 & tag_valid_clken_3[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_9194 = _T_9188 | _T_9193; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_9204 = _T_4959 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_9207 = _T_8693 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_9209 = _T_9207 & tag_valid_clken_3[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_9210 = _T_9204 | _T_9209; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_9220 = _T_4963 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_9223 = _T_8709 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_9225 = _T_9223 & tag_valid_clken_3[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_9226 = _T_9220 | _T_9225; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_9236 = _T_4967 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_9239 = _T_8725 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_9241 = _T_9239 & tag_valid_clken_3[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_9242 = _T_9236 | _T_9241; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_9252 = _T_4971 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_9255 = _T_8741 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_9257 = _T_9255 & tag_valid_clken_3[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_9258 = _T_9252 | _T_9257; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_9268 = _T_4975 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_9271 = _T_8757 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_9273 = _T_9271 & tag_valid_clken_3[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_9274 = _T_9268 | _T_9273; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_9284 = _T_4979 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:58] - wire _T_9287 = _T_8773 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 741:123] - wire _T_9289 = _T_9287 & tag_valid_clken_3[1]; // @[el2_ifu_mem_ctl.scala 741:144] - wire _T_9290 = _T_9284 | _T_9289; // @[el2_ifu_mem_ctl.scala 741:80] - wire _T_10091 = ~fetch_uncacheable_ff; // @[el2_ifu_mem_ctl.scala 795:63] - wire _T_10092 = _T_10091 & ifc_fetch_req_f; // @[el2_ifu_mem_ctl.scala 795:85] + wire _T_5199 = ic_valid_ff & _T_195; // @[el2_ifu_mem_ctl.scala 741:64] + wire _T_5200 = ~perr_sel_invalidate; // @[el2_ifu_mem_ctl.scala 741:91] + wire _T_5201 = _T_5199 & _T_5200; // @[el2_ifu_mem_ctl.scala 741:89] + wire _T_5204 = _T_4471 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_5205 = perr_ic_index_ff == 6'h0; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_5207 = _T_5205 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_5209 = _T_5207 & tag_valid_clken_0[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_5210 = _T_5204 | _T_5209; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_5220 = _T_4475 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_5221 = perr_ic_index_ff == 6'h1; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_5223 = _T_5221 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_5225 = _T_5223 & tag_valid_clken_0[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_5226 = _T_5220 | _T_5225; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_5236 = _T_4479 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_5237 = perr_ic_index_ff == 6'h2; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_5239 = _T_5237 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_5241 = _T_5239 & tag_valid_clken_0[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_5242 = _T_5236 | _T_5241; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_5252 = _T_4483 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_5253 = perr_ic_index_ff == 6'h3; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_5255 = _T_5253 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_5257 = _T_5255 & tag_valid_clken_0[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_5258 = _T_5252 | _T_5257; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_5268 = _T_4487 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_5269 = perr_ic_index_ff == 6'h4; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_5271 = _T_5269 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_5273 = _T_5271 & tag_valid_clken_0[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_5274 = _T_5268 | _T_5273; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_5284 = _T_4491 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_5285 = perr_ic_index_ff == 6'h5; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_5287 = _T_5285 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_5289 = _T_5287 & tag_valid_clken_0[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_5290 = _T_5284 | _T_5289; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_5300 = _T_4495 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_5301 = perr_ic_index_ff == 6'h6; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_5303 = _T_5301 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_5305 = _T_5303 & tag_valid_clken_0[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_5306 = _T_5300 | _T_5305; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_5316 = _T_4499 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_5317 = perr_ic_index_ff == 6'h7; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_5319 = _T_5317 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_5321 = _T_5319 & tag_valid_clken_0[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_5322 = _T_5316 | _T_5321; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_5332 = _T_4503 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_5333 = perr_ic_index_ff == 6'h8; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_5335 = _T_5333 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_5337 = _T_5335 & tag_valid_clken_0[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_5338 = _T_5332 | _T_5337; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_5348 = _T_4507 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_5349 = perr_ic_index_ff == 6'h9; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_5351 = _T_5349 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_5353 = _T_5351 & tag_valid_clken_0[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_5354 = _T_5348 | _T_5353; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_5364 = _T_4511 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_5365 = perr_ic_index_ff == 6'ha; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_5367 = _T_5365 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_5369 = _T_5367 & tag_valid_clken_0[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_5370 = _T_5364 | _T_5369; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_5380 = _T_4515 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_5381 = perr_ic_index_ff == 6'hb; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_5383 = _T_5381 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_5385 = _T_5383 & tag_valid_clken_0[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_5386 = _T_5380 | _T_5385; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_5396 = _T_4519 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_5397 = perr_ic_index_ff == 6'hc; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_5399 = _T_5397 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_5401 = _T_5399 & tag_valid_clken_0[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_5402 = _T_5396 | _T_5401; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_5412 = _T_4523 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_5413 = perr_ic_index_ff == 6'hd; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_5415 = _T_5413 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_5417 = _T_5415 & tag_valid_clken_0[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_5418 = _T_5412 | _T_5417; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_5428 = _T_4527 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_5429 = perr_ic_index_ff == 6'he; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_5431 = _T_5429 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_5433 = _T_5431 & tag_valid_clken_0[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_5434 = _T_5428 | _T_5433; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_5444 = _T_4531 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_5445 = perr_ic_index_ff == 6'hf; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_5447 = _T_5445 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_5449 = _T_5447 & tag_valid_clken_0[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_5450 = _T_5444 | _T_5449; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_5460 = _T_4535 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_5461 = perr_ic_index_ff == 6'h10; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_5463 = _T_5461 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_5465 = _T_5463 & tag_valid_clken_0[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_5466 = _T_5460 | _T_5465; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_5476 = _T_4539 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_5477 = perr_ic_index_ff == 6'h11; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_5479 = _T_5477 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_5481 = _T_5479 & tag_valid_clken_0[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_5482 = _T_5476 | _T_5481; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_5492 = _T_4543 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_5493 = perr_ic_index_ff == 6'h12; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_5495 = _T_5493 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_5497 = _T_5495 & tag_valid_clken_0[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_5498 = _T_5492 | _T_5497; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_5508 = _T_4547 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_5509 = perr_ic_index_ff == 6'h13; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_5511 = _T_5509 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_5513 = _T_5511 & tag_valid_clken_0[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_5514 = _T_5508 | _T_5513; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_5524 = _T_4551 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_5525 = perr_ic_index_ff == 6'h14; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_5527 = _T_5525 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_5529 = _T_5527 & tag_valid_clken_0[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_5530 = _T_5524 | _T_5529; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_5540 = _T_4555 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_5541 = perr_ic_index_ff == 6'h15; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_5543 = _T_5541 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_5545 = _T_5543 & tag_valid_clken_0[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_5546 = _T_5540 | _T_5545; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_5556 = _T_4559 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_5557 = perr_ic_index_ff == 6'h16; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_5559 = _T_5557 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_5561 = _T_5559 & tag_valid_clken_0[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_5562 = _T_5556 | _T_5561; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_5572 = _T_4563 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_5573 = perr_ic_index_ff == 6'h17; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_5575 = _T_5573 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_5577 = _T_5575 & tag_valid_clken_0[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_5578 = _T_5572 | _T_5577; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_5588 = _T_4567 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_5589 = perr_ic_index_ff == 6'h18; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_5591 = _T_5589 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_5593 = _T_5591 & tag_valid_clken_0[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_5594 = _T_5588 | _T_5593; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_5604 = _T_4571 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_5605 = perr_ic_index_ff == 6'h19; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_5607 = _T_5605 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_5609 = _T_5607 & tag_valid_clken_0[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_5610 = _T_5604 | _T_5609; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_5620 = _T_4575 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_5621 = perr_ic_index_ff == 6'h1a; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_5623 = _T_5621 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_5625 = _T_5623 & tag_valid_clken_0[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_5626 = _T_5620 | _T_5625; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_5636 = _T_4579 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_5637 = perr_ic_index_ff == 6'h1b; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_5639 = _T_5637 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_5641 = _T_5639 & tag_valid_clken_0[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_5642 = _T_5636 | _T_5641; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_5652 = _T_4583 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_5653 = perr_ic_index_ff == 6'h1c; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_5655 = _T_5653 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_5657 = _T_5655 & tag_valid_clken_0[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_5658 = _T_5652 | _T_5657; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_5668 = _T_4587 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_5669 = perr_ic_index_ff == 6'h1d; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_5671 = _T_5669 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_5673 = _T_5671 & tag_valid_clken_0[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_5674 = _T_5668 | _T_5673; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_5684 = _T_4591 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_5685 = perr_ic_index_ff == 6'h1e; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_5687 = _T_5685 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_5689 = _T_5687 & tag_valid_clken_0[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_5690 = _T_5684 | _T_5689; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_5700 = _T_4595 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_5701 = perr_ic_index_ff == 6'h1f; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_5703 = _T_5701 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_5705 = _T_5703 & tag_valid_clken_0[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_5706 = _T_5700 | _T_5705; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_5716 = _T_4471 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_5719 = _T_5205 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_5721 = _T_5719 & tag_valid_clken_0[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_5722 = _T_5716 | _T_5721; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_5732 = _T_4475 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_5735 = _T_5221 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_5737 = _T_5735 & tag_valid_clken_0[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_5738 = _T_5732 | _T_5737; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_5748 = _T_4479 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_5751 = _T_5237 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_5753 = _T_5751 & tag_valid_clken_0[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_5754 = _T_5748 | _T_5753; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_5764 = _T_4483 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_5767 = _T_5253 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_5769 = _T_5767 & tag_valid_clken_0[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_5770 = _T_5764 | _T_5769; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_5780 = _T_4487 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_5783 = _T_5269 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_5785 = _T_5783 & tag_valid_clken_0[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_5786 = _T_5780 | _T_5785; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_5796 = _T_4491 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_5799 = _T_5285 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_5801 = _T_5799 & tag_valid_clken_0[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_5802 = _T_5796 | _T_5801; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_5812 = _T_4495 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_5815 = _T_5301 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_5817 = _T_5815 & tag_valid_clken_0[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_5818 = _T_5812 | _T_5817; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_5828 = _T_4499 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_5831 = _T_5317 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_5833 = _T_5831 & tag_valid_clken_0[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_5834 = _T_5828 | _T_5833; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_5844 = _T_4503 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_5847 = _T_5333 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_5849 = _T_5847 & tag_valid_clken_0[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_5850 = _T_5844 | _T_5849; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_5860 = _T_4507 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_5863 = _T_5349 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_5865 = _T_5863 & tag_valid_clken_0[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_5866 = _T_5860 | _T_5865; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_5876 = _T_4511 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_5879 = _T_5365 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_5881 = _T_5879 & tag_valid_clken_0[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_5882 = _T_5876 | _T_5881; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_5892 = _T_4515 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_5895 = _T_5381 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_5897 = _T_5895 & tag_valid_clken_0[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_5898 = _T_5892 | _T_5897; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_5908 = _T_4519 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_5911 = _T_5397 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_5913 = _T_5911 & tag_valid_clken_0[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_5914 = _T_5908 | _T_5913; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_5924 = _T_4523 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_5927 = _T_5413 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_5929 = _T_5927 & tag_valid_clken_0[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_5930 = _T_5924 | _T_5929; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_5940 = _T_4527 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_5943 = _T_5429 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_5945 = _T_5943 & tag_valid_clken_0[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_5946 = _T_5940 | _T_5945; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_5956 = _T_4531 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_5959 = _T_5445 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_5961 = _T_5959 & tag_valid_clken_0[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_5962 = _T_5956 | _T_5961; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_5972 = _T_4535 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_5975 = _T_5461 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_5977 = _T_5975 & tag_valid_clken_0[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_5978 = _T_5972 | _T_5977; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_5988 = _T_4539 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_5991 = _T_5477 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_5993 = _T_5991 & tag_valid_clken_0[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_5994 = _T_5988 | _T_5993; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_6004 = _T_4543 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_6007 = _T_5493 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_6009 = _T_6007 & tag_valid_clken_0[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_6010 = _T_6004 | _T_6009; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_6020 = _T_4547 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_6023 = _T_5509 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_6025 = _T_6023 & tag_valid_clken_0[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_6026 = _T_6020 | _T_6025; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_6036 = _T_4551 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_6039 = _T_5525 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_6041 = _T_6039 & tag_valid_clken_0[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_6042 = _T_6036 | _T_6041; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_6052 = _T_4555 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_6055 = _T_5541 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_6057 = _T_6055 & tag_valid_clken_0[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_6058 = _T_6052 | _T_6057; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_6068 = _T_4559 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_6071 = _T_5557 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_6073 = _T_6071 & tag_valid_clken_0[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_6074 = _T_6068 | _T_6073; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_6084 = _T_4563 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_6087 = _T_5573 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_6089 = _T_6087 & tag_valid_clken_0[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_6090 = _T_6084 | _T_6089; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_6100 = _T_4567 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_6103 = _T_5589 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_6105 = _T_6103 & tag_valid_clken_0[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_6106 = _T_6100 | _T_6105; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_6116 = _T_4571 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_6119 = _T_5605 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_6121 = _T_6119 & tag_valid_clken_0[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_6122 = _T_6116 | _T_6121; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_6132 = _T_4575 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_6135 = _T_5621 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_6137 = _T_6135 & tag_valid_clken_0[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_6138 = _T_6132 | _T_6137; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_6148 = _T_4579 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_6151 = _T_5637 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_6153 = _T_6151 & tag_valid_clken_0[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_6154 = _T_6148 | _T_6153; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_6164 = _T_4583 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_6167 = _T_5653 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_6169 = _T_6167 & tag_valid_clken_0[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_6170 = _T_6164 | _T_6169; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_6180 = _T_4587 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_6183 = _T_5669 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_6185 = _T_6183 & tag_valid_clken_0[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_6186 = _T_6180 | _T_6185; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_6196 = _T_4591 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_6199 = _T_5685 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_6201 = _T_6199 & tag_valid_clken_0[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_6202 = _T_6196 | _T_6201; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_6212 = _T_4595 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_6215 = _T_5701 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_6217 = _T_6215 & tag_valid_clken_0[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_6218 = _T_6212 | _T_6217; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_6228 = _T_4599 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_6229 = perr_ic_index_ff == 6'h20; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_6231 = _T_6229 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_6233 = _T_6231 & tag_valid_clken_1[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_6234 = _T_6228 | _T_6233; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_6244 = _T_4603 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_6245 = perr_ic_index_ff == 6'h21; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_6247 = _T_6245 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_6249 = _T_6247 & tag_valid_clken_1[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_6250 = _T_6244 | _T_6249; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_6260 = _T_4607 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_6261 = perr_ic_index_ff == 6'h22; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_6263 = _T_6261 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_6265 = _T_6263 & tag_valid_clken_1[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_6266 = _T_6260 | _T_6265; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_6276 = _T_4611 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_6277 = perr_ic_index_ff == 6'h23; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_6279 = _T_6277 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_6281 = _T_6279 & tag_valid_clken_1[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_6282 = _T_6276 | _T_6281; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_6292 = _T_4615 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_6293 = perr_ic_index_ff == 6'h24; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_6295 = _T_6293 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_6297 = _T_6295 & tag_valid_clken_1[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_6298 = _T_6292 | _T_6297; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_6308 = _T_4619 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_6309 = perr_ic_index_ff == 6'h25; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_6311 = _T_6309 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_6313 = _T_6311 & tag_valid_clken_1[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_6314 = _T_6308 | _T_6313; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_6324 = _T_4623 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_6325 = perr_ic_index_ff == 6'h26; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_6327 = _T_6325 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_6329 = _T_6327 & tag_valid_clken_1[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_6330 = _T_6324 | _T_6329; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_6340 = _T_4627 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_6341 = perr_ic_index_ff == 6'h27; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_6343 = _T_6341 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_6345 = _T_6343 & tag_valid_clken_1[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_6346 = _T_6340 | _T_6345; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_6356 = _T_4631 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_6357 = perr_ic_index_ff == 6'h28; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_6359 = _T_6357 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_6361 = _T_6359 & tag_valid_clken_1[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_6362 = _T_6356 | _T_6361; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_6372 = _T_4635 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_6373 = perr_ic_index_ff == 6'h29; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_6375 = _T_6373 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_6377 = _T_6375 & tag_valid_clken_1[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_6378 = _T_6372 | _T_6377; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_6388 = _T_4639 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_6389 = perr_ic_index_ff == 6'h2a; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_6391 = _T_6389 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_6393 = _T_6391 & tag_valid_clken_1[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_6394 = _T_6388 | _T_6393; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_6404 = _T_4643 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_6405 = perr_ic_index_ff == 6'h2b; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_6407 = _T_6405 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_6409 = _T_6407 & tag_valid_clken_1[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_6410 = _T_6404 | _T_6409; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_6420 = _T_4647 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_6421 = perr_ic_index_ff == 6'h2c; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_6423 = _T_6421 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_6425 = _T_6423 & tag_valid_clken_1[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_6426 = _T_6420 | _T_6425; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_6436 = _T_4651 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_6437 = perr_ic_index_ff == 6'h2d; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_6439 = _T_6437 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_6441 = _T_6439 & tag_valid_clken_1[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_6442 = _T_6436 | _T_6441; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_6452 = _T_4655 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_6453 = perr_ic_index_ff == 6'h2e; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_6455 = _T_6453 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_6457 = _T_6455 & tag_valid_clken_1[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_6458 = _T_6452 | _T_6457; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_6468 = _T_4659 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_6469 = perr_ic_index_ff == 6'h2f; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_6471 = _T_6469 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_6473 = _T_6471 & tag_valid_clken_1[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_6474 = _T_6468 | _T_6473; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_6484 = _T_4663 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_6485 = perr_ic_index_ff == 6'h30; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_6487 = _T_6485 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_6489 = _T_6487 & tag_valid_clken_1[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_6490 = _T_6484 | _T_6489; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_6500 = _T_4667 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_6501 = perr_ic_index_ff == 6'h31; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_6503 = _T_6501 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_6505 = _T_6503 & tag_valid_clken_1[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_6506 = _T_6500 | _T_6505; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_6516 = _T_4671 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_6517 = perr_ic_index_ff == 6'h32; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_6519 = _T_6517 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_6521 = _T_6519 & tag_valid_clken_1[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_6522 = _T_6516 | _T_6521; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_6532 = _T_4675 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_6533 = perr_ic_index_ff == 6'h33; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_6535 = _T_6533 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_6537 = _T_6535 & tag_valid_clken_1[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_6538 = _T_6532 | _T_6537; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_6548 = _T_4679 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_6549 = perr_ic_index_ff == 6'h34; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_6551 = _T_6549 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_6553 = _T_6551 & tag_valid_clken_1[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_6554 = _T_6548 | _T_6553; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_6564 = _T_4683 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_6565 = perr_ic_index_ff == 6'h35; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_6567 = _T_6565 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_6569 = _T_6567 & tag_valid_clken_1[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_6570 = _T_6564 | _T_6569; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_6580 = _T_4687 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_6581 = perr_ic_index_ff == 6'h36; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_6583 = _T_6581 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_6585 = _T_6583 & tag_valid_clken_1[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_6586 = _T_6580 | _T_6585; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_6596 = _T_4691 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_6597 = perr_ic_index_ff == 6'h37; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_6599 = _T_6597 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_6601 = _T_6599 & tag_valid_clken_1[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_6602 = _T_6596 | _T_6601; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_6612 = _T_4695 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_6613 = perr_ic_index_ff == 6'h38; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_6615 = _T_6613 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_6617 = _T_6615 & tag_valid_clken_1[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_6618 = _T_6612 | _T_6617; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_6628 = _T_4699 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_6629 = perr_ic_index_ff == 6'h39; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_6631 = _T_6629 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_6633 = _T_6631 & tag_valid_clken_1[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_6634 = _T_6628 | _T_6633; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_6644 = _T_4703 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_6645 = perr_ic_index_ff == 6'h3a; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_6647 = _T_6645 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_6649 = _T_6647 & tag_valid_clken_1[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_6650 = _T_6644 | _T_6649; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_6660 = _T_4707 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_6661 = perr_ic_index_ff == 6'h3b; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_6663 = _T_6661 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_6665 = _T_6663 & tag_valid_clken_1[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_6666 = _T_6660 | _T_6665; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_6676 = _T_4711 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_6677 = perr_ic_index_ff == 6'h3c; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_6679 = _T_6677 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_6681 = _T_6679 & tag_valid_clken_1[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_6682 = _T_6676 | _T_6681; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_6692 = _T_4715 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_6693 = perr_ic_index_ff == 6'h3d; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_6695 = _T_6693 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_6697 = _T_6695 & tag_valid_clken_1[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_6698 = _T_6692 | _T_6697; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_6708 = _T_4719 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_6709 = perr_ic_index_ff == 6'h3e; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_6711 = _T_6709 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_6713 = _T_6711 & tag_valid_clken_1[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_6714 = _T_6708 | _T_6713; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_6724 = _T_4723 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_6725 = perr_ic_index_ff == 6'h3f; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_6727 = _T_6725 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_6729 = _T_6727 & tag_valid_clken_1[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_6730 = _T_6724 | _T_6729; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_6740 = _T_4599 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_6743 = _T_6229 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_6745 = _T_6743 & tag_valid_clken_1[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_6746 = _T_6740 | _T_6745; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_6756 = _T_4603 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_6759 = _T_6245 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_6761 = _T_6759 & tag_valid_clken_1[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_6762 = _T_6756 | _T_6761; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_6772 = _T_4607 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_6775 = _T_6261 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_6777 = _T_6775 & tag_valid_clken_1[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_6778 = _T_6772 | _T_6777; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_6788 = _T_4611 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_6791 = _T_6277 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_6793 = _T_6791 & tag_valid_clken_1[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_6794 = _T_6788 | _T_6793; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_6804 = _T_4615 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_6807 = _T_6293 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_6809 = _T_6807 & tag_valid_clken_1[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_6810 = _T_6804 | _T_6809; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_6820 = _T_4619 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_6823 = _T_6309 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_6825 = _T_6823 & tag_valid_clken_1[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_6826 = _T_6820 | _T_6825; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_6836 = _T_4623 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_6839 = _T_6325 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_6841 = _T_6839 & tag_valid_clken_1[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_6842 = _T_6836 | _T_6841; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_6852 = _T_4627 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_6855 = _T_6341 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_6857 = _T_6855 & tag_valid_clken_1[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_6858 = _T_6852 | _T_6857; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_6868 = _T_4631 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_6871 = _T_6357 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_6873 = _T_6871 & tag_valid_clken_1[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_6874 = _T_6868 | _T_6873; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_6884 = _T_4635 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_6887 = _T_6373 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_6889 = _T_6887 & tag_valid_clken_1[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_6890 = _T_6884 | _T_6889; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_6900 = _T_4639 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_6903 = _T_6389 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_6905 = _T_6903 & tag_valid_clken_1[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_6906 = _T_6900 | _T_6905; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_6916 = _T_4643 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_6919 = _T_6405 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_6921 = _T_6919 & tag_valid_clken_1[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_6922 = _T_6916 | _T_6921; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_6932 = _T_4647 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_6935 = _T_6421 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_6937 = _T_6935 & tag_valid_clken_1[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_6938 = _T_6932 | _T_6937; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_6948 = _T_4651 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_6951 = _T_6437 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_6953 = _T_6951 & tag_valid_clken_1[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_6954 = _T_6948 | _T_6953; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_6964 = _T_4655 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_6967 = _T_6453 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_6969 = _T_6967 & tag_valid_clken_1[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_6970 = _T_6964 | _T_6969; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_6980 = _T_4659 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_6983 = _T_6469 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_6985 = _T_6983 & tag_valid_clken_1[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_6986 = _T_6980 | _T_6985; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_6996 = _T_4663 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_6999 = _T_6485 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_7001 = _T_6999 & tag_valid_clken_1[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_7002 = _T_6996 | _T_7001; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_7012 = _T_4667 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_7015 = _T_6501 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_7017 = _T_7015 & tag_valid_clken_1[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_7018 = _T_7012 | _T_7017; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_7028 = _T_4671 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_7031 = _T_6517 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_7033 = _T_7031 & tag_valid_clken_1[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_7034 = _T_7028 | _T_7033; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_7044 = _T_4675 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_7047 = _T_6533 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_7049 = _T_7047 & tag_valid_clken_1[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_7050 = _T_7044 | _T_7049; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_7060 = _T_4679 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_7063 = _T_6549 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_7065 = _T_7063 & tag_valid_clken_1[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_7066 = _T_7060 | _T_7065; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_7076 = _T_4683 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_7079 = _T_6565 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_7081 = _T_7079 & tag_valid_clken_1[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_7082 = _T_7076 | _T_7081; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_7092 = _T_4687 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_7095 = _T_6581 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_7097 = _T_7095 & tag_valid_clken_1[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_7098 = _T_7092 | _T_7097; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_7108 = _T_4691 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_7111 = _T_6597 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_7113 = _T_7111 & tag_valid_clken_1[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_7114 = _T_7108 | _T_7113; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_7124 = _T_4695 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_7127 = _T_6613 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_7129 = _T_7127 & tag_valid_clken_1[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_7130 = _T_7124 | _T_7129; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_7140 = _T_4699 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_7143 = _T_6629 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_7145 = _T_7143 & tag_valid_clken_1[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_7146 = _T_7140 | _T_7145; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_7156 = _T_4703 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_7159 = _T_6645 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_7161 = _T_7159 & tag_valid_clken_1[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_7162 = _T_7156 | _T_7161; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_7172 = _T_4707 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_7175 = _T_6661 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_7177 = _T_7175 & tag_valid_clken_1[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_7178 = _T_7172 | _T_7177; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_7188 = _T_4711 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_7191 = _T_6677 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_7193 = _T_7191 & tag_valid_clken_1[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_7194 = _T_7188 | _T_7193; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_7204 = _T_4715 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_7207 = _T_6693 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_7209 = _T_7207 & tag_valid_clken_1[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_7210 = _T_7204 | _T_7209; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_7220 = _T_4719 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_7223 = _T_6709 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_7225 = _T_7223 & tag_valid_clken_1[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_7226 = _T_7220 | _T_7225; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_7236 = _T_4723 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_7239 = _T_6725 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_7241 = _T_7239 & tag_valid_clken_1[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_7242 = _T_7236 | _T_7241; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_7252 = _T_4727 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire [6:0] _GEN_796 = {{1'd0}, perr_ic_index_ff}; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_7253 = _GEN_796 == 7'h40; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_7255 = _T_7253 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_7257 = _T_7255 & tag_valid_clken_2[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_7258 = _T_7252 | _T_7257; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_7268 = _T_4731 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_7269 = _GEN_796 == 7'h41; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_7271 = _T_7269 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_7273 = _T_7271 & tag_valid_clken_2[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_7274 = _T_7268 | _T_7273; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_7284 = _T_4735 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_7285 = _GEN_796 == 7'h42; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_7287 = _T_7285 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_7289 = _T_7287 & tag_valid_clken_2[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_7290 = _T_7284 | _T_7289; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_7300 = _T_4739 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_7301 = _GEN_796 == 7'h43; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_7303 = _T_7301 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_7305 = _T_7303 & tag_valid_clken_2[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_7306 = _T_7300 | _T_7305; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_7316 = _T_4743 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_7317 = _GEN_796 == 7'h44; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_7319 = _T_7317 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_7321 = _T_7319 & tag_valid_clken_2[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_7322 = _T_7316 | _T_7321; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_7332 = _T_4747 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_7333 = _GEN_796 == 7'h45; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_7335 = _T_7333 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_7337 = _T_7335 & tag_valid_clken_2[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_7338 = _T_7332 | _T_7337; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_7348 = _T_4751 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_7349 = _GEN_796 == 7'h46; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_7351 = _T_7349 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_7353 = _T_7351 & tag_valid_clken_2[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_7354 = _T_7348 | _T_7353; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_7364 = _T_4755 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_7365 = _GEN_796 == 7'h47; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_7367 = _T_7365 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_7369 = _T_7367 & tag_valid_clken_2[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_7370 = _T_7364 | _T_7369; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_7380 = _T_4759 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_7381 = _GEN_796 == 7'h48; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_7383 = _T_7381 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_7385 = _T_7383 & tag_valid_clken_2[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_7386 = _T_7380 | _T_7385; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_7396 = _T_4763 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_7397 = _GEN_796 == 7'h49; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_7399 = _T_7397 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_7401 = _T_7399 & tag_valid_clken_2[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_7402 = _T_7396 | _T_7401; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_7412 = _T_4767 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_7413 = _GEN_796 == 7'h4a; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_7415 = _T_7413 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_7417 = _T_7415 & tag_valid_clken_2[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_7418 = _T_7412 | _T_7417; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_7428 = _T_4771 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_7429 = _GEN_796 == 7'h4b; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_7431 = _T_7429 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_7433 = _T_7431 & tag_valid_clken_2[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_7434 = _T_7428 | _T_7433; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_7444 = _T_4775 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_7445 = _GEN_796 == 7'h4c; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_7447 = _T_7445 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_7449 = _T_7447 & tag_valid_clken_2[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_7450 = _T_7444 | _T_7449; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_7460 = _T_4779 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_7461 = _GEN_796 == 7'h4d; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_7463 = _T_7461 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_7465 = _T_7463 & tag_valid_clken_2[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_7466 = _T_7460 | _T_7465; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_7476 = _T_4783 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_7477 = _GEN_796 == 7'h4e; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_7479 = _T_7477 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_7481 = _T_7479 & tag_valid_clken_2[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_7482 = _T_7476 | _T_7481; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_7492 = _T_4787 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_7493 = _GEN_796 == 7'h4f; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_7495 = _T_7493 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_7497 = _T_7495 & tag_valid_clken_2[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_7498 = _T_7492 | _T_7497; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_7508 = _T_4791 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_7509 = _GEN_796 == 7'h50; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_7511 = _T_7509 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_7513 = _T_7511 & tag_valid_clken_2[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_7514 = _T_7508 | _T_7513; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_7524 = _T_4795 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_7525 = _GEN_796 == 7'h51; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_7527 = _T_7525 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_7529 = _T_7527 & tag_valid_clken_2[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_7530 = _T_7524 | _T_7529; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_7540 = _T_4799 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_7541 = _GEN_796 == 7'h52; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_7543 = _T_7541 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_7545 = _T_7543 & tag_valid_clken_2[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_7546 = _T_7540 | _T_7545; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_7556 = _T_4803 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_7557 = _GEN_796 == 7'h53; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_7559 = _T_7557 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_7561 = _T_7559 & tag_valid_clken_2[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_7562 = _T_7556 | _T_7561; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_7572 = _T_4807 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_7573 = _GEN_796 == 7'h54; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_7575 = _T_7573 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_7577 = _T_7575 & tag_valid_clken_2[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_7578 = _T_7572 | _T_7577; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_7588 = _T_4811 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_7589 = _GEN_796 == 7'h55; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_7591 = _T_7589 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_7593 = _T_7591 & tag_valid_clken_2[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_7594 = _T_7588 | _T_7593; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_7604 = _T_4815 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_7605 = _GEN_796 == 7'h56; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_7607 = _T_7605 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_7609 = _T_7607 & tag_valid_clken_2[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_7610 = _T_7604 | _T_7609; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_7620 = _T_4819 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_7621 = _GEN_796 == 7'h57; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_7623 = _T_7621 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_7625 = _T_7623 & tag_valid_clken_2[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_7626 = _T_7620 | _T_7625; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_7636 = _T_4823 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_7637 = _GEN_796 == 7'h58; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_7639 = _T_7637 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_7641 = _T_7639 & tag_valid_clken_2[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_7642 = _T_7636 | _T_7641; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_7652 = _T_4827 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_7653 = _GEN_796 == 7'h59; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_7655 = _T_7653 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_7657 = _T_7655 & tag_valid_clken_2[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_7658 = _T_7652 | _T_7657; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_7668 = _T_4831 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_7669 = _GEN_796 == 7'h5a; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_7671 = _T_7669 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_7673 = _T_7671 & tag_valid_clken_2[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_7674 = _T_7668 | _T_7673; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_7684 = _T_4835 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_7685 = _GEN_796 == 7'h5b; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_7687 = _T_7685 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_7689 = _T_7687 & tag_valid_clken_2[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_7690 = _T_7684 | _T_7689; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_7700 = _T_4839 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_7701 = _GEN_796 == 7'h5c; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_7703 = _T_7701 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_7705 = _T_7703 & tag_valid_clken_2[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_7706 = _T_7700 | _T_7705; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_7716 = _T_4843 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_7717 = _GEN_796 == 7'h5d; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_7719 = _T_7717 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_7721 = _T_7719 & tag_valid_clken_2[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_7722 = _T_7716 | _T_7721; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_7732 = _T_4847 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_7733 = _GEN_796 == 7'h5e; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_7735 = _T_7733 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_7737 = _T_7735 & tag_valid_clken_2[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_7738 = _T_7732 | _T_7737; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_7748 = _T_4851 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_7749 = _GEN_796 == 7'h5f; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_7751 = _T_7749 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_7753 = _T_7751 & tag_valid_clken_2[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_7754 = _T_7748 | _T_7753; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_7764 = _T_4727 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_7767 = _T_7253 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_7769 = _T_7767 & tag_valid_clken_2[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_7770 = _T_7764 | _T_7769; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_7780 = _T_4731 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_7783 = _T_7269 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_7785 = _T_7783 & tag_valid_clken_2[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_7786 = _T_7780 | _T_7785; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_7796 = _T_4735 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_7799 = _T_7285 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_7801 = _T_7799 & tag_valid_clken_2[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_7802 = _T_7796 | _T_7801; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_7812 = _T_4739 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_7815 = _T_7301 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_7817 = _T_7815 & tag_valid_clken_2[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_7818 = _T_7812 | _T_7817; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_7828 = _T_4743 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_7831 = _T_7317 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_7833 = _T_7831 & tag_valid_clken_2[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_7834 = _T_7828 | _T_7833; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_7844 = _T_4747 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_7847 = _T_7333 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_7849 = _T_7847 & tag_valid_clken_2[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_7850 = _T_7844 | _T_7849; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_7860 = _T_4751 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_7863 = _T_7349 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_7865 = _T_7863 & tag_valid_clken_2[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_7866 = _T_7860 | _T_7865; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_7876 = _T_4755 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_7879 = _T_7365 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_7881 = _T_7879 & tag_valid_clken_2[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_7882 = _T_7876 | _T_7881; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_7892 = _T_4759 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_7895 = _T_7381 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_7897 = _T_7895 & tag_valid_clken_2[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_7898 = _T_7892 | _T_7897; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_7908 = _T_4763 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_7911 = _T_7397 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_7913 = _T_7911 & tag_valid_clken_2[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_7914 = _T_7908 | _T_7913; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_7924 = _T_4767 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_7927 = _T_7413 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_7929 = _T_7927 & tag_valid_clken_2[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_7930 = _T_7924 | _T_7929; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_7940 = _T_4771 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_7943 = _T_7429 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_7945 = _T_7943 & tag_valid_clken_2[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_7946 = _T_7940 | _T_7945; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_7956 = _T_4775 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_7959 = _T_7445 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_7961 = _T_7959 & tag_valid_clken_2[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_7962 = _T_7956 | _T_7961; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_7972 = _T_4779 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_7975 = _T_7461 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_7977 = _T_7975 & tag_valid_clken_2[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_7978 = _T_7972 | _T_7977; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_7988 = _T_4783 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_7991 = _T_7477 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_7993 = _T_7991 & tag_valid_clken_2[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_7994 = _T_7988 | _T_7993; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_8004 = _T_4787 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_8007 = _T_7493 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_8009 = _T_8007 & tag_valid_clken_2[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_8010 = _T_8004 | _T_8009; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_8020 = _T_4791 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_8023 = _T_7509 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_8025 = _T_8023 & tag_valid_clken_2[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_8026 = _T_8020 | _T_8025; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_8036 = _T_4795 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_8039 = _T_7525 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_8041 = _T_8039 & tag_valid_clken_2[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_8042 = _T_8036 | _T_8041; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_8052 = _T_4799 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_8055 = _T_7541 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_8057 = _T_8055 & tag_valid_clken_2[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_8058 = _T_8052 | _T_8057; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_8068 = _T_4803 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_8071 = _T_7557 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_8073 = _T_8071 & tag_valid_clken_2[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_8074 = _T_8068 | _T_8073; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_8084 = _T_4807 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_8087 = _T_7573 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_8089 = _T_8087 & tag_valid_clken_2[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_8090 = _T_8084 | _T_8089; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_8100 = _T_4811 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_8103 = _T_7589 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_8105 = _T_8103 & tag_valid_clken_2[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_8106 = _T_8100 | _T_8105; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_8116 = _T_4815 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_8119 = _T_7605 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_8121 = _T_8119 & tag_valid_clken_2[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_8122 = _T_8116 | _T_8121; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_8132 = _T_4819 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_8135 = _T_7621 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_8137 = _T_8135 & tag_valid_clken_2[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_8138 = _T_8132 | _T_8137; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_8148 = _T_4823 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_8151 = _T_7637 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_8153 = _T_8151 & tag_valid_clken_2[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_8154 = _T_8148 | _T_8153; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_8164 = _T_4827 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_8167 = _T_7653 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_8169 = _T_8167 & tag_valid_clken_2[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_8170 = _T_8164 | _T_8169; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_8180 = _T_4831 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_8183 = _T_7669 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_8185 = _T_8183 & tag_valid_clken_2[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_8186 = _T_8180 | _T_8185; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_8196 = _T_4835 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_8199 = _T_7685 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_8201 = _T_8199 & tag_valid_clken_2[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_8202 = _T_8196 | _T_8201; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_8212 = _T_4839 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_8215 = _T_7701 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_8217 = _T_8215 & tag_valid_clken_2[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_8218 = _T_8212 | _T_8217; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_8228 = _T_4843 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_8231 = _T_7717 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_8233 = _T_8231 & tag_valid_clken_2[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_8234 = _T_8228 | _T_8233; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_8244 = _T_4847 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_8247 = _T_7733 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_8249 = _T_8247 & tag_valid_clken_2[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_8250 = _T_8244 | _T_8249; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_8260 = _T_4851 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_8263 = _T_7749 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_8265 = _T_8263 & tag_valid_clken_2[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_8266 = _T_8260 | _T_8265; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_8276 = _T_4855 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_8277 = _GEN_796 == 7'h60; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_8279 = _T_8277 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_8281 = _T_8279 & tag_valid_clken_3[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_8282 = _T_8276 | _T_8281; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_8292 = _T_4859 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_8293 = _GEN_796 == 7'h61; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_8295 = _T_8293 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_8297 = _T_8295 & tag_valid_clken_3[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_8298 = _T_8292 | _T_8297; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_8308 = _T_4863 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_8309 = _GEN_796 == 7'h62; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_8311 = _T_8309 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_8313 = _T_8311 & tag_valid_clken_3[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_8314 = _T_8308 | _T_8313; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_8324 = _T_4867 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_8325 = _GEN_796 == 7'h63; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_8327 = _T_8325 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_8329 = _T_8327 & tag_valid_clken_3[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_8330 = _T_8324 | _T_8329; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_8340 = _T_4871 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_8341 = _GEN_796 == 7'h64; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_8343 = _T_8341 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_8345 = _T_8343 & tag_valid_clken_3[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_8346 = _T_8340 | _T_8345; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_8356 = _T_4875 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_8357 = _GEN_796 == 7'h65; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_8359 = _T_8357 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_8361 = _T_8359 & tag_valid_clken_3[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_8362 = _T_8356 | _T_8361; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_8372 = _T_4879 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_8373 = _GEN_796 == 7'h66; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_8375 = _T_8373 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_8377 = _T_8375 & tag_valid_clken_3[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_8378 = _T_8372 | _T_8377; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_8388 = _T_4883 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_8389 = _GEN_796 == 7'h67; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_8391 = _T_8389 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_8393 = _T_8391 & tag_valid_clken_3[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_8394 = _T_8388 | _T_8393; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_8404 = _T_4887 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_8405 = _GEN_796 == 7'h68; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_8407 = _T_8405 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_8409 = _T_8407 & tag_valid_clken_3[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_8410 = _T_8404 | _T_8409; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_8420 = _T_4891 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_8421 = _GEN_796 == 7'h69; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_8423 = _T_8421 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_8425 = _T_8423 & tag_valid_clken_3[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_8426 = _T_8420 | _T_8425; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_8436 = _T_4895 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_8437 = _GEN_796 == 7'h6a; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_8439 = _T_8437 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_8441 = _T_8439 & tag_valid_clken_3[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_8442 = _T_8436 | _T_8441; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_8452 = _T_4899 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_8453 = _GEN_796 == 7'h6b; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_8455 = _T_8453 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_8457 = _T_8455 & tag_valid_clken_3[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_8458 = _T_8452 | _T_8457; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_8468 = _T_4903 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_8469 = _GEN_796 == 7'h6c; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_8471 = _T_8469 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_8473 = _T_8471 & tag_valid_clken_3[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_8474 = _T_8468 | _T_8473; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_8484 = _T_4907 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_8485 = _GEN_796 == 7'h6d; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_8487 = _T_8485 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_8489 = _T_8487 & tag_valid_clken_3[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_8490 = _T_8484 | _T_8489; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_8500 = _T_4911 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_8501 = _GEN_796 == 7'h6e; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_8503 = _T_8501 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_8505 = _T_8503 & tag_valid_clken_3[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_8506 = _T_8500 | _T_8505; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_8516 = _T_4915 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_8517 = _GEN_796 == 7'h6f; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_8519 = _T_8517 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_8521 = _T_8519 & tag_valid_clken_3[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_8522 = _T_8516 | _T_8521; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_8532 = _T_4919 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_8533 = _GEN_796 == 7'h70; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_8535 = _T_8533 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_8537 = _T_8535 & tag_valid_clken_3[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_8538 = _T_8532 | _T_8537; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_8548 = _T_4923 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_8549 = _GEN_796 == 7'h71; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_8551 = _T_8549 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_8553 = _T_8551 & tag_valid_clken_3[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_8554 = _T_8548 | _T_8553; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_8564 = _T_4927 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_8565 = _GEN_796 == 7'h72; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_8567 = _T_8565 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_8569 = _T_8567 & tag_valid_clken_3[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_8570 = _T_8564 | _T_8569; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_8580 = _T_4931 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_8581 = _GEN_796 == 7'h73; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_8583 = _T_8581 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_8585 = _T_8583 & tag_valid_clken_3[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_8586 = _T_8580 | _T_8585; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_8596 = _T_4935 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_8597 = _GEN_796 == 7'h74; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_8599 = _T_8597 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_8601 = _T_8599 & tag_valid_clken_3[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_8602 = _T_8596 | _T_8601; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_8612 = _T_4939 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_8613 = _GEN_796 == 7'h75; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_8615 = _T_8613 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_8617 = _T_8615 & tag_valid_clken_3[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_8618 = _T_8612 | _T_8617; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_8628 = _T_4943 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_8629 = _GEN_796 == 7'h76; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_8631 = _T_8629 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_8633 = _T_8631 & tag_valid_clken_3[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_8634 = _T_8628 | _T_8633; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_8644 = _T_4947 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_8645 = _GEN_796 == 7'h77; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_8647 = _T_8645 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_8649 = _T_8647 & tag_valid_clken_3[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_8650 = _T_8644 | _T_8649; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_8660 = _T_4951 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_8661 = _GEN_796 == 7'h78; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_8663 = _T_8661 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_8665 = _T_8663 & tag_valid_clken_3[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_8666 = _T_8660 | _T_8665; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_8676 = _T_4955 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_8677 = _GEN_796 == 7'h79; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_8679 = _T_8677 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_8681 = _T_8679 & tag_valid_clken_3[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_8682 = _T_8676 | _T_8681; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_8692 = _T_4959 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_8693 = _GEN_796 == 7'h7a; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_8695 = _T_8693 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_8697 = _T_8695 & tag_valid_clken_3[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_8698 = _T_8692 | _T_8697; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_8708 = _T_4963 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_8709 = _GEN_796 == 7'h7b; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_8711 = _T_8709 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_8713 = _T_8711 & tag_valid_clken_3[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_8714 = _T_8708 | _T_8713; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_8724 = _T_4967 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_8725 = _GEN_796 == 7'h7c; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_8727 = _T_8725 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_8729 = _T_8727 & tag_valid_clken_3[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_8730 = _T_8724 | _T_8729; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_8740 = _T_4971 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_8741 = _GEN_796 == 7'h7d; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_8743 = _T_8741 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_8745 = _T_8743 & tag_valid_clken_3[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_8746 = _T_8740 | _T_8745; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_8756 = _T_4975 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_8757 = _GEN_796 == 7'h7e; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_8759 = _T_8757 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_8761 = _T_8759 & tag_valid_clken_3[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_8762 = _T_8756 | _T_8761; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_8772 = _T_4979 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_8773 = _GEN_796 == 7'h7f; // @[el2_ifu_mem_ctl.scala 742:101] + wire _T_8775 = _T_8773 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_8777 = _T_8775 & tag_valid_clken_3[0]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_8778 = _T_8772 | _T_8777; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_8788 = _T_4855 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_8791 = _T_8277 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_8793 = _T_8791 & tag_valid_clken_3[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_8794 = _T_8788 | _T_8793; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_8804 = _T_4859 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_8807 = _T_8293 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_8809 = _T_8807 & tag_valid_clken_3[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_8810 = _T_8804 | _T_8809; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_8820 = _T_4863 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_8823 = _T_8309 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_8825 = _T_8823 & tag_valid_clken_3[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_8826 = _T_8820 | _T_8825; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_8836 = _T_4867 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_8839 = _T_8325 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_8841 = _T_8839 & tag_valid_clken_3[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_8842 = _T_8836 | _T_8841; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_8852 = _T_4871 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_8855 = _T_8341 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_8857 = _T_8855 & tag_valid_clken_3[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_8858 = _T_8852 | _T_8857; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_8868 = _T_4875 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_8871 = _T_8357 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_8873 = _T_8871 & tag_valid_clken_3[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_8874 = _T_8868 | _T_8873; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_8884 = _T_4879 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_8887 = _T_8373 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_8889 = _T_8887 & tag_valid_clken_3[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_8890 = _T_8884 | _T_8889; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_8900 = _T_4883 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_8903 = _T_8389 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_8905 = _T_8903 & tag_valid_clken_3[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_8906 = _T_8900 | _T_8905; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_8916 = _T_4887 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_8919 = _T_8405 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_8921 = _T_8919 & tag_valid_clken_3[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_8922 = _T_8916 | _T_8921; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_8932 = _T_4891 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_8935 = _T_8421 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_8937 = _T_8935 & tag_valid_clken_3[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_8938 = _T_8932 | _T_8937; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_8948 = _T_4895 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_8951 = _T_8437 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_8953 = _T_8951 & tag_valid_clken_3[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_8954 = _T_8948 | _T_8953; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_8964 = _T_4899 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_8967 = _T_8453 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_8969 = _T_8967 & tag_valid_clken_3[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_8970 = _T_8964 | _T_8969; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_8980 = _T_4903 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_8983 = _T_8469 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_8985 = _T_8983 & tag_valid_clken_3[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_8986 = _T_8980 | _T_8985; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_8996 = _T_4907 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_8999 = _T_8485 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_9001 = _T_8999 & tag_valid_clken_3[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_9002 = _T_8996 | _T_9001; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_9012 = _T_4911 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_9015 = _T_8501 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_9017 = _T_9015 & tag_valid_clken_3[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_9018 = _T_9012 | _T_9017; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_9028 = _T_4915 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_9031 = _T_8517 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_9033 = _T_9031 & tag_valid_clken_3[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_9034 = _T_9028 | _T_9033; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_9044 = _T_4919 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_9047 = _T_8533 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_9049 = _T_9047 & tag_valid_clken_3[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_9050 = _T_9044 | _T_9049; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_9060 = _T_4923 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_9063 = _T_8549 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_9065 = _T_9063 & tag_valid_clken_3[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_9066 = _T_9060 | _T_9065; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_9076 = _T_4927 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_9079 = _T_8565 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_9081 = _T_9079 & tag_valid_clken_3[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_9082 = _T_9076 | _T_9081; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_9092 = _T_4931 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_9095 = _T_8581 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_9097 = _T_9095 & tag_valid_clken_3[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_9098 = _T_9092 | _T_9097; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_9108 = _T_4935 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_9111 = _T_8597 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_9113 = _T_9111 & tag_valid_clken_3[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_9114 = _T_9108 | _T_9113; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_9124 = _T_4939 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_9127 = _T_8613 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_9129 = _T_9127 & tag_valid_clken_3[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_9130 = _T_9124 | _T_9129; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_9140 = _T_4943 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_9143 = _T_8629 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_9145 = _T_9143 & tag_valid_clken_3[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_9146 = _T_9140 | _T_9145; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_9156 = _T_4947 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_9159 = _T_8645 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_9161 = _T_9159 & tag_valid_clken_3[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_9162 = _T_9156 | _T_9161; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_9172 = _T_4951 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_9175 = _T_8661 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_9177 = _T_9175 & tag_valid_clken_3[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_9178 = _T_9172 | _T_9177; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_9188 = _T_4955 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_9191 = _T_8677 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_9193 = _T_9191 & tag_valid_clken_3[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_9194 = _T_9188 | _T_9193; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_9204 = _T_4959 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_9207 = _T_8693 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_9209 = _T_9207 & tag_valid_clken_3[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_9210 = _T_9204 | _T_9209; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_9220 = _T_4963 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_9223 = _T_8709 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_9225 = _T_9223 & tag_valid_clken_3[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_9226 = _T_9220 | _T_9225; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_9236 = _T_4967 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_9239 = _T_8725 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_9241 = _T_9239 & tag_valid_clken_3[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_9242 = _T_9236 | _T_9241; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_9252 = _T_4971 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_9255 = _T_8741 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_9257 = _T_9255 & tag_valid_clken_3[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_9258 = _T_9252 | _T_9257; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_9268 = _T_4975 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_9271 = _T_8757 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_9273 = _T_9271 & tag_valid_clken_3[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_9274 = _T_9268 | _T_9273; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_9284 = _T_4979 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:58] + wire _T_9287 = _T_8773 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:123] + wire _T_9289 = _T_9287 & tag_valid_clken_3[1]; // @[el2_ifu_mem_ctl.scala 742:144] + wire _T_9290 = _T_9284 | _T_9289; // @[el2_ifu_mem_ctl.scala 742:80] + wire _T_10091 = ~fetch_uncacheable_ff; // @[el2_ifu_mem_ctl.scala 796:63] + wire _T_10092 = _T_10091 & ifc_fetch_req_f; // @[el2_ifu_mem_ctl.scala 796:85] wire [1:0] _T_10094 = _T_10092 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - reg _T_10101; // @[el2_ifu_mem_ctl.scala 800:57] - reg _T_10102; // @[el2_ifu_mem_ctl.scala 801:56] - reg _T_10103; // @[el2_ifu_mem_ctl.scala 802:59] - wire _T_10104 = ~ifu_bus_arready_ff; // @[el2_ifu_mem_ctl.scala 803:80] - wire _T_10105 = ifu_bus_arvalid_ff & _T_10104; // @[el2_ifu_mem_ctl.scala 803:78] - wire _T_10106 = _T_10105 & miss_pending; // @[el2_ifu_mem_ctl.scala 803:100] - reg _T_10107; // @[el2_ifu_mem_ctl.scala 803:58] - reg _T_10108; // @[el2_ifu_mem_ctl.scala 804:58] - wire _T_10111 = io_dec_tlu_ic_diag_pkt_icache_dicawics[15:14] == 2'h3; // @[el2_ifu_mem_ctl.scala 811:71] - wire _T_10113 = io_dec_tlu_ic_diag_pkt_icache_dicawics[15:14] == 2'h2; // @[el2_ifu_mem_ctl.scala 811:124] - wire _T_10115 = io_dec_tlu_ic_diag_pkt_icache_dicawics[15:14] == 2'h1; // @[el2_ifu_mem_ctl.scala 812:50] - wire _T_10117 = io_dec_tlu_ic_diag_pkt_icache_dicawics[15:14] == 2'h0; // @[el2_ifu_mem_ctl.scala 812:103] + reg _T_10101; // @[el2_ifu_mem_ctl.scala 801:57] + reg _T_10102; // @[el2_ifu_mem_ctl.scala 802:56] + reg _T_10103; // @[el2_ifu_mem_ctl.scala 803:59] + wire _T_10104 = ~ifu_bus_arready_ff; // @[el2_ifu_mem_ctl.scala 804:80] + wire _T_10105 = ifu_bus_arvalid_ff & _T_10104; // @[el2_ifu_mem_ctl.scala 804:78] + wire _T_10106 = _T_10105 & miss_pending; // @[el2_ifu_mem_ctl.scala 804:100] + reg _T_10107; // @[el2_ifu_mem_ctl.scala 804:58] + reg _T_10108; // @[el2_ifu_mem_ctl.scala 805:58] + wire _T_10111 = io_dec_tlu_ic_diag_pkt_icache_dicawics[15:14] == 2'h3; // @[el2_ifu_mem_ctl.scala 812:71] + wire _T_10113 = io_dec_tlu_ic_diag_pkt_icache_dicawics[15:14] == 2'h2; // @[el2_ifu_mem_ctl.scala 812:124] + wire _T_10115 = io_dec_tlu_ic_diag_pkt_icache_dicawics[15:14] == 2'h1; // @[el2_ifu_mem_ctl.scala 813:50] + wire _T_10117 = io_dec_tlu_ic_diag_pkt_icache_dicawics[15:14] == 2'h0; // @[el2_ifu_mem_ctl.scala 813:103] wire [3:0] _T_10120 = {_T_10111,_T_10113,_T_10115,_T_10117}; // @[Cat.scala 29:58] - wire ic_debug_ict_array_sel_in = io_ic_debug_rd_en & io_ic_debug_tag_array; // @[el2_ifu_mem_ctl.scala 814:53] + wire ic_debug_ict_array_sel_in = io_ic_debug_rd_en & io_ic_debug_tag_array; // @[el2_ifu_mem_ctl.scala 815:53] reg _T_10131; // @[Reg.scala 27:20] - assign io_ifu_miss_state_idle = miss_state == 3'h0; // @[el2_ifu_mem_ctl.scala 323:26] - assign io_ifu_ic_mb_empty = _T_326 | _T_231; // @[el2_ifu_mem_ctl.scala 322:22] + assign io_ifu_miss_state_idle = miss_state == 3'h0; // @[el2_ifu_mem_ctl.scala 324:26] + assign io_ifu_ic_mb_empty = _T_326 | _T_231; // @[el2_ifu_mem_ctl.scala 323:22] assign io_ic_dma_active = _T_11 | io_dec_tlu_flush_err_wb; // @[el2_ifu_mem_ctl.scala 187:20] - assign io_ic_write_stall = write_ic_16_bytes & _T_3926; // @[el2_ifu_mem_ctl.scala 691:21] - assign io_ifu_pmu_ic_miss = _T_10101; // @[el2_ifu_mem_ctl.scala 800:22] - assign io_ifu_pmu_ic_hit = _T_10102; // @[el2_ifu_mem_ctl.scala 801:21] - assign io_ifu_pmu_bus_error = _T_10103; // @[el2_ifu_mem_ctl.scala 802:24] - assign io_ifu_pmu_bus_busy = _T_10107; // @[el2_ifu_mem_ctl.scala 803:23] - assign io_ifu_pmu_bus_trxn = _T_10108; // @[el2_ifu_mem_ctl.scala 804:23] + assign io_ic_write_stall = write_ic_16_bytes & _T_3926; // @[el2_ifu_mem_ctl.scala 692:21] + assign io_ifu_pmu_ic_miss = _T_10101; // @[el2_ifu_mem_ctl.scala 801:22] + assign io_ifu_pmu_ic_hit = _T_10102; // @[el2_ifu_mem_ctl.scala 802:21] + assign io_ifu_pmu_bus_error = _T_10103; // @[el2_ifu_mem_ctl.scala 803:24] + assign io_ifu_pmu_bus_busy = _T_10107; // @[el2_ifu_mem_ctl.scala 804:23] + assign io_ifu_pmu_bus_trxn = _T_10108; // @[el2_ifu_mem_ctl.scala 805:23] assign io_ifu_axi_awvalid = 1'h0; // @[el2_ifu_mem_ctl.scala 138:22] assign io_ifu_axi_awid = 3'h0; // @[el2_ifu_mem_ctl.scala 137:19] assign io_ifu_axi_awaddr = 32'h0; // @[el2_ifu_mem_ctl.scala 132:21] @@ -4998,56 +4998,56 @@ module el2_ifu_mem_ctl( assign io_ifu_axi_wstrb = 8'h0; // @[el2_ifu_mem_ctl.scala 139:20] assign io_ifu_axi_wlast = 1'h0; // @[el2_ifu_mem_ctl.scala 148:20] assign io_ifu_axi_bready = 1'h0; // @[el2_ifu_mem_ctl.scala 143:21] - assign io_ifu_axi_arvalid = ifu_bus_cmd_valid; // @[el2_ifu_mem_ctl.scala 553:22] - assign io_ifu_axi_arid = bus_rd_addr_count & _T_2520; // @[el2_ifu_mem_ctl.scala 554:19] - assign io_ifu_axi_araddr = _T_2522 & _T_2524; // @[el2_ifu_mem_ctl.scala 555:21] - assign io_ifu_axi_arregion = ifu_ic_req_addr_f[28:25]; // @[el2_ifu_mem_ctl.scala 558:23] + assign io_ifu_axi_arvalid = ifu_bus_cmd_valid; // @[el2_ifu_mem_ctl.scala 554:22] + assign io_ifu_axi_arid = bus_rd_addr_count & _T_2520; // @[el2_ifu_mem_ctl.scala 555:19] + assign io_ifu_axi_araddr = _T_2522 & _T_2524; // @[el2_ifu_mem_ctl.scala 556:21] + assign io_ifu_axi_arregion = ifu_ic_req_addr_f[28:25]; // @[el2_ifu_mem_ctl.scala 559:23] assign io_ifu_axi_arlen = 8'h0; // @[el2_ifu_mem_ctl.scala 144:20] - assign io_ifu_axi_arsize = 3'h3; // @[el2_ifu_mem_ctl.scala 556:21] - assign io_ifu_axi_arburst = 2'h1; // @[el2_ifu_mem_ctl.scala 559:22] + assign io_ifu_axi_arsize = 3'h3; // @[el2_ifu_mem_ctl.scala 557:21] + assign io_ifu_axi_arburst = 2'h1; // @[el2_ifu_mem_ctl.scala 560:22] assign io_ifu_axi_arlock = 1'h0; // @[el2_ifu_mem_ctl.scala 135:21] - assign io_ifu_axi_arcache = 4'hf; // @[el2_ifu_mem_ctl.scala 557:22] + assign io_ifu_axi_arcache = 4'hf; // @[el2_ifu_mem_ctl.scala 558:22] assign io_ifu_axi_arprot = 3'h0; // @[el2_ifu_mem_ctl.scala 146:21] assign io_ifu_axi_arqos = 4'h0; // @[el2_ifu_mem_ctl.scala 141:20] - assign io_ifu_axi_rready = 1'h1; // @[el2_ifu_mem_ctl.scala 560:21] - assign io_iccm_dma_ecc_error = |iccm_double_ecc_error; // @[el2_ifu_mem_ctl.scala 650:25] - assign io_iccm_dma_rvalid = iccm_dma_rvalid; // @[el2_ifu_mem_ctl.scala 648:22] - assign io_iccm_dma_rdata = iccm_dma_rdata; // @[el2_ifu_mem_ctl.scala 652:21] - assign io_iccm_dma_rtag = iccm_dma_rtag; // @[el2_ifu_mem_ctl.scala 643:20] - assign io_iccm_ready = _T_2623 & _T_2617; // @[el2_ifu_mem_ctl.scala 623:17] - assign io_ic_rw_addr = _T_340 | _T_341; // @[el2_ifu_mem_ctl.scala 332:17] - assign io_ic_wr_en = 2'h0; // @[el2_ifu_mem_ctl.scala 690:15] - assign io_ic_rd_en = _T_3904 | _T_3909; // @[el2_ifu_mem_ctl.scala 681:15] - assign io_ic_wr_data_0 = ic_wr_16bytes_data[70:0]; // @[el2_ifu_mem_ctl.scala 339:17] - assign io_ic_wr_data_1 = ic_wr_16bytes_data[141:71]; // @[el2_ifu_mem_ctl.scala 339:17] - assign io_ic_debug_wr_data = io_dec_tlu_ic_diag_pkt_icache_wrdata; // @[el2_ifu_mem_ctl.scala 340:23] - assign io_ifu_ic_debug_rd_data = _T_1211; // @[el2_ifu_mem_ctl.scala 348:27] - assign io_ic_debug_addr = io_dec_tlu_ic_diag_pkt_icache_dicawics[9:0]; // @[el2_ifu_mem_ctl.scala 807:20] - assign io_ic_debug_rd_en = io_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[el2_ifu_mem_ctl.scala 809:21] - assign io_ic_debug_wr_en = io_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[el2_ifu_mem_ctl.scala 810:21] - assign io_ic_debug_tag_array = io_dec_tlu_ic_diag_pkt_icache_dicawics[16]; // @[el2_ifu_mem_ctl.scala 808:25] - assign io_ic_debug_way = _T_10120[1:0]; // @[el2_ifu_mem_ctl.scala 811:19] - assign io_ic_tag_valid = ic_tag_valid_unq & _T_10094; // @[el2_ifu_mem_ctl.scala 795:19] - assign io_iccm_rw_addr = _T_3058[14:0]; // @[el2_ifu_mem_ctl.scala 654:19] - assign io_iccm_wren = _T_2627 | iccm_correct_ecc; // @[el2_ifu_mem_ctl.scala 625:16] - assign io_iccm_rden = _T_2631 | _T_2632; // @[el2_ifu_mem_ctl.scala 626:16] - assign io_iccm_wr_data = _T_3033 ? _T_3034 : _T_3041; // @[el2_ifu_mem_ctl.scala 631:19] - assign io_iccm_wr_size = _T_2637 & io_dma_mem_sz; // @[el2_ifu_mem_ctl.scala 628:19] - assign io_ic_hit_f = _T_263 | _T_264; // @[el2_ifu_mem_ctl.scala 284:15] - assign io_ic_access_fault_f = _T_2405 & _T_317; // @[el2_ifu_mem_ctl.scala 379:24] - assign io_ic_access_fault_type_f = io_iccm_rd_ecc_double_err ? 2'h1 : _T_1275; // @[el2_ifu_mem_ctl.scala 380:29] - assign io_iccm_rd_ecc_single_err = _T_3849 & ifc_fetch_req_f; // @[el2_ifu_mem_ctl.scala 667:29] - assign io_iccm_rd_ecc_double_err = iccm_dma_ecc_error_in & ifc_iccm_access_f; // @[el2_ifu_mem_ctl.scala 668:29] - assign io_ic_error_start = _T_1199 | ic_rd_parity_final_err; // @[el2_ifu_mem_ctl.scala 342:21] + assign io_ifu_axi_rready = 1'h1; // @[el2_ifu_mem_ctl.scala 561:21] + assign io_iccm_dma_ecc_error = |iccm_double_ecc_error; // @[el2_ifu_mem_ctl.scala 651:25] + assign io_iccm_dma_rvalid = iccm_dma_rvalid; // @[el2_ifu_mem_ctl.scala 649:22] + assign io_iccm_dma_rdata = iccm_dma_rdata; // @[el2_ifu_mem_ctl.scala 653:21] + assign io_iccm_dma_rtag = iccm_dma_rtag; // @[el2_ifu_mem_ctl.scala 644:20] + assign io_iccm_ready = _T_2623 & _T_2617; // @[el2_ifu_mem_ctl.scala 624:17] + assign io_ic_rw_addr = _T_340 | _T_341; // @[el2_ifu_mem_ctl.scala 333:17] + assign io_ic_wr_en = 2'h0; // @[el2_ifu_mem_ctl.scala 691:15] + assign io_ic_rd_en = _T_3904 | _T_3909; // @[el2_ifu_mem_ctl.scala 682:15] + assign io_ic_wr_data_0 = ic_wr_16bytes_data[70:0]; // @[el2_ifu_mem_ctl.scala 340:17] + assign io_ic_wr_data_1 = ic_wr_16bytes_data[141:71]; // @[el2_ifu_mem_ctl.scala 340:17] + assign io_ic_debug_wr_data = io_dec_tlu_ic_diag_pkt_icache_wrdata; // @[el2_ifu_mem_ctl.scala 341:23] + assign io_ifu_ic_debug_rd_data = _T_1211; // @[el2_ifu_mem_ctl.scala 349:27] + assign io_ic_debug_addr = io_dec_tlu_ic_diag_pkt_icache_dicawics[9:0]; // @[el2_ifu_mem_ctl.scala 808:20] + assign io_ic_debug_rd_en = io_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[el2_ifu_mem_ctl.scala 810:21] + assign io_ic_debug_wr_en = io_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[el2_ifu_mem_ctl.scala 811:21] + assign io_ic_debug_tag_array = io_dec_tlu_ic_diag_pkt_icache_dicawics[16]; // @[el2_ifu_mem_ctl.scala 809:25] + assign io_ic_debug_way = _T_10120[1:0]; // @[el2_ifu_mem_ctl.scala 812:19] + assign io_ic_tag_valid = ic_tag_valid_unq & _T_10094; // @[el2_ifu_mem_ctl.scala 796:19] + assign io_iccm_rw_addr = _T_3058[14:0]; // @[el2_ifu_mem_ctl.scala 655:19] + assign io_iccm_wren = _T_2627 | iccm_correct_ecc; // @[el2_ifu_mem_ctl.scala 626:16] + assign io_iccm_rden = _T_2631 | _T_2632; // @[el2_ifu_mem_ctl.scala 627:16] + assign io_iccm_wr_data = _T_3033 ? _T_3034 : _T_3041; // @[el2_ifu_mem_ctl.scala 632:19] + assign io_iccm_wr_size = _T_2637 & io_dma_mem_sz; // @[el2_ifu_mem_ctl.scala 629:19] + assign io_ic_hit_f = _T_263 | _T_264; // @[el2_ifu_mem_ctl.scala 285:15] + assign io_ic_access_fault_f = _T_2405 & _T_317; // @[el2_ifu_mem_ctl.scala 380:24] + assign io_ic_access_fault_type_f = io_iccm_rd_ecc_double_err ? 2'h1 : _T_1275; // @[el2_ifu_mem_ctl.scala 381:29] + assign io_iccm_rd_ecc_single_err = _T_3849 & ifc_fetch_req_f; // @[el2_ifu_mem_ctl.scala 668:29] + assign io_iccm_rd_ecc_double_err = iccm_dma_ecc_error_in & ifc_iccm_access_f; // @[el2_ifu_mem_ctl.scala 669:29] + assign io_ic_error_start = _T_1199 | ic_rd_parity_final_err; // @[el2_ifu_mem_ctl.scala 343:21] assign io_ifu_async_error_start = io_iccm_rd_ecc_single_err | io_ic_error_start; // @[el2_ifu_mem_ctl.scala 186:28] assign io_iccm_dma_sb_error = _T_3 & dma_iccm_req_f; // @[el2_ifu_mem_ctl.scala 185:24] - assign io_ic_fetch_val_f = {1'h0,fetch_req_f_qual}; // @[el2_ifu_mem_ctl.scala 384:21] - assign io_ic_data_f = io_ic_rd_data[31:0]; // @[el2_ifu_mem_ctl.scala 376:16] - assign io_ic_premux_data = ic_premux_data[63:0]; // @[el2_ifu_mem_ctl.scala 373:21] - assign io_ic_sel_premux_data = fetch_req_iccm_f | sel_byp_data; // @[el2_ifu_mem_ctl.scala 374:25] - assign io_ifu_ic_debug_rd_data_valid = _T_10131; // @[el2_ifu_mem_ctl.scala 818:33] - assign io_iccm_buf_correct_ecc = iccm_correct_ecc & _T_2410; // @[el2_ifu_mem_ctl.scala 472:27] - assign io_iccm_correction_state = _T_2438 ? 1'h0 : _GEN_59; // @[el2_ifu_mem_ctl.scala 507:28 el2_ifu_mem_ctl.scala 520:32 el2_ifu_mem_ctl.scala 527:32 el2_ifu_mem_ctl.scala 534:32] + assign io_ic_fetch_val_f = {1'h0,fetch_req_f_qual}; // @[el2_ifu_mem_ctl.scala 385:21] + assign io_ic_data_f = io_ic_rd_data[31:0]; // @[el2_ifu_mem_ctl.scala 377:16] + assign io_ic_premux_data = ic_premux_data[63:0]; // @[el2_ifu_mem_ctl.scala 374:21] + assign io_ic_sel_premux_data = fetch_req_iccm_f | sel_byp_data; // @[el2_ifu_mem_ctl.scala 375:25] + assign io_ifu_ic_debug_rd_data_valid = _T_10131; // @[el2_ifu_mem_ctl.scala 819:33] + assign io_iccm_buf_correct_ecc = iccm_correct_ecc & _T_2410; // @[el2_ifu_mem_ctl.scala 473:27] + assign io_iccm_correction_state = _T_2438 ? 1'h0 : _GEN_59; // @[el2_ifu_mem_ctl.scala 508:28 el2_ifu_mem_ctl.scala 521:32 el2_ifu_mem_ctl.scala 528:32 el2_ifu_mem_ctl.scala 535:32] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif diff --git a/src/main/scala/ifu/el2_ifu_mem_ctl.scala b/src/main/scala/ifu/el2_ifu_mem_ctl.scala index 0e4fbdf9..b4662c5b 100644 --- a/src/main/scala/ifu/el2_ifu_mem_ctl.scala +++ b/src/main/scala/ifu/el2_ifu_mem_ctl.scala @@ -185,7 +185,8 @@ class el2_ifu_mem_ctl extends Module with el2_lib { io.iccm_dma_sb_error := iccm_single_ecc_error.orR() & dma_iccm_req_f.asBool() io.ifu_async_error_start := io.iccm_rd_ecc_single_err | io.ic_error_start io.ic_dma_active := iccm_correct_ecc | (perr_state === dma_sb_err_C) | (err_stop_state === err_stop_fetch_C) | err_stop_fetch | io.dec_tlu_flush_err_wb - val scnd_miss_req_in = ifu_bus_rsp_valid & bus_ifu_bus_clk_en & ifu_bus_rsp_ready & bus_new_data_beat_count.andR & + + val scnd_miss_req_in = ifu_bus_rsp_valid & bus_ifu_bus_clk_en & ifu_bus_rsp_ready & (bus_new_data_beat_count.andR) & !uncacheable_miss_ff & ((miss_state === scnd_miss_C)|(miss_nxtstate === scnd_miss_C)) & !io.exu_flush_final val ifu_bp_hit_taken_q_f = io.ifu_bp_hit_taken_f & io.ic_hit_f @@ -325,7 +326,7 @@ class el2_ifu_mem_ctl extends Module with el2_lib { val reset_tag_valid_for_miss = WireInit(Bool(), false.B) val sel_mb_addr = (miss_pending & write_ic_16_bytes & !uncacheable_miss_ff) | reset_tag_valid_for_miss val ifu_ic_rw_int_addr = Mux1H(Seq(sel_mb_addr.asBool->Cat(imb_ff(30,ICACHE_BEAT_ADDR_HI) , ic_wr_addr_bits_hi_3 , imb_ff(1,0)), - !sel_mb_addr.asBool->ifu_fetch_addr_int_f)) + !sel_mb_addr.asBool->io.ifc_fetch_addr_bf)) val bus_ifu_wr_en_ff_q = WireInit(Bool(), false.B) val sel_mb_status_addr = miss_pending & write_ic_16_bytes & !uncacheable_miss_ff & last_beat & bus_ifu_wr_en_ff_q val ifu_status_wr_addr = Mux(sel_mb_status_addr, Cat(imb_ff(30, ICACHE_BEAT_ADDR_HI),ic_wr_addr_bits_hi_3, imb_ff(1,0)), ifu_fetch_addr_int_f) diff --git a/target/scala-2.12/classes/ifu/el2_ifu_mem_ctl.class b/target/scala-2.12/classes/ifu/el2_ifu_mem_ctl.class index 2eb8148b..ba7cb887 100644 Binary files a/target/scala-2.12/classes/ifu/el2_ifu_mem_ctl.class and b/target/scala-2.12/classes/ifu/el2_ifu_mem_ctl.class differ diff --git a/target/scala-2.12/classes/ifu/ifu_mem$.class b/target/scala-2.12/classes/ifu/ifu_mem$.class index 4cac2a57..59fcf7fb 100644 Binary files a/target/scala-2.12/classes/ifu/ifu_mem$.class and b/target/scala-2.12/classes/ifu/ifu_mem$.class differ diff --git a/target/scala-2.12/classes/ifu/ifu_mem$delayedInit$body.class b/target/scala-2.12/classes/ifu/ifu_mem$delayedInit$body.class index ff2a81dd..d9a1f395 100644 Binary files a/target/scala-2.12/classes/ifu/ifu_mem$delayedInit$body.class and b/target/scala-2.12/classes/ifu/ifu_mem$delayedInit$body.class differ