diff --git a/el2_ifu_mem_ctl.fir b/el2_ifu_mem_ctl.fir
index b4c6ade4..7749e390 100644
--- a/el2_ifu_mem_ctl.fir
+++ b/el2_ifu_mem_ctl.fir
@@ -2512,7 +2512,7 @@ circuit el2_ifu_mem_ctl :
       node _T_780 = or(ic_miss_buff_data_error_bypass, ic_miss_buff_data_error_bypass_inc) @[el2_ifu_mem_ctl.scala 451:70]
       ifu_byp_data_err_new <= _T_780 @[el2_ifu_mem_ctl.scala 451:36]
       skip @[el2_ifu_mem_ctl.scala 451:5]
-    node _T_781 = bits(ifu_fetch_addr_int_f, 0, 0) @[el2_ifu_mem_ctl.scala 453:59]
+    node _T_781 = bits(ifu_fetch_addr_int_f, 1, 1) @[el2_ifu_mem_ctl.scala 453:59]
     node _T_782 = bits(_T_781, 0, 0) @[el2_ifu_mem_ctl.scala 453:63]
     node _T_783 = eq(_T_782, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 453:38]
     node _T_784 = eq(byp_fetch_index_inc_0, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 454:73]
diff --git a/el2_ifu_mem_ctl.v b/el2_ifu_mem_ctl.v
index c166093c..d8540d02 100644
--- a/el2_ifu_mem_ctl.v
+++ b/el2_ifu_mem_ctl.v
@@ -3041,6 +3041,7 @@ module el2_ifu_mem_ctl(
   wire [63:0] _T_416 = _T_415 & io_iccm_rd_data; // @[el2_ifu_mem_ctl.scala 389:64]
   wire [63:0] _T_418 = sel_byp_data ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12]
   wire  _T_1270 = ~ifu_fetch_addr_int_f[0]; // @[el2_ifu_mem_ctl.scala 457:31]
+  wire  _T_783 = ~ifu_fetch_addr_int_f[1]; // @[el2_ifu_mem_ctl.scala 453:38]
   wire [3:0] byp_fetch_index_inc_0 = {byp_fetch_index_inc,1'h0}; // @[Cat.scala 29:58]
   wire  _T_784 = byp_fetch_index_inc_0 == 4'h0; // @[el2_ifu_mem_ctl.scala 454:73]
   wire [15:0] _T_832 = _T_784 ? ic_miss_buff_data_0[15:0] : 16'h0; // @[Mux.scala 27:72]
@@ -3266,7 +3267,7 @@ module el2_ifu_mem_ctl(
   wire [31:0] _T_1169 = _T_829 ? ic_miss_buff_data_15 : 32'h0; // @[Mux.scala 27:72]
   wire [31:0] _T_1184 = _T_1183 | _T_1169; // @[Mux.scala 27:72]
   wire [79:0] _T_1267 = {_T_1104,_T_1184,_T_942}; // @[Cat.scala 29:58]
-  wire [79:0] ic_byp_data_only_pre_new = _T_1270 ? _T_1025 : _T_1267; // @[el2_ifu_mem_ctl.scala 453:37]
+  wire [79:0] ic_byp_data_only_pre_new = _T_783 ? _T_1025 : _T_1267; // @[el2_ifu_mem_ctl.scala 453:37]
   wire [79:0] _T_1272 = {16'h0,ic_byp_data_only_pre_new[79:16]}; // @[Cat.scala 29:58]
   wire [79:0] ic_byp_data_only_new = _T_1270 ? ic_byp_data_only_pre_new : _T_1272; // @[el2_ifu_mem_ctl.scala 457:30]
   wire [79:0] _GEN_794 = {{16'd0}, _T_418}; // @[el2_ifu_mem_ctl.scala 389:109]
diff --git a/src/main/scala/ifu/el2_ifu_mem_ctl.scala b/src/main/scala/ifu/el2_ifu_mem_ctl.scala
index bcc4daa3..7630ff1a 100644
--- a/src/main/scala/ifu/el2_ifu_mem_ctl.scala
+++ b/src/main/scala/ifu/el2_ifu_mem_ctl.scala
@@ -450,7 +450,7 @@ class el2_ifu_mem_ctl extends Module with el2_lib {
     ifu_byp_data_err_new := ic_miss_buff_data_error_bypass
   } otherwise{ifu_byp_data_err_new := ic_miss_buff_data_error_bypass | ic_miss_buff_data_error_bypass_inc}
 
-  val ic_byp_data_only_pre_new = Mux(!ifu_fetch_addr_int_f(0).asBool,
+  val ic_byp_data_only_pre_new = Mux(!ifu_fetch_addr_int_f(1).asBool,
     Cat(Mux1H((0 until 2*ICACHE_NUM_BEATS).map(i=>(byp_fetch_index_inc_0===i.U).asBool->ic_miss_buff_data(i)(15,0))), Mux1H((0 until 2*ICACHE_NUM_BEATS).map(i=>(byp_fetch_index_1===i.U).asBool->ic_miss_buff_data(i)(31,0))), Mux1H((0 until 2*ICACHE_NUM_BEATS).map(i=>(byp_fetch_index_0===i.U).asBool->ic_miss_buff_data(i)(31,0)))),
     Cat(Mux1H((0 until 2*ICACHE_NUM_BEATS).map(i=>(byp_fetch_index_inc_1===i.U).asBool->ic_miss_buff_data(i)(15,0))), Mux1H((0 until 2*ICACHE_NUM_BEATS).map(i=>(byp_fetch_index_inc_0===i.U).asBool->ic_miss_buff_data(i)(31,0))), Mux1H((0 until 2*ICACHE_NUM_BEATS).map(i=>(byp_fetch_index_1===i.U).asBool->ic_miss_buff_data(i)(31,0)))))
 
diff --git a/target/scala-2.12/classes/ifu/el2_ifu_mem_ctl.class b/target/scala-2.12/classes/ifu/el2_ifu_mem_ctl.class
index 286c94ec..2ea4997c 100644
Binary files a/target/scala-2.12/classes/ifu/el2_ifu_mem_ctl.class and b/target/scala-2.12/classes/ifu/el2_ifu_mem_ctl.class differ