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miss state update

This commit is contained in:
waleed-lm 2020-10-23 17:38:37 +05:00
parent 6761b7a5fc
commit bcdc49a556
4 changed files with 17776 additions and 17778 deletions
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25677
el2_ifu_mem_ctl.fir
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9875
el2_ifu_mem_ctl.v
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2
src/main/scala/ifu/el2_ifu_mem_ctl.scala
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@ -186,7 +186,7 @@ class el2_ifu_mem_ctl extends Module with el2_lib {
io.ifu_async_error_start := io.iccm_rd_ecc_single_err | io.ic_error_start
io.ic_dma_active := iccm_correct_ecc | (perr_state === dma_sb_err_C) | (err_stop_state === err_stop_fetch_C) | err_stop_fetch | io.dec_tlu_flush_err_wb
val scnd_miss_req_in = ifu_bus_rsp_valid & bus_ifu_bus_clk_en & ifu_bus_rsp_ready & bus_new_data_beat_count.andR &
!uncacheable_miss_ff ((miss_state === scnd_miss_C)|(miss_nxtstate === scnd_miss_C)) & !io.exu_flush_final
!uncacheable_miss_ff & ((miss_state === scnd_miss_C)|(miss_nxtstate === scnd_miss_C)) & !io.exu_flush_final
val ifu_bp_hit_taken_q_f = io.ifu_bp_hit_taken_f & io.ic_hit_f
///////////////////////////////// MISS FSM /////////////////////////////////

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target/scala-2.12/classes/ifu/el2_ifu_mem_ctl.class
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