From bd59d56b53e24dbf5d47e218e7b25bcfb49aa339 Mon Sep 17 00:00:00 2001 From: waleed-lm Date: Mon, 21 Sep 2020 19:14:00 +0500 Subject: [PATCH] IFC Done --- el2_ifu_ifc_ctrl.anno.json | 81 ++++- el2_ifu_ifc_ctrl.fir | 311 ++++++++++++------ el2_ifu_ifc_ctrl.v | 181 ++++++++-- src/main/scala/ifu/el2_ifu_ifc_ctrl.scala | 201 +++++------ .../ifu/el2_ifu_ifc_ctrl$$anon$1.class | Bin 0 -> 5470 bytes .../classes/ifu/el2_ifu_ifc_ctrl.class | Bin 0 -> 117271 bytes target/scala-2.12/classes/ifu/ifu_ifc$.class | Bin 3854 -> 3878 bytes .../ifu/ifu_ifc$delayedInit$body.class | Bin 737 -> 737 bytes .../scala-2.12/classes/ifu/test$$anon$1.class | Bin 2052 -> 0 bytes target/scala-2.12/classes/ifu/test.class | Bin 43127 -> 0 bytes 10 files changed, 547 insertions(+), 227 deletions(-) create mode 100644 target/scala-2.12/classes/ifu/el2_ifu_ifc_ctrl$$anon$1.class create mode 100644 target/scala-2.12/classes/ifu/el2_ifu_ifc_ctrl.class delete mode 100644 target/scala-2.12/classes/ifu/test$$anon$1.class delete mode 100644 target/scala-2.12/classes/ifu/test.class diff --git a/el2_ifu_ifc_ctrl.anno.json b/el2_ifu_ifc_ctrl.anno.json index 2dd6090d..2f44a8ac 100644 --- a/el2_ifu_ifc_ctrl.anno.json +++ b/el2_ifu_ifc_ctrl.anno.json @@ -1,9 +1,88 @@ [ + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_pmu_fetch_stall", + "sources":[ + "~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_req_bf_raw", + "~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ic_dma_active", + "~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_exu_flush_final", + "~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_fb_consume2", + "~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_fb_consume1" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_req_bf", + "sources":[ + "~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_dec_tlu_flush_noredir_wb", + "~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ic_write_stall", + "~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_req_bf_raw", + "~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ic_dma_active", + "~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_fb_consume2", + "~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_fb_consume1", + "~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_exu_flush_final", + "~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_req_f", + "~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ic_hit_f" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_uncacheable_bf", + "sources":[ + "~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_dec_tlu_mrac_ff", + "~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_addr_bf", + "~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_bp_btb_target_f", + "~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_exu_flush_path_final", + "~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_addr_f", + "~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_exu_flush_final", + "~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ic_hit_f", + "~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_bp_hit_taken_f", + "~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_req_f", + "~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_testin" + ] + }, { "class":"firrtl.transforms.CombinationalPath", "sink":"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_test1", "sources":[ - "~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_addr_f" + "~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_addr_bf", + "~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_bp_btb_target_f", + "~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_exu_flush_path_final", + "~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_addr_f", + "~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_exu_flush_final", + "~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ic_hit_f", + "~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_bp_hit_taken_f", + "~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_req_f", + "~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_testin" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_iccm_access_bf", + "sources":[ + "~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_addr_bf", + "~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_bp_btb_target_f", + "~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_exu_flush_path_final", + "~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_addr_f", + "~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_exu_flush_final", + "~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ic_hit_f", + "~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_bp_hit_taken_f", + "~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_req_f", + "~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_testin" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_addr_bf", + "sources":[ + "~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_bp_btb_target_f", + "~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_exu_flush_path_final", + "~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_addr_f", + "~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_exu_flush_final", + "~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ic_hit_f", + "~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_bp_hit_taken_f", + "~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_req_f", + "~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_testin" ] }, { diff --git a/el2_ifu_ifc_ctrl.fir b/el2_ifu_ifc_ctrl.fir index 7a8781ec..42557fba 100644 --- a/el2_ifu_ifc_ctrl.fir +++ b/el2_ifu_ifc_ctrl.fir @@ -3,30 +3,18 @@ circuit el2_ifu_ifc_ctrl : module el2_ifu_ifc_ctrl : input clock : Clock input reset : UInt<1> - output io : {flip free_clk : UInt<1>, flip active_clk : UInt<1>, flip rst_l : UInt<1>, flip scan_mode : UInt<1>, flip ic_hit_f : UInt<1>, flip ifu_ic_mb_empty : UInt<1>, flip ifu_fb_consume1 : UInt<1>, flip ifu_fb_consume2 : UInt<1>, flip dec_tlu_flush_noredir_wb : UInt<1>, flip exu_flush_final : UInt<1>, flip exu_flush_path_final : UInt<32>, flip ifu_bp_hit_taken_f : UInt<1>, flip ifu_bp_btb_target_f : UInt<32>, flip ic_dma_active : UInt<1>, flip ic_write_stall : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip dec_tlu_mrac_ff : UInt<32>, ifc_fetch_addr_f : UInt<32>, ifc_fetch_addr_bf : UInt<32>, ifc_fetch_req_f : UInt<1>, ifu_pmu_fetch_stall : UInt<1>, ifc_fetch_uncacheable_bf : UInt<1>, ifc_fetch_req_bf : UInt<1>, ifc_fetch_req_bf_raw : UInt<1>, ifc_iccm_access_bf : UInt<1>, ifc_region_acc_fault_bf : UInt<1>, ifc_dma_access_ok : UInt<1>, flip testin : UInt<1>, test1 : UInt} + output io : {flip free_clk : UInt<1>, flip active_clk : UInt<1>, flip rst_l : UInt<1>, flip scan_mode : UInt<1>, flip ic_hit_f : UInt<1>, flip ifu_ic_mb_empty : UInt<1>, flip ifu_fb_consume1 : UInt<1>, flip ifu_fb_consume2 : UInt<1>, flip dec_tlu_flush_noredir_wb : UInt<1>, flip exu_flush_final : UInt<1>, flip exu_flush_path_final : UInt<31>, flip ifu_bp_hit_taken_f : UInt<1>, flip ifu_bp_btb_target_f : UInt<31>, flip ic_dma_active : UInt<1>, flip ic_write_stall : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip dec_tlu_mrac_ff : UInt<31>, ifc_fetch_addr_f : UInt<31>, ifc_fetch_addr_bf : UInt<31>, ifc_fetch_req_f : UInt<1>, ifu_pmu_fetch_stall : UInt<1>, ifc_fetch_uncacheable_bf : UInt<1>, ifc_fetch_req_bf : UInt<1>, ifc_fetch_req_bf_raw : UInt<1>, ifc_iccm_access_bf : UInt<1>, ifc_region_acc_fault_bf : UInt<1>, ifc_dma_access_ok : UInt<1>, flip testin : UInt<1>, test1 : UInt} - io.ifc_fetch_addr_f <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 39:23] - io.ifc_fetch_addr_bf <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 40:24] - io.ifc_fetch_req_f <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 41:22] - io.ifu_pmu_fetch_stall <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 42:26] - io.ifc_fetch_uncacheable_bf <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 43:31] - io.ifc_fetch_req_bf <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 44:23] - io.ifc_fetch_req_bf_raw <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 45:27] - io.ifc_iccm_access_bf <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 46:25] - io.ifc_region_acc_fault_bf <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 47:30] - io.ifc_dma_access_ok <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 48:24] wire fetch_addr_bf : UInt<32> fetch_addr_bf <= UInt<1>("h00") wire fetch_addr_next : UInt<32> fetch_addr_next <= UInt<1>("h00") - wire fb_write_f : UInt<4> - fb_write_f <= UInt<1>("h00") wire fb_write_ns : UInt<4> fb_write_ns <= UInt<1>("h00") + wire fb_write_f : UInt<4> + fb_write_f <= UInt<1>("h00") wire fb_full_f_ns : UInt<1> fb_full_f_ns <= UInt<1>("h00") - wire fb_full_f : UInt<1> - fb_full_f <= UInt<1>("h00") wire fb_right : UInt<1> fb_right <= UInt<1>("h00") wire fb_right2 : UInt<1> @@ -45,12 +33,9 @@ circuit el2_ifu_ifc_ctrl : sel_next_addr_bf <= UInt<1>("h00") wire miss_f : UInt<1> miss_f <= UInt<1>("h00") - wire miss_a : UInt<1> - miss_a <= UInt<1>("h00") + wire miss_a : UInt<1> @[el2_ifu_ifc_ctrl.scala 56:20] wire flush_fb : UInt<1> flush_fb <= UInt<1>("h00") - wire dma_iccm_stall_any_f : UInt<1> - dma_iccm_stall_any_f <= UInt<1>("h00") wire mb_empty_mod : UInt<1> mb_empty_mod <= UInt<1>("h00") wire goto_idle : UInt<1> @@ -60,80 +45,220 @@ circuit el2_ifu_ifc_ctrl : wire fetch_bf_en : UInt<1> fetch_bf_en <= UInt<1>("h00") wire line_wrap : UInt<1> - line_wrap <= UInt<1>("h00") + line_wrap <= io.testin wire fetch_addr_next_1 : UInt<1> fetch_addr_next_1 <= UInt<1>("h00") - reg _T : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 76:34] - _T <= io.dma_iccm_stall_any @[el2_ifu_ifc_ctrl.scala 76:34] - dma_iccm_stall_any_f <= _T @[el2_ifu_ifc_ctrl.scala 76:24] - node dma_stall = or(io.ic_dma_active, dma_iccm_stall_any_f) @[el2_ifu_ifc_ctrl.scala 77:36] - reg _T_1 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 79:34] - _T_1 <= io.dma_iccm_stall_any @[el2_ifu_ifc_ctrl.scala 79:34] - dma_iccm_stall_any_f <= _T_1 @[el2_ifu_ifc_ctrl.scala 79:24] - reg _T_2 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 80:20] - _T_2 <= miss_f @[el2_ifu_ifc_ctrl.scala 80:20] - miss_a <= _T_2 @[el2_ifu_ifc_ctrl.scala 80:10] - node _T_3 = not(io.exu_flush_final) @[el2_ifu_ifc_ctrl.scala 81:23] - node _T_4 = not(io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 81:46] - node _T_5 = not(io.ic_hit_f) @[el2_ifu_ifc_ctrl.scala 81:68] - node _T_6 = or(_T_4, _T_5) @[el2_ifu_ifc_ctrl.scala 81:66] - node _T_7 = and(_T_3, _T_6) @[el2_ifu_ifc_ctrl.scala 81:43] - sel_last_addr_bf <= _T_7 @[el2_ifu_ifc_ctrl.scala 81:20] - node _T_8 = not(io.exu_flush_final) @[el2_ifu_ifc_ctrl.scala 82:23] - node _T_9 = and(_T_8, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 82:43] - node _T_10 = and(_T_9, io.ifu_bp_hit_taken_f) @[el2_ifu_ifc_ctrl.scala 82:64] - node _T_11 = and(_T_10, io.ic_hit_f) @[el2_ifu_ifc_ctrl.scala 82:88] - sel_btb_addr_bf <= _T_11 @[el2_ifu_ifc_ctrl.scala 82:20] - node _T_12 = not(io.exu_flush_final) @[el2_ifu_ifc_ctrl.scala 83:23] - node _T_13 = and(_T_12, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 83:43] - node _T_14 = not(io.ifu_bp_hit_taken_f) @[el2_ifu_ifc_ctrl.scala 83:66] - node _T_15 = and(_T_13, _T_14) @[el2_ifu_ifc_ctrl.scala 83:64] - node _T_16 = and(_T_15, io.ic_hit_f) @[el2_ifu_ifc_ctrl.scala 83:89] - sel_next_addr_bf <= _T_16 @[el2_ifu_ifc_ctrl.scala 83:20] - node _T_17 = bits(io.exu_flush_final, 0, 0) @[el2_ifu_ifc_ctrl.scala 84:55] - node _T_18 = cat(io.exu_flush_path_final, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_19 = bits(sel_last_addr_bf, 0, 0) @[el2_ifu_ifc_ctrl.scala 85:52] - node _T_20 = cat(io.ifc_fetch_addr_f, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_21 = bits(sel_btb_addr_bf, 0, 0) @[el2_ifu_ifc_ctrl.scala 86:51] - node _T_22 = cat(io.ifu_bp_btb_target_f, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_23 = bits(sel_next_addr_bf, 0, 0) @[el2_ifu_ifc_ctrl.scala 87:52] - node _T_24 = cat(fetch_addr_next, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_25 = mux(_T_17, _T_18, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_26 = mux(_T_19, _T_20, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_27 = mux(_T_21, _T_22, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_28 = mux(_T_23, _T_24, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_29 = or(_T_25, _T_26) @[Mux.scala 27:72] - node _T_30 = or(_T_29, _T_27) @[Mux.scala 27:72] - node _T_31 = or(_T_30, _T_28) @[Mux.scala 27:72] - wire _T_32 : UInt<33> @[Mux.scala 27:72] - _T_32 <= _T_31 @[Mux.scala 27:72] - fetch_addr_bf <= _T_32 @[el2_ifu_ifc_ctrl.scala 84:17] - node _T_33 = bits(io.ifc_fetch_addr_f, 31, 2) @[el2_ifu_ifc_ctrl.scala 88:46] - node _T_34 = add(_T_33, UInt<1>("h01")) @[el2_ifu_ifc_ctrl.scala 88:53] - node _T_35 = tail(_T_34, 1) @[el2_ifu_ifc_ctrl.scala 88:53] - node _T_36 = cat(_T_35, fetch_addr_next_1) @[Cat.scala 29:58] - fetch_addr_next <= _T_36 @[el2_ifu_ifc_ctrl.scala 88:19] - node _T_37 = bits(fetch_addr_next, 6, 6) @[el2_ifu_ifc_ctrl.scala 89:32] - node _T_38 = bits(io.ifc_fetch_addr_f, 6, 6) @[el2_ifu_ifc_ctrl.scala 89:75] - node _T_39 = xor(_T_37, _T_38) @[el2_ifu_ifc_ctrl.scala 89:54] - line_wrap <= _T_39 @[el2_ifu_ifc_ctrl.scala 89:13] - node _T_40 = not(line_wrap) @[el2_ifu_ifc_ctrl.scala 90:24] - node _T_41 = bits(io.ifc_fetch_addr_f, 1, 1) @[el2_ifu_ifc_ctrl.scala 90:56] - node _T_42 = and(_T_40, _T_41) @[el2_ifu_ifc_ctrl.scala 90:35] - fetch_addr_next_1 <= _T_42 @[el2_ifu_ifc_ctrl.scala 90:21] - node _T_43 = not(idle) @[el2_ifu_ifc_ctrl.scala 91:30] - io.ifc_fetch_req_bf_raw <= _T_43 @[el2_ifu_ifc_ctrl.scala 91:27] - node _T_44 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctrl.scala 92:91] - node _T_45 = not(_T_44) @[el2_ifu_ifc_ctrl.scala 92:70] - node _T_46 = and(fb_full_f_ns, _T_45) @[el2_ifu_ifc_ctrl.scala 92:68] - node _T_47 = not(_T_46) @[el2_ifu_ifc_ctrl.scala 92:53] - node _T_48 = and(io.ifc_fetch_req_bf_raw, _T_47) @[el2_ifu_ifc_ctrl.scala 92:51] - node _T_49 = not(dma_stall) @[el2_ifu_ifc_ctrl.scala 93:5] - node _T_50 = and(_T_48, _T_49) @[el2_ifu_ifc_ctrl.scala 92:114] - node _T_51 = not(io.ic_write_stall) @[el2_ifu_ifc_ctrl.scala 93:18] - node _T_52 = and(_T_50, _T_51) @[el2_ifu_ifc_ctrl.scala 93:16] - node _T_53 = not(io.dec_tlu_flush_noredir_wb) @[el2_ifu_ifc_ctrl.scala 93:39] - node _T_54 = and(_T_52, _T_53) @[el2_ifu_ifc_ctrl.scala 93:37] - io.ifc_fetch_req_bf <= _T_54 @[el2_ifu_ifc_ctrl.scala 92:23] - io.test1 <= io.ifc_fetch_req_bf @[el2_ifu_ifc_ctrl.scala 96:12] + wire state : UInt<2> + state <= UInt<1>("h00") + io.ifc_fetch_addr_f <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 67:23] + io.ifc_fetch_addr_bf <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 68:24] + io.ifc_fetch_req_f <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 69:22] + io.ifu_pmu_fetch_stall <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 70:26] + io.ifc_fetch_uncacheable_bf <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 71:31] + io.ifc_fetch_req_bf <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 72:23] + io.ifc_fetch_req_bf_raw <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 73:27] + io.ifc_iccm_access_bf <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 74:25] + io.ifc_region_acc_fault_bf <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 75:30] + io.ifc_dma_access_ok <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 76:24] + reg dma_iccm_stall_any_f : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 78:37] + dma_iccm_stall_any_f <= io.dma_iccm_stall_any @[el2_ifu_ifc_ctrl.scala 78:37] + node dma_stall = or(io.ic_dma_active, dma_iccm_stall_any_f) @[el2_ifu_ifc_ctrl.scala 79:36] + reg _T : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 80:20] + _T <= miss_f @[el2_ifu_ifc_ctrl.scala 80:20] + miss_a <= _T @[el2_ifu_ifc_ctrl.scala 80:10] + node _T_1 = not(io.exu_flush_final) @[el2_ifu_ifc_ctrl.scala 82:23] + node _T_2 = not(io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 82:46] + node _T_3 = not(io.ic_hit_f) @[el2_ifu_ifc_ctrl.scala 82:68] + node _T_4 = or(_T_2, _T_3) @[el2_ifu_ifc_ctrl.scala 82:66] + node _T_5 = and(_T_1, _T_4) @[el2_ifu_ifc_ctrl.scala 82:43] + sel_last_addr_bf <= _T_5 @[el2_ifu_ifc_ctrl.scala 82:20] + node _T_6 = not(io.exu_flush_final) @[el2_ifu_ifc_ctrl.scala 83:23] + node _T_7 = and(_T_6, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 83:43] + node _T_8 = and(_T_7, io.ifu_bp_hit_taken_f) @[el2_ifu_ifc_ctrl.scala 83:64] + node _T_9 = and(_T_8, io.ic_hit_f) @[el2_ifu_ifc_ctrl.scala 83:88] + sel_btb_addr_bf <= _T_9 @[el2_ifu_ifc_ctrl.scala 83:20] + node _T_10 = not(io.exu_flush_final) @[el2_ifu_ifc_ctrl.scala 84:23] + node _T_11 = and(_T_10, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 84:43] + node _T_12 = not(io.ifu_bp_hit_taken_f) @[el2_ifu_ifc_ctrl.scala 84:66] + node _T_13 = and(_T_11, _T_12) @[el2_ifu_ifc_ctrl.scala 84:64] + node _T_14 = and(_T_13, io.ic_hit_f) @[el2_ifu_ifc_ctrl.scala 84:89] + sel_next_addr_bf <= _T_14 @[el2_ifu_ifc_ctrl.scala 84:20] + node _T_15 = bits(fetch_addr_next, 6, 6) @[el2_ifu_ifc_ctrl.scala 88:31] + node _T_16 = bits(io.ifc_fetch_addr_f, 6, 6) @[el2_ifu_ifc_ctrl.scala 88:74] + node _T_17 = xor(_T_15, _T_16) @[el2_ifu_ifc_ctrl.scala 88:53] + line_wrap <= _T_17 @[el2_ifu_ifc_ctrl.scala 88:13] + node _T_18 = bits(line_wrap, 0, 0) @[el2_ifu_ifc_ctrl.scala 90:44] + node _T_19 = bits(io.ifc_fetch_addr_f, 0, 0) @[el2_ifu_ifc_ctrl.scala 90:72] + node _T_20 = mux(_T_18, UInt<1>("h00"), _T_19) @[el2_ifu_ifc_ctrl.scala 90:27] + fetch_addr_next_1 <= _T_20 @[el2_ifu_ifc_ctrl.scala 90:21] + node _T_21 = add(io.ifc_fetch_addr_f, UInt<2>("h02")) @[el2_ifu_ifc_ctrl.scala 92:45] + node _T_22 = tail(_T_21, 1) @[el2_ifu_ifc_ctrl.scala 92:45] + node _T_23 = cat(_T_22, fetch_addr_next_1) @[Cat.scala 29:58] + fetch_addr_next <= _T_23 @[el2_ifu_ifc_ctrl.scala 92:19] + node _T_24 = bits(io.exu_flush_final, 0, 0) @[el2_ifu_ifc_ctrl.scala 96:56] + node _T_25 = bits(sel_last_addr_bf, 0, 0) @[el2_ifu_ifc_ctrl.scala 97:46] + node _T_26 = bits(sel_btb_addr_bf, 0, 0) @[el2_ifu_ifc_ctrl.scala 98:45] + node _T_27 = bits(sel_next_addr_bf, 0, 0) @[el2_ifu_ifc_ctrl.scala 99:46] + node _T_28 = mux(_T_24, io.exu_flush_path_final, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_29 = mux(_T_25, io.ifc_fetch_addr_f, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_30 = mux(_T_26, io.ifu_bp_btb_target_f, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_31 = mux(_T_27, fetch_addr_next, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_32 = or(_T_28, _T_29) @[Mux.scala 27:72] + node _T_33 = or(_T_32, _T_30) @[Mux.scala 27:72] + node _T_34 = or(_T_33, _T_31) @[Mux.scala 27:72] + wire _T_35 : UInt<32> @[Mux.scala 27:72] + _T_35 <= _T_34 @[Mux.scala 27:72] + io.ifc_fetch_addr_bf <= _T_35 @[el2_ifu_ifc_ctrl.scala 96:24] + node _T_36 = or(io.exu_flush_final, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 102:88] + reg _T_37 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_36 : @[Reg.scala 28:19] + _T_37 <= io.ifc_fetch_addr_bf @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.ifc_fetch_addr_f <= _T_37 @[el2_ifu_ifc_ctrl.scala 102:23] + node _T_38 = not(idle) @[el2_ifu_ifc_ctrl.scala 104:30] + io.ifc_fetch_req_bf_raw <= _T_38 @[el2_ifu_ifc_ctrl.scala 104:27] + reg _T_39 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 106:32] + _T_39 <= io.ifc_fetch_addr_bf @[el2_ifu_ifc_ctrl.scala 106:32] + io.ifc_fetch_req_f <= _T_39 @[el2_ifu_ifc_ctrl.scala 106:22] + io.test1 <= io.ifc_fetch_addr_bf @[el2_ifu_ifc_ctrl.scala 107:12] + node _T_40 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctrl.scala 109:91] + node _T_41 = not(_T_40) @[el2_ifu_ifc_ctrl.scala 109:70] + node _T_42 = and(fb_full_f_ns, _T_41) @[el2_ifu_ifc_ctrl.scala 109:68] + node _T_43 = not(_T_42) @[el2_ifu_ifc_ctrl.scala 109:53] + node _T_44 = and(io.ifc_fetch_req_bf_raw, _T_43) @[el2_ifu_ifc_ctrl.scala 109:51] + node _T_45 = not(dma_stall) @[el2_ifu_ifc_ctrl.scala 110:5] + node _T_46 = and(_T_44, _T_45) @[el2_ifu_ifc_ctrl.scala 109:114] + node _T_47 = not(io.ic_write_stall) @[el2_ifu_ifc_ctrl.scala 110:18] + node _T_48 = and(_T_46, _T_47) @[el2_ifu_ifc_ctrl.scala 110:16] + node _T_49 = not(io.dec_tlu_flush_noredir_wb) @[el2_ifu_ifc_ctrl.scala 110:39] + node _T_50 = and(_T_48, _T_49) @[el2_ifu_ifc_ctrl.scala 110:37] + io.ifc_fetch_req_bf <= _T_50 @[el2_ifu_ifc_ctrl.scala 109:23] + node _T_51 = not(io.ic_hit_f) @[el2_ifu_ifc_ctrl.scala 112:34] + node _T_52 = and(io.ifc_fetch_req_f, _T_51) @[el2_ifu_ifc_ctrl.scala 112:32] + node _T_53 = not(io.exu_flush_final) @[el2_ifu_ifc_ctrl.scala 112:49] + node _T_54 = and(_T_52, _T_53) @[el2_ifu_ifc_ctrl.scala 112:47] + miss_f <= _T_54 @[el2_ifu_ifc_ctrl.scala 112:10] + node _T_55 = and(io.exu_flush_final, io.dec_tlu_flush_noredir_wb) @[el2_ifu_ifc_ctrl.scala 114:35] + goto_idle <= _T_55 @[el2_ifu_ifc_ctrl.scala 114:13] + node _T_56 = or(io.ifu_ic_mb_empty, io.exu_flush_final) @[el2_ifu_ifc_ctrl.scala 116:39] + node _T_57 = not(dma_stall) @[el2_ifu_ifc_ctrl.scala 116:63] + node _T_58 = and(_T_56, _T_57) @[el2_ifu_ifc_ctrl.scala 116:61] + node _T_59 = not(miss_f) @[el2_ifu_ifc_ctrl.scala 116:76] + node _T_60 = and(_T_58, _T_59) @[el2_ifu_ifc_ctrl.scala 116:74] + node _T_61 = not(miss_a) @[el2_ifu_ifc_ctrl.scala 116:86] + node _T_62 = and(_T_60, _T_61) @[el2_ifu_ifc_ctrl.scala 116:84] + mb_empty_mod <= _T_62 @[el2_ifu_ifc_ctrl.scala 116:16] + node _T_63 = not(io.dec_tlu_flush_noredir_wb) @[el2_ifu_ifc_ctrl.scala 118:38] + node _T_64 = and(io.exu_flush_final, _T_63) @[el2_ifu_ifc_ctrl.scala 118:36] + node _T_65 = and(_T_64, idle) @[el2_ifu_ifc_ctrl.scala 118:67] + leave_idle <= _T_65 @[el2_ifu_ifc_ctrl.scala 118:14] + node _T_66 = bits(state, 1, 1) @[el2_ifu_ifc_ctrl.scala 120:29] + node _T_67 = not(_T_66) @[el2_ifu_ifc_ctrl.scala 120:23] + node _T_68 = bits(state, 0, 0) @[el2_ifu_ifc_ctrl.scala 120:40] + node _T_69 = and(_T_67, _T_68) @[el2_ifu_ifc_ctrl.scala 120:33] + node _T_70 = and(_T_69, miss_f) @[el2_ifu_ifc_ctrl.scala 120:44] + node _T_71 = not(goto_idle) @[el2_ifu_ifc_ctrl.scala 120:55] + node _T_72 = and(_T_70, _T_71) @[el2_ifu_ifc_ctrl.scala 120:53] + node _T_73 = bits(state, 1, 1) @[el2_ifu_ifc_ctrl.scala 121:11] + node _T_74 = not(mb_empty_mod) @[el2_ifu_ifc_ctrl.scala 121:17] + node _T_75 = and(_T_73, _T_74) @[el2_ifu_ifc_ctrl.scala 121:15] + node _T_76 = not(goto_idle) @[el2_ifu_ifc_ctrl.scala 121:33] + node _T_77 = and(_T_75, _T_76) @[el2_ifu_ifc_ctrl.scala 121:31] + node next_state_1 = or(_T_72, _T_77) @[el2_ifu_ifc_ctrl.scala 120:67] + node _T_78 = not(goto_idle) @[el2_ifu_ifc_ctrl.scala 123:23] + node _T_79 = and(_T_78, leave_idle) @[el2_ifu_ifc_ctrl.scala 123:34] + node _T_80 = bits(state, 0, 0) @[el2_ifu_ifc_ctrl.scala 123:56] + node _T_81 = not(goto_idle) @[el2_ifu_ifc_ctrl.scala 123:62] + node _T_82 = and(_T_80, _T_81) @[el2_ifu_ifc_ctrl.scala 123:60] + node next_state_0 = or(_T_79, _T_82) @[el2_ifu_ifc_ctrl.scala 123:48] + node _T_83 = cat(next_state_0, next_state_0) @[Cat.scala 29:58] + reg _T_84 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 125:19] + _T_84 <= _T_83 @[el2_ifu_ifc_ctrl.scala 125:19] + state <= _T_84 @[el2_ifu_ifc_ctrl.scala 125:9] + flush_fb <= io.exu_flush_final @[el2_ifu_ifc_ctrl.scala 127:12] + node _T_85 = not(io.ifu_fb_consume2) @[el2_ifu_ifc_ctrl.scala 129:38] + node _T_86 = and(io.ifu_fb_consume1, _T_85) @[el2_ifu_ifc_ctrl.scala 129:36] + node _T_87 = not(io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 129:61] + node _T_88 = or(_T_87, miss_f) @[el2_ifu_ifc_ctrl.scala 129:81] + node _T_89 = and(_T_86, _T_88) @[el2_ifu_ifc_ctrl.scala 129:58] + node _T_90 = and(io.ifu_fb_consume2, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 130:25] + node _T_91 = or(_T_89, _T_90) @[el2_ifu_ifc_ctrl.scala 129:92] + fb_right <= _T_91 @[el2_ifu_ifc_ctrl.scala 129:12] + node _T_92 = not(io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 132:39] + node _T_93 = or(_T_92, miss_f) @[el2_ifu_ifc_ctrl.scala 132:59] + node _T_94 = and(io.ifu_fb_consume2, _T_93) @[el2_ifu_ifc_ctrl.scala 132:36] + fb_right2 <= _T_94 @[el2_ifu_ifc_ctrl.scala 132:13] + node _T_95 = or(io.ifu_fb_consume1, io.ifu_fb_consume2) @[el2_ifu_ifc_ctrl.scala 133:56] + node _T_96 = not(_T_95) @[el2_ifu_ifc_ctrl.scala 133:35] + node _T_97 = and(io.ifc_fetch_req_f, _T_96) @[el2_ifu_ifc_ctrl.scala 133:33] + node _T_98 = not(miss_f) @[el2_ifu_ifc_ctrl.scala 133:80] + node _T_99 = and(_T_97, _T_98) @[el2_ifu_ifc_ctrl.scala 133:78] + fb_left <= _T_99 @[el2_ifu_ifc_ctrl.scala 133:11] + node _T_100 = not(flush_fb) @[el2_ifu_ifc_ctrl.scala 136:6] + node _T_101 = and(_T_100, fb_right) @[el2_ifu_ifc_ctrl.scala 136:16] + node _T_102 = bits(_T_101, 0, 0) @[el2_ifu_ifc_ctrl.scala 136:28] + node _T_103 = bits(fb_write_f, 3, 1) @[el2_ifu_ifc_ctrl.scala 136:62] + node _T_104 = cat(UInt<1>("h00"), _T_103) @[Cat.scala 29:58] + node _T_105 = not(flush_fb) @[el2_ifu_ifc_ctrl.scala 137:6] + node _T_106 = and(_T_105, fb_right2) @[el2_ifu_ifc_ctrl.scala 137:16] + node _T_107 = bits(_T_106, 0, 0) @[el2_ifu_ifc_ctrl.scala 137:29] + node _T_108 = bits(fb_write_f, 3, 2) @[el2_ifu_ifc_ctrl.scala 137:63] + node _T_109 = cat(UInt<2>("h00"), _T_108) @[Cat.scala 29:58] + node _T_110 = not(flush_fb) @[el2_ifu_ifc_ctrl.scala 138:6] + node _T_111 = and(_T_110, fb_left) @[el2_ifu_ifc_ctrl.scala 138:16] + node _T_112 = bits(_T_111, 0, 0) @[el2_ifu_ifc_ctrl.scala 138:27] + node _T_113 = bits(fb_write_f, 2, 0) @[el2_ifu_ifc_ctrl.scala 138:51] + node _T_114 = cat(_T_113, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_115 = not(flush_fb) @[el2_ifu_ifc_ctrl.scala 139:6] + node _T_116 = not(fb_right) @[el2_ifu_ifc_ctrl.scala 139:18] + node _T_117 = and(_T_115, _T_116) @[el2_ifu_ifc_ctrl.scala 139:16] + node _T_118 = not(fb_right2) @[el2_ifu_ifc_ctrl.scala 139:30] + node _T_119 = and(_T_117, _T_118) @[el2_ifu_ifc_ctrl.scala 139:28] + node _T_120 = not(fb_left) @[el2_ifu_ifc_ctrl.scala 139:43] + node _T_121 = and(_T_119, _T_120) @[el2_ifu_ifc_ctrl.scala 139:41] + node _T_122 = bits(_T_121, 0, 0) @[el2_ifu_ifc_ctrl.scala 139:53] + node _T_123 = bits(fb_write_f, 3, 0) @[el2_ifu_ifc_ctrl.scala 139:73] + node _T_124 = mux(io.exu_flush_final, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_125 = mux(_T_102, _T_104, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_126 = mux(_T_107, _T_109, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_127 = mux(_T_112, _T_114, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_128 = mux(_T_122, _T_123, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_129 = or(_T_124, _T_125) @[Mux.scala 27:72] + node _T_130 = or(_T_129, _T_126) @[Mux.scala 27:72] + node _T_131 = or(_T_130, _T_127) @[Mux.scala 27:72] + node _T_132 = or(_T_131, _T_128) @[Mux.scala 27:72] + wire _T_133 : UInt<4> @[Mux.scala 27:72] + _T_133 <= _T_132 @[Mux.scala 27:72] + fb_write_ns <= _T_133 @[el2_ifu_ifc_ctrl.scala 135:15] + reg _T_134 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 142:26] + _T_134 <= fb_write_ns @[el2_ifu_ifc_ctrl.scala 142:26] + fb_full_f_ns <= _T_134 @[el2_ifu_ifc_ctrl.scala 142:16] + node _T_135 = eq(state, UInt<2>("h00")) @[el2_ifu_ifc_ctrl.scala 144:17] + idle <= _T_135 @[el2_ifu_ifc_ctrl.scala 144:8] + node _T_136 = eq(state, UInt<2>("h03")) @[el2_ifu_ifc_ctrl.scala 145:16] + wfm <= _T_136 @[el2_ifu_ifc_ctrl.scala 145:7] + node _T_137 = bits(fb_write_ns, 3, 3) @[el2_ifu_ifc_ctrl.scala 147:30] + fb_full_f_ns <= _T_137 @[el2_ifu_ifc_ctrl.scala 147:16] + reg fb_full_f : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 148:26] + fb_full_f <= fb_full_f_ns @[el2_ifu_ifc_ctrl.scala 148:26] + node _T_138 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctrl.scala 151:26] + node _T_139 = or(_T_138, io.exu_flush_final) @[el2_ifu_ifc_ctrl.scala 151:47] + node _T_140 = not(_T_139) @[el2_ifu_ifc_ctrl.scala 151:5] + node _T_141 = and(fb_full_f, _T_140) @[el2_ifu_ifc_ctrl.scala 150:75] + node _T_142 = or(_T_141, dma_stall) @[el2_ifu_ifc_ctrl.scala 151:70] + node _T_143 = and(io.ifc_fetch_req_bf_raw, _T_142) @[el2_ifu_ifc_ctrl.scala 150:60] + node _T_144 = or(wfm, _T_143) @[el2_ifu_ifc_ctrl.scala 150:33] + io.ifu_pmu_fetch_stall <= _T_144 @[el2_ifu_ifc_ctrl.scala 150:26] + node _T_145 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_146 = bits(_T_145, 31, 28) @[el2_lib.scala 203:25] + node iccm_acc_in_region_bf = eq(_T_146, UInt<4>("h0e")) @[el2_lib.scala 203:47] + node _T_147 = bits(_T_145, 31, 16) @[el2_lib.scala 206:14] + node iccm_acc_in_range_bf = eq(_T_147, UInt<16>("h0ee00")) @[el2_lib.scala 206:29] + io.ifc_iccm_access_bf <= iccm_acc_in_range_bf @[el2_ifu_ifc_ctrl.scala 157:25] + node _T_148 = bits(io.ifc_fetch_addr_bf, 30, 27) @[el2_ifu_ifc_ctrl.scala 158:78] + node _T_149 = cat(_T_148, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_150 = dshr(io.dec_tlu_mrac_ff, _T_149) @[el2_ifu_ifc_ctrl.scala 158:53] + node _T_151 = bits(_T_150, 0, 0) @[el2_ifu_ifc_ctrl.scala 158:53] + node _T_152 = not(_T_151) @[el2_ifu_ifc_ctrl.scala 158:34] + io.ifc_fetch_uncacheable_bf <= _T_152 @[el2_ifu_ifc_ctrl.scala 158:31] diff --git a/el2_ifu_ifc_ctrl.v b/el2_ifu_ifc_ctrl.v index 4ae3cf67..dca4a70c 100644 --- a/el2_ifu_ifc_ctrl.v +++ b/el2_ifu_ifc_ctrl.v @@ -11,15 +11,15 @@ module el2_ifu_ifc_ctrl( input io_ifu_fb_consume2, input io_dec_tlu_flush_noredir_wb, input io_exu_flush_final, - input [31:0] io_exu_flush_path_final, + input [30:0] io_exu_flush_path_final, input io_ifu_bp_hit_taken_f, - input [31:0] io_ifu_bp_btb_target_f, + input [30:0] io_ifu_bp_btb_target_f, input io_ic_dma_active, input io_ic_write_stall, input io_dma_iccm_stall_any, - input [31:0] io_dec_tlu_mrac_ff, - output [31:0] io_ifc_fetch_addr_f, - output [31:0] io_ifc_fetch_addr_bf, + input [30:0] io_dec_tlu_mrac_ff, + output [30:0] io_ifc_fetch_addr_f, + output [30:0] io_ifc_fetch_addr_bf, output io_ifc_fetch_req_f, output io_ifu_pmu_fetch_stall, output io_ifc_fetch_uncacheable_bf, @@ -29,19 +29,162 @@ module el2_ifu_ifc_ctrl( output io_ifc_region_acc_fault_bf, output io_ifc_dma_access_ok, input io_testin, - output [31:0] io_test1 + output [30:0] io_test1 ); - wire [29:0] _T_35 = io_ifc_fetch_addr_f[31:2] + 30'h1; // @[el2_ifu_ifc_ctrl.scala 88:53] - wire [30:0] _T_36 = {_T_35,1'h0}; // @[Cat.scala 29:58] - assign io_ifc_fetch_addr_f = 32'h0; // @[el2_ifu_ifc_ctrl.scala 39:23] - assign io_ifc_fetch_addr_bf = 32'h0; // @[el2_ifu_ifc_ctrl.scala 40:24] - assign io_ifc_fetch_req_f = 1'h0; // @[el2_ifu_ifc_ctrl.scala 41:22] - assign io_ifu_pmu_fetch_stall = 1'h0; // @[el2_ifu_ifc_ctrl.scala 42:26] - assign io_ifc_fetch_uncacheable_bf = 1'h0; // @[el2_ifu_ifc_ctrl.scala 43:31] - assign io_ifc_fetch_req_bf = 1'h0; // @[el2_ifu_ifc_ctrl.scala 44:23] - assign io_ifc_fetch_req_bf_raw = 1'h0; // @[el2_ifu_ifc_ctrl.scala 45:27] - assign io_ifc_iccm_access_bf = 1'h0; // @[el2_ifu_ifc_ctrl.scala 46:25] - assign io_ifc_region_acc_fault_bf = 1'h0; // @[el2_ifu_ifc_ctrl.scala 47:30] - assign io_ifc_dma_access_ok = 1'h0; // @[el2_ifu_ifc_ctrl.scala 48:24] - assign io_test1 = {{1'd0}, _T_36}; // @[el2_ifu_ifc_ctrl.scala 89:12] +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; +`endif // RANDOMIZE_REG_INIT + reg dma_iccm_stall_any_f; // @[el2_ifu_ifc_ctrl.scala 78:37] + wire dma_stall = io_ic_dma_active | dma_iccm_stall_any_f; // @[el2_ifu_ifc_ctrl.scala 79:36] + wire _T_1 = ~io_exu_flush_final; // @[el2_ifu_ifc_ctrl.scala 82:23] + wire _T_2 = ~io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctrl.scala 82:46] + wire _T_3 = ~io_ic_hit_f; // @[el2_ifu_ifc_ctrl.scala 82:68] + wire _T_4 = _T_2 | _T_3; // @[el2_ifu_ifc_ctrl.scala 82:66] + wire sel_last_addr_bf = _T_1 & _T_4; // @[el2_ifu_ifc_ctrl.scala 82:43] + wire _T_7 = _T_1 & io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctrl.scala 83:43] + wire _T_8 = _T_7 & io_ifu_bp_hit_taken_f; // @[el2_ifu_ifc_ctrl.scala 83:64] + wire sel_btb_addr_bf = _T_8 & io_ic_hit_f; // @[el2_ifu_ifc_ctrl.scala 83:88] + wire _T_12 = ~io_ifu_bp_hit_taken_f; // @[el2_ifu_ifc_ctrl.scala 84:66] + wire _T_13 = _T_7 & _T_12; // @[el2_ifu_ifc_ctrl.scala 84:64] + wire sel_next_addr_bf = _T_13 & io_ic_hit_f; // @[el2_ifu_ifc_ctrl.scala 84:89] + wire fetch_addr_next_1 = io_testin ? 1'h0 : io_ifc_fetch_addr_f[0]; // @[el2_ifu_ifc_ctrl.scala 90:27] + wire [30:0] _T_19 = io_ifc_fetch_addr_f + 31'h2; // @[el2_ifu_ifc_ctrl.scala 92:45] + wire [31:0] fetch_addr_next = {_T_19,fetch_addr_next_1}; // @[Cat.scala 29:58] + wire [30:0] _T_25 = io_exu_flush_final ? io_exu_flush_path_final : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_26 = sel_last_addr_bf ? io_ifc_fetch_addr_f : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_27 = sel_btb_addr_bf ? io_ifu_bp_btb_target_f : 31'h0; // @[Mux.scala 27:72] + wire [31:0] _T_28 = sel_next_addr_bf ? fetch_addr_next : 32'h0; // @[Mux.scala 27:72] + wire [30:0] _T_29 = _T_25 | _T_26; // @[Mux.scala 27:72] + wire [30:0] _T_30 = _T_29 | _T_27; // @[Mux.scala 27:72] + wire [31:0] _GEN_1 = {{1'd0}, _T_30}; // @[Mux.scala 27:72] + wire [31:0] _T_31 = _GEN_1 | _T_28; // @[Mux.scala 27:72] + wire _T_33 = io_exu_flush_final | io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctrl.scala 102:88] + reg [30:0] _T_34; // @[Reg.scala 27:20] + reg [1:0] state; // @[el2_ifu_ifc_ctrl.scala 125:19] + wire idle = state == 2'h0; // @[el2_ifu_ifc_ctrl.scala 144:17] + reg [30:0] _T_36; // @[el2_ifu_ifc_ctrl.scala 106:32] + wire _T_37 = io_ifu_fb_consume2 | io_ifu_fb_consume1; // @[el2_ifu_ifc_ctrl.scala 109:91] + wire _T_38 = ~_T_37; // @[el2_ifu_ifc_ctrl.scala 109:70] + wire [3:0] fb_write_ns = {{3'd0}, io_exu_flush_final}; // @[Mux.scala 27:72] + wire fb_full_f_ns = fb_write_ns[3]; // @[el2_ifu_ifc_ctrl.scala 147:30] + wire _T_39 = fb_full_f_ns & _T_38; // @[el2_ifu_ifc_ctrl.scala 109:68] + wire _T_40 = ~_T_39; // @[el2_ifu_ifc_ctrl.scala 109:53] + wire _T_41 = io_ifc_fetch_req_bf_raw & _T_40; // @[el2_ifu_ifc_ctrl.scala 109:51] + wire _T_42 = ~dma_stall; // @[el2_ifu_ifc_ctrl.scala 110:5] + wire _T_43 = _T_41 & _T_42; // @[el2_ifu_ifc_ctrl.scala 109:114] + wire _T_44 = ~io_ic_write_stall; // @[el2_ifu_ifc_ctrl.scala 110:18] + wire _T_45 = _T_43 & _T_44; // @[el2_ifu_ifc_ctrl.scala 110:16] + wire _T_46 = ~io_dec_tlu_flush_noredir_wb; // @[el2_ifu_ifc_ctrl.scala 110:39] + wire goto_idle = io_exu_flush_final & io_dec_tlu_flush_noredir_wb; // @[el2_ifu_ifc_ctrl.scala 114:35] + wire _T_61 = io_exu_flush_final & _T_46; // @[el2_ifu_ifc_ctrl.scala 118:36] + wire leave_idle = _T_61 & idle; // @[el2_ifu_ifc_ctrl.scala 118:67] + wire _T_68 = ~goto_idle; // @[el2_ifu_ifc_ctrl.scala 120:55] + wire _T_76 = _T_68 & leave_idle; // @[el2_ifu_ifc_ctrl.scala 123:34] + wire _T_79 = state[0] & _T_68; // @[el2_ifu_ifc_ctrl.scala 123:60] + wire next_state_0 = _T_76 | _T_79; // @[el2_ifu_ifc_ctrl.scala 123:48] + wire [1:0] _T_80 = {next_state_0,next_state_0}; // @[Cat.scala 29:58] + wire wfm = state == 2'h3; // @[el2_ifu_ifc_ctrl.scala 145:16] + reg fb_full_f; // @[el2_ifu_ifc_ctrl.scala 148:26] + wire _T_136 = _T_37 | io_exu_flush_final; // @[el2_ifu_ifc_ctrl.scala 151:47] + wire _T_137 = ~_T_136; // @[el2_ifu_ifc_ctrl.scala 151:5] + wire _T_138 = fb_full_f & _T_137; // @[el2_ifu_ifc_ctrl.scala 150:75] + wire _T_139 = _T_138 | dma_stall; // @[el2_ifu_ifc_ctrl.scala 151:70] + wire _T_140 = io_ifc_fetch_req_bf_raw & _T_139; // @[el2_ifu_ifc_ctrl.scala 150:60] + wire [31:0] _T_142 = {io_ifc_fetch_addr_bf,1'h0}; // @[Cat.scala 29:58] + wire [4:0] _T_146 = {io_ifc_fetch_addr_bf[30:27],1'h0}; // @[Cat.scala 29:58] + wire [30:0] _T_147 = io_dec_tlu_mrac_ff >> _T_146; // @[el2_ifu_ifc_ctrl.scala 158:53] + assign io_ifc_fetch_addr_f = _T_34; // @[el2_ifu_ifc_ctrl.scala 67:23 el2_ifu_ifc_ctrl.scala 102:23] + assign io_ifc_fetch_addr_bf = _T_31[30:0]; // @[el2_ifu_ifc_ctrl.scala 68:24 el2_ifu_ifc_ctrl.scala 96:24] + assign io_ifc_fetch_req_f = _T_36[0]; // @[el2_ifu_ifc_ctrl.scala 69:22 el2_ifu_ifc_ctrl.scala 106:22] + assign io_ifu_pmu_fetch_stall = wfm | _T_140; // @[el2_ifu_ifc_ctrl.scala 70:26 el2_ifu_ifc_ctrl.scala 150:26] + assign io_ifc_fetch_uncacheable_bf = ~_T_147[0]; // @[el2_ifu_ifc_ctrl.scala 71:31 el2_ifu_ifc_ctrl.scala 158:31] + assign io_ifc_fetch_req_bf = _T_45 & _T_46; // @[el2_ifu_ifc_ctrl.scala 72:23 el2_ifu_ifc_ctrl.scala 109:23] + assign io_ifc_fetch_req_bf_raw = ~idle; // @[el2_ifu_ifc_ctrl.scala 73:27 el2_ifu_ifc_ctrl.scala 104:27] + assign io_ifc_iccm_access_bf = _T_142[31:16] == 16'hee00; // @[el2_ifu_ifc_ctrl.scala 74:25 el2_ifu_ifc_ctrl.scala 157:25] + assign io_ifc_region_acc_fault_bf = 1'h0; // @[el2_ifu_ifc_ctrl.scala 75:30] + assign io_ifc_dma_access_ok = 1'h0; // @[el2_ifu_ifc_ctrl.scala 76:24] + assign io_test1 = io_ifc_fetch_addr_bf; // @[el2_ifu_ifc_ctrl.scala 107:12] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + dma_iccm_stall_any_f = _RAND_0[0:0]; + _RAND_1 = {1{`RANDOM}}; + _T_34 = _RAND_1[30:0]; + _RAND_2 = {1{`RANDOM}}; + state = _RAND_2[1:0]; + _RAND_3 = {1{`RANDOM}}; + _T_36 = _RAND_3[30:0]; + _RAND_4 = {1{`RANDOM}}; + fb_full_f = _RAND_4[0:0]; +`endif // RANDOMIZE_REG_INIT + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge clock) begin + if (reset) begin + dma_iccm_stall_any_f <= 1'h0; + end else begin + dma_iccm_stall_any_f <= io_dma_iccm_stall_any; + end + if (reset) begin + _T_34 <= 31'h0; + end else if (_T_33) begin + _T_34 <= io_ifc_fetch_addr_bf; + end + if (reset) begin + state <= 2'h0; + end else begin + state <= _T_80; + end + if (reset) begin + _T_36 <= 31'h0; + end else begin + _T_36 <= io_ifc_fetch_addr_bf; + end + if (reset) begin + fb_full_f <= 1'h0; + end else begin + fb_full_f <= fb_full_f_ns; + end + end endmodule diff --git a/src/main/scala/ifu/el2_ifu_ifc_ctrl.scala b/src/main/scala/ifu/el2_ifu_ifc_ctrl.scala index 037f6d87..b35dace8 100644 --- a/src/main/scala/ifu/el2_ifu_ifc_ctrl.scala +++ b/src/main/scala/ifu/el2_ifu_ifc_ctrl.scala @@ -2,16 +2,8 @@ package ifu import lib._ import chisel3._ import chisel3.util._ -class test extends Module with el2_lib { - val io = IO (new Bundle{ - val in1 = Input(UInt(8.W)) - val in2 = Input(UInt(8.W)) - val in3 = Input(Bool()) - val out = Output(UInt(1.W))} - ) - io.out := rvmaskandmatch(io.in1, io.in2, io.in3) -} -/*class el2_ifu_ifc_ctrl extends Module with el2_lib { + +class el2_ifu_ifc_ctrl extends Module with el2_lib { val io = IO(new Bundle{ val free_clk = Input(Bool()) val active_clk = Input(Bool()) @@ -23,16 +15,16 @@ val io = IO(new Bundle{ val ifu_fb_consume2 = Input(Bool()) val dec_tlu_flush_noredir_wb = Input(Bool()) val exu_flush_final = Input(Bool()) - val exu_flush_path_final = Input(UInt(32.W)) + val exu_flush_path_final = Input(UInt(31.W)) val ifu_bp_hit_taken_f = Input(Bool()) - val ifu_bp_btb_target_f = Input(UInt(32.W)) + val ifu_bp_btb_target_f = Input(UInt(31.W)) val ic_dma_active = Input(Bool()) val ic_write_stall = Input(Bool()) val dma_iccm_stall_any = Input(Bool()) - val dec_tlu_mrac_ff = Input(UInt(32.W)) + val dec_tlu_mrac_ff = Input(UInt(31.W)) - val ifc_fetch_addr_f = Output(UInt(32.W)) - val ifc_fetch_addr_bf = Output(UInt(32.W)) + val ifc_fetch_addr_f = Output(UInt(31.W)) + val ifc_fetch_addr_bf = Output(UInt(31.W)) val ifc_fetch_req_f = Output(Bool()) val ifu_pmu_fetch_stall = Output(Bool()) val ifc_fetch_uncacheable_bf = Output(Bool()) @@ -41,10 +33,34 @@ val io = IO(new Bundle{ val ifc_iccm_access_bf = Output(Bool()) val ifc_region_acc_fault_bf = Output(Bool()) val ifc_dma_access_ok = Output(Bool()) - val testin = Input(Bool()) - val test1 = Output(UInt()) - //val test2 = Output(Bool()) }) + + val fetch_addr_bf = WireInit(UInt(32.W), init = 0.U) + val fetch_addr_next = WireInit(UInt(32.W), init = 0.U) + val fb_write_ns = WireInit(UInt(4.W), init = 0.U) + val fb_write_f = WireInit(UInt(4.W), init = 0.U) + val fb_full_f_ns = WireInit(Bool(), init = 0.U) + //val fb_full_f = WireInit(Bool(), init = 0.U) + val fb_right = WireInit(Bool(), init = 0.U) + val fb_right2 = WireInit(Bool(), init = 0.U) + val fb_left = WireInit(Bool(), init = 0.U) + val wfm = WireInit(Bool(), init = 0.U) + val idle = WireInit(Bool(), init = 0.U) + val sel_last_addr_bf = WireInit(Bool(), init = 0.U) + val sel_btb_addr_bf = WireInit(Bool(), init = 0.U) + val sel_next_addr_bf = WireInit(Bool(), init = 0.U) + val miss_f = WireInit(Bool(), init = 0.U) + val miss_a = Wire(Bool()) + val flush_fb = WireInit(Bool(), init = 0.U) + val mb_empty_mod = WireInit(Bool(), init = 0.U) + val goto_idle = WireInit(Bool(), init = 0.U) + val leave_idle = WireInit(Bool(), init = 0.U) + val fetch_bf_en = WireInit(Bool(), init = 0.U) + val line_wrap = WireInit(Bool(), init = io.testin) + val fetch_addr_next_1 = WireInit(Bool(), init = 0.U) + val state = WireInit(UInt(2.W), init = 0.U) + val idle_E :: fetch_E :: stall_E :: wfm_E :: Nil = Enum(4) + io.ifc_fetch_addr_f := 0.U io.ifc_fetch_addr_bf := 0.U io.ifc_fetch_req_f := 0.U @@ -56,131 +72,88 @@ val io = IO(new Bundle{ io.ifc_region_acc_fault_bf := 0.U io.ifc_dma_access_ok := 0.U - val fetch_addr_bf = WireInit(UInt(32.W), init = 0.U) - val fetch_addr_next = WireInit(UInt(32.W), init = 0.U) - val fb_write_f = WireInit(UInt(4.W), init = 0.U) - val fb_write_ns = WireInit(UInt(4.W), init = 0.U) - val fb_full_f_ns = WireInit(Bool(), init = 0.U) - val fb_full_f = WireInit(Bool(), init = 0.U) - val fb_right = WireInit(Bool(), init = 0.U) - val fb_right2 = WireInit(Bool(), init = 0.U) - val fb_left = WireInit(Bool(), init = 0.U) - val wfm = WireInit(Bool(), init = 0.U) - val idle = WireInit(Bool(), init = 0.U) - val sel_last_addr_bf = WireInit(Bool(), init = 0.U) - val sel_btb_addr_bf = WireInit(Bool(), init = 0.U) - val sel_next_addr_bf = WireInit(Bool(), init = 0.U) - val miss_f = WireInit(Bool(), init = 0.U) - val miss_a = WireInit(Bool(), init = 0.U) - val flush_fb = WireInit(Bool(), init = 0.U) - val dma_iccm_stall_any_f = WireInit(Bool(), init = 0.U) - val mb_empty_mod = WireInit(Bool(), init = 0.U) - val goto_idle = WireInit(Bool(), init = 0.U) - val leave_idle = WireInit(Bool(), init = 0.U) - val fetch_bf_en = WireInit(Bool(), init = 0.U) - val line_wrap = WireInit(Bool(), init = 0.U) - val fetch_addr_next_1 = WireInit(Bool(), init = 0.U) - - val idle_E :: fetch_E :: stall_E :: wfm_E :: Nil = Enum(4) - dma_iccm_stall_any_f := RegNext(io.dma_iccm_stall_any, init = 0.U) + val dma_iccm_stall_any_f = RegNext(io.dma_iccm_stall_any, init=0.U) val dma_stall = io.ic_dma_active | dma_iccm_stall_any_f + miss_a := RegNext(miss_f, init=0.U) - dma_iccm_stall_any_f := RegNext(io.dma_iccm_stall_any, init = 0.U) - miss_a := RegNext(miss_f, init = 0.U) sel_last_addr_bf := ~io.exu_flush_final & (~io.ifc_fetch_req_f | ~io.ic_hit_f) sel_btb_addr_bf := ~io.exu_flush_final & io.ifc_fetch_req_f & io.ifu_bp_hit_taken_f & io.ic_hit_f sel_next_addr_bf := ~io.exu_flush_final & io.ifc_fetch_req_f & ~io.ifu_bp_hit_taken_f & io.ic_hit_f - fetch_addr_bf := Mux1H(Seq(io.exu_flush_final.asBool()-> Cat(io.exu_flush_path_final,0.U), - sel_last_addr_bf.asBool() -> Cat(io.ifc_fetch_addr_f,0.U), - sel_btb_addr_bf.asBool() -> Cat(io.ifu_bp_btb_target_f,0.U), - sel_next_addr_bf.asBool() -> Cat(fetch_addr_next, 0.U))) - fetch_addr_next := Cat((io.ifc_fetch_addr_f(31,2) + 1.U), fetch_addr_next_1) - line_wrap := (fetch_addr_next(ICACHE_TAG_INDEX_LO) ^ io.ifc_fetch_addr_f(ICACHE_TAG_INDEX_LO)) - fetch_addr_next_1 := ~line_wrap & io.ifc_fetch_addr_f(1) + + + // Checking the end of cache line wrapping + //line_wrap := fetch_addr_next(ICACHE_TAG_INDEX_LO) ^ io.ifc_fetch_addr_f(ICACHE_TAG_INDEX_LO) + + fetch_addr_next_1 := Mux(line_wrap.asBool(), 0.U, io.ifc_fetch_addr_f(0)) + + fetch_addr_next := Cat(io.ifc_fetch_addr_f+2.U,fetch_addr_next_1) + + + // TODO: Make an assertion for the 1H-Mux under here + io.ifc_fetch_addr_bf := Mux1H(Seq(io.exu_flush_final.asBool -> io.exu_flush_path_final, // Replay PC + sel_last_addr_bf.asBool -> io.ifc_fetch_addr_f, // Hold the current PC + sel_btb_addr_bf.asBool -> io.ifu_bp_btb_target_f, // Take the predicted PC + sel_next_addr_bf.asBool -> fetch_addr_next)) // PC+4 + + + io.ifc_fetch_addr_f := RegEnable(io.ifc_fetch_addr_bf, init = 0.U, io.exu_flush_final|io.ifc_fetch_req_f) + io.ifc_fetch_req_bf_raw := ~idle + + io.ifc_fetch_req_f := RegNext(io.ifc_fetch_addr_bf, init=0.U) + io.ifc_fetch_req_bf := io.ifc_fetch_req_bf_raw & ~(fb_full_f_ns & ~(io.ifu_fb_consume2 | io.ifu_fb_consume1)) & ~dma_stall & ~io.ic_write_stall & ~io.dec_tlu_flush_noredir_wb + miss_f := io.ifc_fetch_req_f & ~io.ic_hit_f & ~io.exu_flush_final - io.test1 := io.ifc_fetch_req_bf // RegNext(miss_f, init = 0.U)//waleed// RegNext(miss_f, init = 0.U) + goto_idle := io.exu_flush_final & io.dec_tlu_flush_noredir_wb - /* + mb_empty_mod := (io.ifu_ic_mb_empty | io.exu_flush_final) & ~dma_stall & ~miss_f & ~miss_a + leave_idle := io.exu_flush_final & ~io.dec_tlu_flush_noredir_wb & idle + val next_state_1 = (~state(1) & state(0) & miss_f & ~goto_idle) | + (state(1) & ~mb_empty_mod & ~goto_idle) + val next_state_0 = (~goto_idle & leave_idle) | (state(0) & ~goto_idle) + state := RegNext(Cat(next_state_0, next_state_0), init = 0.U) + flush_fb := io.exu_flush_final - io.ifc_fetch_req_bf_raw := ~idle - io.ifc_fetch_req_bf := io.ifc_fetch_req_bf_raw & ~(fb_full_f_ns & ~(io.ifu_fb_consume2 | io.ifu_fb_consume1)) & - ~dma_stall & ~io.ic_write_stall & ~io.dec_tlu_flush_noredir_wb + fb_right := ( io.ifu_fb_consume1 & ~io.ifu_fb_consume2 & (~io.ifc_fetch_req_f | miss_f)) | + (io.ifu_fb_consume2 & io.ifc_fetch_req_f) + fb_right2 := (io.ifu_fb_consume2 & (~io.ifc_fetch_req_f | miss_f)) + fb_left := io.ifc_fetch_req_f & ~(io.ifu_fb_consume1 | io.ifu_fb_consume2) & ~miss_f + fb_write_ns := Mux1H(Seq(io.exu_flush_final -> 1.U, + (~flush_fb & fb_right).asBool -> Cat(0.U(1.W), fb_write_f(3,1)), + (~flush_fb & fb_right2).asBool -> Cat(0.U(2.W), fb_write_f(3,2)), + (~flush_fb & fb_left).asBool -> Cat(fb_write_f(2,0), 0.U(1.W)), + (~flush_fb & ~fb_right & ~fb_right2 & ~fb_left).asBool -> fb_write_f(3,0) + )) + fb_full_f_ns := RegNext(fb_write_ns, init = 0.U) - val goto_idle = io.exu_flush_final & io.dec_tlu_flush_noredir_wb - val mb_empty_mod = (io.ifu_ic_mb_empty | io.exu_flush_final) & ~dma_stall & ~miss_f & ~miss_a - val leave_idle = io.exu_flush_final & ~io.dec_tlu_flush_noredir_wb & idle - val state = RegNext(next_state, init = 0.U) - val next_state = Wire(UInt(2.W)) - next_state := Cat((~state(1) & state(0) & miss_f & ~goto_idle) | (state(1) & ~mb_empty_mod & ~goto_idle), - (~goto_idle & leave_idle) | (state(0) & ~goto_idle)) - val fb_right = Wire(UInt(1.W)) - fb_right := ( io.ifu_fb_consume1 & ~io.ifu_fb_consume2 & (~io.ifc_fetch_req_f | miss_f)) | // Consumed and no new fetch - (io.ifu_fb_consume2 & io.ifc_fetch_req_f) // Consumed 2 and new fetch + idle := state === idle_E + wfm := state === wfm_E - val fb_right2 = io.ifu_fb_consume2 & (~io.ifc_fetch_req_f | miss_f) - val fb_left = io.ifc_fetch_req_f & ~(io.ifu_fb_consume1 | io.ifu_fb_consume2) & ~miss_f - val fb_write_ns = Wire(UInt(4.W)) - - fb_write_ns := Mux1H(Seq(flush_fb->1.U(4.W), - (~flush_fb & fb_right).asBool ->fb_write_f(3,1), - (~flush_fb & fb_right2).asBool ->0.U, - (~flush_fb & fb_left).asBool -> Cat(fb_write_f,0.U), - (~flush_fb & ~fb_right & ~fb_right2 & ~fb_left).asBool ->fb_write_f)) - - val fb_full_f_ns = fb_write_ns(3) - val idle = state === idle_E - val wfm = state === wfm_E + fb_full_f_ns := fb_write_ns(3) val fb_full_f = RegNext(fb_full_f_ns, init = 0.U) - val fb_write_f = RegNext(fb_write_ns, init = 0.U) - val flush_fb = io.exu_flush_final - val ifu_pmu_fetch_stall = wfm | (io.ifc_fetch_req_bf_raw & ( (fb_full_f & - ~(io.ifu_fb_consume2 rvrangecheck| io.ifu_fb_consume1 | io.exu_flush_final)) | dma_stall)) - - io.test1 := dma_iccm_stall_any_f - io.test2 := dma_stall - - - - - - io.ifc_fetch_req_f := RegNext(io.ifc_fetch_req_bf, init = 0.U) - val ifc_fetch_addr_bf = Cat(fetch_addr_bf(31,1), 0.U) - + io.ifu_pmu_fetch_stall := wfm | (io.ifc_fetch_req_bf_raw & ( (fb_full_f & + ~(io.ifu_fb_consume2 | io.ifu_fb_consume1 | io.exu_flush_final)) | dma_stall)) val (iccm_acc_in_region_bf, iccm_acc_in_range_bf) = if(ICCM_ENABLE) - rvrangecheck(ICCM_SADR, ICCM_SIZE, ifc_fetch_addr_bf) else (0.U, 0.U) + rvrangecheck(ICCM_SADR, ICCM_SIZE, Cat(io.ifc_fetch_addr_bf,0.U)) + else (0.U, 0.U) io.ifc_iccm_access_bf := iccm_acc_in_range_bf - io.ifc_region_acc_fault_bf := ~iccm_acc_in_range_bf & iccm_acc_in_region_bf - io.ifc_dma_access_ok := ( (~io.ifc_iccm_access_bf | - (fb_full_f & ~(io.ifu_fb_consume2 | io.ifu_fb_consume1)) | - (wfm & ~io.ifc_fetch_req_bf) | idle ) & ~io.exu_flush_final) | dma_iccm_stall_any_f*/ - + io.ifc_fetch_uncacheable_bf := ~io.dec_tlu_mrac_ff(Cat(io.ifc_fetch_addr_bf(30,27), 0.U)) } -class test extends Module with el2_lib { - val io= IO(new Bundle() { - val addr = Input(UInt(32.W)) - val in_range = Output(Bool()) - val in_region = Output(Bool()) - }) - val (range, region) = rvrangecheck(ICCM_SADR, ICCM_SIZE, io.addr) - io.in_region := region - io.in_range := range -}*/ object ifu_ifc extends App { - println((new chisel3.stage.ChiselStage).emitVerilog(new test())) + println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_ifc_ctrl())) } \ No newline at end of file diff --git a/target/scala-2.12/classes/ifu/el2_ifu_ifc_ctrl$$anon$1.class b/target/scala-2.12/classes/ifu/el2_ifu_ifc_ctrl$$anon$1.class new file mode 100644 index 0000000000000000000000000000000000000000..22c10f23a947f60293b5d1deb27f172af8c0a982 GIT binary patch literal 5470 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