diff --git a/el2_ifu_ic_mem.anno.json b/el2_ifu_ic_mem.anno.json index 4feca8f8..51ed856b 100644 --- a/el2_ifu_ic_mem.anno.json +++ b/el2_ifu_ic_mem.anno.json @@ -1,38 +1,4 @@ [ - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_rd_data", - "sources":[ - "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_premux_data", - "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_sel_premux_data", - "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_rd_hit", - "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_wr_en", - "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_debug_way", - "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_clk_override", - "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_rw_addr", - "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_debug_wr_en", - "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_debug_addr", - "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_debug_tag_array", - "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_debug_rd_en", - "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_rd_en" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_debug_rd_data", - "sources":[ - "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_rd_hit", - "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_wr_en", - "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_debug_way", - "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_clk_override", - "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_rw_addr", - "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_debug_wr_en", - "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_debug_addr", - "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_debug_tag_array", - "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_debug_rd_en", - "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_rd_en" - ] - }, { "class":"firrtl.transforms.CombinationalPath", "sink":"~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_eccerr", @@ -46,7 +12,56 @@ "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_debug_addr", "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_debug_tag_array", "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_debug_rd_en", - "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_rd_en" + "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_rd_en", + "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_tag_valid" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ictag_debug_rd_data", + "sources":[ + "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_rw_addr", + "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_debug_addr", + "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_debug_rd_en", + "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_debug_wr_en", + "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_wr_en", + "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_debug_way", + "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_rd_en", + "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_clk_override", + "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_debug_tag_array" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_tag_perr", + "sources":[ + "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_tag_valid", + "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_dec_tlu_core_ecc_disable", + "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_rw_addr", + "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_debug_addr", + "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_debug_rd_en", + "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_debug_wr_en", + "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_wr_en", + "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_debug_way", + "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_rd_en", + "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_clk_override", + "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_debug_tag_array" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_rd_hit", + "sources":[ + "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_tag_valid", + "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_rw_addr", + "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_debug_addr", + "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_debug_rd_en", + "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_debug_wr_en", + "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_wr_en", + "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_debug_way", + "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_rd_en", + "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_clk_override", + "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_debug_tag_array" ] }, { @@ -62,7 +77,44 @@ "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_debug_addr", "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_debug_tag_array", "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_debug_rd_en", - "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_rd_en" + "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_rd_en", + "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_tag_valid" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_rd_data", + "sources":[ + "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_premux_data", + "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_sel_premux_data", + "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_rd_hit", + "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_wr_en", + "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_debug_way", + "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_clk_override", + "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_rw_addr", + "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_debug_wr_en", + "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_debug_addr", + "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_debug_tag_array", + "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_debug_rd_en", + "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_rd_en", + "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_tag_valid" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_debug_rd_data", + "sources":[ + "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_rd_hit", + "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_wr_en", + "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_debug_way", + "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_clk_override", + "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_rw_addr", + "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_debug_wr_en", + "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_debug_addr", + "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_debug_tag_array", + "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_debug_rd_en", + "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_rd_en", + "~el2_ifu_ic_mem|el2_ifu_ic_mem>io_ic_tag_valid" ] }, { diff --git a/el2_ifu_ic_mem.fir b/el2_ifu_ic_mem.fir index f211d6fe..b68ba54f 100644 --- a/el2_ifu_ic_mem.fir +++ b/el2_ifu_ic_mem.fir @@ -1,82 +1,1546 @@ ;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10 circuit el2_ifu_ic_mem : - module el2_ifu_ic_mem : + module EL2_IC_TAG : input clock : Clock - input reset : UInt<1> - output io : {flip scan_mode : UInt<1>, flip clk_override : UInt<1>, flip dec_tlu_core_ecc_disable : UInt<1>, flip ic_rw_addr : UInt<31>, flip ic_wr_en : UInt<2>, flip ic_rd_en : UInt<1>, flip ic_debug_addr : UInt<9>, flip ic_debug_rd_en : UInt<1>, flip ic_debug_wr_en : UInt<1>, flip ic_debug_tag_array : UInt<1>, flip ic_debug_way : UInt<2>, flip ic_premux_data : UInt<64>, flip ic_sel_premux_data : UInt<1>, flip ic_tag_valid : UInt<2>, flip ic_debug_wr_data : UInt<71>, flip ic_wr_data : UInt<71>[2], ic_rd_data : UInt<64>, ic_debug_rd_data : UInt<71>, ictag_debug_rd_data : UInt<26>, ic_eccerr : UInt<2>, ic_parerr : UInt<2>, ic_rd_hit : UInt<2>, ic_tag_perr : UInt<1>} + input reset : Reset + output io : {flip scan_mode : UInt<1>, flip clk_override : UInt<1>, flip dec_tlu_core_ecc_disable : UInt<1>, flip ic_rw_addr : UInt<29>, flip ic_wr_en : UInt<2>, flip ic_tag_valid : UInt<2>, flip ic_rd_en : UInt<1>, flip ic_debug_addr : UInt<10>, flip ic_debug_rd_en : UInt<1>, flip ic_debug_wr_en : UInt<1>, flip ic_debug_tag_array : UInt<1>, flip ic_debug_way : UInt<2>, ictag_debug_rd_data : UInt<26>, flip ic_debug_wr_data : UInt<71>, ic_rd_hit : UInt<2>, ic_tag_perr : UInt<1>} - io.ic_tag_perr <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 34:18] - io.ic_rd_hit <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 35:16] - io.ic_parerr <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 36:16] - io.ic_eccerr <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 37:16] - io.ictag_debug_rd_data <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 38:26] - io.ic_debug_rd_data <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 39:23] - io.ic_rd_data <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 40:17] - node _T = eq(io.ic_debug_tag_array, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 42:70] - node _T_1 = and(io.ic_debug_rd_en, _T) @[el2_ifu_ic_mem.scala 42:68] + io.ictag_debug_rd_data <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 104:26] + io.ic_rd_hit <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 105:16] + io.ic_tag_perr <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 106:18] + wire ic_debug_wr_way_en : UInt<2> + ic_debug_wr_way_en <= UInt<1>("h00") + wire ic_debug_rd_way_en : UInt<2> + ic_debug_rd_way_en <= UInt<1>("h00") + node _T = bits(io.ic_rw_addr, 2, 1) @[el2_ifu_ic_mem.scala 110:70] + node _T_1 = eq(_T, UInt<1>("h01")) @[el2_ifu_ic_mem.scala 110:95] node _T_2 = bits(_T_1, 0, 0) @[Bitwise.scala 72:15] node _T_3 = mux(_T_2, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node ic_debug_rd_way_en = and(_T_3, io.ic_debug_way) @[el2_ifu_ic_mem.scala 42:94] - node _T_4 = eq(io.ic_debug_tag_array, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 43:70] - node _T_5 = and(io.ic_debug_wr_en, _T_4) @[el2_ifu_ic_mem.scala 43:68] - node _T_6 = bits(_T_5, 0, 0) @[Bitwise.scala 72:15] - node _T_7 = mux(_T_6, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node ic_debug_wr_way_en = and(_T_7, io.ic_debug_way) @[el2_ifu_ic_mem.scala 43:94] - wire ic_bank_wr_data : UInt<71>[2] @[el2_ifu_ic_mem.scala 45:29] - wire ic_rd_en_with_debug : UInt<1> - ic_rd_en_with_debug <= UInt<1>("h00") - node _T_8 = or(io.ic_debug_rd_en, io.ic_debug_wr_en) @[el2_ifu_ic_mem.scala 48:45] - node _T_9 = bits(_T_8, 0, 0) @[el2_ifu_ic_mem.scala 48:66] - node _T_10 = cat(io.ic_debug_addr, UInt<2>("h00")) @[Cat.scala 29:58] - node ic_rw_addr_q = mux(_T_9, _T_10, io.ic_rw_addr) @[el2_ifu_ic_mem.scala 48:25] - node _T_11 = bits(ic_rw_addr_q, 11, 3) @[el2_ifu_ic_mem.scala 50:38] - node _T_12 = add(_T_11, UInt<1>("h01")) @[el2_ifu_ic_mem.scala 50:79] - node ic_rw_addr_q_inc = tail(_T_12, 1) @[el2_ifu_ic_mem.scala 50:79] - node _T_13 = bits(io.ic_debug_addr, 0, 0) @[el2_ifu_ic_mem.scala 52:78] - node _T_14 = eq(_T_13, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 52:113] + node ic_tag_wren = and(io.ic_wr_en, _T_3) @[el2_ifu_ic_mem.scala 110:33] + node _T_4 = or(io.ic_rd_en, io.clk_override) @[el2_ifu_ic_mem.scala 111:55] + node _T_5 = bits(_T_4, 0, 0) @[Bitwise.scala 72:15] + node _T_6 = mux(_T_5, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_7 = or(_T_6, io.ic_wr_en) @[el2_ifu_ic_mem.scala 111:73] + node _T_8 = or(_T_7, ic_debug_wr_way_en) @[el2_ifu_ic_mem.scala 111:87] + node ic_tag_clken = or(_T_8, ic_debug_rd_way_en) @[el2_ifu_ic_mem.scala 111:108] + reg ic_rd_en_ff : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ic_mem.scala 113:28] + ic_rd_en_ff <= io.ic_rd_en @[el2_ifu_ic_mem.scala 113:28] + node _T_9 = bits(io.ic_rw_addr, 18, 0) @[el2_ifu_ic_mem.scala 114:44] + reg ic_rw_addr_ff : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ic_mem.scala 114:30] + ic_rw_addr_ff <= _T_9 @[el2_ifu_ic_mem.scala 114:30] + node _T_10 = and(io.ic_debug_rd_en, io.ic_debug_tag_array) @[el2_ifu_ic_mem.scala 118:65] + node _T_11 = bits(_T_10, 0, 0) @[Bitwise.scala 72:15] + node _T_12 = mux(_T_11, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_13 = and(_T_12, io.ic_debug_way) @[el2_ifu_ic_mem.scala 118:90] + ic_debug_rd_way_en <= _T_13 @[el2_ifu_ic_mem.scala 118:22] + node _T_14 = and(io.ic_debug_wr_en, io.ic_debug_tag_array) @[el2_ifu_ic_mem.scala 119:65] node _T_15 = bits(_T_14, 0, 0) @[Bitwise.scala 72:15] node _T_16 = mux(_T_15, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_17 = and(ic_debug_wr_way_en, _T_16) @[el2_ifu_ic_mem.scala 52:38] - node ic_b_sb_wren_0 = or(io.ic_wr_en, _T_17) @[el2_ifu_ic_mem.scala 52:17] - node _T_18 = bits(io.ic_debug_addr, 0, 0) @[el2_ifu_ic_mem.scala 52:78] - node _T_19 = eq(_T_18, UInt<1>("h01")) @[el2_ifu_ic_mem.scala 52:113] + node _T_17 = and(_T_16, io.ic_debug_way) @[el2_ifu_ic_mem.scala 119:90] + ic_debug_wr_way_en <= _T_17 @[el2_ifu_ic_mem.scala 119:22] + node ic_tag_wren_q = or(ic_tag_wren, ic_debug_wr_way_en) @[el2_ifu_ic_mem.scala 121:35] + node _T_18 = mux(UInt<1>("h00"), UInt<13>("h01fff"), UInt<13>("h00")) @[Bitwise.scala 72:12] + node _T_19 = bits(io.ic_rw_addr, 28, 10) @[el2_ifu_ic_mem.scala 123:89] + node _T_20 = cat(_T_18, _T_19) @[Cat.scala 29:58] + wire _T_21 : UInt<1>[18] @[el2_lib.scala 245:18] + wire _T_22 : UInt<1>[18] @[el2_lib.scala 246:18] + wire _T_23 : UInt<1>[18] @[el2_lib.scala 247:18] + wire _T_24 : UInt<1>[15] @[el2_lib.scala 248:18] + wire _T_25 : UInt<1>[15] @[el2_lib.scala 249:18] + wire _T_26 : UInt<1>[6] @[el2_lib.scala 250:18] + node _T_27 = bits(_T_20, 0, 0) @[el2_lib.scala 257:36] + _T_22[0] <= _T_27 @[el2_lib.scala 257:30] + node _T_28 = bits(_T_20, 0, 0) @[el2_lib.scala 258:36] + _T_23[0] <= _T_28 @[el2_lib.scala 258:30] + node _T_29 = bits(_T_20, 0, 0) @[el2_lib.scala 261:36] + _T_26[0] <= _T_29 @[el2_lib.scala 261:30] + node _T_30 = bits(_T_20, 1, 1) @[el2_lib.scala 256:36] + _T_21[0] <= _T_30 @[el2_lib.scala 256:30] + node _T_31 = bits(_T_20, 1, 1) @[el2_lib.scala 258:36] + _T_23[1] <= _T_31 @[el2_lib.scala 258:30] + node _T_32 = bits(_T_20, 1, 1) @[el2_lib.scala 261:36] + _T_26[1] <= _T_32 @[el2_lib.scala 261:30] + node _T_33 = bits(_T_20, 2, 2) @[el2_lib.scala 258:36] + _T_23[2] <= _T_33 @[el2_lib.scala 258:30] + node _T_34 = bits(_T_20, 2, 2) @[el2_lib.scala 261:36] + _T_26[2] <= _T_34 @[el2_lib.scala 261:30] + node _T_35 = bits(_T_20, 3, 3) @[el2_lib.scala 256:36] + _T_21[1] <= _T_35 @[el2_lib.scala 256:30] + node _T_36 = bits(_T_20, 3, 3) @[el2_lib.scala 257:36] + _T_22[1] <= _T_36 @[el2_lib.scala 257:30] + node _T_37 = bits(_T_20, 3, 3) @[el2_lib.scala 261:36] + _T_26[3] <= _T_37 @[el2_lib.scala 261:30] + node _T_38 = bits(_T_20, 4, 4) @[el2_lib.scala 257:36] + _T_22[2] <= _T_38 @[el2_lib.scala 257:30] + node _T_39 = bits(_T_20, 4, 4) @[el2_lib.scala 261:36] + _T_26[4] <= _T_39 @[el2_lib.scala 261:30] + node _T_40 = bits(_T_20, 5, 5) @[el2_lib.scala 256:36] + _T_21[2] <= _T_40 @[el2_lib.scala 256:30] + node _T_41 = bits(_T_20, 5, 5) @[el2_lib.scala 261:36] + _T_26[5] <= _T_41 @[el2_lib.scala 261:30] + node _T_42 = bits(_T_20, 6, 6) @[el2_lib.scala 256:36] + _T_21[3] <= _T_42 @[el2_lib.scala 256:30] + node _T_43 = bits(_T_20, 6, 6) @[el2_lib.scala 257:36] + _T_22[3] <= _T_43 @[el2_lib.scala 257:30] + node _T_44 = bits(_T_20, 6, 6) @[el2_lib.scala 258:36] + _T_23[3] <= _T_44 @[el2_lib.scala 258:30] + node _T_45 = bits(_T_20, 6, 6) @[el2_lib.scala 259:36] + _T_24[0] <= _T_45 @[el2_lib.scala 259:30] + node _T_46 = bits(_T_20, 6, 6) @[el2_lib.scala 260:36] + _T_25[0] <= _T_46 @[el2_lib.scala 260:30] + node _T_47 = bits(_T_20, 7, 7) @[el2_lib.scala 257:36] + _T_22[4] <= _T_47 @[el2_lib.scala 257:30] + node _T_48 = bits(_T_20, 7, 7) @[el2_lib.scala 258:36] + _T_23[4] <= _T_48 @[el2_lib.scala 258:30] + node _T_49 = bits(_T_20, 7, 7) @[el2_lib.scala 259:36] + _T_24[1] <= _T_49 @[el2_lib.scala 259:30] + node _T_50 = bits(_T_20, 7, 7) @[el2_lib.scala 260:36] + _T_25[1] <= _T_50 @[el2_lib.scala 260:30] + node _T_51 = bits(_T_20, 8, 8) @[el2_lib.scala 256:36] + _T_21[4] <= _T_51 @[el2_lib.scala 256:30] + node _T_52 = bits(_T_20, 8, 8) @[el2_lib.scala 258:36] + _T_23[5] <= _T_52 @[el2_lib.scala 258:30] + node _T_53 = bits(_T_20, 8, 8) @[el2_lib.scala 259:36] + _T_24[2] <= _T_53 @[el2_lib.scala 259:30] + node _T_54 = bits(_T_20, 8, 8) @[el2_lib.scala 260:36] + _T_25[2] <= _T_54 @[el2_lib.scala 260:30] + node _T_55 = bits(_T_20, 9, 9) @[el2_lib.scala 258:36] + _T_23[6] <= _T_55 @[el2_lib.scala 258:30] + node _T_56 = bits(_T_20, 9, 9) @[el2_lib.scala 259:36] + _T_24[3] <= _T_56 @[el2_lib.scala 259:30] + node _T_57 = bits(_T_20, 9, 9) @[el2_lib.scala 260:36] + _T_25[3] <= _T_57 @[el2_lib.scala 260:30] + node _T_58 = bits(_T_20, 10, 10) @[el2_lib.scala 256:36] + _T_21[5] <= _T_58 @[el2_lib.scala 256:30] + node _T_59 = bits(_T_20, 10, 10) @[el2_lib.scala 257:36] + _T_22[5] <= _T_59 @[el2_lib.scala 257:30] + node _T_60 = bits(_T_20, 10, 10) @[el2_lib.scala 259:36] + _T_24[4] <= _T_60 @[el2_lib.scala 259:30] + node _T_61 = bits(_T_20, 10, 10) @[el2_lib.scala 260:36] + _T_25[4] <= _T_61 @[el2_lib.scala 260:30] + node _T_62 = bits(_T_20, 11, 11) @[el2_lib.scala 257:36] + _T_22[6] <= _T_62 @[el2_lib.scala 257:30] + node _T_63 = bits(_T_20, 11, 11) @[el2_lib.scala 259:36] + _T_24[5] <= _T_63 @[el2_lib.scala 259:30] + node _T_64 = bits(_T_20, 11, 11) @[el2_lib.scala 260:36] + _T_25[5] <= _T_64 @[el2_lib.scala 260:30] + node _T_65 = bits(_T_20, 12, 12) @[el2_lib.scala 256:36] + _T_21[6] <= _T_65 @[el2_lib.scala 256:30] + node _T_66 = bits(_T_20, 12, 12) @[el2_lib.scala 259:36] + _T_24[6] <= _T_66 @[el2_lib.scala 259:30] + node _T_67 = bits(_T_20, 12, 12) @[el2_lib.scala 260:36] + _T_25[6] <= _T_67 @[el2_lib.scala 260:30] + node _T_68 = bits(_T_20, 13, 13) @[el2_lib.scala 259:36] + _T_24[7] <= _T_68 @[el2_lib.scala 259:30] + node _T_69 = bits(_T_20, 13, 13) @[el2_lib.scala 260:36] + _T_25[7] <= _T_69 @[el2_lib.scala 260:30] + node _T_70 = bits(_T_20, 14, 14) @[el2_lib.scala 256:36] + _T_21[7] <= _T_70 @[el2_lib.scala 256:30] + node _T_71 = bits(_T_20, 14, 14) @[el2_lib.scala 257:36] + _T_22[7] <= _T_71 @[el2_lib.scala 257:30] + node _T_72 = bits(_T_20, 14, 14) @[el2_lib.scala 258:36] + _T_23[7] <= _T_72 @[el2_lib.scala 258:30] + node _T_73 = bits(_T_20, 14, 14) @[el2_lib.scala 260:36] + _T_25[8] <= _T_73 @[el2_lib.scala 260:30] + node _T_74 = bits(_T_20, 15, 15) @[el2_lib.scala 257:36] + _T_22[8] <= _T_74 @[el2_lib.scala 257:30] + node _T_75 = bits(_T_20, 15, 15) @[el2_lib.scala 258:36] + _T_23[8] <= _T_75 @[el2_lib.scala 258:30] + node _T_76 = bits(_T_20, 15, 15) @[el2_lib.scala 260:36] + _T_25[9] <= _T_76 @[el2_lib.scala 260:30] + node _T_77 = bits(_T_20, 16, 16) @[el2_lib.scala 256:36] + _T_21[8] <= _T_77 @[el2_lib.scala 256:30] + node _T_78 = bits(_T_20, 16, 16) @[el2_lib.scala 258:36] + _T_23[9] <= _T_78 @[el2_lib.scala 258:30] + node _T_79 = bits(_T_20, 16, 16) @[el2_lib.scala 260:36] + _T_25[10] <= _T_79 @[el2_lib.scala 260:30] + node _T_80 = bits(_T_20, 17, 17) @[el2_lib.scala 258:36] + _T_23[10] <= _T_80 @[el2_lib.scala 258:30] + node _T_81 = bits(_T_20, 17, 17) @[el2_lib.scala 260:36] + _T_25[11] <= _T_81 @[el2_lib.scala 260:30] + node _T_82 = bits(_T_20, 18, 18) @[el2_lib.scala 256:36] + _T_21[9] <= _T_82 @[el2_lib.scala 256:30] + node _T_83 = bits(_T_20, 18, 18) @[el2_lib.scala 257:36] + _T_22[9] <= _T_83 @[el2_lib.scala 257:30] + node _T_84 = bits(_T_20, 18, 18) @[el2_lib.scala 260:36] + _T_25[12] <= _T_84 @[el2_lib.scala 260:30] + node _T_85 = bits(_T_20, 19, 19) @[el2_lib.scala 257:36] + _T_22[10] <= _T_85 @[el2_lib.scala 257:30] + node _T_86 = bits(_T_20, 19, 19) @[el2_lib.scala 260:36] + _T_25[13] <= _T_86 @[el2_lib.scala 260:30] + node _T_87 = bits(_T_20, 20, 20) @[el2_lib.scala 256:36] + _T_21[10] <= _T_87 @[el2_lib.scala 256:30] + node _T_88 = bits(_T_20, 20, 20) @[el2_lib.scala 260:36] + _T_25[14] <= _T_88 @[el2_lib.scala 260:30] + node _T_89 = bits(_T_20, 21, 21) @[el2_lib.scala 256:36] + _T_21[11] <= _T_89 @[el2_lib.scala 256:30] + node _T_90 = bits(_T_20, 21, 21) @[el2_lib.scala 257:36] + _T_22[11] <= _T_90 @[el2_lib.scala 257:30] + node _T_91 = bits(_T_20, 21, 21) @[el2_lib.scala 258:36] + _T_23[11] <= _T_91 @[el2_lib.scala 258:30] + node _T_92 = bits(_T_20, 21, 21) @[el2_lib.scala 259:36] + _T_24[8] <= _T_92 @[el2_lib.scala 259:30] + node _T_93 = bits(_T_20, 22, 22) @[el2_lib.scala 257:36] + _T_22[12] <= _T_93 @[el2_lib.scala 257:30] + node _T_94 = bits(_T_20, 22, 22) @[el2_lib.scala 258:36] + _T_23[12] <= _T_94 @[el2_lib.scala 258:30] + node _T_95 = bits(_T_20, 22, 22) @[el2_lib.scala 259:36] + _T_24[9] <= _T_95 @[el2_lib.scala 259:30] + node _T_96 = bits(_T_20, 23, 23) @[el2_lib.scala 256:36] + _T_21[12] <= _T_96 @[el2_lib.scala 256:30] + node _T_97 = bits(_T_20, 23, 23) @[el2_lib.scala 258:36] + _T_23[13] <= _T_97 @[el2_lib.scala 258:30] + node _T_98 = bits(_T_20, 23, 23) @[el2_lib.scala 259:36] + _T_24[10] <= _T_98 @[el2_lib.scala 259:30] + node _T_99 = bits(_T_20, 24, 24) @[el2_lib.scala 258:36] + _T_23[14] <= _T_99 @[el2_lib.scala 258:30] + node _T_100 = bits(_T_20, 24, 24) @[el2_lib.scala 259:36] + _T_24[11] <= _T_100 @[el2_lib.scala 259:30] + node _T_101 = bits(_T_20, 25, 25) @[el2_lib.scala 256:36] + _T_21[13] <= _T_101 @[el2_lib.scala 256:30] + node _T_102 = bits(_T_20, 25, 25) @[el2_lib.scala 257:36] + _T_22[13] <= _T_102 @[el2_lib.scala 257:30] + node _T_103 = bits(_T_20, 25, 25) @[el2_lib.scala 259:36] + _T_24[12] <= _T_103 @[el2_lib.scala 259:30] + node _T_104 = bits(_T_20, 26, 26) @[el2_lib.scala 257:36] + _T_22[14] <= _T_104 @[el2_lib.scala 257:30] + node _T_105 = bits(_T_20, 26, 26) @[el2_lib.scala 259:36] + _T_24[13] <= _T_105 @[el2_lib.scala 259:30] + node _T_106 = bits(_T_20, 27, 27) @[el2_lib.scala 256:36] + _T_21[14] <= _T_106 @[el2_lib.scala 256:30] + node _T_107 = bits(_T_20, 27, 27) @[el2_lib.scala 259:36] + _T_24[14] <= _T_107 @[el2_lib.scala 259:30] + node _T_108 = bits(_T_20, 28, 28) @[el2_lib.scala 256:36] + _T_21[15] <= _T_108 @[el2_lib.scala 256:30] + node _T_109 = bits(_T_20, 28, 28) @[el2_lib.scala 257:36] + _T_22[15] <= _T_109 @[el2_lib.scala 257:30] + node _T_110 = bits(_T_20, 28, 28) @[el2_lib.scala 258:36] + _T_23[15] <= _T_110 @[el2_lib.scala 258:30] + node _T_111 = bits(_T_20, 29, 29) @[el2_lib.scala 257:36] + _T_22[16] <= _T_111 @[el2_lib.scala 257:30] + node _T_112 = bits(_T_20, 29, 29) @[el2_lib.scala 258:36] + _T_23[16] <= _T_112 @[el2_lib.scala 258:30] + node _T_113 = bits(_T_20, 30, 30) @[el2_lib.scala 256:36] + _T_21[16] <= _T_113 @[el2_lib.scala 256:30] + node _T_114 = bits(_T_20, 30, 30) @[el2_lib.scala 258:36] + _T_23[17] <= _T_114 @[el2_lib.scala 258:30] + node _T_115 = bits(_T_20, 31, 31) @[el2_lib.scala 256:36] + _T_21[17] <= _T_115 @[el2_lib.scala 256:30] + node _T_116 = bits(_T_20, 31, 31) @[el2_lib.scala 257:36] + _T_22[17] <= _T_116 @[el2_lib.scala 257:30] + node _T_117 = cat(_T_21[1], _T_21[0]) @[el2_lib.scala 263:22] + node _T_118 = cat(_T_21[3], _T_21[2]) @[el2_lib.scala 263:22] + node _T_119 = cat(_T_118, _T_117) @[el2_lib.scala 263:22] + node _T_120 = cat(_T_21[5], _T_21[4]) @[el2_lib.scala 263:22] + node _T_121 = cat(_T_21[8], _T_21[7]) @[el2_lib.scala 263:22] + node _T_122 = cat(_T_121, _T_21[6]) @[el2_lib.scala 263:22] + node _T_123 = cat(_T_122, _T_120) @[el2_lib.scala 263:22] + node _T_124 = cat(_T_123, _T_119) @[el2_lib.scala 263:22] + node _T_125 = cat(_T_21[10], _T_21[9]) @[el2_lib.scala 263:22] + node _T_126 = cat(_T_21[12], _T_21[11]) @[el2_lib.scala 263:22] + node _T_127 = cat(_T_126, _T_125) @[el2_lib.scala 263:22] + node _T_128 = cat(_T_21[14], _T_21[13]) @[el2_lib.scala 263:22] + node _T_129 = cat(_T_21[17], _T_21[16]) @[el2_lib.scala 263:22] + node _T_130 = cat(_T_129, _T_21[15]) @[el2_lib.scala 263:22] + node _T_131 = cat(_T_130, _T_128) @[el2_lib.scala 263:22] + node _T_132 = cat(_T_131, _T_127) @[el2_lib.scala 263:22] + node _T_133 = cat(_T_132, _T_124) @[el2_lib.scala 263:22] + node _T_134 = xorr(_T_133) @[el2_lib.scala 263:29] + node _T_135 = cat(_T_22[1], _T_22[0]) @[el2_lib.scala 263:39] + node _T_136 = cat(_T_22[3], _T_22[2]) @[el2_lib.scala 263:39] + node _T_137 = cat(_T_136, _T_135) @[el2_lib.scala 263:39] + node _T_138 = cat(_T_22[5], _T_22[4]) @[el2_lib.scala 263:39] + node _T_139 = cat(_T_22[8], _T_22[7]) @[el2_lib.scala 263:39] + node _T_140 = cat(_T_139, _T_22[6]) @[el2_lib.scala 263:39] + node _T_141 = cat(_T_140, _T_138) @[el2_lib.scala 263:39] + node _T_142 = cat(_T_141, _T_137) @[el2_lib.scala 263:39] + node _T_143 = cat(_T_22[10], _T_22[9]) @[el2_lib.scala 263:39] + node _T_144 = cat(_T_22[12], _T_22[11]) @[el2_lib.scala 263:39] + node _T_145 = cat(_T_144, _T_143) @[el2_lib.scala 263:39] + node _T_146 = cat(_T_22[14], _T_22[13]) @[el2_lib.scala 263:39] + node _T_147 = cat(_T_22[17], _T_22[16]) @[el2_lib.scala 263:39] + node _T_148 = cat(_T_147, _T_22[15]) @[el2_lib.scala 263:39] + node _T_149 = cat(_T_148, _T_146) @[el2_lib.scala 263:39] + node _T_150 = cat(_T_149, _T_145) @[el2_lib.scala 263:39] + node _T_151 = cat(_T_150, _T_142) @[el2_lib.scala 263:39] + node _T_152 = xorr(_T_151) @[el2_lib.scala 263:46] + node _T_153 = cat(_T_23[1], _T_23[0]) @[el2_lib.scala 263:56] + node _T_154 = cat(_T_23[3], _T_23[2]) @[el2_lib.scala 263:56] + node _T_155 = cat(_T_154, _T_153) @[el2_lib.scala 263:56] + node _T_156 = cat(_T_23[5], _T_23[4]) @[el2_lib.scala 263:56] + node _T_157 = cat(_T_23[8], _T_23[7]) @[el2_lib.scala 263:56] + node _T_158 = cat(_T_157, _T_23[6]) @[el2_lib.scala 263:56] + node _T_159 = cat(_T_158, _T_156) @[el2_lib.scala 263:56] + node _T_160 = cat(_T_159, _T_155) @[el2_lib.scala 263:56] + node _T_161 = cat(_T_23[10], _T_23[9]) @[el2_lib.scala 263:56] + node _T_162 = cat(_T_23[12], _T_23[11]) @[el2_lib.scala 263:56] + node _T_163 = cat(_T_162, _T_161) @[el2_lib.scala 263:56] + node _T_164 = cat(_T_23[14], _T_23[13]) @[el2_lib.scala 263:56] + node _T_165 = cat(_T_23[17], _T_23[16]) @[el2_lib.scala 263:56] + node _T_166 = cat(_T_165, _T_23[15]) @[el2_lib.scala 263:56] + node _T_167 = cat(_T_166, _T_164) @[el2_lib.scala 263:56] + node _T_168 = cat(_T_167, _T_163) @[el2_lib.scala 263:56] + node _T_169 = cat(_T_168, _T_160) @[el2_lib.scala 263:56] + node _T_170 = xorr(_T_169) @[el2_lib.scala 263:63] + node _T_171 = cat(_T_24[2], _T_24[1]) @[el2_lib.scala 263:73] + node _T_172 = cat(_T_171, _T_24[0]) @[el2_lib.scala 263:73] + node _T_173 = cat(_T_24[4], _T_24[3]) @[el2_lib.scala 263:73] + node _T_174 = cat(_T_24[6], _T_24[5]) @[el2_lib.scala 263:73] + node _T_175 = cat(_T_174, _T_173) @[el2_lib.scala 263:73] + node _T_176 = cat(_T_175, _T_172) @[el2_lib.scala 263:73] + node _T_177 = cat(_T_24[8], _T_24[7]) @[el2_lib.scala 263:73] + node _T_178 = cat(_T_24[10], _T_24[9]) @[el2_lib.scala 263:73] + node _T_179 = cat(_T_178, _T_177) @[el2_lib.scala 263:73] + node _T_180 = cat(_T_24[12], _T_24[11]) @[el2_lib.scala 263:73] + node _T_181 = cat(_T_24[14], _T_24[13]) @[el2_lib.scala 263:73] + node _T_182 = cat(_T_181, _T_180) @[el2_lib.scala 263:73] + node _T_183 = cat(_T_182, _T_179) @[el2_lib.scala 263:73] + node _T_184 = cat(_T_183, _T_176) @[el2_lib.scala 263:73] + node _T_185 = xorr(_T_184) @[el2_lib.scala 263:80] + node _T_186 = cat(_T_25[2], _T_25[1]) @[el2_lib.scala 263:90] + node _T_187 = cat(_T_186, _T_25[0]) @[el2_lib.scala 263:90] + node _T_188 = cat(_T_25[4], _T_25[3]) @[el2_lib.scala 263:90] + node _T_189 = cat(_T_25[6], _T_25[5]) @[el2_lib.scala 263:90] + node _T_190 = cat(_T_189, _T_188) @[el2_lib.scala 263:90] + node _T_191 = cat(_T_190, _T_187) @[el2_lib.scala 263:90] + node _T_192 = cat(_T_25[8], _T_25[7]) @[el2_lib.scala 263:90] + node _T_193 = cat(_T_25[10], _T_25[9]) @[el2_lib.scala 263:90] + node _T_194 = cat(_T_193, _T_192) @[el2_lib.scala 263:90] + node _T_195 = cat(_T_25[12], _T_25[11]) @[el2_lib.scala 263:90] + node _T_196 = cat(_T_25[14], _T_25[13]) @[el2_lib.scala 263:90] + node _T_197 = cat(_T_196, _T_195) @[el2_lib.scala 263:90] + node _T_198 = cat(_T_197, _T_194) @[el2_lib.scala 263:90] + node _T_199 = cat(_T_198, _T_191) @[el2_lib.scala 263:90] + node _T_200 = xorr(_T_199) @[el2_lib.scala 263:97] + node _T_201 = cat(_T_26[2], _T_26[1]) @[el2_lib.scala 263:107] + node _T_202 = cat(_T_201, _T_26[0]) @[el2_lib.scala 263:107] + node _T_203 = cat(_T_26[5], _T_26[4]) @[el2_lib.scala 263:107] + node _T_204 = cat(_T_203, _T_26[3]) @[el2_lib.scala 263:107] + node _T_205 = cat(_T_204, _T_202) @[el2_lib.scala 263:107] + node _T_206 = xorr(_T_205) @[el2_lib.scala 263:114] + node _T_207 = cat(_T_185, _T_200) @[Cat.scala 29:58] + node _T_208 = cat(_T_207, _T_206) @[Cat.scala 29:58] + node _T_209 = cat(_T_134, _T_152) @[Cat.scala 29:58] + node _T_210 = cat(_T_209, _T_170) @[Cat.scala 29:58] + node _T_211 = cat(_T_210, _T_208) @[Cat.scala 29:58] + node _T_212 = xorr(_T_20) @[el2_lib.scala 264:13] + node _T_213 = xorr(_T_211) @[el2_lib.scala 264:23] + node _T_214 = xor(_T_212, _T_213) @[el2_lib.scala 264:18] + node ic_tag_ecc = cat(_T_214, _T_211) @[Cat.scala 29:58] + node _T_215 = mux(UInt<1>("h00"), UInt<13>("h01fff"), UInt<13>("h00")) @[Bitwise.scala 72:12] + node _T_216 = bits(io.ic_rw_addr, 28, 10) @[el2_ifu_ic_mem.scala 125:96] + node _T_217 = cat(_T_215, _T_216) @[Cat.scala 29:58] + node ic_tag_parity = xorr(_T_217) @[el2_lib.scala 203:13] + node _T_218 = and(io.ic_debug_wr_en, io.ic_debug_tag_array) @[el2_ifu_ic_mem.scala 129:30] + node _T_219 = bits(io.ic_debug_wr_data, 68, 64) @[el2_ifu_ic_mem.scala 129:93] + node _T_220 = bits(io.ic_debug_wr_data, 31, 11) @[el2_ifu_ic_mem.scala 129:150] + node _T_221 = cat(_T_219, _T_220) @[Cat.scala 29:58] + node _T_222 = bits(ic_tag_ecc, 4, 0) @[el2_ifu_ic_mem.scala 130:38] + node _T_223 = mux(UInt<1>("h00"), UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_224 = cat(_T_222, _T_223) @[Cat.scala 29:58] + node _T_225 = bits(io.ic_rw_addr, 28, 10) @[el2_ifu_ic_mem.scala 130:121] + node _T_226 = cat(_T_224, _T_225) @[Cat.scala 29:58] + node ic_tag_wr_data = mux(_T_218, _T_221, _T_226) @[el2_ifu_ic_mem.scala 129:11] + node _T_227 = or(io.ic_debug_rd_en, io.ic_debug_wr_en) @[el2_ifu_ic_mem.scala 132:45] + node _T_228 = bits(_T_227, 0, 0) @[el2_ifu_ic_mem.scala 132:66] + node _T_229 = bits(io.ic_debug_addr, 9, 3) @[el2_ifu_ic_mem.scala 132:89] + node ic_rw_addr_q = mux(_T_228, _T_229, io.ic_rw_addr) @[el2_ifu_ic_mem.scala 132:25] + reg ic_debug_rd_way_en_ff : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ic_mem.scala 134:38] + ic_debug_rd_way_en_ff <= ic_debug_rd_way_en @[el2_ifu_ic_mem.scala 134:38] + cmem tag_mem : UInt<26>[2][128] @[el2_ifu_ic_mem.scala 136:20] + node _T_230 = bits(ic_tag_wren_q, 0, 0) @[el2_ifu_ic_mem.scala 138:69] + node _T_231 = bits(ic_tag_clken, 0, 0) @[el2_ifu_ic_mem.scala 138:85] + node _T_232 = and(_T_230, _T_231) @[el2_ifu_ic_mem.scala 138:72] + node _T_233 = bits(ic_tag_wren_q, 1, 1) @[el2_ifu_ic_mem.scala 138:69] + node _T_234 = bits(ic_tag_clken, 1, 1) @[el2_ifu_ic_mem.scala 138:85] + node _T_235 = and(_T_233, _T_234) @[el2_ifu_ic_mem.scala 138:72] + wire write_vec : UInt<1>[2] @[el2_ifu_ic_mem.scala 138:52] + write_vec[0] <= _T_232 @[el2_ifu_ic_mem.scala 138:52] + write_vec[1] <= _T_235 @[el2_ifu_ic_mem.scala 138:52] + wire _T_236 : UInt<26>[2] @[el2_ifu_ic_mem.scala 139:64] + _T_236[0] <= ic_tag_wr_data @[el2_ifu_ic_mem.scala 139:64] + _T_236[1] <= ic_tag_wr_data @[el2_ifu_ic_mem.scala 139:64] + node _T_237 = bits(ic_rw_addr_q, 6, 0) + write mport _T_238 = tag_mem[_T_237], clock + when write_vec[0] : + _T_238[0] <= _T_236[0] + skip + when write_vec[1] : + _T_238[1] <= _T_236[1] + skip + node _T_239 = bits(ic_tag_wren_q, 0, 0) @[el2_ifu_ic_mem.scala 141:73] + node _T_240 = eq(_T_239, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 141:59] + node _T_241 = bits(ic_tag_clken, 0, 0) @[el2_ifu_ic_mem.scala 141:90] + node _T_242 = and(_T_240, _T_241) @[el2_ifu_ic_mem.scala 141:77] + node _T_243 = bits(ic_tag_wren_q, 1, 1) @[el2_ifu_ic_mem.scala 141:73] + node _T_244 = eq(_T_243, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 141:59] + node _T_245 = bits(ic_tag_clken, 1, 1) @[el2_ifu_ic_mem.scala 141:90] + node _T_246 = and(_T_244, _T_245) @[el2_ifu_ic_mem.scala 141:77] + wire read_enable : UInt<1>[2] @[el2_ifu_ic_mem.scala 141:54] + read_enable[0] <= _T_242 @[el2_ifu_ic_mem.scala 141:54] + read_enable[1] <= _T_246 @[el2_ifu_ic_mem.scala 141:54] + node _T_247 = bits(read_enable[0], 0, 0) @[Bitwise.scala 72:15] + node _T_248 = mux(_T_247, UInt<26>("h03ffffff"), UInt<26>("h00")) @[Bitwise.scala 72:12] + node _T_249 = bits(ic_rw_addr_q, 6, 0) @[el2_ifu_ic_mem.scala 143:100] + read mport _T_250 = tag_mem[_T_249], clock @[el2_ifu_ic_mem.scala 143:100] + node ic_tag_data_raw_0 = and(_T_248, _T_250[0]) @[el2_ifu_ic_mem.scala 143:87] + node _T_251 = bits(read_enable[1], 0, 0) @[Bitwise.scala 72:15] + node _T_252 = mux(_T_251, UInt<26>("h03ffffff"), UInt<26>("h00")) @[Bitwise.scala 72:12] + node _T_253 = bits(ic_rw_addr_q, 6, 0) @[el2_ifu_ic_mem.scala 143:100] + read mport _T_254 = tag_mem[_T_253], clock @[el2_ifu_ic_mem.scala 143:100] + node ic_tag_data_raw_1 = and(_T_252, _T_254[1]) @[el2_ifu_ic_mem.scala 143:87] + node _T_255 = bits(ic_tag_data_raw_0, 25, 21) @[el2_ifu_ic_mem.scala 145:90] + node _T_256 = bits(ic_tag_data_raw_0, 18, 0) @[el2_ifu_ic_mem.scala 145:117] + node _T_257 = cat(_T_255, _T_256) @[Cat.scala 29:58] + node _T_258 = bits(ic_tag_data_raw_1, 25, 21) @[el2_ifu_ic_mem.scala 145:90] + node _T_259 = bits(ic_tag_data_raw_1, 18, 0) @[el2_ifu_ic_mem.scala 145:117] + node _T_260 = cat(_T_258, _T_259) @[Cat.scala 29:58] + wire w_tout : UInt<24>[2] @[el2_ifu_ic_mem.scala 145:64] + w_tout[0] <= _T_257 @[el2_ifu_ic_mem.scala 145:64] + w_tout[1] <= _T_260 @[el2_ifu_ic_mem.scala 145:64] + wire ic_tag_corrected_ecc_unc : UInt<7>[2] @[el2_ifu_ic_mem.scala 148:38] + wire ic_tag_corrected_data_unc : UInt<32>[2] @[el2_ifu_ic_mem.scala 149:39] + wire ic_tag_single_ecc_error : UInt<1>[2] @[el2_ifu_ic_mem.scala 150:37] + wire ic_tag_double_ecc_error : UInt<1>[2] @[el2_ifu_ic_mem.scala 151:37] + node _T_261 = not(io.dec_tlu_core_ecc_disable) @[el2_ifu_ic_mem.scala 153:51] + node _T_262 = and(_T_261, ic_rd_en_ff) @[el2_ifu_ic_mem.scala 153:80] + node _T_263 = bits(ic_tag_data_raw_0, 20, 0) @[el2_ifu_ic_mem.scala 153:127] + node _T_264 = cat(UInt<11>("h00"), _T_263) @[Cat.scala 29:58] + node _T_265 = bits(ic_tag_data_raw_0, 25, 21) @[el2_ifu_ic_mem.scala 153:167] + node _T_266 = cat(UInt<2>("h00"), _T_265) @[Cat.scala 29:58] + wire _T_267 : UInt<1>[18] @[el2_lib.scala 276:18] + wire _T_268 : UInt<1>[18] @[el2_lib.scala 277:18] + wire _T_269 : UInt<1>[18] @[el2_lib.scala 278:18] + wire _T_270 : UInt<1>[15] @[el2_lib.scala 279:18] + wire _T_271 : UInt<1>[15] @[el2_lib.scala 280:18] + wire _T_272 : UInt<1>[6] @[el2_lib.scala 281:18] + node _T_273 = bits(_T_264, 0, 0) @[el2_lib.scala 288:36] + _T_267[0] <= _T_273 @[el2_lib.scala 288:30] + node _T_274 = bits(_T_264, 0, 0) @[el2_lib.scala 289:36] + _T_268[0] <= _T_274 @[el2_lib.scala 289:30] + node _T_275 = bits(_T_264, 1, 1) @[el2_lib.scala 288:36] + _T_267[1] <= _T_275 @[el2_lib.scala 288:30] + node _T_276 = bits(_T_264, 1, 1) @[el2_lib.scala 290:36] + _T_269[0] <= _T_276 @[el2_lib.scala 290:30] + node _T_277 = bits(_T_264, 2, 2) @[el2_lib.scala 289:36] + _T_268[1] <= _T_277 @[el2_lib.scala 289:30] + node _T_278 = bits(_T_264, 2, 2) @[el2_lib.scala 290:36] + _T_269[1] <= _T_278 @[el2_lib.scala 290:30] + node _T_279 = bits(_T_264, 3, 3) @[el2_lib.scala 288:36] + _T_267[2] <= _T_279 @[el2_lib.scala 288:30] + node _T_280 = bits(_T_264, 3, 3) @[el2_lib.scala 289:36] + _T_268[2] <= _T_280 @[el2_lib.scala 289:30] + node _T_281 = bits(_T_264, 3, 3) @[el2_lib.scala 290:36] + _T_269[2] <= _T_281 @[el2_lib.scala 290:30] + node _T_282 = bits(_T_264, 4, 4) @[el2_lib.scala 288:36] + _T_267[3] <= _T_282 @[el2_lib.scala 288:30] + node _T_283 = bits(_T_264, 4, 4) @[el2_lib.scala 291:36] + _T_270[0] <= _T_283 @[el2_lib.scala 291:30] + node _T_284 = bits(_T_264, 5, 5) @[el2_lib.scala 289:36] + _T_268[3] <= _T_284 @[el2_lib.scala 289:30] + node _T_285 = bits(_T_264, 5, 5) @[el2_lib.scala 291:36] + _T_270[1] <= _T_285 @[el2_lib.scala 291:30] + node _T_286 = bits(_T_264, 6, 6) @[el2_lib.scala 288:36] + _T_267[4] <= _T_286 @[el2_lib.scala 288:30] + node _T_287 = bits(_T_264, 6, 6) @[el2_lib.scala 289:36] + _T_268[4] <= _T_287 @[el2_lib.scala 289:30] + node _T_288 = bits(_T_264, 6, 6) @[el2_lib.scala 291:36] + _T_270[2] <= _T_288 @[el2_lib.scala 291:30] + node _T_289 = bits(_T_264, 7, 7) @[el2_lib.scala 290:36] + _T_269[3] <= _T_289 @[el2_lib.scala 290:30] + node _T_290 = bits(_T_264, 7, 7) @[el2_lib.scala 291:36] + _T_270[3] <= _T_290 @[el2_lib.scala 291:30] + node _T_291 = bits(_T_264, 8, 8) @[el2_lib.scala 288:36] + _T_267[5] <= _T_291 @[el2_lib.scala 288:30] + node _T_292 = bits(_T_264, 8, 8) @[el2_lib.scala 290:36] + _T_269[4] <= _T_292 @[el2_lib.scala 290:30] + node _T_293 = bits(_T_264, 8, 8) @[el2_lib.scala 291:36] + _T_270[4] <= _T_293 @[el2_lib.scala 291:30] + node _T_294 = bits(_T_264, 9, 9) @[el2_lib.scala 289:36] + _T_268[5] <= _T_294 @[el2_lib.scala 289:30] + node _T_295 = bits(_T_264, 9, 9) @[el2_lib.scala 290:36] + _T_269[5] <= _T_295 @[el2_lib.scala 290:30] + node _T_296 = bits(_T_264, 9, 9) @[el2_lib.scala 291:36] + _T_270[5] <= _T_296 @[el2_lib.scala 291:30] + node _T_297 = bits(_T_264, 10, 10) @[el2_lib.scala 288:36] + _T_267[6] <= _T_297 @[el2_lib.scala 288:30] + node _T_298 = bits(_T_264, 10, 10) @[el2_lib.scala 289:36] + _T_268[6] <= _T_298 @[el2_lib.scala 289:30] + node _T_299 = bits(_T_264, 10, 10) @[el2_lib.scala 290:36] + _T_269[6] <= _T_299 @[el2_lib.scala 290:30] + node _T_300 = bits(_T_264, 10, 10) @[el2_lib.scala 291:36] + _T_270[6] <= _T_300 @[el2_lib.scala 291:30] + node _T_301 = bits(_T_264, 11, 11) @[el2_lib.scala 288:36] + _T_267[7] <= _T_301 @[el2_lib.scala 288:30] + node _T_302 = bits(_T_264, 11, 11) @[el2_lib.scala 292:36] + _T_271[0] <= _T_302 @[el2_lib.scala 292:30] + node _T_303 = bits(_T_264, 12, 12) @[el2_lib.scala 289:36] + _T_268[7] <= _T_303 @[el2_lib.scala 289:30] + node _T_304 = bits(_T_264, 12, 12) @[el2_lib.scala 292:36] + _T_271[1] <= _T_304 @[el2_lib.scala 292:30] + node _T_305 = bits(_T_264, 13, 13) @[el2_lib.scala 288:36] + _T_267[8] <= _T_305 @[el2_lib.scala 288:30] + node _T_306 = bits(_T_264, 13, 13) @[el2_lib.scala 289:36] + _T_268[8] <= _T_306 @[el2_lib.scala 289:30] + node _T_307 = bits(_T_264, 13, 13) @[el2_lib.scala 292:36] + _T_271[2] <= _T_307 @[el2_lib.scala 292:30] + node _T_308 = bits(_T_264, 14, 14) @[el2_lib.scala 290:36] + _T_269[7] <= _T_308 @[el2_lib.scala 290:30] + node _T_309 = bits(_T_264, 14, 14) @[el2_lib.scala 292:36] + _T_271[3] <= _T_309 @[el2_lib.scala 292:30] + node _T_310 = bits(_T_264, 15, 15) @[el2_lib.scala 288:36] + _T_267[9] <= _T_310 @[el2_lib.scala 288:30] + node _T_311 = bits(_T_264, 15, 15) @[el2_lib.scala 290:36] + _T_269[8] <= _T_311 @[el2_lib.scala 290:30] + node _T_312 = bits(_T_264, 15, 15) @[el2_lib.scala 292:36] + _T_271[4] <= _T_312 @[el2_lib.scala 292:30] + node _T_313 = bits(_T_264, 16, 16) @[el2_lib.scala 289:36] + _T_268[9] <= _T_313 @[el2_lib.scala 289:30] + node _T_314 = bits(_T_264, 16, 16) @[el2_lib.scala 290:36] + _T_269[9] <= _T_314 @[el2_lib.scala 290:30] + node _T_315 = bits(_T_264, 16, 16) @[el2_lib.scala 292:36] + _T_271[5] <= _T_315 @[el2_lib.scala 292:30] + node _T_316 = bits(_T_264, 17, 17) @[el2_lib.scala 288:36] + _T_267[10] <= _T_316 @[el2_lib.scala 288:30] + node _T_317 = bits(_T_264, 17, 17) @[el2_lib.scala 289:36] + _T_268[10] <= _T_317 @[el2_lib.scala 289:30] + node _T_318 = bits(_T_264, 17, 17) @[el2_lib.scala 290:36] + _T_269[10] <= _T_318 @[el2_lib.scala 290:30] + node _T_319 = bits(_T_264, 17, 17) @[el2_lib.scala 292:36] + _T_271[6] <= _T_319 @[el2_lib.scala 292:30] + node _T_320 = bits(_T_264, 18, 18) @[el2_lib.scala 291:36] + _T_270[7] <= _T_320 @[el2_lib.scala 291:30] + node _T_321 = bits(_T_264, 18, 18) @[el2_lib.scala 292:36] + _T_271[7] <= _T_321 @[el2_lib.scala 292:30] + node _T_322 = bits(_T_264, 19, 19) @[el2_lib.scala 288:36] + _T_267[11] <= _T_322 @[el2_lib.scala 288:30] + node _T_323 = bits(_T_264, 19, 19) @[el2_lib.scala 291:36] + _T_270[8] <= _T_323 @[el2_lib.scala 291:30] + node _T_324 = bits(_T_264, 19, 19) @[el2_lib.scala 292:36] + _T_271[8] <= _T_324 @[el2_lib.scala 292:30] + node _T_325 = bits(_T_264, 20, 20) @[el2_lib.scala 289:36] + _T_268[11] <= _T_325 @[el2_lib.scala 289:30] + node _T_326 = bits(_T_264, 20, 20) @[el2_lib.scala 291:36] + _T_270[9] <= _T_326 @[el2_lib.scala 291:30] + node _T_327 = bits(_T_264, 20, 20) @[el2_lib.scala 292:36] + _T_271[9] <= _T_327 @[el2_lib.scala 292:30] + node _T_328 = bits(_T_264, 21, 21) @[el2_lib.scala 288:36] + _T_267[12] <= _T_328 @[el2_lib.scala 288:30] + node _T_329 = bits(_T_264, 21, 21) @[el2_lib.scala 289:36] + _T_268[12] <= _T_329 @[el2_lib.scala 289:30] + node _T_330 = bits(_T_264, 21, 21) @[el2_lib.scala 291:36] + _T_270[10] <= _T_330 @[el2_lib.scala 291:30] + node _T_331 = bits(_T_264, 21, 21) @[el2_lib.scala 292:36] + _T_271[10] <= _T_331 @[el2_lib.scala 292:30] + node _T_332 = bits(_T_264, 22, 22) @[el2_lib.scala 290:36] + _T_269[11] <= _T_332 @[el2_lib.scala 290:30] + node _T_333 = bits(_T_264, 22, 22) @[el2_lib.scala 291:36] + _T_270[11] <= _T_333 @[el2_lib.scala 291:30] + node _T_334 = bits(_T_264, 22, 22) @[el2_lib.scala 292:36] + _T_271[11] <= _T_334 @[el2_lib.scala 292:30] + node _T_335 = bits(_T_264, 23, 23) @[el2_lib.scala 288:36] + _T_267[13] <= _T_335 @[el2_lib.scala 288:30] + node _T_336 = bits(_T_264, 23, 23) @[el2_lib.scala 290:36] + _T_269[12] <= _T_336 @[el2_lib.scala 290:30] + node _T_337 = bits(_T_264, 23, 23) @[el2_lib.scala 291:36] + _T_270[12] <= _T_337 @[el2_lib.scala 291:30] + node _T_338 = bits(_T_264, 23, 23) @[el2_lib.scala 292:36] + _T_271[12] <= _T_338 @[el2_lib.scala 292:30] + node _T_339 = bits(_T_264, 24, 24) @[el2_lib.scala 289:36] + _T_268[13] <= _T_339 @[el2_lib.scala 289:30] + node _T_340 = bits(_T_264, 24, 24) @[el2_lib.scala 290:36] + _T_269[13] <= _T_340 @[el2_lib.scala 290:30] + node _T_341 = bits(_T_264, 24, 24) @[el2_lib.scala 291:36] + _T_270[13] <= _T_341 @[el2_lib.scala 291:30] + node _T_342 = bits(_T_264, 24, 24) @[el2_lib.scala 292:36] + _T_271[13] <= _T_342 @[el2_lib.scala 292:30] + node _T_343 = bits(_T_264, 25, 25) @[el2_lib.scala 288:36] + _T_267[14] <= _T_343 @[el2_lib.scala 288:30] + node _T_344 = bits(_T_264, 25, 25) @[el2_lib.scala 289:36] + _T_268[14] <= _T_344 @[el2_lib.scala 289:30] + node _T_345 = bits(_T_264, 25, 25) @[el2_lib.scala 290:36] + _T_269[14] <= _T_345 @[el2_lib.scala 290:30] + node _T_346 = bits(_T_264, 25, 25) @[el2_lib.scala 291:36] + _T_270[14] <= _T_346 @[el2_lib.scala 291:30] + node _T_347 = bits(_T_264, 25, 25) @[el2_lib.scala 292:36] + _T_271[14] <= _T_347 @[el2_lib.scala 292:30] + node _T_348 = bits(_T_264, 26, 26) @[el2_lib.scala 288:36] + _T_267[15] <= _T_348 @[el2_lib.scala 288:30] + node _T_349 = bits(_T_264, 26, 26) @[el2_lib.scala 293:36] + _T_272[0] <= _T_349 @[el2_lib.scala 293:30] + node _T_350 = bits(_T_264, 27, 27) @[el2_lib.scala 289:36] + _T_268[15] <= _T_350 @[el2_lib.scala 289:30] + node _T_351 = bits(_T_264, 27, 27) @[el2_lib.scala 293:36] + _T_272[1] <= _T_351 @[el2_lib.scala 293:30] + node _T_352 = bits(_T_264, 28, 28) @[el2_lib.scala 288:36] + _T_267[16] <= _T_352 @[el2_lib.scala 288:30] + node _T_353 = bits(_T_264, 28, 28) @[el2_lib.scala 289:36] + _T_268[16] <= _T_353 @[el2_lib.scala 289:30] + node _T_354 = bits(_T_264, 28, 28) @[el2_lib.scala 293:36] + _T_272[2] <= _T_354 @[el2_lib.scala 293:30] + node _T_355 = bits(_T_264, 29, 29) @[el2_lib.scala 290:36] + _T_269[15] <= _T_355 @[el2_lib.scala 290:30] + node _T_356 = bits(_T_264, 29, 29) @[el2_lib.scala 293:36] + _T_272[3] <= _T_356 @[el2_lib.scala 293:30] + node _T_357 = bits(_T_264, 30, 30) @[el2_lib.scala 288:36] + _T_267[17] <= _T_357 @[el2_lib.scala 288:30] + node _T_358 = bits(_T_264, 30, 30) @[el2_lib.scala 290:36] + _T_269[16] <= _T_358 @[el2_lib.scala 290:30] + node _T_359 = bits(_T_264, 30, 30) @[el2_lib.scala 293:36] + _T_272[4] <= _T_359 @[el2_lib.scala 293:30] + node _T_360 = bits(_T_264, 31, 31) @[el2_lib.scala 289:36] + _T_268[17] <= _T_360 @[el2_lib.scala 289:30] + node _T_361 = bits(_T_264, 31, 31) @[el2_lib.scala 290:36] + _T_269[17] <= _T_361 @[el2_lib.scala 290:30] + node _T_362 = bits(_T_264, 31, 31) @[el2_lib.scala 293:36] + _T_272[5] <= _T_362 @[el2_lib.scala 293:30] + node _T_363 = xorr(_T_264) @[el2_lib.scala 296:30] + node _T_364 = xorr(_T_266) @[el2_lib.scala 296:44] + node _T_365 = xor(_T_363, _T_364) @[el2_lib.scala 296:35] + node _T_366 = not(UInt<1>("h01")) @[el2_lib.scala 296:52] + node _T_367 = and(_T_365, _T_366) @[el2_lib.scala 296:50] + node _T_368 = bits(_T_266, 5, 5) @[el2_lib.scala 296:68] + node _T_369 = cat(_T_272[2], _T_272[1]) @[el2_lib.scala 296:76] + node _T_370 = cat(_T_369, _T_272[0]) @[el2_lib.scala 296:76] + node _T_371 = cat(_T_272[5], _T_272[4]) @[el2_lib.scala 296:76] + node _T_372 = cat(_T_371, _T_272[3]) @[el2_lib.scala 296:76] + node _T_373 = cat(_T_372, _T_370) @[el2_lib.scala 296:76] + node _T_374 = xorr(_T_373) @[el2_lib.scala 296:83] + node _T_375 = xor(_T_368, _T_374) @[el2_lib.scala 296:71] + node _T_376 = bits(_T_266, 4, 4) @[el2_lib.scala 296:95] + node _T_377 = cat(_T_271[2], _T_271[1]) @[el2_lib.scala 296:103] + node _T_378 = cat(_T_377, _T_271[0]) @[el2_lib.scala 296:103] + node _T_379 = cat(_T_271[4], _T_271[3]) @[el2_lib.scala 296:103] + node _T_380 = cat(_T_271[6], _T_271[5]) @[el2_lib.scala 296:103] + node _T_381 = cat(_T_380, _T_379) @[el2_lib.scala 296:103] + node _T_382 = cat(_T_381, _T_378) @[el2_lib.scala 296:103] + node _T_383 = cat(_T_271[8], _T_271[7]) @[el2_lib.scala 296:103] + node _T_384 = cat(_T_271[10], _T_271[9]) @[el2_lib.scala 296:103] + node _T_385 = cat(_T_384, _T_383) @[el2_lib.scala 296:103] + node _T_386 = cat(_T_271[12], _T_271[11]) @[el2_lib.scala 296:103] + node _T_387 = cat(_T_271[14], _T_271[13]) @[el2_lib.scala 296:103] + node _T_388 = cat(_T_387, _T_386) @[el2_lib.scala 296:103] + node _T_389 = cat(_T_388, _T_385) @[el2_lib.scala 296:103] + node _T_390 = cat(_T_389, _T_382) @[el2_lib.scala 296:103] + node _T_391 = xorr(_T_390) @[el2_lib.scala 296:110] + node _T_392 = xor(_T_376, _T_391) @[el2_lib.scala 296:98] + node _T_393 = bits(_T_266, 3, 3) @[el2_lib.scala 296:122] + node _T_394 = cat(_T_270[2], _T_270[1]) @[el2_lib.scala 296:130] + node _T_395 = cat(_T_394, _T_270[0]) @[el2_lib.scala 296:130] + node _T_396 = cat(_T_270[4], _T_270[3]) @[el2_lib.scala 296:130] + node _T_397 = cat(_T_270[6], _T_270[5]) @[el2_lib.scala 296:130] + node _T_398 = cat(_T_397, _T_396) @[el2_lib.scala 296:130] + node _T_399 = cat(_T_398, _T_395) @[el2_lib.scala 296:130] + node _T_400 = cat(_T_270[8], _T_270[7]) @[el2_lib.scala 296:130] + node _T_401 = cat(_T_270[10], _T_270[9]) @[el2_lib.scala 296:130] + node _T_402 = cat(_T_401, _T_400) @[el2_lib.scala 296:130] + node _T_403 = cat(_T_270[12], _T_270[11]) @[el2_lib.scala 296:130] + node _T_404 = cat(_T_270[14], _T_270[13]) @[el2_lib.scala 296:130] + node _T_405 = cat(_T_404, _T_403) @[el2_lib.scala 296:130] + node _T_406 = cat(_T_405, _T_402) @[el2_lib.scala 296:130] + node _T_407 = cat(_T_406, _T_399) @[el2_lib.scala 296:130] + node _T_408 = xorr(_T_407) @[el2_lib.scala 296:137] + node _T_409 = xor(_T_393, _T_408) @[el2_lib.scala 296:125] + node _T_410 = bits(_T_266, 2, 2) @[el2_lib.scala 296:149] + node _T_411 = cat(_T_269[1], _T_269[0]) @[el2_lib.scala 296:157] + node _T_412 = cat(_T_269[3], _T_269[2]) @[el2_lib.scala 296:157] + node _T_413 = cat(_T_412, _T_411) @[el2_lib.scala 296:157] + node _T_414 = cat(_T_269[5], _T_269[4]) @[el2_lib.scala 296:157] + node _T_415 = cat(_T_269[8], _T_269[7]) @[el2_lib.scala 296:157] + node _T_416 = cat(_T_415, _T_269[6]) @[el2_lib.scala 296:157] + node _T_417 = cat(_T_416, _T_414) @[el2_lib.scala 296:157] + node _T_418 = cat(_T_417, _T_413) @[el2_lib.scala 296:157] + node _T_419 = cat(_T_269[10], _T_269[9]) @[el2_lib.scala 296:157] + node _T_420 = cat(_T_269[12], _T_269[11]) @[el2_lib.scala 296:157] + node _T_421 = cat(_T_420, _T_419) @[el2_lib.scala 296:157] + node _T_422 = cat(_T_269[14], _T_269[13]) @[el2_lib.scala 296:157] + node _T_423 = cat(_T_269[17], _T_269[16]) @[el2_lib.scala 296:157] + node _T_424 = cat(_T_423, _T_269[15]) @[el2_lib.scala 296:157] + node _T_425 = cat(_T_424, _T_422) @[el2_lib.scala 296:157] + node _T_426 = cat(_T_425, _T_421) @[el2_lib.scala 296:157] + node _T_427 = cat(_T_426, _T_418) @[el2_lib.scala 296:157] + node _T_428 = xorr(_T_427) @[el2_lib.scala 296:164] + node _T_429 = xor(_T_410, _T_428) @[el2_lib.scala 296:152] + node _T_430 = bits(_T_266, 1, 1) @[el2_lib.scala 296:176] + node _T_431 = cat(_T_268[1], _T_268[0]) @[el2_lib.scala 296:184] + node _T_432 = cat(_T_268[3], _T_268[2]) @[el2_lib.scala 296:184] + node _T_433 = cat(_T_432, _T_431) @[el2_lib.scala 296:184] + node _T_434 = cat(_T_268[5], _T_268[4]) @[el2_lib.scala 296:184] + node _T_435 = cat(_T_268[8], _T_268[7]) @[el2_lib.scala 296:184] + node _T_436 = cat(_T_435, _T_268[6]) @[el2_lib.scala 296:184] + node _T_437 = cat(_T_436, _T_434) @[el2_lib.scala 296:184] + node _T_438 = cat(_T_437, _T_433) @[el2_lib.scala 296:184] + node _T_439 = cat(_T_268[10], _T_268[9]) @[el2_lib.scala 296:184] + node _T_440 = cat(_T_268[12], _T_268[11]) @[el2_lib.scala 296:184] + node _T_441 = cat(_T_440, _T_439) @[el2_lib.scala 296:184] + node _T_442 = cat(_T_268[14], _T_268[13]) @[el2_lib.scala 296:184] + node _T_443 = cat(_T_268[17], _T_268[16]) @[el2_lib.scala 296:184] + node _T_444 = cat(_T_443, _T_268[15]) @[el2_lib.scala 296:184] + node _T_445 = cat(_T_444, _T_442) @[el2_lib.scala 296:184] + node _T_446 = cat(_T_445, _T_441) @[el2_lib.scala 296:184] + node _T_447 = cat(_T_446, _T_438) @[el2_lib.scala 296:184] + node _T_448 = xorr(_T_447) @[el2_lib.scala 296:191] + node _T_449 = xor(_T_430, _T_448) @[el2_lib.scala 296:179] + node _T_450 = bits(_T_266, 0, 0) @[el2_lib.scala 296:203] + node _T_451 = cat(_T_267[1], _T_267[0]) @[el2_lib.scala 296:211] + node _T_452 = cat(_T_267[3], _T_267[2]) @[el2_lib.scala 296:211] + node _T_453 = cat(_T_452, _T_451) @[el2_lib.scala 296:211] + node _T_454 = cat(_T_267[5], _T_267[4]) @[el2_lib.scala 296:211] + node _T_455 = cat(_T_267[8], _T_267[7]) @[el2_lib.scala 296:211] + node _T_456 = cat(_T_455, _T_267[6]) @[el2_lib.scala 296:211] + node _T_457 = cat(_T_456, _T_454) @[el2_lib.scala 296:211] + node _T_458 = cat(_T_457, _T_453) @[el2_lib.scala 296:211] + node _T_459 = cat(_T_267[10], _T_267[9]) @[el2_lib.scala 296:211] + node _T_460 = cat(_T_267[12], _T_267[11]) @[el2_lib.scala 296:211] + node _T_461 = cat(_T_460, _T_459) @[el2_lib.scala 296:211] + node _T_462 = cat(_T_267[14], _T_267[13]) @[el2_lib.scala 296:211] + node _T_463 = cat(_T_267[17], _T_267[16]) @[el2_lib.scala 296:211] + node _T_464 = cat(_T_463, _T_267[15]) @[el2_lib.scala 296:211] + node _T_465 = cat(_T_464, _T_462) @[el2_lib.scala 296:211] + node _T_466 = cat(_T_465, _T_461) @[el2_lib.scala 296:211] + node _T_467 = cat(_T_466, _T_458) @[el2_lib.scala 296:211] + node _T_468 = xorr(_T_467) @[el2_lib.scala 296:218] + node _T_469 = xor(_T_450, _T_468) @[el2_lib.scala 296:206] + node _T_470 = cat(_T_429, _T_449) @[Cat.scala 29:58] + node _T_471 = cat(_T_470, _T_469) @[Cat.scala 29:58] + node _T_472 = cat(_T_392, _T_409) @[Cat.scala 29:58] + node _T_473 = cat(_T_367, _T_375) @[Cat.scala 29:58] + node _T_474 = cat(_T_473, _T_472) @[Cat.scala 29:58] + node _T_475 = cat(_T_474, _T_471) @[Cat.scala 29:58] + node _T_476 = neq(_T_475, UInt<1>("h00")) @[el2_lib.scala 297:44] + node _T_477 = and(_T_262, _T_476) @[el2_lib.scala 297:32] + node _T_478 = bits(_T_475, 6, 6) @[el2_lib.scala 297:64] + node _T_479 = and(_T_477, _T_478) @[el2_lib.scala 297:53] + node _T_480 = neq(_T_475, UInt<1>("h00")) @[el2_lib.scala 298:44] + node _T_481 = and(_T_262, _T_480) @[el2_lib.scala 298:32] + node _T_482 = bits(_T_475, 6, 6) @[el2_lib.scala 298:65] + node _T_483 = not(_T_482) @[el2_lib.scala 298:55] + node _T_484 = and(_T_481, _T_483) @[el2_lib.scala 298:53] + wire _T_485 : UInt<1>[39] @[el2_lib.scala 299:26] + node _T_486 = bits(_T_475, 5, 0) @[el2_lib.scala 302:35] + node _T_487 = eq(_T_486, UInt<1>("h01")) @[el2_lib.scala 302:41] + _T_485[0] <= _T_487 @[el2_lib.scala 302:23] + node _T_488 = bits(_T_475, 5, 0) @[el2_lib.scala 302:35] + node _T_489 = eq(_T_488, UInt<2>("h02")) @[el2_lib.scala 302:41] + _T_485[1] <= _T_489 @[el2_lib.scala 302:23] + node _T_490 = bits(_T_475, 5, 0) @[el2_lib.scala 302:35] + node _T_491 = eq(_T_490, UInt<2>("h03")) @[el2_lib.scala 302:41] + _T_485[2] <= _T_491 @[el2_lib.scala 302:23] + node _T_492 = bits(_T_475, 5, 0) @[el2_lib.scala 302:35] + node _T_493 = eq(_T_492, UInt<3>("h04")) @[el2_lib.scala 302:41] + _T_485[3] <= _T_493 @[el2_lib.scala 302:23] + node _T_494 = bits(_T_475, 5, 0) @[el2_lib.scala 302:35] + node _T_495 = eq(_T_494, UInt<3>("h05")) @[el2_lib.scala 302:41] + _T_485[4] <= _T_495 @[el2_lib.scala 302:23] + node _T_496 = bits(_T_475, 5, 0) @[el2_lib.scala 302:35] + node _T_497 = eq(_T_496, UInt<3>("h06")) @[el2_lib.scala 302:41] + _T_485[5] <= _T_497 @[el2_lib.scala 302:23] + node _T_498 = bits(_T_475, 5, 0) @[el2_lib.scala 302:35] + node _T_499 = eq(_T_498, UInt<3>("h07")) @[el2_lib.scala 302:41] + _T_485[6] <= _T_499 @[el2_lib.scala 302:23] + node _T_500 = bits(_T_475, 5, 0) @[el2_lib.scala 302:35] + node _T_501 = eq(_T_500, UInt<4>("h08")) @[el2_lib.scala 302:41] + _T_485[7] <= _T_501 @[el2_lib.scala 302:23] + node _T_502 = bits(_T_475, 5, 0) @[el2_lib.scala 302:35] + node _T_503 = eq(_T_502, UInt<4>("h09")) @[el2_lib.scala 302:41] + _T_485[8] <= _T_503 @[el2_lib.scala 302:23] + node _T_504 = bits(_T_475, 5, 0) @[el2_lib.scala 302:35] + node _T_505 = eq(_T_504, UInt<4>("h0a")) @[el2_lib.scala 302:41] + _T_485[9] <= _T_505 @[el2_lib.scala 302:23] + node _T_506 = bits(_T_475, 5, 0) @[el2_lib.scala 302:35] + node _T_507 = eq(_T_506, UInt<4>("h0b")) @[el2_lib.scala 302:41] + _T_485[10] <= _T_507 @[el2_lib.scala 302:23] + node _T_508 = bits(_T_475, 5, 0) @[el2_lib.scala 302:35] + node _T_509 = eq(_T_508, UInt<4>("h0c")) @[el2_lib.scala 302:41] + _T_485[11] <= _T_509 @[el2_lib.scala 302:23] + node _T_510 = bits(_T_475, 5, 0) @[el2_lib.scala 302:35] + node _T_511 = eq(_T_510, UInt<4>("h0d")) @[el2_lib.scala 302:41] + _T_485[12] <= _T_511 @[el2_lib.scala 302:23] + node _T_512 = bits(_T_475, 5, 0) @[el2_lib.scala 302:35] + node _T_513 = eq(_T_512, UInt<4>("h0e")) @[el2_lib.scala 302:41] + _T_485[13] <= _T_513 @[el2_lib.scala 302:23] + node _T_514 = bits(_T_475, 5, 0) @[el2_lib.scala 302:35] + node _T_515 = eq(_T_514, UInt<4>("h0f")) @[el2_lib.scala 302:41] + _T_485[14] <= _T_515 @[el2_lib.scala 302:23] + node _T_516 = bits(_T_475, 5, 0) @[el2_lib.scala 302:35] + node _T_517 = eq(_T_516, UInt<5>("h010")) @[el2_lib.scala 302:41] + _T_485[15] <= _T_517 @[el2_lib.scala 302:23] + node _T_518 = bits(_T_475, 5, 0) @[el2_lib.scala 302:35] + node _T_519 = eq(_T_518, UInt<5>("h011")) @[el2_lib.scala 302:41] + _T_485[16] <= _T_519 @[el2_lib.scala 302:23] + node _T_520 = bits(_T_475, 5, 0) @[el2_lib.scala 302:35] + node _T_521 = eq(_T_520, UInt<5>("h012")) @[el2_lib.scala 302:41] + _T_485[17] <= _T_521 @[el2_lib.scala 302:23] + node _T_522 = bits(_T_475, 5, 0) @[el2_lib.scala 302:35] + node _T_523 = eq(_T_522, UInt<5>("h013")) @[el2_lib.scala 302:41] + _T_485[18] <= _T_523 @[el2_lib.scala 302:23] + node _T_524 = bits(_T_475, 5, 0) @[el2_lib.scala 302:35] + node _T_525 = eq(_T_524, UInt<5>("h014")) @[el2_lib.scala 302:41] + _T_485[19] <= _T_525 @[el2_lib.scala 302:23] + node _T_526 = bits(_T_475, 5, 0) @[el2_lib.scala 302:35] + node _T_527 = eq(_T_526, UInt<5>("h015")) @[el2_lib.scala 302:41] + _T_485[20] <= _T_527 @[el2_lib.scala 302:23] + node _T_528 = bits(_T_475, 5, 0) @[el2_lib.scala 302:35] + node _T_529 = eq(_T_528, UInt<5>("h016")) @[el2_lib.scala 302:41] + _T_485[21] <= _T_529 @[el2_lib.scala 302:23] + node _T_530 = bits(_T_475, 5, 0) @[el2_lib.scala 302:35] + node _T_531 = eq(_T_530, UInt<5>("h017")) @[el2_lib.scala 302:41] + _T_485[22] <= _T_531 @[el2_lib.scala 302:23] + node _T_532 = bits(_T_475, 5, 0) @[el2_lib.scala 302:35] + node _T_533 = eq(_T_532, UInt<5>("h018")) @[el2_lib.scala 302:41] + _T_485[23] <= _T_533 @[el2_lib.scala 302:23] + node _T_534 = bits(_T_475, 5, 0) @[el2_lib.scala 302:35] + node _T_535 = eq(_T_534, UInt<5>("h019")) @[el2_lib.scala 302:41] + _T_485[24] <= _T_535 @[el2_lib.scala 302:23] + node _T_536 = bits(_T_475, 5, 0) @[el2_lib.scala 302:35] + node _T_537 = eq(_T_536, UInt<5>("h01a")) @[el2_lib.scala 302:41] + _T_485[25] <= _T_537 @[el2_lib.scala 302:23] + node _T_538 = bits(_T_475, 5, 0) @[el2_lib.scala 302:35] + node _T_539 = eq(_T_538, UInt<5>("h01b")) @[el2_lib.scala 302:41] + _T_485[26] <= _T_539 @[el2_lib.scala 302:23] + node _T_540 = bits(_T_475, 5, 0) @[el2_lib.scala 302:35] + node _T_541 = eq(_T_540, UInt<5>("h01c")) @[el2_lib.scala 302:41] + _T_485[27] <= _T_541 @[el2_lib.scala 302:23] + node _T_542 = bits(_T_475, 5, 0) @[el2_lib.scala 302:35] + node _T_543 = eq(_T_542, UInt<5>("h01d")) @[el2_lib.scala 302:41] + _T_485[28] <= _T_543 @[el2_lib.scala 302:23] + node _T_544 = bits(_T_475, 5, 0) @[el2_lib.scala 302:35] + node _T_545 = eq(_T_544, UInt<5>("h01e")) @[el2_lib.scala 302:41] + _T_485[29] <= _T_545 @[el2_lib.scala 302:23] + node _T_546 = bits(_T_475, 5, 0) @[el2_lib.scala 302:35] + node _T_547 = eq(_T_546, UInt<5>("h01f")) @[el2_lib.scala 302:41] + _T_485[30] <= _T_547 @[el2_lib.scala 302:23] + node _T_548 = bits(_T_475, 5, 0) @[el2_lib.scala 302:35] + node _T_549 = eq(_T_548, UInt<6>("h020")) @[el2_lib.scala 302:41] + _T_485[31] <= _T_549 @[el2_lib.scala 302:23] + node _T_550 = bits(_T_475, 5, 0) @[el2_lib.scala 302:35] + node _T_551 = eq(_T_550, UInt<6>("h021")) @[el2_lib.scala 302:41] + _T_485[32] <= _T_551 @[el2_lib.scala 302:23] + node _T_552 = bits(_T_475, 5, 0) @[el2_lib.scala 302:35] + node _T_553 = eq(_T_552, UInt<6>("h022")) @[el2_lib.scala 302:41] + _T_485[33] <= _T_553 @[el2_lib.scala 302:23] + node _T_554 = bits(_T_475, 5, 0) @[el2_lib.scala 302:35] + node _T_555 = eq(_T_554, UInt<6>("h023")) @[el2_lib.scala 302:41] + _T_485[34] <= _T_555 @[el2_lib.scala 302:23] + node _T_556 = bits(_T_475, 5, 0) @[el2_lib.scala 302:35] + node _T_557 = eq(_T_556, UInt<6>("h024")) @[el2_lib.scala 302:41] + _T_485[35] <= _T_557 @[el2_lib.scala 302:23] + node _T_558 = bits(_T_475, 5, 0) @[el2_lib.scala 302:35] + node _T_559 = eq(_T_558, UInt<6>("h025")) @[el2_lib.scala 302:41] + _T_485[36] <= _T_559 @[el2_lib.scala 302:23] + node _T_560 = bits(_T_475, 5, 0) @[el2_lib.scala 302:35] + node _T_561 = eq(_T_560, UInt<6>("h026")) @[el2_lib.scala 302:41] + _T_485[37] <= _T_561 @[el2_lib.scala 302:23] + node _T_562 = bits(_T_475, 5, 0) @[el2_lib.scala 302:35] + node _T_563 = eq(_T_562, UInt<6>("h027")) @[el2_lib.scala 302:41] + _T_485[38] <= _T_563 @[el2_lib.scala 302:23] + node _T_564 = bits(_T_266, 6, 6) @[el2_lib.scala 304:37] + node _T_565 = bits(_T_264, 31, 26) @[el2_lib.scala 304:45] + node _T_566 = bits(_T_266, 5, 5) @[el2_lib.scala 304:60] + node _T_567 = bits(_T_264, 25, 11) @[el2_lib.scala 304:68] + node _T_568 = bits(_T_266, 4, 4) @[el2_lib.scala 304:83] + node _T_569 = bits(_T_264, 10, 4) @[el2_lib.scala 304:91] + node _T_570 = bits(_T_266, 3, 3) @[el2_lib.scala 304:105] + node _T_571 = bits(_T_264, 3, 1) @[el2_lib.scala 304:113] + node _T_572 = bits(_T_266, 2, 2) @[el2_lib.scala 304:126] + node _T_573 = bits(_T_264, 0, 0) @[el2_lib.scala 304:134] + node _T_574 = bits(_T_266, 1, 0) @[el2_lib.scala 304:145] + node _T_575 = cat(_T_573, _T_574) @[Cat.scala 29:58] + node _T_576 = cat(_T_570, _T_571) @[Cat.scala 29:58] + node _T_577 = cat(_T_576, _T_572) @[Cat.scala 29:58] + node _T_578 = cat(_T_577, _T_575) @[Cat.scala 29:58] + node _T_579 = cat(_T_567, _T_568) @[Cat.scala 29:58] + node _T_580 = cat(_T_579, _T_569) @[Cat.scala 29:58] + node _T_581 = cat(_T_564, _T_565) @[Cat.scala 29:58] + node _T_582 = cat(_T_581, _T_566) @[Cat.scala 29:58] + node _T_583 = cat(_T_582, _T_580) @[Cat.scala 29:58] + node _T_584 = cat(_T_583, _T_578) @[Cat.scala 29:58] + node _T_585 = bits(_T_479, 0, 0) @[el2_lib.scala 305:49] + node _T_586 = cat(_T_485[1], _T_485[0]) @[el2_lib.scala 305:69] + node _T_587 = cat(_T_485[3], _T_485[2]) @[el2_lib.scala 305:69] + node _T_588 = cat(_T_587, _T_586) @[el2_lib.scala 305:69] + node _T_589 = cat(_T_485[5], _T_485[4]) @[el2_lib.scala 305:69] + node _T_590 = cat(_T_485[8], _T_485[7]) @[el2_lib.scala 305:69] + node _T_591 = cat(_T_590, _T_485[6]) @[el2_lib.scala 305:69] + node _T_592 = cat(_T_591, _T_589) @[el2_lib.scala 305:69] + node _T_593 = cat(_T_592, _T_588) @[el2_lib.scala 305:69] + node _T_594 = cat(_T_485[10], _T_485[9]) @[el2_lib.scala 305:69] + node _T_595 = cat(_T_485[13], _T_485[12]) @[el2_lib.scala 305:69] + node _T_596 = cat(_T_595, _T_485[11]) @[el2_lib.scala 305:69] + node _T_597 = cat(_T_596, _T_594) @[el2_lib.scala 305:69] + node _T_598 = cat(_T_485[15], _T_485[14]) @[el2_lib.scala 305:69] + node _T_599 = cat(_T_485[18], _T_485[17]) @[el2_lib.scala 305:69] + node _T_600 = cat(_T_599, _T_485[16]) @[el2_lib.scala 305:69] + node _T_601 = cat(_T_600, _T_598) @[el2_lib.scala 305:69] + node _T_602 = cat(_T_601, _T_597) @[el2_lib.scala 305:69] + node _T_603 = cat(_T_602, _T_593) @[el2_lib.scala 305:69] + node _T_604 = cat(_T_485[20], _T_485[19]) @[el2_lib.scala 305:69] + node _T_605 = cat(_T_485[23], _T_485[22]) @[el2_lib.scala 305:69] + node _T_606 = cat(_T_605, _T_485[21]) @[el2_lib.scala 305:69] + node _T_607 = cat(_T_606, _T_604) @[el2_lib.scala 305:69] + node _T_608 = cat(_T_485[25], _T_485[24]) @[el2_lib.scala 305:69] + node _T_609 = cat(_T_485[28], _T_485[27]) @[el2_lib.scala 305:69] + node _T_610 = cat(_T_609, _T_485[26]) @[el2_lib.scala 305:69] + node _T_611 = cat(_T_610, _T_608) @[el2_lib.scala 305:69] + node _T_612 = cat(_T_611, _T_607) @[el2_lib.scala 305:69] + node _T_613 = cat(_T_485[30], _T_485[29]) @[el2_lib.scala 305:69] + node _T_614 = cat(_T_485[33], _T_485[32]) @[el2_lib.scala 305:69] + node _T_615 = cat(_T_614, _T_485[31]) @[el2_lib.scala 305:69] + node _T_616 = cat(_T_615, _T_613) @[el2_lib.scala 305:69] + node _T_617 = cat(_T_485[35], _T_485[34]) @[el2_lib.scala 305:69] + node _T_618 = cat(_T_485[38], _T_485[37]) @[el2_lib.scala 305:69] + node _T_619 = cat(_T_618, _T_485[36]) @[el2_lib.scala 305:69] + node _T_620 = cat(_T_619, _T_617) @[el2_lib.scala 305:69] + node _T_621 = cat(_T_620, _T_616) @[el2_lib.scala 305:69] + node _T_622 = cat(_T_621, _T_612) @[el2_lib.scala 305:69] + node _T_623 = cat(_T_622, _T_603) @[el2_lib.scala 305:69] + node _T_624 = xor(_T_623, _T_584) @[el2_lib.scala 305:76] + node _T_625 = mux(_T_585, _T_624, _T_584) @[el2_lib.scala 305:31] + node _T_626 = bits(_T_625, 37, 32) @[el2_lib.scala 307:37] + node _T_627 = bits(_T_625, 30, 16) @[el2_lib.scala 307:61] + node _T_628 = bits(_T_625, 14, 8) @[el2_lib.scala 307:86] + node _T_629 = bits(_T_625, 6, 4) @[el2_lib.scala 307:110] + node _T_630 = bits(_T_625, 2, 2) @[el2_lib.scala 307:133] + node _T_631 = cat(_T_629, _T_630) @[Cat.scala 29:58] + node _T_632 = cat(_T_626, _T_627) @[Cat.scala 29:58] + node _T_633 = cat(_T_632, _T_628) @[Cat.scala 29:58] + node _T_634 = cat(_T_633, _T_631) @[Cat.scala 29:58] + node _T_635 = bits(_T_625, 38, 38) @[el2_lib.scala 308:39] + node _T_636 = bits(_T_475, 6, 0) @[el2_lib.scala 308:56] + node _T_637 = eq(_T_636, UInt<7>("h040")) @[el2_lib.scala 308:62] + node _T_638 = xor(_T_635, _T_637) @[el2_lib.scala 308:44] + node _T_639 = bits(_T_625, 31, 31) @[el2_lib.scala 308:102] + node _T_640 = bits(_T_625, 15, 15) @[el2_lib.scala 308:124] + node _T_641 = bits(_T_625, 7, 7) @[el2_lib.scala 308:146] + node _T_642 = bits(_T_625, 3, 3) @[el2_lib.scala 308:167] + node _T_643 = bits(_T_625, 1, 0) @[el2_lib.scala 308:188] + node _T_644 = cat(_T_641, _T_642) @[Cat.scala 29:58] + node _T_645 = cat(_T_644, _T_643) @[Cat.scala 29:58] + node _T_646 = cat(_T_638, _T_639) @[Cat.scala 29:58] + node _T_647 = cat(_T_646, _T_640) @[Cat.scala 29:58] + node _T_648 = cat(_T_647, _T_645) @[Cat.scala 29:58] + ic_tag_corrected_ecc_unc[0] <= _T_648 @[el2_ifu_ic_mem.scala 155:33] + ic_tag_corrected_data_unc[0] <= _T_634 @[el2_ifu_ic_mem.scala 156:34] + ic_tag_single_ecc_error[0] <= _T_479 @[el2_ifu_ic_mem.scala 157:31] + ic_tag_double_ecc_error[0] <= _T_484 @[el2_ifu_ic_mem.scala 158:32] + node _T_649 = not(io.dec_tlu_core_ecc_disable) @[el2_ifu_ic_mem.scala 153:51] + node _T_650 = and(_T_649, ic_rd_en_ff) @[el2_ifu_ic_mem.scala 153:80] + node _T_651 = bits(ic_tag_data_raw_1, 20, 0) @[el2_ifu_ic_mem.scala 153:127] + node _T_652 = cat(UInt<11>("h00"), _T_651) @[Cat.scala 29:58] + node _T_653 = bits(ic_tag_data_raw_1, 25, 21) @[el2_ifu_ic_mem.scala 153:167] + node _T_654 = cat(UInt<2>("h00"), _T_653) @[Cat.scala 29:58] + wire _T_655 : UInt<1>[18] @[el2_lib.scala 276:18] + wire _T_656 : UInt<1>[18] @[el2_lib.scala 277:18] + wire _T_657 : UInt<1>[18] @[el2_lib.scala 278:18] + wire _T_658 : UInt<1>[15] @[el2_lib.scala 279:18] + wire _T_659 : UInt<1>[15] @[el2_lib.scala 280:18] + wire _T_660 : UInt<1>[6] @[el2_lib.scala 281:18] + node _T_661 = bits(_T_652, 0, 0) @[el2_lib.scala 288:36] + _T_655[0] <= _T_661 @[el2_lib.scala 288:30] + node _T_662 = bits(_T_652, 0, 0) @[el2_lib.scala 289:36] + _T_656[0] <= _T_662 @[el2_lib.scala 289:30] + node _T_663 = bits(_T_652, 1, 1) @[el2_lib.scala 288:36] + _T_655[1] <= _T_663 @[el2_lib.scala 288:30] + node _T_664 = bits(_T_652, 1, 1) @[el2_lib.scala 290:36] + _T_657[0] <= _T_664 @[el2_lib.scala 290:30] + node _T_665 = bits(_T_652, 2, 2) @[el2_lib.scala 289:36] + _T_656[1] <= _T_665 @[el2_lib.scala 289:30] + node _T_666 = bits(_T_652, 2, 2) @[el2_lib.scala 290:36] + _T_657[1] <= _T_666 @[el2_lib.scala 290:30] + node _T_667 = bits(_T_652, 3, 3) @[el2_lib.scala 288:36] + _T_655[2] <= _T_667 @[el2_lib.scala 288:30] + node _T_668 = bits(_T_652, 3, 3) @[el2_lib.scala 289:36] + _T_656[2] <= _T_668 @[el2_lib.scala 289:30] + node _T_669 = bits(_T_652, 3, 3) @[el2_lib.scala 290:36] + _T_657[2] <= _T_669 @[el2_lib.scala 290:30] + node _T_670 = bits(_T_652, 4, 4) @[el2_lib.scala 288:36] + _T_655[3] <= _T_670 @[el2_lib.scala 288:30] + node _T_671 = bits(_T_652, 4, 4) @[el2_lib.scala 291:36] + _T_658[0] <= _T_671 @[el2_lib.scala 291:30] + node _T_672 = bits(_T_652, 5, 5) @[el2_lib.scala 289:36] + _T_656[3] <= _T_672 @[el2_lib.scala 289:30] + node _T_673 = bits(_T_652, 5, 5) @[el2_lib.scala 291:36] + _T_658[1] <= _T_673 @[el2_lib.scala 291:30] + node _T_674 = bits(_T_652, 6, 6) @[el2_lib.scala 288:36] + _T_655[4] <= _T_674 @[el2_lib.scala 288:30] + node _T_675 = bits(_T_652, 6, 6) @[el2_lib.scala 289:36] + _T_656[4] <= _T_675 @[el2_lib.scala 289:30] + node _T_676 = bits(_T_652, 6, 6) @[el2_lib.scala 291:36] + _T_658[2] <= _T_676 @[el2_lib.scala 291:30] + node _T_677 = bits(_T_652, 7, 7) @[el2_lib.scala 290:36] + _T_657[3] <= _T_677 @[el2_lib.scala 290:30] + node _T_678 = bits(_T_652, 7, 7) @[el2_lib.scala 291:36] + _T_658[3] <= _T_678 @[el2_lib.scala 291:30] + node _T_679 = bits(_T_652, 8, 8) @[el2_lib.scala 288:36] + _T_655[5] <= _T_679 @[el2_lib.scala 288:30] + node _T_680 = bits(_T_652, 8, 8) @[el2_lib.scala 290:36] + _T_657[4] <= _T_680 @[el2_lib.scala 290:30] + node _T_681 = bits(_T_652, 8, 8) @[el2_lib.scala 291:36] + _T_658[4] <= _T_681 @[el2_lib.scala 291:30] + node _T_682 = bits(_T_652, 9, 9) @[el2_lib.scala 289:36] + _T_656[5] <= _T_682 @[el2_lib.scala 289:30] + node _T_683 = bits(_T_652, 9, 9) @[el2_lib.scala 290:36] + _T_657[5] <= _T_683 @[el2_lib.scala 290:30] + node _T_684 = bits(_T_652, 9, 9) @[el2_lib.scala 291:36] + _T_658[5] <= _T_684 @[el2_lib.scala 291:30] + node _T_685 = bits(_T_652, 10, 10) @[el2_lib.scala 288:36] + _T_655[6] <= _T_685 @[el2_lib.scala 288:30] + node _T_686 = bits(_T_652, 10, 10) @[el2_lib.scala 289:36] + _T_656[6] <= _T_686 @[el2_lib.scala 289:30] + node _T_687 = bits(_T_652, 10, 10) @[el2_lib.scala 290:36] + _T_657[6] <= _T_687 @[el2_lib.scala 290:30] + node _T_688 = bits(_T_652, 10, 10) @[el2_lib.scala 291:36] + _T_658[6] <= _T_688 @[el2_lib.scala 291:30] + node _T_689 = bits(_T_652, 11, 11) @[el2_lib.scala 288:36] + _T_655[7] <= _T_689 @[el2_lib.scala 288:30] + node _T_690 = bits(_T_652, 11, 11) @[el2_lib.scala 292:36] + _T_659[0] <= _T_690 @[el2_lib.scala 292:30] + node _T_691 = bits(_T_652, 12, 12) @[el2_lib.scala 289:36] + _T_656[7] <= _T_691 @[el2_lib.scala 289:30] + node _T_692 = bits(_T_652, 12, 12) @[el2_lib.scala 292:36] + _T_659[1] <= _T_692 @[el2_lib.scala 292:30] + node _T_693 = bits(_T_652, 13, 13) @[el2_lib.scala 288:36] + _T_655[8] <= _T_693 @[el2_lib.scala 288:30] + node _T_694 = bits(_T_652, 13, 13) @[el2_lib.scala 289:36] + _T_656[8] <= _T_694 @[el2_lib.scala 289:30] + node _T_695 = bits(_T_652, 13, 13) @[el2_lib.scala 292:36] + _T_659[2] <= _T_695 @[el2_lib.scala 292:30] + node _T_696 = bits(_T_652, 14, 14) @[el2_lib.scala 290:36] + _T_657[7] <= _T_696 @[el2_lib.scala 290:30] + node _T_697 = bits(_T_652, 14, 14) @[el2_lib.scala 292:36] + _T_659[3] <= _T_697 @[el2_lib.scala 292:30] + node _T_698 = bits(_T_652, 15, 15) @[el2_lib.scala 288:36] + _T_655[9] <= _T_698 @[el2_lib.scala 288:30] + node _T_699 = bits(_T_652, 15, 15) @[el2_lib.scala 290:36] + _T_657[8] <= _T_699 @[el2_lib.scala 290:30] + node _T_700 = bits(_T_652, 15, 15) @[el2_lib.scala 292:36] + _T_659[4] <= _T_700 @[el2_lib.scala 292:30] + node _T_701 = bits(_T_652, 16, 16) @[el2_lib.scala 289:36] + _T_656[9] <= _T_701 @[el2_lib.scala 289:30] + node _T_702 = bits(_T_652, 16, 16) @[el2_lib.scala 290:36] + _T_657[9] <= _T_702 @[el2_lib.scala 290:30] + node _T_703 = bits(_T_652, 16, 16) @[el2_lib.scala 292:36] + _T_659[5] <= _T_703 @[el2_lib.scala 292:30] + node _T_704 = bits(_T_652, 17, 17) @[el2_lib.scala 288:36] + _T_655[10] <= _T_704 @[el2_lib.scala 288:30] + node _T_705 = bits(_T_652, 17, 17) @[el2_lib.scala 289:36] + _T_656[10] <= _T_705 @[el2_lib.scala 289:30] + node _T_706 = bits(_T_652, 17, 17) @[el2_lib.scala 290:36] + _T_657[10] <= _T_706 @[el2_lib.scala 290:30] + node _T_707 = bits(_T_652, 17, 17) @[el2_lib.scala 292:36] + _T_659[6] <= _T_707 @[el2_lib.scala 292:30] + node _T_708 = bits(_T_652, 18, 18) @[el2_lib.scala 291:36] + _T_658[7] <= _T_708 @[el2_lib.scala 291:30] + node _T_709 = bits(_T_652, 18, 18) @[el2_lib.scala 292:36] + _T_659[7] <= _T_709 @[el2_lib.scala 292:30] + node _T_710 = bits(_T_652, 19, 19) @[el2_lib.scala 288:36] + _T_655[11] <= _T_710 @[el2_lib.scala 288:30] + node _T_711 = bits(_T_652, 19, 19) @[el2_lib.scala 291:36] + _T_658[8] <= _T_711 @[el2_lib.scala 291:30] + node _T_712 = bits(_T_652, 19, 19) @[el2_lib.scala 292:36] + _T_659[8] <= _T_712 @[el2_lib.scala 292:30] + node _T_713 = bits(_T_652, 20, 20) @[el2_lib.scala 289:36] + _T_656[11] <= _T_713 @[el2_lib.scala 289:30] + node _T_714 = bits(_T_652, 20, 20) @[el2_lib.scala 291:36] + _T_658[9] <= _T_714 @[el2_lib.scala 291:30] + node _T_715 = bits(_T_652, 20, 20) @[el2_lib.scala 292:36] + _T_659[9] <= _T_715 @[el2_lib.scala 292:30] + node _T_716 = bits(_T_652, 21, 21) @[el2_lib.scala 288:36] + _T_655[12] <= _T_716 @[el2_lib.scala 288:30] + node _T_717 = bits(_T_652, 21, 21) @[el2_lib.scala 289:36] + _T_656[12] <= _T_717 @[el2_lib.scala 289:30] + node _T_718 = bits(_T_652, 21, 21) @[el2_lib.scala 291:36] + _T_658[10] <= _T_718 @[el2_lib.scala 291:30] + node _T_719 = bits(_T_652, 21, 21) @[el2_lib.scala 292:36] + _T_659[10] <= _T_719 @[el2_lib.scala 292:30] + node _T_720 = bits(_T_652, 22, 22) @[el2_lib.scala 290:36] + _T_657[11] <= _T_720 @[el2_lib.scala 290:30] + node _T_721 = bits(_T_652, 22, 22) @[el2_lib.scala 291:36] + _T_658[11] <= _T_721 @[el2_lib.scala 291:30] + node _T_722 = bits(_T_652, 22, 22) @[el2_lib.scala 292:36] + _T_659[11] <= _T_722 @[el2_lib.scala 292:30] + node _T_723 = bits(_T_652, 23, 23) @[el2_lib.scala 288:36] + _T_655[13] <= _T_723 @[el2_lib.scala 288:30] + node _T_724 = bits(_T_652, 23, 23) @[el2_lib.scala 290:36] + _T_657[12] <= _T_724 @[el2_lib.scala 290:30] + node _T_725 = bits(_T_652, 23, 23) @[el2_lib.scala 291:36] + _T_658[12] <= _T_725 @[el2_lib.scala 291:30] + node _T_726 = bits(_T_652, 23, 23) @[el2_lib.scala 292:36] + _T_659[12] <= _T_726 @[el2_lib.scala 292:30] + node _T_727 = bits(_T_652, 24, 24) @[el2_lib.scala 289:36] + _T_656[13] <= _T_727 @[el2_lib.scala 289:30] + node _T_728 = bits(_T_652, 24, 24) @[el2_lib.scala 290:36] + _T_657[13] <= _T_728 @[el2_lib.scala 290:30] + node _T_729 = bits(_T_652, 24, 24) @[el2_lib.scala 291:36] + _T_658[13] <= _T_729 @[el2_lib.scala 291:30] + node _T_730 = bits(_T_652, 24, 24) @[el2_lib.scala 292:36] + _T_659[13] <= _T_730 @[el2_lib.scala 292:30] + node _T_731 = bits(_T_652, 25, 25) @[el2_lib.scala 288:36] + _T_655[14] <= _T_731 @[el2_lib.scala 288:30] + node _T_732 = bits(_T_652, 25, 25) @[el2_lib.scala 289:36] + _T_656[14] <= _T_732 @[el2_lib.scala 289:30] + node _T_733 = bits(_T_652, 25, 25) @[el2_lib.scala 290:36] + _T_657[14] <= _T_733 @[el2_lib.scala 290:30] + node _T_734 = bits(_T_652, 25, 25) @[el2_lib.scala 291:36] + _T_658[14] <= _T_734 @[el2_lib.scala 291:30] + node _T_735 = bits(_T_652, 25, 25) @[el2_lib.scala 292:36] + _T_659[14] <= _T_735 @[el2_lib.scala 292:30] + node _T_736 = bits(_T_652, 26, 26) @[el2_lib.scala 288:36] + _T_655[15] <= _T_736 @[el2_lib.scala 288:30] + node _T_737 = bits(_T_652, 26, 26) @[el2_lib.scala 293:36] + _T_660[0] <= _T_737 @[el2_lib.scala 293:30] + node _T_738 = bits(_T_652, 27, 27) @[el2_lib.scala 289:36] + _T_656[15] <= _T_738 @[el2_lib.scala 289:30] + node _T_739 = bits(_T_652, 27, 27) @[el2_lib.scala 293:36] + _T_660[1] <= _T_739 @[el2_lib.scala 293:30] + node _T_740 = bits(_T_652, 28, 28) @[el2_lib.scala 288:36] + _T_655[16] <= _T_740 @[el2_lib.scala 288:30] + node _T_741 = bits(_T_652, 28, 28) @[el2_lib.scala 289:36] + _T_656[16] <= _T_741 @[el2_lib.scala 289:30] + node _T_742 = bits(_T_652, 28, 28) @[el2_lib.scala 293:36] + _T_660[2] <= _T_742 @[el2_lib.scala 293:30] + node _T_743 = bits(_T_652, 29, 29) @[el2_lib.scala 290:36] + _T_657[15] <= _T_743 @[el2_lib.scala 290:30] + node _T_744 = bits(_T_652, 29, 29) @[el2_lib.scala 293:36] + _T_660[3] <= _T_744 @[el2_lib.scala 293:30] + node _T_745 = bits(_T_652, 30, 30) @[el2_lib.scala 288:36] + _T_655[17] <= _T_745 @[el2_lib.scala 288:30] + node _T_746 = bits(_T_652, 30, 30) @[el2_lib.scala 290:36] + _T_657[16] <= _T_746 @[el2_lib.scala 290:30] + node _T_747 = bits(_T_652, 30, 30) @[el2_lib.scala 293:36] + _T_660[4] <= _T_747 @[el2_lib.scala 293:30] + node _T_748 = bits(_T_652, 31, 31) @[el2_lib.scala 289:36] + _T_656[17] <= _T_748 @[el2_lib.scala 289:30] + node _T_749 = bits(_T_652, 31, 31) @[el2_lib.scala 290:36] + _T_657[17] <= _T_749 @[el2_lib.scala 290:30] + node _T_750 = bits(_T_652, 31, 31) @[el2_lib.scala 293:36] + _T_660[5] <= _T_750 @[el2_lib.scala 293:30] + node _T_751 = xorr(_T_652) @[el2_lib.scala 296:30] + node _T_752 = xorr(_T_654) @[el2_lib.scala 296:44] + node _T_753 = xor(_T_751, _T_752) @[el2_lib.scala 296:35] + node _T_754 = not(UInt<1>("h01")) @[el2_lib.scala 296:52] + node _T_755 = and(_T_753, _T_754) @[el2_lib.scala 296:50] + node _T_756 = bits(_T_654, 5, 5) @[el2_lib.scala 296:68] + node _T_757 = cat(_T_660[2], _T_660[1]) @[el2_lib.scala 296:76] + node _T_758 = cat(_T_757, _T_660[0]) @[el2_lib.scala 296:76] + node _T_759 = cat(_T_660[5], _T_660[4]) @[el2_lib.scala 296:76] + node _T_760 = cat(_T_759, _T_660[3]) @[el2_lib.scala 296:76] + node _T_761 = cat(_T_760, _T_758) @[el2_lib.scala 296:76] + node _T_762 = xorr(_T_761) @[el2_lib.scala 296:83] + node _T_763 = xor(_T_756, _T_762) @[el2_lib.scala 296:71] + node _T_764 = bits(_T_654, 4, 4) @[el2_lib.scala 296:95] + node _T_765 = cat(_T_659[2], _T_659[1]) @[el2_lib.scala 296:103] + node _T_766 = cat(_T_765, _T_659[0]) @[el2_lib.scala 296:103] + node _T_767 = cat(_T_659[4], _T_659[3]) @[el2_lib.scala 296:103] + node _T_768 = cat(_T_659[6], _T_659[5]) @[el2_lib.scala 296:103] + node _T_769 = cat(_T_768, _T_767) @[el2_lib.scala 296:103] + node _T_770 = cat(_T_769, _T_766) @[el2_lib.scala 296:103] + node _T_771 = cat(_T_659[8], _T_659[7]) @[el2_lib.scala 296:103] + node _T_772 = cat(_T_659[10], _T_659[9]) @[el2_lib.scala 296:103] + node _T_773 = cat(_T_772, _T_771) @[el2_lib.scala 296:103] + node _T_774 = cat(_T_659[12], _T_659[11]) @[el2_lib.scala 296:103] + node _T_775 = cat(_T_659[14], _T_659[13]) @[el2_lib.scala 296:103] + node _T_776 = cat(_T_775, _T_774) @[el2_lib.scala 296:103] + node _T_777 = cat(_T_776, _T_773) @[el2_lib.scala 296:103] + node _T_778 = cat(_T_777, _T_770) @[el2_lib.scala 296:103] + node _T_779 = xorr(_T_778) @[el2_lib.scala 296:110] + node _T_780 = xor(_T_764, _T_779) @[el2_lib.scala 296:98] + node _T_781 = bits(_T_654, 3, 3) @[el2_lib.scala 296:122] + node _T_782 = cat(_T_658[2], _T_658[1]) @[el2_lib.scala 296:130] + node _T_783 = cat(_T_782, _T_658[0]) @[el2_lib.scala 296:130] + node _T_784 = cat(_T_658[4], _T_658[3]) @[el2_lib.scala 296:130] + node _T_785 = cat(_T_658[6], _T_658[5]) @[el2_lib.scala 296:130] + node _T_786 = cat(_T_785, _T_784) @[el2_lib.scala 296:130] + node _T_787 = cat(_T_786, _T_783) @[el2_lib.scala 296:130] + node _T_788 = cat(_T_658[8], _T_658[7]) @[el2_lib.scala 296:130] + node _T_789 = cat(_T_658[10], _T_658[9]) @[el2_lib.scala 296:130] + node _T_790 = cat(_T_789, _T_788) @[el2_lib.scala 296:130] + node _T_791 = cat(_T_658[12], _T_658[11]) @[el2_lib.scala 296:130] + node _T_792 = cat(_T_658[14], _T_658[13]) @[el2_lib.scala 296:130] + node _T_793 = cat(_T_792, _T_791) @[el2_lib.scala 296:130] + node _T_794 = cat(_T_793, _T_790) @[el2_lib.scala 296:130] + node _T_795 = cat(_T_794, _T_787) @[el2_lib.scala 296:130] + node _T_796 = xorr(_T_795) @[el2_lib.scala 296:137] + node _T_797 = xor(_T_781, _T_796) @[el2_lib.scala 296:125] + node _T_798 = bits(_T_654, 2, 2) @[el2_lib.scala 296:149] + node _T_799 = cat(_T_657[1], _T_657[0]) @[el2_lib.scala 296:157] + node _T_800 = cat(_T_657[3], _T_657[2]) @[el2_lib.scala 296:157] + node _T_801 = cat(_T_800, _T_799) @[el2_lib.scala 296:157] + node _T_802 = cat(_T_657[5], _T_657[4]) @[el2_lib.scala 296:157] + node _T_803 = cat(_T_657[8], _T_657[7]) @[el2_lib.scala 296:157] + node _T_804 = cat(_T_803, _T_657[6]) @[el2_lib.scala 296:157] + node _T_805 = cat(_T_804, _T_802) @[el2_lib.scala 296:157] + node _T_806 = cat(_T_805, _T_801) @[el2_lib.scala 296:157] + node _T_807 = cat(_T_657[10], _T_657[9]) @[el2_lib.scala 296:157] + node _T_808 = cat(_T_657[12], _T_657[11]) @[el2_lib.scala 296:157] + node _T_809 = cat(_T_808, _T_807) @[el2_lib.scala 296:157] + node _T_810 = cat(_T_657[14], _T_657[13]) @[el2_lib.scala 296:157] + node _T_811 = cat(_T_657[17], _T_657[16]) @[el2_lib.scala 296:157] + node _T_812 = cat(_T_811, _T_657[15]) @[el2_lib.scala 296:157] + node _T_813 = cat(_T_812, _T_810) @[el2_lib.scala 296:157] + node _T_814 = cat(_T_813, _T_809) @[el2_lib.scala 296:157] + node _T_815 = cat(_T_814, _T_806) @[el2_lib.scala 296:157] + node _T_816 = xorr(_T_815) @[el2_lib.scala 296:164] + node _T_817 = xor(_T_798, _T_816) @[el2_lib.scala 296:152] + node _T_818 = bits(_T_654, 1, 1) @[el2_lib.scala 296:176] + node _T_819 = cat(_T_656[1], _T_656[0]) @[el2_lib.scala 296:184] + node _T_820 = cat(_T_656[3], _T_656[2]) @[el2_lib.scala 296:184] + node _T_821 = cat(_T_820, _T_819) @[el2_lib.scala 296:184] + node _T_822 = cat(_T_656[5], _T_656[4]) @[el2_lib.scala 296:184] + node _T_823 = cat(_T_656[8], _T_656[7]) @[el2_lib.scala 296:184] + node _T_824 = cat(_T_823, _T_656[6]) @[el2_lib.scala 296:184] + node _T_825 = cat(_T_824, _T_822) @[el2_lib.scala 296:184] + node _T_826 = cat(_T_825, _T_821) @[el2_lib.scala 296:184] + node _T_827 = cat(_T_656[10], _T_656[9]) @[el2_lib.scala 296:184] + node _T_828 = cat(_T_656[12], _T_656[11]) @[el2_lib.scala 296:184] + node _T_829 = cat(_T_828, _T_827) @[el2_lib.scala 296:184] + node _T_830 = cat(_T_656[14], _T_656[13]) @[el2_lib.scala 296:184] + node _T_831 = cat(_T_656[17], _T_656[16]) @[el2_lib.scala 296:184] + node _T_832 = cat(_T_831, _T_656[15]) @[el2_lib.scala 296:184] + node _T_833 = cat(_T_832, _T_830) @[el2_lib.scala 296:184] + node _T_834 = cat(_T_833, _T_829) @[el2_lib.scala 296:184] + node _T_835 = cat(_T_834, _T_826) @[el2_lib.scala 296:184] + node _T_836 = xorr(_T_835) @[el2_lib.scala 296:191] + node _T_837 = xor(_T_818, _T_836) @[el2_lib.scala 296:179] + node _T_838 = bits(_T_654, 0, 0) @[el2_lib.scala 296:203] + node _T_839 = cat(_T_655[1], _T_655[0]) @[el2_lib.scala 296:211] + node _T_840 = cat(_T_655[3], _T_655[2]) @[el2_lib.scala 296:211] + node _T_841 = cat(_T_840, _T_839) @[el2_lib.scala 296:211] + node _T_842 = cat(_T_655[5], _T_655[4]) @[el2_lib.scala 296:211] + node _T_843 = cat(_T_655[8], _T_655[7]) @[el2_lib.scala 296:211] + node _T_844 = cat(_T_843, _T_655[6]) @[el2_lib.scala 296:211] + node _T_845 = cat(_T_844, _T_842) @[el2_lib.scala 296:211] + node _T_846 = cat(_T_845, _T_841) @[el2_lib.scala 296:211] + node _T_847 = cat(_T_655[10], _T_655[9]) @[el2_lib.scala 296:211] + node _T_848 = cat(_T_655[12], _T_655[11]) @[el2_lib.scala 296:211] + node _T_849 = cat(_T_848, _T_847) @[el2_lib.scala 296:211] + node _T_850 = cat(_T_655[14], _T_655[13]) @[el2_lib.scala 296:211] + node _T_851 = cat(_T_655[17], _T_655[16]) @[el2_lib.scala 296:211] + node _T_852 = cat(_T_851, _T_655[15]) @[el2_lib.scala 296:211] + node _T_853 = cat(_T_852, _T_850) @[el2_lib.scala 296:211] + node _T_854 = cat(_T_853, _T_849) @[el2_lib.scala 296:211] + node _T_855 = cat(_T_854, _T_846) @[el2_lib.scala 296:211] + node _T_856 = xorr(_T_855) @[el2_lib.scala 296:218] + node _T_857 = xor(_T_838, _T_856) @[el2_lib.scala 296:206] + node _T_858 = cat(_T_817, _T_837) @[Cat.scala 29:58] + node _T_859 = cat(_T_858, _T_857) @[Cat.scala 29:58] + node _T_860 = cat(_T_780, _T_797) @[Cat.scala 29:58] + node _T_861 = cat(_T_755, _T_763) @[Cat.scala 29:58] + node _T_862 = cat(_T_861, _T_860) @[Cat.scala 29:58] + node _T_863 = cat(_T_862, _T_859) @[Cat.scala 29:58] + node _T_864 = neq(_T_863, UInt<1>("h00")) @[el2_lib.scala 297:44] + node _T_865 = and(_T_650, _T_864) @[el2_lib.scala 297:32] + node _T_866 = bits(_T_863, 6, 6) @[el2_lib.scala 297:64] + node _T_867 = and(_T_865, _T_866) @[el2_lib.scala 297:53] + node _T_868 = neq(_T_863, UInt<1>("h00")) @[el2_lib.scala 298:44] + node _T_869 = and(_T_650, _T_868) @[el2_lib.scala 298:32] + node _T_870 = bits(_T_863, 6, 6) @[el2_lib.scala 298:65] + node _T_871 = not(_T_870) @[el2_lib.scala 298:55] + node _T_872 = and(_T_869, _T_871) @[el2_lib.scala 298:53] + wire _T_873 : UInt<1>[39] @[el2_lib.scala 299:26] + node _T_874 = bits(_T_863, 5, 0) @[el2_lib.scala 302:35] + node _T_875 = eq(_T_874, UInt<1>("h01")) @[el2_lib.scala 302:41] + _T_873[0] <= _T_875 @[el2_lib.scala 302:23] + node _T_876 = bits(_T_863, 5, 0) @[el2_lib.scala 302:35] + node _T_877 = eq(_T_876, UInt<2>("h02")) @[el2_lib.scala 302:41] + _T_873[1] <= _T_877 @[el2_lib.scala 302:23] + node _T_878 = bits(_T_863, 5, 0) @[el2_lib.scala 302:35] + node _T_879 = eq(_T_878, UInt<2>("h03")) @[el2_lib.scala 302:41] + _T_873[2] <= _T_879 @[el2_lib.scala 302:23] + node _T_880 = bits(_T_863, 5, 0) @[el2_lib.scala 302:35] + node _T_881 = eq(_T_880, UInt<3>("h04")) @[el2_lib.scala 302:41] + _T_873[3] <= _T_881 @[el2_lib.scala 302:23] + node _T_882 = bits(_T_863, 5, 0) @[el2_lib.scala 302:35] + node _T_883 = eq(_T_882, UInt<3>("h05")) @[el2_lib.scala 302:41] + _T_873[4] <= _T_883 @[el2_lib.scala 302:23] + node _T_884 = bits(_T_863, 5, 0) @[el2_lib.scala 302:35] + node _T_885 = eq(_T_884, UInt<3>("h06")) @[el2_lib.scala 302:41] + _T_873[5] <= _T_885 @[el2_lib.scala 302:23] + node _T_886 = bits(_T_863, 5, 0) @[el2_lib.scala 302:35] + node _T_887 = eq(_T_886, UInt<3>("h07")) @[el2_lib.scala 302:41] + _T_873[6] <= _T_887 @[el2_lib.scala 302:23] + node _T_888 = bits(_T_863, 5, 0) @[el2_lib.scala 302:35] + node _T_889 = eq(_T_888, UInt<4>("h08")) @[el2_lib.scala 302:41] + _T_873[7] <= _T_889 @[el2_lib.scala 302:23] + node _T_890 = bits(_T_863, 5, 0) @[el2_lib.scala 302:35] + node _T_891 = eq(_T_890, UInt<4>("h09")) @[el2_lib.scala 302:41] + _T_873[8] <= _T_891 @[el2_lib.scala 302:23] + node _T_892 = bits(_T_863, 5, 0) @[el2_lib.scala 302:35] + node _T_893 = eq(_T_892, UInt<4>("h0a")) @[el2_lib.scala 302:41] + _T_873[9] <= _T_893 @[el2_lib.scala 302:23] + node _T_894 = bits(_T_863, 5, 0) @[el2_lib.scala 302:35] + node _T_895 = eq(_T_894, UInt<4>("h0b")) @[el2_lib.scala 302:41] + _T_873[10] <= _T_895 @[el2_lib.scala 302:23] + node _T_896 = bits(_T_863, 5, 0) @[el2_lib.scala 302:35] + node _T_897 = eq(_T_896, UInt<4>("h0c")) @[el2_lib.scala 302:41] + _T_873[11] <= _T_897 @[el2_lib.scala 302:23] + node _T_898 = bits(_T_863, 5, 0) @[el2_lib.scala 302:35] + node _T_899 = eq(_T_898, UInt<4>("h0d")) @[el2_lib.scala 302:41] + _T_873[12] <= _T_899 @[el2_lib.scala 302:23] + node _T_900 = bits(_T_863, 5, 0) @[el2_lib.scala 302:35] + node _T_901 = eq(_T_900, UInt<4>("h0e")) @[el2_lib.scala 302:41] + _T_873[13] <= _T_901 @[el2_lib.scala 302:23] + node _T_902 = bits(_T_863, 5, 0) @[el2_lib.scala 302:35] + node _T_903 = eq(_T_902, UInt<4>("h0f")) @[el2_lib.scala 302:41] + _T_873[14] <= _T_903 @[el2_lib.scala 302:23] + node _T_904 = bits(_T_863, 5, 0) @[el2_lib.scala 302:35] + node _T_905 = eq(_T_904, UInt<5>("h010")) @[el2_lib.scala 302:41] + _T_873[15] <= _T_905 @[el2_lib.scala 302:23] + node _T_906 = bits(_T_863, 5, 0) @[el2_lib.scala 302:35] + node _T_907 = eq(_T_906, UInt<5>("h011")) @[el2_lib.scala 302:41] + _T_873[16] <= _T_907 @[el2_lib.scala 302:23] + node _T_908 = bits(_T_863, 5, 0) @[el2_lib.scala 302:35] + node _T_909 = eq(_T_908, UInt<5>("h012")) @[el2_lib.scala 302:41] + _T_873[17] <= _T_909 @[el2_lib.scala 302:23] + node _T_910 = bits(_T_863, 5, 0) @[el2_lib.scala 302:35] + node _T_911 = eq(_T_910, UInt<5>("h013")) @[el2_lib.scala 302:41] + _T_873[18] <= _T_911 @[el2_lib.scala 302:23] + node _T_912 = bits(_T_863, 5, 0) @[el2_lib.scala 302:35] + node _T_913 = eq(_T_912, UInt<5>("h014")) @[el2_lib.scala 302:41] + _T_873[19] <= _T_913 @[el2_lib.scala 302:23] + node _T_914 = bits(_T_863, 5, 0) @[el2_lib.scala 302:35] + node _T_915 = eq(_T_914, UInt<5>("h015")) @[el2_lib.scala 302:41] + _T_873[20] <= _T_915 @[el2_lib.scala 302:23] + node _T_916 = bits(_T_863, 5, 0) @[el2_lib.scala 302:35] + node _T_917 = eq(_T_916, UInt<5>("h016")) @[el2_lib.scala 302:41] + _T_873[21] <= _T_917 @[el2_lib.scala 302:23] + node _T_918 = bits(_T_863, 5, 0) @[el2_lib.scala 302:35] + node _T_919 = eq(_T_918, UInt<5>("h017")) @[el2_lib.scala 302:41] + _T_873[22] <= _T_919 @[el2_lib.scala 302:23] + node _T_920 = bits(_T_863, 5, 0) @[el2_lib.scala 302:35] + node _T_921 = eq(_T_920, UInt<5>("h018")) @[el2_lib.scala 302:41] + _T_873[23] <= _T_921 @[el2_lib.scala 302:23] + node _T_922 = bits(_T_863, 5, 0) @[el2_lib.scala 302:35] + node _T_923 = eq(_T_922, UInt<5>("h019")) @[el2_lib.scala 302:41] + _T_873[24] <= _T_923 @[el2_lib.scala 302:23] + node _T_924 = bits(_T_863, 5, 0) @[el2_lib.scala 302:35] + node _T_925 = eq(_T_924, UInt<5>("h01a")) @[el2_lib.scala 302:41] + _T_873[25] <= _T_925 @[el2_lib.scala 302:23] + node _T_926 = bits(_T_863, 5, 0) @[el2_lib.scala 302:35] + node _T_927 = eq(_T_926, UInt<5>("h01b")) @[el2_lib.scala 302:41] + _T_873[26] <= _T_927 @[el2_lib.scala 302:23] + node _T_928 = bits(_T_863, 5, 0) @[el2_lib.scala 302:35] + node _T_929 = eq(_T_928, UInt<5>("h01c")) @[el2_lib.scala 302:41] + _T_873[27] <= _T_929 @[el2_lib.scala 302:23] + node _T_930 = bits(_T_863, 5, 0) @[el2_lib.scala 302:35] + node _T_931 = eq(_T_930, UInt<5>("h01d")) @[el2_lib.scala 302:41] + _T_873[28] <= _T_931 @[el2_lib.scala 302:23] + node _T_932 = bits(_T_863, 5, 0) @[el2_lib.scala 302:35] + node _T_933 = eq(_T_932, UInt<5>("h01e")) @[el2_lib.scala 302:41] + _T_873[29] <= _T_933 @[el2_lib.scala 302:23] + node _T_934 = bits(_T_863, 5, 0) @[el2_lib.scala 302:35] + node _T_935 = eq(_T_934, UInt<5>("h01f")) @[el2_lib.scala 302:41] + _T_873[30] <= _T_935 @[el2_lib.scala 302:23] + node _T_936 = bits(_T_863, 5, 0) @[el2_lib.scala 302:35] + node _T_937 = eq(_T_936, UInt<6>("h020")) @[el2_lib.scala 302:41] + _T_873[31] <= _T_937 @[el2_lib.scala 302:23] + node _T_938 = bits(_T_863, 5, 0) @[el2_lib.scala 302:35] + node _T_939 = eq(_T_938, UInt<6>("h021")) @[el2_lib.scala 302:41] + _T_873[32] <= _T_939 @[el2_lib.scala 302:23] + node _T_940 = bits(_T_863, 5, 0) @[el2_lib.scala 302:35] + node _T_941 = eq(_T_940, UInt<6>("h022")) @[el2_lib.scala 302:41] + _T_873[33] <= _T_941 @[el2_lib.scala 302:23] + node _T_942 = bits(_T_863, 5, 0) @[el2_lib.scala 302:35] + node _T_943 = eq(_T_942, UInt<6>("h023")) @[el2_lib.scala 302:41] + _T_873[34] <= _T_943 @[el2_lib.scala 302:23] + node _T_944 = bits(_T_863, 5, 0) @[el2_lib.scala 302:35] + node _T_945 = eq(_T_944, UInt<6>("h024")) @[el2_lib.scala 302:41] + _T_873[35] <= _T_945 @[el2_lib.scala 302:23] + node _T_946 = bits(_T_863, 5, 0) @[el2_lib.scala 302:35] + node _T_947 = eq(_T_946, UInt<6>("h025")) @[el2_lib.scala 302:41] + _T_873[36] <= _T_947 @[el2_lib.scala 302:23] + node _T_948 = bits(_T_863, 5, 0) @[el2_lib.scala 302:35] + node _T_949 = eq(_T_948, UInt<6>("h026")) @[el2_lib.scala 302:41] + _T_873[37] <= _T_949 @[el2_lib.scala 302:23] + node _T_950 = bits(_T_863, 5, 0) @[el2_lib.scala 302:35] + node _T_951 = eq(_T_950, UInt<6>("h027")) @[el2_lib.scala 302:41] + _T_873[38] <= _T_951 @[el2_lib.scala 302:23] + node _T_952 = bits(_T_654, 6, 6) @[el2_lib.scala 304:37] + node _T_953 = bits(_T_652, 31, 26) @[el2_lib.scala 304:45] + node _T_954 = bits(_T_654, 5, 5) @[el2_lib.scala 304:60] + node _T_955 = bits(_T_652, 25, 11) @[el2_lib.scala 304:68] + node _T_956 = bits(_T_654, 4, 4) @[el2_lib.scala 304:83] + node _T_957 = bits(_T_652, 10, 4) @[el2_lib.scala 304:91] + node _T_958 = bits(_T_654, 3, 3) @[el2_lib.scala 304:105] + node _T_959 = bits(_T_652, 3, 1) @[el2_lib.scala 304:113] + node _T_960 = bits(_T_654, 2, 2) @[el2_lib.scala 304:126] + node _T_961 = bits(_T_652, 0, 0) @[el2_lib.scala 304:134] + node _T_962 = bits(_T_654, 1, 0) @[el2_lib.scala 304:145] + node _T_963 = cat(_T_961, _T_962) @[Cat.scala 29:58] + node _T_964 = cat(_T_958, _T_959) @[Cat.scala 29:58] + node _T_965 = cat(_T_964, _T_960) @[Cat.scala 29:58] + node _T_966 = cat(_T_965, _T_963) @[Cat.scala 29:58] + node _T_967 = cat(_T_955, _T_956) @[Cat.scala 29:58] + node _T_968 = cat(_T_967, _T_957) @[Cat.scala 29:58] + node _T_969 = cat(_T_952, _T_953) @[Cat.scala 29:58] + node _T_970 = cat(_T_969, _T_954) @[Cat.scala 29:58] + node _T_971 = cat(_T_970, _T_968) @[Cat.scala 29:58] + node _T_972 = cat(_T_971, _T_966) @[Cat.scala 29:58] + node _T_973 = bits(_T_867, 0, 0) @[el2_lib.scala 305:49] + node _T_974 = cat(_T_873[1], _T_873[0]) @[el2_lib.scala 305:69] + node _T_975 = cat(_T_873[3], _T_873[2]) @[el2_lib.scala 305:69] + node _T_976 = cat(_T_975, _T_974) @[el2_lib.scala 305:69] + node _T_977 = cat(_T_873[5], _T_873[4]) @[el2_lib.scala 305:69] + node _T_978 = cat(_T_873[8], _T_873[7]) @[el2_lib.scala 305:69] + node _T_979 = cat(_T_978, _T_873[6]) @[el2_lib.scala 305:69] + node _T_980 = cat(_T_979, _T_977) @[el2_lib.scala 305:69] + node _T_981 = cat(_T_980, _T_976) @[el2_lib.scala 305:69] + node _T_982 = cat(_T_873[10], _T_873[9]) @[el2_lib.scala 305:69] + node _T_983 = cat(_T_873[13], _T_873[12]) @[el2_lib.scala 305:69] + node _T_984 = cat(_T_983, _T_873[11]) @[el2_lib.scala 305:69] + node _T_985 = cat(_T_984, _T_982) @[el2_lib.scala 305:69] + node _T_986 = cat(_T_873[15], _T_873[14]) @[el2_lib.scala 305:69] + node _T_987 = cat(_T_873[18], _T_873[17]) @[el2_lib.scala 305:69] + node _T_988 = cat(_T_987, _T_873[16]) @[el2_lib.scala 305:69] + node _T_989 = cat(_T_988, _T_986) @[el2_lib.scala 305:69] + node _T_990 = cat(_T_989, _T_985) @[el2_lib.scala 305:69] + node _T_991 = cat(_T_990, _T_981) @[el2_lib.scala 305:69] + node _T_992 = cat(_T_873[20], _T_873[19]) @[el2_lib.scala 305:69] + node _T_993 = cat(_T_873[23], _T_873[22]) @[el2_lib.scala 305:69] + node _T_994 = cat(_T_993, _T_873[21]) @[el2_lib.scala 305:69] + node _T_995 = cat(_T_994, _T_992) @[el2_lib.scala 305:69] + node _T_996 = cat(_T_873[25], _T_873[24]) @[el2_lib.scala 305:69] + node _T_997 = cat(_T_873[28], _T_873[27]) @[el2_lib.scala 305:69] + node _T_998 = cat(_T_997, _T_873[26]) @[el2_lib.scala 305:69] + node _T_999 = cat(_T_998, _T_996) @[el2_lib.scala 305:69] + node _T_1000 = cat(_T_999, _T_995) @[el2_lib.scala 305:69] + node _T_1001 = cat(_T_873[30], _T_873[29]) @[el2_lib.scala 305:69] + node _T_1002 = cat(_T_873[33], _T_873[32]) @[el2_lib.scala 305:69] + node _T_1003 = cat(_T_1002, _T_873[31]) @[el2_lib.scala 305:69] + node _T_1004 = cat(_T_1003, _T_1001) @[el2_lib.scala 305:69] + node _T_1005 = cat(_T_873[35], _T_873[34]) @[el2_lib.scala 305:69] + node _T_1006 = cat(_T_873[38], _T_873[37]) @[el2_lib.scala 305:69] + node _T_1007 = cat(_T_1006, _T_873[36]) @[el2_lib.scala 305:69] + node _T_1008 = cat(_T_1007, _T_1005) @[el2_lib.scala 305:69] + node _T_1009 = cat(_T_1008, _T_1004) @[el2_lib.scala 305:69] + node _T_1010 = cat(_T_1009, _T_1000) @[el2_lib.scala 305:69] + node _T_1011 = cat(_T_1010, _T_991) @[el2_lib.scala 305:69] + node _T_1012 = xor(_T_1011, _T_972) @[el2_lib.scala 305:76] + node _T_1013 = mux(_T_973, _T_1012, _T_972) @[el2_lib.scala 305:31] + node _T_1014 = bits(_T_1013, 37, 32) @[el2_lib.scala 307:37] + node _T_1015 = bits(_T_1013, 30, 16) @[el2_lib.scala 307:61] + node _T_1016 = bits(_T_1013, 14, 8) @[el2_lib.scala 307:86] + node _T_1017 = bits(_T_1013, 6, 4) @[el2_lib.scala 307:110] + node _T_1018 = bits(_T_1013, 2, 2) @[el2_lib.scala 307:133] + node _T_1019 = cat(_T_1017, _T_1018) @[Cat.scala 29:58] + node _T_1020 = cat(_T_1014, _T_1015) @[Cat.scala 29:58] + node _T_1021 = cat(_T_1020, _T_1016) @[Cat.scala 29:58] + node _T_1022 = cat(_T_1021, _T_1019) @[Cat.scala 29:58] + node _T_1023 = bits(_T_1013, 38, 38) @[el2_lib.scala 308:39] + node _T_1024 = bits(_T_863, 6, 0) @[el2_lib.scala 308:56] + node _T_1025 = eq(_T_1024, UInt<7>("h040")) @[el2_lib.scala 308:62] + node _T_1026 = xor(_T_1023, _T_1025) @[el2_lib.scala 308:44] + node _T_1027 = bits(_T_1013, 31, 31) @[el2_lib.scala 308:102] + node _T_1028 = bits(_T_1013, 15, 15) @[el2_lib.scala 308:124] + node _T_1029 = bits(_T_1013, 7, 7) @[el2_lib.scala 308:146] + node _T_1030 = bits(_T_1013, 3, 3) @[el2_lib.scala 308:167] + node _T_1031 = bits(_T_1013, 1, 0) @[el2_lib.scala 308:188] + node _T_1032 = cat(_T_1029, _T_1030) @[Cat.scala 29:58] + node _T_1033 = cat(_T_1032, _T_1031) @[Cat.scala 29:58] + node _T_1034 = cat(_T_1026, _T_1027) @[Cat.scala 29:58] + node _T_1035 = cat(_T_1034, _T_1028) @[Cat.scala 29:58] + node _T_1036 = cat(_T_1035, _T_1033) @[Cat.scala 29:58] + ic_tag_corrected_ecc_unc[1] <= _T_1036 @[el2_ifu_ic_mem.scala 155:33] + ic_tag_corrected_data_unc[1] <= _T_1022 @[el2_ifu_ic_mem.scala 156:34] + ic_tag_single_ecc_error[1] <= _T_867 @[el2_ifu_ic_mem.scala 157:31] + ic_tag_double_ecc_error[1] <= _T_872 @[el2_ifu_ic_mem.scala 158:32] + node _T_1037 = cat(ic_tag_single_ecc_error[1], ic_tag_single_ecc_error[0]) @[Cat.scala 29:58] + node _T_1038 = cat(ic_tag_double_ecc_error[1], ic_tag_double_ecc_error[0]) @[Cat.scala 29:58] + node ic_tag_way_perr = or(_T_1037, _T_1038) @[el2_ifu_ic_mem.scala 161:88] + node _T_1039 = bits(ic_debug_rd_way_en_ff, 0, 0) @[el2_ifu_ic_mem.scala 164:108] + node _T_1040 = bits(_T_1039, 0, 0) @[Bitwise.scala 72:15] + node _T_1041 = mux(_T_1040, UInt<26>("h03ffffff"), UInt<26>("h00")) @[Bitwise.scala 72:12] + node _T_1042 = and(_T_1041, ic_tag_data_raw_0) @[el2_ifu_ic_mem.scala 164:112] + node _T_1043 = bits(ic_debug_rd_way_en_ff, 1, 1) @[el2_ifu_ic_mem.scala 164:108] + node _T_1044 = bits(_T_1043, 0, 0) @[Bitwise.scala 72:15] + node _T_1045 = mux(_T_1044, UInt<26>("h03ffffff"), UInt<26>("h00")) @[Bitwise.scala 72:12] + node _T_1046 = and(_T_1045, ic_tag_data_raw_1) @[el2_ifu_ic_mem.scala 164:112] + node _T_1047 = or(_T_1042, _T_1046) @[el2_ifu_ic_mem.scala 164:221] + io.ictag_debug_rd_data <= _T_1047 @[el2_ifu_ic_mem.scala 164:26] + node _T_1048 = bits(w_tout[0], 18, 0) @[el2_ifu_ic_mem.scala 165:63] + node _T_1049 = eq(_T_1048, ic_rw_addr_ff) @[el2_ifu_ic_mem.scala 165:83] + node _T_1050 = bits(io.ic_tag_valid, 0, 0) @[el2_ifu_ic_mem.scala 165:116] + node _T_1051 = and(_T_1049, _T_1050) @[el2_ifu_ic_mem.scala 165:100] + node _T_1052 = bits(w_tout[1], 18, 0) @[el2_ifu_ic_mem.scala 165:63] + node _T_1053 = eq(_T_1052, ic_rw_addr_ff) @[el2_ifu_ic_mem.scala 165:83] + node _T_1054 = bits(io.ic_tag_valid, 1, 1) @[el2_ifu_ic_mem.scala 165:116] + node _T_1055 = and(_T_1053, _T_1054) @[el2_ifu_ic_mem.scala 165:100] + node _T_1056 = cat(_T_1055, _T_1051) @[Cat.scala 29:58] + io.ic_rd_hit <= _T_1056 @[el2_ifu_ic_mem.scala 165:16] + node _T_1057 = and(ic_tag_way_perr, io.ic_tag_valid) @[el2_ifu_ic_mem.scala 166:38] + node _T_1058 = orr(_T_1057) @[el2_ifu_ic_mem.scala 166:60] + io.ic_tag_perr <= _T_1058 @[el2_ifu_ic_mem.scala 166:18] + + module EL2_IC_DATA : + input clock : Clock + input reset : Reset + output io : {flip clk_override : UInt<1>, flip ic_rw_addr : UInt<12>, flip ic_wr_en : UInt<2>, flip ic_rd_en : UInt<1>, flip ic_wr_data : UInt<71>[2], ic_rd_data : UInt<64>, flip ic_debug_wr_data : UInt<71>, ic_debug_rd_data : UInt<71>, ic_parerr : UInt<2>, ic_eccerr : UInt<2>, flip ic_debug_addr : UInt<9>, flip ic_debug_rd_en : UInt<1>, flip ic_debug_wr_en : UInt<1>, flip ic_debug_tag_array : UInt<1>, flip ic_debug_way : UInt<2>, flip ic_premux_data : UInt<64>, flip ic_sel_premux_data : UInt<1>, flip ic_rd_hit : UInt<2>, flip scan_mode : UInt<1>} + + node _T = eq(io.ic_debug_tag_array, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 195:70] + node _T_1 = and(io.ic_debug_rd_en, _T) @[el2_ifu_ic_mem.scala 195:68] + node _T_2 = bits(_T_1, 0, 0) @[Bitwise.scala 72:15] + node _T_3 = mux(_T_2, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node ic_debug_rd_way_en = and(_T_3, io.ic_debug_way) @[el2_ifu_ic_mem.scala 195:94] + node _T_4 = eq(io.ic_debug_tag_array, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 196:70] + node _T_5 = and(io.ic_debug_wr_en, _T_4) @[el2_ifu_ic_mem.scala 196:68] + node _T_6 = bits(_T_5, 0, 0) @[Bitwise.scala 72:15] + node _T_7 = mux(_T_6, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node ic_debug_wr_way_en = and(_T_7, io.ic_debug_way) @[el2_ifu_ic_mem.scala 196:94] + wire ic_bank_wr_data : UInt<71>[2] @[el2_ifu_ic_mem.scala 198:29] + wire ic_rd_en_with_debug : UInt<1> + ic_rd_en_with_debug <= UInt<1>("h00") + node _T_8 = or(io.ic_debug_rd_en, io.ic_debug_wr_en) @[el2_ifu_ic_mem.scala 201:45] + node _T_9 = bits(_T_8, 0, 0) @[el2_ifu_ic_mem.scala 201:66] + node _T_10 = cat(io.ic_debug_addr, UInt<2>("h00")) @[Cat.scala 29:58] + node ic_rw_addr_q = mux(_T_9, _T_10, io.ic_rw_addr) @[el2_ifu_ic_mem.scala 201:25] + node _T_11 = bits(ic_rw_addr_q, 11, 3) @[el2_ifu_ic_mem.scala 203:38] + node _T_12 = add(_T_11, UInt<1>("h01")) @[el2_ifu_ic_mem.scala 203:79] + node ic_rw_addr_q_inc = tail(_T_12, 1) @[el2_ifu_ic_mem.scala 203:79] + node _T_13 = bits(io.ic_debug_addr, 0, 0) @[el2_ifu_ic_mem.scala 205:78] + node _T_14 = eq(_T_13, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 205:113] + node _T_15 = bits(_T_14, 0, 0) @[Bitwise.scala 72:15] + node _T_16 = mux(_T_15, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_17 = and(ic_debug_wr_way_en, _T_16) @[el2_ifu_ic_mem.scala 205:38] + node ic_b_sb_wren_0 = or(io.ic_wr_en, _T_17) @[el2_ifu_ic_mem.scala 205:17] + node _T_18 = bits(io.ic_debug_addr, 0, 0) @[el2_ifu_ic_mem.scala 205:78] + node _T_19 = eq(_T_18, UInt<1>("h01")) @[el2_ifu_ic_mem.scala 205:113] node _T_20 = bits(_T_19, 0, 0) @[Bitwise.scala 72:15] node _T_21 = mux(_T_20, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_22 = and(ic_debug_wr_way_en, _T_21) @[el2_ifu_ic_mem.scala 52:38] - node ic_b_sb_wren_1 = or(io.ic_wr_en, _T_22) @[el2_ifu_ic_mem.scala 52:17] - node _T_23 = bits(io.ic_debug_addr, 0, 0) @[el2_ifu_ic_mem.scala 53:76] - node _T_24 = eq(_T_23, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 53:111] - node _T_25 = bits(io.ic_debug_addr, 0, 0) @[el2_ifu_ic_mem.scala 53:76] - node _T_26 = eq(_T_25, UInt<1>("h01")) @[el2_ifu_ic_mem.scala 53:111] + node _T_22 = and(ic_debug_wr_way_en, _T_21) @[el2_ifu_ic_mem.scala 205:38] + node ic_b_sb_wren_1 = or(io.ic_wr_en, _T_22) @[el2_ifu_ic_mem.scala 205:17] + node _T_23 = bits(io.ic_debug_addr, 0, 0) @[el2_ifu_ic_mem.scala 206:76] + node _T_24 = eq(_T_23, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 206:111] + node _T_25 = bits(io.ic_debug_addr, 0, 0) @[el2_ifu_ic_mem.scala 206:76] + node _T_26 = eq(_T_25, UInt<1>("h01")) @[el2_ifu_ic_mem.scala 206:111] node ic_debug_sel_sb = cat(_T_26, _T_24) @[Cat.scala 29:58] - node _T_27 = bits(ic_debug_sel_sb, 0, 0) @[el2_ifu_ic_mem.scala 54:77] - node _T_28 = and(_T_27, io.ic_debug_wr_en) @[el2_ifu_ic_mem.scala 54:80] - node _T_29 = bits(_T_28, 0, 0) @[el2_ifu_ic_mem.scala 54:100] - node ic_sb_wr_data_0 = mux(_T_29, io.ic_debug_wr_data, ic_bank_wr_data[0]) @[el2_ifu_ic_mem.scala 54:60] - node _T_30 = bits(ic_debug_sel_sb, 1, 1) @[el2_ifu_ic_mem.scala 54:77] - node _T_31 = and(_T_30, io.ic_debug_wr_en) @[el2_ifu_ic_mem.scala 54:80] - node _T_32 = bits(_T_31, 0, 0) @[el2_ifu_ic_mem.scala 54:100] - node ic_sb_wr_data_1 = mux(_T_32, io.ic_debug_wr_data, ic_bank_wr_data[1]) @[el2_ifu_ic_mem.scala 54:60] - node _T_33 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 56:29] - node _T_34 = bits(_T_33, 0, 0) @[el2_ifu_ic_mem.scala 56:48] - node _T_35 = eq(_T_34, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 56:16] - node _T_36 = eq(UInt<1>("h00"), UInt<1>("h00")) @[el2_ifu_ic_mem.scala 56:63] - node _T_37 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 57:20] - node _T_38 = bits(_T_37, 0, 0) @[el2_ifu_ic_mem.scala 57:40] - node _T_39 = bits(ic_rw_addr_q, 1, 0) @[el2_ifu_ic_mem.scala 57:64] - node _T_40 = eq(_T_39, UInt<2>("h03")) @[el2_ifu_ic_mem.scala 57:69] - node _T_41 = eq(UInt<1>("h00"), UInt<1>("h00")) @[el2_ifu_ic_mem.scala 57:81] - node _T_42 = and(_T_40, _T_41) @[el2_ifu_ic_mem.scala 57:76] - node _T_43 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 58:19] - node _T_44 = bits(_T_43, 0, 0) @[el2_ifu_ic_mem.scala 58:38] - node _T_45 = eq(UInt<1>("h00"), UInt<1>("h01")) @[el2_ifu_ic_mem.scala 58:53] - node _T_46 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 59:21] - node _T_47 = eq(_T_46, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 59:8] - node _T_48 = bits(_T_47, 0, 0) @[el2_ifu_ic_mem.scala 59:41] - node _T_49 = bits(ic_rw_addr_q, 1, 0) @[el2_ifu_ic_mem.scala 59:65] - node _T_50 = eq(_T_49, UInt<2>("h03")) @[el2_ifu_ic_mem.scala 59:70] - node _T_51 = eq(UInt<1>("h00"), UInt<1>("h01")) @[el2_ifu_ic_mem.scala 59:83] - node _T_52 = and(_T_50, _T_51) @[el2_ifu_ic_mem.scala 59:77] + node _T_27 = bits(ic_debug_sel_sb, 0, 0) @[el2_ifu_ic_mem.scala 207:77] + node _T_28 = and(_T_27, io.ic_debug_wr_en) @[el2_ifu_ic_mem.scala 207:80] + node _T_29 = bits(_T_28, 0, 0) @[el2_ifu_ic_mem.scala 207:100] + node ic_sb_wr_data_0 = mux(_T_29, io.ic_debug_wr_data, ic_bank_wr_data[0]) @[el2_ifu_ic_mem.scala 207:60] + node _T_30 = bits(ic_debug_sel_sb, 1, 1) @[el2_ifu_ic_mem.scala 207:77] + node _T_31 = and(_T_30, io.ic_debug_wr_en) @[el2_ifu_ic_mem.scala 207:80] + node _T_32 = bits(_T_31, 0, 0) @[el2_ifu_ic_mem.scala 207:100] + node ic_sb_wr_data_1 = mux(_T_32, io.ic_debug_wr_data, ic_bank_wr_data[1]) @[el2_ifu_ic_mem.scala 207:60] + node _T_33 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 209:29] + node _T_34 = bits(_T_33, 0, 0) @[el2_ifu_ic_mem.scala 209:48] + node _T_35 = eq(_T_34, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 209:16] + node _T_36 = eq(UInt<1>("h00"), UInt<1>("h00")) @[el2_ifu_ic_mem.scala 209:63] + node _T_37 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 210:42] + node _T_38 = bits(_T_37, 0, 0) @[el2_ifu_ic_mem.scala 210:62] + node _T_39 = bits(ic_rw_addr_q, 1, 0) @[el2_ifu_ic_mem.scala 210:86] + node _T_40 = eq(_T_39, UInt<2>("h03")) @[el2_ifu_ic_mem.scala 210:91] + node _T_41 = eq(UInt<1>("h00"), UInt<1>("h00")) @[el2_ifu_ic_mem.scala 210:103] + node _T_42 = and(_T_40, _T_41) @[el2_ifu_ic_mem.scala 210:98] + node _T_43 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 211:42] + node _T_44 = bits(_T_43, 0, 0) @[el2_ifu_ic_mem.scala 211:61] + node _T_45 = eq(UInt<1>("h00"), UInt<1>("h01")) @[el2_ifu_ic_mem.scala 211:76] + node _T_46 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 212:43] + node _T_47 = eq(_T_46, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 212:30] + node _T_48 = bits(_T_47, 0, 0) @[el2_ifu_ic_mem.scala 212:63] + node _T_49 = bits(ic_rw_addr_q, 1, 0) @[el2_ifu_ic_mem.scala 212:87] + node _T_50 = eq(_T_49, UInt<2>("h03")) @[el2_ifu_ic_mem.scala 212:92] + node _T_51 = eq(UInt<1>("h00"), UInt<1>("h01")) @[el2_ifu_ic_mem.scala 212:105] + node _T_52 = and(_T_50, _T_51) @[el2_ifu_ic_mem.scala 212:99] node _T_53 = mux(_T_35, _T_36, UInt<1>("h00")) @[Mux.scala 27:72] node _T_54 = mux(_T_38, _T_42, UInt<1>("h00")) @[Mux.scala 27:72] node _T_55 = mux(_T_44, _T_45, UInt<1>("h00")) @[Mux.scala 27:72] @@ -86,27 +1550,27 @@ circuit el2_ifu_ic_mem : node _T_59 = or(_T_58, _T_56) @[Mux.scala 27:72] wire _T_60 : UInt<1> @[Mux.scala 27:72] _T_60 <= _T_59 @[Mux.scala 27:72] - node _T_61 = and(_T_60, ic_rd_en_with_debug) @[el2_ifu_ic_mem.scala 59:95] - node _T_62 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 56:29] - node _T_63 = bits(_T_62, 0, 0) @[el2_ifu_ic_mem.scala 56:48] - node _T_64 = eq(_T_63, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 56:16] - node _T_65 = eq(UInt<1>("h01"), UInt<1>("h00")) @[el2_ifu_ic_mem.scala 56:63] - node _T_66 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 57:20] - node _T_67 = bits(_T_66, 0, 0) @[el2_ifu_ic_mem.scala 57:40] - node _T_68 = bits(ic_rw_addr_q, 1, 0) @[el2_ifu_ic_mem.scala 57:64] - node _T_69 = eq(_T_68, UInt<2>("h03")) @[el2_ifu_ic_mem.scala 57:69] - node _T_70 = eq(UInt<1>("h01"), UInt<1>("h00")) @[el2_ifu_ic_mem.scala 57:81] - node _T_71 = and(_T_69, _T_70) @[el2_ifu_ic_mem.scala 57:76] - node _T_72 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 58:19] - node _T_73 = bits(_T_72, 0, 0) @[el2_ifu_ic_mem.scala 58:38] - node _T_74 = eq(UInt<1>("h01"), UInt<1>("h01")) @[el2_ifu_ic_mem.scala 58:53] - node _T_75 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 59:21] - node _T_76 = eq(_T_75, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 59:8] - node _T_77 = bits(_T_76, 0, 0) @[el2_ifu_ic_mem.scala 59:41] - node _T_78 = bits(ic_rw_addr_q, 1, 0) @[el2_ifu_ic_mem.scala 59:65] - node _T_79 = eq(_T_78, UInt<2>("h03")) @[el2_ifu_ic_mem.scala 59:70] - node _T_80 = eq(UInt<1>("h01"), UInt<1>("h01")) @[el2_ifu_ic_mem.scala 59:83] - node _T_81 = and(_T_79, _T_80) @[el2_ifu_ic_mem.scala 59:77] + node _T_61 = and(_T_60, ic_rd_en_with_debug) @[el2_ifu_ic_mem.scala 212:117] + node _T_62 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 209:29] + node _T_63 = bits(_T_62, 0, 0) @[el2_ifu_ic_mem.scala 209:48] + node _T_64 = eq(_T_63, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 209:16] + node _T_65 = eq(UInt<1>("h01"), UInt<1>("h00")) @[el2_ifu_ic_mem.scala 209:63] + node _T_66 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 210:42] + node _T_67 = bits(_T_66, 0, 0) @[el2_ifu_ic_mem.scala 210:62] + node _T_68 = bits(ic_rw_addr_q, 1, 0) @[el2_ifu_ic_mem.scala 210:86] + node _T_69 = eq(_T_68, UInt<2>("h03")) @[el2_ifu_ic_mem.scala 210:91] + node _T_70 = eq(UInt<1>("h01"), UInt<1>("h00")) @[el2_ifu_ic_mem.scala 210:103] + node _T_71 = and(_T_69, _T_70) @[el2_ifu_ic_mem.scala 210:98] + node _T_72 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 211:42] + node _T_73 = bits(_T_72, 0, 0) @[el2_ifu_ic_mem.scala 211:61] + node _T_74 = eq(UInt<1>("h01"), UInt<1>("h01")) @[el2_ifu_ic_mem.scala 211:76] + node _T_75 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 212:43] + node _T_76 = eq(_T_75, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 212:30] + node _T_77 = bits(_T_76, 0, 0) @[el2_ifu_ic_mem.scala 212:63] + node _T_78 = bits(ic_rw_addr_q, 1, 0) @[el2_ifu_ic_mem.scala 212:87] + node _T_79 = eq(_T_78, UInt<2>("h03")) @[el2_ifu_ic_mem.scala 212:92] + node _T_80 = eq(UInt<1>("h01"), UInt<1>("h01")) @[el2_ifu_ic_mem.scala 212:105] + node _T_81 = and(_T_79, _T_80) @[el2_ifu_ic_mem.scala 212:99] node _T_82 = mux(_T_64, _T_65, UInt<1>("h00")) @[Mux.scala 27:72] node _T_83 = mux(_T_67, _T_71, UInt<1>("h00")) @[Mux.scala 27:72] node _T_84 = mux(_T_73, _T_74, UInt<1>("h00")) @[Mux.scala 27:72] @@ -116,233 +1580,233 @@ circuit el2_ifu_ic_mem : node _T_88 = or(_T_87, _T_85) @[Mux.scala 27:72] wire _T_89 : UInt<1> @[Mux.scala 27:72] _T_89 <= _T_88 @[Mux.scala 27:72] - node _T_90 = and(_T_89, ic_rd_en_with_debug) @[el2_ifu_ic_mem.scala 59:95] + node _T_90 = and(_T_89, ic_rd_en_with_debug) @[el2_ifu_ic_mem.scala 212:117] node ic_b_rden = cat(_T_90, _T_61) @[Cat.scala 29:58] - node _T_91 = bits(ic_b_rden, 0, 0) @[el2_ifu_ic_mem.scala 60:89] + node _T_91 = bits(ic_b_rden, 0, 0) @[el2_ifu_ic_mem.scala 213:89] node _T_92 = bits(_T_91, 0, 0) @[Bitwise.scala 72:15] node ic_b_sb_rden_0 = mux(_T_92, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_93 = bits(ic_b_rden, 1, 1) @[el2_ifu_ic_mem.scala 60:89] + node _T_93 = bits(ic_b_rden, 1, 1) @[el2_ifu_ic_mem.scala 213:89] node _T_94 = bits(_T_93, 0, 0) @[Bitwise.scala 72:15] node ic_b_sb_rden_1 = mux(_T_94, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_95 = bits(ic_b_sb_rden_0, 0, 0) @[el2_ifu_ic_mem.scala 62:21] - node _T_96 = or(_T_95, io.clk_override) @[el2_ifu_ic_mem.scala 62:25] - node _T_97 = bits(ic_b_sb_wren_0, 0, 0) @[el2_ifu_ic_mem.scala 62:60] - node _T_98 = or(_T_96, _T_97) @[el2_ifu_ic_mem.scala 62:43] - node _T_99 = bits(ic_b_sb_rden_0, 1, 1) @[el2_ifu_ic_mem.scala 62:21] - node _T_100 = or(_T_99, io.clk_override) @[el2_ifu_ic_mem.scala 62:25] - node _T_101 = bits(ic_b_sb_wren_0, 1, 1) @[el2_ifu_ic_mem.scala 62:60] - node _T_102 = or(_T_100, _T_101) @[el2_ifu_ic_mem.scala 62:43] + node _T_95 = bits(ic_b_sb_rden_0, 0, 0) @[el2_ifu_ic_mem.scala 215:21] + node _T_96 = or(_T_95, io.clk_override) @[el2_ifu_ic_mem.scala 215:25] + node _T_97 = bits(ic_b_sb_wren_0, 0, 0) @[el2_ifu_ic_mem.scala 215:60] + node _T_98 = or(_T_96, _T_97) @[el2_ifu_ic_mem.scala 215:43] + node _T_99 = bits(ic_b_sb_rden_0, 1, 1) @[el2_ifu_ic_mem.scala 215:21] + node _T_100 = or(_T_99, io.clk_override) @[el2_ifu_ic_mem.scala 215:25] + node _T_101 = bits(ic_b_sb_wren_0, 1, 1) @[el2_ifu_ic_mem.scala 215:60] + node _T_102 = or(_T_100, _T_101) @[el2_ifu_ic_mem.scala 215:43] node ic_bank_way_clken_0 = cat(_T_98, _T_102) @[Cat.scala 29:58] - node _T_103 = bits(ic_b_sb_rden_1, 0, 0) @[el2_ifu_ic_mem.scala 62:21] - node _T_104 = or(_T_103, io.clk_override) @[el2_ifu_ic_mem.scala 62:25] - node _T_105 = bits(ic_b_sb_wren_1, 0, 0) @[el2_ifu_ic_mem.scala 62:60] - node _T_106 = or(_T_104, _T_105) @[el2_ifu_ic_mem.scala 62:43] - node _T_107 = bits(ic_b_sb_rden_1, 1, 1) @[el2_ifu_ic_mem.scala 62:21] - node _T_108 = or(_T_107, io.clk_override) @[el2_ifu_ic_mem.scala 62:25] - node _T_109 = bits(ic_b_sb_wren_1, 1, 1) @[el2_ifu_ic_mem.scala 62:60] - node _T_110 = or(_T_108, _T_109) @[el2_ifu_ic_mem.scala 62:43] + node _T_103 = bits(ic_b_sb_rden_1, 0, 0) @[el2_ifu_ic_mem.scala 215:21] + node _T_104 = or(_T_103, io.clk_override) @[el2_ifu_ic_mem.scala 215:25] + node _T_105 = bits(ic_b_sb_wren_1, 0, 0) @[el2_ifu_ic_mem.scala 215:60] + node _T_106 = or(_T_104, _T_105) @[el2_ifu_ic_mem.scala 215:43] + node _T_107 = bits(ic_b_sb_rden_1, 1, 1) @[el2_ifu_ic_mem.scala 215:21] + node _T_108 = or(_T_107, io.clk_override) @[el2_ifu_ic_mem.scala 215:25] + node _T_109 = bits(ic_b_sb_wren_1, 1, 1) @[el2_ifu_ic_mem.scala 215:60] + node _T_110 = or(_T_108, _T_109) @[el2_ifu_ic_mem.scala 215:43] node ic_bank_way_clken_1 = cat(_T_106, _T_110) @[Cat.scala 29:58] - node _T_111 = orr(io.ic_wr_en) @[el2_ifu_ic_mem.scala 64:74] - node _T_112 = eq(_T_111, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 64:61] - node _T_113 = and(io.ic_debug_rd_en, _T_112) @[el2_ifu_ic_mem.scala 64:58] - node _T_114 = or(io.ic_rd_en, _T_113) @[el2_ifu_ic_mem.scala 64:38] - ic_rd_en_with_debug <= _T_114 @[el2_ifu_ic_mem.scala 64:23] - node _T_115 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 66:37] - node _T_116 = bits(ic_rw_addr_q, 1, 0) @[el2_ifu_ic_mem.scala 66:71] - node _T_117 = eq(_T_116, UInt<2>("h03")) @[el2_ifu_ic_mem.scala 66:77] - node _T_118 = and(_T_115, _T_117) @[el2_ifu_ic_mem.scala 66:56] - node _T_119 = and(_T_118, ic_rd_en_with_debug) @[el2_ifu_ic_mem.scala 66:86] - node _T_120 = orr(io.ic_wr_en) @[el2_ifu_ic_mem.scala 66:124] - node _T_121 = eq(_T_120, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 66:110] - node ic_rw_addr_wrap = and(_T_119, _T_121) @[el2_ifu_ic_mem.scala 66:108] - node _T_122 = eq(ic_rw_addr_wrap, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 68:40] - node _T_123 = bits(_T_122, 0, 0) @[el2_ifu_ic_mem.scala 68:58] - node _T_124 = bits(ic_rw_addr_q, 11, 3) @[el2_ifu_ic_mem.scala 68:77] - node _T_125 = bits(ic_rw_addr_q, 11, 5) @[el2_ifu_ic_mem.scala 69:21] - node _T_126 = bits(ic_rw_addr_q_inc, 4, 3) @[el2_ifu_ic_mem.scala 69:82] + node _T_111 = orr(io.ic_wr_en) @[el2_ifu_ic_mem.scala 217:74] + node _T_112 = eq(_T_111, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 217:61] + node _T_113 = and(io.ic_debug_rd_en, _T_112) @[el2_ifu_ic_mem.scala 217:58] + node _T_114 = or(io.ic_rd_en, _T_113) @[el2_ifu_ic_mem.scala 217:38] + ic_rd_en_with_debug <= _T_114 @[el2_ifu_ic_mem.scala 217:23] + node _T_115 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 219:37] + node _T_116 = bits(ic_rw_addr_q, 1, 0) @[el2_ifu_ic_mem.scala 219:71] + node _T_117 = eq(_T_116, UInt<2>("h03")) @[el2_ifu_ic_mem.scala 219:77] + node _T_118 = and(_T_115, _T_117) @[el2_ifu_ic_mem.scala 219:56] + node _T_119 = and(_T_118, ic_rd_en_with_debug) @[el2_ifu_ic_mem.scala 219:86] + node _T_120 = orr(io.ic_wr_en) @[el2_ifu_ic_mem.scala 219:124] + node _T_121 = eq(_T_120, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 219:110] + node ic_rw_addr_wrap = and(_T_119, _T_121) @[el2_ifu_ic_mem.scala 219:108] + node _T_122 = eq(ic_rw_addr_wrap, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 221:40] + node _T_123 = bits(_T_122, 0, 0) @[el2_ifu_ic_mem.scala 221:58] + node _T_124 = bits(ic_rw_addr_q, 11, 3) @[el2_ifu_ic_mem.scala 221:77] + node _T_125 = bits(ic_rw_addr_q, 11, 5) @[el2_ifu_ic_mem.scala 222:21] + node _T_126 = bits(ic_rw_addr_q_inc, 4, 3) @[el2_ifu_ic_mem.scala 222:82] node _T_127 = cat(_T_125, _T_126) @[Cat.scala 29:58] - node _T_128 = mux(_T_123, _T_124, _T_127) @[el2_ifu_ic_mem.scala 68:38] - node _T_129 = bits(ic_rw_addr_q, 11, 3) @[el2_ifu_ic_mem.scala 70:17] - wire ic_rw_addr_bank_q : UInt<9>[2] @[el2_ifu_ic_mem.scala 68:34] - ic_rw_addr_bank_q[0] <= _T_128 @[el2_ifu_ic_mem.scala 68:34] - ic_rw_addr_bank_q[1] <= _T_129 @[el2_ifu_ic_mem.scala 68:34] - reg ic_b_rden_ff : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ic_mem.scala 72:29] - ic_b_rden_ff <= ic_b_rden @[el2_ifu_ic_mem.scala 72:29] - node _T_130 = bits(ic_rw_addr_q, 4, 0) @[el2_ifu_ic_mem.scala 73:43] - reg ic_rw_addr_ff : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ic_mem.scala 73:30] - ic_rw_addr_ff <= _T_130 @[el2_ifu_ic_mem.scala 73:30] - reg ic_debug_rd_way_en_ff : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ic_mem.scala 74:38] - ic_debug_rd_way_en_ff <= ic_debug_rd_way_en @[el2_ifu_ic_mem.scala 74:38] - reg ic_debug_rd_en_ff : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ic_mem.scala 75:34] - ic_debug_rd_en_ff <= io.ic_debug_rd_en @[el2_ifu_ic_mem.scala 75:34] - node _T_131 = bits(ic_rw_addr_ff, 4, 2) @[el2_ifu_ic_mem.scala 77:43] + node _T_128 = mux(_T_123, _T_124, _T_127) @[el2_ifu_ic_mem.scala 221:38] + node _T_129 = bits(ic_rw_addr_q, 11, 3) @[el2_ifu_ic_mem.scala 223:17] + wire ic_rw_addr_bank_q : UInt<9>[2] @[el2_ifu_ic_mem.scala 221:34] + ic_rw_addr_bank_q[0] <= _T_128 @[el2_ifu_ic_mem.scala 221:34] + ic_rw_addr_bank_q[1] <= _T_129 @[el2_ifu_ic_mem.scala 221:34] + reg ic_b_rden_ff : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ic_mem.scala 225:29] + ic_b_rden_ff <= ic_b_rden @[el2_ifu_ic_mem.scala 225:29] + node _T_130 = bits(ic_rw_addr_q, 4, 0) @[el2_ifu_ic_mem.scala 226:43] + reg ic_rw_addr_ff : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ic_mem.scala 226:30] + ic_rw_addr_ff <= _T_130 @[el2_ifu_ic_mem.scala 226:30] + reg ic_debug_rd_way_en_ff : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ic_mem.scala 227:38] + ic_debug_rd_way_en_ff <= ic_debug_rd_way_en @[el2_ifu_ic_mem.scala 227:38] + reg ic_debug_rd_en_ff : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ic_mem.scala 228:34] + ic_debug_rd_en_ff <= io.ic_debug_rd_en @[el2_ifu_ic_mem.scala 228:34] + node _T_131 = bits(ic_rw_addr_ff, 4, 2) @[el2_ifu_ic_mem.scala 230:43] node _T_132 = mux(UInt<1>("h01"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node ic_cacheline_wrap_ff = eq(_T_131, _T_132) @[el2_ifu_ic_mem.scala 77:84] - wire wb_dout : UInt<71>[2][2] @[el2_ifu_ic_mem.scala 81:21] - cmem data_mem : UInt<71>[2][2][512] @[el2_ifu_ic_mem.scala 82:21] - wb_dout[0][0] <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 84:19] - node _T_133 = bits(ic_b_sb_wren_0, 0, 0) @[el2_ifu_ic_mem.scala 85:73] - node _T_134 = bits(ic_bank_way_clken_0, 0, 0) @[el2_ifu_ic_mem.scala 86:83] - node _T_135 = bits(ic_b_sb_wren_0, 0, 0) @[el2_ifu_ic_mem.scala 87:26] - node _T_136 = bits(ic_bank_way_clken_0, 0, 0) @[el2_ifu_ic_mem.scala 87:52] - node _T_137 = and(_T_135, _T_136) @[el2_ifu_ic_mem.scala 87:30] - node _T_138 = bits(_T_137, 0, 0) @[el2_ifu_ic_mem.scala 87:57] - when _T_138 : @[el2_ifu_ic_mem.scala 87:64] - infer mport _T_139 = data_mem[ic_rw_addr_bank_q[0]], clock @[el2_ifu_ic_mem.scala 88:15] - _T_139[0][0] <= ic_sb_wr_data_0 @[el2_ifu_ic_mem.scala 88:44] - skip @[el2_ifu_ic_mem.scala 87:64] - else : @[el2_ifu_ic_mem.scala 89:69] - node _T_140 = bits(ic_b_sb_wren_0, 0, 0) @[el2_ifu_ic_mem.scala 89:33] - node _T_141 = eq(_T_140, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 89:17] - node _T_142 = bits(ic_bank_way_clken_0, 0, 0) @[el2_ifu_ic_mem.scala 89:57] - node _T_143 = and(_T_141, _T_142) @[el2_ifu_ic_mem.scala 89:36] - node _T_144 = bits(_T_143, 0, 0) @[el2_ifu_ic_mem.scala 89:62] - when _T_144 : @[el2_ifu_ic_mem.scala 89:69] - infer mport _T_145 = data_mem[ic_rw_addr_bank_q[0]], clock @[el2_ifu_ic_mem.scala 90:32] - wb_dout[0][0] <= _T_145[0][0] @[el2_ifu_ic_mem.scala 90:21] - skip @[el2_ifu_ic_mem.scala 89:69] - wb_dout[0][1] <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 84:19] - node _T_146 = bits(ic_b_sb_wren_1, 0, 0) @[el2_ifu_ic_mem.scala 85:73] - node _T_147 = bits(ic_bank_way_clken_1, 0, 0) @[el2_ifu_ic_mem.scala 86:83] - node _T_148 = bits(ic_b_sb_wren_1, 0, 0) @[el2_ifu_ic_mem.scala 87:26] - node _T_149 = bits(ic_bank_way_clken_1, 0, 0) @[el2_ifu_ic_mem.scala 87:52] - node _T_150 = and(_T_148, _T_149) @[el2_ifu_ic_mem.scala 87:30] - node _T_151 = bits(_T_150, 0, 0) @[el2_ifu_ic_mem.scala 87:57] - when _T_151 : @[el2_ifu_ic_mem.scala 87:64] - infer mport _T_152 = data_mem[ic_rw_addr_bank_q[1]], clock @[el2_ifu_ic_mem.scala 88:15] - _T_152[1][0] <= ic_sb_wr_data_1 @[el2_ifu_ic_mem.scala 88:44] - skip @[el2_ifu_ic_mem.scala 87:64] - else : @[el2_ifu_ic_mem.scala 89:69] - node _T_153 = bits(ic_b_sb_wren_1, 0, 0) @[el2_ifu_ic_mem.scala 89:33] - node _T_154 = eq(_T_153, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 89:17] - node _T_155 = bits(ic_bank_way_clken_1, 0, 0) @[el2_ifu_ic_mem.scala 89:57] - node _T_156 = and(_T_154, _T_155) @[el2_ifu_ic_mem.scala 89:36] - node _T_157 = bits(_T_156, 0, 0) @[el2_ifu_ic_mem.scala 89:62] - when _T_157 : @[el2_ifu_ic_mem.scala 89:69] - infer mport _T_158 = data_mem[ic_rw_addr_bank_q[1]], clock @[el2_ifu_ic_mem.scala 90:32] - wb_dout[0][1] <= _T_158[1][0] @[el2_ifu_ic_mem.scala 90:21] - skip @[el2_ifu_ic_mem.scala 89:69] - wb_dout[1][0] <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 84:19] - node _T_159 = bits(ic_b_sb_wren_0, 1, 1) @[el2_ifu_ic_mem.scala 85:73] - node _T_160 = bits(ic_bank_way_clken_0, 1, 1) @[el2_ifu_ic_mem.scala 86:83] - node _T_161 = bits(ic_b_sb_wren_0, 1, 1) @[el2_ifu_ic_mem.scala 87:26] - node _T_162 = bits(ic_bank_way_clken_0, 1, 1) @[el2_ifu_ic_mem.scala 87:52] - node _T_163 = and(_T_161, _T_162) @[el2_ifu_ic_mem.scala 87:30] - node _T_164 = bits(_T_163, 0, 0) @[el2_ifu_ic_mem.scala 87:57] - when _T_164 : @[el2_ifu_ic_mem.scala 87:64] - infer mport _T_165 = data_mem[ic_rw_addr_bank_q[0]], clock @[el2_ifu_ic_mem.scala 88:15] - _T_165[0][1] <= ic_sb_wr_data_0 @[el2_ifu_ic_mem.scala 88:44] - skip @[el2_ifu_ic_mem.scala 87:64] - else : @[el2_ifu_ic_mem.scala 89:69] - node _T_166 = bits(ic_b_sb_wren_0, 1, 1) @[el2_ifu_ic_mem.scala 89:33] - node _T_167 = eq(_T_166, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 89:17] - node _T_168 = bits(ic_bank_way_clken_0, 1, 1) @[el2_ifu_ic_mem.scala 89:57] - node _T_169 = and(_T_167, _T_168) @[el2_ifu_ic_mem.scala 89:36] - node _T_170 = bits(_T_169, 0, 0) @[el2_ifu_ic_mem.scala 89:62] - when _T_170 : @[el2_ifu_ic_mem.scala 89:69] - infer mport _T_171 = data_mem[ic_rw_addr_bank_q[0]], clock @[el2_ifu_ic_mem.scala 90:32] - wb_dout[1][0] <= _T_171[0][1] @[el2_ifu_ic_mem.scala 90:21] - skip @[el2_ifu_ic_mem.scala 89:69] - wb_dout[1][1] <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 84:19] - node _T_172 = bits(ic_b_sb_wren_1, 1, 1) @[el2_ifu_ic_mem.scala 85:73] - node _T_173 = bits(ic_bank_way_clken_1, 1, 1) @[el2_ifu_ic_mem.scala 86:83] - node _T_174 = bits(ic_b_sb_wren_1, 1, 1) @[el2_ifu_ic_mem.scala 87:26] - node _T_175 = bits(ic_bank_way_clken_1, 1, 1) @[el2_ifu_ic_mem.scala 87:52] - node _T_176 = and(_T_174, _T_175) @[el2_ifu_ic_mem.scala 87:30] - node _T_177 = bits(_T_176, 0, 0) @[el2_ifu_ic_mem.scala 87:57] - when _T_177 : @[el2_ifu_ic_mem.scala 87:64] - infer mport _T_178 = data_mem[ic_rw_addr_bank_q[1]], clock @[el2_ifu_ic_mem.scala 88:15] - _T_178[1][1] <= ic_sb_wr_data_1 @[el2_ifu_ic_mem.scala 88:44] - skip @[el2_ifu_ic_mem.scala 87:64] - else : @[el2_ifu_ic_mem.scala 89:69] - node _T_179 = bits(ic_b_sb_wren_1, 1, 1) @[el2_ifu_ic_mem.scala 89:33] - node _T_180 = eq(_T_179, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 89:17] - node _T_181 = bits(ic_bank_way_clken_1, 1, 1) @[el2_ifu_ic_mem.scala 89:57] - node _T_182 = and(_T_180, _T_181) @[el2_ifu_ic_mem.scala 89:36] - node _T_183 = bits(_T_182, 0, 0) @[el2_ifu_ic_mem.scala 89:62] - when _T_183 : @[el2_ifu_ic_mem.scala 89:69] - infer mport _T_184 = data_mem[ic_rw_addr_bank_q[1]], clock @[el2_ifu_ic_mem.scala 90:32] - wb_dout[1][1] <= _T_184[1][1] @[el2_ifu_ic_mem.scala 90:21] - skip @[el2_ifu_ic_mem.scala 89:69] - node _T_185 = bits(ic_debug_rd_en_ff, 0, 0) @[el2_ifu_ic_mem.scala 93:43] - node ic_rd_hit_q = mux(_T_185, ic_debug_rd_way_en_ff, io.ic_rd_hit) @[el2_ifu_ic_mem.scala 93:24] - ic_bank_wr_data[0] <= io.ic_wr_data[0] @[el2_ifu_ic_mem.scala 94:19] - ic_bank_wr_data[1] <= io.ic_wr_data[1] @[el2_ifu_ic_mem.scala 94:19] - node _T_186 = bits(ic_rw_addr_ff, 2, 2) @[el2_ifu_ic_mem.scala 97:59] - node _T_187 = eq(_T_186, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 97:95] - node _T_188 = bits(_T_187, 0, 0) @[el2_ifu_ic_mem.scala 97:103] - node _T_189 = bits(ic_rw_addr_ff, 2, 2) @[el2_ifu_ic_mem.scala 97:59] - node _T_190 = eq(_T_189, UInt<1>("h01")) @[el2_ifu_ic_mem.scala 97:95] - node _T_191 = bits(_T_190, 0, 0) @[el2_ifu_ic_mem.scala 97:103] + node ic_cacheline_wrap_ff = eq(_T_131, _T_132) @[el2_ifu_ic_mem.scala 230:84] + wire wb_dout : UInt<71>[2][2] @[el2_ifu_ic_mem.scala 234:21] + cmem data_mem : UInt<71>[2][2][512] @[el2_ifu_ic_mem.scala 235:21] + wb_dout[0][0] <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 237:19] + node _T_133 = bits(ic_b_sb_wren_0, 0, 0) @[el2_ifu_ic_mem.scala 238:73] + node _T_134 = bits(ic_bank_way_clken_0, 0, 0) @[el2_ifu_ic_mem.scala 239:83] + node _T_135 = bits(ic_b_sb_wren_0, 0, 0) @[el2_ifu_ic_mem.scala 240:26] + node _T_136 = bits(ic_bank_way_clken_0, 0, 0) @[el2_ifu_ic_mem.scala 240:52] + node _T_137 = and(_T_135, _T_136) @[el2_ifu_ic_mem.scala 240:30] + node _T_138 = bits(_T_137, 0, 0) @[el2_ifu_ic_mem.scala 240:57] + when _T_138 : @[el2_ifu_ic_mem.scala 240:64] + infer mport _T_139 = data_mem[ic_rw_addr_bank_q[0]], clock @[el2_ifu_ic_mem.scala 241:15] + _T_139[0][0] <= ic_sb_wr_data_0 @[el2_ifu_ic_mem.scala 241:44] + skip @[el2_ifu_ic_mem.scala 240:64] + else : @[el2_ifu_ic_mem.scala 242:69] + node _T_140 = bits(ic_b_sb_wren_0, 0, 0) @[el2_ifu_ic_mem.scala 242:33] + node _T_141 = eq(_T_140, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 242:17] + node _T_142 = bits(ic_bank_way_clken_0, 0, 0) @[el2_ifu_ic_mem.scala 242:57] + node _T_143 = and(_T_141, _T_142) @[el2_ifu_ic_mem.scala 242:36] + node _T_144 = bits(_T_143, 0, 0) @[el2_ifu_ic_mem.scala 242:62] + when _T_144 : @[el2_ifu_ic_mem.scala 242:69] + infer mport _T_145 = data_mem[ic_rw_addr_bank_q[0]], clock @[el2_ifu_ic_mem.scala 243:32] + wb_dout[0][0] <= _T_145[0][0] @[el2_ifu_ic_mem.scala 243:21] + skip @[el2_ifu_ic_mem.scala 242:69] + wb_dout[0][1] <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 237:19] + node _T_146 = bits(ic_b_sb_wren_1, 0, 0) @[el2_ifu_ic_mem.scala 238:73] + node _T_147 = bits(ic_bank_way_clken_1, 0, 0) @[el2_ifu_ic_mem.scala 239:83] + node _T_148 = bits(ic_b_sb_wren_1, 0, 0) @[el2_ifu_ic_mem.scala 240:26] + node _T_149 = bits(ic_bank_way_clken_1, 0, 0) @[el2_ifu_ic_mem.scala 240:52] + node _T_150 = and(_T_148, _T_149) @[el2_ifu_ic_mem.scala 240:30] + node _T_151 = bits(_T_150, 0, 0) @[el2_ifu_ic_mem.scala 240:57] + when _T_151 : @[el2_ifu_ic_mem.scala 240:64] + infer mport _T_152 = data_mem[ic_rw_addr_bank_q[1]], clock @[el2_ifu_ic_mem.scala 241:15] + _T_152[1][0] <= ic_sb_wr_data_1 @[el2_ifu_ic_mem.scala 241:44] + skip @[el2_ifu_ic_mem.scala 240:64] + else : @[el2_ifu_ic_mem.scala 242:69] + node _T_153 = bits(ic_b_sb_wren_1, 0, 0) @[el2_ifu_ic_mem.scala 242:33] + node _T_154 = eq(_T_153, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 242:17] + node _T_155 = bits(ic_bank_way_clken_1, 0, 0) @[el2_ifu_ic_mem.scala 242:57] + node _T_156 = and(_T_154, _T_155) @[el2_ifu_ic_mem.scala 242:36] + node _T_157 = bits(_T_156, 0, 0) @[el2_ifu_ic_mem.scala 242:62] + when _T_157 : @[el2_ifu_ic_mem.scala 242:69] + infer mport _T_158 = data_mem[ic_rw_addr_bank_q[1]], clock @[el2_ifu_ic_mem.scala 243:32] + wb_dout[0][1] <= _T_158[1][0] @[el2_ifu_ic_mem.scala 243:21] + skip @[el2_ifu_ic_mem.scala 242:69] + wb_dout[1][0] <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 237:19] + node _T_159 = bits(ic_b_sb_wren_0, 1, 1) @[el2_ifu_ic_mem.scala 238:73] + node _T_160 = bits(ic_bank_way_clken_0, 1, 1) @[el2_ifu_ic_mem.scala 239:83] + node _T_161 = bits(ic_b_sb_wren_0, 1, 1) @[el2_ifu_ic_mem.scala 240:26] + node _T_162 = bits(ic_bank_way_clken_0, 1, 1) @[el2_ifu_ic_mem.scala 240:52] + node _T_163 = and(_T_161, _T_162) @[el2_ifu_ic_mem.scala 240:30] + node _T_164 = bits(_T_163, 0, 0) @[el2_ifu_ic_mem.scala 240:57] + when _T_164 : @[el2_ifu_ic_mem.scala 240:64] + infer mport _T_165 = data_mem[ic_rw_addr_bank_q[0]], clock @[el2_ifu_ic_mem.scala 241:15] + _T_165[0][1] <= ic_sb_wr_data_0 @[el2_ifu_ic_mem.scala 241:44] + skip @[el2_ifu_ic_mem.scala 240:64] + else : @[el2_ifu_ic_mem.scala 242:69] + node _T_166 = bits(ic_b_sb_wren_0, 1, 1) @[el2_ifu_ic_mem.scala 242:33] + node _T_167 = eq(_T_166, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 242:17] + node _T_168 = bits(ic_bank_way_clken_0, 1, 1) @[el2_ifu_ic_mem.scala 242:57] + node _T_169 = and(_T_167, _T_168) @[el2_ifu_ic_mem.scala 242:36] + node _T_170 = bits(_T_169, 0, 0) @[el2_ifu_ic_mem.scala 242:62] + when _T_170 : @[el2_ifu_ic_mem.scala 242:69] + infer mport _T_171 = data_mem[ic_rw_addr_bank_q[0]], clock @[el2_ifu_ic_mem.scala 243:32] + wb_dout[1][0] <= _T_171[0][1] @[el2_ifu_ic_mem.scala 243:21] + skip @[el2_ifu_ic_mem.scala 242:69] + wb_dout[1][1] <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 237:19] + node _T_172 = bits(ic_b_sb_wren_1, 1, 1) @[el2_ifu_ic_mem.scala 238:73] + node _T_173 = bits(ic_bank_way_clken_1, 1, 1) @[el2_ifu_ic_mem.scala 239:83] + node _T_174 = bits(ic_b_sb_wren_1, 1, 1) @[el2_ifu_ic_mem.scala 240:26] + node _T_175 = bits(ic_bank_way_clken_1, 1, 1) @[el2_ifu_ic_mem.scala 240:52] + node _T_176 = and(_T_174, _T_175) @[el2_ifu_ic_mem.scala 240:30] + node _T_177 = bits(_T_176, 0, 0) @[el2_ifu_ic_mem.scala 240:57] + when _T_177 : @[el2_ifu_ic_mem.scala 240:64] + infer mport _T_178 = data_mem[ic_rw_addr_bank_q[1]], clock @[el2_ifu_ic_mem.scala 241:15] + _T_178[1][1] <= ic_sb_wr_data_1 @[el2_ifu_ic_mem.scala 241:44] + skip @[el2_ifu_ic_mem.scala 240:64] + else : @[el2_ifu_ic_mem.scala 242:69] + node _T_179 = bits(ic_b_sb_wren_1, 1, 1) @[el2_ifu_ic_mem.scala 242:33] + node _T_180 = eq(_T_179, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 242:17] + node _T_181 = bits(ic_bank_way_clken_1, 1, 1) @[el2_ifu_ic_mem.scala 242:57] + node _T_182 = and(_T_180, _T_181) @[el2_ifu_ic_mem.scala 242:36] + node _T_183 = bits(_T_182, 0, 0) @[el2_ifu_ic_mem.scala 242:62] + when _T_183 : @[el2_ifu_ic_mem.scala 242:69] + infer mport _T_184 = data_mem[ic_rw_addr_bank_q[1]], clock @[el2_ifu_ic_mem.scala 243:32] + wb_dout[1][1] <= _T_184[1][1] @[el2_ifu_ic_mem.scala 243:21] + skip @[el2_ifu_ic_mem.scala 242:69] + node _T_185 = bits(ic_debug_rd_en_ff, 0, 0) @[el2_ifu_ic_mem.scala 246:43] + node ic_rd_hit_q = mux(_T_185, ic_debug_rd_way_en_ff, io.ic_rd_hit) @[el2_ifu_ic_mem.scala 246:24] + ic_bank_wr_data[0] <= io.ic_wr_data[0] @[el2_ifu_ic_mem.scala 247:19] + ic_bank_wr_data[1] <= io.ic_wr_data[1] @[el2_ifu_ic_mem.scala 247:19] + node _T_186 = bits(ic_rw_addr_ff, 2, 2) @[el2_ifu_ic_mem.scala 250:59] + node _T_187 = eq(_T_186, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 250:95] + node _T_188 = bits(_T_187, 0, 0) @[el2_ifu_ic_mem.scala 250:103] + node _T_189 = bits(ic_rw_addr_ff, 2, 2) @[el2_ifu_ic_mem.scala 250:59] + node _T_190 = eq(_T_189, UInt<1>("h01")) @[el2_ifu_ic_mem.scala 250:95] + node _T_191 = bits(_T_190, 0, 0) @[el2_ifu_ic_mem.scala 250:103] node _T_192 = mux(_T_188, wb_dout[0][0], UInt<1>("h00")) @[Mux.scala 27:72] node _T_193 = mux(_T_191, wb_dout[0][1], UInt<1>("h00")) @[Mux.scala 27:72] node _T_194 = or(_T_192, _T_193) @[Mux.scala 27:72] wire _T_195 : UInt<71> @[Mux.scala 27:72] _T_195 <= _T_194 @[Mux.scala 27:72] - node _T_196 = bits(ic_rw_addr_ff, 2, 2) @[el2_ifu_ic_mem.scala 98:59] - node _T_197 = sub(UInt<1>("h00"), UInt<1>("h01")) @[el2_ifu_ic_mem.scala 98:102] - node _T_198 = tail(_T_197, 1) @[el2_ifu_ic_mem.scala 98:102] - node _T_199 = eq(_T_196, _T_198) @[el2_ifu_ic_mem.scala 98:95] - node _T_200 = bits(_T_199, 0, 0) @[el2_ifu_ic_mem.scala 98:109] - node _T_201 = bits(ic_rw_addr_ff, 2, 2) @[el2_ifu_ic_mem.scala 98:59] - node _T_202 = sub(UInt<1>("h01"), UInt<1>("h01")) @[el2_ifu_ic_mem.scala 98:102] - node _T_203 = tail(_T_202, 1) @[el2_ifu_ic_mem.scala 98:102] - node _T_204 = eq(_T_201, _T_203) @[el2_ifu_ic_mem.scala 98:95] - node _T_205 = bits(_T_204, 0, 0) @[el2_ifu_ic_mem.scala 98:109] + node _T_196 = bits(ic_rw_addr_ff, 2, 2) @[el2_ifu_ic_mem.scala 251:59] + node _T_197 = sub(UInt<1>("h00"), UInt<1>("h01")) @[el2_ifu_ic_mem.scala 251:102] + node _T_198 = tail(_T_197, 1) @[el2_ifu_ic_mem.scala 251:102] + node _T_199 = eq(_T_196, _T_198) @[el2_ifu_ic_mem.scala 251:95] + node _T_200 = bits(_T_199, 0, 0) @[el2_ifu_ic_mem.scala 251:109] + node _T_201 = bits(ic_rw_addr_ff, 2, 2) @[el2_ifu_ic_mem.scala 251:59] + node _T_202 = sub(UInt<1>("h01"), UInt<1>("h01")) @[el2_ifu_ic_mem.scala 251:102] + node _T_203 = tail(_T_202, 1) @[el2_ifu_ic_mem.scala 251:102] + node _T_204 = eq(_T_201, _T_203) @[el2_ifu_ic_mem.scala 251:95] + node _T_205 = bits(_T_204, 0, 0) @[el2_ifu_ic_mem.scala 251:109] node _T_206 = mux(_T_200, wb_dout[0][0], UInt<1>("h00")) @[Mux.scala 27:72] node _T_207 = mux(_T_205, wb_dout[0][1], UInt<1>("h00")) @[Mux.scala 27:72] node _T_208 = or(_T_206, _T_207) @[Mux.scala 27:72] wire _T_209 : UInt<71> @[Mux.scala 27:72] _T_209 <= _T_208 @[Mux.scala 27:72] node wb_dout_way_pre_0 = cat(_T_195, _T_209) @[Cat.scala 29:58] - node _T_210 = bits(ic_rw_addr_ff, 2, 2) @[el2_ifu_ic_mem.scala 97:59] - node _T_211 = eq(_T_210, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 97:95] - node _T_212 = bits(_T_211, 0, 0) @[el2_ifu_ic_mem.scala 97:103] - node _T_213 = bits(ic_rw_addr_ff, 2, 2) @[el2_ifu_ic_mem.scala 97:59] - node _T_214 = eq(_T_213, UInt<1>("h01")) @[el2_ifu_ic_mem.scala 97:95] - node _T_215 = bits(_T_214, 0, 0) @[el2_ifu_ic_mem.scala 97:103] + node _T_210 = bits(ic_rw_addr_ff, 2, 2) @[el2_ifu_ic_mem.scala 250:59] + node _T_211 = eq(_T_210, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 250:95] + node _T_212 = bits(_T_211, 0, 0) @[el2_ifu_ic_mem.scala 250:103] + node _T_213 = bits(ic_rw_addr_ff, 2, 2) @[el2_ifu_ic_mem.scala 250:59] + node _T_214 = eq(_T_213, UInt<1>("h01")) @[el2_ifu_ic_mem.scala 250:95] + node _T_215 = bits(_T_214, 0, 0) @[el2_ifu_ic_mem.scala 250:103] node _T_216 = mux(_T_212, wb_dout[1][0], UInt<1>("h00")) @[Mux.scala 27:72] node _T_217 = mux(_T_215, wb_dout[1][1], UInt<1>("h00")) @[Mux.scala 27:72] node _T_218 = or(_T_216, _T_217) @[Mux.scala 27:72] wire _T_219 : UInt<71> @[Mux.scala 27:72] _T_219 <= _T_218 @[Mux.scala 27:72] - node _T_220 = bits(ic_rw_addr_ff, 2, 2) @[el2_ifu_ic_mem.scala 98:59] - node _T_221 = sub(UInt<1>("h00"), UInt<1>("h01")) @[el2_ifu_ic_mem.scala 98:102] - node _T_222 = tail(_T_221, 1) @[el2_ifu_ic_mem.scala 98:102] - node _T_223 = eq(_T_220, _T_222) @[el2_ifu_ic_mem.scala 98:95] - node _T_224 = bits(_T_223, 0, 0) @[el2_ifu_ic_mem.scala 98:109] - node _T_225 = bits(ic_rw_addr_ff, 2, 2) @[el2_ifu_ic_mem.scala 98:59] - node _T_226 = sub(UInt<1>("h01"), UInt<1>("h01")) @[el2_ifu_ic_mem.scala 98:102] - node _T_227 = tail(_T_226, 1) @[el2_ifu_ic_mem.scala 98:102] - node _T_228 = eq(_T_225, _T_227) @[el2_ifu_ic_mem.scala 98:95] - node _T_229 = bits(_T_228, 0, 0) @[el2_ifu_ic_mem.scala 98:109] + node _T_220 = bits(ic_rw_addr_ff, 2, 2) @[el2_ifu_ic_mem.scala 251:59] + node _T_221 = sub(UInt<1>("h00"), UInt<1>("h01")) @[el2_ifu_ic_mem.scala 251:102] + node _T_222 = tail(_T_221, 1) @[el2_ifu_ic_mem.scala 251:102] + node _T_223 = eq(_T_220, _T_222) @[el2_ifu_ic_mem.scala 251:95] + node _T_224 = bits(_T_223, 0, 0) @[el2_ifu_ic_mem.scala 251:109] + node _T_225 = bits(ic_rw_addr_ff, 2, 2) @[el2_ifu_ic_mem.scala 251:59] + node _T_226 = sub(UInt<1>("h01"), UInt<1>("h01")) @[el2_ifu_ic_mem.scala 251:102] + node _T_227 = tail(_T_226, 1) @[el2_ifu_ic_mem.scala 251:102] + node _T_228 = eq(_T_225, _T_227) @[el2_ifu_ic_mem.scala 251:95] + node _T_229 = bits(_T_228, 0, 0) @[el2_ifu_ic_mem.scala 251:109] node _T_230 = mux(_T_224, wb_dout[1][0], UInt<1>("h00")) @[Mux.scala 27:72] node _T_231 = mux(_T_229, wb_dout[1][1], UInt<1>("h00")) @[Mux.scala 27:72] node _T_232 = or(_T_230, _T_231) @[Mux.scala 27:72] wire _T_233 : UInt<71> @[Mux.scala 27:72] _T_233 <= _T_232 @[Mux.scala 27:72] node wb_dout_way_pre_1 = cat(_T_219, _T_233) @[Cat.scala 29:58] - node _T_234 = bits(ic_rw_addr_ff, 1, 0) @[el2_ifu_ic_mem.scala 100:78] - node _T_235 = eq(_T_234, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 100:83] - node _T_236 = bits(_T_235, 0, 0) @[el2_ifu_ic_mem.scala 100:91] - node _T_237 = bits(wb_dout_way_pre_0, 63, 0) @[el2_ifu_ic_mem.scala 100:117] - node _T_238 = bits(ic_rw_addr_ff, 1, 0) @[el2_ifu_ic_mem.scala 101:19] - node _T_239 = eq(_T_238, UInt<1>("h01")) @[el2_ifu_ic_mem.scala 101:24] - node _T_240 = bits(_T_239, 0, 0) @[el2_ifu_ic_mem.scala 101:32] - node _T_241 = bits(wb_dout_way_pre_0, 86, 71) @[el2_ifu_ic_mem.scala 101:62] - node _T_242 = bits(wb_dout_way_pre_0, 63, 16) @[el2_ifu_ic_mem.scala 101:113] + node _T_234 = bits(ic_rw_addr_ff, 1, 0) @[el2_ifu_ic_mem.scala 253:78] + node _T_235 = eq(_T_234, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 253:83] + node _T_236 = bits(_T_235, 0, 0) @[el2_ifu_ic_mem.scala 253:91] + node _T_237 = bits(wb_dout_way_pre_0, 63, 0) @[el2_ifu_ic_mem.scala 253:117] + node _T_238 = bits(ic_rw_addr_ff, 1, 0) @[el2_ifu_ic_mem.scala 254:19] + node _T_239 = eq(_T_238, UInt<1>("h01")) @[el2_ifu_ic_mem.scala 254:24] + node _T_240 = bits(_T_239, 0, 0) @[el2_ifu_ic_mem.scala 254:32] + node _T_241 = bits(wb_dout_way_pre_0, 86, 71) @[el2_ifu_ic_mem.scala 254:62] + node _T_242 = bits(wb_dout_way_pre_0, 63, 16) @[el2_ifu_ic_mem.scala 254:113] node _T_243 = cat(_T_241, _T_242) @[Cat.scala 29:58] - node _T_244 = bits(ic_rw_addr_ff, 1, 0) @[el2_ifu_ic_mem.scala 102:19] - node _T_245 = eq(_T_244, UInt<2>("h02")) @[el2_ifu_ic_mem.scala 102:24] - node _T_246 = bits(_T_245, 0, 0) @[el2_ifu_ic_mem.scala 102:32] - node _T_247 = bits(wb_dout_way_pre_0, 102, 71) @[el2_ifu_ic_mem.scala 102:62] - node _T_248 = bits(wb_dout_way_pre_0, 63, 32) @[el2_ifu_ic_mem.scala 102:113] + node _T_244 = bits(ic_rw_addr_ff, 1, 0) @[el2_ifu_ic_mem.scala 255:19] + node _T_245 = eq(_T_244, UInt<2>("h02")) @[el2_ifu_ic_mem.scala 255:24] + node _T_246 = bits(_T_245, 0, 0) @[el2_ifu_ic_mem.scala 255:32] + node _T_247 = bits(wb_dout_way_pre_0, 102, 71) @[el2_ifu_ic_mem.scala 255:62] + node _T_248 = bits(wb_dout_way_pre_0, 63, 32) @[el2_ifu_ic_mem.scala 255:113] node _T_249 = cat(_T_247, _T_248) @[Cat.scala 29:58] - node _T_250 = bits(ic_rw_addr_ff, 1, 0) @[el2_ifu_ic_mem.scala 103:19] - node _T_251 = eq(_T_250, UInt<2>("h03")) @[el2_ifu_ic_mem.scala 103:24] - node _T_252 = bits(_T_251, 0, 0) @[el2_ifu_ic_mem.scala 103:32] - node _T_253 = bits(wb_dout_way_pre_0, 118, 71) @[el2_ifu_ic_mem.scala 103:62] - node _T_254 = bits(wb_dout_way_pre_0, 63, 48) @[el2_ifu_ic_mem.scala 103:113] + node _T_250 = bits(ic_rw_addr_ff, 1, 0) @[el2_ifu_ic_mem.scala 256:19] + node _T_251 = eq(_T_250, UInt<2>("h03")) @[el2_ifu_ic_mem.scala 256:24] + node _T_252 = bits(_T_251, 0, 0) @[el2_ifu_ic_mem.scala 256:32] + node _T_253 = bits(wb_dout_way_pre_0, 118, 71) @[el2_ifu_ic_mem.scala 256:62] + node _T_254 = bits(wb_dout_way_pre_0, 63, 48) @[el2_ifu_ic_mem.scala 256:113] node _T_255 = cat(_T_253, _T_254) @[Cat.scala 29:58] node _T_256 = mux(_T_236, _T_237, UInt<1>("h00")) @[Mux.scala 27:72] node _T_257 = mux(_T_240, _T_243, UInt<1>("h00")) @[Mux.scala 27:72] @@ -353,27 +1817,27 @@ circuit el2_ifu_ic_mem : node _T_262 = or(_T_261, _T_259) @[Mux.scala 27:72] wire wb_dout_way_0 : UInt<64> @[Mux.scala 27:72] wb_dout_way_0 <= _T_262 @[Mux.scala 27:72] - node _T_263 = bits(ic_rw_addr_ff, 1, 0) @[el2_ifu_ic_mem.scala 100:78] - node _T_264 = eq(_T_263, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 100:83] - node _T_265 = bits(_T_264, 0, 0) @[el2_ifu_ic_mem.scala 100:91] - node _T_266 = bits(wb_dout_way_pre_1, 63, 0) @[el2_ifu_ic_mem.scala 100:117] - node _T_267 = bits(ic_rw_addr_ff, 1, 0) @[el2_ifu_ic_mem.scala 101:19] - node _T_268 = eq(_T_267, UInt<1>("h01")) @[el2_ifu_ic_mem.scala 101:24] - node _T_269 = bits(_T_268, 0, 0) @[el2_ifu_ic_mem.scala 101:32] - node _T_270 = bits(wb_dout_way_pre_1, 86, 71) @[el2_ifu_ic_mem.scala 101:62] - node _T_271 = bits(wb_dout_way_pre_1, 63, 16) @[el2_ifu_ic_mem.scala 101:113] + node _T_263 = bits(ic_rw_addr_ff, 1, 0) @[el2_ifu_ic_mem.scala 253:78] + node _T_264 = eq(_T_263, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 253:83] + node _T_265 = bits(_T_264, 0, 0) @[el2_ifu_ic_mem.scala 253:91] + node _T_266 = bits(wb_dout_way_pre_1, 63, 0) @[el2_ifu_ic_mem.scala 253:117] + node _T_267 = bits(ic_rw_addr_ff, 1, 0) @[el2_ifu_ic_mem.scala 254:19] + node _T_268 = eq(_T_267, UInt<1>("h01")) @[el2_ifu_ic_mem.scala 254:24] + node _T_269 = bits(_T_268, 0, 0) @[el2_ifu_ic_mem.scala 254:32] + node _T_270 = bits(wb_dout_way_pre_1, 86, 71) @[el2_ifu_ic_mem.scala 254:62] + node _T_271 = bits(wb_dout_way_pre_1, 63, 16) @[el2_ifu_ic_mem.scala 254:113] node _T_272 = cat(_T_270, _T_271) @[Cat.scala 29:58] - node _T_273 = bits(ic_rw_addr_ff, 1, 0) @[el2_ifu_ic_mem.scala 102:19] - node _T_274 = eq(_T_273, UInt<2>("h02")) @[el2_ifu_ic_mem.scala 102:24] - node _T_275 = bits(_T_274, 0, 0) @[el2_ifu_ic_mem.scala 102:32] - node _T_276 = bits(wb_dout_way_pre_1, 102, 71) @[el2_ifu_ic_mem.scala 102:62] - node _T_277 = bits(wb_dout_way_pre_1, 63, 32) @[el2_ifu_ic_mem.scala 102:113] + node _T_273 = bits(ic_rw_addr_ff, 1, 0) @[el2_ifu_ic_mem.scala 255:19] + node _T_274 = eq(_T_273, UInt<2>("h02")) @[el2_ifu_ic_mem.scala 255:24] + node _T_275 = bits(_T_274, 0, 0) @[el2_ifu_ic_mem.scala 255:32] + node _T_276 = bits(wb_dout_way_pre_1, 102, 71) @[el2_ifu_ic_mem.scala 255:62] + node _T_277 = bits(wb_dout_way_pre_1, 63, 32) @[el2_ifu_ic_mem.scala 255:113] node _T_278 = cat(_T_276, _T_277) @[Cat.scala 29:58] - node _T_279 = bits(ic_rw_addr_ff, 1, 0) @[el2_ifu_ic_mem.scala 103:19] - node _T_280 = eq(_T_279, UInt<2>("h03")) @[el2_ifu_ic_mem.scala 103:24] - node _T_281 = bits(_T_280, 0, 0) @[el2_ifu_ic_mem.scala 103:32] - node _T_282 = bits(wb_dout_way_pre_1, 118, 71) @[el2_ifu_ic_mem.scala 103:62] - node _T_283 = bits(wb_dout_way_pre_1, 63, 48) @[el2_ifu_ic_mem.scala 103:113] + node _T_279 = bits(ic_rw_addr_ff, 1, 0) @[el2_ifu_ic_mem.scala 256:19] + node _T_280 = eq(_T_279, UInt<2>("h03")) @[el2_ifu_ic_mem.scala 256:24] + node _T_281 = bits(_T_280, 0, 0) @[el2_ifu_ic_mem.scala 256:32] + node _T_282 = bits(wb_dout_way_pre_1, 118, 71) @[el2_ifu_ic_mem.scala 256:62] + node _T_283 = bits(wb_dout_way_pre_1, 63, 48) @[el2_ifu_ic_mem.scala 256:113] node _T_284 = cat(_T_282, _T_283) @[Cat.scala 29:58] node _T_285 = mux(_T_265, _T_266, UInt<1>("h00")) @[Mux.scala 27:72] node _T_286 = mux(_T_269, _T_272, UInt<1>("h00")) @[Mux.scala 27:72] @@ -384,63 +1848,63 @@ circuit el2_ifu_ic_mem : node _T_291 = or(_T_290, _T_288) @[Mux.scala 27:72] wire wb_dout_way_1 : UInt<64> @[Mux.scala 27:72] wb_dout_way_1 <= _T_291 @[Mux.scala 27:72] - node _T_292 = bits(io.ic_sel_premux_data, 0, 0) @[el2_ifu_ic_mem.scala 105:92] - node wb_dout_way_with_premux_0 = mux(_T_292, io.ic_premux_data, wb_dout_way_0) @[el2_ifu_ic_mem.scala 105:69] - node _T_293 = bits(io.ic_sel_premux_data, 0, 0) @[el2_ifu_ic_mem.scala 105:92] - node wb_dout_way_with_premux_1 = mux(_T_293, io.ic_premux_data, wb_dout_way_1) @[el2_ifu_ic_mem.scala 105:69] - node _T_294 = bits(ic_rd_hit_q, 0, 0) @[el2_ifu_ic_mem.scala 107:71] - node _T_295 = or(_T_294, io.ic_sel_premux_data) @[el2_ifu_ic_mem.scala 107:75] - node _T_296 = bits(_T_295, 0, 0) @[el2_ifu_ic_mem.scala 107:100] - node _T_297 = bits(ic_rd_hit_q, 1, 1) @[el2_ifu_ic_mem.scala 107:71] - node _T_298 = or(_T_297, io.ic_sel_premux_data) @[el2_ifu_ic_mem.scala 107:75] - node _T_299 = bits(_T_298, 0, 0) @[el2_ifu_ic_mem.scala 107:100] + node _T_292 = bits(io.ic_sel_premux_data, 0, 0) @[el2_ifu_ic_mem.scala 258:92] + node wb_dout_way_with_premux_0 = mux(_T_292, io.ic_premux_data, wb_dout_way_0) @[el2_ifu_ic_mem.scala 258:69] + node _T_293 = bits(io.ic_sel_premux_data, 0, 0) @[el2_ifu_ic_mem.scala 258:92] + node wb_dout_way_with_premux_1 = mux(_T_293, io.ic_premux_data, wb_dout_way_1) @[el2_ifu_ic_mem.scala 258:69] + node _T_294 = bits(ic_rd_hit_q, 0, 0) @[el2_ifu_ic_mem.scala 260:71] + node _T_295 = or(_T_294, io.ic_sel_premux_data) @[el2_ifu_ic_mem.scala 260:75] + node _T_296 = bits(_T_295, 0, 0) @[el2_ifu_ic_mem.scala 260:100] + node _T_297 = bits(ic_rd_hit_q, 1, 1) @[el2_ifu_ic_mem.scala 260:71] + node _T_298 = or(_T_297, io.ic_sel_premux_data) @[el2_ifu_ic_mem.scala 260:75] + node _T_299 = bits(_T_298, 0, 0) @[el2_ifu_ic_mem.scala 260:100] node _T_300 = mux(_T_296, wb_dout_way_with_premux_0, UInt<1>("h00")) @[Mux.scala 27:72] node _T_301 = mux(_T_299, wb_dout_way_with_premux_1, UInt<1>("h00")) @[Mux.scala 27:72] node _T_302 = or(_T_300, _T_301) @[Mux.scala 27:72] wire _T_303 : UInt<64> @[Mux.scala 27:72] _T_303 <= _T_302 @[Mux.scala 27:72] - io.ic_rd_data <= _T_303 @[el2_ifu_ic_mem.scala 107:17] - node _T_304 = bits(ic_rd_hit_q, 0, 0) @[el2_ifu_ic_mem.scala 108:76] - node _T_305 = bits(_T_304, 0, 0) @[el2_ifu_ic_mem.scala 108:80] - node _T_306 = bits(wb_dout_way_pre_0, 70, 0) @[el2_ifu_ic_mem.scala 108:106] - node _T_307 = bits(ic_rd_hit_q, 1, 1) @[el2_ifu_ic_mem.scala 108:76] - node _T_308 = bits(_T_307, 0, 0) @[el2_ifu_ic_mem.scala 108:80] - node _T_309 = bits(wb_dout_way_pre_1, 70, 0) @[el2_ifu_ic_mem.scala 108:106] + io.ic_rd_data <= _T_303 @[el2_ifu_ic_mem.scala 260:17] + node _T_304 = bits(ic_rd_hit_q, 0, 0) @[el2_ifu_ic_mem.scala 261:76] + node _T_305 = bits(_T_304, 0, 0) @[el2_ifu_ic_mem.scala 261:80] + node _T_306 = bits(wb_dout_way_pre_0, 70, 0) @[el2_ifu_ic_mem.scala 261:106] + node _T_307 = bits(ic_rd_hit_q, 1, 1) @[el2_ifu_ic_mem.scala 261:76] + node _T_308 = bits(_T_307, 0, 0) @[el2_ifu_ic_mem.scala 261:80] + node _T_309 = bits(wb_dout_way_pre_1, 70, 0) @[el2_ifu_ic_mem.scala 261:106] node _T_310 = mux(_T_305, _T_306, UInt<1>("h00")) @[Mux.scala 27:72] node _T_311 = mux(_T_308, _T_309, UInt<1>("h00")) @[Mux.scala 27:72] node _T_312 = or(_T_310, _T_311) @[Mux.scala 27:72] wire _T_313 : UInt<71> @[Mux.scala 27:72] _T_313 <= _T_312 @[Mux.scala 27:72] - io.ic_debug_rd_data <= _T_313 @[el2_ifu_ic_mem.scala 108:23] - node _T_314 = bits(ic_rd_hit_q, 0, 0) @[el2_ifu_ic_mem.scala 109:71] - node _T_315 = bits(_T_314, 0, 0) @[el2_ifu_ic_mem.scala 109:75] - node _T_316 = bits(ic_rd_hit_q, 1, 1) @[el2_ifu_ic_mem.scala 109:71] - node _T_317 = bits(_T_316, 0, 0) @[el2_ifu_ic_mem.scala 109:75] + io.ic_debug_rd_data <= _T_313 @[el2_ifu_ic_mem.scala 261:23] + node _T_314 = bits(ic_rd_hit_q, 0, 0) @[el2_ifu_ic_mem.scala 262:71] + node _T_315 = bits(_T_314, 0, 0) @[el2_ifu_ic_mem.scala 262:75] + node _T_316 = bits(ic_rd_hit_q, 1, 1) @[el2_ifu_ic_mem.scala 262:71] + node _T_317 = bits(_T_316, 0, 0) @[el2_ifu_ic_mem.scala 262:75] node _T_318 = mux(_T_315, wb_dout_way_pre_0, UInt<1>("h00")) @[Mux.scala 27:72] node _T_319 = mux(_T_317, wb_dout_way_pre_1, UInt<1>("h00")) @[Mux.scala 27:72] node _T_320 = or(_T_318, _T_319) @[Mux.scala 27:72] wire wb_dout_ecc : UInt<142> @[Mux.scala 27:72] wb_dout_ecc <= _T_320 @[Mux.scala 27:72] - node _T_321 = orr(io.ic_rd_hit) @[el2_ifu_ic_mem.scala 111:75] - node _T_322 = eq(ic_cacheline_wrap_ff, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 111:103] - node _T_323 = bits(ic_b_rden_ff, 1, 0) @[el2_ifu_ic_mem.scala 111:140] + node _T_321 = orr(io.ic_rd_hit) @[el2_ifu_ic_mem.scala 264:75] + node _T_322 = eq(ic_cacheline_wrap_ff, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 264:103] + node _T_323 = bits(ic_b_rden_ff, 1, 0) @[el2_ifu_ic_mem.scala 264:140] node _T_324 = mux(UInt<1>("h01"), UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_325 = eq(_T_323, _T_324) @[el2_ifu_ic_mem.scala 111:163] - node _T_326 = and(_T_322, _T_325) @[el2_ifu_ic_mem.scala 111:125] - node _T_327 = or(UInt<1>("h00"), _T_326) @[el2_ifu_ic_mem.scala 111:100] - node bank_check_en_0 = and(_T_321, _T_327) @[el2_ifu_ic_mem.scala 111:79] - node _T_328 = orr(io.ic_rd_hit) @[el2_ifu_ic_mem.scala 111:75] - node _T_329 = eq(ic_cacheline_wrap_ff, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 111:103] - node _T_330 = bits(ic_b_rden_ff, 1, 0) @[el2_ifu_ic_mem.scala 111:140] + node _T_325 = eq(_T_323, _T_324) @[el2_ifu_ic_mem.scala 264:163] + node _T_326 = and(_T_322, _T_325) @[el2_ifu_ic_mem.scala 264:125] + node _T_327 = or(UInt<1>("h00"), _T_326) @[el2_ifu_ic_mem.scala 264:100] + node bank_check_en_0 = and(_T_321, _T_327) @[el2_ifu_ic_mem.scala 264:79] + node _T_328 = orr(io.ic_rd_hit) @[el2_ifu_ic_mem.scala 264:75] + node _T_329 = eq(ic_cacheline_wrap_ff, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 264:103] + node _T_330 = bits(ic_b_rden_ff, 1, 0) @[el2_ifu_ic_mem.scala 264:140] node _T_331 = mux(UInt<1>("h01"), UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_332 = eq(_T_330, _T_331) @[el2_ifu_ic_mem.scala 111:163] - node _T_333 = and(_T_329, _T_332) @[el2_ifu_ic_mem.scala 111:125] - node _T_334 = or(UInt<1>("h00"), _T_333) @[el2_ifu_ic_mem.scala 111:100] - node bank_check_en_1 = and(_T_328, _T_334) @[el2_ifu_ic_mem.scala 111:79] - node wb_dout_ecc_bank_0 = bits(wb_dout_ecc, 70, 0) @[el2_ifu_ic_mem.scala 112:72] - node wb_dout_ecc_bank_1 = bits(wb_dout_ecc, 141, 71) @[el2_ifu_ic_mem.scala 112:72] - node _T_335 = bits(wb_dout_ecc_bank_0, 63, 0) @[el2_ifu_ic_mem.scala 115:104] - node _T_336 = bits(wb_dout_ecc_bank_0, 70, 64) @[el2_ifu_ic_mem.scala 115:130] + node _T_332 = eq(_T_330, _T_331) @[el2_ifu_ic_mem.scala 264:163] + node _T_333 = and(_T_329, _T_332) @[el2_ifu_ic_mem.scala 264:125] + node _T_334 = or(UInt<1>("h00"), _T_333) @[el2_ifu_ic_mem.scala 264:100] + node bank_check_en_1 = and(_T_328, _T_334) @[el2_ifu_ic_mem.scala 264:79] + node wb_dout_ecc_bank_0 = bits(wb_dout_ecc, 70, 0) @[el2_ifu_ic_mem.scala 265:72] + node wb_dout_ecc_bank_1 = bits(wb_dout_ecc, 141, 71) @[el2_ifu_ic_mem.scala 265:72] + node _T_335 = bits(wb_dout_ecc_bank_0, 63, 0) @[el2_ifu_ic_mem.scala 268:104] + node _T_336 = bits(wb_dout_ecc_bank_0, 70, 64) @[el2_ifu_ic_mem.scala 268:130] wire _T_337 : UInt<1>[35] @[el2_lib.scala 357:18] wire _T_338 : UInt<1>[35] @[el2_lib.scala 358:18] wire _T_339 : UInt<1>[35] @[el2_lib.scala 359:18] @@ -1086,8 +2550,8 @@ circuit el2_ifu_ic_mem : node _T_774 = bits(_T_773, 6, 0) @[el2_lib.scala 380:36] node _T_775 = neq(_T_774, UInt<1>("h00")) @[el2_lib.scala 380:42] node _T_776 = and(bank_check_en_0, _T_775) @[el2_lib.scala 380:24] - node _T_777 = bits(wb_dout_ecc_bank_1, 63, 0) @[el2_ifu_ic_mem.scala 115:104] - node _T_778 = bits(wb_dout_ecc_bank_1, 70, 64) @[el2_ifu_ic_mem.scala 115:130] + node _T_777 = bits(wb_dout_ecc_bank_1, 63, 0) @[el2_ifu_ic_mem.scala 268:104] + node _T_778 = bits(wb_dout_ecc_bank_1, 70, 64) @[el2_ifu_ic_mem.scala 268:130] wire _T_779 : UInt<1>[35] @[el2_lib.scala 357:18] wire _T_780 : UInt<1>[35] @[el2_lib.scala 358:18] wire _T_781 : UInt<1>[35] @[el2_lib.scala 359:18] @@ -1734,56 +3198,111 @@ circuit el2_ifu_ic_mem : node _T_1217 = neq(_T_1216, UInt<1>("h00")) @[el2_lib.scala 380:42] node _T_1218 = and(bank_check_en_1, _T_1217) @[el2_lib.scala 380:24] node _T_1219 = cat(_T_1218, _T_776) @[Cat.scala 29:58] - io.ic_eccerr <= _T_1219 @[el2_ifu_ic_mem.scala 115:16] - wire ic_parerr_bank : UInt<1>[4][2] @[el2_ifu_ic_mem.scala 116:28] - node _T_1220 = bits(wb_dout_ecc_bank_0, 15, 0) @[el2_ifu_ic_mem.scala 117:109] - node _T_1221 = bits(wb_dout_ecc_bank_0, 64, 64) @[el2_ifu_ic_mem.scala 117:148] + io.ic_eccerr <= _T_1219 @[el2_ifu_ic_mem.scala 268:16] + wire ic_parerr_bank : UInt<1>[4][2] @[el2_ifu_ic_mem.scala 269:28] + node _T_1220 = bits(wb_dout_ecc_bank_0, 15, 0) @[el2_ifu_ic_mem.scala 270:109] + node _T_1221 = bits(wb_dout_ecc_bank_0, 64, 64) @[el2_ifu_ic_mem.scala 270:148] node _T_1222 = xorr(_T_1220) @[el2_lib.scala 200:14] node _T_1223 = xor(_T_1222, _T_1221) @[el2_lib.scala 200:27] - ic_parerr_bank[0][0] <= _T_1223 @[el2_ifu_ic_mem.scala 117:69] - node _T_1224 = bits(wb_dout_ecc_bank_0, 31, 16) @[el2_ifu_ic_mem.scala 117:109] - node _T_1225 = bits(wb_dout_ecc_bank_0, 65, 65) @[el2_ifu_ic_mem.scala 117:148] + ic_parerr_bank[0][0] <= _T_1223 @[el2_ifu_ic_mem.scala 270:69] + node _T_1224 = bits(wb_dout_ecc_bank_0, 31, 16) @[el2_ifu_ic_mem.scala 270:109] + node _T_1225 = bits(wb_dout_ecc_bank_0, 65, 65) @[el2_ifu_ic_mem.scala 270:148] node _T_1226 = xorr(_T_1224) @[el2_lib.scala 200:14] node _T_1227 = xor(_T_1226, _T_1225) @[el2_lib.scala 200:27] - ic_parerr_bank[0][1] <= _T_1227 @[el2_ifu_ic_mem.scala 117:69] - node _T_1228 = bits(wb_dout_ecc_bank_0, 47, 32) @[el2_ifu_ic_mem.scala 117:109] - node _T_1229 = bits(wb_dout_ecc_bank_0, 66, 66) @[el2_ifu_ic_mem.scala 117:148] + ic_parerr_bank[0][1] <= _T_1227 @[el2_ifu_ic_mem.scala 270:69] + node _T_1228 = bits(wb_dout_ecc_bank_0, 47, 32) @[el2_ifu_ic_mem.scala 270:109] + node _T_1229 = bits(wb_dout_ecc_bank_0, 66, 66) @[el2_ifu_ic_mem.scala 270:148] node _T_1230 = xorr(_T_1228) @[el2_lib.scala 200:14] node _T_1231 = xor(_T_1230, _T_1229) @[el2_lib.scala 200:27] - ic_parerr_bank[0][2] <= _T_1231 @[el2_ifu_ic_mem.scala 117:69] - node _T_1232 = bits(wb_dout_ecc_bank_0, 63, 48) @[el2_ifu_ic_mem.scala 117:109] - node _T_1233 = bits(wb_dout_ecc_bank_0, 67, 67) @[el2_ifu_ic_mem.scala 117:148] + ic_parerr_bank[0][2] <= _T_1231 @[el2_ifu_ic_mem.scala 270:69] + node _T_1232 = bits(wb_dout_ecc_bank_0, 63, 48) @[el2_ifu_ic_mem.scala 270:109] + node _T_1233 = bits(wb_dout_ecc_bank_0, 67, 67) @[el2_ifu_ic_mem.scala 270:148] node _T_1234 = xorr(_T_1232) @[el2_lib.scala 200:14] node _T_1235 = xor(_T_1234, _T_1233) @[el2_lib.scala 200:27] - ic_parerr_bank[0][3] <= _T_1235 @[el2_ifu_ic_mem.scala 117:69] - node _T_1236 = bits(wb_dout_ecc_bank_1, 15, 0) @[el2_ifu_ic_mem.scala 117:109] - node _T_1237 = bits(wb_dout_ecc_bank_1, 64, 64) @[el2_ifu_ic_mem.scala 117:148] + ic_parerr_bank[0][3] <= _T_1235 @[el2_ifu_ic_mem.scala 270:69] + node _T_1236 = bits(wb_dout_ecc_bank_1, 15, 0) @[el2_ifu_ic_mem.scala 270:109] + node _T_1237 = bits(wb_dout_ecc_bank_1, 64, 64) @[el2_ifu_ic_mem.scala 270:148] node _T_1238 = xorr(_T_1236) @[el2_lib.scala 200:14] node _T_1239 = xor(_T_1238, _T_1237) @[el2_lib.scala 200:27] - ic_parerr_bank[1][0] <= _T_1239 @[el2_ifu_ic_mem.scala 117:69] - node _T_1240 = bits(wb_dout_ecc_bank_1, 31, 16) @[el2_ifu_ic_mem.scala 117:109] - node _T_1241 = bits(wb_dout_ecc_bank_1, 65, 65) @[el2_ifu_ic_mem.scala 117:148] + ic_parerr_bank[1][0] <= _T_1239 @[el2_ifu_ic_mem.scala 270:69] + node _T_1240 = bits(wb_dout_ecc_bank_1, 31, 16) @[el2_ifu_ic_mem.scala 270:109] + node _T_1241 = bits(wb_dout_ecc_bank_1, 65, 65) @[el2_ifu_ic_mem.scala 270:148] node _T_1242 = xorr(_T_1240) @[el2_lib.scala 200:14] node _T_1243 = xor(_T_1242, _T_1241) @[el2_lib.scala 200:27] - ic_parerr_bank[1][1] <= _T_1243 @[el2_ifu_ic_mem.scala 117:69] - node _T_1244 = bits(wb_dout_ecc_bank_1, 47, 32) @[el2_ifu_ic_mem.scala 117:109] - node _T_1245 = bits(wb_dout_ecc_bank_1, 66, 66) @[el2_ifu_ic_mem.scala 117:148] + ic_parerr_bank[1][1] <= _T_1243 @[el2_ifu_ic_mem.scala 270:69] + node _T_1244 = bits(wb_dout_ecc_bank_1, 47, 32) @[el2_ifu_ic_mem.scala 270:109] + node _T_1245 = bits(wb_dout_ecc_bank_1, 66, 66) @[el2_ifu_ic_mem.scala 270:148] node _T_1246 = xorr(_T_1244) @[el2_lib.scala 200:14] node _T_1247 = xor(_T_1246, _T_1245) @[el2_lib.scala 200:27] - ic_parerr_bank[1][2] <= _T_1247 @[el2_ifu_ic_mem.scala 117:69] - node _T_1248 = bits(wb_dout_ecc_bank_1, 63, 48) @[el2_ifu_ic_mem.scala 117:109] - node _T_1249 = bits(wb_dout_ecc_bank_1, 67, 67) @[el2_ifu_ic_mem.scala 117:148] + ic_parerr_bank[1][2] <= _T_1247 @[el2_ifu_ic_mem.scala 270:69] + node _T_1248 = bits(wb_dout_ecc_bank_1, 63, 48) @[el2_ifu_ic_mem.scala 270:109] + node _T_1249 = bits(wb_dout_ecc_bank_1, 67, 67) @[el2_ifu_ic_mem.scala 270:148] node _T_1250 = xorr(_T_1248) @[el2_lib.scala 200:14] node _T_1251 = xor(_T_1250, _T_1249) @[el2_lib.scala 200:27] - ic_parerr_bank[1][3] <= _T_1251 @[el2_ifu_ic_mem.scala 117:69] - node _T_1252 = or(ic_parerr_bank[0][0], ic_parerr_bank[0][1]) @[el2_ifu_ic_mem.scala 119:49] - node _T_1253 = or(_T_1252, ic_parerr_bank[0][2]) @[el2_ifu_ic_mem.scala 119:49] - node _T_1254 = or(_T_1253, ic_parerr_bank[0][3]) @[el2_ifu_ic_mem.scala 119:49] - node _T_1255 = and(_T_1254, bank_check_en_0) @[el2_ifu_ic_mem.scala 119:53] - node _T_1256 = or(ic_parerr_bank[1][0], ic_parerr_bank[1][1]) @[el2_ifu_ic_mem.scala 119:99] - node _T_1257 = or(_T_1256, ic_parerr_bank[1][2]) @[el2_ifu_ic_mem.scala 119:99] - node _T_1258 = or(_T_1257, ic_parerr_bank[1][3]) @[el2_ifu_ic_mem.scala 119:99] - node _T_1259 = and(_T_1258, bank_check_en_1) @[el2_ifu_ic_mem.scala 119:103] + ic_parerr_bank[1][3] <= _T_1251 @[el2_ifu_ic_mem.scala 270:69] + node _T_1252 = or(ic_parerr_bank[0][0], ic_parerr_bank[0][1]) @[el2_ifu_ic_mem.scala 272:49] + node _T_1253 = or(_T_1252, ic_parerr_bank[0][2]) @[el2_ifu_ic_mem.scala 272:49] + node _T_1254 = or(_T_1253, ic_parerr_bank[0][3]) @[el2_ifu_ic_mem.scala 272:49] + node _T_1255 = and(_T_1254, bank_check_en_0) @[el2_ifu_ic_mem.scala 272:53] + node _T_1256 = or(ic_parerr_bank[1][0], ic_parerr_bank[1][1]) @[el2_ifu_ic_mem.scala 272:99] + node _T_1257 = or(_T_1256, ic_parerr_bank[1][2]) @[el2_ifu_ic_mem.scala 272:99] + node _T_1258 = or(_T_1257, ic_parerr_bank[1][3]) @[el2_ifu_ic_mem.scala 272:99] + node _T_1259 = and(_T_1258, bank_check_en_1) @[el2_ifu_ic_mem.scala 272:103] node _T_1260 = cat(_T_1255, _T_1259) @[Cat.scala 29:58] - io.ic_parerr <= _T_1260 @[el2_ifu_ic_mem.scala 119:16] + io.ic_parerr <= _T_1260 @[el2_ifu_ic_mem.scala 272:16] + + module el2_ifu_ic_mem : + input clock : Clock + input reset : UInt<1> + output io : {flip scan_mode : UInt<1>, flip clk_override : UInt<1>, flip dec_tlu_core_ecc_disable : UInt<1>, flip ic_rw_addr : UInt<31>, flip ic_wr_en : UInt<2>, flip ic_rd_en : UInt<1>, flip ic_debug_addr : UInt<9>, flip ic_debug_rd_en : UInt<1>, flip ic_debug_wr_en : UInt<1>, flip ic_debug_tag_array : UInt<1>, flip ic_debug_way : UInt<2>, flip ic_premux_data : UInt<64>, flip ic_sel_premux_data : UInt<1>, flip ic_tag_valid : UInt<2>, flip ic_debug_wr_data : UInt<71>, flip ic_wr_data : UInt<71>[2], ic_rd_data : UInt<64>, ic_debug_rd_data : UInt<71>, ictag_debug_rd_data : UInt<26>, ic_eccerr : UInt<2>, ic_parerr : UInt<2>, ic_rd_hit : UInt<2>, ic_tag_perr : UInt<1>} + + io.ic_tag_perr <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 34:18] + io.ic_rd_hit <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 35:16] + io.ic_parerr <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 36:16] + io.ic_eccerr <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 37:16] + io.ictag_debug_rd_data <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 38:26] + io.ic_debug_rd_data <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 39:23] + io.ic_rd_data <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 40:17] + inst ic_tag_inst of EL2_IC_TAG @[el2_ifu_ic_mem.scala 41:27] + ic_tag_inst.clock <= clock + ic_tag_inst.reset <= reset + ic_tag_inst.io.ic_tag_valid <= io.ic_tag_valid @[el2_ifu_ic_mem.scala 43:31] + ic_tag_inst.io.dec_tlu_core_ecc_disable <= io.dec_tlu_core_ecc_disable @[el2_ifu_ic_mem.scala 44:43] + ic_tag_inst.io.clk_override <= io.clk_override @[el2_ifu_ic_mem.scala 45:31] + ic_tag_inst.io.ic_rw_addr <= io.ic_rw_addr @[el2_ifu_ic_mem.scala 46:29] + ic_tag_inst.io.ic_wr_en <= io.ic_wr_en @[el2_ifu_ic_mem.scala 47:27] + ic_tag_inst.io.ic_rd_en <= io.ic_rd_en @[el2_ifu_ic_mem.scala 48:27] + ic_tag_inst.io.ic_debug_addr <= io.ic_debug_addr @[el2_ifu_ic_mem.scala 49:32] + ic_tag_inst.io.ic_debug_rd_en <= io.ic_debug_rd_en @[el2_ifu_ic_mem.scala 50:33] + ic_tag_inst.io.ic_debug_wr_en <= io.ic_debug_wr_en @[el2_ifu_ic_mem.scala 51:33] + ic_tag_inst.io.ic_debug_tag_array <= io.ic_debug_tag_array @[el2_ifu_ic_mem.scala 52:37] + ic_tag_inst.io.ic_debug_way <= io.ic_debug_way @[el2_ifu_ic_mem.scala 53:31] + io.ictag_debug_rd_data <= ic_tag_inst.io.ictag_debug_rd_data @[el2_ifu_ic_mem.scala 54:26] + ic_tag_inst.io.ic_debug_wr_data <= io.ic_debug_wr_data @[el2_ifu_ic_mem.scala 55:35] + io.ic_rd_hit <= ic_tag_inst.io.ic_rd_hit @[el2_ifu_ic_mem.scala 56:16] + io.ic_tag_perr <= ic_tag_inst.io.ic_tag_perr @[el2_ifu_ic_mem.scala 57:18] + ic_tag_inst.io.scan_mode <= io.scan_mode @[el2_ifu_ic_mem.scala 58:28] + inst ic_data_inst of EL2_IC_DATA @[el2_ifu_ic_mem.scala 59:28] + ic_data_inst.clock <= clock + ic_data_inst.reset <= reset + ic_data_inst.io.clk_override <= io.clk_override @[el2_ifu_ic_mem.scala 60:32] + ic_data_inst.io.ic_rw_addr <= io.ic_rw_addr @[el2_ifu_ic_mem.scala 62:30] + ic_data_inst.io.ic_wr_en <= io.ic_wr_en @[el2_ifu_ic_mem.scala 63:28] + ic_data_inst.io.ic_rd_en <= io.ic_rd_en @[el2_ifu_ic_mem.scala 64:28] + ic_data_inst.io.ic_wr_data[0] <= io.ic_wr_data[0] @[el2_ifu_ic_mem.scala 66:30] + ic_data_inst.io.ic_wr_data[1] <= io.ic_wr_data[1] @[el2_ifu_ic_mem.scala 66:30] + io.ic_rd_data <= ic_data_inst.io.ic_rd_data @[el2_ifu_ic_mem.scala 67:17] + ic_data_inst.io.ic_debug_wr_data <= io.ic_debug_wr_data @[el2_ifu_ic_mem.scala 68:36] + io.ic_debug_rd_data <= ic_data_inst.io.ic_debug_rd_data @[el2_ifu_ic_mem.scala 69:23] + io.ic_parerr <= ic_data_inst.io.ic_parerr @[el2_ifu_ic_mem.scala 70:16] + io.ic_eccerr <= ic_data_inst.io.ic_eccerr @[el2_ifu_ic_mem.scala 71:16] + ic_data_inst.io.ic_debug_addr <= io.ic_debug_addr @[el2_ifu_ic_mem.scala 72:33] + ic_data_inst.io.ic_debug_rd_en <= io.ic_debug_rd_en @[el2_ifu_ic_mem.scala 73:34] + ic_data_inst.io.ic_debug_wr_en <= io.ic_debug_wr_en @[el2_ifu_ic_mem.scala 74:34] + ic_data_inst.io.ic_debug_tag_array <= io.ic_debug_tag_array @[el2_ifu_ic_mem.scala 75:38] + ic_data_inst.io.ic_debug_way <= io.ic_debug_way @[el2_ifu_ic_mem.scala 76:32] + ic_data_inst.io.ic_premux_data <= io.ic_premux_data @[el2_ifu_ic_mem.scala 77:34] + ic_data_inst.io.ic_sel_premux_data <= io.ic_sel_premux_data @[el2_ifu_ic_mem.scala 78:38] + ic_data_inst.io.ic_rd_hit <= io.ic_rd_hit @[el2_ifu_ic_mem.scala 80:29] + ic_data_inst.io.scan_mode <= io.scan_mode @[el2_ifu_ic_mem.scala 81:31] diff --git a/el2_ifu_ic_mem.v b/el2_ifu_ic_mem.v index 2c94e1a0..f1268800 100644 --- a/el2_ifu_ic_mem.v +++ b/el2_ifu_ic_mem.v @@ -1,12 +1,292 @@ -module el2_ifu_ic_mem( +module EL2_IC_TAG( input clock, input reset, - input io_scan_mode, input io_clk_override, input io_dec_tlu_core_ecc_disable, - input [30:0] io_ic_rw_addr, + input [28:0] io_ic_rw_addr, + input [1:0] io_ic_wr_en, + input [1:0] io_ic_tag_valid, + input io_ic_rd_en, + input [9:0] io_ic_debug_addr, + input io_ic_debug_rd_en, + input io_ic_debug_wr_en, + input io_ic_debug_tag_array, + input [1:0] io_ic_debug_way, + output [25:0] io_ictag_debug_rd_data, + input [70:0] io_ic_debug_wr_data, + output [1:0] io_ic_rd_hit, + output io_ic_tag_perr +); +`ifdef RANDOMIZE_MEM_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; +`endif // RANDOMIZE_MEM_INIT +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; +`endif // RANDOMIZE_REG_INIT + reg [25:0] tag_mem_0 [0:127]; // @[el2_ifu_ic_mem.scala 136:20] + wire [25:0] tag_mem_0__T_250_data; // @[el2_ifu_ic_mem.scala 136:20] + wire [6:0] tag_mem_0__T_250_addr; // @[el2_ifu_ic_mem.scala 136:20] + wire [25:0] tag_mem_0__T_254_data; // @[el2_ifu_ic_mem.scala 136:20] + wire [6:0] tag_mem_0__T_254_addr; // @[el2_ifu_ic_mem.scala 136:20] + wire [25:0] tag_mem_0__T_238_data; // @[el2_ifu_ic_mem.scala 136:20] + wire [6:0] tag_mem_0__T_238_addr; // @[el2_ifu_ic_mem.scala 136:20] + wire tag_mem_0__T_238_mask; // @[el2_ifu_ic_mem.scala 136:20] + wire tag_mem_0__T_238_en; // @[el2_ifu_ic_mem.scala 136:20] + reg [25:0] tag_mem_1 [0:127]; // @[el2_ifu_ic_mem.scala 136:20] + wire [25:0] tag_mem_1__T_250_data; // @[el2_ifu_ic_mem.scala 136:20] + wire [6:0] tag_mem_1__T_250_addr; // @[el2_ifu_ic_mem.scala 136:20] + wire [25:0] tag_mem_1__T_254_data; // @[el2_ifu_ic_mem.scala 136:20] + wire [6:0] tag_mem_1__T_254_addr; // @[el2_ifu_ic_mem.scala 136:20] + wire [25:0] tag_mem_1__T_238_data; // @[el2_ifu_ic_mem.scala 136:20] + wire [6:0] tag_mem_1__T_238_addr; // @[el2_ifu_ic_mem.scala 136:20] + wire tag_mem_1__T_238_mask; // @[el2_ifu_ic_mem.scala 136:20] + wire tag_mem_1__T_238_en; // @[el2_ifu_ic_mem.scala 136:20] + wire _T_1 = io_ic_rw_addr[2:1] == 2'h1; // @[el2_ifu_ic_mem.scala 110:95] + wire [1:0] _T_3 = _T_1 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] ic_tag_wren = io_ic_wr_en & _T_3; // @[el2_ifu_ic_mem.scala 110:33] + wire _T_4 = io_ic_rd_en | io_clk_override; // @[el2_ifu_ic_mem.scala 111:55] + wire [1:0] _T_6 = _T_4 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_7 = _T_6 | io_ic_wr_en; // @[el2_ifu_ic_mem.scala 111:73] + wire _T_14 = io_ic_debug_wr_en & io_ic_debug_tag_array; // @[el2_ifu_ic_mem.scala 119:65] + wire [1:0] _T_16 = _T_14 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] ic_debug_wr_way_en = _T_16 & io_ic_debug_way; // @[el2_ifu_ic_mem.scala 119:90] + wire [1:0] _T_8 = _T_7 | ic_debug_wr_way_en; // @[el2_ifu_ic_mem.scala 111:87] + wire _T_10 = io_ic_debug_rd_en & io_ic_debug_tag_array; // @[el2_ifu_ic_mem.scala 118:65] + wire [1:0] _T_12 = _T_10 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] ic_debug_rd_way_en = _T_12 & io_ic_debug_way; // @[el2_ifu_ic_mem.scala 118:90] + wire [1:0] ic_tag_clken = _T_8 | ic_debug_rd_way_en; // @[el2_ifu_ic_mem.scala 111:108] + reg ic_rd_en_ff; // @[el2_ifu_ic_mem.scala 113:28] + reg [18:0] ic_rw_addr_ff; // @[el2_ifu_ic_mem.scala 114:30] + wire [1:0] ic_tag_wren_q = ic_tag_wren | ic_debug_wr_way_en; // @[el2_ifu_ic_mem.scala 121:35] + wire [31:0] _T_20 = {13'h0,io_ic_rw_addr[28:10]}; // @[Cat.scala 29:58] + wire [8:0] _T_124 = {_T_20[16],_T_20[14],_T_20[12],_T_20[10],_T_20[8],_T_20[6],_T_20[5],_T_20[3],_T_20[1]}; // @[el2_lib.scala 263:22] + wire [17:0] _T_133 = {_T_20[31],_T_20[30],_T_20[28],_T_20[27],_T_20[25],_T_20[23],_T_20[21],_T_20[20],_T_20[18],_T_124}; // @[el2_lib.scala 263:22] + wire _T_134 = ^_T_133; // @[el2_lib.scala 263:29] + wire [8:0] _T_142 = {_T_20[15],_T_20[14],_T_20[11],_T_20[10],_T_20[7],_T_20[6],_T_20[4],_T_20[3],_T_20[0]}; // @[el2_lib.scala 263:39] + wire [17:0] _T_151 = {_T_20[31],_T_20[29],_T_20[28],_T_20[26],_T_20[25],_T_20[22],_T_20[21],_T_20[19],_T_20[18],_T_142}; // @[el2_lib.scala 263:39] + wire _T_152 = ^_T_151; // @[el2_lib.scala 263:46] + wire [8:0] _T_160 = {_T_20[15],_T_20[14],_T_20[9],_T_20[8],_T_20[7],_T_20[6],_T_20[2],_T_20[1],_T_20[0]}; // @[el2_lib.scala 263:56] + wire [17:0] _T_169 = {_T_20[30],_T_20[29],_T_20[28],_T_20[24],_T_20[23],_T_20[22],_T_20[21],_T_20[17],_T_20[16],_T_160}; // @[el2_lib.scala 263:56] + wire _T_170 = ^_T_169; // @[el2_lib.scala 263:63] + wire [6:0] _T_176 = {_T_20[12],_T_20[11],_T_20[10],_T_20[9],_T_20[8],_T_20[7],_T_20[6]}; // @[el2_lib.scala 263:73] + wire [14:0] _T_184 = {_T_20[27],_T_20[26],_T_20[25],_T_20[24],_T_20[23],_T_20[22],_T_20[21],_T_20[13],_T_176}; // @[el2_lib.scala 263:73] + wire _T_185 = ^_T_184; // @[el2_lib.scala 263:80] + wire [14:0] _T_199 = {_T_20[20],_T_20[19],_T_20[18],_T_20[17],_T_20[16],_T_20[15],_T_20[14],_T_20[13],_T_176}; // @[el2_lib.scala 263:90] + wire _T_200 = ^_T_199; // @[el2_lib.scala 263:97] + wire [5:0] _T_205 = {_T_20[5],_T_20[4],_T_20[3],_T_20[2],_T_20[1],_T_20[0]}; // @[el2_lib.scala 263:107] + wire _T_206 = ^_T_205; // @[el2_lib.scala 263:114] + wire [5:0] _T_211 = {_T_134,_T_152,_T_170,_T_185,_T_200,_T_206}; // @[Cat.scala 29:58] + wire _T_212 = ^_T_20; // @[el2_lib.scala 264:13] + wire _T_213 = ^_T_211; // @[el2_lib.scala 264:23] + wire _T_214 = _T_212 ^ _T_213; // @[el2_lib.scala 264:18] + wire [6:0] ic_tag_ecc = {_T_214,_T_134,_T_152,_T_170,_T_185,_T_200,_T_206}; // @[Cat.scala 29:58] + wire [25:0] _T_221 = {io_ic_debug_wr_data[68:64],io_ic_debug_wr_data[31:11]}; // @[Cat.scala 29:58] + wire [25:0] _T_226 = {ic_tag_ecc[4:0],2'h0,io_ic_rw_addr[28:10]}; // @[Cat.scala 29:58] + wire _T_227 = io_ic_debug_rd_en | io_ic_debug_wr_en; // @[el2_ifu_ic_mem.scala 132:45] + wire [28:0] ic_rw_addr_q = _T_227 ? {{22'd0}, io_ic_debug_addr[9:3]} : io_ic_rw_addr; // @[el2_ifu_ic_mem.scala 132:25] + reg [1:0] ic_debug_rd_way_en_ff; // @[el2_ifu_ic_mem.scala 134:38] + wire _T_240 = ~ic_tag_wren_q[0]; // @[el2_ifu_ic_mem.scala 141:59] + wire read_enable_0 = _T_240 & ic_tag_clken[0]; // @[el2_ifu_ic_mem.scala 141:77] + wire _T_244 = ~ic_tag_wren_q[1]; // @[el2_ifu_ic_mem.scala 141:59] + wire read_enable_1 = _T_244 & ic_tag_clken[1]; // @[el2_ifu_ic_mem.scala 141:77] + wire [25:0] _T_248 = read_enable_0 ? 26'h3ffffff : 26'h0; // @[Bitwise.scala 72:12] + wire [25:0] ic_tag_data_raw_0 = _T_248 & tag_mem_0__T_250_data; // @[el2_ifu_ic_mem.scala 143:87] + wire [25:0] _T_252 = read_enable_1 ? 26'h3ffffff : 26'h0; // @[Bitwise.scala 72:12] + wire [25:0] ic_tag_data_raw_1 = _T_252 & tag_mem_1__T_254_data; // @[el2_ifu_ic_mem.scala 143:87] + wire [23:0] w_tout_0 = {ic_tag_data_raw_0[25:21],ic_tag_data_raw_0[18:0]}; // @[Cat.scala 29:58] + wire [23:0] w_tout_1 = {ic_tag_data_raw_1[25:21],ic_tag_data_raw_1[18:0]}; // @[Cat.scala 29:58] + wire _T_261 = ~io_dec_tlu_core_ecc_disable; // @[el2_ifu_ic_mem.scala 153:51] + wire _T_262 = _T_261 & ic_rd_en_ff; // @[el2_ifu_ic_mem.scala 153:80] + wire [31:0] _T_264 = {11'h0,ic_tag_data_raw_0[20:0]}; // @[Cat.scala 29:58] + wire [6:0] _T_266 = {2'h0,ic_tag_data_raw_0[25:21]}; // @[Cat.scala 29:58] + wire [5:0] _T_373 = {_T_264[31],_T_264[30],_T_264[29],_T_264[28],_T_264[27],_T_264[26]}; // @[el2_lib.scala 296:76] + wire _T_374 = ^_T_373; // @[el2_lib.scala 296:83] + wire _T_375 = _T_266[5] ^ _T_374; // @[el2_lib.scala 296:71] + wire [6:0] _T_382 = {_T_264[17],_T_264[16],_T_264[15],_T_264[14],_T_264[13],_T_264[12],_T_264[11]}; // @[el2_lib.scala 296:103] + wire [14:0] _T_390 = {_T_264[25],_T_264[24],_T_264[23],_T_264[22],_T_264[21],_T_264[20],_T_264[19],_T_264[18],_T_382}; // @[el2_lib.scala 296:103] + wire _T_391 = ^_T_390; // @[el2_lib.scala 296:110] + wire _T_392 = _T_266[4] ^ _T_391; // @[el2_lib.scala 296:98] + wire [6:0] _T_399 = {_T_264[10],_T_264[9],_T_264[8],_T_264[7],_T_264[6],_T_264[5],_T_264[4]}; // @[el2_lib.scala 296:130] + wire [14:0] _T_407 = {_T_264[25],_T_264[24],_T_264[23],_T_264[22],_T_264[21],_T_264[20],_T_264[19],_T_264[18],_T_399}; // @[el2_lib.scala 296:130] + wire _T_408 = ^_T_407; // @[el2_lib.scala 296:137] + wire _T_409 = _T_266[3] ^ _T_408; // @[el2_lib.scala 296:125] + wire [8:0] _T_418 = {_T_264[15],_T_264[14],_T_264[10],_T_264[9],_T_264[8],_T_264[7],_T_264[3],_T_264[2],_T_264[1]}; // @[el2_lib.scala 296:157] + wire [17:0] _T_427 = {_T_264[31],_T_264[30],_T_264[29],_T_264[25],_T_264[24],_T_264[23],_T_264[22],_T_264[17],_T_264[16],_T_418}; // @[el2_lib.scala 296:157] + wire _T_428 = ^_T_427; // @[el2_lib.scala 296:164] + wire _T_429 = _T_266[2] ^ _T_428; // @[el2_lib.scala 296:152] + wire [8:0] _T_438 = {_T_264[13],_T_264[12],_T_264[10],_T_264[9],_T_264[6],_T_264[5],_T_264[3],_T_264[2],_T_264[0]}; // @[el2_lib.scala 296:184] + wire [17:0] _T_447 = {_T_264[31],_T_264[28],_T_264[27],_T_264[25],_T_264[24],_T_264[21],_T_264[20],_T_264[17],_T_264[16],_T_438}; // @[el2_lib.scala 296:184] + wire _T_448 = ^_T_447; // @[el2_lib.scala 296:191] + wire _T_449 = _T_266[1] ^ _T_448; // @[el2_lib.scala 296:179] + wire [8:0] _T_458 = {_T_264[13],_T_264[11],_T_264[10],_T_264[8],_T_264[6],_T_264[4],_T_264[3],_T_264[1],_T_264[0]}; // @[el2_lib.scala 296:211] + wire [17:0] _T_467 = {_T_264[30],_T_264[28],_T_264[26],_T_264[25],_T_264[23],_T_264[21],_T_264[19],_T_264[17],_T_264[15],_T_458}; // @[el2_lib.scala 296:211] + wire _T_468 = ^_T_467; // @[el2_lib.scala 296:218] + wire _T_469 = _T_266[0] ^ _T_468; // @[el2_lib.scala 296:206] + wire [6:0] _T_475 = {1'h0,_T_375,_T_392,_T_409,_T_429,_T_449,_T_469}; // @[Cat.scala 29:58] + wire _T_476 = _T_475 != 7'h0; // @[el2_lib.scala 297:44] + wire _T_477 = _T_262 & _T_476; // @[el2_lib.scala 297:32] + wire ic_tag_single_ecc_error_0 = _T_477 & _T_475[6]; // @[el2_lib.scala 297:53] + wire _T_483 = ~_T_475[6]; // @[el2_lib.scala 298:55] + wire ic_tag_double_ecc_error_0 = _T_477 & _T_483; // @[el2_lib.scala 298:53] + wire [31:0] _T_652 = {11'h0,ic_tag_data_raw_1[20:0]}; // @[Cat.scala 29:58] + wire [6:0] _T_654 = {2'h0,ic_tag_data_raw_1[25:21]}; // @[Cat.scala 29:58] + wire [5:0] _T_761 = {_T_652[31],_T_652[30],_T_652[29],_T_652[28],_T_652[27],_T_652[26]}; // @[el2_lib.scala 296:76] + wire _T_762 = ^_T_761; // @[el2_lib.scala 296:83] + wire _T_763 = _T_654[5] ^ _T_762; // @[el2_lib.scala 296:71] + wire [6:0] _T_770 = {_T_652[17],_T_652[16],_T_652[15],_T_652[14],_T_652[13],_T_652[12],_T_652[11]}; // @[el2_lib.scala 296:103] + wire [14:0] _T_778 = {_T_652[25],_T_652[24],_T_652[23],_T_652[22],_T_652[21],_T_652[20],_T_652[19],_T_652[18],_T_770}; // @[el2_lib.scala 296:103] + wire _T_779 = ^_T_778; // @[el2_lib.scala 296:110] + wire _T_780 = _T_654[4] ^ _T_779; // @[el2_lib.scala 296:98] + wire [6:0] _T_787 = {_T_652[10],_T_652[9],_T_652[8],_T_652[7],_T_652[6],_T_652[5],_T_652[4]}; // @[el2_lib.scala 296:130] + wire [14:0] _T_795 = {_T_652[25],_T_652[24],_T_652[23],_T_652[22],_T_652[21],_T_652[20],_T_652[19],_T_652[18],_T_787}; // @[el2_lib.scala 296:130] + wire _T_796 = ^_T_795; // @[el2_lib.scala 296:137] + wire _T_797 = _T_654[3] ^ _T_796; // @[el2_lib.scala 296:125] + wire [8:0] _T_806 = {_T_652[15],_T_652[14],_T_652[10],_T_652[9],_T_652[8],_T_652[7],_T_652[3],_T_652[2],_T_652[1]}; // @[el2_lib.scala 296:157] + wire [17:0] _T_815 = {_T_652[31],_T_652[30],_T_652[29],_T_652[25],_T_652[24],_T_652[23],_T_652[22],_T_652[17],_T_652[16],_T_806}; // @[el2_lib.scala 296:157] + wire _T_816 = ^_T_815; // @[el2_lib.scala 296:164] + wire _T_817 = _T_654[2] ^ _T_816; // @[el2_lib.scala 296:152] + wire [8:0] _T_826 = {_T_652[13],_T_652[12],_T_652[10],_T_652[9],_T_652[6],_T_652[5],_T_652[3],_T_652[2],_T_652[0]}; // @[el2_lib.scala 296:184] + wire [17:0] _T_835 = {_T_652[31],_T_652[28],_T_652[27],_T_652[25],_T_652[24],_T_652[21],_T_652[20],_T_652[17],_T_652[16],_T_826}; // @[el2_lib.scala 296:184] + wire _T_836 = ^_T_835; // @[el2_lib.scala 296:191] + wire _T_837 = _T_654[1] ^ _T_836; // @[el2_lib.scala 296:179] + wire [8:0] _T_846 = {_T_652[13],_T_652[11],_T_652[10],_T_652[8],_T_652[6],_T_652[4],_T_652[3],_T_652[1],_T_652[0]}; // @[el2_lib.scala 296:211] + wire [17:0] _T_855 = {_T_652[30],_T_652[28],_T_652[26],_T_652[25],_T_652[23],_T_652[21],_T_652[19],_T_652[17],_T_652[15],_T_846}; // @[el2_lib.scala 296:211] + wire _T_856 = ^_T_855; // @[el2_lib.scala 296:218] + wire _T_857 = _T_654[0] ^ _T_856; // @[el2_lib.scala 296:206] + wire [6:0] _T_863 = {1'h0,_T_763,_T_780,_T_797,_T_817,_T_837,_T_857}; // @[Cat.scala 29:58] + wire _T_864 = _T_863 != 7'h0; // @[el2_lib.scala 297:44] + wire _T_865 = _T_262 & _T_864; // @[el2_lib.scala 297:32] + wire ic_tag_single_ecc_error_1 = _T_865 & _T_863[6]; // @[el2_lib.scala 297:53] + wire _T_871 = ~_T_863[6]; // @[el2_lib.scala 298:55] + wire ic_tag_double_ecc_error_1 = _T_865 & _T_871; // @[el2_lib.scala 298:53] + wire [1:0] _T_1037 = {ic_tag_single_ecc_error_1,ic_tag_single_ecc_error_0}; // @[Cat.scala 29:58] + wire [1:0] _T_1038 = {ic_tag_double_ecc_error_1,ic_tag_double_ecc_error_0}; // @[Cat.scala 29:58] + wire [1:0] ic_tag_way_perr = _T_1037 | _T_1038; // @[el2_ifu_ic_mem.scala 161:88] + wire [25:0] _T_1041 = ic_debug_rd_way_en_ff[0] ? 26'h3ffffff : 26'h0; // @[Bitwise.scala 72:12] + wire [25:0] _T_1042 = _T_1041 & ic_tag_data_raw_0; // @[el2_ifu_ic_mem.scala 164:112] + wire [25:0] _T_1045 = ic_debug_rd_way_en_ff[1] ? 26'h3ffffff : 26'h0; // @[Bitwise.scala 72:12] + wire [25:0] _T_1046 = _T_1045 & ic_tag_data_raw_1; // @[el2_ifu_ic_mem.scala 164:112] + wire _T_1049 = w_tout_0[18:0] == ic_rw_addr_ff; // @[el2_ifu_ic_mem.scala 165:83] + wire _T_1051 = _T_1049 & io_ic_tag_valid[0]; // @[el2_ifu_ic_mem.scala 165:100] + wire _T_1053 = w_tout_1[18:0] == ic_rw_addr_ff; // @[el2_ifu_ic_mem.scala 165:83] + wire _T_1055 = _T_1053 & io_ic_tag_valid[1]; // @[el2_ifu_ic_mem.scala 165:100] + wire [1:0] _T_1057 = ic_tag_way_perr & io_ic_tag_valid; // @[el2_ifu_ic_mem.scala 166:38] + assign tag_mem_0__T_250_addr = ic_rw_addr_q[6:0]; + assign tag_mem_0__T_250_data = tag_mem_0[tag_mem_0__T_250_addr]; // @[el2_ifu_ic_mem.scala 136:20] + assign tag_mem_0__T_254_addr = ic_rw_addr_q[6:0]; + assign tag_mem_0__T_254_data = tag_mem_0[tag_mem_0__T_254_addr]; // @[el2_ifu_ic_mem.scala 136:20] + assign tag_mem_0__T_238_data = _T_14 ? _T_221 : _T_226; + assign tag_mem_0__T_238_addr = ic_rw_addr_q[6:0]; + assign tag_mem_0__T_238_mask = ic_tag_wren_q[0] & ic_tag_clken[0]; + assign tag_mem_0__T_238_en = 1'h1; + assign tag_mem_1__T_250_addr = ic_rw_addr_q[6:0]; + assign tag_mem_1__T_250_data = tag_mem_1[tag_mem_1__T_250_addr]; // @[el2_ifu_ic_mem.scala 136:20] + assign tag_mem_1__T_254_addr = ic_rw_addr_q[6:0]; + assign tag_mem_1__T_254_data = tag_mem_1[tag_mem_1__T_254_addr]; // @[el2_ifu_ic_mem.scala 136:20] + assign tag_mem_1__T_238_data = _T_14 ? _T_221 : _T_226; + assign tag_mem_1__T_238_addr = ic_rw_addr_q[6:0]; + assign tag_mem_1__T_238_mask = ic_tag_wren_q[1] & ic_tag_clken[1]; + assign tag_mem_1__T_238_en = 1'h1; + assign io_ictag_debug_rd_data = _T_1042 | _T_1046; // @[el2_ifu_ic_mem.scala 104:26 el2_ifu_ic_mem.scala 164:26] + assign io_ic_rd_hit = {_T_1055,_T_1051}; // @[el2_ifu_ic_mem.scala 105:16 el2_ifu_ic_mem.scala 165:16] + assign io_ic_tag_perr = |_T_1057; // @[el2_ifu_ic_mem.scala 106:18 el2_ifu_ic_mem.scala 166:18] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_MEM_INIT + _RAND_0 = {1{`RANDOM}}; + for (initvar = 0; initvar < 128; initvar = initvar+1) + tag_mem_0[initvar] = _RAND_0[25:0]; + _RAND_1 = {1{`RANDOM}}; + for (initvar = 0; initvar < 128; initvar = initvar+1) + tag_mem_1[initvar] = _RAND_1[25:0]; +`endif // RANDOMIZE_MEM_INIT +`ifdef RANDOMIZE_REG_INIT + _RAND_2 = {1{`RANDOM}}; + ic_rd_en_ff = _RAND_2[0:0]; + _RAND_3 = {1{`RANDOM}}; + ic_rw_addr_ff = _RAND_3[18:0]; + _RAND_4 = {1{`RANDOM}}; + ic_debug_rd_way_en_ff = _RAND_4[1:0]; +`endif // RANDOMIZE_REG_INIT + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge clock) begin + if(tag_mem_0__T_238_en & tag_mem_0__T_238_mask) begin + tag_mem_0[tag_mem_0__T_238_addr] <= tag_mem_0__T_238_data; // @[el2_ifu_ic_mem.scala 136:20] + end + if(tag_mem_1__T_238_en & tag_mem_1__T_238_mask) begin + tag_mem_1[tag_mem_1__T_238_addr] <= tag_mem_1__T_238_data; // @[el2_ifu_ic_mem.scala 136:20] + end + if (reset) begin + ic_rd_en_ff <= 1'h0; + end else begin + ic_rd_en_ff <= io_ic_rd_en; + end + if (reset) begin + ic_rw_addr_ff <= 19'h0; + end else begin + ic_rw_addr_ff <= io_ic_rw_addr[18:0]; + end + if (reset) begin + ic_debug_rd_way_en_ff <= 2'h0; + end else begin + ic_debug_rd_way_en_ff <= ic_debug_rd_way_en; + end + end +endmodule +module EL2_IC_DATA( + input clock, + input reset, + input io_clk_override, + input [11:0] io_ic_rw_addr, input [1:0] io_ic_wr_en, input io_ic_rd_en, + input [70:0] io_ic_wr_data_0, + input [70:0] io_ic_wr_data_1, + output [63:0] io_ic_rd_data, + input [70:0] io_ic_debug_wr_data, + output [70:0] io_ic_debug_rd_data, + output [1:0] io_ic_parerr, + output [1:0] io_ic_eccerr, input [8:0] io_ic_debug_addr, input io_ic_debug_rd_en, input io_ic_debug_wr_en, @@ -14,17 +294,7 @@ module el2_ifu_ic_mem( input [1:0] io_ic_debug_way, input [63:0] io_ic_premux_data, input io_ic_sel_premux_data, - input [1:0] io_ic_tag_valid, - input [70:0] io_ic_debug_wr_data, - input [70:0] io_ic_wr_data_0, - input [70:0] io_ic_wr_data_1, - output [63:0] io_ic_rd_data, - output [70:0] io_ic_debug_rd_data, - output [25:0] io_ictag_debug_rd_data, - output [1:0] io_ic_eccerr, - output [1:0] io_ic_parerr, - output [1:0] io_ic_rd_hit, - output io_ic_tag_perr + input [1:0] io_ic_rd_hit ); `ifdef RANDOMIZE_MEM_INIT reg [95:0] _RAND_0; @@ -38,188 +308,188 @@ module el2_ifu_ic_mem( reg [31:0] _RAND_6; reg [31:0] _RAND_7; `endif // RANDOMIZE_REG_INIT - reg [70:0] data_mem_0_0 [0:511]; // @[el2_ifu_ic_mem.scala 82:21] - wire [70:0] data_mem_0_0__T_145_data; // @[el2_ifu_ic_mem.scala 82:21] - wire [8:0] data_mem_0_0__T_145_addr; // @[el2_ifu_ic_mem.scala 82:21] - wire [70:0] data_mem_0_0__T_158_data; // @[el2_ifu_ic_mem.scala 82:21] - wire [8:0] data_mem_0_0__T_158_addr; // @[el2_ifu_ic_mem.scala 82:21] - wire [70:0] data_mem_0_0__T_171_data; // @[el2_ifu_ic_mem.scala 82:21] - wire [8:0] data_mem_0_0__T_171_addr; // @[el2_ifu_ic_mem.scala 82:21] - wire [70:0] data_mem_0_0__T_184_data; // @[el2_ifu_ic_mem.scala 82:21] - wire [8:0] data_mem_0_0__T_184_addr; // @[el2_ifu_ic_mem.scala 82:21] - wire [70:0] data_mem_0_0__T_139_data; // @[el2_ifu_ic_mem.scala 82:21] - wire [8:0] data_mem_0_0__T_139_addr; // @[el2_ifu_ic_mem.scala 82:21] - wire data_mem_0_0__T_139_mask; // @[el2_ifu_ic_mem.scala 82:21] - wire data_mem_0_0__T_139_en; // @[el2_ifu_ic_mem.scala 82:21] - wire [70:0] data_mem_0_0__T_152_data; // @[el2_ifu_ic_mem.scala 82:21] - wire [8:0] data_mem_0_0__T_152_addr; // @[el2_ifu_ic_mem.scala 82:21] - wire data_mem_0_0__T_152_mask; // @[el2_ifu_ic_mem.scala 82:21] - wire data_mem_0_0__T_152_en; // @[el2_ifu_ic_mem.scala 82:21] - wire [70:0] data_mem_0_0__T_165_data; // @[el2_ifu_ic_mem.scala 82:21] - wire [8:0] data_mem_0_0__T_165_addr; // @[el2_ifu_ic_mem.scala 82:21] - wire data_mem_0_0__T_165_mask; // @[el2_ifu_ic_mem.scala 82:21] - wire data_mem_0_0__T_165_en; // @[el2_ifu_ic_mem.scala 82:21] - wire [70:0] data_mem_0_0__T_178_data; // @[el2_ifu_ic_mem.scala 82:21] - wire [8:0] data_mem_0_0__T_178_addr; // @[el2_ifu_ic_mem.scala 82:21] - wire data_mem_0_0__T_178_mask; // @[el2_ifu_ic_mem.scala 82:21] - wire data_mem_0_0__T_178_en; // @[el2_ifu_ic_mem.scala 82:21] - reg [70:0] data_mem_0_1 [0:511]; // @[el2_ifu_ic_mem.scala 82:21] - wire [70:0] data_mem_0_1__T_145_data; // @[el2_ifu_ic_mem.scala 82:21] - wire [8:0] data_mem_0_1__T_145_addr; // @[el2_ifu_ic_mem.scala 82:21] - wire [70:0] data_mem_0_1__T_158_data; // @[el2_ifu_ic_mem.scala 82:21] - wire [8:0] data_mem_0_1__T_158_addr; // @[el2_ifu_ic_mem.scala 82:21] - wire [70:0] data_mem_0_1__T_171_data; // @[el2_ifu_ic_mem.scala 82:21] - wire [8:0] data_mem_0_1__T_171_addr; // @[el2_ifu_ic_mem.scala 82:21] - wire [70:0] data_mem_0_1__T_184_data; // @[el2_ifu_ic_mem.scala 82:21] - wire [8:0] data_mem_0_1__T_184_addr; // @[el2_ifu_ic_mem.scala 82:21] - wire [70:0] data_mem_0_1__T_139_data; // @[el2_ifu_ic_mem.scala 82:21] - wire [8:0] data_mem_0_1__T_139_addr; // @[el2_ifu_ic_mem.scala 82:21] - wire data_mem_0_1__T_139_mask; // @[el2_ifu_ic_mem.scala 82:21] - wire data_mem_0_1__T_139_en; // @[el2_ifu_ic_mem.scala 82:21] - wire [70:0] data_mem_0_1__T_152_data; // @[el2_ifu_ic_mem.scala 82:21] - wire [8:0] data_mem_0_1__T_152_addr; // @[el2_ifu_ic_mem.scala 82:21] - wire data_mem_0_1__T_152_mask; // @[el2_ifu_ic_mem.scala 82:21] - wire data_mem_0_1__T_152_en; // @[el2_ifu_ic_mem.scala 82:21] - wire [70:0] data_mem_0_1__T_165_data; // @[el2_ifu_ic_mem.scala 82:21] - wire [8:0] data_mem_0_1__T_165_addr; // @[el2_ifu_ic_mem.scala 82:21] - wire data_mem_0_1__T_165_mask; // @[el2_ifu_ic_mem.scala 82:21] - wire data_mem_0_1__T_165_en; // @[el2_ifu_ic_mem.scala 82:21] - wire [70:0] data_mem_0_1__T_178_data; // @[el2_ifu_ic_mem.scala 82:21] - wire [8:0] data_mem_0_1__T_178_addr; // @[el2_ifu_ic_mem.scala 82:21] - wire data_mem_0_1__T_178_mask; // @[el2_ifu_ic_mem.scala 82:21] - wire data_mem_0_1__T_178_en; // @[el2_ifu_ic_mem.scala 82:21] - reg [70:0] data_mem_1_0 [0:511]; // @[el2_ifu_ic_mem.scala 82:21] - wire [70:0] data_mem_1_0__T_145_data; // @[el2_ifu_ic_mem.scala 82:21] - wire [8:0] data_mem_1_0__T_145_addr; // @[el2_ifu_ic_mem.scala 82:21] - wire [70:0] data_mem_1_0__T_158_data; // @[el2_ifu_ic_mem.scala 82:21] - wire [8:0] data_mem_1_0__T_158_addr; // @[el2_ifu_ic_mem.scala 82:21] - wire [70:0] data_mem_1_0__T_171_data; // @[el2_ifu_ic_mem.scala 82:21] - wire [8:0] data_mem_1_0__T_171_addr; // @[el2_ifu_ic_mem.scala 82:21] - wire [70:0] data_mem_1_0__T_184_data; // @[el2_ifu_ic_mem.scala 82:21] - wire [8:0] data_mem_1_0__T_184_addr; // @[el2_ifu_ic_mem.scala 82:21] - wire [70:0] data_mem_1_0__T_139_data; // @[el2_ifu_ic_mem.scala 82:21] - wire [8:0] data_mem_1_0__T_139_addr; // @[el2_ifu_ic_mem.scala 82:21] - wire data_mem_1_0__T_139_mask; // @[el2_ifu_ic_mem.scala 82:21] - wire data_mem_1_0__T_139_en; // @[el2_ifu_ic_mem.scala 82:21] - wire [70:0] data_mem_1_0__T_152_data; // @[el2_ifu_ic_mem.scala 82:21] - wire [8:0] data_mem_1_0__T_152_addr; // @[el2_ifu_ic_mem.scala 82:21] - wire data_mem_1_0__T_152_mask; // @[el2_ifu_ic_mem.scala 82:21] - wire data_mem_1_0__T_152_en; // @[el2_ifu_ic_mem.scala 82:21] - wire [70:0] data_mem_1_0__T_165_data; // @[el2_ifu_ic_mem.scala 82:21] - wire [8:0] data_mem_1_0__T_165_addr; // @[el2_ifu_ic_mem.scala 82:21] - wire data_mem_1_0__T_165_mask; // @[el2_ifu_ic_mem.scala 82:21] - wire data_mem_1_0__T_165_en; // @[el2_ifu_ic_mem.scala 82:21] - wire [70:0] data_mem_1_0__T_178_data; // @[el2_ifu_ic_mem.scala 82:21] - wire [8:0] data_mem_1_0__T_178_addr; // @[el2_ifu_ic_mem.scala 82:21] - wire data_mem_1_0__T_178_mask; // @[el2_ifu_ic_mem.scala 82:21] - wire data_mem_1_0__T_178_en; // @[el2_ifu_ic_mem.scala 82:21] - reg [70:0] data_mem_1_1 [0:511]; // @[el2_ifu_ic_mem.scala 82:21] - wire [70:0] data_mem_1_1__T_145_data; // @[el2_ifu_ic_mem.scala 82:21] - wire [8:0] data_mem_1_1__T_145_addr; // @[el2_ifu_ic_mem.scala 82:21] - wire [70:0] data_mem_1_1__T_158_data; // @[el2_ifu_ic_mem.scala 82:21] - wire [8:0] data_mem_1_1__T_158_addr; // @[el2_ifu_ic_mem.scala 82:21] - wire [70:0] data_mem_1_1__T_171_data; // @[el2_ifu_ic_mem.scala 82:21] - wire [8:0] data_mem_1_1__T_171_addr; // @[el2_ifu_ic_mem.scala 82:21] - wire [70:0] data_mem_1_1__T_184_data; // @[el2_ifu_ic_mem.scala 82:21] - wire [8:0] data_mem_1_1__T_184_addr; // @[el2_ifu_ic_mem.scala 82:21] - wire [70:0] data_mem_1_1__T_139_data; // @[el2_ifu_ic_mem.scala 82:21] - wire [8:0] data_mem_1_1__T_139_addr; // @[el2_ifu_ic_mem.scala 82:21] - wire data_mem_1_1__T_139_mask; // @[el2_ifu_ic_mem.scala 82:21] - wire data_mem_1_1__T_139_en; // @[el2_ifu_ic_mem.scala 82:21] - wire [70:0] data_mem_1_1__T_152_data; // @[el2_ifu_ic_mem.scala 82:21] - wire [8:0] data_mem_1_1__T_152_addr; // @[el2_ifu_ic_mem.scala 82:21] - wire data_mem_1_1__T_152_mask; // @[el2_ifu_ic_mem.scala 82:21] - wire data_mem_1_1__T_152_en; // @[el2_ifu_ic_mem.scala 82:21] - wire [70:0] data_mem_1_1__T_165_data; // @[el2_ifu_ic_mem.scala 82:21] - wire [8:0] data_mem_1_1__T_165_addr; // @[el2_ifu_ic_mem.scala 82:21] - wire data_mem_1_1__T_165_mask; // @[el2_ifu_ic_mem.scala 82:21] - wire data_mem_1_1__T_165_en; // @[el2_ifu_ic_mem.scala 82:21] - wire [70:0] data_mem_1_1__T_178_data; // @[el2_ifu_ic_mem.scala 82:21] - wire [8:0] data_mem_1_1__T_178_addr; // @[el2_ifu_ic_mem.scala 82:21] - wire data_mem_1_1__T_178_mask; // @[el2_ifu_ic_mem.scala 82:21] - wire data_mem_1_1__T_178_en; // @[el2_ifu_ic_mem.scala 82:21] - wire _T = ~io_ic_debug_tag_array; // @[el2_ifu_ic_mem.scala 42:70] - wire _T_1 = io_ic_debug_rd_en & _T; // @[el2_ifu_ic_mem.scala 42:68] + reg [70:0] data_mem_0_0 [0:511]; // @[el2_ifu_ic_mem.scala 235:21] + wire [70:0] data_mem_0_0__T_145_data; // @[el2_ifu_ic_mem.scala 235:21] + wire [8:0] data_mem_0_0__T_145_addr; // @[el2_ifu_ic_mem.scala 235:21] + wire [70:0] data_mem_0_0__T_158_data; // @[el2_ifu_ic_mem.scala 235:21] + wire [8:0] data_mem_0_0__T_158_addr; // @[el2_ifu_ic_mem.scala 235:21] + wire [70:0] data_mem_0_0__T_171_data; // @[el2_ifu_ic_mem.scala 235:21] + wire [8:0] data_mem_0_0__T_171_addr; // @[el2_ifu_ic_mem.scala 235:21] + wire [70:0] data_mem_0_0__T_184_data; // @[el2_ifu_ic_mem.scala 235:21] + wire [8:0] data_mem_0_0__T_184_addr; // @[el2_ifu_ic_mem.scala 235:21] + wire [70:0] data_mem_0_0__T_139_data; // @[el2_ifu_ic_mem.scala 235:21] + wire [8:0] data_mem_0_0__T_139_addr; // @[el2_ifu_ic_mem.scala 235:21] + wire data_mem_0_0__T_139_mask; // @[el2_ifu_ic_mem.scala 235:21] + wire data_mem_0_0__T_139_en; // @[el2_ifu_ic_mem.scala 235:21] + wire [70:0] data_mem_0_0__T_152_data; // @[el2_ifu_ic_mem.scala 235:21] + wire [8:0] data_mem_0_0__T_152_addr; // @[el2_ifu_ic_mem.scala 235:21] + wire data_mem_0_0__T_152_mask; // @[el2_ifu_ic_mem.scala 235:21] + wire data_mem_0_0__T_152_en; // @[el2_ifu_ic_mem.scala 235:21] + wire [70:0] data_mem_0_0__T_165_data; // @[el2_ifu_ic_mem.scala 235:21] + wire [8:0] data_mem_0_0__T_165_addr; // @[el2_ifu_ic_mem.scala 235:21] + wire data_mem_0_0__T_165_mask; // @[el2_ifu_ic_mem.scala 235:21] + wire data_mem_0_0__T_165_en; // @[el2_ifu_ic_mem.scala 235:21] + wire [70:0] data_mem_0_0__T_178_data; // @[el2_ifu_ic_mem.scala 235:21] + wire [8:0] data_mem_0_0__T_178_addr; // @[el2_ifu_ic_mem.scala 235:21] + wire data_mem_0_0__T_178_mask; // @[el2_ifu_ic_mem.scala 235:21] + wire data_mem_0_0__T_178_en; // @[el2_ifu_ic_mem.scala 235:21] + reg [70:0] data_mem_0_1 [0:511]; // @[el2_ifu_ic_mem.scala 235:21] + wire [70:0] data_mem_0_1__T_145_data; // @[el2_ifu_ic_mem.scala 235:21] + wire [8:0] data_mem_0_1__T_145_addr; // @[el2_ifu_ic_mem.scala 235:21] + wire [70:0] data_mem_0_1__T_158_data; // @[el2_ifu_ic_mem.scala 235:21] + wire [8:0] data_mem_0_1__T_158_addr; // @[el2_ifu_ic_mem.scala 235:21] + wire [70:0] data_mem_0_1__T_171_data; // @[el2_ifu_ic_mem.scala 235:21] + wire [8:0] data_mem_0_1__T_171_addr; // @[el2_ifu_ic_mem.scala 235:21] + wire [70:0] data_mem_0_1__T_184_data; // @[el2_ifu_ic_mem.scala 235:21] + wire [8:0] data_mem_0_1__T_184_addr; // @[el2_ifu_ic_mem.scala 235:21] + wire [70:0] data_mem_0_1__T_139_data; // @[el2_ifu_ic_mem.scala 235:21] + wire [8:0] data_mem_0_1__T_139_addr; // @[el2_ifu_ic_mem.scala 235:21] + wire data_mem_0_1__T_139_mask; // @[el2_ifu_ic_mem.scala 235:21] + wire data_mem_0_1__T_139_en; // @[el2_ifu_ic_mem.scala 235:21] + wire [70:0] data_mem_0_1__T_152_data; // @[el2_ifu_ic_mem.scala 235:21] + wire [8:0] data_mem_0_1__T_152_addr; // @[el2_ifu_ic_mem.scala 235:21] + wire data_mem_0_1__T_152_mask; // @[el2_ifu_ic_mem.scala 235:21] + wire data_mem_0_1__T_152_en; // @[el2_ifu_ic_mem.scala 235:21] + wire [70:0] data_mem_0_1__T_165_data; // @[el2_ifu_ic_mem.scala 235:21] + wire [8:0] data_mem_0_1__T_165_addr; // @[el2_ifu_ic_mem.scala 235:21] + wire data_mem_0_1__T_165_mask; // @[el2_ifu_ic_mem.scala 235:21] + wire data_mem_0_1__T_165_en; // @[el2_ifu_ic_mem.scala 235:21] + wire [70:0] data_mem_0_1__T_178_data; // @[el2_ifu_ic_mem.scala 235:21] + wire [8:0] data_mem_0_1__T_178_addr; // @[el2_ifu_ic_mem.scala 235:21] + wire data_mem_0_1__T_178_mask; // @[el2_ifu_ic_mem.scala 235:21] + wire data_mem_0_1__T_178_en; // @[el2_ifu_ic_mem.scala 235:21] + reg [70:0] data_mem_1_0 [0:511]; // @[el2_ifu_ic_mem.scala 235:21] + wire [70:0] data_mem_1_0__T_145_data; // @[el2_ifu_ic_mem.scala 235:21] + wire [8:0] data_mem_1_0__T_145_addr; // @[el2_ifu_ic_mem.scala 235:21] + wire [70:0] data_mem_1_0__T_158_data; // @[el2_ifu_ic_mem.scala 235:21] + wire [8:0] data_mem_1_0__T_158_addr; // @[el2_ifu_ic_mem.scala 235:21] + wire [70:0] data_mem_1_0__T_171_data; // @[el2_ifu_ic_mem.scala 235:21] + wire [8:0] data_mem_1_0__T_171_addr; // @[el2_ifu_ic_mem.scala 235:21] + wire [70:0] data_mem_1_0__T_184_data; // @[el2_ifu_ic_mem.scala 235:21] + wire [8:0] data_mem_1_0__T_184_addr; // @[el2_ifu_ic_mem.scala 235:21] + wire [70:0] data_mem_1_0__T_139_data; // @[el2_ifu_ic_mem.scala 235:21] + wire [8:0] data_mem_1_0__T_139_addr; // @[el2_ifu_ic_mem.scala 235:21] + wire data_mem_1_0__T_139_mask; // @[el2_ifu_ic_mem.scala 235:21] + wire data_mem_1_0__T_139_en; // @[el2_ifu_ic_mem.scala 235:21] + wire [70:0] data_mem_1_0__T_152_data; // @[el2_ifu_ic_mem.scala 235:21] + wire [8:0] data_mem_1_0__T_152_addr; // @[el2_ifu_ic_mem.scala 235:21] + wire data_mem_1_0__T_152_mask; // @[el2_ifu_ic_mem.scala 235:21] + wire data_mem_1_0__T_152_en; // @[el2_ifu_ic_mem.scala 235:21] + wire [70:0] data_mem_1_0__T_165_data; // @[el2_ifu_ic_mem.scala 235:21] + wire [8:0] data_mem_1_0__T_165_addr; // @[el2_ifu_ic_mem.scala 235:21] + wire data_mem_1_0__T_165_mask; // @[el2_ifu_ic_mem.scala 235:21] + wire data_mem_1_0__T_165_en; // @[el2_ifu_ic_mem.scala 235:21] + wire [70:0] data_mem_1_0__T_178_data; // @[el2_ifu_ic_mem.scala 235:21] + wire [8:0] data_mem_1_0__T_178_addr; // @[el2_ifu_ic_mem.scala 235:21] + wire data_mem_1_0__T_178_mask; // @[el2_ifu_ic_mem.scala 235:21] + wire data_mem_1_0__T_178_en; // @[el2_ifu_ic_mem.scala 235:21] + reg [70:0] data_mem_1_1 [0:511]; // @[el2_ifu_ic_mem.scala 235:21] + wire [70:0] data_mem_1_1__T_145_data; // @[el2_ifu_ic_mem.scala 235:21] + wire [8:0] data_mem_1_1__T_145_addr; // @[el2_ifu_ic_mem.scala 235:21] + wire [70:0] data_mem_1_1__T_158_data; // @[el2_ifu_ic_mem.scala 235:21] + wire [8:0] data_mem_1_1__T_158_addr; // @[el2_ifu_ic_mem.scala 235:21] + wire [70:0] data_mem_1_1__T_171_data; // @[el2_ifu_ic_mem.scala 235:21] + wire [8:0] data_mem_1_1__T_171_addr; // @[el2_ifu_ic_mem.scala 235:21] + wire [70:0] data_mem_1_1__T_184_data; // @[el2_ifu_ic_mem.scala 235:21] + wire [8:0] data_mem_1_1__T_184_addr; // @[el2_ifu_ic_mem.scala 235:21] + wire [70:0] data_mem_1_1__T_139_data; // @[el2_ifu_ic_mem.scala 235:21] + wire [8:0] data_mem_1_1__T_139_addr; // @[el2_ifu_ic_mem.scala 235:21] + wire data_mem_1_1__T_139_mask; // @[el2_ifu_ic_mem.scala 235:21] + wire data_mem_1_1__T_139_en; // @[el2_ifu_ic_mem.scala 235:21] + wire [70:0] data_mem_1_1__T_152_data; // @[el2_ifu_ic_mem.scala 235:21] + wire [8:0] data_mem_1_1__T_152_addr; // @[el2_ifu_ic_mem.scala 235:21] + wire data_mem_1_1__T_152_mask; // @[el2_ifu_ic_mem.scala 235:21] + wire data_mem_1_1__T_152_en; // @[el2_ifu_ic_mem.scala 235:21] + wire [70:0] data_mem_1_1__T_165_data; // @[el2_ifu_ic_mem.scala 235:21] + wire [8:0] data_mem_1_1__T_165_addr; // @[el2_ifu_ic_mem.scala 235:21] + wire data_mem_1_1__T_165_mask; // @[el2_ifu_ic_mem.scala 235:21] + wire data_mem_1_1__T_165_en; // @[el2_ifu_ic_mem.scala 235:21] + wire [70:0] data_mem_1_1__T_178_data; // @[el2_ifu_ic_mem.scala 235:21] + wire [8:0] data_mem_1_1__T_178_addr; // @[el2_ifu_ic_mem.scala 235:21] + wire data_mem_1_1__T_178_mask; // @[el2_ifu_ic_mem.scala 235:21] + wire data_mem_1_1__T_178_en; // @[el2_ifu_ic_mem.scala 235:21] + wire _T = ~io_ic_debug_tag_array; // @[el2_ifu_ic_mem.scala 195:70] + wire _T_1 = io_ic_debug_rd_en & _T; // @[el2_ifu_ic_mem.scala 195:68] wire [1:0] _T_3 = _T_1 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] ic_debug_rd_way_en = _T_3 & io_ic_debug_way; // @[el2_ifu_ic_mem.scala 42:94] - wire _T_5 = io_ic_debug_wr_en & _T; // @[el2_ifu_ic_mem.scala 43:68] + wire [1:0] ic_debug_rd_way_en = _T_3 & io_ic_debug_way; // @[el2_ifu_ic_mem.scala 195:94] + wire _T_5 = io_ic_debug_wr_en & _T; // @[el2_ifu_ic_mem.scala 196:68] wire [1:0] _T_7 = _T_5 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] ic_debug_wr_way_en = _T_7 & io_ic_debug_way; // @[el2_ifu_ic_mem.scala 43:94] - wire _T_8 = io_ic_debug_rd_en | io_ic_debug_wr_en; // @[el2_ifu_ic_mem.scala 48:45] + wire [1:0] ic_debug_wr_way_en = _T_7 & io_ic_debug_way; // @[el2_ifu_ic_mem.scala 196:94] + wire _T_8 = io_ic_debug_rd_en | io_ic_debug_wr_en; // @[el2_ifu_ic_mem.scala 201:45] wire [10:0] _T_10 = {io_ic_debug_addr,2'h0}; // @[Cat.scala 29:58] - wire [30:0] ic_rw_addr_q = _T_8 ? {{20'd0}, _T_10} : io_ic_rw_addr; // @[el2_ifu_ic_mem.scala 48:25] - wire [8:0] ic_rw_addr_q_inc = ic_rw_addr_q[11:3] + 9'h1; // @[el2_ifu_ic_mem.scala 50:79] - wire _T_14 = ~io_ic_debug_addr[0]; // @[el2_ifu_ic_mem.scala 52:113] + wire [11:0] ic_rw_addr_q = _T_8 ? {{1'd0}, _T_10} : io_ic_rw_addr; // @[el2_ifu_ic_mem.scala 201:25] + wire [8:0] ic_rw_addr_q_inc = ic_rw_addr_q[11:3] + 9'h1; // @[el2_ifu_ic_mem.scala 203:79] + wire _T_14 = ~io_ic_debug_addr[0]; // @[el2_ifu_ic_mem.scala 205:113] wire [1:0] _T_16 = _T_14 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_17 = ic_debug_wr_way_en & _T_16; // @[el2_ifu_ic_mem.scala 52:38] - wire [1:0] ic_b_sb_wren_0 = io_ic_wr_en | _T_17; // @[el2_ifu_ic_mem.scala 52:17] + wire [1:0] _T_17 = ic_debug_wr_way_en & _T_16; // @[el2_ifu_ic_mem.scala 205:38] + wire [1:0] ic_b_sb_wren_0 = io_ic_wr_en | _T_17; // @[el2_ifu_ic_mem.scala 205:17] wire [1:0] _T_21 = io_ic_debug_addr[0] ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_22 = ic_debug_wr_way_en & _T_21; // @[el2_ifu_ic_mem.scala 52:38] - wire [1:0] ic_b_sb_wren_1 = io_ic_wr_en | _T_22; // @[el2_ifu_ic_mem.scala 52:17] + wire [1:0] _T_22 = ic_debug_wr_way_en & _T_21; // @[el2_ifu_ic_mem.scala 205:38] + wire [1:0] ic_b_sb_wren_1 = io_ic_wr_en | _T_22; // @[el2_ifu_ic_mem.scala 205:17] wire [1:0] ic_debug_sel_sb = {io_ic_debug_addr[0],_T_14}; // @[Cat.scala 29:58] - wire _T_28 = ic_debug_sel_sb[0] & io_ic_debug_wr_en; // @[el2_ifu_ic_mem.scala 54:80] - wire _T_31 = ic_debug_sel_sb[1] & io_ic_debug_wr_en; // @[el2_ifu_ic_mem.scala 54:80] - wire _T_35 = ~ic_rw_addr_q[2]; // @[el2_ifu_ic_mem.scala 56:16] - wire _T_40 = ic_rw_addr_q[1:0] == 2'h3; // @[el2_ifu_ic_mem.scala 57:69] + wire _T_28 = ic_debug_sel_sb[0] & io_ic_debug_wr_en; // @[el2_ifu_ic_mem.scala 207:80] + wire _T_31 = ic_debug_sel_sb[1] & io_ic_debug_wr_en; // @[el2_ifu_ic_mem.scala 207:80] + wire _T_35 = ~ic_rw_addr_q[2]; // @[el2_ifu_ic_mem.scala 209:16] + wire _T_40 = ic_rw_addr_q[1:0] == 2'h3; // @[el2_ifu_ic_mem.scala 210:91] wire _T_54 = ic_rw_addr_q[2] & _T_40; // @[Mux.scala 27:72] wire _T_57 = _T_35 | _T_54; // @[Mux.scala 27:72] - wire _T_111 = |io_ic_wr_en; // @[el2_ifu_ic_mem.scala 64:74] - wire _T_112 = ~_T_111; // @[el2_ifu_ic_mem.scala 64:61] - wire _T_113 = io_ic_debug_rd_en & _T_112; // @[el2_ifu_ic_mem.scala 64:58] - wire ic_rd_en_with_debug = io_ic_rd_en | _T_113; // @[el2_ifu_ic_mem.scala 64:38] - wire _T_61 = _T_57 & ic_rd_en_with_debug; // @[el2_ifu_ic_mem.scala 59:95] + wire _T_111 = |io_ic_wr_en; // @[el2_ifu_ic_mem.scala 217:74] + wire _T_112 = ~_T_111; // @[el2_ifu_ic_mem.scala 217:61] + wire _T_113 = io_ic_debug_rd_en & _T_112; // @[el2_ifu_ic_mem.scala 217:58] + wire ic_rd_en_with_debug = io_ic_rd_en | _T_113; // @[el2_ifu_ic_mem.scala 217:38] + wire _T_61 = _T_57 & ic_rd_en_with_debug; // @[el2_ifu_ic_mem.scala 212:117] wire _T_85 = _T_35 & _T_40; // @[Mux.scala 27:72] wire _T_88 = ic_rw_addr_q[2] | _T_85; // @[Mux.scala 27:72] - wire _T_90 = _T_88 & ic_rd_en_with_debug; // @[el2_ifu_ic_mem.scala 59:95] + wire _T_90 = _T_88 & ic_rd_en_with_debug; // @[el2_ifu_ic_mem.scala 212:117] wire [1:0] ic_b_rden = {_T_90,_T_61}; // @[Cat.scala 29:58] wire [1:0] ic_b_sb_rden_0 = ic_b_rden[0] ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] wire [1:0] ic_b_sb_rden_1 = ic_b_rden[1] ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire _T_96 = ic_b_sb_rden_0[0] | io_clk_override; // @[el2_ifu_ic_mem.scala 62:25] - wire _T_98 = _T_96 | ic_b_sb_wren_0[0]; // @[el2_ifu_ic_mem.scala 62:43] - wire _T_100 = ic_b_sb_rden_0[1] | io_clk_override; // @[el2_ifu_ic_mem.scala 62:25] - wire _T_102 = _T_100 | ic_b_sb_wren_0[1]; // @[el2_ifu_ic_mem.scala 62:43] + wire _T_96 = ic_b_sb_rden_0[0] | io_clk_override; // @[el2_ifu_ic_mem.scala 215:25] + wire _T_98 = _T_96 | ic_b_sb_wren_0[0]; // @[el2_ifu_ic_mem.scala 215:43] + wire _T_100 = ic_b_sb_rden_0[1] | io_clk_override; // @[el2_ifu_ic_mem.scala 215:25] + wire _T_102 = _T_100 | ic_b_sb_wren_0[1]; // @[el2_ifu_ic_mem.scala 215:43] wire [1:0] ic_bank_way_clken_0 = {_T_98,_T_102}; // @[Cat.scala 29:58] - wire _T_104 = ic_b_sb_rden_1[0] | io_clk_override; // @[el2_ifu_ic_mem.scala 62:25] - wire _T_106 = _T_104 | ic_b_sb_wren_1[0]; // @[el2_ifu_ic_mem.scala 62:43] - wire _T_108 = ic_b_sb_rden_1[1] | io_clk_override; // @[el2_ifu_ic_mem.scala 62:25] - wire _T_110 = _T_108 | ic_b_sb_wren_1[1]; // @[el2_ifu_ic_mem.scala 62:43] + wire _T_104 = ic_b_sb_rden_1[0] | io_clk_override; // @[el2_ifu_ic_mem.scala 215:25] + wire _T_106 = _T_104 | ic_b_sb_wren_1[0]; // @[el2_ifu_ic_mem.scala 215:43] + wire _T_108 = ic_b_sb_rden_1[1] | io_clk_override; // @[el2_ifu_ic_mem.scala 215:25] + wire _T_110 = _T_108 | ic_b_sb_wren_1[1]; // @[el2_ifu_ic_mem.scala 215:43] wire [1:0] ic_bank_way_clken_1 = {_T_106,_T_110}; // @[Cat.scala 29:58] - wire _T_119 = _T_54 & ic_rd_en_with_debug; // @[el2_ifu_ic_mem.scala 66:86] - wire ic_rw_addr_wrap = _T_119 & _T_112; // @[el2_ifu_ic_mem.scala 66:108] - wire _T_122 = ~ic_rw_addr_wrap; // @[el2_ifu_ic_mem.scala 68:40] + wire _T_119 = _T_54 & ic_rd_en_with_debug; // @[el2_ifu_ic_mem.scala 219:86] + wire ic_rw_addr_wrap = _T_119 & _T_112; // @[el2_ifu_ic_mem.scala 219:108] + wire _T_122 = ~ic_rw_addr_wrap; // @[el2_ifu_ic_mem.scala 221:40] wire [8:0] _T_127 = {ic_rw_addr_q[11:5],ic_rw_addr_q_inc[4:3]}; // @[Cat.scala 29:58] - reg [1:0] ic_b_rden_ff; // @[el2_ifu_ic_mem.scala 72:29] - reg [4:0] ic_rw_addr_ff; // @[el2_ifu_ic_mem.scala 73:30] - reg [1:0] ic_debug_rd_way_en_ff; // @[el2_ifu_ic_mem.scala 74:38] - reg ic_debug_rd_en_ff; // @[el2_ifu_ic_mem.scala 75:34] - wire ic_cacheline_wrap_ff = ic_rw_addr_ff[4:2] == 3'h7; // @[el2_ifu_ic_mem.scala 77:84] - wire _T_137 = ic_b_sb_wren_0[0] & ic_bank_way_clken_0[0]; // @[el2_ifu_ic_mem.scala 87:30] - wire _T_141 = ~ic_b_sb_wren_0[0]; // @[el2_ifu_ic_mem.scala 89:17] - wire _T_143 = _T_141 & ic_bank_way_clken_0[0]; // @[el2_ifu_ic_mem.scala 89:36] - wire [70:0] _GEN_3 = _T_143 ? data_mem_0_0__T_145_data : 71'h0; // @[el2_ifu_ic_mem.scala 89:69] - wire [70:0] wb_dout_0_0 = _T_137 ? 71'h0 : _GEN_3; // @[el2_ifu_ic_mem.scala 87:64] - wire _T_150 = ic_b_sb_wren_1[0] & ic_bank_way_clken_1[0]; // @[el2_ifu_ic_mem.scala 87:30] - wire _T_154 = ~ic_b_sb_wren_1[0]; // @[el2_ifu_ic_mem.scala 89:17] - wire _T_156 = _T_154 & ic_bank_way_clken_1[0]; // @[el2_ifu_ic_mem.scala 89:36] - wire [70:0] _GEN_17 = _T_156 ? data_mem_1_0__T_158_data : 71'h0; // @[el2_ifu_ic_mem.scala 89:69] - wire [70:0] wb_dout_0_1 = _T_150 ? 71'h0 : _GEN_17; // @[el2_ifu_ic_mem.scala 87:64] - wire _T_163 = ic_b_sb_wren_0[1] & ic_bank_way_clken_0[1]; // @[el2_ifu_ic_mem.scala 87:30] - wire _T_167 = ~ic_b_sb_wren_0[1]; // @[el2_ifu_ic_mem.scala 89:17] - wire _T_169 = _T_167 & ic_bank_way_clken_0[1]; // @[el2_ifu_ic_mem.scala 89:36] - wire [70:0] _GEN_31 = _T_169 ? data_mem_0_1__T_171_data : 71'h0; // @[el2_ifu_ic_mem.scala 89:69] - wire [70:0] wb_dout_1_0 = _T_163 ? 71'h0 : _GEN_31; // @[el2_ifu_ic_mem.scala 87:64] - wire _T_176 = ic_b_sb_wren_1[1] & ic_bank_way_clken_1[1]; // @[el2_ifu_ic_mem.scala 87:30] - wire _T_180 = ~ic_b_sb_wren_1[1]; // @[el2_ifu_ic_mem.scala 89:17] - wire _T_182 = _T_180 & ic_bank_way_clken_1[1]; // @[el2_ifu_ic_mem.scala 89:36] - wire [70:0] _GEN_45 = _T_182 ? data_mem_1_1__T_184_data : 71'h0; // @[el2_ifu_ic_mem.scala 89:69] - wire [70:0] wb_dout_1_1 = _T_176 ? 71'h0 : _GEN_45; // @[el2_ifu_ic_mem.scala 87:64] - wire [1:0] ic_rd_hit_q = ic_debug_rd_en_ff ? ic_debug_rd_way_en_ff : io_ic_rd_hit; // @[el2_ifu_ic_mem.scala 93:24] - wire _T_187 = ~ic_rw_addr_ff[2]; // @[el2_ifu_ic_mem.scala 97:95] + reg [1:0] ic_b_rden_ff; // @[el2_ifu_ic_mem.scala 225:29] + reg [4:0] ic_rw_addr_ff; // @[el2_ifu_ic_mem.scala 226:30] + reg [1:0] ic_debug_rd_way_en_ff; // @[el2_ifu_ic_mem.scala 227:38] + reg ic_debug_rd_en_ff; // @[el2_ifu_ic_mem.scala 228:34] + wire ic_cacheline_wrap_ff = ic_rw_addr_ff[4:2] == 3'h7; // @[el2_ifu_ic_mem.scala 230:84] + wire _T_137 = ic_b_sb_wren_0[0] & ic_bank_way_clken_0[0]; // @[el2_ifu_ic_mem.scala 240:30] + wire _T_141 = ~ic_b_sb_wren_0[0]; // @[el2_ifu_ic_mem.scala 242:17] + wire _T_143 = _T_141 & ic_bank_way_clken_0[0]; // @[el2_ifu_ic_mem.scala 242:36] + wire [70:0] _GEN_3 = _T_143 ? data_mem_0_0__T_145_data : 71'h0; // @[el2_ifu_ic_mem.scala 242:69] + wire [70:0] wb_dout_0_0 = _T_137 ? 71'h0 : _GEN_3; // @[el2_ifu_ic_mem.scala 240:64] + wire _T_150 = ic_b_sb_wren_1[0] & ic_bank_way_clken_1[0]; // @[el2_ifu_ic_mem.scala 240:30] + wire _T_154 = ~ic_b_sb_wren_1[0]; // @[el2_ifu_ic_mem.scala 242:17] + wire _T_156 = _T_154 & ic_bank_way_clken_1[0]; // @[el2_ifu_ic_mem.scala 242:36] + wire [70:0] _GEN_17 = _T_156 ? data_mem_1_0__T_158_data : 71'h0; // @[el2_ifu_ic_mem.scala 242:69] + wire [70:0] wb_dout_0_1 = _T_150 ? 71'h0 : _GEN_17; // @[el2_ifu_ic_mem.scala 240:64] + wire _T_163 = ic_b_sb_wren_0[1] & ic_bank_way_clken_0[1]; // @[el2_ifu_ic_mem.scala 240:30] + wire _T_167 = ~ic_b_sb_wren_0[1]; // @[el2_ifu_ic_mem.scala 242:17] + wire _T_169 = _T_167 & ic_bank_way_clken_0[1]; // @[el2_ifu_ic_mem.scala 242:36] + wire [70:0] _GEN_31 = _T_169 ? data_mem_0_1__T_171_data : 71'h0; // @[el2_ifu_ic_mem.scala 242:69] + wire [70:0] wb_dout_1_0 = _T_163 ? 71'h0 : _GEN_31; // @[el2_ifu_ic_mem.scala 240:64] + wire _T_176 = ic_b_sb_wren_1[1] & ic_bank_way_clken_1[1]; // @[el2_ifu_ic_mem.scala 240:30] + wire _T_180 = ~ic_b_sb_wren_1[1]; // @[el2_ifu_ic_mem.scala 242:17] + wire _T_182 = _T_180 & ic_bank_way_clken_1[1]; // @[el2_ifu_ic_mem.scala 242:36] + wire [70:0] _GEN_45 = _T_182 ? data_mem_1_1__T_184_data : 71'h0; // @[el2_ifu_ic_mem.scala 242:69] + wire [70:0] wb_dout_1_1 = _T_176 ? 71'h0 : _GEN_45; // @[el2_ifu_ic_mem.scala 240:64] + wire [1:0] ic_rd_hit_q = ic_debug_rd_en_ff ? ic_debug_rd_way_en_ff : io_ic_rd_hit; // @[el2_ifu_ic_mem.scala 246:24] + wire _T_187 = ~ic_rw_addr_ff[2]; // @[el2_ifu_ic_mem.scala 250:95] wire [70:0] _T_192 = _T_187 ? wb_dout_0_0 : 71'h0; // @[Mux.scala 27:72] wire [70:0] _T_193 = ic_rw_addr_ff[2] ? wb_dout_0_1 : 71'h0; // @[Mux.scala 27:72] wire [70:0] _T_194 = _T_192 | _T_193; // @[Mux.scala 27:72] - wire _T_198 = 1'h0 - 1'h1; // @[el2_ifu_ic_mem.scala 98:102] - wire _T_199 = ic_rw_addr_ff[2] == _T_198; // @[el2_ifu_ic_mem.scala 98:95] + wire _T_198 = 1'h0 - 1'h1; // @[el2_ifu_ic_mem.scala 251:102] + wire _T_199 = ic_rw_addr_ff[2] == _T_198; // @[el2_ifu_ic_mem.scala 251:95] wire [70:0] _T_206 = _T_199 ? wb_dout_0_0 : 71'h0; // @[Mux.scala 27:72] wire [70:0] _T_207 = _T_187 ? wb_dout_0_1 : 71'h0; // @[Mux.scala 27:72] wire [70:0] _T_208 = _T_206 | _T_207; // @[Mux.scala 27:72] @@ -231,12 +501,12 @@ module el2_ifu_ic_mem( wire [70:0] _T_231 = _T_187 ? wb_dout_1_1 : 71'h0; // @[Mux.scala 27:72] wire [70:0] _T_232 = _T_230 | _T_231; // @[Mux.scala 27:72] wire [141:0] wb_dout_way_pre_1 = {_T_218,_T_232}; // @[Cat.scala 29:58] - wire _T_235 = ic_rw_addr_ff[1:0] == 2'h0; // @[el2_ifu_ic_mem.scala 100:83] - wire _T_239 = ic_rw_addr_ff[1:0] == 2'h1; // @[el2_ifu_ic_mem.scala 101:24] + wire _T_235 = ic_rw_addr_ff[1:0] == 2'h0; // @[el2_ifu_ic_mem.scala 253:83] + wire _T_239 = ic_rw_addr_ff[1:0] == 2'h1; // @[el2_ifu_ic_mem.scala 254:24] wire [63:0] _T_243 = {wb_dout_way_pre_0[86:71],wb_dout_way_pre_0[63:16]}; // @[Cat.scala 29:58] - wire _T_245 = ic_rw_addr_ff[1:0] == 2'h2; // @[el2_ifu_ic_mem.scala 102:24] + wire _T_245 = ic_rw_addr_ff[1:0] == 2'h2; // @[el2_ifu_ic_mem.scala 255:24] wire [63:0] _T_249 = {wb_dout_way_pre_0[102:71],wb_dout_way_pre_0[63:32]}; // @[Cat.scala 29:58] - wire _T_251 = ic_rw_addr_ff[1:0] == 2'h3; // @[el2_ifu_ic_mem.scala 103:24] + wire _T_251 = ic_rw_addr_ff[1:0] == 2'h3; // @[el2_ifu_ic_mem.scala 256:24] wire [63:0] _T_255 = {wb_dout_way_pre_0[118:71],wb_dout_way_pre_0[63:48]}; // @[Cat.scala 29:58] wire [63:0] _T_256 = _T_235 ? wb_dout_way_pre_0[63:0] : 64'h0; // @[Mux.scala 27:72] wire [63:0] _T_257 = _T_239 ? _T_243 : 64'h0; // @[Mux.scala 27:72] @@ -255,10 +525,10 @@ module el2_ifu_ic_mem( wire [63:0] _T_289 = _T_285 | _T_286; // @[Mux.scala 27:72] wire [63:0] _T_290 = _T_289 | _T_287; // @[Mux.scala 27:72] wire [63:0] wb_dout_way_1 = _T_290 | _T_288; // @[Mux.scala 27:72] - wire [63:0] wb_dout_way_with_premux_0 = io_ic_sel_premux_data ? io_ic_premux_data : wb_dout_way_0; // @[el2_ifu_ic_mem.scala 105:69] - wire [63:0] wb_dout_way_with_premux_1 = io_ic_sel_premux_data ? io_ic_premux_data : wb_dout_way_1; // @[el2_ifu_ic_mem.scala 105:69] - wire _T_295 = ic_rd_hit_q[0] | io_ic_sel_premux_data; // @[el2_ifu_ic_mem.scala 107:75] - wire _T_298 = ic_rd_hit_q[1] | io_ic_sel_premux_data; // @[el2_ifu_ic_mem.scala 107:75] + wire [63:0] wb_dout_way_with_premux_0 = io_ic_sel_premux_data ? io_ic_premux_data : wb_dout_way_0; // @[el2_ifu_ic_mem.scala 258:69] + wire [63:0] wb_dout_way_with_premux_1 = io_ic_sel_premux_data ? io_ic_premux_data : wb_dout_way_1; // @[el2_ifu_ic_mem.scala 258:69] + wire _T_295 = ic_rd_hit_q[0] | io_ic_sel_premux_data; // @[el2_ifu_ic_mem.scala 260:75] + wire _T_298 = ic_rd_hit_q[1] | io_ic_sel_premux_data; // @[el2_ifu_ic_mem.scala 260:75] wire [63:0] _T_300 = _T_295 ? wb_dout_way_with_premux_0 : 64'h0; // @[Mux.scala 27:72] wire [63:0] _T_301 = _T_298 ? wb_dout_way_with_premux_1 : 64'h0; // @[Mux.scala 27:72] wire [70:0] _T_310 = ic_rd_hit_q[0] ? wb_dout_way_pre_0[70:0] : 71'h0; // @[Mux.scala 27:72] @@ -266,13 +536,13 @@ module el2_ifu_ic_mem( wire [141:0] _T_318 = ic_rd_hit_q[0] ? wb_dout_way_pre_0 : 142'h0; // @[Mux.scala 27:72] wire [141:0] _T_319 = ic_rd_hit_q[1] ? wb_dout_way_pre_1 : 142'h0; // @[Mux.scala 27:72] wire [141:0] wb_dout_ecc = _T_318 | _T_319; // @[Mux.scala 27:72] - wire _T_321 = |io_ic_rd_hit; // @[el2_ifu_ic_mem.scala 111:75] - wire _T_322 = ~ic_cacheline_wrap_ff; // @[el2_ifu_ic_mem.scala 111:103] - wire _T_325 = ic_b_rden_ff == 2'h3; // @[el2_ifu_ic_mem.scala 111:163] - wire _T_326 = _T_322 & _T_325; // @[el2_ifu_ic_mem.scala 111:125] - wire bank_check_en_0 = _T_321 & _T_326; // @[el2_ifu_ic_mem.scala 111:79] - wire [70:0] wb_dout_ecc_bank_0 = wb_dout_ecc[70:0]; // @[el2_ifu_ic_mem.scala 112:72] - wire [70:0] wb_dout_ecc_bank_1 = wb_dout_ecc[141:71]; // @[el2_ifu_ic_mem.scala 112:72] + wire _T_321 = |io_ic_rd_hit; // @[el2_ifu_ic_mem.scala 264:75] + wire _T_322 = ~ic_cacheline_wrap_ff; // @[el2_ifu_ic_mem.scala 264:103] + wire _T_325 = ic_b_rden_ff == 2'h3; // @[el2_ifu_ic_mem.scala 264:163] + wire _T_326 = _T_322 & _T_325; // @[el2_ifu_ic_mem.scala 264:125] + wire bank_check_en_0 = _T_321 & _T_326; // @[el2_ifu_ic_mem.scala 264:79] + wire [70:0] wb_dout_ecc_bank_0 = wb_dout_ecc[70:0]; // @[el2_ifu_ic_mem.scala 265:72] + wire [70:0] wb_dout_ecc_bank_1 = wb_dout_ecc[141:71]; // @[el2_ifu_ic_mem.scala 265:72] wire [6:0] _T_555 = {wb_dout_ecc_bank_0[63],wb_dout_ecc_bank_0[62],wb_dout_ecc_bank_0[61],wb_dout_ecc_bank_0[60],wb_dout_ecc_bank_0[59],wb_dout_ecc_bank_0[58],wb_dout_ecc_bank_0[57]}; // @[el2_lib.scala 379:41] wire _T_556 = ^_T_555; // @[el2_lib.scala 379:48] wire _T_557 = wb_dout_ecc_bank_0[70] ^ _T_556; // @[el2_lib.scala 379:36] @@ -377,22 +647,22 @@ module el2_ifu_ic_mem( wire ic_parerr_bank_1_2 = _T_1246 ^ wb_dout_ecc_bank_1[66]; // @[el2_lib.scala 200:27] wire _T_1250 = ^wb_dout_ecc_bank_1[63:48]; // @[el2_lib.scala 200:14] wire ic_parerr_bank_1_3 = _T_1250 ^ wb_dout_ecc_bank_1[67]; // @[el2_lib.scala 200:27] - wire _T_1252 = ic_parerr_bank_0_0 | ic_parerr_bank_0_1; // @[el2_ifu_ic_mem.scala 119:49] - wire _T_1253 = _T_1252 | ic_parerr_bank_0_2; // @[el2_ifu_ic_mem.scala 119:49] - wire _T_1254 = _T_1253 | ic_parerr_bank_0_3; // @[el2_ifu_ic_mem.scala 119:49] - wire _T_1255 = _T_1254 & bank_check_en_0; // @[el2_ifu_ic_mem.scala 119:53] - wire _T_1256 = ic_parerr_bank_1_0 | ic_parerr_bank_1_1; // @[el2_ifu_ic_mem.scala 119:99] - wire _T_1257 = _T_1256 | ic_parerr_bank_1_2; // @[el2_ifu_ic_mem.scala 119:99] - wire _T_1258 = _T_1257 | ic_parerr_bank_1_3; // @[el2_ifu_ic_mem.scala 119:99] - wire _T_1259 = _T_1258 & bank_check_en_0; // @[el2_ifu_ic_mem.scala 119:103] + wire _T_1252 = ic_parerr_bank_0_0 | ic_parerr_bank_0_1; // @[el2_ifu_ic_mem.scala 272:49] + wire _T_1253 = _T_1252 | ic_parerr_bank_0_2; // @[el2_ifu_ic_mem.scala 272:49] + wire _T_1254 = _T_1253 | ic_parerr_bank_0_3; // @[el2_ifu_ic_mem.scala 272:49] + wire _T_1255 = _T_1254 & bank_check_en_0; // @[el2_ifu_ic_mem.scala 272:53] + wire _T_1256 = ic_parerr_bank_1_0 | ic_parerr_bank_1_1; // @[el2_ifu_ic_mem.scala 272:99] + wire _T_1257 = _T_1256 | ic_parerr_bank_1_2; // @[el2_ifu_ic_mem.scala 272:99] + wire _T_1258 = _T_1257 | ic_parerr_bank_1_3; // @[el2_ifu_ic_mem.scala 272:99] + wire _T_1259 = _T_1258 & bank_check_en_0; // @[el2_ifu_ic_mem.scala 272:103] assign data_mem_0_0__T_145_addr = _T_122 ? ic_rw_addr_q[11:3] : _T_127; - assign data_mem_0_0__T_145_data = data_mem_0_0[data_mem_0_0__T_145_addr]; // @[el2_ifu_ic_mem.scala 82:21] + assign data_mem_0_0__T_145_data = data_mem_0_0[data_mem_0_0__T_145_addr]; // @[el2_ifu_ic_mem.scala 235:21] assign data_mem_0_0__T_158_addr = ic_rw_addr_q[11:3]; - assign data_mem_0_0__T_158_data = data_mem_0_0[data_mem_0_0__T_158_addr]; // @[el2_ifu_ic_mem.scala 82:21] + assign data_mem_0_0__T_158_data = data_mem_0_0[data_mem_0_0__T_158_addr]; // @[el2_ifu_ic_mem.scala 235:21] assign data_mem_0_0__T_171_addr = _T_122 ? ic_rw_addr_q[11:3] : _T_127; - assign data_mem_0_0__T_171_data = data_mem_0_0[data_mem_0_0__T_171_addr]; // @[el2_ifu_ic_mem.scala 82:21] + assign data_mem_0_0__T_171_data = data_mem_0_0[data_mem_0_0__T_171_addr]; // @[el2_ifu_ic_mem.scala 235:21] assign data_mem_0_0__T_184_addr = ic_rw_addr_q[11:3]; - assign data_mem_0_0__T_184_data = data_mem_0_0[data_mem_0_0__T_184_addr]; // @[el2_ifu_ic_mem.scala 82:21] + assign data_mem_0_0__T_184_data = data_mem_0_0[data_mem_0_0__T_184_addr]; // @[el2_ifu_ic_mem.scala 235:21] assign data_mem_0_0__T_139_data = _T_28 ? io_ic_debug_wr_data : io_ic_wr_data_0; assign data_mem_0_0__T_139_addr = _T_122 ? ic_rw_addr_q[11:3] : _T_127; assign data_mem_0_0__T_139_mask = 1'h1; @@ -410,13 +680,13 @@ module el2_ifu_ic_mem( assign data_mem_0_0__T_178_mask = 1'h0; assign data_mem_0_0__T_178_en = ic_b_sb_wren_1[1] & ic_bank_way_clken_1[1]; assign data_mem_0_1__T_145_addr = _T_122 ? ic_rw_addr_q[11:3] : _T_127; - assign data_mem_0_1__T_145_data = data_mem_0_1[data_mem_0_1__T_145_addr]; // @[el2_ifu_ic_mem.scala 82:21] + assign data_mem_0_1__T_145_data = data_mem_0_1[data_mem_0_1__T_145_addr]; // @[el2_ifu_ic_mem.scala 235:21] assign data_mem_0_1__T_158_addr = ic_rw_addr_q[11:3]; - assign data_mem_0_1__T_158_data = data_mem_0_1[data_mem_0_1__T_158_addr]; // @[el2_ifu_ic_mem.scala 82:21] + assign data_mem_0_1__T_158_data = data_mem_0_1[data_mem_0_1__T_158_addr]; // @[el2_ifu_ic_mem.scala 235:21] assign data_mem_0_1__T_171_addr = _T_122 ? ic_rw_addr_q[11:3] : _T_127; - assign data_mem_0_1__T_171_data = data_mem_0_1[data_mem_0_1__T_171_addr]; // @[el2_ifu_ic_mem.scala 82:21] + assign data_mem_0_1__T_171_data = data_mem_0_1[data_mem_0_1__T_171_addr]; // @[el2_ifu_ic_mem.scala 235:21] assign data_mem_0_1__T_184_addr = ic_rw_addr_q[11:3]; - assign data_mem_0_1__T_184_data = data_mem_0_1[data_mem_0_1__T_184_addr]; // @[el2_ifu_ic_mem.scala 82:21] + assign data_mem_0_1__T_184_data = data_mem_0_1[data_mem_0_1__T_184_addr]; // @[el2_ifu_ic_mem.scala 235:21] assign data_mem_0_1__T_139_data = 71'h0; assign data_mem_0_1__T_139_addr = _T_122 ? ic_rw_addr_q[11:3] : _T_127; assign data_mem_0_1__T_139_mask = 1'h0; @@ -434,13 +704,13 @@ module el2_ifu_ic_mem( assign data_mem_0_1__T_178_mask = 1'h0; assign data_mem_0_1__T_178_en = ic_b_sb_wren_1[1] & ic_bank_way_clken_1[1]; assign data_mem_1_0__T_145_addr = _T_122 ? ic_rw_addr_q[11:3] : _T_127; - assign data_mem_1_0__T_145_data = data_mem_1_0[data_mem_1_0__T_145_addr]; // @[el2_ifu_ic_mem.scala 82:21] + assign data_mem_1_0__T_145_data = data_mem_1_0[data_mem_1_0__T_145_addr]; // @[el2_ifu_ic_mem.scala 235:21] assign data_mem_1_0__T_158_addr = ic_rw_addr_q[11:3]; - assign data_mem_1_0__T_158_data = data_mem_1_0[data_mem_1_0__T_158_addr]; // @[el2_ifu_ic_mem.scala 82:21] + assign data_mem_1_0__T_158_data = data_mem_1_0[data_mem_1_0__T_158_addr]; // @[el2_ifu_ic_mem.scala 235:21] assign data_mem_1_0__T_171_addr = _T_122 ? ic_rw_addr_q[11:3] : _T_127; - assign data_mem_1_0__T_171_data = data_mem_1_0[data_mem_1_0__T_171_addr]; // @[el2_ifu_ic_mem.scala 82:21] + assign data_mem_1_0__T_171_data = data_mem_1_0[data_mem_1_0__T_171_addr]; // @[el2_ifu_ic_mem.scala 235:21] assign data_mem_1_0__T_184_addr = ic_rw_addr_q[11:3]; - assign data_mem_1_0__T_184_data = data_mem_1_0[data_mem_1_0__T_184_addr]; // @[el2_ifu_ic_mem.scala 82:21] + assign data_mem_1_0__T_184_data = data_mem_1_0[data_mem_1_0__T_184_addr]; // @[el2_ifu_ic_mem.scala 235:21] assign data_mem_1_0__T_139_data = 71'h0; assign data_mem_1_0__T_139_addr = _T_122 ? ic_rw_addr_q[11:3] : _T_127; assign data_mem_1_0__T_139_mask = 1'h0; @@ -458,13 +728,13 @@ module el2_ifu_ic_mem( assign data_mem_1_0__T_178_mask = 1'h0; assign data_mem_1_0__T_178_en = ic_b_sb_wren_1[1] & ic_bank_way_clken_1[1]; assign data_mem_1_1__T_145_addr = _T_122 ? ic_rw_addr_q[11:3] : _T_127; - assign data_mem_1_1__T_145_data = data_mem_1_1[data_mem_1_1__T_145_addr]; // @[el2_ifu_ic_mem.scala 82:21] + assign data_mem_1_1__T_145_data = data_mem_1_1[data_mem_1_1__T_145_addr]; // @[el2_ifu_ic_mem.scala 235:21] assign data_mem_1_1__T_158_addr = ic_rw_addr_q[11:3]; - assign data_mem_1_1__T_158_data = data_mem_1_1[data_mem_1_1__T_158_addr]; // @[el2_ifu_ic_mem.scala 82:21] + assign data_mem_1_1__T_158_data = data_mem_1_1[data_mem_1_1__T_158_addr]; // @[el2_ifu_ic_mem.scala 235:21] assign data_mem_1_1__T_171_addr = _T_122 ? ic_rw_addr_q[11:3] : _T_127; - assign data_mem_1_1__T_171_data = data_mem_1_1[data_mem_1_1__T_171_addr]; // @[el2_ifu_ic_mem.scala 82:21] + assign data_mem_1_1__T_171_data = data_mem_1_1[data_mem_1_1__T_171_addr]; // @[el2_ifu_ic_mem.scala 235:21] assign data_mem_1_1__T_184_addr = ic_rw_addr_q[11:3]; - assign data_mem_1_1__T_184_data = data_mem_1_1[data_mem_1_1__T_184_addr]; // @[el2_ifu_ic_mem.scala 82:21] + assign data_mem_1_1__T_184_data = data_mem_1_1[data_mem_1_1__T_184_addr]; // @[el2_ifu_ic_mem.scala 235:21] assign data_mem_1_1__T_139_data = 71'h0; assign data_mem_1_1__T_139_addr = _T_122 ? ic_rw_addr_q[11:3] : _T_127; assign data_mem_1_1__T_139_mask = 1'h0; @@ -481,13 +751,10 @@ module el2_ifu_ic_mem( assign data_mem_1_1__T_178_addr = ic_rw_addr_q[11:3]; assign data_mem_1_1__T_178_mask = 1'h1; assign data_mem_1_1__T_178_en = ic_b_sb_wren_1[1] & ic_bank_way_clken_1[1]; - assign io_ic_rd_data = _T_300 | _T_301; // @[el2_ifu_ic_mem.scala 40:17 el2_ifu_ic_mem.scala 107:17] - assign io_ic_debug_rd_data = _T_310 | _T_311; // @[el2_ifu_ic_mem.scala 39:23 el2_ifu_ic_mem.scala 108:23] - assign io_ictag_debug_rd_data = 26'h0; // @[el2_ifu_ic_mem.scala 38:26] - assign io_ic_eccerr = {_T_1218,_T_776}; // @[el2_ifu_ic_mem.scala 37:16 el2_ifu_ic_mem.scala 115:16] - assign io_ic_parerr = {_T_1255,_T_1259}; // @[el2_ifu_ic_mem.scala 36:16 el2_ifu_ic_mem.scala 119:16] - assign io_ic_rd_hit = 2'h0; // @[el2_ifu_ic_mem.scala 35:16] - assign io_ic_tag_perr = 1'h0; // @[el2_ifu_ic_mem.scala 34:18] + assign io_ic_rd_data = _T_300 | _T_301; // @[el2_ifu_ic_mem.scala 260:17] + assign io_ic_debug_rd_data = _T_310 | _T_311; // @[el2_ifu_ic_mem.scala 261:23] + assign io_ic_parerr = {_T_1255,_T_1259}; // @[el2_ifu_ic_mem.scala 272:16] + assign io_ic_eccerr = {_T_1218,_T_776}; // @[el2_ifu_ic_mem.scala 268:16] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif @@ -554,52 +821,52 @@ end // initial `endif // SYNTHESIS always @(posedge clock) begin if(data_mem_0_0__T_139_en & data_mem_0_0__T_139_mask) begin - data_mem_0_0[data_mem_0_0__T_139_addr] <= data_mem_0_0__T_139_data; // @[el2_ifu_ic_mem.scala 82:21] + data_mem_0_0[data_mem_0_0__T_139_addr] <= data_mem_0_0__T_139_data; // @[el2_ifu_ic_mem.scala 235:21] end if(data_mem_0_0__T_152_en & data_mem_0_0__T_152_mask) begin - data_mem_0_0[data_mem_0_0__T_152_addr] <= data_mem_0_0__T_152_data; // @[el2_ifu_ic_mem.scala 82:21] + data_mem_0_0[data_mem_0_0__T_152_addr] <= data_mem_0_0__T_152_data; // @[el2_ifu_ic_mem.scala 235:21] end if(data_mem_0_0__T_165_en & data_mem_0_0__T_165_mask) begin - data_mem_0_0[data_mem_0_0__T_165_addr] <= data_mem_0_0__T_165_data; // @[el2_ifu_ic_mem.scala 82:21] + data_mem_0_0[data_mem_0_0__T_165_addr] <= data_mem_0_0__T_165_data; // @[el2_ifu_ic_mem.scala 235:21] end if(data_mem_0_0__T_178_en & data_mem_0_0__T_178_mask) begin - data_mem_0_0[data_mem_0_0__T_178_addr] <= data_mem_0_0__T_178_data; // @[el2_ifu_ic_mem.scala 82:21] + data_mem_0_0[data_mem_0_0__T_178_addr] <= data_mem_0_0__T_178_data; // @[el2_ifu_ic_mem.scala 235:21] end if(data_mem_0_1__T_139_en & data_mem_0_1__T_139_mask) begin - data_mem_0_1[data_mem_0_1__T_139_addr] <= data_mem_0_1__T_139_data; // @[el2_ifu_ic_mem.scala 82:21] + data_mem_0_1[data_mem_0_1__T_139_addr] <= data_mem_0_1__T_139_data; // @[el2_ifu_ic_mem.scala 235:21] end if(data_mem_0_1__T_152_en & data_mem_0_1__T_152_mask) begin - data_mem_0_1[data_mem_0_1__T_152_addr] <= data_mem_0_1__T_152_data; // @[el2_ifu_ic_mem.scala 82:21] + data_mem_0_1[data_mem_0_1__T_152_addr] <= data_mem_0_1__T_152_data; // @[el2_ifu_ic_mem.scala 235:21] end if(data_mem_0_1__T_165_en & data_mem_0_1__T_165_mask) begin - data_mem_0_1[data_mem_0_1__T_165_addr] <= data_mem_0_1__T_165_data; // @[el2_ifu_ic_mem.scala 82:21] + data_mem_0_1[data_mem_0_1__T_165_addr] <= data_mem_0_1__T_165_data; // @[el2_ifu_ic_mem.scala 235:21] end if(data_mem_0_1__T_178_en & data_mem_0_1__T_178_mask) begin - data_mem_0_1[data_mem_0_1__T_178_addr] <= data_mem_0_1__T_178_data; // @[el2_ifu_ic_mem.scala 82:21] + data_mem_0_1[data_mem_0_1__T_178_addr] <= data_mem_0_1__T_178_data; // @[el2_ifu_ic_mem.scala 235:21] end if(data_mem_1_0__T_139_en & data_mem_1_0__T_139_mask) begin - data_mem_1_0[data_mem_1_0__T_139_addr] <= data_mem_1_0__T_139_data; // @[el2_ifu_ic_mem.scala 82:21] + data_mem_1_0[data_mem_1_0__T_139_addr] <= data_mem_1_0__T_139_data; // @[el2_ifu_ic_mem.scala 235:21] end if(data_mem_1_0__T_152_en & data_mem_1_0__T_152_mask) begin - data_mem_1_0[data_mem_1_0__T_152_addr] <= data_mem_1_0__T_152_data; // @[el2_ifu_ic_mem.scala 82:21] + data_mem_1_0[data_mem_1_0__T_152_addr] <= data_mem_1_0__T_152_data; // @[el2_ifu_ic_mem.scala 235:21] end if(data_mem_1_0__T_165_en & data_mem_1_0__T_165_mask) begin - data_mem_1_0[data_mem_1_0__T_165_addr] <= data_mem_1_0__T_165_data; // @[el2_ifu_ic_mem.scala 82:21] + data_mem_1_0[data_mem_1_0__T_165_addr] <= data_mem_1_0__T_165_data; // @[el2_ifu_ic_mem.scala 235:21] end if(data_mem_1_0__T_178_en & data_mem_1_0__T_178_mask) begin - data_mem_1_0[data_mem_1_0__T_178_addr] <= data_mem_1_0__T_178_data; // @[el2_ifu_ic_mem.scala 82:21] + data_mem_1_0[data_mem_1_0__T_178_addr] <= data_mem_1_0__T_178_data; // @[el2_ifu_ic_mem.scala 235:21] end if(data_mem_1_1__T_139_en & data_mem_1_1__T_139_mask) begin - data_mem_1_1[data_mem_1_1__T_139_addr] <= data_mem_1_1__T_139_data; // @[el2_ifu_ic_mem.scala 82:21] + data_mem_1_1[data_mem_1_1__T_139_addr] <= data_mem_1_1__T_139_data; // @[el2_ifu_ic_mem.scala 235:21] end if(data_mem_1_1__T_152_en & data_mem_1_1__T_152_mask) begin - data_mem_1_1[data_mem_1_1__T_152_addr] <= data_mem_1_1__T_152_data; // @[el2_ifu_ic_mem.scala 82:21] + data_mem_1_1[data_mem_1_1__T_152_addr] <= data_mem_1_1__T_152_data; // @[el2_ifu_ic_mem.scala 235:21] end if(data_mem_1_1__T_165_en & data_mem_1_1__T_165_mask) begin - data_mem_1_1[data_mem_1_1__T_165_addr] <= data_mem_1_1__T_165_data; // @[el2_ifu_ic_mem.scala 82:21] + data_mem_1_1[data_mem_1_1__T_165_addr] <= data_mem_1_1__T_165_data; // @[el2_ifu_ic_mem.scala 235:21] end if(data_mem_1_1__T_178_en & data_mem_1_1__T_178_mask) begin - data_mem_1_1[data_mem_1_1__T_178_addr] <= data_mem_1_1__T_178_data; // @[el2_ifu_ic_mem.scala 82:21] + data_mem_1_1[data_mem_1_1__T_178_addr] <= data_mem_1_1__T_178_data; // @[el2_ifu_ic_mem.scala 235:21] end if (reset) begin ic_b_rden_ff <= 2'h0; @@ -623,3 +890,150 @@ end // initial end end endmodule +module el2_ifu_ic_mem( + input clock, + input reset, + input io_scan_mode, + input io_clk_override, + input io_dec_tlu_core_ecc_disable, + input [30:0] io_ic_rw_addr, + input [1:0] io_ic_wr_en, + input io_ic_rd_en, + input [8:0] io_ic_debug_addr, + input io_ic_debug_rd_en, + input io_ic_debug_wr_en, + input io_ic_debug_tag_array, + input [1:0] io_ic_debug_way, + input [63:0] io_ic_premux_data, + input io_ic_sel_premux_data, + input [1:0] io_ic_tag_valid, + input [70:0] io_ic_debug_wr_data, + input [70:0] io_ic_wr_data_0, + input [70:0] io_ic_wr_data_1, + output [63:0] io_ic_rd_data, + output [70:0] io_ic_debug_rd_data, + output [25:0] io_ictag_debug_rd_data, + output [1:0] io_ic_eccerr, + output [1:0] io_ic_parerr, + output [1:0] io_ic_rd_hit, + output io_ic_tag_perr +); + wire ic_tag_inst_clock; // @[el2_ifu_ic_mem.scala 41:27] + wire ic_tag_inst_reset; // @[el2_ifu_ic_mem.scala 41:27] + wire ic_tag_inst_io_clk_override; // @[el2_ifu_ic_mem.scala 41:27] + wire ic_tag_inst_io_dec_tlu_core_ecc_disable; // @[el2_ifu_ic_mem.scala 41:27] + wire [28:0] ic_tag_inst_io_ic_rw_addr; // @[el2_ifu_ic_mem.scala 41:27] + wire [1:0] ic_tag_inst_io_ic_wr_en; // @[el2_ifu_ic_mem.scala 41:27] + wire [1:0] ic_tag_inst_io_ic_tag_valid; // @[el2_ifu_ic_mem.scala 41:27] + wire ic_tag_inst_io_ic_rd_en; // @[el2_ifu_ic_mem.scala 41:27] + wire [9:0] ic_tag_inst_io_ic_debug_addr; // @[el2_ifu_ic_mem.scala 41:27] + wire ic_tag_inst_io_ic_debug_rd_en; // @[el2_ifu_ic_mem.scala 41:27] + wire ic_tag_inst_io_ic_debug_wr_en; // @[el2_ifu_ic_mem.scala 41:27] + wire ic_tag_inst_io_ic_debug_tag_array; // @[el2_ifu_ic_mem.scala 41:27] + wire [1:0] ic_tag_inst_io_ic_debug_way; // @[el2_ifu_ic_mem.scala 41:27] + wire [25:0] ic_tag_inst_io_ictag_debug_rd_data; // @[el2_ifu_ic_mem.scala 41:27] + wire [70:0] ic_tag_inst_io_ic_debug_wr_data; // @[el2_ifu_ic_mem.scala 41:27] + wire [1:0] ic_tag_inst_io_ic_rd_hit; // @[el2_ifu_ic_mem.scala 41:27] + wire ic_tag_inst_io_ic_tag_perr; // @[el2_ifu_ic_mem.scala 41:27] + wire ic_data_inst_clock; // @[el2_ifu_ic_mem.scala 59:28] + wire ic_data_inst_reset; // @[el2_ifu_ic_mem.scala 59:28] + wire ic_data_inst_io_clk_override; // @[el2_ifu_ic_mem.scala 59:28] + wire [11:0] ic_data_inst_io_ic_rw_addr; // @[el2_ifu_ic_mem.scala 59:28] + wire [1:0] ic_data_inst_io_ic_wr_en; // @[el2_ifu_ic_mem.scala 59:28] + wire ic_data_inst_io_ic_rd_en; // @[el2_ifu_ic_mem.scala 59:28] + wire [70:0] ic_data_inst_io_ic_wr_data_0; // @[el2_ifu_ic_mem.scala 59:28] + wire [70:0] ic_data_inst_io_ic_wr_data_1; // @[el2_ifu_ic_mem.scala 59:28] + wire [63:0] ic_data_inst_io_ic_rd_data; // @[el2_ifu_ic_mem.scala 59:28] + wire [70:0] ic_data_inst_io_ic_debug_wr_data; // @[el2_ifu_ic_mem.scala 59:28] + wire [70:0] ic_data_inst_io_ic_debug_rd_data; // @[el2_ifu_ic_mem.scala 59:28] + wire [1:0] ic_data_inst_io_ic_parerr; // @[el2_ifu_ic_mem.scala 59:28] + wire [1:0] ic_data_inst_io_ic_eccerr; // @[el2_ifu_ic_mem.scala 59:28] + wire [8:0] ic_data_inst_io_ic_debug_addr; // @[el2_ifu_ic_mem.scala 59:28] + wire ic_data_inst_io_ic_debug_rd_en; // @[el2_ifu_ic_mem.scala 59:28] + wire ic_data_inst_io_ic_debug_wr_en; // @[el2_ifu_ic_mem.scala 59:28] + wire ic_data_inst_io_ic_debug_tag_array; // @[el2_ifu_ic_mem.scala 59:28] + wire [1:0] ic_data_inst_io_ic_debug_way; // @[el2_ifu_ic_mem.scala 59:28] + wire [63:0] ic_data_inst_io_ic_premux_data; // @[el2_ifu_ic_mem.scala 59:28] + wire ic_data_inst_io_ic_sel_premux_data; // @[el2_ifu_ic_mem.scala 59:28] + wire [1:0] ic_data_inst_io_ic_rd_hit; // @[el2_ifu_ic_mem.scala 59:28] + EL2_IC_TAG ic_tag_inst ( // @[el2_ifu_ic_mem.scala 41:27] + .clock(ic_tag_inst_clock), + .reset(ic_tag_inst_reset), + .io_clk_override(ic_tag_inst_io_clk_override), + .io_dec_tlu_core_ecc_disable(ic_tag_inst_io_dec_tlu_core_ecc_disable), + .io_ic_rw_addr(ic_tag_inst_io_ic_rw_addr), + .io_ic_wr_en(ic_tag_inst_io_ic_wr_en), + .io_ic_tag_valid(ic_tag_inst_io_ic_tag_valid), + .io_ic_rd_en(ic_tag_inst_io_ic_rd_en), + .io_ic_debug_addr(ic_tag_inst_io_ic_debug_addr), + .io_ic_debug_rd_en(ic_tag_inst_io_ic_debug_rd_en), + .io_ic_debug_wr_en(ic_tag_inst_io_ic_debug_wr_en), + .io_ic_debug_tag_array(ic_tag_inst_io_ic_debug_tag_array), + .io_ic_debug_way(ic_tag_inst_io_ic_debug_way), + .io_ictag_debug_rd_data(ic_tag_inst_io_ictag_debug_rd_data), + .io_ic_debug_wr_data(ic_tag_inst_io_ic_debug_wr_data), + .io_ic_rd_hit(ic_tag_inst_io_ic_rd_hit), + .io_ic_tag_perr(ic_tag_inst_io_ic_tag_perr) + ); + EL2_IC_DATA ic_data_inst ( // @[el2_ifu_ic_mem.scala 59:28] + .clock(ic_data_inst_clock), + .reset(ic_data_inst_reset), + .io_clk_override(ic_data_inst_io_clk_override), + .io_ic_rw_addr(ic_data_inst_io_ic_rw_addr), + .io_ic_wr_en(ic_data_inst_io_ic_wr_en), + .io_ic_rd_en(ic_data_inst_io_ic_rd_en), + .io_ic_wr_data_0(ic_data_inst_io_ic_wr_data_0), + .io_ic_wr_data_1(ic_data_inst_io_ic_wr_data_1), + .io_ic_rd_data(ic_data_inst_io_ic_rd_data), + .io_ic_debug_wr_data(ic_data_inst_io_ic_debug_wr_data), + .io_ic_debug_rd_data(ic_data_inst_io_ic_debug_rd_data), + .io_ic_parerr(ic_data_inst_io_ic_parerr), + .io_ic_eccerr(ic_data_inst_io_ic_eccerr), + .io_ic_debug_addr(ic_data_inst_io_ic_debug_addr), + .io_ic_debug_rd_en(ic_data_inst_io_ic_debug_rd_en), + .io_ic_debug_wr_en(ic_data_inst_io_ic_debug_wr_en), + .io_ic_debug_tag_array(ic_data_inst_io_ic_debug_tag_array), + .io_ic_debug_way(ic_data_inst_io_ic_debug_way), + .io_ic_premux_data(ic_data_inst_io_ic_premux_data), + .io_ic_sel_premux_data(ic_data_inst_io_ic_sel_premux_data), + .io_ic_rd_hit(ic_data_inst_io_ic_rd_hit) + ); + assign io_ic_rd_data = ic_data_inst_io_ic_rd_data; // @[el2_ifu_ic_mem.scala 40:17 el2_ifu_ic_mem.scala 67:17] + assign io_ic_debug_rd_data = ic_data_inst_io_ic_debug_rd_data; // @[el2_ifu_ic_mem.scala 39:23 el2_ifu_ic_mem.scala 69:23] + assign io_ictag_debug_rd_data = ic_tag_inst_io_ictag_debug_rd_data; // @[el2_ifu_ic_mem.scala 38:26 el2_ifu_ic_mem.scala 54:26] + assign io_ic_eccerr = ic_data_inst_io_ic_eccerr; // @[el2_ifu_ic_mem.scala 37:16 el2_ifu_ic_mem.scala 71:16] + assign io_ic_parerr = ic_data_inst_io_ic_parerr; // @[el2_ifu_ic_mem.scala 36:16 el2_ifu_ic_mem.scala 70:16] + assign io_ic_rd_hit = ic_tag_inst_io_ic_rd_hit; // @[el2_ifu_ic_mem.scala 35:16 el2_ifu_ic_mem.scala 56:16] + assign io_ic_tag_perr = ic_tag_inst_io_ic_tag_perr; // @[el2_ifu_ic_mem.scala 34:18 el2_ifu_ic_mem.scala 57:18] + assign ic_tag_inst_clock = clock; + assign ic_tag_inst_reset = reset; + assign ic_tag_inst_io_clk_override = io_clk_override; // @[el2_ifu_ic_mem.scala 45:31] + assign ic_tag_inst_io_dec_tlu_core_ecc_disable = io_dec_tlu_core_ecc_disable; // @[el2_ifu_ic_mem.scala 44:43] + assign ic_tag_inst_io_ic_rw_addr = io_ic_rw_addr[28:0]; // @[el2_ifu_ic_mem.scala 46:29] + assign ic_tag_inst_io_ic_wr_en = io_ic_wr_en; // @[el2_ifu_ic_mem.scala 47:27] + assign ic_tag_inst_io_ic_tag_valid = io_ic_tag_valid; // @[el2_ifu_ic_mem.scala 43:31] + assign ic_tag_inst_io_ic_rd_en = io_ic_rd_en; // @[el2_ifu_ic_mem.scala 48:27] + assign ic_tag_inst_io_ic_debug_addr = {{1'd0}, io_ic_debug_addr}; // @[el2_ifu_ic_mem.scala 49:32] + assign ic_tag_inst_io_ic_debug_rd_en = io_ic_debug_rd_en; // @[el2_ifu_ic_mem.scala 50:33] + assign ic_tag_inst_io_ic_debug_wr_en = io_ic_debug_wr_en; // @[el2_ifu_ic_mem.scala 51:33] + assign ic_tag_inst_io_ic_debug_tag_array = io_ic_debug_tag_array; // @[el2_ifu_ic_mem.scala 52:37] + assign ic_tag_inst_io_ic_debug_way = io_ic_debug_way; // @[el2_ifu_ic_mem.scala 53:31] + assign ic_tag_inst_io_ic_debug_wr_data = io_ic_debug_wr_data; // @[el2_ifu_ic_mem.scala 55:35] + assign ic_data_inst_clock = clock; + assign ic_data_inst_reset = reset; + assign ic_data_inst_io_clk_override = io_clk_override; // @[el2_ifu_ic_mem.scala 60:32] + assign ic_data_inst_io_ic_rw_addr = io_ic_rw_addr[11:0]; // @[el2_ifu_ic_mem.scala 62:30] + assign ic_data_inst_io_ic_wr_en = io_ic_wr_en; // @[el2_ifu_ic_mem.scala 63:28] + assign ic_data_inst_io_ic_rd_en = io_ic_rd_en; // @[el2_ifu_ic_mem.scala 64:28] + assign ic_data_inst_io_ic_wr_data_0 = io_ic_wr_data_0; // @[el2_ifu_ic_mem.scala 66:30] + assign ic_data_inst_io_ic_wr_data_1 = io_ic_wr_data_1; // @[el2_ifu_ic_mem.scala 66:30] + assign ic_data_inst_io_ic_debug_wr_data = io_ic_debug_wr_data; // @[el2_ifu_ic_mem.scala 68:36] + assign ic_data_inst_io_ic_debug_addr = io_ic_debug_addr; // @[el2_ifu_ic_mem.scala 72:33] + assign ic_data_inst_io_ic_debug_rd_en = io_ic_debug_rd_en; // @[el2_ifu_ic_mem.scala 73:34] + assign ic_data_inst_io_ic_debug_wr_en = io_ic_debug_wr_en; // @[el2_ifu_ic_mem.scala 74:34] + assign ic_data_inst_io_ic_debug_tag_array = io_ic_debug_tag_array; // @[el2_ifu_ic_mem.scala 75:38] + assign ic_data_inst_io_ic_debug_way = io_ic_debug_way; // @[el2_ifu_ic_mem.scala 76:32] + assign ic_data_inst_io_ic_premux_data = io_ic_premux_data; // @[el2_ifu_ic_mem.scala 77:34] + assign ic_data_inst_io_ic_sel_premux_data = io_ic_sel_premux_data; // @[el2_ifu_ic_mem.scala 78:38] + assign ic_data_inst_io_ic_rd_hit = io_ic_rd_hit; // @[el2_ifu_ic_mem.scala 80:29] +endmodule diff --git a/src/main/scala/ifu/el2_ifu_ic_mem.scala b/src/main/scala/ifu/el2_ifu_ic_mem.scala index 03c45846..e9457141 100644 --- a/src/main/scala/ifu/el2_ifu_ic_mem.scala +++ b/src/main/scala/ifu/el2_ifu_ic_mem.scala @@ -3,7 +3,7 @@ import lib._ import chisel3.{util, _} import chisel3.util._ -class el2_ifu_ic_mem extends Module with el2_lib { +class el2_ifu_ic_mem extends Module with param{ val io = IO(new Bundle{ val scan_mode = Input(Bool()) val clk_override = Input(Bool()) @@ -38,6 +38,159 @@ class el2_ifu_ic_mem extends Module with el2_lib { io.ictag_debug_rd_data := 0.U io.ic_debug_rd_data := 0.U io.ic_rd_data := 0.U + val ic_tag_inst = Module(new EL2_IC_TAG()) + //ic_tag_inst.io <> io + ic_tag_inst.io.ic_tag_valid := io.ic_tag_valid + ic_tag_inst.io.dec_tlu_core_ecc_disable := io.dec_tlu_core_ecc_disable + ic_tag_inst.io.clk_override := io.clk_override + ic_tag_inst.io.ic_rw_addr := io.ic_rw_addr + ic_tag_inst.io.ic_wr_en := io.ic_wr_en + ic_tag_inst.io.ic_rd_en := io.ic_rd_en + ic_tag_inst.io.ic_debug_addr := io.ic_debug_addr + ic_tag_inst.io.ic_debug_rd_en := io.ic_debug_rd_en + ic_tag_inst.io.ic_debug_wr_en := io.ic_debug_wr_en + ic_tag_inst.io.ic_debug_tag_array := io.ic_debug_tag_array + ic_tag_inst.io.ic_debug_way := io.ic_debug_way + io.ictag_debug_rd_data := ic_tag_inst.io.ictag_debug_rd_data // Output + ic_tag_inst.io.ic_debug_wr_data := io.ic_debug_wr_data + io.ic_rd_hit := ic_tag_inst.io.ic_rd_hit // Output + io.ic_tag_perr := ic_tag_inst.io.ic_tag_perr // Output + ic_tag_inst.io.scan_mode := io.scan_mode + val ic_data_inst = Module(new EL2_IC_DATA()) + ic_data_inst.io.clk_override := io.clk_override + + ic_data_inst.io.ic_rw_addr :=io.ic_rw_addr + ic_data_inst.io.ic_wr_en := io.ic_wr_en + ic_data_inst.io.ic_rd_en := io.ic_rd_en + + ic_data_inst.io.ic_wr_data := io.ic_wr_data + io.ic_rd_data := ic_data_inst.io.ic_rd_data + ic_data_inst.io.ic_debug_wr_data := io.ic_debug_wr_data + io.ic_debug_rd_data := ic_data_inst.io.ic_debug_rd_data + io.ic_parerr := ic_data_inst.io.ic_parerr + io.ic_eccerr := ic_data_inst.io.ic_eccerr + ic_data_inst.io.ic_debug_addr := io.ic_debug_addr + ic_data_inst.io.ic_debug_rd_en := io.ic_debug_rd_en + ic_data_inst.io.ic_debug_wr_en := io.ic_debug_wr_en + ic_data_inst.io.ic_debug_tag_array := io.ic_debug_tag_array + ic_data_inst.io.ic_debug_way := io.ic_debug_way + ic_data_inst.io.ic_premux_data := io.ic_premux_data + ic_data_inst.io.ic_sel_premux_data := io.ic_sel_premux_data + + ic_data_inst.io.ic_rd_hit :=io.ic_rd_hit + ic_data_inst.io.scan_mode := io.scan_mode +} + +/////////// ICACHE TAG +class EL2_IC_TAG extends Module with el2_lib with param { + val io = IO(new Bundle{ + val scan_mode = Input(Bool()) + val clk_override = Input(Bool()) + val dec_tlu_core_ecc_disable = Input(Bool()) + val ic_rw_addr = Input(UInt(29.W)) // 32:3 + val ic_wr_en = Input(UInt(ICACHE_NUM_WAYS.W)) + val ic_tag_valid = Input(UInt(ICACHE_NUM_WAYS.W)) + val ic_rd_en = Input(Bool()) + val ic_debug_addr = Input(UInt((ICACHE_INDEX_HI-2).W)) // 12-2 = 10-bit value + val ic_debug_rd_en = Input(Bool()) + val ic_debug_wr_en = Input(Bool()) + val ic_debug_tag_array = Input(Bool()) + val ic_debug_way = Input(UInt(ICACHE_NUM_WAYS.W)) + val ictag_debug_rd_data = Output(UInt(26.W)) + val ic_debug_wr_data = Input(UInt(71.W)) + val ic_rd_hit = Output(UInt(ICACHE_NUM_WAYS.W)) + val ic_tag_perr = Output(Bool()) + }) + io.ictag_debug_rd_data := 0.U + io.ic_rd_hit := 0.U + io.ic_tag_perr := 0.U + val ic_debug_wr_way_en = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U) + val ic_debug_rd_way_en = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U) + + val ic_tag_wren = io.ic_wr_en & Fill(ICACHE_NUM_WAYS, io.ic_rw_addr(ICACHE_BEAT_ADDR_HI-3,1)=== Fill(ICACHE_NUM_WAYS-1, 1.U)) + val ic_tag_clken = Fill(ICACHE_NUM_WAYS, io.ic_rd_en|io.clk_override) | io.ic_wr_en | ic_debug_wr_way_en | ic_debug_rd_way_en + + val ic_rd_en_ff = RegNext(io.ic_rd_en, 0.U) + val ic_rw_addr_ff = RegNext(io.ic_rw_addr(31-ICACHE_TAG_LO, 0), 0.U) + + val PAD_BITS = 21 - (32 - ICACHE_TAG_LO) + + ic_debug_rd_way_en := Fill(ICACHE_NUM_WAYS, io.ic_debug_rd_en & io.ic_debug_tag_array) & io.ic_debug_way + ic_debug_wr_way_en := Fill(ICACHE_NUM_WAYS, io.ic_debug_wr_en & io.ic_debug_tag_array) & io.ic_debug_way + + val ic_tag_wren_q = ic_tag_wren | ic_debug_wr_way_en + + val ic_tag_ecc = if(ICACHE_ECC) rvecc_encode(Cat(Fill(ICACHE_TAG_LO,0.U),io.ic_rw_addr(31-3, ICACHE_TAG_LO-3))) else 0.U + + val ic_tag_parity = if(ICACHE_ECC) rveven_paritygen(Cat(Fill(ICACHE_TAG_LO,0.U),io.ic_rw_addr(31-3, ICACHE_TAG_LO-3))) else 0.U + + val ic_tag_wr_data = if(ICACHE_TAG_LO==1)Mux(io.ic_debug_wr_en & io.ic_debug_tag_array, Cat(if(ICACHE_ECC) io.ic_debug_wr_data(68,64) else io.ic_debug_wr_data(64), io.ic_debug_wr_data(31,11)), + Cat(if(ICACHE_ECC) ic_tag_ecc(4,0) else ic_tag_parity, io.ic_rw_addr(31-3,ICACHE_TAG_LO-3))) + else Mux(io.ic_debug_wr_en & io.ic_debug_tag_array, Cat(if(ICACHE_ECC) io.ic_debug_wr_data(68,64) else io.ic_debug_wr_data(64), io.ic_debug_wr_data(31,11)), + Cat(if(ICACHE_ECC) Cat(ic_tag_ecc(4,0),Fill(PAD_BITS,0.U)) else Cat(ic_tag_parity,Fill(PAD_BITS,0.U)), io.ic_rw_addr(31-3,ICACHE_TAG_LO-3))) + + val ic_rw_addr_q = Mux((io.ic_debug_rd_en | io.ic_debug_wr_en).asBool,io.ic_debug_addr(ICACHE_INDEX_HI-3,ICACHE_TAG_INDEX_LO-3),io.ic_rw_addr) + + val ic_debug_rd_way_en_ff = RegNext(ic_debug_rd_way_en, 0.U) + + val tag_mem = Mem(ICACHE_TAG_DEPTH, Vec(ICACHE_NUM_WAYS, UInt(Tag_Word.W))) + + val write_vec = VecInit.tabulate(ICACHE_NUM_WAYS)(i=>ic_tag_wren_q(i)&ic_tag_clken(i)) + tag_mem.write(ic_rw_addr_q, VecInit.tabulate(ICACHE_NUM_WAYS)(i=>ic_tag_wr_data), write_vec) + + val read_enable = VecInit.tabulate(ICACHE_NUM_WAYS)(i=>(!ic_tag_wren_q(i))&ic_tag_clken(i)) + + val ic_tag_data_raw = (0 until ICACHE_NUM_WAYS).map(i=>Fill(Tag_Word,read_enable(i))&tag_mem.read(ic_rw_addr_q)(i)) + + val w_tout = if(ICACHE_ECC) VecInit.tabulate(ICACHE_NUM_WAYS)(i=>Cat(ic_tag_data_raw(i)(25,21), ic_tag_data_raw(i)(31-ICACHE_TAG_LO,0))) + else VecInit.tabulate(ICACHE_NUM_WAYS)(i=>Cat(ic_tag_data_raw(i)(21), ic_tag_data_raw(i)(31-ICACHE_TAG_LO,0))) + + val ic_tag_corrected_ecc_unc = Wire(Vec(ICACHE_NUM_WAYS, UInt(7.W))) + val ic_tag_corrected_data_unc = Wire(Vec(ICACHE_NUM_WAYS, UInt(32.W))) + val ic_tag_single_ecc_error = Wire(Vec(ICACHE_NUM_WAYS, UInt(1.W))) + val ic_tag_double_ecc_error = Wire(Vec(ICACHE_NUM_WAYS, UInt(1.W))) + for(i<- 0 until ICACHE_NUM_WAYS){ + val decoded_ecc = if(ICACHE_ECC) rvecc_decode(~io.dec_tlu_core_ecc_disable & ic_rd_en_ff, Cat(0.U(11.W),ic_tag_data_raw(i)(20,0)), Cat(0.U(2.W),ic_tag_data_raw(i)(25,21)), 1.U) + else (0.U, 0.U, 0.U, 0.U) + ic_tag_corrected_ecc_unc(i) := decoded_ecc._1 + ic_tag_corrected_data_unc(i) := decoded_ecc._2 + ic_tag_single_ecc_error(i):= decoded_ecc._3 + ic_tag_double_ecc_error(i) := decoded_ecc._4 + } + + val ic_tag_way_perr = if(ICACHE_ECC)ic_tag_single_ecc_error.reverse.reduce(Cat(_,_)) | ic_tag_double_ecc_error.reverse.reduce(Cat(_,_)) + else (0 until ICACHE_NUM_WAYS).map(i=>rveven_paritycheck(ic_tag_data_raw(i)(31-ICACHE_TAG_LO,0), ic_tag_data_raw(i)(21))).reverse.reduce(Cat(_,_)) + + io.ictag_debug_rd_data := (0 until ICACHE_NUM_WAYS).map(i=> if(ICACHE_ECC) Fill(26, ic_debug_rd_way_en_ff(i))&ic_tag_data_raw(i) else Cat(0.U(4.W), Fill(22, ic_debug_rd_way_en_ff(i)),ic_tag_data_raw(i)(21,0))).reduce(_|_) + io.ic_rd_hit := (0 until ICACHE_NUM_WAYS).map(i=>((w_tout(i)(31-ICACHE_TAG_LO,0)===ic_rw_addr_ff)&io.ic_tag_valid(i)).asUInt()).reverse.reduce(Cat(_,_)) + io.ic_tag_perr := (ic_tag_way_perr & io.ic_tag_valid).orR() +} + + +//////////////////////////////////////////////// + +class EL2_IC_DATA extends Module with el2_lib { + val io = IO (new Bundle{ + val clk_override = Input(Bool()) + val ic_rw_addr = Input(UInt(ICACHE_INDEX_HI.W)) + val ic_wr_en = Input(UInt(ICACHE_NUM_WAYS.W)) + val ic_rd_en = Input(Bool()) + val ic_wr_data = Input(Vec(ICACHE_NUM_WAYS, UInt(71.W))) + val ic_rd_data = Output(UInt(64.W)) + val ic_debug_wr_data = Input(UInt(71.W)) + val ic_debug_rd_data = Output(UInt(71.W)) + val ic_parerr = Output(UInt(ICACHE_NUM_WAYS.W)) + val ic_eccerr = Output(UInt(ICACHE_BANKS_WAY.W)) + val ic_debug_addr = Input(UInt((ICACHE_INDEX_HI-3).W)) + val ic_debug_rd_en = Input(Bool()) + val ic_debug_wr_en = Input(Bool()) + val ic_debug_tag_array = Input(Bool()) + val ic_debug_way = Input(UInt(ICACHE_NUM_WAYS.W)) + val ic_premux_data = Input(UInt(64.W)) + val ic_sel_premux_data = Input(Bool()) + val ic_rd_hit = Input(UInt(ICACHE_NUM_WAYS.W)) + val scan_mode = Input(UInt(1.W)) + }) val ic_debug_rd_way_en = Fill(ICACHE_NUM_WAYS, io.ic_debug_rd_en & !io.ic_debug_tag_array) & io.ic_debug_way val ic_debug_wr_way_en = Fill(ICACHE_NUM_WAYS, io.ic_debug_wr_en & !io.ic_debug_tag_array) & io.ic_debug_way @@ -54,9 +207,9 @@ class el2_ifu_ic_mem extends Module with el2_lib { val ic_sb_wr_data = (0 until ICACHE_NUM_WAYS).map(i=> Mux((ic_debug_sel_sb(i)&io.ic_debug_wr_en).asBool, io.ic_debug_wr_data, ic_bank_wr_data(i))) val ic_b_rden = (0 until ICACHE_NUM_WAYS).map(i=> (Mux1H(Seq(!ic_rw_addr_q(ICACHE_BANK_HI-1).asBool -> (i.U === 0.U), - (ic_rw_addr_q(ICACHE_BANK_HI-1)).asBool -> ((ic_rw_addr_q(1,0)===3.U)&(i.U===0.U)), - ic_rw_addr_q(ICACHE_BANK_HI-1).asBool -> (i.U === 1.U), - (!ic_rw_addr_q(ICACHE_BANK_HI-1)).asBool -> ((ic_rw_addr_q(1,0)===3.U)&(i.U === 1.U)))) & ic_rd_en_with_debug).asUInt).reverse.reduce(Cat(_,_)) + (ic_rw_addr_q(ICACHE_BANK_HI-1)).asBool -> ((ic_rw_addr_q(1,0)===3.U)&(i.U===0.U)), + ic_rw_addr_q(ICACHE_BANK_HI-1).asBool -> (i.U === 1.U), + (!ic_rw_addr_q(ICACHE_BANK_HI-1)).asBool -> ((ic_rw_addr_q(1,0)===3.U)&(i.U === 1.U)))) & ic_rd_en_with_debug).asUInt).reverse.reduce(Cat(_,_)) val ic_b_sb_rden = (0 until ic_b_rden.getWidth).map(i=>Fill(ICACHE_NUM_WAYS, ic_b_rden(i))) val ic_bank_way_clken = (0 until ICACHE_BANKS_WAY).map(i=>(0 until ICACHE_NUM_WAYS).map(j=> (ic_b_sb_rden(i)(j) | io.clk_override | ic_b_sb_wren(i)(j)).asUInt).reduce(Cat(_,_))) @@ -76,7 +229,7 @@ class el2_ifu_ic_mem extends Module with el2_lib { val ic_cacheline_wrap_ff = ic_rw_addr_ff(ICACHE_TAG_INDEX_LO-2,ICACHE_BANK_LO-1) === Fill(ICACHE_TAG_INDEX_LO-ICACHE_BANK_LO, 1.U) - //////////////////////////////////////////// Memory stated +//////////////////////////////////////////// Memory stated val (data_mem_word, tag_mem_word, ecc_offset, tag_word) = DATA_MEM_LINE val wb_dout = Wire(Vec(ICACHE_BANKS_WAY,Vec(ICACHE_NUM_WAYS, UInt(data_mem_word.W)))) val data_mem = Mem(ICACHE_DATA_DEPTH, Vec(ICACHE_BANKS_WAY,Vec(ICACHE_NUM_WAYS, UInt(data_mem_word.W)))) @@ -117,299 +270,7 @@ class el2_ifu_ic_mem extends Module with el2_lib { for(i<-0 until ICACHE_NUM_WAYS; j<-0 until 4){ic_parerr_bank(i)(j):=rveven_paritycheck(wb_dout_ecc_bank(i)(16*(j+1)-1, 16*j), wb_dout_ecc_bank(i)(64+j))} io.ic_parerr := Cat(ic_parerr_bank(0).reduce(_|_) & bank_check_en(0), ic_parerr_bank(1).reduce(_|_) & bank_check_en(1)) - - - - // ICACHE Tag - -// val ic_tag_wren = io.ic_wr_en & Fill(ICACHE_NUM_WAYS, io.ic_rw_addr(ICACHE_BEAT_ADDR_HI-3,1)=== Fill(ICACHE_NUM_WAYS-1, 1.U)) -// val ic_tag_clken = Fill(ICACHE_NUM_WAYS, io.ic_rd_en|io.clk_override) | io.ic_wr_en | ic_debug_wr_way_en | ic_debug_rd_way_en -// -// val ic_rd_en_ff = RegNext(io.ic_rd_en, 0.U) -// val ic_rw_addr_ff = RegNext(io.ic_rw_addr(31-ICACHE_TAG_LO, 0), 0.U) -// -// val PAD_BITS = 21 - (32 - ICACHE_TAG_LO) -// -// val ic_tag_wren_q = ic_tag_wren | ic_debug_wr_way_en -// -// val ic_tag_ecc = if(ICACHE_ECC) rvecc_encode(Cat(Fill(ICACHE_TAG_LO,0.U),io.ic_rw_addr(31-3, ICACHE_TAG_LO-3))) else 0.U -// -// val ic_tag_parity = if(ICACHE_ECC) rveven_paritygen(Cat(Fill(ICACHE_TAG_LO,0.U),io.ic_rw_addr(31-3, ICACHE_TAG_LO-3))) else 0.U -// -// val ic_tag_wr_data = if(ICACHE_TAG_LO==1)Mux(io.ic_debug_wr_en & io.ic_debug_tag_array, Cat(if(ICACHE_ECC) io.ic_debug_wr_data(68,64) else io.ic_debug_wr_data(64), io.ic_debug_wr_data(31,11)), -// Cat(if(ICACHE_ECC) ic_tag_ecc(4,0) else ic_tag_parity, io.ic_rw_addr(31-3,ICACHE_TAG_LO-3))) -// else Mux(io.ic_debug_wr_en & io.ic_debug_tag_array, Cat(if(ICACHE_ECC) io.ic_debug_wr_data(68,64) else io.ic_debug_wr_data(64), io.ic_debug_wr_data(31,11)), -// Cat(if(ICACHE_ECC) Cat(ic_tag_ecc(4,0),Fill(PAD_BITS,0.U)) else Cat(ic_tag_parity,Fill(PAD_BITS,0.U)), io.ic_rw_addr(31-3,ICACHE_TAG_LO-3))) -// -// val ic_rw_addr_q = Mux((io.ic_debug_rd_en | io.ic_debug_wr_en).asBool,io.ic_debug_addr(ICACHE_INDEX_HI-3,ICACHE_TAG_INDEX_LO-3),io.ic_rw_addr) -// -// val ic_debug_rd_way_en_ff = RegNext(ic_debug_rd_way_en, 0.U) -// -// val tag_mem = Mem(ICACHE_TAG_DEPTH, Vec(ICACHE_NUM_WAYS, UInt(Tag_Word.W))) -// -// val write_vec = VecInit.tabulate(ICACHE_NUM_WAYS)(i=>ic_tag_wren_q(i)&ic_tag_clken(i)) -// tag_mem.write(ic_rw_addr_q, VecInit.tabulate(ICACHE_NUM_WAYS)(i=>ic_tag_wr_data), write_vec) -// -// val read_enable = VecInit.tabulate(ICACHE_NUM_WAYS)(i=>(!ic_tag_wren_q(i))&ic_tag_clken(i)) -// -// val ic_tag_data_raw = (0 until ICACHE_NUM_WAYS).map(i=>Fill(Tag_Word,read_enable(i))&tag_mem.read(ic_rw_addr_q)(i)) -// -// val w_tout = if(ICACHE_ECC) VecInit.tabulate(ICACHE_NUM_WAYS)(i=>Cat(ic_tag_data_raw(i)(25,21), ic_tag_data_raw(i)(31-ICACHE_TAG_LO,0))) -// else VecInit.tabulate(ICACHE_NUM_WAYS)(i=>Cat(ic_tag_data_raw(i)(21), ic_tag_data_raw(i)(31-ICACHE_TAG_LO,0))) -// -// val ic_tag_corrected_ecc_unc = Wire(Vec(ICACHE_NUM_WAYS, UInt(7.W))) -// val ic_tag_corrected_data_unc = Wire(Vec(ICACHE_NUM_WAYS, UInt(32.W))) -// val ic_tag_single_ecc_error = Wire(Vec(ICACHE_NUM_WAYS, UInt(1.W))) -// val ic_tag_double_ecc_error = Wire(Vec(ICACHE_NUM_WAYS, UInt(1.W))) -// for(i<- 0 until ICACHE_NUM_WAYS){ -// val decoded_ecc = if(ICACHE_ECC) rvecc_decode(~io.dec_tlu_core_ecc_disable & ic_rd_en_ff, Cat(0.U(11.W),ic_tag_data_raw(i)(20,0)), Cat(0.U(2.W),ic_tag_data_raw(i)(25,21)), 1.U) -// else (0.U, 0.U, 0.U, 0.U) -// ic_tag_corrected_ecc_unc(i) := decoded_ecc._1 -// ic_tag_corrected_data_unc(i) := decoded_ecc._2 -// ic_tag_single_ecc_error(i):= decoded_ecc._3 -// ic_tag_double_ecc_error(i) := decoded_ecc._4 -// } -// -// val ic_tag_way_perr = if(ICACHE_ECC)ic_tag_single_ecc_error.reverse.reduce(Cat(_,_)) | ic_tag_double_ecc_error.reverse.reduce(Cat(_,_)) -// else (0 until ICACHE_NUM_WAYS).map(i=>rveven_paritycheck(ic_tag_data_raw(i)(31-ICACHE_TAG_LO,0), ic_tag_data_raw(i)(21))).reverse.reduce(Cat(_,_)) -// -// io.ictag_debug_rd_data := (0 until ICACHE_NUM_WAYS).map(i=> if(ICACHE_ECC) Fill(26, ic_debug_rd_way_en_ff(i))&ic_tag_data_raw(i) else Cat(0.U(4.W), Fill(22, ic_debug_rd_way_en_ff(i)),ic_tag_data_raw(i)(21,0))).reduce(_|_) -// io.ic_rd_hit := (0 until ICACHE_NUM_WAYS).map(i=>((w_tout(i)(31-ICACHE_TAG_LO,0)===ic_rw_addr_ff)&io.ic_tag_valid(i)).asUInt()).reverse.reduce(Cat(_,_)) -// io.ic_tag_perr := (ic_tag_way_perr & io.ic_tag_valid).orR() } - //val ic_tag_inst = Module(new EL2_IC_TAG()) - //ic_tag_inst.io <> io - //ic_tag_inst.io.ic_tag_valid := io.ic_tag_valid -// ic_tag_inst.io.dec_tlu_core_ecc_disable := io.dec_tlu_core_ecc_disable -// ic_tag_inst.io.clk_override := io.clk_override -// ic_tag_inst.io.ic_rw_addr := io.ic_rw_addr -// ic_tag_inst.io.ic_wr_en := io.ic_wr_en -// ic_tag_inst.io.ic_rd_en := io.ic_rd_en -// ic_tag_inst.io.ic_debug_addr := io.ic_debug_addr -// ic_tag_inst.io.ic_debug_rd_en := io.ic_debug_rd_en -// ic_tag_inst.io.ic_debug_wr_en := io.ic_debug_wr_en -// ic_tag_inst.io.ic_debug_tag_array := io.ic_debug_tag_array -// ic_tag_inst.io.ic_debug_way := io.ic_debug_way -// io.ictag_debug_rd_data := ic_tag_inst.io.ictag_debug_rd_data // Output -// ic_tag_inst.io.ic_debug_wr_data := io.ic_debug_wr_data -// io.ic_rd_hit := ic_tag_inst.io.ic_rd_hit // Output -// io.ic_tag_perr := ic_tag_inst.io.ic_tag_perr // Output -// ic_tag_inst.io.scan_mode := io.scan_mode -// val ic_data_inst = Module(new EL2_IC_DATA()) -// ic_data_inst.io.clk_override := io.clk_override -// -// ic_data_inst.io.ic_rw_addr :=io.ic_rw_addr -// ic_data_inst.io.ic_wr_en :=io.ic_wr_en -// ic_data_inst.io.ic_rd_en :=io.ic_rd_en -// -// ic_data_inst.io.ic_wr_data :=io.ic_wr_data -// io.ic_rd_data := ic_data_inst.io.ic_rd_data -// ic_data_inst.io.ic_debug_wr_data :=io.ic_debug_wr_data -// io.ic_debug_rd_data := ic_data_inst.io.ic_debug_rd_data -// io.ic_parerr := ic_data_inst.io.ic_parerr -// io.ic_eccerr := ic_data_inst.io.ic_eccerr -// ic_data_inst.io.ic_debug_addr := io.ic_debug_addr -// ic_data_inst.io.ic_debug_rd_en := io.ic_debug_rd_en -// ic_data_inst.io.ic_debug_wr_en := io.ic_debug_wr_en -// ic_data_inst.io.ic_debug_tag_array := io.ic_debug_tag_array -// ic_data_inst.io.ic_debug_way := io.ic_debug_way -// ic_data_inst.io.ic_premux_data := io.ic_premux_data -// ic_data_inst.io.ic_sel_premux_data := io.ic_sel_premux_data -// -// ic_data_inst.io.ic_rd_hit :=io.ic_rd_hit -// ic_data_inst.io.scan_mode :=io.scan_mode - - -/////////// ICACHE TAG -//class EL2_IC_TAG extends Module with el2_lib with param { -// val io = IO(new Bundle{ -// val scan_mode = Input(Bool()) -// val clk_override = Input(Bool()) -// val dec_tlu_core_ecc_disable = Input(Bool()) -// val ic_rw_addr = Input(UInt(29.W)) // 32:3 -// val ic_wr_en = Input(UInt(ICACHE_NUM_WAYS.W)) -// val ic_tag_valid = Input(UInt(ICACHE_NUM_WAYS.W)) -// val ic_rd_en = Input(Bool()) -// val ic_debug_addr = Input(UInt((ICACHE_INDEX_HI-2).W)) // 12-2 = 10-bit value -// val ic_debug_rd_en = Input(Bool()) -// val ic_debug_wr_en = Input(Bool()) -// val ic_debug_tag_array = Input(Bool()) -// val ic_debug_way = Input(UInt(ICACHE_NUM_WAYS.W)) -// val ictag_debug_rd_data = Output(UInt(26.W)) -// val ic_debug_wr_data = Input(UInt(71.W)) -// val ic_rd_hit = Output(UInt(ICACHE_NUM_WAYS.W)) -// val ic_tag_perr = Output(Bool()) -// }) -// io.ictag_debug_rd_data := 0.U -// io.ic_rd_hit := 0.U -// io.ic_tag_perr := 0.U -// val ic_debug_wr_way_en = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U) -// val ic_debug_rd_way_en = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U) -// -// val ic_tag_wren = io.ic_wr_en & Fill(ICACHE_NUM_WAYS, io.ic_rw_addr(ICACHE_BEAT_ADDR_HI-3,1)=== Fill(ICACHE_NUM_WAYS-1, 1.U)) -// val ic_tag_clken = Fill(ICACHE_NUM_WAYS, io.ic_rd_en|io.clk_override) | io.ic_wr_en | ic_debug_wr_way_en | ic_debug_rd_way_en -// -// val ic_rd_en_ff = RegNext(io.ic_rd_en, 0.U) -// val ic_rw_addr_ff = RegNext(io.ic_rw_addr(31-ICACHE_TAG_LO, 0), 0.U) -// -// val PAD_BITS = 21 - (32 - ICACHE_TAG_LO) -// -// ic_debug_rd_way_en := Fill(ICACHE_NUM_WAYS, io.ic_debug_rd_en & io.ic_debug_tag_array) & io.ic_debug_way -// ic_debug_wr_way_en := Fill(ICACHE_NUM_WAYS, io.ic_debug_wr_en & io.ic_debug_tag_array) & io.ic_debug_way -// -// val ic_tag_wren_q = ic_tag_wren | ic_debug_wr_way_en -// -// val ic_tag_ecc = if(ICACHE_ECC) rvecc_encode(Cat(Fill(ICACHE_TAG_LO,0.U),io.ic_rw_addr(31-3, ICACHE_TAG_LO-3))) else 0.U -// -// val ic_tag_parity = if(ICACHE_ECC) rveven_paritygen(Cat(Fill(ICACHE_TAG_LO,0.U),io.ic_rw_addr(31-3, ICACHE_TAG_LO-3))) else 0.U -// -// val ic_tag_wr_data = if(ICACHE_TAG_LO==1)Mux(io.ic_debug_wr_en & io.ic_debug_tag_array, Cat(if(ICACHE_ECC) io.ic_debug_wr_data(68,64) else io.ic_debug_wr_data(64), io.ic_debug_wr_data(31,11)), -// Cat(if(ICACHE_ECC) ic_tag_ecc(4,0) else ic_tag_parity, io.ic_rw_addr(31-3,ICACHE_TAG_LO-3))) -// else Mux(io.ic_debug_wr_en & io.ic_debug_tag_array, Cat(if(ICACHE_ECC) io.ic_debug_wr_data(68,64) else io.ic_debug_wr_data(64), io.ic_debug_wr_data(31,11)), -// Cat(if(ICACHE_ECC) Cat(ic_tag_ecc(4,0),Fill(PAD_BITS,0.U)) else Cat(ic_tag_parity,Fill(PAD_BITS,0.U)), io.ic_rw_addr(31-3,ICACHE_TAG_LO-3))) -// -// val ic_rw_addr_q = Mux((io.ic_debug_rd_en | io.ic_debug_wr_en).asBool,io.ic_debug_addr(ICACHE_INDEX_HI-3,ICACHE_TAG_INDEX_LO-3),io.ic_rw_addr) -// -// val ic_debug_rd_way_en_ff = RegNext(ic_debug_rd_way_en, 0.U) -// -// val tag_mem = Mem(ICACHE_TAG_DEPTH, Vec(ICACHE_NUM_WAYS, UInt(Tag_Word.W))) -// -// val write_vec = VecInit.tabulate(ICACHE_NUM_WAYS)(i=>ic_tag_wren_q(i)&ic_tag_clken(i)) -// tag_mem.write(ic_rw_addr_q, VecInit.tabulate(ICACHE_NUM_WAYS)(i=>ic_tag_wr_data), write_vec) -// -// val read_enable = VecInit.tabulate(ICACHE_NUM_WAYS)(i=>(!ic_tag_wren_q(i))&ic_tag_clken(i)) -// -// val ic_tag_data_raw = (0 until ICACHE_NUM_WAYS).map(i=>Fill(Tag_Word,read_enable(i))&tag_mem.read(ic_rw_addr_q)(i)) -// -// val w_tout = if(ICACHE_ECC) VecInit.tabulate(ICACHE_NUM_WAYS)(i=>Cat(ic_tag_data_raw(i)(25,21), ic_tag_data_raw(i)(31-ICACHE_TAG_LO,0))) -// else VecInit.tabulate(ICACHE_NUM_WAYS)(i=>Cat(ic_tag_data_raw(i)(21), ic_tag_data_raw(i)(31-ICACHE_TAG_LO,0))) -// -// val ic_tag_corrected_ecc_unc = Wire(Vec(ICACHE_NUM_WAYS, UInt(7.W))) -// val ic_tag_corrected_data_unc = Wire(Vec(ICACHE_NUM_WAYS, UInt(32.W))) -// val ic_tag_single_ecc_error = Wire(Vec(ICACHE_NUM_WAYS, UInt(1.W))) -// val ic_tag_double_ecc_error = Wire(Vec(ICACHE_NUM_WAYS, UInt(1.W))) -// for(i<- 0 until ICACHE_NUM_WAYS){ -// val decoded_ecc = if(ICACHE_ECC) rvecc_decode(~io.dec_tlu_core_ecc_disable & ic_rd_en_ff, Cat(0.U(11.W),ic_tag_data_raw(i)(20,0)), Cat(0.U(2.W),ic_tag_data_raw(i)(25,21)), 1.U) -// else (0.U, 0.U, 0.U, 0.U) -// ic_tag_corrected_ecc_unc(i) := decoded_ecc._1 -// ic_tag_corrected_data_unc(i) := decoded_ecc._2 -// ic_tag_single_ecc_error(i):= decoded_ecc._3 -// ic_tag_double_ecc_error(i) := decoded_ecc._4 -// } -// -// val ic_tag_way_perr = if(ICACHE_ECC)ic_tag_single_ecc_error.reverse.reduce(Cat(_,_)) | ic_tag_double_ecc_error.reverse.reduce(Cat(_,_)) -// else (0 until ICACHE_NUM_WAYS).map(i=>rveven_paritycheck(ic_tag_data_raw(i)(31-ICACHE_TAG_LO,0), ic_tag_data_raw(i)(21))).reverse.reduce(Cat(_,_)) -// -// io.ictag_debug_rd_data := (0 until ICACHE_NUM_WAYS).map(i=> if(ICACHE_ECC) Fill(26, ic_debug_rd_way_en_ff(i))&ic_tag_data_raw(i) else Cat(0.U(4.W), Fill(22, ic_debug_rd_way_en_ff(i)),ic_tag_data_raw(i)(21,0))).reduce(_|_) -// io.ic_rd_hit := (0 until ICACHE_NUM_WAYS).map(i=>((w_tout(i)(31-ICACHE_TAG_LO,0)===ic_rw_addr_ff)&io.ic_tag_valid(i)).asUInt()).reverse.reduce(Cat(_,_)) -// io.ic_tag_perr := (ic_tag_way_perr & io.ic_tag_valid).orR() -//} -// -// -////////////////////////////////////////////////// -// -//class EL2_IC_DATA extends Module with el2_lib { -// val io = IO (new Bundle{ -// val clk_override = Input(Bool()) -// val ic_rw_addr = Input(UInt(ICACHE_INDEX_HI.W)) -// val ic_wr_en = Input(UInt(ICACHE_NUM_WAYS.W)) -// val ic_rd_en = Input(Bool()) -// val ic_wr_data = Input(Vec(ICACHE_NUM_WAYS, UInt(71.W))) -// val ic_rd_data = Output(UInt(64.W)) -// val ic_debug_wr_data = Input(UInt(71.W)) -// val ic_debug_rd_data = Output(UInt(71.W)) -// val ic_parerr = Output(UInt(ICACHE_NUM_WAYS.W)) -// val ic_eccerr = Output(UInt(ICACHE_BANKS_WAY.W)) -// val ic_debug_addr = Input(UInt((ICACHE_INDEX_HI-3).W)) -// val ic_debug_rd_en = Input(Bool()) -// val ic_debug_wr_en = Input(Bool()) -// val ic_debug_tag_array = Input(Bool()) -// val ic_debug_way = Input(UInt(ICACHE_NUM_WAYS.W)) -// val ic_premux_data = Input(UInt(64.W)) -// val ic_sel_premux_data = Input(Bool()) -// val ic_rd_hit = Input(UInt(ICACHE_NUM_WAYS.W)) -// val scan_mode = Input(UInt(1.W)) -// }) -// -// val ic_debug_rd_way_en = Fill(ICACHE_NUM_WAYS, io.ic_debug_rd_en & !io.ic_debug_tag_array) & io.ic_debug_way -// val ic_debug_wr_way_en = Fill(ICACHE_NUM_WAYS, io.ic_debug_wr_en & !io.ic_debug_tag_array) & io.ic_debug_way -// -// val ic_bank_wr_data = Wire(Vec(ICACHE_BANKS_WAY,UInt(71.W))) -// val ic_rd_en_with_debug = WireInit(Bool(), 0.U) -// -// val ic_rw_addr_q = Mux((io.ic_debug_rd_en | io.ic_debug_wr_en).asBool, Cat(io.ic_debug_addr,0.U(2.W)), io.ic_rw_addr) -// -// val ic_rw_addr_q_inc = ic_rw_addr_q(ICACHE_TAG_LO-2,ICACHE_DATA_INDEX_LO-1) + 1.U -// val ic_b_sb_wren = (0 until ICACHE_NUM_WAYS).map(i=> -// io.ic_wr_en | ic_debug_wr_way_en & Fill(ICACHE_NUM_WAYS, io.ic_debug_addr(ICACHE_BANK_HI-3,ICACHE_BANK_LO-3)===i.U)) -// val ic_debug_sel_sb = (0 until ICACHE_NUM_WAYS).map(i=> (io.ic_debug_addr(ICACHE_BANK_HI-3,ICACHE_BANK_LO-3)===i.U).asUInt).reverse.reduce(Cat(_,_)) -// val ic_sb_wr_data = (0 until ICACHE_NUM_WAYS).map(i=> Mux((ic_debug_sel_sb(i)&io.ic_debug_wr_en).asBool, io.ic_debug_wr_data, ic_bank_wr_data(i))) -// val ic_b_rden = (0 until ICACHE_NUM_WAYS).map(i=> -// (Mux1H(Seq(!ic_rw_addr_q(ICACHE_BANK_HI-1).asBool -> (i.U === 0.U), -// (ic_rw_addr_q(ICACHE_BANK_HI-1)).asBool -> ((ic_rw_addr_q(1,0)===3.U)&(i.U===0.U)), -// ic_rw_addr_q(ICACHE_BANK_HI-1).asBool -> (i.U === 1.U), -// (!ic_rw_addr_q(ICACHE_BANK_HI-1)).asBool -> ((ic_rw_addr_q(1,0)===3.U)&(i.U === 1.U)))) & ic_rd_en_with_debug).asUInt).reverse.reduce(Cat(_,_)) -// val ic_b_sb_rden = (0 until ic_b_rden.getWidth).map(i=>Fill(ICACHE_NUM_WAYS, ic_b_rden(i))) -// val ic_bank_way_clken = (0 until ICACHE_BANKS_WAY).map(i=>(0 until ICACHE_NUM_WAYS).map(j=> -// (ic_b_sb_rden(i)(j) | io.clk_override | ic_b_sb_wren(i)(j)).asUInt).reduce(Cat(_,_))) -// -// ic_rd_en_with_debug := io.ic_rd_en | io.ic_debug_rd_en & (!io.ic_wr_en.orR) -// -// val ic_rw_addr_wrap = ic_rw_addr_q(ICACHE_BANK_HI-1) & (ic_rw_addr_q(1,0) === 3.U) & ic_rd_en_with_debug & !(io.ic_wr_en.orR) -// -// val ic_rw_addr_bank_q = VecInit(Mux((!ic_rw_addr_wrap).asBool,ic_rw_addr_q(ICACHE_INDEX_HI-1,ICACHE_DATA_INDEX_LO-1), -// Cat(ic_rw_addr_q(ICACHE_INDEX_HI-1, ICACHE_TAG_INDEX_LO-1) , ic_rw_addr_q_inc(ICACHE_TAG_INDEX_LO-2,ICACHE_DATA_INDEX_LO-1))), -// ic_rw_addr_q(ICACHE_INDEX_HI-1,ICACHE_DATA_INDEX_LO-1)) -// -// val ic_b_rden_ff = RegNext(ic_b_rden, 0.U) -// val ic_rw_addr_ff = RegNext(ic_rw_addr_q(ICACHE_TAG_INDEX_LO-2,0), 0.U) -// val ic_debug_rd_way_en_ff = RegNext(ic_debug_rd_way_en, 0.U) -// val ic_debug_rd_en_ff = RegNext(io.ic_debug_rd_en, 0.U) -// -// val ic_cacheline_wrap_ff = ic_rw_addr_ff(ICACHE_TAG_INDEX_LO-2,ICACHE_BANK_LO-1) === Fill(ICACHE_TAG_INDEX_LO-ICACHE_BANK_LO, 1.U) -// -////////////////////////////////////////////// Memory stated -// val (data_mem_word, tag_mem_word, ecc_offset, tag_word) = DATA_MEM_LINE -// val wb_dout = Wire(Vec(ICACHE_BANKS_WAY,Vec(ICACHE_NUM_WAYS, UInt(data_mem_word.W)))) -// val data_mem = Mem(ICACHE_DATA_DEPTH, Vec(ICACHE_BANKS_WAY,Vec(ICACHE_NUM_WAYS, UInt(data_mem_word.W)))) -// for(i<-0 until ICACHE_NUM_WAYS; k<-0 until ICACHE_BANKS_WAY){ -// wb_dout(i)(k) := 0.U -// val WE = if(ICACHE_WAYPACK) ic_b_sb_wren(k).orR else ic_b_sb_wren(k)(i) -// val ME = if(ICACHE_WAYPACK) ic_bank_way_clken(k).orR else ic_bank_way_clken(k)(i) -// when((ic_b_sb_wren(k)(i) & ic_bank_way_clken(k)(i)).asBool){ -// data_mem(ic_rw_addr_bank_q(k))(k)(i) := ic_sb_wr_data(k) -// }.elsewhen((!ic_b_sb_wren(k)(i)&ic_bank_way_clken(k)(i)).asBool){ -// wb_dout(i)(k) := data_mem(ic_rw_addr_bank_q(k))(k)(i) -// } -// } -// val ic_rd_hit_q = Mux(ic_debug_rd_en_ff.asBool, ic_debug_rd_way_en_ff, io.ic_rd_hit) -// ic_bank_wr_data := (0 until ICACHE_BANKS_WAY).map(io.ic_wr_data(_)) -// -// val wb_dout_way_pre = (0 until ICACHE_BANKS_WAY).map(i=>Cat( -// Mux1H((0 until ICACHE_BANKS_WAY).map(j=>(ic_rw_addr_ff(ICACHE_BANK_HI-1, ICACHE_BANK_LO-1)===j.U).asBool->wb_dout(i)(j))), -// Mux1H((0 until ICACHE_BANKS_WAY).map(j=>(ic_rw_addr_ff(ICACHE_BANK_HI-1, ICACHE_BANK_LO-1)===(j.U-1.U)).asBool->wb_dout(i)(j))))) -// -// val wb_dout_way = (0 until ICACHE_NUM_WAYS).map(i=>Mux1H(Seq((ic_rw_addr_ff(1,0)===0.U).asBool->wb_dout_way_pre(i)(63,0), -// (ic_rw_addr_ff(1,0)===1.U).asBool->Cat(wb_dout_way_pre(i)(data_mem_word+15,data_mem_word),wb_dout_way_pre(i)(63,16)), -// (ic_rw_addr_ff(1,0)===2.U).asBool->Cat(wb_dout_way_pre(i)(data_mem_word+31,data_mem_word),wb_dout_way_pre(i)(63,32)), -// (ic_rw_addr_ff(1,0)===3.U).asBool->Cat(wb_dout_way_pre(i)(data_mem_word+47,data_mem_word),wb_dout_way_pre(i)(63,48))))) -// -// val wb_dout_way_with_premux = (0 until ICACHE_NUM_WAYS).map(i=>Mux(io.ic_sel_premux_data.asBool,io.ic_premux_data, wb_dout_way(i))) -// -// io.ic_rd_data := Mux1H((0 until ICACHE_NUM_WAYS).map(i=>(ic_rd_hit_q(i) | io.ic_sel_premux_data).asBool->wb_dout_way_with_premux(i))) -// io.ic_debug_rd_data := Mux1H((0 until ICACHE_NUM_WAYS).map(i=>ic_rd_hit_q(i).asBool->wb_dout_way_pre(i)(70,0))) -// val wb_dout_ecc = Mux1H((0 until ICACHE_NUM_WAYS).map(i=>ic_rd_hit_q(i).asBool->wb_dout_way_pre(i))) -// -// val bank_check_en = for(i<-0 until ICACHE_BANKS_WAY) yield io.ic_rd_hit.orR & ((i.U==0.U).asBool | (!ic_cacheline_wrap_ff & (ic_b_rden_ff(ICACHE_BANKS_WAY-1,0) === Fill(ICACHE_BANKS_WAY,1.U)))) -// val wb_dout_ecc_bank = (0 until ICACHE_BANKS_WAY).map(i=> wb_dout_ecc((data_mem_word*i)+data_mem_word-1,data_mem_word*i)) -// -// // TODO: RVECC -// io.ic_eccerr := (0 until ICACHE_NUM_WAYS).map(i=>rvecc_decode_64(bank_check_en(i),wb_dout_ecc_bank(i)(63,0),wb_dout_ecc_bank(i)(70,64)).asUInt).reverse.reduce(Cat(_,_)) -// val ic_parerr_bank = Wire(Vec(ICACHE_NUM_WAYS, Vec(4, UInt(1.W)))) -// for(i<-0 until ICACHE_NUM_WAYS; j<-0 until 4){ic_parerr_bank(i)(j):=rveven_paritycheck(wb_dout_ecc_bank(i)(16*(j+1)-1, 16*j), wb_dout_ecc_bank(i)(64+j))} -// -// io.ic_parerr := Cat(ic_parerr_bank(0).reduce(_|_) & bank_check_en(0), ic_parerr_bank(1).reduce(_|_) & bank_check_en(1)) -//} object ifu_ic extends App { println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_ic_mem())) diff --git a/target/scala-2.12/classes/ifu/EL2_IC_DATA$$anon$3.class b/target/scala-2.12/classes/ifu/EL2_IC_DATA$$anon$3.class new file mode 100644 index 00000000..7b08864e Binary files /dev/null and b/target/scala-2.12/classes/ifu/EL2_IC_DATA$$anon$3.class differ diff --git a/target/scala-2.12/classes/ifu/EL2_IC_DATA.class b/target/scala-2.12/classes/ifu/EL2_IC_DATA.class new file mode 100644 index 00000000..b78aee98 Binary files /dev/null and b/target/scala-2.12/classes/ifu/EL2_IC_DATA.class differ diff --git a/target/scala-2.12/classes/ifu/EL2_IC_TAG$$anon$2.class b/target/scala-2.12/classes/ifu/EL2_IC_TAG$$anon$2.class new file mode 100644 index 00000000..159bc7f8 Binary files /dev/null and b/target/scala-2.12/classes/ifu/EL2_IC_TAG$$anon$2.class differ diff --git a/target/scala-2.12/classes/ifu/EL2_IC_TAG.class b/target/scala-2.12/classes/ifu/EL2_IC_TAG.class new file mode 100644 index 00000000..ac92e396 Binary files /dev/null and b/target/scala-2.12/classes/ifu/EL2_IC_TAG.class differ diff --git a/target/scala-2.12/classes/ifu/el2_ifu_ic_mem.class b/target/scala-2.12/classes/ifu/el2_ifu_ic_mem.class index 96a496b7..64b71837 100644 Binary files a/target/scala-2.12/classes/ifu/el2_ifu_ic_mem.class and b/target/scala-2.12/classes/ifu/el2_ifu_ic_mem.class differ diff --git a/target/scala-2.12/classes/ifu/ifu_ic$.class b/target/scala-2.12/classes/ifu/ifu_ic$.class index 26575c82..6cf594cd 100644 Binary files a/target/scala-2.12/classes/ifu/ifu_ic$.class and b/target/scala-2.12/classes/ifu/ifu_ic$.class differ diff --git a/target/scala-2.12/classes/ifu/ifu_ic$delayedInit$body.class b/target/scala-2.12/classes/ifu/ifu_ic$delayedInit$body.class index 7ae6a693..a51ae198 100644 Binary files a/target/scala-2.12/classes/ifu/ifu_ic$delayedInit$body.class and b/target/scala-2.12/classes/ifu/ifu_ic$delayedInit$body.class differ