diff --git a/lsu.anno.json b/lsu.anno.json
index 774ce490..0d76d396 100644
--- a/lsu.anno.json
+++ b/lsu.anno.json
@@ -10,29 +10,11 @@
   },
   {
     "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~lsu|lsu>io_lsu_pic_picm_mken",
+    "sink":"~lsu|lsu>io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata",
     "sources":[
-      "~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
-      "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
-      "~lsu|lsu>io_dec_lsu_valid_raw_d",
-      "~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
-      "~lsu|lsu>io_dec_lsu_offset_d",
-      "~lsu|lsu>io_lsu_p_bits_dword",
-      "~lsu|lsu>io_lsu_p_bits_half",
-      "~lsu|lsu>io_lsu_p_bits_word",
-      "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
-      "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
-      "~lsu|lsu>io_lsu_p_valid",
-      "~lsu|lsu>io_dec_tlu_flush_lower_r",
-      "~lsu|lsu>io_lsu_p_bits_fast_int",
-      "~lsu|lsu>io_lsu_p_bits_store",
-      "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
-      "~lsu|lsu>io_dec_tlu_force_halt",
-      "~lsu|lsu>io_lsu_pic_picm_rd_data",
+      "~lsu|lsu>io_dec_tlu_core_ecc_disable",
       "~lsu|lsu>io_dccm_rd_data_hi",
-      "~lsu|lsu>io_dccm_rd_data_lo",
-      "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
-      "~lsu|lsu>io_dec_tlu_core_ecc_disable"
+      "~lsu|lsu>io_dccm_rd_data_lo"
     ]
   },
   {
@@ -45,6 +27,17 @@
       "~lsu|lsu>io_dccm_rd_data_lo"
     ]
   },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu|lsu>io_dccm_rd_addr_hi",
+    "sources":[
+      "~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
+      "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
+      "~lsu|lsu>io_dec_lsu_valid_raw_d",
+      "~lsu|lsu>io_dec_lsu_offset_d",
+      "~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d"
+    ]
+  },
   {
     "class":"firrtl.transforms.CombinationalPath",
     "sink":"~lsu|lsu>io_lsu_dma_dccm_ready",
@@ -52,6 +45,166 @@
       "~lsu|lsu>io_dec_lsu_valid_raw_d"
     ]
   },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu|lsu>io_dccm_wr_data_hi",
+    "sources":[
+      "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
+      "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
+      "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
+      "~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
+      "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
+      "~lsu|lsu>io_dec_lsu_valid_raw_d",
+      "~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
+      "~lsu|lsu>io_dec_lsu_offset_d",
+      "~lsu|lsu>io_lsu_p_bits_dword",
+      "~lsu|lsu>io_lsu_p_bits_half",
+      "~lsu|lsu>io_lsu_p_bits_word",
+      "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_wdata"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu|lsu>io_dccm_wren",
+    "sources":[
+      "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
+      "~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
+      "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
+      "~lsu|lsu>io_dec_lsu_valid_raw_d",
+      "~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
+      "~lsu|lsu>io_dec_lsu_offset_d",
+      "~lsu|lsu>io_lsu_p_bits_dword",
+      "~lsu|lsu>io_lsu_p_bits_half",
+      "~lsu|lsu>io_lsu_p_bits_word",
+      "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
+      "~lsu|lsu>io_lsu_p_valid",
+      "~lsu|lsu>io_dec_tlu_flush_lower_r",
+      "~lsu|lsu>io_lsu_p_bits_fast_int",
+      "~lsu|lsu>io_lsu_p_bits_load",
+      "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
+      "~lsu|lsu>io_lsu_p_bits_store"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu|lsu>io_dccm_wr_addr_hi",
+    "sources":[
+      "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
+      "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
+      "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
+      "~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
+      "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
+      "~lsu|lsu>io_dec_lsu_valid_raw_d",
+      "~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
+      "~lsu|lsu>io_dec_lsu_offset_d",
+      "~lsu|lsu>io_lsu_p_bits_dword",
+      "~lsu|lsu>io_lsu_p_bits_half",
+      "~lsu|lsu>io_lsu_p_bits_word"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu|lsu>io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy",
+    "sources":[
+      "~lsu|lsu>io_axi_ar_ready",
+      "~lsu|lsu>io_axi_aw_ready",
+      "~lsu|lsu>io_axi_w_ready"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu|lsu>io_lsu_pic_picm_rden",
+    "sources":[
+      "~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
+      "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
+      "~lsu|lsu>io_dec_lsu_valid_raw_d",
+      "~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
+      "~lsu|lsu>io_dec_lsu_offset_d",
+      "~lsu|lsu>io_lsu_p_bits_dword",
+      "~lsu|lsu>io_lsu_p_bits_half",
+      "~lsu|lsu>io_lsu_p_bits_word",
+      "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
+      "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
+      "~lsu|lsu>io_lsu_p_valid",
+      "~lsu|lsu>io_dec_tlu_flush_lower_r",
+      "~lsu|lsu>io_lsu_p_bits_fast_int",
+      "~lsu|lsu>io_lsu_p_bits_load",
+      "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu|lsu>io_dccm_rd_addr_lo",
+    "sources":[
+      "~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
+      "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
+      "~lsu|lsu>io_dec_lsu_valid_raw_d",
+      "~lsu|lsu>io_dec_lsu_offset_d",
+      "~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu|lsu>io_dccm_wr_addr_lo",
+    "sources":[
+      "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
+      "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
+      "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
+      "~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
+      "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
+      "~lsu|lsu>io_dec_lsu_valid_raw_d",
+      "~lsu|lsu>io_dec_lsu_offset_d",
+      "~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
+      "~lsu|lsu>io_lsu_p_bits_dword",
+      "~lsu|lsu>io_lsu_p_bits_half",
+      "~lsu|lsu>io_lsu_p_bits_word"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu|lsu>io_lsu_fir_addr",
+    "sources":[
+      "~lsu|lsu>io_dec_tlu_core_ecc_disable",
+      "~lsu|lsu>io_dccm_rd_data_hi",
+      "~lsu|lsu>io_dccm_rd_data_lo"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu|lsu>io_lsu_pic_picm_rdaddr",
+    "sources":[
+      "~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
+      "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
+      "~lsu|lsu>io_dec_lsu_valid_raw_d",
+      "~lsu|lsu>io_dec_lsu_offset_d",
+      "~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu|lsu>io_lsu_pic_picm_wr_data",
+    "sources":[
+      "~lsu|lsu>io_lsu_dma_dma_dccm_ctl_dma_mem_wdata",
+      "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
+      "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
+      "~lsu|lsu>io_dec_tlu_core_ecc_disable",
+      "~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
+      "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
+      "~lsu|lsu>io_dec_lsu_valid_raw_d",
+      "~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
+      "~lsu|lsu>io_dec_lsu_offset_d",
+      "~lsu|lsu>io_lsu_p_bits_dword",
+      "~lsu|lsu>io_lsu_p_bits_half",
+      "~lsu|lsu>io_lsu_p_bits_word",
+      "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
+      "~lsu|lsu>io_lsu_p_valid",
+      "~lsu|lsu>io_dec_tlu_flush_lower_r",
+      "~lsu|lsu>io_lsu_p_bits_fast_int",
+      "~lsu|lsu>io_lsu_p_bits_load",
+      "~lsu|lsu>io_lsu_p_bits_store",
+      "~lsu|lsu>io_dccm_rd_data_lo"
+    ]
+  },
   {
     "class":"firrtl.transforms.CombinationalPath",
     "sink":"~lsu|lsu>io_lsu_trigger_match_m",
@@ -80,232 +233,7 @@
       "~lsu|lsu>io_trigger_pkt_any_3_match_pkt",
       "~lsu|lsu>io_trigger_pkt_any_2_tdata2",
       "~lsu|lsu>io_trigger_pkt_any_2_match_pkt",
-      "~lsu|lsu>io_lsu_pic_picm_rd_data",
-      "~lsu|lsu>io_dec_tlu_force_halt",
-      "~lsu|lsu>io_dccm_rd_data_hi",
-      "~lsu|lsu>io_dccm_rd_data_lo",
-      "~lsu|lsu>io_dec_tlu_flush_lower_r",
-      "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
-      "~lsu|lsu>io_dec_tlu_core_ecc_disable"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~lsu|lsu>io_dccm_wren",
-    "sources":[
-      "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
-      "~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
-      "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
-      "~lsu|lsu>io_dec_lsu_valid_raw_d",
-      "~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
-      "~lsu|lsu>io_dec_lsu_offset_d",
-      "~lsu|lsu>io_lsu_p_bits_dword",
-      "~lsu|lsu>io_lsu_p_bits_half",
-      "~lsu|lsu>io_lsu_p_bits_word",
-      "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
-      "~lsu|lsu>io_lsu_p_valid",
-      "~lsu|lsu>io_dec_tlu_flush_lower_r",
-      "~lsu|lsu>io_lsu_p_bits_fast_int",
-      "~lsu|lsu>io_lsu_p_bits_load",
-      "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
-      "~lsu|lsu>io_lsu_p_bits_store",
-      "~lsu|lsu>io_dec_tlu_force_halt",
-      "~lsu|lsu>io_lsu_pic_picm_rd_data",
-      "~lsu|lsu>io_dccm_rd_data_hi",
-      "~lsu|lsu>io_dccm_rd_data_lo",
-      "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
-      "~lsu|lsu>io_dec_tlu_core_ecc_disable"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~lsu|lsu>io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy",
-    "sources":[
-      "~lsu|lsu>io_axi_ar_ready",
-      "~lsu|lsu>io_axi_aw_ready",
-      "~lsu|lsu>io_axi_w_ready"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~lsu|lsu>io_dccm_wr_data_hi",
-    "sources":[
-      "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
-      "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
-      "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
-      "~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
-      "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
-      "~lsu|lsu>io_dec_lsu_valid_raw_d",
-      "~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
-      "~lsu|lsu>io_dec_lsu_offset_d",
-      "~lsu|lsu>io_lsu_p_bits_dword",
-      "~lsu|lsu>io_lsu_p_bits_half",
-      "~lsu|lsu>io_lsu_p_bits_word",
-      "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_wdata",
-      "~lsu|lsu>io_dec_tlu_force_halt",
-      "~lsu|lsu>io_lsu_pic_picm_rd_data",
-      "~lsu|lsu>io_dccm_rd_data_hi",
-      "~lsu|lsu>io_dccm_rd_data_lo",
-      "~lsu|lsu>io_dec_tlu_flush_lower_r",
-      "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
-      "~lsu|lsu>io_dec_tlu_core_ecc_disable"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~lsu|lsu>io_dccm_wr_addr_lo",
-    "sources":[
-      "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
-      "~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
-      "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
-      "~lsu|lsu>io_dec_lsu_valid_raw_d",
-      "~lsu|lsu>io_dec_lsu_offset_d",
-      "~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
-      "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
-      "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
-      "~lsu|lsu>io_lsu_p_bits_dword",
-      "~lsu|lsu>io_lsu_p_bits_half",
-      "~lsu|lsu>io_lsu_p_bits_word",
-      "~lsu|lsu>io_dec_tlu_force_halt",
-      "~lsu|lsu>io_lsu_pic_picm_rd_data",
-      "~lsu|lsu>io_dccm_rd_data_hi",
-      "~lsu|lsu>io_dccm_rd_data_lo",
-      "~lsu|lsu>io_dec_tlu_flush_lower_r",
-      "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
-      "~lsu|lsu>io_dec_tlu_core_ecc_disable"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~lsu|lsu>io_lsu_store_stall_any",
-    "sources":[
-      "~lsu|lsu>io_dec_lsu_valid_raw_d",
-      "~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
-      "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
-      "~lsu|lsu>io_dec_lsu_offset_d",
-      "~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
-      "~lsu|lsu>io_lsu_p_bits_dword",
-      "~lsu|lsu>io_lsu_p_bits_half",
-      "~lsu|lsu>io_lsu_p_bits_word",
-      "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
-      "~lsu|lsu>io_dec_tlu_flush_lower_r",
-      "~lsu|lsu>io_dec_tlu_force_halt",
-      "~lsu|lsu>io_lsu_pic_picm_rd_data",
-      "~lsu|lsu>io_dccm_rd_data_hi",
-      "~lsu|lsu>io_dccm_rd_data_lo",
-      "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
-      "~lsu|lsu>io_dec_tlu_core_ecc_disable"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~lsu|lsu>io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata",
-    "sources":[
-      "~lsu|lsu>io_lsu_pic_picm_rd_data",
-      "~lsu|lsu>io_dec_tlu_core_ecc_disable",
-      "~lsu|lsu>io_dccm_rd_data_hi",
-      "~lsu|lsu>io_dccm_rd_data_lo",
-      "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~lsu|lsu>io_dccm_wr_addr_hi",
-    "sources":[
-      "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
-      "~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
-      "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
-      "~lsu|lsu>io_dec_lsu_valid_raw_d",
-      "~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
-      "~lsu|lsu>io_dec_lsu_offset_d",
-      "~lsu|lsu>io_lsu_p_bits_dword",
-      "~lsu|lsu>io_lsu_p_bits_half",
-      "~lsu|lsu>io_lsu_p_bits_word",
-      "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
-      "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
-      "~lsu|lsu>io_dec_tlu_force_halt",
-      "~lsu|lsu>io_lsu_pic_picm_rd_data",
-      "~lsu|lsu>io_dccm_rd_data_hi",
-      "~lsu|lsu>io_dccm_rd_data_lo",
-      "~lsu|lsu>io_dec_tlu_flush_lower_r",
-      "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
-      "~lsu|lsu>io_dec_tlu_core_ecc_disable"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~lsu|lsu>io_lsu_fastint_stall_any",
-    "sources":[
-      "~lsu|lsu>io_dec_tlu_core_ecc_disable",
-      "~lsu|lsu>io_dccm_rd_data_hi",
-      "~lsu|lsu>io_dccm_rd_data_lo"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~lsu|lsu>io_dccm_rd_addr_hi",
-    "sources":[
-      "~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
-      "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
-      "~lsu|lsu>io_dec_lsu_valid_raw_d",
-      "~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
-      "~lsu|lsu>io_dec_lsu_offset_d",
-      "~lsu|lsu>io_lsu_p_bits_dword",
-      "~lsu|lsu>io_lsu_p_bits_half",
-      "~lsu|lsu>io_lsu_p_bits_word",
-      "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
-      "~lsu|lsu>io_dec_tlu_force_halt",
-      "~lsu|lsu>io_lsu_pic_picm_rd_data",
-      "~lsu|lsu>io_dccm_rd_data_hi",
-      "~lsu|lsu>io_dccm_rd_data_lo",
-      "~lsu|lsu>io_dec_tlu_flush_lower_r",
-      "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
-      "~lsu|lsu>io_dec_tlu_core_ecc_disable"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~lsu|lsu>io_lsu_result_m",
-    "sources":[
-      "~lsu|lsu>io_dec_tlu_force_halt",
-      "~lsu|lsu>io_lsu_pic_picm_rd_data",
-      "~lsu|lsu>io_dccm_rd_data_hi",
-      "~lsu|lsu>io_dccm_rd_data_lo",
-      "~lsu|lsu>io_dec_tlu_flush_lower_r",
-      "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
-      "~lsu|lsu>io_dec_tlu_core_ecc_disable"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~lsu|lsu>io_dccm_wr_data_lo",
-    "sources":[
-      "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
-      "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
-      "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
-      "~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
-      "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
-      "~lsu|lsu>io_dec_lsu_valid_raw_d",
-      "~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
-      "~lsu|lsu>io_dec_lsu_offset_d",
-      "~lsu|lsu>io_lsu_p_bits_dword",
-      "~lsu|lsu>io_lsu_p_bits_half",
-      "~lsu|lsu>io_lsu_p_bits_word",
-      "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_wdata",
-      "~lsu|lsu>io_dec_tlu_force_halt",
-      "~lsu|lsu>io_lsu_pic_picm_rd_data",
-      "~lsu|lsu>io_dccm_rd_data_hi",
-      "~lsu|lsu>io_dccm_rd_data_lo",
-      "~lsu|lsu>io_dec_tlu_flush_lower_r",
-      "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
-      "~lsu|lsu>io_dec_tlu_core_ecc_disable"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~lsu|lsu>io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned",
-    "sources":[
-      "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r"
+      "~lsu|lsu>io_lsu_pic_picm_rd_data"
     ]
   },
   {
@@ -323,18 +251,12 @@
       "~lsu|lsu>io_lsu_p_bits_dword",
       "~lsu|lsu>io_lsu_p_bits_half",
       "~lsu|lsu>io_lsu_p_bits_word",
-      "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
-      "~lsu|lsu>io_dec_tlu_force_halt",
-      "~lsu|lsu>io_lsu_pic_picm_rd_data",
-      "~lsu|lsu>io_dccm_rd_data_hi",
-      "~lsu|lsu>io_dccm_rd_data_lo",
-      "~lsu|lsu>io_dec_tlu_flush_lower_r",
-      "~lsu|lsu>io_dec_tlu_core_ecc_disable"
+      "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz"
     ]
   },
   {
     "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~lsu|lsu>io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error",
+    "sink":"~lsu|lsu>io_lsu_result_corr_r",
     "sources":[
       "~lsu|lsu>io_dec_tlu_core_ecc_disable",
       "~lsu|lsu>io_dccm_rd_data_hi",
@@ -343,58 +265,50 @@
   },
   {
     "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~lsu|lsu>io_lsu_pic_picm_rden",
+    "sink":"~lsu|lsu>io_lsu_store_stall_any",
     "sources":[
+      "~lsu|lsu>io_dec_lsu_valid_raw_d",
+      "~lsu|lsu>io_dec_tlu_flush_lower_r",
       "~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
       "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
-      "~lsu|lsu>io_dec_lsu_valid_raw_d",
-      "~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
       "~lsu|lsu>io_dec_lsu_offset_d",
-      "~lsu|lsu>io_lsu_p_bits_dword",
-      "~lsu|lsu>io_lsu_p_bits_half",
-      "~lsu|lsu>io_lsu_p_bits_word",
-      "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
+      "~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu|lsu>io_lsu_fastint_stall_any",
+    "sources":[
+      "~lsu|lsu>io_dec_tlu_core_ecc_disable",
+      "~lsu|lsu>io_dccm_rd_data_hi",
+      "~lsu|lsu>io_dccm_rd_data_lo"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu|lsu>io_lsu_pic_picm_wraddr",
+    "sources":[
+      "~lsu|lsu>io_lsu_dma_dma_dccm_ctl_dma_mem_addr",
       "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
-      "~lsu|lsu>io_lsu_p_valid",
-      "~lsu|lsu>io_dec_tlu_flush_lower_r",
-      "~lsu|lsu>io_lsu_p_bits_fast_int",
-      "~lsu|lsu>io_lsu_p_bits_load",
       "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
-      "~lsu|lsu>io_dec_tlu_force_halt",
-      "~lsu|lsu>io_lsu_pic_picm_rd_data",
-      "~lsu|lsu>io_dccm_rd_data_hi",
-      "~lsu|lsu>io_dccm_rd_data_lo",
-      "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
-      "~lsu|lsu>io_dec_tlu_core_ecc_disable"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~lsu|lsu>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r",
-    "sources":[
-      "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~lsu|lsu>io_lsu_load_stall_any",
-    "sources":[
-      "~lsu|lsu>io_dec_lsu_valid_raw_d",
       "~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
       "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
-      "~lsu|lsu>io_dec_lsu_offset_d",
+      "~lsu|lsu>io_dec_lsu_valid_raw_d",
       "~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
+      "~lsu|lsu>io_dec_lsu_offset_d",
       "~lsu|lsu>io_lsu_p_bits_dword",
       "~lsu|lsu>io_lsu_p_bits_half",
       "~lsu|lsu>io_lsu_p_bits_word",
-      "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
-      "~lsu|lsu>io_dec_tlu_flush_lower_r",
-      "~lsu|lsu>io_dec_tlu_force_halt",
-      "~lsu|lsu>io_lsu_pic_picm_rd_data",
+      "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu|lsu>io_lsu_fir_error",
+    "sources":[
+      "~lsu|lsu>io_dec_tlu_core_ecc_disable",
       "~lsu|lsu>io_dccm_rd_data_hi",
-      "~lsu|lsu>io_dccm_rd_data_lo",
-      "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
-      "~lsu|lsu>io_dec_tlu_core_ecc_disable"
+      "~lsu|lsu>io_dccm_rd_data_lo"
     ]
   },
   {
@@ -416,40 +330,13 @@
       "~lsu|lsu>io_lsu_p_bits_fast_int",
       "~lsu|lsu>io_lsu_p_bits_load",
       "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
-      "~lsu|lsu>io_lsu_p_bits_store",
-      "~lsu|lsu>io_dec_tlu_force_halt",
-      "~lsu|lsu>io_lsu_pic_picm_rd_data",
-      "~lsu|lsu>io_dccm_rd_data_hi",
-      "~lsu|lsu>io_dccm_rd_data_lo",
-      "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
-      "~lsu|lsu>io_dec_tlu_core_ecc_disable"
+      "~lsu|lsu>io_lsu_p_bits_store"
     ]
   },
   {
     "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~lsu|lsu>io_dccm_rd_addr_lo",
+    "sink":"~lsu|lsu>io_lsu_pic_picm_mken",
     "sources":[
-      "~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
-      "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
-      "~lsu|lsu>io_dec_lsu_valid_raw_d",
-      "~lsu|lsu>io_dec_lsu_offset_d",
-      "~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
-      "~lsu|lsu>io_dec_tlu_force_halt",
-      "~lsu|lsu>io_lsu_pic_picm_rd_data",
-      "~lsu|lsu>io_dccm_rd_data_hi",
-      "~lsu|lsu>io_dccm_rd_data_lo",
-      "~lsu|lsu>io_dec_tlu_flush_lower_r",
-      "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
-      "~lsu|lsu>io_dec_tlu_core_ecc_disable"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~lsu|lsu>io_lsu_pic_picm_wr_data",
-    "sources":[
-      "~lsu|lsu>io_lsu_dma_dma_dccm_ctl_dma_mem_wdata",
-      "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
-      "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
       "~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
       "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
       "~lsu|lsu>io_dec_lsu_valid_raw_d",
@@ -459,24 +346,72 @@
       "~lsu|lsu>io_lsu_p_bits_half",
       "~lsu|lsu>io_lsu_p_bits_word",
       "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
+      "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
       "~lsu|lsu>io_lsu_p_valid",
       "~lsu|lsu>io_dec_tlu_flush_lower_r",
       "~lsu|lsu>io_lsu_p_bits_fast_int",
-      "~lsu|lsu>io_lsu_p_bits_load",
       "~lsu|lsu>io_lsu_p_bits_store",
-      "~lsu|lsu>io_dec_tlu_force_halt",
-      "~lsu|lsu>io_lsu_pic_picm_rd_data",
-      "~lsu|lsu>io_dccm_rd_data_hi",
-      "~lsu|lsu>io_dccm_rd_data_lo",
-      "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
-      "~lsu|lsu>io_dec_tlu_core_ecc_disable"
+      "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write"
     ]
   },
   {
     "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~lsu|lsu>io_lsu_pic_picm_wraddr",
+    "sink":"~lsu|lsu>io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned",
     "sources":[
-      "~lsu|lsu>io_lsu_dma_dma_dccm_ctl_dma_mem_addr",
+      "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu|lsu>io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error",
+    "sources":[
+      "~lsu|lsu>io_dec_tlu_core_ecc_disable",
+      "~lsu|lsu>io_dccm_rd_data_hi",
+      "~lsu|lsu>io_dccm_rd_data_lo"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu|lsu>io_lsu_error_pkt_r_bits_single_ecc_error",
+    "sources":[
+      "~lsu|lsu>io_dec_tlu_core_ecc_disable",
+      "~lsu|lsu>io_dccm_rd_data_hi",
+      "~lsu|lsu>io_dccm_rd_data_lo"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu|lsu>io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r",
+    "sources":[
+      "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu|lsu>io_lsu_error_pkt_r_valid",
+    "sources":[
+      "~lsu|lsu>io_dec_tlu_core_ecc_disable",
+      "~lsu|lsu>io_dccm_rd_data_hi",
+      "~lsu|lsu>io_dccm_rd_data_lo"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu|lsu>io_lsu_load_stall_any",
+    "sources":[
+      "~lsu|lsu>io_dec_lsu_valid_raw_d",
+      "~lsu|lsu>io_dec_tlu_flush_lower_r",
+      "~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
+      "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
+      "~lsu|lsu>io_dec_lsu_offset_d",
+      "~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu|lsu>io_dccm_wr_data_lo",
+    "sources":[
+      "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
       "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_dccm_req",
       "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_write",
       "~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
@@ -487,32 +422,16 @@
       "~lsu|lsu>io_lsu_p_bits_dword",
       "~lsu|lsu>io_lsu_p_bits_half",
       "~lsu|lsu>io_lsu_p_bits_word",
-      "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_sz",
-      "~lsu|lsu>io_dec_tlu_force_halt",
-      "~lsu|lsu>io_lsu_pic_picm_rd_data",
-      "~lsu|lsu>io_dccm_rd_data_hi",
-      "~lsu|lsu>io_dccm_rd_data_lo",
-      "~lsu|lsu>io_dec_tlu_flush_lower_r",
-      "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
-      "~lsu|lsu>io_dec_tlu_core_ecc_disable"
+      "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_wdata"
     ]
   },
   {
     "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~lsu|lsu>io_lsu_pic_picm_rdaddr",
+    "sink":"~lsu|lsu>io_lsu_error_pkt_r_bits_mscause",
     "sources":[
-      "~lsu|lsu>io_lsu_exu_exu_lsu_rs1_d",
-      "~lsu|lsu>io_lsu_dma_dma_lsc_ctl_dma_mem_addr",
-      "~lsu|lsu>io_dec_lsu_valid_raw_d",
-      "~lsu|lsu>io_dec_lsu_offset_d",
-      "~lsu|lsu>io_lsu_p_bits_load_ldst_bypass_d",
-      "~lsu|lsu>io_dec_tlu_force_halt",
-      "~lsu|lsu>io_lsu_pic_picm_rd_data",
+      "~lsu|lsu>io_dec_tlu_core_ecc_disable",
       "~lsu|lsu>io_dccm_rd_data_hi",
-      "~lsu|lsu>io_dccm_rd_data_lo",
-      "~lsu|lsu>io_dec_tlu_flush_lower_r",
-      "~lsu|lsu>io_dec_tlu_i0_kill_writeb_r",
-      "~lsu|lsu>io_dec_tlu_core_ecc_disable"
+      "~lsu|lsu>io_dccm_rd_data_lo"
     ]
   },
   {
diff --git a/lsu.fir b/lsu.fir
index eeee4b26..e57932b3 100644
--- a/lsu.fir
+++ b/lsu.fir
@@ -3,39 +3,39 @@ circuit lsu :
   module lsu_addrcheck : 
     input clock : Clock
     input reset : AsyncReset
-    output io : {flip lsu_c2_m_clk : Clock, flip start_addr_d : UInt<32>, flip end_addr_d : UInt<32>, flip lsu_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip dec_tlu_mrac_ff : UInt<32>, flip rs1_region_d : UInt<4>, flip rs1_d : UInt<32>, is_sideeffects_m : UInt<1>, addr_in_dccm_d : UInt<1>, addr_in_pic_d : UInt<1>, addr_external_d : UInt<1>, access_fault_d : UInt<1>, misaligned_fault_d : UInt<1>, exc_mscause_d : UInt<4>, fir_dccm_access_error_d : UInt<1>, fir_nondccm_access_error_d : UInt<1>, flip scan_mode : UInt<1>}
+    output io : {flip lsu_c2_m_clk : Clock, flip start_addr_d : UInt<32>, flip end_addr_d : UInt<32>, flip lsu_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip dec_tlu_mrac_ff : UInt<32>, flip rs1_region_d : UInt<4>, flip rs1_d : UInt<32>, is_sideeffects_m : UInt<1>, addr_in_dccm_d : UInt<1>, addr_in_pic_d : UInt<1>, addr_external_d : UInt<1>, access_fault_d : UInt<1>, misaligned_fault_d : UInt<1>, exc_mscause_d : UInt<4>, fir_dccm_access_error_d : UInt<1>, fir_nondccm_access_error_d : UInt<1>, flip scan_mode : UInt<1>}
     
-    node _T = bits(io.start_addr_d, 31, 28) @[lib.scala 356:27]
-    node start_addr_in_dccm_region_d = eq(_T, UInt<4>("h0f")) @[lib.scala 356:49]
-    wire start_addr_in_dccm_d : UInt<1> @[lib.scala 357:26]
-    node _T_1 = bits(io.start_addr_d, 31, 16) @[lib.scala 361:24]
-    node _T_2 = eq(_T_1, UInt<16>("h0f004")) @[lib.scala 361:39]
-    start_addr_in_dccm_d <= _T_2 @[lib.scala 361:16]
-    node _T_3 = bits(io.end_addr_d, 31, 28) @[lib.scala 356:27]
-    node end_addr_in_dccm_region_d = eq(_T_3, UInt<4>("h0f")) @[lib.scala 356:49]
-    wire end_addr_in_dccm_d : UInt<1> @[lib.scala 357:26]
-    node _T_4 = bits(io.end_addr_d, 31, 16) @[lib.scala 361:24]
-    node _T_5 = eq(_T_4, UInt<16>("h0f004")) @[lib.scala 361:39]
-    end_addr_in_dccm_d <= _T_5 @[lib.scala 361:16]
+    node _T = bits(io.start_addr_d, 31, 28) @[lib.scala 365:27]
+    node start_addr_in_dccm_region_d = eq(_T, UInt<4>("h0f")) @[lib.scala 365:49]
+    wire start_addr_in_dccm_d : UInt<1> @[lib.scala 366:26]
+    node _T_1 = bits(io.start_addr_d, 31, 16) @[lib.scala 370:24]
+    node _T_2 = eq(_T_1, UInt<16>("h0f004")) @[lib.scala 370:39]
+    start_addr_in_dccm_d <= _T_2 @[lib.scala 370:16]
+    node _T_3 = bits(io.end_addr_d, 31, 28) @[lib.scala 365:27]
+    node end_addr_in_dccm_region_d = eq(_T_3, UInt<4>("h0f")) @[lib.scala 365:49]
+    wire end_addr_in_dccm_d : UInt<1> @[lib.scala 366:26]
+    node _T_4 = bits(io.end_addr_d, 31, 16) @[lib.scala 370:24]
+    node _T_5 = eq(_T_4, UInt<16>("h0f004")) @[lib.scala 370:39]
+    end_addr_in_dccm_d <= _T_5 @[lib.scala 370:16]
     wire addr_in_iccm : UInt<1>
     addr_in_iccm <= UInt<1>("h00")
     node _T_6 = bits(io.start_addr_d, 31, 28) @[lsu_addrcheck.scala 42:37]
     node _T_7 = eq(_T_6, UInt<4>("h0e")) @[lsu_addrcheck.scala 42:45]
     addr_in_iccm <= _T_7 @[lsu_addrcheck.scala 42:18]
     node _T_8 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 50:89]
-    node _T_9 = bits(_T_8, 31, 28) @[lib.scala 356:27]
-    node start_addr_in_pic_region_d = eq(_T_9, UInt<4>("h0f")) @[lib.scala 356:49]
-    wire start_addr_in_pic_d : UInt<1> @[lib.scala 357:26]
-    node _T_10 = bits(_T_8, 31, 15) @[lib.scala 361:24]
-    node _T_11 = eq(_T_10, UInt<17>("h01e018")) @[lib.scala 361:39]
-    start_addr_in_pic_d <= _T_11 @[lib.scala 361:16]
+    node _T_9 = bits(_T_8, 31, 28) @[lib.scala 365:27]
+    node start_addr_in_pic_region_d = eq(_T_9, UInt<4>("h0f")) @[lib.scala 365:49]
+    wire start_addr_in_pic_d : UInt<1> @[lib.scala 366:26]
+    node _T_10 = bits(_T_8, 31, 15) @[lib.scala 370:24]
+    node _T_11 = eq(_T_10, UInt<17>("h01e018")) @[lib.scala 370:39]
+    start_addr_in_pic_d <= _T_11 @[lib.scala 370:16]
     node _T_12 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 52:83]
-    node _T_13 = bits(_T_12, 31, 28) @[lib.scala 356:27]
-    node end_addr_in_pic_region_d = eq(_T_13, UInt<4>("h0f")) @[lib.scala 356:49]
-    wire end_addr_in_pic_d : UInt<1> @[lib.scala 357:26]
-    node _T_14 = bits(_T_12, 31, 15) @[lib.scala 361:24]
-    node _T_15 = eq(_T_14, UInt<17>("h01e018")) @[lib.scala 361:39]
-    end_addr_in_pic_d <= _T_15 @[lib.scala 361:16]
+    node _T_13 = bits(_T_12, 31, 28) @[lib.scala 365:27]
+    node end_addr_in_pic_region_d = eq(_T_13, UInt<4>("h0f")) @[lib.scala 365:49]
+    wire end_addr_in_pic_d : UInt<1> @[lib.scala 366:26]
+    node _T_14 = bits(_T_12, 31, 15) @[lib.scala 370:24]
+    node _T_15 = eq(_T_14, UInt<17>("h01e018")) @[lib.scala 370:39]
+    end_addr_in_pic_d <= _T_15 @[lib.scala 370:16]
     node start_addr_dccm_or_pic = or(start_addr_in_dccm_region_d, start_addr_in_pic_region_d) @[lsu_addrcheck.scala 54:60]
     node _T_16 = bits(io.rs1_region_d, 3, 0) @[lsu_addrcheck.scala 55:49]
     node _T_17 = eq(_T_16, UInt<4>("h0f")) @[lsu_addrcheck.scala 55:55]
@@ -323,6 +323,607 @@ circuit lsu :
     clkhdr.EN <= io.en @[lib.scala 337:18]
     clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
     
+  module lsu_lsc_ctl : 
+    input clock : Clock
+    input reset : AsyncReset
+    output io : {flip clk_override : UInt<1>, flip lsu_c1_m_clk : Clock, flip lsu_c1_r_clk : Clock, flip lsu_c2_m_clk : Clock, flip lsu_c2_r_clk : Clock, flip lsu_store_c1_m_clk : Clock, flip lsu_ld_data_r : UInt<32>, flip lsu_ld_data_corr_r : UInt<32>, flip lsu_single_ecc_error_r : UInt<1>, flip lsu_double_ecc_error_r : UInt<1>, flip lsu_ld_data_m : UInt<32>, flip lsu_single_ecc_error_m : UInt<1>, flip lsu_double_ecc_error_m : UInt<1>, flip flush_m_up : UInt<1>, flip flush_r : UInt<1>, flip ldst_dual_d : UInt<1>, flip ldst_dual_m : UInt<1>, flip ldst_dual_r : UInt<1>, lsu_exu : {flip exu_lsu_rs1_d : UInt<32>, flip exu_lsu_rs2_d : UInt<32>}, flip lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip dec_lsu_valid_raw_d : UInt<1>, flip dec_lsu_offset_d : UInt<12>, flip picm_mask_data_m : UInt<32>, flip bus_read_data_m : UInt<32>, lsu_result_m : UInt<32>, lsu_result_corr_r : UInt<32>, lsu_addr_d : UInt<32>, lsu_addr_m : UInt<32>, lsu_addr_r : UInt<32>, end_addr_d : UInt<32>, end_addr_m : UInt<32>, end_addr_r : UInt<32>, store_data_m : UInt<32>, flip dec_tlu_mrac_ff : UInt<32>, lsu_exc_m : UInt<1>, is_sideeffects_m : UInt<1>, lsu_commit_r : UInt<1>, lsu_single_ecc_error_incr : UInt<1>, lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, lsu_fir_addr : UInt<31>, lsu_fir_error : UInt<2>, addr_in_dccm_d : UInt<1>, addr_in_dccm_m : UInt<1>, addr_in_dccm_r : UInt<1>, addr_in_pic_d : UInt<1>, addr_in_pic_m : UInt<1>, addr_in_pic_r : UInt<1>, addr_external_m : UInt<1>, dma_lsc_ctl : {flip dma_dccm_req : UInt<1>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_write : UInt<1>, flip dma_mem_wdata : UInt<64>}, lsu_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, lsu_pkt_r : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip scan_mode : UInt<1>}
+    
+    wire end_addr_pre_m : UInt<29>
+    end_addr_pre_m <= UInt<29>("h00")
+    wire end_addr_pre_r : UInt<29>
+    end_addr_pre_r <= UInt<29>("h00")
+    wire dma_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 93:29]
+    wire lsu_pkt_m_in : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 94:29]
+    wire lsu_pkt_r_in : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 95:29]
+    wire lsu_error_pkt_m : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}} @[lsu_lsc_ctl.scala 96:29]
+    wire _T : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}} @[lsu_lsc_ctl.scala 97:35]
+    _T.bits.addr <= UInt<32>("h00") @[lsu_lsc_ctl.scala 97:35]
+    _T.bits.mscause <= UInt<4>("h00") @[lsu_lsc_ctl.scala 97:35]
+    _T.bits.exc_type <= UInt<1>("h00") @[lsu_lsc_ctl.scala 97:35]
+    _T.bits.inst_type <= UInt<1>("h00") @[lsu_lsc_ctl.scala 97:35]
+    _T.bits.single_ecc_error <= UInt<1>("h00") @[lsu_lsc_ctl.scala 97:35]
+    _T.valid <= UInt<1>("h00") @[lsu_lsc_ctl.scala 97:35]
+    lsu_error_pkt_m.bits.addr <= _T.bits.addr @[lsu_lsc_ctl.scala 97:20]
+    lsu_error_pkt_m.bits.mscause <= _T.bits.mscause @[lsu_lsc_ctl.scala 97:20]
+    lsu_error_pkt_m.bits.exc_type <= _T.bits.exc_type @[lsu_lsc_ctl.scala 97:20]
+    lsu_error_pkt_m.bits.inst_type <= _T.bits.inst_type @[lsu_lsc_ctl.scala 97:20]
+    lsu_error_pkt_m.bits.single_ecc_error <= _T.bits.single_ecc_error @[lsu_lsc_ctl.scala 97:20]
+    lsu_error_pkt_m.valid <= _T.valid @[lsu_lsc_ctl.scala 97:20]
+    node _T_1 = bits(io.dec_lsu_valid_raw_d, 0, 0) @[lsu_lsc_ctl.scala 99:52]
+    node lsu_rs1_d = mux(_T_1, io.lsu_exu.exu_lsu_rs1_d, io.dma_lsc_ctl.dma_mem_addr) @[lsu_lsc_ctl.scala 99:28]
+    node _T_2 = bits(io.dec_lsu_offset_d, 11, 0) @[lsu_lsc_ctl.scala 100:44]
+    node _T_3 = bits(io.dec_lsu_valid_raw_d, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4 = mux(_T_3, UInt<12>("h0fff"), UInt<12>("h00")) @[Bitwise.scala 72:12]
+    node lsu_offset_d = and(_T_2, _T_4) @[lsu_lsc_ctl.scala 100:51]
+    node _T_5 = bits(io.lsu_pkt_d.bits.load_ldst_bypass_d, 0, 0) @[lsu_lsc_ctl.scala 103:66]
+    node rs1_d = mux(_T_5, io.lsu_result_m, lsu_rs1_d) @[lsu_lsc_ctl.scala 103:28]
+    node _T_6 = bits(rs1_d, 11, 0) @[lib.scala 92:31]
+    node _T_7 = cat(UInt<1>("h00"), _T_6) @[Cat.scala 29:58]
+    node _T_8 = bits(lsu_offset_d, 11, 0) @[lib.scala 92:60]
+    node _T_9 = cat(UInt<1>("h00"), _T_8) @[Cat.scala 29:58]
+    node _T_10 = add(_T_7, _T_9) @[lib.scala 92:39]
+    node _T_11 = tail(_T_10, 1) @[lib.scala 92:39]
+    node _T_12 = bits(lsu_offset_d, 11, 11) @[lib.scala 93:41]
+    node _T_13 = bits(_T_11, 12, 12) @[lib.scala 93:50]
+    node _T_14 = xor(_T_12, _T_13) @[lib.scala 93:46]
+    node _T_15 = not(_T_14) @[lib.scala 93:33]
+    node _T_16 = bits(_T_15, 0, 0) @[Bitwise.scala 72:15]
+    node _T_17 = mux(_T_16, UInt<20>("h0fffff"), UInt<20>("h00")) @[Bitwise.scala 72:12]
+    node _T_18 = bits(rs1_d, 31, 12) @[lib.scala 93:63]
+    node _T_19 = and(_T_17, _T_18) @[lib.scala 93:58]
+    node _T_20 = bits(lsu_offset_d, 11, 11) @[lib.scala 94:25]
+    node _T_21 = not(_T_20) @[lib.scala 94:18]
+    node _T_22 = bits(_T_11, 12, 12) @[lib.scala 94:34]
+    node _T_23 = and(_T_21, _T_22) @[lib.scala 94:30]
+    node _T_24 = bits(_T_23, 0, 0) @[Bitwise.scala 72:15]
+    node _T_25 = mux(_T_24, UInt<20>("h0fffff"), UInt<20>("h00")) @[Bitwise.scala 72:12]
+    node _T_26 = bits(rs1_d, 31, 12) @[lib.scala 94:47]
+    node _T_27 = add(_T_26, UInt<1>("h01")) @[lib.scala 94:54]
+    node _T_28 = tail(_T_27, 1) @[lib.scala 94:54]
+    node _T_29 = and(_T_25, _T_28) @[lib.scala 94:41]
+    node _T_30 = or(_T_19, _T_29) @[lib.scala 93:72]
+    node _T_31 = bits(lsu_offset_d, 11, 11) @[lib.scala 95:24]
+    node _T_32 = bits(_T_11, 12, 12) @[lib.scala 95:34]
+    node _T_33 = not(_T_32) @[lib.scala 95:31]
+    node _T_34 = and(_T_31, _T_33) @[lib.scala 95:29]
+    node _T_35 = bits(_T_34, 0, 0) @[Bitwise.scala 72:15]
+    node _T_36 = mux(_T_35, UInt<20>("h0fffff"), UInt<20>("h00")) @[Bitwise.scala 72:12]
+    node _T_37 = bits(rs1_d, 31, 12) @[lib.scala 95:47]
+    node _T_38 = sub(_T_37, UInt<1>("h01")) @[lib.scala 95:54]
+    node _T_39 = tail(_T_38, 1) @[lib.scala 95:54]
+    node _T_40 = and(_T_36, _T_39) @[lib.scala 95:41]
+    node _T_41 = or(_T_30, _T_40) @[lib.scala 94:61]
+    node _T_42 = bits(_T_11, 11, 0) @[lib.scala 96:22]
+    node full_addr_d = cat(_T_41, _T_42) @[Cat.scala 29:58]
+    node _T_43 = bits(io.lsu_pkt_d.bits.half, 0, 0) @[Bitwise.scala 72:15]
+    node _T_44 = mux(_T_43, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
+    node _T_45 = and(_T_44, UInt<3>("h01")) @[lsu_lsc_ctl.scala 108:58]
+    node _T_46 = bits(io.lsu_pkt_d.bits.word, 0, 0) @[Bitwise.scala 72:15]
+    node _T_47 = mux(_T_46, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
+    node _T_48 = and(_T_47, UInt<3>("h03")) @[lsu_lsc_ctl.scala 109:40]
+    node _T_49 = or(_T_45, _T_48) @[lsu_lsc_ctl.scala 108:70]
+    node _T_50 = bits(io.lsu_pkt_d.bits.dword, 0, 0) @[Bitwise.scala 72:15]
+    node _T_51 = mux(_T_50, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
+    node _T_52 = and(_T_51, UInt<3>("h07")) @[lsu_lsc_ctl.scala 110:40]
+    node addr_offset_d = or(_T_49, _T_52) @[lsu_lsc_ctl.scala 109:52]
+    node _T_53 = bits(lsu_offset_d, 11, 11) @[lsu_lsc_ctl.scala 112:39]
+    node _T_54 = bits(lsu_offset_d, 11, 0) @[lsu_lsc_ctl.scala 112:52]
+    node _T_55 = cat(_T_53, _T_54) @[Cat.scala 29:58]
+    node _T_56 = mux(UInt<1>("h00"), UInt<9>("h01ff"), UInt<9>("h00")) @[Bitwise.scala 72:12]
+    node _T_57 = bits(addr_offset_d, 2, 0) @[lsu_lsc_ctl.scala 112:91]
+    node _T_58 = cat(_T_56, _T_57) @[Cat.scala 29:58]
+    node _T_59 = add(_T_55, _T_58) @[lsu_lsc_ctl.scala 112:60]
+    node end_addr_offset_d = tail(_T_59, 1) @[lsu_lsc_ctl.scala 112:60]
+    node _T_60 = bits(rs1_d, 31, 0) @[lsu_lsc_ctl.scala 113:32]
+    node _T_61 = bits(end_addr_offset_d, 12, 12) @[lsu_lsc_ctl.scala 113:70]
+    node _T_62 = bits(_T_61, 0, 0) @[Bitwise.scala 72:15]
+    node _T_63 = mux(_T_62, UInt<19>("h07ffff"), UInt<19>("h00")) @[Bitwise.scala 72:12]
+    node _T_64 = bits(end_addr_offset_d, 12, 0) @[lsu_lsc_ctl.scala 113:93]
+    node _T_65 = cat(_T_63, _T_64) @[Cat.scala 29:58]
+    node _T_66 = add(_T_60, _T_65) @[lsu_lsc_ctl.scala 113:39]
+    node full_end_addr_d = tail(_T_66, 1) @[lsu_lsc_ctl.scala 113:39]
+    io.end_addr_d <= full_end_addr_d @[lsu_lsc_ctl.scala 114:24]
+    inst addrcheck of lsu_addrcheck @[lsu_lsc_ctl.scala 117:25]
+    addrcheck.clock <= clock
+    addrcheck.reset <= reset
+    addrcheck.io.lsu_c2_m_clk <= io.lsu_c2_m_clk @[lsu_lsc_ctl.scala 119:42]
+    addrcheck.io.start_addr_d <= full_addr_d @[lsu_lsc_ctl.scala 121:42]
+    addrcheck.io.end_addr_d <= full_end_addr_d @[lsu_lsc_ctl.scala 122:42]
+    addrcheck.io.lsu_pkt_d.bits.store_data_bypass_m <= io.lsu_pkt_d.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 123:42]
+    addrcheck.io.lsu_pkt_d.bits.load_ldst_bypass_d <= io.lsu_pkt_d.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 123:42]
+    addrcheck.io.lsu_pkt_d.bits.store_data_bypass_d <= io.lsu_pkt_d.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 123:42]
+    addrcheck.io.lsu_pkt_d.bits.dma <= io.lsu_pkt_d.bits.dma @[lsu_lsc_ctl.scala 123:42]
+    addrcheck.io.lsu_pkt_d.bits.unsign <= io.lsu_pkt_d.bits.unsign @[lsu_lsc_ctl.scala 123:42]
+    addrcheck.io.lsu_pkt_d.bits.store <= io.lsu_pkt_d.bits.store @[lsu_lsc_ctl.scala 123:42]
+    addrcheck.io.lsu_pkt_d.bits.load <= io.lsu_pkt_d.bits.load @[lsu_lsc_ctl.scala 123:42]
+    addrcheck.io.lsu_pkt_d.bits.dword <= io.lsu_pkt_d.bits.dword @[lsu_lsc_ctl.scala 123:42]
+    addrcheck.io.lsu_pkt_d.bits.word <= io.lsu_pkt_d.bits.word @[lsu_lsc_ctl.scala 123:42]
+    addrcheck.io.lsu_pkt_d.bits.half <= io.lsu_pkt_d.bits.half @[lsu_lsc_ctl.scala 123:42]
+    addrcheck.io.lsu_pkt_d.bits.by <= io.lsu_pkt_d.bits.by @[lsu_lsc_ctl.scala 123:42]
+    addrcheck.io.lsu_pkt_d.bits.stack <= io.lsu_pkt_d.bits.stack @[lsu_lsc_ctl.scala 123:42]
+    addrcheck.io.lsu_pkt_d.bits.fast_int <= io.lsu_pkt_d.bits.fast_int @[lsu_lsc_ctl.scala 123:42]
+    addrcheck.io.lsu_pkt_d.valid <= io.lsu_pkt_d.valid @[lsu_lsc_ctl.scala 123:42]
+    addrcheck.io.dec_tlu_mrac_ff <= io.dec_tlu_mrac_ff @[lsu_lsc_ctl.scala 124:42]
+    node _T_67 = bits(rs1_d, 31, 28) @[lsu_lsc_ctl.scala 125:50]
+    addrcheck.io.rs1_region_d <= _T_67 @[lsu_lsc_ctl.scala 125:42]
+    addrcheck.io.rs1_d <= rs1_d @[lsu_lsc_ctl.scala 126:42]
+    io.is_sideeffects_m <= addrcheck.io.is_sideeffects_m @[lsu_lsc_ctl.scala 127:42]
+    io.addr_in_dccm_d <= addrcheck.io.addr_in_dccm_d @[lsu_lsc_ctl.scala 128:42]
+    io.addr_in_pic_d <= addrcheck.io.addr_in_pic_d @[lsu_lsc_ctl.scala 129:42]
+    addrcheck.io.scan_mode <= io.scan_mode @[lsu_lsc_ctl.scala 136:42]
+    wire exc_mscause_r : UInt<4>
+    exc_mscause_r <= UInt<4>("h00")
+    wire fir_dccm_access_error_r : UInt<1>
+    fir_dccm_access_error_r <= UInt<1>("h00")
+    wire fir_nondccm_access_error_r : UInt<1>
+    fir_nondccm_access_error_r <= UInt<1>("h00")
+    wire access_fault_r : UInt<1>
+    access_fault_r <= UInt<1>("h00")
+    wire misaligned_fault_r : UInt<1>
+    misaligned_fault_r <= UInt<1>("h00")
+    wire lsu_fir_error_m : UInt<2>
+    lsu_fir_error_m <= UInt<2>("h00")
+    wire fir_dccm_access_error_m : UInt<1>
+    fir_dccm_access_error_m <= UInt<1>("h00")
+    wire fir_nondccm_access_error_m : UInt<1>
+    fir_nondccm_access_error_m <= UInt<1>("h00")
+    reg access_fault_m : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 148:75]
+    access_fault_m <= addrcheck.io.access_fault_d @[lsu_lsc_ctl.scala 148:75]
+    reg misaligned_fault_m : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 149:75]
+    misaligned_fault_m <= addrcheck.io.misaligned_fault_d @[lsu_lsc_ctl.scala 149:75]
+    reg exc_mscause_m : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 150:75]
+    exc_mscause_m <= addrcheck.io.exc_mscause_d @[lsu_lsc_ctl.scala 150:75]
+    reg _T_68 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 151:75]
+    _T_68 <= addrcheck.io.fir_dccm_access_error_d @[lsu_lsc_ctl.scala 151:75]
+    fir_dccm_access_error_m <= _T_68 @[lsu_lsc_ctl.scala 151:38]
+    reg _T_69 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 152:75]
+    _T_69 <= addrcheck.io.fir_nondccm_access_error_d @[lsu_lsc_ctl.scala 152:75]
+    fir_nondccm_access_error_m <= _T_69 @[lsu_lsc_ctl.scala 152:38]
+    node _T_70 = or(access_fault_m, misaligned_fault_m) @[lsu_lsc_ctl.scala 154:34]
+    io.lsu_exc_m <= _T_70 @[lsu_lsc_ctl.scala 154:16]
+    node _T_71 = eq(io.lsu_double_ecc_error_r, UInt<1>("h00")) @[lsu_lsc_ctl.scala 155:64]
+    node _T_72 = and(io.lsu_single_ecc_error_r, _T_71) @[lsu_lsc_ctl.scala 155:62]
+    node _T_73 = or(io.lsu_commit_r, io.lsu_pkt_r.bits.dma) @[lsu_lsc_ctl.scala 155:111]
+    node _T_74 = and(_T_72, _T_73) @[lsu_lsc_ctl.scala 155:92]
+    node _T_75 = and(_T_74, io.lsu_pkt_r.valid) @[lsu_lsc_ctl.scala 155:136]
+    io.lsu_single_ecc_error_incr <= _T_75 @[lsu_lsc_ctl.scala 155:32]
+    node _T_76 = or(access_fault_r, misaligned_fault_r) @[lsu_lsc_ctl.scala 159:49]
+    node _T_77 = or(_T_76, io.lsu_double_ecc_error_r) @[lsu_lsc_ctl.scala 159:70]
+    node _T_78 = and(_T_77, io.lsu_pkt_r.valid) @[lsu_lsc_ctl.scala 159:99]
+    node _T_79 = eq(io.lsu_pkt_r.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 159:122]
+    node _T_80 = and(_T_78, _T_79) @[lsu_lsc_ctl.scala 159:120]
+    node _T_81 = eq(io.lsu_pkt_r.bits.fast_int, UInt<1>("h00")) @[lsu_lsc_ctl.scala 159:147]
+    node _T_82 = and(_T_80, _T_81) @[lsu_lsc_ctl.scala 159:145]
+    io.lsu_error_pkt_r.valid <= _T_82 @[lsu_lsc_ctl.scala 159:30]
+    node _T_83 = eq(io.lsu_error_pkt_r.valid, UInt<1>("h00")) @[lsu_lsc_ctl.scala 160:77]
+    node _T_84 = and(io.lsu_single_ecc_error_r, _T_83) @[lsu_lsc_ctl.scala 160:75]
+    node _T_85 = eq(io.lsu_pkt_r.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 160:105]
+    node _T_86 = and(_T_84, _T_85) @[lsu_lsc_ctl.scala 160:103]
+    io.lsu_error_pkt_r.bits.single_ecc_error <= _T_86 @[lsu_lsc_ctl.scala 160:46]
+    io.lsu_error_pkt_r.bits.inst_type <= io.lsu_pkt_r.bits.store @[lsu_lsc_ctl.scala 161:39]
+    node _T_87 = not(misaligned_fault_r) @[lsu_lsc_ctl.scala 162:42]
+    io.lsu_error_pkt_r.bits.exc_type <= _T_87 @[lsu_lsc_ctl.scala 162:39]
+    node _T_88 = eq(misaligned_fault_r, UInt<1>("h00")) @[lsu_lsc_ctl.scala 163:75]
+    node _T_89 = and(io.lsu_double_ecc_error_r, _T_88) @[lsu_lsc_ctl.scala 163:73]
+    node _T_90 = eq(access_fault_r, UInt<1>("h00")) @[lsu_lsc_ctl.scala 163:97]
+    node _T_91 = and(_T_89, _T_90) @[lsu_lsc_ctl.scala 163:95]
+    node _T_92 = bits(_T_91, 0, 0) @[lsu_lsc_ctl.scala 163:114]
+    node _T_93 = bits(exc_mscause_r, 3, 0) @[lsu_lsc_ctl.scala 163:144]
+    node _T_94 = mux(_T_92, UInt<4>("h01"), _T_93) @[lsu_lsc_ctl.scala 163:45]
+    io.lsu_error_pkt_r.bits.mscause <= _T_94 @[lsu_lsc_ctl.scala 163:39]
+    node _T_95 = bits(io.lsu_addr_r, 31, 0) @[lsu_lsc_ctl.scala 164:55]
+    io.lsu_error_pkt_r.bits.addr <= _T_95 @[lsu_lsc_ctl.scala 164:39]
+    node _T_96 = bits(fir_nondccm_access_error_r, 0, 0) @[lsu_lsc_ctl.scala 165:68]
+    node _T_97 = bits(fir_dccm_access_error_r, 0, 0) @[lsu_lsc_ctl.scala 165:113]
+    node _T_98 = and(io.lsu_pkt_r.bits.fast_int, io.lsu_double_ecc_error_r) @[lsu_lsc_ctl.scala 165:162]
+    node _T_99 = bits(_T_98, 0, 0) @[lsu_lsc_ctl.scala 165:191]
+    node _T_100 = mux(_T_99, UInt<2>("h01"), UInt<2>("h00")) @[lsu_lsc_ctl.scala 165:133]
+    node _T_101 = mux(_T_97, UInt<2>("h02"), _T_100) @[lsu_lsc_ctl.scala 165:88]
+    node _T_102 = mux(_T_96, UInt<2>("h03"), _T_101) @[lsu_lsc_ctl.scala 165:40]
+    io.lsu_fir_error <= _T_102 @[lsu_lsc_ctl.scala 165:34]
+    reg _T_103 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 167:71]
+    _T_103 <= access_fault_m @[lsu_lsc_ctl.scala 167:71]
+    access_fault_r <= _T_103 @[lsu_lsc_ctl.scala 167:34]
+    reg _T_104 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 168:71]
+    _T_104 <= exc_mscause_m @[lsu_lsc_ctl.scala 168:71]
+    exc_mscause_r <= _T_104 @[lsu_lsc_ctl.scala 168:34]
+    reg _T_105 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 169:71]
+    _T_105 <= fir_dccm_access_error_m @[lsu_lsc_ctl.scala 169:71]
+    fir_dccm_access_error_r <= _T_105 @[lsu_lsc_ctl.scala 169:34]
+    reg _T_106 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 170:71]
+    _T_106 <= fir_nondccm_access_error_m @[lsu_lsc_ctl.scala 170:71]
+    fir_nondccm_access_error_r <= _T_106 @[lsu_lsc_ctl.scala 170:34]
+    reg _T_107 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 171:71]
+    _T_107 <= misaligned_fault_m @[lsu_lsc_ctl.scala 171:71]
+    misaligned_fault_r <= _T_107 @[lsu_lsc_ctl.scala 171:34]
+    dma_pkt_d.bits.unsign <= UInt<1>("h00") @[lsu_lsc_ctl.scala 189:27]
+    dma_pkt_d.bits.stack <= UInt<1>("h00") @[lsu_lsc_ctl.scala 190:26]
+    dma_pkt_d.bits.fast_int <= UInt<1>("h00") @[lsu_lsc_ctl.scala 191:27]
+    dma_pkt_d.valid <= io.dma_lsc_ctl.dma_dccm_req @[lsu_lsc_ctl.scala 192:22]
+    dma_pkt_d.bits.dma <= UInt<1>("h01") @[lsu_lsc_ctl.scala 193:27]
+    dma_pkt_d.bits.store <= io.dma_lsc_ctl.dma_mem_write @[lsu_lsc_ctl.scala 194:27]
+    node _T_108 = not(io.dma_lsc_ctl.dma_mem_write) @[lsu_lsc_ctl.scala 195:30]
+    dma_pkt_d.bits.load <= _T_108 @[lsu_lsc_ctl.scala 195:27]
+    node _T_109 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 196:56]
+    node _T_110 = eq(_T_109, UInt<3>("h00")) @[lsu_lsc_ctl.scala 196:62]
+    dma_pkt_d.bits.by <= _T_110 @[lsu_lsc_ctl.scala 196:27]
+    node _T_111 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 197:56]
+    node _T_112 = eq(_T_111, UInt<3>("h01")) @[lsu_lsc_ctl.scala 197:62]
+    dma_pkt_d.bits.half <= _T_112 @[lsu_lsc_ctl.scala 197:27]
+    node _T_113 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 198:56]
+    node _T_114 = eq(_T_113, UInt<3>("h02")) @[lsu_lsc_ctl.scala 198:62]
+    dma_pkt_d.bits.word <= _T_114 @[lsu_lsc_ctl.scala 198:27]
+    node _T_115 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 199:56]
+    node _T_116 = eq(_T_115, UInt<3>("h03")) @[lsu_lsc_ctl.scala 199:62]
+    dma_pkt_d.bits.dword <= _T_116 @[lsu_lsc_ctl.scala 199:27]
+    dma_pkt_d.bits.store_data_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 200:39]
+    dma_pkt_d.bits.load_ldst_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 201:39]
+    dma_pkt_d.bits.store_data_bypass_m <= UInt<1>("h00") @[lsu_lsc_ctl.scala 202:39]
+    wire lsu_ld_datafn_r : UInt<32>
+    lsu_ld_datafn_r <= UInt<32>("h00")
+    wire lsu_ld_datafn_corr_r : UInt<32>
+    lsu_ld_datafn_corr_r <= UInt<32>("h00")
+    wire lsu_ld_datafn_m : UInt<32>
+    lsu_ld_datafn_m <= UInt<32>("h00")
+    node _T_117 = bits(io.dec_lsu_valid_raw_d, 0, 0) @[lsu_lsc_ctl.scala 208:50]
+    node _T_118 = mux(_T_117, io.lsu_p, dma_pkt_d) @[lsu_lsc_ctl.scala 208:26]
+    io.lsu_pkt_d.bits.store_data_bypass_m <= _T_118.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 208:20]
+    io.lsu_pkt_d.bits.load_ldst_bypass_d <= _T_118.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 208:20]
+    io.lsu_pkt_d.bits.store_data_bypass_d <= _T_118.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 208:20]
+    io.lsu_pkt_d.bits.dma <= _T_118.bits.dma @[lsu_lsc_ctl.scala 208:20]
+    io.lsu_pkt_d.bits.unsign <= _T_118.bits.unsign @[lsu_lsc_ctl.scala 208:20]
+    io.lsu_pkt_d.bits.store <= _T_118.bits.store @[lsu_lsc_ctl.scala 208:20]
+    io.lsu_pkt_d.bits.load <= _T_118.bits.load @[lsu_lsc_ctl.scala 208:20]
+    io.lsu_pkt_d.bits.dword <= _T_118.bits.dword @[lsu_lsc_ctl.scala 208:20]
+    io.lsu_pkt_d.bits.word <= _T_118.bits.word @[lsu_lsc_ctl.scala 208:20]
+    io.lsu_pkt_d.bits.half <= _T_118.bits.half @[lsu_lsc_ctl.scala 208:20]
+    io.lsu_pkt_d.bits.by <= _T_118.bits.by @[lsu_lsc_ctl.scala 208:20]
+    io.lsu_pkt_d.bits.stack <= _T_118.bits.stack @[lsu_lsc_ctl.scala 208:20]
+    io.lsu_pkt_d.bits.fast_int <= _T_118.bits.fast_int @[lsu_lsc_ctl.scala 208:20]
+    io.lsu_pkt_d.valid <= _T_118.valid @[lsu_lsc_ctl.scala 208:20]
+    lsu_pkt_m_in.bits.store_data_bypass_m <= io.lsu_pkt_d.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 209:20]
+    lsu_pkt_m_in.bits.load_ldst_bypass_d <= io.lsu_pkt_d.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 209:20]
+    lsu_pkt_m_in.bits.store_data_bypass_d <= io.lsu_pkt_d.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 209:20]
+    lsu_pkt_m_in.bits.dma <= io.lsu_pkt_d.bits.dma @[lsu_lsc_ctl.scala 209:20]
+    lsu_pkt_m_in.bits.unsign <= io.lsu_pkt_d.bits.unsign @[lsu_lsc_ctl.scala 209:20]
+    lsu_pkt_m_in.bits.store <= io.lsu_pkt_d.bits.store @[lsu_lsc_ctl.scala 209:20]
+    lsu_pkt_m_in.bits.load <= io.lsu_pkt_d.bits.load @[lsu_lsc_ctl.scala 209:20]
+    lsu_pkt_m_in.bits.dword <= io.lsu_pkt_d.bits.dword @[lsu_lsc_ctl.scala 209:20]
+    lsu_pkt_m_in.bits.word <= io.lsu_pkt_d.bits.word @[lsu_lsc_ctl.scala 209:20]
+    lsu_pkt_m_in.bits.half <= io.lsu_pkt_d.bits.half @[lsu_lsc_ctl.scala 209:20]
+    lsu_pkt_m_in.bits.by <= io.lsu_pkt_d.bits.by @[lsu_lsc_ctl.scala 209:20]
+    lsu_pkt_m_in.bits.stack <= io.lsu_pkt_d.bits.stack @[lsu_lsc_ctl.scala 209:20]
+    lsu_pkt_m_in.bits.fast_int <= io.lsu_pkt_d.bits.fast_int @[lsu_lsc_ctl.scala 209:20]
+    lsu_pkt_m_in.valid <= io.lsu_pkt_d.valid @[lsu_lsc_ctl.scala 209:20]
+    lsu_pkt_r_in.bits.store_data_bypass_m <= io.lsu_pkt_m.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 210:20]
+    lsu_pkt_r_in.bits.load_ldst_bypass_d <= io.lsu_pkt_m.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 210:20]
+    lsu_pkt_r_in.bits.store_data_bypass_d <= io.lsu_pkt_m.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 210:20]
+    lsu_pkt_r_in.bits.dma <= io.lsu_pkt_m.bits.dma @[lsu_lsc_ctl.scala 210:20]
+    lsu_pkt_r_in.bits.unsign <= io.lsu_pkt_m.bits.unsign @[lsu_lsc_ctl.scala 210:20]
+    lsu_pkt_r_in.bits.store <= io.lsu_pkt_m.bits.store @[lsu_lsc_ctl.scala 210:20]
+    lsu_pkt_r_in.bits.load <= io.lsu_pkt_m.bits.load @[lsu_lsc_ctl.scala 210:20]
+    lsu_pkt_r_in.bits.dword <= io.lsu_pkt_m.bits.dword @[lsu_lsc_ctl.scala 210:20]
+    lsu_pkt_r_in.bits.word <= io.lsu_pkt_m.bits.word @[lsu_lsc_ctl.scala 210:20]
+    lsu_pkt_r_in.bits.half <= io.lsu_pkt_m.bits.half @[lsu_lsc_ctl.scala 210:20]
+    lsu_pkt_r_in.bits.by <= io.lsu_pkt_m.bits.by @[lsu_lsc_ctl.scala 210:20]
+    lsu_pkt_r_in.bits.stack <= io.lsu_pkt_m.bits.stack @[lsu_lsc_ctl.scala 210:20]
+    lsu_pkt_r_in.bits.fast_int <= io.lsu_pkt_m.bits.fast_int @[lsu_lsc_ctl.scala 210:20]
+    lsu_pkt_r_in.valid <= io.lsu_pkt_m.valid @[lsu_lsc_ctl.scala 210:20]
+    node _T_119 = eq(io.lsu_p.bits.fast_int, UInt<1>("h00")) @[lsu_lsc_ctl.scala 212:64]
+    node _T_120 = and(io.flush_m_up, _T_119) @[lsu_lsc_ctl.scala 212:61]
+    node _T_121 = eq(_T_120, UInt<1>("h00")) @[lsu_lsc_ctl.scala 212:45]
+    node _T_122 = and(io.lsu_p.valid, _T_121) @[lsu_lsc_ctl.scala 212:43]
+    node _T_123 = or(_T_122, io.dma_lsc_ctl.dma_dccm_req) @[lsu_lsc_ctl.scala 212:90]
+    io.lsu_pkt_d.valid <= _T_123 @[lsu_lsc_ctl.scala 212:24]
+    node _T_124 = eq(io.lsu_pkt_d.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 213:68]
+    node _T_125 = and(io.flush_m_up, _T_124) @[lsu_lsc_ctl.scala 213:65]
+    node _T_126 = eq(_T_125, UInt<1>("h00")) @[lsu_lsc_ctl.scala 213:49]
+    node _T_127 = and(io.lsu_pkt_d.valid, _T_126) @[lsu_lsc_ctl.scala 213:47]
+    lsu_pkt_m_in.valid <= _T_127 @[lsu_lsc_ctl.scala 213:24]
+    node _T_128 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 214:68]
+    node _T_129 = and(io.flush_m_up, _T_128) @[lsu_lsc_ctl.scala 214:65]
+    node _T_130 = eq(_T_129, UInt<1>("h00")) @[lsu_lsc_ctl.scala 214:49]
+    node _T_131 = and(io.lsu_pkt_m.valid, _T_130) @[lsu_lsc_ctl.scala 214:47]
+    lsu_pkt_r_in.valid <= _T_131 @[lsu_lsc_ctl.scala 214:24]
+    wire _T_132 : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 216:91]
+    _T_132.bits.store_data_bypass_m <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91]
+    _T_132.bits.load_ldst_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91]
+    _T_132.bits.store_data_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91]
+    _T_132.bits.dma <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91]
+    _T_132.bits.unsign <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91]
+    _T_132.bits.store <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91]
+    _T_132.bits.load <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91]
+    _T_132.bits.dword <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91]
+    _T_132.bits.word <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91]
+    _T_132.bits.half <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91]
+    _T_132.bits.by <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91]
+    _T_132.bits.stack <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91]
+    _T_132.bits.fast_int <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91]
+    _T_132.valid <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91]
+    reg _T_133 : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, io.lsu_c1_m_clk with : (reset => (reset, _T_132)) @[lsu_lsc_ctl.scala 216:65]
+    _T_133.bits.store_data_bypass_m <= lsu_pkt_m_in.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 216:65]
+    _T_133.bits.load_ldst_bypass_d <= lsu_pkt_m_in.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 216:65]
+    _T_133.bits.store_data_bypass_d <= lsu_pkt_m_in.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 216:65]
+    _T_133.bits.dma <= lsu_pkt_m_in.bits.dma @[lsu_lsc_ctl.scala 216:65]
+    _T_133.bits.unsign <= lsu_pkt_m_in.bits.unsign @[lsu_lsc_ctl.scala 216:65]
+    _T_133.bits.store <= lsu_pkt_m_in.bits.store @[lsu_lsc_ctl.scala 216:65]
+    _T_133.bits.load <= lsu_pkt_m_in.bits.load @[lsu_lsc_ctl.scala 216:65]
+    _T_133.bits.dword <= lsu_pkt_m_in.bits.dword @[lsu_lsc_ctl.scala 216:65]
+    _T_133.bits.word <= lsu_pkt_m_in.bits.word @[lsu_lsc_ctl.scala 216:65]
+    _T_133.bits.half <= lsu_pkt_m_in.bits.half @[lsu_lsc_ctl.scala 216:65]
+    _T_133.bits.by <= lsu_pkt_m_in.bits.by @[lsu_lsc_ctl.scala 216:65]
+    _T_133.bits.stack <= lsu_pkt_m_in.bits.stack @[lsu_lsc_ctl.scala 216:65]
+    _T_133.bits.fast_int <= lsu_pkt_m_in.bits.fast_int @[lsu_lsc_ctl.scala 216:65]
+    _T_133.valid <= lsu_pkt_m_in.valid @[lsu_lsc_ctl.scala 216:65]
+    io.lsu_pkt_m.bits.store_data_bypass_m <= _T_133.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 216:28]
+    io.lsu_pkt_m.bits.load_ldst_bypass_d <= _T_133.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 216:28]
+    io.lsu_pkt_m.bits.store_data_bypass_d <= _T_133.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 216:28]
+    io.lsu_pkt_m.bits.dma <= _T_133.bits.dma @[lsu_lsc_ctl.scala 216:28]
+    io.lsu_pkt_m.bits.unsign <= _T_133.bits.unsign @[lsu_lsc_ctl.scala 216:28]
+    io.lsu_pkt_m.bits.store <= _T_133.bits.store @[lsu_lsc_ctl.scala 216:28]
+    io.lsu_pkt_m.bits.load <= _T_133.bits.load @[lsu_lsc_ctl.scala 216:28]
+    io.lsu_pkt_m.bits.dword <= _T_133.bits.dword @[lsu_lsc_ctl.scala 216:28]
+    io.lsu_pkt_m.bits.word <= _T_133.bits.word @[lsu_lsc_ctl.scala 216:28]
+    io.lsu_pkt_m.bits.half <= _T_133.bits.half @[lsu_lsc_ctl.scala 216:28]
+    io.lsu_pkt_m.bits.by <= _T_133.bits.by @[lsu_lsc_ctl.scala 216:28]
+    io.lsu_pkt_m.bits.stack <= _T_133.bits.stack @[lsu_lsc_ctl.scala 216:28]
+    io.lsu_pkt_m.bits.fast_int <= _T_133.bits.fast_int @[lsu_lsc_ctl.scala 216:28]
+    io.lsu_pkt_m.valid <= _T_133.valid @[lsu_lsc_ctl.scala 216:28]
+    wire _T_134 : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 217:91]
+    _T_134.bits.store_data_bypass_m <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
+    _T_134.bits.load_ldst_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
+    _T_134.bits.store_data_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
+    _T_134.bits.dma <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
+    _T_134.bits.unsign <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
+    _T_134.bits.store <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
+    _T_134.bits.load <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
+    _T_134.bits.dword <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
+    _T_134.bits.word <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
+    _T_134.bits.half <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
+    _T_134.bits.by <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
+    _T_134.bits.stack <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
+    _T_134.bits.fast_int <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
+    _T_134.valid <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
+    reg _T_135 : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, io.lsu_c1_r_clk with : (reset => (reset, _T_134)) @[lsu_lsc_ctl.scala 217:65]
+    _T_135.bits.store_data_bypass_m <= lsu_pkt_r_in.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 217:65]
+    _T_135.bits.load_ldst_bypass_d <= lsu_pkt_r_in.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 217:65]
+    _T_135.bits.store_data_bypass_d <= lsu_pkt_r_in.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 217:65]
+    _T_135.bits.dma <= lsu_pkt_r_in.bits.dma @[lsu_lsc_ctl.scala 217:65]
+    _T_135.bits.unsign <= lsu_pkt_r_in.bits.unsign @[lsu_lsc_ctl.scala 217:65]
+    _T_135.bits.store <= lsu_pkt_r_in.bits.store @[lsu_lsc_ctl.scala 217:65]
+    _T_135.bits.load <= lsu_pkt_r_in.bits.load @[lsu_lsc_ctl.scala 217:65]
+    _T_135.bits.dword <= lsu_pkt_r_in.bits.dword @[lsu_lsc_ctl.scala 217:65]
+    _T_135.bits.word <= lsu_pkt_r_in.bits.word @[lsu_lsc_ctl.scala 217:65]
+    _T_135.bits.half <= lsu_pkt_r_in.bits.half @[lsu_lsc_ctl.scala 217:65]
+    _T_135.bits.by <= lsu_pkt_r_in.bits.by @[lsu_lsc_ctl.scala 217:65]
+    _T_135.bits.stack <= lsu_pkt_r_in.bits.stack @[lsu_lsc_ctl.scala 217:65]
+    _T_135.bits.fast_int <= lsu_pkt_r_in.bits.fast_int @[lsu_lsc_ctl.scala 217:65]
+    _T_135.valid <= lsu_pkt_r_in.valid @[lsu_lsc_ctl.scala 217:65]
+    io.lsu_pkt_r.bits.store_data_bypass_m <= _T_135.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 217:28]
+    io.lsu_pkt_r.bits.load_ldst_bypass_d <= _T_135.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 217:28]
+    io.lsu_pkt_r.bits.store_data_bypass_d <= _T_135.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 217:28]
+    io.lsu_pkt_r.bits.dma <= _T_135.bits.dma @[lsu_lsc_ctl.scala 217:28]
+    io.lsu_pkt_r.bits.unsign <= _T_135.bits.unsign @[lsu_lsc_ctl.scala 217:28]
+    io.lsu_pkt_r.bits.store <= _T_135.bits.store @[lsu_lsc_ctl.scala 217:28]
+    io.lsu_pkt_r.bits.load <= _T_135.bits.load @[lsu_lsc_ctl.scala 217:28]
+    io.lsu_pkt_r.bits.dword <= _T_135.bits.dword @[lsu_lsc_ctl.scala 217:28]
+    io.lsu_pkt_r.bits.word <= _T_135.bits.word @[lsu_lsc_ctl.scala 217:28]
+    io.lsu_pkt_r.bits.half <= _T_135.bits.half @[lsu_lsc_ctl.scala 217:28]
+    io.lsu_pkt_r.bits.by <= _T_135.bits.by @[lsu_lsc_ctl.scala 217:28]
+    io.lsu_pkt_r.bits.stack <= _T_135.bits.stack @[lsu_lsc_ctl.scala 217:28]
+    io.lsu_pkt_r.bits.fast_int <= _T_135.bits.fast_int @[lsu_lsc_ctl.scala 217:28]
+    io.lsu_pkt_r.valid <= _T_135.valid @[lsu_lsc_ctl.scala 217:28]
+    reg _T_136 : UInt<1>, io.lsu_c2_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 218:65]
+    _T_136 <= lsu_pkt_m_in.valid @[lsu_lsc_ctl.scala 218:65]
+    io.lsu_pkt_m.valid <= _T_136 @[lsu_lsc_ctl.scala 218:28]
+    reg _T_137 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 219:65]
+    _T_137 <= lsu_pkt_r_in.valid @[lsu_lsc_ctl.scala 219:65]
+    io.lsu_pkt_r.valid <= _T_137 @[lsu_lsc_ctl.scala 219:28]
+    node _T_138 = bits(io.dma_lsc_ctl.dma_mem_wdata, 63, 0) @[lsu_lsc_ctl.scala 221:59]
+    node _T_139 = bits(io.dma_lsc_ctl.dma_mem_addr, 2, 0) @[lsu_lsc_ctl.scala 221:100]
+    node _T_140 = cat(_T_139, UInt<3>("h00")) @[Cat.scala 29:58]
+    node dma_mem_wdata_shifted = dshr(_T_138, _T_140) @[lsu_lsc_ctl.scala 221:66]
+    node _T_141 = bits(io.dma_lsc_ctl.dma_dccm_req, 0, 0) @[lsu_lsc_ctl.scala 222:63]
+    node _T_142 = bits(dma_mem_wdata_shifted, 31, 0) @[lsu_lsc_ctl.scala 222:91]
+    node _T_143 = bits(io.lsu_exu.exu_lsu_rs2_d, 31, 0) @[lsu_lsc_ctl.scala 222:122]
+    node store_data_d = mux(_T_141, _T_142, _T_143) @[lsu_lsc_ctl.scala 222:34]
+    node _T_144 = bits(io.lsu_pkt_d.bits.store_data_bypass_d, 0, 0) @[lsu_lsc_ctl.scala 223:73]
+    node _T_145 = bits(io.lsu_result_m, 31, 0) @[lsu_lsc_ctl.scala 223:95]
+    node _T_146 = bits(store_data_d, 31, 0) @[lsu_lsc_ctl.scala 223:114]
+    node store_data_m_in = mux(_T_144, _T_145, _T_146) @[lsu_lsc_ctl.scala 223:34]
+    reg store_data_pre_m : UInt, io.lsu_store_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 225:72]
+    store_data_pre_m <= store_data_m_in @[lsu_lsc_ctl.scala 225:72]
+    reg _T_147 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 226:62]
+    _T_147 <= io.lsu_addr_d @[lsu_lsc_ctl.scala 226:62]
+    io.lsu_addr_m <= _T_147 @[lsu_lsc_ctl.scala 226:24]
+    reg _T_148 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 227:62]
+    _T_148 <= io.lsu_addr_m @[lsu_lsc_ctl.scala 227:62]
+    io.lsu_addr_r <= _T_148 @[lsu_lsc_ctl.scala 227:24]
+    node _T_149 = bits(io.ldst_dual_m, 0, 0) @[lib.scala 8:44]
+    node _T_150 = bits(io.lsu_addr_m, 31, 3) @[lsu_lsc_ctl.scala 228:71]
+    node _T_151 = mux(_T_149, end_addr_pre_m, _T_150) @[lsu_lsc_ctl.scala 228:27]
+    node _T_152 = bits(io.end_addr_d, 2, 0) @[lsu_lsc_ctl.scala 228:128]
+    reg _T_153 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 228:114]
+    _T_153 <= _T_152 @[lsu_lsc_ctl.scala 228:114]
+    node _T_154 = cat(_T_151, _T_153) @[Cat.scala 29:58]
+    io.end_addr_m <= _T_154 @[lsu_lsc_ctl.scala 228:17]
+    node _T_155 = bits(io.ldst_dual_r, 0, 0) @[lib.scala 8:44]
+    node _T_156 = bits(io.lsu_addr_r, 31, 3) @[lsu_lsc_ctl.scala 229:71]
+    node _T_157 = mux(_T_155, end_addr_pre_r, _T_156) @[lsu_lsc_ctl.scala 229:27]
+    node _T_158 = bits(io.end_addr_m, 2, 0) @[lsu_lsc_ctl.scala 229:128]
+    reg _T_159 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 229:114]
+    _T_159 <= _T_158 @[lsu_lsc_ctl.scala 229:114]
+    node _T_160 = cat(_T_157, _T_159) @[Cat.scala 29:58]
+    io.end_addr_r <= _T_160 @[lsu_lsc_ctl.scala 229:17]
+    node _T_161 = bits(io.end_addr_d, 31, 3) @[lsu_lsc_ctl.scala 230:41]
+    node _T_162 = and(io.lsu_pkt_d.valid, io.ldst_dual_d) @[lsu_lsc_ctl.scala 230:69]
+    node _T_163 = or(_T_162, io.clk_override) @[lsu_lsc_ctl.scala 230:87]
+    node _T_164 = bits(_T_163, 0, 0) @[lib.scala 8:44]
+    node _T_165 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44]
+    inst rvclkhdr of rvclkhdr @[lib.scala 390:23]
+    rvclkhdr.clock <= clock
+    rvclkhdr.reset <= reset
+    rvclkhdr.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr.io.en <= _T_164 @[lib.scala 393:17]
+    rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg _T_166 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_164 : @[Reg.scala 28:19]
+      _T_166 <= _T_161 @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    end_addr_pre_m <= _T_166 @[lsu_lsc_ctl.scala 230:18]
+    node _T_167 = bits(io.end_addr_m, 31, 3) @[lsu_lsc_ctl.scala 231:41]
+    node _T_168 = and(io.lsu_pkt_m.valid, io.ldst_dual_m) @[lsu_lsc_ctl.scala 231:69]
+    node _T_169 = or(_T_168, io.clk_override) @[lsu_lsc_ctl.scala 231:87]
+    node _T_170 = bits(_T_169, 0, 0) @[lib.scala 8:44]
+    node _T_171 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44]
+    inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 390:23]
+    rvclkhdr_1.clock <= clock
+    rvclkhdr_1.reset <= reset
+    rvclkhdr_1.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr_1.io.en <= _T_170 @[lib.scala 393:17]
+    rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg _T_172 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_170 : @[Reg.scala 28:19]
+      _T_172 <= _T_167 @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    end_addr_pre_r <= _T_172 @[lsu_lsc_ctl.scala 231:18]
+    reg _T_173 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 232:62]
+    _T_173 <= io.addr_in_dccm_d @[lsu_lsc_ctl.scala 232:62]
+    io.addr_in_dccm_m <= _T_173 @[lsu_lsc_ctl.scala 232:24]
+    reg _T_174 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 233:62]
+    _T_174 <= io.addr_in_dccm_m @[lsu_lsc_ctl.scala 233:62]
+    io.addr_in_dccm_r <= _T_174 @[lsu_lsc_ctl.scala 233:24]
+    reg _T_175 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 234:62]
+    _T_175 <= io.addr_in_pic_d @[lsu_lsc_ctl.scala 234:62]
+    io.addr_in_pic_m <= _T_175 @[lsu_lsc_ctl.scala 234:24]
+    reg _T_176 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 235:62]
+    _T_176 <= io.addr_in_pic_m @[lsu_lsc_ctl.scala 235:62]
+    io.addr_in_pic_r <= _T_176 @[lsu_lsc_ctl.scala 235:24]
+    reg _T_177 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 236:62]
+    _T_177 <= addrcheck.io.addr_external_d @[lsu_lsc_ctl.scala 236:62]
+    io.addr_external_m <= _T_177 @[lsu_lsc_ctl.scala 236:24]
+    reg addr_external_r : UInt<1>, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 237:66]
+    addr_external_r <= io.addr_external_m @[lsu_lsc_ctl.scala 237:66]
+    node _T_178 = or(io.addr_external_m, io.clk_override) @[lsu_lsc_ctl.scala 238:77]
+    node _T_179 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44]
+    inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 390:23]
+    rvclkhdr_2.clock <= clock
+    rvclkhdr_2.reset <= reset
+    rvclkhdr_2.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr_2.io.en <= _T_178 @[lib.scala 393:17]
+    rvclkhdr_2.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg bus_read_data_r : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_178 : @[Reg.scala 28:19]
+      bus_read_data_r <= io.bus_read_data_m @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    node _T_180 = bits(io.lsu_ld_data_corr_r, 31, 1) @[lsu_lsc_ctl.scala 241:52]
+    io.lsu_fir_addr <= _T_180 @[lsu_lsc_ctl.scala 241:28]
+    io.lsu_addr_d <= full_addr_d @[lsu_lsc_ctl.scala 243:28]
+    node _T_181 = or(io.lsu_pkt_r.bits.store, io.lsu_pkt_r.bits.load) @[lsu_lsc_ctl.scala 245:68]
+    node _T_182 = and(io.lsu_pkt_r.valid, _T_181) @[lsu_lsc_ctl.scala 245:41]
+    node _T_183 = eq(io.flush_r, UInt<1>("h00")) @[lsu_lsc_ctl.scala 245:96]
+    node _T_184 = and(_T_182, _T_183) @[lsu_lsc_ctl.scala 245:94]
+    node _T_185 = eq(io.lsu_pkt_r.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 245:110]
+    node _T_186 = and(_T_184, _T_185) @[lsu_lsc_ctl.scala 245:108]
+    io.lsu_commit_r <= _T_186 @[lsu_lsc_ctl.scala 245:19]
+    node _T_187 = bits(io.picm_mask_data_m, 31, 0) @[lsu_lsc_ctl.scala 246:52]
+    node _T_188 = eq(io.addr_in_pic_m, UInt<1>("h00")) @[lsu_lsc_ctl.scala 246:69]
+    node _T_189 = bits(_T_188, 0, 0) @[Bitwise.scala 72:15]
+    node _T_190 = mux(_T_189, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
+    node _T_191 = or(_T_187, _T_190) @[lsu_lsc_ctl.scala 246:59]
+    node _T_192 = bits(io.lsu_pkt_m.bits.store_data_bypass_m, 0, 0) @[lsu_lsc_ctl.scala 246:133]
+    node _T_193 = mux(_T_192, io.lsu_result_m, store_data_pre_m) @[lsu_lsc_ctl.scala 246:94]
+    node _T_194 = and(_T_191, _T_193) @[lsu_lsc_ctl.scala 246:89]
+    io.store_data_m <= _T_194 @[lsu_lsc_ctl.scala 246:29]
+    node _T_195 = bits(addr_external_r, 0, 0) @[lib.scala 8:44]
+    node _T_196 = mux(_T_195, bus_read_data_r, io.lsu_ld_data_r) @[lsu_lsc_ctl.scala 250:33]
+    lsu_ld_datafn_r <= _T_196 @[lsu_lsc_ctl.scala 250:27]
+    node _T_197 = bits(addr_external_r, 0, 0) @[lib.scala 8:44]
+    node _T_198 = mux(_T_197, bus_read_data_r, io.lsu_ld_data_corr_r) @[lsu_lsc_ctl.scala 251:33]
+    lsu_ld_datafn_corr_r <= _T_198 @[lsu_lsc_ctl.scala 251:27]
+    node _T_199 = and(io.lsu_pkt_r.bits.unsign, io.lsu_pkt_r.bits.by) @[lsu_lsc_ctl.scala 253:66]
+    node _T_200 = bits(_T_199, 0, 0) @[Bitwise.scala 72:15]
+    node _T_201 = mux(_T_200, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
+    node _T_202 = bits(lsu_ld_datafn_r, 7, 0) @[lsu_lsc_ctl.scala 253:125]
+    node _T_203 = cat(UInt<24>("h00"), _T_202) @[Cat.scala 29:58]
+    node _T_204 = and(_T_201, _T_203) @[lsu_lsc_ctl.scala 253:94]
+    node _T_205 = and(io.lsu_pkt_r.bits.unsign, io.lsu_pkt_r.bits.half) @[lsu_lsc_ctl.scala 254:43]
+    node _T_206 = bits(_T_205, 0, 0) @[Bitwise.scala 72:15]
+    node _T_207 = mux(_T_206, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
+    node _T_208 = bits(lsu_ld_datafn_r, 15, 0) @[lsu_lsc_ctl.scala 254:102]
+    node _T_209 = cat(UInt<16>("h00"), _T_208) @[Cat.scala 29:58]
+    node _T_210 = and(_T_207, _T_209) @[lsu_lsc_ctl.scala 254:71]
+    node _T_211 = or(_T_204, _T_210) @[lsu_lsc_ctl.scala 253:133]
+    node _T_212 = eq(io.lsu_pkt_r.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 255:17]
+    node _T_213 = and(_T_212, io.lsu_pkt_r.bits.by) @[lsu_lsc_ctl.scala 255:43]
+    node _T_214 = bits(_T_213, 0, 0) @[Bitwise.scala 72:15]
+    node _T_215 = mux(_T_214, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
+    node _T_216 = bits(lsu_ld_datafn_r, 7, 7) @[lsu_lsc_ctl.scala 255:102]
+    node _T_217 = bits(_T_216, 0, 0) @[Bitwise.scala 72:15]
+    node _T_218 = mux(_T_217, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12]
+    node _T_219 = bits(lsu_ld_datafn_r, 7, 0) @[lsu_lsc_ctl.scala 255:125]
+    node _T_220 = cat(_T_218, _T_219) @[Cat.scala 29:58]
+    node _T_221 = and(_T_215, _T_220) @[lsu_lsc_ctl.scala 255:71]
+    node _T_222 = or(_T_211, _T_221) @[lsu_lsc_ctl.scala 254:114]
+    node _T_223 = eq(io.lsu_pkt_r.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 256:17]
+    node _T_224 = and(_T_223, io.lsu_pkt_r.bits.half) @[lsu_lsc_ctl.scala 256:43]
+    node _T_225 = bits(_T_224, 0, 0) @[Bitwise.scala 72:15]
+    node _T_226 = mux(_T_225, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
+    node _T_227 = bits(lsu_ld_datafn_r, 15, 15) @[lsu_lsc_ctl.scala 256:101]
+    node _T_228 = bits(_T_227, 0, 0) @[Bitwise.scala 72:15]
+    node _T_229 = mux(_T_228, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12]
+    node _T_230 = bits(lsu_ld_datafn_r, 15, 0) @[lsu_lsc_ctl.scala 256:125]
+    node _T_231 = cat(_T_229, _T_230) @[Cat.scala 29:58]
+    node _T_232 = and(_T_226, _T_231) @[lsu_lsc_ctl.scala 256:71]
+    node _T_233 = or(_T_222, _T_232) @[lsu_lsc_ctl.scala 255:134]
+    node _T_234 = bits(io.lsu_pkt_r.bits.word, 0, 0) @[Bitwise.scala 72:15]
+    node _T_235 = mux(_T_234, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
+    node _T_236 = bits(lsu_ld_datafn_r, 31, 0) @[lsu_lsc_ctl.scala 257:60]
+    node _T_237 = and(_T_235, _T_236) @[lsu_lsc_ctl.scala 257:43]
+    node _T_238 = or(_T_233, _T_237) @[lsu_lsc_ctl.scala 256:134]
+    io.lsu_result_m <= _T_238 @[lsu_lsc_ctl.scala 253:27]
+    node _T_239 = and(io.lsu_pkt_r.bits.unsign, io.lsu_pkt_r.bits.by) @[lsu_lsc_ctl.scala 259:66]
+    node _T_240 = bits(_T_239, 0, 0) @[Bitwise.scala 72:15]
+    node _T_241 = mux(_T_240, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
+    node _T_242 = bits(lsu_ld_datafn_corr_r, 7, 0) @[lsu_lsc_ctl.scala 259:130]
+    node _T_243 = cat(UInt<24>("h00"), _T_242) @[Cat.scala 29:58]
+    node _T_244 = and(_T_241, _T_243) @[lsu_lsc_ctl.scala 259:94]
+    node _T_245 = and(io.lsu_pkt_r.bits.unsign, io.lsu_pkt_r.bits.half) @[lsu_lsc_ctl.scala 260:43]
+    node _T_246 = bits(_T_245, 0, 0) @[Bitwise.scala 72:15]
+    node _T_247 = mux(_T_246, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
+    node _T_248 = bits(lsu_ld_datafn_corr_r, 15, 0) @[lsu_lsc_ctl.scala 260:107]
+    node _T_249 = cat(UInt<16>("h00"), _T_248) @[Cat.scala 29:58]
+    node _T_250 = and(_T_247, _T_249) @[lsu_lsc_ctl.scala 260:71]
+    node _T_251 = or(_T_244, _T_250) @[lsu_lsc_ctl.scala 259:138]
+    node _T_252 = eq(io.lsu_pkt_r.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 261:17]
+    node _T_253 = and(_T_252, io.lsu_pkt_r.bits.by) @[lsu_lsc_ctl.scala 261:43]
+    node _T_254 = bits(_T_253, 0, 0) @[Bitwise.scala 72:15]
+    node _T_255 = mux(_T_254, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
+    node _T_256 = bits(lsu_ld_datafn_corr_r, 7, 7) @[lsu_lsc_ctl.scala 261:107]
+    node _T_257 = bits(_T_256, 0, 0) @[Bitwise.scala 72:15]
+    node _T_258 = mux(_T_257, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12]
+    node _T_259 = bits(lsu_ld_datafn_corr_r, 7, 0) @[lsu_lsc_ctl.scala 261:135]
+    node _T_260 = cat(_T_258, _T_259) @[Cat.scala 29:58]
+    node _T_261 = and(_T_255, _T_260) @[lsu_lsc_ctl.scala 261:71]
+    node _T_262 = or(_T_251, _T_261) @[lsu_lsc_ctl.scala 260:119]
+    node _T_263 = eq(io.lsu_pkt_r.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 262:17]
+    node _T_264 = and(_T_263, io.lsu_pkt_r.bits.half) @[lsu_lsc_ctl.scala 262:43]
+    node _T_265 = bits(_T_264, 0, 0) @[Bitwise.scala 72:15]
+    node _T_266 = mux(_T_265, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
+    node _T_267 = bits(lsu_ld_datafn_corr_r, 15, 15) @[lsu_lsc_ctl.scala 262:106]
+    node _T_268 = bits(_T_267, 0, 0) @[Bitwise.scala 72:15]
+    node _T_269 = mux(_T_268, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12]
+    node _T_270 = bits(lsu_ld_datafn_corr_r, 15, 0) @[lsu_lsc_ctl.scala 262:135]
+    node _T_271 = cat(_T_269, _T_270) @[Cat.scala 29:58]
+    node _T_272 = and(_T_266, _T_271) @[lsu_lsc_ctl.scala 262:71]
+    node _T_273 = or(_T_262, _T_272) @[lsu_lsc_ctl.scala 261:144]
+    node _T_274 = bits(io.lsu_pkt_r.bits.word, 0, 0) @[Bitwise.scala 72:15]
+    node _T_275 = mux(_T_274, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
+    node _T_276 = bits(lsu_ld_datafn_corr_r, 31, 0) @[lsu_lsc_ctl.scala 263:65]
+    node _T_277 = and(_T_275, _T_276) @[lsu_lsc_ctl.scala 263:43]
+    node _T_278 = or(_T_273, _T_277) @[lsu_lsc_ctl.scala 262:144]
+    io.lsu_result_corr_r <= _T_278 @[lsu_lsc_ctl.scala 259:27]
+    
   extmodule gated_latch_3 : 
     output Q : Clock
     input CK : Clock
@@ -347,610 +948,6 @@ circuit lsu :
     clkhdr.EN <= io.en @[lib.scala 337:18]
     clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
     
-  module lsu_lsc_ctl : 
-    input clock : Clock
-    input reset : AsyncReset
-    output io : {flip clk_override : UInt<1>, flip lsu_c1_m_clk : Clock, flip lsu_c1_r_clk : Clock, flip lsu_c2_m_clk : Clock, flip lsu_c2_r_clk : Clock, flip lsu_store_c1_m_clk : Clock, flip lsu_ld_data_r : UInt<32>, flip lsu_ld_data_corr_r : UInt<32>, flip lsu_single_ecc_error_r : UInt<1>, flip lsu_double_ecc_error_r : UInt<1>, flip lsu_ld_data_m : UInt<32>, flip lsu_single_ecc_error_m : UInt<1>, flip lsu_double_ecc_error_m : UInt<1>, flip flush_m_up : UInt<1>, flip flush_r : UInt<1>, flip ldst_dual_d : UInt<1>, flip ldst_dual_m : UInt<1>, flip ldst_dual_r : UInt<1>, lsu_exu : {flip exu_lsu_rs1_d : UInt<32>, flip exu_lsu_rs2_d : UInt<32>}, flip lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip dec_lsu_valid_raw_d : UInt<1>, flip dec_lsu_offset_d : UInt<12>, flip picm_mask_data_m : UInt<32>, flip bus_read_data_m : UInt<32>, lsu_result_m : UInt<32>, lsu_result_corr_r : UInt<32>, lsu_addr_d : UInt<32>, lsu_addr_m : UInt<32>, lsu_addr_r : UInt<32>, end_addr_d : UInt<32>, end_addr_m : UInt<32>, end_addr_r : UInt<32>, store_data_m : UInt<32>, flip dec_tlu_mrac_ff : UInt<32>, lsu_exc_m : UInt<1>, is_sideeffects_m : UInt<1>, lsu_commit_r : UInt<1>, lsu_single_ecc_error_incr : UInt<1>, lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, lsu_fir_addr : UInt<31>, lsu_fir_error : UInt<2>, addr_in_dccm_d : UInt<1>, addr_in_dccm_m : UInt<1>, addr_in_dccm_r : UInt<1>, addr_in_pic_d : UInt<1>, addr_in_pic_m : UInt<1>, addr_in_pic_r : UInt<1>, addr_external_m : UInt<1>, dma_lsc_ctl : {flip dma_dccm_req : UInt<1>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_write : UInt<1>, flip dma_mem_wdata : UInt<64>}, lsu_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, lsu_pkt_r : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip scan_mode : UInt<1>}
-    
-    wire end_addr_pre_m : UInt<29>
-    end_addr_pre_m <= UInt<29>("h00")
-    wire end_addr_pre_r : UInt<29>
-    end_addr_pre_r <= UInt<29>("h00")
-    wire dma_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 95:29]
-    wire lsu_pkt_m_in : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 96:29]
-    wire lsu_pkt_r_in : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 97:29]
-    wire lsu_error_pkt_m : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}} @[lsu_lsc_ctl.scala 98:29]
-    node _T = bits(io.dec_lsu_valid_raw_d, 0, 0) @[lsu_lsc_ctl.scala 100:52]
-    node lsu_rs1_d = mux(_T, io.lsu_exu.exu_lsu_rs1_d, io.dma_lsc_ctl.dma_mem_addr) @[lsu_lsc_ctl.scala 100:28]
-    node _T_1 = bits(io.dec_lsu_offset_d, 11, 0) @[lsu_lsc_ctl.scala 101:44]
-    node _T_2 = bits(io.dec_lsu_valid_raw_d, 0, 0) @[Bitwise.scala 72:15]
-    node _T_3 = mux(_T_2, UInt<12>("h0fff"), UInt<12>("h00")) @[Bitwise.scala 72:12]
-    node lsu_offset_d = and(_T_1, _T_3) @[lsu_lsc_ctl.scala 101:51]
-    node _T_4 = bits(io.lsu_pkt_d.bits.load_ldst_bypass_d, 0, 0) @[lsu_lsc_ctl.scala 104:66]
-    node rs1_d = mux(_T_4, io.lsu_result_m, lsu_rs1_d) @[lsu_lsc_ctl.scala 104:28]
-    node _T_5 = bits(rs1_d, 11, 0) @[lib.scala 92:31]
-    node _T_6 = cat(UInt<1>("h00"), _T_5) @[Cat.scala 29:58]
-    node _T_7 = bits(lsu_offset_d, 11, 0) @[lib.scala 92:60]
-    node _T_8 = cat(UInt<1>("h00"), _T_7) @[Cat.scala 29:58]
-    node _T_9 = add(_T_6, _T_8) @[lib.scala 92:39]
-    node _T_10 = tail(_T_9, 1) @[lib.scala 92:39]
-    node _T_11 = bits(lsu_offset_d, 11, 11) @[lib.scala 93:41]
-    node _T_12 = bits(_T_10, 12, 12) @[lib.scala 93:50]
-    node _T_13 = xor(_T_11, _T_12) @[lib.scala 93:46]
-    node _T_14 = not(_T_13) @[lib.scala 93:33]
-    node _T_15 = bits(_T_14, 0, 0) @[Bitwise.scala 72:15]
-    node _T_16 = mux(_T_15, UInt<20>("h0fffff"), UInt<20>("h00")) @[Bitwise.scala 72:12]
-    node _T_17 = bits(rs1_d, 31, 12) @[lib.scala 93:63]
-    node _T_18 = and(_T_16, _T_17) @[lib.scala 93:58]
-    node _T_19 = bits(lsu_offset_d, 11, 11) @[lib.scala 94:25]
-    node _T_20 = not(_T_19) @[lib.scala 94:18]
-    node _T_21 = bits(_T_10, 12, 12) @[lib.scala 94:34]
-    node _T_22 = and(_T_20, _T_21) @[lib.scala 94:30]
-    node _T_23 = bits(_T_22, 0, 0) @[Bitwise.scala 72:15]
-    node _T_24 = mux(_T_23, UInt<20>("h0fffff"), UInt<20>("h00")) @[Bitwise.scala 72:12]
-    node _T_25 = bits(rs1_d, 31, 12) @[lib.scala 94:47]
-    node _T_26 = add(_T_25, UInt<1>("h01")) @[lib.scala 94:54]
-    node _T_27 = tail(_T_26, 1) @[lib.scala 94:54]
-    node _T_28 = and(_T_24, _T_27) @[lib.scala 94:41]
-    node _T_29 = or(_T_18, _T_28) @[lib.scala 93:72]
-    node _T_30 = bits(lsu_offset_d, 11, 11) @[lib.scala 95:24]
-    node _T_31 = bits(_T_10, 12, 12) @[lib.scala 95:34]
-    node _T_32 = not(_T_31) @[lib.scala 95:31]
-    node _T_33 = and(_T_30, _T_32) @[lib.scala 95:29]
-    node _T_34 = bits(_T_33, 0, 0) @[Bitwise.scala 72:15]
-    node _T_35 = mux(_T_34, UInt<20>("h0fffff"), UInt<20>("h00")) @[Bitwise.scala 72:12]
-    node _T_36 = bits(rs1_d, 31, 12) @[lib.scala 95:47]
-    node _T_37 = sub(_T_36, UInt<1>("h01")) @[lib.scala 95:54]
-    node _T_38 = tail(_T_37, 1) @[lib.scala 95:54]
-    node _T_39 = and(_T_35, _T_38) @[lib.scala 95:41]
-    node _T_40 = or(_T_29, _T_39) @[lib.scala 94:61]
-    node _T_41 = bits(_T_10, 11, 0) @[lib.scala 96:22]
-    node full_addr_d = cat(_T_40, _T_41) @[Cat.scala 29:58]
-    node _T_42 = bits(io.lsu_pkt_d.bits.half, 0, 0) @[Bitwise.scala 72:15]
-    node _T_43 = mux(_T_42, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
-    node _T_44 = and(_T_43, UInt<3>("h01")) @[lsu_lsc_ctl.scala 109:58]
-    node _T_45 = bits(io.lsu_pkt_d.bits.word, 0, 0) @[Bitwise.scala 72:15]
-    node _T_46 = mux(_T_45, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
-    node _T_47 = and(_T_46, UInt<3>("h03")) @[lsu_lsc_ctl.scala 110:40]
-    node _T_48 = or(_T_44, _T_47) @[lsu_lsc_ctl.scala 109:70]
-    node _T_49 = bits(io.lsu_pkt_d.bits.dword, 0, 0) @[Bitwise.scala 72:15]
-    node _T_50 = mux(_T_49, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
-    node _T_51 = and(_T_50, UInt<3>("h07")) @[lsu_lsc_ctl.scala 111:40]
-    node addr_offset_d = or(_T_48, _T_51) @[lsu_lsc_ctl.scala 110:52]
-    node _T_52 = bits(lsu_offset_d, 11, 11) @[lsu_lsc_ctl.scala 113:39]
-    node _T_53 = bits(lsu_offset_d, 11, 0) @[lsu_lsc_ctl.scala 113:52]
-    node _T_54 = cat(_T_52, _T_53) @[Cat.scala 29:58]
-    node _T_55 = mux(UInt<1>("h00"), UInt<9>("h01ff"), UInt<9>("h00")) @[Bitwise.scala 72:12]
-    node _T_56 = bits(addr_offset_d, 2, 0) @[lsu_lsc_ctl.scala 113:91]
-    node _T_57 = cat(_T_55, _T_56) @[Cat.scala 29:58]
-    node _T_58 = add(_T_54, _T_57) @[lsu_lsc_ctl.scala 113:60]
-    node end_addr_offset_d = tail(_T_58, 1) @[lsu_lsc_ctl.scala 113:60]
-    node _T_59 = bits(rs1_d, 31, 0) @[lsu_lsc_ctl.scala 114:32]
-    node _T_60 = bits(end_addr_offset_d, 12, 12) @[lsu_lsc_ctl.scala 114:70]
-    node _T_61 = bits(_T_60, 0, 0) @[Bitwise.scala 72:15]
-    node _T_62 = mux(_T_61, UInt<19>("h07ffff"), UInt<19>("h00")) @[Bitwise.scala 72:12]
-    node _T_63 = bits(end_addr_offset_d, 12, 0) @[lsu_lsc_ctl.scala 114:93]
-    node _T_64 = cat(_T_62, _T_63) @[Cat.scala 29:58]
-    node _T_65 = add(_T_59, _T_64) @[lsu_lsc_ctl.scala 114:39]
-    node full_end_addr_d = tail(_T_65, 1) @[lsu_lsc_ctl.scala 114:39]
-    io.end_addr_d <= full_end_addr_d @[lsu_lsc_ctl.scala 115:24]
-    inst addrcheck of lsu_addrcheck @[lsu_lsc_ctl.scala 118:25]
-    addrcheck.clock <= clock
-    addrcheck.reset <= reset
-    addrcheck.io.lsu_c2_m_clk <= io.lsu_c2_m_clk @[lsu_lsc_ctl.scala 120:42]
-    addrcheck.io.start_addr_d <= full_addr_d @[lsu_lsc_ctl.scala 122:42]
-    addrcheck.io.end_addr_d <= full_end_addr_d @[lsu_lsc_ctl.scala 123:42]
-    addrcheck.io.lsu_pkt_d.bits.store_data_bypass_m <= io.lsu_pkt_d.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 124:42]
-    addrcheck.io.lsu_pkt_d.bits.load_ldst_bypass_d <= io.lsu_pkt_d.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 124:42]
-    addrcheck.io.lsu_pkt_d.bits.store_data_bypass_d <= io.lsu_pkt_d.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 124:42]
-    addrcheck.io.lsu_pkt_d.bits.dma <= io.lsu_pkt_d.bits.dma @[lsu_lsc_ctl.scala 124:42]
-    addrcheck.io.lsu_pkt_d.bits.unsign <= io.lsu_pkt_d.bits.unsign @[lsu_lsc_ctl.scala 124:42]
-    addrcheck.io.lsu_pkt_d.bits.store <= io.lsu_pkt_d.bits.store @[lsu_lsc_ctl.scala 124:42]
-    addrcheck.io.lsu_pkt_d.bits.load <= io.lsu_pkt_d.bits.load @[lsu_lsc_ctl.scala 124:42]
-    addrcheck.io.lsu_pkt_d.bits.dword <= io.lsu_pkt_d.bits.dword @[lsu_lsc_ctl.scala 124:42]
-    addrcheck.io.lsu_pkt_d.bits.word <= io.lsu_pkt_d.bits.word @[lsu_lsc_ctl.scala 124:42]
-    addrcheck.io.lsu_pkt_d.bits.half <= io.lsu_pkt_d.bits.half @[lsu_lsc_ctl.scala 124:42]
-    addrcheck.io.lsu_pkt_d.bits.by <= io.lsu_pkt_d.bits.by @[lsu_lsc_ctl.scala 124:42]
-    addrcheck.io.lsu_pkt_d.bits.fast_int <= io.lsu_pkt_d.bits.fast_int @[lsu_lsc_ctl.scala 124:42]
-    addrcheck.io.lsu_pkt_d.valid <= io.lsu_pkt_d.valid @[lsu_lsc_ctl.scala 124:42]
-    addrcheck.io.dec_tlu_mrac_ff <= io.dec_tlu_mrac_ff @[lsu_lsc_ctl.scala 125:42]
-    node _T_66 = bits(rs1_d, 31, 28) @[lsu_lsc_ctl.scala 126:50]
-    addrcheck.io.rs1_region_d <= _T_66 @[lsu_lsc_ctl.scala 126:42]
-    addrcheck.io.rs1_d <= rs1_d @[lsu_lsc_ctl.scala 127:42]
-    io.is_sideeffects_m <= addrcheck.io.is_sideeffects_m @[lsu_lsc_ctl.scala 128:42]
-    io.addr_in_dccm_d <= addrcheck.io.addr_in_dccm_d @[lsu_lsc_ctl.scala 129:42]
-    io.addr_in_pic_d <= addrcheck.io.addr_in_pic_d @[lsu_lsc_ctl.scala 130:42]
-    addrcheck.io.scan_mode <= io.scan_mode @[lsu_lsc_ctl.scala 137:42]
-    wire exc_mscause_r : UInt<4>
-    exc_mscause_r <= UInt<4>("h00")
-    wire fir_dccm_access_error_r : UInt<1>
-    fir_dccm_access_error_r <= UInt<1>("h00")
-    wire fir_nondccm_access_error_r : UInt<1>
-    fir_nondccm_access_error_r <= UInt<1>("h00")
-    wire access_fault_r : UInt<1>
-    access_fault_r <= UInt<1>("h00")
-    wire misaligned_fault_r : UInt<1>
-    misaligned_fault_r <= UInt<1>("h00")
-    wire lsu_fir_error_m : UInt<2>
-    lsu_fir_error_m <= UInt<2>("h00")
-    wire fir_dccm_access_error_m : UInt<1>
-    fir_dccm_access_error_m <= UInt<1>("h00")
-    wire fir_nondccm_access_error_m : UInt<1>
-    fir_nondccm_access_error_m <= UInt<1>("h00")
-    reg access_fault_m : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 149:75]
-    access_fault_m <= addrcheck.io.access_fault_d @[lsu_lsc_ctl.scala 149:75]
-    reg misaligned_fault_m : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 150:75]
-    misaligned_fault_m <= addrcheck.io.misaligned_fault_d @[lsu_lsc_ctl.scala 150:75]
-    reg exc_mscause_m : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 151:75]
-    exc_mscause_m <= addrcheck.io.exc_mscause_d @[lsu_lsc_ctl.scala 151:75]
-    reg _T_67 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 152:75]
-    _T_67 <= addrcheck.io.fir_dccm_access_error_d @[lsu_lsc_ctl.scala 152:75]
-    fir_dccm_access_error_m <= _T_67 @[lsu_lsc_ctl.scala 152:38]
-    reg _T_68 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 153:75]
-    _T_68 <= addrcheck.io.fir_nondccm_access_error_d @[lsu_lsc_ctl.scala 153:75]
-    fir_nondccm_access_error_m <= _T_68 @[lsu_lsc_ctl.scala 153:38]
-    node _T_69 = or(access_fault_m, misaligned_fault_m) @[lsu_lsc_ctl.scala 155:34]
-    io.lsu_exc_m <= _T_69 @[lsu_lsc_ctl.scala 155:16]
-    node _T_70 = eq(io.lsu_double_ecc_error_r, UInt<1>("h00")) @[lsu_lsc_ctl.scala 156:64]
-    node _T_71 = and(io.lsu_single_ecc_error_r, _T_70) @[lsu_lsc_ctl.scala 156:62]
-    node _T_72 = or(io.lsu_commit_r, io.lsu_pkt_r.bits.dma) @[lsu_lsc_ctl.scala 156:111]
-    node _T_73 = and(_T_71, _T_72) @[lsu_lsc_ctl.scala 156:92]
-    node _T_74 = and(_T_73, io.lsu_pkt_r.valid) @[lsu_lsc_ctl.scala 156:136]
-    io.lsu_single_ecc_error_incr <= _T_74 @[lsu_lsc_ctl.scala 156:32]
-    node _T_75 = or(access_fault_m, misaligned_fault_m) @[lsu_lsc_ctl.scala 178:46]
-    node _T_76 = or(_T_75, io.lsu_double_ecc_error_m) @[lsu_lsc_ctl.scala 178:67]
-    node _T_77 = and(_T_76, io.lsu_pkt_m.valid) @[lsu_lsc_ctl.scala 178:96]
-    node _T_78 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 178:119]
-    node _T_79 = and(_T_77, _T_78) @[lsu_lsc_ctl.scala 178:117]
-    node _T_80 = eq(io.lsu_pkt_m.bits.fast_int, UInt<1>("h00")) @[lsu_lsc_ctl.scala 178:144]
-    node _T_81 = and(_T_79, _T_80) @[lsu_lsc_ctl.scala 178:142]
-    node _T_82 = eq(io.flush_m_up, UInt<1>("h00")) @[lsu_lsc_ctl.scala 178:174]
-    node _T_83 = and(_T_81, _T_82) @[lsu_lsc_ctl.scala 178:172]
-    lsu_error_pkt_m.valid <= _T_83 @[lsu_lsc_ctl.scala 178:27]
-    node _T_84 = eq(lsu_error_pkt_m.valid, UInt<1>("h00")) @[lsu_lsc_ctl.scala 179:75]
-    node _T_85 = and(io.lsu_single_ecc_error_m, _T_84) @[lsu_lsc_ctl.scala 179:73]
-    node _T_86 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 179:101]
-    node _T_87 = and(_T_85, _T_86) @[lsu_lsc_ctl.scala 179:99]
-    lsu_error_pkt_m.bits.single_ecc_error <= _T_87 @[lsu_lsc_ctl.scala 179:43]
-    lsu_error_pkt_m.bits.inst_type <= io.lsu_pkt_m.bits.store @[lsu_lsc_ctl.scala 180:43]
-    node _T_88 = not(misaligned_fault_m) @[lsu_lsc_ctl.scala 181:46]
-    lsu_error_pkt_m.bits.exc_type <= _T_88 @[lsu_lsc_ctl.scala 181:43]
-    node _T_89 = eq(misaligned_fault_m, UInt<1>("h00")) @[lsu_lsc_ctl.scala 182:80]
-    node _T_90 = and(io.lsu_double_ecc_error_m, _T_89) @[lsu_lsc_ctl.scala 182:78]
-    node _T_91 = eq(access_fault_m, UInt<1>("h00")) @[lsu_lsc_ctl.scala 182:102]
-    node _T_92 = and(_T_90, _T_91) @[lsu_lsc_ctl.scala 182:100]
-    node _T_93 = eq(_T_92, UInt<1>("h01")) @[lsu_lsc_ctl.scala 182:118]
-    node _T_94 = bits(exc_mscause_m, 3, 0) @[lsu_lsc_ctl.scala 182:149]
-    node _T_95 = mux(_T_93, UInt<4>("h01"), _T_94) @[lsu_lsc_ctl.scala 182:49]
-    lsu_error_pkt_m.bits.mscause <= _T_95 @[lsu_lsc_ctl.scala 182:43]
-    node _T_96 = bits(io.lsu_addr_m, 31, 0) @[lsu_lsc_ctl.scala 183:59]
-    lsu_error_pkt_m.bits.addr <= _T_96 @[lsu_lsc_ctl.scala 183:43]
-    node _T_97 = bits(fir_nondccm_access_error_m, 0, 0) @[lsu_lsc_ctl.scala 184:72]
-    node _T_98 = bits(fir_dccm_access_error_m, 0, 0) @[lsu_lsc_ctl.scala 184:117]
-    node _T_99 = and(io.lsu_pkt_m.bits.fast_int, io.lsu_double_ecc_error_m) @[lsu_lsc_ctl.scala 184:166]
-    node _T_100 = bits(_T_99, 0, 0) @[lsu_lsc_ctl.scala 184:195]
-    node _T_101 = mux(_T_100, UInt<2>("h01"), UInt<2>("h00")) @[lsu_lsc_ctl.scala 184:137]
-    node _T_102 = mux(_T_98, UInt<2>("h02"), _T_101) @[lsu_lsc_ctl.scala 184:92]
-    node _T_103 = mux(_T_97, UInt<2>("h03"), _T_102) @[lsu_lsc_ctl.scala 184:44]
-    lsu_fir_error_m <= _T_103 @[lsu_lsc_ctl.scala 184:38]
-    node _T_104 = or(lsu_error_pkt_m.valid, lsu_error_pkt_m.bits.single_ecc_error) @[lsu_lsc_ctl.scala 185:73]
-    node _T_105 = or(_T_104, io.clk_override) @[lsu_lsc_ctl.scala 185:113]
-    node _T_106 = bits(_T_105, 0, 0) @[lib.scala 8:44]
-    node _T_107 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44]
-    inst rvclkhdr of rvclkhdr @[lib.scala 378:23]
-    rvclkhdr.clock <= clock
-    rvclkhdr.reset <= reset
-    rvclkhdr.io.clk <= clock @[lib.scala 380:18]
-    rvclkhdr.io.en <= _T_106 @[lib.scala 381:17]
-    rvclkhdr.io.scan_mode <= _T_107 @[lib.scala 382:24]
-    wire _T_108 : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}} @[lib.scala 384:33]
-    _T_108.bits.addr <= UInt<32>("h00") @[lib.scala 384:33]
-    _T_108.bits.mscause <= UInt<4>("h00") @[lib.scala 384:33]
-    _T_108.bits.exc_type <= UInt<1>("h00") @[lib.scala 384:33]
-    _T_108.bits.inst_type <= UInt<1>("h00") @[lib.scala 384:33]
-    _T_108.bits.single_ecc_error <= UInt<1>("h00") @[lib.scala 384:33]
-    _T_108.valid <= UInt<1>("h00") @[lib.scala 384:33]
-    reg _T_109 : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, rvclkhdr.io.l1clk with : (reset => (reset, _T_108)) @[lib.scala 384:16]
-    _T_109.bits.addr <= lsu_error_pkt_m.bits.addr @[lib.scala 384:16]
-    _T_109.bits.mscause <= lsu_error_pkt_m.bits.mscause @[lib.scala 384:16]
-    _T_109.bits.exc_type <= lsu_error_pkt_m.bits.exc_type @[lib.scala 384:16]
-    _T_109.bits.inst_type <= lsu_error_pkt_m.bits.inst_type @[lib.scala 384:16]
-    _T_109.bits.single_ecc_error <= lsu_error_pkt_m.bits.single_ecc_error @[lib.scala 384:16]
-    _T_109.valid <= lsu_error_pkt_m.valid @[lib.scala 384:16]
-    io.lsu_error_pkt_r.bits.addr <= _T_109.bits.addr @[lsu_lsc_ctl.scala 185:24]
-    io.lsu_error_pkt_r.bits.mscause <= _T_109.bits.mscause @[lsu_lsc_ctl.scala 185:24]
-    io.lsu_error_pkt_r.bits.exc_type <= _T_109.bits.exc_type @[lsu_lsc_ctl.scala 185:24]
-    io.lsu_error_pkt_r.bits.inst_type <= _T_109.bits.inst_type @[lsu_lsc_ctl.scala 185:24]
-    io.lsu_error_pkt_r.bits.single_ecc_error <= _T_109.bits.single_ecc_error @[lsu_lsc_ctl.scala 185:24]
-    io.lsu_error_pkt_r.valid <= _T_109.valid @[lsu_lsc_ctl.scala 185:24]
-    reg _T_110 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 186:83]
-    _T_110 <= lsu_error_pkt_m.bits.single_ecc_error @[lsu_lsc_ctl.scala 186:83]
-    io.lsu_error_pkt_r.bits.single_ecc_error <= _T_110 @[lsu_lsc_ctl.scala 186:46]
-    reg _T_111 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 187:67]
-    _T_111 <= lsu_error_pkt_m.valid @[lsu_lsc_ctl.scala 187:67]
-    io.lsu_error_pkt_r.valid <= _T_111 @[lsu_lsc_ctl.scala 187:30]
-    reg _T_112 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 188:48]
-    _T_112 <= lsu_fir_error_m @[lsu_lsc_ctl.scala 188:48]
-    io.lsu_fir_error <= _T_112 @[lsu_lsc_ctl.scala 188:38]
-    dma_pkt_d.bits.unsign <= UInt<1>("h00") @[lsu_lsc_ctl.scala 190:27]
-    dma_pkt_d.bits.fast_int <= UInt<1>("h00") @[lsu_lsc_ctl.scala 191:27]
-    dma_pkt_d.valid <= io.dma_lsc_ctl.dma_dccm_req @[lsu_lsc_ctl.scala 192:22]
-    dma_pkt_d.bits.dma <= UInt<1>("h01") @[lsu_lsc_ctl.scala 193:27]
-    dma_pkt_d.bits.store <= io.dma_lsc_ctl.dma_mem_write @[lsu_lsc_ctl.scala 194:27]
-    node _T_113 = not(io.dma_lsc_ctl.dma_mem_write) @[lsu_lsc_ctl.scala 195:30]
-    dma_pkt_d.bits.load <= _T_113 @[lsu_lsc_ctl.scala 195:27]
-    node _T_114 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 196:56]
-    node _T_115 = eq(_T_114, UInt<3>("h00")) @[lsu_lsc_ctl.scala 196:62]
-    dma_pkt_d.bits.by <= _T_115 @[lsu_lsc_ctl.scala 196:27]
-    node _T_116 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 197:56]
-    node _T_117 = eq(_T_116, UInt<3>("h01")) @[lsu_lsc_ctl.scala 197:62]
-    dma_pkt_d.bits.half <= _T_117 @[lsu_lsc_ctl.scala 197:27]
-    node _T_118 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 198:56]
-    node _T_119 = eq(_T_118, UInt<3>("h02")) @[lsu_lsc_ctl.scala 198:62]
-    dma_pkt_d.bits.word <= _T_119 @[lsu_lsc_ctl.scala 198:27]
-    node _T_120 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 199:56]
-    node _T_121 = eq(_T_120, UInt<3>("h03")) @[lsu_lsc_ctl.scala 199:62]
-    dma_pkt_d.bits.dword <= _T_121 @[lsu_lsc_ctl.scala 199:27]
-    dma_pkt_d.bits.store_data_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 200:39]
-    dma_pkt_d.bits.load_ldst_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 201:39]
-    dma_pkt_d.bits.store_data_bypass_m <= UInt<1>("h00") @[lsu_lsc_ctl.scala 202:39]
-    wire lsu_ld_datafn_r : UInt<32>
-    lsu_ld_datafn_r <= UInt<32>("h00")
-    wire lsu_ld_datafn_corr_r : UInt<32>
-    lsu_ld_datafn_corr_r <= UInt<32>("h00")
-    wire lsu_ld_datafn_m : UInt<32>
-    lsu_ld_datafn_m <= UInt<32>("h00")
-    node _T_122 = bits(io.dec_lsu_valid_raw_d, 0, 0) @[lsu_lsc_ctl.scala 208:50]
-    node _T_123 = mux(_T_122, io.lsu_p, dma_pkt_d) @[lsu_lsc_ctl.scala 208:26]
-    io.lsu_pkt_d.bits.store_data_bypass_m <= _T_123.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 208:20]
-    io.lsu_pkt_d.bits.load_ldst_bypass_d <= _T_123.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 208:20]
-    io.lsu_pkt_d.bits.store_data_bypass_d <= _T_123.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 208:20]
-    io.lsu_pkt_d.bits.dma <= _T_123.bits.dma @[lsu_lsc_ctl.scala 208:20]
-    io.lsu_pkt_d.bits.unsign <= _T_123.bits.unsign @[lsu_lsc_ctl.scala 208:20]
-    io.lsu_pkt_d.bits.store <= _T_123.bits.store @[lsu_lsc_ctl.scala 208:20]
-    io.lsu_pkt_d.bits.load <= _T_123.bits.load @[lsu_lsc_ctl.scala 208:20]
-    io.lsu_pkt_d.bits.dword <= _T_123.bits.dword @[lsu_lsc_ctl.scala 208:20]
-    io.lsu_pkt_d.bits.word <= _T_123.bits.word @[lsu_lsc_ctl.scala 208:20]
-    io.lsu_pkt_d.bits.half <= _T_123.bits.half @[lsu_lsc_ctl.scala 208:20]
-    io.lsu_pkt_d.bits.by <= _T_123.bits.by @[lsu_lsc_ctl.scala 208:20]
-    io.lsu_pkt_d.bits.fast_int <= _T_123.bits.fast_int @[lsu_lsc_ctl.scala 208:20]
-    io.lsu_pkt_d.valid <= _T_123.valid @[lsu_lsc_ctl.scala 208:20]
-    lsu_pkt_m_in.bits.store_data_bypass_m <= io.lsu_pkt_d.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 209:20]
-    lsu_pkt_m_in.bits.load_ldst_bypass_d <= io.lsu_pkt_d.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 209:20]
-    lsu_pkt_m_in.bits.store_data_bypass_d <= io.lsu_pkt_d.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 209:20]
-    lsu_pkt_m_in.bits.dma <= io.lsu_pkt_d.bits.dma @[lsu_lsc_ctl.scala 209:20]
-    lsu_pkt_m_in.bits.unsign <= io.lsu_pkt_d.bits.unsign @[lsu_lsc_ctl.scala 209:20]
-    lsu_pkt_m_in.bits.store <= io.lsu_pkt_d.bits.store @[lsu_lsc_ctl.scala 209:20]
-    lsu_pkt_m_in.bits.load <= io.lsu_pkt_d.bits.load @[lsu_lsc_ctl.scala 209:20]
-    lsu_pkt_m_in.bits.dword <= io.lsu_pkt_d.bits.dword @[lsu_lsc_ctl.scala 209:20]
-    lsu_pkt_m_in.bits.word <= io.lsu_pkt_d.bits.word @[lsu_lsc_ctl.scala 209:20]
-    lsu_pkt_m_in.bits.half <= io.lsu_pkt_d.bits.half @[lsu_lsc_ctl.scala 209:20]
-    lsu_pkt_m_in.bits.by <= io.lsu_pkt_d.bits.by @[lsu_lsc_ctl.scala 209:20]
-    lsu_pkt_m_in.bits.fast_int <= io.lsu_pkt_d.bits.fast_int @[lsu_lsc_ctl.scala 209:20]
-    lsu_pkt_m_in.valid <= io.lsu_pkt_d.valid @[lsu_lsc_ctl.scala 209:20]
-    lsu_pkt_r_in.bits.store_data_bypass_m <= io.lsu_pkt_m.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 210:20]
-    lsu_pkt_r_in.bits.load_ldst_bypass_d <= io.lsu_pkt_m.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 210:20]
-    lsu_pkt_r_in.bits.store_data_bypass_d <= io.lsu_pkt_m.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 210:20]
-    lsu_pkt_r_in.bits.dma <= io.lsu_pkt_m.bits.dma @[lsu_lsc_ctl.scala 210:20]
-    lsu_pkt_r_in.bits.unsign <= io.lsu_pkt_m.bits.unsign @[lsu_lsc_ctl.scala 210:20]
-    lsu_pkt_r_in.bits.store <= io.lsu_pkt_m.bits.store @[lsu_lsc_ctl.scala 210:20]
-    lsu_pkt_r_in.bits.load <= io.lsu_pkt_m.bits.load @[lsu_lsc_ctl.scala 210:20]
-    lsu_pkt_r_in.bits.dword <= io.lsu_pkt_m.bits.dword @[lsu_lsc_ctl.scala 210:20]
-    lsu_pkt_r_in.bits.word <= io.lsu_pkt_m.bits.word @[lsu_lsc_ctl.scala 210:20]
-    lsu_pkt_r_in.bits.half <= io.lsu_pkt_m.bits.half @[lsu_lsc_ctl.scala 210:20]
-    lsu_pkt_r_in.bits.by <= io.lsu_pkt_m.bits.by @[lsu_lsc_ctl.scala 210:20]
-    lsu_pkt_r_in.bits.fast_int <= io.lsu_pkt_m.bits.fast_int @[lsu_lsc_ctl.scala 210:20]
-    lsu_pkt_r_in.valid <= io.lsu_pkt_m.valid @[lsu_lsc_ctl.scala 210:20]
-    node _T_124 = eq(io.lsu_p.bits.fast_int, UInt<1>("h00")) @[lsu_lsc_ctl.scala 212:64]
-    node _T_125 = and(io.flush_m_up, _T_124) @[lsu_lsc_ctl.scala 212:61]
-    node _T_126 = eq(_T_125, UInt<1>("h00")) @[lsu_lsc_ctl.scala 212:45]
-    node _T_127 = and(io.lsu_p.valid, _T_126) @[lsu_lsc_ctl.scala 212:43]
-    node _T_128 = or(_T_127, io.dma_lsc_ctl.dma_dccm_req) @[lsu_lsc_ctl.scala 212:90]
-    io.lsu_pkt_d.valid <= _T_128 @[lsu_lsc_ctl.scala 212:24]
-    node _T_129 = eq(io.lsu_pkt_d.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 213:68]
-    node _T_130 = and(io.flush_m_up, _T_129) @[lsu_lsc_ctl.scala 213:65]
-    node _T_131 = eq(_T_130, UInt<1>("h00")) @[lsu_lsc_ctl.scala 213:49]
-    node _T_132 = and(io.lsu_pkt_d.valid, _T_131) @[lsu_lsc_ctl.scala 213:47]
-    lsu_pkt_m_in.valid <= _T_132 @[lsu_lsc_ctl.scala 213:24]
-    node _T_133 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 214:68]
-    node _T_134 = and(io.flush_m_up, _T_133) @[lsu_lsc_ctl.scala 214:65]
-    node _T_135 = eq(_T_134, UInt<1>("h00")) @[lsu_lsc_ctl.scala 214:49]
-    node _T_136 = and(io.lsu_pkt_m.valid, _T_135) @[lsu_lsc_ctl.scala 214:47]
-    lsu_pkt_r_in.valid <= _T_136 @[lsu_lsc_ctl.scala 214:24]
-    wire _T_137 : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 216:91]
-    _T_137.bits.store_data_bypass_m <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91]
-    _T_137.bits.load_ldst_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91]
-    _T_137.bits.store_data_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91]
-    _T_137.bits.dma <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91]
-    _T_137.bits.unsign <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91]
-    _T_137.bits.store <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91]
-    _T_137.bits.load <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91]
-    _T_137.bits.dword <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91]
-    _T_137.bits.word <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91]
-    _T_137.bits.half <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91]
-    _T_137.bits.by <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91]
-    _T_137.bits.fast_int <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91]
-    _T_137.valid <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91]
-    reg _T_138 : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, io.lsu_c1_m_clk with : (reset => (reset, _T_137)) @[lsu_lsc_ctl.scala 216:65]
-    _T_138.bits.store_data_bypass_m <= lsu_pkt_m_in.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 216:65]
-    _T_138.bits.load_ldst_bypass_d <= lsu_pkt_m_in.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 216:65]
-    _T_138.bits.store_data_bypass_d <= lsu_pkt_m_in.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 216:65]
-    _T_138.bits.dma <= lsu_pkt_m_in.bits.dma @[lsu_lsc_ctl.scala 216:65]
-    _T_138.bits.unsign <= lsu_pkt_m_in.bits.unsign @[lsu_lsc_ctl.scala 216:65]
-    _T_138.bits.store <= lsu_pkt_m_in.bits.store @[lsu_lsc_ctl.scala 216:65]
-    _T_138.bits.load <= lsu_pkt_m_in.bits.load @[lsu_lsc_ctl.scala 216:65]
-    _T_138.bits.dword <= lsu_pkt_m_in.bits.dword @[lsu_lsc_ctl.scala 216:65]
-    _T_138.bits.word <= lsu_pkt_m_in.bits.word @[lsu_lsc_ctl.scala 216:65]
-    _T_138.bits.half <= lsu_pkt_m_in.bits.half @[lsu_lsc_ctl.scala 216:65]
-    _T_138.bits.by <= lsu_pkt_m_in.bits.by @[lsu_lsc_ctl.scala 216:65]
-    _T_138.bits.fast_int <= lsu_pkt_m_in.bits.fast_int @[lsu_lsc_ctl.scala 216:65]
-    _T_138.valid <= lsu_pkt_m_in.valid @[lsu_lsc_ctl.scala 216:65]
-    io.lsu_pkt_m.bits.store_data_bypass_m <= _T_138.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 216:28]
-    io.lsu_pkt_m.bits.load_ldst_bypass_d <= _T_138.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 216:28]
-    io.lsu_pkt_m.bits.store_data_bypass_d <= _T_138.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 216:28]
-    io.lsu_pkt_m.bits.dma <= _T_138.bits.dma @[lsu_lsc_ctl.scala 216:28]
-    io.lsu_pkt_m.bits.unsign <= _T_138.bits.unsign @[lsu_lsc_ctl.scala 216:28]
-    io.lsu_pkt_m.bits.store <= _T_138.bits.store @[lsu_lsc_ctl.scala 216:28]
-    io.lsu_pkt_m.bits.load <= _T_138.bits.load @[lsu_lsc_ctl.scala 216:28]
-    io.lsu_pkt_m.bits.dword <= _T_138.bits.dword @[lsu_lsc_ctl.scala 216:28]
-    io.lsu_pkt_m.bits.word <= _T_138.bits.word @[lsu_lsc_ctl.scala 216:28]
-    io.lsu_pkt_m.bits.half <= _T_138.bits.half @[lsu_lsc_ctl.scala 216:28]
-    io.lsu_pkt_m.bits.by <= _T_138.bits.by @[lsu_lsc_ctl.scala 216:28]
-    io.lsu_pkt_m.bits.fast_int <= _T_138.bits.fast_int @[lsu_lsc_ctl.scala 216:28]
-    io.lsu_pkt_m.valid <= _T_138.valid @[lsu_lsc_ctl.scala 216:28]
-    wire _T_139 : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 217:91]
-    _T_139.bits.store_data_bypass_m <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
-    _T_139.bits.load_ldst_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
-    _T_139.bits.store_data_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
-    _T_139.bits.dma <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
-    _T_139.bits.unsign <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
-    _T_139.bits.store <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
-    _T_139.bits.load <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
-    _T_139.bits.dword <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
-    _T_139.bits.word <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
-    _T_139.bits.half <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
-    _T_139.bits.by <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
-    _T_139.bits.fast_int <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
-    _T_139.valid <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
-    reg _T_140 : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, io.lsu_c1_r_clk with : (reset => (reset, _T_139)) @[lsu_lsc_ctl.scala 217:65]
-    _T_140.bits.store_data_bypass_m <= lsu_pkt_r_in.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 217:65]
-    _T_140.bits.load_ldst_bypass_d <= lsu_pkt_r_in.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 217:65]
-    _T_140.bits.store_data_bypass_d <= lsu_pkt_r_in.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 217:65]
-    _T_140.bits.dma <= lsu_pkt_r_in.bits.dma @[lsu_lsc_ctl.scala 217:65]
-    _T_140.bits.unsign <= lsu_pkt_r_in.bits.unsign @[lsu_lsc_ctl.scala 217:65]
-    _T_140.bits.store <= lsu_pkt_r_in.bits.store @[lsu_lsc_ctl.scala 217:65]
-    _T_140.bits.load <= lsu_pkt_r_in.bits.load @[lsu_lsc_ctl.scala 217:65]
-    _T_140.bits.dword <= lsu_pkt_r_in.bits.dword @[lsu_lsc_ctl.scala 217:65]
-    _T_140.bits.word <= lsu_pkt_r_in.bits.word @[lsu_lsc_ctl.scala 217:65]
-    _T_140.bits.half <= lsu_pkt_r_in.bits.half @[lsu_lsc_ctl.scala 217:65]
-    _T_140.bits.by <= lsu_pkt_r_in.bits.by @[lsu_lsc_ctl.scala 217:65]
-    _T_140.bits.fast_int <= lsu_pkt_r_in.bits.fast_int @[lsu_lsc_ctl.scala 217:65]
-    _T_140.valid <= lsu_pkt_r_in.valid @[lsu_lsc_ctl.scala 217:65]
-    io.lsu_pkt_r.bits.store_data_bypass_m <= _T_140.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 217:28]
-    io.lsu_pkt_r.bits.load_ldst_bypass_d <= _T_140.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 217:28]
-    io.lsu_pkt_r.bits.store_data_bypass_d <= _T_140.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 217:28]
-    io.lsu_pkt_r.bits.dma <= _T_140.bits.dma @[lsu_lsc_ctl.scala 217:28]
-    io.lsu_pkt_r.bits.unsign <= _T_140.bits.unsign @[lsu_lsc_ctl.scala 217:28]
-    io.lsu_pkt_r.bits.store <= _T_140.bits.store @[lsu_lsc_ctl.scala 217:28]
-    io.lsu_pkt_r.bits.load <= _T_140.bits.load @[lsu_lsc_ctl.scala 217:28]
-    io.lsu_pkt_r.bits.dword <= _T_140.bits.dword @[lsu_lsc_ctl.scala 217:28]
-    io.lsu_pkt_r.bits.word <= _T_140.bits.word @[lsu_lsc_ctl.scala 217:28]
-    io.lsu_pkt_r.bits.half <= _T_140.bits.half @[lsu_lsc_ctl.scala 217:28]
-    io.lsu_pkt_r.bits.by <= _T_140.bits.by @[lsu_lsc_ctl.scala 217:28]
-    io.lsu_pkt_r.bits.fast_int <= _T_140.bits.fast_int @[lsu_lsc_ctl.scala 217:28]
-    io.lsu_pkt_r.valid <= _T_140.valid @[lsu_lsc_ctl.scala 217:28]
-    reg _T_141 : UInt<1>, io.lsu_c2_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 218:65]
-    _T_141 <= lsu_pkt_m_in.valid @[lsu_lsc_ctl.scala 218:65]
-    io.lsu_pkt_m.valid <= _T_141 @[lsu_lsc_ctl.scala 218:28]
-    reg _T_142 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 219:65]
-    _T_142 <= lsu_pkt_r_in.valid @[lsu_lsc_ctl.scala 219:65]
-    io.lsu_pkt_r.valid <= _T_142 @[lsu_lsc_ctl.scala 219:28]
-    node _T_143 = bits(io.dma_lsc_ctl.dma_mem_wdata, 63, 0) @[lsu_lsc_ctl.scala 221:59]
-    node _T_144 = bits(io.dma_lsc_ctl.dma_mem_addr, 2, 0) @[lsu_lsc_ctl.scala 221:100]
-    node _T_145 = cat(_T_144, UInt<3>("h00")) @[Cat.scala 29:58]
-    node dma_mem_wdata_shifted = dshr(_T_143, _T_145) @[lsu_lsc_ctl.scala 221:66]
-    node _T_146 = bits(io.dma_lsc_ctl.dma_dccm_req, 0, 0) @[lsu_lsc_ctl.scala 222:63]
-    node _T_147 = bits(dma_mem_wdata_shifted, 31, 0) @[lsu_lsc_ctl.scala 222:91]
-    node _T_148 = bits(io.lsu_exu.exu_lsu_rs2_d, 31, 0) @[lsu_lsc_ctl.scala 222:122]
-    node store_data_d = mux(_T_146, _T_147, _T_148) @[lsu_lsc_ctl.scala 222:34]
-    node _T_149 = bits(io.lsu_pkt_d.bits.store_data_bypass_d, 0, 0) @[lsu_lsc_ctl.scala 223:73]
-    node _T_150 = bits(io.lsu_result_m, 31, 0) @[lsu_lsc_ctl.scala 223:95]
-    node _T_151 = bits(store_data_d, 31, 0) @[lsu_lsc_ctl.scala 223:114]
-    node store_data_m_in = mux(_T_149, _T_150, _T_151) @[lsu_lsc_ctl.scala 223:34]
-    reg store_data_pre_m : UInt, io.lsu_store_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 225:72]
-    store_data_pre_m <= store_data_m_in @[lsu_lsc_ctl.scala 225:72]
-    reg _T_152 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 226:62]
-    _T_152 <= io.lsu_addr_d @[lsu_lsc_ctl.scala 226:62]
-    io.lsu_addr_m <= _T_152 @[lsu_lsc_ctl.scala 226:24]
-    reg _T_153 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 227:62]
-    _T_153 <= io.lsu_addr_m @[lsu_lsc_ctl.scala 227:62]
-    io.lsu_addr_r <= _T_153 @[lsu_lsc_ctl.scala 227:24]
-    node _T_154 = bits(io.ldst_dual_m, 0, 0) @[lib.scala 8:44]
-    node _T_155 = bits(io.lsu_addr_m, 31, 3) @[lsu_lsc_ctl.scala 229:71]
-    node _T_156 = mux(_T_154, end_addr_pre_m, _T_155) @[lsu_lsc_ctl.scala 229:27]
-    node _T_157 = bits(io.end_addr_d, 2, 0) @[lsu_lsc_ctl.scala 229:128]
-    reg _T_158 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 229:114]
-    _T_158 <= _T_157 @[lsu_lsc_ctl.scala 229:114]
-    node _T_159 = cat(_T_156, _T_158) @[Cat.scala 29:58]
-    io.end_addr_m <= _T_159 @[lsu_lsc_ctl.scala 229:17]
-    node _T_160 = bits(io.ldst_dual_r, 0, 0) @[lib.scala 8:44]
-    node _T_161 = bits(io.lsu_addr_r, 31, 3) @[lsu_lsc_ctl.scala 230:71]
-    node _T_162 = mux(_T_160, end_addr_pre_r, _T_161) @[lsu_lsc_ctl.scala 230:27]
-    node _T_163 = bits(io.end_addr_m, 2, 0) @[lsu_lsc_ctl.scala 230:128]
-    reg _T_164 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 230:114]
-    _T_164 <= _T_163 @[lsu_lsc_ctl.scala 230:114]
-    node _T_165 = cat(_T_162, _T_164) @[Cat.scala 29:58]
-    io.end_addr_r <= _T_165 @[lsu_lsc_ctl.scala 230:17]
-    node _T_166 = bits(io.end_addr_d, 31, 3) @[lsu_lsc_ctl.scala 232:41]
-    node _T_167 = and(io.lsu_pkt_d.valid, io.ldst_dual_d) @[lsu_lsc_ctl.scala 232:69]
-    node _T_168 = or(_T_167, io.clk_override) @[lsu_lsc_ctl.scala 232:87]
-    node _T_169 = bits(_T_168, 0, 0) @[lib.scala 8:44]
-    node _T_170 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44]
-    inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 368:23]
-    rvclkhdr_1.clock <= clock
-    rvclkhdr_1.reset <= reset
-    rvclkhdr_1.io.clk <= clock @[lib.scala 370:18]
-    rvclkhdr_1.io.en <= _T_169 @[lib.scala 371:17]
-    rvclkhdr_1.io.scan_mode <= _T_170 @[lib.scala 372:24]
-    reg _T_171 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
-    _T_171 <= _T_166 @[lib.scala 374:16]
-    end_addr_pre_m <= _T_171 @[lsu_lsc_ctl.scala 232:18]
-    node _T_172 = bits(io.end_addr_m, 31, 3) @[lsu_lsc_ctl.scala 233:41]
-    node _T_173 = and(io.lsu_pkt_m.valid, io.ldst_dual_m) @[lsu_lsc_ctl.scala 233:69]
-    node _T_174 = or(_T_173, io.clk_override) @[lsu_lsc_ctl.scala 233:87]
-    node _T_175 = bits(_T_174, 0, 0) @[lib.scala 8:44]
-    node _T_176 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44]
-    inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 368:23]
-    rvclkhdr_2.clock <= clock
-    rvclkhdr_2.reset <= reset
-    rvclkhdr_2.io.clk <= clock @[lib.scala 370:18]
-    rvclkhdr_2.io.en <= _T_175 @[lib.scala 371:17]
-    rvclkhdr_2.io.scan_mode <= _T_176 @[lib.scala 372:24]
-    reg _T_177 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
-    _T_177 <= _T_172 @[lib.scala 374:16]
-    end_addr_pre_r <= _T_177 @[lsu_lsc_ctl.scala 233:18]
-    reg _T_178 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 236:62]
-    _T_178 <= io.end_addr_d @[lsu_lsc_ctl.scala 236:62]
-    io.end_addr_m <= _T_178 @[lsu_lsc_ctl.scala 236:24]
-    reg _T_179 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 237:62]
-    _T_179 <= io.end_addr_m @[lsu_lsc_ctl.scala 237:62]
-    io.end_addr_r <= _T_179 @[lsu_lsc_ctl.scala 237:24]
-    reg _T_180 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 238:62]
-    _T_180 <= io.addr_in_dccm_d @[lsu_lsc_ctl.scala 238:62]
-    io.addr_in_dccm_m <= _T_180 @[lsu_lsc_ctl.scala 238:24]
-    reg _T_181 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 239:62]
-    _T_181 <= io.addr_in_dccm_m @[lsu_lsc_ctl.scala 239:62]
-    io.addr_in_dccm_r <= _T_181 @[lsu_lsc_ctl.scala 239:24]
-    reg _T_182 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 240:62]
-    _T_182 <= io.addr_in_pic_d @[lsu_lsc_ctl.scala 240:62]
-    io.addr_in_pic_m <= _T_182 @[lsu_lsc_ctl.scala 240:24]
-    reg _T_183 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 241:62]
-    _T_183 <= io.addr_in_pic_m @[lsu_lsc_ctl.scala 241:62]
-    io.addr_in_pic_r <= _T_183 @[lsu_lsc_ctl.scala 241:24]
-    reg _T_184 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 242:62]
-    _T_184 <= addrcheck.io.addr_external_d @[lsu_lsc_ctl.scala 242:62]
-    io.addr_external_m <= _T_184 @[lsu_lsc_ctl.scala 242:24]
-    reg addr_external_r : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 243:66]
-    addr_external_r <= io.addr_external_m @[lsu_lsc_ctl.scala 243:66]
-    node _T_185 = or(io.addr_external_m, io.clk_override) @[lsu_lsc_ctl.scala 244:77]
-    node _T_186 = bits(_T_185, 0, 0) @[lib.scala 8:44]
-    node _T_187 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44]
-    inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 368:23]
-    rvclkhdr_3.clock <= clock
-    rvclkhdr_3.reset <= reset
-    rvclkhdr_3.io.clk <= clock @[lib.scala 370:18]
-    rvclkhdr_3.io.en <= _T_186 @[lib.scala 371:17]
-    rvclkhdr_3.io.scan_mode <= _T_187 @[lib.scala 372:24]
-    reg bus_read_data_r : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
-    bus_read_data_r <= io.bus_read_data_m @[lib.scala 374:16]
-    node _T_188 = bits(io.lsu_ld_data_corr_r, 31, 1) @[lsu_lsc_ctl.scala 247:52]
-    io.lsu_fir_addr <= _T_188 @[lsu_lsc_ctl.scala 247:28]
-    io.lsu_addr_d <= full_addr_d @[lsu_lsc_ctl.scala 249:28]
-    node _T_189 = or(io.lsu_pkt_r.bits.store, io.lsu_pkt_r.bits.load) @[lsu_lsc_ctl.scala 251:68]
-    node _T_190 = and(io.lsu_pkt_r.valid, _T_189) @[lsu_lsc_ctl.scala 251:41]
-    node _T_191 = eq(io.flush_r, UInt<1>("h00")) @[lsu_lsc_ctl.scala 251:96]
-    node _T_192 = and(_T_190, _T_191) @[lsu_lsc_ctl.scala 251:94]
-    node _T_193 = eq(io.lsu_pkt_r.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 251:110]
-    node _T_194 = and(_T_192, _T_193) @[lsu_lsc_ctl.scala 251:108]
-    io.lsu_commit_r <= _T_194 @[lsu_lsc_ctl.scala 251:19]
-    node _T_195 = bits(io.picm_mask_data_m, 31, 0) @[lsu_lsc_ctl.scala 252:52]
-    node _T_196 = eq(io.addr_in_pic_m, UInt<1>("h00")) @[lsu_lsc_ctl.scala 252:69]
-    node _T_197 = bits(_T_196, 0, 0) @[Bitwise.scala 72:15]
-    node _T_198 = mux(_T_197, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
-    node _T_199 = or(_T_195, _T_198) @[lsu_lsc_ctl.scala 252:59]
-    node _T_200 = bits(io.lsu_pkt_m.bits.store_data_bypass_m, 0, 0) @[lsu_lsc_ctl.scala 252:133]
-    node _T_201 = mux(_T_200, io.lsu_result_m, store_data_pre_m) @[lsu_lsc_ctl.scala 252:94]
-    node _T_202 = and(_T_199, _T_201) @[lsu_lsc_ctl.scala 252:89]
-    io.store_data_m <= _T_202 @[lsu_lsc_ctl.scala 252:29]
-    node _T_203 = bits(io.addr_external_m, 0, 0) @[lsu_lsc_ctl.scala 273:53]
-    node _T_204 = mux(_T_203, io.bus_read_data_m, io.lsu_ld_data_m) @[lsu_lsc_ctl.scala 273:33]
-    lsu_ld_datafn_m <= _T_204 @[lsu_lsc_ctl.scala 273:27]
-    node _T_205 = eq(addr_external_r, UInt<1>("h01")) @[lsu_lsc_ctl.scala 274:49]
-    node _T_206 = mux(_T_205, bus_read_data_r, io.lsu_ld_data_corr_r) @[lsu_lsc_ctl.scala 274:33]
-    lsu_ld_datafn_corr_r <= _T_206 @[lsu_lsc_ctl.scala 274:27]
-    node _T_207 = and(io.lsu_pkt_m.bits.unsign, io.lsu_pkt_m.bits.by) @[lsu_lsc_ctl.scala 275:66]
-    node _T_208 = bits(_T_207, 0, 0) @[Bitwise.scala 72:15]
-    node _T_209 = mux(_T_208, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
-    node _T_210 = bits(lsu_ld_datafn_m, 7, 0) @[lsu_lsc_ctl.scala 275:125]
-    node _T_211 = cat(UInt<24>("h00"), _T_210) @[Cat.scala 29:58]
-    node _T_212 = and(_T_209, _T_211) @[lsu_lsc_ctl.scala 275:94]
-    node _T_213 = and(io.lsu_pkt_m.bits.unsign, io.lsu_pkt_m.bits.half) @[lsu_lsc_ctl.scala 276:43]
-    node _T_214 = bits(_T_213, 0, 0) @[Bitwise.scala 72:15]
-    node _T_215 = mux(_T_214, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
-    node _T_216 = bits(lsu_ld_datafn_m, 15, 0) @[lsu_lsc_ctl.scala 276:102]
-    node _T_217 = cat(UInt<16>("h00"), _T_216) @[Cat.scala 29:58]
-    node _T_218 = and(_T_215, _T_217) @[lsu_lsc_ctl.scala 276:71]
-    node _T_219 = or(_T_212, _T_218) @[lsu_lsc_ctl.scala 275:133]
-    node _T_220 = eq(io.lsu_pkt_m.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 277:17]
-    node _T_221 = and(_T_220, io.lsu_pkt_m.bits.by) @[lsu_lsc_ctl.scala 277:43]
-    node _T_222 = bits(_T_221, 0, 0) @[Bitwise.scala 72:15]
-    node _T_223 = mux(_T_222, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
-    node _T_224 = bits(lsu_ld_datafn_m, 7, 7) @[lsu_lsc_ctl.scala 277:102]
-    node _T_225 = bits(_T_224, 0, 0) @[Bitwise.scala 72:15]
-    node _T_226 = mux(_T_225, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12]
-    node _T_227 = bits(lsu_ld_datafn_m, 7, 0) @[lsu_lsc_ctl.scala 277:125]
-    node _T_228 = cat(_T_226, _T_227) @[Cat.scala 29:58]
-    node _T_229 = and(_T_223, _T_228) @[lsu_lsc_ctl.scala 277:71]
-    node _T_230 = or(_T_219, _T_229) @[lsu_lsc_ctl.scala 276:114]
-    node _T_231 = eq(io.lsu_pkt_m.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 278:17]
-    node _T_232 = and(_T_231, io.lsu_pkt_m.bits.half) @[lsu_lsc_ctl.scala 278:43]
-    node _T_233 = bits(_T_232, 0, 0) @[Bitwise.scala 72:15]
-    node _T_234 = mux(_T_233, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
-    node _T_235 = bits(lsu_ld_datafn_m, 15, 15) @[lsu_lsc_ctl.scala 278:101]
-    node _T_236 = bits(_T_235, 0, 0) @[Bitwise.scala 72:15]
-    node _T_237 = mux(_T_236, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12]
-    node _T_238 = bits(lsu_ld_datafn_m, 15, 0) @[lsu_lsc_ctl.scala 278:125]
-    node _T_239 = cat(_T_237, _T_238) @[Cat.scala 29:58]
-    node _T_240 = and(_T_234, _T_239) @[lsu_lsc_ctl.scala 278:71]
-    node _T_241 = or(_T_230, _T_240) @[lsu_lsc_ctl.scala 277:134]
-    node _T_242 = bits(io.lsu_pkt_m.bits.word, 0, 0) @[Bitwise.scala 72:15]
-    node _T_243 = mux(_T_242, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
-    node _T_244 = bits(lsu_ld_datafn_m, 31, 0) @[lsu_lsc_ctl.scala 279:60]
-    node _T_245 = and(_T_243, _T_244) @[lsu_lsc_ctl.scala 279:43]
-    node _T_246 = or(_T_241, _T_245) @[lsu_lsc_ctl.scala 278:134]
-    io.lsu_result_m <= _T_246 @[lsu_lsc_ctl.scala 275:27]
-    node _T_247 = and(io.lsu_pkt_r.bits.unsign, io.lsu_pkt_r.bits.by) @[lsu_lsc_ctl.scala 280:66]
-    node _T_248 = bits(_T_247, 0, 0) @[Bitwise.scala 72:15]
-    node _T_249 = mux(_T_248, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
-    node _T_250 = bits(lsu_ld_datafn_corr_r, 7, 0) @[lsu_lsc_ctl.scala 280:130]
-    node _T_251 = cat(UInt<24>("h00"), _T_250) @[Cat.scala 29:58]
-    node _T_252 = and(_T_249, _T_251) @[lsu_lsc_ctl.scala 280:94]
-    node _T_253 = and(io.lsu_pkt_r.bits.unsign, io.lsu_pkt_r.bits.half) @[lsu_lsc_ctl.scala 281:43]
-    node _T_254 = bits(_T_253, 0, 0) @[Bitwise.scala 72:15]
-    node _T_255 = mux(_T_254, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
-    node _T_256 = bits(lsu_ld_datafn_corr_r, 15, 0) @[lsu_lsc_ctl.scala 281:107]
-    node _T_257 = cat(UInt<16>("h00"), _T_256) @[Cat.scala 29:58]
-    node _T_258 = and(_T_255, _T_257) @[lsu_lsc_ctl.scala 281:71]
-    node _T_259 = or(_T_252, _T_258) @[lsu_lsc_ctl.scala 280:138]
-    node _T_260 = eq(io.lsu_pkt_r.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 282:17]
-    node _T_261 = and(_T_260, io.lsu_pkt_r.bits.by) @[lsu_lsc_ctl.scala 282:43]
-    node _T_262 = bits(_T_261, 0, 0) @[Bitwise.scala 72:15]
-    node _T_263 = mux(_T_262, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
-    node _T_264 = bits(lsu_ld_datafn_corr_r, 7, 7) @[lsu_lsc_ctl.scala 282:107]
-    node _T_265 = bits(_T_264, 0, 0) @[Bitwise.scala 72:15]
-    node _T_266 = mux(_T_265, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12]
-    node _T_267 = bits(lsu_ld_datafn_corr_r, 7, 0) @[lsu_lsc_ctl.scala 282:135]
-    node _T_268 = cat(_T_266, _T_267) @[Cat.scala 29:58]
-    node _T_269 = and(_T_263, _T_268) @[lsu_lsc_ctl.scala 282:71]
-    node _T_270 = or(_T_259, _T_269) @[lsu_lsc_ctl.scala 281:119]
-    node _T_271 = eq(io.lsu_pkt_r.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 283:17]
-    node _T_272 = and(_T_271, io.lsu_pkt_r.bits.half) @[lsu_lsc_ctl.scala 283:43]
-    node _T_273 = bits(_T_272, 0, 0) @[Bitwise.scala 72:15]
-    node _T_274 = mux(_T_273, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
-    node _T_275 = bits(lsu_ld_datafn_corr_r, 15, 15) @[lsu_lsc_ctl.scala 283:106]
-    node _T_276 = bits(_T_275, 0, 0) @[Bitwise.scala 72:15]
-    node _T_277 = mux(_T_276, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12]
-    node _T_278 = bits(lsu_ld_datafn_corr_r, 15, 0) @[lsu_lsc_ctl.scala 283:135]
-    node _T_279 = cat(_T_277, _T_278) @[Cat.scala 29:58]
-    node _T_280 = and(_T_274, _T_279) @[lsu_lsc_ctl.scala 283:71]
-    node _T_281 = or(_T_270, _T_280) @[lsu_lsc_ctl.scala 282:144]
-    node _T_282 = bits(io.lsu_pkt_r.bits.word, 0, 0) @[Bitwise.scala 72:15]
-    node _T_283 = mux(_T_282, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
-    node _T_284 = bits(lsu_ld_datafn_corr_r, 31, 0) @[lsu_lsc_ctl.scala 284:65]
-    node _T_285 = and(_T_283, _T_284) @[lsu_lsc_ctl.scala 284:43]
-    node _T_286 = or(_T_281, _T_285) @[lsu_lsc_ctl.scala 283:144]
-    io.lsu_result_corr_r <= _T_286 @[lsu_lsc_ctl.scala 280:27]
-    
   extmodule gated_latch_4 : 
     output Q : Clock
     input CK : Clock
@@ -1047,2160 +1044,6 @@ circuit lsu :
     clkhdr.EN <= io.en @[lib.scala 337:18]
     clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
     
-  module lsu_dccm_ctl : 
-    input clock : Clock
-    input reset : AsyncReset
-    output io : {flip clk_override : UInt<1>, flip lsu_c2_m_clk : Clock, flip lsu_c2_r_clk : Clock, flip lsu_free_c2_clk : Clock, flip lsu_c1_r_clk : Clock, flip lsu_store_c1_r_clk : Clock, flip lsu_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_pkt_r : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip addr_in_dccm_d : UInt<1>, flip addr_in_dccm_m : UInt<1>, flip addr_in_dccm_r : UInt<1>, flip addr_in_pic_d : UInt<1>, flip addr_in_pic_m : UInt<1>, flip addr_in_pic_r : UInt<1>, flip lsu_raw_fwd_lo_r : UInt<1>, flip lsu_raw_fwd_hi_r : UInt<1>, flip lsu_commit_r : UInt<1>, flip ldst_dual_m : UInt<1>, flip ldst_dual_r : UInt<1>, flip lsu_addr_d : UInt<32>, flip lsu_addr_m : UInt<16>, flip lsu_addr_r : UInt<32>, flip end_addr_d : UInt<16>, flip end_addr_m : UInt<16>, flip end_addr_r : UInt<16>, flip stbuf_reqvld_any : UInt<1>, flip stbuf_addr_any : UInt<16>, flip stbuf_data_any : UInt<32>, flip stbuf_ecc_any : UInt<7>, flip stbuf_fwddata_hi_m : UInt<32>, flip stbuf_fwddata_lo_m : UInt<32>, flip stbuf_fwdbyteen_lo_m : UInt<4>, flip stbuf_fwdbyteen_hi_m : UInt<4>, dccm_rdata_hi_r : UInt<32>, dccm_rdata_lo_r : UInt<32>, dccm_data_ecc_hi_r : UInt<7>, dccm_data_ecc_lo_r : UInt<7>, lsu_ld_data_r : UInt<32>, lsu_ld_data_corr_r : UInt<32>, flip lsu_double_ecc_error_r : UInt<1>, flip single_ecc_error_hi_r : UInt<1>, flip single_ecc_error_lo_r : UInt<1>, flip sec_data_hi_r : UInt<32>, flip sec_data_lo_r : UInt<32>, flip sec_data_hi_r_ff : UInt<32>, flip sec_data_lo_r_ff : UInt<32>, flip sec_data_ecc_hi_r_ff : UInt<7>, flip sec_data_ecc_lo_r_ff : UInt<7>, dccm_rdata_hi_m : UInt<32>, dccm_rdata_lo_m : UInt<32>, dccm_data_ecc_hi_m : UInt<7>, dccm_data_ecc_lo_m : UInt<7>, lsu_ld_data_m : UInt<32>, flip lsu_double_ecc_error_m : UInt<1>, flip sec_data_hi_m : UInt<32>, flip sec_data_lo_m : UInt<32>, flip store_data_m : UInt<32>, flip dma_dccm_wen : UInt<1>, flip dma_pic_wen : UInt<1>, flip dma_mem_tag_m : UInt<3>, flip dma_dccm_wdata_lo : UInt<32>, flip dma_dccm_wdata_hi : UInt<32>, flip dma_dccm_wdata_ecc_hi : UInt<7>, flip dma_dccm_wdata_ecc_lo : UInt<7>, store_data_hi_r : UInt<32>, store_data_lo_r : UInt<32>, store_datafn_hi_r : UInt<32>, store_datafn_lo_r : UInt<32>, store_data_r : UInt<32>, ld_single_ecc_error_r : UInt<1>, ld_single_ecc_error_r_ff : UInt<1>, picm_mask_data_m : UInt<32>, lsu_stbuf_commit_any : UInt<1>, lsu_dccm_rden_m : UInt<1>, lsu_dccm_rden_r : UInt<1>, dma_dccm_ctl : {flip dma_mem_addr : UInt<32>, flip dma_mem_wdata : UInt<64>, dccm_dma_rvalid : UInt<1>, dccm_dma_ecc_error : UInt<1>, dccm_dma_rtag : UInt<3>, dccm_dma_rdata : UInt<64>}, flip dccm : {flip wren : UInt<1>, flip rden : UInt<1>, flip wr_addr_lo : UInt<16>, flip wr_addr_hi : UInt<16>, flip rd_addr_lo : UInt<16>, flip rd_addr_hi : UInt<16>, flip wr_data_lo : UInt<39>, flip wr_data_hi : UInt<39>, rd_data_lo : UInt<39>, rd_data_hi : UInt<39>}, lsu_pic : {picm_wren : UInt<1>, picm_rden : UInt<1>, picm_mken : UInt<1>, picm_rdaddr : UInt<32>, picm_wraddr : UInt<32>, picm_wr_data : UInt<32>, flip picm_rd_data : UInt<32>}, flip scan_mode : UInt<1>}
-    
-    node picm_rd_data_m = cat(io.lsu_pic.picm_rd_data, io.lsu_pic.picm_rd_data) @[Cat.scala 29:58]
-    node dccm_rdata_corr_r = cat(io.sec_data_hi_r, io.sec_data_lo_r) @[Cat.scala 29:58]
-    node dccm_rdata_corr_m = cat(io.sec_data_hi_m, io.sec_data_lo_m) @[Cat.scala 29:58]
-    node dccm_rdata_r = cat(io.dccm_rdata_hi_r, io.dccm_rdata_lo_r) @[Cat.scala 29:58]
-    node dccm_rdata_m = cat(io.dccm_rdata_hi_m, io.dccm_rdata_lo_m) @[Cat.scala 29:58]
-    wire lsu_rdata_r : UInt<64>
-    lsu_rdata_r <= UInt<1>("h00")
-    wire lsu_rdata_m : UInt<64>
-    lsu_rdata_m <= UInt<1>("h00")
-    wire lsu_rdata_corr_r : UInt<64>
-    lsu_rdata_corr_r <= UInt<1>("h00")
-    wire lsu_rdata_corr_m : UInt<64>
-    lsu_rdata_corr_m <= UInt<1>("h00")
-    wire stbuf_fwddata_r : UInt<64>
-    stbuf_fwddata_r <= UInt<1>("h00")
-    wire stbuf_fwdbyteen_r : UInt<64>
-    stbuf_fwdbyteen_r <= UInt<1>("h00")
-    wire picm_rd_data_r_32 : UInt<32>
-    picm_rd_data_r_32 <= UInt<1>("h00")
-    wire picm_rd_data_r : UInt<64>
-    picm_rd_data_r <= UInt<1>("h00")
-    wire lsu_ld_data_corr_m : UInt<64>
-    lsu_ld_data_corr_m <= UInt<1>("h00")
-    wire stbuf_fwddata_en : UInt<1>
-    stbuf_fwddata_en <= UInt<1>("h00")
-    wire lsu_double_ecc_error_r_ff : UInt<1>
-    lsu_double_ecc_error_r_ff <= UInt<1>("h00")
-    wire ld_single_ecc_error_hi_r_ff : UInt<1>
-    ld_single_ecc_error_hi_r_ff <= UInt<1>("h00")
-    wire ld_single_ecc_error_lo_r_ff : UInt<1>
-    ld_single_ecc_error_lo_r_ff <= UInt<1>("h00")
-    wire ld_sec_addr_hi_r_ff : UInt<16>
-    ld_sec_addr_hi_r_ff <= UInt<1>("h00")
-    wire ld_sec_addr_lo_r_ff : UInt<16>
-    ld_sec_addr_lo_r_ff <= UInt<1>("h00")
-    node _T = and(io.lsu_pkt_m.valid, io.lsu_pkt_m.bits.load) @[lsu_dccm_ctl.scala 145:63]
-    node _T_1 = and(_T, io.lsu_pkt_m.bits.dma) @[lsu_dccm_ctl.scala 145:88]
-    io.dma_dccm_ctl.dccm_dma_rvalid <= _T_1 @[lsu_dccm_ctl.scala 145:41]
-    io.dma_dccm_ctl.dccm_dma_ecc_error <= io.lsu_double_ecc_error_m @[lsu_dccm_ctl.scala 146:41]
-    node _T_2 = bits(io.ldst_dual_m, 0, 0) @[lib.scala 8:44]
-    node _T_3 = cat(lsu_rdata_corr_m, lsu_rdata_corr_m) @[Cat.scala 29:58]
-    node _T_4 = mux(_T_2, lsu_rdata_corr_m, _T_3) @[lsu_dccm_ctl.scala 147:47]
-    io.dma_dccm_ctl.dccm_dma_rdata <= _T_4 @[lsu_dccm_ctl.scala 147:41]
-    io.dma_dccm_ctl.dccm_dma_rtag <= io.dma_mem_tag_m @[lsu_dccm_ctl.scala 148:41]
-    io.dccm_rdata_lo_r <= UInt<1>("h00") @[lsu_dccm_ctl.scala 149:28]
-    io.dccm_rdata_hi_r <= UInt<1>("h00") @[lsu_dccm_ctl.scala 150:28]
-    io.dccm_data_ecc_hi_r <= UInt<1>("h00") @[lsu_dccm_ctl.scala 151:28]
-    io.dccm_data_ecc_lo_r <= UInt<1>("h00") @[lsu_dccm_ctl.scala 152:28]
-    io.lsu_ld_data_r <= UInt<1>("h00") @[lsu_dccm_ctl.scala 153:28]
-    node _T_5 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58]
-    node _T_6 = bits(_T_5, 0, 0) @[lsu_dccm_ctl.scala 155:134]
-    node _T_7 = bits(_T_6, 0, 0) @[lsu_dccm_ctl.scala 155:139]
-    node _T_8 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58]
-    node _T_9 = bits(_T_8, 7, 0) @[lsu_dccm_ctl.scala 155:196]
-    node _T_10 = bits(io.addr_in_pic_m, 0, 0) @[lsu_dccm_ctl.scala 155:232]
-    node _T_11 = bits(picm_rd_data_m, 7, 0) @[lsu_dccm_ctl.scala 155:253]
-    node _T_12 = bits(io.addr_in_dccm_m, 0, 0) @[Bitwise.scala 72:15]
-    node _T_13 = mux(_T_12, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
-    node _T_14 = bits(dccm_rdata_corr_m, 7, 0) @[lsu_dccm_ctl.scala 155:313]
-    node _T_15 = and(_T_13, _T_14) @[lsu_dccm_ctl.scala 155:294]
-    node _T_16 = mux(_T_10, _T_11, _T_15) @[lsu_dccm_ctl.scala 155:214]
-    node _T_17 = mux(_T_7, _T_9, _T_16) @[lsu_dccm_ctl.scala 155:78]
-    node _T_18 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
-    node _T_19 = xor(UInt<8>("h0ff"), _T_18) @[Bitwise.scala 102:21]
-    node _T_20 = shr(_T_17, 4) @[Bitwise.scala 103:21]
-    node _T_21 = and(_T_20, _T_19) @[Bitwise.scala 103:31]
-    node _T_22 = bits(_T_17, 3, 0) @[Bitwise.scala 103:46]
-    node _T_23 = shl(_T_22, 4) @[Bitwise.scala 103:65]
-    node _T_24 = not(_T_19) @[Bitwise.scala 103:77]
-    node _T_25 = and(_T_23, _T_24) @[Bitwise.scala 103:75]
-    node _T_26 = or(_T_21, _T_25) @[Bitwise.scala 103:39]
-    node _T_27 = bits(_T_19, 5, 0) @[Bitwise.scala 102:28]
-    node _T_28 = shl(_T_27, 2) @[Bitwise.scala 102:47]
-    node _T_29 = xor(_T_19, _T_28) @[Bitwise.scala 102:21]
-    node _T_30 = shr(_T_26, 2) @[Bitwise.scala 103:21]
-    node _T_31 = and(_T_30, _T_29) @[Bitwise.scala 103:31]
-    node _T_32 = bits(_T_26, 5, 0) @[Bitwise.scala 103:46]
-    node _T_33 = shl(_T_32, 2) @[Bitwise.scala 103:65]
-    node _T_34 = not(_T_29) @[Bitwise.scala 103:77]
-    node _T_35 = and(_T_33, _T_34) @[Bitwise.scala 103:75]
-    node _T_36 = or(_T_31, _T_35) @[Bitwise.scala 103:39]
-    node _T_37 = bits(_T_29, 6, 0) @[Bitwise.scala 102:28]
-    node _T_38 = shl(_T_37, 1) @[Bitwise.scala 102:47]
-    node _T_39 = xor(_T_29, _T_38) @[Bitwise.scala 102:21]
-    node _T_40 = shr(_T_36, 1) @[Bitwise.scala 103:21]
-    node _T_41 = and(_T_40, _T_39) @[Bitwise.scala 103:31]
-    node _T_42 = bits(_T_36, 6, 0) @[Bitwise.scala 103:46]
-    node _T_43 = shl(_T_42, 1) @[Bitwise.scala 103:65]
-    node _T_44 = not(_T_39) @[Bitwise.scala 103:77]
-    node _T_45 = and(_T_43, _T_44) @[Bitwise.scala 103:75]
-    node _T_46 = or(_T_41, _T_45) @[Bitwise.scala 103:39]
-    node _T_47 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58]
-    node _T_48 = bits(_T_47, 1, 1) @[lsu_dccm_ctl.scala 155:134]
-    node _T_49 = bits(_T_48, 0, 0) @[lsu_dccm_ctl.scala 155:139]
-    node _T_50 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58]
-    node _T_51 = bits(_T_50, 15, 8) @[lsu_dccm_ctl.scala 155:196]
-    node _T_52 = bits(io.addr_in_pic_m, 0, 0) @[lsu_dccm_ctl.scala 155:232]
-    node _T_53 = bits(picm_rd_data_m, 15, 8) @[lsu_dccm_ctl.scala 155:253]
-    node _T_54 = bits(io.addr_in_dccm_m, 0, 0) @[Bitwise.scala 72:15]
-    node _T_55 = mux(_T_54, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
-    node _T_56 = bits(dccm_rdata_corr_m, 15, 8) @[lsu_dccm_ctl.scala 155:313]
-    node _T_57 = and(_T_55, _T_56) @[lsu_dccm_ctl.scala 155:294]
-    node _T_58 = mux(_T_52, _T_53, _T_57) @[lsu_dccm_ctl.scala 155:214]
-    node _T_59 = mux(_T_49, _T_51, _T_58) @[lsu_dccm_ctl.scala 155:78]
-    node _T_60 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
-    node _T_61 = xor(UInt<8>("h0ff"), _T_60) @[Bitwise.scala 102:21]
-    node _T_62 = shr(_T_59, 4) @[Bitwise.scala 103:21]
-    node _T_63 = and(_T_62, _T_61) @[Bitwise.scala 103:31]
-    node _T_64 = bits(_T_59, 3, 0) @[Bitwise.scala 103:46]
-    node _T_65 = shl(_T_64, 4) @[Bitwise.scala 103:65]
-    node _T_66 = not(_T_61) @[Bitwise.scala 103:77]
-    node _T_67 = and(_T_65, _T_66) @[Bitwise.scala 103:75]
-    node _T_68 = or(_T_63, _T_67) @[Bitwise.scala 103:39]
-    node _T_69 = bits(_T_61, 5, 0) @[Bitwise.scala 102:28]
-    node _T_70 = shl(_T_69, 2) @[Bitwise.scala 102:47]
-    node _T_71 = xor(_T_61, _T_70) @[Bitwise.scala 102:21]
-    node _T_72 = shr(_T_68, 2) @[Bitwise.scala 103:21]
-    node _T_73 = and(_T_72, _T_71) @[Bitwise.scala 103:31]
-    node _T_74 = bits(_T_68, 5, 0) @[Bitwise.scala 103:46]
-    node _T_75 = shl(_T_74, 2) @[Bitwise.scala 103:65]
-    node _T_76 = not(_T_71) @[Bitwise.scala 103:77]
-    node _T_77 = and(_T_75, _T_76) @[Bitwise.scala 103:75]
-    node _T_78 = or(_T_73, _T_77) @[Bitwise.scala 103:39]
-    node _T_79 = bits(_T_71, 6, 0) @[Bitwise.scala 102:28]
-    node _T_80 = shl(_T_79, 1) @[Bitwise.scala 102:47]
-    node _T_81 = xor(_T_71, _T_80) @[Bitwise.scala 102:21]
-    node _T_82 = shr(_T_78, 1) @[Bitwise.scala 103:21]
-    node _T_83 = and(_T_82, _T_81) @[Bitwise.scala 103:31]
-    node _T_84 = bits(_T_78, 6, 0) @[Bitwise.scala 103:46]
-    node _T_85 = shl(_T_84, 1) @[Bitwise.scala 103:65]
-    node _T_86 = not(_T_81) @[Bitwise.scala 103:77]
-    node _T_87 = and(_T_85, _T_86) @[Bitwise.scala 103:75]
-    node _T_88 = or(_T_83, _T_87) @[Bitwise.scala 103:39]
-    node _T_89 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58]
-    node _T_90 = bits(_T_89, 2, 2) @[lsu_dccm_ctl.scala 155:134]
-    node _T_91 = bits(_T_90, 0, 0) @[lsu_dccm_ctl.scala 155:139]
-    node _T_92 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58]
-    node _T_93 = bits(_T_92, 23, 16) @[lsu_dccm_ctl.scala 155:196]
-    node _T_94 = bits(io.addr_in_pic_m, 0, 0) @[lsu_dccm_ctl.scala 155:232]
-    node _T_95 = bits(picm_rd_data_m, 23, 16) @[lsu_dccm_ctl.scala 155:253]
-    node _T_96 = bits(io.addr_in_dccm_m, 0, 0) @[Bitwise.scala 72:15]
-    node _T_97 = mux(_T_96, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
-    node _T_98 = bits(dccm_rdata_corr_m, 23, 16) @[lsu_dccm_ctl.scala 155:313]
-    node _T_99 = and(_T_97, _T_98) @[lsu_dccm_ctl.scala 155:294]
-    node _T_100 = mux(_T_94, _T_95, _T_99) @[lsu_dccm_ctl.scala 155:214]
-    node _T_101 = mux(_T_91, _T_93, _T_100) @[lsu_dccm_ctl.scala 155:78]
-    node _T_102 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
-    node _T_103 = xor(UInt<8>("h0ff"), _T_102) @[Bitwise.scala 102:21]
-    node _T_104 = shr(_T_101, 4) @[Bitwise.scala 103:21]
-    node _T_105 = and(_T_104, _T_103) @[Bitwise.scala 103:31]
-    node _T_106 = bits(_T_101, 3, 0) @[Bitwise.scala 103:46]
-    node _T_107 = shl(_T_106, 4) @[Bitwise.scala 103:65]
-    node _T_108 = not(_T_103) @[Bitwise.scala 103:77]
-    node _T_109 = and(_T_107, _T_108) @[Bitwise.scala 103:75]
-    node _T_110 = or(_T_105, _T_109) @[Bitwise.scala 103:39]
-    node _T_111 = bits(_T_103, 5, 0) @[Bitwise.scala 102:28]
-    node _T_112 = shl(_T_111, 2) @[Bitwise.scala 102:47]
-    node _T_113 = xor(_T_103, _T_112) @[Bitwise.scala 102:21]
-    node _T_114 = shr(_T_110, 2) @[Bitwise.scala 103:21]
-    node _T_115 = and(_T_114, _T_113) @[Bitwise.scala 103:31]
-    node _T_116 = bits(_T_110, 5, 0) @[Bitwise.scala 103:46]
-    node _T_117 = shl(_T_116, 2) @[Bitwise.scala 103:65]
-    node _T_118 = not(_T_113) @[Bitwise.scala 103:77]
-    node _T_119 = and(_T_117, _T_118) @[Bitwise.scala 103:75]
-    node _T_120 = or(_T_115, _T_119) @[Bitwise.scala 103:39]
-    node _T_121 = bits(_T_113, 6, 0) @[Bitwise.scala 102:28]
-    node _T_122 = shl(_T_121, 1) @[Bitwise.scala 102:47]
-    node _T_123 = xor(_T_113, _T_122) @[Bitwise.scala 102:21]
-    node _T_124 = shr(_T_120, 1) @[Bitwise.scala 103:21]
-    node _T_125 = and(_T_124, _T_123) @[Bitwise.scala 103:31]
-    node _T_126 = bits(_T_120, 6, 0) @[Bitwise.scala 103:46]
-    node _T_127 = shl(_T_126, 1) @[Bitwise.scala 103:65]
-    node _T_128 = not(_T_123) @[Bitwise.scala 103:77]
-    node _T_129 = and(_T_127, _T_128) @[Bitwise.scala 103:75]
-    node _T_130 = or(_T_125, _T_129) @[Bitwise.scala 103:39]
-    node _T_131 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58]
-    node _T_132 = bits(_T_131, 3, 3) @[lsu_dccm_ctl.scala 155:134]
-    node _T_133 = bits(_T_132, 0, 0) @[lsu_dccm_ctl.scala 155:139]
-    node _T_134 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58]
-    node _T_135 = bits(_T_134, 31, 24) @[lsu_dccm_ctl.scala 155:196]
-    node _T_136 = bits(io.addr_in_pic_m, 0, 0) @[lsu_dccm_ctl.scala 155:232]
-    node _T_137 = bits(picm_rd_data_m, 31, 24) @[lsu_dccm_ctl.scala 155:253]
-    node _T_138 = bits(io.addr_in_dccm_m, 0, 0) @[Bitwise.scala 72:15]
-    node _T_139 = mux(_T_138, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
-    node _T_140 = bits(dccm_rdata_corr_m, 31, 24) @[lsu_dccm_ctl.scala 155:313]
-    node _T_141 = and(_T_139, _T_140) @[lsu_dccm_ctl.scala 155:294]
-    node _T_142 = mux(_T_136, _T_137, _T_141) @[lsu_dccm_ctl.scala 155:214]
-    node _T_143 = mux(_T_133, _T_135, _T_142) @[lsu_dccm_ctl.scala 155:78]
-    node _T_144 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
-    node _T_145 = xor(UInt<8>("h0ff"), _T_144) @[Bitwise.scala 102:21]
-    node _T_146 = shr(_T_143, 4) @[Bitwise.scala 103:21]
-    node _T_147 = and(_T_146, _T_145) @[Bitwise.scala 103:31]
-    node _T_148 = bits(_T_143, 3, 0) @[Bitwise.scala 103:46]
-    node _T_149 = shl(_T_148, 4) @[Bitwise.scala 103:65]
-    node _T_150 = not(_T_145) @[Bitwise.scala 103:77]
-    node _T_151 = and(_T_149, _T_150) @[Bitwise.scala 103:75]
-    node _T_152 = or(_T_147, _T_151) @[Bitwise.scala 103:39]
-    node _T_153 = bits(_T_145, 5, 0) @[Bitwise.scala 102:28]
-    node _T_154 = shl(_T_153, 2) @[Bitwise.scala 102:47]
-    node _T_155 = xor(_T_145, _T_154) @[Bitwise.scala 102:21]
-    node _T_156 = shr(_T_152, 2) @[Bitwise.scala 103:21]
-    node _T_157 = and(_T_156, _T_155) @[Bitwise.scala 103:31]
-    node _T_158 = bits(_T_152, 5, 0) @[Bitwise.scala 103:46]
-    node _T_159 = shl(_T_158, 2) @[Bitwise.scala 103:65]
-    node _T_160 = not(_T_155) @[Bitwise.scala 103:77]
-    node _T_161 = and(_T_159, _T_160) @[Bitwise.scala 103:75]
-    node _T_162 = or(_T_157, _T_161) @[Bitwise.scala 103:39]
-    node _T_163 = bits(_T_155, 6, 0) @[Bitwise.scala 102:28]
-    node _T_164 = shl(_T_163, 1) @[Bitwise.scala 102:47]
-    node _T_165 = xor(_T_155, _T_164) @[Bitwise.scala 102:21]
-    node _T_166 = shr(_T_162, 1) @[Bitwise.scala 103:21]
-    node _T_167 = and(_T_166, _T_165) @[Bitwise.scala 103:31]
-    node _T_168 = bits(_T_162, 6, 0) @[Bitwise.scala 103:46]
-    node _T_169 = shl(_T_168, 1) @[Bitwise.scala 103:65]
-    node _T_170 = not(_T_165) @[Bitwise.scala 103:77]
-    node _T_171 = and(_T_169, _T_170) @[Bitwise.scala 103:75]
-    node _T_172 = or(_T_167, _T_171) @[Bitwise.scala 103:39]
-    node _T_173 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58]
-    node _T_174 = bits(_T_173, 4, 4) @[lsu_dccm_ctl.scala 155:134]
-    node _T_175 = bits(_T_174, 0, 0) @[lsu_dccm_ctl.scala 155:139]
-    node _T_176 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58]
-    node _T_177 = bits(_T_176, 39, 32) @[lsu_dccm_ctl.scala 155:196]
-    node _T_178 = bits(io.addr_in_pic_m, 0, 0) @[lsu_dccm_ctl.scala 155:232]
-    node _T_179 = bits(picm_rd_data_m, 39, 32) @[lsu_dccm_ctl.scala 155:253]
-    node _T_180 = bits(io.addr_in_dccm_m, 0, 0) @[Bitwise.scala 72:15]
-    node _T_181 = mux(_T_180, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
-    node _T_182 = bits(dccm_rdata_corr_m, 39, 32) @[lsu_dccm_ctl.scala 155:313]
-    node _T_183 = and(_T_181, _T_182) @[lsu_dccm_ctl.scala 155:294]
-    node _T_184 = mux(_T_178, _T_179, _T_183) @[lsu_dccm_ctl.scala 155:214]
-    node _T_185 = mux(_T_175, _T_177, _T_184) @[lsu_dccm_ctl.scala 155:78]
-    node _T_186 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
-    node _T_187 = xor(UInt<8>("h0ff"), _T_186) @[Bitwise.scala 102:21]
-    node _T_188 = shr(_T_185, 4) @[Bitwise.scala 103:21]
-    node _T_189 = and(_T_188, _T_187) @[Bitwise.scala 103:31]
-    node _T_190 = bits(_T_185, 3, 0) @[Bitwise.scala 103:46]
-    node _T_191 = shl(_T_190, 4) @[Bitwise.scala 103:65]
-    node _T_192 = not(_T_187) @[Bitwise.scala 103:77]
-    node _T_193 = and(_T_191, _T_192) @[Bitwise.scala 103:75]
-    node _T_194 = or(_T_189, _T_193) @[Bitwise.scala 103:39]
-    node _T_195 = bits(_T_187, 5, 0) @[Bitwise.scala 102:28]
-    node _T_196 = shl(_T_195, 2) @[Bitwise.scala 102:47]
-    node _T_197 = xor(_T_187, _T_196) @[Bitwise.scala 102:21]
-    node _T_198 = shr(_T_194, 2) @[Bitwise.scala 103:21]
-    node _T_199 = and(_T_198, _T_197) @[Bitwise.scala 103:31]
-    node _T_200 = bits(_T_194, 5, 0) @[Bitwise.scala 103:46]
-    node _T_201 = shl(_T_200, 2) @[Bitwise.scala 103:65]
-    node _T_202 = not(_T_197) @[Bitwise.scala 103:77]
-    node _T_203 = and(_T_201, _T_202) @[Bitwise.scala 103:75]
-    node _T_204 = or(_T_199, _T_203) @[Bitwise.scala 103:39]
-    node _T_205 = bits(_T_197, 6, 0) @[Bitwise.scala 102:28]
-    node _T_206 = shl(_T_205, 1) @[Bitwise.scala 102:47]
-    node _T_207 = xor(_T_197, _T_206) @[Bitwise.scala 102:21]
-    node _T_208 = shr(_T_204, 1) @[Bitwise.scala 103:21]
-    node _T_209 = and(_T_208, _T_207) @[Bitwise.scala 103:31]
-    node _T_210 = bits(_T_204, 6, 0) @[Bitwise.scala 103:46]
-    node _T_211 = shl(_T_210, 1) @[Bitwise.scala 103:65]
-    node _T_212 = not(_T_207) @[Bitwise.scala 103:77]
-    node _T_213 = and(_T_211, _T_212) @[Bitwise.scala 103:75]
-    node _T_214 = or(_T_209, _T_213) @[Bitwise.scala 103:39]
-    node _T_215 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58]
-    node _T_216 = bits(_T_215, 5, 5) @[lsu_dccm_ctl.scala 155:134]
-    node _T_217 = bits(_T_216, 0, 0) @[lsu_dccm_ctl.scala 155:139]
-    node _T_218 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58]
-    node _T_219 = bits(_T_218, 47, 40) @[lsu_dccm_ctl.scala 155:196]
-    node _T_220 = bits(io.addr_in_pic_m, 0, 0) @[lsu_dccm_ctl.scala 155:232]
-    node _T_221 = bits(picm_rd_data_m, 47, 40) @[lsu_dccm_ctl.scala 155:253]
-    node _T_222 = bits(io.addr_in_dccm_m, 0, 0) @[Bitwise.scala 72:15]
-    node _T_223 = mux(_T_222, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
-    node _T_224 = bits(dccm_rdata_corr_m, 47, 40) @[lsu_dccm_ctl.scala 155:313]
-    node _T_225 = and(_T_223, _T_224) @[lsu_dccm_ctl.scala 155:294]
-    node _T_226 = mux(_T_220, _T_221, _T_225) @[lsu_dccm_ctl.scala 155:214]
-    node _T_227 = mux(_T_217, _T_219, _T_226) @[lsu_dccm_ctl.scala 155:78]
-    node _T_228 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
-    node _T_229 = xor(UInt<8>("h0ff"), _T_228) @[Bitwise.scala 102:21]
-    node _T_230 = shr(_T_227, 4) @[Bitwise.scala 103:21]
-    node _T_231 = and(_T_230, _T_229) @[Bitwise.scala 103:31]
-    node _T_232 = bits(_T_227, 3, 0) @[Bitwise.scala 103:46]
-    node _T_233 = shl(_T_232, 4) @[Bitwise.scala 103:65]
-    node _T_234 = not(_T_229) @[Bitwise.scala 103:77]
-    node _T_235 = and(_T_233, _T_234) @[Bitwise.scala 103:75]
-    node _T_236 = or(_T_231, _T_235) @[Bitwise.scala 103:39]
-    node _T_237 = bits(_T_229, 5, 0) @[Bitwise.scala 102:28]
-    node _T_238 = shl(_T_237, 2) @[Bitwise.scala 102:47]
-    node _T_239 = xor(_T_229, _T_238) @[Bitwise.scala 102:21]
-    node _T_240 = shr(_T_236, 2) @[Bitwise.scala 103:21]
-    node _T_241 = and(_T_240, _T_239) @[Bitwise.scala 103:31]
-    node _T_242 = bits(_T_236, 5, 0) @[Bitwise.scala 103:46]
-    node _T_243 = shl(_T_242, 2) @[Bitwise.scala 103:65]
-    node _T_244 = not(_T_239) @[Bitwise.scala 103:77]
-    node _T_245 = and(_T_243, _T_244) @[Bitwise.scala 103:75]
-    node _T_246 = or(_T_241, _T_245) @[Bitwise.scala 103:39]
-    node _T_247 = bits(_T_239, 6, 0) @[Bitwise.scala 102:28]
-    node _T_248 = shl(_T_247, 1) @[Bitwise.scala 102:47]
-    node _T_249 = xor(_T_239, _T_248) @[Bitwise.scala 102:21]
-    node _T_250 = shr(_T_246, 1) @[Bitwise.scala 103:21]
-    node _T_251 = and(_T_250, _T_249) @[Bitwise.scala 103:31]
-    node _T_252 = bits(_T_246, 6, 0) @[Bitwise.scala 103:46]
-    node _T_253 = shl(_T_252, 1) @[Bitwise.scala 103:65]
-    node _T_254 = not(_T_249) @[Bitwise.scala 103:77]
-    node _T_255 = and(_T_253, _T_254) @[Bitwise.scala 103:75]
-    node _T_256 = or(_T_251, _T_255) @[Bitwise.scala 103:39]
-    node _T_257 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58]
-    node _T_258 = bits(_T_257, 6, 6) @[lsu_dccm_ctl.scala 155:134]
-    node _T_259 = bits(_T_258, 0, 0) @[lsu_dccm_ctl.scala 155:139]
-    node _T_260 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58]
-    node _T_261 = bits(_T_260, 55, 48) @[lsu_dccm_ctl.scala 155:196]
-    node _T_262 = bits(io.addr_in_pic_m, 0, 0) @[lsu_dccm_ctl.scala 155:232]
-    node _T_263 = bits(picm_rd_data_m, 55, 48) @[lsu_dccm_ctl.scala 155:253]
-    node _T_264 = bits(io.addr_in_dccm_m, 0, 0) @[Bitwise.scala 72:15]
-    node _T_265 = mux(_T_264, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
-    node _T_266 = bits(dccm_rdata_corr_m, 55, 48) @[lsu_dccm_ctl.scala 155:313]
-    node _T_267 = and(_T_265, _T_266) @[lsu_dccm_ctl.scala 155:294]
-    node _T_268 = mux(_T_262, _T_263, _T_267) @[lsu_dccm_ctl.scala 155:214]
-    node _T_269 = mux(_T_259, _T_261, _T_268) @[lsu_dccm_ctl.scala 155:78]
-    node _T_270 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
-    node _T_271 = xor(UInt<8>("h0ff"), _T_270) @[Bitwise.scala 102:21]
-    node _T_272 = shr(_T_269, 4) @[Bitwise.scala 103:21]
-    node _T_273 = and(_T_272, _T_271) @[Bitwise.scala 103:31]
-    node _T_274 = bits(_T_269, 3, 0) @[Bitwise.scala 103:46]
-    node _T_275 = shl(_T_274, 4) @[Bitwise.scala 103:65]
-    node _T_276 = not(_T_271) @[Bitwise.scala 103:77]
-    node _T_277 = and(_T_275, _T_276) @[Bitwise.scala 103:75]
-    node _T_278 = or(_T_273, _T_277) @[Bitwise.scala 103:39]
-    node _T_279 = bits(_T_271, 5, 0) @[Bitwise.scala 102:28]
-    node _T_280 = shl(_T_279, 2) @[Bitwise.scala 102:47]
-    node _T_281 = xor(_T_271, _T_280) @[Bitwise.scala 102:21]
-    node _T_282 = shr(_T_278, 2) @[Bitwise.scala 103:21]
-    node _T_283 = and(_T_282, _T_281) @[Bitwise.scala 103:31]
-    node _T_284 = bits(_T_278, 5, 0) @[Bitwise.scala 103:46]
-    node _T_285 = shl(_T_284, 2) @[Bitwise.scala 103:65]
-    node _T_286 = not(_T_281) @[Bitwise.scala 103:77]
-    node _T_287 = and(_T_285, _T_286) @[Bitwise.scala 103:75]
-    node _T_288 = or(_T_283, _T_287) @[Bitwise.scala 103:39]
-    node _T_289 = bits(_T_281, 6, 0) @[Bitwise.scala 102:28]
-    node _T_290 = shl(_T_289, 1) @[Bitwise.scala 102:47]
-    node _T_291 = xor(_T_281, _T_290) @[Bitwise.scala 102:21]
-    node _T_292 = shr(_T_288, 1) @[Bitwise.scala 103:21]
-    node _T_293 = and(_T_292, _T_291) @[Bitwise.scala 103:31]
-    node _T_294 = bits(_T_288, 6, 0) @[Bitwise.scala 103:46]
-    node _T_295 = shl(_T_294, 1) @[Bitwise.scala 103:65]
-    node _T_296 = not(_T_291) @[Bitwise.scala 103:77]
-    node _T_297 = and(_T_295, _T_296) @[Bitwise.scala 103:75]
-    node _T_298 = or(_T_293, _T_297) @[Bitwise.scala 103:39]
-    node _T_299 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58]
-    node _T_300 = bits(_T_299, 7, 7) @[lsu_dccm_ctl.scala 155:134]
-    node _T_301 = bits(_T_300, 0, 0) @[lsu_dccm_ctl.scala 155:139]
-    node _T_302 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58]
-    node _T_303 = bits(_T_302, 63, 56) @[lsu_dccm_ctl.scala 155:196]
-    node _T_304 = bits(io.addr_in_pic_m, 0, 0) @[lsu_dccm_ctl.scala 155:232]
-    node _T_305 = bits(picm_rd_data_m, 63, 56) @[lsu_dccm_ctl.scala 155:253]
-    node _T_306 = bits(io.addr_in_dccm_m, 0, 0) @[Bitwise.scala 72:15]
-    node _T_307 = mux(_T_306, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
-    node _T_308 = bits(dccm_rdata_corr_m, 63, 56) @[lsu_dccm_ctl.scala 155:313]
-    node _T_309 = and(_T_307, _T_308) @[lsu_dccm_ctl.scala 155:294]
-    node _T_310 = mux(_T_304, _T_305, _T_309) @[lsu_dccm_ctl.scala 155:214]
-    node _T_311 = mux(_T_301, _T_303, _T_310) @[lsu_dccm_ctl.scala 155:78]
-    node _T_312 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
-    node _T_313 = xor(UInt<8>("h0ff"), _T_312) @[Bitwise.scala 102:21]
-    node _T_314 = shr(_T_311, 4) @[Bitwise.scala 103:21]
-    node _T_315 = and(_T_314, _T_313) @[Bitwise.scala 103:31]
-    node _T_316 = bits(_T_311, 3, 0) @[Bitwise.scala 103:46]
-    node _T_317 = shl(_T_316, 4) @[Bitwise.scala 103:65]
-    node _T_318 = not(_T_313) @[Bitwise.scala 103:77]
-    node _T_319 = and(_T_317, _T_318) @[Bitwise.scala 103:75]
-    node _T_320 = or(_T_315, _T_319) @[Bitwise.scala 103:39]
-    node _T_321 = bits(_T_313, 5, 0) @[Bitwise.scala 102:28]
-    node _T_322 = shl(_T_321, 2) @[Bitwise.scala 102:47]
-    node _T_323 = xor(_T_313, _T_322) @[Bitwise.scala 102:21]
-    node _T_324 = shr(_T_320, 2) @[Bitwise.scala 103:21]
-    node _T_325 = and(_T_324, _T_323) @[Bitwise.scala 103:31]
-    node _T_326 = bits(_T_320, 5, 0) @[Bitwise.scala 103:46]
-    node _T_327 = shl(_T_326, 2) @[Bitwise.scala 103:65]
-    node _T_328 = not(_T_323) @[Bitwise.scala 103:77]
-    node _T_329 = and(_T_327, _T_328) @[Bitwise.scala 103:75]
-    node _T_330 = or(_T_325, _T_329) @[Bitwise.scala 103:39]
-    node _T_331 = bits(_T_323, 6, 0) @[Bitwise.scala 102:28]
-    node _T_332 = shl(_T_331, 1) @[Bitwise.scala 102:47]
-    node _T_333 = xor(_T_323, _T_332) @[Bitwise.scala 102:21]
-    node _T_334 = shr(_T_330, 1) @[Bitwise.scala 103:21]
-    node _T_335 = and(_T_334, _T_333) @[Bitwise.scala 103:31]
-    node _T_336 = bits(_T_330, 6, 0) @[Bitwise.scala 103:46]
-    node _T_337 = shl(_T_336, 1) @[Bitwise.scala 103:65]
-    node _T_338 = not(_T_333) @[Bitwise.scala 103:77]
-    node _T_339 = and(_T_337, _T_338) @[Bitwise.scala 103:75]
-    node _T_340 = or(_T_335, _T_339) @[Bitwise.scala 103:39]
-    wire _T_341 : UInt<8>[8] @[lsu_dccm_ctl.scala 155:62]
-    _T_341[0] <= _T_46 @[lsu_dccm_ctl.scala 155:62]
-    _T_341[1] <= _T_88 @[lsu_dccm_ctl.scala 155:62]
-    _T_341[2] <= _T_130 @[lsu_dccm_ctl.scala 155:62]
-    _T_341[3] <= _T_172 @[lsu_dccm_ctl.scala 155:62]
-    _T_341[4] <= _T_214 @[lsu_dccm_ctl.scala 155:62]
-    _T_341[5] <= _T_256 @[lsu_dccm_ctl.scala 155:62]
-    _T_341[6] <= _T_298 @[lsu_dccm_ctl.scala 155:62]
-    _T_341[7] <= _T_340 @[lsu_dccm_ctl.scala 155:62]
-    node _T_342 = cat(_T_341[6], _T_341[7]) @[Cat.scala 29:58]
-    node _T_343 = cat(_T_341[4], _T_341[5]) @[Cat.scala 29:58]
-    node _T_344 = cat(_T_343, _T_342) @[Cat.scala 29:58]
-    node _T_345 = cat(_T_341[2], _T_341[3]) @[Cat.scala 29:58]
-    node _T_346 = cat(_T_341[0], _T_341[1]) @[Cat.scala 29:58]
-    node _T_347 = cat(_T_346, _T_345) @[Cat.scala 29:58]
-    node _T_348 = cat(_T_347, _T_344) @[Cat.scala 29:58]
-    node _T_349 = shl(UInt<32>("h0ffffffff"), 32) @[Bitwise.scala 102:47]
-    node _T_350 = xor(UInt<64>("h0ffffffffffffffff"), _T_349) @[Bitwise.scala 102:21]
-    node _T_351 = shr(_T_348, 32) @[Bitwise.scala 103:21]
-    node _T_352 = and(_T_351, _T_350) @[Bitwise.scala 103:31]
-    node _T_353 = bits(_T_348, 31, 0) @[Bitwise.scala 103:46]
-    node _T_354 = shl(_T_353, 32) @[Bitwise.scala 103:65]
-    node _T_355 = not(_T_350) @[Bitwise.scala 103:77]
-    node _T_356 = and(_T_354, _T_355) @[Bitwise.scala 103:75]
-    node _T_357 = or(_T_352, _T_356) @[Bitwise.scala 103:39]
-    node _T_358 = bits(_T_350, 47, 0) @[Bitwise.scala 102:28]
-    node _T_359 = shl(_T_358, 16) @[Bitwise.scala 102:47]
-    node _T_360 = xor(_T_350, _T_359) @[Bitwise.scala 102:21]
-    node _T_361 = shr(_T_357, 16) @[Bitwise.scala 103:21]
-    node _T_362 = and(_T_361, _T_360) @[Bitwise.scala 103:31]
-    node _T_363 = bits(_T_357, 47, 0) @[Bitwise.scala 103:46]
-    node _T_364 = shl(_T_363, 16) @[Bitwise.scala 103:65]
-    node _T_365 = not(_T_360) @[Bitwise.scala 103:77]
-    node _T_366 = and(_T_364, _T_365) @[Bitwise.scala 103:75]
-    node _T_367 = or(_T_362, _T_366) @[Bitwise.scala 103:39]
-    node _T_368 = bits(_T_360, 55, 0) @[Bitwise.scala 102:28]
-    node _T_369 = shl(_T_368, 8) @[Bitwise.scala 102:47]
-    node _T_370 = xor(_T_360, _T_369) @[Bitwise.scala 102:21]
-    node _T_371 = shr(_T_367, 8) @[Bitwise.scala 103:21]
-    node _T_372 = and(_T_371, _T_370) @[Bitwise.scala 103:31]
-    node _T_373 = bits(_T_367, 55, 0) @[Bitwise.scala 103:46]
-    node _T_374 = shl(_T_373, 8) @[Bitwise.scala 103:65]
-    node _T_375 = not(_T_370) @[Bitwise.scala 103:77]
-    node _T_376 = and(_T_374, _T_375) @[Bitwise.scala 103:75]
-    node _T_377 = or(_T_372, _T_376) @[Bitwise.scala 103:39]
-    node _T_378 = bits(_T_370, 59, 0) @[Bitwise.scala 102:28]
-    node _T_379 = shl(_T_378, 4) @[Bitwise.scala 102:47]
-    node _T_380 = xor(_T_370, _T_379) @[Bitwise.scala 102:21]
-    node _T_381 = shr(_T_377, 4) @[Bitwise.scala 103:21]
-    node _T_382 = and(_T_381, _T_380) @[Bitwise.scala 103:31]
-    node _T_383 = bits(_T_377, 59, 0) @[Bitwise.scala 103:46]
-    node _T_384 = shl(_T_383, 4) @[Bitwise.scala 103:65]
-    node _T_385 = not(_T_380) @[Bitwise.scala 103:77]
-    node _T_386 = and(_T_384, _T_385) @[Bitwise.scala 103:75]
-    node _T_387 = or(_T_382, _T_386) @[Bitwise.scala 103:39]
-    node _T_388 = bits(_T_380, 61, 0) @[Bitwise.scala 102:28]
-    node _T_389 = shl(_T_388, 2) @[Bitwise.scala 102:47]
-    node _T_390 = xor(_T_380, _T_389) @[Bitwise.scala 102:21]
-    node _T_391 = shr(_T_387, 2) @[Bitwise.scala 103:21]
-    node _T_392 = and(_T_391, _T_390) @[Bitwise.scala 103:31]
-    node _T_393 = bits(_T_387, 61, 0) @[Bitwise.scala 103:46]
-    node _T_394 = shl(_T_393, 2) @[Bitwise.scala 103:65]
-    node _T_395 = not(_T_390) @[Bitwise.scala 103:77]
-    node _T_396 = and(_T_394, _T_395) @[Bitwise.scala 103:75]
-    node _T_397 = or(_T_392, _T_396) @[Bitwise.scala 103:39]
-    node _T_398 = bits(_T_390, 62, 0) @[Bitwise.scala 102:28]
-    node _T_399 = shl(_T_398, 1) @[Bitwise.scala 102:47]
-    node _T_400 = xor(_T_390, _T_399) @[Bitwise.scala 102:21]
-    node _T_401 = shr(_T_397, 1) @[Bitwise.scala 103:21]
-    node _T_402 = and(_T_401, _T_400) @[Bitwise.scala 103:31]
-    node _T_403 = bits(_T_397, 62, 0) @[Bitwise.scala 103:46]
-    node _T_404 = shl(_T_403, 1) @[Bitwise.scala 103:65]
-    node _T_405 = not(_T_400) @[Bitwise.scala 103:77]
-    node _T_406 = and(_T_404, _T_405) @[Bitwise.scala 103:75]
-    node _T_407 = or(_T_402, _T_406) @[Bitwise.scala 103:39]
-    lsu_rdata_corr_m <= _T_407 @[lsu_dccm_ctl.scala 155:28]
-    node _T_408 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58]
-    node _T_409 = bits(_T_408, 0, 0) @[lsu_dccm_ctl.scala 156:134]
-    node _T_410 = bits(_T_409, 0, 0) @[lsu_dccm_ctl.scala 156:139]
-    node _T_411 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58]
-    node _T_412 = bits(_T_411, 7, 0) @[lsu_dccm_ctl.scala 156:196]
-    node _T_413 = bits(io.addr_in_pic_m, 0, 0) @[lsu_dccm_ctl.scala 156:232]
-    node _T_414 = bits(picm_rd_data_m, 7, 0) @[lsu_dccm_ctl.scala 156:253]
-    node _T_415 = bits(io.addr_in_dccm_m, 0, 0) @[Bitwise.scala 72:15]
-    node _T_416 = mux(_T_415, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
-    node _T_417 = bits(dccm_rdata_m, 7, 0) @[lsu_dccm_ctl.scala 156:308]
-    node _T_418 = and(_T_416, _T_417) @[lsu_dccm_ctl.scala 156:294]
-    node _T_419 = mux(_T_413, _T_414, _T_418) @[lsu_dccm_ctl.scala 156:214]
-    node _T_420 = mux(_T_410, _T_412, _T_419) @[lsu_dccm_ctl.scala 156:78]
-    node _T_421 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
-    node _T_422 = xor(UInt<8>("h0ff"), _T_421) @[Bitwise.scala 102:21]
-    node _T_423 = shr(_T_420, 4) @[Bitwise.scala 103:21]
-    node _T_424 = and(_T_423, _T_422) @[Bitwise.scala 103:31]
-    node _T_425 = bits(_T_420, 3, 0) @[Bitwise.scala 103:46]
-    node _T_426 = shl(_T_425, 4) @[Bitwise.scala 103:65]
-    node _T_427 = not(_T_422) @[Bitwise.scala 103:77]
-    node _T_428 = and(_T_426, _T_427) @[Bitwise.scala 103:75]
-    node _T_429 = or(_T_424, _T_428) @[Bitwise.scala 103:39]
-    node _T_430 = bits(_T_422, 5, 0) @[Bitwise.scala 102:28]
-    node _T_431 = shl(_T_430, 2) @[Bitwise.scala 102:47]
-    node _T_432 = xor(_T_422, _T_431) @[Bitwise.scala 102:21]
-    node _T_433 = shr(_T_429, 2) @[Bitwise.scala 103:21]
-    node _T_434 = and(_T_433, _T_432) @[Bitwise.scala 103:31]
-    node _T_435 = bits(_T_429, 5, 0) @[Bitwise.scala 103:46]
-    node _T_436 = shl(_T_435, 2) @[Bitwise.scala 103:65]
-    node _T_437 = not(_T_432) @[Bitwise.scala 103:77]
-    node _T_438 = and(_T_436, _T_437) @[Bitwise.scala 103:75]
-    node _T_439 = or(_T_434, _T_438) @[Bitwise.scala 103:39]
-    node _T_440 = bits(_T_432, 6, 0) @[Bitwise.scala 102:28]
-    node _T_441 = shl(_T_440, 1) @[Bitwise.scala 102:47]
-    node _T_442 = xor(_T_432, _T_441) @[Bitwise.scala 102:21]
-    node _T_443 = shr(_T_439, 1) @[Bitwise.scala 103:21]
-    node _T_444 = and(_T_443, _T_442) @[Bitwise.scala 103:31]
-    node _T_445 = bits(_T_439, 6, 0) @[Bitwise.scala 103:46]
-    node _T_446 = shl(_T_445, 1) @[Bitwise.scala 103:65]
-    node _T_447 = not(_T_442) @[Bitwise.scala 103:77]
-    node _T_448 = and(_T_446, _T_447) @[Bitwise.scala 103:75]
-    node _T_449 = or(_T_444, _T_448) @[Bitwise.scala 103:39]
-    node _T_450 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58]
-    node _T_451 = bits(_T_450, 1, 1) @[lsu_dccm_ctl.scala 156:134]
-    node _T_452 = bits(_T_451, 0, 0) @[lsu_dccm_ctl.scala 156:139]
-    node _T_453 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58]
-    node _T_454 = bits(_T_453, 15, 8) @[lsu_dccm_ctl.scala 156:196]
-    node _T_455 = bits(io.addr_in_pic_m, 0, 0) @[lsu_dccm_ctl.scala 156:232]
-    node _T_456 = bits(picm_rd_data_m, 15, 8) @[lsu_dccm_ctl.scala 156:253]
-    node _T_457 = bits(io.addr_in_dccm_m, 0, 0) @[Bitwise.scala 72:15]
-    node _T_458 = mux(_T_457, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
-    node _T_459 = bits(dccm_rdata_m, 15, 8) @[lsu_dccm_ctl.scala 156:308]
-    node _T_460 = and(_T_458, _T_459) @[lsu_dccm_ctl.scala 156:294]
-    node _T_461 = mux(_T_455, _T_456, _T_460) @[lsu_dccm_ctl.scala 156:214]
-    node _T_462 = mux(_T_452, _T_454, _T_461) @[lsu_dccm_ctl.scala 156:78]
-    node _T_463 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
-    node _T_464 = xor(UInt<8>("h0ff"), _T_463) @[Bitwise.scala 102:21]
-    node _T_465 = shr(_T_462, 4) @[Bitwise.scala 103:21]
-    node _T_466 = and(_T_465, _T_464) @[Bitwise.scala 103:31]
-    node _T_467 = bits(_T_462, 3, 0) @[Bitwise.scala 103:46]
-    node _T_468 = shl(_T_467, 4) @[Bitwise.scala 103:65]
-    node _T_469 = not(_T_464) @[Bitwise.scala 103:77]
-    node _T_470 = and(_T_468, _T_469) @[Bitwise.scala 103:75]
-    node _T_471 = or(_T_466, _T_470) @[Bitwise.scala 103:39]
-    node _T_472 = bits(_T_464, 5, 0) @[Bitwise.scala 102:28]
-    node _T_473 = shl(_T_472, 2) @[Bitwise.scala 102:47]
-    node _T_474 = xor(_T_464, _T_473) @[Bitwise.scala 102:21]
-    node _T_475 = shr(_T_471, 2) @[Bitwise.scala 103:21]
-    node _T_476 = and(_T_475, _T_474) @[Bitwise.scala 103:31]
-    node _T_477 = bits(_T_471, 5, 0) @[Bitwise.scala 103:46]
-    node _T_478 = shl(_T_477, 2) @[Bitwise.scala 103:65]
-    node _T_479 = not(_T_474) @[Bitwise.scala 103:77]
-    node _T_480 = and(_T_478, _T_479) @[Bitwise.scala 103:75]
-    node _T_481 = or(_T_476, _T_480) @[Bitwise.scala 103:39]
-    node _T_482 = bits(_T_474, 6, 0) @[Bitwise.scala 102:28]
-    node _T_483 = shl(_T_482, 1) @[Bitwise.scala 102:47]
-    node _T_484 = xor(_T_474, _T_483) @[Bitwise.scala 102:21]
-    node _T_485 = shr(_T_481, 1) @[Bitwise.scala 103:21]
-    node _T_486 = and(_T_485, _T_484) @[Bitwise.scala 103:31]
-    node _T_487 = bits(_T_481, 6, 0) @[Bitwise.scala 103:46]
-    node _T_488 = shl(_T_487, 1) @[Bitwise.scala 103:65]
-    node _T_489 = not(_T_484) @[Bitwise.scala 103:77]
-    node _T_490 = and(_T_488, _T_489) @[Bitwise.scala 103:75]
-    node _T_491 = or(_T_486, _T_490) @[Bitwise.scala 103:39]
-    node _T_492 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58]
-    node _T_493 = bits(_T_492, 2, 2) @[lsu_dccm_ctl.scala 156:134]
-    node _T_494 = bits(_T_493, 0, 0) @[lsu_dccm_ctl.scala 156:139]
-    node _T_495 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58]
-    node _T_496 = bits(_T_495, 23, 16) @[lsu_dccm_ctl.scala 156:196]
-    node _T_497 = bits(io.addr_in_pic_m, 0, 0) @[lsu_dccm_ctl.scala 156:232]
-    node _T_498 = bits(picm_rd_data_m, 23, 16) @[lsu_dccm_ctl.scala 156:253]
-    node _T_499 = bits(io.addr_in_dccm_m, 0, 0) @[Bitwise.scala 72:15]
-    node _T_500 = mux(_T_499, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
-    node _T_501 = bits(dccm_rdata_m, 23, 16) @[lsu_dccm_ctl.scala 156:308]
-    node _T_502 = and(_T_500, _T_501) @[lsu_dccm_ctl.scala 156:294]
-    node _T_503 = mux(_T_497, _T_498, _T_502) @[lsu_dccm_ctl.scala 156:214]
-    node _T_504 = mux(_T_494, _T_496, _T_503) @[lsu_dccm_ctl.scala 156:78]
-    node _T_505 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
-    node _T_506 = xor(UInt<8>("h0ff"), _T_505) @[Bitwise.scala 102:21]
-    node _T_507 = shr(_T_504, 4) @[Bitwise.scala 103:21]
-    node _T_508 = and(_T_507, _T_506) @[Bitwise.scala 103:31]
-    node _T_509 = bits(_T_504, 3, 0) @[Bitwise.scala 103:46]
-    node _T_510 = shl(_T_509, 4) @[Bitwise.scala 103:65]
-    node _T_511 = not(_T_506) @[Bitwise.scala 103:77]
-    node _T_512 = and(_T_510, _T_511) @[Bitwise.scala 103:75]
-    node _T_513 = or(_T_508, _T_512) @[Bitwise.scala 103:39]
-    node _T_514 = bits(_T_506, 5, 0) @[Bitwise.scala 102:28]
-    node _T_515 = shl(_T_514, 2) @[Bitwise.scala 102:47]
-    node _T_516 = xor(_T_506, _T_515) @[Bitwise.scala 102:21]
-    node _T_517 = shr(_T_513, 2) @[Bitwise.scala 103:21]
-    node _T_518 = and(_T_517, _T_516) @[Bitwise.scala 103:31]
-    node _T_519 = bits(_T_513, 5, 0) @[Bitwise.scala 103:46]
-    node _T_520 = shl(_T_519, 2) @[Bitwise.scala 103:65]
-    node _T_521 = not(_T_516) @[Bitwise.scala 103:77]
-    node _T_522 = and(_T_520, _T_521) @[Bitwise.scala 103:75]
-    node _T_523 = or(_T_518, _T_522) @[Bitwise.scala 103:39]
-    node _T_524 = bits(_T_516, 6, 0) @[Bitwise.scala 102:28]
-    node _T_525 = shl(_T_524, 1) @[Bitwise.scala 102:47]
-    node _T_526 = xor(_T_516, _T_525) @[Bitwise.scala 102:21]
-    node _T_527 = shr(_T_523, 1) @[Bitwise.scala 103:21]
-    node _T_528 = and(_T_527, _T_526) @[Bitwise.scala 103:31]
-    node _T_529 = bits(_T_523, 6, 0) @[Bitwise.scala 103:46]
-    node _T_530 = shl(_T_529, 1) @[Bitwise.scala 103:65]
-    node _T_531 = not(_T_526) @[Bitwise.scala 103:77]
-    node _T_532 = and(_T_530, _T_531) @[Bitwise.scala 103:75]
-    node _T_533 = or(_T_528, _T_532) @[Bitwise.scala 103:39]
-    node _T_534 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58]
-    node _T_535 = bits(_T_534, 3, 3) @[lsu_dccm_ctl.scala 156:134]
-    node _T_536 = bits(_T_535, 0, 0) @[lsu_dccm_ctl.scala 156:139]
-    node _T_537 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58]
-    node _T_538 = bits(_T_537, 31, 24) @[lsu_dccm_ctl.scala 156:196]
-    node _T_539 = bits(io.addr_in_pic_m, 0, 0) @[lsu_dccm_ctl.scala 156:232]
-    node _T_540 = bits(picm_rd_data_m, 31, 24) @[lsu_dccm_ctl.scala 156:253]
-    node _T_541 = bits(io.addr_in_dccm_m, 0, 0) @[Bitwise.scala 72:15]
-    node _T_542 = mux(_T_541, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
-    node _T_543 = bits(dccm_rdata_m, 31, 24) @[lsu_dccm_ctl.scala 156:308]
-    node _T_544 = and(_T_542, _T_543) @[lsu_dccm_ctl.scala 156:294]
-    node _T_545 = mux(_T_539, _T_540, _T_544) @[lsu_dccm_ctl.scala 156:214]
-    node _T_546 = mux(_T_536, _T_538, _T_545) @[lsu_dccm_ctl.scala 156:78]
-    node _T_547 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
-    node _T_548 = xor(UInt<8>("h0ff"), _T_547) @[Bitwise.scala 102:21]
-    node _T_549 = shr(_T_546, 4) @[Bitwise.scala 103:21]
-    node _T_550 = and(_T_549, _T_548) @[Bitwise.scala 103:31]
-    node _T_551 = bits(_T_546, 3, 0) @[Bitwise.scala 103:46]
-    node _T_552 = shl(_T_551, 4) @[Bitwise.scala 103:65]
-    node _T_553 = not(_T_548) @[Bitwise.scala 103:77]
-    node _T_554 = and(_T_552, _T_553) @[Bitwise.scala 103:75]
-    node _T_555 = or(_T_550, _T_554) @[Bitwise.scala 103:39]
-    node _T_556 = bits(_T_548, 5, 0) @[Bitwise.scala 102:28]
-    node _T_557 = shl(_T_556, 2) @[Bitwise.scala 102:47]
-    node _T_558 = xor(_T_548, _T_557) @[Bitwise.scala 102:21]
-    node _T_559 = shr(_T_555, 2) @[Bitwise.scala 103:21]
-    node _T_560 = and(_T_559, _T_558) @[Bitwise.scala 103:31]
-    node _T_561 = bits(_T_555, 5, 0) @[Bitwise.scala 103:46]
-    node _T_562 = shl(_T_561, 2) @[Bitwise.scala 103:65]
-    node _T_563 = not(_T_558) @[Bitwise.scala 103:77]
-    node _T_564 = and(_T_562, _T_563) @[Bitwise.scala 103:75]
-    node _T_565 = or(_T_560, _T_564) @[Bitwise.scala 103:39]
-    node _T_566 = bits(_T_558, 6, 0) @[Bitwise.scala 102:28]
-    node _T_567 = shl(_T_566, 1) @[Bitwise.scala 102:47]
-    node _T_568 = xor(_T_558, _T_567) @[Bitwise.scala 102:21]
-    node _T_569 = shr(_T_565, 1) @[Bitwise.scala 103:21]
-    node _T_570 = and(_T_569, _T_568) @[Bitwise.scala 103:31]
-    node _T_571 = bits(_T_565, 6, 0) @[Bitwise.scala 103:46]
-    node _T_572 = shl(_T_571, 1) @[Bitwise.scala 103:65]
-    node _T_573 = not(_T_568) @[Bitwise.scala 103:77]
-    node _T_574 = and(_T_572, _T_573) @[Bitwise.scala 103:75]
-    node _T_575 = or(_T_570, _T_574) @[Bitwise.scala 103:39]
-    node _T_576 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58]
-    node _T_577 = bits(_T_576, 4, 4) @[lsu_dccm_ctl.scala 156:134]
-    node _T_578 = bits(_T_577, 0, 0) @[lsu_dccm_ctl.scala 156:139]
-    node _T_579 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58]
-    node _T_580 = bits(_T_579, 39, 32) @[lsu_dccm_ctl.scala 156:196]
-    node _T_581 = bits(io.addr_in_pic_m, 0, 0) @[lsu_dccm_ctl.scala 156:232]
-    node _T_582 = bits(picm_rd_data_m, 39, 32) @[lsu_dccm_ctl.scala 156:253]
-    node _T_583 = bits(io.addr_in_dccm_m, 0, 0) @[Bitwise.scala 72:15]
-    node _T_584 = mux(_T_583, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
-    node _T_585 = bits(dccm_rdata_m, 39, 32) @[lsu_dccm_ctl.scala 156:308]
-    node _T_586 = and(_T_584, _T_585) @[lsu_dccm_ctl.scala 156:294]
-    node _T_587 = mux(_T_581, _T_582, _T_586) @[lsu_dccm_ctl.scala 156:214]
-    node _T_588 = mux(_T_578, _T_580, _T_587) @[lsu_dccm_ctl.scala 156:78]
-    node _T_589 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
-    node _T_590 = xor(UInt<8>("h0ff"), _T_589) @[Bitwise.scala 102:21]
-    node _T_591 = shr(_T_588, 4) @[Bitwise.scala 103:21]
-    node _T_592 = and(_T_591, _T_590) @[Bitwise.scala 103:31]
-    node _T_593 = bits(_T_588, 3, 0) @[Bitwise.scala 103:46]
-    node _T_594 = shl(_T_593, 4) @[Bitwise.scala 103:65]
-    node _T_595 = not(_T_590) @[Bitwise.scala 103:77]
-    node _T_596 = and(_T_594, _T_595) @[Bitwise.scala 103:75]
-    node _T_597 = or(_T_592, _T_596) @[Bitwise.scala 103:39]
-    node _T_598 = bits(_T_590, 5, 0) @[Bitwise.scala 102:28]
-    node _T_599 = shl(_T_598, 2) @[Bitwise.scala 102:47]
-    node _T_600 = xor(_T_590, _T_599) @[Bitwise.scala 102:21]
-    node _T_601 = shr(_T_597, 2) @[Bitwise.scala 103:21]
-    node _T_602 = and(_T_601, _T_600) @[Bitwise.scala 103:31]
-    node _T_603 = bits(_T_597, 5, 0) @[Bitwise.scala 103:46]
-    node _T_604 = shl(_T_603, 2) @[Bitwise.scala 103:65]
-    node _T_605 = not(_T_600) @[Bitwise.scala 103:77]
-    node _T_606 = and(_T_604, _T_605) @[Bitwise.scala 103:75]
-    node _T_607 = or(_T_602, _T_606) @[Bitwise.scala 103:39]
-    node _T_608 = bits(_T_600, 6, 0) @[Bitwise.scala 102:28]
-    node _T_609 = shl(_T_608, 1) @[Bitwise.scala 102:47]
-    node _T_610 = xor(_T_600, _T_609) @[Bitwise.scala 102:21]
-    node _T_611 = shr(_T_607, 1) @[Bitwise.scala 103:21]
-    node _T_612 = and(_T_611, _T_610) @[Bitwise.scala 103:31]
-    node _T_613 = bits(_T_607, 6, 0) @[Bitwise.scala 103:46]
-    node _T_614 = shl(_T_613, 1) @[Bitwise.scala 103:65]
-    node _T_615 = not(_T_610) @[Bitwise.scala 103:77]
-    node _T_616 = and(_T_614, _T_615) @[Bitwise.scala 103:75]
-    node _T_617 = or(_T_612, _T_616) @[Bitwise.scala 103:39]
-    node _T_618 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58]
-    node _T_619 = bits(_T_618, 5, 5) @[lsu_dccm_ctl.scala 156:134]
-    node _T_620 = bits(_T_619, 0, 0) @[lsu_dccm_ctl.scala 156:139]
-    node _T_621 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58]
-    node _T_622 = bits(_T_621, 47, 40) @[lsu_dccm_ctl.scala 156:196]
-    node _T_623 = bits(io.addr_in_pic_m, 0, 0) @[lsu_dccm_ctl.scala 156:232]
-    node _T_624 = bits(picm_rd_data_m, 47, 40) @[lsu_dccm_ctl.scala 156:253]
-    node _T_625 = bits(io.addr_in_dccm_m, 0, 0) @[Bitwise.scala 72:15]
-    node _T_626 = mux(_T_625, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
-    node _T_627 = bits(dccm_rdata_m, 47, 40) @[lsu_dccm_ctl.scala 156:308]
-    node _T_628 = and(_T_626, _T_627) @[lsu_dccm_ctl.scala 156:294]
-    node _T_629 = mux(_T_623, _T_624, _T_628) @[lsu_dccm_ctl.scala 156:214]
-    node _T_630 = mux(_T_620, _T_622, _T_629) @[lsu_dccm_ctl.scala 156:78]
-    node _T_631 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
-    node _T_632 = xor(UInt<8>("h0ff"), _T_631) @[Bitwise.scala 102:21]
-    node _T_633 = shr(_T_630, 4) @[Bitwise.scala 103:21]
-    node _T_634 = and(_T_633, _T_632) @[Bitwise.scala 103:31]
-    node _T_635 = bits(_T_630, 3, 0) @[Bitwise.scala 103:46]
-    node _T_636 = shl(_T_635, 4) @[Bitwise.scala 103:65]
-    node _T_637 = not(_T_632) @[Bitwise.scala 103:77]
-    node _T_638 = and(_T_636, _T_637) @[Bitwise.scala 103:75]
-    node _T_639 = or(_T_634, _T_638) @[Bitwise.scala 103:39]
-    node _T_640 = bits(_T_632, 5, 0) @[Bitwise.scala 102:28]
-    node _T_641 = shl(_T_640, 2) @[Bitwise.scala 102:47]
-    node _T_642 = xor(_T_632, _T_641) @[Bitwise.scala 102:21]
-    node _T_643 = shr(_T_639, 2) @[Bitwise.scala 103:21]
-    node _T_644 = and(_T_643, _T_642) @[Bitwise.scala 103:31]
-    node _T_645 = bits(_T_639, 5, 0) @[Bitwise.scala 103:46]
-    node _T_646 = shl(_T_645, 2) @[Bitwise.scala 103:65]
-    node _T_647 = not(_T_642) @[Bitwise.scala 103:77]
-    node _T_648 = and(_T_646, _T_647) @[Bitwise.scala 103:75]
-    node _T_649 = or(_T_644, _T_648) @[Bitwise.scala 103:39]
-    node _T_650 = bits(_T_642, 6, 0) @[Bitwise.scala 102:28]
-    node _T_651 = shl(_T_650, 1) @[Bitwise.scala 102:47]
-    node _T_652 = xor(_T_642, _T_651) @[Bitwise.scala 102:21]
-    node _T_653 = shr(_T_649, 1) @[Bitwise.scala 103:21]
-    node _T_654 = and(_T_653, _T_652) @[Bitwise.scala 103:31]
-    node _T_655 = bits(_T_649, 6, 0) @[Bitwise.scala 103:46]
-    node _T_656 = shl(_T_655, 1) @[Bitwise.scala 103:65]
-    node _T_657 = not(_T_652) @[Bitwise.scala 103:77]
-    node _T_658 = and(_T_656, _T_657) @[Bitwise.scala 103:75]
-    node _T_659 = or(_T_654, _T_658) @[Bitwise.scala 103:39]
-    node _T_660 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58]
-    node _T_661 = bits(_T_660, 6, 6) @[lsu_dccm_ctl.scala 156:134]
-    node _T_662 = bits(_T_661, 0, 0) @[lsu_dccm_ctl.scala 156:139]
-    node _T_663 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58]
-    node _T_664 = bits(_T_663, 55, 48) @[lsu_dccm_ctl.scala 156:196]
-    node _T_665 = bits(io.addr_in_pic_m, 0, 0) @[lsu_dccm_ctl.scala 156:232]
-    node _T_666 = bits(picm_rd_data_m, 55, 48) @[lsu_dccm_ctl.scala 156:253]
-    node _T_667 = bits(io.addr_in_dccm_m, 0, 0) @[Bitwise.scala 72:15]
-    node _T_668 = mux(_T_667, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
-    node _T_669 = bits(dccm_rdata_m, 55, 48) @[lsu_dccm_ctl.scala 156:308]
-    node _T_670 = and(_T_668, _T_669) @[lsu_dccm_ctl.scala 156:294]
-    node _T_671 = mux(_T_665, _T_666, _T_670) @[lsu_dccm_ctl.scala 156:214]
-    node _T_672 = mux(_T_662, _T_664, _T_671) @[lsu_dccm_ctl.scala 156:78]
-    node _T_673 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
-    node _T_674 = xor(UInt<8>("h0ff"), _T_673) @[Bitwise.scala 102:21]
-    node _T_675 = shr(_T_672, 4) @[Bitwise.scala 103:21]
-    node _T_676 = and(_T_675, _T_674) @[Bitwise.scala 103:31]
-    node _T_677 = bits(_T_672, 3, 0) @[Bitwise.scala 103:46]
-    node _T_678 = shl(_T_677, 4) @[Bitwise.scala 103:65]
-    node _T_679 = not(_T_674) @[Bitwise.scala 103:77]
-    node _T_680 = and(_T_678, _T_679) @[Bitwise.scala 103:75]
-    node _T_681 = or(_T_676, _T_680) @[Bitwise.scala 103:39]
-    node _T_682 = bits(_T_674, 5, 0) @[Bitwise.scala 102:28]
-    node _T_683 = shl(_T_682, 2) @[Bitwise.scala 102:47]
-    node _T_684 = xor(_T_674, _T_683) @[Bitwise.scala 102:21]
-    node _T_685 = shr(_T_681, 2) @[Bitwise.scala 103:21]
-    node _T_686 = and(_T_685, _T_684) @[Bitwise.scala 103:31]
-    node _T_687 = bits(_T_681, 5, 0) @[Bitwise.scala 103:46]
-    node _T_688 = shl(_T_687, 2) @[Bitwise.scala 103:65]
-    node _T_689 = not(_T_684) @[Bitwise.scala 103:77]
-    node _T_690 = and(_T_688, _T_689) @[Bitwise.scala 103:75]
-    node _T_691 = or(_T_686, _T_690) @[Bitwise.scala 103:39]
-    node _T_692 = bits(_T_684, 6, 0) @[Bitwise.scala 102:28]
-    node _T_693 = shl(_T_692, 1) @[Bitwise.scala 102:47]
-    node _T_694 = xor(_T_684, _T_693) @[Bitwise.scala 102:21]
-    node _T_695 = shr(_T_691, 1) @[Bitwise.scala 103:21]
-    node _T_696 = and(_T_695, _T_694) @[Bitwise.scala 103:31]
-    node _T_697 = bits(_T_691, 6, 0) @[Bitwise.scala 103:46]
-    node _T_698 = shl(_T_697, 1) @[Bitwise.scala 103:65]
-    node _T_699 = not(_T_694) @[Bitwise.scala 103:77]
-    node _T_700 = and(_T_698, _T_699) @[Bitwise.scala 103:75]
-    node _T_701 = or(_T_696, _T_700) @[Bitwise.scala 103:39]
-    node _T_702 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58]
-    node _T_703 = bits(_T_702, 7, 7) @[lsu_dccm_ctl.scala 156:134]
-    node _T_704 = bits(_T_703, 0, 0) @[lsu_dccm_ctl.scala 156:139]
-    node _T_705 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58]
-    node _T_706 = bits(_T_705, 63, 56) @[lsu_dccm_ctl.scala 156:196]
-    node _T_707 = bits(io.addr_in_pic_m, 0, 0) @[lsu_dccm_ctl.scala 156:232]
-    node _T_708 = bits(picm_rd_data_m, 63, 56) @[lsu_dccm_ctl.scala 156:253]
-    node _T_709 = bits(io.addr_in_dccm_m, 0, 0) @[Bitwise.scala 72:15]
-    node _T_710 = mux(_T_709, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
-    node _T_711 = bits(dccm_rdata_m, 63, 56) @[lsu_dccm_ctl.scala 156:308]
-    node _T_712 = and(_T_710, _T_711) @[lsu_dccm_ctl.scala 156:294]
-    node _T_713 = mux(_T_707, _T_708, _T_712) @[lsu_dccm_ctl.scala 156:214]
-    node _T_714 = mux(_T_704, _T_706, _T_713) @[lsu_dccm_ctl.scala 156:78]
-    node _T_715 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
-    node _T_716 = xor(UInt<8>("h0ff"), _T_715) @[Bitwise.scala 102:21]
-    node _T_717 = shr(_T_714, 4) @[Bitwise.scala 103:21]
-    node _T_718 = and(_T_717, _T_716) @[Bitwise.scala 103:31]
-    node _T_719 = bits(_T_714, 3, 0) @[Bitwise.scala 103:46]
-    node _T_720 = shl(_T_719, 4) @[Bitwise.scala 103:65]
-    node _T_721 = not(_T_716) @[Bitwise.scala 103:77]
-    node _T_722 = and(_T_720, _T_721) @[Bitwise.scala 103:75]
-    node _T_723 = or(_T_718, _T_722) @[Bitwise.scala 103:39]
-    node _T_724 = bits(_T_716, 5, 0) @[Bitwise.scala 102:28]
-    node _T_725 = shl(_T_724, 2) @[Bitwise.scala 102:47]
-    node _T_726 = xor(_T_716, _T_725) @[Bitwise.scala 102:21]
-    node _T_727 = shr(_T_723, 2) @[Bitwise.scala 103:21]
-    node _T_728 = and(_T_727, _T_726) @[Bitwise.scala 103:31]
-    node _T_729 = bits(_T_723, 5, 0) @[Bitwise.scala 103:46]
-    node _T_730 = shl(_T_729, 2) @[Bitwise.scala 103:65]
-    node _T_731 = not(_T_726) @[Bitwise.scala 103:77]
-    node _T_732 = and(_T_730, _T_731) @[Bitwise.scala 103:75]
-    node _T_733 = or(_T_728, _T_732) @[Bitwise.scala 103:39]
-    node _T_734 = bits(_T_726, 6, 0) @[Bitwise.scala 102:28]
-    node _T_735 = shl(_T_734, 1) @[Bitwise.scala 102:47]
-    node _T_736 = xor(_T_726, _T_735) @[Bitwise.scala 102:21]
-    node _T_737 = shr(_T_733, 1) @[Bitwise.scala 103:21]
-    node _T_738 = and(_T_737, _T_736) @[Bitwise.scala 103:31]
-    node _T_739 = bits(_T_733, 6, 0) @[Bitwise.scala 103:46]
-    node _T_740 = shl(_T_739, 1) @[Bitwise.scala 103:65]
-    node _T_741 = not(_T_736) @[Bitwise.scala 103:77]
-    node _T_742 = and(_T_740, _T_741) @[Bitwise.scala 103:75]
-    node _T_743 = or(_T_738, _T_742) @[Bitwise.scala 103:39]
-    wire _T_744 : UInt<8>[8] @[lsu_dccm_ctl.scala 156:62]
-    _T_744[0] <= _T_449 @[lsu_dccm_ctl.scala 156:62]
-    _T_744[1] <= _T_491 @[lsu_dccm_ctl.scala 156:62]
-    _T_744[2] <= _T_533 @[lsu_dccm_ctl.scala 156:62]
-    _T_744[3] <= _T_575 @[lsu_dccm_ctl.scala 156:62]
-    _T_744[4] <= _T_617 @[lsu_dccm_ctl.scala 156:62]
-    _T_744[5] <= _T_659 @[lsu_dccm_ctl.scala 156:62]
-    _T_744[6] <= _T_701 @[lsu_dccm_ctl.scala 156:62]
-    _T_744[7] <= _T_743 @[lsu_dccm_ctl.scala 156:62]
-    node _T_745 = cat(_T_744[6], _T_744[7]) @[Cat.scala 29:58]
-    node _T_746 = cat(_T_744[4], _T_744[5]) @[Cat.scala 29:58]
-    node _T_747 = cat(_T_746, _T_745) @[Cat.scala 29:58]
-    node _T_748 = cat(_T_744[2], _T_744[3]) @[Cat.scala 29:58]
-    node _T_749 = cat(_T_744[0], _T_744[1]) @[Cat.scala 29:58]
-    node _T_750 = cat(_T_749, _T_748) @[Cat.scala 29:58]
-    node _T_751 = cat(_T_750, _T_747) @[Cat.scala 29:58]
-    node _T_752 = shl(UInt<32>("h0ffffffff"), 32) @[Bitwise.scala 102:47]
-    node _T_753 = xor(UInt<64>("h0ffffffffffffffff"), _T_752) @[Bitwise.scala 102:21]
-    node _T_754 = shr(_T_751, 32) @[Bitwise.scala 103:21]
-    node _T_755 = and(_T_754, _T_753) @[Bitwise.scala 103:31]
-    node _T_756 = bits(_T_751, 31, 0) @[Bitwise.scala 103:46]
-    node _T_757 = shl(_T_756, 32) @[Bitwise.scala 103:65]
-    node _T_758 = not(_T_753) @[Bitwise.scala 103:77]
-    node _T_759 = and(_T_757, _T_758) @[Bitwise.scala 103:75]
-    node _T_760 = or(_T_755, _T_759) @[Bitwise.scala 103:39]
-    node _T_761 = bits(_T_753, 47, 0) @[Bitwise.scala 102:28]
-    node _T_762 = shl(_T_761, 16) @[Bitwise.scala 102:47]
-    node _T_763 = xor(_T_753, _T_762) @[Bitwise.scala 102:21]
-    node _T_764 = shr(_T_760, 16) @[Bitwise.scala 103:21]
-    node _T_765 = and(_T_764, _T_763) @[Bitwise.scala 103:31]
-    node _T_766 = bits(_T_760, 47, 0) @[Bitwise.scala 103:46]
-    node _T_767 = shl(_T_766, 16) @[Bitwise.scala 103:65]
-    node _T_768 = not(_T_763) @[Bitwise.scala 103:77]
-    node _T_769 = and(_T_767, _T_768) @[Bitwise.scala 103:75]
-    node _T_770 = or(_T_765, _T_769) @[Bitwise.scala 103:39]
-    node _T_771 = bits(_T_763, 55, 0) @[Bitwise.scala 102:28]
-    node _T_772 = shl(_T_771, 8) @[Bitwise.scala 102:47]
-    node _T_773 = xor(_T_763, _T_772) @[Bitwise.scala 102:21]
-    node _T_774 = shr(_T_770, 8) @[Bitwise.scala 103:21]
-    node _T_775 = and(_T_774, _T_773) @[Bitwise.scala 103:31]
-    node _T_776 = bits(_T_770, 55, 0) @[Bitwise.scala 103:46]
-    node _T_777 = shl(_T_776, 8) @[Bitwise.scala 103:65]
-    node _T_778 = not(_T_773) @[Bitwise.scala 103:77]
-    node _T_779 = and(_T_777, _T_778) @[Bitwise.scala 103:75]
-    node _T_780 = or(_T_775, _T_779) @[Bitwise.scala 103:39]
-    node _T_781 = bits(_T_773, 59, 0) @[Bitwise.scala 102:28]
-    node _T_782 = shl(_T_781, 4) @[Bitwise.scala 102:47]
-    node _T_783 = xor(_T_773, _T_782) @[Bitwise.scala 102:21]
-    node _T_784 = shr(_T_780, 4) @[Bitwise.scala 103:21]
-    node _T_785 = and(_T_784, _T_783) @[Bitwise.scala 103:31]
-    node _T_786 = bits(_T_780, 59, 0) @[Bitwise.scala 103:46]
-    node _T_787 = shl(_T_786, 4) @[Bitwise.scala 103:65]
-    node _T_788 = not(_T_783) @[Bitwise.scala 103:77]
-    node _T_789 = and(_T_787, _T_788) @[Bitwise.scala 103:75]
-    node _T_790 = or(_T_785, _T_789) @[Bitwise.scala 103:39]
-    node _T_791 = bits(_T_783, 61, 0) @[Bitwise.scala 102:28]
-    node _T_792 = shl(_T_791, 2) @[Bitwise.scala 102:47]
-    node _T_793 = xor(_T_783, _T_792) @[Bitwise.scala 102:21]
-    node _T_794 = shr(_T_790, 2) @[Bitwise.scala 103:21]
-    node _T_795 = and(_T_794, _T_793) @[Bitwise.scala 103:31]
-    node _T_796 = bits(_T_790, 61, 0) @[Bitwise.scala 103:46]
-    node _T_797 = shl(_T_796, 2) @[Bitwise.scala 103:65]
-    node _T_798 = not(_T_793) @[Bitwise.scala 103:77]
-    node _T_799 = and(_T_797, _T_798) @[Bitwise.scala 103:75]
-    node _T_800 = or(_T_795, _T_799) @[Bitwise.scala 103:39]
-    node _T_801 = bits(_T_793, 62, 0) @[Bitwise.scala 102:28]
-    node _T_802 = shl(_T_801, 1) @[Bitwise.scala 102:47]
-    node _T_803 = xor(_T_793, _T_802) @[Bitwise.scala 102:21]
-    node _T_804 = shr(_T_800, 1) @[Bitwise.scala 103:21]
-    node _T_805 = and(_T_804, _T_803) @[Bitwise.scala 103:31]
-    node _T_806 = bits(_T_800, 62, 0) @[Bitwise.scala 103:46]
-    node _T_807 = shl(_T_806, 1) @[Bitwise.scala 103:65]
-    node _T_808 = not(_T_803) @[Bitwise.scala 103:77]
-    node _T_809 = and(_T_807, _T_808) @[Bitwise.scala 103:75]
-    node _T_810 = or(_T_805, _T_809) @[Bitwise.scala 103:39]
-    lsu_rdata_m <= _T_810 @[lsu_dccm_ctl.scala 156:28]
-    node _T_811 = and(io.lsu_pkt_m.valid, io.lsu_pkt_m.bits.load) @[lsu_dccm_ctl.scala 157:78]
-    node _T_812 = or(io.addr_in_pic_m, io.addr_in_dccm_m) @[lsu_dccm_ctl.scala 157:123]
-    node _T_813 = and(_T_811, _T_812) @[lsu_dccm_ctl.scala 157:103]
-    node _T_814 = or(_T_813, io.clk_override) @[lsu_dccm_ctl.scala 157:145]
-    node _T_815 = bits(_T_814, 0, 0) @[lib.scala 8:44]
-    node _T_816 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44]
-    inst rvclkhdr of rvclkhdr_4 @[lib.scala 368:23]
-    rvclkhdr.clock <= clock
-    rvclkhdr.reset <= reset
-    rvclkhdr.io.clk <= clock @[lib.scala 370:18]
-    rvclkhdr.io.en <= _T_815 @[lib.scala 371:17]
-    rvclkhdr.io.scan_mode <= _T_816 @[lib.scala 372:24]
-    reg _T_817 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
-    _T_817 <= lsu_ld_data_corr_m @[lib.scala 374:16]
-    io.lsu_ld_data_corr_r <= _T_817 @[lsu_dccm_ctl.scala 157:28]
-    node _T_818 = bits(io.lsu_addr_m, 1, 0) @[lsu_dccm_ctl.scala 158:63]
-    node _T_819 = mul(UInt<4>("h08"), _T_818) @[lsu_dccm_ctl.scala 158:49]
-    node _T_820 = dshr(lsu_rdata_m, _T_819) @[lsu_dccm_ctl.scala 158:43]
-    io.lsu_ld_data_m <= _T_820 @[lsu_dccm_ctl.scala 158:28]
-    node _T_821 = bits(io.lsu_addr_m, 1, 0) @[lsu_dccm_ctl.scala 159:68]
-    node _T_822 = mul(UInt<4>("h08"), _T_821) @[lsu_dccm_ctl.scala 159:54]
-    node _T_823 = dshr(lsu_rdata_corr_m, _T_822) @[lsu_dccm_ctl.scala 159:48]
-    lsu_ld_data_corr_m <= _T_823 @[lsu_dccm_ctl.scala 159:28]
-    node _T_824 = bits(io.lsu_addr_d, 15, 2) @[lsu_dccm_ctl.scala 163:44]
-    node _T_825 = bits(io.lsu_addr_r, 15, 2) @[lsu_dccm_ctl.scala 163:77]
-    node _T_826 = eq(_T_824, _T_825) @[lsu_dccm_ctl.scala 163:60]
-    node _T_827 = bits(io.end_addr_d, 15, 2) @[lsu_dccm_ctl.scala 163:117]
-    node _T_828 = bits(io.lsu_addr_r, 15, 2) @[lsu_dccm_ctl.scala 163:150]
-    node _T_829 = eq(_T_827, _T_828) @[lsu_dccm_ctl.scala 163:133]
-    node _T_830 = or(_T_826, _T_829) @[lsu_dccm_ctl.scala 163:101]
-    node _T_831 = and(_T_830, io.lsu_pkt_d.valid) @[lsu_dccm_ctl.scala 163:175]
-    node _T_832 = and(_T_831, io.lsu_pkt_d.bits.store) @[lsu_dccm_ctl.scala 163:196]
-    node _T_833 = and(_T_832, io.lsu_pkt_d.bits.dma) @[lsu_dccm_ctl.scala 163:222]
-    node _T_834 = and(_T_833, io.addr_in_dccm_d) @[lsu_dccm_ctl.scala 163:246]
-    node _T_835 = bits(io.lsu_addr_m, 15, 2) @[lsu_dccm_ctl.scala 164:21]
-    node _T_836 = bits(io.lsu_addr_r, 15, 2) @[lsu_dccm_ctl.scala 164:54]
-    node _T_837 = eq(_T_835, _T_836) @[lsu_dccm_ctl.scala 164:37]
-    node _T_838 = bits(io.end_addr_m, 15, 2) @[lsu_dccm_ctl.scala 164:94]
-    node _T_839 = bits(io.lsu_addr_r, 15, 2) @[lsu_dccm_ctl.scala 164:127]
-    node _T_840 = eq(_T_838, _T_839) @[lsu_dccm_ctl.scala 164:110]
-    node _T_841 = or(_T_837, _T_840) @[lsu_dccm_ctl.scala 164:78]
-    node _T_842 = and(_T_841, io.lsu_pkt_m.valid) @[lsu_dccm_ctl.scala 164:152]
-    node _T_843 = and(_T_842, io.lsu_pkt_m.bits.store) @[lsu_dccm_ctl.scala 164:173]
-    node _T_844 = and(_T_843, io.lsu_pkt_m.bits.dma) @[lsu_dccm_ctl.scala 164:199]
-    node _T_845 = and(_T_844, io.addr_in_dccm_m) @[lsu_dccm_ctl.scala 164:223]
-    node kill_ecc_corr_lo_r = or(_T_834, _T_845) @[lsu_dccm_ctl.scala 163:267]
-    node _T_846 = bits(io.lsu_addr_d, 15, 2) @[lsu_dccm_ctl.scala 166:44]
-    node _T_847 = bits(io.end_addr_r, 15, 2) @[lsu_dccm_ctl.scala 166:77]
-    node _T_848 = eq(_T_846, _T_847) @[lsu_dccm_ctl.scala 166:60]
-    node _T_849 = bits(io.end_addr_d, 15, 2) @[lsu_dccm_ctl.scala 166:117]
-    node _T_850 = bits(io.end_addr_r, 15, 2) @[lsu_dccm_ctl.scala 166:150]
-    node _T_851 = eq(_T_849, _T_850) @[lsu_dccm_ctl.scala 166:133]
-    node _T_852 = or(_T_848, _T_851) @[lsu_dccm_ctl.scala 166:101]
-    node _T_853 = and(_T_852, io.lsu_pkt_d.valid) @[lsu_dccm_ctl.scala 166:175]
-    node _T_854 = and(_T_853, io.lsu_pkt_d.bits.store) @[lsu_dccm_ctl.scala 166:196]
-    node _T_855 = and(_T_854, io.lsu_pkt_d.bits.dma) @[lsu_dccm_ctl.scala 166:222]
-    node _T_856 = and(_T_855, io.addr_in_dccm_d) @[lsu_dccm_ctl.scala 166:246]
-    node _T_857 = bits(io.lsu_addr_m, 15, 2) @[lsu_dccm_ctl.scala 167:21]
-    node _T_858 = bits(io.end_addr_r, 15, 2) @[lsu_dccm_ctl.scala 167:54]
-    node _T_859 = eq(_T_857, _T_858) @[lsu_dccm_ctl.scala 167:37]
-    node _T_860 = bits(io.end_addr_m, 15, 2) @[lsu_dccm_ctl.scala 167:94]
-    node _T_861 = bits(io.end_addr_r, 15, 2) @[lsu_dccm_ctl.scala 167:127]
-    node _T_862 = eq(_T_860, _T_861) @[lsu_dccm_ctl.scala 167:110]
-    node _T_863 = or(_T_859, _T_862) @[lsu_dccm_ctl.scala 167:78]
-    node _T_864 = and(_T_863, io.lsu_pkt_m.valid) @[lsu_dccm_ctl.scala 167:152]
-    node _T_865 = and(_T_864, io.lsu_pkt_m.bits.store) @[lsu_dccm_ctl.scala 167:173]
-    node _T_866 = and(_T_865, io.lsu_pkt_m.bits.dma) @[lsu_dccm_ctl.scala 167:199]
-    node _T_867 = and(_T_866, io.addr_in_dccm_m) @[lsu_dccm_ctl.scala 167:223]
-    node kill_ecc_corr_hi_r = or(_T_856, _T_867) @[lsu_dccm_ctl.scala 166:267]
-    node _T_868 = and(io.lsu_pkt_r.bits.load, io.single_ecc_error_lo_r) @[lsu_dccm_ctl.scala 169:60]
-    node _T_869 = eq(io.lsu_raw_fwd_lo_r, UInt<1>("h00")) @[lsu_dccm_ctl.scala 169:89]
-    node ld_single_ecc_error_lo_r = and(_T_868, _T_869) @[lsu_dccm_ctl.scala 169:87]
-    node _T_870 = and(io.lsu_pkt_r.bits.load, io.single_ecc_error_hi_r) @[lsu_dccm_ctl.scala 170:60]
-    node _T_871 = eq(io.lsu_raw_fwd_hi_r, UInt<1>("h00")) @[lsu_dccm_ctl.scala 170:89]
-    node ld_single_ecc_error_hi_r = and(_T_870, _T_871) @[lsu_dccm_ctl.scala 170:87]
-    node _T_872 = or(ld_single_ecc_error_lo_r, ld_single_ecc_error_hi_r) @[lsu_dccm_ctl.scala 171:63]
-    node _T_873 = eq(io.lsu_double_ecc_error_r, UInt<1>("h00")) @[lsu_dccm_ctl.scala 171:93]
-    node _T_874 = and(_T_872, _T_873) @[lsu_dccm_ctl.scala 171:91]
-    io.ld_single_ecc_error_r <= _T_874 @[lsu_dccm_ctl.scala 171:34]
-    node _T_875 = or(io.lsu_commit_r, io.lsu_pkt_r.bits.dma) @[lsu_dccm_ctl.scala 172:81]
-    node _T_876 = and(ld_single_ecc_error_lo_r, _T_875) @[lsu_dccm_ctl.scala 172:62]
-    node _T_877 = eq(kill_ecc_corr_lo_r, UInt<1>("h00")) @[lsu_dccm_ctl.scala 172:108]
-    node ld_single_ecc_error_lo_r_ns = and(_T_876, _T_877) @[lsu_dccm_ctl.scala 172:106]
-    node _T_878 = or(io.lsu_commit_r, io.lsu_pkt_r.bits.dma) @[lsu_dccm_ctl.scala 173:81]
-    node _T_879 = and(ld_single_ecc_error_hi_r, _T_878) @[lsu_dccm_ctl.scala 173:62]
-    node _T_880 = eq(kill_ecc_corr_hi_r, UInt<1>("h00")) @[lsu_dccm_ctl.scala 173:108]
-    node ld_single_ecc_error_hi_r_ns = and(_T_879, _T_880) @[lsu_dccm_ctl.scala 173:106]
-    node _T_881 = or(io.lsu_pkt_d.bits.word, io.lsu_pkt_d.bits.dword) @[lsu_dccm_ctl.scala 175:125]
-    node _T_882 = eq(_T_881, UInt<1>("h00")) @[lsu_dccm_ctl.scala 175:100]
-    node _T_883 = bits(io.lsu_addr_d, 1, 0) @[lsu_dccm_ctl.scala 175:168]
-    node _T_884 = neq(_T_883, UInt<2>("h00")) @[lsu_dccm_ctl.scala 175:174]
-    node _T_885 = or(_T_882, _T_884) @[lsu_dccm_ctl.scala 175:152]
-    node _T_886 = and(io.lsu_pkt_d.bits.store, _T_885) @[lsu_dccm_ctl.scala 175:97]
-    node _T_887 = or(io.lsu_pkt_d.bits.load, _T_886) @[lsu_dccm_ctl.scala 175:70]
-    node _T_888 = and(io.lsu_pkt_d.valid, _T_887) @[lsu_dccm_ctl.scala 175:44]
-    node lsu_dccm_rden_d = and(_T_888, io.addr_in_dccm_d) @[lsu_dccm_ctl.scala 175:191]
-    node _T_889 = or(ld_single_ecc_error_lo_r_ff, ld_single_ecc_error_hi_r_ff) @[lsu_dccm_ctl.scala 178:63]
-    node _T_890 = eq(lsu_double_ecc_error_r_ff, UInt<1>("h00")) @[lsu_dccm_ctl.scala 178:96]
-    node _T_891 = and(_T_889, _T_890) @[lsu_dccm_ctl.scala 178:94]
-    io.ld_single_ecc_error_r_ff <= _T_891 @[lsu_dccm_ctl.scala 178:31]
-    node _T_892 = or(lsu_dccm_rden_d, io.dma_dccm_wen) @[lsu_dccm_ctl.scala 179:75]
-    node _T_893 = or(_T_892, io.ld_single_ecc_error_r_ff) @[lsu_dccm_ctl.scala 179:93]
-    node _T_894 = eq(_T_893, UInt<1>("h00")) @[lsu_dccm_ctl.scala 179:57]
-    node _T_895 = bits(io.stbuf_addr_any, 3, 2) @[lsu_dccm_ctl.scala 180:44]
-    node _T_896 = bits(io.lsu_addr_d, 3, 2) @[lsu_dccm_ctl.scala 180:112]
-    node _T_897 = eq(_T_895, _T_896) @[lsu_dccm_ctl.scala 180:95]
-    node _T_898 = bits(io.stbuf_addr_any, 3, 2) @[lsu_dccm_ctl.scala 181:25]
-    node _T_899 = bits(io.end_addr_d, 3, 2) @[lsu_dccm_ctl.scala 181:93]
-    node _T_900 = eq(_T_898, _T_899) @[lsu_dccm_ctl.scala 181:76]
-    node _T_901 = or(_T_897, _T_900) @[lsu_dccm_ctl.scala 180:171]
-    node _T_902 = eq(_T_901, UInt<1>("h00")) @[lsu_dccm_ctl.scala 180:24]
-    node _T_903 = and(lsu_dccm_rden_d, _T_902) @[lsu_dccm_ctl.scala 180:22]
-    node _T_904 = or(_T_894, _T_903) @[lsu_dccm_ctl.scala 179:124]
-    node _T_905 = and(io.stbuf_reqvld_any, _T_904) @[lsu_dccm_ctl.scala 179:54]
-    io.lsu_stbuf_commit_any <= _T_905 @[lsu_dccm_ctl.scala 179:31]
-    node _T_906 = or(io.dma_dccm_wen, io.lsu_stbuf_commit_any) @[lsu_dccm_ctl.scala 185:41]
-    node _T_907 = or(_T_906, io.ld_single_ecc_error_r_ff) @[lsu_dccm_ctl.scala 185:67]
-    io.dccm.wren <= _T_907 @[lsu_dccm_ctl.scala 185:22]
-    node _T_908 = and(lsu_dccm_rden_d, io.addr_in_dccm_d) @[lsu_dccm_ctl.scala 186:41]
-    io.dccm.rden <= _T_908 @[lsu_dccm_ctl.scala 186:22]
-    node _T_909 = bits(io.ld_single_ecc_error_r_ff, 0, 0) @[lsu_dccm_ctl.scala 188:57]
-    node _T_910 = eq(ld_single_ecc_error_lo_r_ff, UInt<1>("h01")) @[lsu_dccm_ctl.scala 189:36]
-    node _T_911 = bits(ld_sec_addr_lo_r_ff, 15, 0) @[lsu_dccm_ctl.scala 189:62]
-    node _T_912 = bits(ld_sec_addr_hi_r_ff, 15, 0) @[lsu_dccm_ctl.scala 189:97]
-    node _T_913 = mux(_T_910, _T_911, _T_912) @[lsu_dccm_ctl.scala 189:8]
-    node _T_914 = bits(io.dma_dccm_wen, 0, 0) @[lsu_dccm_ctl.scala 190:25]
-    node _T_915 = bits(io.lsu_addr_d, 15, 0) @[lsu_dccm_ctl.scala 190:45]
-    node _T_916 = bits(io.stbuf_addr_any, 15, 0) @[lsu_dccm_ctl.scala 190:78]
-    node _T_917 = mux(_T_914, _T_915, _T_916) @[lsu_dccm_ctl.scala 190:8]
-    node _T_918 = mux(_T_909, _T_913, _T_917) @[lsu_dccm_ctl.scala 188:28]
-    io.dccm.wr_addr_lo <= _T_918 @[lsu_dccm_ctl.scala 188:22]
-    node _T_919 = bits(io.ld_single_ecc_error_r_ff, 0, 0) @[lsu_dccm_ctl.scala 192:57]
-    node _T_920 = eq(ld_single_ecc_error_hi_r_ff, UInt<1>("h01")) @[lsu_dccm_ctl.scala 193:36]
-    node _T_921 = bits(ld_sec_addr_hi_r_ff, 15, 0) @[lsu_dccm_ctl.scala 193:63]
-    node _T_922 = bits(ld_sec_addr_lo_r_ff, 15, 0) @[lsu_dccm_ctl.scala 193:99]
-    node _T_923 = mux(_T_920, _T_921, _T_922) @[lsu_dccm_ctl.scala 193:8]
-    node _T_924 = bits(io.dma_dccm_wen, 0, 0) @[lsu_dccm_ctl.scala 194:25]
-    node _T_925 = bits(io.end_addr_d, 15, 0) @[lsu_dccm_ctl.scala 194:46]
-    node _T_926 = bits(io.stbuf_addr_any, 15, 0) @[lsu_dccm_ctl.scala 194:79]
-    node _T_927 = mux(_T_924, _T_925, _T_926) @[lsu_dccm_ctl.scala 194:8]
-    node _T_928 = mux(_T_919, _T_923, _T_927) @[lsu_dccm_ctl.scala 192:28]
-    io.dccm.wr_addr_hi <= _T_928 @[lsu_dccm_ctl.scala 192:22]
-    node _T_929 = bits(io.lsu_addr_d, 15, 0) @[lsu_dccm_ctl.scala 196:38]
-    io.dccm.rd_addr_lo <= _T_929 @[lsu_dccm_ctl.scala 196:22]
-    node _T_930 = bits(io.end_addr_d, 15, 0) @[lsu_dccm_ctl.scala 197:38]
-    io.dccm.rd_addr_hi <= _T_930 @[lsu_dccm_ctl.scala 197:22]
-    node _T_931 = bits(io.ld_single_ecc_error_r_ff, 0, 0) @[lsu_dccm_ctl.scala 199:57]
-    node _T_932 = eq(ld_single_ecc_error_lo_r_ff, UInt<1>("h01")) @[lsu_dccm_ctl.scala 200:36]
-    node _T_933 = bits(io.sec_data_ecc_lo_r_ff, 6, 0) @[lsu_dccm_ctl.scala 200:70]
-    node _T_934 = bits(io.sec_data_lo_r_ff, 31, 0) @[lsu_dccm_ctl.scala 200:110]
-    node _T_935 = cat(_T_933, _T_934) @[Cat.scala 29:58]
-    node _T_936 = bits(io.sec_data_ecc_hi_r_ff, 6, 0) @[lsu_dccm_ctl.scala 201:34]
-    node _T_937 = bits(io.sec_data_hi_r_ff, 31, 0) @[lsu_dccm_ctl.scala 201:74]
-    node _T_938 = cat(_T_936, _T_937) @[Cat.scala 29:58]
-    node _T_939 = mux(_T_932, _T_935, _T_938) @[lsu_dccm_ctl.scala 200:8]
-    node _T_940 = bits(io.dma_dccm_wen, 0, 0) @[lsu_dccm_ctl.scala 202:25]
-    node _T_941 = bits(io.dma_dccm_wdata_ecc_lo, 6, 0) @[lsu_dccm_ctl.scala 202:60]
-    node _T_942 = bits(io.dma_dccm_wdata_lo, 31, 0) @[lsu_dccm_ctl.scala 202:101]
-    node _T_943 = cat(_T_941, _T_942) @[Cat.scala 29:58]
-    node _T_944 = bits(io.stbuf_ecc_any, 6, 0) @[lsu_dccm_ctl.scala 203:27]
-    node _T_945 = bits(io.stbuf_data_any, 31, 0) @[lsu_dccm_ctl.scala 203:65]
-    node _T_946 = cat(_T_944, _T_945) @[Cat.scala 29:58]
-    node _T_947 = mux(_T_940, _T_943, _T_946) @[lsu_dccm_ctl.scala 202:8]
-    node _T_948 = mux(_T_931, _T_939, _T_947) @[lsu_dccm_ctl.scala 199:28]
-    io.dccm.wr_data_lo <= _T_948 @[lsu_dccm_ctl.scala 199:22]
-    node _T_949 = bits(io.ld_single_ecc_error_r_ff, 0, 0) @[lsu_dccm_ctl.scala 205:57]
-    node _T_950 = eq(ld_single_ecc_error_hi_r_ff, UInt<1>("h01")) @[lsu_dccm_ctl.scala 206:36]
-    node _T_951 = bits(io.sec_data_ecc_hi_r_ff, 6, 0) @[lsu_dccm_ctl.scala 206:71]
-    node _T_952 = bits(io.sec_data_hi_r_ff, 31, 0) @[lsu_dccm_ctl.scala 206:111]
-    node _T_953 = cat(_T_951, _T_952) @[Cat.scala 29:58]
-    node _T_954 = bits(io.sec_data_ecc_lo_r_ff, 6, 0) @[lsu_dccm_ctl.scala 207:34]
-    node _T_955 = bits(io.sec_data_lo_r_ff, 31, 0) @[lsu_dccm_ctl.scala 207:74]
-    node _T_956 = cat(_T_954, _T_955) @[Cat.scala 29:58]
-    node _T_957 = mux(_T_950, _T_953, _T_956) @[lsu_dccm_ctl.scala 206:8]
-    node _T_958 = bits(io.dma_dccm_wen, 0, 0) @[lsu_dccm_ctl.scala 208:25]
-    node _T_959 = bits(io.dma_dccm_wdata_ecc_hi, 6, 0) @[lsu_dccm_ctl.scala 208:61]
-    node _T_960 = bits(io.dma_dccm_wdata_hi, 31, 0) @[lsu_dccm_ctl.scala 208:102]
-    node _T_961 = cat(_T_959, _T_960) @[Cat.scala 29:58]
-    node _T_962 = bits(io.stbuf_ecc_any, 6, 0) @[lsu_dccm_ctl.scala 209:27]
-    node _T_963 = bits(io.stbuf_data_any, 31, 0) @[lsu_dccm_ctl.scala 209:65]
-    node _T_964 = cat(_T_962, _T_963) @[Cat.scala 29:58]
-    node _T_965 = mux(_T_958, _T_961, _T_964) @[lsu_dccm_ctl.scala 208:8]
-    node _T_966 = mux(_T_949, _T_957, _T_965) @[lsu_dccm_ctl.scala 205:28]
-    io.dccm.wr_data_hi <= _T_966 @[lsu_dccm_ctl.scala 205:22]
-    node _T_967 = bits(io.lsu_pkt_m.bits.store, 0, 0) @[Bitwise.scala 72:15]
-    node _T_968 = mux(_T_967, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
-    node _T_969 = bits(io.lsu_pkt_m.bits.by, 0, 0) @[Bitwise.scala 72:15]
-    node _T_970 = mux(_T_969, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
-    node _T_971 = and(_T_970, UInt<4>("h01")) @[lsu_dccm_ctl.scala 212:94]
-    node _T_972 = bits(io.lsu_pkt_m.bits.half, 0, 0) @[Bitwise.scala 72:15]
-    node _T_973 = mux(_T_972, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
-    node _T_974 = and(_T_973, UInt<4>("h03")) @[lsu_dccm_ctl.scala 213:38]
-    node _T_975 = or(_T_971, _T_974) @[lsu_dccm_ctl.scala 212:107]
-    node _T_976 = bits(io.lsu_pkt_m.bits.word, 0, 0) @[Bitwise.scala 72:15]
-    node _T_977 = mux(_T_976, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
-    node _T_978 = and(_T_977, UInt<4>("h0f")) @[lsu_dccm_ctl.scala 214:38]
-    node _T_979 = or(_T_975, _T_978) @[lsu_dccm_ctl.scala 213:51]
-    node store_byteen_m = and(_T_968, _T_979) @[lsu_dccm_ctl.scala 212:58]
-    node _T_980 = bits(io.lsu_pkt_r.bits.store, 0, 0) @[Bitwise.scala 72:15]
-    node _T_981 = mux(_T_980, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
-    node _T_982 = bits(io.lsu_pkt_r.bits.by, 0, 0) @[Bitwise.scala 72:15]
-    node _T_983 = mux(_T_982, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
-    node _T_984 = and(_T_983, UInt<4>("h01")) @[lsu_dccm_ctl.scala 216:94]
-    node _T_985 = bits(io.lsu_pkt_r.bits.half, 0, 0) @[Bitwise.scala 72:15]
-    node _T_986 = mux(_T_985, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
-    node _T_987 = and(_T_986, UInt<4>("h03")) @[lsu_dccm_ctl.scala 217:38]
-    node _T_988 = or(_T_984, _T_987) @[lsu_dccm_ctl.scala 216:107]
-    node _T_989 = bits(io.lsu_pkt_r.bits.word, 0, 0) @[Bitwise.scala 72:15]
-    node _T_990 = mux(_T_989, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
-    node _T_991 = and(_T_990, UInt<4>("h0f")) @[lsu_dccm_ctl.scala 218:38]
-    node _T_992 = or(_T_988, _T_991) @[lsu_dccm_ctl.scala 217:51]
-    node store_byteen_r = and(_T_981, _T_992) @[lsu_dccm_ctl.scala 216:58]
-    wire store_byteen_ext_m : UInt<8>
-    store_byteen_ext_m <= UInt<1>("h00")
-    node _T_993 = bits(store_byteen_m, 3, 0) @[lsu_dccm_ctl.scala 220:39]
-    node _T_994 = bits(io.lsu_addr_m, 1, 0) @[lsu_dccm_ctl.scala 220:61]
-    node _T_995 = dshl(_T_993, _T_994) @[lsu_dccm_ctl.scala 220:45]
-    store_byteen_ext_m <= _T_995 @[lsu_dccm_ctl.scala 220:22]
-    wire store_byteen_ext_r : UInt<8>
-    store_byteen_ext_r <= UInt<1>("h00")
-    node _T_996 = bits(store_byteen_r, 3, 0) @[lsu_dccm_ctl.scala 222:39]
-    node _T_997 = bits(io.lsu_addr_r, 1, 0) @[lsu_dccm_ctl.scala 222:61]
-    node _T_998 = dshl(_T_996, _T_997) @[lsu_dccm_ctl.scala 222:45]
-    store_byteen_ext_r <= _T_998 @[lsu_dccm_ctl.scala 222:22]
-    node _T_999 = bits(io.stbuf_addr_any, 15, 2) @[lsu_dccm_ctl.scala 225:51]
-    node _T_1000 = bits(io.lsu_addr_m, 15, 2) @[lsu_dccm_ctl.scala 225:84]
-    node _T_1001 = eq(_T_999, _T_1000) @[lsu_dccm_ctl.scala 225:67]
-    node dccm_wr_bypass_d_m_lo = and(_T_1001, io.addr_in_dccm_m) @[lsu_dccm_ctl.scala 225:101]
-    node _T_1002 = bits(io.stbuf_addr_any, 15, 2) @[lsu_dccm_ctl.scala 226:51]
-    node _T_1003 = bits(io.end_addr_m, 15, 2) @[lsu_dccm_ctl.scala 226:84]
-    node _T_1004 = eq(_T_1002, _T_1003) @[lsu_dccm_ctl.scala 226:67]
-    node dccm_wr_bypass_d_m_hi = and(_T_1004, io.addr_in_dccm_m) @[lsu_dccm_ctl.scala 226:101]
-    node _T_1005 = bits(io.stbuf_addr_any, 15, 2) @[lsu_dccm_ctl.scala 228:51]
-    node _T_1006 = bits(io.lsu_addr_r, 15, 2) @[lsu_dccm_ctl.scala 228:84]
-    node _T_1007 = eq(_T_1005, _T_1006) @[lsu_dccm_ctl.scala 228:67]
-    node dccm_wr_bypass_d_r_lo = and(_T_1007, io.addr_in_dccm_r) @[lsu_dccm_ctl.scala 228:101]
-    node _T_1008 = bits(io.stbuf_addr_any, 15, 2) @[lsu_dccm_ctl.scala 229:51]
-    node _T_1009 = bits(io.end_addr_r, 15, 2) @[lsu_dccm_ctl.scala 229:84]
-    node _T_1010 = eq(_T_1008, _T_1009) @[lsu_dccm_ctl.scala 229:67]
-    node dccm_wr_bypass_d_r_hi = and(_T_1010, io.addr_in_dccm_r) @[lsu_dccm_ctl.scala 229:101]
-    wire dccm_wr_bypass_d_m_hi_Q : UInt<1>
-    dccm_wr_bypass_d_m_hi_Q <= UInt<1>("h00")
-    wire dccm_wr_bypass_d_m_lo_Q : UInt<1>
-    dccm_wr_bypass_d_m_lo_Q <= UInt<1>("h00")
-    wire dccm_wren_Q : UInt<1>
-    dccm_wren_Q <= UInt<1>("h00")
-    wire dccm_wr_data_Q : UInt<32>
-    dccm_wr_data_Q <= UInt<32>("h00")
-    wire store_data_pre_r : UInt<64>
-    store_data_pre_r <= UInt<64>("h00")
-    wire store_data_pre_hi_r : UInt<32>
-    store_data_pre_hi_r <= UInt<32>("h00")
-    wire store_data_pre_lo_r : UInt<32>
-    store_data_pre_lo_r <= UInt<32>("h00")
-    wire store_data_pre_m : UInt<64>
-    store_data_pre_m <= UInt<64>("h00")
-    wire store_data_hi_m : UInt<32>
-    store_data_hi_m <= UInt<32>("h00")
-    wire store_data_lo_m : UInt<32>
-    store_data_lo_m <= UInt<32>("h00")
-    node _T_1011 = mux(UInt<1>("h00"), UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
-    node _T_1012 = bits(io.store_data_m, 31, 0) @[lsu_dccm_ctl.scala 258:64]
-    node _T_1013 = cat(_T_1011, _T_1012) @[Cat.scala 29:58]
-    node _T_1014 = bits(io.lsu_addr_m, 1, 0) @[lsu_dccm_ctl.scala 258:92]
-    node _T_1015 = mul(UInt<4>("h08"), _T_1014) @[lsu_dccm_ctl.scala 258:78]
-    node _T_1016 = dshl(_T_1013, _T_1015) @[lsu_dccm_ctl.scala 258:72]
-    store_data_pre_m <= _T_1016 @[lsu_dccm_ctl.scala 258:29]
-    node _T_1017 = bits(store_data_pre_m, 63, 32) @[lsu_dccm_ctl.scala 259:48]
-    store_data_hi_m <= _T_1017 @[lsu_dccm_ctl.scala 259:29]
-    node _T_1018 = bits(store_data_pre_m, 31, 0) @[lsu_dccm_ctl.scala 260:48]
-    store_data_lo_m <= _T_1018 @[lsu_dccm_ctl.scala 260:29]
-    node _T_1019 = bits(store_byteen_ext_m, 0, 0) @[lsu_dccm_ctl.scala 261:139]
-    node _T_1020 = bits(_T_1019, 0, 0) @[lsu_dccm_ctl.scala 261:143]
-    node _T_1021 = bits(store_data_lo_m, 7, 0) @[lsu_dccm_ctl.scala 261:167]
-    node _T_1022 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_m_lo) @[lsu_dccm_ctl.scala 261:211]
-    node _T_1023 = bits(_T_1022, 0, 0) @[lsu_dccm_ctl.scala 261:237]
-    node _T_1024 = bits(io.stbuf_data_any, 7, 0) @[lsu_dccm_ctl.scala 261:262]
-    node _T_1025 = bits(io.sec_data_lo_m, 7, 0) @[lsu_dccm_ctl.scala 261:292]
-    node _T_1026 = mux(_T_1023, _T_1024, _T_1025) @[lsu_dccm_ctl.scala 261:185]
-    node _T_1027 = mux(_T_1020, _T_1021, _T_1026) @[lsu_dccm_ctl.scala 261:120]
-    node _T_1028 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
-    node _T_1029 = xor(UInt<8>("h0ff"), _T_1028) @[Bitwise.scala 102:21]
-    node _T_1030 = shr(_T_1027, 4) @[Bitwise.scala 103:21]
-    node _T_1031 = and(_T_1030, _T_1029) @[Bitwise.scala 103:31]
-    node _T_1032 = bits(_T_1027, 3, 0) @[Bitwise.scala 103:46]
-    node _T_1033 = shl(_T_1032, 4) @[Bitwise.scala 103:65]
-    node _T_1034 = not(_T_1029) @[Bitwise.scala 103:77]
-    node _T_1035 = and(_T_1033, _T_1034) @[Bitwise.scala 103:75]
-    node _T_1036 = or(_T_1031, _T_1035) @[Bitwise.scala 103:39]
-    node _T_1037 = bits(_T_1029, 5, 0) @[Bitwise.scala 102:28]
-    node _T_1038 = shl(_T_1037, 2) @[Bitwise.scala 102:47]
-    node _T_1039 = xor(_T_1029, _T_1038) @[Bitwise.scala 102:21]
-    node _T_1040 = shr(_T_1036, 2) @[Bitwise.scala 103:21]
-    node _T_1041 = and(_T_1040, _T_1039) @[Bitwise.scala 103:31]
-    node _T_1042 = bits(_T_1036, 5, 0) @[Bitwise.scala 103:46]
-    node _T_1043 = shl(_T_1042, 2) @[Bitwise.scala 103:65]
-    node _T_1044 = not(_T_1039) @[Bitwise.scala 103:77]
-    node _T_1045 = and(_T_1043, _T_1044) @[Bitwise.scala 103:75]
-    node _T_1046 = or(_T_1041, _T_1045) @[Bitwise.scala 103:39]
-    node _T_1047 = bits(_T_1039, 6, 0) @[Bitwise.scala 102:28]
-    node _T_1048 = shl(_T_1047, 1) @[Bitwise.scala 102:47]
-    node _T_1049 = xor(_T_1039, _T_1048) @[Bitwise.scala 102:21]
-    node _T_1050 = shr(_T_1046, 1) @[Bitwise.scala 103:21]
-    node _T_1051 = and(_T_1050, _T_1049) @[Bitwise.scala 103:31]
-    node _T_1052 = bits(_T_1046, 6, 0) @[Bitwise.scala 103:46]
-    node _T_1053 = shl(_T_1052, 1) @[Bitwise.scala 103:65]
-    node _T_1054 = not(_T_1049) @[Bitwise.scala 103:77]
-    node _T_1055 = and(_T_1053, _T_1054) @[Bitwise.scala 103:75]
-    node _T_1056 = or(_T_1051, _T_1055) @[Bitwise.scala 103:39]
-    node _T_1057 = bits(store_byteen_ext_m, 1, 1) @[lsu_dccm_ctl.scala 261:139]
-    node _T_1058 = bits(_T_1057, 0, 0) @[lsu_dccm_ctl.scala 261:143]
-    node _T_1059 = bits(store_data_lo_m, 15, 8) @[lsu_dccm_ctl.scala 261:167]
-    node _T_1060 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_m_lo) @[lsu_dccm_ctl.scala 261:211]
-    node _T_1061 = bits(_T_1060, 0, 0) @[lsu_dccm_ctl.scala 261:237]
-    node _T_1062 = bits(io.stbuf_data_any, 15, 8) @[lsu_dccm_ctl.scala 261:262]
-    node _T_1063 = bits(io.sec_data_lo_m, 15, 8) @[lsu_dccm_ctl.scala 261:292]
-    node _T_1064 = mux(_T_1061, _T_1062, _T_1063) @[lsu_dccm_ctl.scala 261:185]
-    node _T_1065 = mux(_T_1058, _T_1059, _T_1064) @[lsu_dccm_ctl.scala 261:120]
-    node _T_1066 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
-    node _T_1067 = xor(UInt<8>("h0ff"), _T_1066) @[Bitwise.scala 102:21]
-    node _T_1068 = shr(_T_1065, 4) @[Bitwise.scala 103:21]
-    node _T_1069 = and(_T_1068, _T_1067) @[Bitwise.scala 103:31]
-    node _T_1070 = bits(_T_1065, 3, 0) @[Bitwise.scala 103:46]
-    node _T_1071 = shl(_T_1070, 4) @[Bitwise.scala 103:65]
-    node _T_1072 = not(_T_1067) @[Bitwise.scala 103:77]
-    node _T_1073 = and(_T_1071, _T_1072) @[Bitwise.scala 103:75]
-    node _T_1074 = or(_T_1069, _T_1073) @[Bitwise.scala 103:39]
-    node _T_1075 = bits(_T_1067, 5, 0) @[Bitwise.scala 102:28]
-    node _T_1076 = shl(_T_1075, 2) @[Bitwise.scala 102:47]
-    node _T_1077 = xor(_T_1067, _T_1076) @[Bitwise.scala 102:21]
-    node _T_1078 = shr(_T_1074, 2) @[Bitwise.scala 103:21]
-    node _T_1079 = and(_T_1078, _T_1077) @[Bitwise.scala 103:31]
-    node _T_1080 = bits(_T_1074, 5, 0) @[Bitwise.scala 103:46]
-    node _T_1081 = shl(_T_1080, 2) @[Bitwise.scala 103:65]
-    node _T_1082 = not(_T_1077) @[Bitwise.scala 103:77]
-    node _T_1083 = and(_T_1081, _T_1082) @[Bitwise.scala 103:75]
-    node _T_1084 = or(_T_1079, _T_1083) @[Bitwise.scala 103:39]
-    node _T_1085 = bits(_T_1077, 6, 0) @[Bitwise.scala 102:28]
-    node _T_1086 = shl(_T_1085, 1) @[Bitwise.scala 102:47]
-    node _T_1087 = xor(_T_1077, _T_1086) @[Bitwise.scala 102:21]
-    node _T_1088 = shr(_T_1084, 1) @[Bitwise.scala 103:21]
-    node _T_1089 = and(_T_1088, _T_1087) @[Bitwise.scala 103:31]
-    node _T_1090 = bits(_T_1084, 6, 0) @[Bitwise.scala 103:46]
-    node _T_1091 = shl(_T_1090, 1) @[Bitwise.scala 103:65]
-    node _T_1092 = not(_T_1087) @[Bitwise.scala 103:77]
-    node _T_1093 = and(_T_1091, _T_1092) @[Bitwise.scala 103:75]
-    node _T_1094 = or(_T_1089, _T_1093) @[Bitwise.scala 103:39]
-    node _T_1095 = bits(store_byteen_ext_m, 2, 2) @[lsu_dccm_ctl.scala 261:139]
-    node _T_1096 = bits(_T_1095, 0, 0) @[lsu_dccm_ctl.scala 261:143]
-    node _T_1097 = bits(store_data_lo_m, 23, 16) @[lsu_dccm_ctl.scala 261:167]
-    node _T_1098 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_m_lo) @[lsu_dccm_ctl.scala 261:211]
-    node _T_1099 = bits(_T_1098, 0, 0) @[lsu_dccm_ctl.scala 261:237]
-    node _T_1100 = bits(io.stbuf_data_any, 23, 16) @[lsu_dccm_ctl.scala 261:262]
-    node _T_1101 = bits(io.sec_data_lo_m, 23, 16) @[lsu_dccm_ctl.scala 261:292]
-    node _T_1102 = mux(_T_1099, _T_1100, _T_1101) @[lsu_dccm_ctl.scala 261:185]
-    node _T_1103 = mux(_T_1096, _T_1097, _T_1102) @[lsu_dccm_ctl.scala 261:120]
-    node _T_1104 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
-    node _T_1105 = xor(UInt<8>("h0ff"), _T_1104) @[Bitwise.scala 102:21]
-    node _T_1106 = shr(_T_1103, 4) @[Bitwise.scala 103:21]
-    node _T_1107 = and(_T_1106, _T_1105) @[Bitwise.scala 103:31]
-    node _T_1108 = bits(_T_1103, 3, 0) @[Bitwise.scala 103:46]
-    node _T_1109 = shl(_T_1108, 4) @[Bitwise.scala 103:65]
-    node _T_1110 = not(_T_1105) @[Bitwise.scala 103:77]
-    node _T_1111 = and(_T_1109, _T_1110) @[Bitwise.scala 103:75]
-    node _T_1112 = or(_T_1107, _T_1111) @[Bitwise.scala 103:39]
-    node _T_1113 = bits(_T_1105, 5, 0) @[Bitwise.scala 102:28]
-    node _T_1114 = shl(_T_1113, 2) @[Bitwise.scala 102:47]
-    node _T_1115 = xor(_T_1105, _T_1114) @[Bitwise.scala 102:21]
-    node _T_1116 = shr(_T_1112, 2) @[Bitwise.scala 103:21]
-    node _T_1117 = and(_T_1116, _T_1115) @[Bitwise.scala 103:31]
-    node _T_1118 = bits(_T_1112, 5, 0) @[Bitwise.scala 103:46]
-    node _T_1119 = shl(_T_1118, 2) @[Bitwise.scala 103:65]
-    node _T_1120 = not(_T_1115) @[Bitwise.scala 103:77]
-    node _T_1121 = and(_T_1119, _T_1120) @[Bitwise.scala 103:75]
-    node _T_1122 = or(_T_1117, _T_1121) @[Bitwise.scala 103:39]
-    node _T_1123 = bits(_T_1115, 6, 0) @[Bitwise.scala 102:28]
-    node _T_1124 = shl(_T_1123, 1) @[Bitwise.scala 102:47]
-    node _T_1125 = xor(_T_1115, _T_1124) @[Bitwise.scala 102:21]
-    node _T_1126 = shr(_T_1122, 1) @[Bitwise.scala 103:21]
-    node _T_1127 = and(_T_1126, _T_1125) @[Bitwise.scala 103:31]
-    node _T_1128 = bits(_T_1122, 6, 0) @[Bitwise.scala 103:46]
-    node _T_1129 = shl(_T_1128, 1) @[Bitwise.scala 103:65]
-    node _T_1130 = not(_T_1125) @[Bitwise.scala 103:77]
-    node _T_1131 = and(_T_1129, _T_1130) @[Bitwise.scala 103:75]
-    node _T_1132 = or(_T_1127, _T_1131) @[Bitwise.scala 103:39]
-    node _T_1133 = bits(store_byteen_ext_m, 3, 3) @[lsu_dccm_ctl.scala 261:139]
-    node _T_1134 = bits(_T_1133, 0, 0) @[lsu_dccm_ctl.scala 261:143]
-    node _T_1135 = bits(store_data_lo_m, 31, 24) @[lsu_dccm_ctl.scala 261:167]
-    node _T_1136 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_m_lo) @[lsu_dccm_ctl.scala 261:211]
-    node _T_1137 = bits(_T_1136, 0, 0) @[lsu_dccm_ctl.scala 261:237]
-    node _T_1138 = bits(io.stbuf_data_any, 31, 24) @[lsu_dccm_ctl.scala 261:262]
-    node _T_1139 = bits(io.sec_data_lo_m, 31, 24) @[lsu_dccm_ctl.scala 261:292]
-    node _T_1140 = mux(_T_1137, _T_1138, _T_1139) @[lsu_dccm_ctl.scala 261:185]
-    node _T_1141 = mux(_T_1134, _T_1135, _T_1140) @[lsu_dccm_ctl.scala 261:120]
-    node _T_1142 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
-    node _T_1143 = xor(UInt<8>("h0ff"), _T_1142) @[Bitwise.scala 102:21]
-    node _T_1144 = shr(_T_1141, 4) @[Bitwise.scala 103:21]
-    node _T_1145 = and(_T_1144, _T_1143) @[Bitwise.scala 103:31]
-    node _T_1146 = bits(_T_1141, 3, 0) @[Bitwise.scala 103:46]
-    node _T_1147 = shl(_T_1146, 4) @[Bitwise.scala 103:65]
-    node _T_1148 = not(_T_1143) @[Bitwise.scala 103:77]
-    node _T_1149 = and(_T_1147, _T_1148) @[Bitwise.scala 103:75]
-    node _T_1150 = or(_T_1145, _T_1149) @[Bitwise.scala 103:39]
-    node _T_1151 = bits(_T_1143, 5, 0) @[Bitwise.scala 102:28]
-    node _T_1152 = shl(_T_1151, 2) @[Bitwise.scala 102:47]
-    node _T_1153 = xor(_T_1143, _T_1152) @[Bitwise.scala 102:21]
-    node _T_1154 = shr(_T_1150, 2) @[Bitwise.scala 103:21]
-    node _T_1155 = and(_T_1154, _T_1153) @[Bitwise.scala 103:31]
-    node _T_1156 = bits(_T_1150, 5, 0) @[Bitwise.scala 103:46]
-    node _T_1157 = shl(_T_1156, 2) @[Bitwise.scala 103:65]
-    node _T_1158 = not(_T_1153) @[Bitwise.scala 103:77]
-    node _T_1159 = and(_T_1157, _T_1158) @[Bitwise.scala 103:75]
-    node _T_1160 = or(_T_1155, _T_1159) @[Bitwise.scala 103:39]
-    node _T_1161 = bits(_T_1153, 6, 0) @[Bitwise.scala 102:28]
-    node _T_1162 = shl(_T_1161, 1) @[Bitwise.scala 102:47]
-    node _T_1163 = xor(_T_1153, _T_1162) @[Bitwise.scala 102:21]
-    node _T_1164 = shr(_T_1160, 1) @[Bitwise.scala 103:21]
-    node _T_1165 = and(_T_1164, _T_1163) @[Bitwise.scala 103:31]
-    node _T_1166 = bits(_T_1160, 6, 0) @[Bitwise.scala 103:46]
-    node _T_1167 = shl(_T_1166, 1) @[Bitwise.scala 103:65]
-    node _T_1168 = not(_T_1163) @[Bitwise.scala 103:77]
-    node _T_1169 = and(_T_1167, _T_1168) @[Bitwise.scala 103:75]
-    node _T_1170 = or(_T_1165, _T_1169) @[Bitwise.scala 103:39]
-    wire _T_1171 : UInt<8>[4] @[lsu_dccm_ctl.scala 261:104]
-    _T_1171[0] <= _T_1056 @[lsu_dccm_ctl.scala 261:104]
-    _T_1171[1] <= _T_1094 @[lsu_dccm_ctl.scala 261:104]
-    _T_1171[2] <= _T_1132 @[lsu_dccm_ctl.scala 261:104]
-    _T_1171[3] <= _T_1170 @[lsu_dccm_ctl.scala 261:104]
-    node _T_1172 = cat(_T_1171[2], _T_1171[3]) @[Cat.scala 29:58]
-    node _T_1173 = cat(_T_1171[0], _T_1171[1]) @[Cat.scala 29:58]
-    node _T_1174 = cat(_T_1173, _T_1172) @[Cat.scala 29:58]
-    node _T_1175 = shl(UInt<16>("h0ffff"), 16) @[Bitwise.scala 102:47]
-    node _T_1176 = xor(UInt<32>("h0ffffffff"), _T_1175) @[Bitwise.scala 102:21]
-    node _T_1177 = shr(_T_1174, 16) @[Bitwise.scala 103:21]
-    node _T_1178 = and(_T_1177, _T_1176) @[Bitwise.scala 103:31]
-    node _T_1179 = bits(_T_1174, 15, 0) @[Bitwise.scala 103:46]
-    node _T_1180 = shl(_T_1179, 16) @[Bitwise.scala 103:65]
-    node _T_1181 = not(_T_1176) @[Bitwise.scala 103:77]
-    node _T_1182 = and(_T_1180, _T_1181) @[Bitwise.scala 103:75]
-    node _T_1183 = or(_T_1178, _T_1182) @[Bitwise.scala 103:39]
-    node _T_1184 = bits(_T_1176, 23, 0) @[Bitwise.scala 102:28]
-    node _T_1185 = shl(_T_1184, 8) @[Bitwise.scala 102:47]
-    node _T_1186 = xor(_T_1176, _T_1185) @[Bitwise.scala 102:21]
-    node _T_1187 = shr(_T_1183, 8) @[Bitwise.scala 103:21]
-    node _T_1188 = and(_T_1187, _T_1186) @[Bitwise.scala 103:31]
-    node _T_1189 = bits(_T_1183, 23, 0) @[Bitwise.scala 103:46]
-    node _T_1190 = shl(_T_1189, 8) @[Bitwise.scala 103:65]
-    node _T_1191 = not(_T_1186) @[Bitwise.scala 103:77]
-    node _T_1192 = and(_T_1190, _T_1191) @[Bitwise.scala 103:75]
-    node _T_1193 = or(_T_1188, _T_1192) @[Bitwise.scala 103:39]
-    node _T_1194 = bits(_T_1186, 27, 0) @[Bitwise.scala 102:28]
-    node _T_1195 = shl(_T_1194, 4) @[Bitwise.scala 102:47]
-    node _T_1196 = xor(_T_1186, _T_1195) @[Bitwise.scala 102:21]
-    node _T_1197 = shr(_T_1193, 4) @[Bitwise.scala 103:21]
-    node _T_1198 = and(_T_1197, _T_1196) @[Bitwise.scala 103:31]
-    node _T_1199 = bits(_T_1193, 27, 0) @[Bitwise.scala 103:46]
-    node _T_1200 = shl(_T_1199, 4) @[Bitwise.scala 103:65]
-    node _T_1201 = not(_T_1196) @[Bitwise.scala 103:77]
-    node _T_1202 = and(_T_1200, _T_1201) @[Bitwise.scala 103:75]
-    node _T_1203 = or(_T_1198, _T_1202) @[Bitwise.scala 103:39]
-    node _T_1204 = bits(_T_1196, 29, 0) @[Bitwise.scala 102:28]
-    node _T_1205 = shl(_T_1204, 2) @[Bitwise.scala 102:47]
-    node _T_1206 = xor(_T_1196, _T_1205) @[Bitwise.scala 102:21]
-    node _T_1207 = shr(_T_1203, 2) @[Bitwise.scala 103:21]
-    node _T_1208 = and(_T_1207, _T_1206) @[Bitwise.scala 103:31]
-    node _T_1209 = bits(_T_1203, 29, 0) @[Bitwise.scala 103:46]
-    node _T_1210 = shl(_T_1209, 2) @[Bitwise.scala 103:65]
-    node _T_1211 = not(_T_1206) @[Bitwise.scala 103:77]
-    node _T_1212 = and(_T_1210, _T_1211) @[Bitwise.scala 103:75]
-    node _T_1213 = or(_T_1208, _T_1212) @[Bitwise.scala 103:39]
-    node _T_1214 = bits(_T_1206, 30, 0) @[Bitwise.scala 102:28]
-    node _T_1215 = shl(_T_1214, 1) @[Bitwise.scala 102:47]
-    node _T_1216 = xor(_T_1206, _T_1215) @[Bitwise.scala 102:21]
-    node _T_1217 = shr(_T_1213, 1) @[Bitwise.scala 103:21]
-    node _T_1218 = and(_T_1217, _T_1216) @[Bitwise.scala 103:31]
-    node _T_1219 = bits(_T_1213, 30, 0) @[Bitwise.scala 103:46]
-    node _T_1220 = shl(_T_1219, 1) @[Bitwise.scala 103:65]
-    node _T_1221 = not(_T_1216) @[Bitwise.scala 103:77]
-    node _T_1222 = and(_T_1220, _T_1221) @[Bitwise.scala 103:75]
-    node _T_1223 = or(_T_1218, _T_1222) @[Bitwise.scala 103:39]
-    reg _T_1224 : UInt, io.lsu_store_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_dccm_ctl.scala 261:72]
-    _T_1224 <= _T_1223 @[lsu_dccm_ctl.scala 261:72]
-    io.store_data_lo_r <= _T_1224 @[lsu_dccm_ctl.scala 261:29]
-    node _T_1225 = bits(store_byteen_ext_m, 4, 4) @[lsu_dccm_ctl.scala 262:105]
-    node _T_1226 = bits(_T_1225, 0, 0) @[lsu_dccm_ctl.scala 262:111]
-    node _T_1227 = bits(store_data_hi_m, 7, 0) @[lsu_dccm_ctl.scala 262:133]
-    node _T_1228 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_m_hi) @[lsu_dccm_ctl.scala 262:177]
-    node _T_1229 = bits(_T_1228, 0, 0) @[lsu_dccm_ctl.scala 262:203]
-    node _T_1230 = bits(io.stbuf_data_any, 7, 0) @[lsu_dccm_ctl.scala 262:228]
-    node _T_1231 = bits(io.sec_data_hi_m, 7, 0) @[lsu_dccm_ctl.scala 262:258]
-    node _T_1232 = mux(_T_1229, _T_1230, _T_1231) @[lsu_dccm_ctl.scala 262:151]
-    node _T_1233 = mux(_T_1226, _T_1227, _T_1232) @[lsu_dccm_ctl.scala 262:86]
-    node _T_1234 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
-    node _T_1235 = xor(UInt<8>("h0ff"), _T_1234) @[Bitwise.scala 102:21]
-    node _T_1236 = shr(_T_1233, 4) @[Bitwise.scala 103:21]
-    node _T_1237 = and(_T_1236, _T_1235) @[Bitwise.scala 103:31]
-    node _T_1238 = bits(_T_1233, 3, 0) @[Bitwise.scala 103:46]
-    node _T_1239 = shl(_T_1238, 4) @[Bitwise.scala 103:65]
-    node _T_1240 = not(_T_1235) @[Bitwise.scala 103:77]
-    node _T_1241 = and(_T_1239, _T_1240) @[Bitwise.scala 103:75]
-    node _T_1242 = or(_T_1237, _T_1241) @[Bitwise.scala 103:39]
-    node _T_1243 = bits(_T_1235, 5, 0) @[Bitwise.scala 102:28]
-    node _T_1244 = shl(_T_1243, 2) @[Bitwise.scala 102:47]
-    node _T_1245 = xor(_T_1235, _T_1244) @[Bitwise.scala 102:21]
-    node _T_1246 = shr(_T_1242, 2) @[Bitwise.scala 103:21]
-    node _T_1247 = and(_T_1246, _T_1245) @[Bitwise.scala 103:31]
-    node _T_1248 = bits(_T_1242, 5, 0) @[Bitwise.scala 103:46]
-    node _T_1249 = shl(_T_1248, 2) @[Bitwise.scala 103:65]
-    node _T_1250 = not(_T_1245) @[Bitwise.scala 103:77]
-    node _T_1251 = and(_T_1249, _T_1250) @[Bitwise.scala 103:75]
-    node _T_1252 = or(_T_1247, _T_1251) @[Bitwise.scala 103:39]
-    node _T_1253 = bits(_T_1245, 6, 0) @[Bitwise.scala 102:28]
-    node _T_1254 = shl(_T_1253, 1) @[Bitwise.scala 102:47]
-    node _T_1255 = xor(_T_1245, _T_1254) @[Bitwise.scala 102:21]
-    node _T_1256 = shr(_T_1252, 1) @[Bitwise.scala 103:21]
-    node _T_1257 = and(_T_1256, _T_1255) @[Bitwise.scala 103:31]
-    node _T_1258 = bits(_T_1252, 6, 0) @[Bitwise.scala 103:46]
-    node _T_1259 = shl(_T_1258, 1) @[Bitwise.scala 103:65]
-    node _T_1260 = not(_T_1255) @[Bitwise.scala 103:77]
-    node _T_1261 = and(_T_1259, _T_1260) @[Bitwise.scala 103:75]
-    node _T_1262 = or(_T_1257, _T_1261) @[Bitwise.scala 103:39]
-    node _T_1263 = bits(store_byteen_ext_m, 5, 5) @[lsu_dccm_ctl.scala 262:105]
-    node _T_1264 = bits(_T_1263, 0, 0) @[lsu_dccm_ctl.scala 262:111]
-    node _T_1265 = bits(store_data_hi_m, 15, 8) @[lsu_dccm_ctl.scala 262:133]
-    node _T_1266 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_m_hi) @[lsu_dccm_ctl.scala 262:177]
-    node _T_1267 = bits(_T_1266, 0, 0) @[lsu_dccm_ctl.scala 262:203]
-    node _T_1268 = bits(io.stbuf_data_any, 15, 8) @[lsu_dccm_ctl.scala 262:228]
-    node _T_1269 = bits(io.sec_data_hi_m, 15, 8) @[lsu_dccm_ctl.scala 262:258]
-    node _T_1270 = mux(_T_1267, _T_1268, _T_1269) @[lsu_dccm_ctl.scala 262:151]
-    node _T_1271 = mux(_T_1264, _T_1265, _T_1270) @[lsu_dccm_ctl.scala 262:86]
-    node _T_1272 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
-    node _T_1273 = xor(UInt<8>("h0ff"), _T_1272) @[Bitwise.scala 102:21]
-    node _T_1274 = shr(_T_1271, 4) @[Bitwise.scala 103:21]
-    node _T_1275 = and(_T_1274, _T_1273) @[Bitwise.scala 103:31]
-    node _T_1276 = bits(_T_1271, 3, 0) @[Bitwise.scala 103:46]
-    node _T_1277 = shl(_T_1276, 4) @[Bitwise.scala 103:65]
-    node _T_1278 = not(_T_1273) @[Bitwise.scala 103:77]
-    node _T_1279 = and(_T_1277, _T_1278) @[Bitwise.scala 103:75]
-    node _T_1280 = or(_T_1275, _T_1279) @[Bitwise.scala 103:39]
-    node _T_1281 = bits(_T_1273, 5, 0) @[Bitwise.scala 102:28]
-    node _T_1282 = shl(_T_1281, 2) @[Bitwise.scala 102:47]
-    node _T_1283 = xor(_T_1273, _T_1282) @[Bitwise.scala 102:21]
-    node _T_1284 = shr(_T_1280, 2) @[Bitwise.scala 103:21]
-    node _T_1285 = and(_T_1284, _T_1283) @[Bitwise.scala 103:31]
-    node _T_1286 = bits(_T_1280, 5, 0) @[Bitwise.scala 103:46]
-    node _T_1287 = shl(_T_1286, 2) @[Bitwise.scala 103:65]
-    node _T_1288 = not(_T_1283) @[Bitwise.scala 103:77]
-    node _T_1289 = and(_T_1287, _T_1288) @[Bitwise.scala 103:75]
-    node _T_1290 = or(_T_1285, _T_1289) @[Bitwise.scala 103:39]
-    node _T_1291 = bits(_T_1283, 6, 0) @[Bitwise.scala 102:28]
-    node _T_1292 = shl(_T_1291, 1) @[Bitwise.scala 102:47]
-    node _T_1293 = xor(_T_1283, _T_1292) @[Bitwise.scala 102:21]
-    node _T_1294 = shr(_T_1290, 1) @[Bitwise.scala 103:21]
-    node _T_1295 = and(_T_1294, _T_1293) @[Bitwise.scala 103:31]
-    node _T_1296 = bits(_T_1290, 6, 0) @[Bitwise.scala 103:46]
-    node _T_1297 = shl(_T_1296, 1) @[Bitwise.scala 103:65]
-    node _T_1298 = not(_T_1293) @[Bitwise.scala 103:77]
-    node _T_1299 = and(_T_1297, _T_1298) @[Bitwise.scala 103:75]
-    node _T_1300 = or(_T_1295, _T_1299) @[Bitwise.scala 103:39]
-    node _T_1301 = bits(store_byteen_ext_m, 6, 6) @[lsu_dccm_ctl.scala 262:105]
-    node _T_1302 = bits(_T_1301, 0, 0) @[lsu_dccm_ctl.scala 262:111]
-    node _T_1303 = bits(store_data_hi_m, 23, 16) @[lsu_dccm_ctl.scala 262:133]
-    node _T_1304 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_m_hi) @[lsu_dccm_ctl.scala 262:177]
-    node _T_1305 = bits(_T_1304, 0, 0) @[lsu_dccm_ctl.scala 262:203]
-    node _T_1306 = bits(io.stbuf_data_any, 23, 16) @[lsu_dccm_ctl.scala 262:228]
-    node _T_1307 = bits(io.sec_data_hi_m, 23, 16) @[lsu_dccm_ctl.scala 262:258]
-    node _T_1308 = mux(_T_1305, _T_1306, _T_1307) @[lsu_dccm_ctl.scala 262:151]
-    node _T_1309 = mux(_T_1302, _T_1303, _T_1308) @[lsu_dccm_ctl.scala 262:86]
-    node _T_1310 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
-    node _T_1311 = xor(UInt<8>("h0ff"), _T_1310) @[Bitwise.scala 102:21]
-    node _T_1312 = shr(_T_1309, 4) @[Bitwise.scala 103:21]
-    node _T_1313 = and(_T_1312, _T_1311) @[Bitwise.scala 103:31]
-    node _T_1314 = bits(_T_1309, 3, 0) @[Bitwise.scala 103:46]
-    node _T_1315 = shl(_T_1314, 4) @[Bitwise.scala 103:65]
-    node _T_1316 = not(_T_1311) @[Bitwise.scala 103:77]
-    node _T_1317 = and(_T_1315, _T_1316) @[Bitwise.scala 103:75]
-    node _T_1318 = or(_T_1313, _T_1317) @[Bitwise.scala 103:39]
-    node _T_1319 = bits(_T_1311, 5, 0) @[Bitwise.scala 102:28]
-    node _T_1320 = shl(_T_1319, 2) @[Bitwise.scala 102:47]
-    node _T_1321 = xor(_T_1311, _T_1320) @[Bitwise.scala 102:21]
-    node _T_1322 = shr(_T_1318, 2) @[Bitwise.scala 103:21]
-    node _T_1323 = and(_T_1322, _T_1321) @[Bitwise.scala 103:31]
-    node _T_1324 = bits(_T_1318, 5, 0) @[Bitwise.scala 103:46]
-    node _T_1325 = shl(_T_1324, 2) @[Bitwise.scala 103:65]
-    node _T_1326 = not(_T_1321) @[Bitwise.scala 103:77]
-    node _T_1327 = and(_T_1325, _T_1326) @[Bitwise.scala 103:75]
-    node _T_1328 = or(_T_1323, _T_1327) @[Bitwise.scala 103:39]
-    node _T_1329 = bits(_T_1321, 6, 0) @[Bitwise.scala 102:28]
-    node _T_1330 = shl(_T_1329, 1) @[Bitwise.scala 102:47]
-    node _T_1331 = xor(_T_1321, _T_1330) @[Bitwise.scala 102:21]
-    node _T_1332 = shr(_T_1328, 1) @[Bitwise.scala 103:21]
-    node _T_1333 = and(_T_1332, _T_1331) @[Bitwise.scala 103:31]
-    node _T_1334 = bits(_T_1328, 6, 0) @[Bitwise.scala 103:46]
-    node _T_1335 = shl(_T_1334, 1) @[Bitwise.scala 103:65]
-    node _T_1336 = not(_T_1331) @[Bitwise.scala 103:77]
-    node _T_1337 = and(_T_1335, _T_1336) @[Bitwise.scala 103:75]
-    node _T_1338 = or(_T_1333, _T_1337) @[Bitwise.scala 103:39]
-    node _T_1339 = bits(store_byteen_ext_m, 7, 7) @[lsu_dccm_ctl.scala 262:105]
-    node _T_1340 = bits(_T_1339, 0, 0) @[lsu_dccm_ctl.scala 262:111]
-    node _T_1341 = bits(store_data_hi_m, 31, 24) @[lsu_dccm_ctl.scala 262:133]
-    node _T_1342 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_m_hi) @[lsu_dccm_ctl.scala 262:177]
-    node _T_1343 = bits(_T_1342, 0, 0) @[lsu_dccm_ctl.scala 262:203]
-    node _T_1344 = bits(io.stbuf_data_any, 31, 24) @[lsu_dccm_ctl.scala 262:228]
-    node _T_1345 = bits(io.sec_data_hi_m, 31, 24) @[lsu_dccm_ctl.scala 262:258]
-    node _T_1346 = mux(_T_1343, _T_1344, _T_1345) @[lsu_dccm_ctl.scala 262:151]
-    node _T_1347 = mux(_T_1340, _T_1341, _T_1346) @[lsu_dccm_ctl.scala 262:86]
-    node _T_1348 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
-    node _T_1349 = xor(UInt<8>("h0ff"), _T_1348) @[Bitwise.scala 102:21]
-    node _T_1350 = shr(_T_1347, 4) @[Bitwise.scala 103:21]
-    node _T_1351 = and(_T_1350, _T_1349) @[Bitwise.scala 103:31]
-    node _T_1352 = bits(_T_1347, 3, 0) @[Bitwise.scala 103:46]
-    node _T_1353 = shl(_T_1352, 4) @[Bitwise.scala 103:65]
-    node _T_1354 = not(_T_1349) @[Bitwise.scala 103:77]
-    node _T_1355 = and(_T_1353, _T_1354) @[Bitwise.scala 103:75]
-    node _T_1356 = or(_T_1351, _T_1355) @[Bitwise.scala 103:39]
-    node _T_1357 = bits(_T_1349, 5, 0) @[Bitwise.scala 102:28]
-    node _T_1358 = shl(_T_1357, 2) @[Bitwise.scala 102:47]
-    node _T_1359 = xor(_T_1349, _T_1358) @[Bitwise.scala 102:21]
-    node _T_1360 = shr(_T_1356, 2) @[Bitwise.scala 103:21]
-    node _T_1361 = and(_T_1360, _T_1359) @[Bitwise.scala 103:31]
-    node _T_1362 = bits(_T_1356, 5, 0) @[Bitwise.scala 103:46]
-    node _T_1363 = shl(_T_1362, 2) @[Bitwise.scala 103:65]
-    node _T_1364 = not(_T_1359) @[Bitwise.scala 103:77]
-    node _T_1365 = and(_T_1363, _T_1364) @[Bitwise.scala 103:75]
-    node _T_1366 = or(_T_1361, _T_1365) @[Bitwise.scala 103:39]
-    node _T_1367 = bits(_T_1359, 6, 0) @[Bitwise.scala 102:28]
-    node _T_1368 = shl(_T_1367, 1) @[Bitwise.scala 102:47]
-    node _T_1369 = xor(_T_1359, _T_1368) @[Bitwise.scala 102:21]
-    node _T_1370 = shr(_T_1366, 1) @[Bitwise.scala 103:21]
-    node _T_1371 = and(_T_1370, _T_1369) @[Bitwise.scala 103:31]
-    node _T_1372 = bits(_T_1366, 6, 0) @[Bitwise.scala 103:46]
-    node _T_1373 = shl(_T_1372, 1) @[Bitwise.scala 103:65]
-    node _T_1374 = not(_T_1369) @[Bitwise.scala 103:77]
-    node _T_1375 = and(_T_1373, _T_1374) @[Bitwise.scala 103:75]
-    node _T_1376 = or(_T_1371, _T_1375) @[Bitwise.scala 103:39]
-    wire _T_1377 : UInt<8>[4] @[lsu_dccm_ctl.scala 262:70]
-    _T_1377[0] <= _T_1262 @[lsu_dccm_ctl.scala 262:70]
-    _T_1377[1] <= _T_1300 @[lsu_dccm_ctl.scala 262:70]
-    _T_1377[2] <= _T_1338 @[lsu_dccm_ctl.scala 262:70]
-    _T_1377[3] <= _T_1376 @[lsu_dccm_ctl.scala 262:70]
-    node _T_1378 = cat(_T_1377[2], _T_1377[3]) @[Cat.scala 29:58]
-    node _T_1379 = cat(_T_1377[0], _T_1377[1]) @[Cat.scala 29:58]
-    node _T_1380 = cat(_T_1379, _T_1378) @[Cat.scala 29:58]
-    node _T_1381 = shl(UInt<16>("h0ffff"), 16) @[Bitwise.scala 102:47]
-    node _T_1382 = xor(UInt<32>("h0ffffffff"), _T_1381) @[Bitwise.scala 102:21]
-    node _T_1383 = shr(_T_1380, 16) @[Bitwise.scala 103:21]
-    node _T_1384 = and(_T_1383, _T_1382) @[Bitwise.scala 103:31]
-    node _T_1385 = bits(_T_1380, 15, 0) @[Bitwise.scala 103:46]
-    node _T_1386 = shl(_T_1385, 16) @[Bitwise.scala 103:65]
-    node _T_1387 = not(_T_1382) @[Bitwise.scala 103:77]
-    node _T_1388 = and(_T_1386, _T_1387) @[Bitwise.scala 103:75]
-    node _T_1389 = or(_T_1384, _T_1388) @[Bitwise.scala 103:39]
-    node _T_1390 = bits(_T_1382, 23, 0) @[Bitwise.scala 102:28]
-    node _T_1391 = shl(_T_1390, 8) @[Bitwise.scala 102:47]
-    node _T_1392 = xor(_T_1382, _T_1391) @[Bitwise.scala 102:21]
-    node _T_1393 = shr(_T_1389, 8) @[Bitwise.scala 103:21]
-    node _T_1394 = and(_T_1393, _T_1392) @[Bitwise.scala 103:31]
-    node _T_1395 = bits(_T_1389, 23, 0) @[Bitwise.scala 103:46]
-    node _T_1396 = shl(_T_1395, 8) @[Bitwise.scala 103:65]
-    node _T_1397 = not(_T_1392) @[Bitwise.scala 103:77]
-    node _T_1398 = and(_T_1396, _T_1397) @[Bitwise.scala 103:75]
-    node _T_1399 = or(_T_1394, _T_1398) @[Bitwise.scala 103:39]
-    node _T_1400 = bits(_T_1392, 27, 0) @[Bitwise.scala 102:28]
-    node _T_1401 = shl(_T_1400, 4) @[Bitwise.scala 102:47]
-    node _T_1402 = xor(_T_1392, _T_1401) @[Bitwise.scala 102:21]
-    node _T_1403 = shr(_T_1399, 4) @[Bitwise.scala 103:21]
-    node _T_1404 = and(_T_1403, _T_1402) @[Bitwise.scala 103:31]
-    node _T_1405 = bits(_T_1399, 27, 0) @[Bitwise.scala 103:46]
-    node _T_1406 = shl(_T_1405, 4) @[Bitwise.scala 103:65]
-    node _T_1407 = not(_T_1402) @[Bitwise.scala 103:77]
-    node _T_1408 = and(_T_1406, _T_1407) @[Bitwise.scala 103:75]
-    node _T_1409 = or(_T_1404, _T_1408) @[Bitwise.scala 103:39]
-    node _T_1410 = bits(_T_1402, 29, 0) @[Bitwise.scala 102:28]
-    node _T_1411 = shl(_T_1410, 2) @[Bitwise.scala 102:47]
-    node _T_1412 = xor(_T_1402, _T_1411) @[Bitwise.scala 102:21]
-    node _T_1413 = shr(_T_1409, 2) @[Bitwise.scala 103:21]
-    node _T_1414 = and(_T_1413, _T_1412) @[Bitwise.scala 103:31]
-    node _T_1415 = bits(_T_1409, 29, 0) @[Bitwise.scala 103:46]
-    node _T_1416 = shl(_T_1415, 2) @[Bitwise.scala 103:65]
-    node _T_1417 = not(_T_1412) @[Bitwise.scala 103:77]
-    node _T_1418 = and(_T_1416, _T_1417) @[Bitwise.scala 103:75]
-    node _T_1419 = or(_T_1414, _T_1418) @[Bitwise.scala 103:39]
-    node _T_1420 = bits(_T_1412, 30, 0) @[Bitwise.scala 102:28]
-    node _T_1421 = shl(_T_1420, 1) @[Bitwise.scala 102:47]
-    node _T_1422 = xor(_T_1412, _T_1421) @[Bitwise.scala 102:21]
-    node _T_1423 = shr(_T_1419, 1) @[Bitwise.scala 103:21]
-    node _T_1424 = and(_T_1423, _T_1422) @[Bitwise.scala 103:31]
-    node _T_1425 = bits(_T_1419, 30, 0) @[Bitwise.scala 103:46]
-    node _T_1426 = shl(_T_1425, 1) @[Bitwise.scala 103:65]
-    node _T_1427 = not(_T_1422) @[Bitwise.scala 103:77]
-    node _T_1428 = and(_T_1426, _T_1427) @[Bitwise.scala 103:75]
-    node _T_1429 = or(_T_1424, _T_1428) @[Bitwise.scala 103:39]
-    node _T_1430 = and(io.ldst_dual_m, io.lsu_pkt_m.valid) @[lsu_dccm_ctl.scala 262:295]
-    node _T_1431 = and(_T_1430, io.lsu_pkt_m.bits.store) @[lsu_dccm_ctl.scala 262:316]
-    node _T_1432 = or(_T_1431, io.clk_override) @[lsu_dccm_ctl.scala 262:343]
-    node _T_1433 = bits(_T_1432, 0, 0) @[lib.scala 8:44]
-    node _T_1434 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44]
-    inst rvclkhdr_1 of rvclkhdr_5 @[lib.scala 368:23]
-    rvclkhdr_1.clock <= clock
-    rvclkhdr_1.reset <= reset
-    rvclkhdr_1.io.clk <= clock @[lib.scala 370:18]
-    rvclkhdr_1.io.en <= _T_1433 @[lib.scala 371:17]
-    rvclkhdr_1.io.scan_mode <= _T_1434 @[lib.scala 372:24]
-    reg _T_1435 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
-    _T_1435 <= _T_1429 @[lib.scala 374:16]
-    io.store_data_hi_r <= _T_1435 @[lsu_dccm_ctl.scala 262:29]
-    node _T_1436 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_lo) @[lsu_dccm_ctl.scala 263:105]
-    node _T_1437 = bits(store_byteen_ext_r, 0, 0) @[lsu_dccm_ctl.scala 263:150]
-    node _T_1438 = eq(_T_1437, UInt<1>("h00")) @[lsu_dccm_ctl.scala 263:131]
-    node _T_1439 = and(_T_1436, _T_1438) @[lsu_dccm_ctl.scala 263:129]
-    node _T_1440 = bits(_T_1439, 0, 0) @[lsu_dccm_ctl.scala 263:155]
-    node _T_1441 = bits(io.stbuf_data_any, 7, 0) @[lsu_dccm_ctl.scala 263:179]
-    node _T_1442 = bits(io.store_data_lo_r, 7, 0) @[lsu_dccm_ctl.scala 263:211]
-    node _T_1443 = mux(_T_1440, _T_1441, _T_1442) @[lsu_dccm_ctl.scala 263:79]
-    node _T_1444 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
-    node _T_1445 = xor(UInt<8>("h0ff"), _T_1444) @[Bitwise.scala 102:21]
-    node _T_1446 = shr(_T_1443, 4) @[Bitwise.scala 103:21]
-    node _T_1447 = and(_T_1446, _T_1445) @[Bitwise.scala 103:31]
-    node _T_1448 = bits(_T_1443, 3, 0) @[Bitwise.scala 103:46]
-    node _T_1449 = shl(_T_1448, 4) @[Bitwise.scala 103:65]
-    node _T_1450 = not(_T_1445) @[Bitwise.scala 103:77]
-    node _T_1451 = and(_T_1449, _T_1450) @[Bitwise.scala 103:75]
-    node _T_1452 = or(_T_1447, _T_1451) @[Bitwise.scala 103:39]
-    node _T_1453 = bits(_T_1445, 5, 0) @[Bitwise.scala 102:28]
-    node _T_1454 = shl(_T_1453, 2) @[Bitwise.scala 102:47]
-    node _T_1455 = xor(_T_1445, _T_1454) @[Bitwise.scala 102:21]
-    node _T_1456 = shr(_T_1452, 2) @[Bitwise.scala 103:21]
-    node _T_1457 = and(_T_1456, _T_1455) @[Bitwise.scala 103:31]
-    node _T_1458 = bits(_T_1452, 5, 0) @[Bitwise.scala 103:46]
-    node _T_1459 = shl(_T_1458, 2) @[Bitwise.scala 103:65]
-    node _T_1460 = not(_T_1455) @[Bitwise.scala 103:77]
-    node _T_1461 = and(_T_1459, _T_1460) @[Bitwise.scala 103:75]
-    node _T_1462 = or(_T_1457, _T_1461) @[Bitwise.scala 103:39]
-    node _T_1463 = bits(_T_1455, 6, 0) @[Bitwise.scala 102:28]
-    node _T_1464 = shl(_T_1463, 1) @[Bitwise.scala 102:47]
-    node _T_1465 = xor(_T_1455, _T_1464) @[Bitwise.scala 102:21]
-    node _T_1466 = shr(_T_1462, 1) @[Bitwise.scala 103:21]
-    node _T_1467 = and(_T_1466, _T_1465) @[Bitwise.scala 103:31]
-    node _T_1468 = bits(_T_1462, 6, 0) @[Bitwise.scala 103:46]
-    node _T_1469 = shl(_T_1468, 1) @[Bitwise.scala 103:65]
-    node _T_1470 = not(_T_1465) @[Bitwise.scala 103:77]
-    node _T_1471 = and(_T_1469, _T_1470) @[Bitwise.scala 103:75]
-    node _T_1472 = or(_T_1467, _T_1471) @[Bitwise.scala 103:39]
-    node _T_1473 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_lo) @[lsu_dccm_ctl.scala 263:105]
-    node _T_1474 = bits(store_byteen_ext_r, 1, 1) @[lsu_dccm_ctl.scala 263:150]
-    node _T_1475 = eq(_T_1474, UInt<1>("h00")) @[lsu_dccm_ctl.scala 263:131]
-    node _T_1476 = and(_T_1473, _T_1475) @[lsu_dccm_ctl.scala 263:129]
-    node _T_1477 = bits(_T_1476, 0, 0) @[lsu_dccm_ctl.scala 263:155]
-    node _T_1478 = bits(io.stbuf_data_any, 15, 8) @[lsu_dccm_ctl.scala 263:179]
-    node _T_1479 = bits(io.store_data_lo_r, 15, 8) @[lsu_dccm_ctl.scala 263:211]
-    node _T_1480 = mux(_T_1477, _T_1478, _T_1479) @[lsu_dccm_ctl.scala 263:79]
-    node _T_1481 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
-    node _T_1482 = xor(UInt<8>("h0ff"), _T_1481) @[Bitwise.scala 102:21]
-    node _T_1483 = shr(_T_1480, 4) @[Bitwise.scala 103:21]
-    node _T_1484 = and(_T_1483, _T_1482) @[Bitwise.scala 103:31]
-    node _T_1485 = bits(_T_1480, 3, 0) @[Bitwise.scala 103:46]
-    node _T_1486 = shl(_T_1485, 4) @[Bitwise.scala 103:65]
-    node _T_1487 = not(_T_1482) @[Bitwise.scala 103:77]
-    node _T_1488 = and(_T_1486, _T_1487) @[Bitwise.scala 103:75]
-    node _T_1489 = or(_T_1484, _T_1488) @[Bitwise.scala 103:39]
-    node _T_1490 = bits(_T_1482, 5, 0) @[Bitwise.scala 102:28]
-    node _T_1491 = shl(_T_1490, 2) @[Bitwise.scala 102:47]
-    node _T_1492 = xor(_T_1482, _T_1491) @[Bitwise.scala 102:21]
-    node _T_1493 = shr(_T_1489, 2) @[Bitwise.scala 103:21]
-    node _T_1494 = and(_T_1493, _T_1492) @[Bitwise.scala 103:31]
-    node _T_1495 = bits(_T_1489, 5, 0) @[Bitwise.scala 103:46]
-    node _T_1496 = shl(_T_1495, 2) @[Bitwise.scala 103:65]
-    node _T_1497 = not(_T_1492) @[Bitwise.scala 103:77]
-    node _T_1498 = and(_T_1496, _T_1497) @[Bitwise.scala 103:75]
-    node _T_1499 = or(_T_1494, _T_1498) @[Bitwise.scala 103:39]
-    node _T_1500 = bits(_T_1492, 6, 0) @[Bitwise.scala 102:28]
-    node _T_1501 = shl(_T_1500, 1) @[Bitwise.scala 102:47]
-    node _T_1502 = xor(_T_1492, _T_1501) @[Bitwise.scala 102:21]
-    node _T_1503 = shr(_T_1499, 1) @[Bitwise.scala 103:21]
-    node _T_1504 = and(_T_1503, _T_1502) @[Bitwise.scala 103:31]
-    node _T_1505 = bits(_T_1499, 6, 0) @[Bitwise.scala 103:46]
-    node _T_1506 = shl(_T_1505, 1) @[Bitwise.scala 103:65]
-    node _T_1507 = not(_T_1502) @[Bitwise.scala 103:77]
-    node _T_1508 = and(_T_1506, _T_1507) @[Bitwise.scala 103:75]
-    node _T_1509 = or(_T_1504, _T_1508) @[Bitwise.scala 103:39]
-    node _T_1510 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_lo) @[lsu_dccm_ctl.scala 263:105]
-    node _T_1511 = bits(store_byteen_ext_r, 2, 2) @[lsu_dccm_ctl.scala 263:150]
-    node _T_1512 = eq(_T_1511, UInt<1>("h00")) @[lsu_dccm_ctl.scala 263:131]
-    node _T_1513 = and(_T_1510, _T_1512) @[lsu_dccm_ctl.scala 263:129]
-    node _T_1514 = bits(_T_1513, 0, 0) @[lsu_dccm_ctl.scala 263:155]
-    node _T_1515 = bits(io.stbuf_data_any, 23, 16) @[lsu_dccm_ctl.scala 263:179]
-    node _T_1516 = bits(io.store_data_lo_r, 23, 16) @[lsu_dccm_ctl.scala 263:211]
-    node _T_1517 = mux(_T_1514, _T_1515, _T_1516) @[lsu_dccm_ctl.scala 263:79]
-    node _T_1518 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
-    node _T_1519 = xor(UInt<8>("h0ff"), _T_1518) @[Bitwise.scala 102:21]
-    node _T_1520 = shr(_T_1517, 4) @[Bitwise.scala 103:21]
-    node _T_1521 = and(_T_1520, _T_1519) @[Bitwise.scala 103:31]
-    node _T_1522 = bits(_T_1517, 3, 0) @[Bitwise.scala 103:46]
-    node _T_1523 = shl(_T_1522, 4) @[Bitwise.scala 103:65]
-    node _T_1524 = not(_T_1519) @[Bitwise.scala 103:77]
-    node _T_1525 = and(_T_1523, _T_1524) @[Bitwise.scala 103:75]
-    node _T_1526 = or(_T_1521, _T_1525) @[Bitwise.scala 103:39]
-    node _T_1527 = bits(_T_1519, 5, 0) @[Bitwise.scala 102:28]
-    node _T_1528 = shl(_T_1527, 2) @[Bitwise.scala 102:47]
-    node _T_1529 = xor(_T_1519, _T_1528) @[Bitwise.scala 102:21]
-    node _T_1530 = shr(_T_1526, 2) @[Bitwise.scala 103:21]
-    node _T_1531 = and(_T_1530, _T_1529) @[Bitwise.scala 103:31]
-    node _T_1532 = bits(_T_1526, 5, 0) @[Bitwise.scala 103:46]
-    node _T_1533 = shl(_T_1532, 2) @[Bitwise.scala 103:65]
-    node _T_1534 = not(_T_1529) @[Bitwise.scala 103:77]
-    node _T_1535 = and(_T_1533, _T_1534) @[Bitwise.scala 103:75]
-    node _T_1536 = or(_T_1531, _T_1535) @[Bitwise.scala 103:39]
-    node _T_1537 = bits(_T_1529, 6, 0) @[Bitwise.scala 102:28]
-    node _T_1538 = shl(_T_1537, 1) @[Bitwise.scala 102:47]
-    node _T_1539 = xor(_T_1529, _T_1538) @[Bitwise.scala 102:21]
-    node _T_1540 = shr(_T_1536, 1) @[Bitwise.scala 103:21]
-    node _T_1541 = and(_T_1540, _T_1539) @[Bitwise.scala 103:31]
-    node _T_1542 = bits(_T_1536, 6, 0) @[Bitwise.scala 103:46]
-    node _T_1543 = shl(_T_1542, 1) @[Bitwise.scala 103:65]
-    node _T_1544 = not(_T_1539) @[Bitwise.scala 103:77]
-    node _T_1545 = and(_T_1543, _T_1544) @[Bitwise.scala 103:75]
-    node _T_1546 = or(_T_1541, _T_1545) @[Bitwise.scala 103:39]
-    node _T_1547 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_lo) @[lsu_dccm_ctl.scala 263:105]
-    node _T_1548 = bits(store_byteen_ext_r, 3, 3) @[lsu_dccm_ctl.scala 263:150]
-    node _T_1549 = eq(_T_1548, UInt<1>("h00")) @[lsu_dccm_ctl.scala 263:131]
-    node _T_1550 = and(_T_1547, _T_1549) @[lsu_dccm_ctl.scala 263:129]
-    node _T_1551 = bits(_T_1550, 0, 0) @[lsu_dccm_ctl.scala 263:155]
-    node _T_1552 = bits(io.stbuf_data_any, 31, 24) @[lsu_dccm_ctl.scala 263:179]
-    node _T_1553 = bits(io.store_data_lo_r, 31, 24) @[lsu_dccm_ctl.scala 263:211]
-    node _T_1554 = mux(_T_1551, _T_1552, _T_1553) @[lsu_dccm_ctl.scala 263:79]
-    node _T_1555 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
-    node _T_1556 = xor(UInt<8>("h0ff"), _T_1555) @[Bitwise.scala 102:21]
-    node _T_1557 = shr(_T_1554, 4) @[Bitwise.scala 103:21]
-    node _T_1558 = and(_T_1557, _T_1556) @[Bitwise.scala 103:31]
-    node _T_1559 = bits(_T_1554, 3, 0) @[Bitwise.scala 103:46]
-    node _T_1560 = shl(_T_1559, 4) @[Bitwise.scala 103:65]
-    node _T_1561 = not(_T_1556) @[Bitwise.scala 103:77]
-    node _T_1562 = and(_T_1560, _T_1561) @[Bitwise.scala 103:75]
-    node _T_1563 = or(_T_1558, _T_1562) @[Bitwise.scala 103:39]
-    node _T_1564 = bits(_T_1556, 5, 0) @[Bitwise.scala 102:28]
-    node _T_1565 = shl(_T_1564, 2) @[Bitwise.scala 102:47]
-    node _T_1566 = xor(_T_1556, _T_1565) @[Bitwise.scala 102:21]
-    node _T_1567 = shr(_T_1563, 2) @[Bitwise.scala 103:21]
-    node _T_1568 = and(_T_1567, _T_1566) @[Bitwise.scala 103:31]
-    node _T_1569 = bits(_T_1563, 5, 0) @[Bitwise.scala 103:46]
-    node _T_1570 = shl(_T_1569, 2) @[Bitwise.scala 103:65]
-    node _T_1571 = not(_T_1566) @[Bitwise.scala 103:77]
-    node _T_1572 = and(_T_1570, _T_1571) @[Bitwise.scala 103:75]
-    node _T_1573 = or(_T_1568, _T_1572) @[Bitwise.scala 103:39]
-    node _T_1574 = bits(_T_1566, 6, 0) @[Bitwise.scala 102:28]
-    node _T_1575 = shl(_T_1574, 1) @[Bitwise.scala 102:47]
-    node _T_1576 = xor(_T_1566, _T_1575) @[Bitwise.scala 102:21]
-    node _T_1577 = shr(_T_1573, 1) @[Bitwise.scala 103:21]
-    node _T_1578 = and(_T_1577, _T_1576) @[Bitwise.scala 103:31]
-    node _T_1579 = bits(_T_1573, 6, 0) @[Bitwise.scala 103:46]
-    node _T_1580 = shl(_T_1579, 1) @[Bitwise.scala 103:65]
-    node _T_1581 = not(_T_1576) @[Bitwise.scala 103:77]
-    node _T_1582 = and(_T_1580, _T_1581) @[Bitwise.scala 103:75]
-    node _T_1583 = or(_T_1578, _T_1582) @[Bitwise.scala 103:39]
-    wire _T_1584 : UInt<8>[4] @[lsu_dccm_ctl.scala 263:63]
-    _T_1584[0] <= _T_1472 @[lsu_dccm_ctl.scala 263:63]
-    _T_1584[1] <= _T_1509 @[lsu_dccm_ctl.scala 263:63]
-    _T_1584[2] <= _T_1546 @[lsu_dccm_ctl.scala 263:63]
-    _T_1584[3] <= _T_1583 @[lsu_dccm_ctl.scala 263:63]
-    node _T_1585 = cat(_T_1584[2], _T_1584[3]) @[Cat.scala 29:58]
-    node _T_1586 = cat(_T_1584[0], _T_1584[1]) @[Cat.scala 29:58]
-    node _T_1587 = cat(_T_1586, _T_1585) @[Cat.scala 29:58]
-    node _T_1588 = shl(UInt<16>("h0ffff"), 16) @[Bitwise.scala 102:47]
-    node _T_1589 = xor(UInt<32>("h0ffffffff"), _T_1588) @[Bitwise.scala 102:21]
-    node _T_1590 = shr(_T_1587, 16) @[Bitwise.scala 103:21]
-    node _T_1591 = and(_T_1590, _T_1589) @[Bitwise.scala 103:31]
-    node _T_1592 = bits(_T_1587, 15, 0) @[Bitwise.scala 103:46]
-    node _T_1593 = shl(_T_1592, 16) @[Bitwise.scala 103:65]
-    node _T_1594 = not(_T_1589) @[Bitwise.scala 103:77]
-    node _T_1595 = and(_T_1593, _T_1594) @[Bitwise.scala 103:75]
-    node _T_1596 = or(_T_1591, _T_1595) @[Bitwise.scala 103:39]
-    node _T_1597 = bits(_T_1589, 23, 0) @[Bitwise.scala 102:28]
-    node _T_1598 = shl(_T_1597, 8) @[Bitwise.scala 102:47]
-    node _T_1599 = xor(_T_1589, _T_1598) @[Bitwise.scala 102:21]
-    node _T_1600 = shr(_T_1596, 8) @[Bitwise.scala 103:21]
-    node _T_1601 = and(_T_1600, _T_1599) @[Bitwise.scala 103:31]
-    node _T_1602 = bits(_T_1596, 23, 0) @[Bitwise.scala 103:46]
-    node _T_1603 = shl(_T_1602, 8) @[Bitwise.scala 103:65]
-    node _T_1604 = not(_T_1599) @[Bitwise.scala 103:77]
-    node _T_1605 = and(_T_1603, _T_1604) @[Bitwise.scala 103:75]
-    node _T_1606 = or(_T_1601, _T_1605) @[Bitwise.scala 103:39]
-    node _T_1607 = bits(_T_1599, 27, 0) @[Bitwise.scala 102:28]
-    node _T_1608 = shl(_T_1607, 4) @[Bitwise.scala 102:47]
-    node _T_1609 = xor(_T_1599, _T_1608) @[Bitwise.scala 102:21]
-    node _T_1610 = shr(_T_1606, 4) @[Bitwise.scala 103:21]
-    node _T_1611 = and(_T_1610, _T_1609) @[Bitwise.scala 103:31]
-    node _T_1612 = bits(_T_1606, 27, 0) @[Bitwise.scala 103:46]
-    node _T_1613 = shl(_T_1612, 4) @[Bitwise.scala 103:65]
-    node _T_1614 = not(_T_1609) @[Bitwise.scala 103:77]
-    node _T_1615 = and(_T_1613, _T_1614) @[Bitwise.scala 103:75]
-    node _T_1616 = or(_T_1611, _T_1615) @[Bitwise.scala 103:39]
-    node _T_1617 = bits(_T_1609, 29, 0) @[Bitwise.scala 102:28]
-    node _T_1618 = shl(_T_1617, 2) @[Bitwise.scala 102:47]
-    node _T_1619 = xor(_T_1609, _T_1618) @[Bitwise.scala 102:21]
-    node _T_1620 = shr(_T_1616, 2) @[Bitwise.scala 103:21]
-    node _T_1621 = and(_T_1620, _T_1619) @[Bitwise.scala 103:31]
-    node _T_1622 = bits(_T_1616, 29, 0) @[Bitwise.scala 103:46]
-    node _T_1623 = shl(_T_1622, 2) @[Bitwise.scala 103:65]
-    node _T_1624 = not(_T_1619) @[Bitwise.scala 103:77]
-    node _T_1625 = and(_T_1623, _T_1624) @[Bitwise.scala 103:75]
-    node _T_1626 = or(_T_1621, _T_1625) @[Bitwise.scala 103:39]
-    node _T_1627 = bits(_T_1619, 30, 0) @[Bitwise.scala 102:28]
-    node _T_1628 = shl(_T_1627, 1) @[Bitwise.scala 102:47]
-    node _T_1629 = xor(_T_1619, _T_1628) @[Bitwise.scala 102:21]
-    node _T_1630 = shr(_T_1626, 1) @[Bitwise.scala 103:21]
-    node _T_1631 = and(_T_1630, _T_1629) @[Bitwise.scala 103:31]
-    node _T_1632 = bits(_T_1626, 30, 0) @[Bitwise.scala 103:46]
-    node _T_1633 = shl(_T_1632, 1) @[Bitwise.scala 103:65]
-    node _T_1634 = not(_T_1629) @[Bitwise.scala 103:77]
-    node _T_1635 = and(_T_1633, _T_1634) @[Bitwise.scala 103:75]
-    node _T_1636 = or(_T_1631, _T_1635) @[Bitwise.scala 103:39]
-    io.store_datafn_lo_r <= _T_1636 @[lsu_dccm_ctl.scala 263:29]
-    node _T_1637 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_hi) @[lsu_dccm_ctl.scala 264:105]
-    node _T_1638 = bits(store_byteen_ext_r, 4, 4) @[lsu_dccm_ctl.scala 264:150]
-    node _T_1639 = eq(_T_1638, UInt<1>("h00")) @[lsu_dccm_ctl.scala 264:131]
-    node _T_1640 = and(_T_1637, _T_1639) @[lsu_dccm_ctl.scala 264:129]
-    node _T_1641 = bits(_T_1640, 0, 0) @[lsu_dccm_ctl.scala 264:157]
-    node _T_1642 = bits(io.stbuf_data_any, 7, 0) @[lsu_dccm_ctl.scala 264:181]
-    node _T_1643 = bits(io.store_data_hi_r, 7, 0) @[lsu_dccm_ctl.scala 264:213]
-    node _T_1644 = mux(_T_1641, _T_1642, _T_1643) @[lsu_dccm_ctl.scala 264:79]
-    node _T_1645 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
-    node _T_1646 = xor(UInt<8>("h0ff"), _T_1645) @[Bitwise.scala 102:21]
-    node _T_1647 = shr(_T_1644, 4) @[Bitwise.scala 103:21]
-    node _T_1648 = and(_T_1647, _T_1646) @[Bitwise.scala 103:31]
-    node _T_1649 = bits(_T_1644, 3, 0) @[Bitwise.scala 103:46]
-    node _T_1650 = shl(_T_1649, 4) @[Bitwise.scala 103:65]
-    node _T_1651 = not(_T_1646) @[Bitwise.scala 103:77]
-    node _T_1652 = and(_T_1650, _T_1651) @[Bitwise.scala 103:75]
-    node _T_1653 = or(_T_1648, _T_1652) @[Bitwise.scala 103:39]
-    node _T_1654 = bits(_T_1646, 5, 0) @[Bitwise.scala 102:28]
-    node _T_1655 = shl(_T_1654, 2) @[Bitwise.scala 102:47]
-    node _T_1656 = xor(_T_1646, _T_1655) @[Bitwise.scala 102:21]
-    node _T_1657 = shr(_T_1653, 2) @[Bitwise.scala 103:21]
-    node _T_1658 = and(_T_1657, _T_1656) @[Bitwise.scala 103:31]
-    node _T_1659 = bits(_T_1653, 5, 0) @[Bitwise.scala 103:46]
-    node _T_1660 = shl(_T_1659, 2) @[Bitwise.scala 103:65]
-    node _T_1661 = not(_T_1656) @[Bitwise.scala 103:77]
-    node _T_1662 = and(_T_1660, _T_1661) @[Bitwise.scala 103:75]
-    node _T_1663 = or(_T_1658, _T_1662) @[Bitwise.scala 103:39]
-    node _T_1664 = bits(_T_1656, 6, 0) @[Bitwise.scala 102:28]
-    node _T_1665 = shl(_T_1664, 1) @[Bitwise.scala 102:47]
-    node _T_1666 = xor(_T_1656, _T_1665) @[Bitwise.scala 102:21]
-    node _T_1667 = shr(_T_1663, 1) @[Bitwise.scala 103:21]
-    node _T_1668 = and(_T_1667, _T_1666) @[Bitwise.scala 103:31]
-    node _T_1669 = bits(_T_1663, 6, 0) @[Bitwise.scala 103:46]
-    node _T_1670 = shl(_T_1669, 1) @[Bitwise.scala 103:65]
-    node _T_1671 = not(_T_1666) @[Bitwise.scala 103:77]
-    node _T_1672 = and(_T_1670, _T_1671) @[Bitwise.scala 103:75]
-    node _T_1673 = or(_T_1668, _T_1672) @[Bitwise.scala 103:39]
-    node _T_1674 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_hi) @[lsu_dccm_ctl.scala 264:105]
-    node _T_1675 = bits(store_byteen_ext_r, 5, 5) @[lsu_dccm_ctl.scala 264:150]
-    node _T_1676 = eq(_T_1675, UInt<1>("h00")) @[lsu_dccm_ctl.scala 264:131]
-    node _T_1677 = and(_T_1674, _T_1676) @[lsu_dccm_ctl.scala 264:129]
-    node _T_1678 = bits(_T_1677, 0, 0) @[lsu_dccm_ctl.scala 264:157]
-    node _T_1679 = bits(io.stbuf_data_any, 15, 8) @[lsu_dccm_ctl.scala 264:181]
-    node _T_1680 = bits(io.store_data_hi_r, 15, 8) @[lsu_dccm_ctl.scala 264:213]
-    node _T_1681 = mux(_T_1678, _T_1679, _T_1680) @[lsu_dccm_ctl.scala 264:79]
-    node _T_1682 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
-    node _T_1683 = xor(UInt<8>("h0ff"), _T_1682) @[Bitwise.scala 102:21]
-    node _T_1684 = shr(_T_1681, 4) @[Bitwise.scala 103:21]
-    node _T_1685 = and(_T_1684, _T_1683) @[Bitwise.scala 103:31]
-    node _T_1686 = bits(_T_1681, 3, 0) @[Bitwise.scala 103:46]
-    node _T_1687 = shl(_T_1686, 4) @[Bitwise.scala 103:65]
-    node _T_1688 = not(_T_1683) @[Bitwise.scala 103:77]
-    node _T_1689 = and(_T_1687, _T_1688) @[Bitwise.scala 103:75]
-    node _T_1690 = or(_T_1685, _T_1689) @[Bitwise.scala 103:39]
-    node _T_1691 = bits(_T_1683, 5, 0) @[Bitwise.scala 102:28]
-    node _T_1692 = shl(_T_1691, 2) @[Bitwise.scala 102:47]
-    node _T_1693 = xor(_T_1683, _T_1692) @[Bitwise.scala 102:21]
-    node _T_1694 = shr(_T_1690, 2) @[Bitwise.scala 103:21]
-    node _T_1695 = and(_T_1694, _T_1693) @[Bitwise.scala 103:31]
-    node _T_1696 = bits(_T_1690, 5, 0) @[Bitwise.scala 103:46]
-    node _T_1697 = shl(_T_1696, 2) @[Bitwise.scala 103:65]
-    node _T_1698 = not(_T_1693) @[Bitwise.scala 103:77]
-    node _T_1699 = and(_T_1697, _T_1698) @[Bitwise.scala 103:75]
-    node _T_1700 = or(_T_1695, _T_1699) @[Bitwise.scala 103:39]
-    node _T_1701 = bits(_T_1693, 6, 0) @[Bitwise.scala 102:28]
-    node _T_1702 = shl(_T_1701, 1) @[Bitwise.scala 102:47]
-    node _T_1703 = xor(_T_1693, _T_1702) @[Bitwise.scala 102:21]
-    node _T_1704 = shr(_T_1700, 1) @[Bitwise.scala 103:21]
-    node _T_1705 = and(_T_1704, _T_1703) @[Bitwise.scala 103:31]
-    node _T_1706 = bits(_T_1700, 6, 0) @[Bitwise.scala 103:46]
-    node _T_1707 = shl(_T_1706, 1) @[Bitwise.scala 103:65]
-    node _T_1708 = not(_T_1703) @[Bitwise.scala 103:77]
-    node _T_1709 = and(_T_1707, _T_1708) @[Bitwise.scala 103:75]
-    node _T_1710 = or(_T_1705, _T_1709) @[Bitwise.scala 103:39]
-    node _T_1711 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_hi) @[lsu_dccm_ctl.scala 264:105]
-    node _T_1712 = bits(store_byteen_ext_r, 6, 6) @[lsu_dccm_ctl.scala 264:150]
-    node _T_1713 = eq(_T_1712, UInt<1>("h00")) @[lsu_dccm_ctl.scala 264:131]
-    node _T_1714 = and(_T_1711, _T_1713) @[lsu_dccm_ctl.scala 264:129]
-    node _T_1715 = bits(_T_1714, 0, 0) @[lsu_dccm_ctl.scala 264:157]
-    node _T_1716 = bits(io.stbuf_data_any, 23, 16) @[lsu_dccm_ctl.scala 264:181]
-    node _T_1717 = bits(io.store_data_hi_r, 23, 16) @[lsu_dccm_ctl.scala 264:213]
-    node _T_1718 = mux(_T_1715, _T_1716, _T_1717) @[lsu_dccm_ctl.scala 264:79]
-    node _T_1719 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
-    node _T_1720 = xor(UInt<8>("h0ff"), _T_1719) @[Bitwise.scala 102:21]
-    node _T_1721 = shr(_T_1718, 4) @[Bitwise.scala 103:21]
-    node _T_1722 = and(_T_1721, _T_1720) @[Bitwise.scala 103:31]
-    node _T_1723 = bits(_T_1718, 3, 0) @[Bitwise.scala 103:46]
-    node _T_1724 = shl(_T_1723, 4) @[Bitwise.scala 103:65]
-    node _T_1725 = not(_T_1720) @[Bitwise.scala 103:77]
-    node _T_1726 = and(_T_1724, _T_1725) @[Bitwise.scala 103:75]
-    node _T_1727 = or(_T_1722, _T_1726) @[Bitwise.scala 103:39]
-    node _T_1728 = bits(_T_1720, 5, 0) @[Bitwise.scala 102:28]
-    node _T_1729 = shl(_T_1728, 2) @[Bitwise.scala 102:47]
-    node _T_1730 = xor(_T_1720, _T_1729) @[Bitwise.scala 102:21]
-    node _T_1731 = shr(_T_1727, 2) @[Bitwise.scala 103:21]
-    node _T_1732 = and(_T_1731, _T_1730) @[Bitwise.scala 103:31]
-    node _T_1733 = bits(_T_1727, 5, 0) @[Bitwise.scala 103:46]
-    node _T_1734 = shl(_T_1733, 2) @[Bitwise.scala 103:65]
-    node _T_1735 = not(_T_1730) @[Bitwise.scala 103:77]
-    node _T_1736 = and(_T_1734, _T_1735) @[Bitwise.scala 103:75]
-    node _T_1737 = or(_T_1732, _T_1736) @[Bitwise.scala 103:39]
-    node _T_1738 = bits(_T_1730, 6, 0) @[Bitwise.scala 102:28]
-    node _T_1739 = shl(_T_1738, 1) @[Bitwise.scala 102:47]
-    node _T_1740 = xor(_T_1730, _T_1739) @[Bitwise.scala 102:21]
-    node _T_1741 = shr(_T_1737, 1) @[Bitwise.scala 103:21]
-    node _T_1742 = and(_T_1741, _T_1740) @[Bitwise.scala 103:31]
-    node _T_1743 = bits(_T_1737, 6, 0) @[Bitwise.scala 103:46]
-    node _T_1744 = shl(_T_1743, 1) @[Bitwise.scala 103:65]
-    node _T_1745 = not(_T_1740) @[Bitwise.scala 103:77]
-    node _T_1746 = and(_T_1744, _T_1745) @[Bitwise.scala 103:75]
-    node _T_1747 = or(_T_1742, _T_1746) @[Bitwise.scala 103:39]
-    node _T_1748 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_hi) @[lsu_dccm_ctl.scala 264:105]
-    node _T_1749 = bits(store_byteen_ext_r, 7, 7) @[lsu_dccm_ctl.scala 264:150]
-    node _T_1750 = eq(_T_1749, UInt<1>("h00")) @[lsu_dccm_ctl.scala 264:131]
-    node _T_1751 = and(_T_1748, _T_1750) @[lsu_dccm_ctl.scala 264:129]
-    node _T_1752 = bits(_T_1751, 0, 0) @[lsu_dccm_ctl.scala 264:157]
-    node _T_1753 = bits(io.stbuf_data_any, 31, 24) @[lsu_dccm_ctl.scala 264:181]
-    node _T_1754 = bits(io.store_data_hi_r, 31, 24) @[lsu_dccm_ctl.scala 264:213]
-    node _T_1755 = mux(_T_1752, _T_1753, _T_1754) @[lsu_dccm_ctl.scala 264:79]
-    node _T_1756 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
-    node _T_1757 = xor(UInt<8>("h0ff"), _T_1756) @[Bitwise.scala 102:21]
-    node _T_1758 = shr(_T_1755, 4) @[Bitwise.scala 103:21]
-    node _T_1759 = and(_T_1758, _T_1757) @[Bitwise.scala 103:31]
-    node _T_1760 = bits(_T_1755, 3, 0) @[Bitwise.scala 103:46]
-    node _T_1761 = shl(_T_1760, 4) @[Bitwise.scala 103:65]
-    node _T_1762 = not(_T_1757) @[Bitwise.scala 103:77]
-    node _T_1763 = and(_T_1761, _T_1762) @[Bitwise.scala 103:75]
-    node _T_1764 = or(_T_1759, _T_1763) @[Bitwise.scala 103:39]
-    node _T_1765 = bits(_T_1757, 5, 0) @[Bitwise.scala 102:28]
-    node _T_1766 = shl(_T_1765, 2) @[Bitwise.scala 102:47]
-    node _T_1767 = xor(_T_1757, _T_1766) @[Bitwise.scala 102:21]
-    node _T_1768 = shr(_T_1764, 2) @[Bitwise.scala 103:21]
-    node _T_1769 = and(_T_1768, _T_1767) @[Bitwise.scala 103:31]
-    node _T_1770 = bits(_T_1764, 5, 0) @[Bitwise.scala 103:46]
-    node _T_1771 = shl(_T_1770, 2) @[Bitwise.scala 103:65]
-    node _T_1772 = not(_T_1767) @[Bitwise.scala 103:77]
-    node _T_1773 = and(_T_1771, _T_1772) @[Bitwise.scala 103:75]
-    node _T_1774 = or(_T_1769, _T_1773) @[Bitwise.scala 103:39]
-    node _T_1775 = bits(_T_1767, 6, 0) @[Bitwise.scala 102:28]
-    node _T_1776 = shl(_T_1775, 1) @[Bitwise.scala 102:47]
-    node _T_1777 = xor(_T_1767, _T_1776) @[Bitwise.scala 102:21]
-    node _T_1778 = shr(_T_1774, 1) @[Bitwise.scala 103:21]
-    node _T_1779 = and(_T_1778, _T_1777) @[Bitwise.scala 103:31]
-    node _T_1780 = bits(_T_1774, 6, 0) @[Bitwise.scala 103:46]
-    node _T_1781 = shl(_T_1780, 1) @[Bitwise.scala 103:65]
-    node _T_1782 = not(_T_1777) @[Bitwise.scala 103:77]
-    node _T_1783 = and(_T_1781, _T_1782) @[Bitwise.scala 103:75]
-    node _T_1784 = or(_T_1779, _T_1783) @[Bitwise.scala 103:39]
-    wire _T_1785 : UInt<8>[4] @[lsu_dccm_ctl.scala 264:63]
-    _T_1785[0] <= _T_1673 @[lsu_dccm_ctl.scala 264:63]
-    _T_1785[1] <= _T_1710 @[lsu_dccm_ctl.scala 264:63]
-    _T_1785[2] <= _T_1747 @[lsu_dccm_ctl.scala 264:63]
-    _T_1785[3] <= _T_1784 @[lsu_dccm_ctl.scala 264:63]
-    node _T_1786 = cat(_T_1785[2], _T_1785[3]) @[Cat.scala 29:58]
-    node _T_1787 = cat(_T_1785[0], _T_1785[1]) @[Cat.scala 29:58]
-    node _T_1788 = cat(_T_1787, _T_1786) @[Cat.scala 29:58]
-    node _T_1789 = shl(UInt<16>("h0ffff"), 16) @[Bitwise.scala 102:47]
-    node _T_1790 = xor(UInt<32>("h0ffffffff"), _T_1789) @[Bitwise.scala 102:21]
-    node _T_1791 = shr(_T_1788, 16) @[Bitwise.scala 103:21]
-    node _T_1792 = and(_T_1791, _T_1790) @[Bitwise.scala 103:31]
-    node _T_1793 = bits(_T_1788, 15, 0) @[Bitwise.scala 103:46]
-    node _T_1794 = shl(_T_1793, 16) @[Bitwise.scala 103:65]
-    node _T_1795 = not(_T_1790) @[Bitwise.scala 103:77]
-    node _T_1796 = and(_T_1794, _T_1795) @[Bitwise.scala 103:75]
-    node _T_1797 = or(_T_1792, _T_1796) @[Bitwise.scala 103:39]
-    node _T_1798 = bits(_T_1790, 23, 0) @[Bitwise.scala 102:28]
-    node _T_1799 = shl(_T_1798, 8) @[Bitwise.scala 102:47]
-    node _T_1800 = xor(_T_1790, _T_1799) @[Bitwise.scala 102:21]
-    node _T_1801 = shr(_T_1797, 8) @[Bitwise.scala 103:21]
-    node _T_1802 = and(_T_1801, _T_1800) @[Bitwise.scala 103:31]
-    node _T_1803 = bits(_T_1797, 23, 0) @[Bitwise.scala 103:46]
-    node _T_1804 = shl(_T_1803, 8) @[Bitwise.scala 103:65]
-    node _T_1805 = not(_T_1800) @[Bitwise.scala 103:77]
-    node _T_1806 = and(_T_1804, _T_1805) @[Bitwise.scala 103:75]
-    node _T_1807 = or(_T_1802, _T_1806) @[Bitwise.scala 103:39]
-    node _T_1808 = bits(_T_1800, 27, 0) @[Bitwise.scala 102:28]
-    node _T_1809 = shl(_T_1808, 4) @[Bitwise.scala 102:47]
-    node _T_1810 = xor(_T_1800, _T_1809) @[Bitwise.scala 102:21]
-    node _T_1811 = shr(_T_1807, 4) @[Bitwise.scala 103:21]
-    node _T_1812 = and(_T_1811, _T_1810) @[Bitwise.scala 103:31]
-    node _T_1813 = bits(_T_1807, 27, 0) @[Bitwise.scala 103:46]
-    node _T_1814 = shl(_T_1813, 4) @[Bitwise.scala 103:65]
-    node _T_1815 = not(_T_1810) @[Bitwise.scala 103:77]
-    node _T_1816 = and(_T_1814, _T_1815) @[Bitwise.scala 103:75]
-    node _T_1817 = or(_T_1812, _T_1816) @[Bitwise.scala 103:39]
-    node _T_1818 = bits(_T_1810, 29, 0) @[Bitwise.scala 102:28]
-    node _T_1819 = shl(_T_1818, 2) @[Bitwise.scala 102:47]
-    node _T_1820 = xor(_T_1810, _T_1819) @[Bitwise.scala 102:21]
-    node _T_1821 = shr(_T_1817, 2) @[Bitwise.scala 103:21]
-    node _T_1822 = and(_T_1821, _T_1820) @[Bitwise.scala 103:31]
-    node _T_1823 = bits(_T_1817, 29, 0) @[Bitwise.scala 103:46]
-    node _T_1824 = shl(_T_1823, 2) @[Bitwise.scala 103:65]
-    node _T_1825 = not(_T_1820) @[Bitwise.scala 103:77]
-    node _T_1826 = and(_T_1824, _T_1825) @[Bitwise.scala 103:75]
-    node _T_1827 = or(_T_1822, _T_1826) @[Bitwise.scala 103:39]
-    node _T_1828 = bits(_T_1820, 30, 0) @[Bitwise.scala 102:28]
-    node _T_1829 = shl(_T_1828, 1) @[Bitwise.scala 102:47]
-    node _T_1830 = xor(_T_1820, _T_1829) @[Bitwise.scala 102:21]
-    node _T_1831 = shr(_T_1827, 1) @[Bitwise.scala 103:21]
-    node _T_1832 = and(_T_1831, _T_1830) @[Bitwise.scala 103:31]
-    node _T_1833 = bits(_T_1827, 30, 0) @[Bitwise.scala 103:46]
-    node _T_1834 = shl(_T_1833, 1) @[Bitwise.scala 103:65]
-    node _T_1835 = not(_T_1830) @[Bitwise.scala 103:77]
-    node _T_1836 = and(_T_1834, _T_1835) @[Bitwise.scala 103:75]
-    node _T_1837 = or(_T_1832, _T_1836) @[Bitwise.scala 103:39]
-    io.store_datafn_hi_r <= _T_1837 @[lsu_dccm_ctl.scala 264:29]
-    node _T_1838 = bits(io.store_data_hi_r, 31, 0) @[lsu_dccm_ctl.scala 265:55]
-    node _T_1839 = bits(io.store_data_lo_r, 31, 0) @[lsu_dccm_ctl.scala 265:80]
-    node _T_1840 = cat(_T_1838, _T_1839) @[Cat.scala 29:58]
-    node _T_1841 = bits(io.lsu_addr_r, 1, 0) @[lsu_dccm_ctl.scala 265:108]
-    node _T_1842 = mul(UInt<4>("h08"), _T_1841) @[lsu_dccm_ctl.scala 265:94]
-    node _T_1843 = dshr(_T_1840, _T_1842) @[lsu_dccm_ctl.scala 265:88]
-    node _T_1844 = bits(store_byteen_r, 0, 0) @[lsu_dccm_ctl.scala 265:174]
-    node _T_1845 = bits(_T_1844, 0, 0) @[Bitwise.scala 72:15]
-    node _T_1846 = mux(_T_1845, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
-    node _T_1847 = bits(store_byteen_r, 1, 1) @[lsu_dccm_ctl.scala 265:174]
-    node _T_1848 = bits(_T_1847, 0, 0) @[Bitwise.scala 72:15]
-    node _T_1849 = mux(_T_1848, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
-    node _T_1850 = bits(store_byteen_r, 2, 2) @[lsu_dccm_ctl.scala 265:174]
-    node _T_1851 = bits(_T_1850, 0, 0) @[Bitwise.scala 72:15]
-    node _T_1852 = mux(_T_1851, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
-    node _T_1853 = bits(store_byteen_r, 3, 3) @[lsu_dccm_ctl.scala 265:174]
-    node _T_1854 = bits(_T_1853, 0, 0) @[Bitwise.scala 72:15]
-    node _T_1855 = mux(_T_1854, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
-    wire _T_1856 : UInt<8>[4] @[lsu_dccm_ctl.scala 265:148]
-    _T_1856[0] <= _T_1846 @[lsu_dccm_ctl.scala 265:148]
-    _T_1856[1] <= _T_1849 @[lsu_dccm_ctl.scala 265:148]
-    _T_1856[2] <= _T_1852 @[lsu_dccm_ctl.scala 265:148]
-    _T_1856[3] <= _T_1855 @[lsu_dccm_ctl.scala 265:148]
-    node _T_1857 = cat(_T_1856[2], _T_1856[3]) @[Cat.scala 29:58]
-    node _T_1858 = cat(_T_1856[0], _T_1856[1]) @[Cat.scala 29:58]
-    node _T_1859 = cat(_T_1858, _T_1857) @[Cat.scala 29:58]
-    node _T_1860 = shl(UInt<16>("h0ffff"), 16) @[Bitwise.scala 102:47]
-    node _T_1861 = xor(UInt<32>("h0ffffffff"), _T_1860) @[Bitwise.scala 102:21]
-    node _T_1862 = shr(_T_1859, 16) @[Bitwise.scala 103:21]
-    node _T_1863 = and(_T_1862, _T_1861) @[Bitwise.scala 103:31]
-    node _T_1864 = bits(_T_1859, 15, 0) @[Bitwise.scala 103:46]
-    node _T_1865 = shl(_T_1864, 16) @[Bitwise.scala 103:65]
-    node _T_1866 = not(_T_1861) @[Bitwise.scala 103:77]
-    node _T_1867 = and(_T_1865, _T_1866) @[Bitwise.scala 103:75]
-    node _T_1868 = or(_T_1863, _T_1867) @[Bitwise.scala 103:39]
-    node _T_1869 = bits(_T_1861, 23, 0) @[Bitwise.scala 102:28]
-    node _T_1870 = shl(_T_1869, 8) @[Bitwise.scala 102:47]
-    node _T_1871 = xor(_T_1861, _T_1870) @[Bitwise.scala 102:21]
-    node _T_1872 = shr(_T_1868, 8) @[Bitwise.scala 103:21]
-    node _T_1873 = and(_T_1872, _T_1871) @[Bitwise.scala 103:31]
-    node _T_1874 = bits(_T_1868, 23, 0) @[Bitwise.scala 103:46]
-    node _T_1875 = shl(_T_1874, 8) @[Bitwise.scala 103:65]
-    node _T_1876 = not(_T_1871) @[Bitwise.scala 103:77]
-    node _T_1877 = and(_T_1875, _T_1876) @[Bitwise.scala 103:75]
-    node _T_1878 = or(_T_1873, _T_1877) @[Bitwise.scala 103:39]
-    node _T_1879 = bits(_T_1871, 27, 0) @[Bitwise.scala 102:28]
-    node _T_1880 = shl(_T_1879, 4) @[Bitwise.scala 102:47]
-    node _T_1881 = xor(_T_1871, _T_1880) @[Bitwise.scala 102:21]
-    node _T_1882 = shr(_T_1878, 4) @[Bitwise.scala 103:21]
-    node _T_1883 = and(_T_1882, _T_1881) @[Bitwise.scala 103:31]
-    node _T_1884 = bits(_T_1878, 27, 0) @[Bitwise.scala 103:46]
-    node _T_1885 = shl(_T_1884, 4) @[Bitwise.scala 103:65]
-    node _T_1886 = not(_T_1881) @[Bitwise.scala 103:77]
-    node _T_1887 = and(_T_1885, _T_1886) @[Bitwise.scala 103:75]
-    node _T_1888 = or(_T_1883, _T_1887) @[Bitwise.scala 103:39]
-    node _T_1889 = bits(_T_1881, 29, 0) @[Bitwise.scala 102:28]
-    node _T_1890 = shl(_T_1889, 2) @[Bitwise.scala 102:47]
-    node _T_1891 = xor(_T_1881, _T_1890) @[Bitwise.scala 102:21]
-    node _T_1892 = shr(_T_1888, 2) @[Bitwise.scala 103:21]
-    node _T_1893 = and(_T_1892, _T_1891) @[Bitwise.scala 103:31]
-    node _T_1894 = bits(_T_1888, 29, 0) @[Bitwise.scala 103:46]
-    node _T_1895 = shl(_T_1894, 2) @[Bitwise.scala 103:65]
-    node _T_1896 = not(_T_1891) @[Bitwise.scala 103:77]
-    node _T_1897 = and(_T_1895, _T_1896) @[Bitwise.scala 103:75]
-    node _T_1898 = or(_T_1893, _T_1897) @[Bitwise.scala 103:39]
-    node _T_1899 = bits(_T_1891, 30, 0) @[Bitwise.scala 102:28]
-    node _T_1900 = shl(_T_1899, 1) @[Bitwise.scala 102:47]
-    node _T_1901 = xor(_T_1891, _T_1900) @[Bitwise.scala 102:21]
-    node _T_1902 = shr(_T_1898, 1) @[Bitwise.scala 103:21]
-    node _T_1903 = and(_T_1902, _T_1901) @[Bitwise.scala 103:31]
-    node _T_1904 = bits(_T_1898, 30, 0) @[Bitwise.scala 103:46]
-    node _T_1905 = shl(_T_1904, 1) @[Bitwise.scala 103:65]
-    node _T_1906 = not(_T_1901) @[Bitwise.scala 103:77]
-    node _T_1907 = and(_T_1905, _T_1906) @[Bitwise.scala 103:75]
-    node _T_1908 = or(_T_1903, _T_1907) @[Bitwise.scala 103:39]
-    node _T_1909 = and(_T_1843, _T_1908) @[lsu_dccm_ctl.scala 265:115]
-    io.store_data_r <= _T_1909 @[lsu_dccm_ctl.scala 265:29]
-    node _T_1910 = bits(io.dccm.rd_data_lo, 31, 0) @[lsu_dccm_ctl.scala 267:48]
-    io.dccm_rdata_lo_m <= _T_1910 @[lsu_dccm_ctl.scala 267:27]
-    node _T_1911 = bits(io.dccm.rd_data_hi, 31, 0) @[lsu_dccm_ctl.scala 268:48]
-    io.dccm_rdata_hi_m <= _T_1911 @[lsu_dccm_ctl.scala 268:27]
-    node _T_1912 = bits(io.dccm.rd_data_lo, 38, 32) @[lsu_dccm_ctl.scala 269:48]
-    io.dccm_data_ecc_lo_m <= _T_1912 @[lsu_dccm_ctl.scala 269:27]
-    node _T_1913 = bits(io.dccm.rd_data_hi, 38, 32) @[lsu_dccm_ctl.scala 270:48]
-    io.dccm_data_ecc_hi_m <= _T_1913 @[lsu_dccm_ctl.scala 270:27]
-    node _T_1914 = and(io.lsu_pkt_r.valid, io.lsu_pkt_r.bits.store) @[lsu_dccm_ctl.scala 272:58]
-    node _T_1915 = and(_T_1914, io.addr_in_pic_r) @[lsu_dccm_ctl.scala 272:84]
-    node _T_1916 = and(_T_1915, io.lsu_commit_r) @[lsu_dccm_ctl.scala 272:103]
-    node _T_1917 = or(_T_1916, io.dma_pic_wen) @[lsu_dccm_ctl.scala 272:122]
-    io.lsu_pic.picm_wren <= _T_1917 @[lsu_dccm_ctl.scala 272:35]
-    node _T_1918 = and(io.lsu_pkt_d.valid, io.lsu_pkt_d.bits.load) @[lsu_dccm_ctl.scala 273:58]
-    node _T_1919 = and(_T_1918, io.addr_in_pic_d) @[lsu_dccm_ctl.scala 273:84]
-    io.lsu_pic.picm_rden <= _T_1919 @[lsu_dccm_ctl.scala 273:35]
-    node _T_1920 = and(io.lsu_pkt_d.valid, io.lsu_pkt_d.bits.store) @[lsu_dccm_ctl.scala 274:58]
-    node _T_1921 = and(_T_1920, io.addr_in_pic_d) @[lsu_dccm_ctl.scala 274:84]
-    io.lsu_pic.picm_mken <= _T_1921 @[lsu_dccm_ctl.scala 274:35]
-    node _T_1922 = mux(UInt<1>("h00"), UInt<17>("h01ffff"), UInt<17>("h00")) @[Bitwise.scala 72:12]
-    node _T_1923 = bits(io.lsu_addr_d, 14, 0) @[lsu_dccm_ctl.scala 275:103]
-    node _T_1924 = cat(_T_1922, _T_1923) @[Cat.scala 29:58]
-    node _T_1925 = or(UInt<32>("h0f00c0000"), _T_1924) @[lsu_dccm_ctl.scala 275:62]
-    io.lsu_pic.picm_rdaddr <= _T_1925 @[lsu_dccm_ctl.scala 275:35]
-    node _T_1926 = mux(UInt<1>("h00"), UInt<17>("h01ffff"), UInt<17>("h00")) @[Bitwise.scala 72:12]
-    node _T_1927 = bits(io.dma_pic_wen, 0, 0) @[lsu_dccm_ctl.scala 276:109]
-    node _T_1928 = bits(io.dma_dccm_ctl.dma_mem_addr, 14, 0) @[lsu_dccm_ctl.scala 276:144]
-    node _T_1929 = bits(io.lsu_addr_r, 14, 0) @[lsu_dccm_ctl.scala 276:172]
-    node _T_1930 = mux(_T_1927, _T_1928, _T_1929) @[lsu_dccm_ctl.scala 276:93]
-    node _T_1931 = cat(_T_1926, _T_1930) @[Cat.scala 29:58]
-    node _T_1932 = or(UInt<32>("h0f00c0000"), _T_1931) @[lsu_dccm_ctl.scala 276:62]
-    io.lsu_pic.picm_wraddr <= _T_1932 @[lsu_dccm_ctl.scala 276:35]
-    node _T_1933 = bits(picm_rd_data_m, 31, 0) @[lsu_dccm_ctl.scala 277:44]
-    io.picm_mask_data_m <= _T_1933 @[lsu_dccm_ctl.scala 277:27]
-    node _T_1934 = bits(io.dma_pic_wen, 0, 0) @[lsu_dccm_ctl.scala 278:57]
-    node _T_1935 = bits(io.dma_dccm_ctl.dma_mem_wdata, 31, 0) @[lsu_dccm_ctl.scala 278:93]
-    node _T_1936 = bits(io.store_datafn_lo_r, 31, 0) @[lsu_dccm_ctl.scala 278:120]
-    node _T_1937 = mux(_T_1934, _T_1935, _T_1936) @[lsu_dccm_ctl.scala 278:41]
-    io.lsu_pic.picm_wr_data <= _T_1937 @[lsu_dccm_ctl.scala 278:35]
-    reg _T_1938 : UInt, io.lsu_c2_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_dccm_ctl.scala 280:61]
-    _T_1938 <= lsu_dccm_rden_d @[lsu_dccm_ctl.scala 280:61]
-    io.lsu_dccm_rden_m <= _T_1938 @[lsu_dccm_ctl.scala 280:24]
-    reg _T_1939 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_dccm_ctl.scala 281:61]
-    _T_1939 <= io.lsu_dccm_rden_m @[lsu_dccm_ctl.scala 281:61]
-    io.lsu_dccm_rden_r <= _T_1939 @[lsu_dccm_ctl.scala 281:24]
-    reg _T_1940 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_dccm_ctl.scala 282:73]
-    _T_1940 <= io.lsu_double_ecc_error_r @[lsu_dccm_ctl.scala 282:73]
-    lsu_double_ecc_error_r_ff <= _T_1940 @[lsu_dccm_ctl.scala 282:33]
-    reg _T_1941 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_dccm_ctl.scala 283:73]
-    _T_1941 <= ld_single_ecc_error_hi_r_ns @[lsu_dccm_ctl.scala 283:73]
-    ld_single_ecc_error_hi_r_ff <= _T_1941 @[lsu_dccm_ctl.scala 283:33]
-    reg _T_1942 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_dccm_ctl.scala 284:73]
-    _T_1942 <= ld_single_ecc_error_lo_r_ns @[lsu_dccm_ctl.scala 284:73]
-    ld_single_ecc_error_lo_r_ff <= _T_1942 @[lsu_dccm_ctl.scala 284:33]
-    node _T_1943 = bits(io.end_addr_r, 15, 0) @[lsu_dccm_ctl.scala 285:48]
-    node _T_1944 = or(io.ld_single_ecc_error_r, io.clk_override) @[lsu_dccm_ctl.scala 285:90]
-    node _T_1945 = bits(_T_1944, 0, 0) @[lib.scala 8:44]
-    node _T_1946 = bits(io.scan_mode, 0, 0) @[lsu_dccm_ctl.scala 285:128]
-    inst rvclkhdr_2 of rvclkhdr_6 @[lib.scala 368:23]
-    rvclkhdr_2.clock <= clock
-    rvclkhdr_2.reset <= reset
-    rvclkhdr_2.io.clk <= clock @[lib.scala 370:18]
-    rvclkhdr_2.io.en <= _T_1945 @[lib.scala 371:17]
-    rvclkhdr_2.io.scan_mode <= _T_1946 @[lib.scala 372:24]
-    reg _T_1947 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
-    _T_1947 <= _T_1943 @[lib.scala 374:16]
-    ld_sec_addr_hi_r_ff <= _T_1947 @[lsu_dccm_ctl.scala 285:25]
-    node _T_1948 = bits(io.lsu_addr_r, 15, 0) @[lsu_dccm_ctl.scala 286:48]
-    node _T_1949 = or(io.ld_single_ecc_error_r, io.clk_override) @[lsu_dccm_ctl.scala 286:90]
-    node _T_1950 = bits(_T_1949, 0, 0) @[lib.scala 8:44]
-    node _T_1951 = bits(io.scan_mode, 0, 0) @[lsu_dccm_ctl.scala 286:128]
-    inst rvclkhdr_3 of rvclkhdr_7 @[lib.scala 368:23]
-    rvclkhdr_3.clock <= clock
-    rvclkhdr_3.reset <= reset
-    rvclkhdr_3.io.clk <= clock @[lib.scala 370:18]
-    rvclkhdr_3.io.en <= _T_1950 @[lib.scala 371:17]
-    rvclkhdr_3.io.scan_mode <= _T_1951 @[lib.scala 372:24]
-    reg _T_1952 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
-    _T_1952 <= _T_1948 @[lib.scala 374:16]
-    ld_sec_addr_lo_r_ff <= _T_1952 @[lsu_dccm_ctl.scala 286:25]
-    
   extmodule gated_latch_8 : 
     output Q : Clock
     input CK : Clock
@@ -3321,6 +1164,2199 @@ circuit lsu :
     clkhdr.EN <= io.en @[lib.scala 337:18]
     clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
     
+  module lsu_dccm_ctl : 
+    input clock : Clock
+    input reset : AsyncReset
+    output io : {flip clk_override : UInt<1>, flip lsu_c2_m_clk : Clock, flip lsu_c2_r_clk : Clock, flip lsu_free_c2_clk : Clock, flip lsu_c1_r_clk : Clock, flip lsu_store_c1_r_clk : Clock, flip lsu_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_pkt_r : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip addr_in_dccm_d : UInt<1>, flip addr_in_dccm_m : UInt<1>, flip addr_in_dccm_r : UInt<1>, flip addr_in_pic_d : UInt<1>, flip addr_in_pic_m : UInt<1>, flip addr_in_pic_r : UInt<1>, flip lsu_raw_fwd_lo_r : UInt<1>, flip lsu_raw_fwd_hi_r : UInt<1>, flip lsu_commit_r : UInt<1>, flip ldst_dual_m : UInt<1>, flip ldst_dual_r : UInt<1>, flip lsu_addr_d : UInt<32>, flip lsu_addr_m : UInt<16>, flip lsu_addr_r : UInt<32>, flip end_addr_d : UInt<16>, flip end_addr_m : UInt<16>, flip end_addr_r : UInt<16>, flip stbuf_reqvld_any : UInt<1>, flip stbuf_addr_any : UInt<16>, flip stbuf_data_any : UInt<32>, flip stbuf_ecc_any : UInt<7>, flip stbuf_fwddata_hi_m : UInt<32>, flip stbuf_fwddata_lo_m : UInt<32>, flip stbuf_fwdbyteen_lo_m : UInt<4>, flip stbuf_fwdbyteen_hi_m : UInt<4>, dccm_rdata_hi_r : UInt<32>, dccm_rdata_lo_r : UInt<32>, dccm_data_ecc_hi_r : UInt<7>, dccm_data_ecc_lo_r : UInt<7>, lsu_ld_data_r : UInt<32>, lsu_ld_data_corr_r : UInt<32>, flip lsu_double_ecc_error_r : UInt<1>, flip single_ecc_error_hi_r : UInt<1>, flip single_ecc_error_lo_r : UInt<1>, flip sec_data_hi_r : UInt<32>, flip sec_data_lo_r : UInt<32>, flip sec_data_hi_r_ff : UInt<32>, flip sec_data_lo_r_ff : UInt<32>, flip sec_data_ecc_hi_r_ff : UInt<7>, flip sec_data_ecc_lo_r_ff : UInt<7>, dccm_rdata_hi_m : UInt<32>, dccm_rdata_lo_m : UInt<32>, dccm_data_ecc_hi_m : UInt<7>, dccm_data_ecc_lo_m : UInt<7>, lsu_ld_data_m : UInt<32>, flip lsu_double_ecc_error_m : UInt<1>, flip sec_data_hi_m : UInt<32>, flip sec_data_lo_m : UInt<32>, flip store_data_m : UInt<32>, flip dma_dccm_wen : UInt<1>, flip dma_pic_wen : UInt<1>, flip dma_mem_tag_m : UInt<3>, flip dma_dccm_wdata_lo : UInt<32>, flip dma_dccm_wdata_hi : UInt<32>, flip dma_dccm_wdata_ecc_hi : UInt<7>, flip dma_dccm_wdata_ecc_lo : UInt<7>, store_data_hi_r : UInt<32>, store_data_lo_r : UInt<32>, store_datafn_hi_r : UInt<32>, store_datafn_lo_r : UInt<32>, store_data_r : UInt<32>, ld_single_ecc_error_r : UInt<1>, ld_single_ecc_error_r_ff : UInt<1>, picm_mask_data_m : UInt<32>, lsu_stbuf_commit_any : UInt<1>, lsu_dccm_rden_m : UInt<1>, lsu_dccm_rden_r : UInt<1>, dma_dccm_ctl : {flip dma_mem_addr : UInt<32>, flip dma_mem_wdata : UInt<64>, dccm_dma_rvalid : UInt<1>, dccm_dma_ecc_error : UInt<1>, dccm_dma_rtag : UInt<3>, dccm_dma_rdata : UInt<64>}, flip dccm : {flip wren : UInt<1>, flip rden : UInt<1>, flip wr_addr_lo : UInt<16>, flip wr_addr_hi : UInt<16>, flip rd_addr_lo : UInt<16>, flip rd_addr_hi : UInt<16>, flip wr_data_lo : UInt<39>, flip wr_data_hi : UInt<39>, rd_data_lo : UInt<39>, rd_data_hi : UInt<39>}, lsu_pic : {picm_wren : UInt<1>, picm_rden : UInt<1>, picm_mken : UInt<1>, picm_rdaddr : UInt<32>, picm_wraddr : UInt<32>, picm_wr_data : UInt<32>, flip picm_rd_data : UInt<32>}, flip scan_mode : UInt<1>}
+    
+    node picm_rd_data_m = cat(io.lsu_pic.picm_rd_data, io.lsu_pic.picm_rd_data) @[Cat.scala 29:58]
+    node dccm_rdata_corr_r = cat(io.sec_data_hi_r, io.sec_data_lo_r) @[Cat.scala 29:58]
+    node dccm_rdata_corr_m = cat(io.sec_data_hi_m, io.sec_data_lo_m) @[Cat.scala 29:58]
+    node dccm_rdata_r = cat(io.dccm_rdata_hi_r, io.dccm_rdata_lo_r) @[Cat.scala 29:58]
+    node dccm_rdata_m = cat(io.dccm_rdata_hi_m, io.dccm_rdata_lo_m) @[Cat.scala 29:58]
+    wire lsu_rdata_r : UInt<64>
+    lsu_rdata_r <= UInt<1>("h00")
+    wire lsu_rdata_m : UInt<64>
+    lsu_rdata_m <= UInt<1>("h00")
+    wire lsu_rdata_corr_r : UInt<64>
+    lsu_rdata_corr_r <= UInt<1>("h00")
+    wire lsu_rdata_corr_m : UInt<64>
+    lsu_rdata_corr_m <= UInt<1>("h00")
+    wire stbuf_fwddata_r : UInt<64>
+    stbuf_fwddata_r <= UInt<1>("h00")
+    wire stbuf_fwdbyteen_r : UInt<64>
+    stbuf_fwdbyteen_r <= UInt<1>("h00")
+    wire picm_rd_data_r_32 : UInt<32>
+    picm_rd_data_r_32 <= UInt<1>("h00")
+    wire picm_rd_data_r : UInt<64>
+    picm_rd_data_r <= UInt<1>("h00")
+    wire lsu_ld_data_corr_m : UInt<64>
+    lsu_ld_data_corr_m <= UInt<1>("h00")
+    wire stbuf_fwddata_en : UInt<1>
+    stbuf_fwddata_en <= UInt<1>("h00")
+    wire lsu_double_ecc_error_r_ff : UInt<1>
+    lsu_double_ecc_error_r_ff <= UInt<1>("h00")
+    wire ld_single_ecc_error_hi_r_ff : UInt<1>
+    ld_single_ecc_error_hi_r_ff <= UInt<1>("h00")
+    wire ld_single_ecc_error_lo_r_ff : UInt<1>
+    ld_single_ecc_error_lo_r_ff <= UInt<1>("h00")
+    wire ld_sec_addr_hi_r_ff : UInt<16>
+    ld_sec_addr_hi_r_ff <= UInt<1>("h00")
+    wire ld_sec_addr_lo_r_ff : UInt<16>
+    ld_sec_addr_lo_r_ff <= UInt<1>("h00")
+    io.lsu_ld_data_m <= UInt<1>("h00") @[lsu_dccm_ctl.scala 121:20]
+    node _T = and(io.lsu_pkt_r.valid, io.lsu_pkt_r.bits.load) @[lsu_dccm_ctl.scala 124:62]
+    node _T_1 = and(_T, io.lsu_pkt_r.bits.dma) @[lsu_dccm_ctl.scala 124:87]
+    io.dma_dccm_ctl.dccm_dma_rvalid <= _T_1 @[lsu_dccm_ctl.scala 124:40]
+    io.dma_dccm_ctl.dccm_dma_ecc_error <= io.lsu_double_ecc_error_r @[lsu_dccm_ctl.scala 125:40]
+    node _T_2 = bits(io.ldst_dual_r, 0, 0) @[lib.scala 8:44]
+    node _T_3 = bits(lsu_rdata_corr_r, 31, 0) @[lsu_dccm_ctl.scala 126:103]
+    node _T_4 = cat(_T_3, _T_3) @[Cat.scala 29:58]
+    node _T_5 = mux(_T_2, lsu_rdata_corr_r, _T_4) @[lsu_dccm_ctl.scala 126:46]
+    io.dma_dccm_ctl.dccm_dma_rdata <= _T_5 @[lsu_dccm_ctl.scala 126:40]
+    node _T_6 = orr(io.stbuf_fwdbyteen_hi_m) @[lsu_dccm_ctl.scala 127:49]
+    node _T_7 = orr(io.stbuf_fwdbyteen_lo_m) @[lsu_dccm_ctl.scala 127:79]
+    node _T_8 = or(_T_6, _T_7) @[lsu_dccm_ctl.scala 127:53]
+    node _T_9 = or(_T_8, io.clk_override) @[lsu_dccm_ctl.scala 127:83]
+    stbuf_fwddata_en <= _T_9 @[lsu_dccm_ctl.scala 127:22]
+    node _T_10 = and(io.lsu_dccm_rden_m, io.ldst_dual_m) @[lsu_dccm_ctl.scala 129:77]
+    node _T_11 = or(_T_10, io.clk_override) @[lsu_dccm_ctl.scala 129:95]
+    node _T_12 = bits(_T_11, 0, 0) @[lib.scala 8:44]
+    node _T_13 = bits(io.scan_mode, 0, 0) @[lsu_dccm_ctl.scala 129:133]
+    inst rvclkhdr of rvclkhdr_3 @[lib.scala 390:23]
+    rvclkhdr.clock <= clock
+    rvclkhdr.reset <= reset
+    rvclkhdr.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr.io.en <= _T_12 @[lib.scala 393:17]
+    rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg _T_14 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_12 : @[Reg.scala 28:19]
+      _T_14 <= io.dccm_rdata_hi_m @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    io.dccm_rdata_hi_r <= _T_14 @[lsu_dccm_ctl.scala 129:27]
+    node _T_15 = or(io.lsu_dccm_rden_m, io.clk_override) @[lsu_dccm_ctl.scala 130:75]
+    node _T_16 = bits(_T_15, 0, 0) @[lsu_dccm_ctl.scala 130:93]
+    node _T_17 = bits(io.scan_mode, 0, 0) @[lsu_dccm_ctl.scala 130:119]
+    inst rvclkhdr_1 of rvclkhdr_4 @[lib.scala 390:23]
+    rvclkhdr_1.clock <= clock
+    rvclkhdr_1.reset <= reset
+    rvclkhdr_1.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr_1.io.en <= _T_16 @[lib.scala 393:17]
+    rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg _T_18 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_16 : @[Reg.scala 28:19]
+      _T_18 <= io.dccm_rdata_lo_m @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    io.dccm_rdata_lo_r <= _T_18 @[lsu_dccm_ctl.scala 130:27]
+    node _T_19 = or(io.lsu_dccm_rden_m, io.clk_override) @[lsu_dccm_ctl.scala 131:78]
+    node _T_20 = bits(_T_19, 0, 0) @[lsu_dccm_ctl.scala 131:96]
+    node _T_21 = bits(io.scan_mode, 0, 0) @[lsu_dccm_ctl.scala 131:122]
+    inst rvclkhdr_2 of rvclkhdr_5 @[lib.scala 390:23]
+    rvclkhdr_2.clock <= clock
+    rvclkhdr_2.reset <= reset
+    rvclkhdr_2.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr_2.io.en <= _T_20 @[lib.scala 393:17]
+    rvclkhdr_2.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg _T_22 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_20 : @[Reg.scala 28:19]
+      _T_22 <= io.dccm_data_ecc_hi_m @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    io.dccm_data_ecc_hi_r <= _T_22 @[lsu_dccm_ctl.scala 131:27]
+    node _T_23 = or(io.lsu_dccm_rden_m, io.clk_override) @[lsu_dccm_ctl.scala 132:78]
+    node _T_24 = bits(_T_23, 0, 0) @[lsu_dccm_ctl.scala 132:96]
+    node _T_25 = bits(io.scan_mode, 0, 0) @[lsu_dccm_ctl.scala 132:122]
+    inst rvclkhdr_3 of rvclkhdr_6 @[lib.scala 390:23]
+    rvclkhdr_3.clock <= clock
+    rvclkhdr_3.reset <= reset
+    rvclkhdr_3.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr_3.io.en <= _T_24 @[lib.scala 393:17]
+    rvclkhdr_3.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg _T_26 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_24 : @[Reg.scala 28:19]
+      _T_26 <= io.dccm_data_ecc_lo_m @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    io.dccm_data_ecc_lo_r <= _T_26 @[lsu_dccm_ctl.scala 132:27]
+    node _T_27 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58]
+    reg _T_28 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_dccm_ctl.scala 133:64]
+    _T_28 <= _T_27 @[lsu_dccm_ctl.scala 133:64]
+    stbuf_fwdbyteen_r <= _T_28 @[lsu_dccm_ctl.scala 133:27]
+    node _T_29 = bits(stbuf_fwddata_en, 0, 0) @[lib.scala 8:44]
+    node _T_30 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44]
+    inst rvclkhdr_4 of rvclkhdr_7 @[lib.scala 390:23]
+    rvclkhdr_4.clock <= clock
+    rvclkhdr_4.reset <= reset
+    rvclkhdr_4.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr_4.io.en <= _T_29 @[lib.scala 393:17]
+    rvclkhdr_4.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg _T_31 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_29 : @[Reg.scala 28:19]
+      _T_31 <= io.stbuf_fwddata_hi_m @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    node _T_32 = bits(stbuf_fwddata_en, 0, 0) @[lib.scala 8:44]
+    node _T_33 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44]
+    inst rvclkhdr_5 of rvclkhdr_8 @[lib.scala 390:23]
+    rvclkhdr_5.clock <= clock
+    rvclkhdr_5.reset <= reset
+    rvclkhdr_5.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr_5.io.en <= _T_32 @[lib.scala 393:17]
+    rvclkhdr_5.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg _T_34 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_32 : @[Reg.scala 28:19]
+      _T_34 <= io.stbuf_fwddata_lo_m @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    node _T_35 = cat(_T_31, _T_34) @[Cat.scala 29:58]
+    stbuf_fwddata_r <= _T_35 @[lsu_dccm_ctl.scala 134:27]
+    node _T_36 = bits(picm_rd_data_m, 31, 0) @[lsu_dccm_ctl.scala 135:51]
+    node _T_37 = or(io.addr_in_pic_m, io.clk_override) @[lsu_dccm_ctl.scala 135:76]
+    node _T_38 = bits(_T_37, 0, 0) @[lib.scala 8:44]
+    node _T_39 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44]
+    inst rvclkhdr_6 of rvclkhdr_9 @[lib.scala 390:23]
+    rvclkhdr_6.clock <= clock
+    rvclkhdr_6.reset <= reset
+    rvclkhdr_6.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr_6.io.en <= _T_38 @[lib.scala 393:17]
+    rvclkhdr_6.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg _T_40 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_38 : @[Reg.scala 28:19]
+      _T_40 <= _T_36 @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    picm_rd_data_r_32 <= _T_40 @[lsu_dccm_ctl.scala 135:27]
+    node _T_41 = cat(picm_rd_data_r_32, picm_rd_data_r_32) @[Cat.scala 29:58]
+    picm_rd_data_r <= _T_41 @[lsu_dccm_ctl.scala 136:27]
+    reg _T_42 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_dccm_ctl.scala 137:77]
+    _T_42 <= io.dma_mem_tag_m @[lsu_dccm_ctl.scala 137:77]
+    io.dma_dccm_ctl.dccm_dma_rtag <= _T_42 @[lsu_dccm_ctl.scala 137:40]
+    node _T_43 = bits(stbuf_fwdbyteen_r, 0, 0) @[lsu_dccm_ctl.scala 138:95]
+    node _T_44 = bits(_T_43, 0, 0) @[lsu_dccm_ctl.scala 138:99]
+    node _T_45 = bits(stbuf_fwddata_r, 7, 0) @[lsu_dccm_ctl.scala 138:121]
+    node _T_46 = bits(io.addr_in_pic_r, 0, 0) @[lsu_dccm_ctl.scala 138:157]
+    node _T_47 = bits(picm_rd_data_r, 7, 0) @[lsu_dccm_ctl.scala 138:178]
+    node _T_48 = bits(io.addr_in_dccm_r, 0, 0) @[Bitwise.scala 72:15]
+    node _T_49 = mux(_T_48, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
+    node _T_50 = bits(dccm_rdata_corr_r, 7, 0) @[lsu_dccm_ctl.scala 138:238]
+    node _T_51 = and(_T_49, _T_50) @[lsu_dccm_ctl.scala 138:219]
+    node _T_52 = mux(_T_46, _T_47, _T_51) @[lsu_dccm_ctl.scala 138:139]
+    node _T_53 = mux(_T_44, _T_45, _T_52) @[lsu_dccm_ctl.scala 138:77]
+    node _T_54 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
+    node _T_55 = xor(UInt<8>("h0ff"), _T_54) @[Bitwise.scala 102:21]
+    node _T_56 = shr(_T_53, 4) @[Bitwise.scala 103:21]
+    node _T_57 = and(_T_56, _T_55) @[Bitwise.scala 103:31]
+    node _T_58 = bits(_T_53, 3, 0) @[Bitwise.scala 103:46]
+    node _T_59 = shl(_T_58, 4) @[Bitwise.scala 103:65]
+    node _T_60 = not(_T_55) @[Bitwise.scala 103:77]
+    node _T_61 = and(_T_59, _T_60) @[Bitwise.scala 103:75]
+    node _T_62 = or(_T_57, _T_61) @[Bitwise.scala 103:39]
+    node _T_63 = bits(_T_55, 5, 0) @[Bitwise.scala 102:28]
+    node _T_64 = shl(_T_63, 2) @[Bitwise.scala 102:47]
+    node _T_65 = xor(_T_55, _T_64) @[Bitwise.scala 102:21]
+    node _T_66 = shr(_T_62, 2) @[Bitwise.scala 103:21]
+    node _T_67 = and(_T_66, _T_65) @[Bitwise.scala 103:31]
+    node _T_68 = bits(_T_62, 5, 0) @[Bitwise.scala 103:46]
+    node _T_69 = shl(_T_68, 2) @[Bitwise.scala 103:65]
+    node _T_70 = not(_T_65) @[Bitwise.scala 103:77]
+    node _T_71 = and(_T_69, _T_70) @[Bitwise.scala 103:75]
+    node _T_72 = or(_T_67, _T_71) @[Bitwise.scala 103:39]
+    node _T_73 = bits(_T_65, 6, 0) @[Bitwise.scala 102:28]
+    node _T_74 = shl(_T_73, 1) @[Bitwise.scala 102:47]
+    node _T_75 = xor(_T_65, _T_74) @[Bitwise.scala 102:21]
+    node _T_76 = shr(_T_72, 1) @[Bitwise.scala 103:21]
+    node _T_77 = and(_T_76, _T_75) @[Bitwise.scala 103:31]
+    node _T_78 = bits(_T_72, 6, 0) @[Bitwise.scala 103:46]
+    node _T_79 = shl(_T_78, 1) @[Bitwise.scala 103:65]
+    node _T_80 = not(_T_75) @[Bitwise.scala 103:77]
+    node _T_81 = and(_T_79, _T_80) @[Bitwise.scala 103:75]
+    node _T_82 = or(_T_77, _T_81) @[Bitwise.scala 103:39]
+    node _T_83 = bits(stbuf_fwdbyteen_r, 1, 1) @[lsu_dccm_ctl.scala 138:95]
+    node _T_84 = bits(_T_83, 0, 0) @[lsu_dccm_ctl.scala 138:99]
+    node _T_85 = bits(stbuf_fwddata_r, 15, 8) @[lsu_dccm_ctl.scala 138:121]
+    node _T_86 = bits(io.addr_in_pic_r, 0, 0) @[lsu_dccm_ctl.scala 138:157]
+    node _T_87 = bits(picm_rd_data_r, 15, 8) @[lsu_dccm_ctl.scala 138:178]
+    node _T_88 = bits(io.addr_in_dccm_r, 0, 0) @[Bitwise.scala 72:15]
+    node _T_89 = mux(_T_88, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
+    node _T_90 = bits(dccm_rdata_corr_r, 15, 8) @[lsu_dccm_ctl.scala 138:238]
+    node _T_91 = and(_T_89, _T_90) @[lsu_dccm_ctl.scala 138:219]
+    node _T_92 = mux(_T_86, _T_87, _T_91) @[lsu_dccm_ctl.scala 138:139]
+    node _T_93 = mux(_T_84, _T_85, _T_92) @[lsu_dccm_ctl.scala 138:77]
+    node _T_94 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
+    node _T_95 = xor(UInt<8>("h0ff"), _T_94) @[Bitwise.scala 102:21]
+    node _T_96 = shr(_T_93, 4) @[Bitwise.scala 103:21]
+    node _T_97 = and(_T_96, _T_95) @[Bitwise.scala 103:31]
+    node _T_98 = bits(_T_93, 3, 0) @[Bitwise.scala 103:46]
+    node _T_99 = shl(_T_98, 4) @[Bitwise.scala 103:65]
+    node _T_100 = not(_T_95) @[Bitwise.scala 103:77]
+    node _T_101 = and(_T_99, _T_100) @[Bitwise.scala 103:75]
+    node _T_102 = or(_T_97, _T_101) @[Bitwise.scala 103:39]
+    node _T_103 = bits(_T_95, 5, 0) @[Bitwise.scala 102:28]
+    node _T_104 = shl(_T_103, 2) @[Bitwise.scala 102:47]
+    node _T_105 = xor(_T_95, _T_104) @[Bitwise.scala 102:21]
+    node _T_106 = shr(_T_102, 2) @[Bitwise.scala 103:21]
+    node _T_107 = and(_T_106, _T_105) @[Bitwise.scala 103:31]
+    node _T_108 = bits(_T_102, 5, 0) @[Bitwise.scala 103:46]
+    node _T_109 = shl(_T_108, 2) @[Bitwise.scala 103:65]
+    node _T_110 = not(_T_105) @[Bitwise.scala 103:77]
+    node _T_111 = and(_T_109, _T_110) @[Bitwise.scala 103:75]
+    node _T_112 = or(_T_107, _T_111) @[Bitwise.scala 103:39]
+    node _T_113 = bits(_T_105, 6, 0) @[Bitwise.scala 102:28]
+    node _T_114 = shl(_T_113, 1) @[Bitwise.scala 102:47]
+    node _T_115 = xor(_T_105, _T_114) @[Bitwise.scala 102:21]
+    node _T_116 = shr(_T_112, 1) @[Bitwise.scala 103:21]
+    node _T_117 = and(_T_116, _T_115) @[Bitwise.scala 103:31]
+    node _T_118 = bits(_T_112, 6, 0) @[Bitwise.scala 103:46]
+    node _T_119 = shl(_T_118, 1) @[Bitwise.scala 103:65]
+    node _T_120 = not(_T_115) @[Bitwise.scala 103:77]
+    node _T_121 = and(_T_119, _T_120) @[Bitwise.scala 103:75]
+    node _T_122 = or(_T_117, _T_121) @[Bitwise.scala 103:39]
+    node _T_123 = bits(stbuf_fwdbyteen_r, 2, 2) @[lsu_dccm_ctl.scala 138:95]
+    node _T_124 = bits(_T_123, 0, 0) @[lsu_dccm_ctl.scala 138:99]
+    node _T_125 = bits(stbuf_fwddata_r, 23, 16) @[lsu_dccm_ctl.scala 138:121]
+    node _T_126 = bits(io.addr_in_pic_r, 0, 0) @[lsu_dccm_ctl.scala 138:157]
+    node _T_127 = bits(picm_rd_data_r, 23, 16) @[lsu_dccm_ctl.scala 138:178]
+    node _T_128 = bits(io.addr_in_dccm_r, 0, 0) @[Bitwise.scala 72:15]
+    node _T_129 = mux(_T_128, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
+    node _T_130 = bits(dccm_rdata_corr_r, 23, 16) @[lsu_dccm_ctl.scala 138:238]
+    node _T_131 = and(_T_129, _T_130) @[lsu_dccm_ctl.scala 138:219]
+    node _T_132 = mux(_T_126, _T_127, _T_131) @[lsu_dccm_ctl.scala 138:139]
+    node _T_133 = mux(_T_124, _T_125, _T_132) @[lsu_dccm_ctl.scala 138:77]
+    node _T_134 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
+    node _T_135 = xor(UInt<8>("h0ff"), _T_134) @[Bitwise.scala 102:21]
+    node _T_136 = shr(_T_133, 4) @[Bitwise.scala 103:21]
+    node _T_137 = and(_T_136, _T_135) @[Bitwise.scala 103:31]
+    node _T_138 = bits(_T_133, 3, 0) @[Bitwise.scala 103:46]
+    node _T_139 = shl(_T_138, 4) @[Bitwise.scala 103:65]
+    node _T_140 = not(_T_135) @[Bitwise.scala 103:77]
+    node _T_141 = and(_T_139, _T_140) @[Bitwise.scala 103:75]
+    node _T_142 = or(_T_137, _T_141) @[Bitwise.scala 103:39]
+    node _T_143 = bits(_T_135, 5, 0) @[Bitwise.scala 102:28]
+    node _T_144 = shl(_T_143, 2) @[Bitwise.scala 102:47]
+    node _T_145 = xor(_T_135, _T_144) @[Bitwise.scala 102:21]
+    node _T_146 = shr(_T_142, 2) @[Bitwise.scala 103:21]
+    node _T_147 = and(_T_146, _T_145) @[Bitwise.scala 103:31]
+    node _T_148 = bits(_T_142, 5, 0) @[Bitwise.scala 103:46]
+    node _T_149 = shl(_T_148, 2) @[Bitwise.scala 103:65]
+    node _T_150 = not(_T_145) @[Bitwise.scala 103:77]
+    node _T_151 = and(_T_149, _T_150) @[Bitwise.scala 103:75]
+    node _T_152 = or(_T_147, _T_151) @[Bitwise.scala 103:39]
+    node _T_153 = bits(_T_145, 6, 0) @[Bitwise.scala 102:28]
+    node _T_154 = shl(_T_153, 1) @[Bitwise.scala 102:47]
+    node _T_155 = xor(_T_145, _T_154) @[Bitwise.scala 102:21]
+    node _T_156 = shr(_T_152, 1) @[Bitwise.scala 103:21]
+    node _T_157 = and(_T_156, _T_155) @[Bitwise.scala 103:31]
+    node _T_158 = bits(_T_152, 6, 0) @[Bitwise.scala 103:46]
+    node _T_159 = shl(_T_158, 1) @[Bitwise.scala 103:65]
+    node _T_160 = not(_T_155) @[Bitwise.scala 103:77]
+    node _T_161 = and(_T_159, _T_160) @[Bitwise.scala 103:75]
+    node _T_162 = or(_T_157, _T_161) @[Bitwise.scala 103:39]
+    node _T_163 = bits(stbuf_fwdbyteen_r, 3, 3) @[lsu_dccm_ctl.scala 138:95]
+    node _T_164 = bits(_T_163, 0, 0) @[lsu_dccm_ctl.scala 138:99]
+    node _T_165 = bits(stbuf_fwddata_r, 31, 24) @[lsu_dccm_ctl.scala 138:121]
+    node _T_166 = bits(io.addr_in_pic_r, 0, 0) @[lsu_dccm_ctl.scala 138:157]
+    node _T_167 = bits(picm_rd_data_r, 31, 24) @[lsu_dccm_ctl.scala 138:178]
+    node _T_168 = bits(io.addr_in_dccm_r, 0, 0) @[Bitwise.scala 72:15]
+    node _T_169 = mux(_T_168, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
+    node _T_170 = bits(dccm_rdata_corr_r, 31, 24) @[lsu_dccm_ctl.scala 138:238]
+    node _T_171 = and(_T_169, _T_170) @[lsu_dccm_ctl.scala 138:219]
+    node _T_172 = mux(_T_166, _T_167, _T_171) @[lsu_dccm_ctl.scala 138:139]
+    node _T_173 = mux(_T_164, _T_165, _T_172) @[lsu_dccm_ctl.scala 138:77]
+    node _T_174 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
+    node _T_175 = xor(UInt<8>("h0ff"), _T_174) @[Bitwise.scala 102:21]
+    node _T_176 = shr(_T_173, 4) @[Bitwise.scala 103:21]
+    node _T_177 = and(_T_176, _T_175) @[Bitwise.scala 103:31]
+    node _T_178 = bits(_T_173, 3, 0) @[Bitwise.scala 103:46]
+    node _T_179 = shl(_T_178, 4) @[Bitwise.scala 103:65]
+    node _T_180 = not(_T_175) @[Bitwise.scala 103:77]
+    node _T_181 = and(_T_179, _T_180) @[Bitwise.scala 103:75]
+    node _T_182 = or(_T_177, _T_181) @[Bitwise.scala 103:39]
+    node _T_183 = bits(_T_175, 5, 0) @[Bitwise.scala 102:28]
+    node _T_184 = shl(_T_183, 2) @[Bitwise.scala 102:47]
+    node _T_185 = xor(_T_175, _T_184) @[Bitwise.scala 102:21]
+    node _T_186 = shr(_T_182, 2) @[Bitwise.scala 103:21]
+    node _T_187 = and(_T_186, _T_185) @[Bitwise.scala 103:31]
+    node _T_188 = bits(_T_182, 5, 0) @[Bitwise.scala 103:46]
+    node _T_189 = shl(_T_188, 2) @[Bitwise.scala 103:65]
+    node _T_190 = not(_T_185) @[Bitwise.scala 103:77]
+    node _T_191 = and(_T_189, _T_190) @[Bitwise.scala 103:75]
+    node _T_192 = or(_T_187, _T_191) @[Bitwise.scala 103:39]
+    node _T_193 = bits(_T_185, 6, 0) @[Bitwise.scala 102:28]
+    node _T_194 = shl(_T_193, 1) @[Bitwise.scala 102:47]
+    node _T_195 = xor(_T_185, _T_194) @[Bitwise.scala 102:21]
+    node _T_196 = shr(_T_192, 1) @[Bitwise.scala 103:21]
+    node _T_197 = and(_T_196, _T_195) @[Bitwise.scala 103:31]
+    node _T_198 = bits(_T_192, 6, 0) @[Bitwise.scala 103:46]
+    node _T_199 = shl(_T_198, 1) @[Bitwise.scala 103:65]
+    node _T_200 = not(_T_195) @[Bitwise.scala 103:77]
+    node _T_201 = and(_T_199, _T_200) @[Bitwise.scala 103:75]
+    node _T_202 = or(_T_197, _T_201) @[Bitwise.scala 103:39]
+    node _T_203 = bits(stbuf_fwdbyteen_r, 4, 4) @[lsu_dccm_ctl.scala 138:95]
+    node _T_204 = bits(_T_203, 0, 0) @[lsu_dccm_ctl.scala 138:99]
+    node _T_205 = bits(stbuf_fwddata_r, 39, 32) @[lsu_dccm_ctl.scala 138:121]
+    node _T_206 = bits(io.addr_in_pic_r, 0, 0) @[lsu_dccm_ctl.scala 138:157]
+    node _T_207 = bits(picm_rd_data_r, 39, 32) @[lsu_dccm_ctl.scala 138:178]
+    node _T_208 = bits(io.addr_in_dccm_r, 0, 0) @[Bitwise.scala 72:15]
+    node _T_209 = mux(_T_208, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
+    node _T_210 = bits(dccm_rdata_corr_r, 39, 32) @[lsu_dccm_ctl.scala 138:238]
+    node _T_211 = and(_T_209, _T_210) @[lsu_dccm_ctl.scala 138:219]
+    node _T_212 = mux(_T_206, _T_207, _T_211) @[lsu_dccm_ctl.scala 138:139]
+    node _T_213 = mux(_T_204, _T_205, _T_212) @[lsu_dccm_ctl.scala 138:77]
+    node _T_214 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
+    node _T_215 = xor(UInt<8>("h0ff"), _T_214) @[Bitwise.scala 102:21]
+    node _T_216 = shr(_T_213, 4) @[Bitwise.scala 103:21]
+    node _T_217 = and(_T_216, _T_215) @[Bitwise.scala 103:31]
+    node _T_218 = bits(_T_213, 3, 0) @[Bitwise.scala 103:46]
+    node _T_219 = shl(_T_218, 4) @[Bitwise.scala 103:65]
+    node _T_220 = not(_T_215) @[Bitwise.scala 103:77]
+    node _T_221 = and(_T_219, _T_220) @[Bitwise.scala 103:75]
+    node _T_222 = or(_T_217, _T_221) @[Bitwise.scala 103:39]
+    node _T_223 = bits(_T_215, 5, 0) @[Bitwise.scala 102:28]
+    node _T_224 = shl(_T_223, 2) @[Bitwise.scala 102:47]
+    node _T_225 = xor(_T_215, _T_224) @[Bitwise.scala 102:21]
+    node _T_226 = shr(_T_222, 2) @[Bitwise.scala 103:21]
+    node _T_227 = and(_T_226, _T_225) @[Bitwise.scala 103:31]
+    node _T_228 = bits(_T_222, 5, 0) @[Bitwise.scala 103:46]
+    node _T_229 = shl(_T_228, 2) @[Bitwise.scala 103:65]
+    node _T_230 = not(_T_225) @[Bitwise.scala 103:77]
+    node _T_231 = and(_T_229, _T_230) @[Bitwise.scala 103:75]
+    node _T_232 = or(_T_227, _T_231) @[Bitwise.scala 103:39]
+    node _T_233 = bits(_T_225, 6, 0) @[Bitwise.scala 102:28]
+    node _T_234 = shl(_T_233, 1) @[Bitwise.scala 102:47]
+    node _T_235 = xor(_T_225, _T_234) @[Bitwise.scala 102:21]
+    node _T_236 = shr(_T_232, 1) @[Bitwise.scala 103:21]
+    node _T_237 = and(_T_236, _T_235) @[Bitwise.scala 103:31]
+    node _T_238 = bits(_T_232, 6, 0) @[Bitwise.scala 103:46]
+    node _T_239 = shl(_T_238, 1) @[Bitwise.scala 103:65]
+    node _T_240 = not(_T_235) @[Bitwise.scala 103:77]
+    node _T_241 = and(_T_239, _T_240) @[Bitwise.scala 103:75]
+    node _T_242 = or(_T_237, _T_241) @[Bitwise.scala 103:39]
+    node _T_243 = bits(stbuf_fwdbyteen_r, 5, 5) @[lsu_dccm_ctl.scala 138:95]
+    node _T_244 = bits(_T_243, 0, 0) @[lsu_dccm_ctl.scala 138:99]
+    node _T_245 = bits(stbuf_fwddata_r, 47, 40) @[lsu_dccm_ctl.scala 138:121]
+    node _T_246 = bits(io.addr_in_pic_r, 0, 0) @[lsu_dccm_ctl.scala 138:157]
+    node _T_247 = bits(picm_rd_data_r, 47, 40) @[lsu_dccm_ctl.scala 138:178]
+    node _T_248 = bits(io.addr_in_dccm_r, 0, 0) @[Bitwise.scala 72:15]
+    node _T_249 = mux(_T_248, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
+    node _T_250 = bits(dccm_rdata_corr_r, 47, 40) @[lsu_dccm_ctl.scala 138:238]
+    node _T_251 = and(_T_249, _T_250) @[lsu_dccm_ctl.scala 138:219]
+    node _T_252 = mux(_T_246, _T_247, _T_251) @[lsu_dccm_ctl.scala 138:139]
+    node _T_253 = mux(_T_244, _T_245, _T_252) @[lsu_dccm_ctl.scala 138:77]
+    node _T_254 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
+    node _T_255 = xor(UInt<8>("h0ff"), _T_254) @[Bitwise.scala 102:21]
+    node _T_256 = shr(_T_253, 4) @[Bitwise.scala 103:21]
+    node _T_257 = and(_T_256, _T_255) @[Bitwise.scala 103:31]
+    node _T_258 = bits(_T_253, 3, 0) @[Bitwise.scala 103:46]
+    node _T_259 = shl(_T_258, 4) @[Bitwise.scala 103:65]
+    node _T_260 = not(_T_255) @[Bitwise.scala 103:77]
+    node _T_261 = and(_T_259, _T_260) @[Bitwise.scala 103:75]
+    node _T_262 = or(_T_257, _T_261) @[Bitwise.scala 103:39]
+    node _T_263 = bits(_T_255, 5, 0) @[Bitwise.scala 102:28]
+    node _T_264 = shl(_T_263, 2) @[Bitwise.scala 102:47]
+    node _T_265 = xor(_T_255, _T_264) @[Bitwise.scala 102:21]
+    node _T_266 = shr(_T_262, 2) @[Bitwise.scala 103:21]
+    node _T_267 = and(_T_266, _T_265) @[Bitwise.scala 103:31]
+    node _T_268 = bits(_T_262, 5, 0) @[Bitwise.scala 103:46]
+    node _T_269 = shl(_T_268, 2) @[Bitwise.scala 103:65]
+    node _T_270 = not(_T_265) @[Bitwise.scala 103:77]
+    node _T_271 = and(_T_269, _T_270) @[Bitwise.scala 103:75]
+    node _T_272 = or(_T_267, _T_271) @[Bitwise.scala 103:39]
+    node _T_273 = bits(_T_265, 6, 0) @[Bitwise.scala 102:28]
+    node _T_274 = shl(_T_273, 1) @[Bitwise.scala 102:47]
+    node _T_275 = xor(_T_265, _T_274) @[Bitwise.scala 102:21]
+    node _T_276 = shr(_T_272, 1) @[Bitwise.scala 103:21]
+    node _T_277 = and(_T_276, _T_275) @[Bitwise.scala 103:31]
+    node _T_278 = bits(_T_272, 6, 0) @[Bitwise.scala 103:46]
+    node _T_279 = shl(_T_278, 1) @[Bitwise.scala 103:65]
+    node _T_280 = not(_T_275) @[Bitwise.scala 103:77]
+    node _T_281 = and(_T_279, _T_280) @[Bitwise.scala 103:75]
+    node _T_282 = or(_T_277, _T_281) @[Bitwise.scala 103:39]
+    node _T_283 = bits(stbuf_fwdbyteen_r, 6, 6) @[lsu_dccm_ctl.scala 138:95]
+    node _T_284 = bits(_T_283, 0, 0) @[lsu_dccm_ctl.scala 138:99]
+    node _T_285 = bits(stbuf_fwddata_r, 55, 48) @[lsu_dccm_ctl.scala 138:121]
+    node _T_286 = bits(io.addr_in_pic_r, 0, 0) @[lsu_dccm_ctl.scala 138:157]
+    node _T_287 = bits(picm_rd_data_r, 55, 48) @[lsu_dccm_ctl.scala 138:178]
+    node _T_288 = bits(io.addr_in_dccm_r, 0, 0) @[Bitwise.scala 72:15]
+    node _T_289 = mux(_T_288, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
+    node _T_290 = bits(dccm_rdata_corr_r, 55, 48) @[lsu_dccm_ctl.scala 138:238]
+    node _T_291 = and(_T_289, _T_290) @[lsu_dccm_ctl.scala 138:219]
+    node _T_292 = mux(_T_286, _T_287, _T_291) @[lsu_dccm_ctl.scala 138:139]
+    node _T_293 = mux(_T_284, _T_285, _T_292) @[lsu_dccm_ctl.scala 138:77]
+    node _T_294 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
+    node _T_295 = xor(UInt<8>("h0ff"), _T_294) @[Bitwise.scala 102:21]
+    node _T_296 = shr(_T_293, 4) @[Bitwise.scala 103:21]
+    node _T_297 = and(_T_296, _T_295) @[Bitwise.scala 103:31]
+    node _T_298 = bits(_T_293, 3, 0) @[Bitwise.scala 103:46]
+    node _T_299 = shl(_T_298, 4) @[Bitwise.scala 103:65]
+    node _T_300 = not(_T_295) @[Bitwise.scala 103:77]
+    node _T_301 = and(_T_299, _T_300) @[Bitwise.scala 103:75]
+    node _T_302 = or(_T_297, _T_301) @[Bitwise.scala 103:39]
+    node _T_303 = bits(_T_295, 5, 0) @[Bitwise.scala 102:28]
+    node _T_304 = shl(_T_303, 2) @[Bitwise.scala 102:47]
+    node _T_305 = xor(_T_295, _T_304) @[Bitwise.scala 102:21]
+    node _T_306 = shr(_T_302, 2) @[Bitwise.scala 103:21]
+    node _T_307 = and(_T_306, _T_305) @[Bitwise.scala 103:31]
+    node _T_308 = bits(_T_302, 5, 0) @[Bitwise.scala 103:46]
+    node _T_309 = shl(_T_308, 2) @[Bitwise.scala 103:65]
+    node _T_310 = not(_T_305) @[Bitwise.scala 103:77]
+    node _T_311 = and(_T_309, _T_310) @[Bitwise.scala 103:75]
+    node _T_312 = or(_T_307, _T_311) @[Bitwise.scala 103:39]
+    node _T_313 = bits(_T_305, 6, 0) @[Bitwise.scala 102:28]
+    node _T_314 = shl(_T_313, 1) @[Bitwise.scala 102:47]
+    node _T_315 = xor(_T_305, _T_314) @[Bitwise.scala 102:21]
+    node _T_316 = shr(_T_312, 1) @[Bitwise.scala 103:21]
+    node _T_317 = and(_T_316, _T_315) @[Bitwise.scala 103:31]
+    node _T_318 = bits(_T_312, 6, 0) @[Bitwise.scala 103:46]
+    node _T_319 = shl(_T_318, 1) @[Bitwise.scala 103:65]
+    node _T_320 = not(_T_315) @[Bitwise.scala 103:77]
+    node _T_321 = and(_T_319, _T_320) @[Bitwise.scala 103:75]
+    node _T_322 = or(_T_317, _T_321) @[Bitwise.scala 103:39]
+    node _T_323 = bits(stbuf_fwdbyteen_r, 7, 7) @[lsu_dccm_ctl.scala 138:95]
+    node _T_324 = bits(_T_323, 0, 0) @[lsu_dccm_ctl.scala 138:99]
+    node _T_325 = bits(stbuf_fwddata_r, 63, 56) @[lsu_dccm_ctl.scala 138:121]
+    node _T_326 = bits(io.addr_in_pic_r, 0, 0) @[lsu_dccm_ctl.scala 138:157]
+    node _T_327 = bits(picm_rd_data_r, 63, 56) @[lsu_dccm_ctl.scala 138:178]
+    node _T_328 = bits(io.addr_in_dccm_r, 0, 0) @[Bitwise.scala 72:15]
+    node _T_329 = mux(_T_328, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
+    node _T_330 = bits(dccm_rdata_corr_r, 63, 56) @[lsu_dccm_ctl.scala 138:238]
+    node _T_331 = and(_T_329, _T_330) @[lsu_dccm_ctl.scala 138:219]
+    node _T_332 = mux(_T_326, _T_327, _T_331) @[lsu_dccm_ctl.scala 138:139]
+    node _T_333 = mux(_T_324, _T_325, _T_332) @[lsu_dccm_ctl.scala 138:77]
+    node _T_334 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
+    node _T_335 = xor(UInt<8>("h0ff"), _T_334) @[Bitwise.scala 102:21]
+    node _T_336 = shr(_T_333, 4) @[Bitwise.scala 103:21]
+    node _T_337 = and(_T_336, _T_335) @[Bitwise.scala 103:31]
+    node _T_338 = bits(_T_333, 3, 0) @[Bitwise.scala 103:46]
+    node _T_339 = shl(_T_338, 4) @[Bitwise.scala 103:65]
+    node _T_340 = not(_T_335) @[Bitwise.scala 103:77]
+    node _T_341 = and(_T_339, _T_340) @[Bitwise.scala 103:75]
+    node _T_342 = or(_T_337, _T_341) @[Bitwise.scala 103:39]
+    node _T_343 = bits(_T_335, 5, 0) @[Bitwise.scala 102:28]
+    node _T_344 = shl(_T_343, 2) @[Bitwise.scala 102:47]
+    node _T_345 = xor(_T_335, _T_344) @[Bitwise.scala 102:21]
+    node _T_346 = shr(_T_342, 2) @[Bitwise.scala 103:21]
+    node _T_347 = and(_T_346, _T_345) @[Bitwise.scala 103:31]
+    node _T_348 = bits(_T_342, 5, 0) @[Bitwise.scala 103:46]
+    node _T_349 = shl(_T_348, 2) @[Bitwise.scala 103:65]
+    node _T_350 = not(_T_345) @[Bitwise.scala 103:77]
+    node _T_351 = and(_T_349, _T_350) @[Bitwise.scala 103:75]
+    node _T_352 = or(_T_347, _T_351) @[Bitwise.scala 103:39]
+    node _T_353 = bits(_T_345, 6, 0) @[Bitwise.scala 102:28]
+    node _T_354 = shl(_T_353, 1) @[Bitwise.scala 102:47]
+    node _T_355 = xor(_T_345, _T_354) @[Bitwise.scala 102:21]
+    node _T_356 = shr(_T_352, 1) @[Bitwise.scala 103:21]
+    node _T_357 = and(_T_356, _T_355) @[Bitwise.scala 103:31]
+    node _T_358 = bits(_T_352, 6, 0) @[Bitwise.scala 103:46]
+    node _T_359 = shl(_T_358, 1) @[Bitwise.scala 103:65]
+    node _T_360 = not(_T_355) @[Bitwise.scala 103:77]
+    node _T_361 = and(_T_359, _T_360) @[Bitwise.scala 103:75]
+    node _T_362 = or(_T_357, _T_361) @[Bitwise.scala 103:39]
+    wire _T_363 : UInt<8>[8] @[lsu_dccm_ctl.scala 138:61]
+    _T_363[0] <= _T_82 @[lsu_dccm_ctl.scala 138:61]
+    _T_363[1] <= _T_122 @[lsu_dccm_ctl.scala 138:61]
+    _T_363[2] <= _T_162 @[lsu_dccm_ctl.scala 138:61]
+    _T_363[3] <= _T_202 @[lsu_dccm_ctl.scala 138:61]
+    _T_363[4] <= _T_242 @[lsu_dccm_ctl.scala 138:61]
+    _T_363[5] <= _T_282 @[lsu_dccm_ctl.scala 138:61]
+    _T_363[6] <= _T_322 @[lsu_dccm_ctl.scala 138:61]
+    _T_363[7] <= _T_362 @[lsu_dccm_ctl.scala 138:61]
+    node _T_364 = cat(_T_363[6], _T_363[7]) @[Cat.scala 29:58]
+    node _T_365 = cat(_T_363[4], _T_363[5]) @[Cat.scala 29:58]
+    node _T_366 = cat(_T_365, _T_364) @[Cat.scala 29:58]
+    node _T_367 = cat(_T_363[2], _T_363[3]) @[Cat.scala 29:58]
+    node _T_368 = cat(_T_363[0], _T_363[1]) @[Cat.scala 29:58]
+    node _T_369 = cat(_T_368, _T_367) @[Cat.scala 29:58]
+    node _T_370 = cat(_T_369, _T_366) @[Cat.scala 29:58]
+    node _T_371 = shl(UInt<32>("h0ffffffff"), 32) @[Bitwise.scala 102:47]
+    node _T_372 = xor(UInt<64>("h0ffffffffffffffff"), _T_371) @[Bitwise.scala 102:21]
+    node _T_373 = shr(_T_370, 32) @[Bitwise.scala 103:21]
+    node _T_374 = and(_T_373, _T_372) @[Bitwise.scala 103:31]
+    node _T_375 = bits(_T_370, 31, 0) @[Bitwise.scala 103:46]
+    node _T_376 = shl(_T_375, 32) @[Bitwise.scala 103:65]
+    node _T_377 = not(_T_372) @[Bitwise.scala 103:77]
+    node _T_378 = and(_T_376, _T_377) @[Bitwise.scala 103:75]
+    node _T_379 = or(_T_374, _T_378) @[Bitwise.scala 103:39]
+    node _T_380 = bits(_T_372, 47, 0) @[Bitwise.scala 102:28]
+    node _T_381 = shl(_T_380, 16) @[Bitwise.scala 102:47]
+    node _T_382 = xor(_T_372, _T_381) @[Bitwise.scala 102:21]
+    node _T_383 = shr(_T_379, 16) @[Bitwise.scala 103:21]
+    node _T_384 = and(_T_383, _T_382) @[Bitwise.scala 103:31]
+    node _T_385 = bits(_T_379, 47, 0) @[Bitwise.scala 103:46]
+    node _T_386 = shl(_T_385, 16) @[Bitwise.scala 103:65]
+    node _T_387 = not(_T_382) @[Bitwise.scala 103:77]
+    node _T_388 = and(_T_386, _T_387) @[Bitwise.scala 103:75]
+    node _T_389 = or(_T_384, _T_388) @[Bitwise.scala 103:39]
+    node _T_390 = bits(_T_382, 55, 0) @[Bitwise.scala 102:28]
+    node _T_391 = shl(_T_390, 8) @[Bitwise.scala 102:47]
+    node _T_392 = xor(_T_382, _T_391) @[Bitwise.scala 102:21]
+    node _T_393 = shr(_T_389, 8) @[Bitwise.scala 103:21]
+    node _T_394 = and(_T_393, _T_392) @[Bitwise.scala 103:31]
+    node _T_395 = bits(_T_389, 55, 0) @[Bitwise.scala 103:46]
+    node _T_396 = shl(_T_395, 8) @[Bitwise.scala 103:65]
+    node _T_397 = not(_T_392) @[Bitwise.scala 103:77]
+    node _T_398 = and(_T_396, _T_397) @[Bitwise.scala 103:75]
+    node _T_399 = or(_T_394, _T_398) @[Bitwise.scala 103:39]
+    node _T_400 = bits(_T_392, 59, 0) @[Bitwise.scala 102:28]
+    node _T_401 = shl(_T_400, 4) @[Bitwise.scala 102:47]
+    node _T_402 = xor(_T_392, _T_401) @[Bitwise.scala 102:21]
+    node _T_403 = shr(_T_399, 4) @[Bitwise.scala 103:21]
+    node _T_404 = and(_T_403, _T_402) @[Bitwise.scala 103:31]
+    node _T_405 = bits(_T_399, 59, 0) @[Bitwise.scala 103:46]
+    node _T_406 = shl(_T_405, 4) @[Bitwise.scala 103:65]
+    node _T_407 = not(_T_402) @[Bitwise.scala 103:77]
+    node _T_408 = and(_T_406, _T_407) @[Bitwise.scala 103:75]
+    node _T_409 = or(_T_404, _T_408) @[Bitwise.scala 103:39]
+    node _T_410 = bits(_T_402, 61, 0) @[Bitwise.scala 102:28]
+    node _T_411 = shl(_T_410, 2) @[Bitwise.scala 102:47]
+    node _T_412 = xor(_T_402, _T_411) @[Bitwise.scala 102:21]
+    node _T_413 = shr(_T_409, 2) @[Bitwise.scala 103:21]
+    node _T_414 = and(_T_413, _T_412) @[Bitwise.scala 103:31]
+    node _T_415 = bits(_T_409, 61, 0) @[Bitwise.scala 103:46]
+    node _T_416 = shl(_T_415, 2) @[Bitwise.scala 103:65]
+    node _T_417 = not(_T_412) @[Bitwise.scala 103:77]
+    node _T_418 = and(_T_416, _T_417) @[Bitwise.scala 103:75]
+    node _T_419 = or(_T_414, _T_418) @[Bitwise.scala 103:39]
+    node _T_420 = bits(_T_412, 62, 0) @[Bitwise.scala 102:28]
+    node _T_421 = shl(_T_420, 1) @[Bitwise.scala 102:47]
+    node _T_422 = xor(_T_412, _T_421) @[Bitwise.scala 102:21]
+    node _T_423 = shr(_T_419, 1) @[Bitwise.scala 103:21]
+    node _T_424 = and(_T_423, _T_422) @[Bitwise.scala 103:31]
+    node _T_425 = bits(_T_419, 62, 0) @[Bitwise.scala 103:46]
+    node _T_426 = shl(_T_425, 1) @[Bitwise.scala 103:65]
+    node _T_427 = not(_T_422) @[Bitwise.scala 103:77]
+    node _T_428 = and(_T_426, _T_427) @[Bitwise.scala 103:75]
+    node _T_429 = or(_T_424, _T_428) @[Bitwise.scala 103:39]
+    lsu_rdata_corr_r <= _T_429 @[lsu_dccm_ctl.scala 138:27]
+    node _T_430 = bits(stbuf_fwdbyteen_r, 0, 0) @[lsu_dccm_ctl.scala 139:95]
+    node _T_431 = bits(_T_430, 0, 0) @[lsu_dccm_ctl.scala 139:99]
+    node _T_432 = bits(stbuf_fwddata_r, 7, 0) @[lsu_dccm_ctl.scala 139:121]
+    node _T_433 = bits(io.addr_in_pic_r, 0, 0) @[lsu_dccm_ctl.scala 139:157]
+    node _T_434 = bits(picm_rd_data_r, 7, 0) @[lsu_dccm_ctl.scala 139:178]
+    node _T_435 = bits(io.addr_in_dccm_r, 0, 0) @[Bitwise.scala 72:15]
+    node _T_436 = mux(_T_435, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
+    node _T_437 = bits(dccm_rdata_r, 7, 0) @[lsu_dccm_ctl.scala 139:233]
+    node _T_438 = and(_T_436, _T_437) @[lsu_dccm_ctl.scala 139:219]
+    node _T_439 = mux(_T_433, _T_434, _T_438) @[lsu_dccm_ctl.scala 139:139]
+    node _T_440 = mux(_T_431, _T_432, _T_439) @[lsu_dccm_ctl.scala 139:77]
+    node _T_441 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
+    node _T_442 = xor(UInt<8>("h0ff"), _T_441) @[Bitwise.scala 102:21]
+    node _T_443 = shr(_T_440, 4) @[Bitwise.scala 103:21]
+    node _T_444 = and(_T_443, _T_442) @[Bitwise.scala 103:31]
+    node _T_445 = bits(_T_440, 3, 0) @[Bitwise.scala 103:46]
+    node _T_446 = shl(_T_445, 4) @[Bitwise.scala 103:65]
+    node _T_447 = not(_T_442) @[Bitwise.scala 103:77]
+    node _T_448 = and(_T_446, _T_447) @[Bitwise.scala 103:75]
+    node _T_449 = or(_T_444, _T_448) @[Bitwise.scala 103:39]
+    node _T_450 = bits(_T_442, 5, 0) @[Bitwise.scala 102:28]
+    node _T_451 = shl(_T_450, 2) @[Bitwise.scala 102:47]
+    node _T_452 = xor(_T_442, _T_451) @[Bitwise.scala 102:21]
+    node _T_453 = shr(_T_449, 2) @[Bitwise.scala 103:21]
+    node _T_454 = and(_T_453, _T_452) @[Bitwise.scala 103:31]
+    node _T_455 = bits(_T_449, 5, 0) @[Bitwise.scala 103:46]
+    node _T_456 = shl(_T_455, 2) @[Bitwise.scala 103:65]
+    node _T_457 = not(_T_452) @[Bitwise.scala 103:77]
+    node _T_458 = and(_T_456, _T_457) @[Bitwise.scala 103:75]
+    node _T_459 = or(_T_454, _T_458) @[Bitwise.scala 103:39]
+    node _T_460 = bits(_T_452, 6, 0) @[Bitwise.scala 102:28]
+    node _T_461 = shl(_T_460, 1) @[Bitwise.scala 102:47]
+    node _T_462 = xor(_T_452, _T_461) @[Bitwise.scala 102:21]
+    node _T_463 = shr(_T_459, 1) @[Bitwise.scala 103:21]
+    node _T_464 = and(_T_463, _T_462) @[Bitwise.scala 103:31]
+    node _T_465 = bits(_T_459, 6, 0) @[Bitwise.scala 103:46]
+    node _T_466 = shl(_T_465, 1) @[Bitwise.scala 103:65]
+    node _T_467 = not(_T_462) @[Bitwise.scala 103:77]
+    node _T_468 = and(_T_466, _T_467) @[Bitwise.scala 103:75]
+    node _T_469 = or(_T_464, _T_468) @[Bitwise.scala 103:39]
+    node _T_470 = bits(stbuf_fwdbyteen_r, 1, 1) @[lsu_dccm_ctl.scala 139:95]
+    node _T_471 = bits(_T_470, 0, 0) @[lsu_dccm_ctl.scala 139:99]
+    node _T_472 = bits(stbuf_fwddata_r, 15, 8) @[lsu_dccm_ctl.scala 139:121]
+    node _T_473 = bits(io.addr_in_pic_r, 0, 0) @[lsu_dccm_ctl.scala 139:157]
+    node _T_474 = bits(picm_rd_data_r, 15, 8) @[lsu_dccm_ctl.scala 139:178]
+    node _T_475 = bits(io.addr_in_dccm_r, 0, 0) @[Bitwise.scala 72:15]
+    node _T_476 = mux(_T_475, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
+    node _T_477 = bits(dccm_rdata_r, 15, 8) @[lsu_dccm_ctl.scala 139:233]
+    node _T_478 = and(_T_476, _T_477) @[lsu_dccm_ctl.scala 139:219]
+    node _T_479 = mux(_T_473, _T_474, _T_478) @[lsu_dccm_ctl.scala 139:139]
+    node _T_480 = mux(_T_471, _T_472, _T_479) @[lsu_dccm_ctl.scala 139:77]
+    node _T_481 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
+    node _T_482 = xor(UInt<8>("h0ff"), _T_481) @[Bitwise.scala 102:21]
+    node _T_483 = shr(_T_480, 4) @[Bitwise.scala 103:21]
+    node _T_484 = and(_T_483, _T_482) @[Bitwise.scala 103:31]
+    node _T_485 = bits(_T_480, 3, 0) @[Bitwise.scala 103:46]
+    node _T_486 = shl(_T_485, 4) @[Bitwise.scala 103:65]
+    node _T_487 = not(_T_482) @[Bitwise.scala 103:77]
+    node _T_488 = and(_T_486, _T_487) @[Bitwise.scala 103:75]
+    node _T_489 = or(_T_484, _T_488) @[Bitwise.scala 103:39]
+    node _T_490 = bits(_T_482, 5, 0) @[Bitwise.scala 102:28]
+    node _T_491 = shl(_T_490, 2) @[Bitwise.scala 102:47]
+    node _T_492 = xor(_T_482, _T_491) @[Bitwise.scala 102:21]
+    node _T_493 = shr(_T_489, 2) @[Bitwise.scala 103:21]
+    node _T_494 = and(_T_493, _T_492) @[Bitwise.scala 103:31]
+    node _T_495 = bits(_T_489, 5, 0) @[Bitwise.scala 103:46]
+    node _T_496 = shl(_T_495, 2) @[Bitwise.scala 103:65]
+    node _T_497 = not(_T_492) @[Bitwise.scala 103:77]
+    node _T_498 = and(_T_496, _T_497) @[Bitwise.scala 103:75]
+    node _T_499 = or(_T_494, _T_498) @[Bitwise.scala 103:39]
+    node _T_500 = bits(_T_492, 6, 0) @[Bitwise.scala 102:28]
+    node _T_501 = shl(_T_500, 1) @[Bitwise.scala 102:47]
+    node _T_502 = xor(_T_492, _T_501) @[Bitwise.scala 102:21]
+    node _T_503 = shr(_T_499, 1) @[Bitwise.scala 103:21]
+    node _T_504 = and(_T_503, _T_502) @[Bitwise.scala 103:31]
+    node _T_505 = bits(_T_499, 6, 0) @[Bitwise.scala 103:46]
+    node _T_506 = shl(_T_505, 1) @[Bitwise.scala 103:65]
+    node _T_507 = not(_T_502) @[Bitwise.scala 103:77]
+    node _T_508 = and(_T_506, _T_507) @[Bitwise.scala 103:75]
+    node _T_509 = or(_T_504, _T_508) @[Bitwise.scala 103:39]
+    node _T_510 = bits(stbuf_fwdbyteen_r, 2, 2) @[lsu_dccm_ctl.scala 139:95]
+    node _T_511 = bits(_T_510, 0, 0) @[lsu_dccm_ctl.scala 139:99]
+    node _T_512 = bits(stbuf_fwddata_r, 23, 16) @[lsu_dccm_ctl.scala 139:121]
+    node _T_513 = bits(io.addr_in_pic_r, 0, 0) @[lsu_dccm_ctl.scala 139:157]
+    node _T_514 = bits(picm_rd_data_r, 23, 16) @[lsu_dccm_ctl.scala 139:178]
+    node _T_515 = bits(io.addr_in_dccm_r, 0, 0) @[Bitwise.scala 72:15]
+    node _T_516 = mux(_T_515, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
+    node _T_517 = bits(dccm_rdata_r, 23, 16) @[lsu_dccm_ctl.scala 139:233]
+    node _T_518 = and(_T_516, _T_517) @[lsu_dccm_ctl.scala 139:219]
+    node _T_519 = mux(_T_513, _T_514, _T_518) @[lsu_dccm_ctl.scala 139:139]
+    node _T_520 = mux(_T_511, _T_512, _T_519) @[lsu_dccm_ctl.scala 139:77]
+    node _T_521 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
+    node _T_522 = xor(UInt<8>("h0ff"), _T_521) @[Bitwise.scala 102:21]
+    node _T_523 = shr(_T_520, 4) @[Bitwise.scala 103:21]
+    node _T_524 = and(_T_523, _T_522) @[Bitwise.scala 103:31]
+    node _T_525 = bits(_T_520, 3, 0) @[Bitwise.scala 103:46]
+    node _T_526 = shl(_T_525, 4) @[Bitwise.scala 103:65]
+    node _T_527 = not(_T_522) @[Bitwise.scala 103:77]
+    node _T_528 = and(_T_526, _T_527) @[Bitwise.scala 103:75]
+    node _T_529 = or(_T_524, _T_528) @[Bitwise.scala 103:39]
+    node _T_530 = bits(_T_522, 5, 0) @[Bitwise.scala 102:28]
+    node _T_531 = shl(_T_530, 2) @[Bitwise.scala 102:47]
+    node _T_532 = xor(_T_522, _T_531) @[Bitwise.scala 102:21]
+    node _T_533 = shr(_T_529, 2) @[Bitwise.scala 103:21]
+    node _T_534 = and(_T_533, _T_532) @[Bitwise.scala 103:31]
+    node _T_535 = bits(_T_529, 5, 0) @[Bitwise.scala 103:46]
+    node _T_536 = shl(_T_535, 2) @[Bitwise.scala 103:65]
+    node _T_537 = not(_T_532) @[Bitwise.scala 103:77]
+    node _T_538 = and(_T_536, _T_537) @[Bitwise.scala 103:75]
+    node _T_539 = or(_T_534, _T_538) @[Bitwise.scala 103:39]
+    node _T_540 = bits(_T_532, 6, 0) @[Bitwise.scala 102:28]
+    node _T_541 = shl(_T_540, 1) @[Bitwise.scala 102:47]
+    node _T_542 = xor(_T_532, _T_541) @[Bitwise.scala 102:21]
+    node _T_543 = shr(_T_539, 1) @[Bitwise.scala 103:21]
+    node _T_544 = and(_T_543, _T_542) @[Bitwise.scala 103:31]
+    node _T_545 = bits(_T_539, 6, 0) @[Bitwise.scala 103:46]
+    node _T_546 = shl(_T_545, 1) @[Bitwise.scala 103:65]
+    node _T_547 = not(_T_542) @[Bitwise.scala 103:77]
+    node _T_548 = and(_T_546, _T_547) @[Bitwise.scala 103:75]
+    node _T_549 = or(_T_544, _T_548) @[Bitwise.scala 103:39]
+    node _T_550 = bits(stbuf_fwdbyteen_r, 3, 3) @[lsu_dccm_ctl.scala 139:95]
+    node _T_551 = bits(_T_550, 0, 0) @[lsu_dccm_ctl.scala 139:99]
+    node _T_552 = bits(stbuf_fwddata_r, 31, 24) @[lsu_dccm_ctl.scala 139:121]
+    node _T_553 = bits(io.addr_in_pic_r, 0, 0) @[lsu_dccm_ctl.scala 139:157]
+    node _T_554 = bits(picm_rd_data_r, 31, 24) @[lsu_dccm_ctl.scala 139:178]
+    node _T_555 = bits(io.addr_in_dccm_r, 0, 0) @[Bitwise.scala 72:15]
+    node _T_556 = mux(_T_555, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
+    node _T_557 = bits(dccm_rdata_r, 31, 24) @[lsu_dccm_ctl.scala 139:233]
+    node _T_558 = and(_T_556, _T_557) @[lsu_dccm_ctl.scala 139:219]
+    node _T_559 = mux(_T_553, _T_554, _T_558) @[lsu_dccm_ctl.scala 139:139]
+    node _T_560 = mux(_T_551, _T_552, _T_559) @[lsu_dccm_ctl.scala 139:77]
+    node _T_561 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
+    node _T_562 = xor(UInt<8>("h0ff"), _T_561) @[Bitwise.scala 102:21]
+    node _T_563 = shr(_T_560, 4) @[Bitwise.scala 103:21]
+    node _T_564 = and(_T_563, _T_562) @[Bitwise.scala 103:31]
+    node _T_565 = bits(_T_560, 3, 0) @[Bitwise.scala 103:46]
+    node _T_566 = shl(_T_565, 4) @[Bitwise.scala 103:65]
+    node _T_567 = not(_T_562) @[Bitwise.scala 103:77]
+    node _T_568 = and(_T_566, _T_567) @[Bitwise.scala 103:75]
+    node _T_569 = or(_T_564, _T_568) @[Bitwise.scala 103:39]
+    node _T_570 = bits(_T_562, 5, 0) @[Bitwise.scala 102:28]
+    node _T_571 = shl(_T_570, 2) @[Bitwise.scala 102:47]
+    node _T_572 = xor(_T_562, _T_571) @[Bitwise.scala 102:21]
+    node _T_573 = shr(_T_569, 2) @[Bitwise.scala 103:21]
+    node _T_574 = and(_T_573, _T_572) @[Bitwise.scala 103:31]
+    node _T_575 = bits(_T_569, 5, 0) @[Bitwise.scala 103:46]
+    node _T_576 = shl(_T_575, 2) @[Bitwise.scala 103:65]
+    node _T_577 = not(_T_572) @[Bitwise.scala 103:77]
+    node _T_578 = and(_T_576, _T_577) @[Bitwise.scala 103:75]
+    node _T_579 = or(_T_574, _T_578) @[Bitwise.scala 103:39]
+    node _T_580 = bits(_T_572, 6, 0) @[Bitwise.scala 102:28]
+    node _T_581 = shl(_T_580, 1) @[Bitwise.scala 102:47]
+    node _T_582 = xor(_T_572, _T_581) @[Bitwise.scala 102:21]
+    node _T_583 = shr(_T_579, 1) @[Bitwise.scala 103:21]
+    node _T_584 = and(_T_583, _T_582) @[Bitwise.scala 103:31]
+    node _T_585 = bits(_T_579, 6, 0) @[Bitwise.scala 103:46]
+    node _T_586 = shl(_T_585, 1) @[Bitwise.scala 103:65]
+    node _T_587 = not(_T_582) @[Bitwise.scala 103:77]
+    node _T_588 = and(_T_586, _T_587) @[Bitwise.scala 103:75]
+    node _T_589 = or(_T_584, _T_588) @[Bitwise.scala 103:39]
+    node _T_590 = bits(stbuf_fwdbyteen_r, 4, 4) @[lsu_dccm_ctl.scala 139:95]
+    node _T_591 = bits(_T_590, 0, 0) @[lsu_dccm_ctl.scala 139:99]
+    node _T_592 = bits(stbuf_fwddata_r, 39, 32) @[lsu_dccm_ctl.scala 139:121]
+    node _T_593 = bits(io.addr_in_pic_r, 0, 0) @[lsu_dccm_ctl.scala 139:157]
+    node _T_594 = bits(picm_rd_data_r, 39, 32) @[lsu_dccm_ctl.scala 139:178]
+    node _T_595 = bits(io.addr_in_dccm_r, 0, 0) @[Bitwise.scala 72:15]
+    node _T_596 = mux(_T_595, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
+    node _T_597 = bits(dccm_rdata_r, 39, 32) @[lsu_dccm_ctl.scala 139:233]
+    node _T_598 = and(_T_596, _T_597) @[lsu_dccm_ctl.scala 139:219]
+    node _T_599 = mux(_T_593, _T_594, _T_598) @[lsu_dccm_ctl.scala 139:139]
+    node _T_600 = mux(_T_591, _T_592, _T_599) @[lsu_dccm_ctl.scala 139:77]
+    node _T_601 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
+    node _T_602 = xor(UInt<8>("h0ff"), _T_601) @[Bitwise.scala 102:21]
+    node _T_603 = shr(_T_600, 4) @[Bitwise.scala 103:21]
+    node _T_604 = and(_T_603, _T_602) @[Bitwise.scala 103:31]
+    node _T_605 = bits(_T_600, 3, 0) @[Bitwise.scala 103:46]
+    node _T_606 = shl(_T_605, 4) @[Bitwise.scala 103:65]
+    node _T_607 = not(_T_602) @[Bitwise.scala 103:77]
+    node _T_608 = and(_T_606, _T_607) @[Bitwise.scala 103:75]
+    node _T_609 = or(_T_604, _T_608) @[Bitwise.scala 103:39]
+    node _T_610 = bits(_T_602, 5, 0) @[Bitwise.scala 102:28]
+    node _T_611 = shl(_T_610, 2) @[Bitwise.scala 102:47]
+    node _T_612 = xor(_T_602, _T_611) @[Bitwise.scala 102:21]
+    node _T_613 = shr(_T_609, 2) @[Bitwise.scala 103:21]
+    node _T_614 = and(_T_613, _T_612) @[Bitwise.scala 103:31]
+    node _T_615 = bits(_T_609, 5, 0) @[Bitwise.scala 103:46]
+    node _T_616 = shl(_T_615, 2) @[Bitwise.scala 103:65]
+    node _T_617 = not(_T_612) @[Bitwise.scala 103:77]
+    node _T_618 = and(_T_616, _T_617) @[Bitwise.scala 103:75]
+    node _T_619 = or(_T_614, _T_618) @[Bitwise.scala 103:39]
+    node _T_620 = bits(_T_612, 6, 0) @[Bitwise.scala 102:28]
+    node _T_621 = shl(_T_620, 1) @[Bitwise.scala 102:47]
+    node _T_622 = xor(_T_612, _T_621) @[Bitwise.scala 102:21]
+    node _T_623 = shr(_T_619, 1) @[Bitwise.scala 103:21]
+    node _T_624 = and(_T_623, _T_622) @[Bitwise.scala 103:31]
+    node _T_625 = bits(_T_619, 6, 0) @[Bitwise.scala 103:46]
+    node _T_626 = shl(_T_625, 1) @[Bitwise.scala 103:65]
+    node _T_627 = not(_T_622) @[Bitwise.scala 103:77]
+    node _T_628 = and(_T_626, _T_627) @[Bitwise.scala 103:75]
+    node _T_629 = or(_T_624, _T_628) @[Bitwise.scala 103:39]
+    node _T_630 = bits(stbuf_fwdbyteen_r, 5, 5) @[lsu_dccm_ctl.scala 139:95]
+    node _T_631 = bits(_T_630, 0, 0) @[lsu_dccm_ctl.scala 139:99]
+    node _T_632 = bits(stbuf_fwddata_r, 47, 40) @[lsu_dccm_ctl.scala 139:121]
+    node _T_633 = bits(io.addr_in_pic_r, 0, 0) @[lsu_dccm_ctl.scala 139:157]
+    node _T_634 = bits(picm_rd_data_r, 47, 40) @[lsu_dccm_ctl.scala 139:178]
+    node _T_635 = bits(io.addr_in_dccm_r, 0, 0) @[Bitwise.scala 72:15]
+    node _T_636 = mux(_T_635, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
+    node _T_637 = bits(dccm_rdata_r, 47, 40) @[lsu_dccm_ctl.scala 139:233]
+    node _T_638 = and(_T_636, _T_637) @[lsu_dccm_ctl.scala 139:219]
+    node _T_639 = mux(_T_633, _T_634, _T_638) @[lsu_dccm_ctl.scala 139:139]
+    node _T_640 = mux(_T_631, _T_632, _T_639) @[lsu_dccm_ctl.scala 139:77]
+    node _T_641 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
+    node _T_642 = xor(UInt<8>("h0ff"), _T_641) @[Bitwise.scala 102:21]
+    node _T_643 = shr(_T_640, 4) @[Bitwise.scala 103:21]
+    node _T_644 = and(_T_643, _T_642) @[Bitwise.scala 103:31]
+    node _T_645 = bits(_T_640, 3, 0) @[Bitwise.scala 103:46]
+    node _T_646 = shl(_T_645, 4) @[Bitwise.scala 103:65]
+    node _T_647 = not(_T_642) @[Bitwise.scala 103:77]
+    node _T_648 = and(_T_646, _T_647) @[Bitwise.scala 103:75]
+    node _T_649 = or(_T_644, _T_648) @[Bitwise.scala 103:39]
+    node _T_650 = bits(_T_642, 5, 0) @[Bitwise.scala 102:28]
+    node _T_651 = shl(_T_650, 2) @[Bitwise.scala 102:47]
+    node _T_652 = xor(_T_642, _T_651) @[Bitwise.scala 102:21]
+    node _T_653 = shr(_T_649, 2) @[Bitwise.scala 103:21]
+    node _T_654 = and(_T_653, _T_652) @[Bitwise.scala 103:31]
+    node _T_655 = bits(_T_649, 5, 0) @[Bitwise.scala 103:46]
+    node _T_656 = shl(_T_655, 2) @[Bitwise.scala 103:65]
+    node _T_657 = not(_T_652) @[Bitwise.scala 103:77]
+    node _T_658 = and(_T_656, _T_657) @[Bitwise.scala 103:75]
+    node _T_659 = or(_T_654, _T_658) @[Bitwise.scala 103:39]
+    node _T_660 = bits(_T_652, 6, 0) @[Bitwise.scala 102:28]
+    node _T_661 = shl(_T_660, 1) @[Bitwise.scala 102:47]
+    node _T_662 = xor(_T_652, _T_661) @[Bitwise.scala 102:21]
+    node _T_663 = shr(_T_659, 1) @[Bitwise.scala 103:21]
+    node _T_664 = and(_T_663, _T_662) @[Bitwise.scala 103:31]
+    node _T_665 = bits(_T_659, 6, 0) @[Bitwise.scala 103:46]
+    node _T_666 = shl(_T_665, 1) @[Bitwise.scala 103:65]
+    node _T_667 = not(_T_662) @[Bitwise.scala 103:77]
+    node _T_668 = and(_T_666, _T_667) @[Bitwise.scala 103:75]
+    node _T_669 = or(_T_664, _T_668) @[Bitwise.scala 103:39]
+    node _T_670 = bits(stbuf_fwdbyteen_r, 6, 6) @[lsu_dccm_ctl.scala 139:95]
+    node _T_671 = bits(_T_670, 0, 0) @[lsu_dccm_ctl.scala 139:99]
+    node _T_672 = bits(stbuf_fwddata_r, 55, 48) @[lsu_dccm_ctl.scala 139:121]
+    node _T_673 = bits(io.addr_in_pic_r, 0, 0) @[lsu_dccm_ctl.scala 139:157]
+    node _T_674 = bits(picm_rd_data_r, 55, 48) @[lsu_dccm_ctl.scala 139:178]
+    node _T_675 = bits(io.addr_in_dccm_r, 0, 0) @[Bitwise.scala 72:15]
+    node _T_676 = mux(_T_675, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
+    node _T_677 = bits(dccm_rdata_r, 55, 48) @[lsu_dccm_ctl.scala 139:233]
+    node _T_678 = and(_T_676, _T_677) @[lsu_dccm_ctl.scala 139:219]
+    node _T_679 = mux(_T_673, _T_674, _T_678) @[lsu_dccm_ctl.scala 139:139]
+    node _T_680 = mux(_T_671, _T_672, _T_679) @[lsu_dccm_ctl.scala 139:77]
+    node _T_681 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
+    node _T_682 = xor(UInt<8>("h0ff"), _T_681) @[Bitwise.scala 102:21]
+    node _T_683 = shr(_T_680, 4) @[Bitwise.scala 103:21]
+    node _T_684 = and(_T_683, _T_682) @[Bitwise.scala 103:31]
+    node _T_685 = bits(_T_680, 3, 0) @[Bitwise.scala 103:46]
+    node _T_686 = shl(_T_685, 4) @[Bitwise.scala 103:65]
+    node _T_687 = not(_T_682) @[Bitwise.scala 103:77]
+    node _T_688 = and(_T_686, _T_687) @[Bitwise.scala 103:75]
+    node _T_689 = or(_T_684, _T_688) @[Bitwise.scala 103:39]
+    node _T_690 = bits(_T_682, 5, 0) @[Bitwise.scala 102:28]
+    node _T_691 = shl(_T_690, 2) @[Bitwise.scala 102:47]
+    node _T_692 = xor(_T_682, _T_691) @[Bitwise.scala 102:21]
+    node _T_693 = shr(_T_689, 2) @[Bitwise.scala 103:21]
+    node _T_694 = and(_T_693, _T_692) @[Bitwise.scala 103:31]
+    node _T_695 = bits(_T_689, 5, 0) @[Bitwise.scala 103:46]
+    node _T_696 = shl(_T_695, 2) @[Bitwise.scala 103:65]
+    node _T_697 = not(_T_692) @[Bitwise.scala 103:77]
+    node _T_698 = and(_T_696, _T_697) @[Bitwise.scala 103:75]
+    node _T_699 = or(_T_694, _T_698) @[Bitwise.scala 103:39]
+    node _T_700 = bits(_T_692, 6, 0) @[Bitwise.scala 102:28]
+    node _T_701 = shl(_T_700, 1) @[Bitwise.scala 102:47]
+    node _T_702 = xor(_T_692, _T_701) @[Bitwise.scala 102:21]
+    node _T_703 = shr(_T_699, 1) @[Bitwise.scala 103:21]
+    node _T_704 = and(_T_703, _T_702) @[Bitwise.scala 103:31]
+    node _T_705 = bits(_T_699, 6, 0) @[Bitwise.scala 103:46]
+    node _T_706 = shl(_T_705, 1) @[Bitwise.scala 103:65]
+    node _T_707 = not(_T_702) @[Bitwise.scala 103:77]
+    node _T_708 = and(_T_706, _T_707) @[Bitwise.scala 103:75]
+    node _T_709 = or(_T_704, _T_708) @[Bitwise.scala 103:39]
+    node _T_710 = bits(stbuf_fwdbyteen_r, 7, 7) @[lsu_dccm_ctl.scala 139:95]
+    node _T_711 = bits(_T_710, 0, 0) @[lsu_dccm_ctl.scala 139:99]
+    node _T_712 = bits(stbuf_fwddata_r, 63, 56) @[lsu_dccm_ctl.scala 139:121]
+    node _T_713 = bits(io.addr_in_pic_r, 0, 0) @[lsu_dccm_ctl.scala 139:157]
+    node _T_714 = bits(picm_rd_data_r, 63, 56) @[lsu_dccm_ctl.scala 139:178]
+    node _T_715 = bits(io.addr_in_dccm_r, 0, 0) @[Bitwise.scala 72:15]
+    node _T_716 = mux(_T_715, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
+    node _T_717 = bits(dccm_rdata_r, 63, 56) @[lsu_dccm_ctl.scala 139:233]
+    node _T_718 = and(_T_716, _T_717) @[lsu_dccm_ctl.scala 139:219]
+    node _T_719 = mux(_T_713, _T_714, _T_718) @[lsu_dccm_ctl.scala 139:139]
+    node _T_720 = mux(_T_711, _T_712, _T_719) @[lsu_dccm_ctl.scala 139:77]
+    node _T_721 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
+    node _T_722 = xor(UInt<8>("h0ff"), _T_721) @[Bitwise.scala 102:21]
+    node _T_723 = shr(_T_720, 4) @[Bitwise.scala 103:21]
+    node _T_724 = and(_T_723, _T_722) @[Bitwise.scala 103:31]
+    node _T_725 = bits(_T_720, 3, 0) @[Bitwise.scala 103:46]
+    node _T_726 = shl(_T_725, 4) @[Bitwise.scala 103:65]
+    node _T_727 = not(_T_722) @[Bitwise.scala 103:77]
+    node _T_728 = and(_T_726, _T_727) @[Bitwise.scala 103:75]
+    node _T_729 = or(_T_724, _T_728) @[Bitwise.scala 103:39]
+    node _T_730 = bits(_T_722, 5, 0) @[Bitwise.scala 102:28]
+    node _T_731 = shl(_T_730, 2) @[Bitwise.scala 102:47]
+    node _T_732 = xor(_T_722, _T_731) @[Bitwise.scala 102:21]
+    node _T_733 = shr(_T_729, 2) @[Bitwise.scala 103:21]
+    node _T_734 = and(_T_733, _T_732) @[Bitwise.scala 103:31]
+    node _T_735 = bits(_T_729, 5, 0) @[Bitwise.scala 103:46]
+    node _T_736 = shl(_T_735, 2) @[Bitwise.scala 103:65]
+    node _T_737 = not(_T_732) @[Bitwise.scala 103:77]
+    node _T_738 = and(_T_736, _T_737) @[Bitwise.scala 103:75]
+    node _T_739 = or(_T_734, _T_738) @[Bitwise.scala 103:39]
+    node _T_740 = bits(_T_732, 6, 0) @[Bitwise.scala 102:28]
+    node _T_741 = shl(_T_740, 1) @[Bitwise.scala 102:47]
+    node _T_742 = xor(_T_732, _T_741) @[Bitwise.scala 102:21]
+    node _T_743 = shr(_T_739, 1) @[Bitwise.scala 103:21]
+    node _T_744 = and(_T_743, _T_742) @[Bitwise.scala 103:31]
+    node _T_745 = bits(_T_739, 6, 0) @[Bitwise.scala 103:46]
+    node _T_746 = shl(_T_745, 1) @[Bitwise.scala 103:65]
+    node _T_747 = not(_T_742) @[Bitwise.scala 103:77]
+    node _T_748 = and(_T_746, _T_747) @[Bitwise.scala 103:75]
+    node _T_749 = or(_T_744, _T_748) @[Bitwise.scala 103:39]
+    wire _T_750 : UInt<8>[8] @[lsu_dccm_ctl.scala 139:61]
+    _T_750[0] <= _T_469 @[lsu_dccm_ctl.scala 139:61]
+    _T_750[1] <= _T_509 @[lsu_dccm_ctl.scala 139:61]
+    _T_750[2] <= _T_549 @[lsu_dccm_ctl.scala 139:61]
+    _T_750[3] <= _T_589 @[lsu_dccm_ctl.scala 139:61]
+    _T_750[4] <= _T_629 @[lsu_dccm_ctl.scala 139:61]
+    _T_750[5] <= _T_669 @[lsu_dccm_ctl.scala 139:61]
+    _T_750[6] <= _T_709 @[lsu_dccm_ctl.scala 139:61]
+    _T_750[7] <= _T_749 @[lsu_dccm_ctl.scala 139:61]
+    node _T_751 = cat(_T_750[6], _T_750[7]) @[Cat.scala 29:58]
+    node _T_752 = cat(_T_750[4], _T_750[5]) @[Cat.scala 29:58]
+    node _T_753 = cat(_T_752, _T_751) @[Cat.scala 29:58]
+    node _T_754 = cat(_T_750[2], _T_750[3]) @[Cat.scala 29:58]
+    node _T_755 = cat(_T_750[0], _T_750[1]) @[Cat.scala 29:58]
+    node _T_756 = cat(_T_755, _T_754) @[Cat.scala 29:58]
+    node _T_757 = cat(_T_756, _T_753) @[Cat.scala 29:58]
+    node _T_758 = shl(UInt<32>("h0ffffffff"), 32) @[Bitwise.scala 102:47]
+    node _T_759 = xor(UInt<64>("h0ffffffffffffffff"), _T_758) @[Bitwise.scala 102:21]
+    node _T_760 = shr(_T_757, 32) @[Bitwise.scala 103:21]
+    node _T_761 = and(_T_760, _T_759) @[Bitwise.scala 103:31]
+    node _T_762 = bits(_T_757, 31, 0) @[Bitwise.scala 103:46]
+    node _T_763 = shl(_T_762, 32) @[Bitwise.scala 103:65]
+    node _T_764 = not(_T_759) @[Bitwise.scala 103:77]
+    node _T_765 = and(_T_763, _T_764) @[Bitwise.scala 103:75]
+    node _T_766 = or(_T_761, _T_765) @[Bitwise.scala 103:39]
+    node _T_767 = bits(_T_759, 47, 0) @[Bitwise.scala 102:28]
+    node _T_768 = shl(_T_767, 16) @[Bitwise.scala 102:47]
+    node _T_769 = xor(_T_759, _T_768) @[Bitwise.scala 102:21]
+    node _T_770 = shr(_T_766, 16) @[Bitwise.scala 103:21]
+    node _T_771 = and(_T_770, _T_769) @[Bitwise.scala 103:31]
+    node _T_772 = bits(_T_766, 47, 0) @[Bitwise.scala 103:46]
+    node _T_773 = shl(_T_772, 16) @[Bitwise.scala 103:65]
+    node _T_774 = not(_T_769) @[Bitwise.scala 103:77]
+    node _T_775 = and(_T_773, _T_774) @[Bitwise.scala 103:75]
+    node _T_776 = or(_T_771, _T_775) @[Bitwise.scala 103:39]
+    node _T_777 = bits(_T_769, 55, 0) @[Bitwise.scala 102:28]
+    node _T_778 = shl(_T_777, 8) @[Bitwise.scala 102:47]
+    node _T_779 = xor(_T_769, _T_778) @[Bitwise.scala 102:21]
+    node _T_780 = shr(_T_776, 8) @[Bitwise.scala 103:21]
+    node _T_781 = and(_T_780, _T_779) @[Bitwise.scala 103:31]
+    node _T_782 = bits(_T_776, 55, 0) @[Bitwise.scala 103:46]
+    node _T_783 = shl(_T_782, 8) @[Bitwise.scala 103:65]
+    node _T_784 = not(_T_779) @[Bitwise.scala 103:77]
+    node _T_785 = and(_T_783, _T_784) @[Bitwise.scala 103:75]
+    node _T_786 = or(_T_781, _T_785) @[Bitwise.scala 103:39]
+    node _T_787 = bits(_T_779, 59, 0) @[Bitwise.scala 102:28]
+    node _T_788 = shl(_T_787, 4) @[Bitwise.scala 102:47]
+    node _T_789 = xor(_T_779, _T_788) @[Bitwise.scala 102:21]
+    node _T_790 = shr(_T_786, 4) @[Bitwise.scala 103:21]
+    node _T_791 = and(_T_790, _T_789) @[Bitwise.scala 103:31]
+    node _T_792 = bits(_T_786, 59, 0) @[Bitwise.scala 103:46]
+    node _T_793 = shl(_T_792, 4) @[Bitwise.scala 103:65]
+    node _T_794 = not(_T_789) @[Bitwise.scala 103:77]
+    node _T_795 = and(_T_793, _T_794) @[Bitwise.scala 103:75]
+    node _T_796 = or(_T_791, _T_795) @[Bitwise.scala 103:39]
+    node _T_797 = bits(_T_789, 61, 0) @[Bitwise.scala 102:28]
+    node _T_798 = shl(_T_797, 2) @[Bitwise.scala 102:47]
+    node _T_799 = xor(_T_789, _T_798) @[Bitwise.scala 102:21]
+    node _T_800 = shr(_T_796, 2) @[Bitwise.scala 103:21]
+    node _T_801 = and(_T_800, _T_799) @[Bitwise.scala 103:31]
+    node _T_802 = bits(_T_796, 61, 0) @[Bitwise.scala 103:46]
+    node _T_803 = shl(_T_802, 2) @[Bitwise.scala 103:65]
+    node _T_804 = not(_T_799) @[Bitwise.scala 103:77]
+    node _T_805 = and(_T_803, _T_804) @[Bitwise.scala 103:75]
+    node _T_806 = or(_T_801, _T_805) @[Bitwise.scala 103:39]
+    node _T_807 = bits(_T_799, 62, 0) @[Bitwise.scala 102:28]
+    node _T_808 = shl(_T_807, 1) @[Bitwise.scala 102:47]
+    node _T_809 = xor(_T_799, _T_808) @[Bitwise.scala 102:21]
+    node _T_810 = shr(_T_806, 1) @[Bitwise.scala 103:21]
+    node _T_811 = and(_T_810, _T_809) @[Bitwise.scala 103:31]
+    node _T_812 = bits(_T_806, 62, 0) @[Bitwise.scala 103:46]
+    node _T_813 = shl(_T_812, 1) @[Bitwise.scala 103:65]
+    node _T_814 = not(_T_809) @[Bitwise.scala 103:77]
+    node _T_815 = and(_T_813, _T_814) @[Bitwise.scala 103:75]
+    node _T_816 = or(_T_811, _T_815) @[Bitwise.scala 103:39]
+    lsu_rdata_r <= _T_816 @[lsu_dccm_ctl.scala 139:27]
+    node _T_817 = bits(io.lsu_addr_r, 1, 0) @[lsu_dccm_ctl.scala 140:61]
+    node _T_818 = mul(UInt<4>("h08"), _T_817) @[lsu_dccm_ctl.scala 140:47]
+    node _T_819 = dshr(lsu_rdata_r, _T_818) @[lsu_dccm_ctl.scala 140:41]
+    io.lsu_ld_data_r <= _T_819 @[lsu_dccm_ctl.scala 140:27]
+    node _T_820 = bits(io.lsu_addr_r, 1, 0) @[lsu_dccm_ctl.scala 141:67]
+    node _T_821 = mul(UInt<4>("h08"), _T_820) @[lsu_dccm_ctl.scala 141:53]
+    node _T_822 = dshr(lsu_rdata_corr_r, _T_821) @[lsu_dccm_ctl.scala 141:47]
+    io.lsu_ld_data_corr_r <= _T_822 @[lsu_dccm_ctl.scala 141:27]
+    node _T_823 = bits(io.lsu_addr_d, 15, 2) @[lsu_dccm_ctl.scala 163:44]
+    node _T_824 = bits(io.lsu_addr_r, 15, 2) @[lsu_dccm_ctl.scala 163:77]
+    node _T_825 = eq(_T_823, _T_824) @[lsu_dccm_ctl.scala 163:60]
+    node _T_826 = bits(io.end_addr_d, 15, 2) @[lsu_dccm_ctl.scala 163:117]
+    node _T_827 = bits(io.lsu_addr_r, 15, 2) @[lsu_dccm_ctl.scala 163:150]
+    node _T_828 = eq(_T_826, _T_827) @[lsu_dccm_ctl.scala 163:133]
+    node _T_829 = or(_T_825, _T_828) @[lsu_dccm_ctl.scala 163:101]
+    node _T_830 = and(_T_829, io.lsu_pkt_d.valid) @[lsu_dccm_ctl.scala 163:175]
+    node _T_831 = and(_T_830, io.lsu_pkt_d.bits.store) @[lsu_dccm_ctl.scala 163:196]
+    node _T_832 = and(_T_831, io.lsu_pkt_d.bits.dma) @[lsu_dccm_ctl.scala 163:222]
+    node _T_833 = and(_T_832, io.addr_in_dccm_d) @[lsu_dccm_ctl.scala 163:246]
+    node _T_834 = bits(io.lsu_addr_m, 15, 2) @[lsu_dccm_ctl.scala 164:21]
+    node _T_835 = bits(io.lsu_addr_r, 15, 2) @[lsu_dccm_ctl.scala 164:54]
+    node _T_836 = eq(_T_834, _T_835) @[lsu_dccm_ctl.scala 164:37]
+    node _T_837 = bits(io.end_addr_m, 15, 2) @[lsu_dccm_ctl.scala 164:94]
+    node _T_838 = bits(io.lsu_addr_r, 15, 2) @[lsu_dccm_ctl.scala 164:127]
+    node _T_839 = eq(_T_837, _T_838) @[lsu_dccm_ctl.scala 164:110]
+    node _T_840 = or(_T_836, _T_839) @[lsu_dccm_ctl.scala 164:78]
+    node _T_841 = and(_T_840, io.lsu_pkt_m.valid) @[lsu_dccm_ctl.scala 164:152]
+    node _T_842 = and(_T_841, io.lsu_pkt_m.bits.store) @[lsu_dccm_ctl.scala 164:173]
+    node _T_843 = and(_T_842, io.lsu_pkt_m.bits.dma) @[lsu_dccm_ctl.scala 164:199]
+    node _T_844 = and(_T_843, io.addr_in_dccm_m) @[lsu_dccm_ctl.scala 164:223]
+    node kill_ecc_corr_lo_r = or(_T_833, _T_844) @[lsu_dccm_ctl.scala 163:267]
+    node _T_845 = bits(io.lsu_addr_d, 15, 2) @[lsu_dccm_ctl.scala 166:44]
+    node _T_846 = bits(io.end_addr_r, 15, 2) @[lsu_dccm_ctl.scala 166:77]
+    node _T_847 = eq(_T_845, _T_846) @[lsu_dccm_ctl.scala 166:60]
+    node _T_848 = bits(io.end_addr_d, 15, 2) @[lsu_dccm_ctl.scala 166:117]
+    node _T_849 = bits(io.end_addr_r, 15, 2) @[lsu_dccm_ctl.scala 166:150]
+    node _T_850 = eq(_T_848, _T_849) @[lsu_dccm_ctl.scala 166:133]
+    node _T_851 = or(_T_847, _T_850) @[lsu_dccm_ctl.scala 166:101]
+    node _T_852 = and(_T_851, io.lsu_pkt_d.valid) @[lsu_dccm_ctl.scala 166:175]
+    node _T_853 = and(_T_852, io.lsu_pkt_d.bits.store) @[lsu_dccm_ctl.scala 166:196]
+    node _T_854 = and(_T_853, io.lsu_pkt_d.bits.dma) @[lsu_dccm_ctl.scala 166:222]
+    node _T_855 = and(_T_854, io.addr_in_dccm_d) @[lsu_dccm_ctl.scala 166:246]
+    node _T_856 = bits(io.lsu_addr_m, 15, 2) @[lsu_dccm_ctl.scala 167:21]
+    node _T_857 = bits(io.end_addr_r, 15, 2) @[lsu_dccm_ctl.scala 167:54]
+    node _T_858 = eq(_T_856, _T_857) @[lsu_dccm_ctl.scala 167:37]
+    node _T_859 = bits(io.end_addr_m, 15, 2) @[lsu_dccm_ctl.scala 167:94]
+    node _T_860 = bits(io.end_addr_r, 15, 2) @[lsu_dccm_ctl.scala 167:127]
+    node _T_861 = eq(_T_859, _T_860) @[lsu_dccm_ctl.scala 167:110]
+    node _T_862 = or(_T_858, _T_861) @[lsu_dccm_ctl.scala 167:78]
+    node _T_863 = and(_T_862, io.lsu_pkt_m.valid) @[lsu_dccm_ctl.scala 167:152]
+    node _T_864 = and(_T_863, io.lsu_pkt_m.bits.store) @[lsu_dccm_ctl.scala 167:173]
+    node _T_865 = and(_T_864, io.lsu_pkt_m.bits.dma) @[lsu_dccm_ctl.scala 167:199]
+    node _T_866 = and(_T_865, io.addr_in_dccm_m) @[lsu_dccm_ctl.scala 167:223]
+    node kill_ecc_corr_hi_r = or(_T_855, _T_866) @[lsu_dccm_ctl.scala 166:267]
+    node _T_867 = and(io.lsu_pkt_r.bits.load, io.single_ecc_error_lo_r) @[lsu_dccm_ctl.scala 169:60]
+    node _T_868 = eq(io.lsu_raw_fwd_lo_r, UInt<1>("h00")) @[lsu_dccm_ctl.scala 169:89]
+    node ld_single_ecc_error_lo_r = and(_T_867, _T_868) @[lsu_dccm_ctl.scala 169:87]
+    node _T_869 = and(io.lsu_pkt_r.bits.load, io.single_ecc_error_hi_r) @[lsu_dccm_ctl.scala 170:60]
+    node _T_870 = eq(io.lsu_raw_fwd_hi_r, UInt<1>("h00")) @[lsu_dccm_ctl.scala 170:89]
+    node ld_single_ecc_error_hi_r = and(_T_869, _T_870) @[lsu_dccm_ctl.scala 170:87]
+    node _T_871 = or(ld_single_ecc_error_lo_r, ld_single_ecc_error_hi_r) @[lsu_dccm_ctl.scala 171:63]
+    node _T_872 = eq(io.lsu_double_ecc_error_r, UInt<1>("h00")) @[lsu_dccm_ctl.scala 171:93]
+    node _T_873 = and(_T_871, _T_872) @[lsu_dccm_ctl.scala 171:91]
+    io.ld_single_ecc_error_r <= _T_873 @[lsu_dccm_ctl.scala 171:34]
+    node _T_874 = or(io.lsu_commit_r, io.lsu_pkt_r.bits.dma) @[lsu_dccm_ctl.scala 172:81]
+    node _T_875 = and(ld_single_ecc_error_lo_r, _T_874) @[lsu_dccm_ctl.scala 172:62]
+    node _T_876 = eq(kill_ecc_corr_lo_r, UInt<1>("h00")) @[lsu_dccm_ctl.scala 172:108]
+    node ld_single_ecc_error_lo_r_ns = and(_T_875, _T_876) @[lsu_dccm_ctl.scala 172:106]
+    node _T_877 = or(io.lsu_commit_r, io.lsu_pkt_r.bits.dma) @[lsu_dccm_ctl.scala 173:81]
+    node _T_878 = and(ld_single_ecc_error_hi_r, _T_877) @[lsu_dccm_ctl.scala 173:62]
+    node _T_879 = eq(kill_ecc_corr_hi_r, UInt<1>("h00")) @[lsu_dccm_ctl.scala 173:108]
+    node ld_single_ecc_error_hi_r_ns = and(_T_878, _T_879) @[lsu_dccm_ctl.scala 173:106]
+    node _T_880 = or(io.lsu_pkt_d.bits.word, io.lsu_pkt_d.bits.dword) @[lsu_dccm_ctl.scala 175:125]
+    node _T_881 = eq(_T_880, UInt<1>("h00")) @[lsu_dccm_ctl.scala 175:100]
+    node _T_882 = bits(io.lsu_addr_d, 1, 0) @[lsu_dccm_ctl.scala 175:168]
+    node _T_883 = neq(_T_882, UInt<2>("h00")) @[lsu_dccm_ctl.scala 175:174]
+    node _T_884 = or(_T_881, _T_883) @[lsu_dccm_ctl.scala 175:152]
+    node _T_885 = and(io.lsu_pkt_d.bits.store, _T_884) @[lsu_dccm_ctl.scala 175:97]
+    node _T_886 = or(io.lsu_pkt_d.bits.load, _T_885) @[lsu_dccm_ctl.scala 175:70]
+    node _T_887 = and(io.lsu_pkt_d.valid, _T_886) @[lsu_dccm_ctl.scala 175:44]
+    node lsu_dccm_rden_d = and(_T_887, io.addr_in_dccm_d) @[lsu_dccm_ctl.scala 175:191]
+    node _T_888 = or(ld_single_ecc_error_lo_r_ff, ld_single_ecc_error_hi_r_ff) @[lsu_dccm_ctl.scala 178:63]
+    node _T_889 = eq(lsu_double_ecc_error_r_ff, UInt<1>("h00")) @[lsu_dccm_ctl.scala 178:96]
+    node _T_890 = and(_T_888, _T_889) @[lsu_dccm_ctl.scala 178:94]
+    io.ld_single_ecc_error_r_ff <= _T_890 @[lsu_dccm_ctl.scala 178:31]
+    node _T_891 = or(lsu_dccm_rden_d, io.dma_dccm_wen) @[lsu_dccm_ctl.scala 179:75]
+    node _T_892 = or(_T_891, io.ld_single_ecc_error_r_ff) @[lsu_dccm_ctl.scala 179:93]
+    node _T_893 = eq(_T_892, UInt<1>("h00")) @[lsu_dccm_ctl.scala 179:57]
+    node _T_894 = bits(io.stbuf_addr_any, 3, 2) @[lsu_dccm_ctl.scala 180:44]
+    node _T_895 = bits(io.lsu_addr_d, 3, 2) @[lsu_dccm_ctl.scala 180:112]
+    node _T_896 = eq(_T_894, _T_895) @[lsu_dccm_ctl.scala 180:95]
+    node _T_897 = bits(io.stbuf_addr_any, 3, 2) @[lsu_dccm_ctl.scala 181:25]
+    node _T_898 = bits(io.end_addr_d, 3, 2) @[lsu_dccm_ctl.scala 181:93]
+    node _T_899 = eq(_T_897, _T_898) @[lsu_dccm_ctl.scala 181:76]
+    node _T_900 = or(_T_896, _T_899) @[lsu_dccm_ctl.scala 180:171]
+    node _T_901 = eq(_T_900, UInt<1>("h00")) @[lsu_dccm_ctl.scala 180:24]
+    node _T_902 = and(lsu_dccm_rden_d, _T_901) @[lsu_dccm_ctl.scala 180:22]
+    node _T_903 = or(_T_893, _T_902) @[lsu_dccm_ctl.scala 179:124]
+    node _T_904 = and(io.stbuf_reqvld_any, _T_903) @[lsu_dccm_ctl.scala 179:54]
+    io.lsu_stbuf_commit_any <= _T_904 @[lsu_dccm_ctl.scala 179:31]
+    node _T_905 = or(io.dma_dccm_wen, io.lsu_stbuf_commit_any) @[lsu_dccm_ctl.scala 185:41]
+    node _T_906 = or(_T_905, io.ld_single_ecc_error_r_ff) @[lsu_dccm_ctl.scala 185:67]
+    io.dccm.wren <= _T_906 @[lsu_dccm_ctl.scala 185:22]
+    node _T_907 = and(lsu_dccm_rden_d, io.addr_in_dccm_d) @[lsu_dccm_ctl.scala 186:41]
+    io.dccm.rden <= _T_907 @[lsu_dccm_ctl.scala 186:22]
+    node _T_908 = bits(io.ld_single_ecc_error_r_ff, 0, 0) @[lsu_dccm_ctl.scala 188:57]
+    node _T_909 = eq(ld_single_ecc_error_lo_r_ff, UInt<1>("h01")) @[lsu_dccm_ctl.scala 189:36]
+    node _T_910 = bits(ld_sec_addr_lo_r_ff, 15, 0) @[lsu_dccm_ctl.scala 189:62]
+    node _T_911 = bits(ld_sec_addr_hi_r_ff, 15, 0) @[lsu_dccm_ctl.scala 189:97]
+    node _T_912 = mux(_T_909, _T_910, _T_911) @[lsu_dccm_ctl.scala 189:8]
+    node _T_913 = bits(io.dma_dccm_wen, 0, 0) @[lsu_dccm_ctl.scala 190:25]
+    node _T_914 = bits(io.lsu_addr_d, 15, 0) @[lsu_dccm_ctl.scala 190:45]
+    node _T_915 = bits(io.stbuf_addr_any, 15, 0) @[lsu_dccm_ctl.scala 190:78]
+    node _T_916 = mux(_T_913, _T_914, _T_915) @[lsu_dccm_ctl.scala 190:8]
+    node _T_917 = mux(_T_908, _T_912, _T_916) @[lsu_dccm_ctl.scala 188:28]
+    io.dccm.wr_addr_lo <= _T_917 @[lsu_dccm_ctl.scala 188:22]
+    node _T_918 = bits(io.ld_single_ecc_error_r_ff, 0, 0) @[lsu_dccm_ctl.scala 192:57]
+    node _T_919 = eq(ld_single_ecc_error_hi_r_ff, UInt<1>("h01")) @[lsu_dccm_ctl.scala 193:36]
+    node _T_920 = bits(ld_sec_addr_hi_r_ff, 15, 0) @[lsu_dccm_ctl.scala 193:63]
+    node _T_921 = bits(ld_sec_addr_lo_r_ff, 15, 0) @[lsu_dccm_ctl.scala 193:99]
+    node _T_922 = mux(_T_919, _T_920, _T_921) @[lsu_dccm_ctl.scala 193:8]
+    node _T_923 = bits(io.dma_dccm_wen, 0, 0) @[lsu_dccm_ctl.scala 194:25]
+    node _T_924 = bits(io.end_addr_d, 15, 0) @[lsu_dccm_ctl.scala 194:46]
+    node _T_925 = bits(io.stbuf_addr_any, 15, 0) @[lsu_dccm_ctl.scala 194:79]
+    node _T_926 = mux(_T_923, _T_924, _T_925) @[lsu_dccm_ctl.scala 194:8]
+    node _T_927 = mux(_T_918, _T_922, _T_926) @[lsu_dccm_ctl.scala 192:28]
+    io.dccm.wr_addr_hi <= _T_927 @[lsu_dccm_ctl.scala 192:22]
+    node _T_928 = bits(io.lsu_addr_d, 15, 0) @[lsu_dccm_ctl.scala 196:38]
+    io.dccm.rd_addr_lo <= _T_928 @[lsu_dccm_ctl.scala 196:22]
+    node _T_929 = bits(io.end_addr_d, 15, 0) @[lsu_dccm_ctl.scala 197:38]
+    io.dccm.rd_addr_hi <= _T_929 @[lsu_dccm_ctl.scala 197:22]
+    node _T_930 = bits(io.ld_single_ecc_error_r_ff, 0, 0) @[lsu_dccm_ctl.scala 199:57]
+    node _T_931 = eq(ld_single_ecc_error_lo_r_ff, UInt<1>("h01")) @[lsu_dccm_ctl.scala 200:36]
+    node _T_932 = bits(io.sec_data_ecc_lo_r_ff, 6, 0) @[lsu_dccm_ctl.scala 200:70]
+    node _T_933 = bits(io.sec_data_lo_r_ff, 31, 0) @[lsu_dccm_ctl.scala 200:110]
+    node _T_934 = cat(_T_932, _T_933) @[Cat.scala 29:58]
+    node _T_935 = bits(io.sec_data_ecc_hi_r_ff, 6, 0) @[lsu_dccm_ctl.scala 201:34]
+    node _T_936 = bits(io.sec_data_hi_r_ff, 31, 0) @[lsu_dccm_ctl.scala 201:74]
+    node _T_937 = cat(_T_935, _T_936) @[Cat.scala 29:58]
+    node _T_938 = mux(_T_931, _T_934, _T_937) @[lsu_dccm_ctl.scala 200:8]
+    node _T_939 = bits(io.dma_dccm_wen, 0, 0) @[lsu_dccm_ctl.scala 202:25]
+    node _T_940 = bits(io.dma_dccm_wdata_ecc_lo, 6, 0) @[lsu_dccm_ctl.scala 202:60]
+    node _T_941 = bits(io.dma_dccm_wdata_lo, 31, 0) @[lsu_dccm_ctl.scala 202:101]
+    node _T_942 = cat(_T_940, _T_941) @[Cat.scala 29:58]
+    node _T_943 = bits(io.stbuf_ecc_any, 6, 0) @[lsu_dccm_ctl.scala 203:27]
+    node _T_944 = bits(io.stbuf_data_any, 31, 0) @[lsu_dccm_ctl.scala 203:65]
+    node _T_945 = cat(_T_943, _T_944) @[Cat.scala 29:58]
+    node _T_946 = mux(_T_939, _T_942, _T_945) @[lsu_dccm_ctl.scala 202:8]
+    node _T_947 = mux(_T_930, _T_938, _T_946) @[lsu_dccm_ctl.scala 199:28]
+    io.dccm.wr_data_lo <= _T_947 @[lsu_dccm_ctl.scala 199:22]
+    node _T_948 = bits(io.ld_single_ecc_error_r_ff, 0, 0) @[lsu_dccm_ctl.scala 205:57]
+    node _T_949 = eq(ld_single_ecc_error_hi_r_ff, UInt<1>("h01")) @[lsu_dccm_ctl.scala 206:36]
+    node _T_950 = bits(io.sec_data_ecc_hi_r_ff, 6, 0) @[lsu_dccm_ctl.scala 206:71]
+    node _T_951 = bits(io.sec_data_hi_r_ff, 31, 0) @[lsu_dccm_ctl.scala 206:111]
+    node _T_952 = cat(_T_950, _T_951) @[Cat.scala 29:58]
+    node _T_953 = bits(io.sec_data_ecc_lo_r_ff, 6, 0) @[lsu_dccm_ctl.scala 207:34]
+    node _T_954 = bits(io.sec_data_lo_r_ff, 31, 0) @[lsu_dccm_ctl.scala 207:74]
+    node _T_955 = cat(_T_953, _T_954) @[Cat.scala 29:58]
+    node _T_956 = mux(_T_949, _T_952, _T_955) @[lsu_dccm_ctl.scala 206:8]
+    node _T_957 = bits(io.dma_dccm_wen, 0, 0) @[lsu_dccm_ctl.scala 208:25]
+    node _T_958 = bits(io.dma_dccm_wdata_ecc_hi, 6, 0) @[lsu_dccm_ctl.scala 208:61]
+    node _T_959 = bits(io.dma_dccm_wdata_hi, 31, 0) @[lsu_dccm_ctl.scala 208:102]
+    node _T_960 = cat(_T_958, _T_959) @[Cat.scala 29:58]
+    node _T_961 = bits(io.stbuf_ecc_any, 6, 0) @[lsu_dccm_ctl.scala 209:27]
+    node _T_962 = bits(io.stbuf_data_any, 31, 0) @[lsu_dccm_ctl.scala 209:65]
+    node _T_963 = cat(_T_961, _T_962) @[Cat.scala 29:58]
+    node _T_964 = mux(_T_957, _T_960, _T_963) @[lsu_dccm_ctl.scala 208:8]
+    node _T_965 = mux(_T_948, _T_956, _T_964) @[lsu_dccm_ctl.scala 205:28]
+    io.dccm.wr_data_hi <= _T_965 @[lsu_dccm_ctl.scala 205:22]
+    node _T_966 = bits(io.lsu_pkt_m.bits.store, 0, 0) @[Bitwise.scala 72:15]
+    node _T_967 = mux(_T_966, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
+    node _T_968 = bits(io.lsu_pkt_m.bits.by, 0, 0) @[Bitwise.scala 72:15]
+    node _T_969 = mux(_T_968, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
+    node _T_970 = and(_T_969, UInt<4>("h01")) @[lsu_dccm_ctl.scala 212:94]
+    node _T_971 = bits(io.lsu_pkt_m.bits.half, 0, 0) @[Bitwise.scala 72:15]
+    node _T_972 = mux(_T_971, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
+    node _T_973 = and(_T_972, UInt<4>("h03")) @[lsu_dccm_ctl.scala 213:38]
+    node _T_974 = or(_T_970, _T_973) @[lsu_dccm_ctl.scala 212:107]
+    node _T_975 = bits(io.lsu_pkt_m.bits.word, 0, 0) @[Bitwise.scala 72:15]
+    node _T_976 = mux(_T_975, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
+    node _T_977 = and(_T_976, UInt<4>("h0f")) @[lsu_dccm_ctl.scala 214:38]
+    node _T_978 = or(_T_974, _T_977) @[lsu_dccm_ctl.scala 213:51]
+    node store_byteen_m = and(_T_967, _T_978) @[lsu_dccm_ctl.scala 212:58]
+    node _T_979 = bits(io.lsu_pkt_r.bits.store, 0, 0) @[Bitwise.scala 72:15]
+    node _T_980 = mux(_T_979, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
+    node _T_981 = bits(io.lsu_pkt_r.bits.by, 0, 0) @[Bitwise.scala 72:15]
+    node _T_982 = mux(_T_981, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
+    node _T_983 = and(_T_982, UInt<4>("h01")) @[lsu_dccm_ctl.scala 216:94]
+    node _T_984 = bits(io.lsu_pkt_r.bits.half, 0, 0) @[Bitwise.scala 72:15]
+    node _T_985 = mux(_T_984, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
+    node _T_986 = and(_T_985, UInt<4>("h03")) @[lsu_dccm_ctl.scala 217:38]
+    node _T_987 = or(_T_983, _T_986) @[lsu_dccm_ctl.scala 216:107]
+    node _T_988 = bits(io.lsu_pkt_r.bits.word, 0, 0) @[Bitwise.scala 72:15]
+    node _T_989 = mux(_T_988, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
+    node _T_990 = and(_T_989, UInt<4>("h0f")) @[lsu_dccm_ctl.scala 218:38]
+    node _T_991 = or(_T_987, _T_990) @[lsu_dccm_ctl.scala 217:51]
+    node store_byteen_r = and(_T_980, _T_991) @[lsu_dccm_ctl.scala 216:58]
+    wire store_byteen_ext_m : UInt<8>
+    store_byteen_ext_m <= UInt<1>("h00")
+    node _T_992 = bits(store_byteen_m, 3, 0) @[lsu_dccm_ctl.scala 220:39]
+    node _T_993 = bits(io.lsu_addr_m, 1, 0) @[lsu_dccm_ctl.scala 220:61]
+    node _T_994 = dshl(_T_992, _T_993) @[lsu_dccm_ctl.scala 220:45]
+    store_byteen_ext_m <= _T_994 @[lsu_dccm_ctl.scala 220:22]
+    wire store_byteen_ext_r : UInt<8>
+    store_byteen_ext_r <= UInt<1>("h00")
+    node _T_995 = bits(store_byteen_r, 3, 0) @[lsu_dccm_ctl.scala 222:39]
+    node _T_996 = bits(io.lsu_addr_r, 1, 0) @[lsu_dccm_ctl.scala 222:61]
+    node _T_997 = dshl(_T_995, _T_996) @[lsu_dccm_ctl.scala 222:45]
+    store_byteen_ext_r <= _T_997 @[lsu_dccm_ctl.scala 222:22]
+    node _T_998 = bits(io.stbuf_addr_any, 15, 2) @[lsu_dccm_ctl.scala 225:51]
+    node _T_999 = bits(io.lsu_addr_m, 15, 2) @[lsu_dccm_ctl.scala 225:84]
+    node _T_1000 = eq(_T_998, _T_999) @[lsu_dccm_ctl.scala 225:67]
+    node dccm_wr_bypass_d_m_lo = and(_T_1000, io.addr_in_dccm_m) @[lsu_dccm_ctl.scala 225:101]
+    node _T_1001 = bits(io.stbuf_addr_any, 15, 2) @[lsu_dccm_ctl.scala 226:51]
+    node _T_1002 = bits(io.end_addr_m, 15, 2) @[lsu_dccm_ctl.scala 226:84]
+    node _T_1003 = eq(_T_1001, _T_1002) @[lsu_dccm_ctl.scala 226:67]
+    node dccm_wr_bypass_d_m_hi = and(_T_1003, io.addr_in_dccm_m) @[lsu_dccm_ctl.scala 226:101]
+    node _T_1004 = bits(io.stbuf_addr_any, 15, 2) @[lsu_dccm_ctl.scala 228:51]
+    node _T_1005 = bits(io.lsu_addr_r, 15, 2) @[lsu_dccm_ctl.scala 228:84]
+    node _T_1006 = eq(_T_1004, _T_1005) @[lsu_dccm_ctl.scala 228:67]
+    node dccm_wr_bypass_d_r_lo = and(_T_1006, io.addr_in_dccm_r) @[lsu_dccm_ctl.scala 228:101]
+    node _T_1007 = bits(io.stbuf_addr_any, 15, 2) @[lsu_dccm_ctl.scala 229:51]
+    node _T_1008 = bits(io.end_addr_r, 15, 2) @[lsu_dccm_ctl.scala 229:84]
+    node _T_1009 = eq(_T_1007, _T_1008) @[lsu_dccm_ctl.scala 229:67]
+    node dccm_wr_bypass_d_r_hi = and(_T_1009, io.addr_in_dccm_r) @[lsu_dccm_ctl.scala 229:101]
+    wire dccm_wr_bypass_d_m_hi_Q : UInt<1>
+    dccm_wr_bypass_d_m_hi_Q <= UInt<1>("h00")
+    wire dccm_wr_bypass_d_m_lo_Q : UInt<1>
+    dccm_wr_bypass_d_m_lo_Q <= UInt<1>("h00")
+    wire dccm_wren_Q : UInt<1>
+    dccm_wren_Q <= UInt<1>("h00")
+    wire dccm_wr_data_Q : UInt<32>
+    dccm_wr_data_Q <= UInt<32>("h00")
+    wire store_data_pre_r : UInt<64>
+    store_data_pre_r <= UInt<64>("h00")
+    wire store_data_pre_hi_r : UInt<32>
+    store_data_pre_hi_r <= UInt<32>("h00")
+    wire store_data_pre_lo_r : UInt<32>
+    store_data_pre_lo_r <= UInt<32>("h00")
+    wire store_data_pre_m : UInt<64>
+    store_data_pre_m <= UInt<64>("h00")
+    wire store_data_hi_m : UInt<32>
+    store_data_hi_m <= UInt<32>("h00")
+    wire store_data_lo_m : UInt<32>
+    store_data_lo_m <= UInt<32>("h00")
+    node _T_1010 = mux(UInt<1>("h00"), UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
+    node _T_1011 = bits(io.store_data_r, 31, 0) @[lsu_dccm_ctl.scala 243:64]
+    node _T_1012 = cat(_T_1010, _T_1011) @[Cat.scala 29:58]
+    node _T_1013 = bits(io.lsu_addr_r, 1, 0) @[lsu_dccm_ctl.scala 243:92]
+    node _T_1014 = mul(UInt<4>("h08"), _T_1013) @[lsu_dccm_ctl.scala 243:78]
+    node _T_1015 = dshl(_T_1012, _T_1014) @[lsu_dccm_ctl.scala 243:72]
+    store_data_pre_r <= _T_1015 @[lsu_dccm_ctl.scala 243:29]
+    node _T_1016 = bits(store_data_pre_r, 63, 32) @[lsu_dccm_ctl.scala 244:48]
+    store_data_pre_hi_r <= _T_1016 @[lsu_dccm_ctl.scala 244:29]
+    node _T_1017 = bits(store_data_pre_r, 31, 0) @[lsu_dccm_ctl.scala 245:48]
+    store_data_pre_lo_r <= _T_1017 @[lsu_dccm_ctl.scala 245:29]
+    node _T_1018 = bits(store_byteen_ext_r, 0, 0) @[lsu_dccm_ctl.scala 246:98]
+    node _T_1019 = bits(_T_1018, 0, 0) @[lsu_dccm_ctl.scala 246:102]
+    node _T_1020 = bits(store_data_pre_lo_r, 7, 0) @[lsu_dccm_ctl.scala 246:130]
+    node _T_1021 = and(dccm_wren_Q, dccm_wr_bypass_d_m_lo_Q) @[lsu_dccm_ctl.scala 246:162]
+    node _T_1022 = bits(_T_1021, 0, 0) @[lsu_dccm_ctl.scala 246:189]
+    node _T_1023 = bits(dccm_wr_data_Q, 7, 0) @[lsu_dccm_ctl.scala 246:211]
+    node _T_1024 = bits(io.sec_data_lo_r, 7, 0) @[lsu_dccm_ctl.scala 246:241]
+    node _T_1025 = mux(_T_1022, _T_1023, _T_1024) @[lsu_dccm_ctl.scala 246:148]
+    node _T_1026 = mux(_T_1019, _T_1020, _T_1025) @[lsu_dccm_ctl.scala 246:79]
+    node _T_1027 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
+    node _T_1028 = xor(UInt<8>("h0ff"), _T_1027) @[Bitwise.scala 102:21]
+    node _T_1029 = shr(_T_1026, 4) @[Bitwise.scala 103:21]
+    node _T_1030 = and(_T_1029, _T_1028) @[Bitwise.scala 103:31]
+    node _T_1031 = bits(_T_1026, 3, 0) @[Bitwise.scala 103:46]
+    node _T_1032 = shl(_T_1031, 4) @[Bitwise.scala 103:65]
+    node _T_1033 = not(_T_1028) @[Bitwise.scala 103:77]
+    node _T_1034 = and(_T_1032, _T_1033) @[Bitwise.scala 103:75]
+    node _T_1035 = or(_T_1030, _T_1034) @[Bitwise.scala 103:39]
+    node _T_1036 = bits(_T_1028, 5, 0) @[Bitwise.scala 102:28]
+    node _T_1037 = shl(_T_1036, 2) @[Bitwise.scala 102:47]
+    node _T_1038 = xor(_T_1028, _T_1037) @[Bitwise.scala 102:21]
+    node _T_1039 = shr(_T_1035, 2) @[Bitwise.scala 103:21]
+    node _T_1040 = and(_T_1039, _T_1038) @[Bitwise.scala 103:31]
+    node _T_1041 = bits(_T_1035, 5, 0) @[Bitwise.scala 103:46]
+    node _T_1042 = shl(_T_1041, 2) @[Bitwise.scala 103:65]
+    node _T_1043 = not(_T_1038) @[Bitwise.scala 103:77]
+    node _T_1044 = and(_T_1042, _T_1043) @[Bitwise.scala 103:75]
+    node _T_1045 = or(_T_1040, _T_1044) @[Bitwise.scala 103:39]
+    node _T_1046 = bits(_T_1038, 6, 0) @[Bitwise.scala 102:28]
+    node _T_1047 = shl(_T_1046, 1) @[Bitwise.scala 102:47]
+    node _T_1048 = xor(_T_1038, _T_1047) @[Bitwise.scala 102:21]
+    node _T_1049 = shr(_T_1045, 1) @[Bitwise.scala 103:21]
+    node _T_1050 = and(_T_1049, _T_1048) @[Bitwise.scala 103:31]
+    node _T_1051 = bits(_T_1045, 6, 0) @[Bitwise.scala 103:46]
+    node _T_1052 = shl(_T_1051, 1) @[Bitwise.scala 103:65]
+    node _T_1053 = not(_T_1048) @[Bitwise.scala 103:77]
+    node _T_1054 = and(_T_1052, _T_1053) @[Bitwise.scala 103:75]
+    node _T_1055 = or(_T_1050, _T_1054) @[Bitwise.scala 103:39]
+    node _T_1056 = bits(store_byteen_ext_r, 1, 1) @[lsu_dccm_ctl.scala 246:98]
+    node _T_1057 = bits(_T_1056, 0, 0) @[lsu_dccm_ctl.scala 246:102]
+    node _T_1058 = bits(store_data_pre_lo_r, 15, 8) @[lsu_dccm_ctl.scala 246:130]
+    node _T_1059 = and(dccm_wren_Q, dccm_wr_bypass_d_m_lo_Q) @[lsu_dccm_ctl.scala 246:162]
+    node _T_1060 = bits(_T_1059, 0, 0) @[lsu_dccm_ctl.scala 246:189]
+    node _T_1061 = bits(dccm_wr_data_Q, 15, 8) @[lsu_dccm_ctl.scala 246:211]
+    node _T_1062 = bits(io.sec_data_lo_r, 15, 8) @[lsu_dccm_ctl.scala 246:241]
+    node _T_1063 = mux(_T_1060, _T_1061, _T_1062) @[lsu_dccm_ctl.scala 246:148]
+    node _T_1064 = mux(_T_1057, _T_1058, _T_1063) @[lsu_dccm_ctl.scala 246:79]
+    node _T_1065 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
+    node _T_1066 = xor(UInt<8>("h0ff"), _T_1065) @[Bitwise.scala 102:21]
+    node _T_1067 = shr(_T_1064, 4) @[Bitwise.scala 103:21]
+    node _T_1068 = and(_T_1067, _T_1066) @[Bitwise.scala 103:31]
+    node _T_1069 = bits(_T_1064, 3, 0) @[Bitwise.scala 103:46]
+    node _T_1070 = shl(_T_1069, 4) @[Bitwise.scala 103:65]
+    node _T_1071 = not(_T_1066) @[Bitwise.scala 103:77]
+    node _T_1072 = and(_T_1070, _T_1071) @[Bitwise.scala 103:75]
+    node _T_1073 = or(_T_1068, _T_1072) @[Bitwise.scala 103:39]
+    node _T_1074 = bits(_T_1066, 5, 0) @[Bitwise.scala 102:28]
+    node _T_1075 = shl(_T_1074, 2) @[Bitwise.scala 102:47]
+    node _T_1076 = xor(_T_1066, _T_1075) @[Bitwise.scala 102:21]
+    node _T_1077 = shr(_T_1073, 2) @[Bitwise.scala 103:21]
+    node _T_1078 = and(_T_1077, _T_1076) @[Bitwise.scala 103:31]
+    node _T_1079 = bits(_T_1073, 5, 0) @[Bitwise.scala 103:46]
+    node _T_1080 = shl(_T_1079, 2) @[Bitwise.scala 103:65]
+    node _T_1081 = not(_T_1076) @[Bitwise.scala 103:77]
+    node _T_1082 = and(_T_1080, _T_1081) @[Bitwise.scala 103:75]
+    node _T_1083 = or(_T_1078, _T_1082) @[Bitwise.scala 103:39]
+    node _T_1084 = bits(_T_1076, 6, 0) @[Bitwise.scala 102:28]
+    node _T_1085 = shl(_T_1084, 1) @[Bitwise.scala 102:47]
+    node _T_1086 = xor(_T_1076, _T_1085) @[Bitwise.scala 102:21]
+    node _T_1087 = shr(_T_1083, 1) @[Bitwise.scala 103:21]
+    node _T_1088 = and(_T_1087, _T_1086) @[Bitwise.scala 103:31]
+    node _T_1089 = bits(_T_1083, 6, 0) @[Bitwise.scala 103:46]
+    node _T_1090 = shl(_T_1089, 1) @[Bitwise.scala 103:65]
+    node _T_1091 = not(_T_1086) @[Bitwise.scala 103:77]
+    node _T_1092 = and(_T_1090, _T_1091) @[Bitwise.scala 103:75]
+    node _T_1093 = or(_T_1088, _T_1092) @[Bitwise.scala 103:39]
+    node _T_1094 = bits(store_byteen_ext_r, 2, 2) @[lsu_dccm_ctl.scala 246:98]
+    node _T_1095 = bits(_T_1094, 0, 0) @[lsu_dccm_ctl.scala 246:102]
+    node _T_1096 = bits(store_data_pre_lo_r, 23, 16) @[lsu_dccm_ctl.scala 246:130]
+    node _T_1097 = and(dccm_wren_Q, dccm_wr_bypass_d_m_lo_Q) @[lsu_dccm_ctl.scala 246:162]
+    node _T_1098 = bits(_T_1097, 0, 0) @[lsu_dccm_ctl.scala 246:189]
+    node _T_1099 = bits(dccm_wr_data_Q, 23, 16) @[lsu_dccm_ctl.scala 246:211]
+    node _T_1100 = bits(io.sec_data_lo_r, 23, 16) @[lsu_dccm_ctl.scala 246:241]
+    node _T_1101 = mux(_T_1098, _T_1099, _T_1100) @[lsu_dccm_ctl.scala 246:148]
+    node _T_1102 = mux(_T_1095, _T_1096, _T_1101) @[lsu_dccm_ctl.scala 246:79]
+    node _T_1103 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
+    node _T_1104 = xor(UInt<8>("h0ff"), _T_1103) @[Bitwise.scala 102:21]
+    node _T_1105 = shr(_T_1102, 4) @[Bitwise.scala 103:21]
+    node _T_1106 = and(_T_1105, _T_1104) @[Bitwise.scala 103:31]
+    node _T_1107 = bits(_T_1102, 3, 0) @[Bitwise.scala 103:46]
+    node _T_1108 = shl(_T_1107, 4) @[Bitwise.scala 103:65]
+    node _T_1109 = not(_T_1104) @[Bitwise.scala 103:77]
+    node _T_1110 = and(_T_1108, _T_1109) @[Bitwise.scala 103:75]
+    node _T_1111 = or(_T_1106, _T_1110) @[Bitwise.scala 103:39]
+    node _T_1112 = bits(_T_1104, 5, 0) @[Bitwise.scala 102:28]
+    node _T_1113 = shl(_T_1112, 2) @[Bitwise.scala 102:47]
+    node _T_1114 = xor(_T_1104, _T_1113) @[Bitwise.scala 102:21]
+    node _T_1115 = shr(_T_1111, 2) @[Bitwise.scala 103:21]
+    node _T_1116 = and(_T_1115, _T_1114) @[Bitwise.scala 103:31]
+    node _T_1117 = bits(_T_1111, 5, 0) @[Bitwise.scala 103:46]
+    node _T_1118 = shl(_T_1117, 2) @[Bitwise.scala 103:65]
+    node _T_1119 = not(_T_1114) @[Bitwise.scala 103:77]
+    node _T_1120 = and(_T_1118, _T_1119) @[Bitwise.scala 103:75]
+    node _T_1121 = or(_T_1116, _T_1120) @[Bitwise.scala 103:39]
+    node _T_1122 = bits(_T_1114, 6, 0) @[Bitwise.scala 102:28]
+    node _T_1123 = shl(_T_1122, 1) @[Bitwise.scala 102:47]
+    node _T_1124 = xor(_T_1114, _T_1123) @[Bitwise.scala 102:21]
+    node _T_1125 = shr(_T_1121, 1) @[Bitwise.scala 103:21]
+    node _T_1126 = and(_T_1125, _T_1124) @[Bitwise.scala 103:31]
+    node _T_1127 = bits(_T_1121, 6, 0) @[Bitwise.scala 103:46]
+    node _T_1128 = shl(_T_1127, 1) @[Bitwise.scala 103:65]
+    node _T_1129 = not(_T_1124) @[Bitwise.scala 103:77]
+    node _T_1130 = and(_T_1128, _T_1129) @[Bitwise.scala 103:75]
+    node _T_1131 = or(_T_1126, _T_1130) @[Bitwise.scala 103:39]
+    node _T_1132 = bits(store_byteen_ext_r, 3, 3) @[lsu_dccm_ctl.scala 246:98]
+    node _T_1133 = bits(_T_1132, 0, 0) @[lsu_dccm_ctl.scala 246:102]
+    node _T_1134 = bits(store_data_pre_lo_r, 31, 24) @[lsu_dccm_ctl.scala 246:130]
+    node _T_1135 = and(dccm_wren_Q, dccm_wr_bypass_d_m_lo_Q) @[lsu_dccm_ctl.scala 246:162]
+    node _T_1136 = bits(_T_1135, 0, 0) @[lsu_dccm_ctl.scala 246:189]
+    node _T_1137 = bits(dccm_wr_data_Q, 31, 24) @[lsu_dccm_ctl.scala 246:211]
+    node _T_1138 = bits(io.sec_data_lo_r, 31, 24) @[lsu_dccm_ctl.scala 246:241]
+    node _T_1139 = mux(_T_1136, _T_1137, _T_1138) @[lsu_dccm_ctl.scala 246:148]
+    node _T_1140 = mux(_T_1133, _T_1134, _T_1139) @[lsu_dccm_ctl.scala 246:79]
+    node _T_1141 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
+    node _T_1142 = xor(UInt<8>("h0ff"), _T_1141) @[Bitwise.scala 102:21]
+    node _T_1143 = shr(_T_1140, 4) @[Bitwise.scala 103:21]
+    node _T_1144 = and(_T_1143, _T_1142) @[Bitwise.scala 103:31]
+    node _T_1145 = bits(_T_1140, 3, 0) @[Bitwise.scala 103:46]
+    node _T_1146 = shl(_T_1145, 4) @[Bitwise.scala 103:65]
+    node _T_1147 = not(_T_1142) @[Bitwise.scala 103:77]
+    node _T_1148 = and(_T_1146, _T_1147) @[Bitwise.scala 103:75]
+    node _T_1149 = or(_T_1144, _T_1148) @[Bitwise.scala 103:39]
+    node _T_1150 = bits(_T_1142, 5, 0) @[Bitwise.scala 102:28]
+    node _T_1151 = shl(_T_1150, 2) @[Bitwise.scala 102:47]
+    node _T_1152 = xor(_T_1142, _T_1151) @[Bitwise.scala 102:21]
+    node _T_1153 = shr(_T_1149, 2) @[Bitwise.scala 103:21]
+    node _T_1154 = and(_T_1153, _T_1152) @[Bitwise.scala 103:31]
+    node _T_1155 = bits(_T_1149, 5, 0) @[Bitwise.scala 103:46]
+    node _T_1156 = shl(_T_1155, 2) @[Bitwise.scala 103:65]
+    node _T_1157 = not(_T_1152) @[Bitwise.scala 103:77]
+    node _T_1158 = and(_T_1156, _T_1157) @[Bitwise.scala 103:75]
+    node _T_1159 = or(_T_1154, _T_1158) @[Bitwise.scala 103:39]
+    node _T_1160 = bits(_T_1152, 6, 0) @[Bitwise.scala 102:28]
+    node _T_1161 = shl(_T_1160, 1) @[Bitwise.scala 102:47]
+    node _T_1162 = xor(_T_1152, _T_1161) @[Bitwise.scala 102:21]
+    node _T_1163 = shr(_T_1159, 1) @[Bitwise.scala 103:21]
+    node _T_1164 = and(_T_1163, _T_1162) @[Bitwise.scala 103:31]
+    node _T_1165 = bits(_T_1159, 6, 0) @[Bitwise.scala 103:46]
+    node _T_1166 = shl(_T_1165, 1) @[Bitwise.scala 103:65]
+    node _T_1167 = not(_T_1162) @[Bitwise.scala 103:77]
+    node _T_1168 = and(_T_1166, _T_1167) @[Bitwise.scala 103:75]
+    node _T_1169 = or(_T_1164, _T_1168) @[Bitwise.scala 103:39]
+    wire _T_1170 : UInt<8>[4] @[lsu_dccm_ctl.scala 246:63]
+    _T_1170[0] <= _T_1055 @[lsu_dccm_ctl.scala 246:63]
+    _T_1170[1] <= _T_1093 @[lsu_dccm_ctl.scala 246:63]
+    _T_1170[2] <= _T_1131 @[lsu_dccm_ctl.scala 246:63]
+    _T_1170[3] <= _T_1169 @[lsu_dccm_ctl.scala 246:63]
+    node _T_1171 = cat(_T_1170[2], _T_1170[3]) @[Cat.scala 29:58]
+    node _T_1172 = cat(_T_1170[0], _T_1170[1]) @[Cat.scala 29:58]
+    node _T_1173 = cat(_T_1172, _T_1171) @[Cat.scala 29:58]
+    node _T_1174 = shl(UInt<16>("h0ffff"), 16) @[Bitwise.scala 102:47]
+    node _T_1175 = xor(UInt<32>("h0ffffffff"), _T_1174) @[Bitwise.scala 102:21]
+    node _T_1176 = shr(_T_1173, 16) @[Bitwise.scala 103:21]
+    node _T_1177 = and(_T_1176, _T_1175) @[Bitwise.scala 103:31]
+    node _T_1178 = bits(_T_1173, 15, 0) @[Bitwise.scala 103:46]
+    node _T_1179 = shl(_T_1178, 16) @[Bitwise.scala 103:65]
+    node _T_1180 = not(_T_1175) @[Bitwise.scala 103:77]
+    node _T_1181 = and(_T_1179, _T_1180) @[Bitwise.scala 103:75]
+    node _T_1182 = or(_T_1177, _T_1181) @[Bitwise.scala 103:39]
+    node _T_1183 = bits(_T_1175, 23, 0) @[Bitwise.scala 102:28]
+    node _T_1184 = shl(_T_1183, 8) @[Bitwise.scala 102:47]
+    node _T_1185 = xor(_T_1175, _T_1184) @[Bitwise.scala 102:21]
+    node _T_1186 = shr(_T_1182, 8) @[Bitwise.scala 103:21]
+    node _T_1187 = and(_T_1186, _T_1185) @[Bitwise.scala 103:31]
+    node _T_1188 = bits(_T_1182, 23, 0) @[Bitwise.scala 103:46]
+    node _T_1189 = shl(_T_1188, 8) @[Bitwise.scala 103:65]
+    node _T_1190 = not(_T_1185) @[Bitwise.scala 103:77]
+    node _T_1191 = and(_T_1189, _T_1190) @[Bitwise.scala 103:75]
+    node _T_1192 = or(_T_1187, _T_1191) @[Bitwise.scala 103:39]
+    node _T_1193 = bits(_T_1185, 27, 0) @[Bitwise.scala 102:28]
+    node _T_1194 = shl(_T_1193, 4) @[Bitwise.scala 102:47]
+    node _T_1195 = xor(_T_1185, _T_1194) @[Bitwise.scala 102:21]
+    node _T_1196 = shr(_T_1192, 4) @[Bitwise.scala 103:21]
+    node _T_1197 = and(_T_1196, _T_1195) @[Bitwise.scala 103:31]
+    node _T_1198 = bits(_T_1192, 27, 0) @[Bitwise.scala 103:46]
+    node _T_1199 = shl(_T_1198, 4) @[Bitwise.scala 103:65]
+    node _T_1200 = not(_T_1195) @[Bitwise.scala 103:77]
+    node _T_1201 = and(_T_1199, _T_1200) @[Bitwise.scala 103:75]
+    node _T_1202 = or(_T_1197, _T_1201) @[Bitwise.scala 103:39]
+    node _T_1203 = bits(_T_1195, 29, 0) @[Bitwise.scala 102:28]
+    node _T_1204 = shl(_T_1203, 2) @[Bitwise.scala 102:47]
+    node _T_1205 = xor(_T_1195, _T_1204) @[Bitwise.scala 102:21]
+    node _T_1206 = shr(_T_1202, 2) @[Bitwise.scala 103:21]
+    node _T_1207 = and(_T_1206, _T_1205) @[Bitwise.scala 103:31]
+    node _T_1208 = bits(_T_1202, 29, 0) @[Bitwise.scala 103:46]
+    node _T_1209 = shl(_T_1208, 2) @[Bitwise.scala 103:65]
+    node _T_1210 = not(_T_1205) @[Bitwise.scala 103:77]
+    node _T_1211 = and(_T_1209, _T_1210) @[Bitwise.scala 103:75]
+    node _T_1212 = or(_T_1207, _T_1211) @[Bitwise.scala 103:39]
+    node _T_1213 = bits(_T_1205, 30, 0) @[Bitwise.scala 102:28]
+    node _T_1214 = shl(_T_1213, 1) @[Bitwise.scala 102:47]
+    node _T_1215 = xor(_T_1205, _T_1214) @[Bitwise.scala 102:21]
+    node _T_1216 = shr(_T_1212, 1) @[Bitwise.scala 103:21]
+    node _T_1217 = and(_T_1216, _T_1215) @[Bitwise.scala 103:31]
+    node _T_1218 = bits(_T_1212, 30, 0) @[Bitwise.scala 103:46]
+    node _T_1219 = shl(_T_1218, 1) @[Bitwise.scala 103:65]
+    node _T_1220 = not(_T_1215) @[Bitwise.scala 103:77]
+    node _T_1221 = and(_T_1219, _T_1220) @[Bitwise.scala 103:75]
+    node _T_1222 = or(_T_1217, _T_1221) @[Bitwise.scala 103:39]
+    io.store_data_lo_r <= _T_1222 @[lsu_dccm_ctl.scala 246:29]
+    node _T_1223 = bits(store_byteen_ext_r, 4, 4) @[lsu_dccm_ctl.scala 247:98]
+    node _T_1224 = bits(_T_1223, 0, 0) @[lsu_dccm_ctl.scala 247:104]
+    node _T_1225 = bits(store_data_pre_hi_r, 7, 0) @[lsu_dccm_ctl.scala 247:130]
+    node _T_1226 = and(dccm_wren_Q, dccm_wr_bypass_d_m_hi_Q) @[lsu_dccm_ctl.scala 247:162]
+    node _T_1227 = bits(_T_1226, 0, 0) @[lsu_dccm_ctl.scala 247:189]
+    node _T_1228 = bits(dccm_wr_data_Q, 7, 0) @[lsu_dccm_ctl.scala 247:211]
+    node _T_1229 = bits(io.sec_data_hi_r, 7, 0) @[lsu_dccm_ctl.scala 247:241]
+    node _T_1230 = mux(_T_1227, _T_1228, _T_1229) @[lsu_dccm_ctl.scala 247:148]
+    node _T_1231 = mux(_T_1224, _T_1225, _T_1230) @[lsu_dccm_ctl.scala 247:79]
+    node _T_1232 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
+    node _T_1233 = xor(UInt<8>("h0ff"), _T_1232) @[Bitwise.scala 102:21]
+    node _T_1234 = shr(_T_1231, 4) @[Bitwise.scala 103:21]
+    node _T_1235 = and(_T_1234, _T_1233) @[Bitwise.scala 103:31]
+    node _T_1236 = bits(_T_1231, 3, 0) @[Bitwise.scala 103:46]
+    node _T_1237 = shl(_T_1236, 4) @[Bitwise.scala 103:65]
+    node _T_1238 = not(_T_1233) @[Bitwise.scala 103:77]
+    node _T_1239 = and(_T_1237, _T_1238) @[Bitwise.scala 103:75]
+    node _T_1240 = or(_T_1235, _T_1239) @[Bitwise.scala 103:39]
+    node _T_1241 = bits(_T_1233, 5, 0) @[Bitwise.scala 102:28]
+    node _T_1242 = shl(_T_1241, 2) @[Bitwise.scala 102:47]
+    node _T_1243 = xor(_T_1233, _T_1242) @[Bitwise.scala 102:21]
+    node _T_1244 = shr(_T_1240, 2) @[Bitwise.scala 103:21]
+    node _T_1245 = and(_T_1244, _T_1243) @[Bitwise.scala 103:31]
+    node _T_1246 = bits(_T_1240, 5, 0) @[Bitwise.scala 103:46]
+    node _T_1247 = shl(_T_1246, 2) @[Bitwise.scala 103:65]
+    node _T_1248 = not(_T_1243) @[Bitwise.scala 103:77]
+    node _T_1249 = and(_T_1247, _T_1248) @[Bitwise.scala 103:75]
+    node _T_1250 = or(_T_1245, _T_1249) @[Bitwise.scala 103:39]
+    node _T_1251 = bits(_T_1243, 6, 0) @[Bitwise.scala 102:28]
+    node _T_1252 = shl(_T_1251, 1) @[Bitwise.scala 102:47]
+    node _T_1253 = xor(_T_1243, _T_1252) @[Bitwise.scala 102:21]
+    node _T_1254 = shr(_T_1250, 1) @[Bitwise.scala 103:21]
+    node _T_1255 = and(_T_1254, _T_1253) @[Bitwise.scala 103:31]
+    node _T_1256 = bits(_T_1250, 6, 0) @[Bitwise.scala 103:46]
+    node _T_1257 = shl(_T_1256, 1) @[Bitwise.scala 103:65]
+    node _T_1258 = not(_T_1253) @[Bitwise.scala 103:77]
+    node _T_1259 = and(_T_1257, _T_1258) @[Bitwise.scala 103:75]
+    node _T_1260 = or(_T_1255, _T_1259) @[Bitwise.scala 103:39]
+    node _T_1261 = bits(store_byteen_ext_r, 5, 5) @[lsu_dccm_ctl.scala 247:98]
+    node _T_1262 = bits(_T_1261, 0, 0) @[lsu_dccm_ctl.scala 247:104]
+    node _T_1263 = bits(store_data_pre_hi_r, 15, 8) @[lsu_dccm_ctl.scala 247:130]
+    node _T_1264 = and(dccm_wren_Q, dccm_wr_bypass_d_m_hi_Q) @[lsu_dccm_ctl.scala 247:162]
+    node _T_1265 = bits(_T_1264, 0, 0) @[lsu_dccm_ctl.scala 247:189]
+    node _T_1266 = bits(dccm_wr_data_Q, 15, 8) @[lsu_dccm_ctl.scala 247:211]
+    node _T_1267 = bits(io.sec_data_hi_r, 15, 8) @[lsu_dccm_ctl.scala 247:241]
+    node _T_1268 = mux(_T_1265, _T_1266, _T_1267) @[lsu_dccm_ctl.scala 247:148]
+    node _T_1269 = mux(_T_1262, _T_1263, _T_1268) @[lsu_dccm_ctl.scala 247:79]
+    node _T_1270 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
+    node _T_1271 = xor(UInt<8>("h0ff"), _T_1270) @[Bitwise.scala 102:21]
+    node _T_1272 = shr(_T_1269, 4) @[Bitwise.scala 103:21]
+    node _T_1273 = and(_T_1272, _T_1271) @[Bitwise.scala 103:31]
+    node _T_1274 = bits(_T_1269, 3, 0) @[Bitwise.scala 103:46]
+    node _T_1275 = shl(_T_1274, 4) @[Bitwise.scala 103:65]
+    node _T_1276 = not(_T_1271) @[Bitwise.scala 103:77]
+    node _T_1277 = and(_T_1275, _T_1276) @[Bitwise.scala 103:75]
+    node _T_1278 = or(_T_1273, _T_1277) @[Bitwise.scala 103:39]
+    node _T_1279 = bits(_T_1271, 5, 0) @[Bitwise.scala 102:28]
+    node _T_1280 = shl(_T_1279, 2) @[Bitwise.scala 102:47]
+    node _T_1281 = xor(_T_1271, _T_1280) @[Bitwise.scala 102:21]
+    node _T_1282 = shr(_T_1278, 2) @[Bitwise.scala 103:21]
+    node _T_1283 = and(_T_1282, _T_1281) @[Bitwise.scala 103:31]
+    node _T_1284 = bits(_T_1278, 5, 0) @[Bitwise.scala 103:46]
+    node _T_1285 = shl(_T_1284, 2) @[Bitwise.scala 103:65]
+    node _T_1286 = not(_T_1281) @[Bitwise.scala 103:77]
+    node _T_1287 = and(_T_1285, _T_1286) @[Bitwise.scala 103:75]
+    node _T_1288 = or(_T_1283, _T_1287) @[Bitwise.scala 103:39]
+    node _T_1289 = bits(_T_1281, 6, 0) @[Bitwise.scala 102:28]
+    node _T_1290 = shl(_T_1289, 1) @[Bitwise.scala 102:47]
+    node _T_1291 = xor(_T_1281, _T_1290) @[Bitwise.scala 102:21]
+    node _T_1292 = shr(_T_1288, 1) @[Bitwise.scala 103:21]
+    node _T_1293 = and(_T_1292, _T_1291) @[Bitwise.scala 103:31]
+    node _T_1294 = bits(_T_1288, 6, 0) @[Bitwise.scala 103:46]
+    node _T_1295 = shl(_T_1294, 1) @[Bitwise.scala 103:65]
+    node _T_1296 = not(_T_1291) @[Bitwise.scala 103:77]
+    node _T_1297 = and(_T_1295, _T_1296) @[Bitwise.scala 103:75]
+    node _T_1298 = or(_T_1293, _T_1297) @[Bitwise.scala 103:39]
+    node _T_1299 = bits(store_byteen_ext_r, 6, 6) @[lsu_dccm_ctl.scala 247:98]
+    node _T_1300 = bits(_T_1299, 0, 0) @[lsu_dccm_ctl.scala 247:104]
+    node _T_1301 = bits(store_data_pre_hi_r, 23, 16) @[lsu_dccm_ctl.scala 247:130]
+    node _T_1302 = and(dccm_wren_Q, dccm_wr_bypass_d_m_hi_Q) @[lsu_dccm_ctl.scala 247:162]
+    node _T_1303 = bits(_T_1302, 0, 0) @[lsu_dccm_ctl.scala 247:189]
+    node _T_1304 = bits(dccm_wr_data_Q, 23, 16) @[lsu_dccm_ctl.scala 247:211]
+    node _T_1305 = bits(io.sec_data_hi_r, 23, 16) @[lsu_dccm_ctl.scala 247:241]
+    node _T_1306 = mux(_T_1303, _T_1304, _T_1305) @[lsu_dccm_ctl.scala 247:148]
+    node _T_1307 = mux(_T_1300, _T_1301, _T_1306) @[lsu_dccm_ctl.scala 247:79]
+    node _T_1308 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
+    node _T_1309 = xor(UInt<8>("h0ff"), _T_1308) @[Bitwise.scala 102:21]
+    node _T_1310 = shr(_T_1307, 4) @[Bitwise.scala 103:21]
+    node _T_1311 = and(_T_1310, _T_1309) @[Bitwise.scala 103:31]
+    node _T_1312 = bits(_T_1307, 3, 0) @[Bitwise.scala 103:46]
+    node _T_1313 = shl(_T_1312, 4) @[Bitwise.scala 103:65]
+    node _T_1314 = not(_T_1309) @[Bitwise.scala 103:77]
+    node _T_1315 = and(_T_1313, _T_1314) @[Bitwise.scala 103:75]
+    node _T_1316 = or(_T_1311, _T_1315) @[Bitwise.scala 103:39]
+    node _T_1317 = bits(_T_1309, 5, 0) @[Bitwise.scala 102:28]
+    node _T_1318 = shl(_T_1317, 2) @[Bitwise.scala 102:47]
+    node _T_1319 = xor(_T_1309, _T_1318) @[Bitwise.scala 102:21]
+    node _T_1320 = shr(_T_1316, 2) @[Bitwise.scala 103:21]
+    node _T_1321 = and(_T_1320, _T_1319) @[Bitwise.scala 103:31]
+    node _T_1322 = bits(_T_1316, 5, 0) @[Bitwise.scala 103:46]
+    node _T_1323 = shl(_T_1322, 2) @[Bitwise.scala 103:65]
+    node _T_1324 = not(_T_1319) @[Bitwise.scala 103:77]
+    node _T_1325 = and(_T_1323, _T_1324) @[Bitwise.scala 103:75]
+    node _T_1326 = or(_T_1321, _T_1325) @[Bitwise.scala 103:39]
+    node _T_1327 = bits(_T_1319, 6, 0) @[Bitwise.scala 102:28]
+    node _T_1328 = shl(_T_1327, 1) @[Bitwise.scala 102:47]
+    node _T_1329 = xor(_T_1319, _T_1328) @[Bitwise.scala 102:21]
+    node _T_1330 = shr(_T_1326, 1) @[Bitwise.scala 103:21]
+    node _T_1331 = and(_T_1330, _T_1329) @[Bitwise.scala 103:31]
+    node _T_1332 = bits(_T_1326, 6, 0) @[Bitwise.scala 103:46]
+    node _T_1333 = shl(_T_1332, 1) @[Bitwise.scala 103:65]
+    node _T_1334 = not(_T_1329) @[Bitwise.scala 103:77]
+    node _T_1335 = and(_T_1333, _T_1334) @[Bitwise.scala 103:75]
+    node _T_1336 = or(_T_1331, _T_1335) @[Bitwise.scala 103:39]
+    node _T_1337 = bits(store_byteen_ext_r, 7, 7) @[lsu_dccm_ctl.scala 247:98]
+    node _T_1338 = bits(_T_1337, 0, 0) @[lsu_dccm_ctl.scala 247:104]
+    node _T_1339 = bits(store_data_pre_hi_r, 31, 24) @[lsu_dccm_ctl.scala 247:130]
+    node _T_1340 = and(dccm_wren_Q, dccm_wr_bypass_d_m_hi_Q) @[lsu_dccm_ctl.scala 247:162]
+    node _T_1341 = bits(_T_1340, 0, 0) @[lsu_dccm_ctl.scala 247:189]
+    node _T_1342 = bits(dccm_wr_data_Q, 31, 24) @[lsu_dccm_ctl.scala 247:211]
+    node _T_1343 = bits(io.sec_data_hi_r, 31, 24) @[lsu_dccm_ctl.scala 247:241]
+    node _T_1344 = mux(_T_1341, _T_1342, _T_1343) @[lsu_dccm_ctl.scala 247:148]
+    node _T_1345 = mux(_T_1338, _T_1339, _T_1344) @[lsu_dccm_ctl.scala 247:79]
+    node _T_1346 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
+    node _T_1347 = xor(UInt<8>("h0ff"), _T_1346) @[Bitwise.scala 102:21]
+    node _T_1348 = shr(_T_1345, 4) @[Bitwise.scala 103:21]
+    node _T_1349 = and(_T_1348, _T_1347) @[Bitwise.scala 103:31]
+    node _T_1350 = bits(_T_1345, 3, 0) @[Bitwise.scala 103:46]
+    node _T_1351 = shl(_T_1350, 4) @[Bitwise.scala 103:65]
+    node _T_1352 = not(_T_1347) @[Bitwise.scala 103:77]
+    node _T_1353 = and(_T_1351, _T_1352) @[Bitwise.scala 103:75]
+    node _T_1354 = or(_T_1349, _T_1353) @[Bitwise.scala 103:39]
+    node _T_1355 = bits(_T_1347, 5, 0) @[Bitwise.scala 102:28]
+    node _T_1356 = shl(_T_1355, 2) @[Bitwise.scala 102:47]
+    node _T_1357 = xor(_T_1347, _T_1356) @[Bitwise.scala 102:21]
+    node _T_1358 = shr(_T_1354, 2) @[Bitwise.scala 103:21]
+    node _T_1359 = and(_T_1358, _T_1357) @[Bitwise.scala 103:31]
+    node _T_1360 = bits(_T_1354, 5, 0) @[Bitwise.scala 103:46]
+    node _T_1361 = shl(_T_1360, 2) @[Bitwise.scala 103:65]
+    node _T_1362 = not(_T_1357) @[Bitwise.scala 103:77]
+    node _T_1363 = and(_T_1361, _T_1362) @[Bitwise.scala 103:75]
+    node _T_1364 = or(_T_1359, _T_1363) @[Bitwise.scala 103:39]
+    node _T_1365 = bits(_T_1357, 6, 0) @[Bitwise.scala 102:28]
+    node _T_1366 = shl(_T_1365, 1) @[Bitwise.scala 102:47]
+    node _T_1367 = xor(_T_1357, _T_1366) @[Bitwise.scala 102:21]
+    node _T_1368 = shr(_T_1364, 1) @[Bitwise.scala 103:21]
+    node _T_1369 = and(_T_1368, _T_1367) @[Bitwise.scala 103:31]
+    node _T_1370 = bits(_T_1364, 6, 0) @[Bitwise.scala 103:46]
+    node _T_1371 = shl(_T_1370, 1) @[Bitwise.scala 103:65]
+    node _T_1372 = not(_T_1367) @[Bitwise.scala 103:77]
+    node _T_1373 = and(_T_1371, _T_1372) @[Bitwise.scala 103:75]
+    node _T_1374 = or(_T_1369, _T_1373) @[Bitwise.scala 103:39]
+    wire _T_1375 : UInt<8>[4] @[lsu_dccm_ctl.scala 247:63]
+    _T_1375[0] <= _T_1260 @[lsu_dccm_ctl.scala 247:63]
+    _T_1375[1] <= _T_1298 @[lsu_dccm_ctl.scala 247:63]
+    _T_1375[2] <= _T_1336 @[lsu_dccm_ctl.scala 247:63]
+    _T_1375[3] <= _T_1374 @[lsu_dccm_ctl.scala 247:63]
+    node _T_1376 = cat(_T_1375[2], _T_1375[3]) @[Cat.scala 29:58]
+    node _T_1377 = cat(_T_1375[0], _T_1375[1]) @[Cat.scala 29:58]
+    node _T_1378 = cat(_T_1377, _T_1376) @[Cat.scala 29:58]
+    node _T_1379 = shl(UInt<16>("h0ffff"), 16) @[Bitwise.scala 102:47]
+    node _T_1380 = xor(UInt<32>("h0ffffffff"), _T_1379) @[Bitwise.scala 102:21]
+    node _T_1381 = shr(_T_1378, 16) @[Bitwise.scala 103:21]
+    node _T_1382 = and(_T_1381, _T_1380) @[Bitwise.scala 103:31]
+    node _T_1383 = bits(_T_1378, 15, 0) @[Bitwise.scala 103:46]
+    node _T_1384 = shl(_T_1383, 16) @[Bitwise.scala 103:65]
+    node _T_1385 = not(_T_1380) @[Bitwise.scala 103:77]
+    node _T_1386 = and(_T_1384, _T_1385) @[Bitwise.scala 103:75]
+    node _T_1387 = or(_T_1382, _T_1386) @[Bitwise.scala 103:39]
+    node _T_1388 = bits(_T_1380, 23, 0) @[Bitwise.scala 102:28]
+    node _T_1389 = shl(_T_1388, 8) @[Bitwise.scala 102:47]
+    node _T_1390 = xor(_T_1380, _T_1389) @[Bitwise.scala 102:21]
+    node _T_1391 = shr(_T_1387, 8) @[Bitwise.scala 103:21]
+    node _T_1392 = and(_T_1391, _T_1390) @[Bitwise.scala 103:31]
+    node _T_1393 = bits(_T_1387, 23, 0) @[Bitwise.scala 103:46]
+    node _T_1394 = shl(_T_1393, 8) @[Bitwise.scala 103:65]
+    node _T_1395 = not(_T_1390) @[Bitwise.scala 103:77]
+    node _T_1396 = and(_T_1394, _T_1395) @[Bitwise.scala 103:75]
+    node _T_1397 = or(_T_1392, _T_1396) @[Bitwise.scala 103:39]
+    node _T_1398 = bits(_T_1390, 27, 0) @[Bitwise.scala 102:28]
+    node _T_1399 = shl(_T_1398, 4) @[Bitwise.scala 102:47]
+    node _T_1400 = xor(_T_1390, _T_1399) @[Bitwise.scala 102:21]
+    node _T_1401 = shr(_T_1397, 4) @[Bitwise.scala 103:21]
+    node _T_1402 = and(_T_1401, _T_1400) @[Bitwise.scala 103:31]
+    node _T_1403 = bits(_T_1397, 27, 0) @[Bitwise.scala 103:46]
+    node _T_1404 = shl(_T_1403, 4) @[Bitwise.scala 103:65]
+    node _T_1405 = not(_T_1400) @[Bitwise.scala 103:77]
+    node _T_1406 = and(_T_1404, _T_1405) @[Bitwise.scala 103:75]
+    node _T_1407 = or(_T_1402, _T_1406) @[Bitwise.scala 103:39]
+    node _T_1408 = bits(_T_1400, 29, 0) @[Bitwise.scala 102:28]
+    node _T_1409 = shl(_T_1408, 2) @[Bitwise.scala 102:47]
+    node _T_1410 = xor(_T_1400, _T_1409) @[Bitwise.scala 102:21]
+    node _T_1411 = shr(_T_1407, 2) @[Bitwise.scala 103:21]
+    node _T_1412 = and(_T_1411, _T_1410) @[Bitwise.scala 103:31]
+    node _T_1413 = bits(_T_1407, 29, 0) @[Bitwise.scala 103:46]
+    node _T_1414 = shl(_T_1413, 2) @[Bitwise.scala 103:65]
+    node _T_1415 = not(_T_1410) @[Bitwise.scala 103:77]
+    node _T_1416 = and(_T_1414, _T_1415) @[Bitwise.scala 103:75]
+    node _T_1417 = or(_T_1412, _T_1416) @[Bitwise.scala 103:39]
+    node _T_1418 = bits(_T_1410, 30, 0) @[Bitwise.scala 102:28]
+    node _T_1419 = shl(_T_1418, 1) @[Bitwise.scala 102:47]
+    node _T_1420 = xor(_T_1410, _T_1419) @[Bitwise.scala 102:21]
+    node _T_1421 = shr(_T_1417, 1) @[Bitwise.scala 103:21]
+    node _T_1422 = and(_T_1421, _T_1420) @[Bitwise.scala 103:31]
+    node _T_1423 = bits(_T_1417, 30, 0) @[Bitwise.scala 103:46]
+    node _T_1424 = shl(_T_1423, 1) @[Bitwise.scala 103:65]
+    node _T_1425 = not(_T_1420) @[Bitwise.scala 103:77]
+    node _T_1426 = and(_T_1424, _T_1425) @[Bitwise.scala 103:75]
+    node _T_1427 = or(_T_1422, _T_1426) @[Bitwise.scala 103:39]
+    io.store_data_hi_r <= _T_1427 @[lsu_dccm_ctl.scala 247:29]
+    node _T_1428 = bits(store_byteen_ext_r, 0, 0) @[lsu_dccm_ctl.scala 248:98]
+    node _T_1429 = bits(_T_1428, 0, 0) @[lsu_dccm_ctl.scala 248:102]
+    node _T_1430 = bits(store_data_pre_lo_r, 7, 0) @[lsu_dccm_ctl.scala 248:130]
+    node _T_1431 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_lo) @[lsu_dccm_ctl.scala 248:174]
+    node _T_1432 = bits(_T_1431, 0, 0) @[lsu_dccm_ctl.scala 248:199]
+    node _T_1433 = bits(io.stbuf_data_any, 7, 0) @[lsu_dccm_ctl.scala 248:223]
+    node _T_1434 = and(dccm_wren_Q, dccm_wr_bypass_d_m_lo_Q) @[lsu_dccm_ctl.scala 248:256]
+    node _T_1435 = bits(_T_1434, 0, 0) @[lsu_dccm_ctl.scala 248:283]
+    node _T_1436 = bits(dccm_wr_data_Q, 7, 0) @[lsu_dccm_ctl.scala 248:305]
+    node _T_1437 = bits(io.sec_data_lo_r, 7, 0) @[lsu_dccm_ctl.scala 248:335]
+    node _T_1438 = mux(_T_1435, _T_1436, _T_1437) @[lsu_dccm_ctl.scala 248:242]
+    node _T_1439 = mux(_T_1432, _T_1433, _T_1438) @[lsu_dccm_ctl.scala 248:148]
+    node _T_1440 = mux(_T_1429, _T_1430, _T_1439) @[lsu_dccm_ctl.scala 248:79]
+    node _T_1441 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
+    node _T_1442 = xor(UInt<8>("h0ff"), _T_1441) @[Bitwise.scala 102:21]
+    node _T_1443 = shr(_T_1440, 4) @[Bitwise.scala 103:21]
+    node _T_1444 = and(_T_1443, _T_1442) @[Bitwise.scala 103:31]
+    node _T_1445 = bits(_T_1440, 3, 0) @[Bitwise.scala 103:46]
+    node _T_1446 = shl(_T_1445, 4) @[Bitwise.scala 103:65]
+    node _T_1447 = not(_T_1442) @[Bitwise.scala 103:77]
+    node _T_1448 = and(_T_1446, _T_1447) @[Bitwise.scala 103:75]
+    node _T_1449 = or(_T_1444, _T_1448) @[Bitwise.scala 103:39]
+    node _T_1450 = bits(_T_1442, 5, 0) @[Bitwise.scala 102:28]
+    node _T_1451 = shl(_T_1450, 2) @[Bitwise.scala 102:47]
+    node _T_1452 = xor(_T_1442, _T_1451) @[Bitwise.scala 102:21]
+    node _T_1453 = shr(_T_1449, 2) @[Bitwise.scala 103:21]
+    node _T_1454 = and(_T_1453, _T_1452) @[Bitwise.scala 103:31]
+    node _T_1455 = bits(_T_1449, 5, 0) @[Bitwise.scala 103:46]
+    node _T_1456 = shl(_T_1455, 2) @[Bitwise.scala 103:65]
+    node _T_1457 = not(_T_1452) @[Bitwise.scala 103:77]
+    node _T_1458 = and(_T_1456, _T_1457) @[Bitwise.scala 103:75]
+    node _T_1459 = or(_T_1454, _T_1458) @[Bitwise.scala 103:39]
+    node _T_1460 = bits(_T_1452, 6, 0) @[Bitwise.scala 102:28]
+    node _T_1461 = shl(_T_1460, 1) @[Bitwise.scala 102:47]
+    node _T_1462 = xor(_T_1452, _T_1461) @[Bitwise.scala 102:21]
+    node _T_1463 = shr(_T_1459, 1) @[Bitwise.scala 103:21]
+    node _T_1464 = and(_T_1463, _T_1462) @[Bitwise.scala 103:31]
+    node _T_1465 = bits(_T_1459, 6, 0) @[Bitwise.scala 103:46]
+    node _T_1466 = shl(_T_1465, 1) @[Bitwise.scala 103:65]
+    node _T_1467 = not(_T_1462) @[Bitwise.scala 103:77]
+    node _T_1468 = and(_T_1466, _T_1467) @[Bitwise.scala 103:75]
+    node _T_1469 = or(_T_1464, _T_1468) @[Bitwise.scala 103:39]
+    node _T_1470 = bits(store_byteen_ext_r, 1, 1) @[lsu_dccm_ctl.scala 248:98]
+    node _T_1471 = bits(_T_1470, 0, 0) @[lsu_dccm_ctl.scala 248:102]
+    node _T_1472 = bits(store_data_pre_lo_r, 15, 8) @[lsu_dccm_ctl.scala 248:130]
+    node _T_1473 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_lo) @[lsu_dccm_ctl.scala 248:174]
+    node _T_1474 = bits(_T_1473, 0, 0) @[lsu_dccm_ctl.scala 248:199]
+    node _T_1475 = bits(io.stbuf_data_any, 15, 8) @[lsu_dccm_ctl.scala 248:223]
+    node _T_1476 = and(dccm_wren_Q, dccm_wr_bypass_d_m_lo_Q) @[lsu_dccm_ctl.scala 248:256]
+    node _T_1477 = bits(_T_1476, 0, 0) @[lsu_dccm_ctl.scala 248:283]
+    node _T_1478 = bits(dccm_wr_data_Q, 15, 8) @[lsu_dccm_ctl.scala 248:305]
+    node _T_1479 = bits(io.sec_data_lo_r, 15, 8) @[lsu_dccm_ctl.scala 248:335]
+    node _T_1480 = mux(_T_1477, _T_1478, _T_1479) @[lsu_dccm_ctl.scala 248:242]
+    node _T_1481 = mux(_T_1474, _T_1475, _T_1480) @[lsu_dccm_ctl.scala 248:148]
+    node _T_1482 = mux(_T_1471, _T_1472, _T_1481) @[lsu_dccm_ctl.scala 248:79]
+    node _T_1483 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
+    node _T_1484 = xor(UInt<8>("h0ff"), _T_1483) @[Bitwise.scala 102:21]
+    node _T_1485 = shr(_T_1482, 4) @[Bitwise.scala 103:21]
+    node _T_1486 = and(_T_1485, _T_1484) @[Bitwise.scala 103:31]
+    node _T_1487 = bits(_T_1482, 3, 0) @[Bitwise.scala 103:46]
+    node _T_1488 = shl(_T_1487, 4) @[Bitwise.scala 103:65]
+    node _T_1489 = not(_T_1484) @[Bitwise.scala 103:77]
+    node _T_1490 = and(_T_1488, _T_1489) @[Bitwise.scala 103:75]
+    node _T_1491 = or(_T_1486, _T_1490) @[Bitwise.scala 103:39]
+    node _T_1492 = bits(_T_1484, 5, 0) @[Bitwise.scala 102:28]
+    node _T_1493 = shl(_T_1492, 2) @[Bitwise.scala 102:47]
+    node _T_1494 = xor(_T_1484, _T_1493) @[Bitwise.scala 102:21]
+    node _T_1495 = shr(_T_1491, 2) @[Bitwise.scala 103:21]
+    node _T_1496 = and(_T_1495, _T_1494) @[Bitwise.scala 103:31]
+    node _T_1497 = bits(_T_1491, 5, 0) @[Bitwise.scala 103:46]
+    node _T_1498 = shl(_T_1497, 2) @[Bitwise.scala 103:65]
+    node _T_1499 = not(_T_1494) @[Bitwise.scala 103:77]
+    node _T_1500 = and(_T_1498, _T_1499) @[Bitwise.scala 103:75]
+    node _T_1501 = or(_T_1496, _T_1500) @[Bitwise.scala 103:39]
+    node _T_1502 = bits(_T_1494, 6, 0) @[Bitwise.scala 102:28]
+    node _T_1503 = shl(_T_1502, 1) @[Bitwise.scala 102:47]
+    node _T_1504 = xor(_T_1494, _T_1503) @[Bitwise.scala 102:21]
+    node _T_1505 = shr(_T_1501, 1) @[Bitwise.scala 103:21]
+    node _T_1506 = and(_T_1505, _T_1504) @[Bitwise.scala 103:31]
+    node _T_1507 = bits(_T_1501, 6, 0) @[Bitwise.scala 103:46]
+    node _T_1508 = shl(_T_1507, 1) @[Bitwise.scala 103:65]
+    node _T_1509 = not(_T_1504) @[Bitwise.scala 103:77]
+    node _T_1510 = and(_T_1508, _T_1509) @[Bitwise.scala 103:75]
+    node _T_1511 = or(_T_1506, _T_1510) @[Bitwise.scala 103:39]
+    node _T_1512 = bits(store_byteen_ext_r, 2, 2) @[lsu_dccm_ctl.scala 248:98]
+    node _T_1513 = bits(_T_1512, 0, 0) @[lsu_dccm_ctl.scala 248:102]
+    node _T_1514 = bits(store_data_pre_lo_r, 23, 16) @[lsu_dccm_ctl.scala 248:130]
+    node _T_1515 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_lo) @[lsu_dccm_ctl.scala 248:174]
+    node _T_1516 = bits(_T_1515, 0, 0) @[lsu_dccm_ctl.scala 248:199]
+    node _T_1517 = bits(io.stbuf_data_any, 23, 16) @[lsu_dccm_ctl.scala 248:223]
+    node _T_1518 = and(dccm_wren_Q, dccm_wr_bypass_d_m_lo_Q) @[lsu_dccm_ctl.scala 248:256]
+    node _T_1519 = bits(_T_1518, 0, 0) @[lsu_dccm_ctl.scala 248:283]
+    node _T_1520 = bits(dccm_wr_data_Q, 23, 16) @[lsu_dccm_ctl.scala 248:305]
+    node _T_1521 = bits(io.sec_data_lo_r, 23, 16) @[lsu_dccm_ctl.scala 248:335]
+    node _T_1522 = mux(_T_1519, _T_1520, _T_1521) @[lsu_dccm_ctl.scala 248:242]
+    node _T_1523 = mux(_T_1516, _T_1517, _T_1522) @[lsu_dccm_ctl.scala 248:148]
+    node _T_1524 = mux(_T_1513, _T_1514, _T_1523) @[lsu_dccm_ctl.scala 248:79]
+    node _T_1525 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
+    node _T_1526 = xor(UInt<8>("h0ff"), _T_1525) @[Bitwise.scala 102:21]
+    node _T_1527 = shr(_T_1524, 4) @[Bitwise.scala 103:21]
+    node _T_1528 = and(_T_1527, _T_1526) @[Bitwise.scala 103:31]
+    node _T_1529 = bits(_T_1524, 3, 0) @[Bitwise.scala 103:46]
+    node _T_1530 = shl(_T_1529, 4) @[Bitwise.scala 103:65]
+    node _T_1531 = not(_T_1526) @[Bitwise.scala 103:77]
+    node _T_1532 = and(_T_1530, _T_1531) @[Bitwise.scala 103:75]
+    node _T_1533 = or(_T_1528, _T_1532) @[Bitwise.scala 103:39]
+    node _T_1534 = bits(_T_1526, 5, 0) @[Bitwise.scala 102:28]
+    node _T_1535 = shl(_T_1534, 2) @[Bitwise.scala 102:47]
+    node _T_1536 = xor(_T_1526, _T_1535) @[Bitwise.scala 102:21]
+    node _T_1537 = shr(_T_1533, 2) @[Bitwise.scala 103:21]
+    node _T_1538 = and(_T_1537, _T_1536) @[Bitwise.scala 103:31]
+    node _T_1539 = bits(_T_1533, 5, 0) @[Bitwise.scala 103:46]
+    node _T_1540 = shl(_T_1539, 2) @[Bitwise.scala 103:65]
+    node _T_1541 = not(_T_1536) @[Bitwise.scala 103:77]
+    node _T_1542 = and(_T_1540, _T_1541) @[Bitwise.scala 103:75]
+    node _T_1543 = or(_T_1538, _T_1542) @[Bitwise.scala 103:39]
+    node _T_1544 = bits(_T_1536, 6, 0) @[Bitwise.scala 102:28]
+    node _T_1545 = shl(_T_1544, 1) @[Bitwise.scala 102:47]
+    node _T_1546 = xor(_T_1536, _T_1545) @[Bitwise.scala 102:21]
+    node _T_1547 = shr(_T_1543, 1) @[Bitwise.scala 103:21]
+    node _T_1548 = and(_T_1547, _T_1546) @[Bitwise.scala 103:31]
+    node _T_1549 = bits(_T_1543, 6, 0) @[Bitwise.scala 103:46]
+    node _T_1550 = shl(_T_1549, 1) @[Bitwise.scala 103:65]
+    node _T_1551 = not(_T_1546) @[Bitwise.scala 103:77]
+    node _T_1552 = and(_T_1550, _T_1551) @[Bitwise.scala 103:75]
+    node _T_1553 = or(_T_1548, _T_1552) @[Bitwise.scala 103:39]
+    node _T_1554 = bits(store_byteen_ext_r, 3, 3) @[lsu_dccm_ctl.scala 248:98]
+    node _T_1555 = bits(_T_1554, 0, 0) @[lsu_dccm_ctl.scala 248:102]
+    node _T_1556 = bits(store_data_pre_lo_r, 31, 24) @[lsu_dccm_ctl.scala 248:130]
+    node _T_1557 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_lo) @[lsu_dccm_ctl.scala 248:174]
+    node _T_1558 = bits(_T_1557, 0, 0) @[lsu_dccm_ctl.scala 248:199]
+    node _T_1559 = bits(io.stbuf_data_any, 31, 24) @[lsu_dccm_ctl.scala 248:223]
+    node _T_1560 = and(dccm_wren_Q, dccm_wr_bypass_d_m_lo_Q) @[lsu_dccm_ctl.scala 248:256]
+    node _T_1561 = bits(_T_1560, 0, 0) @[lsu_dccm_ctl.scala 248:283]
+    node _T_1562 = bits(dccm_wr_data_Q, 31, 24) @[lsu_dccm_ctl.scala 248:305]
+    node _T_1563 = bits(io.sec_data_lo_r, 31, 24) @[lsu_dccm_ctl.scala 248:335]
+    node _T_1564 = mux(_T_1561, _T_1562, _T_1563) @[lsu_dccm_ctl.scala 248:242]
+    node _T_1565 = mux(_T_1558, _T_1559, _T_1564) @[lsu_dccm_ctl.scala 248:148]
+    node _T_1566 = mux(_T_1555, _T_1556, _T_1565) @[lsu_dccm_ctl.scala 248:79]
+    node _T_1567 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
+    node _T_1568 = xor(UInt<8>("h0ff"), _T_1567) @[Bitwise.scala 102:21]
+    node _T_1569 = shr(_T_1566, 4) @[Bitwise.scala 103:21]
+    node _T_1570 = and(_T_1569, _T_1568) @[Bitwise.scala 103:31]
+    node _T_1571 = bits(_T_1566, 3, 0) @[Bitwise.scala 103:46]
+    node _T_1572 = shl(_T_1571, 4) @[Bitwise.scala 103:65]
+    node _T_1573 = not(_T_1568) @[Bitwise.scala 103:77]
+    node _T_1574 = and(_T_1572, _T_1573) @[Bitwise.scala 103:75]
+    node _T_1575 = or(_T_1570, _T_1574) @[Bitwise.scala 103:39]
+    node _T_1576 = bits(_T_1568, 5, 0) @[Bitwise.scala 102:28]
+    node _T_1577 = shl(_T_1576, 2) @[Bitwise.scala 102:47]
+    node _T_1578 = xor(_T_1568, _T_1577) @[Bitwise.scala 102:21]
+    node _T_1579 = shr(_T_1575, 2) @[Bitwise.scala 103:21]
+    node _T_1580 = and(_T_1579, _T_1578) @[Bitwise.scala 103:31]
+    node _T_1581 = bits(_T_1575, 5, 0) @[Bitwise.scala 103:46]
+    node _T_1582 = shl(_T_1581, 2) @[Bitwise.scala 103:65]
+    node _T_1583 = not(_T_1578) @[Bitwise.scala 103:77]
+    node _T_1584 = and(_T_1582, _T_1583) @[Bitwise.scala 103:75]
+    node _T_1585 = or(_T_1580, _T_1584) @[Bitwise.scala 103:39]
+    node _T_1586 = bits(_T_1578, 6, 0) @[Bitwise.scala 102:28]
+    node _T_1587 = shl(_T_1586, 1) @[Bitwise.scala 102:47]
+    node _T_1588 = xor(_T_1578, _T_1587) @[Bitwise.scala 102:21]
+    node _T_1589 = shr(_T_1585, 1) @[Bitwise.scala 103:21]
+    node _T_1590 = and(_T_1589, _T_1588) @[Bitwise.scala 103:31]
+    node _T_1591 = bits(_T_1585, 6, 0) @[Bitwise.scala 103:46]
+    node _T_1592 = shl(_T_1591, 1) @[Bitwise.scala 103:65]
+    node _T_1593 = not(_T_1588) @[Bitwise.scala 103:77]
+    node _T_1594 = and(_T_1592, _T_1593) @[Bitwise.scala 103:75]
+    node _T_1595 = or(_T_1590, _T_1594) @[Bitwise.scala 103:39]
+    wire _T_1596 : UInt<8>[4] @[lsu_dccm_ctl.scala 248:63]
+    _T_1596[0] <= _T_1469 @[lsu_dccm_ctl.scala 248:63]
+    _T_1596[1] <= _T_1511 @[lsu_dccm_ctl.scala 248:63]
+    _T_1596[2] <= _T_1553 @[lsu_dccm_ctl.scala 248:63]
+    _T_1596[3] <= _T_1595 @[lsu_dccm_ctl.scala 248:63]
+    node _T_1597 = cat(_T_1596[2], _T_1596[3]) @[Cat.scala 29:58]
+    node _T_1598 = cat(_T_1596[0], _T_1596[1]) @[Cat.scala 29:58]
+    node _T_1599 = cat(_T_1598, _T_1597) @[Cat.scala 29:58]
+    node _T_1600 = shl(UInt<16>("h0ffff"), 16) @[Bitwise.scala 102:47]
+    node _T_1601 = xor(UInt<32>("h0ffffffff"), _T_1600) @[Bitwise.scala 102:21]
+    node _T_1602 = shr(_T_1599, 16) @[Bitwise.scala 103:21]
+    node _T_1603 = and(_T_1602, _T_1601) @[Bitwise.scala 103:31]
+    node _T_1604 = bits(_T_1599, 15, 0) @[Bitwise.scala 103:46]
+    node _T_1605 = shl(_T_1604, 16) @[Bitwise.scala 103:65]
+    node _T_1606 = not(_T_1601) @[Bitwise.scala 103:77]
+    node _T_1607 = and(_T_1605, _T_1606) @[Bitwise.scala 103:75]
+    node _T_1608 = or(_T_1603, _T_1607) @[Bitwise.scala 103:39]
+    node _T_1609 = bits(_T_1601, 23, 0) @[Bitwise.scala 102:28]
+    node _T_1610 = shl(_T_1609, 8) @[Bitwise.scala 102:47]
+    node _T_1611 = xor(_T_1601, _T_1610) @[Bitwise.scala 102:21]
+    node _T_1612 = shr(_T_1608, 8) @[Bitwise.scala 103:21]
+    node _T_1613 = and(_T_1612, _T_1611) @[Bitwise.scala 103:31]
+    node _T_1614 = bits(_T_1608, 23, 0) @[Bitwise.scala 103:46]
+    node _T_1615 = shl(_T_1614, 8) @[Bitwise.scala 103:65]
+    node _T_1616 = not(_T_1611) @[Bitwise.scala 103:77]
+    node _T_1617 = and(_T_1615, _T_1616) @[Bitwise.scala 103:75]
+    node _T_1618 = or(_T_1613, _T_1617) @[Bitwise.scala 103:39]
+    node _T_1619 = bits(_T_1611, 27, 0) @[Bitwise.scala 102:28]
+    node _T_1620 = shl(_T_1619, 4) @[Bitwise.scala 102:47]
+    node _T_1621 = xor(_T_1611, _T_1620) @[Bitwise.scala 102:21]
+    node _T_1622 = shr(_T_1618, 4) @[Bitwise.scala 103:21]
+    node _T_1623 = and(_T_1622, _T_1621) @[Bitwise.scala 103:31]
+    node _T_1624 = bits(_T_1618, 27, 0) @[Bitwise.scala 103:46]
+    node _T_1625 = shl(_T_1624, 4) @[Bitwise.scala 103:65]
+    node _T_1626 = not(_T_1621) @[Bitwise.scala 103:77]
+    node _T_1627 = and(_T_1625, _T_1626) @[Bitwise.scala 103:75]
+    node _T_1628 = or(_T_1623, _T_1627) @[Bitwise.scala 103:39]
+    node _T_1629 = bits(_T_1621, 29, 0) @[Bitwise.scala 102:28]
+    node _T_1630 = shl(_T_1629, 2) @[Bitwise.scala 102:47]
+    node _T_1631 = xor(_T_1621, _T_1630) @[Bitwise.scala 102:21]
+    node _T_1632 = shr(_T_1628, 2) @[Bitwise.scala 103:21]
+    node _T_1633 = and(_T_1632, _T_1631) @[Bitwise.scala 103:31]
+    node _T_1634 = bits(_T_1628, 29, 0) @[Bitwise.scala 103:46]
+    node _T_1635 = shl(_T_1634, 2) @[Bitwise.scala 103:65]
+    node _T_1636 = not(_T_1631) @[Bitwise.scala 103:77]
+    node _T_1637 = and(_T_1635, _T_1636) @[Bitwise.scala 103:75]
+    node _T_1638 = or(_T_1633, _T_1637) @[Bitwise.scala 103:39]
+    node _T_1639 = bits(_T_1631, 30, 0) @[Bitwise.scala 102:28]
+    node _T_1640 = shl(_T_1639, 1) @[Bitwise.scala 102:47]
+    node _T_1641 = xor(_T_1631, _T_1640) @[Bitwise.scala 102:21]
+    node _T_1642 = shr(_T_1638, 1) @[Bitwise.scala 103:21]
+    node _T_1643 = and(_T_1642, _T_1641) @[Bitwise.scala 103:31]
+    node _T_1644 = bits(_T_1638, 30, 0) @[Bitwise.scala 103:46]
+    node _T_1645 = shl(_T_1644, 1) @[Bitwise.scala 103:65]
+    node _T_1646 = not(_T_1641) @[Bitwise.scala 103:77]
+    node _T_1647 = and(_T_1645, _T_1646) @[Bitwise.scala 103:75]
+    node _T_1648 = or(_T_1643, _T_1647) @[Bitwise.scala 103:39]
+    io.store_datafn_lo_r <= _T_1648 @[lsu_dccm_ctl.scala 248:29]
+    node _T_1649 = bits(store_byteen_ext_r, 4, 4) @[lsu_dccm_ctl.scala 249:98]
+    node _T_1650 = bits(_T_1649, 0, 0) @[lsu_dccm_ctl.scala 249:104]
+    node _T_1651 = bits(store_data_pre_hi_r, 7, 0) @[lsu_dccm_ctl.scala 249:130]
+    node _T_1652 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_lo) @[lsu_dccm_ctl.scala 249:174]
+    node _T_1653 = bits(_T_1652, 0, 0) @[lsu_dccm_ctl.scala 249:199]
+    node _T_1654 = bits(io.stbuf_data_any, 7, 0) @[lsu_dccm_ctl.scala 249:223]
+    node _T_1655 = and(dccm_wren_Q, dccm_wr_bypass_d_m_hi_Q) @[lsu_dccm_ctl.scala 249:256]
+    node _T_1656 = bits(_T_1655, 0, 0) @[lsu_dccm_ctl.scala 249:283]
+    node _T_1657 = bits(dccm_wr_data_Q, 7, 0) @[lsu_dccm_ctl.scala 249:305]
+    node _T_1658 = bits(io.sec_data_hi_r, 7, 0) @[lsu_dccm_ctl.scala 249:335]
+    node _T_1659 = mux(_T_1656, _T_1657, _T_1658) @[lsu_dccm_ctl.scala 249:242]
+    node _T_1660 = mux(_T_1653, _T_1654, _T_1659) @[lsu_dccm_ctl.scala 249:148]
+    node _T_1661 = mux(_T_1650, _T_1651, _T_1660) @[lsu_dccm_ctl.scala 249:79]
+    node _T_1662 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
+    node _T_1663 = xor(UInt<8>("h0ff"), _T_1662) @[Bitwise.scala 102:21]
+    node _T_1664 = shr(_T_1661, 4) @[Bitwise.scala 103:21]
+    node _T_1665 = and(_T_1664, _T_1663) @[Bitwise.scala 103:31]
+    node _T_1666 = bits(_T_1661, 3, 0) @[Bitwise.scala 103:46]
+    node _T_1667 = shl(_T_1666, 4) @[Bitwise.scala 103:65]
+    node _T_1668 = not(_T_1663) @[Bitwise.scala 103:77]
+    node _T_1669 = and(_T_1667, _T_1668) @[Bitwise.scala 103:75]
+    node _T_1670 = or(_T_1665, _T_1669) @[Bitwise.scala 103:39]
+    node _T_1671 = bits(_T_1663, 5, 0) @[Bitwise.scala 102:28]
+    node _T_1672 = shl(_T_1671, 2) @[Bitwise.scala 102:47]
+    node _T_1673 = xor(_T_1663, _T_1672) @[Bitwise.scala 102:21]
+    node _T_1674 = shr(_T_1670, 2) @[Bitwise.scala 103:21]
+    node _T_1675 = and(_T_1674, _T_1673) @[Bitwise.scala 103:31]
+    node _T_1676 = bits(_T_1670, 5, 0) @[Bitwise.scala 103:46]
+    node _T_1677 = shl(_T_1676, 2) @[Bitwise.scala 103:65]
+    node _T_1678 = not(_T_1673) @[Bitwise.scala 103:77]
+    node _T_1679 = and(_T_1677, _T_1678) @[Bitwise.scala 103:75]
+    node _T_1680 = or(_T_1675, _T_1679) @[Bitwise.scala 103:39]
+    node _T_1681 = bits(_T_1673, 6, 0) @[Bitwise.scala 102:28]
+    node _T_1682 = shl(_T_1681, 1) @[Bitwise.scala 102:47]
+    node _T_1683 = xor(_T_1673, _T_1682) @[Bitwise.scala 102:21]
+    node _T_1684 = shr(_T_1680, 1) @[Bitwise.scala 103:21]
+    node _T_1685 = and(_T_1684, _T_1683) @[Bitwise.scala 103:31]
+    node _T_1686 = bits(_T_1680, 6, 0) @[Bitwise.scala 103:46]
+    node _T_1687 = shl(_T_1686, 1) @[Bitwise.scala 103:65]
+    node _T_1688 = not(_T_1683) @[Bitwise.scala 103:77]
+    node _T_1689 = and(_T_1687, _T_1688) @[Bitwise.scala 103:75]
+    node _T_1690 = or(_T_1685, _T_1689) @[Bitwise.scala 103:39]
+    node _T_1691 = bits(store_byteen_ext_r, 5, 5) @[lsu_dccm_ctl.scala 249:98]
+    node _T_1692 = bits(_T_1691, 0, 0) @[lsu_dccm_ctl.scala 249:104]
+    node _T_1693 = bits(store_data_pre_hi_r, 15, 8) @[lsu_dccm_ctl.scala 249:130]
+    node _T_1694 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_lo) @[lsu_dccm_ctl.scala 249:174]
+    node _T_1695 = bits(_T_1694, 0, 0) @[lsu_dccm_ctl.scala 249:199]
+    node _T_1696 = bits(io.stbuf_data_any, 15, 8) @[lsu_dccm_ctl.scala 249:223]
+    node _T_1697 = and(dccm_wren_Q, dccm_wr_bypass_d_m_hi_Q) @[lsu_dccm_ctl.scala 249:256]
+    node _T_1698 = bits(_T_1697, 0, 0) @[lsu_dccm_ctl.scala 249:283]
+    node _T_1699 = bits(dccm_wr_data_Q, 15, 8) @[lsu_dccm_ctl.scala 249:305]
+    node _T_1700 = bits(io.sec_data_hi_r, 15, 8) @[lsu_dccm_ctl.scala 249:335]
+    node _T_1701 = mux(_T_1698, _T_1699, _T_1700) @[lsu_dccm_ctl.scala 249:242]
+    node _T_1702 = mux(_T_1695, _T_1696, _T_1701) @[lsu_dccm_ctl.scala 249:148]
+    node _T_1703 = mux(_T_1692, _T_1693, _T_1702) @[lsu_dccm_ctl.scala 249:79]
+    node _T_1704 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
+    node _T_1705 = xor(UInt<8>("h0ff"), _T_1704) @[Bitwise.scala 102:21]
+    node _T_1706 = shr(_T_1703, 4) @[Bitwise.scala 103:21]
+    node _T_1707 = and(_T_1706, _T_1705) @[Bitwise.scala 103:31]
+    node _T_1708 = bits(_T_1703, 3, 0) @[Bitwise.scala 103:46]
+    node _T_1709 = shl(_T_1708, 4) @[Bitwise.scala 103:65]
+    node _T_1710 = not(_T_1705) @[Bitwise.scala 103:77]
+    node _T_1711 = and(_T_1709, _T_1710) @[Bitwise.scala 103:75]
+    node _T_1712 = or(_T_1707, _T_1711) @[Bitwise.scala 103:39]
+    node _T_1713 = bits(_T_1705, 5, 0) @[Bitwise.scala 102:28]
+    node _T_1714 = shl(_T_1713, 2) @[Bitwise.scala 102:47]
+    node _T_1715 = xor(_T_1705, _T_1714) @[Bitwise.scala 102:21]
+    node _T_1716 = shr(_T_1712, 2) @[Bitwise.scala 103:21]
+    node _T_1717 = and(_T_1716, _T_1715) @[Bitwise.scala 103:31]
+    node _T_1718 = bits(_T_1712, 5, 0) @[Bitwise.scala 103:46]
+    node _T_1719 = shl(_T_1718, 2) @[Bitwise.scala 103:65]
+    node _T_1720 = not(_T_1715) @[Bitwise.scala 103:77]
+    node _T_1721 = and(_T_1719, _T_1720) @[Bitwise.scala 103:75]
+    node _T_1722 = or(_T_1717, _T_1721) @[Bitwise.scala 103:39]
+    node _T_1723 = bits(_T_1715, 6, 0) @[Bitwise.scala 102:28]
+    node _T_1724 = shl(_T_1723, 1) @[Bitwise.scala 102:47]
+    node _T_1725 = xor(_T_1715, _T_1724) @[Bitwise.scala 102:21]
+    node _T_1726 = shr(_T_1722, 1) @[Bitwise.scala 103:21]
+    node _T_1727 = and(_T_1726, _T_1725) @[Bitwise.scala 103:31]
+    node _T_1728 = bits(_T_1722, 6, 0) @[Bitwise.scala 103:46]
+    node _T_1729 = shl(_T_1728, 1) @[Bitwise.scala 103:65]
+    node _T_1730 = not(_T_1725) @[Bitwise.scala 103:77]
+    node _T_1731 = and(_T_1729, _T_1730) @[Bitwise.scala 103:75]
+    node _T_1732 = or(_T_1727, _T_1731) @[Bitwise.scala 103:39]
+    node _T_1733 = bits(store_byteen_ext_r, 6, 6) @[lsu_dccm_ctl.scala 249:98]
+    node _T_1734 = bits(_T_1733, 0, 0) @[lsu_dccm_ctl.scala 249:104]
+    node _T_1735 = bits(store_data_pre_hi_r, 23, 16) @[lsu_dccm_ctl.scala 249:130]
+    node _T_1736 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_lo) @[lsu_dccm_ctl.scala 249:174]
+    node _T_1737 = bits(_T_1736, 0, 0) @[lsu_dccm_ctl.scala 249:199]
+    node _T_1738 = bits(io.stbuf_data_any, 23, 16) @[lsu_dccm_ctl.scala 249:223]
+    node _T_1739 = and(dccm_wren_Q, dccm_wr_bypass_d_m_hi_Q) @[lsu_dccm_ctl.scala 249:256]
+    node _T_1740 = bits(_T_1739, 0, 0) @[lsu_dccm_ctl.scala 249:283]
+    node _T_1741 = bits(dccm_wr_data_Q, 23, 16) @[lsu_dccm_ctl.scala 249:305]
+    node _T_1742 = bits(io.sec_data_hi_r, 23, 16) @[lsu_dccm_ctl.scala 249:335]
+    node _T_1743 = mux(_T_1740, _T_1741, _T_1742) @[lsu_dccm_ctl.scala 249:242]
+    node _T_1744 = mux(_T_1737, _T_1738, _T_1743) @[lsu_dccm_ctl.scala 249:148]
+    node _T_1745 = mux(_T_1734, _T_1735, _T_1744) @[lsu_dccm_ctl.scala 249:79]
+    node _T_1746 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
+    node _T_1747 = xor(UInt<8>("h0ff"), _T_1746) @[Bitwise.scala 102:21]
+    node _T_1748 = shr(_T_1745, 4) @[Bitwise.scala 103:21]
+    node _T_1749 = and(_T_1748, _T_1747) @[Bitwise.scala 103:31]
+    node _T_1750 = bits(_T_1745, 3, 0) @[Bitwise.scala 103:46]
+    node _T_1751 = shl(_T_1750, 4) @[Bitwise.scala 103:65]
+    node _T_1752 = not(_T_1747) @[Bitwise.scala 103:77]
+    node _T_1753 = and(_T_1751, _T_1752) @[Bitwise.scala 103:75]
+    node _T_1754 = or(_T_1749, _T_1753) @[Bitwise.scala 103:39]
+    node _T_1755 = bits(_T_1747, 5, 0) @[Bitwise.scala 102:28]
+    node _T_1756 = shl(_T_1755, 2) @[Bitwise.scala 102:47]
+    node _T_1757 = xor(_T_1747, _T_1756) @[Bitwise.scala 102:21]
+    node _T_1758 = shr(_T_1754, 2) @[Bitwise.scala 103:21]
+    node _T_1759 = and(_T_1758, _T_1757) @[Bitwise.scala 103:31]
+    node _T_1760 = bits(_T_1754, 5, 0) @[Bitwise.scala 103:46]
+    node _T_1761 = shl(_T_1760, 2) @[Bitwise.scala 103:65]
+    node _T_1762 = not(_T_1757) @[Bitwise.scala 103:77]
+    node _T_1763 = and(_T_1761, _T_1762) @[Bitwise.scala 103:75]
+    node _T_1764 = or(_T_1759, _T_1763) @[Bitwise.scala 103:39]
+    node _T_1765 = bits(_T_1757, 6, 0) @[Bitwise.scala 102:28]
+    node _T_1766 = shl(_T_1765, 1) @[Bitwise.scala 102:47]
+    node _T_1767 = xor(_T_1757, _T_1766) @[Bitwise.scala 102:21]
+    node _T_1768 = shr(_T_1764, 1) @[Bitwise.scala 103:21]
+    node _T_1769 = and(_T_1768, _T_1767) @[Bitwise.scala 103:31]
+    node _T_1770 = bits(_T_1764, 6, 0) @[Bitwise.scala 103:46]
+    node _T_1771 = shl(_T_1770, 1) @[Bitwise.scala 103:65]
+    node _T_1772 = not(_T_1767) @[Bitwise.scala 103:77]
+    node _T_1773 = and(_T_1771, _T_1772) @[Bitwise.scala 103:75]
+    node _T_1774 = or(_T_1769, _T_1773) @[Bitwise.scala 103:39]
+    node _T_1775 = bits(store_byteen_ext_r, 7, 7) @[lsu_dccm_ctl.scala 249:98]
+    node _T_1776 = bits(_T_1775, 0, 0) @[lsu_dccm_ctl.scala 249:104]
+    node _T_1777 = bits(store_data_pre_hi_r, 31, 24) @[lsu_dccm_ctl.scala 249:130]
+    node _T_1778 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_lo) @[lsu_dccm_ctl.scala 249:174]
+    node _T_1779 = bits(_T_1778, 0, 0) @[lsu_dccm_ctl.scala 249:199]
+    node _T_1780 = bits(io.stbuf_data_any, 31, 24) @[lsu_dccm_ctl.scala 249:223]
+    node _T_1781 = and(dccm_wren_Q, dccm_wr_bypass_d_m_hi_Q) @[lsu_dccm_ctl.scala 249:256]
+    node _T_1782 = bits(_T_1781, 0, 0) @[lsu_dccm_ctl.scala 249:283]
+    node _T_1783 = bits(dccm_wr_data_Q, 31, 24) @[lsu_dccm_ctl.scala 249:305]
+    node _T_1784 = bits(io.sec_data_hi_r, 31, 24) @[lsu_dccm_ctl.scala 249:335]
+    node _T_1785 = mux(_T_1782, _T_1783, _T_1784) @[lsu_dccm_ctl.scala 249:242]
+    node _T_1786 = mux(_T_1779, _T_1780, _T_1785) @[lsu_dccm_ctl.scala 249:148]
+    node _T_1787 = mux(_T_1776, _T_1777, _T_1786) @[lsu_dccm_ctl.scala 249:79]
+    node _T_1788 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
+    node _T_1789 = xor(UInt<8>("h0ff"), _T_1788) @[Bitwise.scala 102:21]
+    node _T_1790 = shr(_T_1787, 4) @[Bitwise.scala 103:21]
+    node _T_1791 = and(_T_1790, _T_1789) @[Bitwise.scala 103:31]
+    node _T_1792 = bits(_T_1787, 3, 0) @[Bitwise.scala 103:46]
+    node _T_1793 = shl(_T_1792, 4) @[Bitwise.scala 103:65]
+    node _T_1794 = not(_T_1789) @[Bitwise.scala 103:77]
+    node _T_1795 = and(_T_1793, _T_1794) @[Bitwise.scala 103:75]
+    node _T_1796 = or(_T_1791, _T_1795) @[Bitwise.scala 103:39]
+    node _T_1797 = bits(_T_1789, 5, 0) @[Bitwise.scala 102:28]
+    node _T_1798 = shl(_T_1797, 2) @[Bitwise.scala 102:47]
+    node _T_1799 = xor(_T_1789, _T_1798) @[Bitwise.scala 102:21]
+    node _T_1800 = shr(_T_1796, 2) @[Bitwise.scala 103:21]
+    node _T_1801 = and(_T_1800, _T_1799) @[Bitwise.scala 103:31]
+    node _T_1802 = bits(_T_1796, 5, 0) @[Bitwise.scala 103:46]
+    node _T_1803 = shl(_T_1802, 2) @[Bitwise.scala 103:65]
+    node _T_1804 = not(_T_1799) @[Bitwise.scala 103:77]
+    node _T_1805 = and(_T_1803, _T_1804) @[Bitwise.scala 103:75]
+    node _T_1806 = or(_T_1801, _T_1805) @[Bitwise.scala 103:39]
+    node _T_1807 = bits(_T_1799, 6, 0) @[Bitwise.scala 102:28]
+    node _T_1808 = shl(_T_1807, 1) @[Bitwise.scala 102:47]
+    node _T_1809 = xor(_T_1799, _T_1808) @[Bitwise.scala 102:21]
+    node _T_1810 = shr(_T_1806, 1) @[Bitwise.scala 103:21]
+    node _T_1811 = and(_T_1810, _T_1809) @[Bitwise.scala 103:31]
+    node _T_1812 = bits(_T_1806, 6, 0) @[Bitwise.scala 103:46]
+    node _T_1813 = shl(_T_1812, 1) @[Bitwise.scala 103:65]
+    node _T_1814 = not(_T_1809) @[Bitwise.scala 103:77]
+    node _T_1815 = and(_T_1813, _T_1814) @[Bitwise.scala 103:75]
+    node _T_1816 = or(_T_1811, _T_1815) @[Bitwise.scala 103:39]
+    wire _T_1817 : UInt<8>[4] @[lsu_dccm_ctl.scala 249:63]
+    _T_1817[0] <= _T_1690 @[lsu_dccm_ctl.scala 249:63]
+    _T_1817[1] <= _T_1732 @[lsu_dccm_ctl.scala 249:63]
+    _T_1817[2] <= _T_1774 @[lsu_dccm_ctl.scala 249:63]
+    _T_1817[3] <= _T_1816 @[lsu_dccm_ctl.scala 249:63]
+    node _T_1818 = cat(_T_1817[2], _T_1817[3]) @[Cat.scala 29:58]
+    node _T_1819 = cat(_T_1817[0], _T_1817[1]) @[Cat.scala 29:58]
+    node _T_1820 = cat(_T_1819, _T_1818) @[Cat.scala 29:58]
+    node _T_1821 = shl(UInt<16>("h0ffff"), 16) @[Bitwise.scala 102:47]
+    node _T_1822 = xor(UInt<32>("h0ffffffff"), _T_1821) @[Bitwise.scala 102:21]
+    node _T_1823 = shr(_T_1820, 16) @[Bitwise.scala 103:21]
+    node _T_1824 = and(_T_1823, _T_1822) @[Bitwise.scala 103:31]
+    node _T_1825 = bits(_T_1820, 15, 0) @[Bitwise.scala 103:46]
+    node _T_1826 = shl(_T_1825, 16) @[Bitwise.scala 103:65]
+    node _T_1827 = not(_T_1822) @[Bitwise.scala 103:77]
+    node _T_1828 = and(_T_1826, _T_1827) @[Bitwise.scala 103:75]
+    node _T_1829 = or(_T_1824, _T_1828) @[Bitwise.scala 103:39]
+    node _T_1830 = bits(_T_1822, 23, 0) @[Bitwise.scala 102:28]
+    node _T_1831 = shl(_T_1830, 8) @[Bitwise.scala 102:47]
+    node _T_1832 = xor(_T_1822, _T_1831) @[Bitwise.scala 102:21]
+    node _T_1833 = shr(_T_1829, 8) @[Bitwise.scala 103:21]
+    node _T_1834 = and(_T_1833, _T_1832) @[Bitwise.scala 103:31]
+    node _T_1835 = bits(_T_1829, 23, 0) @[Bitwise.scala 103:46]
+    node _T_1836 = shl(_T_1835, 8) @[Bitwise.scala 103:65]
+    node _T_1837 = not(_T_1832) @[Bitwise.scala 103:77]
+    node _T_1838 = and(_T_1836, _T_1837) @[Bitwise.scala 103:75]
+    node _T_1839 = or(_T_1834, _T_1838) @[Bitwise.scala 103:39]
+    node _T_1840 = bits(_T_1832, 27, 0) @[Bitwise.scala 102:28]
+    node _T_1841 = shl(_T_1840, 4) @[Bitwise.scala 102:47]
+    node _T_1842 = xor(_T_1832, _T_1841) @[Bitwise.scala 102:21]
+    node _T_1843 = shr(_T_1839, 4) @[Bitwise.scala 103:21]
+    node _T_1844 = and(_T_1843, _T_1842) @[Bitwise.scala 103:31]
+    node _T_1845 = bits(_T_1839, 27, 0) @[Bitwise.scala 103:46]
+    node _T_1846 = shl(_T_1845, 4) @[Bitwise.scala 103:65]
+    node _T_1847 = not(_T_1842) @[Bitwise.scala 103:77]
+    node _T_1848 = and(_T_1846, _T_1847) @[Bitwise.scala 103:75]
+    node _T_1849 = or(_T_1844, _T_1848) @[Bitwise.scala 103:39]
+    node _T_1850 = bits(_T_1842, 29, 0) @[Bitwise.scala 102:28]
+    node _T_1851 = shl(_T_1850, 2) @[Bitwise.scala 102:47]
+    node _T_1852 = xor(_T_1842, _T_1851) @[Bitwise.scala 102:21]
+    node _T_1853 = shr(_T_1849, 2) @[Bitwise.scala 103:21]
+    node _T_1854 = and(_T_1853, _T_1852) @[Bitwise.scala 103:31]
+    node _T_1855 = bits(_T_1849, 29, 0) @[Bitwise.scala 103:46]
+    node _T_1856 = shl(_T_1855, 2) @[Bitwise.scala 103:65]
+    node _T_1857 = not(_T_1852) @[Bitwise.scala 103:77]
+    node _T_1858 = and(_T_1856, _T_1857) @[Bitwise.scala 103:75]
+    node _T_1859 = or(_T_1854, _T_1858) @[Bitwise.scala 103:39]
+    node _T_1860 = bits(_T_1852, 30, 0) @[Bitwise.scala 102:28]
+    node _T_1861 = shl(_T_1860, 1) @[Bitwise.scala 102:47]
+    node _T_1862 = xor(_T_1852, _T_1861) @[Bitwise.scala 102:21]
+    node _T_1863 = shr(_T_1859, 1) @[Bitwise.scala 103:21]
+    node _T_1864 = and(_T_1863, _T_1862) @[Bitwise.scala 103:31]
+    node _T_1865 = bits(_T_1859, 30, 0) @[Bitwise.scala 103:46]
+    node _T_1866 = shl(_T_1865, 1) @[Bitwise.scala 103:65]
+    node _T_1867 = not(_T_1862) @[Bitwise.scala 103:77]
+    node _T_1868 = and(_T_1866, _T_1867) @[Bitwise.scala 103:75]
+    node _T_1869 = or(_T_1864, _T_1868) @[Bitwise.scala 103:39]
+    io.store_datafn_hi_r <= _T_1869 @[lsu_dccm_ctl.scala 249:29]
+    reg _T_1870 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_dccm_ctl.scala 250:69]
+    _T_1870 <= io.lsu_stbuf_commit_any @[lsu_dccm_ctl.scala 250:69]
+    dccm_wren_Q <= _T_1870 @[lsu_dccm_ctl.scala 250:29]
+    node _T_1871 = or(io.lsu_stbuf_commit_any, io.clk_override) @[lsu_dccm_ctl.scala 251:82]
+    node _T_1872 = bits(_T_1871, 0, 0) @[lsu_dccm_ctl.scala 251:101]
+    node _T_1873 = bits(io.scan_mode, 0, 0) @[lsu_dccm_ctl.scala 251:127]
+    inst rvclkhdr_7 of rvclkhdr_10 @[lib.scala 390:23]
+    rvclkhdr_7.clock <= clock
+    rvclkhdr_7.reset <= reset
+    rvclkhdr_7.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr_7.io.en <= _T_1872 @[lib.scala 393:17]
+    rvclkhdr_7.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg _T_1874 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_1872 : @[Reg.scala 28:19]
+      _T_1874 <= io.stbuf_data_any @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    dccm_wr_data_Q <= _T_1874 @[lsu_dccm_ctl.scala 251:29]
+    reg _T_1875 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_dccm_ctl.scala 252:69]
+    _T_1875 <= dccm_wr_bypass_d_m_lo @[lsu_dccm_ctl.scala 252:69]
+    dccm_wr_bypass_d_m_lo_Q <= _T_1875 @[lsu_dccm_ctl.scala 252:29]
+    reg _T_1876 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_dccm_ctl.scala 253:69]
+    _T_1876 <= dccm_wr_bypass_d_m_hi @[lsu_dccm_ctl.scala 253:69]
+    dccm_wr_bypass_d_m_hi_Q <= _T_1876 @[lsu_dccm_ctl.scala 253:29]
+    reg _T_1877 : UInt, io.lsu_store_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_dccm_ctl.scala 254:72]
+    _T_1877 <= io.store_data_m @[lsu_dccm_ctl.scala 254:72]
+    io.store_data_r <= _T_1877 @[lsu_dccm_ctl.scala 254:29]
+    node _T_1878 = bits(io.dccm.rd_data_lo, 31, 0) @[lsu_dccm_ctl.scala 267:48]
+    io.dccm_rdata_lo_m <= _T_1878 @[lsu_dccm_ctl.scala 267:27]
+    node _T_1879 = bits(io.dccm.rd_data_hi, 31, 0) @[lsu_dccm_ctl.scala 268:48]
+    io.dccm_rdata_hi_m <= _T_1879 @[lsu_dccm_ctl.scala 268:27]
+    node _T_1880 = bits(io.dccm.rd_data_lo, 38, 32) @[lsu_dccm_ctl.scala 269:48]
+    io.dccm_data_ecc_lo_m <= _T_1880 @[lsu_dccm_ctl.scala 269:27]
+    node _T_1881 = bits(io.dccm.rd_data_hi, 38, 32) @[lsu_dccm_ctl.scala 270:48]
+    io.dccm_data_ecc_hi_m <= _T_1881 @[lsu_dccm_ctl.scala 270:27]
+    node _T_1882 = and(io.lsu_pkt_r.valid, io.lsu_pkt_r.bits.store) @[lsu_dccm_ctl.scala 272:58]
+    node _T_1883 = and(_T_1882, io.addr_in_pic_r) @[lsu_dccm_ctl.scala 272:84]
+    node _T_1884 = and(_T_1883, io.lsu_commit_r) @[lsu_dccm_ctl.scala 272:103]
+    node _T_1885 = or(_T_1884, io.dma_pic_wen) @[lsu_dccm_ctl.scala 272:122]
+    io.lsu_pic.picm_wren <= _T_1885 @[lsu_dccm_ctl.scala 272:35]
+    node _T_1886 = and(io.lsu_pkt_d.valid, io.lsu_pkt_d.bits.load) @[lsu_dccm_ctl.scala 273:58]
+    node _T_1887 = and(_T_1886, io.addr_in_pic_d) @[lsu_dccm_ctl.scala 273:84]
+    io.lsu_pic.picm_rden <= _T_1887 @[lsu_dccm_ctl.scala 273:35]
+    node _T_1888 = and(io.lsu_pkt_d.valid, io.lsu_pkt_d.bits.store) @[lsu_dccm_ctl.scala 274:58]
+    node _T_1889 = and(_T_1888, io.addr_in_pic_d) @[lsu_dccm_ctl.scala 274:84]
+    io.lsu_pic.picm_mken <= _T_1889 @[lsu_dccm_ctl.scala 274:35]
+    node _T_1890 = mux(UInt<1>("h00"), UInt<17>("h01ffff"), UInt<17>("h00")) @[Bitwise.scala 72:12]
+    node _T_1891 = bits(io.lsu_addr_d, 14, 0) @[lsu_dccm_ctl.scala 275:103]
+    node _T_1892 = cat(_T_1890, _T_1891) @[Cat.scala 29:58]
+    node _T_1893 = or(UInt<32>("h0f00c0000"), _T_1892) @[lsu_dccm_ctl.scala 275:62]
+    io.lsu_pic.picm_rdaddr <= _T_1893 @[lsu_dccm_ctl.scala 275:35]
+    node _T_1894 = mux(UInt<1>("h00"), UInt<17>("h01ffff"), UInt<17>("h00")) @[Bitwise.scala 72:12]
+    node _T_1895 = bits(io.dma_pic_wen, 0, 0) @[lsu_dccm_ctl.scala 276:109]
+    node _T_1896 = bits(io.dma_dccm_ctl.dma_mem_addr, 14, 0) @[lsu_dccm_ctl.scala 276:144]
+    node _T_1897 = bits(io.lsu_addr_r, 14, 0) @[lsu_dccm_ctl.scala 276:172]
+    node _T_1898 = mux(_T_1895, _T_1896, _T_1897) @[lsu_dccm_ctl.scala 276:93]
+    node _T_1899 = cat(_T_1894, _T_1898) @[Cat.scala 29:58]
+    node _T_1900 = or(UInt<32>("h0f00c0000"), _T_1899) @[lsu_dccm_ctl.scala 276:62]
+    io.lsu_pic.picm_wraddr <= _T_1900 @[lsu_dccm_ctl.scala 276:35]
+    node _T_1901 = bits(picm_rd_data_m, 31, 0) @[lsu_dccm_ctl.scala 277:44]
+    io.picm_mask_data_m <= _T_1901 @[lsu_dccm_ctl.scala 277:27]
+    node _T_1902 = bits(io.dma_pic_wen, 0, 0) @[lsu_dccm_ctl.scala 278:57]
+    node _T_1903 = bits(io.dma_dccm_ctl.dma_mem_wdata, 31, 0) @[lsu_dccm_ctl.scala 278:93]
+    node _T_1904 = bits(io.store_datafn_lo_r, 31, 0) @[lsu_dccm_ctl.scala 278:120]
+    node _T_1905 = mux(_T_1902, _T_1903, _T_1904) @[lsu_dccm_ctl.scala 278:41]
+    io.lsu_pic.picm_wr_data <= _T_1905 @[lsu_dccm_ctl.scala 278:35]
+    reg _T_1906 : UInt, io.lsu_c2_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_dccm_ctl.scala 280:61]
+    _T_1906 <= lsu_dccm_rden_d @[lsu_dccm_ctl.scala 280:61]
+    io.lsu_dccm_rden_m <= _T_1906 @[lsu_dccm_ctl.scala 280:24]
+    reg _T_1907 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_dccm_ctl.scala 281:61]
+    _T_1907 <= io.lsu_dccm_rden_m @[lsu_dccm_ctl.scala 281:61]
+    io.lsu_dccm_rden_r <= _T_1907 @[lsu_dccm_ctl.scala 281:24]
+    reg _T_1908 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_dccm_ctl.scala 282:73]
+    _T_1908 <= io.lsu_double_ecc_error_r @[lsu_dccm_ctl.scala 282:73]
+    lsu_double_ecc_error_r_ff <= _T_1908 @[lsu_dccm_ctl.scala 282:33]
+    reg _T_1909 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_dccm_ctl.scala 283:73]
+    _T_1909 <= ld_single_ecc_error_hi_r_ns @[lsu_dccm_ctl.scala 283:73]
+    ld_single_ecc_error_hi_r_ff <= _T_1909 @[lsu_dccm_ctl.scala 283:33]
+    reg _T_1910 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_dccm_ctl.scala 284:73]
+    _T_1910 <= ld_single_ecc_error_lo_r_ns @[lsu_dccm_ctl.scala 284:73]
+    ld_single_ecc_error_lo_r_ff <= _T_1910 @[lsu_dccm_ctl.scala 284:33]
+    node _T_1911 = bits(io.end_addr_r, 15, 0) @[lsu_dccm_ctl.scala 285:48]
+    node _T_1912 = or(io.ld_single_ecc_error_r, io.clk_override) @[lsu_dccm_ctl.scala 285:90]
+    node _T_1913 = bits(_T_1912, 0, 0) @[lib.scala 8:44]
+    node _T_1914 = bits(io.scan_mode, 0, 0) @[lsu_dccm_ctl.scala 285:128]
+    inst rvclkhdr_8 of rvclkhdr_11 @[lib.scala 390:23]
+    rvclkhdr_8.clock <= clock
+    rvclkhdr_8.reset <= reset
+    rvclkhdr_8.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr_8.io.en <= _T_1913 @[lib.scala 393:17]
+    rvclkhdr_8.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg _T_1915 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_1913 : @[Reg.scala 28:19]
+      _T_1915 <= _T_1911 @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    ld_sec_addr_hi_r_ff <= _T_1915 @[lsu_dccm_ctl.scala 285:25]
+    node _T_1916 = bits(io.lsu_addr_r, 15, 0) @[lsu_dccm_ctl.scala 286:48]
+    node _T_1917 = or(io.ld_single_ecc_error_r, io.clk_override) @[lsu_dccm_ctl.scala 286:90]
+    node _T_1918 = bits(_T_1917, 0, 0) @[lib.scala 8:44]
+    node _T_1919 = bits(io.scan_mode, 0, 0) @[lsu_dccm_ctl.scala 286:128]
+    inst rvclkhdr_9 of rvclkhdr_12 @[lib.scala 390:23]
+    rvclkhdr_9.clock <= clock
+    rvclkhdr_9.reset <= reset
+    rvclkhdr_9.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr_9.io.en <= _T_1918 @[lib.scala 393:17]
+    rvclkhdr_9.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg _T_1920 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_1918 : @[Reg.scala 28:19]
+      _T_1920 <= _T_1916 @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    ld_sec_addr_lo_r_ff <= _T_1920 @[lsu_dccm_ctl.scala 286:25]
+    
   extmodule gated_latch_13 : 
     output Q : Clock
     input CK : Clock
@@ -3393,10 +3429,130 @@ circuit lsu :
     clkhdr.EN <= io.en @[lib.scala 337:18]
     clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
     
+  extmodule gated_latch_16 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr_16 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch_16 @[lib.scala 334:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 335:14]
+    clkhdr.CK <= io.clk @[lib.scala 336:18]
+    clkhdr.EN <= io.en @[lib.scala 337:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
+    
+  extmodule gated_latch_17 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr_17 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch_17 @[lib.scala 334:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 335:14]
+    clkhdr.CK <= io.clk @[lib.scala 336:18]
+    clkhdr.EN <= io.en @[lib.scala 337:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
+    
+  extmodule gated_latch_18 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr_18 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch_18 @[lib.scala 334:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 335:14]
+    clkhdr.CK <= io.clk @[lib.scala 336:18]
+    clkhdr.EN <= io.en @[lib.scala 337:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
+    
+  extmodule gated_latch_19 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr_19 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch_19 @[lib.scala 334:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 335:14]
+    clkhdr.CK <= io.clk @[lib.scala 336:18]
+    clkhdr.EN <= io.en @[lib.scala 337:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
+    
+  extmodule gated_latch_20 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr_20 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch_20 @[lib.scala 334:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 335:14]
+    clkhdr.CK <= io.clk @[lib.scala 336:18]
+    clkhdr.EN <= io.en @[lib.scala 337:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
+    
   module lsu_stbuf : 
     input clock : Clock
     input reset : AsyncReset
-    output io : {flip lsu_stbuf_c1_clk : Clock, flip lsu_free_c2_clk : Clock, flip lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_pkt_r : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip store_stbuf_reqvld_r : UInt<1>, flip lsu_commit_r : UInt<1>, flip dec_lsu_valid_raw_d : UInt<1>, flip store_data_hi_r : UInt<32>, flip store_data_lo_r : UInt<32>, flip store_datafn_hi_r : UInt<32>, flip store_datafn_lo_r : UInt<32>, flip lsu_stbuf_commit_any : UInt<1>, flip lsu_addr_d : UInt<16>, flip lsu_addr_m : UInt<32>, flip lsu_addr_r : UInt<32>, flip end_addr_d : UInt<16>, flip end_addr_m : UInt<32>, flip end_addr_r : UInt<32>, flip ldst_dual_d : UInt<1>, flip ldst_dual_m : UInt<1>, flip ldst_dual_r : UInt<1>, flip addr_in_dccm_m : UInt<1>, flip addr_in_dccm_r : UInt<1>, flip lsu_cmpen_m : UInt<1>, flip scan_mode : UInt<1>, stbuf_reqvld_any : UInt<1>, stbuf_reqvld_flushed_any : UInt<1>, stbuf_addr_any : UInt<16>, stbuf_data_any : UInt<32>, lsu_stbuf_full_any : UInt<1>, lsu_stbuf_empty_any : UInt<1>, ldst_stbuf_reqvld_r : UInt<1>, stbuf_fwddata_hi_m : UInt<32>, stbuf_fwddata_lo_m : UInt<32>, stbuf_fwdbyteen_hi_m : UInt<4>, stbuf_fwdbyteen_lo_m : UInt<4>}
+    output io : {flip lsu_stbuf_c1_clk : Clock, flip lsu_free_c2_clk : Clock, flip lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_pkt_r : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip store_stbuf_reqvld_r : UInt<1>, flip lsu_commit_r : UInt<1>, flip dec_lsu_valid_raw_d : UInt<1>, flip store_data_hi_r : UInt<32>, flip store_data_lo_r : UInt<32>, flip store_datafn_hi_r : UInt<32>, flip store_datafn_lo_r : UInt<32>, flip lsu_stbuf_commit_any : UInt<1>, flip lsu_addr_d : UInt<16>, flip lsu_addr_m : UInt<32>, flip lsu_addr_r : UInt<32>, flip end_addr_d : UInt<16>, flip end_addr_m : UInt<32>, flip end_addr_r : UInt<32>, flip ldst_dual_d : UInt<1>, flip ldst_dual_m : UInt<1>, flip ldst_dual_r : UInt<1>, flip addr_in_dccm_m : UInt<1>, flip addr_in_dccm_r : UInt<1>, flip lsu_cmpen_m : UInt<1>, flip scan_mode : UInt<1>, stbuf_reqvld_any : UInt<1>, stbuf_reqvld_flushed_any : UInt<1>, stbuf_addr_any : UInt<16>, stbuf_data_any : UInt<32>, lsu_stbuf_full_any : UInt<1>, lsu_stbuf_empty_any : UInt<1>, ldst_stbuf_reqvld_r : UInt<1>, stbuf_fwddata_hi_m : UInt<32>, stbuf_fwddata_lo_m : UInt<32>, stbuf_fwdbyteen_hi_m : UInt<4>, stbuf_fwdbyteen_lo_m : UInt<4>}
     
     io.stbuf_reqvld_any <= UInt<1>("h00") @[lsu_stbuf.scala 51:47]
     io.stbuf_reqvld_flushed_any <= UInt<1>("h00") @[lsu_stbuf.scala 52:35]
@@ -4220,91 +4376,107 @@ circuit lsu :
     stbuf_byteen[3] <= _T_661 @[lsu_stbuf.scala 165:18]
     node _T_662 = bits(stbuf_wr_en, 0, 0) @[lsu_stbuf.scala 169:59]
     node _T_663 = bits(_T_662, 0, 0) @[lsu_stbuf.scala 169:69]
-    inst rvclkhdr of rvclkhdr_8 @[lib.scala 368:23]
+    inst rvclkhdr of rvclkhdr_13 @[lib.scala 390:23]
     rvclkhdr.clock <= clock
     rvclkhdr.reset <= reset
-    rvclkhdr.io.clk <= clock @[lib.scala 370:18]
-    rvclkhdr.io.en <= _T_663 @[lib.scala 371:17]
-    rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
-    reg _T_664 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
-    _T_664 <= stbuf_addrin[0] @[lib.scala 374:16]
+    rvclkhdr.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr.io.en <= _T_663 @[lib.scala 393:17]
+    rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg _T_664 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_663 : @[Reg.scala 28:19]
+      _T_664 <= stbuf_addrin[0] @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
     stbuf_addr[0] <= _T_664 @[lsu_stbuf.scala 169:21]
     node _T_665 = bits(stbuf_wr_en, 0, 0) @[lsu_stbuf.scala 170:59]
     node _T_666 = bits(_T_665, 0, 0) @[lsu_stbuf.scala 170:69]
-    inst rvclkhdr_1 of rvclkhdr_9 @[lib.scala 368:23]
+    inst rvclkhdr_1 of rvclkhdr_14 @[lib.scala 390:23]
     rvclkhdr_1.clock <= clock
     rvclkhdr_1.reset <= reset
-    rvclkhdr_1.io.clk <= clock @[lib.scala 370:18]
-    rvclkhdr_1.io.en <= _T_666 @[lib.scala 371:17]
-    rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
-    reg _T_667 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
-    _T_667 <= stbuf_datain[0] @[lib.scala 374:16]
+    rvclkhdr_1.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr_1.io.en <= _T_666 @[lib.scala 393:17]
+    rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg _T_667 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_666 : @[Reg.scala 28:19]
+      _T_667 <= stbuf_datain[0] @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
     stbuf_data[0] <= _T_667 @[lsu_stbuf.scala 170:21]
     node _T_668 = bits(stbuf_wr_en, 1, 1) @[lsu_stbuf.scala 169:59]
     node _T_669 = bits(_T_668, 0, 0) @[lsu_stbuf.scala 169:69]
-    inst rvclkhdr_2 of rvclkhdr_10 @[lib.scala 368:23]
+    inst rvclkhdr_2 of rvclkhdr_15 @[lib.scala 390:23]
     rvclkhdr_2.clock <= clock
     rvclkhdr_2.reset <= reset
-    rvclkhdr_2.io.clk <= clock @[lib.scala 370:18]
-    rvclkhdr_2.io.en <= _T_669 @[lib.scala 371:17]
-    rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
-    reg _T_670 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
-    _T_670 <= stbuf_addrin[1] @[lib.scala 374:16]
+    rvclkhdr_2.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr_2.io.en <= _T_669 @[lib.scala 393:17]
+    rvclkhdr_2.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg _T_670 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_669 : @[Reg.scala 28:19]
+      _T_670 <= stbuf_addrin[1] @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
     stbuf_addr[1] <= _T_670 @[lsu_stbuf.scala 169:21]
     node _T_671 = bits(stbuf_wr_en, 1, 1) @[lsu_stbuf.scala 170:59]
     node _T_672 = bits(_T_671, 0, 0) @[lsu_stbuf.scala 170:69]
-    inst rvclkhdr_3 of rvclkhdr_11 @[lib.scala 368:23]
+    inst rvclkhdr_3 of rvclkhdr_16 @[lib.scala 390:23]
     rvclkhdr_3.clock <= clock
     rvclkhdr_3.reset <= reset
-    rvclkhdr_3.io.clk <= clock @[lib.scala 370:18]
-    rvclkhdr_3.io.en <= _T_672 @[lib.scala 371:17]
-    rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
-    reg _T_673 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
-    _T_673 <= stbuf_datain[1] @[lib.scala 374:16]
+    rvclkhdr_3.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr_3.io.en <= _T_672 @[lib.scala 393:17]
+    rvclkhdr_3.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg _T_673 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_672 : @[Reg.scala 28:19]
+      _T_673 <= stbuf_datain[1] @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
     stbuf_data[1] <= _T_673 @[lsu_stbuf.scala 170:21]
     node _T_674 = bits(stbuf_wr_en, 2, 2) @[lsu_stbuf.scala 169:59]
     node _T_675 = bits(_T_674, 0, 0) @[lsu_stbuf.scala 169:69]
-    inst rvclkhdr_4 of rvclkhdr_12 @[lib.scala 368:23]
+    inst rvclkhdr_4 of rvclkhdr_17 @[lib.scala 390:23]
     rvclkhdr_4.clock <= clock
     rvclkhdr_4.reset <= reset
-    rvclkhdr_4.io.clk <= clock @[lib.scala 370:18]
-    rvclkhdr_4.io.en <= _T_675 @[lib.scala 371:17]
-    rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
-    reg _T_676 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
-    _T_676 <= stbuf_addrin[2] @[lib.scala 374:16]
+    rvclkhdr_4.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr_4.io.en <= _T_675 @[lib.scala 393:17]
+    rvclkhdr_4.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg _T_676 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_675 : @[Reg.scala 28:19]
+      _T_676 <= stbuf_addrin[2] @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
     stbuf_addr[2] <= _T_676 @[lsu_stbuf.scala 169:21]
     node _T_677 = bits(stbuf_wr_en, 2, 2) @[lsu_stbuf.scala 170:59]
     node _T_678 = bits(_T_677, 0, 0) @[lsu_stbuf.scala 170:69]
-    inst rvclkhdr_5 of rvclkhdr_13 @[lib.scala 368:23]
+    inst rvclkhdr_5 of rvclkhdr_18 @[lib.scala 390:23]
     rvclkhdr_5.clock <= clock
     rvclkhdr_5.reset <= reset
-    rvclkhdr_5.io.clk <= clock @[lib.scala 370:18]
-    rvclkhdr_5.io.en <= _T_678 @[lib.scala 371:17]
-    rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
-    reg _T_679 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
-    _T_679 <= stbuf_datain[2] @[lib.scala 374:16]
+    rvclkhdr_5.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr_5.io.en <= _T_678 @[lib.scala 393:17]
+    rvclkhdr_5.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg _T_679 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_678 : @[Reg.scala 28:19]
+      _T_679 <= stbuf_datain[2] @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
     stbuf_data[2] <= _T_679 @[lsu_stbuf.scala 170:21]
     node _T_680 = bits(stbuf_wr_en, 3, 3) @[lsu_stbuf.scala 169:59]
     node _T_681 = bits(_T_680, 0, 0) @[lsu_stbuf.scala 169:69]
-    inst rvclkhdr_6 of rvclkhdr_14 @[lib.scala 368:23]
+    inst rvclkhdr_6 of rvclkhdr_19 @[lib.scala 390:23]
     rvclkhdr_6.clock <= clock
     rvclkhdr_6.reset <= reset
-    rvclkhdr_6.io.clk <= clock @[lib.scala 370:18]
-    rvclkhdr_6.io.en <= _T_681 @[lib.scala 371:17]
-    rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
-    reg _T_682 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
-    _T_682 <= stbuf_addrin[3] @[lib.scala 374:16]
+    rvclkhdr_6.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr_6.io.en <= _T_681 @[lib.scala 393:17]
+    rvclkhdr_6.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg _T_682 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_681 : @[Reg.scala 28:19]
+      _T_682 <= stbuf_addrin[3] @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
     stbuf_addr[3] <= _T_682 @[lsu_stbuf.scala 169:21]
     node _T_683 = bits(stbuf_wr_en, 3, 3) @[lsu_stbuf.scala 170:59]
     node _T_684 = bits(_T_683, 0, 0) @[lsu_stbuf.scala 170:69]
-    inst rvclkhdr_7 of rvclkhdr_15 @[lib.scala 368:23]
+    inst rvclkhdr_7 of rvclkhdr_20 @[lib.scala 390:23]
     rvclkhdr_7.clock <= clock
     rvclkhdr_7.reset <= reset
-    rvclkhdr_7.io.clk <= clock @[lib.scala 370:18]
-    rvclkhdr_7.io.en <= _T_684 @[lib.scala 371:17]
-    rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
-    reg _T_685 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
-    _T_685 <= stbuf_datain[3] @[lib.scala 374:16]
+    rvclkhdr_7.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr_7.io.en <= _T_684 @[lib.scala 393:17]
+    rvclkhdr_7.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg _T_685 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_684 : @[Reg.scala 28:19]
+      _T_685 <= stbuf_datain[3] @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
     stbuf_data[3] <= _T_685 @[lsu_stbuf.scala 170:21]
     node _T_686 = dshr(stbuf_vld, RdPtr) @[lsu_stbuf.scala 183:43]
     node _T_687 = bits(_T_686, 0, 0) @[lsu_stbuf.scala 183:43]
@@ -5052,7 +5224,7 @@ circuit lsu :
     node _T_1311 = cat(_T_1310, _T_1309) @[Cat.scala 29:58]
     io.stbuf_fwddata_hi_m <= _T_1311 @[lsu_stbuf.scala 272:25]
     
-  extmodule gated_latch_16 : 
+  extmodule gated_latch_21 : 
     output Q : Clock
     input CK : Clock
     input EN : UInt<1>
@@ -5061,12 +5233,12 @@ circuit lsu :
     defname = gated_latch
     
     
-  module rvclkhdr_16 : 
+  module rvclkhdr_21 : 
     input clock : Clock
     input reset : Reset
     output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
     
-    inst clkhdr of gated_latch_16 @[lib.scala 334:26]
+    inst clkhdr of gated_latch_21 @[lib.scala 334:26]
     clkhdr.SE is invalid
     clkhdr.EN is invalid
     clkhdr.CK is invalid
@@ -5076,7 +5248,7 @@ circuit lsu :
     clkhdr.EN <= io.en @[lib.scala 337:18]
     clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
     
-  extmodule gated_latch_17 : 
+  extmodule gated_latch_22 : 
     output Q : Clock
     input CK : Clock
     input EN : UInt<1>
@@ -5085,12 +5257,12 @@ circuit lsu :
     defname = gated_latch
     
     
-  module rvclkhdr_17 : 
+  module rvclkhdr_22 : 
     input clock : Clock
     input reset : Reset
     output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
     
-    inst clkhdr of gated_latch_17 @[lib.scala 334:26]
+    inst clkhdr of gated_latch_22 @[lib.scala 334:26]
     clkhdr.SE is invalid
     clkhdr.EN is invalid
     clkhdr.CK is invalid
@@ -5100,7 +5272,7 @@ circuit lsu :
     clkhdr.EN <= io.en @[lib.scala 337:18]
     clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
     
-  extmodule gated_latch_18 : 
+  extmodule gated_latch_23 : 
     output Q : Clock
     input CK : Clock
     input EN : UInt<1>
@@ -5109,12 +5281,12 @@ circuit lsu :
     defname = gated_latch
     
     
-  module rvclkhdr_18 : 
+  module rvclkhdr_23 : 
     input clock : Clock
     input reset : Reset
     output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
     
-    inst clkhdr of gated_latch_18 @[lib.scala 334:26]
+    inst clkhdr of gated_latch_23 @[lib.scala 334:26]
     clkhdr.SE is invalid
     clkhdr.EN is invalid
     clkhdr.CK is invalid
@@ -5124,7 +5296,7 @@ circuit lsu :
     clkhdr.EN <= io.en @[lib.scala 337:18]
     clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
     
-  extmodule gated_latch_19 : 
+  extmodule gated_latch_24 : 
     output Q : Clock
     input CK : Clock
     input EN : UInt<1>
@@ -5133,12 +5305,12 @@ circuit lsu :
     defname = gated_latch
     
     
-  module rvclkhdr_19 : 
+  module rvclkhdr_24 : 
     input clock : Clock
     input reset : Reset
     output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
     
-    inst clkhdr of gated_latch_19 @[lib.scala 334:26]
+    inst clkhdr of gated_latch_24 @[lib.scala 334:26]
     clkhdr.SE is invalid
     clkhdr.EN is invalid
     clkhdr.CK is invalid
@@ -5151,7 +5323,7 @@ circuit lsu :
   module lsu_ecc : 
     input clock : Clock
     input reset : AsyncReset
-    output io : {flip lsu_c2_r_clk : Clock, flip clk_override : UInt<1>, flip lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_pkt_r : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip stbuf_data_any : UInt<32>, flip dec_tlu_core_ecc_disable : UInt<1>, flip lsu_dccm_rden_r : UInt<1>, flip addr_in_dccm_r : UInt<1>, flip lsu_addr_r : UInt<16>, flip end_addr_r : UInt<16>, flip lsu_addr_m : UInt<16>, flip end_addr_m : UInt<16>, flip dccm_rdata_hi_r : UInt<32>, flip dccm_rdata_lo_r : UInt<32>, flip dccm_rdata_hi_m : UInt<32>, flip dccm_rdata_lo_m : UInt<32>, flip dccm_data_ecc_hi_r : UInt<7>, flip dccm_data_ecc_lo_r : UInt<7>, flip dccm_data_ecc_hi_m : UInt<7>, flip dccm_data_ecc_lo_m : UInt<7>, flip ld_single_ecc_error_r : UInt<1>, flip ld_single_ecc_error_r_ff : UInt<1>, flip lsu_dccm_rden_m : UInt<1>, flip addr_in_dccm_m : UInt<1>, flip dma_dccm_wen : UInt<1>, flip dma_dccm_wdata_lo : UInt<32>, flip dma_dccm_wdata_hi : UInt<32>, flip scan_mode : UInt<1>, sec_data_hi_r : UInt<32>, sec_data_lo_r : UInt<32>, sec_data_hi_m : UInt<32>, sec_data_lo_m : UInt<32>, sec_data_hi_r_ff : UInt<32>, sec_data_lo_r_ff : UInt<32>, dma_dccm_wdata_ecc_hi : UInt<7>, dma_dccm_wdata_ecc_lo : UInt<7>, stbuf_ecc_any : UInt<7>, sec_data_ecc_hi_r_ff : UInt<7>, sec_data_ecc_lo_r_ff : UInt<7>, single_ecc_error_hi_r : UInt<1>, single_ecc_error_lo_r : UInt<1>, lsu_single_ecc_error_r : UInt<1>, lsu_double_ecc_error_r : UInt<1>, lsu_single_ecc_error_m : UInt<1>, lsu_double_ecc_error_m : UInt<1>}
+    output io : {flip lsu_c2_r_clk : Clock, flip clk_override : UInt<1>, flip lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_pkt_r : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip stbuf_data_any : UInt<32>, flip dec_tlu_core_ecc_disable : UInt<1>, flip lsu_dccm_rden_r : UInt<1>, flip addr_in_dccm_r : UInt<1>, flip lsu_addr_r : UInt<16>, flip end_addr_r : UInt<16>, flip lsu_addr_m : UInt<16>, flip end_addr_m : UInt<16>, flip dccm_rdata_hi_r : UInt<32>, flip dccm_rdata_lo_r : UInt<32>, flip dccm_rdata_hi_m : UInt<32>, flip dccm_rdata_lo_m : UInt<32>, flip dccm_data_ecc_hi_r : UInt<7>, flip dccm_data_ecc_lo_r : UInt<7>, flip dccm_data_ecc_hi_m : UInt<7>, flip dccm_data_ecc_lo_m : UInt<7>, flip ld_single_ecc_error_r : UInt<1>, flip ld_single_ecc_error_r_ff : UInt<1>, flip lsu_dccm_rden_m : UInt<1>, flip addr_in_dccm_m : UInt<1>, flip dma_dccm_wen : UInt<1>, flip dma_dccm_wdata_lo : UInt<32>, flip dma_dccm_wdata_hi : UInt<32>, flip scan_mode : UInt<1>, sec_data_hi_r : UInt<32>, sec_data_lo_r : UInt<32>, sec_data_hi_m : UInt<32>, sec_data_lo_m : UInt<32>, sec_data_hi_r_ff : UInt<32>, sec_data_lo_r_ff : UInt<32>, dma_dccm_wdata_ecc_hi : UInt<7>, dma_dccm_wdata_ecc_lo : UInt<7>, stbuf_ecc_any : UInt<7>, sec_data_ecc_hi_r_ff : UInt<7>, sec_data_ecc_lo_r_ff : UInt<7>, single_ecc_error_hi_r : UInt<1>, single_ecc_error_lo_r : UInt<1>, lsu_single_ecc_error_r : UInt<1>, lsu_double_ecc_error_r : UInt<1>, lsu_single_ecc_error_m : UInt<1>, lsu_double_ecc_error_m : UInt<1>}
     
     wire is_ldst_r : UInt<1>
     is_ldst_r <= UInt<1>("h00")
@@ -6585,7 +6757,7 @@ circuit lsu :
     node _T_1118 = xorr(_T_1116) @[lib.scala 127:23]
     node _T_1119 = xor(_T_1117, _T_1118) @[lib.scala 127:18]
     node dccm_wdata_ecc_hi_any = cat(_T_1119, _T_1116) @[Cat.scala 29:58]
-    when UInt<1>("h00") : @[lsu_ecc.scala 102:30]
+    when UInt<1>("h01") : @[lsu_ecc.scala 102:30]
       node _T_1120 = bits(io.lsu_addr_r, 2, 2) @[lsu_ecc.scala 103:33]
       node _T_1121 = bits(io.end_addr_r, 2, 2) @[lsu_ecc.scala 103:54]
       node _T_1122 = neq(_T_1120, _T_1121) @[lsu_ecc.scala 103:37]
@@ -6664,24 +6836,28 @@ circuit lsu :
       _T_1152 <= single_ecc_error_hi_any @[lsu_ecc.scala 143:72]
       io.single_ecc_error_hi_r <= _T_1152 @[lsu_ecc.scala 143:62]
       node _T_1153 = or(io.lsu_single_ecc_error_m, io.clk_override) @[lsu_ecc.scala 144:87]
-      inst rvclkhdr of rvclkhdr_16 @[lib.scala 368:23]
+      inst rvclkhdr of rvclkhdr_21 @[lib.scala 390:23]
       rvclkhdr.clock <= clock
       rvclkhdr.reset <= reset
-      rvclkhdr.io.clk <= clock @[lib.scala 370:18]
-      rvclkhdr.io.en <= _T_1153 @[lib.scala 371:17]
-      rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
-      reg _T_1154 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
-      _T_1154 <= io.sec_data_hi_m @[lib.scala 374:16]
+      rvclkhdr.io.clk <= clock @[lib.scala 392:18]
+      rvclkhdr.io.en <= _T_1153 @[lib.scala 393:17]
+      rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+      reg _T_1154 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+      when _T_1153 : @[Reg.scala 28:19]
+        _T_1154 <= io.sec_data_hi_m @[Reg.scala 28:23]
+        skip @[Reg.scala 28:19]
       io.sec_data_hi_r <= _T_1154 @[lsu_ecc.scala 144:34]
       node _T_1155 = or(io.lsu_single_ecc_error_m, io.clk_override) @[lsu_ecc.scala 145:87]
-      inst rvclkhdr_1 of rvclkhdr_17 @[lib.scala 368:23]
+      inst rvclkhdr_1 of rvclkhdr_22 @[lib.scala 390:23]
       rvclkhdr_1.clock <= clock
       rvclkhdr_1.reset <= reset
-      rvclkhdr_1.io.clk <= clock @[lib.scala 370:18]
-      rvclkhdr_1.io.en <= _T_1155 @[lib.scala 371:17]
-      rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
-      reg _T_1156 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
-      _T_1156 <= io.sec_data_lo_m @[lib.scala 374:16]
+      rvclkhdr_1.io.clk <= clock @[lib.scala 392:18]
+      rvclkhdr_1.io.en <= _T_1155 @[lib.scala 393:17]
+      rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+      reg _T_1156 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+      when _T_1155 : @[Reg.scala 28:19]
+        _T_1156 <= io.sec_data_lo_m @[Reg.scala 28:23]
+        skip @[Reg.scala 28:19]
       io.sec_data_lo_r <= _T_1156 @[lsu_ecc.scala 145:34]
       skip @[lsu_ecc.scala 122:16]
     node _T_1157 = bits(io.ld_single_ecc_error_r_ff, 0, 0) @[lsu_ecc.scala 148:56]
@@ -6700,30 +6876,34 @@ circuit lsu :
     io.dma_dccm_wdata_ecc_hi <= dccm_wdata_ecc_hi_any @[lsu_ecc.scala 153:28]
     io.dma_dccm_wdata_ecc_lo <= dccm_wdata_ecc_lo_any @[lsu_ecc.scala 154:28]
     node _T_1165 = or(io.ld_single_ecc_error_r, io.clk_override) @[lsu_ecc.scala 156:75]
-    inst rvclkhdr_2 of rvclkhdr_18 @[lib.scala 368:23]
+    inst rvclkhdr_2 of rvclkhdr_23 @[lib.scala 390:23]
     rvclkhdr_2.clock <= clock
     rvclkhdr_2.reset <= reset
-    rvclkhdr_2.io.clk <= clock @[lib.scala 370:18]
-    rvclkhdr_2.io.en <= _T_1165 @[lib.scala 371:17]
-    rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
-    reg _T_1166 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
-    _T_1166 <= io.sec_data_hi_r @[lib.scala 374:16]
+    rvclkhdr_2.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr_2.io.en <= _T_1165 @[lib.scala 393:17]
+    rvclkhdr_2.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg _T_1166 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_1165 : @[Reg.scala 28:19]
+      _T_1166 <= io.sec_data_hi_r @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
     io.sec_data_hi_r_ff <= _T_1166 @[lsu_ecc.scala 156:23]
     node _T_1167 = or(io.ld_single_ecc_error_r, io.clk_override) @[lsu_ecc.scala 157:75]
-    inst rvclkhdr_3 of rvclkhdr_19 @[lib.scala 368:23]
+    inst rvclkhdr_3 of rvclkhdr_24 @[lib.scala 390:23]
     rvclkhdr_3.clock <= clock
     rvclkhdr_3.reset <= reset
-    rvclkhdr_3.io.clk <= clock @[lib.scala 370:18]
-    rvclkhdr_3.io.en <= _T_1167 @[lib.scala 371:17]
-    rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
-    reg _T_1168 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
-    _T_1168 <= io.sec_data_lo_r @[lib.scala 374:16]
+    rvclkhdr_3.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr_3.io.en <= _T_1167 @[lib.scala 393:17]
+    rvclkhdr_3.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg _T_1168 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_1167 : @[Reg.scala 28:19]
+      _T_1168 <= io.sec_data_lo_r @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
     io.sec_data_lo_r_ff <= _T_1168 @[lsu_ecc.scala 157:23]
     
   module lsu_trigger : 
     input clock : Clock
     input reset : AsyncReset
-    output io : {flip trigger_pkt_any : {select : UInt<1>, match_pkt : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_addr_m : UInt<32>, flip store_data_m : UInt<32>, lsu_trigger_match_m : UInt<4>}
+    output io : {flip trigger_pkt_any : {select : UInt<1>, match_pkt : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_addr_m : UInt<32>, flip store_data_m : UInt<32>, lsu_trigger_match_m : UInt<4>}
     
     wire trigger_enable : UInt<1>
     trigger_enable <= UInt<1>("h00")
@@ -7987,126 +8167,6 @@ circuit lsu :
     node _T_1118 = cat(_T_1117, _T_311) @[Cat.scala 29:58]
     io.lsu_trigger_match_m <= _T_1118 @[lsu_trigger.scala 20:25]
     
-  extmodule gated_latch_20 : 
-    output Q : Clock
-    input CK : Clock
-    input EN : UInt<1>
-    input SE : UInt<1>
-    
-    defname = gated_latch
-    
-    
-  module rvclkhdr_20 : 
-    input clock : Clock
-    input reset : Reset
-    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
-    
-    inst clkhdr of gated_latch_20 @[lib.scala 334:26]
-    clkhdr.SE is invalid
-    clkhdr.EN is invalid
-    clkhdr.CK is invalid
-    clkhdr.Q is invalid
-    io.l1clk <= clkhdr.Q @[lib.scala 335:14]
-    clkhdr.CK <= io.clk @[lib.scala 336:18]
-    clkhdr.EN <= io.en @[lib.scala 337:18]
-    clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
-    
-  extmodule gated_latch_21 : 
-    output Q : Clock
-    input CK : Clock
-    input EN : UInt<1>
-    input SE : UInt<1>
-    
-    defname = gated_latch
-    
-    
-  module rvclkhdr_21 : 
-    input clock : Clock
-    input reset : Reset
-    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
-    
-    inst clkhdr of gated_latch_21 @[lib.scala 334:26]
-    clkhdr.SE is invalid
-    clkhdr.EN is invalid
-    clkhdr.CK is invalid
-    clkhdr.Q is invalid
-    io.l1clk <= clkhdr.Q @[lib.scala 335:14]
-    clkhdr.CK <= io.clk @[lib.scala 336:18]
-    clkhdr.EN <= io.en @[lib.scala 337:18]
-    clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
-    
-  extmodule gated_latch_22 : 
-    output Q : Clock
-    input CK : Clock
-    input EN : UInt<1>
-    input SE : UInt<1>
-    
-    defname = gated_latch
-    
-    
-  module rvclkhdr_22 : 
-    input clock : Clock
-    input reset : Reset
-    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
-    
-    inst clkhdr of gated_latch_22 @[lib.scala 334:26]
-    clkhdr.SE is invalid
-    clkhdr.EN is invalid
-    clkhdr.CK is invalid
-    clkhdr.Q is invalid
-    io.l1clk <= clkhdr.Q @[lib.scala 335:14]
-    clkhdr.CK <= io.clk @[lib.scala 336:18]
-    clkhdr.EN <= io.en @[lib.scala 337:18]
-    clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
-    
-  extmodule gated_latch_23 : 
-    output Q : Clock
-    input CK : Clock
-    input EN : UInt<1>
-    input SE : UInt<1>
-    
-    defname = gated_latch
-    
-    
-  module rvclkhdr_23 : 
-    input clock : Clock
-    input reset : Reset
-    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
-    
-    inst clkhdr of gated_latch_23 @[lib.scala 334:26]
-    clkhdr.SE is invalid
-    clkhdr.EN is invalid
-    clkhdr.CK is invalid
-    clkhdr.Q is invalid
-    io.l1clk <= clkhdr.Q @[lib.scala 335:14]
-    clkhdr.CK <= io.clk @[lib.scala 336:18]
-    clkhdr.EN <= io.en @[lib.scala 337:18]
-    clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
-    
-  extmodule gated_latch_24 : 
-    output Q : Clock
-    input CK : Clock
-    input EN : UInt<1>
-    input SE : UInt<1>
-    
-    defname = gated_latch
-    
-    
-  module rvclkhdr_24 : 
-    input clock : Clock
-    input reset : Reset
-    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
-    
-    inst clkhdr of gated_latch_24 @[lib.scala 334:26]
-    clkhdr.SE is invalid
-    clkhdr.EN is invalid
-    clkhdr.CK is invalid
-    clkhdr.Q is invalid
-    io.l1clk <= clkhdr.Q @[lib.scala 335:14]
-    clkhdr.CK <= io.clk @[lib.scala 336:18]
-    clkhdr.EN <= io.en @[lib.scala 337:18]
-    clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
-    
   extmodule gated_latch_25 : 
     output Q : Clock
     input CK : Clock
@@ -8275,159 +8335,6 @@ circuit lsu :
     clkhdr.EN <= io.en @[lib.scala 337:18]
     clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
     
-  module lsu_clkdomain : 
-    input clock : Clock
-    input reset : AsyncReset
-    output io : {flip active_clk : Clock, flip clk_override : UInt<1>, flip dec_tlu_force_halt : UInt<1>, flip dma_dccm_req : UInt<1>, flip ldst_stbuf_reqvld_r : UInt<1>, flip stbuf_reqvld_any : UInt<1>, flip stbuf_reqvld_flushed_any : UInt<1>, flip lsu_busreq_r : UInt<1>, flip lsu_bus_buffer_pend_any : UInt<1>, flip lsu_bus_buffer_empty_any : UInt<1>, flip lsu_stbuf_empty_any : UInt<1>, flip lsu_bus_clk_en : UInt<1>, flip lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_pkt_r : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, lsu_bus_obuf_c1_clken : UInt<1>, lsu_busm_clken : UInt<1>, lsu_c1_m_clk : Clock, lsu_c1_r_clk : Clock, lsu_c2_m_clk : Clock, lsu_c2_r_clk : Clock, lsu_store_c1_m_clk : Clock, lsu_store_c1_r_clk : Clock, lsu_stbuf_c1_clk : Clock, lsu_bus_obuf_c1_clk : Clock, lsu_bus_ibuf_c1_clk : Clock, lsu_bus_buf_c1_clk : Clock, lsu_busm_clk : Clock, lsu_free_c2_clk : Clock, flip scan_mode : UInt<1>}
-    
-    wire lsu_c1_m_clken_q : UInt<1> @[lsu_clkdomain.scala 60:36]
-    wire lsu_c1_r_clken_q : UInt<1> @[lsu_clkdomain.scala 61:36]
-    wire lsu_free_c1_clken_q : UInt<1> @[lsu_clkdomain.scala 62:36]
-    node _T = or(io.lsu_p.valid, io.dma_dccm_req) @[lsu_clkdomain.scala 64:47]
-    node lsu_c1_m_clken = or(_T, io.clk_override) @[lsu_clkdomain.scala 64:65]
-    node _T_1 = or(io.lsu_pkt_m.valid, lsu_c1_m_clken_q) @[lsu_clkdomain.scala 65:51]
-    node lsu_c1_r_clken = or(_T_1, io.clk_override) @[lsu_clkdomain.scala 65:70]
-    node _T_2 = or(lsu_c1_m_clken, lsu_c1_m_clken_q) @[lsu_clkdomain.scala 67:47]
-    node lsu_c2_m_clken = or(_T_2, io.clk_override) @[lsu_clkdomain.scala 67:66]
-    node _T_3 = or(lsu_c1_r_clken, lsu_c1_r_clken_q) @[lsu_clkdomain.scala 68:47]
-    node lsu_c2_r_clken = or(_T_3, io.clk_override) @[lsu_clkdomain.scala 68:66]
-    node _T_4 = and(lsu_c1_m_clken, io.lsu_pkt_d.bits.store) @[lsu_clkdomain.scala 70:49]
-    node lsu_store_c1_m_clken = or(_T_4, io.clk_override) @[lsu_clkdomain.scala 70:76]
-    node _T_5 = and(lsu_c1_r_clken, io.lsu_pkt_m.bits.store) @[lsu_clkdomain.scala 71:49]
-    node lsu_store_c1_r_clken = or(_T_5, io.clk_override) @[lsu_clkdomain.scala 71:76]
-    node _T_6 = or(io.ldst_stbuf_reqvld_r, io.stbuf_reqvld_any) @[lsu_clkdomain.scala 72:55]
-    node _T_7 = or(_T_6, io.stbuf_reqvld_flushed_any) @[lsu_clkdomain.scala 72:77]
-    node lsu_stbuf_c1_clken = or(_T_7, io.clk_override) @[lsu_clkdomain.scala 72:107]
-    node lsu_bus_ibuf_c1_clken = or(io.lsu_busreq_r, io.clk_override) @[lsu_clkdomain.scala 73:49]
-    node _T_8 = or(io.lsu_bus_buffer_pend_any, io.lsu_busreq_r) @[lsu_clkdomain.scala 74:62]
-    node _T_9 = or(_T_8, io.clk_override) @[lsu_clkdomain.scala 74:80]
-    node _T_10 = and(_T_9, io.lsu_bus_clk_en) @[lsu_clkdomain.scala 74:99]
-    io.lsu_bus_obuf_c1_clken <= _T_10 @[lsu_clkdomain.scala 74:30]
-    node _T_11 = eq(io.lsu_bus_buffer_empty_any, UInt<1>("h00")) @[lsu_clkdomain.scala 75:32]
-    node _T_12 = or(_T_11, io.lsu_busreq_r) @[lsu_clkdomain.scala 75:61]
-    node _T_13 = or(_T_12, io.dec_tlu_force_halt) @[lsu_clkdomain.scala 75:79]
-    node lsu_bus_buf_c1_clken = or(_T_13, io.clk_override) @[lsu_clkdomain.scala 75:103]
-    node _T_14 = or(io.lsu_p.valid, io.lsu_pkt_d.valid) @[lsu_clkdomain.scala 77:48]
-    node _T_15 = or(_T_14, io.lsu_pkt_m.valid) @[lsu_clkdomain.scala 77:69]
-    node _T_16 = or(_T_15, io.lsu_pkt_r.valid) @[lsu_clkdomain.scala 77:90]
-    node _T_17 = eq(io.lsu_bus_buffer_empty_any, UInt<1>("h00")) @[lsu_clkdomain.scala 77:114]
-    node _T_18 = or(_T_16, _T_17) @[lsu_clkdomain.scala 77:112]
-    node _T_19 = eq(io.lsu_stbuf_empty_any, UInt<1>("h00")) @[lsu_clkdomain.scala 77:145]
-    node _T_20 = or(_T_18, _T_19) @[lsu_clkdomain.scala 77:143]
-    node lsu_free_c1_clken = or(_T_20, io.clk_override) @[lsu_clkdomain.scala 77:169]
-    node _T_21 = or(lsu_free_c1_clken, lsu_free_c1_clken_q) @[lsu_clkdomain.scala 78:50]
-    node lsu_free_c2_clken = or(_T_21, io.clk_override) @[lsu_clkdomain.scala 78:72]
-    node _T_22 = eq(io.lsu_bus_buffer_empty_any, UInt<1>("h00")) @[lsu_clkdomain.scala 79:25]
-    node _T_23 = or(_T_22, io.lsu_busreq_r) @[lsu_clkdomain.scala 79:54]
-    node _T_24 = or(_T_23, io.clk_override) @[lsu_clkdomain.scala 79:72]
-    node _T_25 = and(_T_24, io.lsu_bus_clk_en) @[lsu_clkdomain.scala 79:91]
-    io.lsu_busm_clken <= _T_25 @[lsu_clkdomain.scala 79:21]
-    reg _T_26 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_clkdomain.scala 82:62]
-    _T_26 <= lsu_free_c1_clken @[lsu_clkdomain.scala 82:62]
-    lsu_free_c1_clken_q <= _T_26 @[lsu_clkdomain.scala 82:26]
-    reg _T_27 : UInt<1>, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_clkdomain.scala 84:67]
-    _T_27 <= lsu_c1_m_clken @[lsu_clkdomain.scala 84:67]
-    lsu_c1_m_clken_q <= _T_27 @[lsu_clkdomain.scala 84:26]
-    reg _T_28 : UInt<1>, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_clkdomain.scala 85:67]
-    _T_28 <= lsu_c1_r_clken @[lsu_clkdomain.scala 85:67]
-    lsu_c1_r_clken_q <= _T_28 @[lsu_clkdomain.scala 85:26]
-    node _T_29 = bits(lsu_c1_m_clken, 0, 0) @[lsu_clkdomain.scala 87:59]
-    inst rvclkhdr of rvclkhdr_20 @[lib.scala 343:22]
-    rvclkhdr.clock <= clock
-    rvclkhdr.reset <= reset
-    rvclkhdr.io.clk <= clock @[lib.scala 344:17]
-    rvclkhdr.io.en <= _T_29 @[lib.scala 345:16]
-    rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 346:23]
-    io.lsu_c1_m_clk <= rvclkhdr.io.l1clk @[lsu_clkdomain.scala 87:26]
-    node _T_30 = bits(lsu_c1_r_clken, 0, 0) @[lsu_clkdomain.scala 88:59]
-    inst rvclkhdr_1 of rvclkhdr_21 @[lib.scala 343:22]
-    rvclkhdr_1.clock <= clock
-    rvclkhdr_1.reset <= reset
-    rvclkhdr_1.io.clk <= clock @[lib.scala 344:17]
-    rvclkhdr_1.io.en <= _T_30 @[lib.scala 345:16]
-    rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 346:23]
-    io.lsu_c1_r_clk <= rvclkhdr_1.io.l1clk @[lsu_clkdomain.scala 88:26]
-    node _T_31 = bits(lsu_c2_m_clken, 0, 0) @[lsu_clkdomain.scala 89:59]
-    inst rvclkhdr_2 of rvclkhdr_22 @[lib.scala 343:22]
-    rvclkhdr_2.clock <= clock
-    rvclkhdr_2.reset <= reset
-    rvclkhdr_2.io.clk <= clock @[lib.scala 344:17]
-    rvclkhdr_2.io.en <= _T_31 @[lib.scala 345:16]
-    rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 346:23]
-    io.lsu_c2_m_clk <= rvclkhdr_2.io.l1clk @[lsu_clkdomain.scala 89:26]
-    node _T_32 = bits(lsu_c2_r_clken, 0, 0) @[lsu_clkdomain.scala 90:59]
-    inst rvclkhdr_3 of rvclkhdr_23 @[lib.scala 343:22]
-    rvclkhdr_3.clock <= clock
-    rvclkhdr_3.reset <= reset
-    rvclkhdr_3.io.clk <= clock @[lib.scala 344:17]
-    rvclkhdr_3.io.en <= _T_32 @[lib.scala 345:16]
-    rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 346:23]
-    io.lsu_c2_r_clk <= rvclkhdr_3.io.l1clk @[lsu_clkdomain.scala 90:26]
-    node _T_33 = bits(lsu_store_c1_m_clken, 0, 0) @[lsu_clkdomain.scala 91:65]
-    inst rvclkhdr_4 of rvclkhdr_24 @[lib.scala 343:22]
-    rvclkhdr_4.clock <= clock
-    rvclkhdr_4.reset <= reset
-    rvclkhdr_4.io.clk <= clock @[lib.scala 344:17]
-    rvclkhdr_4.io.en <= _T_33 @[lib.scala 345:16]
-    rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 346:23]
-    io.lsu_store_c1_m_clk <= rvclkhdr_4.io.l1clk @[lsu_clkdomain.scala 91:26]
-    node _T_34 = bits(lsu_store_c1_r_clken, 0, 0) @[lsu_clkdomain.scala 92:65]
-    inst rvclkhdr_5 of rvclkhdr_25 @[lib.scala 343:22]
-    rvclkhdr_5.clock <= clock
-    rvclkhdr_5.reset <= reset
-    rvclkhdr_5.io.clk <= clock @[lib.scala 344:17]
-    rvclkhdr_5.io.en <= _T_34 @[lib.scala 345:16]
-    rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 346:23]
-    io.lsu_store_c1_r_clk <= rvclkhdr_5.io.l1clk @[lsu_clkdomain.scala 92:26]
-    node _T_35 = bits(lsu_stbuf_c1_clken, 0, 0) @[lsu_clkdomain.scala 93:63]
-    inst rvclkhdr_6 of rvclkhdr_26 @[lib.scala 343:22]
-    rvclkhdr_6.clock <= clock
-    rvclkhdr_6.reset <= reset
-    rvclkhdr_6.io.clk <= clock @[lib.scala 344:17]
-    rvclkhdr_6.io.en <= _T_35 @[lib.scala 345:16]
-    rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 346:23]
-    io.lsu_stbuf_c1_clk <= rvclkhdr_6.io.l1clk @[lsu_clkdomain.scala 93:26]
-    node _T_36 = bits(lsu_bus_ibuf_c1_clken, 0, 0) @[lsu_clkdomain.scala 94:66]
-    inst rvclkhdr_7 of rvclkhdr_27 @[lib.scala 343:22]
-    rvclkhdr_7.clock <= clock
-    rvclkhdr_7.reset <= reset
-    rvclkhdr_7.io.clk <= clock @[lib.scala 344:17]
-    rvclkhdr_7.io.en <= _T_36 @[lib.scala 345:16]
-    rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 346:23]
-    io.lsu_bus_ibuf_c1_clk <= rvclkhdr_7.io.l1clk @[lsu_clkdomain.scala 94:26]
-    node _T_37 = bits(io.lsu_bus_obuf_c1_clken, 0, 0) @[lsu_clkdomain.scala 95:69]
-    inst rvclkhdr_8 of rvclkhdr_28 @[lib.scala 343:22]
-    rvclkhdr_8.clock <= clock
-    rvclkhdr_8.reset <= reset
-    rvclkhdr_8.io.clk <= clock @[lib.scala 344:17]
-    rvclkhdr_8.io.en <= _T_37 @[lib.scala 345:16]
-    rvclkhdr_8.io.scan_mode <= io.scan_mode @[lib.scala 346:23]
-    io.lsu_bus_obuf_c1_clk <= rvclkhdr_8.io.l1clk @[lsu_clkdomain.scala 95:26]
-    node _T_38 = bits(lsu_bus_buf_c1_clken, 0, 0) @[lsu_clkdomain.scala 96:65]
-    inst rvclkhdr_9 of rvclkhdr_29 @[lib.scala 343:22]
-    rvclkhdr_9.clock <= clock
-    rvclkhdr_9.reset <= reset
-    rvclkhdr_9.io.clk <= clock @[lib.scala 344:17]
-    rvclkhdr_9.io.en <= _T_38 @[lib.scala 345:16]
-    rvclkhdr_9.io.scan_mode <= io.scan_mode @[lib.scala 346:23]
-    io.lsu_bus_buf_c1_clk <= rvclkhdr_9.io.l1clk @[lsu_clkdomain.scala 96:26]
-    node _T_39 = bits(io.lsu_busm_clken, 0, 0) @[lsu_clkdomain.scala 97:62]
-    inst rvclkhdr_10 of rvclkhdr_30 @[lib.scala 343:22]
-    rvclkhdr_10.clock <= clock
-    rvclkhdr_10.reset <= reset
-    rvclkhdr_10.io.clk <= clock @[lib.scala 344:17]
-    rvclkhdr_10.io.en <= _T_39 @[lib.scala 345:16]
-    rvclkhdr_10.io.scan_mode <= io.scan_mode @[lib.scala 346:23]
-    io.lsu_busm_clk <= rvclkhdr_10.io.l1clk @[lsu_clkdomain.scala 97:26]
-    node _T_40 = bits(lsu_free_c2_clken, 0, 0) @[lsu_clkdomain.scala 98:62]
-    inst rvclkhdr_11 of rvclkhdr_31 @[lib.scala 343:22]
-    rvclkhdr_11.clock <= clock
-    rvclkhdr_11.reset <= reset
-    rvclkhdr_11.io.clk <= clock @[lib.scala 344:17]
-    rvclkhdr_11.io.en <= _T_40 @[lib.scala 345:16]
-    rvclkhdr_11.io.scan_mode <= io.scan_mode @[lib.scala 346:23]
-    io.lsu_free_c2_clk <= rvclkhdr_11.io.l1clk @[lsu_clkdomain.scala 98:26]
-    
   extmodule gated_latch_32 : 
     output Q : Clock
     input CK : Clock
@@ -8548,6 +8455,159 @@ circuit lsu :
     clkhdr.EN <= io.en @[lib.scala 337:18]
     clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
     
+  module lsu_clkdomain : 
+    input clock : Clock
+    input reset : AsyncReset
+    output io : {flip active_clk : Clock, flip clk_override : UInt<1>, flip dec_tlu_force_halt : UInt<1>, flip dma_dccm_req : UInt<1>, flip ldst_stbuf_reqvld_r : UInt<1>, flip stbuf_reqvld_any : UInt<1>, flip stbuf_reqvld_flushed_any : UInt<1>, flip lsu_busreq_r : UInt<1>, flip lsu_bus_buffer_pend_any : UInt<1>, flip lsu_bus_buffer_empty_any : UInt<1>, flip lsu_stbuf_empty_any : UInt<1>, flip lsu_bus_clk_en : UInt<1>, flip lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_pkt_r : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, lsu_bus_obuf_c1_clken : UInt<1>, lsu_busm_clken : UInt<1>, lsu_c1_m_clk : Clock, lsu_c1_r_clk : Clock, lsu_c2_m_clk : Clock, lsu_c2_r_clk : Clock, lsu_store_c1_m_clk : Clock, lsu_store_c1_r_clk : Clock, lsu_stbuf_c1_clk : Clock, lsu_bus_obuf_c1_clk : Clock, lsu_bus_ibuf_c1_clk : Clock, lsu_bus_buf_c1_clk : Clock, lsu_busm_clk : Clock, lsu_free_c2_clk : Clock, flip scan_mode : UInt<1>}
+    
+    wire lsu_c1_m_clken_q : UInt<1> @[lsu_clkdomain.scala 60:36]
+    wire lsu_c1_r_clken_q : UInt<1> @[lsu_clkdomain.scala 61:36]
+    wire lsu_free_c1_clken_q : UInt<1> @[lsu_clkdomain.scala 62:36]
+    node _T = or(io.lsu_p.valid, io.dma_dccm_req) @[lsu_clkdomain.scala 64:47]
+    node lsu_c1_m_clken = or(_T, io.clk_override) @[lsu_clkdomain.scala 64:65]
+    node _T_1 = or(io.lsu_pkt_m.valid, lsu_c1_m_clken_q) @[lsu_clkdomain.scala 65:51]
+    node lsu_c1_r_clken = or(_T_1, io.clk_override) @[lsu_clkdomain.scala 65:70]
+    node _T_2 = or(lsu_c1_m_clken, lsu_c1_m_clken_q) @[lsu_clkdomain.scala 67:47]
+    node lsu_c2_m_clken = or(_T_2, io.clk_override) @[lsu_clkdomain.scala 67:66]
+    node _T_3 = or(lsu_c1_r_clken, lsu_c1_r_clken_q) @[lsu_clkdomain.scala 68:47]
+    node lsu_c2_r_clken = or(_T_3, io.clk_override) @[lsu_clkdomain.scala 68:66]
+    node _T_4 = and(lsu_c1_m_clken, io.lsu_pkt_d.bits.store) @[lsu_clkdomain.scala 70:49]
+    node lsu_store_c1_m_clken = or(_T_4, io.clk_override) @[lsu_clkdomain.scala 70:76]
+    node _T_5 = and(lsu_c1_r_clken, io.lsu_pkt_m.bits.store) @[lsu_clkdomain.scala 71:49]
+    node lsu_store_c1_r_clken = or(_T_5, io.clk_override) @[lsu_clkdomain.scala 71:76]
+    node _T_6 = or(io.ldst_stbuf_reqvld_r, io.stbuf_reqvld_any) @[lsu_clkdomain.scala 72:55]
+    node _T_7 = or(_T_6, io.stbuf_reqvld_flushed_any) @[lsu_clkdomain.scala 72:77]
+    node lsu_stbuf_c1_clken = or(_T_7, io.clk_override) @[lsu_clkdomain.scala 72:107]
+    node lsu_bus_ibuf_c1_clken = or(io.lsu_busreq_r, io.clk_override) @[lsu_clkdomain.scala 73:49]
+    node _T_8 = or(io.lsu_bus_buffer_pend_any, io.lsu_busreq_r) @[lsu_clkdomain.scala 74:62]
+    node _T_9 = or(_T_8, io.clk_override) @[lsu_clkdomain.scala 74:80]
+    node _T_10 = and(_T_9, io.lsu_bus_clk_en) @[lsu_clkdomain.scala 74:99]
+    io.lsu_bus_obuf_c1_clken <= _T_10 @[lsu_clkdomain.scala 74:30]
+    node _T_11 = eq(io.lsu_bus_buffer_empty_any, UInt<1>("h00")) @[lsu_clkdomain.scala 75:32]
+    node _T_12 = or(_T_11, io.lsu_busreq_r) @[lsu_clkdomain.scala 75:61]
+    node _T_13 = or(_T_12, io.dec_tlu_force_halt) @[lsu_clkdomain.scala 75:79]
+    node lsu_bus_buf_c1_clken = or(_T_13, io.clk_override) @[lsu_clkdomain.scala 75:103]
+    node _T_14 = or(io.lsu_p.valid, io.lsu_pkt_d.valid) @[lsu_clkdomain.scala 77:48]
+    node _T_15 = or(_T_14, io.lsu_pkt_m.valid) @[lsu_clkdomain.scala 77:69]
+    node _T_16 = or(_T_15, io.lsu_pkt_r.valid) @[lsu_clkdomain.scala 77:90]
+    node _T_17 = eq(io.lsu_bus_buffer_empty_any, UInt<1>("h00")) @[lsu_clkdomain.scala 77:114]
+    node _T_18 = or(_T_16, _T_17) @[lsu_clkdomain.scala 77:112]
+    node _T_19 = eq(io.lsu_stbuf_empty_any, UInt<1>("h00")) @[lsu_clkdomain.scala 77:145]
+    node _T_20 = or(_T_18, _T_19) @[lsu_clkdomain.scala 77:143]
+    node lsu_free_c1_clken = or(_T_20, io.clk_override) @[lsu_clkdomain.scala 77:169]
+    node _T_21 = or(lsu_free_c1_clken, lsu_free_c1_clken_q) @[lsu_clkdomain.scala 78:50]
+    node lsu_free_c2_clken = or(_T_21, io.clk_override) @[lsu_clkdomain.scala 78:72]
+    node _T_22 = eq(io.lsu_bus_buffer_empty_any, UInt<1>("h00")) @[lsu_clkdomain.scala 79:25]
+    node _T_23 = or(_T_22, io.lsu_busreq_r) @[lsu_clkdomain.scala 79:54]
+    node _T_24 = or(_T_23, io.clk_override) @[lsu_clkdomain.scala 79:72]
+    node _T_25 = and(_T_24, io.lsu_bus_clk_en) @[lsu_clkdomain.scala 79:91]
+    io.lsu_busm_clken <= _T_25 @[lsu_clkdomain.scala 79:21]
+    reg _T_26 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_clkdomain.scala 82:62]
+    _T_26 <= lsu_free_c1_clken @[lsu_clkdomain.scala 82:62]
+    lsu_free_c1_clken_q <= _T_26 @[lsu_clkdomain.scala 82:26]
+    reg _T_27 : UInt<1>, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_clkdomain.scala 84:67]
+    _T_27 <= lsu_c1_m_clken @[lsu_clkdomain.scala 84:67]
+    lsu_c1_m_clken_q <= _T_27 @[lsu_clkdomain.scala 84:26]
+    reg _T_28 : UInt<1>, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_clkdomain.scala 85:67]
+    _T_28 <= lsu_c1_r_clken @[lsu_clkdomain.scala 85:67]
+    lsu_c1_r_clken_q <= _T_28 @[lsu_clkdomain.scala 85:26]
+    node _T_29 = bits(lsu_c1_m_clken, 0, 0) @[lsu_clkdomain.scala 87:60]
+    inst rvclkhdr of rvclkhdr_25 @[lib.scala 352:22]
+    rvclkhdr.clock <= clock
+    rvclkhdr.reset <= reset
+    rvclkhdr.io.clk <= clock @[lib.scala 353:17]
+    rvclkhdr.io.en <= _T_29 @[lib.scala 354:16]
+    rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 355:23]
+    io.lsu_c1_m_clk <= rvclkhdr.io.l1clk @[lsu_clkdomain.scala 87:26]
+    node _T_30 = bits(lsu_c1_r_clken, 0, 0) @[lsu_clkdomain.scala 88:60]
+    inst rvclkhdr_1 of rvclkhdr_26 @[lib.scala 352:22]
+    rvclkhdr_1.clock <= clock
+    rvclkhdr_1.reset <= reset
+    rvclkhdr_1.io.clk <= clock @[lib.scala 353:17]
+    rvclkhdr_1.io.en <= _T_30 @[lib.scala 354:16]
+    rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 355:23]
+    io.lsu_c1_r_clk <= rvclkhdr_1.io.l1clk @[lsu_clkdomain.scala 88:26]
+    node _T_31 = bits(lsu_c2_m_clken, 0, 0) @[lsu_clkdomain.scala 89:60]
+    inst rvclkhdr_2 of rvclkhdr_27 @[lib.scala 352:22]
+    rvclkhdr_2.clock <= clock
+    rvclkhdr_2.reset <= reset
+    rvclkhdr_2.io.clk <= clock @[lib.scala 353:17]
+    rvclkhdr_2.io.en <= _T_31 @[lib.scala 354:16]
+    rvclkhdr_2.io.scan_mode <= UInt<1>("h00") @[lib.scala 355:23]
+    io.lsu_c2_m_clk <= rvclkhdr_2.io.l1clk @[lsu_clkdomain.scala 89:26]
+    node _T_32 = bits(lsu_c2_r_clken, 0, 0) @[lsu_clkdomain.scala 90:60]
+    inst rvclkhdr_3 of rvclkhdr_28 @[lib.scala 352:22]
+    rvclkhdr_3.clock <= clock
+    rvclkhdr_3.reset <= reset
+    rvclkhdr_3.io.clk <= clock @[lib.scala 353:17]
+    rvclkhdr_3.io.en <= _T_32 @[lib.scala 354:16]
+    rvclkhdr_3.io.scan_mode <= UInt<1>("h00") @[lib.scala 355:23]
+    io.lsu_c2_r_clk <= rvclkhdr_3.io.l1clk @[lsu_clkdomain.scala 90:26]
+    node _T_33 = bits(lsu_store_c1_m_clken, 0, 0) @[lsu_clkdomain.scala 91:66]
+    inst rvclkhdr_4 of rvclkhdr_29 @[lib.scala 352:22]
+    rvclkhdr_4.clock <= clock
+    rvclkhdr_4.reset <= reset
+    rvclkhdr_4.io.clk <= clock @[lib.scala 353:17]
+    rvclkhdr_4.io.en <= _T_33 @[lib.scala 354:16]
+    rvclkhdr_4.io.scan_mode <= UInt<1>("h00") @[lib.scala 355:23]
+    io.lsu_store_c1_m_clk <= rvclkhdr_4.io.l1clk @[lsu_clkdomain.scala 91:26]
+    node _T_34 = bits(lsu_store_c1_r_clken, 0, 0) @[lsu_clkdomain.scala 92:66]
+    inst rvclkhdr_5 of rvclkhdr_30 @[lib.scala 352:22]
+    rvclkhdr_5.clock <= clock
+    rvclkhdr_5.reset <= reset
+    rvclkhdr_5.io.clk <= clock @[lib.scala 353:17]
+    rvclkhdr_5.io.en <= _T_34 @[lib.scala 354:16]
+    rvclkhdr_5.io.scan_mode <= UInt<1>("h00") @[lib.scala 355:23]
+    io.lsu_store_c1_r_clk <= rvclkhdr_5.io.l1clk @[lsu_clkdomain.scala 92:26]
+    node _T_35 = bits(lsu_stbuf_c1_clken, 0, 0) @[lsu_clkdomain.scala 93:64]
+    inst rvclkhdr_6 of rvclkhdr_31 @[lib.scala 352:22]
+    rvclkhdr_6.clock <= clock
+    rvclkhdr_6.reset <= reset
+    rvclkhdr_6.io.clk <= clock @[lib.scala 353:17]
+    rvclkhdr_6.io.en <= _T_35 @[lib.scala 354:16]
+    rvclkhdr_6.io.scan_mode <= UInt<1>("h00") @[lib.scala 355:23]
+    io.lsu_stbuf_c1_clk <= rvclkhdr_6.io.l1clk @[lsu_clkdomain.scala 93:26]
+    node _T_36 = bits(lsu_bus_ibuf_c1_clken, 0, 0) @[lsu_clkdomain.scala 94:67]
+    inst rvclkhdr_7 of rvclkhdr_32 @[lib.scala 352:22]
+    rvclkhdr_7.clock <= clock
+    rvclkhdr_7.reset <= reset
+    rvclkhdr_7.io.clk <= clock @[lib.scala 353:17]
+    rvclkhdr_7.io.en <= _T_36 @[lib.scala 354:16]
+    rvclkhdr_7.io.scan_mode <= UInt<1>("h00") @[lib.scala 355:23]
+    io.lsu_bus_ibuf_c1_clk <= rvclkhdr_7.io.l1clk @[lsu_clkdomain.scala 94:26]
+    node _T_37 = bits(io.lsu_bus_obuf_c1_clken, 0, 0) @[lsu_clkdomain.scala 95:69]
+    inst rvclkhdr_8 of rvclkhdr_33 @[lib.scala 343:22]
+    rvclkhdr_8.clock <= clock
+    rvclkhdr_8.reset <= reset
+    rvclkhdr_8.io.clk <= clock @[lib.scala 344:17]
+    rvclkhdr_8.io.en <= _T_37 @[lib.scala 345:16]
+    rvclkhdr_8.io.scan_mode <= UInt<1>("h00") @[lib.scala 346:23]
+    io.lsu_bus_obuf_c1_clk <= rvclkhdr_8.io.l1clk @[lsu_clkdomain.scala 95:26]
+    node _T_38 = bits(lsu_bus_buf_c1_clken, 0, 0) @[lsu_clkdomain.scala 96:66]
+    inst rvclkhdr_9 of rvclkhdr_34 @[lib.scala 352:22]
+    rvclkhdr_9.clock <= clock
+    rvclkhdr_9.reset <= reset
+    rvclkhdr_9.io.clk <= clock @[lib.scala 353:17]
+    rvclkhdr_9.io.en <= _T_38 @[lib.scala 354:16]
+    rvclkhdr_9.io.scan_mode <= UInt<1>("h00") @[lib.scala 355:23]
+    io.lsu_bus_buf_c1_clk <= rvclkhdr_9.io.l1clk @[lsu_clkdomain.scala 96:26]
+    node _T_39 = bits(io.lsu_busm_clken, 0, 0) @[lsu_clkdomain.scala 97:62]
+    inst rvclkhdr_10 of rvclkhdr_35 @[lib.scala 343:22]
+    rvclkhdr_10.clock <= clock
+    rvclkhdr_10.reset <= reset
+    rvclkhdr_10.io.clk <= clock @[lib.scala 344:17]
+    rvclkhdr_10.io.en <= _T_39 @[lib.scala 345:16]
+    rvclkhdr_10.io.scan_mode <= UInt<1>("h00") @[lib.scala 346:23]
+    io.lsu_busm_clk <= rvclkhdr_10.io.l1clk @[lsu_clkdomain.scala 97:26]
+    node _T_40 = bits(lsu_free_c2_clken, 0, 0) @[lsu_clkdomain.scala 98:63]
+    inst rvclkhdr_11 of rvclkhdr_36 @[lib.scala 352:22]
+    rvclkhdr_11.clock <= clock
+    rvclkhdr_11.reset <= reset
+    rvclkhdr_11.io.clk <= clock @[lib.scala 353:17]
+    rvclkhdr_11.io.en <= _T_40 @[lib.scala 354:16]
+    rvclkhdr_11.io.scan_mode <= UInt<1>("h00") @[lib.scala 355:23]
+    io.lsu_free_c2_clk <= rvclkhdr_11.io.l1clk @[lsu_clkdomain.scala 98:26]
+    
   extmodule gated_latch_37 : 
     output Q : Clock
     input CK : Clock
@@ -8716,10 +8776,130 @@ circuit lsu :
     clkhdr.EN <= io.en @[lib.scala 337:18]
     clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
     
+  extmodule gated_latch_44 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr_44 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch_44 @[lib.scala 334:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 335:14]
+    clkhdr.CK <= io.clk @[lib.scala 336:18]
+    clkhdr.EN <= io.en @[lib.scala 337:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
+    
+  extmodule gated_latch_45 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr_45 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch_45 @[lib.scala 334:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 335:14]
+    clkhdr.CK <= io.clk @[lib.scala 336:18]
+    clkhdr.EN <= io.en @[lib.scala 337:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
+    
+  extmodule gated_latch_46 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr_46 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch_46 @[lib.scala 334:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 335:14]
+    clkhdr.CK <= io.clk @[lib.scala 336:18]
+    clkhdr.EN <= io.en @[lib.scala 337:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
+    
+  extmodule gated_latch_47 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr_47 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch_47 @[lib.scala 334:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 335:14]
+    clkhdr.CK <= io.clk @[lib.scala 336:18]
+    clkhdr.EN <= io.en @[lib.scala 337:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
+    
+  extmodule gated_latch_48 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr_48 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch_48 @[lib.scala 334:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 335:14]
+    clkhdr.CK <= io.clk @[lib.scala 336:18]
+    clkhdr.EN <= io.en @[lib.scala 337:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
+    
   module lsu_bus_buffer : 
     input clock : Clock
     input reset : AsyncReset
-    output io : {flip clk_override : UInt<1>, flip scan_mode : UInt<1>, tlu_busbuff : {lsu_pmu_bus_trxn : UInt<1>, lsu_pmu_bus_misaligned : UInt<1>, lsu_pmu_bus_error : UInt<1>, lsu_pmu_bus_busy : UInt<1>, flip dec_tlu_external_ldfwd_disable : UInt<1>, flip dec_tlu_wb_coalescing_disable : UInt<1>, flip dec_tlu_sideeffect_posted_disable : UInt<1>, lsu_imprecise_error_load_any : UInt<1>, lsu_imprecise_error_store_any : UInt<1>, lsu_imprecise_error_addr_any : UInt<32>}, dctl_busbuff : {lsu_nonblock_load_valid_m : UInt<1>, lsu_nonblock_load_tag_m : UInt<2>, lsu_nonblock_load_inv_r : UInt<1>, lsu_nonblock_load_inv_tag_r : UInt<2>, lsu_nonblock_load_data_valid : UInt<1>, lsu_nonblock_load_data_error : UInt<1>, lsu_nonblock_load_data_tag : UInt<2>, lsu_nonblock_load_data : UInt<32>}, flip dec_tlu_force_halt : UInt<1>, flip lsu_bus_obuf_c1_clken : UInt<1>, flip lsu_busm_clken : UInt<1>, flip lsu_c2_r_clk : Clock, flip lsu_bus_ibuf_c1_clk : Clock, flip lsu_bus_obuf_c1_clk : Clock, flip lsu_bus_buf_c1_clk : Clock, flip lsu_free_c2_clk : Clock, flip lsu_busm_clk : Clock, flip dec_lsu_valid_raw_d : UInt<1>, flip lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_pkt_r : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_addr_m : UInt<32>, flip end_addr_m : UInt<32>, flip lsu_addr_r : UInt<32>, flip end_addr_r : UInt<32>, flip store_data_r : UInt<32>, flip no_word_merge_r : UInt<1>, flip no_dword_merge_r : UInt<1>, flip lsu_busreq_m : UInt<1>, flip ld_full_hit_m : UInt<1>, flip flush_m_up : UInt<1>, flip flush_r : UInt<1>, flip lsu_commit_r : UInt<1>, flip is_sideeffects_r : UInt<1>, flip ldst_dual_d : UInt<1>, flip ldst_dual_m : UInt<1>, flip ldst_dual_r : UInt<1>, flip ldst_byteen_ext_m : UInt<8>, lsu_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip lsu_bus_clk_en : UInt<1>, flip lsu_bus_clk_en_q : UInt<1>, lsu_busreq_r : UInt<1>, lsu_bus_buffer_pend_any : UInt<1>, lsu_bus_buffer_full_any : UInt<1>, lsu_bus_buffer_empty_any : UInt<1>, ld_byte_hit_buf_lo : UInt<4>, ld_byte_hit_buf_hi : UInt<4>, ld_fwddata_buf_lo : UInt<32>, ld_fwddata_buf_hi : UInt<32>}
+    output io : {flip clk_override : UInt<1>, flip scan_mode : UInt<1>, tlu_busbuff : {lsu_pmu_bus_trxn : UInt<1>, lsu_pmu_bus_misaligned : UInt<1>, lsu_pmu_bus_error : UInt<1>, lsu_pmu_bus_busy : UInt<1>, flip dec_tlu_external_ldfwd_disable : UInt<1>, flip dec_tlu_wb_coalescing_disable : UInt<1>, flip dec_tlu_sideeffect_posted_disable : UInt<1>, lsu_imprecise_error_load_any : UInt<1>, lsu_imprecise_error_store_any : UInt<1>, lsu_imprecise_error_addr_any : UInt<32>}, dctl_busbuff : {lsu_nonblock_load_valid_m : UInt<1>, lsu_nonblock_load_tag_m : UInt<2>, lsu_nonblock_load_inv_r : UInt<1>, lsu_nonblock_load_inv_tag_r : UInt<2>, lsu_nonblock_load_data_valid : UInt<1>, lsu_nonblock_load_data_error : UInt<1>, lsu_nonblock_load_data_tag : UInt<2>, lsu_nonblock_load_data : UInt<32>}, flip dec_tlu_force_halt : UInt<1>, flip lsu_bus_obuf_c1_clken : UInt<1>, flip lsu_busm_clken : UInt<1>, flip lsu_c2_r_clk : Clock, flip lsu_bus_ibuf_c1_clk : Clock, flip lsu_bus_obuf_c1_clk : Clock, flip lsu_bus_buf_c1_clk : Clock, flip lsu_free_c2_clk : Clock, flip lsu_busm_clk : Clock, flip dec_lsu_valid_raw_d : UInt<1>, flip lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_pkt_r : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_addr_m : UInt<32>, flip end_addr_m : UInt<32>, flip lsu_addr_r : UInt<32>, flip end_addr_r : UInt<32>, flip store_data_r : UInt<32>, flip no_word_merge_r : UInt<1>, flip no_dword_merge_r : UInt<1>, flip lsu_busreq_m : UInt<1>, flip ld_full_hit_m : UInt<1>, flip flush_m_up : UInt<1>, flip flush_r : UInt<1>, flip lsu_commit_r : UInt<1>, flip is_sideeffects_r : UInt<1>, flip ldst_dual_d : UInt<1>, flip ldst_dual_m : UInt<1>, flip ldst_dual_r : UInt<1>, flip ldst_byteen_ext_m : UInt<8>, lsu_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip lsu_bus_clk_en : UInt<1>, flip lsu_bus_clk_en_q : UInt<1>, lsu_busreq_r : UInt<1>, lsu_bus_buffer_pend_any : UInt<1>, lsu_bus_buffer_full_any : UInt<1>, lsu_bus_buffer_empty_any : UInt<1>, ld_byte_hit_buf_lo : UInt<4>, ld_byte_hit_buf_hi : UInt<4>, ld_fwddata_buf_lo : UInt<32>, ld_fwddata_buf_hi : UInt<32>}
     
     wire buf_addr : UInt<32>[4] @[lsu_bus_buffer.scala 70:22]
     wire buf_state : UInt<3>[4] @[lsu_bus_buffer.scala 71:23]
@@ -8879,10 +9059,10 @@ circuit lsu :
     buf_ldfwdtag[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 117:16]
     buf_ldfwdtag[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 117:16]
     wire buf_rst : UInt<1>[4] @[lsu_bus_buffer.scala 118:21]
-    buf_rst[0] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 119:11]
-    buf_rst[1] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 119:11]
-    buf_rst[2] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 119:11]
-    buf_rst[3] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 119:11]
+    buf_rst[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 119:11]
+    buf_rst[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 119:11]
+    buf_rst[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 119:11]
+    buf_rst[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 119:11]
     wire ibuf_drainvec_vld : UInt<4>
     ibuf_drainvec_vld <= UInt<1>("h00")
     wire buf_byteen_in : UInt<4>[4] @[lsu_bus_buffer.scala 121:27]
@@ -9880,10 +10060,10 @@ circuit lsu :
     node _T_921 = cat(_T_920, _T_911) @[Cat.scala 29:58]
     node _T_922 = cat(_T_921, _T_902) @[Cat.scala 29:58]
     node ibuf_data_in = cat(_T_922, _T_893) @[Cat.scala 29:58]
-    node _T_923 = lt(ibuf_timer, UInt<3>("h07")) @[lsu_bus_buffer.scala 236:59]
-    node _T_924 = bits(_T_923, 0, 0) @[lsu_bus_buffer.scala 236:79]
-    node _T_925 = add(ibuf_timer, UInt<1>("h01")) @[lsu_bus_buffer.scala 236:93]
-    node _T_926 = tail(_T_925, 1) @[lsu_bus_buffer.scala 236:93]
+    node _T_923 = lt(ibuf_timer, UInt<3>("h07")) @[lsu_bus_buffer.scala 236:60]
+    node _T_924 = bits(_T_923, 0, 0) @[lsu_bus_buffer.scala 236:81]
+    node _T_925 = add(ibuf_timer, UInt<1>("h01")) @[lsu_bus_buffer.scala 236:95]
+    node _T_926 = tail(_T_925, 1) @[lsu_bus_buffer.scala 236:95]
     node _T_927 = mux(_T_924, _T_926, ibuf_timer) @[lsu_bus_buffer.scala 236:47]
     node ibuf_timer_in = mux(ibuf_wr_en, UInt<1>("h00"), _T_927) @[lsu_bus_buffer.scala 236:26]
     node _T_928 = and(io.lsu_busreq_r, io.lsu_commit_r) @[lsu_bus_buffer.scala 238:36]
@@ -10012,28 +10192,32 @@ circuit lsu :
     when ibuf_wr_en : @[Reg.scala 28:19]
       ibuf_sz <= ibuf_sz_in @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    inst rvclkhdr of rvclkhdr_32 @[lib.scala 368:23]
+    inst rvclkhdr of rvclkhdr_37 @[lib.scala 390:23]
     rvclkhdr.clock <= clock
     rvclkhdr.reset <= reset
-    rvclkhdr.io.clk <= clock @[lib.scala 370:18]
-    rvclkhdr.io.en <= ibuf_wr_en @[lib.scala 371:17]
-    rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
-    reg _T_1012 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
-    _T_1012 <= ibuf_addr_in @[lib.scala 374:16]
+    rvclkhdr.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr.io.en <= ibuf_wr_en @[lib.scala 393:17]
+    rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg _T_1012 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when ibuf_wr_en : @[Reg.scala 28:19]
+      _T_1012 <= ibuf_addr_in @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
     ibuf_addr <= _T_1012 @[lsu_bus_buffer.scala 253:13]
     reg _T_1013 : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
     when ibuf_wr_en : @[Reg.scala 28:19]
       _T_1013 <= ibuf_byteen_in @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
     ibuf_byteen <= _T_1013 @[lsu_bus_buffer.scala 254:15]
-    inst rvclkhdr_1 of rvclkhdr_33 @[lib.scala 368:23]
+    inst rvclkhdr_1 of rvclkhdr_38 @[lib.scala 390:23]
     rvclkhdr_1.clock <= clock
     rvclkhdr_1.reset <= reset
-    rvclkhdr_1.io.clk <= clock @[lib.scala 370:18]
-    rvclkhdr_1.io.en <= ibuf_wr_en @[lib.scala 371:17]
-    rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
-    reg _T_1014 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
-    _T_1014 <= ibuf_data_in @[lib.scala 374:16]
+    rvclkhdr_1.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr_1.io.en <= ibuf_wr_en @[lib.scala 393:17]
+    rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg _T_1014 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when ibuf_wr_en : @[Reg.scala 28:19]
+      _T_1014 <= ibuf_data_in @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
     ibuf_data <= _T_1014 @[lsu_bus_buffer.scala 255:13]
     reg _T_1015 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 256:55]
     _T_1015 <= ibuf_timer_in @[lsu_bus_buffer.scala 256:55]
@@ -10168,10 +10352,10 @@ circuit lsu :
     obuf_nosend <= UInt<1>("h00")
     wire bus_addr_match_pending : UInt<1>
     bus_addr_match_pending <= UInt<1>("h00")
-    node _T_1091 = and(ibuf_buf_byp, io.lsu_commit_r) @[lsu_bus_buffer.scala 287:32]
-    node _T_1092 = and(io.is_sideeffects_r, bus_sideeffect_pend) @[lsu_bus_buffer.scala 287:74]
-    node _T_1093 = eq(_T_1092, UInt<1>("h00")) @[lsu_bus_buffer.scala 287:52]
-    node _T_1094 = and(_T_1091, _T_1093) @[lsu_bus_buffer.scala 287:50]
+    node _T_1091 = and(ibuf_buf_byp, io.lsu_commit_r) @[lsu_bus_buffer.scala 288:32]
+    node _T_1092 = and(io.is_sideeffects_r, bus_sideeffect_pend) @[lsu_bus_buffer.scala 288:74]
+    node _T_1093 = eq(_T_1092, UInt<1>("h00")) @[lsu_bus_buffer.scala 288:52]
+    node _T_1094 = and(_T_1091, _T_1093) @[lsu_bus_buffer.scala 288:50]
     node _T_1095 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 61:123]
     node _T_1096 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 61:123]
     node _T_1097 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 61:123]
@@ -10185,8 +10369,8 @@ circuit lsu :
     node _T_1105 = or(_T_1104, _T_1102) @[Mux.scala 27:72]
     wire _T_1106 : UInt<3> @[Mux.scala 27:72]
     _T_1106 <= _T_1105 @[Mux.scala 27:72]
-    node _T_1107 = eq(_T_1106, UInt<3>("h02")) @[lsu_bus_buffer.scala 288:36]
-    node _T_1108 = and(_T_1107, found_cmdptr0) @[lsu_bus_buffer.scala 288:47]
+    node _T_1107 = eq(_T_1106, UInt<3>("h02")) @[lsu_bus_buffer.scala 289:36]
+    node _T_1108 = and(_T_1107, found_cmdptr0) @[lsu_bus_buffer.scala 289:47]
     node _T_1109 = cat(buf_cmd_state_bus_en[3], buf_cmd_state_bus_en[2]) @[Cat.scala 29:58]
     node _T_1110 = cat(_T_1109, buf_cmd_state_bus_en[1]) @[Cat.scala 29:58]
     node _T_1111 = cat(_T_1110, buf_cmd_state_bus_en[0]) @[Cat.scala 29:58]
@@ -10207,8 +10391,8 @@ circuit lsu :
     node _T_1126 = or(_T_1125, _T_1123) @[Mux.scala 27:72]
     wire _T_1127 : UInt<1> @[Mux.scala 27:72]
     _T_1127 <= _T_1126 @[Mux.scala 27:72]
-    node _T_1128 = eq(_T_1127, UInt<1>("h00")) @[lsu_bus_buffer.scala 289:23]
-    node _T_1129 = and(_T_1108, _T_1128) @[lsu_bus_buffer.scala 289:21]
+    node _T_1128 = eq(_T_1127, UInt<1>("h00")) @[lsu_bus_buffer.scala 290:23]
+    node _T_1129 = and(_T_1108, _T_1128) @[lsu_bus_buffer.scala 290:21]
     node _T_1130 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 60:118]
     node _T_1131 = bits(buf_sideeffect, 0, 0) @[lsu_bus_buffer.scala 60:129]
     node _T_1132 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 60:118]
@@ -10226,9 +10410,9 @@ circuit lsu :
     node _T_1144 = or(_T_1143, _T_1141) @[Mux.scala 27:72]
     wire _T_1145 : UInt<1> @[Mux.scala 27:72]
     _T_1145 <= _T_1144 @[Mux.scala 27:72]
-    node _T_1146 = and(_T_1145, bus_sideeffect_pend) @[lsu_bus_buffer.scala 289:141]
-    node _T_1147 = eq(_T_1146, UInt<1>("h00")) @[lsu_bus_buffer.scala 289:105]
-    node _T_1148 = and(_T_1129, _T_1147) @[lsu_bus_buffer.scala 289:103]
+    node _T_1146 = and(_T_1145, bus_sideeffect_pend) @[lsu_bus_buffer.scala 290:141]
+    node _T_1147 = eq(_T_1146, UInt<1>("h00")) @[lsu_bus_buffer.scala 290:105]
+    node _T_1148 = and(_T_1129, _T_1147) @[lsu_bus_buffer.scala 290:103]
     node _T_1149 = cat(buf_dual[3], buf_dual[2]) @[Cat.scala 29:58]
     node _T_1150 = cat(_T_1149, buf_dual[1]) @[Cat.scala 29:58]
     node _T_1151 = cat(_T_1150, buf_dual[0]) @[Cat.scala 29:58]
@@ -10269,7 +10453,7 @@ circuit lsu :
     node _T_1185 = or(_T_1184, _T_1182) @[Mux.scala 27:72]
     wire _T_1186 : UInt<1> @[Mux.scala 27:72]
     _T_1186 <= _T_1185 @[Mux.scala 27:72]
-    node _T_1187 = and(_T_1167, _T_1186) @[lsu_bus_buffer.scala 290:77]
+    node _T_1187 = and(_T_1167, _T_1186) @[lsu_bus_buffer.scala 291:77]
     node _T_1188 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 60:118]
     node _T_1189 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 60:129]
     node _T_1190 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 60:118]
@@ -10287,10 +10471,10 @@ circuit lsu :
     node _T_1202 = or(_T_1201, _T_1199) @[Mux.scala 27:72]
     wire _T_1203 : UInt<1> @[Mux.scala 27:72]
     _T_1203 <= _T_1202 @[Mux.scala 27:72]
-    node _T_1204 = eq(_T_1203, UInt<1>("h00")) @[lsu_bus_buffer.scala 290:150]
-    node _T_1205 = and(_T_1187, _T_1204) @[lsu_bus_buffer.scala 290:148]
-    node _T_1206 = eq(_T_1205, UInt<1>("h00")) @[lsu_bus_buffer.scala 290:8]
-    node _T_1207 = or(_T_1206, found_cmdptr1) @[lsu_bus_buffer.scala 290:181]
+    node _T_1204 = eq(_T_1203, UInt<1>("h00")) @[lsu_bus_buffer.scala 291:150]
+    node _T_1205 = and(_T_1187, _T_1204) @[lsu_bus_buffer.scala 291:148]
+    node _T_1206 = eq(_T_1205, UInt<1>("h00")) @[lsu_bus_buffer.scala 291:8]
+    node _T_1207 = or(_T_1206, found_cmdptr1) @[lsu_bus_buffer.scala 291:181]
     node _T_1208 = cat(buf_nomerge[3], buf_nomerge[2]) @[Cat.scala 29:58]
     node _T_1209 = cat(_T_1208, buf_nomerge[1]) @[Cat.scala 29:58]
     node _T_1210 = cat(_T_1209, buf_nomerge[0]) @[Cat.scala 29:58]
@@ -10311,28 +10495,28 @@ circuit lsu :
     node _T_1225 = or(_T_1224, _T_1222) @[Mux.scala 27:72]
     wire _T_1226 : UInt<1> @[Mux.scala 27:72]
     _T_1226 <= _T_1225 @[Mux.scala 27:72]
-    node _T_1227 = or(_T_1207, _T_1226) @[lsu_bus_buffer.scala 290:197]
-    node _T_1228 = or(_T_1227, obuf_force_wr_en) @[lsu_bus_buffer.scala 290:269]
-    node _T_1229 = and(_T_1148, _T_1228) @[lsu_bus_buffer.scala 289:164]
-    node _T_1230 = or(_T_1094, _T_1229) @[lsu_bus_buffer.scala 287:98]
-    node _T_1231 = eq(obuf_valid, UInt<1>("h00")) @[lsu_bus_buffer.scala 291:48]
-    node _T_1232 = or(bus_cmd_ready, _T_1231) @[lsu_bus_buffer.scala 291:46]
-    node _T_1233 = or(_T_1232, obuf_nosend) @[lsu_bus_buffer.scala 291:60]
-    node _T_1234 = and(_T_1230, _T_1233) @[lsu_bus_buffer.scala 291:29]
-    node _T_1235 = eq(obuf_wr_wait, UInt<1>("h00")) @[lsu_bus_buffer.scala 291:77]
-    node _T_1236 = and(_T_1234, _T_1235) @[lsu_bus_buffer.scala 291:75]
-    node _T_1237 = eq(bus_addr_match_pending, UInt<1>("h00")) @[lsu_bus_buffer.scala 291:94]
-    node _T_1238 = and(_T_1236, _T_1237) @[lsu_bus_buffer.scala 291:92]
-    node _T_1239 = and(_T_1238, io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 291:118]
-    obuf_wr_en <= _T_1239 @[lsu_bus_buffer.scala 287:14]
+    node _T_1227 = or(_T_1207, _T_1226) @[lsu_bus_buffer.scala 291:197]
+    node _T_1228 = or(_T_1227, obuf_force_wr_en) @[lsu_bus_buffer.scala 291:269]
+    node _T_1229 = and(_T_1148, _T_1228) @[lsu_bus_buffer.scala 290:164]
+    node _T_1230 = or(_T_1094, _T_1229) @[lsu_bus_buffer.scala 288:98]
+    node _T_1231 = eq(obuf_valid, UInt<1>("h00")) @[lsu_bus_buffer.scala 292:48]
+    node _T_1232 = or(bus_cmd_ready, _T_1231) @[lsu_bus_buffer.scala 292:46]
+    node _T_1233 = or(_T_1232, obuf_nosend) @[lsu_bus_buffer.scala 292:60]
+    node _T_1234 = and(_T_1230, _T_1233) @[lsu_bus_buffer.scala 292:29]
+    node _T_1235 = eq(obuf_wr_wait, UInt<1>("h00")) @[lsu_bus_buffer.scala 292:77]
+    node _T_1236 = and(_T_1234, _T_1235) @[lsu_bus_buffer.scala 292:75]
+    node _T_1237 = eq(bus_addr_match_pending, UInt<1>("h00")) @[lsu_bus_buffer.scala 292:94]
+    node _T_1238 = and(_T_1236, _T_1237) @[lsu_bus_buffer.scala 292:92]
+    node _T_1239 = and(_T_1238, io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 292:118]
+    obuf_wr_en <= _T_1239 @[lsu_bus_buffer.scala 288:14]
     wire bus_cmd_sent : UInt<1>
     bus_cmd_sent <= UInt<1>("h00")
-    node _T_1240 = and(obuf_valid, obuf_nosend) @[lsu_bus_buffer.scala 293:47]
-    node _T_1241 = or(bus_cmd_sent, _T_1240) @[lsu_bus_buffer.scala 293:33]
-    node _T_1242 = eq(obuf_wr_en, UInt<1>("h00")) @[lsu_bus_buffer.scala 293:65]
-    node _T_1243 = and(_T_1241, _T_1242) @[lsu_bus_buffer.scala 293:63]
-    node _T_1244 = and(_T_1243, io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 293:77]
-    node obuf_rst = or(_T_1244, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 293:98]
+    node _T_1240 = and(obuf_valid, obuf_nosend) @[lsu_bus_buffer.scala 295:47]
+    node _T_1241 = or(bus_cmd_sent, _T_1240) @[lsu_bus_buffer.scala 295:33]
+    node _T_1242 = eq(obuf_wr_en, UInt<1>("h00")) @[lsu_bus_buffer.scala 295:65]
+    node _T_1243 = and(_T_1241, _T_1242) @[lsu_bus_buffer.scala 295:63]
+    node _T_1244 = and(_T_1243, io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 295:77]
+    node obuf_rst = or(_T_1244, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 295:98]
     node _T_1245 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 60:118]
     node _T_1246 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 60:129]
     node _T_1247 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 60:118]
@@ -10350,7 +10534,7 @@ circuit lsu :
     node _T_1259 = or(_T_1258, _T_1256) @[Mux.scala 27:72]
     wire _T_1260 : UInt<1> @[Mux.scala 27:72]
     _T_1260 <= _T_1259 @[Mux.scala 27:72]
-    node obuf_write_in = mux(ibuf_buf_byp, io.lsu_pkt_r.bits.store, _T_1260) @[lsu_bus_buffer.scala 294:26]
+    node obuf_write_in = mux(ibuf_buf_byp, io.lsu_pkt_r.bits.store, _T_1260) @[lsu_bus_buffer.scala 296:26]
     node _T_1261 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 60:118]
     node _T_1262 = bits(buf_sideeffect, 0, 0) @[lsu_bus_buffer.scala 60:129]
     node _T_1263 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 60:118]
@@ -10368,7 +10552,7 @@ circuit lsu :
     node _T_1275 = or(_T_1274, _T_1272) @[Mux.scala 27:72]
     wire _T_1276 : UInt<1> @[Mux.scala 27:72]
     _T_1276 <= _T_1275 @[Mux.scala 27:72]
-    node obuf_sideeffect_in = mux(ibuf_buf_byp, io.is_sideeffects_r, _T_1276) @[lsu_bus_buffer.scala 295:31]
+    node obuf_sideeffect_in = mux(ibuf_buf_byp, io.is_sideeffects_r, _T_1276) @[lsu_bus_buffer.scala 297:31]
     node _T_1277 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 61:123]
     node _T_1278 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 61:123]
     node _T_1279 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 61:123]
@@ -10382,12 +10566,12 @@ circuit lsu :
     node _T_1287 = or(_T_1286, _T_1284) @[Mux.scala 27:72]
     wire _T_1288 : UInt<32> @[Mux.scala 27:72]
     _T_1288 <= _T_1287 @[Mux.scala 27:72]
-    node obuf_addr_in = mux(ibuf_buf_byp, io.lsu_addr_r, _T_1288) @[lsu_bus_buffer.scala 296:25]
-    wire buf_sz : UInt<2>[4] @[lsu_bus_buffer.scala 297:20]
-    buf_sz[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 298:10]
-    buf_sz[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 298:10]
-    buf_sz[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 298:10]
-    buf_sz[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 298:10]
+    node obuf_addr_in = mux(ibuf_buf_byp, io.lsu_addr_r, _T_1288) @[lsu_bus_buffer.scala 298:25]
+    wire buf_sz : UInt<2>[4] @[lsu_bus_buffer.scala 299:20]
+    buf_sz[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 300:10]
+    buf_sz[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 300:10]
+    buf_sz[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 300:10]
+    buf_sz[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 300:10]
     node _T_1289 = cat(io.lsu_pkt_r.bits.word, io.lsu_pkt_r.bits.half) @[Cat.scala 29:58]
     node _T_1290 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 61:123]
     node _T_1291 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 61:123]
@@ -10402,41 +10586,41 @@ circuit lsu :
     node _T_1300 = or(_T_1299, _T_1297) @[Mux.scala 27:72]
     wire _T_1301 : UInt<2> @[Mux.scala 27:72]
     _T_1301 <= _T_1300 @[Mux.scala 27:72]
-    node obuf_sz_in = mux(ibuf_buf_byp, _T_1289, _T_1301) @[lsu_bus_buffer.scala 299:23]
+    node obuf_sz_in = mux(ibuf_buf_byp, _T_1289, _T_1301) @[lsu_bus_buffer.scala 301:23]
     wire obuf_merge_en : UInt<1>
     obuf_merge_en <= UInt<1>("h00")
-    node obuf_tag0_in = mux(ibuf_buf_byp, WrPtr0_r, CmdPtr0) @[lsu_bus_buffer.scala 302:25]
-    node obuf_tag1_in = mux(ibuf_buf_byp, WrPtr1_r, CmdPtr1) @[lsu_bus_buffer.scala 304:25]
+    node obuf_tag0_in = mux(ibuf_buf_byp, WrPtr0_r, CmdPtr0) @[lsu_bus_buffer.scala 304:25]
+    node obuf_tag1_in = mux(ibuf_buf_byp, WrPtr1_r, CmdPtr1) @[lsu_bus_buffer.scala 306:25]
     wire obuf_cmd_done : UInt<1>
     obuf_cmd_done <= UInt<1>("h00")
     wire bus_wcmd_sent : UInt<1>
     bus_wcmd_sent <= UInt<1>("h00")
-    node _T_1302 = or(obuf_wr_en, obuf_rst) @[lsu_bus_buffer.scala 307:39]
-    node _T_1303 = eq(_T_1302, UInt<1>("h00")) @[lsu_bus_buffer.scala 307:26]
-    node _T_1304 = or(obuf_cmd_done, bus_wcmd_sent) @[lsu_bus_buffer.scala 307:68]
-    node obuf_cmd_done_in = and(_T_1303, _T_1304) @[lsu_bus_buffer.scala 307:51]
+    node _T_1302 = or(obuf_wr_en, obuf_rst) @[lsu_bus_buffer.scala 309:39]
+    node _T_1303 = eq(_T_1302, UInt<1>("h00")) @[lsu_bus_buffer.scala 309:26]
+    node _T_1304 = or(obuf_cmd_done, bus_wcmd_sent) @[lsu_bus_buffer.scala 309:68]
+    node obuf_cmd_done_in = and(_T_1303, _T_1304) @[lsu_bus_buffer.scala 309:51]
     wire obuf_data_done : UInt<1>
     obuf_data_done <= UInt<1>("h00")
     wire bus_wdata_sent : UInt<1>
     bus_wdata_sent <= UInt<1>("h00")
-    node _T_1305 = or(obuf_wr_en, obuf_rst) @[lsu_bus_buffer.scala 310:40]
-    node _T_1306 = eq(_T_1305, UInt<1>("h00")) @[lsu_bus_buffer.scala 310:27]
-    node _T_1307 = or(obuf_data_done, bus_wdata_sent) @[lsu_bus_buffer.scala 310:70]
-    node obuf_data_done_in = and(_T_1306, _T_1307) @[lsu_bus_buffer.scala 310:52]
-    node _T_1308 = bits(obuf_sz_in, 1, 0) @[lsu_bus_buffer.scala 311:67]
-    node _T_1309 = eq(_T_1308, UInt<1>("h00")) @[lsu_bus_buffer.scala 311:72]
-    node _T_1310 = bits(obuf_sz_in, 0, 0) @[lsu_bus_buffer.scala 311:92]
-    node _T_1311 = bits(obuf_addr_in, 0, 0) @[lsu_bus_buffer.scala 311:111]
-    node _T_1312 = eq(_T_1311, UInt<1>("h00")) @[lsu_bus_buffer.scala 311:98]
-    node _T_1313 = and(_T_1310, _T_1312) @[lsu_bus_buffer.scala 311:96]
-    node _T_1314 = or(_T_1309, _T_1313) @[lsu_bus_buffer.scala 311:79]
-    node _T_1315 = bits(obuf_sz_in, 1, 1) @[lsu_bus_buffer.scala 311:129]
-    node _T_1316 = bits(obuf_addr_in, 1, 0) @[lsu_bus_buffer.scala 311:147]
-    node _T_1317 = orr(_T_1316) @[lsu_bus_buffer.scala 311:153]
-    node _T_1318 = eq(_T_1317, UInt<1>("h00")) @[lsu_bus_buffer.scala 311:134]
-    node _T_1319 = and(_T_1315, _T_1318) @[lsu_bus_buffer.scala 311:132]
-    node _T_1320 = or(_T_1314, _T_1319) @[lsu_bus_buffer.scala 311:116]
-    node obuf_aligned_in = mux(ibuf_buf_byp, is_aligned_r, _T_1320) @[lsu_bus_buffer.scala 311:28]
+    node _T_1305 = or(obuf_wr_en, obuf_rst) @[lsu_bus_buffer.scala 312:40]
+    node _T_1306 = eq(_T_1305, UInt<1>("h00")) @[lsu_bus_buffer.scala 312:27]
+    node _T_1307 = or(obuf_data_done, bus_wdata_sent) @[lsu_bus_buffer.scala 312:70]
+    node obuf_data_done_in = and(_T_1306, _T_1307) @[lsu_bus_buffer.scala 312:52]
+    node _T_1308 = bits(obuf_sz_in, 1, 0) @[lsu_bus_buffer.scala 313:67]
+    node _T_1309 = eq(_T_1308, UInt<1>("h00")) @[lsu_bus_buffer.scala 313:72]
+    node _T_1310 = bits(obuf_sz_in, 0, 0) @[lsu_bus_buffer.scala 313:92]
+    node _T_1311 = bits(obuf_addr_in, 0, 0) @[lsu_bus_buffer.scala 313:111]
+    node _T_1312 = eq(_T_1311, UInt<1>("h00")) @[lsu_bus_buffer.scala 313:98]
+    node _T_1313 = and(_T_1310, _T_1312) @[lsu_bus_buffer.scala 313:96]
+    node _T_1314 = or(_T_1309, _T_1313) @[lsu_bus_buffer.scala 313:79]
+    node _T_1315 = bits(obuf_sz_in, 1, 1) @[lsu_bus_buffer.scala 313:129]
+    node _T_1316 = bits(obuf_addr_in, 1, 0) @[lsu_bus_buffer.scala 313:147]
+    node _T_1317 = orr(_T_1316) @[lsu_bus_buffer.scala 313:153]
+    node _T_1318 = eq(_T_1317, UInt<1>("h00")) @[lsu_bus_buffer.scala 313:134]
+    node _T_1319 = and(_T_1315, _T_1318) @[lsu_bus_buffer.scala 313:132]
+    node _T_1320 = or(_T_1314, _T_1319) @[lsu_bus_buffer.scala 313:116]
+    node obuf_aligned_in = mux(ibuf_buf_byp, is_aligned_r, _T_1320) @[lsu_bus_buffer.scala 313:28]
     wire obuf_nosend_in : UInt<1>
     obuf_nosend_in <= UInt<1>("h00")
     wire obuf_rdrsp_pend : UInt<1>
@@ -10449,54 +10633,54 @@ circuit lsu :
     obuf_rdrsp_tag <= UInt<1>("h00")
     wire obuf_write : UInt<1>
     obuf_write <= UInt<1>("h00")
-    node _T_1321 = eq(obuf_nosend_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 319:45]
-    node _T_1322 = and(obuf_wr_en, _T_1321) @[lsu_bus_buffer.scala 319:43]
-    node _T_1323 = eq(_T_1322, UInt<1>("h00")) @[lsu_bus_buffer.scala 319:30]
-    node _T_1324 = and(_T_1323, obuf_rdrsp_pend) @[lsu_bus_buffer.scala 319:62]
-    node _T_1325 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[lsu_bus_buffer.scala 319:117]
-    node _T_1326 = and(bus_rsp_read, _T_1325) @[lsu_bus_buffer.scala 319:97]
-    node _T_1327 = eq(_T_1326, UInt<1>("h00")) @[lsu_bus_buffer.scala 319:82]
-    node _T_1328 = and(_T_1324, _T_1327) @[lsu_bus_buffer.scala 319:80]
-    node _T_1329 = eq(obuf_write, UInt<1>("h00")) @[lsu_bus_buffer.scala 320:21]
-    node _T_1330 = and(bus_cmd_sent, _T_1329) @[lsu_bus_buffer.scala 320:19]
-    node _T_1331 = or(_T_1328, _T_1330) @[lsu_bus_buffer.scala 319:139]
-    node _T_1332 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 320:37]
-    node obuf_rdrsp_pend_in = and(_T_1331, _T_1332) @[lsu_bus_buffer.scala 320:35]
-    node obuf_rdrsp_pend_en = or(io.lsu_bus_clk_en, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 321:47]
+    node _T_1321 = eq(obuf_nosend_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 321:45]
+    node _T_1322 = and(obuf_wr_en, _T_1321) @[lsu_bus_buffer.scala 321:43]
+    node _T_1323 = eq(_T_1322, UInt<1>("h00")) @[lsu_bus_buffer.scala 321:30]
+    node _T_1324 = and(_T_1323, obuf_rdrsp_pend) @[lsu_bus_buffer.scala 321:62]
+    node _T_1325 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[lsu_bus_buffer.scala 321:117]
+    node _T_1326 = and(bus_rsp_read, _T_1325) @[lsu_bus_buffer.scala 321:97]
+    node _T_1327 = eq(_T_1326, UInt<1>("h00")) @[lsu_bus_buffer.scala 321:82]
+    node _T_1328 = and(_T_1324, _T_1327) @[lsu_bus_buffer.scala 321:80]
+    node _T_1329 = eq(obuf_write, UInt<1>("h00")) @[lsu_bus_buffer.scala 321:157]
+    node _T_1330 = and(bus_cmd_sent, _T_1329) @[lsu_bus_buffer.scala 321:155]
+    node _T_1331 = or(_T_1328, _T_1330) @[lsu_bus_buffer.scala 321:139]
+    node _T_1332 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 321:173]
+    node obuf_rdrsp_pend_in = and(_T_1331, _T_1332) @[lsu_bus_buffer.scala 321:171]
+    node obuf_rdrsp_pend_en = or(io.lsu_bus_clk_en, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 322:47]
     wire obuf_tag0 : UInt<3>
     obuf_tag0 <= UInt<1>("h00")
-    node _T_1333 = eq(obuf_write, UInt<1>("h00")) @[lsu_bus_buffer.scala 323:46]
-    node _T_1334 = and(bus_cmd_sent, _T_1333) @[lsu_bus_buffer.scala 323:44]
-    node obuf_rdrsp_tag_in = mux(_T_1334, obuf_tag0, obuf_rdrsp_tag) @[lsu_bus_buffer.scala 323:30]
+    node _T_1333 = eq(obuf_write, UInt<1>("h00")) @[lsu_bus_buffer.scala 324:46]
+    node _T_1334 = and(bus_cmd_sent, _T_1333) @[lsu_bus_buffer.scala 324:44]
+    node obuf_rdrsp_tag_in = mux(_T_1334, obuf_tag0, obuf_rdrsp_tag) @[lsu_bus_buffer.scala 324:30]
     wire obuf_addr : UInt<32>
     obuf_addr <= UInt<1>("h00")
     wire obuf_sideeffect : UInt<1>
     obuf_sideeffect <= UInt<1>("h00")
-    node _T_1335 = bits(obuf_addr_in, 31, 3) @[lsu_bus_buffer.scala 326:34]
-    node _T_1336 = bits(obuf_addr, 31, 3) @[lsu_bus_buffer.scala 326:52]
-    node _T_1337 = eq(_T_1335, _T_1336) @[lsu_bus_buffer.scala 326:40]
-    node _T_1338 = and(_T_1337, obuf_aligned_in) @[lsu_bus_buffer.scala 326:60]
-    node _T_1339 = eq(obuf_sideeffect, UInt<1>("h00")) @[lsu_bus_buffer.scala 326:80]
-    node _T_1340 = and(_T_1338, _T_1339) @[lsu_bus_buffer.scala 326:78]
-    node _T_1341 = eq(obuf_write, UInt<1>("h00")) @[lsu_bus_buffer.scala 326:99]
-    node _T_1342 = and(_T_1340, _T_1341) @[lsu_bus_buffer.scala 326:97]
-    node _T_1343 = eq(obuf_write_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 326:113]
-    node _T_1344 = and(_T_1342, _T_1343) @[lsu_bus_buffer.scala 326:111]
-    node _T_1345 = eq(io.tlu_busbuff.dec_tlu_external_ldfwd_disable, UInt<1>("h00")) @[lsu_bus_buffer.scala 326:130]
-    node _T_1346 = and(_T_1344, _T_1345) @[lsu_bus_buffer.scala 326:128]
-    node _T_1347 = eq(obuf_nosend, UInt<1>("h00")) @[lsu_bus_buffer.scala 327:20]
-    node _T_1348 = and(obuf_valid, _T_1347) @[lsu_bus_buffer.scala 327:18]
-    node _T_1349 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[lsu_bus_buffer.scala 327:90]
-    node _T_1350 = and(bus_rsp_read, _T_1349) @[lsu_bus_buffer.scala 327:70]
-    node _T_1351 = eq(_T_1350, UInt<1>("h00")) @[lsu_bus_buffer.scala 327:55]
-    node _T_1352 = and(obuf_rdrsp_pend, _T_1351) @[lsu_bus_buffer.scala 327:53]
-    node _T_1353 = or(_T_1348, _T_1352) @[lsu_bus_buffer.scala 327:34]
-    node _T_1354 = and(_T_1346, _T_1353) @[lsu_bus_buffer.scala 326:177]
-    obuf_nosend_in <= _T_1354 @[lsu_bus_buffer.scala 326:18]
-    node _T_1355 = bits(io.lsu_addr_r, 2, 2) @[lsu_bus_buffer.scala 328:60]
+    node _T_1335 = bits(obuf_addr_in, 31, 3) @[lsu_bus_buffer.scala 327:34]
+    node _T_1336 = bits(obuf_addr, 31, 3) @[lsu_bus_buffer.scala 327:52]
+    node _T_1337 = eq(_T_1335, _T_1336) @[lsu_bus_buffer.scala 327:40]
+    node _T_1338 = and(_T_1337, obuf_aligned_in) @[lsu_bus_buffer.scala 327:60]
+    node _T_1339 = eq(obuf_sideeffect, UInt<1>("h00")) @[lsu_bus_buffer.scala 327:80]
+    node _T_1340 = and(_T_1338, _T_1339) @[lsu_bus_buffer.scala 327:78]
+    node _T_1341 = eq(obuf_write, UInt<1>("h00")) @[lsu_bus_buffer.scala 327:99]
+    node _T_1342 = and(_T_1340, _T_1341) @[lsu_bus_buffer.scala 327:97]
+    node _T_1343 = eq(obuf_write_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 327:113]
+    node _T_1344 = and(_T_1342, _T_1343) @[lsu_bus_buffer.scala 327:111]
+    node _T_1345 = eq(io.tlu_busbuff.dec_tlu_external_ldfwd_disable, UInt<1>("h00")) @[lsu_bus_buffer.scala 327:130]
+    node _T_1346 = and(_T_1344, _T_1345) @[lsu_bus_buffer.scala 327:128]
+    node _T_1347 = eq(obuf_nosend, UInt<1>("h00")) @[lsu_bus_buffer.scala 328:20]
+    node _T_1348 = and(obuf_valid, _T_1347) @[lsu_bus_buffer.scala 328:18]
+    node _T_1349 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[lsu_bus_buffer.scala 328:90]
+    node _T_1350 = and(bus_rsp_read, _T_1349) @[lsu_bus_buffer.scala 328:70]
+    node _T_1351 = eq(_T_1350, UInt<1>("h00")) @[lsu_bus_buffer.scala 328:55]
+    node _T_1352 = and(obuf_rdrsp_pend, _T_1351) @[lsu_bus_buffer.scala 328:53]
+    node _T_1353 = or(_T_1348, _T_1352) @[lsu_bus_buffer.scala 328:34]
+    node _T_1354 = and(_T_1346, _T_1353) @[lsu_bus_buffer.scala 327:177]
+    obuf_nosend_in <= _T_1354 @[lsu_bus_buffer.scala 327:18]
+    node _T_1355 = bits(io.lsu_addr_r, 2, 2) @[lsu_bus_buffer.scala 329:60]
     node _T_1356 = cat(ldst_byteen_lo_r, UInt<4>("h00")) @[Cat.scala 29:58]
     node _T_1357 = cat(UInt<4>("h00"), ldst_byteen_lo_r) @[Cat.scala 29:58]
-    node _T_1358 = mux(_T_1355, _T_1356, _T_1357) @[lsu_bus_buffer.scala 328:46]
+    node _T_1358 = mux(_T_1355, _T_1356, _T_1357) @[lsu_bus_buffer.scala 329:46]
     node _T_1359 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 61:123]
     node _T_1360 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 61:123]
     node _T_1361 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 61:123]
@@ -10510,8 +10694,8 @@ circuit lsu :
     node _T_1369 = or(_T_1368, _T_1366) @[Mux.scala 27:72]
     wire _T_1370 : UInt<32> @[Mux.scala 27:72]
     _T_1370 <= _T_1369 @[Mux.scala 27:72]
-    node _T_1371 = bits(_T_1370, 2, 2) @[lsu_bus_buffer.scala 329:36]
-    node _T_1372 = bits(_T_1371, 0, 0) @[lsu_bus_buffer.scala 329:46]
+    node _T_1371 = bits(_T_1370, 2, 2) @[lsu_bus_buffer.scala 330:36]
+    node _T_1372 = bits(_T_1371, 0, 0) @[lsu_bus_buffer.scala 330:46]
     node _T_1373 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 61:123]
     node _T_1374 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 61:123]
     node _T_1375 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 61:123]
@@ -10540,12 +10724,12 @@ circuit lsu :
     wire _T_1397 : UInt<4> @[Mux.scala 27:72]
     _T_1397 <= _T_1396 @[Mux.scala 27:72]
     node _T_1398 = cat(UInt<4>("h00"), _T_1397) @[Cat.scala 29:58]
-    node _T_1399 = mux(_T_1372, _T_1385, _T_1398) @[lsu_bus_buffer.scala 329:8]
-    node obuf_byteen0_in = mux(ibuf_buf_byp, _T_1358, _T_1399) @[lsu_bus_buffer.scala 328:28]
-    node _T_1400 = bits(io.end_addr_r, 2, 2) @[lsu_bus_buffer.scala 330:60]
+    node _T_1399 = mux(_T_1372, _T_1385, _T_1398) @[lsu_bus_buffer.scala 330:8]
+    node obuf_byteen0_in = mux(ibuf_buf_byp, _T_1358, _T_1399) @[lsu_bus_buffer.scala 329:28]
+    node _T_1400 = bits(io.end_addr_r, 2, 2) @[lsu_bus_buffer.scala 331:60]
     node _T_1401 = cat(ldst_byteen_hi_r, UInt<4>("h00")) @[Cat.scala 29:58]
     node _T_1402 = cat(UInt<4>("h00"), ldst_byteen_hi_r) @[Cat.scala 29:58]
-    node _T_1403 = mux(_T_1400, _T_1401, _T_1402) @[lsu_bus_buffer.scala 330:46]
+    node _T_1403 = mux(_T_1400, _T_1401, _T_1402) @[lsu_bus_buffer.scala 331:46]
     node _T_1404 = eq(CmdPtr1, UInt<1>("h00")) @[lsu_bus_buffer.scala 61:123]
     node _T_1405 = eq(CmdPtr1, UInt<1>("h01")) @[lsu_bus_buffer.scala 61:123]
     node _T_1406 = eq(CmdPtr1, UInt<2>("h02")) @[lsu_bus_buffer.scala 61:123]
@@ -10559,8 +10743,8 @@ circuit lsu :
     node _T_1414 = or(_T_1413, _T_1411) @[Mux.scala 27:72]
     wire _T_1415 : UInt<32> @[Mux.scala 27:72]
     _T_1415 <= _T_1414 @[Mux.scala 27:72]
-    node _T_1416 = bits(_T_1415, 2, 2) @[lsu_bus_buffer.scala 331:36]
-    node _T_1417 = bits(_T_1416, 0, 0) @[lsu_bus_buffer.scala 331:46]
+    node _T_1416 = bits(_T_1415, 2, 2) @[lsu_bus_buffer.scala 332:36]
+    node _T_1417 = bits(_T_1416, 0, 0) @[lsu_bus_buffer.scala 332:46]
     node _T_1418 = eq(CmdPtr1, UInt<1>("h00")) @[lsu_bus_buffer.scala 61:123]
     node _T_1419 = eq(CmdPtr1, UInt<1>("h01")) @[lsu_bus_buffer.scala 61:123]
     node _T_1420 = eq(CmdPtr1, UInt<2>("h02")) @[lsu_bus_buffer.scala 61:123]
@@ -10589,12 +10773,12 @@ circuit lsu :
     wire _T_1442 : UInt<4> @[Mux.scala 27:72]
     _T_1442 <= _T_1441 @[Mux.scala 27:72]
     node _T_1443 = cat(UInt<4>("h00"), _T_1442) @[Cat.scala 29:58]
-    node _T_1444 = mux(_T_1417, _T_1430, _T_1443) @[lsu_bus_buffer.scala 331:8]
-    node obuf_byteen1_in = mux(ibuf_buf_byp, _T_1403, _T_1444) @[lsu_bus_buffer.scala 330:28]
-    node _T_1445 = bits(io.lsu_addr_r, 2, 2) @[lsu_bus_buffer.scala 333:58]
+    node _T_1444 = mux(_T_1417, _T_1430, _T_1443) @[lsu_bus_buffer.scala 332:8]
+    node obuf_byteen1_in = mux(ibuf_buf_byp, _T_1403, _T_1444) @[lsu_bus_buffer.scala 331:28]
+    node _T_1445 = bits(io.lsu_addr_r, 2, 2) @[lsu_bus_buffer.scala 334:58]
     node _T_1446 = cat(store_data_lo_r, UInt<32>("h00")) @[Cat.scala 29:58]
     node _T_1447 = cat(UInt<32>("h00"), store_data_lo_r) @[Cat.scala 29:58]
-    node _T_1448 = mux(_T_1445, _T_1446, _T_1447) @[lsu_bus_buffer.scala 333:44]
+    node _T_1448 = mux(_T_1445, _T_1446, _T_1447) @[lsu_bus_buffer.scala 334:44]
     node _T_1449 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 61:123]
     node _T_1450 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 61:123]
     node _T_1451 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 61:123]
@@ -10608,8 +10792,8 @@ circuit lsu :
     node _T_1459 = or(_T_1458, _T_1456) @[Mux.scala 27:72]
     wire _T_1460 : UInt<32> @[Mux.scala 27:72]
     _T_1460 <= _T_1459 @[Mux.scala 27:72]
-    node _T_1461 = bits(_T_1460, 2, 2) @[lsu_bus_buffer.scala 334:36]
-    node _T_1462 = bits(_T_1461, 0, 0) @[lsu_bus_buffer.scala 334:46]
+    node _T_1461 = bits(_T_1460, 2, 2) @[lsu_bus_buffer.scala 335:36]
+    node _T_1462 = bits(_T_1461, 0, 0) @[lsu_bus_buffer.scala 335:46]
     node _T_1463 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 61:123]
     node _T_1464 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 61:123]
     node _T_1465 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 61:123]
@@ -10638,12 +10822,12 @@ circuit lsu :
     wire _T_1487 : UInt<32> @[Mux.scala 27:72]
     _T_1487 <= _T_1486 @[Mux.scala 27:72]
     node _T_1488 = cat(UInt<32>("h00"), _T_1487) @[Cat.scala 29:58]
-    node _T_1489 = mux(_T_1462, _T_1475, _T_1488) @[lsu_bus_buffer.scala 334:8]
-    node obuf_data0_in = mux(ibuf_buf_byp, _T_1448, _T_1489) @[lsu_bus_buffer.scala 333:26]
-    node _T_1490 = bits(io.end_addr_r, 2, 2) @[lsu_bus_buffer.scala 335:58]
+    node _T_1489 = mux(_T_1462, _T_1475, _T_1488) @[lsu_bus_buffer.scala 335:8]
+    node obuf_data0_in = mux(ibuf_buf_byp, _T_1448, _T_1489) @[lsu_bus_buffer.scala 334:26]
+    node _T_1490 = bits(io.end_addr_r, 2, 2) @[lsu_bus_buffer.scala 336:58]
     node _T_1491 = cat(store_data_hi_r, UInt<32>("h00")) @[Cat.scala 29:58]
     node _T_1492 = cat(UInt<32>("h00"), store_data_hi_r) @[Cat.scala 29:58]
-    node _T_1493 = mux(_T_1490, _T_1491, _T_1492) @[lsu_bus_buffer.scala 335:44]
+    node _T_1493 = mux(_T_1490, _T_1491, _T_1492) @[lsu_bus_buffer.scala 336:44]
     node _T_1494 = eq(CmdPtr1, UInt<1>("h00")) @[lsu_bus_buffer.scala 61:123]
     node _T_1495 = eq(CmdPtr1, UInt<1>("h01")) @[lsu_bus_buffer.scala 61:123]
     node _T_1496 = eq(CmdPtr1, UInt<2>("h02")) @[lsu_bus_buffer.scala 61:123]
@@ -10657,8 +10841,8 @@ circuit lsu :
     node _T_1504 = or(_T_1503, _T_1501) @[Mux.scala 27:72]
     wire _T_1505 : UInt<32> @[Mux.scala 27:72]
     _T_1505 <= _T_1504 @[Mux.scala 27:72]
-    node _T_1506 = bits(_T_1505, 2, 2) @[lsu_bus_buffer.scala 336:36]
-    node _T_1507 = bits(_T_1506, 0, 0) @[lsu_bus_buffer.scala 336:46]
+    node _T_1506 = bits(_T_1505, 2, 2) @[lsu_bus_buffer.scala 337:36]
+    node _T_1507 = bits(_T_1506, 0, 0) @[lsu_bus_buffer.scala 337:46]
     node _T_1508 = eq(CmdPtr1, UInt<1>("h00")) @[lsu_bus_buffer.scala 61:123]
     node _T_1509 = eq(CmdPtr1, UInt<1>("h01")) @[lsu_bus_buffer.scala 61:123]
     node _T_1510 = eq(CmdPtr1, UInt<2>("h02")) @[lsu_bus_buffer.scala 61:123]
@@ -10687,40 +10871,40 @@ circuit lsu :
     wire _T_1532 : UInt<32> @[Mux.scala 27:72]
     _T_1532 <= _T_1531 @[Mux.scala 27:72]
     node _T_1533 = cat(UInt<32>("h00"), _T_1532) @[Cat.scala 29:58]
-    node _T_1534 = mux(_T_1507, _T_1520, _T_1533) @[lsu_bus_buffer.scala 336:8]
-    node obuf_data1_in = mux(ibuf_buf_byp, _T_1493, _T_1534) @[lsu_bus_buffer.scala 335:26]
-    node _T_1535 = bits(obuf_byteen0_in, 0, 0) @[lsu_bus_buffer.scala 337:59]
-    node _T_1536 = bits(obuf_byteen1_in, 0, 0) @[lsu_bus_buffer.scala 337:97]
-    node _T_1537 = and(obuf_merge_en, _T_1536) @[lsu_bus_buffer.scala 337:80]
-    node _T_1538 = or(_T_1535, _T_1537) @[lsu_bus_buffer.scala 337:63]
-    node _T_1539 = bits(obuf_byteen0_in, 1, 1) @[lsu_bus_buffer.scala 337:59]
-    node _T_1540 = bits(obuf_byteen1_in, 1, 1) @[lsu_bus_buffer.scala 337:97]
-    node _T_1541 = and(obuf_merge_en, _T_1540) @[lsu_bus_buffer.scala 337:80]
-    node _T_1542 = or(_T_1539, _T_1541) @[lsu_bus_buffer.scala 337:63]
-    node _T_1543 = bits(obuf_byteen0_in, 2, 2) @[lsu_bus_buffer.scala 337:59]
-    node _T_1544 = bits(obuf_byteen1_in, 2, 2) @[lsu_bus_buffer.scala 337:97]
-    node _T_1545 = and(obuf_merge_en, _T_1544) @[lsu_bus_buffer.scala 337:80]
-    node _T_1546 = or(_T_1543, _T_1545) @[lsu_bus_buffer.scala 337:63]
-    node _T_1547 = bits(obuf_byteen0_in, 3, 3) @[lsu_bus_buffer.scala 337:59]
-    node _T_1548 = bits(obuf_byteen1_in, 3, 3) @[lsu_bus_buffer.scala 337:97]
-    node _T_1549 = and(obuf_merge_en, _T_1548) @[lsu_bus_buffer.scala 337:80]
-    node _T_1550 = or(_T_1547, _T_1549) @[lsu_bus_buffer.scala 337:63]
-    node _T_1551 = bits(obuf_byteen0_in, 4, 4) @[lsu_bus_buffer.scala 337:59]
-    node _T_1552 = bits(obuf_byteen1_in, 4, 4) @[lsu_bus_buffer.scala 337:97]
-    node _T_1553 = and(obuf_merge_en, _T_1552) @[lsu_bus_buffer.scala 337:80]
-    node _T_1554 = or(_T_1551, _T_1553) @[lsu_bus_buffer.scala 337:63]
-    node _T_1555 = bits(obuf_byteen0_in, 5, 5) @[lsu_bus_buffer.scala 337:59]
-    node _T_1556 = bits(obuf_byteen1_in, 5, 5) @[lsu_bus_buffer.scala 337:97]
-    node _T_1557 = and(obuf_merge_en, _T_1556) @[lsu_bus_buffer.scala 337:80]
-    node _T_1558 = or(_T_1555, _T_1557) @[lsu_bus_buffer.scala 337:63]
-    node _T_1559 = bits(obuf_byteen0_in, 6, 6) @[lsu_bus_buffer.scala 337:59]
-    node _T_1560 = bits(obuf_byteen1_in, 6, 6) @[lsu_bus_buffer.scala 337:97]
-    node _T_1561 = and(obuf_merge_en, _T_1560) @[lsu_bus_buffer.scala 337:80]
-    node _T_1562 = or(_T_1559, _T_1561) @[lsu_bus_buffer.scala 337:63]
-    node _T_1563 = bits(obuf_byteen0_in, 7, 7) @[lsu_bus_buffer.scala 337:59]
-    node _T_1564 = bits(obuf_byteen1_in, 7, 7) @[lsu_bus_buffer.scala 337:97]
-    node _T_1565 = and(obuf_merge_en, _T_1564) @[lsu_bus_buffer.scala 337:80]
-    node _T_1566 = or(_T_1563, _T_1565) @[lsu_bus_buffer.scala 337:63]
+    node _T_1534 = mux(_T_1507, _T_1520, _T_1533) @[lsu_bus_buffer.scala 337:8]
+    node obuf_data1_in = mux(ibuf_buf_byp, _T_1493, _T_1534) @[lsu_bus_buffer.scala 336:26]
+    node _T_1535 = bits(obuf_byteen0_in, 0, 0) @[lsu_bus_buffer.scala 338:59]
+    node _T_1536 = bits(obuf_byteen1_in, 0, 0) @[lsu_bus_buffer.scala 338:97]
+    node _T_1537 = and(obuf_merge_en, _T_1536) @[lsu_bus_buffer.scala 338:80]
+    node _T_1538 = or(_T_1535, _T_1537) @[lsu_bus_buffer.scala 338:63]
+    node _T_1539 = bits(obuf_byteen0_in, 1, 1) @[lsu_bus_buffer.scala 338:59]
+    node _T_1540 = bits(obuf_byteen1_in, 1, 1) @[lsu_bus_buffer.scala 338:97]
+    node _T_1541 = and(obuf_merge_en, _T_1540) @[lsu_bus_buffer.scala 338:80]
+    node _T_1542 = or(_T_1539, _T_1541) @[lsu_bus_buffer.scala 338:63]
+    node _T_1543 = bits(obuf_byteen0_in, 2, 2) @[lsu_bus_buffer.scala 338:59]
+    node _T_1544 = bits(obuf_byteen1_in, 2, 2) @[lsu_bus_buffer.scala 338:97]
+    node _T_1545 = and(obuf_merge_en, _T_1544) @[lsu_bus_buffer.scala 338:80]
+    node _T_1546 = or(_T_1543, _T_1545) @[lsu_bus_buffer.scala 338:63]
+    node _T_1547 = bits(obuf_byteen0_in, 3, 3) @[lsu_bus_buffer.scala 338:59]
+    node _T_1548 = bits(obuf_byteen1_in, 3, 3) @[lsu_bus_buffer.scala 338:97]
+    node _T_1549 = and(obuf_merge_en, _T_1548) @[lsu_bus_buffer.scala 338:80]
+    node _T_1550 = or(_T_1547, _T_1549) @[lsu_bus_buffer.scala 338:63]
+    node _T_1551 = bits(obuf_byteen0_in, 4, 4) @[lsu_bus_buffer.scala 338:59]
+    node _T_1552 = bits(obuf_byteen1_in, 4, 4) @[lsu_bus_buffer.scala 338:97]
+    node _T_1553 = and(obuf_merge_en, _T_1552) @[lsu_bus_buffer.scala 338:80]
+    node _T_1554 = or(_T_1551, _T_1553) @[lsu_bus_buffer.scala 338:63]
+    node _T_1555 = bits(obuf_byteen0_in, 5, 5) @[lsu_bus_buffer.scala 338:59]
+    node _T_1556 = bits(obuf_byteen1_in, 5, 5) @[lsu_bus_buffer.scala 338:97]
+    node _T_1557 = and(obuf_merge_en, _T_1556) @[lsu_bus_buffer.scala 338:80]
+    node _T_1558 = or(_T_1555, _T_1557) @[lsu_bus_buffer.scala 338:63]
+    node _T_1559 = bits(obuf_byteen0_in, 6, 6) @[lsu_bus_buffer.scala 338:59]
+    node _T_1560 = bits(obuf_byteen1_in, 6, 6) @[lsu_bus_buffer.scala 338:97]
+    node _T_1561 = and(obuf_merge_en, _T_1560) @[lsu_bus_buffer.scala 338:80]
+    node _T_1562 = or(_T_1559, _T_1561) @[lsu_bus_buffer.scala 338:63]
+    node _T_1563 = bits(obuf_byteen0_in, 7, 7) @[lsu_bus_buffer.scala 338:59]
+    node _T_1564 = bits(obuf_byteen1_in, 7, 7) @[lsu_bus_buffer.scala 338:97]
+    node _T_1565 = and(obuf_merge_en, _T_1564) @[lsu_bus_buffer.scala 338:80]
+    node _T_1566 = or(_T_1563, _T_1565) @[lsu_bus_buffer.scala 338:63]
     node _T_1567 = cat(_T_1566, _T_1562) @[Cat.scala 29:58]
     node _T_1568 = cat(_T_1567, _T_1558) @[Cat.scala 29:58]
     node _T_1569 = cat(_T_1568, _T_1554) @[Cat.scala 29:58]
@@ -10728,46 +10912,46 @@ circuit lsu :
     node _T_1571 = cat(_T_1570, _T_1546) @[Cat.scala 29:58]
     node _T_1572 = cat(_T_1571, _T_1542) @[Cat.scala 29:58]
     node obuf_byteen_in = cat(_T_1572, _T_1538) @[Cat.scala 29:58]
-    node _T_1573 = bits(obuf_byteen1_in, 0, 0) @[lsu_bus_buffer.scala 338:76]
-    node _T_1574 = and(obuf_merge_en, _T_1573) @[lsu_bus_buffer.scala 338:59]
-    node _T_1575 = bits(obuf_data1_in, 7, 0) @[lsu_bus_buffer.scala 338:94]
-    node _T_1576 = bits(obuf_data0_in, 7, 0) @[lsu_bus_buffer.scala 338:123]
-    node _T_1577 = mux(_T_1574, _T_1575, _T_1576) @[lsu_bus_buffer.scala 338:44]
-    node _T_1578 = bits(obuf_byteen1_in, 1, 1) @[lsu_bus_buffer.scala 338:76]
-    node _T_1579 = and(obuf_merge_en, _T_1578) @[lsu_bus_buffer.scala 338:59]
-    node _T_1580 = bits(obuf_data1_in, 15, 8) @[lsu_bus_buffer.scala 338:94]
-    node _T_1581 = bits(obuf_data0_in, 15, 8) @[lsu_bus_buffer.scala 338:123]
-    node _T_1582 = mux(_T_1579, _T_1580, _T_1581) @[lsu_bus_buffer.scala 338:44]
-    node _T_1583 = bits(obuf_byteen1_in, 2, 2) @[lsu_bus_buffer.scala 338:76]
-    node _T_1584 = and(obuf_merge_en, _T_1583) @[lsu_bus_buffer.scala 338:59]
-    node _T_1585 = bits(obuf_data1_in, 23, 16) @[lsu_bus_buffer.scala 338:94]
-    node _T_1586 = bits(obuf_data0_in, 23, 16) @[lsu_bus_buffer.scala 338:123]
-    node _T_1587 = mux(_T_1584, _T_1585, _T_1586) @[lsu_bus_buffer.scala 338:44]
-    node _T_1588 = bits(obuf_byteen1_in, 3, 3) @[lsu_bus_buffer.scala 338:76]
-    node _T_1589 = and(obuf_merge_en, _T_1588) @[lsu_bus_buffer.scala 338:59]
-    node _T_1590 = bits(obuf_data1_in, 31, 24) @[lsu_bus_buffer.scala 338:94]
-    node _T_1591 = bits(obuf_data0_in, 31, 24) @[lsu_bus_buffer.scala 338:123]
-    node _T_1592 = mux(_T_1589, _T_1590, _T_1591) @[lsu_bus_buffer.scala 338:44]
-    node _T_1593 = bits(obuf_byteen1_in, 4, 4) @[lsu_bus_buffer.scala 338:76]
-    node _T_1594 = and(obuf_merge_en, _T_1593) @[lsu_bus_buffer.scala 338:59]
-    node _T_1595 = bits(obuf_data1_in, 39, 32) @[lsu_bus_buffer.scala 338:94]
-    node _T_1596 = bits(obuf_data0_in, 39, 32) @[lsu_bus_buffer.scala 338:123]
-    node _T_1597 = mux(_T_1594, _T_1595, _T_1596) @[lsu_bus_buffer.scala 338:44]
-    node _T_1598 = bits(obuf_byteen1_in, 5, 5) @[lsu_bus_buffer.scala 338:76]
-    node _T_1599 = and(obuf_merge_en, _T_1598) @[lsu_bus_buffer.scala 338:59]
-    node _T_1600 = bits(obuf_data1_in, 47, 40) @[lsu_bus_buffer.scala 338:94]
-    node _T_1601 = bits(obuf_data0_in, 47, 40) @[lsu_bus_buffer.scala 338:123]
-    node _T_1602 = mux(_T_1599, _T_1600, _T_1601) @[lsu_bus_buffer.scala 338:44]
-    node _T_1603 = bits(obuf_byteen1_in, 6, 6) @[lsu_bus_buffer.scala 338:76]
-    node _T_1604 = and(obuf_merge_en, _T_1603) @[lsu_bus_buffer.scala 338:59]
-    node _T_1605 = bits(obuf_data1_in, 55, 48) @[lsu_bus_buffer.scala 338:94]
-    node _T_1606 = bits(obuf_data0_in, 55, 48) @[lsu_bus_buffer.scala 338:123]
-    node _T_1607 = mux(_T_1604, _T_1605, _T_1606) @[lsu_bus_buffer.scala 338:44]
-    node _T_1608 = bits(obuf_byteen1_in, 7, 7) @[lsu_bus_buffer.scala 338:76]
-    node _T_1609 = and(obuf_merge_en, _T_1608) @[lsu_bus_buffer.scala 338:59]
-    node _T_1610 = bits(obuf_data1_in, 63, 56) @[lsu_bus_buffer.scala 338:94]
-    node _T_1611 = bits(obuf_data0_in, 63, 56) @[lsu_bus_buffer.scala 338:123]
-    node _T_1612 = mux(_T_1609, _T_1610, _T_1611) @[lsu_bus_buffer.scala 338:44]
+    node _T_1573 = bits(obuf_byteen1_in, 0, 0) @[lsu_bus_buffer.scala 339:76]
+    node _T_1574 = and(obuf_merge_en, _T_1573) @[lsu_bus_buffer.scala 339:59]
+    node _T_1575 = bits(obuf_data1_in, 7, 0) @[lsu_bus_buffer.scala 339:94]
+    node _T_1576 = bits(obuf_data0_in, 7, 0) @[lsu_bus_buffer.scala 339:123]
+    node _T_1577 = mux(_T_1574, _T_1575, _T_1576) @[lsu_bus_buffer.scala 339:44]
+    node _T_1578 = bits(obuf_byteen1_in, 1, 1) @[lsu_bus_buffer.scala 339:76]
+    node _T_1579 = and(obuf_merge_en, _T_1578) @[lsu_bus_buffer.scala 339:59]
+    node _T_1580 = bits(obuf_data1_in, 15, 8) @[lsu_bus_buffer.scala 339:94]
+    node _T_1581 = bits(obuf_data0_in, 15, 8) @[lsu_bus_buffer.scala 339:123]
+    node _T_1582 = mux(_T_1579, _T_1580, _T_1581) @[lsu_bus_buffer.scala 339:44]
+    node _T_1583 = bits(obuf_byteen1_in, 2, 2) @[lsu_bus_buffer.scala 339:76]
+    node _T_1584 = and(obuf_merge_en, _T_1583) @[lsu_bus_buffer.scala 339:59]
+    node _T_1585 = bits(obuf_data1_in, 23, 16) @[lsu_bus_buffer.scala 339:94]
+    node _T_1586 = bits(obuf_data0_in, 23, 16) @[lsu_bus_buffer.scala 339:123]
+    node _T_1587 = mux(_T_1584, _T_1585, _T_1586) @[lsu_bus_buffer.scala 339:44]
+    node _T_1588 = bits(obuf_byteen1_in, 3, 3) @[lsu_bus_buffer.scala 339:76]
+    node _T_1589 = and(obuf_merge_en, _T_1588) @[lsu_bus_buffer.scala 339:59]
+    node _T_1590 = bits(obuf_data1_in, 31, 24) @[lsu_bus_buffer.scala 339:94]
+    node _T_1591 = bits(obuf_data0_in, 31, 24) @[lsu_bus_buffer.scala 339:123]
+    node _T_1592 = mux(_T_1589, _T_1590, _T_1591) @[lsu_bus_buffer.scala 339:44]
+    node _T_1593 = bits(obuf_byteen1_in, 4, 4) @[lsu_bus_buffer.scala 339:76]
+    node _T_1594 = and(obuf_merge_en, _T_1593) @[lsu_bus_buffer.scala 339:59]
+    node _T_1595 = bits(obuf_data1_in, 39, 32) @[lsu_bus_buffer.scala 339:94]
+    node _T_1596 = bits(obuf_data0_in, 39, 32) @[lsu_bus_buffer.scala 339:123]
+    node _T_1597 = mux(_T_1594, _T_1595, _T_1596) @[lsu_bus_buffer.scala 339:44]
+    node _T_1598 = bits(obuf_byteen1_in, 5, 5) @[lsu_bus_buffer.scala 339:76]
+    node _T_1599 = and(obuf_merge_en, _T_1598) @[lsu_bus_buffer.scala 339:59]
+    node _T_1600 = bits(obuf_data1_in, 47, 40) @[lsu_bus_buffer.scala 339:94]
+    node _T_1601 = bits(obuf_data0_in, 47, 40) @[lsu_bus_buffer.scala 339:123]
+    node _T_1602 = mux(_T_1599, _T_1600, _T_1601) @[lsu_bus_buffer.scala 339:44]
+    node _T_1603 = bits(obuf_byteen1_in, 6, 6) @[lsu_bus_buffer.scala 339:76]
+    node _T_1604 = and(obuf_merge_en, _T_1603) @[lsu_bus_buffer.scala 339:59]
+    node _T_1605 = bits(obuf_data1_in, 55, 48) @[lsu_bus_buffer.scala 339:94]
+    node _T_1606 = bits(obuf_data0_in, 55, 48) @[lsu_bus_buffer.scala 339:123]
+    node _T_1607 = mux(_T_1604, _T_1605, _T_1606) @[lsu_bus_buffer.scala 339:44]
+    node _T_1608 = bits(obuf_byteen1_in, 7, 7) @[lsu_bus_buffer.scala 339:76]
+    node _T_1609 = and(obuf_merge_en, _T_1608) @[lsu_bus_buffer.scala 339:59]
+    node _T_1610 = bits(obuf_data1_in, 63, 56) @[lsu_bus_buffer.scala 339:94]
+    node _T_1611 = bits(obuf_data0_in, 63, 56) @[lsu_bus_buffer.scala 339:123]
+    node _T_1612 = mux(_T_1609, _T_1610, _T_1611) @[lsu_bus_buffer.scala 339:44]
     node _T_1613 = cat(_T_1612, _T_1607) @[Cat.scala 29:58]
     node _T_1614 = cat(_T_1613, _T_1602) @[Cat.scala 29:58]
     node _T_1615 = cat(_T_1614, _T_1597) @[Cat.scala 29:58]
@@ -10775,14 +10959,14 @@ circuit lsu :
     node _T_1617 = cat(_T_1616, _T_1587) @[Cat.scala 29:58]
     node _T_1618 = cat(_T_1617, _T_1582) @[Cat.scala 29:58]
     node obuf_data_in = cat(_T_1618, _T_1577) @[Cat.scala 29:58]
-    wire buf_dualhi : UInt<1>[4] @[lsu_bus_buffer.scala 340:24]
-    buf_dualhi[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 341:14]
-    buf_dualhi[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 341:14]
-    buf_dualhi[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 341:14]
-    buf_dualhi[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 341:14]
-    node _T_1619 = neq(CmdPtr0, CmdPtr1) @[lsu_bus_buffer.scala 342:30]
-    node _T_1620 = and(_T_1619, found_cmdptr0) @[lsu_bus_buffer.scala 342:43]
-    node _T_1621 = and(_T_1620, found_cmdptr1) @[lsu_bus_buffer.scala 342:59]
+    wire buf_dualhi : UInt<1>[4] @[lsu_bus_buffer.scala 341:24]
+    buf_dualhi[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 342:14]
+    buf_dualhi[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 342:14]
+    buf_dualhi[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 342:14]
+    buf_dualhi[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 342:14]
+    node _T_1619 = neq(CmdPtr0, CmdPtr1) @[lsu_bus_buffer.scala 343:30]
+    node _T_1620 = and(_T_1619, found_cmdptr0) @[lsu_bus_buffer.scala 343:43]
+    node _T_1621 = and(_T_1620, found_cmdptr1) @[lsu_bus_buffer.scala 343:59]
     node _T_1622 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 61:123]
     node _T_1623 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 61:123]
     node _T_1624 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 61:123]
@@ -10796,8 +10980,8 @@ circuit lsu :
     node _T_1632 = or(_T_1631, _T_1629) @[Mux.scala 27:72]
     wire _T_1633 : UInt<3> @[Mux.scala 27:72]
     _T_1633 <= _T_1632 @[Mux.scala 27:72]
-    node _T_1634 = eq(_T_1633, UInt<3>("h02")) @[lsu_bus_buffer.scala 342:107]
-    node _T_1635 = and(_T_1621, _T_1634) @[lsu_bus_buffer.scala 342:75]
+    node _T_1634 = eq(_T_1633, UInt<3>("h02")) @[lsu_bus_buffer.scala 343:107]
+    node _T_1635 = and(_T_1621, _T_1634) @[lsu_bus_buffer.scala 343:75]
     node _T_1636 = eq(CmdPtr1, UInt<1>("h00")) @[lsu_bus_buffer.scala 61:123]
     node _T_1637 = eq(CmdPtr1, UInt<1>("h01")) @[lsu_bus_buffer.scala 61:123]
     node _T_1638 = eq(CmdPtr1, UInt<2>("h02")) @[lsu_bus_buffer.scala 61:123]
@@ -10811,8 +10995,8 @@ circuit lsu :
     node _T_1646 = or(_T_1645, _T_1643) @[Mux.scala 27:72]
     wire _T_1647 : UInt<3> @[Mux.scala 27:72]
     _T_1647 <= _T_1646 @[Mux.scala 27:72]
-    node _T_1648 = eq(_T_1647, UInt<3>("h02")) @[lsu_bus_buffer.scala 342:150]
-    node _T_1649 = and(_T_1635, _T_1648) @[lsu_bus_buffer.scala 342:118]
+    node _T_1648 = eq(_T_1647, UInt<3>("h02")) @[lsu_bus_buffer.scala 343:150]
+    node _T_1649 = and(_T_1635, _T_1648) @[lsu_bus_buffer.scala 343:118]
     node _T_1650 = cat(buf_cmd_state_bus_en[3], buf_cmd_state_bus_en[2]) @[Cat.scala 29:58]
     node _T_1651 = cat(_T_1650, buf_cmd_state_bus_en[1]) @[Cat.scala 29:58]
     node _T_1652 = cat(_T_1651, buf_cmd_state_bus_en[0]) @[Cat.scala 29:58]
@@ -10833,8 +11017,8 @@ circuit lsu :
     node _T_1667 = or(_T_1666, _T_1664) @[Mux.scala 27:72]
     wire _T_1668 : UInt<1> @[Mux.scala 27:72]
     _T_1668 <= _T_1667 @[Mux.scala 27:72]
-    node _T_1669 = eq(_T_1668, UInt<1>("h00")) @[lsu_bus_buffer.scala 343:5]
-    node _T_1670 = and(_T_1649, _T_1669) @[lsu_bus_buffer.scala 342:161]
+    node _T_1669 = eq(_T_1668, UInt<1>("h00")) @[lsu_bus_buffer.scala 344:5]
+    node _T_1670 = and(_T_1649, _T_1669) @[lsu_bus_buffer.scala 343:161]
     node _T_1671 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 60:118]
     node _T_1672 = bits(buf_sideeffect, 0, 0) @[lsu_bus_buffer.scala 60:129]
     node _T_1673 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 60:118]
@@ -10852,8 +11036,8 @@ circuit lsu :
     node _T_1685 = or(_T_1684, _T_1682) @[Mux.scala 27:72]
     wire _T_1686 : UInt<1> @[Mux.scala 27:72]
     _T_1686 <= _T_1685 @[Mux.scala 27:72]
-    node _T_1687 = eq(_T_1686, UInt<1>("h00")) @[lsu_bus_buffer.scala 343:87]
-    node _T_1688 = and(_T_1670, _T_1687) @[lsu_bus_buffer.scala 343:85]
+    node _T_1687 = eq(_T_1686, UInt<1>("h00")) @[lsu_bus_buffer.scala 344:87]
+    node _T_1688 = and(_T_1670, _T_1687) @[lsu_bus_buffer.scala 344:85]
     node _T_1689 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 60:118]
     node _T_1690 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 60:129]
     node _T_1691 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 60:118]
@@ -10871,7 +11055,7 @@ circuit lsu :
     node _T_1703 = or(_T_1702, _T_1700) @[Mux.scala 27:72]
     wire _T_1704 : UInt<1> @[Mux.scala 27:72]
     _T_1704 <= _T_1703 @[Mux.scala 27:72]
-    node _T_1705 = eq(_T_1704, UInt<1>("h00")) @[lsu_bus_buffer.scala 344:6]
+    node _T_1705 = eq(_T_1704, UInt<1>("h00")) @[lsu_bus_buffer.scala 345:6]
     node _T_1706 = cat(buf_dual[3], buf_dual[2]) @[Cat.scala 29:58]
     node _T_1707 = cat(_T_1706, buf_dual[1]) @[Cat.scala 29:58]
     node _T_1708 = cat(_T_1707, buf_dual[0]) @[Cat.scala 29:58]
@@ -10892,7 +11076,7 @@ circuit lsu :
     node _T_1723 = or(_T_1722, _T_1720) @[Mux.scala 27:72]
     wire _T_1724 : UInt<1> @[Mux.scala 27:72]
     _T_1724 <= _T_1723 @[Mux.scala 27:72]
-    node _T_1725 = and(_T_1705, _T_1724) @[lsu_bus_buffer.scala 344:36]
+    node _T_1725 = and(_T_1705, _T_1724) @[lsu_bus_buffer.scala 345:36]
     node _T_1726 = cat(buf_dualhi[3], buf_dualhi[2]) @[Cat.scala 29:58]
     node _T_1727 = cat(_T_1726, buf_dualhi[1]) @[Cat.scala 29:58]
     node _T_1728 = cat(_T_1727, buf_dualhi[0]) @[Cat.scala 29:58]
@@ -10913,8 +11097,8 @@ circuit lsu :
     node _T_1743 = or(_T_1742, _T_1740) @[Mux.scala 27:72]
     wire _T_1744 : UInt<1> @[Mux.scala 27:72]
     _T_1744 <= _T_1743 @[Mux.scala 27:72]
-    node _T_1745 = eq(_T_1744, UInt<1>("h00")) @[lsu_bus_buffer.scala 344:107]
-    node _T_1746 = and(_T_1725, _T_1745) @[lsu_bus_buffer.scala 344:105]
+    node _T_1745 = eq(_T_1744, UInt<1>("h00")) @[lsu_bus_buffer.scala 345:107]
+    node _T_1746 = and(_T_1725, _T_1745) @[lsu_bus_buffer.scala 345:105]
     node _T_1747 = cat(buf_samedw[3], buf_samedw[2]) @[Cat.scala 29:58]
     node _T_1748 = cat(_T_1747, buf_samedw[1]) @[Cat.scala 29:58]
     node _T_1749 = cat(_T_1748, buf_samedw[0]) @[Cat.scala 29:58]
@@ -10935,14 +11119,16 @@ circuit lsu :
     node _T_1764 = or(_T_1763, _T_1761) @[Mux.scala 27:72]
     wire _T_1765 : UInt<1> @[Mux.scala 27:72]
     _T_1765 <= _T_1764 @[Mux.scala 27:72]
-    node _T_1766 = and(_T_1746, _T_1765) @[lsu_bus_buffer.scala 344:177]
-    node _T_1767 = and(_T_1688, _T_1766) @[lsu_bus_buffer.scala 343:122]
-    node _T_1768 = and(ibuf_buf_byp, ldst_samedw_r) @[lsu_bus_buffer.scala 345:19]
-    node _T_1769 = and(_T_1768, io.ldst_dual_r) @[lsu_bus_buffer.scala 345:35]
-    node _T_1770 = or(_T_1767, _T_1769) @[lsu_bus_buffer.scala 344:250]
-    obuf_merge_en <= _T_1770 @[lsu_bus_buffer.scala 342:17]
-    reg obuf_wr_enQ : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 347:55]
-    obuf_wr_enQ <= obuf_wr_en @[lsu_bus_buffer.scala 347:55]
+    node _T_1766 = and(_T_1746, _T_1765) @[lsu_bus_buffer.scala 345:177]
+    node _T_1767 = and(_T_1688, _T_1766) @[lsu_bus_buffer.scala 344:122]
+    node _T_1768 = and(ibuf_buf_byp, ldst_samedw_r) @[lsu_bus_buffer.scala 346:19]
+    node _T_1769 = and(_T_1768, io.ldst_dual_r) @[lsu_bus_buffer.scala 346:35]
+    node _T_1770 = or(_T_1767, _T_1769) @[lsu_bus_buffer.scala 345:250]
+    obuf_merge_en <= _T_1770 @[lsu_bus_buffer.scala 343:17]
+    reg obuf_wr_enQ : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when io.lsu_busm_clken : @[Reg.scala 28:19]
+      obuf_wr_enQ <= obuf_wr_en @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
     node _T_1771 = mux(obuf_wr_en, UInt<1>("h01"), obuf_valid) @[lsu_bus_buffer.scala 348:58]
     node _T_1772 = eq(obuf_rst, UInt<1>("h00")) @[lsu_bus_buffer.scala 348:93]
     node _T_1773 = and(_T_1771, _T_1772) @[lsu_bus_buffer.scala 348:91]
@@ -10954,3963 +11140,4028 @@ circuit lsu :
       _T_1775 <= obuf_nosend_in @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
     obuf_nosend <= _T_1775 @[lsu_bus_buffer.scala 349:15]
-    reg _T_1776 : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 350:54]
-    _T_1776 <= obuf_cmd_done_in @[lsu_bus_buffer.scala 350:54]
-    obuf_cmd_done <= _T_1776 @[lsu_bus_buffer.scala 350:17]
-    reg _T_1777 : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 351:55]
-    _T_1777 <= obuf_data_done_in @[lsu_bus_buffer.scala 351:55]
-    obuf_data_done <= _T_1777 @[lsu_bus_buffer.scala 351:18]
-    reg _T_1778 : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 352:56]
-    _T_1778 <= obuf_rdrsp_pend_in @[lsu_bus_buffer.scala 352:56]
-    obuf_rdrsp_pend <= _T_1778 @[lsu_bus_buffer.scala 352:19]
-    reg _T_1779 : UInt, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 353:55]
-    _T_1779 <= obuf_rdrsp_tag_in @[lsu_bus_buffer.scala 353:55]
-    obuf_rdrsp_tag <= _T_1779 @[lsu_bus_buffer.scala 353:18]
-    reg _T_1780 : UInt, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when obuf_wr_en : @[Reg.scala 28:19]
-      _T_1780 <= obuf_tag0_in @[Reg.scala 28:23]
+    reg _T_1776 : UInt<1>, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when obuf_rdrsp_pend_en : @[Reg.scala 28:19]
+      _T_1776 <= obuf_rdrsp_pend_in @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    obuf_tag0 <= _T_1780 @[lsu_bus_buffer.scala 354:13]
-    reg obuf_tag1 : UInt, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when obuf_wr_en : @[Reg.scala 28:19]
+    obuf_rdrsp_pend <= _T_1776 @[lsu_bus_buffer.scala 350:19]
+    reg _T_1777 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when io.lsu_busm_clken : @[Reg.scala 28:19]
+      _T_1777 <= obuf_cmd_done_in @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    obuf_cmd_done <= _T_1777 @[lsu_bus_buffer.scala 351:17]
+    reg _T_1778 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when io.lsu_busm_clken : @[Reg.scala 28:19]
+      _T_1778 <= obuf_data_done_in @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    obuf_data_done <= _T_1778 @[lsu_bus_buffer.scala 352:18]
+    reg _T_1779 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when io.lsu_busm_clken : @[Reg.scala 28:19]
+      _T_1779 <= obuf_rdrsp_tag_in @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    obuf_rdrsp_tag <= _T_1779 @[lsu_bus_buffer.scala 353:18]
+    node _T_1780 = and(io.lsu_bus_obuf_c1_clken, obuf_wr_en) @[lib.scala 383:57]
+    reg _T_1781 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_1780 : @[Reg.scala 28:19]
+      _T_1781 <= obuf_tag0_in @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    obuf_tag0 <= _T_1781 @[lsu_bus_buffer.scala 355:13]
+    node _T_1782 = and(io.lsu_bus_obuf_c1_clken, obuf_wr_en) @[lib.scala 383:57]
+    reg obuf_tag1 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_1782 : @[Reg.scala 28:19]
       obuf_tag1 <= obuf_tag1_in @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    reg obuf_merge : UInt<1>, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when obuf_wr_en : @[Reg.scala 28:19]
+    node _T_1783 = and(io.lsu_bus_obuf_c1_clken, obuf_wr_en) @[lib.scala 383:57]
+    reg obuf_merge : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_1783 : @[Reg.scala 28:19]
       obuf_merge <= obuf_merge_en @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    reg _T_1781 : UInt<1>, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when obuf_wr_en : @[Reg.scala 28:19]
-      _T_1781 <= obuf_write_in @[Reg.scala 28:23]
+    node _T_1784 = and(io.lsu_bus_obuf_c1_clken, obuf_wr_en) @[lib.scala 383:57]
+    reg _T_1785 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_1784 : @[Reg.scala 28:19]
+      _T_1785 <= obuf_write_in @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    obuf_write <= _T_1781 @[lsu_bus_buffer.scala 357:14]
-    reg _T_1782 : UInt<1>, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when obuf_wr_en : @[Reg.scala 28:19]
-      _T_1782 <= obuf_sideeffect_in @[Reg.scala 28:23]
+    obuf_write <= _T_1785 @[lsu_bus_buffer.scala 358:14]
+    node _T_1786 = and(io.lsu_bus_obuf_c1_clken, obuf_wr_en) @[lib.scala 383:57]
+    reg _T_1787 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_1786 : @[Reg.scala 28:19]
+      _T_1787 <= obuf_sideeffect_in @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    obuf_sideeffect <= _T_1782 @[lsu_bus_buffer.scala 358:19]
-    reg obuf_sz : UInt, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when obuf_wr_en : @[Reg.scala 28:19]
+    obuf_sideeffect <= _T_1787 @[lsu_bus_buffer.scala 359:19]
+    node _T_1788 = and(io.lsu_bus_obuf_c1_clken, obuf_wr_en) @[lib.scala 383:57]
+    reg obuf_sz : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_1788 : @[Reg.scala 28:19]
       obuf_sz <= obuf_sz_in @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    inst rvclkhdr_2 of rvclkhdr_34 @[lib.scala 368:23]
-    rvclkhdr_2.clock <= clock
-    rvclkhdr_2.reset <= reset
-    rvclkhdr_2.io.clk <= clock @[lib.scala 370:18]
-    rvclkhdr_2.io.en <= obuf_wr_en @[lib.scala 371:17]
-    rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
-    reg _T_1783 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
-    _T_1783 <= obuf_addr_in @[lib.scala 374:16]
-    obuf_addr <= _T_1783 @[lsu_bus_buffer.scala 360:13]
-    reg obuf_byteen : UInt, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when obuf_wr_en : @[Reg.scala 28:19]
+    node _T_1789 = and(io.lsu_bus_obuf_c1_clken, obuf_wr_en) @[lib.scala 383:57]
+    reg obuf_byteen : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_1789 : @[Reg.scala 28:19]
       obuf_byteen <= obuf_byteen_in @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    inst rvclkhdr_3 of rvclkhdr_35 @[lib.scala 368:23]
+    inst rvclkhdr_2 of rvclkhdr_39 @[lib.scala 390:23]
+    rvclkhdr_2.clock <= clock
+    rvclkhdr_2.reset <= reset
+    rvclkhdr_2.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr_2.io.en <= obuf_wr_en @[lib.scala 393:17]
+    rvclkhdr_2.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg _T_1790 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when obuf_wr_en : @[Reg.scala 28:19]
+      _T_1790 <= obuf_addr_in @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    obuf_addr <= _T_1790 @[lsu_bus_buffer.scala 362:13]
+    inst rvclkhdr_3 of rvclkhdr_40 @[lib.scala 390:23]
     rvclkhdr_3.clock <= clock
     rvclkhdr_3.reset <= reset
-    rvclkhdr_3.io.clk <= clock @[lib.scala 370:18]
-    rvclkhdr_3.io.en <= obuf_wr_en @[lib.scala 371:17]
-    rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
-    reg obuf_data : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
-    obuf_data <= obuf_data_in @[lib.scala 374:16]
-    reg _T_1784 : UInt, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 363:54]
-    _T_1784 <= obuf_wr_timer_in @[lsu_bus_buffer.scala 363:54]
-    obuf_wr_timer <= _T_1784 @[lsu_bus_buffer.scala 363:17]
+    rvclkhdr_3.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr_3.io.en <= obuf_wr_en @[lib.scala 393:17]
+    rvclkhdr_3.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg obuf_data : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when obuf_wr_en : @[Reg.scala 28:19]
+      obuf_data <= obuf_data_in @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    reg _T_1791 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when obuf_wr_en : @[Reg.scala 28:19]
+      _T_1791 <= obuf_data_done_in @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    obuf_wr_timer <= _T_1791 @[lsu_bus_buffer.scala 364:17]
     wire WrPtr0_m : UInt<2>
     WrPtr0_m <= UInt<1>("h00")
-    node _T_1785 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 366:65]
-    node _T_1786 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 367:30]
-    node _T_1787 = and(ibuf_valid, _T_1786) @[lsu_bus_buffer.scala 367:19]
-    node _T_1788 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 368:18]
-    node _T_1789 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 368:57]
-    node _T_1790 = and(io.ldst_dual_r, _T_1789) @[lsu_bus_buffer.scala 368:45]
-    node _T_1791 = or(_T_1788, _T_1790) @[lsu_bus_buffer.scala 368:27]
-    node _T_1792 = and(io.lsu_busreq_r, _T_1791) @[lsu_bus_buffer.scala 367:58]
-    node _T_1793 = or(_T_1787, _T_1792) @[lsu_bus_buffer.scala 367:39]
-    node _T_1794 = eq(_T_1793, UInt<1>("h00")) @[lsu_bus_buffer.scala 367:5]
-    node _T_1795 = and(_T_1785, _T_1794) @[lsu_bus_buffer.scala 366:76]
-    node _T_1796 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 366:65]
-    node _T_1797 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 367:30]
-    node _T_1798 = and(ibuf_valid, _T_1797) @[lsu_bus_buffer.scala 367:19]
-    node _T_1799 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 368:18]
-    node _T_1800 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 368:57]
-    node _T_1801 = and(io.ldst_dual_r, _T_1800) @[lsu_bus_buffer.scala 368:45]
-    node _T_1802 = or(_T_1799, _T_1801) @[lsu_bus_buffer.scala 368:27]
-    node _T_1803 = and(io.lsu_busreq_r, _T_1802) @[lsu_bus_buffer.scala 367:58]
-    node _T_1804 = or(_T_1798, _T_1803) @[lsu_bus_buffer.scala 367:39]
-    node _T_1805 = eq(_T_1804, UInt<1>("h00")) @[lsu_bus_buffer.scala 367:5]
-    node _T_1806 = and(_T_1796, _T_1805) @[lsu_bus_buffer.scala 366:76]
-    node _T_1807 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 366:65]
-    node _T_1808 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 367:30]
-    node _T_1809 = and(ibuf_valid, _T_1808) @[lsu_bus_buffer.scala 367:19]
-    node _T_1810 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 368:18]
-    node _T_1811 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 368:57]
-    node _T_1812 = and(io.ldst_dual_r, _T_1811) @[lsu_bus_buffer.scala 368:45]
-    node _T_1813 = or(_T_1810, _T_1812) @[lsu_bus_buffer.scala 368:27]
-    node _T_1814 = and(io.lsu_busreq_r, _T_1813) @[lsu_bus_buffer.scala 367:58]
-    node _T_1815 = or(_T_1809, _T_1814) @[lsu_bus_buffer.scala 367:39]
-    node _T_1816 = eq(_T_1815, UInt<1>("h00")) @[lsu_bus_buffer.scala 367:5]
-    node _T_1817 = and(_T_1807, _T_1816) @[lsu_bus_buffer.scala 366:76]
-    node _T_1818 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 366:65]
-    node _T_1819 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 367:30]
-    node _T_1820 = and(ibuf_valid, _T_1819) @[lsu_bus_buffer.scala 367:19]
-    node _T_1821 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 368:18]
-    node _T_1822 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 368:57]
-    node _T_1823 = and(io.ldst_dual_r, _T_1822) @[lsu_bus_buffer.scala 368:45]
-    node _T_1824 = or(_T_1821, _T_1823) @[lsu_bus_buffer.scala 368:27]
-    node _T_1825 = and(io.lsu_busreq_r, _T_1824) @[lsu_bus_buffer.scala 367:58]
-    node _T_1826 = or(_T_1820, _T_1825) @[lsu_bus_buffer.scala 367:39]
-    node _T_1827 = eq(_T_1826, UInt<1>("h00")) @[lsu_bus_buffer.scala 367:5]
-    node _T_1828 = and(_T_1818, _T_1827) @[lsu_bus_buffer.scala 366:76]
-    node _T_1829 = mux(_T_1828, UInt<2>("h03"), UInt<2>("h03")) @[Mux.scala 98:16]
-    node _T_1830 = mux(_T_1817, UInt<2>("h02"), _T_1829) @[Mux.scala 98:16]
-    node _T_1831 = mux(_T_1806, UInt<1>("h01"), _T_1830) @[Mux.scala 98:16]
-    node _T_1832 = mux(_T_1795, UInt<1>("h00"), _T_1831) @[Mux.scala 98:16]
-    WrPtr0_m <= _T_1832 @[lsu_bus_buffer.scala 366:12]
+    node _T_1792 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 367:65]
+    node _T_1793 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 368:30]
+    node _T_1794 = and(ibuf_valid, _T_1793) @[lsu_bus_buffer.scala 368:19]
+    node _T_1795 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 369:18]
+    node _T_1796 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 369:57]
+    node _T_1797 = and(io.ldst_dual_r, _T_1796) @[lsu_bus_buffer.scala 369:45]
+    node _T_1798 = or(_T_1795, _T_1797) @[lsu_bus_buffer.scala 369:27]
+    node _T_1799 = and(io.lsu_busreq_r, _T_1798) @[lsu_bus_buffer.scala 368:58]
+    node _T_1800 = or(_T_1794, _T_1799) @[lsu_bus_buffer.scala 368:39]
+    node _T_1801 = eq(_T_1800, UInt<1>("h00")) @[lsu_bus_buffer.scala 368:5]
+    node _T_1802 = and(_T_1792, _T_1801) @[lsu_bus_buffer.scala 367:76]
+    node _T_1803 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 367:65]
+    node _T_1804 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 368:30]
+    node _T_1805 = and(ibuf_valid, _T_1804) @[lsu_bus_buffer.scala 368:19]
+    node _T_1806 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 369:18]
+    node _T_1807 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 369:57]
+    node _T_1808 = and(io.ldst_dual_r, _T_1807) @[lsu_bus_buffer.scala 369:45]
+    node _T_1809 = or(_T_1806, _T_1808) @[lsu_bus_buffer.scala 369:27]
+    node _T_1810 = and(io.lsu_busreq_r, _T_1809) @[lsu_bus_buffer.scala 368:58]
+    node _T_1811 = or(_T_1805, _T_1810) @[lsu_bus_buffer.scala 368:39]
+    node _T_1812 = eq(_T_1811, UInt<1>("h00")) @[lsu_bus_buffer.scala 368:5]
+    node _T_1813 = and(_T_1803, _T_1812) @[lsu_bus_buffer.scala 367:76]
+    node _T_1814 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 367:65]
+    node _T_1815 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 368:30]
+    node _T_1816 = and(ibuf_valid, _T_1815) @[lsu_bus_buffer.scala 368:19]
+    node _T_1817 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 369:18]
+    node _T_1818 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 369:57]
+    node _T_1819 = and(io.ldst_dual_r, _T_1818) @[lsu_bus_buffer.scala 369:45]
+    node _T_1820 = or(_T_1817, _T_1819) @[lsu_bus_buffer.scala 369:27]
+    node _T_1821 = and(io.lsu_busreq_r, _T_1820) @[lsu_bus_buffer.scala 368:58]
+    node _T_1822 = or(_T_1816, _T_1821) @[lsu_bus_buffer.scala 368:39]
+    node _T_1823 = eq(_T_1822, UInt<1>("h00")) @[lsu_bus_buffer.scala 368:5]
+    node _T_1824 = and(_T_1814, _T_1823) @[lsu_bus_buffer.scala 367:76]
+    node _T_1825 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 367:65]
+    node _T_1826 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 368:30]
+    node _T_1827 = and(ibuf_valid, _T_1826) @[lsu_bus_buffer.scala 368:19]
+    node _T_1828 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 369:18]
+    node _T_1829 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 369:57]
+    node _T_1830 = and(io.ldst_dual_r, _T_1829) @[lsu_bus_buffer.scala 369:45]
+    node _T_1831 = or(_T_1828, _T_1830) @[lsu_bus_buffer.scala 369:27]
+    node _T_1832 = and(io.lsu_busreq_r, _T_1831) @[lsu_bus_buffer.scala 368:58]
+    node _T_1833 = or(_T_1827, _T_1832) @[lsu_bus_buffer.scala 368:39]
+    node _T_1834 = eq(_T_1833, UInt<1>("h00")) @[lsu_bus_buffer.scala 368:5]
+    node _T_1835 = and(_T_1825, _T_1834) @[lsu_bus_buffer.scala 367:76]
+    node _T_1836 = mux(_T_1835, UInt<2>("h03"), UInt<2>("h03")) @[Mux.scala 98:16]
+    node _T_1837 = mux(_T_1824, UInt<2>("h02"), _T_1836) @[Mux.scala 98:16]
+    node _T_1838 = mux(_T_1813, UInt<1>("h01"), _T_1837) @[Mux.scala 98:16]
+    node _T_1839 = mux(_T_1802, UInt<1>("h00"), _T_1838) @[Mux.scala 98:16]
+    WrPtr0_m <= _T_1839 @[lsu_bus_buffer.scala 367:12]
     wire WrPtr1_m : UInt<2>
     WrPtr1_m <= UInt<1>("h00")
-    node _T_1833 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 372:65]
-    node _T_1834 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 372:103]
-    node _T_1835 = and(ibuf_valid, _T_1834) @[lsu_bus_buffer.scala 372:92]
-    node _T_1836 = eq(WrPtr0_m, UInt<1>("h00")) @[lsu_bus_buffer.scala 373:33]
-    node _T_1837 = and(io.lsu_busreq_m, _T_1836) @[lsu_bus_buffer.scala 373:22]
-    node _T_1838 = or(_T_1835, _T_1837) @[lsu_bus_buffer.scala 372:112]
-    node _T_1839 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 374:36]
-    node _T_1840 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 375:34]
-    node _T_1841 = and(io.ldst_dual_r, _T_1840) @[lsu_bus_buffer.scala 375:23]
-    node _T_1842 = or(_T_1839, _T_1841) @[lsu_bus_buffer.scala 374:46]
-    node _T_1843 = and(io.lsu_busreq_r, _T_1842) @[lsu_bus_buffer.scala 374:22]
-    node _T_1844 = or(_T_1838, _T_1843) @[lsu_bus_buffer.scala 373:42]
-    node _T_1845 = eq(_T_1844, UInt<1>("h00")) @[lsu_bus_buffer.scala 372:78]
-    node _T_1846 = and(_T_1833, _T_1845) @[lsu_bus_buffer.scala 372:76]
-    node _T_1847 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 372:65]
-    node _T_1848 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 372:103]
-    node _T_1849 = and(ibuf_valid, _T_1848) @[lsu_bus_buffer.scala 372:92]
-    node _T_1850 = eq(WrPtr0_m, UInt<1>("h01")) @[lsu_bus_buffer.scala 373:33]
-    node _T_1851 = and(io.lsu_busreq_m, _T_1850) @[lsu_bus_buffer.scala 373:22]
-    node _T_1852 = or(_T_1849, _T_1851) @[lsu_bus_buffer.scala 372:112]
-    node _T_1853 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 374:36]
-    node _T_1854 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 375:34]
-    node _T_1855 = and(io.ldst_dual_r, _T_1854) @[lsu_bus_buffer.scala 375:23]
-    node _T_1856 = or(_T_1853, _T_1855) @[lsu_bus_buffer.scala 374:46]
-    node _T_1857 = and(io.lsu_busreq_r, _T_1856) @[lsu_bus_buffer.scala 374:22]
-    node _T_1858 = or(_T_1852, _T_1857) @[lsu_bus_buffer.scala 373:42]
-    node _T_1859 = eq(_T_1858, UInt<1>("h00")) @[lsu_bus_buffer.scala 372:78]
-    node _T_1860 = and(_T_1847, _T_1859) @[lsu_bus_buffer.scala 372:76]
-    node _T_1861 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 372:65]
-    node _T_1862 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 372:103]
-    node _T_1863 = and(ibuf_valid, _T_1862) @[lsu_bus_buffer.scala 372:92]
-    node _T_1864 = eq(WrPtr0_m, UInt<2>("h02")) @[lsu_bus_buffer.scala 373:33]
-    node _T_1865 = and(io.lsu_busreq_m, _T_1864) @[lsu_bus_buffer.scala 373:22]
-    node _T_1866 = or(_T_1863, _T_1865) @[lsu_bus_buffer.scala 372:112]
-    node _T_1867 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 374:36]
-    node _T_1868 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 375:34]
-    node _T_1869 = and(io.ldst_dual_r, _T_1868) @[lsu_bus_buffer.scala 375:23]
-    node _T_1870 = or(_T_1867, _T_1869) @[lsu_bus_buffer.scala 374:46]
-    node _T_1871 = and(io.lsu_busreq_r, _T_1870) @[lsu_bus_buffer.scala 374:22]
-    node _T_1872 = or(_T_1866, _T_1871) @[lsu_bus_buffer.scala 373:42]
-    node _T_1873 = eq(_T_1872, UInt<1>("h00")) @[lsu_bus_buffer.scala 372:78]
-    node _T_1874 = and(_T_1861, _T_1873) @[lsu_bus_buffer.scala 372:76]
-    node _T_1875 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 372:65]
-    node _T_1876 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 372:103]
-    node _T_1877 = and(ibuf_valid, _T_1876) @[lsu_bus_buffer.scala 372:92]
-    node _T_1878 = eq(WrPtr0_m, UInt<2>("h03")) @[lsu_bus_buffer.scala 373:33]
-    node _T_1879 = and(io.lsu_busreq_m, _T_1878) @[lsu_bus_buffer.scala 373:22]
-    node _T_1880 = or(_T_1877, _T_1879) @[lsu_bus_buffer.scala 372:112]
-    node _T_1881 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 374:36]
-    node _T_1882 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 375:34]
-    node _T_1883 = and(io.ldst_dual_r, _T_1882) @[lsu_bus_buffer.scala 375:23]
-    node _T_1884 = or(_T_1881, _T_1883) @[lsu_bus_buffer.scala 374:46]
-    node _T_1885 = and(io.lsu_busreq_r, _T_1884) @[lsu_bus_buffer.scala 374:22]
-    node _T_1886 = or(_T_1880, _T_1885) @[lsu_bus_buffer.scala 373:42]
-    node _T_1887 = eq(_T_1886, UInt<1>("h00")) @[lsu_bus_buffer.scala 372:78]
-    node _T_1888 = and(_T_1875, _T_1887) @[lsu_bus_buffer.scala 372:76]
-    node _T_1889 = mux(_T_1888, UInt<2>("h03"), UInt<2>("h03")) @[Mux.scala 98:16]
-    node _T_1890 = mux(_T_1874, UInt<2>("h02"), _T_1889) @[Mux.scala 98:16]
-    node _T_1891 = mux(_T_1860, UInt<1>("h01"), _T_1890) @[Mux.scala 98:16]
-    node _T_1892 = mux(_T_1846, UInt<1>("h00"), _T_1891) @[Mux.scala 98:16]
-    WrPtr1_m <= _T_1892 @[lsu_bus_buffer.scala 372:12]
-    wire buf_age : UInt<4>[4] @[lsu_bus_buffer.scala 377:21]
-    buf_age[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 378:11]
-    buf_age[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 378:11]
-    buf_age[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 378:11]
-    buf_age[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 378:11]
-    node _T_1893 = orr(buf_age[0]) @[lsu_bus_buffer.scala 380:58]
-    node _T_1894 = eq(_T_1893, UInt<1>("h00")) @[lsu_bus_buffer.scala 380:45]
-    node _T_1895 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 380:78]
-    node _T_1896 = and(_T_1894, _T_1895) @[lsu_bus_buffer.scala 380:63]
-    node _T_1897 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 380:90]
-    node _T_1898 = and(_T_1896, _T_1897) @[lsu_bus_buffer.scala 380:88]
-    node _T_1899 = orr(buf_age[1]) @[lsu_bus_buffer.scala 380:58]
-    node _T_1900 = eq(_T_1899, UInt<1>("h00")) @[lsu_bus_buffer.scala 380:45]
-    node _T_1901 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 380:78]
-    node _T_1902 = and(_T_1900, _T_1901) @[lsu_bus_buffer.scala 380:63]
-    node _T_1903 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 380:90]
-    node _T_1904 = and(_T_1902, _T_1903) @[lsu_bus_buffer.scala 380:88]
-    node _T_1905 = orr(buf_age[2]) @[lsu_bus_buffer.scala 380:58]
-    node _T_1906 = eq(_T_1905, UInt<1>("h00")) @[lsu_bus_buffer.scala 380:45]
-    node _T_1907 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 380:78]
-    node _T_1908 = and(_T_1906, _T_1907) @[lsu_bus_buffer.scala 380:63]
-    node _T_1909 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 380:90]
-    node _T_1910 = and(_T_1908, _T_1909) @[lsu_bus_buffer.scala 380:88]
-    node _T_1911 = orr(buf_age[3]) @[lsu_bus_buffer.scala 380:58]
-    node _T_1912 = eq(_T_1911, UInt<1>("h00")) @[lsu_bus_buffer.scala 380:45]
-    node _T_1913 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 380:78]
-    node _T_1914 = and(_T_1912, _T_1913) @[lsu_bus_buffer.scala 380:63]
-    node _T_1915 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 380:90]
-    node _T_1916 = and(_T_1914, _T_1915) @[lsu_bus_buffer.scala 380:88]
-    node _T_1917 = cat(_T_1916, _T_1910) @[Cat.scala 29:58]
-    node _T_1918 = cat(_T_1917, _T_1904) @[Cat.scala 29:58]
-    node CmdPtr0Dec = cat(_T_1918, _T_1898) @[Cat.scala 29:58]
-    node _T_1919 = not(CmdPtr0Dec) @[lsu_bus_buffer.scala 381:62]
-    node _T_1920 = and(buf_age[0], _T_1919) @[lsu_bus_buffer.scala 381:59]
-    node _T_1921 = orr(_T_1920) @[lsu_bus_buffer.scala 381:76]
-    node _T_1922 = eq(_T_1921, UInt<1>("h00")) @[lsu_bus_buffer.scala 381:45]
-    node _T_1923 = bits(CmdPtr0Dec, 0, 0) @[lsu_bus_buffer.scala 381:94]
-    node _T_1924 = eq(_T_1923, UInt<1>("h00")) @[lsu_bus_buffer.scala 381:83]
-    node _T_1925 = and(_T_1922, _T_1924) @[lsu_bus_buffer.scala 381:81]
-    node _T_1926 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 381:113]
-    node _T_1927 = and(_T_1925, _T_1926) @[lsu_bus_buffer.scala 381:98]
-    node _T_1928 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 381:125]
-    node _T_1929 = and(_T_1927, _T_1928) @[lsu_bus_buffer.scala 381:123]
-    node _T_1930 = not(CmdPtr0Dec) @[lsu_bus_buffer.scala 381:62]
-    node _T_1931 = and(buf_age[1], _T_1930) @[lsu_bus_buffer.scala 381:59]
-    node _T_1932 = orr(_T_1931) @[lsu_bus_buffer.scala 381:76]
-    node _T_1933 = eq(_T_1932, UInt<1>("h00")) @[lsu_bus_buffer.scala 381:45]
-    node _T_1934 = bits(CmdPtr0Dec, 1, 1) @[lsu_bus_buffer.scala 381:94]
-    node _T_1935 = eq(_T_1934, UInt<1>("h00")) @[lsu_bus_buffer.scala 381:83]
-    node _T_1936 = and(_T_1933, _T_1935) @[lsu_bus_buffer.scala 381:81]
-    node _T_1937 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 381:113]
-    node _T_1938 = and(_T_1936, _T_1937) @[lsu_bus_buffer.scala 381:98]
-    node _T_1939 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 381:125]
-    node _T_1940 = and(_T_1938, _T_1939) @[lsu_bus_buffer.scala 381:123]
-    node _T_1941 = not(CmdPtr0Dec) @[lsu_bus_buffer.scala 381:62]
-    node _T_1942 = and(buf_age[2], _T_1941) @[lsu_bus_buffer.scala 381:59]
-    node _T_1943 = orr(_T_1942) @[lsu_bus_buffer.scala 381:76]
-    node _T_1944 = eq(_T_1943, UInt<1>("h00")) @[lsu_bus_buffer.scala 381:45]
-    node _T_1945 = bits(CmdPtr0Dec, 2, 2) @[lsu_bus_buffer.scala 381:94]
-    node _T_1946 = eq(_T_1945, UInt<1>("h00")) @[lsu_bus_buffer.scala 381:83]
-    node _T_1947 = and(_T_1944, _T_1946) @[lsu_bus_buffer.scala 381:81]
-    node _T_1948 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 381:113]
-    node _T_1949 = and(_T_1947, _T_1948) @[lsu_bus_buffer.scala 381:98]
-    node _T_1950 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 381:125]
-    node _T_1951 = and(_T_1949, _T_1950) @[lsu_bus_buffer.scala 381:123]
-    node _T_1952 = not(CmdPtr0Dec) @[lsu_bus_buffer.scala 381:62]
-    node _T_1953 = and(buf_age[3], _T_1952) @[lsu_bus_buffer.scala 381:59]
-    node _T_1954 = orr(_T_1953) @[lsu_bus_buffer.scala 381:76]
-    node _T_1955 = eq(_T_1954, UInt<1>("h00")) @[lsu_bus_buffer.scala 381:45]
-    node _T_1956 = bits(CmdPtr0Dec, 3, 3) @[lsu_bus_buffer.scala 381:94]
-    node _T_1957 = eq(_T_1956, UInt<1>("h00")) @[lsu_bus_buffer.scala 381:83]
-    node _T_1958 = and(_T_1955, _T_1957) @[lsu_bus_buffer.scala 381:81]
-    node _T_1959 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 381:113]
-    node _T_1960 = and(_T_1958, _T_1959) @[lsu_bus_buffer.scala 381:98]
-    node _T_1961 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 381:125]
-    node _T_1962 = and(_T_1960, _T_1961) @[lsu_bus_buffer.scala 381:123]
-    node _T_1963 = cat(_T_1962, _T_1951) @[Cat.scala 29:58]
-    node _T_1964 = cat(_T_1963, _T_1940) @[Cat.scala 29:58]
-    node CmdPtr1Dec = cat(_T_1964, _T_1929) @[Cat.scala 29:58]
-    wire buf_rsp_pickage : UInt<4>[4] @[lsu_bus_buffer.scala 382:29]
-    buf_rsp_pickage[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 383:19]
-    buf_rsp_pickage[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 383:19]
-    buf_rsp_pickage[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 383:19]
-    buf_rsp_pickage[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 383:19]
-    node _T_1965 = orr(buf_rsp_pickage[0]) @[lsu_bus_buffer.scala 384:65]
-    node _T_1966 = eq(_T_1965, UInt<1>("h00")) @[lsu_bus_buffer.scala 384:44]
-    node _T_1967 = eq(buf_state[0], UInt<3>("h05")) @[lsu_bus_buffer.scala 384:85]
-    node _T_1968 = and(_T_1966, _T_1967) @[lsu_bus_buffer.scala 384:70]
-    node _T_1969 = orr(buf_rsp_pickage[1]) @[lsu_bus_buffer.scala 384:65]
-    node _T_1970 = eq(_T_1969, UInt<1>("h00")) @[lsu_bus_buffer.scala 384:44]
-    node _T_1971 = eq(buf_state[1], UInt<3>("h05")) @[lsu_bus_buffer.scala 384:85]
-    node _T_1972 = and(_T_1970, _T_1971) @[lsu_bus_buffer.scala 384:70]
-    node _T_1973 = orr(buf_rsp_pickage[2]) @[lsu_bus_buffer.scala 384:65]
-    node _T_1974 = eq(_T_1973, UInt<1>("h00")) @[lsu_bus_buffer.scala 384:44]
-    node _T_1975 = eq(buf_state[2], UInt<3>("h05")) @[lsu_bus_buffer.scala 384:85]
-    node _T_1976 = and(_T_1974, _T_1975) @[lsu_bus_buffer.scala 384:70]
-    node _T_1977 = orr(buf_rsp_pickage[3]) @[lsu_bus_buffer.scala 384:65]
-    node _T_1978 = eq(_T_1977, UInt<1>("h00")) @[lsu_bus_buffer.scala 384:44]
-    node _T_1979 = eq(buf_state[3], UInt<3>("h05")) @[lsu_bus_buffer.scala 384:85]
-    node _T_1980 = and(_T_1978, _T_1979) @[lsu_bus_buffer.scala 384:70]
-    node _T_1981 = cat(_T_1980, _T_1976) @[Cat.scala 29:58]
-    node _T_1982 = cat(_T_1981, _T_1972) @[Cat.scala 29:58]
-    node RspPtrDec = cat(_T_1982, _T_1968) @[Cat.scala 29:58]
-    node _T_1983 = orr(CmdPtr0Dec) @[lsu_bus_buffer.scala 385:31]
-    found_cmdptr0 <= _T_1983 @[lsu_bus_buffer.scala 385:17]
-    node _T_1984 = orr(CmdPtr1Dec) @[lsu_bus_buffer.scala 386:31]
-    found_cmdptr1 <= _T_1984 @[lsu_bus_buffer.scala 386:17]
+    node _T_1840 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 373:65]
+    node _T_1841 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 373:103]
+    node _T_1842 = and(ibuf_valid, _T_1841) @[lsu_bus_buffer.scala 373:92]
+    node _T_1843 = eq(WrPtr0_m, UInt<1>("h00")) @[lsu_bus_buffer.scala 374:33]
+    node _T_1844 = and(io.lsu_busreq_m, _T_1843) @[lsu_bus_buffer.scala 374:22]
+    node _T_1845 = or(_T_1842, _T_1844) @[lsu_bus_buffer.scala 373:112]
+    node _T_1846 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 375:36]
+    node _T_1847 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 376:34]
+    node _T_1848 = and(io.ldst_dual_r, _T_1847) @[lsu_bus_buffer.scala 376:23]
+    node _T_1849 = or(_T_1846, _T_1848) @[lsu_bus_buffer.scala 375:46]
+    node _T_1850 = and(io.lsu_busreq_r, _T_1849) @[lsu_bus_buffer.scala 375:22]
+    node _T_1851 = or(_T_1845, _T_1850) @[lsu_bus_buffer.scala 374:42]
+    node _T_1852 = eq(_T_1851, UInt<1>("h00")) @[lsu_bus_buffer.scala 373:78]
+    node _T_1853 = and(_T_1840, _T_1852) @[lsu_bus_buffer.scala 373:76]
+    node _T_1854 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 373:65]
+    node _T_1855 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 373:103]
+    node _T_1856 = and(ibuf_valid, _T_1855) @[lsu_bus_buffer.scala 373:92]
+    node _T_1857 = eq(WrPtr0_m, UInt<1>("h01")) @[lsu_bus_buffer.scala 374:33]
+    node _T_1858 = and(io.lsu_busreq_m, _T_1857) @[lsu_bus_buffer.scala 374:22]
+    node _T_1859 = or(_T_1856, _T_1858) @[lsu_bus_buffer.scala 373:112]
+    node _T_1860 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 375:36]
+    node _T_1861 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 376:34]
+    node _T_1862 = and(io.ldst_dual_r, _T_1861) @[lsu_bus_buffer.scala 376:23]
+    node _T_1863 = or(_T_1860, _T_1862) @[lsu_bus_buffer.scala 375:46]
+    node _T_1864 = and(io.lsu_busreq_r, _T_1863) @[lsu_bus_buffer.scala 375:22]
+    node _T_1865 = or(_T_1859, _T_1864) @[lsu_bus_buffer.scala 374:42]
+    node _T_1866 = eq(_T_1865, UInt<1>("h00")) @[lsu_bus_buffer.scala 373:78]
+    node _T_1867 = and(_T_1854, _T_1866) @[lsu_bus_buffer.scala 373:76]
+    node _T_1868 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 373:65]
+    node _T_1869 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 373:103]
+    node _T_1870 = and(ibuf_valid, _T_1869) @[lsu_bus_buffer.scala 373:92]
+    node _T_1871 = eq(WrPtr0_m, UInt<2>("h02")) @[lsu_bus_buffer.scala 374:33]
+    node _T_1872 = and(io.lsu_busreq_m, _T_1871) @[lsu_bus_buffer.scala 374:22]
+    node _T_1873 = or(_T_1870, _T_1872) @[lsu_bus_buffer.scala 373:112]
+    node _T_1874 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 375:36]
+    node _T_1875 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 376:34]
+    node _T_1876 = and(io.ldst_dual_r, _T_1875) @[lsu_bus_buffer.scala 376:23]
+    node _T_1877 = or(_T_1874, _T_1876) @[lsu_bus_buffer.scala 375:46]
+    node _T_1878 = and(io.lsu_busreq_r, _T_1877) @[lsu_bus_buffer.scala 375:22]
+    node _T_1879 = or(_T_1873, _T_1878) @[lsu_bus_buffer.scala 374:42]
+    node _T_1880 = eq(_T_1879, UInt<1>("h00")) @[lsu_bus_buffer.scala 373:78]
+    node _T_1881 = and(_T_1868, _T_1880) @[lsu_bus_buffer.scala 373:76]
+    node _T_1882 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 373:65]
+    node _T_1883 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 373:103]
+    node _T_1884 = and(ibuf_valid, _T_1883) @[lsu_bus_buffer.scala 373:92]
+    node _T_1885 = eq(WrPtr0_m, UInt<2>("h03")) @[lsu_bus_buffer.scala 374:33]
+    node _T_1886 = and(io.lsu_busreq_m, _T_1885) @[lsu_bus_buffer.scala 374:22]
+    node _T_1887 = or(_T_1884, _T_1886) @[lsu_bus_buffer.scala 373:112]
+    node _T_1888 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 375:36]
+    node _T_1889 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 376:34]
+    node _T_1890 = and(io.ldst_dual_r, _T_1889) @[lsu_bus_buffer.scala 376:23]
+    node _T_1891 = or(_T_1888, _T_1890) @[lsu_bus_buffer.scala 375:46]
+    node _T_1892 = and(io.lsu_busreq_r, _T_1891) @[lsu_bus_buffer.scala 375:22]
+    node _T_1893 = or(_T_1887, _T_1892) @[lsu_bus_buffer.scala 374:42]
+    node _T_1894 = eq(_T_1893, UInt<1>("h00")) @[lsu_bus_buffer.scala 373:78]
+    node _T_1895 = and(_T_1882, _T_1894) @[lsu_bus_buffer.scala 373:76]
+    node _T_1896 = mux(_T_1895, UInt<2>("h03"), UInt<2>("h03")) @[Mux.scala 98:16]
+    node _T_1897 = mux(_T_1881, UInt<2>("h02"), _T_1896) @[Mux.scala 98:16]
+    node _T_1898 = mux(_T_1867, UInt<1>("h01"), _T_1897) @[Mux.scala 98:16]
+    node _T_1899 = mux(_T_1853, UInt<1>("h00"), _T_1898) @[Mux.scala 98:16]
+    WrPtr1_m <= _T_1899 @[lsu_bus_buffer.scala 373:12]
+    wire buf_age : UInt<4>[4] @[lsu_bus_buffer.scala 378:21]
+    buf_age[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 379:11]
+    buf_age[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 379:11]
+    buf_age[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 379:11]
+    buf_age[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 379:11]
+    node _T_1900 = orr(buf_age[0]) @[lsu_bus_buffer.scala 381:58]
+    node _T_1901 = eq(_T_1900, UInt<1>("h00")) @[lsu_bus_buffer.scala 381:45]
+    node _T_1902 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 381:78]
+    node _T_1903 = and(_T_1901, _T_1902) @[lsu_bus_buffer.scala 381:63]
+    node _T_1904 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 381:90]
+    node _T_1905 = and(_T_1903, _T_1904) @[lsu_bus_buffer.scala 381:88]
+    node _T_1906 = orr(buf_age[1]) @[lsu_bus_buffer.scala 381:58]
+    node _T_1907 = eq(_T_1906, UInt<1>("h00")) @[lsu_bus_buffer.scala 381:45]
+    node _T_1908 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 381:78]
+    node _T_1909 = and(_T_1907, _T_1908) @[lsu_bus_buffer.scala 381:63]
+    node _T_1910 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 381:90]
+    node _T_1911 = and(_T_1909, _T_1910) @[lsu_bus_buffer.scala 381:88]
+    node _T_1912 = orr(buf_age[2]) @[lsu_bus_buffer.scala 381:58]
+    node _T_1913 = eq(_T_1912, UInt<1>("h00")) @[lsu_bus_buffer.scala 381:45]
+    node _T_1914 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 381:78]
+    node _T_1915 = and(_T_1913, _T_1914) @[lsu_bus_buffer.scala 381:63]
+    node _T_1916 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 381:90]
+    node _T_1917 = and(_T_1915, _T_1916) @[lsu_bus_buffer.scala 381:88]
+    node _T_1918 = orr(buf_age[3]) @[lsu_bus_buffer.scala 381:58]
+    node _T_1919 = eq(_T_1918, UInt<1>("h00")) @[lsu_bus_buffer.scala 381:45]
+    node _T_1920 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 381:78]
+    node _T_1921 = and(_T_1919, _T_1920) @[lsu_bus_buffer.scala 381:63]
+    node _T_1922 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 381:90]
+    node _T_1923 = and(_T_1921, _T_1922) @[lsu_bus_buffer.scala 381:88]
+    node _T_1924 = cat(_T_1923, _T_1917) @[Cat.scala 29:58]
+    node _T_1925 = cat(_T_1924, _T_1911) @[Cat.scala 29:58]
+    node CmdPtr0Dec = cat(_T_1925, _T_1905) @[Cat.scala 29:58]
+    node _T_1926 = not(CmdPtr0Dec) @[lsu_bus_buffer.scala 382:62]
+    node _T_1927 = and(buf_age[0], _T_1926) @[lsu_bus_buffer.scala 382:59]
+    node _T_1928 = orr(_T_1927) @[lsu_bus_buffer.scala 382:76]
+    node _T_1929 = eq(_T_1928, UInt<1>("h00")) @[lsu_bus_buffer.scala 382:45]
+    node _T_1930 = bits(CmdPtr0Dec, 0, 0) @[lsu_bus_buffer.scala 382:94]
+    node _T_1931 = eq(_T_1930, UInt<1>("h00")) @[lsu_bus_buffer.scala 382:83]
+    node _T_1932 = and(_T_1929, _T_1931) @[lsu_bus_buffer.scala 382:81]
+    node _T_1933 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 382:113]
+    node _T_1934 = and(_T_1932, _T_1933) @[lsu_bus_buffer.scala 382:98]
+    node _T_1935 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 382:125]
+    node _T_1936 = and(_T_1934, _T_1935) @[lsu_bus_buffer.scala 382:123]
+    node _T_1937 = not(CmdPtr0Dec) @[lsu_bus_buffer.scala 382:62]
+    node _T_1938 = and(buf_age[1], _T_1937) @[lsu_bus_buffer.scala 382:59]
+    node _T_1939 = orr(_T_1938) @[lsu_bus_buffer.scala 382:76]
+    node _T_1940 = eq(_T_1939, UInt<1>("h00")) @[lsu_bus_buffer.scala 382:45]
+    node _T_1941 = bits(CmdPtr0Dec, 1, 1) @[lsu_bus_buffer.scala 382:94]
+    node _T_1942 = eq(_T_1941, UInt<1>("h00")) @[lsu_bus_buffer.scala 382:83]
+    node _T_1943 = and(_T_1940, _T_1942) @[lsu_bus_buffer.scala 382:81]
+    node _T_1944 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 382:113]
+    node _T_1945 = and(_T_1943, _T_1944) @[lsu_bus_buffer.scala 382:98]
+    node _T_1946 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 382:125]
+    node _T_1947 = and(_T_1945, _T_1946) @[lsu_bus_buffer.scala 382:123]
+    node _T_1948 = not(CmdPtr0Dec) @[lsu_bus_buffer.scala 382:62]
+    node _T_1949 = and(buf_age[2], _T_1948) @[lsu_bus_buffer.scala 382:59]
+    node _T_1950 = orr(_T_1949) @[lsu_bus_buffer.scala 382:76]
+    node _T_1951 = eq(_T_1950, UInt<1>("h00")) @[lsu_bus_buffer.scala 382:45]
+    node _T_1952 = bits(CmdPtr0Dec, 2, 2) @[lsu_bus_buffer.scala 382:94]
+    node _T_1953 = eq(_T_1952, UInt<1>("h00")) @[lsu_bus_buffer.scala 382:83]
+    node _T_1954 = and(_T_1951, _T_1953) @[lsu_bus_buffer.scala 382:81]
+    node _T_1955 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 382:113]
+    node _T_1956 = and(_T_1954, _T_1955) @[lsu_bus_buffer.scala 382:98]
+    node _T_1957 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 382:125]
+    node _T_1958 = and(_T_1956, _T_1957) @[lsu_bus_buffer.scala 382:123]
+    node _T_1959 = not(CmdPtr0Dec) @[lsu_bus_buffer.scala 382:62]
+    node _T_1960 = and(buf_age[3], _T_1959) @[lsu_bus_buffer.scala 382:59]
+    node _T_1961 = orr(_T_1960) @[lsu_bus_buffer.scala 382:76]
+    node _T_1962 = eq(_T_1961, UInt<1>("h00")) @[lsu_bus_buffer.scala 382:45]
+    node _T_1963 = bits(CmdPtr0Dec, 3, 3) @[lsu_bus_buffer.scala 382:94]
+    node _T_1964 = eq(_T_1963, UInt<1>("h00")) @[lsu_bus_buffer.scala 382:83]
+    node _T_1965 = and(_T_1962, _T_1964) @[lsu_bus_buffer.scala 382:81]
+    node _T_1966 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 382:113]
+    node _T_1967 = and(_T_1965, _T_1966) @[lsu_bus_buffer.scala 382:98]
+    node _T_1968 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 382:125]
+    node _T_1969 = and(_T_1967, _T_1968) @[lsu_bus_buffer.scala 382:123]
+    node _T_1970 = cat(_T_1969, _T_1958) @[Cat.scala 29:58]
+    node _T_1971 = cat(_T_1970, _T_1947) @[Cat.scala 29:58]
+    node CmdPtr1Dec = cat(_T_1971, _T_1936) @[Cat.scala 29:58]
+    wire buf_rsp_pickage : UInt<4>[4] @[lsu_bus_buffer.scala 383:29]
+    buf_rsp_pickage[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 384:19]
+    buf_rsp_pickage[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 384:19]
+    buf_rsp_pickage[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 384:19]
+    buf_rsp_pickage[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 384:19]
+    node _T_1972 = orr(buf_rsp_pickage[0]) @[lsu_bus_buffer.scala 385:65]
+    node _T_1973 = eq(_T_1972, UInt<1>("h00")) @[lsu_bus_buffer.scala 385:44]
+    node _T_1974 = eq(buf_state[0], UInt<3>("h05")) @[lsu_bus_buffer.scala 385:85]
+    node _T_1975 = and(_T_1973, _T_1974) @[lsu_bus_buffer.scala 385:70]
+    node _T_1976 = orr(buf_rsp_pickage[1]) @[lsu_bus_buffer.scala 385:65]
+    node _T_1977 = eq(_T_1976, UInt<1>("h00")) @[lsu_bus_buffer.scala 385:44]
+    node _T_1978 = eq(buf_state[1], UInt<3>("h05")) @[lsu_bus_buffer.scala 385:85]
+    node _T_1979 = and(_T_1977, _T_1978) @[lsu_bus_buffer.scala 385:70]
+    node _T_1980 = orr(buf_rsp_pickage[2]) @[lsu_bus_buffer.scala 385:65]
+    node _T_1981 = eq(_T_1980, UInt<1>("h00")) @[lsu_bus_buffer.scala 385:44]
+    node _T_1982 = eq(buf_state[2], UInt<3>("h05")) @[lsu_bus_buffer.scala 385:85]
+    node _T_1983 = and(_T_1981, _T_1982) @[lsu_bus_buffer.scala 385:70]
+    node _T_1984 = orr(buf_rsp_pickage[3]) @[lsu_bus_buffer.scala 385:65]
+    node _T_1985 = eq(_T_1984, UInt<1>("h00")) @[lsu_bus_buffer.scala 385:44]
+    node _T_1986 = eq(buf_state[3], UInt<3>("h05")) @[lsu_bus_buffer.scala 385:85]
+    node _T_1987 = and(_T_1985, _T_1986) @[lsu_bus_buffer.scala 385:70]
+    node _T_1988 = cat(_T_1987, _T_1983) @[Cat.scala 29:58]
+    node _T_1989 = cat(_T_1988, _T_1979) @[Cat.scala 29:58]
+    node RspPtrDec = cat(_T_1989, _T_1975) @[Cat.scala 29:58]
+    node _T_1990 = orr(CmdPtr0Dec) @[lsu_bus_buffer.scala 386:31]
+    found_cmdptr0 <= _T_1990 @[lsu_bus_buffer.scala 386:17]
+    node _T_1991 = orr(CmdPtr1Dec) @[lsu_bus_buffer.scala 387:31]
+    found_cmdptr1 <= _T_1991 @[lsu_bus_buffer.scala 387:17]
     wire RspPtr : UInt<2>
     RspPtr <= UInt<1>("h00")
-    node _T_1985 = mux(UInt<1>("h00"), UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
-    node _T_1986 = cat(_T_1985, CmdPtr0Dec) @[Cat.scala 29:58]
-    node _T_1987 = bits(_T_1986, 4, 4) @[lsu_bus_buffer.scala 388:39]
-    node _T_1988 = bits(_T_1986, 5, 5) @[lsu_bus_buffer.scala 388:45]
-    node _T_1989 = or(_T_1987, _T_1988) @[lsu_bus_buffer.scala 388:42]
-    node _T_1990 = bits(_T_1986, 6, 6) @[lsu_bus_buffer.scala 388:51]
-    node _T_1991 = or(_T_1989, _T_1990) @[lsu_bus_buffer.scala 388:48]
-    node _T_1992 = bits(_T_1986, 7, 7) @[lsu_bus_buffer.scala 388:57]
-    node _T_1993 = or(_T_1991, _T_1992) @[lsu_bus_buffer.scala 388:54]
-    node _T_1994 = bits(_T_1986, 2, 2) @[lsu_bus_buffer.scala 388:64]
-    node _T_1995 = bits(_T_1986, 3, 3) @[lsu_bus_buffer.scala 388:70]
-    node _T_1996 = or(_T_1994, _T_1995) @[lsu_bus_buffer.scala 388:67]
-    node _T_1997 = bits(_T_1986, 6, 6) @[lsu_bus_buffer.scala 388:76]
-    node _T_1998 = or(_T_1996, _T_1997) @[lsu_bus_buffer.scala 388:73]
-    node _T_1999 = bits(_T_1986, 7, 7) @[lsu_bus_buffer.scala 388:82]
-    node _T_2000 = or(_T_1998, _T_1999) @[lsu_bus_buffer.scala 388:79]
-    node _T_2001 = bits(_T_1986, 1, 1) @[lsu_bus_buffer.scala 388:89]
-    node _T_2002 = bits(_T_1986, 3, 3) @[lsu_bus_buffer.scala 388:95]
-    node _T_2003 = or(_T_2001, _T_2002) @[lsu_bus_buffer.scala 388:92]
-    node _T_2004 = bits(_T_1986, 5, 5) @[lsu_bus_buffer.scala 388:101]
-    node _T_2005 = or(_T_2003, _T_2004) @[lsu_bus_buffer.scala 388:98]
-    node _T_2006 = bits(_T_1986, 7, 7) @[lsu_bus_buffer.scala 388:107]
-    node _T_2007 = or(_T_2005, _T_2006) @[lsu_bus_buffer.scala 388:104]
-    node _T_2008 = cat(_T_1993, _T_2000) @[Cat.scala 29:58]
-    node _T_2009 = cat(_T_2008, _T_2007) @[Cat.scala 29:58]
-    CmdPtr0 <= _T_2009 @[lsu_bus_buffer.scala 393:11]
-    node _T_2010 = mux(UInt<1>("h00"), UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
-    node _T_2011 = cat(_T_2010, CmdPtr1Dec) @[Cat.scala 29:58]
-    node _T_2012 = bits(_T_2011, 4, 4) @[lsu_bus_buffer.scala 388:39]
-    node _T_2013 = bits(_T_2011, 5, 5) @[lsu_bus_buffer.scala 388:45]
-    node _T_2014 = or(_T_2012, _T_2013) @[lsu_bus_buffer.scala 388:42]
-    node _T_2015 = bits(_T_2011, 6, 6) @[lsu_bus_buffer.scala 388:51]
-    node _T_2016 = or(_T_2014, _T_2015) @[lsu_bus_buffer.scala 388:48]
-    node _T_2017 = bits(_T_2011, 7, 7) @[lsu_bus_buffer.scala 388:57]
-    node _T_2018 = or(_T_2016, _T_2017) @[lsu_bus_buffer.scala 388:54]
-    node _T_2019 = bits(_T_2011, 2, 2) @[lsu_bus_buffer.scala 388:64]
-    node _T_2020 = bits(_T_2011, 3, 3) @[lsu_bus_buffer.scala 388:70]
-    node _T_2021 = or(_T_2019, _T_2020) @[lsu_bus_buffer.scala 388:67]
-    node _T_2022 = bits(_T_2011, 6, 6) @[lsu_bus_buffer.scala 388:76]
-    node _T_2023 = or(_T_2021, _T_2022) @[lsu_bus_buffer.scala 388:73]
-    node _T_2024 = bits(_T_2011, 7, 7) @[lsu_bus_buffer.scala 388:82]
-    node _T_2025 = or(_T_2023, _T_2024) @[lsu_bus_buffer.scala 388:79]
-    node _T_2026 = bits(_T_2011, 1, 1) @[lsu_bus_buffer.scala 388:89]
-    node _T_2027 = bits(_T_2011, 3, 3) @[lsu_bus_buffer.scala 388:95]
-    node _T_2028 = or(_T_2026, _T_2027) @[lsu_bus_buffer.scala 388:92]
-    node _T_2029 = bits(_T_2011, 5, 5) @[lsu_bus_buffer.scala 388:101]
-    node _T_2030 = or(_T_2028, _T_2029) @[lsu_bus_buffer.scala 388:98]
-    node _T_2031 = bits(_T_2011, 7, 7) @[lsu_bus_buffer.scala 388:107]
-    node _T_2032 = or(_T_2030, _T_2031) @[lsu_bus_buffer.scala 388:104]
-    node _T_2033 = cat(_T_2018, _T_2025) @[Cat.scala 29:58]
-    node _T_2034 = cat(_T_2033, _T_2032) @[Cat.scala 29:58]
-    CmdPtr1 <= _T_2034 @[lsu_bus_buffer.scala 395:11]
-    node _T_2035 = mux(UInt<1>("h00"), UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
-    node _T_2036 = cat(_T_2035, RspPtrDec) @[Cat.scala 29:58]
-    node _T_2037 = bits(_T_2036, 4, 4) @[lsu_bus_buffer.scala 388:39]
-    node _T_2038 = bits(_T_2036, 5, 5) @[lsu_bus_buffer.scala 388:45]
-    node _T_2039 = or(_T_2037, _T_2038) @[lsu_bus_buffer.scala 388:42]
-    node _T_2040 = bits(_T_2036, 6, 6) @[lsu_bus_buffer.scala 388:51]
-    node _T_2041 = or(_T_2039, _T_2040) @[lsu_bus_buffer.scala 388:48]
-    node _T_2042 = bits(_T_2036, 7, 7) @[lsu_bus_buffer.scala 388:57]
-    node _T_2043 = or(_T_2041, _T_2042) @[lsu_bus_buffer.scala 388:54]
-    node _T_2044 = bits(_T_2036, 2, 2) @[lsu_bus_buffer.scala 388:64]
-    node _T_2045 = bits(_T_2036, 3, 3) @[lsu_bus_buffer.scala 388:70]
-    node _T_2046 = or(_T_2044, _T_2045) @[lsu_bus_buffer.scala 388:67]
-    node _T_2047 = bits(_T_2036, 6, 6) @[lsu_bus_buffer.scala 388:76]
-    node _T_2048 = or(_T_2046, _T_2047) @[lsu_bus_buffer.scala 388:73]
-    node _T_2049 = bits(_T_2036, 7, 7) @[lsu_bus_buffer.scala 388:82]
-    node _T_2050 = or(_T_2048, _T_2049) @[lsu_bus_buffer.scala 388:79]
-    node _T_2051 = bits(_T_2036, 1, 1) @[lsu_bus_buffer.scala 388:89]
-    node _T_2052 = bits(_T_2036, 3, 3) @[lsu_bus_buffer.scala 388:95]
-    node _T_2053 = or(_T_2051, _T_2052) @[lsu_bus_buffer.scala 388:92]
-    node _T_2054 = bits(_T_2036, 5, 5) @[lsu_bus_buffer.scala 388:101]
-    node _T_2055 = or(_T_2053, _T_2054) @[lsu_bus_buffer.scala 388:98]
-    node _T_2056 = bits(_T_2036, 7, 7) @[lsu_bus_buffer.scala 388:107]
-    node _T_2057 = or(_T_2055, _T_2056) @[lsu_bus_buffer.scala 388:104]
-    node _T_2058 = cat(_T_2043, _T_2050) @[Cat.scala 29:58]
-    node _T_2059 = cat(_T_2058, _T_2057) @[Cat.scala 29:58]
-    RspPtr <= _T_2059 @[lsu_bus_buffer.scala 396:10]
-    wire buf_state_en : UInt<1>[4] @[lsu_bus_buffer.scala 397:26]
-    buf_state_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 398:16]
-    buf_state_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 398:16]
-    buf_state_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 398:16]
-    buf_state_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 398:16]
-    wire buf_rspageQ : UInt<4>[4] @[lsu_bus_buffer.scala 399:25]
-    buf_rspageQ[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 400:15]
-    buf_rspageQ[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 400:15]
-    buf_rspageQ[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 400:15]
-    buf_rspageQ[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 400:15]
-    wire buf_rspage_set : UInt<4>[4] @[lsu_bus_buffer.scala 401:28]
-    buf_rspage_set[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 402:18]
-    buf_rspage_set[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 402:18]
-    buf_rspage_set[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 402:18]
-    buf_rspage_set[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 402:18]
-    wire buf_rspage_in : UInt<4>[4] @[lsu_bus_buffer.scala 403:27]
-    buf_rspage_in[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 404:17]
-    buf_rspage_in[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 404:17]
-    buf_rspage_in[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 404:17]
-    buf_rspage_in[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 404:17]
-    wire buf_rspage : UInt<4>[4] @[lsu_bus_buffer.scala 405:24]
-    buf_rspage[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 406:14]
-    buf_rspage[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 406:14]
-    buf_rspage[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 406:14]
-    buf_rspage[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 406:14]
-    node _T_2060 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 408:83]
-    node _T_2061 = and(_T_2060, buf_state_en[0]) @[lsu_bus_buffer.scala 408:94]
-    node _T_2062 = eq(buf_state[0], UInt<3>("h01")) @[lsu_bus_buffer.scala 409:20]
-    node _T_2063 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 409:47]
-    node _T_2064 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 409:59]
-    node _T_2065 = and(_T_2063, _T_2064) @[lsu_bus_buffer.scala 409:57]
-    node _T_2066 = or(_T_2062, _T_2065) @[lsu_bus_buffer.scala 409:31]
-    node _T_2067 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 410:23]
-    node _T_2068 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 410:53]
-    node _T_2069 = and(_T_2067, _T_2068) @[lsu_bus_buffer.scala 410:41]
-    node _T_2070 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 410:83]
-    node _T_2071 = and(_T_2069, _T_2070) @[lsu_bus_buffer.scala 410:71]
-    node _T_2072 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 410:104]
-    node _T_2073 = and(_T_2071, _T_2072) @[lsu_bus_buffer.scala 410:92]
-    node _T_2074 = or(_T_2066, _T_2073) @[lsu_bus_buffer.scala 409:86]
-    node _T_2075 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 411:17]
-    node _T_2076 = and(_T_2075, io.ldst_dual_r) @[lsu_bus_buffer.scala 411:35]
-    node _T_2077 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 411:64]
-    node _T_2078 = and(_T_2076, _T_2077) @[lsu_bus_buffer.scala 411:52]
-    node _T_2079 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 411:85]
-    node _T_2080 = and(_T_2078, _T_2079) @[lsu_bus_buffer.scala 411:73]
-    node _T_2081 = or(_T_2074, _T_2080) @[lsu_bus_buffer.scala 410:114]
-    node _T_2082 = and(_T_2061, _T_2081) @[lsu_bus_buffer.scala 408:113]
-    node _T_2083 = bits(buf_age[0], 0, 0) @[lsu_bus_buffer.scala 411:109]
-    node _T_2084 = or(_T_2082, _T_2083) @[lsu_bus_buffer.scala 411:97]
-    node _T_2085 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 408:83]
-    node _T_2086 = and(_T_2085, buf_state_en[0]) @[lsu_bus_buffer.scala 408:94]
-    node _T_2087 = eq(buf_state[1], UInt<3>("h01")) @[lsu_bus_buffer.scala 409:20]
-    node _T_2088 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 409:47]
-    node _T_2089 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 409:59]
-    node _T_2090 = and(_T_2088, _T_2089) @[lsu_bus_buffer.scala 409:57]
-    node _T_2091 = or(_T_2087, _T_2090) @[lsu_bus_buffer.scala 409:31]
-    node _T_2092 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 410:23]
-    node _T_2093 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 410:53]
-    node _T_2094 = and(_T_2092, _T_2093) @[lsu_bus_buffer.scala 410:41]
-    node _T_2095 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 410:83]
-    node _T_2096 = and(_T_2094, _T_2095) @[lsu_bus_buffer.scala 410:71]
-    node _T_2097 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 410:104]
-    node _T_2098 = and(_T_2096, _T_2097) @[lsu_bus_buffer.scala 410:92]
-    node _T_2099 = or(_T_2091, _T_2098) @[lsu_bus_buffer.scala 409:86]
-    node _T_2100 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 411:17]
-    node _T_2101 = and(_T_2100, io.ldst_dual_r) @[lsu_bus_buffer.scala 411:35]
-    node _T_2102 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 411:64]
-    node _T_2103 = and(_T_2101, _T_2102) @[lsu_bus_buffer.scala 411:52]
-    node _T_2104 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 411:85]
-    node _T_2105 = and(_T_2103, _T_2104) @[lsu_bus_buffer.scala 411:73]
-    node _T_2106 = or(_T_2099, _T_2105) @[lsu_bus_buffer.scala 410:114]
-    node _T_2107 = and(_T_2086, _T_2106) @[lsu_bus_buffer.scala 408:113]
-    node _T_2108 = bits(buf_age[0], 1, 1) @[lsu_bus_buffer.scala 411:109]
-    node _T_2109 = or(_T_2107, _T_2108) @[lsu_bus_buffer.scala 411:97]
-    node _T_2110 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 408:83]
-    node _T_2111 = and(_T_2110, buf_state_en[0]) @[lsu_bus_buffer.scala 408:94]
-    node _T_2112 = eq(buf_state[2], UInt<3>("h01")) @[lsu_bus_buffer.scala 409:20]
-    node _T_2113 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 409:47]
-    node _T_2114 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 409:59]
-    node _T_2115 = and(_T_2113, _T_2114) @[lsu_bus_buffer.scala 409:57]
-    node _T_2116 = or(_T_2112, _T_2115) @[lsu_bus_buffer.scala 409:31]
-    node _T_2117 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 410:23]
-    node _T_2118 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 410:53]
-    node _T_2119 = and(_T_2117, _T_2118) @[lsu_bus_buffer.scala 410:41]
-    node _T_2120 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 410:83]
-    node _T_2121 = and(_T_2119, _T_2120) @[lsu_bus_buffer.scala 410:71]
-    node _T_2122 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 410:104]
-    node _T_2123 = and(_T_2121, _T_2122) @[lsu_bus_buffer.scala 410:92]
-    node _T_2124 = or(_T_2116, _T_2123) @[lsu_bus_buffer.scala 409:86]
-    node _T_2125 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 411:17]
-    node _T_2126 = and(_T_2125, io.ldst_dual_r) @[lsu_bus_buffer.scala 411:35]
-    node _T_2127 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 411:64]
-    node _T_2128 = and(_T_2126, _T_2127) @[lsu_bus_buffer.scala 411:52]
-    node _T_2129 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 411:85]
-    node _T_2130 = and(_T_2128, _T_2129) @[lsu_bus_buffer.scala 411:73]
-    node _T_2131 = or(_T_2124, _T_2130) @[lsu_bus_buffer.scala 410:114]
-    node _T_2132 = and(_T_2111, _T_2131) @[lsu_bus_buffer.scala 408:113]
-    node _T_2133 = bits(buf_age[0], 2, 2) @[lsu_bus_buffer.scala 411:109]
-    node _T_2134 = or(_T_2132, _T_2133) @[lsu_bus_buffer.scala 411:97]
-    node _T_2135 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 408:83]
-    node _T_2136 = and(_T_2135, buf_state_en[0]) @[lsu_bus_buffer.scala 408:94]
-    node _T_2137 = eq(buf_state[3], UInt<3>("h01")) @[lsu_bus_buffer.scala 409:20]
-    node _T_2138 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 409:47]
-    node _T_2139 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 409:59]
-    node _T_2140 = and(_T_2138, _T_2139) @[lsu_bus_buffer.scala 409:57]
-    node _T_2141 = or(_T_2137, _T_2140) @[lsu_bus_buffer.scala 409:31]
-    node _T_2142 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 410:23]
-    node _T_2143 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 410:53]
-    node _T_2144 = and(_T_2142, _T_2143) @[lsu_bus_buffer.scala 410:41]
-    node _T_2145 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 410:83]
-    node _T_2146 = and(_T_2144, _T_2145) @[lsu_bus_buffer.scala 410:71]
-    node _T_2147 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 410:104]
-    node _T_2148 = and(_T_2146, _T_2147) @[lsu_bus_buffer.scala 410:92]
-    node _T_2149 = or(_T_2141, _T_2148) @[lsu_bus_buffer.scala 409:86]
-    node _T_2150 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 411:17]
-    node _T_2151 = and(_T_2150, io.ldst_dual_r) @[lsu_bus_buffer.scala 411:35]
-    node _T_2152 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 411:64]
-    node _T_2153 = and(_T_2151, _T_2152) @[lsu_bus_buffer.scala 411:52]
-    node _T_2154 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 411:85]
-    node _T_2155 = and(_T_2153, _T_2154) @[lsu_bus_buffer.scala 411:73]
-    node _T_2156 = or(_T_2149, _T_2155) @[lsu_bus_buffer.scala 410:114]
-    node _T_2157 = and(_T_2136, _T_2156) @[lsu_bus_buffer.scala 408:113]
-    node _T_2158 = bits(buf_age[0], 3, 3) @[lsu_bus_buffer.scala 411:109]
-    node _T_2159 = or(_T_2157, _T_2158) @[lsu_bus_buffer.scala 411:97]
-    node _T_2160 = cat(_T_2159, _T_2134) @[Cat.scala 29:58]
-    node _T_2161 = cat(_T_2160, _T_2109) @[Cat.scala 29:58]
-    node buf_age_in_0 = cat(_T_2161, _T_2084) @[Cat.scala 29:58]
-    node _T_2162 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 408:83]
-    node _T_2163 = and(_T_2162, buf_state_en[1]) @[lsu_bus_buffer.scala 408:94]
-    node _T_2164 = eq(buf_state[0], UInt<3>("h01")) @[lsu_bus_buffer.scala 409:20]
-    node _T_2165 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 409:47]
-    node _T_2166 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 409:59]
-    node _T_2167 = and(_T_2165, _T_2166) @[lsu_bus_buffer.scala 409:57]
-    node _T_2168 = or(_T_2164, _T_2167) @[lsu_bus_buffer.scala 409:31]
-    node _T_2169 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 410:23]
-    node _T_2170 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 410:53]
-    node _T_2171 = and(_T_2169, _T_2170) @[lsu_bus_buffer.scala 410:41]
-    node _T_2172 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 410:83]
-    node _T_2173 = and(_T_2171, _T_2172) @[lsu_bus_buffer.scala 410:71]
-    node _T_2174 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 410:104]
-    node _T_2175 = and(_T_2173, _T_2174) @[lsu_bus_buffer.scala 410:92]
-    node _T_2176 = or(_T_2168, _T_2175) @[lsu_bus_buffer.scala 409:86]
-    node _T_2177 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 411:17]
-    node _T_2178 = and(_T_2177, io.ldst_dual_r) @[lsu_bus_buffer.scala 411:35]
-    node _T_2179 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 411:64]
-    node _T_2180 = and(_T_2178, _T_2179) @[lsu_bus_buffer.scala 411:52]
-    node _T_2181 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 411:85]
-    node _T_2182 = and(_T_2180, _T_2181) @[lsu_bus_buffer.scala 411:73]
-    node _T_2183 = or(_T_2176, _T_2182) @[lsu_bus_buffer.scala 410:114]
-    node _T_2184 = and(_T_2163, _T_2183) @[lsu_bus_buffer.scala 408:113]
-    node _T_2185 = bits(buf_age[1], 0, 0) @[lsu_bus_buffer.scala 411:109]
-    node _T_2186 = or(_T_2184, _T_2185) @[lsu_bus_buffer.scala 411:97]
-    node _T_2187 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 408:83]
-    node _T_2188 = and(_T_2187, buf_state_en[1]) @[lsu_bus_buffer.scala 408:94]
-    node _T_2189 = eq(buf_state[1], UInt<3>("h01")) @[lsu_bus_buffer.scala 409:20]
-    node _T_2190 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 409:47]
-    node _T_2191 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 409:59]
-    node _T_2192 = and(_T_2190, _T_2191) @[lsu_bus_buffer.scala 409:57]
-    node _T_2193 = or(_T_2189, _T_2192) @[lsu_bus_buffer.scala 409:31]
-    node _T_2194 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 410:23]
-    node _T_2195 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 410:53]
-    node _T_2196 = and(_T_2194, _T_2195) @[lsu_bus_buffer.scala 410:41]
-    node _T_2197 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 410:83]
-    node _T_2198 = and(_T_2196, _T_2197) @[lsu_bus_buffer.scala 410:71]
-    node _T_2199 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 410:104]
-    node _T_2200 = and(_T_2198, _T_2199) @[lsu_bus_buffer.scala 410:92]
-    node _T_2201 = or(_T_2193, _T_2200) @[lsu_bus_buffer.scala 409:86]
-    node _T_2202 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 411:17]
-    node _T_2203 = and(_T_2202, io.ldst_dual_r) @[lsu_bus_buffer.scala 411:35]
-    node _T_2204 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 411:64]
-    node _T_2205 = and(_T_2203, _T_2204) @[lsu_bus_buffer.scala 411:52]
-    node _T_2206 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 411:85]
-    node _T_2207 = and(_T_2205, _T_2206) @[lsu_bus_buffer.scala 411:73]
-    node _T_2208 = or(_T_2201, _T_2207) @[lsu_bus_buffer.scala 410:114]
-    node _T_2209 = and(_T_2188, _T_2208) @[lsu_bus_buffer.scala 408:113]
-    node _T_2210 = bits(buf_age[1], 1, 1) @[lsu_bus_buffer.scala 411:109]
-    node _T_2211 = or(_T_2209, _T_2210) @[lsu_bus_buffer.scala 411:97]
-    node _T_2212 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 408:83]
-    node _T_2213 = and(_T_2212, buf_state_en[1]) @[lsu_bus_buffer.scala 408:94]
-    node _T_2214 = eq(buf_state[2], UInt<3>("h01")) @[lsu_bus_buffer.scala 409:20]
-    node _T_2215 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 409:47]
-    node _T_2216 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 409:59]
-    node _T_2217 = and(_T_2215, _T_2216) @[lsu_bus_buffer.scala 409:57]
-    node _T_2218 = or(_T_2214, _T_2217) @[lsu_bus_buffer.scala 409:31]
-    node _T_2219 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 410:23]
-    node _T_2220 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 410:53]
-    node _T_2221 = and(_T_2219, _T_2220) @[lsu_bus_buffer.scala 410:41]
-    node _T_2222 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 410:83]
-    node _T_2223 = and(_T_2221, _T_2222) @[lsu_bus_buffer.scala 410:71]
-    node _T_2224 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 410:104]
-    node _T_2225 = and(_T_2223, _T_2224) @[lsu_bus_buffer.scala 410:92]
-    node _T_2226 = or(_T_2218, _T_2225) @[lsu_bus_buffer.scala 409:86]
-    node _T_2227 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 411:17]
-    node _T_2228 = and(_T_2227, io.ldst_dual_r) @[lsu_bus_buffer.scala 411:35]
-    node _T_2229 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 411:64]
-    node _T_2230 = and(_T_2228, _T_2229) @[lsu_bus_buffer.scala 411:52]
-    node _T_2231 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 411:85]
-    node _T_2232 = and(_T_2230, _T_2231) @[lsu_bus_buffer.scala 411:73]
-    node _T_2233 = or(_T_2226, _T_2232) @[lsu_bus_buffer.scala 410:114]
-    node _T_2234 = and(_T_2213, _T_2233) @[lsu_bus_buffer.scala 408:113]
-    node _T_2235 = bits(buf_age[1], 2, 2) @[lsu_bus_buffer.scala 411:109]
-    node _T_2236 = or(_T_2234, _T_2235) @[lsu_bus_buffer.scala 411:97]
-    node _T_2237 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 408:83]
-    node _T_2238 = and(_T_2237, buf_state_en[1]) @[lsu_bus_buffer.scala 408:94]
-    node _T_2239 = eq(buf_state[3], UInt<3>("h01")) @[lsu_bus_buffer.scala 409:20]
-    node _T_2240 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 409:47]
-    node _T_2241 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 409:59]
-    node _T_2242 = and(_T_2240, _T_2241) @[lsu_bus_buffer.scala 409:57]
-    node _T_2243 = or(_T_2239, _T_2242) @[lsu_bus_buffer.scala 409:31]
-    node _T_2244 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 410:23]
-    node _T_2245 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 410:53]
-    node _T_2246 = and(_T_2244, _T_2245) @[lsu_bus_buffer.scala 410:41]
-    node _T_2247 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 410:83]
-    node _T_2248 = and(_T_2246, _T_2247) @[lsu_bus_buffer.scala 410:71]
-    node _T_2249 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 410:104]
-    node _T_2250 = and(_T_2248, _T_2249) @[lsu_bus_buffer.scala 410:92]
-    node _T_2251 = or(_T_2243, _T_2250) @[lsu_bus_buffer.scala 409:86]
-    node _T_2252 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 411:17]
-    node _T_2253 = and(_T_2252, io.ldst_dual_r) @[lsu_bus_buffer.scala 411:35]
-    node _T_2254 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 411:64]
-    node _T_2255 = and(_T_2253, _T_2254) @[lsu_bus_buffer.scala 411:52]
-    node _T_2256 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 411:85]
-    node _T_2257 = and(_T_2255, _T_2256) @[lsu_bus_buffer.scala 411:73]
-    node _T_2258 = or(_T_2251, _T_2257) @[lsu_bus_buffer.scala 410:114]
-    node _T_2259 = and(_T_2238, _T_2258) @[lsu_bus_buffer.scala 408:113]
-    node _T_2260 = bits(buf_age[1], 3, 3) @[lsu_bus_buffer.scala 411:109]
-    node _T_2261 = or(_T_2259, _T_2260) @[lsu_bus_buffer.scala 411:97]
-    node _T_2262 = cat(_T_2261, _T_2236) @[Cat.scala 29:58]
-    node _T_2263 = cat(_T_2262, _T_2211) @[Cat.scala 29:58]
-    node buf_age_in_1 = cat(_T_2263, _T_2186) @[Cat.scala 29:58]
-    node _T_2264 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 408:83]
-    node _T_2265 = and(_T_2264, buf_state_en[2]) @[lsu_bus_buffer.scala 408:94]
-    node _T_2266 = eq(buf_state[0], UInt<3>("h01")) @[lsu_bus_buffer.scala 409:20]
-    node _T_2267 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 409:47]
-    node _T_2268 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 409:59]
-    node _T_2269 = and(_T_2267, _T_2268) @[lsu_bus_buffer.scala 409:57]
-    node _T_2270 = or(_T_2266, _T_2269) @[lsu_bus_buffer.scala 409:31]
-    node _T_2271 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 410:23]
-    node _T_2272 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 410:53]
-    node _T_2273 = and(_T_2271, _T_2272) @[lsu_bus_buffer.scala 410:41]
-    node _T_2274 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 410:83]
-    node _T_2275 = and(_T_2273, _T_2274) @[lsu_bus_buffer.scala 410:71]
-    node _T_2276 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 410:104]
-    node _T_2277 = and(_T_2275, _T_2276) @[lsu_bus_buffer.scala 410:92]
-    node _T_2278 = or(_T_2270, _T_2277) @[lsu_bus_buffer.scala 409:86]
-    node _T_2279 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 411:17]
-    node _T_2280 = and(_T_2279, io.ldst_dual_r) @[lsu_bus_buffer.scala 411:35]
-    node _T_2281 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 411:64]
-    node _T_2282 = and(_T_2280, _T_2281) @[lsu_bus_buffer.scala 411:52]
-    node _T_2283 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 411:85]
-    node _T_2284 = and(_T_2282, _T_2283) @[lsu_bus_buffer.scala 411:73]
-    node _T_2285 = or(_T_2278, _T_2284) @[lsu_bus_buffer.scala 410:114]
-    node _T_2286 = and(_T_2265, _T_2285) @[lsu_bus_buffer.scala 408:113]
-    node _T_2287 = bits(buf_age[2], 0, 0) @[lsu_bus_buffer.scala 411:109]
-    node _T_2288 = or(_T_2286, _T_2287) @[lsu_bus_buffer.scala 411:97]
-    node _T_2289 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 408:83]
-    node _T_2290 = and(_T_2289, buf_state_en[2]) @[lsu_bus_buffer.scala 408:94]
-    node _T_2291 = eq(buf_state[1], UInt<3>("h01")) @[lsu_bus_buffer.scala 409:20]
-    node _T_2292 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 409:47]
-    node _T_2293 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 409:59]
-    node _T_2294 = and(_T_2292, _T_2293) @[lsu_bus_buffer.scala 409:57]
-    node _T_2295 = or(_T_2291, _T_2294) @[lsu_bus_buffer.scala 409:31]
-    node _T_2296 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 410:23]
-    node _T_2297 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 410:53]
-    node _T_2298 = and(_T_2296, _T_2297) @[lsu_bus_buffer.scala 410:41]
-    node _T_2299 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 410:83]
-    node _T_2300 = and(_T_2298, _T_2299) @[lsu_bus_buffer.scala 410:71]
-    node _T_2301 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 410:104]
-    node _T_2302 = and(_T_2300, _T_2301) @[lsu_bus_buffer.scala 410:92]
-    node _T_2303 = or(_T_2295, _T_2302) @[lsu_bus_buffer.scala 409:86]
-    node _T_2304 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 411:17]
-    node _T_2305 = and(_T_2304, io.ldst_dual_r) @[lsu_bus_buffer.scala 411:35]
-    node _T_2306 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 411:64]
-    node _T_2307 = and(_T_2305, _T_2306) @[lsu_bus_buffer.scala 411:52]
-    node _T_2308 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 411:85]
-    node _T_2309 = and(_T_2307, _T_2308) @[lsu_bus_buffer.scala 411:73]
-    node _T_2310 = or(_T_2303, _T_2309) @[lsu_bus_buffer.scala 410:114]
-    node _T_2311 = and(_T_2290, _T_2310) @[lsu_bus_buffer.scala 408:113]
-    node _T_2312 = bits(buf_age[2], 1, 1) @[lsu_bus_buffer.scala 411:109]
-    node _T_2313 = or(_T_2311, _T_2312) @[lsu_bus_buffer.scala 411:97]
-    node _T_2314 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 408:83]
-    node _T_2315 = and(_T_2314, buf_state_en[2]) @[lsu_bus_buffer.scala 408:94]
-    node _T_2316 = eq(buf_state[2], UInt<3>("h01")) @[lsu_bus_buffer.scala 409:20]
-    node _T_2317 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 409:47]
-    node _T_2318 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 409:59]
-    node _T_2319 = and(_T_2317, _T_2318) @[lsu_bus_buffer.scala 409:57]
-    node _T_2320 = or(_T_2316, _T_2319) @[lsu_bus_buffer.scala 409:31]
-    node _T_2321 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 410:23]
-    node _T_2322 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 410:53]
-    node _T_2323 = and(_T_2321, _T_2322) @[lsu_bus_buffer.scala 410:41]
-    node _T_2324 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 410:83]
-    node _T_2325 = and(_T_2323, _T_2324) @[lsu_bus_buffer.scala 410:71]
-    node _T_2326 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 410:104]
-    node _T_2327 = and(_T_2325, _T_2326) @[lsu_bus_buffer.scala 410:92]
-    node _T_2328 = or(_T_2320, _T_2327) @[lsu_bus_buffer.scala 409:86]
-    node _T_2329 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 411:17]
-    node _T_2330 = and(_T_2329, io.ldst_dual_r) @[lsu_bus_buffer.scala 411:35]
-    node _T_2331 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 411:64]
-    node _T_2332 = and(_T_2330, _T_2331) @[lsu_bus_buffer.scala 411:52]
-    node _T_2333 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 411:85]
-    node _T_2334 = and(_T_2332, _T_2333) @[lsu_bus_buffer.scala 411:73]
-    node _T_2335 = or(_T_2328, _T_2334) @[lsu_bus_buffer.scala 410:114]
-    node _T_2336 = and(_T_2315, _T_2335) @[lsu_bus_buffer.scala 408:113]
-    node _T_2337 = bits(buf_age[2], 2, 2) @[lsu_bus_buffer.scala 411:109]
-    node _T_2338 = or(_T_2336, _T_2337) @[lsu_bus_buffer.scala 411:97]
-    node _T_2339 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 408:83]
-    node _T_2340 = and(_T_2339, buf_state_en[2]) @[lsu_bus_buffer.scala 408:94]
-    node _T_2341 = eq(buf_state[3], UInt<3>("h01")) @[lsu_bus_buffer.scala 409:20]
-    node _T_2342 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 409:47]
-    node _T_2343 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 409:59]
-    node _T_2344 = and(_T_2342, _T_2343) @[lsu_bus_buffer.scala 409:57]
-    node _T_2345 = or(_T_2341, _T_2344) @[lsu_bus_buffer.scala 409:31]
-    node _T_2346 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 410:23]
-    node _T_2347 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 410:53]
-    node _T_2348 = and(_T_2346, _T_2347) @[lsu_bus_buffer.scala 410:41]
-    node _T_2349 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 410:83]
-    node _T_2350 = and(_T_2348, _T_2349) @[lsu_bus_buffer.scala 410:71]
-    node _T_2351 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 410:104]
-    node _T_2352 = and(_T_2350, _T_2351) @[lsu_bus_buffer.scala 410:92]
-    node _T_2353 = or(_T_2345, _T_2352) @[lsu_bus_buffer.scala 409:86]
-    node _T_2354 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 411:17]
-    node _T_2355 = and(_T_2354, io.ldst_dual_r) @[lsu_bus_buffer.scala 411:35]
-    node _T_2356 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 411:64]
-    node _T_2357 = and(_T_2355, _T_2356) @[lsu_bus_buffer.scala 411:52]
-    node _T_2358 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 411:85]
-    node _T_2359 = and(_T_2357, _T_2358) @[lsu_bus_buffer.scala 411:73]
-    node _T_2360 = or(_T_2353, _T_2359) @[lsu_bus_buffer.scala 410:114]
-    node _T_2361 = and(_T_2340, _T_2360) @[lsu_bus_buffer.scala 408:113]
-    node _T_2362 = bits(buf_age[2], 3, 3) @[lsu_bus_buffer.scala 411:109]
-    node _T_2363 = or(_T_2361, _T_2362) @[lsu_bus_buffer.scala 411:97]
-    node _T_2364 = cat(_T_2363, _T_2338) @[Cat.scala 29:58]
-    node _T_2365 = cat(_T_2364, _T_2313) @[Cat.scala 29:58]
-    node buf_age_in_2 = cat(_T_2365, _T_2288) @[Cat.scala 29:58]
-    node _T_2366 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 408:83]
-    node _T_2367 = and(_T_2366, buf_state_en[3]) @[lsu_bus_buffer.scala 408:94]
-    node _T_2368 = eq(buf_state[0], UInt<3>("h01")) @[lsu_bus_buffer.scala 409:20]
-    node _T_2369 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 409:47]
-    node _T_2370 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 409:59]
-    node _T_2371 = and(_T_2369, _T_2370) @[lsu_bus_buffer.scala 409:57]
-    node _T_2372 = or(_T_2368, _T_2371) @[lsu_bus_buffer.scala 409:31]
-    node _T_2373 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 410:23]
-    node _T_2374 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 410:53]
-    node _T_2375 = and(_T_2373, _T_2374) @[lsu_bus_buffer.scala 410:41]
-    node _T_2376 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 410:83]
-    node _T_2377 = and(_T_2375, _T_2376) @[lsu_bus_buffer.scala 410:71]
-    node _T_2378 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 410:104]
-    node _T_2379 = and(_T_2377, _T_2378) @[lsu_bus_buffer.scala 410:92]
-    node _T_2380 = or(_T_2372, _T_2379) @[lsu_bus_buffer.scala 409:86]
-    node _T_2381 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 411:17]
-    node _T_2382 = and(_T_2381, io.ldst_dual_r) @[lsu_bus_buffer.scala 411:35]
-    node _T_2383 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 411:64]
-    node _T_2384 = and(_T_2382, _T_2383) @[lsu_bus_buffer.scala 411:52]
-    node _T_2385 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 411:85]
-    node _T_2386 = and(_T_2384, _T_2385) @[lsu_bus_buffer.scala 411:73]
-    node _T_2387 = or(_T_2380, _T_2386) @[lsu_bus_buffer.scala 410:114]
-    node _T_2388 = and(_T_2367, _T_2387) @[lsu_bus_buffer.scala 408:113]
-    node _T_2389 = bits(buf_age[3], 0, 0) @[lsu_bus_buffer.scala 411:109]
-    node _T_2390 = or(_T_2388, _T_2389) @[lsu_bus_buffer.scala 411:97]
-    node _T_2391 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 408:83]
-    node _T_2392 = and(_T_2391, buf_state_en[3]) @[lsu_bus_buffer.scala 408:94]
-    node _T_2393 = eq(buf_state[1], UInt<3>("h01")) @[lsu_bus_buffer.scala 409:20]
-    node _T_2394 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 409:47]
-    node _T_2395 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 409:59]
-    node _T_2396 = and(_T_2394, _T_2395) @[lsu_bus_buffer.scala 409:57]
-    node _T_2397 = or(_T_2393, _T_2396) @[lsu_bus_buffer.scala 409:31]
-    node _T_2398 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 410:23]
-    node _T_2399 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 410:53]
-    node _T_2400 = and(_T_2398, _T_2399) @[lsu_bus_buffer.scala 410:41]
-    node _T_2401 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 410:83]
-    node _T_2402 = and(_T_2400, _T_2401) @[lsu_bus_buffer.scala 410:71]
-    node _T_2403 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 410:104]
-    node _T_2404 = and(_T_2402, _T_2403) @[lsu_bus_buffer.scala 410:92]
-    node _T_2405 = or(_T_2397, _T_2404) @[lsu_bus_buffer.scala 409:86]
-    node _T_2406 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 411:17]
-    node _T_2407 = and(_T_2406, io.ldst_dual_r) @[lsu_bus_buffer.scala 411:35]
-    node _T_2408 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 411:64]
-    node _T_2409 = and(_T_2407, _T_2408) @[lsu_bus_buffer.scala 411:52]
-    node _T_2410 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 411:85]
-    node _T_2411 = and(_T_2409, _T_2410) @[lsu_bus_buffer.scala 411:73]
-    node _T_2412 = or(_T_2405, _T_2411) @[lsu_bus_buffer.scala 410:114]
-    node _T_2413 = and(_T_2392, _T_2412) @[lsu_bus_buffer.scala 408:113]
-    node _T_2414 = bits(buf_age[3], 1, 1) @[lsu_bus_buffer.scala 411:109]
-    node _T_2415 = or(_T_2413, _T_2414) @[lsu_bus_buffer.scala 411:97]
-    node _T_2416 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 408:83]
-    node _T_2417 = and(_T_2416, buf_state_en[3]) @[lsu_bus_buffer.scala 408:94]
-    node _T_2418 = eq(buf_state[2], UInt<3>("h01")) @[lsu_bus_buffer.scala 409:20]
-    node _T_2419 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 409:47]
-    node _T_2420 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 409:59]
-    node _T_2421 = and(_T_2419, _T_2420) @[lsu_bus_buffer.scala 409:57]
-    node _T_2422 = or(_T_2418, _T_2421) @[lsu_bus_buffer.scala 409:31]
-    node _T_2423 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 410:23]
-    node _T_2424 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 410:53]
-    node _T_2425 = and(_T_2423, _T_2424) @[lsu_bus_buffer.scala 410:41]
-    node _T_2426 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 410:83]
-    node _T_2427 = and(_T_2425, _T_2426) @[lsu_bus_buffer.scala 410:71]
-    node _T_2428 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 410:104]
-    node _T_2429 = and(_T_2427, _T_2428) @[lsu_bus_buffer.scala 410:92]
-    node _T_2430 = or(_T_2422, _T_2429) @[lsu_bus_buffer.scala 409:86]
-    node _T_2431 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 411:17]
-    node _T_2432 = and(_T_2431, io.ldst_dual_r) @[lsu_bus_buffer.scala 411:35]
-    node _T_2433 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 411:64]
-    node _T_2434 = and(_T_2432, _T_2433) @[lsu_bus_buffer.scala 411:52]
-    node _T_2435 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 411:85]
-    node _T_2436 = and(_T_2434, _T_2435) @[lsu_bus_buffer.scala 411:73]
-    node _T_2437 = or(_T_2430, _T_2436) @[lsu_bus_buffer.scala 410:114]
-    node _T_2438 = and(_T_2417, _T_2437) @[lsu_bus_buffer.scala 408:113]
-    node _T_2439 = bits(buf_age[3], 2, 2) @[lsu_bus_buffer.scala 411:109]
-    node _T_2440 = or(_T_2438, _T_2439) @[lsu_bus_buffer.scala 411:97]
-    node _T_2441 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 408:83]
-    node _T_2442 = and(_T_2441, buf_state_en[3]) @[lsu_bus_buffer.scala 408:94]
-    node _T_2443 = eq(buf_state[3], UInt<3>("h01")) @[lsu_bus_buffer.scala 409:20]
-    node _T_2444 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 409:47]
-    node _T_2445 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 409:59]
-    node _T_2446 = and(_T_2444, _T_2445) @[lsu_bus_buffer.scala 409:57]
-    node _T_2447 = or(_T_2443, _T_2446) @[lsu_bus_buffer.scala 409:31]
-    node _T_2448 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 410:23]
-    node _T_2449 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 410:53]
-    node _T_2450 = and(_T_2448, _T_2449) @[lsu_bus_buffer.scala 410:41]
-    node _T_2451 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 410:83]
-    node _T_2452 = and(_T_2450, _T_2451) @[lsu_bus_buffer.scala 410:71]
-    node _T_2453 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 410:104]
-    node _T_2454 = and(_T_2452, _T_2453) @[lsu_bus_buffer.scala 410:92]
-    node _T_2455 = or(_T_2447, _T_2454) @[lsu_bus_buffer.scala 409:86]
-    node _T_2456 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 411:17]
-    node _T_2457 = and(_T_2456, io.ldst_dual_r) @[lsu_bus_buffer.scala 411:35]
-    node _T_2458 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 411:64]
-    node _T_2459 = and(_T_2457, _T_2458) @[lsu_bus_buffer.scala 411:52]
-    node _T_2460 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 411:85]
-    node _T_2461 = and(_T_2459, _T_2460) @[lsu_bus_buffer.scala 411:73]
-    node _T_2462 = or(_T_2455, _T_2461) @[lsu_bus_buffer.scala 410:114]
-    node _T_2463 = and(_T_2442, _T_2462) @[lsu_bus_buffer.scala 408:113]
-    node _T_2464 = bits(buf_age[3], 3, 3) @[lsu_bus_buffer.scala 411:109]
-    node _T_2465 = or(_T_2463, _T_2464) @[lsu_bus_buffer.scala 411:97]
-    node _T_2466 = cat(_T_2465, _T_2440) @[Cat.scala 29:58]
-    node _T_2467 = cat(_T_2466, _T_2415) @[Cat.scala 29:58]
-    node buf_age_in_3 = cat(_T_2467, _T_2390) @[Cat.scala 29:58]
-    wire buf_ageQ : UInt<4>[4] @[lsu_bus_buffer.scala 412:22]
-    buf_ageQ[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 413:12]
-    buf_ageQ[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 413:12]
-    buf_ageQ[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 413:12]
-    buf_ageQ[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 413:12]
-    node _T_2468 = bits(buf_ageQ[0], 0, 0) @[lsu_bus_buffer.scala 414:72]
-    node _T_2469 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 414:93]
-    node _T_2470 = and(_T_2469, buf_cmd_state_bus_en[0]) @[lsu_bus_buffer.scala 414:103]
-    node _T_2471 = eq(_T_2470, UInt<1>("h00")) @[lsu_bus_buffer.scala 414:78]
-    node _T_2472 = and(_T_2468, _T_2471) @[lsu_bus_buffer.scala 414:76]
-    node _T_2473 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 414:140]
-    node _T_2474 = and(_T_2472, _T_2473) @[lsu_bus_buffer.scala 414:138]
-    node _T_2475 = bits(buf_ageQ[0], 1, 1) @[lsu_bus_buffer.scala 414:72]
-    node _T_2476 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 414:93]
-    node _T_2477 = and(_T_2476, buf_cmd_state_bus_en[1]) @[lsu_bus_buffer.scala 414:103]
-    node _T_2478 = eq(_T_2477, UInt<1>("h00")) @[lsu_bus_buffer.scala 414:78]
-    node _T_2479 = and(_T_2475, _T_2478) @[lsu_bus_buffer.scala 414:76]
-    node _T_2480 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 414:140]
-    node _T_2481 = and(_T_2479, _T_2480) @[lsu_bus_buffer.scala 414:138]
-    node _T_2482 = bits(buf_ageQ[0], 2, 2) @[lsu_bus_buffer.scala 414:72]
-    node _T_2483 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 414:93]
-    node _T_2484 = and(_T_2483, buf_cmd_state_bus_en[2]) @[lsu_bus_buffer.scala 414:103]
-    node _T_2485 = eq(_T_2484, UInt<1>("h00")) @[lsu_bus_buffer.scala 414:78]
-    node _T_2486 = and(_T_2482, _T_2485) @[lsu_bus_buffer.scala 414:76]
-    node _T_2487 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 414:140]
-    node _T_2488 = and(_T_2486, _T_2487) @[lsu_bus_buffer.scala 414:138]
-    node _T_2489 = bits(buf_ageQ[0], 3, 3) @[lsu_bus_buffer.scala 414:72]
-    node _T_2490 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 414:93]
-    node _T_2491 = and(_T_2490, buf_cmd_state_bus_en[3]) @[lsu_bus_buffer.scala 414:103]
-    node _T_2492 = eq(_T_2491, UInt<1>("h00")) @[lsu_bus_buffer.scala 414:78]
-    node _T_2493 = and(_T_2489, _T_2492) @[lsu_bus_buffer.scala 414:76]
-    node _T_2494 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 414:140]
-    node _T_2495 = and(_T_2493, _T_2494) @[lsu_bus_buffer.scala 414:138]
-    node _T_2496 = cat(_T_2495, _T_2488) @[Cat.scala 29:58]
-    node _T_2497 = cat(_T_2496, _T_2481) @[Cat.scala 29:58]
-    node _T_2498 = cat(_T_2497, _T_2474) @[Cat.scala 29:58]
-    node _T_2499 = bits(buf_ageQ[1], 0, 0) @[lsu_bus_buffer.scala 414:72]
-    node _T_2500 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 414:93]
-    node _T_2501 = and(_T_2500, buf_cmd_state_bus_en[0]) @[lsu_bus_buffer.scala 414:103]
-    node _T_2502 = eq(_T_2501, UInt<1>("h00")) @[lsu_bus_buffer.scala 414:78]
-    node _T_2503 = and(_T_2499, _T_2502) @[lsu_bus_buffer.scala 414:76]
-    node _T_2504 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 414:140]
-    node _T_2505 = and(_T_2503, _T_2504) @[lsu_bus_buffer.scala 414:138]
-    node _T_2506 = bits(buf_ageQ[1], 1, 1) @[lsu_bus_buffer.scala 414:72]
-    node _T_2507 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 414:93]
-    node _T_2508 = and(_T_2507, buf_cmd_state_bus_en[1]) @[lsu_bus_buffer.scala 414:103]
-    node _T_2509 = eq(_T_2508, UInt<1>("h00")) @[lsu_bus_buffer.scala 414:78]
-    node _T_2510 = and(_T_2506, _T_2509) @[lsu_bus_buffer.scala 414:76]
-    node _T_2511 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 414:140]
-    node _T_2512 = and(_T_2510, _T_2511) @[lsu_bus_buffer.scala 414:138]
-    node _T_2513 = bits(buf_ageQ[1], 2, 2) @[lsu_bus_buffer.scala 414:72]
-    node _T_2514 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 414:93]
-    node _T_2515 = and(_T_2514, buf_cmd_state_bus_en[2]) @[lsu_bus_buffer.scala 414:103]
-    node _T_2516 = eq(_T_2515, UInt<1>("h00")) @[lsu_bus_buffer.scala 414:78]
-    node _T_2517 = and(_T_2513, _T_2516) @[lsu_bus_buffer.scala 414:76]
-    node _T_2518 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 414:140]
-    node _T_2519 = and(_T_2517, _T_2518) @[lsu_bus_buffer.scala 414:138]
-    node _T_2520 = bits(buf_ageQ[1], 3, 3) @[lsu_bus_buffer.scala 414:72]
-    node _T_2521 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 414:93]
-    node _T_2522 = and(_T_2521, buf_cmd_state_bus_en[3]) @[lsu_bus_buffer.scala 414:103]
-    node _T_2523 = eq(_T_2522, UInt<1>("h00")) @[lsu_bus_buffer.scala 414:78]
-    node _T_2524 = and(_T_2520, _T_2523) @[lsu_bus_buffer.scala 414:76]
-    node _T_2525 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 414:140]
-    node _T_2526 = and(_T_2524, _T_2525) @[lsu_bus_buffer.scala 414:138]
-    node _T_2527 = cat(_T_2526, _T_2519) @[Cat.scala 29:58]
-    node _T_2528 = cat(_T_2527, _T_2512) @[Cat.scala 29:58]
-    node _T_2529 = cat(_T_2528, _T_2505) @[Cat.scala 29:58]
-    node _T_2530 = bits(buf_ageQ[2], 0, 0) @[lsu_bus_buffer.scala 414:72]
-    node _T_2531 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 414:93]
-    node _T_2532 = and(_T_2531, buf_cmd_state_bus_en[0]) @[lsu_bus_buffer.scala 414:103]
-    node _T_2533 = eq(_T_2532, UInt<1>("h00")) @[lsu_bus_buffer.scala 414:78]
-    node _T_2534 = and(_T_2530, _T_2533) @[lsu_bus_buffer.scala 414:76]
-    node _T_2535 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 414:140]
-    node _T_2536 = and(_T_2534, _T_2535) @[lsu_bus_buffer.scala 414:138]
-    node _T_2537 = bits(buf_ageQ[2], 1, 1) @[lsu_bus_buffer.scala 414:72]
-    node _T_2538 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 414:93]
-    node _T_2539 = and(_T_2538, buf_cmd_state_bus_en[1]) @[lsu_bus_buffer.scala 414:103]
-    node _T_2540 = eq(_T_2539, UInt<1>("h00")) @[lsu_bus_buffer.scala 414:78]
-    node _T_2541 = and(_T_2537, _T_2540) @[lsu_bus_buffer.scala 414:76]
-    node _T_2542 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 414:140]
-    node _T_2543 = and(_T_2541, _T_2542) @[lsu_bus_buffer.scala 414:138]
-    node _T_2544 = bits(buf_ageQ[2], 2, 2) @[lsu_bus_buffer.scala 414:72]
-    node _T_2545 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 414:93]
-    node _T_2546 = and(_T_2545, buf_cmd_state_bus_en[2]) @[lsu_bus_buffer.scala 414:103]
-    node _T_2547 = eq(_T_2546, UInt<1>("h00")) @[lsu_bus_buffer.scala 414:78]
-    node _T_2548 = and(_T_2544, _T_2547) @[lsu_bus_buffer.scala 414:76]
-    node _T_2549 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 414:140]
-    node _T_2550 = and(_T_2548, _T_2549) @[lsu_bus_buffer.scala 414:138]
-    node _T_2551 = bits(buf_ageQ[2], 3, 3) @[lsu_bus_buffer.scala 414:72]
-    node _T_2552 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 414:93]
-    node _T_2553 = and(_T_2552, buf_cmd_state_bus_en[3]) @[lsu_bus_buffer.scala 414:103]
-    node _T_2554 = eq(_T_2553, UInt<1>("h00")) @[lsu_bus_buffer.scala 414:78]
-    node _T_2555 = and(_T_2551, _T_2554) @[lsu_bus_buffer.scala 414:76]
-    node _T_2556 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 414:140]
-    node _T_2557 = and(_T_2555, _T_2556) @[lsu_bus_buffer.scala 414:138]
-    node _T_2558 = cat(_T_2557, _T_2550) @[Cat.scala 29:58]
-    node _T_2559 = cat(_T_2558, _T_2543) @[Cat.scala 29:58]
-    node _T_2560 = cat(_T_2559, _T_2536) @[Cat.scala 29:58]
-    node _T_2561 = bits(buf_ageQ[3], 0, 0) @[lsu_bus_buffer.scala 414:72]
-    node _T_2562 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 414:93]
-    node _T_2563 = and(_T_2562, buf_cmd_state_bus_en[0]) @[lsu_bus_buffer.scala 414:103]
-    node _T_2564 = eq(_T_2563, UInt<1>("h00")) @[lsu_bus_buffer.scala 414:78]
-    node _T_2565 = and(_T_2561, _T_2564) @[lsu_bus_buffer.scala 414:76]
-    node _T_2566 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 414:140]
-    node _T_2567 = and(_T_2565, _T_2566) @[lsu_bus_buffer.scala 414:138]
-    node _T_2568 = bits(buf_ageQ[3], 1, 1) @[lsu_bus_buffer.scala 414:72]
-    node _T_2569 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 414:93]
-    node _T_2570 = and(_T_2569, buf_cmd_state_bus_en[1]) @[lsu_bus_buffer.scala 414:103]
-    node _T_2571 = eq(_T_2570, UInt<1>("h00")) @[lsu_bus_buffer.scala 414:78]
-    node _T_2572 = and(_T_2568, _T_2571) @[lsu_bus_buffer.scala 414:76]
-    node _T_2573 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 414:140]
-    node _T_2574 = and(_T_2572, _T_2573) @[lsu_bus_buffer.scala 414:138]
-    node _T_2575 = bits(buf_ageQ[3], 2, 2) @[lsu_bus_buffer.scala 414:72]
-    node _T_2576 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 414:93]
-    node _T_2577 = and(_T_2576, buf_cmd_state_bus_en[2]) @[lsu_bus_buffer.scala 414:103]
-    node _T_2578 = eq(_T_2577, UInt<1>("h00")) @[lsu_bus_buffer.scala 414:78]
-    node _T_2579 = and(_T_2575, _T_2578) @[lsu_bus_buffer.scala 414:76]
-    node _T_2580 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 414:140]
-    node _T_2581 = and(_T_2579, _T_2580) @[lsu_bus_buffer.scala 414:138]
-    node _T_2582 = bits(buf_ageQ[3], 3, 3) @[lsu_bus_buffer.scala 414:72]
-    node _T_2583 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 414:93]
-    node _T_2584 = and(_T_2583, buf_cmd_state_bus_en[3]) @[lsu_bus_buffer.scala 414:103]
-    node _T_2585 = eq(_T_2584, UInt<1>("h00")) @[lsu_bus_buffer.scala 414:78]
-    node _T_2586 = and(_T_2582, _T_2585) @[lsu_bus_buffer.scala 414:76]
-    node _T_2587 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 414:140]
-    node _T_2588 = and(_T_2586, _T_2587) @[lsu_bus_buffer.scala 414:138]
-    node _T_2589 = cat(_T_2588, _T_2581) @[Cat.scala 29:58]
-    node _T_2590 = cat(_T_2589, _T_2574) @[Cat.scala 29:58]
-    node _T_2591 = cat(_T_2590, _T_2567) @[Cat.scala 29:58]
-    buf_age[0] <= _T_2498 @[lsu_bus_buffer.scala 414:11]
-    buf_age[1] <= _T_2529 @[lsu_bus_buffer.scala 414:11]
-    buf_age[2] <= _T_2560 @[lsu_bus_buffer.scala 414:11]
-    buf_age[3] <= _T_2591 @[lsu_bus_buffer.scala 414:11]
-    node _T_2592 = eq(UInt<1>("h00"), UInt<1>("h00")) @[lsu_bus_buffer.scala 415:76]
-    node _T_2593 = bits(buf_age[0], 0, 0) @[lsu_bus_buffer.scala 415:100]
-    node _T_2594 = eq(_T_2593, UInt<1>("h00")) @[lsu_bus_buffer.scala 415:89]
-    node _T_2595 = neq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 415:119]
-    node _T_2596 = and(_T_2594, _T_2595) @[lsu_bus_buffer.scala 415:104]
-    node _T_2597 = mux(_T_2592, UInt<1>("h00"), _T_2596) @[lsu_bus_buffer.scala 415:72]
-    node _T_2598 = eq(UInt<1>("h00"), UInt<1>("h01")) @[lsu_bus_buffer.scala 415:76]
-    node _T_2599 = bits(buf_age[0], 1, 1) @[lsu_bus_buffer.scala 415:100]
-    node _T_2600 = eq(_T_2599, UInt<1>("h00")) @[lsu_bus_buffer.scala 415:89]
-    node _T_2601 = neq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 415:119]
-    node _T_2602 = and(_T_2600, _T_2601) @[lsu_bus_buffer.scala 415:104]
-    node _T_2603 = mux(_T_2598, UInt<1>("h00"), _T_2602) @[lsu_bus_buffer.scala 415:72]
-    node _T_2604 = eq(UInt<1>("h00"), UInt<2>("h02")) @[lsu_bus_buffer.scala 415:76]
-    node _T_2605 = bits(buf_age[0], 2, 2) @[lsu_bus_buffer.scala 415:100]
-    node _T_2606 = eq(_T_2605, UInt<1>("h00")) @[lsu_bus_buffer.scala 415:89]
-    node _T_2607 = neq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 415:119]
-    node _T_2608 = and(_T_2606, _T_2607) @[lsu_bus_buffer.scala 415:104]
-    node _T_2609 = mux(_T_2604, UInt<1>("h00"), _T_2608) @[lsu_bus_buffer.scala 415:72]
-    node _T_2610 = eq(UInt<1>("h00"), UInt<2>("h03")) @[lsu_bus_buffer.scala 415:76]
-    node _T_2611 = bits(buf_age[0], 3, 3) @[lsu_bus_buffer.scala 415:100]
-    node _T_2612 = eq(_T_2611, UInt<1>("h00")) @[lsu_bus_buffer.scala 415:89]
-    node _T_2613 = neq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 415:119]
-    node _T_2614 = and(_T_2612, _T_2613) @[lsu_bus_buffer.scala 415:104]
-    node _T_2615 = mux(_T_2610, UInt<1>("h00"), _T_2614) @[lsu_bus_buffer.scala 415:72]
-    node _T_2616 = cat(_T_2615, _T_2609) @[Cat.scala 29:58]
-    node _T_2617 = cat(_T_2616, _T_2603) @[Cat.scala 29:58]
-    node _T_2618 = cat(_T_2617, _T_2597) @[Cat.scala 29:58]
-    node _T_2619 = eq(UInt<1>("h01"), UInt<1>("h00")) @[lsu_bus_buffer.scala 415:76]
-    node _T_2620 = bits(buf_age[1], 0, 0) @[lsu_bus_buffer.scala 415:100]
-    node _T_2621 = eq(_T_2620, UInt<1>("h00")) @[lsu_bus_buffer.scala 415:89]
-    node _T_2622 = neq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 415:119]
-    node _T_2623 = and(_T_2621, _T_2622) @[lsu_bus_buffer.scala 415:104]
-    node _T_2624 = mux(_T_2619, UInt<1>("h00"), _T_2623) @[lsu_bus_buffer.scala 415:72]
-    node _T_2625 = eq(UInt<1>("h01"), UInt<1>("h01")) @[lsu_bus_buffer.scala 415:76]
-    node _T_2626 = bits(buf_age[1], 1, 1) @[lsu_bus_buffer.scala 415:100]
-    node _T_2627 = eq(_T_2626, UInt<1>("h00")) @[lsu_bus_buffer.scala 415:89]
-    node _T_2628 = neq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 415:119]
-    node _T_2629 = and(_T_2627, _T_2628) @[lsu_bus_buffer.scala 415:104]
-    node _T_2630 = mux(_T_2625, UInt<1>("h00"), _T_2629) @[lsu_bus_buffer.scala 415:72]
-    node _T_2631 = eq(UInt<1>("h01"), UInt<2>("h02")) @[lsu_bus_buffer.scala 415:76]
-    node _T_2632 = bits(buf_age[1], 2, 2) @[lsu_bus_buffer.scala 415:100]
-    node _T_2633 = eq(_T_2632, UInt<1>("h00")) @[lsu_bus_buffer.scala 415:89]
-    node _T_2634 = neq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 415:119]
-    node _T_2635 = and(_T_2633, _T_2634) @[lsu_bus_buffer.scala 415:104]
-    node _T_2636 = mux(_T_2631, UInt<1>("h00"), _T_2635) @[lsu_bus_buffer.scala 415:72]
-    node _T_2637 = eq(UInt<1>("h01"), UInt<2>("h03")) @[lsu_bus_buffer.scala 415:76]
-    node _T_2638 = bits(buf_age[1], 3, 3) @[lsu_bus_buffer.scala 415:100]
-    node _T_2639 = eq(_T_2638, UInt<1>("h00")) @[lsu_bus_buffer.scala 415:89]
-    node _T_2640 = neq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 415:119]
-    node _T_2641 = and(_T_2639, _T_2640) @[lsu_bus_buffer.scala 415:104]
-    node _T_2642 = mux(_T_2637, UInt<1>("h00"), _T_2641) @[lsu_bus_buffer.scala 415:72]
-    node _T_2643 = cat(_T_2642, _T_2636) @[Cat.scala 29:58]
-    node _T_2644 = cat(_T_2643, _T_2630) @[Cat.scala 29:58]
-    node _T_2645 = cat(_T_2644, _T_2624) @[Cat.scala 29:58]
-    node _T_2646 = eq(UInt<2>("h02"), UInt<1>("h00")) @[lsu_bus_buffer.scala 415:76]
-    node _T_2647 = bits(buf_age[2], 0, 0) @[lsu_bus_buffer.scala 415:100]
-    node _T_2648 = eq(_T_2647, UInt<1>("h00")) @[lsu_bus_buffer.scala 415:89]
-    node _T_2649 = neq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 415:119]
-    node _T_2650 = and(_T_2648, _T_2649) @[lsu_bus_buffer.scala 415:104]
-    node _T_2651 = mux(_T_2646, UInt<1>("h00"), _T_2650) @[lsu_bus_buffer.scala 415:72]
-    node _T_2652 = eq(UInt<2>("h02"), UInt<1>("h01")) @[lsu_bus_buffer.scala 415:76]
-    node _T_2653 = bits(buf_age[2], 1, 1) @[lsu_bus_buffer.scala 415:100]
-    node _T_2654 = eq(_T_2653, UInt<1>("h00")) @[lsu_bus_buffer.scala 415:89]
-    node _T_2655 = neq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 415:119]
-    node _T_2656 = and(_T_2654, _T_2655) @[lsu_bus_buffer.scala 415:104]
-    node _T_2657 = mux(_T_2652, UInt<1>("h00"), _T_2656) @[lsu_bus_buffer.scala 415:72]
-    node _T_2658 = eq(UInt<2>("h02"), UInt<2>("h02")) @[lsu_bus_buffer.scala 415:76]
-    node _T_2659 = bits(buf_age[2], 2, 2) @[lsu_bus_buffer.scala 415:100]
-    node _T_2660 = eq(_T_2659, UInt<1>("h00")) @[lsu_bus_buffer.scala 415:89]
-    node _T_2661 = neq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 415:119]
-    node _T_2662 = and(_T_2660, _T_2661) @[lsu_bus_buffer.scala 415:104]
-    node _T_2663 = mux(_T_2658, UInt<1>("h00"), _T_2662) @[lsu_bus_buffer.scala 415:72]
-    node _T_2664 = eq(UInt<2>("h02"), UInt<2>("h03")) @[lsu_bus_buffer.scala 415:76]
-    node _T_2665 = bits(buf_age[2], 3, 3) @[lsu_bus_buffer.scala 415:100]
-    node _T_2666 = eq(_T_2665, UInt<1>("h00")) @[lsu_bus_buffer.scala 415:89]
-    node _T_2667 = neq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 415:119]
-    node _T_2668 = and(_T_2666, _T_2667) @[lsu_bus_buffer.scala 415:104]
-    node _T_2669 = mux(_T_2664, UInt<1>("h00"), _T_2668) @[lsu_bus_buffer.scala 415:72]
-    node _T_2670 = cat(_T_2669, _T_2663) @[Cat.scala 29:58]
-    node _T_2671 = cat(_T_2670, _T_2657) @[Cat.scala 29:58]
-    node _T_2672 = cat(_T_2671, _T_2651) @[Cat.scala 29:58]
-    node _T_2673 = eq(UInt<2>("h03"), UInt<1>("h00")) @[lsu_bus_buffer.scala 415:76]
-    node _T_2674 = bits(buf_age[3], 0, 0) @[lsu_bus_buffer.scala 415:100]
-    node _T_2675 = eq(_T_2674, UInt<1>("h00")) @[lsu_bus_buffer.scala 415:89]
-    node _T_2676 = neq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 415:119]
-    node _T_2677 = and(_T_2675, _T_2676) @[lsu_bus_buffer.scala 415:104]
-    node _T_2678 = mux(_T_2673, UInt<1>("h00"), _T_2677) @[lsu_bus_buffer.scala 415:72]
-    node _T_2679 = eq(UInt<2>("h03"), UInt<1>("h01")) @[lsu_bus_buffer.scala 415:76]
-    node _T_2680 = bits(buf_age[3], 1, 1) @[lsu_bus_buffer.scala 415:100]
-    node _T_2681 = eq(_T_2680, UInt<1>("h00")) @[lsu_bus_buffer.scala 415:89]
-    node _T_2682 = neq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 415:119]
-    node _T_2683 = and(_T_2681, _T_2682) @[lsu_bus_buffer.scala 415:104]
-    node _T_2684 = mux(_T_2679, UInt<1>("h00"), _T_2683) @[lsu_bus_buffer.scala 415:72]
-    node _T_2685 = eq(UInt<2>("h03"), UInt<2>("h02")) @[lsu_bus_buffer.scala 415:76]
-    node _T_2686 = bits(buf_age[3], 2, 2) @[lsu_bus_buffer.scala 415:100]
-    node _T_2687 = eq(_T_2686, UInt<1>("h00")) @[lsu_bus_buffer.scala 415:89]
-    node _T_2688 = neq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 415:119]
-    node _T_2689 = and(_T_2687, _T_2688) @[lsu_bus_buffer.scala 415:104]
-    node _T_2690 = mux(_T_2685, UInt<1>("h00"), _T_2689) @[lsu_bus_buffer.scala 415:72]
-    node _T_2691 = eq(UInt<2>("h03"), UInt<2>("h03")) @[lsu_bus_buffer.scala 415:76]
-    node _T_2692 = bits(buf_age[3], 3, 3) @[lsu_bus_buffer.scala 415:100]
-    node _T_2693 = eq(_T_2692, UInt<1>("h00")) @[lsu_bus_buffer.scala 415:89]
-    node _T_2694 = neq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 415:119]
-    node _T_2695 = and(_T_2693, _T_2694) @[lsu_bus_buffer.scala 415:104]
-    node _T_2696 = mux(_T_2691, UInt<1>("h00"), _T_2695) @[lsu_bus_buffer.scala 415:72]
-    node _T_2697 = cat(_T_2696, _T_2690) @[Cat.scala 29:58]
-    node _T_2698 = cat(_T_2697, _T_2684) @[Cat.scala 29:58]
-    node _T_2699 = cat(_T_2698, _T_2678) @[Cat.scala 29:58]
-    buf_age_younger[0] <= _T_2618 @[lsu_bus_buffer.scala 415:19]
-    buf_age_younger[1] <= _T_2645 @[lsu_bus_buffer.scala 415:19]
-    buf_age_younger[2] <= _T_2672 @[lsu_bus_buffer.scala 415:19]
-    buf_age_younger[3] <= _T_2699 @[lsu_bus_buffer.scala 415:19]
-    node _T_2700 = bits(buf_rspageQ[0], 0, 0) @[lsu_bus_buffer.scala 416:83]
-    node _T_2701 = eq(buf_state[0], UInt<3>("h05")) @[lsu_bus_buffer.scala 416:102]
-    node _T_2702 = and(_T_2700, _T_2701) @[lsu_bus_buffer.scala 416:87]
-    node _T_2703 = bits(buf_rspageQ[0], 1, 1) @[lsu_bus_buffer.scala 416:83]
-    node _T_2704 = eq(buf_state[1], UInt<3>("h05")) @[lsu_bus_buffer.scala 416:102]
-    node _T_2705 = and(_T_2703, _T_2704) @[lsu_bus_buffer.scala 416:87]
-    node _T_2706 = bits(buf_rspageQ[0], 2, 2) @[lsu_bus_buffer.scala 416:83]
-    node _T_2707 = eq(buf_state[2], UInt<3>("h05")) @[lsu_bus_buffer.scala 416:102]
-    node _T_2708 = and(_T_2706, _T_2707) @[lsu_bus_buffer.scala 416:87]
-    node _T_2709 = bits(buf_rspageQ[0], 3, 3) @[lsu_bus_buffer.scala 416:83]
-    node _T_2710 = eq(buf_state[3], UInt<3>("h05")) @[lsu_bus_buffer.scala 416:102]
-    node _T_2711 = and(_T_2709, _T_2710) @[lsu_bus_buffer.scala 416:87]
-    node _T_2712 = cat(_T_2711, _T_2708) @[Cat.scala 29:58]
-    node _T_2713 = cat(_T_2712, _T_2705) @[Cat.scala 29:58]
-    node _T_2714 = cat(_T_2713, _T_2702) @[Cat.scala 29:58]
-    node _T_2715 = bits(buf_rspageQ[1], 0, 0) @[lsu_bus_buffer.scala 416:83]
-    node _T_2716 = eq(buf_state[0], UInt<3>("h05")) @[lsu_bus_buffer.scala 416:102]
-    node _T_2717 = and(_T_2715, _T_2716) @[lsu_bus_buffer.scala 416:87]
-    node _T_2718 = bits(buf_rspageQ[1], 1, 1) @[lsu_bus_buffer.scala 416:83]
-    node _T_2719 = eq(buf_state[1], UInt<3>("h05")) @[lsu_bus_buffer.scala 416:102]
-    node _T_2720 = and(_T_2718, _T_2719) @[lsu_bus_buffer.scala 416:87]
-    node _T_2721 = bits(buf_rspageQ[1], 2, 2) @[lsu_bus_buffer.scala 416:83]
-    node _T_2722 = eq(buf_state[2], UInt<3>("h05")) @[lsu_bus_buffer.scala 416:102]
-    node _T_2723 = and(_T_2721, _T_2722) @[lsu_bus_buffer.scala 416:87]
-    node _T_2724 = bits(buf_rspageQ[1], 3, 3) @[lsu_bus_buffer.scala 416:83]
-    node _T_2725 = eq(buf_state[3], UInt<3>("h05")) @[lsu_bus_buffer.scala 416:102]
-    node _T_2726 = and(_T_2724, _T_2725) @[lsu_bus_buffer.scala 416:87]
-    node _T_2727 = cat(_T_2726, _T_2723) @[Cat.scala 29:58]
-    node _T_2728 = cat(_T_2727, _T_2720) @[Cat.scala 29:58]
-    node _T_2729 = cat(_T_2728, _T_2717) @[Cat.scala 29:58]
-    node _T_2730 = bits(buf_rspageQ[2], 0, 0) @[lsu_bus_buffer.scala 416:83]
-    node _T_2731 = eq(buf_state[0], UInt<3>("h05")) @[lsu_bus_buffer.scala 416:102]
-    node _T_2732 = and(_T_2730, _T_2731) @[lsu_bus_buffer.scala 416:87]
-    node _T_2733 = bits(buf_rspageQ[2], 1, 1) @[lsu_bus_buffer.scala 416:83]
-    node _T_2734 = eq(buf_state[1], UInt<3>("h05")) @[lsu_bus_buffer.scala 416:102]
-    node _T_2735 = and(_T_2733, _T_2734) @[lsu_bus_buffer.scala 416:87]
-    node _T_2736 = bits(buf_rspageQ[2], 2, 2) @[lsu_bus_buffer.scala 416:83]
-    node _T_2737 = eq(buf_state[2], UInt<3>("h05")) @[lsu_bus_buffer.scala 416:102]
-    node _T_2738 = and(_T_2736, _T_2737) @[lsu_bus_buffer.scala 416:87]
-    node _T_2739 = bits(buf_rspageQ[2], 3, 3) @[lsu_bus_buffer.scala 416:83]
-    node _T_2740 = eq(buf_state[3], UInt<3>("h05")) @[lsu_bus_buffer.scala 416:102]
-    node _T_2741 = and(_T_2739, _T_2740) @[lsu_bus_buffer.scala 416:87]
-    node _T_2742 = cat(_T_2741, _T_2738) @[Cat.scala 29:58]
-    node _T_2743 = cat(_T_2742, _T_2735) @[Cat.scala 29:58]
-    node _T_2744 = cat(_T_2743, _T_2732) @[Cat.scala 29:58]
-    node _T_2745 = bits(buf_rspageQ[3], 0, 0) @[lsu_bus_buffer.scala 416:83]
-    node _T_2746 = eq(buf_state[0], UInt<3>("h05")) @[lsu_bus_buffer.scala 416:102]
-    node _T_2747 = and(_T_2745, _T_2746) @[lsu_bus_buffer.scala 416:87]
-    node _T_2748 = bits(buf_rspageQ[3], 1, 1) @[lsu_bus_buffer.scala 416:83]
-    node _T_2749 = eq(buf_state[1], UInt<3>("h05")) @[lsu_bus_buffer.scala 416:102]
-    node _T_2750 = and(_T_2748, _T_2749) @[lsu_bus_buffer.scala 416:87]
-    node _T_2751 = bits(buf_rspageQ[3], 2, 2) @[lsu_bus_buffer.scala 416:83]
-    node _T_2752 = eq(buf_state[2], UInt<3>("h05")) @[lsu_bus_buffer.scala 416:102]
-    node _T_2753 = and(_T_2751, _T_2752) @[lsu_bus_buffer.scala 416:87]
-    node _T_2754 = bits(buf_rspageQ[3], 3, 3) @[lsu_bus_buffer.scala 416:83]
-    node _T_2755 = eq(buf_state[3], UInt<3>("h05")) @[lsu_bus_buffer.scala 416:102]
-    node _T_2756 = and(_T_2754, _T_2755) @[lsu_bus_buffer.scala 416:87]
-    node _T_2757 = cat(_T_2756, _T_2753) @[Cat.scala 29:58]
-    node _T_2758 = cat(_T_2757, _T_2750) @[Cat.scala 29:58]
-    node _T_2759 = cat(_T_2758, _T_2747) @[Cat.scala 29:58]
-    buf_rsp_pickage[0] <= _T_2714 @[lsu_bus_buffer.scala 416:19]
-    buf_rsp_pickage[1] <= _T_2729 @[lsu_bus_buffer.scala 416:19]
-    buf_rsp_pickage[2] <= _T_2744 @[lsu_bus_buffer.scala 416:19]
-    buf_rsp_pickage[3] <= _T_2759 @[lsu_bus_buffer.scala 416:19]
-    node _T_2760 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:82]
-    node _T_2761 = and(_T_2760, buf_state_en[0]) @[lsu_bus_buffer.scala 418:93]
-    node _T_2762 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 419:21]
-    node _T_2763 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 419:47]
-    node _T_2764 = or(_T_2762, _T_2763) @[lsu_bus_buffer.scala 419:32]
-    node _T_2765 = eq(_T_2764, UInt<1>("h00")) @[lsu_bus_buffer.scala 419:6]
-    node _T_2766 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 420:23]
-    node _T_2767 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 420:53]
-    node _T_2768 = and(_T_2766, _T_2767) @[lsu_bus_buffer.scala 420:41]
-    node _T_2769 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 420:82]
-    node _T_2770 = and(_T_2768, _T_2769) @[lsu_bus_buffer.scala 420:71]
-    node _T_2771 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 420:101]
-    node _T_2772 = and(_T_2770, _T_2771) @[lsu_bus_buffer.scala 420:90]
-    node _T_2773 = or(_T_2765, _T_2772) @[lsu_bus_buffer.scala 419:59]
-    node _T_2774 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 421:17]
-    node _T_2775 = and(_T_2774, io.ldst_dual_r) @[lsu_bus_buffer.scala 421:35]
-    node _T_2776 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 421:63]
-    node _T_2777 = and(_T_2775, _T_2776) @[lsu_bus_buffer.scala 421:52]
-    node _T_2778 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 421:82]
-    node _T_2779 = and(_T_2777, _T_2778) @[lsu_bus_buffer.scala 421:71]
-    node _T_2780 = or(_T_2773, _T_2779) @[lsu_bus_buffer.scala 420:110]
-    node _T_2781 = and(_T_2761, _T_2780) @[lsu_bus_buffer.scala 418:112]
-    node _T_2782 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:82]
-    node _T_2783 = and(_T_2782, buf_state_en[0]) @[lsu_bus_buffer.scala 418:93]
-    node _T_2784 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 419:21]
-    node _T_2785 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 419:47]
-    node _T_2786 = or(_T_2784, _T_2785) @[lsu_bus_buffer.scala 419:32]
-    node _T_2787 = eq(_T_2786, UInt<1>("h00")) @[lsu_bus_buffer.scala 419:6]
-    node _T_2788 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 420:23]
-    node _T_2789 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 420:53]
-    node _T_2790 = and(_T_2788, _T_2789) @[lsu_bus_buffer.scala 420:41]
-    node _T_2791 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 420:82]
-    node _T_2792 = and(_T_2790, _T_2791) @[lsu_bus_buffer.scala 420:71]
-    node _T_2793 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 420:101]
-    node _T_2794 = and(_T_2792, _T_2793) @[lsu_bus_buffer.scala 420:90]
-    node _T_2795 = or(_T_2787, _T_2794) @[lsu_bus_buffer.scala 419:59]
-    node _T_2796 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 421:17]
-    node _T_2797 = and(_T_2796, io.ldst_dual_r) @[lsu_bus_buffer.scala 421:35]
-    node _T_2798 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 421:63]
-    node _T_2799 = and(_T_2797, _T_2798) @[lsu_bus_buffer.scala 421:52]
-    node _T_2800 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 421:82]
-    node _T_2801 = and(_T_2799, _T_2800) @[lsu_bus_buffer.scala 421:71]
-    node _T_2802 = or(_T_2795, _T_2801) @[lsu_bus_buffer.scala 420:110]
-    node _T_2803 = and(_T_2783, _T_2802) @[lsu_bus_buffer.scala 418:112]
-    node _T_2804 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:82]
-    node _T_2805 = and(_T_2804, buf_state_en[0]) @[lsu_bus_buffer.scala 418:93]
-    node _T_2806 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 419:21]
-    node _T_2807 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 419:47]
-    node _T_2808 = or(_T_2806, _T_2807) @[lsu_bus_buffer.scala 419:32]
-    node _T_2809 = eq(_T_2808, UInt<1>("h00")) @[lsu_bus_buffer.scala 419:6]
-    node _T_2810 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 420:23]
-    node _T_2811 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 420:53]
-    node _T_2812 = and(_T_2810, _T_2811) @[lsu_bus_buffer.scala 420:41]
-    node _T_2813 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 420:82]
-    node _T_2814 = and(_T_2812, _T_2813) @[lsu_bus_buffer.scala 420:71]
-    node _T_2815 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 420:101]
-    node _T_2816 = and(_T_2814, _T_2815) @[lsu_bus_buffer.scala 420:90]
-    node _T_2817 = or(_T_2809, _T_2816) @[lsu_bus_buffer.scala 419:59]
-    node _T_2818 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 421:17]
-    node _T_2819 = and(_T_2818, io.ldst_dual_r) @[lsu_bus_buffer.scala 421:35]
-    node _T_2820 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 421:63]
-    node _T_2821 = and(_T_2819, _T_2820) @[lsu_bus_buffer.scala 421:52]
-    node _T_2822 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 421:82]
-    node _T_2823 = and(_T_2821, _T_2822) @[lsu_bus_buffer.scala 421:71]
-    node _T_2824 = or(_T_2817, _T_2823) @[lsu_bus_buffer.scala 420:110]
-    node _T_2825 = and(_T_2805, _T_2824) @[lsu_bus_buffer.scala 418:112]
-    node _T_2826 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:82]
-    node _T_2827 = and(_T_2826, buf_state_en[0]) @[lsu_bus_buffer.scala 418:93]
-    node _T_2828 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 419:21]
-    node _T_2829 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 419:47]
-    node _T_2830 = or(_T_2828, _T_2829) @[lsu_bus_buffer.scala 419:32]
-    node _T_2831 = eq(_T_2830, UInt<1>("h00")) @[lsu_bus_buffer.scala 419:6]
-    node _T_2832 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 420:23]
-    node _T_2833 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 420:53]
-    node _T_2834 = and(_T_2832, _T_2833) @[lsu_bus_buffer.scala 420:41]
-    node _T_2835 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 420:82]
-    node _T_2836 = and(_T_2834, _T_2835) @[lsu_bus_buffer.scala 420:71]
-    node _T_2837 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 420:101]
-    node _T_2838 = and(_T_2836, _T_2837) @[lsu_bus_buffer.scala 420:90]
-    node _T_2839 = or(_T_2831, _T_2838) @[lsu_bus_buffer.scala 419:59]
-    node _T_2840 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 421:17]
-    node _T_2841 = and(_T_2840, io.ldst_dual_r) @[lsu_bus_buffer.scala 421:35]
-    node _T_2842 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 421:63]
-    node _T_2843 = and(_T_2841, _T_2842) @[lsu_bus_buffer.scala 421:52]
-    node _T_2844 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 421:82]
-    node _T_2845 = and(_T_2843, _T_2844) @[lsu_bus_buffer.scala 421:71]
-    node _T_2846 = or(_T_2839, _T_2845) @[lsu_bus_buffer.scala 420:110]
-    node _T_2847 = and(_T_2827, _T_2846) @[lsu_bus_buffer.scala 418:112]
-    node _T_2848 = cat(_T_2847, _T_2825) @[Cat.scala 29:58]
-    node _T_2849 = cat(_T_2848, _T_2803) @[Cat.scala 29:58]
-    node _T_2850 = cat(_T_2849, _T_2781) @[Cat.scala 29:58]
-    node _T_2851 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:82]
-    node _T_2852 = and(_T_2851, buf_state_en[1]) @[lsu_bus_buffer.scala 418:93]
-    node _T_2853 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 419:21]
-    node _T_2854 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 419:47]
-    node _T_2855 = or(_T_2853, _T_2854) @[lsu_bus_buffer.scala 419:32]
-    node _T_2856 = eq(_T_2855, UInt<1>("h00")) @[lsu_bus_buffer.scala 419:6]
-    node _T_2857 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 420:23]
-    node _T_2858 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 420:53]
-    node _T_2859 = and(_T_2857, _T_2858) @[lsu_bus_buffer.scala 420:41]
-    node _T_2860 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 420:82]
-    node _T_2861 = and(_T_2859, _T_2860) @[lsu_bus_buffer.scala 420:71]
-    node _T_2862 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 420:101]
-    node _T_2863 = and(_T_2861, _T_2862) @[lsu_bus_buffer.scala 420:90]
-    node _T_2864 = or(_T_2856, _T_2863) @[lsu_bus_buffer.scala 419:59]
-    node _T_2865 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 421:17]
-    node _T_2866 = and(_T_2865, io.ldst_dual_r) @[lsu_bus_buffer.scala 421:35]
-    node _T_2867 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 421:63]
-    node _T_2868 = and(_T_2866, _T_2867) @[lsu_bus_buffer.scala 421:52]
-    node _T_2869 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 421:82]
-    node _T_2870 = and(_T_2868, _T_2869) @[lsu_bus_buffer.scala 421:71]
-    node _T_2871 = or(_T_2864, _T_2870) @[lsu_bus_buffer.scala 420:110]
-    node _T_2872 = and(_T_2852, _T_2871) @[lsu_bus_buffer.scala 418:112]
-    node _T_2873 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:82]
-    node _T_2874 = and(_T_2873, buf_state_en[1]) @[lsu_bus_buffer.scala 418:93]
-    node _T_2875 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 419:21]
-    node _T_2876 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 419:47]
-    node _T_2877 = or(_T_2875, _T_2876) @[lsu_bus_buffer.scala 419:32]
-    node _T_2878 = eq(_T_2877, UInt<1>("h00")) @[lsu_bus_buffer.scala 419:6]
-    node _T_2879 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 420:23]
-    node _T_2880 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 420:53]
-    node _T_2881 = and(_T_2879, _T_2880) @[lsu_bus_buffer.scala 420:41]
-    node _T_2882 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 420:82]
-    node _T_2883 = and(_T_2881, _T_2882) @[lsu_bus_buffer.scala 420:71]
-    node _T_2884 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 420:101]
-    node _T_2885 = and(_T_2883, _T_2884) @[lsu_bus_buffer.scala 420:90]
-    node _T_2886 = or(_T_2878, _T_2885) @[lsu_bus_buffer.scala 419:59]
-    node _T_2887 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 421:17]
-    node _T_2888 = and(_T_2887, io.ldst_dual_r) @[lsu_bus_buffer.scala 421:35]
-    node _T_2889 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 421:63]
-    node _T_2890 = and(_T_2888, _T_2889) @[lsu_bus_buffer.scala 421:52]
-    node _T_2891 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 421:82]
-    node _T_2892 = and(_T_2890, _T_2891) @[lsu_bus_buffer.scala 421:71]
-    node _T_2893 = or(_T_2886, _T_2892) @[lsu_bus_buffer.scala 420:110]
-    node _T_2894 = and(_T_2874, _T_2893) @[lsu_bus_buffer.scala 418:112]
-    node _T_2895 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:82]
-    node _T_2896 = and(_T_2895, buf_state_en[1]) @[lsu_bus_buffer.scala 418:93]
-    node _T_2897 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 419:21]
-    node _T_2898 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 419:47]
-    node _T_2899 = or(_T_2897, _T_2898) @[lsu_bus_buffer.scala 419:32]
-    node _T_2900 = eq(_T_2899, UInt<1>("h00")) @[lsu_bus_buffer.scala 419:6]
-    node _T_2901 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 420:23]
-    node _T_2902 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 420:53]
-    node _T_2903 = and(_T_2901, _T_2902) @[lsu_bus_buffer.scala 420:41]
-    node _T_2904 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 420:82]
-    node _T_2905 = and(_T_2903, _T_2904) @[lsu_bus_buffer.scala 420:71]
-    node _T_2906 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 420:101]
-    node _T_2907 = and(_T_2905, _T_2906) @[lsu_bus_buffer.scala 420:90]
-    node _T_2908 = or(_T_2900, _T_2907) @[lsu_bus_buffer.scala 419:59]
-    node _T_2909 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 421:17]
-    node _T_2910 = and(_T_2909, io.ldst_dual_r) @[lsu_bus_buffer.scala 421:35]
-    node _T_2911 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 421:63]
-    node _T_2912 = and(_T_2910, _T_2911) @[lsu_bus_buffer.scala 421:52]
-    node _T_2913 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 421:82]
-    node _T_2914 = and(_T_2912, _T_2913) @[lsu_bus_buffer.scala 421:71]
-    node _T_2915 = or(_T_2908, _T_2914) @[lsu_bus_buffer.scala 420:110]
-    node _T_2916 = and(_T_2896, _T_2915) @[lsu_bus_buffer.scala 418:112]
-    node _T_2917 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:82]
-    node _T_2918 = and(_T_2917, buf_state_en[1]) @[lsu_bus_buffer.scala 418:93]
-    node _T_2919 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 419:21]
-    node _T_2920 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 419:47]
-    node _T_2921 = or(_T_2919, _T_2920) @[lsu_bus_buffer.scala 419:32]
-    node _T_2922 = eq(_T_2921, UInt<1>("h00")) @[lsu_bus_buffer.scala 419:6]
-    node _T_2923 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 420:23]
-    node _T_2924 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 420:53]
-    node _T_2925 = and(_T_2923, _T_2924) @[lsu_bus_buffer.scala 420:41]
-    node _T_2926 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 420:82]
-    node _T_2927 = and(_T_2925, _T_2926) @[lsu_bus_buffer.scala 420:71]
-    node _T_2928 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 420:101]
-    node _T_2929 = and(_T_2927, _T_2928) @[lsu_bus_buffer.scala 420:90]
-    node _T_2930 = or(_T_2922, _T_2929) @[lsu_bus_buffer.scala 419:59]
-    node _T_2931 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 421:17]
-    node _T_2932 = and(_T_2931, io.ldst_dual_r) @[lsu_bus_buffer.scala 421:35]
-    node _T_2933 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 421:63]
-    node _T_2934 = and(_T_2932, _T_2933) @[lsu_bus_buffer.scala 421:52]
-    node _T_2935 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 421:82]
-    node _T_2936 = and(_T_2934, _T_2935) @[lsu_bus_buffer.scala 421:71]
-    node _T_2937 = or(_T_2930, _T_2936) @[lsu_bus_buffer.scala 420:110]
-    node _T_2938 = and(_T_2918, _T_2937) @[lsu_bus_buffer.scala 418:112]
-    node _T_2939 = cat(_T_2938, _T_2916) @[Cat.scala 29:58]
-    node _T_2940 = cat(_T_2939, _T_2894) @[Cat.scala 29:58]
-    node _T_2941 = cat(_T_2940, _T_2872) @[Cat.scala 29:58]
-    node _T_2942 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:82]
-    node _T_2943 = and(_T_2942, buf_state_en[2]) @[lsu_bus_buffer.scala 418:93]
-    node _T_2944 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 419:21]
-    node _T_2945 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 419:47]
-    node _T_2946 = or(_T_2944, _T_2945) @[lsu_bus_buffer.scala 419:32]
-    node _T_2947 = eq(_T_2946, UInt<1>("h00")) @[lsu_bus_buffer.scala 419:6]
-    node _T_2948 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 420:23]
-    node _T_2949 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 420:53]
-    node _T_2950 = and(_T_2948, _T_2949) @[lsu_bus_buffer.scala 420:41]
-    node _T_2951 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 420:82]
-    node _T_2952 = and(_T_2950, _T_2951) @[lsu_bus_buffer.scala 420:71]
-    node _T_2953 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 420:101]
-    node _T_2954 = and(_T_2952, _T_2953) @[lsu_bus_buffer.scala 420:90]
-    node _T_2955 = or(_T_2947, _T_2954) @[lsu_bus_buffer.scala 419:59]
-    node _T_2956 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 421:17]
-    node _T_2957 = and(_T_2956, io.ldst_dual_r) @[lsu_bus_buffer.scala 421:35]
-    node _T_2958 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 421:63]
-    node _T_2959 = and(_T_2957, _T_2958) @[lsu_bus_buffer.scala 421:52]
-    node _T_2960 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 421:82]
-    node _T_2961 = and(_T_2959, _T_2960) @[lsu_bus_buffer.scala 421:71]
-    node _T_2962 = or(_T_2955, _T_2961) @[lsu_bus_buffer.scala 420:110]
-    node _T_2963 = and(_T_2943, _T_2962) @[lsu_bus_buffer.scala 418:112]
-    node _T_2964 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:82]
-    node _T_2965 = and(_T_2964, buf_state_en[2]) @[lsu_bus_buffer.scala 418:93]
-    node _T_2966 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 419:21]
-    node _T_2967 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 419:47]
-    node _T_2968 = or(_T_2966, _T_2967) @[lsu_bus_buffer.scala 419:32]
-    node _T_2969 = eq(_T_2968, UInt<1>("h00")) @[lsu_bus_buffer.scala 419:6]
-    node _T_2970 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 420:23]
-    node _T_2971 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 420:53]
-    node _T_2972 = and(_T_2970, _T_2971) @[lsu_bus_buffer.scala 420:41]
-    node _T_2973 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 420:82]
-    node _T_2974 = and(_T_2972, _T_2973) @[lsu_bus_buffer.scala 420:71]
-    node _T_2975 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 420:101]
-    node _T_2976 = and(_T_2974, _T_2975) @[lsu_bus_buffer.scala 420:90]
-    node _T_2977 = or(_T_2969, _T_2976) @[lsu_bus_buffer.scala 419:59]
-    node _T_2978 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 421:17]
-    node _T_2979 = and(_T_2978, io.ldst_dual_r) @[lsu_bus_buffer.scala 421:35]
-    node _T_2980 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 421:63]
-    node _T_2981 = and(_T_2979, _T_2980) @[lsu_bus_buffer.scala 421:52]
-    node _T_2982 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 421:82]
-    node _T_2983 = and(_T_2981, _T_2982) @[lsu_bus_buffer.scala 421:71]
-    node _T_2984 = or(_T_2977, _T_2983) @[lsu_bus_buffer.scala 420:110]
-    node _T_2985 = and(_T_2965, _T_2984) @[lsu_bus_buffer.scala 418:112]
-    node _T_2986 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:82]
-    node _T_2987 = and(_T_2986, buf_state_en[2]) @[lsu_bus_buffer.scala 418:93]
-    node _T_2988 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 419:21]
-    node _T_2989 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 419:47]
-    node _T_2990 = or(_T_2988, _T_2989) @[lsu_bus_buffer.scala 419:32]
-    node _T_2991 = eq(_T_2990, UInt<1>("h00")) @[lsu_bus_buffer.scala 419:6]
-    node _T_2992 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 420:23]
-    node _T_2993 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 420:53]
-    node _T_2994 = and(_T_2992, _T_2993) @[lsu_bus_buffer.scala 420:41]
-    node _T_2995 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 420:82]
-    node _T_2996 = and(_T_2994, _T_2995) @[lsu_bus_buffer.scala 420:71]
-    node _T_2997 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 420:101]
-    node _T_2998 = and(_T_2996, _T_2997) @[lsu_bus_buffer.scala 420:90]
-    node _T_2999 = or(_T_2991, _T_2998) @[lsu_bus_buffer.scala 419:59]
-    node _T_3000 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 421:17]
-    node _T_3001 = and(_T_3000, io.ldst_dual_r) @[lsu_bus_buffer.scala 421:35]
-    node _T_3002 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 421:63]
-    node _T_3003 = and(_T_3001, _T_3002) @[lsu_bus_buffer.scala 421:52]
-    node _T_3004 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 421:82]
-    node _T_3005 = and(_T_3003, _T_3004) @[lsu_bus_buffer.scala 421:71]
-    node _T_3006 = or(_T_2999, _T_3005) @[lsu_bus_buffer.scala 420:110]
-    node _T_3007 = and(_T_2987, _T_3006) @[lsu_bus_buffer.scala 418:112]
-    node _T_3008 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:82]
-    node _T_3009 = and(_T_3008, buf_state_en[2]) @[lsu_bus_buffer.scala 418:93]
-    node _T_3010 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 419:21]
-    node _T_3011 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 419:47]
-    node _T_3012 = or(_T_3010, _T_3011) @[lsu_bus_buffer.scala 419:32]
-    node _T_3013 = eq(_T_3012, UInt<1>("h00")) @[lsu_bus_buffer.scala 419:6]
-    node _T_3014 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 420:23]
-    node _T_3015 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 420:53]
-    node _T_3016 = and(_T_3014, _T_3015) @[lsu_bus_buffer.scala 420:41]
-    node _T_3017 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 420:82]
-    node _T_3018 = and(_T_3016, _T_3017) @[lsu_bus_buffer.scala 420:71]
-    node _T_3019 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 420:101]
-    node _T_3020 = and(_T_3018, _T_3019) @[lsu_bus_buffer.scala 420:90]
-    node _T_3021 = or(_T_3013, _T_3020) @[lsu_bus_buffer.scala 419:59]
-    node _T_3022 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 421:17]
-    node _T_3023 = and(_T_3022, io.ldst_dual_r) @[lsu_bus_buffer.scala 421:35]
-    node _T_3024 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 421:63]
-    node _T_3025 = and(_T_3023, _T_3024) @[lsu_bus_buffer.scala 421:52]
-    node _T_3026 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 421:82]
-    node _T_3027 = and(_T_3025, _T_3026) @[lsu_bus_buffer.scala 421:71]
-    node _T_3028 = or(_T_3021, _T_3027) @[lsu_bus_buffer.scala 420:110]
-    node _T_3029 = and(_T_3009, _T_3028) @[lsu_bus_buffer.scala 418:112]
-    node _T_3030 = cat(_T_3029, _T_3007) @[Cat.scala 29:58]
-    node _T_3031 = cat(_T_3030, _T_2985) @[Cat.scala 29:58]
-    node _T_3032 = cat(_T_3031, _T_2963) @[Cat.scala 29:58]
-    node _T_3033 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:82]
-    node _T_3034 = and(_T_3033, buf_state_en[3]) @[lsu_bus_buffer.scala 418:93]
-    node _T_3035 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 419:21]
-    node _T_3036 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 419:47]
-    node _T_3037 = or(_T_3035, _T_3036) @[lsu_bus_buffer.scala 419:32]
-    node _T_3038 = eq(_T_3037, UInt<1>("h00")) @[lsu_bus_buffer.scala 419:6]
-    node _T_3039 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 420:23]
-    node _T_3040 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 420:53]
-    node _T_3041 = and(_T_3039, _T_3040) @[lsu_bus_buffer.scala 420:41]
-    node _T_3042 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 420:82]
-    node _T_3043 = and(_T_3041, _T_3042) @[lsu_bus_buffer.scala 420:71]
-    node _T_3044 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 420:101]
-    node _T_3045 = and(_T_3043, _T_3044) @[lsu_bus_buffer.scala 420:90]
-    node _T_3046 = or(_T_3038, _T_3045) @[lsu_bus_buffer.scala 419:59]
-    node _T_3047 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 421:17]
-    node _T_3048 = and(_T_3047, io.ldst_dual_r) @[lsu_bus_buffer.scala 421:35]
-    node _T_3049 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 421:63]
-    node _T_3050 = and(_T_3048, _T_3049) @[lsu_bus_buffer.scala 421:52]
-    node _T_3051 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 421:82]
-    node _T_3052 = and(_T_3050, _T_3051) @[lsu_bus_buffer.scala 421:71]
-    node _T_3053 = or(_T_3046, _T_3052) @[lsu_bus_buffer.scala 420:110]
-    node _T_3054 = and(_T_3034, _T_3053) @[lsu_bus_buffer.scala 418:112]
-    node _T_3055 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:82]
-    node _T_3056 = and(_T_3055, buf_state_en[3]) @[lsu_bus_buffer.scala 418:93]
-    node _T_3057 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 419:21]
-    node _T_3058 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 419:47]
-    node _T_3059 = or(_T_3057, _T_3058) @[lsu_bus_buffer.scala 419:32]
-    node _T_3060 = eq(_T_3059, UInt<1>("h00")) @[lsu_bus_buffer.scala 419:6]
-    node _T_3061 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 420:23]
-    node _T_3062 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 420:53]
-    node _T_3063 = and(_T_3061, _T_3062) @[lsu_bus_buffer.scala 420:41]
-    node _T_3064 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 420:82]
-    node _T_3065 = and(_T_3063, _T_3064) @[lsu_bus_buffer.scala 420:71]
-    node _T_3066 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 420:101]
-    node _T_3067 = and(_T_3065, _T_3066) @[lsu_bus_buffer.scala 420:90]
-    node _T_3068 = or(_T_3060, _T_3067) @[lsu_bus_buffer.scala 419:59]
-    node _T_3069 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 421:17]
-    node _T_3070 = and(_T_3069, io.ldst_dual_r) @[lsu_bus_buffer.scala 421:35]
-    node _T_3071 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 421:63]
-    node _T_3072 = and(_T_3070, _T_3071) @[lsu_bus_buffer.scala 421:52]
-    node _T_3073 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 421:82]
-    node _T_3074 = and(_T_3072, _T_3073) @[lsu_bus_buffer.scala 421:71]
-    node _T_3075 = or(_T_3068, _T_3074) @[lsu_bus_buffer.scala 420:110]
-    node _T_3076 = and(_T_3056, _T_3075) @[lsu_bus_buffer.scala 418:112]
-    node _T_3077 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:82]
-    node _T_3078 = and(_T_3077, buf_state_en[3]) @[lsu_bus_buffer.scala 418:93]
-    node _T_3079 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 419:21]
-    node _T_3080 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 419:47]
-    node _T_3081 = or(_T_3079, _T_3080) @[lsu_bus_buffer.scala 419:32]
-    node _T_3082 = eq(_T_3081, UInt<1>("h00")) @[lsu_bus_buffer.scala 419:6]
-    node _T_3083 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 420:23]
-    node _T_3084 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 420:53]
-    node _T_3085 = and(_T_3083, _T_3084) @[lsu_bus_buffer.scala 420:41]
-    node _T_3086 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 420:82]
-    node _T_3087 = and(_T_3085, _T_3086) @[lsu_bus_buffer.scala 420:71]
-    node _T_3088 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 420:101]
-    node _T_3089 = and(_T_3087, _T_3088) @[lsu_bus_buffer.scala 420:90]
-    node _T_3090 = or(_T_3082, _T_3089) @[lsu_bus_buffer.scala 419:59]
-    node _T_3091 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 421:17]
-    node _T_3092 = and(_T_3091, io.ldst_dual_r) @[lsu_bus_buffer.scala 421:35]
-    node _T_3093 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 421:63]
-    node _T_3094 = and(_T_3092, _T_3093) @[lsu_bus_buffer.scala 421:52]
-    node _T_3095 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 421:82]
-    node _T_3096 = and(_T_3094, _T_3095) @[lsu_bus_buffer.scala 421:71]
-    node _T_3097 = or(_T_3090, _T_3096) @[lsu_bus_buffer.scala 420:110]
-    node _T_3098 = and(_T_3078, _T_3097) @[lsu_bus_buffer.scala 418:112]
-    node _T_3099 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 418:82]
-    node _T_3100 = and(_T_3099, buf_state_en[3]) @[lsu_bus_buffer.scala 418:93]
-    node _T_3101 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 419:21]
-    node _T_3102 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 419:47]
-    node _T_3103 = or(_T_3101, _T_3102) @[lsu_bus_buffer.scala 419:32]
-    node _T_3104 = eq(_T_3103, UInt<1>("h00")) @[lsu_bus_buffer.scala 419:6]
-    node _T_3105 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 420:23]
-    node _T_3106 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 420:53]
-    node _T_3107 = and(_T_3105, _T_3106) @[lsu_bus_buffer.scala 420:41]
-    node _T_3108 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 420:82]
-    node _T_3109 = and(_T_3107, _T_3108) @[lsu_bus_buffer.scala 420:71]
-    node _T_3110 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 420:101]
-    node _T_3111 = and(_T_3109, _T_3110) @[lsu_bus_buffer.scala 420:90]
-    node _T_3112 = or(_T_3104, _T_3111) @[lsu_bus_buffer.scala 419:59]
-    node _T_3113 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 421:17]
-    node _T_3114 = and(_T_3113, io.ldst_dual_r) @[lsu_bus_buffer.scala 421:35]
-    node _T_3115 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 421:63]
-    node _T_3116 = and(_T_3114, _T_3115) @[lsu_bus_buffer.scala 421:52]
-    node _T_3117 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 421:82]
-    node _T_3118 = and(_T_3116, _T_3117) @[lsu_bus_buffer.scala 421:71]
-    node _T_3119 = or(_T_3112, _T_3118) @[lsu_bus_buffer.scala 420:110]
-    node _T_3120 = and(_T_3100, _T_3119) @[lsu_bus_buffer.scala 418:112]
-    node _T_3121 = cat(_T_3120, _T_3098) @[Cat.scala 29:58]
-    node _T_3122 = cat(_T_3121, _T_3076) @[Cat.scala 29:58]
-    node _T_3123 = cat(_T_3122, _T_3054) @[Cat.scala 29:58]
-    buf_rspage_set[0] <= _T_2850 @[lsu_bus_buffer.scala 418:18]
-    buf_rspage_set[1] <= _T_2941 @[lsu_bus_buffer.scala 418:18]
-    buf_rspage_set[2] <= _T_3032 @[lsu_bus_buffer.scala 418:18]
-    buf_rspage_set[3] <= _T_3123 @[lsu_bus_buffer.scala 418:18]
-    node _T_3124 = bits(buf_rspage_set[0], 0, 0) @[lsu_bus_buffer.scala 422:84]
-    node _T_3125 = bits(buf_rspage[0], 0, 0) @[lsu_bus_buffer.scala 422:103]
-    node _T_3126 = or(_T_3124, _T_3125) @[lsu_bus_buffer.scala 422:88]
-    node _T_3127 = bits(buf_rspage_set[0], 1, 1) @[lsu_bus_buffer.scala 422:84]
-    node _T_3128 = bits(buf_rspage[0], 1, 1) @[lsu_bus_buffer.scala 422:103]
-    node _T_3129 = or(_T_3127, _T_3128) @[lsu_bus_buffer.scala 422:88]
-    node _T_3130 = bits(buf_rspage_set[0], 2, 2) @[lsu_bus_buffer.scala 422:84]
-    node _T_3131 = bits(buf_rspage[0], 2, 2) @[lsu_bus_buffer.scala 422:103]
-    node _T_3132 = or(_T_3130, _T_3131) @[lsu_bus_buffer.scala 422:88]
-    node _T_3133 = bits(buf_rspage_set[0], 3, 3) @[lsu_bus_buffer.scala 422:84]
-    node _T_3134 = bits(buf_rspage[0], 3, 3) @[lsu_bus_buffer.scala 422:103]
-    node _T_3135 = or(_T_3133, _T_3134) @[lsu_bus_buffer.scala 422:88]
-    node _T_3136 = cat(_T_3135, _T_3132) @[Cat.scala 29:58]
-    node _T_3137 = cat(_T_3136, _T_3129) @[Cat.scala 29:58]
-    node _T_3138 = cat(_T_3137, _T_3126) @[Cat.scala 29:58]
-    node _T_3139 = bits(buf_rspage_set[1], 0, 0) @[lsu_bus_buffer.scala 422:84]
-    node _T_3140 = bits(buf_rspage[1], 0, 0) @[lsu_bus_buffer.scala 422:103]
-    node _T_3141 = or(_T_3139, _T_3140) @[lsu_bus_buffer.scala 422:88]
-    node _T_3142 = bits(buf_rspage_set[1], 1, 1) @[lsu_bus_buffer.scala 422:84]
-    node _T_3143 = bits(buf_rspage[1], 1, 1) @[lsu_bus_buffer.scala 422:103]
-    node _T_3144 = or(_T_3142, _T_3143) @[lsu_bus_buffer.scala 422:88]
-    node _T_3145 = bits(buf_rspage_set[1], 2, 2) @[lsu_bus_buffer.scala 422:84]
-    node _T_3146 = bits(buf_rspage[1], 2, 2) @[lsu_bus_buffer.scala 422:103]
-    node _T_3147 = or(_T_3145, _T_3146) @[lsu_bus_buffer.scala 422:88]
-    node _T_3148 = bits(buf_rspage_set[1], 3, 3) @[lsu_bus_buffer.scala 422:84]
-    node _T_3149 = bits(buf_rspage[1], 3, 3) @[lsu_bus_buffer.scala 422:103]
-    node _T_3150 = or(_T_3148, _T_3149) @[lsu_bus_buffer.scala 422:88]
-    node _T_3151 = cat(_T_3150, _T_3147) @[Cat.scala 29:58]
-    node _T_3152 = cat(_T_3151, _T_3144) @[Cat.scala 29:58]
-    node _T_3153 = cat(_T_3152, _T_3141) @[Cat.scala 29:58]
-    node _T_3154 = bits(buf_rspage_set[2], 0, 0) @[lsu_bus_buffer.scala 422:84]
-    node _T_3155 = bits(buf_rspage[2], 0, 0) @[lsu_bus_buffer.scala 422:103]
-    node _T_3156 = or(_T_3154, _T_3155) @[lsu_bus_buffer.scala 422:88]
-    node _T_3157 = bits(buf_rspage_set[2], 1, 1) @[lsu_bus_buffer.scala 422:84]
-    node _T_3158 = bits(buf_rspage[2], 1, 1) @[lsu_bus_buffer.scala 422:103]
-    node _T_3159 = or(_T_3157, _T_3158) @[lsu_bus_buffer.scala 422:88]
-    node _T_3160 = bits(buf_rspage_set[2], 2, 2) @[lsu_bus_buffer.scala 422:84]
-    node _T_3161 = bits(buf_rspage[2], 2, 2) @[lsu_bus_buffer.scala 422:103]
-    node _T_3162 = or(_T_3160, _T_3161) @[lsu_bus_buffer.scala 422:88]
-    node _T_3163 = bits(buf_rspage_set[2], 3, 3) @[lsu_bus_buffer.scala 422:84]
-    node _T_3164 = bits(buf_rspage[2], 3, 3) @[lsu_bus_buffer.scala 422:103]
-    node _T_3165 = or(_T_3163, _T_3164) @[lsu_bus_buffer.scala 422:88]
-    node _T_3166 = cat(_T_3165, _T_3162) @[Cat.scala 29:58]
-    node _T_3167 = cat(_T_3166, _T_3159) @[Cat.scala 29:58]
-    node _T_3168 = cat(_T_3167, _T_3156) @[Cat.scala 29:58]
-    node _T_3169 = bits(buf_rspage_set[3], 0, 0) @[lsu_bus_buffer.scala 422:84]
-    node _T_3170 = bits(buf_rspage[3], 0, 0) @[lsu_bus_buffer.scala 422:103]
-    node _T_3171 = or(_T_3169, _T_3170) @[lsu_bus_buffer.scala 422:88]
-    node _T_3172 = bits(buf_rspage_set[3], 1, 1) @[lsu_bus_buffer.scala 422:84]
-    node _T_3173 = bits(buf_rspage[3], 1, 1) @[lsu_bus_buffer.scala 422:103]
-    node _T_3174 = or(_T_3172, _T_3173) @[lsu_bus_buffer.scala 422:88]
-    node _T_3175 = bits(buf_rspage_set[3], 2, 2) @[lsu_bus_buffer.scala 422:84]
-    node _T_3176 = bits(buf_rspage[3], 2, 2) @[lsu_bus_buffer.scala 422:103]
-    node _T_3177 = or(_T_3175, _T_3176) @[lsu_bus_buffer.scala 422:88]
-    node _T_3178 = bits(buf_rspage_set[3], 3, 3) @[lsu_bus_buffer.scala 422:84]
-    node _T_3179 = bits(buf_rspage[3], 3, 3) @[lsu_bus_buffer.scala 422:103]
-    node _T_3180 = or(_T_3178, _T_3179) @[lsu_bus_buffer.scala 422:88]
-    node _T_3181 = cat(_T_3180, _T_3177) @[Cat.scala 29:58]
-    node _T_3182 = cat(_T_3181, _T_3174) @[Cat.scala 29:58]
-    node _T_3183 = cat(_T_3182, _T_3171) @[Cat.scala 29:58]
-    buf_rspage_in[0] <= _T_3138 @[lsu_bus_buffer.scala 422:17]
-    buf_rspage_in[1] <= _T_3153 @[lsu_bus_buffer.scala 422:17]
-    buf_rspage_in[2] <= _T_3168 @[lsu_bus_buffer.scala 422:17]
-    buf_rspage_in[3] <= _T_3183 @[lsu_bus_buffer.scala 422:17]
-    node _T_3184 = bits(buf_rspageQ[0], 0, 0) @[lsu_bus_buffer.scala 423:78]
-    node _T_3185 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 423:99]
-    node _T_3186 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 423:125]
-    node _T_3187 = or(_T_3185, _T_3186) @[lsu_bus_buffer.scala 423:110]
-    node _T_3188 = eq(_T_3187, UInt<1>("h00")) @[lsu_bus_buffer.scala 423:84]
-    node _T_3189 = and(_T_3184, _T_3188) @[lsu_bus_buffer.scala 423:82]
-    node _T_3190 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 423:147]
-    node _T_3191 = and(_T_3189, _T_3190) @[lsu_bus_buffer.scala 423:145]
-    node _T_3192 = bits(buf_rspageQ[0], 1, 1) @[lsu_bus_buffer.scala 423:78]
-    node _T_3193 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 423:99]
-    node _T_3194 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 423:125]
-    node _T_3195 = or(_T_3193, _T_3194) @[lsu_bus_buffer.scala 423:110]
-    node _T_3196 = eq(_T_3195, UInt<1>("h00")) @[lsu_bus_buffer.scala 423:84]
-    node _T_3197 = and(_T_3192, _T_3196) @[lsu_bus_buffer.scala 423:82]
-    node _T_3198 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 423:147]
-    node _T_3199 = and(_T_3197, _T_3198) @[lsu_bus_buffer.scala 423:145]
-    node _T_3200 = bits(buf_rspageQ[0], 2, 2) @[lsu_bus_buffer.scala 423:78]
-    node _T_3201 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 423:99]
-    node _T_3202 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 423:125]
-    node _T_3203 = or(_T_3201, _T_3202) @[lsu_bus_buffer.scala 423:110]
-    node _T_3204 = eq(_T_3203, UInt<1>("h00")) @[lsu_bus_buffer.scala 423:84]
-    node _T_3205 = and(_T_3200, _T_3204) @[lsu_bus_buffer.scala 423:82]
-    node _T_3206 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 423:147]
-    node _T_3207 = and(_T_3205, _T_3206) @[lsu_bus_buffer.scala 423:145]
-    node _T_3208 = bits(buf_rspageQ[0], 3, 3) @[lsu_bus_buffer.scala 423:78]
-    node _T_3209 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 423:99]
-    node _T_3210 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 423:125]
-    node _T_3211 = or(_T_3209, _T_3210) @[lsu_bus_buffer.scala 423:110]
-    node _T_3212 = eq(_T_3211, UInt<1>("h00")) @[lsu_bus_buffer.scala 423:84]
-    node _T_3213 = and(_T_3208, _T_3212) @[lsu_bus_buffer.scala 423:82]
-    node _T_3214 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 423:147]
-    node _T_3215 = and(_T_3213, _T_3214) @[lsu_bus_buffer.scala 423:145]
-    node _T_3216 = cat(_T_3215, _T_3207) @[Cat.scala 29:58]
-    node _T_3217 = cat(_T_3216, _T_3199) @[Cat.scala 29:58]
-    node _T_3218 = cat(_T_3217, _T_3191) @[Cat.scala 29:58]
-    node _T_3219 = bits(buf_rspageQ[1], 0, 0) @[lsu_bus_buffer.scala 423:78]
-    node _T_3220 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 423:99]
-    node _T_3221 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 423:125]
-    node _T_3222 = or(_T_3220, _T_3221) @[lsu_bus_buffer.scala 423:110]
-    node _T_3223 = eq(_T_3222, UInt<1>("h00")) @[lsu_bus_buffer.scala 423:84]
-    node _T_3224 = and(_T_3219, _T_3223) @[lsu_bus_buffer.scala 423:82]
-    node _T_3225 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 423:147]
-    node _T_3226 = and(_T_3224, _T_3225) @[lsu_bus_buffer.scala 423:145]
-    node _T_3227 = bits(buf_rspageQ[1], 1, 1) @[lsu_bus_buffer.scala 423:78]
-    node _T_3228 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 423:99]
-    node _T_3229 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 423:125]
-    node _T_3230 = or(_T_3228, _T_3229) @[lsu_bus_buffer.scala 423:110]
-    node _T_3231 = eq(_T_3230, UInt<1>("h00")) @[lsu_bus_buffer.scala 423:84]
-    node _T_3232 = and(_T_3227, _T_3231) @[lsu_bus_buffer.scala 423:82]
-    node _T_3233 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 423:147]
-    node _T_3234 = and(_T_3232, _T_3233) @[lsu_bus_buffer.scala 423:145]
-    node _T_3235 = bits(buf_rspageQ[1], 2, 2) @[lsu_bus_buffer.scala 423:78]
-    node _T_3236 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 423:99]
-    node _T_3237 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 423:125]
-    node _T_3238 = or(_T_3236, _T_3237) @[lsu_bus_buffer.scala 423:110]
-    node _T_3239 = eq(_T_3238, UInt<1>("h00")) @[lsu_bus_buffer.scala 423:84]
-    node _T_3240 = and(_T_3235, _T_3239) @[lsu_bus_buffer.scala 423:82]
-    node _T_3241 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 423:147]
-    node _T_3242 = and(_T_3240, _T_3241) @[lsu_bus_buffer.scala 423:145]
-    node _T_3243 = bits(buf_rspageQ[1], 3, 3) @[lsu_bus_buffer.scala 423:78]
-    node _T_3244 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 423:99]
-    node _T_3245 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 423:125]
-    node _T_3246 = or(_T_3244, _T_3245) @[lsu_bus_buffer.scala 423:110]
-    node _T_3247 = eq(_T_3246, UInt<1>("h00")) @[lsu_bus_buffer.scala 423:84]
-    node _T_3248 = and(_T_3243, _T_3247) @[lsu_bus_buffer.scala 423:82]
-    node _T_3249 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 423:147]
-    node _T_3250 = and(_T_3248, _T_3249) @[lsu_bus_buffer.scala 423:145]
-    node _T_3251 = cat(_T_3250, _T_3242) @[Cat.scala 29:58]
-    node _T_3252 = cat(_T_3251, _T_3234) @[Cat.scala 29:58]
-    node _T_3253 = cat(_T_3252, _T_3226) @[Cat.scala 29:58]
-    node _T_3254 = bits(buf_rspageQ[2], 0, 0) @[lsu_bus_buffer.scala 423:78]
-    node _T_3255 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 423:99]
-    node _T_3256 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 423:125]
-    node _T_3257 = or(_T_3255, _T_3256) @[lsu_bus_buffer.scala 423:110]
-    node _T_3258 = eq(_T_3257, UInt<1>("h00")) @[lsu_bus_buffer.scala 423:84]
-    node _T_3259 = and(_T_3254, _T_3258) @[lsu_bus_buffer.scala 423:82]
-    node _T_3260 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 423:147]
-    node _T_3261 = and(_T_3259, _T_3260) @[lsu_bus_buffer.scala 423:145]
-    node _T_3262 = bits(buf_rspageQ[2], 1, 1) @[lsu_bus_buffer.scala 423:78]
-    node _T_3263 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 423:99]
-    node _T_3264 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 423:125]
-    node _T_3265 = or(_T_3263, _T_3264) @[lsu_bus_buffer.scala 423:110]
-    node _T_3266 = eq(_T_3265, UInt<1>("h00")) @[lsu_bus_buffer.scala 423:84]
-    node _T_3267 = and(_T_3262, _T_3266) @[lsu_bus_buffer.scala 423:82]
-    node _T_3268 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 423:147]
-    node _T_3269 = and(_T_3267, _T_3268) @[lsu_bus_buffer.scala 423:145]
-    node _T_3270 = bits(buf_rspageQ[2], 2, 2) @[lsu_bus_buffer.scala 423:78]
-    node _T_3271 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 423:99]
-    node _T_3272 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 423:125]
-    node _T_3273 = or(_T_3271, _T_3272) @[lsu_bus_buffer.scala 423:110]
-    node _T_3274 = eq(_T_3273, UInt<1>("h00")) @[lsu_bus_buffer.scala 423:84]
-    node _T_3275 = and(_T_3270, _T_3274) @[lsu_bus_buffer.scala 423:82]
-    node _T_3276 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 423:147]
-    node _T_3277 = and(_T_3275, _T_3276) @[lsu_bus_buffer.scala 423:145]
-    node _T_3278 = bits(buf_rspageQ[2], 3, 3) @[lsu_bus_buffer.scala 423:78]
-    node _T_3279 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 423:99]
-    node _T_3280 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 423:125]
-    node _T_3281 = or(_T_3279, _T_3280) @[lsu_bus_buffer.scala 423:110]
-    node _T_3282 = eq(_T_3281, UInt<1>("h00")) @[lsu_bus_buffer.scala 423:84]
-    node _T_3283 = and(_T_3278, _T_3282) @[lsu_bus_buffer.scala 423:82]
-    node _T_3284 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 423:147]
-    node _T_3285 = and(_T_3283, _T_3284) @[lsu_bus_buffer.scala 423:145]
-    node _T_3286 = cat(_T_3285, _T_3277) @[Cat.scala 29:58]
-    node _T_3287 = cat(_T_3286, _T_3269) @[Cat.scala 29:58]
-    node _T_3288 = cat(_T_3287, _T_3261) @[Cat.scala 29:58]
-    node _T_3289 = bits(buf_rspageQ[3], 0, 0) @[lsu_bus_buffer.scala 423:78]
-    node _T_3290 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 423:99]
-    node _T_3291 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 423:125]
-    node _T_3292 = or(_T_3290, _T_3291) @[lsu_bus_buffer.scala 423:110]
-    node _T_3293 = eq(_T_3292, UInt<1>("h00")) @[lsu_bus_buffer.scala 423:84]
-    node _T_3294 = and(_T_3289, _T_3293) @[lsu_bus_buffer.scala 423:82]
-    node _T_3295 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 423:147]
-    node _T_3296 = and(_T_3294, _T_3295) @[lsu_bus_buffer.scala 423:145]
-    node _T_3297 = bits(buf_rspageQ[3], 1, 1) @[lsu_bus_buffer.scala 423:78]
-    node _T_3298 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 423:99]
-    node _T_3299 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 423:125]
-    node _T_3300 = or(_T_3298, _T_3299) @[lsu_bus_buffer.scala 423:110]
-    node _T_3301 = eq(_T_3300, UInt<1>("h00")) @[lsu_bus_buffer.scala 423:84]
-    node _T_3302 = and(_T_3297, _T_3301) @[lsu_bus_buffer.scala 423:82]
-    node _T_3303 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 423:147]
-    node _T_3304 = and(_T_3302, _T_3303) @[lsu_bus_buffer.scala 423:145]
-    node _T_3305 = bits(buf_rspageQ[3], 2, 2) @[lsu_bus_buffer.scala 423:78]
-    node _T_3306 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 423:99]
-    node _T_3307 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 423:125]
-    node _T_3308 = or(_T_3306, _T_3307) @[lsu_bus_buffer.scala 423:110]
-    node _T_3309 = eq(_T_3308, UInt<1>("h00")) @[lsu_bus_buffer.scala 423:84]
-    node _T_3310 = and(_T_3305, _T_3309) @[lsu_bus_buffer.scala 423:82]
-    node _T_3311 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 423:147]
-    node _T_3312 = and(_T_3310, _T_3311) @[lsu_bus_buffer.scala 423:145]
-    node _T_3313 = bits(buf_rspageQ[3], 3, 3) @[lsu_bus_buffer.scala 423:78]
-    node _T_3314 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 423:99]
-    node _T_3315 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 423:125]
-    node _T_3316 = or(_T_3314, _T_3315) @[lsu_bus_buffer.scala 423:110]
-    node _T_3317 = eq(_T_3316, UInt<1>("h00")) @[lsu_bus_buffer.scala 423:84]
-    node _T_3318 = and(_T_3313, _T_3317) @[lsu_bus_buffer.scala 423:82]
-    node _T_3319 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 423:147]
-    node _T_3320 = and(_T_3318, _T_3319) @[lsu_bus_buffer.scala 423:145]
-    node _T_3321 = cat(_T_3320, _T_3312) @[Cat.scala 29:58]
-    node _T_3322 = cat(_T_3321, _T_3304) @[Cat.scala 29:58]
-    node _T_3323 = cat(_T_3322, _T_3296) @[Cat.scala 29:58]
-    buf_rspage[0] <= _T_3218 @[lsu_bus_buffer.scala 423:14]
-    buf_rspage[1] <= _T_3253 @[lsu_bus_buffer.scala 423:14]
-    buf_rspage[2] <= _T_3288 @[lsu_bus_buffer.scala 423:14]
-    buf_rspage[3] <= _T_3323 @[lsu_bus_buffer.scala 423:14]
-    node _T_3324 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 428:75]
-    node _T_3325 = and(ibuf_drain_vld, _T_3324) @[lsu_bus_buffer.scala 428:63]
-    node _T_3326 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 428:75]
-    node _T_3327 = and(ibuf_drain_vld, _T_3326) @[lsu_bus_buffer.scala 428:63]
-    node _T_3328 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 428:75]
-    node _T_3329 = and(ibuf_drain_vld, _T_3328) @[lsu_bus_buffer.scala 428:63]
-    node _T_3330 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 428:75]
-    node _T_3331 = and(ibuf_drain_vld, _T_3330) @[lsu_bus_buffer.scala 428:63]
-    node _T_3332 = cat(_T_3331, _T_3329) @[Cat.scala 29:58]
-    node _T_3333 = cat(_T_3332, _T_3327) @[Cat.scala 29:58]
-    node _T_3334 = cat(_T_3333, _T_3325) @[Cat.scala 29:58]
-    ibuf_drainvec_vld <= _T_3334 @[lsu_bus_buffer.scala 428:21]
-    node _T_3335 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 429:64]
-    node _T_3336 = bits(ibuf_byteen_out, 3, 0) @[lsu_bus_buffer.scala 429:84]
-    node _T_3337 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 430:18]
-    node _T_3338 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 430:46]
-    node _T_3339 = and(_T_3337, _T_3338) @[lsu_bus_buffer.scala 430:35]
-    node _T_3340 = bits(ldst_byteen_hi_r, 3, 0) @[lsu_bus_buffer.scala 430:71]
-    node _T_3341 = bits(ldst_byteen_lo_r, 3, 0) @[lsu_bus_buffer.scala 430:94]
-    node _T_3342 = mux(_T_3339, _T_3340, _T_3341) @[lsu_bus_buffer.scala 430:8]
-    node _T_3343 = mux(_T_3335, _T_3336, _T_3342) @[lsu_bus_buffer.scala 429:46]
-    node _T_3344 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 429:64]
-    node _T_3345 = bits(ibuf_byteen_out, 3, 0) @[lsu_bus_buffer.scala 429:84]
-    node _T_3346 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 430:18]
-    node _T_3347 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 430:46]
-    node _T_3348 = and(_T_3346, _T_3347) @[lsu_bus_buffer.scala 430:35]
-    node _T_3349 = bits(ldst_byteen_hi_r, 3, 0) @[lsu_bus_buffer.scala 430:71]
-    node _T_3350 = bits(ldst_byteen_lo_r, 3, 0) @[lsu_bus_buffer.scala 430:94]
-    node _T_3351 = mux(_T_3348, _T_3349, _T_3350) @[lsu_bus_buffer.scala 430:8]
-    node _T_3352 = mux(_T_3344, _T_3345, _T_3351) @[lsu_bus_buffer.scala 429:46]
-    node _T_3353 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 429:64]
-    node _T_3354 = bits(ibuf_byteen_out, 3, 0) @[lsu_bus_buffer.scala 429:84]
-    node _T_3355 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 430:18]
-    node _T_3356 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 430:46]
-    node _T_3357 = and(_T_3355, _T_3356) @[lsu_bus_buffer.scala 430:35]
-    node _T_3358 = bits(ldst_byteen_hi_r, 3, 0) @[lsu_bus_buffer.scala 430:71]
-    node _T_3359 = bits(ldst_byteen_lo_r, 3, 0) @[lsu_bus_buffer.scala 430:94]
-    node _T_3360 = mux(_T_3357, _T_3358, _T_3359) @[lsu_bus_buffer.scala 430:8]
-    node _T_3361 = mux(_T_3353, _T_3354, _T_3360) @[lsu_bus_buffer.scala 429:46]
-    node _T_3362 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 429:64]
-    node _T_3363 = bits(ibuf_byteen_out, 3, 0) @[lsu_bus_buffer.scala 429:84]
-    node _T_3364 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 430:18]
-    node _T_3365 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 430:46]
-    node _T_3366 = and(_T_3364, _T_3365) @[lsu_bus_buffer.scala 430:35]
-    node _T_3367 = bits(ldst_byteen_hi_r, 3, 0) @[lsu_bus_buffer.scala 430:71]
-    node _T_3368 = bits(ldst_byteen_lo_r, 3, 0) @[lsu_bus_buffer.scala 430:94]
-    node _T_3369 = mux(_T_3366, _T_3367, _T_3368) @[lsu_bus_buffer.scala 430:8]
-    node _T_3370 = mux(_T_3362, _T_3363, _T_3369) @[lsu_bus_buffer.scala 429:46]
-    buf_byteen_in[0] <= _T_3343 @[lsu_bus_buffer.scala 429:17]
-    buf_byteen_in[1] <= _T_3352 @[lsu_bus_buffer.scala 429:17]
-    buf_byteen_in[2] <= _T_3361 @[lsu_bus_buffer.scala 429:17]
-    buf_byteen_in[3] <= _T_3370 @[lsu_bus_buffer.scala 429:17]
-    node _T_3371 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 431:62]
-    node _T_3372 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 431:91]
-    node _T_3373 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 431:119]
-    node _T_3374 = and(_T_3372, _T_3373) @[lsu_bus_buffer.scala 431:108]
-    node _T_3375 = mux(_T_3374, io.end_addr_r, io.lsu_addr_r) @[lsu_bus_buffer.scala 431:81]
-    node _T_3376 = mux(_T_3371, ibuf_addr, _T_3375) @[lsu_bus_buffer.scala 431:44]
-    node _T_3377 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 431:62]
-    node _T_3378 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 431:91]
-    node _T_3379 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 431:119]
-    node _T_3380 = and(_T_3378, _T_3379) @[lsu_bus_buffer.scala 431:108]
-    node _T_3381 = mux(_T_3380, io.end_addr_r, io.lsu_addr_r) @[lsu_bus_buffer.scala 431:81]
-    node _T_3382 = mux(_T_3377, ibuf_addr, _T_3381) @[lsu_bus_buffer.scala 431:44]
-    node _T_3383 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 431:62]
-    node _T_3384 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 431:91]
-    node _T_3385 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 431:119]
-    node _T_3386 = and(_T_3384, _T_3385) @[lsu_bus_buffer.scala 431:108]
-    node _T_3387 = mux(_T_3386, io.end_addr_r, io.lsu_addr_r) @[lsu_bus_buffer.scala 431:81]
-    node _T_3388 = mux(_T_3383, ibuf_addr, _T_3387) @[lsu_bus_buffer.scala 431:44]
-    node _T_3389 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 431:62]
-    node _T_3390 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 431:91]
-    node _T_3391 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 431:119]
-    node _T_3392 = and(_T_3390, _T_3391) @[lsu_bus_buffer.scala 431:108]
-    node _T_3393 = mux(_T_3392, io.end_addr_r, io.lsu_addr_r) @[lsu_bus_buffer.scala 431:81]
-    node _T_3394 = mux(_T_3389, ibuf_addr, _T_3393) @[lsu_bus_buffer.scala 431:44]
-    buf_addr_in[0] <= _T_3376 @[lsu_bus_buffer.scala 431:15]
-    buf_addr_in[1] <= _T_3382 @[lsu_bus_buffer.scala 431:15]
-    buf_addr_in[2] <= _T_3388 @[lsu_bus_buffer.scala 431:15]
-    buf_addr_in[3] <= _T_3394 @[lsu_bus_buffer.scala 431:15]
-    node _T_3395 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 432:63]
-    node _T_3396 = mux(_T_3395, ibuf_dual, io.ldst_dual_r) @[lsu_bus_buffer.scala 432:45]
-    node _T_3397 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 432:63]
-    node _T_3398 = mux(_T_3397, ibuf_dual, io.ldst_dual_r) @[lsu_bus_buffer.scala 432:45]
-    node _T_3399 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 432:63]
-    node _T_3400 = mux(_T_3399, ibuf_dual, io.ldst_dual_r) @[lsu_bus_buffer.scala 432:45]
-    node _T_3401 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 432:63]
-    node _T_3402 = mux(_T_3401, ibuf_dual, io.ldst_dual_r) @[lsu_bus_buffer.scala 432:45]
-    node _T_3403 = cat(_T_3402, _T_3400) @[Cat.scala 29:58]
-    node _T_3404 = cat(_T_3403, _T_3398) @[Cat.scala 29:58]
-    node _T_3405 = cat(_T_3404, _T_3396) @[Cat.scala 29:58]
-    buf_dual_in <= _T_3405 @[lsu_bus_buffer.scala 432:15]
-    node _T_3406 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 433:65]
-    node _T_3407 = mux(_T_3406, ibuf_samedw, ldst_samedw_r) @[lsu_bus_buffer.scala 433:47]
-    node _T_3408 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 433:65]
-    node _T_3409 = mux(_T_3408, ibuf_samedw, ldst_samedw_r) @[lsu_bus_buffer.scala 433:47]
-    node _T_3410 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 433:65]
-    node _T_3411 = mux(_T_3410, ibuf_samedw, ldst_samedw_r) @[lsu_bus_buffer.scala 433:47]
-    node _T_3412 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 433:65]
-    node _T_3413 = mux(_T_3412, ibuf_samedw, ldst_samedw_r) @[lsu_bus_buffer.scala 433:47]
-    node _T_3414 = cat(_T_3413, _T_3411) @[Cat.scala 29:58]
-    node _T_3415 = cat(_T_3414, _T_3409) @[Cat.scala 29:58]
-    node _T_3416 = cat(_T_3415, _T_3407) @[Cat.scala 29:58]
-    buf_samedw_in <= _T_3416 @[lsu_bus_buffer.scala 433:17]
-    node _T_3417 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 434:66]
-    node _T_3418 = or(ibuf_nomerge, ibuf_force_drain) @[lsu_bus_buffer.scala 434:84]
-    node _T_3419 = mux(_T_3417, _T_3418, io.no_dword_merge_r) @[lsu_bus_buffer.scala 434:48]
-    node _T_3420 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 434:66]
-    node _T_3421 = or(ibuf_nomerge, ibuf_force_drain) @[lsu_bus_buffer.scala 434:84]
-    node _T_3422 = mux(_T_3420, _T_3421, io.no_dword_merge_r) @[lsu_bus_buffer.scala 434:48]
-    node _T_3423 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 434:66]
-    node _T_3424 = or(ibuf_nomerge, ibuf_force_drain) @[lsu_bus_buffer.scala 434:84]
-    node _T_3425 = mux(_T_3423, _T_3424, io.no_dword_merge_r) @[lsu_bus_buffer.scala 434:48]
-    node _T_3426 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 434:66]
-    node _T_3427 = or(ibuf_nomerge, ibuf_force_drain) @[lsu_bus_buffer.scala 434:84]
-    node _T_3428 = mux(_T_3426, _T_3427, io.no_dword_merge_r) @[lsu_bus_buffer.scala 434:48]
-    node _T_3429 = cat(_T_3428, _T_3425) @[Cat.scala 29:58]
-    node _T_3430 = cat(_T_3429, _T_3422) @[Cat.scala 29:58]
-    node _T_3431 = cat(_T_3430, _T_3419) @[Cat.scala 29:58]
-    buf_nomerge_in <= _T_3431 @[lsu_bus_buffer.scala 434:18]
-    node _T_3432 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 435:65]
-    node _T_3433 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 435:90]
-    node _T_3434 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 435:118]
-    node _T_3435 = and(_T_3433, _T_3434) @[lsu_bus_buffer.scala 435:107]
-    node _T_3436 = mux(_T_3432, ibuf_dual, _T_3435) @[lsu_bus_buffer.scala 435:47]
-    node _T_3437 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 435:65]
-    node _T_3438 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 435:90]
-    node _T_3439 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 435:118]
-    node _T_3440 = and(_T_3438, _T_3439) @[lsu_bus_buffer.scala 435:107]
-    node _T_3441 = mux(_T_3437, ibuf_dual, _T_3440) @[lsu_bus_buffer.scala 435:47]
-    node _T_3442 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 435:65]
-    node _T_3443 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 435:90]
-    node _T_3444 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 435:118]
-    node _T_3445 = and(_T_3443, _T_3444) @[lsu_bus_buffer.scala 435:107]
-    node _T_3446 = mux(_T_3442, ibuf_dual, _T_3445) @[lsu_bus_buffer.scala 435:47]
-    node _T_3447 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 435:65]
-    node _T_3448 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 435:90]
-    node _T_3449 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 435:118]
-    node _T_3450 = and(_T_3448, _T_3449) @[lsu_bus_buffer.scala 435:107]
-    node _T_3451 = mux(_T_3447, ibuf_dual, _T_3450) @[lsu_bus_buffer.scala 435:47]
-    node _T_3452 = cat(_T_3451, _T_3446) @[Cat.scala 29:58]
-    node _T_3453 = cat(_T_3452, _T_3441) @[Cat.scala 29:58]
-    node _T_3454 = cat(_T_3453, _T_3436) @[Cat.scala 29:58]
-    buf_dualhi_in <= _T_3454 @[lsu_bus_buffer.scala 435:17]
-    node _T_3455 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 436:65]
-    node _T_3456 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 436:97]
-    node _T_3457 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 436:125]
-    node _T_3458 = and(_T_3456, _T_3457) @[lsu_bus_buffer.scala 436:114]
-    node _T_3459 = mux(_T_3458, WrPtr0_r, WrPtr1_r) @[lsu_bus_buffer.scala 436:87]
-    node _T_3460 = mux(_T_3455, ibuf_dualtag, _T_3459) @[lsu_bus_buffer.scala 436:47]
-    node _T_3461 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 436:65]
-    node _T_3462 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 436:97]
-    node _T_3463 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 436:125]
-    node _T_3464 = and(_T_3462, _T_3463) @[lsu_bus_buffer.scala 436:114]
-    node _T_3465 = mux(_T_3464, WrPtr0_r, WrPtr1_r) @[lsu_bus_buffer.scala 436:87]
-    node _T_3466 = mux(_T_3461, ibuf_dualtag, _T_3465) @[lsu_bus_buffer.scala 436:47]
-    node _T_3467 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 436:65]
-    node _T_3468 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 436:97]
-    node _T_3469 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 436:125]
-    node _T_3470 = and(_T_3468, _T_3469) @[lsu_bus_buffer.scala 436:114]
-    node _T_3471 = mux(_T_3470, WrPtr0_r, WrPtr1_r) @[lsu_bus_buffer.scala 436:87]
-    node _T_3472 = mux(_T_3467, ibuf_dualtag, _T_3471) @[lsu_bus_buffer.scala 436:47]
-    node _T_3473 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 436:65]
-    node _T_3474 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 436:97]
-    node _T_3475 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 436:125]
-    node _T_3476 = and(_T_3474, _T_3475) @[lsu_bus_buffer.scala 436:114]
-    node _T_3477 = mux(_T_3476, WrPtr0_r, WrPtr1_r) @[lsu_bus_buffer.scala 436:87]
-    node _T_3478 = mux(_T_3473, ibuf_dualtag, _T_3477) @[lsu_bus_buffer.scala 436:47]
-    buf_dualtag_in[0] <= _T_3460 @[lsu_bus_buffer.scala 436:18]
-    buf_dualtag_in[1] <= _T_3466 @[lsu_bus_buffer.scala 436:18]
-    buf_dualtag_in[2] <= _T_3472 @[lsu_bus_buffer.scala 436:18]
-    buf_dualtag_in[3] <= _T_3478 @[lsu_bus_buffer.scala 436:18]
-    node _T_3479 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 437:69]
-    node _T_3480 = mux(_T_3479, ibuf_sideeffect, io.is_sideeffects_r) @[lsu_bus_buffer.scala 437:51]
-    node _T_3481 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 437:69]
-    node _T_3482 = mux(_T_3481, ibuf_sideeffect, io.is_sideeffects_r) @[lsu_bus_buffer.scala 437:51]
-    node _T_3483 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 437:69]
-    node _T_3484 = mux(_T_3483, ibuf_sideeffect, io.is_sideeffects_r) @[lsu_bus_buffer.scala 437:51]
-    node _T_3485 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 437:69]
-    node _T_3486 = mux(_T_3485, ibuf_sideeffect, io.is_sideeffects_r) @[lsu_bus_buffer.scala 437:51]
-    node _T_3487 = cat(_T_3486, _T_3484) @[Cat.scala 29:58]
-    node _T_3488 = cat(_T_3487, _T_3482) @[Cat.scala 29:58]
-    node _T_3489 = cat(_T_3488, _T_3480) @[Cat.scala 29:58]
-    buf_sideeffect_in <= _T_3489 @[lsu_bus_buffer.scala 437:21]
-    node _T_3490 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 438:65]
-    node _T_3491 = mux(_T_3490, ibuf_unsign, io.lsu_pkt_r.bits.unsign) @[lsu_bus_buffer.scala 438:47]
-    node _T_3492 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 438:65]
-    node _T_3493 = mux(_T_3492, ibuf_unsign, io.lsu_pkt_r.bits.unsign) @[lsu_bus_buffer.scala 438:47]
-    node _T_3494 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 438:65]
-    node _T_3495 = mux(_T_3494, ibuf_unsign, io.lsu_pkt_r.bits.unsign) @[lsu_bus_buffer.scala 438:47]
-    node _T_3496 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 438:65]
-    node _T_3497 = mux(_T_3496, ibuf_unsign, io.lsu_pkt_r.bits.unsign) @[lsu_bus_buffer.scala 438:47]
-    node _T_3498 = cat(_T_3497, _T_3495) @[Cat.scala 29:58]
-    node _T_3499 = cat(_T_3498, _T_3493) @[Cat.scala 29:58]
-    node _T_3500 = cat(_T_3499, _T_3491) @[Cat.scala 29:58]
-    buf_unsign_in <= _T_3500 @[lsu_bus_buffer.scala 438:17]
-    node _T_3501 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 439:60]
-    node _T_3502 = cat(io.lsu_pkt_r.bits.word, io.lsu_pkt_r.bits.half) @[Cat.scala 29:58]
-    node _T_3503 = mux(_T_3501, ibuf_sz, _T_3502) @[lsu_bus_buffer.scala 439:42]
-    node _T_3504 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 439:60]
-    node _T_3505 = cat(io.lsu_pkt_r.bits.word, io.lsu_pkt_r.bits.half) @[Cat.scala 29:58]
-    node _T_3506 = mux(_T_3504, ibuf_sz, _T_3505) @[lsu_bus_buffer.scala 439:42]
-    node _T_3507 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 439:60]
-    node _T_3508 = cat(io.lsu_pkt_r.bits.word, io.lsu_pkt_r.bits.half) @[Cat.scala 29:58]
-    node _T_3509 = mux(_T_3507, ibuf_sz, _T_3508) @[lsu_bus_buffer.scala 439:42]
-    node _T_3510 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 439:60]
-    node _T_3511 = cat(io.lsu_pkt_r.bits.word, io.lsu_pkt_r.bits.half) @[Cat.scala 29:58]
-    node _T_3512 = mux(_T_3510, ibuf_sz, _T_3511) @[lsu_bus_buffer.scala 439:42]
-    buf_sz_in[0] <= _T_3503 @[lsu_bus_buffer.scala 439:13]
-    buf_sz_in[1] <= _T_3506 @[lsu_bus_buffer.scala 439:13]
-    buf_sz_in[2] <= _T_3509 @[lsu_bus_buffer.scala 439:13]
-    buf_sz_in[3] <= _T_3512 @[lsu_bus_buffer.scala 439:13]
-    node _T_3513 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 440:64]
-    node _T_3514 = mux(_T_3513, ibuf_write, io.lsu_pkt_r.bits.store) @[lsu_bus_buffer.scala 440:46]
-    node _T_3515 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 440:64]
-    node _T_3516 = mux(_T_3515, ibuf_write, io.lsu_pkt_r.bits.store) @[lsu_bus_buffer.scala 440:46]
-    node _T_3517 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 440:64]
-    node _T_3518 = mux(_T_3517, ibuf_write, io.lsu_pkt_r.bits.store) @[lsu_bus_buffer.scala 440:46]
-    node _T_3519 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 440:64]
-    node _T_3520 = mux(_T_3519, ibuf_write, io.lsu_pkt_r.bits.store) @[lsu_bus_buffer.scala 440:46]
-    node _T_3521 = cat(_T_3520, _T_3518) @[Cat.scala 29:58]
-    node _T_3522 = cat(_T_3521, _T_3516) @[Cat.scala 29:58]
-    node _T_3523 = cat(_T_3522, _T_3514) @[Cat.scala 29:58]
-    buf_write_in <= _T_3523 @[lsu_bus_buffer.scala 440:16]
-    node _T_3524 = eq(UInt<3>("h00"), buf_state[0]) @[Conditional.scala 37:30]
-    when _T_3524 : @[Conditional.scala 40:58]
-      node _T_3525 = bits(io.lsu_bus_clk_en, 0, 0) @[lsu_bus_buffer.scala 445:56]
-      node _T_3526 = mux(_T_3525, UInt<3>("h02"), UInt<3>("h01")) @[lsu_bus_buffer.scala 445:31]
-      buf_nxtstate[0] <= _T_3526 @[lsu_bus_buffer.scala 445:25]
-      node _T_3527 = and(io.lsu_busreq_r, io.lsu_commit_r) @[lsu_bus_buffer.scala 446:45]
-      node _T_3528 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 446:77]
-      node _T_3529 = eq(ibuf_merge_en, UInt<1>("h00")) @[lsu_bus_buffer.scala 446:97]
-      node _T_3530 = and(_T_3528, _T_3529) @[lsu_bus_buffer.scala 446:95]
-      node _T_3531 = eq(UInt<1>("h00"), WrPtr0_r) @[lsu_bus_buffer.scala 446:117]
-      node _T_3532 = and(_T_3530, _T_3531) @[lsu_bus_buffer.scala 446:112]
-      node _T_3533 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 446:144]
-      node _T_3534 = eq(UInt<1>("h00"), WrPtr1_r) @[lsu_bus_buffer.scala 446:166]
-      node _T_3535 = and(_T_3533, _T_3534) @[lsu_bus_buffer.scala 446:161]
-      node _T_3536 = or(_T_3532, _T_3535) @[lsu_bus_buffer.scala 446:132]
-      node _T_3537 = and(_T_3527, _T_3536) @[lsu_bus_buffer.scala 446:63]
-      node _T_3538 = eq(UInt<1>("h00"), ibuf_tag) @[lsu_bus_buffer.scala 446:206]
-      node _T_3539 = and(ibuf_drain_vld, _T_3538) @[lsu_bus_buffer.scala 446:201]
-      node _T_3540 = or(_T_3537, _T_3539) @[lsu_bus_buffer.scala 446:183]
-      buf_state_en[0] <= _T_3540 @[lsu_bus_buffer.scala 446:25]
-      buf_wr_en[0] <= buf_state_en[0] @[lsu_bus_buffer.scala 447:22]
-      buf_data_en[0] <= buf_state_en[0] @[lsu_bus_buffer.scala 448:24]
-      node _T_3541 = eq(UInt<1>("h00"), ibuf_tag) @[lsu_bus_buffer.scala 449:52]
-      node _T_3542 = and(ibuf_drain_vld, _T_3541) @[lsu_bus_buffer.scala 449:47]
-      node _T_3543 = bits(_T_3542, 0, 0) @[lsu_bus_buffer.scala 449:73]
-      node _T_3544 = bits(ibuf_data_out, 31, 0) @[lsu_bus_buffer.scala 449:90]
-      node _T_3545 = bits(store_data_lo_r, 31, 0) @[lsu_bus_buffer.scala 449:114]
-      node _T_3546 = mux(_T_3543, _T_3544, _T_3545) @[lsu_bus_buffer.scala 449:30]
-      buf_data_in[0] <= _T_3546 @[lsu_bus_buffer.scala 449:24]
-      buf_cmd_state_bus_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 450:34]
+    node _T_1992 = mux(UInt<1>("h00"), UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
+    node _T_1993 = cat(_T_1992, CmdPtr0Dec) @[Cat.scala 29:58]
+    node _T_1994 = bits(_T_1993, 4, 4) @[lsu_bus_buffer.scala 389:39]
+    node _T_1995 = bits(_T_1993, 5, 5) @[lsu_bus_buffer.scala 389:45]
+    node _T_1996 = or(_T_1994, _T_1995) @[lsu_bus_buffer.scala 389:42]
+    node _T_1997 = bits(_T_1993, 6, 6) @[lsu_bus_buffer.scala 389:51]
+    node _T_1998 = or(_T_1996, _T_1997) @[lsu_bus_buffer.scala 389:48]
+    node _T_1999 = bits(_T_1993, 7, 7) @[lsu_bus_buffer.scala 389:57]
+    node _T_2000 = or(_T_1998, _T_1999) @[lsu_bus_buffer.scala 389:54]
+    node _T_2001 = bits(_T_1993, 2, 2) @[lsu_bus_buffer.scala 389:64]
+    node _T_2002 = bits(_T_1993, 3, 3) @[lsu_bus_buffer.scala 389:70]
+    node _T_2003 = or(_T_2001, _T_2002) @[lsu_bus_buffer.scala 389:67]
+    node _T_2004 = bits(_T_1993, 6, 6) @[lsu_bus_buffer.scala 389:76]
+    node _T_2005 = or(_T_2003, _T_2004) @[lsu_bus_buffer.scala 389:73]
+    node _T_2006 = bits(_T_1993, 7, 7) @[lsu_bus_buffer.scala 389:82]
+    node _T_2007 = or(_T_2005, _T_2006) @[lsu_bus_buffer.scala 389:79]
+    node _T_2008 = bits(_T_1993, 1, 1) @[lsu_bus_buffer.scala 389:89]
+    node _T_2009 = bits(_T_1993, 3, 3) @[lsu_bus_buffer.scala 389:95]
+    node _T_2010 = or(_T_2008, _T_2009) @[lsu_bus_buffer.scala 389:92]
+    node _T_2011 = bits(_T_1993, 5, 5) @[lsu_bus_buffer.scala 389:101]
+    node _T_2012 = or(_T_2010, _T_2011) @[lsu_bus_buffer.scala 389:98]
+    node _T_2013 = bits(_T_1993, 7, 7) @[lsu_bus_buffer.scala 389:107]
+    node _T_2014 = or(_T_2012, _T_2013) @[lsu_bus_buffer.scala 389:104]
+    node _T_2015 = cat(_T_2000, _T_2007) @[Cat.scala 29:58]
+    node _T_2016 = cat(_T_2015, _T_2014) @[Cat.scala 29:58]
+    CmdPtr0 <= _T_2016 @[lsu_bus_buffer.scala 394:11]
+    node _T_2017 = mux(UInt<1>("h00"), UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
+    node _T_2018 = cat(_T_2017, CmdPtr1Dec) @[Cat.scala 29:58]
+    node _T_2019 = bits(_T_2018, 4, 4) @[lsu_bus_buffer.scala 389:39]
+    node _T_2020 = bits(_T_2018, 5, 5) @[lsu_bus_buffer.scala 389:45]
+    node _T_2021 = or(_T_2019, _T_2020) @[lsu_bus_buffer.scala 389:42]
+    node _T_2022 = bits(_T_2018, 6, 6) @[lsu_bus_buffer.scala 389:51]
+    node _T_2023 = or(_T_2021, _T_2022) @[lsu_bus_buffer.scala 389:48]
+    node _T_2024 = bits(_T_2018, 7, 7) @[lsu_bus_buffer.scala 389:57]
+    node _T_2025 = or(_T_2023, _T_2024) @[lsu_bus_buffer.scala 389:54]
+    node _T_2026 = bits(_T_2018, 2, 2) @[lsu_bus_buffer.scala 389:64]
+    node _T_2027 = bits(_T_2018, 3, 3) @[lsu_bus_buffer.scala 389:70]
+    node _T_2028 = or(_T_2026, _T_2027) @[lsu_bus_buffer.scala 389:67]
+    node _T_2029 = bits(_T_2018, 6, 6) @[lsu_bus_buffer.scala 389:76]
+    node _T_2030 = or(_T_2028, _T_2029) @[lsu_bus_buffer.scala 389:73]
+    node _T_2031 = bits(_T_2018, 7, 7) @[lsu_bus_buffer.scala 389:82]
+    node _T_2032 = or(_T_2030, _T_2031) @[lsu_bus_buffer.scala 389:79]
+    node _T_2033 = bits(_T_2018, 1, 1) @[lsu_bus_buffer.scala 389:89]
+    node _T_2034 = bits(_T_2018, 3, 3) @[lsu_bus_buffer.scala 389:95]
+    node _T_2035 = or(_T_2033, _T_2034) @[lsu_bus_buffer.scala 389:92]
+    node _T_2036 = bits(_T_2018, 5, 5) @[lsu_bus_buffer.scala 389:101]
+    node _T_2037 = or(_T_2035, _T_2036) @[lsu_bus_buffer.scala 389:98]
+    node _T_2038 = bits(_T_2018, 7, 7) @[lsu_bus_buffer.scala 389:107]
+    node _T_2039 = or(_T_2037, _T_2038) @[lsu_bus_buffer.scala 389:104]
+    node _T_2040 = cat(_T_2025, _T_2032) @[Cat.scala 29:58]
+    node _T_2041 = cat(_T_2040, _T_2039) @[Cat.scala 29:58]
+    CmdPtr1 <= _T_2041 @[lsu_bus_buffer.scala 396:11]
+    node _T_2042 = mux(UInt<1>("h00"), UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
+    node _T_2043 = cat(_T_2042, RspPtrDec) @[Cat.scala 29:58]
+    node _T_2044 = bits(_T_2043, 4, 4) @[lsu_bus_buffer.scala 389:39]
+    node _T_2045 = bits(_T_2043, 5, 5) @[lsu_bus_buffer.scala 389:45]
+    node _T_2046 = or(_T_2044, _T_2045) @[lsu_bus_buffer.scala 389:42]
+    node _T_2047 = bits(_T_2043, 6, 6) @[lsu_bus_buffer.scala 389:51]
+    node _T_2048 = or(_T_2046, _T_2047) @[lsu_bus_buffer.scala 389:48]
+    node _T_2049 = bits(_T_2043, 7, 7) @[lsu_bus_buffer.scala 389:57]
+    node _T_2050 = or(_T_2048, _T_2049) @[lsu_bus_buffer.scala 389:54]
+    node _T_2051 = bits(_T_2043, 2, 2) @[lsu_bus_buffer.scala 389:64]
+    node _T_2052 = bits(_T_2043, 3, 3) @[lsu_bus_buffer.scala 389:70]
+    node _T_2053 = or(_T_2051, _T_2052) @[lsu_bus_buffer.scala 389:67]
+    node _T_2054 = bits(_T_2043, 6, 6) @[lsu_bus_buffer.scala 389:76]
+    node _T_2055 = or(_T_2053, _T_2054) @[lsu_bus_buffer.scala 389:73]
+    node _T_2056 = bits(_T_2043, 7, 7) @[lsu_bus_buffer.scala 389:82]
+    node _T_2057 = or(_T_2055, _T_2056) @[lsu_bus_buffer.scala 389:79]
+    node _T_2058 = bits(_T_2043, 1, 1) @[lsu_bus_buffer.scala 389:89]
+    node _T_2059 = bits(_T_2043, 3, 3) @[lsu_bus_buffer.scala 389:95]
+    node _T_2060 = or(_T_2058, _T_2059) @[lsu_bus_buffer.scala 389:92]
+    node _T_2061 = bits(_T_2043, 5, 5) @[lsu_bus_buffer.scala 389:101]
+    node _T_2062 = or(_T_2060, _T_2061) @[lsu_bus_buffer.scala 389:98]
+    node _T_2063 = bits(_T_2043, 7, 7) @[lsu_bus_buffer.scala 389:107]
+    node _T_2064 = or(_T_2062, _T_2063) @[lsu_bus_buffer.scala 389:104]
+    node _T_2065 = cat(_T_2050, _T_2057) @[Cat.scala 29:58]
+    node _T_2066 = cat(_T_2065, _T_2064) @[Cat.scala 29:58]
+    RspPtr <= _T_2066 @[lsu_bus_buffer.scala 397:10]
+    wire buf_state_en : UInt<1>[4] @[lsu_bus_buffer.scala 398:26]
+    buf_state_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 399:16]
+    buf_state_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 399:16]
+    buf_state_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 399:16]
+    buf_state_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 399:16]
+    wire buf_rspageQ : UInt<4>[4] @[lsu_bus_buffer.scala 400:25]
+    buf_rspageQ[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 401:15]
+    buf_rspageQ[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 401:15]
+    buf_rspageQ[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 401:15]
+    buf_rspageQ[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 401:15]
+    wire buf_rspage_set : UInt<4>[4] @[lsu_bus_buffer.scala 402:28]
+    buf_rspage_set[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 403:18]
+    buf_rspage_set[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 403:18]
+    buf_rspage_set[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 403:18]
+    buf_rspage_set[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 403:18]
+    wire buf_rspage_in : UInt<4>[4] @[lsu_bus_buffer.scala 404:27]
+    buf_rspage_in[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 405:17]
+    buf_rspage_in[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 405:17]
+    buf_rspage_in[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 405:17]
+    buf_rspage_in[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 405:17]
+    wire buf_rspage : UInt<4>[4] @[lsu_bus_buffer.scala 406:24]
+    buf_rspage[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 407:14]
+    buf_rspage[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 407:14]
+    buf_rspage[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 407:14]
+    buf_rspage[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 407:14]
+    node _T_2067 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 409:83]
+    node _T_2068 = and(_T_2067, buf_state_en[0]) @[lsu_bus_buffer.scala 409:94]
+    node _T_2069 = eq(buf_state[0], UInt<3>("h01")) @[lsu_bus_buffer.scala 410:20]
+    node _T_2070 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 410:47]
+    node _T_2071 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 410:59]
+    node _T_2072 = and(_T_2070, _T_2071) @[lsu_bus_buffer.scala 410:57]
+    node _T_2073 = or(_T_2069, _T_2072) @[lsu_bus_buffer.scala 410:31]
+    node _T_2074 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 411:23]
+    node _T_2075 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 411:53]
+    node _T_2076 = and(_T_2074, _T_2075) @[lsu_bus_buffer.scala 411:41]
+    node _T_2077 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 411:83]
+    node _T_2078 = and(_T_2076, _T_2077) @[lsu_bus_buffer.scala 411:71]
+    node _T_2079 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 411:104]
+    node _T_2080 = and(_T_2078, _T_2079) @[lsu_bus_buffer.scala 411:92]
+    node _T_2081 = or(_T_2073, _T_2080) @[lsu_bus_buffer.scala 410:86]
+    node _T_2082 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 412:17]
+    node _T_2083 = and(_T_2082, io.ldst_dual_r) @[lsu_bus_buffer.scala 412:35]
+    node _T_2084 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 412:64]
+    node _T_2085 = and(_T_2083, _T_2084) @[lsu_bus_buffer.scala 412:52]
+    node _T_2086 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 412:85]
+    node _T_2087 = and(_T_2085, _T_2086) @[lsu_bus_buffer.scala 412:73]
+    node _T_2088 = or(_T_2081, _T_2087) @[lsu_bus_buffer.scala 411:114]
+    node _T_2089 = and(_T_2068, _T_2088) @[lsu_bus_buffer.scala 409:113]
+    node _T_2090 = bits(buf_age[0], 0, 0) @[lsu_bus_buffer.scala 412:109]
+    node _T_2091 = or(_T_2089, _T_2090) @[lsu_bus_buffer.scala 412:97]
+    node _T_2092 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 409:83]
+    node _T_2093 = and(_T_2092, buf_state_en[0]) @[lsu_bus_buffer.scala 409:94]
+    node _T_2094 = eq(buf_state[1], UInt<3>("h01")) @[lsu_bus_buffer.scala 410:20]
+    node _T_2095 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 410:47]
+    node _T_2096 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 410:59]
+    node _T_2097 = and(_T_2095, _T_2096) @[lsu_bus_buffer.scala 410:57]
+    node _T_2098 = or(_T_2094, _T_2097) @[lsu_bus_buffer.scala 410:31]
+    node _T_2099 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 411:23]
+    node _T_2100 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 411:53]
+    node _T_2101 = and(_T_2099, _T_2100) @[lsu_bus_buffer.scala 411:41]
+    node _T_2102 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 411:83]
+    node _T_2103 = and(_T_2101, _T_2102) @[lsu_bus_buffer.scala 411:71]
+    node _T_2104 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 411:104]
+    node _T_2105 = and(_T_2103, _T_2104) @[lsu_bus_buffer.scala 411:92]
+    node _T_2106 = or(_T_2098, _T_2105) @[lsu_bus_buffer.scala 410:86]
+    node _T_2107 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 412:17]
+    node _T_2108 = and(_T_2107, io.ldst_dual_r) @[lsu_bus_buffer.scala 412:35]
+    node _T_2109 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 412:64]
+    node _T_2110 = and(_T_2108, _T_2109) @[lsu_bus_buffer.scala 412:52]
+    node _T_2111 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 412:85]
+    node _T_2112 = and(_T_2110, _T_2111) @[lsu_bus_buffer.scala 412:73]
+    node _T_2113 = or(_T_2106, _T_2112) @[lsu_bus_buffer.scala 411:114]
+    node _T_2114 = and(_T_2093, _T_2113) @[lsu_bus_buffer.scala 409:113]
+    node _T_2115 = bits(buf_age[0], 1, 1) @[lsu_bus_buffer.scala 412:109]
+    node _T_2116 = or(_T_2114, _T_2115) @[lsu_bus_buffer.scala 412:97]
+    node _T_2117 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 409:83]
+    node _T_2118 = and(_T_2117, buf_state_en[0]) @[lsu_bus_buffer.scala 409:94]
+    node _T_2119 = eq(buf_state[2], UInt<3>("h01")) @[lsu_bus_buffer.scala 410:20]
+    node _T_2120 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 410:47]
+    node _T_2121 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 410:59]
+    node _T_2122 = and(_T_2120, _T_2121) @[lsu_bus_buffer.scala 410:57]
+    node _T_2123 = or(_T_2119, _T_2122) @[lsu_bus_buffer.scala 410:31]
+    node _T_2124 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 411:23]
+    node _T_2125 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 411:53]
+    node _T_2126 = and(_T_2124, _T_2125) @[lsu_bus_buffer.scala 411:41]
+    node _T_2127 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 411:83]
+    node _T_2128 = and(_T_2126, _T_2127) @[lsu_bus_buffer.scala 411:71]
+    node _T_2129 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 411:104]
+    node _T_2130 = and(_T_2128, _T_2129) @[lsu_bus_buffer.scala 411:92]
+    node _T_2131 = or(_T_2123, _T_2130) @[lsu_bus_buffer.scala 410:86]
+    node _T_2132 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 412:17]
+    node _T_2133 = and(_T_2132, io.ldst_dual_r) @[lsu_bus_buffer.scala 412:35]
+    node _T_2134 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 412:64]
+    node _T_2135 = and(_T_2133, _T_2134) @[lsu_bus_buffer.scala 412:52]
+    node _T_2136 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 412:85]
+    node _T_2137 = and(_T_2135, _T_2136) @[lsu_bus_buffer.scala 412:73]
+    node _T_2138 = or(_T_2131, _T_2137) @[lsu_bus_buffer.scala 411:114]
+    node _T_2139 = and(_T_2118, _T_2138) @[lsu_bus_buffer.scala 409:113]
+    node _T_2140 = bits(buf_age[0], 2, 2) @[lsu_bus_buffer.scala 412:109]
+    node _T_2141 = or(_T_2139, _T_2140) @[lsu_bus_buffer.scala 412:97]
+    node _T_2142 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 409:83]
+    node _T_2143 = and(_T_2142, buf_state_en[0]) @[lsu_bus_buffer.scala 409:94]
+    node _T_2144 = eq(buf_state[3], UInt<3>("h01")) @[lsu_bus_buffer.scala 410:20]
+    node _T_2145 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 410:47]
+    node _T_2146 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 410:59]
+    node _T_2147 = and(_T_2145, _T_2146) @[lsu_bus_buffer.scala 410:57]
+    node _T_2148 = or(_T_2144, _T_2147) @[lsu_bus_buffer.scala 410:31]
+    node _T_2149 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 411:23]
+    node _T_2150 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 411:53]
+    node _T_2151 = and(_T_2149, _T_2150) @[lsu_bus_buffer.scala 411:41]
+    node _T_2152 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 411:83]
+    node _T_2153 = and(_T_2151, _T_2152) @[lsu_bus_buffer.scala 411:71]
+    node _T_2154 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 411:104]
+    node _T_2155 = and(_T_2153, _T_2154) @[lsu_bus_buffer.scala 411:92]
+    node _T_2156 = or(_T_2148, _T_2155) @[lsu_bus_buffer.scala 410:86]
+    node _T_2157 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 412:17]
+    node _T_2158 = and(_T_2157, io.ldst_dual_r) @[lsu_bus_buffer.scala 412:35]
+    node _T_2159 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 412:64]
+    node _T_2160 = and(_T_2158, _T_2159) @[lsu_bus_buffer.scala 412:52]
+    node _T_2161 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 412:85]
+    node _T_2162 = and(_T_2160, _T_2161) @[lsu_bus_buffer.scala 412:73]
+    node _T_2163 = or(_T_2156, _T_2162) @[lsu_bus_buffer.scala 411:114]
+    node _T_2164 = and(_T_2143, _T_2163) @[lsu_bus_buffer.scala 409:113]
+    node _T_2165 = bits(buf_age[0], 3, 3) @[lsu_bus_buffer.scala 412:109]
+    node _T_2166 = or(_T_2164, _T_2165) @[lsu_bus_buffer.scala 412:97]
+    node _T_2167 = cat(_T_2166, _T_2141) @[Cat.scala 29:58]
+    node _T_2168 = cat(_T_2167, _T_2116) @[Cat.scala 29:58]
+    node buf_age_in_0 = cat(_T_2168, _T_2091) @[Cat.scala 29:58]
+    node _T_2169 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 409:83]
+    node _T_2170 = and(_T_2169, buf_state_en[1]) @[lsu_bus_buffer.scala 409:94]
+    node _T_2171 = eq(buf_state[0], UInt<3>("h01")) @[lsu_bus_buffer.scala 410:20]
+    node _T_2172 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 410:47]
+    node _T_2173 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 410:59]
+    node _T_2174 = and(_T_2172, _T_2173) @[lsu_bus_buffer.scala 410:57]
+    node _T_2175 = or(_T_2171, _T_2174) @[lsu_bus_buffer.scala 410:31]
+    node _T_2176 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 411:23]
+    node _T_2177 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 411:53]
+    node _T_2178 = and(_T_2176, _T_2177) @[lsu_bus_buffer.scala 411:41]
+    node _T_2179 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 411:83]
+    node _T_2180 = and(_T_2178, _T_2179) @[lsu_bus_buffer.scala 411:71]
+    node _T_2181 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 411:104]
+    node _T_2182 = and(_T_2180, _T_2181) @[lsu_bus_buffer.scala 411:92]
+    node _T_2183 = or(_T_2175, _T_2182) @[lsu_bus_buffer.scala 410:86]
+    node _T_2184 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 412:17]
+    node _T_2185 = and(_T_2184, io.ldst_dual_r) @[lsu_bus_buffer.scala 412:35]
+    node _T_2186 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 412:64]
+    node _T_2187 = and(_T_2185, _T_2186) @[lsu_bus_buffer.scala 412:52]
+    node _T_2188 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 412:85]
+    node _T_2189 = and(_T_2187, _T_2188) @[lsu_bus_buffer.scala 412:73]
+    node _T_2190 = or(_T_2183, _T_2189) @[lsu_bus_buffer.scala 411:114]
+    node _T_2191 = and(_T_2170, _T_2190) @[lsu_bus_buffer.scala 409:113]
+    node _T_2192 = bits(buf_age[1], 0, 0) @[lsu_bus_buffer.scala 412:109]
+    node _T_2193 = or(_T_2191, _T_2192) @[lsu_bus_buffer.scala 412:97]
+    node _T_2194 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 409:83]
+    node _T_2195 = and(_T_2194, buf_state_en[1]) @[lsu_bus_buffer.scala 409:94]
+    node _T_2196 = eq(buf_state[1], UInt<3>("h01")) @[lsu_bus_buffer.scala 410:20]
+    node _T_2197 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 410:47]
+    node _T_2198 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 410:59]
+    node _T_2199 = and(_T_2197, _T_2198) @[lsu_bus_buffer.scala 410:57]
+    node _T_2200 = or(_T_2196, _T_2199) @[lsu_bus_buffer.scala 410:31]
+    node _T_2201 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 411:23]
+    node _T_2202 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 411:53]
+    node _T_2203 = and(_T_2201, _T_2202) @[lsu_bus_buffer.scala 411:41]
+    node _T_2204 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 411:83]
+    node _T_2205 = and(_T_2203, _T_2204) @[lsu_bus_buffer.scala 411:71]
+    node _T_2206 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 411:104]
+    node _T_2207 = and(_T_2205, _T_2206) @[lsu_bus_buffer.scala 411:92]
+    node _T_2208 = or(_T_2200, _T_2207) @[lsu_bus_buffer.scala 410:86]
+    node _T_2209 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 412:17]
+    node _T_2210 = and(_T_2209, io.ldst_dual_r) @[lsu_bus_buffer.scala 412:35]
+    node _T_2211 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 412:64]
+    node _T_2212 = and(_T_2210, _T_2211) @[lsu_bus_buffer.scala 412:52]
+    node _T_2213 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 412:85]
+    node _T_2214 = and(_T_2212, _T_2213) @[lsu_bus_buffer.scala 412:73]
+    node _T_2215 = or(_T_2208, _T_2214) @[lsu_bus_buffer.scala 411:114]
+    node _T_2216 = and(_T_2195, _T_2215) @[lsu_bus_buffer.scala 409:113]
+    node _T_2217 = bits(buf_age[1], 1, 1) @[lsu_bus_buffer.scala 412:109]
+    node _T_2218 = or(_T_2216, _T_2217) @[lsu_bus_buffer.scala 412:97]
+    node _T_2219 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 409:83]
+    node _T_2220 = and(_T_2219, buf_state_en[1]) @[lsu_bus_buffer.scala 409:94]
+    node _T_2221 = eq(buf_state[2], UInt<3>("h01")) @[lsu_bus_buffer.scala 410:20]
+    node _T_2222 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 410:47]
+    node _T_2223 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 410:59]
+    node _T_2224 = and(_T_2222, _T_2223) @[lsu_bus_buffer.scala 410:57]
+    node _T_2225 = or(_T_2221, _T_2224) @[lsu_bus_buffer.scala 410:31]
+    node _T_2226 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 411:23]
+    node _T_2227 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 411:53]
+    node _T_2228 = and(_T_2226, _T_2227) @[lsu_bus_buffer.scala 411:41]
+    node _T_2229 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 411:83]
+    node _T_2230 = and(_T_2228, _T_2229) @[lsu_bus_buffer.scala 411:71]
+    node _T_2231 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 411:104]
+    node _T_2232 = and(_T_2230, _T_2231) @[lsu_bus_buffer.scala 411:92]
+    node _T_2233 = or(_T_2225, _T_2232) @[lsu_bus_buffer.scala 410:86]
+    node _T_2234 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 412:17]
+    node _T_2235 = and(_T_2234, io.ldst_dual_r) @[lsu_bus_buffer.scala 412:35]
+    node _T_2236 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 412:64]
+    node _T_2237 = and(_T_2235, _T_2236) @[lsu_bus_buffer.scala 412:52]
+    node _T_2238 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 412:85]
+    node _T_2239 = and(_T_2237, _T_2238) @[lsu_bus_buffer.scala 412:73]
+    node _T_2240 = or(_T_2233, _T_2239) @[lsu_bus_buffer.scala 411:114]
+    node _T_2241 = and(_T_2220, _T_2240) @[lsu_bus_buffer.scala 409:113]
+    node _T_2242 = bits(buf_age[1], 2, 2) @[lsu_bus_buffer.scala 412:109]
+    node _T_2243 = or(_T_2241, _T_2242) @[lsu_bus_buffer.scala 412:97]
+    node _T_2244 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 409:83]
+    node _T_2245 = and(_T_2244, buf_state_en[1]) @[lsu_bus_buffer.scala 409:94]
+    node _T_2246 = eq(buf_state[3], UInt<3>("h01")) @[lsu_bus_buffer.scala 410:20]
+    node _T_2247 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 410:47]
+    node _T_2248 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 410:59]
+    node _T_2249 = and(_T_2247, _T_2248) @[lsu_bus_buffer.scala 410:57]
+    node _T_2250 = or(_T_2246, _T_2249) @[lsu_bus_buffer.scala 410:31]
+    node _T_2251 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 411:23]
+    node _T_2252 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 411:53]
+    node _T_2253 = and(_T_2251, _T_2252) @[lsu_bus_buffer.scala 411:41]
+    node _T_2254 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 411:83]
+    node _T_2255 = and(_T_2253, _T_2254) @[lsu_bus_buffer.scala 411:71]
+    node _T_2256 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 411:104]
+    node _T_2257 = and(_T_2255, _T_2256) @[lsu_bus_buffer.scala 411:92]
+    node _T_2258 = or(_T_2250, _T_2257) @[lsu_bus_buffer.scala 410:86]
+    node _T_2259 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 412:17]
+    node _T_2260 = and(_T_2259, io.ldst_dual_r) @[lsu_bus_buffer.scala 412:35]
+    node _T_2261 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 412:64]
+    node _T_2262 = and(_T_2260, _T_2261) @[lsu_bus_buffer.scala 412:52]
+    node _T_2263 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 412:85]
+    node _T_2264 = and(_T_2262, _T_2263) @[lsu_bus_buffer.scala 412:73]
+    node _T_2265 = or(_T_2258, _T_2264) @[lsu_bus_buffer.scala 411:114]
+    node _T_2266 = and(_T_2245, _T_2265) @[lsu_bus_buffer.scala 409:113]
+    node _T_2267 = bits(buf_age[1], 3, 3) @[lsu_bus_buffer.scala 412:109]
+    node _T_2268 = or(_T_2266, _T_2267) @[lsu_bus_buffer.scala 412:97]
+    node _T_2269 = cat(_T_2268, _T_2243) @[Cat.scala 29:58]
+    node _T_2270 = cat(_T_2269, _T_2218) @[Cat.scala 29:58]
+    node buf_age_in_1 = cat(_T_2270, _T_2193) @[Cat.scala 29:58]
+    node _T_2271 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 409:83]
+    node _T_2272 = and(_T_2271, buf_state_en[2]) @[lsu_bus_buffer.scala 409:94]
+    node _T_2273 = eq(buf_state[0], UInt<3>("h01")) @[lsu_bus_buffer.scala 410:20]
+    node _T_2274 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 410:47]
+    node _T_2275 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 410:59]
+    node _T_2276 = and(_T_2274, _T_2275) @[lsu_bus_buffer.scala 410:57]
+    node _T_2277 = or(_T_2273, _T_2276) @[lsu_bus_buffer.scala 410:31]
+    node _T_2278 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 411:23]
+    node _T_2279 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 411:53]
+    node _T_2280 = and(_T_2278, _T_2279) @[lsu_bus_buffer.scala 411:41]
+    node _T_2281 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 411:83]
+    node _T_2282 = and(_T_2280, _T_2281) @[lsu_bus_buffer.scala 411:71]
+    node _T_2283 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 411:104]
+    node _T_2284 = and(_T_2282, _T_2283) @[lsu_bus_buffer.scala 411:92]
+    node _T_2285 = or(_T_2277, _T_2284) @[lsu_bus_buffer.scala 410:86]
+    node _T_2286 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 412:17]
+    node _T_2287 = and(_T_2286, io.ldst_dual_r) @[lsu_bus_buffer.scala 412:35]
+    node _T_2288 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 412:64]
+    node _T_2289 = and(_T_2287, _T_2288) @[lsu_bus_buffer.scala 412:52]
+    node _T_2290 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 412:85]
+    node _T_2291 = and(_T_2289, _T_2290) @[lsu_bus_buffer.scala 412:73]
+    node _T_2292 = or(_T_2285, _T_2291) @[lsu_bus_buffer.scala 411:114]
+    node _T_2293 = and(_T_2272, _T_2292) @[lsu_bus_buffer.scala 409:113]
+    node _T_2294 = bits(buf_age[2], 0, 0) @[lsu_bus_buffer.scala 412:109]
+    node _T_2295 = or(_T_2293, _T_2294) @[lsu_bus_buffer.scala 412:97]
+    node _T_2296 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 409:83]
+    node _T_2297 = and(_T_2296, buf_state_en[2]) @[lsu_bus_buffer.scala 409:94]
+    node _T_2298 = eq(buf_state[1], UInt<3>("h01")) @[lsu_bus_buffer.scala 410:20]
+    node _T_2299 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 410:47]
+    node _T_2300 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 410:59]
+    node _T_2301 = and(_T_2299, _T_2300) @[lsu_bus_buffer.scala 410:57]
+    node _T_2302 = or(_T_2298, _T_2301) @[lsu_bus_buffer.scala 410:31]
+    node _T_2303 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 411:23]
+    node _T_2304 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 411:53]
+    node _T_2305 = and(_T_2303, _T_2304) @[lsu_bus_buffer.scala 411:41]
+    node _T_2306 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 411:83]
+    node _T_2307 = and(_T_2305, _T_2306) @[lsu_bus_buffer.scala 411:71]
+    node _T_2308 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 411:104]
+    node _T_2309 = and(_T_2307, _T_2308) @[lsu_bus_buffer.scala 411:92]
+    node _T_2310 = or(_T_2302, _T_2309) @[lsu_bus_buffer.scala 410:86]
+    node _T_2311 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 412:17]
+    node _T_2312 = and(_T_2311, io.ldst_dual_r) @[lsu_bus_buffer.scala 412:35]
+    node _T_2313 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 412:64]
+    node _T_2314 = and(_T_2312, _T_2313) @[lsu_bus_buffer.scala 412:52]
+    node _T_2315 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 412:85]
+    node _T_2316 = and(_T_2314, _T_2315) @[lsu_bus_buffer.scala 412:73]
+    node _T_2317 = or(_T_2310, _T_2316) @[lsu_bus_buffer.scala 411:114]
+    node _T_2318 = and(_T_2297, _T_2317) @[lsu_bus_buffer.scala 409:113]
+    node _T_2319 = bits(buf_age[2], 1, 1) @[lsu_bus_buffer.scala 412:109]
+    node _T_2320 = or(_T_2318, _T_2319) @[lsu_bus_buffer.scala 412:97]
+    node _T_2321 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 409:83]
+    node _T_2322 = and(_T_2321, buf_state_en[2]) @[lsu_bus_buffer.scala 409:94]
+    node _T_2323 = eq(buf_state[2], UInt<3>("h01")) @[lsu_bus_buffer.scala 410:20]
+    node _T_2324 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 410:47]
+    node _T_2325 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 410:59]
+    node _T_2326 = and(_T_2324, _T_2325) @[lsu_bus_buffer.scala 410:57]
+    node _T_2327 = or(_T_2323, _T_2326) @[lsu_bus_buffer.scala 410:31]
+    node _T_2328 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 411:23]
+    node _T_2329 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 411:53]
+    node _T_2330 = and(_T_2328, _T_2329) @[lsu_bus_buffer.scala 411:41]
+    node _T_2331 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 411:83]
+    node _T_2332 = and(_T_2330, _T_2331) @[lsu_bus_buffer.scala 411:71]
+    node _T_2333 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 411:104]
+    node _T_2334 = and(_T_2332, _T_2333) @[lsu_bus_buffer.scala 411:92]
+    node _T_2335 = or(_T_2327, _T_2334) @[lsu_bus_buffer.scala 410:86]
+    node _T_2336 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 412:17]
+    node _T_2337 = and(_T_2336, io.ldst_dual_r) @[lsu_bus_buffer.scala 412:35]
+    node _T_2338 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 412:64]
+    node _T_2339 = and(_T_2337, _T_2338) @[lsu_bus_buffer.scala 412:52]
+    node _T_2340 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 412:85]
+    node _T_2341 = and(_T_2339, _T_2340) @[lsu_bus_buffer.scala 412:73]
+    node _T_2342 = or(_T_2335, _T_2341) @[lsu_bus_buffer.scala 411:114]
+    node _T_2343 = and(_T_2322, _T_2342) @[lsu_bus_buffer.scala 409:113]
+    node _T_2344 = bits(buf_age[2], 2, 2) @[lsu_bus_buffer.scala 412:109]
+    node _T_2345 = or(_T_2343, _T_2344) @[lsu_bus_buffer.scala 412:97]
+    node _T_2346 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 409:83]
+    node _T_2347 = and(_T_2346, buf_state_en[2]) @[lsu_bus_buffer.scala 409:94]
+    node _T_2348 = eq(buf_state[3], UInt<3>("h01")) @[lsu_bus_buffer.scala 410:20]
+    node _T_2349 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 410:47]
+    node _T_2350 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 410:59]
+    node _T_2351 = and(_T_2349, _T_2350) @[lsu_bus_buffer.scala 410:57]
+    node _T_2352 = or(_T_2348, _T_2351) @[lsu_bus_buffer.scala 410:31]
+    node _T_2353 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 411:23]
+    node _T_2354 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 411:53]
+    node _T_2355 = and(_T_2353, _T_2354) @[lsu_bus_buffer.scala 411:41]
+    node _T_2356 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 411:83]
+    node _T_2357 = and(_T_2355, _T_2356) @[lsu_bus_buffer.scala 411:71]
+    node _T_2358 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 411:104]
+    node _T_2359 = and(_T_2357, _T_2358) @[lsu_bus_buffer.scala 411:92]
+    node _T_2360 = or(_T_2352, _T_2359) @[lsu_bus_buffer.scala 410:86]
+    node _T_2361 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 412:17]
+    node _T_2362 = and(_T_2361, io.ldst_dual_r) @[lsu_bus_buffer.scala 412:35]
+    node _T_2363 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 412:64]
+    node _T_2364 = and(_T_2362, _T_2363) @[lsu_bus_buffer.scala 412:52]
+    node _T_2365 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 412:85]
+    node _T_2366 = and(_T_2364, _T_2365) @[lsu_bus_buffer.scala 412:73]
+    node _T_2367 = or(_T_2360, _T_2366) @[lsu_bus_buffer.scala 411:114]
+    node _T_2368 = and(_T_2347, _T_2367) @[lsu_bus_buffer.scala 409:113]
+    node _T_2369 = bits(buf_age[2], 3, 3) @[lsu_bus_buffer.scala 412:109]
+    node _T_2370 = or(_T_2368, _T_2369) @[lsu_bus_buffer.scala 412:97]
+    node _T_2371 = cat(_T_2370, _T_2345) @[Cat.scala 29:58]
+    node _T_2372 = cat(_T_2371, _T_2320) @[Cat.scala 29:58]
+    node buf_age_in_2 = cat(_T_2372, _T_2295) @[Cat.scala 29:58]
+    node _T_2373 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 409:83]
+    node _T_2374 = and(_T_2373, buf_state_en[3]) @[lsu_bus_buffer.scala 409:94]
+    node _T_2375 = eq(buf_state[0], UInt<3>("h01")) @[lsu_bus_buffer.scala 410:20]
+    node _T_2376 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 410:47]
+    node _T_2377 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 410:59]
+    node _T_2378 = and(_T_2376, _T_2377) @[lsu_bus_buffer.scala 410:57]
+    node _T_2379 = or(_T_2375, _T_2378) @[lsu_bus_buffer.scala 410:31]
+    node _T_2380 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 411:23]
+    node _T_2381 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 411:53]
+    node _T_2382 = and(_T_2380, _T_2381) @[lsu_bus_buffer.scala 411:41]
+    node _T_2383 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 411:83]
+    node _T_2384 = and(_T_2382, _T_2383) @[lsu_bus_buffer.scala 411:71]
+    node _T_2385 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 411:104]
+    node _T_2386 = and(_T_2384, _T_2385) @[lsu_bus_buffer.scala 411:92]
+    node _T_2387 = or(_T_2379, _T_2386) @[lsu_bus_buffer.scala 410:86]
+    node _T_2388 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 412:17]
+    node _T_2389 = and(_T_2388, io.ldst_dual_r) @[lsu_bus_buffer.scala 412:35]
+    node _T_2390 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 412:64]
+    node _T_2391 = and(_T_2389, _T_2390) @[lsu_bus_buffer.scala 412:52]
+    node _T_2392 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 412:85]
+    node _T_2393 = and(_T_2391, _T_2392) @[lsu_bus_buffer.scala 412:73]
+    node _T_2394 = or(_T_2387, _T_2393) @[lsu_bus_buffer.scala 411:114]
+    node _T_2395 = and(_T_2374, _T_2394) @[lsu_bus_buffer.scala 409:113]
+    node _T_2396 = bits(buf_age[3], 0, 0) @[lsu_bus_buffer.scala 412:109]
+    node _T_2397 = or(_T_2395, _T_2396) @[lsu_bus_buffer.scala 412:97]
+    node _T_2398 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 409:83]
+    node _T_2399 = and(_T_2398, buf_state_en[3]) @[lsu_bus_buffer.scala 409:94]
+    node _T_2400 = eq(buf_state[1], UInt<3>("h01")) @[lsu_bus_buffer.scala 410:20]
+    node _T_2401 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 410:47]
+    node _T_2402 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 410:59]
+    node _T_2403 = and(_T_2401, _T_2402) @[lsu_bus_buffer.scala 410:57]
+    node _T_2404 = or(_T_2400, _T_2403) @[lsu_bus_buffer.scala 410:31]
+    node _T_2405 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 411:23]
+    node _T_2406 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 411:53]
+    node _T_2407 = and(_T_2405, _T_2406) @[lsu_bus_buffer.scala 411:41]
+    node _T_2408 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 411:83]
+    node _T_2409 = and(_T_2407, _T_2408) @[lsu_bus_buffer.scala 411:71]
+    node _T_2410 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 411:104]
+    node _T_2411 = and(_T_2409, _T_2410) @[lsu_bus_buffer.scala 411:92]
+    node _T_2412 = or(_T_2404, _T_2411) @[lsu_bus_buffer.scala 410:86]
+    node _T_2413 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 412:17]
+    node _T_2414 = and(_T_2413, io.ldst_dual_r) @[lsu_bus_buffer.scala 412:35]
+    node _T_2415 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 412:64]
+    node _T_2416 = and(_T_2414, _T_2415) @[lsu_bus_buffer.scala 412:52]
+    node _T_2417 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 412:85]
+    node _T_2418 = and(_T_2416, _T_2417) @[lsu_bus_buffer.scala 412:73]
+    node _T_2419 = or(_T_2412, _T_2418) @[lsu_bus_buffer.scala 411:114]
+    node _T_2420 = and(_T_2399, _T_2419) @[lsu_bus_buffer.scala 409:113]
+    node _T_2421 = bits(buf_age[3], 1, 1) @[lsu_bus_buffer.scala 412:109]
+    node _T_2422 = or(_T_2420, _T_2421) @[lsu_bus_buffer.scala 412:97]
+    node _T_2423 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 409:83]
+    node _T_2424 = and(_T_2423, buf_state_en[3]) @[lsu_bus_buffer.scala 409:94]
+    node _T_2425 = eq(buf_state[2], UInt<3>("h01")) @[lsu_bus_buffer.scala 410:20]
+    node _T_2426 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 410:47]
+    node _T_2427 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 410:59]
+    node _T_2428 = and(_T_2426, _T_2427) @[lsu_bus_buffer.scala 410:57]
+    node _T_2429 = or(_T_2425, _T_2428) @[lsu_bus_buffer.scala 410:31]
+    node _T_2430 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 411:23]
+    node _T_2431 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 411:53]
+    node _T_2432 = and(_T_2430, _T_2431) @[lsu_bus_buffer.scala 411:41]
+    node _T_2433 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 411:83]
+    node _T_2434 = and(_T_2432, _T_2433) @[lsu_bus_buffer.scala 411:71]
+    node _T_2435 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 411:104]
+    node _T_2436 = and(_T_2434, _T_2435) @[lsu_bus_buffer.scala 411:92]
+    node _T_2437 = or(_T_2429, _T_2436) @[lsu_bus_buffer.scala 410:86]
+    node _T_2438 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 412:17]
+    node _T_2439 = and(_T_2438, io.ldst_dual_r) @[lsu_bus_buffer.scala 412:35]
+    node _T_2440 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 412:64]
+    node _T_2441 = and(_T_2439, _T_2440) @[lsu_bus_buffer.scala 412:52]
+    node _T_2442 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 412:85]
+    node _T_2443 = and(_T_2441, _T_2442) @[lsu_bus_buffer.scala 412:73]
+    node _T_2444 = or(_T_2437, _T_2443) @[lsu_bus_buffer.scala 411:114]
+    node _T_2445 = and(_T_2424, _T_2444) @[lsu_bus_buffer.scala 409:113]
+    node _T_2446 = bits(buf_age[3], 2, 2) @[lsu_bus_buffer.scala 412:109]
+    node _T_2447 = or(_T_2445, _T_2446) @[lsu_bus_buffer.scala 412:97]
+    node _T_2448 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 409:83]
+    node _T_2449 = and(_T_2448, buf_state_en[3]) @[lsu_bus_buffer.scala 409:94]
+    node _T_2450 = eq(buf_state[3], UInt<3>("h01")) @[lsu_bus_buffer.scala 410:20]
+    node _T_2451 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 410:47]
+    node _T_2452 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 410:59]
+    node _T_2453 = and(_T_2451, _T_2452) @[lsu_bus_buffer.scala 410:57]
+    node _T_2454 = or(_T_2450, _T_2453) @[lsu_bus_buffer.scala 410:31]
+    node _T_2455 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 411:23]
+    node _T_2456 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 411:53]
+    node _T_2457 = and(_T_2455, _T_2456) @[lsu_bus_buffer.scala 411:41]
+    node _T_2458 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 411:83]
+    node _T_2459 = and(_T_2457, _T_2458) @[lsu_bus_buffer.scala 411:71]
+    node _T_2460 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 411:104]
+    node _T_2461 = and(_T_2459, _T_2460) @[lsu_bus_buffer.scala 411:92]
+    node _T_2462 = or(_T_2454, _T_2461) @[lsu_bus_buffer.scala 410:86]
+    node _T_2463 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 412:17]
+    node _T_2464 = and(_T_2463, io.ldst_dual_r) @[lsu_bus_buffer.scala 412:35]
+    node _T_2465 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 412:64]
+    node _T_2466 = and(_T_2464, _T_2465) @[lsu_bus_buffer.scala 412:52]
+    node _T_2467 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 412:85]
+    node _T_2468 = and(_T_2466, _T_2467) @[lsu_bus_buffer.scala 412:73]
+    node _T_2469 = or(_T_2462, _T_2468) @[lsu_bus_buffer.scala 411:114]
+    node _T_2470 = and(_T_2449, _T_2469) @[lsu_bus_buffer.scala 409:113]
+    node _T_2471 = bits(buf_age[3], 3, 3) @[lsu_bus_buffer.scala 412:109]
+    node _T_2472 = or(_T_2470, _T_2471) @[lsu_bus_buffer.scala 412:97]
+    node _T_2473 = cat(_T_2472, _T_2447) @[Cat.scala 29:58]
+    node _T_2474 = cat(_T_2473, _T_2422) @[Cat.scala 29:58]
+    node buf_age_in_3 = cat(_T_2474, _T_2397) @[Cat.scala 29:58]
+    wire buf_ageQ : UInt<4>[4] @[lsu_bus_buffer.scala 413:22]
+    buf_ageQ[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 414:12]
+    buf_ageQ[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 414:12]
+    buf_ageQ[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 414:12]
+    buf_ageQ[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 414:12]
+    node _T_2475 = bits(buf_ageQ[0], 0, 0) @[lsu_bus_buffer.scala 415:72]
+    node _T_2476 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 415:93]
+    node _T_2477 = and(_T_2476, buf_cmd_state_bus_en[0]) @[lsu_bus_buffer.scala 415:103]
+    node _T_2478 = eq(_T_2477, UInt<1>("h00")) @[lsu_bus_buffer.scala 415:78]
+    node _T_2479 = and(_T_2475, _T_2478) @[lsu_bus_buffer.scala 415:76]
+    node _T_2480 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 415:132]
+    node _T_2481 = and(_T_2479, _T_2480) @[lsu_bus_buffer.scala 415:130]
+    node _T_2482 = bits(buf_ageQ[0], 1, 1) @[lsu_bus_buffer.scala 415:72]
+    node _T_2483 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 415:93]
+    node _T_2484 = and(_T_2483, buf_cmd_state_bus_en[1]) @[lsu_bus_buffer.scala 415:103]
+    node _T_2485 = eq(_T_2484, UInt<1>("h00")) @[lsu_bus_buffer.scala 415:78]
+    node _T_2486 = and(_T_2482, _T_2485) @[lsu_bus_buffer.scala 415:76]
+    node _T_2487 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 415:132]
+    node _T_2488 = and(_T_2486, _T_2487) @[lsu_bus_buffer.scala 415:130]
+    node _T_2489 = bits(buf_ageQ[0], 2, 2) @[lsu_bus_buffer.scala 415:72]
+    node _T_2490 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 415:93]
+    node _T_2491 = and(_T_2490, buf_cmd_state_bus_en[2]) @[lsu_bus_buffer.scala 415:103]
+    node _T_2492 = eq(_T_2491, UInt<1>("h00")) @[lsu_bus_buffer.scala 415:78]
+    node _T_2493 = and(_T_2489, _T_2492) @[lsu_bus_buffer.scala 415:76]
+    node _T_2494 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 415:132]
+    node _T_2495 = and(_T_2493, _T_2494) @[lsu_bus_buffer.scala 415:130]
+    node _T_2496 = bits(buf_ageQ[0], 3, 3) @[lsu_bus_buffer.scala 415:72]
+    node _T_2497 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 415:93]
+    node _T_2498 = and(_T_2497, buf_cmd_state_bus_en[3]) @[lsu_bus_buffer.scala 415:103]
+    node _T_2499 = eq(_T_2498, UInt<1>("h00")) @[lsu_bus_buffer.scala 415:78]
+    node _T_2500 = and(_T_2496, _T_2499) @[lsu_bus_buffer.scala 415:76]
+    node _T_2501 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 415:132]
+    node _T_2502 = and(_T_2500, _T_2501) @[lsu_bus_buffer.scala 415:130]
+    node _T_2503 = cat(_T_2502, _T_2495) @[Cat.scala 29:58]
+    node _T_2504 = cat(_T_2503, _T_2488) @[Cat.scala 29:58]
+    node _T_2505 = cat(_T_2504, _T_2481) @[Cat.scala 29:58]
+    node _T_2506 = bits(buf_ageQ[1], 0, 0) @[lsu_bus_buffer.scala 415:72]
+    node _T_2507 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 415:93]
+    node _T_2508 = and(_T_2507, buf_cmd_state_bus_en[0]) @[lsu_bus_buffer.scala 415:103]
+    node _T_2509 = eq(_T_2508, UInt<1>("h00")) @[lsu_bus_buffer.scala 415:78]
+    node _T_2510 = and(_T_2506, _T_2509) @[lsu_bus_buffer.scala 415:76]
+    node _T_2511 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 415:132]
+    node _T_2512 = and(_T_2510, _T_2511) @[lsu_bus_buffer.scala 415:130]
+    node _T_2513 = bits(buf_ageQ[1], 1, 1) @[lsu_bus_buffer.scala 415:72]
+    node _T_2514 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 415:93]
+    node _T_2515 = and(_T_2514, buf_cmd_state_bus_en[1]) @[lsu_bus_buffer.scala 415:103]
+    node _T_2516 = eq(_T_2515, UInt<1>("h00")) @[lsu_bus_buffer.scala 415:78]
+    node _T_2517 = and(_T_2513, _T_2516) @[lsu_bus_buffer.scala 415:76]
+    node _T_2518 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 415:132]
+    node _T_2519 = and(_T_2517, _T_2518) @[lsu_bus_buffer.scala 415:130]
+    node _T_2520 = bits(buf_ageQ[1], 2, 2) @[lsu_bus_buffer.scala 415:72]
+    node _T_2521 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 415:93]
+    node _T_2522 = and(_T_2521, buf_cmd_state_bus_en[2]) @[lsu_bus_buffer.scala 415:103]
+    node _T_2523 = eq(_T_2522, UInt<1>("h00")) @[lsu_bus_buffer.scala 415:78]
+    node _T_2524 = and(_T_2520, _T_2523) @[lsu_bus_buffer.scala 415:76]
+    node _T_2525 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 415:132]
+    node _T_2526 = and(_T_2524, _T_2525) @[lsu_bus_buffer.scala 415:130]
+    node _T_2527 = bits(buf_ageQ[1], 3, 3) @[lsu_bus_buffer.scala 415:72]
+    node _T_2528 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 415:93]
+    node _T_2529 = and(_T_2528, buf_cmd_state_bus_en[3]) @[lsu_bus_buffer.scala 415:103]
+    node _T_2530 = eq(_T_2529, UInt<1>("h00")) @[lsu_bus_buffer.scala 415:78]
+    node _T_2531 = and(_T_2527, _T_2530) @[lsu_bus_buffer.scala 415:76]
+    node _T_2532 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 415:132]
+    node _T_2533 = and(_T_2531, _T_2532) @[lsu_bus_buffer.scala 415:130]
+    node _T_2534 = cat(_T_2533, _T_2526) @[Cat.scala 29:58]
+    node _T_2535 = cat(_T_2534, _T_2519) @[Cat.scala 29:58]
+    node _T_2536 = cat(_T_2535, _T_2512) @[Cat.scala 29:58]
+    node _T_2537 = bits(buf_ageQ[2], 0, 0) @[lsu_bus_buffer.scala 415:72]
+    node _T_2538 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 415:93]
+    node _T_2539 = and(_T_2538, buf_cmd_state_bus_en[0]) @[lsu_bus_buffer.scala 415:103]
+    node _T_2540 = eq(_T_2539, UInt<1>("h00")) @[lsu_bus_buffer.scala 415:78]
+    node _T_2541 = and(_T_2537, _T_2540) @[lsu_bus_buffer.scala 415:76]
+    node _T_2542 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 415:132]
+    node _T_2543 = and(_T_2541, _T_2542) @[lsu_bus_buffer.scala 415:130]
+    node _T_2544 = bits(buf_ageQ[2], 1, 1) @[lsu_bus_buffer.scala 415:72]
+    node _T_2545 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 415:93]
+    node _T_2546 = and(_T_2545, buf_cmd_state_bus_en[1]) @[lsu_bus_buffer.scala 415:103]
+    node _T_2547 = eq(_T_2546, UInt<1>("h00")) @[lsu_bus_buffer.scala 415:78]
+    node _T_2548 = and(_T_2544, _T_2547) @[lsu_bus_buffer.scala 415:76]
+    node _T_2549 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 415:132]
+    node _T_2550 = and(_T_2548, _T_2549) @[lsu_bus_buffer.scala 415:130]
+    node _T_2551 = bits(buf_ageQ[2], 2, 2) @[lsu_bus_buffer.scala 415:72]
+    node _T_2552 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 415:93]
+    node _T_2553 = and(_T_2552, buf_cmd_state_bus_en[2]) @[lsu_bus_buffer.scala 415:103]
+    node _T_2554 = eq(_T_2553, UInt<1>("h00")) @[lsu_bus_buffer.scala 415:78]
+    node _T_2555 = and(_T_2551, _T_2554) @[lsu_bus_buffer.scala 415:76]
+    node _T_2556 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 415:132]
+    node _T_2557 = and(_T_2555, _T_2556) @[lsu_bus_buffer.scala 415:130]
+    node _T_2558 = bits(buf_ageQ[2], 3, 3) @[lsu_bus_buffer.scala 415:72]
+    node _T_2559 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 415:93]
+    node _T_2560 = and(_T_2559, buf_cmd_state_bus_en[3]) @[lsu_bus_buffer.scala 415:103]
+    node _T_2561 = eq(_T_2560, UInt<1>("h00")) @[lsu_bus_buffer.scala 415:78]
+    node _T_2562 = and(_T_2558, _T_2561) @[lsu_bus_buffer.scala 415:76]
+    node _T_2563 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 415:132]
+    node _T_2564 = and(_T_2562, _T_2563) @[lsu_bus_buffer.scala 415:130]
+    node _T_2565 = cat(_T_2564, _T_2557) @[Cat.scala 29:58]
+    node _T_2566 = cat(_T_2565, _T_2550) @[Cat.scala 29:58]
+    node _T_2567 = cat(_T_2566, _T_2543) @[Cat.scala 29:58]
+    node _T_2568 = bits(buf_ageQ[3], 0, 0) @[lsu_bus_buffer.scala 415:72]
+    node _T_2569 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 415:93]
+    node _T_2570 = and(_T_2569, buf_cmd_state_bus_en[0]) @[lsu_bus_buffer.scala 415:103]
+    node _T_2571 = eq(_T_2570, UInt<1>("h00")) @[lsu_bus_buffer.scala 415:78]
+    node _T_2572 = and(_T_2568, _T_2571) @[lsu_bus_buffer.scala 415:76]
+    node _T_2573 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 415:132]
+    node _T_2574 = and(_T_2572, _T_2573) @[lsu_bus_buffer.scala 415:130]
+    node _T_2575 = bits(buf_ageQ[3], 1, 1) @[lsu_bus_buffer.scala 415:72]
+    node _T_2576 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 415:93]
+    node _T_2577 = and(_T_2576, buf_cmd_state_bus_en[1]) @[lsu_bus_buffer.scala 415:103]
+    node _T_2578 = eq(_T_2577, UInt<1>("h00")) @[lsu_bus_buffer.scala 415:78]
+    node _T_2579 = and(_T_2575, _T_2578) @[lsu_bus_buffer.scala 415:76]
+    node _T_2580 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 415:132]
+    node _T_2581 = and(_T_2579, _T_2580) @[lsu_bus_buffer.scala 415:130]
+    node _T_2582 = bits(buf_ageQ[3], 2, 2) @[lsu_bus_buffer.scala 415:72]
+    node _T_2583 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 415:93]
+    node _T_2584 = and(_T_2583, buf_cmd_state_bus_en[2]) @[lsu_bus_buffer.scala 415:103]
+    node _T_2585 = eq(_T_2584, UInt<1>("h00")) @[lsu_bus_buffer.scala 415:78]
+    node _T_2586 = and(_T_2582, _T_2585) @[lsu_bus_buffer.scala 415:76]
+    node _T_2587 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 415:132]
+    node _T_2588 = and(_T_2586, _T_2587) @[lsu_bus_buffer.scala 415:130]
+    node _T_2589 = bits(buf_ageQ[3], 3, 3) @[lsu_bus_buffer.scala 415:72]
+    node _T_2590 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 415:93]
+    node _T_2591 = and(_T_2590, buf_cmd_state_bus_en[3]) @[lsu_bus_buffer.scala 415:103]
+    node _T_2592 = eq(_T_2591, UInt<1>("h00")) @[lsu_bus_buffer.scala 415:78]
+    node _T_2593 = and(_T_2589, _T_2592) @[lsu_bus_buffer.scala 415:76]
+    node _T_2594 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 415:132]
+    node _T_2595 = and(_T_2593, _T_2594) @[lsu_bus_buffer.scala 415:130]
+    node _T_2596 = cat(_T_2595, _T_2588) @[Cat.scala 29:58]
+    node _T_2597 = cat(_T_2596, _T_2581) @[Cat.scala 29:58]
+    node _T_2598 = cat(_T_2597, _T_2574) @[Cat.scala 29:58]
+    buf_age[0] <= _T_2505 @[lsu_bus_buffer.scala 415:11]
+    buf_age[1] <= _T_2536 @[lsu_bus_buffer.scala 415:11]
+    buf_age[2] <= _T_2567 @[lsu_bus_buffer.scala 415:11]
+    buf_age[3] <= _T_2598 @[lsu_bus_buffer.scala 415:11]
+    node _T_2599 = eq(UInt<1>("h00"), UInt<1>("h00")) @[lsu_bus_buffer.scala 416:76]
+    node _T_2600 = bits(buf_age[0], 0, 0) @[lsu_bus_buffer.scala 416:100]
+    node _T_2601 = eq(_T_2600, UInt<1>("h00")) @[lsu_bus_buffer.scala 416:89]
+    node _T_2602 = neq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:119]
+    node _T_2603 = and(_T_2601, _T_2602) @[lsu_bus_buffer.scala 416:104]
+    node _T_2604 = mux(_T_2599, UInt<1>("h00"), _T_2603) @[lsu_bus_buffer.scala 416:72]
+    node _T_2605 = eq(UInt<1>("h00"), UInt<1>("h01")) @[lsu_bus_buffer.scala 416:76]
+    node _T_2606 = bits(buf_age[0], 1, 1) @[lsu_bus_buffer.scala 416:100]
+    node _T_2607 = eq(_T_2606, UInt<1>("h00")) @[lsu_bus_buffer.scala 416:89]
+    node _T_2608 = neq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:119]
+    node _T_2609 = and(_T_2607, _T_2608) @[lsu_bus_buffer.scala 416:104]
+    node _T_2610 = mux(_T_2605, UInt<1>("h00"), _T_2609) @[lsu_bus_buffer.scala 416:72]
+    node _T_2611 = eq(UInt<1>("h00"), UInt<2>("h02")) @[lsu_bus_buffer.scala 416:76]
+    node _T_2612 = bits(buf_age[0], 2, 2) @[lsu_bus_buffer.scala 416:100]
+    node _T_2613 = eq(_T_2612, UInt<1>("h00")) @[lsu_bus_buffer.scala 416:89]
+    node _T_2614 = neq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:119]
+    node _T_2615 = and(_T_2613, _T_2614) @[lsu_bus_buffer.scala 416:104]
+    node _T_2616 = mux(_T_2611, UInt<1>("h00"), _T_2615) @[lsu_bus_buffer.scala 416:72]
+    node _T_2617 = eq(UInt<1>("h00"), UInt<2>("h03")) @[lsu_bus_buffer.scala 416:76]
+    node _T_2618 = bits(buf_age[0], 3, 3) @[lsu_bus_buffer.scala 416:100]
+    node _T_2619 = eq(_T_2618, UInt<1>("h00")) @[lsu_bus_buffer.scala 416:89]
+    node _T_2620 = neq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:119]
+    node _T_2621 = and(_T_2619, _T_2620) @[lsu_bus_buffer.scala 416:104]
+    node _T_2622 = mux(_T_2617, UInt<1>("h00"), _T_2621) @[lsu_bus_buffer.scala 416:72]
+    node _T_2623 = cat(_T_2622, _T_2616) @[Cat.scala 29:58]
+    node _T_2624 = cat(_T_2623, _T_2610) @[Cat.scala 29:58]
+    node _T_2625 = cat(_T_2624, _T_2604) @[Cat.scala 29:58]
+    node _T_2626 = eq(UInt<1>("h01"), UInt<1>("h00")) @[lsu_bus_buffer.scala 416:76]
+    node _T_2627 = bits(buf_age[1], 0, 0) @[lsu_bus_buffer.scala 416:100]
+    node _T_2628 = eq(_T_2627, UInt<1>("h00")) @[lsu_bus_buffer.scala 416:89]
+    node _T_2629 = neq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:119]
+    node _T_2630 = and(_T_2628, _T_2629) @[lsu_bus_buffer.scala 416:104]
+    node _T_2631 = mux(_T_2626, UInt<1>("h00"), _T_2630) @[lsu_bus_buffer.scala 416:72]
+    node _T_2632 = eq(UInt<1>("h01"), UInt<1>("h01")) @[lsu_bus_buffer.scala 416:76]
+    node _T_2633 = bits(buf_age[1], 1, 1) @[lsu_bus_buffer.scala 416:100]
+    node _T_2634 = eq(_T_2633, UInt<1>("h00")) @[lsu_bus_buffer.scala 416:89]
+    node _T_2635 = neq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:119]
+    node _T_2636 = and(_T_2634, _T_2635) @[lsu_bus_buffer.scala 416:104]
+    node _T_2637 = mux(_T_2632, UInt<1>("h00"), _T_2636) @[lsu_bus_buffer.scala 416:72]
+    node _T_2638 = eq(UInt<1>("h01"), UInt<2>("h02")) @[lsu_bus_buffer.scala 416:76]
+    node _T_2639 = bits(buf_age[1], 2, 2) @[lsu_bus_buffer.scala 416:100]
+    node _T_2640 = eq(_T_2639, UInt<1>("h00")) @[lsu_bus_buffer.scala 416:89]
+    node _T_2641 = neq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:119]
+    node _T_2642 = and(_T_2640, _T_2641) @[lsu_bus_buffer.scala 416:104]
+    node _T_2643 = mux(_T_2638, UInt<1>("h00"), _T_2642) @[lsu_bus_buffer.scala 416:72]
+    node _T_2644 = eq(UInt<1>("h01"), UInt<2>("h03")) @[lsu_bus_buffer.scala 416:76]
+    node _T_2645 = bits(buf_age[1], 3, 3) @[lsu_bus_buffer.scala 416:100]
+    node _T_2646 = eq(_T_2645, UInt<1>("h00")) @[lsu_bus_buffer.scala 416:89]
+    node _T_2647 = neq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:119]
+    node _T_2648 = and(_T_2646, _T_2647) @[lsu_bus_buffer.scala 416:104]
+    node _T_2649 = mux(_T_2644, UInt<1>("h00"), _T_2648) @[lsu_bus_buffer.scala 416:72]
+    node _T_2650 = cat(_T_2649, _T_2643) @[Cat.scala 29:58]
+    node _T_2651 = cat(_T_2650, _T_2637) @[Cat.scala 29:58]
+    node _T_2652 = cat(_T_2651, _T_2631) @[Cat.scala 29:58]
+    node _T_2653 = eq(UInt<2>("h02"), UInt<1>("h00")) @[lsu_bus_buffer.scala 416:76]
+    node _T_2654 = bits(buf_age[2], 0, 0) @[lsu_bus_buffer.scala 416:100]
+    node _T_2655 = eq(_T_2654, UInt<1>("h00")) @[lsu_bus_buffer.scala 416:89]
+    node _T_2656 = neq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:119]
+    node _T_2657 = and(_T_2655, _T_2656) @[lsu_bus_buffer.scala 416:104]
+    node _T_2658 = mux(_T_2653, UInt<1>("h00"), _T_2657) @[lsu_bus_buffer.scala 416:72]
+    node _T_2659 = eq(UInt<2>("h02"), UInt<1>("h01")) @[lsu_bus_buffer.scala 416:76]
+    node _T_2660 = bits(buf_age[2], 1, 1) @[lsu_bus_buffer.scala 416:100]
+    node _T_2661 = eq(_T_2660, UInt<1>("h00")) @[lsu_bus_buffer.scala 416:89]
+    node _T_2662 = neq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:119]
+    node _T_2663 = and(_T_2661, _T_2662) @[lsu_bus_buffer.scala 416:104]
+    node _T_2664 = mux(_T_2659, UInt<1>("h00"), _T_2663) @[lsu_bus_buffer.scala 416:72]
+    node _T_2665 = eq(UInt<2>("h02"), UInt<2>("h02")) @[lsu_bus_buffer.scala 416:76]
+    node _T_2666 = bits(buf_age[2], 2, 2) @[lsu_bus_buffer.scala 416:100]
+    node _T_2667 = eq(_T_2666, UInt<1>("h00")) @[lsu_bus_buffer.scala 416:89]
+    node _T_2668 = neq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:119]
+    node _T_2669 = and(_T_2667, _T_2668) @[lsu_bus_buffer.scala 416:104]
+    node _T_2670 = mux(_T_2665, UInt<1>("h00"), _T_2669) @[lsu_bus_buffer.scala 416:72]
+    node _T_2671 = eq(UInt<2>("h02"), UInt<2>("h03")) @[lsu_bus_buffer.scala 416:76]
+    node _T_2672 = bits(buf_age[2], 3, 3) @[lsu_bus_buffer.scala 416:100]
+    node _T_2673 = eq(_T_2672, UInt<1>("h00")) @[lsu_bus_buffer.scala 416:89]
+    node _T_2674 = neq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:119]
+    node _T_2675 = and(_T_2673, _T_2674) @[lsu_bus_buffer.scala 416:104]
+    node _T_2676 = mux(_T_2671, UInt<1>("h00"), _T_2675) @[lsu_bus_buffer.scala 416:72]
+    node _T_2677 = cat(_T_2676, _T_2670) @[Cat.scala 29:58]
+    node _T_2678 = cat(_T_2677, _T_2664) @[Cat.scala 29:58]
+    node _T_2679 = cat(_T_2678, _T_2658) @[Cat.scala 29:58]
+    node _T_2680 = eq(UInt<2>("h03"), UInt<1>("h00")) @[lsu_bus_buffer.scala 416:76]
+    node _T_2681 = bits(buf_age[3], 0, 0) @[lsu_bus_buffer.scala 416:100]
+    node _T_2682 = eq(_T_2681, UInt<1>("h00")) @[lsu_bus_buffer.scala 416:89]
+    node _T_2683 = neq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:119]
+    node _T_2684 = and(_T_2682, _T_2683) @[lsu_bus_buffer.scala 416:104]
+    node _T_2685 = mux(_T_2680, UInt<1>("h00"), _T_2684) @[lsu_bus_buffer.scala 416:72]
+    node _T_2686 = eq(UInt<2>("h03"), UInt<1>("h01")) @[lsu_bus_buffer.scala 416:76]
+    node _T_2687 = bits(buf_age[3], 1, 1) @[lsu_bus_buffer.scala 416:100]
+    node _T_2688 = eq(_T_2687, UInt<1>("h00")) @[lsu_bus_buffer.scala 416:89]
+    node _T_2689 = neq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:119]
+    node _T_2690 = and(_T_2688, _T_2689) @[lsu_bus_buffer.scala 416:104]
+    node _T_2691 = mux(_T_2686, UInt<1>("h00"), _T_2690) @[lsu_bus_buffer.scala 416:72]
+    node _T_2692 = eq(UInt<2>("h03"), UInt<2>("h02")) @[lsu_bus_buffer.scala 416:76]
+    node _T_2693 = bits(buf_age[3], 2, 2) @[lsu_bus_buffer.scala 416:100]
+    node _T_2694 = eq(_T_2693, UInt<1>("h00")) @[lsu_bus_buffer.scala 416:89]
+    node _T_2695 = neq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:119]
+    node _T_2696 = and(_T_2694, _T_2695) @[lsu_bus_buffer.scala 416:104]
+    node _T_2697 = mux(_T_2692, UInt<1>("h00"), _T_2696) @[lsu_bus_buffer.scala 416:72]
+    node _T_2698 = eq(UInt<2>("h03"), UInt<2>("h03")) @[lsu_bus_buffer.scala 416:76]
+    node _T_2699 = bits(buf_age[3], 3, 3) @[lsu_bus_buffer.scala 416:100]
+    node _T_2700 = eq(_T_2699, UInt<1>("h00")) @[lsu_bus_buffer.scala 416:89]
+    node _T_2701 = neq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:119]
+    node _T_2702 = and(_T_2700, _T_2701) @[lsu_bus_buffer.scala 416:104]
+    node _T_2703 = mux(_T_2698, UInt<1>("h00"), _T_2702) @[lsu_bus_buffer.scala 416:72]
+    node _T_2704 = cat(_T_2703, _T_2697) @[Cat.scala 29:58]
+    node _T_2705 = cat(_T_2704, _T_2691) @[Cat.scala 29:58]
+    node _T_2706 = cat(_T_2705, _T_2685) @[Cat.scala 29:58]
+    buf_age_younger[0] <= _T_2625 @[lsu_bus_buffer.scala 416:19]
+    buf_age_younger[1] <= _T_2652 @[lsu_bus_buffer.scala 416:19]
+    buf_age_younger[2] <= _T_2679 @[lsu_bus_buffer.scala 416:19]
+    buf_age_younger[3] <= _T_2706 @[lsu_bus_buffer.scala 416:19]
+    node _T_2707 = bits(buf_rspageQ[0], 0, 0) @[lsu_bus_buffer.scala 417:83]
+    node _T_2708 = eq(buf_state[0], UInt<3>("h05")) @[lsu_bus_buffer.scala 417:102]
+    node _T_2709 = and(_T_2707, _T_2708) @[lsu_bus_buffer.scala 417:87]
+    node _T_2710 = bits(buf_rspageQ[0], 1, 1) @[lsu_bus_buffer.scala 417:83]
+    node _T_2711 = eq(buf_state[1], UInt<3>("h05")) @[lsu_bus_buffer.scala 417:102]
+    node _T_2712 = and(_T_2710, _T_2711) @[lsu_bus_buffer.scala 417:87]
+    node _T_2713 = bits(buf_rspageQ[0], 2, 2) @[lsu_bus_buffer.scala 417:83]
+    node _T_2714 = eq(buf_state[2], UInt<3>("h05")) @[lsu_bus_buffer.scala 417:102]
+    node _T_2715 = and(_T_2713, _T_2714) @[lsu_bus_buffer.scala 417:87]
+    node _T_2716 = bits(buf_rspageQ[0], 3, 3) @[lsu_bus_buffer.scala 417:83]
+    node _T_2717 = eq(buf_state[3], UInt<3>("h05")) @[lsu_bus_buffer.scala 417:102]
+    node _T_2718 = and(_T_2716, _T_2717) @[lsu_bus_buffer.scala 417:87]
+    node _T_2719 = cat(_T_2718, _T_2715) @[Cat.scala 29:58]
+    node _T_2720 = cat(_T_2719, _T_2712) @[Cat.scala 29:58]
+    node _T_2721 = cat(_T_2720, _T_2709) @[Cat.scala 29:58]
+    node _T_2722 = bits(buf_rspageQ[1], 0, 0) @[lsu_bus_buffer.scala 417:83]
+    node _T_2723 = eq(buf_state[0], UInt<3>("h05")) @[lsu_bus_buffer.scala 417:102]
+    node _T_2724 = and(_T_2722, _T_2723) @[lsu_bus_buffer.scala 417:87]
+    node _T_2725 = bits(buf_rspageQ[1], 1, 1) @[lsu_bus_buffer.scala 417:83]
+    node _T_2726 = eq(buf_state[1], UInt<3>("h05")) @[lsu_bus_buffer.scala 417:102]
+    node _T_2727 = and(_T_2725, _T_2726) @[lsu_bus_buffer.scala 417:87]
+    node _T_2728 = bits(buf_rspageQ[1], 2, 2) @[lsu_bus_buffer.scala 417:83]
+    node _T_2729 = eq(buf_state[2], UInt<3>("h05")) @[lsu_bus_buffer.scala 417:102]
+    node _T_2730 = and(_T_2728, _T_2729) @[lsu_bus_buffer.scala 417:87]
+    node _T_2731 = bits(buf_rspageQ[1], 3, 3) @[lsu_bus_buffer.scala 417:83]
+    node _T_2732 = eq(buf_state[3], UInt<3>("h05")) @[lsu_bus_buffer.scala 417:102]
+    node _T_2733 = and(_T_2731, _T_2732) @[lsu_bus_buffer.scala 417:87]
+    node _T_2734 = cat(_T_2733, _T_2730) @[Cat.scala 29:58]
+    node _T_2735 = cat(_T_2734, _T_2727) @[Cat.scala 29:58]
+    node _T_2736 = cat(_T_2735, _T_2724) @[Cat.scala 29:58]
+    node _T_2737 = bits(buf_rspageQ[2], 0, 0) @[lsu_bus_buffer.scala 417:83]
+    node _T_2738 = eq(buf_state[0], UInt<3>("h05")) @[lsu_bus_buffer.scala 417:102]
+    node _T_2739 = and(_T_2737, _T_2738) @[lsu_bus_buffer.scala 417:87]
+    node _T_2740 = bits(buf_rspageQ[2], 1, 1) @[lsu_bus_buffer.scala 417:83]
+    node _T_2741 = eq(buf_state[1], UInt<3>("h05")) @[lsu_bus_buffer.scala 417:102]
+    node _T_2742 = and(_T_2740, _T_2741) @[lsu_bus_buffer.scala 417:87]
+    node _T_2743 = bits(buf_rspageQ[2], 2, 2) @[lsu_bus_buffer.scala 417:83]
+    node _T_2744 = eq(buf_state[2], UInt<3>("h05")) @[lsu_bus_buffer.scala 417:102]
+    node _T_2745 = and(_T_2743, _T_2744) @[lsu_bus_buffer.scala 417:87]
+    node _T_2746 = bits(buf_rspageQ[2], 3, 3) @[lsu_bus_buffer.scala 417:83]
+    node _T_2747 = eq(buf_state[3], UInt<3>("h05")) @[lsu_bus_buffer.scala 417:102]
+    node _T_2748 = and(_T_2746, _T_2747) @[lsu_bus_buffer.scala 417:87]
+    node _T_2749 = cat(_T_2748, _T_2745) @[Cat.scala 29:58]
+    node _T_2750 = cat(_T_2749, _T_2742) @[Cat.scala 29:58]
+    node _T_2751 = cat(_T_2750, _T_2739) @[Cat.scala 29:58]
+    node _T_2752 = bits(buf_rspageQ[3], 0, 0) @[lsu_bus_buffer.scala 417:83]
+    node _T_2753 = eq(buf_state[0], UInt<3>("h05")) @[lsu_bus_buffer.scala 417:102]
+    node _T_2754 = and(_T_2752, _T_2753) @[lsu_bus_buffer.scala 417:87]
+    node _T_2755 = bits(buf_rspageQ[3], 1, 1) @[lsu_bus_buffer.scala 417:83]
+    node _T_2756 = eq(buf_state[1], UInt<3>("h05")) @[lsu_bus_buffer.scala 417:102]
+    node _T_2757 = and(_T_2755, _T_2756) @[lsu_bus_buffer.scala 417:87]
+    node _T_2758 = bits(buf_rspageQ[3], 2, 2) @[lsu_bus_buffer.scala 417:83]
+    node _T_2759 = eq(buf_state[2], UInt<3>("h05")) @[lsu_bus_buffer.scala 417:102]
+    node _T_2760 = and(_T_2758, _T_2759) @[lsu_bus_buffer.scala 417:87]
+    node _T_2761 = bits(buf_rspageQ[3], 3, 3) @[lsu_bus_buffer.scala 417:83]
+    node _T_2762 = eq(buf_state[3], UInt<3>("h05")) @[lsu_bus_buffer.scala 417:102]
+    node _T_2763 = and(_T_2761, _T_2762) @[lsu_bus_buffer.scala 417:87]
+    node _T_2764 = cat(_T_2763, _T_2760) @[Cat.scala 29:58]
+    node _T_2765 = cat(_T_2764, _T_2757) @[Cat.scala 29:58]
+    node _T_2766 = cat(_T_2765, _T_2754) @[Cat.scala 29:58]
+    buf_rsp_pickage[0] <= _T_2721 @[lsu_bus_buffer.scala 417:19]
+    buf_rsp_pickage[1] <= _T_2736 @[lsu_bus_buffer.scala 417:19]
+    buf_rsp_pickage[2] <= _T_2751 @[lsu_bus_buffer.scala 417:19]
+    buf_rsp_pickage[3] <= _T_2766 @[lsu_bus_buffer.scala 417:19]
+    node _T_2767 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 419:82]
+    node _T_2768 = and(_T_2767, buf_state_en[0]) @[lsu_bus_buffer.scala 419:93]
+    node _T_2769 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 420:21]
+    node _T_2770 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 420:47]
+    node _T_2771 = or(_T_2769, _T_2770) @[lsu_bus_buffer.scala 420:32]
+    node _T_2772 = eq(_T_2771, UInt<1>("h00")) @[lsu_bus_buffer.scala 420:6]
+    node _T_2773 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 421:23]
+    node _T_2774 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 421:53]
+    node _T_2775 = and(_T_2773, _T_2774) @[lsu_bus_buffer.scala 421:41]
+    node _T_2776 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 421:82]
+    node _T_2777 = and(_T_2775, _T_2776) @[lsu_bus_buffer.scala 421:71]
+    node _T_2778 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 421:101]
+    node _T_2779 = and(_T_2777, _T_2778) @[lsu_bus_buffer.scala 421:90]
+    node _T_2780 = or(_T_2772, _T_2779) @[lsu_bus_buffer.scala 420:59]
+    node _T_2781 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 422:17]
+    node _T_2782 = and(_T_2781, io.ldst_dual_r) @[lsu_bus_buffer.scala 422:35]
+    node _T_2783 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 422:63]
+    node _T_2784 = and(_T_2782, _T_2783) @[lsu_bus_buffer.scala 422:52]
+    node _T_2785 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 422:82]
+    node _T_2786 = and(_T_2784, _T_2785) @[lsu_bus_buffer.scala 422:71]
+    node _T_2787 = or(_T_2780, _T_2786) @[lsu_bus_buffer.scala 421:110]
+    node _T_2788 = and(_T_2768, _T_2787) @[lsu_bus_buffer.scala 419:112]
+    node _T_2789 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 419:82]
+    node _T_2790 = and(_T_2789, buf_state_en[0]) @[lsu_bus_buffer.scala 419:93]
+    node _T_2791 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 420:21]
+    node _T_2792 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 420:47]
+    node _T_2793 = or(_T_2791, _T_2792) @[lsu_bus_buffer.scala 420:32]
+    node _T_2794 = eq(_T_2793, UInt<1>("h00")) @[lsu_bus_buffer.scala 420:6]
+    node _T_2795 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 421:23]
+    node _T_2796 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 421:53]
+    node _T_2797 = and(_T_2795, _T_2796) @[lsu_bus_buffer.scala 421:41]
+    node _T_2798 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 421:82]
+    node _T_2799 = and(_T_2797, _T_2798) @[lsu_bus_buffer.scala 421:71]
+    node _T_2800 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 421:101]
+    node _T_2801 = and(_T_2799, _T_2800) @[lsu_bus_buffer.scala 421:90]
+    node _T_2802 = or(_T_2794, _T_2801) @[lsu_bus_buffer.scala 420:59]
+    node _T_2803 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 422:17]
+    node _T_2804 = and(_T_2803, io.ldst_dual_r) @[lsu_bus_buffer.scala 422:35]
+    node _T_2805 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 422:63]
+    node _T_2806 = and(_T_2804, _T_2805) @[lsu_bus_buffer.scala 422:52]
+    node _T_2807 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 422:82]
+    node _T_2808 = and(_T_2806, _T_2807) @[lsu_bus_buffer.scala 422:71]
+    node _T_2809 = or(_T_2802, _T_2808) @[lsu_bus_buffer.scala 421:110]
+    node _T_2810 = and(_T_2790, _T_2809) @[lsu_bus_buffer.scala 419:112]
+    node _T_2811 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 419:82]
+    node _T_2812 = and(_T_2811, buf_state_en[0]) @[lsu_bus_buffer.scala 419:93]
+    node _T_2813 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 420:21]
+    node _T_2814 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 420:47]
+    node _T_2815 = or(_T_2813, _T_2814) @[lsu_bus_buffer.scala 420:32]
+    node _T_2816 = eq(_T_2815, UInt<1>("h00")) @[lsu_bus_buffer.scala 420:6]
+    node _T_2817 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 421:23]
+    node _T_2818 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 421:53]
+    node _T_2819 = and(_T_2817, _T_2818) @[lsu_bus_buffer.scala 421:41]
+    node _T_2820 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 421:82]
+    node _T_2821 = and(_T_2819, _T_2820) @[lsu_bus_buffer.scala 421:71]
+    node _T_2822 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 421:101]
+    node _T_2823 = and(_T_2821, _T_2822) @[lsu_bus_buffer.scala 421:90]
+    node _T_2824 = or(_T_2816, _T_2823) @[lsu_bus_buffer.scala 420:59]
+    node _T_2825 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 422:17]
+    node _T_2826 = and(_T_2825, io.ldst_dual_r) @[lsu_bus_buffer.scala 422:35]
+    node _T_2827 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 422:63]
+    node _T_2828 = and(_T_2826, _T_2827) @[lsu_bus_buffer.scala 422:52]
+    node _T_2829 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 422:82]
+    node _T_2830 = and(_T_2828, _T_2829) @[lsu_bus_buffer.scala 422:71]
+    node _T_2831 = or(_T_2824, _T_2830) @[lsu_bus_buffer.scala 421:110]
+    node _T_2832 = and(_T_2812, _T_2831) @[lsu_bus_buffer.scala 419:112]
+    node _T_2833 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 419:82]
+    node _T_2834 = and(_T_2833, buf_state_en[0]) @[lsu_bus_buffer.scala 419:93]
+    node _T_2835 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 420:21]
+    node _T_2836 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 420:47]
+    node _T_2837 = or(_T_2835, _T_2836) @[lsu_bus_buffer.scala 420:32]
+    node _T_2838 = eq(_T_2837, UInt<1>("h00")) @[lsu_bus_buffer.scala 420:6]
+    node _T_2839 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 421:23]
+    node _T_2840 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 421:53]
+    node _T_2841 = and(_T_2839, _T_2840) @[lsu_bus_buffer.scala 421:41]
+    node _T_2842 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 421:82]
+    node _T_2843 = and(_T_2841, _T_2842) @[lsu_bus_buffer.scala 421:71]
+    node _T_2844 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 421:101]
+    node _T_2845 = and(_T_2843, _T_2844) @[lsu_bus_buffer.scala 421:90]
+    node _T_2846 = or(_T_2838, _T_2845) @[lsu_bus_buffer.scala 420:59]
+    node _T_2847 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 422:17]
+    node _T_2848 = and(_T_2847, io.ldst_dual_r) @[lsu_bus_buffer.scala 422:35]
+    node _T_2849 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 422:63]
+    node _T_2850 = and(_T_2848, _T_2849) @[lsu_bus_buffer.scala 422:52]
+    node _T_2851 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 422:82]
+    node _T_2852 = and(_T_2850, _T_2851) @[lsu_bus_buffer.scala 422:71]
+    node _T_2853 = or(_T_2846, _T_2852) @[lsu_bus_buffer.scala 421:110]
+    node _T_2854 = and(_T_2834, _T_2853) @[lsu_bus_buffer.scala 419:112]
+    node _T_2855 = cat(_T_2854, _T_2832) @[Cat.scala 29:58]
+    node _T_2856 = cat(_T_2855, _T_2810) @[Cat.scala 29:58]
+    node _T_2857 = cat(_T_2856, _T_2788) @[Cat.scala 29:58]
+    node _T_2858 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 419:82]
+    node _T_2859 = and(_T_2858, buf_state_en[1]) @[lsu_bus_buffer.scala 419:93]
+    node _T_2860 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 420:21]
+    node _T_2861 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 420:47]
+    node _T_2862 = or(_T_2860, _T_2861) @[lsu_bus_buffer.scala 420:32]
+    node _T_2863 = eq(_T_2862, UInt<1>("h00")) @[lsu_bus_buffer.scala 420:6]
+    node _T_2864 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 421:23]
+    node _T_2865 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 421:53]
+    node _T_2866 = and(_T_2864, _T_2865) @[lsu_bus_buffer.scala 421:41]
+    node _T_2867 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 421:82]
+    node _T_2868 = and(_T_2866, _T_2867) @[lsu_bus_buffer.scala 421:71]
+    node _T_2869 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 421:101]
+    node _T_2870 = and(_T_2868, _T_2869) @[lsu_bus_buffer.scala 421:90]
+    node _T_2871 = or(_T_2863, _T_2870) @[lsu_bus_buffer.scala 420:59]
+    node _T_2872 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 422:17]
+    node _T_2873 = and(_T_2872, io.ldst_dual_r) @[lsu_bus_buffer.scala 422:35]
+    node _T_2874 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 422:63]
+    node _T_2875 = and(_T_2873, _T_2874) @[lsu_bus_buffer.scala 422:52]
+    node _T_2876 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 422:82]
+    node _T_2877 = and(_T_2875, _T_2876) @[lsu_bus_buffer.scala 422:71]
+    node _T_2878 = or(_T_2871, _T_2877) @[lsu_bus_buffer.scala 421:110]
+    node _T_2879 = and(_T_2859, _T_2878) @[lsu_bus_buffer.scala 419:112]
+    node _T_2880 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 419:82]
+    node _T_2881 = and(_T_2880, buf_state_en[1]) @[lsu_bus_buffer.scala 419:93]
+    node _T_2882 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 420:21]
+    node _T_2883 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 420:47]
+    node _T_2884 = or(_T_2882, _T_2883) @[lsu_bus_buffer.scala 420:32]
+    node _T_2885 = eq(_T_2884, UInt<1>("h00")) @[lsu_bus_buffer.scala 420:6]
+    node _T_2886 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 421:23]
+    node _T_2887 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 421:53]
+    node _T_2888 = and(_T_2886, _T_2887) @[lsu_bus_buffer.scala 421:41]
+    node _T_2889 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 421:82]
+    node _T_2890 = and(_T_2888, _T_2889) @[lsu_bus_buffer.scala 421:71]
+    node _T_2891 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 421:101]
+    node _T_2892 = and(_T_2890, _T_2891) @[lsu_bus_buffer.scala 421:90]
+    node _T_2893 = or(_T_2885, _T_2892) @[lsu_bus_buffer.scala 420:59]
+    node _T_2894 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 422:17]
+    node _T_2895 = and(_T_2894, io.ldst_dual_r) @[lsu_bus_buffer.scala 422:35]
+    node _T_2896 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 422:63]
+    node _T_2897 = and(_T_2895, _T_2896) @[lsu_bus_buffer.scala 422:52]
+    node _T_2898 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 422:82]
+    node _T_2899 = and(_T_2897, _T_2898) @[lsu_bus_buffer.scala 422:71]
+    node _T_2900 = or(_T_2893, _T_2899) @[lsu_bus_buffer.scala 421:110]
+    node _T_2901 = and(_T_2881, _T_2900) @[lsu_bus_buffer.scala 419:112]
+    node _T_2902 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 419:82]
+    node _T_2903 = and(_T_2902, buf_state_en[1]) @[lsu_bus_buffer.scala 419:93]
+    node _T_2904 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 420:21]
+    node _T_2905 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 420:47]
+    node _T_2906 = or(_T_2904, _T_2905) @[lsu_bus_buffer.scala 420:32]
+    node _T_2907 = eq(_T_2906, UInt<1>("h00")) @[lsu_bus_buffer.scala 420:6]
+    node _T_2908 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 421:23]
+    node _T_2909 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 421:53]
+    node _T_2910 = and(_T_2908, _T_2909) @[lsu_bus_buffer.scala 421:41]
+    node _T_2911 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 421:82]
+    node _T_2912 = and(_T_2910, _T_2911) @[lsu_bus_buffer.scala 421:71]
+    node _T_2913 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 421:101]
+    node _T_2914 = and(_T_2912, _T_2913) @[lsu_bus_buffer.scala 421:90]
+    node _T_2915 = or(_T_2907, _T_2914) @[lsu_bus_buffer.scala 420:59]
+    node _T_2916 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 422:17]
+    node _T_2917 = and(_T_2916, io.ldst_dual_r) @[lsu_bus_buffer.scala 422:35]
+    node _T_2918 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 422:63]
+    node _T_2919 = and(_T_2917, _T_2918) @[lsu_bus_buffer.scala 422:52]
+    node _T_2920 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 422:82]
+    node _T_2921 = and(_T_2919, _T_2920) @[lsu_bus_buffer.scala 422:71]
+    node _T_2922 = or(_T_2915, _T_2921) @[lsu_bus_buffer.scala 421:110]
+    node _T_2923 = and(_T_2903, _T_2922) @[lsu_bus_buffer.scala 419:112]
+    node _T_2924 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 419:82]
+    node _T_2925 = and(_T_2924, buf_state_en[1]) @[lsu_bus_buffer.scala 419:93]
+    node _T_2926 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 420:21]
+    node _T_2927 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 420:47]
+    node _T_2928 = or(_T_2926, _T_2927) @[lsu_bus_buffer.scala 420:32]
+    node _T_2929 = eq(_T_2928, UInt<1>("h00")) @[lsu_bus_buffer.scala 420:6]
+    node _T_2930 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 421:23]
+    node _T_2931 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 421:53]
+    node _T_2932 = and(_T_2930, _T_2931) @[lsu_bus_buffer.scala 421:41]
+    node _T_2933 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 421:82]
+    node _T_2934 = and(_T_2932, _T_2933) @[lsu_bus_buffer.scala 421:71]
+    node _T_2935 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 421:101]
+    node _T_2936 = and(_T_2934, _T_2935) @[lsu_bus_buffer.scala 421:90]
+    node _T_2937 = or(_T_2929, _T_2936) @[lsu_bus_buffer.scala 420:59]
+    node _T_2938 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 422:17]
+    node _T_2939 = and(_T_2938, io.ldst_dual_r) @[lsu_bus_buffer.scala 422:35]
+    node _T_2940 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 422:63]
+    node _T_2941 = and(_T_2939, _T_2940) @[lsu_bus_buffer.scala 422:52]
+    node _T_2942 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 422:82]
+    node _T_2943 = and(_T_2941, _T_2942) @[lsu_bus_buffer.scala 422:71]
+    node _T_2944 = or(_T_2937, _T_2943) @[lsu_bus_buffer.scala 421:110]
+    node _T_2945 = and(_T_2925, _T_2944) @[lsu_bus_buffer.scala 419:112]
+    node _T_2946 = cat(_T_2945, _T_2923) @[Cat.scala 29:58]
+    node _T_2947 = cat(_T_2946, _T_2901) @[Cat.scala 29:58]
+    node _T_2948 = cat(_T_2947, _T_2879) @[Cat.scala 29:58]
+    node _T_2949 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 419:82]
+    node _T_2950 = and(_T_2949, buf_state_en[2]) @[lsu_bus_buffer.scala 419:93]
+    node _T_2951 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 420:21]
+    node _T_2952 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 420:47]
+    node _T_2953 = or(_T_2951, _T_2952) @[lsu_bus_buffer.scala 420:32]
+    node _T_2954 = eq(_T_2953, UInt<1>("h00")) @[lsu_bus_buffer.scala 420:6]
+    node _T_2955 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 421:23]
+    node _T_2956 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 421:53]
+    node _T_2957 = and(_T_2955, _T_2956) @[lsu_bus_buffer.scala 421:41]
+    node _T_2958 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 421:82]
+    node _T_2959 = and(_T_2957, _T_2958) @[lsu_bus_buffer.scala 421:71]
+    node _T_2960 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 421:101]
+    node _T_2961 = and(_T_2959, _T_2960) @[lsu_bus_buffer.scala 421:90]
+    node _T_2962 = or(_T_2954, _T_2961) @[lsu_bus_buffer.scala 420:59]
+    node _T_2963 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 422:17]
+    node _T_2964 = and(_T_2963, io.ldst_dual_r) @[lsu_bus_buffer.scala 422:35]
+    node _T_2965 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 422:63]
+    node _T_2966 = and(_T_2964, _T_2965) @[lsu_bus_buffer.scala 422:52]
+    node _T_2967 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 422:82]
+    node _T_2968 = and(_T_2966, _T_2967) @[lsu_bus_buffer.scala 422:71]
+    node _T_2969 = or(_T_2962, _T_2968) @[lsu_bus_buffer.scala 421:110]
+    node _T_2970 = and(_T_2950, _T_2969) @[lsu_bus_buffer.scala 419:112]
+    node _T_2971 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 419:82]
+    node _T_2972 = and(_T_2971, buf_state_en[2]) @[lsu_bus_buffer.scala 419:93]
+    node _T_2973 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 420:21]
+    node _T_2974 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 420:47]
+    node _T_2975 = or(_T_2973, _T_2974) @[lsu_bus_buffer.scala 420:32]
+    node _T_2976 = eq(_T_2975, UInt<1>("h00")) @[lsu_bus_buffer.scala 420:6]
+    node _T_2977 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 421:23]
+    node _T_2978 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 421:53]
+    node _T_2979 = and(_T_2977, _T_2978) @[lsu_bus_buffer.scala 421:41]
+    node _T_2980 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 421:82]
+    node _T_2981 = and(_T_2979, _T_2980) @[lsu_bus_buffer.scala 421:71]
+    node _T_2982 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 421:101]
+    node _T_2983 = and(_T_2981, _T_2982) @[lsu_bus_buffer.scala 421:90]
+    node _T_2984 = or(_T_2976, _T_2983) @[lsu_bus_buffer.scala 420:59]
+    node _T_2985 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 422:17]
+    node _T_2986 = and(_T_2985, io.ldst_dual_r) @[lsu_bus_buffer.scala 422:35]
+    node _T_2987 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 422:63]
+    node _T_2988 = and(_T_2986, _T_2987) @[lsu_bus_buffer.scala 422:52]
+    node _T_2989 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 422:82]
+    node _T_2990 = and(_T_2988, _T_2989) @[lsu_bus_buffer.scala 422:71]
+    node _T_2991 = or(_T_2984, _T_2990) @[lsu_bus_buffer.scala 421:110]
+    node _T_2992 = and(_T_2972, _T_2991) @[lsu_bus_buffer.scala 419:112]
+    node _T_2993 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 419:82]
+    node _T_2994 = and(_T_2993, buf_state_en[2]) @[lsu_bus_buffer.scala 419:93]
+    node _T_2995 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 420:21]
+    node _T_2996 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 420:47]
+    node _T_2997 = or(_T_2995, _T_2996) @[lsu_bus_buffer.scala 420:32]
+    node _T_2998 = eq(_T_2997, UInt<1>("h00")) @[lsu_bus_buffer.scala 420:6]
+    node _T_2999 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 421:23]
+    node _T_3000 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 421:53]
+    node _T_3001 = and(_T_2999, _T_3000) @[lsu_bus_buffer.scala 421:41]
+    node _T_3002 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 421:82]
+    node _T_3003 = and(_T_3001, _T_3002) @[lsu_bus_buffer.scala 421:71]
+    node _T_3004 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 421:101]
+    node _T_3005 = and(_T_3003, _T_3004) @[lsu_bus_buffer.scala 421:90]
+    node _T_3006 = or(_T_2998, _T_3005) @[lsu_bus_buffer.scala 420:59]
+    node _T_3007 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 422:17]
+    node _T_3008 = and(_T_3007, io.ldst_dual_r) @[lsu_bus_buffer.scala 422:35]
+    node _T_3009 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 422:63]
+    node _T_3010 = and(_T_3008, _T_3009) @[lsu_bus_buffer.scala 422:52]
+    node _T_3011 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 422:82]
+    node _T_3012 = and(_T_3010, _T_3011) @[lsu_bus_buffer.scala 422:71]
+    node _T_3013 = or(_T_3006, _T_3012) @[lsu_bus_buffer.scala 421:110]
+    node _T_3014 = and(_T_2994, _T_3013) @[lsu_bus_buffer.scala 419:112]
+    node _T_3015 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 419:82]
+    node _T_3016 = and(_T_3015, buf_state_en[2]) @[lsu_bus_buffer.scala 419:93]
+    node _T_3017 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 420:21]
+    node _T_3018 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 420:47]
+    node _T_3019 = or(_T_3017, _T_3018) @[lsu_bus_buffer.scala 420:32]
+    node _T_3020 = eq(_T_3019, UInt<1>("h00")) @[lsu_bus_buffer.scala 420:6]
+    node _T_3021 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 421:23]
+    node _T_3022 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 421:53]
+    node _T_3023 = and(_T_3021, _T_3022) @[lsu_bus_buffer.scala 421:41]
+    node _T_3024 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 421:82]
+    node _T_3025 = and(_T_3023, _T_3024) @[lsu_bus_buffer.scala 421:71]
+    node _T_3026 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 421:101]
+    node _T_3027 = and(_T_3025, _T_3026) @[lsu_bus_buffer.scala 421:90]
+    node _T_3028 = or(_T_3020, _T_3027) @[lsu_bus_buffer.scala 420:59]
+    node _T_3029 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 422:17]
+    node _T_3030 = and(_T_3029, io.ldst_dual_r) @[lsu_bus_buffer.scala 422:35]
+    node _T_3031 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 422:63]
+    node _T_3032 = and(_T_3030, _T_3031) @[lsu_bus_buffer.scala 422:52]
+    node _T_3033 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 422:82]
+    node _T_3034 = and(_T_3032, _T_3033) @[lsu_bus_buffer.scala 422:71]
+    node _T_3035 = or(_T_3028, _T_3034) @[lsu_bus_buffer.scala 421:110]
+    node _T_3036 = and(_T_3016, _T_3035) @[lsu_bus_buffer.scala 419:112]
+    node _T_3037 = cat(_T_3036, _T_3014) @[Cat.scala 29:58]
+    node _T_3038 = cat(_T_3037, _T_2992) @[Cat.scala 29:58]
+    node _T_3039 = cat(_T_3038, _T_2970) @[Cat.scala 29:58]
+    node _T_3040 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 419:82]
+    node _T_3041 = and(_T_3040, buf_state_en[3]) @[lsu_bus_buffer.scala 419:93]
+    node _T_3042 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 420:21]
+    node _T_3043 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 420:47]
+    node _T_3044 = or(_T_3042, _T_3043) @[lsu_bus_buffer.scala 420:32]
+    node _T_3045 = eq(_T_3044, UInt<1>("h00")) @[lsu_bus_buffer.scala 420:6]
+    node _T_3046 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 421:23]
+    node _T_3047 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 421:53]
+    node _T_3048 = and(_T_3046, _T_3047) @[lsu_bus_buffer.scala 421:41]
+    node _T_3049 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 421:82]
+    node _T_3050 = and(_T_3048, _T_3049) @[lsu_bus_buffer.scala 421:71]
+    node _T_3051 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 421:101]
+    node _T_3052 = and(_T_3050, _T_3051) @[lsu_bus_buffer.scala 421:90]
+    node _T_3053 = or(_T_3045, _T_3052) @[lsu_bus_buffer.scala 420:59]
+    node _T_3054 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 422:17]
+    node _T_3055 = and(_T_3054, io.ldst_dual_r) @[lsu_bus_buffer.scala 422:35]
+    node _T_3056 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 422:63]
+    node _T_3057 = and(_T_3055, _T_3056) @[lsu_bus_buffer.scala 422:52]
+    node _T_3058 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 422:82]
+    node _T_3059 = and(_T_3057, _T_3058) @[lsu_bus_buffer.scala 422:71]
+    node _T_3060 = or(_T_3053, _T_3059) @[lsu_bus_buffer.scala 421:110]
+    node _T_3061 = and(_T_3041, _T_3060) @[lsu_bus_buffer.scala 419:112]
+    node _T_3062 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 419:82]
+    node _T_3063 = and(_T_3062, buf_state_en[3]) @[lsu_bus_buffer.scala 419:93]
+    node _T_3064 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 420:21]
+    node _T_3065 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 420:47]
+    node _T_3066 = or(_T_3064, _T_3065) @[lsu_bus_buffer.scala 420:32]
+    node _T_3067 = eq(_T_3066, UInt<1>("h00")) @[lsu_bus_buffer.scala 420:6]
+    node _T_3068 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 421:23]
+    node _T_3069 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 421:53]
+    node _T_3070 = and(_T_3068, _T_3069) @[lsu_bus_buffer.scala 421:41]
+    node _T_3071 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 421:82]
+    node _T_3072 = and(_T_3070, _T_3071) @[lsu_bus_buffer.scala 421:71]
+    node _T_3073 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 421:101]
+    node _T_3074 = and(_T_3072, _T_3073) @[lsu_bus_buffer.scala 421:90]
+    node _T_3075 = or(_T_3067, _T_3074) @[lsu_bus_buffer.scala 420:59]
+    node _T_3076 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 422:17]
+    node _T_3077 = and(_T_3076, io.ldst_dual_r) @[lsu_bus_buffer.scala 422:35]
+    node _T_3078 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 422:63]
+    node _T_3079 = and(_T_3077, _T_3078) @[lsu_bus_buffer.scala 422:52]
+    node _T_3080 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 422:82]
+    node _T_3081 = and(_T_3079, _T_3080) @[lsu_bus_buffer.scala 422:71]
+    node _T_3082 = or(_T_3075, _T_3081) @[lsu_bus_buffer.scala 421:110]
+    node _T_3083 = and(_T_3063, _T_3082) @[lsu_bus_buffer.scala 419:112]
+    node _T_3084 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 419:82]
+    node _T_3085 = and(_T_3084, buf_state_en[3]) @[lsu_bus_buffer.scala 419:93]
+    node _T_3086 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 420:21]
+    node _T_3087 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 420:47]
+    node _T_3088 = or(_T_3086, _T_3087) @[lsu_bus_buffer.scala 420:32]
+    node _T_3089 = eq(_T_3088, UInt<1>("h00")) @[lsu_bus_buffer.scala 420:6]
+    node _T_3090 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 421:23]
+    node _T_3091 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 421:53]
+    node _T_3092 = and(_T_3090, _T_3091) @[lsu_bus_buffer.scala 421:41]
+    node _T_3093 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 421:82]
+    node _T_3094 = and(_T_3092, _T_3093) @[lsu_bus_buffer.scala 421:71]
+    node _T_3095 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 421:101]
+    node _T_3096 = and(_T_3094, _T_3095) @[lsu_bus_buffer.scala 421:90]
+    node _T_3097 = or(_T_3089, _T_3096) @[lsu_bus_buffer.scala 420:59]
+    node _T_3098 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 422:17]
+    node _T_3099 = and(_T_3098, io.ldst_dual_r) @[lsu_bus_buffer.scala 422:35]
+    node _T_3100 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 422:63]
+    node _T_3101 = and(_T_3099, _T_3100) @[lsu_bus_buffer.scala 422:52]
+    node _T_3102 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 422:82]
+    node _T_3103 = and(_T_3101, _T_3102) @[lsu_bus_buffer.scala 422:71]
+    node _T_3104 = or(_T_3097, _T_3103) @[lsu_bus_buffer.scala 421:110]
+    node _T_3105 = and(_T_3085, _T_3104) @[lsu_bus_buffer.scala 419:112]
+    node _T_3106 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 419:82]
+    node _T_3107 = and(_T_3106, buf_state_en[3]) @[lsu_bus_buffer.scala 419:93]
+    node _T_3108 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 420:21]
+    node _T_3109 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 420:47]
+    node _T_3110 = or(_T_3108, _T_3109) @[lsu_bus_buffer.scala 420:32]
+    node _T_3111 = eq(_T_3110, UInt<1>("h00")) @[lsu_bus_buffer.scala 420:6]
+    node _T_3112 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 421:23]
+    node _T_3113 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 421:53]
+    node _T_3114 = and(_T_3112, _T_3113) @[lsu_bus_buffer.scala 421:41]
+    node _T_3115 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 421:82]
+    node _T_3116 = and(_T_3114, _T_3115) @[lsu_bus_buffer.scala 421:71]
+    node _T_3117 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 421:101]
+    node _T_3118 = and(_T_3116, _T_3117) @[lsu_bus_buffer.scala 421:90]
+    node _T_3119 = or(_T_3111, _T_3118) @[lsu_bus_buffer.scala 420:59]
+    node _T_3120 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 422:17]
+    node _T_3121 = and(_T_3120, io.ldst_dual_r) @[lsu_bus_buffer.scala 422:35]
+    node _T_3122 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 422:63]
+    node _T_3123 = and(_T_3121, _T_3122) @[lsu_bus_buffer.scala 422:52]
+    node _T_3124 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 422:82]
+    node _T_3125 = and(_T_3123, _T_3124) @[lsu_bus_buffer.scala 422:71]
+    node _T_3126 = or(_T_3119, _T_3125) @[lsu_bus_buffer.scala 421:110]
+    node _T_3127 = and(_T_3107, _T_3126) @[lsu_bus_buffer.scala 419:112]
+    node _T_3128 = cat(_T_3127, _T_3105) @[Cat.scala 29:58]
+    node _T_3129 = cat(_T_3128, _T_3083) @[Cat.scala 29:58]
+    node _T_3130 = cat(_T_3129, _T_3061) @[Cat.scala 29:58]
+    buf_rspage_set[0] <= _T_2857 @[lsu_bus_buffer.scala 419:18]
+    buf_rspage_set[1] <= _T_2948 @[lsu_bus_buffer.scala 419:18]
+    buf_rspage_set[2] <= _T_3039 @[lsu_bus_buffer.scala 419:18]
+    buf_rspage_set[3] <= _T_3130 @[lsu_bus_buffer.scala 419:18]
+    node _T_3131 = bits(buf_rspage_set[0], 0, 0) @[lsu_bus_buffer.scala 423:84]
+    node _T_3132 = bits(buf_rspage[0], 0, 0) @[lsu_bus_buffer.scala 423:103]
+    node _T_3133 = or(_T_3131, _T_3132) @[lsu_bus_buffer.scala 423:88]
+    node _T_3134 = bits(buf_rspage_set[0], 1, 1) @[lsu_bus_buffer.scala 423:84]
+    node _T_3135 = bits(buf_rspage[0], 1, 1) @[lsu_bus_buffer.scala 423:103]
+    node _T_3136 = or(_T_3134, _T_3135) @[lsu_bus_buffer.scala 423:88]
+    node _T_3137 = bits(buf_rspage_set[0], 2, 2) @[lsu_bus_buffer.scala 423:84]
+    node _T_3138 = bits(buf_rspage[0], 2, 2) @[lsu_bus_buffer.scala 423:103]
+    node _T_3139 = or(_T_3137, _T_3138) @[lsu_bus_buffer.scala 423:88]
+    node _T_3140 = bits(buf_rspage_set[0], 3, 3) @[lsu_bus_buffer.scala 423:84]
+    node _T_3141 = bits(buf_rspage[0], 3, 3) @[lsu_bus_buffer.scala 423:103]
+    node _T_3142 = or(_T_3140, _T_3141) @[lsu_bus_buffer.scala 423:88]
+    node _T_3143 = cat(_T_3142, _T_3139) @[Cat.scala 29:58]
+    node _T_3144 = cat(_T_3143, _T_3136) @[Cat.scala 29:58]
+    node _T_3145 = cat(_T_3144, _T_3133) @[Cat.scala 29:58]
+    node _T_3146 = bits(buf_rspage_set[1], 0, 0) @[lsu_bus_buffer.scala 423:84]
+    node _T_3147 = bits(buf_rspage[1], 0, 0) @[lsu_bus_buffer.scala 423:103]
+    node _T_3148 = or(_T_3146, _T_3147) @[lsu_bus_buffer.scala 423:88]
+    node _T_3149 = bits(buf_rspage_set[1], 1, 1) @[lsu_bus_buffer.scala 423:84]
+    node _T_3150 = bits(buf_rspage[1], 1, 1) @[lsu_bus_buffer.scala 423:103]
+    node _T_3151 = or(_T_3149, _T_3150) @[lsu_bus_buffer.scala 423:88]
+    node _T_3152 = bits(buf_rspage_set[1], 2, 2) @[lsu_bus_buffer.scala 423:84]
+    node _T_3153 = bits(buf_rspage[1], 2, 2) @[lsu_bus_buffer.scala 423:103]
+    node _T_3154 = or(_T_3152, _T_3153) @[lsu_bus_buffer.scala 423:88]
+    node _T_3155 = bits(buf_rspage_set[1], 3, 3) @[lsu_bus_buffer.scala 423:84]
+    node _T_3156 = bits(buf_rspage[1], 3, 3) @[lsu_bus_buffer.scala 423:103]
+    node _T_3157 = or(_T_3155, _T_3156) @[lsu_bus_buffer.scala 423:88]
+    node _T_3158 = cat(_T_3157, _T_3154) @[Cat.scala 29:58]
+    node _T_3159 = cat(_T_3158, _T_3151) @[Cat.scala 29:58]
+    node _T_3160 = cat(_T_3159, _T_3148) @[Cat.scala 29:58]
+    node _T_3161 = bits(buf_rspage_set[2], 0, 0) @[lsu_bus_buffer.scala 423:84]
+    node _T_3162 = bits(buf_rspage[2], 0, 0) @[lsu_bus_buffer.scala 423:103]
+    node _T_3163 = or(_T_3161, _T_3162) @[lsu_bus_buffer.scala 423:88]
+    node _T_3164 = bits(buf_rspage_set[2], 1, 1) @[lsu_bus_buffer.scala 423:84]
+    node _T_3165 = bits(buf_rspage[2], 1, 1) @[lsu_bus_buffer.scala 423:103]
+    node _T_3166 = or(_T_3164, _T_3165) @[lsu_bus_buffer.scala 423:88]
+    node _T_3167 = bits(buf_rspage_set[2], 2, 2) @[lsu_bus_buffer.scala 423:84]
+    node _T_3168 = bits(buf_rspage[2], 2, 2) @[lsu_bus_buffer.scala 423:103]
+    node _T_3169 = or(_T_3167, _T_3168) @[lsu_bus_buffer.scala 423:88]
+    node _T_3170 = bits(buf_rspage_set[2], 3, 3) @[lsu_bus_buffer.scala 423:84]
+    node _T_3171 = bits(buf_rspage[2], 3, 3) @[lsu_bus_buffer.scala 423:103]
+    node _T_3172 = or(_T_3170, _T_3171) @[lsu_bus_buffer.scala 423:88]
+    node _T_3173 = cat(_T_3172, _T_3169) @[Cat.scala 29:58]
+    node _T_3174 = cat(_T_3173, _T_3166) @[Cat.scala 29:58]
+    node _T_3175 = cat(_T_3174, _T_3163) @[Cat.scala 29:58]
+    node _T_3176 = bits(buf_rspage_set[3], 0, 0) @[lsu_bus_buffer.scala 423:84]
+    node _T_3177 = bits(buf_rspage[3], 0, 0) @[lsu_bus_buffer.scala 423:103]
+    node _T_3178 = or(_T_3176, _T_3177) @[lsu_bus_buffer.scala 423:88]
+    node _T_3179 = bits(buf_rspage_set[3], 1, 1) @[lsu_bus_buffer.scala 423:84]
+    node _T_3180 = bits(buf_rspage[3], 1, 1) @[lsu_bus_buffer.scala 423:103]
+    node _T_3181 = or(_T_3179, _T_3180) @[lsu_bus_buffer.scala 423:88]
+    node _T_3182 = bits(buf_rspage_set[3], 2, 2) @[lsu_bus_buffer.scala 423:84]
+    node _T_3183 = bits(buf_rspage[3], 2, 2) @[lsu_bus_buffer.scala 423:103]
+    node _T_3184 = or(_T_3182, _T_3183) @[lsu_bus_buffer.scala 423:88]
+    node _T_3185 = bits(buf_rspage_set[3], 3, 3) @[lsu_bus_buffer.scala 423:84]
+    node _T_3186 = bits(buf_rspage[3], 3, 3) @[lsu_bus_buffer.scala 423:103]
+    node _T_3187 = or(_T_3185, _T_3186) @[lsu_bus_buffer.scala 423:88]
+    node _T_3188 = cat(_T_3187, _T_3184) @[Cat.scala 29:58]
+    node _T_3189 = cat(_T_3188, _T_3181) @[Cat.scala 29:58]
+    node _T_3190 = cat(_T_3189, _T_3178) @[Cat.scala 29:58]
+    buf_rspage_in[0] <= _T_3145 @[lsu_bus_buffer.scala 423:17]
+    buf_rspage_in[1] <= _T_3160 @[lsu_bus_buffer.scala 423:17]
+    buf_rspage_in[2] <= _T_3175 @[lsu_bus_buffer.scala 423:17]
+    buf_rspage_in[3] <= _T_3190 @[lsu_bus_buffer.scala 423:17]
+    node _T_3191 = bits(buf_rspageQ[0], 0, 0) @[lsu_bus_buffer.scala 424:78]
+    node _T_3192 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 424:99]
+    node _T_3193 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 424:125]
+    node _T_3194 = or(_T_3192, _T_3193) @[lsu_bus_buffer.scala 424:110]
+    node _T_3195 = eq(_T_3194, UInt<1>("h00")) @[lsu_bus_buffer.scala 424:84]
+    node _T_3196 = and(_T_3191, _T_3195) @[lsu_bus_buffer.scala 424:82]
+    node _T_3197 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 424:138]
+    node _T_3198 = and(_T_3196, _T_3197) @[lsu_bus_buffer.scala 424:136]
+    node _T_3199 = bits(buf_rspageQ[0], 1, 1) @[lsu_bus_buffer.scala 424:78]
+    node _T_3200 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 424:99]
+    node _T_3201 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 424:125]
+    node _T_3202 = or(_T_3200, _T_3201) @[lsu_bus_buffer.scala 424:110]
+    node _T_3203 = eq(_T_3202, UInt<1>("h00")) @[lsu_bus_buffer.scala 424:84]
+    node _T_3204 = and(_T_3199, _T_3203) @[lsu_bus_buffer.scala 424:82]
+    node _T_3205 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 424:138]
+    node _T_3206 = and(_T_3204, _T_3205) @[lsu_bus_buffer.scala 424:136]
+    node _T_3207 = bits(buf_rspageQ[0], 2, 2) @[lsu_bus_buffer.scala 424:78]
+    node _T_3208 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 424:99]
+    node _T_3209 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 424:125]
+    node _T_3210 = or(_T_3208, _T_3209) @[lsu_bus_buffer.scala 424:110]
+    node _T_3211 = eq(_T_3210, UInt<1>("h00")) @[lsu_bus_buffer.scala 424:84]
+    node _T_3212 = and(_T_3207, _T_3211) @[lsu_bus_buffer.scala 424:82]
+    node _T_3213 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 424:138]
+    node _T_3214 = and(_T_3212, _T_3213) @[lsu_bus_buffer.scala 424:136]
+    node _T_3215 = bits(buf_rspageQ[0], 3, 3) @[lsu_bus_buffer.scala 424:78]
+    node _T_3216 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 424:99]
+    node _T_3217 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 424:125]
+    node _T_3218 = or(_T_3216, _T_3217) @[lsu_bus_buffer.scala 424:110]
+    node _T_3219 = eq(_T_3218, UInt<1>("h00")) @[lsu_bus_buffer.scala 424:84]
+    node _T_3220 = and(_T_3215, _T_3219) @[lsu_bus_buffer.scala 424:82]
+    node _T_3221 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 424:138]
+    node _T_3222 = and(_T_3220, _T_3221) @[lsu_bus_buffer.scala 424:136]
+    node _T_3223 = cat(_T_3222, _T_3214) @[Cat.scala 29:58]
+    node _T_3224 = cat(_T_3223, _T_3206) @[Cat.scala 29:58]
+    node _T_3225 = cat(_T_3224, _T_3198) @[Cat.scala 29:58]
+    node _T_3226 = bits(buf_rspageQ[1], 0, 0) @[lsu_bus_buffer.scala 424:78]
+    node _T_3227 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 424:99]
+    node _T_3228 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 424:125]
+    node _T_3229 = or(_T_3227, _T_3228) @[lsu_bus_buffer.scala 424:110]
+    node _T_3230 = eq(_T_3229, UInt<1>("h00")) @[lsu_bus_buffer.scala 424:84]
+    node _T_3231 = and(_T_3226, _T_3230) @[lsu_bus_buffer.scala 424:82]
+    node _T_3232 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 424:138]
+    node _T_3233 = and(_T_3231, _T_3232) @[lsu_bus_buffer.scala 424:136]
+    node _T_3234 = bits(buf_rspageQ[1], 1, 1) @[lsu_bus_buffer.scala 424:78]
+    node _T_3235 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 424:99]
+    node _T_3236 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 424:125]
+    node _T_3237 = or(_T_3235, _T_3236) @[lsu_bus_buffer.scala 424:110]
+    node _T_3238 = eq(_T_3237, UInt<1>("h00")) @[lsu_bus_buffer.scala 424:84]
+    node _T_3239 = and(_T_3234, _T_3238) @[lsu_bus_buffer.scala 424:82]
+    node _T_3240 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 424:138]
+    node _T_3241 = and(_T_3239, _T_3240) @[lsu_bus_buffer.scala 424:136]
+    node _T_3242 = bits(buf_rspageQ[1], 2, 2) @[lsu_bus_buffer.scala 424:78]
+    node _T_3243 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 424:99]
+    node _T_3244 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 424:125]
+    node _T_3245 = or(_T_3243, _T_3244) @[lsu_bus_buffer.scala 424:110]
+    node _T_3246 = eq(_T_3245, UInt<1>("h00")) @[lsu_bus_buffer.scala 424:84]
+    node _T_3247 = and(_T_3242, _T_3246) @[lsu_bus_buffer.scala 424:82]
+    node _T_3248 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 424:138]
+    node _T_3249 = and(_T_3247, _T_3248) @[lsu_bus_buffer.scala 424:136]
+    node _T_3250 = bits(buf_rspageQ[1], 3, 3) @[lsu_bus_buffer.scala 424:78]
+    node _T_3251 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 424:99]
+    node _T_3252 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 424:125]
+    node _T_3253 = or(_T_3251, _T_3252) @[lsu_bus_buffer.scala 424:110]
+    node _T_3254 = eq(_T_3253, UInt<1>("h00")) @[lsu_bus_buffer.scala 424:84]
+    node _T_3255 = and(_T_3250, _T_3254) @[lsu_bus_buffer.scala 424:82]
+    node _T_3256 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 424:138]
+    node _T_3257 = and(_T_3255, _T_3256) @[lsu_bus_buffer.scala 424:136]
+    node _T_3258 = cat(_T_3257, _T_3249) @[Cat.scala 29:58]
+    node _T_3259 = cat(_T_3258, _T_3241) @[Cat.scala 29:58]
+    node _T_3260 = cat(_T_3259, _T_3233) @[Cat.scala 29:58]
+    node _T_3261 = bits(buf_rspageQ[2], 0, 0) @[lsu_bus_buffer.scala 424:78]
+    node _T_3262 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 424:99]
+    node _T_3263 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 424:125]
+    node _T_3264 = or(_T_3262, _T_3263) @[lsu_bus_buffer.scala 424:110]
+    node _T_3265 = eq(_T_3264, UInt<1>("h00")) @[lsu_bus_buffer.scala 424:84]
+    node _T_3266 = and(_T_3261, _T_3265) @[lsu_bus_buffer.scala 424:82]
+    node _T_3267 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 424:138]
+    node _T_3268 = and(_T_3266, _T_3267) @[lsu_bus_buffer.scala 424:136]
+    node _T_3269 = bits(buf_rspageQ[2], 1, 1) @[lsu_bus_buffer.scala 424:78]
+    node _T_3270 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 424:99]
+    node _T_3271 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 424:125]
+    node _T_3272 = or(_T_3270, _T_3271) @[lsu_bus_buffer.scala 424:110]
+    node _T_3273 = eq(_T_3272, UInt<1>("h00")) @[lsu_bus_buffer.scala 424:84]
+    node _T_3274 = and(_T_3269, _T_3273) @[lsu_bus_buffer.scala 424:82]
+    node _T_3275 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 424:138]
+    node _T_3276 = and(_T_3274, _T_3275) @[lsu_bus_buffer.scala 424:136]
+    node _T_3277 = bits(buf_rspageQ[2], 2, 2) @[lsu_bus_buffer.scala 424:78]
+    node _T_3278 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 424:99]
+    node _T_3279 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 424:125]
+    node _T_3280 = or(_T_3278, _T_3279) @[lsu_bus_buffer.scala 424:110]
+    node _T_3281 = eq(_T_3280, UInt<1>("h00")) @[lsu_bus_buffer.scala 424:84]
+    node _T_3282 = and(_T_3277, _T_3281) @[lsu_bus_buffer.scala 424:82]
+    node _T_3283 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 424:138]
+    node _T_3284 = and(_T_3282, _T_3283) @[lsu_bus_buffer.scala 424:136]
+    node _T_3285 = bits(buf_rspageQ[2], 3, 3) @[lsu_bus_buffer.scala 424:78]
+    node _T_3286 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 424:99]
+    node _T_3287 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 424:125]
+    node _T_3288 = or(_T_3286, _T_3287) @[lsu_bus_buffer.scala 424:110]
+    node _T_3289 = eq(_T_3288, UInt<1>("h00")) @[lsu_bus_buffer.scala 424:84]
+    node _T_3290 = and(_T_3285, _T_3289) @[lsu_bus_buffer.scala 424:82]
+    node _T_3291 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 424:138]
+    node _T_3292 = and(_T_3290, _T_3291) @[lsu_bus_buffer.scala 424:136]
+    node _T_3293 = cat(_T_3292, _T_3284) @[Cat.scala 29:58]
+    node _T_3294 = cat(_T_3293, _T_3276) @[Cat.scala 29:58]
+    node _T_3295 = cat(_T_3294, _T_3268) @[Cat.scala 29:58]
+    node _T_3296 = bits(buf_rspageQ[3], 0, 0) @[lsu_bus_buffer.scala 424:78]
+    node _T_3297 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 424:99]
+    node _T_3298 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 424:125]
+    node _T_3299 = or(_T_3297, _T_3298) @[lsu_bus_buffer.scala 424:110]
+    node _T_3300 = eq(_T_3299, UInt<1>("h00")) @[lsu_bus_buffer.scala 424:84]
+    node _T_3301 = and(_T_3296, _T_3300) @[lsu_bus_buffer.scala 424:82]
+    node _T_3302 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 424:138]
+    node _T_3303 = and(_T_3301, _T_3302) @[lsu_bus_buffer.scala 424:136]
+    node _T_3304 = bits(buf_rspageQ[3], 1, 1) @[lsu_bus_buffer.scala 424:78]
+    node _T_3305 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 424:99]
+    node _T_3306 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 424:125]
+    node _T_3307 = or(_T_3305, _T_3306) @[lsu_bus_buffer.scala 424:110]
+    node _T_3308 = eq(_T_3307, UInt<1>("h00")) @[lsu_bus_buffer.scala 424:84]
+    node _T_3309 = and(_T_3304, _T_3308) @[lsu_bus_buffer.scala 424:82]
+    node _T_3310 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 424:138]
+    node _T_3311 = and(_T_3309, _T_3310) @[lsu_bus_buffer.scala 424:136]
+    node _T_3312 = bits(buf_rspageQ[3], 2, 2) @[lsu_bus_buffer.scala 424:78]
+    node _T_3313 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 424:99]
+    node _T_3314 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 424:125]
+    node _T_3315 = or(_T_3313, _T_3314) @[lsu_bus_buffer.scala 424:110]
+    node _T_3316 = eq(_T_3315, UInt<1>("h00")) @[lsu_bus_buffer.scala 424:84]
+    node _T_3317 = and(_T_3312, _T_3316) @[lsu_bus_buffer.scala 424:82]
+    node _T_3318 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 424:138]
+    node _T_3319 = and(_T_3317, _T_3318) @[lsu_bus_buffer.scala 424:136]
+    node _T_3320 = bits(buf_rspageQ[3], 3, 3) @[lsu_bus_buffer.scala 424:78]
+    node _T_3321 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 424:99]
+    node _T_3322 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 424:125]
+    node _T_3323 = or(_T_3321, _T_3322) @[lsu_bus_buffer.scala 424:110]
+    node _T_3324 = eq(_T_3323, UInt<1>("h00")) @[lsu_bus_buffer.scala 424:84]
+    node _T_3325 = and(_T_3320, _T_3324) @[lsu_bus_buffer.scala 424:82]
+    node _T_3326 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 424:138]
+    node _T_3327 = and(_T_3325, _T_3326) @[lsu_bus_buffer.scala 424:136]
+    node _T_3328 = cat(_T_3327, _T_3319) @[Cat.scala 29:58]
+    node _T_3329 = cat(_T_3328, _T_3311) @[Cat.scala 29:58]
+    node _T_3330 = cat(_T_3329, _T_3303) @[Cat.scala 29:58]
+    buf_rspage[0] <= _T_3225 @[lsu_bus_buffer.scala 424:14]
+    buf_rspage[1] <= _T_3260 @[lsu_bus_buffer.scala 424:14]
+    buf_rspage[2] <= _T_3295 @[lsu_bus_buffer.scala 424:14]
+    buf_rspage[3] <= _T_3330 @[lsu_bus_buffer.scala 424:14]
+    node _T_3331 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 425:75]
+    node _T_3332 = and(ibuf_drain_vld, _T_3331) @[lsu_bus_buffer.scala 425:63]
+    node _T_3333 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 425:75]
+    node _T_3334 = and(ibuf_drain_vld, _T_3333) @[lsu_bus_buffer.scala 425:63]
+    node _T_3335 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 425:75]
+    node _T_3336 = and(ibuf_drain_vld, _T_3335) @[lsu_bus_buffer.scala 425:63]
+    node _T_3337 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 425:75]
+    node _T_3338 = and(ibuf_drain_vld, _T_3337) @[lsu_bus_buffer.scala 425:63]
+    node _T_3339 = cat(_T_3338, _T_3336) @[Cat.scala 29:58]
+    node _T_3340 = cat(_T_3339, _T_3334) @[Cat.scala 29:58]
+    node _T_3341 = cat(_T_3340, _T_3332) @[Cat.scala 29:58]
+    ibuf_drainvec_vld <= _T_3341 @[lsu_bus_buffer.scala 425:21]
+    node _T_3342 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 426:64]
+    node _T_3343 = bits(ibuf_byteen_out, 3, 0) @[lsu_bus_buffer.scala 426:84]
+    node _T_3344 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 427:18]
+    node _T_3345 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 427:46]
+    node _T_3346 = and(_T_3344, _T_3345) @[lsu_bus_buffer.scala 427:35]
+    node _T_3347 = bits(ldst_byteen_hi_r, 3, 0) @[lsu_bus_buffer.scala 427:71]
+    node _T_3348 = bits(ldst_byteen_lo_r, 3, 0) @[lsu_bus_buffer.scala 427:94]
+    node _T_3349 = mux(_T_3346, _T_3347, _T_3348) @[lsu_bus_buffer.scala 427:8]
+    node _T_3350 = mux(_T_3342, _T_3343, _T_3349) @[lsu_bus_buffer.scala 426:46]
+    node _T_3351 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 426:64]
+    node _T_3352 = bits(ibuf_byteen_out, 3, 0) @[lsu_bus_buffer.scala 426:84]
+    node _T_3353 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 427:18]
+    node _T_3354 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 427:46]
+    node _T_3355 = and(_T_3353, _T_3354) @[lsu_bus_buffer.scala 427:35]
+    node _T_3356 = bits(ldst_byteen_hi_r, 3, 0) @[lsu_bus_buffer.scala 427:71]
+    node _T_3357 = bits(ldst_byteen_lo_r, 3, 0) @[lsu_bus_buffer.scala 427:94]
+    node _T_3358 = mux(_T_3355, _T_3356, _T_3357) @[lsu_bus_buffer.scala 427:8]
+    node _T_3359 = mux(_T_3351, _T_3352, _T_3358) @[lsu_bus_buffer.scala 426:46]
+    node _T_3360 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 426:64]
+    node _T_3361 = bits(ibuf_byteen_out, 3, 0) @[lsu_bus_buffer.scala 426:84]
+    node _T_3362 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 427:18]
+    node _T_3363 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 427:46]
+    node _T_3364 = and(_T_3362, _T_3363) @[lsu_bus_buffer.scala 427:35]
+    node _T_3365 = bits(ldst_byteen_hi_r, 3, 0) @[lsu_bus_buffer.scala 427:71]
+    node _T_3366 = bits(ldst_byteen_lo_r, 3, 0) @[lsu_bus_buffer.scala 427:94]
+    node _T_3367 = mux(_T_3364, _T_3365, _T_3366) @[lsu_bus_buffer.scala 427:8]
+    node _T_3368 = mux(_T_3360, _T_3361, _T_3367) @[lsu_bus_buffer.scala 426:46]
+    node _T_3369 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 426:64]
+    node _T_3370 = bits(ibuf_byteen_out, 3, 0) @[lsu_bus_buffer.scala 426:84]
+    node _T_3371 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 427:18]
+    node _T_3372 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 427:46]
+    node _T_3373 = and(_T_3371, _T_3372) @[lsu_bus_buffer.scala 427:35]
+    node _T_3374 = bits(ldst_byteen_hi_r, 3, 0) @[lsu_bus_buffer.scala 427:71]
+    node _T_3375 = bits(ldst_byteen_lo_r, 3, 0) @[lsu_bus_buffer.scala 427:94]
+    node _T_3376 = mux(_T_3373, _T_3374, _T_3375) @[lsu_bus_buffer.scala 427:8]
+    node _T_3377 = mux(_T_3369, _T_3370, _T_3376) @[lsu_bus_buffer.scala 426:46]
+    buf_byteen_in[0] <= _T_3350 @[lsu_bus_buffer.scala 426:17]
+    buf_byteen_in[1] <= _T_3359 @[lsu_bus_buffer.scala 426:17]
+    buf_byteen_in[2] <= _T_3368 @[lsu_bus_buffer.scala 426:17]
+    buf_byteen_in[3] <= _T_3377 @[lsu_bus_buffer.scala 426:17]
+    node _T_3378 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 428:62]
+    node _T_3379 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 428:91]
+    node _T_3380 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 428:119]
+    node _T_3381 = and(_T_3379, _T_3380) @[lsu_bus_buffer.scala 428:108]
+    node _T_3382 = mux(_T_3381, io.end_addr_r, io.lsu_addr_r) @[lsu_bus_buffer.scala 428:81]
+    node _T_3383 = mux(_T_3378, ibuf_addr, _T_3382) @[lsu_bus_buffer.scala 428:44]
+    node _T_3384 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 428:62]
+    node _T_3385 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 428:91]
+    node _T_3386 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 428:119]
+    node _T_3387 = and(_T_3385, _T_3386) @[lsu_bus_buffer.scala 428:108]
+    node _T_3388 = mux(_T_3387, io.end_addr_r, io.lsu_addr_r) @[lsu_bus_buffer.scala 428:81]
+    node _T_3389 = mux(_T_3384, ibuf_addr, _T_3388) @[lsu_bus_buffer.scala 428:44]
+    node _T_3390 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 428:62]
+    node _T_3391 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 428:91]
+    node _T_3392 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 428:119]
+    node _T_3393 = and(_T_3391, _T_3392) @[lsu_bus_buffer.scala 428:108]
+    node _T_3394 = mux(_T_3393, io.end_addr_r, io.lsu_addr_r) @[lsu_bus_buffer.scala 428:81]
+    node _T_3395 = mux(_T_3390, ibuf_addr, _T_3394) @[lsu_bus_buffer.scala 428:44]
+    node _T_3396 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 428:62]
+    node _T_3397 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 428:91]
+    node _T_3398 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 428:119]
+    node _T_3399 = and(_T_3397, _T_3398) @[lsu_bus_buffer.scala 428:108]
+    node _T_3400 = mux(_T_3399, io.end_addr_r, io.lsu_addr_r) @[lsu_bus_buffer.scala 428:81]
+    node _T_3401 = mux(_T_3396, ibuf_addr, _T_3400) @[lsu_bus_buffer.scala 428:44]
+    buf_addr_in[0] <= _T_3383 @[lsu_bus_buffer.scala 428:15]
+    buf_addr_in[1] <= _T_3389 @[lsu_bus_buffer.scala 428:15]
+    buf_addr_in[2] <= _T_3395 @[lsu_bus_buffer.scala 428:15]
+    buf_addr_in[3] <= _T_3401 @[lsu_bus_buffer.scala 428:15]
+    node _T_3402 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 429:63]
+    node _T_3403 = mux(_T_3402, ibuf_dual, io.ldst_dual_r) @[lsu_bus_buffer.scala 429:45]
+    node _T_3404 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 429:63]
+    node _T_3405 = mux(_T_3404, ibuf_dual, io.ldst_dual_r) @[lsu_bus_buffer.scala 429:45]
+    node _T_3406 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 429:63]
+    node _T_3407 = mux(_T_3406, ibuf_dual, io.ldst_dual_r) @[lsu_bus_buffer.scala 429:45]
+    node _T_3408 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 429:63]
+    node _T_3409 = mux(_T_3408, ibuf_dual, io.ldst_dual_r) @[lsu_bus_buffer.scala 429:45]
+    node _T_3410 = cat(_T_3409, _T_3407) @[Cat.scala 29:58]
+    node _T_3411 = cat(_T_3410, _T_3405) @[Cat.scala 29:58]
+    node _T_3412 = cat(_T_3411, _T_3403) @[Cat.scala 29:58]
+    buf_dual_in <= _T_3412 @[lsu_bus_buffer.scala 429:15]
+    node _T_3413 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 430:65]
+    node _T_3414 = mux(_T_3413, ibuf_samedw, ldst_samedw_r) @[lsu_bus_buffer.scala 430:47]
+    node _T_3415 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 430:65]
+    node _T_3416 = mux(_T_3415, ibuf_samedw, ldst_samedw_r) @[lsu_bus_buffer.scala 430:47]
+    node _T_3417 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 430:65]
+    node _T_3418 = mux(_T_3417, ibuf_samedw, ldst_samedw_r) @[lsu_bus_buffer.scala 430:47]
+    node _T_3419 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 430:65]
+    node _T_3420 = mux(_T_3419, ibuf_samedw, ldst_samedw_r) @[lsu_bus_buffer.scala 430:47]
+    node _T_3421 = cat(_T_3420, _T_3418) @[Cat.scala 29:58]
+    node _T_3422 = cat(_T_3421, _T_3416) @[Cat.scala 29:58]
+    node _T_3423 = cat(_T_3422, _T_3414) @[Cat.scala 29:58]
+    buf_samedw_in <= _T_3423 @[lsu_bus_buffer.scala 430:17]
+    node _T_3424 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 431:66]
+    node _T_3425 = or(ibuf_nomerge, ibuf_force_drain) @[lsu_bus_buffer.scala 431:84]
+    node _T_3426 = mux(_T_3424, _T_3425, io.no_dword_merge_r) @[lsu_bus_buffer.scala 431:48]
+    node _T_3427 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 431:66]
+    node _T_3428 = or(ibuf_nomerge, ibuf_force_drain) @[lsu_bus_buffer.scala 431:84]
+    node _T_3429 = mux(_T_3427, _T_3428, io.no_dword_merge_r) @[lsu_bus_buffer.scala 431:48]
+    node _T_3430 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 431:66]
+    node _T_3431 = or(ibuf_nomerge, ibuf_force_drain) @[lsu_bus_buffer.scala 431:84]
+    node _T_3432 = mux(_T_3430, _T_3431, io.no_dword_merge_r) @[lsu_bus_buffer.scala 431:48]
+    node _T_3433 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 431:66]
+    node _T_3434 = or(ibuf_nomerge, ibuf_force_drain) @[lsu_bus_buffer.scala 431:84]
+    node _T_3435 = mux(_T_3433, _T_3434, io.no_dword_merge_r) @[lsu_bus_buffer.scala 431:48]
+    node _T_3436 = cat(_T_3435, _T_3432) @[Cat.scala 29:58]
+    node _T_3437 = cat(_T_3436, _T_3429) @[Cat.scala 29:58]
+    node _T_3438 = cat(_T_3437, _T_3426) @[Cat.scala 29:58]
+    buf_nomerge_in <= _T_3438 @[lsu_bus_buffer.scala 431:18]
+    node _T_3439 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 432:65]
+    node _T_3440 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 432:90]
+    node _T_3441 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 432:118]
+    node _T_3442 = and(_T_3440, _T_3441) @[lsu_bus_buffer.scala 432:107]
+    node _T_3443 = mux(_T_3439, ibuf_dual, _T_3442) @[lsu_bus_buffer.scala 432:47]
+    node _T_3444 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 432:65]
+    node _T_3445 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 432:90]
+    node _T_3446 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 432:118]
+    node _T_3447 = and(_T_3445, _T_3446) @[lsu_bus_buffer.scala 432:107]
+    node _T_3448 = mux(_T_3444, ibuf_dual, _T_3447) @[lsu_bus_buffer.scala 432:47]
+    node _T_3449 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 432:65]
+    node _T_3450 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 432:90]
+    node _T_3451 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 432:118]
+    node _T_3452 = and(_T_3450, _T_3451) @[lsu_bus_buffer.scala 432:107]
+    node _T_3453 = mux(_T_3449, ibuf_dual, _T_3452) @[lsu_bus_buffer.scala 432:47]
+    node _T_3454 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 432:65]
+    node _T_3455 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 432:90]
+    node _T_3456 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 432:118]
+    node _T_3457 = and(_T_3455, _T_3456) @[lsu_bus_buffer.scala 432:107]
+    node _T_3458 = mux(_T_3454, ibuf_dual, _T_3457) @[lsu_bus_buffer.scala 432:47]
+    node _T_3459 = cat(_T_3458, _T_3453) @[Cat.scala 29:58]
+    node _T_3460 = cat(_T_3459, _T_3448) @[Cat.scala 29:58]
+    node _T_3461 = cat(_T_3460, _T_3443) @[Cat.scala 29:58]
+    buf_dualhi_in <= _T_3461 @[lsu_bus_buffer.scala 432:17]
+    node _T_3462 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 433:65]
+    node _T_3463 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 433:97]
+    node _T_3464 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 433:125]
+    node _T_3465 = and(_T_3463, _T_3464) @[lsu_bus_buffer.scala 433:114]
+    node _T_3466 = mux(_T_3465, WrPtr0_r, WrPtr1_r) @[lsu_bus_buffer.scala 433:87]
+    node _T_3467 = mux(_T_3462, ibuf_dualtag, _T_3466) @[lsu_bus_buffer.scala 433:47]
+    node _T_3468 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 433:65]
+    node _T_3469 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 433:97]
+    node _T_3470 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 433:125]
+    node _T_3471 = and(_T_3469, _T_3470) @[lsu_bus_buffer.scala 433:114]
+    node _T_3472 = mux(_T_3471, WrPtr0_r, WrPtr1_r) @[lsu_bus_buffer.scala 433:87]
+    node _T_3473 = mux(_T_3468, ibuf_dualtag, _T_3472) @[lsu_bus_buffer.scala 433:47]
+    node _T_3474 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 433:65]
+    node _T_3475 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 433:97]
+    node _T_3476 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 433:125]
+    node _T_3477 = and(_T_3475, _T_3476) @[lsu_bus_buffer.scala 433:114]
+    node _T_3478 = mux(_T_3477, WrPtr0_r, WrPtr1_r) @[lsu_bus_buffer.scala 433:87]
+    node _T_3479 = mux(_T_3474, ibuf_dualtag, _T_3478) @[lsu_bus_buffer.scala 433:47]
+    node _T_3480 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 433:65]
+    node _T_3481 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 433:97]
+    node _T_3482 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 433:125]
+    node _T_3483 = and(_T_3481, _T_3482) @[lsu_bus_buffer.scala 433:114]
+    node _T_3484 = mux(_T_3483, WrPtr0_r, WrPtr1_r) @[lsu_bus_buffer.scala 433:87]
+    node _T_3485 = mux(_T_3480, ibuf_dualtag, _T_3484) @[lsu_bus_buffer.scala 433:47]
+    buf_dualtag_in[0] <= _T_3467 @[lsu_bus_buffer.scala 433:18]
+    buf_dualtag_in[1] <= _T_3473 @[lsu_bus_buffer.scala 433:18]
+    buf_dualtag_in[2] <= _T_3479 @[lsu_bus_buffer.scala 433:18]
+    buf_dualtag_in[3] <= _T_3485 @[lsu_bus_buffer.scala 433:18]
+    node _T_3486 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 434:69]
+    node _T_3487 = mux(_T_3486, ibuf_sideeffect, io.is_sideeffects_r) @[lsu_bus_buffer.scala 434:51]
+    node _T_3488 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 434:69]
+    node _T_3489 = mux(_T_3488, ibuf_sideeffect, io.is_sideeffects_r) @[lsu_bus_buffer.scala 434:51]
+    node _T_3490 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 434:69]
+    node _T_3491 = mux(_T_3490, ibuf_sideeffect, io.is_sideeffects_r) @[lsu_bus_buffer.scala 434:51]
+    node _T_3492 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 434:69]
+    node _T_3493 = mux(_T_3492, ibuf_sideeffect, io.is_sideeffects_r) @[lsu_bus_buffer.scala 434:51]
+    node _T_3494 = cat(_T_3493, _T_3491) @[Cat.scala 29:58]
+    node _T_3495 = cat(_T_3494, _T_3489) @[Cat.scala 29:58]
+    node _T_3496 = cat(_T_3495, _T_3487) @[Cat.scala 29:58]
+    buf_sideeffect_in <= _T_3496 @[lsu_bus_buffer.scala 434:21]
+    node _T_3497 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 435:65]
+    node _T_3498 = mux(_T_3497, ibuf_unsign, io.lsu_pkt_r.bits.unsign) @[lsu_bus_buffer.scala 435:47]
+    node _T_3499 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 435:65]
+    node _T_3500 = mux(_T_3499, ibuf_unsign, io.lsu_pkt_r.bits.unsign) @[lsu_bus_buffer.scala 435:47]
+    node _T_3501 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 435:65]
+    node _T_3502 = mux(_T_3501, ibuf_unsign, io.lsu_pkt_r.bits.unsign) @[lsu_bus_buffer.scala 435:47]
+    node _T_3503 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 435:65]
+    node _T_3504 = mux(_T_3503, ibuf_unsign, io.lsu_pkt_r.bits.unsign) @[lsu_bus_buffer.scala 435:47]
+    node _T_3505 = cat(_T_3504, _T_3502) @[Cat.scala 29:58]
+    node _T_3506 = cat(_T_3505, _T_3500) @[Cat.scala 29:58]
+    node _T_3507 = cat(_T_3506, _T_3498) @[Cat.scala 29:58]
+    buf_unsign_in <= _T_3507 @[lsu_bus_buffer.scala 435:17]
+    node _T_3508 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 436:60]
+    node _T_3509 = cat(io.lsu_pkt_r.bits.word, io.lsu_pkt_r.bits.half) @[Cat.scala 29:58]
+    node _T_3510 = mux(_T_3508, ibuf_sz, _T_3509) @[lsu_bus_buffer.scala 436:42]
+    node _T_3511 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 436:60]
+    node _T_3512 = cat(io.lsu_pkt_r.bits.word, io.lsu_pkt_r.bits.half) @[Cat.scala 29:58]
+    node _T_3513 = mux(_T_3511, ibuf_sz, _T_3512) @[lsu_bus_buffer.scala 436:42]
+    node _T_3514 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 436:60]
+    node _T_3515 = cat(io.lsu_pkt_r.bits.word, io.lsu_pkt_r.bits.half) @[Cat.scala 29:58]
+    node _T_3516 = mux(_T_3514, ibuf_sz, _T_3515) @[lsu_bus_buffer.scala 436:42]
+    node _T_3517 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 436:60]
+    node _T_3518 = cat(io.lsu_pkt_r.bits.word, io.lsu_pkt_r.bits.half) @[Cat.scala 29:58]
+    node _T_3519 = mux(_T_3517, ibuf_sz, _T_3518) @[lsu_bus_buffer.scala 436:42]
+    buf_sz_in[0] <= _T_3510 @[lsu_bus_buffer.scala 436:13]
+    buf_sz_in[1] <= _T_3513 @[lsu_bus_buffer.scala 436:13]
+    buf_sz_in[2] <= _T_3516 @[lsu_bus_buffer.scala 436:13]
+    buf_sz_in[3] <= _T_3519 @[lsu_bus_buffer.scala 436:13]
+    node _T_3520 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 437:64]
+    node _T_3521 = mux(_T_3520, ibuf_write, io.lsu_pkt_r.bits.store) @[lsu_bus_buffer.scala 437:46]
+    node _T_3522 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 437:64]
+    node _T_3523 = mux(_T_3522, ibuf_write, io.lsu_pkt_r.bits.store) @[lsu_bus_buffer.scala 437:46]
+    node _T_3524 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 437:64]
+    node _T_3525 = mux(_T_3524, ibuf_write, io.lsu_pkt_r.bits.store) @[lsu_bus_buffer.scala 437:46]
+    node _T_3526 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 437:64]
+    node _T_3527 = mux(_T_3526, ibuf_write, io.lsu_pkt_r.bits.store) @[lsu_bus_buffer.scala 437:46]
+    node _T_3528 = cat(_T_3527, _T_3525) @[Cat.scala 29:58]
+    node _T_3529 = cat(_T_3528, _T_3523) @[Cat.scala 29:58]
+    node _T_3530 = cat(_T_3529, _T_3521) @[Cat.scala 29:58]
+    buf_write_in <= _T_3530 @[lsu_bus_buffer.scala 437:16]
+    node _T_3531 = eq(UInt<3>("h00"), buf_state[0]) @[Conditional.scala 37:30]
+    when _T_3531 : @[Conditional.scala 40:58]
+      node _T_3532 = bits(io.lsu_bus_clk_en, 0, 0) @[lsu_bus_buffer.scala 442:56]
+      node _T_3533 = mux(_T_3532, UInt<3>("h02"), UInt<3>("h01")) @[lsu_bus_buffer.scala 442:31]
+      buf_nxtstate[0] <= _T_3533 @[lsu_bus_buffer.scala 442:25]
+      node _T_3534 = and(io.lsu_busreq_r, io.lsu_commit_r) @[lsu_bus_buffer.scala 443:45]
+      node _T_3535 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 443:77]
+      node _T_3536 = eq(ibuf_merge_en, UInt<1>("h00")) @[lsu_bus_buffer.scala 443:97]
+      node _T_3537 = and(_T_3535, _T_3536) @[lsu_bus_buffer.scala 443:95]
+      node _T_3538 = eq(UInt<1>("h00"), WrPtr0_r) @[lsu_bus_buffer.scala 443:117]
+      node _T_3539 = and(_T_3537, _T_3538) @[lsu_bus_buffer.scala 443:112]
+      node _T_3540 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 443:144]
+      node _T_3541 = eq(UInt<1>("h00"), WrPtr1_r) @[lsu_bus_buffer.scala 443:166]
+      node _T_3542 = and(_T_3540, _T_3541) @[lsu_bus_buffer.scala 443:161]
+      node _T_3543 = or(_T_3539, _T_3542) @[lsu_bus_buffer.scala 443:132]
+      node _T_3544 = and(_T_3534, _T_3543) @[lsu_bus_buffer.scala 443:63]
+      node _T_3545 = eq(UInt<1>("h00"), ibuf_tag) @[lsu_bus_buffer.scala 443:206]
+      node _T_3546 = and(ibuf_drain_vld, _T_3545) @[lsu_bus_buffer.scala 443:201]
+      node _T_3547 = or(_T_3544, _T_3546) @[lsu_bus_buffer.scala 443:183]
+      buf_state_en[0] <= _T_3547 @[lsu_bus_buffer.scala 443:25]
+      buf_wr_en[0] <= buf_state_en[0] @[lsu_bus_buffer.scala 444:22]
+      buf_data_en[0] <= buf_state_en[0] @[lsu_bus_buffer.scala 445:24]
+      node _T_3548 = eq(UInt<1>("h00"), ibuf_tag) @[lsu_bus_buffer.scala 446:52]
+      node _T_3549 = and(ibuf_drain_vld, _T_3548) @[lsu_bus_buffer.scala 446:47]
+      node _T_3550 = bits(_T_3549, 0, 0) @[lsu_bus_buffer.scala 446:73]
+      node _T_3551 = bits(ibuf_data_out, 31, 0) @[lsu_bus_buffer.scala 446:90]
+      node _T_3552 = bits(store_data_lo_r, 31, 0) @[lsu_bus_buffer.scala 446:114]
+      node _T_3553 = mux(_T_3550, _T_3551, _T_3552) @[lsu_bus_buffer.scala 446:30]
+      buf_data_in[0] <= _T_3553 @[lsu_bus_buffer.scala 446:24]
+      buf_cmd_state_bus_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 447:34]
+      buf_rst[0] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 448:21]
       skip @[Conditional.scala 40:58]
     else : @[Conditional.scala 39:67]
-      node _T_3547 = eq(UInt<3>("h01"), buf_state[0]) @[Conditional.scala 37:30]
-      when _T_3547 : @[Conditional.scala 39:67]
-        node _T_3548 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 453:60]
-        node _T_3549 = mux(_T_3548, UInt<3>("h00"), UInt<3>("h02")) @[lsu_bus_buffer.scala 453:31]
-        buf_nxtstate[0] <= _T_3549 @[lsu_bus_buffer.scala 453:25]
-        node _T_3550 = or(io.lsu_bus_clk_en, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 454:46]
-        buf_state_en[0] <= _T_3550 @[lsu_bus_buffer.scala 454:25]
-        buf_cmd_state_bus_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 455:34]
+      node _T_3554 = eq(UInt<3>("h01"), buf_state[0]) @[Conditional.scala 37:30]
+      when _T_3554 : @[Conditional.scala 39:67]
+        node _T_3555 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 451:60]
+        node _T_3556 = mux(_T_3555, UInt<3>("h00"), UInt<3>("h02")) @[lsu_bus_buffer.scala 451:31]
+        buf_nxtstate[0] <= _T_3556 @[lsu_bus_buffer.scala 451:25]
+        node _T_3557 = or(io.lsu_bus_clk_en, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 452:46]
+        buf_state_en[0] <= _T_3557 @[lsu_bus_buffer.scala 452:25]
+        buf_cmd_state_bus_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 453:34]
+        buf_rst[0] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 454:20]
         skip @[Conditional.scala 39:67]
       else : @[Conditional.scala 39:67]
-        node _T_3551 = eq(UInt<3>("h02"), buf_state[0]) @[Conditional.scala 37:30]
-        when _T_3551 : @[Conditional.scala 39:67]
-          node _T_3552 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 458:60]
-          node _T_3553 = and(obuf_nosend, bus_rsp_read) @[lsu_bus_buffer.scala 458:89]
-          node _T_3554 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[lsu_bus_buffer.scala 458:124]
-          node _T_3555 = and(_T_3553, _T_3554) @[lsu_bus_buffer.scala 458:104]
-          node _T_3556 = mux(_T_3555, UInt<3>("h05"), UInt<3>("h03")) @[lsu_bus_buffer.scala 458:75]
-          node _T_3557 = mux(_T_3552, UInt<3>("h00"), _T_3556) @[lsu_bus_buffer.scala 458:31]
-          buf_nxtstate[0] <= _T_3557 @[lsu_bus_buffer.scala 458:25]
-          node _T_3558 = eq(obuf_tag0, UInt<3>("h00")) @[lsu_bus_buffer.scala 459:48]
-          node _T_3559 = eq(obuf_tag1, UInt<3>("h00")) @[lsu_bus_buffer.scala 459:104]
-          node _T_3560 = and(obuf_merge, _T_3559) @[lsu_bus_buffer.scala 459:91]
-          node _T_3561 = or(_T_3558, _T_3560) @[lsu_bus_buffer.scala 459:77]
-          node _T_3562 = and(_T_3561, obuf_valid) @[lsu_bus_buffer.scala 459:135]
-          node _T_3563 = and(_T_3562, obuf_wr_enQ) @[lsu_bus_buffer.scala 459:148]
-          buf_cmd_state_bus_en[0] <= _T_3563 @[lsu_bus_buffer.scala 459:33]
-          buf_state_bus_en[0] <= buf_cmd_state_bus_en[0] @[lsu_bus_buffer.scala 460:29]
-          node _T_3564 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 461:49]
-          node _T_3565 = or(_T_3564, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 461:70]
-          buf_state_en[0] <= _T_3565 @[lsu_bus_buffer.scala 461:25]
-          buf_ldfwd_in[0] <= UInt<1>("h01") @[lsu_bus_buffer.scala 462:25]
-          node _T_3566 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 463:56]
-          node _T_3567 = eq(_T_3566, UInt<1>("h00")) @[lsu_bus_buffer.scala 463:46]
-          node _T_3568 = and(buf_state_en[0], _T_3567) @[lsu_bus_buffer.scala 463:44]
-          node _T_3569 = and(_T_3568, obuf_nosend) @[lsu_bus_buffer.scala 463:60]
-          node _T_3570 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 463:76]
-          node _T_3571 = and(_T_3569, _T_3570) @[lsu_bus_buffer.scala 463:74]
-          buf_ldfwd_en[0] <= _T_3571 @[lsu_bus_buffer.scala 463:25]
-          node _T_3572 = bits(obuf_rdrsp_tag, 1, 0) @[lsu_bus_buffer.scala 464:46]
-          buf_ldfwdtag_in[0] <= _T_3572 @[lsu_bus_buffer.scala 464:28]
-          node _T_3573 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 465:47]
-          node _T_3574 = and(_T_3573, obuf_nosend) @[lsu_bus_buffer.scala 465:67]
-          node _T_3575 = and(_T_3574, bus_rsp_read) @[lsu_bus_buffer.scala 465:81]
-          buf_data_en[0] <= _T_3575 @[lsu_bus_buffer.scala 465:24]
-          node _T_3576 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 466:48]
-          node _T_3577 = and(_T_3576, obuf_nosend) @[lsu_bus_buffer.scala 466:68]
-          node _T_3578 = and(_T_3577, bus_rsp_read_error) @[lsu_bus_buffer.scala 466:82]
-          buf_error_en[0] <= _T_3578 @[lsu_bus_buffer.scala 466:25]
-          node _T_3579 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 467:61]
-          node _T_3580 = bits(buf_addr[0], 2, 2) @[lsu_bus_buffer.scala 467:85]
-          node _T_3581 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 467:103]
-          node _T_3582 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 467:126]
-          node _T_3583 = mux(_T_3580, _T_3581, _T_3582) @[lsu_bus_buffer.scala 467:73]
-          node _T_3584 = mux(buf_error_en[0], _T_3579, _T_3583) @[lsu_bus_buffer.scala 467:30]
-          buf_data_in[0] <= _T_3584 @[lsu_bus_buffer.scala 467:24]
+        node _T_3558 = eq(UInt<3>("h02"), buf_state[0]) @[Conditional.scala 37:30]
+        when _T_3558 : @[Conditional.scala 39:67]
+          node _T_3559 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 457:60]
+          node _T_3560 = and(obuf_nosend, bus_rsp_read) @[lsu_bus_buffer.scala 457:89]
+          node _T_3561 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[lsu_bus_buffer.scala 457:124]
+          node _T_3562 = and(_T_3560, _T_3561) @[lsu_bus_buffer.scala 457:104]
+          node _T_3563 = mux(_T_3562, UInt<3>("h05"), UInt<3>("h03")) @[lsu_bus_buffer.scala 457:75]
+          node _T_3564 = mux(_T_3559, UInt<3>("h00"), _T_3563) @[lsu_bus_buffer.scala 457:31]
+          buf_nxtstate[0] <= _T_3564 @[lsu_bus_buffer.scala 457:25]
+          node _T_3565 = eq(obuf_tag0, UInt<3>("h00")) @[lsu_bus_buffer.scala 458:48]
+          node _T_3566 = eq(obuf_tag1, UInt<3>("h00")) @[lsu_bus_buffer.scala 458:104]
+          node _T_3567 = and(obuf_merge, _T_3566) @[lsu_bus_buffer.scala 458:91]
+          node _T_3568 = or(_T_3565, _T_3567) @[lsu_bus_buffer.scala 458:77]
+          node _T_3569 = and(_T_3568, obuf_valid) @[lsu_bus_buffer.scala 458:135]
+          node _T_3570 = and(_T_3569, obuf_wr_enQ) @[lsu_bus_buffer.scala 458:148]
+          buf_cmd_state_bus_en[0] <= _T_3570 @[lsu_bus_buffer.scala 458:33]
+          buf_state_bus_en[0] <= buf_cmd_state_bus_en[0] @[lsu_bus_buffer.scala 459:29]
+          node _T_3571 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 460:49]
+          node _T_3572 = or(_T_3571, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 460:70]
+          buf_state_en[0] <= _T_3572 @[lsu_bus_buffer.scala 460:25]
+          buf_ldfwd_in[0] <= UInt<1>("h01") @[lsu_bus_buffer.scala 461:25]
+          node _T_3573 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 462:56]
+          node _T_3574 = eq(_T_3573, UInt<1>("h00")) @[lsu_bus_buffer.scala 462:46]
+          node _T_3575 = and(buf_state_en[0], _T_3574) @[lsu_bus_buffer.scala 462:44]
+          node _T_3576 = and(_T_3575, obuf_nosend) @[lsu_bus_buffer.scala 462:60]
+          node _T_3577 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 462:76]
+          node _T_3578 = and(_T_3576, _T_3577) @[lsu_bus_buffer.scala 462:74]
+          buf_ldfwd_en[0] <= _T_3578 @[lsu_bus_buffer.scala 462:25]
+          node _T_3579 = bits(obuf_rdrsp_tag, 1, 0) @[lsu_bus_buffer.scala 463:46]
+          buf_ldfwdtag_in[0] <= _T_3579 @[lsu_bus_buffer.scala 463:28]
+          node _T_3580 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 464:47]
+          node _T_3581 = and(_T_3580, obuf_nosend) @[lsu_bus_buffer.scala 464:67]
+          node _T_3582 = and(_T_3581, bus_rsp_read) @[lsu_bus_buffer.scala 464:81]
+          buf_data_en[0] <= _T_3582 @[lsu_bus_buffer.scala 464:24]
+          node _T_3583 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 465:48]
+          node _T_3584 = and(_T_3583, obuf_nosend) @[lsu_bus_buffer.scala 465:68]
+          node _T_3585 = and(_T_3584, bus_rsp_read_error) @[lsu_bus_buffer.scala 465:82]
+          buf_error_en[0] <= _T_3585 @[lsu_bus_buffer.scala 465:25]
+          node _T_3586 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 466:61]
+          node _T_3587 = bits(buf_addr[0], 2, 2) @[lsu_bus_buffer.scala 466:85]
+          node _T_3588 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 466:103]
+          node _T_3589 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 466:126]
+          node _T_3590 = mux(_T_3587, _T_3588, _T_3589) @[lsu_bus_buffer.scala 466:73]
+          node _T_3591 = mux(buf_error_en[0], _T_3586, _T_3590) @[lsu_bus_buffer.scala 466:30]
+          buf_data_in[0] <= _T_3591 @[lsu_bus_buffer.scala 466:24]
+          buf_rst[0] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 467:20]
           skip @[Conditional.scala 39:67]
         else : @[Conditional.scala 39:67]
-          node _T_3585 = eq(UInt<3>("h03"), buf_state[0]) @[Conditional.scala 37:30]
-          when _T_3585 : @[Conditional.scala 39:67]
-            node _T_3586 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 470:67]
-            node _T_3587 = and(_T_3586, bus_rsp_write_error) @[lsu_bus_buffer.scala 470:71]
-            node _T_3588 = or(io.dec_tlu_force_halt, _T_3587) @[lsu_bus_buffer.scala 470:55]
-            node _T_3589 = bits(_T_3588, 0, 0) @[lsu_bus_buffer.scala 470:101]
-            node _T_3590 = eq(buf_samedw[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 471:30]
-            node _T_3591 = and(buf_dual[0], _T_3590) @[lsu_bus_buffer.scala 471:28]
-            node _T_3592 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 471:57]
-            node _T_3593 = eq(_T_3592, UInt<1>("h00")) @[lsu_bus_buffer.scala 471:47]
-            node _T_3594 = and(_T_3591, _T_3593) @[lsu_bus_buffer.scala 471:45]
-            node _T_3595 = neq(buf_state[buf_dualtag[0]], UInt<3>("h04")) @[lsu_bus_buffer.scala 471:90]
-            node _T_3596 = and(_T_3594, _T_3595) @[lsu_bus_buffer.scala 471:61]
-            node _T_3597 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 472:27]
-            node _T_3598 = or(_T_3597, any_done_wait_state) @[lsu_bus_buffer.scala 472:31]
-            node _T_3599 = eq(buf_samedw[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 472:70]
-            node _T_3600 = and(buf_dual[0], _T_3599) @[lsu_bus_buffer.scala 472:68]
-            node _T_3601 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 472:97]
-            node _T_3602 = eq(_T_3601, UInt<1>("h00")) @[lsu_bus_buffer.scala 472:87]
-            node _T_3603 = and(_T_3600, _T_3602) @[lsu_bus_buffer.scala 472:85]
-            node _T_3604 = eq(buf_dualtag[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 60:118]
-            node _T_3605 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 60:129]
-            node _T_3606 = eq(buf_dualtag[0], UInt<1>("h01")) @[lsu_bus_buffer.scala 60:118]
-            node _T_3607 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 60:129]
-            node _T_3608 = eq(buf_dualtag[0], UInt<2>("h02")) @[lsu_bus_buffer.scala 60:118]
-            node _T_3609 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 60:129]
-            node _T_3610 = eq(buf_dualtag[0], UInt<2>("h03")) @[lsu_bus_buffer.scala 60:118]
-            node _T_3611 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 60:129]
-            node _T_3612 = mux(_T_3604, _T_3605, UInt<1>("h00")) @[Mux.scala 27:72]
-            node _T_3613 = mux(_T_3606, _T_3607, UInt<1>("h00")) @[Mux.scala 27:72]
-            node _T_3614 = mux(_T_3608, _T_3609, UInt<1>("h00")) @[Mux.scala 27:72]
-            node _T_3615 = mux(_T_3610, _T_3611, UInt<1>("h00")) @[Mux.scala 27:72]
-            node _T_3616 = or(_T_3612, _T_3613) @[Mux.scala 27:72]
-            node _T_3617 = or(_T_3616, _T_3614) @[Mux.scala 27:72]
-            node _T_3618 = or(_T_3617, _T_3615) @[Mux.scala 27:72]
-            wire _T_3619 : UInt<1> @[Mux.scala 27:72]
-            _T_3619 <= _T_3618 @[Mux.scala 27:72]
-            node _T_3620 = and(_T_3603, _T_3619) @[lsu_bus_buffer.scala 472:101]
-            node _T_3621 = eq(buf_state[buf_dualtag[0]], UInt<3>("h04")) @[lsu_bus_buffer.scala 472:167]
-            node _T_3622 = and(_T_3620, _T_3621) @[lsu_bus_buffer.scala 472:138]
-            node _T_3623 = and(_T_3622, any_done_wait_state) @[lsu_bus_buffer.scala 472:187]
-            node _T_3624 = or(_T_3598, _T_3623) @[lsu_bus_buffer.scala 472:53]
-            node _T_3625 = mux(_T_3624, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 472:16]
-            node _T_3626 = mux(_T_3596, UInt<3>("h04"), _T_3625) @[lsu_bus_buffer.scala 471:14]
-            node _T_3627 = mux(_T_3589, UInt<3>("h00"), _T_3626) @[lsu_bus_buffer.scala 470:31]
-            buf_nxtstate[0] <= _T_3627 @[lsu_bus_buffer.scala 470:25]
-            node _T_3628 = eq(bus_rsp_write_tag, UInt<3>("h00")) @[lsu_bus_buffer.scala 473:73]
-            node _T_3629 = and(bus_rsp_write, _T_3628) @[lsu_bus_buffer.scala 473:52]
-            node _T_3630 = eq(bus_rsp_read_tag, UInt<3>("h00")) @[lsu_bus_buffer.scala 474:46]
-            node _T_3631 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 475:23]
-            node _T_3632 = eq(bus_rsp_read_tag, buf_ldfwdtag[0]) @[lsu_bus_buffer.scala 475:47]
-            node _T_3633 = and(_T_3631, _T_3632) @[lsu_bus_buffer.scala 475:27]
-            node _T_3634 = or(_T_3630, _T_3633) @[lsu_bus_buffer.scala 474:77]
-            node _T_3635 = and(buf_dual[0], buf_dualhi[0]) @[lsu_bus_buffer.scala 476:26]
-            node _T_3636 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 476:54]
-            node _T_3637 = not(_T_3636) @[lsu_bus_buffer.scala 476:44]
-            node _T_3638 = and(_T_3635, _T_3637) @[lsu_bus_buffer.scala 476:42]
-            node _T_3639 = and(_T_3638, buf_samedw[0]) @[lsu_bus_buffer.scala 476:58]
-            node _T_3640 = eq(bus_rsp_read_tag, buf_dualtag[0]) @[lsu_bus_buffer.scala 476:94]
-            node _T_3641 = and(_T_3639, _T_3640) @[lsu_bus_buffer.scala 476:74]
-            node _T_3642 = or(_T_3634, _T_3641) @[lsu_bus_buffer.scala 475:71]
-            node _T_3643 = and(bus_rsp_read, _T_3642) @[lsu_bus_buffer.scala 474:25]
-            node _T_3644 = or(_T_3629, _T_3643) @[lsu_bus_buffer.scala 473:105]
-            buf_resp_state_bus_en[0] <= _T_3644 @[lsu_bus_buffer.scala 473:34]
+          node _T_3592 = eq(UInt<3>("h03"), buf_state[0]) @[Conditional.scala 37:30]
+          when _T_3592 : @[Conditional.scala 39:67]
+            node _T_3593 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 470:69]
+            node _T_3594 = eq(bus_rsp_write_error, UInt<1>("h00")) @[lsu_bus_buffer.scala 470:75]
+            node _T_3595 = and(_T_3593, _T_3594) @[lsu_bus_buffer.scala 470:73]
+            node _T_3596 = or(io.dec_tlu_force_halt, _T_3595) @[lsu_bus_buffer.scala 470:57]
+            node _T_3597 = bits(_T_3596, 0, 0) @[lsu_bus_buffer.scala 470:104]
+            node _T_3598 = eq(buf_samedw[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 471:30]
+            node _T_3599 = and(buf_dual[0], _T_3598) @[lsu_bus_buffer.scala 471:28]
+            node _T_3600 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 471:57]
+            node _T_3601 = eq(_T_3600, UInt<1>("h00")) @[lsu_bus_buffer.scala 471:47]
+            node _T_3602 = and(_T_3599, _T_3601) @[lsu_bus_buffer.scala 471:45]
+            node _T_3603 = neq(buf_state[buf_dualtag[0]], UInt<3>("h04")) @[lsu_bus_buffer.scala 471:90]
+            node _T_3604 = and(_T_3602, _T_3603) @[lsu_bus_buffer.scala 471:61]
+            node _T_3605 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 472:27]
+            node _T_3606 = or(_T_3605, any_done_wait_state) @[lsu_bus_buffer.scala 472:31]
+            node _T_3607 = eq(buf_samedw[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 472:70]
+            node _T_3608 = and(buf_dual[0], _T_3607) @[lsu_bus_buffer.scala 472:68]
+            node _T_3609 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 472:97]
+            node _T_3610 = eq(_T_3609, UInt<1>("h00")) @[lsu_bus_buffer.scala 472:87]
+            node _T_3611 = and(_T_3608, _T_3610) @[lsu_bus_buffer.scala 472:85]
+            node _T_3612 = eq(buf_dualtag[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 60:118]
+            node _T_3613 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 60:129]
+            node _T_3614 = eq(buf_dualtag[0], UInt<1>("h01")) @[lsu_bus_buffer.scala 60:118]
+            node _T_3615 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 60:129]
+            node _T_3616 = eq(buf_dualtag[0], UInt<2>("h02")) @[lsu_bus_buffer.scala 60:118]
+            node _T_3617 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 60:129]
+            node _T_3618 = eq(buf_dualtag[0], UInt<2>("h03")) @[lsu_bus_buffer.scala 60:118]
+            node _T_3619 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 60:129]
+            node _T_3620 = mux(_T_3612, _T_3613, UInt<1>("h00")) @[Mux.scala 27:72]
+            node _T_3621 = mux(_T_3614, _T_3615, UInt<1>("h00")) @[Mux.scala 27:72]
+            node _T_3622 = mux(_T_3616, _T_3617, UInt<1>("h00")) @[Mux.scala 27:72]
+            node _T_3623 = mux(_T_3618, _T_3619, UInt<1>("h00")) @[Mux.scala 27:72]
+            node _T_3624 = or(_T_3620, _T_3621) @[Mux.scala 27:72]
+            node _T_3625 = or(_T_3624, _T_3622) @[Mux.scala 27:72]
+            node _T_3626 = or(_T_3625, _T_3623) @[Mux.scala 27:72]
+            wire _T_3627 : UInt<1> @[Mux.scala 27:72]
+            _T_3627 <= _T_3626 @[Mux.scala 27:72]
+            node _T_3628 = and(_T_3611, _T_3627) @[lsu_bus_buffer.scala 472:101]
+            node _T_3629 = eq(buf_state[buf_dualtag[0]], UInt<3>("h04")) @[lsu_bus_buffer.scala 472:167]
+            node _T_3630 = and(_T_3628, _T_3629) @[lsu_bus_buffer.scala 472:138]
+            node _T_3631 = and(_T_3630, any_done_wait_state) @[lsu_bus_buffer.scala 472:187]
+            node _T_3632 = or(_T_3606, _T_3631) @[lsu_bus_buffer.scala 472:53]
+            node _T_3633 = mux(_T_3632, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 472:16]
+            node _T_3634 = mux(_T_3604, UInt<3>("h04"), _T_3633) @[lsu_bus_buffer.scala 471:14]
+            node _T_3635 = mux(_T_3597, UInt<3>("h00"), _T_3634) @[lsu_bus_buffer.scala 470:33]
+            buf_nxtstate[0] <= _T_3635 @[lsu_bus_buffer.scala 470:27]
+            node _T_3636 = eq(bus_rsp_write_tag, UInt<3>("h00")) @[lsu_bus_buffer.scala 473:73]
+            node _T_3637 = and(bus_rsp_write, _T_3636) @[lsu_bus_buffer.scala 473:52]
+            node _T_3638 = eq(bus_rsp_read_tag, UInt<3>("h00")) @[lsu_bus_buffer.scala 474:46]
+            node _T_3639 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 475:23]
+            node _T_3640 = eq(bus_rsp_read_tag, buf_ldfwdtag[0]) @[lsu_bus_buffer.scala 475:47]
+            node _T_3641 = and(_T_3639, _T_3640) @[lsu_bus_buffer.scala 475:27]
+            node _T_3642 = or(_T_3638, _T_3641) @[lsu_bus_buffer.scala 474:77]
+            node _T_3643 = and(buf_dual[0], buf_dualhi[0]) @[lsu_bus_buffer.scala 476:26]
+            node _T_3644 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 476:54]
+            node _T_3645 = not(_T_3644) @[lsu_bus_buffer.scala 476:44]
+            node _T_3646 = and(_T_3643, _T_3645) @[lsu_bus_buffer.scala 476:42]
+            node _T_3647 = and(_T_3646, buf_samedw[0]) @[lsu_bus_buffer.scala 476:58]
+            node _T_3648 = eq(bus_rsp_read_tag, buf_dualtag[0]) @[lsu_bus_buffer.scala 476:94]
+            node _T_3649 = and(_T_3647, _T_3648) @[lsu_bus_buffer.scala 476:74]
+            node _T_3650 = or(_T_3642, _T_3649) @[lsu_bus_buffer.scala 475:71]
+            node _T_3651 = and(bus_rsp_read, _T_3650) @[lsu_bus_buffer.scala 474:25]
+            node _T_3652 = or(_T_3637, _T_3651) @[lsu_bus_buffer.scala 473:105]
+            buf_resp_state_bus_en[0] <= _T_3652 @[lsu_bus_buffer.scala 473:34]
             buf_state_bus_en[0] <= buf_resp_state_bus_en[0] @[lsu_bus_buffer.scala 477:29]
-            node _T_3645 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 478:49]
-            node _T_3646 = or(_T_3645, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 478:70]
-            buf_state_en[0] <= _T_3646 @[lsu_bus_buffer.scala 478:25]
-            node _T_3647 = and(buf_state_bus_en[0], bus_rsp_read) @[lsu_bus_buffer.scala 479:47]
-            node _T_3648 = and(_T_3647, io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 479:62]
-            buf_data_en[0] <= _T_3648 @[lsu_bus_buffer.scala 479:24]
-            node _T_3649 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 480:48]
-            node _T_3650 = eq(bus_rsp_read_tag, UInt<3>("h00")) @[lsu_bus_buffer.scala 480:111]
-            node _T_3651 = and(bus_rsp_read_error, _T_3650) @[lsu_bus_buffer.scala 480:91]
-            node _T_3652 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 481:42]
-            node _T_3653 = and(bus_rsp_read_error, _T_3652) @[lsu_bus_buffer.scala 481:31]
-            node _T_3654 = eq(bus_rsp_read_tag, buf_ldfwdtag[0]) @[lsu_bus_buffer.scala 481:66]
-            node _T_3655 = and(_T_3653, _T_3654) @[lsu_bus_buffer.scala 481:46]
-            node _T_3656 = or(_T_3651, _T_3655) @[lsu_bus_buffer.scala 480:143]
-            node _T_3657 = eq(bus_rsp_write_tag, UInt<3>("h00")) @[lsu_bus_buffer.scala 482:54]
-            node _T_3658 = and(bus_rsp_write_error, _T_3657) @[lsu_bus_buffer.scala 482:33]
-            node _T_3659 = or(_T_3656, _T_3658) @[lsu_bus_buffer.scala 481:88]
-            node _T_3660 = and(_T_3649, _T_3659) @[lsu_bus_buffer.scala 480:68]
-            buf_error_en[0] <= _T_3660 @[lsu_bus_buffer.scala 480:25]
-            node _T_3661 = eq(buf_error_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 483:50]
-            node _T_3662 = and(buf_state_en[0], _T_3661) @[lsu_bus_buffer.scala 483:48]
-            node _T_3663 = bits(buf_addr[0], 2, 2) @[lsu_bus_buffer.scala 483:84]
-            node _T_3664 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 483:102]
-            node _T_3665 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 483:125]
-            node _T_3666 = mux(_T_3663, _T_3664, _T_3665) @[lsu_bus_buffer.scala 483:72]
-            node _T_3667 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 483:148]
-            node _T_3668 = mux(_T_3662, _T_3666, _T_3667) @[lsu_bus_buffer.scala 483:30]
-            buf_data_in[0] <= _T_3668 @[lsu_bus_buffer.scala 483:24]
+            node _T_3653 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 478:49]
+            node _T_3654 = or(_T_3653, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 478:70]
+            buf_state_en[0] <= _T_3654 @[lsu_bus_buffer.scala 478:25]
+            node _T_3655 = and(buf_state_bus_en[0], bus_rsp_read) @[lsu_bus_buffer.scala 479:47]
+            node _T_3656 = and(_T_3655, io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 479:62]
+            buf_data_en[0] <= _T_3656 @[lsu_bus_buffer.scala 479:24]
+            node _T_3657 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 480:48]
+            node _T_3658 = eq(bus_rsp_read_tag, UInt<3>("h00")) @[lsu_bus_buffer.scala 480:111]
+            node _T_3659 = and(bus_rsp_read_error, _T_3658) @[lsu_bus_buffer.scala 480:91]
+            node _T_3660 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 481:42]
+            node _T_3661 = and(bus_rsp_read_error, _T_3660) @[lsu_bus_buffer.scala 481:31]
+            node _T_3662 = eq(bus_rsp_read_tag, buf_ldfwdtag[0]) @[lsu_bus_buffer.scala 481:66]
+            node _T_3663 = and(_T_3661, _T_3662) @[lsu_bus_buffer.scala 481:46]
+            node _T_3664 = or(_T_3659, _T_3663) @[lsu_bus_buffer.scala 480:143]
+            node _T_3665 = eq(bus_rsp_write_tag, UInt<3>("h00")) @[lsu_bus_buffer.scala 482:54]
+            node _T_3666 = and(bus_rsp_write_error, _T_3665) @[lsu_bus_buffer.scala 482:33]
+            node _T_3667 = or(_T_3664, _T_3666) @[lsu_bus_buffer.scala 481:88]
+            node _T_3668 = and(_T_3657, _T_3667) @[lsu_bus_buffer.scala 480:68]
+            buf_error_en[0] <= _T_3668 @[lsu_bus_buffer.scala 480:25]
+            node _T_3669 = eq(buf_error_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 483:50]
+            node _T_3670 = and(buf_state_en[0], _T_3669) @[lsu_bus_buffer.scala 483:48]
+            node _T_3671 = bits(buf_addr[0], 2, 2) @[lsu_bus_buffer.scala 483:84]
+            node _T_3672 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 483:102]
+            node _T_3673 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 483:125]
+            node _T_3674 = mux(_T_3671, _T_3672, _T_3673) @[lsu_bus_buffer.scala 483:72]
+            node _T_3675 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 483:148]
+            node _T_3676 = mux(_T_3670, _T_3674, _T_3675) @[lsu_bus_buffer.scala 483:30]
+            buf_data_in[0] <= _T_3676 @[lsu_bus_buffer.scala 483:24]
             buf_cmd_state_bus_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 484:34]
+            buf_rst[0] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 485:20]
             skip @[Conditional.scala 39:67]
           else : @[Conditional.scala 39:67]
-            node _T_3669 = eq(UInt<3>("h04"), buf_state[0]) @[Conditional.scala 37:30]
-            when _T_3669 : @[Conditional.scala 39:67]
-              node _T_3670 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 487:60]
-              node _T_3671 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 487:86]
-              node _T_3672 = dshr(buf_ldfwd, buf_dualtag[0]) @[lsu_bus_buffer.scala 487:101]
-              node _T_3673 = bits(_T_3672, 0, 0) @[lsu_bus_buffer.scala 487:101]
-              node _T_3674 = or(_T_3671, _T_3673) @[lsu_bus_buffer.scala 487:90]
-              node _T_3675 = or(_T_3674, any_done_wait_state) @[lsu_bus_buffer.scala 487:118]
-              node _T_3676 = mux(_T_3675, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 487:75]
-              node _T_3677 = mux(_T_3670, UInt<3>("h00"), _T_3676) @[lsu_bus_buffer.scala 487:31]
-              buf_nxtstate[0] <= _T_3677 @[lsu_bus_buffer.scala 487:25]
-              node _T_3678 = eq(bus_rsp_read_tag, buf_dualtag[0]) @[lsu_bus_buffer.scala 488:66]
-              node _T_3679 = dshr(buf_ldfwd, buf_dualtag[0]) @[lsu_bus_buffer.scala 489:21]
-              node _T_3680 = bits(_T_3679, 0, 0) @[lsu_bus_buffer.scala 489:21]
-              node _T_3681 = eq(bus_rsp_read_tag, buf_ldfwdtag[buf_dualtag[0]]) @[lsu_bus_buffer.scala 489:58]
-              node _T_3682 = and(_T_3680, _T_3681) @[lsu_bus_buffer.scala 489:38]
-              node _T_3683 = or(_T_3678, _T_3682) @[lsu_bus_buffer.scala 488:95]
-              node _T_3684 = and(bus_rsp_read, _T_3683) @[lsu_bus_buffer.scala 488:45]
-              buf_state_bus_en[0] <= _T_3684 @[lsu_bus_buffer.scala 488:29]
-              node _T_3685 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 490:49]
-              node _T_3686 = or(_T_3685, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 490:70]
-              buf_state_en[0] <= _T_3686 @[lsu_bus_buffer.scala 490:25]
-              buf_cmd_state_bus_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 491:34]
+            node _T_3677 = eq(UInt<3>("h04"), buf_state[0]) @[Conditional.scala 37:30]
+            when _T_3677 : @[Conditional.scala 39:67]
+              node _T_3678 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 488:60]
+              node _T_3679 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 488:86]
+              node _T_3680 = dshr(buf_ldfwd, buf_dualtag[0]) @[lsu_bus_buffer.scala 488:101]
+              node _T_3681 = bits(_T_3680, 0, 0) @[lsu_bus_buffer.scala 488:101]
+              node _T_3682 = or(_T_3679, _T_3681) @[lsu_bus_buffer.scala 488:90]
+              node _T_3683 = or(_T_3682, any_done_wait_state) @[lsu_bus_buffer.scala 488:118]
+              node _T_3684 = mux(_T_3683, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 488:75]
+              node _T_3685 = mux(_T_3678, UInt<3>("h00"), _T_3684) @[lsu_bus_buffer.scala 488:31]
+              buf_nxtstate[0] <= _T_3685 @[lsu_bus_buffer.scala 488:25]
+              node _T_3686 = eq(bus_rsp_read_tag, buf_dualtag[0]) @[lsu_bus_buffer.scala 489:66]
+              node _T_3687 = dshr(buf_ldfwd, buf_dualtag[0]) @[lsu_bus_buffer.scala 490:21]
+              node _T_3688 = bits(_T_3687, 0, 0) @[lsu_bus_buffer.scala 490:21]
+              node _T_3689 = eq(bus_rsp_read_tag, buf_ldfwdtag[buf_dualtag[0]]) @[lsu_bus_buffer.scala 490:58]
+              node _T_3690 = and(_T_3688, _T_3689) @[lsu_bus_buffer.scala 490:38]
+              node _T_3691 = or(_T_3686, _T_3690) @[lsu_bus_buffer.scala 489:95]
+              node _T_3692 = and(bus_rsp_read, _T_3691) @[lsu_bus_buffer.scala 489:45]
+              buf_state_bus_en[0] <= _T_3692 @[lsu_bus_buffer.scala 489:29]
+              node _T_3693 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 491:49]
+              node _T_3694 = or(_T_3693, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 491:70]
+              buf_state_en[0] <= _T_3694 @[lsu_bus_buffer.scala 491:25]
+              buf_cmd_state_bus_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 492:34]
+              buf_rst[0] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 493:20]
               skip @[Conditional.scala 39:67]
             else : @[Conditional.scala 39:67]
-              node _T_3687 = eq(UInt<3>("h05"), buf_state[0]) @[Conditional.scala 37:30]
-              when _T_3687 : @[Conditional.scala 39:67]
-                node _T_3688 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 494:60]
-                node _T_3689 = mux(_T_3688, UInt<3>("h00"), UInt<3>("h06")) @[lsu_bus_buffer.scala 494:31]
-                buf_nxtstate[0] <= _T_3689 @[lsu_bus_buffer.scala 494:25]
-                node _T_3690 = eq(RspPtr, UInt<2>("h00")) @[lsu_bus_buffer.scala 495:37]
-                node _T_3691 = eq(buf_dualtag[0], RspPtr) @[lsu_bus_buffer.scala 495:98]
-                node _T_3692 = and(buf_dual[0], _T_3691) @[lsu_bus_buffer.scala 495:80]
-                node _T_3693 = or(_T_3690, _T_3692) @[lsu_bus_buffer.scala 495:65]
-                node _T_3694 = or(_T_3693, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 495:112]
-                buf_state_en[0] <= _T_3694 @[lsu_bus_buffer.scala 495:25]
-                buf_cmd_state_bus_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 496:34]
+              node _T_3695 = eq(UInt<3>("h05"), buf_state[0]) @[Conditional.scala 37:30]
+              when _T_3695 : @[Conditional.scala 39:67]
+                node _T_3696 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 496:60]
+                node _T_3697 = mux(_T_3696, UInt<3>("h00"), UInt<3>("h06")) @[lsu_bus_buffer.scala 496:31]
+                buf_nxtstate[0] <= _T_3697 @[lsu_bus_buffer.scala 496:25]
+                node _T_3698 = eq(RspPtr, UInt<2>("h00")) @[lsu_bus_buffer.scala 497:37]
+                node _T_3699 = eq(buf_dualtag[0], RspPtr) @[lsu_bus_buffer.scala 497:98]
+                node _T_3700 = and(buf_dual[0], _T_3699) @[lsu_bus_buffer.scala 497:80]
+                node _T_3701 = or(_T_3698, _T_3700) @[lsu_bus_buffer.scala 497:65]
+                node _T_3702 = or(_T_3701, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 497:112]
+                buf_state_en[0] <= _T_3702 @[lsu_bus_buffer.scala 497:25]
+                buf_cmd_state_bus_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 498:34]
+                buf_rst[0] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 499:20]
                 skip @[Conditional.scala 39:67]
               else : @[Conditional.scala 39:67]
-                node _T_3695 = eq(UInt<3>("h06"), buf_state[0]) @[Conditional.scala 37:30]
-                when _T_3695 : @[Conditional.scala 39:67]
-                  buf_nxtstate[0] <= UInt<3>("h00") @[lsu_bus_buffer.scala 499:25]
-                  buf_rst[0] <= UInt<1>("h01") @[lsu_bus_buffer.scala 500:20]
-                  buf_state_en[0] <= UInt<1>("h01") @[lsu_bus_buffer.scala 501:25]
-                  buf_ldfwd_in[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 502:25]
-                  buf_ldfwd_en[0] <= buf_state_en[0] @[lsu_bus_buffer.scala 503:25]
-                  buf_cmd_state_bus_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 504:34]
+                node _T_3703 = eq(UInt<3>("h06"), buf_state[0]) @[Conditional.scala 37:30]
+                when _T_3703 : @[Conditional.scala 39:67]
+                  buf_nxtstate[0] <= UInt<3>("h00") @[lsu_bus_buffer.scala 502:25]
+                  buf_rst[0] <= UInt<1>("h01") @[lsu_bus_buffer.scala 503:20]
+                  buf_state_en[0] <= UInt<1>("h01") @[lsu_bus_buffer.scala 504:25]
+                  buf_ldfwd_in[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 505:25]
+                  buf_ldfwd_en[0] <= buf_state_en[0] @[lsu_bus_buffer.scala 506:25]
+                  buf_cmd_state_bus_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 507:34]
                   skip @[Conditional.scala 39:67]
-    node _T_3696 = bits(buf_state_en[0], 0, 0) @[lsu_bus_buffer.scala 507:108]
-    reg _T_3697 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when _T_3696 : @[Reg.scala 28:19]
-      _T_3697 <= buf_nxtstate[0] @[Reg.scala 28:23]
+    node _T_3704 = bits(buf_state_en[0], 0, 0) @[lsu_bus_buffer.scala 510:108]
+    reg _T_3705 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_3704 : @[Reg.scala 28:19]
+      _T_3705 <= buf_nxtstate[0] @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    buf_state[0] <= _T_3697 @[lsu_bus_buffer.scala 507:18]
-    reg _T_3698 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 508:60]
-    _T_3698 <= buf_age_in_0 @[lsu_bus_buffer.scala 508:60]
-    buf_ageQ[0] <= _T_3698 @[lsu_bus_buffer.scala 508:17]
-    reg _T_3699 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 509:63]
-    _T_3699 <= buf_rspage_in[0] @[lsu_bus_buffer.scala 509:63]
-    buf_rspageQ[0] <= _T_3699 @[lsu_bus_buffer.scala 509:20]
-    node _T_3700 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 510:109]
-    reg _T_3701 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when _T_3700 : @[Reg.scala 28:19]
-      _T_3701 <= buf_dualtag_in[0] @[Reg.scala 28:23]
+    buf_state[0] <= _T_3705 @[lsu_bus_buffer.scala 510:18]
+    reg _T_3706 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 511:60]
+    _T_3706 <= buf_age_in_0 @[lsu_bus_buffer.scala 511:60]
+    buf_ageQ[0] <= _T_3706 @[lsu_bus_buffer.scala 511:17]
+    reg _T_3707 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 512:63]
+    _T_3707 <= buf_rspage_in[0] @[lsu_bus_buffer.scala 512:63]
+    buf_rspageQ[0] <= _T_3707 @[lsu_bus_buffer.scala 512:20]
+    node _T_3708 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 513:109]
+    reg _T_3709 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_3708 : @[Reg.scala 28:19]
+      _T_3709 <= buf_dualtag_in[0] @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    buf_dualtag[0] <= _T_3701 @[lsu_bus_buffer.scala 510:20]
-    node _T_3702 = bits(buf_dual_in, 0, 0) @[lsu_bus_buffer.scala 511:74]
-    node _T_3703 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 511:107]
-    reg _T_3704 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when _T_3703 : @[Reg.scala 28:19]
-      _T_3704 <= _T_3702 @[Reg.scala 28:23]
+    buf_dualtag[0] <= _T_3709 @[lsu_bus_buffer.scala 513:20]
+    node _T_3710 = bits(buf_dual_in, 0, 0) @[lsu_bus_buffer.scala 514:74]
+    node _T_3711 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 514:107]
+    reg _T_3712 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_3711 : @[Reg.scala 28:19]
+      _T_3712 <= _T_3710 @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    buf_dual[0] <= _T_3704 @[lsu_bus_buffer.scala 511:17]
-    node _T_3705 = bits(buf_samedw_in, 0, 0) @[lsu_bus_buffer.scala 512:78]
-    node _T_3706 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 512:111]
-    reg _T_3707 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when _T_3706 : @[Reg.scala 28:19]
-      _T_3707 <= _T_3705 @[Reg.scala 28:23]
+    buf_dual[0] <= _T_3712 @[lsu_bus_buffer.scala 514:17]
+    node _T_3713 = bits(buf_samedw_in, 0, 0) @[lsu_bus_buffer.scala 515:78]
+    node _T_3714 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 515:111]
+    reg _T_3715 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_3714 : @[Reg.scala 28:19]
+      _T_3715 <= _T_3713 @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    buf_samedw[0] <= _T_3707 @[lsu_bus_buffer.scala 512:19]
-    node _T_3708 = bits(buf_nomerge_in, 0, 0) @[lsu_bus_buffer.scala 513:80]
-    node _T_3709 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 513:113]
-    reg _T_3710 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when _T_3709 : @[Reg.scala 28:19]
-      _T_3710 <= _T_3708 @[Reg.scala 28:23]
+    buf_samedw[0] <= _T_3715 @[lsu_bus_buffer.scala 515:19]
+    node _T_3716 = bits(buf_nomerge_in, 0, 0) @[lsu_bus_buffer.scala 516:80]
+    node _T_3717 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 516:113]
+    reg _T_3718 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_3717 : @[Reg.scala 28:19]
+      _T_3718 <= _T_3716 @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    buf_nomerge[0] <= _T_3710 @[lsu_bus_buffer.scala 513:20]
-    node _T_3711 = bits(buf_dualhi_in, 0, 0) @[lsu_bus_buffer.scala 514:78]
-    node _T_3712 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 514:111]
-    reg _T_3713 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when _T_3712 : @[Reg.scala 28:19]
-      _T_3713 <= _T_3711 @[Reg.scala 28:23]
+    buf_nomerge[0] <= _T_3718 @[lsu_bus_buffer.scala 516:20]
+    node _T_3719 = bits(buf_dualhi_in, 0, 0) @[lsu_bus_buffer.scala 517:78]
+    node _T_3720 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 517:111]
+    reg _T_3721 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_3720 : @[Reg.scala 28:19]
+      _T_3721 <= _T_3719 @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    buf_dualhi[0] <= _T_3713 @[lsu_bus_buffer.scala 514:19]
-    node _T_3714 = eq(UInt<3>("h00"), buf_state[1]) @[Conditional.scala 37:30]
-    when _T_3714 : @[Conditional.scala 40:58]
-      node _T_3715 = bits(io.lsu_bus_clk_en, 0, 0) @[lsu_bus_buffer.scala 445:56]
-      node _T_3716 = mux(_T_3715, UInt<3>("h02"), UInt<3>("h01")) @[lsu_bus_buffer.scala 445:31]
-      buf_nxtstate[1] <= _T_3716 @[lsu_bus_buffer.scala 445:25]
-      node _T_3717 = and(io.lsu_busreq_r, io.lsu_commit_r) @[lsu_bus_buffer.scala 446:45]
-      node _T_3718 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 446:77]
-      node _T_3719 = eq(ibuf_merge_en, UInt<1>("h00")) @[lsu_bus_buffer.scala 446:97]
-      node _T_3720 = and(_T_3718, _T_3719) @[lsu_bus_buffer.scala 446:95]
-      node _T_3721 = eq(UInt<1>("h01"), WrPtr0_r) @[lsu_bus_buffer.scala 446:117]
-      node _T_3722 = and(_T_3720, _T_3721) @[lsu_bus_buffer.scala 446:112]
-      node _T_3723 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 446:144]
-      node _T_3724 = eq(UInt<1>("h01"), WrPtr1_r) @[lsu_bus_buffer.scala 446:166]
-      node _T_3725 = and(_T_3723, _T_3724) @[lsu_bus_buffer.scala 446:161]
-      node _T_3726 = or(_T_3722, _T_3725) @[lsu_bus_buffer.scala 446:132]
-      node _T_3727 = and(_T_3717, _T_3726) @[lsu_bus_buffer.scala 446:63]
-      node _T_3728 = eq(UInt<1>("h01"), ibuf_tag) @[lsu_bus_buffer.scala 446:206]
-      node _T_3729 = and(ibuf_drain_vld, _T_3728) @[lsu_bus_buffer.scala 446:201]
-      node _T_3730 = or(_T_3727, _T_3729) @[lsu_bus_buffer.scala 446:183]
-      buf_state_en[1] <= _T_3730 @[lsu_bus_buffer.scala 446:25]
-      buf_wr_en[1] <= buf_state_en[1] @[lsu_bus_buffer.scala 447:22]
-      buf_data_en[1] <= buf_state_en[1] @[lsu_bus_buffer.scala 448:24]
-      node _T_3731 = eq(UInt<1>("h01"), ibuf_tag) @[lsu_bus_buffer.scala 449:52]
-      node _T_3732 = and(ibuf_drain_vld, _T_3731) @[lsu_bus_buffer.scala 449:47]
-      node _T_3733 = bits(_T_3732, 0, 0) @[lsu_bus_buffer.scala 449:73]
-      node _T_3734 = bits(ibuf_data_out, 31, 0) @[lsu_bus_buffer.scala 449:90]
-      node _T_3735 = bits(store_data_lo_r, 31, 0) @[lsu_bus_buffer.scala 449:114]
-      node _T_3736 = mux(_T_3733, _T_3734, _T_3735) @[lsu_bus_buffer.scala 449:30]
-      buf_data_in[1] <= _T_3736 @[lsu_bus_buffer.scala 449:24]
-      buf_cmd_state_bus_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 450:34]
+    buf_dualhi[0] <= _T_3721 @[lsu_bus_buffer.scala 517:19]
+    node _T_3722 = eq(UInt<3>("h00"), buf_state[1]) @[Conditional.scala 37:30]
+    when _T_3722 : @[Conditional.scala 40:58]
+      node _T_3723 = bits(io.lsu_bus_clk_en, 0, 0) @[lsu_bus_buffer.scala 442:56]
+      node _T_3724 = mux(_T_3723, UInt<3>("h02"), UInt<3>("h01")) @[lsu_bus_buffer.scala 442:31]
+      buf_nxtstate[1] <= _T_3724 @[lsu_bus_buffer.scala 442:25]
+      node _T_3725 = and(io.lsu_busreq_r, io.lsu_commit_r) @[lsu_bus_buffer.scala 443:45]
+      node _T_3726 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 443:77]
+      node _T_3727 = eq(ibuf_merge_en, UInt<1>("h00")) @[lsu_bus_buffer.scala 443:97]
+      node _T_3728 = and(_T_3726, _T_3727) @[lsu_bus_buffer.scala 443:95]
+      node _T_3729 = eq(UInt<1>("h01"), WrPtr0_r) @[lsu_bus_buffer.scala 443:117]
+      node _T_3730 = and(_T_3728, _T_3729) @[lsu_bus_buffer.scala 443:112]
+      node _T_3731 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 443:144]
+      node _T_3732 = eq(UInt<1>("h01"), WrPtr1_r) @[lsu_bus_buffer.scala 443:166]
+      node _T_3733 = and(_T_3731, _T_3732) @[lsu_bus_buffer.scala 443:161]
+      node _T_3734 = or(_T_3730, _T_3733) @[lsu_bus_buffer.scala 443:132]
+      node _T_3735 = and(_T_3725, _T_3734) @[lsu_bus_buffer.scala 443:63]
+      node _T_3736 = eq(UInt<1>("h01"), ibuf_tag) @[lsu_bus_buffer.scala 443:206]
+      node _T_3737 = and(ibuf_drain_vld, _T_3736) @[lsu_bus_buffer.scala 443:201]
+      node _T_3738 = or(_T_3735, _T_3737) @[lsu_bus_buffer.scala 443:183]
+      buf_state_en[1] <= _T_3738 @[lsu_bus_buffer.scala 443:25]
+      buf_wr_en[1] <= buf_state_en[1] @[lsu_bus_buffer.scala 444:22]
+      buf_data_en[1] <= buf_state_en[1] @[lsu_bus_buffer.scala 445:24]
+      node _T_3739 = eq(UInt<1>("h01"), ibuf_tag) @[lsu_bus_buffer.scala 446:52]
+      node _T_3740 = and(ibuf_drain_vld, _T_3739) @[lsu_bus_buffer.scala 446:47]
+      node _T_3741 = bits(_T_3740, 0, 0) @[lsu_bus_buffer.scala 446:73]
+      node _T_3742 = bits(ibuf_data_out, 31, 0) @[lsu_bus_buffer.scala 446:90]
+      node _T_3743 = bits(store_data_lo_r, 31, 0) @[lsu_bus_buffer.scala 446:114]
+      node _T_3744 = mux(_T_3741, _T_3742, _T_3743) @[lsu_bus_buffer.scala 446:30]
+      buf_data_in[1] <= _T_3744 @[lsu_bus_buffer.scala 446:24]
+      buf_cmd_state_bus_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 447:34]
+      buf_rst[1] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 448:21]
       skip @[Conditional.scala 40:58]
     else : @[Conditional.scala 39:67]
-      node _T_3737 = eq(UInt<3>("h01"), buf_state[1]) @[Conditional.scala 37:30]
-      when _T_3737 : @[Conditional.scala 39:67]
-        node _T_3738 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 453:60]
-        node _T_3739 = mux(_T_3738, UInt<3>("h00"), UInt<3>("h02")) @[lsu_bus_buffer.scala 453:31]
-        buf_nxtstate[1] <= _T_3739 @[lsu_bus_buffer.scala 453:25]
-        node _T_3740 = or(io.lsu_bus_clk_en, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 454:46]
-        buf_state_en[1] <= _T_3740 @[lsu_bus_buffer.scala 454:25]
-        buf_cmd_state_bus_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 455:34]
+      node _T_3745 = eq(UInt<3>("h01"), buf_state[1]) @[Conditional.scala 37:30]
+      when _T_3745 : @[Conditional.scala 39:67]
+        node _T_3746 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 451:60]
+        node _T_3747 = mux(_T_3746, UInt<3>("h00"), UInt<3>("h02")) @[lsu_bus_buffer.scala 451:31]
+        buf_nxtstate[1] <= _T_3747 @[lsu_bus_buffer.scala 451:25]
+        node _T_3748 = or(io.lsu_bus_clk_en, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 452:46]
+        buf_state_en[1] <= _T_3748 @[lsu_bus_buffer.scala 452:25]
+        buf_cmd_state_bus_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 453:34]
+        buf_rst[1] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 454:20]
         skip @[Conditional.scala 39:67]
       else : @[Conditional.scala 39:67]
-        node _T_3741 = eq(UInt<3>("h02"), buf_state[1]) @[Conditional.scala 37:30]
-        when _T_3741 : @[Conditional.scala 39:67]
-          node _T_3742 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 458:60]
-          node _T_3743 = and(obuf_nosend, bus_rsp_read) @[lsu_bus_buffer.scala 458:89]
-          node _T_3744 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[lsu_bus_buffer.scala 458:124]
-          node _T_3745 = and(_T_3743, _T_3744) @[lsu_bus_buffer.scala 458:104]
-          node _T_3746 = mux(_T_3745, UInt<3>("h05"), UInt<3>("h03")) @[lsu_bus_buffer.scala 458:75]
-          node _T_3747 = mux(_T_3742, UInt<3>("h00"), _T_3746) @[lsu_bus_buffer.scala 458:31]
-          buf_nxtstate[1] <= _T_3747 @[lsu_bus_buffer.scala 458:25]
-          node _T_3748 = eq(obuf_tag0, UInt<3>("h01")) @[lsu_bus_buffer.scala 459:48]
-          node _T_3749 = eq(obuf_tag1, UInt<3>("h01")) @[lsu_bus_buffer.scala 459:104]
-          node _T_3750 = and(obuf_merge, _T_3749) @[lsu_bus_buffer.scala 459:91]
-          node _T_3751 = or(_T_3748, _T_3750) @[lsu_bus_buffer.scala 459:77]
-          node _T_3752 = and(_T_3751, obuf_valid) @[lsu_bus_buffer.scala 459:135]
-          node _T_3753 = and(_T_3752, obuf_wr_enQ) @[lsu_bus_buffer.scala 459:148]
-          buf_cmd_state_bus_en[1] <= _T_3753 @[lsu_bus_buffer.scala 459:33]
-          buf_state_bus_en[1] <= buf_cmd_state_bus_en[1] @[lsu_bus_buffer.scala 460:29]
-          node _T_3754 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 461:49]
-          node _T_3755 = or(_T_3754, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 461:70]
-          buf_state_en[1] <= _T_3755 @[lsu_bus_buffer.scala 461:25]
-          buf_ldfwd_in[1] <= UInt<1>("h01") @[lsu_bus_buffer.scala 462:25]
-          node _T_3756 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 463:56]
-          node _T_3757 = eq(_T_3756, UInt<1>("h00")) @[lsu_bus_buffer.scala 463:46]
-          node _T_3758 = and(buf_state_en[1], _T_3757) @[lsu_bus_buffer.scala 463:44]
-          node _T_3759 = and(_T_3758, obuf_nosend) @[lsu_bus_buffer.scala 463:60]
-          node _T_3760 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 463:76]
-          node _T_3761 = and(_T_3759, _T_3760) @[lsu_bus_buffer.scala 463:74]
-          buf_ldfwd_en[1] <= _T_3761 @[lsu_bus_buffer.scala 463:25]
-          node _T_3762 = bits(obuf_rdrsp_tag, 1, 0) @[lsu_bus_buffer.scala 464:46]
-          buf_ldfwdtag_in[1] <= _T_3762 @[lsu_bus_buffer.scala 464:28]
-          node _T_3763 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 465:47]
-          node _T_3764 = and(_T_3763, obuf_nosend) @[lsu_bus_buffer.scala 465:67]
-          node _T_3765 = and(_T_3764, bus_rsp_read) @[lsu_bus_buffer.scala 465:81]
-          buf_data_en[1] <= _T_3765 @[lsu_bus_buffer.scala 465:24]
-          node _T_3766 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 466:48]
-          node _T_3767 = and(_T_3766, obuf_nosend) @[lsu_bus_buffer.scala 466:68]
-          node _T_3768 = and(_T_3767, bus_rsp_read_error) @[lsu_bus_buffer.scala 466:82]
-          buf_error_en[1] <= _T_3768 @[lsu_bus_buffer.scala 466:25]
-          node _T_3769 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 467:61]
-          node _T_3770 = bits(buf_addr[1], 2, 2) @[lsu_bus_buffer.scala 467:85]
-          node _T_3771 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 467:103]
-          node _T_3772 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 467:126]
-          node _T_3773 = mux(_T_3770, _T_3771, _T_3772) @[lsu_bus_buffer.scala 467:73]
-          node _T_3774 = mux(buf_error_en[1], _T_3769, _T_3773) @[lsu_bus_buffer.scala 467:30]
-          buf_data_in[1] <= _T_3774 @[lsu_bus_buffer.scala 467:24]
+        node _T_3749 = eq(UInt<3>("h02"), buf_state[1]) @[Conditional.scala 37:30]
+        when _T_3749 : @[Conditional.scala 39:67]
+          node _T_3750 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 457:60]
+          node _T_3751 = and(obuf_nosend, bus_rsp_read) @[lsu_bus_buffer.scala 457:89]
+          node _T_3752 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[lsu_bus_buffer.scala 457:124]
+          node _T_3753 = and(_T_3751, _T_3752) @[lsu_bus_buffer.scala 457:104]
+          node _T_3754 = mux(_T_3753, UInt<3>("h05"), UInt<3>("h03")) @[lsu_bus_buffer.scala 457:75]
+          node _T_3755 = mux(_T_3750, UInt<3>("h00"), _T_3754) @[lsu_bus_buffer.scala 457:31]
+          buf_nxtstate[1] <= _T_3755 @[lsu_bus_buffer.scala 457:25]
+          node _T_3756 = eq(obuf_tag0, UInt<3>("h01")) @[lsu_bus_buffer.scala 458:48]
+          node _T_3757 = eq(obuf_tag1, UInt<3>("h01")) @[lsu_bus_buffer.scala 458:104]
+          node _T_3758 = and(obuf_merge, _T_3757) @[lsu_bus_buffer.scala 458:91]
+          node _T_3759 = or(_T_3756, _T_3758) @[lsu_bus_buffer.scala 458:77]
+          node _T_3760 = and(_T_3759, obuf_valid) @[lsu_bus_buffer.scala 458:135]
+          node _T_3761 = and(_T_3760, obuf_wr_enQ) @[lsu_bus_buffer.scala 458:148]
+          buf_cmd_state_bus_en[1] <= _T_3761 @[lsu_bus_buffer.scala 458:33]
+          buf_state_bus_en[1] <= buf_cmd_state_bus_en[1] @[lsu_bus_buffer.scala 459:29]
+          node _T_3762 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 460:49]
+          node _T_3763 = or(_T_3762, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 460:70]
+          buf_state_en[1] <= _T_3763 @[lsu_bus_buffer.scala 460:25]
+          buf_ldfwd_in[1] <= UInt<1>("h01") @[lsu_bus_buffer.scala 461:25]
+          node _T_3764 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 462:56]
+          node _T_3765 = eq(_T_3764, UInt<1>("h00")) @[lsu_bus_buffer.scala 462:46]
+          node _T_3766 = and(buf_state_en[1], _T_3765) @[lsu_bus_buffer.scala 462:44]
+          node _T_3767 = and(_T_3766, obuf_nosend) @[lsu_bus_buffer.scala 462:60]
+          node _T_3768 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 462:76]
+          node _T_3769 = and(_T_3767, _T_3768) @[lsu_bus_buffer.scala 462:74]
+          buf_ldfwd_en[1] <= _T_3769 @[lsu_bus_buffer.scala 462:25]
+          node _T_3770 = bits(obuf_rdrsp_tag, 1, 0) @[lsu_bus_buffer.scala 463:46]
+          buf_ldfwdtag_in[1] <= _T_3770 @[lsu_bus_buffer.scala 463:28]
+          node _T_3771 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 464:47]
+          node _T_3772 = and(_T_3771, obuf_nosend) @[lsu_bus_buffer.scala 464:67]
+          node _T_3773 = and(_T_3772, bus_rsp_read) @[lsu_bus_buffer.scala 464:81]
+          buf_data_en[1] <= _T_3773 @[lsu_bus_buffer.scala 464:24]
+          node _T_3774 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 465:48]
+          node _T_3775 = and(_T_3774, obuf_nosend) @[lsu_bus_buffer.scala 465:68]
+          node _T_3776 = and(_T_3775, bus_rsp_read_error) @[lsu_bus_buffer.scala 465:82]
+          buf_error_en[1] <= _T_3776 @[lsu_bus_buffer.scala 465:25]
+          node _T_3777 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 466:61]
+          node _T_3778 = bits(buf_addr[1], 2, 2) @[lsu_bus_buffer.scala 466:85]
+          node _T_3779 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 466:103]
+          node _T_3780 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 466:126]
+          node _T_3781 = mux(_T_3778, _T_3779, _T_3780) @[lsu_bus_buffer.scala 466:73]
+          node _T_3782 = mux(buf_error_en[1], _T_3777, _T_3781) @[lsu_bus_buffer.scala 466:30]
+          buf_data_in[1] <= _T_3782 @[lsu_bus_buffer.scala 466:24]
+          buf_rst[1] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 467:20]
           skip @[Conditional.scala 39:67]
         else : @[Conditional.scala 39:67]
-          node _T_3775 = eq(UInt<3>("h03"), buf_state[1]) @[Conditional.scala 37:30]
-          when _T_3775 : @[Conditional.scala 39:67]
-            node _T_3776 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 470:67]
-            node _T_3777 = and(_T_3776, bus_rsp_write_error) @[lsu_bus_buffer.scala 470:71]
-            node _T_3778 = or(io.dec_tlu_force_halt, _T_3777) @[lsu_bus_buffer.scala 470:55]
-            node _T_3779 = bits(_T_3778, 0, 0) @[lsu_bus_buffer.scala 470:101]
-            node _T_3780 = eq(buf_samedw[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 471:30]
-            node _T_3781 = and(buf_dual[1], _T_3780) @[lsu_bus_buffer.scala 471:28]
-            node _T_3782 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 471:57]
-            node _T_3783 = eq(_T_3782, UInt<1>("h00")) @[lsu_bus_buffer.scala 471:47]
-            node _T_3784 = and(_T_3781, _T_3783) @[lsu_bus_buffer.scala 471:45]
-            node _T_3785 = neq(buf_state[buf_dualtag[1]], UInt<3>("h04")) @[lsu_bus_buffer.scala 471:90]
-            node _T_3786 = and(_T_3784, _T_3785) @[lsu_bus_buffer.scala 471:61]
-            node _T_3787 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 472:27]
-            node _T_3788 = or(_T_3787, any_done_wait_state) @[lsu_bus_buffer.scala 472:31]
-            node _T_3789 = eq(buf_samedw[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 472:70]
-            node _T_3790 = and(buf_dual[1], _T_3789) @[lsu_bus_buffer.scala 472:68]
-            node _T_3791 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 472:97]
-            node _T_3792 = eq(_T_3791, UInt<1>("h00")) @[lsu_bus_buffer.scala 472:87]
-            node _T_3793 = and(_T_3790, _T_3792) @[lsu_bus_buffer.scala 472:85]
-            node _T_3794 = eq(buf_dualtag[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 60:118]
-            node _T_3795 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 60:129]
-            node _T_3796 = eq(buf_dualtag[1], UInt<1>("h01")) @[lsu_bus_buffer.scala 60:118]
-            node _T_3797 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 60:129]
-            node _T_3798 = eq(buf_dualtag[1], UInt<2>("h02")) @[lsu_bus_buffer.scala 60:118]
-            node _T_3799 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 60:129]
-            node _T_3800 = eq(buf_dualtag[1], UInt<2>("h03")) @[lsu_bus_buffer.scala 60:118]
-            node _T_3801 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 60:129]
-            node _T_3802 = mux(_T_3794, _T_3795, UInt<1>("h00")) @[Mux.scala 27:72]
-            node _T_3803 = mux(_T_3796, _T_3797, UInt<1>("h00")) @[Mux.scala 27:72]
-            node _T_3804 = mux(_T_3798, _T_3799, UInt<1>("h00")) @[Mux.scala 27:72]
-            node _T_3805 = mux(_T_3800, _T_3801, UInt<1>("h00")) @[Mux.scala 27:72]
-            node _T_3806 = or(_T_3802, _T_3803) @[Mux.scala 27:72]
-            node _T_3807 = or(_T_3806, _T_3804) @[Mux.scala 27:72]
-            node _T_3808 = or(_T_3807, _T_3805) @[Mux.scala 27:72]
-            wire _T_3809 : UInt<1> @[Mux.scala 27:72]
-            _T_3809 <= _T_3808 @[Mux.scala 27:72]
-            node _T_3810 = and(_T_3793, _T_3809) @[lsu_bus_buffer.scala 472:101]
-            node _T_3811 = eq(buf_state[buf_dualtag[1]], UInt<3>("h04")) @[lsu_bus_buffer.scala 472:167]
-            node _T_3812 = and(_T_3810, _T_3811) @[lsu_bus_buffer.scala 472:138]
-            node _T_3813 = and(_T_3812, any_done_wait_state) @[lsu_bus_buffer.scala 472:187]
-            node _T_3814 = or(_T_3788, _T_3813) @[lsu_bus_buffer.scala 472:53]
-            node _T_3815 = mux(_T_3814, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 472:16]
-            node _T_3816 = mux(_T_3786, UInt<3>("h04"), _T_3815) @[lsu_bus_buffer.scala 471:14]
-            node _T_3817 = mux(_T_3779, UInt<3>("h00"), _T_3816) @[lsu_bus_buffer.scala 470:31]
-            buf_nxtstate[1] <= _T_3817 @[lsu_bus_buffer.scala 470:25]
-            node _T_3818 = eq(bus_rsp_write_tag, UInt<3>("h01")) @[lsu_bus_buffer.scala 473:73]
-            node _T_3819 = and(bus_rsp_write, _T_3818) @[lsu_bus_buffer.scala 473:52]
-            node _T_3820 = eq(bus_rsp_read_tag, UInt<3>("h01")) @[lsu_bus_buffer.scala 474:46]
-            node _T_3821 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 475:23]
-            node _T_3822 = eq(bus_rsp_read_tag, buf_ldfwdtag[1]) @[lsu_bus_buffer.scala 475:47]
-            node _T_3823 = and(_T_3821, _T_3822) @[lsu_bus_buffer.scala 475:27]
-            node _T_3824 = or(_T_3820, _T_3823) @[lsu_bus_buffer.scala 474:77]
-            node _T_3825 = and(buf_dual[1], buf_dualhi[1]) @[lsu_bus_buffer.scala 476:26]
-            node _T_3826 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 476:54]
-            node _T_3827 = not(_T_3826) @[lsu_bus_buffer.scala 476:44]
-            node _T_3828 = and(_T_3825, _T_3827) @[lsu_bus_buffer.scala 476:42]
-            node _T_3829 = and(_T_3828, buf_samedw[1]) @[lsu_bus_buffer.scala 476:58]
-            node _T_3830 = eq(bus_rsp_read_tag, buf_dualtag[1]) @[lsu_bus_buffer.scala 476:94]
-            node _T_3831 = and(_T_3829, _T_3830) @[lsu_bus_buffer.scala 476:74]
-            node _T_3832 = or(_T_3824, _T_3831) @[lsu_bus_buffer.scala 475:71]
-            node _T_3833 = and(bus_rsp_read, _T_3832) @[lsu_bus_buffer.scala 474:25]
-            node _T_3834 = or(_T_3819, _T_3833) @[lsu_bus_buffer.scala 473:105]
-            buf_resp_state_bus_en[1] <= _T_3834 @[lsu_bus_buffer.scala 473:34]
+          node _T_3783 = eq(UInt<3>("h03"), buf_state[1]) @[Conditional.scala 37:30]
+          when _T_3783 : @[Conditional.scala 39:67]
+            node _T_3784 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 470:69]
+            node _T_3785 = eq(bus_rsp_write_error, UInt<1>("h00")) @[lsu_bus_buffer.scala 470:75]
+            node _T_3786 = and(_T_3784, _T_3785) @[lsu_bus_buffer.scala 470:73]
+            node _T_3787 = or(io.dec_tlu_force_halt, _T_3786) @[lsu_bus_buffer.scala 470:57]
+            node _T_3788 = bits(_T_3787, 0, 0) @[lsu_bus_buffer.scala 470:104]
+            node _T_3789 = eq(buf_samedw[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 471:30]
+            node _T_3790 = and(buf_dual[1], _T_3789) @[lsu_bus_buffer.scala 471:28]
+            node _T_3791 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 471:57]
+            node _T_3792 = eq(_T_3791, UInt<1>("h00")) @[lsu_bus_buffer.scala 471:47]
+            node _T_3793 = and(_T_3790, _T_3792) @[lsu_bus_buffer.scala 471:45]
+            node _T_3794 = neq(buf_state[buf_dualtag[1]], UInt<3>("h04")) @[lsu_bus_buffer.scala 471:90]
+            node _T_3795 = and(_T_3793, _T_3794) @[lsu_bus_buffer.scala 471:61]
+            node _T_3796 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 472:27]
+            node _T_3797 = or(_T_3796, any_done_wait_state) @[lsu_bus_buffer.scala 472:31]
+            node _T_3798 = eq(buf_samedw[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 472:70]
+            node _T_3799 = and(buf_dual[1], _T_3798) @[lsu_bus_buffer.scala 472:68]
+            node _T_3800 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 472:97]
+            node _T_3801 = eq(_T_3800, UInt<1>("h00")) @[lsu_bus_buffer.scala 472:87]
+            node _T_3802 = and(_T_3799, _T_3801) @[lsu_bus_buffer.scala 472:85]
+            node _T_3803 = eq(buf_dualtag[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 60:118]
+            node _T_3804 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 60:129]
+            node _T_3805 = eq(buf_dualtag[1], UInt<1>("h01")) @[lsu_bus_buffer.scala 60:118]
+            node _T_3806 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 60:129]
+            node _T_3807 = eq(buf_dualtag[1], UInt<2>("h02")) @[lsu_bus_buffer.scala 60:118]
+            node _T_3808 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 60:129]
+            node _T_3809 = eq(buf_dualtag[1], UInt<2>("h03")) @[lsu_bus_buffer.scala 60:118]
+            node _T_3810 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 60:129]
+            node _T_3811 = mux(_T_3803, _T_3804, UInt<1>("h00")) @[Mux.scala 27:72]
+            node _T_3812 = mux(_T_3805, _T_3806, UInt<1>("h00")) @[Mux.scala 27:72]
+            node _T_3813 = mux(_T_3807, _T_3808, UInt<1>("h00")) @[Mux.scala 27:72]
+            node _T_3814 = mux(_T_3809, _T_3810, UInt<1>("h00")) @[Mux.scala 27:72]
+            node _T_3815 = or(_T_3811, _T_3812) @[Mux.scala 27:72]
+            node _T_3816 = or(_T_3815, _T_3813) @[Mux.scala 27:72]
+            node _T_3817 = or(_T_3816, _T_3814) @[Mux.scala 27:72]
+            wire _T_3818 : UInt<1> @[Mux.scala 27:72]
+            _T_3818 <= _T_3817 @[Mux.scala 27:72]
+            node _T_3819 = and(_T_3802, _T_3818) @[lsu_bus_buffer.scala 472:101]
+            node _T_3820 = eq(buf_state[buf_dualtag[1]], UInt<3>("h04")) @[lsu_bus_buffer.scala 472:167]
+            node _T_3821 = and(_T_3819, _T_3820) @[lsu_bus_buffer.scala 472:138]
+            node _T_3822 = and(_T_3821, any_done_wait_state) @[lsu_bus_buffer.scala 472:187]
+            node _T_3823 = or(_T_3797, _T_3822) @[lsu_bus_buffer.scala 472:53]
+            node _T_3824 = mux(_T_3823, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 472:16]
+            node _T_3825 = mux(_T_3795, UInt<3>("h04"), _T_3824) @[lsu_bus_buffer.scala 471:14]
+            node _T_3826 = mux(_T_3788, UInt<3>("h00"), _T_3825) @[lsu_bus_buffer.scala 470:33]
+            buf_nxtstate[1] <= _T_3826 @[lsu_bus_buffer.scala 470:27]
+            node _T_3827 = eq(bus_rsp_write_tag, UInt<3>("h01")) @[lsu_bus_buffer.scala 473:73]
+            node _T_3828 = and(bus_rsp_write, _T_3827) @[lsu_bus_buffer.scala 473:52]
+            node _T_3829 = eq(bus_rsp_read_tag, UInt<3>("h01")) @[lsu_bus_buffer.scala 474:46]
+            node _T_3830 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 475:23]
+            node _T_3831 = eq(bus_rsp_read_tag, buf_ldfwdtag[1]) @[lsu_bus_buffer.scala 475:47]
+            node _T_3832 = and(_T_3830, _T_3831) @[lsu_bus_buffer.scala 475:27]
+            node _T_3833 = or(_T_3829, _T_3832) @[lsu_bus_buffer.scala 474:77]
+            node _T_3834 = and(buf_dual[1], buf_dualhi[1]) @[lsu_bus_buffer.scala 476:26]
+            node _T_3835 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 476:54]
+            node _T_3836 = not(_T_3835) @[lsu_bus_buffer.scala 476:44]
+            node _T_3837 = and(_T_3834, _T_3836) @[lsu_bus_buffer.scala 476:42]
+            node _T_3838 = and(_T_3837, buf_samedw[1]) @[lsu_bus_buffer.scala 476:58]
+            node _T_3839 = eq(bus_rsp_read_tag, buf_dualtag[1]) @[lsu_bus_buffer.scala 476:94]
+            node _T_3840 = and(_T_3838, _T_3839) @[lsu_bus_buffer.scala 476:74]
+            node _T_3841 = or(_T_3833, _T_3840) @[lsu_bus_buffer.scala 475:71]
+            node _T_3842 = and(bus_rsp_read, _T_3841) @[lsu_bus_buffer.scala 474:25]
+            node _T_3843 = or(_T_3828, _T_3842) @[lsu_bus_buffer.scala 473:105]
+            buf_resp_state_bus_en[1] <= _T_3843 @[lsu_bus_buffer.scala 473:34]
             buf_state_bus_en[1] <= buf_resp_state_bus_en[1] @[lsu_bus_buffer.scala 477:29]
-            node _T_3835 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 478:49]
-            node _T_3836 = or(_T_3835, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 478:70]
-            buf_state_en[1] <= _T_3836 @[lsu_bus_buffer.scala 478:25]
-            node _T_3837 = and(buf_state_bus_en[1], bus_rsp_read) @[lsu_bus_buffer.scala 479:47]
-            node _T_3838 = and(_T_3837, io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 479:62]
-            buf_data_en[1] <= _T_3838 @[lsu_bus_buffer.scala 479:24]
-            node _T_3839 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 480:48]
-            node _T_3840 = eq(bus_rsp_read_tag, UInt<3>("h01")) @[lsu_bus_buffer.scala 480:111]
-            node _T_3841 = and(bus_rsp_read_error, _T_3840) @[lsu_bus_buffer.scala 480:91]
-            node _T_3842 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 481:42]
-            node _T_3843 = and(bus_rsp_read_error, _T_3842) @[lsu_bus_buffer.scala 481:31]
-            node _T_3844 = eq(bus_rsp_read_tag, buf_ldfwdtag[1]) @[lsu_bus_buffer.scala 481:66]
-            node _T_3845 = and(_T_3843, _T_3844) @[lsu_bus_buffer.scala 481:46]
-            node _T_3846 = or(_T_3841, _T_3845) @[lsu_bus_buffer.scala 480:143]
-            node _T_3847 = eq(bus_rsp_write_tag, UInt<3>("h01")) @[lsu_bus_buffer.scala 482:54]
-            node _T_3848 = and(bus_rsp_write_error, _T_3847) @[lsu_bus_buffer.scala 482:33]
-            node _T_3849 = or(_T_3846, _T_3848) @[lsu_bus_buffer.scala 481:88]
-            node _T_3850 = and(_T_3839, _T_3849) @[lsu_bus_buffer.scala 480:68]
-            buf_error_en[1] <= _T_3850 @[lsu_bus_buffer.scala 480:25]
-            node _T_3851 = eq(buf_error_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 483:50]
-            node _T_3852 = and(buf_state_en[1], _T_3851) @[lsu_bus_buffer.scala 483:48]
-            node _T_3853 = bits(buf_addr[1], 2, 2) @[lsu_bus_buffer.scala 483:84]
-            node _T_3854 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 483:102]
-            node _T_3855 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 483:125]
-            node _T_3856 = mux(_T_3853, _T_3854, _T_3855) @[lsu_bus_buffer.scala 483:72]
-            node _T_3857 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 483:148]
-            node _T_3858 = mux(_T_3852, _T_3856, _T_3857) @[lsu_bus_buffer.scala 483:30]
-            buf_data_in[1] <= _T_3858 @[lsu_bus_buffer.scala 483:24]
+            node _T_3844 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 478:49]
+            node _T_3845 = or(_T_3844, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 478:70]
+            buf_state_en[1] <= _T_3845 @[lsu_bus_buffer.scala 478:25]
+            node _T_3846 = and(buf_state_bus_en[1], bus_rsp_read) @[lsu_bus_buffer.scala 479:47]
+            node _T_3847 = and(_T_3846, io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 479:62]
+            buf_data_en[1] <= _T_3847 @[lsu_bus_buffer.scala 479:24]
+            node _T_3848 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 480:48]
+            node _T_3849 = eq(bus_rsp_read_tag, UInt<3>("h01")) @[lsu_bus_buffer.scala 480:111]
+            node _T_3850 = and(bus_rsp_read_error, _T_3849) @[lsu_bus_buffer.scala 480:91]
+            node _T_3851 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 481:42]
+            node _T_3852 = and(bus_rsp_read_error, _T_3851) @[lsu_bus_buffer.scala 481:31]
+            node _T_3853 = eq(bus_rsp_read_tag, buf_ldfwdtag[1]) @[lsu_bus_buffer.scala 481:66]
+            node _T_3854 = and(_T_3852, _T_3853) @[lsu_bus_buffer.scala 481:46]
+            node _T_3855 = or(_T_3850, _T_3854) @[lsu_bus_buffer.scala 480:143]
+            node _T_3856 = eq(bus_rsp_write_tag, UInt<3>("h01")) @[lsu_bus_buffer.scala 482:54]
+            node _T_3857 = and(bus_rsp_write_error, _T_3856) @[lsu_bus_buffer.scala 482:33]
+            node _T_3858 = or(_T_3855, _T_3857) @[lsu_bus_buffer.scala 481:88]
+            node _T_3859 = and(_T_3848, _T_3858) @[lsu_bus_buffer.scala 480:68]
+            buf_error_en[1] <= _T_3859 @[lsu_bus_buffer.scala 480:25]
+            node _T_3860 = eq(buf_error_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 483:50]
+            node _T_3861 = and(buf_state_en[1], _T_3860) @[lsu_bus_buffer.scala 483:48]
+            node _T_3862 = bits(buf_addr[1], 2, 2) @[lsu_bus_buffer.scala 483:84]
+            node _T_3863 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 483:102]
+            node _T_3864 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 483:125]
+            node _T_3865 = mux(_T_3862, _T_3863, _T_3864) @[lsu_bus_buffer.scala 483:72]
+            node _T_3866 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 483:148]
+            node _T_3867 = mux(_T_3861, _T_3865, _T_3866) @[lsu_bus_buffer.scala 483:30]
+            buf_data_in[1] <= _T_3867 @[lsu_bus_buffer.scala 483:24]
             buf_cmd_state_bus_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 484:34]
+            buf_rst[1] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 485:20]
             skip @[Conditional.scala 39:67]
           else : @[Conditional.scala 39:67]
-            node _T_3859 = eq(UInt<3>("h04"), buf_state[1]) @[Conditional.scala 37:30]
-            when _T_3859 : @[Conditional.scala 39:67]
-              node _T_3860 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 487:60]
-              node _T_3861 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 487:86]
-              node _T_3862 = dshr(buf_ldfwd, buf_dualtag[1]) @[lsu_bus_buffer.scala 487:101]
-              node _T_3863 = bits(_T_3862, 0, 0) @[lsu_bus_buffer.scala 487:101]
-              node _T_3864 = or(_T_3861, _T_3863) @[lsu_bus_buffer.scala 487:90]
-              node _T_3865 = or(_T_3864, any_done_wait_state) @[lsu_bus_buffer.scala 487:118]
-              node _T_3866 = mux(_T_3865, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 487:75]
-              node _T_3867 = mux(_T_3860, UInt<3>("h00"), _T_3866) @[lsu_bus_buffer.scala 487:31]
-              buf_nxtstate[1] <= _T_3867 @[lsu_bus_buffer.scala 487:25]
-              node _T_3868 = eq(bus_rsp_read_tag, buf_dualtag[1]) @[lsu_bus_buffer.scala 488:66]
-              node _T_3869 = dshr(buf_ldfwd, buf_dualtag[1]) @[lsu_bus_buffer.scala 489:21]
-              node _T_3870 = bits(_T_3869, 0, 0) @[lsu_bus_buffer.scala 489:21]
-              node _T_3871 = eq(bus_rsp_read_tag, buf_ldfwdtag[buf_dualtag[1]]) @[lsu_bus_buffer.scala 489:58]
-              node _T_3872 = and(_T_3870, _T_3871) @[lsu_bus_buffer.scala 489:38]
-              node _T_3873 = or(_T_3868, _T_3872) @[lsu_bus_buffer.scala 488:95]
-              node _T_3874 = and(bus_rsp_read, _T_3873) @[lsu_bus_buffer.scala 488:45]
-              buf_state_bus_en[1] <= _T_3874 @[lsu_bus_buffer.scala 488:29]
-              node _T_3875 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 490:49]
-              node _T_3876 = or(_T_3875, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 490:70]
-              buf_state_en[1] <= _T_3876 @[lsu_bus_buffer.scala 490:25]
-              buf_cmd_state_bus_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 491:34]
+            node _T_3868 = eq(UInt<3>("h04"), buf_state[1]) @[Conditional.scala 37:30]
+            when _T_3868 : @[Conditional.scala 39:67]
+              node _T_3869 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 488:60]
+              node _T_3870 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 488:86]
+              node _T_3871 = dshr(buf_ldfwd, buf_dualtag[1]) @[lsu_bus_buffer.scala 488:101]
+              node _T_3872 = bits(_T_3871, 0, 0) @[lsu_bus_buffer.scala 488:101]
+              node _T_3873 = or(_T_3870, _T_3872) @[lsu_bus_buffer.scala 488:90]
+              node _T_3874 = or(_T_3873, any_done_wait_state) @[lsu_bus_buffer.scala 488:118]
+              node _T_3875 = mux(_T_3874, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 488:75]
+              node _T_3876 = mux(_T_3869, UInt<3>("h00"), _T_3875) @[lsu_bus_buffer.scala 488:31]
+              buf_nxtstate[1] <= _T_3876 @[lsu_bus_buffer.scala 488:25]
+              node _T_3877 = eq(bus_rsp_read_tag, buf_dualtag[1]) @[lsu_bus_buffer.scala 489:66]
+              node _T_3878 = dshr(buf_ldfwd, buf_dualtag[1]) @[lsu_bus_buffer.scala 490:21]
+              node _T_3879 = bits(_T_3878, 0, 0) @[lsu_bus_buffer.scala 490:21]
+              node _T_3880 = eq(bus_rsp_read_tag, buf_ldfwdtag[buf_dualtag[1]]) @[lsu_bus_buffer.scala 490:58]
+              node _T_3881 = and(_T_3879, _T_3880) @[lsu_bus_buffer.scala 490:38]
+              node _T_3882 = or(_T_3877, _T_3881) @[lsu_bus_buffer.scala 489:95]
+              node _T_3883 = and(bus_rsp_read, _T_3882) @[lsu_bus_buffer.scala 489:45]
+              buf_state_bus_en[1] <= _T_3883 @[lsu_bus_buffer.scala 489:29]
+              node _T_3884 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 491:49]
+              node _T_3885 = or(_T_3884, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 491:70]
+              buf_state_en[1] <= _T_3885 @[lsu_bus_buffer.scala 491:25]
+              buf_cmd_state_bus_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 492:34]
+              buf_rst[1] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 493:20]
               skip @[Conditional.scala 39:67]
             else : @[Conditional.scala 39:67]
-              node _T_3877 = eq(UInt<3>("h05"), buf_state[1]) @[Conditional.scala 37:30]
-              when _T_3877 : @[Conditional.scala 39:67]
-                node _T_3878 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 494:60]
-                node _T_3879 = mux(_T_3878, UInt<3>("h00"), UInt<3>("h06")) @[lsu_bus_buffer.scala 494:31]
-                buf_nxtstate[1] <= _T_3879 @[lsu_bus_buffer.scala 494:25]
-                node _T_3880 = eq(RspPtr, UInt<2>("h01")) @[lsu_bus_buffer.scala 495:37]
-                node _T_3881 = eq(buf_dualtag[1], RspPtr) @[lsu_bus_buffer.scala 495:98]
-                node _T_3882 = and(buf_dual[1], _T_3881) @[lsu_bus_buffer.scala 495:80]
-                node _T_3883 = or(_T_3880, _T_3882) @[lsu_bus_buffer.scala 495:65]
-                node _T_3884 = or(_T_3883, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 495:112]
-                buf_state_en[1] <= _T_3884 @[lsu_bus_buffer.scala 495:25]
-                buf_cmd_state_bus_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 496:34]
+              node _T_3886 = eq(UInt<3>("h05"), buf_state[1]) @[Conditional.scala 37:30]
+              when _T_3886 : @[Conditional.scala 39:67]
+                node _T_3887 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 496:60]
+                node _T_3888 = mux(_T_3887, UInt<3>("h00"), UInt<3>("h06")) @[lsu_bus_buffer.scala 496:31]
+                buf_nxtstate[1] <= _T_3888 @[lsu_bus_buffer.scala 496:25]
+                node _T_3889 = eq(RspPtr, UInt<2>("h01")) @[lsu_bus_buffer.scala 497:37]
+                node _T_3890 = eq(buf_dualtag[1], RspPtr) @[lsu_bus_buffer.scala 497:98]
+                node _T_3891 = and(buf_dual[1], _T_3890) @[lsu_bus_buffer.scala 497:80]
+                node _T_3892 = or(_T_3889, _T_3891) @[lsu_bus_buffer.scala 497:65]
+                node _T_3893 = or(_T_3892, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 497:112]
+                buf_state_en[1] <= _T_3893 @[lsu_bus_buffer.scala 497:25]
+                buf_cmd_state_bus_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 498:34]
+                buf_rst[1] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 499:20]
                 skip @[Conditional.scala 39:67]
               else : @[Conditional.scala 39:67]
-                node _T_3885 = eq(UInt<3>("h06"), buf_state[1]) @[Conditional.scala 37:30]
-                when _T_3885 : @[Conditional.scala 39:67]
-                  buf_nxtstate[1] <= UInt<3>("h00") @[lsu_bus_buffer.scala 499:25]
-                  buf_rst[1] <= UInt<1>("h01") @[lsu_bus_buffer.scala 500:20]
-                  buf_state_en[1] <= UInt<1>("h01") @[lsu_bus_buffer.scala 501:25]
-                  buf_ldfwd_in[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 502:25]
-                  buf_ldfwd_en[1] <= buf_state_en[1] @[lsu_bus_buffer.scala 503:25]
-                  buf_cmd_state_bus_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 504:34]
+                node _T_3894 = eq(UInt<3>("h06"), buf_state[1]) @[Conditional.scala 37:30]
+                when _T_3894 : @[Conditional.scala 39:67]
+                  buf_nxtstate[1] <= UInt<3>("h00") @[lsu_bus_buffer.scala 502:25]
+                  buf_rst[1] <= UInt<1>("h01") @[lsu_bus_buffer.scala 503:20]
+                  buf_state_en[1] <= UInt<1>("h01") @[lsu_bus_buffer.scala 504:25]
+                  buf_ldfwd_in[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 505:25]
+                  buf_ldfwd_en[1] <= buf_state_en[1] @[lsu_bus_buffer.scala 506:25]
+                  buf_cmd_state_bus_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 507:34]
                   skip @[Conditional.scala 39:67]
-    node _T_3886 = bits(buf_state_en[1], 0, 0) @[lsu_bus_buffer.scala 507:108]
-    reg _T_3887 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when _T_3886 : @[Reg.scala 28:19]
-      _T_3887 <= buf_nxtstate[1] @[Reg.scala 28:23]
+    node _T_3895 = bits(buf_state_en[1], 0, 0) @[lsu_bus_buffer.scala 510:108]
+    reg _T_3896 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_3895 : @[Reg.scala 28:19]
+      _T_3896 <= buf_nxtstate[1] @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    buf_state[1] <= _T_3887 @[lsu_bus_buffer.scala 507:18]
-    reg _T_3888 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 508:60]
-    _T_3888 <= buf_age_in_1 @[lsu_bus_buffer.scala 508:60]
-    buf_ageQ[1] <= _T_3888 @[lsu_bus_buffer.scala 508:17]
-    reg _T_3889 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 509:63]
-    _T_3889 <= buf_rspage_in[1] @[lsu_bus_buffer.scala 509:63]
-    buf_rspageQ[1] <= _T_3889 @[lsu_bus_buffer.scala 509:20]
-    node _T_3890 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 510:109]
-    reg _T_3891 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when _T_3890 : @[Reg.scala 28:19]
-      _T_3891 <= buf_dualtag_in[1] @[Reg.scala 28:23]
-      skip @[Reg.scala 28:19]
-    buf_dualtag[1] <= _T_3891 @[lsu_bus_buffer.scala 510:20]
-    node _T_3892 = bits(buf_dual_in, 1, 1) @[lsu_bus_buffer.scala 511:74]
-    node _T_3893 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 511:107]
-    reg _T_3894 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when _T_3893 : @[Reg.scala 28:19]
-      _T_3894 <= _T_3892 @[Reg.scala 28:23]
-      skip @[Reg.scala 28:19]
-    buf_dual[1] <= _T_3894 @[lsu_bus_buffer.scala 511:17]
-    node _T_3895 = bits(buf_samedw_in, 1, 1) @[lsu_bus_buffer.scala 512:78]
-    node _T_3896 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 512:111]
-    reg _T_3897 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when _T_3896 : @[Reg.scala 28:19]
-      _T_3897 <= _T_3895 @[Reg.scala 28:23]
-      skip @[Reg.scala 28:19]
-    buf_samedw[1] <= _T_3897 @[lsu_bus_buffer.scala 512:19]
-    node _T_3898 = bits(buf_nomerge_in, 1, 1) @[lsu_bus_buffer.scala 513:80]
-    node _T_3899 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 513:113]
-    reg _T_3900 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    buf_state[1] <= _T_3896 @[lsu_bus_buffer.scala 510:18]
+    reg _T_3897 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 511:60]
+    _T_3897 <= buf_age_in_1 @[lsu_bus_buffer.scala 511:60]
+    buf_ageQ[1] <= _T_3897 @[lsu_bus_buffer.scala 511:17]
+    reg _T_3898 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 512:63]
+    _T_3898 <= buf_rspage_in[1] @[lsu_bus_buffer.scala 512:63]
+    buf_rspageQ[1] <= _T_3898 @[lsu_bus_buffer.scala 512:20]
+    node _T_3899 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 513:109]
+    reg _T_3900 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
     when _T_3899 : @[Reg.scala 28:19]
-      _T_3900 <= _T_3898 @[Reg.scala 28:23]
+      _T_3900 <= buf_dualtag_in[1] @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    buf_nomerge[1] <= _T_3900 @[lsu_bus_buffer.scala 513:20]
-    node _T_3901 = bits(buf_dualhi_in, 1, 1) @[lsu_bus_buffer.scala 514:78]
-    node _T_3902 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 514:111]
+    buf_dualtag[1] <= _T_3900 @[lsu_bus_buffer.scala 513:20]
+    node _T_3901 = bits(buf_dual_in, 1, 1) @[lsu_bus_buffer.scala 514:74]
+    node _T_3902 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 514:107]
     reg _T_3903 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
     when _T_3902 : @[Reg.scala 28:19]
       _T_3903 <= _T_3901 @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    buf_dualhi[1] <= _T_3903 @[lsu_bus_buffer.scala 514:19]
-    node _T_3904 = eq(UInt<3>("h00"), buf_state[2]) @[Conditional.scala 37:30]
-    when _T_3904 : @[Conditional.scala 40:58]
-      node _T_3905 = bits(io.lsu_bus_clk_en, 0, 0) @[lsu_bus_buffer.scala 445:56]
-      node _T_3906 = mux(_T_3905, UInt<3>("h02"), UInt<3>("h01")) @[lsu_bus_buffer.scala 445:31]
-      buf_nxtstate[2] <= _T_3906 @[lsu_bus_buffer.scala 445:25]
-      node _T_3907 = and(io.lsu_busreq_r, io.lsu_commit_r) @[lsu_bus_buffer.scala 446:45]
-      node _T_3908 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 446:77]
-      node _T_3909 = eq(ibuf_merge_en, UInt<1>("h00")) @[lsu_bus_buffer.scala 446:97]
-      node _T_3910 = and(_T_3908, _T_3909) @[lsu_bus_buffer.scala 446:95]
-      node _T_3911 = eq(UInt<2>("h02"), WrPtr0_r) @[lsu_bus_buffer.scala 446:117]
-      node _T_3912 = and(_T_3910, _T_3911) @[lsu_bus_buffer.scala 446:112]
-      node _T_3913 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 446:144]
-      node _T_3914 = eq(UInt<2>("h02"), WrPtr1_r) @[lsu_bus_buffer.scala 446:166]
-      node _T_3915 = and(_T_3913, _T_3914) @[lsu_bus_buffer.scala 446:161]
-      node _T_3916 = or(_T_3912, _T_3915) @[lsu_bus_buffer.scala 446:132]
-      node _T_3917 = and(_T_3907, _T_3916) @[lsu_bus_buffer.scala 446:63]
-      node _T_3918 = eq(UInt<2>("h02"), ibuf_tag) @[lsu_bus_buffer.scala 446:206]
-      node _T_3919 = and(ibuf_drain_vld, _T_3918) @[lsu_bus_buffer.scala 446:201]
-      node _T_3920 = or(_T_3917, _T_3919) @[lsu_bus_buffer.scala 446:183]
-      buf_state_en[2] <= _T_3920 @[lsu_bus_buffer.scala 446:25]
-      buf_wr_en[2] <= buf_state_en[2] @[lsu_bus_buffer.scala 447:22]
-      buf_data_en[2] <= buf_state_en[2] @[lsu_bus_buffer.scala 448:24]
-      node _T_3921 = eq(UInt<2>("h02"), ibuf_tag) @[lsu_bus_buffer.scala 449:52]
-      node _T_3922 = and(ibuf_drain_vld, _T_3921) @[lsu_bus_buffer.scala 449:47]
-      node _T_3923 = bits(_T_3922, 0, 0) @[lsu_bus_buffer.scala 449:73]
-      node _T_3924 = bits(ibuf_data_out, 31, 0) @[lsu_bus_buffer.scala 449:90]
-      node _T_3925 = bits(store_data_lo_r, 31, 0) @[lsu_bus_buffer.scala 449:114]
-      node _T_3926 = mux(_T_3923, _T_3924, _T_3925) @[lsu_bus_buffer.scala 449:30]
-      buf_data_in[2] <= _T_3926 @[lsu_bus_buffer.scala 449:24]
-      buf_cmd_state_bus_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 450:34]
+    buf_dual[1] <= _T_3903 @[lsu_bus_buffer.scala 514:17]
+    node _T_3904 = bits(buf_samedw_in, 1, 1) @[lsu_bus_buffer.scala 515:78]
+    node _T_3905 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 515:111]
+    reg _T_3906 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_3905 : @[Reg.scala 28:19]
+      _T_3906 <= _T_3904 @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    buf_samedw[1] <= _T_3906 @[lsu_bus_buffer.scala 515:19]
+    node _T_3907 = bits(buf_nomerge_in, 1, 1) @[lsu_bus_buffer.scala 516:80]
+    node _T_3908 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 516:113]
+    reg _T_3909 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_3908 : @[Reg.scala 28:19]
+      _T_3909 <= _T_3907 @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    buf_nomerge[1] <= _T_3909 @[lsu_bus_buffer.scala 516:20]
+    node _T_3910 = bits(buf_dualhi_in, 1, 1) @[lsu_bus_buffer.scala 517:78]
+    node _T_3911 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 517:111]
+    reg _T_3912 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_3911 : @[Reg.scala 28:19]
+      _T_3912 <= _T_3910 @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    buf_dualhi[1] <= _T_3912 @[lsu_bus_buffer.scala 517:19]
+    node _T_3913 = eq(UInt<3>("h00"), buf_state[2]) @[Conditional.scala 37:30]
+    when _T_3913 : @[Conditional.scala 40:58]
+      node _T_3914 = bits(io.lsu_bus_clk_en, 0, 0) @[lsu_bus_buffer.scala 442:56]
+      node _T_3915 = mux(_T_3914, UInt<3>("h02"), UInt<3>("h01")) @[lsu_bus_buffer.scala 442:31]
+      buf_nxtstate[2] <= _T_3915 @[lsu_bus_buffer.scala 442:25]
+      node _T_3916 = and(io.lsu_busreq_r, io.lsu_commit_r) @[lsu_bus_buffer.scala 443:45]
+      node _T_3917 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 443:77]
+      node _T_3918 = eq(ibuf_merge_en, UInt<1>("h00")) @[lsu_bus_buffer.scala 443:97]
+      node _T_3919 = and(_T_3917, _T_3918) @[lsu_bus_buffer.scala 443:95]
+      node _T_3920 = eq(UInt<2>("h02"), WrPtr0_r) @[lsu_bus_buffer.scala 443:117]
+      node _T_3921 = and(_T_3919, _T_3920) @[lsu_bus_buffer.scala 443:112]
+      node _T_3922 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 443:144]
+      node _T_3923 = eq(UInt<2>("h02"), WrPtr1_r) @[lsu_bus_buffer.scala 443:166]
+      node _T_3924 = and(_T_3922, _T_3923) @[lsu_bus_buffer.scala 443:161]
+      node _T_3925 = or(_T_3921, _T_3924) @[lsu_bus_buffer.scala 443:132]
+      node _T_3926 = and(_T_3916, _T_3925) @[lsu_bus_buffer.scala 443:63]
+      node _T_3927 = eq(UInt<2>("h02"), ibuf_tag) @[lsu_bus_buffer.scala 443:206]
+      node _T_3928 = and(ibuf_drain_vld, _T_3927) @[lsu_bus_buffer.scala 443:201]
+      node _T_3929 = or(_T_3926, _T_3928) @[lsu_bus_buffer.scala 443:183]
+      buf_state_en[2] <= _T_3929 @[lsu_bus_buffer.scala 443:25]
+      buf_wr_en[2] <= buf_state_en[2] @[lsu_bus_buffer.scala 444:22]
+      buf_data_en[2] <= buf_state_en[2] @[lsu_bus_buffer.scala 445:24]
+      node _T_3930 = eq(UInt<2>("h02"), ibuf_tag) @[lsu_bus_buffer.scala 446:52]
+      node _T_3931 = and(ibuf_drain_vld, _T_3930) @[lsu_bus_buffer.scala 446:47]
+      node _T_3932 = bits(_T_3931, 0, 0) @[lsu_bus_buffer.scala 446:73]
+      node _T_3933 = bits(ibuf_data_out, 31, 0) @[lsu_bus_buffer.scala 446:90]
+      node _T_3934 = bits(store_data_lo_r, 31, 0) @[lsu_bus_buffer.scala 446:114]
+      node _T_3935 = mux(_T_3932, _T_3933, _T_3934) @[lsu_bus_buffer.scala 446:30]
+      buf_data_in[2] <= _T_3935 @[lsu_bus_buffer.scala 446:24]
+      buf_cmd_state_bus_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 447:34]
+      buf_rst[2] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 448:21]
       skip @[Conditional.scala 40:58]
     else : @[Conditional.scala 39:67]
-      node _T_3927 = eq(UInt<3>("h01"), buf_state[2]) @[Conditional.scala 37:30]
-      when _T_3927 : @[Conditional.scala 39:67]
-        node _T_3928 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 453:60]
-        node _T_3929 = mux(_T_3928, UInt<3>("h00"), UInt<3>("h02")) @[lsu_bus_buffer.scala 453:31]
-        buf_nxtstate[2] <= _T_3929 @[lsu_bus_buffer.scala 453:25]
-        node _T_3930 = or(io.lsu_bus_clk_en, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 454:46]
-        buf_state_en[2] <= _T_3930 @[lsu_bus_buffer.scala 454:25]
-        buf_cmd_state_bus_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 455:34]
+      node _T_3936 = eq(UInt<3>("h01"), buf_state[2]) @[Conditional.scala 37:30]
+      when _T_3936 : @[Conditional.scala 39:67]
+        node _T_3937 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 451:60]
+        node _T_3938 = mux(_T_3937, UInt<3>("h00"), UInt<3>("h02")) @[lsu_bus_buffer.scala 451:31]
+        buf_nxtstate[2] <= _T_3938 @[lsu_bus_buffer.scala 451:25]
+        node _T_3939 = or(io.lsu_bus_clk_en, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 452:46]
+        buf_state_en[2] <= _T_3939 @[lsu_bus_buffer.scala 452:25]
+        buf_cmd_state_bus_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 453:34]
+        buf_rst[2] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 454:20]
         skip @[Conditional.scala 39:67]
       else : @[Conditional.scala 39:67]
-        node _T_3931 = eq(UInt<3>("h02"), buf_state[2]) @[Conditional.scala 37:30]
-        when _T_3931 : @[Conditional.scala 39:67]
-          node _T_3932 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 458:60]
-          node _T_3933 = and(obuf_nosend, bus_rsp_read) @[lsu_bus_buffer.scala 458:89]
-          node _T_3934 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[lsu_bus_buffer.scala 458:124]
-          node _T_3935 = and(_T_3933, _T_3934) @[lsu_bus_buffer.scala 458:104]
-          node _T_3936 = mux(_T_3935, UInt<3>("h05"), UInt<3>("h03")) @[lsu_bus_buffer.scala 458:75]
-          node _T_3937 = mux(_T_3932, UInt<3>("h00"), _T_3936) @[lsu_bus_buffer.scala 458:31]
-          buf_nxtstate[2] <= _T_3937 @[lsu_bus_buffer.scala 458:25]
-          node _T_3938 = eq(obuf_tag0, UInt<3>("h02")) @[lsu_bus_buffer.scala 459:48]
-          node _T_3939 = eq(obuf_tag1, UInt<3>("h02")) @[lsu_bus_buffer.scala 459:104]
-          node _T_3940 = and(obuf_merge, _T_3939) @[lsu_bus_buffer.scala 459:91]
-          node _T_3941 = or(_T_3938, _T_3940) @[lsu_bus_buffer.scala 459:77]
-          node _T_3942 = and(_T_3941, obuf_valid) @[lsu_bus_buffer.scala 459:135]
-          node _T_3943 = and(_T_3942, obuf_wr_enQ) @[lsu_bus_buffer.scala 459:148]
-          buf_cmd_state_bus_en[2] <= _T_3943 @[lsu_bus_buffer.scala 459:33]
-          buf_state_bus_en[2] <= buf_cmd_state_bus_en[2] @[lsu_bus_buffer.scala 460:29]
-          node _T_3944 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 461:49]
-          node _T_3945 = or(_T_3944, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 461:70]
-          buf_state_en[2] <= _T_3945 @[lsu_bus_buffer.scala 461:25]
-          buf_ldfwd_in[2] <= UInt<1>("h01") @[lsu_bus_buffer.scala 462:25]
-          node _T_3946 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 463:56]
-          node _T_3947 = eq(_T_3946, UInt<1>("h00")) @[lsu_bus_buffer.scala 463:46]
-          node _T_3948 = and(buf_state_en[2], _T_3947) @[lsu_bus_buffer.scala 463:44]
-          node _T_3949 = and(_T_3948, obuf_nosend) @[lsu_bus_buffer.scala 463:60]
-          node _T_3950 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 463:76]
-          node _T_3951 = and(_T_3949, _T_3950) @[lsu_bus_buffer.scala 463:74]
-          buf_ldfwd_en[2] <= _T_3951 @[lsu_bus_buffer.scala 463:25]
-          node _T_3952 = bits(obuf_rdrsp_tag, 1, 0) @[lsu_bus_buffer.scala 464:46]
-          buf_ldfwdtag_in[2] <= _T_3952 @[lsu_bus_buffer.scala 464:28]
-          node _T_3953 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 465:47]
-          node _T_3954 = and(_T_3953, obuf_nosend) @[lsu_bus_buffer.scala 465:67]
-          node _T_3955 = and(_T_3954, bus_rsp_read) @[lsu_bus_buffer.scala 465:81]
-          buf_data_en[2] <= _T_3955 @[lsu_bus_buffer.scala 465:24]
-          node _T_3956 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 466:48]
-          node _T_3957 = and(_T_3956, obuf_nosend) @[lsu_bus_buffer.scala 466:68]
-          node _T_3958 = and(_T_3957, bus_rsp_read_error) @[lsu_bus_buffer.scala 466:82]
-          buf_error_en[2] <= _T_3958 @[lsu_bus_buffer.scala 466:25]
-          node _T_3959 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 467:61]
-          node _T_3960 = bits(buf_addr[2], 2, 2) @[lsu_bus_buffer.scala 467:85]
-          node _T_3961 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 467:103]
-          node _T_3962 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 467:126]
-          node _T_3963 = mux(_T_3960, _T_3961, _T_3962) @[lsu_bus_buffer.scala 467:73]
-          node _T_3964 = mux(buf_error_en[2], _T_3959, _T_3963) @[lsu_bus_buffer.scala 467:30]
-          buf_data_in[2] <= _T_3964 @[lsu_bus_buffer.scala 467:24]
+        node _T_3940 = eq(UInt<3>("h02"), buf_state[2]) @[Conditional.scala 37:30]
+        when _T_3940 : @[Conditional.scala 39:67]
+          node _T_3941 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 457:60]
+          node _T_3942 = and(obuf_nosend, bus_rsp_read) @[lsu_bus_buffer.scala 457:89]
+          node _T_3943 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[lsu_bus_buffer.scala 457:124]
+          node _T_3944 = and(_T_3942, _T_3943) @[lsu_bus_buffer.scala 457:104]
+          node _T_3945 = mux(_T_3944, UInt<3>("h05"), UInt<3>("h03")) @[lsu_bus_buffer.scala 457:75]
+          node _T_3946 = mux(_T_3941, UInt<3>("h00"), _T_3945) @[lsu_bus_buffer.scala 457:31]
+          buf_nxtstate[2] <= _T_3946 @[lsu_bus_buffer.scala 457:25]
+          node _T_3947 = eq(obuf_tag0, UInt<3>("h02")) @[lsu_bus_buffer.scala 458:48]
+          node _T_3948 = eq(obuf_tag1, UInt<3>("h02")) @[lsu_bus_buffer.scala 458:104]
+          node _T_3949 = and(obuf_merge, _T_3948) @[lsu_bus_buffer.scala 458:91]
+          node _T_3950 = or(_T_3947, _T_3949) @[lsu_bus_buffer.scala 458:77]
+          node _T_3951 = and(_T_3950, obuf_valid) @[lsu_bus_buffer.scala 458:135]
+          node _T_3952 = and(_T_3951, obuf_wr_enQ) @[lsu_bus_buffer.scala 458:148]
+          buf_cmd_state_bus_en[2] <= _T_3952 @[lsu_bus_buffer.scala 458:33]
+          buf_state_bus_en[2] <= buf_cmd_state_bus_en[2] @[lsu_bus_buffer.scala 459:29]
+          node _T_3953 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 460:49]
+          node _T_3954 = or(_T_3953, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 460:70]
+          buf_state_en[2] <= _T_3954 @[lsu_bus_buffer.scala 460:25]
+          buf_ldfwd_in[2] <= UInt<1>("h01") @[lsu_bus_buffer.scala 461:25]
+          node _T_3955 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 462:56]
+          node _T_3956 = eq(_T_3955, UInt<1>("h00")) @[lsu_bus_buffer.scala 462:46]
+          node _T_3957 = and(buf_state_en[2], _T_3956) @[lsu_bus_buffer.scala 462:44]
+          node _T_3958 = and(_T_3957, obuf_nosend) @[lsu_bus_buffer.scala 462:60]
+          node _T_3959 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 462:76]
+          node _T_3960 = and(_T_3958, _T_3959) @[lsu_bus_buffer.scala 462:74]
+          buf_ldfwd_en[2] <= _T_3960 @[lsu_bus_buffer.scala 462:25]
+          node _T_3961 = bits(obuf_rdrsp_tag, 1, 0) @[lsu_bus_buffer.scala 463:46]
+          buf_ldfwdtag_in[2] <= _T_3961 @[lsu_bus_buffer.scala 463:28]
+          node _T_3962 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 464:47]
+          node _T_3963 = and(_T_3962, obuf_nosend) @[lsu_bus_buffer.scala 464:67]
+          node _T_3964 = and(_T_3963, bus_rsp_read) @[lsu_bus_buffer.scala 464:81]
+          buf_data_en[2] <= _T_3964 @[lsu_bus_buffer.scala 464:24]
+          node _T_3965 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 465:48]
+          node _T_3966 = and(_T_3965, obuf_nosend) @[lsu_bus_buffer.scala 465:68]
+          node _T_3967 = and(_T_3966, bus_rsp_read_error) @[lsu_bus_buffer.scala 465:82]
+          buf_error_en[2] <= _T_3967 @[lsu_bus_buffer.scala 465:25]
+          node _T_3968 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 466:61]
+          node _T_3969 = bits(buf_addr[2], 2, 2) @[lsu_bus_buffer.scala 466:85]
+          node _T_3970 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 466:103]
+          node _T_3971 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 466:126]
+          node _T_3972 = mux(_T_3969, _T_3970, _T_3971) @[lsu_bus_buffer.scala 466:73]
+          node _T_3973 = mux(buf_error_en[2], _T_3968, _T_3972) @[lsu_bus_buffer.scala 466:30]
+          buf_data_in[2] <= _T_3973 @[lsu_bus_buffer.scala 466:24]
+          buf_rst[2] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 467:20]
           skip @[Conditional.scala 39:67]
         else : @[Conditional.scala 39:67]
-          node _T_3965 = eq(UInt<3>("h03"), buf_state[2]) @[Conditional.scala 37:30]
-          when _T_3965 : @[Conditional.scala 39:67]
-            node _T_3966 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 470:67]
-            node _T_3967 = and(_T_3966, bus_rsp_write_error) @[lsu_bus_buffer.scala 470:71]
-            node _T_3968 = or(io.dec_tlu_force_halt, _T_3967) @[lsu_bus_buffer.scala 470:55]
-            node _T_3969 = bits(_T_3968, 0, 0) @[lsu_bus_buffer.scala 470:101]
-            node _T_3970 = eq(buf_samedw[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 471:30]
-            node _T_3971 = and(buf_dual[2], _T_3970) @[lsu_bus_buffer.scala 471:28]
-            node _T_3972 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 471:57]
-            node _T_3973 = eq(_T_3972, UInt<1>("h00")) @[lsu_bus_buffer.scala 471:47]
-            node _T_3974 = and(_T_3971, _T_3973) @[lsu_bus_buffer.scala 471:45]
-            node _T_3975 = neq(buf_state[buf_dualtag[2]], UInt<3>("h04")) @[lsu_bus_buffer.scala 471:90]
-            node _T_3976 = and(_T_3974, _T_3975) @[lsu_bus_buffer.scala 471:61]
-            node _T_3977 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 472:27]
-            node _T_3978 = or(_T_3977, any_done_wait_state) @[lsu_bus_buffer.scala 472:31]
-            node _T_3979 = eq(buf_samedw[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 472:70]
-            node _T_3980 = and(buf_dual[2], _T_3979) @[lsu_bus_buffer.scala 472:68]
-            node _T_3981 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 472:97]
-            node _T_3982 = eq(_T_3981, UInt<1>("h00")) @[lsu_bus_buffer.scala 472:87]
-            node _T_3983 = and(_T_3980, _T_3982) @[lsu_bus_buffer.scala 472:85]
-            node _T_3984 = eq(buf_dualtag[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 60:118]
-            node _T_3985 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 60:129]
-            node _T_3986 = eq(buf_dualtag[2], UInt<1>("h01")) @[lsu_bus_buffer.scala 60:118]
-            node _T_3987 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 60:129]
-            node _T_3988 = eq(buf_dualtag[2], UInt<2>("h02")) @[lsu_bus_buffer.scala 60:118]
-            node _T_3989 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 60:129]
-            node _T_3990 = eq(buf_dualtag[2], UInt<2>("h03")) @[lsu_bus_buffer.scala 60:118]
-            node _T_3991 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 60:129]
-            node _T_3992 = mux(_T_3984, _T_3985, UInt<1>("h00")) @[Mux.scala 27:72]
-            node _T_3993 = mux(_T_3986, _T_3987, UInt<1>("h00")) @[Mux.scala 27:72]
-            node _T_3994 = mux(_T_3988, _T_3989, UInt<1>("h00")) @[Mux.scala 27:72]
-            node _T_3995 = mux(_T_3990, _T_3991, UInt<1>("h00")) @[Mux.scala 27:72]
-            node _T_3996 = or(_T_3992, _T_3993) @[Mux.scala 27:72]
-            node _T_3997 = or(_T_3996, _T_3994) @[Mux.scala 27:72]
-            node _T_3998 = or(_T_3997, _T_3995) @[Mux.scala 27:72]
-            wire _T_3999 : UInt<1> @[Mux.scala 27:72]
-            _T_3999 <= _T_3998 @[Mux.scala 27:72]
-            node _T_4000 = and(_T_3983, _T_3999) @[lsu_bus_buffer.scala 472:101]
-            node _T_4001 = eq(buf_state[buf_dualtag[2]], UInt<3>("h04")) @[lsu_bus_buffer.scala 472:167]
-            node _T_4002 = and(_T_4000, _T_4001) @[lsu_bus_buffer.scala 472:138]
-            node _T_4003 = and(_T_4002, any_done_wait_state) @[lsu_bus_buffer.scala 472:187]
-            node _T_4004 = or(_T_3978, _T_4003) @[lsu_bus_buffer.scala 472:53]
-            node _T_4005 = mux(_T_4004, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 472:16]
-            node _T_4006 = mux(_T_3976, UInt<3>("h04"), _T_4005) @[lsu_bus_buffer.scala 471:14]
-            node _T_4007 = mux(_T_3969, UInt<3>("h00"), _T_4006) @[lsu_bus_buffer.scala 470:31]
-            buf_nxtstate[2] <= _T_4007 @[lsu_bus_buffer.scala 470:25]
-            node _T_4008 = eq(bus_rsp_write_tag, UInt<3>("h02")) @[lsu_bus_buffer.scala 473:73]
-            node _T_4009 = and(bus_rsp_write, _T_4008) @[lsu_bus_buffer.scala 473:52]
-            node _T_4010 = eq(bus_rsp_read_tag, UInt<3>("h02")) @[lsu_bus_buffer.scala 474:46]
-            node _T_4011 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 475:23]
-            node _T_4012 = eq(bus_rsp_read_tag, buf_ldfwdtag[2]) @[lsu_bus_buffer.scala 475:47]
-            node _T_4013 = and(_T_4011, _T_4012) @[lsu_bus_buffer.scala 475:27]
-            node _T_4014 = or(_T_4010, _T_4013) @[lsu_bus_buffer.scala 474:77]
-            node _T_4015 = and(buf_dual[2], buf_dualhi[2]) @[lsu_bus_buffer.scala 476:26]
-            node _T_4016 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 476:54]
-            node _T_4017 = not(_T_4016) @[lsu_bus_buffer.scala 476:44]
-            node _T_4018 = and(_T_4015, _T_4017) @[lsu_bus_buffer.scala 476:42]
-            node _T_4019 = and(_T_4018, buf_samedw[2]) @[lsu_bus_buffer.scala 476:58]
-            node _T_4020 = eq(bus_rsp_read_tag, buf_dualtag[2]) @[lsu_bus_buffer.scala 476:94]
-            node _T_4021 = and(_T_4019, _T_4020) @[lsu_bus_buffer.scala 476:74]
-            node _T_4022 = or(_T_4014, _T_4021) @[lsu_bus_buffer.scala 475:71]
-            node _T_4023 = and(bus_rsp_read, _T_4022) @[lsu_bus_buffer.scala 474:25]
-            node _T_4024 = or(_T_4009, _T_4023) @[lsu_bus_buffer.scala 473:105]
-            buf_resp_state_bus_en[2] <= _T_4024 @[lsu_bus_buffer.scala 473:34]
+          node _T_3974 = eq(UInt<3>("h03"), buf_state[2]) @[Conditional.scala 37:30]
+          when _T_3974 : @[Conditional.scala 39:67]
+            node _T_3975 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 470:69]
+            node _T_3976 = eq(bus_rsp_write_error, UInt<1>("h00")) @[lsu_bus_buffer.scala 470:75]
+            node _T_3977 = and(_T_3975, _T_3976) @[lsu_bus_buffer.scala 470:73]
+            node _T_3978 = or(io.dec_tlu_force_halt, _T_3977) @[lsu_bus_buffer.scala 470:57]
+            node _T_3979 = bits(_T_3978, 0, 0) @[lsu_bus_buffer.scala 470:104]
+            node _T_3980 = eq(buf_samedw[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 471:30]
+            node _T_3981 = and(buf_dual[2], _T_3980) @[lsu_bus_buffer.scala 471:28]
+            node _T_3982 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 471:57]
+            node _T_3983 = eq(_T_3982, UInt<1>("h00")) @[lsu_bus_buffer.scala 471:47]
+            node _T_3984 = and(_T_3981, _T_3983) @[lsu_bus_buffer.scala 471:45]
+            node _T_3985 = neq(buf_state[buf_dualtag[2]], UInt<3>("h04")) @[lsu_bus_buffer.scala 471:90]
+            node _T_3986 = and(_T_3984, _T_3985) @[lsu_bus_buffer.scala 471:61]
+            node _T_3987 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 472:27]
+            node _T_3988 = or(_T_3987, any_done_wait_state) @[lsu_bus_buffer.scala 472:31]
+            node _T_3989 = eq(buf_samedw[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 472:70]
+            node _T_3990 = and(buf_dual[2], _T_3989) @[lsu_bus_buffer.scala 472:68]
+            node _T_3991 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 472:97]
+            node _T_3992 = eq(_T_3991, UInt<1>("h00")) @[lsu_bus_buffer.scala 472:87]
+            node _T_3993 = and(_T_3990, _T_3992) @[lsu_bus_buffer.scala 472:85]
+            node _T_3994 = eq(buf_dualtag[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 60:118]
+            node _T_3995 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 60:129]
+            node _T_3996 = eq(buf_dualtag[2], UInt<1>("h01")) @[lsu_bus_buffer.scala 60:118]
+            node _T_3997 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 60:129]
+            node _T_3998 = eq(buf_dualtag[2], UInt<2>("h02")) @[lsu_bus_buffer.scala 60:118]
+            node _T_3999 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 60:129]
+            node _T_4000 = eq(buf_dualtag[2], UInt<2>("h03")) @[lsu_bus_buffer.scala 60:118]
+            node _T_4001 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 60:129]
+            node _T_4002 = mux(_T_3994, _T_3995, UInt<1>("h00")) @[Mux.scala 27:72]
+            node _T_4003 = mux(_T_3996, _T_3997, UInt<1>("h00")) @[Mux.scala 27:72]
+            node _T_4004 = mux(_T_3998, _T_3999, UInt<1>("h00")) @[Mux.scala 27:72]
+            node _T_4005 = mux(_T_4000, _T_4001, UInt<1>("h00")) @[Mux.scala 27:72]
+            node _T_4006 = or(_T_4002, _T_4003) @[Mux.scala 27:72]
+            node _T_4007 = or(_T_4006, _T_4004) @[Mux.scala 27:72]
+            node _T_4008 = or(_T_4007, _T_4005) @[Mux.scala 27:72]
+            wire _T_4009 : UInt<1> @[Mux.scala 27:72]
+            _T_4009 <= _T_4008 @[Mux.scala 27:72]
+            node _T_4010 = and(_T_3993, _T_4009) @[lsu_bus_buffer.scala 472:101]
+            node _T_4011 = eq(buf_state[buf_dualtag[2]], UInt<3>("h04")) @[lsu_bus_buffer.scala 472:167]
+            node _T_4012 = and(_T_4010, _T_4011) @[lsu_bus_buffer.scala 472:138]
+            node _T_4013 = and(_T_4012, any_done_wait_state) @[lsu_bus_buffer.scala 472:187]
+            node _T_4014 = or(_T_3988, _T_4013) @[lsu_bus_buffer.scala 472:53]
+            node _T_4015 = mux(_T_4014, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 472:16]
+            node _T_4016 = mux(_T_3986, UInt<3>("h04"), _T_4015) @[lsu_bus_buffer.scala 471:14]
+            node _T_4017 = mux(_T_3979, UInt<3>("h00"), _T_4016) @[lsu_bus_buffer.scala 470:33]
+            buf_nxtstate[2] <= _T_4017 @[lsu_bus_buffer.scala 470:27]
+            node _T_4018 = eq(bus_rsp_write_tag, UInt<3>("h02")) @[lsu_bus_buffer.scala 473:73]
+            node _T_4019 = and(bus_rsp_write, _T_4018) @[lsu_bus_buffer.scala 473:52]
+            node _T_4020 = eq(bus_rsp_read_tag, UInt<3>("h02")) @[lsu_bus_buffer.scala 474:46]
+            node _T_4021 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 475:23]
+            node _T_4022 = eq(bus_rsp_read_tag, buf_ldfwdtag[2]) @[lsu_bus_buffer.scala 475:47]
+            node _T_4023 = and(_T_4021, _T_4022) @[lsu_bus_buffer.scala 475:27]
+            node _T_4024 = or(_T_4020, _T_4023) @[lsu_bus_buffer.scala 474:77]
+            node _T_4025 = and(buf_dual[2], buf_dualhi[2]) @[lsu_bus_buffer.scala 476:26]
+            node _T_4026 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 476:54]
+            node _T_4027 = not(_T_4026) @[lsu_bus_buffer.scala 476:44]
+            node _T_4028 = and(_T_4025, _T_4027) @[lsu_bus_buffer.scala 476:42]
+            node _T_4029 = and(_T_4028, buf_samedw[2]) @[lsu_bus_buffer.scala 476:58]
+            node _T_4030 = eq(bus_rsp_read_tag, buf_dualtag[2]) @[lsu_bus_buffer.scala 476:94]
+            node _T_4031 = and(_T_4029, _T_4030) @[lsu_bus_buffer.scala 476:74]
+            node _T_4032 = or(_T_4024, _T_4031) @[lsu_bus_buffer.scala 475:71]
+            node _T_4033 = and(bus_rsp_read, _T_4032) @[lsu_bus_buffer.scala 474:25]
+            node _T_4034 = or(_T_4019, _T_4033) @[lsu_bus_buffer.scala 473:105]
+            buf_resp_state_bus_en[2] <= _T_4034 @[lsu_bus_buffer.scala 473:34]
             buf_state_bus_en[2] <= buf_resp_state_bus_en[2] @[lsu_bus_buffer.scala 477:29]
-            node _T_4025 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 478:49]
-            node _T_4026 = or(_T_4025, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 478:70]
-            buf_state_en[2] <= _T_4026 @[lsu_bus_buffer.scala 478:25]
-            node _T_4027 = and(buf_state_bus_en[2], bus_rsp_read) @[lsu_bus_buffer.scala 479:47]
-            node _T_4028 = and(_T_4027, io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 479:62]
-            buf_data_en[2] <= _T_4028 @[lsu_bus_buffer.scala 479:24]
-            node _T_4029 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 480:48]
-            node _T_4030 = eq(bus_rsp_read_tag, UInt<3>("h02")) @[lsu_bus_buffer.scala 480:111]
-            node _T_4031 = and(bus_rsp_read_error, _T_4030) @[lsu_bus_buffer.scala 480:91]
-            node _T_4032 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 481:42]
-            node _T_4033 = and(bus_rsp_read_error, _T_4032) @[lsu_bus_buffer.scala 481:31]
-            node _T_4034 = eq(bus_rsp_read_tag, buf_ldfwdtag[2]) @[lsu_bus_buffer.scala 481:66]
-            node _T_4035 = and(_T_4033, _T_4034) @[lsu_bus_buffer.scala 481:46]
-            node _T_4036 = or(_T_4031, _T_4035) @[lsu_bus_buffer.scala 480:143]
-            node _T_4037 = eq(bus_rsp_write_tag, UInt<3>("h02")) @[lsu_bus_buffer.scala 482:54]
-            node _T_4038 = and(bus_rsp_write_error, _T_4037) @[lsu_bus_buffer.scala 482:33]
-            node _T_4039 = or(_T_4036, _T_4038) @[lsu_bus_buffer.scala 481:88]
-            node _T_4040 = and(_T_4029, _T_4039) @[lsu_bus_buffer.scala 480:68]
-            buf_error_en[2] <= _T_4040 @[lsu_bus_buffer.scala 480:25]
-            node _T_4041 = eq(buf_error_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 483:50]
-            node _T_4042 = and(buf_state_en[2], _T_4041) @[lsu_bus_buffer.scala 483:48]
-            node _T_4043 = bits(buf_addr[2], 2, 2) @[lsu_bus_buffer.scala 483:84]
-            node _T_4044 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 483:102]
-            node _T_4045 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 483:125]
-            node _T_4046 = mux(_T_4043, _T_4044, _T_4045) @[lsu_bus_buffer.scala 483:72]
-            node _T_4047 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 483:148]
-            node _T_4048 = mux(_T_4042, _T_4046, _T_4047) @[lsu_bus_buffer.scala 483:30]
-            buf_data_in[2] <= _T_4048 @[lsu_bus_buffer.scala 483:24]
+            node _T_4035 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 478:49]
+            node _T_4036 = or(_T_4035, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 478:70]
+            buf_state_en[2] <= _T_4036 @[lsu_bus_buffer.scala 478:25]
+            node _T_4037 = and(buf_state_bus_en[2], bus_rsp_read) @[lsu_bus_buffer.scala 479:47]
+            node _T_4038 = and(_T_4037, io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 479:62]
+            buf_data_en[2] <= _T_4038 @[lsu_bus_buffer.scala 479:24]
+            node _T_4039 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 480:48]
+            node _T_4040 = eq(bus_rsp_read_tag, UInt<3>("h02")) @[lsu_bus_buffer.scala 480:111]
+            node _T_4041 = and(bus_rsp_read_error, _T_4040) @[lsu_bus_buffer.scala 480:91]
+            node _T_4042 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 481:42]
+            node _T_4043 = and(bus_rsp_read_error, _T_4042) @[lsu_bus_buffer.scala 481:31]
+            node _T_4044 = eq(bus_rsp_read_tag, buf_ldfwdtag[2]) @[lsu_bus_buffer.scala 481:66]
+            node _T_4045 = and(_T_4043, _T_4044) @[lsu_bus_buffer.scala 481:46]
+            node _T_4046 = or(_T_4041, _T_4045) @[lsu_bus_buffer.scala 480:143]
+            node _T_4047 = eq(bus_rsp_write_tag, UInt<3>("h02")) @[lsu_bus_buffer.scala 482:54]
+            node _T_4048 = and(bus_rsp_write_error, _T_4047) @[lsu_bus_buffer.scala 482:33]
+            node _T_4049 = or(_T_4046, _T_4048) @[lsu_bus_buffer.scala 481:88]
+            node _T_4050 = and(_T_4039, _T_4049) @[lsu_bus_buffer.scala 480:68]
+            buf_error_en[2] <= _T_4050 @[lsu_bus_buffer.scala 480:25]
+            node _T_4051 = eq(buf_error_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 483:50]
+            node _T_4052 = and(buf_state_en[2], _T_4051) @[lsu_bus_buffer.scala 483:48]
+            node _T_4053 = bits(buf_addr[2], 2, 2) @[lsu_bus_buffer.scala 483:84]
+            node _T_4054 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 483:102]
+            node _T_4055 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 483:125]
+            node _T_4056 = mux(_T_4053, _T_4054, _T_4055) @[lsu_bus_buffer.scala 483:72]
+            node _T_4057 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 483:148]
+            node _T_4058 = mux(_T_4052, _T_4056, _T_4057) @[lsu_bus_buffer.scala 483:30]
+            buf_data_in[2] <= _T_4058 @[lsu_bus_buffer.scala 483:24]
             buf_cmd_state_bus_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 484:34]
+            buf_rst[2] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 485:20]
             skip @[Conditional.scala 39:67]
           else : @[Conditional.scala 39:67]
-            node _T_4049 = eq(UInt<3>("h04"), buf_state[2]) @[Conditional.scala 37:30]
-            when _T_4049 : @[Conditional.scala 39:67]
-              node _T_4050 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 487:60]
-              node _T_4051 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 487:86]
-              node _T_4052 = dshr(buf_ldfwd, buf_dualtag[2]) @[lsu_bus_buffer.scala 487:101]
-              node _T_4053 = bits(_T_4052, 0, 0) @[lsu_bus_buffer.scala 487:101]
-              node _T_4054 = or(_T_4051, _T_4053) @[lsu_bus_buffer.scala 487:90]
-              node _T_4055 = or(_T_4054, any_done_wait_state) @[lsu_bus_buffer.scala 487:118]
-              node _T_4056 = mux(_T_4055, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 487:75]
-              node _T_4057 = mux(_T_4050, UInt<3>("h00"), _T_4056) @[lsu_bus_buffer.scala 487:31]
-              buf_nxtstate[2] <= _T_4057 @[lsu_bus_buffer.scala 487:25]
-              node _T_4058 = eq(bus_rsp_read_tag, buf_dualtag[2]) @[lsu_bus_buffer.scala 488:66]
-              node _T_4059 = dshr(buf_ldfwd, buf_dualtag[2]) @[lsu_bus_buffer.scala 489:21]
-              node _T_4060 = bits(_T_4059, 0, 0) @[lsu_bus_buffer.scala 489:21]
-              node _T_4061 = eq(bus_rsp_read_tag, buf_ldfwdtag[buf_dualtag[2]]) @[lsu_bus_buffer.scala 489:58]
-              node _T_4062 = and(_T_4060, _T_4061) @[lsu_bus_buffer.scala 489:38]
-              node _T_4063 = or(_T_4058, _T_4062) @[lsu_bus_buffer.scala 488:95]
-              node _T_4064 = and(bus_rsp_read, _T_4063) @[lsu_bus_buffer.scala 488:45]
-              buf_state_bus_en[2] <= _T_4064 @[lsu_bus_buffer.scala 488:29]
-              node _T_4065 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 490:49]
-              node _T_4066 = or(_T_4065, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 490:70]
-              buf_state_en[2] <= _T_4066 @[lsu_bus_buffer.scala 490:25]
-              buf_cmd_state_bus_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 491:34]
+            node _T_4059 = eq(UInt<3>("h04"), buf_state[2]) @[Conditional.scala 37:30]
+            when _T_4059 : @[Conditional.scala 39:67]
+              node _T_4060 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 488:60]
+              node _T_4061 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 488:86]
+              node _T_4062 = dshr(buf_ldfwd, buf_dualtag[2]) @[lsu_bus_buffer.scala 488:101]
+              node _T_4063 = bits(_T_4062, 0, 0) @[lsu_bus_buffer.scala 488:101]
+              node _T_4064 = or(_T_4061, _T_4063) @[lsu_bus_buffer.scala 488:90]
+              node _T_4065 = or(_T_4064, any_done_wait_state) @[lsu_bus_buffer.scala 488:118]
+              node _T_4066 = mux(_T_4065, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 488:75]
+              node _T_4067 = mux(_T_4060, UInt<3>("h00"), _T_4066) @[lsu_bus_buffer.scala 488:31]
+              buf_nxtstate[2] <= _T_4067 @[lsu_bus_buffer.scala 488:25]
+              node _T_4068 = eq(bus_rsp_read_tag, buf_dualtag[2]) @[lsu_bus_buffer.scala 489:66]
+              node _T_4069 = dshr(buf_ldfwd, buf_dualtag[2]) @[lsu_bus_buffer.scala 490:21]
+              node _T_4070 = bits(_T_4069, 0, 0) @[lsu_bus_buffer.scala 490:21]
+              node _T_4071 = eq(bus_rsp_read_tag, buf_ldfwdtag[buf_dualtag[2]]) @[lsu_bus_buffer.scala 490:58]
+              node _T_4072 = and(_T_4070, _T_4071) @[lsu_bus_buffer.scala 490:38]
+              node _T_4073 = or(_T_4068, _T_4072) @[lsu_bus_buffer.scala 489:95]
+              node _T_4074 = and(bus_rsp_read, _T_4073) @[lsu_bus_buffer.scala 489:45]
+              buf_state_bus_en[2] <= _T_4074 @[lsu_bus_buffer.scala 489:29]
+              node _T_4075 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 491:49]
+              node _T_4076 = or(_T_4075, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 491:70]
+              buf_state_en[2] <= _T_4076 @[lsu_bus_buffer.scala 491:25]
+              buf_cmd_state_bus_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 492:34]
+              buf_rst[2] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 493:20]
               skip @[Conditional.scala 39:67]
             else : @[Conditional.scala 39:67]
-              node _T_4067 = eq(UInt<3>("h05"), buf_state[2]) @[Conditional.scala 37:30]
-              when _T_4067 : @[Conditional.scala 39:67]
-                node _T_4068 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 494:60]
-                node _T_4069 = mux(_T_4068, UInt<3>("h00"), UInt<3>("h06")) @[lsu_bus_buffer.scala 494:31]
-                buf_nxtstate[2] <= _T_4069 @[lsu_bus_buffer.scala 494:25]
-                node _T_4070 = eq(RspPtr, UInt<2>("h02")) @[lsu_bus_buffer.scala 495:37]
-                node _T_4071 = eq(buf_dualtag[2], RspPtr) @[lsu_bus_buffer.scala 495:98]
-                node _T_4072 = and(buf_dual[2], _T_4071) @[lsu_bus_buffer.scala 495:80]
-                node _T_4073 = or(_T_4070, _T_4072) @[lsu_bus_buffer.scala 495:65]
-                node _T_4074 = or(_T_4073, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 495:112]
-                buf_state_en[2] <= _T_4074 @[lsu_bus_buffer.scala 495:25]
-                buf_cmd_state_bus_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 496:34]
+              node _T_4077 = eq(UInt<3>("h05"), buf_state[2]) @[Conditional.scala 37:30]
+              when _T_4077 : @[Conditional.scala 39:67]
+                node _T_4078 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 496:60]
+                node _T_4079 = mux(_T_4078, UInt<3>("h00"), UInt<3>("h06")) @[lsu_bus_buffer.scala 496:31]
+                buf_nxtstate[2] <= _T_4079 @[lsu_bus_buffer.scala 496:25]
+                node _T_4080 = eq(RspPtr, UInt<2>("h02")) @[lsu_bus_buffer.scala 497:37]
+                node _T_4081 = eq(buf_dualtag[2], RspPtr) @[lsu_bus_buffer.scala 497:98]
+                node _T_4082 = and(buf_dual[2], _T_4081) @[lsu_bus_buffer.scala 497:80]
+                node _T_4083 = or(_T_4080, _T_4082) @[lsu_bus_buffer.scala 497:65]
+                node _T_4084 = or(_T_4083, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 497:112]
+                buf_state_en[2] <= _T_4084 @[lsu_bus_buffer.scala 497:25]
+                buf_cmd_state_bus_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 498:34]
+                buf_rst[2] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 499:20]
                 skip @[Conditional.scala 39:67]
               else : @[Conditional.scala 39:67]
-                node _T_4075 = eq(UInt<3>("h06"), buf_state[2]) @[Conditional.scala 37:30]
-                when _T_4075 : @[Conditional.scala 39:67]
-                  buf_nxtstate[2] <= UInt<3>("h00") @[lsu_bus_buffer.scala 499:25]
-                  buf_rst[2] <= UInt<1>("h01") @[lsu_bus_buffer.scala 500:20]
-                  buf_state_en[2] <= UInt<1>("h01") @[lsu_bus_buffer.scala 501:25]
-                  buf_ldfwd_in[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 502:25]
-                  buf_ldfwd_en[2] <= buf_state_en[2] @[lsu_bus_buffer.scala 503:25]
-                  buf_cmd_state_bus_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 504:34]
+                node _T_4085 = eq(UInt<3>("h06"), buf_state[2]) @[Conditional.scala 37:30]
+                when _T_4085 : @[Conditional.scala 39:67]
+                  buf_nxtstate[2] <= UInt<3>("h00") @[lsu_bus_buffer.scala 502:25]
+                  buf_rst[2] <= UInt<1>("h01") @[lsu_bus_buffer.scala 503:20]
+                  buf_state_en[2] <= UInt<1>("h01") @[lsu_bus_buffer.scala 504:25]
+                  buf_ldfwd_in[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 505:25]
+                  buf_ldfwd_en[2] <= buf_state_en[2] @[lsu_bus_buffer.scala 506:25]
+                  buf_cmd_state_bus_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 507:34]
                   skip @[Conditional.scala 39:67]
-    node _T_4076 = bits(buf_state_en[2], 0, 0) @[lsu_bus_buffer.scala 507:108]
-    reg _T_4077 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when _T_4076 : @[Reg.scala 28:19]
-      _T_4077 <= buf_nxtstate[2] @[Reg.scala 28:23]
-      skip @[Reg.scala 28:19]
-    buf_state[2] <= _T_4077 @[lsu_bus_buffer.scala 507:18]
-    reg _T_4078 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 508:60]
-    _T_4078 <= buf_age_in_2 @[lsu_bus_buffer.scala 508:60]
-    buf_ageQ[2] <= _T_4078 @[lsu_bus_buffer.scala 508:17]
-    reg _T_4079 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 509:63]
-    _T_4079 <= buf_rspage_in[2] @[lsu_bus_buffer.scala 509:63]
-    buf_rspageQ[2] <= _T_4079 @[lsu_bus_buffer.scala 509:20]
-    node _T_4080 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 510:109]
-    reg _T_4081 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when _T_4080 : @[Reg.scala 28:19]
-      _T_4081 <= buf_dualtag_in[2] @[Reg.scala 28:23]
-      skip @[Reg.scala 28:19]
-    buf_dualtag[2] <= _T_4081 @[lsu_bus_buffer.scala 510:20]
-    node _T_4082 = bits(buf_dual_in, 2, 2) @[lsu_bus_buffer.scala 511:74]
-    node _T_4083 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 511:107]
-    reg _T_4084 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when _T_4083 : @[Reg.scala 28:19]
-      _T_4084 <= _T_4082 @[Reg.scala 28:23]
-      skip @[Reg.scala 28:19]
-    buf_dual[2] <= _T_4084 @[lsu_bus_buffer.scala 511:17]
-    node _T_4085 = bits(buf_samedw_in, 2, 2) @[lsu_bus_buffer.scala 512:78]
-    node _T_4086 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 512:111]
-    reg _T_4087 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    node _T_4086 = bits(buf_state_en[2], 0, 0) @[lsu_bus_buffer.scala 510:108]
+    reg _T_4087 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
     when _T_4086 : @[Reg.scala 28:19]
-      _T_4087 <= _T_4085 @[Reg.scala 28:23]
+      _T_4087 <= buf_nxtstate[2] @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    buf_samedw[2] <= _T_4087 @[lsu_bus_buffer.scala 512:19]
-    node _T_4088 = bits(buf_nomerge_in, 2, 2) @[lsu_bus_buffer.scala 513:80]
-    node _T_4089 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 513:113]
-    reg _T_4090 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when _T_4089 : @[Reg.scala 28:19]
-      _T_4090 <= _T_4088 @[Reg.scala 28:23]
+    buf_state[2] <= _T_4087 @[lsu_bus_buffer.scala 510:18]
+    reg _T_4088 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 511:60]
+    _T_4088 <= buf_age_in_2 @[lsu_bus_buffer.scala 511:60]
+    buf_ageQ[2] <= _T_4088 @[lsu_bus_buffer.scala 511:17]
+    reg _T_4089 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 512:63]
+    _T_4089 <= buf_rspage_in[2] @[lsu_bus_buffer.scala 512:63]
+    buf_rspageQ[2] <= _T_4089 @[lsu_bus_buffer.scala 512:20]
+    node _T_4090 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 513:109]
+    reg _T_4091 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4090 : @[Reg.scala 28:19]
+      _T_4091 <= buf_dualtag_in[2] @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    buf_nomerge[2] <= _T_4090 @[lsu_bus_buffer.scala 513:20]
-    node _T_4091 = bits(buf_dualhi_in, 2, 2) @[lsu_bus_buffer.scala 514:78]
-    node _T_4092 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 514:111]
-    reg _T_4093 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when _T_4092 : @[Reg.scala 28:19]
-      _T_4093 <= _T_4091 @[Reg.scala 28:23]
+    buf_dualtag[2] <= _T_4091 @[lsu_bus_buffer.scala 513:20]
+    node _T_4092 = bits(buf_dual_in, 2, 2) @[lsu_bus_buffer.scala 514:74]
+    node _T_4093 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 514:107]
+    reg _T_4094 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4093 : @[Reg.scala 28:19]
+      _T_4094 <= _T_4092 @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    buf_dualhi[2] <= _T_4093 @[lsu_bus_buffer.scala 514:19]
-    node _T_4094 = eq(UInt<3>("h00"), buf_state[3]) @[Conditional.scala 37:30]
-    when _T_4094 : @[Conditional.scala 40:58]
-      node _T_4095 = bits(io.lsu_bus_clk_en, 0, 0) @[lsu_bus_buffer.scala 445:56]
-      node _T_4096 = mux(_T_4095, UInt<3>("h02"), UInt<3>("h01")) @[lsu_bus_buffer.scala 445:31]
-      buf_nxtstate[3] <= _T_4096 @[lsu_bus_buffer.scala 445:25]
-      node _T_4097 = and(io.lsu_busreq_r, io.lsu_commit_r) @[lsu_bus_buffer.scala 446:45]
-      node _T_4098 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 446:77]
-      node _T_4099 = eq(ibuf_merge_en, UInt<1>("h00")) @[lsu_bus_buffer.scala 446:97]
-      node _T_4100 = and(_T_4098, _T_4099) @[lsu_bus_buffer.scala 446:95]
-      node _T_4101 = eq(UInt<2>("h03"), WrPtr0_r) @[lsu_bus_buffer.scala 446:117]
-      node _T_4102 = and(_T_4100, _T_4101) @[lsu_bus_buffer.scala 446:112]
-      node _T_4103 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 446:144]
-      node _T_4104 = eq(UInt<2>("h03"), WrPtr1_r) @[lsu_bus_buffer.scala 446:166]
-      node _T_4105 = and(_T_4103, _T_4104) @[lsu_bus_buffer.scala 446:161]
-      node _T_4106 = or(_T_4102, _T_4105) @[lsu_bus_buffer.scala 446:132]
-      node _T_4107 = and(_T_4097, _T_4106) @[lsu_bus_buffer.scala 446:63]
-      node _T_4108 = eq(UInt<2>("h03"), ibuf_tag) @[lsu_bus_buffer.scala 446:206]
-      node _T_4109 = and(ibuf_drain_vld, _T_4108) @[lsu_bus_buffer.scala 446:201]
-      node _T_4110 = or(_T_4107, _T_4109) @[lsu_bus_buffer.scala 446:183]
-      buf_state_en[3] <= _T_4110 @[lsu_bus_buffer.scala 446:25]
-      buf_wr_en[3] <= buf_state_en[3] @[lsu_bus_buffer.scala 447:22]
-      buf_data_en[3] <= buf_state_en[3] @[lsu_bus_buffer.scala 448:24]
-      node _T_4111 = eq(UInt<2>("h03"), ibuf_tag) @[lsu_bus_buffer.scala 449:52]
-      node _T_4112 = and(ibuf_drain_vld, _T_4111) @[lsu_bus_buffer.scala 449:47]
-      node _T_4113 = bits(_T_4112, 0, 0) @[lsu_bus_buffer.scala 449:73]
-      node _T_4114 = bits(ibuf_data_out, 31, 0) @[lsu_bus_buffer.scala 449:90]
-      node _T_4115 = bits(store_data_lo_r, 31, 0) @[lsu_bus_buffer.scala 449:114]
-      node _T_4116 = mux(_T_4113, _T_4114, _T_4115) @[lsu_bus_buffer.scala 449:30]
-      buf_data_in[3] <= _T_4116 @[lsu_bus_buffer.scala 449:24]
-      buf_cmd_state_bus_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 450:34]
+    buf_dual[2] <= _T_4094 @[lsu_bus_buffer.scala 514:17]
+    node _T_4095 = bits(buf_samedw_in, 2, 2) @[lsu_bus_buffer.scala 515:78]
+    node _T_4096 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 515:111]
+    reg _T_4097 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4096 : @[Reg.scala 28:19]
+      _T_4097 <= _T_4095 @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    buf_samedw[2] <= _T_4097 @[lsu_bus_buffer.scala 515:19]
+    node _T_4098 = bits(buf_nomerge_in, 2, 2) @[lsu_bus_buffer.scala 516:80]
+    node _T_4099 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 516:113]
+    reg _T_4100 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4099 : @[Reg.scala 28:19]
+      _T_4100 <= _T_4098 @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    buf_nomerge[2] <= _T_4100 @[lsu_bus_buffer.scala 516:20]
+    node _T_4101 = bits(buf_dualhi_in, 2, 2) @[lsu_bus_buffer.scala 517:78]
+    node _T_4102 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 517:111]
+    reg _T_4103 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4102 : @[Reg.scala 28:19]
+      _T_4103 <= _T_4101 @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    buf_dualhi[2] <= _T_4103 @[lsu_bus_buffer.scala 517:19]
+    node _T_4104 = eq(UInt<3>("h00"), buf_state[3]) @[Conditional.scala 37:30]
+    when _T_4104 : @[Conditional.scala 40:58]
+      node _T_4105 = bits(io.lsu_bus_clk_en, 0, 0) @[lsu_bus_buffer.scala 442:56]
+      node _T_4106 = mux(_T_4105, UInt<3>("h02"), UInt<3>("h01")) @[lsu_bus_buffer.scala 442:31]
+      buf_nxtstate[3] <= _T_4106 @[lsu_bus_buffer.scala 442:25]
+      node _T_4107 = and(io.lsu_busreq_r, io.lsu_commit_r) @[lsu_bus_buffer.scala 443:45]
+      node _T_4108 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 443:77]
+      node _T_4109 = eq(ibuf_merge_en, UInt<1>("h00")) @[lsu_bus_buffer.scala 443:97]
+      node _T_4110 = and(_T_4108, _T_4109) @[lsu_bus_buffer.scala 443:95]
+      node _T_4111 = eq(UInt<2>("h03"), WrPtr0_r) @[lsu_bus_buffer.scala 443:117]
+      node _T_4112 = and(_T_4110, _T_4111) @[lsu_bus_buffer.scala 443:112]
+      node _T_4113 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 443:144]
+      node _T_4114 = eq(UInt<2>("h03"), WrPtr1_r) @[lsu_bus_buffer.scala 443:166]
+      node _T_4115 = and(_T_4113, _T_4114) @[lsu_bus_buffer.scala 443:161]
+      node _T_4116 = or(_T_4112, _T_4115) @[lsu_bus_buffer.scala 443:132]
+      node _T_4117 = and(_T_4107, _T_4116) @[lsu_bus_buffer.scala 443:63]
+      node _T_4118 = eq(UInt<2>("h03"), ibuf_tag) @[lsu_bus_buffer.scala 443:206]
+      node _T_4119 = and(ibuf_drain_vld, _T_4118) @[lsu_bus_buffer.scala 443:201]
+      node _T_4120 = or(_T_4117, _T_4119) @[lsu_bus_buffer.scala 443:183]
+      buf_state_en[3] <= _T_4120 @[lsu_bus_buffer.scala 443:25]
+      buf_wr_en[3] <= buf_state_en[3] @[lsu_bus_buffer.scala 444:22]
+      buf_data_en[3] <= buf_state_en[3] @[lsu_bus_buffer.scala 445:24]
+      node _T_4121 = eq(UInt<2>("h03"), ibuf_tag) @[lsu_bus_buffer.scala 446:52]
+      node _T_4122 = and(ibuf_drain_vld, _T_4121) @[lsu_bus_buffer.scala 446:47]
+      node _T_4123 = bits(_T_4122, 0, 0) @[lsu_bus_buffer.scala 446:73]
+      node _T_4124 = bits(ibuf_data_out, 31, 0) @[lsu_bus_buffer.scala 446:90]
+      node _T_4125 = bits(store_data_lo_r, 31, 0) @[lsu_bus_buffer.scala 446:114]
+      node _T_4126 = mux(_T_4123, _T_4124, _T_4125) @[lsu_bus_buffer.scala 446:30]
+      buf_data_in[3] <= _T_4126 @[lsu_bus_buffer.scala 446:24]
+      buf_cmd_state_bus_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 447:34]
+      buf_rst[3] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 448:21]
       skip @[Conditional.scala 40:58]
     else : @[Conditional.scala 39:67]
-      node _T_4117 = eq(UInt<3>("h01"), buf_state[3]) @[Conditional.scala 37:30]
-      when _T_4117 : @[Conditional.scala 39:67]
-        node _T_4118 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 453:60]
-        node _T_4119 = mux(_T_4118, UInt<3>("h00"), UInt<3>("h02")) @[lsu_bus_buffer.scala 453:31]
-        buf_nxtstate[3] <= _T_4119 @[lsu_bus_buffer.scala 453:25]
-        node _T_4120 = or(io.lsu_bus_clk_en, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 454:46]
-        buf_state_en[3] <= _T_4120 @[lsu_bus_buffer.scala 454:25]
-        buf_cmd_state_bus_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 455:34]
+      node _T_4127 = eq(UInt<3>("h01"), buf_state[3]) @[Conditional.scala 37:30]
+      when _T_4127 : @[Conditional.scala 39:67]
+        node _T_4128 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 451:60]
+        node _T_4129 = mux(_T_4128, UInt<3>("h00"), UInt<3>("h02")) @[lsu_bus_buffer.scala 451:31]
+        buf_nxtstate[3] <= _T_4129 @[lsu_bus_buffer.scala 451:25]
+        node _T_4130 = or(io.lsu_bus_clk_en, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 452:46]
+        buf_state_en[3] <= _T_4130 @[lsu_bus_buffer.scala 452:25]
+        buf_cmd_state_bus_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 453:34]
+        buf_rst[3] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 454:20]
         skip @[Conditional.scala 39:67]
       else : @[Conditional.scala 39:67]
-        node _T_4121 = eq(UInt<3>("h02"), buf_state[3]) @[Conditional.scala 37:30]
-        when _T_4121 : @[Conditional.scala 39:67]
-          node _T_4122 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 458:60]
-          node _T_4123 = and(obuf_nosend, bus_rsp_read) @[lsu_bus_buffer.scala 458:89]
-          node _T_4124 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[lsu_bus_buffer.scala 458:124]
-          node _T_4125 = and(_T_4123, _T_4124) @[lsu_bus_buffer.scala 458:104]
-          node _T_4126 = mux(_T_4125, UInt<3>("h05"), UInt<3>("h03")) @[lsu_bus_buffer.scala 458:75]
-          node _T_4127 = mux(_T_4122, UInt<3>("h00"), _T_4126) @[lsu_bus_buffer.scala 458:31]
-          buf_nxtstate[3] <= _T_4127 @[lsu_bus_buffer.scala 458:25]
-          node _T_4128 = eq(obuf_tag0, UInt<3>("h03")) @[lsu_bus_buffer.scala 459:48]
-          node _T_4129 = eq(obuf_tag1, UInt<3>("h03")) @[lsu_bus_buffer.scala 459:104]
-          node _T_4130 = and(obuf_merge, _T_4129) @[lsu_bus_buffer.scala 459:91]
-          node _T_4131 = or(_T_4128, _T_4130) @[lsu_bus_buffer.scala 459:77]
-          node _T_4132 = and(_T_4131, obuf_valid) @[lsu_bus_buffer.scala 459:135]
-          node _T_4133 = and(_T_4132, obuf_wr_enQ) @[lsu_bus_buffer.scala 459:148]
-          buf_cmd_state_bus_en[3] <= _T_4133 @[lsu_bus_buffer.scala 459:33]
-          buf_state_bus_en[3] <= buf_cmd_state_bus_en[3] @[lsu_bus_buffer.scala 460:29]
-          node _T_4134 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 461:49]
-          node _T_4135 = or(_T_4134, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 461:70]
-          buf_state_en[3] <= _T_4135 @[lsu_bus_buffer.scala 461:25]
-          buf_ldfwd_in[3] <= UInt<1>("h01") @[lsu_bus_buffer.scala 462:25]
-          node _T_4136 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 463:56]
-          node _T_4137 = eq(_T_4136, UInt<1>("h00")) @[lsu_bus_buffer.scala 463:46]
-          node _T_4138 = and(buf_state_en[3], _T_4137) @[lsu_bus_buffer.scala 463:44]
-          node _T_4139 = and(_T_4138, obuf_nosend) @[lsu_bus_buffer.scala 463:60]
-          node _T_4140 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 463:76]
-          node _T_4141 = and(_T_4139, _T_4140) @[lsu_bus_buffer.scala 463:74]
-          buf_ldfwd_en[3] <= _T_4141 @[lsu_bus_buffer.scala 463:25]
-          node _T_4142 = bits(obuf_rdrsp_tag, 1, 0) @[lsu_bus_buffer.scala 464:46]
-          buf_ldfwdtag_in[3] <= _T_4142 @[lsu_bus_buffer.scala 464:28]
-          node _T_4143 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 465:47]
-          node _T_4144 = and(_T_4143, obuf_nosend) @[lsu_bus_buffer.scala 465:67]
-          node _T_4145 = and(_T_4144, bus_rsp_read) @[lsu_bus_buffer.scala 465:81]
-          buf_data_en[3] <= _T_4145 @[lsu_bus_buffer.scala 465:24]
-          node _T_4146 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 466:48]
-          node _T_4147 = and(_T_4146, obuf_nosend) @[lsu_bus_buffer.scala 466:68]
-          node _T_4148 = and(_T_4147, bus_rsp_read_error) @[lsu_bus_buffer.scala 466:82]
-          buf_error_en[3] <= _T_4148 @[lsu_bus_buffer.scala 466:25]
-          node _T_4149 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 467:61]
-          node _T_4150 = bits(buf_addr[3], 2, 2) @[lsu_bus_buffer.scala 467:85]
-          node _T_4151 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 467:103]
-          node _T_4152 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 467:126]
-          node _T_4153 = mux(_T_4150, _T_4151, _T_4152) @[lsu_bus_buffer.scala 467:73]
-          node _T_4154 = mux(buf_error_en[3], _T_4149, _T_4153) @[lsu_bus_buffer.scala 467:30]
-          buf_data_in[3] <= _T_4154 @[lsu_bus_buffer.scala 467:24]
+        node _T_4131 = eq(UInt<3>("h02"), buf_state[3]) @[Conditional.scala 37:30]
+        when _T_4131 : @[Conditional.scala 39:67]
+          node _T_4132 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 457:60]
+          node _T_4133 = and(obuf_nosend, bus_rsp_read) @[lsu_bus_buffer.scala 457:89]
+          node _T_4134 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[lsu_bus_buffer.scala 457:124]
+          node _T_4135 = and(_T_4133, _T_4134) @[lsu_bus_buffer.scala 457:104]
+          node _T_4136 = mux(_T_4135, UInt<3>("h05"), UInt<3>("h03")) @[lsu_bus_buffer.scala 457:75]
+          node _T_4137 = mux(_T_4132, UInt<3>("h00"), _T_4136) @[lsu_bus_buffer.scala 457:31]
+          buf_nxtstate[3] <= _T_4137 @[lsu_bus_buffer.scala 457:25]
+          node _T_4138 = eq(obuf_tag0, UInt<3>("h03")) @[lsu_bus_buffer.scala 458:48]
+          node _T_4139 = eq(obuf_tag1, UInt<3>("h03")) @[lsu_bus_buffer.scala 458:104]
+          node _T_4140 = and(obuf_merge, _T_4139) @[lsu_bus_buffer.scala 458:91]
+          node _T_4141 = or(_T_4138, _T_4140) @[lsu_bus_buffer.scala 458:77]
+          node _T_4142 = and(_T_4141, obuf_valid) @[lsu_bus_buffer.scala 458:135]
+          node _T_4143 = and(_T_4142, obuf_wr_enQ) @[lsu_bus_buffer.scala 458:148]
+          buf_cmd_state_bus_en[3] <= _T_4143 @[lsu_bus_buffer.scala 458:33]
+          buf_state_bus_en[3] <= buf_cmd_state_bus_en[3] @[lsu_bus_buffer.scala 459:29]
+          node _T_4144 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 460:49]
+          node _T_4145 = or(_T_4144, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 460:70]
+          buf_state_en[3] <= _T_4145 @[lsu_bus_buffer.scala 460:25]
+          buf_ldfwd_in[3] <= UInt<1>("h01") @[lsu_bus_buffer.scala 461:25]
+          node _T_4146 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 462:56]
+          node _T_4147 = eq(_T_4146, UInt<1>("h00")) @[lsu_bus_buffer.scala 462:46]
+          node _T_4148 = and(buf_state_en[3], _T_4147) @[lsu_bus_buffer.scala 462:44]
+          node _T_4149 = and(_T_4148, obuf_nosend) @[lsu_bus_buffer.scala 462:60]
+          node _T_4150 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 462:76]
+          node _T_4151 = and(_T_4149, _T_4150) @[lsu_bus_buffer.scala 462:74]
+          buf_ldfwd_en[3] <= _T_4151 @[lsu_bus_buffer.scala 462:25]
+          node _T_4152 = bits(obuf_rdrsp_tag, 1, 0) @[lsu_bus_buffer.scala 463:46]
+          buf_ldfwdtag_in[3] <= _T_4152 @[lsu_bus_buffer.scala 463:28]
+          node _T_4153 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 464:47]
+          node _T_4154 = and(_T_4153, obuf_nosend) @[lsu_bus_buffer.scala 464:67]
+          node _T_4155 = and(_T_4154, bus_rsp_read) @[lsu_bus_buffer.scala 464:81]
+          buf_data_en[3] <= _T_4155 @[lsu_bus_buffer.scala 464:24]
+          node _T_4156 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 465:48]
+          node _T_4157 = and(_T_4156, obuf_nosend) @[lsu_bus_buffer.scala 465:68]
+          node _T_4158 = and(_T_4157, bus_rsp_read_error) @[lsu_bus_buffer.scala 465:82]
+          buf_error_en[3] <= _T_4158 @[lsu_bus_buffer.scala 465:25]
+          node _T_4159 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 466:61]
+          node _T_4160 = bits(buf_addr[3], 2, 2) @[lsu_bus_buffer.scala 466:85]
+          node _T_4161 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 466:103]
+          node _T_4162 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 466:126]
+          node _T_4163 = mux(_T_4160, _T_4161, _T_4162) @[lsu_bus_buffer.scala 466:73]
+          node _T_4164 = mux(buf_error_en[3], _T_4159, _T_4163) @[lsu_bus_buffer.scala 466:30]
+          buf_data_in[3] <= _T_4164 @[lsu_bus_buffer.scala 466:24]
+          buf_rst[3] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 467:20]
           skip @[Conditional.scala 39:67]
         else : @[Conditional.scala 39:67]
-          node _T_4155 = eq(UInt<3>("h03"), buf_state[3]) @[Conditional.scala 37:30]
-          when _T_4155 : @[Conditional.scala 39:67]
-            node _T_4156 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 470:67]
-            node _T_4157 = and(_T_4156, bus_rsp_write_error) @[lsu_bus_buffer.scala 470:71]
-            node _T_4158 = or(io.dec_tlu_force_halt, _T_4157) @[lsu_bus_buffer.scala 470:55]
-            node _T_4159 = bits(_T_4158, 0, 0) @[lsu_bus_buffer.scala 470:101]
-            node _T_4160 = eq(buf_samedw[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 471:30]
-            node _T_4161 = and(buf_dual[3], _T_4160) @[lsu_bus_buffer.scala 471:28]
-            node _T_4162 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 471:57]
-            node _T_4163 = eq(_T_4162, UInt<1>("h00")) @[lsu_bus_buffer.scala 471:47]
-            node _T_4164 = and(_T_4161, _T_4163) @[lsu_bus_buffer.scala 471:45]
-            node _T_4165 = neq(buf_state[buf_dualtag[3]], UInt<3>("h04")) @[lsu_bus_buffer.scala 471:90]
-            node _T_4166 = and(_T_4164, _T_4165) @[lsu_bus_buffer.scala 471:61]
-            node _T_4167 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 472:27]
-            node _T_4168 = or(_T_4167, any_done_wait_state) @[lsu_bus_buffer.scala 472:31]
-            node _T_4169 = eq(buf_samedw[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 472:70]
-            node _T_4170 = and(buf_dual[3], _T_4169) @[lsu_bus_buffer.scala 472:68]
-            node _T_4171 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 472:97]
-            node _T_4172 = eq(_T_4171, UInt<1>("h00")) @[lsu_bus_buffer.scala 472:87]
-            node _T_4173 = and(_T_4170, _T_4172) @[lsu_bus_buffer.scala 472:85]
-            node _T_4174 = eq(buf_dualtag[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 60:118]
-            node _T_4175 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 60:129]
-            node _T_4176 = eq(buf_dualtag[3], UInt<1>("h01")) @[lsu_bus_buffer.scala 60:118]
-            node _T_4177 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 60:129]
-            node _T_4178 = eq(buf_dualtag[3], UInt<2>("h02")) @[lsu_bus_buffer.scala 60:118]
-            node _T_4179 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 60:129]
-            node _T_4180 = eq(buf_dualtag[3], UInt<2>("h03")) @[lsu_bus_buffer.scala 60:118]
-            node _T_4181 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 60:129]
-            node _T_4182 = mux(_T_4174, _T_4175, UInt<1>("h00")) @[Mux.scala 27:72]
-            node _T_4183 = mux(_T_4176, _T_4177, UInt<1>("h00")) @[Mux.scala 27:72]
-            node _T_4184 = mux(_T_4178, _T_4179, UInt<1>("h00")) @[Mux.scala 27:72]
-            node _T_4185 = mux(_T_4180, _T_4181, UInt<1>("h00")) @[Mux.scala 27:72]
-            node _T_4186 = or(_T_4182, _T_4183) @[Mux.scala 27:72]
-            node _T_4187 = or(_T_4186, _T_4184) @[Mux.scala 27:72]
-            node _T_4188 = or(_T_4187, _T_4185) @[Mux.scala 27:72]
-            wire _T_4189 : UInt<1> @[Mux.scala 27:72]
-            _T_4189 <= _T_4188 @[Mux.scala 27:72]
-            node _T_4190 = and(_T_4173, _T_4189) @[lsu_bus_buffer.scala 472:101]
-            node _T_4191 = eq(buf_state[buf_dualtag[3]], UInt<3>("h04")) @[lsu_bus_buffer.scala 472:167]
-            node _T_4192 = and(_T_4190, _T_4191) @[lsu_bus_buffer.scala 472:138]
-            node _T_4193 = and(_T_4192, any_done_wait_state) @[lsu_bus_buffer.scala 472:187]
-            node _T_4194 = or(_T_4168, _T_4193) @[lsu_bus_buffer.scala 472:53]
-            node _T_4195 = mux(_T_4194, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 472:16]
-            node _T_4196 = mux(_T_4166, UInt<3>("h04"), _T_4195) @[lsu_bus_buffer.scala 471:14]
-            node _T_4197 = mux(_T_4159, UInt<3>("h00"), _T_4196) @[lsu_bus_buffer.scala 470:31]
-            buf_nxtstate[3] <= _T_4197 @[lsu_bus_buffer.scala 470:25]
-            node _T_4198 = eq(bus_rsp_write_tag, UInt<3>("h03")) @[lsu_bus_buffer.scala 473:73]
-            node _T_4199 = and(bus_rsp_write, _T_4198) @[lsu_bus_buffer.scala 473:52]
-            node _T_4200 = eq(bus_rsp_read_tag, UInt<3>("h03")) @[lsu_bus_buffer.scala 474:46]
-            node _T_4201 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 475:23]
-            node _T_4202 = eq(bus_rsp_read_tag, buf_ldfwdtag[3]) @[lsu_bus_buffer.scala 475:47]
-            node _T_4203 = and(_T_4201, _T_4202) @[lsu_bus_buffer.scala 475:27]
-            node _T_4204 = or(_T_4200, _T_4203) @[lsu_bus_buffer.scala 474:77]
-            node _T_4205 = and(buf_dual[3], buf_dualhi[3]) @[lsu_bus_buffer.scala 476:26]
-            node _T_4206 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 476:54]
-            node _T_4207 = not(_T_4206) @[lsu_bus_buffer.scala 476:44]
-            node _T_4208 = and(_T_4205, _T_4207) @[lsu_bus_buffer.scala 476:42]
-            node _T_4209 = and(_T_4208, buf_samedw[3]) @[lsu_bus_buffer.scala 476:58]
-            node _T_4210 = eq(bus_rsp_read_tag, buf_dualtag[3]) @[lsu_bus_buffer.scala 476:94]
-            node _T_4211 = and(_T_4209, _T_4210) @[lsu_bus_buffer.scala 476:74]
-            node _T_4212 = or(_T_4204, _T_4211) @[lsu_bus_buffer.scala 475:71]
-            node _T_4213 = and(bus_rsp_read, _T_4212) @[lsu_bus_buffer.scala 474:25]
-            node _T_4214 = or(_T_4199, _T_4213) @[lsu_bus_buffer.scala 473:105]
-            buf_resp_state_bus_en[3] <= _T_4214 @[lsu_bus_buffer.scala 473:34]
+          node _T_4165 = eq(UInt<3>("h03"), buf_state[3]) @[Conditional.scala 37:30]
+          when _T_4165 : @[Conditional.scala 39:67]
+            node _T_4166 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 470:69]
+            node _T_4167 = eq(bus_rsp_write_error, UInt<1>("h00")) @[lsu_bus_buffer.scala 470:75]
+            node _T_4168 = and(_T_4166, _T_4167) @[lsu_bus_buffer.scala 470:73]
+            node _T_4169 = or(io.dec_tlu_force_halt, _T_4168) @[lsu_bus_buffer.scala 470:57]
+            node _T_4170 = bits(_T_4169, 0, 0) @[lsu_bus_buffer.scala 470:104]
+            node _T_4171 = eq(buf_samedw[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 471:30]
+            node _T_4172 = and(buf_dual[3], _T_4171) @[lsu_bus_buffer.scala 471:28]
+            node _T_4173 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 471:57]
+            node _T_4174 = eq(_T_4173, UInt<1>("h00")) @[lsu_bus_buffer.scala 471:47]
+            node _T_4175 = and(_T_4172, _T_4174) @[lsu_bus_buffer.scala 471:45]
+            node _T_4176 = neq(buf_state[buf_dualtag[3]], UInt<3>("h04")) @[lsu_bus_buffer.scala 471:90]
+            node _T_4177 = and(_T_4175, _T_4176) @[lsu_bus_buffer.scala 471:61]
+            node _T_4178 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 472:27]
+            node _T_4179 = or(_T_4178, any_done_wait_state) @[lsu_bus_buffer.scala 472:31]
+            node _T_4180 = eq(buf_samedw[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 472:70]
+            node _T_4181 = and(buf_dual[3], _T_4180) @[lsu_bus_buffer.scala 472:68]
+            node _T_4182 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 472:97]
+            node _T_4183 = eq(_T_4182, UInt<1>("h00")) @[lsu_bus_buffer.scala 472:87]
+            node _T_4184 = and(_T_4181, _T_4183) @[lsu_bus_buffer.scala 472:85]
+            node _T_4185 = eq(buf_dualtag[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 60:118]
+            node _T_4186 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 60:129]
+            node _T_4187 = eq(buf_dualtag[3], UInt<1>("h01")) @[lsu_bus_buffer.scala 60:118]
+            node _T_4188 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 60:129]
+            node _T_4189 = eq(buf_dualtag[3], UInt<2>("h02")) @[lsu_bus_buffer.scala 60:118]
+            node _T_4190 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 60:129]
+            node _T_4191 = eq(buf_dualtag[3], UInt<2>("h03")) @[lsu_bus_buffer.scala 60:118]
+            node _T_4192 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 60:129]
+            node _T_4193 = mux(_T_4185, _T_4186, UInt<1>("h00")) @[Mux.scala 27:72]
+            node _T_4194 = mux(_T_4187, _T_4188, UInt<1>("h00")) @[Mux.scala 27:72]
+            node _T_4195 = mux(_T_4189, _T_4190, UInt<1>("h00")) @[Mux.scala 27:72]
+            node _T_4196 = mux(_T_4191, _T_4192, UInt<1>("h00")) @[Mux.scala 27:72]
+            node _T_4197 = or(_T_4193, _T_4194) @[Mux.scala 27:72]
+            node _T_4198 = or(_T_4197, _T_4195) @[Mux.scala 27:72]
+            node _T_4199 = or(_T_4198, _T_4196) @[Mux.scala 27:72]
+            wire _T_4200 : UInt<1> @[Mux.scala 27:72]
+            _T_4200 <= _T_4199 @[Mux.scala 27:72]
+            node _T_4201 = and(_T_4184, _T_4200) @[lsu_bus_buffer.scala 472:101]
+            node _T_4202 = eq(buf_state[buf_dualtag[3]], UInt<3>("h04")) @[lsu_bus_buffer.scala 472:167]
+            node _T_4203 = and(_T_4201, _T_4202) @[lsu_bus_buffer.scala 472:138]
+            node _T_4204 = and(_T_4203, any_done_wait_state) @[lsu_bus_buffer.scala 472:187]
+            node _T_4205 = or(_T_4179, _T_4204) @[lsu_bus_buffer.scala 472:53]
+            node _T_4206 = mux(_T_4205, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 472:16]
+            node _T_4207 = mux(_T_4177, UInt<3>("h04"), _T_4206) @[lsu_bus_buffer.scala 471:14]
+            node _T_4208 = mux(_T_4170, UInt<3>("h00"), _T_4207) @[lsu_bus_buffer.scala 470:33]
+            buf_nxtstate[3] <= _T_4208 @[lsu_bus_buffer.scala 470:27]
+            node _T_4209 = eq(bus_rsp_write_tag, UInt<3>("h03")) @[lsu_bus_buffer.scala 473:73]
+            node _T_4210 = and(bus_rsp_write, _T_4209) @[lsu_bus_buffer.scala 473:52]
+            node _T_4211 = eq(bus_rsp_read_tag, UInt<3>("h03")) @[lsu_bus_buffer.scala 474:46]
+            node _T_4212 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 475:23]
+            node _T_4213 = eq(bus_rsp_read_tag, buf_ldfwdtag[3]) @[lsu_bus_buffer.scala 475:47]
+            node _T_4214 = and(_T_4212, _T_4213) @[lsu_bus_buffer.scala 475:27]
+            node _T_4215 = or(_T_4211, _T_4214) @[lsu_bus_buffer.scala 474:77]
+            node _T_4216 = and(buf_dual[3], buf_dualhi[3]) @[lsu_bus_buffer.scala 476:26]
+            node _T_4217 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 476:54]
+            node _T_4218 = not(_T_4217) @[lsu_bus_buffer.scala 476:44]
+            node _T_4219 = and(_T_4216, _T_4218) @[lsu_bus_buffer.scala 476:42]
+            node _T_4220 = and(_T_4219, buf_samedw[3]) @[lsu_bus_buffer.scala 476:58]
+            node _T_4221 = eq(bus_rsp_read_tag, buf_dualtag[3]) @[lsu_bus_buffer.scala 476:94]
+            node _T_4222 = and(_T_4220, _T_4221) @[lsu_bus_buffer.scala 476:74]
+            node _T_4223 = or(_T_4215, _T_4222) @[lsu_bus_buffer.scala 475:71]
+            node _T_4224 = and(bus_rsp_read, _T_4223) @[lsu_bus_buffer.scala 474:25]
+            node _T_4225 = or(_T_4210, _T_4224) @[lsu_bus_buffer.scala 473:105]
+            buf_resp_state_bus_en[3] <= _T_4225 @[lsu_bus_buffer.scala 473:34]
             buf_state_bus_en[3] <= buf_resp_state_bus_en[3] @[lsu_bus_buffer.scala 477:29]
-            node _T_4215 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 478:49]
-            node _T_4216 = or(_T_4215, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 478:70]
-            buf_state_en[3] <= _T_4216 @[lsu_bus_buffer.scala 478:25]
-            node _T_4217 = and(buf_state_bus_en[3], bus_rsp_read) @[lsu_bus_buffer.scala 479:47]
-            node _T_4218 = and(_T_4217, io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 479:62]
-            buf_data_en[3] <= _T_4218 @[lsu_bus_buffer.scala 479:24]
-            node _T_4219 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 480:48]
-            node _T_4220 = eq(bus_rsp_read_tag, UInt<3>("h03")) @[lsu_bus_buffer.scala 480:111]
-            node _T_4221 = and(bus_rsp_read_error, _T_4220) @[lsu_bus_buffer.scala 480:91]
-            node _T_4222 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 481:42]
-            node _T_4223 = and(bus_rsp_read_error, _T_4222) @[lsu_bus_buffer.scala 481:31]
-            node _T_4224 = eq(bus_rsp_read_tag, buf_ldfwdtag[3]) @[lsu_bus_buffer.scala 481:66]
-            node _T_4225 = and(_T_4223, _T_4224) @[lsu_bus_buffer.scala 481:46]
-            node _T_4226 = or(_T_4221, _T_4225) @[lsu_bus_buffer.scala 480:143]
-            node _T_4227 = eq(bus_rsp_write_tag, UInt<3>("h03")) @[lsu_bus_buffer.scala 482:54]
-            node _T_4228 = and(bus_rsp_write_error, _T_4227) @[lsu_bus_buffer.scala 482:33]
-            node _T_4229 = or(_T_4226, _T_4228) @[lsu_bus_buffer.scala 481:88]
-            node _T_4230 = and(_T_4219, _T_4229) @[lsu_bus_buffer.scala 480:68]
-            buf_error_en[3] <= _T_4230 @[lsu_bus_buffer.scala 480:25]
-            node _T_4231 = eq(buf_error_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 483:50]
-            node _T_4232 = and(buf_state_en[3], _T_4231) @[lsu_bus_buffer.scala 483:48]
-            node _T_4233 = bits(buf_addr[3], 2, 2) @[lsu_bus_buffer.scala 483:84]
-            node _T_4234 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 483:102]
-            node _T_4235 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 483:125]
-            node _T_4236 = mux(_T_4233, _T_4234, _T_4235) @[lsu_bus_buffer.scala 483:72]
-            node _T_4237 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 483:148]
-            node _T_4238 = mux(_T_4232, _T_4236, _T_4237) @[lsu_bus_buffer.scala 483:30]
-            buf_data_in[3] <= _T_4238 @[lsu_bus_buffer.scala 483:24]
+            node _T_4226 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 478:49]
+            node _T_4227 = or(_T_4226, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 478:70]
+            buf_state_en[3] <= _T_4227 @[lsu_bus_buffer.scala 478:25]
+            node _T_4228 = and(buf_state_bus_en[3], bus_rsp_read) @[lsu_bus_buffer.scala 479:47]
+            node _T_4229 = and(_T_4228, io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 479:62]
+            buf_data_en[3] <= _T_4229 @[lsu_bus_buffer.scala 479:24]
+            node _T_4230 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 480:48]
+            node _T_4231 = eq(bus_rsp_read_tag, UInt<3>("h03")) @[lsu_bus_buffer.scala 480:111]
+            node _T_4232 = and(bus_rsp_read_error, _T_4231) @[lsu_bus_buffer.scala 480:91]
+            node _T_4233 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 481:42]
+            node _T_4234 = and(bus_rsp_read_error, _T_4233) @[lsu_bus_buffer.scala 481:31]
+            node _T_4235 = eq(bus_rsp_read_tag, buf_ldfwdtag[3]) @[lsu_bus_buffer.scala 481:66]
+            node _T_4236 = and(_T_4234, _T_4235) @[lsu_bus_buffer.scala 481:46]
+            node _T_4237 = or(_T_4232, _T_4236) @[lsu_bus_buffer.scala 480:143]
+            node _T_4238 = eq(bus_rsp_write_tag, UInt<3>("h03")) @[lsu_bus_buffer.scala 482:54]
+            node _T_4239 = and(bus_rsp_write_error, _T_4238) @[lsu_bus_buffer.scala 482:33]
+            node _T_4240 = or(_T_4237, _T_4239) @[lsu_bus_buffer.scala 481:88]
+            node _T_4241 = and(_T_4230, _T_4240) @[lsu_bus_buffer.scala 480:68]
+            buf_error_en[3] <= _T_4241 @[lsu_bus_buffer.scala 480:25]
+            node _T_4242 = eq(buf_error_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 483:50]
+            node _T_4243 = and(buf_state_en[3], _T_4242) @[lsu_bus_buffer.scala 483:48]
+            node _T_4244 = bits(buf_addr[3], 2, 2) @[lsu_bus_buffer.scala 483:84]
+            node _T_4245 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 483:102]
+            node _T_4246 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 483:125]
+            node _T_4247 = mux(_T_4244, _T_4245, _T_4246) @[lsu_bus_buffer.scala 483:72]
+            node _T_4248 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 483:148]
+            node _T_4249 = mux(_T_4243, _T_4247, _T_4248) @[lsu_bus_buffer.scala 483:30]
+            buf_data_in[3] <= _T_4249 @[lsu_bus_buffer.scala 483:24]
             buf_cmd_state_bus_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 484:34]
+            buf_rst[3] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 485:20]
             skip @[Conditional.scala 39:67]
           else : @[Conditional.scala 39:67]
-            node _T_4239 = eq(UInt<3>("h04"), buf_state[3]) @[Conditional.scala 37:30]
-            when _T_4239 : @[Conditional.scala 39:67]
-              node _T_4240 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 487:60]
-              node _T_4241 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 487:86]
-              node _T_4242 = dshr(buf_ldfwd, buf_dualtag[3]) @[lsu_bus_buffer.scala 487:101]
-              node _T_4243 = bits(_T_4242, 0, 0) @[lsu_bus_buffer.scala 487:101]
-              node _T_4244 = or(_T_4241, _T_4243) @[lsu_bus_buffer.scala 487:90]
-              node _T_4245 = or(_T_4244, any_done_wait_state) @[lsu_bus_buffer.scala 487:118]
-              node _T_4246 = mux(_T_4245, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 487:75]
-              node _T_4247 = mux(_T_4240, UInt<3>("h00"), _T_4246) @[lsu_bus_buffer.scala 487:31]
-              buf_nxtstate[3] <= _T_4247 @[lsu_bus_buffer.scala 487:25]
-              node _T_4248 = eq(bus_rsp_read_tag, buf_dualtag[3]) @[lsu_bus_buffer.scala 488:66]
-              node _T_4249 = dshr(buf_ldfwd, buf_dualtag[3]) @[lsu_bus_buffer.scala 489:21]
-              node _T_4250 = bits(_T_4249, 0, 0) @[lsu_bus_buffer.scala 489:21]
-              node _T_4251 = eq(bus_rsp_read_tag, buf_ldfwdtag[buf_dualtag[3]]) @[lsu_bus_buffer.scala 489:58]
-              node _T_4252 = and(_T_4250, _T_4251) @[lsu_bus_buffer.scala 489:38]
-              node _T_4253 = or(_T_4248, _T_4252) @[lsu_bus_buffer.scala 488:95]
-              node _T_4254 = and(bus_rsp_read, _T_4253) @[lsu_bus_buffer.scala 488:45]
-              buf_state_bus_en[3] <= _T_4254 @[lsu_bus_buffer.scala 488:29]
-              node _T_4255 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 490:49]
-              node _T_4256 = or(_T_4255, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 490:70]
-              buf_state_en[3] <= _T_4256 @[lsu_bus_buffer.scala 490:25]
-              buf_cmd_state_bus_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 491:34]
+            node _T_4250 = eq(UInt<3>("h04"), buf_state[3]) @[Conditional.scala 37:30]
+            when _T_4250 : @[Conditional.scala 39:67]
+              node _T_4251 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 488:60]
+              node _T_4252 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 488:86]
+              node _T_4253 = dshr(buf_ldfwd, buf_dualtag[3]) @[lsu_bus_buffer.scala 488:101]
+              node _T_4254 = bits(_T_4253, 0, 0) @[lsu_bus_buffer.scala 488:101]
+              node _T_4255 = or(_T_4252, _T_4254) @[lsu_bus_buffer.scala 488:90]
+              node _T_4256 = or(_T_4255, any_done_wait_state) @[lsu_bus_buffer.scala 488:118]
+              node _T_4257 = mux(_T_4256, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 488:75]
+              node _T_4258 = mux(_T_4251, UInt<3>("h00"), _T_4257) @[lsu_bus_buffer.scala 488:31]
+              buf_nxtstate[3] <= _T_4258 @[lsu_bus_buffer.scala 488:25]
+              node _T_4259 = eq(bus_rsp_read_tag, buf_dualtag[3]) @[lsu_bus_buffer.scala 489:66]
+              node _T_4260 = dshr(buf_ldfwd, buf_dualtag[3]) @[lsu_bus_buffer.scala 490:21]
+              node _T_4261 = bits(_T_4260, 0, 0) @[lsu_bus_buffer.scala 490:21]
+              node _T_4262 = eq(bus_rsp_read_tag, buf_ldfwdtag[buf_dualtag[3]]) @[lsu_bus_buffer.scala 490:58]
+              node _T_4263 = and(_T_4261, _T_4262) @[lsu_bus_buffer.scala 490:38]
+              node _T_4264 = or(_T_4259, _T_4263) @[lsu_bus_buffer.scala 489:95]
+              node _T_4265 = and(bus_rsp_read, _T_4264) @[lsu_bus_buffer.scala 489:45]
+              buf_state_bus_en[3] <= _T_4265 @[lsu_bus_buffer.scala 489:29]
+              node _T_4266 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 491:49]
+              node _T_4267 = or(_T_4266, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 491:70]
+              buf_state_en[3] <= _T_4267 @[lsu_bus_buffer.scala 491:25]
+              buf_cmd_state_bus_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 492:34]
+              buf_rst[3] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 493:20]
               skip @[Conditional.scala 39:67]
             else : @[Conditional.scala 39:67]
-              node _T_4257 = eq(UInt<3>("h05"), buf_state[3]) @[Conditional.scala 37:30]
-              when _T_4257 : @[Conditional.scala 39:67]
-                node _T_4258 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 494:60]
-                node _T_4259 = mux(_T_4258, UInt<3>("h00"), UInt<3>("h06")) @[lsu_bus_buffer.scala 494:31]
-                buf_nxtstate[3] <= _T_4259 @[lsu_bus_buffer.scala 494:25]
-                node _T_4260 = eq(RspPtr, UInt<2>("h03")) @[lsu_bus_buffer.scala 495:37]
-                node _T_4261 = eq(buf_dualtag[3], RspPtr) @[lsu_bus_buffer.scala 495:98]
-                node _T_4262 = and(buf_dual[3], _T_4261) @[lsu_bus_buffer.scala 495:80]
-                node _T_4263 = or(_T_4260, _T_4262) @[lsu_bus_buffer.scala 495:65]
-                node _T_4264 = or(_T_4263, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 495:112]
-                buf_state_en[3] <= _T_4264 @[lsu_bus_buffer.scala 495:25]
-                buf_cmd_state_bus_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 496:34]
+              node _T_4268 = eq(UInt<3>("h05"), buf_state[3]) @[Conditional.scala 37:30]
+              when _T_4268 : @[Conditional.scala 39:67]
+                node _T_4269 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 496:60]
+                node _T_4270 = mux(_T_4269, UInt<3>("h00"), UInt<3>("h06")) @[lsu_bus_buffer.scala 496:31]
+                buf_nxtstate[3] <= _T_4270 @[lsu_bus_buffer.scala 496:25]
+                node _T_4271 = eq(RspPtr, UInt<2>("h03")) @[lsu_bus_buffer.scala 497:37]
+                node _T_4272 = eq(buf_dualtag[3], RspPtr) @[lsu_bus_buffer.scala 497:98]
+                node _T_4273 = and(buf_dual[3], _T_4272) @[lsu_bus_buffer.scala 497:80]
+                node _T_4274 = or(_T_4271, _T_4273) @[lsu_bus_buffer.scala 497:65]
+                node _T_4275 = or(_T_4274, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 497:112]
+                buf_state_en[3] <= _T_4275 @[lsu_bus_buffer.scala 497:25]
+                buf_cmd_state_bus_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 498:34]
+                buf_rst[3] <= io.dec_tlu_force_halt @[lsu_bus_buffer.scala 499:20]
                 skip @[Conditional.scala 39:67]
               else : @[Conditional.scala 39:67]
-                node _T_4265 = eq(UInt<3>("h06"), buf_state[3]) @[Conditional.scala 37:30]
-                when _T_4265 : @[Conditional.scala 39:67]
-                  buf_nxtstate[3] <= UInt<3>("h00") @[lsu_bus_buffer.scala 499:25]
-                  buf_rst[3] <= UInt<1>("h01") @[lsu_bus_buffer.scala 500:20]
-                  buf_state_en[3] <= UInt<1>("h01") @[lsu_bus_buffer.scala 501:25]
-                  buf_ldfwd_in[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 502:25]
-                  buf_ldfwd_en[3] <= buf_state_en[3] @[lsu_bus_buffer.scala 503:25]
-                  buf_cmd_state_bus_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 504:34]
+                node _T_4276 = eq(UInt<3>("h06"), buf_state[3]) @[Conditional.scala 37:30]
+                when _T_4276 : @[Conditional.scala 39:67]
+                  buf_nxtstate[3] <= UInt<3>("h00") @[lsu_bus_buffer.scala 502:25]
+                  buf_rst[3] <= UInt<1>("h01") @[lsu_bus_buffer.scala 503:20]
+                  buf_state_en[3] <= UInt<1>("h01") @[lsu_bus_buffer.scala 504:25]
+                  buf_ldfwd_in[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 505:25]
+                  buf_ldfwd_en[3] <= buf_state_en[3] @[lsu_bus_buffer.scala 506:25]
+                  buf_cmd_state_bus_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 507:34]
                   skip @[Conditional.scala 39:67]
-    node _T_4266 = bits(buf_state_en[3], 0, 0) @[lsu_bus_buffer.scala 507:108]
-    reg _T_4267 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when _T_4266 : @[Reg.scala 28:19]
-      _T_4267 <= buf_nxtstate[3] @[Reg.scala 28:23]
+    node _T_4277 = bits(buf_state_en[3], 0, 0) @[lsu_bus_buffer.scala 510:108]
+    reg _T_4278 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4277 : @[Reg.scala 28:19]
+      _T_4278 <= buf_nxtstate[3] @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    buf_state[3] <= _T_4267 @[lsu_bus_buffer.scala 507:18]
-    reg _T_4268 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 508:60]
-    _T_4268 <= buf_age_in_3 @[lsu_bus_buffer.scala 508:60]
-    buf_ageQ[3] <= _T_4268 @[lsu_bus_buffer.scala 508:17]
-    reg _T_4269 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 509:63]
-    _T_4269 <= buf_rspage_in[3] @[lsu_bus_buffer.scala 509:63]
-    buf_rspageQ[3] <= _T_4269 @[lsu_bus_buffer.scala 509:20]
-    node _T_4270 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 510:109]
-    reg _T_4271 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when _T_4270 : @[Reg.scala 28:19]
-      _T_4271 <= buf_dualtag_in[3] @[Reg.scala 28:23]
+    buf_state[3] <= _T_4278 @[lsu_bus_buffer.scala 510:18]
+    reg _T_4279 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 511:60]
+    _T_4279 <= buf_age_in_3 @[lsu_bus_buffer.scala 511:60]
+    buf_ageQ[3] <= _T_4279 @[lsu_bus_buffer.scala 511:17]
+    reg _T_4280 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 512:63]
+    _T_4280 <= buf_rspage_in[3] @[lsu_bus_buffer.scala 512:63]
+    buf_rspageQ[3] <= _T_4280 @[lsu_bus_buffer.scala 512:20]
+    node _T_4281 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 513:109]
+    reg _T_4282 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4281 : @[Reg.scala 28:19]
+      _T_4282 <= buf_dualtag_in[3] @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    buf_dualtag[3] <= _T_4271 @[lsu_bus_buffer.scala 510:20]
-    node _T_4272 = bits(buf_dual_in, 3, 3) @[lsu_bus_buffer.scala 511:74]
-    node _T_4273 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 511:107]
-    reg _T_4274 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when _T_4273 : @[Reg.scala 28:19]
-      _T_4274 <= _T_4272 @[Reg.scala 28:23]
-      skip @[Reg.scala 28:19]
-    buf_dual[3] <= _T_4274 @[lsu_bus_buffer.scala 511:17]
-    node _T_4275 = bits(buf_samedw_in, 3, 3) @[lsu_bus_buffer.scala 512:78]
-    node _T_4276 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 512:111]
-    reg _T_4277 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when _T_4276 : @[Reg.scala 28:19]
-      _T_4277 <= _T_4275 @[Reg.scala 28:23]
-      skip @[Reg.scala 28:19]
-    buf_samedw[3] <= _T_4277 @[lsu_bus_buffer.scala 512:19]
-    node _T_4278 = bits(buf_nomerge_in, 3, 3) @[lsu_bus_buffer.scala 513:80]
-    node _T_4279 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 513:113]
-    reg _T_4280 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when _T_4279 : @[Reg.scala 28:19]
-      _T_4280 <= _T_4278 @[Reg.scala 28:23]
-      skip @[Reg.scala 28:19]
-    buf_nomerge[3] <= _T_4280 @[lsu_bus_buffer.scala 513:20]
-    node _T_4281 = bits(buf_dualhi_in, 3, 3) @[lsu_bus_buffer.scala 514:78]
-    node _T_4282 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 514:111]
-    reg _T_4283 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when _T_4282 : @[Reg.scala 28:19]
-      _T_4283 <= _T_4281 @[Reg.scala 28:23]
-      skip @[Reg.scala 28:19]
-    buf_dualhi[3] <= _T_4283 @[lsu_bus_buffer.scala 514:19]
-    node _T_4284 = bits(buf_ldfwd_en[0], 0, 0) @[lsu_bus_buffer.scala 517:131]
+    buf_dualtag[3] <= _T_4282 @[lsu_bus_buffer.scala 513:20]
+    node _T_4283 = bits(buf_dual_in, 3, 3) @[lsu_bus_buffer.scala 514:74]
+    node _T_4284 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 514:107]
     reg _T_4285 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
     when _T_4284 : @[Reg.scala 28:19]
-      _T_4285 <= buf_ldfwd_in[0] @[Reg.scala 28:23]
+      _T_4285 <= _T_4283 @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    node _T_4286 = bits(buf_ldfwd_en[1], 0, 0) @[lsu_bus_buffer.scala 517:131]
-    reg _T_4287 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when _T_4286 : @[Reg.scala 28:19]
-      _T_4287 <= buf_ldfwd_in[1] @[Reg.scala 28:23]
+    buf_dual[3] <= _T_4285 @[lsu_bus_buffer.scala 514:17]
+    node _T_4286 = bits(buf_samedw_in, 3, 3) @[lsu_bus_buffer.scala 515:78]
+    node _T_4287 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 515:111]
+    reg _T_4288 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4287 : @[Reg.scala 28:19]
+      _T_4288 <= _T_4286 @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    node _T_4288 = bits(buf_ldfwd_en[2], 0, 0) @[lsu_bus_buffer.scala 517:131]
-    reg _T_4289 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when _T_4288 : @[Reg.scala 28:19]
-      _T_4289 <= buf_ldfwd_in[2] @[Reg.scala 28:23]
-      skip @[Reg.scala 28:19]
-    node _T_4290 = bits(buf_ldfwd_en[3], 0, 0) @[lsu_bus_buffer.scala 517:131]
+    buf_samedw[3] <= _T_4288 @[lsu_bus_buffer.scala 515:19]
+    node _T_4289 = bits(buf_nomerge_in, 3, 3) @[lsu_bus_buffer.scala 516:80]
+    node _T_4290 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 516:113]
     reg _T_4291 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
     when _T_4290 : @[Reg.scala 28:19]
-      _T_4291 <= buf_ldfwd_in[3] @[Reg.scala 28:23]
+      _T_4291 <= _T_4289 @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    node _T_4292 = cat(_T_4291, _T_4289) @[Cat.scala 29:58]
-    node _T_4293 = cat(_T_4292, _T_4287) @[Cat.scala 29:58]
-    node _T_4294 = cat(_T_4293, _T_4285) @[Cat.scala 29:58]
-    buf_ldfwd <= _T_4294 @[lsu_bus_buffer.scala 517:13]
-    node _T_4295 = bits(buf_ldfwd_en[0], 0, 0) @[lsu_bus_buffer.scala 518:132]
-    reg _T_4296 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    buf_nomerge[3] <= _T_4291 @[lsu_bus_buffer.scala 516:20]
+    node _T_4292 = bits(buf_dualhi_in, 3, 3) @[lsu_bus_buffer.scala 517:78]
+    node _T_4293 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 517:111]
+    reg _T_4294 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4293 : @[Reg.scala 28:19]
+      _T_4294 <= _T_4292 @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    buf_dualhi[3] <= _T_4294 @[lsu_bus_buffer.scala 517:19]
+    node _T_4295 = bits(buf_ldfwd_en[0], 0, 0) @[lsu_bus_buffer.scala 520:131]
+    reg _T_4296 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
     when _T_4295 : @[Reg.scala 28:19]
-      _T_4296 <= buf_ldfwdtag_in[0] @[Reg.scala 28:23]
+      _T_4296 <= buf_ldfwd_in[0] @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    node _T_4297 = bits(buf_ldfwd_en[1], 0, 0) @[lsu_bus_buffer.scala 518:132]
-    reg _T_4298 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    node _T_4297 = bits(buf_ldfwd_en[1], 0, 0) @[lsu_bus_buffer.scala 520:131]
+    reg _T_4298 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
     when _T_4297 : @[Reg.scala 28:19]
-      _T_4298 <= buf_ldfwdtag_in[1] @[Reg.scala 28:23]
+      _T_4298 <= buf_ldfwd_in[1] @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    node _T_4299 = bits(buf_ldfwd_en[2], 0, 0) @[lsu_bus_buffer.scala 518:132]
-    reg _T_4300 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    node _T_4299 = bits(buf_ldfwd_en[2], 0, 0) @[lsu_bus_buffer.scala 520:131]
+    reg _T_4300 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
     when _T_4299 : @[Reg.scala 28:19]
-      _T_4300 <= buf_ldfwdtag_in[2] @[Reg.scala 28:23]
+      _T_4300 <= buf_ldfwd_in[2] @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    node _T_4301 = bits(buf_ldfwd_en[3], 0, 0) @[lsu_bus_buffer.scala 518:132]
-    reg _T_4302 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    node _T_4301 = bits(buf_ldfwd_en[3], 0, 0) @[lsu_bus_buffer.scala 520:131]
+    reg _T_4302 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
     when _T_4301 : @[Reg.scala 28:19]
-      _T_4302 <= buf_ldfwdtag_in[3] @[Reg.scala 28:23]
+      _T_4302 <= buf_ldfwd_in[3] @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    buf_ldfwdtag[0] <= _T_4296 @[lsu_bus_buffer.scala 518:16]
-    buf_ldfwdtag[1] <= _T_4298 @[lsu_bus_buffer.scala 518:16]
-    buf_ldfwdtag[2] <= _T_4300 @[lsu_bus_buffer.scala 518:16]
-    buf_ldfwdtag[3] <= _T_4302 @[lsu_bus_buffer.scala 518:16]
-    node _T_4303 = bits(buf_sideeffect_in, 0, 0) @[lsu_bus_buffer.scala 519:105]
-    node _T_4304 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 519:138]
-    reg _T_4305 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when _T_4304 : @[Reg.scala 28:19]
-      _T_4305 <= _T_4303 @[Reg.scala 28:23]
+    node _T_4303 = cat(_T_4302, _T_4300) @[Cat.scala 29:58]
+    node _T_4304 = cat(_T_4303, _T_4298) @[Cat.scala 29:58]
+    node _T_4305 = cat(_T_4304, _T_4296) @[Cat.scala 29:58]
+    buf_ldfwd <= _T_4305 @[lsu_bus_buffer.scala 520:13]
+    node _T_4306 = bits(buf_ldfwd_en[0], 0, 0) @[lsu_bus_buffer.scala 521:132]
+    reg _T_4307 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4306 : @[Reg.scala 28:19]
+      _T_4307 <= buf_ldfwdtag_in[0] @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    node _T_4306 = bits(buf_sideeffect_in, 1, 1) @[lsu_bus_buffer.scala 519:105]
-    node _T_4307 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 519:138]
-    reg _T_4308 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when _T_4307 : @[Reg.scala 28:19]
-      _T_4308 <= _T_4306 @[Reg.scala 28:23]
+    node _T_4308 = bits(buf_ldfwd_en[1], 0, 0) @[lsu_bus_buffer.scala 521:132]
+    reg _T_4309 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4308 : @[Reg.scala 28:19]
+      _T_4309 <= buf_ldfwdtag_in[1] @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    node _T_4309 = bits(buf_sideeffect_in, 2, 2) @[lsu_bus_buffer.scala 519:105]
-    node _T_4310 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 519:138]
-    reg _T_4311 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    node _T_4310 = bits(buf_ldfwd_en[2], 0, 0) @[lsu_bus_buffer.scala 521:132]
+    reg _T_4311 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
     when _T_4310 : @[Reg.scala 28:19]
-      _T_4311 <= _T_4309 @[Reg.scala 28:23]
+      _T_4311 <= buf_ldfwdtag_in[2] @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    node _T_4312 = bits(buf_sideeffect_in, 3, 3) @[lsu_bus_buffer.scala 519:105]
-    node _T_4313 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 519:138]
-    reg _T_4314 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when _T_4313 : @[Reg.scala 28:19]
-      _T_4314 <= _T_4312 @[Reg.scala 28:23]
+    node _T_4312 = bits(buf_ldfwd_en[3], 0, 0) @[lsu_bus_buffer.scala 521:132]
+    reg _T_4313 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4312 : @[Reg.scala 28:19]
+      _T_4313 <= buf_ldfwdtag_in[3] @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    node _T_4315 = cat(_T_4314, _T_4311) @[Cat.scala 29:58]
-    node _T_4316 = cat(_T_4315, _T_4308) @[Cat.scala 29:58]
-    node _T_4317 = cat(_T_4316, _T_4305) @[Cat.scala 29:58]
-    buf_sideeffect <= _T_4317 @[lsu_bus_buffer.scala 519:18]
-    node _T_4318 = bits(buf_unsign_in, 0, 0) @[lsu_bus_buffer.scala 520:97]
-    node _T_4319 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 520:130]
-    reg _T_4320 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when _T_4319 : @[Reg.scala 28:19]
-      _T_4320 <= _T_4318 @[Reg.scala 28:23]
+    buf_ldfwdtag[0] <= _T_4307 @[lsu_bus_buffer.scala 521:16]
+    buf_ldfwdtag[1] <= _T_4309 @[lsu_bus_buffer.scala 521:16]
+    buf_ldfwdtag[2] <= _T_4311 @[lsu_bus_buffer.scala 521:16]
+    buf_ldfwdtag[3] <= _T_4313 @[lsu_bus_buffer.scala 521:16]
+    node _T_4314 = bits(buf_sideeffect_in, 0, 0) @[lsu_bus_buffer.scala 522:105]
+    node _T_4315 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 522:138]
+    reg _T_4316 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4315 : @[Reg.scala 28:19]
+      _T_4316 <= _T_4314 @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    node _T_4321 = bits(buf_unsign_in, 1, 1) @[lsu_bus_buffer.scala 520:97]
-    node _T_4322 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 520:130]
-    reg _T_4323 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when _T_4322 : @[Reg.scala 28:19]
-      _T_4323 <= _T_4321 @[Reg.scala 28:23]
+    node _T_4317 = bits(buf_sideeffect_in, 1, 1) @[lsu_bus_buffer.scala 522:105]
+    node _T_4318 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 522:138]
+    reg _T_4319 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4318 : @[Reg.scala 28:19]
+      _T_4319 <= _T_4317 @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    node _T_4324 = bits(buf_unsign_in, 2, 2) @[lsu_bus_buffer.scala 520:97]
-    node _T_4325 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 520:130]
-    reg _T_4326 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when _T_4325 : @[Reg.scala 28:19]
-      _T_4326 <= _T_4324 @[Reg.scala 28:23]
+    node _T_4320 = bits(buf_sideeffect_in, 2, 2) @[lsu_bus_buffer.scala 522:105]
+    node _T_4321 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 522:138]
+    reg _T_4322 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4321 : @[Reg.scala 28:19]
+      _T_4322 <= _T_4320 @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    node _T_4327 = bits(buf_unsign_in, 3, 3) @[lsu_bus_buffer.scala 520:97]
-    node _T_4328 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 520:130]
-    reg _T_4329 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when _T_4328 : @[Reg.scala 28:19]
-      _T_4329 <= _T_4327 @[Reg.scala 28:23]
+    node _T_4323 = bits(buf_sideeffect_in, 3, 3) @[lsu_bus_buffer.scala 522:105]
+    node _T_4324 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 522:138]
+    reg _T_4325 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4324 : @[Reg.scala 28:19]
+      _T_4325 <= _T_4323 @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    node _T_4330 = cat(_T_4329, _T_4326) @[Cat.scala 29:58]
-    node _T_4331 = cat(_T_4330, _T_4323) @[Cat.scala 29:58]
-    node _T_4332 = cat(_T_4331, _T_4320) @[Cat.scala 29:58]
-    buf_unsign <= _T_4332 @[lsu_bus_buffer.scala 520:14]
-    node _T_4333 = bits(buf_write_in, 0, 0) @[lsu_bus_buffer.scala 521:95]
-    node _T_4334 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 521:128]
-    reg _T_4335 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when _T_4334 : @[Reg.scala 28:19]
-      _T_4335 <= _T_4333 @[Reg.scala 28:23]
+    node _T_4326 = cat(_T_4325, _T_4322) @[Cat.scala 29:58]
+    node _T_4327 = cat(_T_4326, _T_4319) @[Cat.scala 29:58]
+    node _T_4328 = cat(_T_4327, _T_4316) @[Cat.scala 29:58]
+    buf_sideeffect <= _T_4328 @[lsu_bus_buffer.scala 522:18]
+    node _T_4329 = bits(buf_unsign_in, 0, 0) @[lsu_bus_buffer.scala 523:97]
+    node _T_4330 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 523:130]
+    reg _T_4331 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4330 : @[Reg.scala 28:19]
+      _T_4331 <= _T_4329 @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    node _T_4336 = bits(buf_write_in, 1, 1) @[lsu_bus_buffer.scala 521:95]
-    node _T_4337 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 521:128]
-    reg _T_4338 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when _T_4337 : @[Reg.scala 28:19]
-      _T_4338 <= _T_4336 @[Reg.scala 28:23]
+    node _T_4332 = bits(buf_unsign_in, 1, 1) @[lsu_bus_buffer.scala 523:97]
+    node _T_4333 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 523:130]
+    reg _T_4334 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4333 : @[Reg.scala 28:19]
+      _T_4334 <= _T_4332 @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    node _T_4339 = bits(buf_write_in, 2, 2) @[lsu_bus_buffer.scala 521:95]
-    node _T_4340 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 521:128]
-    reg _T_4341 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when _T_4340 : @[Reg.scala 28:19]
-      _T_4341 <= _T_4339 @[Reg.scala 28:23]
+    node _T_4335 = bits(buf_unsign_in, 2, 2) @[lsu_bus_buffer.scala 523:97]
+    node _T_4336 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 523:130]
+    reg _T_4337 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4336 : @[Reg.scala 28:19]
+      _T_4337 <= _T_4335 @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    node _T_4342 = bits(buf_write_in, 3, 3) @[lsu_bus_buffer.scala 521:95]
-    node _T_4343 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 521:128]
-    reg _T_4344 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when _T_4343 : @[Reg.scala 28:19]
-      _T_4344 <= _T_4342 @[Reg.scala 28:23]
+    node _T_4338 = bits(buf_unsign_in, 3, 3) @[lsu_bus_buffer.scala 523:97]
+    node _T_4339 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 523:130]
+    reg _T_4340 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4339 : @[Reg.scala 28:19]
+      _T_4340 <= _T_4338 @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    node _T_4345 = cat(_T_4344, _T_4341) @[Cat.scala 29:58]
-    node _T_4346 = cat(_T_4345, _T_4338) @[Cat.scala 29:58]
-    node _T_4347 = cat(_T_4346, _T_4335) @[Cat.scala 29:58]
-    buf_write <= _T_4347 @[lsu_bus_buffer.scala 521:13]
-    node _T_4348 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 522:117]
-    reg _T_4349 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    node _T_4341 = cat(_T_4340, _T_4337) @[Cat.scala 29:58]
+    node _T_4342 = cat(_T_4341, _T_4334) @[Cat.scala 29:58]
+    node _T_4343 = cat(_T_4342, _T_4331) @[Cat.scala 29:58]
+    buf_unsign <= _T_4343 @[lsu_bus_buffer.scala 523:14]
+    node _T_4344 = bits(buf_write_in, 0, 0) @[lsu_bus_buffer.scala 524:95]
+    node _T_4345 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 524:128]
+    reg _T_4346 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4345 : @[Reg.scala 28:19]
+      _T_4346 <= _T_4344 @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    node _T_4347 = bits(buf_write_in, 1, 1) @[lsu_bus_buffer.scala 524:95]
+    node _T_4348 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 524:128]
+    reg _T_4349 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
     when _T_4348 : @[Reg.scala 28:19]
-      _T_4349 <= buf_sz_in[0] @[Reg.scala 28:23]
+      _T_4349 <= _T_4347 @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    node _T_4350 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 522:117]
-    reg _T_4351 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when _T_4350 : @[Reg.scala 28:19]
-      _T_4351 <= buf_sz_in[1] @[Reg.scala 28:23]
+    node _T_4350 = bits(buf_write_in, 2, 2) @[lsu_bus_buffer.scala 524:95]
+    node _T_4351 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 524:128]
+    reg _T_4352 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4351 : @[Reg.scala 28:19]
+      _T_4352 <= _T_4350 @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    node _T_4352 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 522:117]
-    reg _T_4353 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when _T_4352 : @[Reg.scala 28:19]
-      _T_4353 <= buf_sz_in[2] @[Reg.scala 28:23]
-      skip @[Reg.scala 28:19]
-    node _T_4354 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 522:117]
-    reg _T_4355 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    node _T_4353 = bits(buf_write_in, 3, 3) @[lsu_bus_buffer.scala 524:95]
+    node _T_4354 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 524:128]
+    reg _T_4355 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
     when _T_4354 : @[Reg.scala 28:19]
-      _T_4355 <= buf_sz_in[3] @[Reg.scala 28:23]
+      _T_4355 <= _T_4353 @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    buf_sz[0] <= _T_4349 @[lsu_bus_buffer.scala 522:10]
-    buf_sz[1] <= _T_4351 @[lsu_bus_buffer.scala 522:10]
-    buf_sz[2] <= _T_4353 @[lsu_bus_buffer.scala 522:10]
-    buf_sz[3] <= _T_4355 @[lsu_bus_buffer.scala 522:10]
-    node _T_4356 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 523:80]
-    inst rvclkhdr_4 of rvclkhdr_36 @[lib.scala 368:23]
+    node _T_4356 = cat(_T_4355, _T_4352) @[Cat.scala 29:58]
+    node _T_4357 = cat(_T_4356, _T_4349) @[Cat.scala 29:58]
+    node _T_4358 = cat(_T_4357, _T_4346) @[Cat.scala 29:58]
+    buf_write <= _T_4358 @[lsu_bus_buffer.scala 524:13]
+    node _T_4359 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 525:117]
+    reg _T_4360 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4359 : @[Reg.scala 28:19]
+      _T_4360 <= buf_sz_in[0] @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    node _T_4361 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 525:117]
+    reg _T_4362 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4361 : @[Reg.scala 28:19]
+      _T_4362 <= buf_sz_in[1] @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    node _T_4363 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 525:117]
+    reg _T_4364 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4363 : @[Reg.scala 28:19]
+      _T_4364 <= buf_sz_in[2] @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    node _T_4365 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 525:117]
+    reg _T_4366 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4365 : @[Reg.scala 28:19]
+      _T_4366 <= buf_sz_in[3] @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    buf_sz[0] <= _T_4360 @[lsu_bus_buffer.scala 525:10]
+    buf_sz[1] <= _T_4362 @[lsu_bus_buffer.scala 525:10]
+    buf_sz[2] <= _T_4364 @[lsu_bus_buffer.scala 525:10]
+    buf_sz[3] <= _T_4366 @[lsu_bus_buffer.scala 525:10]
+    node _T_4367 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 526:80]
+    inst rvclkhdr_4 of rvclkhdr_41 @[lib.scala 390:23]
     rvclkhdr_4.clock <= clock
     rvclkhdr_4.reset <= reset
-    rvclkhdr_4.io.clk <= clock @[lib.scala 370:18]
-    rvclkhdr_4.io.en <= _T_4356 @[lib.scala 371:17]
-    rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
-    reg _T_4357 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
-    _T_4357 <= buf_addr_in[0] @[lib.scala 374:16]
-    node _T_4358 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 523:80]
-    inst rvclkhdr_5 of rvclkhdr_37 @[lib.scala 368:23]
+    rvclkhdr_4.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr_4.io.en <= _T_4367 @[lib.scala 393:17]
+    rvclkhdr_4.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg _T_4368 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4367 : @[Reg.scala 28:19]
+      _T_4368 <= buf_addr_in[0] @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    node _T_4369 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 526:80]
+    inst rvclkhdr_5 of rvclkhdr_42 @[lib.scala 390:23]
     rvclkhdr_5.clock <= clock
     rvclkhdr_5.reset <= reset
-    rvclkhdr_5.io.clk <= clock @[lib.scala 370:18]
-    rvclkhdr_5.io.en <= _T_4358 @[lib.scala 371:17]
-    rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
-    reg _T_4359 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
-    _T_4359 <= buf_addr_in[1] @[lib.scala 374:16]
-    node _T_4360 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 523:80]
-    inst rvclkhdr_6 of rvclkhdr_38 @[lib.scala 368:23]
+    rvclkhdr_5.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr_5.io.en <= _T_4369 @[lib.scala 393:17]
+    rvclkhdr_5.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg _T_4370 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4369 : @[Reg.scala 28:19]
+      _T_4370 <= buf_addr_in[1] @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    node _T_4371 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 526:80]
+    inst rvclkhdr_6 of rvclkhdr_43 @[lib.scala 390:23]
     rvclkhdr_6.clock <= clock
     rvclkhdr_6.reset <= reset
-    rvclkhdr_6.io.clk <= clock @[lib.scala 370:18]
-    rvclkhdr_6.io.en <= _T_4360 @[lib.scala 371:17]
-    rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
-    reg _T_4361 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
-    _T_4361 <= buf_addr_in[2] @[lib.scala 374:16]
-    node _T_4362 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 523:80]
-    inst rvclkhdr_7 of rvclkhdr_39 @[lib.scala 368:23]
+    rvclkhdr_6.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr_6.io.en <= _T_4371 @[lib.scala 393:17]
+    rvclkhdr_6.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg _T_4372 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4371 : @[Reg.scala 28:19]
+      _T_4372 <= buf_addr_in[2] @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    node _T_4373 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 526:80]
+    inst rvclkhdr_7 of rvclkhdr_44 @[lib.scala 390:23]
     rvclkhdr_7.clock <= clock
     rvclkhdr_7.reset <= reset
-    rvclkhdr_7.io.clk <= clock @[lib.scala 370:18]
-    rvclkhdr_7.io.en <= _T_4362 @[lib.scala 371:17]
-    rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
-    reg _T_4363 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
-    _T_4363 <= buf_addr_in[3] @[lib.scala 374:16]
-    buf_addr[0] <= _T_4357 @[lsu_bus_buffer.scala 523:12]
-    buf_addr[1] <= _T_4359 @[lsu_bus_buffer.scala 523:12]
-    buf_addr[2] <= _T_4361 @[lsu_bus_buffer.scala 523:12]
-    buf_addr[3] <= _T_4363 @[lsu_bus_buffer.scala 523:12]
-    node _T_4364 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 524:125]
-    reg _T_4365 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when _T_4364 : @[Reg.scala 28:19]
-      _T_4365 <= buf_byteen_in[0] @[Reg.scala 28:23]
+    rvclkhdr_7.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr_7.io.en <= _T_4373 @[lib.scala 393:17]
+    rvclkhdr_7.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg _T_4374 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4373 : @[Reg.scala 28:19]
+      _T_4374 <= buf_addr_in[3] @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    node _T_4366 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 524:125]
-    reg _T_4367 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when _T_4366 : @[Reg.scala 28:19]
-      _T_4367 <= buf_byteen_in[1] @[Reg.scala 28:23]
+    buf_addr[0] <= _T_4368 @[lsu_bus_buffer.scala 526:12]
+    buf_addr[1] <= _T_4370 @[lsu_bus_buffer.scala 526:12]
+    buf_addr[2] <= _T_4372 @[lsu_bus_buffer.scala 526:12]
+    buf_addr[3] <= _T_4374 @[lsu_bus_buffer.scala 526:12]
+    node _T_4375 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 527:125]
+    reg _T_4376 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4375 : @[Reg.scala 28:19]
+      _T_4376 <= buf_byteen_in[0] @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    node _T_4368 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 524:125]
-    reg _T_4369 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when _T_4368 : @[Reg.scala 28:19]
-      _T_4369 <= buf_byteen_in[2] @[Reg.scala 28:23]
+    node _T_4377 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 527:125]
+    reg _T_4378 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4377 : @[Reg.scala 28:19]
+      _T_4378 <= buf_byteen_in[1] @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    node _T_4370 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 524:125]
-    reg _T_4371 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when _T_4370 : @[Reg.scala 28:19]
-      _T_4371 <= buf_byteen_in[3] @[Reg.scala 28:23]
+    node _T_4379 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 527:125]
+    reg _T_4380 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4379 : @[Reg.scala 28:19]
+      _T_4380 <= buf_byteen_in[2] @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    buf_byteen[0] <= _T_4365 @[lsu_bus_buffer.scala 524:14]
-    buf_byteen[1] <= _T_4367 @[lsu_bus_buffer.scala 524:14]
-    buf_byteen[2] <= _T_4369 @[lsu_bus_buffer.scala 524:14]
-    buf_byteen[3] <= _T_4371 @[lsu_bus_buffer.scala 524:14]
-    inst rvclkhdr_8 of rvclkhdr_40 @[lib.scala 368:23]
+    node _T_4381 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 527:125]
+    reg _T_4382 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4381 : @[Reg.scala 28:19]
+      _T_4382 <= buf_byteen_in[3] @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    buf_byteen[0] <= _T_4376 @[lsu_bus_buffer.scala 527:14]
+    buf_byteen[1] <= _T_4378 @[lsu_bus_buffer.scala 527:14]
+    buf_byteen[2] <= _T_4380 @[lsu_bus_buffer.scala 527:14]
+    buf_byteen[3] <= _T_4382 @[lsu_bus_buffer.scala 527:14]
+    inst rvclkhdr_8 of rvclkhdr_45 @[lib.scala 390:23]
     rvclkhdr_8.clock <= clock
     rvclkhdr_8.reset <= reset
-    rvclkhdr_8.io.clk <= clock @[lib.scala 370:18]
-    rvclkhdr_8.io.en <= buf_data_en[0] @[lib.scala 371:17]
-    rvclkhdr_8.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
-    reg _T_4372 : UInt, rvclkhdr_8.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
-    _T_4372 <= buf_data_in[0] @[lib.scala 374:16]
-    inst rvclkhdr_9 of rvclkhdr_41 @[lib.scala 368:23]
+    rvclkhdr_8.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr_8.io.en <= buf_data_en[0] @[lib.scala 393:17]
+    rvclkhdr_8.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg _T_4383 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when buf_data_en[0] : @[Reg.scala 28:19]
+      _T_4383 <= buf_data_in[0] @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    inst rvclkhdr_9 of rvclkhdr_46 @[lib.scala 390:23]
     rvclkhdr_9.clock <= clock
     rvclkhdr_9.reset <= reset
-    rvclkhdr_9.io.clk <= clock @[lib.scala 370:18]
-    rvclkhdr_9.io.en <= buf_data_en[1] @[lib.scala 371:17]
-    rvclkhdr_9.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
-    reg _T_4373 : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
-    _T_4373 <= buf_data_in[1] @[lib.scala 374:16]
-    inst rvclkhdr_10 of rvclkhdr_42 @[lib.scala 368:23]
+    rvclkhdr_9.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr_9.io.en <= buf_data_en[1] @[lib.scala 393:17]
+    rvclkhdr_9.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg _T_4384 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when buf_data_en[1] : @[Reg.scala 28:19]
+      _T_4384 <= buf_data_in[1] @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    inst rvclkhdr_10 of rvclkhdr_47 @[lib.scala 390:23]
     rvclkhdr_10.clock <= clock
     rvclkhdr_10.reset <= reset
-    rvclkhdr_10.io.clk <= clock @[lib.scala 370:18]
-    rvclkhdr_10.io.en <= buf_data_en[2] @[lib.scala 371:17]
-    rvclkhdr_10.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
-    reg _T_4374 : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
-    _T_4374 <= buf_data_in[2] @[lib.scala 374:16]
-    inst rvclkhdr_11 of rvclkhdr_43 @[lib.scala 368:23]
+    rvclkhdr_10.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr_10.io.en <= buf_data_en[2] @[lib.scala 393:17]
+    rvclkhdr_10.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg _T_4385 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when buf_data_en[2] : @[Reg.scala 28:19]
+      _T_4385 <= buf_data_in[2] @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    inst rvclkhdr_11 of rvclkhdr_48 @[lib.scala 390:23]
     rvclkhdr_11.clock <= clock
     rvclkhdr_11.reset <= reset
-    rvclkhdr_11.io.clk <= clock @[lib.scala 370:18]
-    rvclkhdr_11.io.en <= buf_data_en[3] @[lib.scala 371:17]
-    rvclkhdr_11.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
-    reg _T_4375 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
-    _T_4375 <= buf_data_in[3] @[lib.scala 374:16]
-    buf_data[0] <= _T_4372 @[lsu_bus_buffer.scala 525:12]
-    buf_data[1] <= _T_4373 @[lsu_bus_buffer.scala 525:12]
-    buf_data[2] <= _T_4374 @[lsu_bus_buffer.scala 525:12]
-    buf_data[3] <= _T_4375 @[lsu_bus_buffer.scala 525:12]
-    node _T_4376 = bits(buf_error, 0, 0) @[lsu_bus_buffer.scala 526:119]
-    node _T_4377 = mux(buf_error_en[0], UInt<1>("h01"), _T_4376) @[lsu_bus_buffer.scala 526:84]
-    node _T_4378 = eq(buf_rst[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 526:126]
-    node _T_4379 = and(_T_4377, _T_4378) @[lsu_bus_buffer.scala 526:124]
-    reg _T_4380 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 526:80]
-    _T_4380 <= _T_4379 @[lsu_bus_buffer.scala 526:80]
-    node _T_4381 = bits(buf_error, 1, 1) @[lsu_bus_buffer.scala 526:119]
-    node _T_4382 = mux(buf_error_en[1], UInt<1>("h01"), _T_4381) @[lsu_bus_buffer.scala 526:84]
-    node _T_4383 = eq(buf_rst[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 526:126]
-    node _T_4384 = and(_T_4382, _T_4383) @[lsu_bus_buffer.scala 526:124]
-    reg _T_4385 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 526:80]
-    _T_4385 <= _T_4384 @[lsu_bus_buffer.scala 526:80]
-    node _T_4386 = bits(buf_error, 2, 2) @[lsu_bus_buffer.scala 526:119]
-    node _T_4387 = mux(buf_error_en[2], UInt<1>("h01"), _T_4386) @[lsu_bus_buffer.scala 526:84]
-    node _T_4388 = eq(buf_rst[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 526:126]
-    node _T_4389 = and(_T_4387, _T_4388) @[lsu_bus_buffer.scala 526:124]
-    reg _T_4390 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 526:80]
-    _T_4390 <= _T_4389 @[lsu_bus_buffer.scala 526:80]
-    node _T_4391 = bits(buf_error, 3, 3) @[lsu_bus_buffer.scala 526:119]
-    node _T_4392 = mux(buf_error_en[3], UInt<1>("h01"), _T_4391) @[lsu_bus_buffer.scala 526:84]
-    node _T_4393 = eq(buf_rst[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 526:126]
-    node _T_4394 = and(_T_4392, _T_4393) @[lsu_bus_buffer.scala 526:124]
-    reg _T_4395 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 526:80]
-    _T_4395 <= _T_4394 @[lsu_bus_buffer.scala 526:80]
-    node _T_4396 = cat(_T_4395, _T_4390) @[Cat.scala 29:58]
-    node _T_4397 = cat(_T_4396, _T_4385) @[Cat.scala 29:58]
-    node _T_4398 = cat(_T_4397, _T_4380) @[Cat.scala 29:58]
-    buf_error <= _T_4398 @[lsu_bus_buffer.scala 526:13]
-    node _T_4399 = cat(io.lsu_busreq_m, UInt<1>("h00")) @[Cat.scala 29:58]
-    node _T_4400 = mux(io.ldst_dual_m, _T_4399, io.lsu_busreq_m) @[lsu_bus_buffer.scala 528:28]
-    node _T_4401 = cat(io.lsu_busreq_r, UInt<1>("h00")) @[Cat.scala 29:58]
-    node _T_4402 = mux(io.ldst_dual_r, _T_4401, io.lsu_busreq_r) @[lsu_bus_buffer.scala 528:94]
-    node _T_4403 = add(_T_4400, _T_4402) @[lsu_bus_buffer.scala 528:88]
-    node _T_4404 = add(_T_4403, ibuf_valid) @[lsu_bus_buffer.scala 528:154]
-    node _T_4405 = neq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 528:190]
-    node _T_4406 = neq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 528:190]
-    node _T_4407 = neq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 528:190]
-    node _T_4408 = neq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 528:190]
-    node _T_4409 = add(_T_4405, _T_4406) @[lsu_bus_buffer.scala 528:217]
-    node _T_4410 = add(_T_4409, _T_4407) @[lsu_bus_buffer.scala 528:217]
-    node _T_4411 = add(_T_4410, _T_4408) @[lsu_bus_buffer.scala 528:217]
-    node _T_4412 = add(_T_4404, _T_4411) @[lsu_bus_buffer.scala 528:169]
-    node buf_numvld_any = tail(_T_4412, 1) @[lsu_bus_buffer.scala 528:169]
-    node _T_4413 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 529:60]
-    node _T_4414 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 529:79]
-    node _T_4415 = and(_T_4413, _T_4414) @[lsu_bus_buffer.scala 529:64]
-    node _T_4416 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 529:91]
-    node _T_4417 = and(_T_4415, _T_4416) @[lsu_bus_buffer.scala 529:89]
-    node _T_4418 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 529:60]
-    node _T_4419 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 529:79]
-    node _T_4420 = and(_T_4418, _T_4419) @[lsu_bus_buffer.scala 529:64]
-    node _T_4421 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 529:91]
-    node _T_4422 = and(_T_4420, _T_4421) @[lsu_bus_buffer.scala 529:89]
-    node _T_4423 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 529:60]
-    node _T_4424 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 529:79]
-    node _T_4425 = and(_T_4423, _T_4424) @[lsu_bus_buffer.scala 529:64]
-    node _T_4426 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 529:91]
-    node _T_4427 = and(_T_4425, _T_4426) @[lsu_bus_buffer.scala 529:89]
-    node _T_4428 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 529:60]
-    node _T_4429 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 529:79]
-    node _T_4430 = and(_T_4428, _T_4429) @[lsu_bus_buffer.scala 529:64]
-    node _T_4431 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 529:91]
-    node _T_4432 = and(_T_4430, _T_4431) @[lsu_bus_buffer.scala 529:89]
-    node _T_4433 = add(_T_4432, _T_4427) @[lsu_bus_buffer.scala 529:142]
-    node _T_4434 = add(_T_4433, _T_4422) @[lsu_bus_buffer.scala 529:142]
-    node _T_4435 = add(_T_4434, _T_4417) @[lsu_bus_buffer.scala 529:142]
-    buf_numvld_wrcmd_any <= _T_4435 @[lsu_bus_buffer.scala 529:24]
-    node _T_4436 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 530:63]
-    node _T_4437 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 530:75]
-    node _T_4438 = and(_T_4436, _T_4437) @[lsu_bus_buffer.scala 530:73]
-    node _T_4439 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 530:63]
-    node _T_4440 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 530:75]
-    node _T_4441 = and(_T_4439, _T_4440) @[lsu_bus_buffer.scala 530:73]
-    node _T_4442 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 530:63]
-    node _T_4443 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 530:75]
-    node _T_4444 = and(_T_4442, _T_4443) @[lsu_bus_buffer.scala 530:73]
-    node _T_4445 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 530:63]
-    node _T_4446 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 530:75]
-    node _T_4447 = and(_T_4445, _T_4446) @[lsu_bus_buffer.scala 530:73]
-    node _T_4448 = add(_T_4447, _T_4444) @[lsu_bus_buffer.scala 530:126]
-    node _T_4449 = add(_T_4448, _T_4441) @[lsu_bus_buffer.scala 530:126]
-    node _T_4450 = add(_T_4449, _T_4438) @[lsu_bus_buffer.scala 530:126]
-    buf_numvld_cmd_any <= _T_4450 @[lsu_bus_buffer.scala 530:22]
-    node _T_4451 = eq(buf_state[0], UInt<3>("h01")) @[lsu_bus_buffer.scala 531:63]
-    node _T_4452 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 531:90]
-    node _T_4453 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 531:102]
-    node _T_4454 = and(_T_4452, _T_4453) @[lsu_bus_buffer.scala 531:100]
-    node _T_4455 = or(_T_4451, _T_4454) @[lsu_bus_buffer.scala 531:74]
-    node _T_4456 = eq(buf_state[1], UInt<3>("h01")) @[lsu_bus_buffer.scala 531:63]
-    node _T_4457 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 531:90]
-    node _T_4458 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 531:102]
-    node _T_4459 = and(_T_4457, _T_4458) @[lsu_bus_buffer.scala 531:100]
-    node _T_4460 = or(_T_4456, _T_4459) @[lsu_bus_buffer.scala 531:74]
-    node _T_4461 = eq(buf_state[2], UInt<3>("h01")) @[lsu_bus_buffer.scala 531:63]
-    node _T_4462 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 531:90]
-    node _T_4463 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 531:102]
-    node _T_4464 = and(_T_4462, _T_4463) @[lsu_bus_buffer.scala 531:100]
-    node _T_4465 = or(_T_4461, _T_4464) @[lsu_bus_buffer.scala 531:74]
-    node _T_4466 = eq(buf_state[3], UInt<3>("h01")) @[lsu_bus_buffer.scala 531:63]
-    node _T_4467 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 531:90]
-    node _T_4468 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 531:102]
-    node _T_4469 = and(_T_4467, _T_4468) @[lsu_bus_buffer.scala 531:100]
-    node _T_4470 = or(_T_4466, _T_4469) @[lsu_bus_buffer.scala 531:74]
-    node _T_4471 = add(_T_4470, _T_4465) @[lsu_bus_buffer.scala 531:154]
-    node _T_4472 = add(_T_4471, _T_4460) @[lsu_bus_buffer.scala 531:154]
-    node _T_4473 = add(_T_4472, _T_4455) @[lsu_bus_buffer.scala 531:154]
-    buf_numvld_pend_any <= _T_4473 @[lsu_bus_buffer.scala 531:23]
-    node _T_4474 = eq(buf_state[0], UInt<3>("h05")) @[lsu_bus_buffer.scala 532:61]
-    node _T_4475 = eq(buf_state[1], UInt<3>("h05")) @[lsu_bus_buffer.scala 532:61]
-    node _T_4476 = eq(buf_state[2], UInt<3>("h05")) @[lsu_bus_buffer.scala 532:61]
-    node _T_4477 = eq(buf_state[3], UInt<3>("h05")) @[lsu_bus_buffer.scala 532:61]
-    node _T_4478 = or(_T_4477, _T_4476) @[lsu_bus_buffer.scala 532:93]
-    node _T_4479 = or(_T_4478, _T_4475) @[lsu_bus_buffer.scala 532:93]
-    node _T_4480 = or(_T_4479, _T_4474) @[lsu_bus_buffer.scala 532:93]
-    any_done_wait_state <= _T_4480 @[lsu_bus_buffer.scala 532:23]
-    node _T_4481 = orr(buf_numvld_pend_any) @[lsu_bus_buffer.scala 533:53]
-    io.lsu_bus_buffer_pend_any <= _T_4481 @[lsu_bus_buffer.scala 533:30]
-    node _T_4482 = and(io.ldst_dual_d, io.dec_lsu_valid_raw_d) @[lsu_bus_buffer.scala 534:52]
-    node _T_4483 = geq(buf_numvld_any, UInt<2>("h03")) @[lsu_bus_buffer.scala 534:92]
-    node _T_4484 = eq(buf_numvld_any, UInt<3>("h04")) @[lsu_bus_buffer.scala 534:121]
-    node _T_4485 = mux(_T_4482, _T_4483, _T_4484) @[lsu_bus_buffer.scala 534:36]
-    io.lsu_bus_buffer_full_any <= _T_4485 @[lsu_bus_buffer.scala 534:30]
-    node _T_4486 = orr(buf_state[0]) @[lsu_bus_buffer.scala 535:52]
-    node _T_4487 = orr(buf_state[1]) @[lsu_bus_buffer.scala 535:52]
-    node _T_4488 = orr(buf_state[2]) @[lsu_bus_buffer.scala 535:52]
-    node _T_4489 = orr(buf_state[3]) @[lsu_bus_buffer.scala 535:52]
-    node _T_4490 = or(_T_4486, _T_4487) @[lsu_bus_buffer.scala 535:65]
-    node _T_4491 = or(_T_4490, _T_4488) @[lsu_bus_buffer.scala 535:65]
-    node _T_4492 = or(_T_4491, _T_4489) @[lsu_bus_buffer.scala 535:65]
-    node _T_4493 = eq(_T_4492, UInt<1>("h00")) @[lsu_bus_buffer.scala 535:34]
-    node _T_4494 = eq(ibuf_valid, UInt<1>("h00")) @[lsu_bus_buffer.scala 535:72]
-    node _T_4495 = and(_T_4493, _T_4494) @[lsu_bus_buffer.scala 535:70]
-    node _T_4496 = eq(obuf_valid, UInt<1>("h00")) @[lsu_bus_buffer.scala 535:86]
-    node _T_4497 = and(_T_4495, _T_4496) @[lsu_bus_buffer.scala 535:84]
-    io.lsu_bus_buffer_empty_any <= _T_4497 @[lsu_bus_buffer.scala 535:31]
-    node _T_4498 = and(io.lsu_busreq_m, io.lsu_pkt_m.valid) @[lsu_bus_buffer.scala 537:64]
-    node _T_4499 = and(_T_4498, io.lsu_pkt_m.bits.load) @[lsu_bus_buffer.scala 537:85]
-    node _T_4500 = eq(io.flush_m_up, UInt<1>("h00")) @[lsu_bus_buffer.scala 537:112]
-    node _T_4501 = and(_T_4499, _T_4500) @[lsu_bus_buffer.scala 537:110]
-    node _T_4502 = eq(io.ld_full_hit_m, UInt<1>("h00")) @[lsu_bus_buffer.scala 537:129]
-    node _T_4503 = and(_T_4501, _T_4502) @[lsu_bus_buffer.scala 537:127]
-    io.dctl_busbuff.lsu_nonblock_load_valid_m <= _T_4503 @[lsu_bus_buffer.scala 537:45]
-    io.dctl_busbuff.lsu_nonblock_load_tag_m <= WrPtr0_m @[lsu_bus_buffer.scala 538:43]
+    rvclkhdr_11.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr_11.io.en <= buf_data_en[3] @[lib.scala 393:17]
+    rvclkhdr_11.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg _T_4386 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when buf_data_en[3] : @[Reg.scala 28:19]
+      _T_4386 <= buf_data_in[3] @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    buf_data[0] <= _T_4383 @[lsu_bus_buffer.scala 528:12]
+    buf_data[1] <= _T_4384 @[lsu_bus_buffer.scala 528:12]
+    buf_data[2] <= _T_4385 @[lsu_bus_buffer.scala 528:12]
+    buf_data[3] <= _T_4386 @[lsu_bus_buffer.scala 528:12]
+    node _T_4387 = eq(buf_rst[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 529:81]
+    node _T_4388 = bits(buf_error, 0, 0) @[lsu_bus_buffer.scala 529:133]
+    node _T_4389 = mux(buf_error_en[0], UInt<1>("h01"), _T_4388) @[lsu_bus_buffer.scala 529:98]
+    node _T_4390 = and(_T_4387, _T_4389) @[lsu_bus_buffer.scala 529:93]
+    reg _T_4391 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 529:80]
+    _T_4391 <= _T_4390 @[lsu_bus_buffer.scala 529:80]
+    node _T_4392 = eq(buf_rst[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 529:81]
+    node _T_4393 = bits(buf_error, 1, 1) @[lsu_bus_buffer.scala 529:133]
+    node _T_4394 = mux(buf_error_en[1], UInt<1>("h01"), _T_4393) @[lsu_bus_buffer.scala 529:98]
+    node _T_4395 = and(_T_4392, _T_4394) @[lsu_bus_buffer.scala 529:93]
+    reg _T_4396 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 529:80]
+    _T_4396 <= _T_4395 @[lsu_bus_buffer.scala 529:80]
+    node _T_4397 = eq(buf_rst[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 529:81]
+    node _T_4398 = bits(buf_error, 2, 2) @[lsu_bus_buffer.scala 529:133]
+    node _T_4399 = mux(buf_error_en[2], UInt<1>("h01"), _T_4398) @[lsu_bus_buffer.scala 529:98]
+    node _T_4400 = and(_T_4397, _T_4399) @[lsu_bus_buffer.scala 529:93]
+    reg _T_4401 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 529:80]
+    _T_4401 <= _T_4400 @[lsu_bus_buffer.scala 529:80]
+    node _T_4402 = eq(buf_rst[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 529:81]
+    node _T_4403 = bits(buf_error, 3, 3) @[lsu_bus_buffer.scala 529:133]
+    node _T_4404 = mux(buf_error_en[3], UInt<1>("h01"), _T_4403) @[lsu_bus_buffer.scala 529:98]
+    node _T_4405 = and(_T_4402, _T_4404) @[lsu_bus_buffer.scala 529:93]
+    reg _T_4406 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 529:80]
+    _T_4406 <= _T_4405 @[lsu_bus_buffer.scala 529:80]
+    node _T_4407 = cat(_T_4406, _T_4401) @[Cat.scala 29:58]
+    node _T_4408 = cat(_T_4407, _T_4396) @[Cat.scala 29:58]
+    node _T_4409 = cat(_T_4408, _T_4391) @[Cat.scala 29:58]
+    buf_error <= _T_4409 @[lsu_bus_buffer.scala 529:13]
+    node _T_4410 = cat(io.lsu_busreq_m, UInt<1>("h00")) @[Cat.scala 29:58]
+    node _T_4411 = mux(io.ldst_dual_m, _T_4410, io.lsu_busreq_m) @[lsu_bus_buffer.scala 530:28]
+    node _T_4412 = cat(io.lsu_busreq_r, UInt<1>("h00")) @[Cat.scala 29:58]
+    node _T_4413 = mux(io.ldst_dual_r, _T_4412, io.lsu_busreq_r) @[lsu_bus_buffer.scala 530:94]
+    node _T_4414 = add(_T_4411, _T_4413) @[lsu_bus_buffer.scala 530:88]
+    node _T_4415 = add(_T_4414, ibuf_valid) @[lsu_bus_buffer.scala 530:154]
+    node _T_4416 = neq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 530:190]
+    node _T_4417 = neq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 530:190]
+    node _T_4418 = neq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 530:190]
+    node _T_4419 = neq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 530:190]
+    node _T_4420 = add(_T_4416, _T_4417) @[lsu_bus_buffer.scala 530:217]
+    node _T_4421 = add(_T_4420, _T_4418) @[lsu_bus_buffer.scala 530:217]
+    node _T_4422 = add(_T_4421, _T_4419) @[lsu_bus_buffer.scala 530:217]
+    node _T_4423 = add(_T_4415, _T_4422) @[lsu_bus_buffer.scala 530:169]
+    node buf_numvld_any = tail(_T_4423, 1) @[lsu_bus_buffer.scala 530:169]
+    node _T_4424 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 531:60]
+    node _T_4425 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 531:79]
+    node _T_4426 = and(_T_4424, _T_4425) @[lsu_bus_buffer.scala 531:64]
+    node _T_4427 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 531:91]
+    node _T_4428 = and(_T_4426, _T_4427) @[lsu_bus_buffer.scala 531:89]
+    node _T_4429 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 531:60]
+    node _T_4430 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 531:79]
+    node _T_4431 = and(_T_4429, _T_4430) @[lsu_bus_buffer.scala 531:64]
+    node _T_4432 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 531:91]
+    node _T_4433 = and(_T_4431, _T_4432) @[lsu_bus_buffer.scala 531:89]
+    node _T_4434 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 531:60]
+    node _T_4435 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 531:79]
+    node _T_4436 = and(_T_4434, _T_4435) @[lsu_bus_buffer.scala 531:64]
+    node _T_4437 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 531:91]
+    node _T_4438 = and(_T_4436, _T_4437) @[lsu_bus_buffer.scala 531:89]
+    node _T_4439 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 531:60]
+    node _T_4440 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 531:79]
+    node _T_4441 = and(_T_4439, _T_4440) @[lsu_bus_buffer.scala 531:64]
+    node _T_4442 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 531:91]
+    node _T_4443 = and(_T_4441, _T_4442) @[lsu_bus_buffer.scala 531:89]
+    node _T_4444 = add(_T_4443, _T_4438) @[lsu_bus_buffer.scala 531:142]
+    node _T_4445 = add(_T_4444, _T_4433) @[lsu_bus_buffer.scala 531:142]
+    node _T_4446 = add(_T_4445, _T_4428) @[lsu_bus_buffer.scala 531:142]
+    buf_numvld_wrcmd_any <= _T_4446 @[lsu_bus_buffer.scala 531:24]
+    node _T_4447 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 532:63]
+    node _T_4448 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 532:75]
+    node _T_4449 = and(_T_4447, _T_4448) @[lsu_bus_buffer.scala 532:73]
+    node _T_4450 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 532:63]
+    node _T_4451 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 532:75]
+    node _T_4452 = and(_T_4450, _T_4451) @[lsu_bus_buffer.scala 532:73]
+    node _T_4453 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 532:63]
+    node _T_4454 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 532:75]
+    node _T_4455 = and(_T_4453, _T_4454) @[lsu_bus_buffer.scala 532:73]
+    node _T_4456 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 532:63]
+    node _T_4457 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 532:75]
+    node _T_4458 = and(_T_4456, _T_4457) @[lsu_bus_buffer.scala 532:73]
+    node _T_4459 = add(_T_4458, _T_4455) @[lsu_bus_buffer.scala 532:126]
+    node _T_4460 = add(_T_4459, _T_4452) @[lsu_bus_buffer.scala 532:126]
+    node _T_4461 = add(_T_4460, _T_4449) @[lsu_bus_buffer.scala 532:126]
+    buf_numvld_cmd_any <= _T_4461 @[lsu_bus_buffer.scala 532:22]
+    node _T_4462 = eq(buf_state[0], UInt<3>("h01")) @[lsu_bus_buffer.scala 533:63]
+    node _T_4463 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 533:90]
+    node _T_4464 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 533:102]
+    node _T_4465 = and(_T_4463, _T_4464) @[lsu_bus_buffer.scala 533:100]
+    node _T_4466 = or(_T_4462, _T_4465) @[lsu_bus_buffer.scala 533:74]
+    node _T_4467 = eq(buf_state[1], UInt<3>("h01")) @[lsu_bus_buffer.scala 533:63]
+    node _T_4468 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 533:90]
+    node _T_4469 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 533:102]
+    node _T_4470 = and(_T_4468, _T_4469) @[lsu_bus_buffer.scala 533:100]
+    node _T_4471 = or(_T_4467, _T_4470) @[lsu_bus_buffer.scala 533:74]
+    node _T_4472 = eq(buf_state[2], UInt<3>("h01")) @[lsu_bus_buffer.scala 533:63]
+    node _T_4473 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 533:90]
+    node _T_4474 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 533:102]
+    node _T_4475 = and(_T_4473, _T_4474) @[lsu_bus_buffer.scala 533:100]
+    node _T_4476 = or(_T_4472, _T_4475) @[lsu_bus_buffer.scala 533:74]
+    node _T_4477 = eq(buf_state[3], UInt<3>("h01")) @[lsu_bus_buffer.scala 533:63]
+    node _T_4478 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 533:90]
+    node _T_4479 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 533:102]
+    node _T_4480 = and(_T_4478, _T_4479) @[lsu_bus_buffer.scala 533:100]
+    node _T_4481 = or(_T_4477, _T_4480) @[lsu_bus_buffer.scala 533:74]
+    node _T_4482 = add(_T_4481, _T_4476) @[lsu_bus_buffer.scala 533:154]
+    node _T_4483 = add(_T_4482, _T_4471) @[lsu_bus_buffer.scala 533:154]
+    node _T_4484 = add(_T_4483, _T_4466) @[lsu_bus_buffer.scala 533:154]
+    buf_numvld_pend_any <= _T_4484 @[lsu_bus_buffer.scala 533:23]
+    node _T_4485 = eq(buf_state[0], UInt<3>("h05")) @[lsu_bus_buffer.scala 534:61]
+    node _T_4486 = eq(buf_state[1], UInt<3>("h05")) @[lsu_bus_buffer.scala 534:61]
+    node _T_4487 = eq(buf_state[2], UInt<3>("h05")) @[lsu_bus_buffer.scala 534:61]
+    node _T_4488 = eq(buf_state[3], UInt<3>("h05")) @[lsu_bus_buffer.scala 534:61]
+    node _T_4489 = or(_T_4488, _T_4487) @[lsu_bus_buffer.scala 534:93]
+    node _T_4490 = or(_T_4489, _T_4486) @[lsu_bus_buffer.scala 534:93]
+    node _T_4491 = or(_T_4490, _T_4485) @[lsu_bus_buffer.scala 534:93]
+    any_done_wait_state <= _T_4491 @[lsu_bus_buffer.scala 534:23]
+    node _T_4492 = orr(buf_numvld_pend_any) @[lsu_bus_buffer.scala 535:53]
+    io.lsu_bus_buffer_pend_any <= _T_4492 @[lsu_bus_buffer.scala 535:30]
+    node _T_4493 = and(io.ldst_dual_d, io.dec_lsu_valid_raw_d) @[lsu_bus_buffer.scala 536:52]
+    node _T_4494 = geq(buf_numvld_any, UInt<2>("h03")) @[lsu_bus_buffer.scala 536:92]
+    node _T_4495 = eq(buf_numvld_any, UInt<3>("h04")) @[lsu_bus_buffer.scala 536:121]
+    node _T_4496 = mux(_T_4493, _T_4494, _T_4495) @[lsu_bus_buffer.scala 536:36]
+    io.lsu_bus_buffer_full_any <= _T_4496 @[lsu_bus_buffer.scala 536:30]
+    node _T_4497 = orr(buf_state[0]) @[lsu_bus_buffer.scala 537:52]
+    node _T_4498 = orr(buf_state[1]) @[lsu_bus_buffer.scala 537:52]
+    node _T_4499 = orr(buf_state[2]) @[lsu_bus_buffer.scala 537:52]
+    node _T_4500 = orr(buf_state[3]) @[lsu_bus_buffer.scala 537:52]
+    node _T_4501 = or(_T_4497, _T_4498) @[lsu_bus_buffer.scala 537:65]
+    node _T_4502 = or(_T_4501, _T_4499) @[lsu_bus_buffer.scala 537:65]
+    node _T_4503 = or(_T_4502, _T_4500) @[lsu_bus_buffer.scala 537:65]
+    node _T_4504 = eq(_T_4503, UInt<1>("h00")) @[lsu_bus_buffer.scala 537:34]
+    node _T_4505 = eq(ibuf_valid, UInt<1>("h00")) @[lsu_bus_buffer.scala 537:72]
+    node _T_4506 = and(_T_4504, _T_4505) @[lsu_bus_buffer.scala 537:70]
+    node _T_4507 = eq(obuf_valid, UInt<1>("h00")) @[lsu_bus_buffer.scala 537:86]
+    node _T_4508 = and(_T_4506, _T_4507) @[lsu_bus_buffer.scala 537:84]
+    io.lsu_bus_buffer_empty_any <= _T_4508 @[lsu_bus_buffer.scala 537:31]
+    node _T_4509 = and(io.lsu_busreq_m, io.lsu_pkt_m.valid) @[lsu_bus_buffer.scala 539:64]
+    node _T_4510 = and(_T_4509, io.lsu_pkt_m.bits.load) @[lsu_bus_buffer.scala 539:85]
+    node _T_4511 = eq(io.flush_m_up, UInt<1>("h00")) @[lsu_bus_buffer.scala 539:112]
+    node _T_4512 = and(_T_4510, _T_4511) @[lsu_bus_buffer.scala 539:110]
+    node _T_4513 = eq(io.ld_full_hit_m, UInt<1>("h00")) @[lsu_bus_buffer.scala 539:129]
+    node _T_4514 = and(_T_4512, _T_4513) @[lsu_bus_buffer.scala 539:127]
+    io.dctl_busbuff.lsu_nonblock_load_valid_m <= _T_4514 @[lsu_bus_buffer.scala 539:45]
+    io.dctl_busbuff.lsu_nonblock_load_tag_m <= WrPtr0_m @[lsu_bus_buffer.scala 540:43]
     wire lsu_nonblock_load_valid_r : UInt<1>
     lsu_nonblock_load_valid_r <= UInt<1>("h00")
-    node _T_4504 = eq(io.lsu_commit_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 540:74]
-    node _T_4505 = and(lsu_nonblock_load_valid_r, _T_4504) @[lsu_bus_buffer.scala 540:72]
-    io.dctl_busbuff.lsu_nonblock_load_inv_r <= _T_4505 @[lsu_bus_buffer.scala 540:43]
-    io.dctl_busbuff.lsu_nonblock_load_inv_tag_r <= WrPtr0_r @[lsu_bus_buffer.scala 541:47]
-    node _T_4506 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 542:80]
-    node _T_4507 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 542:106]
-    node _T_4508 = eq(_T_4507, UInt<1>("h00")) @[lsu_bus_buffer.scala 542:95]
-    node _T_4509 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 542:80]
-    node _T_4510 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 542:106]
-    node _T_4511 = eq(_T_4510, UInt<1>("h00")) @[lsu_bus_buffer.scala 542:95]
-    node _T_4512 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 542:80]
-    node _T_4513 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 542:106]
-    node _T_4514 = eq(_T_4513, UInt<1>("h00")) @[lsu_bus_buffer.scala 542:95]
-    node _T_4515 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 542:80]
-    node _T_4516 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 542:106]
-    node _T_4517 = eq(_T_4516, UInt<1>("h00")) @[lsu_bus_buffer.scala 542:95]
-    node _T_4518 = mux(_T_4506, _T_4508, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_4519 = mux(_T_4509, _T_4511, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_4520 = mux(_T_4512, _T_4514, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_4521 = mux(_T_4515, _T_4517, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_4522 = or(_T_4518, _T_4519) @[Mux.scala 27:72]
-    node _T_4523 = or(_T_4522, _T_4520) @[Mux.scala 27:72]
-    node _T_4524 = or(_T_4523, _T_4521) @[Mux.scala 27:72]
+    node _T_4515 = eq(io.lsu_commit_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 542:74]
+    node _T_4516 = and(lsu_nonblock_load_valid_r, _T_4515) @[lsu_bus_buffer.scala 542:72]
+    io.dctl_busbuff.lsu_nonblock_load_inv_r <= _T_4516 @[lsu_bus_buffer.scala 542:43]
+    io.dctl_busbuff.lsu_nonblock_load_inv_tag_r <= WrPtr0_r @[lsu_bus_buffer.scala 543:47]
+    node _T_4517 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 544:80]
+    node _T_4518 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 544:106]
+    node _T_4519 = eq(_T_4518, UInt<1>("h00")) @[lsu_bus_buffer.scala 544:95]
+    node _T_4520 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 544:80]
+    node _T_4521 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 544:106]
+    node _T_4522 = eq(_T_4521, UInt<1>("h00")) @[lsu_bus_buffer.scala 544:95]
+    node _T_4523 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 544:80]
+    node _T_4524 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 544:106]
+    node _T_4525 = eq(_T_4524, UInt<1>("h00")) @[lsu_bus_buffer.scala 544:95]
+    node _T_4526 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 544:80]
+    node _T_4527 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 544:106]
+    node _T_4528 = eq(_T_4527, UInt<1>("h00")) @[lsu_bus_buffer.scala 544:95]
+    node _T_4529 = mux(_T_4517, _T_4519, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_4530 = mux(_T_4520, _T_4522, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_4531 = mux(_T_4523, _T_4525, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_4532 = mux(_T_4526, _T_4528, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_4533 = or(_T_4529, _T_4530) @[Mux.scala 27:72]
+    node _T_4534 = or(_T_4533, _T_4531) @[Mux.scala 27:72]
+    node _T_4535 = or(_T_4534, _T_4532) @[Mux.scala 27:72]
     wire lsu_nonblock_load_data_ready : UInt<1> @[Mux.scala 27:72]
-    lsu_nonblock_load_data_ready <= _T_4524 @[Mux.scala 27:72]
-    node _T_4525 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 543:93]
-    node _T_4526 = bits(buf_error, 0, 0) @[lsu_bus_buffer.scala 543:117]
-    node _T_4527 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 543:133]
-    node _T_4528 = eq(_T_4527, UInt<1>("h00")) @[lsu_bus_buffer.scala 543:123]
-    node _T_4529 = and(_T_4526, _T_4528) @[lsu_bus_buffer.scala 543:121]
-    node _T_4530 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 543:93]
-    node _T_4531 = bits(buf_error, 1, 1) @[lsu_bus_buffer.scala 543:117]
-    node _T_4532 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 543:133]
-    node _T_4533 = eq(_T_4532, UInt<1>("h00")) @[lsu_bus_buffer.scala 543:123]
-    node _T_4534 = and(_T_4531, _T_4533) @[lsu_bus_buffer.scala 543:121]
-    node _T_4535 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 543:93]
-    node _T_4536 = bits(buf_error, 2, 2) @[lsu_bus_buffer.scala 543:117]
-    node _T_4537 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 543:133]
-    node _T_4538 = eq(_T_4537, UInt<1>("h00")) @[lsu_bus_buffer.scala 543:123]
-    node _T_4539 = and(_T_4536, _T_4538) @[lsu_bus_buffer.scala 543:121]
-    node _T_4540 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 543:93]
-    node _T_4541 = bits(buf_error, 3, 3) @[lsu_bus_buffer.scala 543:117]
-    node _T_4542 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 543:133]
-    node _T_4543 = eq(_T_4542, UInt<1>("h00")) @[lsu_bus_buffer.scala 543:123]
-    node _T_4544 = and(_T_4541, _T_4543) @[lsu_bus_buffer.scala 543:121]
-    node _T_4545 = mux(_T_4525, _T_4529, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_4546 = mux(_T_4530, _T_4534, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_4547 = mux(_T_4535, _T_4539, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_4548 = mux(_T_4540, _T_4544, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_4549 = or(_T_4545, _T_4546) @[Mux.scala 27:72]
-    node _T_4550 = or(_T_4549, _T_4547) @[Mux.scala 27:72]
-    node _T_4551 = or(_T_4550, _T_4548) @[Mux.scala 27:72]
-    wire _T_4552 : UInt<1> @[Mux.scala 27:72]
-    _T_4552 <= _T_4551 @[Mux.scala 27:72]
-    io.dctl_busbuff.lsu_nonblock_load_data_error <= _T_4552 @[lsu_bus_buffer.scala 543:48]
-    node _T_4553 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 544:92]
-    node _T_4554 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 544:115]
-    node _T_4555 = eq(_T_4554, UInt<1>("h00")) @[lsu_bus_buffer.scala 544:105]
-    node _T_4556 = and(_T_4553, _T_4555) @[lsu_bus_buffer.scala 544:103]
-    node _T_4557 = eq(buf_dual[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 544:122]
-    node _T_4558 = eq(buf_dualhi[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 544:137]
-    node _T_4559 = or(_T_4557, _T_4558) @[lsu_bus_buffer.scala 544:135]
-    node _T_4560 = and(_T_4556, _T_4559) @[lsu_bus_buffer.scala 544:119]
-    node _T_4561 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 544:92]
-    node _T_4562 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 544:115]
-    node _T_4563 = eq(_T_4562, UInt<1>("h00")) @[lsu_bus_buffer.scala 544:105]
-    node _T_4564 = and(_T_4561, _T_4563) @[lsu_bus_buffer.scala 544:103]
-    node _T_4565 = eq(buf_dual[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 544:122]
-    node _T_4566 = eq(buf_dualhi[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 544:137]
-    node _T_4567 = or(_T_4565, _T_4566) @[lsu_bus_buffer.scala 544:135]
-    node _T_4568 = and(_T_4564, _T_4567) @[lsu_bus_buffer.scala 544:119]
-    node _T_4569 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 544:92]
-    node _T_4570 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 544:115]
-    node _T_4571 = eq(_T_4570, UInt<1>("h00")) @[lsu_bus_buffer.scala 544:105]
-    node _T_4572 = and(_T_4569, _T_4571) @[lsu_bus_buffer.scala 544:103]
-    node _T_4573 = eq(buf_dual[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 544:122]
-    node _T_4574 = eq(buf_dualhi[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 544:137]
-    node _T_4575 = or(_T_4573, _T_4574) @[lsu_bus_buffer.scala 544:135]
-    node _T_4576 = and(_T_4572, _T_4575) @[lsu_bus_buffer.scala 544:119]
-    node _T_4577 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 544:92]
-    node _T_4578 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 544:115]
-    node _T_4579 = eq(_T_4578, UInt<1>("h00")) @[lsu_bus_buffer.scala 544:105]
-    node _T_4580 = and(_T_4577, _T_4579) @[lsu_bus_buffer.scala 544:103]
-    node _T_4581 = eq(buf_dual[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 544:122]
-    node _T_4582 = eq(buf_dualhi[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 544:137]
-    node _T_4583 = or(_T_4581, _T_4582) @[lsu_bus_buffer.scala 544:135]
-    node _T_4584 = and(_T_4580, _T_4583) @[lsu_bus_buffer.scala 544:119]
-    node _T_4585 = mux(_T_4560, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_4586 = mux(_T_4568, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_4587 = mux(_T_4576, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_4588 = mux(_T_4584, UInt<2>("h03"), UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_4589 = or(_T_4585, _T_4586) @[Mux.scala 27:72]
-    node _T_4590 = or(_T_4589, _T_4587) @[Mux.scala 27:72]
-    node _T_4591 = or(_T_4590, _T_4588) @[Mux.scala 27:72]
-    wire _T_4592 : UInt<2> @[Mux.scala 27:72]
-    _T_4592 <= _T_4591 @[Mux.scala 27:72]
-    io.dctl_busbuff.lsu_nonblock_load_data_tag <= _T_4592 @[lsu_bus_buffer.scala 544:46]
-    node _T_4593 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 545:78]
-    node _T_4594 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 545:101]
-    node _T_4595 = eq(_T_4594, UInt<1>("h00")) @[lsu_bus_buffer.scala 545:91]
-    node _T_4596 = and(_T_4593, _T_4595) @[lsu_bus_buffer.scala 545:89]
-    node _T_4597 = eq(buf_dual[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 545:108]
-    node _T_4598 = eq(buf_dualhi[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 545:123]
-    node _T_4599 = or(_T_4597, _T_4598) @[lsu_bus_buffer.scala 545:121]
-    node _T_4600 = and(_T_4596, _T_4599) @[lsu_bus_buffer.scala 545:105]
-    node _T_4601 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 545:78]
-    node _T_4602 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 545:101]
-    node _T_4603 = eq(_T_4602, UInt<1>("h00")) @[lsu_bus_buffer.scala 545:91]
-    node _T_4604 = and(_T_4601, _T_4603) @[lsu_bus_buffer.scala 545:89]
-    node _T_4605 = eq(buf_dual[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 545:108]
-    node _T_4606 = eq(buf_dualhi[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 545:123]
-    node _T_4607 = or(_T_4605, _T_4606) @[lsu_bus_buffer.scala 545:121]
-    node _T_4608 = and(_T_4604, _T_4607) @[lsu_bus_buffer.scala 545:105]
-    node _T_4609 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 545:78]
-    node _T_4610 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 545:101]
-    node _T_4611 = eq(_T_4610, UInt<1>("h00")) @[lsu_bus_buffer.scala 545:91]
-    node _T_4612 = and(_T_4609, _T_4611) @[lsu_bus_buffer.scala 545:89]
-    node _T_4613 = eq(buf_dual[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 545:108]
-    node _T_4614 = eq(buf_dualhi[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 545:123]
-    node _T_4615 = or(_T_4613, _T_4614) @[lsu_bus_buffer.scala 545:121]
-    node _T_4616 = and(_T_4612, _T_4615) @[lsu_bus_buffer.scala 545:105]
-    node _T_4617 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 545:78]
-    node _T_4618 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 545:101]
-    node _T_4619 = eq(_T_4618, UInt<1>("h00")) @[lsu_bus_buffer.scala 545:91]
-    node _T_4620 = and(_T_4617, _T_4619) @[lsu_bus_buffer.scala 545:89]
-    node _T_4621 = eq(buf_dual[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 545:108]
-    node _T_4622 = eq(buf_dualhi[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 545:123]
-    node _T_4623 = or(_T_4621, _T_4622) @[lsu_bus_buffer.scala 545:121]
-    node _T_4624 = and(_T_4620, _T_4623) @[lsu_bus_buffer.scala 545:105]
-    node _T_4625 = mux(_T_4600, buf_data[0], UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_4626 = mux(_T_4608, buf_data[1], UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_4627 = mux(_T_4616, buf_data[2], UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_4628 = mux(_T_4624, buf_data[3], UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_4629 = or(_T_4625, _T_4626) @[Mux.scala 27:72]
-    node _T_4630 = or(_T_4629, _T_4627) @[Mux.scala 27:72]
-    node _T_4631 = or(_T_4630, _T_4628) @[Mux.scala 27:72]
+    lsu_nonblock_load_data_ready <= _T_4535 @[Mux.scala 27:72]
+    node _T_4536 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 545:93]
+    node _T_4537 = bits(buf_error, 0, 0) @[lsu_bus_buffer.scala 545:117]
+    node _T_4538 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 545:133]
+    node _T_4539 = eq(_T_4538, UInt<1>("h00")) @[lsu_bus_buffer.scala 545:123]
+    node _T_4540 = and(_T_4537, _T_4539) @[lsu_bus_buffer.scala 545:121]
+    node _T_4541 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 545:93]
+    node _T_4542 = bits(buf_error, 1, 1) @[lsu_bus_buffer.scala 545:117]
+    node _T_4543 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 545:133]
+    node _T_4544 = eq(_T_4543, UInt<1>("h00")) @[lsu_bus_buffer.scala 545:123]
+    node _T_4545 = and(_T_4542, _T_4544) @[lsu_bus_buffer.scala 545:121]
+    node _T_4546 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 545:93]
+    node _T_4547 = bits(buf_error, 2, 2) @[lsu_bus_buffer.scala 545:117]
+    node _T_4548 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 545:133]
+    node _T_4549 = eq(_T_4548, UInt<1>("h00")) @[lsu_bus_buffer.scala 545:123]
+    node _T_4550 = and(_T_4547, _T_4549) @[lsu_bus_buffer.scala 545:121]
+    node _T_4551 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 545:93]
+    node _T_4552 = bits(buf_error, 3, 3) @[lsu_bus_buffer.scala 545:117]
+    node _T_4553 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 545:133]
+    node _T_4554 = eq(_T_4553, UInt<1>("h00")) @[lsu_bus_buffer.scala 545:123]
+    node _T_4555 = and(_T_4552, _T_4554) @[lsu_bus_buffer.scala 545:121]
+    node _T_4556 = mux(_T_4536, _T_4540, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_4557 = mux(_T_4541, _T_4545, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_4558 = mux(_T_4546, _T_4550, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_4559 = mux(_T_4551, _T_4555, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_4560 = or(_T_4556, _T_4557) @[Mux.scala 27:72]
+    node _T_4561 = or(_T_4560, _T_4558) @[Mux.scala 27:72]
+    node _T_4562 = or(_T_4561, _T_4559) @[Mux.scala 27:72]
+    wire _T_4563 : UInt<1> @[Mux.scala 27:72]
+    _T_4563 <= _T_4562 @[Mux.scala 27:72]
+    io.dctl_busbuff.lsu_nonblock_load_data_error <= _T_4563 @[lsu_bus_buffer.scala 545:48]
+    node _T_4564 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 546:91]
+    node _T_4565 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 546:114]
+    node _T_4566 = eq(_T_4565, UInt<1>("h00")) @[lsu_bus_buffer.scala 546:104]
+    node _T_4567 = and(_T_4564, _T_4566) @[lsu_bus_buffer.scala 546:102]
+    node _T_4568 = eq(buf_dual[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 546:121]
+    node _T_4569 = eq(buf_dualhi[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 546:136]
+    node _T_4570 = or(_T_4568, _T_4569) @[lsu_bus_buffer.scala 546:134]
+    node _T_4571 = and(_T_4567, _T_4570) @[lsu_bus_buffer.scala 546:118]
+    node _T_4572 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 546:91]
+    node _T_4573 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 546:114]
+    node _T_4574 = eq(_T_4573, UInt<1>("h00")) @[lsu_bus_buffer.scala 546:104]
+    node _T_4575 = and(_T_4572, _T_4574) @[lsu_bus_buffer.scala 546:102]
+    node _T_4576 = eq(buf_dual[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 546:121]
+    node _T_4577 = eq(buf_dualhi[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 546:136]
+    node _T_4578 = or(_T_4576, _T_4577) @[lsu_bus_buffer.scala 546:134]
+    node _T_4579 = and(_T_4575, _T_4578) @[lsu_bus_buffer.scala 546:118]
+    node _T_4580 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 546:91]
+    node _T_4581 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 546:114]
+    node _T_4582 = eq(_T_4581, UInt<1>("h00")) @[lsu_bus_buffer.scala 546:104]
+    node _T_4583 = and(_T_4580, _T_4582) @[lsu_bus_buffer.scala 546:102]
+    node _T_4584 = eq(buf_dual[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 546:121]
+    node _T_4585 = eq(buf_dualhi[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 546:136]
+    node _T_4586 = or(_T_4584, _T_4585) @[lsu_bus_buffer.scala 546:134]
+    node _T_4587 = and(_T_4583, _T_4586) @[lsu_bus_buffer.scala 546:118]
+    node _T_4588 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 546:91]
+    node _T_4589 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 546:114]
+    node _T_4590 = eq(_T_4589, UInt<1>("h00")) @[lsu_bus_buffer.scala 546:104]
+    node _T_4591 = and(_T_4588, _T_4590) @[lsu_bus_buffer.scala 546:102]
+    node _T_4592 = eq(buf_dual[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 546:121]
+    node _T_4593 = eq(buf_dualhi[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 546:136]
+    node _T_4594 = or(_T_4592, _T_4593) @[lsu_bus_buffer.scala 546:134]
+    node _T_4595 = and(_T_4591, _T_4594) @[lsu_bus_buffer.scala 546:118]
+    node _T_4596 = mux(_T_4571, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_4597 = mux(_T_4579, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_4598 = mux(_T_4587, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_4599 = mux(_T_4595, UInt<2>("h03"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_4600 = or(_T_4596, _T_4597) @[Mux.scala 27:72]
+    node _T_4601 = or(_T_4600, _T_4598) @[Mux.scala 27:72]
+    node _T_4602 = or(_T_4601, _T_4599) @[Mux.scala 27:72]
+    wire _T_4603 : UInt<2> @[Mux.scala 27:72]
+    _T_4603 <= _T_4602 @[Mux.scala 27:72]
+    io.dctl_busbuff.lsu_nonblock_load_data_tag <= _T_4603 @[lsu_bus_buffer.scala 546:45]
+    node _T_4604 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 547:78]
+    node _T_4605 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 547:101]
+    node _T_4606 = eq(_T_4605, UInt<1>("h00")) @[lsu_bus_buffer.scala 547:91]
+    node _T_4607 = and(_T_4604, _T_4606) @[lsu_bus_buffer.scala 547:89]
+    node _T_4608 = eq(buf_dual[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 547:108]
+    node _T_4609 = eq(buf_dualhi[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 547:123]
+    node _T_4610 = or(_T_4608, _T_4609) @[lsu_bus_buffer.scala 547:121]
+    node _T_4611 = and(_T_4607, _T_4610) @[lsu_bus_buffer.scala 547:105]
+    node _T_4612 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 547:78]
+    node _T_4613 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 547:101]
+    node _T_4614 = eq(_T_4613, UInt<1>("h00")) @[lsu_bus_buffer.scala 547:91]
+    node _T_4615 = and(_T_4612, _T_4614) @[lsu_bus_buffer.scala 547:89]
+    node _T_4616 = eq(buf_dual[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 547:108]
+    node _T_4617 = eq(buf_dualhi[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 547:123]
+    node _T_4618 = or(_T_4616, _T_4617) @[lsu_bus_buffer.scala 547:121]
+    node _T_4619 = and(_T_4615, _T_4618) @[lsu_bus_buffer.scala 547:105]
+    node _T_4620 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 547:78]
+    node _T_4621 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 547:101]
+    node _T_4622 = eq(_T_4621, UInt<1>("h00")) @[lsu_bus_buffer.scala 547:91]
+    node _T_4623 = and(_T_4620, _T_4622) @[lsu_bus_buffer.scala 547:89]
+    node _T_4624 = eq(buf_dual[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 547:108]
+    node _T_4625 = eq(buf_dualhi[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 547:123]
+    node _T_4626 = or(_T_4624, _T_4625) @[lsu_bus_buffer.scala 547:121]
+    node _T_4627 = and(_T_4623, _T_4626) @[lsu_bus_buffer.scala 547:105]
+    node _T_4628 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 547:78]
+    node _T_4629 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 547:101]
+    node _T_4630 = eq(_T_4629, UInt<1>("h00")) @[lsu_bus_buffer.scala 547:91]
+    node _T_4631 = and(_T_4628, _T_4630) @[lsu_bus_buffer.scala 547:89]
+    node _T_4632 = eq(buf_dual[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 547:108]
+    node _T_4633 = eq(buf_dualhi[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 547:123]
+    node _T_4634 = or(_T_4632, _T_4633) @[lsu_bus_buffer.scala 547:121]
+    node _T_4635 = and(_T_4631, _T_4634) @[lsu_bus_buffer.scala 547:105]
+    node _T_4636 = mux(_T_4611, buf_data[0], UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_4637 = mux(_T_4619, buf_data[1], UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_4638 = mux(_T_4627, buf_data[2], UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_4639 = mux(_T_4635, buf_data[3], UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_4640 = or(_T_4636, _T_4637) @[Mux.scala 27:72]
+    node _T_4641 = or(_T_4640, _T_4638) @[Mux.scala 27:72]
+    node _T_4642 = or(_T_4641, _T_4639) @[Mux.scala 27:72]
     wire lsu_nonblock_load_data_lo : UInt<32> @[Mux.scala 27:72]
-    lsu_nonblock_load_data_lo <= _T_4631 @[Mux.scala 27:72]
-    node _T_4632 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 546:78]
-    node _T_4633 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 546:101]
-    node _T_4634 = eq(_T_4633, UInt<1>("h00")) @[lsu_bus_buffer.scala 546:91]
-    node _T_4635 = and(_T_4632, _T_4634) @[lsu_bus_buffer.scala 546:89]
-    node _T_4636 = and(buf_dual[0], buf_dualhi[0]) @[lsu_bus_buffer.scala 546:120]
-    node _T_4637 = and(_T_4635, _T_4636) @[lsu_bus_buffer.scala 546:105]
-    node _T_4638 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 546:78]
-    node _T_4639 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 546:101]
-    node _T_4640 = eq(_T_4639, UInt<1>("h00")) @[lsu_bus_buffer.scala 546:91]
-    node _T_4641 = and(_T_4638, _T_4640) @[lsu_bus_buffer.scala 546:89]
-    node _T_4642 = and(buf_dual[1], buf_dualhi[1]) @[lsu_bus_buffer.scala 546:120]
-    node _T_4643 = and(_T_4641, _T_4642) @[lsu_bus_buffer.scala 546:105]
-    node _T_4644 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 546:78]
-    node _T_4645 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 546:101]
-    node _T_4646 = eq(_T_4645, UInt<1>("h00")) @[lsu_bus_buffer.scala 546:91]
-    node _T_4647 = and(_T_4644, _T_4646) @[lsu_bus_buffer.scala 546:89]
-    node _T_4648 = and(buf_dual[2], buf_dualhi[2]) @[lsu_bus_buffer.scala 546:120]
-    node _T_4649 = and(_T_4647, _T_4648) @[lsu_bus_buffer.scala 546:105]
-    node _T_4650 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 546:78]
-    node _T_4651 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 546:101]
-    node _T_4652 = eq(_T_4651, UInt<1>("h00")) @[lsu_bus_buffer.scala 546:91]
-    node _T_4653 = and(_T_4650, _T_4652) @[lsu_bus_buffer.scala 546:89]
-    node _T_4654 = and(buf_dual[3], buf_dualhi[3]) @[lsu_bus_buffer.scala 546:120]
-    node _T_4655 = and(_T_4653, _T_4654) @[lsu_bus_buffer.scala 546:105]
-    node _T_4656 = mux(_T_4637, buf_data[0], UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_4657 = mux(_T_4643, buf_data[1], UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_4658 = mux(_T_4649, buf_data[2], UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_4659 = mux(_T_4655, buf_data[3], UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_4660 = or(_T_4656, _T_4657) @[Mux.scala 27:72]
-    node _T_4661 = or(_T_4660, _T_4658) @[Mux.scala 27:72]
-    node _T_4662 = or(_T_4661, _T_4659) @[Mux.scala 27:72]
-    wire lsu_nonblock_load_data_hi : UInt<32> @[Mux.scala 27:72]
-    lsu_nonblock_load_data_hi <= _T_4662 @[Mux.scala 27:72]
-    node _T_4663 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 61:123]
-    node _T_4664 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 61:123]
-    node _T_4665 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 61:123]
-    node _T_4666 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 61:123]
-    node _T_4667 = mux(_T_4663, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_4668 = mux(_T_4664, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_4669 = mux(_T_4665, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_4670 = mux(_T_4666, buf_addr[3], UInt<1>("h00")) @[Mux.scala 27:72]
+    lsu_nonblock_load_data_lo <= _T_4642 @[Mux.scala 27:72]
+    node _T_4643 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 548:78]
+    node _T_4644 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 548:101]
+    node _T_4645 = eq(_T_4644, UInt<1>("h00")) @[lsu_bus_buffer.scala 548:91]
+    node _T_4646 = and(_T_4643, _T_4645) @[lsu_bus_buffer.scala 548:89]
+    node _T_4647 = and(buf_dual[0], buf_dualhi[0]) @[lsu_bus_buffer.scala 548:120]
+    node _T_4648 = and(_T_4646, _T_4647) @[lsu_bus_buffer.scala 548:105]
+    node _T_4649 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 548:78]
+    node _T_4650 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 548:101]
+    node _T_4651 = eq(_T_4650, UInt<1>("h00")) @[lsu_bus_buffer.scala 548:91]
+    node _T_4652 = and(_T_4649, _T_4651) @[lsu_bus_buffer.scala 548:89]
+    node _T_4653 = and(buf_dual[1], buf_dualhi[1]) @[lsu_bus_buffer.scala 548:120]
+    node _T_4654 = and(_T_4652, _T_4653) @[lsu_bus_buffer.scala 548:105]
+    node _T_4655 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 548:78]
+    node _T_4656 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 548:101]
+    node _T_4657 = eq(_T_4656, UInt<1>("h00")) @[lsu_bus_buffer.scala 548:91]
+    node _T_4658 = and(_T_4655, _T_4657) @[lsu_bus_buffer.scala 548:89]
+    node _T_4659 = and(buf_dual[2], buf_dualhi[2]) @[lsu_bus_buffer.scala 548:120]
+    node _T_4660 = and(_T_4658, _T_4659) @[lsu_bus_buffer.scala 548:105]
+    node _T_4661 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 548:78]
+    node _T_4662 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 548:101]
+    node _T_4663 = eq(_T_4662, UInt<1>("h00")) @[lsu_bus_buffer.scala 548:91]
+    node _T_4664 = and(_T_4661, _T_4663) @[lsu_bus_buffer.scala 548:89]
+    node _T_4665 = and(buf_dual[3], buf_dualhi[3]) @[lsu_bus_buffer.scala 548:120]
+    node _T_4666 = and(_T_4664, _T_4665) @[lsu_bus_buffer.scala 548:105]
+    node _T_4667 = mux(_T_4648, buf_data[0], UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_4668 = mux(_T_4654, buf_data[1], UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_4669 = mux(_T_4660, buf_data[2], UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_4670 = mux(_T_4666, buf_data[3], UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_4671 = or(_T_4667, _T_4668) @[Mux.scala 27:72]
     node _T_4672 = or(_T_4671, _T_4669) @[Mux.scala 27:72]
     node _T_4673 = or(_T_4672, _T_4670) @[Mux.scala 27:72]
-    wire _T_4674 : UInt<32> @[Mux.scala 27:72]
-    _T_4674 <= _T_4673 @[Mux.scala 27:72]
-    node lsu_nonblock_addr_offset = bits(_T_4674, 1, 0) @[lsu_bus_buffer.scala 547:96]
-    node _T_4675 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 61:123]
-    node _T_4676 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 61:123]
-    node _T_4677 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 61:123]
-    node _T_4678 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 61:123]
-    node _T_4679 = mux(_T_4675, buf_sz[0], UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_4680 = mux(_T_4676, buf_sz[1], UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_4681 = mux(_T_4677, buf_sz[2], UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_4682 = mux(_T_4678, buf_sz[3], UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_4683 = or(_T_4679, _T_4680) @[Mux.scala 27:72]
+    wire lsu_nonblock_load_data_hi : UInt<32> @[Mux.scala 27:72]
+    lsu_nonblock_load_data_hi <= _T_4673 @[Mux.scala 27:72]
+    node _T_4674 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 61:123]
+    node _T_4675 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 61:123]
+    node _T_4676 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 61:123]
+    node _T_4677 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 61:123]
+    node _T_4678 = mux(_T_4674, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_4679 = mux(_T_4675, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_4680 = mux(_T_4676, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_4681 = mux(_T_4677, buf_addr[3], UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_4682 = or(_T_4678, _T_4679) @[Mux.scala 27:72]
+    node _T_4683 = or(_T_4682, _T_4680) @[Mux.scala 27:72]
     node _T_4684 = or(_T_4683, _T_4681) @[Mux.scala 27:72]
-    node _T_4685 = or(_T_4684, _T_4682) @[Mux.scala 27:72]
+    wire _T_4685 : UInt<32> @[Mux.scala 27:72]
+    _T_4685 <= _T_4684 @[Mux.scala 27:72]
+    node lsu_nonblock_addr_offset = bits(_T_4685, 1, 0) @[lsu_bus_buffer.scala 549:96]
+    node _T_4686 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 61:123]
+    node _T_4687 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 61:123]
+    node _T_4688 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 61:123]
+    node _T_4689 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 61:123]
+    node _T_4690 = mux(_T_4686, buf_sz[0], UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_4691 = mux(_T_4687, buf_sz[1], UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_4692 = mux(_T_4688, buf_sz[2], UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_4693 = mux(_T_4689, buf_sz[3], UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_4694 = or(_T_4690, _T_4691) @[Mux.scala 27:72]
+    node _T_4695 = or(_T_4694, _T_4692) @[Mux.scala 27:72]
+    node _T_4696 = or(_T_4695, _T_4693) @[Mux.scala 27:72]
     wire lsu_nonblock_sz : UInt<2> @[Mux.scala 27:72]
-    lsu_nonblock_sz <= _T_4685 @[Mux.scala 27:72]
-    node _T_4686 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 60:118]
-    node _T_4687 = bits(buf_unsign, 0, 0) @[lsu_bus_buffer.scala 60:129]
-    node _T_4688 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 60:118]
-    node _T_4689 = bits(buf_unsign, 1, 1) @[lsu_bus_buffer.scala 60:129]
-    node _T_4690 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 60:118]
-    node _T_4691 = bits(buf_unsign, 2, 2) @[lsu_bus_buffer.scala 60:129]
-    node _T_4692 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 60:118]
-    node _T_4693 = bits(buf_unsign, 3, 3) @[lsu_bus_buffer.scala 60:129]
-    node _T_4694 = mux(_T_4686, _T_4687, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_4695 = mux(_T_4688, _T_4689, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_4696 = mux(_T_4690, _T_4691, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_4697 = mux(_T_4692, _T_4693, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_4698 = or(_T_4694, _T_4695) @[Mux.scala 27:72]
-    node _T_4699 = or(_T_4698, _T_4696) @[Mux.scala 27:72]
-    node _T_4700 = or(_T_4699, _T_4697) @[Mux.scala 27:72]
+    lsu_nonblock_sz <= _T_4696 @[Mux.scala 27:72]
+    node _T_4697 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 60:118]
+    node _T_4698 = bits(buf_unsign, 0, 0) @[lsu_bus_buffer.scala 60:129]
+    node _T_4699 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 60:118]
+    node _T_4700 = bits(buf_unsign, 1, 1) @[lsu_bus_buffer.scala 60:129]
+    node _T_4701 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 60:118]
+    node _T_4702 = bits(buf_unsign, 2, 2) @[lsu_bus_buffer.scala 60:129]
+    node _T_4703 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 60:118]
+    node _T_4704 = bits(buf_unsign, 3, 3) @[lsu_bus_buffer.scala 60:129]
+    node _T_4705 = mux(_T_4697, _T_4698, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_4706 = mux(_T_4699, _T_4700, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_4707 = mux(_T_4701, _T_4702, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_4708 = mux(_T_4703, _T_4704, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_4709 = or(_T_4705, _T_4706) @[Mux.scala 27:72]
+    node _T_4710 = or(_T_4709, _T_4707) @[Mux.scala 27:72]
+    node _T_4711 = or(_T_4710, _T_4708) @[Mux.scala 27:72]
     wire lsu_nonblock_unsign : UInt<1> @[Mux.scala 27:72]
-    lsu_nonblock_unsign <= _T_4700 @[Mux.scala 27:72]
-    node _T_4701 = cat(lsu_nonblock_load_data_hi, lsu_nonblock_load_data_lo) @[Cat.scala 29:58]
-    node _T_4702 = mul(lsu_nonblock_addr_offset, UInt<4>("h08")) @[lsu_bus_buffer.scala 551:121]
-    node lsu_nonblock_data_unalgn = dshr(_T_4701, _T_4702) @[lsu_bus_buffer.scala 551:92]
-    node _T_4703 = eq(io.dctl_busbuff.lsu_nonblock_load_data_error, UInt<1>("h00")) @[lsu_bus_buffer.scala 553:82]
-    node _T_4704 = and(lsu_nonblock_load_data_ready, _T_4703) @[lsu_bus_buffer.scala 553:80]
-    io.dctl_busbuff.lsu_nonblock_load_data_valid <= _T_4704 @[lsu_bus_buffer.scala 553:48]
-    node _T_4705 = eq(lsu_nonblock_sz, UInt<1>("h00")) @[lsu_bus_buffer.scala 554:94]
-    node _T_4706 = and(lsu_nonblock_unsign, _T_4705) @[lsu_bus_buffer.scala 554:76]
-    node _T_4707 = bits(lsu_nonblock_data_unalgn, 7, 0) @[lsu_bus_buffer.scala 554:144]
-    node _T_4708 = cat(UInt<24>("h00"), _T_4707) @[Cat.scala 29:58]
-    node _T_4709 = eq(lsu_nonblock_sz, UInt<1>("h01")) @[lsu_bus_buffer.scala 555:45]
-    node _T_4710 = and(lsu_nonblock_unsign, _T_4709) @[lsu_bus_buffer.scala 555:26]
-    node _T_4711 = bits(lsu_nonblock_data_unalgn, 15, 0) @[lsu_bus_buffer.scala 555:95]
-    node _T_4712 = cat(UInt<16>("h00"), _T_4711) @[Cat.scala 29:58]
-    node _T_4713 = eq(lsu_nonblock_unsign, UInt<1>("h00")) @[lsu_bus_buffer.scala 556:6]
-    node _T_4714 = eq(lsu_nonblock_sz, UInt<1>("h00")) @[lsu_bus_buffer.scala 556:45]
-    node _T_4715 = and(_T_4713, _T_4714) @[lsu_bus_buffer.scala 556:27]
-    node _T_4716 = bits(lsu_nonblock_data_unalgn, 7, 7) @[lsu_bus_buffer.scala 556:93]
-    node _T_4717 = bits(_T_4716, 0, 0) @[Bitwise.scala 72:15]
-    node _T_4718 = mux(_T_4717, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12]
-    node _T_4719 = bits(lsu_nonblock_data_unalgn, 7, 0) @[lsu_bus_buffer.scala 556:123]
-    node _T_4720 = cat(_T_4718, _T_4719) @[Cat.scala 29:58]
-    node _T_4721 = eq(lsu_nonblock_unsign, UInt<1>("h00")) @[lsu_bus_buffer.scala 557:6]
-    node _T_4722 = eq(lsu_nonblock_sz, UInt<1>("h01")) @[lsu_bus_buffer.scala 557:45]
-    node _T_4723 = and(_T_4721, _T_4722) @[lsu_bus_buffer.scala 557:27]
-    node _T_4724 = bits(lsu_nonblock_data_unalgn, 15, 15) @[lsu_bus_buffer.scala 557:93]
-    node _T_4725 = bits(_T_4724, 0, 0) @[Bitwise.scala 72:15]
-    node _T_4726 = mux(_T_4725, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12]
-    node _T_4727 = bits(lsu_nonblock_data_unalgn, 15, 0) @[lsu_bus_buffer.scala 557:124]
-    node _T_4728 = cat(_T_4726, _T_4727) @[Cat.scala 29:58]
-    node _T_4729 = eq(lsu_nonblock_sz, UInt<2>("h02")) @[lsu_bus_buffer.scala 558:21]
-    node _T_4730 = mux(_T_4706, _T_4708, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_4731 = mux(_T_4710, _T_4712, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_4732 = mux(_T_4715, _T_4720, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_4733 = mux(_T_4723, _T_4728, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_4734 = mux(_T_4729, lsu_nonblock_data_unalgn, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_4735 = or(_T_4730, _T_4731) @[Mux.scala 27:72]
-    node _T_4736 = or(_T_4735, _T_4732) @[Mux.scala 27:72]
-    node _T_4737 = or(_T_4736, _T_4733) @[Mux.scala 27:72]
-    node _T_4738 = or(_T_4737, _T_4734) @[Mux.scala 27:72]
-    wire _T_4739 : UInt<64> @[Mux.scala 27:72]
-    _T_4739 <= _T_4738 @[Mux.scala 27:72]
-    io.dctl_busbuff.lsu_nonblock_load_data <= _T_4739 @[lsu_bus_buffer.scala 554:42]
-    node _T_4740 = eq(buf_state[0], UInt<3>("h03")) @[lsu_bus_buffer.scala 559:62]
-    node _T_4741 = bits(buf_sideeffect, 0, 0) @[lsu_bus_buffer.scala 559:89]
-    node _T_4742 = and(_T_4740, _T_4741) @[lsu_bus_buffer.scala 559:73]
-    node _T_4743 = and(_T_4742, io.tlu_busbuff.dec_tlu_sideeffect_posted_disable) @[lsu_bus_buffer.scala 559:93]
-    node _T_4744 = eq(buf_state[1], UInt<3>("h03")) @[lsu_bus_buffer.scala 559:62]
-    node _T_4745 = bits(buf_sideeffect, 1, 1) @[lsu_bus_buffer.scala 559:89]
-    node _T_4746 = and(_T_4744, _T_4745) @[lsu_bus_buffer.scala 559:73]
-    node _T_4747 = and(_T_4746, io.tlu_busbuff.dec_tlu_sideeffect_posted_disable) @[lsu_bus_buffer.scala 559:93]
-    node _T_4748 = eq(buf_state[2], UInt<3>("h03")) @[lsu_bus_buffer.scala 559:62]
-    node _T_4749 = bits(buf_sideeffect, 2, 2) @[lsu_bus_buffer.scala 559:89]
-    node _T_4750 = and(_T_4748, _T_4749) @[lsu_bus_buffer.scala 559:73]
-    node _T_4751 = and(_T_4750, io.tlu_busbuff.dec_tlu_sideeffect_posted_disable) @[lsu_bus_buffer.scala 559:93]
-    node _T_4752 = eq(buf_state[3], UInt<3>("h03")) @[lsu_bus_buffer.scala 559:62]
-    node _T_4753 = bits(buf_sideeffect, 3, 3) @[lsu_bus_buffer.scala 559:89]
-    node _T_4754 = and(_T_4752, _T_4753) @[lsu_bus_buffer.scala 559:73]
-    node _T_4755 = and(_T_4754, io.tlu_busbuff.dec_tlu_sideeffect_posted_disable) @[lsu_bus_buffer.scala 559:93]
-    node _T_4756 = or(_T_4743, _T_4747) @[lsu_bus_buffer.scala 559:153]
-    node _T_4757 = or(_T_4756, _T_4751) @[lsu_bus_buffer.scala 559:153]
-    node _T_4758 = or(_T_4757, _T_4755) @[lsu_bus_buffer.scala 559:153]
-    node _T_4759 = and(obuf_valid, obuf_sideeffect) @[lsu_bus_buffer.scala 559:171]
-    node _T_4760 = and(_T_4759, io.tlu_busbuff.dec_tlu_sideeffect_posted_disable) @[lsu_bus_buffer.scala 559:189]
-    node _T_4761 = or(_T_4758, _T_4760) @[lsu_bus_buffer.scala 559:157]
-    bus_sideeffect_pend <= _T_4761 @[lsu_bus_buffer.scala 559:23]
-    node _T_4762 = eq(buf_state[0], UInt<3>("h03")) @[lsu_bus_buffer.scala 560:71]
-    node _T_4763 = bits(obuf_addr, 31, 3) @[lsu_bus_buffer.scala 561:31]
-    node _T_4764 = bits(buf_addr[0], 31, 3) @[lsu_bus_buffer.scala 561:51]
-    node _T_4765 = eq(_T_4763, _T_4764) @[lsu_bus_buffer.scala 561:37]
-    node _T_4766 = and(obuf_valid, _T_4765) @[lsu_bus_buffer.scala 561:19]
-    node _T_4767 = eq(obuf_tag0, UInt<1>("h00")) @[lsu_bus_buffer.scala 561:73]
-    node _T_4768 = eq(obuf_tag1, UInt<1>("h00")) @[lsu_bus_buffer.scala 561:107]
-    node _T_4769 = and(obuf_merge, _T_4768) @[lsu_bus_buffer.scala 561:95]
-    node _T_4770 = or(_T_4767, _T_4769) @[lsu_bus_buffer.scala 561:81]
-    node _T_4771 = eq(_T_4770, UInt<1>("h00")) @[lsu_bus_buffer.scala 561:61]
-    node _T_4772 = and(_T_4766, _T_4771) @[lsu_bus_buffer.scala 561:59]
-    node _T_4773 = eq(buf_state[1], UInt<3>("h03")) @[lsu_bus_buffer.scala 560:71]
-    node _T_4774 = bits(obuf_addr, 31, 3) @[lsu_bus_buffer.scala 561:31]
-    node _T_4775 = bits(buf_addr[1], 31, 3) @[lsu_bus_buffer.scala 561:51]
-    node _T_4776 = eq(_T_4774, _T_4775) @[lsu_bus_buffer.scala 561:37]
-    node _T_4777 = and(obuf_valid, _T_4776) @[lsu_bus_buffer.scala 561:19]
-    node _T_4778 = eq(obuf_tag0, UInt<1>("h01")) @[lsu_bus_buffer.scala 561:73]
-    node _T_4779 = eq(obuf_tag1, UInt<1>("h01")) @[lsu_bus_buffer.scala 561:107]
-    node _T_4780 = and(obuf_merge, _T_4779) @[lsu_bus_buffer.scala 561:95]
-    node _T_4781 = or(_T_4778, _T_4780) @[lsu_bus_buffer.scala 561:81]
-    node _T_4782 = eq(_T_4781, UInt<1>("h00")) @[lsu_bus_buffer.scala 561:61]
-    node _T_4783 = and(_T_4777, _T_4782) @[lsu_bus_buffer.scala 561:59]
-    node _T_4784 = eq(buf_state[2], UInt<3>("h03")) @[lsu_bus_buffer.scala 560:71]
-    node _T_4785 = bits(obuf_addr, 31, 3) @[lsu_bus_buffer.scala 561:31]
-    node _T_4786 = bits(buf_addr[2], 31, 3) @[lsu_bus_buffer.scala 561:51]
-    node _T_4787 = eq(_T_4785, _T_4786) @[lsu_bus_buffer.scala 561:37]
-    node _T_4788 = and(obuf_valid, _T_4787) @[lsu_bus_buffer.scala 561:19]
-    node _T_4789 = eq(obuf_tag0, UInt<2>("h02")) @[lsu_bus_buffer.scala 561:73]
-    node _T_4790 = eq(obuf_tag1, UInt<2>("h02")) @[lsu_bus_buffer.scala 561:107]
-    node _T_4791 = and(obuf_merge, _T_4790) @[lsu_bus_buffer.scala 561:95]
-    node _T_4792 = or(_T_4789, _T_4791) @[lsu_bus_buffer.scala 561:81]
-    node _T_4793 = eq(_T_4792, UInt<1>("h00")) @[lsu_bus_buffer.scala 561:61]
-    node _T_4794 = and(_T_4788, _T_4793) @[lsu_bus_buffer.scala 561:59]
-    node _T_4795 = eq(buf_state[3], UInt<3>("h03")) @[lsu_bus_buffer.scala 560:71]
-    node _T_4796 = bits(obuf_addr, 31, 3) @[lsu_bus_buffer.scala 561:31]
-    node _T_4797 = bits(buf_addr[3], 31, 3) @[lsu_bus_buffer.scala 561:51]
-    node _T_4798 = eq(_T_4796, _T_4797) @[lsu_bus_buffer.scala 561:37]
-    node _T_4799 = and(obuf_valid, _T_4798) @[lsu_bus_buffer.scala 561:19]
-    node _T_4800 = eq(obuf_tag0, UInt<2>("h03")) @[lsu_bus_buffer.scala 561:73]
-    node _T_4801 = eq(obuf_tag1, UInt<2>("h03")) @[lsu_bus_buffer.scala 561:107]
-    node _T_4802 = and(obuf_merge, _T_4801) @[lsu_bus_buffer.scala 561:95]
-    node _T_4803 = or(_T_4800, _T_4802) @[lsu_bus_buffer.scala 561:81]
-    node _T_4804 = eq(_T_4803, UInt<1>("h00")) @[lsu_bus_buffer.scala 561:61]
-    node _T_4805 = and(_T_4799, _T_4804) @[lsu_bus_buffer.scala 561:59]
-    node _T_4806 = mux(_T_4762, _T_4772, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_4807 = mux(_T_4773, _T_4783, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_4808 = mux(_T_4784, _T_4794, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_4809 = mux(_T_4795, _T_4805, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_4810 = or(_T_4806, _T_4807) @[Mux.scala 27:72]
-    node _T_4811 = or(_T_4810, _T_4808) @[Mux.scala 27:72]
-    node _T_4812 = or(_T_4811, _T_4809) @[Mux.scala 27:72]
-    wire _T_4813 : UInt<1> @[Mux.scala 27:72]
-    _T_4813 <= _T_4812 @[Mux.scala 27:72]
-    bus_addr_match_pending <= _T_4813 @[lsu_bus_buffer.scala 560:26]
-    node _T_4814 = or(obuf_cmd_done, obuf_data_done) @[lsu_bus_buffer.scala 563:54]
-    node _T_4815 = mux(obuf_cmd_done, io.lsu_axi.w.ready, io.lsu_axi.aw.ready) @[lsu_bus_buffer.scala 563:75]
-    node _T_4816 = and(io.lsu_axi.aw.ready, io.lsu_axi.w.ready) @[lsu_bus_buffer.scala 563:153]
-    node _T_4817 = mux(_T_4814, _T_4815, _T_4816) @[lsu_bus_buffer.scala 563:39]
-    node _T_4818 = mux(obuf_write, _T_4817, io.lsu_axi.ar.ready) @[lsu_bus_buffer.scala 563:23]
-    bus_cmd_ready <= _T_4818 @[lsu_bus_buffer.scala 563:17]
-    node _T_4819 = and(io.lsu_axi.aw.valid, io.lsu_axi.aw.ready) @[lsu_bus_buffer.scala 564:40]
-    bus_wcmd_sent <= _T_4819 @[lsu_bus_buffer.scala 564:17]
-    node _T_4820 = and(io.lsu_axi.w.valid, io.lsu_axi.w.ready) @[lsu_bus_buffer.scala 565:40]
-    bus_wdata_sent <= _T_4820 @[lsu_bus_buffer.scala 565:18]
-    node _T_4821 = or(obuf_cmd_done, bus_wcmd_sent) @[lsu_bus_buffer.scala 566:35]
-    node _T_4822 = or(obuf_data_done, bus_wdata_sent) @[lsu_bus_buffer.scala 566:70]
-    node _T_4823 = and(_T_4821, _T_4822) @[lsu_bus_buffer.scala 566:52]
-    node _T_4824 = and(io.lsu_axi.ar.valid, io.lsu_axi.ar.ready) @[lsu_bus_buffer.scala 566:112]
-    node _T_4825 = or(_T_4823, _T_4824) @[lsu_bus_buffer.scala 566:89]
-    bus_cmd_sent <= _T_4825 @[lsu_bus_buffer.scala 566:16]
-    node _T_4826 = and(io.lsu_axi.r.valid, io.lsu_axi.r.ready) @[lsu_bus_buffer.scala 567:38]
-    bus_rsp_read <= _T_4826 @[lsu_bus_buffer.scala 567:16]
-    node _T_4827 = and(io.lsu_axi.b.valid, io.lsu_axi.b.ready) @[lsu_bus_buffer.scala 568:39]
-    bus_rsp_write <= _T_4827 @[lsu_bus_buffer.scala 568:17]
-    bus_rsp_read_tag <= io.lsu_axi.r.bits.id @[lsu_bus_buffer.scala 569:20]
-    bus_rsp_write_tag <= io.lsu_axi.b.bits.id @[lsu_bus_buffer.scala 570:21]
-    node _T_4828 = neq(io.lsu_axi.b.bits.resp, UInt<1>("h00")) @[lsu_bus_buffer.scala 571:66]
-    node _T_4829 = and(bus_rsp_write, _T_4828) @[lsu_bus_buffer.scala 571:40]
-    bus_rsp_write_error <= _T_4829 @[lsu_bus_buffer.scala 571:23]
-    node _T_4830 = neq(io.lsu_axi.r.bits.resp, UInt<1>("h00")) @[lsu_bus_buffer.scala 572:64]
-    node _T_4831 = and(bus_rsp_read, _T_4830) @[lsu_bus_buffer.scala 572:38]
-    bus_rsp_read_error <= _T_4831 @[lsu_bus_buffer.scala 572:22]
-    bus_rsp_rdata <= io.lsu_axi.r.bits.data @[lsu_bus_buffer.scala 573:17]
-    node _T_4832 = and(obuf_valid, obuf_write) @[lsu_bus_buffer.scala 576:37]
-    node _T_4833 = eq(obuf_cmd_done, UInt<1>("h00")) @[lsu_bus_buffer.scala 576:52]
-    node _T_4834 = and(_T_4832, _T_4833) @[lsu_bus_buffer.scala 576:50]
-    node _T_4835 = eq(bus_addr_match_pending, UInt<1>("h00")) @[lsu_bus_buffer.scala 576:69]
-    node _T_4836 = and(_T_4834, _T_4835) @[lsu_bus_buffer.scala 576:67]
-    io.lsu_axi.aw.valid <= _T_4836 @[lsu_bus_buffer.scala 576:23]
-    io.lsu_axi.aw.bits.id <= obuf_tag0 @[lsu_bus_buffer.scala 577:25]
-    node _T_4837 = bits(obuf_addr, 31, 3) @[lsu_bus_buffer.scala 578:75]
-    node _T_4838 = cat(_T_4837, UInt<3>("h00")) @[Cat.scala 29:58]
-    node _T_4839 = mux(obuf_sideeffect, obuf_addr, _T_4838) @[lsu_bus_buffer.scala 578:33]
-    io.lsu_axi.aw.bits.addr <= _T_4839 @[lsu_bus_buffer.scala 578:27]
-    node _T_4840 = cat(UInt<1>("h00"), obuf_sz) @[Cat.scala 29:58]
-    node _T_4841 = mux(obuf_sideeffect, _T_4840, UInt<3>("h03")) @[lsu_bus_buffer.scala 579:33]
-    io.lsu_axi.aw.bits.size <= _T_4841 @[lsu_bus_buffer.scala 579:27]
-    io.lsu_axi.aw.bits.prot <= UInt<1>("h01") @[lsu_bus_buffer.scala 580:27]
-    node _T_4842 = mux(obuf_sideeffect, UInt<1>("h00"), UInt<4>("h0f")) @[lsu_bus_buffer.scala 581:34]
-    io.lsu_axi.aw.bits.cache <= _T_4842 @[lsu_bus_buffer.scala 581:28]
-    node _T_4843 = bits(obuf_addr, 31, 28) @[lsu_bus_buffer.scala 582:41]
-    io.lsu_axi.aw.bits.region <= _T_4843 @[lsu_bus_buffer.scala 582:29]
-    io.lsu_axi.aw.bits.len <= UInt<1>("h00") @[lsu_bus_buffer.scala 583:26]
-    io.lsu_axi.aw.bits.burst <= UInt<2>("h01") @[lsu_bus_buffer.scala 584:28]
-    io.lsu_axi.aw.bits.qos <= UInt<1>("h00") @[lsu_bus_buffer.scala 585:26]
-    io.lsu_axi.aw.bits.lock <= UInt<1>("h00") @[lsu_bus_buffer.scala 586:27]
-    node _T_4844 = and(obuf_valid, obuf_write) @[lsu_bus_buffer.scala 588:36]
-    node _T_4845 = eq(obuf_data_done, UInt<1>("h00")) @[lsu_bus_buffer.scala 588:51]
-    node _T_4846 = and(_T_4844, _T_4845) @[lsu_bus_buffer.scala 588:49]
-    node _T_4847 = eq(bus_addr_match_pending, UInt<1>("h00")) @[lsu_bus_buffer.scala 588:69]
-    node _T_4848 = and(_T_4846, _T_4847) @[lsu_bus_buffer.scala 588:67]
-    io.lsu_axi.w.valid <= _T_4848 @[lsu_bus_buffer.scala 588:22]
-    node _T_4849 = bits(obuf_write, 0, 0) @[Bitwise.scala 72:15]
-    node _T_4850 = mux(_T_4849, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
-    node _T_4851 = and(obuf_byteen, _T_4850) @[lsu_bus_buffer.scala 589:41]
-    io.lsu_axi.w.bits.strb <= _T_4851 @[lsu_bus_buffer.scala 589:26]
-    io.lsu_axi.w.bits.data <= obuf_data @[lsu_bus_buffer.scala 590:26]
-    io.lsu_axi.w.bits.last <= UInt<1>("h01") @[lsu_bus_buffer.scala 591:26]
-    node _T_4852 = eq(obuf_write, UInt<1>("h00")) @[lsu_bus_buffer.scala 593:39]
-    node _T_4853 = and(obuf_valid, _T_4852) @[lsu_bus_buffer.scala 593:37]
-    node _T_4854 = eq(obuf_nosend, UInt<1>("h00")) @[lsu_bus_buffer.scala 593:53]
-    node _T_4855 = and(_T_4853, _T_4854) @[lsu_bus_buffer.scala 593:51]
-    node _T_4856 = eq(bus_addr_match_pending, UInt<1>("h00")) @[lsu_bus_buffer.scala 593:68]
-    node _T_4857 = and(_T_4855, _T_4856) @[lsu_bus_buffer.scala 593:66]
-    io.lsu_axi.ar.valid <= _T_4857 @[lsu_bus_buffer.scala 593:23]
-    io.lsu_axi.ar.bits.id <= obuf_tag0 @[lsu_bus_buffer.scala 594:25]
-    node _T_4858 = bits(obuf_addr, 31, 3) @[lsu_bus_buffer.scala 595:75]
-    node _T_4859 = cat(_T_4858, UInt<3>("h00")) @[Cat.scala 29:58]
-    node _T_4860 = mux(obuf_sideeffect, obuf_addr, _T_4859) @[lsu_bus_buffer.scala 595:33]
-    io.lsu_axi.ar.bits.addr <= _T_4860 @[lsu_bus_buffer.scala 595:27]
-    node _T_4861 = cat(UInt<1>("h00"), obuf_sz) @[Cat.scala 29:58]
-    node _T_4862 = mux(obuf_sideeffect, _T_4861, UInt<3>("h03")) @[lsu_bus_buffer.scala 596:33]
-    io.lsu_axi.ar.bits.size <= _T_4862 @[lsu_bus_buffer.scala 596:27]
-    io.lsu_axi.ar.bits.prot <= UInt<1>("h01") @[lsu_bus_buffer.scala 597:27]
-    node _T_4863 = mux(obuf_sideeffect, UInt<4>("h00"), UInt<4>("h0f")) @[lsu_bus_buffer.scala 598:34]
-    io.lsu_axi.ar.bits.cache <= _T_4863 @[lsu_bus_buffer.scala 598:28]
-    node _T_4864 = bits(obuf_addr, 31, 28) @[lsu_bus_buffer.scala 599:41]
-    io.lsu_axi.ar.bits.region <= _T_4864 @[lsu_bus_buffer.scala 599:29]
-    io.lsu_axi.ar.bits.len <= UInt<1>("h00") @[lsu_bus_buffer.scala 600:26]
-    io.lsu_axi.ar.bits.burst <= UInt<2>("h01") @[lsu_bus_buffer.scala 601:28]
-    io.lsu_axi.ar.bits.qos <= UInt<1>("h00") @[lsu_bus_buffer.scala 602:26]
-    io.lsu_axi.ar.bits.lock <= UInt<1>("h00") @[lsu_bus_buffer.scala 603:27]
-    io.lsu_axi.b.ready <= UInt<1>("h01") @[lsu_bus_buffer.scala 604:22]
-    io.lsu_axi.r.ready <= UInt<1>("h01") @[lsu_bus_buffer.scala 605:22]
-    node _T_4865 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 606:93]
-    node _T_4866 = bits(buf_error, 0, 0) @[lsu_bus_buffer.scala 606:137]
-    node _T_4867 = and(io.lsu_bus_clk_en_q, _T_4866) @[lsu_bus_buffer.scala 606:126]
-    node _T_4868 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 606:152]
-    node _T_4869 = and(_T_4867, _T_4868) @[lsu_bus_buffer.scala 606:141]
-    node _T_4870 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 606:93]
-    node _T_4871 = bits(buf_error, 1, 1) @[lsu_bus_buffer.scala 606:137]
-    node _T_4872 = and(io.lsu_bus_clk_en_q, _T_4871) @[lsu_bus_buffer.scala 606:126]
-    node _T_4873 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 606:152]
-    node _T_4874 = and(_T_4872, _T_4873) @[lsu_bus_buffer.scala 606:141]
-    node _T_4875 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 606:93]
-    node _T_4876 = bits(buf_error, 2, 2) @[lsu_bus_buffer.scala 606:137]
-    node _T_4877 = and(io.lsu_bus_clk_en_q, _T_4876) @[lsu_bus_buffer.scala 606:126]
-    node _T_4878 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 606:152]
-    node _T_4879 = and(_T_4877, _T_4878) @[lsu_bus_buffer.scala 606:141]
-    node _T_4880 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 606:93]
-    node _T_4881 = bits(buf_error, 3, 3) @[lsu_bus_buffer.scala 606:137]
-    node _T_4882 = and(io.lsu_bus_clk_en_q, _T_4881) @[lsu_bus_buffer.scala 606:126]
-    node _T_4883 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 606:152]
-    node _T_4884 = and(_T_4882, _T_4883) @[lsu_bus_buffer.scala 606:141]
-    node _T_4885 = mux(_T_4865, _T_4869, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_4886 = mux(_T_4870, _T_4874, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_4887 = mux(_T_4875, _T_4879, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_4888 = mux(_T_4880, _T_4884, UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_4889 = or(_T_4885, _T_4886) @[Mux.scala 27:72]
-    node _T_4890 = or(_T_4889, _T_4887) @[Mux.scala 27:72]
-    node _T_4891 = or(_T_4890, _T_4888) @[Mux.scala 27:72]
-    wire _T_4892 : UInt<1> @[Mux.scala 27:72]
-    _T_4892 <= _T_4891 @[Mux.scala 27:72]
-    io.tlu_busbuff.lsu_imprecise_error_store_any <= _T_4892 @[lsu_bus_buffer.scala 606:48]
-    node _T_4893 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 607:82]
-    node _T_4894 = bits(buf_error, 0, 0) @[lsu_bus_buffer.scala 607:104]
-    node _T_4895 = and(_T_4893, _T_4894) @[lsu_bus_buffer.scala 607:93]
-    node _T_4896 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 607:119]
-    node _T_4897 = and(_T_4895, _T_4896) @[lsu_bus_buffer.scala 607:108]
-    node _T_4898 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 607:82]
-    node _T_4899 = bits(buf_error, 1, 1) @[lsu_bus_buffer.scala 607:104]
-    node _T_4900 = and(_T_4898, _T_4899) @[lsu_bus_buffer.scala 607:93]
-    node _T_4901 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 607:119]
-    node _T_4902 = and(_T_4900, _T_4901) @[lsu_bus_buffer.scala 607:108]
-    node _T_4903 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 607:82]
-    node _T_4904 = bits(buf_error, 2, 2) @[lsu_bus_buffer.scala 607:104]
-    node _T_4905 = and(_T_4903, _T_4904) @[lsu_bus_buffer.scala 607:93]
-    node _T_4906 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 607:119]
-    node _T_4907 = and(_T_4905, _T_4906) @[lsu_bus_buffer.scala 607:108]
-    node _T_4908 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 607:82]
-    node _T_4909 = bits(buf_error, 3, 3) @[lsu_bus_buffer.scala 607:104]
-    node _T_4910 = and(_T_4908, _T_4909) @[lsu_bus_buffer.scala 607:93]
-    node _T_4911 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 607:119]
-    node _T_4912 = and(_T_4910, _T_4911) @[lsu_bus_buffer.scala 607:108]
-    node _T_4913 = mux(_T_4897, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_4914 = mux(_T_4902, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_4915 = mux(_T_4907, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_4916 = mux(_T_4912, UInt<2>("h03"), UInt<1>("h00")) @[Mux.scala 27:72]
-    node _T_4917 = or(_T_4913, _T_4914) @[Mux.scala 27:72]
-    node _T_4918 = or(_T_4917, _T_4915) @[Mux.scala 27:72]
-    node _T_4919 = or(_T_4918, _T_4916) @[Mux.scala 27:72]
+    lsu_nonblock_unsign <= _T_4711 @[Mux.scala 27:72]
+    node _T_4712 = cat(lsu_nonblock_load_data_hi, lsu_nonblock_load_data_lo) @[Cat.scala 29:58]
+    node _T_4713 = mul(lsu_nonblock_addr_offset, UInt<4>("h08")) @[lsu_bus_buffer.scala 553:121]
+    node lsu_nonblock_data_unalgn = dshr(_T_4712, _T_4713) @[lsu_bus_buffer.scala 553:92]
+    node _T_4714 = eq(io.dctl_busbuff.lsu_nonblock_load_data_error, UInt<1>("h00")) @[lsu_bus_buffer.scala 555:82]
+    node _T_4715 = and(lsu_nonblock_load_data_ready, _T_4714) @[lsu_bus_buffer.scala 555:80]
+    io.dctl_busbuff.lsu_nonblock_load_data_valid <= _T_4715 @[lsu_bus_buffer.scala 555:48]
+    node _T_4716 = eq(lsu_nonblock_sz, UInt<1>("h00")) @[lsu_bus_buffer.scala 556:94]
+    node _T_4717 = and(lsu_nonblock_unsign, _T_4716) @[lsu_bus_buffer.scala 556:76]
+    node _T_4718 = bits(lsu_nonblock_data_unalgn, 7, 0) @[lsu_bus_buffer.scala 556:144]
+    node _T_4719 = cat(UInt<24>("h00"), _T_4718) @[Cat.scala 29:58]
+    node _T_4720 = eq(lsu_nonblock_sz, UInt<1>("h01")) @[lsu_bus_buffer.scala 557:45]
+    node _T_4721 = and(lsu_nonblock_unsign, _T_4720) @[lsu_bus_buffer.scala 557:26]
+    node _T_4722 = bits(lsu_nonblock_data_unalgn, 15, 0) @[lsu_bus_buffer.scala 557:95]
+    node _T_4723 = cat(UInt<16>("h00"), _T_4722) @[Cat.scala 29:58]
+    node _T_4724 = eq(lsu_nonblock_unsign, UInt<1>("h00")) @[lsu_bus_buffer.scala 558:6]
+    node _T_4725 = eq(lsu_nonblock_sz, UInt<1>("h00")) @[lsu_bus_buffer.scala 558:45]
+    node _T_4726 = and(_T_4724, _T_4725) @[lsu_bus_buffer.scala 558:27]
+    node _T_4727 = bits(lsu_nonblock_data_unalgn, 7, 7) @[lsu_bus_buffer.scala 558:93]
+    node _T_4728 = bits(_T_4727, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4729 = mux(_T_4728, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12]
+    node _T_4730 = bits(lsu_nonblock_data_unalgn, 7, 0) @[lsu_bus_buffer.scala 558:123]
+    node _T_4731 = cat(_T_4729, _T_4730) @[Cat.scala 29:58]
+    node _T_4732 = eq(lsu_nonblock_unsign, UInt<1>("h00")) @[lsu_bus_buffer.scala 559:6]
+    node _T_4733 = eq(lsu_nonblock_sz, UInt<1>("h01")) @[lsu_bus_buffer.scala 559:45]
+    node _T_4734 = and(_T_4732, _T_4733) @[lsu_bus_buffer.scala 559:27]
+    node _T_4735 = bits(lsu_nonblock_data_unalgn, 15, 15) @[lsu_bus_buffer.scala 559:93]
+    node _T_4736 = bits(_T_4735, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4737 = mux(_T_4736, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12]
+    node _T_4738 = bits(lsu_nonblock_data_unalgn, 15, 0) @[lsu_bus_buffer.scala 559:124]
+    node _T_4739 = cat(_T_4737, _T_4738) @[Cat.scala 29:58]
+    node _T_4740 = eq(lsu_nonblock_sz, UInt<2>("h02")) @[lsu_bus_buffer.scala 560:21]
+    node _T_4741 = mux(_T_4717, _T_4719, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_4742 = mux(_T_4721, _T_4723, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_4743 = mux(_T_4726, _T_4731, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_4744 = mux(_T_4734, _T_4739, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_4745 = mux(_T_4740, lsu_nonblock_data_unalgn, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_4746 = or(_T_4741, _T_4742) @[Mux.scala 27:72]
+    node _T_4747 = or(_T_4746, _T_4743) @[Mux.scala 27:72]
+    node _T_4748 = or(_T_4747, _T_4744) @[Mux.scala 27:72]
+    node _T_4749 = or(_T_4748, _T_4745) @[Mux.scala 27:72]
+    wire _T_4750 : UInt<64> @[Mux.scala 27:72]
+    _T_4750 <= _T_4749 @[Mux.scala 27:72]
+    io.dctl_busbuff.lsu_nonblock_load_data <= _T_4750 @[lsu_bus_buffer.scala 556:42]
+    node _T_4751 = eq(buf_state[0], UInt<3>("h03")) @[lsu_bus_buffer.scala 561:62]
+    node _T_4752 = bits(buf_sideeffect, 0, 0) @[lsu_bus_buffer.scala 561:89]
+    node _T_4753 = and(_T_4751, _T_4752) @[lsu_bus_buffer.scala 561:73]
+    node _T_4754 = and(_T_4753, io.tlu_busbuff.dec_tlu_sideeffect_posted_disable) @[lsu_bus_buffer.scala 561:93]
+    node _T_4755 = eq(buf_state[1], UInt<3>("h03")) @[lsu_bus_buffer.scala 561:62]
+    node _T_4756 = bits(buf_sideeffect, 1, 1) @[lsu_bus_buffer.scala 561:89]
+    node _T_4757 = and(_T_4755, _T_4756) @[lsu_bus_buffer.scala 561:73]
+    node _T_4758 = and(_T_4757, io.tlu_busbuff.dec_tlu_sideeffect_posted_disable) @[lsu_bus_buffer.scala 561:93]
+    node _T_4759 = eq(buf_state[2], UInt<3>("h03")) @[lsu_bus_buffer.scala 561:62]
+    node _T_4760 = bits(buf_sideeffect, 2, 2) @[lsu_bus_buffer.scala 561:89]
+    node _T_4761 = and(_T_4759, _T_4760) @[lsu_bus_buffer.scala 561:73]
+    node _T_4762 = and(_T_4761, io.tlu_busbuff.dec_tlu_sideeffect_posted_disable) @[lsu_bus_buffer.scala 561:93]
+    node _T_4763 = eq(buf_state[3], UInt<3>("h03")) @[lsu_bus_buffer.scala 561:62]
+    node _T_4764 = bits(buf_sideeffect, 3, 3) @[lsu_bus_buffer.scala 561:89]
+    node _T_4765 = and(_T_4763, _T_4764) @[lsu_bus_buffer.scala 561:73]
+    node _T_4766 = and(_T_4765, io.tlu_busbuff.dec_tlu_sideeffect_posted_disable) @[lsu_bus_buffer.scala 561:93]
+    node _T_4767 = or(_T_4754, _T_4758) @[lsu_bus_buffer.scala 561:153]
+    node _T_4768 = or(_T_4767, _T_4762) @[lsu_bus_buffer.scala 561:153]
+    node _T_4769 = or(_T_4768, _T_4766) @[lsu_bus_buffer.scala 561:153]
+    node _T_4770 = and(obuf_valid, obuf_sideeffect) @[lsu_bus_buffer.scala 561:171]
+    node _T_4771 = and(_T_4770, io.tlu_busbuff.dec_tlu_sideeffect_posted_disable) @[lsu_bus_buffer.scala 561:189]
+    node _T_4772 = or(_T_4769, _T_4771) @[lsu_bus_buffer.scala 561:157]
+    bus_sideeffect_pend <= _T_4772 @[lsu_bus_buffer.scala 561:23]
+    node _T_4773 = eq(buf_state[0], UInt<3>("h03")) @[lsu_bus_buffer.scala 562:71]
+    node _T_4774 = bits(obuf_addr, 31, 3) @[lsu_bus_buffer.scala 563:31]
+    node _T_4775 = bits(buf_addr[0], 31, 3) @[lsu_bus_buffer.scala 563:51]
+    node _T_4776 = eq(_T_4774, _T_4775) @[lsu_bus_buffer.scala 563:37]
+    node _T_4777 = and(obuf_valid, _T_4776) @[lsu_bus_buffer.scala 563:19]
+    node _T_4778 = eq(obuf_tag0, UInt<1>("h00")) @[lsu_bus_buffer.scala 563:73]
+    node _T_4779 = eq(obuf_tag1, UInt<1>("h00")) @[lsu_bus_buffer.scala 563:107]
+    node _T_4780 = and(obuf_merge, _T_4779) @[lsu_bus_buffer.scala 563:95]
+    node _T_4781 = or(_T_4778, _T_4780) @[lsu_bus_buffer.scala 563:81]
+    node _T_4782 = eq(_T_4781, UInt<1>("h00")) @[lsu_bus_buffer.scala 563:61]
+    node _T_4783 = and(_T_4777, _T_4782) @[lsu_bus_buffer.scala 563:59]
+    node _T_4784 = eq(buf_state[1], UInt<3>("h03")) @[lsu_bus_buffer.scala 562:71]
+    node _T_4785 = bits(obuf_addr, 31, 3) @[lsu_bus_buffer.scala 563:31]
+    node _T_4786 = bits(buf_addr[1], 31, 3) @[lsu_bus_buffer.scala 563:51]
+    node _T_4787 = eq(_T_4785, _T_4786) @[lsu_bus_buffer.scala 563:37]
+    node _T_4788 = and(obuf_valid, _T_4787) @[lsu_bus_buffer.scala 563:19]
+    node _T_4789 = eq(obuf_tag0, UInt<1>("h01")) @[lsu_bus_buffer.scala 563:73]
+    node _T_4790 = eq(obuf_tag1, UInt<1>("h01")) @[lsu_bus_buffer.scala 563:107]
+    node _T_4791 = and(obuf_merge, _T_4790) @[lsu_bus_buffer.scala 563:95]
+    node _T_4792 = or(_T_4789, _T_4791) @[lsu_bus_buffer.scala 563:81]
+    node _T_4793 = eq(_T_4792, UInt<1>("h00")) @[lsu_bus_buffer.scala 563:61]
+    node _T_4794 = and(_T_4788, _T_4793) @[lsu_bus_buffer.scala 563:59]
+    node _T_4795 = eq(buf_state[2], UInt<3>("h03")) @[lsu_bus_buffer.scala 562:71]
+    node _T_4796 = bits(obuf_addr, 31, 3) @[lsu_bus_buffer.scala 563:31]
+    node _T_4797 = bits(buf_addr[2], 31, 3) @[lsu_bus_buffer.scala 563:51]
+    node _T_4798 = eq(_T_4796, _T_4797) @[lsu_bus_buffer.scala 563:37]
+    node _T_4799 = and(obuf_valid, _T_4798) @[lsu_bus_buffer.scala 563:19]
+    node _T_4800 = eq(obuf_tag0, UInt<2>("h02")) @[lsu_bus_buffer.scala 563:73]
+    node _T_4801 = eq(obuf_tag1, UInt<2>("h02")) @[lsu_bus_buffer.scala 563:107]
+    node _T_4802 = and(obuf_merge, _T_4801) @[lsu_bus_buffer.scala 563:95]
+    node _T_4803 = or(_T_4800, _T_4802) @[lsu_bus_buffer.scala 563:81]
+    node _T_4804 = eq(_T_4803, UInt<1>("h00")) @[lsu_bus_buffer.scala 563:61]
+    node _T_4805 = and(_T_4799, _T_4804) @[lsu_bus_buffer.scala 563:59]
+    node _T_4806 = eq(buf_state[3], UInt<3>("h03")) @[lsu_bus_buffer.scala 562:71]
+    node _T_4807 = bits(obuf_addr, 31, 3) @[lsu_bus_buffer.scala 563:31]
+    node _T_4808 = bits(buf_addr[3], 31, 3) @[lsu_bus_buffer.scala 563:51]
+    node _T_4809 = eq(_T_4807, _T_4808) @[lsu_bus_buffer.scala 563:37]
+    node _T_4810 = and(obuf_valid, _T_4809) @[lsu_bus_buffer.scala 563:19]
+    node _T_4811 = eq(obuf_tag0, UInt<2>("h03")) @[lsu_bus_buffer.scala 563:73]
+    node _T_4812 = eq(obuf_tag1, UInt<2>("h03")) @[lsu_bus_buffer.scala 563:107]
+    node _T_4813 = and(obuf_merge, _T_4812) @[lsu_bus_buffer.scala 563:95]
+    node _T_4814 = or(_T_4811, _T_4813) @[lsu_bus_buffer.scala 563:81]
+    node _T_4815 = eq(_T_4814, UInt<1>("h00")) @[lsu_bus_buffer.scala 563:61]
+    node _T_4816 = and(_T_4810, _T_4815) @[lsu_bus_buffer.scala 563:59]
+    node _T_4817 = mux(_T_4773, _T_4783, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_4818 = mux(_T_4784, _T_4794, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_4819 = mux(_T_4795, _T_4805, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_4820 = mux(_T_4806, _T_4816, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_4821 = or(_T_4817, _T_4818) @[Mux.scala 27:72]
+    node _T_4822 = or(_T_4821, _T_4819) @[Mux.scala 27:72]
+    node _T_4823 = or(_T_4822, _T_4820) @[Mux.scala 27:72]
+    wire _T_4824 : UInt<1> @[Mux.scala 27:72]
+    _T_4824 <= _T_4823 @[Mux.scala 27:72]
+    bus_addr_match_pending <= _T_4824 @[lsu_bus_buffer.scala 562:26]
+    node _T_4825 = or(obuf_cmd_done, obuf_data_done) @[lsu_bus_buffer.scala 565:54]
+    node _T_4826 = mux(obuf_cmd_done, io.lsu_axi.w.ready, io.lsu_axi.aw.ready) @[lsu_bus_buffer.scala 565:75]
+    node _T_4827 = and(io.lsu_axi.aw.ready, io.lsu_axi.w.ready) @[lsu_bus_buffer.scala 565:153]
+    node _T_4828 = mux(_T_4825, _T_4826, _T_4827) @[lsu_bus_buffer.scala 565:39]
+    node _T_4829 = mux(obuf_write, _T_4828, io.lsu_axi.ar.ready) @[lsu_bus_buffer.scala 565:23]
+    bus_cmd_ready <= _T_4829 @[lsu_bus_buffer.scala 565:17]
+    node _T_4830 = and(io.lsu_axi.aw.valid, io.lsu_axi.aw.ready) @[lsu_bus_buffer.scala 566:40]
+    bus_wcmd_sent <= _T_4830 @[lsu_bus_buffer.scala 566:17]
+    node _T_4831 = and(io.lsu_axi.w.valid, io.lsu_axi.w.ready) @[lsu_bus_buffer.scala 567:40]
+    bus_wdata_sent <= _T_4831 @[lsu_bus_buffer.scala 567:18]
+    node _T_4832 = or(obuf_cmd_done, bus_wcmd_sent) @[lsu_bus_buffer.scala 568:35]
+    node _T_4833 = or(obuf_data_done, bus_wdata_sent) @[lsu_bus_buffer.scala 568:70]
+    node _T_4834 = and(_T_4832, _T_4833) @[lsu_bus_buffer.scala 568:52]
+    node _T_4835 = and(io.lsu_axi.ar.valid, io.lsu_axi.ar.ready) @[lsu_bus_buffer.scala 568:112]
+    node _T_4836 = or(_T_4834, _T_4835) @[lsu_bus_buffer.scala 568:89]
+    bus_cmd_sent <= _T_4836 @[lsu_bus_buffer.scala 568:16]
+    node _T_4837 = and(io.lsu_axi.r.valid, io.lsu_axi.r.ready) @[lsu_bus_buffer.scala 569:38]
+    bus_rsp_read <= _T_4837 @[lsu_bus_buffer.scala 569:16]
+    node _T_4838 = and(io.lsu_axi.b.valid, io.lsu_axi.b.ready) @[lsu_bus_buffer.scala 570:39]
+    bus_rsp_write <= _T_4838 @[lsu_bus_buffer.scala 570:17]
+    bus_rsp_read_tag <= io.lsu_axi.r.bits.id @[lsu_bus_buffer.scala 571:20]
+    bus_rsp_write_tag <= io.lsu_axi.b.bits.id @[lsu_bus_buffer.scala 572:21]
+    node _T_4839 = neq(io.lsu_axi.b.bits.resp, UInt<1>("h00")) @[lsu_bus_buffer.scala 573:66]
+    node _T_4840 = and(bus_rsp_write, _T_4839) @[lsu_bus_buffer.scala 573:40]
+    bus_rsp_write_error <= _T_4840 @[lsu_bus_buffer.scala 573:23]
+    node _T_4841 = neq(io.lsu_axi.r.bits.resp, UInt<1>("h00")) @[lsu_bus_buffer.scala 574:64]
+    node _T_4842 = and(bus_rsp_read, _T_4841) @[lsu_bus_buffer.scala 574:38]
+    bus_rsp_read_error <= _T_4842 @[lsu_bus_buffer.scala 574:22]
+    bus_rsp_rdata <= io.lsu_axi.r.bits.data @[lsu_bus_buffer.scala 575:17]
+    node _T_4843 = and(obuf_valid, obuf_write) @[lsu_bus_buffer.scala 578:37]
+    node _T_4844 = eq(obuf_cmd_done, UInt<1>("h00")) @[lsu_bus_buffer.scala 578:52]
+    node _T_4845 = and(_T_4843, _T_4844) @[lsu_bus_buffer.scala 578:50]
+    node _T_4846 = eq(bus_addr_match_pending, UInt<1>("h00")) @[lsu_bus_buffer.scala 578:69]
+    node _T_4847 = and(_T_4845, _T_4846) @[lsu_bus_buffer.scala 578:67]
+    io.lsu_axi.aw.valid <= _T_4847 @[lsu_bus_buffer.scala 578:23]
+    io.lsu_axi.aw.bits.id <= obuf_tag0 @[lsu_bus_buffer.scala 579:25]
+    node _T_4848 = bits(obuf_addr, 31, 3) @[lsu_bus_buffer.scala 580:75]
+    node _T_4849 = cat(_T_4848, UInt<3>("h00")) @[Cat.scala 29:58]
+    node _T_4850 = mux(obuf_sideeffect, obuf_addr, _T_4849) @[lsu_bus_buffer.scala 580:33]
+    io.lsu_axi.aw.bits.addr <= _T_4850 @[lsu_bus_buffer.scala 580:27]
+    node _T_4851 = cat(UInt<1>("h00"), obuf_sz) @[Cat.scala 29:58]
+    node _T_4852 = mux(obuf_sideeffect, _T_4851, UInt<3>("h03")) @[lsu_bus_buffer.scala 581:33]
+    io.lsu_axi.aw.bits.size <= _T_4852 @[lsu_bus_buffer.scala 581:27]
+    io.lsu_axi.aw.bits.prot <= UInt<3>("h01") @[lsu_bus_buffer.scala 582:27]
+    node _T_4853 = mux(obuf_sideeffect, UInt<1>("h00"), UInt<4>("h0f")) @[lsu_bus_buffer.scala 583:34]
+    io.lsu_axi.aw.bits.cache <= _T_4853 @[lsu_bus_buffer.scala 583:28]
+    node _T_4854 = bits(obuf_addr, 31, 28) @[lsu_bus_buffer.scala 584:41]
+    io.lsu_axi.aw.bits.region <= _T_4854 @[lsu_bus_buffer.scala 584:29]
+    io.lsu_axi.aw.bits.len <= UInt<1>("h00") @[lsu_bus_buffer.scala 585:26]
+    io.lsu_axi.aw.bits.burst <= UInt<2>("h01") @[lsu_bus_buffer.scala 586:28]
+    io.lsu_axi.aw.bits.qos <= UInt<1>("h00") @[lsu_bus_buffer.scala 587:26]
+    io.lsu_axi.aw.bits.lock <= UInt<1>("h00") @[lsu_bus_buffer.scala 588:27]
+    node _T_4855 = and(obuf_valid, obuf_write) @[lsu_bus_buffer.scala 590:36]
+    node _T_4856 = eq(obuf_data_done, UInt<1>("h00")) @[lsu_bus_buffer.scala 590:51]
+    node _T_4857 = and(_T_4855, _T_4856) @[lsu_bus_buffer.scala 590:49]
+    node _T_4858 = eq(bus_addr_match_pending, UInt<1>("h00")) @[lsu_bus_buffer.scala 590:69]
+    node _T_4859 = and(_T_4857, _T_4858) @[lsu_bus_buffer.scala 590:67]
+    io.lsu_axi.w.valid <= _T_4859 @[lsu_bus_buffer.scala 590:22]
+    node _T_4860 = bits(obuf_write, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4861 = mux(_T_4860, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
+    node _T_4862 = and(obuf_byteen, _T_4861) @[lsu_bus_buffer.scala 591:41]
+    io.lsu_axi.w.bits.strb <= _T_4862 @[lsu_bus_buffer.scala 591:26]
+    io.lsu_axi.w.bits.data <= obuf_data @[lsu_bus_buffer.scala 592:26]
+    io.lsu_axi.w.bits.last <= UInt<1>("h01") @[lsu_bus_buffer.scala 593:26]
+    node _T_4863 = eq(obuf_write, UInt<1>("h00")) @[lsu_bus_buffer.scala 595:39]
+    node _T_4864 = and(obuf_valid, _T_4863) @[lsu_bus_buffer.scala 595:37]
+    node _T_4865 = eq(obuf_nosend, UInt<1>("h00")) @[lsu_bus_buffer.scala 595:53]
+    node _T_4866 = and(_T_4864, _T_4865) @[lsu_bus_buffer.scala 595:51]
+    node _T_4867 = eq(bus_addr_match_pending, UInt<1>("h00")) @[lsu_bus_buffer.scala 595:68]
+    node _T_4868 = and(_T_4866, _T_4867) @[lsu_bus_buffer.scala 595:66]
+    io.lsu_axi.ar.valid <= _T_4868 @[lsu_bus_buffer.scala 595:23]
+    io.lsu_axi.ar.bits.id <= obuf_tag0 @[lsu_bus_buffer.scala 596:25]
+    node _T_4869 = bits(obuf_addr, 31, 3) @[lsu_bus_buffer.scala 597:75]
+    node _T_4870 = cat(_T_4869, UInt<3>("h00")) @[Cat.scala 29:58]
+    node _T_4871 = mux(obuf_sideeffect, obuf_addr, _T_4870) @[lsu_bus_buffer.scala 597:33]
+    io.lsu_axi.ar.bits.addr <= _T_4871 @[lsu_bus_buffer.scala 597:27]
+    node _T_4872 = cat(UInt<1>("h00"), obuf_sz) @[Cat.scala 29:58]
+    node _T_4873 = mux(obuf_sideeffect, _T_4872, UInt<3>("h03")) @[lsu_bus_buffer.scala 598:33]
+    io.lsu_axi.ar.bits.size <= _T_4873 @[lsu_bus_buffer.scala 598:27]
+    io.lsu_axi.ar.bits.prot <= UInt<3>("h01") @[lsu_bus_buffer.scala 599:27]
+    node _T_4874 = mux(obuf_sideeffect, UInt<4>("h00"), UInt<4>("h0f")) @[lsu_bus_buffer.scala 600:34]
+    io.lsu_axi.ar.bits.cache <= _T_4874 @[lsu_bus_buffer.scala 600:28]
+    node _T_4875 = bits(obuf_addr, 31, 28) @[lsu_bus_buffer.scala 601:41]
+    io.lsu_axi.ar.bits.region <= _T_4875 @[lsu_bus_buffer.scala 601:29]
+    io.lsu_axi.ar.bits.len <= UInt<1>("h00") @[lsu_bus_buffer.scala 602:26]
+    io.lsu_axi.ar.bits.burst <= UInt<2>("h01") @[lsu_bus_buffer.scala 603:28]
+    io.lsu_axi.ar.bits.qos <= UInt<1>("h00") @[lsu_bus_buffer.scala 604:26]
+    io.lsu_axi.ar.bits.lock <= UInt<1>("h00") @[lsu_bus_buffer.scala 605:27]
+    io.lsu_axi.b.ready <= UInt<1>("h01") @[lsu_bus_buffer.scala 606:22]
+    io.lsu_axi.r.ready <= UInt<1>("h01") @[lsu_bus_buffer.scala 607:22]
+    node _T_4876 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 608:93]
+    node _T_4877 = bits(buf_error, 0, 0) @[lsu_bus_buffer.scala 608:137]
+    node _T_4878 = and(io.lsu_bus_clk_en_q, _T_4877) @[lsu_bus_buffer.scala 608:126]
+    node _T_4879 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 608:152]
+    node _T_4880 = and(_T_4878, _T_4879) @[lsu_bus_buffer.scala 608:141]
+    node _T_4881 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 608:93]
+    node _T_4882 = bits(buf_error, 1, 1) @[lsu_bus_buffer.scala 608:137]
+    node _T_4883 = and(io.lsu_bus_clk_en_q, _T_4882) @[lsu_bus_buffer.scala 608:126]
+    node _T_4884 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 608:152]
+    node _T_4885 = and(_T_4883, _T_4884) @[lsu_bus_buffer.scala 608:141]
+    node _T_4886 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 608:93]
+    node _T_4887 = bits(buf_error, 2, 2) @[lsu_bus_buffer.scala 608:137]
+    node _T_4888 = and(io.lsu_bus_clk_en_q, _T_4887) @[lsu_bus_buffer.scala 608:126]
+    node _T_4889 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 608:152]
+    node _T_4890 = and(_T_4888, _T_4889) @[lsu_bus_buffer.scala 608:141]
+    node _T_4891 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 608:93]
+    node _T_4892 = bits(buf_error, 3, 3) @[lsu_bus_buffer.scala 608:137]
+    node _T_4893 = and(io.lsu_bus_clk_en_q, _T_4892) @[lsu_bus_buffer.scala 608:126]
+    node _T_4894 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 608:152]
+    node _T_4895 = and(_T_4893, _T_4894) @[lsu_bus_buffer.scala 608:141]
+    node _T_4896 = mux(_T_4876, _T_4880, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_4897 = mux(_T_4881, _T_4885, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_4898 = mux(_T_4886, _T_4890, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_4899 = mux(_T_4891, _T_4895, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_4900 = or(_T_4896, _T_4897) @[Mux.scala 27:72]
+    node _T_4901 = or(_T_4900, _T_4898) @[Mux.scala 27:72]
+    node _T_4902 = or(_T_4901, _T_4899) @[Mux.scala 27:72]
+    wire _T_4903 : UInt<1> @[Mux.scala 27:72]
+    _T_4903 <= _T_4902 @[Mux.scala 27:72]
+    io.tlu_busbuff.lsu_imprecise_error_store_any <= _T_4903 @[lsu_bus_buffer.scala 608:48]
+    node _T_4904 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 609:82]
+    node _T_4905 = bits(buf_error, 0, 0) @[lsu_bus_buffer.scala 609:104]
+    node _T_4906 = and(_T_4904, _T_4905) @[lsu_bus_buffer.scala 609:93]
+    node _T_4907 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 609:119]
+    node _T_4908 = and(_T_4906, _T_4907) @[lsu_bus_buffer.scala 609:108]
+    node _T_4909 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 609:82]
+    node _T_4910 = bits(buf_error, 1, 1) @[lsu_bus_buffer.scala 609:104]
+    node _T_4911 = and(_T_4909, _T_4910) @[lsu_bus_buffer.scala 609:93]
+    node _T_4912 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 609:119]
+    node _T_4913 = and(_T_4911, _T_4912) @[lsu_bus_buffer.scala 609:108]
+    node _T_4914 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 609:82]
+    node _T_4915 = bits(buf_error, 2, 2) @[lsu_bus_buffer.scala 609:104]
+    node _T_4916 = and(_T_4914, _T_4915) @[lsu_bus_buffer.scala 609:93]
+    node _T_4917 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 609:119]
+    node _T_4918 = and(_T_4916, _T_4917) @[lsu_bus_buffer.scala 609:108]
+    node _T_4919 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 609:82]
+    node _T_4920 = bits(buf_error, 3, 3) @[lsu_bus_buffer.scala 609:104]
+    node _T_4921 = and(_T_4919, _T_4920) @[lsu_bus_buffer.scala 609:93]
+    node _T_4922 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 609:119]
+    node _T_4923 = and(_T_4921, _T_4922) @[lsu_bus_buffer.scala 609:108]
+    node _T_4924 = mux(_T_4908, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_4925 = mux(_T_4913, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_4926 = mux(_T_4918, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_4927 = mux(_T_4923, UInt<2>("h03"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_4928 = or(_T_4924, _T_4925) @[Mux.scala 27:72]
+    node _T_4929 = or(_T_4928, _T_4926) @[Mux.scala 27:72]
+    node _T_4930 = or(_T_4929, _T_4927) @[Mux.scala 27:72]
     wire lsu_imprecise_error_store_tag : UInt<2> @[Mux.scala 27:72]
-    lsu_imprecise_error_store_tag <= _T_4919 @[Mux.scala 27:72]
-    node _T_4920 = eq(io.tlu_busbuff.lsu_imprecise_error_store_any, UInt<1>("h00")) @[lsu_bus_buffer.scala 609:97]
-    node _T_4921 = and(io.dctl_busbuff.lsu_nonblock_load_data_error, _T_4920) @[lsu_bus_buffer.scala 609:95]
-    io.tlu_busbuff.lsu_imprecise_error_load_any <= _T_4921 @[lsu_bus_buffer.scala 609:47]
-    node _T_4922 = mux(io.tlu_busbuff.lsu_imprecise_error_store_any, buf_addr[lsu_imprecise_error_store_tag], buf_addr[io.dctl_busbuff.lsu_nonblock_load_data_tag]) @[lsu_bus_buffer.scala 610:53]
-    io.tlu_busbuff.lsu_imprecise_error_addr_any <= _T_4922 @[lsu_bus_buffer.scala 610:47]
-    node _T_4923 = and(io.lsu_axi.aw.valid, io.lsu_axi.aw.ready) @[lsu_bus_buffer.scala 616:59]
-    node _T_4924 = and(io.lsu_axi.w.valid, io.lsu_axi.w.ready) @[lsu_bus_buffer.scala 616:104]
-    node _T_4925 = or(_T_4923, _T_4924) @[lsu_bus_buffer.scala 616:82]
-    node _T_4926 = and(io.lsu_axi.ar.valid, io.lsu_axi.ar.ready) @[lsu_bus_buffer.scala 616:149]
-    node _T_4927 = or(_T_4925, _T_4926) @[lsu_bus_buffer.scala 616:126]
-    io.tlu_busbuff.lsu_pmu_bus_trxn <= _T_4927 @[lsu_bus_buffer.scala 616:35]
-    node _T_4928 = and(io.lsu_busreq_r, io.ldst_dual_r) @[lsu_bus_buffer.scala 617:60]
-    node _T_4929 = and(_T_4928, io.lsu_commit_r) @[lsu_bus_buffer.scala 617:77]
-    io.tlu_busbuff.lsu_pmu_bus_misaligned <= _T_4929 @[lsu_bus_buffer.scala 617:41]
-    node _T_4930 = or(io.tlu_busbuff.lsu_imprecise_error_load_any, io.tlu_busbuff.lsu_imprecise_error_store_any) @[lsu_bus_buffer.scala 618:83]
-    io.tlu_busbuff.lsu_pmu_bus_error <= _T_4930 @[lsu_bus_buffer.scala 618:36]
-    node _T_4931 = eq(io.lsu_axi.aw.ready, UInt<1>("h00")) @[lsu_bus_buffer.scala 620:61]
-    node _T_4932 = and(io.lsu_axi.aw.valid, _T_4931) @[lsu_bus_buffer.scala 620:59]
-    node _T_4933 = eq(io.lsu_axi.w.ready, UInt<1>("h00")) @[lsu_bus_buffer.scala 620:107]
-    node _T_4934 = and(io.lsu_axi.w.valid, _T_4933) @[lsu_bus_buffer.scala 620:105]
-    node _T_4935 = or(_T_4932, _T_4934) @[lsu_bus_buffer.scala 620:83]
-    node _T_4936 = eq(io.lsu_axi.ar.ready, UInt<1>("h00")) @[lsu_bus_buffer.scala 620:153]
-    node _T_4937 = and(io.lsu_axi.ar.valid, _T_4936) @[lsu_bus_buffer.scala 620:151]
-    node _T_4938 = or(_T_4935, _T_4937) @[lsu_bus_buffer.scala 620:128]
-    io.tlu_busbuff.lsu_pmu_bus_busy <= _T_4938 @[lsu_bus_buffer.scala 620:35]
-    reg _T_4939 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 622:49]
-    _T_4939 <= WrPtr0_m @[lsu_bus_buffer.scala 622:49]
-    WrPtr0_r <= _T_4939 @[lsu_bus_buffer.scala 622:12]
-    reg _T_4940 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 623:49]
-    _T_4940 <= WrPtr1_m @[lsu_bus_buffer.scala 623:49]
-    WrPtr1_r <= _T_4940 @[lsu_bus_buffer.scala 623:12]
-    node _T_4941 = eq(io.flush_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 624:75]
-    node _T_4942 = and(io.lsu_busreq_m, _T_4941) @[lsu_bus_buffer.scala 624:73]
-    node _T_4943 = eq(io.ld_full_hit_m, UInt<1>("h00")) @[lsu_bus_buffer.scala 624:89]
-    node _T_4944 = and(_T_4942, _T_4943) @[lsu_bus_buffer.scala 624:87]
-    reg _T_4945 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 624:56]
-    _T_4945 <= _T_4944 @[lsu_bus_buffer.scala 624:56]
-    io.lsu_busreq_r <= _T_4945 @[lsu_bus_buffer.scala 624:19]
-    reg _T_4946 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 625:66]
-    _T_4946 <= io.dctl_busbuff.lsu_nonblock_load_valid_m @[lsu_bus_buffer.scala 625:66]
-    lsu_nonblock_load_valid_r <= _T_4946 @[lsu_bus_buffer.scala 625:29]
+    lsu_imprecise_error_store_tag <= _T_4930 @[Mux.scala 27:72]
+    node _T_4931 = eq(io.tlu_busbuff.lsu_imprecise_error_store_any, UInt<1>("h00")) @[lsu_bus_buffer.scala 611:97]
+    node _T_4932 = and(io.dctl_busbuff.lsu_nonblock_load_data_error, _T_4931) @[lsu_bus_buffer.scala 611:95]
+    io.tlu_busbuff.lsu_imprecise_error_load_any <= _T_4932 @[lsu_bus_buffer.scala 611:47]
+    node _T_4933 = mux(io.tlu_busbuff.lsu_imprecise_error_store_any, buf_addr[lsu_imprecise_error_store_tag], buf_addr[io.dctl_busbuff.lsu_nonblock_load_data_tag]) @[lsu_bus_buffer.scala 612:53]
+    io.tlu_busbuff.lsu_imprecise_error_addr_any <= _T_4933 @[lsu_bus_buffer.scala 612:47]
+    node _T_4934 = and(io.lsu_axi.aw.valid, io.lsu_axi.aw.ready) @[lsu_bus_buffer.scala 618:59]
+    node _T_4935 = and(io.lsu_axi.w.valid, io.lsu_axi.w.ready) @[lsu_bus_buffer.scala 618:104]
+    node _T_4936 = or(_T_4934, _T_4935) @[lsu_bus_buffer.scala 618:82]
+    node _T_4937 = and(io.lsu_axi.ar.valid, io.lsu_axi.ar.ready) @[lsu_bus_buffer.scala 618:149]
+    node _T_4938 = or(_T_4936, _T_4937) @[lsu_bus_buffer.scala 618:126]
+    io.tlu_busbuff.lsu_pmu_bus_trxn <= _T_4938 @[lsu_bus_buffer.scala 618:35]
+    node _T_4939 = and(io.lsu_busreq_r, io.ldst_dual_r) @[lsu_bus_buffer.scala 619:60]
+    node _T_4940 = and(_T_4939, io.lsu_commit_r) @[lsu_bus_buffer.scala 619:77]
+    io.tlu_busbuff.lsu_pmu_bus_misaligned <= _T_4940 @[lsu_bus_buffer.scala 619:41]
+    node _T_4941 = or(io.tlu_busbuff.lsu_imprecise_error_load_any, io.tlu_busbuff.lsu_imprecise_error_store_any) @[lsu_bus_buffer.scala 620:83]
+    io.tlu_busbuff.lsu_pmu_bus_error <= _T_4941 @[lsu_bus_buffer.scala 620:36]
+    node _T_4942 = eq(io.lsu_axi.aw.ready, UInt<1>("h00")) @[lsu_bus_buffer.scala 622:61]
+    node _T_4943 = and(io.lsu_axi.aw.valid, _T_4942) @[lsu_bus_buffer.scala 622:59]
+    node _T_4944 = eq(io.lsu_axi.w.ready, UInt<1>("h00")) @[lsu_bus_buffer.scala 622:107]
+    node _T_4945 = and(io.lsu_axi.w.valid, _T_4944) @[lsu_bus_buffer.scala 622:105]
+    node _T_4946 = or(_T_4943, _T_4945) @[lsu_bus_buffer.scala 622:83]
+    node _T_4947 = eq(io.lsu_axi.ar.ready, UInt<1>("h00")) @[lsu_bus_buffer.scala 622:153]
+    node _T_4948 = and(io.lsu_axi.ar.valid, _T_4947) @[lsu_bus_buffer.scala 622:151]
+    node _T_4949 = or(_T_4946, _T_4948) @[lsu_bus_buffer.scala 622:128]
+    io.tlu_busbuff.lsu_pmu_bus_busy <= _T_4949 @[lsu_bus_buffer.scala 622:35]
+    reg _T_4950 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 624:49]
+    _T_4950 <= WrPtr0_m @[lsu_bus_buffer.scala 624:49]
+    WrPtr0_r <= _T_4950 @[lsu_bus_buffer.scala 624:12]
+    reg _T_4951 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 625:49]
+    _T_4951 <= WrPtr1_m @[lsu_bus_buffer.scala 625:49]
+    WrPtr1_r <= _T_4951 @[lsu_bus_buffer.scala 625:12]
+    node _T_4952 = eq(io.flush_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 626:75]
+    node _T_4953 = and(io.lsu_busreq_m, _T_4952) @[lsu_bus_buffer.scala 626:73]
+    node _T_4954 = eq(io.ld_full_hit_m, UInt<1>("h00")) @[lsu_bus_buffer.scala 626:89]
+    node _T_4955 = and(_T_4953, _T_4954) @[lsu_bus_buffer.scala 626:87]
+    reg _T_4956 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 626:56]
+    _T_4956 <= _T_4955 @[lsu_bus_buffer.scala 626:56]
+    io.lsu_busreq_r <= _T_4956 @[lsu_bus_buffer.scala 626:19]
+    reg _T_4957 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 627:66]
+    _T_4957 <= io.dctl_busbuff.lsu_nonblock_load_valid_m @[lsu_bus_buffer.scala 627:66]
+    lsu_nonblock_load_valid_r <= _T_4957 @[lsu_bus_buffer.scala 627:29]
     
   module lsu_bus_intf : 
     input clock : Clock
     input reset : AsyncReset
-    output io : {flip scan_mode : UInt<1>, flip clk_override : UInt<1>, tlu_busbuff : {lsu_pmu_bus_trxn : UInt<1>, lsu_pmu_bus_misaligned : UInt<1>, lsu_pmu_bus_error : UInt<1>, lsu_pmu_bus_busy : UInt<1>, flip dec_tlu_external_ldfwd_disable : UInt<1>, flip dec_tlu_wb_coalescing_disable : UInt<1>, flip dec_tlu_sideeffect_posted_disable : UInt<1>, lsu_imprecise_error_load_any : UInt<1>, lsu_imprecise_error_store_any : UInt<1>, lsu_imprecise_error_addr_any : UInt<32>}, flip lsu_bus_obuf_c1_clken : UInt<1>, flip lsu_busm_clken : UInt<1>, flip lsu_c1_r_clk : Clock, flip lsu_c2_r_clk : Clock, flip lsu_bus_ibuf_c1_clk : Clock, flip lsu_bus_obuf_c1_clk : Clock, flip lsu_bus_buf_c1_clk : Clock, flip lsu_free_c2_clk : Clock, flip active_clk : Clock, flip lsu_busm_clk : Clock, axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip dec_lsu_valid_raw_d : UInt<1>, flip lsu_busreq_m : UInt<1>, flip lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_pkt_r : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_addr_m : UInt<32>, flip lsu_addr_r : UInt<32>, flip end_addr_m : UInt<32>, flip end_addr_r : UInt<32>, flip ldst_dual_d : UInt<1>, flip ldst_dual_m : UInt<1>, flip ldst_dual_r : UInt<1>, flip store_data_r : UInt<32>, flip dec_tlu_force_halt : UInt<1>, flip lsu_commit_r : UInt<1>, flip is_sideeffects_m : UInt<1>, flip flush_m_up : UInt<1>, flip flush_r : UInt<1>, lsu_busreq_r : UInt<1>, lsu_bus_buffer_pend_any : UInt<1>, lsu_bus_buffer_full_any : UInt<1>, lsu_bus_buffer_empty_any : UInt<1>, bus_read_data_m : UInt<32>, dctl_busbuff : {lsu_nonblock_load_valid_m : UInt<1>, lsu_nonblock_load_tag_m : UInt<2>, lsu_nonblock_load_inv_r : UInt<1>, lsu_nonblock_load_inv_tag_r : UInt<2>, lsu_nonblock_load_data_valid : UInt<1>, lsu_nonblock_load_data_error : UInt<1>, lsu_nonblock_load_data_tag : UInt<2>, lsu_nonblock_load_data : UInt<32>}, flip lsu_bus_clk_en : UInt<1>}
+    output io : {flip scan_mode : UInt<1>, flip clk_override : UInt<1>, tlu_busbuff : {lsu_pmu_bus_trxn : UInt<1>, lsu_pmu_bus_misaligned : UInt<1>, lsu_pmu_bus_error : UInt<1>, lsu_pmu_bus_busy : UInt<1>, flip dec_tlu_external_ldfwd_disable : UInt<1>, flip dec_tlu_wb_coalescing_disable : UInt<1>, flip dec_tlu_sideeffect_posted_disable : UInt<1>, lsu_imprecise_error_load_any : UInt<1>, lsu_imprecise_error_store_any : UInt<1>, lsu_imprecise_error_addr_any : UInt<32>}, flip lsu_bus_obuf_c1_clken : UInt<1>, flip lsu_busm_clken : UInt<1>, flip lsu_c1_r_clk : Clock, flip lsu_c2_r_clk : Clock, flip lsu_bus_ibuf_c1_clk : Clock, flip lsu_bus_obuf_c1_clk : Clock, flip lsu_bus_buf_c1_clk : Clock, flip lsu_free_c2_clk : Clock, flip active_clk : Clock, flip lsu_busm_clk : Clock, axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip dec_lsu_valid_raw_d : UInt<1>, flip lsu_busreq_m : UInt<1>, flip lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_pkt_r : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_addr_m : UInt<32>, flip lsu_addr_r : UInt<32>, flip end_addr_m : UInt<32>, flip end_addr_r : UInt<32>, flip ldst_dual_d : UInt<1>, flip ldst_dual_m : UInt<1>, flip ldst_dual_r : UInt<1>, flip store_data_r : UInt<32>, flip dec_tlu_force_halt : UInt<1>, flip lsu_commit_r : UInt<1>, flip is_sideeffects_m : UInt<1>, flip flush_m_up : UInt<1>, flip flush_r : UInt<1>, lsu_busreq_r : UInt<1>, lsu_bus_buffer_pend_any : UInt<1>, lsu_bus_buffer_full_any : UInt<1>, lsu_bus_buffer_empty_any : UInt<1>, bus_read_data_m : UInt<32>, dctl_busbuff : {lsu_nonblock_load_valid_m : UInt<1>, lsu_nonblock_load_tag_m : UInt<2>, lsu_nonblock_load_inv_r : UInt<1>, lsu_nonblock_load_inv_tag_r : UInt<2>, lsu_nonblock_load_data_valid : UInt<1>, lsu_nonblock_load_data_error : UInt<1>, lsu_nonblock_load_data_tag : UInt<2>, lsu_nonblock_load_data : UInt<32>}, flip lsu_bus_clk_en : UInt<1>}
     
     wire lsu_bus_clk_en_q : UInt<1>
     lsu_bus_clk_en_q <= UInt<1>("h00")
@@ -15030,6 +15281,7 @@ circuit lsu :
     bus_buffer.io.lsu_pkt_m.bits.word <= io.lsu_pkt_m.bits.word @[lsu_bus_intf.scala 117:27]
     bus_buffer.io.lsu_pkt_m.bits.half <= io.lsu_pkt_m.bits.half @[lsu_bus_intf.scala 117:27]
     bus_buffer.io.lsu_pkt_m.bits.by <= io.lsu_pkt_m.bits.by @[lsu_bus_intf.scala 117:27]
+    bus_buffer.io.lsu_pkt_m.bits.stack <= io.lsu_pkt_m.bits.stack @[lsu_bus_intf.scala 117:27]
     bus_buffer.io.lsu_pkt_m.bits.fast_int <= io.lsu_pkt_m.bits.fast_int @[lsu_bus_intf.scala 117:27]
     bus_buffer.io.lsu_pkt_m.valid <= io.lsu_pkt_m.valid @[lsu_bus_intf.scala 117:27]
     bus_buffer.io.lsu_pkt_r.bits.store_data_bypass_m <= io.lsu_pkt_r.bits.store_data_bypass_m @[lsu_bus_intf.scala 118:27]
@@ -15043,6 +15295,7 @@ circuit lsu :
     bus_buffer.io.lsu_pkt_r.bits.word <= io.lsu_pkt_r.bits.word @[lsu_bus_intf.scala 118:27]
     bus_buffer.io.lsu_pkt_r.bits.half <= io.lsu_pkt_r.bits.half @[lsu_bus_intf.scala 118:27]
     bus_buffer.io.lsu_pkt_r.bits.by <= io.lsu_pkt_r.bits.by @[lsu_bus_intf.scala 118:27]
+    bus_buffer.io.lsu_pkt_r.bits.stack <= io.lsu_pkt_r.bits.stack @[lsu_bus_intf.scala 118:27]
     bus_buffer.io.lsu_pkt_r.bits.fast_int <= io.lsu_pkt_r.bits.fast_int @[lsu_bus_intf.scala 118:27]
     bus_buffer.io.lsu_pkt_r.valid <= io.lsu_pkt_r.valid @[lsu_bus_intf.scala 118:27]
     bus_buffer.io.lsu_addr_m <= io.lsu_addr_m @[lsu_bus_intf.scala 121:51]
@@ -15555,7 +15808,7 @@ circuit lsu :
   module lsu : 
     input clock : Clock
     input reset : AsyncReset
-    output io : {flip clk_override : UInt<1>, lsu_dma : {dma_lsc_ctl : {flip dma_dccm_req : UInt<1>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_write : UInt<1>, flip dma_mem_wdata : UInt<64>}, dma_dccm_ctl : {flip dma_mem_addr : UInt<32>, flip dma_mem_wdata : UInt<64>, dccm_dma_rvalid : UInt<1>, dccm_dma_ecc_error : UInt<1>, dccm_dma_rtag : UInt<3>, dccm_dma_rdata : UInt<64>}, dccm_ready : UInt<1>, flip dma_mem_tag : UInt<3>}, lsu_pic : {picm_wren : UInt<1>, picm_rden : UInt<1>, picm_mken : UInt<1>, picm_rdaddr : UInt<32>, picm_wraddr : UInt<32>, picm_wr_data : UInt<32>, flip picm_rd_data : UInt<32>}, lsu_exu : {flip exu_lsu_rs1_d : UInt<32>, flip exu_lsu_rs2_d : UInt<32>}, lsu_dec : {tlu_busbuff : {lsu_pmu_bus_trxn : UInt<1>, lsu_pmu_bus_misaligned : UInt<1>, lsu_pmu_bus_error : UInt<1>, lsu_pmu_bus_busy : UInt<1>, flip dec_tlu_external_ldfwd_disable : UInt<1>, flip dec_tlu_wb_coalescing_disable : UInt<1>, flip dec_tlu_sideeffect_posted_disable : UInt<1>, lsu_imprecise_error_load_any : UInt<1>, lsu_imprecise_error_store_any : UInt<1>, lsu_imprecise_error_addr_any : UInt<32>}, dctl_busbuff : {lsu_nonblock_load_valid_m : UInt<1>, lsu_nonblock_load_tag_m : UInt<2>, lsu_nonblock_load_inv_r : UInt<1>, lsu_nonblock_load_inv_tag_r : UInt<2>, lsu_nonblock_load_data_valid : UInt<1>, lsu_nonblock_load_data_error : UInt<1>, lsu_nonblock_load_data_tag : UInt<2>, lsu_nonblock_load_data : UInt<32>}}, flip dccm : {flip wren : UInt<1>, flip rden : UInt<1>, flip wr_addr_lo : UInt<16>, flip wr_addr_hi : UInt<16>, flip rd_addr_lo : UInt<16>, flip rd_addr_hi : UInt<16>, flip wr_data_lo : UInt<39>, flip wr_data_hi : UInt<39>, rd_data_lo : UInt<39>, rd_data_hi : UInt<39>}, lsu_tlu : {lsu_pmu_load_external_m : UInt<1>, lsu_pmu_store_external_m : UInt<1>}, axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip dec_tlu_flush_lower_r : UInt<1>, flip dec_tlu_i0_kill_writeb_r : UInt<1>, flip dec_tlu_force_halt : UInt<1>, flip dec_tlu_core_ecc_disable : UInt<1>, flip dec_lsu_offset_d : UInt<12>, flip lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip trigger_pkt_any : {select : UInt<1>, match_pkt : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip dec_lsu_valid_raw_d : UInt<1>, flip dec_tlu_mrac_ff : UInt<32>, lsu_result_m : UInt<32>, lsu_result_corr_r : UInt<32>, lsu_load_stall_any : UInt<1>, lsu_store_stall_any : UInt<1>, lsu_fastint_stall_any : UInt<1>, lsu_idle_any : UInt<1>, lsu_active : UInt<1>, lsu_fir_addr : UInt<31>, lsu_fir_error : UInt<2>, lsu_single_ecc_error_incr : UInt<1>, lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, lsu_pmu_misaligned_m : UInt<1>, lsu_trigger_match_m : UInt<4>, flip lsu_bus_clk_en : UInt<1>, flip scan_mode : UInt<1>, flip active_clk : Clock}
+    output io : {flip clk_override : UInt<1>, lsu_dma : {dma_lsc_ctl : {flip dma_dccm_req : UInt<1>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_write : UInt<1>, flip dma_mem_wdata : UInt<64>}, dma_dccm_ctl : {flip dma_mem_addr : UInt<32>, flip dma_mem_wdata : UInt<64>, dccm_dma_rvalid : UInt<1>, dccm_dma_ecc_error : UInt<1>, dccm_dma_rtag : UInt<3>, dccm_dma_rdata : UInt<64>}, dccm_ready : UInt<1>, flip dma_mem_tag : UInt<3>}, lsu_pic : {picm_wren : UInt<1>, picm_rden : UInt<1>, picm_mken : UInt<1>, picm_rdaddr : UInt<32>, picm_wraddr : UInt<32>, picm_wr_data : UInt<32>, flip picm_rd_data : UInt<32>}, lsu_exu : {flip exu_lsu_rs1_d : UInt<32>, flip exu_lsu_rs2_d : UInt<32>}, lsu_dec : {tlu_busbuff : {lsu_pmu_bus_trxn : UInt<1>, lsu_pmu_bus_misaligned : UInt<1>, lsu_pmu_bus_error : UInt<1>, lsu_pmu_bus_busy : UInt<1>, flip dec_tlu_external_ldfwd_disable : UInt<1>, flip dec_tlu_wb_coalescing_disable : UInt<1>, flip dec_tlu_sideeffect_posted_disable : UInt<1>, lsu_imprecise_error_load_any : UInt<1>, lsu_imprecise_error_store_any : UInt<1>, lsu_imprecise_error_addr_any : UInt<32>}, dctl_busbuff : {lsu_nonblock_load_valid_m : UInt<1>, lsu_nonblock_load_tag_m : UInt<2>, lsu_nonblock_load_inv_r : UInt<1>, lsu_nonblock_load_inv_tag_r : UInt<2>, lsu_nonblock_load_data_valid : UInt<1>, lsu_nonblock_load_data_error : UInt<1>, lsu_nonblock_load_data_tag : UInt<2>, lsu_nonblock_load_data : UInt<32>}}, flip dccm : {flip wren : UInt<1>, flip rden : UInt<1>, flip wr_addr_lo : UInt<16>, flip wr_addr_hi : UInt<16>, flip rd_addr_lo : UInt<16>, flip rd_addr_hi : UInt<16>, flip wr_data_lo : UInt<39>, flip wr_data_hi : UInt<39>, rd_data_lo : UInt<39>, rd_data_hi : UInt<39>}, lsu_tlu : {lsu_pmu_load_external_m : UInt<1>, lsu_pmu_store_external_m : UInt<1>}, axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip dec_tlu_flush_lower_r : UInt<1>, flip dec_tlu_i0_kill_writeb_r : UInt<1>, flip dec_tlu_force_halt : UInt<1>, flip dec_tlu_core_ecc_disable : UInt<1>, flip dec_lsu_offset_d : UInt<12>, flip lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip trigger_pkt_any : {select : UInt<1>, match_pkt : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip dec_lsu_valid_raw_d : UInt<1>, flip dec_tlu_mrac_ff : UInt<32>, lsu_result_m : UInt<32>, lsu_result_corr_r : UInt<32>, lsu_load_stall_any : UInt<1>, lsu_store_stall_any : UInt<1>, lsu_fastint_stall_any : UInt<1>, lsu_idle_any : UInt<1>, lsu_active : UInt<1>, lsu_fir_addr : UInt<31>, lsu_fir_error : UInt<2>, lsu_single_ecc_error_incr : UInt<1>, lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, lsu_pmu_misaligned_m : UInt<1>, lsu_trigger_match_m : UInt<4>, flip lsu_bus_clk_en : UInt<1>, flip scan_mode : UInt<1>, flip active_clk : Clock}
     
     wire dma_dccm_wdata : UInt<64>
     dma_dccm_wdata <= UInt<64>("h00")
@@ -15573,614 +15826,671 @@ circuit lsu :
     lsu_busm_clken <= UInt<1>("h00")
     wire lsu_bus_obuf_c1_clken : UInt<1>
     lsu_bus_obuf_c1_clken <= UInt<1>("h00")
-    inst lsu_lsc_ctl of lsu_lsc_ctl @[lsu.scala 65:30]
+    wire lsu_addr_d : UInt<32>
+    lsu_addr_d <= UInt<32>("h00")
+    wire lsu_addr_m : UInt<32>
+    lsu_addr_m <= UInt<32>("h00")
+    wire lsu_addr_r : UInt<32>
+    lsu_addr_r <= UInt<32>("h00")
+    wire end_addr_d : UInt<32>
+    end_addr_d <= UInt<32>("h00")
+    wire end_addr_m : UInt<32>
+    end_addr_m <= UInt<32>("h00")
+    wire end_addr_r : UInt<32>
+    end_addr_r <= UInt<32>("h00")
+    wire lsu_busreq_r : UInt<1>
+    lsu_busreq_r <= UInt<1>("h00")
+    inst lsu_lsc_ctl of lsu_lsc_ctl @[lsu.scala 70:30]
     lsu_lsc_ctl.clock <= clock
     lsu_lsc_ctl.reset <= reset
-    io.lsu_result_m <= lsu_lsc_ctl.io.lsu_result_m @[lsu.scala 66:19]
-    io.lsu_result_corr_r <= lsu_lsc_ctl.io.lsu_result_corr_r @[lsu.scala 67:24]
-    inst dccm_ctl of lsu_dccm_ctl @[lsu.scala 68:30]
+    io.lsu_result_m <= lsu_lsc_ctl.io.lsu_result_m @[lsu.scala 71:19]
+    io.lsu_result_corr_r <= lsu_lsc_ctl.io.lsu_result_corr_r @[lsu.scala 72:24]
+    inst dccm_ctl of lsu_dccm_ctl @[lsu.scala 73:30]
     dccm_ctl.clock <= clock
     dccm_ctl.reset <= reset
-    inst stbuf of lsu_stbuf @[lsu.scala 69:30]
+    inst stbuf of lsu_stbuf @[lsu.scala 74:30]
     stbuf.clock <= clock
     stbuf.reset <= reset
-    inst ecc of lsu_ecc @[lsu.scala 70:30]
+    inst ecc of lsu_ecc @[lsu.scala 75:30]
     ecc.clock <= clock
     ecc.reset <= reset
-    inst trigger of lsu_trigger @[lsu.scala 71:30]
+    inst trigger of lsu_trigger @[lsu.scala 76:30]
     trigger.clock <= clock
     trigger.reset <= reset
-    inst clkdomain of lsu_clkdomain @[lsu.scala 72:30]
+    inst clkdomain of lsu_clkdomain @[lsu.scala 77:30]
     clkdomain.clock <= clock
     clkdomain.reset <= reset
-    inst bus_intf of lsu_bus_intf @[lsu.scala 73:30]
+    inst bus_intf of lsu_bus_intf @[lsu.scala 78:30]
     bus_intf.clock <= clock
     bus_intf.reset <= reset
-    node lsu_raw_fwd_lo_m = orr(stbuf.io.stbuf_fwdbyteen_lo_m) @[lsu.scala 75:56]
-    node lsu_raw_fwd_hi_m = orr(stbuf.io.stbuf_fwdbyteen_hi_m) @[lsu.scala 76:56]
-    node _T = or(stbuf.io.lsu_stbuf_full_any, bus_intf.io.lsu_bus_buffer_full_any) @[lsu.scala 79:57]
-    node _T_1 = or(_T, dccm_ctl.io.ld_single_ecc_error_r_ff) @[lsu.scala 79:95]
-    io.lsu_store_stall_any <= _T_1 @[lsu.scala 79:26]
-    node _T_2 = or(bus_intf.io.lsu_bus_buffer_full_any, dccm_ctl.io.ld_single_ecc_error_r_ff) @[lsu.scala 80:64]
-    io.lsu_load_stall_any <= _T_2 @[lsu.scala 80:25]
-    io.lsu_fastint_stall_any <= dccm_ctl.io.ld_single_ecc_error_r @[lsu.scala 81:28]
-    node _T_3 = eq(lsu_lsc_ctl.io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu.scala 86:58]
-    node _T_4 = and(lsu_lsc_ctl.io.lsu_pkt_m.valid, _T_3) @[lsu.scala 86:56]
-    node _T_5 = or(lsu_lsc_ctl.io.addr_in_dccm_m, lsu_lsc_ctl.io.addr_in_pic_m) @[lsu.scala 86:126]
-    node _T_6 = and(_T_4, _T_5) @[lsu.scala 86:93]
-    node ldst_nodma_mtor = and(_T_6, lsu_lsc_ctl.io.lsu_pkt_m.bits.store) @[lsu.scala 86:158]
-    node _T_7 = or(io.dec_lsu_valid_raw_d, ldst_nodma_mtor) @[lsu.scala 87:53]
-    node _T_8 = or(_T_7, dccm_ctl.io.ld_single_ecc_error_r_ff) @[lsu.scala 87:71]
-    node _T_9 = eq(_T_8, UInt<1>("h00")) @[lsu.scala 87:28]
-    io.lsu_dma.dccm_ready <= _T_9 @[lsu.scala 87:25]
-    node _T_10 = and(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, io.lsu_dma.dma_lsc_ctl.dma_mem_write) @[lsu.scala 88:58]
-    node _T_11 = and(_T_10, lsu_lsc_ctl.io.addr_in_dccm_d) @[lsu.scala 88:97]
-    node _T_12 = bits(io.lsu_dma.dma_lsc_ctl.dma_mem_sz, 1, 1) @[lsu.scala 88:164]
-    node dma_dccm_wen = and(_T_11, _T_12) @[lsu.scala 88:129]
-    node _T_13 = and(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, io.lsu_dma.dma_lsc_ctl.dma_mem_write) @[lsu.scala 89:58]
-    node dma_pic_wen = and(_T_13, lsu_lsc_ctl.io.addr_in_pic_d) @[lsu.scala 89:97]
-    node _T_14 = bits(io.lsu_dma.dma_lsc_ctl.dma_mem_addr, 2, 0) @[lsu.scala 90:100]
+    node lsu_raw_fwd_lo_m = orr(stbuf.io.stbuf_fwdbyteen_lo_m) @[lsu.scala 80:56]
+    node lsu_raw_fwd_hi_m = orr(stbuf.io.stbuf_fwdbyteen_hi_m) @[lsu.scala 81:56]
+    node _T = or(stbuf.io.lsu_stbuf_full_any, bus_intf.io.lsu_bus_buffer_full_any) @[lsu.scala 84:57]
+    node _T_1 = or(_T, dccm_ctl.io.ld_single_ecc_error_r_ff) @[lsu.scala 84:95]
+    io.lsu_store_stall_any <= _T_1 @[lsu.scala 84:26]
+    node _T_2 = or(bus_intf.io.lsu_bus_buffer_full_any, dccm_ctl.io.ld_single_ecc_error_r_ff) @[lsu.scala 85:64]
+    io.lsu_load_stall_any <= _T_2 @[lsu.scala 85:25]
+    io.lsu_fastint_stall_any <= dccm_ctl.io.ld_single_ecc_error_r @[lsu.scala 86:28]
+    node _T_3 = eq(lsu_lsc_ctl.io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu.scala 91:58]
+    node _T_4 = and(lsu_lsc_ctl.io.lsu_pkt_m.valid, _T_3) @[lsu.scala 91:56]
+    node _T_5 = or(lsu_lsc_ctl.io.addr_in_dccm_m, lsu_lsc_ctl.io.addr_in_pic_m) @[lsu.scala 91:126]
+    node _T_6 = and(_T_4, _T_5) @[lsu.scala 91:93]
+    node ldst_nodma_mtor = and(_T_6, lsu_lsc_ctl.io.lsu_pkt_m.bits.store) @[lsu.scala 91:158]
+    node _T_7 = or(io.dec_lsu_valid_raw_d, ldst_nodma_mtor) @[lsu.scala 92:53]
+    node _T_8 = or(_T_7, dccm_ctl.io.ld_single_ecc_error_r_ff) @[lsu.scala 92:71]
+    node _T_9 = eq(_T_8, UInt<1>("h00")) @[lsu.scala 92:28]
+    io.lsu_dma.dccm_ready <= _T_9 @[lsu.scala 92:25]
+    node _T_10 = and(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, io.lsu_dma.dma_lsc_ctl.dma_mem_write) @[lsu.scala 93:58]
+    node _T_11 = and(_T_10, lsu_lsc_ctl.io.addr_in_dccm_d) @[lsu.scala 93:97]
+    node _T_12 = bits(io.lsu_dma.dma_lsc_ctl.dma_mem_sz, 1, 1) @[lsu.scala 93:164]
+    node dma_dccm_wen = and(_T_11, _T_12) @[lsu.scala 93:129]
+    node _T_13 = and(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, io.lsu_dma.dma_lsc_ctl.dma_mem_write) @[lsu.scala 94:58]
+    node dma_pic_wen = and(_T_13, lsu_lsc_ctl.io.addr_in_pic_d) @[lsu.scala 94:97]
+    node _T_14 = bits(io.lsu_dma.dma_lsc_ctl.dma_mem_addr, 2, 0) @[lsu.scala 95:100]
     node _T_15 = cat(_T_14, UInt<3>("h00")) @[Cat.scala 29:58]
-    node _T_16 = dshr(io.lsu_dma.dma_lsc_ctl.dma_mem_wdata, _T_15) @[lsu.scala 90:58]
-    dma_dccm_wdata <= _T_16 @[lsu.scala 90:18]
-    node _T_17 = bits(dma_dccm_wdata, 63, 32) @[lsu.scala 91:38]
-    dma_dccm_wdata_hi <= _T_17 @[lsu.scala 91:21]
-    node _T_18 = bits(dma_dccm_wdata, 31, 0) @[lsu.scala 92:38]
-    dma_dccm_wdata_lo <= _T_18 @[lsu.scala 92:21]
-    node _T_19 = eq(lsu_lsc_ctl.io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu.scala 101:58]
-    node _T_20 = and(lsu_lsc_ctl.io.lsu_pkt_m.valid, _T_19) @[lsu.scala 101:56]
-    node _T_21 = eq(lsu_lsc_ctl.io.lsu_pkt_r.bits.dma, UInt<1>("h00")) @[lsu.scala 101:130]
-    node _T_22 = and(lsu_lsc_ctl.io.lsu_pkt_r.valid, _T_21) @[lsu.scala 101:128]
-    node _T_23 = or(_T_20, _T_22) @[lsu.scala 101:94]
-    node _T_24 = eq(_T_23, UInt<1>("h00")) @[lsu.scala 101:22]
-    node _T_25 = and(_T_24, bus_intf.io.lsu_bus_buffer_empty_any) @[lsu.scala 101:167]
-    io.lsu_idle_any <= _T_25 @[lsu.scala 101:19]
-    node _T_26 = or(lsu_lsc_ctl.io.lsu_pkt_m.valid, lsu_lsc_ctl.io.lsu_pkt_r.valid) @[lsu.scala 102:52]
-    node _T_27 = or(_T_26, dccm_ctl.io.ld_single_ecc_error_r_ff) @[lsu.scala 102:85]
-    node _T_28 = eq(bus_intf.io.lsu_bus_buffer_empty_any, UInt<1>("h00")) @[lsu.scala 102:127]
-    node _T_29 = or(_T_27, _T_28) @[lsu.scala 102:125]
-    io.lsu_active <= _T_29 @[lsu.scala 102:17]
-    node _T_30 = and(lsu_lsc_ctl.io.lsu_pkt_r.valid, lsu_lsc_ctl.io.lsu_pkt_r.bits.store) @[lsu.scala 104:61]
-    node _T_31 = and(_T_30, lsu_lsc_ctl.io.addr_in_dccm_r) @[lsu.scala 104:99]
-    node _T_32 = eq(io.dec_tlu_i0_kill_writeb_r, UInt<1>("h00")) @[lsu.scala 104:133]
-    node _T_33 = and(_T_31, _T_32) @[lsu.scala 104:131]
-    node _T_34 = eq(lsu_lsc_ctl.io.lsu_pkt_r.bits.dma, UInt<1>("h00")) @[lsu.scala 104:145]
-    node _T_35 = or(lsu_lsc_ctl.io.lsu_pkt_r.bits.by, lsu_lsc_ctl.io.lsu_pkt_r.bits.half) @[lsu.scala 104:217]
-    node _T_36 = eq(ecc.io.lsu_double_ecc_error_r, UInt<1>("h00")) @[lsu.scala 104:257]
-    node _T_37 = and(_T_35, _T_36) @[lsu.scala 104:255]
-    node _T_38 = or(_T_34, _T_37) @[lsu.scala 104:180]
-    node store_stbuf_reqvld_r = and(_T_33, _T_38) @[lsu.scala 104:142]
-    node _T_39 = or(lsu_lsc_ctl.io.lsu_pkt_m.bits.load, lsu_lsc_ctl.io.lsu_pkt_m.bits.store) @[lsu.scala 106:90]
-    node _T_40 = and(lsu_lsc_ctl.io.lsu_pkt_m.valid, _T_39) @[lsu.scala 106:52]
-    node _T_41 = or(lsu_lsc_ctl.io.addr_in_dccm_m, lsu_lsc_ctl.io.addr_in_pic_m) @[lsu.scala 106:162]
-    node lsu_cmpen_m = and(_T_40, _T_41) @[lsu.scala 106:129]
-    node _T_42 = or(lsu_lsc_ctl.io.lsu_pkt_m.bits.load, lsu_lsc_ctl.io.lsu_pkt_m.bits.store) @[lsu.scala 108:92]
-    node _T_43 = and(_T_42, lsu_lsc_ctl.io.addr_external_m) @[lsu.scala 108:131]
-    node _T_44 = and(lsu_lsc_ctl.io.lsu_pkt_m.valid, _T_43) @[lsu.scala 108:53]
-    node _T_45 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[lsu.scala 108:167]
-    node _T_46 = and(_T_44, _T_45) @[lsu.scala 108:165]
-    node _T_47 = eq(lsu_lsc_ctl.io.lsu_exc_m, UInt<1>("h00")) @[lsu.scala 108:181]
-    node _T_48 = and(_T_46, _T_47) @[lsu.scala 108:179]
-    node _T_49 = eq(lsu_lsc_ctl.io.lsu_pkt_m.bits.fast_int, UInt<1>("h00")) @[lsu.scala 108:209]
-    node lsu_busreq_m = and(_T_48, _T_49) @[lsu.scala 108:207]
-    node _T_50 = bits(lsu_lsc_ctl.io.lsu_addr_d, 2, 2) @[lsu.scala 110:47]
-    node _T_51 = bits(lsu_lsc_ctl.io.end_addr_d, 2, 2) @[lsu.scala 110:80]
-    node ldst_dual_d = neq(_T_50, _T_51) @[lsu.scala 110:51]
-    node _T_52 = bits(lsu_lsc_ctl.io.lsu_addr_m, 2, 2) @[lsu.scala 111:47]
-    node _T_53 = bits(lsu_lsc_ctl.io.end_addr_m, 2, 2) @[lsu.scala 111:80]
-    node ldst_dual_m = neq(_T_52, _T_53) @[lsu.scala 111:51]
-    node _T_54 = bits(lsu_lsc_ctl.io.lsu_addr_r, 2, 2) @[lsu.scala 112:47]
-    node _T_55 = bits(lsu_lsc_ctl.io.end_addr_r, 2, 2) @[lsu.scala 112:80]
-    node ldst_dual_r = neq(_T_54, _T_55) @[lsu.scala 112:51]
-    node _T_56 = bits(lsu_lsc_ctl.io.lsu_addr_m, 0, 0) @[lsu.scala 114:127]
-    node _T_57 = and(lsu_lsc_ctl.io.lsu_pkt_m.bits.half, _T_56) @[lsu.scala 114:100]
-    node _T_58 = bits(lsu_lsc_ctl.io.lsu_addr_m, 1, 0) @[lsu.scala 114:197]
-    node _T_59 = orr(_T_58) @[lsu.scala 114:203]
-    node _T_60 = and(lsu_lsc_ctl.io.lsu_pkt_m.bits.word, _T_59) @[lsu.scala 114:170]
-    node _T_61 = or(_T_57, _T_60) @[lsu.scala 114:132]
-    node _T_62 = and(lsu_lsc_ctl.io.lsu_pkt_m.valid, _T_61) @[lsu.scala 114:61]
-    io.lsu_pmu_misaligned_m <= _T_62 @[lsu.scala 114:27]
-    node _T_63 = and(lsu_lsc_ctl.io.lsu_pkt_m.valid, lsu_lsc_ctl.io.lsu_pkt_m.bits.load) @[lsu.scala 115:73]
-    node _T_64 = and(_T_63, lsu_lsc_ctl.io.addr_external_m) @[lsu.scala 115:110]
-    io.lsu_tlu.lsu_pmu_load_external_m <= _T_64 @[lsu.scala 115:39]
-    node _T_65 = and(lsu_lsc_ctl.io.lsu_pkt_m.valid, lsu_lsc_ctl.io.lsu_pkt_m.bits.store) @[lsu.scala 116:73]
-    node _T_66 = and(_T_65, lsu_lsc_ctl.io.addr_external_m) @[lsu.scala 116:111]
-    io.lsu_tlu.lsu_pmu_store_external_m <= _T_66 @[lsu.scala 116:39]
-    lsu_lsc_ctl.io.clk_override <= io.clk_override @[lsu.scala 120:46]
-    lsu_lsc_ctl.io.lsu_c1_m_clk <= clkdomain.io.lsu_c1_m_clk @[lsu.scala 121:46]
-    lsu_lsc_ctl.io.lsu_c1_r_clk <= clkdomain.io.lsu_c1_r_clk @[lsu.scala 122:46]
-    lsu_lsc_ctl.io.lsu_c2_m_clk <= clkdomain.io.lsu_c2_m_clk @[lsu.scala 123:46]
-    lsu_lsc_ctl.io.lsu_c2_r_clk <= clkdomain.io.lsu_c2_r_clk @[lsu.scala 124:46]
-    lsu_lsc_ctl.io.lsu_store_c1_m_clk <= clkdomain.io.lsu_store_c1_m_clk @[lsu.scala 125:46]
-    lsu_lsc_ctl.io.lsu_ld_data_r <= dccm_ctl.io.lsu_ld_data_r @[lsu.scala 126:46]
-    lsu_lsc_ctl.io.lsu_ld_data_corr_r <= dccm_ctl.io.lsu_ld_data_corr_r @[lsu.scala 127:46]
-    lsu_lsc_ctl.io.lsu_single_ecc_error_r <= ecc.io.lsu_single_ecc_error_r @[lsu.scala 128:46]
-    lsu_lsc_ctl.io.lsu_double_ecc_error_r <= ecc.io.lsu_double_ecc_error_r @[lsu.scala 129:46]
-    lsu_lsc_ctl.io.lsu_ld_data_m <= dccm_ctl.io.lsu_ld_data_m @[lsu.scala 130:46]
-    lsu_lsc_ctl.io.lsu_single_ecc_error_m <= ecc.io.lsu_single_ecc_error_m @[lsu.scala 131:46]
-    lsu_lsc_ctl.io.lsu_double_ecc_error_m <= ecc.io.lsu_double_ecc_error_m @[lsu.scala 132:46]
-    lsu_lsc_ctl.io.flush_m_up <= io.dec_tlu_flush_lower_r @[lsu.scala 133:46]
-    lsu_lsc_ctl.io.flush_r <= io.dec_tlu_i0_kill_writeb_r @[lsu.scala 134:46]
-    lsu_lsc_ctl.io.ldst_dual_d <= ldst_dual_d @[lsu.scala 135:46]
-    lsu_lsc_ctl.io.ldst_dual_m <= ldst_dual_m @[lsu.scala 136:46]
-    lsu_lsc_ctl.io.ldst_dual_r <= ldst_dual_r @[lsu.scala 137:46]
-    lsu_lsc_ctl.io.lsu_exu.exu_lsu_rs2_d <= io.lsu_exu.exu_lsu_rs2_d @[lsu.scala 138:46]
-    lsu_lsc_ctl.io.lsu_exu.exu_lsu_rs1_d <= io.lsu_exu.exu_lsu_rs1_d @[lsu.scala 138:46]
-    lsu_lsc_ctl.io.lsu_p.bits.store_data_bypass_m <= io.lsu_p.bits.store_data_bypass_m @[lsu.scala 139:46]
-    lsu_lsc_ctl.io.lsu_p.bits.load_ldst_bypass_d <= io.lsu_p.bits.load_ldst_bypass_d @[lsu.scala 139:46]
-    lsu_lsc_ctl.io.lsu_p.bits.store_data_bypass_d <= io.lsu_p.bits.store_data_bypass_d @[lsu.scala 139:46]
-    lsu_lsc_ctl.io.lsu_p.bits.dma <= io.lsu_p.bits.dma @[lsu.scala 139:46]
-    lsu_lsc_ctl.io.lsu_p.bits.unsign <= io.lsu_p.bits.unsign @[lsu.scala 139:46]
-    lsu_lsc_ctl.io.lsu_p.bits.store <= io.lsu_p.bits.store @[lsu.scala 139:46]
-    lsu_lsc_ctl.io.lsu_p.bits.load <= io.lsu_p.bits.load @[lsu.scala 139:46]
-    lsu_lsc_ctl.io.lsu_p.bits.dword <= io.lsu_p.bits.dword @[lsu.scala 139:46]
-    lsu_lsc_ctl.io.lsu_p.bits.word <= io.lsu_p.bits.word @[lsu.scala 139:46]
-    lsu_lsc_ctl.io.lsu_p.bits.half <= io.lsu_p.bits.half @[lsu.scala 139:46]
-    lsu_lsc_ctl.io.lsu_p.bits.by <= io.lsu_p.bits.by @[lsu.scala 139:46]
-    lsu_lsc_ctl.io.lsu_p.bits.fast_int <= io.lsu_p.bits.fast_int @[lsu.scala 139:46]
-    lsu_lsc_ctl.io.lsu_p.valid <= io.lsu_p.valid @[lsu.scala 139:46]
-    lsu_lsc_ctl.io.dec_lsu_valid_raw_d <= io.dec_lsu_valid_raw_d @[lsu.scala 140:46]
-    lsu_lsc_ctl.io.dec_lsu_offset_d <= io.dec_lsu_offset_d @[lsu.scala 141:46]
-    lsu_lsc_ctl.io.picm_mask_data_m <= dccm_ctl.io.picm_mask_data_m @[lsu.scala 142:46]
-    lsu_lsc_ctl.io.bus_read_data_m <= bus_intf.io.bus_read_data_m @[lsu.scala 143:46]
-    lsu_lsc_ctl.io.dma_lsc_ctl.dma_mem_wdata <= io.lsu_dma.dma_lsc_ctl.dma_mem_wdata @[lsu.scala 144:38]
-    lsu_lsc_ctl.io.dma_lsc_ctl.dma_mem_write <= io.lsu_dma.dma_lsc_ctl.dma_mem_write @[lsu.scala 144:38]
-    lsu_lsc_ctl.io.dma_lsc_ctl.dma_mem_sz <= io.lsu_dma.dma_lsc_ctl.dma_mem_sz @[lsu.scala 144:38]
-    lsu_lsc_ctl.io.dma_lsc_ctl.dma_mem_addr <= io.lsu_dma.dma_lsc_ctl.dma_mem_addr @[lsu.scala 144:38]
-    lsu_lsc_ctl.io.dma_lsc_ctl.dma_dccm_req <= io.lsu_dma.dma_lsc_ctl.dma_dccm_req @[lsu.scala 144:38]
-    lsu_lsc_ctl.io.dec_tlu_mrac_ff <= io.dec_tlu_mrac_ff @[lsu.scala 145:46]
-    lsu_lsc_ctl.io.scan_mode <= io.scan_mode @[lsu.scala 146:46]
-    io.lsu_single_ecc_error_incr <= lsu_lsc_ctl.io.lsu_single_ecc_error_incr @[lsu.scala 149:49]
-    io.lsu_error_pkt_r.bits.addr <= lsu_lsc_ctl.io.lsu_error_pkt_r.bits.addr @[lsu.scala 150:49]
-    io.lsu_error_pkt_r.bits.mscause <= lsu_lsc_ctl.io.lsu_error_pkt_r.bits.mscause @[lsu.scala 150:49]
-    io.lsu_error_pkt_r.bits.exc_type <= lsu_lsc_ctl.io.lsu_error_pkt_r.bits.exc_type @[lsu.scala 150:49]
-    io.lsu_error_pkt_r.bits.inst_type <= lsu_lsc_ctl.io.lsu_error_pkt_r.bits.inst_type @[lsu.scala 150:49]
-    io.lsu_error_pkt_r.bits.single_ecc_error <= lsu_lsc_ctl.io.lsu_error_pkt_r.bits.single_ecc_error @[lsu.scala 150:49]
-    io.lsu_error_pkt_r.valid <= lsu_lsc_ctl.io.lsu_error_pkt_r.valid @[lsu.scala 150:49]
-    io.lsu_fir_addr <= lsu_lsc_ctl.io.lsu_fir_addr @[lsu.scala 151:49]
-    io.lsu_fir_error <= lsu_lsc_ctl.io.lsu_fir_error @[lsu.scala 152:49]
-    dccm_ctl.io.clk_override <= io.clk_override @[lsu.scala 155:46]
-    dccm_ctl.io.ldst_dual_m <= ldst_dual_m @[lsu.scala 156:46]
-    dccm_ctl.io.ldst_dual_r <= ldst_dual_r @[lsu.scala 157:46]
-    dccm_ctl.io.lsu_c2_m_clk <= clkdomain.io.lsu_c2_m_clk @[lsu.scala 158:46]
-    dccm_ctl.io.lsu_c2_r_clk <= clkdomain.io.lsu_c2_r_clk @[lsu.scala 159:46]
-    dccm_ctl.io.lsu_free_c2_clk <= clkdomain.io.lsu_free_c2_clk @[lsu.scala 160:46]
-    dccm_ctl.io.lsu_c1_r_clk <= clkdomain.io.lsu_c1_r_clk @[lsu.scala 161:46]
-    dccm_ctl.io.lsu_store_c1_r_clk <= clkdomain.io.lsu_store_c1_r_clk @[lsu.scala 162:46]
-    dccm_ctl.io.lsu_pkt_d.bits.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_d.bits.store_data_bypass_m @[lsu.scala 163:46]
-    dccm_ctl.io.lsu_pkt_d.bits.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_d.bits.load_ldst_bypass_d @[lsu.scala 163:46]
-    dccm_ctl.io.lsu_pkt_d.bits.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_d.bits.store_data_bypass_d @[lsu.scala 163:46]
-    dccm_ctl.io.lsu_pkt_d.bits.dma <= lsu_lsc_ctl.io.lsu_pkt_d.bits.dma @[lsu.scala 163:46]
-    dccm_ctl.io.lsu_pkt_d.bits.unsign <= lsu_lsc_ctl.io.lsu_pkt_d.bits.unsign @[lsu.scala 163:46]
-    dccm_ctl.io.lsu_pkt_d.bits.store <= lsu_lsc_ctl.io.lsu_pkt_d.bits.store @[lsu.scala 163:46]
-    dccm_ctl.io.lsu_pkt_d.bits.load <= lsu_lsc_ctl.io.lsu_pkt_d.bits.load @[lsu.scala 163:46]
-    dccm_ctl.io.lsu_pkt_d.bits.dword <= lsu_lsc_ctl.io.lsu_pkt_d.bits.dword @[lsu.scala 163:46]
-    dccm_ctl.io.lsu_pkt_d.bits.word <= lsu_lsc_ctl.io.lsu_pkt_d.bits.word @[lsu.scala 163:46]
-    dccm_ctl.io.lsu_pkt_d.bits.half <= lsu_lsc_ctl.io.lsu_pkt_d.bits.half @[lsu.scala 163:46]
-    dccm_ctl.io.lsu_pkt_d.bits.by <= lsu_lsc_ctl.io.lsu_pkt_d.bits.by @[lsu.scala 163:46]
-    dccm_ctl.io.lsu_pkt_d.bits.fast_int <= lsu_lsc_ctl.io.lsu_pkt_d.bits.fast_int @[lsu.scala 163:46]
-    dccm_ctl.io.lsu_pkt_d.valid <= lsu_lsc_ctl.io.lsu_pkt_d.valid @[lsu.scala 163:46]
-    dccm_ctl.io.lsu_pkt_m.bits.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store_data_bypass_m @[lsu.scala 164:46]
-    dccm_ctl.io.lsu_pkt_m.bits.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.bits.load_ldst_bypass_d @[lsu.scala 164:46]
-    dccm_ctl.io.lsu_pkt_m.bits.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store_data_bypass_d @[lsu.scala 164:46]
-    dccm_ctl.io.lsu_pkt_m.bits.dma <= lsu_lsc_ctl.io.lsu_pkt_m.bits.dma @[lsu.scala 164:46]
-    dccm_ctl.io.lsu_pkt_m.bits.unsign <= lsu_lsc_ctl.io.lsu_pkt_m.bits.unsign @[lsu.scala 164:46]
-    dccm_ctl.io.lsu_pkt_m.bits.store <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store @[lsu.scala 164:46]
-    dccm_ctl.io.lsu_pkt_m.bits.load <= lsu_lsc_ctl.io.lsu_pkt_m.bits.load @[lsu.scala 164:46]
-    dccm_ctl.io.lsu_pkt_m.bits.dword <= lsu_lsc_ctl.io.lsu_pkt_m.bits.dword @[lsu.scala 164:46]
-    dccm_ctl.io.lsu_pkt_m.bits.word <= lsu_lsc_ctl.io.lsu_pkt_m.bits.word @[lsu.scala 164:46]
-    dccm_ctl.io.lsu_pkt_m.bits.half <= lsu_lsc_ctl.io.lsu_pkt_m.bits.half @[lsu.scala 164:46]
-    dccm_ctl.io.lsu_pkt_m.bits.by <= lsu_lsc_ctl.io.lsu_pkt_m.bits.by @[lsu.scala 164:46]
-    dccm_ctl.io.lsu_pkt_m.bits.fast_int <= lsu_lsc_ctl.io.lsu_pkt_m.bits.fast_int @[lsu.scala 164:46]
-    dccm_ctl.io.lsu_pkt_m.valid <= lsu_lsc_ctl.io.lsu_pkt_m.valid @[lsu.scala 164:46]
-    dccm_ctl.io.lsu_pkt_r.bits.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store_data_bypass_m @[lsu.scala 165:46]
-    dccm_ctl.io.lsu_pkt_r.bits.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_r.bits.load_ldst_bypass_d @[lsu.scala 165:46]
-    dccm_ctl.io.lsu_pkt_r.bits.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store_data_bypass_d @[lsu.scala 165:46]
-    dccm_ctl.io.lsu_pkt_r.bits.dma <= lsu_lsc_ctl.io.lsu_pkt_r.bits.dma @[lsu.scala 165:46]
-    dccm_ctl.io.lsu_pkt_r.bits.unsign <= lsu_lsc_ctl.io.lsu_pkt_r.bits.unsign @[lsu.scala 165:46]
-    dccm_ctl.io.lsu_pkt_r.bits.store <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store @[lsu.scala 165:46]
-    dccm_ctl.io.lsu_pkt_r.bits.load <= lsu_lsc_ctl.io.lsu_pkt_r.bits.load @[lsu.scala 165:46]
-    dccm_ctl.io.lsu_pkt_r.bits.dword <= lsu_lsc_ctl.io.lsu_pkt_r.bits.dword @[lsu.scala 165:46]
-    dccm_ctl.io.lsu_pkt_r.bits.word <= lsu_lsc_ctl.io.lsu_pkt_r.bits.word @[lsu.scala 165:46]
-    dccm_ctl.io.lsu_pkt_r.bits.half <= lsu_lsc_ctl.io.lsu_pkt_r.bits.half @[lsu.scala 165:46]
-    dccm_ctl.io.lsu_pkt_r.bits.by <= lsu_lsc_ctl.io.lsu_pkt_r.bits.by @[lsu.scala 165:46]
-    dccm_ctl.io.lsu_pkt_r.bits.fast_int <= lsu_lsc_ctl.io.lsu_pkt_r.bits.fast_int @[lsu.scala 165:46]
-    dccm_ctl.io.lsu_pkt_r.valid <= lsu_lsc_ctl.io.lsu_pkt_r.valid @[lsu.scala 165:46]
-    dccm_ctl.io.addr_in_dccm_d <= lsu_lsc_ctl.io.addr_in_dccm_d @[lsu.scala 166:46]
-    dccm_ctl.io.addr_in_dccm_m <= lsu_lsc_ctl.io.addr_in_dccm_m @[lsu.scala 167:46]
-    dccm_ctl.io.addr_in_dccm_r <= lsu_lsc_ctl.io.addr_in_dccm_r @[lsu.scala 168:46]
-    dccm_ctl.io.addr_in_pic_d <= lsu_lsc_ctl.io.addr_in_pic_d @[lsu.scala 169:46]
-    dccm_ctl.io.addr_in_pic_m <= lsu_lsc_ctl.io.addr_in_pic_m @[lsu.scala 170:46]
-    dccm_ctl.io.addr_in_pic_r <= lsu_lsc_ctl.io.addr_in_pic_r @[lsu.scala 171:46]
-    dccm_ctl.io.lsu_raw_fwd_lo_r <= lsu_raw_fwd_lo_r @[lsu.scala 172:46]
-    dccm_ctl.io.lsu_raw_fwd_hi_r <= lsu_raw_fwd_hi_r @[lsu.scala 173:46]
-    dccm_ctl.io.lsu_commit_r <= lsu_lsc_ctl.io.lsu_commit_r @[lsu.scala 174:46]
-    dccm_ctl.io.lsu_addr_d <= lsu_lsc_ctl.io.lsu_addr_d @[lsu.scala 175:46]
-    dccm_ctl.io.lsu_addr_m <= lsu_lsc_ctl.io.lsu_addr_m @[lsu.scala 176:46]
-    dccm_ctl.io.lsu_addr_r <= lsu_lsc_ctl.io.lsu_addr_r @[lsu.scala 177:46]
-    dccm_ctl.io.end_addr_d <= lsu_lsc_ctl.io.end_addr_d @[lsu.scala 178:46]
-    dccm_ctl.io.end_addr_m <= lsu_lsc_ctl.io.end_addr_m @[lsu.scala 179:46]
-    dccm_ctl.io.end_addr_r <= lsu_lsc_ctl.io.end_addr_r @[lsu.scala 180:46]
-    dccm_ctl.io.stbuf_reqvld_any <= stbuf.io.stbuf_reqvld_any @[lsu.scala 181:46]
-    dccm_ctl.io.stbuf_addr_any <= stbuf.io.stbuf_addr_any @[lsu.scala 182:46]
-    dccm_ctl.io.stbuf_data_any <= stbuf.io.stbuf_data_any @[lsu.scala 183:46]
-    dccm_ctl.io.stbuf_ecc_any <= ecc.io.stbuf_ecc_any @[lsu.scala 184:46]
-    dccm_ctl.io.stbuf_fwddata_hi_m <= stbuf.io.stbuf_fwddata_hi_m @[lsu.scala 185:46]
-    dccm_ctl.io.stbuf_fwddata_lo_m <= stbuf.io.stbuf_fwddata_lo_m @[lsu.scala 186:46]
-    dccm_ctl.io.stbuf_fwdbyteen_lo_m <= stbuf.io.stbuf_fwdbyteen_lo_m @[lsu.scala 187:46]
-    dccm_ctl.io.stbuf_fwdbyteen_hi_m <= stbuf.io.stbuf_fwdbyteen_hi_m @[lsu.scala 188:46]
-    dccm_ctl.io.lsu_double_ecc_error_r <= ecc.io.lsu_double_ecc_error_r @[lsu.scala 189:46]
-    dccm_ctl.io.single_ecc_error_hi_r <= ecc.io.single_ecc_error_hi_r @[lsu.scala 190:46]
-    dccm_ctl.io.single_ecc_error_lo_r <= ecc.io.single_ecc_error_lo_r @[lsu.scala 191:46]
-    dccm_ctl.io.sec_data_hi_r <= ecc.io.sec_data_hi_r @[lsu.scala 192:46]
-    dccm_ctl.io.sec_data_lo_r <= ecc.io.sec_data_lo_r @[lsu.scala 193:46]
-    dccm_ctl.io.sec_data_hi_r_ff <= ecc.io.sec_data_hi_r_ff @[lsu.scala 194:46]
-    dccm_ctl.io.sec_data_lo_r_ff <= ecc.io.sec_data_lo_r_ff @[lsu.scala 195:46]
-    dccm_ctl.io.sec_data_ecc_hi_r_ff <= ecc.io.sec_data_ecc_hi_r_ff @[lsu.scala 196:46]
-    dccm_ctl.io.sec_data_ecc_lo_r_ff <= ecc.io.sec_data_ecc_lo_r_ff @[lsu.scala 197:46]
-    dccm_ctl.io.lsu_double_ecc_error_m <= ecc.io.lsu_double_ecc_error_m @[lsu.scala 198:46]
-    dccm_ctl.io.sec_data_hi_m <= ecc.io.sec_data_hi_m @[lsu.scala 199:46]
-    dccm_ctl.io.sec_data_lo_m <= ecc.io.sec_data_lo_m @[lsu.scala 200:46]
-    dccm_ctl.io.store_data_m <= lsu_lsc_ctl.io.store_data_m @[lsu.scala 201:46]
-    dccm_ctl.io.dma_dccm_wen <= dma_dccm_wen @[lsu.scala 202:46]
-    dccm_ctl.io.dma_pic_wen <= dma_pic_wen @[lsu.scala 203:46]
-    dccm_ctl.io.dma_mem_tag_m <= dma_mem_tag_m @[lsu.scala 204:46]
-    dccm_ctl.io.dma_dccm_wdata_lo <= dma_dccm_wdata_lo @[lsu.scala 205:46]
-    dccm_ctl.io.dma_dccm_wdata_hi <= dma_dccm_wdata_hi @[lsu.scala 206:46]
-    dccm_ctl.io.dma_dccm_wdata_ecc_hi <= ecc.io.dma_dccm_wdata_ecc_hi @[lsu.scala 207:46]
-    dccm_ctl.io.dma_dccm_wdata_ecc_lo <= ecc.io.dma_dccm_wdata_ecc_lo @[lsu.scala 208:46]
-    dccm_ctl.io.scan_mode <= io.scan_mode @[lsu.scala 209:46]
-    io.lsu_dma.dma_dccm_ctl.dccm_dma_rdata <= dccm_ctl.io.dma_dccm_ctl.dccm_dma_rdata @[lsu.scala 211:27]
-    io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag <= dccm_ctl.io.dma_dccm_ctl.dccm_dma_rtag @[lsu.scala 211:27]
-    io.lsu_dma.dma_dccm_ctl.dccm_dma_ecc_error <= dccm_ctl.io.dma_dccm_ctl.dccm_dma_ecc_error @[lsu.scala 211:27]
-    io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid <= dccm_ctl.io.dma_dccm_ctl.dccm_dma_rvalid @[lsu.scala 211:27]
-    dccm_ctl.io.dma_dccm_ctl.dma_mem_wdata <= io.lsu_dma.dma_dccm_ctl.dma_mem_wdata @[lsu.scala 211:27]
-    dccm_ctl.io.dma_dccm_ctl.dma_mem_addr <= io.lsu_dma.dma_dccm_ctl.dma_mem_addr @[lsu.scala 211:27]
-    dccm_ctl.io.dccm.rd_data_hi <= io.dccm.rd_data_hi @[lsu.scala 212:11]
-    dccm_ctl.io.dccm.rd_data_lo <= io.dccm.rd_data_lo @[lsu.scala 212:11]
-    io.dccm.wr_data_hi <= dccm_ctl.io.dccm.wr_data_hi @[lsu.scala 212:11]
-    io.dccm.wr_data_lo <= dccm_ctl.io.dccm.wr_data_lo @[lsu.scala 212:11]
-    io.dccm.rd_addr_hi <= dccm_ctl.io.dccm.rd_addr_hi @[lsu.scala 212:11]
-    io.dccm.rd_addr_lo <= dccm_ctl.io.dccm.rd_addr_lo @[lsu.scala 212:11]
-    io.dccm.wr_addr_hi <= dccm_ctl.io.dccm.wr_addr_hi @[lsu.scala 212:11]
-    io.dccm.wr_addr_lo <= dccm_ctl.io.dccm.wr_addr_lo @[lsu.scala 212:11]
-    io.dccm.rden <= dccm_ctl.io.dccm.rden @[lsu.scala 212:11]
-    io.dccm.wren <= dccm_ctl.io.dccm.wren @[lsu.scala 212:11]
-    dccm_ctl.io.lsu_pic.picm_rd_data <= io.lsu_pic.picm_rd_data @[lsu.scala 213:14]
-    io.lsu_pic.picm_wr_data <= dccm_ctl.io.lsu_pic.picm_wr_data @[lsu.scala 213:14]
-    io.lsu_pic.picm_wraddr <= dccm_ctl.io.lsu_pic.picm_wraddr @[lsu.scala 213:14]
-    io.lsu_pic.picm_rdaddr <= dccm_ctl.io.lsu_pic.picm_rdaddr @[lsu.scala 213:14]
-    io.lsu_pic.picm_mken <= dccm_ctl.io.lsu_pic.picm_mken @[lsu.scala 213:14]
-    io.lsu_pic.picm_rden <= dccm_ctl.io.lsu_pic.picm_rden @[lsu.scala 213:14]
-    io.lsu_pic.picm_wren <= dccm_ctl.io.lsu_pic.picm_wren @[lsu.scala 213:14]
-    stbuf.io.ldst_dual_d <= ldst_dual_d @[lsu.scala 216:50]
-    stbuf.io.ldst_dual_m <= ldst_dual_m @[lsu.scala 217:50]
-    stbuf.io.ldst_dual_r <= ldst_dual_r @[lsu.scala 218:50]
-    stbuf.io.lsu_stbuf_c1_clk <= clkdomain.io.lsu_stbuf_c1_clk @[lsu.scala 219:54]
-    stbuf.io.lsu_free_c2_clk <= clkdomain.io.lsu_free_c2_clk @[lsu.scala 220:54]
-    stbuf.io.lsu_pkt_m.bits.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store_data_bypass_m @[lsu.scala 221:48]
-    stbuf.io.lsu_pkt_m.bits.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.bits.load_ldst_bypass_d @[lsu.scala 221:48]
-    stbuf.io.lsu_pkt_m.bits.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store_data_bypass_d @[lsu.scala 221:48]
-    stbuf.io.lsu_pkt_m.bits.dma <= lsu_lsc_ctl.io.lsu_pkt_m.bits.dma @[lsu.scala 221:48]
-    stbuf.io.lsu_pkt_m.bits.unsign <= lsu_lsc_ctl.io.lsu_pkt_m.bits.unsign @[lsu.scala 221:48]
-    stbuf.io.lsu_pkt_m.bits.store <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store @[lsu.scala 221:48]
-    stbuf.io.lsu_pkt_m.bits.load <= lsu_lsc_ctl.io.lsu_pkt_m.bits.load @[lsu.scala 221:48]
-    stbuf.io.lsu_pkt_m.bits.dword <= lsu_lsc_ctl.io.lsu_pkt_m.bits.dword @[lsu.scala 221:48]
-    stbuf.io.lsu_pkt_m.bits.word <= lsu_lsc_ctl.io.lsu_pkt_m.bits.word @[lsu.scala 221:48]
-    stbuf.io.lsu_pkt_m.bits.half <= lsu_lsc_ctl.io.lsu_pkt_m.bits.half @[lsu.scala 221:48]
-    stbuf.io.lsu_pkt_m.bits.by <= lsu_lsc_ctl.io.lsu_pkt_m.bits.by @[lsu.scala 221:48]
-    stbuf.io.lsu_pkt_m.bits.fast_int <= lsu_lsc_ctl.io.lsu_pkt_m.bits.fast_int @[lsu.scala 221:48]
-    stbuf.io.lsu_pkt_m.valid <= lsu_lsc_ctl.io.lsu_pkt_m.valid @[lsu.scala 221:48]
-    stbuf.io.lsu_pkt_r.bits.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store_data_bypass_m @[lsu.scala 222:48]
-    stbuf.io.lsu_pkt_r.bits.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_r.bits.load_ldst_bypass_d @[lsu.scala 222:48]
-    stbuf.io.lsu_pkt_r.bits.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store_data_bypass_d @[lsu.scala 222:48]
-    stbuf.io.lsu_pkt_r.bits.dma <= lsu_lsc_ctl.io.lsu_pkt_r.bits.dma @[lsu.scala 222:48]
-    stbuf.io.lsu_pkt_r.bits.unsign <= lsu_lsc_ctl.io.lsu_pkt_r.bits.unsign @[lsu.scala 222:48]
-    stbuf.io.lsu_pkt_r.bits.store <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store @[lsu.scala 222:48]
-    stbuf.io.lsu_pkt_r.bits.load <= lsu_lsc_ctl.io.lsu_pkt_r.bits.load @[lsu.scala 222:48]
-    stbuf.io.lsu_pkt_r.bits.dword <= lsu_lsc_ctl.io.lsu_pkt_r.bits.dword @[lsu.scala 222:48]
-    stbuf.io.lsu_pkt_r.bits.word <= lsu_lsc_ctl.io.lsu_pkt_r.bits.word @[lsu.scala 222:48]
-    stbuf.io.lsu_pkt_r.bits.half <= lsu_lsc_ctl.io.lsu_pkt_r.bits.half @[lsu.scala 222:48]
-    stbuf.io.lsu_pkt_r.bits.by <= lsu_lsc_ctl.io.lsu_pkt_r.bits.by @[lsu.scala 222:48]
-    stbuf.io.lsu_pkt_r.bits.fast_int <= lsu_lsc_ctl.io.lsu_pkt_r.bits.fast_int @[lsu.scala 222:48]
-    stbuf.io.lsu_pkt_r.valid <= lsu_lsc_ctl.io.lsu_pkt_r.valid @[lsu.scala 222:48]
-    stbuf.io.store_stbuf_reqvld_r <= store_stbuf_reqvld_r @[lsu.scala 223:48]
-    stbuf.io.lsu_commit_r <= lsu_lsc_ctl.io.lsu_commit_r @[lsu.scala 224:49]
-    stbuf.io.dec_lsu_valid_raw_d <= io.dec_lsu_valid_raw_d @[lsu.scala 225:49]
-    stbuf.io.store_data_hi_r <= dccm_ctl.io.store_data_hi_r @[lsu.scala 226:62]
-    stbuf.io.store_data_lo_r <= dccm_ctl.io.store_data_lo_r @[lsu.scala 227:62]
-    stbuf.io.store_datafn_hi_r <= dccm_ctl.io.store_datafn_hi_r @[lsu.scala 228:49]
-    stbuf.io.store_datafn_lo_r <= dccm_ctl.io.store_datafn_lo_r @[lsu.scala 229:56]
-    stbuf.io.lsu_stbuf_commit_any <= dccm_ctl.io.lsu_stbuf_commit_any @[lsu.scala 230:52]
-    stbuf.io.lsu_addr_d <= lsu_lsc_ctl.io.lsu_addr_d @[lsu.scala 231:64]
-    stbuf.io.lsu_addr_m <= lsu_lsc_ctl.io.lsu_addr_m @[lsu.scala 232:64]
-    stbuf.io.lsu_addr_r <= lsu_lsc_ctl.io.lsu_addr_r @[lsu.scala 233:64]
-    stbuf.io.end_addr_d <= lsu_lsc_ctl.io.end_addr_d @[lsu.scala 234:64]
-    stbuf.io.end_addr_m <= lsu_lsc_ctl.io.end_addr_m @[lsu.scala 235:64]
-    stbuf.io.end_addr_r <= lsu_lsc_ctl.io.end_addr_r @[lsu.scala 236:64]
-    stbuf.io.addr_in_dccm_m <= lsu_lsc_ctl.io.addr_in_dccm_m @[lsu.scala 237:49]
-    stbuf.io.addr_in_dccm_r <= lsu_lsc_ctl.io.addr_in_dccm_r @[lsu.scala 238:56]
-    stbuf.io.lsu_cmpen_m <= lsu_cmpen_m @[lsu.scala 239:54]
-    stbuf.io.scan_mode <= io.scan_mode @[lsu.scala 240:49]
-    ecc.io.clk_override <= io.clk_override @[lsu.scala 244:50]
-    ecc.io.lsu_c2_r_clk <= clkdomain.io.lsu_c2_r_clk @[lsu.scala 245:52]
-    ecc.io.lsu_pkt_m.bits.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store_data_bypass_m @[lsu.scala 246:52]
-    ecc.io.lsu_pkt_m.bits.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.bits.load_ldst_bypass_d @[lsu.scala 246:52]
-    ecc.io.lsu_pkt_m.bits.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store_data_bypass_d @[lsu.scala 246:52]
-    ecc.io.lsu_pkt_m.bits.dma <= lsu_lsc_ctl.io.lsu_pkt_m.bits.dma @[lsu.scala 246:52]
-    ecc.io.lsu_pkt_m.bits.unsign <= lsu_lsc_ctl.io.lsu_pkt_m.bits.unsign @[lsu.scala 246:52]
-    ecc.io.lsu_pkt_m.bits.store <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store @[lsu.scala 246:52]
-    ecc.io.lsu_pkt_m.bits.load <= lsu_lsc_ctl.io.lsu_pkt_m.bits.load @[lsu.scala 246:52]
-    ecc.io.lsu_pkt_m.bits.dword <= lsu_lsc_ctl.io.lsu_pkt_m.bits.dword @[lsu.scala 246:52]
-    ecc.io.lsu_pkt_m.bits.word <= lsu_lsc_ctl.io.lsu_pkt_m.bits.word @[lsu.scala 246:52]
-    ecc.io.lsu_pkt_m.bits.half <= lsu_lsc_ctl.io.lsu_pkt_m.bits.half @[lsu.scala 246:52]
-    ecc.io.lsu_pkt_m.bits.by <= lsu_lsc_ctl.io.lsu_pkt_m.bits.by @[lsu.scala 246:52]
-    ecc.io.lsu_pkt_m.bits.fast_int <= lsu_lsc_ctl.io.lsu_pkt_m.bits.fast_int @[lsu.scala 246:52]
-    ecc.io.lsu_pkt_m.valid <= lsu_lsc_ctl.io.lsu_pkt_m.valid @[lsu.scala 246:52]
-    ecc.io.lsu_pkt_r.bits.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store_data_bypass_m @[lsu.scala 247:52]
-    ecc.io.lsu_pkt_r.bits.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_r.bits.load_ldst_bypass_d @[lsu.scala 247:52]
-    ecc.io.lsu_pkt_r.bits.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store_data_bypass_d @[lsu.scala 247:52]
-    ecc.io.lsu_pkt_r.bits.dma <= lsu_lsc_ctl.io.lsu_pkt_r.bits.dma @[lsu.scala 247:52]
-    ecc.io.lsu_pkt_r.bits.unsign <= lsu_lsc_ctl.io.lsu_pkt_r.bits.unsign @[lsu.scala 247:52]
-    ecc.io.lsu_pkt_r.bits.store <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store @[lsu.scala 247:52]
-    ecc.io.lsu_pkt_r.bits.load <= lsu_lsc_ctl.io.lsu_pkt_r.bits.load @[lsu.scala 247:52]
-    ecc.io.lsu_pkt_r.bits.dword <= lsu_lsc_ctl.io.lsu_pkt_r.bits.dword @[lsu.scala 247:52]
-    ecc.io.lsu_pkt_r.bits.word <= lsu_lsc_ctl.io.lsu_pkt_r.bits.word @[lsu.scala 247:52]
-    ecc.io.lsu_pkt_r.bits.half <= lsu_lsc_ctl.io.lsu_pkt_r.bits.half @[lsu.scala 247:52]
-    ecc.io.lsu_pkt_r.bits.by <= lsu_lsc_ctl.io.lsu_pkt_r.bits.by @[lsu.scala 247:52]
-    ecc.io.lsu_pkt_r.bits.fast_int <= lsu_lsc_ctl.io.lsu_pkt_r.bits.fast_int @[lsu.scala 247:52]
-    ecc.io.lsu_pkt_r.valid <= lsu_lsc_ctl.io.lsu_pkt_r.valid @[lsu.scala 247:52]
-    ecc.io.stbuf_data_any <= stbuf.io.stbuf_data_any @[lsu.scala 248:54]
-    ecc.io.dec_tlu_core_ecc_disable <= io.dec_tlu_core_ecc_disable @[lsu.scala 249:50]
-    ecc.io.lsu_dccm_rden_r <= dccm_ctl.io.lsu_dccm_rden_r @[lsu.scala 250:56]
-    ecc.io.addr_in_dccm_r <= lsu_lsc_ctl.io.addr_in_dccm_r @[lsu.scala 251:50]
-    ecc.io.lsu_addr_r <= lsu_lsc_ctl.io.lsu_addr_r @[lsu.scala 252:58]
-    ecc.io.end_addr_r <= lsu_lsc_ctl.io.end_addr_r @[lsu.scala 253:58]
-    ecc.io.lsu_addr_m <= lsu_lsc_ctl.io.lsu_addr_m @[lsu.scala 254:58]
-    ecc.io.end_addr_m <= lsu_lsc_ctl.io.end_addr_m @[lsu.scala 255:58]
-    ecc.io.dccm_rdata_hi_r <= dccm_ctl.io.dccm_rdata_hi_r @[lsu.scala 256:54]
-    ecc.io.dccm_rdata_lo_r <= dccm_ctl.io.dccm_rdata_lo_r @[lsu.scala 257:54]
-    ecc.io.dccm_rdata_hi_m <= dccm_ctl.io.dccm_rdata_hi_m @[lsu.scala 258:54]
-    ecc.io.dccm_rdata_lo_m <= dccm_ctl.io.dccm_rdata_lo_m @[lsu.scala 259:54]
-    ecc.io.dccm_data_ecc_hi_r <= dccm_ctl.io.dccm_data_ecc_hi_r @[lsu.scala 260:50]
-    ecc.io.dccm_data_ecc_lo_r <= dccm_ctl.io.dccm_data_ecc_lo_r @[lsu.scala 261:50]
-    ecc.io.dccm_data_ecc_hi_m <= dccm_ctl.io.dccm_data_ecc_hi_m @[lsu.scala 262:50]
-    ecc.io.dccm_data_ecc_lo_m <= dccm_ctl.io.dccm_data_ecc_lo_m @[lsu.scala 263:50]
-    ecc.io.ld_single_ecc_error_r <= dccm_ctl.io.ld_single_ecc_error_r @[lsu.scala 264:50]
-    ecc.io.ld_single_ecc_error_r_ff <= dccm_ctl.io.ld_single_ecc_error_r_ff @[lsu.scala 265:50]
-    ecc.io.lsu_dccm_rden_m <= dccm_ctl.io.lsu_dccm_rden_m @[lsu.scala 266:50]
-    ecc.io.addr_in_dccm_m <= lsu_lsc_ctl.io.addr_in_dccm_m @[lsu.scala 267:50]
-    ecc.io.dma_dccm_wen <= dma_dccm_wen @[lsu.scala 268:50]
-    ecc.io.dma_dccm_wdata_lo <= dma_dccm_wdata_lo @[lsu.scala 269:50]
-    ecc.io.dma_dccm_wdata_hi <= dma_dccm_wdata_hi @[lsu.scala 270:50]
-    ecc.io.scan_mode <= io.scan_mode @[lsu.scala 271:50]
-    trigger.io.trigger_pkt_any[0].tdata2 <= io.trigger_pkt_any[0].tdata2 @[lsu.scala 275:50]
-    trigger.io.trigger_pkt_any[0].m <= io.trigger_pkt_any[0].m @[lsu.scala 275:50]
-    trigger.io.trigger_pkt_any[0].execute <= io.trigger_pkt_any[0].execute @[lsu.scala 275:50]
-    trigger.io.trigger_pkt_any[0].load <= io.trigger_pkt_any[0].load @[lsu.scala 275:50]
-    trigger.io.trigger_pkt_any[0].store <= io.trigger_pkt_any[0].store @[lsu.scala 275:50]
-    trigger.io.trigger_pkt_any[0].match_pkt <= io.trigger_pkt_any[0].match_pkt @[lsu.scala 275:50]
-    trigger.io.trigger_pkt_any[0].select <= io.trigger_pkt_any[0].select @[lsu.scala 275:50]
-    trigger.io.trigger_pkt_any[1].tdata2 <= io.trigger_pkt_any[1].tdata2 @[lsu.scala 275:50]
-    trigger.io.trigger_pkt_any[1].m <= io.trigger_pkt_any[1].m @[lsu.scala 275:50]
-    trigger.io.trigger_pkt_any[1].execute <= io.trigger_pkt_any[1].execute @[lsu.scala 275:50]
-    trigger.io.trigger_pkt_any[1].load <= io.trigger_pkt_any[1].load @[lsu.scala 275:50]
-    trigger.io.trigger_pkt_any[1].store <= io.trigger_pkt_any[1].store @[lsu.scala 275:50]
-    trigger.io.trigger_pkt_any[1].match_pkt <= io.trigger_pkt_any[1].match_pkt @[lsu.scala 275:50]
-    trigger.io.trigger_pkt_any[1].select <= io.trigger_pkt_any[1].select @[lsu.scala 275:50]
-    trigger.io.trigger_pkt_any[2].tdata2 <= io.trigger_pkt_any[2].tdata2 @[lsu.scala 275:50]
-    trigger.io.trigger_pkt_any[2].m <= io.trigger_pkt_any[2].m @[lsu.scala 275:50]
-    trigger.io.trigger_pkt_any[2].execute <= io.trigger_pkt_any[2].execute @[lsu.scala 275:50]
-    trigger.io.trigger_pkt_any[2].load <= io.trigger_pkt_any[2].load @[lsu.scala 275:50]
-    trigger.io.trigger_pkt_any[2].store <= io.trigger_pkt_any[2].store @[lsu.scala 275:50]
-    trigger.io.trigger_pkt_any[2].match_pkt <= io.trigger_pkt_any[2].match_pkt @[lsu.scala 275:50]
-    trigger.io.trigger_pkt_any[2].select <= io.trigger_pkt_any[2].select @[lsu.scala 275:50]
-    trigger.io.trigger_pkt_any[3].tdata2 <= io.trigger_pkt_any[3].tdata2 @[lsu.scala 275:50]
-    trigger.io.trigger_pkt_any[3].m <= io.trigger_pkt_any[3].m @[lsu.scala 275:50]
-    trigger.io.trigger_pkt_any[3].execute <= io.trigger_pkt_any[3].execute @[lsu.scala 275:50]
-    trigger.io.trigger_pkt_any[3].load <= io.trigger_pkt_any[3].load @[lsu.scala 275:50]
-    trigger.io.trigger_pkt_any[3].store <= io.trigger_pkt_any[3].store @[lsu.scala 275:50]
-    trigger.io.trigger_pkt_any[3].match_pkt <= io.trigger_pkt_any[3].match_pkt @[lsu.scala 275:50]
-    trigger.io.trigger_pkt_any[3].select <= io.trigger_pkt_any[3].select @[lsu.scala 275:50]
-    trigger.io.lsu_pkt_m.bits.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store_data_bypass_m @[lsu.scala 276:50]
-    trigger.io.lsu_pkt_m.bits.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.bits.load_ldst_bypass_d @[lsu.scala 276:50]
-    trigger.io.lsu_pkt_m.bits.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store_data_bypass_d @[lsu.scala 276:50]
-    trigger.io.lsu_pkt_m.bits.dma <= lsu_lsc_ctl.io.lsu_pkt_m.bits.dma @[lsu.scala 276:50]
-    trigger.io.lsu_pkt_m.bits.unsign <= lsu_lsc_ctl.io.lsu_pkt_m.bits.unsign @[lsu.scala 276:50]
-    trigger.io.lsu_pkt_m.bits.store <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store @[lsu.scala 276:50]
-    trigger.io.lsu_pkt_m.bits.load <= lsu_lsc_ctl.io.lsu_pkt_m.bits.load @[lsu.scala 276:50]
-    trigger.io.lsu_pkt_m.bits.dword <= lsu_lsc_ctl.io.lsu_pkt_m.bits.dword @[lsu.scala 276:50]
-    trigger.io.lsu_pkt_m.bits.word <= lsu_lsc_ctl.io.lsu_pkt_m.bits.word @[lsu.scala 276:50]
-    trigger.io.lsu_pkt_m.bits.half <= lsu_lsc_ctl.io.lsu_pkt_m.bits.half @[lsu.scala 276:50]
-    trigger.io.lsu_pkt_m.bits.by <= lsu_lsc_ctl.io.lsu_pkt_m.bits.by @[lsu.scala 276:50]
-    trigger.io.lsu_pkt_m.bits.fast_int <= lsu_lsc_ctl.io.lsu_pkt_m.bits.fast_int @[lsu.scala 276:50]
-    trigger.io.lsu_pkt_m.valid <= lsu_lsc_ctl.io.lsu_pkt_m.valid @[lsu.scala 276:50]
-    trigger.io.lsu_addr_m <= lsu_lsc_ctl.io.lsu_addr_m @[lsu.scala 277:50]
-    trigger.io.store_data_m <= lsu_lsc_ctl.io.store_data_m @[lsu.scala 278:50]
-    io.lsu_trigger_match_m <= trigger.io.lsu_trigger_match_m @[lsu.scala 280:50]
-    clkdomain.io.active_clk <= io.active_clk @[lsu.scala 284:50]
-    clkdomain.io.clk_override <= io.clk_override @[lsu.scala 285:50]
-    clkdomain.io.dec_tlu_force_halt <= io.dec_tlu_force_halt @[lsu.scala 286:50]
-    clkdomain.io.dma_dccm_req <= io.lsu_dma.dma_lsc_ctl.dma_dccm_req @[lsu.scala 287:50]
-    clkdomain.io.ldst_stbuf_reqvld_r <= stbuf.io.ldst_stbuf_reqvld_r @[lsu.scala 288:50]
-    clkdomain.io.stbuf_reqvld_any <= stbuf.io.stbuf_reqvld_any @[lsu.scala 289:50]
-    clkdomain.io.stbuf_reqvld_flushed_any <= stbuf.io.stbuf_reqvld_flushed_any @[lsu.scala 290:50]
-    clkdomain.io.lsu_busreq_r <= bus_intf.io.lsu_busreq_r @[lsu.scala 291:50]
-    clkdomain.io.lsu_bus_buffer_pend_any <= bus_intf.io.lsu_bus_buffer_pend_any @[lsu.scala 292:50]
-    clkdomain.io.lsu_bus_buffer_empty_any <= bus_intf.io.lsu_bus_buffer_empty_any @[lsu.scala 293:50]
-    clkdomain.io.lsu_stbuf_empty_any <= stbuf.io.lsu_stbuf_empty_any @[lsu.scala 294:50]
-    clkdomain.io.lsu_bus_clk_en <= io.lsu_bus_clk_en @[lsu.scala 295:50]
-    clkdomain.io.lsu_p.bits.store_data_bypass_m <= io.lsu_p.bits.store_data_bypass_m @[lsu.scala 296:50]
-    clkdomain.io.lsu_p.bits.load_ldst_bypass_d <= io.lsu_p.bits.load_ldst_bypass_d @[lsu.scala 296:50]
-    clkdomain.io.lsu_p.bits.store_data_bypass_d <= io.lsu_p.bits.store_data_bypass_d @[lsu.scala 296:50]
-    clkdomain.io.lsu_p.bits.dma <= io.lsu_p.bits.dma @[lsu.scala 296:50]
-    clkdomain.io.lsu_p.bits.unsign <= io.lsu_p.bits.unsign @[lsu.scala 296:50]
-    clkdomain.io.lsu_p.bits.store <= io.lsu_p.bits.store @[lsu.scala 296:50]
-    clkdomain.io.lsu_p.bits.load <= io.lsu_p.bits.load @[lsu.scala 296:50]
-    clkdomain.io.lsu_p.bits.dword <= io.lsu_p.bits.dword @[lsu.scala 296:50]
-    clkdomain.io.lsu_p.bits.word <= io.lsu_p.bits.word @[lsu.scala 296:50]
-    clkdomain.io.lsu_p.bits.half <= io.lsu_p.bits.half @[lsu.scala 296:50]
-    clkdomain.io.lsu_p.bits.by <= io.lsu_p.bits.by @[lsu.scala 296:50]
-    clkdomain.io.lsu_p.bits.fast_int <= io.lsu_p.bits.fast_int @[lsu.scala 296:50]
-    clkdomain.io.lsu_p.valid <= io.lsu_p.valid @[lsu.scala 296:50]
-    clkdomain.io.lsu_pkt_d.bits.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_d.bits.store_data_bypass_m @[lsu.scala 297:50]
-    clkdomain.io.lsu_pkt_d.bits.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_d.bits.load_ldst_bypass_d @[lsu.scala 297:50]
-    clkdomain.io.lsu_pkt_d.bits.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_d.bits.store_data_bypass_d @[lsu.scala 297:50]
-    clkdomain.io.lsu_pkt_d.bits.dma <= lsu_lsc_ctl.io.lsu_pkt_d.bits.dma @[lsu.scala 297:50]
-    clkdomain.io.lsu_pkt_d.bits.unsign <= lsu_lsc_ctl.io.lsu_pkt_d.bits.unsign @[lsu.scala 297:50]
-    clkdomain.io.lsu_pkt_d.bits.store <= lsu_lsc_ctl.io.lsu_pkt_d.bits.store @[lsu.scala 297:50]
-    clkdomain.io.lsu_pkt_d.bits.load <= lsu_lsc_ctl.io.lsu_pkt_d.bits.load @[lsu.scala 297:50]
-    clkdomain.io.lsu_pkt_d.bits.dword <= lsu_lsc_ctl.io.lsu_pkt_d.bits.dword @[lsu.scala 297:50]
-    clkdomain.io.lsu_pkt_d.bits.word <= lsu_lsc_ctl.io.lsu_pkt_d.bits.word @[lsu.scala 297:50]
-    clkdomain.io.lsu_pkt_d.bits.half <= lsu_lsc_ctl.io.lsu_pkt_d.bits.half @[lsu.scala 297:50]
-    clkdomain.io.lsu_pkt_d.bits.by <= lsu_lsc_ctl.io.lsu_pkt_d.bits.by @[lsu.scala 297:50]
-    clkdomain.io.lsu_pkt_d.bits.fast_int <= lsu_lsc_ctl.io.lsu_pkt_d.bits.fast_int @[lsu.scala 297:50]
-    clkdomain.io.lsu_pkt_d.valid <= lsu_lsc_ctl.io.lsu_pkt_d.valid @[lsu.scala 297:50]
-    clkdomain.io.lsu_pkt_m.bits.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store_data_bypass_m @[lsu.scala 298:50]
-    clkdomain.io.lsu_pkt_m.bits.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.bits.load_ldst_bypass_d @[lsu.scala 298:50]
-    clkdomain.io.lsu_pkt_m.bits.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store_data_bypass_d @[lsu.scala 298:50]
-    clkdomain.io.lsu_pkt_m.bits.dma <= lsu_lsc_ctl.io.lsu_pkt_m.bits.dma @[lsu.scala 298:50]
-    clkdomain.io.lsu_pkt_m.bits.unsign <= lsu_lsc_ctl.io.lsu_pkt_m.bits.unsign @[lsu.scala 298:50]
-    clkdomain.io.lsu_pkt_m.bits.store <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store @[lsu.scala 298:50]
-    clkdomain.io.lsu_pkt_m.bits.load <= lsu_lsc_ctl.io.lsu_pkt_m.bits.load @[lsu.scala 298:50]
-    clkdomain.io.lsu_pkt_m.bits.dword <= lsu_lsc_ctl.io.lsu_pkt_m.bits.dword @[lsu.scala 298:50]
-    clkdomain.io.lsu_pkt_m.bits.word <= lsu_lsc_ctl.io.lsu_pkt_m.bits.word @[lsu.scala 298:50]
-    clkdomain.io.lsu_pkt_m.bits.half <= lsu_lsc_ctl.io.lsu_pkt_m.bits.half @[lsu.scala 298:50]
-    clkdomain.io.lsu_pkt_m.bits.by <= lsu_lsc_ctl.io.lsu_pkt_m.bits.by @[lsu.scala 298:50]
-    clkdomain.io.lsu_pkt_m.bits.fast_int <= lsu_lsc_ctl.io.lsu_pkt_m.bits.fast_int @[lsu.scala 298:50]
-    clkdomain.io.lsu_pkt_m.valid <= lsu_lsc_ctl.io.lsu_pkt_m.valid @[lsu.scala 298:50]
-    clkdomain.io.lsu_pkt_r.bits.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store_data_bypass_m @[lsu.scala 299:50]
-    clkdomain.io.lsu_pkt_r.bits.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_r.bits.load_ldst_bypass_d @[lsu.scala 299:50]
-    clkdomain.io.lsu_pkt_r.bits.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store_data_bypass_d @[lsu.scala 299:50]
-    clkdomain.io.lsu_pkt_r.bits.dma <= lsu_lsc_ctl.io.lsu_pkt_r.bits.dma @[lsu.scala 299:50]
-    clkdomain.io.lsu_pkt_r.bits.unsign <= lsu_lsc_ctl.io.lsu_pkt_r.bits.unsign @[lsu.scala 299:50]
-    clkdomain.io.lsu_pkt_r.bits.store <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store @[lsu.scala 299:50]
-    clkdomain.io.lsu_pkt_r.bits.load <= lsu_lsc_ctl.io.lsu_pkt_r.bits.load @[lsu.scala 299:50]
-    clkdomain.io.lsu_pkt_r.bits.dword <= lsu_lsc_ctl.io.lsu_pkt_r.bits.dword @[lsu.scala 299:50]
-    clkdomain.io.lsu_pkt_r.bits.word <= lsu_lsc_ctl.io.lsu_pkt_r.bits.word @[lsu.scala 299:50]
-    clkdomain.io.lsu_pkt_r.bits.half <= lsu_lsc_ctl.io.lsu_pkt_r.bits.half @[lsu.scala 299:50]
-    clkdomain.io.lsu_pkt_r.bits.by <= lsu_lsc_ctl.io.lsu_pkt_r.bits.by @[lsu.scala 299:50]
-    clkdomain.io.lsu_pkt_r.bits.fast_int <= lsu_lsc_ctl.io.lsu_pkt_r.bits.fast_int @[lsu.scala 299:50]
-    clkdomain.io.lsu_pkt_r.valid <= lsu_lsc_ctl.io.lsu_pkt_r.valid @[lsu.scala 299:50]
-    clkdomain.io.scan_mode <= io.scan_mode @[lsu.scala 300:50]
-    bus_intf.io.scan_mode <= io.scan_mode @[lsu.scala 304:49]
-    io.lsu_dec.tlu_busbuff.lsu_imprecise_error_addr_any <= bus_intf.io.tlu_busbuff.lsu_imprecise_error_addr_any @[lsu.scala 305:26]
-    io.lsu_dec.tlu_busbuff.lsu_imprecise_error_store_any <= bus_intf.io.tlu_busbuff.lsu_imprecise_error_store_any @[lsu.scala 305:26]
-    io.lsu_dec.tlu_busbuff.lsu_imprecise_error_load_any <= bus_intf.io.tlu_busbuff.lsu_imprecise_error_load_any @[lsu.scala 305:26]
-    bus_intf.io.tlu_busbuff.dec_tlu_sideeffect_posted_disable <= io.lsu_dec.tlu_busbuff.dec_tlu_sideeffect_posted_disable @[lsu.scala 305:26]
-    bus_intf.io.tlu_busbuff.dec_tlu_wb_coalescing_disable <= io.lsu_dec.tlu_busbuff.dec_tlu_wb_coalescing_disable @[lsu.scala 305:26]
-    bus_intf.io.tlu_busbuff.dec_tlu_external_ldfwd_disable <= io.lsu_dec.tlu_busbuff.dec_tlu_external_ldfwd_disable @[lsu.scala 305:26]
-    io.lsu_dec.tlu_busbuff.lsu_pmu_bus_busy <= bus_intf.io.tlu_busbuff.lsu_pmu_bus_busy @[lsu.scala 305:26]
-    io.lsu_dec.tlu_busbuff.lsu_pmu_bus_error <= bus_intf.io.tlu_busbuff.lsu_pmu_bus_error @[lsu.scala 305:26]
-    io.lsu_dec.tlu_busbuff.lsu_pmu_bus_misaligned <= bus_intf.io.tlu_busbuff.lsu_pmu_bus_misaligned @[lsu.scala 305:26]
-    io.lsu_dec.tlu_busbuff.lsu_pmu_bus_trxn <= bus_intf.io.tlu_busbuff.lsu_pmu_bus_trxn @[lsu.scala 305:26]
-    bus_intf.io.clk_override <= io.clk_override @[lsu.scala 306:49]
-    bus_intf.io.lsu_c1_r_clk <= clkdomain.io.lsu_c1_r_clk @[lsu.scala 307:49]
-    bus_intf.io.lsu_c2_r_clk <= clkdomain.io.lsu_c2_r_clk @[lsu.scala 308:49]
-    bus_intf.io.lsu_busm_clken <= lsu_busm_clken @[lsu.scala 309:49]
-    bus_intf.io.lsu_bus_obuf_c1_clken <= lsu_bus_obuf_c1_clken @[lsu.scala 310:49]
-    bus_intf.io.lsu_bus_ibuf_c1_clk <= clkdomain.io.lsu_bus_ibuf_c1_clk @[lsu.scala 311:49]
-    bus_intf.io.lsu_bus_obuf_c1_clk <= clkdomain.io.lsu_bus_obuf_c1_clk @[lsu.scala 312:49]
-    bus_intf.io.lsu_bus_buf_c1_clk <= clkdomain.io.lsu_bus_buf_c1_clk @[lsu.scala 313:49]
-    bus_intf.io.lsu_free_c2_clk <= clkdomain.io.lsu_free_c2_clk @[lsu.scala 314:49]
-    bus_intf.io.active_clk <= io.active_clk @[lsu.scala 315:49]
-    bus_intf.io.lsu_busm_clk <= clkdomain.io.lsu_busm_clk @[lsu.scala 316:49]
-    bus_intf.io.dec_lsu_valid_raw_d <= io.dec_lsu_valid_raw_d @[lsu.scala 317:49]
-    bus_intf.io.lsu_busreq_m <= lsu_busreq_m @[lsu.scala 318:49]
-    bus_intf.io.ldst_dual_d <= ldst_dual_d @[lsu.scala 319:49]
-    bus_intf.io.ldst_dual_m <= ldst_dual_m @[lsu.scala 320:49]
-    bus_intf.io.ldst_dual_r <= ldst_dual_r @[lsu.scala 321:49]
-    bus_intf.io.lsu_addr_m <= lsu_lsc_ctl.io.lsu_addr_m @[lsu.scala 322:49]
-    bus_intf.io.lsu_addr_r <= lsu_lsc_ctl.io.lsu_addr_r @[lsu.scala 323:49]
-    bus_intf.io.end_addr_m <= lsu_lsc_ctl.io.end_addr_m @[lsu.scala 324:49]
-    bus_intf.io.end_addr_r <= lsu_lsc_ctl.io.end_addr_r @[lsu.scala 325:49]
-    bus_intf.io.store_data_r <= dccm_ctl.io.store_data_r @[lsu.scala 326:49]
-    bus_intf.io.lsu_pkt_m.bits.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store_data_bypass_m @[lsu.scala 327:49]
-    bus_intf.io.lsu_pkt_m.bits.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.bits.load_ldst_bypass_d @[lsu.scala 327:49]
-    bus_intf.io.lsu_pkt_m.bits.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store_data_bypass_d @[lsu.scala 327:49]
-    bus_intf.io.lsu_pkt_m.bits.dma <= lsu_lsc_ctl.io.lsu_pkt_m.bits.dma @[lsu.scala 327:49]
-    bus_intf.io.lsu_pkt_m.bits.unsign <= lsu_lsc_ctl.io.lsu_pkt_m.bits.unsign @[lsu.scala 327:49]
-    bus_intf.io.lsu_pkt_m.bits.store <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store @[lsu.scala 327:49]
-    bus_intf.io.lsu_pkt_m.bits.load <= lsu_lsc_ctl.io.lsu_pkt_m.bits.load @[lsu.scala 327:49]
-    bus_intf.io.lsu_pkt_m.bits.dword <= lsu_lsc_ctl.io.lsu_pkt_m.bits.dword @[lsu.scala 327:49]
-    bus_intf.io.lsu_pkt_m.bits.word <= lsu_lsc_ctl.io.lsu_pkt_m.bits.word @[lsu.scala 327:49]
-    bus_intf.io.lsu_pkt_m.bits.half <= lsu_lsc_ctl.io.lsu_pkt_m.bits.half @[lsu.scala 327:49]
-    bus_intf.io.lsu_pkt_m.bits.by <= lsu_lsc_ctl.io.lsu_pkt_m.bits.by @[lsu.scala 327:49]
-    bus_intf.io.lsu_pkt_m.bits.fast_int <= lsu_lsc_ctl.io.lsu_pkt_m.bits.fast_int @[lsu.scala 327:49]
-    bus_intf.io.lsu_pkt_m.valid <= lsu_lsc_ctl.io.lsu_pkt_m.valid @[lsu.scala 327:49]
-    bus_intf.io.lsu_pkt_r.bits.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store_data_bypass_m @[lsu.scala 328:49]
-    bus_intf.io.lsu_pkt_r.bits.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_r.bits.load_ldst_bypass_d @[lsu.scala 328:49]
-    bus_intf.io.lsu_pkt_r.bits.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store_data_bypass_d @[lsu.scala 328:49]
-    bus_intf.io.lsu_pkt_r.bits.dma <= lsu_lsc_ctl.io.lsu_pkt_r.bits.dma @[lsu.scala 328:49]
-    bus_intf.io.lsu_pkt_r.bits.unsign <= lsu_lsc_ctl.io.lsu_pkt_r.bits.unsign @[lsu.scala 328:49]
-    bus_intf.io.lsu_pkt_r.bits.store <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store @[lsu.scala 328:49]
-    bus_intf.io.lsu_pkt_r.bits.load <= lsu_lsc_ctl.io.lsu_pkt_r.bits.load @[lsu.scala 328:49]
-    bus_intf.io.lsu_pkt_r.bits.dword <= lsu_lsc_ctl.io.lsu_pkt_r.bits.dword @[lsu.scala 328:49]
-    bus_intf.io.lsu_pkt_r.bits.word <= lsu_lsc_ctl.io.lsu_pkt_r.bits.word @[lsu.scala 328:49]
-    bus_intf.io.lsu_pkt_r.bits.half <= lsu_lsc_ctl.io.lsu_pkt_r.bits.half @[lsu.scala 328:49]
-    bus_intf.io.lsu_pkt_r.bits.by <= lsu_lsc_ctl.io.lsu_pkt_r.bits.by @[lsu.scala 328:49]
-    bus_intf.io.lsu_pkt_r.bits.fast_int <= lsu_lsc_ctl.io.lsu_pkt_r.bits.fast_int @[lsu.scala 328:49]
-    bus_intf.io.lsu_pkt_r.valid <= lsu_lsc_ctl.io.lsu_pkt_r.valid @[lsu.scala 328:49]
-    bus_intf.io.dec_tlu_force_halt <= io.dec_tlu_force_halt @[lsu.scala 329:49]
-    bus_intf.io.lsu_commit_r <= lsu_lsc_ctl.io.lsu_commit_r @[lsu.scala 330:49]
-    bus_intf.io.is_sideeffects_m <= lsu_lsc_ctl.io.is_sideeffects_m @[lsu.scala 331:49]
-    bus_intf.io.flush_m_up <= io.dec_tlu_flush_lower_r @[lsu.scala 332:49]
-    bus_intf.io.flush_r <= io.dec_tlu_i0_kill_writeb_r @[lsu.scala 333:49]
-    io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data <= bus_intf.io.dctl_busbuff.lsu_nonblock_load_data @[lsu.scala 335:27]
-    io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_tag <= bus_intf.io.dctl_busbuff.lsu_nonblock_load_data_tag @[lsu.scala 335:27]
-    io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_error <= bus_intf.io.dctl_busbuff.lsu_nonblock_load_data_error @[lsu.scala 335:27]
-    io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_valid <= bus_intf.io.dctl_busbuff.lsu_nonblock_load_data_valid @[lsu.scala 335:27]
-    io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_tag_r <= bus_intf.io.dctl_busbuff.lsu_nonblock_load_inv_tag_r @[lsu.scala 335:27]
-    io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_r <= bus_intf.io.dctl_busbuff.lsu_nonblock_load_inv_r @[lsu.scala 335:27]
-    io.lsu_dec.dctl_busbuff.lsu_nonblock_load_tag_m <= bus_intf.io.dctl_busbuff.lsu_nonblock_load_tag_m @[lsu.scala 335:27]
-    io.lsu_dec.dctl_busbuff.lsu_nonblock_load_valid_m <= bus_intf.io.dctl_busbuff.lsu_nonblock_load_valid_m @[lsu.scala 335:27]
-    bus_intf.io.axi.r.bits.last <= io.axi.r.bits.last @[lsu.scala 336:49]
-    bus_intf.io.axi.r.bits.resp <= io.axi.r.bits.resp @[lsu.scala 336:49]
-    bus_intf.io.axi.r.bits.data <= io.axi.r.bits.data @[lsu.scala 336:49]
-    bus_intf.io.axi.r.bits.id <= io.axi.r.bits.id @[lsu.scala 336:49]
-    bus_intf.io.axi.r.valid <= io.axi.r.valid @[lsu.scala 336:49]
-    io.axi.r.ready <= bus_intf.io.axi.r.ready @[lsu.scala 336:49]
-    io.axi.ar.bits.qos <= bus_intf.io.axi.ar.bits.qos @[lsu.scala 336:49]
-    io.axi.ar.bits.prot <= bus_intf.io.axi.ar.bits.prot @[lsu.scala 336:49]
-    io.axi.ar.bits.cache <= bus_intf.io.axi.ar.bits.cache @[lsu.scala 336:49]
-    io.axi.ar.bits.lock <= bus_intf.io.axi.ar.bits.lock @[lsu.scala 336:49]
-    io.axi.ar.bits.burst <= bus_intf.io.axi.ar.bits.burst @[lsu.scala 336:49]
-    io.axi.ar.bits.size <= bus_intf.io.axi.ar.bits.size @[lsu.scala 336:49]
-    io.axi.ar.bits.len <= bus_intf.io.axi.ar.bits.len @[lsu.scala 336:49]
-    io.axi.ar.bits.region <= bus_intf.io.axi.ar.bits.region @[lsu.scala 336:49]
-    io.axi.ar.bits.addr <= bus_intf.io.axi.ar.bits.addr @[lsu.scala 336:49]
-    io.axi.ar.bits.id <= bus_intf.io.axi.ar.bits.id @[lsu.scala 336:49]
-    io.axi.ar.valid <= bus_intf.io.axi.ar.valid @[lsu.scala 336:49]
-    bus_intf.io.axi.ar.ready <= io.axi.ar.ready @[lsu.scala 336:49]
-    bus_intf.io.axi.b.bits.id <= io.axi.b.bits.id @[lsu.scala 336:49]
-    bus_intf.io.axi.b.bits.resp <= io.axi.b.bits.resp @[lsu.scala 336:49]
-    bus_intf.io.axi.b.valid <= io.axi.b.valid @[lsu.scala 336:49]
-    io.axi.b.ready <= bus_intf.io.axi.b.ready @[lsu.scala 336:49]
-    io.axi.w.bits.last <= bus_intf.io.axi.w.bits.last @[lsu.scala 336:49]
-    io.axi.w.bits.strb <= bus_intf.io.axi.w.bits.strb @[lsu.scala 336:49]
-    io.axi.w.bits.data <= bus_intf.io.axi.w.bits.data @[lsu.scala 336:49]
-    io.axi.w.valid <= bus_intf.io.axi.w.valid @[lsu.scala 336:49]
-    bus_intf.io.axi.w.ready <= io.axi.w.ready @[lsu.scala 336:49]
-    io.axi.aw.bits.qos <= bus_intf.io.axi.aw.bits.qos @[lsu.scala 336:49]
-    io.axi.aw.bits.prot <= bus_intf.io.axi.aw.bits.prot @[lsu.scala 336:49]
-    io.axi.aw.bits.cache <= bus_intf.io.axi.aw.bits.cache @[lsu.scala 336:49]
-    io.axi.aw.bits.lock <= bus_intf.io.axi.aw.bits.lock @[lsu.scala 336:49]
-    io.axi.aw.bits.burst <= bus_intf.io.axi.aw.bits.burst @[lsu.scala 336:49]
-    io.axi.aw.bits.size <= bus_intf.io.axi.aw.bits.size @[lsu.scala 336:49]
-    io.axi.aw.bits.len <= bus_intf.io.axi.aw.bits.len @[lsu.scala 336:49]
-    io.axi.aw.bits.region <= bus_intf.io.axi.aw.bits.region @[lsu.scala 336:49]
-    io.axi.aw.bits.addr <= bus_intf.io.axi.aw.bits.addr @[lsu.scala 336:49]
-    io.axi.aw.bits.id <= bus_intf.io.axi.aw.bits.id @[lsu.scala 336:49]
-    io.axi.aw.valid <= bus_intf.io.axi.aw.valid @[lsu.scala 336:49]
-    bus_intf.io.axi.aw.ready <= io.axi.aw.ready @[lsu.scala 336:49]
-    bus_intf.io.lsu_bus_clk_en <= io.lsu_bus_clk_en @[lsu.scala 337:49]
-    reg _T_67 : UInt, clkdomain.io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu.scala 339:67]
-    _T_67 <= io.lsu_dma.dma_mem_tag @[lsu.scala 339:67]
-    dma_mem_tag_m <= _T_67 @[lsu.scala 339:57]
-    reg _T_68 : UInt<1>, clkdomain.io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu.scala 340:67]
-    _T_68 <= lsu_raw_fwd_hi_m @[lsu.scala 340:67]
-    lsu_raw_fwd_hi_r <= _T_68 @[lsu.scala 340:57]
-    reg _T_69 : UInt<1>, clkdomain.io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu.scala 341:67]
-    _T_69 <= lsu_raw_fwd_lo_m @[lsu.scala 341:67]
-    lsu_raw_fwd_lo_r <= _T_69 @[lsu.scala 341:57]
+    node _T_16 = dshr(io.lsu_dma.dma_lsc_ctl.dma_mem_wdata, _T_15) @[lsu.scala 95:58]
+    dma_dccm_wdata <= _T_16 @[lsu.scala 95:18]
+    node _T_17 = bits(dma_dccm_wdata, 63, 32) @[lsu.scala 96:38]
+    dma_dccm_wdata_hi <= _T_17 @[lsu.scala 96:21]
+    node _T_18 = bits(dma_dccm_wdata, 31, 0) @[lsu.scala 97:38]
+    dma_dccm_wdata_lo <= _T_18 @[lsu.scala 97:21]
+    node _T_19 = eq(lsu_lsc_ctl.io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu.scala 106:58]
+    node _T_20 = and(lsu_lsc_ctl.io.lsu_pkt_m.valid, _T_19) @[lsu.scala 106:56]
+    node _T_21 = eq(lsu_lsc_ctl.io.lsu_pkt_r.bits.dma, UInt<1>("h00")) @[lsu.scala 106:130]
+    node _T_22 = and(lsu_lsc_ctl.io.lsu_pkt_r.valid, _T_21) @[lsu.scala 106:128]
+    node _T_23 = or(_T_20, _T_22) @[lsu.scala 106:94]
+    node _T_24 = eq(_T_23, UInt<1>("h00")) @[lsu.scala 106:22]
+    node _T_25 = and(_T_24, bus_intf.io.lsu_bus_buffer_empty_any) @[lsu.scala 106:167]
+    io.lsu_idle_any <= _T_25 @[lsu.scala 106:19]
+    node _T_26 = or(lsu_lsc_ctl.io.lsu_pkt_m.valid, lsu_lsc_ctl.io.lsu_pkt_r.valid) @[lsu.scala 107:52]
+    node _T_27 = or(_T_26, dccm_ctl.io.ld_single_ecc_error_r_ff) @[lsu.scala 107:85]
+    node _T_28 = eq(bus_intf.io.lsu_bus_buffer_empty_any, UInt<1>("h00")) @[lsu.scala 107:127]
+    node _T_29 = or(_T_27, _T_28) @[lsu.scala 107:125]
+    io.lsu_active <= _T_29 @[lsu.scala 107:17]
+    node _T_30 = and(lsu_lsc_ctl.io.lsu_pkt_r.valid, lsu_lsc_ctl.io.lsu_pkt_r.bits.store) @[lsu.scala 109:61]
+    node _T_31 = and(_T_30, lsu_lsc_ctl.io.addr_in_dccm_r) @[lsu.scala 109:99]
+    node _T_32 = eq(io.dec_tlu_i0_kill_writeb_r, UInt<1>("h00")) @[lsu.scala 109:133]
+    node _T_33 = and(_T_31, _T_32) @[lsu.scala 109:131]
+    node _T_34 = eq(lsu_lsc_ctl.io.lsu_pkt_r.bits.dma, UInt<1>("h00")) @[lsu.scala 109:145]
+    node _T_35 = or(lsu_lsc_ctl.io.lsu_pkt_r.bits.by, lsu_lsc_ctl.io.lsu_pkt_r.bits.half) @[lsu.scala 109:217]
+    node _T_36 = eq(ecc.io.lsu_double_ecc_error_r, UInt<1>("h00")) @[lsu.scala 109:257]
+    node _T_37 = and(_T_35, _T_36) @[lsu.scala 109:255]
+    node _T_38 = or(_T_34, _T_37) @[lsu.scala 109:180]
+    node store_stbuf_reqvld_r = and(_T_33, _T_38) @[lsu.scala 109:142]
+    node _T_39 = or(lsu_lsc_ctl.io.lsu_pkt_m.bits.load, lsu_lsc_ctl.io.lsu_pkt_m.bits.store) @[lsu.scala 111:90]
+    node _T_40 = and(lsu_lsc_ctl.io.lsu_pkt_m.valid, _T_39) @[lsu.scala 111:52]
+    node _T_41 = or(lsu_lsc_ctl.io.addr_in_dccm_m, lsu_lsc_ctl.io.addr_in_pic_m) @[lsu.scala 111:162]
+    node lsu_cmpen_m = and(_T_40, _T_41) @[lsu.scala 111:129]
+    node _T_42 = or(lsu_lsc_ctl.io.lsu_pkt_m.bits.load, lsu_lsc_ctl.io.lsu_pkt_m.bits.store) @[lsu.scala 113:92]
+    node _T_43 = and(_T_42, lsu_lsc_ctl.io.addr_external_m) @[lsu.scala 113:131]
+    node _T_44 = and(lsu_lsc_ctl.io.lsu_pkt_m.valid, _T_43) @[lsu.scala 113:53]
+    node _T_45 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[lsu.scala 113:167]
+    node _T_46 = and(_T_44, _T_45) @[lsu.scala 113:165]
+    node _T_47 = eq(lsu_lsc_ctl.io.lsu_exc_m, UInt<1>("h00")) @[lsu.scala 113:181]
+    node _T_48 = and(_T_46, _T_47) @[lsu.scala 113:179]
+    node _T_49 = eq(lsu_lsc_ctl.io.lsu_pkt_m.bits.fast_int, UInt<1>("h00")) @[lsu.scala 113:209]
+    node lsu_busreq_m = and(_T_48, _T_49) @[lsu.scala 113:207]
+    node _T_50 = bits(lsu_addr_d, 2, 2) @[lsu.scala 115:32]
+    node _T_51 = bits(end_addr_d, 2, 2) @[lsu.scala 115:50]
+    node ldst_dual_d = neq(_T_50, _T_51) @[lsu.scala 115:36]
+    node _T_52 = bits(lsu_addr_m, 2, 2) @[lsu.scala 116:32]
+    node _T_53 = bits(end_addr_m, 2, 2) @[lsu.scala 116:50]
+    node ldst_dual_m = neq(_T_52, _T_53) @[lsu.scala 116:36]
+    node _T_54 = bits(lsu_addr_r, 2, 2) @[lsu.scala 117:32]
+    node _T_55 = bits(end_addr_r, 2, 2) @[lsu.scala 117:50]
+    node ldst_dual_r = neq(_T_54, _T_55) @[lsu.scala 117:36]
+    node _T_56 = bits(lsu_lsc_ctl.io.lsu_addr_m, 0, 0) @[lsu.scala 119:127]
+    node _T_57 = and(lsu_lsc_ctl.io.lsu_pkt_m.bits.half, _T_56) @[lsu.scala 119:100]
+    node _T_58 = bits(lsu_lsc_ctl.io.lsu_addr_m, 1, 0) @[lsu.scala 119:197]
+    node _T_59 = orr(_T_58) @[lsu.scala 119:203]
+    node _T_60 = and(lsu_lsc_ctl.io.lsu_pkt_m.bits.word, _T_59) @[lsu.scala 119:170]
+    node _T_61 = or(_T_57, _T_60) @[lsu.scala 119:132]
+    node _T_62 = and(lsu_lsc_ctl.io.lsu_pkt_m.valid, _T_61) @[lsu.scala 119:61]
+    io.lsu_pmu_misaligned_m <= _T_62 @[lsu.scala 119:27]
+    node _T_63 = and(lsu_lsc_ctl.io.lsu_pkt_m.valid, lsu_lsc_ctl.io.lsu_pkt_m.bits.load) @[lsu.scala 120:73]
+    node _T_64 = and(_T_63, lsu_lsc_ctl.io.addr_external_m) @[lsu.scala 120:110]
+    io.lsu_tlu.lsu_pmu_load_external_m <= _T_64 @[lsu.scala 120:39]
+    node _T_65 = and(lsu_lsc_ctl.io.lsu_pkt_m.valid, lsu_lsc_ctl.io.lsu_pkt_m.bits.store) @[lsu.scala 121:73]
+    node _T_66 = and(_T_65, lsu_lsc_ctl.io.addr_external_m) @[lsu.scala 121:111]
+    io.lsu_tlu.lsu_pmu_store_external_m <= _T_66 @[lsu.scala 121:39]
+    lsu_lsc_ctl.io.clk_override <= io.clk_override @[lsu.scala 125:46]
+    lsu_lsc_ctl.io.lsu_c1_m_clk <= clkdomain.io.lsu_c1_m_clk @[lsu.scala 126:46]
+    lsu_lsc_ctl.io.lsu_c1_r_clk <= clkdomain.io.lsu_c1_r_clk @[lsu.scala 127:46]
+    lsu_lsc_ctl.io.lsu_c2_m_clk <= clkdomain.io.lsu_c2_m_clk @[lsu.scala 128:46]
+    lsu_lsc_ctl.io.lsu_c2_r_clk <= clkdomain.io.lsu_c2_r_clk @[lsu.scala 129:46]
+    lsu_lsc_ctl.io.lsu_store_c1_m_clk <= clkdomain.io.lsu_store_c1_m_clk @[lsu.scala 130:46]
+    lsu_lsc_ctl.io.lsu_ld_data_r <= dccm_ctl.io.lsu_ld_data_r @[lsu.scala 131:46]
+    lsu_lsc_ctl.io.lsu_ld_data_corr_r <= dccm_ctl.io.lsu_ld_data_corr_r @[lsu.scala 132:46]
+    lsu_lsc_ctl.io.lsu_single_ecc_error_r <= ecc.io.lsu_single_ecc_error_r @[lsu.scala 133:46]
+    lsu_lsc_ctl.io.lsu_double_ecc_error_r <= ecc.io.lsu_double_ecc_error_r @[lsu.scala 134:46]
+    lsu_lsc_ctl.io.lsu_ld_data_m <= dccm_ctl.io.lsu_ld_data_m @[lsu.scala 135:46]
+    lsu_lsc_ctl.io.lsu_single_ecc_error_m <= ecc.io.lsu_single_ecc_error_m @[lsu.scala 136:46]
+    lsu_lsc_ctl.io.lsu_double_ecc_error_m <= ecc.io.lsu_double_ecc_error_m @[lsu.scala 137:46]
+    lsu_lsc_ctl.io.flush_m_up <= io.dec_tlu_flush_lower_r @[lsu.scala 138:46]
+    lsu_lsc_ctl.io.flush_r <= io.dec_tlu_i0_kill_writeb_r @[lsu.scala 139:46]
+    lsu_lsc_ctl.io.ldst_dual_d <= ldst_dual_d @[lsu.scala 140:46]
+    lsu_lsc_ctl.io.ldst_dual_m <= ldst_dual_m @[lsu.scala 141:46]
+    lsu_lsc_ctl.io.ldst_dual_r <= ldst_dual_r @[lsu.scala 142:46]
+    lsu_lsc_ctl.io.lsu_exu.exu_lsu_rs2_d <= io.lsu_exu.exu_lsu_rs2_d @[lsu.scala 143:46]
+    lsu_lsc_ctl.io.lsu_exu.exu_lsu_rs1_d <= io.lsu_exu.exu_lsu_rs1_d @[lsu.scala 143:46]
+    lsu_lsc_ctl.io.lsu_p.bits.store_data_bypass_m <= io.lsu_p.bits.store_data_bypass_m @[lsu.scala 144:46]
+    lsu_lsc_ctl.io.lsu_p.bits.load_ldst_bypass_d <= io.lsu_p.bits.load_ldst_bypass_d @[lsu.scala 144:46]
+    lsu_lsc_ctl.io.lsu_p.bits.store_data_bypass_d <= io.lsu_p.bits.store_data_bypass_d @[lsu.scala 144:46]
+    lsu_lsc_ctl.io.lsu_p.bits.dma <= io.lsu_p.bits.dma @[lsu.scala 144:46]
+    lsu_lsc_ctl.io.lsu_p.bits.unsign <= io.lsu_p.bits.unsign @[lsu.scala 144:46]
+    lsu_lsc_ctl.io.lsu_p.bits.store <= io.lsu_p.bits.store @[lsu.scala 144:46]
+    lsu_lsc_ctl.io.lsu_p.bits.load <= io.lsu_p.bits.load @[lsu.scala 144:46]
+    lsu_lsc_ctl.io.lsu_p.bits.dword <= io.lsu_p.bits.dword @[lsu.scala 144:46]
+    lsu_lsc_ctl.io.lsu_p.bits.word <= io.lsu_p.bits.word @[lsu.scala 144:46]
+    lsu_lsc_ctl.io.lsu_p.bits.half <= io.lsu_p.bits.half @[lsu.scala 144:46]
+    lsu_lsc_ctl.io.lsu_p.bits.by <= io.lsu_p.bits.by @[lsu.scala 144:46]
+    lsu_lsc_ctl.io.lsu_p.bits.stack <= io.lsu_p.bits.stack @[lsu.scala 144:46]
+    lsu_lsc_ctl.io.lsu_p.bits.fast_int <= io.lsu_p.bits.fast_int @[lsu.scala 144:46]
+    lsu_lsc_ctl.io.lsu_p.valid <= io.lsu_p.valid @[lsu.scala 144:46]
+    lsu_lsc_ctl.io.dec_lsu_valid_raw_d <= io.dec_lsu_valid_raw_d @[lsu.scala 145:46]
+    lsu_lsc_ctl.io.dec_lsu_offset_d <= io.dec_lsu_offset_d @[lsu.scala 146:46]
+    lsu_lsc_ctl.io.picm_mask_data_m <= dccm_ctl.io.picm_mask_data_m @[lsu.scala 147:46]
+    lsu_lsc_ctl.io.bus_read_data_m <= bus_intf.io.bus_read_data_m @[lsu.scala 148:46]
+    lsu_lsc_ctl.io.dma_lsc_ctl.dma_mem_wdata <= io.lsu_dma.dma_lsc_ctl.dma_mem_wdata @[lsu.scala 149:46]
+    lsu_lsc_ctl.io.dma_lsc_ctl.dma_mem_write <= io.lsu_dma.dma_lsc_ctl.dma_mem_write @[lsu.scala 149:46]
+    lsu_lsc_ctl.io.dma_lsc_ctl.dma_mem_sz <= io.lsu_dma.dma_lsc_ctl.dma_mem_sz @[lsu.scala 149:46]
+    lsu_lsc_ctl.io.dma_lsc_ctl.dma_mem_addr <= io.lsu_dma.dma_lsc_ctl.dma_mem_addr @[lsu.scala 149:46]
+    lsu_lsc_ctl.io.dma_lsc_ctl.dma_dccm_req <= io.lsu_dma.dma_lsc_ctl.dma_dccm_req @[lsu.scala 149:46]
+    lsu_lsc_ctl.io.dec_tlu_mrac_ff <= io.dec_tlu_mrac_ff @[lsu.scala 150:46]
+    lsu_lsc_ctl.io.scan_mode <= io.scan_mode @[lsu.scala 151:46]
+    lsu_addr_d <= lsu_lsc_ctl.io.lsu_addr_d @[lsu.scala 153:14]
+    lsu_addr_m <= lsu_lsc_ctl.io.lsu_addr_m @[lsu.scala 154:14]
+    lsu_addr_r <= lsu_lsc_ctl.io.lsu_addr_r @[lsu.scala 155:14]
+    end_addr_d <= lsu_lsc_ctl.io.lsu_addr_d @[lsu.scala 156:14]
+    end_addr_m <= lsu_lsc_ctl.io.lsu_addr_m @[lsu.scala 157:14]
+    end_addr_r <= lsu_lsc_ctl.io.lsu_addr_r @[lsu.scala 158:14]
+    io.lsu_single_ecc_error_incr <= lsu_lsc_ctl.io.lsu_single_ecc_error_incr @[lsu.scala 159:49]
+    io.lsu_error_pkt_r.bits.addr <= lsu_lsc_ctl.io.lsu_error_pkt_r.bits.addr @[lsu.scala 160:49]
+    io.lsu_error_pkt_r.bits.mscause <= lsu_lsc_ctl.io.lsu_error_pkt_r.bits.mscause @[lsu.scala 160:49]
+    io.lsu_error_pkt_r.bits.exc_type <= lsu_lsc_ctl.io.lsu_error_pkt_r.bits.exc_type @[lsu.scala 160:49]
+    io.lsu_error_pkt_r.bits.inst_type <= lsu_lsc_ctl.io.lsu_error_pkt_r.bits.inst_type @[lsu.scala 160:49]
+    io.lsu_error_pkt_r.bits.single_ecc_error <= lsu_lsc_ctl.io.lsu_error_pkt_r.bits.single_ecc_error @[lsu.scala 160:49]
+    io.lsu_error_pkt_r.valid <= lsu_lsc_ctl.io.lsu_error_pkt_r.valid @[lsu.scala 160:49]
+    io.lsu_fir_addr <= lsu_lsc_ctl.io.lsu_fir_addr @[lsu.scala 161:49]
+    io.lsu_fir_error <= lsu_lsc_ctl.io.lsu_fir_error @[lsu.scala 162:49]
+    dccm_ctl.io.clk_override <= io.clk_override @[lsu.scala 165:46]
+    dccm_ctl.io.ldst_dual_m <= ldst_dual_m @[lsu.scala 166:46]
+    dccm_ctl.io.ldst_dual_r <= ldst_dual_r @[lsu.scala 167:46]
+    dccm_ctl.io.lsu_c2_m_clk <= clkdomain.io.lsu_c2_m_clk @[lsu.scala 168:46]
+    dccm_ctl.io.lsu_c2_r_clk <= clkdomain.io.lsu_c2_r_clk @[lsu.scala 169:46]
+    dccm_ctl.io.lsu_free_c2_clk <= clkdomain.io.lsu_free_c2_clk @[lsu.scala 170:46]
+    dccm_ctl.io.lsu_c1_r_clk <= clkdomain.io.lsu_c1_r_clk @[lsu.scala 171:46]
+    dccm_ctl.io.lsu_store_c1_r_clk <= clkdomain.io.lsu_store_c1_r_clk @[lsu.scala 172:46]
+    dccm_ctl.io.lsu_pkt_d.bits.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_d.bits.store_data_bypass_m @[lsu.scala 173:46]
+    dccm_ctl.io.lsu_pkt_d.bits.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_d.bits.load_ldst_bypass_d @[lsu.scala 173:46]
+    dccm_ctl.io.lsu_pkt_d.bits.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_d.bits.store_data_bypass_d @[lsu.scala 173:46]
+    dccm_ctl.io.lsu_pkt_d.bits.dma <= lsu_lsc_ctl.io.lsu_pkt_d.bits.dma @[lsu.scala 173:46]
+    dccm_ctl.io.lsu_pkt_d.bits.unsign <= lsu_lsc_ctl.io.lsu_pkt_d.bits.unsign @[lsu.scala 173:46]
+    dccm_ctl.io.lsu_pkt_d.bits.store <= lsu_lsc_ctl.io.lsu_pkt_d.bits.store @[lsu.scala 173:46]
+    dccm_ctl.io.lsu_pkt_d.bits.load <= lsu_lsc_ctl.io.lsu_pkt_d.bits.load @[lsu.scala 173:46]
+    dccm_ctl.io.lsu_pkt_d.bits.dword <= lsu_lsc_ctl.io.lsu_pkt_d.bits.dword @[lsu.scala 173:46]
+    dccm_ctl.io.lsu_pkt_d.bits.word <= lsu_lsc_ctl.io.lsu_pkt_d.bits.word @[lsu.scala 173:46]
+    dccm_ctl.io.lsu_pkt_d.bits.half <= lsu_lsc_ctl.io.lsu_pkt_d.bits.half @[lsu.scala 173:46]
+    dccm_ctl.io.lsu_pkt_d.bits.by <= lsu_lsc_ctl.io.lsu_pkt_d.bits.by @[lsu.scala 173:46]
+    dccm_ctl.io.lsu_pkt_d.bits.stack <= lsu_lsc_ctl.io.lsu_pkt_d.bits.stack @[lsu.scala 173:46]
+    dccm_ctl.io.lsu_pkt_d.bits.fast_int <= lsu_lsc_ctl.io.lsu_pkt_d.bits.fast_int @[lsu.scala 173:46]
+    dccm_ctl.io.lsu_pkt_d.valid <= lsu_lsc_ctl.io.lsu_pkt_d.valid @[lsu.scala 173:46]
+    dccm_ctl.io.lsu_pkt_m.bits.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store_data_bypass_m @[lsu.scala 174:46]
+    dccm_ctl.io.lsu_pkt_m.bits.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.bits.load_ldst_bypass_d @[lsu.scala 174:46]
+    dccm_ctl.io.lsu_pkt_m.bits.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store_data_bypass_d @[lsu.scala 174:46]
+    dccm_ctl.io.lsu_pkt_m.bits.dma <= lsu_lsc_ctl.io.lsu_pkt_m.bits.dma @[lsu.scala 174:46]
+    dccm_ctl.io.lsu_pkt_m.bits.unsign <= lsu_lsc_ctl.io.lsu_pkt_m.bits.unsign @[lsu.scala 174:46]
+    dccm_ctl.io.lsu_pkt_m.bits.store <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store @[lsu.scala 174:46]
+    dccm_ctl.io.lsu_pkt_m.bits.load <= lsu_lsc_ctl.io.lsu_pkt_m.bits.load @[lsu.scala 174:46]
+    dccm_ctl.io.lsu_pkt_m.bits.dword <= lsu_lsc_ctl.io.lsu_pkt_m.bits.dword @[lsu.scala 174:46]
+    dccm_ctl.io.lsu_pkt_m.bits.word <= lsu_lsc_ctl.io.lsu_pkt_m.bits.word @[lsu.scala 174:46]
+    dccm_ctl.io.lsu_pkt_m.bits.half <= lsu_lsc_ctl.io.lsu_pkt_m.bits.half @[lsu.scala 174:46]
+    dccm_ctl.io.lsu_pkt_m.bits.by <= lsu_lsc_ctl.io.lsu_pkt_m.bits.by @[lsu.scala 174:46]
+    dccm_ctl.io.lsu_pkt_m.bits.stack <= lsu_lsc_ctl.io.lsu_pkt_m.bits.stack @[lsu.scala 174:46]
+    dccm_ctl.io.lsu_pkt_m.bits.fast_int <= lsu_lsc_ctl.io.lsu_pkt_m.bits.fast_int @[lsu.scala 174:46]
+    dccm_ctl.io.lsu_pkt_m.valid <= lsu_lsc_ctl.io.lsu_pkt_m.valid @[lsu.scala 174:46]
+    dccm_ctl.io.lsu_pkt_r.bits.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store_data_bypass_m @[lsu.scala 175:46]
+    dccm_ctl.io.lsu_pkt_r.bits.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_r.bits.load_ldst_bypass_d @[lsu.scala 175:46]
+    dccm_ctl.io.lsu_pkt_r.bits.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store_data_bypass_d @[lsu.scala 175:46]
+    dccm_ctl.io.lsu_pkt_r.bits.dma <= lsu_lsc_ctl.io.lsu_pkt_r.bits.dma @[lsu.scala 175:46]
+    dccm_ctl.io.lsu_pkt_r.bits.unsign <= lsu_lsc_ctl.io.lsu_pkt_r.bits.unsign @[lsu.scala 175:46]
+    dccm_ctl.io.lsu_pkt_r.bits.store <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store @[lsu.scala 175:46]
+    dccm_ctl.io.lsu_pkt_r.bits.load <= lsu_lsc_ctl.io.lsu_pkt_r.bits.load @[lsu.scala 175:46]
+    dccm_ctl.io.lsu_pkt_r.bits.dword <= lsu_lsc_ctl.io.lsu_pkt_r.bits.dword @[lsu.scala 175:46]
+    dccm_ctl.io.lsu_pkt_r.bits.word <= lsu_lsc_ctl.io.lsu_pkt_r.bits.word @[lsu.scala 175:46]
+    dccm_ctl.io.lsu_pkt_r.bits.half <= lsu_lsc_ctl.io.lsu_pkt_r.bits.half @[lsu.scala 175:46]
+    dccm_ctl.io.lsu_pkt_r.bits.by <= lsu_lsc_ctl.io.lsu_pkt_r.bits.by @[lsu.scala 175:46]
+    dccm_ctl.io.lsu_pkt_r.bits.stack <= lsu_lsc_ctl.io.lsu_pkt_r.bits.stack @[lsu.scala 175:46]
+    dccm_ctl.io.lsu_pkt_r.bits.fast_int <= lsu_lsc_ctl.io.lsu_pkt_r.bits.fast_int @[lsu.scala 175:46]
+    dccm_ctl.io.lsu_pkt_r.valid <= lsu_lsc_ctl.io.lsu_pkt_r.valid @[lsu.scala 175:46]
+    dccm_ctl.io.addr_in_dccm_d <= lsu_lsc_ctl.io.addr_in_dccm_d @[lsu.scala 176:46]
+    dccm_ctl.io.addr_in_dccm_m <= lsu_lsc_ctl.io.addr_in_dccm_m @[lsu.scala 177:46]
+    dccm_ctl.io.addr_in_dccm_r <= lsu_lsc_ctl.io.addr_in_dccm_r @[lsu.scala 178:46]
+    dccm_ctl.io.addr_in_pic_d <= lsu_lsc_ctl.io.addr_in_pic_d @[lsu.scala 179:46]
+    dccm_ctl.io.addr_in_pic_m <= lsu_lsc_ctl.io.addr_in_pic_m @[lsu.scala 180:46]
+    dccm_ctl.io.addr_in_pic_r <= lsu_lsc_ctl.io.addr_in_pic_r @[lsu.scala 181:46]
+    dccm_ctl.io.lsu_raw_fwd_lo_r <= lsu_raw_fwd_lo_r @[lsu.scala 182:46]
+    dccm_ctl.io.lsu_raw_fwd_hi_r <= lsu_raw_fwd_hi_r @[lsu.scala 183:46]
+    dccm_ctl.io.lsu_commit_r <= lsu_lsc_ctl.io.lsu_commit_r @[lsu.scala 184:46]
+    dccm_ctl.io.lsu_addr_d <= lsu_addr_d @[lsu.scala 185:46]
+    node _T_67 = bits(lsu_addr_m, 15, 0) @[lsu.scala 186:59]
+    dccm_ctl.io.lsu_addr_m <= _T_67 @[lsu.scala 186:46]
+    dccm_ctl.io.lsu_addr_r <= lsu_addr_r @[lsu.scala 187:46]
+    node _T_68 = bits(end_addr_d, 15, 0) @[lsu.scala 188:59]
+    dccm_ctl.io.end_addr_d <= _T_68 @[lsu.scala 188:46]
+    node _T_69 = bits(end_addr_m, 15, 0) @[lsu.scala 189:59]
+    dccm_ctl.io.end_addr_m <= _T_69 @[lsu.scala 189:46]
+    node _T_70 = bits(end_addr_r, 15, 0) @[lsu.scala 190:59]
+    dccm_ctl.io.end_addr_r <= _T_70 @[lsu.scala 190:46]
+    dccm_ctl.io.stbuf_reqvld_any <= stbuf.io.stbuf_reqvld_any @[lsu.scala 191:46]
+    dccm_ctl.io.stbuf_addr_any <= stbuf.io.stbuf_addr_any @[lsu.scala 192:46]
+    dccm_ctl.io.stbuf_data_any <= stbuf.io.stbuf_data_any @[lsu.scala 193:46]
+    dccm_ctl.io.stbuf_ecc_any <= ecc.io.stbuf_ecc_any @[lsu.scala 194:46]
+    dccm_ctl.io.stbuf_fwddata_hi_m <= stbuf.io.stbuf_fwddata_hi_m @[lsu.scala 195:46]
+    dccm_ctl.io.stbuf_fwddata_lo_m <= stbuf.io.stbuf_fwddata_lo_m @[lsu.scala 196:46]
+    dccm_ctl.io.stbuf_fwdbyteen_lo_m <= stbuf.io.stbuf_fwdbyteen_lo_m @[lsu.scala 197:46]
+    dccm_ctl.io.stbuf_fwdbyteen_hi_m <= stbuf.io.stbuf_fwdbyteen_hi_m @[lsu.scala 198:46]
+    dccm_ctl.io.lsu_double_ecc_error_r <= ecc.io.lsu_double_ecc_error_r @[lsu.scala 199:46]
+    dccm_ctl.io.single_ecc_error_hi_r <= ecc.io.single_ecc_error_hi_r @[lsu.scala 200:46]
+    dccm_ctl.io.single_ecc_error_lo_r <= ecc.io.single_ecc_error_lo_r @[lsu.scala 201:46]
+    dccm_ctl.io.sec_data_hi_r <= ecc.io.sec_data_hi_r @[lsu.scala 202:46]
+    dccm_ctl.io.sec_data_lo_r <= ecc.io.sec_data_lo_r @[lsu.scala 203:46]
+    dccm_ctl.io.sec_data_hi_r_ff <= ecc.io.sec_data_hi_r_ff @[lsu.scala 204:46]
+    dccm_ctl.io.sec_data_lo_r_ff <= ecc.io.sec_data_lo_r_ff @[lsu.scala 205:46]
+    dccm_ctl.io.sec_data_ecc_hi_r_ff <= ecc.io.sec_data_ecc_hi_r_ff @[lsu.scala 206:46]
+    dccm_ctl.io.sec_data_ecc_lo_r_ff <= ecc.io.sec_data_ecc_lo_r_ff @[lsu.scala 207:46]
+    dccm_ctl.io.lsu_double_ecc_error_m <= ecc.io.lsu_double_ecc_error_m @[lsu.scala 208:46]
+    dccm_ctl.io.sec_data_hi_m <= ecc.io.sec_data_hi_m @[lsu.scala 209:46]
+    dccm_ctl.io.sec_data_lo_m <= ecc.io.sec_data_lo_m @[lsu.scala 210:46]
+    dccm_ctl.io.store_data_m <= lsu_lsc_ctl.io.store_data_m @[lsu.scala 211:46]
+    dccm_ctl.io.dma_dccm_wen <= dma_dccm_wen @[lsu.scala 212:46]
+    dccm_ctl.io.dma_pic_wen <= dma_pic_wen @[lsu.scala 213:46]
+    dccm_ctl.io.dma_mem_tag_m <= dma_mem_tag_m @[lsu.scala 214:46]
+    dccm_ctl.io.dma_dccm_wdata_lo <= dma_dccm_wdata_lo @[lsu.scala 215:46]
+    dccm_ctl.io.dma_dccm_wdata_hi <= dma_dccm_wdata_hi @[lsu.scala 216:46]
+    dccm_ctl.io.dma_dccm_wdata_ecc_hi <= ecc.io.dma_dccm_wdata_ecc_hi @[lsu.scala 217:46]
+    dccm_ctl.io.dma_dccm_wdata_ecc_lo <= ecc.io.dma_dccm_wdata_ecc_lo @[lsu.scala 218:46]
+    dccm_ctl.io.scan_mode <= io.scan_mode @[lsu.scala 219:46]
+    io.lsu_dma.dma_dccm_ctl.dccm_dma_rdata <= dccm_ctl.io.dma_dccm_ctl.dccm_dma_rdata @[lsu.scala 221:27]
+    io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag <= dccm_ctl.io.dma_dccm_ctl.dccm_dma_rtag @[lsu.scala 221:27]
+    io.lsu_dma.dma_dccm_ctl.dccm_dma_ecc_error <= dccm_ctl.io.dma_dccm_ctl.dccm_dma_ecc_error @[lsu.scala 221:27]
+    io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid <= dccm_ctl.io.dma_dccm_ctl.dccm_dma_rvalid @[lsu.scala 221:27]
+    dccm_ctl.io.dma_dccm_ctl.dma_mem_wdata <= io.lsu_dma.dma_dccm_ctl.dma_mem_wdata @[lsu.scala 221:27]
+    dccm_ctl.io.dma_dccm_ctl.dma_mem_addr <= io.lsu_dma.dma_dccm_ctl.dma_mem_addr @[lsu.scala 221:27]
+    dccm_ctl.io.dccm.rd_data_hi <= io.dccm.rd_data_hi @[lsu.scala 222:11]
+    dccm_ctl.io.dccm.rd_data_lo <= io.dccm.rd_data_lo @[lsu.scala 222:11]
+    io.dccm.wr_data_hi <= dccm_ctl.io.dccm.wr_data_hi @[lsu.scala 222:11]
+    io.dccm.wr_data_lo <= dccm_ctl.io.dccm.wr_data_lo @[lsu.scala 222:11]
+    io.dccm.rd_addr_hi <= dccm_ctl.io.dccm.rd_addr_hi @[lsu.scala 222:11]
+    io.dccm.rd_addr_lo <= dccm_ctl.io.dccm.rd_addr_lo @[lsu.scala 222:11]
+    io.dccm.wr_addr_hi <= dccm_ctl.io.dccm.wr_addr_hi @[lsu.scala 222:11]
+    io.dccm.wr_addr_lo <= dccm_ctl.io.dccm.wr_addr_lo @[lsu.scala 222:11]
+    io.dccm.rden <= dccm_ctl.io.dccm.rden @[lsu.scala 222:11]
+    io.dccm.wren <= dccm_ctl.io.dccm.wren @[lsu.scala 222:11]
+    dccm_ctl.io.lsu_pic.picm_rd_data <= io.lsu_pic.picm_rd_data @[lsu.scala 223:14]
+    io.lsu_pic.picm_wr_data <= dccm_ctl.io.lsu_pic.picm_wr_data @[lsu.scala 223:14]
+    io.lsu_pic.picm_wraddr <= dccm_ctl.io.lsu_pic.picm_wraddr @[lsu.scala 223:14]
+    io.lsu_pic.picm_rdaddr <= dccm_ctl.io.lsu_pic.picm_rdaddr @[lsu.scala 223:14]
+    io.lsu_pic.picm_mken <= dccm_ctl.io.lsu_pic.picm_mken @[lsu.scala 223:14]
+    io.lsu_pic.picm_rden <= dccm_ctl.io.lsu_pic.picm_rden @[lsu.scala 223:14]
+    io.lsu_pic.picm_wren <= dccm_ctl.io.lsu_pic.picm_wren @[lsu.scala 223:14]
+    stbuf.io.ldst_dual_d <= ldst_dual_d @[lsu.scala 226:50]
+    stbuf.io.ldst_dual_m <= ldst_dual_m @[lsu.scala 227:50]
+    stbuf.io.ldst_dual_r <= ldst_dual_r @[lsu.scala 228:50]
+    stbuf.io.lsu_stbuf_c1_clk <= clkdomain.io.lsu_stbuf_c1_clk @[lsu.scala 229:54]
+    stbuf.io.lsu_free_c2_clk <= clkdomain.io.lsu_free_c2_clk @[lsu.scala 230:54]
+    stbuf.io.lsu_pkt_m.bits.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store_data_bypass_m @[lsu.scala 231:48]
+    stbuf.io.lsu_pkt_m.bits.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.bits.load_ldst_bypass_d @[lsu.scala 231:48]
+    stbuf.io.lsu_pkt_m.bits.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store_data_bypass_d @[lsu.scala 231:48]
+    stbuf.io.lsu_pkt_m.bits.dma <= lsu_lsc_ctl.io.lsu_pkt_m.bits.dma @[lsu.scala 231:48]
+    stbuf.io.lsu_pkt_m.bits.unsign <= lsu_lsc_ctl.io.lsu_pkt_m.bits.unsign @[lsu.scala 231:48]
+    stbuf.io.lsu_pkt_m.bits.store <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store @[lsu.scala 231:48]
+    stbuf.io.lsu_pkt_m.bits.load <= lsu_lsc_ctl.io.lsu_pkt_m.bits.load @[lsu.scala 231:48]
+    stbuf.io.lsu_pkt_m.bits.dword <= lsu_lsc_ctl.io.lsu_pkt_m.bits.dword @[lsu.scala 231:48]
+    stbuf.io.lsu_pkt_m.bits.word <= lsu_lsc_ctl.io.lsu_pkt_m.bits.word @[lsu.scala 231:48]
+    stbuf.io.lsu_pkt_m.bits.half <= lsu_lsc_ctl.io.lsu_pkt_m.bits.half @[lsu.scala 231:48]
+    stbuf.io.lsu_pkt_m.bits.by <= lsu_lsc_ctl.io.lsu_pkt_m.bits.by @[lsu.scala 231:48]
+    stbuf.io.lsu_pkt_m.bits.stack <= lsu_lsc_ctl.io.lsu_pkt_m.bits.stack @[lsu.scala 231:48]
+    stbuf.io.lsu_pkt_m.bits.fast_int <= lsu_lsc_ctl.io.lsu_pkt_m.bits.fast_int @[lsu.scala 231:48]
+    stbuf.io.lsu_pkt_m.valid <= lsu_lsc_ctl.io.lsu_pkt_m.valid @[lsu.scala 231:48]
+    stbuf.io.lsu_pkt_r.bits.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store_data_bypass_m @[lsu.scala 232:48]
+    stbuf.io.lsu_pkt_r.bits.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_r.bits.load_ldst_bypass_d @[lsu.scala 232:48]
+    stbuf.io.lsu_pkt_r.bits.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store_data_bypass_d @[lsu.scala 232:48]
+    stbuf.io.lsu_pkt_r.bits.dma <= lsu_lsc_ctl.io.lsu_pkt_r.bits.dma @[lsu.scala 232:48]
+    stbuf.io.lsu_pkt_r.bits.unsign <= lsu_lsc_ctl.io.lsu_pkt_r.bits.unsign @[lsu.scala 232:48]
+    stbuf.io.lsu_pkt_r.bits.store <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store @[lsu.scala 232:48]
+    stbuf.io.lsu_pkt_r.bits.load <= lsu_lsc_ctl.io.lsu_pkt_r.bits.load @[lsu.scala 232:48]
+    stbuf.io.lsu_pkt_r.bits.dword <= lsu_lsc_ctl.io.lsu_pkt_r.bits.dword @[lsu.scala 232:48]
+    stbuf.io.lsu_pkt_r.bits.word <= lsu_lsc_ctl.io.lsu_pkt_r.bits.word @[lsu.scala 232:48]
+    stbuf.io.lsu_pkt_r.bits.half <= lsu_lsc_ctl.io.lsu_pkt_r.bits.half @[lsu.scala 232:48]
+    stbuf.io.lsu_pkt_r.bits.by <= lsu_lsc_ctl.io.lsu_pkt_r.bits.by @[lsu.scala 232:48]
+    stbuf.io.lsu_pkt_r.bits.stack <= lsu_lsc_ctl.io.lsu_pkt_r.bits.stack @[lsu.scala 232:48]
+    stbuf.io.lsu_pkt_r.bits.fast_int <= lsu_lsc_ctl.io.lsu_pkt_r.bits.fast_int @[lsu.scala 232:48]
+    stbuf.io.lsu_pkt_r.valid <= lsu_lsc_ctl.io.lsu_pkt_r.valid @[lsu.scala 232:48]
+    stbuf.io.store_stbuf_reqvld_r <= store_stbuf_reqvld_r @[lsu.scala 233:48]
+    stbuf.io.lsu_commit_r <= lsu_lsc_ctl.io.lsu_commit_r @[lsu.scala 234:49]
+    stbuf.io.dec_lsu_valid_raw_d <= io.dec_lsu_valid_raw_d @[lsu.scala 235:49]
+    stbuf.io.store_data_hi_r <= dccm_ctl.io.store_data_hi_r @[lsu.scala 236:62]
+    stbuf.io.store_data_lo_r <= dccm_ctl.io.store_data_lo_r @[lsu.scala 237:62]
+    stbuf.io.store_datafn_hi_r <= dccm_ctl.io.store_datafn_hi_r @[lsu.scala 238:49]
+    stbuf.io.store_datafn_lo_r <= dccm_ctl.io.store_datafn_lo_r @[lsu.scala 239:56]
+    stbuf.io.lsu_stbuf_commit_any <= dccm_ctl.io.lsu_stbuf_commit_any @[lsu.scala 240:52]
+    stbuf.io.lsu_addr_d <= lsu_addr_d @[lsu.scala 241:64]
+    stbuf.io.lsu_addr_m <= lsu_lsc_ctl.io.lsu_addr_m @[lsu.scala 242:64]
+    stbuf.io.lsu_addr_r <= lsu_lsc_ctl.io.lsu_addr_r @[lsu.scala 243:64]
+    stbuf.io.end_addr_d <= end_addr_d @[lsu.scala 244:64]
+    stbuf.io.end_addr_m <= lsu_lsc_ctl.io.end_addr_m @[lsu.scala 245:64]
+    stbuf.io.end_addr_r <= lsu_lsc_ctl.io.end_addr_r @[lsu.scala 246:64]
+    stbuf.io.addr_in_dccm_m <= lsu_lsc_ctl.io.addr_in_dccm_m @[lsu.scala 247:49]
+    stbuf.io.addr_in_dccm_r <= lsu_lsc_ctl.io.addr_in_dccm_r @[lsu.scala 248:56]
+    stbuf.io.lsu_cmpen_m <= lsu_cmpen_m @[lsu.scala 249:54]
+    stbuf.io.scan_mode <= io.scan_mode @[lsu.scala 250:49]
+    ecc.io.clk_override <= io.clk_override @[lsu.scala 254:50]
+    ecc.io.lsu_c2_r_clk <= clkdomain.io.lsu_c2_r_clk @[lsu.scala 255:52]
+    ecc.io.lsu_pkt_m.bits.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store_data_bypass_m @[lsu.scala 256:52]
+    ecc.io.lsu_pkt_m.bits.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.bits.load_ldst_bypass_d @[lsu.scala 256:52]
+    ecc.io.lsu_pkt_m.bits.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store_data_bypass_d @[lsu.scala 256:52]
+    ecc.io.lsu_pkt_m.bits.dma <= lsu_lsc_ctl.io.lsu_pkt_m.bits.dma @[lsu.scala 256:52]
+    ecc.io.lsu_pkt_m.bits.unsign <= lsu_lsc_ctl.io.lsu_pkt_m.bits.unsign @[lsu.scala 256:52]
+    ecc.io.lsu_pkt_m.bits.store <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store @[lsu.scala 256:52]
+    ecc.io.lsu_pkt_m.bits.load <= lsu_lsc_ctl.io.lsu_pkt_m.bits.load @[lsu.scala 256:52]
+    ecc.io.lsu_pkt_m.bits.dword <= lsu_lsc_ctl.io.lsu_pkt_m.bits.dword @[lsu.scala 256:52]
+    ecc.io.lsu_pkt_m.bits.word <= lsu_lsc_ctl.io.lsu_pkt_m.bits.word @[lsu.scala 256:52]
+    ecc.io.lsu_pkt_m.bits.half <= lsu_lsc_ctl.io.lsu_pkt_m.bits.half @[lsu.scala 256:52]
+    ecc.io.lsu_pkt_m.bits.by <= lsu_lsc_ctl.io.lsu_pkt_m.bits.by @[lsu.scala 256:52]
+    ecc.io.lsu_pkt_m.bits.stack <= lsu_lsc_ctl.io.lsu_pkt_m.bits.stack @[lsu.scala 256:52]
+    ecc.io.lsu_pkt_m.bits.fast_int <= lsu_lsc_ctl.io.lsu_pkt_m.bits.fast_int @[lsu.scala 256:52]
+    ecc.io.lsu_pkt_m.valid <= lsu_lsc_ctl.io.lsu_pkt_m.valid @[lsu.scala 256:52]
+    ecc.io.lsu_pkt_r.bits.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store_data_bypass_m @[lsu.scala 257:52]
+    ecc.io.lsu_pkt_r.bits.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_r.bits.load_ldst_bypass_d @[lsu.scala 257:52]
+    ecc.io.lsu_pkt_r.bits.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store_data_bypass_d @[lsu.scala 257:52]
+    ecc.io.lsu_pkt_r.bits.dma <= lsu_lsc_ctl.io.lsu_pkt_r.bits.dma @[lsu.scala 257:52]
+    ecc.io.lsu_pkt_r.bits.unsign <= lsu_lsc_ctl.io.lsu_pkt_r.bits.unsign @[lsu.scala 257:52]
+    ecc.io.lsu_pkt_r.bits.store <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store @[lsu.scala 257:52]
+    ecc.io.lsu_pkt_r.bits.load <= lsu_lsc_ctl.io.lsu_pkt_r.bits.load @[lsu.scala 257:52]
+    ecc.io.lsu_pkt_r.bits.dword <= lsu_lsc_ctl.io.lsu_pkt_r.bits.dword @[lsu.scala 257:52]
+    ecc.io.lsu_pkt_r.bits.word <= lsu_lsc_ctl.io.lsu_pkt_r.bits.word @[lsu.scala 257:52]
+    ecc.io.lsu_pkt_r.bits.half <= lsu_lsc_ctl.io.lsu_pkt_r.bits.half @[lsu.scala 257:52]
+    ecc.io.lsu_pkt_r.bits.by <= lsu_lsc_ctl.io.lsu_pkt_r.bits.by @[lsu.scala 257:52]
+    ecc.io.lsu_pkt_r.bits.stack <= lsu_lsc_ctl.io.lsu_pkt_r.bits.stack @[lsu.scala 257:52]
+    ecc.io.lsu_pkt_r.bits.fast_int <= lsu_lsc_ctl.io.lsu_pkt_r.bits.fast_int @[lsu.scala 257:52]
+    ecc.io.lsu_pkt_r.valid <= lsu_lsc_ctl.io.lsu_pkt_r.valid @[lsu.scala 257:52]
+    ecc.io.stbuf_data_any <= stbuf.io.stbuf_data_any @[lsu.scala 258:54]
+    ecc.io.dec_tlu_core_ecc_disable <= io.dec_tlu_core_ecc_disable @[lsu.scala 259:50]
+    ecc.io.lsu_dccm_rden_r <= dccm_ctl.io.lsu_dccm_rden_r @[lsu.scala 260:56]
+    ecc.io.addr_in_dccm_r <= lsu_lsc_ctl.io.addr_in_dccm_r @[lsu.scala 261:50]
+    ecc.io.lsu_addr_r <= lsu_addr_r @[lsu.scala 262:58]
+    ecc.io.end_addr_r <= end_addr_r @[lsu.scala 263:58]
+    ecc.io.lsu_addr_m <= lsu_addr_m @[lsu.scala 264:58]
+    ecc.io.end_addr_m <= end_addr_m @[lsu.scala 265:58]
+    ecc.io.dccm_rdata_hi_r <= dccm_ctl.io.dccm_rdata_hi_r @[lsu.scala 266:54]
+    ecc.io.dccm_rdata_lo_r <= dccm_ctl.io.dccm_rdata_lo_r @[lsu.scala 267:54]
+    ecc.io.dccm_rdata_hi_m <= dccm_ctl.io.dccm_rdata_hi_m @[lsu.scala 268:54]
+    ecc.io.dccm_rdata_lo_m <= dccm_ctl.io.dccm_rdata_lo_m @[lsu.scala 269:54]
+    ecc.io.dccm_data_ecc_hi_r <= dccm_ctl.io.dccm_data_ecc_hi_r @[lsu.scala 270:50]
+    ecc.io.dccm_data_ecc_lo_r <= dccm_ctl.io.dccm_data_ecc_lo_r @[lsu.scala 271:50]
+    ecc.io.dccm_data_ecc_hi_m <= dccm_ctl.io.dccm_data_ecc_hi_m @[lsu.scala 272:50]
+    ecc.io.dccm_data_ecc_lo_m <= dccm_ctl.io.dccm_data_ecc_lo_m @[lsu.scala 273:50]
+    ecc.io.ld_single_ecc_error_r <= dccm_ctl.io.ld_single_ecc_error_r @[lsu.scala 274:50]
+    ecc.io.ld_single_ecc_error_r_ff <= dccm_ctl.io.ld_single_ecc_error_r_ff @[lsu.scala 275:50]
+    ecc.io.lsu_dccm_rden_m <= dccm_ctl.io.lsu_dccm_rden_m @[lsu.scala 276:50]
+    ecc.io.addr_in_dccm_m <= lsu_lsc_ctl.io.addr_in_dccm_m @[lsu.scala 277:50]
+    ecc.io.dma_dccm_wen <= dma_dccm_wen @[lsu.scala 278:50]
+    ecc.io.dma_dccm_wdata_lo <= dma_dccm_wdata_lo @[lsu.scala 279:50]
+    ecc.io.dma_dccm_wdata_hi <= dma_dccm_wdata_hi @[lsu.scala 280:50]
+    ecc.io.scan_mode <= io.scan_mode @[lsu.scala 281:50]
+    trigger.io.trigger_pkt_any[0].tdata2 <= io.trigger_pkt_any[0].tdata2 @[lsu.scala 285:50]
+    trigger.io.trigger_pkt_any[0].m <= io.trigger_pkt_any[0].m @[lsu.scala 285:50]
+    trigger.io.trigger_pkt_any[0].execute <= io.trigger_pkt_any[0].execute @[lsu.scala 285:50]
+    trigger.io.trigger_pkt_any[0].load <= io.trigger_pkt_any[0].load @[lsu.scala 285:50]
+    trigger.io.trigger_pkt_any[0].store <= io.trigger_pkt_any[0].store @[lsu.scala 285:50]
+    trigger.io.trigger_pkt_any[0].match_pkt <= io.trigger_pkt_any[0].match_pkt @[lsu.scala 285:50]
+    trigger.io.trigger_pkt_any[0].select <= io.trigger_pkt_any[0].select @[lsu.scala 285:50]
+    trigger.io.trigger_pkt_any[1].tdata2 <= io.trigger_pkt_any[1].tdata2 @[lsu.scala 285:50]
+    trigger.io.trigger_pkt_any[1].m <= io.trigger_pkt_any[1].m @[lsu.scala 285:50]
+    trigger.io.trigger_pkt_any[1].execute <= io.trigger_pkt_any[1].execute @[lsu.scala 285:50]
+    trigger.io.trigger_pkt_any[1].load <= io.trigger_pkt_any[1].load @[lsu.scala 285:50]
+    trigger.io.trigger_pkt_any[1].store <= io.trigger_pkt_any[1].store @[lsu.scala 285:50]
+    trigger.io.trigger_pkt_any[1].match_pkt <= io.trigger_pkt_any[1].match_pkt @[lsu.scala 285:50]
+    trigger.io.trigger_pkt_any[1].select <= io.trigger_pkt_any[1].select @[lsu.scala 285:50]
+    trigger.io.trigger_pkt_any[2].tdata2 <= io.trigger_pkt_any[2].tdata2 @[lsu.scala 285:50]
+    trigger.io.trigger_pkt_any[2].m <= io.trigger_pkt_any[2].m @[lsu.scala 285:50]
+    trigger.io.trigger_pkt_any[2].execute <= io.trigger_pkt_any[2].execute @[lsu.scala 285:50]
+    trigger.io.trigger_pkt_any[2].load <= io.trigger_pkt_any[2].load @[lsu.scala 285:50]
+    trigger.io.trigger_pkt_any[2].store <= io.trigger_pkt_any[2].store @[lsu.scala 285:50]
+    trigger.io.trigger_pkt_any[2].match_pkt <= io.trigger_pkt_any[2].match_pkt @[lsu.scala 285:50]
+    trigger.io.trigger_pkt_any[2].select <= io.trigger_pkt_any[2].select @[lsu.scala 285:50]
+    trigger.io.trigger_pkt_any[3].tdata2 <= io.trigger_pkt_any[3].tdata2 @[lsu.scala 285:50]
+    trigger.io.trigger_pkt_any[3].m <= io.trigger_pkt_any[3].m @[lsu.scala 285:50]
+    trigger.io.trigger_pkt_any[3].execute <= io.trigger_pkt_any[3].execute @[lsu.scala 285:50]
+    trigger.io.trigger_pkt_any[3].load <= io.trigger_pkt_any[3].load @[lsu.scala 285:50]
+    trigger.io.trigger_pkt_any[3].store <= io.trigger_pkt_any[3].store @[lsu.scala 285:50]
+    trigger.io.trigger_pkt_any[3].match_pkt <= io.trigger_pkt_any[3].match_pkt @[lsu.scala 285:50]
+    trigger.io.trigger_pkt_any[3].select <= io.trigger_pkt_any[3].select @[lsu.scala 285:50]
+    trigger.io.lsu_pkt_m.bits.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store_data_bypass_m @[lsu.scala 286:50]
+    trigger.io.lsu_pkt_m.bits.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.bits.load_ldst_bypass_d @[lsu.scala 286:50]
+    trigger.io.lsu_pkt_m.bits.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store_data_bypass_d @[lsu.scala 286:50]
+    trigger.io.lsu_pkt_m.bits.dma <= lsu_lsc_ctl.io.lsu_pkt_m.bits.dma @[lsu.scala 286:50]
+    trigger.io.lsu_pkt_m.bits.unsign <= lsu_lsc_ctl.io.lsu_pkt_m.bits.unsign @[lsu.scala 286:50]
+    trigger.io.lsu_pkt_m.bits.store <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store @[lsu.scala 286:50]
+    trigger.io.lsu_pkt_m.bits.load <= lsu_lsc_ctl.io.lsu_pkt_m.bits.load @[lsu.scala 286:50]
+    trigger.io.lsu_pkt_m.bits.dword <= lsu_lsc_ctl.io.lsu_pkt_m.bits.dword @[lsu.scala 286:50]
+    trigger.io.lsu_pkt_m.bits.word <= lsu_lsc_ctl.io.lsu_pkt_m.bits.word @[lsu.scala 286:50]
+    trigger.io.lsu_pkt_m.bits.half <= lsu_lsc_ctl.io.lsu_pkt_m.bits.half @[lsu.scala 286:50]
+    trigger.io.lsu_pkt_m.bits.by <= lsu_lsc_ctl.io.lsu_pkt_m.bits.by @[lsu.scala 286:50]
+    trigger.io.lsu_pkt_m.bits.stack <= lsu_lsc_ctl.io.lsu_pkt_m.bits.stack @[lsu.scala 286:50]
+    trigger.io.lsu_pkt_m.bits.fast_int <= lsu_lsc_ctl.io.lsu_pkt_m.bits.fast_int @[lsu.scala 286:50]
+    trigger.io.lsu_pkt_m.valid <= lsu_lsc_ctl.io.lsu_pkt_m.valid @[lsu.scala 286:50]
+    trigger.io.lsu_addr_m <= lsu_lsc_ctl.io.lsu_addr_m @[lsu.scala 287:50]
+    trigger.io.store_data_m <= lsu_lsc_ctl.io.store_data_m @[lsu.scala 288:50]
+    io.lsu_trigger_match_m <= trigger.io.lsu_trigger_match_m @[lsu.scala 290:50]
+    clkdomain.io.active_clk <= io.active_clk @[lsu.scala 294:50]
+    clkdomain.io.clk_override <= io.clk_override @[lsu.scala 295:50]
+    clkdomain.io.dec_tlu_force_halt <= io.dec_tlu_force_halt @[lsu.scala 296:50]
+    clkdomain.io.dma_dccm_req <= io.lsu_dma.dma_lsc_ctl.dma_dccm_req @[lsu.scala 297:50]
+    clkdomain.io.ldst_stbuf_reqvld_r <= stbuf.io.ldst_stbuf_reqvld_r @[lsu.scala 298:50]
+    clkdomain.io.stbuf_reqvld_any <= stbuf.io.stbuf_reqvld_any @[lsu.scala 299:50]
+    clkdomain.io.stbuf_reqvld_flushed_any <= stbuf.io.stbuf_reqvld_flushed_any @[lsu.scala 300:50]
+    clkdomain.io.lsu_busreq_r <= bus_intf.io.lsu_busreq_r @[lsu.scala 301:50]
+    clkdomain.io.lsu_bus_buffer_pend_any <= bus_intf.io.lsu_bus_buffer_pend_any @[lsu.scala 302:50]
+    clkdomain.io.lsu_bus_buffer_empty_any <= bus_intf.io.lsu_bus_buffer_empty_any @[lsu.scala 303:50]
+    clkdomain.io.lsu_stbuf_empty_any <= stbuf.io.lsu_stbuf_empty_any @[lsu.scala 304:50]
+    clkdomain.io.lsu_bus_clk_en <= io.lsu_bus_clk_en @[lsu.scala 305:50]
+    clkdomain.io.lsu_p.bits.store_data_bypass_m <= io.lsu_p.bits.store_data_bypass_m @[lsu.scala 306:50]
+    clkdomain.io.lsu_p.bits.load_ldst_bypass_d <= io.lsu_p.bits.load_ldst_bypass_d @[lsu.scala 306:50]
+    clkdomain.io.lsu_p.bits.store_data_bypass_d <= io.lsu_p.bits.store_data_bypass_d @[lsu.scala 306:50]
+    clkdomain.io.lsu_p.bits.dma <= io.lsu_p.bits.dma @[lsu.scala 306:50]
+    clkdomain.io.lsu_p.bits.unsign <= io.lsu_p.bits.unsign @[lsu.scala 306:50]
+    clkdomain.io.lsu_p.bits.store <= io.lsu_p.bits.store @[lsu.scala 306:50]
+    clkdomain.io.lsu_p.bits.load <= io.lsu_p.bits.load @[lsu.scala 306:50]
+    clkdomain.io.lsu_p.bits.dword <= io.lsu_p.bits.dword @[lsu.scala 306:50]
+    clkdomain.io.lsu_p.bits.word <= io.lsu_p.bits.word @[lsu.scala 306:50]
+    clkdomain.io.lsu_p.bits.half <= io.lsu_p.bits.half @[lsu.scala 306:50]
+    clkdomain.io.lsu_p.bits.by <= io.lsu_p.bits.by @[lsu.scala 306:50]
+    clkdomain.io.lsu_p.bits.stack <= io.lsu_p.bits.stack @[lsu.scala 306:50]
+    clkdomain.io.lsu_p.bits.fast_int <= io.lsu_p.bits.fast_int @[lsu.scala 306:50]
+    clkdomain.io.lsu_p.valid <= io.lsu_p.valid @[lsu.scala 306:50]
+    clkdomain.io.lsu_pkt_d.bits.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_d.bits.store_data_bypass_m @[lsu.scala 307:50]
+    clkdomain.io.lsu_pkt_d.bits.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_d.bits.load_ldst_bypass_d @[lsu.scala 307:50]
+    clkdomain.io.lsu_pkt_d.bits.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_d.bits.store_data_bypass_d @[lsu.scala 307:50]
+    clkdomain.io.lsu_pkt_d.bits.dma <= lsu_lsc_ctl.io.lsu_pkt_d.bits.dma @[lsu.scala 307:50]
+    clkdomain.io.lsu_pkt_d.bits.unsign <= lsu_lsc_ctl.io.lsu_pkt_d.bits.unsign @[lsu.scala 307:50]
+    clkdomain.io.lsu_pkt_d.bits.store <= lsu_lsc_ctl.io.lsu_pkt_d.bits.store @[lsu.scala 307:50]
+    clkdomain.io.lsu_pkt_d.bits.load <= lsu_lsc_ctl.io.lsu_pkt_d.bits.load @[lsu.scala 307:50]
+    clkdomain.io.lsu_pkt_d.bits.dword <= lsu_lsc_ctl.io.lsu_pkt_d.bits.dword @[lsu.scala 307:50]
+    clkdomain.io.lsu_pkt_d.bits.word <= lsu_lsc_ctl.io.lsu_pkt_d.bits.word @[lsu.scala 307:50]
+    clkdomain.io.lsu_pkt_d.bits.half <= lsu_lsc_ctl.io.lsu_pkt_d.bits.half @[lsu.scala 307:50]
+    clkdomain.io.lsu_pkt_d.bits.by <= lsu_lsc_ctl.io.lsu_pkt_d.bits.by @[lsu.scala 307:50]
+    clkdomain.io.lsu_pkt_d.bits.stack <= lsu_lsc_ctl.io.lsu_pkt_d.bits.stack @[lsu.scala 307:50]
+    clkdomain.io.lsu_pkt_d.bits.fast_int <= lsu_lsc_ctl.io.lsu_pkt_d.bits.fast_int @[lsu.scala 307:50]
+    clkdomain.io.lsu_pkt_d.valid <= lsu_lsc_ctl.io.lsu_pkt_d.valid @[lsu.scala 307:50]
+    clkdomain.io.lsu_pkt_m.bits.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store_data_bypass_m @[lsu.scala 308:50]
+    clkdomain.io.lsu_pkt_m.bits.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.bits.load_ldst_bypass_d @[lsu.scala 308:50]
+    clkdomain.io.lsu_pkt_m.bits.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store_data_bypass_d @[lsu.scala 308:50]
+    clkdomain.io.lsu_pkt_m.bits.dma <= lsu_lsc_ctl.io.lsu_pkt_m.bits.dma @[lsu.scala 308:50]
+    clkdomain.io.lsu_pkt_m.bits.unsign <= lsu_lsc_ctl.io.lsu_pkt_m.bits.unsign @[lsu.scala 308:50]
+    clkdomain.io.lsu_pkt_m.bits.store <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store @[lsu.scala 308:50]
+    clkdomain.io.lsu_pkt_m.bits.load <= lsu_lsc_ctl.io.lsu_pkt_m.bits.load @[lsu.scala 308:50]
+    clkdomain.io.lsu_pkt_m.bits.dword <= lsu_lsc_ctl.io.lsu_pkt_m.bits.dword @[lsu.scala 308:50]
+    clkdomain.io.lsu_pkt_m.bits.word <= lsu_lsc_ctl.io.lsu_pkt_m.bits.word @[lsu.scala 308:50]
+    clkdomain.io.lsu_pkt_m.bits.half <= lsu_lsc_ctl.io.lsu_pkt_m.bits.half @[lsu.scala 308:50]
+    clkdomain.io.lsu_pkt_m.bits.by <= lsu_lsc_ctl.io.lsu_pkt_m.bits.by @[lsu.scala 308:50]
+    clkdomain.io.lsu_pkt_m.bits.stack <= lsu_lsc_ctl.io.lsu_pkt_m.bits.stack @[lsu.scala 308:50]
+    clkdomain.io.lsu_pkt_m.bits.fast_int <= lsu_lsc_ctl.io.lsu_pkt_m.bits.fast_int @[lsu.scala 308:50]
+    clkdomain.io.lsu_pkt_m.valid <= lsu_lsc_ctl.io.lsu_pkt_m.valid @[lsu.scala 308:50]
+    clkdomain.io.lsu_pkt_r.bits.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store_data_bypass_m @[lsu.scala 309:50]
+    clkdomain.io.lsu_pkt_r.bits.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_r.bits.load_ldst_bypass_d @[lsu.scala 309:50]
+    clkdomain.io.lsu_pkt_r.bits.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store_data_bypass_d @[lsu.scala 309:50]
+    clkdomain.io.lsu_pkt_r.bits.dma <= lsu_lsc_ctl.io.lsu_pkt_r.bits.dma @[lsu.scala 309:50]
+    clkdomain.io.lsu_pkt_r.bits.unsign <= lsu_lsc_ctl.io.lsu_pkt_r.bits.unsign @[lsu.scala 309:50]
+    clkdomain.io.lsu_pkt_r.bits.store <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store @[lsu.scala 309:50]
+    clkdomain.io.lsu_pkt_r.bits.load <= lsu_lsc_ctl.io.lsu_pkt_r.bits.load @[lsu.scala 309:50]
+    clkdomain.io.lsu_pkt_r.bits.dword <= lsu_lsc_ctl.io.lsu_pkt_r.bits.dword @[lsu.scala 309:50]
+    clkdomain.io.lsu_pkt_r.bits.word <= lsu_lsc_ctl.io.lsu_pkt_r.bits.word @[lsu.scala 309:50]
+    clkdomain.io.lsu_pkt_r.bits.half <= lsu_lsc_ctl.io.lsu_pkt_r.bits.half @[lsu.scala 309:50]
+    clkdomain.io.lsu_pkt_r.bits.by <= lsu_lsc_ctl.io.lsu_pkt_r.bits.by @[lsu.scala 309:50]
+    clkdomain.io.lsu_pkt_r.bits.stack <= lsu_lsc_ctl.io.lsu_pkt_r.bits.stack @[lsu.scala 309:50]
+    clkdomain.io.lsu_pkt_r.bits.fast_int <= lsu_lsc_ctl.io.lsu_pkt_r.bits.fast_int @[lsu.scala 309:50]
+    clkdomain.io.lsu_pkt_r.valid <= lsu_lsc_ctl.io.lsu_pkt_r.valid @[lsu.scala 309:50]
+    clkdomain.io.scan_mode <= io.scan_mode @[lsu.scala 310:50]
+    bus_intf.io.scan_mode <= io.scan_mode @[lsu.scala 314:49]
+    io.lsu_dec.tlu_busbuff.lsu_imprecise_error_addr_any <= bus_intf.io.tlu_busbuff.lsu_imprecise_error_addr_any @[lsu.scala 315:26]
+    io.lsu_dec.tlu_busbuff.lsu_imprecise_error_store_any <= bus_intf.io.tlu_busbuff.lsu_imprecise_error_store_any @[lsu.scala 315:26]
+    io.lsu_dec.tlu_busbuff.lsu_imprecise_error_load_any <= bus_intf.io.tlu_busbuff.lsu_imprecise_error_load_any @[lsu.scala 315:26]
+    bus_intf.io.tlu_busbuff.dec_tlu_sideeffect_posted_disable <= io.lsu_dec.tlu_busbuff.dec_tlu_sideeffect_posted_disable @[lsu.scala 315:26]
+    bus_intf.io.tlu_busbuff.dec_tlu_wb_coalescing_disable <= io.lsu_dec.tlu_busbuff.dec_tlu_wb_coalescing_disable @[lsu.scala 315:26]
+    bus_intf.io.tlu_busbuff.dec_tlu_external_ldfwd_disable <= io.lsu_dec.tlu_busbuff.dec_tlu_external_ldfwd_disable @[lsu.scala 315:26]
+    io.lsu_dec.tlu_busbuff.lsu_pmu_bus_busy <= bus_intf.io.tlu_busbuff.lsu_pmu_bus_busy @[lsu.scala 315:26]
+    io.lsu_dec.tlu_busbuff.lsu_pmu_bus_error <= bus_intf.io.tlu_busbuff.lsu_pmu_bus_error @[lsu.scala 315:26]
+    io.lsu_dec.tlu_busbuff.lsu_pmu_bus_misaligned <= bus_intf.io.tlu_busbuff.lsu_pmu_bus_misaligned @[lsu.scala 315:26]
+    io.lsu_dec.tlu_busbuff.lsu_pmu_bus_trxn <= bus_intf.io.tlu_busbuff.lsu_pmu_bus_trxn @[lsu.scala 315:26]
+    bus_intf.io.clk_override <= io.clk_override @[lsu.scala 316:49]
+    bus_intf.io.lsu_c1_r_clk <= clkdomain.io.lsu_c1_r_clk @[lsu.scala 317:49]
+    bus_intf.io.lsu_c2_r_clk <= clkdomain.io.lsu_c2_r_clk @[lsu.scala 318:49]
+    bus_intf.io.lsu_busm_clken <= lsu_busm_clken @[lsu.scala 319:49]
+    bus_intf.io.lsu_bus_obuf_c1_clken <= lsu_bus_obuf_c1_clken @[lsu.scala 320:49]
+    bus_intf.io.lsu_bus_ibuf_c1_clk <= clkdomain.io.lsu_bus_ibuf_c1_clk @[lsu.scala 321:49]
+    bus_intf.io.lsu_bus_obuf_c1_clk <= clkdomain.io.lsu_bus_obuf_c1_clk @[lsu.scala 322:49]
+    bus_intf.io.lsu_bus_buf_c1_clk <= clkdomain.io.lsu_bus_buf_c1_clk @[lsu.scala 323:49]
+    bus_intf.io.lsu_free_c2_clk <= clkdomain.io.lsu_free_c2_clk @[lsu.scala 324:49]
+    bus_intf.io.active_clk <= io.active_clk @[lsu.scala 325:49]
+    bus_intf.io.lsu_busm_clk <= clkdomain.io.lsu_busm_clk @[lsu.scala 326:49]
+    bus_intf.io.dec_lsu_valid_raw_d <= io.dec_lsu_valid_raw_d @[lsu.scala 327:49]
+    bus_intf.io.lsu_busreq_m <= lsu_busreq_m @[lsu.scala 328:49]
+    bus_intf.io.ldst_dual_d <= ldst_dual_d @[lsu.scala 329:49]
+    bus_intf.io.ldst_dual_m <= ldst_dual_m @[lsu.scala 330:49]
+    bus_intf.io.ldst_dual_r <= ldst_dual_r @[lsu.scala 331:49]
+    node _T_71 = and(lsu_lsc_ctl.io.addr_external_m, lsu_lsc_ctl.io.lsu_pkt_m.valid) @[lsu.scala 332:104]
+    node _T_72 = bits(_T_71, 0, 0) @[Bitwise.scala 72:15]
+    node _T_73 = mux(_T_72, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
+    node _T_74 = and(lsu_addr_m, _T_73) @[lsu.scala 332:63]
+    bus_intf.io.lsu_addr_m <= _T_74 @[lsu.scala 332:49]
+    node _T_75 = bits(lsu_busreq_r, 0, 0) @[Bitwise.scala 72:15]
+    node _T_76 = mux(_T_75, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
+    node _T_77 = and(lsu_addr_r, _T_76) @[lsu.scala 333:63]
+    bus_intf.io.lsu_addr_r <= _T_77 @[lsu.scala 333:49]
+    node _T_78 = and(lsu_lsc_ctl.io.addr_external_m, lsu_lsc_ctl.io.lsu_pkt_m.valid) @[lsu.scala 334:104]
+    node _T_79 = bits(_T_78, 0, 0) @[Bitwise.scala 72:15]
+    node _T_80 = mux(_T_79, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
+    node _T_81 = and(end_addr_m, _T_80) @[lsu.scala 334:63]
+    bus_intf.io.end_addr_m <= _T_81 @[lsu.scala 334:49]
+    node _T_82 = bits(lsu_busreq_r, 0, 0) @[Bitwise.scala 72:15]
+    node _T_83 = mux(_T_82, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
+    node _T_84 = and(end_addr_r, _T_83) @[lsu.scala 335:63]
+    bus_intf.io.end_addr_r <= _T_84 @[lsu.scala 335:49]
+    node _T_85 = bits(lsu_busreq_r, 0, 0) @[Bitwise.scala 72:15]
+    node _T_86 = mux(_T_85, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
+    node _T_87 = and(dccm_ctl.io.store_data_r, _T_86) @[lsu.scala 336:77]
+    bus_intf.io.store_data_r <= _T_87 @[lsu.scala 336:49]
+    bus_intf.io.lsu_pkt_m.bits.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store_data_bypass_m @[lsu.scala 337:49]
+    bus_intf.io.lsu_pkt_m.bits.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.bits.load_ldst_bypass_d @[lsu.scala 337:49]
+    bus_intf.io.lsu_pkt_m.bits.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store_data_bypass_d @[lsu.scala 337:49]
+    bus_intf.io.lsu_pkt_m.bits.dma <= lsu_lsc_ctl.io.lsu_pkt_m.bits.dma @[lsu.scala 337:49]
+    bus_intf.io.lsu_pkt_m.bits.unsign <= lsu_lsc_ctl.io.lsu_pkt_m.bits.unsign @[lsu.scala 337:49]
+    bus_intf.io.lsu_pkt_m.bits.store <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store @[lsu.scala 337:49]
+    bus_intf.io.lsu_pkt_m.bits.load <= lsu_lsc_ctl.io.lsu_pkt_m.bits.load @[lsu.scala 337:49]
+    bus_intf.io.lsu_pkt_m.bits.dword <= lsu_lsc_ctl.io.lsu_pkt_m.bits.dword @[lsu.scala 337:49]
+    bus_intf.io.lsu_pkt_m.bits.word <= lsu_lsc_ctl.io.lsu_pkt_m.bits.word @[lsu.scala 337:49]
+    bus_intf.io.lsu_pkt_m.bits.half <= lsu_lsc_ctl.io.lsu_pkt_m.bits.half @[lsu.scala 337:49]
+    bus_intf.io.lsu_pkt_m.bits.by <= lsu_lsc_ctl.io.lsu_pkt_m.bits.by @[lsu.scala 337:49]
+    bus_intf.io.lsu_pkt_m.bits.stack <= lsu_lsc_ctl.io.lsu_pkt_m.bits.stack @[lsu.scala 337:49]
+    bus_intf.io.lsu_pkt_m.bits.fast_int <= lsu_lsc_ctl.io.lsu_pkt_m.bits.fast_int @[lsu.scala 337:49]
+    bus_intf.io.lsu_pkt_m.valid <= lsu_lsc_ctl.io.lsu_pkt_m.valid @[lsu.scala 337:49]
+    bus_intf.io.lsu_pkt_r.bits.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store_data_bypass_m @[lsu.scala 338:49]
+    bus_intf.io.lsu_pkt_r.bits.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_r.bits.load_ldst_bypass_d @[lsu.scala 338:49]
+    bus_intf.io.lsu_pkt_r.bits.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store_data_bypass_d @[lsu.scala 338:49]
+    bus_intf.io.lsu_pkt_r.bits.dma <= lsu_lsc_ctl.io.lsu_pkt_r.bits.dma @[lsu.scala 338:49]
+    bus_intf.io.lsu_pkt_r.bits.unsign <= lsu_lsc_ctl.io.lsu_pkt_r.bits.unsign @[lsu.scala 338:49]
+    bus_intf.io.lsu_pkt_r.bits.store <= lsu_lsc_ctl.io.lsu_pkt_r.bits.store @[lsu.scala 338:49]
+    bus_intf.io.lsu_pkt_r.bits.load <= lsu_lsc_ctl.io.lsu_pkt_r.bits.load @[lsu.scala 338:49]
+    bus_intf.io.lsu_pkt_r.bits.dword <= lsu_lsc_ctl.io.lsu_pkt_r.bits.dword @[lsu.scala 338:49]
+    bus_intf.io.lsu_pkt_r.bits.word <= lsu_lsc_ctl.io.lsu_pkt_r.bits.word @[lsu.scala 338:49]
+    bus_intf.io.lsu_pkt_r.bits.half <= lsu_lsc_ctl.io.lsu_pkt_r.bits.half @[lsu.scala 338:49]
+    bus_intf.io.lsu_pkt_r.bits.by <= lsu_lsc_ctl.io.lsu_pkt_r.bits.by @[lsu.scala 338:49]
+    bus_intf.io.lsu_pkt_r.bits.stack <= lsu_lsc_ctl.io.lsu_pkt_r.bits.stack @[lsu.scala 338:49]
+    bus_intf.io.lsu_pkt_r.bits.fast_int <= lsu_lsc_ctl.io.lsu_pkt_r.bits.fast_int @[lsu.scala 338:49]
+    bus_intf.io.lsu_pkt_r.valid <= lsu_lsc_ctl.io.lsu_pkt_r.valid @[lsu.scala 338:49]
+    bus_intf.io.dec_tlu_force_halt <= io.dec_tlu_force_halt @[lsu.scala 339:49]
+    bus_intf.io.lsu_commit_r <= lsu_lsc_ctl.io.lsu_commit_r @[lsu.scala 340:49]
+    bus_intf.io.is_sideeffects_m <= lsu_lsc_ctl.io.is_sideeffects_m @[lsu.scala 341:49]
+    bus_intf.io.flush_m_up <= io.dec_tlu_flush_lower_r @[lsu.scala 342:49]
+    bus_intf.io.flush_r <= io.dec_tlu_i0_kill_writeb_r @[lsu.scala 343:49]
+    io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data <= bus_intf.io.dctl_busbuff.lsu_nonblock_load_data @[lsu.scala 345:27]
+    io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_tag <= bus_intf.io.dctl_busbuff.lsu_nonblock_load_data_tag @[lsu.scala 345:27]
+    io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_error <= bus_intf.io.dctl_busbuff.lsu_nonblock_load_data_error @[lsu.scala 345:27]
+    io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_valid <= bus_intf.io.dctl_busbuff.lsu_nonblock_load_data_valid @[lsu.scala 345:27]
+    io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_tag_r <= bus_intf.io.dctl_busbuff.lsu_nonblock_load_inv_tag_r @[lsu.scala 345:27]
+    io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_r <= bus_intf.io.dctl_busbuff.lsu_nonblock_load_inv_r @[lsu.scala 345:27]
+    io.lsu_dec.dctl_busbuff.lsu_nonblock_load_tag_m <= bus_intf.io.dctl_busbuff.lsu_nonblock_load_tag_m @[lsu.scala 345:27]
+    io.lsu_dec.dctl_busbuff.lsu_nonblock_load_valid_m <= bus_intf.io.dctl_busbuff.lsu_nonblock_load_valid_m @[lsu.scala 345:27]
+    lsu_busreq_r <= bus_intf.io.lsu_busreq_r @[lsu.scala 346:16]
+    bus_intf.io.axi.r.bits.last <= io.axi.r.bits.last @[lsu.scala 347:49]
+    bus_intf.io.axi.r.bits.resp <= io.axi.r.bits.resp @[lsu.scala 347:49]
+    bus_intf.io.axi.r.bits.data <= io.axi.r.bits.data @[lsu.scala 347:49]
+    bus_intf.io.axi.r.bits.id <= io.axi.r.bits.id @[lsu.scala 347:49]
+    bus_intf.io.axi.r.valid <= io.axi.r.valid @[lsu.scala 347:49]
+    io.axi.r.ready <= bus_intf.io.axi.r.ready @[lsu.scala 347:49]
+    io.axi.ar.bits.qos <= bus_intf.io.axi.ar.bits.qos @[lsu.scala 347:49]
+    io.axi.ar.bits.prot <= bus_intf.io.axi.ar.bits.prot @[lsu.scala 347:49]
+    io.axi.ar.bits.cache <= bus_intf.io.axi.ar.bits.cache @[lsu.scala 347:49]
+    io.axi.ar.bits.lock <= bus_intf.io.axi.ar.bits.lock @[lsu.scala 347:49]
+    io.axi.ar.bits.burst <= bus_intf.io.axi.ar.bits.burst @[lsu.scala 347:49]
+    io.axi.ar.bits.size <= bus_intf.io.axi.ar.bits.size @[lsu.scala 347:49]
+    io.axi.ar.bits.len <= bus_intf.io.axi.ar.bits.len @[lsu.scala 347:49]
+    io.axi.ar.bits.region <= bus_intf.io.axi.ar.bits.region @[lsu.scala 347:49]
+    io.axi.ar.bits.addr <= bus_intf.io.axi.ar.bits.addr @[lsu.scala 347:49]
+    io.axi.ar.bits.id <= bus_intf.io.axi.ar.bits.id @[lsu.scala 347:49]
+    io.axi.ar.valid <= bus_intf.io.axi.ar.valid @[lsu.scala 347:49]
+    bus_intf.io.axi.ar.ready <= io.axi.ar.ready @[lsu.scala 347:49]
+    bus_intf.io.axi.b.bits.id <= io.axi.b.bits.id @[lsu.scala 347:49]
+    bus_intf.io.axi.b.bits.resp <= io.axi.b.bits.resp @[lsu.scala 347:49]
+    bus_intf.io.axi.b.valid <= io.axi.b.valid @[lsu.scala 347:49]
+    io.axi.b.ready <= bus_intf.io.axi.b.ready @[lsu.scala 347:49]
+    io.axi.w.bits.last <= bus_intf.io.axi.w.bits.last @[lsu.scala 347:49]
+    io.axi.w.bits.strb <= bus_intf.io.axi.w.bits.strb @[lsu.scala 347:49]
+    io.axi.w.bits.data <= bus_intf.io.axi.w.bits.data @[lsu.scala 347:49]
+    io.axi.w.valid <= bus_intf.io.axi.w.valid @[lsu.scala 347:49]
+    bus_intf.io.axi.w.ready <= io.axi.w.ready @[lsu.scala 347:49]
+    io.axi.aw.bits.qos <= bus_intf.io.axi.aw.bits.qos @[lsu.scala 347:49]
+    io.axi.aw.bits.prot <= bus_intf.io.axi.aw.bits.prot @[lsu.scala 347:49]
+    io.axi.aw.bits.cache <= bus_intf.io.axi.aw.bits.cache @[lsu.scala 347:49]
+    io.axi.aw.bits.lock <= bus_intf.io.axi.aw.bits.lock @[lsu.scala 347:49]
+    io.axi.aw.bits.burst <= bus_intf.io.axi.aw.bits.burst @[lsu.scala 347:49]
+    io.axi.aw.bits.size <= bus_intf.io.axi.aw.bits.size @[lsu.scala 347:49]
+    io.axi.aw.bits.len <= bus_intf.io.axi.aw.bits.len @[lsu.scala 347:49]
+    io.axi.aw.bits.region <= bus_intf.io.axi.aw.bits.region @[lsu.scala 347:49]
+    io.axi.aw.bits.addr <= bus_intf.io.axi.aw.bits.addr @[lsu.scala 347:49]
+    io.axi.aw.bits.id <= bus_intf.io.axi.aw.bits.id @[lsu.scala 347:49]
+    io.axi.aw.valid <= bus_intf.io.axi.aw.valid @[lsu.scala 347:49]
+    bus_intf.io.axi.aw.ready <= io.axi.aw.ready @[lsu.scala 347:49]
+    bus_intf.io.lsu_bus_clk_en <= io.lsu_bus_clk_en @[lsu.scala 348:49]
+    reg _T_88 : UInt, clkdomain.io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu.scala 350:67]
+    _T_88 <= io.lsu_dma.dma_mem_tag @[lsu.scala 350:67]
+    dma_mem_tag_m <= _T_88 @[lsu.scala 350:57]
+    reg _T_89 : UInt<1>, clkdomain.io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu.scala 351:67]
+    _T_89 <= lsu_raw_fwd_hi_m @[lsu.scala 351:67]
+    lsu_raw_fwd_hi_r <= _T_89 @[lsu.scala 351:57]
+    reg _T_90 : UInt<1>, clkdomain.io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu.scala 352:67]
+    _T_90 <= lsu_raw_fwd_lo_m @[lsu.scala 352:67]
+    lsu_raw_fwd_lo_r <= _T_90 @[lsu.scala 352:57]
     
diff --git a/lsu.v b/lsu.v
index 1cea6e1a..0ef0faa3 100644
--- a/lsu.v
+++ b/lsu.v
@@ -26,13 +26,13 @@ module lsu_addrcheck(
 `ifdef RANDOMIZE_REG_INIT
   reg [31:0] _RAND_0;
 `endif // RANDOMIZE_REG_INIT
-  wire  start_addr_in_dccm_region_d = io_start_addr_d[31:28] == 4'hf; // @[lib.scala 356:49]
-  wire  start_addr_in_dccm_d = io_start_addr_d[31:16] == 16'hf004; // @[lib.scala 361:39]
-  wire  end_addr_in_dccm_region_d = io_end_addr_d[31:28] == 4'hf; // @[lib.scala 356:49]
-  wire  end_addr_in_dccm_d = io_end_addr_d[31:16] == 16'hf004; // @[lib.scala 361:39]
+  wire  start_addr_in_dccm_region_d = io_start_addr_d[31:28] == 4'hf; // @[lib.scala 365:49]
+  wire  start_addr_in_dccm_d = io_start_addr_d[31:16] == 16'hf004; // @[lib.scala 370:39]
+  wire  end_addr_in_dccm_region_d = io_end_addr_d[31:28] == 4'hf; // @[lib.scala 365:49]
+  wire  end_addr_in_dccm_d = io_end_addr_d[31:16] == 16'hf004; // @[lib.scala 370:39]
   wire  addr_in_iccm = io_start_addr_d[31:28] == 4'he; // @[lsu_addrcheck.scala 42:45]
-  wire  start_addr_in_pic_d = io_start_addr_d[31:15] == 17'h1e018; // @[lib.scala 361:39]
-  wire  end_addr_in_pic_d = io_end_addr_d[31:15] == 17'h1e018; // @[lib.scala 361:39]
+  wire  start_addr_in_pic_d = io_start_addr_d[31:15] == 17'h1e018; // @[lib.scala 370:39]
+  wire  end_addr_in_pic_d = io_end_addr_d[31:15] == 17'h1e018; // @[lib.scala 370:39]
   wire  start_addr_dccm_or_pic = start_addr_in_dccm_region_d | start_addr_in_dccm_region_d; // @[lsu_addrcheck.scala 54:60]
   wire  _T_17 = io_rs1_region_d == 4'hf; // @[lsu_addrcheck.scala 55:55]
   wire  base_reg_dccm_or_pic = _T_17 | _T_17; // @[lsu_addrcheck.scala 55:91]
@@ -186,8 +186,7 @@ endmodule
 module rvclkhdr(
   output  io_l1clk,
   input   io_clk,
-  input   io_en,
-  input   io_scan_mode
+  input   io_en
 );
   wire  clkhdr_Q; // @[lib.scala 334:26]
   wire  clkhdr_CK; // @[lib.scala 334:26]
@@ -202,7 +201,7 @@ module rvclkhdr(
   assign io_l1clk = clkhdr_Q; // @[lib.scala 335:14]
   assign clkhdr_CK = io_clk; // @[lib.scala 336:18]
   assign clkhdr_EN = io_en; // @[lib.scala 337:18]
-  assign clkhdr_SE = io_scan_mode; // @[lib.scala 338:18]
+  assign clkhdr_SE = 1'h0; // @[lib.scala 338:18]
 endmodule
 module lsu_lsc_ctl(
   input         clock,
@@ -213,16 +212,15 @@ module lsu_lsc_ctl(
   input         io_lsu_c2_m_clk,
   input         io_lsu_c2_r_clk,
   input         io_lsu_store_c1_m_clk,
+  input  [31:0] io_lsu_ld_data_r,
   input  [31:0] io_lsu_ld_data_corr_r,
   input         io_lsu_single_ecc_error_r,
   input         io_lsu_double_ecc_error_r,
-  input  [31:0] io_lsu_ld_data_m,
-  input         io_lsu_single_ecc_error_m,
-  input         io_lsu_double_ecc_error_m,
   input         io_flush_m_up,
   input         io_flush_r,
   input         io_ldst_dual_d,
   input         io_ldst_dual_m,
+  input         io_ldst_dual_r,
   input  [31:0] io_lsu_exu_exu_lsu_rs1_d,
   input  [31:0] io_lsu_exu_exu_lsu_rs2_d,
   input         io_lsu_p_valid,
@@ -301,6 +299,7 @@ module lsu_lsc_ctl(
   output        io_lsu_pkt_m_bits_dma,
   output        io_lsu_pkt_m_bits_store_data_bypass_m,
   output        io_lsu_pkt_r_valid,
+  output        io_lsu_pkt_r_bits_fast_int,
   output        io_lsu_pkt_r_bits_by,
   output        io_lsu_pkt_r_bits_half,
   output        io_lsu_pkt_r_bits_word,
@@ -308,8 +307,7 @@ module lsu_lsc_ctl(
   output        io_lsu_pkt_r_bits_load,
   output        io_lsu_pkt_r_bits_store,
   output        io_lsu_pkt_r_bits_unsign,
-  output        io_lsu_pkt_r_bits_dma,
-  input         io_scan_mode
+  output        io_lsu_pkt_r_bits_dma
 );
 `ifdef RANDOMIZE_REG_INIT
   reg [31:0] _RAND_0;
@@ -356,226 +354,213 @@ module lsu_lsc_ctl(
   reg [31:0] _RAND_41;
   reg [31:0] _RAND_42;
   reg [31:0] _RAND_43;
+  reg [31:0] _RAND_44;
 `endif // RANDOMIZE_REG_INIT
-  wire  addrcheck_reset; // @[lsu_lsc_ctl.scala 118:25]
-  wire  addrcheck_io_lsu_c2_m_clk; // @[lsu_lsc_ctl.scala 118:25]
-  wire [31:0] addrcheck_io_start_addr_d; // @[lsu_lsc_ctl.scala 118:25]
-  wire [31:0] addrcheck_io_end_addr_d; // @[lsu_lsc_ctl.scala 118:25]
-  wire  addrcheck_io_lsu_pkt_d_valid; // @[lsu_lsc_ctl.scala 118:25]
-  wire  addrcheck_io_lsu_pkt_d_bits_fast_int; // @[lsu_lsc_ctl.scala 118:25]
-  wire  addrcheck_io_lsu_pkt_d_bits_by; // @[lsu_lsc_ctl.scala 118:25]
-  wire  addrcheck_io_lsu_pkt_d_bits_half; // @[lsu_lsc_ctl.scala 118:25]
-  wire  addrcheck_io_lsu_pkt_d_bits_word; // @[lsu_lsc_ctl.scala 118:25]
-  wire  addrcheck_io_lsu_pkt_d_bits_load; // @[lsu_lsc_ctl.scala 118:25]
-  wire  addrcheck_io_lsu_pkt_d_bits_store; // @[lsu_lsc_ctl.scala 118:25]
-  wire  addrcheck_io_lsu_pkt_d_bits_dma; // @[lsu_lsc_ctl.scala 118:25]
-  wire [31:0] addrcheck_io_dec_tlu_mrac_ff; // @[lsu_lsc_ctl.scala 118:25]
-  wire [3:0] addrcheck_io_rs1_region_d; // @[lsu_lsc_ctl.scala 118:25]
-  wire  addrcheck_io_is_sideeffects_m; // @[lsu_lsc_ctl.scala 118:25]
-  wire  addrcheck_io_addr_in_dccm_d; // @[lsu_lsc_ctl.scala 118:25]
-  wire  addrcheck_io_addr_in_pic_d; // @[lsu_lsc_ctl.scala 118:25]
-  wire  addrcheck_io_addr_external_d; // @[lsu_lsc_ctl.scala 118:25]
-  wire  addrcheck_io_access_fault_d; // @[lsu_lsc_ctl.scala 118:25]
-  wire  addrcheck_io_misaligned_fault_d; // @[lsu_lsc_ctl.scala 118:25]
-  wire [3:0] addrcheck_io_exc_mscause_d; // @[lsu_lsc_ctl.scala 118:25]
-  wire  addrcheck_io_fir_dccm_access_error_d; // @[lsu_lsc_ctl.scala 118:25]
-  wire  addrcheck_io_fir_nondccm_access_error_d; // @[lsu_lsc_ctl.scala 118:25]
-  wire  rvclkhdr_io_l1clk; // @[lib.scala 378:23]
-  wire  rvclkhdr_io_clk; // @[lib.scala 378:23]
-  wire  rvclkhdr_io_en; // @[lib.scala 378:23]
-  wire  rvclkhdr_io_scan_mode; // @[lib.scala 378:23]
-  wire  rvclkhdr_1_io_l1clk; // @[lib.scala 368:23]
-  wire  rvclkhdr_1_io_clk; // @[lib.scala 368:23]
-  wire  rvclkhdr_1_io_en; // @[lib.scala 368:23]
-  wire  rvclkhdr_1_io_scan_mode; // @[lib.scala 368:23]
-  wire  rvclkhdr_2_io_l1clk; // @[lib.scala 368:23]
-  wire  rvclkhdr_2_io_clk; // @[lib.scala 368:23]
-  wire  rvclkhdr_2_io_en; // @[lib.scala 368:23]
-  wire  rvclkhdr_2_io_scan_mode; // @[lib.scala 368:23]
-  wire  rvclkhdr_3_io_l1clk; // @[lib.scala 368:23]
-  wire  rvclkhdr_3_io_clk; // @[lib.scala 368:23]
-  wire  rvclkhdr_3_io_en; // @[lib.scala 368:23]
-  wire  rvclkhdr_3_io_scan_mode; // @[lib.scala 368:23]
-  wire [31:0] lsu_rs1_d = io_dec_lsu_valid_raw_d ? io_lsu_exu_exu_lsu_rs1_d : io_dma_lsc_ctl_dma_mem_addr; // @[lsu_lsc_ctl.scala 100:28]
-  wire [11:0] _T_3 = io_dec_lsu_valid_raw_d ? 12'hfff : 12'h0; // @[Bitwise.scala 72:12]
-  wire [11:0] lsu_offset_d = io_dec_lsu_offset_d & _T_3; // @[lsu_lsc_ctl.scala 101:51]
-  wire [31:0] rs1_d = io_lsu_pkt_d_bits_load_ldst_bypass_d ? io_lsu_result_m : lsu_rs1_d; // @[lsu_lsc_ctl.scala 104:28]
-  wire [12:0] _T_6 = {1'h0,rs1_d[11:0]}; // @[Cat.scala 29:58]
-  wire [12:0] _T_8 = {1'h0,lsu_offset_d}; // @[Cat.scala 29:58]
-  wire [12:0] _T_10 = _T_6 + _T_8; // @[lib.scala 92:39]
-  wire  _T_13 = lsu_offset_d[11] ^ _T_10[12]; // @[lib.scala 93:46]
-  wire  _T_14 = ~_T_13; // @[lib.scala 93:33]
-  wire [19:0] _T_16 = _T_14 ? 20'hfffff : 20'h0; // @[Bitwise.scala 72:12]
-  wire [19:0] _T_18 = _T_16 & rs1_d[31:12]; // @[lib.scala 93:58]
-  wire  _T_20 = ~lsu_offset_d[11]; // @[lib.scala 94:18]
-  wire  _T_22 = _T_20 & _T_10[12]; // @[lib.scala 94:30]
-  wire [19:0] _T_24 = _T_22 ? 20'hfffff : 20'h0; // @[Bitwise.scala 72:12]
-  wire [19:0] _T_27 = rs1_d[31:12] + 20'h1; // @[lib.scala 94:54]
-  wire [19:0] _T_28 = _T_24 & _T_27; // @[lib.scala 94:41]
-  wire [19:0] _T_29 = _T_18 | _T_28; // @[lib.scala 93:72]
-  wire  _T_32 = ~_T_10[12]; // @[lib.scala 95:31]
-  wire  _T_33 = lsu_offset_d[11] & _T_32; // @[lib.scala 95:29]
-  wire [19:0] _T_35 = _T_33 ? 20'hfffff : 20'h0; // @[Bitwise.scala 72:12]
-  wire [19:0] _T_38 = rs1_d[31:12] - 20'h1; // @[lib.scala 95:54]
-  wire [19:0] _T_39 = _T_35 & _T_38; // @[lib.scala 95:41]
-  wire [19:0] _T_40 = _T_29 | _T_39; // @[lib.scala 94:61]
-  wire [2:0] _T_43 = io_lsu_pkt_d_bits_half ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
-  wire [2:0] _T_44 = _T_43 & 3'h1; // @[lsu_lsc_ctl.scala 109:58]
-  wire [2:0] _T_46 = io_lsu_pkt_d_bits_word ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
-  wire [2:0] _T_47 = _T_46 & 3'h3; // @[lsu_lsc_ctl.scala 110:40]
-  wire [2:0] _T_48 = _T_44 | _T_47; // @[lsu_lsc_ctl.scala 109:70]
-  wire [2:0] _T_50 = io_lsu_pkt_d_bits_dword ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
-  wire [2:0] addr_offset_d = _T_48 | _T_50; // @[lsu_lsc_ctl.scala 110:52]
-  wire [12:0] _T_54 = {lsu_offset_d[11],lsu_offset_d}; // @[Cat.scala 29:58]
-  wire [11:0] _T_57 = {9'h0,addr_offset_d}; // @[Cat.scala 29:58]
-  wire [12:0] _GEN_0 = {{1'd0}, _T_57}; // @[lsu_lsc_ctl.scala 113:60]
-  wire [12:0] end_addr_offset_d = _T_54 + _GEN_0; // @[lsu_lsc_ctl.scala 113:60]
-  wire [18:0] _T_62 = end_addr_offset_d[12] ? 19'h7ffff : 19'h0; // @[Bitwise.scala 72:12]
-  wire [31:0] _T_64 = {_T_62,end_addr_offset_d}; // @[Cat.scala 29:58]
-  reg  access_fault_m; // @[lsu_lsc_ctl.scala 149:75]
-  reg  misaligned_fault_m; // @[lsu_lsc_ctl.scala 150:75]
-  reg [3:0] exc_mscause_m; // @[lsu_lsc_ctl.scala 151:75]
-  reg  fir_dccm_access_error_m; // @[lsu_lsc_ctl.scala 152:75]
-  reg  fir_nondccm_access_error_m; // @[lsu_lsc_ctl.scala 153:75]
-  wire  _T_69 = access_fault_m | misaligned_fault_m; // @[lsu_lsc_ctl.scala 155:34]
-  wire  _T_70 = ~io_lsu_double_ecc_error_r; // @[lsu_lsc_ctl.scala 156:64]
-  wire  _T_71 = io_lsu_single_ecc_error_r & _T_70; // @[lsu_lsc_ctl.scala 156:62]
-  wire  _T_72 = io_lsu_commit_r | io_lsu_pkt_r_bits_dma; // @[lsu_lsc_ctl.scala 156:111]
-  wire  _T_73 = _T_71 & _T_72; // @[lsu_lsc_ctl.scala 156:92]
-  wire  _T_76 = _T_69 | io_lsu_double_ecc_error_m; // @[lsu_lsc_ctl.scala 178:67]
-  wire  _T_77 = _T_76 & io_lsu_pkt_m_valid; // @[lsu_lsc_ctl.scala 178:96]
-  wire  _T_78 = ~io_lsu_pkt_m_bits_dma; // @[lsu_lsc_ctl.scala 178:119]
-  wire  _T_79 = _T_77 & _T_78; // @[lsu_lsc_ctl.scala 178:117]
-  wire  _T_80 = ~io_lsu_pkt_m_bits_fast_int; // @[lsu_lsc_ctl.scala 178:144]
-  wire  _T_81 = _T_79 & _T_80; // @[lsu_lsc_ctl.scala 178:142]
-  wire  _T_82 = ~io_flush_m_up; // @[lsu_lsc_ctl.scala 178:174]
-  wire  lsu_error_pkt_m_valid = _T_81 & _T_82; // @[lsu_lsc_ctl.scala 178:172]
-  wire  _T_84 = ~lsu_error_pkt_m_valid; // @[lsu_lsc_ctl.scala 179:75]
-  wire  _T_85 = io_lsu_single_ecc_error_m & _T_84; // @[lsu_lsc_ctl.scala 179:73]
-  wire  lsu_error_pkt_m_bits_single_ecc_error = _T_85 & _T_78; // @[lsu_lsc_ctl.scala 179:99]
-  wire  lsu_error_pkt_m_bits_exc_type = ~misaligned_fault_m; // @[lsu_lsc_ctl.scala 181:46]
-  wire  _T_90 = io_lsu_double_ecc_error_m & lsu_error_pkt_m_bits_exc_type; // @[lsu_lsc_ctl.scala 182:78]
-  wire  _T_91 = ~access_fault_m; // @[lsu_lsc_ctl.scala 182:102]
-  wire  _T_92 = _T_90 & _T_91; // @[lsu_lsc_ctl.scala 182:100]
-  wire  _T_99 = io_lsu_pkt_m_bits_fast_int & io_lsu_double_ecc_error_m; // @[lsu_lsc_ctl.scala 184:166]
-  wire  _T_104 = lsu_error_pkt_m_valid | lsu_error_pkt_m_bits_single_ecc_error; // @[lsu_lsc_ctl.scala 185:73]
-  reg  _T_109_bits_inst_type; // @[lib.scala 384:16]
-  reg  _T_109_bits_exc_type; // @[lib.scala 384:16]
-  reg [3:0] _T_109_bits_mscause; // @[lib.scala 384:16]
-  reg [31:0] _T_109_bits_addr; // @[lib.scala 384:16]
-  reg  _T_110; // @[lsu_lsc_ctl.scala 186:83]
-  reg  _T_111; // @[lsu_lsc_ctl.scala 187:67]
-  reg [1:0] _T_112; // @[lsu_lsc_ctl.scala 188:48]
+  wire  addrcheck_reset; // @[lsu_lsc_ctl.scala 117:25]
+  wire  addrcheck_io_lsu_c2_m_clk; // @[lsu_lsc_ctl.scala 117:25]
+  wire [31:0] addrcheck_io_start_addr_d; // @[lsu_lsc_ctl.scala 117:25]
+  wire [31:0] addrcheck_io_end_addr_d; // @[lsu_lsc_ctl.scala 117:25]
+  wire  addrcheck_io_lsu_pkt_d_valid; // @[lsu_lsc_ctl.scala 117:25]
+  wire  addrcheck_io_lsu_pkt_d_bits_fast_int; // @[lsu_lsc_ctl.scala 117:25]
+  wire  addrcheck_io_lsu_pkt_d_bits_by; // @[lsu_lsc_ctl.scala 117:25]
+  wire  addrcheck_io_lsu_pkt_d_bits_half; // @[lsu_lsc_ctl.scala 117:25]
+  wire  addrcheck_io_lsu_pkt_d_bits_word; // @[lsu_lsc_ctl.scala 117:25]
+  wire  addrcheck_io_lsu_pkt_d_bits_load; // @[lsu_lsc_ctl.scala 117:25]
+  wire  addrcheck_io_lsu_pkt_d_bits_store; // @[lsu_lsc_ctl.scala 117:25]
+  wire  addrcheck_io_lsu_pkt_d_bits_dma; // @[lsu_lsc_ctl.scala 117:25]
+  wire [31:0] addrcheck_io_dec_tlu_mrac_ff; // @[lsu_lsc_ctl.scala 117:25]
+  wire [3:0] addrcheck_io_rs1_region_d; // @[lsu_lsc_ctl.scala 117:25]
+  wire  addrcheck_io_is_sideeffects_m; // @[lsu_lsc_ctl.scala 117:25]
+  wire  addrcheck_io_addr_in_dccm_d; // @[lsu_lsc_ctl.scala 117:25]
+  wire  addrcheck_io_addr_in_pic_d; // @[lsu_lsc_ctl.scala 117:25]
+  wire  addrcheck_io_addr_external_d; // @[lsu_lsc_ctl.scala 117:25]
+  wire  addrcheck_io_access_fault_d; // @[lsu_lsc_ctl.scala 117:25]
+  wire  addrcheck_io_misaligned_fault_d; // @[lsu_lsc_ctl.scala 117:25]
+  wire [3:0] addrcheck_io_exc_mscause_d; // @[lsu_lsc_ctl.scala 117:25]
+  wire  addrcheck_io_fir_dccm_access_error_d; // @[lsu_lsc_ctl.scala 117:25]
+  wire  addrcheck_io_fir_nondccm_access_error_d; // @[lsu_lsc_ctl.scala 117:25]
+  wire  rvclkhdr_io_l1clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_io_clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_io_en; // @[lib.scala 390:23]
+  wire  rvclkhdr_1_io_l1clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_1_io_clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_1_io_en; // @[lib.scala 390:23]
+  wire  rvclkhdr_2_io_l1clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_2_io_clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_2_io_en; // @[lib.scala 390:23]
+  wire [31:0] lsu_rs1_d = io_dec_lsu_valid_raw_d ? io_lsu_exu_exu_lsu_rs1_d : io_dma_lsc_ctl_dma_mem_addr; // @[lsu_lsc_ctl.scala 99:28]
+  wire [11:0] _T_4 = io_dec_lsu_valid_raw_d ? 12'hfff : 12'h0; // @[Bitwise.scala 72:12]
+  wire [11:0] lsu_offset_d = io_dec_lsu_offset_d & _T_4; // @[lsu_lsc_ctl.scala 100:51]
+  wire [31:0] rs1_d = io_lsu_pkt_d_bits_load_ldst_bypass_d ? io_lsu_result_m : lsu_rs1_d; // @[lsu_lsc_ctl.scala 103:28]
+  wire [12:0] _T_7 = {1'h0,rs1_d[11:0]}; // @[Cat.scala 29:58]
+  wire [12:0] _T_9 = {1'h0,lsu_offset_d}; // @[Cat.scala 29:58]
+  wire [12:0] _T_11 = _T_7 + _T_9; // @[lib.scala 92:39]
+  wire  _T_14 = lsu_offset_d[11] ^ _T_11[12]; // @[lib.scala 93:46]
+  wire  _T_15 = ~_T_14; // @[lib.scala 93:33]
+  wire [19:0] _T_17 = _T_15 ? 20'hfffff : 20'h0; // @[Bitwise.scala 72:12]
+  wire [19:0] _T_19 = _T_17 & rs1_d[31:12]; // @[lib.scala 93:58]
+  wire  _T_21 = ~lsu_offset_d[11]; // @[lib.scala 94:18]
+  wire  _T_23 = _T_21 & _T_11[12]; // @[lib.scala 94:30]
+  wire [19:0] _T_25 = _T_23 ? 20'hfffff : 20'h0; // @[Bitwise.scala 72:12]
+  wire [19:0] _T_28 = rs1_d[31:12] + 20'h1; // @[lib.scala 94:54]
+  wire [19:0] _T_29 = _T_25 & _T_28; // @[lib.scala 94:41]
+  wire [19:0] _T_30 = _T_19 | _T_29; // @[lib.scala 93:72]
+  wire  _T_33 = ~_T_11[12]; // @[lib.scala 95:31]
+  wire  _T_34 = lsu_offset_d[11] & _T_33; // @[lib.scala 95:29]
+  wire [19:0] _T_36 = _T_34 ? 20'hfffff : 20'h0; // @[Bitwise.scala 72:12]
+  wire [19:0] _T_39 = rs1_d[31:12] - 20'h1; // @[lib.scala 95:54]
+  wire [19:0] _T_40 = _T_36 & _T_39; // @[lib.scala 95:41]
+  wire [19:0] _T_41 = _T_30 | _T_40; // @[lib.scala 94:61]
+  wire [2:0] _T_44 = io_lsu_pkt_d_bits_half ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
+  wire [2:0] _T_45 = _T_44 & 3'h1; // @[lsu_lsc_ctl.scala 108:58]
+  wire [2:0] _T_47 = io_lsu_pkt_d_bits_word ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
+  wire [2:0] _T_48 = _T_47 & 3'h3; // @[lsu_lsc_ctl.scala 109:40]
+  wire [2:0] _T_49 = _T_45 | _T_48; // @[lsu_lsc_ctl.scala 108:70]
+  wire [2:0] _T_51 = io_lsu_pkt_d_bits_dword ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
+  wire [2:0] addr_offset_d = _T_49 | _T_51; // @[lsu_lsc_ctl.scala 109:52]
+  wire [12:0] _T_55 = {lsu_offset_d[11],lsu_offset_d}; // @[Cat.scala 29:58]
+  wire [11:0] _T_58 = {9'h0,addr_offset_d}; // @[Cat.scala 29:58]
+  wire [12:0] _GEN_3 = {{1'd0}, _T_58}; // @[lsu_lsc_ctl.scala 112:60]
+  wire [12:0] end_addr_offset_d = _T_55 + _GEN_3; // @[lsu_lsc_ctl.scala 112:60]
+  wire [18:0] _T_63 = end_addr_offset_d[12] ? 19'h7ffff : 19'h0; // @[Bitwise.scala 72:12]
+  wire [31:0] _T_65 = {_T_63,end_addr_offset_d}; // @[Cat.scala 29:58]
+  reg  access_fault_m; // @[lsu_lsc_ctl.scala 148:75]
+  reg  misaligned_fault_m; // @[lsu_lsc_ctl.scala 149:75]
+  reg [3:0] exc_mscause_m; // @[lsu_lsc_ctl.scala 150:75]
+  reg  fir_dccm_access_error_m; // @[lsu_lsc_ctl.scala 151:75]
+  reg  fir_nondccm_access_error_m; // @[lsu_lsc_ctl.scala 152:75]
+  wire  _T_71 = ~io_lsu_double_ecc_error_r; // @[lsu_lsc_ctl.scala 155:64]
+  wire  _T_72 = io_lsu_single_ecc_error_r & _T_71; // @[lsu_lsc_ctl.scala 155:62]
+  wire  _T_73 = io_lsu_commit_r | io_lsu_pkt_r_bits_dma; // @[lsu_lsc_ctl.scala 155:111]
+  wire  _T_74 = _T_72 & _T_73; // @[lsu_lsc_ctl.scala 155:92]
+  reg  access_fault_r; // @[lsu_lsc_ctl.scala 167:71]
+  reg  misaligned_fault_r; // @[lsu_lsc_ctl.scala 171:71]
+  wire  _T_76 = access_fault_r | misaligned_fault_r; // @[lsu_lsc_ctl.scala 159:49]
+  wire  _T_77 = _T_76 | io_lsu_double_ecc_error_r; // @[lsu_lsc_ctl.scala 159:70]
+  wire  _T_78 = _T_77 & io_lsu_pkt_r_valid; // @[lsu_lsc_ctl.scala 159:99]
+  wire  _T_79 = ~io_lsu_pkt_r_bits_dma; // @[lsu_lsc_ctl.scala 159:122]
+  wire  _T_80 = _T_78 & _T_79; // @[lsu_lsc_ctl.scala 159:120]
+  wire  _T_81 = ~io_lsu_pkt_r_bits_fast_int; // @[lsu_lsc_ctl.scala 159:147]
+  wire  _T_83 = ~io_lsu_error_pkt_r_valid; // @[lsu_lsc_ctl.scala 160:77]
+  wire  _T_84 = io_lsu_single_ecc_error_r & _T_83; // @[lsu_lsc_ctl.scala 160:75]
+  wire  _T_87 = ~misaligned_fault_r; // @[lsu_lsc_ctl.scala 162:42]
+  wire  _T_89 = io_lsu_double_ecc_error_r & _T_87; // @[lsu_lsc_ctl.scala 163:73]
+  wire  _T_90 = ~access_fault_r; // @[lsu_lsc_ctl.scala 163:97]
+  wire  _T_91 = _T_89 & _T_90; // @[lsu_lsc_ctl.scala 163:95]
+  reg [3:0] exc_mscause_r; // @[lsu_lsc_ctl.scala 168:71]
+  reg  fir_nondccm_access_error_r; // @[lsu_lsc_ctl.scala 170:71]
+  reg  fir_dccm_access_error_r; // @[lsu_lsc_ctl.scala 169:71]
+  wire  _T_98 = io_lsu_pkt_r_bits_fast_int & io_lsu_double_ecc_error_r; // @[lsu_lsc_ctl.scala 165:162]
+  wire [1:0] _T_100 = _T_98 ? 2'h1 : 2'h0; // @[lsu_lsc_ctl.scala 165:133]
+  wire [1:0] _T_101 = fir_dccm_access_error_r ? 2'h2 : _T_100; // @[lsu_lsc_ctl.scala 165:88]
   wire  dma_pkt_d_bits_load = ~io_dma_lsc_ctl_dma_mem_write; // @[lsu_lsc_ctl.scala 195:30]
   wire  dma_pkt_d_bits_by = io_dma_lsc_ctl_dma_mem_sz == 3'h0; // @[lsu_lsc_ctl.scala 196:62]
   wire  dma_pkt_d_bits_half = io_dma_lsc_ctl_dma_mem_sz == 3'h1; // @[lsu_lsc_ctl.scala 197:62]
   wire  dma_pkt_d_bits_word = io_dma_lsc_ctl_dma_mem_sz == 3'h2; // @[lsu_lsc_ctl.scala 198:62]
   wire  dma_pkt_d_bits_dword = io_dma_lsc_ctl_dma_mem_sz == 3'h3; // @[lsu_lsc_ctl.scala 199:62]
-  wire  _T_124 = ~io_lsu_p_bits_fast_int; // @[lsu_lsc_ctl.scala 212:64]
-  wire  _T_125 = io_flush_m_up & _T_124; // @[lsu_lsc_ctl.scala 212:61]
-  wire  _T_126 = ~_T_125; // @[lsu_lsc_ctl.scala 212:45]
-  wire  _T_127 = io_lsu_p_valid & _T_126; // @[lsu_lsc_ctl.scala 212:43]
-  wire  _T_129 = ~io_lsu_pkt_d_bits_dma; // @[lsu_lsc_ctl.scala 213:68]
-  wire  _T_130 = io_flush_m_up & _T_129; // @[lsu_lsc_ctl.scala 213:65]
-  wire  _T_131 = ~_T_130; // @[lsu_lsc_ctl.scala 213:49]
-  wire  _T_134 = io_flush_m_up & _T_78; // @[lsu_lsc_ctl.scala 214:65]
-  wire  _T_135 = ~_T_134; // @[lsu_lsc_ctl.scala 214:49]
-  reg  _T_138_bits_fast_int; // @[lsu_lsc_ctl.scala 216:65]
-  reg  _T_138_bits_by; // @[lsu_lsc_ctl.scala 216:65]
-  reg  _T_138_bits_half; // @[lsu_lsc_ctl.scala 216:65]
-  reg  _T_138_bits_word; // @[lsu_lsc_ctl.scala 216:65]
-  reg  _T_138_bits_dword; // @[lsu_lsc_ctl.scala 216:65]
-  reg  _T_138_bits_load; // @[lsu_lsc_ctl.scala 216:65]
-  reg  _T_138_bits_store; // @[lsu_lsc_ctl.scala 216:65]
-  reg  _T_138_bits_unsign; // @[lsu_lsc_ctl.scala 216:65]
-  reg  _T_138_bits_dma; // @[lsu_lsc_ctl.scala 216:65]
-  reg  _T_138_bits_store_data_bypass_m; // @[lsu_lsc_ctl.scala 216:65]
-  reg  _T_140_bits_by; // @[lsu_lsc_ctl.scala 217:65]
-  reg  _T_140_bits_half; // @[lsu_lsc_ctl.scala 217:65]
-  reg  _T_140_bits_word; // @[lsu_lsc_ctl.scala 217:65]
-  reg  _T_140_bits_dword; // @[lsu_lsc_ctl.scala 217:65]
-  reg  _T_140_bits_load; // @[lsu_lsc_ctl.scala 217:65]
-  reg  _T_140_bits_store; // @[lsu_lsc_ctl.scala 217:65]
-  reg  _T_140_bits_unsign; // @[lsu_lsc_ctl.scala 217:65]
-  reg  _T_140_bits_dma; // @[lsu_lsc_ctl.scala 217:65]
-  reg  _T_141; // @[lsu_lsc_ctl.scala 218:65]
-  reg  _T_142; // @[lsu_lsc_ctl.scala 219:65]
-  wire [5:0] _T_145 = {io_dma_lsc_ctl_dma_mem_addr[2:0],3'h0}; // @[Cat.scala 29:58]
-  wire [63:0] dma_mem_wdata_shifted = io_dma_lsc_ctl_dma_mem_wdata >> _T_145; // @[lsu_lsc_ctl.scala 221:66]
+  wire  _T_119 = ~io_lsu_p_bits_fast_int; // @[lsu_lsc_ctl.scala 212:64]
+  wire  _T_120 = io_flush_m_up & _T_119; // @[lsu_lsc_ctl.scala 212:61]
+  wire  _T_121 = ~_T_120; // @[lsu_lsc_ctl.scala 212:45]
+  wire  _T_122 = io_lsu_p_valid & _T_121; // @[lsu_lsc_ctl.scala 212:43]
+  wire  _T_124 = ~io_lsu_pkt_d_bits_dma; // @[lsu_lsc_ctl.scala 213:68]
+  wire  _T_125 = io_flush_m_up & _T_124; // @[lsu_lsc_ctl.scala 213:65]
+  wire  _T_126 = ~_T_125; // @[lsu_lsc_ctl.scala 213:49]
+  wire  _T_128 = ~io_lsu_pkt_m_bits_dma; // @[lsu_lsc_ctl.scala 214:68]
+  wire  _T_129 = io_flush_m_up & _T_128; // @[lsu_lsc_ctl.scala 214:65]
+  wire  _T_130 = ~_T_129; // @[lsu_lsc_ctl.scala 214:49]
+  reg  _T_133_bits_fast_int; // @[lsu_lsc_ctl.scala 216:65]
+  reg  _T_133_bits_by; // @[lsu_lsc_ctl.scala 216:65]
+  reg  _T_133_bits_half; // @[lsu_lsc_ctl.scala 216:65]
+  reg  _T_133_bits_word; // @[lsu_lsc_ctl.scala 216:65]
+  reg  _T_133_bits_dword; // @[lsu_lsc_ctl.scala 216:65]
+  reg  _T_133_bits_load; // @[lsu_lsc_ctl.scala 216:65]
+  reg  _T_133_bits_store; // @[lsu_lsc_ctl.scala 216:65]
+  reg  _T_133_bits_unsign; // @[lsu_lsc_ctl.scala 216:65]
+  reg  _T_133_bits_dma; // @[lsu_lsc_ctl.scala 216:65]
+  reg  _T_133_bits_store_data_bypass_m; // @[lsu_lsc_ctl.scala 216:65]
+  reg  _T_135_bits_fast_int; // @[lsu_lsc_ctl.scala 217:65]
+  reg  _T_135_bits_by; // @[lsu_lsc_ctl.scala 217:65]
+  reg  _T_135_bits_half; // @[lsu_lsc_ctl.scala 217:65]
+  reg  _T_135_bits_word; // @[lsu_lsc_ctl.scala 217:65]
+  reg  _T_135_bits_dword; // @[lsu_lsc_ctl.scala 217:65]
+  reg  _T_135_bits_load; // @[lsu_lsc_ctl.scala 217:65]
+  reg  _T_135_bits_store; // @[lsu_lsc_ctl.scala 217:65]
+  reg  _T_135_bits_unsign; // @[lsu_lsc_ctl.scala 217:65]
+  reg  _T_135_bits_dma; // @[lsu_lsc_ctl.scala 217:65]
+  reg  _T_136; // @[lsu_lsc_ctl.scala 218:65]
+  reg  _T_137; // @[lsu_lsc_ctl.scala 219:65]
+  wire [5:0] _T_140 = {io_dma_lsc_ctl_dma_mem_addr[2:0],3'h0}; // @[Cat.scala 29:58]
+  wire [63:0] dma_mem_wdata_shifted = io_dma_lsc_ctl_dma_mem_wdata >> _T_140; // @[lsu_lsc_ctl.scala 221:66]
   reg [31:0] store_data_pre_m; // @[lsu_lsc_ctl.scala 225:72]
-  reg [31:0] _T_152; // @[lsu_lsc_ctl.scala 226:62]
-  reg [31:0] _T_153; // @[lsu_lsc_ctl.scala 227:62]
-  wire  _T_167 = io_lsu_pkt_d_valid & io_ldst_dual_d; // @[lsu_lsc_ctl.scala 232:69]
-  wire  _T_173 = io_lsu_pkt_m_valid & io_ldst_dual_m; // @[lsu_lsc_ctl.scala 233:69]
-  reg [31:0] _T_178; // @[lsu_lsc_ctl.scala 236:62]
-  reg [31:0] _T_179; // @[lsu_lsc_ctl.scala 237:62]
-  reg  _T_180; // @[lsu_lsc_ctl.scala 238:62]
-  reg  _T_181; // @[lsu_lsc_ctl.scala 239:62]
-  reg  _T_182; // @[lsu_lsc_ctl.scala 240:62]
-  reg  _T_183; // @[lsu_lsc_ctl.scala 241:62]
-  reg  _T_184; // @[lsu_lsc_ctl.scala 242:62]
-  reg  addr_external_r; // @[lsu_lsc_ctl.scala 243:66]
-  reg [31:0] bus_read_data_r; // @[lib.scala 374:16]
-  wire  _T_189 = io_lsu_pkt_r_bits_store | io_lsu_pkt_r_bits_load; // @[lsu_lsc_ctl.scala 251:68]
-  wire  _T_190 = io_lsu_pkt_r_valid & _T_189; // @[lsu_lsc_ctl.scala 251:41]
-  wire  _T_191 = ~io_flush_r; // @[lsu_lsc_ctl.scala 251:96]
-  wire  _T_192 = _T_190 & _T_191; // @[lsu_lsc_ctl.scala 251:94]
-  wire  _T_193 = ~io_lsu_pkt_r_bits_dma; // @[lsu_lsc_ctl.scala 251:110]
-  wire  _T_196 = ~io_addr_in_pic_m; // @[lsu_lsc_ctl.scala 252:69]
-  wire [31:0] _T_198 = _T_196 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
-  wire [31:0] _T_199 = io_picm_mask_data_m | _T_198; // @[lsu_lsc_ctl.scala 252:59]
-  wire [31:0] _T_201 = io_lsu_pkt_m_bits_store_data_bypass_m ? io_lsu_result_m : store_data_pre_m; // @[lsu_lsc_ctl.scala 252:94]
-  wire [31:0] lsu_ld_datafn_m = io_addr_external_m ? io_bus_read_data_m : io_lsu_ld_data_m; // @[lsu_lsc_ctl.scala 273:33]
-  wire [31:0] lsu_ld_datafn_corr_r = addr_external_r ? bus_read_data_r : io_lsu_ld_data_corr_r; // @[lsu_lsc_ctl.scala 274:33]
-  wire  _T_207 = io_lsu_pkt_m_bits_unsign & io_lsu_pkt_m_bits_by; // @[lsu_lsc_ctl.scala 275:66]
-  wire [31:0] _T_209 = _T_207 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
-  wire [31:0] _T_211 = {24'h0,lsu_ld_datafn_m[7:0]}; // @[Cat.scala 29:58]
-  wire [31:0] _T_212 = _T_209 & _T_211; // @[lsu_lsc_ctl.scala 275:94]
-  wire  _T_213 = io_lsu_pkt_m_bits_unsign & io_lsu_pkt_m_bits_half; // @[lsu_lsc_ctl.scala 276:43]
+  reg [31:0] _T_147; // @[lsu_lsc_ctl.scala 226:62]
+  reg [31:0] _T_148; // @[lsu_lsc_ctl.scala 227:62]
+  reg [28:0] end_addr_pre_m; // @[Reg.scala 27:20]
+  wire [28:0] _T_151 = io_ldst_dual_m ? end_addr_pre_m : io_lsu_addr_m[31:3]; // @[lsu_lsc_ctl.scala 228:27]
+  reg [2:0] _T_153; // @[lsu_lsc_ctl.scala 228:114]
+  reg [28:0] end_addr_pre_r; // @[Reg.scala 27:20]
+  wire [28:0] _T_157 = io_ldst_dual_r ? end_addr_pre_r : io_lsu_addr_r[31:3]; // @[lsu_lsc_ctl.scala 229:27]
+  reg [2:0] _T_159; // @[lsu_lsc_ctl.scala 229:114]
+  wire  _T_162 = io_lsu_pkt_d_valid & io_ldst_dual_d; // @[lsu_lsc_ctl.scala 230:69]
+  wire  _T_163 = _T_162 | io_clk_override; // @[lsu_lsc_ctl.scala 230:87]
+  wire  _T_168 = io_lsu_pkt_m_valid & io_ldst_dual_m; // @[lsu_lsc_ctl.scala 231:69]
+  wire  _T_169 = _T_168 | io_clk_override; // @[lsu_lsc_ctl.scala 231:87]
+  reg  _T_173; // @[lsu_lsc_ctl.scala 232:62]
+  reg  _T_174; // @[lsu_lsc_ctl.scala 233:62]
+  reg  _T_175; // @[lsu_lsc_ctl.scala 234:62]
+  reg  _T_176; // @[lsu_lsc_ctl.scala 235:62]
+  reg  _T_177; // @[lsu_lsc_ctl.scala 236:62]
+  reg  addr_external_r; // @[lsu_lsc_ctl.scala 237:66]
+  wire  _T_178 = io_addr_external_m | io_clk_override; // @[lsu_lsc_ctl.scala 238:77]
+  reg [31:0] bus_read_data_r; // @[Reg.scala 27:20]
+  wire  _T_181 = io_lsu_pkt_r_bits_store | io_lsu_pkt_r_bits_load; // @[lsu_lsc_ctl.scala 245:68]
+  wire  _T_182 = io_lsu_pkt_r_valid & _T_181; // @[lsu_lsc_ctl.scala 245:41]
+  wire  _T_183 = ~io_flush_r; // @[lsu_lsc_ctl.scala 245:96]
+  wire  _T_184 = _T_182 & _T_183; // @[lsu_lsc_ctl.scala 245:94]
+  wire  _T_188 = ~io_addr_in_pic_m; // @[lsu_lsc_ctl.scala 246:69]
+  wire [31:0] _T_190 = _T_188 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
+  wire [31:0] _T_191 = io_picm_mask_data_m | _T_190; // @[lsu_lsc_ctl.scala 246:59]
+  wire [31:0] _T_193 = io_lsu_pkt_m_bits_store_data_bypass_m ? io_lsu_result_m : store_data_pre_m; // @[lsu_lsc_ctl.scala 246:94]
+  wire [31:0] lsu_ld_datafn_r = addr_external_r ? bus_read_data_r : io_lsu_ld_data_r; // @[lsu_lsc_ctl.scala 250:33]
+  wire [31:0] lsu_ld_datafn_corr_r = addr_external_r ? bus_read_data_r : io_lsu_ld_data_corr_r; // @[lsu_lsc_ctl.scala 251:33]
+  wire  _T_199 = io_lsu_pkt_r_bits_unsign & io_lsu_pkt_r_bits_by; // @[lsu_lsc_ctl.scala 253:66]
+  wire [31:0] _T_201 = _T_199 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
+  wire [31:0] _T_203 = {24'h0,lsu_ld_datafn_r[7:0]}; // @[Cat.scala 29:58]
+  wire [31:0] _T_204 = _T_201 & _T_203; // @[lsu_lsc_ctl.scala 253:94]
+  wire  _T_205 = io_lsu_pkt_r_bits_unsign & io_lsu_pkt_r_bits_half; // @[lsu_lsc_ctl.scala 254:43]
+  wire [31:0] _T_207 = _T_205 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
+  wire [31:0] _T_209 = {16'h0,lsu_ld_datafn_r[15:0]}; // @[Cat.scala 29:58]
+  wire [31:0] _T_210 = _T_207 & _T_209; // @[lsu_lsc_ctl.scala 254:71]
+  wire [31:0] _T_211 = _T_204 | _T_210; // @[lsu_lsc_ctl.scala 253:133]
+  wire  _T_212 = ~io_lsu_pkt_r_bits_unsign; // @[lsu_lsc_ctl.scala 255:17]
+  wire  _T_213 = _T_212 & io_lsu_pkt_r_bits_by; // @[lsu_lsc_ctl.scala 255:43]
   wire [31:0] _T_215 = _T_213 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
-  wire [31:0] _T_217 = {16'h0,lsu_ld_datafn_m[15:0]}; // @[Cat.scala 29:58]
-  wire [31:0] _T_218 = _T_215 & _T_217; // @[lsu_lsc_ctl.scala 276:71]
-  wire [31:0] _T_219 = _T_212 | _T_218; // @[lsu_lsc_ctl.scala 275:133]
-  wire  _T_220 = ~io_lsu_pkt_m_bits_unsign; // @[lsu_lsc_ctl.scala 277:17]
-  wire  _T_221 = _T_220 & io_lsu_pkt_m_bits_by; // @[lsu_lsc_ctl.scala 277:43]
-  wire [31:0] _T_223 = _T_221 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
-  wire [23:0] _T_226 = lsu_ld_datafn_m[7] ? 24'hffffff : 24'h0; // @[Bitwise.scala 72:12]
-  wire [31:0] _T_228 = {_T_226,lsu_ld_datafn_m[7:0]}; // @[Cat.scala 29:58]
-  wire [31:0] _T_229 = _T_223 & _T_228; // @[lsu_lsc_ctl.scala 277:71]
-  wire [31:0] _T_230 = _T_219 | _T_229; // @[lsu_lsc_ctl.scala 276:114]
-  wire  _T_232 = _T_220 & io_lsu_pkt_m_bits_half; // @[lsu_lsc_ctl.scala 278:43]
-  wire [31:0] _T_234 = _T_232 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
-  wire [15:0] _T_237 = lsu_ld_datafn_m[15] ? 16'hffff : 16'h0; // @[Bitwise.scala 72:12]
-  wire [31:0] _T_239 = {_T_237,lsu_ld_datafn_m[15:0]}; // @[Cat.scala 29:58]
-  wire [31:0] _T_240 = _T_234 & _T_239; // @[lsu_lsc_ctl.scala 278:71]
-  wire [31:0] _T_241 = _T_230 | _T_240; // @[lsu_lsc_ctl.scala 277:134]
-  wire [31:0] _T_243 = io_lsu_pkt_m_bits_word ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
-  wire [31:0] _T_245 = _T_243 & lsu_ld_datafn_m; // @[lsu_lsc_ctl.scala 279:43]
-  wire  _T_247 = io_lsu_pkt_r_bits_unsign & io_lsu_pkt_r_bits_by; // @[lsu_lsc_ctl.scala 280:66]
-  wire [31:0] _T_249 = _T_247 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
-  wire [31:0] _T_251 = {24'h0,lsu_ld_datafn_corr_r[7:0]}; // @[Cat.scala 29:58]
-  wire [31:0] _T_252 = _T_249 & _T_251; // @[lsu_lsc_ctl.scala 280:94]
-  wire  _T_253 = io_lsu_pkt_r_bits_unsign & io_lsu_pkt_r_bits_half; // @[lsu_lsc_ctl.scala 281:43]
-  wire [31:0] _T_255 = _T_253 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
-  wire [31:0] _T_257 = {16'h0,lsu_ld_datafn_corr_r[15:0]}; // @[Cat.scala 29:58]
-  wire [31:0] _T_258 = _T_255 & _T_257; // @[lsu_lsc_ctl.scala 281:71]
-  wire [31:0] _T_259 = _T_252 | _T_258; // @[lsu_lsc_ctl.scala 280:138]
-  wire  _T_260 = ~io_lsu_pkt_r_bits_unsign; // @[lsu_lsc_ctl.scala 282:17]
-  wire  _T_261 = _T_260 & io_lsu_pkt_r_bits_by; // @[lsu_lsc_ctl.scala 282:43]
-  wire [31:0] _T_263 = _T_261 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
-  wire [23:0] _T_266 = lsu_ld_datafn_corr_r[7] ? 24'hffffff : 24'h0; // @[Bitwise.scala 72:12]
-  wire [31:0] _T_268 = {_T_266,lsu_ld_datafn_corr_r[7:0]}; // @[Cat.scala 29:58]
-  wire [31:0] _T_269 = _T_263 & _T_268; // @[lsu_lsc_ctl.scala 282:71]
-  wire [31:0] _T_270 = _T_259 | _T_269; // @[lsu_lsc_ctl.scala 281:119]
-  wire  _T_272 = _T_260 & io_lsu_pkt_r_bits_half; // @[lsu_lsc_ctl.scala 283:43]
-  wire [31:0] _T_274 = _T_272 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
-  wire [15:0] _T_277 = lsu_ld_datafn_corr_r[15] ? 16'hffff : 16'h0; // @[Bitwise.scala 72:12]
-  wire [31:0] _T_279 = {_T_277,lsu_ld_datafn_corr_r[15:0]}; // @[Cat.scala 29:58]
-  wire [31:0] _T_280 = _T_274 & _T_279; // @[lsu_lsc_ctl.scala 283:71]
-  wire [31:0] _T_281 = _T_270 | _T_280; // @[lsu_lsc_ctl.scala 282:144]
-  wire [31:0] _T_283 = io_lsu_pkt_r_bits_word ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
-  wire [31:0] _T_285 = _T_283 & lsu_ld_datafn_corr_r; // @[lsu_lsc_ctl.scala 284:43]
-  lsu_addrcheck addrcheck ( // @[lsu_lsc_ctl.scala 118:25]
+  wire [23:0] _T_218 = lsu_ld_datafn_r[7] ? 24'hffffff : 24'h0; // @[Bitwise.scala 72:12]
+  wire [31:0] _T_220 = {_T_218,lsu_ld_datafn_r[7:0]}; // @[Cat.scala 29:58]
+  wire [31:0] _T_221 = _T_215 & _T_220; // @[lsu_lsc_ctl.scala 255:71]
+  wire [31:0] _T_222 = _T_211 | _T_221; // @[lsu_lsc_ctl.scala 254:114]
+  wire  _T_224 = _T_212 & io_lsu_pkt_r_bits_half; // @[lsu_lsc_ctl.scala 256:43]
+  wire [31:0] _T_226 = _T_224 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
+  wire [15:0] _T_229 = lsu_ld_datafn_r[15] ? 16'hffff : 16'h0; // @[Bitwise.scala 72:12]
+  wire [31:0] _T_231 = {_T_229,lsu_ld_datafn_r[15:0]}; // @[Cat.scala 29:58]
+  wire [31:0] _T_232 = _T_226 & _T_231; // @[lsu_lsc_ctl.scala 256:71]
+  wire [31:0] _T_233 = _T_222 | _T_232; // @[lsu_lsc_ctl.scala 255:134]
+  wire [31:0] _T_235 = io_lsu_pkt_r_bits_word ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
+  wire [31:0] _T_237 = _T_235 & lsu_ld_datafn_r; // @[lsu_lsc_ctl.scala 257:43]
+  wire [31:0] _T_243 = {24'h0,lsu_ld_datafn_corr_r[7:0]}; // @[Cat.scala 29:58]
+  wire [31:0] _T_244 = _T_201 & _T_243; // @[lsu_lsc_ctl.scala 259:94]
+  wire [31:0] _T_249 = {16'h0,lsu_ld_datafn_corr_r[15:0]}; // @[Cat.scala 29:58]
+  wire [31:0] _T_250 = _T_207 & _T_249; // @[lsu_lsc_ctl.scala 260:71]
+  wire [31:0] _T_251 = _T_244 | _T_250; // @[lsu_lsc_ctl.scala 259:138]
+  wire [23:0] _T_258 = lsu_ld_datafn_corr_r[7] ? 24'hffffff : 24'h0; // @[Bitwise.scala 72:12]
+  wire [31:0] _T_260 = {_T_258,lsu_ld_datafn_corr_r[7:0]}; // @[Cat.scala 29:58]
+  wire [31:0] _T_261 = _T_215 & _T_260; // @[lsu_lsc_ctl.scala 261:71]
+  wire [31:0] _T_262 = _T_251 | _T_261; // @[lsu_lsc_ctl.scala 260:119]
+  wire [15:0] _T_269 = lsu_ld_datafn_corr_r[15] ? 16'hffff : 16'h0; // @[Bitwise.scala 72:12]
+  wire [31:0] _T_271 = {_T_269,lsu_ld_datafn_corr_r[15:0]}; // @[Cat.scala 29:58]
+  wire [31:0] _T_272 = _T_226 & _T_271; // @[lsu_lsc_ctl.scala 262:71]
+  wire [31:0] _T_273 = _T_262 | _T_272; // @[lsu_lsc_ctl.scala 261:144]
+  wire [31:0] _T_277 = _T_235 & lsu_ld_datafn_corr_r; // @[lsu_lsc_ctl.scala 263:43]
+  lsu_addrcheck addrcheck ( // @[lsu_lsc_ctl.scala 117:25]
     .reset(addrcheck_reset),
     .io_lsu_c2_m_clk(addrcheck_io_lsu_c2_m_clk),
     .io_start_addr_d(addrcheck_io_start_addr_d),
@@ -600,59 +585,50 @@ module lsu_lsc_ctl(
     .io_fir_dccm_access_error_d(addrcheck_io_fir_dccm_access_error_d),
     .io_fir_nondccm_access_error_d(addrcheck_io_fir_nondccm_access_error_d)
   );
-  rvclkhdr rvclkhdr ( // @[lib.scala 378:23]
+  rvclkhdr rvclkhdr ( // @[lib.scala 390:23]
     .io_l1clk(rvclkhdr_io_l1clk),
     .io_clk(rvclkhdr_io_clk),
-    .io_en(rvclkhdr_io_en),
-    .io_scan_mode(rvclkhdr_io_scan_mode)
+    .io_en(rvclkhdr_io_en)
   );
-  rvclkhdr rvclkhdr_1 ( // @[lib.scala 368:23]
+  rvclkhdr rvclkhdr_1 ( // @[lib.scala 390:23]
     .io_l1clk(rvclkhdr_1_io_l1clk),
     .io_clk(rvclkhdr_1_io_clk),
-    .io_en(rvclkhdr_1_io_en),
-    .io_scan_mode(rvclkhdr_1_io_scan_mode)
+    .io_en(rvclkhdr_1_io_en)
   );
-  rvclkhdr rvclkhdr_2 ( // @[lib.scala 368:23]
+  rvclkhdr rvclkhdr_2 ( // @[lib.scala 390:23]
     .io_l1clk(rvclkhdr_2_io_l1clk),
     .io_clk(rvclkhdr_2_io_clk),
-    .io_en(rvclkhdr_2_io_en),
-    .io_scan_mode(rvclkhdr_2_io_scan_mode)
+    .io_en(rvclkhdr_2_io_en)
   );
-  rvclkhdr rvclkhdr_3 ( // @[lib.scala 368:23]
-    .io_l1clk(rvclkhdr_3_io_l1clk),
-    .io_clk(rvclkhdr_3_io_clk),
-    .io_en(rvclkhdr_3_io_en),
-    .io_scan_mode(rvclkhdr_3_io_scan_mode)
-  );
-  assign io_lsu_result_m = _T_241 | _T_245; // @[lsu_lsc_ctl.scala 275:27]
-  assign io_lsu_result_corr_r = _T_281 | _T_285; // @[lsu_lsc_ctl.scala 280:27]
-  assign io_lsu_addr_d = {_T_40,_T_10[11:0]}; // @[lsu_lsc_ctl.scala 249:28]
-  assign io_lsu_addr_m = _T_152; // @[lsu_lsc_ctl.scala 226:24]
-  assign io_lsu_addr_r = _T_153; // @[lsu_lsc_ctl.scala 227:24]
-  assign io_end_addr_d = rs1_d + _T_64; // @[lsu_lsc_ctl.scala 115:24]
-  assign io_end_addr_m = _T_178; // @[lsu_lsc_ctl.scala 229:17 lsu_lsc_ctl.scala 236:24]
-  assign io_end_addr_r = _T_179; // @[lsu_lsc_ctl.scala 230:17 lsu_lsc_ctl.scala 237:24]
-  assign io_store_data_m = _T_199 & _T_201; // @[lsu_lsc_ctl.scala 252:29]
-  assign io_lsu_exc_m = access_fault_m | misaligned_fault_m; // @[lsu_lsc_ctl.scala 155:16]
-  assign io_is_sideeffects_m = addrcheck_io_is_sideeffects_m; // @[lsu_lsc_ctl.scala 128:42]
-  assign io_lsu_commit_r = _T_192 & _T_193; // @[lsu_lsc_ctl.scala 251:19]
-  assign io_lsu_single_ecc_error_incr = _T_73 & io_lsu_pkt_r_valid; // @[lsu_lsc_ctl.scala 156:32]
-  assign io_lsu_error_pkt_r_valid = _T_111; // @[lsu_lsc_ctl.scala 185:24 lsu_lsc_ctl.scala 187:30]
-  assign io_lsu_error_pkt_r_bits_single_ecc_error = _T_110; // @[lsu_lsc_ctl.scala 185:24 lsu_lsc_ctl.scala 186:46]
-  assign io_lsu_error_pkt_r_bits_inst_type = _T_109_bits_inst_type; // @[lsu_lsc_ctl.scala 185:24]
-  assign io_lsu_error_pkt_r_bits_exc_type = _T_109_bits_exc_type; // @[lsu_lsc_ctl.scala 185:24]
-  assign io_lsu_error_pkt_r_bits_mscause = _T_109_bits_mscause; // @[lsu_lsc_ctl.scala 185:24]
-  assign io_lsu_error_pkt_r_bits_addr = _T_109_bits_addr; // @[lsu_lsc_ctl.scala 185:24]
-  assign io_lsu_fir_addr = io_lsu_ld_data_corr_r[31:1]; // @[lsu_lsc_ctl.scala 247:28]
-  assign io_lsu_fir_error = _T_112; // @[lsu_lsc_ctl.scala 188:38]
-  assign io_addr_in_dccm_d = addrcheck_io_addr_in_dccm_d; // @[lsu_lsc_ctl.scala 129:42]
-  assign io_addr_in_dccm_m = _T_180; // @[lsu_lsc_ctl.scala 238:24]
-  assign io_addr_in_dccm_r = _T_181; // @[lsu_lsc_ctl.scala 239:24]
-  assign io_addr_in_pic_d = addrcheck_io_addr_in_pic_d; // @[lsu_lsc_ctl.scala 130:42]
-  assign io_addr_in_pic_m = _T_182; // @[lsu_lsc_ctl.scala 240:24]
-  assign io_addr_in_pic_r = _T_183; // @[lsu_lsc_ctl.scala 241:24]
-  assign io_addr_external_m = _T_184; // @[lsu_lsc_ctl.scala 242:24]
-  assign io_lsu_pkt_d_valid = _T_127 | io_dma_lsc_ctl_dma_dccm_req; // @[lsu_lsc_ctl.scala 208:20 lsu_lsc_ctl.scala 212:24]
+  assign io_lsu_result_m = _T_233 | _T_237; // @[lsu_lsc_ctl.scala 253:27]
+  assign io_lsu_result_corr_r = _T_273 | _T_277; // @[lsu_lsc_ctl.scala 259:27]
+  assign io_lsu_addr_d = {_T_41,_T_11[11:0]}; // @[lsu_lsc_ctl.scala 243:28]
+  assign io_lsu_addr_m = _T_147; // @[lsu_lsc_ctl.scala 226:24]
+  assign io_lsu_addr_r = _T_148; // @[lsu_lsc_ctl.scala 227:24]
+  assign io_end_addr_d = rs1_d + _T_65; // @[lsu_lsc_ctl.scala 114:24]
+  assign io_end_addr_m = {_T_151,_T_153}; // @[lsu_lsc_ctl.scala 228:17]
+  assign io_end_addr_r = {_T_157,_T_159}; // @[lsu_lsc_ctl.scala 229:17]
+  assign io_store_data_m = _T_191 & _T_193; // @[lsu_lsc_ctl.scala 246:29]
+  assign io_lsu_exc_m = access_fault_m | misaligned_fault_m; // @[lsu_lsc_ctl.scala 154:16]
+  assign io_is_sideeffects_m = addrcheck_io_is_sideeffects_m; // @[lsu_lsc_ctl.scala 127:42]
+  assign io_lsu_commit_r = _T_184 & _T_79; // @[lsu_lsc_ctl.scala 245:19]
+  assign io_lsu_single_ecc_error_incr = _T_74 & io_lsu_pkt_r_valid; // @[lsu_lsc_ctl.scala 155:32]
+  assign io_lsu_error_pkt_r_valid = _T_80 & _T_81; // @[lsu_lsc_ctl.scala 159:30]
+  assign io_lsu_error_pkt_r_bits_single_ecc_error = _T_84 & _T_79; // @[lsu_lsc_ctl.scala 160:46]
+  assign io_lsu_error_pkt_r_bits_inst_type = io_lsu_pkt_r_bits_store; // @[lsu_lsc_ctl.scala 161:39]
+  assign io_lsu_error_pkt_r_bits_exc_type = ~misaligned_fault_r; // @[lsu_lsc_ctl.scala 162:39]
+  assign io_lsu_error_pkt_r_bits_mscause = _T_91 ? 4'h1 : exc_mscause_r; // @[lsu_lsc_ctl.scala 163:39]
+  assign io_lsu_error_pkt_r_bits_addr = io_lsu_addr_r; // @[lsu_lsc_ctl.scala 164:39]
+  assign io_lsu_fir_addr = io_lsu_ld_data_corr_r[31:1]; // @[lsu_lsc_ctl.scala 241:28]
+  assign io_lsu_fir_error = fir_nondccm_access_error_r ? 2'h3 : _T_101; // @[lsu_lsc_ctl.scala 165:34]
+  assign io_addr_in_dccm_d = addrcheck_io_addr_in_dccm_d; // @[lsu_lsc_ctl.scala 128:42]
+  assign io_addr_in_dccm_m = _T_173; // @[lsu_lsc_ctl.scala 232:24]
+  assign io_addr_in_dccm_r = _T_174; // @[lsu_lsc_ctl.scala 233:24]
+  assign io_addr_in_pic_d = addrcheck_io_addr_in_pic_d; // @[lsu_lsc_ctl.scala 129:42]
+  assign io_addr_in_pic_m = _T_175; // @[lsu_lsc_ctl.scala 234:24]
+  assign io_addr_in_pic_r = _T_176; // @[lsu_lsc_ctl.scala 235:24]
+  assign io_addr_external_m = _T_177; // @[lsu_lsc_ctl.scala 236:24]
+  assign io_lsu_pkt_d_valid = _T_122 | io_dma_lsc_ctl_dma_dccm_req; // @[lsu_lsc_ctl.scala 208:20 lsu_lsc_ctl.scala 212:24]
   assign io_lsu_pkt_d_bits_fast_int = io_dec_lsu_valid_raw_d & io_lsu_p_bits_fast_int; // @[lsu_lsc_ctl.scala 208:20]
   assign io_lsu_pkt_d_bits_by = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_by : dma_pkt_d_bits_by; // @[lsu_lsc_ctl.scala 208:20]
   assign io_lsu_pkt_d_bits_half = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_half : dma_pkt_d_bits_half; // @[lsu_lsc_ctl.scala 208:20]
@@ -665,52 +641,47 @@ module lsu_lsc_ctl(
   assign io_lsu_pkt_d_bits_store_data_bypass_d = io_dec_lsu_valid_raw_d & io_lsu_p_bits_store_data_bypass_d; // @[lsu_lsc_ctl.scala 208:20]
   assign io_lsu_pkt_d_bits_load_ldst_bypass_d = io_dec_lsu_valid_raw_d & io_lsu_p_bits_load_ldst_bypass_d; // @[lsu_lsc_ctl.scala 208:20]
   assign io_lsu_pkt_d_bits_store_data_bypass_m = io_dec_lsu_valid_raw_d & io_lsu_p_bits_store_data_bypass_m; // @[lsu_lsc_ctl.scala 208:20]
-  assign io_lsu_pkt_m_valid = _T_141; // @[lsu_lsc_ctl.scala 216:28 lsu_lsc_ctl.scala 218:28]
-  assign io_lsu_pkt_m_bits_fast_int = _T_138_bits_fast_int; // @[lsu_lsc_ctl.scala 216:28]
-  assign io_lsu_pkt_m_bits_by = _T_138_bits_by; // @[lsu_lsc_ctl.scala 216:28]
-  assign io_lsu_pkt_m_bits_half = _T_138_bits_half; // @[lsu_lsc_ctl.scala 216:28]
-  assign io_lsu_pkt_m_bits_word = _T_138_bits_word; // @[lsu_lsc_ctl.scala 216:28]
-  assign io_lsu_pkt_m_bits_dword = _T_138_bits_dword; // @[lsu_lsc_ctl.scala 216:28]
-  assign io_lsu_pkt_m_bits_load = _T_138_bits_load; // @[lsu_lsc_ctl.scala 216:28]
-  assign io_lsu_pkt_m_bits_store = _T_138_bits_store; // @[lsu_lsc_ctl.scala 216:28]
-  assign io_lsu_pkt_m_bits_unsign = _T_138_bits_unsign; // @[lsu_lsc_ctl.scala 216:28]
-  assign io_lsu_pkt_m_bits_dma = _T_138_bits_dma; // @[lsu_lsc_ctl.scala 216:28]
-  assign io_lsu_pkt_m_bits_store_data_bypass_m = _T_138_bits_store_data_bypass_m; // @[lsu_lsc_ctl.scala 216:28]
-  assign io_lsu_pkt_r_valid = _T_142; // @[lsu_lsc_ctl.scala 217:28 lsu_lsc_ctl.scala 219:28]
-  assign io_lsu_pkt_r_bits_by = _T_140_bits_by; // @[lsu_lsc_ctl.scala 217:28]
-  assign io_lsu_pkt_r_bits_half = _T_140_bits_half; // @[lsu_lsc_ctl.scala 217:28]
-  assign io_lsu_pkt_r_bits_word = _T_140_bits_word; // @[lsu_lsc_ctl.scala 217:28]
-  assign io_lsu_pkt_r_bits_dword = _T_140_bits_dword; // @[lsu_lsc_ctl.scala 217:28]
-  assign io_lsu_pkt_r_bits_load = _T_140_bits_load; // @[lsu_lsc_ctl.scala 217:28]
-  assign io_lsu_pkt_r_bits_store = _T_140_bits_store; // @[lsu_lsc_ctl.scala 217:28]
-  assign io_lsu_pkt_r_bits_unsign = _T_140_bits_unsign; // @[lsu_lsc_ctl.scala 217:28]
-  assign io_lsu_pkt_r_bits_dma = _T_140_bits_dma; // @[lsu_lsc_ctl.scala 217:28]
+  assign io_lsu_pkt_m_valid = _T_136; // @[lsu_lsc_ctl.scala 216:28 lsu_lsc_ctl.scala 218:28]
+  assign io_lsu_pkt_m_bits_fast_int = _T_133_bits_fast_int; // @[lsu_lsc_ctl.scala 216:28]
+  assign io_lsu_pkt_m_bits_by = _T_133_bits_by; // @[lsu_lsc_ctl.scala 216:28]
+  assign io_lsu_pkt_m_bits_half = _T_133_bits_half; // @[lsu_lsc_ctl.scala 216:28]
+  assign io_lsu_pkt_m_bits_word = _T_133_bits_word; // @[lsu_lsc_ctl.scala 216:28]
+  assign io_lsu_pkt_m_bits_dword = _T_133_bits_dword; // @[lsu_lsc_ctl.scala 216:28]
+  assign io_lsu_pkt_m_bits_load = _T_133_bits_load; // @[lsu_lsc_ctl.scala 216:28]
+  assign io_lsu_pkt_m_bits_store = _T_133_bits_store; // @[lsu_lsc_ctl.scala 216:28]
+  assign io_lsu_pkt_m_bits_unsign = _T_133_bits_unsign; // @[lsu_lsc_ctl.scala 216:28]
+  assign io_lsu_pkt_m_bits_dma = _T_133_bits_dma; // @[lsu_lsc_ctl.scala 216:28]
+  assign io_lsu_pkt_m_bits_store_data_bypass_m = _T_133_bits_store_data_bypass_m; // @[lsu_lsc_ctl.scala 216:28]
+  assign io_lsu_pkt_r_valid = _T_137; // @[lsu_lsc_ctl.scala 217:28 lsu_lsc_ctl.scala 219:28]
+  assign io_lsu_pkt_r_bits_fast_int = _T_135_bits_fast_int; // @[lsu_lsc_ctl.scala 217:28]
+  assign io_lsu_pkt_r_bits_by = _T_135_bits_by; // @[lsu_lsc_ctl.scala 217:28]
+  assign io_lsu_pkt_r_bits_half = _T_135_bits_half; // @[lsu_lsc_ctl.scala 217:28]
+  assign io_lsu_pkt_r_bits_word = _T_135_bits_word; // @[lsu_lsc_ctl.scala 217:28]
+  assign io_lsu_pkt_r_bits_dword = _T_135_bits_dword; // @[lsu_lsc_ctl.scala 217:28]
+  assign io_lsu_pkt_r_bits_load = _T_135_bits_load; // @[lsu_lsc_ctl.scala 217:28]
+  assign io_lsu_pkt_r_bits_store = _T_135_bits_store; // @[lsu_lsc_ctl.scala 217:28]
+  assign io_lsu_pkt_r_bits_unsign = _T_135_bits_unsign; // @[lsu_lsc_ctl.scala 217:28]
+  assign io_lsu_pkt_r_bits_dma = _T_135_bits_dma; // @[lsu_lsc_ctl.scala 217:28]
   assign addrcheck_reset = reset;
-  assign addrcheck_io_lsu_c2_m_clk = io_lsu_c2_m_clk; // @[lsu_lsc_ctl.scala 120:42]
-  assign addrcheck_io_start_addr_d = {_T_40,_T_10[11:0]}; // @[lsu_lsc_ctl.scala 122:42]
-  assign addrcheck_io_end_addr_d = rs1_d + _T_64; // @[lsu_lsc_ctl.scala 123:42]
-  assign addrcheck_io_lsu_pkt_d_valid = io_lsu_pkt_d_valid; // @[lsu_lsc_ctl.scala 124:42]
-  assign addrcheck_io_lsu_pkt_d_bits_fast_int = io_lsu_pkt_d_bits_fast_int; // @[lsu_lsc_ctl.scala 124:42]
-  assign addrcheck_io_lsu_pkt_d_bits_by = io_lsu_pkt_d_bits_by; // @[lsu_lsc_ctl.scala 124:42]
-  assign addrcheck_io_lsu_pkt_d_bits_half = io_lsu_pkt_d_bits_half; // @[lsu_lsc_ctl.scala 124:42]
-  assign addrcheck_io_lsu_pkt_d_bits_word = io_lsu_pkt_d_bits_word; // @[lsu_lsc_ctl.scala 124:42]
-  assign addrcheck_io_lsu_pkt_d_bits_load = io_lsu_pkt_d_bits_load; // @[lsu_lsc_ctl.scala 124:42]
-  assign addrcheck_io_lsu_pkt_d_bits_store = io_lsu_pkt_d_bits_store; // @[lsu_lsc_ctl.scala 124:42]
-  assign addrcheck_io_lsu_pkt_d_bits_dma = io_lsu_pkt_d_bits_dma; // @[lsu_lsc_ctl.scala 124:42]
-  assign addrcheck_io_dec_tlu_mrac_ff = io_dec_tlu_mrac_ff; // @[lsu_lsc_ctl.scala 125:42]
-  assign addrcheck_io_rs1_region_d = rs1_d[31:28]; // @[lsu_lsc_ctl.scala 126:42]
-  assign rvclkhdr_io_clk = clock; // @[lib.scala 380:18]
-  assign rvclkhdr_io_en = _T_104 | io_clk_override; // @[lib.scala 381:17]
-  assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 382:24]
-  assign rvclkhdr_1_io_clk = clock; // @[lib.scala 370:18]
-  assign rvclkhdr_1_io_en = _T_167 | io_clk_override; // @[lib.scala 371:17]
-  assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
-  assign rvclkhdr_2_io_clk = clock; // @[lib.scala 370:18]
-  assign rvclkhdr_2_io_en = _T_173 | io_clk_override; // @[lib.scala 371:17]
-  assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
-  assign rvclkhdr_3_io_clk = clock; // @[lib.scala 370:18]
-  assign rvclkhdr_3_io_en = io_addr_external_m | io_clk_override; // @[lib.scala 371:17]
-  assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
+  assign addrcheck_io_lsu_c2_m_clk = io_lsu_c2_m_clk; // @[lsu_lsc_ctl.scala 119:42]
+  assign addrcheck_io_start_addr_d = {_T_41,_T_11[11:0]}; // @[lsu_lsc_ctl.scala 121:42]
+  assign addrcheck_io_end_addr_d = rs1_d + _T_65; // @[lsu_lsc_ctl.scala 122:42]
+  assign addrcheck_io_lsu_pkt_d_valid = io_lsu_pkt_d_valid; // @[lsu_lsc_ctl.scala 123:42]
+  assign addrcheck_io_lsu_pkt_d_bits_fast_int = io_lsu_pkt_d_bits_fast_int; // @[lsu_lsc_ctl.scala 123:42]
+  assign addrcheck_io_lsu_pkt_d_bits_by = io_lsu_pkt_d_bits_by; // @[lsu_lsc_ctl.scala 123:42]
+  assign addrcheck_io_lsu_pkt_d_bits_half = io_lsu_pkt_d_bits_half; // @[lsu_lsc_ctl.scala 123:42]
+  assign addrcheck_io_lsu_pkt_d_bits_word = io_lsu_pkt_d_bits_word; // @[lsu_lsc_ctl.scala 123:42]
+  assign addrcheck_io_lsu_pkt_d_bits_load = io_lsu_pkt_d_bits_load; // @[lsu_lsc_ctl.scala 123:42]
+  assign addrcheck_io_lsu_pkt_d_bits_store = io_lsu_pkt_d_bits_store; // @[lsu_lsc_ctl.scala 123:42]
+  assign addrcheck_io_lsu_pkt_d_bits_dma = io_lsu_pkt_d_bits_dma; // @[lsu_lsc_ctl.scala 123:42]
+  assign addrcheck_io_dec_tlu_mrac_ff = io_dec_tlu_mrac_ff; // @[lsu_lsc_ctl.scala 124:42]
+  assign addrcheck_io_rs1_region_d = rs1_d[31:28]; // @[lsu_lsc_ctl.scala 125:42]
+  assign rvclkhdr_io_clk = clock; // @[lib.scala 392:18]
+  assign rvclkhdr_io_en = _T_162 | io_clk_override; // @[lib.scala 393:17]
+  assign rvclkhdr_1_io_clk = clock; // @[lib.scala 392:18]
+  assign rvclkhdr_1_io_en = _T_168 | io_clk_override; // @[lib.scala 393:17]
+  assign rvclkhdr_2_io_clk = clock; // @[lib.scala 392:18]
+  assign rvclkhdr_2_io_en = io_addr_external_m | io_clk_override; // @[lib.scala 393:17]
 `ifdef RANDOMIZE_GARBAGE_ASSIGN
 `define RANDOMIZE
 `endif
@@ -757,83 +728,85 @@ initial begin
   _RAND_4 = {1{`RANDOM}};
   fir_nondccm_access_error_m = _RAND_4[0:0];
   _RAND_5 = {1{`RANDOM}};
-  _T_109_bits_inst_type = _RAND_5[0:0];
+  access_fault_r = _RAND_5[0:0];
   _RAND_6 = {1{`RANDOM}};
-  _T_109_bits_exc_type = _RAND_6[0:0];
+  misaligned_fault_r = _RAND_6[0:0];
   _RAND_7 = {1{`RANDOM}};
-  _T_109_bits_mscause = _RAND_7[3:0];
+  exc_mscause_r = _RAND_7[3:0];
   _RAND_8 = {1{`RANDOM}};
-  _T_109_bits_addr = _RAND_8[31:0];
+  fir_nondccm_access_error_r = _RAND_8[0:0];
   _RAND_9 = {1{`RANDOM}};
-  _T_110 = _RAND_9[0:0];
+  fir_dccm_access_error_r = _RAND_9[0:0];
   _RAND_10 = {1{`RANDOM}};
-  _T_111 = _RAND_10[0:0];
+  _T_133_bits_fast_int = _RAND_10[0:0];
   _RAND_11 = {1{`RANDOM}};
-  _T_112 = _RAND_11[1:0];
+  _T_133_bits_by = _RAND_11[0:0];
   _RAND_12 = {1{`RANDOM}};
-  _T_138_bits_fast_int = _RAND_12[0:0];
+  _T_133_bits_half = _RAND_12[0:0];
   _RAND_13 = {1{`RANDOM}};
-  _T_138_bits_by = _RAND_13[0:0];
+  _T_133_bits_word = _RAND_13[0:0];
   _RAND_14 = {1{`RANDOM}};
-  _T_138_bits_half = _RAND_14[0:0];
+  _T_133_bits_dword = _RAND_14[0:0];
   _RAND_15 = {1{`RANDOM}};
-  _T_138_bits_word = _RAND_15[0:0];
+  _T_133_bits_load = _RAND_15[0:0];
   _RAND_16 = {1{`RANDOM}};
-  _T_138_bits_dword = _RAND_16[0:0];
+  _T_133_bits_store = _RAND_16[0:0];
   _RAND_17 = {1{`RANDOM}};
-  _T_138_bits_load = _RAND_17[0:0];
+  _T_133_bits_unsign = _RAND_17[0:0];
   _RAND_18 = {1{`RANDOM}};
-  _T_138_bits_store = _RAND_18[0:0];
+  _T_133_bits_dma = _RAND_18[0:0];
   _RAND_19 = {1{`RANDOM}};
-  _T_138_bits_unsign = _RAND_19[0:0];
+  _T_133_bits_store_data_bypass_m = _RAND_19[0:0];
   _RAND_20 = {1{`RANDOM}};
-  _T_138_bits_dma = _RAND_20[0:0];
+  _T_135_bits_fast_int = _RAND_20[0:0];
   _RAND_21 = {1{`RANDOM}};
-  _T_138_bits_store_data_bypass_m = _RAND_21[0:0];
+  _T_135_bits_by = _RAND_21[0:0];
   _RAND_22 = {1{`RANDOM}};
-  _T_140_bits_by = _RAND_22[0:0];
+  _T_135_bits_half = _RAND_22[0:0];
   _RAND_23 = {1{`RANDOM}};
-  _T_140_bits_half = _RAND_23[0:0];
+  _T_135_bits_word = _RAND_23[0:0];
   _RAND_24 = {1{`RANDOM}};
-  _T_140_bits_word = _RAND_24[0:0];
+  _T_135_bits_dword = _RAND_24[0:0];
   _RAND_25 = {1{`RANDOM}};
-  _T_140_bits_dword = _RAND_25[0:0];
+  _T_135_bits_load = _RAND_25[0:0];
   _RAND_26 = {1{`RANDOM}};
-  _T_140_bits_load = _RAND_26[0:0];
+  _T_135_bits_store = _RAND_26[0:0];
   _RAND_27 = {1{`RANDOM}};
-  _T_140_bits_store = _RAND_27[0:0];
+  _T_135_bits_unsign = _RAND_27[0:0];
   _RAND_28 = {1{`RANDOM}};
-  _T_140_bits_unsign = _RAND_28[0:0];
+  _T_135_bits_dma = _RAND_28[0:0];
   _RAND_29 = {1{`RANDOM}};
-  _T_140_bits_dma = _RAND_29[0:0];
+  _T_136 = _RAND_29[0:0];
   _RAND_30 = {1{`RANDOM}};
-  _T_141 = _RAND_30[0:0];
+  _T_137 = _RAND_30[0:0];
   _RAND_31 = {1{`RANDOM}};
-  _T_142 = _RAND_31[0:0];
+  store_data_pre_m = _RAND_31[31:0];
   _RAND_32 = {1{`RANDOM}};
-  store_data_pre_m = _RAND_32[31:0];
+  _T_147 = _RAND_32[31:0];
   _RAND_33 = {1{`RANDOM}};
-  _T_152 = _RAND_33[31:0];
+  _T_148 = _RAND_33[31:0];
   _RAND_34 = {1{`RANDOM}};
-  _T_153 = _RAND_34[31:0];
+  end_addr_pre_m = _RAND_34[28:0];
   _RAND_35 = {1{`RANDOM}};
-  _T_178 = _RAND_35[31:0];
+  _T_153 = _RAND_35[2:0];
   _RAND_36 = {1{`RANDOM}};
-  _T_179 = _RAND_36[31:0];
+  end_addr_pre_r = _RAND_36[28:0];
   _RAND_37 = {1{`RANDOM}};
-  _T_180 = _RAND_37[0:0];
+  _T_159 = _RAND_37[2:0];
   _RAND_38 = {1{`RANDOM}};
-  _T_181 = _RAND_38[0:0];
+  _T_173 = _RAND_38[0:0];
   _RAND_39 = {1{`RANDOM}};
-  _T_182 = _RAND_39[0:0];
+  _T_174 = _RAND_39[0:0];
   _RAND_40 = {1{`RANDOM}};
-  _T_183 = _RAND_40[0:0];
+  _T_175 = _RAND_40[0:0];
   _RAND_41 = {1{`RANDOM}};
-  _T_184 = _RAND_41[0:0];
+  _T_176 = _RAND_41[0:0];
   _RAND_42 = {1{`RANDOM}};
-  addr_external_r = _RAND_42[0:0];
+  _T_177 = _RAND_42[0:0];
   _RAND_43 = {1{`RANDOM}};
-  bus_read_data_r = _RAND_43[31:0];
+  addr_external_r = _RAND_43[0:0];
+  _RAND_44 = {1{`RANDOM}};
+  bus_read_data_r = _RAND_44[31:0];
 `endif // RANDOMIZE_REG_INIT
   if (reset) begin
     access_fault_m = 1'h0;
@@ -851,115 +824,118 @@ initial begin
     fir_nondccm_access_error_m = 1'h0;
   end
   if (reset) begin
-    _T_109_bits_inst_type = 1'h0;
+    access_fault_r = 1'h0;
   end
   if (reset) begin
-    _T_109_bits_exc_type = 1'h0;
+    misaligned_fault_r = 1'h0;
   end
   if (reset) begin
-    _T_109_bits_mscause = 4'h0;
+    exc_mscause_r = 4'h0;
   end
   if (reset) begin
-    _T_109_bits_addr = 32'h0;
+    fir_nondccm_access_error_r = 1'h0;
   end
   if (reset) begin
-    _T_110 = 1'h0;
+    fir_dccm_access_error_r = 1'h0;
   end
   if (reset) begin
-    _T_111 = 1'h0;
+    _T_133_bits_fast_int = 1'h0;
   end
   if (reset) begin
-    _T_112 = 2'h0;
+    _T_133_bits_by = 1'h0;
   end
   if (reset) begin
-    _T_138_bits_fast_int = 1'h0;
+    _T_133_bits_half = 1'h0;
   end
   if (reset) begin
-    _T_138_bits_by = 1'h0;
+    _T_133_bits_word = 1'h0;
   end
   if (reset) begin
-    _T_138_bits_half = 1'h0;
+    _T_133_bits_dword = 1'h0;
   end
   if (reset) begin
-    _T_138_bits_word = 1'h0;
+    _T_133_bits_load = 1'h0;
   end
   if (reset) begin
-    _T_138_bits_dword = 1'h0;
+    _T_133_bits_store = 1'h0;
   end
   if (reset) begin
-    _T_138_bits_load = 1'h0;
+    _T_133_bits_unsign = 1'h0;
   end
   if (reset) begin
-    _T_138_bits_store = 1'h0;
+    _T_133_bits_dma = 1'h0;
   end
   if (reset) begin
-    _T_138_bits_unsign = 1'h0;
+    _T_133_bits_store_data_bypass_m = 1'h0;
   end
   if (reset) begin
-    _T_138_bits_dma = 1'h0;
+    _T_135_bits_fast_int = 1'h0;
   end
   if (reset) begin
-    _T_138_bits_store_data_bypass_m = 1'h0;
+    _T_135_bits_by = 1'h0;
   end
   if (reset) begin
-    _T_140_bits_by = 1'h0;
+    _T_135_bits_half = 1'h0;
   end
   if (reset) begin
-    _T_140_bits_half = 1'h0;
+    _T_135_bits_word = 1'h0;
   end
   if (reset) begin
-    _T_140_bits_word = 1'h0;
+    _T_135_bits_dword = 1'h0;
   end
   if (reset) begin
-    _T_140_bits_dword = 1'h0;
+    _T_135_bits_load = 1'h0;
   end
   if (reset) begin
-    _T_140_bits_load = 1'h0;
+    _T_135_bits_store = 1'h0;
   end
   if (reset) begin
-    _T_140_bits_store = 1'h0;
+    _T_135_bits_unsign = 1'h0;
   end
   if (reset) begin
-    _T_140_bits_unsign = 1'h0;
+    _T_135_bits_dma = 1'h0;
   end
   if (reset) begin
-    _T_140_bits_dma = 1'h0;
+    _T_136 = 1'h0;
   end
   if (reset) begin
-    _T_141 = 1'h0;
-  end
-  if (reset) begin
-    _T_142 = 1'h0;
+    _T_137 = 1'h0;
   end
   if (reset) begin
     store_data_pre_m = 32'h0;
   end
   if (reset) begin
-    _T_152 = 32'h0;
+    _T_147 = 32'h0;
   end
   if (reset) begin
-    _T_153 = 32'h0;
+    _T_148 = 32'h0;
   end
   if (reset) begin
-    _T_178 = 32'h0;
+    end_addr_pre_m = 29'h0;
   end
   if (reset) begin
-    _T_179 = 32'h0;
+    _T_153 = 3'h0;
   end
   if (reset) begin
-    _T_180 = 1'h0;
+    end_addr_pre_r = 29'h0;
   end
   if (reset) begin
-    _T_181 = 1'h0;
+    _T_159 = 3'h0;
   end
   if (reset) begin
-    _T_182 = 1'h0;
+    _T_173 = 1'h0;
   end
   if (reset) begin
-    _T_183 = 1'h0;
+    _T_174 = 1'h0;
   end
   if (reset) begin
-    _T_184 = 1'h0;
+    _T_175 = 1'h0;
+  end
+  if (reset) begin
+    _T_176 = 1'h0;
+  end
+  if (reset) begin
+    _T_177 = 1'h0;
   end
   if (reset) begin
     addr_external_r = 1'h0;
@@ -1008,201 +984,186 @@ end // initial
       fir_nondccm_access_error_m <= addrcheck_io_fir_nondccm_access_error_d;
     end
   end
-  always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
+  always @(posedge io_lsu_c1_r_clk or posedge reset) begin
     if (reset) begin
-      _T_109_bits_inst_type <= 1'h0;
+      access_fault_r <= 1'h0;
     end else begin
-      _T_109_bits_inst_type <= io_lsu_pkt_m_bits_store;
-    end
-  end
-  always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
-    if (reset) begin
-      _T_109_bits_exc_type <= 1'h0;
-    end else begin
-      _T_109_bits_exc_type <= ~misaligned_fault_m;
-    end
-  end
-  always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
-    if (reset) begin
-      _T_109_bits_mscause <= 4'h0;
-    end else if (_T_92) begin
-      _T_109_bits_mscause <= 4'h1;
-    end else begin
-      _T_109_bits_mscause <= exc_mscause_m;
-    end
-  end
-  always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
-    if (reset) begin
-      _T_109_bits_addr <= 32'h0;
-    end else begin
-      _T_109_bits_addr <= io_lsu_addr_m;
-    end
-  end
-  always @(posedge io_lsu_c2_r_clk or posedge reset) begin
-    if (reset) begin
-      _T_110 <= 1'h0;
-    end else begin
-      _T_110 <= _T_85 & _T_78;
-    end
-  end
-  always @(posedge io_lsu_c2_r_clk or posedge reset) begin
-    if (reset) begin
-      _T_111 <= 1'h0;
-    end else begin
-      _T_111 <= _T_81 & _T_82;
-    end
-  end
-  always @(posedge clock or posedge reset) begin
-    if (reset) begin
-      _T_112 <= 2'h0;
-    end else if (fir_nondccm_access_error_m) begin
-      _T_112 <= 2'h3;
-    end else if (fir_dccm_access_error_m) begin
-      _T_112 <= 2'h2;
-    end else if (_T_99) begin
-      _T_112 <= 2'h1;
-    end else begin
-      _T_112 <= 2'h0;
-    end
-  end
-  always @(posedge io_lsu_c1_m_clk or posedge reset) begin
-    if (reset) begin
-      _T_138_bits_fast_int <= 1'h0;
-    end else begin
-      _T_138_bits_fast_int <= io_lsu_pkt_d_bits_fast_int;
-    end
-  end
-  always @(posedge io_lsu_c1_m_clk or posedge reset) begin
-    if (reset) begin
-      _T_138_bits_by <= 1'h0;
-    end else begin
-      _T_138_bits_by <= io_lsu_pkt_d_bits_by;
-    end
-  end
-  always @(posedge io_lsu_c1_m_clk or posedge reset) begin
-    if (reset) begin
-      _T_138_bits_half <= 1'h0;
-    end else begin
-      _T_138_bits_half <= io_lsu_pkt_d_bits_half;
-    end
-  end
-  always @(posedge io_lsu_c1_m_clk or posedge reset) begin
-    if (reset) begin
-      _T_138_bits_word <= 1'h0;
-    end else begin
-      _T_138_bits_word <= io_lsu_pkt_d_bits_word;
-    end
-  end
-  always @(posedge io_lsu_c1_m_clk or posedge reset) begin
-    if (reset) begin
-      _T_138_bits_dword <= 1'h0;
-    end else begin
-      _T_138_bits_dword <= io_lsu_pkt_d_bits_dword;
-    end
-  end
-  always @(posedge io_lsu_c1_m_clk or posedge reset) begin
-    if (reset) begin
-      _T_138_bits_load <= 1'h0;
-    end else begin
-      _T_138_bits_load <= io_lsu_pkt_d_bits_load;
-    end
-  end
-  always @(posedge io_lsu_c1_m_clk or posedge reset) begin
-    if (reset) begin
-      _T_138_bits_store <= 1'h0;
-    end else begin
-      _T_138_bits_store <= io_lsu_pkt_d_bits_store;
-    end
-  end
-  always @(posedge io_lsu_c1_m_clk or posedge reset) begin
-    if (reset) begin
-      _T_138_bits_unsign <= 1'h0;
-    end else begin
-      _T_138_bits_unsign <= io_lsu_pkt_d_bits_unsign;
-    end
-  end
-  always @(posedge io_lsu_c1_m_clk or posedge reset) begin
-    if (reset) begin
-      _T_138_bits_dma <= 1'h0;
-    end else begin
-      _T_138_bits_dma <= io_lsu_pkt_d_bits_dma;
-    end
-  end
-  always @(posedge io_lsu_c1_m_clk or posedge reset) begin
-    if (reset) begin
-      _T_138_bits_store_data_bypass_m <= 1'h0;
-    end else begin
-      _T_138_bits_store_data_bypass_m <= io_lsu_pkt_d_bits_store_data_bypass_m;
+      access_fault_r <= access_fault_m;
     end
   end
   always @(posedge io_lsu_c1_r_clk or posedge reset) begin
     if (reset) begin
-      _T_140_bits_by <= 1'h0;
+      misaligned_fault_r <= 1'h0;
     end else begin
-      _T_140_bits_by <= io_lsu_pkt_m_bits_by;
+      misaligned_fault_r <= misaligned_fault_m;
     end
   end
   always @(posedge io_lsu_c1_r_clk or posedge reset) begin
     if (reset) begin
-      _T_140_bits_half <= 1'h0;
+      exc_mscause_r <= 4'h0;
     end else begin
-      _T_140_bits_half <= io_lsu_pkt_m_bits_half;
+      exc_mscause_r <= exc_mscause_m;
     end
   end
   always @(posedge io_lsu_c1_r_clk or posedge reset) begin
     if (reset) begin
-      _T_140_bits_word <= 1'h0;
+      fir_nondccm_access_error_r <= 1'h0;
     end else begin
-      _T_140_bits_word <= io_lsu_pkt_m_bits_word;
+      fir_nondccm_access_error_r <= fir_nondccm_access_error_m;
     end
   end
   always @(posedge io_lsu_c1_r_clk or posedge reset) begin
     if (reset) begin
-      _T_140_bits_dword <= 1'h0;
+      fir_dccm_access_error_r <= 1'h0;
     end else begin
-      _T_140_bits_dword <= io_lsu_pkt_m_bits_dword;
+      fir_dccm_access_error_r <= fir_dccm_access_error_m;
+    end
+  end
+  always @(posedge io_lsu_c1_m_clk or posedge reset) begin
+    if (reset) begin
+      _T_133_bits_fast_int <= 1'h0;
+    end else begin
+      _T_133_bits_fast_int <= io_lsu_pkt_d_bits_fast_int;
+    end
+  end
+  always @(posedge io_lsu_c1_m_clk or posedge reset) begin
+    if (reset) begin
+      _T_133_bits_by <= 1'h0;
+    end else begin
+      _T_133_bits_by <= io_lsu_pkt_d_bits_by;
+    end
+  end
+  always @(posedge io_lsu_c1_m_clk or posedge reset) begin
+    if (reset) begin
+      _T_133_bits_half <= 1'h0;
+    end else begin
+      _T_133_bits_half <= io_lsu_pkt_d_bits_half;
+    end
+  end
+  always @(posedge io_lsu_c1_m_clk or posedge reset) begin
+    if (reset) begin
+      _T_133_bits_word <= 1'h0;
+    end else begin
+      _T_133_bits_word <= io_lsu_pkt_d_bits_word;
+    end
+  end
+  always @(posedge io_lsu_c1_m_clk or posedge reset) begin
+    if (reset) begin
+      _T_133_bits_dword <= 1'h0;
+    end else begin
+      _T_133_bits_dword <= io_lsu_pkt_d_bits_dword;
+    end
+  end
+  always @(posedge io_lsu_c1_m_clk or posedge reset) begin
+    if (reset) begin
+      _T_133_bits_load <= 1'h0;
+    end else begin
+      _T_133_bits_load <= io_lsu_pkt_d_bits_load;
+    end
+  end
+  always @(posedge io_lsu_c1_m_clk or posedge reset) begin
+    if (reset) begin
+      _T_133_bits_store <= 1'h0;
+    end else begin
+      _T_133_bits_store <= io_lsu_pkt_d_bits_store;
+    end
+  end
+  always @(posedge io_lsu_c1_m_clk or posedge reset) begin
+    if (reset) begin
+      _T_133_bits_unsign <= 1'h0;
+    end else begin
+      _T_133_bits_unsign <= io_lsu_pkt_d_bits_unsign;
+    end
+  end
+  always @(posedge io_lsu_c1_m_clk or posedge reset) begin
+    if (reset) begin
+      _T_133_bits_dma <= 1'h0;
+    end else begin
+      _T_133_bits_dma <= io_lsu_pkt_d_bits_dma;
+    end
+  end
+  always @(posedge io_lsu_c1_m_clk or posedge reset) begin
+    if (reset) begin
+      _T_133_bits_store_data_bypass_m <= 1'h0;
+    end else begin
+      _T_133_bits_store_data_bypass_m <= io_lsu_pkt_d_bits_store_data_bypass_m;
     end
   end
   always @(posedge io_lsu_c1_r_clk or posedge reset) begin
     if (reset) begin
-      _T_140_bits_load <= 1'h0;
+      _T_135_bits_fast_int <= 1'h0;
     end else begin
-      _T_140_bits_load <= io_lsu_pkt_m_bits_load;
+      _T_135_bits_fast_int <= io_lsu_pkt_m_bits_fast_int;
     end
   end
   always @(posedge io_lsu_c1_r_clk or posedge reset) begin
     if (reset) begin
-      _T_140_bits_store <= 1'h0;
+      _T_135_bits_by <= 1'h0;
     end else begin
-      _T_140_bits_store <= io_lsu_pkt_m_bits_store;
+      _T_135_bits_by <= io_lsu_pkt_m_bits_by;
     end
   end
   always @(posedge io_lsu_c1_r_clk or posedge reset) begin
     if (reset) begin
-      _T_140_bits_unsign <= 1'h0;
+      _T_135_bits_half <= 1'h0;
     end else begin
-      _T_140_bits_unsign <= io_lsu_pkt_m_bits_unsign;
+      _T_135_bits_half <= io_lsu_pkt_m_bits_half;
     end
   end
   always @(posedge io_lsu_c1_r_clk or posedge reset) begin
     if (reset) begin
-      _T_140_bits_dma <= 1'h0;
+      _T_135_bits_word <= 1'h0;
     end else begin
-      _T_140_bits_dma <= io_lsu_pkt_m_bits_dma;
+      _T_135_bits_word <= io_lsu_pkt_m_bits_word;
+    end
+  end
+  always @(posedge io_lsu_c1_r_clk or posedge reset) begin
+    if (reset) begin
+      _T_135_bits_dword <= 1'h0;
+    end else begin
+      _T_135_bits_dword <= io_lsu_pkt_m_bits_dword;
+    end
+  end
+  always @(posedge io_lsu_c1_r_clk or posedge reset) begin
+    if (reset) begin
+      _T_135_bits_load <= 1'h0;
+    end else begin
+      _T_135_bits_load <= io_lsu_pkt_m_bits_load;
+    end
+  end
+  always @(posedge io_lsu_c1_r_clk or posedge reset) begin
+    if (reset) begin
+      _T_135_bits_store <= 1'h0;
+    end else begin
+      _T_135_bits_store <= io_lsu_pkt_m_bits_store;
+    end
+  end
+  always @(posedge io_lsu_c1_r_clk or posedge reset) begin
+    if (reset) begin
+      _T_135_bits_unsign <= 1'h0;
+    end else begin
+      _T_135_bits_unsign <= io_lsu_pkt_m_bits_unsign;
+    end
+  end
+  always @(posedge io_lsu_c1_r_clk or posedge reset) begin
+    if (reset) begin
+      _T_135_bits_dma <= 1'h0;
+    end else begin
+      _T_135_bits_dma <= io_lsu_pkt_m_bits_dma;
     end
   end
   always @(posedge io_lsu_c2_m_clk or posedge reset) begin
     if (reset) begin
-      _T_141 <= 1'h0;
+      _T_136 <= 1'h0;
     end else begin
-      _T_141 <= io_lsu_pkt_d_valid & _T_131;
+      _T_136 <= io_lsu_pkt_d_valid & _T_126;
     end
   end
   always @(posedge io_lsu_c2_r_clk or posedge reset) begin
     if (reset) begin
-      _T_142 <= 1'h0;
+      _T_137 <= 1'h0;
     end else begin
-      _T_142 <= io_lsu_pkt_m_valid & _T_135;
+      _T_137 <= io_lsu_pkt_m_valid & _T_130;
     end
   end
   always @(posedge io_lsu_store_c1_m_clk or posedge reset) begin
@@ -1218,65 +1179,79 @@ end // initial
   end
   always @(posedge io_lsu_c1_m_clk or posedge reset) begin
     if (reset) begin
-      _T_152 <= 32'h0;
+      _T_147 <= 32'h0;
     end else begin
-      _T_152 <= io_lsu_addr_d;
+      _T_147 <= io_lsu_addr_d;
     end
   end
   always @(posedge io_lsu_c1_r_clk or posedge reset) begin
     if (reset) begin
-      _T_153 <= 32'h0;
+      _T_148 <= 32'h0;
     end else begin
-      _T_153 <= io_lsu_addr_m;
+      _T_148 <= io_lsu_addr_m;
+    end
+  end
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      end_addr_pre_m <= 29'h0;
+    end else if (_T_163) begin
+      end_addr_pre_m <= io_end_addr_d[31:3];
     end
   end
   always @(posedge io_lsu_c1_m_clk or posedge reset) begin
     if (reset) begin
-      _T_178 <= 32'h0;
+      _T_153 <= 3'h0;
     end else begin
-      _T_178 <= io_end_addr_d;
+      _T_153 <= io_end_addr_d[2:0];
+    end
+  end
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      end_addr_pre_r <= 29'h0;
+    end else if (_T_169) begin
+      end_addr_pre_r <= io_end_addr_m[31:3];
     end
   end
   always @(posedge io_lsu_c1_r_clk or posedge reset) begin
     if (reset) begin
-      _T_179 <= 32'h0;
+      _T_159 <= 3'h0;
     end else begin
-      _T_179 <= io_end_addr_m;
+      _T_159 <= io_end_addr_m[2:0];
     end
   end
   always @(posedge io_lsu_c1_m_clk or posedge reset) begin
     if (reset) begin
-      _T_180 <= 1'h0;
+      _T_173 <= 1'h0;
     end else begin
-      _T_180 <= io_addr_in_dccm_d;
+      _T_173 <= io_addr_in_dccm_d;
     end
   end
   always @(posedge io_lsu_c1_r_clk or posedge reset) begin
     if (reset) begin
-      _T_181 <= 1'h0;
+      _T_174 <= 1'h0;
     end else begin
-      _T_181 <= io_addr_in_dccm_m;
+      _T_174 <= io_addr_in_dccm_m;
     end
   end
   always @(posedge io_lsu_c1_m_clk or posedge reset) begin
     if (reset) begin
-      _T_182 <= 1'h0;
+      _T_175 <= 1'h0;
     end else begin
-      _T_182 <= io_addr_in_pic_d;
+      _T_175 <= io_addr_in_pic_d;
     end
   end
   always @(posedge io_lsu_c1_r_clk or posedge reset) begin
     if (reset) begin
-      _T_183 <= 1'h0;
+      _T_176 <= 1'h0;
     end else begin
-      _T_183 <= io_addr_in_pic_m;
+      _T_176 <= io_addr_in_pic_m;
     end
   end
   always @(posedge io_lsu_c1_m_clk or posedge reset) begin
     if (reset) begin
-      _T_184 <= 1'h0;
+      _T_177 <= 1'h0;
     end else begin
-      _T_184 <= addrcheck_io_addr_external_d;
+      _T_177 <= addrcheck_io_addr_external_d;
     end
   end
   always @(posedge io_lsu_c1_r_clk or posedge reset) begin
@@ -1286,10 +1261,10 @@ end // initial
       addr_external_r <= io_addr_external_m;
     end
   end
-  always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin
+  always @(posedge clock or posedge reset) begin
     if (reset) begin
       bus_read_data_r <= 32'h0;
-    end else begin
+    end else if (_T_178) begin
       bus_read_data_r <= io_bus_read_data_m;
     end
   end
@@ -1299,7 +1274,9 @@ module lsu_dccm_ctl(
   input         reset,
   input         io_clk_override,
   input         io_lsu_c2_m_clk,
+  input         io_lsu_c2_r_clk,
   input         io_lsu_free_c2_clk,
+  input         io_lsu_c1_r_clk,
   input         io_lsu_store_c1_r_clk,
   input         io_lsu_pkt_d_valid,
   input         io_lsu_pkt_d_bits_word,
@@ -1308,10 +1285,6 @@ module lsu_dccm_ctl(
   input         io_lsu_pkt_d_bits_store,
   input         io_lsu_pkt_d_bits_dma,
   input         io_lsu_pkt_m_valid,
-  input         io_lsu_pkt_m_bits_by,
-  input         io_lsu_pkt_m_bits_half,
-  input         io_lsu_pkt_m_bits_word,
-  input         io_lsu_pkt_m_bits_load,
   input         io_lsu_pkt_m_bits_store,
   input         io_lsu_pkt_m_bits_dma,
   input         io_lsu_pkt_r_valid,
@@ -1331,6 +1304,7 @@ module lsu_dccm_ctl(
   input         io_lsu_raw_fwd_hi_r,
   input         io_lsu_commit_r,
   input         io_ldst_dual_m,
+  input         io_ldst_dual_r,
   input  [31:0] io_lsu_addr_d,
   input  [15:0] io_lsu_addr_m,
   input  [31:0] io_lsu_addr_r,
@@ -1345,10 +1319,17 @@ module lsu_dccm_ctl(
   input  [31:0] io_stbuf_fwddata_lo_m,
   input  [3:0]  io_stbuf_fwdbyteen_lo_m,
   input  [3:0]  io_stbuf_fwdbyteen_hi_m,
+  output [31:0] io_dccm_rdata_hi_r,
+  output [31:0] io_dccm_rdata_lo_r,
+  output [6:0]  io_dccm_data_ecc_hi_r,
+  output [6:0]  io_dccm_data_ecc_lo_r,
+  output [31:0] io_lsu_ld_data_r,
   output [31:0] io_lsu_ld_data_corr_r,
   input         io_lsu_double_ecc_error_r,
   input         io_single_ecc_error_hi_r,
   input         io_single_ecc_error_lo_r,
+  input  [31:0] io_sec_data_hi_r,
+  input  [31:0] io_sec_data_lo_r,
   input  [31:0] io_sec_data_hi_r_ff,
   input  [31:0] io_sec_data_lo_r_ff,
   input  [6:0]  io_sec_data_ecc_hi_r_ff,
@@ -1357,10 +1338,6 @@ module lsu_dccm_ctl(
   output [31:0] io_dccm_rdata_lo_m,
   output [6:0]  io_dccm_data_ecc_hi_m,
   output [6:0]  io_dccm_data_ecc_lo_m,
-  output [31:0] io_lsu_ld_data_m,
-  input         io_lsu_double_ecc_error_m,
-  input  [31:0] io_sec_data_hi_m,
-  input  [31:0] io_sec_data_lo_m,
   input  [31:0] io_store_data_m,
   input         io_dma_dccm_wen,
   input         io_dma_pic_wen,
@@ -1379,6 +1356,7 @@ module lsu_dccm_ctl(
   output [31:0] io_picm_mask_data_m,
   output        io_lsu_stbuf_commit_any,
   output        io_lsu_dccm_rden_m,
+  output        io_lsu_dccm_rden_r,
   input  [31:0] io_dma_dccm_ctl_dma_mem_addr,
   input  [63:0] io_dma_dccm_ctl_dma_mem_wdata,
   output        io_dma_dccm_ctl_dccm_dma_rvalid,
@@ -1401,11 +1379,10 @@ module lsu_dccm_ctl(
   output [31:0] io_lsu_pic_picm_rdaddr,
   output [31:0] io_lsu_pic_picm_wraddr,
   output [31:0] io_lsu_pic_picm_wr_data,
-  input  [31:0] io_lsu_pic_picm_rd_data,
-  input         io_scan_mode
+  input  [31:0] io_lsu_pic_picm_rd_data
 );
 `ifdef RANDOMIZE_REG_INIT
-  reg [63:0] _RAND_0;
+  reg [31:0] _RAND_0;
   reg [31:0] _RAND_1;
   reg [31:0] _RAND_2;
   reg [31:0] _RAND_3;
@@ -1414,972 +1391,995 @@ module lsu_dccm_ctl(
   reg [31:0] _RAND_6;
   reg [31:0] _RAND_7;
   reg [31:0] _RAND_8;
+  reg [31:0] _RAND_9;
+  reg [31:0] _RAND_10;
+  reg [31:0] _RAND_11;
+  reg [31:0] _RAND_12;
+  reg [31:0] _RAND_13;
+  reg [31:0] _RAND_14;
+  reg [31:0] _RAND_15;
+  reg [31:0] _RAND_16;
+  reg [31:0] _RAND_17;
+  reg [31:0] _RAND_18;
+  reg [31:0] _RAND_19;
+  reg [31:0] _RAND_20;
 `endif // RANDOMIZE_REG_INIT
-  wire  rvclkhdr_io_l1clk; // @[lib.scala 368:23]
-  wire  rvclkhdr_io_clk; // @[lib.scala 368:23]
-  wire  rvclkhdr_io_en; // @[lib.scala 368:23]
-  wire  rvclkhdr_io_scan_mode; // @[lib.scala 368:23]
-  wire  rvclkhdr_1_io_l1clk; // @[lib.scala 368:23]
-  wire  rvclkhdr_1_io_clk; // @[lib.scala 368:23]
-  wire  rvclkhdr_1_io_en; // @[lib.scala 368:23]
-  wire  rvclkhdr_1_io_scan_mode; // @[lib.scala 368:23]
-  wire  rvclkhdr_2_io_l1clk; // @[lib.scala 368:23]
-  wire  rvclkhdr_2_io_clk; // @[lib.scala 368:23]
-  wire  rvclkhdr_2_io_en; // @[lib.scala 368:23]
-  wire  rvclkhdr_2_io_scan_mode; // @[lib.scala 368:23]
-  wire  rvclkhdr_3_io_l1clk; // @[lib.scala 368:23]
-  wire  rvclkhdr_3_io_clk; // @[lib.scala 368:23]
-  wire  rvclkhdr_3_io_en; // @[lib.scala 368:23]
-  wire  rvclkhdr_3_io_scan_mode; // @[lib.scala 368:23]
+  wire  rvclkhdr_io_l1clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_io_clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_io_en; // @[lib.scala 390:23]
+  wire  rvclkhdr_1_io_l1clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_1_io_clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_1_io_en; // @[lib.scala 390:23]
+  wire  rvclkhdr_2_io_l1clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_2_io_clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_2_io_en; // @[lib.scala 390:23]
+  wire  rvclkhdr_3_io_l1clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_3_io_clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_3_io_en; // @[lib.scala 390:23]
+  wire  rvclkhdr_4_io_l1clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_4_io_clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_4_io_en; // @[lib.scala 390:23]
+  wire  rvclkhdr_5_io_l1clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_5_io_clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_5_io_en; // @[lib.scala 390:23]
+  wire  rvclkhdr_6_io_l1clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_6_io_clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_6_io_en; // @[lib.scala 390:23]
+  wire  rvclkhdr_7_io_l1clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_7_io_clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_7_io_en; // @[lib.scala 390:23]
+  wire  rvclkhdr_8_io_l1clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_8_io_clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_8_io_en; // @[lib.scala 390:23]
+  wire  rvclkhdr_9_io_l1clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_9_io_clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_9_io_en; // @[lib.scala 390:23]
   wire [63:0] picm_rd_data_m = {io_lsu_pic_picm_rd_data,io_lsu_pic_picm_rd_data}; // @[Cat.scala 29:58]
-  wire [63:0] dccm_rdata_corr_m = {io_sec_data_hi_m,io_sec_data_lo_m}; // @[Cat.scala 29:58]
-  wire [63:0] dccm_rdata_m = {io_dccm_rdata_hi_m,io_dccm_rdata_lo_m}; // @[Cat.scala 29:58]
-  wire  _T = io_lsu_pkt_m_valid & io_lsu_pkt_m_bits_load; // @[lsu_dccm_ctl.scala 145:63]
-  wire [7:0] _T_5 = {io_stbuf_fwdbyteen_hi_m,io_stbuf_fwdbyteen_lo_m}; // @[Cat.scala 29:58]
-  wire [63:0] _T_8 = {io_stbuf_fwddata_hi_m,io_stbuf_fwddata_lo_m}; // @[Cat.scala 29:58]
-  wire [1:0] _T_13 = io_addr_in_dccm_m ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
-  wire [7:0] _GEN_0 = {{6'd0}, _T_13}; // @[lsu_dccm_ctl.scala 155:294]
-  wire [7:0] _T_15 = _GEN_0 & dccm_rdata_corr_m[7:0]; // @[lsu_dccm_ctl.scala 155:294]
-  wire [7:0] _T_16 = io_addr_in_pic_m ? picm_rd_data_m[7:0] : _T_15; // @[lsu_dccm_ctl.scala 155:214]
-  wire [7:0] _T_17 = _T_5[0] ? _T_8[7:0] : _T_16; // @[lsu_dccm_ctl.scala 155:78]
-  wire [7:0] _T_21 = {{4'd0}, _T_17[7:4]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_23 = {_T_17[3:0], 4'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_25 = _T_23 & 8'hf0; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_26 = _T_21 | _T_25; // @[Bitwise.scala 103:39]
-  wire [7:0] _GEN_1 = {{2'd0}, _T_26[7:2]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_31 = _GEN_1 & 8'h33; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_33 = {_T_26[5:0], 2'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_35 = _T_33 & 8'hcc; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_36 = _T_31 | _T_35; // @[Bitwise.scala 103:39]
-  wire [7:0] _GEN_2 = {{1'd0}, _T_36[7:1]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_41 = _GEN_2 & 8'h55; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_43 = {_T_36[6:0], 1'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_45 = _T_43 & 8'haa; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_46 = _T_41 | _T_45; // @[Bitwise.scala 103:39]
-  wire [7:0] _T_57 = _GEN_0 & dccm_rdata_corr_m[15:8]; // @[lsu_dccm_ctl.scala 155:294]
-  wire [7:0] _T_58 = io_addr_in_pic_m ? picm_rd_data_m[15:8] : _T_57; // @[lsu_dccm_ctl.scala 155:214]
-  wire [7:0] _T_59 = _T_5[1] ? _T_8[15:8] : _T_58; // @[lsu_dccm_ctl.scala 155:78]
-  wire [7:0] _T_63 = {{4'd0}, _T_59[7:4]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_65 = {_T_59[3:0], 4'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_67 = _T_65 & 8'hf0; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_68 = _T_63 | _T_67; // @[Bitwise.scala 103:39]
-  wire [7:0] _GEN_4 = {{2'd0}, _T_68[7:2]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_73 = _GEN_4 & 8'h33; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_75 = {_T_68[5:0], 2'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_77 = _T_75 & 8'hcc; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_78 = _T_73 | _T_77; // @[Bitwise.scala 103:39]
-  wire [7:0] _GEN_5 = {{1'd0}, _T_78[7:1]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_83 = _GEN_5 & 8'h55; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_85 = {_T_78[6:0], 1'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_87 = _T_85 & 8'haa; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_88 = _T_83 | _T_87; // @[Bitwise.scala 103:39]
-  wire [7:0] _T_99 = _GEN_0 & dccm_rdata_corr_m[23:16]; // @[lsu_dccm_ctl.scala 155:294]
-  wire [7:0] _T_100 = io_addr_in_pic_m ? picm_rd_data_m[23:16] : _T_99; // @[lsu_dccm_ctl.scala 155:214]
-  wire [7:0] _T_101 = _T_5[2] ? _T_8[23:16] : _T_100; // @[lsu_dccm_ctl.scala 155:78]
-  wire [7:0] _T_105 = {{4'd0}, _T_101[7:4]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_107 = {_T_101[3:0], 4'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_109 = _T_107 & 8'hf0; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_110 = _T_105 | _T_109; // @[Bitwise.scala 103:39]
-  wire [7:0] _GEN_7 = {{2'd0}, _T_110[7:2]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_115 = _GEN_7 & 8'h33; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_117 = {_T_110[5:0], 2'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_119 = _T_117 & 8'hcc; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_120 = _T_115 | _T_119; // @[Bitwise.scala 103:39]
-  wire [7:0] _GEN_8 = {{1'd0}, _T_120[7:1]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_125 = _GEN_8 & 8'h55; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_127 = {_T_120[6:0], 1'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_129 = _T_127 & 8'haa; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_130 = _T_125 | _T_129; // @[Bitwise.scala 103:39]
-  wire [7:0] _T_141 = _GEN_0 & dccm_rdata_corr_m[31:24]; // @[lsu_dccm_ctl.scala 155:294]
-  wire [7:0] _T_142 = io_addr_in_pic_m ? picm_rd_data_m[31:24] : _T_141; // @[lsu_dccm_ctl.scala 155:214]
-  wire [7:0] _T_143 = _T_5[3] ? _T_8[31:24] : _T_142; // @[lsu_dccm_ctl.scala 155:78]
-  wire [7:0] _T_147 = {{4'd0}, _T_143[7:4]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_149 = {_T_143[3:0], 4'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_151 = _T_149 & 8'hf0; // @[Bitwise.scala 103:75]
+  wire [63:0] dccm_rdata_corr_r = {io_sec_data_hi_r,io_sec_data_lo_r}; // @[Cat.scala 29:58]
+  wire [63:0] dccm_rdata_r = {io_dccm_rdata_hi_r,io_dccm_rdata_lo_r}; // @[Cat.scala 29:58]
+  wire  _T = io_lsu_pkt_r_valid & io_lsu_pkt_r_bits_load; // @[lsu_dccm_ctl.scala 124:62]
+  reg [7:0] _T_28; // @[lsu_dccm_ctl.scala 133:64]
+  wire [63:0] stbuf_fwdbyteen_r = {{56'd0}, _T_28}; // @[lsu_dccm_ctl.scala 133:27]
+  reg [31:0] _T_31; // @[Reg.scala 27:20]
+  reg [31:0] _T_34; // @[Reg.scala 27:20]
+  wire [63:0] stbuf_fwddata_r = {_T_31,_T_34}; // @[Cat.scala 29:58]
+  reg [31:0] picm_rd_data_r_32; // @[Reg.scala 27:20]
+  wire [63:0] picm_rd_data_r = {picm_rd_data_r_32,picm_rd_data_r_32}; // @[Cat.scala 29:58]
+  wire [7:0] _T_49 = io_addr_in_dccm_r ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
+  wire [7:0] _T_51 = _T_49 & dccm_rdata_corr_r[7:0]; // @[lsu_dccm_ctl.scala 138:219]
+  wire [7:0] _T_52 = io_addr_in_pic_r ? picm_rd_data_r[7:0] : _T_51; // @[lsu_dccm_ctl.scala 138:139]
+  wire [7:0] _T_53 = stbuf_fwdbyteen_r[0] ? stbuf_fwddata_r[7:0] : _T_52; // @[lsu_dccm_ctl.scala 138:77]
+  wire [7:0] _T_57 = {{4'd0}, _T_53[7:4]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_59 = {_T_53[3:0], 4'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_61 = _T_59 & 8'hf0; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_62 = _T_57 | _T_61; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_10 = {{2'd0}, _T_62[7:2]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_67 = _GEN_10 & 8'h33; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_69 = {_T_62[5:0], 2'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_71 = _T_69 & 8'hcc; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_72 = _T_67 | _T_71; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_11 = {{1'd0}, _T_72[7:1]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_77 = _GEN_11 & 8'h55; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_79 = {_T_72[6:0], 1'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_81 = _T_79 & 8'haa; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_82 = _T_77 | _T_81; // @[Bitwise.scala 103:39]
+  wire [7:0] _T_91 = _T_49 & dccm_rdata_corr_r[15:8]; // @[lsu_dccm_ctl.scala 138:219]
+  wire [7:0] _T_92 = io_addr_in_pic_r ? picm_rd_data_r[15:8] : _T_91; // @[lsu_dccm_ctl.scala 138:139]
+  wire [7:0] _T_93 = stbuf_fwdbyteen_r[1] ? stbuf_fwddata_r[15:8] : _T_92; // @[lsu_dccm_ctl.scala 138:77]
+  wire [7:0] _T_97 = {{4'd0}, _T_93[7:4]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_99 = {_T_93[3:0], 4'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_101 = _T_99 & 8'hf0; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_102 = _T_97 | _T_101; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_12 = {{2'd0}, _T_102[7:2]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_107 = _GEN_12 & 8'h33; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_109 = {_T_102[5:0], 2'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_111 = _T_109 & 8'hcc; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_112 = _T_107 | _T_111; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_13 = {{1'd0}, _T_112[7:1]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_117 = _GEN_13 & 8'h55; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_119 = {_T_112[6:0], 1'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_121 = _T_119 & 8'haa; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_122 = _T_117 | _T_121; // @[Bitwise.scala 103:39]
+  wire [7:0] _T_131 = _T_49 & dccm_rdata_corr_r[23:16]; // @[lsu_dccm_ctl.scala 138:219]
+  wire [7:0] _T_132 = io_addr_in_pic_r ? picm_rd_data_r[23:16] : _T_131; // @[lsu_dccm_ctl.scala 138:139]
+  wire [7:0] _T_133 = stbuf_fwdbyteen_r[2] ? stbuf_fwddata_r[23:16] : _T_132; // @[lsu_dccm_ctl.scala 138:77]
+  wire [7:0] _T_137 = {{4'd0}, _T_133[7:4]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_139 = {_T_133[3:0], 4'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_141 = _T_139 & 8'hf0; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_142 = _T_137 | _T_141; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_14 = {{2'd0}, _T_142[7:2]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_147 = _GEN_14 & 8'h33; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_149 = {_T_142[5:0], 2'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_151 = _T_149 & 8'hcc; // @[Bitwise.scala 103:75]
   wire [7:0] _T_152 = _T_147 | _T_151; // @[Bitwise.scala 103:39]
-  wire [7:0] _GEN_10 = {{2'd0}, _T_152[7:2]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_157 = _GEN_10 & 8'h33; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_159 = {_T_152[5:0], 2'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_161 = _T_159 & 8'hcc; // @[Bitwise.scala 103:75]
+  wire [7:0] _GEN_15 = {{1'd0}, _T_152[7:1]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_157 = _GEN_15 & 8'h55; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_159 = {_T_152[6:0], 1'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_161 = _T_159 & 8'haa; // @[Bitwise.scala 103:75]
   wire [7:0] _T_162 = _T_157 | _T_161; // @[Bitwise.scala 103:39]
-  wire [7:0] _GEN_11 = {{1'd0}, _T_162[7:1]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_167 = _GEN_11 & 8'h55; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_169 = {_T_162[6:0], 1'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_171 = _T_169 & 8'haa; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_172 = _T_167 | _T_171; // @[Bitwise.scala 103:39]
-  wire [7:0] _T_183 = _GEN_0 & dccm_rdata_corr_m[39:32]; // @[lsu_dccm_ctl.scala 155:294]
-  wire [7:0] _T_184 = io_addr_in_pic_m ? picm_rd_data_m[39:32] : _T_183; // @[lsu_dccm_ctl.scala 155:214]
-  wire [7:0] _T_185 = _T_5[4] ? _T_8[39:32] : _T_184; // @[lsu_dccm_ctl.scala 155:78]
-  wire [7:0] _T_189 = {{4'd0}, _T_185[7:4]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_191 = {_T_185[3:0], 4'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_193 = _T_191 & 8'hf0; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_194 = _T_189 | _T_193; // @[Bitwise.scala 103:39]
-  wire [7:0] _GEN_13 = {{2'd0}, _T_194[7:2]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_199 = _GEN_13 & 8'h33; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_201 = {_T_194[5:0], 2'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_203 = _T_201 & 8'hcc; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_204 = _T_199 | _T_203; // @[Bitwise.scala 103:39]
-  wire [7:0] _GEN_14 = {{1'd0}, _T_204[7:1]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_209 = _GEN_14 & 8'h55; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_211 = {_T_204[6:0], 1'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_213 = _T_211 & 8'haa; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_214 = _T_209 | _T_213; // @[Bitwise.scala 103:39]
-  wire [7:0] _T_225 = _GEN_0 & dccm_rdata_corr_m[47:40]; // @[lsu_dccm_ctl.scala 155:294]
-  wire [7:0] _T_226 = io_addr_in_pic_m ? picm_rd_data_m[47:40] : _T_225; // @[lsu_dccm_ctl.scala 155:214]
-  wire [7:0] _T_227 = _T_5[5] ? _T_8[47:40] : _T_226; // @[lsu_dccm_ctl.scala 155:78]
-  wire [7:0] _T_231 = {{4'd0}, _T_227[7:4]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_233 = {_T_227[3:0], 4'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_235 = _T_233 & 8'hf0; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_236 = _T_231 | _T_235; // @[Bitwise.scala 103:39]
-  wire [7:0] _GEN_16 = {{2'd0}, _T_236[7:2]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_241 = _GEN_16 & 8'h33; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_243 = {_T_236[5:0], 2'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_245 = _T_243 & 8'hcc; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_246 = _T_241 | _T_245; // @[Bitwise.scala 103:39]
-  wire [7:0] _GEN_17 = {{1'd0}, _T_246[7:1]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_251 = _GEN_17 & 8'h55; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_253 = {_T_246[6:0], 1'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_255 = _T_253 & 8'haa; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_256 = _T_251 | _T_255; // @[Bitwise.scala 103:39]
-  wire [7:0] _T_267 = _GEN_0 & dccm_rdata_corr_m[55:48]; // @[lsu_dccm_ctl.scala 155:294]
-  wire [7:0] _T_268 = io_addr_in_pic_m ? picm_rd_data_m[55:48] : _T_267; // @[lsu_dccm_ctl.scala 155:214]
-  wire [7:0] _T_269 = _T_5[6] ? _T_8[55:48] : _T_268; // @[lsu_dccm_ctl.scala 155:78]
-  wire [7:0] _T_273 = {{4'd0}, _T_269[7:4]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_275 = {_T_269[3:0], 4'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_277 = _T_275 & 8'hf0; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_278 = _T_273 | _T_277; // @[Bitwise.scala 103:39]
-  wire [7:0] _GEN_19 = {{2'd0}, _T_278[7:2]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_283 = _GEN_19 & 8'h33; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_285 = {_T_278[5:0], 2'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_287 = _T_285 & 8'hcc; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_288 = _T_283 | _T_287; // @[Bitwise.scala 103:39]
-  wire [7:0] _GEN_20 = {{1'd0}, _T_288[7:1]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_293 = _GEN_20 & 8'h55; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_295 = {_T_288[6:0], 1'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_297 = _T_295 & 8'haa; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_298 = _T_293 | _T_297; // @[Bitwise.scala 103:39]
-  wire [7:0] _T_309 = _GEN_0 & dccm_rdata_corr_m[63:56]; // @[lsu_dccm_ctl.scala 155:294]
-  wire [7:0] _T_310 = io_addr_in_pic_m ? picm_rd_data_m[63:56] : _T_309; // @[lsu_dccm_ctl.scala 155:214]
-  wire [7:0] _T_311 = _T_5[7] ? _T_8[63:56] : _T_310; // @[lsu_dccm_ctl.scala 155:78]
-  wire [7:0] _T_315 = {{4'd0}, _T_311[7:4]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_317 = {_T_311[3:0], 4'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_319 = _T_317 & 8'hf0; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_320 = _T_315 | _T_319; // @[Bitwise.scala 103:39]
-  wire [7:0] _GEN_22 = {{2'd0}, _T_320[7:2]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_325 = _GEN_22 & 8'h33; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_327 = {_T_320[5:0], 2'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_329 = _T_327 & 8'hcc; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_330 = _T_325 | _T_329; // @[Bitwise.scala 103:39]
-  wire [7:0] _GEN_23 = {{1'd0}, _T_330[7:1]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_335 = _GEN_23 & 8'h55; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_337 = {_T_330[6:0], 1'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_339 = _T_337 & 8'haa; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_340 = _T_335 | _T_339; // @[Bitwise.scala 103:39]
-  wire [63:0] _T_348 = {_T_46,_T_88,_T_130,_T_172,_T_214,_T_256,_T_298,_T_340}; // @[Cat.scala 29:58]
-  wire [63:0] _T_352 = {{32'd0}, _T_348[63:32]}; // @[Bitwise.scala 103:31]
-  wire [63:0] _T_354 = {_T_348[31:0], 32'h0}; // @[Bitwise.scala 103:65]
-  wire [63:0] _T_356 = _T_354 & 64'hffffffff00000000; // @[Bitwise.scala 103:75]
-  wire [63:0] _T_357 = _T_352 | _T_356; // @[Bitwise.scala 103:39]
-  wire [63:0] _GEN_24 = {{16'd0}, _T_357[63:16]}; // @[Bitwise.scala 103:31]
-  wire [63:0] _T_362 = _GEN_24 & 64'hffff0000ffff; // @[Bitwise.scala 103:31]
-  wire [63:0] _T_364 = {_T_357[47:0], 16'h0}; // @[Bitwise.scala 103:65]
-  wire [63:0] _T_366 = _T_364 & 64'hffff0000ffff0000; // @[Bitwise.scala 103:75]
-  wire [63:0] _T_367 = _T_362 | _T_366; // @[Bitwise.scala 103:39]
-  wire [63:0] _GEN_25 = {{8'd0}, _T_367[63:8]}; // @[Bitwise.scala 103:31]
-  wire [63:0] _T_372 = _GEN_25 & 64'hff00ff00ff00ff; // @[Bitwise.scala 103:31]
-  wire [63:0] _T_374 = {_T_367[55:0], 8'h0}; // @[Bitwise.scala 103:65]
-  wire [63:0] _T_376 = _T_374 & 64'hff00ff00ff00ff00; // @[Bitwise.scala 103:75]
-  wire [63:0] _T_377 = _T_372 | _T_376; // @[Bitwise.scala 103:39]
-  wire [63:0] _GEN_26 = {{4'd0}, _T_377[63:4]}; // @[Bitwise.scala 103:31]
-  wire [63:0] _T_382 = _GEN_26 & 64'hf0f0f0f0f0f0f0f; // @[Bitwise.scala 103:31]
-  wire [63:0] _T_384 = {_T_377[59:0], 4'h0}; // @[Bitwise.scala 103:65]
-  wire [63:0] _T_386 = _T_384 & 64'hf0f0f0f0f0f0f0f0; // @[Bitwise.scala 103:75]
-  wire [63:0] _T_387 = _T_382 | _T_386; // @[Bitwise.scala 103:39]
-  wire [63:0] _GEN_27 = {{2'd0}, _T_387[63:2]}; // @[Bitwise.scala 103:31]
-  wire [63:0] _T_392 = _GEN_27 & 64'h3333333333333333; // @[Bitwise.scala 103:31]
-  wire [63:0] _T_394 = {_T_387[61:0], 2'h0}; // @[Bitwise.scala 103:65]
-  wire [63:0] _T_396 = _T_394 & 64'hcccccccccccccccc; // @[Bitwise.scala 103:75]
-  wire [63:0] _T_397 = _T_392 | _T_396; // @[Bitwise.scala 103:39]
-  wire [63:0] _GEN_28 = {{1'd0}, _T_397[63:1]}; // @[Bitwise.scala 103:31]
-  wire [63:0] _T_402 = _GEN_28 & 64'h5555555555555555; // @[Bitwise.scala 103:31]
-  wire [63:0] _T_404 = {_T_397[62:0], 1'h0}; // @[Bitwise.scala 103:65]
-  wire [63:0] _T_406 = _T_404 & 64'haaaaaaaaaaaaaaaa; // @[Bitwise.scala 103:75]
-  wire [63:0] lsu_rdata_corr_m = _T_402 | _T_406; // @[Bitwise.scala 103:39]
-  wire [127:0] _T_3 = {lsu_rdata_corr_m,lsu_rdata_corr_m}; // @[Cat.scala 29:58]
-  wire [127:0] _T_4 = io_ldst_dual_m ? {{64'd0}, lsu_rdata_corr_m} : _T_3; // @[lsu_dccm_ctl.scala 147:47]
-  wire [7:0] _T_418 = _GEN_0 & dccm_rdata_m[7:0]; // @[lsu_dccm_ctl.scala 156:294]
-  wire [7:0] _T_419 = io_addr_in_pic_m ? picm_rd_data_m[7:0] : _T_418; // @[lsu_dccm_ctl.scala 156:214]
-  wire [7:0] _T_420 = _T_5[0] ? _T_8[7:0] : _T_419; // @[lsu_dccm_ctl.scala 156:78]
-  wire [7:0] _T_424 = {{4'd0}, _T_420[7:4]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_426 = {_T_420[3:0], 4'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_428 = _T_426 & 8'hf0; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_429 = _T_424 | _T_428; // @[Bitwise.scala 103:39]
-  wire [7:0] _GEN_30 = {{2'd0}, _T_429[7:2]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_434 = _GEN_30 & 8'h33; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_436 = {_T_429[5:0], 2'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_438 = _T_436 & 8'hcc; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_439 = _T_434 | _T_438; // @[Bitwise.scala 103:39]
-  wire [7:0] _GEN_31 = {{1'd0}, _T_439[7:1]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_444 = _GEN_31 & 8'h55; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_446 = {_T_439[6:0], 1'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_448 = _T_446 & 8'haa; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_171 = _T_49 & dccm_rdata_corr_r[31:24]; // @[lsu_dccm_ctl.scala 138:219]
+  wire [7:0] _T_172 = io_addr_in_pic_r ? picm_rd_data_r[31:24] : _T_171; // @[lsu_dccm_ctl.scala 138:139]
+  wire [7:0] _T_173 = stbuf_fwdbyteen_r[3] ? stbuf_fwddata_r[31:24] : _T_172; // @[lsu_dccm_ctl.scala 138:77]
+  wire [7:0] _T_177 = {{4'd0}, _T_173[7:4]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_179 = {_T_173[3:0], 4'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_181 = _T_179 & 8'hf0; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_182 = _T_177 | _T_181; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_16 = {{2'd0}, _T_182[7:2]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_187 = _GEN_16 & 8'h33; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_189 = {_T_182[5:0], 2'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_191 = _T_189 & 8'hcc; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_192 = _T_187 | _T_191; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_17 = {{1'd0}, _T_192[7:1]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_197 = _GEN_17 & 8'h55; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_199 = {_T_192[6:0], 1'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_201 = _T_199 & 8'haa; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_202 = _T_197 | _T_201; // @[Bitwise.scala 103:39]
+  wire [7:0] _T_211 = _T_49 & dccm_rdata_corr_r[39:32]; // @[lsu_dccm_ctl.scala 138:219]
+  wire [7:0] _T_212 = io_addr_in_pic_r ? picm_rd_data_r[39:32] : _T_211; // @[lsu_dccm_ctl.scala 138:139]
+  wire [7:0] _T_213 = stbuf_fwdbyteen_r[4] ? stbuf_fwddata_r[39:32] : _T_212; // @[lsu_dccm_ctl.scala 138:77]
+  wire [7:0] _T_217 = {{4'd0}, _T_213[7:4]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_219 = {_T_213[3:0], 4'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_221 = _T_219 & 8'hf0; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_222 = _T_217 | _T_221; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_18 = {{2'd0}, _T_222[7:2]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_227 = _GEN_18 & 8'h33; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_229 = {_T_222[5:0], 2'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_231 = _T_229 & 8'hcc; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_232 = _T_227 | _T_231; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_19 = {{1'd0}, _T_232[7:1]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_237 = _GEN_19 & 8'h55; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_239 = {_T_232[6:0], 1'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_241 = _T_239 & 8'haa; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_242 = _T_237 | _T_241; // @[Bitwise.scala 103:39]
+  wire [7:0] _T_251 = _T_49 & dccm_rdata_corr_r[47:40]; // @[lsu_dccm_ctl.scala 138:219]
+  wire [7:0] _T_252 = io_addr_in_pic_r ? picm_rd_data_r[47:40] : _T_251; // @[lsu_dccm_ctl.scala 138:139]
+  wire [7:0] _T_253 = stbuf_fwdbyteen_r[5] ? stbuf_fwddata_r[47:40] : _T_252; // @[lsu_dccm_ctl.scala 138:77]
+  wire [7:0] _T_257 = {{4'd0}, _T_253[7:4]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_259 = {_T_253[3:0], 4'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_261 = _T_259 & 8'hf0; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_262 = _T_257 | _T_261; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_20 = {{2'd0}, _T_262[7:2]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_267 = _GEN_20 & 8'h33; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_269 = {_T_262[5:0], 2'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_271 = _T_269 & 8'hcc; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_272 = _T_267 | _T_271; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_21 = {{1'd0}, _T_272[7:1]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_277 = _GEN_21 & 8'h55; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_279 = {_T_272[6:0], 1'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_281 = _T_279 & 8'haa; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_282 = _T_277 | _T_281; // @[Bitwise.scala 103:39]
+  wire [7:0] _T_291 = _T_49 & dccm_rdata_corr_r[55:48]; // @[lsu_dccm_ctl.scala 138:219]
+  wire [7:0] _T_292 = io_addr_in_pic_r ? picm_rd_data_r[55:48] : _T_291; // @[lsu_dccm_ctl.scala 138:139]
+  wire [7:0] _T_293 = stbuf_fwdbyteen_r[6] ? stbuf_fwddata_r[55:48] : _T_292; // @[lsu_dccm_ctl.scala 138:77]
+  wire [7:0] _T_297 = {{4'd0}, _T_293[7:4]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_299 = {_T_293[3:0], 4'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_301 = _T_299 & 8'hf0; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_302 = _T_297 | _T_301; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_22 = {{2'd0}, _T_302[7:2]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_307 = _GEN_22 & 8'h33; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_309 = {_T_302[5:0], 2'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_311 = _T_309 & 8'hcc; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_312 = _T_307 | _T_311; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_23 = {{1'd0}, _T_312[7:1]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_317 = _GEN_23 & 8'h55; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_319 = {_T_312[6:0], 1'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_321 = _T_319 & 8'haa; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_322 = _T_317 | _T_321; // @[Bitwise.scala 103:39]
+  wire [7:0] _T_331 = _T_49 & dccm_rdata_corr_r[63:56]; // @[lsu_dccm_ctl.scala 138:219]
+  wire [7:0] _T_332 = io_addr_in_pic_r ? picm_rd_data_r[63:56] : _T_331; // @[lsu_dccm_ctl.scala 138:139]
+  wire [7:0] _T_333 = stbuf_fwdbyteen_r[7] ? stbuf_fwddata_r[63:56] : _T_332; // @[lsu_dccm_ctl.scala 138:77]
+  wire [7:0] _T_337 = {{4'd0}, _T_333[7:4]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_339 = {_T_333[3:0], 4'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_341 = _T_339 & 8'hf0; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_342 = _T_337 | _T_341; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_24 = {{2'd0}, _T_342[7:2]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_347 = _GEN_24 & 8'h33; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_349 = {_T_342[5:0], 2'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_351 = _T_349 & 8'hcc; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_352 = _T_347 | _T_351; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_25 = {{1'd0}, _T_352[7:1]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_357 = _GEN_25 & 8'h55; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_359 = {_T_352[6:0], 1'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_361 = _T_359 & 8'haa; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_362 = _T_357 | _T_361; // @[Bitwise.scala 103:39]
+  wire [63:0] _T_370 = {_T_82,_T_122,_T_162,_T_202,_T_242,_T_282,_T_322,_T_362}; // @[Cat.scala 29:58]
+  wire [63:0] _T_374 = {{32'd0}, _T_370[63:32]}; // @[Bitwise.scala 103:31]
+  wire [63:0] _T_376 = {_T_370[31:0], 32'h0}; // @[Bitwise.scala 103:65]
+  wire [63:0] _T_378 = _T_376 & 64'hffffffff00000000; // @[Bitwise.scala 103:75]
+  wire [63:0] _T_379 = _T_374 | _T_378; // @[Bitwise.scala 103:39]
+  wire [63:0] _GEN_26 = {{16'd0}, _T_379[63:16]}; // @[Bitwise.scala 103:31]
+  wire [63:0] _T_384 = _GEN_26 & 64'hffff0000ffff; // @[Bitwise.scala 103:31]
+  wire [63:0] _T_386 = {_T_379[47:0], 16'h0}; // @[Bitwise.scala 103:65]
+  wire [63:0] _T_388 = _T_386 & 64'hffff0000ffff0000; // @[Bitwise.scala 103:75]
+  wire [63:0] _T_389 = _T_384 | _T_388; // @[Bitwise.scala 103:39]
+  wire [63:0] _GEN_27 = {{8'd0}, _T_389[63:8]}; // @[Bitwise.scala 103:31]
+  wire [63:0] _T_394 = _GEN_27 & 64'hff00ff00ff00ff; // @[Bitwise.scala 103:31]
+  wire [63:0] _T_396 = {_T_389[55:0], 8'h0}; // @[Bitwise.scala 103:65]
+  wire [63:0] _T_398 = _T_396 & 64'hff00ff00ff00ff00; // @[Bitwise.scala 103:75]
+  wire [63:0] _T_399 = _T_394 | _T_398; // @[Bitwise.scala 103:39]
+  wire [63:0] _GEN_28 = {{4'd0}, _T_399[63:4]}; // @[Bitwise.scala 103:31]
+  wire [63:0] _T_404 = _GEN_28 & 64'hf0f0f0f0f0f0f0f; // @[Bitwise.scala 103:31]
+  wire [63:0] _T_406 = {_T_399[59:0], 4'h0}; // @[Bitwise.scala 103:65]
+  wire [63:0] _T_408 = _T_406 & 64'hf0f0f0f0f0f0f0f0; // @[Bitwise.scala 103:75]
+  wire [63:0] _T_409 = _T_404 | _T_408; // @[Bitwise.scala 103:39]
+  wire [63:0] _GEN_29 = {{2'd0}, _T_409[63:2]}; // @[Bitwise.scala 103:31]
+  wire [63:0] _T_414 = _GEN_29 & 64'h3333333333333333; // @[Bitwise.scala 103:31]
+  wire [63:0] _T_416 = {_T_409[61:0], 2'h0}; // @[Bitwise.scala 103:65]
+  wire [63:0] _T_418 = _T_416 & 64'hcccccccccccccccc; // @[Bitwise.scala 103:75]
+  wire [63:0] _T_419 = _T_414 | _T_418; // @[Bitwise.scala 103:39]
+  wire [63:0] _GEN_30 = {{1'd0}, _T_419[63:1]}; // @[Bitwise.scala 103:31]
+  wire [63:0] _T_424 = _GEN_30 & 64'h5555555555555555; // @[Bitwise.scala 103:31]
+  wire [63:0] _T_426 = {_T_419[62:0], 1'h0}; // @[Bitwise.scala 103:65]
+  wire [63:0] _T_428 = _T_426 & 64'haaaaaaaaaaaaaaaa; // @[Bitwise.scala 103:75]
+  wire [63:0] lsu_rdata_corr_r = _T_424 | _T_428; // @[Bitwise.scala 103:39]
+  wire [63:0] _T_4 = {lsu_rdata_corr_r[31:0],lsu_rdata_corr_r[31:0]}; // @[Cat.scala 29:58]
+  wire  _T_6 = |io_stbuf_fwdbyteen_hi_m; // @[lsu_dccm_ctl.scala 127:49]
+  wire  _T_7 = |io_stbuf_fwdbyteen_lo_m; // @[lsu_dccm_ctl.scala 127:79]
+  wire  _T_8 = _T_6 | _T_7; // @[lsu_dccm_ctl.scala 127:53]
+  wire  stbuf_fwddata_en = _T_8 | io_clk_override; // @[lsu_dccm_ctl.scala 127:83]
+  wire  _T_10 = io_lsu_dccm_rden_m & io_ldst_dual_m; // @[lsu_dccm_ctl.scala 129:77]
+  wire  _T_11 = _T_10 | io_clk_override; // @[lsu_dccm_ctl.scala 129:95]
+  reg [31:0] _T_14; // @[Reg.scala 27:20]
+  wire  _T_15 = io_lsu_dccm_rden_m | io_clk_override; // @[lsu_dccm_ctl.scala 130:75]
+  reg [31:0] _T_18; // @[Reg.scala 27:20]
+  reg [6:0] _T_22; // @[Reg.scala 27:20]
+  reg [6:0] _T_26; // @[Reg.scala 27:20]
+  wire  _T_37 = io_addr_in_pic_m | io_clk_override; // @[lsu_dccm_ctl.scala 135:76]
+  reg [2:0] _T_42; // @[lsu_dccm_ctl.scala 137:77]
+  wire [7:0] _T_438 = _T_49 & dccm_rdata_r[7:0]; // @[lsu_dccm_ctl.scala 139:219]
+  wire [7:0] _T_439 = io_addr_in_pic_r ? picm_rd_data_r[7:0] : _T_438; // @[lsu_dccm_ctl.scala 139:139]
+  wire [7:0] _T_440 = stbuf_fwdbyteen_r[0] ? stbuf_fwddata_r[7:0] : _T_439; // @[lsu_dccm_ctl.scala 139:77]
+  wire [7:0] _T_444 = {{4'd0}, _T_440[7:4]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_446 = {_T_440[3:0], 4'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_448 = _T_446 & 8'hf0; // @[Bitwise.scala 103:75]
   wire [7:0] _T_449 = _T_444 | _T_448; // @[Bitwise.scala 103:39]
-  wire [7:0] _T_460 = _GEN_0 & dccm_rdata_m[15:8]; // @[lsu_dccm_ctl.scala 156:294]
-  wire [7:0] _T_461 = io_addr_in_pic_m ? picm_rd_data_m[15:8] : _T_460; // @[lsu_dccm_ctl.scala 156:214]
-  wire [7:0] _T_462 = _T_5[1] ? _T_8[15:8] : _T_461; // @[lsu_dccm_ctl.scala 156:78]
-  wire [7:0] _T_466 = {{4'd0}, _T_462[7:4]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_468 = {_T_462[3:0], 4'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_470 = _T_468 & 8'hf0; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_471 = _T_466 | _T_470; // @[Bitwise.scala 103:39]
-  wire [7:0] _GEN_33 = {{2'd0}, _T_471[7:2]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_476 = _GEN_33 & 8'h33; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_478 = {_T_471[5:0], 2'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_480 = _T_478 & 8'hcc; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_481 = _T_476 | _T_480; // @[Bitwise.scala 103:39]
-  wire [7:0] _GEN_34 = {{1'd0}, _T_481[7:1]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_486 = _GEN_34 & 8'h55; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_488 = {_T_481[6:0], 1'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_490 = _T_488 & 8'haa; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_491 = _T_486 | _T_490; // @[Bitwise.scala 103:39]
-  wire [7:0] _T_502 = _GEN_0 & dccm_rdata_m[23:16]; // @[lsu_dccm_ctl.scala 156:294]
-  wire [7:0] _T_503 = io_addr_in_pic_m ? picm_rd_data_m[23:16] : _T_502; // @[lsu_dccm_ctl.scala 156:214]
-  wire [7:0] _T_504 = _T_5[2] ? _T_8[23:16] : _T_503; // @[lsu_dccm_ctl.scala 156:78]
-  wire [7:0] _T_508 = {{4'd0}, _T_504[7:4]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_510 = {_T_504[3:0], 4'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_512 = _T_510 & 8'hf0; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_513 = _T_508 | _T_512; // @[Bitwise.scala 103:39]
-  wire [7:0] _GEN_36 = {{2'd0}, _T_513[7:2]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_518 = _GEN_36 & 8'h33; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_520 = {_T_513[5:0], 2'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_522 = _T_520 & 8'hcc; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_523 = _T_518 | _T_522; // @[Bitwise.scala 103:39]
-  wire [7:0] _GEN_37 = {{1'd0}, _T_523[7:1]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_528 = _GEN_37 & 8'h55; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_530 = {_T_523[6:0], 1'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_532 = _T_530 & 8'haa; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_533 = _T_528 | _T_532; // @[Bitwise.scala 103:39]
-  wire [7:0] _T_544 = _GEN_0 & dccm_rdata_m[31:24]; // @[lsu_dccm_ctl.scala 156:294]
-  wire [7:0] _T_545 = io_addr_in_pic_m ? picm_rd_data_m[31:24] : _T_544; // @[lsu_dccm_ctl.scala 156:214]
-  wire [7:0] _T_546 = _T_5[3] ? _T_8[31:24] : _T_545; // @[lsu_dccm_ctl.scala 156:78]
-  wire [7:0] _T_550 = {{4'd0}, _T_546[7:4]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_552 = {_T_546[3:0], 4'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_554 = _T_552 & 8'hf0; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_555 = _T_550 | _T_554; // @[Bitwise.scala 103:39]
-  wire [7:0] _GEN_39 = {{2'd0}, _T_555[7:2]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_560 = _GEN_39 & 8'h33; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_562 = {_T_555[5:0], 2'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_564 = _T_562 & 8'hcc; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_565 = _T_560 | _T_564; // @[Bitwise.scala 103:39]
-  wire [7:0] _GEN_40 = {{1'd0}, _T_565[7:1]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_570 = _GEN_40 & 8'h55; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_572 = {_T_565[6:0], 1'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_574 = _T_572 & 8'haa; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_575 = _T_570 | _T_574; // @[Bitwise.scala 103:39]
-  wire [7:0] _T_586 = _GEN_0 & dccm_rdata_m[39:32]; // @[lsu_dccm_ctl.scala 156:294]
-  wire [7:0] _T_587 = io_addr_in_pic_m ? picm_rd_data_m[39:32] : _T_586; // @[lsu_dccm_ctl.scala 156:214]
-  wire [7:0] _T_588 = _T_5[4] ? _T_8[39:32] : _T_587; // @[lsu_dccm_ctl.scala 156:78]
-  wire [7:0] _T_592 = {{4'd0}, _T_588[7:4]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_594 = {_T_588[3:0], 4'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_596 = _T_594 & 8'hf0; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_597 = _T_592 | _T_596; // @[Bitwise.scala 103:39]
-  wire [7:0] _GEN_42 = {{2'd0}, _T_597[7:2]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_602 = _GEN_42 & 8'h33; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_604 = {_T_597[5:0], 2'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_606 = _T_604 & 8'hcc; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_607 = _T_602 | _T_606; // @[Bitwise.scala 103:39]
-  wire [7:0] _GEN_43 = {{1'd0}, _T_607[7:1]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_612 = _GEN_43 & 8'h55; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_614 = {_T_607[6:0], 1'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_616 = _T_614 & 8'haa; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_617 = _T_612 | _T_616; // @[Bitwise.scala 103:39]
-  wire [7:0] _T_628 = _GEN_0 & dccm_rdata_m[47:40]; // @[lsu_dccm_ctl.scala 156:294]
-  wire [7:0] _T_629 = io_addr_in_pic_m ? picm_rd_data_m[47:40] : _T_628; // @[lsu_dccm_ctl.scala 156:214]
-  wire [7:0] _T_630 = _T_5[5] ? _T_8[47:40] : _T_629; // @[lsu_dccm_ctl.scala 156:78]
-  wire [7:0] _T_634 = {{4'd0}, _T_630[7:4]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_636 = {_T_630[3:0], 4'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_638 = _T_636 & 8'hf0; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_639 = _T_634 | _T_638; // @[Bitwise.scala 103:39]
-  wire [7:0] _GEN_45 = {{2'd0}, _T_639[7:2]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_644 = _GEN_45 & 8'h33; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_646 = {_T_639[5:0], 2'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_648 = _T_646 & 8'hcc; // @[Bitwise.scala 103:75]
+  wire [7:0] _GEN_31 = {{2'd0}, _T_449[7:2]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_454 = _GEN_31 & 8'h33; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_456 = {_T_449[5:0], 2'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_458 = _T_456 & 8'hcc; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_459 = _T_454 | _T_458; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_32 = {{1'd0}, _T_459[7:1]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_464 = _GEN_32 & 8'h55; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_466 = {_T_459[6:0], 1'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_468 = _T_466 & 8'haa; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_469 = _T_464 | _T_468; // @[Bitwise.scala 103:39]
+  wire [7:0] _T_478 = _T_49 & dccm_rdata_r[15:8]; // @[lsu_dccm_ctl.scala 139:219]
+  wire [7:0] _T_479 = io_addr_in_pic_r ? picm_rd_data_r[15:8] : _T_478; // @[lsu_dccm_ctl.scala 139:139]
+  wire [7:0] _T_480 = stbuf_fwdbyteen_r[1] ? stbuf_fwddata_r[15:8] : _T_479; // @[lsu_dccm_ctl.scala 139:77]
+  wire [7:0] _T_484 = {{4'd0}, _T_480[7:4]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_486 = {_T_480[3:0], 4'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_488 = _T_486 & 8'hf0; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_489 = _T_484 | _T_488; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_33 = {{2'd0}, _T_489[7:2]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_494 = _GEN_33 & 8'h33; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_496 = {_T_489[5:0], 2'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_498 = _T_496 & 8'hcc; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_499 = _T_494 | _T_498; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_34 = {{1'd0}, _T_499[7:1]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_504 = _GEN_34 & 8'h55; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_506 = {_T_499[6:0], 1'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_508 = _T_506 & 8'haa; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_509 = _T_504 | _T_508; // @[Bitwise.scala 103:39]
+  wire [7:0] _T_518 = _T_49 & dccm_rdata_r[23:16]; // @[lsu_dccm_ctl.scala 139:219]
+  wire [7:0] _T_519 = io_addr_in_pic_r ? picm_rd_data_r[23:16] : _T_518; // @[lsu_dccm_ctl.scala 139:139]
+  wire [7:0] _T_520 = stbuf_fwdbyteen_r[2] ? stbuf_fwddata_r[23:16] : _T_519; // @[lsu_dccm_ctl.scala 139:77]
+  wire [7:0] _T_524 = {{4'd0}, _T_520[7:4]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_526 = {_T_520[3:0], 4'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_528 = _T_526 & 8'hf0; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_529 = _T_524 | _T_528; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_35 = {{2'd0}, _T_529[7:2]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_534 = _GEN_35 & 8'h33; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_536 = {_T_529[5:0], 2'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_538 = _T_536 & 8'hcc; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_539 = _T_534 | _T_538; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_36 = {{1'd0}, _T_539[7:1]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_544 = _GEN_36 & 8'h55; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_546 = {_T_539[6:0], 1'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_548 = _T_546 & 8'haa; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_549 = _T_544 | _T_548; // @[Bitwise.scala 103:39]
+  wire [7:0] _T_558 = _T_49 & dccm_rdata_r[31:24]; // @[lsu_dccm_ctl.scala 139:219]
+  wire [7:0] _T_559 = io_addr_in_pic_r ? picm_rd_data_r[31:24] : _T_558; // @[lsu_dccm_ctl.scala 139:139]
+  wire [7:0] _T_560 = stbuf_fwdbyteen_r[3] ? stbuf_fwddata_r[31:24] : _T_559; // @[lsu_dccm_ctl.scala 139:77]
+  wire [7:0] _T_564 = {{4'd0}, _T_560[7:4]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_566 = {_T_560[3:0], 4'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_568 = _T_566 & 8'hf0; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_569 = _T_564 | _T_568; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_37 = {{2'd0}, _T_569[7:2]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_574 = _GEN_37 & 8'h33; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_576 = {_T_569[5:0], 2'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_578 = _T_576 & 8'hcc; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_579 = _T_574 | _T_578; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_38 = {{1'd0}, _T_579[7:1]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_584 = _GEN_38 & 8'h55; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_586 = {_T_579[6:0], 1'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_588 = _T_586 & 8'haa; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_589 = _T_584 | _T_588; // @[Bitwise.scala 103:39]
+  wire [7:0] _T_598 = _T_49 & dccm_rdata_r[39:32]; // @[lsu_dccm_ctl.scala 139:219]
+  wire [7:0] _T_599 = io_addr_in_pic_r ? picm_rd_data_r[39:32] : _T_598; // @[lsu_dccm_ctl.scala 139:139]
+  wire [7:0] _T_600 = stbuf_fwdbyteen_r[4] ? stbuf_fwddata_r[39:32] : _T_599; // @[lsu_dccm_ctl.scala 139:77]
+  wire [7:0] _T_604 = {{4'd0}, _T_600[7:4]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_606 = {_T_600[3:0], 4'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_608 = _T_606 & 8'hf0; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_609 = _T_604 | _T_608; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_39 = {{2'd0}, _T_609[7:2]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_614 = _GEN_39 & 8'h33; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_616 = {_T_609[5:0], 2'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_618 = _T_616 & 8'hcc; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_619 = _T_614 | _T_618; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_40 = {{1'd0}, _T_619[7:1]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_624 = _GEN_40 & 8'h55; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_626 = {_T_619[6:0], 1'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_628 = _T_626 & 8'haa; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_629 = _T_624 | _T_628; // @[Bitwise.scala 103:39]
+  wire [7:0] _T_638 = _T_49 & dccm_rdata_r[47:40]; // @[lsu_dccm_ctl.scala 139:219]
+  wire [7:0] _T_639 = io_addr_in_pic_r ? picm_rd_data_r[47:40] : _T_638; // @[lsu_dccm_ctl.scala 139:139]
+  wire [7:0] _T_640 = stbuf_fwdbyteen_r[5] ? stbuf_fwddata_r[47:40] : _T_639; // @[lsu_dccm_ctl.scala 139:77]
+  wire [7:0] _T_644 = {{4'd0}, _T_640[7:4]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_646 = {_T_640[3:0], 4'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_648 = _T_646 & 8'hf0; // @[Bitwise.scala 103:75]
   wire [7:0] _T_649 = _T_644 | _T_648; // @[Bitwise.scala 103:39]
-  wire [7:0] _GEN_46 = {{1'd0}, _T_649[7:1]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_654 = _GEN_46 & 8'h55; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_656 = {_T_649[6:0], 1'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_658 = _T_656 & 8'haa; // @[Bitwise.scala 103:75]
+  wire [7:0] _GEN_41 = {{2'd0}, _T_649[7:2]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_654 = _GEN_41 & 8'h33; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_656 = {_T_649[5:0], 2'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_658 = _T_656 & 8'hcc; // @[Bitwise.scala 103:75]
   wire [7:0] _T_659 = _T_654 | _T_658; // @[Bitwise.scala 103:39]
-  wire [7:0] _T_670 = _GEN_0 & dccm_rdata_m[55:48]; // @[lsu_dccm_ctl.scala 156:294]
-  wire [7:0] _T_671 = io_addr_in_pic_m ? picm_rd_data_m[55:48] : _T_670; // @[lsu_dccm_ctl.scala 156:214]
-  wire [7:0] _T_672 = _T_5[6] ? _T_8[55:48] : _T_671; // @[lsu_dccm_ctl.scala 156:78]
-  wire [7:0] _T_676 = {{4'd0}, _T_672[7:4]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_678 = {_T_672[3:0], 4'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_680 = _T_678 & 8'hf0; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_681 = _T_676 | _T_680; // @[Bitwise.scala 103:39]
-  wire [7:0] _GEN_48 = {{2'd0}, _T_681[7:2]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_686 = _GEN_48 & 8'h33; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_688 = {_T_681[5:0], 2'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_690 = _T_688 & 8'hcc; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_691 = _T_686 | _T_690; // @[Bitwise.scala 103:39]
-  wire [7:0] _GEN_49 = {{1'd0}, _T_691[7:1]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_696 = _GEN_49 & 8'h55; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_698 = {_T_691[6:0], 1'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_700 = _T_698 & 8'haa; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_701 = _T_696 | _T_700; // @[Bitwise.scala 103:39]
-  wire [7:0] _T_712 = _GEN_0 & dccm_rdata_m[63:56]; // @[lsu_dccm_ctl.scala 156:294]
-  wire [7:0] _T_713 = io_addr_in_pic_m ? picm_rd_data_m[63:56] : _T_712; // @[lsu_dccm_ctl.scala 156:214]
-  wire [7:0] _T_714 = _T_5[7] ? _T_8[63:56] : _T_713; // @[lsu_dccm_ctl.scala 156:78]
-  wire [7:0] _T_718 = {{4'd0}, _T_714[7:4]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_720 = {_T_714[3:0], 4'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_722 = _T_720 & 8'hf0; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_723 = _T_718 | _T_722; // @[Bitwise.scala 103:39]
-  wire [7:0] _GEN_51 = {{2'd0}, _T_723[7:2]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_728 = _GEN_51 & 8'h33; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_730 = {_T_723[5:0], 2'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_732 = _T_730 & 8'hcc; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_733 = _T_728 | _T_732; // @[Bitwise.scala 103:39]
-  wire [7:0] _GEN_52 = {{1'd0}, _T_733[7:1]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_738 = _GEN_52 & 8'h55; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_740 = {_T_733[6:0], 1'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_742 = _T_740 & 8'haa; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_743 = _T_738 | _T_742; // @[Bitwise.scala 103:39]
-  wire [63:0] _T_751 = {_T_449,_T_491,_T_533,_T_575,_T_617,_T_659,_T_701,_T_743}; // @[Cat.scala 29:58]
-  wire [63:0] _T_755 = {{32'd0}, _T_751[63:32]}; // @[Bitwise.scala 103:31]
-  wire [63:0] _T_757 = {_T_751[31:0], 32'h0}; // @[Bitwise.scala 103:65]
-  wire [63:0] _T_759 = _T_757 & 64'hffffffff00000000; // @[Bitwise.scala 103:75]
-  wire [63:0] _T_760 = _T_755 | _T_759; // @[Bitwise.scala 103:39]
-  wire [63:0] _GEN_53 = {{16'd0}, _T_760[63:16]}; // @[Bitwise.scala 103:31]
-  wire [63:0] _T_765 = _GEN_53 & 64'hffff0000ffff; // @[Bitwise.scala 103:31]
-  wire [63:0] _T_767 = {_T_760[47:0], 16'h0}; // @[Bitwise.scala 103:65]
-  wire [63:0] _T_769 = _T_767 & 64'hffff0000ffff0000; // @[Bitwise.scala 103:75]
-  wire [63:0] _T_770 = _T_765 | _T_769; // @[Bitwise.scala 103:39]
-  wire [63:0] _GEN_54 = {{8'd0}, _T_770[63:8]}; // @[Bitwise.scala 103:31]
-  wire [63:0] _T_775 = _GEN_54 & 64'hff00ff00ff00ff; // @[Bitwise.scala 103:31]
-  wire [63:0] _T_777 = {_T_770[55:0], 8'h0}; // @[Bitwise.scala 103:65]
-  wire [63:0] _T_779 = _T_777 & 64'hff00ff00ff00ff00; // @[Bitwise.scala 103:75]
-  wire [63:0] _T_780 = _T_775 | _T_779; // @[Bitwise.scala 103:39]
-  wire [63:0] _GEN_55 = {{4'd0}, _T_780[63:4]}; // @[Bitwise.scala 103:31]
-  wire [63:0] _T_785 = _GEN_55 & 64'hf0f0f0f0f0f0f0f; // @[Bitwise.scala 103:31]
-  wire [63:0] _T_787 = {_T_780[59:0], 4'h0}; // @[Bitwise.scala 103:65]
-  wire [63:0] _T_789 = _T_787 & 64'hf0f0f0f0f0f0f0f0; // @[Bitwise.scala 103:75]
-  wire [63:0] _T_790 = _T_785 | _T_789; // @[Bitwise.scala 103:39]
-  wire [63:0] _GEN_56 = {{2'd0}, _T_790[63:2]}; // @[Bitwise.scala 103:31]
-  wire [63:0] _T_795 = _GEN_56 & 64'h3333333333333333; // @[Bitwise.scala 103:31]
-  wire [63:0] _T_797 = {_T_790[61:0], 2'h0}; // @[Bitwise.scala 103:65]
-  wire [63:0] _T_799 = _T_797 & 64'hcccccccccccccccc; // @[Bitwise.scala 103:75]
-  wire [63:0] _T_800 = _T_795 | _T_799; // @[Bitwise.scala 103:39]
-  wire [63:0] _GEN_57 = {{1'd0}, _T_800[63:1]}; // @[Bitwise.scala 103:31]
-  wire [63:0] _T_805 = _GEN_57 & 64'h5555555555555555; // @[Bitwise.scala 103:31]
-  wire [63:0] _T_807 = {_T_800[62:0], 1'h0}; // @[Bitwise.scala 103:65]
-  wire [63:0] _T_809 = _T_807 & 64'haaaaaaaaaaaaaaaa; // @[Bitwise.scala 103:75]
-  wire [63:0] lsu_rdata_m = _T_805 | _T_809; // @[Bitwise.scala 103:39]
-  wire  _T_812 = io_addr_in_pic_m | io_addr_in_dccm_m; // @[lsu_dccm_ctl.scala 157:123]
-  wire  _T_813 = _T & _T_812; // @[lsu_dccm_ctl.scala 157:103]
-  reg [63:0] _T_817; // @[lib.scala 374:16]
-  wire [3:0] _GEN_58 = {{2'd0}, io_lsu_addr_m[1:0]}; // @[lsu_dccm_ctl.scala 158:49]
-  wire [5:0] _T_819 = 4'h8 * _GEN_58; // @[lsu_dccm_ctl.scala 158:49]
-  wire [63:0] _T_820 = lsu_rdata_m >> _T_819; // @[lsu_dccm_ctl.scala 158:43]
-  wire  _T_826 = io_lsu_addr_d[15:2] == io_lsu_addr_r[15:2]; // @[lsu_dccm_ctl.scala 163:60]
-  wire  _T_829 = io_end_addr_d[15:2] == io_lsu_addr_r[15:2]; // @[lsu_dccm_ctl.scala 163:133]
-  wire  _T_830 = _T_826 | _T_829; // @[lsu_dccm_ctl.scala 163:101]
-  wire  _T_831 = _T_830 & io_lsu_pkt_d_valid; // @[lsu_dccm_ctl.scala 163:175]
-  wire  _T_832 = _T_831 & io_lsu_pkt_d_bits_store; // @[lsu_dccm_ctl.scala 163:196]
-  wire  _T_833 = _T_832 & io_lsu_pkt_d_bits_dma; // @[lsu_dccm_ctl.scala 163:222]
-  wire  _T_834 = _T_833 & io_addr_in_dccm_d; // @[lsu_dccm_ctl.scala 163:246]
-  wire  _T_837 = io_lsu_addr_m[15:2] == io_lsu_addr_r[15:2]; // @[lsu_dccm_ctl.scala 164:37]
-  wire  _T_840 = io_end_addr_m[15:2] == io_lsu_addr_r[15:2]; // @[lsu_dccm_ctl.scala 164:110]
-  wire  _T_841 = _T_837 | _T_840; // @[lsu_dccm_ctl.scala 164:78]
-  wire  _T_842 = _T_841 & io_lsu_pkt_m_valid; // @[lsu_dccm_ctl.scala 164:152]
-  wire  _T_843 = _T_842 & io_lsu_pkt_m_bits_store; // @[lsu_dccm_ctl.scala 164:173]
-  wire  _T_844 = _T_843 & io_lsu_pkt_m_bits_dma; // @[lsu_dccm_ctl.scala 164:199]
-  wire  _T_845 = _T_844 & io_addr_in_dccm_m; // @[lsu_dccm_ctl.scala 164:223]
-  wire  kill_ecc_corr_lo_r = _T_834 | _T_845; // @[lsu_dccm_ctl.scala 163:267]
-  wire  _T_848 = io_lsu_addr_d[15:2] == io_end_addr_r[15:2]; // @[lsu_dccm_ctl.scala 166:60]
-  wire  _T_851 = io_end_addr_d[15:2] == io_end_addr_r[15:2]; // @[lsu_dccm_ctl.scala 166:133]
-  wire  _T_852 = _T_848 | _T_851; // @[lsu_dccm_ctl.scala 166:101]
-  wire  _T_853 = _T_852 & io_lsu_pkt_d_valid; // @[lsu_dccm_ctl.scala 166:175]
-  wire  _T_854 = _T_853 & io_lsu_pkt_d_bits_store; // @[lsu_dccm_ctl.scala 166:196]
-  wire  _T_855 = _T_854 & io_lsu_pkt_d_bits_dma; // @[lsu_dccm_ctl.scala 166:222]
-  wire  _T_856 = _T_855 & io_addr_in_dccm_d; // @[lsu_dccm_ctl.scala 166:246]
-  wire  _T_859 = io_lsu_addr_m[15:2] == io_end_addr_r[15:2]; // @[lsu_dccm_ctl.scala 167:37]
-  wire  _T_862 = io_end_addr_m[15:2] == io_end_addr_r[15:2]; // @[lsu_dccm_ctl.scala 167:110]
-  wire  _T_863 = _T_859 | _T_862; // @[lsu_dccm_ctl.scala 167:78]
-  wire  _T_864 = _T_863 & io_lsu_pkt_m_valid; // @[lsu_dccm_ctl.scala 167:152]
-  wire  _T_865 = _T_864 & io_lsu_pkt_m_bits_store; // @[lsu_dccm_ctl.scala 167:173]
-  wire  _T_866 = _T_865 & io_lsu_pkt_m_bits_dma; // @[lsu_dccm_ctl.scala 167:199]
-  wire  _T_867 = _T_866 & io_addr_in_dccm_m; // @[lsu_dccm_ctl.scala 167:223]
-  wire  kill_ecc_corr_hi_r = _T_856 | _T_867; // @[lsu_dccm_ctl.scala 166:267]
-  wire  _T_868 = io_lsu_pkt_r_bits_load & io_single_ecc_error_lo_r; // @[lsu_dccm_ctl.scala 169:60]
-  wire  _T_869 = ~io_lsu_raw_fwd_lo_r; // @[lsu_dccm_ctl.scala 169:89]
-  wire  ld_single_ecc_error_lo_r = _T_868 & _T_869; // @[lsu_dccm_ctl.scala 169:87]
-  wire  _T_870 = io_lsu_pkt_r_bits_load & io_single_ecc_error_hi_r; // @[lsu_dccm_ctl.scala 170:60]
-  wire  _T_871 = ~io_lsu_raw_fwd_hi_r; // @[lsu_dccm_ctl.scala 170:89]
-  wire  ld_single_ecc_error_hi_r = _T_870 & _T_871; // @[lsu_dccm_ctl.scala 170:87]
-  wire  _T_872 = ld_single_ecc_error_lo_r | ld_single_ecc_error_hi_r; // @[lsu_dccm_ctl.scala 171:63]
-  wire  _T_873 = ~io_lsu_double_ecc_error_r; // @[lsu_dccm_ctl.scala 171:93]
-  wire  _T_875 = io_lsu_commit_r | io_lsu_pkt_r_bits_dma; // @[lsu_dccm_ctl.scala 172:81]
-  wire  _T_876 = ld_single_ecc_error_lo_r & _T_875; // @[lsu_dccm_ctl.scala 172:62]
-  wire  _T_877 = ~kill_ecc_corr_lo_r; // @[lsu_dccm_ctl.scala 172:108]
-  wire  _T_879 = ld_single_ecc_error_hi_r & _T_875; // @[lsu_dccm_ctl.scala 173:62]
-  wire  _T_880 = ~kill_ecc_corr_hi_r; // @[lsu_dccm_ctl.scala 173:108]
-  wire  _T_881 = io_lsu_pkt_d_bits_word | io_lsu_pkt_d_bits_dword; // @[lsu_dccm_ctl.scala 175:125]
-  wire  _T_882 = ~_T_881; // @[lsu_dccm_ctl.scala 175:100]
-  wire  _T_884 = io_lsu_addr_d[1:0] != 2'h0; // @[lsu_dccm_ctl.scala 175:174]
-  wire  _T_885 = _T_882 | _T_884; // @[lsu_dccm_ctl.scala 175:152]
-  wire  _T_886 = io_lsu_pkt_d_bits_store & _T_885; // @[lsu_dccm_ctl.scala 175:97]
-  wire  _T_887 = io_lsu_pkt_d_bits_load | _T_886; // @[lsu_dccm_ctl.scala 175:70]
-  wire  _T_888 = io_lsu_pkt_d_valid & _T_887; // @[lsu_dccm_ctl.scala 175:44]
-  wire  lsu_dccm_rden_d = _T_888 & io_addr_in_dccm_d; // @[lsu_dccm_ctl.scala 175:191]
+  wire [7:0] _GEN_42 = {{1'd0}, _T_659[7:1]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_664 = _GEN_42 & 8'h55; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_666 = {_T_659[6:0], 1'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_668 = _T_666 & 8'haa; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_669 = _T_664 | _T_668; // @[Bitwise.scala 103:39]
+  wire [7:0] _T_678 = _T_49 & dccm_rdata_r[55:48]; // @[lsu_dccm_ctl.scala 139:219]
+  wire [7:0] _T_679 = io_addr_in_pic_r ? picm_rd_data_r[55:48] : _T_678; // @[lsu_dccm_ctl.scala 139:139]
+  wire [7:0] _T_680 = stbuf_fwdbyteen_r[6] ? stbuf_fwddata_r[55:48] : _T_679; // @[lsu_dccm_ctl.scala 139:77]
+  wire [7:0] _T_684 = {{4'd0}, _T_680[7:4]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_686 = {_T_680[3:0], 4'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_688 = _T_686 & 8'hf0; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_689 = _T_684 | _T_688; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_43 = {{2'd0}, _T_689[7:2]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_694 = _GEN_43 & 8'h33; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_696 = {_T_689[5:0], 2'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_698 = _T_696 & 8'hcc; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_699 = _T_694 | _T_698; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_44 = {{1'd0}, _T_699[7:1]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_704 = _GEN_44 & 8'h55; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_706 = {_T_699[6:0], 1'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_708 = _T_706 & 8'haa; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_709 = _T_704 | _T_708; // @[Bitwise.scala 103:39]
+  wire [7:0] _T_718 = _T_49 & dccm_rdata_r[63:56]; // @[lsu_dccm_ctl.scala 139:219]
+  wire [7:0] _T_719 = io_addr_in_pic_r ? picm_rd_data_r[63:56] : _T_718; // @[lsu_dccm_ctl.scala 139:139]
+  wire [7:0] _T_720 = stbuf_fwdbyteen_r[7] ? stbuf_fwddata_r[63:56] : _T_719; // @[lsu_dccm_ctl.scala 139:77]
+  wire [7:0] _T_724 = {{4'd0}, _T_720[7:4]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_726 = {_T_720[3:0], 4'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_728 = _T_726 & 8'hf0; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_729 = _T_724 | _T_728; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_45 = {{2'd0}, _T_729[7:2]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_734 = _GEN_45 & 8'h33; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_736 = {_T_729[5:0], 2'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_738 = _T_736 & 8'hcc; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_739 = _T_734 | _T_738; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_46 = {{1'd0}, _T_739[7:1]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_744 = _GEN_46 & 8'h55; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_746 = {_T_739[6:0], 1'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_748 = _T_746 & 8'haa; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_749 = _T_744 | _T_748; // @[Bitwise.scala 103:39]
+  wire [63:0] _T_757 = {_T_469,_T_509,_T_549,_T_589,_T_629,_T_669,_T_709,_T_749}; // @[Cat.scala 29:58]
+  wire [63:0] _T_761 = {{32'd0}, _T_757[63:32]}; // @[Bitwise.scala 103:31]
+  wire [63:0] _T_763 = {_T_757[31:0], 32'h0}; // @[Bitwise.scala 103:65]
+  wire [63:0] _T_765 = _T_763 & 64'hffffffff00000000; // @[Bitwise.scala 103:75]
+  wire [63:0] _T_766 = _T_761 | _T_765; // @[Bitwise.scala 103:39]
+  wire [63:0] _GEN_47 = {{16'd0}, _T_766[63:16]}; // @[Bitwise.scala 103:31]
+  wire [63:0] _T_771 = _GEN_47 & 64'hffff0000ffff; // @[Bitwise.scala 103:31]
+  wire [63:0] _T_773 = {_T_766[47:0], 16'h0}; // @[Bitwise.scala 103:65]
+  wire [63:0] _T_775 = _T_773 & 64'hffff0000ffff0000; // @[Bitwise.scala 103:75]
+  wire [63:0] _T_776 = _T_771 | _T_775; // @[Bitwise.scala 103:39]
+  wire [63:0] _GEN_48 = {{8'd0}, _T_776[63:8]}; // @[Bitwise.scala 103:31]
+  wire [63:0] _T_781 = _GEN_48 & 64'hff00ff00ff00ff; // @[Bitwise.scala 103:31]
+  wire [63:0] _T_783 = {_T_776[55:0], 8'h0}; // @[Bitwise.scala 103:65]
+  wire [63:0] _T_785 = _T_783 & 64'hff00ff00ff00ff00; // @[Bitwise.scala 103:75]
+  wire [63:0] _T_786 = _T_781 | _T_785; // @[Bitwise.scala 103:39]
+  wire [63:0] _GEN_49 = {{4'd0}, _T_786[63:4]}; // @[Bitwise.scala 103:31]
+  wire [63:0] _T_791 = _GEN_49 & 64'hf0f0f0f0f0f0f0f; // @[Bitwise.scala 103:31]
+  wire [63:0] _T_793 = {_T_786[59:0], 4'h0}; // @[Bitwise.scala 103:65]
+  wire [63:0] _T_795 = _T_793 & 64'hf0f0f0f0f0f0f0f0; // @[Bitwise.scala 103:75]
+  wire [63:0] _T_796 = _T_791 | _T_795; // @[Bitwise.scala 103:39]
+  wire [63:0] _GEN_50 = {{2'd0}, _T_796[63:2]}; // @[Bitwise.scala 103:31]
+  wire [63:0] _T_801 = _GEN_50 & 64'h3333333333333333; // @[Bitwise.scala 103:31]
+  wire [63:0] _T_803 = {_T_796[61:0], 2'h0}; // @[Bitwise.scala 103:65]
+  wire [63:0] _T_805 = _T_803 & 64'hcccccccccccccccc; // @[Bitwise.scala 103:75]
+  wire [63:0] _T_806 = _T_801 | _T_805; // @[Bitwise.scala 103:39]
+  wire [63:0] _GEN_51 = {{1'd0}, _T_806[63:1]}; // @[Bitwise.scala 103:31]
+  wire [63:0] _T_811 = _GEN_51 & 64'h5555555555555555; // @[Bitwise.scala 103:31]
+  wire [63:0] _T_813 = {_T_806[62:0], 1'h0}; // @[Bitwise.scala 103:65]
+  wire [63:0] _T_815 = _T_813 & 64'haaaaaaaaaaaaaaaa; // @[Bitwise.scala 103:75]
+  wire [63:0] lsu_rdata_r = _T_811 | _T_815; // @[Bitwise.scala 103:39]
+  wire [3:0] _GEN_52 = {{2'd0}, io_lsu_addr_r[1:0]}; // @[lsu_dccm_ctl.scala 140:47]
+  wire [5:0] _T_818 = 4'h8 * _GEN_52; // @[lsu_dccm_ctl.scala 140:47]
+  wire [63:0] _T_819 = lsu_rdata_r >> _T_818; // @[lsu_dccm_ctl.scala 140:41]
+  wire [63:0] _T_822 = lsu_rdata_corr_r >> _T_818; // @[lsu_dccm_ctl.scala 141:47]
+  wire  _T_825 = io_lsu_addr_d[15:2] == io_lsu_addr_r[15:2]; // @[lsu_dccm_ctl.scala 163:60]
+  wire  _T_828 = io_end_addr_d[15:2] == io_lsu_addr_r[15:2]; // @[lsu_dccm_ctl.scala 163:133]
+  wire  _T_829 = _T_825 | _T_828; // @[lsu_dccm_ctl.scala 163:101]
+  wire  _T_830 = _T_829 & io_lsu_pkt_d_valid; // @[lsu_dccm_ctl.scala 163:175]
+  wire  _T_831 = _T_830 & io_lsu_pkt_d_bits_store; // @[lsu_dccm_ctl.scala 163:196]
+  wire  _T_832 = _T_831 & io_lsu_pkt_d_bits_dma; // @[lsu_dccm_ctl.scala 163:222]
+  wire  _T_833 = _T_832 & io_addr_in_dccm_d; // @[lsu_dccm_ctl.scala 163:246]
+  wire  _T_836 = io_lsu_addr_m[15:2] == io_lsu_addr_r[15:2]; // @[lsu_dccm_ctl.scala 164:37]
+  wire  _T_839 = io_end_addr_m[15:2] == io_lsu_addr_r[15:2]; // @[lsu_dccm_ctl.scala 164:110]
+  wire  _T_840 = _T_836 | _T_839; // @[lsu_dccm_ctl.scala 164:78]
+  wire  _T_841 = _T_840 & io_lsu_pkt_m_valid; // @[lsu_dccm_ctl.scala 164:152]
+  wire  _T_842 = _T_841 & io_lsu_pkt_m_bits_store; // @[lsu_dccm_ctl.scala 164:173]
+  wire  _T_843 = _T_842 & io_lsu_pkt_m_bits_dma; // @[lsu_dccm_ctl.scala 164:199]
+  wire  _T_844 = _T_843 & io_addr_in_dccm_m; // @[lsu_dccm_ctl.scala 164:223]
+  wire  kill_ecc_corr_lo_r = _T_833 | _T_844; // @[lsu_dccm_ctl.scala 163:267]
+  wire  _T_847 = io_lsu_addr_d[15:2] == io_end_addr_r[15:2]; // @[lsu_dccm_ctl.scala 166:60]
+  wire  _T_850 = io_end_addr_d[15:2] == io_end_addr_r[15:2]; // @[lsu_dccm_ctl.scala 166:133]
+  wire  _T_851 = _T_847 | _T_850; // @[lsu_dccm_ctl.scala 166:101]
+  wire  _T_852 = _T_851 & io_lsu_pkt_d_valid; // @[lsu_dccm_ctl.scala 166:175]
+  wire  _T_853 = _T_852 & io_lsu_pkt_d_bits_store; // @[lsu_dccm_ctl.scala 166:196]
+  wire  _T_854 = _T_853 & io_lsu_pkt_d_bits_dma; // @[lsu_dccm_ctl.scala 166:222]
+  wire  _T_855 = _T_854 & io_addr_in_dccm_d; // @[lsu_dccm_ctl.scala 166:246]
+  wire  _T_858 = io_lsu_addr_m[15:2] == io_end_addr_r[15:2]; // @[lsu_dccm_ctl.scala 167:37]
+  wire  _T_861 = io_end_addr_m[15:2] == io_end_addr_r[15:2]; // @[lsu_dccm_ctl.scala 167:110]
+  wire  _T_862 = _T_858 | _T_861; // @[lsu_dccm_ctl.scala 167:78]
+  wire  _T_863 = _T_862 & io_lsu_pkt_m_valid; // @[lsu_dccm_ctl.scala 167:152]
+  wire  _T_864 = _T_863 & io_lsu_pkt_m_bits_store; // @[lsu_dccm_ctl.scala 167:173]
+  wire  _T_865 = _T_864 & io_lsu_pkt_m_bits_dma; // @[lsu_dccm_ctl.scala 167:199]
+  wire  _T_866 = _T_865 & io_addr_in_dccm_m; // @[lsu_dccm_ctl.scala 167:223]
+  wire  kill_ecc_corr_hi_r = _T_855 | _T_866; // @[lsu_dccm_ctl.scala 166:267]
+  wire  _T_867 = io_lsu_pkt_r_bits_load & io_single_ecc_error_lo_r; // @[lsu_dccm_ctl.scala 169:60]
+  wire  _T_868 = ~io_lsu_raw_fwd_lo_r; // @[lsu_dccm_ctl.scala 169:89]
+  wire  ld_single_ecc_error_lo_r = _T_867 & _T_868; // @[lsu_dccm_ctl.scala 169:87]
+  wire  _T_869 = io_lsu_pkt_r_bits_load & io_single_ecc_error_hi_r; // @[lsu_dccm_ctl.scala 170:60]
+  wire  _T_870 = ~io_lsu_raw_fwd_hi_r; // @[lsu_dccm_ctl.scala 170:89]
+  wire  ld_single_ecc_error_hi_r = _T_869 & _T_870; // @[lsu_dccm_ctl.scala 170:87]
+  wire  _T_871 = ld_single_ecc_error_lo_r | ld_single_ecc_error_hi_r; // @[lsu_dccm_ctl.scala 171:63]
+  wire  _T_872 = ~io_lsu_double_ecc_error_r; // @[lsu_dccm_ctl.scala 171:93]
+  wire  _T_874 = io_lsu_commit_r | io_lsu_pkt_r_bits_dma; // @[lsu_dccm_ctl.scala 172:81]
+  wire  _T_875 = ld_single_ecc_error_lo_r & _T_874; // @[lsu_dccm_ctl.scala 172:62]
+  wire  _T_876 = ~kill_ecc_corr_lo_r; // @[lsu_dccm_ctl.scala 172:108]
+  wire  _T_878 = ld_single_ecc_error_hi_r & _T_874; // @[lsu_dccm_ctl.scala 173:62]
+  wire  _T_879 = ~kill_ecc_corr_hi_r; // @[lsu_dccm_ctl.scala 173:108]
+  wire  _T_880 = io_lsu_pkt_d_bits_word | io_lsu_pkt_d_bits_dword; // @[lsu_dccm_ctl.scala 175:125]
+  wire  _T_881 = ~_T_880; // @[lsu_dccm_ctl.scala 175:100]
+  wire  _T_883 = io_lsu_addr_d[1:0] != 2'h0; // @[lsu_dccm_ctl.scala 175:174]
+  wire  _T_884 = _T_881 | _T_883; // @[lsu_dccm_ctl.scala 175:152]
+  wire  _T_885 = io_lsu_pkt_d_bits_store & _T_884; // @[lsu_dccm_ctl.scala 175:97]
+  wire  _T_886 = io_lsu_pkt_d_bits_load | _T_885; // @[lsu_dccm_ctl.scala 175:70]
+  wire  _T_887 = io_lsu_pkt_d_valid & _T_886; // @[lsu_dccm_ctl.scala 175:44]
+  wire  lsu_dccm_rden_d = _T_887 & io_addr_in_dccm_d; // @[lsu_dccm_ctl.scala 175:191]
   reg  ld_single_ecc_error_lo_r_ff; // @[lsu_dccm_ctl.scala 284:73]
   reg  ld_single_ecc_error_hi_r_ff; // @[lsu_dccm_ctl.scala 283:73]
-  wire  _T_889 = ld_single_ecc_error_lo_r_ff | ld_single_ecc_error_hi_r_ff; // @[lsu_dccm_ctl.scala 178:63]
+  wire  _T_888 = ld_single_ecc_error_lo_r_ff | ld_single_ecc_error_hi_r_ff; // @[lsu_dccm_ctl.scala 178:63]
   reg  lsu_double_ecc_error_r_ff; // @[lsu_dccm_ctl.scala 282:73]
-  wire  _T_890 = ~lsu_double_ecc_error_r_ff; // @[lsu_dccm_ctl.scala 178:96]
-  wire  _T_892 = lsu_dccm_rden_d | io_dma_dccm_wen; // @[lsu_dccm_ctl.scala 179:75]
-  wire  _T_893 = _T_892 | io_ld_single_ecc_error_r_ff; // @[lsu_dccm_ctl.scala 179:93]
-  wire  _T_894 = ~_T_893; // @[lsu_dccm_ctl.scala 179:57]
-  wire  _T_897 = io_stbuf_addr_any[3:2] == io_lsu_addr_d[3:2]; // @[lsu_dccm_ctl.scala 180:95]
-  wire  _T_900 = io_stbuf_addr_any[3:2] == io_end_addr_d[3:2]; // @[lsu_dccm_ctl.scala 181:76]
-  wire  _T_901 = _T_897 | _T_900; // @[lsu_dccm_ctl.scala 180:171]
-  wire  _T_902 = ~_T_901; // @[lsu_dccm_ctl.scala 180:24]
-  wire  _T_903 = lsu_dccm_rden_d & _T_902; // @[lsu_dccm_ctl.scala 180:22]
-  wire  _T_904 = _T_894 | _T_903; // @[lsu_dccm_ctl.scala 179:124]
-  wire  _T_906 = io_dma_dccm_wen | io_lsu_stbuf_commit_any; // @[lsu_dccm_ctl.scala 185:41]
-  reg [15:0] ld_sec_addr_lo_r_ff; // @[lib.scala 374:16]
-  reg [15:0] ld_sec_addr_hi_r_ff; // @[lib.scala 374:16]
-  wire [15:0] _T_913 = ld_single_ecc_error_lo_r_ff ? ld_sec_addr_lo_r_ff : ld_sec_addr_hi_r_ff; // @[lsu_dccm_ctl.scala 189:8]
-  wire [15:0] _T_917 = io_dma_dccm_wen ? io_lsu_addr_d[15:0] : io_stbuf_addr_any; // @[lsu_dccm_ctl.scala 190:8]
-  wire [15:0] _T_923 = ld_single_ecc_error_hi_r_ff ? ld_sec_addr_hi_r_ff : ld_sec_addr_lo_r_ff; // @[lsu_dccm_ctl.scala 193:8]
-  wire [15:0] _T_927 = io_dma_dccm_wen ? io_end_addr_d : io_stbuf_addr_any; // @[lsu_dccm_ctl.scala 194:8]
-  wire [38:0] _T_935 = {io_sec_data_ecc_lo_r_ff,io_sec_data_lo_r_ff}; // @[Cat.scala 29:58]
-  wire [38:0] _T_938 = {io_sec_data_ecc_hi_r_ff,io_sec_data_hi_r_ff}; // @[Cat.scala 29:58]
-  wire [38:0] _T_939 = ld_single_ecc_error_lo_r_ff ? _T_935 : _T_938; // @[lsu_dccm_ctl.scala 200:8]
-  wire [38:0] _T_943 = {io_dma_dccm_wdata_ecc_lo,io_dma_dccm_wdata_lo}; // @[Cat.scala 29:58]
-  wire [38:0] _T_946 = {io_stbuf_ecc_any,io_stbuf_data_any}; // @[Cat.scala 29:58]
-  wire [38:0] _T_947 = io_dma_dccm_wen ? _T_943 : _T_946; // @[lsu_dccm_ctl.scala 202:8]
-  wire [38:0] _T_957 = ld_single_ecc_error_hi_r_ff ? _T_938 : _T_935; // @[lsu_dccm_ctl.scala 206:8]
-  wire [38:0] _T_961 = {io_dma_dccm_wdata_ecc_hi,io_dma_dccm_wdata_hi}; // @[Cat.scala 29:58]
-  wire [38:0] _T_965 = io_dma_dccm_wen ? _T_961 : _T_946; // @[lsu_dccm_ctl.scala 208:8]
-  wire [3:0] _T_968 = io_lsu_pkt_m_bits_store ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
-  wire [3:0] _T_970 = io_lsu_pkt_m_bits_by ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
-  wire [3:0] _T_971 = _T_970 & 4'h1; // @[lsu_dccm_ctl.scala 212:94]
-  wire [3:0] _T_973 = io_lsu_pkt_m_bits_half ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
-  wire [3:0] _T_974 = _T_973 & 4'h3; // @[lsu_dccm_ctl.scala 213:38]
-  wire [3:0] _T_975 = _T_971 | _T_974; // @[lsu_dccm_ctl.scala 212:107]
-  wire [3:0] _T_977 = io_lsu_pkt_m_bits_word ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
-  wire [3:0] _T_979 = _T_975 | _T_977; // @[lsu_dccm_ctl.scala 213:51]
-  wire [3:0] store_byteen_m = _T_968 & _T_979; // @[lsu_dccm_ctl.scala 212:58]
-  wire [3:0] _T_981 = io_lsu_pkt_r_bits_store ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
-  wire [3:0] _T_983 = io_lsu_pkt_r_bits_by ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
-  wire [3:0] _T_984 = _T_983 & 4'h1; // @[lsu_dccm_ctl.scala 216:94]
-  wire [3:0] _T_986 = io_lsu_pkt_r_bits_half ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
-  wire [3:0] _T_987 = _T_986 & 4'h3; // @[lsu_dccm_ctl.scala 217:38]
-  wire [3:0] _T_988 = _T_984 | _T_987; // @[lsu_dccm_ctl.scala 216:107]
-  wire [3:0] _T_990 = io_lsu_pkt_r_bits_word ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
-  wire [3:0] _T_992 = _T_988 | _T_990; // @[lsu_dccm_ctl.scala 217:51]
-  wire [3:0] store_byteen_r = _T_981 & _T_992; // @[lsu_dccm_ctl.scala 216:58]
-  wire [6:0] _GEN_60 = {{3'd0}, store_byteen_m}; // @[lsu_dccm_ctl.scala 220:45]
-  wire [6:0] _T_995 = _GEN_60 << io_lsu_addr_m[1:0]; // @[lsu_dccm_ctl.scala 220:45]
-  wire [6:0] _GEN_61 = {{3'd0}, store_byteen_r}; // @[lsu_dccm_ctl.scala 222:45]
-  wire [6:0] _T_998 = _GEN_61 << io_lsu_addr_r[1:0]; // @[lsu_dccm_ctl.scala 222:45]
-  wire  _T_1001 = io_stbuf_addr_any[15:2] == io_lsu_addr_m[15:2]; // @[lsu_dccm_ctl.scala 225:67]
-  wire  dccm_wr_bypass_d_m_lo = _T_1001 & io_addr_in_dccm_m; // @[lsu_dccm_ctl.scala 225:101]
-  wire  _T_1004 = io_stbuf_addr_any[15:2] == io_end_addr_m[15:2]; // @[lsu_dccm_ctl.scala 226:67]
-  wire  dccm_wr_bypass_d_m_hi = _T_1004 & io_addr_in_dccm_m; // @[lsu_dccm_ctl.scala 226:101]
-  wire  _T_1007 = io_stbuf_addr_any[15:2] == io_lsu_addr_r[15:2]; // @[lsu_dccm_ctl.scala 228:67]
-  wire  dccm_wr_bypass_d_r_lo = _T_1007 & io_addr_in_dccm_r; // @[lsu_dccm_ctl.scala 228:101]
-  wire  _T_1010 = io_stbuf_addr_any[15:2] == io_end_addr_r[15:2]; // @[lsu_dccm_ctl.scala 229:67]
-  wire  dccm_wr_bypass_d_r_hi = _T_1010 & io_addr_in_dccm_r; // @[lsu_dccm_ctl.scala 229:101]
-  wire [63:0] _T_1013 = {32'h0,io_store_data_m}; // @[Cat.scala 29:58]
-  wire [126:0] _GEN_63 = {{63'd0}, _T_1013}; // @[lsu_dccm_ctl.scala 258:72]
-  wire [126:0] _T_1016 = _GEN_63 << _T_819; // @[lsu_dccm_ctl.scala 258:72]
-  wire [63:0] store_data_pre_m = _T_1016[63:0]; // @[lsu_dccm_ctl.scala 258:29]
-  wire [31:0] store_data_hi_m = store_data_pre_m[63:32]; // @[lsu_dccm_ctl.scala 259:48]
-  wire [31:0] store_data_lo_m = store_data_pre_m[31:0]; // @[lsu_dccm_ctl.scala 260:48]
-  wire [7:0] store_byteen_ext_m = {{1'd0}, _T_995}; // @[lsu_dccm_ctl.scala 220:22]
-  wire  _T_1022 = io_lsu_stbuf_commit_any & dccm_wr_bypass_d_m_lo; // @[lsu_dccm_ctl.scala 261:211]
-  wire [7:0] _T_1026 = _T_1022 ? io_stbuf_data_any[7:0] : io_sec_data_lo_m[7:0]; // @[lsu_dccm_ctl.scala 261:185]
-  wire [7:0] _T_1027 = store_byteen_ext_m[0] ? store_data_lo_m[7:0] : _T_1026; // @[lsu_dccm_ctl.scala 261:120]
-  wire [7:0] _T_1031 = {{4'd0}, _T_1027[7:4]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1033 = {_T_1027[3:0], 4'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_1035 = _T_1033 & 8'hf0; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_1036 = _T_1031 | _T_1035; // @[Bitwise.scala 103:39]
-  wire [7:0] _GEN_64 = {{2'd0}, _T_1036[7:2]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1041 = _GEN_64 & 8'h33; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1043 = {_T_1036[5:0], 2'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_1045 = _T_1043 & 8'hcc; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_1046 = _T_1041 | _T_1045; // @[Bitwise.scala 103:39]
-  wire [7:0] _GEN_65 = {{1'd0}, _T_1046[7:1]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1051 = _GEN_65 & 8'h55; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1053 = {_T_1046[6:0], 1'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_1055 = _T_1053 & 8'haa; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_1056 = _T_1051 | _T_1055; // @[Bitwise.scala 103:39]
-  wire [7:0] _T_1064 = _T_1022 ? io_stbuf_data_any[15:8] : io_sec_data_lo_m[15:8]; // @[lsu_dccm_ctl.scala 261:185]
-  wire [7:0] _T_1065 = store_byteen_ext_m[1] ? store_data_lo_m[15:8] : _T_1064; // @[lsu_dccm_ctl.scala 261:120]
-  wire [7:0] _T_1069 = {{4'd0}, _T_1065[7:4]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1071 = {_T_1065[3:0], 4'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_1073 = _T_1071 & 8'hf0; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_1074 = _T_1069 | _T_1073; // @[Bitwise.scala 103:39]
-  wire [7:0] _GEN_66 = {{2'd0}, _T_1074[7:2]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1079 = _GEN_66 & 8'h33; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1081 = {_T_1074[5:0], 2'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_1083 = _T_1081 & 8'hcc; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_1084 = _T_1079 | _T_1083; // @[Bitwise.scala 103:39]
-  wire [7:0] _GEN_67 = {{1'd0}, _T_1084[7:1]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1089 = _GEN_67 & 8'h55; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1091 = {_T_1084[6:0], 1'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_1093 = _T_1091 & 8'haa; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_1094 = _T_1089 | _T_1093; // @[Bitwise.scala 103:39]
-  wire [7:0] _T_1102 = _T_1022 ? io_stbuf_data_any[23:16] : io_sec_data_lo_m[23:16]; // @[lsu_dccm_ctl.scala 261:185]
-  wire [7:0] _T_1103 = store_byteen_ext_m[2] ? store_data_lo_m[23:16] : _T_1102; // @[lsu_dccm_ctl.scala 261:120]
-  wire [7:0] _T_1107 = {{4'd0}, _T_1103[7:4]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1109 = {_T_1103[3:0], 4'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_1111 = _T_1109 & 8'hf0; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_1112 = _T_1107 | _T_1111; // @[Bitwise.scala 103:39]
-  wire [7:0] _GEN_68 = {{2'd0}, _T_1112[7:2]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1117 = _GEN_68 & 8'h33; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1119 = {_T_1112[5:0], 2'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_1121 = _T_1119 & 8'hcc; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_1122 = _T_1117 | _T_1121; // @[Bitwise.scala 103:39]
-  wire [7:0] _GEN_69 = {{1'd0}, _T_1122[7:1]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1127 = _GEN_69 & 8'h55; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1129 = {_T_1122[6:0], 1'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_1131 = _T_1129 & 8'haa; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_1132 = _T_1127 | _T_1131; // @[Bitwise.scala 103:39]
-  wire [7:0] _T_1140 = _T_1022 ? io_stbuf_data_any[31:24] : io_sec_data_lo_m[31:24]; // @[lsu_dccm_ctl.scala 261:185]
-  wire [7:0] _T_1141 = store_byteen_ext_m[3] ? store_data_lo_m[31:24] : _T_1140; // @[lsu_dccm_ctl.scala 261:120]
-  wire [7:0] _T_1145 = {{4'd0}, _T_1141[7:4]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1147 = {_T_1141[3:0], 4'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_1149 = _T_1147 & 8'hf0; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_1150 = _T_1145 | _T_1149; // @[Bitwise.scala 103:39]
-  wire [7:0] _GEN_70 = {{2'd0}, _T_1150[7:2]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1155 = _GEN_70 & 8'h33; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1157 = {_T_1150[5:0], 2'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_1159 = _T_1157 & 8'hcc; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_1160 = _T_1155 | _T_1159; // @[Bitwise.scala 103:39]
-  wire [7:0] _GEN_71 = {{1'd0}, _T_1160[7:1]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1165 = _GEN_71 & 8'h55; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1167 = {_T_1160[6:0], 1'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_1169 = _T_1167 & 8'haa; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_1170 = _T_1165 | _T_1169; // @[Bitwise.scala 103:39]
-  wire [31:0] _T_1174 = {_T_1056,_T_1094,_T_1132,_T_1170}; // @[Cat.scala 29:58]
-  wire [31:0] _T_1178 = {{16'd0}, _T_1174[31:16]}; // @[Bitwise.scala 103:31]
-  wire [31:0] _T_1180 = {_T_1174[15:0], 16'h0}; // @[Bitwise.scala 103:65]
-  wire [31:0] _T_1182 = _T_1180 & 32'hffff0000; // @[Bitwise.scala 103:75]
-  wire [31:0] _T_1183 = _T_1178 | _T_1182; // @[Bitwise.scala 103:39]
-  wire [31:0] _GEN_72 = {{8'd0}, _T_1183[31:8]}; // @[Bitwise.scala 103:31]
-  wire [31:0] _T_1188 = _GEN_72 & 32'hff00ff; // @[Bitwise.scala 103:31]
-  wire [31:0] _T_1190 = {_T_1183[23:0], 8'h0}; // @[Bitwise.scala 103:65]
-  wire [31:0] _T_1192 = _T_1190 & 32'hff00ff00; // @[Bitwise.scala 103:75]
-  wire [31:0] _T_1193 = _T_1188 | _T_1192; // @[Bitwise.scala 103:39]
-  wire [31:0] _GEN_73 = {{4'd0}, _T_1193[31:4]}; // @[Bitwise.scala 103:31]
-  wire [31:0] _T_1198 = _GEN_73 & 32'hf0f0f0f; // @[Bitwise.scala 103:31]
-  wire [31:0] _T_1200 = {_T_1193[27:0], 4'h0}; // @[Bitwise.scala 103:65]
-  wire [31:0] _T_1202 = _T_1200 & 32'hf0f0f0f0; // @[Bitwise.scala 103:75]
-  wire [31:0] _T_1203 = _T_1198 | _T_1202; // @[Bitwise.scala 103:39]
-  wire [31:0] _GEN_74 = {{2'd0}, _T_1203[31:2]}; // @[Bitwise.scala 103:31]
-  wire [31:0] _T_1208 = _GEN_74 & 32'h33333333; // @[Bitwise.scala 103:31]
-  wire [31:0] _T_1210 = {_T_1203[29:0], 2'h0}; // @[Bitwise.scala 103:65]
-  wire [31:0] _T_1212 = _T_1210 & 32'hcccccccc; // @[Bitwise.scala 103:75]
-  wire [31:0] _T_1213 = _T_1208 | _T_1212; // @[Bitwise.scala 103:39]
-  wire [31:0] _GEN_75 = {{1'd0}, _T_1213[31:1]}; // @[Bitwise.scala 103:31]
-  wire [31:0] _T_1218 = _GEN_75 & 32'h55555555; // @[Bitwise.scala 103:31]
-  wire [31:0] _T_1220 = {_T_1213[30:0], 1'h0}; // @[Bitwise.scala 103:65]
-  wire [31:0] _T_1222 = _T_1220 & 32'haaaaaaaa; // @[Bitwise.scala 103:75]
-  reg [31:0] _T_1224; // @[lsu_dccm_ctl.scala 261:72]
-  wire  _T_1228 = io_lsu_stbuf_commit_any & dccm_wr_bypass_d_m_hi; // @[lsu_dccm_ctl.scala 262:177]
-  wire [7:0] _T_1232 = _T_1228 ? io_stbuf_data_any[7:0] : io_sec_data_hi_m[7:0]; // @[lsu_dccm_ctl.scala 262:151]
-  wire [7:0] _T_1233 = store_byteen_ext_m[4] ? store_data_hi_m[7:0] : _T_1232; // @[lsu_dccm_ctl.scala 262:86]
-  wire [7:0] _T_1237 = {{4'd0}, _T_1233[7:4]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1239 = {_T_1233[3:0], 4'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_1241 = _T_1239 & 8'hf0; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_1242 = _T_1237 | _T_1241; // @[Bitwise.scala 103:39]
-  wire [7:0] _GEN_76 = {{2'd0}, _T_1242[7:2]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1247 = _GEN_76 & 8'h33; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1249 = {_T_1242[5:0], 2'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_1251 = _T_1249 & 8'hcc; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_1252 = _T_1247 | _T_1251; // @[Bitwise.scala 103:39]
-  wire [7:0] _GEN_77 = {{1'd0}, _T_1252[7:1]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1257 = _GEN_77 & 8'h55; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1259 = {_T_1252[6:0], 1'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_1261 = _T_1259 & 8'haa; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_1262 = _T_1257 | _T_1261; // @[Bitwise.scala 103:39]
-  wire [7:0] _T_1270 = _T_1228 ? io_stbuf_data_any[15:8] : io_sec_data_hi_m[15:8]; // @[lsu_dccm_ctl.scala 262:151]
-  wire [7:0] _T_1271 = store_byteen_ext_m[5] ? store_data_hi_m[15:8] : _T_1270; // @[lsu_dccm_ctl.scala 262:86]
-  wire [7:0] _T_1275 = {{4'd0}, _T_1271[7:4]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1277 = {_T_1271[3:0], 4'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_1279 = _T_1277 & 8'hf0; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_1280 = _T_1275 | _T_1279; // @[Bitwise.scala 103:39]
-  wire [7:0] _GEN_78 = {{2'd0}, _T_1280[7:2]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1285 = _GEN_78 & 8'h33; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1287 = {_T_1280[5:0], 2'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_1289 = _T_1287 & 8'hcc; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_1290 = _T_1285 | _T_1289; // @[Bitwise.scala 103:39]
-  wire [7:0] _GEN_79 = {{1'd0}, _T_1290[7:1]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1295 = _GEN_79 & 8'h55; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1297 = {_T_1290[6:0], 1'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_1299 = _T_1297 & 8'haa; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_1300 = _T_1295 | _T_1299; // @[Bitwise.scala 103:39]
-  wire [7:0] _T_1308 = _T_1228 ? io_stbuf_data_any[23:16] : io_sec_data_hi_m[23:16]; // @[lsu_dccm_ctl.scala 262:151]
-  wire [7:0] _T_1309 = store_byteen_ext_m[6] ? store_data_hi_m[23:16] : _T_1308; // @[lsu_dccm_ctl.scala 262:86]
-  wire [7:0] _T_1313 = {{4'd0}, _T_1309[7:4]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1315 = {_T_1309[3:0], 4'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_1317 = _T_1315 & 8'hf0; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_1318 = _T_1313 | _T_1317; // @[Bitwise.scala 103:39]
-  wire [7:0] _GEN_80 = {{2'd0}, _T_1318[7:2]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1323 = _GEN_80 & 8'h33; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1325 = {_T_1318[5:0], 2'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_1327 = _T_1325 & 8'hcc; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_1328 = _T_1323 | _T_1327; // @[Bitwise.scala 103:39]
-  wire [7:0] _GEN_81 = {{1'd0}, _T_1328[7:1]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1333 = _GEN_81 & 8'h55; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1335 = {_T_1328[6:0], 1'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_1337 = _T_1335 & 8'haa; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_1338 = _T_1333 | _T_1337; // @[Bitwise.scala 103:39]
-  wire [7:0] _T_1346 = _T_1228 ? io_stbuf_data_any[31:24] : io_sec_data_hi_m[31:24]; // @[lsu_dccm_ctl.scala 262:151]
-  wire [7:0] _T_1347 = store_byteen_ext_m[7] ? store_data_hi_m[31:24] : _T_1346; // @[lsu_dccm_ctl.scala 262:86]
-  wire [7:0] _T_1351 = {{4'd0}, _T_1347[7:4]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1353 = {_T_1347[3:0], 4'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_1355 = _T_1353 & 8'hf0; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_1356 = _T_1351 | _T_1355; // @[Bitwise.scala 103:39]
-  wire [7:0] _GEN_82 = {{2'd0}, _T_1356[7:2]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1361 = _GEN_82 & 8'h33; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1363 = {_T_1356[5:0], 2'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_1365 = _T_1363 & 8'hcc; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_1366 = _T_1361 | _T_1365; // @[Bitwise.scala 103:39]
-  wire [7:0] _GEN_83 = {{1'd0}, _T_1366[7:1]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1371 = _GEN_83 & 8'h55; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1373 = {_T_1366[6:0], 1'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_1375 = _T_1373 & 8'haa; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_1376 = _T_1371 | _T_1375; // @[Bitwise.scala 103:39]
-  wire [31:0] _T_1380 = {_T_1262,_T_1300,_T_1338,_T_1376}; // @[Cat.scala 29:58]
-  wire [31:0] _T_1384 = {{16'd0}, _T_1380[31:16]}; // @[Bitwise.scala 103:31]
-  wire [31:0] _T_1386 = {_T_1380[15:0], 16'h0}; // @[Bitwise.scala 103:65]
-  wire [31:0] _T_1388 = _T_1386 & 32'hffff0000; // @[Bitwise.scala 103:75]
-  wire [31:0] _T_1389 = _T_1384 | _T_1388; // @[Bitwise.scala 103:39]
-  wire [31:0] _GEN_84 = {{8'd0}, _T_1389[31:8]}; // @[Bitwise.scala 103:31]
-  wire [31:0] _T_1394 = _GEN_84 & 32'hff00ff; // @[Bitwise.scala 103:31]
-  wire [31:0] _T_1396 = {_T_1389[23:0], 8'h0}; // @[Bitwise.scala 103:65]
-  wire [31:0] _T_1398 = _T_1396 & 32'hff00ff00; // @[Bitwise.scala 103:75]
-  wire [31:0] _T_1399 = _T_1394 | _T_1398; // @[Bitwise.scala 103:39]
-  wire [31:0] _GEN_85 = {{4'd0}, _T_1399[31:4]}; // @[Bitwise.scala 103:31]
-  wire [31:0] _T_1404 = _GEN_85 & 32'hf0f0f0f; // @[Bitwise.scala 103:31]
-  wire [31:0] _T_1406 = {_T_1399[27:0], 4'h0}; // @[Bitwise.scala 103:65]
-  wire [31:0] _T_1408 = _T_1406 & 32'hf0f0f0f0; // @[Bitwise.scala 103:75]
-  wire [31:0] _T_1409 = _T_1404 | _T_1408; // @[Bitwise.scala 103:39]
-  wire [31:0] _GEN_86 = {{2'd0}, _T_1409[31:2]}; // @[Bitwise.scala 103:31]
-  wire [31:0] _T_1414 = _GEN_86 & 32'h33333333; // @[Bitwise.scala 103:31]
-  wire [31:0] _T_1416 = {_T_1409[29:0], 2'h0}; // @[Bitwise.scala 103:65]
-  wire [31:0] _T_1418 = _T_1416 & 32'hcccccccc; // @[Bitwise.scala 103:75]
-  wire [31:0] _T_1419 = _T_1414 | _T_1418; // @[Bitwise.scala 103:39]
-  wire [31:0] _GEN_87 = {{1'd0}, _T_1419[31:1]}; // @[Bitwise.scala 103:31]
-  wire [31:0] _T_1424 = _GEN_87 & 32'h55555555; // @[Bitwise.scala 103:31]
-  wire [31:0] _T_1426 = {_T_1419[30:0], 1'h0}; // @[Bitwise.scala 103:65]
-  wire [31:0] _T_1428 = _T_1426 & 32'haaaaaaaa; // @[Bitwise.scala 103:75]
-  wire  _T_1430 = io_ldst_dual_m & io_lsu_pkt_m_valid; // @[lsu_dccm_ctl.scala 262:295]
-  wire  _T_1431 = _T_1430 & io_lsu_pkt_m_bits_store; // @[lsu_dccm_ctl.scala 262:316]
-  reg [31:0] _T_1435; // @[lib.scala 374:16]
-  wire  _T_1436 = io_lsu_stbuf_commit_any & dccm_wr_bypass_d_r_lo; // @[lsu_dccm_ctl.scala 263:105]
-  wire [7:0] store_byteen_ext_r = {{1'd0}, _T_998}; // @[lsu_dccm_ctl.scala 222:22]
-  wire  _T_1438 = ~store_byteen_ext_r[0]; // @[lsu_dccm_ctl.scala 263:131]
-  wire  _T_1439 = _T_1436 & _T_1438; // @[lsu_dccm_ctl.scala 263:129]
-  wire [7:0] _T_1443 = _T_1439 ? io_stbuf_data_any[7:0] : io_store_data_lo_r[7:0]; // @[lsu_dccm_ctl.scala 263:79]
-  wire [7:0] _T_1447 = {{4'd0}, _T_1443[7:4]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1449 = {_T_1443[3:0], 4'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_1451 = _T_1449 & 8'hf0; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_1452 = _T_1447 | _T_1451; // @[Bitwise.scala 103:39]
-  wire [7:0] _GEN_88 = {{2'd0}, _T_1452[7:2]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1457 = _GEN_88 & 8'h33; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1459 = {_T_1452[5:0], 2'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_1461 = _T_1459 & 8'hcc; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_1462 = _T_1457 | _T_1461; // @[Bitwise.scala 103:39]
-  wire [7:0] _GEN_89 = {{1'd0}, _T_1462[7:1]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1467 = _GEN_89 & 8'h55; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1469 = {_T_1462[6:0], 1'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_1471 = _T_1469 & 8'haa; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_1472 = _T_1467 | _T_1471; // @[Bitwise.scala 103:39]
-  wire  _T_1475 = ~store_byteen_ext_r[1]; // @[lsu_dccm_ctl.scala 263:131]
-  wire  _T_1476 = _T_1436 & _T_1475; // @[lsu_dccm_ctl.scala 263:129]
-  wire [7:0] _T_1480 = _T_1476 ? io_stbuf_data_any[15:8] : io_store_data_lo_r[15:8]; // @[lsu_dccm_ctl.scala 263:79]
-  wire [7:0] _T_1484 = {{4'd0}, _T_1480[7:4]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1486 = {_T_1480[3:0], 4'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_1488 = _T_1486 & 8'hf0; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_1489 = _T_1484 | _T_1488; // @[Bitwise.scala 103:39]
-  wire [7:0] _GEN_90 = {{2'd0}, _T_1489[7:2]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1494 = _GEN_90 & 8'h33; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1496 = {_T_1489[5:0], 2'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_1498 = _T_1496 & 8'hcc; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_1499 = _T_1494 | _T_1498; // @[Bitwise.scala 103:39]
-  wire [7:0] _GEN_91 = {{1'd0}, _T_1499[7:1]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1504 = _GEN_91 & 8'h55; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1506 = {_T_1499[6:0], 1'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_1508 = _T_1506 & 8'haa; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_1509 = _T_1504 | _T_1508; // @[Bitwise.scala 103:39]
-  wire  _T_1512 = ~store_byteen_ext_r[2]; // @[lsu_dccm_ctl.scala 263:131]
-  wire  _T_1513 = _T_1436 & _T_1512; // @[lsu_dccm_ctl.scala 263:129]
-  wire [7:0] _T_1517 = _T_1513 ? io_stbuf_data_any[23:16] : io_store_data_lo_r[23:16]; // @[lsu_dccm_ctl.scala 263:79]
-  wire [7:0] _T_1521 = {{4'd0}, _T_1517[7:4]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1523 = {_T_1517[3:0], 4'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_1525 = _T_1523 & 8'hf0; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_1526 = _T_1521 | _T_1525; // @[Bitwise.scala 103:39]
-  wire [7:0] _GEN_92 = {{2'd0}, _T_1526[7:2]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1531 = _GEN_92 & 8'h33; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1533 = {_T_1526[5:0], 2'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_1535 = _T_1533 & 8'hcc; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_1536 = _T_1531 | _T_1535; // @[Bitwise.scala 103:39]
-  wire [7:0] _GEN_93 = {{1'd0}, _T_1536[7:1]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1541 = _GEN_93 & 8'h55; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1543 = {_T_1536[6:0], 1'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_1545 = _T_1543 & 8'haa; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_1546 = _T_1541 | _T_1545; // @[Bitwise.scala 103:39]
-  wire  _T_1549 = ~store_byteen_ext_r[3]; // @[lsu_dccm_ctl.scala 263:131]
-  wire  _T_1550 = _T_1436 & _T_1549; // @[lsu_dccm_ctl.scala 263:129]
-  wire [7:0] _T_1554 = _T_1550 ? io_stbuf_data_any[31:24] : io_store_data_lo_r[31:24]; // @[lsu_dccm_ctl.scala 263:79]
-  wire [7:0] _T_1558 = {{4'd0}, _T_1554[7:4]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1560 = {_T_1554[3:0], 4'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_1562 = _T_1560 & 8'hf0; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_1563 = _T_1558 | _T_1562; // @[Bitwise.scala 103:39]
-  wire [7:0] _GEN_94 = {{2'd0}, _T_1563[7:2]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1568 = _GEN_94 & 8'h33; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1570 = {_T_1563[5:0], 2'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_1572 = _T_1570 & 8'hcc; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_1573 = _T_1568 | _T_1572; // @[Bitwise.scala 103:39]
-  wire [7:0] _GEN_95 = {{1'd0}, _T_1573[7:1]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1578 = _GEN_95 & 8'h55; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1580 = {_T_1573[6:0], 1'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_1582 = _T_1580 & 8'haa; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_1583 = _T_1578 | _T_1582; // @[Bitwise.scala 103:39]
-  wire [31:0] _T_1587 = {_T_1472,_T_1509,_T_1546,_T_1583}; // @[Cat.scala 29:58]
-  wire [31:0] _T_1591 = {{16'd0}, _T_1587[31:16]}; // @[Bitwise.scala 103:31]
-  wire [31:0] _T_1593 = {_T_1587[15:0], 16'h0}; // @[Bitwise.scala 103:65]
-  wire [31:0] _T_1595 = _T_1593 & 32'hffff0000; // @[Bitwise.scala 103:75]
-  wire [31:0] _T_1596 = _T_1591 | _T_1595; // @[Bitwise.scala 103:39]
-  wire [31:0] _GEN_96 = {{8'd0}, _T_1596[31:8]}; // @[Bitwise.scala 103:31]
-  wire [31:0] _T_1601 = _GEN_96 & 32'hff00ff; // @[Bitwise.scala 103:31]
-  wire [31:0] _T_1603 = {_T_1596[23:0], 8'h0}; // @[Bitwise.scala 103:65]
-  wire [31:0] _T_1605 = _T_1603 & 32'hff00ff00; // @[Bitwise.scala 103:75]
-  wire [31:0] _T_1606 = _T_1601 | _T_1605; // @[Bitwise.scala 103:39]
-  wire [31:0] _GEN_97 = {{4'd0}, _T_1606[31:4]}; // @[Bitwise.scala 103:31]
-  wire [31:0] _T_1611 = _GEN_97 & 32'hf0f0f0f; // @[Bitwise.scala 103:31]
-  wire [31:0] _T_1613 = {_T_1606[27:0], 4'h0}; // @[Bitwise.scala 103:65]
-  wire [31:0] _T_1615 = _T_1613 & 32'hf0f0f0f0; // @[Bitwise.scala 103:75]
-  wire [31:0] _T_1616 = _T_1611 | _T_1615; // @[Bitwise.scala 103:39]
-  wire [31:0] _GEN_98 = {{2'd0}, _T_1616[31:2]}; // @[Bitwise.scala 103:31]
-  wire [31:0] _T_1621 = _GEN_98 & 32'h33333333; // @[Bitwise.scala 103:31]
-  wire [31:0] _T_1623 = {_T_1616[29:0], 2'h0}; // @[Bitwise.scala 103:65]
-  wire [31:0] _T_1625 = _T_1623 & 32'hcccccccc; // @[Bitwise.scala 103:75]
-  wire [31:0] _T_1626 = _T_1621 | _T_1625; // @[Bitwise.scala 103:39]
-  wire [31:0] _GEN_99 = {{1'd0}, _T_1626[31:1]}; // @[Bitwise.scala 103:31]
-  wire [31:0] _T_1631 = _GEN_99 & 32'h55555555; // @[Bitwise.scala 103:31]
-  wire [31:0] _T_1633 = {_T_1626[30:0], 1'h0}; // @[Bitwise.scala 103:65]
-  wire [31:0] _T_1635 = _T_1633 & 32'haaaaaaaa; // @[Bitwise.scala 103:75]
-  wire  _T_1637 = io_lsu_stbuf_commit_any & dccm_wr_bypass_d_r_hi; // @[lsu_dccm_ctl.scala 264:105]
-  wire  _T_1639 = ~store_byteen_ext_r[4]; // @[lsu_dccm_ctl.scala 264:131]
-  wire  _T_1640 = _T_1637 & _T_1639; // @[lsu_dccm_ctl.scala 264:129]
-  wire [7:0] _T_1644 = _T_1640 ? io_stbuf_data_any[7:0] : io_store_data_hi_r[7:0]; // @[lsu_dccm_ctl.scala 264:79]
-  wire [7:0] _T_1648 = {{4'd0}, _T_1644[7:4]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1650 = {_T_1644[3:0], 4'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_1652 = _T_1650 & 8'hf0; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_1653 = _T_1648 | _T_1652; // @[Bitwise.scala 103:39]
-  wire [7:0] _GEN_100 = {{2'd0}, _T_1653[7:2]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1658 = _GEN_100 & 8'h33; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1660 = {_T_1653[5:0], 2'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_1662 = _T_1660 & 8'hcc; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_1663 = _T_1658 | _T_1662; // @[Bitwise.scala 103:39]
-  wire [7:0] _GEN_101 = {{1'd0}, _T_1663[7:1]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1668 = _GEN_101 & 8'h55; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1670 = {_T_1663[6:0], 1'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_1672 = _T_1670 & 8'haa; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_1673 = _T_1668 | _T_1672; // @[Bitwise.scala 103:39]
-  wire  _T_1676 = ~store_byteen_ext_r[5]; // @[lsu_dccm_ctl.scala 264:131]
-  wire  _T_1677 = _T_1637 & _T_1676; // @[lsu_dccm_ctl.scala 264:129]
-  wire [7:0] _T_1681 = _T_1677 ? io_stbuf_data_any[15:8] : io_store_data_hi_r[15:8]; // @[lsu_dccm_ctl.scala 264:79]
-  wire [7:0] _T_1685 = {{4'd0}, _T_1681[7:4]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1687 = {_T_1681[3:0], 4'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_1689 = _T_1687 & 8'hf0; // @[Bitwise.scala 103:75]
+  wire  _T_889 = ~lsu_double_ecc_error_r_ff; // @[lsu_dccm_ctl.scala 178:96]
+  wire  _T_891 = lsu_dccm_rden_d | io_dma_dccm_wen; // @[lsu_dccm_ctl.scala 179:75]
+  wire  _T_892 = _T_891 | io_ld_single_ecc_error_r_ff; // @[lsu_dccm_ctl.scala 179:93]
+  wire  _T_893 = ~_T_892; // @[lsu_dccm_ctl.scala 179:57]
+  wire  _T_896 = io_stbuf_addr_any[3:2] == io_lsu_addr_d[3:2]; // @[lsu_dccm_ctl.scala 180:95]
+  wire  _T_899 = io_stbuf_addr_any[3:2] == io_end_addr_d[3:2]; // @[lsu_dccm_ctl.scala 181:76]
+  wire  _T_900 = _T_896 | _T_899; // @[lsu_dccm_ctl.scala 180:171]
+  wire  _T_901 = ~_T_900; // @[lsu_dccm_ctl.scala 180:24]
+  wire  _T_902 = lsu_dccm_rden_d & _T_901; // @[lsu_dccm_ctl.scala 180:22]
+  wire  _T_903 = _T_893 | _T_902; // @[lsu_dccm_ctl.scala 179:124]
+  wire  _T_905 = io_dma_dccm_wen | io_lsu_stbuf_commit_any; // @[lsu_dccm_ctl.scala 185:41]
+  reg [15:0] ld_sec_addr_lo_r_ff; // @[Reg.scala 27:20]
+  reg [15:0] ld_sec_addr_hi_r_ff; // @[Reg.scala 27:20]
+  wire [15:0] _T_912 = ld_single_ecc_error_lo_r_ff ? ld_sec_addr_lo_r_ff : ld_sec_addr_hi_r_ff; // @[lsu_dccm_ctl.scala 189:8]
+  wire [15:0] _T_916 = io_dma_dccm_wen ? io_lsu_addr_d[15:0] : io_stbuf_addr_any; // @[lsu_dccm_ctl.scala 190:8]
+  wire [15:0] _T_922 = ld_single_ecc_error_hi_r_ff ? ld_sec_addr_hi_r_ff : ld_sec_addr_lo_r_ff; // @[lsu_dccm_ctl.scala 193:8]
+  wire [15:0] _T_926 = io_dma_dccm_wen ? io_end_addr_d : io_stbuf_addr_any; // @[lsu_dccm_ctl.scala 194:8]
+  wire [38:0] _T_934 = {io_sec_data_ecc_lo_r_ff,io_sec_data_lo_r_ff}; // @[Cat.scala 29:58]
+  wire [38:0] _T_937 = {io_sec_data_ecc_hi_r_ff,io_sec_data_hi_r_ff}; // @[Cat.scala 29:58]
+  wire [38:0] _T_938 = ld_single_ecc_error_lo_r_ff ? _T_934 : _T_937; // @[lsu_dccm_ctl.scala 200:8]
+  wire [38:0] _T_942 = {io_dma_dccm_wdata_ecc_lo,io_dma_dccm_wdata_lo}; // @[Cat.scala 29:58]
+  wire [38:0] _T_945 = {io_stbuf_ecc_any,io_stbuf_data_any}; // @[Cat.scala 29:58]
+  wire [38:0] _T_946 = io_dma_dccm_wen ? _T_942 : _T_945; // @[lsu_dccm_ctl.scala 202:8]
+  wire [38:0] _T_956 = ld_single_ecc_error_hi_r_ff ? _T_937 : _T_934; // @[lsu_dccm_ctl.scala 206:8]
+  wire [38:0] _T_960 = {io_dma_dccm_wdata_ecc_hi,io_dma_dccm_wdata_hi}; // @[Cat.scala 29:58]
+  wire [38:0] _T_964 = io_dma_dccm_wen ? _T_960 : _T_945; // @[lsu_dccm_ctl.scala 208:8]
+  wire [3:0] _T_980 = io_lsu_pkt_r_bits_store ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
+  wire [3:0] _T_982 = io_lsu_pkt_r_bits_by ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
+  wire [3:0] _T_983 = _T_982 & 4'h1; // @[lsu_dccm_ctl.scala 216:94]
+  wire [3:0] _T_985 = io_lsu_pkt_r_bits_half ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
+  wire [3:0] _T_986 = _T_985 & 4'h3; // @[lsu_dccm_ctl.scala 217:38]
+  wire [3:0] _T_987 = _T_983 | _T_986; // @[lsu_dccm_ctl.scala 216:107]
+  wire [3:0] _T_989 = io_lsu_pkt_r_bits_word ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
+  wire [3:0] _T_991 = _T_987 | _T_989; // @[lsu_dccm_ctl.scala 217:51]
+  wire [3:0] store_byteen_r = _T_980 & _T_991; // @[lsu_dccm_ctl.scala 216:58]
+  wire [6:0] _GEN_55 = {{3'd0}, store_byteen_r}; // @[lsu_dccm_ctl.scala 222:45]
+  wire [6:0] _T_997 = _GEN_55 << io_lsu_addr_r[1:0]; // @[lsu_dccm_ctl.scala 222:45]
+  wire  _T_1000 = io_stbuf_addr_any[15:2] == io_lsu_addr_m[15:2]; // @[lsu_dccm_ctl.scala 225:67]
+  wire  _T_1003 = io_stbuf_addr_any[15:2] == io_end_addr_m[15:2]; // @[lsu_dccm_ctl.scala 226:67]
+  wire  _T_1006 = io_stbuf_addr_any[15:2] == io_lsu_addr_r[15:2]; // @[lsu_dccm_ctl.scala 228:67]
+  wire  dccm_wr_bypass_d_r_lo = _T_1006 & io_addr_in_dccm_r; // @[lsu_dccm_ctl.scala 228:101]
+  wire [63:0] _T_1012 = {32'h0,io_store_data_r}; // @[Cat.scala 29:58]
+  wire [126:0] _GEN_57 = {{63'd0}, _T_1012}; // @[lsu_dccm_ctl.scala 243:72]
+  wire [126:0] _T_1015 = _GEN_57 << _T_818; // @[lsu_dccm_ctl.scala 243:72]
+  wire [63:0] store_data_pre_r = _T_1015[63:0]; // @[lsu_dccm_ctl.scala 243:29]
+  wire [31:0] store_data_pre_hi_r = store_data_pre_r[63:32]; // @[lsu_dccm_ctl.scala 244:48]
+  wire [31:0] store_data_pre_lo_r = store_data_pre_r[31:0]; // @[lsu_dccm_ctl.scala 245:48]
+  wire [7:0] store_byteen_ext_r = {{1'd0}, _T_997}; // @[lsu_dccm_ctl.scala 222:22]
+  reg  dccm_wren_Q; // @[lsu_dccm_ctl.scala 250:69]
+  reg  dccm_wr_bypass_d_m_lo_Q; // @[lsu_dccm_ctl.scala 252:69]
+  wire  _T_1021 = dccm_wren_Q & dccm_wr_bypass_d_m_lo_Q; // @[lsu_dccm_ctl.scala 246:162]
+  reg [31:0] dccm_wr_data_Q; // @[Reg.scala 27:20]
+  wire [7:0] _T_1025 = _T_1021 ? dccm_wr_data_Q[7:0] : io_sec_data_lo_r[7:0]; // @[lsu_dccm_ctl.scala 246:148]
+  wire [7:0] _T_1026 = store_byteen_ext_r[0] ? store_data_pre_lo_r[7:0] : _T_1025; // @[lsu_dccm_ctl.scala 246:79]
+  wire [7:0] _T_1030 = {{4'd0}, _T_1026[7:4]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1032 = {_T_1026[3:0], 4'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1034 = _T_1032 & 8'hf0; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1035 = _T_1030 | _T_1034; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_58 = {{2'd0}, _T_1035[7:2]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1040 = _GEN_58 & 8'h33; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1042 = {_T_1035[5:0], 2'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1044 = _T_1042 & 8'hcc; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1045 = _T_1040 | _T_1044; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_59 = {{1'd0}, _T_1045[7:1]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1050 = _GEN_59 & 8'h55; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1052 = {_T_1045[6:0], 1'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1054 = _T_1052 & 8'haa; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1055 = _T_1050 | _T_1054; // @[Bitwise.scala 103:39]
+  wire [7:0] _T_1063 = _T_1021 ? dccm_wr_data_Q[15:8] : io_sec_data_lo_r[15:8]; // @[lsu_dccm_ctl.scala 246:148]
+  wire [7:0] _T_1064 = store_byteen_ext_r[1] ? store_data_pre_lo_r[15:8] : _T_1063; // @[lsu_dccm_ctl.scala 246:79]
+  wire [7:0] _T_1068 = {{4'd0}, _T_1064[7:4]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1070 = {_T_1064[3:0], 4'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1072 = _T_1070 & 8'hf0; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1073 = _T_1068 | _T_1072; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_60 = {{2'd0}, _T_1073[7:2]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1078 = _GEN_60 & 8'h33; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1080 = {_T_1073[5:0], 2'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1082 = _T_1080 & 8'hcc; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1083 = _T_1078 | _T_1082; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_61 = {{1'd0}, _T_1083[7:1]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1088 = _GEN_61 & 8'h55; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1090 = {_T_1083[6:0], 1'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1092 = _T_1090 & 8'haa; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1093 = _T_1088 | _T_1092; // @[Bitwise.scala 103:39]
+  wire [7:0] _T_1101 = _T_1021 ? dccm_wr_data_Q[23:16] : io_sec_data_lo_r[23:16]; // @[lsu_dccm_ctl.scala 246:148]
+  wire [7:0] _T_1102 = store_byteen_ext_r[2] ? store_data_pre_lo_r[23:16] : _T_1101; // @[lsu_dccm_ctl.scala 246:79]
+  wire [7:0] _T_1106 = {{4'd0}, _T_1102[7:4]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1108 = {_T_1102[3:0], 4'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1110 = _T_1108 & 8'hf0; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1111 = _T_1106 | _T_1110; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_62 = {{2'd0}, _T_1111[7:2]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1116 = _GEN_62 & 8'h33; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1118 = {_T_1111[5:0], 2'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1120 = _T_1118 & 8'hcc; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1121 = _T_1116 | _T_1120; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_63 = {{1'd0}, _T_1121[7:1]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1126 = _GEN_63 & 8'h55; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1128 = {_T_1121[6:0], 1'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1130 = _T_1128 & 8'haa; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1131 = _T_1126 | _T_1130; // @[Bitwise.scala 103:39]
+  wire [7:0] _T_1139 = _T_1021 ? dccm_wr_data_Q[31:24] : io_sec_data_lo_r[31:24]; // @[lsu_dccm_ctl.scala 246:148]
+  wire [7:0] _T_1140 = store_byteen_ext_r[3] ? store_data_pre_lo_r[31:24] : _T_1139; // @[lsu_dccm_ctl.scala 246:79]
+  wire [7:0] _T_1144 = {{4'd0}, _T_1140[7:4]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1146 = {_T_1140[3:0], 4'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1148 = _T_1146 & 8'hf0; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1149 = _T_1144 | _T_1148; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_64 = {{2'd0}, _T_1149[7:2]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1154 = _GEN_64 & 8'h33; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1156 = {_T_1149[5:0], 2'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1158 = _T_1156 & 8'hcc; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1159 = _T_1154 | _T_1158; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_65 = {{1'd0}, _T_1159[7:1]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1164 = _GEN_65 & 8'h55; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1166 = {_T_1159[6:0], 1'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1168 = _T_1166 & 8'haa; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1169 = _T_1164 | _T_1168; // @[Bitwise.scala 103:39]
+  wire [31:0] _T_1173 = {_T_1055,_T_1093,_T_1131,_T_1169}; // @[Cat.scala 29:58]
+  wire [31:0] _T_1177 = {{16'd0}, _T_1173[31:16]}; // @[Bitwise.scala 103:31]
+  wire [31:0] _T_1179 = {_T_1173[15:0], 16'h0}; // @[Bitwise.scala 103:65]
+  wire [31:0] _T_1181 = _T_1179 & 32'hffff0000; // @[Bitwise.scala 103:75]
+  wire [31:0] _T_1182 = _T_1177 | _T_1181; // @[Bitwise.scala 103:39]
+  wire [31:0] _GEN_66 = {{8'd0}, _T_1182[31:8]}; // @[Bitwise.scala 103:31]
+  wire [31:0] _T_1187 = _GEN_66 & 32'hff00ff; // @[Bitwise.scala 103:31]
+  wire [31:0] _T_1189 = {_T_1182[23:0], 8'h0}; // @[Bitwise.scala 103:65]
+  wire [31:0] _T_1191 = _T_1189 & 32'hff00ff00; // @[Bitwise.scala 103:75]
+  wire [31:0] _T_1192 = _T_1187 | _T_1191; // @[Bitwise.scala 103:39]
+  wire [31:0] _GEN_67 = {{4'd0}, _T_1192[31:4]}; // @[Bitwise.scala 103:31]
+  wire [31:0] _T_1197 = _GEN_67 & 32'hf0f0f0f; // @[Bitwise.scala 103:31]
+  wire [31:0] _T_1199 = {_T_1192[27:0], 4'h0}; // @[Bitwise.scala 103:65]
+  wire [31:0] _T_1201 = _T_1199 & 32'hf0f0f0f0; // @[Bitwise.scala 103:75]
+  wire [31:0] _T_1202 = _T_1197 | _T_1201; // @[Bitwise.scala 103:39]
+  wire [31:0] _GEN_68 = {{2'd0}, _T_1202[31:2]}; // @[Bitwise.scala 103:31]
+  wire [31:0] _T_1207 = _GEN_68 & 32'h33333333; // @[Bitwise.scala 103:31]
+  wire [31:0] _T_1209 = {_T_1202[29:0], 2'h0}; // @[Bitwise.scala 103:65]
+  wire [31:0] _T_1211 = _T_1209 & 32'hcccccccc; // @[Bitwise.scala 103:75]
+  wire [31:0] _T_1212 = _T_1207 | _T_1211; // @[Bitwise.scala 103:39]
+  wire [31:0] _GEN_69 = {{1'd0}, _T_1212[31:1]}; // @[Bitwise.scala 103:31]
+  wire [31:0] _T_1217 = _GEN_69 & 32'h55555555; // @[Bitwise.scala 103:31]
+  wire [31:0] _T_1219 = {_T_1212[30:0], 1'h0}; // @[Bitwise.scala 103:65]
+  wire [31:0] _T_1221 = _T_1219 & 32'haaaaaaaa; // @[Bitwise.scala 103:75]
+  reg  dccm_wr_bypass_d_m_hi_Q; // @[lsu_dccm_ctl.scala 253:69]
+  wire  _T_1226 = dccm_wren_Q & dccm_wr_bypass_d_m_hi_Q; // @[lsu_dccm_ctl.scala 247:162]
+  wire [7:0] _T_1230 = _T_1226 ? dccm_wr_data_Q[7:0] : io_sec_data_hi_r[7:0]; // @[lsu_dccm_ctl.scala 247:148]
+  wire [7:0] _T_1231 = store_byteen_ext_r[4] ? store_data_pre_hi_r[7:0] : _T_1230; // @[lsu_dccm_ctl.scala 247:79]
+  wire [7:0] _T_1235 = {{4'd0}, _T_1231[7:4]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1237 = {_T_1231[3:0], 4'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1239 = _T_1237 & 8'hf0; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1240 = _T_1235 | _T_1239; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_70 = {{2'd0}, _T_1240[7:2]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1245 = _GEN_70 & 8'h33; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1247 = {_T_1240[5:0], 2'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1249 = _T_1247 & 8'hcc; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1250 = _T_1245 | _T_1249; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_71 = {{1'd0}, _T_1250[7:1]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1255 = _GEN_71 & 8'h55; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1257 = {_T_1250[6:0], 1'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1259 = _T_1257 & 8'haa; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1260 = _T_1255 | _T_1259; // @[Bitwise.scala 103:39]
+  wire [7:0] _T_1268 = _T_1226 ? dccm_wr_data_Q[15:8] : io_sec_data_hi_r[15:8]; // @[lsu_dccm_ctl.scala 247:148]
+  wire [7:0] _T_1269 = store_byteen_ext_r[5] ? store_data_pre_hi_r[15:8] : _T_1268; // @[lsu_dccm_ctl.scala 247:79]
+  wire [7:0] _T_1273 = {{4'd0}, _T_1269[7:4]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1275 = {_T_1269[3:0], 4'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1277 = _T_1275 & 8'hf0; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1278 = _T_1273 | _T_1277; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_72 = {{2'd0}, _T_1278[7:2]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1283 = _GEN_72 & 8'h33; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1285 = {_T_1278[5:0], 2'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1287 = _T_1285 & 8'hcc; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1288 = _T_1283 | _T_1287; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_73 = {{1'd0}, _T_1288[7:1]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1293 = _GEN_73 & 8'h55; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1295 = {_T_1288[6:0], 1'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1297 = _T_1295 & 8'haa; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1298 = _T_1293 | _T_1297; // @[Bitwise.scala 103:39]
+  wire [7:0] _T_1306 = _T_1226 ? dccm_wr_data_Q[23:16] : io_sec_data_hi_r[23:16]; // @[lsu_dccm_ctl.scala 247:148]
+  wire [7:0] _T_1307 = store_byteen_ext_r[6] ? store_data_pre_hi_r[23:16] : _T_1306; // @[lsu_dccm_ctl.scala 247:79]
+  wire [7:0] _T_1311 = {{4'd0}, _T_1307[7:4]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1313 = {_T_1307[3:0], 4'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1315 = _T_1313 & 8'hf0; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1316 = _T_1311 | _T_1315; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_74 = {{2'd0}, _T_1316[7:2]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1321 = _GEN_74 & 8'h33; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1323 = {_T_1316[5:0], 2'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1325 = _T_1323 & 8'hcc; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1326 = _T_1321 | _T_1325; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_75 = {{1'd0}, _T_1326[7:1]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1331 = _GEN_75 & 8'h55; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1333 = {_T_1326[6:0], 1'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1335 = _T_1333 & 8'haa; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1336 = _T_1331 | _T_1335; // @[Bitwise.scala 103:39]
+  wire [7:0] _T_1344 = _T_1226 ? dccm_wr_data_Q[31:24] : io_sec_data_hi_r[31:24]; // @[lsu_dccm_ctl.scala 247:148]
+  wire [7:0] _T_1345 = store_byteen_ext_r[7] ? store_data_pre_hi_r[31:24] : _T_1344; // @[lsu_dccm_ctl.scala 247:79]
+  wire [7:0] _T_1349 = {{4'd0}, _T_1345[7:4]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1351 = {_T_1345[3:0], 4'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1353 = _T_1351 & 8'hf0; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1354 = _T_1349 | _T_1353; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_76 = {{2'd0}, _T_1354[7:2]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1359 = _GEN_76 & 8'h33; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1361 = {_T_1354[5:0], 2'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1363 = _T_1361 & 8'hcc; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1364 = _T_1359 | _T_1363; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_77 = {{1'd0}, _T_1364[7:1]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1369 = _GEN_77 & 8'h55; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1371 = {_T_1364[6:0], 1'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1373 = _T_1371 & 8'haa; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1374 = _T_1369 | _T_1373; // @[Bitwise.scala 103:39]
+  wire [31:0] _T_1378 = {_T_1260,_T_1298,_T_1336,_T_1374}; // @[Cat.scala 29:58]
+  wire [31:0] _T_1382 = {{16'd0}, _T_1378[31:16]}; // @[Bitwise.scala 103:31]
+  wire [31:0] _T_1384 = {_T_1378[15:0], 16'h0}; // @[Bitwise.scala 103:65]
+  wire [31:0] _T_1386 = _T_1384 & 32'hffff0000; // @[Bitwise.scala 103:75]
+  wire [31:0] _T_1387 = _T_1382 | _T_1386; // @[Bitwise.scala 103:39]
+  wire [31:0] _GEN_78 = {{8'd0}, _T_1387[31:8]}; // @[Bitwise.scala 103:31]
+  wire [31:0] _T_1392 = _GEN_78 & 32'hff00ff; // @[Bitwise.scala 103:31]
+  wire [31:0] _T_1394 = {_T_1387[23:0], 8'h0}; // @[Bitwise.scala 103:65]
+  wire [31:0] _T_1396 = _T_1394 & 32'hff00ff00; // @[Bitwise.scala 103:75]
+  wire [31:0] _T_1397 = _T_1392 | _T_1396; // @[Bitwise.scala 103:39]
+  wire [31:0] _GEN_79 = {{4'd0}, _T_1397[31:4]}; // @[Bitwise.scala 103:31]
+  wire [31:0] _T_1402 = _GEN_79 & 32'hf0f0f0f; // @[Bitwise.scala 103:31]
+  wire [31:0] _T_1404 = {_T_1397[27:0], 4'h0}; // @[Bitwise.scala 103:65]
+  wire [31:0] _T_1406 = _T_1404 & 32'hf0f0f0f0; // @[Bitwise.scala 103:75]
+  wire [31:0] _T_1407 = _T_1402 | _T_1406; // @[Bitwise.scala 103:39]
+  wire [31:0] _GEN_80 = {{2'd0}, _T_1407[31:2]}; // @[Bitwise.scala 103:31]
+  wire [31:0] _T_1412 = _GEN_80 & 32'h33333333; // @[Bitwise.scala 103:31]
+  wire [31:0] _T_1414 = {_T_1407[29:0], 2'h0}; // @[Bitwise.scala 103:65]
+  wire [31:0] _T_1416 = _T_1414 & 32'hcccccccc; // @[Bitwise.scala 103:75]
+  wire [31:0] _T_1417 = _T_1412 | _T_1416; // @[Bitwise.scala 103:39]
+  wire [31:0] _GEN_81 = {{1'd0}, _T_1417[31:1]}; // @[Bitwise.scala 103:31]
+  wire [31:0] _T_1422 = _GEN_81 & 32'h55555555; // @[Bitwise.scala 103:31]
+  wire [31:0] _T_1424 = {_T_1417[30:0], 1'h0}; // @[Bitwise.scala 103:65]
+  wire [31:0] _T_1426 = _T_1424 & 32'haaaaaaaa; // @[Bitwise.scala 103:75]
+  wire  _T_1431 = io_lsu_stbuf_commit_any & dccm_wr_bypass_d_r_lo; // @[lsu_dccm_ctl.scala 248:174]
+  wire [7:0] _T_1439 = _T_1431 ? io_stbuf_data_any[7:0] : _T_1025; // @[lsu_dccm_ctl.scala 248:148]
+  wire [7:0] _T_1440 = store_byteen_ext_r[0] ? store_data_pre_lo_r[7:0] : _T_1439; // @[lsu_dccm_ctl.scala 248:79]
+  wire [7:0] _T_1444 = {{4'd0}, _T_1440[7:4]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1446 = {_T_1440[3:0], 4'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1448 = _T_1446 & 8'hf0; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1449 = _T_1444 | _T_1448; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_82 = {{2'd0}, _T_1449[7:2]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1454 = _GEN_82 & 8'h33; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1456 = {_T_1449[5:0], 2'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1458 = _T_1456 & 8'hcc; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1459 = _T_1454 | _T_1458; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_83 = {{1'd0}, _T_1459[7:1]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1464 = _GEN_83 & 8'h55; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1466 = {_T_1459[6:0], 1'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1468 = _T_1466 & 8'haa; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1469 = _T_1464 | _T_1468; // @[Bitwise.scala 103:39]
+  wire [7:0] _T_1481 = _T_1431 ? io_stbuf_data_any[15:8] : _T_1063; // @[lsu_dccm_ctl.scala 248:148]
+  wire [7:0] _T_1482 = store_byteen_ext_r[1] ? store_data_pre_lo_r[15:8] : _T_1481; // @[lsu_dccm_ctl.scala 248:79]
+  wire [7:0] _T_1486 = {{4'd0}, _T_1482[7:4]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1488 = {_T_1482[3:0], 4'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1490 = _T_1488 & 8'hf0; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1491 = _T_1486 | _T_1490; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_84 = {{2'd0}, _T_1491[7:2]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1496 = _GEN_84 & 8'h33; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1498 = {_T_1491[5:0], 2'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1500 = _T_1498 & 8'hcc; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1501 = _T_1496 | _T_1500; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_85 = {{1'd0}, _T_1501[7:1]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1506 = _GEN_85 & 8'h55; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1508 = {_T_1501[6:0], 1'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1510 = _T_1508 & 8'haa; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1511 = _T_1506 | _T_1510; // @[Bitwise.scala 103:39]
+  wire [7:0] _T_1523 = _T_1431 ? io_stbuf_data_any[23:16] : _T_1101; // @[lsu_dccm_ctl.scala 248:148]
+  wire [7:0] _T_1524 = store_byteen_ext_r[2] ? store_data_pre_lo_r[23:16] : _T_1523; // @[lsu_dccm_ctl.scala 248:79]
+  wire [7:0] _T_1528 = {{4'd0}, _T_1524[7:4]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1530 = {_T_1524[3:0], 4'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1532 = _T_1530 & 8'hf0; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1533 = _T_1528 | _T_1532; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_86 = {{2'd0}, _T_1533[7:2]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1538 = _GEN_86 & 8'h33; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1540 = {_T_1533[5:0], 2'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1542 = _T_1540 & 8'hcc; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1543 = _T_1538 | _T_1542; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_87 = {{1'd0}, _T_1543[7:1]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1548 = _GEN_87 & 8'h55; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1550 = {_T_1543[6:0], 1'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1552 = _T_1550 & 8'haa; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1553 = _T_1548 | _T_1552; // @[Bitwise.scala 103:39]
+  wire [7:0] _T_1565 = _T_1431 ? io_stbuf_data_any[31:24] : _T_1139; // @[lsu_dccm_ctl.scala 248:148]
+  wire [7:0] _T_1566 = store_byteen_ext_r[3] ? store_data_pre_lo_r[31:24] : _T_1565; // @[lsu_dccm_ctl.scala 248:79]
+  wire [7:0] _T_1570 = {{4'd0}, _T_1566[7:4]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1572 = {_T_1566[3:0], 4'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1574 = _T_1572 & 8'hf0; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1575 = _T_1570 | _T_1574; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_88 = {{2'd0}, _T_1575[7:2]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1580 = _GEN_88 & 8'h33; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1582 = {_T_1575[5:0], 2'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1584 = _T_1582 & 8'hcc; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1585 = _T_1580 | _T_1584; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_89 = {{1'd0}, _T_1585[7:1]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1590 = _GEN_89 & 8'h55; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1592 = {_T_1585[6:0], 1'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1594 = _T_1592 & 8'haa; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1595 = _T_1590 | _T_1594; // @[Bitwise.scala 103:39]
+  wire [31:0] _T_1599 = {_T_1469,_T_1511,_T_1553,_T_1595}; // @[Cat.scala 29:58]
+  wire [31:0] _T_1603 = {{16'd0}, _T_1599[31:16]}; // @[Bitwise.scala 103:31]
+  wire [31:0] _T_1605 = {_T_1599[15:0], 16'h0}; // @[Bitwise.scala 103:65]
+  wire [31:0] _T_1607 = _T_1605 & 32'hffff0000; // @[Bitwise.scala 103:75]
+  wire [31:0] _T_1608 = _T_1603 | _T_1607; // @[Bitwise.scala 103:39]
+  wire [31:0] _GEN_90 = {{8'd0}, _T_1608[31:8]}; // @[Bitwise.scala 103:31]
+  wire [31:0] _T_1613 = _GEN_90 & 32'hff00ff; // @[Bitwise.scala 103:31]
+  wire [31:0] _T_1615 = {_T_1608[23:0], 8'h0}; // @[Bitwise.scala 103:65]
+  wire [31:0] _T_1617 = _T_1615 & 32'hff00ff00; // @[Bitwise.scala 103:75]
+  wire [31:0] _T_1618 = _T_1613 | _T_1617; // @[Bitwise.scala 103:39]
+  wire [31:0] _GEN_91 = {{4'd0}, _T_1618[31:4]}; // @[Bitwise.scala 103:31]
+  wire [31:0] _T_1623 = _GEN_91 & 32'hf0f0f0f; // @[Bitwise.scala 103:31]
+  wire [31:0] _T_1625 = {_T_1618[27:0], 4'h0}; // @[Bitwise.scala 103:65]
+  wire [31:0] _T_1627 = _T_1625 & 32'hf0f0f0f0; // @[Bitwise.scala 103:75]
+  wire [31:0] _T_1628 = _T_1623 | _T_1627; // @[Bitwise.scala 103:39]
+  wire [31:0] _GEN_92 = {{2'd0}, _T_1628[31:2]}; // @[Bitwise.scala 103:31]
+  wire [31:0] _T_1633 = _GEN_92 & 32'h33333333; // @[Bitwise.scala 103:31]
+  wire [31:0] _T_1635 = {_T_1628[29:0], 2'h0}; // @[Bitwise.scala 103:65]
+  wire [31:0] _T_1637 = _T_1635 & 32'hcccccccc; // @[Bitwise.scala 103:75]
+  wire [31:0] _T_1638 = _T_1633 | _T_1637; // @[Bitwise.scala 103:39]
+  wire [31:0] _GEN_93 = {{1'd0}, _T_1638[31:1]}; // @[Bitwise.scala 103:31]
+  wire [31:0] _T_1643 = _GEN_93 & 32'h55555555; // @[Bitwise.scala 103:31]
+  wire [31:0] _T_1645 = {_T_1638[30:0], 1'h0}; // @[Bitwise.scala 103:65]
+  wire [31:0] _T_1647 = _T_1645 & 32'haaaaaaaa; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1660 = _T_1431 ? io_stbuf_data_any[7:0] : _T_1230; // @[lsu_dccm_ctl.scala 249:148]
+  wire [7:0] _T_1661 = store_byteen_ext_r[4] ? store_data_pre_hi_r[7:0] : _T_1660; // @[lsu_dccm_ctl.scala 249:79]
+  wire [7:0] _T_1665 = {{4'd0}, _T_1661[7:4]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1667 = {_T_1661[3:0], 4'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1669 = _T_1667 & 8'hf0; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1670 = _T_1665 | _T_1669; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_94 = {{2'd0}, _T_1670[7:2]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1675 = _GEN_94 & 8'h33; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1677 = {_T_1670[5:0], 2'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1679 = _T_1677 & 8'hcc; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1680 = _T_1675 | _T_1679; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_95 = {{1'd0}, _T_1680[7:1]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1685 = _GEN_95 & 8'h55; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1687 = {_T_1680[6:0], 1'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1689 = _T_1687 & 8'haa; // @[Bitwise.scala 103:75]
   wire [7:0] _T_1690 = _T_1685 | _T_1689; // @[Bitwise.scala 103:39]
-  wire [7:0] _GEN_102 = {{2'd0}, _T_1690[7:2]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1695 = _GEN_102 & 8'h33; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1697 = {_T_1690[5:0], 2'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_1699 = _T_1697 & 8'hcc; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_1700 = _T_1695 | _T_1699; // @[Bitwise.scala 103:39]
-  wire [7:0] _GEN_103 = {{1'd0}, _T_1700[7:1]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1705 = _GEN_103 & 8'h55; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1707 = {_T_1700[6:0], 1'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_1709 = _T_1707 & 8'haa; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_1710 = _T_1705 | _T_1709; // @[Bitwise.scala 103:39]
-  wire  _T_1713 = ~store_byteen_ext_r[6]; // @[lsu_dccm_ctl.scala 264:131]
-  wire  _T_1714 = _T_1637 & _T_1713; // @[lsu_dccm_ctl.scala 264:129]
-  wire [7:0] _T_1718 = _T_1714 ? io_stbuf_data_any[23:16] : io_store_data_hi_r[23:16]; // @[lsu_dccm_ctl.scala 264:79]
-  wire [7:0] _T_1722 = {{4'd0}, _T_1718[7:4]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1724 = {_T_1718[3:0], 4'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_1726 = _T_1724 & 8'hf0; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_1727 = _T_1722 | _T_1726; // @[Bitwise.scala 103:39]
-  wire [7:0] _GEN_104 = {{2'd0}, _T_1727[7:2]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1732 = _GEN_104 & 8'h33; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1734 = {_T_1727[5:0], 2'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_1736 = _T_1734 & 8'hcc; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_1737 = _T_1732 | _T_1736; // @[Bitwise.scala 103:39]
-  wire [7:0] _GEN_105 = {{1'd0}, _T_1737[7:1]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1742 = _GEN_105 & 8'h55; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1744 = {_T_1737[6:0], 1'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_1746 = _T_1744 & 8'haa; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_1747 = _T_1742 | _T_1746; // @[Bitwise.scala 103:39]
-  wire  _T_1750 = ~store_byteen_ext_r[7]; // @[lsu_dccm_ctl.scala 264:131]
-  wire  _T_1751 = _T_1637 & _T_1750; // @[lsu_dccm_ctl.scala 264:129]
-  wire [7:0] _T_1755 = _T_1751 ? io_stbuf_data_any[31:24] : io_store_data_hi_r[31:24]; // @[lsu_dccm_ctl.scala 264:79]
-  wire [7:0] _T_1759 = {{4'd0}, _T_1755[7:4]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1761 = {_T_1755[3:0], 4'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_1763 = _T_1761 & 8'hf0; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1702 = _T_1431 ? io_stbuf_data_any[15:8] : _T_1268; // @[lsu_dccm_ctl.scala 249:148]
+  wire [7:0] _T_1703 = store_byteen_ext_r[5] ? store_data_pre_hi_r[15:8] : _T_1702; // @[lsu_dccm_ctl.scala 249:79]
+  wire [7:0] _T_1707 = {{4'd0}, _T_1703[7:4]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1709 = {_T_1703[3:0], 4'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1711 = _T_1709 & 8'hf0; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1712 = _T_1707 | _T_1711; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_96 = {{2'd0}, _T_1712[7:2]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1717 = _GEN_96 & 8'h33; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1719 = {_T_1712[5:0], 2'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1721 = _T_1719 & 8'hcc; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1722 = _T_1717 | _T_1721; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_97 = {{1'd0}, _T_1722[7:1]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1727 = _GEN_97 & 8'h55; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1729 = {_T_1722[6:0], 1'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1731 = _T_1729 & 8'haa; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1732 = _T_1727 | _T_1731; // @[Bitwise.scala 103:39]
+  wire [7:0] _T_1744 = _T_1431 ? io_stbuf_data_any[23:16] : _T_1306; // @[lsu_dccm_ctl.scala 249:148]
+  wire [7:0] _T_1745 = store_byteen_ext_r[6] ? store_data_pre_hi_r[23:16] : _T_1744; // @[lsu_dccm_ctl.scala 249:79]
+  wire [7:0] _T_1749 = {{4'd0}, _T_1745[7:4]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1751 = {_T_1745[3:0], 4'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1753 = _T_1751 & 8'hf0; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1754 = _T_1749 | _T_1753; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_98 = {{2'd0}, _T_1754[7:2]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1759 = _GEN_98 & 8'h33; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1761 = {_T_1754[5:0], 2'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1763 = _T_1761 & 8'hcc; // @[Bitwise.scala 103:75]
   wire [7:0] _T_1764 = _T_1759 | _T_1763; // @[Bitwise.scala 103:39]
-  wire [7:0] _GEN_106 = {{2'd0}, _T_1764[7:2]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1769 = _GEN_106 & 8'h33; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1771 = {_T_1764[5:0], 2'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_1773 = _T_1771 & 8'hcc; // @[Bitwise.scala 103:75]
+  wire [7:0] _GEN_99 = {{1'd0}, _T_1764[7:1]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1769 = _GEN_99 & 8'h55; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1771 = {_T_1764[6:0], 1'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1773 = _T_1771 & 8'haa; // @[Bitwise.scala 103:75]
   wire [7:0] _T_1774 = _T_1769 | _T_1773; // @[Bitwise.scala 103:39]
-  wire [7:0] _GEN_107 = {{1'd0}, _T_1774[7:1]}; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1779 = _GEN_107 & 8'h55; // @[Bitwise.scala 103:31]
-  wire [7:0] _T_1781 = {_T_1774[6:0], 1'h0}; // @[Bitwise.scala 103:65]
-  wire [7:0] _T_1783 = _T_1781 & 8'haa; // @[Bitwise.scala 103:75]
-  wire [7:0] _T_1784 = _T_1779 | _T_1783; // @[Bitwise.scala 103:39]
-  wire [31:0] _T_1788 = {_T_1673,_T_1710,_T_1747,_T_1784}; // @[Cat.scala 29:58]
-  wire [31:0] _T_1792 = {{16'd0}, _T_1788[31:16]}; // @[Bitwise.scala 103:31]
-  wire [31:0] _T_1794 = {_T_1788[15:0], 16'h0}; // @[Bitwise.scala 103:65]
-  wire [31:0] _T_1796 = _T_1794 & 32'hffff0000; // @[Bitwise.scala 103:75]
-  wire [31:0] _T_1797 = _T_1792 | _T_1796; // @[Bitwise.scala 103:39]
-  wire [31:0] _GEN_108 = {{8'd0}, _T_1797[31:8]}; // @[Bitwise.scala 103:31]
-  wire [31:0] _T_1802 = _GEN_108 & 32'hff00ff; // @[Bitwise.scala 103:31]
-  wire [31:0] _T_1804 = {_T_1797[23:0], 8'h0}; // @[Bitwise.scala 103:65]
-  wire [31:0] _T_1806 = _T_1804 & 32'hff00ff00; // @[Bitwise.scala 103:75]
-  wire [31:0] _T_1807 = _T_1802 | _T_1806; // @[Bitwise.scala 103:39]
-  wire [31:0] _GEN_109 = {{4'd0}, _T_1807[31:4]}; // @[Bitwise.scala 103:31]
-  wire [31:0] _T_1812 = _GEN_109 & 32'hf0f0f0f; // @[Bitwise.scala 103:31]
-  wire [31:0] _T_1814 = {_T_1807[27:0], 4'h0}; // @[Bitwise.scala 103:65]
-  wire [31:0] _T_1816 = _T_1814 & 32'hf0f0f0f0; // @[Bitwise.scala 103:75]
-  wire [31:0] _T_1817 = _T_1812 | _T_1816; // @[Bitwise.scala 103:39]
-  wire [31:0] _GEN_110 = {{2'd0}, _T_1817[31:2]}; // @[Bitwise.scala 103:31]
-  wire [31:0] _T_1822 = _GEN_110 & 32'h33333333; // @[Bitwise.scala 103:31]
-  wire [31:0] _T_1824 = {_T_1817[29:0], 2'h0}; // @[Bitwise.scala 103:65]
-  wire [31:0] _T_1826 = _T_1824 & 32'hcccccccc; // @[Bitwise.scala 103:75]
-  wire [31:0] _T_1827 = _T_1822 | _T_1826; // @[Bitwise.scala 103:39]
-  wire [31:0] _GEN_111 = {{1'd0}, _T_1827[31:1]}; // @[Bitwise.scala 103:31]
-  wire [31:0] _T_1832 = _GEN_111 & 32'h55555555; // @[Bitwise.scala 103:31]
-  wire [31:0] _T_1834 = {_T_1827[30:0], 1'h0}; // @[Bitwise.scala 103:65]
-  wire [31:0] _T_1836 = _T_1834 & 32'haaaaaaaa; // @[Bitwise.scala 103:75]
-  wire [63:0] _T_1840 = {io_store_data_hi_r,io_store_data_lo_r}; // @[Cat.scala 29:58]
-  wire [3:0] _GEN_112 = {{2'd0}, io_lsu_addr_r[1:0]}; // @[lsu_dccm_ctl.scala 265:94]
-  wire [5:0] _T_1842 = 4'h8 * _GEN_112; // @[lsu_dccm_ctl.scala 265:94]
-  wire [63:0] _T_1843 = _T_1840 >> _T_1842; // @[lsu_dccm_ctl.scala 265:88]
-  wire [7:0] _T_1846 = store_byteen_r[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
-  wire [7:0] _T_1849 = store_byteen_r[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
-  wire [7:0] _T_1852 = store_byteen_r[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
-  wire [7:0] _T_1855 = store_byteen_r[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
-  wire [31:0] _T_1859 = {_T_1846,_T_1849,_T_1852,_T_1855}; // @[Cat.scala 29:58]
-  wire [31:0] _T_1863 = {{16'd0}, _T_1859[31:16]}; // @[Bitwise.scala 103:31]
-  wire [31:0] _T_1865 = {_T_1859[15:0], 16'h0}; // @[Bitwise.scala 103:65]
-  wire [31:0] _T_1867 = _T_1865 & 32'hffff0000; // @[Bitwise.scala 103:75]
-  wire [31:0] _T_1868 = _T_1863 | _T_1867; // @[Bitwise.scala 103:39]
-  wire [31:0] _GEN_113 = {{8'd0}, _T_1868[31:8]}; // @[Bitwise.scala 103:31]
-  wire [31:0] _T_1873 = _GEN_113 & 32'hff00ff; // @[Bitwise.scala 103:31]
-  wire [31:0] _T_1875 = {_T_1868[23:0], 8'h0}; // @[Bitwise.scala 103:65]
-  wire [31:0] _T_1877 = _T_1875 & 32'hff00ff00; // @[Bitwise.scala 103:75]
-  wire [31:0] _T_1878 = _T_1873 | _T_1877; // @[Bitwise.scala 103:39]
-  wire [31:0] _GEN_114 = {{4'd0}, _T_1878[31:4]}; // @[Bitwise.scala 103:31]
-  wire [31:0] _T_1883 = _GEN_114 & 32'hf0f0f0f; // @[Bitwise.scala 103:31]
-  wire [31:0] _T_1885 = {_T_1878[27:0], 4'h0}; // @[Bitwise.scala 103:65]
-  wire [31:0] _T_1887 = _T_1885 & 32'hf0f0f0f0; // @[Bitwise.scala 103:75]
-  wire [31:0] _T_1888 = _T_1883 | _T_1887; // @[Bitwise.scala 103:39]
-  wire [31:0] _GEN_115 = {{2'd0}, _T_1888[31:2]}; // @[Bitwise.scala 103:31]
-  wire [31:0] _T_1893 = _GEN_115 & 32'h33333333; // @[Bitwise.scala 103:31]
-  wire [31:0] _T_1895 = {_T_1888[29:0], 2'h0}; // @[Bitwise.scala 103:65]
-  wire [31:0] _T_1897 = _T_1895 & 32'hcccccccc; // @[Bitwise.scala 103:75]
-  wire [31:0] _T_1898 = _T_1893 | _T_1897; // @[Bitwise.scala 103:39]
-  wire [31:0] _GEN_116 = {{1'd0}, _T_1898[31:1]}; // @[Bitwise.scala 103:31]
-  wire [31:0] _T_1903 = _GEN_116 & 32'h55555555; // @[Bitwise.scala 103:31]
-  wire [31:0] _T_1905 = {_T_1898[30:0], 1'h0}; // @[Bitwise.scala 103:65]
-  wire [31:0] _T_1907 = _T_1905 & 32'haaaaaaaa; // @[Bitwise.scala 103:75]
-  wire [31:0] _T_1908 = _T_1903 | _T_1907; // @[Bitwise.scala 103:39]
-  wire [63:0] _GEN_117 = {{32'd0}, _T_1908}; // @[lsu_dccm_ctl.scala 265:115]
-  wire [63:0] _T_1909 = _T_1843 & _GEN_117; // @[lsu_dccm_ctl.scala 265:115]
-  wire  _T_1914 = io_lsu_pkt_r_valid & io_lsu_pkt_r_bits_store; // @[lsu_dccm_ctl.scala 272:58]
-  wire  _T_1915 = _T_1914 & io_addr_in_pic_r; // @[lsu_dccm_ctl.scala 272:84]
-  wire  _T_1916 = _T_1915 & io_lsu_commit_r; // @[lsu_dccm_ctl.scala 272:103]
-  wire  _T_1918 = io_lsu_pkt_d_valid & io_lsu_pkt_d_bits_load; // @[lsu_dccm_ctl.scala 273:58]
-  wire  _T_1920 = io_lsu_pkt_d_valid & io_lsu_pkt_d_bits_store; // @[lsu_dccm_ctl.scala 274:58]
-  wire [31:0] _T_1924 = {17'h0,io_lsu_addr_d[14:0]}; // @[Cat.scala 29:58]
-  wire [14:0] _T_1930 = io_dma_pic_wen ? io_dma_dccm_ctl_dma_mem_addr[14:0] : io_lsu_addr_r[14:0]; // @[lsu_dccm_ctl.scala 276:93]
-  wire [31:0] _T_1931 = {17'h0,_T_1930}; // @[Cat.scala 29:58]
-  reg  _T_1938; // @[lsu_dccm_ctl.scala 280:61]
-  rvclkhdr rvclkhdr ( // @[lib.scala 368:23]
+  wire [7:0] _T_1786 = _T_1431 ? io_stbuf_data_any[31:24] : _T_1344; // @[lsu_dccm_ctl.scala 249:148]
+  wire [7:0] _T_1787 = store_byteen_ext_r[7] ? store_data_pre_hi_r[31:24] : _T_1786; // @[lsu_dccm_ctl.scala 249:79]
+  wire [7:0] _T_1791 = {{4'd0}, _T_1787[7:4]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1793 = {_T_1787[3:0], 4'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1795 = _T_1793 & 8'hf0; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1796 = _T_1791 | _T_1795; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_100 = {{2'd0}, _T_1796[7:2]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1801 = _GEN_100 & 8'h33; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1803 = {_T_1796[5:0], 2'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1805 = _T_1803 & 8'hcc; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1806 = _T_1801 | _T_1805; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_101 = {{1'd0}, _T_1806[7:1]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1811 = _GEN_101 & 8'h55; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1813 = {_T_1806[6:0], 1'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1815 = _T_1813 & 8'haa; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1816 = _T_1811 | _T_1815; // @[Bitwise.scala 103:39]
+  wire [31:0] _T_1820 = {_T_1690,_T_1732,_T_1774,_T_1816}; // @[Cat.scala 29:58]
+  wire [31:0] _T_1824 = {{16'd0}, _T_1820[31:16]}; // @[Bitwise.scala 103:31]
+  wire [31:0] _T_1826 = {_T_1820[15:0], 16'h0}; // @[Bitwise.scala 103:65]
+  wire [31:0] _T_1828 = _T_1826 & 32'hffff0000; // @[Bitwise.scala 103:75]
+  wire [31:0] _T_1829 = _T_1824 | _T_1828; // @[Bitwise.scala 103:39]
+  wire [31:0] _GEN_102 = {{8'd0}, _T_1829[31:8]}; // @[Bitwise.scala 103:31]
+  wire [31:0] _T_1834 = _GEN_102 & 32'hff00ff; // @[Bitwise.scala 103:31]
+  wire [31:0] _T_1836 = {_T_1829[23:0], 8'h0}; // @[Bitwise.scala 103:65]
+  wire [31:0] _T_1838 = _T_1836 & 32'hff00ff00; // @[Bitwise.scala 103:75]
+  wire [31:0] _T_1839 = _T_1834 | _T_1838; // @[Bitwise.scala 103:39]
+  wire [31:0] _GEN_103 = {{4'd0}, _T_1839[31:4]}; // @[Bitwise.scala 103:31]
+  wire [31:0] _T_1844 = _GEN_103 & 32'hf0f0f0f; // @[Bitwise.scala 103:31]
+  wire [31:0] _T_1846 = {_T_1839[27:0], 4'h0}; // @[Bitwise.scala 103:65]
+  wire [31:0] _T_1848 = _T_1846 & 32'hf0f0f0f0; // @[Bitwise.scala 103:75]
+  wire [31:0] _T_1849 = _T_1844 | _T_1848; // @[Bitwise.scala 103:39]
+  wire [31:0] _GEN_104 = {{2'd0}, _T_1849[31:2]}; // @[Bitwise.scala 103:31]
+  wire [31:0] _T_1854 = _GEN_104 & 32'h33333333; // @[Bitwise.scala 103:31]
+  wire [31:0] _T_1856 = {_T_1849[29:0], 2'h0}; // @[Bitwise.scala 103:65]
+  wire [31:0] _T_1858 = _T_1856 & 32'hcccccccc; // @[Bitwise.scala 103:75]
+  wire [31:0] _T_1859 = _T_1854 | _T_1858; // @[Bitwise.scala 103:39]
+  wire [31:0] _GEN_105 = {{1'd0}, _T_1859[31:1]}; // @[Bitwise.scala 103:31]
+  wire [31:0] _T_1864 = _GEN_105 & 32'h55555555; // @[Bitwise.scala 103:31]
+  wire [31:0] _T_1866 = {_T_1859[30:0], 1'h0}; // @[Bitwise.scala 103:65]
+  wire [31:0] _T_1868 = _T_1866 & 32'haaaaaaaa; // @[Bitwise.scala 103:75]
+  wire  _T_1871 = io_lsu_stbuf_commit_any | io_clk_override; // @[lsu_dccm_ctl.scala 251:82]
+  reg [31:0] _T_1877; // @[lsu_dccm_ctl.scala 254:72]
+  wire  _T_1882 = io_lsu_pkt_r_valid & io_lsu_pkt_r_bits_store; // @[lsu_dccm_ctl.scala 272:58]
+  wire  _T_1883 = _T_1882 & io_addr_in_pic_r; // @[lsu_dccm_ctl.scala 272:84]
+  wire  _T_1884 = _T_1883 & io_lsu_commit_r; // @[lsu_dccm_ctl.scala 272:103]
+  wire  _T_1886 = io_lsu_pkt_d_valid & io_lsu_pkt_d_bits_load; // @[lsu_dccm_ctl.scala 273:58]
+  wire  _T_1888 = io_lsu_pkt_d_valid & io_lsu_pkt_d_bits_store; // @[lsu_dccm_ctl.scala 274:58]
+  wire [31:0] _T_1892 = {17'h0,io_lsu_addr_d[14:0]}; // @[Cat.scala 29:58]
+  wire [14:0] _T_1898 = io_dma_pic_wen ? io_dma_dccm_ctl_dma_mem_addr[14:0] : io_lsu_addr_r[14:0]; // @[lsu_dccm_ctl.scala 276:93]
+  wire [31:0] _T_1899 = {17'h0,_T_1898}; // @[Cat.scala 29:58]
+  reg  _T_1906; // @[lsu_dccm_ctl.scala 280:61]
+  reg  _T_1907; // @[lsu_dccm_ctl.scala 281:61]
+  wire  _T_1912 = io_ld_single_ecc_error_r | io_clk_override; // @[lsu_dccm_ctl.scala 285:90]
+  rvclkhdr rvclkhdr ( // @[lib.scala 390:23]
     .io_l1clk(rvclkhdr_io_l1clk),
     .io_clk(rvclkhdr_io_clk),
-    .io_en(rvclkhdr_io_en),
-    .io_scan_mode(rvclkhdr_io_scan_mode)
+    .io_en(rvclkhdr_io_en)
   );
-  rvclkhdr rvclkhdr_1 ( // @[lib.scala 368:23]
+  rvclkhdr rvclkhdr_1 ( // @[lib.scala 390:23]
     .io_l1clk(rvclkhdr_1_io_l1clk),
     .io_clk(rvclkhdr_1_io_clk),
-    .io_en(rvclkhdr_1_io_en),
-    .io_scan_mode(rvclkhdr_1_io_scan_mode)
+    .io_en(rvclkhdr_1_io_en)
   );
-  rvclkhdr rvclkhdr_2 ( // @[lib.scala 368:23]
+  rvclkhdr rvclkhdr_2 ( // @[lib.scala 390:23]
     .io_l1clk(rvclkhdr_2_io_l1clk),
     .io_clk(rvclkhdr_2_io_clk),
-    .io_en(rvclkhdr_2_io_en),
-    .io_scan_mode(rvclkhdr_2_io_scan_mode)
+    .io_en(rvclkhdr_2_io_en)
   );
-  rvclkhdr rvclkhdr_3 ( // @[lib.scala 368:23]
+  rvclkhdr rvclkhdr_3 ( // @[lib.scala 390:23]
     .io_l1clk(rvclkhdr_3_io_l1clk),
     .io_clk(rvclkhdr_3_io_clk),
-    .io_en(rvclkhdr_3_io_en),
-    .io_scan_mode(rvclkhdr_3_io_scan_mode)
+    .io_en(rvclkhdr_3_io_en)
   );
-  assign io_lsu_ld_data_corr_r = _T_817[31:0]; // @[lsu_dccm_ctl.scala 157:28]
+  rvclkhdr rvclkhdr_4 ( // @[lib.scala 390:23]
+    .io_l1clk(rvclkhdr_4_io_l1clk),
+    .io_clk(rvclkhdr_4_io_clk),
+    .io_en(rvclkhdr_4_io_en)
+  );
+  rvclkhdr rvclkhdr_5 ( // @[lib.scala 390:23]
+    .io_l1clk(rvclkhdr_5_io_l1clk),
+    .io_clk(rvclkhdr_5_io_clk),
+    .io_en(rvclkhdr_5_io_en)
+  );
+  rvclkhdr rvclkhdr_6 ( // @[lib.scala 390:23]
+    .io_l1clk(rvclkhdr_6_io_l1clk),
+    .io_clk(rvclkhdr_6_io_clk),
+    .io_en(rvclkhdr_6_io_en)
+  );
+  rvclkhdr rvclkhdr_7 ( // @[lib.scala 390:23]
+    .io_l1clk(rvclkhdr_7_io_l1clk),
+    .io_clk(rvclkhdr_7_io_clk),
+    .io_en(rvclkhdr_7_io_en)
+  );
+  rvclkhdr rvclkhdr_8 ( // @[lib.scala 390:23]
+    .io_l1clk(rvclkhdr_8_io_l1clk),
+    .io_clk(rvclkhdr_8_io_clk),
+    .io_en(rvclkhdr_8_io_en)
+  );
+  rvclkhdr rvclkhdr_9 ( // @[lib.scala 390:23]
+    .io_l1clk(rvclkhdr_9_io_l1clk),
+    .io_clk(rvclkhdr_9_io_clk),
+    .io_en(rvclkhdr_9_io_en)
+  );
+  assign io_dccm_rdata_hi_r = _T_14; // @[lsu_dccm_ctl.scala 129:27]
+  assign io_dccm_rdata_lo_r = _T_18; // @[lsu_dccm_ctl.scala 130:27]
+  assign io_dccm_data_ecc_hi_r = _T_22; // @[lsu_dccm_ctl.scala 131:27]
+  assign io_dccm_data_ecc_lo_r = _T_26; // @[lsu_dccm_ctl.scala 132:27]
+  assign io_lsu_ld_data_r = _T_819[31:0]; // @[lsu_dccm_ctl.scala 140:27]
+  assign io_lsu_ld_data_corr_r = _T_822[31:0]; // @[lsu_dccm_ctl.scala 141:27]
   assign io_dccm_rdata_hi_m = io_dccm_rd_data_hi[31:0]; // @[lsu_dccm_ctl.scala 268:27]
   assign io_dccm_rdata_lo_m = io_dccm_rd_data_lo[31:0]; // @[lsu_dccm_ctl.scala 267:27]
   assign io_dccm_data_ecc_hi_m = io_dccm_rd_data_hi[38:32]; // @[lsu_dccm_ctl.scala 270:27]
   assign io_dccm_data_ecc_lo_m = io_dccm_rd_data_lo[38:32]; // @[lsu_dccm_ctl.scala 269:27]
-  assign io_lsu_ld_data_m = _T_820[31:0]; // @[lsu_dccm_ctl.scala 158:28]
-  assign io_store_data_hi_r = _T_1435; // @[lsu_dccm_ctl.scala 262:29]
-  assign io_store_data_lo_r = _T_1224; // @[lsu_dccm_ctl.scala 261:29]
-  assign io_store_datafn_hi_r = _T_1832 | _T_1836; // @[lsu_dccm_ctl.scala 264:29]
-  assign io_store_datafn_lo_r = _T_1631 | _T_1635; // @[lsu_dccm_ctl.scala 263:29]
-  assign io_store_data_r = _T_1909[31:0]; // @[lsu_dccm_ctl.scala 265:29]
-  assign io_ld_single_ecc_error_r = _T_872 & _T_873; // @[lsu_dccm_ctl.scala 171:34]
-  assign io_ld_single_ecc_error_r_ff = _T_889 & _T_890; // @[lsu_dccm_ctl.scala 178:31]
+  assign io_store_data_hi_r = _T_1422 | _T_1426; // @[lsu_dccm_ctl.scala 247:29]
+  assign io_store_data_lo_r = _T_1217 | _T_1221; // @[lsu_dccm_ctl.scala 246:29]
+  assign io_store_datafn_hi_r = _T_1864 | _T_1868; // @[lsu_dccm_ctl.scala 249:29]
+  assign io_store_datafn_lo_r = _T_1643 | _T_1647; // @[lsu_dccm_ctl.scala 248:29]
+  assign io_store_data_r = _T_1877; // @[lsu_dccm_ctl.scala 254:29]
+  assign io_ld_single_ecc_error_r = _T_871 & _T_872; // @[lsu_dccm_ctl.scala 171:34]
+  assign io_ld_single_ecc_error_r_ff = _T_888 & _T_889; // @[lsu_dccm_ctl.scala 178:31]
   assign io_picm_mask_data_m = picm_rd_data_m[31:0]; // @[lsu_dccm_ctl.scala 277:27]
-  assign io_lsu_stbuf_commit_any = io_stbuf_reqvld_any & _T_904; // @[lsu_dccm_ctl.scala 179:31]
-  assign io_lsu_dccm_rden_m = _T_1938; // @[lsu_dccm_ctl.scala 280:24]
-  assign io_dma_dccm_ctl_dccm_dma_rvalid = _T & io_lsu_pkt_m_bits_dma; // @[lsu_dccm_ctl.scala 145:41]
-  assign io_dma_dccm_ctl_dccm_dma_ecc_error = io_lsu_double_ecc_error_m; // @[lsu_dccm_ctl.scala 146:41]
-  assign io_dma_dccm_ctl_dccm_dma_rtag = io_dma_mem_tag_m; // @[lsu_dccm_ctl.scala 148:41]
-  assign io_dma_dccm_ctl_dccm_dma_rdata = _T_4[63:0]; // @[lsu_dccm_ctl.scala 147:41]
-  assign io_dccm_wren = _T_906 | io_ld_single_ecc_error_r_ff; // @[lsu_dccm_ctl.scala 185:22]
+  assign io_lsu_stbuf_commit_any = io_stbuf_reqvld_any & _T_903; // @[lsu_dccm_ctl.scala 179:31]
+  assign io_lsu_dccm_rden_m = _T_1906; // @[lsu_dccm_ctl.scala 280:24]
+  assign io_lsu_dccm_rden_r = _T_1907; // @[lsu_dccm_ctl.scala 281:24]
+  assign io_dma_dccm_ctl_dccm_dma_rvalid = _T & io_lsu_pkt_r_bits_dma; // @[lsu_dccm_ctl.scala 124:40]
+  assign io_dma_dccm_ctl_dccm_dma_ecc_error = io_lsu_double_ecc_error_r; // @[lsu_dccm_ctl.scala 125:40]
+  assign io_dma_dccm_ctl_dccm_dma_rtag = _T_42; // @[lsu_dccm_ctl.scala 137:40]
+  assign io_dma_dccm_ctl_dccm_dma_rdata = io_ldst_dual_r ? lsu_rdata_corr_r : _T_4; // @[lsu_dccm_ctl.scala 126:40]
+  assign io_dccm_wren = _T_905 | io_ld_single_ecc_error_r_ff; // @[lsu_dccm_ctl.scala 185:22]
   assign io_dccm_rden = lsu_dccm_rden_d & io_addr_in_dccm_d; // @[lsu_dccm_ctl.scala 186:22]
-  assign io_dccm_wr_addr_lo = io_ld_single_ecc_error_r_ff ? _T_913 : _T_917; // @[lsu_dccm_ctl.scala 188:22]
-  assign io_dccm_wr_addr_hi = io_ld_single_ecc_error_r_ff ? _T_923 : _T_927; // @[lsu_dccm_ctl.scala 192:22]
+  assign io_dccm_wr_addr_lo = io_ld_single_ecc_error_r_ff ? _T_912 : _T_916; // @[lsu_dccm_ctl.scala 188:22]
+  assign io_dccm_wr_addr_hi = io_ld_single_ecc_error_r_ff ? _T_922 : _T_926; // @[lsu_dccm_ctl.scala 192:22]
   assign io_dccm_rd_addr_lo = io_lsu_addr_d[15:0]; // @[lsu_dccm_ctl.scala 196:22]
   assign io_dccm_rd_addr_hi = io_end_addr_d; // @[lsu_dccm_ctl.scala 197:22]
-  assign io_dccm_wr_data_lo = io_ld_single_ecc_error_r_ff ? _T_939 : _T_947; // @[lsu_dccm_ctl.scala 199:22]
-  assign io_dccm_wr_data_hi = io_ld_single_ecc_error_r_ff ? _T_957 : _T_965; // @[lsu_dccm_ctl.scala 205:22]
-  assign io_lsu_pic_picm_wren = _T_1916 | io_dma_pic_wen; // @[lsu_dccm_ctl.scala 272:35]
-  assign io_lsu_pic_picm_rden = _T_1918 & io_addr_in_pic_d; // @[lsu_dccm_ctl.scala 273:35]
-  assign io_lsu_pic_picm_mken = _T_1920 & io_addr_in_pic_d; // @[lsu_dccm_ctl.scala 274:35]
-  assign io_lsu_pic_picm_rdaddr = 32'hf00c0000 | _T_1924; // @[lsu_dccm_ctl.scala 275:35]
-  assign io_lsu_pic_picm_wraddr = 32'hf00c0000 | _T_1931; // @[lsu_dccm_ctl.scala 276:35]
+  assign io_dccm_wr_data_lo = io_ld_single_ecc_error_r_ff ? _T_938 : _T_946; // @[lsu_dccm_ctl.scala 199:22]
+  assign io_dccm_wr_data_hi = io_ld_single_ecc_error_r_ff ? _T_956 : _T_964; // @[lsu_dccm_ctl.scala 205:22]
+  assign io_lsu_pic_picm_wren = _T_1884 | io_dma_pic_wen; // @[lsu_dccm_ctl.scala 272:35]
+  assign io_lsu_pic_picm_rden = _T_1886 & io_addr_in_pic_d; // @[lsu_dccm_ctl.scala 273:35]
+  assign io_lsu_pic_picm_mken = _T_1888 & io_addr_in_pic_d; // @[lsu_dccm_ctl.scala 274:35]
+  assign io_lsu_pic_picm_rdaddr = 32'hf00c0000 | _T_1892; // @[lsu_dccm_ctl.scala 275:35]
+  assign io_lsu_pic_picm_wraddr = 32'hf00c0000 | _T_1899; // @[lsu_dccm_ctl.scala 276:35]
   assign io_lsu_pic_picm_wr_data = io_dma_pic_wen ? io_dma_dccm_ctl_dma_mem_wdata[31:0] : io_store_datafn_lo_r; // @[lsu_dccm_ctl.scala 278:35]
-  assign rvclkhdr_io_clk = clock; // @[lib.scala 370:18]
-  assign rvclkhdr_io_en = _T_813 | io_clk_override; // @[lib.scala 371:17]
-  assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
-  assign rvclkhdr_1_io_clk = clock; // @[lib.scala 370:18]
-  assign rvclkhdr_1_io_en = _T_1431 | io_clk_override; // @[lib.scala 371:17]
-  assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
-  assign rvclkhdr_2_io_clk = clock; // @[lib.scala 370:18]
-  assign rvclkhdr_2_io_en = io_ld_single_ecc_error_r | io_clk_override; // @[lib.scala 371:17]
-  assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
-  assign rvclkhdr_3_io_clk = clock; // @[lib.scala 370:18]
-  assign rvclkhdr_3_io_en = io_ld_single_ecc_error_r | io_clk_override; // @[lib.scala 371:17]
-  assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
+  assign rvclkhdr_io_clk = clock; // @[lib.scala 392:18]
+  assign rvclkhdr_io_en = _T_10 | io_clk_override; // @[lib.scala 393:17]
+  assign rvclkhdr_1_io_clk = clock; // @[lib.scala 392:18]
+  assign rvclkhdr_1_io_en = io_lsu_dccm_rden_m | io_clk_override; // @[lib.scala 393:17]
+  assign rvclkhdr_2_io_clk = clock; // @[lib.scala 392:18]
+  assign rvclkhdr_2_io_en = io_lsu_dccm_rden_m | io_clk_override; // @[lib.scala 393:17]
+  assign rvclkhdr_3_io_clk = clock; // @[lib.scala 392:18]
+  assign rvclkhdr_3_io_en = io_lsu_dccm_rden_m | io_clk_override; // @[lib.scala 393:17]
+  assign rvclkhdr_4_io_clk = clock; // @[lib.scala 392:18]
+  assign rvclkhdr_4_io_en = _T_8 | io_clk_override; // @[lib.scala 393:17]
+  assign rvclkhdr_5_io_clk = clock; // @[lib.scala 392:18]
+  assign rvclkhdr_5_io_en = _T_8 | io_clk_override; // @[lib.scala 393:17]
+  assign rvclkhdr_6_io_clk = clock; // @[lib.scala 392:18]
+  assign rvclkhdr_6_io_en = io_addr_in_pic_m | io_clk_override; // @[lib.scala 393:17]
+  assign rvclkhdr_7_io_clk = clock; // @[lib.scala 392:18]
+  assign rvclkhdr_7_io_en = io_lsu_stbuf_commit_any | io_clk_override; // @[lib.scala 393:17]
+  assign rvclkhdr_8_io_clk = clock; // @[lib.scala 392:18]
+  assign rvclkhdr_8_io_en = io_ld_single_ecc_error_r | io_clk_override; // @[lib.scala 393:17]
+  assign rvclkhdr_9_io_clk = clock; // @[lib.scala 392:18]
+  assign rvclkhdr_9_io_en = io_ld_single_ecc_error_r | io_clk_override; // @[lib.scala 393:17]
 `ifdef RANDOMIZE_GARBAGE_ASSIGN
 `define RANDOMIZE
 `endif
@@ -2415,27 +2415,75 @@ initial begin
       `endif
     `endif
 `ifdef RANDOMIZE_REG_INIT
-  _RAND_0 = {2{`RANDOM}};
-  _T_817 = _RAND_0[63:0];
+  _RAND_0 = {1{`RANDOM}};
+  _T_28 = _RAND_0[7:0];
   _RAND_1 = {1{`RANDOM}};
-  ld_single_ecc_error_lo_r_ff = _RAND_1[0:0];
+  _T_31 = _RAND_1[31:0];
   _RAND_2 = {1{`RANDOM}};
-  ld_single_ecc_error_hi_r_ff = _RAND_2[0:0];
+  _T_34 = _RAND_2[31:0];
   _RAND_3 = {1{`RANDOM}};
-  lsu_double_ecc_error_r_ff = _RAND_3[0:0];
+  picm_rd_data_r_32 = _RAND_3[31:0];
   _RAND_4 = {1{`RANDOM}};
-  ld_sec_addr_lo_r_ff = _RAND_4[15:0];
+  _T_14 = _RAND_4[31:0];
   _RAND_5 = {1{`RANDOM}};
-  ld_sec_addr_hi_r_ff = _RAND_5[15:0];
+  _T_18 = _RAND_5[31:0];
   _RAND_6 = {1{`RANDOM}};
-  _T_1224 = _RAND_6[31:0];
+  _T_22 = _RAND_6[6:0];
   _RAND_7 = {1{`RANDOM}};
-  _T_1435 = _RAND_7[31:0];
+  _T_26 = _RAND_7[6:0];
   _RAND_8 = {1{`RANDOM}};
-  _T_1938 = _RAND_8[0:0];
+  _T_42 = _RAND_8[2:0];
+  _RAND_9 = {1{`RANDOM}};
+  ld_single_ecc_error_lo_r_ff = _RAND_9[0:0];
+  _RAND_10 = {1{`RANDOM}};
+  ld_single_ecc_error_hi_r_ff = _RAND_10[0:0];
+  _RAND_11 = {1{`RANDOM}};
+  lsu_double_ecc_error_r_ff = _RAND_11[0:0];
+  _RAND_12 = {1{`RANDOM}};
+  ld_sec_addr_lo_r_ff = _RAND_12[15:0];
+  _RAND_13 = {1{`RANDOM}};
+  ld_sec_addr_hi_r_ff = _RAND_13[15:0];
+  _RAND_14 = {1{`RANDOM}};
+  dccm_wren_Q = _RAND_14[0:0];
+  _RAND_15 = {1{`RANDOM}};
+  dccm_wr_bypass_d_m_lo_Q = _RAND_15[0:0];
+  _RAND_16 = {1{`RANDOM}};
+  dccm_wr_data_Q = _RAND_16[31:0];
+  _RAND_17 = {1{`RANDOM}};
+  dccm_wr_bypass_d_m_hi_Q = _RAND_17[0:0];
+  _RAND_18 = {1{`RANDOM}};
+  _T_1877 = _RAND_18[31:0];
+  _RAND_19 = {1{`RANDOM}};
+  _T_1906 = _RAND_19[0:0];
+  _RAND_20 = {1{`RANDOM}};
+  _T_1907 = _RAND_20[0:0];
 `endif // RANDOMIZE_REG_INIT
   if (reset) begin
-    _T_817 = 64'h0;
+    _T_28 = 8'h0;
+  end
+  if (reset) begin
+    _T_31 = 32'h0;
+  end
+  if (reset) begin
+    _T_34 = 32'h0;
+  end
+  if (reset) begin
+    picm_rd_data_r_32 = 32'h0;
+  end
+  if (reset) begin
+    _T_14 = 32'h0;
+  end
+  if (reset) begin
+    _T_18 = 32'h0;
+  end
+  if (reset) begin
+    _T_22 = 7'h0;
+  end
+  if (reset) begin
+    _T_26 = 7'h0;
+  end
+  if (reset) begin
+    _T_42 = 3'h0;
   end
   if (reset) begin
     ld_single_ecc_error_lo_r_ff = 1'h0;
@@ -2453,13 +2501,25 @@ initial begin
     ld_sec_addr_hi_r_ff = 16'h0;
   end
   if (reset) begin
-    _T_1224 = 32'h0;
+    dccm_wren_Q = 1'h0;
   end
   if (reset) begin
-    _T_1435 = 32'h0;
+    dccm_wr_bypass_d_m_lo_Q = 1'h0;
   end
   if (reset) begin
-    _T_1938 = 1'h0;
+    dccm_wr_data_Q = 32'h0;
+  end
+  if (reset) begin
+    dccm_wr_bypass_d_m_hi_Q = 1'h0;
+  end
+  if (reset) begin
+    _T_1877 = 32'h0;
+  end
+  if (reset) begin
+    _T_1906 = 1'h0;
+  end
+  if (reset) begin
+    _T_1907 = 1'h0;
   end
   `endif // RANDOMIZE
 end // initial
@@ -2467,25 +2527,81 @@ end // initial
 `FIRRTL_AFTER_INITIAL
 `endif
 `endif // SYNTHESIS
-  always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
+  always @(posedge io_lsu_c2_r_clk or posedge reset) begin
     if (reset) begin
-      _T_817 <= 64'h0;
+      _T_28 <= 8'h0;
     end else begin
-      _T_817 <= lsu_rdata_corr_m >> _T_819;
+      _T_28 <= {io_stbuf_fwdbyteen_hi_m,io_stbuf_fwdbyteen_lo_m};
+    end
+  end
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      _T_31 <= 32'h0;
+    end else if (stbuf_fwddata_en) begin
+      _T_31 <= io_stbuf_fwddata_hi_m;
+    end
+  end
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      _T_34 <= 32'h0;
+    end else if (stbuf_fwddata_en) begin
+      _T_34 <= io_stbuf_fwddata_lo_m;
+    end
+  end
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      picm_rd_data_r_32 <= 32'h0;
+    end else if (_T_37) begin
+      picm_rd_data_r_32 <= picm_rd_data_m[31:0];
+    end
+  end
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      _T_14 <= 32'h0;
+    end else if (_T_11) begin
+      _T_14 <= io_dccm_rdata_hi_m;
+    end
+  end
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      _T_18 <= 32'h0;
+    end else if (_T_15) begin
+      _T_18 <= io_dccm_rdata_lo_m;
+    end
+  end
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      _T_22 <= 7'h0;
+    end else if (_T_15) begin
+      _T_22 <= io_dccm_data_ecc_hi_m;
+    end
+  end
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      _T_26 <= 7'h0;
+    end else if (_T_15) begin
+      _T_26 <= io_dccm_data_ecc_lo_m;
+    end
+  end
+  always @(posedge io_lsu_c1_r_clk or posedge reset) begin
+    if (reset) begin
+      _T_42 <= 3'h0;
+    end else begin
+      _T_42 <= io_dma_mem_tag_m;
     end
   end
   always @(posedge io_lsu_free_c2_clk or posedge reset) begin
     if (reset) begin
       ld_single_ecc_error_lo_r_ff <= 1'h0;
     end else begin
-      ld_single_ecc_error_lo_r_ff <= _T_876 & _T_877;
+      ld_single_ecc_error_lo_r_ff <= _T_875 & _T_876;
     end
   end
   always @(posedge io_lsu_free_c2_clk or posedge reset) begin
     if (reset) begin
       ld_single_ecc_error_hi_r_ff <= 1'h0;
     end else begin
-      ld_single_ecc_error_hi_r_ff <= _T_879 & _T_880;
+      ld_single_ecc_error_hi_r_ff <= _T_878 & _T_879;
     end
   end
   always @(posedge io_lsu_free_c2_clk or posedge reset) begin
@@ -2495,39 +2611,67 @@ end // initial
       lsu_double_ecc_error_r_ff <= io_lsu_double_ecc_error_r;
     end
   end
-  always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin
+  always @(posedge clock or posedge reset) begin
     if (reset) begin
       ld_sec_addr_lo_r_ff <= 16'h0;
-    end else begin
+    end else if (_T_1912) begin
       ld_sec_addr_lo_r_ff <= io_lsu_addr_r[15:0];
     end
   end
-  always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
+  always @(posedge clock or posedge reset) begin
     if (reset) begin
       ld_sec_addr_hi_r_ff <= 16'h0;
-    end else begin
+    end else if (_T_1912) begin
       ld_sec_addr_hi_r_ff <= io_end_addr_r;
     end
   end
+  always @(posedge io_lsu_free_c2_clk or posedge reset) begin
+    if (reset) begin
+      dccm_wren_Q <= 1'h0;
+    end else begin
+      dccm_wren_Q <= io_lsu_stbuf_commit_any;
+    end
+  end
+  always @(posedge io_lsu_free_c2_clk or posedge reset) begin
+    if (reset) begin
+      dccm_wr_bypass_d_m_lo_Q <= 1'h0;
+    end else begin
+      dccm_wr_bypass_d_m_lo_Q <= _T_1000 & io_addr_in_dccm_m;
+    end
+  end
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      dccm_wr_data_Q <= 32'h0;
+    end else if (_T_1871) begin
+      dccm_wr_data_Q <= io_stbuf_data_any;
+    end
+  end
+  always @(posedge io_lsu_free_c2_clk or posedge reset) begin
+    if (reset) begin
+      dccm_wr_bypass_d_m_hi_Q <= 1'h0;
+    end else begin
+      dccm_wr_bypass_d_m_hi_Q <= _T_1003 & io_addr_in_dccm_m;
+    end
+  end
   always @(posedge io_lsu_store_c1_r_clk or posedge reset) begin
     if (reset) begin
-      _T_1224 <= 32'h0;
+      _T_1877 <= 32'h0;
     end else begin
-      _T_1224 <= _T_1218 | _T_1222;
-    end
-  end
-  always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin
-    if (reset) begin
-      _T_1435 <= 32'h0;
-    end else begin
-      _T_1435 <= _T_1424 | _T_1428;
+      _T_1877 <= io_store_data_m;
     end
   end
   always @(posedge io_lsu_c2_m_clk or posedge reset) begin
     if (reset) begin
-      _T_1938 <= 1'h0;
+      _T_1906 <= 1'h0;
     end else begin
-      _T_1938 <= _T_888 & io_addr_in_dccm_d;
+      _T_1906 <= _T_887 & io_addr_in_dccm_d;
+    end
+  end
+  always @(posedge io_lsu_c2_r_clk or posedge reset) begin
+    if (reset) begin
+      _T_1907 <= 1'h0;
+    end else begin
+      _T_1907 <= io_lsu_dccm_rden_m;
     end
   end
 endmodule
@@ -2563,7 +2707,6 @@ module lsu_stbuf(
   input         io_ldst_dual_r,
   input         io_addr_in_dccm_m,
   input         io_addr_in_dccm_r,
-  input         io_scan_mode,
   output        io_stbuf_reqvld_any,
   output        io_stbuf_reqvld_flushed_any,
   output [15:0] io_stbuf_addr_any,
@@ -2600,50 +2743,42 @@ module lsu_stbuf(
   reg [31:0] _RAND_20;
   reg [31:0] _RAND_21;
 `endif // RANDOMIZE_REG_INIT
-  wire  rvclkhdr_io_l1clk; // @[lib.scala 368:23]
-  wire  rvclkhdr_io_clk; // @[lib.scala 368:23]
-  wire  rvclkhdr_io_en; // @[lib.scala 368:23]
-  wire  rvclkhdr_io_scan_mode; // @[lib.scala 368:23]
-  wire  rvclkhdr_1_io_l1clk; // @[lib.scala 368:23]
-  wire  rvclkhdr_1_io_clk; // @[lib.scala 368:23]
-  wire  rvclkhdr_1_io_en; // @[lib.scala 368:23]
-  wire  rvclkhdr_1_io_scan_mode; // @[lib.scala 368:23]
-  wire  rvclkhdr_2_io_l1clk; // @[lib.scala 368:23]
-  wire  rvclkhdr_2_io_clk; // @[lib.scala 368:23]
-  wire  rvclkhdr_2_io_en; // @[lib.scala 368:23]
-  wire  rvclkhdr_2_io_scan_mode; // @[lib.scala 368:23]
-  wire  rvclkhdr_3_io_l1clk; // @[lib.scala 368:23]
-  wire  rvclkhdr_3_io_clk; // @[lib.scala 368:23]
-  wire  rvclkhdr_3_io_en; // @[lib.scala 368:23]
-  wire  rvclkhdr_3_io_scan_mode; // @[lib.scala 368:23]
-  wire  rvclkhdr_4_io_l1clk; // @[lib.scala 368:23]
-  wire  rvclkhdr_4_io_clk; // @[lib.scala 368:23]
-  wire  rvclkhdr_4_io_en; // @[lib.scala 368:23]
-  wire  rvclkhdr_4_io_scan_mode; // @[lib.scala 368:23]
-  wire  rvclkhdr_5_io_l1clk; // @[lib.scala 368:23]
-  wire  rvclkhdr_5_io_clk; // @[lib.scala 368:23]
-  wire  rvclkhdr_5_io_en; // @[lib.scala 368:23]
-  wire  rvclkhdr_5_io_scan_mode; // @[lib.scala 368:23]
-  wire  rvclkhdr_6_io_l1clk; // @[lib.scala 368:23]
-  wire  rvclkhdr_6_io_clk; // @[lib.scala 368:23]
-  wire  rvclkhdr_6_io_en; // @[lib.scala 368:23]
-  wire  rvclkhdr_6_io_scan_mode; // @[lib.scala 368:23]
-  wire  rvclkhdr_7_io_l1clk; // @[lib.scala 368:23]
-  wire  rvclkhdr_7_io_clk; // @[lib.scala 368:23]
-  wire  rvclkhdr_7_io_en; // @[lib.scala 368:23]
-  wire  rvclkhdr_7_io_scan_mode; // @[lib.scala 368:23]
+  wire  rvclkhdr_io_l1clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_io_clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_io_en; // @[lib.scala 390:23]
+  wire  rvclkhdr_1_io_l1clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_1_io_clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_1_io_en; // @[lib.scala 390:23]
+  wire  rvclkhdr_2_io_l1clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_2_io_clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_2_io_en; // @[lib.scala 390:23]
+  wire  rvclkhdr_3_io_l1clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_3_io_clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_3_io_en; // @[lib.scala 390:23]
+  wire  rvclkhdr_4_io_l1clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_4_io_clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_4_io_en; // @[lib.scala 390:23]
+  wire  rvclkhdr_5_io_l1clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_5_io_clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_5_io_en; // @[lib.scala 390:23]
+  wire  rvclkhdr_6_io_l1clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_6_io_clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_6_io_en; // @[lib.scala 390:23]
+  wire  rvclkhdr_7_io_l1clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_7_io_clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_7_io_en; // @[lib.scala 390:23]
   wire [1:0] _T_5 = io_lsu_pkt_r_bits_half ? 2'h3 : 2'h0; // @[Mux.scala 27:72]
   wire [3:0] _T_6 = io_lsu_pkt_r_bits_word ? 4'hf : 4'h0; // @[Mux.scala 27:72]
   wire [7:0] _T_7 = io_lsu_pkt_r_bits_dword ? 8'hff : 8'h0; // @[Mux.scala 27:72]
-  wire [1:0] _GEN_10 = {{1'd0}, io_lsu_pkt_r_bits_by}; // @[Mux.scala 27:72]
-  wire [1:0] _T_8 = _GEN_10 | _T_5; // @[Mux.scala 27:72]
-  wire [3:0] _GEN_11 = {{2'd0}, _T_8}; // @[Mux.scala 27:72]
-  wire [3:0] _T_9 = _GEN_11 | _T_6; // @[Mux.scala 27:72]
-  wire [7:0] _GEN_12 = {{4'd0}, _T_9}; // @[Mux.scala 27:72]
-  wire [7:0] ldst_byteen_r = _GEN_12 | _T_7; // @[Mux.scala 27:72]
+  wire [1:0] _GEN_18 = {{1'd0}, io_lsu_pkt_r_bits_by}; // @[Mux.scala 27:72]
+  wire [1:0] _T_8 = _GEN_18 | _T_5; // @[Mux.scala 27:72]
+  wire [3:0] _GEN_19 = {{2'd0}, _T_8}; // @[Mux.scala 27:72]
+  wire [3:0] _T_9 = _GEN_19 | _T_6; // @[Mux.scala 27:72]
+  wire [7:0] _GEN_20 = {{4'd0}, _T_9}; // @[Mux.scala 27:72]
+  wire [7:0] ldst_byteen_r = _GEN_20 | _T_7; // @[Mux.scala 27:72]
   wire  dual_stbuf_write_r = io_ldst_dual_r & io_store_stbuf_reqvld_r; // @[lsu_stbuf.scala 115:43]
-  wire [10:0] _GEN_13 = {{3'd0}, ldst_byteen_r}; // @[lsu_stbuf.scala 117:39]
-  wire [10:0] _T_12 = _GEN_13 << io_lsu_addr_r[1:0]; // @[lsu_stbuf.scala 117:39]
+  wire [10:0] _GEN_21 = {{3'd0}, ldst_byteen_r}; // @[lsu_stbuf.scala 117:39]
+  wire [10:0] _T_12 = _GEN_21 << io_lsu_addr_r[1:0]; // @[lsu_stbuf.scala 117:39]
   wire [7:0] store_byteen_ext_r = _T_12[7:0]; // @[lsu_stbuf.scala 117:22]
   wire [3:0] _T_15 = io_lsu_pkt_r_bits_store ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
   wire [3:0] store_byteen_hi_r = store_byteen_ext_r[7:4] & _T_15; // @[lsu_stbuf.scala 118:52]
@@ -2654,7 +2789,7 @@ module lsu_stbuf(
   wire [1:0] WrPtrPlus1 = WrPtr + 2'h1; // @[lsu_stbuf.scala 122:26]
   wire [1:0] WrPtrPlus2 = WrPtr + 2'h2; // @[lsu_stbuf.scala 123:26]
   wire  _T_22 = io_lsu_commit_r | io_lsu_pkt_r_bits_dma; // @[lsu_stbuf.scala 125:46]
-  reg [15:0] stbuf_addr_0; // @[lib.scala 374:16]
+  reg [15:0] stbuf_addr_0; // @[Reg.scala 27:20]
   wire  _T_26 = stbuf_addr_0[15:2] == io_lsu_addr_r[15:2]; // @[lsu_stbuf.scala 127:120]
   reg  _T_587; // @[lsu_stbuf.scala 160:14]
   reg  _T_579; // @[lsu_stbuf.scala 160:14]
@@ -2681,21 +2816,21 @@ module lsu_stbuf(
   wire [3:0] stbuf_reset = {_T_214,_T_210,_T_206,_T_202}; // @[Cat.scala 29:58]
   wire  _T_33 = ~stbuf_reset[0]; // @[lsu_stbuf.scala 127:218]
   wire  _T_34 = _T_31 & _T_33; // @[lsu_stbuf.scala 127:216]
-  reg [15:0] stbuf_addr_1; // @[lib.scala 374:16]
+  reg [15:0] stbuf_addr_1; // @[Reg.scala 27:20]
   wire  _T_37 = stbuf_addr_1[15:2] == io_lsu_addr_r[15:2]; // @[lsu_stbuf.scala 127:120]
   wire  _T_39 = _T_37 & stbuf_vld[1]; // @[lsu_stbuf.scala 127:179]
   wire  _T_41 = ~stbuf_dma_kill[1]; // @[lsu_stbuf.scala 127:197]
   wire  _T_42 = _T_39 & _T_41; // @[lsu_stbuf.scala 127:195]
   wire  _T_44 = ~stbuf_reset[1]; // @[lsu_stbuf.scala 127:218]
   wire  _T_45 = _T_42 & _T_44; // @[lsu_stbuf.scala 127:216]
-  reg [15:0] stbuf_addr_2; // @[lib.scala 374:16]
+  reg [15:0] stbuf_addr_2; // @[Reg.scala 27:20]
   wire  _T_48 = stbuf_addr_2[15:2] == io_lsu_addr_r[15:2]; // @[lsu_stbuf.scala 127:120]
   wire  _T_50 = _T_48 & stbuf_vld[2]; // @[lsu_stbuf.scala 127:179]
   wire  _T_52 = ~stbuf_dma_kill[2]; // @[lsu_stbuf.scala 127:197]
   wire  _T_53 = _T_50 & _T_52; // @[lsu_stbuf.scala 127:195]
   wire  _T_55 = ~stbuf_reset[2]; // @[lsu_stbuf.scala 127:218]
   wire  _T_56 = _T_53 & _T_55; // @[lsu_stbuf.scala 127:216]
-  reg [15:0] stbuf_addr_3; // @[lib.scala 374:16]
+  reg [15:0] stbuf_addr_3; // @[Reg.scala 27:20]
   wire  _T_59 = stbuf_addr_3[15:2] == io_lsu_addr_r[15:2]; // @[lsu_stbuf.scala 127:120]
   wire  _T_61 = _T_59 & stbuf_vld[3]; // @[lsu_stbuf.scala 127:179]
   wire  _T_63 = ~stbuf_dma_kill[3]; // @[lsu_stbuf.scala 127:197]
@@ -2812,28 +2947,28 @@ module lsu_stbuf(
   wire [3:0] stbuf_byteenin_3 = sel_lo[3] ? _T_285 : _T_286; // @[lsu_stbuf.scala 142:61]
   wire  _T_290 = ~stbuf_byteen_0[0]; // @[lsu_stbuf.scala 144:70]
   wire  _T_292 = _T_290 | store_byteen_lo_r[0]; // @[lsu_stbuf.scala 144:90]
-  reg [31:0] stbuf_data_0; // @[lib.scala 374:16]
+  reg [31:0] stbuf_data_0; // @[Reg.scala 27:20]
   wire [7:0] _T_295 = _T_292 ? io_store_datafn_lo_r[7:0] : stbuf_data_0[7:0]; // @[lsu_stbuf.scala 144:69]
   wire  _T_299 = _T_290 | store_byteen_hi_r[0]; // @[lsu_stbuf.scala 145:31]
   wire [7:0] _T_302 = _T_299 ? io_store_datafn_hi_r[7:0] : stbuf_data_0[7:0]; // @[lsu_stbuf.scala 145:10]
   wire [7:0] datain1_0 = sel_lo[0] ? _T_295 : _T_302; // @[lsu_stbuf.scala 144:54]
   wire  _T_306 = ~stbuf_byteen_1[0]; // @[lsu_stbuf.scala 144:70]
   wire  _T_308 = _T_306 | store_byteen_lo_r[0]; // @[lsu_stbuf.scala 144:90]
-  reg [31:0] stbuf_data_1; // @[lib.scala 374:16]
+  reg [31:0] stbuf_data_1; // @[Reg.scala 27:20]
   wire [7:0] _T_311 = _T_308 ? io_store_datafn_lo_r[7:0] : stbuf_data_1[7:0]; // @[lsu_stbuf.scala 144:69]
   wire  _T_315 = _T_306 | store_byteen_hi_r[0]; // @[lsu_stbuf.scala 145:31]
   wire [7:0] _T_318 = _T_315 ? io_store_datafn_hi_r[7:0] : stbuf_data_1[7:0]; // @[lsu_stbuf.scala 145:10]
   wire [7:0] datain1_1 = sel_lo[1] ? _T_311 : _T_318; // @[lsu_stbuf.scala 144:54]
   wire  _T_322 = ~stbuf_byteen_2[0]; // @[lsu_stbuf.scala 144:70]
   wire  _T_324 = _T_322 | store_byteen_lo_r[0]; // @[lsu_stbuf.scala 144:90]
-  reg [31:0] stbuf_data_2; // @[lib.scala 374:16]
+  reg [31:0] stbuf_data_2; // @[Reg.scala 27:20]
   wire [7:0] _T_327 = _T_324 ? io_store_datafn_lo_r[7:0] : stbuf_data_2[7:0]; // @[lsu_stbuf.scala 144:69]
   wire  _T_331 = _T_322 | store_byteen_hi_r[0]; // @[lsu_stbuf.scala 145:31]
   wire [7:0] _T_334 = _T_331 ? io_store_datafn_hi_r[7:0] : stbuf_data_2[7:0]; // @[lsu_stbuf.scala 145:10]
   wire [7:0] datain1_2 = sel_lo[2] ? _T_327 : _T_334; // @[lsu_stbuf.scala 144:54]
   wire  _T_338 = ~stbuf_byteen_3[0]; // @[lsu_stbuf.scala 144:70]
   wire  _T_340 = _T_338 | store_byteen_lo_r[0]; // @[lsu_stbuf.scala 144:90]
-  reg [31:0] stbuf_data_3; // @[lib.scala 374:16]
+  reg [31:0] stbuf_data_3; // @[Reg.scala 27:20]
   wire [7:0] _T_343 = _T_340 ? io_store_datafn_lo_r[7:0] : stbuf_data_3[7:0]; // @[lsu_stbuf.scala 144:69]
   wire  _T_347 = _T_338 | store_byteen_hi_r[0]; // @[lsu_stbuf.scala 145:31]
   wire [7:0] _T_350 = _T_347 ? io_store_datafn_hi_r[7:0] : stbuf_data_3[7:0]; // @[lsu_stbuf.scala 145:10]
@@ -2910,14 +3045,10 @@ module lsu_stbuf(
   wire  _T_539 = _T_530 | store_byteen_hi_r[3]; // @[lsu_stbuf.scala 154:31]
   wire [7:0] _T_542 = _T_539 ? io_store_datafn_hi_r[31:24] : stbuf_data_3[31:24]; // @[lsu_stbuf.scala 154:10]
   wire [7:0] datain4_3 = sel_lo[3] ? _T_535 : _T_542; // @[lsu_stbuf.scala 153:54]
-  wire [15:0] _T_544 = {datain2_0,datain1_0}; // @[Cat.scala 29:58]
-  wire [15:0] _T_545 = {datain4_0,datain3_0}; // @[Cat.scala 29:58]
-  wire [15:0] _T_547 = {datain2_1,datain1_1}; // @[Cat.scala 29:58]
-  wire [15:0] _T_548 = {datain4_1,datain3_1}; // @[Cat.scala 29:58]
-  wire [15:0] _T_550 = {datain2_2,datain1_2}; // @[Cat.scala 29:58]
-  wire [15:0] _T_551 = {datain4_2,datain3_2}; // @[Cat.scala 29:58]
-  wire [15:0] _T_553 = {datain2_3,datain1_3}; // @[Cat.scala 29:58]
-  wire [15:0] _T_554 = {datain4_3,datain3_3}; // @[Cat.scala 29:58]
+  wire [31:0] stbuf_datain_0 = {datain4_0,datain3_0,datain2_0,datain1_0}; // @[Cat.scala 29:58]
+  wire [31:0] stbuf_datain_1 = {datain4_1,datain3_1,datain2_1,datain1_1}; // @[Cat.scala 29:58]
+  wire [31:0] stbuf_datain_2 = {datain4_2,datain3_2,datain2_2,datain1_2}; // @[Cat.scala 29:58]
+  wire [31:0] stbuf_datain_3 = {datain4_3,datain3_3,datain2_3,datain1_3}; // @[Cat.scala 29:58]
   wire  _T_559 = stbuf_wr_en[0] | stbuf_vld[0]; // @[lsu_stbuf.scala 160:18]
   wire  _T_567 = stbuf_wr_en[1] | stbuf_vld[1]; // @[lsu_stbuf.scala 160:18]
   wire  _T_575 = stbuf_wr_en[2] | stbuf_vld[2]; // @[lsu_stbuf.scala 160:18]
@@ -2993,10 +3124,10 @@ module lsu_stbuf(
   wire  _T_696 = _T_686[0] & _T_695; // @[lsu_stbuf.scala 184:44]
   wire  _T_697 = |stbuf_dma_kill_en; // @[lsu_stbuf.scala 184:91]
   wire  _T_698 = ~_T_697; // @[lsu_stbuf.scala 184:71]
-  wire [15:0] _GEN_1 = 2'h1 == RdPtr ? stbuf_addr_1 : stbuf_addr_0; // @[lsu_stbuf.scala 185:22]
-  wire [15:0] _GEN_2 = 2'h2 == RdPtr ? stbuf_addr_2 : _GEN_1; // @[lsu_stbuf.scala 185:22]
-  wire [31:0] _GEN_5 = 2'h1 == RdPtr ? stbuf_data_1 : stbuf_data_0; // @[lsu_stbuf.scala 186:22]
-  wire [31:0] _GEN_6 = 2'h2 == RdPtr ? stbuf_data_2 : _GEN_5; // @[lsu_stbuf.scala 186:22]
+  wire [15:0] _GEN_9 = 2'h1 == RdPtr ? stbuf_addr_1 : stbuf_addr_0; // @[lsu_stbuf.scala 185:22]
+  wire [15:0] _GEN_10 = 2'h2 == RdPtr ? stbuf_addr_2 : _GEN_9; // @[lsu_stbuf.scala 185:22]
+  wire [31:0] _GEN_13 = 2'h1 == RdPtr ? stbuf_data_1 : stbuf_data_0; // @[lsu_stbuf.scala 186:22]
+  wire [31:0] _GEN_14 = 2'h2 == RdPtr ? stbuf_data_2 : _GEN_13; // @[lsu_stbuf.scala 186:22]
   wire  _T_700 = ~dual_stbuf_write_r; // @[lsu_stbuf.scala 188:44]
   wire  _T_701 = io_ldst_stbuf_reqvld_r & _T_700; // @[lsu_stbuf.scala 188:42]
   wire  _T_702 = store_coalesce_hi_r | store_coalesce_lo_r; // @[lsu_stbuf.scala 188:88]
@@ -3025,12 +3156,12 @@ module lsu_stbuf(
   wire  isdccmst_r = _T_735 & _T_736; // @[lsu_stbuf.scala 199:85]
   wire [1:0] _T_737 = {1'h0,isdccmst_m}; // @[Cat.scala 29:58]
   wire  _T_738 = isdccmst_m & io_ldst_dual_m; // @[lsu_stbuf.scala 201:62]
-  wire [2:0] _GEN_14 = {{1'd0}, _T_737}; // @[lsu_stbuf.scala 201:47]
-  wire [2:0] _T_739 = _GEN_14 << _T_738; // @[lsu_stbuf.scala 201:47]
+  wire [2:0] _GEN_22 = {{1'd0}, _T_737}; // @[lsu_stbuf.scala 201:47]
+  wire [2:0] _T_739 = _GEN_22 << _T_738; // @[lsu_stbuf.scala 201:47]
   wire [1:0] _T_740 = {1'h0,isdccmst_r}; // @[Cat.scala 29:58]
   wire  _T_741 = isdccmst_r & io_ldst_dual_r; // @[lsu_stbuf.scala 202:62]
-  wire [2:0] _GEN_15 = {{1'd0}, _T_740}; // @[lsu_stbuf.scala 202:47]
-  wire [2:0] _T_742 = _GEN_15 << _T_741; // @[lsu_stbuf.scala 202:47]
+  wire [2:0] _GEN_23 = {{1'd0}, _T_740}; // @[lsu_stbuf.scala 202:47]
+  wire [2:0] _T_742 = _GEN_23 << _T_741; // @[lsu_stbuf.scala 202:47]
   wire [1:0] stbuf_specvld_m = _T_739[1:0]; // @[lsu_stbuf.scala 201:19]
   wire [3:0] _T_743 = {2'h0,stbuf_specvld_m}; // @[Cat.scala 29:58]
   wire [3:0] _T_745 = stbuf_numvld_any + _T_743; // @[lsu_stbuf.scala 203:44]
@@ -3263,58 +3394,50 @@ module lsu_stbuf(
   wire [7:0] stbuf_fwdpipe4_hi = ld_byte_rhit_hi[3] ? ld_fwddata_rpipe_hi[31:24] : stbuf_fwddata_hi_pre_m[31:24]; // @[lsu_stbuf.scala 271:30]
   wire [15:0] _T_1309 = {stbuf_fwdpipe2_hi,stbuf_fwdpipe1_hi}; // @[Cat.scala 29:58]
   wire [15:0] _T_1310 = {stbuf_fwdpipe4_hi,stbuf_fwdpipe3_hi}; // @[Cat.scala 29:58]
-  rvclkhdr rvclkhdr ( // @[lib.scala 368:23]
+  rvclkhdr rvclkhdr ( // @[lib.scala 390:23]
     .io_l1clk(rvclkhdr_io_l1clk),
     .io_clk(rvclkhdr_io_clk),
-    .io_en(rvclkhdr_io_en),
-    .io_scan_mode(rvclkhdr_io_scan_mode)
+    .io_en(rvclkhdr_io_en)
   );
-  rvclkhdr rvclkhdr_1 ( // @[lib.scala 368:23]
+  rvclkhdr rvclkhdr_1 ( // @[lib.scala 390:23]
     .io_l1clk(rvclkhdr_1_io_l1clk),
     .io_clk(rvclkhdr_1_io_clk),
-    .io_en(rvclkhdr_1_io_en),
-    .io_scan_mode(rvclkhdr_1_io_scan_mode)
+    .io_en(rvclkhdr_1_io_en)
   );
-  rvclkhdr rvclkhdr_2 ( // @[lib.scala 368:23]
+  rvclkhdr rvclkhdr_2 ( // @[lib.scala 390:23]
     .io_l1clk(rvclkhdr_2_io_l1clk),
     .io_clk(rvclkhdr_2_io_clk),
-    .io_en(rvclkhdr_2_io_en),
-    .io_scan_mode(rvclkhdr_2_io_scan_mode)
+    .io_en(rvclkhdr_2_io_en)
   );
-  rvclkhdr rvclkhdr_3 ( // @[lib.scala 368:23]
+  rvclkhdr rvclkhdr_3 ( // @[lib.scala 390:23]
     .io_l1clk(rvclkhdr_3_io_l1clk),
     .io_clk(rvclkhdr_3_io_clk),
-    .io_en(rvclkhdr_3_io_en),
-    .io_scan_mode(rvclkhdr_3_io_scan_mode)
+    .io_en(rvclkhdr_3_io_en)
   );
-  rvclkhdr rvclkhdr_4 ( // @[lib.scala 368:23]
+  rvclkhdr rvclkhdr_4 ( // @[lib.scala 390:23]
     .io_l1clk(rvclkhdr_4_io_l1clk),
     .io_clk(rvclkhdr_4_io_clk),
-    .io_en(rvclkhdr_4_io_en),
-    .io_scan_mode(rvclkhdr_4_io_scan_mode)
+    .io_en(rvclkhdr_4_io_en)
   );
-  rvclkhdr rvclkhdr_5 ( // @[lib.scala 368:23]
+  rvclkhdr rvclkhdr_5 ( // @[lib.scala 390:23]
     .io_l1clk(rvclkhdr_5_io_l1clk),
     .io_clk(rvclkhdr_5_io_clk),
-    .io_en(rvclkhdr_5_io_en),
-    .io_scan_mode(rvclkhdr_5_io_scan_mode)
+    .io_en(rvclkhdr_5_io_en)
   );
-  rvclkhdr rvclkhdr_6 ( // @[lib.scala 368:23]
+  rvclkhdr rvclkhdr_6 ( // @[lib.scala 390:23]
     .io_l1clk(rvclkhdr_6_io_l1clk),
     .io_clk(rvclkhdr_6_io_clk),
-    .io_en(rvclkhdr_6_io_en),
-    .io_scan_mode(rvclkhdr_6_io_scan_mode)
+    .io_en(rvclkhdr_6_io_en)
   );
-  rvclkhdr rvclkhdr_7 ( // @[lib.scala 368:23]
+  rvclkhdr rvclkhdr_7 ( // @[lib.scala 390:23]
     .io_l1clk(rvclkhdr_7_io_l1clk),
     .io_clk(rvclkhdr_7_io_clk),
-    .io_en(rvclkhdr_7_io_en),
-    .io_scan_mode(rvclkhdr_7_io_scan_mode)
+    .io_en(rvclkhdr_7_io_en)
   );
   assign io_stbuf_reqvld_any = _T_696 & _T_698; // @[lsu_stbuf.scala 51:47 lsu_stbuf.scala 184:24]
   assign io_stbuf_reqvld_flushed_any = _T_686[0] & _T_688[0]; // @[lsu_stbuf.scala 52:35 lsu_stbuf.scala 183:31]
-  assign io_stbuf_addr_any = 2'h3 == RdPtr ? stbuf_addr_3 : _GEN_2; // @[lsu_stbuf.scala 53:35 lsu_stbuf.scala 185:22]
-  assign io_stbuf_data_any = 2'h3 == RdPtr ? stbuf_data_3 : _GEN_6; // @[lsu_stbuf.scala 54:35 lsu_stbuf.scala 186:22]
+  assign io_stbuf_addr_any = 2'h3 == RdPtr ? stbuf_addr_3 : _GEN_10; // @[lsu_stbuf.scala 53:35 lsu_stbuf.scala 185:22]
+  assign io_stbuf_data_any = 2'h3 == RdPtr ? stbuf_data_3 : _GEN_14; // @[lsu_stbuf.scala 54:35 lsu_stbuf.scala 186:22]
   assign io_lsu_stbuf_full_any = _T_749 ? _T_751 : _T_752; // @[lsu_stbuf.scala 55:43 lsu_stbuf.scala 205:26]
   assign io_lsu_stbuf_empty_any = stbuf_numvld_any == 4'h0; // @[lsu_stbuf.scala 56:43 lsu_stbuf.scala 206:26]
   assign io_ldst_stbuf_reqvld_r = _T_22 & io_store_stbuf_reqvld_r; // @[lsu_stbuf.scala 57:43 lsu_stbuf.scala 125:26]
@@ -3322,30 +3445,22 @@ module lsu_stbuf(
   assign io_stbuf_fwddata_lo_m = {_T_1295,_T_1294}; // @[lsu_stbuf.scala 59:43 lsu_stbuf.scala 266:25]
   assign io_stbuf_fwdbyteen_hi_m = {_T_1269,_T_1261}; // @[lsu_stbuf.scala 60:37 lsu_stbuf.scala 258:27]
   assign io_stbuf_fwdbyteen_lo_m = {_T_1280,_T_1272}; // @[lsu_stbuf.scala 61:37 lsu_stbuf.scala 259:27]
-  assign rvclkhdr_io_clk = clock; // @[lib.scala 370:18]
-  assign rvclkhdr_io_en = stbuf_wr_en[0]; // @[lib.scala 371:17]
-  assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
-  assign rvclkhdr_1_io_clk = clock; // @[lib.scala 370:18]
-  assign rvclkhdr_1_io_en = stbuf_wr_en[0]; // @[lib.scala 371:17]
-  assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
-  assign rvclkhdr_2_io_clk = clock; // @[lib.scala 370:18]
-  assign rvclkhdr_2_io_en = stbuf_wr_en[1]; // @[lib.scala 371:17]
-  assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
-  assign rvclkhdr_3_io_clk = clock; // @[lib.scala 370:18]
-  assign rvclkhdr_3_io_en = stbuf_wr_en[1]; // @[lib.scala 371:17]
-  assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
-  assign rvclkhdr_4_io_clk = clock; // @[lib.scala 370:18]
-  assign rvclkhdr_4_io_en = stbuf_wr_en[2]; // @[lib.scala 371:17]
-  assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
-  assign rvclkhdr_5_io_clk = clock; // @[lib.scala 370:18]
-  assign rvclkhdr_5_io_en = stbuf_wr_en[2]; // @[lib.scala 371:17]
-  assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
-  assign rvclkhdr_6_io_clk = clock; // @[lib.scala 370:18]
-  assign rvclkhdr_6_io_en = stbuf_wr_en[3]; // @[lib.scala 371:17]
-  assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
-  assign rvclkhdr_7_io_clk = clock; // @[lib.scala 370:18]
-  assign rvclkhdr_7_io_en = stbuf_wr_en[3]; // @[lib.scala 371:17]
-  assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
+  assign rvclkhdr_io_clk = clock; // @[lib.scala 392:18]
+  assign rvclkhdr_io_en = stbuf_wr_en[0]; // @[lib.scala 393:17]
+  assign rvclkhdr_1_io_clk = clock; // @[lib.scala 392:18]
+  assign rvclkhdr_1_io_en = stbuf_wr_en[0]; // @[lib.scala 393:17]
+  assign rvclkhdr_2_io_clk = clock; // @[lib.scala 392:18]
+  assign rvclkhdr_2_io_en = stbuf_wr_en[1]; // @[lib.scala 393:17]
+  assign rvclkhdr_3_io_clk = clock; // @[lib.scala 392:18]
+  assign rvclkhdr_3_io_en = stbuf_wr_en[1]; // @[lib.scala 393:17]
+  assign rvclkhdr_4_io_clk = clock; // @[lib.scala 392:18]
+  assign rvclkhdr_4_io_en = stbuf_wr_en[2]; // @[lib.scala 393:17]
+  assign rvclkhdr_5_io_clk = clock; // @[lib.scala 392:18]
+  assign rvclkhdr_5_io_en = stbuf_wr_en[2]; // @[lib.scala 393:17]
+  assign rvclkhdr_6_io_clk = clock; // @[lib.scala 392:18]
+  assign rvclkhdr_6_io_en = stbuf_wr_en[3]; // @[lib.scala 393:17]
+  assign rvclkhdr_7_io_clk = clock; // @[lib.scala 392:18]
+  assign rvclkhdr_7_io_en = stbuf_wr_en[3]; // @[lib.scala 393:17]
 `ifdef RANDOMIZE_GARBAGE_ASSIGN
 `define RANDOMIZE
 `endif
@@ -3516,13 +3631,15 @@ end // initial
       end
     end
   end
-  always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
+  always @(posedge clock or posedge reset) begin
     if (reset) begin
       stbuf_addr_0 <= 16'h0;
-    end else if (sel_lo[0]) begin
-      stbuf_addr_0 <= io_lsu_addr_r[15:0];
-    end else begin
-      stbuf_addr_0 <= io_end_addr_r[15:0];
+    end else if (stbuf_wr_en[0]) begin
+      if (sel_lo[0]) begin
+        stbuf_addr_0 <= io_lsu_addr_r[15:0];
+      end else begin
+        stbuf_addr_0 <= io_end_addr_r[15:0];
+      end
     end
   end
   always @(posedge io_lsu_free_c2_clk or posedge reset) begin
@@ -3581,31 +3698,37 @@ end // initial
       _T_598 <= _T_594 & _T_33;
     end
   end
-  always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
+  always @(posedge clock or posedge reset) begin
     if (reset) begin
       stbuf_addr_1 <= 16'h0;
-    end else if (sel_lo[1]) begin
-      stbuf_addr_1 <= io_lsu_addr_r[15:0];
-    end else begin
-      stbuf_addr_1 <= io_end_addr_r[15:0];
+    end else if (stbuf_wr_en[1]) begin
+      if (sel_lo[1]) begin
+        stbuf_addr_1 <= io_lsu_addr_r[15:0];
+      end else begin
+        stbuf_addr_1 <= io_end_addr_r[15:0];
+      end
     end
   end
-  always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin
+  always @(posedge clock or posedge reset) begin
     if (reset) begin
       stbuf_addr_2 <= 16'h0;
-    end else if (sel_lo[2]) begin
-      stbuf_addr_2 <= io_lsu_addr_r[15:0];
-    end else begin
-      stbuf_addr_2 <= io_end_addr_r[15:0];
+    end else if (stbuf_wr_en[2]) begin
+      if (sel_lo[2]) begin
+        stbuf_addr_2 <= io_lsu_addr_r[15:0];
+      end else begin
+        stbuf_addr_2 <= io_end_addr_r[15:0];
+      end
     end
   end
-  always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin
+  always @(posedge clock or posedge reset) begin
     if (reset) begin
       stbuf_addr_3 <= 16'h0;
-    end else if (sel_lo[3]) begin
-      stbuf_addr_3 <= io_lsu_addr_r[15:0];
-    end else begin
-      stbuf_addr_3 <= io_end_addr_r[15:0];
+    end else if (stbuf_wr_en[3]) begin
+      if (sel_lo[3]) begin
+        stbuf_addr_3 <= io_lsu_addr_r[15:0];
+      end else begin
+        stbuf_addr_3 <= io_end_addr_r[15:0];
+      end
     end
   end
   always @(posedge io_lsu_stbuf_c1_clk or posedge reset) begin
@@ -3636,64 +3759,59 @@ end // initial
       stbuf_byteen_3 <= _T_655 & _T_659;
     end
   end
-  always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin
+  always @(posedge clock or posedge reset) begin
     if (reset) begin
       stbuf_data_0 <= 32'h0;
-    end else begin
-      stbuf_data_0 <= {_T_545,_T_544};
+    end else if (stbuf_wr_en[0]) begin
+      stbuf_data_0 <= stbuf_datain_0;
     end
   end
-  always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin
+  always @(posedge clock or posedge reset) begin
     if (reset) begin
       stbuf_data_1 <= 32'h0;
-    end else begin
-      stbuf_data_1 <= {_T_548,_T_547};
+    end else if (stbuf_wr_en[1]) begin
+      stbuf_data_1 <= stbuf_datain_1;
     end
   end
-  always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin
+  always @(posedge clock or posedge reset) begin
     if (reset) begin
       stbuf_data_2 <= 32'h0;
-    end else begin
-      stbuf_data_2 <= {_T_551,_T_550};
+    end else if (stbuf_wr_en[2]) begin
+      stbuf_data_2 <= stbuf_datain_2;
     end
   end
-  always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin
+  always @(posedge clock or posedge reset) begin
     if (reset) begin
       stbuf_data_3 <= 32'h0;
-    end else begin
-      stbuf_data_3 <= {_T_554,_T_553};
+    end else if (stbuf_wr_en[3]) begin
+      stbuf_data_3 <= stbuf_datain_3;
     end
   end
 endmodule
 module lsu_ecc(
   input         clock,
   input         reset,
-  input         io_lsu_c2_r_clk,
   input         io_clk_override,
-  input         io_lsu_pkt_m_valid,
-  input         io_lsu_pkt_m_bits_load,
-  input         io_lsu_pkt_m_bits_store,
-  input         io_lsu_pkt_m_bits_dma,
+  input         io_lsu_pkt_r_valid,
+  input         io_lsu_pkt_r_bits_load,
+  input         io_lsu_pkt_r_bits_store,
   input  [31:0] io_stbuf_data_any,
   input         io_dec_tlu_core_ecc_disable,
-  input  [15:0] io_lsu_addr_m,
-  input  [15:0] io_end_addr_m,
-  input  [31:0] io_dccm_rdata_hi_m,
-  input  [31:0] io_dccm_rdata_lo_m,
-  input  [6:0]  io_dccm_data_ecc_hi_m,
-  input  [6:0]  io_dccm_data_ecc_lo_m,
+  input         io_lsu_dccm_rden_r,
+  input         io_addr_in_dccm_r,
+  input  [15:0] io_lsu_addr_r,
+  input  [15:0] io_end_addr_r,
+  input  [31:0] io_dccm_rdata_hi_r,
+  input  [31:0] io_dccm_rdata_lo_r,
+  input  [6:0]  io_dccm_data_ecc_hi_r,
+  input  [6:0]  io_dccm_data_ecc_lo_r,
   input         io_ld_single_ecc_error_r,
   input         io_ld_single_ecc_error_r_ff,
-  input         io_lsu_dccm_rden_m,
-  input         io_addr_in_dccm_m,
   input         io_dma_dccm_wen,
   input  [31:0] io_dma_dccm_wdata_lo,
   input  [31:0] io_dma_dccm_wdata_hi,
-  input         io_scan_mode,
   output [31:0] io_sec_data_hi_r,
   output [31:0] io_sec_data_lo_r,
-  output [31:0] io_sec_data_hi_m,
-  output [31:0] io_sec_data_lo_m,
   output [31:0] io_sec_data_hi_r_ff,
   output [31:0] io_sec_data_lo_r_ff,
   output [6:0]  io_dma_dccm_wdata_ecc_hi,
@@ -3705,73 +3823,61 @@ module lsu_ecc(
   output        io_single_ecc_error_lo_r,
   output        io_lsu_single_ecc_error_r,
   output        io_lsu_double_ecc_error_r,
-  output        io_lsu_single_ecc_error_m,
-  output        io_lsu_double_ecc_error_m
+  output        io_lsu_single_ecc_error_m
 );
 `ifdef RANDOMIZE_REG_INIT
   reg [31:0] _RAND_0;
   reg [31:0] _RAND_1;
-  reg [31:0] _RAND_2;
-  reg [31:0] _RAND_3;
-  reg [31:0] _RAND_4;
-  reg [31:0] _RAND_5;
-  reg [31:0] _RAND_6;
-  reg [31:0] _RAND_7;
 `endif // RANDOMIZE_REG_INIT
-  wire  rvclkhdr_io_l1clk; // @[lib.scala 368:23]
-  wire  rvclkhdr_io_clk; // @[lib.scala 368:23]
-  wire  rvclkhdr_io_en; // @[lib.scala 368:23]
-  wire  rvclkhdr_io_scan_mode; // @[lib.scala 368:23]
-  wire  rvclkhdr_1_io_l1clk; // @[lib.scala 368:23]
-  wire  rvclkhdr_1_io_clk; // @[lib.scala 368:23]
-  wire  rvclkhdr_1_io_en; // @[lib.scala 368:23]
-  wire  rvclkhdr_1_io_scan_mode; // @[lib.scala 368:23]
-  wire  rvclkhdr_2_io_l1clk; // @[lib.scala 368:23]
-  wire  rvclkhdr_2_io_clk; // @[lib.scala 368:23]
-  wire  rvclkhdr_2_io_en; // @[lib.scala 368:23]
-  wire  rvclkhdr_2_io_scan_mode; // @[lib.scala 368:23]
-  wire  rvclkhdr_3_io_l1clk; // @[lib.scala 368:23]
-  wire  rvclkhdr_3_io_clk; // @[lib.scala 368:23]
-  wire  rvclkhdr_3_io_en; // @[lib.scala 368:23]
-  wire  rvclkhdr_3_io_scan_mode; // @[lib.scala 368:23]
-  wire  _T_96 = ^io_dccm_rdata_hi_m; // @[lib.scala 193:30]
-  wire  _T_97 = ^io_dccm_data_ecc_hi_m; // @[lib.scala 193:44]
+  wire  rvclkhdr_io_l1clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_io_clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_io_en; // @[lib.scala 390:23]
+  wire  rvclkhdr_1_io_l1clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_1_io_clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_1_io_en; // @[lib.scala 390:23]
+  wire  rvclkhdr_2_io_l1clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_2_io_clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_2_io_en; // @[lib.scala 390:23]
+  wire  rvclkhdr_3_io_l1clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_3_io_clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_3_io_en; // @[lib.scala 390:23]
+  wire  _T_96 = ^io_dccm_rdata_hi_r; // @[lib.scala 193:30]
+  wire  _T_97 = ^io_dccm_data_ecc_hi_r; // @[lib.scala 193:44]
   wire  _T_98 = _T_96 ^ _T_97; // @[lib.scala 193:35]
-  wire [5:0] _T_106 = {io_dccm_rdata_hi_m[31],io_dccm_rdata_hi_m[30],io_dccm_rdata_hi_m[29],io_dccm_rdata_hi_m[28],io_dccm_rdata_hi_m[27],io_dccm_rdata_hi_m[26]}; // @[lib.scala 193:76]
+  wire [5:0] _T_106 = {io_dccm_rdata_hi_r[31],io_dccm_rdata_hi_r[30],io_dccm_rdata_hi_r[29],io_dccm_rdata_hi_r[28],io_dccm_rdata_hi_r[27],io_dccm_rdata_hi_r[26]}; // @[lib.scala 193:76]
   wire  _T_107 = ^_T_106; // @[lib.scala 193:83]
-  wire  _T_108 = io_dccm_data_ecc_hi_m[5] ^ _T_107; // @[lib.scala 193:71]
-  wire [6:0] _T_115 = {io_dccm_rdata_hi_m[17],io_dccm_rdata_hi_m[16],io_dccm_rdata_hi_m[15],io_dccm_rdata_hi_m[14],io_dccm_rdata_hi_m[13],io_dccm_rdata_hi_m[12],io_dccm_rdata_hi_m[11]}; // @[lib.scala 193:103]
-  wire [14:0] _T_123 = {io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[24],io_dccm_rdata_hi_m[23],io_dccm_rdata_hi_m[22],io_dccm_rdata_hi_m[21],io_dccm_rdata_hi_m[20],io_dccm_rdata_hi_m[19],io_dccm_rdata_hi_m[18],_T_115}; // @[lib.scala 193:103]
+  wire  _T_108 = io_dccm_data_ecc_hi_r[5] ^ _T_107; // @[lib.scala 193:71]
+  wire [6:0] _T_115 = {io_dccm_rdata_hi_r[17],io_dccm_rdata_hi_r[16],io_dccm_rdata_hi_r[15],io_dccm_rdata_hi_r[14],io_dccm_rdata_hi_r[13],io_dccm_rdata_hi_r[12],io_dccm_rdata_hi_r[11]}; // @[lib.scala 193:103]
+  wire [14:0] _T_123 = {io_dccm_rdata_hi_r[25],io_dccm_rdata_hi_r[24],io_dccm_rdata_hi_r[23],io_dccm_rdata_hi_r[22],io_dccm_rdata_hi_r[21],io_dccm_rdata_hi_r[20],io_dccm_rdata_hi_r[19],io_dccm_rdata_hi_r[18],_T_115}; // @[lib.scala 193:103]
   wire  _T_124 = ^_T_123; // @[lib.scala 193:110]
-  wire  _T_125 = io_dccm_data_ecc_hi_m[4] ^ _T_124; // @[lib.scala 193:98]
-  wire [6:0] _T_132 = {io_dccm_rdata_hi_m[10],io_dccm_rdata_hi_m[9],io_dccm_rdata_hi_m[8],io_dccm_rdata_hi_m[7],io_dccm_rdata_hi_m[6],io_dccm_rdata_hi_m[5],io_dccm_rdata_hi_m[4]}; // @[lib.scala 193:130]
-  wire [14:0] _T_140 = {io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[24],io_dccm_rdata_hi_m[23],io_dccm_rdata_hi_m[22],io_dccm_rdata_hi_m[21],io_dccm_rdata_hi_m[20],io_dccm_rdata_hi_m[19],io_dccm_rdata_hi_m[18],_T_132}; // @[lib.scala 193:130]
+  wire  _T_125 = io_dccm_data_ecc_hi_r[4] ^ _T_124; // @[lib.scala 193:98]
+  wire [6:0] _T_132 = {io_dccm_rdata_hi_r[10],io_dccm_rdata_hi_r[9],io_dccm_rdata_hi_r[8],io_dccm_rdata_hi_r[7],io_dccm_rdata_hi_r[6],io_dccm_rdata_hi_r[5],io_dccm_rdata_hi_r[4]}; // @[lib.scala 193:130]
+  wire [14:0] _T_140 = {io_dccm_rdata_hi_r[25],io_dccm_rdata_hi_r[24],io_dccm_rdata_hi_r[23],io_dccm_rdata_hi_r[22],io_dccm_rdata_hi_r[21],io_dccm_rdata_hi_r[20],io_dccm_rdata_hi_r[19],io_dccm_rdata_hi_r[18],_T_132}; // @[lib.scala 193:130]
   wire  _T_141 = ^_T_140; // @[lib.scala 193:137]
-  wire  _T_142 = io_dccm_data_ecc_hi_m[3] ^ _T_141; // @[lib.scala 193:125]
-  wire [8:0] _T_151 = {io_dccm_rdata_hi_m[15],io_dccm_rdata_hi_m[14],io_dccm_rdata_hi_m[10],io_dccm_rdata_hi_m[9],io_dccm_rdata_hi_m[8],io_dccm_rdata_hi_m[7],io_dccm_rdata_hi_m[3],io_dccm_rdata_hi_m[2],io_dccm_rdata_hi_m[1]}; // @[lib.scala 193:157]
-  wire [17:0] _T_160 = {io_dccm_rdata_hi_m[31],io_dccm_rdata_hi_m[30],io_dccm_rdata_hi_m[29],io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[24],io_dccm_rdata_hi_m[23],io_dccm_rdata_hi_m[22],io_dccm_rdata_hi_m[17],io_dccm_rdata_hi_m[16],_T_151}; // @[lib.scala 193:157]
+  wire  _T_142 = io_dccm_data_ecc_hi_r[3] ^ _T_141; // @[lib.scala 193:125]
+  wire [8:0] _T_151 = {io_dccm_rdata_hi_r[15],io_dccm_rdata_hi_r[14],io_dccm_rdata_hi_r[10],io_dccm_rdata_hi_r[9],io_dccm_rdata_hi_r[8],io_dccm_rdata_hi_r[7],io_dccm_rdata_hi_r[3],io_dccm_rdata_hi_r[2],io_dccm_rdata_hi_r[1]}; // @[lib.scala 193:157]
+  wire [17:0] _T_160 = {io_dccm_rdata_hi_r[31],io_dccm_rdata_hi_r[30],io_dccm_rdata_hi_r[29],io_dccm_rdata_hi_r[25],io_dccm_rdata_hi_r[24],io_dccm_rdata_hi_r[23],io_dccm_rdata_hi_r[22],io_dccm_rdata_hi_r[17],io_dccm_rdata_hi_r[16],_T_151}; // @[lib.scala 193:157]
   wire  _T_161 = ^_T_160; // @[lib.scala 193:164]
-  wire  _T_162 = io_dccm_data_ecc_hi_m[2] ^ _T_161; // @[lib.scala 193:152]
-  wire [8:0] _T_171 = {io_dccm_rdata_hi_m[13],io_dccm_rdata_hi_m[12],io_dccm_rdata_hi_m[10],io_dccm_rdata_hi_m[9],io_dccm_rdata_hi_m[6],io_dccm_rdata_hi_m[5],io_dccm_rdata_hi_m[3],io_dccm_rdata_hi_m[2],io_dccm_rdata_hi_m[0]}; // @[lib.scala 193:184]
-  wire [17:0] _T_180 = {io_dccm_rdata_hi_m[31],io_dccm_rdata_hi_m[28],io_dccm_rdata_hi_m[27],io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[24],io_dccm_rdata_hi_m[21],io_dccm_rdata_hi_m[20],io_dccm_rdata_hi_m[17],io_dccm_rdata_hi_m[16],_T_171}; // @[lib.scala 193:184]
+  wire  _T_162 = io_dccm_data_ecc_hi_r[2] ^ _T_161; // @[lib.scala 193:152]
+  wire [8:0] _T_171 = {io_dccm_rdata_hi_r[13],io_dccm_rdata_hi_r[12],io_dccm_rdata_hi_r[10],io_dccm_rdata_hi_r[9],io_dccm_rdata_hi_r[6],io_dccm_rdata_hi_r[5],io_dccm_rdata_hi_r[3],io_dccm_rdata_hi_r[2],io_dccm_rdata_hi_r[0]}; // @[lib.scala 193:184]
+  wire [17:0] _T_180 = {io_dccm_rdata_hi_r[31],io_dccm_rdata_hi_r[28],io_dccm_rdata_hi_r[27],io_dccm_rdata_hi_r[25],io_dccm_rdata_hi_r[24],io_dccm_rdata_hi_r[21],io_dccm_rdata_hi_r[20],io_dccm_rdata_hi_r[17],io_dccm_rdata_hi_r[16],_T_171}; // @[lib.scala 193:184]
   wire  _T_181 = ^_T_180; // @[lib.scala 193:191]
-  wire  _T_182 = io_dccm_data_ecc_hi_m[1] ^ _T_181; // @[lib.scala 193:179]
-  wire [8:0] _T_191 = {io_dccm_rdata_hi_m[13],io_dccm_rdata_hi_m[11],io_dccm_rdata_hi_m[10],io_dccm_rdata_hi_m[8],io_dccm_rdata_hi_m[6],io_dccm_rdata_hi_m[4],io_dccm_rdata_hi_m[3],io_dccm_rdata_hi_m[1],io_dccm_rdata_hi_m[0]}; // @[lib.scala 193:211]
-  wire [17:0] _T_200 = {io_dccm_rdata_hi_m[30],io_dccm_rdata_hi_m[28],io_dccm_rdata_hi_m[26],io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[23],io_dccm_rdata_hi_m[21],io_dccm_rdata_hi_m[19],io_dccm_rdata_hi_m[17],io_dccm_rdata_hi_m[15],_T_191}; // @[lib.scala 193:211]
+  wire  _T_182 = io_dccm_data_ecc_hi_r[1] ^ _T_181; // @[lib.scala 193:179]
+  wire [8:0] _T_191 = {io_dccm_rdata_hi_r[13],io_dccm_rdata_hi_r[11],io_dccm_rdata_hi_r[10],io_dccm_rdata_hi_r[8],io_dccm_rdata_hi_r[6],io_dccm_rdata_hi_r[4],io_dccm_rdata_hi_r[3],io_dccm_rdata_hi_r[1],io_dccm_rdata_hi_r[0]}; // @[lib.scala 193:211]
+  wire [17:0] _T_200 = {io_dccm_rdata_hi_r[30],io_dccm_rdata_hi_r[28],io_dccm_rdata_hi_r[26],io_dccm_rdata_hi_r[25],io_dccm_rdata_hi_r[23],io_dccm_rdata_hi_r[21],io_dccm_rdata_hi_r[19],io_dccm_rdata_hi_r[17],io_dccm_rdata_hi_r[15],_T_191}; // @[lib.scala 193:211]
   wire  _T_201 = ^_T_200; // @[lib.scala 193:218]
-  wire  _T_202 = io_dccm_data_ecc_hi_m[0] ^ _T_201; // @[lib.scala 193:206]
+  wire  _T_202 = io_dccm_data_ecc_hi_r[0] ^ _T_201; // @[lib.scala 193:206]
   wire [6:0] _T_208 = {_T_98,_T_108,_T_125,_T_142,_T_162,_T_182,_T_202}; // @[Cat.scala 29:58]
   wire  _T_209 = _T_208 != 7'h0; // @[lib.scala 194:44]
+  wire  _T_1123 = io_lsu_pkt_r_bits_load | io_lsu_pkt_r_bits_store; // @[lsu_ecc.scala 104:63]
+  wire  _T_1124 = io_lsu_pkt_r_valid & _T_1123; // @[lsu_ecc.scala 104:37]
+  wire  _T_1125 = _T_1124 & io_addr_in_dccm_r; // @[lsu_ecc.scala 104:90]
+  wire  is_ldst_r = _T_1125 & io_lsu_dccm_rden_r; // @[lsu_ecc.scala 104:110]
+  wire  ldst_dual_r = io_lsu_addr_r[2] != io_end_addr_r[2]; // @[lsu_ecc.scala 103:37]
+  wire  _T_1129 = is_ldst_r & ldst_dual_r; // @[lsu_ecc.scala 106:31]
   wire  _T_1130 = ~io_dec_tlu_core_ecc_disable; // @[lsu_ecc.scala 106:48]
-  wire  _T_1137 = io_lsu_pkt_m_bits_load | io_lsu_pkt_m_bits_store; // @[lsu_ecc.scala 124:65]
-  wire  _T_1138 = io_lsu_pkt_m_valid & _T_1137; // @[lsu_ecc.scala 124:39]
-  wire  _T_1139 = _T_1138 & io_addr_in_dccm_m; // @[lsu_ecc.scala 124:92]
-  wire  is_ldst_m = _T_1139 & io_lsu_dccm_rden_m; // @[lsu_ecc.scala 124:112]
-  wire  ldst_dual_m = io_lsu_addr_m[2] != io_end_addr_m[2]; // @[lsu_ecc.scala 123:39]
-  wire  _T_1143 = ldst_dual_m | io_lsu_pkt_m_bits_dma; // @[lsu_ecc.scala 126:48]
-  wire  _T_1144 = is_ldst_m & _T_1143; // @[lsu_ecc.scala 126:33]
-  wire  is_ldst_hi_m = _T_1144 & _T_1130; // @[lsu_ecc.scala 126:73]
-  wire  _T_210 = is_ldst_hi_m & _T_209; // @[lib.scala 194:32]
+  wire  is_ldst_hi_r = _T_1129 & _T_1130; // @[lsu_ecc.scala 106:46]
+  wire  _T_210 = is_ldst_hi_r & _T_209; // @[lib.scala 194:32]
   wire  single_ecc_error_hi_any = _T_210 & _T_208[6]; // @[lib.scala 194:53]
   wire  _T_215 = ~_T_208[6]; // @[lib.scala 195:55]
   wire  double_ecc_error_hi_any = _T_210 & _T_215; // @[lib.scala 195:53]
@@ -3814,8 +3920,8 @@ module lsu_ecc(
   wire  _T_290 = _T_208[5:0] == 6'h25; // @[lib.scala 199:41]
   wire  _T_292 = _T_208[5:0] == 6'h26; // @[lib.scala 199:41]
   wire  _T_294 = _T_208[5:0] == 6'h27; // @[lib.scala 199:41]
-  wire [7:0] _T_309 = {io_dccm_data_ecc_hi_m[3],io_dccm_rdata_hi_m[3:1],io_dccm_data_ecc_hi_m[2],io_dccm_rdata_hi_m[0],io_dccm_data_ecc_hi_m[1:0]}; // @[Cat.scala 29:58]
-  wire [38:0] _T_315 = {io_dccm_data_ecc_hi_m[6],io_dccm_rdata_hi_m[31:26],io_dccm_data_ecc_hi_m[5],io_dccm_rdata_hi_m[25:11],io_dccm_data_ecc_hi_m[4],io_dccm_rdata_hi_m[10:4],_T_309}; // @[Cat.scala 29:58]
+  wire [7:0] _T_309 = {io_dccm_data_ecc_hi_r[3],io_dccm_rdata_hi_r[3:1],io_dccm_data_ecc_hi_r[2],io_dccm_rdata_hi_r[0],io_dccm_data_ecc_hi_r[1:0]}; // @[Cat.scala 29:58]
+  wire [38:0] _T_315 = {io_dccm_data_ecc_hi_r[6],io_dccm_rdata_hi_r[31:26],io_dccm_data_ecc_hi_r[5],io_dccm_rdata_hi_r[25:11],io_dccm_data_ecc_hi_r[4],io_dccm_rdata_hi_r[10:4],_T_309}; // @[Cat.scala 29:58]
   wire [9:0] _T_333 = {_T_254,_T_252,_T_250,_T_248,_T_246,_T_244,_T_242,_T_240,_T_238,_T_236}; // @[lib.scala 202:69]
   wire [18:0] _T_334 = {_T_333,_T_234,_T_232,_T_230,_T_228,_T_226,_T_224,_T_222,_T_220,_T_218}; // @[lib.scala 202:69]
   wire [9:0] _T_343 = {_T_274,_T_272,_T_270,_T_268,_T_266,_T_264,_T_262,_T_260,_T_258,_T_256}; // @[lib.scala 202:69]
@@ -3825,36 +3931,36 @@ module lsu_ecc(
   wire [38:0] _T_356 = single_ecc_error_hi_any ? _T_355 : _T_315; // @[lib.scala 202:31]
   wire [3:0] _T_362 = {_T_356[6:4],_T_356[2]}; // @[Cat.scala 29:58]
   wire [27:0] _T_364 = {_T_356[37:32],_T_356[30:16],_T_356[14:8]}; // @[Cat.scala 29:58]
-  wire  _T_474 = ^io_dccm_rdata_lo_m; // @[lib.scala 193:30]
-  wire  _T_475 = ^io_dccm_data_ecc_lo_m; // @[lib.scala 193:44]
+  wire  _T_474 = ^io_dccm_rdata_lo_r; // @[lib.scala 193:30]
+  wire  _T_475 = ^io_dccm_data_ecc_lo_r; // @[lib.scala 193:44]
   wire  _T_476 = _T_474 ^ _T_475; // @[lib.scala 193:35]
-  wire [5:0] _T_484 = {io_dccm_rdata_lo_m[31],io_dccm_rdata_lo_m[30],io_dccm_rdata_lo_m[29],io_dccm_rdata_lo_m[28],io_dccm_rdata_lo_m[27],io_dccm_rdata_lo_m[26]}; // @[lib.scala 193:76]
+  wire [5:0] _T_484 = {io_dccm_rdata_lo_r[31],io_dccm_rdata_lo_r[30],io_dccm_rdata_lo_r[29],io_dccm_rdata_lo_r[28],io_dccm_rdata_lo_r[27],io_dccm_rdata_lo_r[26]}; // @[lib.scala 193:76]
   wire  _T_485 = ^_T_484; // @[lib.scala 193:83]
-  wire  _T_486 = io_dccm_data_ecc_lo_m[5] ^ _T_485; // @[lib.scala 193:71]
-  wire [6:0] _T_493 = {io_dccm_rdata_lo_m[17],io_dccm_rdata_lo_m[16],io_dccm_rdata_lo_m[15],io_dccm_rdata_lo_m[14],io_dccm_rdata_lo_m[13],io_dccm_rdata_lo_m[12],io_dccm_rdata_lo_m[11]}; // @[lib.scala 193:103]
-  wire [14:0] _T_501 = {io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[24],io_dccm_rdata_lo_m[23],io_dccm_rdata_lo_m[22],io_dccm_rdata_lo_m[21],io_dccm_rdata_lo_m[20],io_dccm_rdata_lo_m[19],io_dccm_rdata_lo_m[18],_T_493}; // @[lib.scala 193:103]
+  wire  _T_486 = io_dccm_data_ecc_lo_r[5] ^ _T_485; // @[lib.scala 193:71]
+  wire [6:0] _T_493 = {io_dccm_rdata_lo_r[17],io_dccm_rdata_lo_r[16],io_dccm_rdata_lo_r[15],io_dccm_rdata_lo_r[14],io_dccm_rdata_lo_r[13],io_dccm_rdata_lo_r[12],io_dccm_rdata_lo_r[11]}; // @[lib.scala 193:103]
+  wire [14:0] _T_501 = {io_dccm_rdata_lo_r[25],io_dccm_rdata_lo_r[24],io_dccm_rdata_lo_r[23],io_dccm_rdata_lo_r[22],io_dccm_rdata_lo_r[21],io_dccm_rdata_lo_r[20],io_dccm_rdata_lo_r[19],io_dccm_rdata_lo_r[18],_T_493}; // @[lib.scala 193:103]
   wire  _T_502 = ^_T_501; // @[lib.scala 193:110]
-  wire  _T_503 = io_dccm_data_ecc_lo_m[4] ^ _T_502; // @[lib.scala 193:98]
-  wire [6:0] _T_510 = {io_dccm_rdata_lo_m[10],io_dccm_rdata_lo_m[9],io_dccm_rdata_lo_m[8],io_dccm_rdata_lo_m[7],io_dccm_rdata_lo_m[6],io_dccm_rdata_lo_m[5],io_dccm_rdata_lo_m[4]}; // @[lib.scala 193:130]
-  wire [14:0] _T_518 = {io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[24],io_dccm_rdata_lo_m[23],io_dccm_rdata_lo_m[22],io_dccm_rdata_lo_m[21],io_dccm_rdata_lo_m[20],io_dccm_rdata_lo_m[19],io_dccm_rdata_lo_m[18],_T_510}; // @[lib.scala 193:130]
+  wire  _T_503 = io_dccm_data_ecc_lo_r[4] ^ _T_502; // @[lib.scala 193:98]
+  wire [6:0] _T_510 = {io_dccm_rdata_lo_r[10],io_dccm_rdata_lo_r[9],io_dccm_rdata_lo_r[8],io_dccm_rdata_lo_r[7],io_dccm_rdata_lo_r[6],io_dccm_rdata_lo_r[5],io_dccm_rdata_lo_r[4]}; // @[lib.scala 193:130]
+  wire [14:0] _T_518 = {io_dccm_rdata_lo_r[25],io_dccm_rdata_lo_r[24],io_dccm_rdata_lo_r[23],io_dccm_rdata_lo_r[22],io_dccm_rdata_lo_r[21],io_dccm_rdata_lo_r[20],io_dccm_rdata_lo_r[19],io_dccm_rdata_lo_r[18],_T_510}; // @[lib.scala 193:130]
   wire  _T_519 = ^_T_518; // @[lib.scala 193:137]
-  wire  _T_520 = io_dccm_data_ecc_lo_m[3] ^ _T_519; // @[lib.scala 193:125]
-  wire [8:0] _T_529 = {io_dccm_rdata_lo_m[15],io_dccm_rdata_lo_m[14],io_dccm_rdata_lo_m[10],io_dccm_rdata_lo_m[9],io_dccm_rdata_lo_m[8],io_dccm_rdata_lo_m[7],io_dccm_rdata_lo_m[3],io_dccm_rdata_lo_m[2],io_dccm_rdata_lo_m[1]}; // @[lib.scala 193:157]
-  wire [17:0] _T_538 = {io_dccm_rdata_lo_m[31],io_dccm_rdata_lo_m[30],io_dccm_rdata_lo_m[29],io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[24],io_dccm_rdata_lo_m[23],io_dccm_rdata_lo_m[22],io_dccm_rdata_lo_m[17],io_dccm_rdata_lo_m[16],_T_529}; // @[lib.scala 193:157]
+  wire  _T_520 = io_dccm_data_ecc_lo_r[3] ^ _T_519; // @[lib.scala 193:125]
+  wire [8:0] _T_529 = {io_dccm_rdata_lo_r[15],io_dccm_rdata_lo_r[14],io_dccm_rdata_lo_r[10],io_dccm_rdata_lo_r[9],io_dccm_rdata_lo_r[8],io_dccm_rdata_lo_r[7],io_dccm_rdata_lo_r[3],io_dccm_rdata_lo_r[2],io_dccm_rdata_lo_r[1]}; // @[lib.scala 193:157]
+  wire [17:0] _T_538 = {io_dccm_rdata_lo_r[31],io_dccm_rdata_lo_r[30],io_dccm_rdata_lo_r[29],io_dccm_rdata_lo_r[25],io_dccm_rdata_lo_r[24],io_dccm_rdata_lo_r[23],io_dccm_rdata_lo_r[22],io_dccm_rdata_lo_r[17],io_dccm_rdata_lo_r[16],_T_529}; // @[lib.scala 193:157]
   wire  _T_539 = ^_T_538; // @[lib.scala 193:164]
-  wire  _T_540 = io_dccm_data_ecc_lo_m[2] ^ _T_539; // @[lib.scala 193:152]
-  wire [8:0] _T_549 = {io_dccm_rdata_lo_m[13],io_dccm_rdata_lo_m[12],io_dccm_rdata_lo_m[10],io_dccm_rdata_lo_m[9],io_dccm_rdata_lo_m[6],io_dccm_rdata_lo_m[5],io_dccm_rdata_lo_m[3],io_dccm_rdata_lo_m[2],io_dccm_rdata_lo_m[0]}; // @[lib.scala 193:184]
-  wire [17:0] _T_558 = {io_dccm_rdata_lo_m[31],io_dccm_rdata_lo_m[28],io_dccm_rdata_lo_m[27],io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[24],io_dccm_rdata_lo_m[21],io_dccm_rdata_lo_m[20],io_dccm_rdata_lo_m[17],io_dccm_rdata_lo_m[16],_T_549}; // @[lib.scala 193:184]
+  wire  _T_540 = io_dccm_data_ecc_lo_r[2] ^ _T_539; // @[lib.scala 193:152]
+  wire [8:0] _T_549 = {io_dccm_rdata_lo_r[13],io_dccm_rdata_lo_r[12],io_dccm_rdata_lo_r[10],io_dccm_rdata_lo_r[9],io_dccm_rdata_lo_r[6],io_dccm_rdata_lo_r[5],io_dccm_rdata_lo_r[3],io_dccm_rdata_lo_r[2],io_dccm_rdata_lo_r[0]}; // @[lib.scala 193:184]
+  wire [17:0] _T_558 = {io_dccm_rdata_lo_r[31],io_dccm_rdata_lo_r[28],io_dccm_rdata_lo_r[27],io_dccm_rdata_lo_r[25],io_dccm_rdata_lo_r[24],io_dccm_rdata_lo_r[21],io_dccm_rdata_lo_r[20],io_dccm_rdata_lo_r[17],io_dccm_rdata_lo_r[16],_T_549}; // @[lib.scala 193:184]
   wire  _T_559 = ^_T_558; // @[lib.scala 193:191]
-  wire  _T_560 = io_dccm_data_ecc_lo_m[1] ^ _T_559; // @[lib.scala 193:179]
-  wire [8:0] _T_569 = {io_dccm_rdata_lo_m[13],io_dccm_rdata_lo_m[11],io_dccm_rdata_lo_m[10],io_dccm_rdata_lo_m[8],io_dccm_rdata_lo_m[6],io_dccm_rdata_lo_m[4],io_dccm_rdata_lo_m[3],io_dccm_rdata_lo_m[1],io_dccm_rdata_lo_m[0]}; // @[lib.scala 193:211]
-  wire [17:0] _T_578 = {io_dccm_rdata_lo_m[30],io_dccm_rdata_lo_m[28],io_dccm_rdata_lo_m[26],io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[23],io_dccm_rdata_lo_m[21],io_dccm_rdata_lo_m[19],io_dccm_rdata_lo_m[17],io_dccm_rdata_lo_m[15],_T_569}; // @[lib.scala 193:211]
+  wire  _T_560 = io_dccm_data_ecc_lo_r[1] ^ _T_559; // @[lib.scala 193:179]
+  wire [8:0] _T_569 = {io_dccm_rdata_lo_r[13],io_dccm_rdata_lo_r[11],io_dccm_rdata_lo_r[10],io_dccm_rdata_lo_r[8],io_dccm_rdata_lo_r[6],io_dccm_rdata_lo_r[4],io_dccm_rdata_lo_r[3],io_dccm_rdata_lo_r[1],io_dccm_rdata_lo_r[0]}; // @[lib.scala 193:211]
+  wire [17:0] _T_578 = {io_dccm_rdata_lo_r[30],io_dccm_rdata_lo_r[28],io_dccm_rdata_lo_r[26],io_dccm_rdata_lo_r[25],io_dccm_rdata_lo_r[23],io_dccm_rdata_lo_r[21],io_dccm_rdata_lo_r[19],io_dccm_rdata_lo_r[17],io_dccm_rdata_lo_r[15],_T_569}; // @[lib.scala 193:211]
   wire  _T_579 = ^_T_578; // @[lib.scala 193:218]
-  wire  _T_580 = io_dccm_data_ecc_lo_m[0] ^ _T_579; // @[lib.scala 193:206]
+  wire  _T_580 = io_dccm_data_ecc_lo_r[0] ^ _T_579; // @[lib.scala 193:206]
   wire [6:0] _T_586 = {_T_476,_T_486,_T_503,_T_520,_T_540,_T_560,_T_580}; // @[Cat.scala 29:58]
   wire  _T_587 = _T_586 != 7'h0; // @[lib.scala 194:44]
-  wire  is_ldst_lo_m = is_ldst_m & _T_1130; // @[lsu_ecc.scala 125:33]
-  wire  _T_588 = is_ldst_lo_m & _T_587; // @[lib.scala 194:32]
+  wire  is_ldst_lo_r = is_ldst_r & _T_1130; // @[lsu_ecc.scala 105:31]
+  wire  _T_588 = is_ldst_lo_r & _T_587; // @[lib.scala 194:32]
   wire  single_ecc_error_lo_any = _T_588 & _T_586[6]; // @[lib.scala 194:53]
   wire  _T_593 = ~_T_586[6]; // @[lib.scala 195:55]
   wire  double_ecc_error_lo_any = _T_588 & _T_593; // @[lib.scala 195:53]
@@ -3897,8 +4003,8 @@ module lsu_ecc(
   wire  _T_668 = _T_586[5:0] == 6'h25; // @[lib.scala 199:41]
   wire  _T_670 = _T_586[5:0] == 6'h26; // @[lib.scala 199:41]
   wire  _T_672 = _T_586[5:0] == 6'h27; // @[lib.scala 199:41]
-  wire [7:0] _T_687 = {io_dccm_data_ecc_lo_m[3],io_dccm_rdata_lo_m[3:1],io_dccm_data_ecc_lo_m[2],io_dccm_rdata_lo_m[0],io_dccm_data_ecc_lo_m[1:0]}; // @[Cat.scala 29:58]
-  wire [38:0] _T_693 = {io_dccm_data_ecc_lo_m[6],io_dccm_rdata_lo_m[31:26],io_dccm_data_ecc_lo_m[5],io_dccm_rdata_lo_m[25:11],io_dccm_data_ecc_lo_m[4],io_dccm_rdata_lo_m[10:4],_T_687}; // @[Cat.scala 29:58]
+  wire [7:0] _T_687 = {io_dccm_data_ecc_lo_r[3],io_dccm_rdata_lo_r[3:1],io_dccm_data_ecc_lo_r[2],io_dccm_rdata_lo_r[0],io_dccm_data_ecc_lo_r[1:0]}; // @[Cat.scala 29:58]
+  wire [38:0] _T_693 = {io_dccm_data_ecc_lo_r[6],io_dccm_rdata_lo_r[31:26],io_dccm_data_ecc_lo_r[5],io_dccm_rdata_lo_r[25:11],io_dccm_data_ecc_lo_r[4],io_dccm_rdata_lo_r[10:4],_T_687}; // @[Cat.scala 29:58]
   wire [9:0] _T_711 = {_T_632,_T_630,_T_628,_T_626,_T_624,_T_622,_T_620,_T_618,_T_616,_T_614}; // @[lib.scala 202:69]
   wire [18:0] _T_712 = {_T_711,_T_612,_T_610,_T_608,_T_606,_T_604,_T_602,_T_600,_T_598,_T_596}; // @[lib.scala 202:69]
   wire [9:0] _T_721 = {_T_652,_T_650,_T_648,_T_646,_T_644,_T_642,_T_640,_T_638,_T_636,_T_634}; // @[lib.scala 202:69]
@@ -4088,42 +4194,31 @@ module lsu_ecc(
   wire  _T_1117 = ^dccm_wdata_hi_any; // @[lib.scala 127:13]
   wire  _T_1118 = ^_T_1116; // @[lib.scala 127:23]
   wire  _T_1119 = _T_1117 ^ _T_1118; // @[lib.scala 127:18]
-  reg  _T_1149; // @[lsu_ecc.scala 140:72]
-  reg  _T_1150; // @[lsu_ecc.scala 141:72]
-  reg  _T_1151; // @[lsu_ecc.scala 142:72]
-  reg  _T_1152; // @[lsu_ecc.scala 143:72]
-  reg [31:0] _T_1154; // @[lib.scala 374:16]
-  reg [31:0] _T_1156; // @[lib.scala 374:16]
-  reg [31:0] _T_1166; // @[lib.scala 374:16]
-  reg [31:0] _T_1168; // @[lib.scala 374:16]
-  rvclkhdr rvclkhdr ( // @[lib.scala 368:23]
+  wire  _T_1165 = io_ld_single_ecc_error_r | io_clk_override; // @[lsu_ecc.scala 156:75]
+  reg [31:0] _T_1166; // @[Reg.scala 27:20]
+  reg [31:0] _T_1168; // @[Reg.scala 27:20]
+  rvclkhdr rvclkhdr ( // @[lib.scala 390:23]
     .io_l1clk(rvclkhdr_io_l1clk),
     .io_clk(rvclkhdr_io_clk),
-    .io_en(rvclkhdr_io_en),
-    .io_scan_mode(rvclkhdr_io_scan_mode)
+    .io_en(rvclkhdr_io_en)
   );
-  rvclkhdr rvclkhdr_1 ( // @[lib.scala 368:23]
+  rvclkhdr rvclkhdr_1 ( // @[lib.scala 390:23]
     .io_l1clk(rvclkhdr_1_io_l1clk),
     .io_clk(rvclkhdr_1_io_clk),
-    .io_en(rvclkhdr_1_io_en),
-    .io_scan_mode(rvclkhdr_1_io_scan_mode)
+    .io_en(rvclkhdr_1_io_en)
   );
-  rvclkhdr rvclkhdr_2 ( // @[lib.scala 368:23]
+  rvclkhdr rvclkhdr_2 ( // @[lib.scala 390:23]
     .io_l1clk(rvclkhdr_2_io_l1clk),
     .io_clk(rvclkhdr_2_io_clk),
-    .io_en(rvclkhdr_2_io_en),
-    .io_scan_mode(rvclkhdr_2_io_scan_mode)
+    .io_en(rvclkhdr_2_io_en)
   );
-  rvclkhdr rvclkhdr_3 ( // @[lib.scala 368:23]
+  rvclkhdr rvclkhdr_3 ( // @[lib.scala 390:23]
     .io_l1clk(rvclkhdr_3_io_l1clk),
     .io_clk(rvclkhdr_3_io_clk),
-    .io_en(rvclkhdr_3_io_en),
-    .io_scan_mode(rvclkhdr_3_io_scan_mode)
+    .io_en(rvclkhdr_3_io_en)
   );
-  assign io_sec_data_hi_r = _T_1154; // @[lsu_ecc.scala 113:22 lsu_ecc.scala 144:34]
-  assign io_sec_data_lo_r = _T_1156; // @[lsu_ecc.scala 116:25 lsu_ecc.scala 145:34]
-  assign io_sec_data_hi_m = {_T_364,_T_362}; // @[lsu_ecc.scala 89:32 lsu_ecc.scala 133:27]
-  assign io_sec_data_lo_m = {_T_742,_T_740}; // @[lsu_ecc.scala 90:32 lsu_ecc.scala 135:27]
+  assign io_sec_data_hi_r = {_T_364,_T_362}; // @[lsu_ecc.scala 113:22 lsu_ecc.scala 144:34]
+  assign io_sec_data_lo_r = {_T_742,_T_740}; // @[lsu_ecc.scala 116:25 lsu_ecc.scala 145:34]
   assign io_sec_data_hi_r_ff = _T_1166; // @[lsu_ecc.scala 156:23]
   assign io_sec_data_lo_r_ff = _T_1168; // @[lsu_ecc.scala 157:23]
   assign io_dma_dccm_wdata_ecc_hi = {_T_1119,_T_1116}; // @[lsu_ecc.scala 153:28]
@@ -4131,24 +4226,19 @@ module lsu_ecc(
   assign io_stbuf_ecc_any = {_T_937,_T_934}; // @[lsu_ecc.scala 152:28]
   assign io_sec_data_ecc_hi_r_ff = {_T_1119,_T_1116}; // @[lsu_ecc.scala 150:28]
   assign io_sec_data_ecc_lo_r_ff = {_T_937,_T_934}; // @[lsu_ecc.scala 151:28]
-  assign io_single_ecc_error_hi_r = _T_1152; // @[lsu_ecc.scala 114:31 lsu_ecc.scala 143:62]
-  assign io_single_ecc_error_lo_r = _T_1151; // @[lsu_ecc.scala 117:31 lsu_ecc.scala 142:62]
-  assign io_lsu_single_ecc_error_r = _T_1149; // @[lsu_ecc.scala 119:31 lsu_ecc.scala 140:62]
-  assign io_lsu_double_ecc_error_r = _T_1150; // @[lsu_ecc.scala 120:31 lsu_ecc.scala 141:62]
-  assign io_lsu_single_ecc_error_m = single_ecc_error_hi_any | single_ecc_error_lo_any; // @[lsu_ecc.scala 91:30 lsu_ecc.scala 137:33]
-  assign io_lsu_double_ecc_error_m = double_ecc_error_hi_any | double_ecc_error_lo_any; // @[lsu_ecc.scala 92:30 lsu_ecc.scala 138:33]
-  assign rvclkhdr_io_clk = clock; // @[lib.scala 370:18]
-  assign rvclkhdr_io_en = io_lsu_single_ecc_error_m | io_clk_override; // @[lib.scala 371:17]
-  assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
-  assign rvclkhdr_1_io_clk = clock; // @[lib.scala 370:18]
-  assign rvclkhdr_1_io_en = io_lsu_single_ecc_error_m | io_clk_override; // @[lib.scala 371:17]
-  assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
-  assign rvclkhdr_2_io_clk = clock; // @[lib.scala 370:18]
-  assign rvclkhdr_2_io_en = io_ld_single_ecc_error_r | io_clk_override; // @[lib.scala 371:17]
-  assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
-  assign rvclkhdr_3_io_clk = clock; // @[lib.scala 370:18]
-  assign rvclkhdr_3_io_en = io_ld_single_ecc_error_r | io_clk_override; // @[lib.scala 371:17]
-  assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
+  assign io_single_ecc_error_hi_r = _T_210 & _T_208[6]; // @[lsu_ecc.scala 114:31 lsu_ecc.scala 143:62]
+  assign io_single_ecc_error_lo_r = _T_588 & _T_586[6]; // @[lsu_ecc.scala 117:31 lsu_ecc.scala 142:62]
+  assign io_lsu_single_ecc_error_r = io_single_ecc_error_hi_r | io_single_ecc_error_lo_r; // @[lsu_ecc.scala 119:31 lsu_ecc.scala 140:62]
+  assign io_lsu_double_ecc_error_r = double_ecc_error_hi_any | double_ecc_error_lo_any; // @[lsu_ecc.scala 120:31 lsu_ecc.scala 141:62]
+  assign io_lsu_single_ecc_error_m = 1'h0; // @[lsu_ecc.scala 91:30 lsu_ecc.scala 137:33]
+  assign rvclkhdr_io_clk = clock; // @[lib.scala 392:18]
+  assign rvclkhdr_io_en = io_lsu_single_ecc_error_m | io_clk_override; // @[lib.scala 393:17]
+  assign rvclkhdr_1_io_clk = clock; // @[lib.scala 392:18]
+  assign rvclkhdr_1_io_en = io_lsu_single_ecc_error_m | io_clk_override; // @[lib.scala 393:17]
+  assign rvclkhdr_2_io_clk = clock; // @[lib.scala 392:18]
+  assign rvclkhdr_2_io_en = io_ld_single_ecc_error_r | io_clk_override; // @[lib.scala 393:17]
+  assign rvclkhdr_3_io_clk = clock; // @[lib.scala 392:18]
+  assign rvclkhdr_3_io_en = io_ld_single_ecc_error_r | io_clk_override; // @[lib.scala 393:17]
 `ifdef RANDOMIZE_GARBAGE_ASSIGN
 `define RANDOMIZE
 `endif
@@ -4185,40 +4275,10 @@ initial begin
     `endif
 `ifdef RANDOMIZE_REG_INIT
   _RAND_0 = {1{`RANDOM}};
-  _T_1149 = _RAND_0[0:0];
+  _T_1166 = _RAND_0[31:0];
   _RAND_1 = {1{`RANDOM}};
-  _T_1150 = _RAND_1[0:0];
-  _RAND_2 = {1{`RANDOM}};
-  _T_1151 = _RAND_2[0:0];
-  _RAND_3 = {1{`RANDOM}};
-  _T_1152 = _RAND_3[0:0];
-  _RAND_4 = {1{`RANDOM}};
-  _T_1154 = _RAND_4[31:0];
-  _RAND_5 = {1{`RANDOM}};
-  _T_1156 = _RAND_5[31:0];
-  _RAND_6 = {1{`RANDOM}};
-  _T_1166 = _RAND_6[31:0];
-  _RAND_7 = {1{`RANDOM}};
-  _T_1168 = _RAND_7[31:0];
+  _T_1168 = _RAND_1[31:0];
 `endif // RANDOMIZE_REG_INIT
-  if (reset) begin
-    _T_1149 = 1'h0;
-  end
-  if (reset) begin
-    _T_1150 = 1'h0;
-  end
-  if (reset) begin
-    _T_1151 = 1'h0;
-  end
-  if (reset) begin
-    _T_1152 = 1'h0;
-  end
-  if (reset) begin
-    _T_1154 = 32'h0;
-  end
-  if (reset) begin
-    _T_1156 = 32'h0;
-  end
   if (reset) begin
     _T_1166 = 32'h0;
   end
@@ -4231,59 +4291,17 @@ end // initial
 `FIRRTL_AFTER_INITIAL
 `endif
 `endif // SYNTHESIS
-  always @(posedge io_lsu_c2_r_clk or posedge reset) begin
-    if (reset) begin
-      _T_1149 <= 1'h0;
-    end else begin
-      _T_1149 <= io_lsu_single_ecc_error_m;
-    end
-  end
-  always @(posedge io_lsu_c2_r_clk or posedge reset) begin
-    if (reset) begin
-      _T_1150 <= 1'h0;
-    end else begin
-      _T_1150 <= io_lsu_double_ecc_error_m;
-    end
-  end
-  always @(posedge io_lsu_c2_r_clk or posedge reset) begin
-    if (reset) begin
-      _T_1151 <= 1'h0;
-    end else begin
-      _T_1151 <= _T_588 & _T_586[6];
-    end
-  end
-  always @(posedge io_lsu_c2_r_clk or posedge reset) begin
-    if (reset) begin
-      _T_1152 <= 1'h0;
-    end else begin
-      _T_1152 <= _T_210 & _T_208[6];
-    end
-  end
-  always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
-    if (reset) begin
-      _T_1154 <= 32'h0;
-    end else begin
-      _T_1154 <= io_sec_data_hi_m;
-    end
-  end
-  always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin
-    if (reset) begin
-      _T_1156 <= 32'h0;
-    end else begin
-      _T_1156 <= io_sec_data_lo_m;
-    end
-  end
-  always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
+  always @(posedge clock or posedge reset) begin
     if (reset) begin
       _T_1166 <= 32'h0;
-    end else begin
+    end else if (_T_1165) begin
       _T_1166 <= io_sec_data_hi_r;
     end
   end
-  always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin
+  always @(posedge clock or posedge reset) begin
     if (reset) begin
       _T_1168 <= 32'h0;
-    end else begin
+    end else if (_T_1165) begin
       _T_1168 <= io_sec_data_lo_r;
     end
   end
@@ -4950,66 +4968,51 @@ module lsu_clkdomain(
   output  io_lsu_store_c1_m_clk,
   output  io_lsu_store_c1_r_clk,
   output  io_lsu_stbuf_c1_clk,
-  output  io_lsu_bus_obuf_c1_clk,
   output  io_lsu_bus_ibuf_c1_clk,
   output  io_lsu_bus_buf_c1_clk,
-  output  io_lsu_busm_clk,
-  output  io_lsu_free_c2_clk,
-  input   io_scan_mode
+  output  io_lsu_free_c2_clk
 );
 `ifdef RANDOMIZE_REG_INIT
   reg [31:0] _RAND_0;
   reg [31:0] _RAND_1;
   reg [31:0] _RAND_2;
 `endif // RANDOMIZE_REG_INIT
-  wire  rvclkhdr_io_l1clk; // @[lib.scala 343:22]
-  wire  rvclkhdr_io_clk; // @[lib.scala 343:22]
-  wire  rvclkhdr_io_en; // @[lib.scala 343:22]
-  wire  rvclkhdr_io_scan_mode; // @[lib.scala 343:22]
-  wire  rvclkhdr_1_io_l1clk; // @[lib.scala 343:22]
-  wire  rvclkhdr_1_io_clk; // @[lib.scala 343:22]
-  wire  rvclkhdr_1_io_en; // @[lib.scala 343:22]
-  wire  rvclkhdr_1_io_scan_mode; // @[lib.scala 343:22]
-  wire  rvclkhdr_2_io_l1clk; // @[lib.scala 343:22]
-  wire  rvclkhdr_2_io_clk; // @[lib.scala 343:22]
-  wire  rvclkhdr_2_io_en; // @[lib.scala 343:22]
-  wire  rvclkhdr_2_io_scan_mode; // @[lib.scala 343:22]
-  wire  rvclkhdr_3_io_l1clk; // @[lib.scala 343:22]
-  wire  rvclkhdr_3_io_clk; // @[lib.scala 343:22]
-  wire  rvclkhdr_3_io_en; // @[lib.scala 343:22]
-  wire  rvclkhdr_3_io_scan_mode; // @[lib.scala 343:22]
-  wire  rvclkhdr_4_io_l1clk; // @[lib.scala 343:22]
-  wire  rvclkhdr_4_io_clk; // @[lib.scala 343:22]
-  wire  rvclkhdr_4_io_en; // @[lib.scala 343:22]
-  wire  rvclkhdr_4_io_scan_mode; // @[lib.scala 343:22]
-  wire  rvclkhdr_5_io_l1clk; // @[lib.scala 343:22]
-  wire  rvclkhdr_5_io_clk; // @[lib.scala 343:22]
-  wire  rvclkhdr_5_io_en; // @[lib.scala 343:22]
-  wire  rvclkhdr_5_io_scan_mode; // @[lib.scala 343:22]
-  wire  rvclkhdr_6_io_l1clk; // @[lib.scala 343:22]
-  wire  rvclkhdr_6_io_clk; // @[lib.scala 343:22]
-  wire  rvclkhdr_6_io_en; // @[lib.scala 343:22]
-  wire  rvclkhdr_6_io_scan_mode; // @[lib.scala 343:22]
-  wire  rvclkhdr_7_io_l1clk; // @[lib.scala 343:22]
-  wire  rvclkhdr_7_io_clk; // @[lib.scala 343:22]
-  wire  rvclkhdr_7_io_en; // @[lib.scala 343:22]
-  wire  rvclkhdr_7_io_scan_mode; // @[lib.scala 343:22]
+  wire  rvclkhdr_io_l1clk; // @[lib.scala 352:22]
+  wire  rvclkhdr_io_clk; // @[lib.scala 352:22]
+  wire  rvclkhdr_io_en; // @[lib.scala 352:22]
+  wire  rvclkhdr_1_io_l1clk; // @[lib.scala 352:22]
+  wire  rvclkhdr_1_io_clk; // @[lib.scala 352:22]
+  wire  rvclkhdr_1_io_en; // @[lib.scala 352:22]
+  wire  rvclkhdr_2_io_l1clk; // @[lib.scala 352:22]
+  wire  rvclkhdr_2_io_clk; // @[lib.scala 352:22]
+  wire  rvclkhdr_2_io_en; // @[lib.scala 352:22]
+  wire  rvclkhdr_3_io_l1clk; // @[lib.scala 352:22]
+  wire  rvclkhdr_3_io_clk; // @[lib.scala 352:22]
+  wire  rvclkhdr_3_io_en; // @[lib.scala 352:22]
+  wire  rvclkhdr_4_io_l1clk; // @[lib.scala 352:22]
+  wire  rvclkhdr_4_io_clk; // @[lib.scala 352:22]
+  wire  rvclkhdr_4_io_en; // @[lib.scala 352:22]
+  wire  rvclkhdr_5_io_l1clk; // @[lib.scala 352:22]
+  wire  rvclkhdr_5_io_clk; // @[lib.scala 352:22]
+  wire  rvclkhdr_5_io_en; // @[lib.scala 352:22]
+  wire  rvclkhdr_6_io_l1clk; // @[lib.scala 352:22]
+  wire  rvclkhdr_6_io_clk; // @[lib.scala 352:22]
+  wire  rvclkhdr_6_io_en; // @[lib.scala 352:22]
+  wire  rvclkhdr_7_io_l1clk; // @[lib.scala 352:22]
+  wire  rvclkhdr_7_io_clk; // @[lib.scala 352:22]
+  wire  rvclkhdr_7_io_en; // @[lib.scala 352:22]
   wire  rvclkhdr_8_io_l1clk; // @[lib.scala 343:22]
   wire  rvclkhdr_8_io_clk; // @[lib.scala 343:22]
   wire  rvclkhdr_8_io_en; // @[lib.scala 343:22]
-  wire  rvclkhdr_8_io_scan_mode; // @[lib.scala 343:22]
-  wire  rvclkhdr_9_io_l1clk; // @[lib.scala 343:22]
-  wire  rvclkhdr_9_io_clk; // @[lib.scala 343:22]
-  wire  rvclkhdr_9_io_en; // @[lib.scala 343:22]
-  wire  rvclkhdr_9_io_scan_mode; // @[lib.scala 343:22]
+  wire  rvclkhdr_9_io_l1clk; // @[lib.scala 352:22]
+  wire  rvclkhdr_9_io_clk; // @[lib.scala 352:22]
+  wire  rvclkhdr_9_io_en; // @[lib.scala 352:22]
   wire  rvclkhdr_10_io_l1clk; // @[lib.scala 343:22]
   wire  rvclkhdr_10_io_clk; // @[lib.scala 343:22]
   wire  rvclkhdr_10_io_en; // @[lib.scala 343:22]
-  wire  rvclkhdr_10_io_scan_mode; // @[lib.scala 343:22]
-  wire  rvclkhdr_11_io_l1clk; // @[lib.scala 343:22]
-  wire  rvclkhdr_11_io_clk; // @[lib.scala 343:22]
-  wire  rvclkhdr_11_io_en; // @[lib.scala 343:22]
-  wire  rvclkhdr_11_io_scan_mode; // @[lib.scala 343:22]
+  wire  rvclkhdr_11_io_l1clk; // @[lib.scala 352:22]
+  wire  rvclkhdr_11_io_clk; // @[lib.scala 352:22]
+  wire  rvclkhdr_11_io_en; // @[lib.scala 352:22]
   wire  _T = io_lsu_p_valid | io_dma_dccm_req; // @[lsu_clkdomain.scala 64:47]
   wire  lsu_c1_m_clken = _T | io_clk_override; // @[lsu_clkdomain.scala 64:65]
   reg  lsu_c1_m_clken_q; // @[lsu_clkdomain.scala 84:67]
@@ -5037,77 +5040,65 @@ module lsu_clkdomain(
   reg  lsu_free_c1_clken_q; // @[lsu_clkdomain.scala 82:62]
   wire  _T_21 = lsu_free_c1_clken | lsu_free_c1_clken_q; // @[lsu_clkdomain.scala 78:50]
   wire  _T_24 = _T_12 | io_clk_override; // @[lsu_clkdomain.scala 79:72]
-  rvclkhdr rvclkhdr ( // @[lib.scala 343:22]
+  rvclkhdr rvclkhdr ( // @[lib.scala 352:22]
     .io_l1clk(rvclkhdr_io_l1clk),
     .io_clk(rvclkhdr_io_clk),
-    .io_en(rvclkhdr_io_en),
-    .io_scan_mode(rvclkhdr_io_scan_mode)
+    .io_en(rvclkhdr_io_en)
   );
-  rvclkhdr rvclkhdr_1 ( // @[lib.scala 343:22]
+  rvclkhdr rvclkhdr_1 ( // @[lib.scala 352:22]
     .io_l1clk(rvclkhdr_1_io_l1clk),
     .io_clk(rvclkhdr_1_io_clk),
-    .io_en(rvclkhdr_1_io_en),
-    .io_scan_mode(rvclkhdr_1_io_scan_mode)
+    .io_en(rvclkhdr_1_io_en)
   );
-  rvclkhdr rvclkhdr_2 ( // @[lib.scala 343:22]
+  rvclkhdr rvclkhdr_2 ( // @[lib.scala 352:22]
     .io_l1clk(rvclkhdr_2_io_l1clk),
     .io_clk(rvclkhdr_2_io_clk),
-    .io_en(rvclkhdr_2_io_en),
-    .io_scan_mode(rvclkhdr_2_io_scan_mode)
+    .io_en(rvclkhdr_2_io_en)
   );
-  rvclkhdr rvclkhdr_3 ( // @[lib.scala 343:22]
+  rvclkhdr rvclkhdr_3 ( // @[lib.scala 352:22]
     .io_l1clk(rvclkhdr_3_io_l1clk),
     .io_clk(rvclkhdr_3_io_clk),
-    .io_en(rvclkhdr_3_io_en),
-    .io_scan_mode(rvclkhdr_3_io_scan_mode)
+    .io_en(rvclkhdr_3_io_en)
   );
-  rvclkhdr rvclkhdr_4 ( // @[lib.scala 343:22]
+  rvclkhdr rvclkhdr_4 ( // @[lib.scala 352:22]
     .io_l1clk(rvclkhdr_4_io_l1clk),
     .io_clk(rvclkhdr_4_io_clk),
-    .io_en(rvclkhdr_4_io_en),
-    .io_scan_mode(rvclkhdr_4_io_scan_mode)
+    .io_en(rvclkhdr_4_io_en)
   );
-  rvclkhdr rvclkhdr_5 ( // @[lib.scala 343:22]
+  rvclkhdr rvclkhdr_5 ( // @[lib.scala 352:22]
     .io_l1clk(rvclkhdr_5_io_l1clk),
     .io_clk(rvclkhdr_5_io_clk),
-    .io_en(rvclkhdr_5_io_en),
-    .io_scan_mode(rvclkhdr_5_io_scan_mode)
+    .io_en(rvclkhdr_5_io_en)
   );
-  rvclkhdr rvclkhdr_6 ( // @[lib.scala 343:22]
+  rvclkhdr rvclkhdr_6 ( // @[lib.scala 352:22]
     .io_l1clk(rvclkhdr_6_io_l1clk),
     .io_clk(rvclkhdr_6_io_clk),
-    .io_en(rvclkhdr_6_io_en),
-    .io_scan_mode(rvclkhdr_6_io_scan_mode)
+    .io_en(rvclkhdr_6_io_en)
   );
-  rvclkhdr rvclkhdr_7 ( // @[lib.scala 343:22]
+  rvclkhdr rvclkhdr_7 ( // @[lib.scala 352:22]
     .io_l1clk(rvclkhdr_7_io_l1clk),
     .io_clk(rvclkhdr_7_io_clk),
-    .io_en(rvclkhdr_7_io_en),
-    .io_scan_mode(rvclkhdr_7_io_scan_mode)
+    .io_en(rvclkhdr_7_io_en)
   );
   rvclkhdr rvclkhdr_8 ( // @[lib.scala 343:22]
     .io_l1clk(rvclkhdr_8_io_l1clk),
     .io_clk(rvclkhdr_8_io_clk),
-    .io_en(rvclkhdr_8_io_en),
-    .io_scan_mode(rvclkhdr_8_io_scan_mode)
+    .io_en(rvclkhdr_8_io_en)
   );
-  rvclkhdr rvclkhdr_9 ( // @[lib.scala 343:22]
+  rvclkhdr rvclkhdr_9 ( // @[lib.scala 352:22]
     .io_l1clk(rvclkhdr_9_io_l1clk),
     .io_clk(rvclkhdr_9_io_clk),
-    .io_en(rvclkhdr_9_io_en),
-    .io_scan_mode(rvclkhdr_9_io_scan_mode)
+    .io_en(rvclkhdr_9_io_en)
   );
   rvclkhdr rvclkhdr_10 ( // @[lib.scala 343:22]
     .io_l1clk(rvclkhdr_10_io_l1clk),
     .io_clk(rvclkhdr_10_io_clk),
-    .io_en(rvclkhdr_10_io_en),
-    .io_scan_mode(rvclkhdr_10_io_scan_mode)
+    .io_en(rvclkhdr_10_io_en)
   );
-  rvclkhdr rvclkhdr_11 ( // @[lib.scala 343:22]
+  rvclkhdr rvclkhdr_11 ( // @[lib.scala 352:22]
     .io_l1clk(rvclkhdr_11_io_l1clk),
     .io_clk(rvclkhdr_11_io_clk),
-    .io_en(rvclkhdr_11_io_en),
-    .io_scan_mode(rvclkhdr_11_io_scan_mode)
+    .io_en(rvclkhdr_11_io_en)
   );
   assign io_lsu_bus_obuf_c1_clken = _T_9 & io_lsu_bus_clk_en; // @[lsu_clkdomain.scala 74:30]
   assign io_lsu_busm_clken = _T_24 & io_lsu_bus_clk_en; // @[lsu_clkdomain.scala 79:21]
@@ -5118,47 +5109,33 @@ module lsu_clkdomain(
   assign io_lsu_store_c1_m_clk = rvclkhdr_4_io_l1clk; // @[lsu_clkdomain.scala 91:26]
   assign io_lsu_store_c1_r_clk = rvclkhdr_5_io_l1clk; // @[lsu_clkdomain.scala 92:26]
   assign io_lsu_stbuf_c1_clk = rvclkhdr_6_io_l1clk; // @[lsu_clkdomain.scala 93:26]
-  assign io_lsu_bus_obuf_c1_clk = rvclkhdr_8_io_l1clk; // @[lsu_clkdomain.scala 95:26]
   assign io_lsu_bus_ibuf_c1_clk = rvclkhdr_7_io_l1clk; // @[lsu_clkdomain.scala 94:26]
   assign io_lsu_bus_buf_c1_clk = rvclkhdr_9_io_l1clk; // @[lsu_clkdomain.scala 96:26]
-  assign io_lsu_busm_clk = rvclkhdr_10_io_l1clk; // @[lsu_clkdomain.scala 97:26]
   assign io_lsu_free_c2_clk = rvclkhdr_11_io_l1clk; // @[lsu_clkdomain.scala 98:26]
-  assign rvclkhdr_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_io_en = _T | io_clk_override; // @[lib.scala 345:16]
-  assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
-  assign rvclkhdr_1_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_1_io_en = _T_1 | io_clk_override; // @[lib.scala 345:16]
-  assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
-  assign rvclkhdr_2_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_2_io_en = _T_2 | io_clk_override; // @[lib.scala 345:16]
-  assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
-  assign rvclkhdr_3_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_3_io_en = _T_3 | io_clk_override; // @[lib.scala 345:16]
-  assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
-  assign rvclkhdr_4_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_4_io_en = _T_4 | io_clk_override; // @[lib.scala 345:16]
-  assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
-  assign rvclkhdr_5_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_5_io_en = _T_5 | io_clk_override; // @[lib.scala 345:16]
-  assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
-  assign rvclkhdr_6_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_6_io_en = _T_7 | io_clk_override; // @[lib.scala 345:16]
-  assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
-  assign rvclkhdr_7_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_7_io_en = io_lsu_busreq_r | io_clk_override; // @[lib.scala 345:16]
-  assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
+  assign rvclkhdr_io_clk = clock; // @[lib.scala 353:17]
+  assign rvclkhdr_io_en = _T | io_clk_override; // @[lib.scala 354:16]
+  assign rvclkhdr_1_io_clk = clock; // @[lib.scala 353:17]
+  assign rvclkhdr_1_io_en = _T_1 | io_clk_override; // @[lib.scala 354:16]
+  assign rvclkhdr_2_io_clk = clock; // @[lib.scala 353:17]
+  assign rvclkhdr_2_io_en = _T_2 | io_clk_override; // @[lib.scala 354:16]
+  assign rvclkhdr_3_io_clk = clock; // @[lib.scala 353:17]
+  assign rvclkhdr_3_io_en = _T_3 | io_clk_override; // @[lib.scala 354:16]
+  assign rvclkhdr_4_io_clk = clock; // @[lib.scala 353:17]
+  assign rvclkhdr_4_io_en = _T_4 | io_clk_override; // @[lib.scala 354:16]
+  assign rvclkhdr_5_io_clk = clock; // @[lib.scala 353:17]
+  assign rvclkhdr_5_io_en = _T_5 | io_clk_override; // @[lib.scala 354:16]
+  assign rvclkhdr_6_io_clk = clock; // @[lib.scala 353:17]
+  assign rvclkhdr_6_io_en = _T_7 | io_clk_override; // @[lib.scala 354:16]
+  assign rvclkhdr_7_io_clk = clock; // @[lib.scala 353:17]
+  assign rvclkhdr_7_io_en = io_lsu_busreq_r | io_clk_override; // @[lib.scala 354:16]
   assign rvclkhdr_8_io_clk = clock; // @[lib.scala 344:17]
   assign rvclkhdr_8_io_en = io_lsu_bus_obuf_c1_clken; // @[lib.scala 345:16]
-  assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
-  assign rvclkhdr_9_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_9_io_en = _T_13 | io_clk_override; // @[lib.scala 345:16]
-  assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
+  assign rvclkhdr_9_io_clk = clock; // @[lib.scala 353:17]
+  assign rvclkhdr_9_io_en = _T_13 | io_clk_override; // @[lib.scala 354:16]
   assign rvclkhdr_10_io_clk = clock; // @[lib.scala 344:17]
   assign rvclkhdr_10_io_en = io_lsu_busm_clken; // @[lib.scala 345:16]
-  assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
-  assign rvclkhdr_11_io_clk = clock; // @[lib.scala 344:17]
-  assign rvclkhdr_11_io_en = _T_21 | io_clk_override; // @[lib.scala 345:16]
-  assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[lib.scala 346:23]
+  assign rvclkhdr_11_io_clk = clock; // @[lib.scala 353:17]
+  assign rvclkhdr_11_io_en = _T_21 | io_clk_override; // @[lib.scala 354:16]
 `ifdef RANDOMIZE_GARBAGE_ASSIGN
 `define RANDOMIZE
 `endif
@@ -5241,7 +5218,6 @@ endmodule
 module lsu_bus_buffer(
   input         clock,
   input         reset,
-  input         io_scan_mode,
   output        io_tlu_busbuff_lsu_pmu_bus_trxn,
   output        io_tlu_busbuff_lsu_pmu_bus_misaligned,
   output        io_tlu_busbuff_lsu_pmu_bus_error,
@@ -5263,10 +5239,8 @@ module lsu_bus_buffer(
   input         io_dec_tlu_force_halt,
   input         io_lsu_c2_r_clk,
   input         io_lsu_bus_ibuf_c1_clk,
-  input         io_lsu_bus_obuf_c1_clk,
   input         io_lsu_bus_buf_c1_clk,
   input         io_lsu_free_c2_clk,
-  input         io_lsu_busm_clk,
   input         io_dec_lsu_valid_raw_d,
   input         io_lsu_pkt_m_valid,
   input         io_lsu_pkt_m_bits_load,
@@ -5295,26 +5269,19 @@ module lsu_bus_buffer(
   input  [7:0]  io_ldst_byteen_ext_m,
   input         io_lsu_axi_aw_ready,
   output        io_lsu_axi_aw_valid,
-  output [2:0]  io_lsu_axi_aw_bits_id,
   output [31:0] io_lsu_axi_aw_bits_addr,
   output [3:0]  io_lsu_axi_aw_bits_region,
-  output [2:0]  io_lsu_axi_aw_bits_size,
-  output [3:0]  io_lsu_axi_aw_bits_cache,
   input         io_lsu_axi_w_ready,
   output        io_lsu_axi_w_valid,
   output [63:0] io_lsu_axi_w_bits_data,
-  output [7:0]  io_lsu_axi_w_bits_strb,
   output        io_lsu_axi_b_ready,
   input         io_lsu_axi_b_valid,
   input  [1:0]  io_lsu_axi_b_bits_resp,
   input  [2:0]  io_lsu_axi_b_bits_id,
   input         io_lsu_axi_ar_ready,
   output        io_lsu_axi_ar_valid,
-  output [2:0]  io_lsu_axi_ar_bits_id,
   output [31:0] io_lsu_axi_ar_bits_addr,
   output [3:0]  io_lsu_axi_ar_bits_region,
-  output [2:0]  io_lsu_axi_ar_bits_size,
-  output [3:0]  io_lsu_axi_ar_bits_cache,
   output        io_lsu_axi_r_ready,
   input         io_lsu_axi_r_valid,
   input  [2:0]  io_lsu_axi_r_bits_id,
@@ -5401,7 +5368,7 @@ module lsu_bus_buffer(
   reg [31:0] _RAND_66;
   reg [31:0] _RAND_67;
   reg [31:0] _RAND_68;
-  reg [31:0] _RAND_69;
+  reg [63:0] _RAND_69;
   reg [31:0] _RAND_70;
   reg [31:0] _RAND_71;
   reg [31:0] _RAND_72;
@@ -5412,7 +5379,7 @@ module lsu_bus_buffer(
   reg [31:0] _RAND_77;
   reg [31:0] _RAND_78;
   reg [31:0] _RAND_79;
-  reg [63:0] _RAND_80;
+  reg [31:0] _RAND_80;
   reg [31:0] _RAND_81;
   reg [31:0] _RAND_82;
   reg [31:0] _RAND_83;
@@ -5424,99 +5391,72 @@ module lsu_bus_buffer(
   reg [31:0] _RAND_89;
   reg [31:0] _RAND_90;
   reg [31:0] _RAND_91;
-  reg [31:0] _RAND_92;
-  reg [31:0] _RAND_93;
-  reg [31:0] _RAND_94;
-  reg [31:0] _RAND_95;
-  reg [31:0] _RAND_96;
-  reg [31:0] _RAND_97;
-  reg [31:0] _RAND_98;
-  reg [31:0] _RAND_99;
-  reg [31:0] _RAND_100;
-  reg [31:0] _RAND_101;
-  reg [31:0] _RAND_102;
-  reg [31:0] _RAND_103;
-  reg [31:0] _RAND_104;
-  reg [31:0] _RAND_105;
-  reg [31:0] _RAND_106;
 `endif // RANDOMIZE_REG_INIT
-  wire  rvclkhdr_io_l1clk; // @[lib.scala 368:23]
-  wire  rvclkhdr_io_clk; // @[lib.scala 368:23]
-  wire  rvclkhdr_io_en; // @[lib.scala 368:23]
-  wire  rvclkhdr_io_scan_mode; // @[lib.scala 368:23]
-  wire  rvclkhdr_1_io_l1clk; // @[lib.scala 368:23]
-  wire  rvclkhdr_1_io_clk; // @[lib.scala 368:23]
-  wire  rvclkhdr_1_io_en; // @[lib.scala 368:23]
-  wire  rvclkhdr_1_io_scan_mode; // @[lib.scala 368:23]
-  wire  rvclkhdr_2_io_l1clk; // @[lib.scala 368:23]
-  wire  rvclkhdr_2_io_clk; // @[lib.scala 368:23]
-  wire  rvclkhdr_2_io_en; // @[lib.scala 368:23]
-  wire  rvclkhdr_2_io_scan_mode; // @[lib.scala 368:23]
-  wire  rvclkhdr_3_io_l1clk; // @[lib.scala 368:23]
-  wire  rvclkhdr_3_io_clk; // @[lib.scala 368:23]
-  wire  rvclkhdr_3_io_en; // @[lib.scala 368:23]
-  wire  rvclkhdr_3_io_scan_mode; // @[lib.scala 368:23]
-  wire  rvclkhdr_4_io_l1clk; // @[lib.scala 368:23]
-  wire  rvclkhdr_4_io_clk; // @[lib.scala 368:23]
-  wire  rvclkhdr_4_io_en; // @[lib.scala 368:23]
-  wire  rvclkhdr_4_io_scan_mode; // @[lib.scala 368:23]
-  wire  rvclkhdr_5_io_l1clk; // @[lib.scala 368:23]
-  wire  rvclkhdr_5_io_clk; // @[lib.scala 368:23]
-  wire  rvclkhdr_5_io_en; // @[lib.scala 368:23]
-  wire  rvclkhdr_5_io_scan_mode; // @[lib.scala 368:23]
-  wire  rvclkhdr_6_io_l1clk; // @[lib.scala 368:23]
-  wire  rvclkhdr_6_io_clk; // @[lib.scala 368:23]
-  wire  rvclkhdr_6_io_en; // @[lib.scala 368:23]
-  wire  rvclkhdr_6_io_scan_mode; // @[lib.scala 368:23]
-  wire  rvclkhdr_7_io_l1clk; // @[lib.scala 368:23]
-  wire  rvclkhdr_7_io_clk; // @[lib.scala 368:23]
-  wire  rvclkhdr_7_io_en; // @[lib.scala 368:23]
-  wire  rvclkhdr_7_io_scan_mode; // @[lib.scala 368:23]
-  wire  rvclkhdr_8_io_l1clk; // @[lib.scala 368:23]
-  wire  rvclkhdr_8_io_clk; // @[lib.scala 368:23]
-  wire  rvclkhdr_8_io_en; // @[lib.scala 368:23]
-  wire  rvclkhdr_8_io_scan_mode; // @[lib.scala 368:23]
-  wire  rvclkhdr_9_io_l1clk; // @[lib.scala 368:23]
-  wire  rvclkhdr_9_io_clk; // @[lib.scala 368:23]
-  wire  rvclkhdr_9_io_en; // @[lib.scala 368:23]
-  wire  rvclkhdr_9_io_scan_mode; // @[lib.scala 368:23]
-  wire  rvclkhdr_10_io_l1clk; // @[lib.scala 368:23]
-  wire  rvclkhdr_10_io_clk; // @[lib.scala 368:23]
-  wire  rvclkhdr_10_io_en; // @[lib.scala 368:23]
-  wire  rvclkhdr_10_io_scan_mode; // @[lib.scala 368:23]
-  wire  rvclkhdr_11_io_l1clk; // @[lib.scala 368:23]
-  wire  rvclkhdr_11_io_clk; // @[lib.scala 368:23]
-  wire  rvclkhdr_11_io_en; // @[lib.scala 368:23]
-  wire  rvclkhdr_11_io_scan_mode; // @[lib.scala 368:23]
+  wire  rvclkhdr_io_l1clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_io_clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_io_en; // @[lib.scala 390:23]
+  wire  rvclkhdr_1_io_l1clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_1_io_clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_1_io_en; // @[lib.scala 390:23]
+  wire  rvclkhdr_2_io_l1clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_2_io_clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_2_io_en; // @[lib.scala 390:23]
+  wire  rvclkhdr_3_io_l1clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_3_io_clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_3_io_en; // @[lib.scala 390:23]
+  wire  rvclkhdr_4_io_l1clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_4_io_clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_4_io_en; // @[lib.scala 390:23]
+  wire  rvclkhdr_5_io_l1clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_5_io_clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_5_io_en; // @[lib.scala 390:23]
+  wire  rvclkhdr_6_io_l1clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_6_io_clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_6_io_en; // @[lib.scala 390:23]
+  wire  rvclkhdr_7_io_l1clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_7_io_clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_7_io_en; // @[lib.scala 390:23]
+  wire  rvclkhdr_8_io_l1clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_8_io_clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_8_io_en; // @[lib.scala 390:23]
+  wire  rvclkhdr_9_io_l1clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_9_io_clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_9_io_en; // @[lib.scala 390:23]
+  wire  rvclkhdr_10_io_l1clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_10_io_clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_10_io_en; // @[lib.scala 390:23]
+  wire  rvclkhdr_11_io_l1clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_11_io_clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_11_io_en; // @[lib.scala 390:23]
   wire [3:0] ldst_byteen_hi_m = io_ldst_byteen_ext_m[7:4]; // @[lsu_bus_buffer.scala 76:46]
   wire [3:0] ldst_byteen_lo_m = io_ldst_byteen_ext_m[3:0]; // @[lsu_bus_buffer.scala 77:46]
-  reg [31:0] buf_addr_0; // @[lib.scala 374:16]
+  reg [31:0] buf_addr_0; // @[Reg.scala 27:20]
   wire  _T_2 = io_lsu_addr_m[31:2] == buf_addr_0[31:2]; // @[lsu_bus_buffer.scala 79:74]
-  reg  _T_4344; // @[Reg.scala 27:20]
-  reg  _T_4341; // @[Reg.scala 27:20]
-  reg  _T_4338; // @[Reg.scala 27:20]
-  reg  _T_4335; // @[Reg.scala 27:20]
-  wire [3:0] buf_write = {_T_4344,_T_4341,_T_4338,_T_4335}; // @[Cat.scala 29:58]
+  reg  _T_4355; // @[Reg.scala 27:20]
+  reg  _T_4352; // @[Reg.scala 27:20]
+  reg  _T_4349; // @[Reg.scala 27:20]
+  reg  _T_4346; // @[Reg.scala 27:20]
+  wire [3:0] buf_write = {_T_4355,_T_4352,_T_4349,_T_4346}; // @[Cat.scala 29:58]
   wire  _T_4 = _T_2 & buf_write[0]; // @[lsu_bus_buffer.scala 79:98]
   reg [2:0] buf_state_0; // @[Reg.scala 27:20]
   wire  _T_5 = buf_state_0 != 3'h0; // @[lsu_bus_buffer.scala 79:129]
   wire  _T_6 = _T_4 & _T_5; // @[lsu_bus_buffer.scala 79:113]
   wire  ld_addr_hitvec_lo_0 = _T_6 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 79:141]
-  reg [31:0] buf_addr_1; // @[lib.scala 374:16]
+  reg [31:0] buf_addr_1; // @[Reg.scala 27:20]
   wire  _T_9 = io_lsu_addr_m[31:2] == buf_addr_1[31:2]; // @[lsu_bus_buffer.scala 79:74]
   wire  _T_11 = _T_9 & buf_write[1]; // @[lsu_bus_buffer.scala 79:98]
   reg [2:0] buf_state_1; // @[Reg.scala 27:20]
   wire  _T_12 = buf_state_1 != 3'h0; // @[lsu_bus_buffer.scala 79:129]
   wire  _T_13 = _T_11 & _T_12; // @[lsu_bus_buffer.scala 79:113]
   wire  ld_addr_hitvec_lo_1 = _T_13 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 79:141]
-  reg [31:0] buf_addr_2; // @[lib.scala 374:16]
+  reg [31:0] buf_addr_2; // @[Reg.scala 27:20]
   wire  _T_16 = io_lsu_addr_m[31:2] == buf_addr_2[31:2]; // @[lsu_bus_buffer.scala 79:74]
   wire  _T_18 = _T_16 & buf_write[2]; // @[lsu_bus_buffer.scala 79:98]
   reg [2:0] buf_state_2; // @[Reg.scala 27:20]
   wire  _T_19 = buf_state_2 != 3'h0; // @[lsu_bus_buffer.scala 79:129]
   wire  _T_20 = _T_18 & _T_19; // @[lsu_bus_buffer.scala 79:113]
   wire  ld_addr_hitvec_lo_2 = _T_20 & io_lsu_busreq_m; // @[lsu_bus_buffer.scala 79:141]
-  reg [31:0] buf_addr_3; // @[lib.scala 374:16]
+  reg [31:0] buf_addr_3; // @[Reg.scala 27:20]
   wire  _T_23 = io_lsu_addr_m[31:2] == buf_addr_3[31:2]; // @[lsu_bus_buffer.scala 79:74]
   wire  _T_25 = _T_23 & buf_write[3]; // @[lsu_bus_buffer.scala 79:98]
   reg [2:0] buf_state_3; // @[Reg.scala 27:20]
@@ -5552,112 +5492,58 @@ module lsu_bus_buffer(
   wire  _T_87 = ld_addr_hitvec_lo_0 & buf_byteen_0[0]; // @[lsu_bus_buffer.scala 144:95]
   wire  _T_89 = _T_87 & ldst_byteen_lo_m[0]; // @[lsu_bus_buffer.scala 144:114]
   wire [3:0] ld_byte_hitvec_lo_0 = {_T_101,_T_97,_T_93,_T_89}; // @[Cat.scala 29:58]
-  reg [3:0] buf_ageQ_3; // @[lsu_bus_buffer.scala 508:60]
-  wire  _T_2583 = buf_state_3 == 3'h2; // @[lsu_bus_buffer.scala 414:93]
-  wire  _T_4094 = 3'h0 == buf_state_3; // @[Conditional.scala 37:30]
-  wire  _T_4117 = 3'h1 == buf_state_3; // @[Conditional.scala 37:30]
-  wire  _T_4121 = 3'h2 == buf_state_3; // @[Conditional.scala 37:30]
-  reg [1:0] _T_1780; // @[Reg.scala 27:20]
-  wire [2:0] obuf_tag0 = {{1'd0}, _T_1780}; // @[lsu_bus_buffer.scala 354:13]
-  wire  _T_4128 = obuf_tag0 == 3'h3; // @[lsu_bus_buffer.scala 459:48]
-  reg  obuf_merge; // @[Reg.scala 27:20]
-  reg [1:0] obuf_tag1; // @[Reg.scala 27:20]
-  wire [2:0] _GEN_362 = {{1'd0}, obuf_tag1}; // @[lsu_bus_buffer.scala 459:104]
-  wire  _T_4129 = _GEN_362 == 3'h3; // @[lsu_bus_buffer.scala 459:104]
-  wire  _T_4130 = obuf_merge & _T_4129; // @[lsu_bus_buffer.scala 459:91]
-  wire  _T_4131 = _T_4128 | _T_4130; // @[lsu_bus_buffer.scala 459:77]
+  reg [3:0] buf_ageQ_3; // @[lsu_bus_buffer.scala 511:60]
+  wire  _T_2590 = buf_state_3 == 3'h2; // @[lsu_bus_buffer.scala 415:93]
+  wire  _T_4104 = 3'h0 == buf_state_3; // @[Conditional.scala 37:30]
+  wire  _T_4127 = 3'h1 == buf_state_3; // @[Conditional.scala 37:30]
+  wire  _T_4131 = 3'h2 == buf_state_3; // @[Conditional.scala 37:30]
   reg  obuf_valid; // @[lsu_bus_buffer.scala 348:54]
-  wire  _T_4132 = _T_4131 & obuf_valid; // @[lsu_bus_buffer.scala 459:135]
-  reg  obuf_wr_enQ; // @[lsu_bus_buffer.scala 347:55]
-  wire  _T_4133 = _T_4132 & obuf_wr_enQ; // @[lsu_bus_buffer.scala 459:148]
-  wire  _T_4155 = 3'h3 == buf_state_3; // @[Conditional.scala 37:30]
-  wire  _T_4239 = 3'h4 == buf_state_3; // @[Conditional.scala 37:30]
-  wire  _T_4257 = 3'h5 == buf_state_3; // @[Conditional.scala 37:30]
-  wire  _T_4265 = 3'h6 == buf_state_3; // @[Conditional.scala 37:30]
-  wire  _GEN_284 = _T_4121 & _T_4133; // @[Conditional.scala 39:67]
-  wire  _GEN_297 = _T_4117 ? 1'h0 : _GEN_284; // @[Conditional.scala 39:67]
-  wire  buf_cmd_state_bus_en_3 = _T_4094 ? 1'h0 : _GEN_297; // @[Conditional.scala 40:58]
-  wire  _T_2584 = _T_2583 & buf_cmd_state_bus_en_3; // @[lsu_bus_buffer.scala 414:103]
-  wire  _T_2585 = ~_T_2584; // @[lsu_bus_buffer.scala 414:78]
-  wire  _T_2586 = buf_ageQ_3[3] & _T_2585; // @[lsu_bus_buffer.scala 414:76]
-  wire  _T_2587 = ~io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 414:140]
-  wire  _T_2588 = _T_2586 & _T_2587; // @[lsu_bus_buffer.scala 414:138]
-  wire  _T_2576 = buf_state_2 == 3'h2; // @[lsu_bus_buffer.scala 414:93]
-  wire  _T_3904 = 3'h0 == buf_state_2; // @[Conditional.scala 37:30]
-  wire  _T_3927 = 3'h1 == buf_state_2; // @[Conditional.scala 37:30]
-  wire  _T_3931 = 3'h2 == buf_state_2; // @[Conditional.scala 37:30]
-  wire  _T_3938 = obuf_tag0 == 3'h2; // @[lsu_bus_buffer.scala 459:48]
-  wire  _T_3939 = _GEN_362 == 3'h2; // @[lsu_bus_buffer.scala 459:104]
-  wire  _T_3940 = obuf_merge & _T_3939; // @[lsu_bus_buffer.scala 459:91]
-  wire  _T_3941 = _T_3938 | _T_3940; // @[lsu_bus_buffer.scala 459:77]
-  wire  _T_3942 = _T_3941 & obuf_valid; // @[lsu_bus_buffer.scala 459:135]
-  wire  _T_3943 = _T_3942 & obuf_wr_enQ; // @[lsu_bus_buffer.scala 459:148]
-  wire  _T_3965 = 3'h3 == buf_state_2; // @[Conditional.scala 37:30]
-  wire  _T_4049 = 3'h4 == buf_state_2; // @[Conditional.scala 37:30]
-  wire  _T_4067 = 3'h5 == buf_state_2; // @[Conditional.scala 37:30]
-  wire  _T_4075 = 3'h6 == buf_state_2; // @[Conditional.scala 37:30]
-  wire  _GEN_207 = _T_3931 & _T_3943; // @[Conditional.scala 39:67]
-  wire  _GEN_220 = _T_3927 ? 1'h0 : _GEN_207; // @[Conditional.scala 39:67]
-  wire  buf_cmd_state_bus_en_2 = _T_3904 ? 1'h0 : _GEN_220; // @[Conditional.scala 40:58]
-  wire  _T_2577 = _T_2576 & buf_cmd_state_bus_en_2; // @[lsu_bus_buffer.scala 414:103]
-  wire  _T_2578 = ~_T_2577; // @[lsu_bus_buffer.scala 414:78]
-  wire  _T_2579 = buf_ageQ_3[2] & _T_2578; // @[lsu_bus_buffer.scala 414:76]
-  wire  _T_2581 = _T_2579 & _T_2587; // @[lsu_bus_buffer.scala 414:138]
-  wire  _T_2569 = buf_state_1 == 3'h2; // @[lsu_bus_buffer.scala 414:93]
-  wire  _T_3714 = 3'h0 == buf_state_1; // @[Conditional.scala 37:30]
-  wire  _T_3737 = 3'h1 == buf_state_1; // @[Conditional.scala 37:30]
-  wire  _T_3741 = 3'h2 == buf_state_1; // @[Conditional.scala 37:30]
-  wire  _T_3748 = obuf_tag0 == 3'h1; // @[lsu_bus_buffer.scala 459:48]
-  wire  _T_3749 = _GEN_362 == 3'h1; // @[lsu_bus_buffer.scala 459:104]
-  wire  _T_3750 = obuf_merge & _T_3749; // @[lsu_bus_buffer.scala 459:91]
-  wire  _T_3751 = _T_3748 | _T_3750; // @[lsu_bus_buffer.scala 459:77]
-  wire  _T_3752 = _T_3751 & obuf_valid; // @[lsu_bus_buffer.scala 459:135]
-  wire  _T_3753 = _T_3752 & obuf_wr_enQ; // @[lsu_bus_buffer.scala 459:148]
-  wire  _T_3775 = 3'h3 == buf_state_1; // @[Conditional.scala 37:30]
-  wire  _T_3859 = 3'h4 == buf_state_1; // @[Conditional.scala 37:30]
-  wire  _T_3877 = 3'h5 == buf_state_1; // @[Conditional.scala 37:30]
-  wire  _T_3885 = 3'h6 == buf_state_1; // @[Conditional.scala 37:30]
-  wire  _GEN_130 = _T_3741 & _T_3753; // @[Conditional.scala 39:67]
-  wire  _GEN_143 = _T_3737 ? 1'h0 : _GEN_130; // @[Conditional.scala 39:67]
-  wire  buf_cmd_state_bus_en_1 = _T_3714 ? 1'h0 : _GEN_143; // @[Conditional.scala 40:58]
-  wire  _T_2570 = _T_2569 & buf_cmd_state_bus_en_1; // @[lsu_bus_buffer.scala 414:103]
-  wire  _T_2571 = ~_T_2570; // @[lsu_bus_buffer.scala 414:78]
-  wire  _T_2572 = buf_ageQ_3[1] & _T_2571; // @[lsu_bus_buffer.scala 414:76]
-  wire  _T_2574 = _T_2572 & _T_2587; // @[lsu_bus_buffer.scala 414:138]
-  wire  _T_2562 = buf_state_0 == 3'h2; // @[lsu_bus_buffer.scala 414:93]
-  wire  _T_3524 = 3'h0 == buf_state_0; // @[Conditional.scala 37:30]
-  wire  _T_3547 = 3'h1 == buf_state_0; // @[Conditional.scala 37:30]
-  wire  _T_3551 = 3'h2 == buf_state_0; // @[Conditional.scala 37:30]
-  wire  _T_3558 = obuf_tag0 == 3'h0; // @[lsu_bus_buffer.scala 459:48]
-  wire  _T_3559 = _GEN_362 == 3'h0; // @[lsu_bus_buffer.scala 459:104]
-  wire  _T_3560 = obuf_merge & _T_3559; // @[lsu_bus_buffer.scala 459:91]
-  wire  _T_3561 = _T_3558 | _T_3560; // @[lsu_bus_buffer.scala 459:77]
-  wire  _T_3562 = _T_3561 & obuf_valid; // @[lsu_bus_buffer.scala 459:135]
-  wire  _T_3563 = _T_3562 & obuf_wr_enQ; // @[lsu_bus_buffer.scala 459:148]
-  wire  _T_3585 = 3'h3 == buf_state_0; // @[Conditional.scala 37:30]
-  wire  _T_3669 = 3'h4 == buf_state_0; // @[Conditional.scala 37:30]
-  wire  _T_3687 = 3'h5 == buf_state_0; // @[Conditional.scala 37:30]
-  wire  _T_3695 = 3'h6 == buf_state_0; // @[Conditional.scala 37:30]
-  wire  _GEN_53 = _T_3551 & _T_3563; // @[Conditional.scala 39:67]
-  wire  _GEN_66 = _T_3547 ? 1'h0 : _GEN_53; // @[Conditional.scala 39:67]
-  wire  buf_cmd_state_bus_en_0 = _T_3524 ? 1'h0 : _GEN_66; // @[Conditional.scala 40:58]
-  wire  _T_2563 = _T_2562 & buf_cmd_state_bus_en_0; // @[lsu_bus_buffer.scala 414:103]
-  wire  _T_2564 = ~_T_2563; // @[lsu_bus_buffer.scala 414:78]
-  wire  _T_2565 = buf_ageQ_3[0] & _T_2564; // @[lsu_bus_buffer.scala 414:76]
-  wire  _T_2567 = _T_2565 & _T_2587; // @[lsu_bus_buffer.scala 414:138]
-  wire [3:0] buf_age_3 = {_T_2588,_T_2581,_T_2574,_T_2567}; // @[Cat.scala 29:58]
-  wire  _T_2687 = ~buf_age_3[2]; // @[lsu_bus_buffer.scala 415:89]
-  wire  _T_2689 = _T_2687 & _T_19; // @[lsu_bus_buffer.scala 415:104]
-  wire  _T_2681 = ~buf_age_3[1]; // @[lsu_bus_buffer.scala 415:89]
-  wire  _T_2683 = _T_2681 & _T_12; // @[lsu_bus_buffer.scala 415:104]
-  wire  _T_2675 = ~buf_age_3[0]; // @[lsu_bus_buffer.scala 415:89]
-  wire  _T_2677 = _T_2675 & _T_5; // @[lsu_bus_buffer.scala 415:104]
-  wire [3:0] buf_age_younger_3 = {1'h0,_T_2689,_T_2683,_T_2677}; // @[Cat.scala 29:58]
+  wire  _T_4165 = 3'h3 == buf_state_3; // @[Conditional.scala 37:30]
+  wire  _T_4250 = 3'h4 == buf_state_3; // @[Conditional.scala 37:30]
+  wire  _T_4268 = 3'h5 == buf_state_3; // @[Conditional.scala 37:30]
+  wire  _T_4276 = 3'h6 == buf_state_3; // @[Conditional.scala 37:30]
+  wire  _T_2594 = ~io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 415:132]
+  wire  _T_2595 = buf_ageQ_3[3] & _T_2594; // @[lsu_bus_buffer.scala 415:130]
+  wire  _T_2583 = buf_state_2 == 3'h2; // @[lsu_bus_buffer.scala 415:93]
+  wire  _T_3913 = 3'h0 == buf_state_2; // @[Conditional.scala 37:30]
+  wire  _T_3936 = 3'h1 == buf_state_2; // @[Conditional.scala 37:30]
+  wire  _T_3940 = 3'h2 == buf_state_2; // @[Conditional.scala 37:30]
+  wire  _T_3974 = 3'h3 == buf_state_2; // @[Conditional.scala 37:30]
+  wire  _T_4059 = 3'h4 == buf_state_2; // @[Conditional.scala 37:30]
+  wire  _T_4077 = 3'h5 == buf_state_2; // @[Conditional.scala 37:30]
+  wire  _T_4085 = 3'h6 == buf_state_2; // @[Conditional.scala 37:30]
+  wire  _T_2588 = buf_ageQ_3[2] & _T_2594; // @[lsu_bus_buffer.scala 415:130]
+  wire  _T_2576 = buf_state_1 == 3'h2; // @[lsu_bus_buffer.scala 415:93]
+  wire  _T_3722 = 3'h0 == buf_state_1; // @[Conditional.scala 37:30]
+  wire  _T_3745 = 3'h1 == buf_state_1; // @[Conditional.scala 37:30]
+  wire  _T_3749 = 3'h2 == buf_state_1; // @[Conditional.scala 37:30]
+  wire  _T_3783 = 3'h3 == buf_state_1; // @[Conditional.scala 37:30]
+  wire  _T_3868 = 3'h4 == buf_state_1; // @[Conditional.scala 37:30]
+  wire  _T_3886 = 3'h5 == buf_state_1; // @[Conditional.scala 37:30]
+  wire  _T_3894 = 3'h6 == buf_state_1; // @[Conditional.scala 37:30]
+  wire  _T_2581 = buf_ageQ_3[1] & _T_2594; // @[lsu_bus_buffer.scala 415:130]
+  wire  _T_2569 = buf_state_0 == 3'h2; // @[lsu_bus_buffer.scala 415:93]
+  wire  _T_3531 = 3'h0 == buf_state_0; // @[Conditional.scala 37:30]
+  wire  _T_3554 = 3'h1 == buf_state_0; // @[Conditional.scala 37:30]
+  wire  _T_3558 = 3'h2 == buf_state_0; // @[Conditional.scala 37:30]
+  wire  _T_3592 = 3'h3 == buf_state_0; // @[Conditional.scala 37:30]
+  wire  _T_3677 = 3'h4 == buf_state_0; // @[Conditional.scala 37:30]
+  wire  _T_3695 = 3'h5 == buf_state_0; // @[Conditional.scala 37:30]
+  wire  _T_3703 = 3'h6 == buf_state_0; // @[Conditional.scala 37:30]
+  wire  _T_2574 = buf_ageQ_3[0] & _T_2594; // @[lsu_bus_buffer.scala 415:130]
+  wire [3:0] buf_age_3 = {_T_2595,_T_2588,_T_2581,_T_2574}; // @[Cat.scala 29:58]
+  wire  _T_2694 = ~buf_age_3[2]; // @[lsu_bus_buffer.scala 416:89]
+  wire  _T_2696 = _T_2694 & _T_19; // @[lsu_bus_buffer.scala 416:104]
+  wire  _T_2688 = ~buf_age_3[1]; // @[lsu_bus_buffer.scala 416:89]
+  wire  _T_2690 = _T_2688 & _T_12; // @[lsu_bus_buffer.scala 416:104]
+  wire  _T_2682 = ~buf_age_3[0]; // @[lsu_bus_buffer.scala 416:89]
+  wire  _T_2684 = _T_2682 & _T_5; // @[lsu_bus_buffer.scala 416:104]
+  wire [3:0] buf_age_younger_3 = {1'h0,_T_2696,_T_2690,_T_2684}; // @[Cat.scala 29:58]
   wire [3:0] _T_255 = ld_byte_hitvec_lo_0 & buf_age_younger_3; // @[lsu_bus_buffer.scala 149:122]
   wire  _T_256 = |_T_255; // @[lsu_bus_buffer.scala 149:144]
   wire  _T_257 = ~_T_256; // @[lsu_bus_buffer.scala 149:99]
   wire  _T_258 = ld_byte_hitvec_lo_0[3] & _T_257; // @[lsu_bus_buffer.scala 149:97]
-  reg [31:0] ibuf_addr; // @[lib.scala 374:16]
+  reg [31:0] ibuf_addr; // @[Reg.scala 27:20]
   wire  _T_512 = io_lsu_addr_m[31:2] == ibuf_addr[31:2]; // @[lsu_bus_buffer.scala 155:51]
   reg  ibuf_write; // @[Reg.scala 27:20]
   wire  _T_513 = _T_512 & ibuf_write; // @[lsu_bus_buffer.scala 155:73]
@@ -5670,67 +5556,55 @@ module lsu_bus_buffer(
   wire [3:0] ld_byte_ibuf_hit_lo = _T_522 & ldst_byteen_lo_m; // @[lsu_bus_buffer.scala 160:69]
   wire  _T_260 = ~ld_byte_ibuf_hit_lo[0]; // @[lsu_bus_buffer.scala 149:150]
   wire  _T_261 = _T_258 & _T_260; // @[lsu_bus_buffer.scala 149:148]
-  reg [3:0] buf_ageQ_2; // @[lsu_bus_buffer.scala 508:60]
-  wire  _T_2555 = buf_ageQ_2[3] & _T_2585; // @[lsu_bus_buffer.scala 414:76]
-  wire  _T_2557 = _T_2555 & _T_2587; // @[lsu_bus_buffer.scala 414:138]
-  wire  _T_2548 = buf_ageQ_2[2] & _T_2578; // @[lsu_bus_buffer.scala 414:76]
-  wire  _T_2550 = _T_2548 & _T_2587; // @[lsu_bus_buffer.scala 414:138]
-  wire  _T_2541 = buf_ageQ_2[1] & _T_2571; // @[lsu_bus_buffer.scala 414:76]
-  wire  _T_2543 = _T_2541 & _T_2587; // @[lsu_bus_buffer.scala 414:138]
-  wire  _T_2534 = buf_ageQ_2[0] & _T_2564; // @[lsu_bus_buffer.scala 414:76]
-  wire  _T_2536 = _T_2534 & _T_2587; // @[lsu_bus_buffer.scala 414:138]
-  wire [3:0] buf_age_2 = {_T_2557,_T_2550,_T_2543,_T_2536}; // @[Cat.scala 29:58]
-  wire  _T_2666 = ~buf_age_2[3]; // @[lsu_bus_buffer.scala 415:89]
-  wire  _T_2668 = _T_2666 & _T_26; // @[lsu_bus_buffer.scala 415:104]
-  wire  _T_2654 = ~buf_age_2[1]; // @[lsu_bus_buffer.scala 415:89]
-  wire  _T_2656 = _T_2654 & _T_12; // @[lsu_bus_buffer.scala 415:104]
-  wire  _T_2648 = ~buf_age_2[0]; // @[lsu_bus_buffer.scala 415:89]
-  wire  _T_2650 = _T_2648 & _T_5; // @[lsu_bus_buffer.scala 415:104]
-  wire [3:0] buf_age_younger_2 = {_T_2668,1'h0,_T_2656,_T_2650}; // @[Cat.scala 29:58]
+  reg [3:0] buf_ageQ_2; // @[lsu_bus_buffer.scala 511:60]
+  wire  _T_2564 = buf_ageQ_2[3] & _T_2594; // @[lsu_bus_buffer.scala 415:130]
+  wire  _T_2557 = buf_ageQ_2[2] & _T_2594; // @[lsu_bus_buffer.scala 415:130]
+  wire  _T_2550 = buf_ageQ_2[1] & _T_2594; // @[lsu_bus_buffer.scala 415:130]
+  wire  _T_2543 = buf_ageQ_2[0] & _T_2594; // @[lsu_bus_buffer.scala 415:130]
+  wire [3:0] buf_age_2 = {_T_2564,_T_2557,_T_2550,_T_2543}; // @[Cat.scala 29:58]
+  wire  _T_2673 = ~buf_age_2[3]; // @[lsu_bus_buffer.scala 416:89]
+  wire  _T_2675 = _T_2673 & _T_26; // @[lsu_bus_buffer.scala 416:104]
+  wire  _T_2661 = ~buf_age_2[1]; // @[lsu_bus_buffer.scala 416:89]
+  wire  _T_2663 = _T_2661 & _T_12; // @[lsu_bus_buffer.scala 416:104]
+  wire  _T_2655 = ~buf_age_2[0]; // @[lsu_bus_buffer.scala 416:89]
+  wire  _T_2657 = _T_2655 & _T_5; // @[lsu_bus_buffer.scala 416:104]
+  wire [3:0] buf_age_younger_2 = {_T_2675,1'h0,_T_2663,_T_2657}; // @[Cat.scala 29:58]
   wire [3:0] _T_247 = ld_byte_hitvec_lo_0 & buf_age_younger_2; // @[lsu_bus_buffer.scala 149:122]
   wire  _T_248 = |_T_247; // @[lsu_bus_buffer.scala 149:144]
   wire  _T_249 = ~_T_248; // @[lsu_bus_buffer.scala 149:99]
   wire  _T_250 = ld_byte_hitvec_lo_0[2] & _T_249; // @[lsu_bus_buffer.scala 149:97]
   wire  _T_253 = _T_250 & _T_260; // @[lsu_bus_buffer.scala 149:148]
-  reg [3:0] buf_ageQ_1; // @[lsu_bus_buffer.scala 508:60]
-  wire  _T_2524 = buf_ageQ_1[3] & _T_2585; // @[lsu_bus_buffer.scala 414:76]
-  wire  _T_2526 = _T_2524 & _T_2587; // @[lsu_bus_buffer.scala 414:138]
-  wire  _T_2517 = buf_ageQ_1[2] & _T_2578; // @[lsu_bus_buffer.scala 414:76]
-  wire  _T_2519 = _T_2517 & _T_2587; // @[lsu_bus_buffer.scala 414:138]
-  wire  _T_2510 = buf_ageQ_1[1] & _T_2571; // @[lsu_bus_buffer.scala 414:76]
-  wire  _T_2512 = _T_2510 & _T_2587; // @[lsu_bus_buffer.scala 414:138]
-  wire  _T_2503 = buf_ageQ_1[0] & _T_2564; // @[lsu_bus_buffer.scala 414:76]
-  wire  _T_2505 = _T_2503 & _T_2587; // @[lsu_bus_buffer.scala 414:138]
-  wire [3:0] buf_age_1 = {_T_2526,_T_2519,_T_2512,_T_2505}; // @[Cat.scala 29:58]
-  wire  _T_2639 = ~buf_age_1[3]; // @[lsu_bus_buffer.scala 415:89]
-  wire  _T_2641 = _T_2639 & _T_26; // @[lsu_bus_buffer.scala 415:104]
-  wire  _T_2633 = ~buf_age_1[2]; // @[lsu_bus_buffer.scala 415:89]
-  wire  _T_2635 = _T_2633 & _T_19; // @[lsu_bus_buffer.scala 415:104]
-  wire  _T_2621 = ~buf_age_1[0]; // @[lsu_bus_buffer.scala 415:89]
-  wire  _T_2623 = _T_2621 & _T_5; // @[lsu_bus_buffer.scala 415:104]
-  wire [3:0] buf_age_younger_1 = {_T_2641,_T_2635,1'h0,_T_2623}; // @[Cat.scala 29:58]
+  reg [3:0] buf_ageQ_1; // @[lsu_bus_buffer.scala 511:60]
+  wire  _T_2533 = buf_ageQ_1[3] & _T_2594; // @[lsu_bus_buffer.scala 415:130]
+  wire  _T_2526 = buf_ageQ_1[2] & _T_2594; // @[lsu_bus_buffer.scala 415:130]
+  wire  _T_2519 = buf_ageQ_1[1] & _T_2594; // @[lsu_bus_buffer.scala 415:130]
+  wire  _T_2512 = buf_ageQ_1[0] & _T_2594; // @[lsu_bus_buffer.scala 415:130]
+  wire [3:0] buf_age_1 = {_T_2533,_T_2526,_T_2519,_T_2512}; // @[Cat.scala 29:58]
+  wire  _T_2646 = ~buf_age_1[3]; // @[lsu_bus_buffer.scala 416:89]
+  wire  _T_2648 = _T_2646 & _T_26; // @[lsu_bus_buffer.scala 416:104]
+  wire  _T_2640 = ~buf_age_1[2]; // @[lsu_bus_buffer.scala 416:89]
+  wire  _T_2642 = _T_2640 & _T_19; // @[lsu_bus_buffer.scala 416:104]
+  wire  _T_2628 = ~buf_age_1[0]; // @[lsu_bus_buffer.scala 416:89]
+  wire  _T_2630 = _T_2628 & _T_5; // @[lsu_bus_buffer.scala 416:104]
+  wire [3:0] buf_age_younger_1 = {_T_2648,_T_2642,1'h0,_T_2630}; // @[Cat.scala 29:58]
   wire [3:0] _T_239 = ld_byte_hitvec_lo_0 & buf_age_younger_1; // @[lsu_bus_buffer.scala 149:122]
   wire  _T_240 = |_T_239; // @[lsu_bus_buffer.scala 149:144]
   wire  _T_241 = ~_T_240; // @[lsu_bus_buffer.scala 149:99]
   wire  _T_242 = ld_byte_hitvec_lo_0[1] & _T_241; // @[lsu_bus_buffer.scala 149:97]
   wire  _T_245 = _T_242 & _T_260; // @[lsu_bus_buffer.scala 149:148]
-  reg [3:0] buf_ageQ_0; // @[lsu_bus_buffer.scala 508:60]
-  wire  _T_2493 = buf_ageQ_0[3] & _T_2585; // @[lsu_bus_buffer.scala 414:76]
-  wire  _T_2495 = _T_2493 & _T_2587; // @[lsu_bus_buffer.scala 414:138]
-  wire  _T_2486 = buf_ageQ_0[2] & _T_2578; // @[lsu_bus_buffer.scala 414:76]
-  wire  _T_2488 = _T_2486 & _T_2587; // @[lsu_bus_buffer.scala 414:138]
-  wire  _T_2479 = buf_ageQ_0[1] & _T_2571; // @[lsu_bus_buffer.scala 414:76]
-  wire  _T_2481 = _T_2479 & _T_2587; // @[lsu_bus_buffer.scala 414:138]
-  wire  _T_2472 = buf_ageQ_0[0] & _T_2564; // @[lsu_bus_buffer.scala 414:76]
-  wire  _T_2474 = _T_2472 & _T_2587; // @[lsu_bus_buffer.scala 414:138]
-  wire [3:0] buf_age_0 = {_T_2495,_T_2488,_T_2481,_T_2474}; // @[Cat.scala 29:58]
-  wire  _T_2612 = ~buf_age_0[3]; // @[lsu_bus_buffer.scala 415:89]
-  wire  _T_2614 = _T_2612 & _T_26; // @[lsu_bus_buffer.scala 415:104]
-  wire  _T_2606 = ~buf_age_0[2]; // @[lsu_bus_buffer.scala 415:89]
-  wire  _T_2608 = _T_2606 & _T_19; // @[lsu_bus_buffer.scala 415:104]
-  wire  _T_2600 = ~buf_age_0[1]; // @[lsu_bus_buffer.scala 415:89]
-  wire  _T_2602 = _T_2600 & _T_12; // @[lsu_bus_buffer.scala 415:104]
-  wire [3:0] buf_age_younger_0 = {_T_2614,_T_2608,_T_2602,1'h0}; // @[Cat.scala 29:58]
+  reg [3:0] buf_ageQ_0; // @[lsu_bus_buffer.scala 511:60]
+  wire  _T_2502 = buf_ageQ_0[3] & _T_2594; // @[lsu_bus_buffer.scala 415:130]
+  wire  _T_2495 = buf_ageQ_0[2] & _T_2594; // @[lsu_bus_buffer.scala 415:130]
+  wire  _T_2488 = buf_ageQ_0[1] & _T_2594; // @[lsu_bus_buffer.scala 415:130]
+  wire  _T_2481 = buf_ageQ_0[0] & _T_2594; // @[lsu_bus_buffer.scala 415:130]
+  wire [3:0] buf_age_0 = {_T_2502,_T_2495,_T_2488,_T_2481}; // @[Cat.scala 29:58]
+  wire  _T_2619 = ~buf_age_0[3]; // @[lsu_bus_buffer.scala 416:89]
+  wire  _T_2621 = _T_2619 & _T_26; // @[lsu_bus_buffer.scala 416:104]
+  wire  _T_2613 = ~buf_age_0[2]; // @[lsu_bus_buffer.scala 416:89]
+  wire  _T_2615 = _T_2613 & _T_19; // @[lsu_bus_buffer.scala 416:104]
+  wire  _T_2607 = ~buf_age_0[1]; // @[lsu_bus_buffer.scala 416:89]
+  wire  _T_2609 = _T_2607 & _T_12; // @[lsu_bus_buffer.scala 416:104]
+  wire [3:0] buf_age_younger_0 = {_T_2621,_T_2615,_T_2609,1'h0}; // @[Cat.scala 29:58]
   wire [3:0] _T_231 = ld_byte_hitvec_lo_0 & buf_age_younger_0; // @[lsu_bus_buffer.scala 149:122]
   wire  _T_232 = |_T_231; // @[lsu_bus_buffer.scala 149:144]
   wire  _T_233 = ~_T_232; // @[lsu_bus_buffer.scala 149:99]
@@ -5990,16 +5864,16 @@ module lsu_bus_buffer(
   wire [7:0] _T_553 = ld_byte_ibuf_hit_hi[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
   wire [31:0] ld_fwddata_buf_hi_initial = {_T_553,_T_550,_T_547,_T_544}; // @[Cat.scala 29:58]
   wire [7:0] _T_558 = ld_byte_hitvecfn_lo_3[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
-  reg [31:0] buf_data_0; // @[lib.scala 374:16]
+  reg [31:0] buf_data_0; // @[Reg.scala 27:20]
   wire [7:0] _T_560 = _T_558 & buf_data_0[31:24]; // @[lsu_bus_buffer.scala 168:91]
   wire [7:0] _T_563 = ld_byte_hitvecfn_lo_3[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
-  reg [31:0] buf_data_1; // @[lib.scala 374:16]
+  reg [31:0] buf_data_1; // @[Reg.scala 27:20]
   wire [7:0] _T_565 = _T_563 & buf_data_1[31:24]; // @[lsu_bus_buffer.scala 168:91]
   wire [7:0] _T_568 = ld_byte_hitvecfn_lo_3[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
-  reg [31:0] buf_data_2; // @[lib.scala 374:16]
+  reg [31:0] buf_data_2; // @[Reg.scala 27:20]
   wire [7:0] _T_570 = _T_568 & buf_data_2[31:24]; // @[lsu_bus_buffer.scala 168:91]
   wire [7:0] _T_573 = ld_byte_hitvecfn_lo_3[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
-  reg [31:0] buf_data_3; // @[lib.scala 374:16]
+  reg [31:0] buf_data_3; // @[Reg.scala 27:20]
   wire [7:0] _T_575 = _T_573 & buf_data_3[31:24]; // @[lsu_bus_buffer.scala 168:91]
   wire [7:0] _T_576 = _T_560 | _T_565; // @[lsu_bus_buffer.scala 168:123]
   wire [7:0] _T_577 = _T_576 | _T_570; // @[lsu_bus_buffer.scala 168:123]
@@ -6038,7 +5912,7 @@ module lsu_bus_buffer(
   wire [7:0] _T_646 = _T_645 | _T_639; // @[lsu_bus_buffer.scala 171:97]
   wire [7:0] _T_647 = _T_646 | _T_644; // @[lsu_bus_buffer.scala 171:97]
   wire [31:0] _T_650 = {_T_578,_T_601,_T_624,_T_647}; // @[Cat.scala 29:58]
-  reg [31:0] ibuf_data; // @[lib.scala 374:16]
+  reg [31:0] ibuf_data; // @[Reg.scala 27:20]
   wire [31:0] _T_651 = ld_fwddata_buf_lo_initial & ibuf_data; // @[lsu_bus_buffer.scala 172:32]
   wire [7:0] _T_655 = ld_byte_hitvecfn_hi_3[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
   wire [7:0] _T_657 = _T_655 & buf_data_0[31:24]; // @[lsu_bus_buffer.scala 174:91]
@@ -6177,8 +6051,8 @@ module lsu_bus_buffer(
   wire  ibuf_drain_vld = ibuf_valid & _T_874; // @[lsu_bus_buffer.scala 219:32]
   wire  _T_856 = ibuf_drain_vld & _T_855; // @[lsu_bus_buffer.scala 213:34]
   wire  ibuf_rst = _T_856 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 213:49]
-  reg [1:0] WrPtr1_r; // @[lsu_bus_buffer.scala 623:49]
-  reg [1:0] WrPtr0_r; // @[lsu_bus_buffer.scala 622:49]
+  reg [1:0] WrPtr1_r; // @[lsu_bus_buffer.scala 625:49]
+  reg [1:0] WrPtr0_r; // @[lsu_bus_buffer.scala 624:49]
   reg [1:0] ibuf_tag; // @[Reg.scala 27:20]
   wire [1:0] ibuf_sz_in = {io_lsu_pkt_r_bits_word,io_lsu_pkt_r_bits_half}; // @[Cat.scala 29:58]
   wire [3:0] _T_881 = ibuf_byteen | ldst_byteen_lo_r; // @[lsu_bus_buffer.scala 229:77]
@@ -6194,9 +6068,9 @@ module lsu_bus_buffer(
   wire [7:0] _T_916 = ldst_byteen_lo_r[3] ? store_data_lo_r[31:24] : ibuf_data[31:24]; // @[lsu_bus_buffer.scala 234:8]
   wire [7:0] _T_919 = io_ldst_dual_r ? store_data_hi_r[31:24] : store_data_lo_r[31:24]; // @[lsu_bus_buffer.scala 235:8]
   wire [7:0] _T_920 = _T_866 ? _T_916 : _T_919; // @[lsu_bus_buffer.scala 233:46]
-  wire [23:0] _T_922 = {_T_920,_T_911,_T_902}; // @[Cat.scala 29:58]
-  wire  _T_923 = ibuf_timer < 3'h7; // @[lsu_bus_buffer.scala 236:59]
-  wire [2:0] _T_926 = ibuf_timer + 3'h1; // @[lsu_bus_buffer.scala 236:93]
+  wire [31:0] ibuf_data_in = {_T_920,_T_911,_T_902,_T_893}; // @[Cat.scala 29:58]
+  wire  _T_923 = ibuf_timer < 3'h7; // @[lsu_bus_buffer.scala 236:60]
+  wire [2:0] _T_926 = ibuf_timer + 3'h1; // @[lsu_bus_buffer.scala 236:95]
   wire  _T_941 = ~ibuf_merge_in; // @[lsu_bus_buffer.scala 240:65]
   wire  _T_942 = ibuf_merge_en & _T_941; // @[lsu_bus_buffer.scala 240:63]
   wire  _T_945 = ibuf_byteen[0] | ldst_byteen_lo_r[0]; // @[lsu_bus_buffer.scala 240:96]
@@ -6221,68 +6095,53 @@ module lsu_bus_buffer(
   reg  ibuf_nomerge; // @[Reg.scala 27:20]
   reg  ibuf_unsign; // @[Reg.scala 27:20]
   reg [1:0] ibuf_sz; // @[Reg.scala 27:20]
-  wire  _T_4430 = buf_write[3] & _T_2583; // @[lsu_bus_buffer.scala 529:64]
-  wire  _T_4431 = ~buf_cmd_state_bus_en_3; // @[lsu_bus_buffer.scala 529:91]
-  wire  _T_4432 = _T_4430 & _T_4431; // @[lsu_bus_buffer.scala 529:89]
-  wire  _T_4425 = buf_write[2] & _T_2576; // @[lsu_bus_buffer.scala 529:64]
-  wire  _T_4426 = ~buf_cmd_state_bus_en_2; // @[lsu_bus_buffer.scala 529:91]
-  wire  _T_4427 = _T_4425 & _T_4426; // @[lsu_bus_buffer.scala 529:89]
-  wire [1:0] _T_4433 = _T_4432 + _T_4427; // @[lsu_bus_buffer.scala 529:142]
-  wire  _T_4420 = buf_write[1] & _T_2569; // @[lsu_bus_buffer.scala 529:64]
-  wire  _T_4421 = ~buf_cmd_state_bus_en_1; // @[lsu_bus_buffer.scala 529:91]
-  wire  _T_4422 = _T_4420 & _T_4421; // @[lsu_bus_buffer.scala 529:89]
-  wire [1:0] _GEN_366 = {{1'd0}, _T_4422}; // @[lsu_bus_buffer.scala 529:142]
-  wire [2:0] _T_4434 = _T_4433 + _GEN_366; // @[lsu_bus_buffer.scala 529:142]
-  wire  _T_4415 = buf_write[0] & _T_2562; // @[lsu_bus_buffer.scala 529:64]
-  wire  _T_4416 = ~buf_cmd_state_bus_en_0; // @[lsu_bus_buffer.scala 529:91]
-  wire  _T_4417 = _T_4415 & _T_4416; // @[lsu_bus_buffer.scala 529:89]
-  wire [2:0] _GEN_367 = {{2'd0}, _T_4417}; // @[lsu_bus_buffer.scala 529:142]
-  wire [3:0] buf_numvld_wrcmd_any = _T_4434 + _GEN_367; // @[lsu_bus_buffer.scala 529:142]
+  wire  _T_4441 = buf_write[3] & _T_2590; // @[lsu_bus_buffer.scala 531:64]
+  wire  _T_4436 = buf_write[2] & _T_2583; // @[lsu_bus_buffer.scala 531:64]
+  wire [1:0] _T_4444 = _T_4441 + _T_4436; // @[lsu_bus_buffer.scala 531:142]
+  wire  _T_4431 = buf_write[1] & _T_2576; // @[lsu_bus_buffer.scala 531:64]
+  wire [1:0] _GEN_376 = {{1'd0}, _T_4431}; // @[lsu_bus_buffer.scala 531:142]
+  wire [2:0] _T_4445 = _T_4444 + _GEN_376; // @[lsu_bus_buffer.scala 531:142]
+  wire  _T_4426 = buf_write[0] & _T_2569; // @[lsu_bus_buffer.scala 531:64]
+  wire [2:0] _GEN_377 = {{2'd0}, _T_4426}; // @[lsu_bus_buffer.scala 531:142]
+  wire [3:0] buf_numvld_wrcmd_any = _T_4445 + _GEN_377; // @[lsu_bus_buffer.scala 531:142]
   wire  _T_1016 = buf_numvld_wrcmd_any == 4'h1; // @[lsu_bus_buffer.scala 266:43]
-  wire  _T_4447 = _T_2583 & _T_4431; // @[lsu_bus_buffer.scala 530:73]
-  wire  _T_4444 = _T_2576 & _T_4426; // @[lsu_bus_buffer.scala 530:73]
-  wire [1:0] _T_4448 = _T_4447 + _T_4444; // @[lsu_bus_buffer.scala 530:126]
-  wire  _T_4441 = _T_2569 & _T_4421; // @[lsu_bus_buffer.scala 530:73]
-  wire [1:0] _GEN_368 = {{1'd0}, _T_4441}; // @[lsu_bus_buffer.scala 530:126]
-  wire [2:0] _T_4449 = _T_4448 + _GEN_368; // @[lsu_bus_buffer.scala 530:126]
-  wire  _T_4438 = _T_2562 & _T_4416; // @[lsu_bus_buffer.scala 530:73]
-  wire [2:0] _GEN_369 = {{2'd0}, _T_4438}; // @[lsu_bus_buffer.scala 530:126]
-  wire [3:0] buf_numvld_cmd_any = _T_4449 + _GEN_369; // @[lsu_bus_buffer.scala 530:126]
+  wire [1:0] _T_4459 = _T_2590 + _T_2583; // @[lsu_bus_buffer.scala 532:126]
+  wire [1:0] _GEN_378 = {{1'd0}, _T_2576}; // @[lsu_bus_buffer.scala 532:126]
+  wire [2:0] _T_4460 = _T_4459 + _GEN_378; // @[lsu_bus_buffer.scala 532:126]
+  wire [2:0] _GEN_379 = {{2'd0}, _T_2569}; // @[lsu_bus_buffer.scala 532:126]
+  wire [3:0] buf_numvld_cmd_any = _T_4460 + _GEN_379; // @[lsu_bus_buffer.scala 532:126]
   wire  _T_1017 = buf_numvld_cmd_any == 4'h1; // @[lsu_bus_buffer.scala 266:72]
   wire  _T_1018 = _T_1016 & _T_1017; // @[lsu_bus_buffer.scala 266:51]
-  reg [2:0] obuf_wr_timer; // @[lsu_bus_buffer.scala 363:54]
+  reg  _T_1791; // @[Reg.scala 27:20]
+  wire [2:0] obuf_wr_timer = {{2'd0}, _T_1791}; // @[lsu_bus_buffer.scala 364:17]
   wire  _T_1019 = obuf_wr_timer != 3'h7; // @[lsu_bus_buffer.scala 266:97]
   wire  _T_1020 = _T_1018 & _T_1019; // @[lsu_bus_buffer.scala 266:80]
   wire  _T_1022 = _T_1020 & _T_938; // @[lsu_bus_buffer.scala 266:114]
-  wire  _T_1911 = |buf_age_3; // @[lsu_bus_buffer.scala 380:58]
-  wire  _T_1912 = ~_T_1911; // @[lsu_bus_buffer.scala 380:45]
-  wire  _T_1914 = _T_1912 & _T_2583; // @[lsu_bus_buffer.scala 380:63]
-  wire  _T_1916 = _T_1914 & _T_4431; // @[lsu_bus_buffer.scala 380:88]
-  wire  _T_1905 = |buf_age_2; // @[lsu_bus_buffer.scala 380:58]
-  wire  _T_1906 = ~_T_1905; // @[lsu_bus_buffer.scala 380:45]
-  wire  _T_1908 = _T_1906 & _T_2576; // @[lsu_bus_buffer.scala 380:63]
-  wire  _T_1910 = _T_1908 & _T_4426; // @[lsu_bus_buffer.scala 380:88]
-  wire  _T_1899 = |buf_age_1; // @[lsu_bus_buffer.scala 380:58]
-  wire  _T_1900 = ~_T_1899; // @[lsu_bus_buffer.scala 380:45]
-  wire  _T_1902 = _T_1900 & _T_2569; // @[lsu_bus_buffer.scala 380:63]
-  wire  _T_1904 = _T_1902 & _T_4421; // @[lsu_bus_buffer.scala 380:88]
-  wire  _T_1893 = |buf_age_0; // @[lsu_bus_buffer.scala 380:58]
-  wire  _T_1894 = ~_T_1893; // @[lsu_bus_buffer.scala 380:45]
-  wire  _T_1896 = _T_1894 & _T_2562; // @[lsu_bus_buffer.scala 380:63]
-  wire  _T_1898 = _T_1896 & _T_4416; // @[lsu_bus_buffer.scala 380:88]
-  wire [3:0] CmdPtr0Dec = {_T_1916,_T_1910,_T_1904,_T_1898}; // @[Cat.scala 29:58]
-  wire [7:0] _T_1986 = {4'h0,_T_1916,_T_1910,_T_1904,_T_1898}; // @[Cat.scala 29:58]
-  wire  _T_1989 = _T_1986[4] | _T_1986[5]; // @[lsu_bus_buffer.scala 388:42]
-  wire  _T_1991 = _T_1989 | _T_1986[6]; // @[lsu_bus_buffer.scala 388:48]
-  wire  _T_1993 = _T_1991 | _T_1986[7]; // @[lsu_bus_buffer.scala 388:54]
-  wire  _T_1996 = _T_1986[2] | _T_1986[3]; // @[lsu_bus_buffer.scala 388:67]
-  wire  _T_1998 = _T_1996 | _T_1986[6]; // @[lsu_bus_buffer.scala 388:73]
-  wire  _T_2000 = _T_1998 | _T_1986[7]; // @[lsu_bus_buffer.scala 388:79]
-  wire  _T_2003 = _T_1986[1] | _T_1986[3]; // @[lsu_bus_buffer.scala 388:92]
-  wire  _T_2005 = _T_2003 | _T_1986[5]; // @[lsu_bus_buffer.scala 388:98]
-  wire  _T_2007 = _T_2005 | _T_1986[7]; // @[lsu_bus_buffer.scala 388:104]
-  wire [2:0] _T_2009 = {_T_1993,_T_2000,_T_2007}; // @[Cat.scala 29:58]
-  wire [1:0] CmdPtr0 = _T_2009[1:0]; // @[lsu_bus_buffer.scala 393:11]
+  wire  _T_1918 = |buf_age_3; // @[lsu_bus_buffer.scala 381:58]
+  wire  _T_1919 = ~_T_1918; // @[lsu_bus_buffer.scala 381:45]
+  wire  _T_1921 = _T_1919 & _T_2590; // @[lsu_bus_buffer.scala 381:63]
+  wire  _T_1912 = |buf_age_2; // @[lsu_bus_buffer.scala 381:58]
+  wire  _T_1913 = ~_T_1912; // @[lsu_bus_buffer.scala 381:45]
+  wire  _T_1915 = _T_1913 & _T_2583; // @[lsu_bus_buffer.scala 381:63]
+  wire  _T_1906 = |buf_age_1; // @[lsu_bus_buffer.scala 381:58]
+  wire  _T_1907 = ~_T_1906; // @[lsu_bus_buffer.scala 381:45]
+  wire  _T_1909 = _T_1907 & _T_2576; // @[lsu_bus_buffer.scala 381:63]
+  wire  _T_1900 = |buf_age_0; // @[lsu_bus_buffer.scala 381:58]
+  wire  _T_1901 = ~_T_1900; // @[lsu_bus_buffer.scala 381:45]
+  wire  _T_1903 = _T_1901 & _T_2569; // @[lsu_bus_buffer.scala 381:63]
+  wire [3:0] CmdPtr0Dec = {_T_1921,_T_1915,_T_1909,_T_1903}; // @[Cat.scala 29:58]
+  wire [7:0] _T_1993 = {4'h0,_T_1921,_T_1915,_T_1909,_T_1903}; // @[Cat.scala 29:58]
+  wire  _T_1996 = _T_1993[4] | _T_1993[5]; // @[lsu_bus_buffer.scala 389:42]
+  wire  _T_1998 = _T_1996 | _T_1993[6]; // @[lsu_bus_buffer.scala 389:48]
+  wire  _T_2000 = _T_1998 | _T_1993[7]; // @[lsu_bus_buffer.scala 389:54]
+  wire  _T_2003 = _T_1993[2] | _T_1993[3]; // @[lsu_bus_buffer.scala 389:67]
+  wire  _T_2005 = _T_2003 | _T_1993[6]; // @[lsu_bus_buffer.scala 389:73]
+  wire  _T_2007 = _T_2005 | _T_1993[7]; // @[lsu_bus_buffer.scala 389:79]
+  wire  _T_2010 = _T_1993[1] | _T_1993[3]; // @[lsu_bus_buffer.scala 389:92]
+  wire  _T_2012 = _T_2010 | _T_1993[5]; // @[lsu_bus_buffer.scala 389:98]
+  wire  _T_2014 = _T_2012 | _T_1993[7]; // @[lsu_bus_buffer.scala 389:104]
+  wire [2:0] _T_2016 = {_T_2000,_T_2007,_T_2014}; // @[Cat.scala 29:58]
+  wire [1:0] CmdPtr0 = _T_2016[1:0]; // @[lsu_bus_buffer.scala 394:11]
   wire  _T_1023 = CmdPtr0 == 2'h0; // @[lsu_bus_buffer.scala 267:114]
   wire  _T_1024 = CmdPtr0 == 2'h1; // @[lsu_bus_buffer.scala 267:114]
   wire  _T_1025 = CmdPtr0 == 2'h2; // @[lsu_bus_buffer.scala 267:114]
@@ -6300,11 +6159,11 @@ module lsu_bus_buffer(
   wire  _T_1033 = _T_1032 | _T_1030; // @[Mux.scala 27:72]
   wire  _T_1035 = ~_T_1033; // @[lsu_bus_buffer.scala 267:31]
   wire  _T_1036 = _T_1022 & _T_1035; // @[lsu_bus_buffer.scala 267:29]
-  reg  _T_4314; // @[Reg.scala 27:20]
-  reg  _T_4311; // @[Reg.scala 27:20]
-  reg  _T_4308; // @[Reg.scala 27:20]
-  reg  _T_4305; // @[Reg.scala 27:20]
-  wire [3:0] buf_sideeffect = {_T_4314,_T_4311,_T_4308,_T_4305}; // @[Cat.scala 29:58]
+  reg  _T_4325; // @[Reg.scala 27:20]
+  reg  _T_4322; // @[Reg.scala 27:20]
+  reg  _T_4319; // @[Reg.scala 27:20]
+  reg  _T_4316; // @[Reg.scala 27:20]
+  wire [3:0] buf_sideeffect = {_T_4325,_T_4322,_T_4319,_T_4316}; // @[Cat.scala 29:58]
   wire  _T_1045 = _T_1023 & buf_sideeffect[0]; // @[Mux.scala 27:72]
   wire  _T_1046 = _T_1024 & buf_sideeffect[1]; // @[Mux.scala 27:72]
   wire  _T_1047 = _T_1025 & buf_sideeffect[2]; // @[Mux.scala 27:72]
@@ -6327,51 +6186,43 @@ module lsu_bus_buffer(
   wire  obuf_force_wr_en = _T_1067 & _T_1085; // @[lsu_bus_buffer.scala 270:101]
   wire  _T_1055 = ~obuf_force_wr_en; // @[lsu_bus_buffer.scala 268:119]
   wire  obuf_wr_wait = _T_1054 & _T_1055; // @[lsu_bus_buffer.scala 268:117]
-  wire  _T_1056 = |buf_numvld_cmd_any; // @[lsu_bus_buffer.scala 269:75]
-  wire  _T_1057 = obuf_wr_timer < 3'h7; // @[lsu_bus_buffer.scala 269:95]
-  wire  _T_1058 = _T_1056 & _T_1057; // @[lsu_bus_buffer.scala 269:79]
-  wire [2:0] _T_1060 = obuf_wr_timer + 3'h1; // @[lsu_bus_buffer.scala 269:123]
-  wire  _T_4466 = buf_state_3 == 3'h1; // @[lsu_bus_buffer.scala 531:63]
-  wire  _T_4470 = _T_4466 | _T_4447; // @[lsu_bus_buffer.scala 531:74]
-  wire  _T_4461 = buf_state_2 == 3'h1; // @[lsu_bus_buffer.scala 531:63]
-  wire  _T_4465 = _T_4461 | _T_4444; // @[lsu_bus_buffer.scala 531:74]
-  wire [1:0] _T_4471 = _T_4470 + _T_4465; // @[lsu_bus_buffer.scala 531:154]
-  wire  _T_4456 = buf_state_1 == 3'h1; // @[lsu_bus_buffer.scala 531:63]
-  wire  _T_4460 = _T_4456 | _T_4441; // @[lsu_bus_buffer.scala 531:74]
-  wire [1:0] _GEN_370 = {{1'd0}, _T_4460}; // @[lsu_bus_buffer.scala 531:154]
-  wire [2:0] _T_4472 = _T_4471 + _GEN_370; // @[lsu_bus_buffer.scala 531:154]
-  wire  _T_4451 = buf_state_0 == 3'h1; // @[lsu_bus_buffer.scala 531:63]
-  wire  _T_4455 = _T_4451 | _T_4438; // @[lsu_bus_buffer.scala 531:74]
-  wire [2:0] _GEN_371 = {{2'd0}, _T_4455}; // @[lsu_bus_buffer.scala 531:154]
-  wire [3:0] buf_numvld_pend_any = _T_4472 + _GEN_371; // @[lsu_bus_buffer.scala 531:154]
+  wire  _T_4477 = buf_state_3 == 3'h1; // @[lsu_bus_buffer.scala 533:63]
+  wire  _T_4481 = _T_4477 | _T_2590; // @[lsu_bus_buffer.scala 533:74]
+  wire  _T_4472 = buf_state_2 == 3'h1; // @[lsu_bus_buffer.scala 533:63]
+  wire  _T_4476 = _T_4472 | _T_2583; // @[lsu_bus_buffer.scala 533:74]
+  wire [1:0] _T_4482 = _T_4481 + _T_4476; // @[lsu_bus_buffer.scala 533:154]
+  wire  _T_4467 = buf_state_1 == 3'h1; // @[lsu_bus_buffer.scala 533:63]
+  wire  _T_4471 = _T_4467 | _T_2576; // @[lsu_bus_buffer.scala 533:74]
+  wire [1:0] _GEN_380 = {{1'd0}, _T_4471}; // @[lsu_bus_buffer.scala 533:154]
+  wire [2:0] _T_4483 = _T_4482 + _GEN_380; // @[lsu_bus_buffer.scala 533:154]
+  wire  _T_4462 = buf_state_0 == 3'h1; // @[lsu_bus_buffer.scala 533:63]
+  wire  _T_4466 = _T_4462 | _T_2569; // @[lsu_bus_buffer.scala 533:74]
+  wire [2:0] _GEN_381 = {{2'd0}, _T_4466}; // @[lsu_bus_buffer.scala 533:154]
+  wire [3:0] buf_numvld_pend_any = _T_4483 + _GEN_381; // @[lsu_bus_buffer.scala 533:154]
   wire  _T_1087 = buf_numvld_pend_any == 4'h0; // @[lsu_bus_buffer.scala 272:53]
   wire  _T_1088 = ibuf_byp & _T_1087; // @[lsu_bus_buffer.scala 272:31]
   wire  _T_1089 = ~io_lsu_pkt_r_bits_store; // @[lsu_bus_buffer.scala 272:64]
   wire  _T_1090 = _T_1089 | io_no_dword_merge_r; // @[lsu_bus_buffer.scala 272:89]
   wire  ibuf_buf_byp = _T_1088 & _T_1090; // @[lsu_bus_buffer.scala 272:61]
-  wire  _T_1091 = ibuf_buf_byp & io_lsu_commit_r; // @[lsu_bus_buffer.scala 287:32]
-  wire  _T_4740 = buf_state_0 == 3'h3; // @[lsu_bus_buffer.scala 559:62]
-  wire  _T_4742 = _T_4740 & buf_sideeffect[0]; // @[lsu_bus_buffer.scala 559:73]
-  wire  _T_4743 = _T_4742 & io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_buffer.scala 559:93]
-  wire  _T_4744 = buf_state_1 == 3'h3; // @[lsu_bus_buffer.scala 559:62]
-  wire  _T_4746 = _T_4744 & buf_sideeffect[1]; // @[lsu_bus_buffer.scala 559:73]
-  wire  _T_4747 = _T_4746 & io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_buffer.scala 559:93]
-  wire  _T_4756 = _T_4743 | _T_4747; // @[lsu_bus_buffer.scala 559:153]
-  wire  _T_4748 = buf_state_2 == 3'h3; // @[lsu_bus_buffer.scala 559:62]
-  wire  _T_4750 = _T_4748 & buf_sideeffect[2]; // @[lsu_bus_buffer.scala 559:73]
-  wire  _T_4751 = _T_4750 & io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_buffer.scala 559:93]
-  wire  _T_4757 = _T_4756 | _T_4751; // @[lsu_bus_buffer.scala 559:153]
-  wire  _T_4752 = buf_state_3 == 3'h3; // @[lsu_bus_buffer.scala 559:62]
-  wire  _T_4754 = _T_4752 & buf_sideeffect[3]; // @[lsu_bus_buffer.scala 559:73]
-  wire  _T_4755 = _T_4754 & io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_buffer.scala 559:93]
-  wire  _T_4758 = _T_4757 | _T_4755; // @[lsu_bus_buffer.scala 559:153]
-  reg  obuf_sideeffect; // @[Reg.scala 27:20]
-  wire  _T_4759 = obuf_valid & obuf_sideeffect; // @[lsu_bus_buffer.scala 559:171]
-  wire  _T_4760 = _T_4759 & io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_buffer.scala 559:189]
-  wire  bus_sideeffect_pend = _T_4758 | _T_4760; // @[lsu_bus_buffer.scala 559:157]
-  wire  _T_1092 = io_is_sideeffects_r & bus_sideeffect_pend; // @[lsu_bus_buffer.scala 287:74]
-  wire  _T_1093 = ~_T_1092; // @[lsu_bus_buffer.scala 287:52]
-  wire  _T_1094 = _T_1091 & _T_1093; // @[lsu_bus_buffer.scala 287:50]
+  wire  _T_1091 = ibuf_buf_byp & io_lsu_commit_r; // @[lsu_bus_buffer.scala 288:32]
+  wire  _T_4751 = buf_state_0 == 3'h3; // @[lsu_bus_buffer.scala 561:62]
+  wire  _T_4753 = _T_4751 & buf_sideeffect[0]; // @[lsu_bus_buffer.scala 561:73]
+  wire  _T_4754 = _T_4753 & io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_buffer.scala 561:93]
+  wire  _T_4755 = buf_state_1 == 3'h3; // @[lsu_bus_buffer.scala 561:62]
+  wire  _T_4757 = _T_4755 & buf_sideeffect[1]; // @[lsu_bus_buffer.scala 561:73]
+  wire  _T_4758 = _T_4757 & io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_buffer.scala 561:93]
+  wire  _T_4767 = _T_4754 | _T_4758; // @[lsu_bus_buffer.scala 561:153]
+  wire  _T_4759 = buf_state_2 == 3'h3; // @[lsu_bus_buffer.scala 561:62]
+  wire  _T_4761 = _T_4759 & buf_sideeffect[2]; // @[lsu_bus_buffer.scala 561:73]
+  wire  _T_4762 = _T_4761 & io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_buffer.scala 561:93]
+  wire  _T_4768 = _T_4767 | _T_4762; // @[lsu_bus_buffer.scala 561:153]
+  wire  _T_4763 = buf_state_3 == 3'h3; // @[lsu_bus_buffer.scala 561:62]
+  wire  _T_4765 = _T_4763 & buf_sideeffect[3]; // @[lsu_bus_buffer.scala 561:73]
+  wire  _T_4766 = _T_4765 & io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_buffer.scala 561:93]
+  wire  bus_sideeffect_pend = _T_4768 | _T_4766; // @[lsu_bus_buffer.scala 561:153]
+  wire  _T_1092 = io_is_sideeffects_r & bus_sideeffect_pend; // @[lsu_bus_buffer.scala 288:74]
+  wire  _T_1093 = ~_T_1092; // @[lsu_bus_buffer.scala 288:52]
+  wire  _T_1094 = _T_1091 & _T_1093; // @[lsu_bus_buffer.scala 288:50]
   wire [2:0] _T_1099 = _T_1023 ? buf_state_0 : 3'h0; // @[Mux.scala 27:72]
   wire [2:0] _T_1100 = _T_1024 ? buf_state_1 : 3'h0; // @[Mux.scala 27:72]
   wire [2:0] _T_1103 = _T_1099 | _T_1100; // @[Mux.scala 27:72]
@@ -6379,22 +6230,12 @@ module lsu_bus_buffer(
   wire [2:0] _T_1104 = _T_1103 | _T_1101; // @[Mux.scala 27:72]
   wire [2:0] _T_1102 = _T_1026 ? buf_state_3 : 3'h0; // @[Mux.scala 27:72]
   wire [2:0] _T_1105 = _T_1104 | _T_1102; // @[Mux.scala 27:72]
-  wire  _T_1107 = _T_1105 == 3'h2; // @[lsu_bus_buffer.scala 288:36]
-  wire  found_cmdptr0 = |CmdPtr0Dec; // @[lsu_bus_buffer.scala 385:31]
-  wire  _T_1108 = _T_1107 & found_cmdptr0; // @[lsu_bus_buffer.scala 288:47]
-  wire [3:0] _T_1111 = {buf_cmd_state_bus_en_3,buf_cmd_state_bus_en_2,buf_cmd_state_bus_en_1,buf_cmd_state_bus_en_0}; // @[Cat.scala 29:58]
-  wire  _T_1120 = _T_1023 & _T_1111[0]; // @[Mux.scala 27:72]
-  wire  _T_1121 = _T_1024 & _T_1111[1]; // @[Mux.scala 27:72]
-  wire  _T_1124 = _T_1120 | _T_1121; // @[Mux.scala 27:72]
-  wire  _T_1122 = _T_1025 & _T_1111[2]; // @[Mux.scala 27:72]
-  wire  _T_1125 = _T_1124 | _T_1122; // @[Mux.scala 27:72]
-  wire  _T_1123 = _T_1026 & _T_1111[3]; // @[Mux.scala 27:72]
-  wire  _T_1126 = _T_1125 | _T_1123; // @[Mux.scala 27:72]
-  wire  _T_1128 = ~_T_1126; // @[lsu_bus_buffer.scala 289:23]
-  wire  _T_1129 = _T_1108 & _T_1128; // @[lsu_bus_buffer.scala 289:21]
-  wire  _T_1146 = _T_1051 & bus_sideeffect_pend; // @[lsu_bus_buffer.scala 289:141]
-  wire  _T_1147 = ~_T_1146; // @[lsu_bus_buffer.scala 289:105]
-  wire  _T_1148 = _T_1129 & _T_1147; // @[lsu_bus_buffer.scala 289:103]
+  wire  _T_1107 = _T_1105 == 3'h2; // @[lsu_bus_buffer.scala 289:36]
+  wire  found_cmdptr0 = |CmdPtr0Dec; // @[lsu_bus_buffer.scala 386:31]
+  wire  _T_1108 = _T_1107 & found_cmdptr0; // @[lsu_bus_buffer.scala 289:47]
+  wire  _T_1146 = _T_1051 & bus_sideeffect_pend; // @[lsu_bus_buffer.scala 290:141]
+  wire  _T_1147 = ~_T_1146; // @[lsu_bus_buffer.scala 290:105]
+  wire  _T_1148 = _T_1108 & _T_1147; // @[lsu_bus_buffer.scala 290:103]
   reg  buf_dual_3; // @[Reg.scala 27:20]
   reg  buf_dual_2; // @[Reg.scala 27:20]
   reg  buf_dual_1; // @[Reg.scala 27:20]
@@ -6419,7 +6260,7 @@ module lsu_bus_buffer(
   wire  _T_1184 = _T_1183 | _T_1181; // @[Mux.scala 27:72]
   wire  _T_1182 = _T_1026 & _T_1170[3]; // @[Mux.scala 27:72]
   wire  _T_1185 = _T_1184 | _T_1182; // @[Mux.scala 27:72]
-  wire  _T_1187 = _T_1166 & _T_1185; // @[lsu_bus_buffer.scala 290:77]
+  wire  _T_1187 = _T_1166 & _T_1185; // @[lsu_bus_buffer.scala 291:77]
   wire  _T_1196 = _T_1023 & buf_write[0]; // @[Mux.scala 27:72]
   wire  _T_1197 = _T_1024 & buf_write[1]; // @[Mux.scala 27:72]
   wire  _T_1200 = _T_1196 | _T_1197; // @[Mux.scala 27:72]
@@ -6427,41 +6268,37 @@ module lsu_bus_buffer(
   wire  _T_1201 = _T_1200 | _T_1198; // @[Mux.scala 27:72]
   wire  _T_1199 = _T_1026 & buf_write[3]; // @[Mux.scala 27:72]
   wire  _T_1202 = _T_1201 | _T_1199; // @[Mux.scala 27:72]
-  wire  _T_1204 = ~_T_1202; // @[lsu_bus_buffer.scala 290:150]
-  wire  _T_1205 = _T_1187 & _T_1204; // @[lsu_bus_buffer.scala 290:148]
-  wire  _T_1206 = ~_T_1205; // @[lsu_bus_buffer.scala 290:8]
-  wire [3:0] _T_1952 = ~CmdPtr0Dec; // @[lsu_bus_buffer.scala 381:62]
-  wire [3:0] _T_1953 = buf_age_3 & _T_1952; // @[lsu_bus_buffer.scala 381:59]
-  wire  _T_1954 = |_T_1953; // @[lsu_bus_buffer.scala 381:76]
-  wire  _T_1955 = ~_T_1954; // @[lsu_bus_buffer.scala 381:45]
-  wire  _T_1957 = ~CmdPtr0Dec[3]; // @[lsu_bus_buffer.scala 381:83]
-  wire  _T_1958 = _T_1955 & _T_1957; // @[lsu_bus_buffer.scala 381:81]
-  wire  _T_1960 = _T_1958 & _T_2583; // @[lsu_bus_buffer.scala 381:98]
-  wire  _T_1962 = _T_1960 & _T_4431; // @[lsu_bus_buffer.scala 381:123]
-  wire [3:0] _T_1942 = buf_age_2 & _T_1952; // @[lsu_bus_buffer.scala 381:59]
-  wire  _T_1943 = |_T_1942; // @[lsu_bus_buffer.scala 381:76]
-  wire  _T_1944 = ~_T_1943; // @[lsu_bus_buffer.scala 381:45]
-  wire  _T_1946 = ~CmdPtr0Dec[2]; // @[lsu_bus_buffer.scala 381:83]
-  wire  _T_1947 = _T_1944 & _T_1946; // @[lsu_bus_buffer.scala 381:81]
-  wire  _T_1949 = _T_1947 & _T_2576; // @[lsu_bus_buffer.scala 381:98]
-  wire  _T_1951 = _T_1949 & _T_4426; // @[lsu_bus_buffer.scala 381:123]
-  wire [3:0] _T_1931 = buf_age_1 & _T_1952; // @[lsu_bus_buffer.scala 381:59]
-  wire  _T_1932 = |_T_1931; // @[lsu_bus_buffer.scala 381:76]
-  wire  _T_1933 = ~_T_1932; // @[lsu_bus_buffer.scala 381:45]
-  wire  _T_1935 = ~CmdPtr0Dec[1]; // @[lsu_bus_buffer.scala 381:83]
-  wire  _T_1936 = _T_1933 & _T_1935; // @[lsu_bus_buffer.scala 381:81]
-  wire  _T_1938 = _T_1936 & _T_2569; // @[lsu_bus_buffer.scala 381:98]
-  wire  _T_1940 = _T_1938 & _T_4421; // @[lsu_bus_buffer.scala 381:123]
-  wire [3:0] _T_1920 = buf_age_0 & _T_1952; // @[lsu_bus_buffer.scala 381:59]
-  wire  _T_1921 = |_T_1920; // @[lsu_bus_buffer.scala 381:76]
-  wire  _T_1922 = ~_T_1921; // @[lsu_bus_buffer.scala 381:45]
-  wire  _T_1924 = ~CmdPtr0Dec[0]; // @[lsu_bus_buffer.scala 381:83]
-  wire  _T_1925 = _T_1922 & _T_1924; // @[lsu_bus_buffer.scala 381:81]
-  wire  _T_1927 = _T_1925 & _T_2562; // @[lsu_bus_buffer.scala 381:98]
-  wire  _T_1929 = _T_1927 & _T_4416; // @[lsu_bus_buffer.scala 381:123]
-  wire [3:0] CmdPtr1Dec = {_T_1962,_T_1951,_T_1940,_T_1929}; // @[Cat.scala 29:58]
-  wire  found_cmdptr1 = |CmdPtr1Dec; // @[lsu_bus_buffer.scala 386:31]
-  wire  _T_1207 = _T_1206 | found_cmdptr1; // @[lsu_bus_buffer.scala 290:181]
+  wire  _T_1204 = ~_T_1202; // @[lsu_bus_buffer.scala 291:150]
+  wire  _T_1205 = _T_1187 & _T_1204; // @[lsu_bus_buffer.scala 291:148]
+  wire  _T_1206 = ~_T_1205; // @[lsu_bus_buffer.scala 291:8]
+  wire [3:0] _T_1959 = ~CmdPtr0Dec; // @[lsu_bus_buffer.scala 382:62]
+  wire [3:0] _T_1960 = buf_age_3 & _T_1959; // @[lsu_bus_buffer.scala 382:59]
+  wire  _T_1961 = |_T_1960; // @[lsu_bus_buffer.scala 382:76]
+  wire  _T_1962 = ~_T_1961; // @[lsu_bus_buffer.scala 382:45]
+  wire  _T_1964 = ~CmdPtr0Dec[3]; // @[lsu_bus_buffer.scala 382:83]
+  wire  _T_1965 = _T_1962 & _T_1964; // @[lsu_bus_buffer.scala 382:81]
+  wire  _T_1967 = _T_1965 & _T_2590; // @[lsu_bus_buffer.scala 382:98]
+  wire [3:0] _T_1949 = buf_age_2 & _T_1959; // @[lsu_bus_buffer.scala 382:59]
+  wire  _T_1950 = |_T_1949; // @[lsu_bus_buffer.scala 382:76]
+  wire  _T_1951 = ~_T_1950; // @[lsu_bus_buffer.scala 382:45]
+  wire  _T_1953 = ~CmdPtr0Dec[2]; // @[lsu_bus_buffer.scala 382:83]
+  wire  _T_1954 = _T_1951 & _T_1953; // @[lsu_bus_buffer.scala 382:81]
+  wire  _T_1956 = _T_1954 & _T_2583; // @[lsu_bus_buffer.scala 382:98]
+  wire [3:0] _T_1938 = buf_age_1 & _T_1959; // @[lsu_bus_buffer.scala 382:59]
+  wire  _T_1939 = |_T_1938; // @[lsu_bus_buffer.scala 382:76]
+  wire  _T_1940 = ~_T_1939; // @[lsu_bus_buffer.scala 382:45]
+  wire  _T_1942 = ~CmdPtr0Dec[1]; // @[lsu_bus_buffer.scala 382:83]
+  wire  _T_1943 = _T_1940 & _T_1942; // @[lsu_bus_buffer.scala 382:81]
+  wire  _T_1945 = _T_1943 & _T_2576; // @[lsu_bus_buffer.scala 382:98]
+  wire [3:0] _T_1927 = buf_age_0 & _T_1959; // @[lsu_bus_buffer.scala 382:59]
+  wire  _T_1928 = |_T_1927; // @[lsu_bus_buffer.scala 382:76]
+  wire  _T_1929 = ~_T_1928; // @[lsu_bus_buffer.scala 382:45]
+  wire  _T_1931 = ~CmdPtr0Dec[0]; // @[lsu_bus_buffer.scala 382:83]
+  wire  _T_1932 = _T_1929 & _T_1931; // @[lsu_bus_buffer.scala 382:81]
+  wire  _T_1934 = _T_1932 & _T_2569; // @[lsu_bus_buffer.scala 382:98]
+  wire [3:0] CmdPtr1Dec = {_T_1967,_T_1956,_T_1945,_T_1934}; // @[Cat.scala 29:58]
+  wire  found_cmdptr1 = |CmdPtr1Dec; // @[lsu_bus_buffer.scala 387:31]
+  wire  _T_1207 = _T_1206 | found_cmdptr1; // @[lsu_bus_buffer.scala 291:181]
   wire [3:0] _T_1210 = {buf_nomerge_3,buf_nomerge_2,buf_nomerge_1,buf_nomerge_0}; // @[Cat.scala 29:58]
   wire  _T_1219 = _T_1023 & _T_1210[0]; // @[Mux.scala 27:72]
   wire  _T_1220 = _T_1024 & _T_1210[1]; // @[Mux.scala 27:72]
@@ -6470,78 +6307,44 @@ module lsu_bus_buffer(
   wire  _T_1224 = _T_1223 | _T_1221; // @[Mux.scala 27:72]
   wire  _T_1222 = _T_1026 & _T_1210[3]; // @[Mux.scala 27:72]
   wire  _T_1225 = _T_1224 | _T_1222; // @[Mux.scala 27:72]
-  wire  _T_1227 = _T_1207 | _T_1225; // @[lsu_bus_buffer.scala 290:197]
-  wire  _T_1228 = _T_1227 | obuf_force_wr_en; // @[lsu_bus_buffer.scala 290:269]
-  wire  _T_1229 = _T_1148 & _T_1228; // @[lsu_bus_buffer.scala 289:164]
-  wire  _T_1230 = _T_1094 | _T_1229; // @[lsu_bus_buffer.scala 287:98]
-  reg  obuf_write; // @[Reg.scala 27:20]
-  reg  obuf_cmd_done; // @[lsu_bus_buffer.scala 350:54]
-  reg  obuf_data_done; // @[lsu_bus_buffer.scala 351:55]
-  wire  _T_4814 = obuf_cmd_done | obuf_data_done; // @[lsu_bus_buffer.scala 563:54]
-  wire  _T_4815 = obuf_cmd_done ? io_lsu_axi_w_ready : io_lsu_axi_aw_ready; // @[lsu_bus_buffer.scala 563:75]
-  wire  _T_4816 = io_lsu_axi_aw_ready & io_lsu_axi_w_ready; // @[lsu_bus_buffer.scala 563:153]
-  wire  _T_4817 = _T_4814 ? _T_4815 : _T_4816; // @[lsu_bus_buffer.scala 563:39]
-  wire  bus_cmd_ready = obuf_write ? _T_4817 : io_lsu_axi_ar_ready; // @[lsu_bus_buffer.scala 563:23]
-  wire  _T_1231 = ~obuf_valid; // @[lsu_bus_buffer.scala 291:48]
-  wire  _T_1232 = bus_cmd_ready | _T_1231; // @[lsu_bus_buffer.scala 291:46]
+  wire  _T_1227 = _T_1207 | _T_1225; // @[lsu_bus_buffer.scala 291:197]
+  wire  _T_1228 = _T_1227 | obuf_force_wr_en; // @[lsu_bus_buffer.scala 291:269]
+  wire  _T_1229 = _T_1148 & _T_1228; // @[lsu_bus_buffer.scala 290:164]
+  wire  _T_1230 = _T_1094 | _T_1229; // @[lsu_bus_buffer.scala 288:98]
+  wire  _T_1231 = ~obuf_valid; // @[lsu_bus_buffer.scala 292:48]
+  wire  _T_1232 = io_lsu_axi_ar_ready | _T_1231; // @[lsu_bus_buffer.scala 292:46]
   reg  obuf_nosend; // @[Reg.scala 27:20]
-  wire  _T_1233 = _T_1232 | obuf_nosend; // @[lsu_bus_buffer.scala 291:60]
-  wire  _T_1234 = _T_1230 & _T_1233; // @[lsu_bus_buffer.scala 291:29]
-  wire  _T_1235 = ~obuf_wr_wait; // @[lsu_bus_buffer.scala 291:77]
-  wire  _T_1236 = _T_1234 & _T_1235; // @[lsu_bus_buffer.scala 291:75]
-  reg [31:0] obuf_addr; // @[lib.scala 374:16]
-  wire  _T_4765 = obuf_addr[31:3] == buf_addr_0[31:3]; // @[lsu_bus_buffer.scala 561:37]
-  wire  _T_4766 = obuf_valid & _T_4765; // @[lsu_bus_buffer.scala 561:19]
-  wire  _T_4768 = obuf_tag1 == 2'h0; // @[lsu_bus_buffer.scala 561:107]
-  wire  _T_4769 = obuf_merge & _T_4768; // @[lsu_bus_buffer.scala 561:95]
-  wire  _T_4770 = _T_3558 | _T_4769; // @[lsu_bus_buffer.scala 561:81]
-  wire  _T_4771 = ~_T_4770; // @[lsu_bus_buffer.scala 561:61]
-  wire  _T_4772 = _T_4766 & _T_4771; // @[lsu_bus_buffer.scala 561:59]
-  wire  _T_4806 = _T_4740 & _T_4772; // @[Mux.scala 27:72]
-  wire  _T_4776 = obuf_addr[31:3] == buf_addr_1[31:3]; // @[lsu_bus_buffer.scala 561:37]
-  wire  _T_4777 = obuf_valid & _T_4776; // @[lsu_bus_buffer.scala 561:19]
-  wire  _T_4779 = obuf_tag1 == 2'h1; // @[lsu_bus_buffer.scala 561:107]
-  wire  _T_4780 = obuf_merge & _T_4779; // @[lsu_bus_buffer.scala 561:95]
-  wire  _T_4781 = _T_3748 | _T_4780; // @[lsu_bus_buffer.scala 561:81]
-  wire  _T_4782 = ~_T_4781; // @[lsu_bus_buffer.scala 561:61]
-  wire  _T_4783 = _T_4777 & _T_4782; // @[lsu_bus_buffer.scala 561:59]
-  wire  _T_4807 = _T_4744 & _T_4783; // @[Mux.scala 27:72]
-  wire  _T_4810 = _T_4806 | _T_4807; // @[Mux.scala 27:72]
-  wire  _T_4787 = obuf_addr[31:3] == buf_addr_2[31:3]; // @[lsu_bus_buffer.scala 561:37]
-  wire  _T_4788 = obuf_valid & _T_4787; // @[lsu_bus_buffer.scala 561:19]
-  wire  _T_4790 = obuf_tag1 == 2'h2; // @[lsu_bus_buffer.scala 561:107]
-  wire  _T_4791 = obuf_merge & _T_4790; // @[lsu_bus_buffer.scala 561:95]
-  wire  _T_4792 = _T_3938 | _T_4791; // @[lsu_bus_buffer.scala 561:81]
-  wire  _T_4793 = ~_T_4792; // @[lsu_bus_buffer.scala 561:61]
-  wire  _T_4794 = _T_4788 & _T_4793; // @[lsu_bus_buffer.scala 561:59]
-  wire  _T_4808 = _T_4748 & _T_4794; // @[Mux.scala 27:72]
-  wire  _T_4811 = _T_4810 | _T_4808; // @[Mux.scala 27:72]
-  wire  _T_4798 = obuf_addr[31:3] == buf_addr_3[31:3]; // @[lsu_bus_buffer.scala 561:37]
-  wire  _T_4799 = obuf_valid & _T_4798; // @[lsu_bus_buffer.scala 561:19]
-  wire  _T_4801 = obuf_tag1 == 2'h3; // @[lsu_bus_buffer.scala 561:107]
-  wire  _T_4802 = obuf_merge & _T_4801; // @[lsu_bus_buffer.scala 561:95]
-  wire  _T_4803 = _T_4128 | _T_4802; // @[lsu_bus_buffer.scala 561:81]
-  wire  _T_4804 = ~_T_4803; // @[lsu_bus_buffer.scala 561:61]
-  wire  _T_4805 = _T_4799 & _T_4804; // @[lsu_bus_buffer.scala 561:59]
-  wire  _T_4809 = _T_4752 & _T_4805; // @[Mux.scala 27:72]
-  wire  bus_addr_match_pending = _T_4811 | _T_4809; // @[Mux.scala 27:72]
-  wire  _T_1237 = ~bus_addr_match_pending; // @[lsu_bus_buffer.scala 291:94]
-  wire  _T_1238 = _T_1236 & _T_1237; // @[lsu_bus_buffer.scala 291:92]
-  wire  obuf_wr_en = _T_1238 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 291:118]
-  wire  _T_1240 = obuf_valid & obuf_nosend; // @[lsu_bus_buffer.scala 293:47]
-  wire  bus_wcmd_sent = io_lsu_axi_aw_valid & io_lsu_axi_aw_ready; // @[lsu_bus_buffer.scala 564:40]
-  wire  _T_4821 = obuf_cmd_done | bus_wcmd_sent; // @[lsu_bus_buffer.scala 566:35]
-  wire  bus_wdata_sent = io_lsu_axi_w_valid & io_lsu_axi_w_ready; // @[lsu_bus_buffer.scala 565:40]
-  wire  _T_4822 = obuf_data_done | bus_wdata_sent; // @[lsu_bus_buffer.scala 566:70]
-  wire  _T_4823 = _T_4821 & _T_4822; // @[lsu_bus_buffer.scala 566:52]
-  wire  _T_4824 = io_lsu_axi_ar_valid & io_lsu_axi_ar_ready; // @[lsu_bus_buffer.scala 566:112]
-  wire  bus_cmd_sent = _T_4823 | _T_4824; // @[lsu_bus_buffer.scala 566:89]
-  wire  _T_1241 = bus_cmd_sent | _T_1240; // @[lsu_bus_buffer.scala 293:33]
-  wire  _T_1242 = ~obuf_wr_en; // @[lsu_bus_buffer.scala 293:65]
-  wire  _T_1243 = _T_1241 & _T_1242; // @[lsu_bus_buffer.scala 293:63]
-  wire  _T_1244 = _T_1243 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 293:77]
-  wire  obuf_rst = _T_1244 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 293:98]
-  wire  obuf_write_in = ibuf_buf_byp ? io_lsu_pkt_r_bits_store : _T_1202; // @[lsu_bus_buffer.scala 294:26]
+  wire  _T_1233 = _T_1232 | obuf_nosend; // @[lsu_bus_buffer.scala 292:60]
+  wire  _T_1234 = _T_1230 & _T_1233; // @[lsu_bus_buffer.scala 292:29]
+  wire  _T_1235 = ~obuf_wr_wait; // @[lsu_bus_buffer.scala 292:77]
+  wire  _T_1236 = _T_1234 & _T_1235; // @[lsu_bus_buffer.scala 292:75]
+  reg [31:0] obuf_addr; // @[Reg.scala 27:20]
+  wire  _T_4787 = obuf_addr[31:3] == buf_addr_1[31:3]; // @[lsu_bus_buffer.scala 563:37]
+  wire  _T_4788 = obuf_valid & _T_4787; // @[lsu_bus_buffer.scala 563:19]
+  wire  _T_4818 = _T_4755 & _T_4788; // @[Mux.scala 27:72]
+  wire  _T_4798 = obuf_addr[31:3] == buf_addr_2[31:3]; // @[lsu_bus_buffer.scala 563:37]
+  wire  _T_4799 = obuf_valid & _T_4798; // @[lsu_bus_buffer.scala 563:19]
+  wire  _T_4819 = _T_4759 & _T_4799; // @[Mux.scala 27:72]
+  wire  _T_4822 = _T_4818 | _T_4819; // @[Mux.scala 27:72]
+  wire  _T_4809 = obuf_addr[31:3] == buf_addr_3[31:3]; // @[lsu_bus_buffer.scala 563:37]
+  wire  _T_4810 = obuf_valid & _T_4809; // @[lsu_bus_buffer.scala 563:19]
+  wire  _T_4820 = _T_4763 & _T_4810; // @[Mux.scala 27:72]
+  wire  bus_addr_match_pending = _T_4822 | _T_4820; // @[Mux.scala 27:72]
+  wire  _T_1237 = ~bus_addr_match_pending; // @[lsu_bus_buffer.scala 292:94]
+  wire  _T_1238 = _T_1236 & _T_1237; // @[lsu_bus_buffer.scala 292:92]
+  wire  obuf_wr_en = _T_1238 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 292:118]
+  wire  _T_1240 = obuf_valid & obuf_nosend; // @[lsu_bus_buffer.scala 295:47]
+  wire  bus_wcmd_sent = io_lsu_axi_aw_valid & io_lsu_axi_aw_ready; // @[lsu_bus_buffer.scala 566:40]
+  wire  bus_wdata_sent = io_lsu_axi_w_valid & io_lsu_axi_w_ready; // @[lsu_bus_buffer.scala 567:40]
+  wire  _T_4834 = bus_wcmd_sent & bus_wdata_sent; // @[lsu_bus_buffer.scala 568:52]
+  wire  _T_4835 = io_lsu_axi_ar_valid & io_lsu_axi_ar_ready; // @[lsu_bus_buffer.scala 568:112]
+  wire  bus_cmd_sent = _T_4834 | _T_4835; // @[lsu_bus_buffer.scala 568:89]
+  wire  _T_1241 = bus_cmd_sent | _T_1240; // @[lsu_bus_buffer.scala 295:33]
+  wire  _T_1242 = ~obuf_wr_en; // @[lsu_bus_buffer.scala 295:65]
+  wire  _T_1243 = _T_1241 & _T_1242; // @[lsu_bus_buffer.scala 295:63]
+  wire  _T_1244 = _T_1243 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 295:77]
+  wire  obuf_rst = _T_1244 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 295:98]
+  wire  obuf_write_in = ibuf_buf_byp ? io_lsu_pkt_r_bits_store : _T_1202; // @[lsu_bus_buffer.scala 296:26]
   wire [31:0] _T_1281 = _T_1023 ? buf_addr_0 : 32'h0; // @[Mux.scala 27:72]
   wire [31:0] _T_1282 = _T_1024 ? buf_addr_1 : 32'h0; // @[Mux.scala 27:72]
   wire [31:0] _T_1283 = _T_1025 ? buf_addr_2 : 32'h0; // @[Mux.scala 27:72]
@@ -6549,7 +6352,7 @@ module lsu_bus_buffer(
   wire [31:0] _T_1285 = _T_1281 | _T_1282; // @[Mux.scala 27:72]
   wire [31:0] _T_1286 = _T_1285 | _T_1283; // @[Mux.scala 27:72]
   wire [31:0] _T_1287 = _T_1286 | _T_1284; // @[Mux.scala 27:72]
-  wire [31:0] obuf_addr_in = ibuf_buf_byp ? io_lsu_addr_r : _T_1287; // @[lsu_bus_buffer.scala 296:25]
+  wire [31:0] obuf_addr_in = ibuf_buf_byp ? io_lsu_addr_r : _T_1287; // @[lsu_bus_buffer.scala 298:25]
   reg [1:0] buf_sz_0; // @[Reg.scala 27:20]
   wire [1:0] _T_1294 = _T_1023 ? buf_sz_0 : 2'h0; // @[Mux.scala 27:72]
   reg [1:0] buf_sz_1; // @[Reg.scala 27:20]
@@ -6561,76 +6364,58 @@ module lsu_bus_buffer(
   wire [1:0] _T_1298 = _T_1294 | _T_1295; // @[Mux.scala 27:72]
   wire [1:0] _T_1299 = _T_1298 | _T_1296; // @[Mux.scala 27:72]
   wire [1:0] _T_1300 = _T_1299 | _T_1297; // @[Mux.scala 27:72]
-  wire [1:0] obuf_sz_in = ibuf_buf_byp ? ibuf_sz_in : _T_1300; // @[lsu_bus_buffer.scala 299:23]
-  wire [7:0] _T_2011 = {4'h0,_T_1962,_T_1951,_T_1940,_T_1929}; // @[Cat.scala 29:58]
-  wire  _T_2014 = _T_2011[4] | _T_2011[5]; // @[lsu_bus_buffer.scala 388:42]
-  wire  _T_2016 = _T_2014 | _T_2011[6]; // @[lsu_bus_buffer.scala 388:48]
-  wire  _T_2018 = _T_2016 | _T_2011[7]; // @[lsu_bus_buffer.scala 388:54]
-  wire  _T_2021 = _T_2011[2] | _T_2011[3]; // @[lsu_bus_buffer.scala 388:67]
-  wire  _T_2023 = _T_2021 | _T_2011[6]; // @[lsu_bus_buffer.scala 388:73]
-  wire  _T_2025 = _T_2023 | _T_2011[7]; // @[lsu_bus_buffer.scala 388:79]
-  wire  _T_2028 = _T_2011[1] | _T_2011[3]; // @[lsu_bus_buffer.scala 388:92]
-  wire  _T_2030 = _T_2028 | _T_2011[5]; // @[lsu_bus_buffer.scala 388:98]
-  wire  _T_2032 = _T_2030 | _T_2011[7]; // @[lsu_bus_buffer.scala 388:104]
-  wire [2:0] _T_2034 = {_T_2018,_T_2025,_T_2032}; // @[Cat.scala 29:58]
-  wire [1:0] CmdPtr1 = _T_2034[1:0]; // @[lsu_bus_buffer.scala 395:11]
-  wire  _T_1302 = obuf_wr_en | obuf_rst; // @[lsu_bus_buffer.scala 307:39]
-  wire  _T_1303 = ~_T_1302; // @[lsu_bus_buffer.scala 307:26]
-  wire  _T_1309 = obuf_sz_in == 2'h0; // @[lsu_bus_buffer.scala 311:72]
-  wire  _T_1312 = ~obuf_addr_in[0]; // @[lsu_bus_buffer.scala 311:98]
-  wire  _T_1313 = obuf_sz_in[0] & _T_1312; // @[lsu_bus_buffer.scala 311:96]
-  wire  _T_1314 = _T_1309 | _T_1313; // @[lsu_bus_buffer.scala 311:79]
-  wire  _T_1317 = |obuf_addr_in[1:0]; // @[lsu_bus_buffer.scala 311:153]
-  wire  _T_1318 = ~_T_1317; // @[lsu_bus_buffer.scala 311:134]
-  wire  _T_1319 = obuf_sz_in[1] & _T_1318; // @[lsu_bus_buffer.scala 311:132]
-  wire  _T_1320 = _T_1314 | _T_1319; // @[lsu_bus_buffer.scala 311:116]
-  wire  obuf_aligned_in = ibuf_buf_byp ? is_aligned_r : _T_1320; // @[lsu_bus_buffer.scala 311:28]
-  wire  _T_1337 = obuf_addr_in[31:3] == obuf_addr[31:3]; // @[lsu_bus_buffer.scala 326:40]
-  wire  _T_1338 = _T_1337 & obuf_aligned_in; // @[lsu_bus_buffer.scala 326:60]
-  wire  _T_1339 = ~obuf_sideeffect; // @[lsu_bus_buffer.scala 326:80]
-  wire  _T_1340 = _T_1338 & _T_1339; // @[lsu_bus_buffer.scala 326:78]
-  wire  _T_1341 = ~obuf_write; // @[lsu_bus_buffer.scala 326:99]
-  wire  _T_1342 = _T_1340 & _T_1341; // @[lsu_bus_buffer.scala 326:97]
-  wire  _T_1343 = ~obuf_write_in; // @[lsu_bus_buffer.scala 326:113]
-  wire  _T_1344 = _T_1342 & _T_1343; // @[lsu_bus_buffer.scala 326:111]
-  wire  _T_1345 = ~io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[lsu_bus_buffer.scala 326:130]
-  wire  _T_1346 = _T_1344 & _T_1345; // @[lsu_bus_buffer.scala 326:128]
-  wire  _T_1347 = ~obuf_nosend; // @[lsu_bus_buffer.scala 327:20]
-  wire  _T_1348 = obuf_valid & _T_1347; // @[lsu_bus_buffer.scala 327:18]
-  reg  obuf_rdrsp_pend; // @[lsu_bus_buffer.scala 352:56]
-  wire  bus_rsp_read = io_lsu_axi_r_valid & io_lsu_axi_r_ready; // @[lsu_bus_buffer.scala 567:38]
-  reg [2:0] obuf_rdrsp_tag; // @[lsu_bus_buffer.scala 353:55]
-  wire  _T_1349 = io_lsu_axi_r_bits_id == obuf_rdrsp_tag; // @[lsu_bus_buffer.scala 327:90]
-  wire  _T_1350 = bus_rsp_read & _T_1349; // @[lsu_bus_buffer.scala 327:70]
-  wire  _T_1351 = ~_T_1350; // @[lsu_bus_buffer.scala 327:55]
-  wire  _T_1352 = obuf_rdrsp_pend & _T_1351; // @[lsu_bus_buffer.scala 327:53]
-  wire  _T_1353 = _T_1348 | _T_1352; // @[lsu_bus_buffer.scala 327:34]
-  wire  obuf_nosend_in = _T_1346 & _T_1353; // @[lsu_bus_buffer.scala 326:177]
-  wire  _T_1321 = ~obuf_nosend_in; // @[lsu_bus_buffer.scala 319:45]
-  wire  _T_1322 = obuf_wr_en & _T_1321; // @[lsu_bus_buffer.scala 319:43]
-  wire  _T_1323 = ~_T_1322; // @[lsu_bus_buffer.scala 319:30]
-  wire  _T_1324 = _T_1323 & obuf_rdrsp_pend; // @[lsu_bus_buffer.scala 319:62]
-  wire  _T_1328 = _T_1324 & _T_1351; // @[lsu_bus_buffer.scala 319:80]
-  wire  _T_1330 = bus_cmd_sent & _T_1341; // @[lsu_bus_buffer.scala 320:19]
-  wire  _T_1331 = _T_1328 | _T_1330; // @[lsu_bus_buffer.scala 319:139]
-  wire  obuf_rdrsp_pend_en = io_lsu_bus_clk_en | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 321:47]
-  wire [7:0] _T_1356 = {ldst_byteen_lo_r,4'h0}; // @[Cat.scala 29:58]
-  wire [7:0] _T_1357 = {4'h0,ldst_byteen_lo_r}; // @[Cat.scala 29:58]
-  wire [7:0] _T_1358 = io_lsu_addr_r[2] ? _T_1356 : _T_1357; // @[lsu_bus_buffer.scala 328:46]
-  wire [3:0] _T_1377 = _T_1023 ? buf_byteen_0 : 4'h0; // @[Mux.scala 27:72]
-  wire [3:0] _T_1378 = _T_1024 ? buf_byteen_1 : 4'h0; // @[Mux.scala 27:72]
-  wire [3:0] _T_1379 = _T_1025 ? buf_byteen_2 : 4'h0; // @[Mux.scala 27:72]
-  wire [3:0] _T_1380 = _T_1026 ? buf_byteen_3 : 4'h0; // @[Mux.scala 27:72]
-  wire [3:0] _T_1381 = _T_1377 | _T_1378; // @[Mux.scala 27:72]
-  wire [3:0] _T_1382 = _T_1381 | _T_1379; // @[Mux.scala 27:72]
-  wire [3:0] _T_1383 = _T_1382 | _T_1380; // @[Mux.scala 27:72]
-  wire [7:0] _T_1385 = {_T_1383,4'h0}; // @[Cat.scala 29:58]
-  wire [7:0] _T_1398 = {4'h0,_T_1383}; // @[Cat.scala 29:58]
-  wire [7:0] _T_1399 = _T_1287[2] ? _T_1385 : _T_1398; // @[lsu_bus_buffer.scala 329:8]
-  wire [7:0] obuf_byteen0_in = ibuf_buf_byp ? _T_1358 : _T_1399; // @[lsu_bus_buffer.scala 328:28]
+  wire [1:0] obuf_sz_in = ibuf_buf_byp ? ibuf_sz_in : _T_1300; // @[lsu_bus_buffer.scala 301:23]
+  wire [7:0] _T_2018 = {4'h0,_T_1967,_T_1956,_T_1945,_T_1934}; // @[Cat.scala 29:58]
+  wire  _T_2021 = _T_2018[4] | _T_2018[5]; // @[lsu_bus_buffer.scala 389:42]
+  wire  _T_2023 = _T_2021 | _T_2018[6]; // @[lsu_bus_buffer.scala 389:48]
+  wire  _T_2025 = _T_2023 | _T_2018[7]; // @[lsu_bus_buffer.scala 389:54]
+  wire  _T_2028 = _T_2018[2] | _T_2018[3]; // @[lsu_bus_buffer.scala 389:67]
+  wire  _T_2030 = _T_2028 | _T_2018[6]; // @[lsu_bus_buffer.scala 389:73]
+  wire  _T_2032 = _T_2030 | _T_2018[7]; // @[lsu_bus_buffer.scala 389:79]
+  wire  _T_2035 = _T_2018[1] | _T_2018[3]; // @[lsu_bus_buffer.scala 389:92]
+  wire  _T_2037 = _T_2035 | _T_2018[5]; // @[lsu_bus_buffer.scala 389:98]
+  wire  _T_2039 = _T_2037 | _T_2018[7]; // @[lsu_bus_buffer.scala 389:104]
+  wire [2:0] _T_2041 = {_T_2025,_T_2032,_T_2039}; // @[Cat.scala 29:58]
+  wire [1:0] CmdPtr1 = _T_2041[1:0]; // @[lsu_bus_buffer.scala 396:11]
+  wire  _T_1302 = obuf_wr_en | obuf_rst; // @[lsu_bus_buffer.scala 309:39]
+  wire  _T_1303 = ~_T_1302; // @[lsu_bus_buffer.scala 309:26]
+  wire  obuf_data_done_in = _T_1303 & bus_wdata_sent; // @[lsu_bus_buffer.scala 312:52]
+  wire  _T_1309 = obuf_sz_in == 2'h0; // @[lsu_bus_buffer.scala 313:72]
+  wire  _T_1312 = ~obuf_addr_in[0]; // @[lsu_bus_buffer.scala 313:98]
+  wire  _T_1313 = obuf_sz_in[0] & _T_1312; // @[lsu_bus_buffer.scala 313:96]
+  wire  _T_1314 = _T_1309 | _T_1313; // @[lsu_bus_buffer.scala 313:79]
+  wire  _T_1317 = |obuf_addr_in[1:0]; // @[lsu_bus_buffer.scala 313:153]
+  wire  _T_1318 = ~_T_1317; // @[lsu_bus_buffer.scala 313:134]
+  wire  _T_1319 = obuf_sz_in[1] & _T_1318; // @[lsu_bus_buffer.scala 313:132]
+  wire  _T_1320 = _T_1314 | _T_1319; // @[lsu_bus_buffer.scala 313:116]
+  wire  obuf_aligned_in = ibuf_buf_byp ? is_aligned_r : _T_1320; // @[lsu_bus_buffer.scala 313:28]
+  wire  _T_1337 = obuf_addr_in[31:3] == obuf_addr[31:3]; // @[lsu_bus_buffer.scala 327:40]
+  wire  _T_1338 = _T_1337 & obuf_aligned_in; // @[lsu_bus_buffer.scala 327:60]
+  wire  _T_1343 = ~obuf_write_in; // @[lsu_bus_buffer.scala 327:113]
+  wire  _T_1344 = _T_1338 & _T_1343; // @[lsu_bus_buffer.scala 327:111]
+  wire  _T_1345 = ~io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[lsu_bus_buffer.scala 327:130]
+  wire  _T_1346 = _T_1344 & _T_1345; // @[lsu_bus_buffer.scala 327:128]
+  wire  _T_1347 = ~obuf_nosend; // @[lsu_bus_buffer.scala 328:20]
+  wire  _T_1348 = obuf_valid & _T_1347; // @[lsu_bus_buffer.scala 328:18]
+  reg  obuf_rdrsp_pend; // @[Reg.scala 27:20]
+  wire  bus_rsp_read = io_lsu_axi_r_valid & io_lsu_axi_r_ready; // @[lsu_bus_buffer.scala 569:38]
+  wire  _T_1349 = io_lsu_axi_r_bits_id == 3'h0; // @[lsu_bus_buffer.scala 328:90]
+  wire  _T_1350 = bus_rsp_read & _T_1349; // @[lsu_bus_buffer.scala 328:70]
+  wire  _T_1351 = ~_T_1350; // @[lsu_bus_buffer.scala 328:55]
+  wire  _T_1352 = obuf_rdrsp_pend & _T_1351; // @[lsu_bus_buffer.scala 328:53]
+  wire  _T_1353 = _T_1348 | _T_1352; // @[lsu_bus_buffer.scala 328:34]
+  wire  obuf_nosend_in = _T_1346 & _T_1353; // @[lsu_bus_buffer.scala 327:177]
+  wire  _T_1321 = ~obuf_nosend_in; // @[lsu_bus_buffer.scala 321:45]
+  wire  _T_1322 = obuf_wr_en & _T_1321; // @[lsu_bus_buffer.scala 321:43]
+  wire  _T_1323 = ~_T_1322; // @[lsu_bus_buffer.scala 321:30]
+  wire  _T_1324 = _T_1323 & obuf_rdrsp_pend; // @[lsu_bus_buffer.scala 321:62]
+  wire  _T_1328 = _T_1324 & _T_1351; // @[lsu_bus_buffer.scala 321:80]
+  wire  _T_1331 = _T_1328 | bus_cmd_sent; // @[lsu_bus_buffer.scala 321:139]
+  wire  obuf_rdrsp_pend_in = _T_1331 & _T_2594; // @[lsu_bus_buffer.scala 321:171]
+  wire  obuf_rdrsp_pend_en = io_lsu_bus_clk_en | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 322:47]
   wire [7:0] _T_1401 = {ldst_byteen_hi_r,4'h0}; // @[Cat.scala 29:58]
   wire [7:0] _T_1402 = {4'h0,ldst_byteen_hi_r}; // @[Cat.scala 29:58]
-  wire [7:0] _T_1403 = io_end_addr_r[2] ? _T_1401 : _T_1402; // @[lsu_bus_buffer.scala 330:46]
+  wire [7:0] _T_1403 = io_end_addr_r[2] ? _T_1401 : _T_1402; // @[lsu_bus_buffer.scala 331:46]
   wire  _T_1404 = CmdPtr1 == 2'h0; // @[lsu_bus_buffer.scala 61:123]
   wire  _T_1405 = CmdPtr1 == 2'h1; // @[lsu_bus_buffer.scala 61:123]
   wire  _T_1406 = CmdPtr1 == 2'h2; // @[lsu_bus_buffer.scala 61:123]
@@ -6651,11 +6436,11 @@ module lsu_bus_buffer(
   wire [3:0] _T_1428 = _T_1427 | _T_1425; // @[Mux.scala 27:72]
   wire [7:0] _T_1430 = {_T_1428,4'h0}; // @[Cat.scala 29:58]
   wire [7:0] _T_1443 = {4'h0,_T_1428}; // @[Cat.scala 29:58]
-  wire [7:0] _T_1444 = _T_1414[2] ? _T_1430 : _T_1443; // @[lsu_bus_buffer.scala 331:8]
-  wire [7:0] obuf_byteen1_in = ibuf_buf_byp ? _T_1403 : _T_1444; // @[lsu_bus_buffer.scala 330:28]
+  wire [7:0] _T_1444 = _T_1414[2] ? _T_1430 : _T_1443; // @[lsu_bus_buffer.scala 332:8]
+  wire [7:0] obuf_byteen1_in = ibuf_buf_byp ? _T_1403 : _T_1444; // @[lsu_bus_buffer.scala 331:28]
   wire [63:0] _T_1446 = {store_data_lo_r,32'h0}; // @[Cat.scala 29:58]
   wire [63:0] _T_1447 = {32'h0,store_data_lo_r}; // @[Cat.scala 29:58]
-  wire [63:0] _T_1448 = io_lsu_addr_r[2] ? _T_1446 : _T_1447; // @[lsu_bus_buffer.scala 333:44]
+  wire [63:0] _T_1448 = io_lsu_addr_r[2] ? _T_1446 : _T_1447; // @[lsu_bus_buffer.scala 334:44]
   wire [31:0] _T_1467 = _T_1023 ? buf_data_0 : 32'h0; // @[Mux.scala 27:72]
   wire [31:0] _T_1468 = _T_1024 ? buf_data_1 : 32'h0; // @[Mux.scala 27:72]
   wire [31:0] _T_1469 = _T_1025 ? buf_data_2 : 32'h0; // @[Mux.scala 27:72]
@@ -6665,11 +6450,11 @@ module lsu_bus_buffer(
   wire [31:0] _T_1473 = _T_1472 | _T_1470; // @[Mux.scala 27:72]
   wire [63:0] _T_1475 = {_T_1473,32'h0}; // @[Cat.scala 29:58]
   wire [63:0] _T_1488 = {32'h0,_T_1473}; // @[Cat.scala 29:58]
-  wire [63:0] _T_1489 = _T_1287[2] ? _T_1475 : _T_1488; // @[lsu_bus_buffer.scala 334:8]
-  wire [63:0] obuf_data0_in = ibuf_buf_byp ? _T_1448 : _T_1489; // @[lsu_bus_buffer.scala 333:26]
+  wire [63:0] _T_1489 = _T_1287[2] ? _T_1475 : _T_1488; // @[lsu_bus_buffer.scala 335:8]
+  wire [63:0] obuf_data0_in = ibuf_buf_byp ? _T_1448 : _T_1489; // @[lsu_bus_buffer.scala 334:26]
   wire [63:0] _T_1491 = {store_data_hi_r,32'h0}; // @[Cat.scala 29:58]
   wire [63:0] _T_1492 = {32'h0,store_data_hi_r}; // @[Cat.scala 29:58]
-  wire [63:0] _T_1493 = io_end_addr_r[2] ? _T_1491 : _T_1492; // @[lsu_bus_buffer.scala 335:44]
+  wire [63:0] _T_1493 = io_end_addr_r[2] ? _T_1491 : _T_1492; // @[lsu_bus_buffer.scala 336:44]
   wire [31:0] _T_1512 = _T_1404 ? buf_data_0 : 32'h0; // @[Mux.scala 27:72]
   wire [31:0] _T_1513 = _T_1405 ? buf_data_1 : 32'h0; // @[Mux.scala 27:72]
   wire [31:0] _T_1514 = _T_1406 ? buf_data_2 : 32'h0; // @[Mux.scala 27:72]
@@ -6679,12 +6464,12 @@ module lsu_bus_buffer(
   wire [31:0] _T_1518 = _T_1517 | _T_1515; // @[Mux.scala 27:72]
   wire [63:0] _T_1520 = {_T_1518,32'h0}; // @[Cat.scala 29:58]
   wire [63:0] _T_1533 = {32'h0,_T_1518}; // @[Cat.scala 29:58]
-  wire [63:0] _T_1534 = _T_1414[2] ? _T_1520 : _T_1533; // @[lsu_bus_buffer.scala 336:8]
-  wire [63:0] obuf_data1_in = ibuf_buf_byp ? _T_1493 : _T_1534; // @[lsu_bus_buffer.scala 335:26]
-  wire  _T_1619 = CmdPtr0 != CmdPtr1; // @[lsu_bus_buffer.scala 342:30]
-  wire  _T_1620 = _T_1619 & found_cmdptr0; // @[lsu_bus_buffer.scala 342:43]
-  wire  _T_1621 = _T_1620 & found_cmdptr1; // @[lsu_bus_buffer.scala 342:59]
-  wire  _T_1635 = _T_1621 & _T_1107; // @[lsu_bus_buffer.scala 342:75]
+  wire [63:0] _T_1534 = _T_1414[2] ? _T_1520 : _T_1533; // @[lsu_bus_buffer.scala 337:8]
+  wire [63:0] obuf_data1_in = ibuf_buf_byp ? _T_1493 : _T_1534; // @[lsu_bus_buffer.scala 336:26]
+  wire  _T_1619 = CmdPtr0 != CmdPtr1; // @[lsu_bus_buffer.scala 343:30]
+  wire  _T_1620 = _T_1619 & found_cmdptr0; // @[lsu_bus_buffer.scala 343:43]
+  wire  _T_1621 = _T_1620 & found_cmdptr1; // @[lsu_bus_buffer.scala 343:59]
+  wire  _T_1635 = _T_1621 & _T_1107; // @[lsu_bus_buffer.scala 343:75]
   wire [2:0] _T_1640 = _T_1404 ? buf_state_0 : 3'h0; // @[Mux.scala 27:72]
   wire [2:0] _T_1641 = _T_1405 ? buf_state_1 : 3'h0; // @[Mux.scala 27:72]
   wire [2:0] _T_1644 = _T_1640 | _T_1641; // @[Mux.scala 27:72]
@@ -6692,11 +6477,10 @@ module lsu_bus_buffer(
   wire [2:0] _T_1645 = _T_1644 | _T_1642; // @[Mux.scala 27:72]
   wire [2:0] _T_1643 = _T_1407 ? buf_state_3 : 3'h0; // @[Mux.scala 27:72]
   wire [2:0] _T_1646 = _T_1645 | _T_1643; // @[Mux.scala 27:72]
-  wire  _T_1648 = _T_1646 == 3'h2; // @[lsu_bus_buffer.scala 342:150]
-  wire  _T_1649 = _T_1635 & _T_1648; // @[lsu_bus_buffer.scala 342:118]
-  wire  _T_1670 = _T_1649 & _T_1128; // @[lsu_bus_buffer.scala 342:161]
-  wire  _T_1688 = _T_1670 & _T_1053; // @[lsu_bus_buffer.scala 343:85]
-  wire  _T_1725 = _T_1204 & _T_1166; // @[lsu_bus_buffer.scala 344:36]
+  wire  _T_1648 = _T_1646 == 3'h2; // @[lsu_bus_buffer.scala 343:150]
+  wire  _T_1649 = _T_1635 & _T_1648; // @[lsu_bus_buffer.scala 343:118]
+  wire  _T_1688 = _T_1649 & _T_1053; // @[lsu_bus_buffer.scala 344:85]
+  wire  _T_1725 = _T_1204 & _T_1166; // @[lsu_bus_buffer.scala 345:36]
   reg  buf_dualhi_3; // @[Reg.scala 27:20]
   reg  buf_dualhi_2; // @[Reg.scala 27:20]
   reg  buf_dualhi_1; // @[Reg.scala 27:20]
@@ -6709,1332 +6493,1248 @@ module lsu_bus_buffer(
   wire  _T_1742 = _T_1741 | _T_1739; // @[Mux.scala 27:72]
   wire  _T_1740 = _T_1026 & _T_1728[3]; // @[Mux.scala 27:72]
   wire  _T_1743 = _T_1742 | _T_1740; // @[Mux.scala 27:72]
-  wire  _T_1745 = ~_T_1743; // @[lsu_bus_buffer.scala 344:107]
-  wire  _T_1746 = _T_1725 & _T_1745; // @[lsu_bus_buffer.scala 344:105]
-  wire  _T_1766 = _T_1746 & _T_1185; // @[lsu_bus_buffer.scala 344:177]
-  wire  _T_1767 = _T_1688 & _T_1766; // @[lsu_bus_buffer.scala 343:122]
-  wire  _T_1768 = ibuf_buf_byp & ldst_samedw_r; // @[lsu_bus_buffer.scala 345:19]
-  wire  _T_1769 = _T_1768 & io_ldst_dual_r; // @[lsu_bus_buffer.scala 345:35]
-  wire  obuf_merge_en = _T_1767 | _T_1769; // @[lsu_bus_buffer.scala 344:250]
-  wire  _T_1537 = obuf_merge_en & obuf_byteen1_in[0]; // @[lsu_bus_buffer.scala 337:80]
-  wire  _T_1538 = obuf_byteen0_in[0] | _T_1537; // @[lsu_bus_buffer.scala 337:63]
-  wire  _T_1541 = obuf_merge_en & obuf_byteen1_in[1]; // @[lsu_bus_buffer.scala 337:80]
-  wire  _T_1542 = obuf_byteen0_in[1] | _T_1541; // @[lsu_bus_buffer.scala 337:63]
-  wire  _T_1545 = obuf_merge_en & obuf_byteen1_in[2]; // @[lsu_bus_buffer.scala 337:80]
-  wire  _T_1546 = obuf_byteen0_in[2] | _T_1545; // @[lsu_bus_buffer.scala 337:63]
-  wire  _T_1549 = obuf_merge_en & obuf_byteen1_in[3]; // @[lsu_bus_buffer.scala 337:80]
-  wire  _T_1550 = obuf_byteen0_in[3] | _T_1549; // @[lsu_bus_buffer.scala 337:63]
-  wire  _T_1553 = obuf_merge_en & obuf_byteen1_in[4]; // @[lsu_bus_buffer.scala 337:80]
-  wire  _T_1554 = obuf_byteen0_in[4] | _T_1553; // @[lsu_bus_buffer.scala 337:63]
-  wire  _T_1557 = obuf_merge_en & obuf_byteen1_in[5]; // @[lsu_bus_buffer.scala 337:80]
-  wire  _T_1558 = obuf_byteen0_in[5] | _T_1557; // @[lsu_bus_buffer.scala 337:63]
-  wire  _T_1561 = obuf_merge_en & obuf_byteen1_in[6]; // @[lsu_bus_buffer.scala 337:80]
-  wire  _T_1562 = obuf_byteen0_in[6] | _T_1561; // @[lsu_bus_buffer.scala 337:63]
-  wire  _T_1565 = obuf_merge_en & obuf_byteen1_in[7]; // @[lsu_bus_buffer.scala 337:80]
-  wire  _T_1566 = obuf_byteen0_in[7] | _T_1565; // @[lsu_bus_buffer.scala 337:63]
-  wire [7:0] obuf_byteen_in = {_T_1566,_T_1562,_T_1558,_T_1554,_T_1550,_T_1546,_T_1542,_T_1538}; // @[Cat.scala 29:58]
-  wire [7:0] _T_1577 = _T_1537 ? obuf_data1_in[7:0] : obuf_data0_in[7:0]; // @[lsu_bus_buffer.scala 338:44]
-  wire [7:0] _T_1582 = _T_1541 ? obuf_data1_in[15:8] : obuf_data0_in[15:8]; // @[lsu_bus_buffer.scala 338:44]
-  wire [7:0] _T_1587 = _T_1545 ? obuf_data1_in[23:16] : obuf_data0_in[23:16]; // @[lsu_bus_buffer.scala 338:44]
-  wire [7:0] _T_1592 = _T_1549 ? obuf_data1_in[31:24] : obuf_data0_in[31:24]; // @[lsu_bus_buffer.scala 338:44]
-  wire [7:0] _T_1597 = _T_1553 ? obuf_data1_in[39:32] : obuf_data0_in[39:32]; // @[lsu_bus_buffer.scala 338:44]
-  wire [7:0] _T_1602 = _T_1557 ? obuf_data1_in[47:40] : obuf_data0_in[47:40]; // @[lsu_bus_buffer.scala 338:44]
-  wire [7:0] _T_1607 = _T_1561 ? obuf_data1_in[55:48] : obuf_data0_in[55:48]; // @[lsu_bus_buffer.scala 338:44]
-  wire [7:0] _T_1612 = _T_1565 ? obuf_data1_in[63:56] : obuf_data0_in[63:56]; // @[lsu_bus_buffer.scala 338:44]
-  wire [55:0] _T_1618 = {_T_1612,_T_1607,_T_1602,_T_1597,_T_1592,_T_1587,_T_1582}; // @[Cat.scala 29:58]
+  wire  _T_1745 = ~_T_1743; // @[lsu_bus_buffer.scala 345:107]
+  wire  _T_1746 = _T_1725 & _T_1745; // @[lsu_bus_buffer.scala 345:105]
+  wire  _T_1766 = _T_1746 & _T_1185; // @[lsu_bus_buffer.scala 345:177]
+  wire  _T_1767 = _T_1688 & _T_1766; // @[lsu_bus_buffer.scala 344:122]
+  wire  _T_1768 = ibuf_buf_byp & ldst_samedw_r; // @[lsu_bus_buffer.scala 346:19]
+  wire  _T_1769 = _T_1768 & io_ldst_dual_r; // @[lsu_bus_buffer.scala 346:35]
+  wire  obuf_merge_en = _T_1767 | _T_1769; // @[lsu_bus_buffer.scala 345:250]
+  wire  _T_1537 = obuf_merge_en & obuf_byteen1_in[0]; // @[lsu_bus_buffer.scala 338:80]
+  wire  _T_1541 = obuf_merge_en & obuf_byteen1_in[1]; // @[lsu_bus_buffer.scala 338:80]
+  wire  _T_1545 = obuf_merge_en & obuf_byteen1_in[2]; // @[lsu_bus_buffer.scala 338:80]
+  wire  _T_1549 = obuf_merge_en & obuf_byteen1_in[3]; // @[lsu_bus_buffer.scala 338:80]
+  wire  _T_1553 = obuf_merge_en & obuf_byteen1_in[4]; // @[lsu_bus_buffer.scala 338:80]
+  wire  _T_1557 = obuf_merge_en & obuf_byteen1_in[5]; // @[lsu_bus_buffer.scala 338:80]
+  wire  _T_1561 = obuf_merge_en & obuf_byteen1_in[6]; // @[lsu_bus_buffer.scala 338:80]
+  wire  _T_1565 = obuf_merge_en & obuf_byteen1_in[7]; // @[lsu_bus_buffer.scala 338:80]
+  wire [7:0] _T_1577 = _T_1537 ? obuf_data1_in[7:0] : obuf_data0_in[7:0]; // @[lsu_bus_buffer.scala 339:44]
+  wire [7:0] _T_1582 = _T_1541 ? obuf_data1_in[15:8] : obuf_data0_in[15:8]; // @[lsu_bus_buffer.scala 339:44]
+  wire [7:0] _T_1587 = _T_1545 ? obuf_data1_in[23:16] : obuf_data0_in[23:16]; // @[lsu_bus_buffer.scala 339:44]
+  wire [7:0] _T_1592 = _T_1549 ? obuf_data1_in[31:24] : obuf_data0_in[31:24]; // @[lsu_bus_buffer.scala 339:44]
+  wire [7:0] _T_1597 = _T_1553 ? obuf_data1_in[39:32] : obuf_data0_in[39:32]; // @[lsu_bus_buffer.scala 339:44]
+  wire [7:0] _T_1602 = _T_1557 ? obuf_data1_in[47:40] : obuf_data0_in[47:40]; // @[lsu_bus_buffer.scala 339:44]
+  wire [7:0] _T_1607 = _T_1561 ? obuf_data1_in[55:48] : obuf_data0_in[55:48]; // @[lsu_bus_buffer.scala 339:44]
+  wire [7:0] _T_1612 = _T_1565 ? obuf_data1_in[63:56] : obuf_data0_in[63:56]; // @[lsu_bus_buffer.scala 339:44]
+  wire [63:0] obuf_data_in = {_T_1612,_T_1607,_T_1602,_T_1597,_T_1592,_T_1587,_T_1582,_T_1577}; // @[Cat.scala 29:58]
   wire  _T_1771 = obuf_wr_en | obuf_valid; // @[lsu_bus_buffer.scala 348:58]
   wire  _T_1772 = ~obuf_rst; // @[lsu_bus_buffer.scala 348:93]
-  reg [1:0] obuf_sz; // @[Reg.scala 27:20]
-  reg [7:0] obuf_byteen; // @[Reg.scala 27:20]
-  reg [63:0] obuf_data; // @[lib.scala 374:16]
-  wire  _T_1785 = buf_state_0 == 3'h0; // @[lsu_bus_buffer.scala 366:65]
-  wire  _T_1786 = ibuf_tag == 2'h0; // @[lsu_bus_buffer.scala 367:30]
-  wire  _T_1787 = ibuf_valid & _T_1786; // @[lsu_bus_buffer.scala 367:19]
-  wire  _T_1788 = WrPtr0_r == 2'h0; // @[lsu_bus_buffer.scala 368:18]
-  wire  _T_1789 = WrPtr1_r == 2'h0; // @[lsu_bus_buffer.scala 368:57]
-  wire  _T_1790 = io_ldst_dual_r & _T_1789; // @[lsu_bus_buffer.scala 368:45]
-  wire  _T_1791 = _T_1788 | _T_1790; // @[lsu_bus_buffer.scala 368:27]
-  wire  _T_1792 = io_lsu_busreq_r & _T_1791; // @[lsu_bus_buffer.scala 367:58]
-  wire  _T_1793 = _T_1787 | _T_1792; // @[lsu_bus_buffer.scala 367:39]
-  wire  _T_1794 = ~_T_1793; // @[lsu_bus_buffer.scala 367:5]
-  wire  _T_1795 = _T_1785 & _T_1794; // @[lsu_bus_buffer.scala 366:76]
-  wire  _T_1796 = buf_state_1 == 3'h0; // @[lsu_bus_buffer.scala 366:65]
-  wire  _T_1797 = ibuf_tag == 2'h1; // @[lsu_bus_buffer.scala 367:30]
-  wire  _T_1798 = ibuf_valid & _T_1797; // @[lsu_bus_buffer.scala 367:19]
-  wire  _T_1799 = WrPtr0_r == 2'h1; // @[lsu_bus_buffer.scala 368:18]
-  wire  _T_1800 = WrPtr1_r == 2'h1; // @[lsu_bus_buffer.scala 368:57]
-  wire  _T_1801 = io_ldst_dual_r & _T_1800; // @[lsu_bus_buffer.scala 368:45]
-  wire  _T_1802 = _T_1799 | _T_1801; // @[lsu_bus_buffer.scala 368:27]
-  wire  _T_1803 = io_lsu_busreq_r & _T_1802; // @[lsu_bus_buffer.scala 367:58]
-  wire  _T_1804 = _T_1798 | _T_1803; // @[lsu_bus_buffer.scala 367:39]
-  wire  _T_1805 = ~_T_1804; // @[lsu_bus_buffer.scala 367:5]
-  wire  _T_1806 = _T_1796 & _T_1805; // @[lsu_bus_buffer.scala 366:76]
-  wire  _T_1807 = buf_state_2 == 3'h0; // @[lsu_bus_buffer.scala 366:65]
-  wire  _T_1808 = ibuf_tag == 2'h2; // @[lsu_bus_buffer.scala 367:30]
-  wire  _T_1809 = ibuf_valid & _T_1808; // @[lsu_bus_buffer.scala 367:19]
-  wire  _T_1810 = WrPtr0_r == 2'h2; // @[lsu_bus_buffer.scala 368:18]
-  wire  _T_1811 = WrPtr1_r == 2'h2; // @[lsu_bus_buffer.scala 368:57]
-  wire  _T_1812 = io_ldst_dual_r & _T_1811; // @[lsu_bus_buffer.scala 368:45]
-  wire  _T_1813 = _T_1810 | _T_1812; // @[lsu_bus_buffer.scala 368:27]
-  wire  _T_1814 = io_lsu_busreq_r & _T_1813; // @[lsu_bus_buffer.scala 367:58]
-  wire  _T_1815 = _T_1809 | _T_1814; // @[lsu_bus_buffer.scala 367:39]
-  wire  _T_1816 = ~_T_1815; // @[lsu_bus_buffer.scala 367:5]
-  wire  _T_1817 = _T_1807 & _T_1816; // @[lsu_bus_buffer.scala 366:76]
-  wire  _T_1818 = buf_state_3 == 3'h0; // @[lsu_bus_buffer.scala 366:65]
-  wire  _T_1819 = ibuf_tag == 2'h3; // @[lsu_bus_buffer.scala 367:30]
-  wire  _T_1821 = WrPtr0_r == 2'h3; // @[lsu_bus_buffer.scala 368:18]
-  wire  _T_1822 = WrPtr1_r == 2'h3; // @[lsu_bus_buffer.scala 368:57]
-  wire [1:0] _T_1830 = _T_1817 ? 2'h2 : 2'h3; // @[Mux.scala 98:16]
-  wire [1:0] _T_1831 = _T_1806 ? 2'h1 : _T_1830; // @[Mux.scala 98:16]
-  wire [1:0] WrPtr0_m = _T_1795 ? 2'h0 : _T_1831; // @[Mux.scala 98:16]
-  wire  _T_1836 = WrPtr0_m == 2'h0; // @[lsu_bus_buffer.scala 373:33]
-  wire  _T_1837 = io_lsu_busreq_m & _T_1836; // @[lsu_bus_buffer.scala 373:22]
-  wire  _T_1838 = _T_1787 | _T_1837; // @[lsu_bus_buffer.scala 372:112]
-  wire  _T_1844 = _T_1838 | _T_1792; // @[lsu_bus_buffer.scala 373:42]
-  wire  _T_1845 = ~_T_1844; // @[lsu_bus_buffer.scala 372:78]
-  wire  _T_1846 = _T_1785 & _T_1845; // @[lsu_bus_buffer.scala 372:76]
-  wire  _T_1850 = WrPtr0_m == 2'h1; // @[lsu_bus_buffer.scala 373:33]
-  wire  _T_1851 = io_lsu_busreq_m & _T_1850; // @[lsu_bus_buffer.scala 373:22]
-  wire  _T_1852 = _T_1798 | _T_1851; // @[lsu_bus_buffer.scala 372:112]
-  wire  _T_1858 = _T_1852 | _T_1803; // @[lsu_bus_buffer.scala 373:42]
-  wire  _T_1859 = ~_T_1858; // @[lsu_bus_buffer.scala 372:78]
-  wire  _T_1860 = _T_1796 & _T_1859; // @[lsu_bus_buffer.scala 372:76]
-  wire  _T_1864 = WrPtr0_m == 2'h2; // @[lsu_bus_buffer.scala 373:33]
-  wire  _T_1865 = io_lsu_busreq_m & _T_1864; // @[lsu_bus_buffer.scala 373:22]
-  wire  _T_1866 = _T_1809 | _T_1865; // @[lsu_bus_buffer.scala 372:112]
-  wire  _T_1872 = _T_1866 | _T_1814; // @[lsu_bus_buffer.scala 373:42]
-  wire  _T_1873 = ~_T_1872; // @[lsu_bus_buffer.scala 372:78]
-  wire  _T_1874 = _T_1807 & _T_1873; // @[lsu_bus_buffer.scala 372:76]
-  reg [3:0] buf_rspageQ_0; // @[lsu_bus_buffer.scala 509:63]
-  wire  _T_2710 = buf_state_3 == 3'h5; // @[lsu_bus_buffer.scala 416:102]
-  wire  _T_2711 = buf_rspageQ_0[3] & _T_2710; // @[lsu_bus_buffer.scala 416:87]
-  wire  _T_2707 = buf_state_2 == 3'h5; // @[lsu_bus_buffer.scala 416:102]
-  wire  _T_2708 = buf_rspageQ_0[2] & _T_2707; // @[lsu_bus_buffer.scala 416:87]
-  wire  _T_2704 = buf_state_1 == 3'h5; // @[lsu_bus_buffer.scala 416:102]
-  wire  _T_2705 = buf_rspageQ_0[1] & _T_2704; // @[lsu_bus_buffer.scala 416:87]
-  wire  _T_2701 = buf_state_0 == 3'h5; // @[lsu_bus_buffer.scala 416:102]
-  wire  _T_2702 = buf_rspageQ_0[0] & _T_2701; // @[lsu_bus_buffer.scala 416:87]
-  wire [3:0] buf_rsp_pickage_0 = {_T_2711,_T_2708,_T_2705,_T_2702}; // @[Cat.scala 29:58]
-  wire  _T_1965 = |buf_rsp_pickage_0; // @[lsu_bus_buffer.scala 384:65]
-  wire  _T_1966 = ~_T_1965; // @[lsu_bus_buffer.scala 384:44]
-  wire  _T_1968 = _T_1966 & _T_2701; // @[lsu_bus_buffer.scala 384:70]
-  reg [3:0] buf_rspageQ_1; // @[lsu_bus_buffer.scala 509:63]
-  wire  _T_2726 = buf_rspageQ_1[3] & _T_2710; // @[lsu_bus_buffer.scala 416:87]
-  wire  _T_2723 = buf_rspageQ_1[2] & _T_2707; // @[lsu_bus_buffer.scala 416:87]
-  wire  _T_2720 = buf_rspageQ_1[1] & _T_2704; // @[lsu_bus_buffer.scala 416:87]
-  wire  _T_2717 = buf_rspageQ_1[0] & _T_2701; // @[lsu_bus_buffer.scala 416:87]
-  wire [3:0] buf_rsp_pickage_1 = {_T_2726,_T_2723,_T_2720,_T_2717}; // @[Cat.scala 29:58]
-  wire  _T_1969 = |buf_rsp_pickage_1; // @[lsu_bus_buffer.scala 384:65]
-  wire  _T_1970 = ~_T_1969; // @[lsu_bus_buffer.scala 384:44]
-  wire  _T_1972 = _T_1970 & _T_2704; // @[lsu_bus_buffer.scala 384:70]
-  reg [3:0] buf_rspageQ_2; // @[lsu_bus_buffer.scala 509:63]
-  wire  _T_2741 = buf_rspageQ_2[3] & _T_2710; // @[lsu_bus_buffer.scala 416:87]
-  wire  _T_2738 = buf_rspageQ_2[2] & _T_2707; // @[lsu_bus_buffer.scala 416:87]
-  wire  _T_2735 = buf_rspageQ_2[1] & _T_2704; // @[lsu_bus_buffer.scala 416:87]
-  wire  _T_2732 = buf_rspageQ_2[0] & _T_2701; // @[lsu_bus_buffer.scala 416:87]
-  wire [3:0] buf_rsp_pickage_2 = {_T_2741,_T_2738,_T_2735,_T_2732}; // @[Cat.scala 29:58]
-  wire  _T_1973 = |buf_rsp_pickage_2; // @[lsu_bus_buffer.scala 384:65]
-  wire  _T_1974 = ~_T_1973; // @[lsu_bus_buffer.scala 384:44]
-  wire  _T_1976 = _T_1974 & _T_2707; // @[lsu_bus_buffer.scala 384:70]
-  reg [3:0] buf_rspageQ_3; // @[lsu_bus_buffer.scala 509:63]
-  wire  _T_2756 = buf_rspageQ_3[3] & _T_2710; // @[lsu_bus_buffer.scala 416:87]
-  wire  _T_2753 = buf_rspageQ_3[2] & _T_2707; // @[lsu_bus_buffer.scala 416:87]
-  wire  _T_2750 = buf_rspageQ_3[1] & _T_2704; // @[lsu_bus_buffer.scala 416:87]
-  wire  _T_2747 = buf_rspageQ_3[0] & _T_2701; // @[lsu_bus_buffer.scala 416:87]
-  wire [3:0] buf_rsp_pickage_3 = {_T_2756,_T_2753,_T_2750,_T_2747}; // @[Cat.scala 29:58]
-  wire  _T_1977 = |buf_rsp_pickage_3; // @[lsu_bus_buffer.scala 384:65]
-  wire  _T_1978 = ~_T_1977; // @[lsu_bus_buffer.scala 384:44]
-  wire  _T_1980 = _T_1978 & _T_2710; // @[lsu_bus_buffer.scala 384:70]
-  wire [7:0] _T_2036 = {4'h0,_T_1980,_T_1976,_T_1972,_T_1968}; // @[Cat.scala 29:58]
-  wire  _T_2039 = _T_2036[4] | _T_2036[5]; // @[lsu_bus_buffer.scala 388:42]
-  wire  _T_2041 = _T_2039 | _T_2036[6]; // @[lsu_bus_buffer.scala 388:48]
-  wire  _T_2043 = _T_2041 | _T_2036[7]; // @[lsu_bus_buffer.scala 388:54]
-  wire  _T_2046 = _T_2036[2] | _T_2036[3]; // @[lsu_bus_buffer.scala 388:67]
-  wire  _T_2048 = _T_2046 | _T_2036[6]; // @[lsu_bus_buffer.scala 388:73]
-  wire  _T_2050 = _T_2048 | _T_2036[7]; // @[lsu_bus_buffer.scala 388:79]
-  wire  _T_2053 = _T_2036[1] | _T_2036[3]; // @[lsu_bus_buffer.scala 388:92]
-  wire  _T_2055 = _T_2053 | _T_2036[5]; // @[lsu_bus_buffer.scala 388:98]
-  wire  _T_2057 = _T_2055 | _T_2036[7]; // @[lsu_bus_buffer.scala 388:104]
-  wire [2:0] _T_2059 = {_T_2043,_T_2050,_T_2057}; // @[Cat.scala 29:58]
-  wire  _T_3528 = ibuf_byp | io_ldst_dual_r; // @[lsu_bus_buffer.scala 446:77]
-  wire  _T_3529 = ~ibuf_merge_en; // @[lsu_bus_buffer.scala 446:97]
-  wire  _T_3530 = _T_3528 & _T_3529; // @[lsu_bus_buffer.scala 446:95]
-  wire  _T_3531 = 2'h0 == WrPtr0_r; // @[lsu_bus_buffer.scala 446:117]
-  wire  _T_3532 = _T_3530 & _T_3531; // @[lsu_bus_buffer.scala 446:112]
-  wire  _T_3533 = ibuf_byp & io_ldst_dual_r; // @[lsu_bus_buffer.scala 446:144]
-  wire  _T_3534 = 2'h0 == WrPtr1_r; // @[lsu_bus_buffer.scala 446:166]
-  wire  _T_3535 = _T_3533 & _T_3534; // @[lsu_bus_buffer.scala 446:161]
-  wire  _T_3536 = _T_3532 | _T_3535; // @[lsu_bus_buffer.scala 446:132]
-  wire  _T_3537 = _T_853 & _T_3536; // @[lsu_bus_buffer.scala 446:63]
-  wire  _T_3538 = 2'h0 == ibuf_tag; // @[lsu_bus_buffer.scala 446:206]
-  wire  _T_3539 = ibuf_drain_vld & _T_3538; // @[lsu_bus_buffer.scala 446:201]
-  wire  _T_3540 = _T_3537 | _T_3539; // @[lsu_bus_buffer.scala 446:183]
-  wire  bus_rsp_write = io_lsu_axi_b_valid & io_lsu_axi_b_ready; // @[lsu_bus_buffer.scala 568:39]
-  wire  _T_3628 = io_lsu_axi_b_bits_id == 3'h0; // @[lsu_bus_buffer.scala 473:73]
-  wire  _T_3629 = bus_rsp_write & _T_3628; // @[lsu_bus_buffer.scala 473:52]
-  wire  _T_3630 = io_lsu_axi_r_bits_id == 3'h0; // @[lsu_bus_buffer.scala 474:46]
-  reg  _T_4291; // @[Reg.scala 27:20]
-  reg  _T_4289; // @[Reg.scala 27:20]
-  reg  _T_4287; // @[Reg.scala 27:20]
-  reg  _T_4285; // @[Reg.scala 27:20]
-  wire [3:0] buf_ldfwd = {_T_4291,_T_4289,_T_4287,_T_4285}; // @[Cat.scala 29:58]
-  reg [1:0] buf_ldfwdtag_0; // @[Reg.scala 27:20]
-  wire [2:0] _GEN_372 = {{1'd0}, buf_ldfwdtag_0}; // @[lsu_bus_buffer.scala 475:47]
-  wire  _T_3632 = io_lsu_axi_r_bits_id == _GEN_372; // @[lsu_bus_buffer.scala 475:47]
-  wire  _T_3633 = buf_ldfwd[0] & _T_3632; // @[lsu_bus_buffer.scala 475:27]
-  wire  _T_3634 = _T_3630 | _T_3633; // @[lsu_bus_buffer.scala 474:77]
-  wire  _T_3635 = buf_dual_0 & buf_dualhi_0; // @[lsu_bus_buffer.scala 476:26]
-  wire  _T_3637 = ~buf_write[0]; // @[lsu_bus_buffer.scala 476:44]
-  wire  _T_3638 = _T_3635 & _T_3637; // @[lsu_bus_buffer.scala 476:42]
-  wire  _T_3639 = _T_3638 & buf_samedw_0; // @[lsu_bus_buffer.scala 476:58]
+  reg [63:0] obuf_data; // @[Reg.scala 27:20]
+  wire  _T_1792 = buf_state_0 == 3'h0; // @[lsu_bus_buffer.scala 367:65]
+  wire  _T_1793 = ibuf_tag == 2'h0; // @[lsu_bus_buffer.scala 368:30]
+  wire  _T_1794 = ibuf_valid & _T_1793; // @[lsu_bus_buffer.scala 368:19]
+  wire  _T_1795 = WrPtr0_r == 2'h0; // @[lsu_bus_buffer.scala 369:18]
+  wire  _T_1796 = WrPtr1_r == 2'h0; // @[lsu_bus_buffer.scala 369:57]
+  wire  _T_1797 = io_ldst_dual_r & _T_1796; // @[lsu_bus_buffer.scala 369:45]
+  wire  _T_1798 = _T_1795 | _T_1797; // @[lsu_bus_buffer.scala 369:27]
+  wire  _T_1799 = io_lsu_busreq_r & _T_1798; // @[lsu_bus_buffer.scala 368:58]
+  wire  _T_1800 = _T_1794 | _T_1799; // @[lsu_bus_buffer.scala 368:39]
+  wire  _T_1801 = ~_T_1800; // @[lsu_bus_buffer.scala 368:5]
+  wire  _T_1802 = _T_1792 & _T_1801; // @[lsu_bus_buffer.scala 367:76]
+  wire  _T_1803 = buf_state_1 == 3'h0; // @[lsu_bus_buffer.scala 367:65]
+  wire  _T_1804 = ibuf_tag == 2'h1; // @[lsu_bus_buffer.scala 368:30]
+  wire  _T_1805 = ibuf_valid & _T_1804; // @[lsu_bus_buffer.scala 368:19]
+  wire  _T_1806 = WrPtr0_r == 2'h1; // @[lsu_bus_buffer.scala 369:18]
+  wire  _T_1807 = WrPtr1_r == 2'h1; // @[lsu_bus_buffer.scala 369:57]
+  wire  _T_1808 = io_ldst_dual_r & _T_1807; // @[lsu_bus_buffer.scala 369:45]
+  wire  _T_1809 = _T_1806 | _T_1808; // @[lsu_bus_buffer.scala 369:27]
+  wire  _T_1810 = io_lsu_busreq_r & _T_1809; // @[lsu_bus_buffer.scala 368:58]
+  wire  _T_1811 = _T_1805 | _T_1810; // @[lsu_bus_buffer.scala 368:39]
+  wire  _T_1812 = ~_T_1811; // @[lsu_bus_buffer.scala 368:5]
+  wire  _T_1813 = _T_1803 & _T_1812; // @[lsu_bus_buffer.scala 367:76]
+  wire  _T_1814 = buf_state_2 == 3'h0; // @[lsu_bus_buffer.scala 367:65]
+  wire  _T_1815 = ibuf_tag == 2'h2; // @[lsu_bus_buffer.scala 368:30]
+  wire  _T_1816 = ibuf_valid & _T_1815; // @[lsu_bus_buffer.scala 368:19]
+  wire  _T_1817 = WrPtr0_r == 2'h2; // @[lsu_bus_buffer.scala 369:18]
+  wire  _T_1818 = WrPtr1_r == 2'h2; // @[lsu_bus_buffer.scala 369:57]
+  wire  _T_1819 = io_ldst_dual_r & _T_1818; // @[lsu_bus_buffer.scala 369:45]
+  wire  _T_1820 = _T_1817 | _T_1819; // @[lsu_bus_buffer.scala 369:27]
+  wire  _T_1821 = io_lsu_busreq_r & _T_1820; // @[lsu_bus_buffer.scala 368:58]
+  wire  _T_1822 = _T_1816 | _T_1821; // @[lsu_bus_buffer.scala 368:39]
+  wire  _T_1823 = ~_T_1822; // @[lsu_bus_buffer.scala 368:5]
+  wire  _T_1824 = _T_1814 & _T_1823; // @[lsu_bus_buffer.scala 367:76]
+  wire  _T_1825 = buf_state_3 == 3'h0; // @[lsu_bus_buffer.scala 367:65]
+  wire  _T_1826 = ibuf_tag == 2'h3; // @[lsu_bus_buffer.scala 368:30]
+  wire  _T_1828 = WrPtr0_r == 2'h3; // @[lsu_bus_buffer.scala 369:18]
+  wire  _T_1829 = WrPtr1_r == 2'h3; // @[lsu_bus_buffer.scala 369:57]
+  wire [1:0] _T_1837 = _T_1824 ? 2'h2 : 2'h3; // @[Mux.scala 98:16]
+  wire [1:0] _T_1838 = _T_1813 ? 2'h1 : _T_1837; // @[Mux.scala 98:16]
+  wire [1:0] WrPtr0_m = _T_1802 ? 2'h0 : _T_1838; // @[Mux.scala 98:16]
+  wire  _T_1843 = WrPtr0_m == 2'h0; // @[lsu_bus_buffer.scala 374:33]
+  wire  _T_1844 = io_lsu_busreq_m & _T_1843; // @[lsu_bus_buffer.scala 374:22]
+  wire  _T_1845 = _T_1794 | _T_1844; // @[lsu_bus_buffer.scala 373:112]
+  wire  _T_1851 = _T_1845 | _T_1799; // @[lsu_bus_buffer.scala 374:42]
+  wire  _T_1852 = ~_T_1851; // @[lsu_bus_buffer.scala 373:78]
+  wire  _T_1853 = _T_1792 & _T_1852; // @[lsu_bus_buffer.scala 373:76]
+  wire  _T_1857 = WrPtr0_m == 2'h1; // @[lsu_bus_buffer.scala 374:33]
+  wire  _T_1858 = io_lsu_busreq_m & _T_1857; // @[lsu_bus_buffer.scala 374:22]
+  wire  _T_1859 = _T_1805 | _T_1858; // @[lsu_bus_buffer.scala 373:112]
+  wire  _T_1865 = _T_1859 | _T_1810; // @[lsu_bus_buffer.scala 374:42]
+  wire  _T_1866 = ~_T_1865; // @[lsu_bus_buffer.scala 373:78]
+  wire  _T_1867 = _T_1803 & _T_1866; // @[lsu_bus_buffer.scala 373:76]
+  wire  _T_1871 = WrPtr0_m == 2'h2; // @[lsu_bus_buffer.scala 374:33]
+  wire  _T_1872 = io_lsu_busreq_m & _T_1871; // @[lsu_bus_buffer.scala 374:22]
+  wire  _T_1873 = _T_1816 | _T_1872; // @[lsu_bus_buffer.scala 373:112]
+  wire  _T_1879 = _T_1873 | _T_1821; // @[lsu_bus_buffer.scala 374:42]
+  wire  _T_1880 = ~_T_1879; // @[lsu_bus_buffer.scala 373:78]
+  wire  _T_1881 = _T_1814 & _T_1880; // @[lsu_bus_buffer.scala 373:76]
+  reg [3:0] buf_rspageQ_0; // @[lsu_bus_buffer.scala 512:63]
+  wire  _T_2717 = buf_state_3 == 3'h5; // @[lsu_bus_buffer.scala 417:102]
+  wire  _T_2718 = buf_rspageQ_0[3] & _T_2717; // @[lsu_bus_buffer.scala 417:87]
+  wire  _T_2714 = buf_state_2 == 3'h5; // @[lsu_bus_buffer.scala 417:102]
+  wire  _T_2715 = buf_rspageQ_0[2] & _T_2714; // @[lsu_bus_buffer.scala 417:87]
+  wire  _T_2711 = buf_state_1 == 3'h5; // @[lsu_bus_buffer.scala 417:102]
+  wire  _T_2712 = buf_rspageQ_0[1] & _T_2711; // @[lsu_bus_buffer.scala 417:87]
+  wire  _T_2708 = buf_state_0 == 3'h5; // @[lsu_bus_buffer.scala 417:102]
+  wire  _T_2709 = buf_rspageQ_0[0] & _T_2708; // @[lsu_bus_buffer.scala 417:87]
+  wire [3:0] buf_rsp_pickage_0 = {_T_2718,_T_2715,_T_2712,_T_2709}; // @[Cat.scala 29:58]
+  wire  _T_1972 = |buf_rsp_pickage_0; // @[lsu_bus_buffer.scala 385:65]
+  wire  _T_1973 = ~_T_1972; // @[lsu_bus_buffer.scala 385:44]
+  wire  _T_1975 = _T_1973 & _T_2708; // @[lsu_bus_buffer.scala 385:70]
+  reg [3:0] buf_rspageQ_1; // @[lsu_bus_buffer.scala 512:63]
+  wire  _T_2733 = buf_rspageQ_1[3] & _T_2717; // @[lsu_bus_buffer.scala 417:87]
+  wire  _T_2730 = buf_rspageQ_1[2] & _T_2714; // @[lsu_bus_buffer.scala 417:87]
+  wire  _T_2727 = buf_rspageQ_1[1] & _T_2711; // @[lsu_bus_buffer.scala 417:87]
+  wire  _T_2724 = buf_rspageQ_1[0] & _T_2708; // @[lsu_bus_buffer.scala 417:87]
+  wire [3:0] buf_rsp_pickage_1 = {_T_2733,_T_2730,_T_2727,_T_2724}; // @[Cat.scala 29:58]
+  wire  _T_1976 = |buf_rsp_pickage_1; // @[lsu_bus_buffer.scala 385:65]
+  wire  _T_1977 = ~_T_1976; // @[lsu_bus_buffer.scala 385:44]
+  wire  _T_1979 = _T_1977 & _T_2711; // @[lsu_bus_buffer.scala 385:70]
+  reg [3:0] buf_rspageQ_2; // @[lsu_bus_buffer.scala 512:63]
+  wire  _T_2748 = buf_rspageQ_2[3] & _T_2717; // @[lsu_bus_buffer.scala 417:87]
+  wire  _T_2745 = buf_rspageQ_2[2] & _T_2714; // @[lsu_bus_buffer.scala 417:87]
+  wire  _T_2742 = buf_rspageQ_2[1] & _T_2711; // @[lsu_bus_buffer.scala 417:87]
+  wire  _T_2739 = buf_rspageQ_2[0] & _T_2708; // @[lsu_bus_buffer.scala 417:87]
+  wire [3:0] buf_rsp_pickage_2 = {_T_2748,_T_2745,_T_2742,_T_2739}; // @[Cat.scala 29:58]
+  wire  _T_1980 = |buf_rsp_pickage_2; // @[lsu_bus_buffer.scala 385:65]
+  wire  _T_1981 = ~_T_1980; // @[lsu_bus_buffer.scala 385:44]
+  wire  _T_1983 = _T_1981 & _T_2714; // @[lsu_bus_buffer.scala 385:70]
+  reg [3:0] buf_rspageQ_3; // @[lsu_bus_buffer.scala 512:63]
+  wire  _T_2763 = buf_rspageQ_3[3] & _T_2717; // @[lsu_bus_buffer.scala 417:87]
+  wire  _T_2760 = buf_rspageQ_3[2] & _T_2714; // @[lsu_bus_buffer.scala 417:87]
+  wire  _T_2757 = buf_rspageQ_3[1] & _T_2711; // @[lsu_bus_buffer.scala 417:87]
+  wire  _T_2754 = buf_rspageQ_3[0] & _T_2708; // @[lsu_bus_buffer.scala 417:87]
+  wire [3:0] buf_rsp_pickage_3 = {_T_2763,_T_2760,_T_2757,_T_2754}; // @[Cat.scala 29:58]
+  wire  _T_1984 = |buf_rsp_pickage_3; // @[lsu_bus_buffer.scala 385:65]
+  wire  _T_1985 = ~_T_1984; // @[lsu_bus_buffer.scala 385:44]
+  wire  _T_1987 = _T_1985 & _T_2717; // @[lsu_bus_buffer.scala 385:70]
+  wire [7:0] _T_2043 = {4'h0,_T_1987,_T_1983,_T_1979,_T_1975}; // @[Cat.scala 29:58]
+  wire  _T_2046 = _T_2043[4] | _T_2043[5]; // @[lsu_bus_buffer.scala 389:42]
+  wire  _T_2048 = _T_2046 | _T_2043[6]; // @[lsu_bus_buffer.scala 389:48]
+  wire  _T_2050 = _T_2048 | _T_2043[7]; // @[lsu_bus_buffer.scala 389:54]
+  wire  _T_2053 = _T_2043[2] | _T_2043[3]; // @[lsu_bus_buffer.scala 389:67]
+  wire  _T_2055 = _T_2053 | _T_2043[6]; // @[lsu_bus_buffer.scala 389:73]
+  wire  _T_2057 = _T_2055 | _T_2043[7]; // @[lsu_bus_buffer.scala 389:79]
+  wire  _T_2060 = _T_2043[1] | _T_2043[3]; // @[lsu_bus_buffer.scala 389:92]
+  wire  _T_2062 = _T_2060 | _T_2043[5]; // @[lsu_bus_buffer.scala 389:98]
+  wire  _T_2064 = _T_2062 | _T_2043[7]; // @[lsu_bus_buffer.scala 389:104]
+  wire [2:0] _T_2066 = {_T_2050,_T_2057,_T_2064}; // @[Cat.scala 29:58]
+  wire  _T_3535 = ibuf_byp | io_ldst_dual_r; // @[lsu_bus_buffer.scala 443:77]
+  wire  _T_3536 = ~ibuf_merge_en; // @[lsu_bus_buffer.scala 443:97]
+  wire  _T_3537 = _T_3535 & _T_3536; // @[lsu_bus_buffer.scala 443:95]
+  wire  _T_3538 = 2'h0 == WrPtr0_r; // @[lsu_bus_buffer.scala 443:117]
+  wire  _T_3539 = _T_3537 & _T_3538; // @[lsu_bus_buffer.scala 443:112]
+  wire  _T_3540 = ibuf_byp & io_ldst_dual_r; // @[lsu_bus_buffer.scala 443:144]
+  wire  _T_3541 = 2'h0 == WrPtr1_r; // @[lsu_bus_buffer.scala 443:166]
+  wire  _T_3542 = _T_3540 & _T_3541; // @[lsu_bus_buffer.scala 443:161]
+  wire  _T_3543 = _T_3539 | _T_3542; // @[lsu_bus_buffer.scala 443:132]
+  wire  _T_3544 = _T_853 & _T_3543; // @[lsu_bus_buffer.scala 443:63]
+  wire  _T_3545 = 2'h0 == ibuf_tag; // @[lsu_bus_buffer.scala 443:206]
+  wire  _T_3546 = ibuf_drain_vld & _T_3545; // @[lsu_bus_buffer.scala 443:201]
+  wire  _T_3547 = _T_3544 | _T_3546; // @[lsu_bus_buffer.scala 443:183]
+  wire  bus_rsp_write = io_lsu_axi_b_valid & io_lsu_axi_b_ready; // @[lsu_bus_buffer.scala 570:39]
+  wire  _T_3636 = io_lsu_axi_b_bits_id == 3'h0; // @[lsu_bus_buffer.scala 473:73]
+  wire  _T_3637 = bus_rsp_write & _T_3636; // @[lsu_bus_buffer.scala 473:52]
+  reg  _T_4302; // @[Reg.scala 27:20]
+  reg  _T_4300; // @[Reg.scala 27:20]
+  reg  _T_4298; // @[Reg.scala 27:20]
+  reg  _T_4296; // @[Reg.scala 27:20]
+  wire [3:0] buf_ldfwd = {_T_4302,_T_4300,_T_4298,_T_4296}; // @[Cat.scala 29:58]
+  wire  _T_3641 = buf_ldfwd[0] & _T_1349; // @[lsu_bus_buffer.scala 475:27]
+  wire  _T_3642 = _T_1349 | _T_3641; // @[lsu_bus_buffer.scala 474:77]
+  wire  _T_3643 = buf_dual_0 & buf_dualhi_0; // @[lsu_bus_buffer.scala 476:26]
+  wire  _T_3645 = ~buf_write[0]; // @[lsu_bus_buffer.scala 476:44]
+  wire  _T_3646 = _T_3643 & _T_3645; // @[lsu_bus_buffer.scala 476:42]
+  wire  _T_3647 = _T_3646 & buf_samedw_0; // @[lsu_bus_buffer.scala 476:58]
   reg [1:0] buf_dualtag_0; // @[Reg.scala 27:20]
-  wire [2:0] _GEN_373 = {{1'd0}, buf_dualtag_0}; // @[lsu_bus_buffer.scala 476:94]
-  wire  _T_3640 = io_lsu_axi_r_bits_id == _GEN_373; // @[lsu_bus_buffer.scala 476:94]
-  wire  _T_3641 = _T_3639 & _T_3640; // @[lsu_bus_buffer.scala 476:74]
-  wire  _T_3642 = _T_3634 | _T_3641; // @[lsu_bus_buffer.scala 475:71]
-  wire  _T_3643 = bus_rsp_read & _T_3642; // @[lsu_bus_buffer.scala 474:25]
-  wire  _T_3644 = _T_3629 | _T_3643; // @[lsu_bus_buffer.scala 473:105]
-  wire  _GEN_43 = _T_3585 & _T_3644; // @[Conditional.scala 39:67]
-  wire  _GEN_62 = _T_3551 ? 1'h0 : _GEN_43; // @[Conditional.scala 39:67]
-  wire  _GEN_74 = _T_3547 ? 1'h0 : _GEN_62; // @[Conditional.scala 39:67]
-  wire  buf_resp_state_bus_en_0 = _T_3524 ? 1'h0 : _GEN_74; // @[Conditional.scala 40:58]
-  wire [3:0] _T_3679 = buf_ldfwd >> buf_dualtag_0; // @[lsu_bus_buffer.scala 489:21]
-  reg [1:0] buf_ldfwdtag_3; // @[Reg.scala 27:20]
-  reg [1:0] buf_ldfwdtag_2; // @[Reg.scala 27:20]
-  reg [1:0] buf_ldfwdtag_1; // @[Reg.scala 27:20]
-  wire [1:0] _GEN_23 = 2'h1 == buf_dualtag_0 ? buf_ldfwdtag_1 : buf_ldfwdtag_0; // @[lsu_bus_buffer.scala 489:58]
-  wire [1:0] _GEN_24 = 2'h2 == buf_dualtag_0 ? buf_ldfwdtag_2 : _GEN_23; // @[lsu_bus_buffer.scala 489:58]
-  wire [1:0] _GEN_25 = 2'h3 == buf_dualtag_0 ? buf_ldfwdtag_3 : _GEN_24; // @[lsu_bus_buffer.scala 489:58]
-  wire [2:0] _GEN_375 = {{1'd0}, _GEN_25}; // @[lsu_bus_buffer.scala 489:58]
-  wire  _T_3681 = io_lsu_axi_r_bits_id == _GEN_375; // @[lsu_bus_buffer.scala 489:58]
-  wire  _T_3682 = _T_3679[0] & _T_3681; // @[lsu_bus_buffer.scala 489:38]
-  wire  _T_3683 = _T_3640 | _T_3682; // @[lsu_bus_buffer.scala 488:95]
-  wire  _T_3684 = bus_rsp_read & _T_3683; // @[lsu_bus_buffer.scala 488:45]
-  wire  _GEN_37 = _T_3669 & _T_3684; // @[Conditional.scala 39:67]
-  wire  _GEN_44 = _T_3585 ? buf_resp_state_bus_en_0 : _GEN_37; // @[Conditional.scala 39:67]
-  wire  _GEN_54 = _T_3551 ? buf_cmd_state_bus_en_0 : _GEN_44; // @[Conditional.scala 39:67]
-  wire  _GEN_67 = _T_3547 ? 1'h0 : _GEN_54; // @[Conditional.scala 39:67]
-  wire  buf_state_bus_en_0 = _T_3524 ? 1'h0 : _GEN_67; // @[Conditional.scala 40:58]
-  wire  _T_3564 = buf_state_bus_en_0 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 461:49]
-  wire  _T_3565 = _T_3564 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 461:70]
-  wire [1:0] RspPtr = _T_2059[1:0]; // @[lsu_bus_buffer.scala 396:10]
-  wire  _T_3690 = RspPtr == 2'h0; // @[lsu_bus_buffer.scala 495:37]
-  wire  _T_3691 = buf_dualtag_0 == RspPtr; // @[lsu_bus_buffer.scala 495:98]
-  wire  _T_3692 = buf_dual_0 & _T_3691; // @[lsu_bus_buffer.scala 495:80]
-  wire  _T_3693 = _T_3690 | _T_3692; // @[lsu_bus_buffer.scala 495:65]
-  wire  _T_3694 = _T_3693 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 495:112]
-  wire  _GEN_32 = _T_3687 ? _T_3694 : _T_3695; // @[Conditional.scala 39:67]
-  wire  _GEN_38 = _T_3669 ? _T_3565 : _GEN_32; // @[Conditional.scala 39:67]
-  wire  _GEN_45 = _T_3585 ? _T_3565 : _GEN_38; // @[Conditional.scala 39:67]
-  wire  _GEN_55 = _T_3551 ? _T_3565 : _GEN_45; // @[Conditional.scala 39:67]
-  wire  _GEN_65 = _T_3547 ? obuf_rdrsp_pend_en : _GEN_55; // @[Conditional.scala 39:67]
-  wire  buf_state_en_0 = _T_3524 ? _T_3540 : _GEN_65; // @[Conditional.scala 40:58]
-  wire  _T_2061 = _T_1785 & buf_state_en_0; // @[lsu_bus_buffer.scala 408:94]
-  wire  _T_2067 = ibuf_drain_vld & io_lsu_busreq_r; // @[lsu_bus_buffer.scala 410:23]
-  wire  _T_2069 = _T_2067 & _T_3528; // @[lsu_bus_buffer.scala 410:41]
-  wire  _T_2071 = _T_2069 & _T_1788; // @[lsu_bus_buffer.scala 410:71]
-  wire  _T_2073 = _T_2071 & _T_1786; // @[lsu_bus_buffer.scala 410:92]
-  wire  _T_2074 = _T_4455 | _T_2073; // @[lsu_bus_buffer.scala 409:86]
-  wire  _T_2075 = ibuf_byp & io_lsu_busreq_r; // @[lsu_bus_buffer.scala 411:17]
-  wire  _T_2076 = _T_2075 & io_ldst_dual_r; // @[lsu_bus_buffer.scala 411:35]
-  wire  _T_2078 = _T_2076 & _T_1789; // @[lsu_bus_buffer.scala 411:52]
-  wire  _T_2080 = _T_2078 & _T_1788; // @[lsu_bus_buffer.scala 411:73]
-  wire  _T_2081 = _T_2074 | _T_2080; // @[lsu_bus_buffer.scala 410:114]
-  wire  _T_2082 = _T_2061 & _T_2081; // @[lsu_bus_buffer.scala 408:113]
-  wire  _T_2084 = _T_2082 | buf_age_0[0]; // @[lsu_bus_buffer.scala 411:97]
-  wire  _T_2098 = _T_2071 & _T_1797; // @[lsu_bus_buffer.scala 410:92]
-  wire  _T_2099 = _T_4460 | _T_2098; // @[lsu_bus_buffer.scala 409:86]
-  wire  _T_2105 = _T_2078 & _T_1799; // @[lsu_bus_buffer.scala 411:73]
-  wire  _T_2106 = _T_2099 | _T_2105; // @[lsu_bus_buffer.scala 410:114]
-  wire  _T_2107 = _T_2061 & _T_2106; // @[lsu_bus_buffer.scala 408:113]
-  wire  _T_2109 = _T_2107 | buf_age_0[1]; // @[lsu_bus_buffer.scala 411:97]
-  wire  _T_2123 = _T_2071 & _T_1808; // @[lsu_bus_buffer.scala 410:92]
-  wire  _T_2124 = _T_4465 | _T_2123; // @[lsu_bus_buffer.scala 409:86]
-  wire  _T_2130 = _T_2078 & _T_1810; // @[lsu_bus_buffer.scala 411:73]
-  wire  _T_2131 = _T_2124 | _T_2130; // @[lsu_bus_buffer.scala 410:114]
-  wire  _T_2132 = _T_2061 & _T_2131; // @[lsu_bus_buffer.scala 408:113]
-  wire  _T_2134 = _T_2132 | buf_age_0[2]; // @[lsu_bus_buffer.scala 411:97]
-  wire  _T_2148 = _T_2071 & _T_1819; // @[lsu_bus_buffer.scala 410:92]
-  wire  _T_2149 = _T_4470 | _T_2148; // @[lsu_bus_buffer.scala 409:86]
-  wire  _T_2155 = _T_2078 & _T_1821; // @[lsu_bus_buffer.scala 411:73]
-  wire  _T_2156 = _T_2149 | _T_2155; // @[lsu_bus_buffer.scala 410:114]
-  wire  _T_2157 = _T_2061 & _T_2156; // @[lsu_bus_buffer.scala 408:113]
-  wire  _T_2159 = _T_2157 | buf_age_0[3]; // @[lsu_bus_buffer.scala 411:97]
-  wire [2:0] _T_2161 = {_T_2159,_T_2134,_T_2109}; // @[Cat.scala 29:58]
-  wire  _T_3721 = 2'h1 == WrPtr0_r; // @[lsu_bus_buffer.scala 446:117]
-  wire  _T_3722 = _T_3530 & _T_3721; // @[lsu_bus_buffer.scala 446:112]
-  wire  _T_3724 = 2'h1 == WrPtr1_r; // @[lsu_bus_buffer.scala 446:166]
-  wire  _T_3725 = _T_3533 & _T_3724; // @[lsu_bus_buffer.scala 446:161]
-  wire  _T_3726 = _T_3722 | _T_3725; // @[lsu_bus_buffer.scala 446:132]
-  wire  _T_3727 = _T_853 & _T_3726; // @[lsu_bus_buffer.scala 446:63]
-  wire  _T_3728 = 2'h1 == ibuf_tag; // @[lsu_bus_buffer.scala 446:206]
-  wire  _T_3729 = ibuf_drain_vld & _T_3728; // @[lsu_bus_buffer.scala 446:201]
-  wire  _T_3730 = _T_3727 | _T_3729; // @[lsu_bus_buffer.scala 446:183]
-  wire  _T_3818 = io_lsu_axi_b_bits_id == 3'h1; // @[lsu_bus_buffer.scala 473:73]
-  wire  _T_3819 = bus_rsp_write & _T_3818; // @[lsu_bus_buffer.scala 473:52]
-  wire  _T_3820 = io_lsu_axi_r_bits_id == 3'h1; // @[lsu_bus_buffer.scala 474:46]
-  wire [2:0] _GEN_376 = {{1'd0}, buf_ldfwdtag_1}; // @[lsu_bus_buffer.scala 475:47]
-  wire  _T_3822 = io_lsu_axi_r_bits_id == _GEN_376; // @[lsu_bus_buffer.scala 475:47]
-  wire  _T_3823 = buf_ldfwd[1] & _T_3822; // @[lsu_bus_buffer.scala 475:27]
-  wire  _T_3824 = _T_3820 | _T_3823; // @[lsu_bus_buffer.scala 474:77]
-  wire  _T_3825 = buf_dual_1 & buf_dualhi_1; // @[lsu_bus_buffer.scala 476:26]
-  wire  _T_3827 = ~buf_write[1]; // @[lsu_bus_buffer.scala 476:44]
-  wire  _T_3828 = _T_3825 & _T_3827; // @[lsu_bus_buffer.scala 476:42]
-  wire  _T_3829 = _T_3828 & buf_samedw_1; // @[lsu_bus_buffer.scala 476:58]
+  wire [2:0] _GEN_382 = {{1'd0}, buf_dualtag_0}; // @[lsu_bus_buffer.scala 476:94]
+  wire  _T_3648 = io_lsu_axi_r_bits_id == _GEN_382; // @[lsu_bus_buffer.scala 476:94]
+  wire  _T_3649 = _T_3647 & _T_3648; // @[lsu_bus_buffer.scala 476:74]
+  wire  _T_3650 = _T_3642 | _T_3649; // @[lsu_bus_buffer.scala 475:71]
+  wire  _T_3651 = bus_rsp_read & _T_3650; // @[lsu_bus_buffer.scala 474:25]
+  wire  _T_3652 = _T_3637 | _T_3651; // @[lsu_bus_buffer.scala 473:105]
+  wire  _GEN_52 = _T_3592 & _T_3652; // @[Conditional.scala 39:67]
+  wire  _GEN_72 = _T_3558 ? 1'h0 : _GEN_52; // @[Conditional.scala 39:67]
+  wire  _GEN_84 = _T_3554 ? 1'h0 : _GEN_72; // @[Conditional.scala 39:67]
+  wire  buf_resp_state_bus_en_0 = _T_3531 ? 1'h0 : _GEN_84; // @[Conditional.scala 40:58]
+  wire [3:0] _T_3687 = buf_ldfwd >> buf_dualtag_0; // @[lsu_bus_buffer.scala 490:21]
+  wire  _T_3690 = _T_3687[0] & _T_1349; // @[lsu_bus_buffer.scala 490:38]
+  wire  _T_3691 = _T_3648 | _T_3690; // @[lsu_bus_buffer.scala 489:95]
+  wire  _T_3692 = bus_rsp_read & _T_3691; // @[lsu_bus_buffer.scala 489:45]
+  wire  _GEN_46 = _T_3677 & _T_3692; // @[Conditional.scala 39:67]
+  wire  _GEN_53 = _T_3592 ? buf_resp_state_bus_en_0 : _GEN_46; // @[Conditional.scala 39:67]
+  wire  _GEN_63 = _T_3558 ? 1'h0 : _GEN_53; // @[Conditional.scala 39:67]
+  wire  _GEN_77 = _T_3554 ? 1'h0 : _GEN_63; // @[Conditional.scala 39:67]
+  wire  buf_state_bus_en_0 = _T_3531 ? 1'h0 : _GEN_77; // @[Conditional.scala 40:58]
+  wire  _T_3571 = buf_state_bus_en_0 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 460:49]
+  wire  _T_3572 = _T_3571 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 460:70]
+  wire [1:0] RspPtr = _T_2066[1:0]; // @[lsu_bus_buffer.scala 397:10]
+  wire  _T_3698 = RspPtr == 2'h0; // @[lsu_bus_buffer.scala 497:37]
+  wire  _T_3699 = buf_dualtag_0 == RspPtr; // @[lsu_bus_buffer.scala 497:98]
+  wire  _T_3700 = buf_dual_0 & _T_3699; // @[lsu_bus_buffer.scala 497:80]
+  wire  _T_3701 = _T_3698 | _T_3700; // @[lsu_bus_buffer.scala 497:65]
+  wire  _T_3702 = _T_3701 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 497:112]
+  wire  _GEN_41 = _T_3695 ? _T_3702 : _T_3703; // @[Conditional.scala 39:67]
+  wire  _GEN_47 = _T_3677 ? _T_3572 : _GEN_41; // @[Conditional.scala 39:67]
+  wire  _GEN_54 = _T_3592 ? _T_3572 : _GEN_47; // @[Conditional.scala 39:67]
+  wire  _GEN_64 = _T_3558 ? _T_3572 : _GEN_54; // @[Conditional.scala 39:67]
+  wire  _GEN_74 = _T_3554 ? obuf_rdrsp_pend_en : _GEN_64; // @[Conditional.scala 39:67]
+  wire  buf_state_en_0 = _T_3531 ? _T_3547 : _GEN_74; // @[Conditional.scala 40:58]
+  wire  _T_2068 = _T_1792 & buf_state_en_0; // @[lsu_bus_buffer.scala 409:94]
+  wire  _T_2074 = ibuf_drain_vld & io_lsu_busreq_r; // @[lsu_bus_buffer.scala 411:23]
+  wire  _T_2076 = _T_2074 & _T_3535; // @[lsu_bus_buffer.scala 411:41]
+  wire  _T_2078 = _T_2076 & _T_1795; // @[lsu_bus_buffer.scala 411:71]
+  wire  _T_2080 = _T_2078 & _T_1793; // @[lsu_bus_buffer.scala 411:92]
+  wire  _T_2081 = _T_4466 | _T_2080; // @[lsu_bus_buffer.scala 410:86]
+  wire  _T_2082 = ibuf_byp & io_lsu_busreq_r; // @[lsu_bus_buffer.scala 412:17]
+  wire  _T_2083 = _T_2082 & io_ldst_dual_r; // @[lsu_bus_buffer.scala 412:35]
+  wire  _T_2085 = _T_2083 & _T_1796; // @[lsu_bus_buffer.scala 412:52]
+  wire  _T_2087 = _T_2085 & _T_1795; // @[lsu_bus_buffer.scala 412:73]
+  wire  _T_2088 = _T_2081 | _T_2087; // @[lsu_bus_buffer.scala 411:114]
+  wire  _T_2089 = _T_2068 & _T_2088; // @[lsu_bus_buffer.scala 409:113]
+  wire  _T_2091 = _T_2089 | buf_age_0[0]; // @[lsu_bus_buffer.scala 412:97]
+  wire  _T_2105 = _T_2078 & _T_1804; // @[lsu_bus_buffer.scala 411:92]
+  wire  _T_2106 = _T_4471 | _T_2105; // @[lsu_bus_buffer.scala 410:86]
+  wire  _T_2112 = _T_2085 & _T_1806; // @[lsu_bus_buffer.scala 412:73]
+  wire  _T_2113 = _T_2106 | _T_2112; // @[lsu_bus_buffer.scala 411:114]
+  wire  _T_2114 = _T_2068 & _T_2113; // @[lsu_bus_buffer.scala 409:113]
+  wire  _T_2116 = _T_2114 | buf_age_0[1]; // @[lsu_bus_buffer.scala 412:97]
+  wire  _T_2130 = _T_2078 & _T_1815; // @[lsu_bus_buffer.scala 411:92]
+  wire  _T_2131 = _T_4476 | _T_2130; // @[lsu_bus_buffer.scala 410:86]
+  wire  _T_2137 = _T_2085 & _T_1817; // @[lsu_bus_buffer.scala 412:73]
+  wire  _T_2138 = _T_2131 | _T_2137; // @[lsu_bus_buffer.scala 411:114]
+  wire  _T_2139 = _T_2068 & _T_2138; // @[lsu_bus_buffer.scala 409:113]
+  wire  _T_2141 = _T_2139 | buf_age_0[2]; // @[lsu_bus_buffer.scala 412:97]
+  wire  _T_2155 = _T_2078 & _T_1826; // @[lsu_bus_buffer.scala 411:92]
+  wire  _T_2156 = _T_4481 | _T_2155; // @[lsu_bus_buffer.scala 410:86]
+  wire  _T_2162 = _T_2085 & _T_1828; // @[lsu_bus_buffer.scala 412:73]
+  wire  _T_2163 = _T_2156 | _T_2162; // @[lsu_bus_buffer.scala 411:114]
+  wire  _T_2164 = _T_2068 & _T_2163; // @[lsu_bus_buffer.scala 409:113]
+  wire  _T_2166 = _T_2164 | buf_age_0[3]; // @[lsu_bus_buffer.scala 412:97]
+  wire [2:0] _T_2168 = {_T_2166,_T_2141,_T_2116}; // @[Cat.scala 29:58]
+  wire  _T_3729 = 2'h1 == WrPtr0_r; // @[lsu_bus_buffer.scala 443:117]
+  wire  _T_3730 = _T_3537 & _T_3729; // @[lsu_bus_buffer.scala 443:112]
+  wire  _T_3732 = 2'h1 == WrPtr1_r; // @[lsu_bus_buffer.scala 443:166]
+  wire  _T_3733 = _T_3540 & _T_3732; // @[lsu_bus_buffer.scala 443:161]
+  wire  _T_3734 = _T_3730 | _T_3733; // @[lsu_bus_buffer.scala 443:132]
+  wire  _T_3735 = _T_853 & _T_3734; // @[lsu_bus_buffer.scala 443:63]
+  wire  _T_3736 = 2'h1 == ibuf_tag; // @[lsu_bus_buffer.scala 443:206]
+  wire  _T_3737 = ibuf_drain_vld & _T_3736; // @[lsu_bus_buffer.scala 443:201]
+  wire  _T_3738 = _T_3735 | _T_3737; // @[lsu_bus_buffer.scala 443:183]
+  wire  _T_3827 = io_lsu_axi_b_bits_id == 3'h1; // @[lsu_bus_buffer.scala 473:73]
+  wire  _T_3828 = bus_rsp_write & _T_3827; // @[lsu_bus_buffer.scala 473:52]
+  wire  _T_3829 = io_lsu_axi_r_bits_id == 3'h1; // @[lsu_bus_buffer.scala 474:46]
+  wire  _T_3832 = buf_ldfwd[1] & _T_1349; // @[lsu_bus_buffer.scala 475:27]
+  wire  _T_3833 = _T_3829 | _T_3832; // @[lsu_bus_buffer.scala 474:77]
+  wire  _T_3834 = buf_dual_1 & buf_dualhi_1; // @[lsu_bus_buffer.scala 476:26]
+  wire  _T_3836 = ~buf_write[1]; // @[lsu_bus_buffer.scala 476:44]
+  wire  _T_3837 = _T_3834 & _T_3836; // @[lsu_bus_buffer.scala 476:42]
+  wire  _T_3838 = _T_3837 & buf_samedw_1; // @[lsu_bus_buffer.scala 476:58]
   reg [1:0] buf_dualtag_1; // @[Reg.scala 27:20]
-  wire [2:0] _GEN_377 = {{1'd0}, buf_dualtag_1}; // @[lsu_bus_buffer.scala 476:94]
-  wire  _T_3830 = io_lsu_axi_r_bits_id == _GEN_377; // @[lsu_bus_buffer.scala 476:94]
-  wire  _T_3831 = _T_3829 & _T_3830; // @[lsu_bus_buffer.scala 476:74]
-  wire  _T_3832 = _T_3824 | _T_3831; // @[lsu_bus_buffer.scala 475:71]
-  wire  _T_3833 = bus_rsp_read & _T_3832; // @[lsu_bus_buffer.scala 474:25]
-  wire  _T_3834 = _T_3819 | _T_3833; // @[lsu_bus_buffer.scala 473:105]
-  wire  _GEN_120 = _T_3775 & _T_3834; // @[Conditional.scala 39:67]
-  wire  _GEN_139 = _T_3741 ? 1'h0 : _GEN_120; // @[Conditional.scala 39:67]
-  wire  _GEN_151 = _T_3737 ? 1'h0 : _GEN_139; // @[Conditional.scala 39:67]
-  wire  buf_resp_state_bus_en_1 = _T_3714 ? 1'h0 : _GEN_151; // @[Conditional.scala 40:58]
-  wire [3:0] _T_3869 = buf_ldfwd >> buf_dualtag_1; // @[lsu_bus_buffer.scala 489:21]
-  wire [1:0] _GEN_100 = 2'h1 == buf_dualtag_1 ? buf_ldfwdtag_1 : buf_ldfwdtag_0; // @[lsu_bus_buffer.scala 489:58]
-  wire [1:0] _GEN_101 = 2'h2 == buf_dualtag_1 ? buf_ldfwdtag_2 : _GEN_100; // @[lsu_bus_buffer.scala 489:58]
-  wire [1:0] _GEN_102 = 2'h3 == buf_dualtag_1 ? buf_ldfwdtag_3 : _GEN_101; // @[lsu_bus_buffer.scala 489:58]
-  wire [2:0] _GEN_379 = {{1'd0}, _GEN_102}; // @[lsu_bus_buffer.scala 489:58]
-  wire  _T_3871 = io_lsu_axi_r_bits_id == _GEN_379; // @[lsu_bus_buffer.scala 489:58]
-  wire  _T_3872 = _T_3869[0] & _T_3871; // @[lsu_bus_buffer.scala 489:38]
-  wire  _T_3873 = _T_3830 | _T_3872; // @[lsu_bus_buffer.scala 488:95]
-  wire  _T_3874 = bus_rsp_read & _T_3873; // @[lsu_bus_buffer.scala 488:45]
-  wire  _GEN_114 = _T_3859 & _T_3874; // @[Conditional.scala 39:67]
-  wire  _GEN_121 = _T_3775 ? buf_resp_state_bus_en_1 : _GEN_114; // @[Conditional.scala 39:67]
-  wire  _GEN_131 = _T_3741 ? buf_cmd_state_bus_en_1 : _GEN_121; // @[Conditional.scala 39:67]
-  wire  _GEN_144 = _T_3737 ? 1'h0 : _GEN_131; // @[Conditional.scala 39:67]
-  wire  buf_state_bus_en_1 = _T_3714 ? 1'h0 : _GEN_144; // @[Conditional.scala 40:58]
-  wire  _T_3754 = buf_state_bus_en_1 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 461:49]
-  wire  _T_3755 = _T_3754 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 461:70]
-  wire  _T_3880 = RspPtr == 2'h1; // @[lsu_bus_buffer.scala 495:37]
-  wire  _T_3881 = buf_dualtag_1 == RspPtr; // @[lsu_bus_buffer.scala 495:98]
-  wire  _T_3882 = buf_dual_1 & _T_3881; // @[lsu_bus_buffer.scala 495:80]
-  wire  _T_3883 = _T_3880 | _T_3882; // @[lsu_bus_buffer.scala 495:65]
-  wire  _T_3884 = _T_3883 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 495:112]
-  wire  _GEN_109 = _T_3877 ? _T_3884 : _T_3885; // @[Conditional.scala 39:67]
-  wire  _GEN_115 = _T_3859 ? _T_3755 : _GEN_109; // @[Conditional.scala 39:67]
-  wire  _GEN_122 = _T_3775 ? _T_3755 : _GEN_115; // @[Conditional.scala 39:67]
-  wire  _GEN_132 = _T_3741 ? _T_3755 : _GEN_122; // @[Conditional.scala 39:67]
-  wire  _GEN_142 = _T_3737 ? obuf_rdrsp_pend_en : _GEN_132; // @[Conditional.scala 39:67]
-  wire  buf_state_en_1 = _T_3714 ? _T_3730 : _GEN_142; // @[Conditional.scala 40:58]
-  wire  _T_2163 = _T_1796 & buf_state_en_1; // @[lsu_bus_buffer.scala 408:94]
-  wire  _T_2173 = _T_2069 & _T_1799; // @[lsu_bus_buffer.scala 410:71]
-  wire  _T_2175 = _T_2173 & _T_1786; // @[lsu_bus_buffer.scala 410:92]
-  wire  _T_2176 = _T_4455 | _T_2175; // @[lsu_bus_buffer.scala 409:86]
-  wire  _T_2180 = _T_2076 & _T_1800; // @[lsu_bus_buffer.scala 411:52]
-  wire  _T_2182 = _T_2180 & _T_1788; // @[lsu_bus_buffer.scala 411:73]
-  wire  _T_2183 = _T_2176 | _T_2182; // @[lsu_bus_buffer.scala 410:114]
-  wire  _T_2184 = _T_2163 & _T_2183; // @[lsu_bus_buffer.scala 408:113]
-  wire  _T_2186 = _T_2184 | buf_age_1[0]; // @[lsu_bus_buffer.scala 411:97]
-  wire  _T_2200 = _T_2173 & _T_1797; // @[lsu_bus_buffer.scala 410:92]
-  wire  _T_2201 = _T_4460 | _T_2200; // @[lsu_bus_buffer.scala 409:86]
-  wire  _T_2207 = _T_2180 & _T_1799; // @[lsu_bus_buffer.scala 411:73]
-  wire  _T_2208 = _T_2201 | _T_2207; // @[lsu_bus_buffer.scala 410:114]
-  wire  _T_2209 = _T_2163 & _T_2208; // @[lsu_bus_buffer.scala 408:113]
-  wire  _T_2211 = _T_2209 | buf_age_1[1]; // @[lsu_bus_buffer.scala 411:97]
-  wire  _T_2225 = _T_2173 & _T_1808; // @[lsu_bus_buffer.scala 410:92]
-  wire  _T_2226 = _T_4465 | _T_2225; // @[lsu_bus_buffer.scala 409:86]
-  wire  _T_2232 = _T_2180 & _T_1810; // @[lsu_bus_buffer.scala 411:73]
-  wire  _T_2233 = _T_2226 | _T_2232; // @[lsu_bus_buffer.scala 410:114]
-  wire  _T_2234 = _T_2163 & _T_2233; // @[lsu_bus_buffer.scala 408:113]
-  wire  _T_2236 = _T_2234 | buf_age_1[2]; // @[lsu_bus_buffer.scala 411:97]
-  wire  _T_2250 = _T_2173 & _T_1819; // @[lsu_bus_buffer.scala 410:92]
-  wire  _T_2251 = _T_4470 | _T_2250; // @[lsu_bus_buffer.scala 409:86]
-  wire  _T_2257 = _T_2180 & _T_1821; // @[lsu_bus_buffer.scala 411:73]
-  wire  _T_2258 = _T_2251 | _T_2257; // @[lsu_bus_buffer.scala 410:114]
-  wire  _T_2259 = _T_2163 & _T_2258; // @[lsu_bus_buffer.scala 408:113]
-  wire  _T_2261 = _T_2259 | buf_age_1[3]; // @[lsu_bus_buffer.scala 411:97]
-  wire [2:0] _T_2263 = {_T_2261,_T_2236,_T_2211}; // @[Cat.scala 29:58]
-  wire  _T_3911 = 2'h2 == WrPtr0_r; // @[lsu_bus_buffer.scala 446:117]
-  wire  _T_3912 = _T_3530 & _T_3911; // @[lsu_bus_buffer.scala 446:112]
-  wire  _T_3914 = 2'h2 == WrPtr1_r; // @[lsu_bus_buffer.scala 446:166]
-  wire  _T_3915 = _T_3533 & _T_3914; // @[lsu_bus_buffer.scala 446:161]
-  wire  _T_3916 = _T_3912 | _T_3915; // @[lsu_bus_buffer.scala 446:132]
-  wire  _T_3917 = _T_853 & _T_3916; // @[lsu_bus_buffer.scala 446:63]
-  wire  _T_3918 = 2'h2 == ibuf_tag; // @[lsu_bus_buffer.scala 446:206]
-  wire  _T_3919 = ibuf_drain_vld & _T_3918; // @[lsu_bus_buffer.scala 446:201]
-  wire  _T_3920 = _T_3917 | _T_3919; // @[lsu_bus_buffer.scala 446:183]
-  wire  _T_4008 = io_lsu_axi_b_bits_id == 3'h2; // @[lsu_bus_buffer.scala 473:73]
-  wire  _T_4009 = bus_rsp_write & _T_4008; // @[lsu_bus_buffer.scala 473:52]
-  wire  _T_4010 = io_lsu_axi_r_bits_id == 3'h2; // @[lsu_bus_buffer.scala 474:46]
-  wire [2:0] _GEN_380 = {{1'd0}, buf_ldfwdtag_2}; // @[lsu_bus_buffer.scala 475:47]
-  wire  _T_4012 = io_lsu_axi_r_bits_id == _GEN_380; // @[lsu_bus_buffer.scala 475:47]
-  wire  _T_4013 = buf_ldfwd[2] & _T_4012; // @[lsu_bus_buffer.scala 475:27]
-  wire  _T_4014 = _T_4010 | _T_4013; // @[lsu_bus_buffer.scala 474:77]
-  wire  _T_4015 = buf_dual_2 & buf_dualhi_2; // @[lsu_bus_buffer.scala 476:26]
-  wire  _T_4017 = ~buf_write[2]; // @[lsu_bus_buffer.scala 476:44]
-  wire  _T_4018 = _T_4015 & _T_4017; // @[lsu_bus_buffer.scala 476:42]
-  wire  _T_4019 = _T_4018 & buf_samedw_2; // @[lsu_bus_buffer.scala 476:58]
+  wire [2:0] _GEN_384 = {{1'd0}, buf_dualtag_1}; // @[lsu_bus_buffer.scala 476:94]
+  wire  _T_3839 = io_lsu_axi_r_bits_id == _GEN_384; // @[lsu_bus_buffer.scala 476:94]
+  wire  _T_3840 = _T_3838 & _T_3839; // @[lsu_bus_buffer.scala 476:74]
+  wire  _T_3841 = _T_3833 | _T_3840; // @[lsu_bus_buffer.scala 475:71]
+  wire  _T_3842 = bus_rsp_read & _T_3841; // @[lsu_bus_buffer.scala 474:25]
+  wire  _T_3843 = _T_3828 | _T_3842; // @[lsu_bus_buffer.scala 473:105]
+  wire  _GEN_128 = _T_3783 & _T_3843; // @[Conditional.scala 39:67]
+  wire  _GEN_148 = _T_3749 ? 1'h0 : _GEN_128; // @[Conditional.scala 39:67]
+  wire  _GEN_160 = _T_3745 ? 1'h0 : _GEN_148; // @[Conditional.scala 39:67]
+  wire  buf_resp_state_bus_en_1 = _T_3722 ? 1'h0 : _GEN_160; // @[Conditional.scala 40:58]
+  wire [3:0] _T_3878 = buf_ldfwd >> buf_dualtag_1; // @[lsu_bus_buffer.scala 490:21]
+  wire  _T_3881 = _T_3878[0] & _T_1349; // @[lsu_bus_buffer.scala 490:38]
+  wire  _T_3882 = _T_3839 | _T_3881; // @[lsu_bus_buffer.scala 489:95]
+  wire  _T_3883 = bus_rsp_read & _T_3882; // @[lsu_bus_buffer.scala 489:45]
+  wire  _GEN_122 = _T_3868 & _T_3883; // @[Conditional.scala 39:67]
+  wire  _GEN_129 = _T_3783 ? buf_resp_state_bus_en_1 : _GEN_122; // @[Conditional.scala 39:67]
+  wire  _GEN_139 = _T_3749 ? 1'h0 : _GEN_129; // @[Conditional.scala 39:67]
+  wire  _GEN_153 = _T_3745 ? 1'h0 : _GEN_139; // @[Conditional.scala 39:67]
+  wire  buf_state_bus_en_1 = _T_3722 ? 1'h0 : _GEN_153; // @[Conditional.scala 40:58]
+  wire  _T_3762 = buf_state_bus_en_1 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 460:49]
+  wire  _T_3763 = _T_3762 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 460:70]
+  wire  _T_3889 = RspPtr == 2'h1; // @[lsu_bus_buffer.scala 497:37]
+  wire  _T_3890 = buf_dualtag_1 == RspPtr; // @[lsu_bus_buffer.scala 497:98]
+  wire  _T_3891 = buf_dual_1 & _T_3890; // @[lsu_bus_buffer.scala 497:80]
+  wire  _T_3892 = _T_3889 | _T_3891; // @[lsu_bus_buffer.scala 497:65]
+  wire  _T_3893 = _T_3892 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 497:112]
+  wire  _GEN_117 = _T_3886 ? _T_3893 : _T_3894; // @[Conditional.scala 39:67]
+  wire  _GEN_123 = _T_3868 ? _T_3763 : _GEN_117; // @[Conditional.scala 39:67]
+  wire  _GEN_130 = _T_3783 ? _T_3763 : _GEN_123; // @[Conditional.scala 39:67]
+  wire  _GEN_140 = _T_3749 ? _T_3763 : _GEN_130; // @[Conditional.scala 39:67]
+  wire  _GEN_150 = _T_3745 ? obuf_rdrsp_pend_en : _GEN_140; // @[Conditional.scala 39:67]
+  wire  buf_state_en_1 = _T_3722 ? _T_3738 : _GEN_150; // @[Conditional.scala 40:58]
+  wire  _T_2170 = _T_1803 & buf_state_en_1; // @[lsu_bus_buffer.scala 409:94]
+  wire  _T_2180 = _T_2076 & _T_1806; // @[lsu_bus_buffer.scala 411:71]
+  wire  _T_2182 = _T_2180 & _T_1793; // @[lsu_bus_buffer.scala 411:92]
+  wire  _T_2183 = _T_4466 | _T_2182; // @[lsu_bus_buffer.scala 410:86]
+  wire  _T_2187 = _T_2083 & _T_1807; // @[lsu_bus_buffer.scala 412:52]
+  wire  _T_2189 = _T_2187 & _T_1795; // @[lsu_bus_buffer.scala 412:73]
+  wire  _T_2190 = _T_2183 | _T_2189; // @[lsu_bus_buffer.scala 411:114]
+  wire  _T_2191 = _T_2170 & _T_2190; // @[lsu_bus_buffer.scala 409:113]
+  wire  _T_2193 = _T_2191 | buf_age_1[0]; // @[lsu_bus_buffer.scala 412:97]
+  wire  _T_2207 = _T_2180 & _T_1804; // @[lsu_bus_buffer.scala 411:92]
+  wire  _T_2208 = _T_4471 | _T_2207; // @[lsu_bus_buffer.scala 410:86]
+  wire  _T_2214 = _T_2187 & _T_1806; // @[lsu_bus_buffer.scala 412:73]
+  wire  _T_2215 = _T_2208 | _T_2214; // @[lsu_bus_buffer.scala 411:114]
+  wire  _T_2216 = _T_2170 & _T_2215; // @[lsu_bus_buffer.scala 409:113]
+  wire  _T_2218 = _T_2216 | buf_age_1[1]; // @[lsu_bus_buffer.scala 412:97]
+  wire  _T_2232 = _T_2180 & _T_1815; // @[lsu_bus_buffer.scala 411:92]
+  wire  _T_2233 = _T_4476 | _T_2232; // @[lsu_bus_buffer.scala 410:86]
+  wire  _T_2239 = _T_2187 & _T_1817; // @[lsu_bus_buffer.scala 412:73]
+  wire  _T_2240 = _T_2233 | _T_2239; // @[lsu_bus_buffer.scala 411:114]
+  wire  _T_2241 = _T_2170 & _T_2240; // @[lsu_bus_buffer.scala 409:113]
+  wire  _T_2243 = _T_2241 | buf_age_1[2]; // @[lsu_bus_buffer.scala 412:97]
+  wire  _T_2257 = _T_2180 & _T_1826; // @[lsu_bus_buffer.scala 411:92]
+  wire  _T_2258 = _T_4481 | _T_2257; // @[lsu_bus_buffer.scala 410:86]
+  wire  _T_2264 = _T_2187 & _T_1828; // @[lsu_bus_buffer.scala 412:73]
+  wire  _T_2265 = _T_2258 | _T_2264; // @[lsu_bus_buffer.scala 411:114]
+  wire  _T_2266 = _T_2170 & _T_2265; // @[lsu_bus_buffer.scala 409:113]
+  wire  _T_2268 = _T_2266 | buf_age_1[3]; // @[lsu_bus_buffer.scala 412:97]
+  wire [2:0] _T_2270 = {_T_2268,_T_2243,_T_2218}; // @[Cat.scala 29:58]
+  wire  _T_3920 = 2'h2 == WrPtr0_r; // @[lsu_bus_buffer.scala 443:117]
+  wire  _T_3921 = _T_3537 & _T_3920; // @[lsu_bus_buffer.scala 443:112]
+  wire  _T_3923 = 2'h2 == WrPtr1_r; // @[lsu_bus_buffer.scala 443:166]
+  wire  _T_3924 = _T_3540 & _T_3923; // @[lsu_bus_buffer.scala 443:161]
+  wire  _T_3925 = _T_3921 | _T_3924; // @[lsu_bus_buffer.scala 443:132]
+  wire  _T_3926 = _T_853 & _T_3925; // @[lsu_bus_buffer.scala 443:63]
+  wire  _T_3927 = 2'h2 == ibuf_tag; // @[lsu_bus_buffer.scala 443:206]
+  wire  _T_3928 = ibuf_drain_vld & _T_3927; // @[lsu_bus_buffer.scala 443:201]
+  wire  _T_3929 = _T_3926 | _T_3928; // @[lsu_bus_buffer.scala 443:183]
+  wire  _T_4018 = io_lsu_axi_b_bits_id == 3'h2; // @[lsu_bus_buffer.scala 473:73]
+  wire  _T_4019 = bus_rsp_write & _T_4018; // @[lsu_bus_buffer.scala 473:52]
+  wire  _T_4020 = io_lsu_axi_r_bits_id == 3'h2; // @[lsu_bus_buffer.scala 474:46]
+  wire  _T_4023 = buf_ldfwd[2] & _T_1349; // @[lsu_bus_buffer.scala 475:27]
+  wire  _T_4024 = _T_4020 | _T_4023; // @[lsu_bus_buffer.scala 474:77]
+  wire  _T_4025 = buf_dual_2 & buf_dualhi_2; // @[lsu_bus_buffer.scala 476:26]
+  wire  _T_4027 = ~buf_write[2]; // @[lsu_bus_buffer.scala 476:44]
+  wire  _T_4028 = _T_4025 & _T_4027; // @[lsu_bus_buffer.scala 476:42]
+  wire  _T_4029 = _T_4028 & buf_samedw_2; // @[lsu_bus_buffer.scala 476:58]
   reg [1:0] buf_dualtag_2; // @[Reg.scala 27:20]
-  wire [2:0] _GEN_381 = {{1'd0}, buf_dualtag_2}; // @[lsu_bus_buffer.scala 476:94]
-  wire  _T_4020 = io_lsu_axi_r_bits_id == _GEN_381; // @[lsu_bus_buffer.scala 476:94]
-  wire  _T_4021 = _T_4019 & _T_4020; // @[lsu_bus_buffer.scala 476:74]
-  wire  _T_4022 = _T_4014 | _T_4021; // @[lsu_bus_buffer.scala 475:71]
-  wire  _T_4023 = bus_rsp_read & _T_4022; // @[lsu_bus_buffer.scala 474:25]
-  wire  _T_4024 = _T_4009 | _T_4023; // @[lsu_bus_buffer.scala 473:105]
-  wire  _GEN_197 = _T_3965 & _T_4024; // @[Conditional.scala 39:67]
-  wire  _GEN_216 = _T_3931 ? 1'h0 : _GEN_197; // @[Conditional.scala 39:67]
-  wire  _GEN_228 = _T_3927 ? 1'h0 : _GEN_216; // @[Conditional.scala 39:67]
-  wire  buf_resp_state_bus_en_2 = _T_3904 ? 1'h0 : _GEN_228; // @[Conditional.scala 40:58]
-  wire [3:0] _T_4059 = buf_ldfwd >> buf_dualtag_2; // @[lsu_bus_buffer.scala 489:21]
-  wire [1:0] _GEN_177 = 2'h1 == buf_dualtag_2 ? buf_ldfwdtag_1 : buf_ldfwdtag_0; // @[lsu_bus_buffer.scala 489:58]
-  wire [1:0] _GEN_178 = 2'h2 == buf_dualtag_2 ? buf_ldfwdtag_2 : _GEN_177; // @[lsu_bus_buffer.scala 489:58]
-  wire [1:0] _GEN_179 = 2'h3 == buf_dualtag_2 ? buf_ldfwdtag_3 : _GEN_178; // @[lsu_bus_buffer.scala 489:58]
-  wire [2:0] _GEN_383 = {{1'd0}, _GEN_179}; // @[lsu_bus_buffer.scala 489:58]
-  wire  _T_4061 = io_lsu_axi_r_bits_id == _GEN_383; // @[lsu_bus_buffer.scala 489:58]
-  wire  _T_4062 = _T_4059[0] & _T_4061; // @[lsu_bus_buffer.scala 489:38]
-  wire  _T_4063 = _T_4020 | _T_4062; // @[lsu_bus_buffer.scala 488:95]
-  wire  _T_4064 = bus_rsp_read & _T_4063; // @[lsu_bus_buffer.scala 488:45]
-  wire  _GEN_191 = _T_4049 & _T_4064; // @[Conditional.scala 39:67]
-  wire  _GEN_198 = _T_3965 ? buf_resp_state_bus_en_2 : _GEN_191; // @[Conditional.scala 39:67]
-  wire  _GEN_208 = _T_3931 ? buf_cmd_state_bus_en_2 : _GEN_198; // @[Conditional.scala 39:67]
-  wire  _GEN_221 = _T_3927 ? 1'h0 : _GEN_208; // @[Conditional.scala 39:67]
-  wire  buf_state_bus_en_2 = _T_3904 ? 1'h0 : _GEN_221; // @[Conditional.scala 40:58]
-  wire  _T_3944 = buf_state_bus_en_2 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 461:49]
-  wire  _T_3945 = _T_3944 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 461:70]
-  wire  _T_4070 = RspPtr == 2'h2; // @[lsu_bus_buffer.scala 495:37]
-  wire  _T_4071 = buf_dualtag_2 == RspPtr; // @[lsu_bus_buffer.scala 495:98]
-  wire  _T_4072 = buf_dual_2 & _T_4071; // @[lsu_bus_buffer.scala 495:80]
-  wire  _T_4073 = _T_4070 | _T_4072; // @[lsu_bus_buffer.scala 495:65]
-  wire  _T_4074 = _T_4073 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 495:112]
-  wire  _GEN_186 = _T_4067 ? _T_4074 : _T_4075; // @[Conditional.scala 39:67]
-  wire  _GEN_192 = _T_4049 ? _T_3945 : _GEN_186; // @[Conditional.scala 39:67]
-  wire  _GEN_199 = _T_3965 ? _T_3945 : _GEN_192; // @[Conditional.scala 39:67]
-  wire  _GEN_209 = _T_3931 ? _T_3945 : _GEN_199; // @[Conditional.scala 39:67]
-  wire  _GEN_219 = _T_3927 ? obuf_rdrsp_pend_en : _GEN_209; // @[Conditional.scala 39:67]
-  wire  buf_state_en_2 = _T_3904 ? _T_3920 : _GEN_219; // @[Conditional.scala 40:58]
-  wire  _T_2265 = _T_1807 & buf_state_en_2; // @[lsu_bus_buffer.scala 408:94]
-  wire  _T_2275 = _T_2069 & _T_1810; // @[lsu_bus_buffer.scala 410:71]
-  wire  _T_2277 = _T_2275 & _T_1786; // @[lsu_bus_buffer.scala 410:92]
-  wire  _T_2278 = _T_4455 | _T_2277; // @[lsu_bus_buffer.scala 409:86]
-  wire  _T_2282 = _T_2076 & _T_1811; // @[lsu_bus_buffer.scala 411:52]
-  wire  _T_2284 = _T_2282 & _T_1788; // @[lsu_bus_buffer.scala 411:73]
-  wire  _T_2285 = _T_2278 | _T_2284; // @[lsu_bus_buffer.scala 410:114]
-  wire  _T_2286 = _T_2265 & _T_2285; // @[lsu_bus_buffer.scala 408:113]
-  wire  _T_2288 = _T_2286 | buf_age_2[0]; // @[lsu_bus_buffer.scala 411:97]
-  wire  _T_2302 = _T_2275 & _T_1797; // @[lsu_bus_buffer.scala 410:92]
-  wire  _T_2303 = _T_4460 | _T_2302; // @[lsu_bus_buffer.scala 409:86]
-  wire  _T_2309 = _T_2282 & _T_1799; // @[lsu_bus_buffer.scala 411:73]
-  wire  _T_2310 = _T_2303 | _T_2309; // @[lsu_bus_buffer.scala 410:114]
-  wire  _T_2311 = _T_2265 & _T_2310; // @[lsu_bus_buffer.scala 408:113]
-  wire  _T_2313 = _T_2311 | buf_age_2[1]; // @[lsu_bus_buffer.scala 411:97]
-  wire  _T_2327 = _T_2275 & _T_1808; // @[lsu_bus_buffer.scala 410:92]
-  wire  _T_2328 = _T_4465 | _T_2327; // @[lsu_bus_buffer.scala 409:86]
-  wire  _T_2334 = _T_2282 & _T_1810; // @[lsu_bus_buffer.scala 411:73]
-  wire  _T_2335 = _T_2328 | _T_2334; // @[lsu_bus_buffer.scala 410:114]
-  wire  _T_2336 = _T_2265 & _T_2335; // @[lsu_bus_buffer.scala 408:113]
-  wire  _T_2338 = _T_2336 | buf_age_2[2]; // @[lsu_bus_buffer.scala 411:97]
-  wire  _T_2352 = _T_2275 & _T_1819; // @[lsu_bus_buffer.scala 410:92]
-  wire  _T_2353 = _T_4470 | _T_2352; // @[lsu_bus_buffer.scala 409:86]
-  wire  _T_2359 = _T_2282 & _T_1821; // @[lsu_bus_buffer.scala 411:73]
-  wire  _T_2360 = _T_2353 | _T_2359; // @[lsu_bus_buffer.scala 410:114]
-  wire  _T_2361 = _T_2265 & _T_2360; // @[lsu_bus_buffer.scala 408:113]
-  wire  _T_2363 = _T_2361 | buf_age_2[3]; // @[lsu_bus_buffer.scala 411:97]
-  wire [2:0] _T_2365 = {_T_2363,_T_2338,_T_2313}; // @[Cat.scala 29:58]
-  wire  _T_4101 = 2'h3 == WrPtr0_r; // @[lsu_bus_buffer.scala 446:117]
-  wire  _T_4102 = _T_3530 & _T_4101; // @[lsu_bus_buffer.scala 446:112]
-  wire  _T_4104 = 2'h3 == WrPtr1_r; // @[lsu_bus_buffer.scala 446:166]
-  wire  _T_4105 = _T_3533 & _T_4104; // @[lsu_bus_buffer.scala 446:161]
-  wire  _T_4106 = _T_4102 | _T_4105; // @[lsu_bus_buffer.scala 446:132]
-  wire  _T_4107 = _T_853 & _T_4106; // @[lsu_bus_buffer.scala 446:63]
-  wire  _T_4108 = 2'h3 == ibuf_tag; // @[lsu_bus_buffer.scala 446:206]
-  wire  _T_4109 = ibuf_drain_vld & _T_4108; // @[lsu_bus_buffer.scala 446:201]
-  wire  _T_4110 = _T_4107 | _T_4109; // @[lsu_bus_buffer.scala 446:183]
-  wire  _T_4198 = io_lsu_axi_b_bits_id == 3'h3; // @[lsu_bus_buffer.scala 473:73]
-  wire  _T_4199 = bus_rsp_write & _T_4198; // @[lsu_bus_buffer.scala 473:52]
-  wire  _T_4200 = io_lsu_axi_r_bits_id == 3'h3; // @[lsu_bus_buffer.scala 474:46]
-  wire [2:0] _GEN_384 = {{1'd0}, buf_ldfwdtag_3}; // @[lsu_bus_buffer.scala 475:47]
-  wire  _T_4202 = io_lsu_axi_r_bits_id == _GEN_384; // @[lsu_bus_buffer.scala 475:47]
-  wire  _T_4203 = buf_ldfwd[3] & _T_4202; // @[lsu_bus_buffer.scala 475:27]
-  wire  _T_4204 = _T_4200 | _T_4203; // @[lsu_bus_buffer.scala 474:77]
-  wire  _T_4205 = buf_dual_3 & buf_dualhi_3; // @[lsu_bus_buffer.scala 476:26]
-  wire  _T_4207 = ~buf_write[3]; // @[lsu_bus_buffer.scala 476:44]
-  wire  _T_4208 = _T_4205 & _T_4207; // @[lsu_bus_buffer.scala 476:42]
-  wire  _T_4209 = _T_4208 & buf_samedw_3; // @[lsu_bus_buffer.scala 476:58]
+  wire [2:0] _GEN_386 = {{1'd0}, buf_dualtag_2}; // @[lsu_bus_buffer.scala 476:94]
+  wire  _T_4030 = io_lsu_axi_r_bits_id == _GEN_386; // @[lsu_bus_buffer.scala 476:94]
+  wire  _T_4031 = _T_4029 & _T_4030; // @[lsu_bus_buffer.scala 476:74]
+  wire  _T_4032 = _T_4024 | _T_4031; // @[lsu_bus_buffer.scala 475:71]
+  wire  _T_4033 = bus_rsp_read & _T_4032; // @[lsu_bus_buffer.scala 474:25]
+  wire  _T_4034 = _T_4019 | _T_4033; // @[lsu_bus_buffer.scala 473:105]
+  wire  _GEN_204 = _T_3974 & _T_4034; // @[Conditional.scala 39:67]
+  wire  _GEN_224 = _T_3940 ? 1'h0 : _GEN_204; // @[Conditional.scala 39:67]
+  wire  _GEN_236 = _T_3936 ? 1'h0 : _GEN_224; // @[Conditional.scala 39:67]
+  wire  buf_resp_state_bus_en_2 = _T_3913 ? 1'h0 : _GEN_236; // @[Conditional.scala 40:58]
+  wire [3:0] _T_4069 = buf_ldfwd >> buf_dualtag_2; // @[lsu_bus_buffer.scala 490:21]
+  wire  _T_4072 = _T_4069[0] & _T_1349; // @[lsu_bus_buffer.scala 490:38]
+  wire  _T_4073 = _T_4030 | _T_4072; // @[lsu_bus_buffer.scala 489:95]
+  wire  _T_4074 = bus_rsp_read & _T_4073; // @[lsu_bus_buffer.scala 489:45]
+  wire  _GEN_198 = _T_4059 & _T_4074; // @[Conditional.scala 39:67]
+  wire  _GEN_205 = _T_3974 ? buf_resp_state_bus_en_2 : _GEN_198; // @[Conditional.scala 39:67]
+  wire  _GEN_215 = _T_3940 ? 1'h0 : _GEN_205; // @[Conditional.scala 39:67]
+  wire  _GEN_229 = _T_3936 ? 1'h0 : _GEN_215; // @[Conditional.scala 39:67]
+  wire  buf_state_bus_en_2 = _T_3913 ? 1'h0 : _GEN_229; // @[Conditional.scala 40:58]
+  wire  _T_3953 = buf_state_bus_en_2 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 460:49]
+  wire  _T_3954 = _T_3953 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 460:70]
+  wire  _T_4080 = RspPtr == 2'h2; // @[lsu_bus_buffer.scala 497:37]
+  wire  _T_4081 = buf_dualtag_2 == RspPtr; // @[lsu_bus_buffer.scala 497:98]
+  wire  _T_4082 = buf_dual_2 & _T_4081; // @[lsu_bus_buffer.scala 497:80]
+  wire  _T_4083 = _T_4080 | _T_4082; // @[lsu_bus_buffer.scala 497:65]
+  wire  _T_4084 = _T_4083 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 497:112]
+  wire  _GEN_193 = _T_4077 ? _T_4084 : _T_4085; // @[Conditional.scala 39:67]
+  wire  _GEN_199 = _T_4059 ? _T_3954 : _GEN_193; // @[Conditional.scala 39:67]
+  wire  _GEN_206 = _T_3974 ? _T_3954 : _GEN_199; // @[Conditional.scala 39:67]
+  wire  _GEN_216 = _T_3940 ? _T_3954 : _GEN_206; // @[Conditional.scala 39:67]
+  wire  _GEN_226 = _T_3936 ? obuf_rdrsp_pend_en : _GEN_216; // @[Conditional.scala 39:67]
+  wire  buf_state_en_2 = _T_3913 ? _T_3929 : _GEN_226; // @[Conditional.scala 40:58]
+  wire  _T_2272 = _T_1814 & buf_state_en_2; // @[lsu_bus_buffer.scala 409:94]
+  wire  _T_2282 = _T_2076 & _T_1817; // @[lsu_bus_buffer.scala 411:71]
+  wire  _T_2284 = _T_2282 & _T_1793; // @[lsu_bus_buffer.scala 411:92]
+  wire  _T_2285 = _T_4466 | _T_2284; // @[lsu_bus_buffer.scala 410:86]
+  wire  _T_2289 = _T_2083 & _T_1818; // @[lsu_bus_buffer.scala 412:52]
+  wire  _T_2291 = _T_2289 & _T_1795; // @[lsu_bus_buffer.scala 412:73]
+  wire  _T_2292 = _T_2285 | _T_2291; // @[lsu_bus_buffer.scala 411:114]
+  wire  _T_2293 = _T_2272 & _T_2292; // @[lsu_bus_buffer.scala 409:113]
+  wire  _T_2295 = _T_2293 | buf_age_2[0]; // @[lsu_bus_buffer.scala 412:97]
+  wire  _T_2309 = _T_2282 & _T_1804; // @[lsu_bus_buffer.scala 411:92]
+  wire  _T_2310 = _T_4471 | _T_2309; // @[lsu_bus_buffer.scala 410:86]
+  wire  _T_2316 = _T_2289 & _T_1806; // @[lsu_bus_buffer.scala 412:73]
+  wire  _T_2317 = _T_2310 | _T_2316; // @[lsu_bus_buffer.scala 411:114]
+  wire  _T_2318 = _T_2272 & _T_2317; // @[lsu_bus_buffer.scala 409:113]
+  wire  _T_2320 = _T_2318 | buf_age_2[1]; // @[lsu_bus_buffer.scala 412:97]
+  wire  _T_2334 = _T_2282 & _T_1815; // @[lsu_bus_buffer.scala 411:92]
+  wire  _T_2335 = _T_4476 | _T_2334; // @[lsu_bus_buffer.scala 410:86]
+  wire  _T_2341 = _T_2289 & _T_1817; // @[lsu_bus_buffer.scala 412:73]
+  wire  _T_2342 = _T_2335 | _T_2341; // @[lsu_bus_buffer.scala 411:114]
+  wire  _T_2343 = _T_2272 & _T_2342; // @[lsu_bus_buffer.scala 409:113]
+  wire  _T_2345 = _T_2343 | buf_age_2[2]; // @[lsu_bus_buffer.scala 412:97]
+  wire  _T_2359 = _T_2282 & _T_1826; // @[lsu_bus_buffer.scala 411:92]
+  wire  _T_2360 = _T_4481 | _T_2359; // @[lsu_bus_buffer.scala 410:86]
+  wire  _T_2366 = _T_2289 & _T_1828; // @[lsu_bus_buffer.scala 412:73]
+  wire  _T_2367 = _T_2360 | _T_2366; // @[lsu_bus_buffer.scala 411:114]
+  wire  _T_2368 = _T_2272 & _T_2367; // @[lsu_bus_buffer.scala 409:113]
+  wire  _T_2370 = _T_2368 | buf_age_2[3]; // @[lsu_bus_buffer.scala 412:97]
+  wire [2:0] _T_2372 = {_T_2370,_T_2345,_T_2320}; // @[Cat.scala 29:58]
+  wire  _T_4111 = 2'h3 == WrPtr0_r; // @[lsu_bus_buffer.scala 443:117]
+  wire  _T_4112 = _T_3537 & _T_4111; // @[lsu_bus_buffer.scala 443:112]
+  wire  _T_4114 = 2'h3 == WrPtr1_r; // @[lsu_bus_buffer.scala 443:166]
+  wire  _T_4115 = _T_3540 & _T_4114; // @[lsu_bus_buffer.scala 443:161]
+  wire  _T_4116 = _T_4112 | _T_4115; // @[lsu_bus_buffer.scala 443:132]
+  wire  _T_4117 = _T_853 & _T_4116; // @[lsu_bus_buffer.scala 443:63]
+  wire  _T_4118 = 2'h3 == ibuf_tag; // @[lsu_bus_buffer.scala 443:206]
+  wire  _T_4119 = ibuf_drain_vld & _T_4118; // @[lsu_bus_buffer.scala 443:201]
+  wire  _T_4120 = _T_4117 | _T_4119; // @[lsu_bus_buffer.scala 443:183]
+  wire  _T_4209 = io_lsu_axi_b_bits_id == 3'h3; // @[lsu_bus_buffer.scala 473:73]
+  wire  _T_4210 = bus_rsp_write & _T_4209; // @[lsu_bus_buffer.scala 473:52]
+  wire  _T_4211 = io_lsu_axi_r_bits_id == 3'h3; // @[lsu_bus_buffer.scala 474:46]
+  wire  _T_4214 = buf_ldfwd[3] & _T_1349; // @[lsu_bus_buffer.scala 475:27]
+  wire  _T_4215 = _T_4211 | _T_4214; // @[lsu_bus_buffer.scala 474:77]
+  wire  _T_4216 = buf_dual_3 & buf_dualhi_3; // @[lsu_bus_buffer.scala 476:26]
+  wire  _T_4218 = ~buf_write[3]; // @[lsu_bus_buffer.scala 476:44]
+  wire  _T_4219 = _T_4216 & _T_4218; // @[lsu_bus_buffer.scala 476:42]
+  wire  _T_4220 = _T_4219 & buf_samedw_3; // @[lsu_bus_buffer.scala 476:58]
   reg [1:0] buf_dualtag_3; // @[Reg.scala 27:20]
-  wire [2:0] _GEN_385 = {{1'd0}, buf_dualtag_3}; // @[lsu_bus_buffer.scala 476:94]
-  wire  _T_4210 = io_lsu_axi_r_bits_id == _GEN_385; // @[lsu_bus_buffer.scala 476:94]
-  wire  _T_4211 = _T_4209 & _T_4210; // @[lsu_bus_buffer.scala 476:74]
-  wire  _T_4212 = _T_4204 | _T_4211; // @[lsu_bus_buffer.scala 475:71]
-  wire  _T_4213 = bus_rsp_read & _T_4212; // @[lsu_bus_buffer.scala 474:25]
-  wire  _T_4214 = _T_4199 | _T_4213; // @[lsu_bus_buffer.scala 473:105]
-  wire  _GEN_274 = _T_4155 & _T_4214; // @[Conditional.scala 39:67]
-  wire  _GEN_293 = _T_4121 ? 1'h0 : _GEN_274; // @[Conditional.scala 39:67]
-  wire  _GEN_305 = _T_4117 ? 1'h0 : _GEN_293; // @[Conditional.scala 39:67]
-  wire  buf_resp_state_bus_en_3 = _T_4094 ? 1'h0 : _GEN_305; // @[Conditional.scala 40:58]
-  wire [3:0] _T_4249 = buf_ldfwd >> buf_dualtag_3; // @[lsu_bus_buffer.scala 489:21]
-  wire [1:0] _GEN_254 = 2'h1 == buf_dualtag_3 ? buf_ldfwdtag_1 : buf_ldfwdtag_0; // @[lsu_bus_buffer.scala 489:58]
-  wire [1:0] _GEN_255 = 2'h2 == buf_dualtag_3 ? buf_ldfwdtag_2 : _GEN_254; // @[lsu_bus_buffer.scala 489:58]
-  wire [1:0] _GEN_256 = 2'h3 == buf_dualtag_3 ? buf_ldfwdtag_3 : _GEN_255; // @[lsu_bus_buffer.scala 489:58]
-  wire [2:0] _GEN_387 = {{1'd0}, _GEN_256}; // @[lsu_bus_buffer.scala 489:58]
-  wire  _T_4251 = io_lsu_axi_r_bits_id == _GEN_387; // @[lsu_bus_buffer.scala 489:58]
-  wire  _T_4252 = _T_4249[0] & _T_4251; // @[lsu_bus_buffer.scala 489:38]
-  wire  _T_4253 = _T_4210 | _T_4252; // @[lsu_bus_buffer.scala 488:95]
-  wire  _T_4254 = bus_rsp_read & _T_4253; // @[lsu_bus_buffer.scala 488:45]
-  wire  _GEN_268 = _T_4239 & _T_4254; // @[Conditional.scala 39:67]
-  wire  _GEN_275 = _T_4155 ? buf_resp_state_bus_en_3 : _GEN_268; // @[Conditional.scala 39:67]
-  wire  _GEN_285 = _T_4121 ? buf_cmd_state_bus_en_3 : _GEN_275; // @[Conditional.scala 39:67]
-  wire  _GEN_298 = _T_4117 ? 1'h0 : _GEN_285; // @[Conditional.scala 39:67]
-  wire  buf_state_bus_en_3 = _T_4094 ? 1'h0 : _GEN_298; // @[Conditional.scala 40:58]
-  wire  _T_4134 = buf_state_bus_en_3 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 461:49]
-  wire  _T_4135 = _T_4134 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 461:70]
-  wire  _T_4260 = RspPtr == 2'h3; // @[lsu_bus_buffer.scala 495:37]
-  wire  _T_4261 = buf_dualtag_3 == RspPtr; // @[lsu_bus_buffer.scala 495:98]
-  wire  _T_4262 = buf_dual_3 & _T_4261; // @[lsu_bus_buffer.scala 495:80]
-  wire  _T_4263 = _T_4260 | _T_4262; // @[lsu_bus_buffer.scala 495:65]
-  wire  _T_4264 = _T_4263 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 495:112]
-  wire  _GEN_263 = _T_4257 ? _T_4264 : _T_4265; // @[Conditional.scala 39:67]
-  wire  _GEN_269 = _T_4239 ? _T_4135 : _GEN_263; // @[Conditional.scala 39:67]
-  wire  _GEN_276 = _T_4155 ? _T_4135 : _GEN_269; // @[Conditional.scala 39:67]
-  wire  _GEN_286 = _T_4121 ? _T_4135 : _GEN_276; // @[Conditional.scala 39:67]
-  wire  _GEN_296 = _T_4117 ? obuf_rdrsp_pend_en : _GEN_286; // @[Conditional.scala 39:67]
-  wire  buf_state_en_3 = _T_4094 ? _T_4110 : _GEN_296; // @[Conditional.scala 40:58]
-  wire  _T_2367 = _T_1818 & buf_state_en_3; // @[lsu_bus_buffer.scala 408:94]
-  wire  _T_2377 = _T_2069 & _T_1821; // @[lsu_bus_buffer.scala 410:71]
-  wire  _T_2379 = _T_2377 & _T_1786; // @[lsu_bus_buffer.scala 410:92]
-  wire  _T_2380 = _T_4455 | _T_2379; // @[lsu_bus_buffer.scala 409:86]
-  wire  _T_2384 = _T_2076 & _T_1822; // @[lsu_bus_buffer.scala 411:52]
-  wire  _T_2386 = _T_2384 & _T_1788; // @[lsu_bus_buffer.scala 411:73]
-  wire  _T_2387 = _T_2380 | _T_2386; // @[lsu_bus_buffer.scala 410:114]
-  wire  _T_2388 = _T_2367 & _T_2387; // @[lsu_bus_buffer.scala 408:113]
-  wire  _T_2390 = _T_2388 | buf_age_3[0]; // @[lsu_bus_buffer.scala 411:97]
-  wire  _T_2404 = _T_2377 & _T_1797; // @[lsu_bus_buffer.scala 410:92]
-  wire  _T_2405 = _T_4460 | _T_2404; // @[lsu_bus_buffer.scala 409:86]
-  wire  _T_2411 = _T_2384 & _T_1799; // @[lsu_bus_buffer.scala 411:73]
-  wire  _T_2412 = _T_2405 | _T_2411; // @[lsu_bus_buffer.scala 410:114]
-  wire  _T_2413 = _T_2367 & _T_2412; // @[lsu_bus_buffer.scala 408:113]
-  wire  _T_2415 = _T_2413 | buf_age_3[1]; // @[lsu_bus_buffer.scala 411:97]
-  wire  _T_2429 = _T_2377 & _T_1808; // @[lsu_bus_buffer.scala 410:92]
-  wire  _T_2430 = _T_4465 | _T_2429; // @[lsu_bus_buffer.scala 409:86]
-  wire  _T_2436 = _T_2384 & _T_1810; // @[lsu_bus_buffer.scala 411:73]
-  wire  _T_2437 = _T_2430 | _T_2436; // @[lsu_bus_buffer.scala 410:114]
-  wire  _T_2438 = _T_2367 & _T_2437; // @[lsu_bus_buffer.scala 408:113]
-  wire  _T_2440 = _T_2438 | buf_age_3[2]; // @[lsu_bus_buffer.scala 411:97]
-  wire  _T_2454 = _T_2377 & _T_1819; // @[lsu_bus_buffer.scala 410:92]
-  wire  _T_2455 = _T_4470 | _T_2454; // @[lsu_bus_buffer.scala 409:86]
-  wire  _T_2461 = _T_2384 & _T_1821; // @[lsu_bus_buffer.scala 411:73]
-  wire  _T_2462 = _T_2455 | _T_2461; // @[lsu_bus_buffer.scala 410:114]
-  wire  _T_2463 = _T_2367 & _T_2462; // @[lsu_bus_buffer.scala 408:113]
-  wire  _T_2465 = _T_2463 | buf_age_3[3]; // @[lsu_bus_buffer.scala 411:97]
-  wire [2:0] _T_2467 = {_T_2465,_T_2440,_T_2415}; // @[Cat.scala 29:58]
-  wire  _T_2763 = buf_state_0 == 3'h6; // @[lsu_bus_buffer.scala 419:47]
-  wire  _T_2764 = _T_1785 | _T_2763; // @[lsu_bus_buffer.scala 419:32]
-  wire  _T_2765 = ~_T_2764; // @[lsu_bus_buffer.scala 419:6]
-  wire  _T_2773 = _T_2765 | _T_2073; // @[lsu_bus_buffer.scala 419:59]
-  wire  _T_2780 = _T_2773 | _T_2080; // @[lsu_bus_buffer.scala 420:110]
-  wire  _T_2781 = _T_2061 & _T_2780; // @[lsu_bus_buffer.scala 418:112]
-  wire  _T_2785 = buf_state_1 == 3'h6; // @[lsu_bus_buffer.scala 419:47]
-  wire  _T_2786 = _T_1796 | _T_2785; // @[lsu_bus_buffer.scala 419:32]
-  wire  _T_2787 = ~_T_2786; // @[lsu_bus_buffer.scala 419:6]
-  wire  _T_2795 = _T_2787 | _T_2098; // @[lsu_bus_buffer.scala 419:59]
-  wire  _T_2802 = _T_2795 | _T_2105; // @[lsu_bus_buffer.scala 420:110]
-  wire  _T_2803 = _T_2061 & _T_2802; // @[lsu_bus_buffer.scala 418:112]
-  wire  _T_2807 = buf_state_2 == 3'h6; // @[lsu_bus_buffer.scala 419:47]
-  wire  _T_2808 = _T_1807 | _T_2807; // @[lsu_bus_buffer.scala 419:32]
-  wire  _T_2809 = ~_T_2808; // @[lsu_bus_buffer.scala 419:6]
-  wire  _T_2817 = _T_2809 | _T_2123; // @[lsu_bus_buffer.scala 419:59]
-  wire  _T_2824 = _T_2817 | _T_2130; // @[lsu_bus_buffer.scala 420:110]
-  wire  _T_2825 = _T_2061 & _T_2824; // @[lsu_bus_buffer.scala 418:112]
-  wire  _T_2829 = buf_state_3 == 3'h6; // @[lsu_bus_buffer.scala 419:47]
-  wire  _T_2830 = _T_1818 | _T_2829; // @[lsu_bus_buffer.scala 419:32]
-  wire  _T_2831 = ~_T_2830; // @[lsu_bus_buffer.scala 419:6]
-  wire  _T_2839 = _T_2831 | _T_2148; // @[lsu_bus_buffer.scala 419:59]
-  wire  _T_2846 = _T_2839 | _T_2155; // @[lsu_bus_buffer.scala 420:110]
-  wire  _T_2847 = _T_2061 & _T_2846; // @[lsu_bus_buffer.scala 418:112]
-  wire [3:0] buf_rspage_set_0 = {_T_2847,_T_2825,_T_2803,_T_2781}; // @[Cat.scala 29:58]
-  wire  _T_2864 = _T_2765 | _T_2175; // @[lsu_bus_buffer.scala 419:59]
-  wire  _T_2871 = _T_2864 | _T_2182; // @[lsu_bus_buffer.scala 420:110]
-  wire  _T_2872 = _T_2163 & _T_2871; // @[lsu_bus_buffer.scala 418:112]
-  wire  _T_2886 = _T_2787 | _T_2200; // @[lsu_bus_buffer.scala 419:59]
-  wire  _T_2893 = _T_2886 | _T_2207; // @[lsu_bus_buffer.scala 420:110]
-  wire  _T_2894 = _T_2163 & _T_2893; // @[lsu_bus_buffer.scala 418:112]
-  wire  _T_2908 = _T_2809 | _T_2225; // @[lsu_bus_buffer.scala 419:59]
-  wire  _T_2915 = _T_2908 | _T_2232; // @[lsu_bus_buffer.scala 420:110]
-  wire  _T_2916 = _T_2163 & _T_2915; // @[lsu_bus_buffer.scala 418:112]
-  wire  _T_2930 = _T_2831 | _T_2250; // @[lsu_bus_buffer.scala 419:59]
-  wire  _T_2937 = _T_2930 | _T_2257; // @[lsu_bus_buffer.scala 420:110]
-  wire  _T_2938 = _T_2163 & _T_2937; // @[lsu_bus_buffer.scala 418:112]
-  wire [3:0] buf_rspage_set_1 = {_T_2938,_T_2916,_T_2894,_T_2872}; // @[Cat.scala 29:58]
-  wire  _T_2955 = _T_2765 | _T_2277; // @[lsu_bus_buffer.scala 419:59]
-  wire  _T_2962 = _T_2955 | _T_2284; // @[lsu_bus_buffer.scala 420:110]
-  wire  _T_2963 = _T_2265 & _T_2962; // @[lsu_bus_buffer.scala 418:112]
-  wire  _T_2977 = _T_2787 | _T_2302; // @[lsu_bus_buffer.scala 419:59]
-  wire  _T_2984 = _T_2977 | _T_2309; // @[lsu_bus_buffer.scala 420:110]
-  wire  _T_2985 = _T_2265 & _T_2984; // @[lsu_bus_buffer.scala 418:112]
-  wire  _T_2999 = _T_2809 | _T_2327; // @[lsu_bus_buffer.scala 419:59]
-  wire  _T_3006 = _T_2999 | _T_2334; // @[lsu_bus_buffer.scala 420:110]
-  wire  _T_3007 = _T_2265 & _T_3006; // @[lsu_bus_buffer.scala 418:112]
-  wire  _T_3021 = _T_2831 | _T_2352; // @[lsu_bus_buffer.scala 419:59]
-  wire  _T_3028 = _T_3021 | _T_2359; // @[lsu_bus_buffer.scala 420:110]
-  wire  _T_3029 = _T_2265 & _T_3028; // @[lsu_bus_buffer.scala 418:112]
-  wire [3:0] buf_rspage_set_2 = {_T_3029,_T_3007,_T_2985,_T_2963}; // @[Cat.scala 29:58]
-  wire  _T_3046 = _T_2765 | _T_2379; // @[lsu_bus_buffer.scala 419:59]
-  wire  _T_3053 = _T_3046 | _T_2386; // @[lsu_bus_buffer.scala 420:110]
-  wire  _T_3054 = _T_2367 & _T_3053; // @[lsu_bus_buffer.scala 418:112]
-  wire  _T_3068 = _T_2787 | _T_2404; // @[lsu_bus_buffer.scala 419:59]
-  wire  _T_3075 = _T_3068 | _T_2411; // @[lsu_bus_buffer.scala 420:110]
-  wire  _T_3076 = _T_2367 & _T_3075; // @[lsu_bus_buffer.scala 418:112]
-  wire  _T_3090 = _T_2809 | _T_2429; // @[lsu_bus_buffer.scala 419:59]
-  wire  _T_3097 = _T_3090 | _T_2436; // @[lsu_bus_buffer.scala 420:110]
-  wire  _T_3098 = _T_2367 & _T_3097; // @[lsu_bus_buffer.scala 418:112]
-  wire  _T_3112 = _T_2831 | _T_2454; // @[lsu_bus_buffer.scala 419:59]
-  wire  _T_3119 = _T_3112 | _T_2461; // @[lsu_bus_buffer.scala 420:110]
-  wire  _T_3120 = _T_2367 & _T_3119; // @[lsu_bus_buffer.scala 418:112]
-  wire [3:0] buf_rspage_set_3 = {_T_3120,_T_3098,_T_3076,_T_3054}; // @[Cat.scala 29:58]
-  wire  _T_3211 = _T_2829 | _T_1818; // @[lsu_bus_buffer.scala 423:110]
-  wire  _T_3212 = ~_T_3211; // @[lsu_bus_buffer.scala 423:84]
-  wire  _T_3213 = buf_rspageQ_0[3] & _T_3212; // @[lsu_bus_buffer.scala 423:82]
-  wire  _T_3215 = _T_3213 & _T_2587; // @[lsu_bus_buffer.scala 423:145]
-  wire  _T_3203 = _T_2807 | _T_1807; // @[lsu_bus_buffer.scala 423:110]
-  wire  _T_3204 = ~_T_3203; // @[lsu_bus_buffer.scala 423:84]
-  wire  _T_3205 = buf_rspageQ_0[2] & _T_3204; // @[lsu_bus_buffer.scala 423:82]
-  wire  _T_3207 = _T_3205 & _T_2587; // @[lsu_bus_buffer.scala 423:145]
-  wire  _T_3195 = _T_2785 | _T_1796; // @[lsu_bus_buffer.scala 423:110]
-  wire  _T_3196 = ~_T_3195; // @[lsu_bus_buffer.scala 423:84]
-  wire  _T_3197 = buf_rspageQ_0[1] & _T_3196; // @[lsu_bus_buffer.scala 423:82]
-  wire  _T_3199 = _T_3197 & _T_2587; // @[lsu_bus_buffer.scala 423:145]
-  wire  _T_3187 = _T_2763 | _T_1785; // @[lsu_bus_buffer.scala 423:110]
-  wire  _T_3188 = ~_T_3187; // @[lsu_bus_buffer.scala 423:84]
-  wire  _T_3189 = buf_rspageQ_0[0] & _T_3188; // @[lsu_bus_buffer.scala 423:82]
-  wire  _T_3191 = _T_3189 & _T_2587; // @[lsu_bus_buffer.scala 423:145]
-  wire [3:0] buf_rspage_0 = {_T_3215,_T_3207,_T_3199,_T_3191}; // @[Cat.scala 29:58]
-  wire  _T_3126 = buf_rspage_set_0[0] | buf_rspage_0[0]; // @[lsu_bus_buffer.scala 422:88]
-  wire  _T_3129 = buf_rspage_set_0[1] | buf_rspage_0[1]; // @[lsu_bus_buffer.scala 422:88]
-  wire  _T_3132 = buf_rspage_set_0[2] | buf_rspage_0[2]; // @[lsu_bus_buffer.scala 422:88]
-  wire  _T_3135 = buf_rspage_set_0[3] | buf_rspage_0[3]; // @[lsu_bus_buffer.scala 422:88]
-  wire [2:0] _T_3137 = {_T_3135,_T_3132,_T_3129}; // @[Cat.scala 29:58]
-  wire  _T_3248 = buf_rspageQ_1[3] & _T_3212; // @[lsu_bus_buffer.scala 423:82]
-  wire  _T_3250 = _T_3248 & _T_2587; // @[lsu_bus_buffer.scala 423:145]
-  wire  _T_3240 = buf_rspageQ_1[2] & _T_3204; // @[lsu_bus_buffer.scala 423:82]
-  wire  _T_3242 = _T_3240 & _T_2587; // @[lsu_bus_buffer.scala 423:145]
-  wire  _T_3232 = buf_rspageQ_1[1] & _T_3196; // @[lsu_bus_buffer.scala 423:82]
-  wire  _T_3234 = _T_3232 & _T_2587; // @[lsu_bus_buffer.scala 423:145]
-  wire  _T_3224 = buf_rspageQ_1[0] & _T_3188; // @[lsu_bus_buffer.scala 423:82]
-  wire  _T_3226 = _T_3224 & _T_2587; // @[lsu_bus_buffer.scala 423:145]
-  wire [3:0] buf_rspage_1 = {_T_3250,_T_3242,_T_3234,_T_3226}; // @[Cat.scala 29:58]
-  wire  _T_3141 = buf_rspage_set_1[0] | buf_rspage_1[0]; // @[lsu_bus_buffer.scala 422:88]
-  wire  _T_3144 = buf_rspage_set_1[1] | buf_rspage_1[1]; // @[lsu_bus_buffer.scala 422:88]
-  wire  _T_3147 = buf_rspage_set_1[2] | buf_rspage_1[2]; // @[lsu_bus_buffer.scala 422:88]
-  wire  _T_3150 = buf_rspage_set_1[3] | buf_rspage_1[3]; // @[lsu_bus_buffer.scala 422:88]
-  wire [2:0] _T_3152 = {_T_3150,_T_3147,_T_3144}; // @[Cat.scala 29:58]
-  wire  _T_3283 = buf_rspageQ_2[3] & _T_3212; // @[lsu_bus_buffer.scala 423:82]
-  wire  _T_3285 = _T_3283 & _T_2587; // @[lsu_bus_buffer.scala 423:145]
-  wire  _T_3275 = buf_rspageQ_2[2] & _T_3204; // @[lsu_bus_buffer.scala 423:82]
-  wire  _T_3277 = _T_3275 & _T_2587; // @[lsu_bus_buffer.scala 423:145]
-  wire  _T_3267 = buf_rspageQ_2[1] & _T_3196; // @[lsu_bus_buffer.scala 423:82]
-  wire  _T_3269 = _T_3267 & _T_2587; // @[lsu_bus_buffer.scala 423:145]
-  wire  _T_3259 = buf_rspageQ_2[0] & _T_3188; // @[lsu_bus_buffer.scala 423:82]
-  wire  _T_3261 = _T_3259 & _T_2587; // @[lsu_bus_buffer.scala 423:145]
-  wire [3:0] buf_rspage_2 = {_T_3285,_T_3277,_T_3269,_T_3261}; // @[Cat.scala 29:58]
-  wire  _T_3156 = buf_rspage_set_2[0] | buf_rspage_2[0]; // @[lsu_bus_buffer.scala 422:88]
-  wire  _T_3159 = buf_rspage_set_2[1] | buf_rspage_2[1]; // @[lsu_bus_buffer.scala 422:88]
-  wire  _T_3162 = buf_rspage_set_2[2] | buf_rspage_2[2]; // @[lsu_bus_buffer.scala 422:88]
-  wire  _T_3165 = buf_rspage_set_2[3] | buf_rspage_2[3]; // @[lsu_bus_buffer.scala 422:88]
-  wire [2:0] _T_3167 = {_T_3165,_T_3162,_T_3159}; // @[Cat.scala 29:58]
-  wire  _T_3318 = buf_rspageQ_3[3] & _T_3212; // @[lsu_bus_buffer.scala 423:82]
-  wire  _T_3320 = _T_3318 & _T_2587; // @[lsu_bus_buffer.scala 423:145]
-  wire  _T_3310 = buf_rspageQ_3[2] & _T_3204; // @[lsu_bus_buffer.scala 423:82]
-  wire  _T_3312 = _T_3310 & _T_2587; // @[lsu_bus_buffer.scala 423:145]
-  wire  _T_3302 = buf_rspageQ_3[1] & _T_3196; // @[lsu_bus_buffer.scala 423:82]
-  wire  _T_3304 = _T_3302 & _T_2587; // @[lsu_bus_buffer.scala 423:145]
-  wire  _T_3294 = buf_rspageQ_3[0] & _T_3188; // @[lsu_bus_buffer.scala 423:82]
-  wire  _T_3296 = _T_3294 & _T_2587; // @[lsu_bus_buffer.scala 423:145]
-  wire [3:0] buf_rspage_3 = {_T_3320,_T_3312,_T_3304,_T_3296}; // @[Cat.scala 29:58]
-  wire  _T_3171 = buf_rspage_set_3[0] | buf_rspage_3[0]; // @[lsu_bus_buffer.scala 422:88]
-  wire  _T_3174 = buf_rspage_set_3[1] | buf_rspage_3[1]; // @[lsu_bus_buffer.scala 422:88]
-  wire  _T_3177 = buf_rspage_set_3[2] | buf_rspage_3[2]; // @[lsu_bus_buffer.scala 422:88]
-  wire  _T_3180 = buf_rspage_set_3[3] | buf_rspage_3[3]; // @[lsu_bus_buffer.scala 422:88]
-  wire [2:0] _T_3182 = {_T_3180,_T_3177,_T_3174}; // @[Cat.scala 29:58]
-  wire  _T_3325 = ibuf_drain_vld & _T_1786; // @[lsu_bus_buffer.scala 428:63]
-  wire  _T_3327 = ibuf_drain_vld & _T_1797; // @[lsu_bus_buffer.scala 428:63]
-  wire  _T_3329 = ibuf_drain_vld & _T_1808; // @[lsu_bus_buffer.scala 428:63]
-  wire  _T_3331 = ibuf_drain_vld & _T_1819; // @[lsu_bus_buffer.scala 428:63]
-  wire [3:0] ibuf_drainvec_vld = {_T_3331,_T_3329,_T_3327,_T_3325}; // @[Cat.scala 29:58]
-  wire  _T_3339 = _T_3533 & _T_1789; // @[lsu_bus_buffer.scala 430:35]
-  wire  _T_3348 = _T_3533 & _T_1800; // @[lsu_bus_buffer.scala 430:35]
-  wire  _T_3357 = _T_3533 & _T_1811; // @[lsu_bus_buffer.scala 430:35]
-  wire  _T_3366 = _T_3533 & _T_1822; // @[lsu_bus_buffer.scala 430:35]
-  wire  _T_3396 = ibuf_drainvec_vld[0] ? ibuf_dual : io_ldst_dual_r; // @[lsu_bus_buffer.scala 432:45]
-  wire  _T_3398 = ibuf_drainvec_vld[1] ? ibuf_dual : io_ldst_dual_r; // @[lsu_bus_buffer.scala 432:45]
-  wire  _T_3400 = ibuf_drainvec_vld[2] ? ibuf_dual : io_ldst_dual_r; // @[lsu_bus_buffer.scala 432:45]
-  wire  _T_3402 = ibuf_drainvec_vld[3] ? ibuf_dual : io_ldst_dual_r; // @[lsu_bus_buffer.scala 432:45]
-  wire [3:0] buf_dual_in = {_T_3402,_T_3400,_T_3398,_T_3396}; // @[Cat.scala 29:58]
-  wire  _T_3407 = ibuf_drainvec_vld[0] ? ibuf_samedw : ldst_samedw_r; // @[lsu_bus_buffer.scala 433:47]
-  wire  _T_3409 = ibuf_drainvec_vld[1] ? ibuf_samedw : ldst_samedw_r; // @[lsu_bus_buffer.scala 433:47]
-  wire  _T_3411 = ibuf_drainvec_vld[2] ? ibuf_samedw : ldst_samedw_r; // @[lsu_bus_buffer.scala 433:47]
-  wire  _T_3413 = ibuf_drainvec_vld[3] ? ibuf_samedw : ldst_samedw_r; // @[lsu_bus_buffer.scala 433:47]
-  wire [3:0] buf_samedw_in = {_T_3413,_T_3411,_T_3409,_T_3407}; // @[Cat.scala 29:58]
-  wire  _T_3418 = ibuf_nomerge | ibuf_force_drain; // @[lsu_bus_buffer.scala 434:84]
-  wire  _T_3419 = ibuf_drainvec_vld[0] ? _T_3418 : io_no_dword_merge_r; // @[lsu_bus_buffer.scala 434:48]
-  wire  _T_3422 = ibuf_drainvec_vld[1] ? _T_3418 : io_no_dword_merge_r; // @[lsu_bus_buffer.scala 434:48]
-  wire  _T_3425 = ibuf_drainvec_vld[2] ? _T_3418 : io_no_dword_merge_r; // @[lsu_bus_buffer.scala 434:48]
-  wire  _T_3428 = ibuf_drainvec_vld[3] ? _T_3418 : io_no_dword_merge_r; // @[lsu_bus_buffer.scala 434:48]
-  wire [3:0] buf_nomerge_in = {_T_3428,_T_3425,_T_3422,_T_3419}; // @[Cat.scala 29:58]
-  wire  _T_3436 = ibuf_drainvec_vld[0] ? ibuf_dual : _T_3339; // @[lsu_bus_buffer.scala 435:47]
-  wire  _T_3441 = ibuf_drainvec_vld[1] ? ibuf_dual : _T_3348; // @[lsu_bus_buffer.scala 435:47]
-  wire  _T_3446 = ibuf_drainvec_vld[2] ? ibuf_dual : _T_3357; // @[lsu_bus_buffer.scala 435:47]
-  wire  _T_3451 = ibuf_drainvec_vld[3] ? ibuf_dual : _T_3366; // @[lsu_bus_buffer.scala 435:47]
-  wire [3:0] buf_dualhi_in = {_T_3451,_T_3446,_T_3441,_T_3436}; // @[Cat.scala 29:58]
-  wire  _T_3480 = ibuf_drainvec_vld[0] ? ibuf_sideeffect : io_is_sideeffects_r; // @[lsu_bus_buffer.scala 437:51]
-  wire  _T_3482 = ibuf_drainvec_vld[1] ? ibuf_sideeffect : io_is_sideeffects_r; // @[lsu_bus_buffer.scala 437:51]
-  wire  _T_3484 = ibuf_drainvec_vld[2] ? ibuf_sideeffect : io_is_sideeffects_r; // @[lsu_bus_buffer.scala 437:51]
-  wire  _T_3486 = ibuf_drainvec_vld[3] ? ibuf_sideeffect : io_is_sideeffects_r; // @[lsu_bus_buffer.scala 437:51]
-  wire [3:0] buf_sideeffect_in = {_T_3486,_T_3484,_T_3482,_T_3480}; // @[Cat.scala 29:58]
-  wire  _T_3491 = ibuf_drainvec_vld[0] ? ibuf_unsign : io_lsu_pkt_r_bits_unsign; // @[lsu_bus_buffer.scala 438:47]
-  wire  _T_3493 = ibuf_drainvec_vld[1] ? ibuf_unsign : io_lsu_pkt_r_bits_unsign; // @[lsu_bus_buffer.scala 438:47]
-  wire  _T_3495 = ibuf_drainvec_vld[2] ? ibuf_unsign : io_lsu_pkt_r_bits_unsign; // @[lsu_bus_buffer.scala 438:47]
-  wire  _T_3497 = ibuf_drainvec_vld[3] ? ibuf_unsign : io_lsu_pkt_r_bits_unsign; // @[lsu_bus_buffer.scala 438:47]
-  wire [3:0] buf_unsign_in = {_T_3497,_T_3495,_T_3493,_T_3491}; // @[Cat.scala 29:58]
-  wire  _T_3514 = ibuf_drainvec_vld[0] ? ibuf_write : io_lsu_pkt_r_bits_store; // @[lsu_bus_buffer.scala 440:46]
-  wire  _T_3516 = ibuf_drainvec_vld[1] ? ibuf_write : io_lsu_pkt_r_bits_store; // @[lsu_bus_buffer.scala 440:46]
-  wire  _T_3518 = ibuf_drainvec_vld[2] ? ibuf_write : io_lsu_pkt_r_bits_store; // @[lsu_bus_buffer.scala 440:46]
-  wire  _T_3520 = ibuf_drainvec_vld[3] ? ibuf_write : io_lsu_pkt_r_bits_store; // @[lsu_bus_buffer.scala 440:46]
-  wire [3:0] buf_write_in = {_T_3520,_T_3518,_T_3516,_T_3514}; // @[Cat.scala 29:58]
-  wire  _T_3553 = obuf_nosend & bus_rsp_read; // @[lsu_bus_buffer.scala 458:89]
-  wire  _T_3555 = _T_3553 & _T_1349; // @[lsu_bus_buffer.scala 458:104]
-  wire  _T_3568 = buf_state_en_0 & _T_3637; // @[lsu_bus_buffer.scala 463:44]
-  wire  _T_3569 = _T_3568 & obuf_nosend; // @[lsu_bus_buffer.scala 463:60]
-  wire  _T_3571 = _T_3569 & _T_2587; // @[lsu_bus_buffer.scala 463:74]
-  wire  _T_3574 = _T_3564 & obuf_nosend; // @[lsu_bus_buffer.scala 465:67]
-  wire  _T_3575 = _T_3574 & bus_rsp_read; // @[lsu_bus_buffer.scala 465:81]
-  wire  _T_4830 = io_lsu_axi_r_bits_resp != 2'h0; // @[lsu_bus_buffer.scala 572:64]
-  wire  bus_rsp_read_error = bus_rsp_read & _T_4830; // @[lsu_bus_buffer.scala 572:38]
-  wire  _T_3578 = _T_3574 & bus_rsp_read_error; // @[lsu_bus_buffer.scala 466:82]
-  wire  _T_3651 = bus_rsp_read_error & _T_3630; // @[lsu_bus_buffer.scala 480:91]
-  wire  _T_3653 = bus_rsp_read_error & buf_ldfwd[0]; // @[lsu_bus_buffer.scala 481:31]
-  wire  _T_3655 = _T_3653 & _T_3632; // @[lsu_bus_buffer.scala 481:46]
-  wire  _T_3656 = _T_3651 | _T_3655; // @[lsu_bus_buffer.scala 480:143]
-  wire  _T_4828 = io_lsu_axi_b_bits_resp != 2'h0; // @[lsu_bus_buffer.scala 571:66]
-  wire  bus_rsp_write_error = bus_rsp_write & _T_4828; // @[lsu_bus_buffer.scala 571:40]
-  wire  _T_3658 = bus_rsp_write_error & _T_3628; // @[lsu_bus_buffer.scala 482:33]
-  wire  _T_3659 = _T_3656 | _T_3658; // @[lsu_bus_buffer.scala 481:88]
-  wire  _T_3660 = _T_3564 & _T_3659; // @[lsu_bus_buffer.scala 480:68]
-  wire  _GEN_47 = _T_3585 & _T_3660; // @[Conditional.scala 39:67]
-  wire  _GEN_60 = _T_3551 ? _T_3578 : _GEN_47; // @[Conditional.scala 39:67]
-  wire  _GEN_72 = _T_3547 ? 1'h0 : _GEN_60; // @[Conditional.scala 39:67]
-  wire  buf_error_en_0 = _T_3524 ? 1'h0 : _GEN_72; // @[Conditional.scala 40:58]
-  wire  _T_3587 = buf_write[0] & bus_rsp_write_error; // @[lsu_bus_buffer.scala 470:71]
-  wire  _T_3588 = io_dec_tlu_force_halt | _T_3587; // @[lsu_bus_buffer.scala 470:55]
-  wire  _T_3590 = ~buf_samedw_0; // @[lsu_bus_buffer.scala 471:30]
-  wire  _T_3591 = buf_dual_0 & _T_3590; // @[lsu_bus_buffer.scala 471:28]
-  wire  _T_3594 = _T_3591 & _T_3637; // @[lsu_bus_buffer.scala 471:45]
-  wire [2:0] _GEN_19 = 2'h1 == buf_dualtag_0 ? buf_state_1 : buf_state_0; // @[lsu_bus_buffer.scala 471:90]
-  wire [2:0] _GEN_20 = 2'h2 == buf_dualtag_0 ? buf_state_2 : _GEN_19; // @[lsu_bus_buffer.scala 471:90]
-  wire [2:0] _GEN_21 = 2'h3 == buf_dualtag_0 ? buf_state_3 : _GEN_20; // @[lsu_bus_buffer.scala 471:90]
-  wire  _T_3595 = _GEN_21 != 3'h4; // @[lsu_bus_buffer.scala 471:90]
-  wire  _T_3596 = _T_3594 & _T_3595; // @[lsu_bus_buffer.scala 471:61]
-  wire  _T_4478 = _T_2710 | _T_2707; // @[lsu_bus_buffer.scala 532:93]
-  wire  _T_4479 = _T_4478 | _T_2704; // @[lsu_bus_buffer.scala 532:93]
-  wire  any_done_wait_state = _T_4479 | _T_2701; // @[lsu_bus_buffer.scala 532:93]
-  wire  _T_3598 = buf_ldfwd[0] | any_done_wait_state; // @[lsu_bus_buffer.scala 472:31]
-  wire  _T_3604 = buf_dualtag_0 == 2'h0; // @[lsu_bus_buffer.scala 60:118]
-  wire  _T_3606 = buf_dualtag_0 == 2'h1; // @[lsu_bus_buffer.scala 60:118]
-  wire  _T_3608 = buf_dualtag_0 == 2'h2; // @[lsu_bus_buffer.scala 60:118]
-  wire  _T_3610 = buf_dualtag_0 == 2'h3; // @[lsu_bus_buffer.scala 60:118]
-  wire  _T_3612 = _T_3604 & buf_ldfwd[0]; // @[Mux.scala 27:72]
-  wire  _T_3613 = _T_3606 & buf_ldfwd[1]; // @[Mux.scala 27:72]
-  wire  _T_3614 = _T_3608 & buf_ldfwd[2]; // @[Mux.scala 27:72]
-  wire  _T_3615 = _T_3610 & buf_ldfwd[3]; // @[Mux.scala 27:72]
-  wire  _T_3616 = _T_3612 | _T_3613; // @[Mux.scala 27:72]
-  wire  _T_3617 = _T_3616 | _T_3614; // @[Mux.scala 27:72]
-  wire  _T_3618 = _T_3617 | _T_3615; // @[Mux.scala 27:72]
-  wire  _T_3620 = _T_3594 & _T_3618; // @[lsu_bus_buffer.scala 472:101]
-  wire  _T_3621 = _GEN_21 == 3'h4; // @[lsu_bus_buffer.scala 472:167]
-  wire  _T_3622 = _T_3620 & _T_3621; // @[lsu_bus_buffer.scala 472:138]
-  wire  _T_3623 = _T_3622 & any_done_wait_state; // @[lsu_bus_buffer.scala 472:187]
-  wire  _T_3624 = _T_3598 | _T_3623; // @[lsu_bus_buffer.scala 472:53]
-  wire  _T_3647 = buf_state_bus_en_0 & bus_rsp_read; // @[lsu_bus_buffer.scala 479:47]
-  wire  _T_3648 = _T_3647 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 479:62]
-  wire  _T_3661 = ~buf_error_en_0; // @[lsu_bus_buffer.scala 483:50]
-  wire  _T_3662 = buf_state_en_0 & _T_3661; // @[lsu_bus_buffer.scala 483:48]
-  wire  _T_3674 = buf_ldfwd[0] | _T_3679[0]; // @[lsu_bus_buffer.scala 487:90]
-  wire  _T_3675 = _T_3674 | any_done_wait_state; // @[lsu_bus_buffer.scala 487:118]
-  wire  _GEN_27 = _T_3695 | io_dec_tlu_force_halt; // @[Conditional.scala 39:67]
-  wire  _GEN_30 = _T_3695 ? buf_state_en_0 : io_dec_tlu_force_halt; // @[Conditional.scala 39:67]
-  wire  _GEN_34 = _T_3687 ? io_dec_tlu_force_halt : _GEN_27; // @[Conditional.scala 39:67]
-  wire  _GEN_35 = _T_3687 ? io_dec_tlu_force_halt : _GEN_30; // @[Conditional.scala 39:67]
-  wire  _GEN_40 = _T_3669 ? io_dec_tlu_force_halt : _GEN_34; // @[Conditional.scala 39:67]
-  wire  _GEN_41 = _T_3669 ? io_dec_tlu_force_halt : _GEN_35; // @[Conditional.scala 39:67]
-  wire  _GEN_46 = _T_3585 & _T_3648; // @[Conditional.scala 39:67]
-  wire  _GEN_50 = _T_3585 ? io_dec_tlu_force_halt : _GEN_40; // @[Conditional.scala 39:67]
-  wire  _GEN_51 = _T_3585 ? io_dec_tlu_force_halt : _GEN_41; // @[Conditional.scala 39:67]
-  wire  _GEN_57 = _T_3551 ? _T_3571 : _GEN_51; // @[Conditional.scala 39:67]
-  wire  _GEN_59 = _T_3551 ? _T_3575 : _GEN_46; // @[Conditional.scala 39:67]
-  wire  _GEN_63 = _T_3551 ? io_dec_tlu_force_halt : _GEN_50; // @[Conditional.scala 39:67]
-  wire  _GEN_69 = _T_3547 ? io_dec_tlu_force_halt : _GEN_57; // @[Conditional.scala 39:67]
-  wire  _GEN_71 = _T_3547 ? 1'h0 : _GEN_59; // @[Conditional.scala 39:67]
-  wire  _GEN_75 = _T_3547 ? io_dec_tlu_force_halt : _GEN_63; // @[Conditional.scala 39:67]
-  wire  buf_wr_en_0 = _T_3524 & buf_state_en_0; // @[Conditional.scala 40:58]
-  wire  buf_ldfwd_en_0 = _T_3524 ? io_dec_tlu_force_halt : _GEN_69; // @[Conditional.scala 40:58]
-  wire  buf_rst_0 = _T_3524 ? io_dec_tlu_force_halt : _GEN_75; // @[Conditional.scala 40:58]
-  wire  _T_3758 = buf_state_en_1 & _T_3827; // @[lsu_bus_buffer.scala 463:44]
-  wire  _T_3759 = _T_3758 & obuf_nosend; // @[lsu_bus_buffer.scala 463:60]
-  wire  _T_3761 = _T_3759 & _T_2587; // @[lsu_bus_buffer.scala 463:74]
-  wire  _T_3764 = _T_3754 & obuf_nosend; // @[lsu_bus_buffer.scala 465:67]
-  wire  _T_3765 = _T_3764 & bus_rsp_read; // @[lsu_bus_buffer.scala 465:81]
-  wire  _T_3768 = _T_3764 & bus_rsp_read_error; // @[lsu_bus_buffer.scala 466:82]
-  wire  _T_3841 = bus_rsp_read_error & _T_3820; // @[lsu_bus_buffer.scala 480:91]
-  wire  _T_3843 = bus_rsp_read_error & buf_ldfwd[1]; // @[lsu_bus_buffer.scala 481:31]
-  wire  _T_3845 = _T_3843 & _T_3822; // @[lsu_bus_buffer.scala 481:46]
-  wire  _T_3846 = _T_3841 | _T_3845; // @[lsu_bus_buffer.scala 480:143]
-  wire  _T_3848 = bus_rsp_write_error & _T_3818; // @[lsu_bus_buffer.scala 482:33]
-  wire  _T_3849 = _T_3846 | _T_3848; // @[lsu_bus_buffer.scala 481:88]
-  wire  _T_3850 = _T_3754 & _T_3849; // @[lsu_bus_buffer.scala 480:68]
-  wire  _GEN_124 = _T_3775 & _T_3850; // @[Conditional.scala 39:67]
-  wire  _GEN_137 = _T_3741 ? _T_3768 : _GEN_124; // @[Conditional.scala 39:67]
-  wire  _GEN_149 = _T_3737 ? 1'h0 : _GEN_137; // @[Conditional.scala 39:67]
-  wire  buf_error_en_1 = _T_3714 ? 1'h0 : _GEN_149; // @[Conditional.scala 40:58]
-  wire  _T_3777 = buf_write[1] & bus_rsp_write_error; // @[lsu_bus_buffer.scala 470:71]
-  wire  _T_3778 = io_dec_tlu_force_halt | _T_3777; // @[lsu_bus_buffer.scala 470:55]
-  wire  _T_3780 = ~buf_samedw_1; // @[lsu_bus_buffer.scala 471:30]
-  wire  _T_3781 = buf_dual_1 & _T_3780; // @[lsu_bus_buffer.scala 471:28]
-  wire  _T_3784 = _T_3781 & _T_3827; // @[lsu_bus_buffer.scala 471:45]
-  wire [2:0] _GEN_96 = 2'h1 == buf_dualtag_1 ? buf_state_1 : buf_state_0; // @[lsu_bus_buffer.scala 471:90]
-  wire [2:0] _GEN_97 = 2'h2 == buf_dualtag_1 ? buf_state_2 : _GEN_96; // @[lsu_bus_buffer.scala 471:90]
-  wire [2:0] _GEN_98 = 2'h3 == buf_dualtag_1 ? buf_state_3 : _GEN_97; // @[lsu_bus_buffer.scala 471:90]
-  wire  _T_3785 = _GEN_98 != 3'h4; // @[lsu_bus_buffer.scala 471:90]
-  wire  _T_3786 = _T_3784 & _T_3785; // @[lsu_bus_buffer.scala 471:61]
-  wire  _T_3788 = buf_ldfwd[1] | any_done_wait_state; // @[lsu_bus_buffer.scala 472:31]
-  wire  _T_3794 = buf_dualtag_1 == 2'h0; // @[lsu_bus_buffer.scala 60:118]
-  wire  _T_3796 = buf_dualtag_1 == 2'h1; // @[lsu_bus_buffer.scala 60:118]
-  wire  _T_3798 = buf_dualtag_1 == 2'h2; // @[lsu_bus_buffer.scala 60:118]
-  wire  _T_3800 = buf_dualtag_1 == 2'h3; // @[lsu_bus_buffer.scala 60:118]
-  wire  _T_3802 = _T_3794 & buf_ldfwd[0]; // @[Mux.scala 27:72]
-  wire  _T_3803 = _T_3796 & buf_ldfwd[1]; // @[Mux.scala 27:72]
-  wire  _T_3804 = _T_3798 & buf_ldfwd[2]; // @[Mux.scala 27:72]
-  wire  _T_3805 = _T_3800 & buf_ldfwd[3]; // @[Mux.scala 27:72]
-  wire  _T_3806 = _T_3802 | _T_3803; // @[Mux.scala 27:72]
-  wire  _T_3807 = _T_3806 | _T_3804; // @[Mux.scala 27:72]
-  wire  _T_3808 = _T_3807 | _T_3805; // @[Mux.scala 27:72]
-  wire  _T_3810 = _T_3784 & _T_3808; // @[lsu_bus_buffer.scala 472:101]
-  wire  _T_3811 = _GEN_98 == 3'h4; // @[lsu_bus_buffer.scala 472:167]
-  wire  _T_3812 = _T_3810 & _T_3811; // @[lsu_bus_buffer.scala 472:138]
-  wire  _T_3813 = _T_3812 & any_done_wait_state; // @[lsu_bus_buffer.scala 472:187]
-  wire  _T_3814 = _T_3788 | _T_3813; // @[lsu_bus_buffer.scala 472:53]
-  wire  _T_3837 = buf_state_bus_en_1 & bus_rsp_read; // @[lsu_bus_buffer.scala 479:47]
-  wire  _T_3838 = _T_3837 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 479:62]
-  wire  _T_3851 = ~buf_error_en_1; // @[lsu_bus_buffer.scala 483:50]
-  wire  _T_3852 = buf_state_en_1 & _T_3851; // @[lsu_bus_buffer.scala 483:48]
-  wire  _T_3864 = buf_ldfwd[1] | _T_3869[0]; // @[lsu_bus_buffer.scala 487:90]
-  wire  _T_3865 = _T_3864 | any_done_wait_state; // @[lsu_bus_buffer.scala 487:118]
-  wire  _GEN_104 = _T_3885 | io_dec_tlu_force_halt; // @[Conditional.scala 39:67]
-  wire  _GEN_107 = _T_3885 ? buf_state_en_1 : io_dec_tlu_force_halt; // @[Conditional.scala 39:67]
-  wire  _GEN_111 = _T_3877 ? io_dec_tlu_force_halt : _GEN_104; // @[Conditional.scala 39:67]
-  wire  _GEN_112 = _T_3877 ? io_dec_tlu_force_halt : _GEN_107; // @[Conditional.scala 39:67]
-  wire  _GEN_117 = _T_3859 ? io_dec_tlu_force_halt : _GEN_111; // @[Conditional.scala 39:67]
-  wire  _GEN_118 = _T_3859 ? io_dec_tlu_force_halt : _GEN_112; // @[Conditional.scala 39:67]
-  wire  _GEN_123 = _T_3775 & _T_3838; // @[Conditional.scala 39:67]
-  wire  _GEN_127 = _T_3775 ? io_dec_tlu_force_halt : _GEN_117; // @[Conditional.scala 39:67]
-  wire  _GEN_128 = _T_3775 ? io_dec_tlu_force_halt : _GEN_118; // @[Conditional.scala 39:67]
-  wire  _GEN_134 = _T_3741 ? _T_3761 : _GEN_128; // @[Conditional.scala 39:67]
-  wire  _GEN_136 = _T_3741 ? _T_3765 : _GEN_123; // @[Conditional.scala 39:67]
-  wire  _GEN_140 = _T_3741 ? io_dec_tlu_force_halt : _GEN_127; // @[Conditional.scala 39:67]
-  wire  _GEN_146 = _T_3737 ? io_dec_tlu_force_halt : _GEN_134; // @[Conditional.scala 39:67]
-  wire  _GEN_148 = _T_3737 ? 1'h0 : _GEN_136; // @[Conditional.scala 39:67]
-  wire  _GEN_152 = _T_3737 ? io_dec_tlu_force_halt : _GEN_140; // @[Conditional.scala 39:67]
-  wire  buf_wr_en_1 = _T_3714 & buf_state_en_1; // @[Conditional.scala 40:58]
-  wire  buf_ldfwd_en_1 = _T_3714 ? io_dec_tlu_force_halt : _GEN_146; // @[Conditional.scala 40:58]
-  wire  buf_rst_1 = _T_3714 ? io_dec_tlu_force_halt : _GEN_152; // @[Conditional.scala 40:58]
-  wire  _T_3948 = buf_state_en_2 & _T_4017; // @[lsu_bus_buffer.scala 463:44]
-  wire  _T_3949 = _T_3948 & obuf_nosend; // @[lsu_bus_buffer.scala 463:60]
-  wire  _T_3951 = _T_3949 & _T_2587; // @[lsu_bus_buffer.scala 463:74]
-  wire  _T_3954 = _T_3944 & obuf_nosend; // @[lsu_bus_buffer.scala 465:67]
-  wire  _T_3955 = _T_3954 & bus_rsp_read; // @[lsu_bus_buffer.scala 465:81]
-  wire  _T_3958 = _T_3954 & bus_rsp_read_error; // @[lsu_bus_buffer.scala 466:82]
-  wire  _T_4031 = bus_rsp_read_error & _T_4010; // @[lsu_bus_buffer.scala 480:91]
-  wire  _T_4033 = bus_rsp_read_error & buf_ldfwd[2]; // @[lsu_bus_buffer.scala 481:31]
-  wire  _T_4035 = _T_4033 & _T_4012; // @[lsu_bus_buffer.scala 481:46]
-  wire  _T_4036 = _T_4031 | _T_4035; // @[lsu_bus_buffer.scala 480:143]
-  wire  _T_4038 = bus_rsp_write_error & _T_4008; // @[lsu_bus_buffer.scala 482:33]
-  wire  _T_4039 = _T_4036 | _T_4038; // @[lsu_bus_buffer.scala 481:88]
-  wire  _T_4040 = _T_3944 & _T_4039; // @[lsu_bus_buffer.scala 480:68]
-  wire  _GEN_201 = _T_3965 & _T_4040; // @[Conditional.scala 39:67]
-  wire  _GEN_214 = _T_3931 ? _T_3958 : _GEN_201; // @[Conditional.scala 39:67]
-  wire  _GEN_226 = _T_3927 ? 1'h0 : _GEN_214; // @[Conditional.scala 39:67]
-  wire  buf_error_en_2 = _T_3904 ? 1'h0 : _GEN_226; // @[Conditional.scala 40:58]
-  wire  _T_3967 = buf_write[2] & bus_rsp_write_error; // @[lsu_bus_buffer.scala 470:71]
-  wire  _T_3968 = io_dec_tlu_force_halt | _T_3967; // @[lsu_bus_buffer.scala 470:55]
-  wire  _T_3970 = ~buf_samedw_2; // @[lsu_bus_buffer.scala 471:30]
-  wire  _T_3971 = buf_dual_2 & _T_3970; // @[lsu_bus_buffer.scala 471:28]
-  wire  _T_3974 = _T_3971 & _T_4017; // @[lsu_bus_buffer.scala 471:45]
-  wire [2:0] _GEN_173 = 2'h1 == buf_dualtag_2 ? buf_state_1 : buf_state_0; // @[lsu_bus_buffer.scala 471:90]
-  wire [2:0] _GEN_174 = 2'h2 == buf_dualtag_2 ? buf_state_2 : _GEN_173; // @[lsu_bus_buffer.scala 471:90]
-  wire [2:0] _GEN_175 = 2'h3 == buf_dualtag_2 ? buf_state_3 : _GEN_174; // @[lsu_bus_buffer.scala 471:90]
-  wire  _T_3975 = _GEN_175 != 3'h4; // @[lsu_bus_buffer.scala 471:90]
-  wire  _T_3976 = _T_3974 & _T_3975; // @[lsu_bus_buffer.scala 471:61]
-  wire  _T_3978 = buf_ldfwd[2] | any_done_wait_state; // @[lsu_bus_buffer.scala 472:31]
-  wire  _T_3984 = buf_dualtag_2 == 2'h0; // @[lsu_bus_buffer.scala 60:118]
-  wire  _T_3986 = buf_dualtag_2 == 2'h1; // @[lsu_bus_buffer.scala 60:118]
-  wire  _T_3988 = buf_dualtag_2 == 2'h2; // @[lsu_bus_buffer.scala 60:118]
-  wire  _T_3990 = buf_dualtag_2 == 2'h3; // @[lsu_bus_buffer.scala 60:118]
-  wire  _T_3992 = _T_3984 & buf_ldfwd[0]; // @[Mux.scala 27:72]
-  wire  _T_3993 = _T_3986 & buf_ldfwd[1]; // @[Mux.scala 27:72]
-  wire  _T_3994 = _T_3988 & buf_ldfwd[2]; // @[Mux.scala 27:72]
-  wire  _T_3995 = _T_3990 & buf_ldfwd[3]; // @[Mux.scala 27:72]
-  wire  _T_3996 = _T_3992 | _T_3993; // @[Mux.scala 27:72]
-  wire  _T_3997 = _T_3996 | _T_3994; // @[Mux.scala 27:72]
-  wire  _T_3998 = _T_3997 | _T_3995; // @[Mux.scala 27:72]
-  wire  _T_4000 = _T_3974 & _T_3998; // @[lsu_bus_buffer.scala 472:101]
-  wire  _T_4001 = _GEN_175 == 3'h4; // @[lsu_bus_buffer.scala 472:167]
-  wire  _T_4002 = _T_4000 & _T_4001; // @[lsu_bus_buffer.scala 472:138]
-  wire  _T_4003 = _T_4002 & any_done_wait_state; // @[lsu_bus_buffer.scala 472:187]
-  wire  _T_4004 = _T_3978 | _T_4003; // @[lsu_bus_buffer.scala 472:53]
-  wire  _T_4027 = buf_state_bus_en_2 & bus_rsp_read; // @[lsu_bus_buffer.scala 479:47]
-  wire  _T_4028 = _T_4027 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 479:62]
-  wire  _T_4041 = ~buf_error_en_2; // @[lsu_bus_buffer.scala 483:50]
-  wire  _T_4042 = buf_state_en_2 & _T_4041; // @[lsu_bus_buffer.scala 483:48]
-  wire  _T_4054 = buf_ldfwd[2] | _T_4059[0]; // @[lsu_bus_buffer.scala 487:90]
-  wire  _T_4055 = _T_4054 | any_done_wait_state; // @[lsu_bus_buffer.scala 487:118]
-  wire  _GEN_181 = _T_4075 | io_dec_tlu_force_halt; // @[Conditional.scala 39:67]
-  wire  _GEN_184 = _T_4075 ? buf_state_en_2 : io_dec_tlu_force_halt; // @[Conditional.scala 39:67]
-  wire  _GEN_188 = _T_4067 ? io_dec_tlu_force_halt : _GEN_181; // @[Conditional.scala 39:67]
-  wire  _GEN_189 = _T_4067 ? io_dec_tlu_force_halt : _GEN_184; // @[Conditional.scala 39:67]
-  wire  _GEN_194 = _T_4049 ? io_dec_tlu_force_halt : _GEN_188; // @[Conditional.scala 39:67]
-  wire  _GEN_195 = _T_4049 ? io_dec_tlu_force_halt : _GEN_189; // @[Conditional.scala 39:67]
-  wire  _GEN_200 = _T_3965 & _T_4028; // @[Conditional.scala 39:67]
-  wire  _GEN_204 = _T_3965 ? io_dec_tlu_force_halt : _GEN_194; // @[Conditional.scala 39:67]
-  wire  _GEN_205 = _T_3965 ? io_dec_tlu_force_halt : _GEN_195; // @[Conditional.scala 39:67]
-  wire  _GEN_211 = _T_3931 ? _T_3951 : _GEN_205; // @[Conditional.scala 39:67]
-  wire  _GEN_213 = _T_3931 ? _T_3955 : _GEN_200; // @[Conditional.scala 39:67]
-  wire  _GEN_217 = _T_3931 ? io_dec_tlu_force_halt : _GEN_204; // @[Conditional.scala 39:67]
-  wire  _GEN_223 = _T_3927 ? io_dec_tlu_force_halt : _GEN_211; // @[Conditional.scala 39:67]
-  wire  _GEN_225 = _T_3927 ? 1'h0 : _GEN_213; // @[Conditional.scala 39:67]
-  wire  _GEN_229 = _T_3927 ? io_dec_tlu_force_halt : _GEN_217; // @[Conditional.scala 39:67]
-  wire  buf_wr_en_2 = _T_3904 & buf_state_en_2; // @[Conditional.scala 40:58]
-  wire  buf_ldfwd_en_2 = _T_3904 ? io_dec_tlu_force_halt : _GEN_223; // @[Conditional.scala 40:58]
-  wire  buf_rst_2 = _T_3904 ? io_dec_tlu_force_halt : _GEN_229; // @[Conditional.scala 40:58]
-  wire  _T_4138 = buf_state_en_3 & _T_4207; // @[lsu_bus_buffer.scala 463:44]
-  wire  _T_4139 = _T_4138 & obuf_nosend; // @[lsu_bus_buffer.scala 463:60]
-  wire  _T_4141 = _T_4139 & _T_2587; // @[lsu_bus_buffer.scala 463:74]
-  wire  _T_4144 = _T_4134 & obuf_nosend; // @[lsu_bus_buffer.scala 465:67]
-  wire  _T_4145 = _T_4144 & bus_rsp_read; // @[lsu_bus_buffer.scala 465:81]
-  wire  _T_4148 = _T_4144 & bus_rsp_read_error; // @[lsu_bus_buffer.scala 466:82]
-  wire  _T_4221 = bus_rsp_read_error & _T_4200; // @[lsu_bus_buffer.scala 480:91]
-  wire  _T_4223 = bus_rsp_read_error & buf_ldfwd[3]; // @[lsu_bus_buffer.scala 481:31]
-  wire  _T_4225 = _T_4223 & _T_4202; // @[lsu_bus_buffer.scala 481:46]
-  wire  _T_4226 = _T_4221 | _T_4225; // @[lsu_bus_buffer.scala 480:143]
-  wire  _T_4228 = bus_rsp_write_error & _T_4198; // @[lsu_bus_buffer.scala 482:33]
-  wire  _T_4229 = _T_4226 | _T_4228; // @[lsu_bus_buffer.scala 481:88]
-  wire  _T_4230 = _T_4134 & _T_4229; // @[lsu_bus_buffer.scala 480:68]
-  wire  _GEN_278 = _T_4155 & _T_4230; // @[Conditional.scala 39:67]
-  wire  _GEN_291 = _T_4121 ? _T_4148 : _GEN_278; // @[Conditional.scala 39:67]
-  wire  _GEN_303 = _T_4117 ? 1'h0 : _GEN_291; // @[Conditional.scala 39:67]
-  wire  buf_error_en_3 = _T_4094 ? 1'h0 : _GEN_303; // @[Conditional.scala 40:58]
-  wire  _T_4157 = buf_write[3] & bus_rsp_write_error; // @[lsu_bus_buffer.scala 470:71]
-  wire  _T_4158 = io_dec_tlu_force_halt | _T_4157; // @[lsu_bus_buffer.scala 470:55]
-  wire  _T_4160 = ~buf_samedw_3; // @[lsu_bus_buffer.scala 471:30]
-  wire  _T_4161 = buf_dual_3 & _T_4160; // @[lsu_bus_buffer.scala 471:28]
-  wire  _T_4164 = _T_4161 & _T_4207; // @[lsu_bus_buffer.scala 471:45]
-  wire [2:0] _GEN_250 = 2'h1 == buf_dualtag_3 ? buf_state_1 : buf_state_0; // @[lsu_bus_buffer.scala 471:90]
-  wire [2:0] _GEN_251 = 2'h2 == buf_dualtag_3 ? buf_state_2 : _GEN_250; // @[lsu_bus_buffer.scala 471:90]
-  wire [2:0] _GEN_252 = 2'h3 == buf_dualtag_3 ? buf_state_3 : _GEN_251; // @[lsu_bus_buffer.scala 471:90]
-  wire  _T_4165 = _GEN_252 != 3'h4; // @[lsu_bus_buffer.scala 471:90]
-  wire  _T_4166 = _T_4164 & _T_4165; // @[lsu_bus_buffer.scala 471:61]
-  wire  _T_4168 = buf_ldfwd[3] | any_done_wait_state; // @[lsu_bus_buffer.scala 472:31]
-  wire  _T_4174 = buf_dualtag_3 == 2'h0; // @[lsu_bus_buffer.scala 60:118]
-  wire  _T_4176 = buf_dualtag_3 == 2'h1; // @[lsu_bus_buffer.scala 60:118]
-  wire  _T_4178 = buf_dualtag_3 == 2'h2; // @[lsu_bus_buffer.scala 60:118]
-  wire  _T_4180 = buf_dualtag_3 == 2'h3; // @[lsu_bus_buffer.scala 60:118]
-  wire  _T_4182 = _T_4174 & buf_ldfwd[0]; // @[Mux.scala 27:72]
-  wire  _T_4183 = _T_4176 & buf_ldfwd[1]; // @[Mux.scala 27:72]
-  wire  _T_4184 = _T_4178 & buf_ldfwd[2]; // @[Mux.scala 27:72]
-  wire  _T_4185 = _T_4180 & buf_ldfwd[3]; // @[Mux.scala 27:72]
-  wire  _T_4186 = _T_4182 | _T_4183; // @[Mux.scala 27:72]
-  wire  _T_4187 = _T_4186 | _T_4184; // @[Mux.scala 27:72]
-  wire  _T_4188 = _T_4187 | _T_4185; // @[Mux.scala 27:72]
-  wire  _T_4190 = _T_4164 & _T_4188; // @[lsu_bus_buffer.scala 472:101]
-  wire  _T_4191 = _GEN_252 == 3'h4; // @[lsu_bus_buffer.scala 472:167]
-  wire  _T_4192 = _T_4190 & _T_4191; // @[lsu_bus_buffer.scala 472:138]
-  wire  _T_4193 = _T_4192 & any_done_wait_state; // @[lsu_bus_buffer.scala 472:187]
-  wire  _T_4194 = _T_4168 | _T_4193; // @[lsu_bus_buffer.scala 472:53]
-  wire  _T_4217 = buf_state_bus_en_3 & bus_rsp_read; // @[lsu_bus_buffer.scala 479:47]
-  wire  _T_4218 = _T_4217 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 479:62]
-  wire  _T_4231 = ~buf_error_en_3; // @[lsu_bus_buffer.scala 483:50]
-  wire  _T_4232 = buf_state_en_3 & _T_4231; // @[lsu_bus_buffer.scala 483:48]
-  wire  _T_4244 = buf_ldfwd[3] | _T_4249[0]; // @[lsu_bus_buffer.scala 487:90]
-  wire  _T_4245 = _T_4244 | any_done_wait_state; // @[lsu_bus_buffer.scala 487:118]
-  wire  _GEN_258 = _T_4265 | io_dec_tlu_force_halt; // @[Conditional.scala 39:67]
-  wire  _GEN_261 = _T_4265 ? buf_state_en_3 : io_dec_tlu_force_halt; // @[Conditional.scala 39:67]
-  wire  _GEN_265 = _T_4257 ? io_dec_tlu_force_halt : _GEN_258; // @[Conditional.scala 39:67]
-  wire  _GEN_266 = _T_4257 ? io_dec_tlu_force_halt : _GEN_261; // @[Conditional.scala 39:67]
-  wire  _GEN_271 = _T_4239 ? io_dec_tlu_force_halt : _GEN_265; // @[Conditional.scala 39:67]
-  wire  _GEN_272 = _T_4239 ? io_dec_tlu_force_halt : _GEN_266; // @[Conditional.scala 39:67]
-  wire  _GEN_277 = _T_4155 & _T_4218; // @[Conditional.scala 39:67]
-  wire  _GEN_281 = _T_4155 ? io_dec_tlu_force_halt : _GEN_271; // @[Conditional.scala 39:67]
-  wire  _GEN_282 = _T_4155 ? io_dec_tlu_force_halt : _GEN_272; // @[Conditional.scala 39:67]
-  wire  _GEN_288 = _T_4121 ? _T_4141 : _GEN_282; // @[Conditional.scala 39:67]
-  wire  _GEN_290 = _T_4121 ? _T_4145 : _GEN_277; // @[Conditional.scala 39:67]
-  wire  _GEN_294 = _T_4121 ? io_dec_tlu_force_halt : _GEN_281; // @[Conditional.scala 39:67]
-  wire  _GEN_300 = _T_4117 ? io_dec_tlu_force_halt : _GEN_288; // @[Conditional.scala 39:67]
-  wire  _GEN_302 = _T_4117 ? 1'h0 : _GEN_290; // @[Conditional.scala 39:67]
-  wire  _GEN_306 = _T_4117 ? io_dec_tlu_force_halt : _GEN_294; // @[Conditional.scala 39:67]
-  wire  buf_wr_en_3 = _T_4094 & buf_state_en_3; // @[Conditional.scala 40:58]
-  wire  buf_ldfwd_en_3 = _T_4094 ? io_dec_tlu_force_halt : _GEN_300; // @[Conditional.scala 40:58]
-  wire  buf_rst_3 = _T_4094 ? io_dec_tlu_force_halt : _GEN_306; // @[Conditional.scala 40:58]
-  reg  _T_4320; // @[Reg.scala 27:20]
-  reg  _T_4323; // @[Reg.scala 27:20]
-  reg  _T_4326; // @[Reg.scala 27:20]
-  reg  _T_4329; // @[Reg.scala 27:20]
-  wire [3:0] buf_unsign = {_T_4329,_T_4326,_T_4323,_T_4320}; // @[Cat.scala 29:58]
-  reg  _T_4395; // @[lsu_bus_buffer.scala 526:80]
-  reg  _T_4390; // @[lsu_bus_buffer.scala 526:80]
-  reg  _T_4385; // @[lsu_bus_buffer.scala 526:80]
-  reg  _T_4380; // @[lsu_bus_buffer.scala 526:80]
-  wire [3:0] buf_error = {_T_4395,_T_4390,_T_4385,_T_4380}; // @[Cat.scala 29:58]
-  wire  _T_4377 = buf_error_en_0 | buf_error[0]; // @[lsu_bus_buffer.scala 526:84]
-  wire  _T_4378 = ~buf_rst_0; // @[lsu_bus_buffer.scala 526:126]
-  wire  _T_4382 = buf_error_en_1 | buf_error[1]; // @[lsu_bus_buffer.scala 526:84]
-  wire  _T_4383 = ~buf_rst_1; // @[lsu_bus_buffer.scala 526:126]
-  wire  _T_4387 = buf_error_en_2 | buf_error[2]; // @[lsu_bus_buffer.scala 526:84]
-  wire  _T_4388 = ~buf_rst_2; // @[lsu_bus_buffer.scala 526:126]
-  wire  _T_4392 = buf_error_en_3 | buf_error[3]; // @[lsu_bus_buffer.scala 526:84]
-  wire  _T_4393 = ~buf_rst_3; // @[lsu_bus_buffer.scala 526:126]
-  wire [1:0] _T_4399 = {io_lsu_busreq_m,1'h0}; // @[Cat.scala 29:58]
-  wire [1:0] _T_4400 = io_ldst_dual_m ? _T_4399 : {{1'd0}, io_lsu_busreq_m}; // @[lsu_bus_buffer.scala 528:28]
-  wire [1:0] _T_4401 = {io_lsu_busreq_r,1'h0}; // @[Cat.scala 29:58]
-  wire [1:0] _T_4402 = io_ldst_dual_r ? _T_4401 : {{1'd0}, io_lsu_busreq_r}; // @[lsu_bus_buffer.scala 528:94]
-  wire [2:0] _T_4403 = _T_4400 + _T_4402; // @[lsu_bus_buffer.scala 528:88]
-  wire [2:0] _GEN_392 = {{2'd0}, ibuf_valid}; // @[lsu_bus_buffer.scala 528:154]
-  wire [3:0] _T_4404 = _T_4403 + _GEN_392; // @[lsu_bus_buffer.scala 528:154]
-  wire [1:0] _T_4409 = _T_5 + _T_12; // @[lsu_bus_buffer.scala 528:217]
-  wire [1:0] _GEN_393 = {{1'd0}, _T_19}; // @[lsu_bus_buffer.scala 528:217]
-  wire [2:0] _T_4410 = _T_4409 + _GEN_393; // @[lsu_bus_buffer.scala 528:217]
-  wire [2:0] _GEN_394 = {{2'd0}, _T_26}; // @[lsu_bus_buffer.scala 528:217]
-  wire [3:0] _T_4411 = _T_4410 + _GEN_394; // @[lsu_bus_buffer.scala 528:217]
-  wire [3:0] buf_numvld_any = _T_4404 + _T_4411; // @[lsu_bus_buffer.scala 528:169]
-  wire  _T_4482 = io_ldst_dual_d & io_dec_lsu_valid_raw_d; // @[lsu_bus_buffer.scala 534:52]
-  wire  _T_4483 = buf_numvld_any >= 4'h3; // @[lsu_bus_buffer.scala 534:92]
-  wire  _T_4484 = buf_numvld_any == 4'h4; // @[lsu_bus_buffer.scala 534:121]
-  wire  _T_4486 = |buf_state_0; // @[lsu_bus_buffer.scala 535:52]
-  wire  _T_4487 = |buf_state_1; // @[lsu_bus_buffer.scala 535:52]
-  wire  _T_4488 = |buf_state_2; // @[lsu_bus_buffer.scala 535:52]
-  wire  _T_4489 = |buf_state_3; // @[lsu_bus_buffer.scala 535:52]
-  wire  _T_4490 = _T_4486 | _T_4487; // @[lsu_bus_buffer.scala 535:65]
-  wire  _T_4491 = _T_4490 | _T_4488; // @[lsu_bus_buffer.scala 535:65]
-  wire  _T_4492 = _T_4491 | _T_4489; // @[lsu_bus_buffer.scala 535:65]
-  wire  _T_4493 = ~_T_4492; // @[lsu_bus_buffer.scala 535:34]
-  wire  _T_4495 = _T_4493 & _T_852; // @[lsu_bus_buffer.scala 535:70]
-  wire  _T_4498 = io_lsu_busreq_m & io_lsu_pkt_m_valid; // @[lsu_bus_buffer.scala 537:64]
-  wire  _T_4499 = _T_4498 & io_lsu_pkt_m_bits_load; // @[lsu_bus_buffer.scala 537:85]
-  wire  _T_4500 = ~io_flush_m_up; // @[lsu_bus_buffer.scala 537:112]
-  wire  _T_4501 = _T_4499 & _T_4500; // @[lsu_bus_buffer.scala 537:110]
-  wire  _T_4502 = ~io_ld_full_hit_m; // @[lsu_bus_buffer.scala 537:129]
-  wire  _T_4504 = ~io_lsu_commit_r; // @[lsu_bus_buffer.scala 540:74]
-  reg  lsu_nonblock_load_valid_r; // @[lsu_bus_buffer.scala 625:66]
-  wire  _T_4518 = _T_2763 & _T_3637; // @[Mux.scala 27:72]
-  wire  _T_4519 = _T_2785 & _T_3827; // @[Mux.scala 27:72]
-  wire  _T_4520 = _T_2807 & _T_4017; // @[Mux.scala 27:72]
-  wire  _T_4521 = _T_2829 & _T_4207; // @[Mux.scala 27:72]
-  wire  _T_4522 = _T_4518 | _T_4519; // @[Mux.scala 27:72]
-  wire  _T_4523 = _T_4522 | _T_4520; // @[Mux.scala 27:72]
-  wire  lsu_nonblock_load_data_ready = _T_4523 | _T_4521; // @[Mux.scala 27:72]
-  wire  _T_4529 = buf_error[0] & _T_3637; // @[lsu_bus_buffer.scala 543:121]
-  wire  _T_4534 = buf_error[1] & _T_3827; // @[lsu_bus_buffer.scala 543:121]
-  wire  _T_4539 = buf_error[2] & _T_4017; // @[lsu_bus_buffer.scala 543:121]
-  wire  _T_4544 = buf_error[3] & _T_4207; // @[lsu_bus_buffer.scala 543:121]
-  wire  _T_4545 = _T_2763 & _T_4529; // @[Mux.scala 27:72]
-  wire  _T_4546 = _T_2785 & _T_4534; // @[Mux.scala 27:72]
-  wire  _T_4547 = _T_2807 & _T_4539; // @[Mux.scala 27:72]
-  wire  _T_4548 = _T_2829 & _T_4544; // @[Mux.scala 27:72]
-  wire  _T_4549 = _T_4545 | _T_4546; // @[Mux.scala 27:72]
-  wire  _T_4550 = _T_4549 | _T_4547; // @[Mux.scala 27:72]
-  wire  _T_4557 = ~buf_dual_0; // @[lsu_bus_buffer.scala 544:122]
-  wire  _T_4558 = ~buf_dualhi_0; // @[lsu_bus_buffer.scala 544:137]
-  wire  _T_4559 = _T_4557 | _T_4558; // @[lsu_bus_buffer.scala 544:135]
-  wire  _T_4560 = _T_4518 & _T_4559; // @[lsu_bus_buffer.scala 544:119]
-  wire  _T_4565 = ~buf_dual_1; // @[lsu_bus_buffer.scala 544:122]
-  wire  _T_4566 = ~buf_dualhi_1; // @[lsu_bus_buffer.scala 544:137]
-  wire  _T_4567 = _T_4565 | _T_4566; // @[lsu_bus_buffer.scala 544:135]
-  wire  _T_4568 = _T_4519 & _T_4567; // @[lsu_bus_buffer.scala 544:119]
-  wire  _T_4573 = ~buf_dual_2; // @[lsu_bus_buffer.scala 544:122]
-  wire  _T_4574 = ~buf_dualhi_2; // @[lsu_bus_buffer.scala 544:137]
-  wire  _T_4575 = _T_4573 | _T_4574; // @[lsu_bus_buffer.scala 544:135]
-  wire  _T_4576 = _T_4520 & _T_4575; // @[lsu_bus_buffer.scala 544:119]
-  wire  _T_4581 = ~buf_dual_3; // @[lsu_bus_buffer.scala 544:122]
-  wire  _T_4582 = ~buf_dualhi_3; // @[lsu_bus_buffer.scala 544:137]
-  wire  _T_4583 = _T_4581 | _T_4582; // @[lsu_bus_buffer.scala 544:135]
-  wire  _T_4584 = _T_4521 & _T_4583; // @[lsu_bus_buffer.scala 544:119]
-  wire [1:0] _T_4587 = _T_4576 ? 2'h2 : 2'h0; // @[Mux.scala 27:72]
-  wire [1:0] _T_4588 = _T_4584 ? 2'h3 : 2'h0; // @[Mux.scala 27:72]
-  wire [1:0] _GEN_395 = {{1'd0}, _T_4568}; // @[Mux.scala 27:72]
-  wire [1:0] _T_4590 = _GEN_395 | _T_4587; // @[Mux.scala 27:72]
-  wire [31:0] _T_4625 = _T_4560 ? buf_data_0 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_4626 = _T_4568 ? buf_data_1 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_4627 = _T_4576 ? buf_data_2 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_4628 = _T_4584 ? buf_data_3 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_4629 = _T_4625 | _T_4626; // @[Mux.scala 27:72]
-  wire [31:0] _T_4630 = _T_4629 | _T_4627; // @[Mux.scala 27:72]
-  wire [31:0] lsu_nonblock_load_data_lo = _T_4630 | _T_4628; // @[Mux.scala 27:72]
-  wire  _T_4637 = _T_4518 & _T_3635; // @[lsu_bus_buffer.scala 546:105]
-  wire  _T_4643 = _T_4519 & _T_3825; // @[lsu_bus_buffer.scala 546:105]
-  wire  _T_4649 = _T_4520 & _T_4015; // @[lsu_bus_buffer.scala 546:105]
-  wire  _T_4655 = _T_4521 & _T_4205; // @[lsu_bus_buffer.scala 546:105]
-  wire [31:0] _T_4656 = _T_4637 ? buf_data_0 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_4657 = _T_4643 ? buf_data_1 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_4658 = _T_4649 ? buf_data_2 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_4659 = _T_4655 ? buf_data_3 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_4660 = _T_4656 | _T_4657; // @[Mux.scala 27:72]
-  wire [31:0] _T_4661 = _T_4660 | _T_4658; // @[Mux.scala 27:72]
-  wire [31:0] lsu_nonblock_load_data_hi = _T_4661 | _T_4659; // @[Mux.scala 27:72]
-  wire  _T_4663 = io_dctl_busbuff_lsu_nonblock_load_data_tag == 2'h0; // @[lsu_bus_buffer.scala 61:123]
-  wire  _T_4664 = io_dctl_busbuff_lsu_nonblock_load_data_tag == 2'h1; // @[lsu_bus_buffer.scala 61:123]
-  wire  _T_4665 = io_dctl_busbuff_lsu_nonblock_load_data_tag == 2'h2; // @[lsu_bus_buffer.scala 61:123]
-  wire  _T_4666 = io_dctl_busbuff_lsu_nonblock_load_data_tag == 2'h3; // @[lsu_bus_buffer.scala 61:123]
-  wire [31:0] _T_4667 = _T_4663 ? buf_addr_0 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_4668 = _T_4664 ? buf_addr_1 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_4669 = _T_4665 ? buf_addr_2 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_4670 = _T_4666 ? buf_addr_3 : 32'h0; // @[Mux.scala 27:72]
+  wire [2:0] _GEN_388 = {{1'd0}, buf_dualtag_3}; // @[lsu_bus_buffer.scala 476:94]
+  wire  _T_4221 = io_lsu_axi_r_bits_id == _GEN_388; // @[lsu_bus_buffer.scala 476:94]
+  wire  _T_4222 = _T_4220 & _T_4221; // @[lsu_bus_buffer.scala 476:74]
+  wire  _T_4223 = _T_4215 | _T_4222; // @[lsu_bus_buffer.scala 475:71]
+  wire  _T_4224 = bus_rsp_read & _T_4223; // @[lsu_bus_buffer.scala 474:25]
+  wire  _T_4225 = _T_4210 | _T_4224; // @[lsu_bus_buffer.scala 473:105]
+  wire  _GEN_280 = _T_4165 & _T_4225; // @[Conditional.scala 39:67]
+  wire  _GEN_300 = _T_4131 ? 1'h0 : _GEN_280; // @[Conditional.scala 39:67]
+  wire  _GEN_312 = _T_4127 ? 1'h0 : _GEN_300; // @[Conditional.scala 39:67]
+  wire  buf_resp_state_bus_en_3 = _T_4104 ? 1'h0 : _GEN_312; // @[Conditional.scala 40:58]
+  wire [3:0] _T_4260 = buf_ldfwd >> buf_dualtag_3; // @[lsu_bus_buffer.scala 490:21]
+  wire  _T_4263 = _T_4260[0] & _T_1349; // @[lsu_bus_buffer.scala 490:38]
+  wire  _T_4264 = _T_4221 | _T_4263; // @[lsu_bus_buffer.scala 489:95]
+  wire  _T_4265 = bus_rsp_read & _T_4264; // @[lsu_bus_buffer.scala 489:45]
+  wire  _GEN_274 = _T_4250 & _T_4265; // @[Conditional.scala 39:67]
+  wire  _GEN_281 = _T_4165 ? buf_resp_state_bus_en_3 : _GEN_274; // @[Conditional.scala 39:67]
+  wire  _GEN_291 = _T_4131 ? 1'h0 : _GEN_281; // @[Conditional.scala 39:67]
+  wire  _GEN_305 = _T_4127 ? 1'h0 : _GEN_291; // @[Conditional.scala 39:67]
+  wire  buf_state_bus_en_3 = _T_4104 ? 1'h0 : _GEN_305; // @[Conditional.scala 40:58]
+  wire  _T_4144 = buf_state_bus_en_3 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 460:49]
+  wire  _T_4145 = _T_4144 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 460:70]
+  wire  _T_4271 = RspPtr == 2'h3; // @[lsu_bus_buffer.scala 497:37]
+  wire  _T_4272 = buf_dualtag_3 == RspPtr; // @[lsu_bus_buffer.scala 497:98]
+  wire  _T_4273 = buf_dual_3 & _T_4272; // @[lsu_bus_buffer.scala 497:80]
+  wire  _T_4274 = _T_4271 | _T_4273; // @[lsu_bus_buffer.scala 497:65]
+  wire  _T_4275 = _T_4274 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 497:112]
+  wire  _GEN_269 = _T_4268 ? _T_4275 : _T_4276; // @[Conditional.scala 39:67]
+  wire  _GEN_275 = _T_4250 ? _T_4145 : _GEN_269; // @[Conditional.scala 39:67]
+  wire  _GEN_282 = _T_4165 ? _T_4145 : _GEN_275; // @[Conditional.scala 39:67]
+  wire  _GEN_292 = _T_4131 ? _T_4145 : _GEN_282; // @[Conditional.scala 39:67]
+  wire  _GEN_302 = _T_4127 ? obuf_rdrsp_pend_en : _GEN_292; // @[Conditional.scala 39:67]
+  wire  buf_state_en_3 = _T_4104 ? _T_4120 : _GEN_302; // @[Conditional.scala 40:58]
+  wire  _T_2374 = _T_1825 & buf_state_en_3; // @[lsu_bus_buffer.scala 409:94]
+  wire  _T_2384 = _T_2076 & _T_1828; // @[lsu_bus_buffer.scala 411:71]
+  wire  _T_2386 = _T_2384 & _T_1793; // @[lsu_bus_buffer.scala 411:92]
+  wire  _T_2387 = _T_4466 | _T_2386; // @[lsu_bus_buffer.scala 410:86]
+  wire  _T_2391 = _T_2083 & _T_1829; // @[lsu_bus_buffer.scala 412:52]
+  wire  _T_2393 = _T_2391 & _T_1795; // @[lsu_bus_buffer.scala 412:73]
+  wire  _T_2394 = _T_2387 | _T_2393; // @[lsu_bus_buffer.scala 411:114]
+  wire  _T_2395 = _T_2374 & _T_2394; // @[lsu_bus_buffer.scala 409:113]
+  wire  _T_2397 = _T_2395 | buf_age_3[0]; // @[lsu_bus_buffer.scala 412:97]
+  wire  _T_2411 = _T_2384 & _T_1804; // @[lsu_bus_buffer.scala 411:92]
+  wire  _T_2412 = _T_4471 | _T_2411; // @[lsu_bus_buffer.scala 410:86]
+  wire  _T_2418 = _T_2391 & _T_1806; // @[lsu_bus_buffer.scala 412:73]
+  wire  _T_2419 = _T_2412 | _T_2418; // @[lsu_bus_buffer.scala 411:114]
+  wire  _T_2420 = _T_2374 & _T_2419; // @[lsu_bus_buffer.scala 409:113]
+  wire  _T_2422 = _T_2420 | buf_age_3[1]; // @[lsu_bus_buffer.scala 412:97]
+  wire  _T_2436 = _T_2384 & _T_1815; // @[lsu_bus_buffer.scala 411:92]
+  wire  _T_2437 = _T_4476 | _T_2436; // @[lsu_bus_buffer.scala 410:86]
+  wire  _T_2443 = _T_2391 & _T_1817; // @[lsu_bus_buffer.scala 412:73]
+  wire  _T_2444 = _T_2437 | _T_2443; // @[lsu_bus_buffer.scala 411:114]
+  wire  _T_2445 = _T_2374 & _T_2444; // @[lsu_bus_buffer.scala 409:113]
+  wire  _T_2447 = _T_2445 | buf_age_3[2]; // @[lsu_bus_buffer.scala 412:97]
+  wire  _T_2461 = _T_2384 & _T_1826; // @[lsu_bus_buffer.scala 411:92]
+  wire  _T_2462 = _T_4481 | _T_2461; // @[lsu_bus_buffer.scala 410:86]
+  wire  _T_2468 = _T_2391 & _T_1828; // @[lsu_bus_buffer.scala 412:73]
+  wire  _T_2469 = _T_2462 | _T_2468; // @[lsu_bus_buffer.scala 411:114]
+  wire  _T_2470 = _T_2374 & _T_2469; // @[lsu_bus_buffer.scala 409:113]
+  wire  _T_2472 = _T_2470 | buf_age_3[3]; // @[lsu_bus_buffer.scala 412:97]
+  wire [2:0] _T_2474 = {_T_2472,_T_2447,_T_2422}; // @[Cat.scala 29:58]
+  wire  _T_2770 = buf_state_0 == 3'h6; // @[lsu_bus_buffer.scala 420:47]
+  wire  _T_2771 = _T_1792 | _T_2770; // @[lsu_bus_buffer.scala 420:32]
+  wire  _T_2772 = ~_T_2771; // @[lsu_bus_buffer.scala 420:6]
+  wire  _T_2780 = _T_2772 | _T_2080; // @[lsu_bus_buffer.scala 420:59]
+  wire  _T_2787 = _T_2780 | _T_2087; // @[lsu_bus_buffer.scala 421:110]
+  wire  _T_2788 = _T_2068 & _T_2787; // @[lsu_bus_buffer.scala 419:112]
+  wire  _T_2792 = buf_state_1 == 3'h6; // @[lsu_bus_buffer.scala 420:47]
+  wire  _T_2793 = _T_1803 | _T_2792; // @[lsu_bus_buffer.scala 420:32]
+  wire  _T_2794 = ~_T_2793; // @[lsu_bus_buffer.scala 420:6]
+  wire  _T_2802 = _T_2794 | _T_2105; // @[lsu_bus_buffer.scala 420:59]
+  wire  _T_2809 = _T_2802 | _T_2112; // @[lsu_bus_buffer.scala 421:110]
+  wire  _T_2810 = _T_2068 & _T_2809; // @[lsu_bus_buffer.scala 419:112]
+  wire  _T_2814 = buf_state_2 == 3'h6; // @[lsu_bus_buffer.scala 420:47]
+  wire  _T_2815 = _T_1814 | _T_2814; // @[lsu_bus_buffer.scala 420:32]
+  wire  _T_2816 = ~_T_2815; // @[lsu_bus_buffer.scala 420:6]
+  wire  _T_2824 = _T_2816 | _T_2130; // @[lsu_bus_buffer.scala 420:59]
+  wire  _T_2831 = _T_2824 | _T_2137; // @[lsu_bus_buffer.scala 421:110]
+  wire  _T_2832 = _T_2068 & _T_2831; // @[lsu_bus_buffer.scala 419:112]
+  wire  _T_2836 = buf_state_3 == 3'h6; // @[lsu_bus_buffer.scala 420:47]
+  wire  _T_2837 = _T_1825 | _T_2836; // @[lsu_bus_buffer.scala 420:32]
+  wire  _T_2838 = ~_T_2837; // @[lsu_bus_buffer.scala 420:6]
+  wire  _T_2846 = _T_2838 | _T_2155; // @[lsu_bus_buffer.scala 420:59]
+  wire  _T_2853 = _T_2846 | _T_2162; // @[lsu_bus_buffer.scala 421:110]
+  wire  _T_2854 = _T_2068 & _T_2853; // @[lsu_bus_buffer.scala 419:112]
+  wire [3:0] buf_rspage_set_0 = {_T_2854,_T_2832,_T_2810,_T_2788}; // @[Cat.scala 29:58]
+  wire  _T_2871 = _T_2772 | _T_2182; // @[lsu_bus_buffer.scala 420:59]
+  wire  _T_2878 = _T_2871 | _T_2189; // @[lsu_bus_buffer.scala 421:110]
+  wire  _T_2879 = _T_2170 & _T_2878; // @[lsu_bus_buffer.scala 419:112]
+  wire  _T_2893 = _T_2794 | _T_2207; // @[lsu_bus_buffer.scala 420:59]
+  wire  _T_2900 = _T_2893 | _T_2214; // @[lsu_bus_buffer.scala 421:110]
+  wire  _T_2901 = _T_2170 & _T_2900; // @[lsu_bus_buffer.scala 419:112]
+  wire  _T_2915 = _T_2816 | _T_2232; // @[lsu_bus_buffer.scala 420:59]
+  wire  _T_2922 = _T_2915 | _T_2239; // @[lsu_bus_buffer.scala 421:110]
+  wire  _T_2923 = _T_2170 & _T_2922; // @[lsu_bus_buffer.scala 419:112]
+  wire  _T_2937 = _T_2838 | _T_2257; // @[lsu_bus_buffer.scala 420:59]
+  wire  _T_2944 = _T_2937 | _T_2264; // @[lsu_bus_buffer.scala 421:110]
+  wire  _T_2945 = _T_2170 & _T_2944; // @[lsu_bus_buffer.scala 419:112]
+  wire [3:0] buf_rspage_set_1 = {_T_2945,_T_2923,_T_2901,_T_2879}; // @[Cat.scala 29:58]
+  wire  _T_2962 = _T_2772 | _T_2284; // @[lsu_bus_buffer.scala 420:59]
+  wire  _T_2969 = _T_2962 | _T_2291; // @[lsu_bus_buffer.scala 421:110]
+  wire  _T_2970 = _T_2272 & _T_2969; // @[lsu_bus_buffer.scala 419:112]
+  wire  _T_2984 = _T_2794 | _T_2309; // @[lsu_bus_buffer.scala 420:59]
+  wire  _T_2991 = _T_2984 | _T_2316; // @[lsu_bus_buffer.scala 421:110]
+  wire  _T_2992 = _T_2272 & _T_2991; // @[lsu_bus_buffer.scala 419:112]
+  wire  _T_3006 = _T_2816 | _T_2334; // @[lsu_bus_buffer.scala 420:59]
+  wire  _T_3013 = _T_3006 | _T_2341; // @[lsu_bus_buffer.scala 421:110]
+  wire  _T_3014 = _T_2272 & _T_3013; // @[lsu_bus_buffer.scala 419:112]
+  wire  _T_3028 = _T_2838 | _T_2359; // @[lsu_bus_buffer.scala 420:59]
+  wire  _T_3035 = _T_3028 | _T_2366; // @[lsu_bus_buffer.scala 421:110]
+  wire  _T_3036 = _T_2272 & _T_3035; // @[lsu_bus_buffer.scala 419:112]
+  wire [3:0] buf_rspage_set_2 = {_T_3036,_T_3014,_T_2992,_T_2970}; // @[Cat.scala 29:58]
+  wire  _T_3053 = _T_2772 | _T_2386; // @[lsu_bus_buffer.scala 420:59]
+  wire  _T_3060 = _T_3053 | _T_2393; // @[lsu_bus_buffer.scala 421:110]
+  wire  _T_3061 = _T_2374 & _T_3060; // @[lsu_bus_buffer.scala 419:112]
+  wire  _T_3075 = _T_2794 | _T_2411; // @[lsu_bus_buffer.scala 420:59]
+  wire  _T_3082 = _T_3075 | _T_2418; // @[lsu_bus_buffer.scala 421:110]
+  wire  _T_3083 = _T_2374 & _T_3082; // @[lsu_bus_buffer.scala 419:112]
+  wire  _T_3097 = _T_2816 | _T_2436; // @[lsu_bus_buffer.scala 420:59]
+  wire  _T_3104 = _T_3097 | _T_2443; // @[lsu_bus_buffer.scala 421:110]
+  wire  _T_3105 = _T_2374 & _T_3104; // @[lsu_bus_buffer.scala 419:112]
+  wire  _T_3119 = _T_2838 | _T_2461; // @[lsu_bus_buffer.scala 420:59]
+  wire  _T_3126 = _T_3119 | _T_2468; // @[lsu_bus_buffer.scala 421:110]
+  wire  _T_3127 = _T_2374 & _T_3126; // @[lsu_bus_buffer.scala 419:112]
+  wire [3:0] buf_rspage_set_3 = {_T_3127,_T_3105,_T_3083,_T_3061}; // @[Cat.scala 29:58]
+  wire  _T_3218 = _T_2836 | _T_1825; // @[lsu_bus_buffer.scala 424:110]
+  wire  _T_3219 = ~_T_3218; // @[lsu_bus_buffer.scala 424:84]
+  wire  _T_3220 = buf_rspageQ_0[3] & _T_3219; // @[lsu_bus_buffer.scala 424:82]
+  wire  _T_3222 = _T_3220 & _T_2594; // @[lsu_bus_buffer.scala 424:136]
+  wire  _T_3210 = _T_2814 | _T_1814; // @[lsu_bus_buffer.scala 424:110]
+  wire  _T_3211 = ~_T_3210; // @[lsu_bus_buffer.scala 424:84]
+  wire  _T_3212 = buf_rspageQ_0[2] & _T_3211; // @[lsu_bus_buffer.scala 424:82]
+  wire  _T_3214 = _T_3212 & _T_2594; // @[lsu_bus_buffer.scala 424:136]
+  wire  _T_3202 = _T_2792 | _T_1803; // @[lsu_bus_buffer.scala 424:110]
+  wire  _T_3203 = ~_T_3202; // @[lsu_bus_buffer.scala 424:84]
+  wire  _T_3204 = buf_rspageQ_0[1] & _T_3203; // @[lsu_bus_buffer.scala 424:82]
+  wire  _T_3206 = _T_3204 & _T_2594; // @[lsu_bus_buffer.scala 424:136]
+  wire  _T_3194 = _T_2770 | _T_1792; // @[lsu_bus_buffer.scala 424:110]
+  wire  _T_3195 = ~_T_3194; // @[lsu_bus_buffer.scala 424:84]
+  wire  _T_3196 = buf_rspageQ_0[0] & _T_3195; // @[lsu_bus_buffer.scala 424:82]
+  wire  _T_3198 = _T_3196 & _T_2594; // @[lsu_bus_buffer.scala 424:136]
+  wire [3:0] buf_rspage_0 = {_T_3222,_T_3214,_T_3206,_T_3198}; // @[Cat.scala 29:58]
+  wire  _T_3133 = buf_rspage_set_0[0] | buf_rspage_0[0]; // @[lsu_bus_buffer.scala 423:88]
+  wire  _T_3136 = buf_rspage_set_0[1] | buf_rspage_0[1]; // @[lsu_bus_buffer.scala 423:88]
+  wire  _T_3139 = buf_rspage_set_0[2] | buf_rspage_0[2]; // @[lsu_bus_buffer.scala 423:88]
+  wire  _T_3142 = buf_rspage_set_0[3] | buf_rspage_0[3]; // @[lsu_bus_buffer.scala 423:88]
+  wire [2:0] _T_3144 = {_T_3142,_T_3139,_T_3136}; // @[Cat.scala 29:58]
+  wire  _T_3255 = buf_rspageQ_1[3] & _T_3219; // @[lsu_bus_buffer.scala 424:82]
+  wire  _T_3257 = _T_3255 & _T_2594; // @[lsu_bus_buffer.scala 424:136]
+  wire  _T_3247 = buf_rspageQ_1[2] & _T_3211; // @[lsu_bus_buffer.scala 424:82]
+  wire  _T_3249 = _T_3247 & _T_2594; // @[lsu_bus_buffer.scala 424:136]
+  wire  _T_3239 = buf_rspageQ_1[1] & _T_3203; // @[lsu_bus_buffer.scala 424:82]
+  wire  _T_3241 = _T_3239 & _T_2594; // @[lsu_bus_buffer.scala 424:136]
+  wire  _T_3231 = buf_rspageQ_1[0] & _T_3195; // @[lsu_bus_buffer.scala 424:82]
+  wire  _T_3233 = _T_3231 & _T_2594; // @[lsu_bus_buffer.scala 424:136]
+  wire [3:0] buf_rspage_1 = {_T_3257,_T_3249,_T_3241,_T_3233}; // @[Cat.scala 29:58]
+  wire  _T_3148 = buf_rspage_set_1[0] | buf_rspage_1[0]; // @[lsu_bus_buffer.scala 423:88]
+  wire  _T_3151 = buf_rspage_set_1[1] | buf_rspage_1[1]; // @[lsu_bus_buffer.scala 423:88]
+  wire  _T_3154 = buf_rspage_set_1[2] | buf_rspage_1[2]; // @[lsu_bus_buffer.scala 423:88]
+  wire  _T_3157 = buf_rspage_set_1[3] | buf_rspage_1[3]; // @[lsu_bus_buffer.scala 423:88]
+  wire [2:0] _T_3159 = {_T_3157,_T_3154,_T_3151}; // @[Cat.scala 29:58]
+  wire  _T_3290 = buf_rspageQ_2[3] & _T_3219; // @[lsu_bus_buffer.scala 424:82]
+  wire  _T_3292 = _T_3290 & _T_2594; // @[lsu_bus_buffer.scala 424:136]
+  wire  _T_3282 = buf_rspageQ_2[2] & _T_3211; // @[lsu_bus_buffer.scala 424:82]
+  wire  _T_3284 = _T_3282 & _T_2594; // @[lsu_bus_buffer.scala 424:136]
+  wire  _T_3274 = buf_rspageQ_2[1] & _T_3203; // @[lsu_bus_buffer.scala 424:82]
+  wire  _T_3276 = _T_3274 & _T_2594; // @[lsu_bus_buffer.scala 424:136]
+  wire  _T_3266 = buf_rspageQ_2[0] & _T_3195; // @[lsu_bus_buffer.scala 424:82]
+  wire  _T_3268 = _T_3266 & _T_2594; // @[lsu_bus_buffer.scala 424:136]
+  wire [3:0] buf_rspage_2 = {_T_3292,_T_3284,_T_3276,_T_3268}; // @[Cat.scala 29:58]
+  wire  _T_3163 = buf_rspage_set_2[0] | buf_rspage_2[0]; // @[lsu_bus_buffer.scala 423:88]
+  wire  _T_3166 = buf_rspage_set_2[1] | buf_rspage_2[1]; // @[lsu_bus_buffer.scala 423:88]
+  wire  _T_3169 = buf_rspage_set_2[2] | buf_rspage_2[2]; // @[lsu_bus_buffer.scala 423:88]
+  wire  _T_3172 = buf_rspage_set_2[3] | buf_rspage_2[3]; // @[lsu_bus_buffer.scala 423:88]
+  wire [2:0] _T_3174 = {_T_3172,_T_3169,_T_3166}; // @[Cat.scala 29:58]
+  wire  _T_3325 = buf_rspageQ_3[3] & _T_3219; // @[lsu_bus_buffer.scala 424:82]
+  wire  _T_3327 = _T_3325 & _T_2594; // @[lsu_bus_buffer.scala 424:136]
+  wire  _T_3317 = buf_rspageQ_3[2] & _T_3211; // @[lsu_bus_buffer.scala 424:82]
+  wire  _T_3319 = _T_3317 & _T_2594; // @[lsu_bus_buffer.scala 424:136]
+  wire  _T_3309 = buf_rspageQ_3[1] & _T_3203; // @[lsu_bus_buffer.scala 424:82]
+  wire  _T_3311 = _T_3309 & _T_2594; // @[lsu_bus_buffer.scala 424:136]
+  wire  _T_3301 = buf_rspageQ_3[0] & _T_3195; // @[lsu_bus_buffer.scala 424:82]
+  wire  _T_3303 = _T_3301 & _T_2594; // @[lsu_bus_buffer.scala 424:136]
+  wire [3:0] buf_rspage_3 = {_T_3327,_T_3319,_T_3311,_T_3303}; // @[Cat.scala 29:58]
+  wire  _T_3178 = buf_rspage_set_3[0] | buf_rspage_3[0]; // @[lsu_bus_buffer.scala 423:88]
+  wire  _T_3181 = buf_rspage_set_3[1] | buf_rspage_3[1]; // @[lsu_bus_buffer.scala 423:88]
+  wire  _T_3184 = buf_rspage_set_3[2] | buf_rspage_3[2]; // @[lsu_bus_buffer.scala 423:88]
+  wire  _T_3187 = buf_rspage_set_3[3] | buf_rspage_3[3]; // @[lsu_bus_buffer.scala 423:88]
+  wire [2:0] _T_3189 = {_T_3187,_T_3184,_T_3181}; // @[Cat.scala 29:58]
+  wire  _T_3332 = ibuf_drain_vld & _T_1793; // @[lsu_bus_buffer.scala 425:63]
+  wire  _T_3334 = ibuf_drain_vld & _T_1804; // @[lsu_bus_buffer.scala 425:63]
+  wire  _T_3336 = ibuf_drain_vld & _T_1815; // @[lsu_bus_buffer.scala 425:63]
+  wire  _T_3338 = ibuf_drain_vld & _T_1826; // @[lsu_bus_buffer.scala 425:63]
+  wire [3:0] ibuf_drainvec_vld = {_T_3338,_T_3336,_T_3334,_T_3332}; // @[Cat.scala 29:58]
+  wire  _T_3346 = _T_3540 & _T_1796; // @[lsu_bus_buffer.scala 427:35]
+  wire  _T_3355 = _T_3540 & _T_1807; // @[lsu_bus_buffer.scala 427:35]
+  wire  _T_3364 = _T_3540 & _T_1818; // @[lsu_bus_buffer.scala 427:35]
+  wire  _T_3373 = _T_3540 & _T_1829; // @[lsu_bus_buffer.scala 427:35]
+  wire  _T_3403 = ibuf_drainvec_vld[0] ? ibuf_dual : io_ldst_dual_r; // @[lsu_bus_buffer.scala 429:45]
+  wire  _T_3405 = ibuf_drainvec_vld[1] ? ibuf_dual : io_ldst_dual_r; // @[lsu_bus_buffer.scala 429:45]
+  wire  _T_3407 = ibuf_drainvec_vld[2] ? ibuf_dual : io_ldst_dual_r; // @[lsu_bus_buffer.scala 429:45]
+  wire  _T_3409 = ibuf_drainvec_vld[3] ? ibuf_dual : io_ldst_dual_r; // @[lsu_bus_buffer.scala 429:45]
+  wire [3:0] buf_dual_in = {_T_3409,_T_3407,_T_3405,_T_3403}; // @[Cat.scala 29:58]
+  wire  _T_3414 = ibuf_drainvec_vld[0] ? ibuf_samedw : ldst_samedw_r; // @[lsu_bus_buffer.scala 430:47]
+  wire  _T_3416 = ibuf_drainvec_vld[1] ? ibuf_samedw : ldst_samedw_r; // @[lsu_bus_buffer.scala 430:47]
+  wire  _T_3418 = ibuf_drainvec_vld[2] ? ibuf_samedw : ldst_samedw_r; // @[lsu_bus_buffer.scala 430:47]
+  wire  _T_3420 = ibuf_drainvec_vld[3] ? ibuf_samedw : ldst_samedw_r; // @[lsu_bus_buffer.scala 430:47]
+  wire [3:0] buf_samedw_in = {_T_3420,_T_3418,_T_3416,_T_3414}; // @[Cat.scala 29:58]
+  wire  _T_3425 = ibuf_nomerge | ibuf_force_drain; // @[lsu_bus_buffer.scala 431:84]
+  wire  _T_3426 = ibuf_drainvec_vld[0] ? _T_3425 : io_no_dword_merge_r; // @[lsu_bus_buffer.scala 431:48]
+  wire  _T_3429 = ibuf_drainvec_vld[1] ? _T_3425 : io_no_dword_merge_r; // @[lsu_bus_buffer.scala 431:48]
+  wire  _T_3432 = ibuf_drainvec_vld[2] ? _T_3425 : io_no_dword_merge_r; // @[lsu_bus_buffer.scala 431:48]
+  wire  _T_3435 = ibuf_drainvec_vld[3] ? _T_3425 : io_no_dword_merge_r; // @[lsu_bus_buffer.scala 431:48]
+  wire [3:0] buf_nomerge_in = {_T_3435,_T_3432,_T_3429,_T_3426}; // @[Cat.scala 29:58]
+  wire  _T_3443 = ibuf_drainvec_vld[0] ? ibuf_dual : _T_3346; // @[lsu_bus_buffer.scala 432:47]
+  wire  _T_3448 = ibuf_drainvec_vld[1] ? ibuf_dual : _T_3355; // @[lsu_bus_buffer.scala 432:47]
+  wire  _T_3453 = ibuf_drainvec_vld[2] ? ibuf_dual : _T_3364; // @[lsu_bus_buffer.scala 432:47]
+  wire  _T_3458 = ibuf_drainvec_vld[3] ? ibuf_dual : _T_3373; // @[lsu_bus_buffer.scala 432:47]
+  wire [3:0] buf_dualhi_in = {_T_3458,_T_3453,_T_3448,_T_3443}; // @[Cat.scala 29:58]
+  wire  _T_3487 = ibuf_drainvec_vld[0] ? ibuf_sideeffect : io_is_sideeffects_r; // @[lsu_bus_buffer.scala 434:51]
+  wire  _T_3489 = ibuf_drainvec_vld[1] ? ibuf_sideeffect : io_is_sideeffects_r; // @[lsu_bus_buffer.scala 434:51]
+  wire  _T_3491 = ibuf_drainvec_vld[2] ? ibuf_sideeffect : io_is_sideeffects_r; // @[lsu_bus_buffer.scala 434:51]
+  wire  _T_3493 = ibuf_drainvec_vld[3] ? ibuf_sideeffect : io_is_sideeffects_r; // @[lsu_bus_buffer.scala 434:51]
+  wire [3:0] buf_sideeffect_in = {_T_3493,_T_3491,_T_3489,_T_3487}; // @[Cat.scala 29:58]
+  wire  _T_3498 = ibuf_drainvec_vld[0] ? ibuf_unsign : io_lsu_pkt_r_bits_unsign; // @[lsu_bus_buffer.scala 435:47]
+  wire  _T_3500 = ibuf_drainvec_vld[1] ? ibuf_unsign : io_lsu_pkt_r_bits_unsign; // @[lsu_bus_buffer.scala 435:47]
+  wire  _T_3502 = ibuf_drainvec_vld[2] ? ibuf_unsign : io_lsu_pkt_r_bits_unsign; // @[lsu_bus_buffer.scala 435:47]
+  wire  _T_3504 = ibuf_drainvec_vld[3] ? ibuf_unsign : io_lsu_pkt_r_bits_unsign; // @[lsu_bus_buffer.scala 435:47]
+  wire [3:0] buf_unsign_in = {_T_3504,_T_3502,_T_3500,_T_3498}; // @[Cat.scala 29:58]
+  wire  _T_3521 = ibuf_drainvec_vld[0] ? ibuf_write : io_lsu_pkt_r_bits_store; // @[lsu_bus_buffer.scala 437:46]
+  wire  _T_3523 = ibuf_drainvec_vld[1] ? ibuf_write : io_lsu_pkt_r_bits_store; // @[lsu_bus_buffer.scala 437:46]
+  wire  _T_3525 = ibuf_drainvec_vld[2] ? ibuf_write : io_lsu_pkt_r_bits_store; // @[lsu_bus_buffer.scala 437:46]
+  wire  _T_3527 = ibuf_drainvec_vld[3] ? ibuf_write : io_lsu_pkt_r_bits_store; // @[lsu_bus_buffer.scala 437:46]
+  wire [3:0] buf_write_in = {_T_3527,_T_3525,_T_3523,_T_3521}; // @[Cat.scala 29:58]
+  wire  _T_3560 = obuf_nosend & bus_rsp_read; // @[lsu_bus_buffer.scala 457:89]
+  wire  _T_3562 = _T_3560 & _T_1349; // @[lsu_bus_buffer.scala 457:104]
+  wire  _T_3575 = buf_state_en_0 & _T_3645; // @[lsu_bus_buffer.scala 462:44]
+  wire  _T_3576 = _T_3575 & obuf_nosend; // @[lsu_bus_buffer.scala 462:60]
+  wire  _T_3578 = _T_3576 & _T_2594; // @[lsu_bus_buffer.scala 462:74]
+  wire  _T_3581 = _T_3571 & obuf_nosend; // @[lsu_bus_buffer.scala 464:67]
+  wire  _T_3582 = _T_3581 & bus_rsp_read; // @[lsu_bus_buffer.scala 464:81]
+  wire  _T_4841 = io_lsu_axi_r_bits_resp != 2'h0; // @[lsu_bus_buffer.scala 574:64]
+  wire  bus_rsp_read_error = bus_rsp_read & _T_4841; // @[lsu_bus_buffer.scala 574:38]
+  wire  _T_3585 = _T_3581 & bus_rsp_read_error; // @[lsu_bus_buffer.scala 465:82]
+  wire  _T_3659 = bus_rsp_read_error & _T_1349; // @[lsu_bus_buffer.scala 480:91]
+  wire  _T_3661 = bus_rsp_read_error & buf_ldfwd[0]; // @[lsu_bus_buffer.scala 481:31]
+  wire  _T_3663 = _T_3661 & _T_1349; // @[lsu_bus_buffer.scala 481:46]
+  wire  _T_3664 = _T_3659 | _T_3663; // @[lsu_bus_buffer.scala 480:143]
+  wire  _T_4839 = io_lsu_axi_b_bits_resp != 2'h0; // @[lsu_bus_buffer.scala 573:66]
+  wire  bus_rsp_write_error = bus_rsp_write & _T_4839; // @[lsu_bus_buffer.scala 573:40]
+  wire  _T_3666 = bus_rsp_write_error & _T_3636; // @[lsu_bus_buffer.scala 482:33]
+  wire  _T_3667 = _T_3664 | _T_3666; // @[lsu_bus_buffer.scala 481:88]
+  wire  _T_3668 = _T_3571 & _T_3667; // @[lsu_bus_buffer.scala 480:68]
+  wire  _GEN_56 = _T_3592 & _T_3668; // @[Conditional.scala 39:67]
+  wire  _GEN_69 = _T_3558 ? _T_3585 : _GEN_56; // @[Conditional.scala 39:67]
+  wire  _GEN_82 = _T_3554 ? 1'h0 : _GEN_69; // @[Conditional.scala 39:67]
+  wire  buf_error_en_0 = _T_3531 ? 1'h0 : _GEN_82; // @[Conditional.scala 40:58]
+  wire  _T_3594 = ~bus_rsp_write_error; // @[lsu_bus_buffer.scala 470:75]
+  wire  _T_3595 = buf_write[0] & _T_3594; // @[lsu_bus_buffer.scala 470:73]
+  wire  _T_3596 = io_dec_tlu_force_halt | _T_3595; // @[lsu_bus_buffer.scala 470:57]
+  wire  _T_3598 = ~buf_samedw_0; // @[lsu_bus_buffer.scala 471:30]
+  wire  _T_3599 = buf_dual_0 & _T_3598; // @[lsu_bus_buffer.scala 471:28]
+  wire  _T_3602 = _T_3599 & _T_3645; // @[lsu_bus_buffer.scala 471:45]
+  wire [2:0] _GEN_29 = 2'h1 == buf_dualtag_0 ? buf_state_1 : buf_state_0; // @[lsu_bus_buffer.scala 471:90]
+  wire [2:0] _GEN_30 = 2'h2 == buf_dualtag_0 ? buf_state_2 : _GEN_29; // @[lsu_bus_buffer.scala 471:90]
+  wire [2:0] _GEN_31 = 2'h3 == buf_dualtag_0 ? buf_state_3 : _GEN_30; // @[lsu_bus_buffer.scala 471:90]
+  wire  _T_3603 = _GEN_31 != 3'h4; // @[lsu_bus_buffer.scala 471:90]
+  wire  _T_3604 = _T_3602 & _T_3603; // @[lsu_bus_buffer.scala 471:61]
+  wire  _T_4489 = _T_2717 | _T_2714; // @[lsu_bus_buffer.scala 534:93]
+  wire  _T_4490 = _T_4489 | _T_2711; // @[lsu_bus_buffer.scala 534:93]
+  wire  any_done_wait_state = _T_4490 | _T_2708; // @[lsu_bus_buffer.scala 534:93]
+  wire  _T_3606 = buf_ldfwd[0] | any_done_wait_state; // @[lsu_bus_buffer.scala 472:31]
+  wire  _T_3612 = buf_dualtag_0 == 2'h0; // @[lsu_bus_buffer.scala 60:118]
+  wire  _T_3614 = buf_dualtag_0 == 2'h1; // @[lsu_bus_buffer.scala 60:118]
+  wire  _T_3616 = buf_dualtag_0 == 2'h2; // @[lsu_bus_buffer.scala 60:118]
+  wire  _T_3618 = buf_dualtag_0 == 2'h3; // @[lsu_bus_buffer.scala 60:118]
+  wire  _T_3620 = _T_3612 & buf_ldfwd[0]; // @[Mux.scala 27:72]
+  wire  _T_3621 = _T_3614 & buf_ldfwd[1]; // @[Mux.scala 27:72]
+  wire  _T_3622 = _T_3616 & buf_ldfwd[2]; // @[Mux.scala 27:72]
+  wire  _T_3623 = _T_3618 & buf_ldfwd[3]; // @[Mux.scala 27:72]
+  wire  _T_3624 = _T_3620 | _T_3621; // @[Mux.scala 27:72]
+  wire  _T_3625 = _T_3624 | _T_3622; // @[Mux.scala 27:72]
+  wire  _T_3626 = _T_3625 | _T_3623; // @[Mux.scala 27:72]
+  wire  _T_3628 = _T_3602 & _T_3626; // @[lsu_bus_buffer.scala 472:101]
+  wire  _T_3629 = _GEN_31 == 3'h4; // @[lsu_bus_buffer.scala 472:167]
+  wire  _T_3630 = _T_3628 & _T_3629; // @[lsu_bus_buffer.scala 472:138]
+  wire  _T_3631 = _T_3630 & any_done_wait_state; // @[lsu_bus_buffer.scala 472:187]
+  wire  _T_3632 = _T_3606 | _T_3631; // @[lsu_bus_buffer.scala 472:53]
+  wire  _T_3655 = buf_state_bus_en_0 & bus_rsp_read; // @[lsu_bus_buffer.scala 479:47]
+  wire  _T_3656 = _T_3655 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 479:62]
+  wire  _T_3669 = ~buf_error_en_0; // @[lsu_bus_buffer.scala 483:50]
+  wire  _T_3670 = buf_state_en_0 & _T_3669; // @[lsu_bus_buffer.scala 483:48]
+  wire  _T_3682 = buf_ldfwd[0] | _T_3687[0]; // @[lsu_bus_buffer.scala 488:90]
+  wire  _T_3683 = _T_3682 | any_done_wait_state; // @[lsu_bus_buffer.scala 488:118]
+  wire  _GEN_39 = _T_3703 ? buf_state_en_0 : io_dec_tlu_force_halt; // @[Conditional.scala 39:67]
+  wire  _GEN_43 = _T_3695 ? io_dec_tlu_force_halt : _T_3703; // @[Conditional.scala 39:67]
+  wire  _GEN_44 = _T_3695 ? io_dec_tlu_force_halt : _GEN_39; // @[Conditional.scala 39:67]
+  wire  _GEN_49 = _T_3677 ? io_dec_tlu_force_halt : _GEN_43; // @[Conditional.scala 39:67]
+  wire  _GEN_50 = _T_3677 ? io_dec_tlu_force_halt : _GEN_44; // @[Conditional.scala 39:67]
+  wire  _GEN_55 = _T_3592 & _T_3656; // @[Conditional.scala 39:67]
+  wire  _GEN_59 = _T_3592 ? io_dec_tlu_force_halt : _GEN_49; // @[Conditional.scala 39:67]
+  wire  _GEN_60 = _T_3592 ? io_dec_tlu_force_halt : _GEN_50; // @[Conditional.scala 39:67]
+  wire  _GEN_66 = _T_3558 ? _T_3578 : _GEN_60; // @[Conditional.scala 39:67]
+  wire  _GEN_68 = _T_3558 ? _T_3582 : _GEN_55; // @[Conditional.scala 39:67]
+  wire  _GEN_71 = _T_3558 ? io_dec_tlu_force_halt : _GEN_59; // @[Conditional.scala 39:67]
+  wire  _GEN_76 = _T_3554 ? io_dec_tlu_force_halt : _GEN_71; // @[Conditional.scala 39:67]
+  wire  _GEN_79 = _T_3554 ? io_dec_tlu_force_halt : _GEN_66; // @[Conditional.scala 39:67]
+  wire  _GEN_81 = _T_3554 ? 1'h0 : _GEN_68; // @[Conditional.scala 39:67]
+  wire  buf_wr_en_0 = _T_3531 & buf_state_en_0; // @[Conditional.scala 40:58]
+  wire  buf_data_en_0 = _T_3531 ? buf_state_en_0 : _GEN_81; // @[Conditional.scala 40:58]
+  wire  buf_rst_0 = _T_3531 ? io_dec_tlu_force_halt : _GEN_76; // @[Conditional.scala 40:58]
+  wire  buf_ldfwd_en_0 = _T_3531 ? io_dec_tlu_force_halt : _GEN_79; // @[Conditional.scala 40:58]
+  wire  _T_3766 = buf_state_en_1 & _T_3836; // @[lsu_bus_buffer.scala 462:44]
+  wire  _T_3767 = _T_3766 & obuf_nosend; // @[lsu_bus_buffer.scala 462:60]
+  wire  _T_3769 = _T_3767 & _T_2594; // @[lsu_bus_buffer.scala 462:74]
+  wire  _T_3772 = _T_3762 & obuf_nosend; // @[lsu_bus_buffer.scala 464:67]
+  wire  _T_3773 = _T_3772 & bus_rsp_read; // @[lsu_bus_buffer.scala 464:81]
+  wire  _T_3776 = _T_3772 & bus_rsp_read_error; // @[lsu_bus_buffer.scala 465:82]
+  wire  _T_3850 = bus_rsp_read_error & _T_3829; // @[lsu_bus_buffer.scala 480:91]
+  wire  _T_3852 = bus_rsp_read_error & buf_ldfwd[1]; // @[lsu_bus_buffer.scala 481:31]
+  wire  _T_3854 = _T_3852 & _T_1349; // @[lsu_bus_buffer.scala 481:46]
+  wire  _T_3855 = _T_3850 | _T_3854; // @[lsu_bus_buffer.scala 480:143]
+  wire  _T_3857 = bus_rsp_write_error & _T_3827; // @[lsu_bus_buffer.scala 482:33]
+  wire  _T_3858 = _T_3855 | _T_3857; // @[lsu_bus_buffer.scala 481:88]
+  wire  _T_3859 = _T_3762 & _T_3858; // @[lsu_bus_buffer.scala 480:68]
+  wire  _GEN_132 = _T_3783 & _T_3859; // @[Conditional.scala 39:67]
+  wire  _GEN_145 = _T_3749 ? _T_3776 : _GEN_132; // @[Conditional.scala 39:67]
+  wire  _GEN_158 = _T_3745 ? 1'h0 : _GEN_145; // @[Conditional.scala 39:67]
+  wire  buf_error_en_1 = _T_3722 ? 1'h0 : _GEN_158; // @[Conditional.scala 40:58]
+  wire  _T_3786 = buf_write[1] & _T_3594; // @[lsu_bus_buffer.scala 470:73]
+  wire  _T_3787 = io_dec_tlu_force_halt | _T_3786; // @[lsu_bus_buffer.scala 470:57]
+  wire  _T_3789 = ~buf_samedw_1; // @[lsu_bus_buffer.scala 471:30]
+  wire  _T_3790 = buf_dual_1 & _T_3789; // @[lsu_bus_buffer.scala 471:28]
+  wire  _T_3793 = _T_3790 & _T_3836; // @[lsu_bus_buffer.scala 471:45]
+  wire [2:0] _GEN_105 = 2'h1 == buf_dualtag_1 ? buf_state_1 : buf_state_0; // @[lsu_bus_buffer.scala 471:90]
+  wire [2:0] _GEN_106 = 2'h2 == buf_dualtag_1 ? buf_state_2 : _GEN_105; // @[lsu_bus_buffer.scala 471:90]
+  wire [2:0] _GEN_107 = 2'h3 == buf_dualtag_1 ? buf_state_3 : _GEN_106; // @[lsu_bus_buffer.scala 471:90]
+  wire  _T_3794 = _GEN_107 != 3'h4; // @[lsu_bus_buffer.scala 471:90]
+  wire  _T_3795 = _T_3793 & _T_3794; // @[lsu_bus_buffer.scala 471:61]
+  wire  _T_3797 = buf_ldfwd[1] | any_done_wait_state; // @[lsu_bus_buffer.scala 472:31]
+  wire  _T_3803 = buf_dualtag_1 == 2'h0; // @[lsu_bus_buffer.scala 60:118]
+  wire  _T_3805 = buf_dualtag_1 == 2'h1; // @[lsu_bus_buffer.scala 60:118]
+  wire  _T_3807 = buf_dualtag_1 == 2'h2; // @[lsu_bus_buffer.scala 60:118]
+  wire  _T_3809 = buf_dualtag_1 == 2'h3; // @[lsu_bus_buffer.scala 60:118]
+  wire  _T_3811 = _T_3803 & buf_ldfwd[0]; // @[Mux.scala 27:72]
+  wire  _T_3812 = _T_3805 & buf_ldfwd[1]; // @[Mux.scala 27:72]
+  wire  _T_3813 = _T_3807 & buf_ldfwd[2]; // @[Mux.scala 27:72]
+  wire  _T_3814 = _T_3809 & buf_ldfwd[3]; // @[Mux.scala 27:72]
+  wire  _T_3815 = _T_3811 | _T_3812; // @[Mux.scala 27:72]
+  wire  _T_3816 = _T_3815 | _T_3813; // @[Mux.scala 27:72]
+  wire  _T_3817 = _T_3816 | _T_3814; // @[Mux.scala 27:72]
+  wire  _T_3819 = _T_3793 & _T_3817; // @[lsu_bus_buffer.scala 472:101]
+  wire  _T_3820 = _GEN_107 == 3'h4; // @[lsu_bus_buffer.scala 472:167]
+  wire  _T_3821 = _T_3819 & _T_3820; // @[lsu_bus_buffer.scala 472:138]
+  wire  _T_3822 = _T_3821 & any_done_wait_state; // @[lsu_bus_buffer.scala 472:187]
+  wire  _T_3823 = _T_3797 | _T_3822; // @[lsu_bus_buffer.scala 472:53]
+  wire  _T_3846 = buf_state_bus_en_1 & bus_rsp_read; // @[lsu_bus_buffer.scala 479:47]
+  wire  _T_3847 = _T_3846 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 479:62]
+  wire  _T_3860 = ~buf_error_en_1; // @[lsu_bus_buffer.scala 483:50]
+  wire  _T_3861 = buf_state_en_1 & _T_3860; // @[lsu_bus_buffer.scala 483:48]
+  wire  _T_3873 = buf_ldfwd[1] | _T_3878[0]; // @[lsu_bus_buffer.scala 488:90]
+  wire  _T_3874 = _T_3873 | any_done_wait_state; // @[lsu_bus_buffer.scala 488:118]
+  wire  _GEN_115 = _T_3894 ? buf_state_en_1 : io_dec_tlu_force_halt; // @[Conditional.scala 39:67]
+  wire  _GEN_119 = _T_3886 ? io_dec_tlu_force_halt : _T_3894; // @[Conditional.scala 39:67]
+  wire  _GEN_120 = _T_3886 ? io_dec_tlu_force_halt : _GEN_115; // @[Conditional.scala 39:67]
+  wire  _GEN_125 = _T_3868 ? io_dec_tlu_force_halt : _GEN_119; // @[Conditional.scala 39:67]
+  wire  _GEN_126 = _T_3868 ? io_dec_tlu_force_halt : _GEN_120; // @[Conditional.scala 39:67]
+  wire  _GEN_131 = _T_3783 & _T_3847; // @[Conditional.scala 39:67]
+  wire  _GEN_135 = _T_3783 ? io_dec_tlu_force_halt : _GEN_125; // @[Conditional.scala 39:67]
+  wire  _GEN_136 = _T_3783 ? io_dec_tlu_force_halt : _GEN_126; // @[Conditional.scala 39:67]
+  wire  _GEN_142 = _T_3749 ? _T_3769 : _GEN_136; // @[Conditional.scala 39:67]
+  wire  _GEN_144 = _T_3749 ? _T_3773 : _GEN_131; // @[Conditional.scala 39:67]
+  wire  _GEN_147 = _T_3749 ? io_dec_tlu_force_halt : _GEN_135; // @[Conditional.scala 39:67]
+  wire  _GEN_152 = _T_3745 ? io_dec_tlu_force_halt : _GEN_147; // @[Conditional.scala 39:67]
+  wire  _GEN_155 = _T_3745 ? io_dec_tlu_force_halt : _GEN_142; // @[Conditional.scala 39:67]
+  wire  _GEN_157 = _T_3745 ? 1'h0 : _GEN_144; // @[Conditional.scala 39:67]
+  wire  buf_wr_en_1 = _T_3722 & buf_state_en_1; // @[Conditional.scala 40:58]
+  wire  buf_data_en_1 = _T_3722 ? buf_state_en_1 : _GEN_157; // @[Conditional.scala 40:58]
+  wire  buf_rst_1 = _T_3722 ? io_dec_tlu_force_halt : _GEN_152; // @[Conditional.scala 40:58]
+  wire  buf_ldfwd_en_1 = _T_3722 ? io_dec_tlu_force_halt : _GEN_155; // @[Conditional.scala 40:58]
+  wire  _T_3957 = buf_state_en_2 & _T_4027; // @[lsu_bus_buffer.scala 462:44]
+  wire  _T_3958 = _T_3957 & obuf_nosend; // @[lsu_bus_buffer.scala 462:60]
+  wire  _T_3960 = _T_3958 & _T_2594; // @[lsu_bus_buffer.scala 462:74]
+  wire  _T_3963 = _T_3953 & obuf_nosend; // @[lsu_bus_buffer.scala 464:67]
+  wire  _T_3964 = _T_3963 & bus_rsp_read; // @[lsu_bus_buffer.scala 464:81]
+  wire  _T_3967 = _T_3963 & bus_rsp_read_error; // @[lsu_bus_buffer.scala 465:82]
+  wire  _T_4041 = bus_rsp_read_error & _T_4020; // @[lsu_bus_buffer.scala 480:91]
+  wire  _T_4043 = bus_rsp_read_error & buf_ldfwd[2]; // @[lsu_bus_buffer.scala 481:31]
+  wire  _T_4045 = _T_4043 & _T_1349; // @[lsu_bus_buffer.scala 481:46]
+  wire  _T_4046 = _T_4041 | _T_4045; // @[lsu_bus_buffer.scala 480:143]
+  wire  _T_4048 = bus_rsp_write_error & _T_4018; // @[lsu_bus_buffer.scala 482:33]
+  wire  _T_4049 = _T_4046 | _T_4048; // @[lsu_bus_buffer.scala 481:88]
+  wire  _T_4050 = _T_3953 & _T_4049; // @[lsu_bus_buffer.scala 480:68]
+  wire  _GEN_208 = _T_3974 & _T_4050; // @[Conditional.scala 39:67]
+  wire  _GEN_221 = _T_3940 ? _T_3967 : _GEN_208; // @[Conditional.scala 39:67]
+  wire  _GEN_234 = _T_3936 ? 1'h0 : _GEN_221; // @[Conditional.scala 39:67]
+  wire  buf_error_en_2 = _T_3913 ? 1'h0 : _GEN_234; // @[Conditional.scala 40:58]
+  wire  _T_3977 = buf_write[2] & _T_3594; // @[lsu_bus_buffer.scala 470:73]
+  wire  _T_3978 = io_dec_tlu_force_halt | _T_3977; // @[lsu_bus_buffer.scala 470:57]
+  wire  _T_3980 = ~buf_samedw_2; // @[lsu_bus_buffer.scala 471:30]
+  wire  _T_3981 = buf_dual_2 & _T_3980; // @[lsu_bus_buffer.scala 471:28]
+  wire  _T_3984 = _T_3981 & _T_4027; // @[lsu_bus_buffer.scala 471:45]
+  wire [2:0] _GEN_181 = 2'h1 == buf_dualtag_2 ? buf_state_1 : buf_state_0; // @[lsu_bus_buffer.scala 471:90]
+  wire [2:0] _GEN_182 = 2'h2 == buf_dualtag_2 ? buf_state_2 : _GEN_181; // @[lsu_bus_buffer.scala 471:90]
+  wire [2:0] _GEN_183 = 2'h3 == buf_dualtag_2 ? buf_state_3 : _GEN_182; // @[lsu_bus_buffer.scala 471:90]
+  wire  _T_3985 = _GEN_183 != 3'h4; // @[lsu_bus_buffer.scala 471:90]
+  wire  _T_3986 = _T_3984 & _T_3985; // @[lsu_bus_buffer.scala 471:61]
+  wire  _T_3988 = buf_ldfwd[2] | any_done_wait_state; // @[lsu_bus_buffer.scala 472:31]
+  wire  _T_3994 = buf_dualtag_2 == 2'h0; // @[lsu_bus_buffer.scala 60:118]
+  wire  _T_3996 = buf_dualtag_2 == 2'h1; // @[lsu_bus_buffer.scala 60:118]
+  wire  _T_3998 = buf_dualtag_2 == 2'h2; // @[lsu_bus_buffer.scala 60:118]
+  wire  _T_4000 = buf_dualtag_2 == 2'h3; // @[lsu_bus_buffer.scala 60:118]
+  wire  _T_4002 = _T_3994 & buf_ldfwd[0]; // @[Mux.scala 27:72]
+  wire  _T_4003 = _T_3996 & buf_ldfwd[1]; // @[Mux.scala 27:72]
+  wire  _T_4004 = _T_3998 & buf_ldfwd[2]; // @[Mux.scala 27:72]
+  wire  _T_4005 = _T_4000 & buf_ldfwd[3]; // @[Mux.scala 27:72]
+  wire  _T_4006 = _T_4002 | _T_4003; // @[Mux.scala 27:72]
+  wire  _T_4007 = _T_4006 | _T_4004; // @[Mux.scala 27:72]
+  wire  _T_4008 = _T_4007 | _T_4005; // @[Mux.scala 27:72]
+  wire  _T_4010 = _T_3984 & _T_4008; // @[lsu_bus_buffer.scala 472:101]
+  wire  _T_4011 = _GEN_183 == 3'h4; // @[lsu_bus_buffer.scala 472:167]
+  wire  _T_4012 = _T_4010 & _T_4011; // @[lsu_bus_buffer.scala 472:138]
+  wire  _T_4013 = _T_4012 & any_done_wait_state; // @[lsu_bus_buffer.scala 472:187]
+  wire  _T_4014 = _T_3988 | _T_4013; // @[lsu_bus_buffer.scala 472:53]
+  wire  _T_4037 = buf_state_bus_en_2 & bus_rsp_read; // @[lsu_bus_buffer.scala 479:47]
+  wire  _T_4038 = _T_4037 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 479:62]
+  wire  _T_4051 = ~buf_error_en_2; // @[lsu_bus_buffer.scala 483:50]
+  wire  _T_4052 = buf_state_en_2 & _T_4051; // @[lsu_bus_buffer.scala 483:48]
+  wire  _T_4064 = buf_ldfwd[2] | _T_4069[0]; // @[lsu_bus_buffer.scala 488:90]
+  wire  _T_4065 = _T_4064 | any_done_wait_state; // @[lsu_bus_buffer.scala 488:118]
+  wire  _GEN_191 = _T_4085 ? buf_state_en_2 : io_dec_tlu_force_halt; // @[Conditional.scala 39:67]
+  wire  _GEN_195 = _T_4077 ? io_dec_tlu_force_halt : _T_4085; // @[Conditional.scala 39:67]
+  wire  _GEN_196 = _T_4077 ? io_dec_tlu_force_halt : _GEN_191; // @[Conditional.scala 39:67]
+  wire  _GEN_201 = _T_4059 ? io_dec_tlu_force_halt : _GEN_195; // @[Conditional.scala 39:67]
+  wire  _GEN_202 = _T_4059 ? io_dec_tlu_force_halt : _GEN_196; // @[Conditional.scala 39:67]
+  wire  _GEN_207 = _T_3974 & _T_4038; // @[Conditional.scala 39:67]
+  wire  _GEN_211 = _T_3974 ? io_dec_tlu_force_halt : _GEN_201; // @[Conditional.scala 39:67]
+  wire  _GEN_212 = _T_3974 ? io_dec_tlu_force_halt : _GEN_202; // @[Conditional.scala 39:67]
+  wire  _GEN_218 = _T_3940 ? _T_3960 : _GEN_212; // @[Conditional.scala 39:67]
+  wire  _GEN_220 = _T_3940 ? _T_3964 : _GEN_207; // @[Conditional.scala 39:67]
+  wire  _GEN_223 = _T_3940 ? io_dec_tlu_force_halt : _GEN_211; // @[Conditional.scala 39:67]
+  wire  _GEN_228 = _T_3936 ? io_dec_tlu_force_halt : _GEN_223; // @[Conditional.scala 39:67]
+  wire  _GEN_231 = _T_3936 ? io_dec_tlu_force_halt : _GEN_218; // @[Conditional.scala 39:67]
+  wire  _GEN_233 = _T_3936 ? 1'h0 : _GEN_220; // @[Conditional.scala 39:67]
+  wire  buf_wr_en_2 = _T_3913 & buf_state_en_2; // @[Conditional.scala 40:58]
+  wire  buf_data_en_2 = _T_3913 ? buf_state_en_2 : _GEN_233; // @[Conditional.scala 40:58]
+  wire  buf_rst_2 = _T_3913 ? io_dec_tlu_force_halt : _GEN_228; // @[Conditional.scala 40:58]
+  wire  buf_ldfwd_en_2 = _T_3913 ? io_dec_tlu_force_halt : _GEN_231; // @[Conditional.scala 40:58]
+  wire  _T_4148 = buf_state_en_3 & _T_4218; // @[lsu_bus_buffer.scala 462:44]
+  wire  _T_4149 = _T_4148 & obuf_nosend; // @[lsu_bus_buffer.scala 462:60]
+  wire  _T_4151 = _T_4149 & _T_2594; // @[lsu_bus_buffer.scala 462:74]
+  wire  _T_4154 = _T_4144 & obuf_nosend; // @[lsu_bus_buffer.scala 464:67]
+  wire  _T_4155 = _T_4154 & bus_rsp_read; // @[lsu_bus_buffer.scala 464:81]
+  wire  _T_4158 = _T_4154 & bus_rsp_read_error; // @[lsu_bus_buffer.scala 465:82]
+  wire  _T_4232 = bus_rsp_read_error & _T_4211; // @[lsu_bus_buffer.scala 480:91]
+  wire  _T_4234 = bus_rsp_read_error & buf_ldfwd[3]; // @[lsu_bus_buffer.scala 481:31]
+  wire  _T_4236 = _T_4234 & _T_1349; // @[lsu_bus_buffer.scala 481:46]
+  wire  _T_4237 = _T_4232 | _T_4236; // @[lsu_bus_buffer.scala 480:143]
+  wire  _T_4239 = bus_rsp_write_error & _T_4209; // @[lsu_bus_buffer.scala 482:33]
+  wire  _T_4240 = _T_4237 | _T_4239; // @[lsu_bus_buffer.scala 481:88]
+  wire  _T_4241 = _T_4144 & _T_4240; // @[lsu_bus_buffer.scala 480:68]
+  wire  _GEN_284 = _T_4165 & _T_4241; // @[Conditional.scala 39:67]
+  wire  _GEN_297 = _T_4131 ? _T_4158 : _GEN_284; // @[Conditional.scala 39:67]
+  wire  _GEN_310 = _T_4127 ? 1'h0 : _GEN_297; // @[Conditional.scala 39:67]
+  wire  buf_error_en_3 = _T_4104 ? 1'h0 : _GEN_310; // @[Conditional.scala 40:58]
+  wire  _T_4168 = buf_write[3] & _T_3594; // @[lsu_bus_buffer.scala 470:73]
+  wire  _T_4169 = io_dec_tlu_force_halt | _T_4168; // @[lsu_bus_buffer.scala 470:57]
+  wire  _T_4171 = ~buf_samedw_3; // @[lsu_bus_buffer.scala 471:30]
+  wire  _T_4172 = buf_dual_3 & _T_4171; // @[lsu_bus_buffer.scala 471:28]
+  wire  _T_4175 = _T_4172 & _T_4218; // @[lsu_bus_buffer.scala 471:45]
+  wire [2:0] _GEN_257 = 2'h1 == buf_dualtag_3 ? buf_state_1 : buf_state_0; // @[lsu_bus_buffer.scala 471:90]
+  wire [2:0] _GEN_258 = 2'h2 == buf_dualtag_3 ? buf_state_2 : _GEN_257; // @[lsu_bus_buffer.scala 471:90]
+  wire [2:0] _GEN_259 = 2'h3 == buf_dualtag_3 ? buf_state_3 : _GEN_258; // @[lsu_bus_buffer.scala 471:90]
+  wire  _T_4176 = _GEN_259 != 3'h4; // @[lsu_bus_buffer.scala 471:90]
+  wire  _T_4177 = _T_4175 & _T_4176; // @[lsu_bus_buffer.scala 471:61]
+  wire  _T_4179 = buf_ldfwd[3] | any_done_wait_state; // @[lsu_bus_buffer.scala 472:31]
+  wire  _T_4185 = buf_dualtag_3 == 2'h0; // @[lsu_bus_buffer.scala 60:118]
+  wire  _T_4187 = buf_dualtag_3 == 2'h1; // @[lsu_bus_buffer.scala 60:118]
+  wire  _T_4189 = buf_dualtag_3 == 2'h2; // @[lsu_bus_buffer.scala 60:118]
+  wire  _T_4191 = buf_dualtag_3 == 2'h3; // @[lsu_bus_buffer.scala 60:118]
+  wire  _T_4193 = _T_4185 & buf_ldfwd[0]; // @[Mux.scala 27:72]
+  wire  _T_4194 = _T_4187 & buf_ldfwd[1]; // @[Mux.scala 27:72]
+  wire  _T_4195 = _T_4189 & buf_ldfwd[2]; // @[Mux.scala 27:72]
+  wire  _T_4196 = _T_4191 & buf_ldfwd[3]; // @[Mux.scala 27:72]
+  wire  _T_4197 = _T_4193 | _T_4194; // @[Mux.scala 27:72]
+  wire  _T_4198 = _T_4197 | _T_4195; // @[Mux.scala 27:72]
+  wire  _T_4199 = _T_4198 | _T_4196; // @[Mux.scala 27:72]
+  wire  _T_4201 = _T_4175 & _T_4199; // @[lsu_bus_buffer.scala 472:101]
+  wire  _T_4202 = _GEN_259 == 3'h4; // @[lsu_bus_buffer.scala 472:167]
+  wire  _T_4203 = _T_4201 & _T_4202; // @[lsu_bus_buffer.scala 472:138]
+  wire  _T_4204 = _T_4203 & any_done_wait_state; // @[lsu_bus_buffer.scala 472:187]
+  wire  _T_4205 = _T_4179 | _T_4204; // @[lsu_bus_buffer.scala 472:53]
+  wire  _T_4228 = buf_state_bus_en_3 & bus_rsp_read; // @[lsu_bus_buffer.scala 479:47]
+  wire  _T_4229 = _T_4228 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 479:62]
+  wire  _T_4242 = ~buf_error_en_3; // @[lsu_bus_buffer.scala 483:50]
+  wire  _T_4243 = buf_state_en_3 & _T_4242; // @[lsu_bus_buffer.scala 483:48]
+  wire  _T_4255 = buf_ldfwd[3] | _T_4260[0]; // @[lsu_bus_buffer.scala 488:90]
+  wire  _T_4256 = _T_4255 | any_done_wait_state; // @[lsu_bus_buffer.scala 488:118]
+  wire  _GEN_267 = _T_4276 ? buf_state_en_3 : io_dec_tlu_force_halt; // @[Conditional.scala 39:67]
+  wire  _GEN_271 = _T_4268 ? io_dec_tlu_force_halt : _T_4276; // @[Conditional.scala 39:67]
+  wire  _GEN_272 = _T_4268 ? io_dec_tlu_force_halt : _GEN_267; // @[Conditional.scala 39:67]
+  wire  _GEN_277 = _T_4250 ? io_dec_tlu_force_halt : _GEN_271; // @[Conditional.scala 39:67]
+  wire  _GEN_278 = _T_4250 ? io_dec_tlu_force_halt : _GEN_272; // @[Conditional.scala 39:67]
+  wire  _GEN_283 = _T_4165 & _T_4229; // @[Conditional.scala 39:67]
+  wire  _GEN_287 = _T_4165 ? io_dec_tlu_force_halt : _GEN_277; // @[Conditional.scala 39:67]
+  wire  _GEN_288 = _T_4165 ? io_dec_tlu_force_halt : _GEN_278; // @[Conditional.scala 39:67]
+  wire  _GEN_294 = _T_4131 ? _T_4151 : _GEN_288; // @[Conditional.scala 39:67]
+  wire  _GEN_296 = _T_4131 ? _T_4155 : _GEN_283; // @[Conditional.scala 39:67]
+  wire  _GEN_299 = _T_4131 ? io_dec_tlu_force_halt : _GEN_287; // @[Conditional.scala 39:67]
+  wire  _GEN_304 = _T_4127 ? io_dec_tlu_force_halt : _GEN_299; // @[Conditional.scala 39:67]
+  wire  _GEN_307 = _T_4127 ? io_dec_tlu_force_halt : _GEN_294; // @[Conditional.scala 39:67]
+  wire  _GEN_309 = _T_4127 ? 1'h0 : _GEN_296; // @[Conditional.scala 39:67]
+  wire  buf_wr_en_3 = _T_4104 & buf_state_en_3; // @[Conditional.scala 40:58]
+  wire  buf_data_en_3 = _T_4104 ? buf_state_en_3 : _GEN_309; // @[Conditional.scala 40:58]
+  wire  buf_rst_3 = _T_4104 ? io_dec_tlu_force_halt : _GEN_304; // @[Conditional.scala 40:58]
+  wire  buf_ldfwd_en_3 = _T_4104 ? io_dec_tlu_force_halt : _GEN_307; // @[Conditional.scala 40:58]
+  reg  _T_4331; // @[Reg.scala 27:20]
+  reg  _T_4334; // @[Reg.scala 27:20]
+  reg  _T_4337; // @[Reg.scala 27:20]
+  reg  _T_4340; // @[Reg.scala 27:20]
+  wire [3:0] buf_unsign = {_T_4340,_T_4337,_T_4334,_T_4331}; // @[Cat.scala 29:58]
+  wire  _T_4387 = ~buf_rst_0; // @[lsu_bus_buffer.scala 529:81]
+  reg  _T_4406; // @[lsu_bus_buffer.scala 529:80]
+  reg  _T_4401; // @[lsu_bus_buffer.scala 529:80]
+  reg  _T_4396; // @[lsu_bus_buffer.scala 529:80]
+  reg  _T_4391; // @[lsu_bus_buffer.scala 529:80]
+  wire [3:0] buf_error = {_T_4406,_T_4401,_T_4396,_T_4391}; // @[Cat.scala 29:58]
+  wire  _T_4389 = buf_error_en_0 | buf_error[0]; // @[lsu_bus_buffer.scala 529:98]
+  wire  _T_4392 = ~buf_rst_1; // @[lsu_bus_buffer.scala 529:81]
+  wire  _T_4394 = buf_error_en_1 | buf_error[1]; // @[lsu_bus_buffer.scala 529:98]
+  wire  _T_4397 = ~buf_rst_2; // @[lsu_bus_buffer.scala 529:81]
+  wire  _T_4399 = buf_error_en_2 | buf_error[2]; // @[lsu_bus_buffer.scala 529:98]
+  wire  _T_4402 = ~buf_rst_3; // @[lsu_bus_buffer.scala 529:81]
+  wire  _T_4404 = buf_error_en_3 | buf_error[3]; // @[lsu_bus_buffer.scala 529:98]
+  wire [1:0] _T_4410 = {io_lsu_busreq_m,1'h0}; // @[Cat.scala 29:58]
+  wire [1:0] _T_4411 = io_ldst_dual_m ? _T_4410 : {{1'd0}, io_lsu_busreq_m}; // @[lsu_bus_buffer.scala 530:28]
+  wire [1:0] _T_4412 = {io_lsu_busreq_r,1'h0}; // @[Cat.scala 29:58]
+  wire [1:0] _T_4413 = io_ldst_dual_r ? _T_4412 : {{1'd0}, io_lsu_busreq_r}; // @[lsu_bus_buffer.scala 530:94]
+  wire [2:0] _T_4414 = _T_4411 + _T_4413; // @[lsu_bus_buffer.scala 530:88]
+  wire [2:0] _GEN_390 = {{2'd0}, ibuf_valid}; // @[lsu_bus_buffer.scala 530:154]
+  wire [3:0] _T_4415 = _T_4414 + _GEN_390; // @[lsu_bus_buffer.scala 530:154]
+  wire [1:0] _T_4420 = _T_5 + _T_12; // @[lsu_bus_buffer.scala 530:217]
+  wire [1:0] _GEN_391 = {{1'd0}, _T_19}; // @[lsu_bus_buffer.scala 530:217]
+  wire [2:0] _T_4421 = _T_4420 + _GEN_391; // @[lsu_bus_buffer.scala 530:217]
+  wire [2:0] _GEN_392 = {{2'd0}, _T_26}; // @[lsu_bus_buffer.scala 530:217]
+  wire [3:0] _T_4422 = _T_4421 + _GEN_392; // @[lsu_bus_buffer.scala 530:217]
+  wire [3:0] buf_numvld_any = _T_4415 + _T_4422; // @[lsu_bus_buffer.scala 530:169]
+  wire  _T_4493 = io_ldst_dual_d & io_dec_lsu_valid_raw_d; // @[lsu_bus_buffer.scala 536:52]
+  wire  _T_4494 = buf_numvld_any >= 4'h3; // @[lsu_bus_buffer.scala 536:92]
+  wire  _T_4495 = buf_numvld_any == 4'h4; // @[lsu_bus_buffer.scala 536:121]
+  wire  _T_4497 = |buf_state_0; // @[lsu_bus_buffer.scala 537:52]
+  wire  _T_4498 = |buf_state_1; // @[lsu_bus_buffer.scala 537:52]
+  wire  _T_4499 = |buf_state_2; // @[lsu_bus_buffer.scala 537:52]
+  wire  _T_4500 = |buf_state_3; // @[lsu_bus_buffer.scala 537:52]
+  wire  _T_4501 = _T_4497 | _T_4498; // @[lsu_bus_buffer.scala 537:65]
+  wire  _T_4502 = _T_4501 | _T_4499; // @[lsu_bus_buffer.scala 537:65]
+  wire  _T_4503 = _T_4502 | _T_4500; // @[lsu_bus_buffer.scala 537:65]
+  wire  _T_4504 = ~_T_4503; // @[lsu_bus_buffer.scala 537:34]
+  wire  _T_4506 = _T_4504 & _T_852; // @[lsu_bus_buffer.scala 537:70]
+  wire  _T_4509 = io_lsu_busreq_m & io_lsu_pkt_m_valid; // @[lsu_bus_buffer.scala 539:64]
+  wire  _T_4510 = _T_4509 & io_lsu_pkt_m_bits_load; // @[lsu_bus_buffer.scala 539:85]
+  wire  _T_4511 = ~io_flush_m_up; // @[lsu_bus_buffer.scala 539:112]
+  wire  _T_4512 = _T_4510 & _T_4511; // @[lsu_bus_buffer.scala 539:110]
+  wire  _T_4513 = ~io_ld_full_hit_m; // @[lsu_bus_buffer.scala 539:129]
+  wire  _T_4515 = ~io_lsu_commit_r; // @[lsu_bus_buffer.scala 542:74]
+  reg  lsu_nonblock_load_valid_r; // @[lsu_bus_buffer.scala 627:66]
+  wire  _T_4529 = _T_2770 & _T_3645; // @[Mux.scala 27:72]
+  wire  _T_4530 = _T_2792 & _T_3836; // @[Mux.scala 27:72]
+  wire  _T_4531 = _T_2814 & _T_4027; // @[Mux.scala 27:72]
+  wire  _T_4532 = _T_2836 & _T_4218; // @[Mux.scala 27:72]
+  wire  _T_4533 = _T_4529 | _T_4530; // @[Mux.scala 27:72]
+  wire  _T_4534 = _T_4533 | _T_4531; // @[Mux.scala 27:72]
+  wire  lsu_nonblock_load_data_ready = _T_4534 | _T_4532; // @[Mux.scala 27:72]
+  wire  _T_4540 = buf_error[0] & _T_3645; // @[lsu_bus_buffer.scala 545:121]
+  wire  _T_4545 = buf_error[1] & _T_3836; // @[lsu_bus_buffer.scala 545:121]
+  wire  _T_4550 = buf_error[2] & _T_4027; // @[lsu_bus_buffer.scala 545:121]
+  wire  _T_4555 = buf_error[3] & _T_4218; // @[lsu_bus_buffer.scala 545:121]
+  wire  _T_4556 = _T_2770 & _T_4540; // @[Mux.scala 27:72]
+  wire  _T_4557 = _T_2792 & _T_4545; // @[Mux.scala 27:72]
+  wire  _T_4558 = _T_2814 & _T_4550; // @[Mux.scala 27:72]
+  wire  _T_4559 = _T_2836 & _T_4555; // @[Mux.scala 27:72]
+  wire  _T_4560 = _T_4556 | _T_4557; // @[Mux.scala 27:72]
+  wire  _T_4561 = _T_4560 | _T_4558; // @[Mux.scala 27:72]
+  wire  _T_4568 = ~buf_dual_0; // @[lsu_bus_buffer.scala 546:121]
+  wire  _T_4569 = ~buf_dualhi_0; // @[lsu_bus_buffer.scala 546:136]
+  wire  _T_4570 = _T_4568 | _T_4569; // @[lsu_bus_buffer.scala 546:134]
+  wire  _T_4571 = _T_4529 & _T_4570; // @[lsu_bus_buffer.scala 546:118]
+  wire  _T_4576 = ~buf_dual_1; // @[lsu_bus_buffer.scala 546:121]
+  wire  _T_4577 = ~buf_dualhi_1; // @[lsu_bus_buffer.scala 546:136]
+  wire  _T_4578 = _T_4576 | _T_4577; // @[lsu_bus_buffer.scala 546:134]
+  wire  _T_4579 = _T_4530 & _T_4578; // @[lsu_bus_buffer.scala 546:118]
+  wire  _T_4584 = ~buf_dual_2; // @[lsu_bus_buffer.scala 546:121]
+  wire  _T_4585 = ~buf_dualhi_2; // @[lsu_bus_buffer.scala 546:136]
+  wire  _T_4586 = _T_4584 | _T_4585; // @[lsu_bus_buffer.scala 546:134]
+  wire  _T_4587 = _T_4531 & _T_4586; // @[lsu_bus_buffer.scala 546:118]
+  wire  _T_4592 = ~buf_dual_3; // @[lsu_bus_buffer.scala 546:121]
+  wire  _T_4593 = ~buf_dualhi_3; // @[lsu_bus_buffer.scala 546:136]
+  wire  _T_4594 = _T_4592 | _T_4593; // @[lsu_bus_buffer.scala 546:134]
+  wire  _T_4595 = _T_4532 & _T_4594; // @[lsu_bus_buffer.scala 546:118]
+  wire [1:0] _T_4598 = _T_4587 ? 2'h2 : 2'h0; // @[Mux.scala 27:72]
+  wire [1:0] _T_4599 = _T_4595 ? 2'h3 : 2'h0; // @[Mux.scala 27:72]
+  wire [1:0] _GEN_393 = {{1'd0}, _T_4579}; // @[Mux.scala 27:72]
+  wire [1:0] _T_4601 = _GEN_393 | _T_4598; // @[Mux.scala 27:72]
+  wire [31:0] _T_4636 = _T_4571 ? buf_data_0 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_4637 = _T_4579 ? buf_data_1 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_4638 = _T_4587 ? buf_data_2 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_4639 = _T_4595 ? buf_data_3 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_4640 = _T_4636 | _T_4637; // @[Mux.scala 27:72]
+  wire [31:0] _T_4641 = _T_4640 | _T_4638; // @[Mux.scala 27:72]
+  wire [31:0] lsu_nonblock_load_data_lo = _T_4641 | _T_4639; // @[Mux.scala 27:72]
+  wire  _T_4648 = _T_4529 & _T_3643; // @[lsu_bus_buffer.scala 548:105]
+  wire  _T_4654 = _T_4530 & _T_3834; // @[lsu_bus_buffer.scala 548:105]
+  wire  _T_4660 = _T_4531 & _T_4025; // @[lsu_bus_buffer.scala 548:105]
+  wire  _T_4666 = _T_4532 & _T_4216; // @[lsu_bus_buffer.scala 548:105]
+  wire [31:0] _T_4667 = _T_4648 ? buf_data_0 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_4668 = _T_4654 ? buf_data_1 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_4669 = _T_4660 ? buf_data_2 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_4670 = _T_4666 ? buf_data_3 : 32'h0; // @[Mux.scala 27:72]
   wire [31:0] _T_4671 = _T_4667 | _T_4668; // @[Mux.scala 27:72]
   wire [31:0] _T_4672 = _T_4671 | _T_4669; // @[Mux.scala 27:72]
-  wire [31:0] _T_4673 = _T_4672 | _T_4670; // @[Mux.scala 27:72]
-  wire [1:0] lsu_nonblock_addr_offset = _T_4673[1:0]; // @[lsu_bus_buffer.scala 547:96]
-  wire [1:0] _T_4679 = _T_4663 ? buf_sz_0 : 2'h0; // @[Mux.scala 27:72]
-  wire [1:0] _T_4680 = _T_4664 ? buf_sz_1 : 2'h0; // @[Mux.scala 27:72]
-  wire [1:0] _T_4681 = _T_4665 ? buf_sz_2 : 2'h0; // @[Mux.scala 27:72]
-  wire [1:0] _T_4682 = _T_4666 ? buf_sz_3 : 2'h0; // @[Mux.scala 27:72]
-  wire [1:0] _T_4683 = _T_4679 | _T_4680; // @[Mux.scala 27:72]
-  wire [1:0] _T_4684 = _T_4683 | _T_4681; // @[Mux.scala 27:72]
-  wire [1:0] lsu_nonblock_sz = _T_4684 | _T_4682; // @[Mux.scala 27:72]
-  wire  _T_4694 = _T_4663 & buf_unsign[0]; // @[Mux.scala 27:72]
-  wire  _T_4695 = _T_4664 & buf_unsign[1]; // @[Mux.scala 27:72]
-  wire  _T_4696 = _T_4665 & buf_unsign[2]; // @[Mux.scala 27:72]
-  wire  _T_4697 = _T_4666 & buf_unsign[3]; // @[Mux.scala 27:72]
-  wire  _T_4698 = _T_4694 | _T_4695; // @[Mux.scala 27:72]
-  wire  _T_4699 = _T_4698 | _T_4696; // @[Mux.scala 27:72]
-  wire  lsu_nonblock_unsign = _T_4699 | _T_4697; // @[Mux.scala 27:72]
-  wire [63:0] _T_4701 = {lsu_nonblock_load_data_hi,lsu_nonblock_load_data_lo}; // @[Cat.scala 29:58]
-  wire [3:0] _GEN_396 = {{2'd0}, lsu_nonblock_addr_offset}; // @[lsu_bus_buffer.scala 551:121]
-  wire [5:0] _T_4702 = _GEN_396 * 4'h8; // @[lsu_bus_buffer.scala 551:121]
-  wire [63:0] lsu_nonblock_data_unalgn = _T_4701 >> _T_4702; // @[lsu_bus_buffer.scala 551:92]
-  wire  _T_4703 = ~io_dctl_busbuff_lsu_nonblock_load_data_error; // @[lsu_bus_buffer.scala 553:82]
-  wire  _T_4705 = lsu_nonblock_sz == 2'h0; // @[lsu_bus_buffer.scala 554:94]
-  wire  _T_4706 = lsu_nonblock_unsign & _T_4705; // @[lsu_bus_buffer.scala 554:76]
-  wire [31:0] _T_4708 = {24'h0,lsu_nonblock_data_unalgn[7:0]}; // @[Cat.scala 29:58]
-  wire  _T_4709 = lsu_nonblock_sz == 2'h1; // @[lsu_bus_buffer.scala 555:45]
-  wire  _T_4710 = lsu_nonblock_unsign & _T_4709; // @[lsu_bus_buffer.scala 555:26]
-  wire [31:0] _T_4712 = {16'h0,lsu_nonblock_data_unalgn[15:0]}; // @[Cat.scala 29:58]
-  wire  _T_4713 = ~lsu_nonblock_unsign; // @[lsu_bus_buffer.scala 556:6]
-  wire  _T_4715 = _T_4713 & _T_4705; // @[lsu_bus_buffer.scala 556:27]
-  wire [23:0] _T_4718 = lsu_nonblock_data_unalgn[7] ? 24'hffffff : 24'h0; // @[Bitwise.scala 72:12]
-  wire [31:0] _T_4720 = {_T_4718,lsu_nonblock_data_unalgn[7:0]}; // @[Cat.scala 29:58]
-  wire  _T_4723 = _T_4713 & _T_4709; // @[lsu_bus_buffer.scala 557:27]
-  wire [15:0] _T_4726 = lsu_nonblock_data_unalgn[15] ? 16'hffff : 16'h0; // @[Bitwise.scala 72:12]
-  wire [31:0] _T_4728 = {_T_4726,lsu_nonblock_data_unalgn[15:0]}; // @[Cat.scala 29:58]
-  wire  _T_4729 = lsu_nonblock_sz == 2'h2; // @[lsu_bus_buffer.scala 558:21]
-  wire [31:0] _T_4730 = _T_4706 ? _T_4708 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_4731 = _T_4710 ? _T_4712 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_4732 = _T_4715 ? _T_4720 : 32'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_4733 = _T_4723 ? _T_4728 : 32'h0; // @[Mux.scala 27:72]
-  wire [63:0] _T_4734 = _T_4729 ? lsu_nonblock_data_unalgn : 64'h0; // @[Mux.scala 27:72]
-  wire [31:0] _T_4735 = _T_4730 | _T_4731; // @[Mux.scala 27:72]
-  wire [31:0] _T_4736 = _T_4735 | _T_4732; // @[Mux.scala 27:72]
-  wire [31:0] _T_4737 = _T_4736 | _T_4733; // @[Mux.scala 27:72]
-  wire [63:0] _GEN_397 = {{32'd0}, _T_4737}; // @[Mux.scala 27:72]
-  wire [63:0] _T_4738 = _GEN_397 | _T_4734; // @[Mux.scala 27:72]
-  wire  _T_4832 = obuf_valid & obuf_write; // @[lsu_bus_buffer.scala 576:37]
-  wire  _T_4833 = ~obuf_cmd_done; // @[lsu_bus_buffer.scala 576:52]
-  wire  _T_4834 = _T_4832 & _T_4833; // @[lsu_bus_buffer.scala 576:50]
-  wire [31:0] _T_4838 = {obuf_addr[31:3],3'h0}; // @[Cat.scala 29:58]
-  wire [2:0] _T_4840 = {1'h0,obuf_sz}; // @[Cat.scala 29:58]
-  wire  _T_4845 = ~obuf_data_done; // @[lsu_bus_buffer.scala 588:51]
-  wire  _T_4846 = _T_4832 & _T_4845; // @[lsu_bus_buffer.scala 588:49]
-  wire [7:0] _T_4850 = obuf_write ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
-  wire  _T_4853 = obuf_valid & _T_1341; // @[lsu_bus_buffer.scala 593:37]
-  wire  _T_4855 = _T_4853 & _T_1347; // @[lsu_bus_buffer.scala 593:51]
-  wire  _T_4867 = io_lsu_bus_clk_en_q & buf_error[0]; // @[lsu_bus_buffer.scala 606:126]
-  wire  _T_4869 = _T_4867 & buf_write[0]; // @[lsu_bus_buffer.scala 606:141]
-  wire  _T_4872 = io_lsu_bus_clk_en_q & buf_error[1]; // @[lsu_bus_buffer.scala 606:126]
-  wire  _T_4874 = _T_4872 & buf_write[1]; // @[lsu_bus_buffer.scala 606:141]
-  wire  _T_4877 = io_lsu_bus_clk_en_q & buf_error[2]; // @[lsu_bus_buffer.scala 606:126]
-  wire  _T_4879 = _T_4877 & buf_write[2]; // @[lsu_bus_buffer.scala 606:141]
-  wire  _T_4882 = io_lsu_bus_clk_en_q & buf_error[3]; // @[lsu_bus_buffer.scala 606:126]
-  wire  _T_4884 = _T_4882 & buf_write[3]; // @[lsu_bus_buffer.scala 606:141]
-  wire  _T_4885 = _T_2763 & _T_4869; // @[Mux.scala 27:72]
-  wire  _T_4886 = _T_2785 & _T_4874; // @[Mux.scala 27:72]
-  wire  _T_4887 = _T_2807 & _T_4879; // @[Mux.scala 27:72]
-  wire  _T_4888 = _T_2829 & _T_4884; // @[Mux.scala 27:72]
-  wire  _T_4889 = _T_4885 | _T_4886; // @[Mux.scala 27:72]
-  wire  _T_4890 = _T_4889 | _T_4887; // @[Mux.scala 27:72]
-  wire  _T_4900 = _T_2785 & buf_error[1]; // @[lsu_bus_buffer.scala 607:93]
-  wire  _T_4902 = _T_4900 & buf_write[1]; // @[lsu_bus_buffer.scala 607:108]
-  wire  _T_4905 = _T_2807 & buf_error[2]; // @[lsu_bus_buffer.scala 607:93]
-  wire  _T_4907 = _T_4905 & buf_write[2]; // @[lsu_bus_buffer.scala 607:108]
-  wire  _T_4910 = _T_2829 & buf_error[3]; // @[lsu_bus_buffer.scala 607:93]
-  wire  _T_4912 = _T_4910 & buf_write[3]; // @[lsu_bus_buffer.scala 607:108]
-  wire [1:0] _T_4915 = _T_4907 ? 2'h2 : 2'h0; // @[Mux.scala 27:72]
-  wire [1:0] _T_4916 = _T_4912 ? 2'h3 : 2'h0; // @[Mux.scala 27:72]
-  wire [1:0] _GEN_398 = {{1'd0}, _T_4902}; // @[Mux.scala 27:72]
-  wire [1:0] _T_4918 = _GEN_398 | _T_4915; // @[Mux.scala 27:72]
-  wire [1:0] lsu_imprecise_error_store_tag = _T_4918 | _T_4916; // @[Mux.scala 27:72]
-  wire  _T_4920 = ~io_tlu_busbuff_lsu_imprecise_error_store_any; // @[lsu_bus_buffer.scala 609:97]
-  wire [31:0] _GEN_355 = 2'h1 == lsu_imprecise_error_store_tag ? buf_addr_1 : buf_addr_0; // @[lsu_bus_buffer.scala 610:53]
-  wire [31:0] _GEN_356 = 2'h2 == lsu_imprecise_error_store_tag ? buf_addr_2 : _GEN_355; // @[lsu_bus_buffer.scala 610:53]
-  wire [31:0] _GEN_357 = 2'h3 == lsu_imprecise_error_store_tag ? buf_addr_3 : _GEN_356; // @[lsu_bus_buffer.scala 610:53]
-  wire [31:0] _GEN_359 = 2'h1 == io_dctl_busbuff_lsu_nonblock_load_data_tag ? buf_addr_1 : buf_addr_0; // @[lsu_bus_buffer.scala 610:53]
-  wire [31:0] _GEN_360 = 2'h2 == io_dctl_busbuff_lsu_nonblock_load_data_tag ? buf_addr_2 : _GEN_359; // @[lsu_bus_buffer.scala 610:53]
-  wire [31:0] _GEN_361 = 2'h3 == io_dctl_busbuff_lsu_nonblock_load_data_tag ? buf_addr_3 : _GEN_360; // @[lsu_bus_buffer.scala 610:53]
-  wire  _T_4925 = bus_wcmd_sent | bus_wdata_sent; // @[lsu_bus_buffer.scala 616:82]
-  wire  _T_4928 = io_lsu_busreq_r & io_ldst_dual_r; // @[lsu_bus_buffer.scala 617:60]
-  wire  _T_4931 = ~io_lsu_axi_aw_ready; // @[lsu_bus_buffer.scala 620:61]
-  wire  _T_4932 = io_lsu_axi_aw_valid & _T_4931; // @[lsu_bus_buffer.scala 620:59]
-  wire  _T_4933 = ~io_lsu_axi_w_ready; // @[lsu_bus_buffer.scala 620:107]
-  wire  _T_4934 = io_lsu_axi_w_valid & _T_4933; // @[lsu_bus_buffer.scala 620:105]
-  wire  _T_4935 = _T_4932 | _T_4934; // @[lsu_bus_buffer.scala 620:83]
-  wire  _T_4936 = ~io_lsu_axi_ar_ready; // @[lsu_bus_buffer.scala 620:153]
-  wire  _T_4937 = io_lsu_axi_ar_valid & _T_4936; // @[lsu_bus_buffer.scala 620:151]
-  wire  _T_4941 = ~io_flush_r; // @[lsu_bus_buffer.scala 624:75]
-  wire  _T_4942 = io_lsu_busreq_m & _T_4941; // @[lsu_bus_buffer.scala 624:73]
-  reg  _T_4945; // @[lsu_bus_buffer.scala 624:56]
-  rvclkhdr rvclkhdr ( // @[lib.scala 368:23]
+  wire [31:0] lsu_nonblock_load_data_hi = _T_4672 | _T_4670; // @[Mux.scala 27:72]
+  wire  _T_4674 = io_dctl_busbuff_lsu_nonblock_load_data_tag == 2'h0; // @[lsu_bus_buffer.scala 61:123]
+  wire  _T_4675 = io_dctl_busbuff_lsu_nonblock_load_data_tag == 2'h1; // @[lsu_bus_buffer.scala 61:123]
+  wire  _T_4676 = io_dctl_busbuff_lsu_nonblock_load_data_tag == 2'h2; // @[lsu_bus_buffer.scala 61:123]
+  wire  _T_4677 = io_dctl_busbuff_lsu_nonblock_load_data_tag == 2'h3; // @[lsu_bus_buffer.scala 61:123]
+  wire [31:0] _T_4678 = _T_4674 ? buf_addr_0 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_4679 = _T_4675 ? buf_addr_1 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_4680 = _T_4676 ? buf_addr_2 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_4681 = _T_4677 ? buf_addr_3 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_4682 = _T_4678 | _T_4679; // @[Mux.scala 27:72]
+  wire [31:0] _T_4683 = _T_4682 | _T_4680; // @[Mux.scala 27:72]
+  wire [31:0] _T_4684 = _T_4683 | _T_4681; // @[Mux.scala 27:72]
+  wire [1:0] lsu_nonblock_addr_offset = _T_4684[1:0]; // @[lsu_bus_buffer.scala 549:96]
+  wire [1:0] _T_4690 = _T_4674 ? buf_sz_0 : 2'h0; // @[Mux.scala 27:72]
+  wire [1:0] _T_4691 = _T_4675 ? buf_sz_1 : 2'h0; // @[Mux.scala 27:72]
+  wire [1:0] _T_4692 = _T_4676 ? buf_sz_2 : 2'h0; // @[Mux.scala 27:72]
+  wire [1:0] _T_4693 = _T_4677 ? buf_sz_3 : 2'h0; // @[Mux.scala 27:72]
+  wire [1:0] _T_4694 = _T_4690 | _T_4691; // @[Mux.scala 27:72]
+  wire [1:0] _T_4695 = _T_4694 | _T_4692; // @[Mux.scala 27:72]
+  wire [1:0] lsu_nonblock_sz = _T_4695 | _T_4693; // @[Mux.scala 27:72]
+  wire  _T_4705 = _T_4674 & buf_unsign[0]; // @[Mux.scala 27:72]
+  wire  _T_4706 = _T_4675 & buf_unsign[1]; // @[Mux.scala 27:72]
+  wire  _T_4707 = _T_4676 & buf_unsign[2]; // @[Mux.scala 27:72]
+  wire  _T_4708 = _T_4677 & buf_unsign[3]; // @[Mux.scala 27:72]
+  wire  _T_4709 = _T_4705 | _T_4706; // @[Mux.scala 27:72]
+  wire  _T_4710 = _T_4709 | _T_4707; // @[Mux.scala 27:72]
+  wire  lsu_nonblock_unsign = _T_4710 | _T_4708; // @[Mux.scala 27:72]
+  wire [63:0] _T_4712 = {lsu_nonblock_load_data_hi,lsu_nonblock_load_data_lo}; // @[Cat.scala 29:58]
+  wire [3:0] _GEN_394 = {{2'd0}, lsu_nonblock_addr_offset}; // @[lsu_bus_buffer.scala 553:121]
+  wire [5:0] _T_4713 = _GEN_394 * 4'h8; // @[lsu_bus_buffer.scala 553:121]
+  wire [63:0] lsu_nonblock_data_unalgn = _T_4712 >> _T_4713; // @[lsu_bus_buffer.scala 553:92]
+  wire  _T_4714 = ~io_dctl_busbuff_lsu_nonblock_load_data_error; // @[lsu_bus_buffer.scala 555:82]
+  wire  _T_4716 = lsu_nonblock_sz == 2'h0; // @[lsu_bus_buffer.scala 556:94]
+  wire  _T_4717 = lsu_nonblock_unsign & _T_4716; // @[lsu_bus_buffer.scala 556:76]
+  wire [31:0] _T_4719 = {24'h0,lsu_nonblock_data_unalgn[7:0]}; // @[Cat.scala 29:58]
+  wire  _T_4720 = lsu_nonblock_sz == 2'h1; // @[lsu_bus_buffer.scala 557:45]
+  wire  _T_4721 = lsu_nonblock_unsign & _T_4720; // @[lsu_bus_buffer.scala 557:26]
+  wire [31:0] _T_4723 = {16'h0,lsu_nonblock_data_unalgn[15:0]}; // @[Cat.scala 29:58]
+  wire  _T_4724 = ~lsu_nonblock_unsign; // @[lsu_bus_buffer.scala 558:6]
+  wire  _T_4726 = _T_4724 & _T_4716; // @[lsu_bus_buffer.scala 558:27]
+  wire [23:0] _T_4729 = lsu_nonblock_data_unalgn[7] ? 24'hffffff : 24'h0; // @[Bitwise.scala 72:12]
+  wire [31:0] _T_4731 = {_T_4729,lsu_nonblock_data_unalgn[7:0]}; // @[Cat.scala 29:58]
+  wire  _T_4734 = _T_4724 & _T_4720; // @[lsu_bus_buffer.scala 559:27]
+  wire [15:0] _T_4737 = lsu_nonblock_data_unalgn[15] ? 16'hffff : 16'h0; // @[Bitwise.scala 72:12]
+  wire [31:0] _T_4739 = {_T_4737,lsu_nonblock_data_unalgn[15:0]}; // @[Cat.scala 29:58]
+  wire  _T_4740 = lsu_nonblock_sz == 2'h2; // @[lsu_bus_buffer.scala 560:21]
+  wire [31:0] _T_4741 = _T_4717 ? _T_4719 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_4742 = _T_4721 ? _T_4723 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_4743 = _T_4726 ? _T_4731 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_4744 = _T_4734 ? _T_4739 : 32'h0; // @[Mux.scala 27:72]
+  wire [63:0] _T_4745 = _T_4740 ? lsu_nonblock_data_unalgn : 64'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_4746 = _T_4741 | _T_4742; // @[Mux.scala 27:72]
+  wire [31:0] _T_4747 = _T_4746 | _T_4743; // @[Mux.scala 27:72]
+  wire [31:0] _T_4748 = _T_4747 | _T_4744; // @[Mux.scala 27:72]
+  wire [63:0] _GEN_395 = {{32'd0}, _T_4748}; // @[Mux.scala 27:72]
+  wire [63:0] _T_4749 = _GEN_395 | _T_4745; // @[Mux.scala 27:72]
+  wire  _T_4878 = io_lsu_bus_clk_en_q & buf_error[0]; // @[lsu_bus_buffer.scala 608:126]
+  wire  _T_4880 = _T_4878 & buf_write[0]; // @[lsu_bus_buffer.scala 608:141]
+  wire  _T_4883 = io_lsu_bus_clk_en_q & buf_error[1]; // @[lsu_bus_buffer.scala 608:126]
+  wire  _T_4885 = _T_4883 & buf_write[1]; // @[lsu_bus_buffer.scala 608:141]
+  wire  _T_4888 = io_lsu_bus_clk_en_q & buf_error[2]; // @[lsu_bus_buffer.scala 608:126]
+  wire  _T_4890 = _T_4888 & buf_write[2]; // @[lsu_bus_buffer.scala 608:141]
+  wire  _T_4893 = io_lsu_bus_clk_en_q & buf_error[3]; // @[lsu_bus_buffer.scala 608:126]
+  wire  _T_4895 = _T_4893 & buf_write[3]; // @[lsu_bus_buffer.scala 608:141]
+  wire  _T_4896 = _T_2770 & _T_4880; // @[Mux.scala 27:72]
+  wire  _T_4897 = _T_2792 & _T_4885; // @[Mux.scala 27:72]
+  wire  _T_4898 = _T_2814 & _T_4890; // @[Mux.scala 27:72]
+  wire  _T_4899 = _T_2836 & _T_4895; // @[Mux.scala 27:72]
+  wire  _T_4900 = _T_4896 | _T_4897; // @[Mux.scala 27:72]
+  wire  _T_4901 = _T_4900 | _T_4898; // @[Mux.scala 27:72]
+  wire  _T_4911 = _T_2792 & buf_error[1]; // @[lsu_bus_buffer.scala 609:93]
+  wire  _T_4913 = _T_4911 & buf_write[1]; // @[lsu_bus_buffer.scala 609:108]
+  wire  _T_4916 = _T_2814 & buf_error[2]; // @[lsu_bus_buffer.scala 609:93]
+  wire  _T_4918 = _T_4916 & buf_write[2]; // @[lsu_bus_buffer.scala 609:108]
+  wire  _T_4921 = _T_2836 & buf_error[3]; // @[lsu_bus_buffer.scala 609:93]
+  wire  _T_4923 = _T_4921 & buf_write[3]; // @[lsu_bus_buffer.scala 609:108]
+  wire [1:0] _T_4926 = _T_4918 ? 2'h2 : 2'h0; // @[Mux.scala 27:72]
+  wire [1:0] _T_4927 = _T_4923 ? 2'h3 : 2'h0; // @[Mux.scala 27:72]
+  wire [1:0] _GEN_396 = {{1'd0}, _T_4913}; // @[Mux.scala 27:72]
+  wire [1:0] _T_4929 = _GEN_396 | _T_4926; // @[Mux.scala 27:72]
+  wire [1:0] lsu_imprecise_error_store_tag = _T_4929 | _T_4927; // @[Mux.scala 27:72]
+  wire  _T_4931 = ~io_tlu_busbuff_lsu_imprecise_error_store_any; // @[lsu_bus_buffer.scala 611:97]
+  wire [31:0] _GEN_369 = 2'h1 == lsu_imprecise_error_store_tag ? buf_addr_1 : buf_addr_0; // @[lsu_bus_buffer.scala 612:53]
+  wire [31:0] _GEN_370 = 2'h2 == lsu_imprecise_error_store_tag ? buf_addr_2 : _GEN_369; // @[lsu_bus_buffer.scala 612:53]
+  wire [31:0] _GEN_371 = 2'h3 == lsu_imprecise_error_store_tag ? buf_addr_3 : _GEN_370; // @[lsu_bus_buffer.scala 612:53]
+  wire [31:0] _GEN_373 = 2'h1 == io_dctl_busbuff_lsu_nonblock_load_data_tag ? buf_addr_1 : buf_addr_0; // @[lsu_bus_buffer.scala 612:53]
+  wire [31:0] _GEN_374 = 2'h2 == io_dctl_busbuff_lsu_nonblock_load_data_tag ? buf_addr_2 : _GEN_373; // @[lsu_bus_buffer.scala 612:53]
+  wire [31:0] _GEN_375 = 2'h3 == io_dctl_busbuff_lsu_nonblock_load_data_tag ? buf_addr_3 : _GEN_374; // @[lsu_bus_buffer.scala 612:53]
+  wire  _T_4936 = bus_wcmd_sent | bus_wdata_sent; // @[lsu_bus_buffer.scala 618:82]
+  wire  _T_4939 = io_lsu_busreq_r & io_ldst_dual_r; // @[lsu_bus_buffer.scala 619:60]
+  wire  _T_4942 = ~io_lsu_axi_aw_ready; // @[lsu_bus_buffer.scala 622:61]
+  wire  _T_4943 = io_lsu_axi_aw_valid & _T_4942; // @[lsu_bus_buffer.scala 622:59]
+  wire  _T_4944 = ~io_lsu_axi_w_ready; // @[lsu_bus_buffer.scala 622:107]
+  wire  _T_4945 = io_lsu_axi_w_valid & _T_4944; // @[lsu_bus_buffer.scala 622:105]
+  wire  _T_4946 = _T_4943 | _T_4945; // @[lsu_bus_buffer.scala 622:83]
+  wire  _T_4947 = ~io_lsu_axi_ar_ready; // @[lsu_bus_buffer.scala 622:153]
+  wire  _T_4948 = io_lsu_axi_ar_valid & _T_4947; // @[lsu_bus_buffer.scala 622:151]
+  wire  _T_4952 = ~io_flush_r; // @[lsu_bus_buffer.scala 626:75]
+  wire  _T_4953 = io_lsu_busreq_m & _T_4952; // @[lsu_bus_buffer.scala 626:73]
+  reg  _T_4956; // @[lsu_bus_buffer.scala 626:56]
+  rvclkhdr rvclkhdr ( // @[lib.scala 390:23]
     .io_l1clk(rvclkhdr_io_l1clk),
     .io_clk(rvclkhdr_io_clk),
-    .io_en(rvclkhdr_io_en),
-    .io_scan_mode(rvclkhdr_io_scan_mode)
+    .io_en(rvclkhdr_io_en)
   );
-  rvclkhdr rvclkhdr_1 ( // @[lib.scala 368:23]
+  rvclkhdr rvclkhdr_1 ( // @[lib.scala 390:23]
     .io_l1clk(rvclkhdr_1_io_l1clk),
     .io_clk(rvclkhdr_1_io_clk),
-    .io_en(rvclkhdr_1_io_en),
-    .io_scan_mode(rvclkhdr_1_io_scan_mode)
+    .io_en(rvclkhdr_1_io_en)
   );
-  rvclkhdr rvclkhdr_2 ( // @[lib.scala 368:23]
+  rvclkhdr rvclkhdr_2 ( // @[lib.scala 390:23]
     .io_l1clk(rvclkhdr_2_io_l1clk),
     .io_clk(rvclkhdr_2_io_clk),
-    .io_en(rvclkhdr_2_io_en),
-    .io_scan_mode(rvclkhdr_2_io_scan_mode)
+    .io_en(rvclkhdr_2_io_en)
   );
-  rvclkhdr rvclkhdr_3 ( // @[lib.scala 368:23]
+  rvclkhdr rvclkhdr_3 ( // @[lib.scala 390:23]
     .io_l1clk(rvclkhdr_3_io_l1clk),
     .io_clk(rvclkhdr_3_io_clk),
-    .io_en(rvclkhdr_3_io_en),
-    .io_scan_mode(rvclkhdr_3_io_scan_mode)
+    .io_en(rvclkhdr_3_io_en)
   );
-  rvclkhdr rvclkhdr_4 ( // @[lib.scala 368:23]
+  rvclkhdr rvclkhdr_4 ( // @[lib.scala 390:23]
     .io_l1clk(rvclkhdr_4_io_l1clk),
     .io_clk(rvclkhdr_4_io_clk),
-    .io_en(rvclkhdr_4_io_en),
-    .io_scan_mode(rvclkhdr_4_io_scan_mode)
+    .io_en(rvclkhdr_4_io_en)
   );
-  rvclkhdr rvclkhdr_5 ( // @[lib.scala 368:23]
+  rvclkhdr rvclkhdr_5 ( // @[lib.scala 390:23]
     .io_l1clk(rvclkhdr_5_io_l1clk),
     .io_clk(rvclkhdr_5_io_clk),
-    .io_en(rvclkhdr_5_io_en),
-    .io_scan_mode(rvclkhdr_5_io_scan_mode)
+    .io_en(rvclkhdr_5_io_en)
   );
-  rvclkhdr rvclkhdr_6 ( // @[lib.scala 368:23]
+  rvclkhdr rvclkhdr_6 ( // @[lib.scala 390:23]
     .io_l1clk(rvclkhdr_6_io_l1clk),
     .io_clk(rvclkhdr_6_io_clk),
-    .io_en(rvclkhdr_6_io_en),
-    .io_scan_mode(rvclkhdr_6_io_scan_mode)
+    .io_en(rvclkhdr_6_io_en)
   );
-  rvclkhdr rvclkhdr_7 ( // @[lib.scala 368:23]
+  rvclkhdr rvclkhdr_7 ( // @[lib.scala 390:23]
     .io_l1clk(rvclkhdr_7_io_l1clk),
     .io_clk(rvclkhdr_7_io_clk),
-    .io_en(rvclkhdr_7_io_en),
-    .io_scan_mode(rvclkhdr_7_io_scan_mode)
+    .io_en(rvclkhdr_7_io_en)
   );
-  rvclkhdr rvclkhdr_8 ( // @[lib.scala 368:23]
+  rvclkhdr rvclkhdr_8 ( // @[lib.scala 390:23]
     .io_l1clk(rvclkhdr_8_io_l1clk),
     .io_clk(rvclkhdr_8_io_clk),
-    .io_en(rvclkhdr_8_io_en),
-    .io_scan_mode(rvclkhdr_8_io_scan_mode)
+    .io_en(rvclkhdr_8_io_en)
   );
-  rvclkhdr rvclkhdr_9 ( // @[lib.scala 368:23]
+  rvclkhdr rvclkhdr_9 ( // @[lib.scala 390:23]
     .io_l1clk(rvclkhdr_9_io_l1clk),
     .io_clk(rvclkhdr_9_io_clk),
-    .io_en(rvclkhdr_9_io_en),
-    .io_scan_mode(rvclkhdr_9_io_scan_mode)
+    .io_en(rvclkhdr_9_io_en)
   );
-  rvclkhdr rvclkhdr_10 ( // @[lib.scala 368:23]
+  rvclkhdr rvclkhdr_10 ( // @[lib.scala 390:23]
     .io_l1clk(rvclkhdr_10_io_l1clk),
     .io_clk(rvclkhdr_10_io_clk),
-    .io_en(rvclkhdr_10_io_en),
-    .io_scan_mode(rvclkhdr_10_io_scan_mode)
+    .io_en(rvclkhdr_10_io_en)
   );
-  rvclkhdr rvclkhdr_11 ( // @[lib.scala 368:23]
+  rvclkhdr rvclkhdr_11 ( // @[lib.scala 390:23]
     .io_l1clk(rvclkhdr_11_io_l1clk),
     .io_clk(rvclkhdr_11_io_clk),
-    .io_en(rvclkhdr_11_io_en),
-    .io_scan_mode(rvclkhdr_11_io_scan_mode)
+    .io_en(rvclkhdr_11_io_en)
   );
-  assign io_tlu_busbuff_lsu_pmu_bus_trxn = _T_4925 | _T_4824; // @[lsu_bus_buffer.scala 616:35]
-  assign io_tlu_busbuff_lsu_pmu_bus_misaligned = _T_4928 & io_lsu_commit_r; // @[lsu_bus_buffer.scala 617:41]
-  assign io_tlu_busbuff_lsu_pmu_bus_error = io_tlu_busbuff_lsu_imprecise_error_load_any | io_tlu_busbuff_lsu_imprecise_error_store_any; // @[lsu_bus_buffer.scala 618:36]
-  assign io_tlu_busbuff_lsu_pmu_bus_busy = _T_4935 | _T_4937; // @[lsu_bus_buffer.scala 620:35]
-  assign io_tlu_busbuff_lsu_imprecise_error_load_any = io_dctl_busbuff_lsu_nonblock_load_data_error & _T_4920; // @[lsu_bus_buffer.scala 609:47]
-  assign io_tlu_busbuff_lsu_imprecise_error_store_any = _T_4890 | _T_4888; // @[lsu_bus_buffer.scala 606:48]
-  assign io_tlu_busbuff_lsu_imprecise_error_addr_any = io_tlu_busbuff_lsu_imprecise_error_store_any ? _GEN_357 : _GEN_361; // @[lsu_bus_buffer.scala 610:47]
-  assign io_dctl_busbuff_lsu_nonblock_load_valid_m = _T_4501 & _T_4502; // @[lsu_bus_buffer.scala 537:45]
-  assign io_dctl_busbuff_lsu_nonblock_load_tag_m = _T_1795 ? 2'h0 : _T_1831; // @[lsu_bus_buffer.scala 538:43]
-  assign io_dctl_busbuff_lsu_nonblock_load_inv_r = lsu_nonblock_load_valid_r & _T_4504; // @[lsu_bus_buffer.scala 540:43]
-  assign io_dctl_busbuff_lsu_nonblock_load_inv_tag_r = WrPtr0_r; // @[lsu_bus_buffer.scala 541:47]
-  assign io_dctl_busbuff_lsu_nonblock_load_data_valid = lsu_nonblock_load_data_ready & _T_4703; // @[lsu_bus_buffer.scala 553:48]
-  assign io_dctl_busbuff_lsu_nonblock_load_data_error = _T_4550 | _T_4548; // @[lsu_bus_buffer.scala 543:48]
-  assign io_dctl_busbuff_lsu_nonblock_load_data_tag = _T_4590 | _T_4588; // @[lsu_bus_buffer.scala 544:46]
-  assign io_dctl_busbuff_lsu_nonblock_load_data = _T_4738[31:0]; // @[lsu_bus_buffer.scala 554:42]
-  assign io_lsu_axi_aw_valid = _T_4834 & _T_1237; // @[lsu_bus_buffer.scala 576:23]
-  assign io_lsu_axi_aw_bits_id = {{1'd0}, _T_1780}; // @[lsu_bus_buffer.scala 577:25]
-  assign io_lsu_axi_aw_bits_addr = obuf_sideeffect ? obuf_addr : _T_4838; // @[lsu_bus_buffer.scala 578:27]
-  assign io_lsu_axi_aw_bits_region = obuf_addr[31:28]; // @[lsu_bus_buffer.scala 582:29]
-  assign io_lsu_axi_aw_bits_size = obuf_sideeffect ? _T_4840 : 3'h3; // @[lsu_bus_buffer.scala 579:27]
-  assign io_lsu_axi_aw_bits_cache = obuf_sideeffect ? 4'h0 : 4'hf; // @[lsu_bus_buffer.scala 581:28]
-  assign io_lsu_axi_w_valid = _T_4846 & _T_1237; // @[lsu_bus_buffer.scala 588:22]
-  assign io_lsu_axi_w_bits_data = obuf_data; // @[lsu_bus_buffer.scala 590:26]
-  assign io_lsu_axi_w_bits_strb = obuf_byteen & _T_4850; // @[lsu_bus_buffer.scala 589:26]
-  assign io_lsu_axi_b_ready = 1'h1; // @[lsu_bus_buffer.scala 604:22]
-  assign io_lsu_axi_ar_valid = _T_4855 & _T_1237; // @[lsu_bus_buffer.scala 593:23]
-  assign io_lsu_axi_ar_bits_id = {{1'd0}, _T_1780}; // @[lsu_bus_buffer.scala 594:25]
-  assign io_lsu_axi_ar_bits_addr = obuf_sideeffect ? obuf_addr : _T_4838; // @[lsu_bus_buffer.scala 595:27]
-  assign io_lsu_axi_ar_bits_region = obuf_addr[31:28]; // @[lsu_bus_buffer.scala 599:29]
-  assign io_lsu_axi_ar_bits_size = obuf_sideeffect ? _T_4840 : 3'h3; // @[lsu_bus_buffer.scala 596:27]
-  assign io_lsu_axi_ar_bits_cache = obuf_sideeffect ? 4'h0 : 4'hf; // @[lsu_bus_buffer.scala 598:28]
-  assign io_lsu_axi_r_ready = 1'h1; // @[lsu_bus_buffer.scala 605:22]
-  assign io_lsu_busreq_r = _T_4945; // @[lsu_bus_buffer.scala 624:19]
-  assign io_lsu_bus_buffer_pend_any = |buf_numvld_pend_any; // @[lsu_bus_buffer.scala 533:30]
-  assign io_lsu_bus_buffer_full_any = _T_4482 ? _T_4483 : _T_4484; // @[lsu_bus_buffer.scala 534:30]
-  assign io_lsu_bus_buffer_empty_any = _T_4495 & _T_1231; // @[lsu_bus_buffer.scala 535:31]
+  assign io_tlu_busbuff_lsu_pmu_bus_trxn = _T_4936 | _T_4835; // @[lsu_bus_buffer.scala 618:35]
+  assign io_tlu_busbuff_lsu_pmu_bus_misaligned = _T_4939 & io_lsu_commit_r; // @[lsu_bus_buffer.scala 619:41]
+  assign io_tlu_busbuff_lsu_pmu_bus_error = io_tlu_busbuff_lsu_imprecise_error_load_any | io_tlu_busbuff_lsu_imprecise_error_store_any; // @[lsu_bus_buffer.scala 620:36]
+  assign io_tlu_busbuff_lsu_pmu_bus_busy = _T_4946 | _T_4948; // @[lsu_bus_buffer.scala 622:35]
+  assign io_tlu_busbuff_lsu_imprecise_error_load_any = io_dctl_busbuff_lsu_nonblock_load_data_error & _T_4931; // @[lsu_bus_buffer.scala 611:47]
+  assign io_tlu_busbuff_lsu_imprecise_error_store_any = _T_4901 | _T_4899; // @[lsu_bus_buffer.scala 608:48]
+  assign io_tlu_busbuff_lsu_imprecise_error_addr_any = io_tlu_busbuff_lsu_imprecise_error_store_any ? _GEN_371 : _GEN_375; // @[lsu_bus_buffer.scala 612:47]
+  assign io_dctl_busbuff_lsu_nonblock_load_valid_m = _T_4512 & _T_4513; // @[lsu_bus_buffer.scala 539:45]
+  assign io_dctl_busbuff_lsu_nonblock_load_tag_m = _T_1802 ? 2'h0 : _T_1838; // @[lsu_bus_buffer.scala 540:43]
+  assign io_dctl_busbuff_lsu_nonblock_load_inv_r = lsu_nonblock_load_valid_r & _T_4515; // @[lsu_bus_buffer.scala 542:43]
+  assign io_dctl_busbuff_lsu_nonblock_load_inv_tag_r = WrPtr0_r; // @[lsu_bus_buffer.scala 543:47]
+  assign io_dctl_busbuff_lsu_nonblock_load_data_valid = lsu_nonblock_load_data_ready & _T_4714; // @[lsu_bus_buffer.scala 555:48]
+  assign io_dctl_busbuff_lsu_nonblock_load_data_error = _T_4561 | _T_4559; // @[lsu_bus_buffer.scala 545:48]
+  assign io_dctl_busbuff_lsu_nonblock_load_data_tag = _T_4601 | _T_4599; // @[lsu_bus_buffer.scala 546:45]
+  assign io_dctl_busbuff_lsu_nonblock_load_data = _T_4749[31:0]; // @[lsu_bus_buffer.scala 556:42]
+  assign io_lsu_axi_aw_valid = 1'h0; // @[lsu_bus_buffer.scala 578:23]
+  assign io_lsu_axi_aw_bits_addr = {obuf_addr[31:3],3'h0}; // @[lsu_bus_buffer.scala 580:27]
+  assign io_lsu_axi_aw_bits_region = obuf_addr[31:28]; // @[lsu_bus_buffer.scala 584:29]
+  assign io_lsu_axi_w_valid = 1'h0; // @[lsu_bus_buffer.scala 590:22]
+  assign io_lsu_axi_w_bits_data = obuf_data; // @[lsu_bus_buffer.scala 592:26]
+  assign io_lsu_axi_b_ready = 1'h1; // @[lsu_bus_buffer.scala 606:22]
+  assign io_lsu_axi_ar_valid = _T_1348 & _T_1237; // @[lsu_bus_buffer.scala 595:23]
+  assign io_lsu_axi_ar_bits_addr = {obuf_addr[31:3],3'h0}; // @[lsu_bus_buffer.scala 597:27]
+  assign io_lsu_axi_ar_bits_region = obuf_addr[31:28]; // @[lsu_bus_buffer.scala 601:29]
+  assign io_lsu_axi_r_ready = 1'h1; // @[lsu_bus_buffer.scala 607:22]
+  assign io_lsu_busreq_r = _T_4956; // @[lsu_bus_buffer.scala 626:19]
+  assign io_lsu_bus_buffer_pend_any = |buf_numvld_pend_any; // @[lsu_bus_buffer.scala 535:30]
+  assign io_lsu_bus_buffer_full_any = _T_4493 ? _T_4494 : _T_4495; // @[lsu_bus_buffer.scala 536:30]
+  assign io_lsu_bus_buffer_empty_any = _T_4506 & _T_1231; // @[lsu_bus_buffer.scala 537:31]
   assign io_ld_byte_hit_buf_lo = {_T_69,_T_58}; // @[lsu_bus_buffer.scala 141:25]
   assign io_ld_byte_hit_buf_hi = {_T_84,_T_73}; // @[lsu_bus_buffer.scala 142:25]
   assign io_ld_fwddata_buf_lo = _T_650 | _T_651; // @[lsu_bus_buffer.scala 168:24]
   assign io_ld_fwddata_buf_hi = _T_747 | _T_748; // @[lsu_bus_buffer.scala 174:24]
-  assign rvclkhdr_io_clk = clock; // @[lib.scala 370:18]
-  assign rvclkhdr_io_en = _T_853 & _T_854; // @[lib.scala 371:17]
-  assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
-  assign rvclkhdr_1_io_clk = clock; // @[lib.scala 370:18]
-  assign rvclkhdr_1_io_en = _T_853 & _T_854; // @[lib.scala 371:17]
-  assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
-  assign rvclkhdr_2_io_clk = clock; // @[lib.scala 370:18]
-  assign rvclkhdr_2_io_en = _T_1238 & io_lsu_bus_clk_en; // @[lib.scala 371:17]
-  assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
-  assign rvclkhdr_3_io_clk = clock; // @[lib.scala 370:18]
-  assign rvclkhdr_3_io_en = _T_1238 & io_lsu_bus_clk_en; // @[lib.scala 371:17]
-  assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
-  assign rvclkhdr_4_io_clk = clock; // @[lib.scala 370:18]
-  assign rvclkhdr_4_io_en = _T_3524 & buf_state_en_0; // @[lib.scala 371:17]
-  assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
-  assign rvclkhdr_5_io_clk = clock; // @[lib.scala 370:18]
-  assign rvclkhdr_5_io_en = _T_3714 & buf_state_en_1; // @[lib.scala 371:17]
-  assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
-  assign rvclkhdr_6_io_clk = clock; // @[lib.scala 370:18]
-  assign rvclkhdr_6_io_en = _T_3904 & buf_state_en_2; // @[lib.scala 371:17]
-  assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
-  assign rvclkhdr_7_io_clk = clock; // @[lib.scala 370:18]
-  assign rvclkhdr_7_io_en = _T_4094 & buf_state_en_3; // @[lib.scala 371:17]
-  assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
-  assign rvclkhdr_8_io_clk = clock; // @[lib.scala 370:18]
-  assign rvclkhdr_8_io_en = _T_3524 ? buf_state_en_0 : _GEN_71; // @[lib.scala 371:17]
-  assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
-  assign rvclkhdr_9_io_clk = clock; // @[lib.scala 370:18]
-  assign rvclkhdr_9_io_en = _T_3714 ? buf_state_en_1 : _GEN_148; // @[lib.scala 371:17]
-  assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
-  assign rvclkhdr_10_io_clk = clock; // @[lib.scala 370:18]
-  assign rvclkhdr_10_io_en = _T_3904 ? buf_state_en_2 : _GEN_225; // @[lib.scala 371:17]
-  assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
-  assign rvclkhdr_11_io_clk = clock; // @[lib.scala 370:18]
-  assign rvclkhdr_11_io_en = _T_4094 ? buf_state_en_3 : _GEN_302; // @[lib.scala 371:17]
-  assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[lib.scala 372:24]
+  assign rvclkhdr_io_clk = clock; // @[lib.scala 392:18]
+  assign rvclkhdr_io_en = _T_853 & _T_854; // @[lib.scala 393:17]
+  assign rvclkhdr_1_io_clk = clock; // @[lib.scala 392:18]
+  assign rvclkhdr_1_io_en = _T_853 & _T_854; // @[lib.scala 393:17]
+  assign rvclkhdr_2_io_clk = clock; // @[lib.scala 392:18]
+  assign rvclkhdr_2_io_en = _T_1238 & io_lsu_bus_clk_en; // @[lib.scala 393:17]
+  assign rvclkhdr_3_io_clk = clock; // @[lib.scala 392:18]
+  assign rvclkhdr_3_io_en = _T_1238 & io_lsu_bus_clk_en; // @[lib.scala 393:17]
+  assign rvclkhdr_4_io_clk = clock; // @[lib.scala 392:18]
+  assign rvclkhdr_4_io_en = _T_3531 & buf_state_en_0; // @[lib.scala 393:17]
+  assign rvclkhdr_5_io_clk = clock; // @[lib.scala 392:18]
+  assign rvclkhdr_5_io_en = _T_3722 & buf_state_en_1; // @[lib.scala 393:17]
+  assign rvclkhdr_6_io_clk = clock; // @[lib.scala 392:18]
+  assign rvclkhdr_6_io_en = _T_3913 & buf_state_en_2; // @[lib.scala 393:17]
+  assign rvclkhdr_7_io_clk = clock; // @[lib.scala 392:18]
+  assign rvclkhdr_7_io_en = _T_4104 & buf_state_en_3; // @[lib.scala 393:17]
+  assign rvclkhdr_8_io_clk = clock; // @[lib.scala 392:18]
+  assign rvclkhdr_8_io_en = _T_3531 ? buf_state_en_0 : _GEN_81; // @[lib.scala 393:17]
+  assign rvclkhdr_9_io_clk = clock; // @[lib.scala 392:18]
+  assign rvclkhdr_9_io_en = _T_3722 ? buf_state_en_1 : _GEN_157; // @[lib.scala 393:17]
+  assign rvclkhdr_10_io_clk = clock; // @[lib.scala 392:18]
+  assign rvclkhdr_10_io_en = _T_3913 ? buf_state_en_2 : _GEN_233; // @[lib.scala 393:17]
+  assign rvclkhdr_11_io_clk = clock; // @[lib.scala 392:18]
+  assign rvclkhdr_11_io_en = _T_4104 ? buf_state_en_3 : _GEN_309; // @[lib.scala 393:17]
 `ifdef RANDOMIZE_GARBAGE_ASSIGN
 `define RANDOMIZE
 `endif
@@ -8073,13 +7773,13 @@ initial begin
   _RAND_0 = {1{`RANDOM}};
   buf_addr_0 = _RAND_0[31:0];
   _RAND_1 = {1{`RANDOM}};
-  _T_4344 = _RAND_1[0:0];
+  _T_4355 = _RAND_1[0:0];
   _RAND_2 = {1{`RANDOM}};
-  _T_4341 = _RAND_2[0:0];
+  _T_4352 = _RAND_2[0:0];
   _RAND_3 = {1{`RANDOM}};
-  _T_4338 = _RAND_3[0:0];
+  _T_4349 = _RAND_3[0:0];
   _RAND_4 = {1{`RANDOM}};
-  _T_4335 = _RAND_4[0:0];
+  _T_4346 = _RAND_4[0:0];
   _RAND_5 = {1{`RANDOM}};
   buf_state_0 = _RAND_5[2:0];
   _RAND_6 = {1{`RANDOM}};
@@ -8105,200 +7805,170 @@ initial begin
   _RAND_16 = {1{`RANDOM}};
   buf_ageQ_3 = _RAND_16[3:0];
   _RAND_17 = {1{`RANDOM}};
-  _T_1780 = _RAND_17[1:0];
+  obuf_valid = _RAND_17[0:0];
   _RAND_18 = {1{`RANDOM}};
-  obuf_merge = _RAND_18[0:0];
+  ibuf_addr = _RAND_18[31:0];
   _RAND_19 = {1{`RANDOM}};
-  obuf_tag1 = _RAND_19[1:0];
+  ibuf_write = _RAND_19[0:0];
   _RAND_20 = {1{`RANDOM}};
-  obuf_valid = _RAND_20[0:0];
+  ibuf_valid = _RAND_20[0:0];
   _RAND_21 = {1{`RANDOM}};
-  obuf_wr_enQ = _RAND_21[0:0];
+  ibuf_byteen = _RAND_21[3:0];
   _RAND_22 = {1{`RANDOM}};
-  ibuf_addr = _RAND_22[31:0];
+  buf_ageQ_2 = _RAND_22[3:0];
   _RAND_23 = {1{`RANDOM}};
-  ibuf_write = _RAND_23[0:0];
+  buf_ageQ_1 = _RAND_23[3:0];
   _RAND_24 = {1{`RANDOM}};
-  ibuf_valid = _RAND_24[0:0];
+  buf_ageQ_0 = _RAND_24[3:0];
   _RAND_25 = {1{`RANDOM}};
-  ibuf_byteen = _RAND_25[3:0];
+  buf_data_0 = _RAND_25[31:0];
   _RAND_26 = {1{`RANDOM}};
-  buf_ageQ_2 = _RAND_26[3:0];
+  buf_data_1 = _RAND_26[31:0];
   _RAND_27 = {1{`RANDOM}};
-  buf_ageQ_1 = _RAND_27[3:0];
+  buf_data_2 = _RAND_27[31:0];
   _RAND_28 = {1{`RANDOM}};
-  buf_ageQ_0 = _RAND_28[3:0];
+  buf_data_3 = _RAND_28[31:0];
   _RAND_29 = {1{`RANDOM}};
-  buf_data_0 = _RAND_29[31:0];
+  ibuf_data = _RAND_29[31:0];
   _RAND_30 = {1{`RANDOM}};
-  buf_data_1 = _RAND_30[31:0];
+  ibuf_timer = _RAND_30[2:0];
   _RAND_31 = {1{`RANDOM}};
-  buf_data_2 = _RAND_31[31:0];
+  ibuf_sideeffect = _RAND_31[0:0];
   _RAND_32 = {1{`RANDOM}};
-  buf_data_3 = _RAND_32[31:0];
+  WrPtr1_r = _RAND_32[1:0];
   _RAND_33 = {1{`RANDOM}};
-  ibuf_data = _RAND_33[31:0];
+  WrPtr0_r = _RAND_33[1:0];
   _RAND_34 = {1{`RANDOM}};
-  ibuf_timer = _RAND_34[2:0];
+  ibuf_tag = _RAND_34[1:0];
   _RAND_35 = {1{`RANDOM}};
-  ibuf_sideeffect = _RAND_35[0:0];
+  ibuf_dualtag = _RAND_35[1:0];
   _RAND_36 = {1{`RANDOM}};
-  WrPtr1_r = _RAND_36[1:0];
+  ibuf_dual = _RAND_36[0:0];
   _RAND_37 = {1{`RANDOM}};
-  WrPtr0_r = _RAND_37[1:0];
+  ibuf_samedw = _RAND_37[0:0];
   _RAND_38 = {1{`RANDOM}};
-  ibuf_tag = _RAND_38[1:0];
+  ibuf_nomerge = _RAND_38[0:0];
   _RAND_39 = {1{`RANDOM}};
-  ibuf_dualtag = _RAND_39[1:0];
+  ibuf_unsign = _RAND_39[0:0];
   _RAND_40 = {1{`RANDOM}};
-  ibuf_dual = _RAND_40[0:0];
+  ibuf_sz = _RAND_40[1:0];
   _RAND_41 = {1{`RANDOM}};
-  ibuf_samedw = _RAND_41[0:0];
+  _T_1791 = _RAND_41[0:0];
   _RAND_42 = {1{`RANDOM}};
-  ibuf_nomerge = _RAND_42[0:0];
+  buf_nomerge_0 = _RAND_42[0:0];
   _RAND_43 = {1{`RANDOM}};
-  ibuf_unsign = _RAND_43[0:0];
+  buf_nomerge_1 = _RAND_43[0:0];
   _RAND_44 = {1{`RANDOM}};
-  ibuf_sz = _RAND_44[1:0];
+  buf_nomerge_2 = _RAND_44[0:0];
   _RAND_45 = {1{`RANDOM}};
-  obuf_wr_timer = _RAND_45[2:0];
+  buf_nomerge_3 = _RAND_45[0:0];
   _RAND_46 = {1{`RANDOM}};
-  buf_nomerge_0 = _RAND_46[0:0];
+  _T_4325 = _RAND_46[0:0];
   _RAND_47 = {1{`RANDOM}};
-  buf_nomerge_1 = _RAND_47[0:0];
+  _T_4322 = _RAND_47[0:0];
   _RAND_48 = {1{`RANDOM}};
-  buf_nomerge_2 = _RAND_48[0:0];
+  _T_4319 = _RAND_48[0:0];
   _RAND_49 = {1{`RANDOM}};
-  buf_nomerge_3 = _RAND_49[0:0];
+  _T_4316 = _RAND_49[0:0];
   _RAND_50 = {1{`RANDOM}};
-  _T_4314 = _RAND_50[0:0];
+  buf_dual_3 = _RAND_50[0:0];
   _RAND_51 = {1{`RANDOM}};
-  _T_4311 = _RAND_51[0:0];
+  buf_dual_2 = _RAND_51[0:0];
   _RAND_52 = {1{`RANDOM}};
-  _T_4308 = _RAND_52[0:0];
+  buf_dual_1 = _RAND_52[0:0];
   _RAND_53 = {1{`RANDOM}};
-  _T_4305 = _RAND_53[0:0];
+  buf_dual_0 = _RAND_53[0:0];
   _RAND_54 = {1{`RANDOM}};
-  obuf_sideeffect = _RAND_54[0:0];
+  buf_samedw_3 = _RAND_54[0:0];
   _RAND_55 = {1{`RANDOM}};
-  buf_dual_3 = _RAND_55[0:0];
+  buf_samedw_2 = _RAND_55[0:0];
   _RAND_56 = {1{`RANDOM}};
-  buf_dual_2 = _RAND_56[0:0];
+  buf_samedw_1 = _RAND_56[0:0];
   _RAND_57 = {1{`RANDOM}};
-  buf_dual_1 = _RAND_57[0:0];
+  buf_samedw_0 = _RAND_57[0:0];
   _RAND_58 = {1{`RANDOM}};
-  buf_dual_0 = _RAND_58[0:0];
+  obuf_nosend = _RAND_58[0:0];
   _RAND_59 = {1{`RANDOM}};
-  buf_samedw_3 = _RAND_59[0:0];
+  obuf_addr = _RAND_59[31:0];
   _RAND_60 = {1{`RANDOM}};
-  buf_samedw_2 = _RAND_60[0:0];
+  buf_sz_0 = _RAND_60[1:0];
   _RAND_61 = {1{`RANDOM}};
-  buf_samedw_1 = _RAND_61[0:0];
+  buf_sz_1 = _RAND_61[1:0];
   _RAND_62 = {1{`RANDOM}};
-  buf_samedw_0 = _RAND_62[0:0];
+  buf_sz_2 = _RAND_62[1:0];
   _RAND_63 = {1{`RANDOM}};
-  obuf_write = _RAND_63[0:0];
+  buf_sz_3 = _RAND_63[1:0];
   _RAND_64 = {1{`RANDOM}};
-  obuf_cmd_done = _RAND_64[0:0];
+  obuf_rdrsp_pend = _RAND_64[0:0];
   _RAND_65 = {1{`RANDOM}};
-  obuf_data_done = _RAND_65[0:0];
+  buf_dualhi_3 = _RAND_65[0:0];
   _RAND_66 = {1{`RANDOM}};
-  obuf_nosend = _RAND_66[0:0];
+  buf_dualhi_2 = _RAND_66[0:0];
   _RAND_67 = {1{`RANDOM}};
-  obuf_addr = _RAND_67[31:0];
+  buf_dualhi_1 = _RAND_67[0:0];
   _RAND_68 = {1{`RANDOM}};
-  buf_sz_0 = _RAND_68[1:0];
-  _RAND_69 = {1{`RANDOM}};
-  buf_sz_1 = _RAND_69[1:0];
+  buf_dualhi_0 = _RAND_68[0:0];
+  _RAND_69 = {2{`RANDOM}};
+  obuf_data = _RAND_69[63:0];
   _RAND_70 = {1{`RANDOM}};
-  buf_sz_2 = _RAND_70[1:0];
+  buf_rspageQ_0 = _RAND_70[3:0];
   _RAND_71 = {1{`RANDOM}};
-  buf_sz_3 = _RAND_71[1:0];
+  buf_rspageQ_1 = _RAND_71[3:0];
   _RAND_72 = {1{`RANDOM}};
-  obuf_rdrsp_pend = _RAND_72[0:0];
+  buf_rspageQ_2 = _RAND_72[3:0];
   _RAND_73 = {1{`RANDOM}};
-  obuf_rdrsp_tag = _RAND_73[2:0];
+  buf_rspageQ_3 = _RAND_73[3:0];
   _RAND_74 = {1{`RANDOM}};
-  buf_dualhi_3 = _RAND_74[0:0];
+  _T_4302 = _RAND_74[0:0];
   _RAND_75 = {1{`RANDOM}};
-  buf_dualhi_2 = _RAND_75[0:0];
+  _T_4300 = _RAND_75[0:0];
   _RAND_76 = {1{`RANDOM}};
-  buf_dualhi_1 = _RAND_76[0:0];
+  _T_4298 = _RAND_76[0:0];
   _RAND_77 = {1{`RANDOM}};
-  buf_dualhi_0 = _RAND_77[0:0];
+  _T_4296 = _RAND_77[0:0];
   _RAND_78 = {1{`RANDOM}};
-  obuf_sz = _RAND_78[1:0];
+  buf_dualtag_0 = _RAND_78[1:0];
   _RAND_79 = {1{`RANDOM}};
-  obuf_byteen = _RAND_79[7:0];
-  _RAND_80 = {2{`RANDOM}};
-  obuf_data = _RAND_80[63:0];
+  buf_dualtag_1 = _RAND_79[1:0];
+  _RAND_80 = {1{`RANDOM}};
+  buf_dualtag_2 = _RAND_80[1:0];
   _RAND_81 = {1{`RANDOM}};
-  buf_rspageQ_0 = _RAND_81[3:0];
+  buf_dualtag_3 = _RAND_81[1:0];
   _RAND_82 = {1{`RANDOM}};
-  buf_rspageQ_1 = _RAND_82[3:0];
+  _T_4331 = _RAND_82[0:0];
   _RAND_83 = {1{`RANDOM}};
-  buf_rspageQ_2 = _RAND_83[3:0];
+  _T_4334 = _RAND_83[0:0];
   _RAND_84 = {1{`RANDOM}};
-  buf_rspageQ_3 = _RAND_84[3:0];
+  _T_4337 = _RAND_84[0:0];
   _RAND_85 = {1{`RANDOM}};
-  _T_4291 = _RAND_85[0:0];
+  _T_4340 = _RAND_85[0:0];
   _RAND_86 = {1{`RANDOM}};
-  _T_4289 = _RAND_86[0:0];
+  _T_4406 = _RAND_86[0:0];
   _RAND_87 = {1{`RANDOM}};
-  _T_4287 = _RAND_87[0:0];
+  _T_4401 = _RAND_87[0:0];
   _RAND_88 = {1{`RANDOM}};
-  _T_4285 = _RAND_88[0:0];
+  _T_4396 = _RAND_88[0:0];
   _RAND_89 = {1{`RANDOM}};
-  buf_ldfwdtag_0 = _RAND_89[1:0];
+  _T_4391 = _RAND_89[0:0];
   _RAND_90 = {1{`RANDOM}};
-  buf_dualtag_0 = _RAND_90[1:0];
+  lsu_nonblock_load_valid_r = _RAND_90[0:0];
   _RAND_91 = {1{`RANDOM}};
-  buf_ldfwdtag_3 = _RAND_91[1:0];
-  _RAND_92 = {1{`RANDOM}};
-  buf_ldfwdtag_2 = _RAND_92[1:0];
-  _RAND_93 = {1{`RANDOM}};
-  buf_ldfwdtag_1 = _RAND_93[1:0];
-  _RAND_94 = {1{`RANDOM}};
-  buf_dualtag_1 = _RAND_94[1:0];
-  _RAND_95 = {1{`RANDOM}};
-  buf_dualtag_2 = _RAND_95[1:0];
-  _RAND_96 = {1{`RANDOM}};
-  buf_dualtag_3 = _RAND_96[1:0];
-  _RAND_97 = {1{`RANDOM}};
-  _T_4320 = _RAND_97[0:0];
-  _RAND_98 = {1{`RANDOM}};
-  _T_4323 = _RAND_98[0:0];
-  _RAND_99 = {1{`RANDOM}};
-  _T_4326 = _RAND_99[0:0];
-  _RAND_100 = {1{`RANDOM}};
-  _T_4329 = _RAND_100[0:0];
-  _RAND_101 = {1{`RANDOM}};
-  _T_4395 = _RAND_101[0:0];
-  _RAND_102 = {1{`RANDOM}};
-  _T_4390 = _RAND_102[0:0];
-  _RAND_103 = {1{`RANDOM}};
-  _T_4385 = _RAND_103[0:0];
-  _RAND_104 = {1{`RANDOM}};
-  _T_4380 = _RAND_104[0:0];
-  _RAND_105 = {1{`RANDOM}};
-  lsu_nonblock_load_valid_r = _RAND_105[0:0];
-  _RAND_106 = {1{`RANDOM}};
-  _T_4945 = _RAND_106[0:0];
+  _T_4956 = _RAND_91[0:0];
 `endif // RANDOMIZE_REG_INIT
   if (reset) begin
     buf_addr_0 = 32'h0;
   end
   if (reset) begin
-    _T_4344 = 1'h0;
+    _T_4355 = 1'h0;
   end
   if (reset) begin
-    _T_4341 = 1'h0;
+    _T_4352 = 1'h0;
   end
   if (reset) begin
-    _T_4338 = 1'h0;
+    _T_4349 = 1'h0;
   end
   if (reset) begin
-    _T_4335 = 1'h0;
+    _T_4346 = 1'h0;
   end
   if (reset) begin
     buf_state_0 = 3'h0;
@@ -8336,21 +8006,9 @@ initial begin
   if (reset) begin
     buf_ageQ_3 = 4'h0;
   end
-  if (reset) begin
-    _T_1780 = 2'h0;
-  end
-  if (reset) begin
-    obuf_merge = 1'h0;
-  end
-  if (reset) begin
-    obuf_tag1 = 2'h0;
-  end
   if (reset) begin
     obuf_valid = 1'h0;
   end
-  if (reset) begin
-    obuf_wr_enQ = 1'h0;
-  end
   if (reset) begin
     ibuf_addr = 32'h0;
   end
@@ -8421,7 +8079,7 @@ initial begin
     ibuf_sz = 2'h0;
   end
   if (reset) begin
-    obuf_wr_timer = 3'h0;
+    _T_1791 = 1'h0;
   end
   if (reset) begin
     buf_nomerge_0 = 1'h0;
@@ -8436,19 +8094,16 @@ initial begin
     buf_nomerge_3 = 1'h0;
   end
   if (reset) begin
-    _T_4314 = 1'h0;
+    _T_4325 = 1'h0;
   end
   if (reset) begin
-    _T_4311 = 1'h0;
+    _T_4322 = 1'h0;
   end
   if (reset) begin
-    _T_4308 = 1'h0;
+    _T_4319 = 1'h0;
   end
   if (reset) begin
-    _T_4305 = 1'h0;
-  end
-  if (reset) begin
-    obuf_sideeffect = 1'h0;
+    _T_4316 = 1'h0;
   end
   if (reset) begin
     buf_dual_3 = 1'h0;
@@ -8474,15 +8129,6 @@ initial begin
   if (reset) begin
     buf_samedw_0 = 1'h0;
   end
-  if (reset) begin
-    obuf_write = 1'h0;
-  end
-  if (reset) begin
-    obuf_cmd_done = 1'h0;
-  end
-  if (reset) begin
-    obuf_data_done = 1'h0;
-  end
   if (reset) begin
     obuf_nosend = 1'h0;
   end
@@ -8504,9 +8150,6 @@ initial begin
   if (reset) begin
     obuf_rdrsp_pend = 1'h0;
   end
-  if (reset) begin
-    obuf_rdrsp_tag = 3'h0;
-  end
   if (reset) begin
     buf_dualhi_3 = 1'h0;
   end
@@ -8519,12 +8162,6 @@ initial begin
   if (reset) begin
     buf_dualhi_0 = 1'h0;
   end
-  if (reset) begin
-    obuf_sz = 2'h0;
-  end
-  if (reset) begin
-    obuf_byteen = 8'h0;
-  end
   if (reset) begin
     obuf_data = 64'h0;
   end
@@ -8541,32 +8178,20 @@ initial begin
     buf_rspageQ_3 = 4'h0;
   end
   if (reset) begin
-    _T_4291 = 1'h0;
+    _T_4302 = 1'h0;
   end
   if (reset) begin
-    _T_4289 = 1'h0;
+    _T_4300 = 1'h0;
   end
   if (reset) begin
-    _T_4287 = 1'h0;
+    _T_4298 = 1'h0;
   end
   if (reset) begin
-    _T_4285 = 1'h0;
-  end
-  if (reset) begin
-    buf_ldfwdtag_0 = 2'h0;
+    _T_4296 = 1'h0;
   end
   if (reset) begin
     buf_dualtag_0 = 2'h0;
   end
-  if (reset) begin
-    buf_ldfwdtag_3 = 2'h0;
-  end
-  if (reset) begin
-    buf_ldfwdtag_2 = 2'h0;
-  end
-  if (reset) begin
-    buf_ldfwdtag_1 = 2'h0;
-  end
   if (reset) begin
     buf_dualtag_1 = 2'h0;
   end
@@ -8577,34 +8202,34 @@ initial begin
     buf_dualtag_3 = 2'h0;
   end
   if (reset) begin
-    _T_4320 = 1'h0;
+    _T_4331 = 1'h0;
   end
   if (reset) begin
-    _T_4323 = 1'h0;
+    _T_4334 = 1'h0;
   end
   if (reset) begin
-    _T_4326 = 1'h0;
+    _T_4337 = 1'h0;
   end
   if (reset) begin
-    _T_4329 = 1'h0;
+    _T_4340 = 1'h0;
   end
   if (reset) begin
-    _T_4395 = 1'h0;
+    _T_4406 = 1'h0;
   end
   if (reset) begin
-    _T_4390 = 1'h0;
+    _T_4401 = 1'h0;
   end
   if (reset) begin
-    _T_4385 = 1'h0;
+    _T_4396 = 1'h0;
   end
   if (reset) begin
-    _T_4380 = 1'h0;
+    _T_4391 = 1'h0;
   end
   if (reset) begin
     lsu_nonblock_load_valid_r = 1'h0;
   end
   if (reset) begin
-    _T_4945 = 1'h0;
+    _T_4956 = 1'h0;
   end
   `endif // RANDOMIZE
 end // initial
@@ -8612,88 +8237,90 @@ end // initial
 `FIRRTL_AFTER_INITIAL
 `endif
 `endif // SYNTHESIS
-  always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin
+  always @(posedge clock or posedge reset) begin
     if (reset) begin
       buf_addr_0 <= 32'h0;
-    end else if (ibuf_drainvec_vld[0]) begin
-      buf_addr_0 <= ibuf_addr;
-    end else if (_T_3339) begin
-      buf_addr_0 <= io_end_addr_r;
-    end else begin
-      buf_addr_0 <= io_lsu_addr_r;
-    end
-  end
-  always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
-    if (reset) begin
-      _T_4344 <= 1'h0;
-    end else if (buf_wr_en_3) begin
-      _T_4344 <= buf_write_in[3];
-    end
-  end
-  always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
-    if (reset) begin
-      _T_4341 <= 1'h0;
-    end else if (buf_wr_en_2) begin
-      _T_4341 <= buf_write_in[2];
-    end
-  end
-  always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
-    if (reset) begin
-      _T_4338 <= 1'h0;
-    end else if (buf_wr_en_1) begin
-      _T_4338 <= buf_write_in[1];
-    end
-  end
-  always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
-    if (reset) begin
-      _T_4335 <= 1'h0;
     end else if (buf_wr_en_0) begin
-      _T_4335 <= buf_write_in[0];
+      if (ibuf_drainvec_vld[0]) begin
+        buf_addr_0 <= ibuf_addr;
+      end else if (_T_3346) begin
+        buf_addr_0 <= io_end_addr_r;
+      end else begin
+        buf_addr_0 <= io_lsu_addr_r;
+      end
+    end
+  end
+  always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
+    if (reset) begin
+      _T_4355 <= 1'h0;
+    end else if (buf_wr_en_3) begin
+      _T_4355 <= buf_write_in[3];
+    end
+  end
+  always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
+    if (reset) begin
+      _T_4352 <= 1'h0;
+    end else if (buf_wr_en_2) begin
+      _T_4352 <= buf_write_in[2];
+    end
+  end
+  always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
+    if (reset) begin
+      _T_4349 <= 1'h0;
+    end else if (buf_wr_en_1) begin
+      _T_4349 <= buf_write_in[1];
+    end
+  end
+  always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
+    if (reset) begin
+      _T_4346 <= 1'h0;
+    end else if (buf_wr_en_0) begin
+      _T_4346 <= buf_write_in[0];
     end
   end
   always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
     if (reset) begin
       buf_state_0 <= 3'h0;
     end else if (buf_state_en_0) begin
-      if (_T_3524) begin
+      if (_T_3531) begin
         if (io_lsu_bus_clk_en) begin
           buf_state_0 <= 3'h2;
         end else begin
           buf_state_0 <= 3'h1;
         end
-      end else if (_T_3547) begin
+      end else if (_T_3554) begin
         if (io_dec_tlu_force_halt) begin
           buf_state_0 <= 3'h0;
         end else begin
           buf_state_0 <= 3'h2;
         end
-      end else if (_T_3551) begin
+      end else if (_T_3558) begin
         if (io_dec_tlu_force_halt) begin
           buf_state_0 <= 3'h0;
-        end else if (_T_3555) begin
+        end else if (_T_3562) begin
           buf_state_0 <= 3'h5;
         end else begin
           buf_state_0 <= 3'h3;
         end
-      end else if (_T_3585) begin
-        if (_T_3588) begin
+      end else if (_T_3592) begin
+        if (_T_3596) begin
           buf_state_0 <= 3'h0;
-        end else if (_T_3596) begin
+        end else if (_T_3604) begin
           buf_state_0 <= 3'h4;
-        end else if (_T_3624) begin
+        end else if (_T_3632) begin
           buf_state_0 <= 3'h5;
         end else begin
           buf_state_0 <= 3'h6;
         end
-      end else if (_T_3669) begin
+      end else if (_T_3677) begin
         if (io_dec_tlu_force_halt) begin
           buf_state_0 <= 3'h0;
-        end else if (_T_3675) begin
+        end else if (_T_3683) begin
           buf_state_0 <= 3'h5;
         end else begin
           buf_state_0 <= 3'h6;
         end
-      end else if (_T_3687) begin
+      end else if (_T_3695) begin
         if (io_dec_tlu_force_halt) begin
           buf_state_0 <= 3'h0;
         end else begin
@@ -8704,60 +8331,62 @@ end // initial
       end
     end
   end
-  always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin
+  always @(posedge clock or posedge reset) begin
     if (reset) begin
       buf_addr_1 <= 32'h0;
-    end else if (ibuf_drainvec_vld[1]) begin
-      buf_addr_1 <= ibuf_addr;
-    end else if (_T_3348) begin
-      buf_addr_1 <= io_end_addr_r;
-    end else begin
-      buf_addr_1 <= io_lsu_addr_r;
+    end else if (buf_wr_en_1) begin
+      if (ibuf_drainvec_vld[1]) begin
+        buf_addr_1 <= ibuf_addr;
+      end else if (_T_3355) begin
+        buf_addr_1 <= io_end_addr_r;
+      end else begin
+        buf_addr_1 <= io_lsu_addr_r;
+      end
     end
   end
   always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
     if (reset) begin
       buf_state_1 <= 3'h0;
     end else if (buf_state_en_1) begin
-      if (_T_3714) begin
+      if (_T_3722) begin
         if (io_lsu_bus_clk_en) begin
           buf_state_1 <= 3'h2;
         end else begin
           buf_state_1 <= 3'h1;
         end
-      end else if (_T_3737) begin
+      end else if (_T_3745) begin
         if (io_dec_tlu_force_halt) begin
           buf_state_1 <= 3'h0;
         end else begin
           buf_state_1 <= 3'h2;
         end
-      end else if (_T_3741) begin
+      end else if (_T_3749) begin
         if (io_dec_tlu_force_halt) begin
           buf_state_1 <= 3'h0;
-        end else if (_T_3555) begin
+        end else if (_T_3562) begin
           buf_state_1 <= 3'h5;
         end else begin
           buf_state_1 <= 3'h3;
         end
-      end else if (_T_3775) begin
-        if (_T_3778) begin
+      end else if (_T_3783) begin
+        if (_T_3787) begin
           buf_state_1 <= 3'h0;
-        end else if (_T_3786) begin
+        end else if (_T_3795) begin
           buf_state_1 <= 3'h4;
-        end else if (_T_3814) begin
+        end else if (_T_3823) begin
           buf_state_1 <= 3'h5;
         end else begin
           buf_state_1 <= 3'h6;
         end
-      end else if (_T_3859) begin
+      end else if (_T_3868) begin
         if (io_dec_tlu_force_halt) begin
           buf_state_1 <= 3'h0;
-        end else if (_T_3865) begin
+        end else if (_T_3874) begin
           buf_state_1 <= 3'h5;
         end else begin
           buf_state_1 <= 3'h6;
         end
-      end else if (_T_3877) begin
+      end else if (_T_3886) begin
         if (io_dec_tlu_force_halt) begin
           buf_state_1 <= 3'h0;
         end else begin
@@ -8768,60 +8397,62 @@ end // initial
       end
     end
   end
-  always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin
+  always @(posedge clock or posedge reset) begin
     if (reset) begin
       buf_addr_2 <= 32'h0;
-    end else if (ibuf_drainvec_vld[2]) begin
-      buf_addr_2 <= ibuf_addr;
-    end else if (_T_3357) begin
-      buf_addr_2 <= io_end_addr_r;
-    end else begin
-      buf_addr_2 <= io_lsu_addr_r;
+    end else if (buf_wr_en_2) begin
+      if (ibuf_drainvec_vld[2]) begin
+        buf_addr_2 <= ibuf_addr;
+      end else if (_T_3364) begin
+        buf_addr_2 <= io_end_addr_r;
+      end else begin
+        buf_addr_2 <= io_lsu_addr_r;
+      end
     end
   end
   always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
     if (reset) begin
       buf_state_2 <= 3'h0;
     end else if (buf_state_en_2) begin
-      if (_T_3904) begin
+      if (_T_3913) begin
         if (io_lsu_bus_clk_en) begin
           buf_state_2 <= 3'h2;
         end else begin
           buf_state_2 <= 3'h1;
         end
-      end else if (_T_3927) begin
+      end else if (_T_3936) begin
         if (io_dec_tlu_force_halt) begin
           buf_state_2 <= 3'h0;
         end else begin
           buf_state_2 <= 3'h2;
         end
-      end else if (_T_3931) begin
+      end else if (_T_3940) begin
         if (io_dec_tlu_force_halt) begin
           buf_state_2 <= 3'h0;
-        end else if (_T_3555) begin
+        end else if (_T_3562) begin
           buf_state_2 <= 3'h5;
         end else begin
           buf_state_2 <= 3'h3;
         end
-      end else if (_T_3965) begin
-        if (_T_3968) begin
+      end else if (_T_3974) begin
+        if (_T_3978) begin
           buf_state_2 <= 3'h0;
-        end else if (_T_3976) begin
+        end else if (_T_3986) begin
           buf_state_2 <= 3'h4;
-        end else if (_T_4004) begin
+        end else if (_T_4014) begin
           buf_state_2 <= 3'h5;
         end else begin
           buf_state_2 <= 3'h6;
         end
-      end else if (_T_4049) begin
+      end else if (_T_4059) begin
         if (io_dec_tlu_force_halt) begin
           buf_state_2 <= 3'h0;
-        end else if (_T_4055) begin
+        end else if (_T_4065) begin
           buf_state_2 <= 3'h5;
         end else begin
           buf_state_2 <= 3'h6;
         end
-      end else if (_T_4067) begin
+      end else if (_T_4077) begin
         if (io_dec_tlu_force_halt) begin
           buf_state_2 <= 3'h0;
         end else begin
@@ -8832,60 +8463,62 @@ end // initial
       end
     end
   end
-  always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin
+  always @(posedge clock or posedge reset) begin
     if (reset) begin
       buf_addr_3 <= 32'h0;
-    end else if (ibuf_drainvec_vld[3]) begin
-      buf_addr_3 <= ibuf_addr;
-    end else if (_T_3366) begin
-      buf_addr_3 <= io_end_addr_r;
-    end else begin
-      buf_addr_3 <= io_lsu_addr_r;
+    end else if (buf_wr_en_3) begin
+      if (ibuf_drainvec_vld[3]) begin
+        buf_addr_3 <= ibuf_addr;
+      end else if (_T_3373) begin
+        buf_addr_3 <= io_end_addr_r;
+      end else begin
+        buf_addr_3 <= io_lsu_addr_r;
+      end
     end
   end
   always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
     if (reset) begin
       buf_state_3 <= 3'h0;
     end else if (buf_state_en_3) begin
-      if (_T_4094) begin
+      if (_T_4104) begin
         if (io_lsu_bus_clk_en) begin
           buf_state_3 <= 3'h2;
         end else begin
           buf_state_3 <= 3'h1;
         end
-      end else if (_T_4117) begin
+      end else if (_T_4127) begin
         if (io_dec_tlu_force_halt) begin
           buf_state_3 <= 3'h0;
         end else begin
           buf_state_3 <= 3'h2;
         end
-      end else if (_T_4121) begin
+      end else if (_T_4131) begin
         if (io_dec_tlu_force_halt) begin
           buf_state_3 <= 3'h0;
-        end else if (_T_3555) begin
+        end else if (_T_3562) begin
           buf_state_3 <= 3'h5;
         end else begin
           buf_state_3 <= 3'h3;
         end
-      end else if (_T_4155) begin
-        if (_T_4158) begin
+      end else if (_T_4165) begin
+        if (_T_4169) begin
           buf_state_3 <= 3'h0;
-        end else if (_T_4166) begin
+        end else if (_T_4177) begin
           buf_state_3 <= 3'h4;
-        end else if (_T_4194) begin
+        end else if (_T_4205) begin
           buf_state_3 <= 3'h5;
         end else begin
           buf_state_3 <= 3'h6;
         end
-      end else if (_T_4239) begin
+      end else if (_T_4250) begin
         if (io_dec_tlu_force_halt) begin
           buf_state_3 <= 3'h0;
-        end else if (_T_4245) begin
+        end else if (_T_4256) begin
           buf_state_3 <= 3'h5;
         end else begin
           buf_state_3 <= 3'h6;
         end
-      end else if (_T_4257) begin
+      end else if (_T_4268) begin
         if (io_dec_tlu_force_halt) begin
           buf_state_3 <= 3'h0;
         end else begin
@@ -8902,7 +8535,7 @@ end // initial
     end else if (buf_wr_en_3) begin
       if (ibuf_drainvec_vld[3]) begin
         buf_byteen_3 <= ibuf_byteen_out;
-      end else if (_T_3366) begin
+      end else if (_T_3373) begin
         buf_byteen_3 <= ldst_byteen_hi_r;
       end else begin
         buf_byteen_3 <= ldst_byteen_lo_r;
@@ -8915,7 +8548,7 @@ end // initial
     end else if (buf_wr_en_2) begin
       if (ibuf_drainvec_vld[2]) begin
         buf_byteen_2 <= ibuf_byteen_out;
-      end else if (_T_3357) begin
+      end else if (_T_3364) begin
         buf_byteen_2 <= ldst_byteen_hi_r;
       end else begin
         buf_byteen_2 <= ldst_byteen_lo_r;
@@ -8928,7 +8561,7 @@ end // initial
     end else if (buf_wr_en_1) begin
       if (ibuf_drainvec_vld[1]) begin
         buf_byteen_1 <= ibuf_byteen_out;
-      end else if (_T_3348) begin
+      end else if (_T_3355) begin
         buf_byteen_1 <= ldst_byteen_hi_r;
       end else begin
         buf_byteen_1 <= ldst_byteen_lo_r;
@@ -8941,7 +8574,7 @@ end // initial
     end else if (buf_wr_en_0) begin
       if (ibuf_drainvec_vld[0]) begin
         buf_byteen_0 <= ibuf_byteen_out;
-      end else if (_T_3339) begin
+      end else if (_T_3346) begin
         buf_byteen_0 <= ldst_byteen_hi_r;
       end else begin
         buf_byteen_0 <= ldst_byteen_lo_r;
@@ -8952,36 +8585,7 @@ end // initial
     if (reset) begin
       buf_ageQ_3 <= 4'h0;
     end else begin
-      buf_ageQ_3 <= {_T_2467,_T_2390};
-    end
-  end
-  always @(posedge io_lsu_bus_obuf_c1_clk or posedge reset) begin
-    if (reset) begin
-      _T_1780 <= 2'h0;
-    end else if (obuf_wr_en) begin
-      if (ibuf_buf_byp) begin
-        _T_1780 <= WrPtr0_r;
-      end else begin
-        _T_1780 <= CmdPtr0;
-      end
-    end
-  end
-  always @(posedge io_lsu_bus_obuf_c1_clk or posedge reset) begin
-    if (reset) begin
-      obuf_merge <= 1'h0;
-    end else if (obuf_wr_en) begin
-      obuf_merge <= obuf_merge_en;
-    end
-  end
-  always @(posedge io_lsu_bus_obuf_c1_clk or posedge reset) begin
-    if (reset) begin
-      obuf_tag1 <= 2'h0;
-    end else if (obuf_wr_en) begin
-      if (ibuf_buf_byp) begin
-        obuf_tag1 <= WrPtr1_r;
-      end else begin
-        obuf_tag1 <= CmdPtr1;
-      end
+      buf_ageQ_3 <= {_T_2474,_T_2397};
     end
   end
   always @(posedge io_lsu_free_c2_clk or posedge reset) begin
@@ -8991,20 +8595,15 @@ end // initial
       obuf_valid <= _T_1771 & _T_1772;
     end
   end
-  always @(posedge io_lsu_busm_clk or posedge reset) begin
-    if (reset) begin
-      obuf_wr_enQ <= 1'h0;
-    end else begin
-      obuf_wr_enQ <= _T_1238 & io_lsu_bus_clk_en;
-    end
-  end
-  always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
+  always @(posedge clock or posedge reset) begin
     if (reset) begin
       ibuf_addr <= 32'h0;
-    end else if (io_ldst_dual_r) begin
-      ibuf_addr <= io_end_addr_r;
-    end else begin
-      ibuf_addr <= io_lsu_addr_r;
+    end else if (ibuf_wr_en) begin
+      if (io_ldst_dual_r) begin
+        ibuf_addr <= io_end_addr_r;
+      end else begin
+        ibuf_addr <= io_lsu_addr_r;
+      end
     end
   end
   always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin
@@ -9038,160 +8637,168 @@ end // initial
     if (reset) begin
       buf_ageQ_2 <= 4'h0;
     end else begin
-      buf_ageQ_2 <= {_T_2365,_T_2288};
+      buf_ageQ_2 <= {_T_2372,_T_2295};
     end
   end
   always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
     if (reset) begin
       buf_ageQ_1 <= 4'h0;
     end else begin
-      buf_ageQ_1 <= {_T_2263,_T_2186};
+      buf_ageQ_1 <= {_T_2270,_T_2193};
     end
   end
   always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
     if (reset) begin
       buf_ageQ_0 <= 4'h0;
     end else begin
-      buf_ageQ_0 <= {_T_2161,_T_2084};
+      buf_ageQ_0 <= {_T_2168,_T_2091};
     end
   end
-  always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin
+  always @(posedge clock or posedge reset) begin
     if (reset) begin
       buf_data_0 <= 32'h0;
-    end else if (_T_3524) begin
-      if (_T_3539) begin
-        buf_data_0 <= ibuf_data_out;
-      end else begin
-        buf_data_0 <= store_data_lo_r;
-      end
-    end else if (_T_3547) begin
-      buf_data_0 <= 32'h0;
-    end else if (_T_3551) begin
-      if (buf_error_en_0) begin
-        buf_data_0 <= io_lsu_axi_r_bits_data[31:0];
-      end else if (buf_addr_0[2]) begin
-        buf_data_0 <= io_lsu_axi_r_bits_data[63:32];
-      end else begin
-        buf_data_0 <= io_lsu_axi_r_bits_data[31:0];
-      end
-    end else if (_T_3585) begin
-      if (_T_3662) begin
-        if (buf_addr_0[2]) begin
+    end else if (buf_data_en_0) begin
+      if (_T_3531) begin
+        if (_T_3546) begin
+          buf_data_0 <= ibuf_data_out;
+        end else begin
+          buf_data_0 <= store_data_lo_r;
+        end
+      end else if (_T_3554) begin
+        buf_data_0 <= 32'h0;
+      end else if (_T_3558) begin
+        if (buf_error_en_0) begin
+          buf_data_0 <= io_lsu_axi_r_bits_data[31:0];
+        end else if (buf_addr_0[2]) begin
           buf_data_0 <= io_lsu_axi_r_bits_data[63:32];
         end else begin
           buf_data_0 <= io_lsu_axi_r_bits_data[31:0];
         end
+      end else if (_T_3592) begin
+        if (_T_3670) begin
+          if (buf_addr_0[2]) begin
+            buf_data_0 <= io_lsu_axi_r_bits_data[63:32];
+          end else begin
+            buf_data_0 <= io_lsu_axi_r_bits_data[31:0];
+          end
+        end else begin
+          buf_data_0 <= io_lsu_axi_r_bits_data[31:0];
+        end
       end else begin
-        buf_data_0 <= io_lsu_axi_r_bits_data[31:0];
+        buf_data_0 <= 32'h0;
       end
-    end else begin
-      buf_data_0 <= 32'h0;
     end
   end
-  always @(posedge rvclkhdr_9_io_l1clk or posedge reset) begin
+  always @(posedge clock or posedge reset) begin
     if (reset) begin
       buf_data_1 <= 32'h0;
-    end else if (_T_3714) begin
-      if (_T_3729) begin
-        buf_data_1 <= ibuf_data_out;
-      end else begin
-        buf_data_1 <= store_data_lo_r;
-      end
-    end else if (_T_3737) begin
-      buf_data_1 <= 32'h0;
-    end else if (_T_3741) begin
-      if (buf_error_en_1) begin
-        buf_data_1 <= io_lsu_axi_r_bits_data[31:0];
-      end else if (buf_addr_1[2]) begin
-        buf_data_1 <= io_lsu_axi_r_bits_data[63:32];
-      end else begin
-        buf_data_1 <= io_lsu_axi_r_bits_data[31:0];
-      end
-    end else if (_T_3775) begin
-      if (_T_3852) begin
-        if (buf_addr_1[2]) begin
+    end else if (buf_data_en_1) begin
+      if (_T_3722) begin
+        if (_T_3737) begin
+          buf_data_1 <= ibuf_data_out;
+        end else begin
+          buf_data_1 <= store_data_lo_r;
+        end
+      end else if (_T_3745) begin
+        buf_data_1 <= 32'h0;
+      end else if (_T_3749) begin
+        if (buf_error_en_1) begin
+          buf_data_1 <= io_lsu_axi_r_bits_data[31:0];
+        end else if (buf_addr_1[2]) begin
           buf_data_1 <= io_lsu_axi_r_bits_data[63:32];
         end else begin
           buf_data_1 <= io_lsu_axi_r_bits_data[31:0];
         end
+      end else if (_T_3783) begin
+        if (_T_3861) begin
+          if (buf_addr_1[2]) begin
+            buf_data_1 <= io_lsu_axi_r_bits_data[63:32];
+          end else begin
+            buf_data_1 <= io_lsu_axi_r_bits_data[31:0];
+          end
+        end else begin
+          buf_data_1 <= io_lsu_axi_r_bits_data[31:0];
+        end
       end else begin
-        buf_data_1 <= io_lsu_axi_r_bits_data[31:0];
+        buf_data_1 <= 32'h0;
       end
-    end else begin
-      buf_data_1 <= 32'h0;
     end
   end
-  always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin
+  always @(posedge clock or posedge reset) begin
     if (reset) begin
       buf_data_2 <= 32'h0;
-    end else if (_T_3904) begin
-      if (_T_3919) begin
-        buf_data_2 <= ibuf_data_out;
-      end else begin
-        buf_data_2 <= store_data_lo_r;
-      end
-    end else if (_T_3927) begin
-      buf_data_2 <= 32'h0;
-    end else if (_T_3931) begin
-      if (buf_error_en_2) begin
-        buf_data_2 <= io_lsu_axi_r_bits_data[31:0];
-      end else if (buf_addr_2[2]) begin
-        buf_data_2 <= io_lsu_axi_r_bits_data[63:32];
-      end else begin
-        buf_data_2 <= io_lsu_axi_r_bits_data[31:0];
-      end
-    end else if (_T_3965) begin
-      if (_T_4042) begin
-        if (buf_addr_2[2]) begin
+    end else if (buf_data_en_2) begin
+      if (_T_3913) begin
+        if (_T_3928) begin
+          buf_data_2 <= ibuf_data_out;
+        end else begin
+          buf_data_2 <= store_data_lo_r;
+        end
+      end else if (_T_3936) begin
+        buf_data_2 <= 32'h0;
+      end else if (_T_3940) begin
+        if (buf_error_en_2) begin
+          buf_data_2 <= io_lsu_axi_r_bits_data[31:0];
+        end else if (buf_addr_2[2]) begin
           buf_data_2 <= io_lsu_axi_r_bits_data[63:32];
         end else begin
           buf_data_2 <= io_lsu_axi_r_bits_data[31:0];
         end
+      end else if (_T_3974) begin
+        if (_T_4052) begin
+          if (buf_addr_2[2]) begin
+            buf_data_2 <= io_lsu_axi_r_bits_data[63:32];
+          end else begin
+            buf_data_2 <= io_lsu_axi_r_bits_data[31:0];
+          end
+        end else begin
+          buf_data_2 <= io_lsu_axi_r_bits_data[31:0];
+        end
       end else begin
-        buf_data_2 <= io_lsu_axi_r_bits_data[31:0];
+        buf_data_2 <= 32'h0;
       end
-    end else begin
-      buf_data_2 <= 32'h0;
     end
   end
-  always @(posedge rvclkhdr_11_io_l1clk or posedge reset) begin
+  always @(posedge clock or posedge reset) begin
     if (reset) begin
       buf_data_3 <= 32'h0;
-    end else if (_T_4094) begin
-      if (_T_4109) begin
-        buf_data_3 <= ibuf_data_out;
-      end else begin
-        buf_data_3 <= store_data_lo_r;
-      end
-    end else if (_T_4117) begin
-      buf_data_3 <= 32'h0;
-    end else if (_T_4121) begin
-      if (buf_error_en_3) begin
-        buf_data_3 <= io_lsu_axi_r_bits_data[31:0];
-      end else if (buf_addr_3[2]) begin
-        buf_data_3 <= io_lsu_axi_r_bits_data[63:32];
-      end else begin
-        buf_data_3 <= io_lsu_axi_r_bits_data[31:0];
-      end
-    end else if (_T_4155) begin
-      if (_T_4232) begin
-        if (buf_addr_3[2]) begin
+    end else if (buf_data_en_3) begin
+      if (_T_4104) begin
+        if (_T_4119) begin
+          buf_data_3 <= ibuf_data_out;
+        end else begin
+          buf_data_3 <= store_data_lo_r;
+        end
+      end else if (_T_4127) begin
+        buf_data_3 <= 32'h0;
+      end else if (_T_4131) begin
+        if (buf_error_en_3) begin
+          buf_data_3 <= io_lsu_axi_r_bits_data[31:0];
+        end else if (buf_addr_3[2]) begin
           buf_data_3 <= io_lsu_axi_r_bits_data[63:32];
         end else begin
           buf_data_3 <= io_lsu_axi_r_bits_data[31:0];
         end
+      end else if (_T_4165) begin
+        if (_T_4243) begin
+          if (buf_addr_3[2]) begin
+            buf_data_3 <= io_lsu_axi_r_bits_data[63:32];
+          end else begin
+            buf_data_3 <= io_lsu_axi_r_bits_data[31:0];
+          end
+        end else begin
+          buf_data_3 <= io_lsu_axi_r_bits_data[31:0];
+        end
       end else begin
-        buf_data_3 <= io_lsu_axi_r_bits_data[31:0];
+        buf_data_3 <= 32'h0;
       end
-    end else begin
-      buf_data_3 <= 32'h0;
     end
   end
-  always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin
+  always @(posedge clock or posedge reset) begin
     if (reset) begin
       ibuf_data <= 32'h0;
-    end else begin
-      ibuf_data <= {_T_922,_T_893};
+    end else if (ibuf_wr_en) begin
+      ibuf_data <= ibuf_data_in;
     end
   end
   always @(posedge io_lsu_free_c2_clk or posedge reset) begin
@@ -9213,11 +8820,11 @@ end // initial
   always @(posedge io_lsu_c2_r_clk or posedge reset) begin
     if (reset) begin
       WrPtr1_r <= 2'h0;
-    end else if (_T_1846) begin
+    end else if (_T_1853) begin
       WrPtr1_r <= 2'h0;
-    end else if (_T_1860) begin
+    end else if (_T_1867) begin
       WrPtr1_r <= 2'h1;
-    end else if (_T_1874) begin
+    end else if (_T_1881) begin
       WrPtr1_r <= 2'h2;
     end else begin
       WrPtr1_r <= 2'h3;
@@ -9226,11 +8833,11 @@ end // initial
   always @(posedge io_lsu_c2_r_clk or posedge reset) begin
     if (reset) begin
       WrPtr0_r <= 2'h0;
-    end else if (_T_1795) begin
+    end else if (_T_1802) begin
       WrPtr0_r <= 2'h0;
-    end else if (_T_1806) begin
+    end else if (_T_1813) begin
       WrPtr0_r <= 2'h1;
-    end else if (_T_1817) begin
+    end else if (_T_1824) begin
       WrPtr0_r <= 2'h2;
     end else begin
       WrPtr0_r <= 2'h3;
@@ -9291,13 +8898,11 @@ end // initial
       ibuf_sz <= ibuf_sz_in;
     end
   end
-  always @(posedge io_lsu_busm_clk or posedge reset) begin
+  always @(posedge clock or posedge reset) begin
     if (reset) begin
-      obuf_wr_timer <= 3'h0;
+      _T_1791 <= 1'h0;
     end else if (obuf_wr_en) begin
-      obuf_wr_timer <= 3'h0;
-    end else if (_T_1058) begin
-      obuf_wr_timer <= _T_1060;
+      _T_1791 <= obuf_data_done_in;
     end
   end
   always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
@@ -9330,41 +8935,30 @@ end // initial
   end
   always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
     if (reset) begin
-      _T_4314 <= 1'h0;
+      _T_4325 <= 1'h0;
     end else if (buf_wr_en_3) begin
-      _T_4314 <= buf_sideeffect_in[3];
+      _T_4325 <= buf_sideeffect_in[3];
     end
   end
   always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
     if (reset) begin
-      _T_4311 <= 1'h0;
+      _T_4322 <= 1'h0;
     end else if (buf_wr_en_2) begin
-      _T_4311 <= buf_sideeffect_in[2];
+      _T_4322 <= buf_sideeffect_in[2];
     end
   end
   always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
     if (reset) begin
-      _T_4308 <= 1'h0;
+      _T_4319 <= 1'h0;
     end else if (buf_wr_en_1) begin
-      _T_4308 <= buf_sideeffect_in[1];
+      _T_4319 <= buf_sideeffect_in[1];
     end
   end
   always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
     if (reset) begin
-      _T_4305 <= 1'h0;
+      _T_4316 <= 1'h0;
     end else if (buf_wr_en_0) begin
-      _T_4305 <= buf_sideeffect_in[0];
-    end
-  end
-  always @(posedge io_lsu_bus_obuf_c1_clk or posedge reset) begin
-    if (reset) begin
-      obuf_sideeffect <= 1'h0;
-    end else if (obuf_wr_en) begin
-      if (ibuf_buf_byp) begin
-        obuf_sideeffect <= io_is_sideeffects_r;
-      end else begin
-        obuf_sideeffect <= _T_1051;
-      end
+      _T_4316 <= buf_sideeffect_in[0];
     end
   end
   always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
@@ -9423,31 +9017,6 @@ end // initial
       buf_samedw_0 <= buf_samedw_in[0];
     end
   end
-  always @(posedge io_lsu_bus_obuf_c1_clk or posedge reset) begin
-    if (reset) begin
-      obuf_write <= 1'h0;
-    end else if (obuf_wr_en) begin
-      if (ibuf_buf_byp) begin
-        obuf_write <= io_lsu_pkt_r_bits_store;
-      end else begin
-        obuf_write <= _T_1202;
-      end
-    end
-  end
-  always @(posedge io_lsu_busm_clk or posedge reset) begin
-    if (reset) begin
-      obuf_cmd_done <= 1'h0;
-    end else begin
-      obuf_cmd_done <= _T_1303 & _T_4821;
-    end
-  end
-  always @(posedge io_lsu_busm_clk or posedge reset) begin
-    if (reset) begin
-      obuf_data_done <= 1'h0;
-    end else begin
-      obuf_data_done <= _T_1303 & _T_4822;
-    end
-  end
   always @(posedge io_lsu_free_c2_clk or posedge reset) begin
     if (reset) begin
       obuf_nosend <= 1'h0;
@@ -9455,13 +9024,15 @@ end // initial
       obuf_nosend <= obuf_nosend_in;
     end
   end
-  always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
+  always @(posedge clock or posedge reset) begin
     if (reset) begin
       obuf_addr <= 32'h0;
-    end else if (ibuf_buf_byp) begin
-      obuf_addr <= io_lsu_addr_r;
-    end else begin
-      obuf_addr <= _T_1287;
+    end else if (obuf_wr_en) begin
+      if (ibuf_buf_byp) begin
+        obuf_addr <= io_lsu_addr_r;
+      end else begin
+        obuf_addr <= _T_1287;
+      end
     end
   end
   always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
@@ -9508,18 +9079,11 @@ end // initial
       end
     end
   end
-  always @(posedge io_lsu_busm_clk or posedge reset) begin
+  always @(posedge io_lsu_free_c2_clk or posedge reset) begin
     if (reset) begin
       obuf_rdrsp_pend <= 1'h0;
-    end else begin
-      obuf_rdrsp_pend <= _T_1331 & _T_2587;
-    end
-  end
-  always @(posedge io_lsu_busm_clk or posedge reset) begin
-    if (reset) begin
-      obuf_rdrsp_tag <= 3'h0;
-    end else if (_T_1330) begin
-      obuf_rdrsp_tag <= obuf_tag0;
+    end else if (obuf_rdrsp_pend_en) begin
+      obuf_rdrsp_pend <= obuf_rdrsp_pend_in;
     end
   end
   always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
@@ -9550,123 +9114,90 @@ end // initial
       buf_dualhi_0 <= buf_dualhi_in[0];
     end
   end
-  always @(posedge io_lsu_bus_obuf_c1_clk or posedge reset) begin
-    if (reset) begin
-      obuf_sz <= 2'h0;
-    end else if (obuf_wr_en) begin
-      if (ibuf_buf_byp) begin
-        obuf_sz <= ibuf_sz_in;
-      end else begin
-        obuf_sz <= _T_1300;
-      end
-    end
-  end
-  always @(posedge io_lsu_bus_obuf_c1_clk or posedge reset) begin
-    if (reset) begin
-      obuf_byteen <= 8'h0;
-    end else if (obuf_wr_en) begin
-      obuf_byteen <= obuf_byteen_in;
-    end
-  end
-  always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin
+  always @(posedge clock or posedge reset) begin
     if (reset) begin
       obuf_data <= 64'h0;
-    end else begin
-      obuf_data <= {_T_1618,_T_1577};
+    end else if (obuf_wr_en) begin
+      obuf_data <= obuf_data_in;
     end
   end
   always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
     if (reset) begin
       buf_rspageQ_0 <= 4'h0;
     end else begin
-      buf_rspageQ_0 <= {_T_3137,_T_3126};
+      buf_rspageQ_0 <= {_T_3144,_T_3133};
     end
   end
   always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
     if (reset) begin
       buf_rspageQ_1 <= 4'h0;
     end else begin
-      buf_rspageQ_1 <= {_T_3152,_T_3141};
+      buf_rspageQ_1 <= {_T_3159,_T_3148};
     end
   end
   always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
     if (reset) begin
       buf_rspageQ_2 <= 4'h0;
     end else begin
-      buf_rspageQ_2 <= {_T_3167,_T_3156};
+      buf_rspageQ_2 <= {_T_3174,_T_3163};
     end
   end
   always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
     if (reset) begin
       buf_rspageQ_3 <= 4'h0;
     end else begin
-      buf_rspageQ_3 <= {_T_3182,_T_3171};
+      buf_rspageQ_3 <= {_T_3189,_T_3178};
     end
   end
   always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
     if (reset) begin
-      _T_4291 <= 1'h0;
+      _T_4302 <= 1'h0;
     end else if (buf_ldfwd_en_3) begin
-      if (_T_4094) begin
-        _T_4291 <= 1'h0;
-      end else if (_T_4117) begin
-        _T_4291 <= 1'h0;
+      if (_T_4104) begin
+        _T_4302 <= 1'h0;
+      end else if (_T_4127) begin
+        _T_4302 <= 1'h0;
       end else begin
-        _T_4291 <= _T_4121;
+        _T_4302 <= _T_4131;
       end
     end
   end
   always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
     if (reset) begin
-      _T_4289 <= 1'h0;
+      _T_4300 <= 1'h0;
     end else if (buf_ldfwd_en_2) begin
-      if (_T_3904) begin
-        _T_4289 <= 1'h0;
-      end else if (_T_3927) begin
-        _T_4289 <= 1'h0;
+      if (_T_3913) begin
+        _T_4300 <= 1'h0;
+      end else if (_T_3936) begin
+        _T_4300 <= 1'h0;
       end else begin
-        _T_4289 <= _T_3931;
+        _T_4300 <= _T_3940;
       end
     end
   end
   always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
     if (reset) begin
-      _T_4287 <= 1'h0;
+      _T_4298 <= 1'h0;
     end else if (buf_ldfwd_en_1) begin
-      if (_T_3714) begin
-        _T_4287 <= 1'h0;
-      end else if (_T_3737) begin
-        _T_4287 <= 1'h0;
+      if (_T_3722) begin
+        _T_4298 <= 1'h0;
+      end else if (_T_3745) begin
+        _T_4298 <= 1'h0;
       end else begin
-        _T_4287 <= _T_3741;
+        _T_4298 <= _T_3749;
       end
     end
   end
   always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
     if (reset) begin
-      _T_4285 <= 1'h0;
+      _T_4296 <= 1'h0;
     end else if (buf_ldfwd_en_0) begin
-      if (_T_3524) begin
-        _T_4285 <= 1'h0;
-      end else if (_T_3547) begin
-        _T_4285 <= 1'h0;
+      if (_T_3531) begin
+        _T_4296 <= 1'h0;
+      end else if (_T_3554) begin
+        _T_4296 <= 1'h0;
       end else begin
-        _T_4285 <= _T_3551;
-      end
-    end
-  end
-  always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
-    if (reset) begin
-      buf_ldfwdtag_0 <= 2'h0;
-    end else if (buf_ldfwd_en_0) begin
-      if (_T_3524) begin
-        buf_ldfwdtag_0 <= 2'h0;
-      end else if (_T_3547) begin
-        buf_ldfwdtag_0 <= 2'h0;
-      end else if (_T_3551) begin
-        buf_ldfwdtag_0 <= obuf_rdrsp_tag[1:0];
-      end else begin
-        buf_ldfwdtag_0 <= 2'h0;
+        _T_4296 <= _T_3558;
       end
     end
   end
@@ -9676,65 +9207,20 @@ end // initial
     end else if (buf_wr_en_0) begin
       if (ibuf_drainvec_vld[0]) begin
         buf_dualtag_0 <= ibuf_dualtag;
-      end else if (_T_3339) begin
+      end else if (_T_3346) begin
         buf_dualtag_0 <= WrPtr0_r;
       end else begin
         buf_dualtag_0 <= WrPtr1_r;
       end
     end
   end
-  always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
-    if (reset) begin
-      buf_ldfwdtag_3 <= 2'h0;
-    end else if (buf_ldfwd_en_3) begin
-      if (_T_4094) begin
-        buf_ldfwdtag_3 <= 2'h0;
-      end else if (_T_4117) begin
-        buf_ldfwdtag_3 <= 2'h0;
-      end else if (_T_4121) begin
-        buf_ldfwdtag_3 <= obuf_rdrsp_tag[1:0];
-      end else begin
-        buf_ldfwdtag_3 <= 2'h0;
-      end
-    end
-  end
-  always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
-    if (reset) begin
-      buf_ldfwdtag_2 <= 2'h0;
-    end else if (buf_ldfwd_en_2) begin
-      if (_T_3904) begin
-        buf_ldfwdtag_2 <= 2'h0;
-      end else if (_T_3927) begin
-        buf_ldfwdtag_2 <= 2'h0;
-      end else if (_T_3931) begin
-        buf_ldfwdtag_2 <= obuf_rdrsp_tag[1:0];
-      end else begin
-        buf_ldfwdtag_2 <= 2'h0;
-      end
-    end
-  end
-  always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
-    if (reset) begin
-      buf_ldfwdtag_1 <= 2'h0;
-    end else if (buf_ldfwd_en_1) begin
-      if (_T_3714) begin
-        buf_ldfwdtag_1 <= 2'h0;
-      end else if (_T_3737) begin
-        buf_ldfwdtag_1 <= 2'h0;
-      end else if (_T_3741) begin
-        buf_ldfwdtag_1 <= obuf_rdrsp_tag[1:0];
-      end else begin
-        buf_ldfwdtag_1 <= 2'h0;
-      end
-    end
-  end
   always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
     if (reset) begin
       buf_dualtag_1 <= 2'h0;
     end else if (buf_wr_en_1) begin
       if (ibuf_drainvec_vld[1]) begin
         buf_dualtag_1 <= ibuf_dualtag;
-      end else if (_T_3348) begin
+      end else if (_T_3355) begin
         buf_dualtag_1 <= WrPtr0_r;
       end else begin
         buf_dualtag_1 <= WrPtr1_r;
@@ -9747,7 +9233,7 @@ end // initial
     end else if (buf_wr_en_2) begin
       if (ibuf_drainvec_vld[2]) begin
         buf_dualtag_2 <= ibuf_dualtag;
-      end else if (_T_3357) begin
+      end else if (_T_3364) begin
         buf_dualtag_2 <= WrPtr0_r;
       end else begin
         buf_dualtag_2 <= WrPtr1_r;
@@ -9760,7 +9246,7 @@ end // initial
     end else if (buf_wr_en_3) begin
       if (ibuf_drainvec_vld[3]) begin
         buf_dualtag_3 <= ibuf_dualtag;
-      end else if (_T_3366) begin
+      end else if (_T_3373) begin
         buf_dualtag_3 <= WrPtr0_r;
       end else begin
         buf_dualtag_3 <= WrPtr1_r;
@@ -9769,58 +9255,58 @@ end // initial
   end
   always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
     if (reset) begin
-      _T_4320 <= 1'h0;
+      _T_4331 <= 1'h0;
     end else if (buf_wr_en_0) begin
-      _T_4320 <= buf_unsign_in[0];
+      _T_4331 <= buf_unsign_in[0];
     end
   end
   always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
     if (reset) begin
-      _T_4323 <= 1'h0;
+      _T_4334 <= 1'h0;
     end else if (buf_wr_en_1) begin
-      _T_4323 <= buf_unsign_in[1];
+      _T_4334 <= buf_unsign_in[1];
     end
   end
   always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
     if (reset) begin
-      _T_4326 <= 1'h0;
+      _T_4337 <= 1'h0;
     end else if (buf_wr_en_2) begin
-      _T_4326 <= buf_unsign_in[2];
+      _T_4337 <= buf_unsign_in[2];
     end
   end
   always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
     if (reset) begin
-      _T_4329 <= 1'h0;
+      _T_4340 <= 1'h0;
     end else if (buf_wr_en_3) begin
-      _T_4329 <= buf_unsign_in[3];
+      _T_4340 <= buf_unsign_in[3];
     end
   end
   always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
     if (reset) begin
-      _T_4395 <= 1'h0;
+      _T_4406 <= 1'h0;
     end else begin
-      _T_4395 <= _T_4392 & _T_4393;
+      _T_4406 <= _T_4402 & _T_4404;
     end
   end
   always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
     if (reset) begin
-      _T_4390 <= 1'h0;
+      _T_4401 <= 1'h0;
     end else begin
-      _T_4390 <= _T_4387 & _T_4388;
+      _T_4401 <= _T_4397 & _T_4399;
     end
   end
   always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
     if (reset) begin
-      _T_4385 <= 1'h0;
+      _T_4396 <= 1'h0;
     end else begin
-      _T_4385 <= _T_4382 & _T_4383;
+      _T_4396 <= _T_4392 & _T_4394;
     end
   end
   always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin
     if (reset) begin
-      _T_4380 <= 1'h0;
+      _T_4391 <= 1'h0;
     end else begin
-      _T_4380 <= _T_4377 & _T_4378;
+      _T_4391 <= _T_4387 & _T_4389;
     end
   end
   always @(posedge io_lsu_c2_r_clk or posedge reset) begin
@@ -9832,16 +9318,15 @@ end // initial
   end
   always @(posedge io_lsu_c2_r_clk or posedge reset) begin
     if (reset) begin
-      _T_4945 <= 1'h0;
+      _T_4956 <= 1'h0;
     end else begin
-      _T_4945 <= _T_4942 & _T_4502;
+      _T_4956 <= _T_4953 & _T_4513;
     end
   end
 endmodule
 module lsu_bus_intf(
   input         clock,
   input         reset,
-  input         io_scan_mode,
   output        io_tlu_busbuff_lsu_pmu_bus_trxn,
   output        io_tlu_busbuff_lsu_pmu_bus_misaligned,
   output        io_tlu_busbuff_lsu_pmu_bus_error,
@@ -9855,32 +9340,21 @@ module lsu_bus_intf(
   input         io_lsu_c1_r_clk,
   input         io_lsu_c2_r_clk,
   input         io_lsu_bus_ibuf_c1_clk,
-  input         io_lsu_bus_obuf_c1_clk,
   input         io_lsu_bus_buf_c1_clk,
   input         io_lsu_free_c2_clk,
   input         io_active_clk,
-  input         io_lsu_busm_clk,
   input         io_axi_aw_ready,
-  output        io_axi_aw_valid,
-  output [2:0]  io_axi_aw_bits_id,
   output [31:0] io_axi_aw_bits_addr,
   output [3:0]  io_axi_aw_bits_region,
-  output [2:0]  io_axi_aw_bits_size,
-  output [3:0]  io_axi_aw_bits_cache,
   input         io_axi_w_ready,
-  output        io_axi_w_valid,
   output [63:0] io_axi_w_bits_data,
-  output [7:0]  io_axi_w_bits_strb,
   input         io_axi_b_valid,
   input  [1:0]  io_axi_b_bits_resp,
   input  [2:0]  io_axi_b_bits_id,
   input         io_axi_ar_ready,
   output        io_axi_ar_valid,
-  output [2:0]  io_axi_ar_bits_id,
   output [31:0] io_axi_ar_bits_addr,
   output [3:0]  io_axi_ar_bits_region,
-  output [2:0]  io_axi_ar_bits_size,
-  output [3:0]  io_axi_ar_bits_cache,
   input         io_axi_r_valid,
   input  [2:0]  io_axi_r_bits_id,
   input  [63:0] io_axi_r_bits_data,
@@ -9934,7 +9408,6 @@ module lsu_bus_intf(
 `endif // RANDOMIZE_REG_INIT
   wire  bus_buffer_clock; // @[lsu_bus_intf.scala 100:39]
   wire  bus_buffer_reset; // @[lsu_bus_intf.scala 100:39]
-  wire  bus_buffer_io_scan_mode; // @[lsu_bus_intf.scala 100:39]
   wire  bus_buffer_io_tlu_busbuff_lsu_pmu_bus_trxn; // @[lsu_bus_intf.scala 100:39]
   wire  bus_buffer_io_tlu_busbuff_lsu_pmu_bus_misaligned; // @[lsu_bus_intf.scala 100:39]
   wire  bus_buffer_io_tlu_busbuff_lsu_pmu_bus_error; // @[lsu_bus_intf.scala 100:39]
@@ -9956,10 +9429,8 @@ module lsu_bus_intf(
   wire  bus_buffer_io_dec_tlu_force_halt; // @[lsu_bus_intf.scala 100:39]
   wire  bus_buffer_io_lsu_c2_r_clk; // @[lsu_bus_intf.scala 100:39]
   wire  bus_buffer_io_lsu_bus_ibuf_c1_clk; // @[lsu_bus_intf.scala 100:39]
-  wire  bus_buffer_io_lsu_bus_obuf_c1_clk; // @[lsu_bus_intf.scala 100:39]
   wire  bus_buffer_io_lsu_bus_buf_c1_clk; // @[lsu_bus_intf.scala 100:39]
   wire  bus_buffer_io_lsu_free_c2_clk; // @[lsu_bus_intf.scala 100:39]
-  wire  bus_buffer_io_lsu_busm_clk; // @[lsu_bus_intf.scala 100:39]
   wire  bus_buffer_io_dec_lsu_valid_raw_d; // @[lsu_bus_intf.scala 100:39]
   wire  bus_buffer_io_lsu_pkt_m_valid; // @[lsu_bus_intf.scala 100:39]
   wire  bus_buffer_io_lsu_pkt_m_bits_load; // @[lsu_bus_intf.scala 100:39]
@@ -9988,26 +9459,19 @@ module lsu_bus_intf(
   wire [7:0] bus_buffer_io_ldst_byteen_ext_m; // @[lsu_bus_intf.scala 100:39]
   wire  bus_buffer_io_lsu_axi_aw_ready; // @[lsu_bus_intf.scala 100:39]
   wire  bus_buffer_io_lsu_axi_aw_valid; // @[lsu_bus_intf.scala 100:39]
-  wire [2:0] bus_buffer_io_lsu_axi_aw_bits_id; // @[lsu_bus_intf.scala 100:39]
   wire [31:0] bus_buffer_io_lsu_axi_aw_bits_addr; // @[lsu_bus_intf.scala 100:39]
   wire [3:0] bus_buffer_io_lsu_axi_aw_bits_region; // @[lsu_bus_intf.scala 100:39]
-  wire [2:0] bus_buffer_io_lsu_axi_aw_bits_size; // @[lsu_bus_intf.scala 100:39]
-  wire [3:0] bus_buffer_io_lsu_axi_aw_bits_cache; // @[lsu_bus_intf.scala 100:39]
   wire  bus_buffer_io_lsu_axi_w_ready; // @[lsu_bus_intf.scala 100:39]
   wire  bus_buffer_io_lsu_axi_w_valid; // @[lsu_bus_intf.scala 100:39]
   wire [63:0] bus_buffer_io_lsu_axi_w_bits_data; // @[lsu_bus_intf.scala 100:39]
-  wire [7:0] bus_buffer_io_lsu_axi_w_bits_strb; // @[lsu_bus_intf.scala 100:39]
   wire  bus_buffer_io_lsu_axi_b_ready; // @[lsu_bus_intf.scala 100:39]
   wire  bus_buffer_io_lsu_axi_b_valid; // @[lsu_bus_intf.scala 100:39]
   wire [1:0] bus_buffer_io_lsu_axi_b_bits_resp; // @[lsu_bus_intf.scala 100:39]
   wire [2:0] bus_buffer_io_lsu_axi_b_bits_id; // @[lsu_bus_intf.scala 100:39]
   wire  bus_buffer_io_lsu_axi_ar_ready; // @[lsu_bus_intf.scala 100:39]
   wire  bus_buffer_io_lsu_axi_ar_valid; // @[lsu_bus_intf.scala 100:39]
-  wire [2:0] bus_buffer_io_lsu_axi_ar_bits_id; // @[lsu_bus_intf.scala 100:39]
   wire [31:0] bus_buffer_io_lsu_axi_ar_bits_addr; // @[lsu_bus_intf.scala 100:39]
   wire [3:0] bus_buffer_io_lsu_axi_ar_bits_region; // @[lsu_bus_intf.scala 100:39]
-  wire [2:0] bus_buffer_io_lsu_axi_ar_bits_size; // @[lsu_bus_intf.scala 100:39]
-  wire [3:0] bus_buffer_io_lsu_axi_ar_bits_cache; // @[lsu_bus_intf.scala 100:39]
   wire  bus_buffer_io_lsu_axi_r_ready; // @[lsu_bus_intf.scala 100:39]
   wire  bus_buffer_io_lsu_axi_r_valid; // @[lsu_bus_intf.scala 100:39]
   wire [2:0] bus_buffer_io_lsu_axi_r_bits_id; // @[lsu_bus_intf.scala 100:39]
@@ -10205,7 +9669,6 @@ module lsu_bus_intf(
   lsu_bus_buffer bus_buffer ( // @[lsu_bus_intf.scala 100:39]
     .clock(bus_buffer_clock),
     .reset(bus_buffer_reset),
-    .io_scan_mode(bus_buffer_io_scan_mode),
     .io_tlu_busbuff_lsu_pmu_bus_trxn(bus_buffer_io_tlu_busbuff_lsu_pmu_bus_trxn),
     .io_tlu_busbuff_lsu_pmu_bus_misaligned(bus_buffer_io_tlu_busbuff_lsu_pmu_bus_misaligned),
     .io_tlu_busbuff_lsu_pmu_bus_error(bus_buffer_io_tlu_busbuff_lsu_pmu_bus_error),
@@ -10227,10 +9690,8 @@ module lsu_bus_intf(
     .io_dec_tlu_force_halt(bus_buffer_io_dec_tlu_force_halt),
     .io_lsu_c2_r_clk(bus_buffer_io_lsu_c2_r_clk),
     .io_lsu_bus_ibuf_c1_clk(bus_buffer_io_lsu_bus_ibuf_c1_clk),
-    .io_lsu_bus_obuf_c1_clk(bus_buffer_io_lsu_bus_obuf_c1_clk),
     .io_lsu_bus_buf_c1_clk(bus_buffer_io_lsu_bus_buf_c1_clk),
     .io_lsu_free_c2_clk(bus_buffer_io_lsu_free_c2_clk),
-    .io_lsu_busm_clk(bus_buffer_io_lsu_busm_clk),
     .io_dec_lsu_valid_raw_d(bus_buffer_io_dec_lsu_valid_raw_d),
     .io_lsu_pkt_m_valid(bus_buffer_io_lsu_pkt_m_valid),
     .io_lsu_pkt_m_bits_load(bus_buffer_io_lsu_pkt_m_bits_load),
@@ -10259,26 +9720,19 @@ module lsu_bus_intf(
     .io_ldst_byteen_ext_m(bus_buffer_io_ldst_byteen_ext_m),
     .io_lsu_axi_aw_ready(bus_buffer_io_lsu_axi_aw_ready),
     .io_lsu_axi_aw_valid(bus_buffer_io_lsu_axi_aw_valid),
-    .io_lsu_axi_aw_bits_id(bus_buffer_io_lsu_axi_aw_bits_id),
     .io_lsu_axi_aw_bits_addr(bus_buffer_io_lsu_axi_aw_bits_addr),
     .io_lsu_axi_aw_bits_region(bus_buffer_io_lsu_axi_aw_bits_region),
-    .io_lsu_axi_aw_bits_size(bus_buffer_io_lsu_axi_aw_bits_size),
-    .io_lsu_axi_aw_bits_cache(bus_buffer_io_lsu_axi_aw_bits_cache),
     .io_lsu_axi_w_ready(bus_buffer_io_lsu_axi_w_ready),
     .io_lsu_axi_w_valid(bus_buffer_io_lsu_axi_w_valid),
     .io_lsu_axi_w_bits_data(bus_buffer_io_lsu_axi_w_bits_data),
-    .io_lsu_axi_w_bits_strb(bus_buffer_io_lsu_axi_w_bits_strb),
     .io_lsu_axi_b_ready(bus_buffer_io_lsu_axi_b_ready),
     .io_lsu_axi_b_valid(bus_buffer_io_lsu_axi_b_valid),
     .io_lsu_axi_b_bits_resp(bus_buffer_io_lsu_axi_b_bits_resp),
     .io_lsu_axi_b_bits_id(bus_buffer_io_lsu_axi_b_bits_id),
     .io_lsu_axi_ar_ready(bus_buffer_io_lsu_axi_ar_ready),
     .io_lsu_axi_ar_valid(bus_buffer_io_lsu_axi_ar_valid),
-    .io_lsu_axi_ar_bits_id(bus_buffer_io_lsu_axi_ar_bits_id),
     .io_lsu_axi_ar_bits_addr(bus_buffer_io_lsu_axi_ar_bits_addr),
     .io_lsu_axi_ar_bits_region(bus_buffer_io_lsu_axi_ar_bits_region),
-    .io_lsu_axi_ar_bits_size(bus_buffer_io_lsu_axi_ar_bits_size),
-    .io_lsu_axi_ar_bits_cache(bus_buffer_io_lsu_axi_ar_bits_cache),
     .io_lsu_axi_r_ready(bus_buffer_io_lsu_axi_r_ready),
     .io_lsu_axi_r_valid(bus_buffer_io_lsu_axi_r_valid),
     .io_lsu_axi_r_bits_id(bus_buffer_io_lsu_axi_r_bits_id),
@@ -10302,21 +9756,12 @@ module lsu_bus_intf(
   assign io_tlu_busbuff_lsu_imprecise_error_load_any = bus_buffer_io_tlu_busbuff_lsu_imprecise_error_load_any; // @[lsu_bus_intf.scala 103:18]
   assign io_tlu_busbuff_lsu_imprecise_error_store_any = bus_buffer_io_tlu_busbuff_lsu_imprecise_error_store_any; // @[lsu_bus_intf.scala 103:18]
   assign io_tlu_busbuff_lsu_imprecise_error_addr_any = bus_buffer_io_tlu_busbuff_lsu_imprecise_error_addr_any; // @[lsu_bus_intf.scala 103:18]
-  assign io_axi_aw_valid = bus_buffer_io_lsu_axi_aw_valid; // @[lsu_bus_intf.scala 131:51]
-  assign io_axi_aw_bits_id = bus_buffer_io_lsu_axi_aw_bits_id; // @[lsu_bus_intf.scala 131:51]
   assign io_axi_aw_bits_addr = bus_buffer_io_lsu_axi_aw_bits_addr; // @[lsu_bus_intf.scala 131:51]
   assign io_axi_aw_bits_region = bus_buffer_io_lsu_axi_aw_bits_region; // @[lsu_bus_intf.scala 131:51]
-  assign io_axi_aw_bits_size = bus_buffer_io_lsu_axi_aw_bits_size; // @[lsu_bus_intf.scala 131:51]
-  assign io_axi_aw_bits_cache = bus_buffer_io_lsu_axi_aw_bits_cache; // @[lsu_bus_intf.scala 131:51]
-  assign io_axi_w_valid = bus_buffer_io_lsu_axi_w_valid; // @[lsu_bus_intf.scala 131:51]
   assign io_axi_w_bits_data = bus_buffer_io_lsu_axi_w_bits_data; // @[lsu_bus_intf.scala 131:51]
-  assign io_axi_w_bits_strb = bus_buffer_io_lsu_axi_w_bits_strb; // @[lsu_bus_intf.scala 131:51]
   assign io_axi_ar_valid = bus_buffer_io_lsu_axi_ar_valid; // @[lsu_bus_intf.scala 131:51]
-  assign io_axi_ar_bits_id = bus_buffer_io_lsu_axi_ar_bits_id; // @[lsu_bus_intf.scala 131:51]
   assign io_axi_ar_bits_addr = bus_buffer_io_lsu_axi_ar_bits_addr; // @[lsu_bus_intf.scala 131:51]
   assign io_axi_ar_bits_region = bus_buffer_io_lsu_axi_ar_bits_region; // @[lsu_bus_intf.scala 131:51]
-  assign io_axi_ar_bits_size = bus_buffer_io_lsu_axi_ar_bits_size; // @[lsu_bus_intf.scala 131:51]
-  assign io_axi_ar_bits_cache = bus_buffer_io_lsu_axi_ar_bits_cache; // @[lsu_bus_intf.scala 131:51]
   assign io_lsu_busreq_r = bus_buffer_io_lsu_busreq_r; // @[lsu_bus_intf.scala 134:38]
   assign io_lsu_bus_buffer_pend_any = bus_buffer_io_lsu_bus_buffer_pend_any; // @[lsu_bus_intf.scala 135:38]
   assign io_lsu_bus_buffer_full_any = bus_buffer_io_lsu_bus_buffer_full_any; // @[lsu_bus_intf.scala 136:38]
@@ -10332,17 +9777,14 @@ module lsu_bus_intf(
   assign io_dctl_busbuff_lsu_nonblock_load_data = bus_buffer_io_dctl_busbuff_lsu_nonblock_load_data; // @[lsu_bus_intf.scala 143:19]
   assign bus_buffer_clock = clock;
   assign bus_buffer_reset = reset;
-  assign bus_buffer_io_scan_mode = io_scan_mode; // @[lsu_bus_intf.scala 102:29]
   assign bus_buffer_io_tlu_busbuff_dec_tlu_external_ldfwd_disable = io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[lsu_bus_intf.scala 103:18]
   assign bus_buffer_io_tlu_busbuff_dec_tlu_wb_coalescing_disable = io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu_bus_intf.scala 103:18]
   assign bus_buffer_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable = io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_intf.scala 103:18]
   assign bus_buffer_io_dec_tlu_force_halt = io_dec_tlu_force_halt; // @[lsu_bus_intf.scala 107:51]
   assign bus_buffer_io_lsu_c2_r_clk = io_lsu_c2_r_clk; // @[lsu_bus_intf.scala 108:51]
   assign bus_buffer_io_lsu_bus_ibuf_c1_clk = io_lsu_bus_ibuf_c1_clk; // @[lsu_bus_intf.scala 109:51]
-  assign bus_buffer_io_lsu_bus_obuf_c1_clk = io_lsu_bus_obuf_c1_clk; // @[lsu_bus_intf.scala 110:51]
   assign bus_buffer_io_lsu_bus_buf_c1_clk = io_lsu_bus_buf_c1_clk; // @[lsu_bus_intf.scala 111:51]
   assign bus_buffer_io_lsu_free_c2_clk = io_lsu_free_c2_clk; // @[lsu_bus_intf.scala 112:51]
-  assign bus_buffer_io_lsu_busm_clk = io_lsu_busm_clk; // @[lsu_bus_intf.scala 113:51]
   assign bus_buffer_io_dec_lsu_valid_raw_d = io_dec_lsu_valid_raw_d; // @[lsu_bus_intf.scala 114:51]
   assign bus_buffer_io_lsu_pkt_m_valid = io_lsu_pkt_m_valid; // @[lsu_bus_intf.scala 117:27]
   assign bus_buffer_io_lsu_pkt_m_bits_load = io_lsu_pkt_m_bits_load; // @[lsu_bus_intf.scala 117:27]
@@ -10562,6 +10004,7 @@ module lsu(
   input  [11:0] io_dec_lsu_offset_d,
   input         io_lsu_p_valid,
   input         io_lsu_p_bits_fast_int,
+  input         io_lsu_p_bits_stack,
   input         io_lsu_p_bits_by,
   input         io_lsu_p_bits_half,
   input         io_lsu_p_bits_word,
@@ -10630,503 +10073,489 @@ module lsu(
   reg [31:0] _RAND_1;
   reg [31:0] _RAND_2;
 `endif // RANDOMIZE_REG_INIT
-  wire  lsu_lsc_ctl_clock; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_reset; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_clk_override; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_lsu_c1_m_clk; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_lsu_c1_r_clk; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_lsu_c2_m_clk; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_lsu_c2_r_clk; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_lsu_store_c1_m_clk; // @[lsu.scala 65:30]
-  wire [31:0] lsu_lsc_ctl_io_lsu_ld_data_corr_r; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_lsu_single_ecc_error_r; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_lsu_double_ecc_error_r; // @[lsu.scala 65:30]
-  wire [31:0] lsu_lsc_ctl_io_lsu_ld_data_m; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_lsu_single_ecc_error_m; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_lsu_double_ecc_error_m; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_flush_m_up; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_flush_r; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_ldst_dual_d; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_ldst_dual_m; // @[lsu.scala 65:30]
-  wire [31:0] lsu_lsc_ctl_io_lsu_exu_exu_lsu_rs1_d; // @[lsu.scala 65:30]
-  wire [31:0] lsu_lsc_ctl_io_lsu_exu_exu_lsu_rs2_d; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_lsu_p_valid; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_lsu_p_bits_fast_int; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_lsu_p_bits_by; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_lsu_p_bits_half; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_lsu_p_bits_word; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_lsu_p_bits_dword; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_lsu_p_bits_load; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_lsu_p_bits_store; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_lsu_p_bits_unsign; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_lsu_p_bits_dma; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_lsu_p_bits_store_data_bypass_d; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_lsu_p_bits_load_ldst_bypass_d; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_lsu_p_bits_store_data_bypass_m; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_dec_lsu_valid_raw_d; // @[lsu.scala 65:30]
-  wire [11:0] lsu_lsc_ctl_io_dec_lsu_offset_d; // @[lsu.scala 65:30]
-  wire [31:0] lsu_lsc_ctl_io_picm_mask_data_m; // @[lsu.scala 65:30]
-  wire [31:0] lsu_lsc_ctl_io_bus_read_data_m; // @[lsu.scala 65:30]
-  wire [31:0] lsu_lsc_ctl_io_lsu_result_m; // @[lsu.scala 65:30]
-  wire [31:0] lsu_lsc_ctl_io_lsu_result_corr_r; // @[lsu.scala 65:30]
-  wire [31:0] lsu_lsc_ctl_io_lsu_addr_d; // @[lsu.scala 65:30]
-  wire [31:0] lsu_lsc_ctl_io_lsu_addr_m; // @[lsu.scala 65:30]
-  wire [31:0] lsu_lsc_ctl_io_lsu_addr_r; // @[lsu.scala 65:30]
-  wire [31:0] lsu_lsc_ctl_io_end_addr_d; // @[lsu.scala 65:30]
-  wire [31:0] lsu_lsc_ctl_io_end_addr_m; // @[lsu.scala 65:30]
-  wire [31:0] lsu_lsc_ctl_io_end_addr_r; // @[lsu.scala 65:30]
-  wire [31:0] lsu_lsc_ctl_io_store_data_m; // @[lsu.scala 65:30]
-  wire [31:0] lsu_lsc_ctl_io_dec_tlu_mrac_ff; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_lsu_exc_m; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_is_sideeffects_m; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_lsu_commit_r; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_lsu_single_ecc_error_incr; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_lsu_error_pkt_r_valid; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_lsu_error_pkt_r_bits_single_ecc_error; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_lsu_error_pkt_r_bits_inst_type; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_lsu_error_pkt_r_bits_exc_type; // @[lsu.scala 65:30]
-  wire [3:0] lsu_lsc_ctl_io_lsu_error_pkt_r_bits_mscause; // @[lsu.scala 65:30]
-  wire [31:0] lsu_lsc_ctl_io_lsu_error_pkt_r_bits_addr; // @[lsu.scala 65:30]
-  wire [30:0] lsu_lsc_ctl_io_lsu_fir_addr; // @[lsu.scala 65:30]
-  wire [1:0] lsu_lsc_ctl_io_lsu_fir_error; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_addr_in_dccm_d; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_addr_in_dccm_m; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_addr_in_dccm_r; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_addr_in_pic_d; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_addr_in_pic_m; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_addr_in_pic_r; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_addr_external_m; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_dma_lsc_ctl_dma_dccm_req; // @[lsu.scala 65:30]
-  wire [31:0] lsu_lsc_ctl_io_dma_lsc_ctl_dma_mem_addr; // @[lsu.scala 65:30]
-  wire [2:0] lsu_lsc_ctl_io_dma_lsc_ctl_dma_mem_sz; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_dma_lsc_ctl_dma_mem_write; // @[lsu.scala 65:30]
-  wire [63:0] lsu_lsc_ctl_io_dma_lsc_ctl_dma_mem_wdata; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_lsu_pkt_d_valid; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_lsu_pkt_d_bits_fast_int; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_lsu_pkt_d_bits_by; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_lsu_pkt_d_bits_half; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_lsu_pkt_d_bits_word; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_lsu_pkt_d_bits_dword; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_lsu_pkt_d_bits_load; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_lsu_pkt_d_bits_store; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_lsu_pkt_d_bits_unsign; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_lsu_pkt_d_bits_dma; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_lsu_pkt_d_bits_store_data_bypass_d; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_lsu_pkt_d_bits_load_ldst_bypass_d; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_lsu_pkt_d_bits_store_data_bypass_m; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_lsu_pkt_m_valid; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_lsu_pkt_m_bits_fast_int; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_lsu_pkt_m_bits_by; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_lsu_pkt_m_bits_half; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_lsu_pkt_m_bits_word; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_lsu_pkt_m_bits_dword; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_lsu_pkt_m_bits_load; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_lsu_pkt_m_bits_store; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_lsu_pkt_m_bits_unsign; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_lsu_pkt_m_bits_dma; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_lsu_pkt_m_bits_store_data_bypass_m; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_lsu_pkt_r_valid; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_lsu_pkt_r_bits_by; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_lsu_pkt_r_bits_half; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_lsu_pkt_r_bits_word; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_lsu_pkt_r_bits_dword; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_lsu_pkt_r_bits_load; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_lsu_pkt_r_bits_store; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_lsu_pkt_r_bits_unsign; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_lsu_pkt_r_bits_dma; // @[lsu.scala 65:30]
-  wire  lsu_lsc_ctl_io_scan_mode; // @[lsu.scala 65:30]
-  wire  dccm_ctl_clock; // @[lsu.scala 68:30]
-  wire  dccm_ctl_reset; // @[lsu.scala 68:30]
-  wire  dccm_ctl_io_clk_override; // @[lsu.scala 68:30]
-  wire  dccm_ctl_io_lsu_c2_m_clk; // @[lsu.scala 68:30]
-  wire  dccm_ctl_io_lsu_free_c2_clk; // @[lsu.scala 68:30]
-  wire  dccm_ctl_io_lsu_store_c1_r_clk; // @[lsu.scala 68:30]
-  wire  dccm_ctl_io_lsu_pkt_d_valid; // @[lsu.scala 68:30]
-  wire  dccm_ctl_io_lsu_pkt_d_bits_word; // @[lsu.scala 68:30]
-  wire  dccm_ctl_io_lsu_pkt_d_bits_dword; // @[lsu.scala 68:30]
-  wire  dccm_ctl_io_lsu_pkt_d_bits_load; // @[lsu.scala 68:30]
-  wire  dccm_ctl_io_lsu_pkt_d_bits_store; // @[lsu.scala 68:30]
-  wire  dccm_ctl_io_lsu_pkt_d_bits_dma; // @[lsu.scala 68:30]
-  wire  dccm_ctl_io_lsu_pkt_m_valid; // @[lsu.scala 68:30]
-  wire  dccm_ctl_io_lsu_pkt_m_bits_by; // @[lsu.scala 68:30]
-  wire  dccm_ctl_io_lsu_pkt_m_bits_half; // @[lsu.scala 68:30]
-  wire  dccm_ctl_io_lsu_pkt_m_bits_word; // @[lsu.scala 68:30]
-  wire  dccm_ctl_io_lsu_pkt_m_bits_load; // @[lsu.scala 68:30]
-  wire  dccm_ctl_io_lsu_pkt_m_bits_store; // @[lsu.scala 68:30]
-  wire  dccm_ctl_io_lsu_pkt_m_bits_dma; // @[lsu.scala 68:30]
-  wire  dccm_ctl_io_lsu_pkt_r_valid; // @[lsu.scala 68:30]
-  wire  dccm_ctl_io_lsu_pkt_r_bits_by; // @[lsu.scala 68:30]
-  wire  dccm_ctl_io_lsu_pkt_r_bits_half; // @[lsu.scala 68:30]
-  wire  dccm_ctl_io_lsu_pkt_r_bits_word; // @[lsu.scala 68:30]
-  wire  dccm_ctl_io_lsu_pkt_r_bits_load; // @[lsu.scala 68:30]
-  wire  dccm_ctl_io_lsu_pkt_r_bits_store; // @[lsu.scala 68:30]
-  wire  dccm_ctl_io_lsu_pkt_r_bits_dma; // @[lsu.scala 68:30]
-  wire  dccm_ctl_io_addr_in_dccm_d; // @[lsu.scala 68:30]
-  wire  dccm_ctl_io_addr_in_dccm_m; // @[lsu.scala 68:30]
-  wire  dccm_ctl_io_addr_in_dccm_r; // @[lsu.scala 68:30]
-  wire  dccm_ctl_io_addr_in_pic_d; // @[lsu.scala 68:30]
-  wire  dccm_ctl_io_addr_in_pic_m; // @[lsu.scala 68:30]
-  wire  dccm_ctl_io_addr_in_pic_r; // @[lsu.scala 68:30]
-  wire  dccm_ctl_io_lsu_raw_fwd_lo_r; // @[lsu.scala 68:30]
-  wire  dccm_ctl_io_lsu_raw_fwd_hi_r; // @[lsu.scala 68:30]
-  wire  dccm_ctl_io_lsu_commit_r; // @[lsu.scala 68:30]
-  wire  dccm_ctl_io_ldst_dual_m; // @[lsu.scala 68:30]
-  wire [31:0] dccm_ctl_io_lsu_addr_d; // @[lsu.scala 68:30]
-  wire [15:0] dccm_ctl_io_lsu_addr_m; // @[lsu.scala 68:30]
-  wire [31:0] dccm_ctl_io_lsu_addr_r; // @[lsu.scala 68:30]
-  wire [15:0] dccm_ctl_io_end_addr_d; // @[lsu.scala 68:30]
-  wire [15:0] dccm_ctl_io_end_addr_m; // @[lsu.scala 68:30]
-  wire [15:0] dccm_ctl_io_end_addr_r; // @[lsu.scala 68:30]
-  wire  dccm_ctl_io_stbuf_reqvld_any; // @[lsu.scala 68:30]
-  wire [15:0] dccm_ctl_io_stbuf_addr_any; // @[lsu.scala 68:30]
-  wire [31:0] dccm_ctl_io_stbuf_data_any; // @[lsu.scala 68:30]
-  wire [6:0] dccm_ctl_io_stbuf_ecc_any; // @[lsu.scala 68:30]
-  wire [31:0] dccm_ctl_io_stbuf_fwddata_hi_m; // @[lsu.scala 68:30]
-  wire [31:0] dccm_ctl_io_stbuf_fwddata_lo_m; // @[lsu.scala 68:30]
-  wire [3:0] dccm_ctl_io_stbuf_fwdbyteen_lo_m; // @[lsu.scala 68:30]
-  wire [3:0] dccm_ctl_io_stbuf_fwdbyteen_hi_m; // @[lsu.scala 68:30]
-  wire [31:0] dccm_ctl_io_lsu_ld_data_corr_r; // @[lsu.scala 68:30]
-  wire  dccm_ctl_io_lsu_double_ecc_error_r; // @[lsu.scala 68:30]
-  wire  dccm_ctl_io_single_ecc_error_hi_r; // @[lsu.scala 68:30]
-  wire  dccm_ctl_io_single_ecc_error_lo_r; // @[lsu.scala 68:30]
-  wire [31:0] dccm_ctl_io_sec_data_hi_r_ff; // @[lsu.scala 68:30]
-  wire [31:0] dccm_ctl_io_sec_data_lo_r_ff; // @[lsu.scala 68:30]
-  wire [6:0] dccm_ctl_io_sec_data_ecc_hi_r_ff; // @[lsu.scala 68:30]
-  wire [6:0] dccm_ctl_io_sec_data_ecc_lo_r_ff; // @[lsu.scala 68:30]
-  wire [31:0] dccm_ctl_io_dccm_rdata_hi_m; // @[lsu.scala 68:30]
-  wire [31:0] dccm_ctl_io_dccm_rdata_lo_m; // @[lsu.scala 68:30]
-  wire [6:0] dccm_ctl_io_dccm_data_ecc_hi_m; // @[lsu.scala 68:30]
-  wire [6:0] dccm_ctl_io_dccm_data_ecc_lo_m; // @[lsu.scala 68:30]
-  wire [31:0] dccm_ctl_io_lsu_ld_data_m; // @[lsu.scala 68:30]
-  wire  dccm_ctl_io_lsu_double_ecc_error_m; // @[lsu.scala 68:30]
-  wire [31:0] dccm_ctl_io_sec_data_hi_m; // @[lsu.scala 68:30]
-  wire [31:0] dccm_ctl_io_sec_data_lo_m; // @[lsu.scala 68:30]
-  wire [31:0] dccm_ctl_io_store_data_m; // @[lsu.scala 68:30]
-  wire  dccm_ctl_io_dma_dccm_wen; // @[lsu.scala 68:30]
-  wire  dccm_ctl_io_dma_pic_wen; // @[lsu.scala 68:30]
-  wire [2:0] dccm_ctl_io_dma_mem_tag_m; // @[lsu.scala 68:30]
-  wire [31:0] dccm_ctl_io_dma_dccm_wdata_lo; // @[lsu.scala 68:30]
-  wire [31:0] dccm_ctl_io_dma_dccm_wdata_hi; // @[lsu.scala 68:30]
-  wire [6:0] dccm_ctl_io_dma_dccm_wdata_ecc_hi; // @[lsu.scala 68:30]
-  wire [6:0] dccm_ctl_io_dma_dccm_wdata_ecc_lo; // @[lsu.scala 68:30]
-  wire [31:0] dccm_ctl_io_store_data_hi_r; // @[lsu.scala 68:30]
-  wire [31:0] dccm_ctl_io_store_data_lo_r; // @[lsu.scala 68:30]
-  wire [31:0] dccm_ctl_io_store_datafn_hi_r; // @[lsu.scala 68:30]
-  wire [31:0] dccm_ctl_io_store_datafn_lo_r; // @[lsu.scala 68:30]
-  wire [31:0] dccm_ctl_io_store_data_r; // @[lsu.scala 68:30]
-  wire  dccm_ctl_io_ld_single_ecc_error_r; // @[lsu.scala 68:30]
-  wire  dccm_ctl_io_ld_single_ecc_error_r_ff; // @[lsu.scala 68:30]
-  wire [31:0] dccm_ctl_io_picm_mask_data_m; // @[lsu.scala 68:30]
-  wire  dccm_ctl_io_lsu_stbuf_commit_any; // @[lsu.scala 68:30]
-  wire  dccm_ctl_io_lsu_dccm_rden_m; // @[lsu.scala 68:30]
-  wire [31:0] dccm_ctl_io_dma_dccm_ctl_dma_mem_addr; // @[lsu.scala 68:30]
-  wire [63:0] dccm_ctl_io_dma_dccm_ctl_dma_mem_wdata; // @[lsu.scala 68:30]
-  wire  dccm_ctl_io_dma_dccm_ctl_dccm_dma_rvalid; // @[lsu.scala 68:30]
-  wire  dccm_ctl_io_dma_dccm_ctl_dccm_dma_ecc_error; // @[lsu.scala 68:30]
-  wire [2:0] dccm_ctl_io_dma_dccm_ctl_dccm_dma_rtag; // @[lsu.scala 68:30]
-  wire [63:0] dccm_ctl_io_dma_dccm_ctl_dccm_dma_rdata; // @[lsu.scala 68:30]
-  wire  dccm_ctl_io_dccm_wren; // @[lsu.scala 68:30]
-  wire  dccm_ctl_io_dccm_rden; // @[lsu.scala 68:30]
-  wire [15:0] dccm_ctl_io_dccm_wr_addr_lo; // @[lsu.scala 68:30]
-  wire [15:0] dccm_ctl_io_dccm_wr_addr_hi; // @[lsu.scala 68:30]
-  wire [15:0] dccm_ctl_io_dccm_rd_addr_lo; // @[lsu.scala 68:30]
-  wire [15:0] dccm_ctl_io_dccm_rd_addr_hi; // @[lsu.scala 68:30]
-  wire [38:0] dccm_ctl_io_dccm_wr_data_lo; // @[lsu.scala 68:30]
-  wire [38:0] dccm_ctl_io_dccm_wr_data_hi; // @[lsu.scala 68:30]
-  wire [38:0] dccm_ctl_io_dccm_rd_data_lo; // @[lsu.scala 68:30]
-  wire [38:0] dccm_ctl_io_dccm_rd_data_hi; // @[lsu.scala 68:30]
-  wire  dccm_ctl_io_lsu_pic_picm_wren; // @[lsu.scala 68:30]
-  wire  dccm_ctl_io_lsu_pic_picm_rden; // @[lsu.scala 68:30]
-  wire  dccm_ctl_io_lsu_pic_picm_mken; // @[lsu.scala 68:30]
-  wire [31:0] dccm_ctl_io_lsu_pic_picm_rdaddr; // @[lsu.scala 68:30]
-  wire [31:0] dccm_ctl_io_lsu_pic_picm_wraddr; // @[lsu.scala 68:30]
-  wire [31:0] dccm_ctl_io_lsu_pic_picm_wr_data; // @[lsu.scala 68:30]
-  wire [31:0] dccm_ctl_io_lsu_pic_picm_rd_data; // @[lsu.scala 68:30]
-  wire  dccm_ctl_io_scan_mode; // @[lsu.scala 68:30]
-  wire  stbuf_clock; // @[lsu.scala 69:30]
-  wire  stbuf_reset; // @[lsu.scala 69:30]
-  wire  stbuf_io_lsu_stbuf_c1_clk; // @[lsu.scala 69:30]
-  wire  stbuf_io_lsu_free_c2_clk; // @[lsu.scala 69:30]
-  wire  stbuf_io_lsu_pkt_m_valid; // @[lsu.scala 69:30]
-  wire  stbuf_io_lsu_pkt_m_bits_store; // @[lsu.scala 69:30]
-  wire  stbuf_io_lsu_pkt_m_bits_dma; // @[lsu.scala 69:30]
-  wire  stbuf_io_lsu_pkt_r_valid; // @[lsu.scala 69:30]
-  wire  stbuf_io_lsu_pkt_r_bits_by; // @[lsu.scala 69:30]
-  wire  stbuf_io_lsu_pkt_r_bits_half; // @[lsu.scala 69:30]
-  wire  stbuf_io_lsu_pkt_r_bits_word; // @[lsu.scala 69:30]
-  wire  stbuf_io_lsu_pkt_r_bits_dword; // @[lsu.scala 69:30]
-  wire  stbuf_io_lsu_pkt_r_bits_store; // @[lsu.scala 69:30]
-  wire  stbuf_io_lsu_pkt_r_bits_dma; // @[lsu.scala 69:30]
-  wire  stbuf_io_store_stbuf_reqvld_r; // @[lsu.scala 69:30]
-  wire  stbuf_io_lsu_commit_r; // @[lsu.scala 69:30]
-  wire  stbuf_io_dec_lsu_valid_raw_d; // @[lsu.scala 69:30]
-  wire [31:0] stbuf_io_store_data_hi_r; // @[lsu.scala 69:30]
-  wire [31:0] stbuf_io_store_data_lo_r; // @[lsu.scala 69:30]
-  wire [31:0] stbuf_io_store_datafn_hi_r; // @[lsu.scala 69:30]
-  wire [31:0] stbuf_io_store_datafn_lo_r; // @[lsu.scala 69:30]
-  wire  stbuf_io_lsu_stbuf_commit_any; // @[lsu.scala 69:30]
-  wire [31:0] stbuf_io_lsu_addr_m; // @[lsu.scala 69:30]
-  wire [31:0] stbuf_io_lsu_addr_r; // @[lsu.scala 69:30]
-  wire [31:0] stbuf_io_end_addr_m; // @[lsu.scala 69:30]
-  wire [31:0] stbuf_io_end_addr_r; // @[lsu.scala 69:30]
-  wire  stbuf_io_ldst_dual_d; // @[lsu.scala 69:30]
-  wire  stbuf_io_ldst_dual_m; // @[lsu.scala 69:30]
-  wire  stbuf_io_ldst_dual_r; // @[lsu.scala 69:30]
-  wire  stbuf_io_addr_in_dccm_m; // @[lsu.scala 69:30]
-  wire  stbuf_io_addr_in_dccm_r; // @[lsu.scala 69:30]
-  wire  stbuf_io_scan_mode; // @[lsu.scala 69:30]
-  wire  stbuf_io_stbuf_reqvld_any; // @[lsu.scala 69:30]
-  wire  stbuf_io_stbuf_reqvld_flushed_any; // @[lsu.scala 69:30]
-  wire [15:0] stbuf_io_stbuf_addr_any; // @[lsu.scala 69:30]
-  wire [31:0] stbuf_io_stbuf_data_any; // @[lsu.scala 69:30]
-  wire  stbuf_io_lsu_stbuf_full_any; // @[lsu.scala 69:30]
-  wire  stbuf_io_lsu_stbuf_empty_any; // @[lsu.scala 69:30]
-  wire  stbuf_io_ldst_stbuf_reqvld_r; // @[lsu.scala 69:30]
-  wire [31:0] stbuf_io_stbuf_fwddata_hi_m; // @[lsu.scala 69:30]
-  wire [31:0] stbuf_io_stbuf_fwddata_lo_m; // @[lsu.scala 69:30]
-  wire [3:0] stbuf_io_stbuf_fwdbyteen_hi_m; // @[lsu.scala 69:30]
-  wire [3:0] stbuf_io_stbuf_fwdbyteen_lo_m; // @[lsu.scala 69:30]
-  wire  ecc_clock; // @[lsu.scala 70:30]
-  wire  ecc_reset; // @[lsu.scala 70:30]
-  wire  ecc_io_lsu_c2_r_clk; // @[lsu.scala 70:30]
-  wire  ecc_io_clk_override; // @[lsu.scala 70:30]
-  wire  ecc_io_lsu_pkt_m_valid; // @[lsu.scala 70:30]
-  wire  ecc_io_lsu_pkt_m_bits_load; // @[lsu.scala 70:30]
-  wire  ecc_io_lsu_pkt_m_bits_store; // @[lsu.scala 70:30]
-  wire  ecc_io_lsu_pkt_m_bits_dma; // @[lsu.scala 70:30]
-  wire [31:0] ecc_io_stbuf_data_any; // @[lsu.scala 70:30]
-  wire  ecc_io_dec_tlu_core_ecc_disable; // @[lsu.scala 70:30]
-  wire [15:0] ecc_io_lsu_addr_m; // @[lsu.scala 70:30]
-  wire [15:0] ecc_io_end_addr_m; // @[lsu.scala 70:30]
-  wire [31:0] ecc_io_dccm_rdata_hi_m; // @[lsu.scala 70:30]
-  wire [31:0] ecc_io_dccm_rdata_lo_m; // @[lsu.scala 70:30]
-  wire [6:0] ecc_io_dccm_data_ecc_hi_m; // @[lsu.scala 70:30]
-  wire [6:0] ecc_io_dccm_data_ecc_lo_m; // @[lsu.scala 70:30]
-  wire  ecc_io_ld_single_ecc_error_r; // @[lsu.scala 70:30]
-  wire  ecc_io_ld_single_ecc_error_r_ff; // @[lsu.scala 70:30]
-  wire  ecc_io_lsu_dccm_rden_m; // @[lsu.scala 70:30]
-  wire  ecc_io_addr_in_dccm_m; // @[lsu.scala 70:30]
-  wire  ecc_io_dma_dccm_wen; // @[lsu.scala 70:30]
-  wire [31:0] ecc_io_dma_dccm_wdata_lo; // @[lsu.scala 70:30]
-  wire [31:0] ecc_io_dma_dccm_wdata_hi; // @[lsu.scala 70:30]
-  wire  ecc_io_scan_mode; // @[lsu.scala 70:30]
-  wire [31:0] ecc_io_sec_data_hi_r; // @[lsu.scala 70:30]
-  wire [31:0] ecc_io_sec_data_lo_r; // @[lsu.scala 70:30]
-  wire [31:0] ecc_io_sec_data_hi_m; // @[lsu.scala 70:30]
-  wire [31:0] ecc_io_sec_data_lo_m; // @[lsu.scala 70:30]
-  wire [31:0] ecc_io_sec_data_hi_r_ff; // @[lsu.scala 70:30]
-  wire [31:0] ecc_io_sec_data_lo_r_ff; // @[lsu.scala 70:30]
-  wire [6:0] ecc_io_dma_dccm_wdata_ecc_hi; // @[lsu.scala 70:30]
-  wire [6:0] ecc_io_dma_dccm_wdata_ecc_lo; // @[lsu.scala 70:30]
-  wire [6:0] ecc_io_stbuf_ecc_any; // @[lsu.scala 70:30]
-  wire [6:0] ecc_io_sec_data_ecc_hi_r_ff; // @[lsu.scala 70:30]
-  wire [6:0] ecc_io_sec_data_ecc_lo_r_ff; // @[lsu.scala 70:30]
-  wire  ecc_io_single_ecc_error_hi_r; // @[lsu.scala 70:30]
-  wire  ecc_io_single_ecc_error_lo_r; // @[lsu.scala 70:30]
-  wire  ecc_io_lsu_single_ecc_error_r; // @[lsu.scala 70:30]
-  wire  ecc_io_lsu_double_ecc_error_r; // @[lsu.scala 70:30]
-  wire  ecc_io_lsu_single_ecc_error_m; // @[lsu.scala 70:30]
-  wire  ecc_io_lsu_double_ecc_error_m; // @[lsu.scala 70:30]
-  wire  trigger_io_trigger_pkt_any_0_select; // @[lsu.scala 71:30]
-  wire  trigger_io_trigger_pkt_any_0_match_pkt; // @[lsu.scala 71:30]
-  wire  trigger_io_trigger_pkt_any_0_store; // @[lsu.scala 71:30]
-  wire  trigger_io_trigger_pkt_any_0_load; // @[lsu.scala 71:30]
-  wire  trigger_io_trigger_pkt_any_0_m; // @[lsu.scala 71:30]
-  wire [31:0] trigger_io_trigger_pkt_any_0_tdata2; // @[lsu.scala 71:30]
-  wire  trigger_io_trigger_pkt_any_1_select; // @[lsu.scala 71:30]
-  wire  trigger_io_trigger_pkt_any_1_match_pkt; // @[lsu.scala 71:30]
-  wire  trigger_io_trigger_pkt_any_1_store; // @[lsu.scala 71:30]
-  wire  trigger_io_trigger_pkt_any_1_load; // @[lsu.scala 71:30]
-  wire  trigger_io_trigger_pkt_any_1_m; // @[lsu.scala 71:30]
-  wire [31:0] trigger_io_trigger_pkt_any_1_tdata2; // @[lsu.scala 71:30]
-  wire  trigger_io_trigger_pkt_any_2_select; // @[lsu.scala 71:30]
-  wire  trigger_io_trigger_pkt_any_2_match_pkt; // @[lsu.scala 71:30]
-  wire  trigger_io_trigger_pkt_any_2_store; // @[lsu.scala 71:30]
-  wire  trigger_io_trigger_pkt_any_2_load; // @[lsu.scala 71:30]
-  wire  trigger_io_trigger_pkt_any_2_m; // @[lsu.scala 71:30]
-  wire [31:0] trigger_io_trigger_pkt_any_2_tdata2; // @[lsu.scala 71:30]
-  wire  trigger_io_trigger_pkt_any_3_select; // @[lsu.scala 71:30]
-  wire  trigger_io_trigger_pkt_any_3_match_pkt; // @[lsu.scala 71:30]
-  wire  trigger_io_trigger_pkt_any_3_store; // @[lsu.scala 71:30]
-  wire  trigger_io_trigger_pkt_any_3_load; // @[lsu.scala 71:30]
-  wire  trigger_io_trigger_pkt_any_3_m; // @[lsu.scala 71:30]
-  wire [31:0] trigger_io_trigger_pkt_any_3_tdata2; // @[lsu.scala 71:30]
-  wire  trigger_io_lsu_pkt_m_valid; // @[lsu.scala 71:30]
-  wire  trigger_io_lsu_pkt_m_bits_half; // @[lsu.scala 71:30]
-  wire  trigger_io_lsu_pkt_m_bits_word; // @[lsu.scala 71:30]
-  wire  trigger_io_lsu_pkt_m_bits_load; // @[lsu.scala 71:30]
-  wire  trigger_io_lsu_pkt_m_bits_store; // @[lsu.scala 71:30]
-  wire  trigger_io_lsu_pkt_m_bits_dma; // @[lsu.scala 71:30]
-  wire [31:0] trigger_io_lsu_addr_m; // @[lsu.scala 71:30]
-  wire [31:0] trigger_io_store_data_m; // @[lsu.scala 71:30]
-  wire [3:0] trigger_io_lsu_trigger_match_m; // @[lsu.scala 71:30]
-  wire  clkdomain_clock; // @[lsu.scala 72:30]
-  wire  clkdomain_reset; // @[lsu.scala 72:30]
-  wire  clkdomain_io_active_clk; // @[lsu.scala 72:30]
-  wire  clkdomain_io_clk_override; // @[lsu.scala 72:30]
-  wire  clkdomain_io_dec_tlu_force_halt; // @[lsu.scala 72:30]
-  wire  clkdomain_io_dma_dccm_req; // @[lsu.scala 72:30]
-  wire  clkdomain_io_ldst_stbuf_reqvld_r; // @[lsu.scala 72:30]
-  wire  clkdomain_io_stbuf_reqvld_any; // @[lsu.scala 72:30]
-  wire  clkdomain_io_stbuf_reqvld_flushed_any; // @[lsu.scala 72:30]
-  wire  clkdomain_io_lsu_busreq_r; // @[lsu.scala 72:30]
-  wire  clkdomain_io_lsu_bus_buffer_pend_any; // @[lsu.scala 72:30]
-  wire  clkdomain_io_lsu_bus_buffer_empty_any; // @[lsu.scala 72:30]
-  wire  clkdomain_io_lsu_stbuf_empty_any; // @[lsu.scala 72:30]
-  wire  clkdomain_io_lsu_bus_clk_en; // @[lsu.scala 72:30]
-  wire  clkdomain_io_lsu_p_valid; // @[lsu.scala 72:30]
-  wire  clkdomain_io_lsu_pkt_d_valid; // @[lsu.scala 72:30]
-  wire  clkdomain_io_lsu_pkt_d_bits_store; // @[lsu.scala 72:30]
-  wire  clkdomain_io_lsu_pkt_m_valid; // @[lsu.scala 72:30]
-  wire  clkdomain_io_lsu_pkt_m_bits_store; // @[lsu.scala 72:30]
-  wire  clkdomain_io_lsu_pkt_r_valid; // @[lsu.scala 72:30]
-  wire  clkdomain_io_lsu_bus_obuf_c1_clken; // @[lsu.scala 72:30]
-  wire  clkdomain_io_lsu_busm_clken; // @[lsu.scala 72:30]
-  wire  clkdomain_io_lsu_c1_m_clk; // @[lsu.scala 72:30]
-  wire  clkdomain_io_lsu_c1_r_clk; // @[lsu.scala 72:30]
-  wire  clkdomain_io_lsu_c2_m_clk; // @[lsu.scala 72:30]
-  wire  clkdomain_io_lsu_c2_r_clk; // @[lsu.scala 72:30]
-  wire  clkdomain_io_lsu_store_c1_m_clk; // @[lsu.scala 72:30]
-  wire  clkdomain_io_lsu_store_c1_r_clk; // @[lsu.scala 72:30]
-  wire  clkdomain_io_lsu_stbuf_c1_clk; // @[lsu.scala 72:30]
-  wire  clkdomain_io_lsu_bus_obuf_c1_clk; // @[lsu.scala 72:30]
-  wire  clkdomain_io_lsu_bus_ibuf_c1_clk; // @[lsu.scala 72:30]
-  wire  clkdomain_io_lsu_bus_buf_c1_clk; // @[lsu.scala 72:30]
-  wire  clkdomain_io_lsu_busm_clk; // @[lsu.scala 72:30]
-  wire  clkdomain_io_lsu_free_c2_clk; // @[lsu.scala 72:30]
-  wire  clkdomain_io_scan_mode; // @[lsu.scala 72:30]
-  wire  bus_intf_clock; // @[lsu.scala 73:30]
-  wire  bus_intf_reset; // @[lsu.scala 73:30]
-  wire  bus_intf_io_scan_mode; // @[lsu.scala 73:30]
-  wire  bus_intf_io_tlu_busbuff_lsu_pmu_bus_trxn; // @[lsu.scala 73:30]
-  wire  bus_intf_io_tlu_busbuff_lsu_pmu_bus_misaligned; // @[lsu.scala 73:30]
-  wire  bus_intf_io_tlu_busbuff_lsu_pmu_bus_error; // @[lsu.scala 73:30]
-  wire  bus_intf_io_tlu_busbuff_lsu_pmu_bus_busy; // @[lsu.scala 73:30]
-  wire  bus_intf_io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[lsu.scala 73:30]
-  wire  bus_intf_io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu.scala 73:30]
-  wire  bus_intf_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu.scala 73:30]
-  wire  bus_intf_io_tlu_busbuff_lsu_imprecise_error_load_any; // @[lsu.scala 73:30]
-  wire  bus_intf_io_tlu_busbuff_lsu_imprecise_error_store_any; // @[lsu.scala 73:30]
-  wire [31:0] bus_intf_io_tlu_busbuff_lsu_imprecise_error_addr_any; // @[lsu.scala 73:30]
-  wire  bus_intf_io_lsu_c1_r_clk; // @[lsu.scala 73:30]
-  wire  bus_intf_io_lsu_c2_r_clk; // @[lsu.scala 73:30]
-  wire  bus_intf_io_lsu_bus_ibuf_c1_clk; // @[lsu.scala 73:30]
-  wire  bus_intf_io_lsu_bus_obuf_c1_clk; // @[lsu.scala 73:30]
-  wire  bus_intf_io_lsu_bus_buf_c1_clk; // @[lsu.scala 73:30]
-  wire  bus_intf_io_lsu_free_c2_clk; // @[lsu.scala 73:30]
-  wire  bus_intf_io_active_clk; // @[lsu.scala 73:30]
-  wire  bus_intf_io_lsu_busm_clk; // @[lsu.scala 73:30]
-  wire  bus_intf_io_axi_aw_ready; // @[lsu.scala 73:30]
-  wire  bus_intf_io_axi_aw_valid; // @[lsu.scala 73:30]
-  wire [2:0] bus_intf_io_axi_aw_bits_id; // @[lsu.scala 73:30]
-  wire [31:0] bus_intf_io_axi_aw_bits_addr; // @[lsu.scala 73:30]
-  wire [3:0] bus_intf_io_axi_aw_bits_region; // @[lsu.scala 73:30]
-  wire [2:0] bus_intf_io_axi_aw_bits_size; // @[lsu.scala 73:30]
-  wire [3:0] bus_intf_io_axi_aw_bits_cache; // @[lsu.scala 73:30]
-  wire  bus_intf_io_axi_w_ready; // @[lsu.scala 73:30]
-  wire  bus_intf_io_axi_w_valid; // @[lsu.scala 73:30]
-  wire [63:0] bus_intf_io_axi_w_bits_data; // @[lsu.scala 73:30]
-  wire [7:0] bus_intf_io_axi_w_bits_strb; // @[lsu.scala 73:30]
-  wire  bus_intf_io_axi_b_valid; // @[lsu.scala 73:30]
-  wire [1:0] bus_intf_io_axi_b_bits_resp; // @[lsu.scala 73:30]
-  wire [2:0] bus_intf_io_axi_b_bits_id; // @[lsu.scala 73:30]
-  wire  bus_intf_io_axi_ar_ready; // @[lsu.scala 73:30]
-  wire  bus_intf_io_axi_ar_valid; // @[lsu.scala 73:30]
-  wire [2:0] bus_intf_io_axi_ar_bits_id; // @[lsu.scala 73:30]
-  wire [31:0] bus_intf_io_axi_ar_bits_addr; // @[lsu.scala 73:30]
-  wire [3:0] bus_intf_io_axi_ar_bits_region; // @[lsu.scala 73:30]
-  wire [2:0] bus_intf_io_axi_ar_bits_size; // @[lsu.scala 73:30]
-  wire [3:0] bus_intf_io_axi_ar_bits_cache; // @[lsu.scala 73:30]
-  wire  bus_intf_io_axi_r_valid; // @[lsu.scala 73:30]
-  wire [2:0] bus_intf_io_axi_r_bits_id; // @[lsu.scala 73:30]
-  wire [63:0] bus_intf_io_axi_r_bits_data; // @[lsu.scala 73:30]
-  wire [1:0] bus_intf_io_axi_r_bits_resp; // @[lsu.scala 73:30]
-  wire  bus_intf_io_dec_lsu_valid_raw_d; // @[lsu.scala 73:30]
-  wire  bus_intf_io_lsu_busreq_m; // @[lsu.scala 73:30]
-  wire  bus_intf_io_lsu_pkt_m_valid; // @[lsu.scala 73:30]
-  wire  bus_intf_io_lsu_pkt_m_bits_by; // @[lsu.scala 73:30]
-  wire  bus_intf_io_lsu_pkt_m_bits_half; // @[lsu.scala 73:30]
-  wire  bus_intf_io_lsu_pkt_m_bits_word; // @[lsu.scala 73:30]
-  wire  bus_intf_io_lsu_pkt_m_bits_load; // @[lsu.scala 73:30]
-  wire  bus_intf_io_lsu_pkt_r_valid; // @[lsu.scala 73:30]
-  wire  bus_intf_io_lsu_pkt_r_bits_by; // @[lsu.scala 73:30]
-  wire  bus_intf_io_lsu_pkt_r_bits_half; // @[lsu.scala 73:30]
-  wire  bus_intf_io_lsu_pkt_r_bits_word; // @[lsu.scala 73:30]
-  wire  bus_intf_io_lsu_pkt_r_bits_load; // @[lsu.scala 73:30]
-  wire  bus_intf_io_lsu_pkt_r_bits_store; // @[lsu.scala 73:30]
-  wire  bus_intf_io_lsu_pkt_r_bits_unsign; // @[lsu.scala 73:30]
-  wire [31:0] bus_intf_io_lsu_addr_m; // @[lsu.scala 73:30]
-  wire [31:0] bus_intf_io_lsu_addr_r; // @[lsu.scala 73:30]
-  wire [31:0] bus_intf_io_end_addr_m; // @[lsu.scala 73:30]
-  wire [31:0] bus_intf_io_end_addr_r; // @[lsu.scala 73:30]
-  wire  bus_intf_io_ldst_dual_d; // @[lsu.scala 73:30]
-  wire  bus_intf_io_ldst_dual_m; // @[lsu.scala 73:30]
-  wire  bus_intf_io_ldst_dual_r; // @[lsu.scala 73:30]
-  wire [31:0] bus_intf_io_store_data_r; // @[lsu.scala 73:30]
-  wire  bus_intf_io_dec_tlu_force_halt; // @[lsu.scala 73:30]
-  wire  bus_intf_io_lsu_commit_r; // @[lsu.scala 73:30]
-  wire  bus_intf_io_is_sideeffects_m; // @[lsu.scala 73:30]
-  wire  bus_intf_io_flush_m_up; // @[lsu.scala 73:30]
-  wire  bus_intf_io_flush_r; // @[lsu.scala 73:30]
-  wire  bus_intf_io_lsu_busreq_r; // @[lsu.scala 73:30]
-  wire  bus_intf_io_lsu_bus_buffer_pend_any; // @[lsu.scala 73:30]
-  wire  bus_intf_io_lsu_bus_buffer_full_any; // @[lsu.scala 73:30]
-  wire  bus_intf_io_lsu_bus_buffer_empty_any; // @[lsu.scala 73:30]
-  wire [31:0] bus_intf_io_bus_read_data_m; // @[lsu.scala 73:30]
-  wire  bus_intf_io_dctl_busbuff_lsu_nonblock_load_valid_m; // @[lsu.scala 73:30]
-  wire [1:0] bus_intf_io_dctl_busbuff_lsu_nonblock_load_tag_m; // @[lsu.scala 73:30]
-  wire  bus_intf_io_dctl_busbuff_lsu_nonblock_load_inv_r; // @[lsu.scala 73:30]
-  wire [1:0] bus_intf_io_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[lsu.scala 73:30]
-  wire  bus_intf_io_dctl_busbuff_lsu_nonblock_load_data_valid; // @[lsu.scala 73:30]
-  wire  bus_intf_io_dctl_busbuff_lsu_nonblock_load_data_error; // @[lsu.scala 73:30]
-  wire [1:0] bus_intf_io_dctl_busbuff_lsu_nonblock_load_data_tag; // @[lsu.scala 73:30]
-  wire [31:0] bus_intf_io_dctl_busbuff_lsu_nonblock_load_data; // @[lsu.scala 73:30]
-  wire  bus_intf_io_lsu_bus_clk_en; // @[lsu.scala 73:30]
-  wire  _T = stbuf_io_lsu_stbuf_full_any | bus_intf_io_lsu_bus_buffer_full_any; // @[lsu.scala 79:57]
-  wire  _T_3 = ~lsu_lsc_ctl_io_lsu_pkt_m_bits_dma; // @[lsu.scala 86:58]
-  wire  _T_4 = lsu_lsc_ctl_io_lsu_pkt_m_valid & _T_3; // @[lsu.scala 86:56]
-  wire  _T_5 = lsu_lsc_ctl_io_addr_in_dccm_m | lsu_lsc_ctl_io_addr_in_pic_m; // @[lsu.scala 86:126]
-  wire  _T_6 = _T_4 & _T_5; // @[lsu.scala 86:93]
-  wire  ldst_nodma_mtor = _T_6 & lsu_lsc_ctl_io_lsu_pkt_m_bits_store; // @[lsu.scala 86:158]
-  wire  _T_7 = io_dec_lsu_valid_raw_d | ldst_nodma_mtor; // @[lsu.scala 87:53]
-  wire  _T_8 = _T_7 | dccm_ctl_io_ld_single_ecc_error_r_ff; // @[lsu.scala 87:71]
-  wire  _T_10 = io_lsu_dma_dma_lsc_ctl_dma_dccm_req & io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[lsu.scala 88:58]
-  wire  _T_11 = _T_10 & lsu_lsc_ctl_io_addr_in_dccm_d; // @[lsu.scala 88:97]
+  wire  lsu_lsc_ctl_clock; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_reset; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_io_clk_override; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_io_lsu_c1_m_clk; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_io_lsu_c1_r_clk; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_io_lsu_c2_m_clk; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_io_lsu_c2_r_clk; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_io_lsu_store_c1_m_clk; // @[lsu.scala 70:30]
+  wire [31:0] lsu_lsc_ctl_io_lsu_ld_data_r; // @[lsu.scala 70:30]
+  wire [31:0] lsu_lsc_ctl_io_lsu_ld_data_corr_r; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_io_lsu_single_ecc_error_r; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_io_lsu_double_ecc_error_r; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_io_flush_m_up; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_io_flush_r; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_io_ldst_dual_d; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_io_ldst_dual_m; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_io_ldst_dual_r; // @[lsu.scala 70:30]
+  wire [31:0] lsu_lsc_ctl_io_lsu_exu_exu_lsu_rs1_d; // @[lsu.scala 70:30]
+  wire [31:0] lsu_lsc_ctl_io_lsu_exu_exu_lsu_rs2_d; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_io_lsu_p_valid; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_io_lsu_p_bits_fast_int; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_io_lsu_p_bits_by; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_io_lsu_p_bits_half; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_io_lsu_p_bits_word; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_io_lsu_p_bits_dword; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_io_lsu_p_bits_load; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_io_lsu_p_bits_store; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_io_lsu_p_bits_unsign; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_io_lsu_p_bits_dma; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_io_lsu_p_bits_store_data_bypass_d; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_io_lsu_p_bits_load_ldst_bypass_d; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_io_lsu_p_bits_store_data_bypass_m; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_io_dec_lsu_valid_raw_d; // @[lsu.scala 70:30]
+  wire [11:0] lsu_lsc_ctl_io_dec_lsu_offset_d; // @[lsu.scala 70:30]
+  wire [31:0] lsu_lsc_ctl_io_picm_mask_data_m; // @[lsu.scala 70:30]
+  wire [31:0] lsu_lsc_ctl_io_bus_read_data_m; // @[lsu.scala 70:30]
+  wire [31:0] lsu_lsc_ctl_io_lsu_result_m; // @[lsu.scala 70:30]
+  wire [31:0] lsu_lsc_ctl_io_lsu_result_corr_r; // @[lsu.scala 70:30]
+  wire [31:0] lsu_lsc_ctl_io_lsu_addr_d; // @[lsu.scala 70:30]
+  wire [31:0] lsu_lsc_ctl_io_lsu_addr_m; // @[lsu.scala 70:30]
+  wire [31:0] lsu_lsc_ctl_io_lsu_addr_r; // @[lsu.scala 70:30]
+  wire [31:0] lsu_lsc_ctl_io_end_addr_d; // @[lsu.scala 70:30]
+  wire [31:0] lsu_lsc_ctl_io_end_addr_m; // @[lsu.scala 70:30]
+  wire [31:0] lsu_lsc_ctl_io_end_addr_r; // @[lsu.scala 70:30]
+  wire [31:0] lsu_lsc_ctl_io_store_data_m; // @[lsu.scala 70:30]
+  wire [31:0] lsu_lsc_ctl_io_dec_tlu_mrac_ff; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_io_lsu_exc_m; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_io_is_sideeffects_m; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_io_lsu_commit_r; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_io_lsu_single_ecc_error_incr; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_io_lsu_error_pkt_r_valid; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_io_lsu_error_pkt_r_bits_single_ecc_error; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_io_lsu_error_pkt_r_bits_inst_type; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_io_lsu_error_pkt_r_bits_exc_type; // @[lsu.scala 70:30]
+  wire [3:0] lsu_lsc_ctl_io_lsu_error_pkt_r_bits_mscause; // @[lsu.scala 70:30]
+  wire [31:0] lsu_lsc_ctl_io_lsu_error_pkt_r_bits_addr; // @[lsu.scala 70:30]
+  wire [30:0] lsu_lsc_ctl_io_lsu_fir_addr; // @[lsu.scala 70:30]
+  wire [1:0] lsu_lsc_ctl_io_lsu_fir_error; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_io_addr_in_dccm_d; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_io_addr_in_dccm_m; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_io_addr_in_dccm_r; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_io_addr_in_pic_d; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_io_addr_in_pic_m; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_io_addr_in_pic_r; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_io_addr_external_m; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_io_dma_lsc_ctl_dma_dccm_req; // @[lsu.scala 70:30]
+  wire [31:0] lsu_lsc_ctl_io_dma_lsc_ctl_dma_mem_addr; // @[lsu.scala 70:30]
+  wire [2:0] lsu_lsc_ctl_io_dma_lsc_ctl_dma_mem_sz; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_io_dma_lsc_ctl_dma_mem_write; // @[lsu.scala 70:30]
+  wire [63:0] lsu_lsc_ctl_io_dma_lsc_ctl_dma_mem_wdata; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_io_lsu_pkt_d_valid; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_io_lsu_pkt_d_bits_fast_int; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_io_lsu_pkt_d_bits_by; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_io_lsu_pkt_d_bits_half; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_io_lsu_pkt_d_bits_word; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_io_lsu_pkt_d_bits_dword; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_io_lsu_pkt_d_bits_load; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_io_lsu_pkt_d_bits_store; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_io_lsu_pkt_d_bits_unsign; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_io_lsu_pkt_d_bits_dma; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_io_lsu_pkt_d_bits_store_data_bypass_d; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_io_lsu_pkt_d_bits_load_ldst_bypass_d; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_io_lsu_pkt_d_bits_store_data_bypass_m; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_io_lsu_pkt_m_valid; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_io_lsu_pkt_m_bits_fast_int; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_io_lsu_pkt_m_bits_by; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_io_lsu_pkt_m_bits_half; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_io_lsu_pkt_m_bits_word; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_io_lsu_pkt_m_bits_dword; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_io_lsu_pkt_m_bits_load; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_io_lsu_pkt_m_bits_store; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_io_lsu_pkt_m_bits_unsign; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_io_lsu_pkt_m_bits_dma; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_io_lsu_pkt_m_bits_store_data_bypass_m; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_io_lsu_pkt_r_valid; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_io_lsu_pkt_r_bits_fast_int; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_io_lsu_pkt_r_bits_by; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_io_lsu_pkt_r_bits_half; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_io_lsu_pkt_r_bits_word; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_io_lsu_pkt_r_bits_dword; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_io_lsu_pkt_r_bits_load; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_io_lsu_pkt_r_bits_store; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_io_lsu_pkt_r_bits_unsign; // @[lsu.scala 70:30]
+  wire  lsu_lsc_ctl_io_lsu_pkt_r_bits_dma; // @[lsu.scala 70:30]
+  wire  dccm_ctl_clock; // @[lsu.scala 73:30]
+  wire  dccm_ctl_reset; // @[lsu.scala 73:30]
+  wire  dccm_ctl_io_clk_override; // @[lsu.scala 73:30]
+  wire  dccm_ctl_io_lsu_c2_m_clk; // @[lsu.scala 73:30]
+  wire  dccm_ctl_io_lsu_c2_r_clk; // @[lsu.scala 73:30]
+  wire  dccm_ctl_io_lsu_free_c2_clk; // @[lsu.scala 73:30]
+  wire  dccm_ctl_io_lsu_c1_r_clk; // @[lsu.scala 73:30]
+  wire  dccm_ctl_io_lsu_store_c1_r_clk; // @[lsu.scala 73:30]
+  wire  dccm_ctl_io_lsu_pkt_d_valid; // @[lsu.scala 73:30]
+  wire  dccm_ctl_io_lsu_pkt_d_bits_word; // @[lsu.scala 73:30]
+  wire  dccm_ctl_io_lsu_pkt_d_bits_dword; // @[lsu.scala 73:30]
+  wire  dccm_ctl_io_lsu_pkt_d_bits_load; // @[lsu.scala 73:30]
+  wire  dccm_ctl_io_lsu_pkt_d_bits_store; // @[lsu.scala 73:30]
+  wire  dccm_ctl_io_lsu_pkt_d_bits_dma; // @[lsu.scala 73:30]
+  wire  dccm_ctl_io_lsu_pkt_m_valid; // @[lsu.scala 73:30]
+  wire  dccm_ctl_io_lsu_pkt_m_bits_store; // @[lsu.scala 73:30]
+  wire  dccm_ctl_io_lsu_pkt_m_bits_dma; // @[lsu.scala 73:30]
+  wire  dccm_ctl_io_lsu_pkt_r_valid; // @[lsu.scala 73:30]
+  wire  dccm_ctl_io_lsu_pkt_r_bits_by; // @[lsu.scala 73:30]
+  wire  dccm_ctl_io_lsu_pkt_r_bits_half; // @[lsu.scala 73:30]
+  wire  dccm_ctl_io_lsu_pkt_r_bits_word; // @[lsu.scala 73:30]
+  wire  dccm_ctl_io_lsu_pkt_r_bits_load; // @[lsu.scala 73:30]
+  wire  dccm_ctl_io_lsu_pkt_r_bits_store; // @[lsu.scala 73:30]
+  wire  dccm_ctl_io_lsu_pkt_r_bits_dma; // @[lsu.scala 73:30]
+  wire  dccm_ctl_io_addr_in_dccm_d; // @[lsu.scala 73:30]
+  wire  dccm_ctl_io_addr_in_dccm_m; // @[lsu.scala 73:30]
+  wire  dccm_ctl_io_addr_in_dccm_r; // @[lsu.scala 73:30]
+  wire  dccm_ctl_io_addr_in_pic_d; // @[lsu.scala 73:30]
+  wire  dccm_ctl_io_addr_in_pic_m; // @[lsu.scala 73:30]
+  wire  dccm_ctl_io_addr_in_pic_r; // @[lsu.scala 73:30]
+  wire  dccm_ctl_io_lsu_raw_fwd_lo_r; // @[lsu.scala 73:30]
+  wire  dccm_ctl_io_lsu_raw_fwd_hi_r; // @[lsu.scala 73:30]
+  wire  dccm_ctl_io_lsu_commit_r; // @[lsu.scala 73:30]
+  wire  dccm_ctl_io_ldst_dual_m; // @[lsu.scala 73:30]
+  wire  dccm_ctl_io_ldst_dual_r; // @[lsu.scala 73:30]
+  wire [31:0] dccm_ctl_io_lsu_addr_d; // @[lsu.scala 73:30]
+  wire [15:0] dccm_ctl_io_lsu_addr_m; // @[lsu.scala 73:30]
+  wire [31:0] dccm_ctl_io_lsu_addr_r; // @[lsu.scala 73:30]
+  wire [15:0] dccm_ctl_io_end_addr_d; // @[lsu.scala 73:30]
+  wire [15:0] dccm_ctl_io_end_addr_m; // @[lsu.scala 73:30]
+  wire [15:0] dccm_ctl_io_end_addr_r; // @[lsu.scala 73:30]
+  wire  dccm_ctl_io_stbuf_reqvld_any; // @[lsu.scala 73:30]
+  wire [15:0] dccm_ctl_io_stbuf_addr_any; // @[lsu.scala 73:30]
+  wire [31:0] dccm_ctl_io_stbuf_data_any; // @[lsu.scala 73:30]
+  wire [6:0] dccm_ctl_io_stbuf_ecc_any; // @[lsu.scala 73:30]
+  wire [31:0] dccm_ctl_io_stbuf_fwddata_hi_m; // @[lsu.scala 73:30]
+  wire [31:0] dccm_ctl_io_stbuf_fwddata_lo_m; // @[lsu.scala 73:30]
+  wire [3:0] dccm_ctl_io_stbuf_fwdbyteen_lo_m; // @[lsu.scala 73:30]
+  wire [3:0] dccm_ctl_io_stbuf_fwdbyteen_hi_m; // @[lsu.scala 73:30]
+  wire [31:0] dccm_ctl_io_dccm_rdata_hi_r; // @[lsu.scala 73:30]
+  wire [31:0] dccm_ctl_io_dccm_rdata_lo_r; // @[lsu.scala 73:30]
+  wire [6:0] dccm_ctl_io_dccm_data_ecc_hi_r; // @[lsu.scala 73:30]
+  wire [6:0] dccm_ctl_io_dccm_data_ecc_lo_r; // @[lsu.scala 73:30]
+  wire [31:0] dccm_ctl_io_lsu_ld_data_r; // @[lsu.scala 73:30]
+  wire [31:0] dccm_ctl_io_lsu_ld_data_corr_r; // @[lsu.scala 73:30]
+  wire  dccm_ctl_io_lsu_double_ecc_error_r; // @[lsu.scala 73:30]
+  wire  dccm_ctl_io_single_ecc_error_hi_r; // @[lsu.scala 73:30]
+  wire  dccm_ctl_io_single_ecc_error_lo_r; // @[lsu.scala 73:30]
+  wire [31:0] dccm_ctl_io_sec_data_hi_r; // @[lsu.scala 73:30]
+  wire [31:0] dccm_ctl_io_sec_data_lo_r; // @[lsu.scala 73:30]
+  wire [31:0] dccm_ctl_io_sec_data_hi_r_ff; // @[lsu.scala 73:30]
+  wire [31:0] dccm_ctl_io_sec_data_lo_r_ff; // @[lsu.scala 73:30]
+  wire [6:0] dccm_ctl_io_sec_data_ecc_hi_r_ff; // @[lsu.scala 73:30]
+  wire [6:0] dccm_ctl_io_sec_data_ecc_lo_r_ff; // @[lsu.scala 73:30]
+  wire [31:0] dccm_ctl_io_dccm_rdata_hi_m; // @[lsu.scala 73:30]
+  wire [31:0] dccm_ctl_io_dccm_rdata_lo_m; // @[lsu.scala 73:30]
+  wire [6:0] dccm_ctl_io_dccm_data_ecc_hi_m; // @[lsu.scala 73:30]
+  wire [6:0] dccm_ctl_io_dccm_data_ecc_lo_m; // @[lsu.scala 73:30]
+  wire [31:0] dccm_ctl_io_store_data_m; // @[lsu.scala 73:30]
+  wire  dccm_ctl_io_dma_dccm_wen; // @[lsu.scala 73:30]
+  wire  dccm_ctl_io_dma_pic_wen; // @[lsu.scala 73:30]
+  wire [2:0] dccm_ctl_io_dma_mem_tag_m; // @[lsu.scala 73:30]
+  wire [31:0] dccm_ctl_io_dma_dccm_wdata_lo; // @[lsu.scala 73:30]
+  wire [31:0] dccm_ctl_io_dma_dccm_wdata_hi; // @[lsu.scala 73:30]
+  wire [6:0] dccm_ctl_io_dma_dccm_wdata_ecc_hi; // @[lsu.scala 73:30]
+  wire [6:0] dccm_ctl_io_dma_dccm_wdata_ecc_lo; // @[lsu.scala 73:30]
+  wire [31:0] dccm_ctl_io_store_data_hi_r; // @[lsu.scala 73:30]
+  wire [31:0] dccm_ctl_io_store_data_lo_r; // @[lsu.scala 73:30]
+  wire [31:0] dccm_ctl_io_store_datafn_hi_r; // @[lsu.scala 73:30]
+  wire [31:0] dccm_ctl_io_store_datafn_lo_r; // @[lsu.scala 73:30]
+  wire [31:0] dccm_ctl_io_store_data_r; // @[lsu.scala 73:30]
+  wire  dccm_ctl_io_ld_single_ecc_error_r; // @[lsu.scala 73:30]
+  wire  dccm_ctl_io_ld_single_ecc_error_r_ff; // @[lsu.scala 73:30]
+  wire [31:0] dccm_ctl_io_picm_mask_data_m; // @[lsu.scala 73:30]
+  wire  dccm_ctl_io_lsu_stbuf_commit_any; // @[lsu.scala 73:30]
+  wire  dccm_ctl_io_lsu_dccm_rden_m; // @[lsu.scala 73:30]
+  wire  dccm_ctl_io_lsu_dccm_rden_r; // @[lsu.scala 73:30]
+  wire [31:0] dccm_ctl_io_dma_dccm_ctl_dma_mem_addr; // @[lsu.scala 73:30]
+  wire [63:0] dccm_ctl_io_dma_dccm_ctl_dma_mem_wdata; // @[lsu.scala 73:30]
+  wire  dccm_ctl_io_dma_dccm_ctl_dccm_dma_rvalid; // @[lsu.scala 73:30]
+  wire  dccm_ctl_io_dma_dccm_ctl_dccm_dma_ecc_error; // @[lsu.scala 73:30]
+  wire [2:0] dccm_ctl_io_dma_dccm_ctl_dccm_dma_rtag; // @[lsu.scala 73:30]
+  wire [63:0] dccm_ctl_io_dma_dccm_ctl_dccm_dma_rdata; // @[lsu.scala 73:30]
+  wire  dccm_ctl_io_dccm_wren; // @[lsu.scala 73:30]
+  wire  dccm_ctl_io_dccm_rden; // @[lsu.scala 73:30]
+  wire [15:0] dccm_ctl_io_dccm_wr_addr_lo; // @[lsu.scala 73:30]
+  wire [15:0] dccm_ctl_io_dccm_wr_addr_hi; // @[lsu.scala 73:30]
+  wire [15:0] dccm_ctl_io_dccm_rd_addr_lo; // @[lsu.scala 73:30]
+  wire [15:0] dccm_ctl_io_dccm_rd_addr_hi; // @[lsu.scala 73:30]
+  wire [38:0] dccm_ctl_io_dccm_wr_data_lo; // @[lsu.scala 73:30]
+  wire [38:0] dccm_ctl_io_dccm_wr_data_hi; // @[lsu.scala 73:30]
+  wire [38:0] dccm_ctl_io_dccm_rd_data_lo; // @[lsu.scala 73:30]
+  wire [38:0] dccm_ctl_io_dccm_rd_data_hi; // @[lsu.scala 73:30]
+  wire  dccm_ctl_io_lsu_pic_picm_wren; // @[lsu.scala 73:30]
+  wire  dccm_ctl_io_lsu_pic_picm_rden; // @[lsu.scala 73:30]
+  wire  dccm_ctl_io_lsu_pic_picm_mken; // @[lsu.scala 73:30]
+  wire [31:0] dccm_ctl_io_lsu_pic_picm_rdaddr; // @[lsu.scala 73:30]
+  wire [31:0] dccm_ctl_io_lsu_pic_picm_wraddr; // @[lsu.scala 73:30]
+  wire [31:0] dccm_ctl_io_lsu_pic_picm_wr_data; // @[lsu.scala 73:30]
+  wire [31:0] dccm_ctl_io_lsu_pic_picm_rd_data; // @[lsu.scala 73:30]
+  wire  stbuf_clock; // @[lsu.scala 74:30]
+  wire  stbuf_reset; // @[lsu.scala 74:30]
+  wire  stbuf_io_lsu_stbuf_c1_clk; // @[lsu.scala 74:30]
+  wire  stbuf_io_lsu_free_c2_clk; // @[lsu.scala 74:30]
+  wire  stbuf_io_lsu_pkt_m_valid; // @[lsu.scala 74:30]
+  wire  stbuf_io_lsu_pkt_m_bits_store; // @[lsu.scala 74:30]
+  wire  stbuf_io_lsu_pkt_m_bits_dma; // @[lsu.scala 74:30]
+  wire  stbuf_io_lsu_pkt_r_valid; // @[lsu.scala 74:30]
+  wire  stbuf_io_lsu_pkt_r_bits_by; // @[lsu.scala 74:30]
+  wire  stbuf_io_lsu_pkt_r_bits_half; // @[lsu.scala 74:30]
+  wire  stbuf_io_lsu_pkt_r_bits_word; // @[lsu.scala 74:30]
+  wire  stbuf_io_lsu_pkt_r_bits_dword; // @[lsu.scala 74:30]
+  wire  stbuf_io_lsu_pkt_r_bits_store; // @[lsu.scala 74:30]
+  wire  stbuf_io_lsu_pkt_r_bits_dma; // @[lsu.scala 74:30]
+  wire  stbuf_io_store_stbuf_reqvld_r; // @[lsu.scala 74:30]
+  wire  stbuf_io_lsu_commit_r; // @[lsu.scala 74:30]
+  wire  stbuf_io_dec_lsu_valid_raw_d; // @[lsu.scala 74:30]
+  wire [31:0] stbuf_io_store_data_hi_r; // @[lsu.scala 74:30]
+  wire [31:0] stbuf_io_store_data_lo_r; // @[lsu.scala 74:30]
+  wire [31:0] stbuf_io_store_datafn_hi_r; // @[lsu.scala 74:30]
+  wire [31:0] stbuf_io_store_datafn_lo_r; // @[lsu.scala 74:30]
+  wire  stbuf_io_lsu_stbuf_commit_any; // @[lsu.scala 74:30]
+  wire [31:0] stbuf_io_lsu_addr_m; // @[lsu.scala 74:30]
+  wire [31:0] stbuf_io_lsu_addr_r; // @[lsu.scala 74:30]
+  wire [31:0] stbuf_io_end_addr_m; // @[lsu.scala 74:30]
+  wire [31:0] stbuf_io_end_addr_r; // @[lsu.scala 74:30]
+  wire  stbuf_io_ldst_dual_d; // @[lsu.scala 74:30]
+  wire  stbuf_io_ldst_dual_m; // @[lsu.scala 74:30]
+  wire  stbuf_io_ldst_dual_r; // @[lsu.scala 74:30]
+  wire  stbuf_io_addr_in_dccm_m; // @[lsu.scala 74:30]
+  wire  stbuf_io_addr_in_dccm_r; // @[lsu.scala 74:30]
+  wire  stbuf_io_stbuf_reqvld_any; // @[lsu.scala 74:30]
+  wire  stbuf_io_stbuf_reqvld_flushed_any; // @[lsu.scala 74:30]
+  wire [15:0] stbuf_io_stbuf_addr_any; // @[lsu.scala 74:30]
+  wire [31:0] stbuf_io_stbuf_data_any; // @[lsu.scala 74:30]
+  wire  stbuf_io_lsu_stbuf_full_any; // @[lsu.scala 74:30]
+  wire  stbuf_io_lsu_stbuf_empty_any; // @[lsu.scala 74:30]
+  wire  stbuf_io_ldst_stbuf_reqvld_r; // @[lsu.scala 74:30]
+  wire [31:0] stbuf_io_stbuf_fwddata_hi_m; // @[lsu.scala 74:30]
+  wire [31:0] stbuf_io_stbuf_fwddata_lo_m; // @[lsu.scala 74:30]
+  wire [3:0] stbuf_io_stbuf_fwdbyteen_hi_m; // @[lsu.scala 74:30]
+  wire [3:0] stbuf_io_stbuf_fwdbyteen_lo_m; // @[lsu.scala 74:30]
+  wire  ecc_clock; // @[lsu.scala 75:30]
+  wire  ecc_reset; // @[lsu.scala 75:30]
+  wire  ecc_io_clk_override; // @[lsu.scala 75:30]
+  wire  ecc_io_lsu_pkt_r_valid; // @[lsu.scala 75:30]
+  wire  ecc_io_lsu_pkt_r_bits_load; // @[lsu.scala 75:30]
+  wire  ecc_io_lsu_pkt_r_bits_store; // @[lsu.scala 75:30]
+  wire [31:0] ecc_io_stbuf_data_any; // @[lsu.scala 75:30]
+  wire  ecc_io_dec_tlu_core_ecc_disable; // @[lsu.scala 75:30]
+  wire  ecc_io_lsu_dccm_rden_r; // @[lsu.scala 75:30]
+  wire  ecc_io_addr_in_dccm_r; // @[lsu.scala 75:30]
+  wire [15:0] ecc_io_lsu_addr_r; // @[lsu.scala 75:30]
+  wire [15:0] ecc_io_end_addr_r; // @[lsu.scala 75:30]
+  wire [31:0] ecc_io_dccm_rdata_hi_r; // @[lsu.scala 75:30]
+  wire [31:0] ecc_io_dccm_rdata_lo_r; // @[lsu.scala 75:30]
+  wire [6:0] ecc_io_dccm_data_ecc_hi_r; // @[lsu.scala 75:30]
+  wire [6:0] ecc_io_dccm_data_ecc_lo_r; // @[lsu.scala 75:30]
+  wire  ecc_io_ld_single_ecc_error_r; // @[lsu.scala 75:30]
+  wire  ecc_io_ld_single_ecc_error_r_ff; // @[lsu.scala 75:30]
+  wire  ecc_io_dma_dccm_wen; // @[lsu.scala 75:30]
+  wire [31:0] ecc_io_dma_dccm_wdata_lo; // @[lsu.scala 75:30]
+  wire [31:0] ecc_io_dma_dccm_wdata_hi; // @[lsu.scala 75:30]
+  wire [31:0] ecc_io_sec_data_hi_r; // @[lsu.scala 75:30]
+  wire [31:0] ecc_io_sec_data_lo_r; // @[lsu.scala 75:30]
+  wire [31:0] ecc_io_sec_data_hi_r_ff; // @[lsu.scala 75:30]
+  wire [31:0] ecc_io_sec_data_lo_r_ff; // @[lsu.scala 75:30]
+  wire [6:0] ecc_io_dma_dccm_wdata_ecc_hi; // @[lsu.scala 75:30]
+  wire [6:0] ecc_io_dma_dccm_wdata_ecc_lo; // @[lsu.scala 75:30]
+  wire [6:0] ecc_io_stbuf_ecc_any; // @[lsu.scala 75:30]
+  wire [6:0] ecc_io_sec_data_ecc_hi_r_ff; // @[lsu.scala 75:30]
+  wire [6:0] ecc_io_sec_data_ecc_lo_r_ff; // @[lsu.scala 75:30]
+  wire  ecc_io_single_ecc_error_hi_r; // @[lsu.scala 75:30]
+  wire  ecc_io_single_ecc_error_lo_r; // @[lsu.scala 75:30]
+  wire  ecc_io_lsu_single_ecc_error_r; // @[lsu.scala 75:30]
+  wire  ecc_io_lsu_double_ecc_error_r; // @[lsu.scala 75:30]
+  wire  ecc_io_lsu_single_ecc_error_m; // @[lsu.scala 75:30]
+  wire  trigger_io_trigger_pkt_any_0_select; // @[lsu.scala 76:30]
+  wire  trigger_io_trigger_pkt_any_0_match_pkt; // @[lsu.scala 76:30]
+  wire  trigger_io_trigger_pkt_any_0_store; // @[lsu.scala 76:30]
+  wire  trigger_io_trigger_pkt_any_0_load; // @[lsu.scala 76:30]
+  wire  trigger_io_trigger_pkt_any_0_m; // @[lsu.scala 76:30]
+  wire [31:0] trigger_io_trigger_pkt_any_0_tdata2; // @[lsu.scala 76:30]
+  wire  trigger_io_trigger_pkt_any_1_select; // @[lsu.scala 76:30]
+  wire  trigger_io_trigger_pkt_any_1_match_pkt; // @[lsu.scala 76:30]
+  wire  trigger_io_trigger_pkt_any_1_store; // @[lsu.scala 76:30]
+  wire  trigger_io_trigger_pkt_any_1_load; // @[lsu.scala 76:30]
+  wire  trigger_io_trigger_pkt_any_1_m; // @[lsu.scala 76:30]
+  wire [31:0] trigger_io_trigger_pkt_any_1_tdata2; // @[lsu.scala 76:30]
+  wire  trigger_io_trigger_pkt_any_2_select; // @[lsu.scala 76:30]
+  wire  trigger_io_trigger_pkt_any_2_match_pkt; // @[lsu.scala 76:30]
+  wire  trigger_io_trigger_pkt_any_2_store; // @[lsu.scala 76:30]
+  wire  trigger_io_trigger_pkt_any_2_load; // @[lsu.scala 76:30]
+  wire  trigger_io_trigger_pkt_any_2_m; // @[lsu.scala 76:30]
+  wire [31:0] trigger_io_trigger_pkt_any_2_tdata2; // @[lsu.scala 76:30]
+  wire  trigger_io_trigger_pkt_any_3_select; // @[lsu.scala 76:30]
+  wire  trigger_io_trigger_pkt_any_3_match_pkt; // @[lsu.scala 76:30]
+  wire  trigger_io_trigger_pkt_any_3_store; // @[lsu.scala 76:30]
+  wire  trigger_io_trigger_pkt_any_3_load; // @[lsu.scala 76:30]
+  wire  trigger_io_trigger_pkt_any_3_m; // @[lsu.scala 76:30]
+  wire [31:0] trigger_io_trigger_pkt_any_3_tdata2; // @[lsu.scala 76:30]
+  wire  trigger_io_lsu_pkt_m_valid; // @[lsu.scala 76:30]
+  wire  trigger_io_lsu_pkt_m_bits_half; // @[lsu.scala 76:30]
+  wire  trigger_io_lsu_pkt_m_bits_word; // @[lsu.scala 76:30]
+  wire  trigger_io_lsu_pkt_m_bits_load; // @[lsu.scala 76:30]
+  wire  trigger_io_lsu_pkt_m_bits_store; // @[lsu.scala 76:30]
+  wire  trigger_io_lsu_pkt_m_bits_dma; // @[lsu.scala 76:30]
+  wire [31:0] trigger_io_lsu_addr_m; // @[lsu.scala 76:30]
+  wire [31:0] trigger_io_store_data_m; // @[lsu.scala 76:30]
+  wire [3:0] trigger_io_lsu_trigger_match_m; // @[lsu.scala 76:30]
+  wire  clkdomain_clock; // @[lsu.scala 77:30]
+  wire  clkdomain_reset; // @[lsu.scala 77:30]
+  wire  clkdomain_io_active_clk; // @[lsu.scala 77:30]
+  wire  clkdomain_io_clk_override; // @[lsu.scala 77:30]
+  wire  clkdomain_io_dec_tlu_force_halt; // @[lsu.scala 77:30]
+  wire  clkdomain_io_dma_dccm_req; // @[lsu.scala 77:30]
+  wire  clkdomain_io_ldst_stbuf_reqvld_r; // @[lsu.scala 77:30]
+  wire  clkdomain_io_stbuf_reqvld_any; // @[lsu.scala 77:30]
+  wire  clkdomain_io_stbuf_reqvld_flushed_any; // @[lsu.scala 77:30]
+  wire  clkdomain_io_lsu_busreq_r; // @[lsu.scala 77:30]
+  wire  clkdomain_io_lsu_bus_buffer_pend_any; // @[lsu.scala 77:30]
+  wire  clkdomain_io_lsu_bus_buffer_empty_any; // @[lsu.scala 77:30]
+  wire  clkdomain_io_lsu_stbuf_empty_any; // @[lsu.scala 77:30]
+  wire  clkdomain_io_lsu_bus_clk_en; // @[lsu.scala 77:30]
+  wire  clkdomain_io_lsu_p_valid; // @[lsu.scala 77:30]
+  wire  clkdomain_io_lsu_pkt_d_valid; // @[lsu.scala 77:30]
+  wire  clkdomain_io_lsu_pkt_d_bits_store; // @[lsu.scala 77:30]
+  wire  clkdomain_io_lsu_pkt_m_valid; // @[lsu.scala 77:30]
+  wire  clkdomain_io_lsu_pkt_m_bits_store; // @[lsu.scala 77:30]
+  wire  clkdomain_io_lsu_pkt_r_valid; // @[lsu.scala 77:30]
+  wire  clkdomain_io_lsu_bus_obuf_c1_clken; // @[lsu.scala 77:30]
+  wire  clkdomain_io_lsu_busm_clken; // @[lsu.scala 77:30]
+  wire  clkdomain_io_lsu_c1_m_clk; // @[lsu.scala 77:30]
+  wire  clkdomain_io_lsu_c1_r_clk; // @[lsu.scala 77:30]
+  wire  clkdomain_io_lsu_c2_m_clk; // @[lsu.scala 77:30]
+  wire  clkdomain_io_lsu_c2_r_clk; // @[lsu.scala 77:30]
+  wire  clkdomain_io_lsu_store_c1_m_clk; // @[lsu.scala 77:30]
+  wire  clkdomain_io_lsu_store_c1_r_clk; // @[lsu.scala 77:30]
+  wire  clkdomain_io_lsu_stbuf_c1_clk; // @[lsu.scala 77:30]
+  wire  clkdomain_io_lsu_bus_ibuf_c1_clk; // @[lsu.scala 77:30]
+  wire  clkdomain_io_lsu_bus_buf_c1_clk; // @[lsu.scala 77:30]
+  wire  clkdomain_io_lsu_free_c2_clk; // @[lsu.scala 77:30]
+  wire  bus_intf_clock; // @[lsu.scala 78:30]
+  wire  bus_intf_reset; // @[lsu.scala 78:30]
+  wire  bus_intf_io_tlu_busbuff_lsu_pmu_bus_trxn; // @[lsu.scala 78:30]
+  wire  bus_intf_io_tlu_busbuff_lsu_pmu_bus_misaligned; // @[lsu.scala 78:30]
+  wire  bus_intf_io_tlu_busbuff_lsu_pmu_bus_error; // @[lsu.scala 78:30]
+  wire  bus_intf_io_tlu_busbuff_lsu_pmu_bus_busy; // @[lsu.scala 78:30]
+  wire  bus_intf_io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[lsu.scala 78:30]
+  wire  bus_intf_io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu.scala 78:30]
+  wire  bus_intf_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu.scala 78:30]
+  wire  bus_intf_io_tlu_busbuff_lsu_imprecise_error_load_any; // @[lsu.scala 78:30]
+  wire  bus_intf_io_tlu_busbuff_lsu_imprecise_error_store_any; // @[lsu.scala 78:30]
+  wire [31:0] bus_intf_io_tlu_busbuff_lsu_imprecise_error_addr_any; // @[lsu.scala 78:30]
+  wire  bus_intf_io_lsu_c1_r_clk; // @[lsu.scala 78:30]
+  wire  bus_intf_io_lsu_c2_r_clk; // @[lsu.scala 78:30]
+  wire  bus_intf_io_lsu_bus_ibuf_c1_clk; // @[lsu.scala 78:30]
+  wire  bus_intf_io_lsu_bus_buf_c1_clk; // @[lsu.scala 78:30]
+  wire  bus_intf_io_lsu_free_c2_clk; // @[lsu.scala 78:30]
+  wire  bus_intf_io_active_clk; // @[lsu.scala 78:30]
+  wire  bus_intf_io_axi_aw_ready; // @[lsu.scala 78:30]
+  wire [31:0] bus_intf_io_axi_aw_bits_addr; // @[lsu.scala 78:30]
+  wire [3:0] bus_intf_io_axi_aw_bits_region; // @[lsu.scala 78:30]
+  wire  bus_intf_io_axi_w_ready; // @[lsu.scala 78:30]
+  wire [63:0] bus_intf_io_axi_w_bits_data; // @[lsu.scala 78:30]
+  wire  bus_intf_io_axi_b_valid; // @[lsu.scala 78:30]
+  wire [1:0] bus_intf_io_axi_b_bits_resp; // @[lsu.scala 78:30]
+  wire [2:0] bus_intf_io_axi_b_bits_id; // @[lsu.scala 78:30]
+  wire  bus_intf_io_axi_ar_ready; // @[lsu.scala 78:30]
+  wire  bus_intf_io_axi_ar_valid; // @[lsu.scala 78:30]
+  wire [31:0] bus_intf_io_axi_ar_bits_addr; // @[lsu.scala 78:30]
+  wire [3:0] bus_intf_io_axi_ar_bits_region; // @[lsu.scala 78:30]
+  wire  bus_intf_io_axi_r_valid; // @[lsu.scala 78:30]
+  wire [2:0] bus_intf_io_axi_r_bits_id; // @[lsu.scala 78:30]
+  wire [63:0] bus_intf_io_axi_r_bits_data; // @[lsu.scala 78:30]
+  wire [1:0] bus_intf_io_axi_r_bits_resp; // @[lsu.scala 78:30]
+  wire  bus_intf_io_dec_lsu_valid_raw_d; // @[lsu.scala 78:30]
+  wire  bus_intf_io_lsu_busreq_m; // @[lsu.scala 78:30]
+  wire  bus_intf_io_lsu_pkt_m_valid; // @[lsu.scala 78:30]
+  wire  bus_intf_io_lsu_pkt_m_bits_by; // @[lsu.scala 78:30]
+  wire  bus_intf_io_lsu_pkt_m_bits_half; // @[lsu.scala 78:30]
+  wire  bus_intf_io_lsu_pkt_m_bits_word; // @[lsu.scala 78:30]
+  wire  bus_intf_io_lsu_pkt_m_bits_load; // @[lsu.scala 78:30]
+  wire  bus_intf_io_lsu_pkt_r_valid; // @[lsu.scala 78:30]
+  wire  bus_intf_io_lsu_pkt_r_bits_by; // @[lsu.scala 78:30]
+  wire  bus_intf_io_lsu_pkt_r_bits_half; // @[lsu.scala 78:30]
+  wire  bus_intf_io_lsu_pkt_r_bits_word; // @[lsu.scala 78:30]
+  wire  bus_intf_io_lsu_pkt_r_bits_load; // @[lsu.scala 78:30]
+  wire  bus_intf_io_lsu_pkt_r_bits_store; // @[lsu.scala 78:30]
+  wire  bus_intf_io_lsu_pkt_r_bits_unsign; // @[lsu.scala 78:30]
+  wire [31:0] bus_intf_io_lsu_addr_m; // @[lsu.scala 78:30]
+  wire [31:0] bus_intf_io_lsu_addr_r; // @[lsu.scala 78:30]
+  wire [31:0] bus_intf_io_end_addr_m; // @[lsu.scala 78:30]
+  wire [31:0] bus_intf_io_end_addr_r; // @[lsu.scala 78:30]
+  wire  bus_intf_io_ldst_dual_d; // @[lsu.scala 78:30]
+  wire  bus_intf_io_ldst_dual_m; // @[lsu.scala 78:30]
+  wire  bus_intf_io_ldst_dual_r; // @[lsu.scala 78:30]
+  wire [31:0] bus_intf_io_store_data_r; // @[lsu.scala 78:30]
+  wire  bus_intf_io_dec_tlu_force_halt; // @[lsu.scala 78:30]
+  wire  bus_intf_io_lsu_commit_r; // @[lsu.scala 78:30]
+  wire  bus_intf_io_is_sideeffects_m; // @[lsu.scala 78:30]
+  wire  bus_intf_io_flush_m_up; // @[lsu.scala 78:30]
+  wire  bus_intf_io_flush_r; // @[lsu.scala 78:30]
+  wire  bus_intf_io_lsu_busreq_r; // @[lsu.scala 78:30]
+  wire  bus_intf_io_lsu_bus_buffer_pend_any; // @[lsu.scala 78:30]
+  wire  bus_intf_io_lsu_bus_buffer_full_any; // @[lsu.scala 78:30]
+  wire  bus_intf_io_lsu_bus_buffer_empty_any; // @[lsu.scala 78:30]
+  wire [31:0] bus_intf_io_bus_read_data_m; // @[lsu.scala 78:30]
+  wire  bus_intf_io_dctl_busbuff_lsu_nonblock_load_valid_m; // @[lsu.scala 78:30]
+  wire [1:0] bus_intf_io_dctl_busbuff_lsu_nonblock_load_tag_m; // @[lsu.scala 78:30]
+  wire  bus_intf_io_dctl_busbuff_lsu_nonblock_load_inv_r; // @[lsu.scala 78:30]
+  wire [1:0] bus_intf_io_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[lsu.scala 78:30]
+  wire  bus_intf_io_dctl_busbuff_lsu_nonblock_load_data_valid; // @[lsu.scala 78:30]
+  wire  bus_intf_io_dctl_busbuff_lsu_nonblock_load_data_error; // @[lsu.scala 78:30]
+  wire [1:0] bus_intf_io_dctl_busbuff_lsu_nonblock_load_data_tag; // @[lsu.scala 78:30]
+  wire [31:0] bus_intf_io_dctl_busbuff_lsu_nonblock_load_data; // @[lsu.scala 78:30]
+  wire  bus_intf_io_lsu_bus_clk_en; // @[lsu.scala 78:30]
+  wire  _T = stbuf_io_lsu_stbuf_full_any | bus_intf_io_lsu_bus_buffer_full_any; // @[lsu.scala 84:57]
+  wire  _T_3 = ~lsu_lsc_ctl_io_lsu_pkt_m_bits_dma; // @[lsu.scala 91:58]
+  wire  _T_4 = lsu_lsc_ctl_io_lsu_pkt_m_valid & _T_3; // @[lsu.scala 91:56]
+  wire  _T_5 = lsu_lsc_ctl_io_addr_in_dccm_m | lsu_lsc_ctl_io_addr_in_pic_m; // @[lsu.scala 91:126]
+  wire  _T_6 = _T_4 & _T_5; // @[lsu.scala 91:93]
+  wire  ldst_nodma_mtor = _T_6 & lsu_lsc_ctl_io_lsu_pkt_m_bits_store; // @[lsu.scala 91:158]
+  wire  _T_7 = io_dec_lsu_valid_raw_d | ldst_nodma_mtor; // @[lsu.scala 92:53]
+  wire  _T_8 = _T_7 | dccm_ctl_io_ld_single_ecc_error_r_ff; // @[lsu.scala 92:71]
+  wire  _T_10 = io_lsu_dma_dma_lsc_ctl_dma_dccm_req & io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[lsu.scala 93:58]
+  wire  _T_11 = _T_10 & lsu_lsc_ctl_io_addr_in_dccm_d; // @[lsu.scala 93:97]
   wire [5:0] _T_15 = {io_lsu_dma_dma_lsc_ctl_dma_mem_addr[2:0],3'h0}; // @[Cat.scala 29:58]
-  wire [63:0] dma_dccm_wdata = io_lsu_dma_dma_lsc_ctl_dma_mem_wdata >> _T_15; // @[lsu.scala 90:58]
-  wire  _T_21 = ~lsu_lsc_ctl_io_lsu_pkt_r_bits_dma; // @[lsu.scala 101:130]
-  wire  _T_22 = lsu_lsc_ctl_io_lsu_pkt_r_valid & _T_21; // @[lsu.scala 101:128]
-  wire  _T_23 = _T_4 | _T_22; // @[lsu.scala 101:94]
-  wire  _T_24 = ~_T_23; // @[lsu.scala 101:22]
-  wire  _T_26 = lsu_lsc_ctl_io_lsu_pkt_m_valid | lsu_lsc_ctl_io_lsu_pkt_r_valid; // @[lsu.scala 102:52]
-  wire  _T_27 = _T_26 | dccm_ctl_io_ld_single_ecc_error_r_ff; // @[lsu.scala 102:85]
-  wire  _T_28 = ~bus_intf_io_lsu_bus_buffer_empty_any; // @[lsu.scala 102:127]
-  wire  _T_30 = lsu_lsc_ctl_io_lsu_pkt_r_valid & lsu_lsc_ctl_io_lsu_pkt_r_bits_store; // @[lsu.scala 104:61]
-  wire  _T_31 = _T_30 & lsu_lsc_ctl_io_addr_in_dccm_r; // @[lsu.scala 104:99]
-  wire  _T_32 = ~io_dec_tlu_i0_kill_writeb_r; // @[lsu.scala 104:133]
-  wire  _T_33 = _T_31 & _T_32; // @[lsu.scala 104:131]
-  wire  _T_35 = lsu_lsc_ctl_io_lsu_pkt_r_bits_by | lsu_lsc_ctl_io_lsu_pkt_r_bits_half; // @[lsu.scala 104:217]
-  wire  _T_36 = ~ecc_io_lsu_double_ecc_error_r; // @[lsu.scala 104:257]
-  wire  _T_37 = _T_35 & _T_36; // @[lsu.scala 104:255]
-  wire  _T_38 = _T_21 | _T_37; // @[lsu.scala 104:180]
-  wire  _T_39 = lsu_lsc_ctl_io_lsu_pkt_m_bits_load | lsu_lsc_ctl_io_lsu_pkt_m_bits_store; // @[lsu.scala 106:90]
-  wire  _T_43 = _T_39 & lsu_lsc_ctl_io_addr_external_m; // @[lsu.scala 108:131]
-  wire  _T_44 = lsu_lsc_ctl_io_lsu_pkt_m_valid & _T_43; // @[lsu.scala 108:53]
-  wire  _T_45 = ~io_dec_tlu_flush_lower_r; // @[lsu.scala 108:167]
-  wire  _T_46 = _T_44 & _T_45; // @[lsu.scala 108:165]
-  wire  _T_47 = ~lsu_lsc_ctl_io_lsu_exc_m; // @[lsu.scala 108:181]
-  wire  _T_48 = _T_46 & _T_47; // @[lsu.scala 108:179]
-  wire  _T_49 = ~lsu_lsc_ctl_io_lsu_pkt_m_bits_fast_int; // @[lsu.scala 108:209]
-  wire  _T_57 = lsu_lsc_ctl_io_lsu_pkt_m_bits_half & lsu_lsc_ctl_io_lsu_addr_m[0]; // @[lsu.scala 114:100]
-  wire  _T_59 = |lsu_lsc_ctl_io_lsu_addr_m[1:0]; // @[lsu.scala 114:203]
-  wire  _T_60 = lsu_lsc_ctl_io_lsu_pkt_m_bits_word & _T_59; // @[lsu.scala 114:170]
-  wire  _T_61 = _T_57 | _T_60; // @[lsu.scala 114:132]
-  wire  _T_63 = lsu_lsc_ctl_io_lsu_pkt_m_valid & lsu_lsc_ctl_io_lsu_pkt_m_bits_load; // @[lsu.scala 115:73]
-  wire  _T_65 = lsu_lsc_ctl_io_lsu_pkt_m_valid & lsu_lsc_ctl_io_lsu_pkt_m_bits_store; // @[lsu.scala 116:73]
-  reg [2:0] dma_mem_tag_m; // @[lsu.scala 339:67]
-  reg  lsu_raw_fwd_hi_r; // @[lsu.scala 340:67]
-  reg  lsu_raw_fwd_lo_r; // @[lsu.scala 341:67]
-  lsu_lsc_ctl lsu_lsc_ctl ( // @[lsu.scala 65:30]
+  wire [63:0] dma_dccm_wdata = io_lsu_dma_dma_lsc_ctl_dma_mem_wdata >> _T_15; // @[lsu.scala 95:58]
+  wire  _T_21 = ~lsu_lsc_ctl_io_lsu_pkt_r_bits_dma; // @[lsu.scala 106:130]
+  wire  _T_22 = lsu_lsc_ctl_io_lsu_pkt_r_valid & _T_21; // @[lsu.scala 106:128]
+  wire  _T_23 = _T_4 | _T_22; // @[lsu.scala 106:94]
+  wire  _T_24 = ~_T_23; // @[lsu.scala 106:22]
+  wire  _T_26 = lsu_lsc_ctl_io_lsu_pkt_m_valid | lsu_lsc_ctl_io_lsu_pkt_r_valid; // @[lsu.scala 107:52]
+  wire  _T_27 = _T_26 | dccm_ctl_io_ld_single_ecc_error_r_ff; // @[lsu.scala 107:85]
+  wire  _T_28 = ~bus_intf_io_lsu_bus_buffer_empty_any; // @[lsu.scala 107:127]
+  wire  _T_30 = lsu_lsc_ctl_io_lsu_pkt_r_valid & lsu_lsc_ctl_io_lsu_pkt_r_bits_store; // @[lsu.scala 109:61]
+  wire  _T_31 = _T_30 & lsu_lsc_ctl_io_addr_in_dccm_r; // @[lsu.scala 109:99]
+  wire  _T_32 = ~io_dec_tlu_i0_kill_writeb_r; // @[lsu.scala 109:133]
+  wire  _T_33 = _T_31 & _T_32; // @[lsu.scala 109:131]
+  wire  _T_35 = lsu_lsc_ctl_io_lsu_pkt_r_bits_by | lsu_lsc_ctl_io_lsu_pkt_r_bits_half; // @[lsu.scala 109:217]
+  wire  _T_36 = ~ecc_io_lsu_double_ecc_error_r; // @[lsu.scala 109:257]
+  wire  _T_37 = _T_35 & _T_36; // @[lsu.scala 109:255]
+  wire  _T_38 = _T_21 | _T_37; // @[lsu.scala 109:180]
+  wire  _T_39 = lsu_lsc_ctl_io_lsu_pkt_m_bits_load | lsu_lsc_ctl_io_lsu_pkt_m_bits_store; // @[lsu.scala 111:90]
+  wire  _T_43 = _T_39 & lsu_lsc_ctl_io_addr_external_m; // @[lsu.scala 113:131]
+  wire  _T_44 = lsu_lsc_ctl_io_lsu_pkt_m_valid & _T_43; // @[lsu.scala 113:53]
+  wire  _T_45 = ~io_dec_tlu_flush_lower_r; // @[lsu.scala 113:167]
+  wire  _T_46 = _T_44 & _T_45; // @[lsu.scala 113:165]
+  wire  _T_47 = ~lsu_lsc_ctl_io_lsu_exc_m; // @[lsu.scala 113:181]
+  wire  _T_48 = _T_46 & _T_47; // @[lsu.scala 113:179]
+  wire  _T_49 = ~lsu_lsc_ctl_io_lsu_pkt_m_bits_fast_int; // @[lsu.scala 113:209]
+  wire [31:0] lsu_addr_d = lsu_lsc_ctl_io_lsu_addr_d; // @[lsu.scala 153:14]
+  wire [31:0] lsu_addr_m = lsu_lsc_ctl_io_lsu_addr_m; // @[lsu.scala 154:14]
+  wire [31:0] lsu_addr_r = lsu_lsc_ctl_io_lsu_addr_r; // @[lsu.scala 155:14]
+  wire  _T_57 = lsu_lsc_ctl_io_lsu_pkt_m_bits_half & lsu_lsc_ctl_io_lsu_addr_m[0]; // @[lsu.scala 119:100]
+  wire  _T_59 = |lsu_lsc_ctl_io_lsu_addr_m[1:0]; // @[lsu.scala 119:203]
+  wire  _T_60 = lsu_lsc_ctl_io_lsu_pkt_m_bits_word & _T_59; // @[lsu.scala 119:170]
+  wire  _T_61 = _T_57 | _T_60; // @[lsu.scala 119:132]
+  wire  _T_63 = lsu_lsc_ctl_io_lsu_pkt_m_valid & lsu_lsc_ctl_io_lsu_pkt_m_bits_load; // @[lsu.scala 120:73]
+  wire  _T_65 = lsu_lsc_ctl_io_lsu_pkt_m_valid & lsu_lsc_ctl_io_lsu_pkt_m_bits_store; // @[lsu.scala 121:73]
+  wire  _T_71 = lsu_lsc_ctl_io_addr_external_m & lsu_lsc_ctl_io_lsu_pkt_m_valid; // @[lsu.scala 332:104]
+  wire [31:0] _T_73 = _T_71 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
+  wire  lsu_busreq_r = bus_intf_io_lsu_busreq_r; // @[lsu.scala 346:16]
+  wire [31:0] _T_76 = lsu_busreq_r ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
+  reg [2:0] dma_mem_tag_m; // @[lsu.scala 350:67]
+  reg  lsu_raw_fwd_hi_r; // @[lsu.scala 351:67]
+  reg  lsu_raw_fwd_lo_r; // @[lsu.scala 352:67]
+  lsu_lsc_ctl lsu_lsc_ctl ( // @[lsu.scala 70:30]
     .clock(lsu_lsc_ctl_clock),
     .reset(lsu_lsc_ctl_reset),
     .io_clk_override(lsu_lsc_ctl_io_clk_override),
@@ -11135,16 +10564,15 @@ module lsu(
     .io_lsu_c2_m_clk(lsu_lsc_ctl_io_lsu_c2_m_clk),
     .io_lsu_c2_r_clk(lsu_lsc_ctl_io_lsu_c2_r_clk),
     .io_lsu_store_c1_m_clk(lsu_lsc_ctl_io_lsu_store_c1_m_clk),
+    .io_lsu_ld_data_r(lsu_lsc_ctl_io_lsu_ld_data_r),
     .io_lsu_ld_data_corr_r(lsu_lsc_ctl_io_lsu_ld_data_corr_r),
     .io_lsu_single_ecc_error_r(lsu_lsc_ctl_io_lsu_single_ecc_error_r),
     .io_lsu_double_ecc_error_r(lsu_lsc_ctl_io_lsu_double_ecc_error_r),
-    .io_lsu_ld_data_m(lsu_lsc_ctl_io_lsu_ld_data_m),
-    .io_lsu_single_ecc_error_m(lsu_lsc_ctl_io_lsu_single_ecc_error_m),
-    .io_lsu_double_ecc_error_m(lsu_lsc_ctl_io_lsu_double_ecc_error_m),
     .io_flush_m_up(lsu_lsc_ctl_io_flush_m_up),
     .io_flush_r(lsu_lsc_ctl_io_flush_r),
     .io_ldst_dual_d(lsu_lsc_ctl_io_ldst_dual_d),
     .io_ldst_dual_m(lsu_lsc_ctl_io_ldst_dual_m),
+    .io_ldst_dual_r(lsu_lsc_ctl_io_ldst_dual_r),
     .io_lsu_exu_exu_lsu_rs1_d(lsu_lsc_ctl_io_lsu_exu_exu_lsu_rs1_d),
     .io_lsu_exu_exu_lsu_rs2_d(lsu_lsc_ctl_io_lsu_exu_exu_lsu_rs2_d),
     .io_lsu_p_valid(lsu_lsc_ctl_io_lsu_p_valid),
@@ -11223,6 +10651,7 @@ module lsu(
     .io_lsu_pkt_m_bits_dma(lsu_lsc_ctl_io_lsu_pkt_m_bits_dma),
     .io_lsu_pkt_m_bits_store_data_bypass_m(lsu_lsc_ctl_io_lsu_pkt_m_bits_store_data_bypass_m),
     .io_lsu_pkt_r_valid(lsu_lsc_ctl_io_lsu_pkt_r_valid),
+    .io_lsu_pkt_r_bits_fast_int(lsu_lsc_ctl_io_lsu_pkt_r_bits_fast_int),
     .io_lsu_pkt_r_bits_by(lsu_lsc_ctl_io_lsu_pkt_r_bits_by),
     .io_lsu_pkt_r_bits_half(lsu_lsc_ctl_io_lsu_pkt_r_bits_half),
     .io_lsu_pkt_r_bits_word(lsu_lsc_ctl_io_lsu_pkt_r_bits_word),
@@ -11230,15 +10659,16 @@ module lsu(
     .io_lsu_pkt_r_bits_load(lsu_lsc_ctl_io_lsu_pkt_r_bits_load),
     .io_lsu_pkt_r_bits_store(lsu_lsc_ctl_io_lsu_pkt_r_bits_store),
     .io_lsu_pkt_r_bits_unsign(lsu_lsc_ctl_io_lsu_pkt_r_bits_unsign),
-    .io_lsu_pkt_r_bits_dma(lsu_lsc_ctl_io_lsu_pkt_r_bits_dma),
-    .io_scan_mode(lsu_lsc_ctl_io_scan_mode)
+    .io_lsu_pkt_r_bits_dma(lsu_lsc_ctl_io_lsu_pkt_r_bits_dma)
   );
-  lsu_dccm_ctl dccm_ctl ( // @[lsu.scala 68:30]
+  lsu_dccm_ctl dccm_ctl ( // @[lsu.scala 73:30]
     .clock(dccm_ctl_clock),
     .reset(dccm_ctl_reset),
     .io_clk_override(dccm_ctl_io_clk_override),
     .io_lsu_c2_m_clk(dccm_ctl_io_lsu_c2_m_clk),
+    .io_lsu_c2_r_clk(dccm_ctl_io_lsu_c2_r_clk),
     .io_lsu_free_c2_clk(dccm_ctl_io_lsu_free_c2_clk),
+    .io_lsu_c1_r_clk(dccm_ctl_io_lsu_c1_r_clk),
     .io_lsu_store_c1_r_clk(dccm_ctl_io_lsu_store_c1_r_clk),
     .io_lsu_pkt_d_valid(dccm_ctl_io_lsu_pkt_d_valid),
     .io_lsu_pkt_d_bits_word(dccm_ctl_io_lsu_pkt_d_bits_word),
@@ -11247,10 +10677,6 @@ module lsu(
     .io_lsu_pkt_d_bits_store(dccm_ctl_io_lsu_pkt_d_bits_store),
     .io_lsu_pkt_d_bits_dma(dccm_ctl_io_lsu_pkt_d_bits_dma),
     .io_lsu_pkt_m_valid(dccm_ctl_io_lsu_pkt_m_valid),
-    .io_lsu_pkt_m_bits_by(dccm_ctl_io_lsu_pkt_m_bits_by),
-    .io_lsu_pkt_m_bits_half(dccm_ctl_io_lsu_pkt_m_bits_half),
-    .io_lsu_pkt_m_bits_word(dccm_ctl_io_lsu_pkt_m_bits_word),
-    .io_lsu_pkt_m_bits_load(dccm_ctl_io_lsu_pkt_m_bits_load),
     .io_lsu_pkt_m_bits_store(dccm_ctl_io_lsu_pkt_m_bits_store),
     .io_lsu_pkt_m_bits_dma(dccm_ctl_io_lsu_pkt_m_bits_dma),
     .io_lsu_pkt_r_valid(dccm_ctl_io_lsu_pkt_r_valid),
@@ -11270,6 +10696,7 @@ module lsu(
     .io_lsu_raw_fwd_hi_r(dccm_ctl_io_lsu_raw_fwd_hi_r),
     .io_lsu_commit_r(dccm_ctl_io_lsu_commit_r),
     .io_ldst_dual_m(dccm_ctl_io_ldst_dual_m),
+    .io_ldst_dual_r(dccm_ctl_io_ldst_dual_r),
     .io_lsu_addr_d(dccm_ctl_io_lsu_addr_d),
     .io_lsu_addr_m(dccm_ctl_io_lsu_addr_m),
     .io_lsu_addr_r(dccm_ctl_io_lsu_addr_r),
@@ -11284,10 +10711,17 @@ module lsu(
     .io_stbuf_fwddata_lo_m(dccm_ctl_io_stbuf_fwddata_lo_m),
     .io_stbuf_fwdbyteen_lo_m(dccm_ctl_io_stbuf_fwdbyteen_lo_m),
     .io_stbuf_fwdbyteen_hi_m(dccm_ctl_io_stbuf_fwdbyteen_hi_m),
+    .io_dccm_rdata_hi_r(dccm_ctl_io_dccm_rdata_hi_r),
+    .io_dccm_rdata_lo_r(dccm_ctl_io_dccm_rdata_lo_r),
+    .io_dccm_data_ecc_hi_r(dccm_ctl_io_dccm_data_ecc_hi_r),
+    .io_dccm_data_ecc_lo_r(dccm_ctl_io_dccm_data_ecc_lo_r),
+    .io_lsu_ld_data_r(dccm_ctl_io_lsu_ld_data_r),
     .io_lsu_ld_data_corr_r(dccm_ctl_io_lsu_ld_data_corr_r),
     .io_lsu_double_ecc_error_r(dccm_ctl_io_lsu_double_ecc_error_r),
     .io_single_ecc_error_hi_r(dccm_ctl_io_single_ecc_error_hi_r),
     .io_single_ecc_error_lo_r(dccm_ctl_io_single_ecc_error_lo_r),
+    .io_sec_data_hi_r(dccm_ctl_io_sec_data_hi_r),
+    .io_sec_data_lo_r(dccm_ctl_io_sec_data_lo_r),
     .io_sec_data_hi_r_ff(dccm_ctl_io_sec_data_hi_r_ff),
     .io_sec_data_lo_r_ff(dccm_ctl_io_sec_data_lo_r_ff),
     .io_sec_data_ecc_hi_r_ff(dccm_ctl_io_sec_data_ecc_hi_r_ff),
@@ -11296,10 +10730,6 @@ module lsu(
     .io_dccm_rdata_lo_m(dccm_ctl_io_dccm_rdata_lo_m),
     .io_dccm_data_ecc_hi_m(dccm_ctl_io_dccm_data_ecc_hi_m),
     .io_dccm_data_ecc_lo_m(dccm_ctl_io_dccm_data_ecc_lo_m),
-    .io_lsu_ld_data_m(dccm_ctl_io_lsu_ld_data_m),
-    .io_lsu_double_ecc_error_m(dccm_ctl_io_lsu_double_ecc_error_m),
-    .io_sec_data_hi_m(dccm_ctl_io_sec_data_hi_m),
-    .io_sec_data_lo_m(dccm_ctl_io_sec_data_lo_m),
     .io_store_data_m(dccm_ctl_io_store_data_m),
     .io_dma_dccm_wen(dccm_ctl_io_dma_dccm_wen),
     .io_dma_pic_wen(dccm_ctl_io_dma_pic_wen),
@@ -11318,6 +10748,7 @@ module lsu(
     .io_picm_mask_data_m(dccm_ctl_io_picm_mask_data_m),
     .io_lsu_stbuf_commit_any(dccm_ctl_io_lsu_stbuf_commit_any),
     .io_lsu_dccm_rden_m(dccm_ctl_io_lsu_dccm_rden_m),
+    .io_lsu_dccm_rden_r(dccm_ctl_io_lsu_dccm_rden_r),
     .io_dma_dccm_ctl_dma_mem_addr(dccm_ctl_io_dma_dccm_ctl_dma_mem_addr),
     .io_dma_dccm_ctl_dma_mem_wdata(dccm_ctl_io_dma_dccm_ctl_dma_mem_wdata),
     .io_dma_dccm_ctl_dccm_dma_rvalid(dccm_ctl_io_dma_dccm_ctl_dccm_dma_rvalid),
@@ -11340,10 +10771,9 @@ module lsu(
     .io_lsu_pic_picm_rdaddr(dccm_ctl_io_lsu_pic_picm_rdaddr),
     .io_lsu_pic_picm_wraddr(dccm_ctl_io_lsu_pic_picm_wraddr),
     .io_lsu_pic_picm_wr_data(dccm_ctl_io_lsu_pic_picm_wr_data),
-    .io_lsu_pic_picm_rd_data(dccm_ctl_io_lsu_pic_picm_rd_data),
-    .io_scan_mode(dccm_ctl_io_scan_mode)
+    .io_lsu_pic_picm_rd_data(dccm_ctl_io_lsu_pic_picm_rd_data)
   );
-  lsu_stbuf stbuf ( // @[lsu.scala 69:30]
+  lsu_stbuf stbuf ( // @[lsu.scala 74:30]
     .clock(stbuf_clock),
     .reset(stbuf_reset),
     .io_lsu_stbuf_c1_clk(stbuf_io_lsu_stbuf_c1_clk),
@@ -11375,7 +10805,6 @@ module lsu(
     .io_ldst_dual_r(stbuf_io_ldst_dual_r),
     .io_addr_in_dccm_m(stbuf_io_addr_in_dccm_m),
     .io_addr_in_dccm_r(stbuf_io_addr_in_dccm_r),
-    .io_scan_mode(stbuf_io_scan_mode),
     .io_stbuf_reqvld_any(stbuf_io_stbuf_reqvld_any),
     .io_stbuf_reqvld_flushed_any(stbuf_io_stbuf_reqvld_flushed_any),
     .io_stbuf_addr_any(stbuf_io_stbuf_addr_any),
@@ -11388,35 +10817,30 @@ module lsu(
     .io_stbuf_fwdbyteen_hi_m(stbuf_io_stbuf_fwdbyteen_hi_m),
     .io_stbuf_fwdbyteen_lo_m(stbuf_io_stbuf_fwdbyteen_lo_m)
   );
-  lsu_ecc ecc ( // @[lsu.scala 70:30]
+  lsu_ecc ecc ( // @[lsu.scala 75:30]
     .clock(ecc_clock),
     .reset(ecc_reset),
-    .io_lsu_c2_r_clk(ecc_io_lsu_c2_r_clk),
     .io_clk_override(ecc_io_clk_override),
-    .io_lsu_pkt_m_valid(ecc_io_lsu_pkt_m_valid),
-    .io_lsu_pkt_m_bits_load(ecc_io_lsu_pkt_m_bits_load),
-    .io_lsu_pkt_m_bits_store(ecc_io_lsu_pkt_m_bits_store),
-    .io_lsu_pkt_m_bits_dma(ecc_io_lsu_pkt_m_bits_dma),
+    .io_lsu_pkt_r_valid(ecc_io_lsu_pkt_r_valid),
+    .io_lsu_pkt_r_bits_load(ecc_io_lsu_pkt_r_bits_load),
+    .io_lsu_pkt_r_bits_store(ecc_io_lsu_pkt_r_bits_store),
     .io_stbuf_data_any(ecc_io_stbuf_data_any),
     .io_dec_tlu_core_ecc_disable(ecc_io_dec_tlu_core_ecc_disable),
-    .io_lsu_addr_m(ecc_io_lsu_addr_m),
-    .io_end_addr_m(ecc_io_end_addr_m),
-    .io_dccm_rdata_hi_m(ecc_io_dccm_rdata_hi_m),
-    .io_dccm_rdata_lo_m(ecc_io_dccm_rdata_lo_m),
-    .io_dccm_data_ecc_hi_m(ecc_io_dccm_data_ecc_hi_m),
-    .io_dccm_data_ecc_lo_m(ecc_io_dccm_data_ecc_lo_m),
+    .io_lsu_dccm_rden_r(ecc_io_lsu_dccm_rden_r),
+    .io_addr_in_dccm_r(ecc_io_addr_in_dccm_r),
+    .io_lsu_addr_r(ecc_io_lsu_addr_r),
+    .io_end_addr_r(ecc_io_end_addr_r),
+    .io_dccm_rdata_hi_r(ecc_io_dccm_rdata_hi_r),
+    .io_dccm_rdata_lo_r(ecc_io_dccm_rdata_lo_r),
+    .io_dccm_data_ecc_hi_r(ecc_io_dccm_data_ecc_hi_r),
+    .io_dccm_data_ecc_lo_r(ecc_io_dccm_data_ecc_lo_r),
     .io_ld_single_ecc_error_r(ecc_io_ld_single_ecc_error_r),
     .io_ld_single_ecc_error_r_ff(ecc_io_ld_single_ecc_error_r_ff),
-    .io_lsu_dccm_rden_m(ecc_io_lsu_dccm_rden_m),
-    .io_addr_in_dccm_m(ecc_io_addr_in_dccm_m),
     .io_dma_dccm_wen(ecc_io_dma_dccm_wen),
     .io_dma_dccm_wdata_lo(ecc_io_dma_dccm_wdata_lo),
     .io_dma_dccm_wdata_hi(ecc_io_dma_dccm_wdata_hi),
-    .io_scan_mode(ecc_io_scan_mode),
     .io_sec_data_hi_r(ecc_io_sec_data_hi_r),
     .io_sec_data_lo_r(ecc_io_sec_data_lo_r),
-    .io_sec_data_hi_m(ecc_io_sec_data_hi_m),
-    .io_sec_data_lo_m(ecc_io_sec_data_lo_m),
     .io_sec_data_hi_r_ff(ecc_io_sec_data_hi_r_ff),
     .io_sec_data_lo_r_ff(ecc_io_sec_data_lo_r_ff),
     .io_dma_dccm_wdata_ecc_hi(ecc_io_dma_dccm_wdata_ecc_hi),
@@ -11428,10 +10852,9 @@ module lsu(
     .io_single_ecc_error_lo_r(ecc_io_single_ecc_error_lo_r),
     .io_lsu_single_ecc_error_r(ecc_io_lsu_single_ecc_error_r),
     .io_lsu_double_ecc_error_r(ecc_io_lsu_double_ecc_error_r),
-    .io_lsu_single_ecc_error_m(ecc_io_lsu_single_ecc_error_m),
-    .io_lsu_double_ecc_error_m(ecc_io_lsu_double_ecc_error_m)
+    .io_lsu_single_ecc_error_m(ecc_io_lsu_single_ecc_error_m)
   );
-  lsu_trigger trigger ( // @[lsu.scala 71:30]
+  lsu_trigger trigger ( // @[lsu.scala 76:30]
     .io_trigger_pkt_any_0_select(trigger_io_trigger_pkt_any_0_select),
     .io_trigger_pkt_any_0_match_pkt(trigger_io_trigger_pkt_any_0_match_pkt),
     .io_trigger_pkt_any_0_store(trigger_io_trigger_pkt_any_0_store),
@@ -11466,7 +10889,7 @@ module lsu(
     .io_store_data_m(trigger_io_store_data_m),
     .io_lsu_trigger_match_m(trigger_io_lsu_trigger_match_m)
   );
-  lsu_clkdomain clkdomain ( // @[lsu.scala 72:30]
+  lsu_clkdomain clkdomain ( // @[lsu.scala 77:30]
     .clock(clkdomain_clock),
     .reset(clkdomain_reset),
     .io_active_clk(clkdomain_io_active_clk),
@@ -11496,17 +10919,13 @@ module lsu(
     .io_lsu_store_c1_m_clk(clkdomain_io_lsu_store_c1_m_clk),
     .io_lsu_store_c1_r_clk(clkdomain_io_lsu_store_c1_r_clk),
     .io_lsu_stbuf_c1_clk(clkdomain_io_lsu_stbuf_c1_clk),
-    .io_lsu_bus_obuf_c1_clk(clkdomain_io_lsu_bus_obuf_c1_clk),
     .io_lsu_bus_ibuf_c1_clk(clkdomain_io_lsu_bus_ibuf_c1_clk),
     .io_lsu_bus_buf_c1_clk(clkdomain_io_lsu_bus_buf_c1_clk),
-    .io_lsu_busm_clk(clkdomain_io_lsu_busm_clk),
-    .io_lsu_free_c2_clk(clkdomain_io_lsu_free_c2_clk),
-    .io_scan_mode(clkdomain_io_scan_mode)
+    .io_lsu_free_c2_clk(clkdomain_io_lsu_free_c2_clk)
   );
-  lsu_bus_intf bus_intf ( // @[lsu.scala 73:30]
+  lsu_bus_intf bus_intf ( // @[lsu.scala 78:30]
     .clock(bus_intf_clock),
     .reset(bus_intf_reset),
-    .io_scan_mode(bus_intf_io_scan_mode),
     .io_tlu_busbuff_lsu_pmu_bus_trxn(bus_intf_io_tlu_busbuff_lsu_pmu_bus_trxn),
     .io_tlu_busbuff_lsu_pmu_bus_misaligned(bus_intf_io_tlu_busbuff_lsu_pmu_bus_misaligned),
     .io_tlu_busbuff_lsu_pmu_bus_error(bus_intf_io_tlu_busbuff_lsu_pmu_bus_error),
@@ -11520,32 +10939,21 @@ module lsu(
     .io_lsu_c1_r_clk(bus_intf_io_lsu_c1_r_clk),
     .io_lsu_c2_r_clk(bus_intf_io_lsu_c2_r_clk),
     .io_lsu_bus_ibuf_c1_clk(bus_intf_io_lsu_bus_ibuf_c1_clk),
-    .io_lsu_bus_obuf_c1_clk(bus_intf_io_lsu_bus_obuf_c1_clk),
     .io_lsu_bus_buf_c1_clk(bus_intf_io_lsu_bus_buf_c1_clk),
     .io_lsu_free_c2_clk(bus_intf_io_lsu_free_c2_clk),
     .io_active_clk(bus_intf_io_active_clk),
-    .io_lsu_busm_clk(bus_intf_io_lsu_busm_clk),
     .io_axi_aw_ready(bus_intf_io_axi_aw_ready),
-    .io_axi_aw_valid(bus_intf_io_axi_aw_valid),
-    .io_axi_aw_bits_id(bus_intf_io_axi_aw_bits_id),
     .io_axi_aw_bits_addr(bus_intf_io_axi_aw_bits_addr),
     .io_axi_aw_bits_region(bus_intf_io_axi_aw_bits_region),
-    .io_axi_aw_bits_size(bus_intf_io_axi_aw_bits_size),
-    .io_axi_aw_bits_cache(bus_intf_io_axi_aw_bits_cache),
     .io_axi_w_ready(bus_intf_io_axi_w_ready),
-    .io_axi_w_valid(bus_intf_io_axi_w_valid),
     .io_axi_w_bits_data(bus_intf_io_axi_w_bits_data),
-    .io_axi_w_bits_strb(bus_intf_io_axi_w_bits_strb),
     .io_axi_b_valid(bus_intf_io_axi_b_valid),
     .io_axi_b_bits_resp(bus_intf_io_axi_b_bits_resp),
     .io_axi_b_bits_id(bus_intf_io_axi_b_bits_id),
     .io_axi_ar_ready(bus_intf_io_axi_ar_ready),
     .io_axi_ar_valid(bus_intf_io_axi_ar_valid),
-    .io_axi_ar_bits_id(bus_intf_io_axi_ar_bits_id),
     .io_axi_ar_bits_addr(bus_intf_io_axi_ar_bits_addr),
     .io_axi_ar_bits_region(bus_intf_io_axi_ar_bits_region),
-    .io_axi_ar_bits_size(bus_intf_io_axi_ar_bits_size),
-    .io_axi_ar_bits_cache(bus_intf_io_axi_ar_bits_cache),
     .io_axi_r_valid(bus_intf_io_axi_r_valid),
     .io_axi_r_bits_id(bus_intf_io_axi_r_bits_id),
     .io_axi_r_bits_data(bus_intf_io_axi_r_bits_data),
@@ -11592,367 +11000,354 @@ module lsu(
     .io_dctl_busbuff_lsu_nonblock_load_data(bus_intf_io_dctl_busbuff_lsu_nonblock_load_data),
     .io_lsu_bus_clk_en(bus_intf_io_lsu_bus_clk_en)
   );
-  assign io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid = dccm_ctl_io_dma_dccm_ctl_dccm_dma_rvalid; // @[lsu.scala 211:27]
-  assign io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error = dccm_ctl_io_dma_dccm_ctl_dccm_dma_ecc_error; // @[lsu.scala 211:27]
-  assign io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag = dccm_ctl_io_dma_dccm_ctl_dccm_dma_rtag; // @[lsu.scala 211:27]
-  assign io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata = dccm_ctl_io_dma_dccm_ctl_dccm_dma_rdata; // @[lsu.scala 211:27]
-  assign io_lsu_dma_dccm_ready = ~_T_8; // @[lsu.scala 87:25]
-  assign io_lsu_pic_picm_wren = dccm_ctl_io_lsu_pic_picm_wren; // @[lsu.scala 213:14]
-  assign io_lsu_pic_picm_rden = dccm_ctl_io_lsu_pic_picm_rden; // @[lsu.scala 213:14]
-  assign io_lsu_pic_picm_mken = dccm_ctl_io_lsu_pic_picm_mken; // @[lsu.scala 213:14]
-  assign io_lsu_pic_picm_rdaddr = dccm_ctl_io_lsu_pic_picm_rdaddr; // @[lsu.scala 213:14]
-  assign io_lsu_pic_picm_wraddr = dccm_ctl_io_lsu_pic_picm_wraddr; // @[lsu.scala 213:14]
-  assign io_lsu_pic_picm_wr_data = dccm_ctl_io_lsu_pic_picm_wr_data; // @[lsu.scala 213:14]
-  assign io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn = bus_intf_io_tlu_busbuff_lsu_pmu_bus_trxn; // @[lsu.scala 305:26]
-  assign io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned = bus_intf_io_tlu_busbuff_lsu_pmu_bus_misaligned; // @[lsu.scala 305:26]
-  assign io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error = bus_intf_io_tlu_busbuff_lsu_pmu_bus_error; // @[lsu.scala 305:26]
-  assign io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy = bus_intf_io_tlu_busbuff_lsu_pmu_bus_busy; // @[lsu.scala 305:26]
-  assign io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any = bus_intf_io_tlu_busbuff_lsu_imprecise_error_load_any; // @[lsu.scala 305:26]
-  assign io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any = bus_intf_io_tlu_busbuff_lsu_imprecise_error_store_any; // @[lsu.scala 305:26]
-  assign io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any = bus_intf_io_tlu_busbuff_lsu_imprecise_error_addr_any; // @[lsu.scala 305:26]
-  assign io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m = bus_intf_io_dctl_busbuff_lsu_nonblock_load_valid_m; // @[lsu.scala 335:27]
-  assign io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m = bus_intf_io_dctl_busbuff_lsu_nonblock_load_tag_m; // @[lsu.scala 335:27]
-  assign io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r = bus_intf_io_dctl_busbuff_lsu_nonblock_load_inv_r; // @[lsu.scala 335:27]
-  assign io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r = bus_intf_io_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[lsu.scala 335:27]
-  assign io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid = bus_intf_io_dctl_busbuff_lsu_nonblock_load_data_valid; // @[lsu.scala 335:27]
-  assign io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error = bus_intf_io_dctl_busbuff_lsu_nonblock_load_data_error; // @[lsu.scala 335:27]
-  assign io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag = bus_intf_io_dctl_busbuff_lsu_nonblock_load_data_tag; // @[lsu.scala 335:27]
-  assign io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data = bus_intf_io_dctl_busbuff_lsu_nonblock_load_data; // @[lsu.scala 335:27]
-  assign io_dccm_wren = dccm_ctl_io_dccm_wren; // @[lsu.scala 212:11]
-  assign io_dccm_rden = dccm_ctl_io_dccm_rden; // @[lsu.scala 212:11]
-  assign io_dccm_wr_addr_lo = dccm_ctl_io_dccm_wr_addr_lo; // @[lsu.scala 212:11]
-  assign io_dccm_wr_addr_hi = dccm_ctl_io_dccm_wr_addr_hi; // @[lsu.scala 212:11]
-  assign io_dccm_rd_addr_lo = dccm_ctl_io_dccm_rd_addr_lo; // @[lsu.scala 212:11]
-  assign io_dccm_rd_addr_hi = dccm_ctl_io_dccm_rd_addr_hi; // @[lsu.scala 212:11]
-  assign io_dccm_wr_data_lo = dccm_ctl_io_dccm_wr_data_lo; // @[lsu.scala 212:11]
-  assign io_dccm_wr_data_hi = dccm_ctl_io_dccm_wr_data_hi; // @[lsu.scala 212:11]
-  assign io_lsu_tlu_lsu_pmu_load_external_m = _T_63 & lsu_lsc_ctl_io_addr_external_m; // @[lsu.scala 115:39]
-  assign io_lsu_tlu_lsu_pmu_store_external_m = _T_65 & lsu_lsc_ctl_io_addr_external_m; // @[lsu.scala 116:39]
-  assign io_axi_aw_valid = bus_intf_io_axi_aw_valid; // @[lsu.scala 336:49]
-  assign io_axi_aw_bits_id = bus_intf_io_axi_aw_bits_id; // @[lsu.scala 336:49]
-  assign io_axi_aw_bits_addr = bus_intf_io_axi_aw_bits_addr; // @[lsu.scala 336:49]
-  assign io_axi_aw_bits_region = bus_intf_io_axi_aw_bits_region; // @[lsu.scala 336:49]
-  assign io_axi_aw_bits_len = 8'h0; // @[lsu.scala 336:49]
-  assign io_axi_aw_bits_size = bus_intf_io_axi_aw_bits_size; // @[lsu.scala 336:49]
-  assign io_axi_aw_bits_burst = 2'h1; // @[lsu.scala 336:49]
-  assign io_axi_aw_bits_lock = 1'h0; // @[lsu.scala 336:49]
-  assign io_axi_aw_bits_cache = bus_intf_io_axi_aw_bits_cache; // @[lsu.scala 336:49]
-  assign io_axi_aw_bits_prot = 3'h1; // @[lsu.scala 336:49]
-  assign io_axi_aw_bits_qos = 4'h0; // @[lsu.scala 336:49]
-  assign io_axi_w_valid = bus_intf_io_axi_w_valid; // @[lsu.scala 336:49]
-  assign io_axi_w_bits_data = bus_intf_io_axi_w_bits_data; // @[lsu.scala 336:49]
-  assign io_axi_w_bits_strb = bus_intf_io_axi_w_bits_strb; // @[lsu.scala 336:49]
-  assign io_axi_w_bits_last = 1'h1; // @[lsu.scala 336:49]
-  assign io_axi_b_ready = 1'h1; // @[lsu.scala 336:49]
-  assign io_axi_ar_valid = bus_intf_io_axi_ar_valid; // @[lsu.scala 336:49]
-  assign io_axi_ar_bits_id = bus_intf_io_axi_ar_bits_id; // @[lsu.scala 336:49]
-  assign io_axi_ar_bits_addr = bus_intf_io_axi_ar_bits_addr; // @[lsu.scala 336:49]
-  assign io_axi_ar_bits_region = bus_intf_io_axi_ar_bits_region; // @[lsu.scala 336:49]
-  assign io_axi_ar_bits_len = 8'h0; // @[lsu.scala 336:49]
-  assign io_axi_ar_bits_size = bus_intf_io_axi_ar_bits_size; // @[lsu.scala 336:49]
-  assign io_axi_ar_bits_burst = 2'h1; // @[lsu.scala 336:49]
-  assign io_axi_ar_bits_lock = 1'h0; // @[lsu.scala 336:49]
-  assign io_axi_ar_bits_cache = bus_intf_io_axi_ar_bits_cache; // @[lsu.scala 336:49]
-  assign io_axi_ar_bits_prot = 3'h1; // @[lsu.scala 336:49]
-  assign io_axi_ar_bits_qos = 4'h0; // @[lsu.scala 336:49]
-  assign io_axi_r_ready = 1'h1; // @[lsu.scala 336:49]
-  assign io_lsu_result_m = lsu_lsc_ctl_io_lsu_result_m; // @[lsu.scala 66:19]
-  assign io_lsu_result_corr_r = lsu_lsc_ctl_io_lsu_result_corr_r; // @[lsu.scala 67:24]
-  assign io_lsu_load_stall_any = bus_intf_io_lsu_bus_buffer_full_any | dccm_ctl_io_ld_single_ecc_error_r_ff; // @[lsu.scala 80:25]
-  assign io_lsu_store_stall_any = _T | dccm_ctl_io_ld_single_ecc_error_r_ff; // @[lsu.scala 79:26]
-  assign io_lsu_fastint_stall_any = dccm_ctl_io_ld_single_ecc_error_r; // @[lsu.scala 81:28]
-  assign io_lsu_idle_any = _T_24 & bus_intf_io_lsu_bus_buffer_empty_any; // @[lsu.scala 101:19]
-  assign io_lsu_active = _T_27 | _T_28; // @[lsu.scala 102:17]
-  assign io_lsu_fir_addr = lsu_lsc_ctl_io_lsu_fir_addr; // @[lsu.scala 151:49]
-  assign io_lsu_fir_error = lsu_lsc_ctl_io_lsu_fir_error; // @[lsu.scala 152:49]
-  assign io_lsu_single_ecc_error_incr = lsu_lsc_ctl_io_lsu_single_ecc_error_incr; // @[lsu.scala 149:49]
-  assign io_lsu_error_pkt_r_valid = lsu_lsc_ctl_io_lsu_error_pkt_r_valid; // @[lsu.scala 150:49]
-  assign io_lsu_error_pkt_r_bits_single_ecc_error = lsu_lsc_ctl_io_lsu_error_pkt_r_bits_single_ecc_error; // @[lsu.scala 150:49]
-  assign io_lsu_error_pkt_r_bits_inst_type = lsu_lsc_ctl_io_lsu_error_pkt_r_bits_inst_type; // @[lsu.scala 150:49]
-  assign io_lsu_error_pkt_r_bits_exc_type = lsu_lsc_ctl_io_lsu_error_pkt_r_bits_exc_type; // @[lsu.scala 150:49]
-  assign io_lsu_error_pkt_r_bits_mscause = lsu_lsc_ctl_io_lsu_error_pkt_r_bits_mscause; // @[lsu.scala 150:49]
-  assign io_lsu_error_pkt_r_bits_addr = lsu_lsc_ctl_io_lsu_error_pkt_r_bits_addr; // @[lsu.scala 150:49]
-  assign io_lsu_pmu_misaligned_m = lsu_lsc_ctl_io_lsu_pkt_m_valid & _T_61; // @[lsu.scala 114:27]
-  assign io_lsu_trigger_match_m = trigger_io_lsu_trigger_match_m; // @[lsu.scala 280:50]
+  assign io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid = dccm_ctl_io_dma_dccm_ctl_dccm_dma_rvalid; // @[lsu.scala 221:27]
+  assign io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error = dccm_ctl_io_dma_dccm_ctl_dccm_dma_ecc_error; // @[lsu.scala 221:27]
+  assign io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag = dccm_ctl_io_dma_dccm_ctl_dccm_dma_rtag; // @[lsu.scala 221:27]
+  assign io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata = dccm_ctl_io_dma_dccm_ctl_dccm_dma_rdata; // @[lsu.scala 221:27]
+  assign io_lsu_dma_dccm_ready = ~_T_8; // @[lsu.scala 92:25]
+  assign io_lsu_pic_picm_wren = dccm_ctl_io_lsu_pic_picm_wren; // @[lsu.scala 223:14]
+  assign io_lsu_pic_picm_rden = dccm_ctl_io_lsu_pic_picm_rden; // @[lsu.scala 223:14]
+  assign io_lsu_pic_picm_mken = dccm_ctl_io_lsu_pic_picm_mken; // @[lsu.scala 223:14]
+  assign io_lsu_pic_picm_rdaddr = dccm_ctl_io_lsu_pic_picm_rdaddr; // @[lsu.scala 223:14]
+  assign io_lsu_pic_picm_wraddr = dccm_ctl_io_lsu_pic_picm_wraddr; // @[lsu.scala 223:14]
+  assign io_lsu_pic_picm_wr_data = dccm_ctl_io_lsu_pic_picm_wr_data; // @[lsu.scala 223:14]
+  assign io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn = bus_intf_io_tlu_busbuff_lsu_pmu_bus_trxn; // @[lsu.scala 315:26]
+  assign io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned = bus_intf_io_tlu_busbuff_lsu_pmu_bus_misaligned; // @[lsu.scala 315:26]
+  assign io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error = bus_intf_io_tlu_busbuff_lsu_pmu_bus_error; // @[lsu.scala 315:26]
+  assign io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy = bus_intf_io_tlu_busbuff_lsu_pmu_bus_busy; // @[lsu.scala 315:26]
+  assign io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any = bus_intf_io_tlu_busbuff_lsu_imprecise_error_load_any; // @[lsu.scala 315:26]
+  assign io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any = bus_intf_io_tlu_busbuff_lsu_imprecise_error_store_any; // @[lsu.scala 315:26]
+  assign io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any = bus_intf_io_tlu_busbuff_lsu_imprecise_error_addr_any; // @[lsu.scala 315:26]
+  assign io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m = bus_intf_io_dctl_busbuff_lsu_nonblock_load_valid_m; // @[lsu.scala 345:27]
+  assign io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m = bus_intf_io_dctl_busbuff_lsu_nonblock_load_tag_m; // @[lsu.scala 345:27]
+  assign io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r = bus_intf_io_dctl_busbuff_lsu_nonblock_load_inv_r; // @[lsu.scala 345:27]
+  assign io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r = bus_intf_io_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[lsu.scala 345:27]
+  assign io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid = bus_intf_io_dctl_busbuff_lsu_nonblock_load_data_valid; // @[lsu.scala 345:27]
+  assign io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error = bus_intf_io_dctl_busbuff_lsu_nonblock_load_data_error; // @[lsu.scala 345:27]
+  assign io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag = bus_intf_io_dctl_busbuff_lsu_nonblock_load_data_tag; // @[lsu.scala 345:27]
+  assign io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data = bus_intf_io_dctl_busbuff_lsu_nonblock_load_data; // @[lsu.scala 345:27]
+  assign io_dccm_wren = dccm_ctl_io_dccm_wren; // @[lsu.scala 222:11]
+  assign io_dccm_rden = dccm_ctl_io_dccm_rden; // @[lsu.scala 222:11]
+  assign io_dccm_wr_addr_lo = dccm_ctl_io_dccm_wr_addr_lo; // @[lsu.scala 222:11]
+  assign io_dccm_wr_addr_hi = dccm_ctl_io_dccm_wr_addr_hi; // @[lsu.scala 222:11]
+  assign io_dccm_rd_addr_lo = dccm_ctl_io_dccm_rd_addr_lo; // @[lsu.scala 222:11]
+  assign io_dccm_rd_addr_hi = dccm_ctl_io_dccm_rd_addr_hi; // @[lsu.scala 222:11]
+  assign io_dccm_wr_data_lo = dccm_ctl_io_dccm_wr_data_lo; // @[lsu.scala 222:11]
+  assign io_dccm_wr_data_hi = dccm_ctl_io_dccm_wr_data_hi; // @[lsu.scala 222:11]
+  assign io_lsu_tlu_lsu_pmu_load_external_m = _T_63 & lsu_lsc_ctl_io_addr_external_m; // @[lsu.scala 120:39]
+  assign io_lsu_tlu_lsu_pmu_store_external_m = _T_65 & lsu_lsc_ctl_io_addr_external_m; // @[lsu.scala 121:39]
+  assign io_axi_aw_valid = 1'h0; // @[lsu.scala 347:49]
+  assign io_axi_aw_bits_id = 3'h0; // @[lsu.scala 347:49]
+  assign io_axi_aw_bits_addr = bus_intf_io_axi_aw_bits_addr; // @[lsu.scala 347:49]
+  assign io_axi_aw_bits_region = bus_intf_io_axi_aw_bits_region; // @[lsu.scala 347:49]
+  assign io_axi_aw_bits_len = 8'h0; // @[lsu.scala 347:49]
+  assign io_axi_aw_bits_size = 3'h3; // @[lsu.scala 347:49]
+  assign io_axi_aw_bits_burst = 2'h1; // @[lsu.scala 347:49]
+  assign io_axi_aw_bits_lock = 1'h0; // @[lsu.scala 347:49]
+  assign io_axi_aw_bits_cache = 4'hf; // @[lsu.scala 347:49]
+  assign io_axi_aw_bits_prot = 3'h1; // @[lsu.scala 347:49]
+  assign io_axi_aw_bits_qos = 4'h0; // @[lsu.scala 347:49]
+  assign io_axi_w_valid = 1'h0; // @[lsu.scala 347:49]
+  assign io_axi_w_bits_data = bus_intf_io_axi_w_bits_data; // @[lsu.scala 347:49]
+  assign io_axi_w_bits_strb = 8'h0; // @[lsu.scala 347:49]
+  assign io_axi_w_bits_last = 1'h1; // @[lsu.scala 347:49]
+  assign io_axi_b_ready = 1'h1; // @[lsu.scala 347:49]
+  assign io_axi_ar_valid = bus_intf_io_axi_ar_valid; // @[lsu.scala 347:49]
+  assign io_axi_ar_bits_id = 3'h0; // @[lsu.scala 347:49]
+  assign io_axi_ar_bits_addr = bus_intf_io_axi_ar_bits_addr; // @[lsu.scala 347:49]
+  assign io_axi_ar_bits_region = bus_intf_io_axi_ar_bits_region; // @[lsu.scala 347:49]
+  assign io_axi_ar_bits_len = 8'h0; // @[lsu.scala 347:49]
+  assign io_axi_ar_bits_size = 3'h3; // @[lsu.scala 347:49]
+  assign io_axi_ar_bits_burst = 2'h1; // @[lsu.scala 347:49]
+  assign io_axi_ar_bits_lock = 1'h0; // @[lsu.scala 347:49]
+  assign io_axi_ar_bits_cache = 4'hf; // @[lsu.scala 347:49]
+  assign io_axi_ar_bits_prot = 3'h1; // @[lsu.scala 347:49]
+  assign io_axi_ar_bits_qos = 4'h0; // @[lsu.scala 347:49]
+  assign io_axi_r_ready = 1'h1; // @[lsu.scala 347:49]
+  assign io_lsu_result_m = lsu_lsc_ctl_io_lsu_result_m; // @[lsu.scala 71:19]
+  assign io_lsu_result_corr_r = lsu_lsc_ctl_io_lsu_result_corr_r; // @[lsu.scala 72:24]
+  assign io_lsu_load_stall_any = bus_intf_io_lsu_bus_buffer_full_any | dccm_ctl_io_ld_single_ecc_error_r_ff; // @[lsu.scala 85:25]
+  assign io_lsu_store_stall_any = _T | dccm_ctl_io_ld_single_ecc_error_r_ff; // @[lsu.scala 84:26]
+  assign io_lsu_fastint_stall_any = dccm_ctl_io_ld_single_ecc_error_r; // @[lsu.scala 86:28]
+  assign io_lsu_idle_any = _T_24 & bus_intf_io_lsu_bus_buffer_empty_any; // @[lsu.scala 106:19]
+  assign io_lsu_active = _T_27 | _T_28; // @[lsu.scala 107:17]
+  assign io_lsu_fir_addr = lsu_lsc_ctl_io_lsu_fir_addr; // @[lsu.scala 161:49]
+  assign io_lsu_fir_error = lsu_lsc_ctl_io_lsu_fir_error; // @[lsu.scala 162:49]
+  assign io_lsu_single_ecc_error_incr = lsu_lsc_ctl_io_lsu_single_ecc_error_incr; // @[lsu.scala 159:49]
+  assign io_lsu_error_pkt_r_valid = lsu_lsc_ctl_io_lsu_error_pkt_r_valid; // @[lsu.scala 160:49]
+  assign io_lsu_error_pkt_r_bits_single_ecc_error = lsu_lsc_ctl_io_lsu_error_pkt_r_bits_single_ecc_error; // @[lsu.scala 160:49]
+  assign io_lsu_error_pkt_r_bits_inst_type = lsu_lsc_ctl_io_lsu_error_pkt_r_bits_inst_type; // @[lsu.scala 160:49]
+  assign io_lsu_error_pkt_r_bits_exc_type = lsu_lsc_ctl_io_lsu_error_pkt_r_bits_exc_type; // @[lsu.scala 160:49]
+  assign io_lsu_error_pkt_r_bits_mscause = lsu_lsc_ctl_io_lsu_error_pkt_r_bits_mscause; // @[lsu.scala 160:49]
+  assign io_lsu_error_pkt_r_bits_addr = lsu_lsc_ctl_io_lsu_error_pkt_r_bits_addr; // @[lsu.scala 160:49]
+  assign io_lsu_pmu_misaligned_m = lsu_lsc_ctl_io_lsu_pkt_m_valid & _T_61; // @[lsu.scala 119:27]
+  assign io_lsu_trigger_match_m = trigger_io_lsu_trigger_match_m; // @[lsu.scala 290:50]
   assign lsu_lsc_ctl_clock = clock;
   assign lsu_lsc_ctl_reset = reset;
-  assign lsu_lsc_ctl_io_clk_override = io_clk_override; // @[lsu.scala 120:46]
-  assign lsu_lsc_ctl_io_lsu_c1_m_clk = clkdomain_io_lsu_c1_m_clk; // @[lsu.scala 121:46]
-  assign lsu_lsc_ctl_io_lsu_c1_r_clk = clkdomain_io_lsu_c1_r_clk; // @[lsu.scala 122:46]
-  assign lsu_lsc_ctl_io_lsu_c2_m_clk = clkdomain_io_lsu_c2_m_clk; // @[lsu.scala 123:46]
-  assign lsu_lsc_ctl_io_lsu_c2_r_clk = clkdomain_io_lsu_c2_r_clk; // @[lsu.scala 124:46]
-  assign lsu_lsc_ctl_io_lsu_store_c1_m_clk = clkdomain_io_lsu_store_c1_m_clk; // @[lsu.scala 125:46]
-  assign lsu_lsc_ctl_io_lsu_ld_data_corr_r = dccm_ctl_io_lsu_ld_data_corr_r; // @[lsu.scala 127:46]
-  assign lsu_lsc_ctl_io_lsu_single_ecc_error_r = ecc_io_lsu_single_ecc_error_r; // @[lsu.scala 128:46]
-  assign lsu_lsc_ctl_io_lsu_double_ecc_error_r = ecc_io_lsu_double_ecc_error_r; // @[lsu.scala 129:46]
-  assign lsu_lsc_ctl_io_lsu_ld_data_m = dccm_ctl_io_lsu_ld_data_m; // @[lsu.scala 130:46]
-  assign lsu_lsc_ctl_io_lsu_single_ecc_error_m = ecc_io_lsu_single_ecc_error_m; // @[lsu.scala 131:46]
-  assign lsu_lsc_ctl_io_lsu_double_ecc_error_m = ecc_io_lsu_double_ecc_error_m; // @[lsu.scala 132:46]
-  assign lsu_lsc_ctl_io_flush_m_up = io_dec_tlu_flush_lower_r; // @[lsu.scala 133:46]
-  assign lsu_lsc_ctl_io_flush_r = io_dec_tlu_i0_kill_writeb_r; // @[lsu.scala 134:46]
-  assign lsu_lsc_ctl_io_ldst_dual_d = lsu_lsc_ctl_io_lsu_addr_d[2] != lsu_lsc_ctl_io_end_addr_d[2]; // @[lsu.scala 135:46]
-  assign lsu_lsc_ctl_io_ldst_dual_m = lsu_lsc_ctl_io_lsu_addr_m[2] != lsu_lsc_ctl_io_end_addr_m[2]; // @[lsu.scala 136:46]
-  assign lsu_lsc_ctl_io_lsu_exu_exu_lsu_rs1_d = io_lsu_exu_exu_lsu_rs1_d; // @[lsu.scala 138:46]
-  assign lsu_lsc_ctl_io_lsu_exu_exu_lsu_rs2_d = io_lsu_exu_exu_lsu_rs2_d; // @[lsu.scala 138:46]
-  assign lsu_lsc_ctl_io_lsu_p_valid = io_lsu_p_valid; // @[lsu.scala 139:46]
-  assign lsu_lsc_ctl_io_lsu_p_bits_fast_int = io_lsu_p_bits_fast_int; // @[lsu.scala 139:46]
-  assign lsu_lsc_ctl_io_lsu_p_bits_by = io_lsu_p_bits_by; // @[lsu.scala 139:46]
-  assign lsu_lsc_ctl_io_lsu_p_bits_half = io_lsu_p_bits_half; // @[lsu.scala 139:46]
-  assign lsu_lsc_ctl_io_lsu_p_bits_word = io_lsu_p_bits_word; // @[lsu.scala 139:46]
-  assign lsu_lsc_ctl_io_lsu_p_bits_dword = io_lsu_p_bits_dword; // @[lsu.scala 139:46]
-  assign lsu_lsc_ctl_io_lsu_p_bits_load = io_lsu_p_bits_load; // @[lsu.scala 139:46]
-  assign lsu_lsc_ctl_io_lsu_p_bits_store = io_lsu_p_bits_store; // @[lsu.scala 139:46]
-  assign lsu_lsc_ctl_io_lsu_p_bits_unsign = io_lsu_p_bits_unsign; // @[lsu.scala 139:46]
-  assign lsu_lsc_ctl_io_lsu_p_bits_dma = io_lsu_p_bits_dma; // @[lsu.scala 139:46]
-  assign lsu_lsc_ctl_io_lsu_p_bits_store_data_bypass_d = io_lsu_p_bits_store_data_bypass_d; // @[lsu.scala 139:46]
-  assign lsu_lsc_ctl_io_lsu_p_bits_load_ldst_bypass_d = io_lsu_p_bits_load_ldst_bypass_d; // @[lsu.scala 139:46]
-  assign lsu_lsc_ctl_io_lsu_p_bits_store_data_bypass_m = io_lsu_p_bits_store_data_bypass_m; // @[lsu.scala 139:46]
-  assign lsu_lsc_ctl_io_dec_lsu_valid_raw_d = io_dec_lsu_valid_raw_d; // @[lsu.scala 140:46]
-  assign lsu_lsc_ctl_io_dec_lsu_offset_d = io_dec_lsu_offset_d; // @[lsu.scala 141:46]
-  assign lsu_lsc_ctl_io_picm_mask_data_m = dccm_ctl_io_picm_mask_data_m; // @[lsu.scala 142:46]
-  assign lsu_lsc_ctl_io_bus_read_data_m = bus_intf_io_bus_read_data_m; // @[lsu.scala 143:46]
-  assign lsu_lsc_ctl_io_dec_tlu_mrac_ff = io_dec_tlu_mrac_ff; // @[lsu.scala 145:46]
-  assign lsu_lsc_ctl_io_dma_lsc_ctl_dma_dccm_req = io_lsu_dma_dma_lsc_ctl_dma_dccm_req; // @[lsu.scala 144:38]
-  assign lsu_lsc_ctl_io_dma_lsc_ctl_dma_mem_addr = io_lsu_dma_dma_lsc_ctl_dma_mem_addr; // @[lsu.scala 144:38]
-  assign lsu_lsc_ctl_io_dma_lsc_ctl_dma_mem_sz = io_lsu_dma_dma_lsc_ctl_dma_mem_sz; // @[lsu.scala 144:38]
-  assign lsu_lsc_ctl_io_dma_lsc_ctl_dma_mem_write = io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[lsu.scala 144:38]
-  assign lsu_lsc_ctl_io_dma_lsc_ctl_dma_mem_wdata = io_lsu_dma_dma_lsc_ctl_dma_mem_wdata; // @[lsu.scala 144:38]
-  assign lsu_lsc_ctl_io_scan_mode = io_scan_mode; // @[lsu.scala 146:46]
+  assign lsu_lsc_ctl_io_clk_override = io_clk_override; // @[lsu.scala 125:46]
+  assign lsu_lsc_ctl_io_lsu_c1_m_clk = clkdomain_io_lsu_c1_m_clk; // @[lsu.scala 126:46]
+  assign lsu_lsc_ctl_io_lsu_c1_r_clk = clkdomain_io_lsu_c1_r_clk; // @[lsu.scala 127:46]
+  assign lsu_lsc_ctl_io_lsu_c2_m_clk = clkdomain_io_lsu_c2_m_clk; // @[lsu.scala 128:46]
+  assign lsu_lsc_ctl_io_lsu_c2_r_clk = clkdomain_io_lsu_c2_r_clk; // @[lsu.scala 129:46]
+  assign lsu_lsc_ctl_io_lsu_store_c1_m_clk = clkdomain_io_lsu_store_c1_m_clk; // @[lsu.scala 130:46]
+  assign lsu_lsc_ctl_io_lsu_ld_data_r = dccm_ctl_io_lsu_ld_data_r; // @[lsu.scala 131:46]
+  assign lsu_lsc_ctl_io_lsu_ld_data_corr_r = dccm_ctl_io_lsu_ld_data_corr_r; // @[lsu.scala 132:46]
+  assign lsu_lsc_ctl_io_lsu_single_ecc_error_r = ecc_io_lsu_single_ecc_error_r; // @[lsu.scala 133:46]
+  assign lsu_lsc_ctl_io_lsu_double_ecc_error_r = ecc_io_lsu_double_ecc_error_r; // @[lsu.scala 134:46]
+  assign lsu_lsc_ctl_io_flush_m_up = io_dec_tlu_flush_lower_r; // @[lsu.scala 138:46]
+  assign lsu_lsc_ctl_io_flush_r = io_dec_tlu_i0_kill_writeb_r; // @[lsu.scala 139:46]
+  assign lsu_lsc_ctl_io_ldst_dual_d = lsu_addr_d[2] != lsu_addr_d[2]; // @[lsu.scala 140:46]
+  assign lsu_lsc_ctl_io_ldst_dual_m = lsu_addr_m[2] != lsu_addr_m[2]; // @[lsu.scala 141:46]
+  assign lsu_lsc_ctl_io_ldst_dual_r = lsu_addr_r[2] != lsu_addr_r[2]; // @[lsu.scala 142:46]
+  assign lsu_lsc_ctl_io_lsu_exu_exu_lsu_rs1_d = io_lsu_exu_exu_lsu_rs1_d; // @[lsu.scala 143:46]
+  assign lsu_lsc_ctl_io_lsu_exu_exu_lsu_rs2_d = io_lsu_exu_exu_lsu_rs2_d; // @[lsu.scala 143:46]
+  assign lsu_lsc_ctl_io_lsu_p_valid = io_lsu_p_valid; // @[lsu.scala 144:46]
+  assign lsu_lsc_ctl_io_lsu_p_bits_fast_int = io_lsu_p_bits_fast_int; // @[lsu.scala 144:46]
+  assign lsu_lsc_ctl_io_lsu_p_bits_by = io_lsu_p_bits_by; // @[lsu.scala 144:46]
+  assign lsu_lsc_ctl_io_lsu_p_bits_half = io_lsu_p_bits_half; // @[lsu.scala 144:46]
+  assign lsu_lsc_ctl_io_lsu_p_bits_word = io_lsu_p_bits_word; // @[lsu.scala 144:46]
+  assign lsu_lsc_ctl_io_lsu_p_bits_dword = io_lsu_p_bits_dword; // @[lsu.scala 144:46]
+  assign lsu_lsc_ctl_io_lsu_p_bits_load = io_lsu_p_bits_load; // @[lsu.scala 144:46]
+  assign lsu_lsc_ctl_io_lsu_p_bits_store = io_lsu_p_bits_store; // @[lsu.scala 144:46]
+  assign lsu_lsc_ctl_io_lsu_p_bits_unsign = io_lsu_p_bits_unsign; // @[lsu.scala 144:46]
+  assign lsu_lsc_ctl_io_lsu_p_bits_dma = io_lsu_p_bits_dma; // @[lsu.scala 144:46]
+  assign lsu_lsc_ctl_io_lsu_p_bits_store_data_bypass_d = io_lsu_p_bits_store_data_bypass_d; // @[lsu.scala 144:46]
+  assign lsu_lsc_ctl_io_lsu_p_bits_load_ldst_bypass_d = io_lsu_p_bits_load_ldst_bypass_d; // @[lsu.scala 144:46]
+  assign lsu_lsc_ctl_io_lsu_p_bits_store_data_bypass_m = io_lsu_p_bits_store_data_bypass_m; // @[lsu.scala 144:46]
+  assign lsu_lsc_ctl_io_dec_lsu_valid_raw_d = io_dec_lsu_valid_raw_d; // @[lsu.scala 145:46]
+  assign lsu_lsc_ctl_io_dec_lsu_offset_d = io_dec_lsu_offset_d; // @[lsu.scala 146:46]
+  assign lsu_lsc_ctl_io_picm_mask_data_m = dccm_ctl_io_picm_mask_data_m; // @[lsu.scala 147:46]
+  assign lsu_lsc_ctl_io_bus_read_data_m = bus_intf_io_bus_read_data_m; // @[lsu.scala 148:46]
+  assign lsu_lsc_ctl_io_dec_tlu_mrac_ff = io_dec_tlu_mrac_ff; // @[lsu.scala 150:46]
+  assign lsu_lsc_ctl_io_dma_lsc_ctl_dma_dccm_req = io_lsu_dma_dma_lsc_ctl_dma_dccm_req; // @[lsu.scala 149:46]
+  assign lsu_lsc_ctl_io_dma_lsc_ctl_dma_mem_addr = io_lsu_dma_dma_lsc_ctl_dma_mem_addr; // @[lsu.scala 149:46]
+  assign lsu_lsc_ctl_io_dma_lsc_ctl_dma_mem_sz = io_lsu_dma_dma_lsc_ctl_dma_mem_sz; // @[lsu.scala 149:46]
+  assign lsu_lsc_ctl_io_dma_lsc_ctl_dma_mem_write = io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[lsu.scala 149:46]
+  assign lsu_lsc_ctl_io_dma_lsc_ctl_dma_mem_wdata = io_lsu_dma_dma_lsc_ctl_dma_mem_wdata; // @[lsu.scala 149:46]
   assign dccm_ctl_clock = clock;
   assign dccm_ctl_reset = reset;
-  assign dccm_ctl_io_clk_override = io_clk_override; // @[lsu.scala 155:46]
-  assign dccm_ctl_io_lsu_c2_m_clk = clkdomain_io_lsu_c2_m_clk; // @[lsu.scala 158:46]
-  assign dccm_ctl_io_lsu_free_c2_clk = clkdomain_io_lsu_free_c2_clk; // @[lsu.scala 160:46]
-  assign dccm_ctl_io_lsu_store_c1_r_clk = clkdomain_io_lsu_store_c1_r_clk; // @[lsu.scala 162:46]
-  assign dccm_ctl_io_lsu_pkt_d_valid = lsu_lsc_ctl_io_lsu_pkt_d_valid; // @[lsu.scala 163:46]
-  assign dccm_ctl_io_lsu_pkt_d_bits_word = lsu_lsc_ctl_io_lsu_pkt_d_bits_word; // @[lsu.scala 163:46]
-  assign dccm_ctl_io_lsu_pkt_d_bits_dword = lsu_lsc_ctl_io_lsu_pkt_d_bits_dword; // @[lsu.scala 163:46]
-  assign dccm_ctl_io_lsu_pkt_d_bits_load = lsu_lsc_ctl_io_lsu_pkt_d_bits_load; // @[lsu.scala 163:46]
-  assign dccm_ctl_io_lsu_pkt_d_bits_store = lsu_lsc_ctl_io_lsu_pkt_d_bits_store; // @[lsu.scala 163:46]
-  assign dccm_ctl_io_lsu_pkt_d_bits_dma = lsu_lsc_ctl_io_lsu_pkt_d_bits_dma; // @[lsu.scala 163:46]
-  assign dccm_ctl_io_lsu_pkt_m_valid = lsu_lsc_ctl_io_lsu_pkt_m_valid; // @[lsu.scala 164:46]
-  assign dccm_ctl_io_lsu_pkt_m_bits_by = lsu_lsc_ctl_io_lsu_pkt_m_bits_by; // @[lsu.scala 164:46]
-  assign dccm_ctl_io_lsu_pkt_m_bits_half = lsu_lsc_ctl_io_lsu_pkt_m_bits_half; // @[lsu.scala 164:46]
-  assign dccm_ctl_io_lsu_pkt_m_bits_word = lsu_lsc_ctl_io_lsu_pkt_m_bits_word; // @[lsu.scala 164:46]
-  assign dccm_ctl_io_lsu_pkt_m_bits_load = lsu_lsc_ctl_io_lsu_pkt_m_bits_load; // @[lsu.scala 164:46]
-  assign dccm_ctl_io_lsu_pkt_m_bits_store = lsu_lsc_ctl_io_lsu_pkt_m_bits_store; // @[lsu.scala 164:46]
-  assign dccm_ctl_io_lsu_pkt_m_bits_dma = lsu_lsc_ctl_io_lsu_pkt_m_bits_dma; // @[lsu.scala 164:46]
-  assign dccm_ctl_io_lsu_pkt_r_valid = lsu_lsc_ctl_io_lsu_pkt_r_valid; // @[lsu.scala 165:46]
-  assign dccm_ctl_io_lsu_pkt_r_bits_by = lsu_lsc_ctl_io_lsu_pkt_r_bits_by; // @[lsu.scala 165:46]
-  assign dccm_ctl_io_lsu_pkt_r_bits_half = lsu_lsc_ctl_io_lsu_pkt_r_bits_half; // @[lsu.scala 165:46]
-  assign dccm_ctl_io_lsu_pkt_r_bits_word = lsu_lsc_ctl_io_lsu_pkt_r_bits_word; // @[lsu.scala 165:46]
-  assign dccm_ctl_io_lsu_pkt_r_bits_load = lsu_lsc_ctl_io_lsu_pkt_r_bits_load; // @[lsu.scala 165:46]
-  assign dccm_ctl_io_lsu_pkt_r_bits_store = lsu_lsc_ctl_io_lsu_pkt_r_bits_store; // @[lsu.scala 165:46]
-  assign dccm_ctl_io_lsu_pkt_r_bits_dma = lsu_lsc_ctl_io_lsu_pkt_r_bits_dma; // @[lsu.scala 165:46]
-  assign dccm_ctl_io_addr_in_dccm_d = lsu_lsc_ctl_io_addr_in_dccm_d; // @[lsu.scala 166:46]
-  assign dccm_ctl_io_addr_in_dccm_m = lsu_lsc_ctl_io_addr_in_dccm_m; // @[lsu.scala 167:46]
-  assign dccm_ctl_io_addr_in_dccm_r = lsu_lsc_ctl_io_addr_in_dccm_r; // @[lsu.scala 168:46]
-  assign dccm_ctl_io_addr_in_pic_d = lsu_lsc_ctl_io_addr_in_pic_d; // @[lsu.scala 169:46]
-  assign dccm_ctl_io_addr_in_pic_m = lsu_lsc_ctl_io_addr_in_pic_m; // @[lsu.scala 170:46]
-  assign dccm_ctl_io_addr_in_pic_r = lsu_lsc_ctl_io_addr_in_pic_r; // @[lsu.scala 171:46]
-  assign dccm_ctl_io_lsu_raw_fwd_lo_r = lsu_raw_fwd_lo_r; // @[lsu.scala 172:46]
-  assign dccm_ctl_io_lsu_raw_fwd_hi_r = lsu_raw_fwd_hi_r; // @[lsu.scala 173:46]
-  assign dccm_ctl_io_lsu_commit_r = lsu_lsc_ctl_io_lsu_commit_r; // @[lsu.scala 174:46]
-  assign dccm_ctl_io_ldst_dual_m = lsu_lsc_ctl_io_lsu_addr_m[2] != lsu_lsc_ctl_io_end_addr_m[2]; // @[lsu.scala 156:46]
-  assign dccm_ctl_io_lsu_addr_d = lsu_lsc_ctl_io_lsu_addr_d; // @[lsu.scala 175:46]
-  assign dccm_ctl_io_lsu_addr_m = lsu_lsc_ctl_io_lsu_addr_m[15:0]; // @[lsu.scala 176:46]
-  assign dccm_ctl_io_lsu_addr_r = lsu_lsc_ctl_io_lsu_addr_r; // @[lsu.scala 177:46]
-  assign dccm_ctl_io_end_addr_d = lsu_lsc_ctl_io_end_addr_d[15:0]; // @[lsu.scala 178:46]
-  assign dccm_ctl_io_end_addr_m = lsu_lsc_ctl_io_end_addr_m[15:0]; // @[lsu.scala 179:46]
-  assign dccm_ctl_io_end_addr_r = lsu_lsc_ctl_io_end_addr_r[15:0]; // @[lsu.scala 180:46]
-  assign dccm_ctl_io_stbuf_reqvld_any = stbuf_io_stbuf_reqvld_any; // @[lsu.scala 181:46]
-  assign dccm_ctl_io_stbuf_addr_any = stbuf_io_stbuf_addr_any; // @[lsu.scala 182:46]
-  assign dccm_ctl_io_stbuf_data_any = stbuf_io_stbuf_data_any; // @[lsu.scala 183:46]
-  assign dccm_ctl_io_stbuf_ecc_any = ecc_io_stbuf_ecc_any; // @[lsu.scala 184:46]
-  assign dccm_ctl_io_stbuf_fwddata_hi_m = stbuf_io_stbuf_fwddata_hi_m; // @[lsu.scala 185:46]
-  assign dccm_ctl_io_stbuf_fwddata_lo_m = stbuf_io_stbuf_fwddata_lo_m; // @[lsu.scala 186:46]
-  assign dccm_ctl_io_stbuf_fwdbyteen_lo_m = stbuf_io_stbuf_fwdbyteen_lo_m; // @[lsu.scala 187:46]
-  assign dccm_ctl_io_stbuf_fwdbyteen_hi_m = stbuf_io_stbuf_fwdbyteen_hi_m; // @[lsu.scala 188:46]
-  assign dccm_ctl_io_lsu_double_ecc_error_r = ecc_io_lsu_double_ecc_error_r; // @[lsu.scala 189:46]
-  assign dccm_ctl_io_single_ecc_error_hi_r = ecc_io_single_ecc_error_hi_r; // @[lsu.scala 190:46]
-  assign dccm_ctl_io_single_ecc_error_lo_r = ecc_io_single_ecc_error_lo_r; // @[lsu.scala 191:46]
-  assign dccm_ctl_io_sec_data_hi_r_ff = ecc_io_sec_data_hi_r_ff; // @[lsu.scala 194:46]
-  assign dccm_ctl_io_sec_data_lo_r_ff = ecc_io_sec_data_lo_r_ff; // @[lsu.scala 195:46]
-  assign dccm_ctl_io_sec_data_ecc_hi_r_ff = ecc_io_sec_data_ecc_hi_r_ff; // @[lsu.scala 196:46]
-  assign dccm_ctl_io_sec_data_ecc_lo_r_ff = ecc_io_sec_data_ecc_lo_r_ff; // @[lsu.scala 197:46]
-  assign dccm_ctl_io_lsu_double_ecc_error_m = ecc_io_lsu_double_ecc_error_m; // @[lsu.scala 198:46]
-  assign dccm_ctl_io_sec_data_hi_m = ecc_io_sec_data_hi_m; // @[lsu.scala 199:46]
-  assign dccm_ctl_io_sec_data_lo_m = ecc_io_sec_data_lo_m; // @[lsu.scala 200:46]
-  assign dccm_ctl_io_store_data_m = lsu_lsc_ctl_io_store_data_m; // @[lsu.scala 201:46]
-  assign dccm_ctl_io_dma_dccm_wen = _T_11 & io_lsu_dma_dma_lsc_ctl_dma_mem_sz[1]; // @[lsu.scala 202:46]
-  assign dccm_ctl_io_dma_pic_wen = _T_10 & lsu_lsc_ctl_io_addr_in_pic_d; // @[lsu.scala 203:46]
-  assign dccm_ctl_io_dma_mem_tag_m = dma_mem_tag_m; // @[lsu.scala 204:46]
-  assign dccm_ctl_io_dma_dccm_wdata_lo = dma_dccm_wdata[31:0]; // @[lsu.scala 205:46]
-  assign dccm_ctl_io_dma_dccm_wdata_hi = dma_dccm_wdata[63:32]; // @[lsu.scala 206:46]
-  assign dccm_ctl_io_dma_dccm_wdata_ecc_hi = ecc_io_dma_dccm_wdata_ecc_hi; // @[lsu.scala 207:46]
-  assign dccm_ctl_io_dma_dccm_wdata_ecc_lo = ecc_io_dma_dccm_wdata_ecc_lo; // @[lsu.scala 208:46]
-  assign dccm_ctl_io_dma_dccm_ctl_dma_mem_addr = io_lsu_dma_dma_dccm_ctl_dma_mem_addr; // @[lsu.scala 211:27]
-  assign dccm_ctl_io_dma_dccm_ctl_dma_mem_wdata = io_lsu_dma_dma_dccm_ctl_dma_mem_wdata; // @[lsu.scala 211:27]
-  assign dccm_ctl_io_dccm_rd_data_lo = io_dccm_rd_data_lo; // @[lsu.scala 212:11]
-  assign dccm_ctl_io_dccm_rd_data_hi = io_dccm_rd_data_hi; // @[lsu.scala 212:11]
-  assign dccm_ctl_io_lsu_pic_picm_rd_data = io_lsu_pic_picm_rd_data; // @[lsu.scala 213:14]
-  assign dccm_ctl_io_scan_mode = io_scan_mode; // @[lsu.scala 209:46]
+  assign dccm_ctl_io_clk_override = io_clk_override; // @[lsu.scala 165:46]
+  assign dccm_ctl_io_lsu_c2_m_clk = clkdomain_io_lsu_c2_m_clk; // @[lsu.scala 168:46]
+  assign dccm_ctl_io_lsu_c2_r_clk = clkdomain_io_lsu_c2_r_clk; // @[lsu.scala 169:46]
+  assign dccm_ctl_io_lsu_free_c2_clk = clkdomain_io_lsu_free_c2_clk; // @[lsu.scala 170:46]
+  assign dccm_ctl_io_lsu_c1_r_clk = clkdomain_io_lsu_c1_r_clk; // @[lsu.scala 171:46]
+  assign dccm_ctl_io_lsu_store_c1_r_clk = clkdomain_io_lsu_store_c1_r_clk; // @[lsu.scala 172:46]
+  assign dccm_ctl_io_lsu_pkt_d_valid = lsu_lsc_ctl_io_lsu_pkt_d_valid; // @[lsu.scala 173:46]
+  assign dccm_ctl_io_lsu_pkt_d_bits_word = lsu_lsc_ctl_io_lsu_pkt_d_bits_word; // @[lsu.scala 173:46]
+  assign dccm_ctl_io_lsu_pkt_d_bits_dword = lsu_lsc_ctl_io_lsu_pkt_d_bits_dword; // @[lsu.scala 173:46]
+  assign dccm_ctl_io_lsu_pkt_d_bits_load = lsu_lsc_ctl_io_lsu_pkt_d_bits_load; // @[lsu.scala 173:46]
+  assign dccm_ctl_io_lsu_pkt_d_bits_store = lsu_lsc_ctl_io_lsu_pkt_d_bits_store; // @[lsu.scala 173:46]
+  assign dccm_ctl_io_lsu_pkt_d_bits_dma = lsu_lsc_ctl_io_lsu_pkt_d_bits_dma; // @[lsu.scala 173:46]
+  assign dccm_ctl_io_lsu_pkt_m_valid = lsu_lsc_ctl_io_lsu_pkt_m_valid; // @[lsu.scala 174:46]
+  assign dccm_ctl_io_lsu_pkt_m_bits_store = lsu_lsc_ctl_io_lsu_pkt_m_bits_store; // @[lsu.scala 174:46]
+  assign dccm_ctl_io_lsu_pkt_m_bits_dma = lsu_lsc_ctl_io_lsu_pkt_m_bits_dma; // @[lsu.scala 174:46]
+  assign dccm_ctl_io_lsu_pkt_r_valid = lsu_lsc_ctl_io_lsu_pkt_r_valid; // @[lsu.scala 175:46]
+  assign dccm_ctl_io_lsu_pkt_r_bits_by = lsu_lsc_ctl_io_lsu_pkt_r_bits_by; // @[lsu.scala 175:46]
+  assign dccm_ctl_io_lsu_pkt_r_bits_half = lsu_lsc_ctl_io_lsu_pkt_r_bits_half; // @[lsu.scala 175:46]
+  assign dccm_ctl_io_lsu_pkt_r_bits_word = lsu_lsc_ctl_io_lsu_pkt_r_bits_word; // @[lsu.scala 175:46]
+  assign dccm_ctl_io_lsu_pkt_r_bits_load = lsu_lsc_ctl_io_lsu_pkt_r_bits_load; // @[lsu.scala 175:46]
+  assign dccm_ctl_io_lsu_pkt_r_bits_store = lsu_lsc_ctl_io_lsu_pkt_r_bits_store; // @[lsu.scala 175:46]
+  assign dccm_ctl_io_lsu_pkt_r_bits_dma = lsu_lsc_ctl_io_lsu_pkt_r_bits_dma; // @[lsu.scala 175:46]
+  assign dccm_ctl_io_addr_in_dccm_d = lsu_lsc_ctl_io_addr_in_dccm_d; // @[lsu.scala 176:46]
+  assign dccm_ctl_io_addr_in_dccm_m = lsu_lsc_ctl_io_addr_in_dccm_m; // @[lsu.scala 177:46]
+  assign dccm_ctl_io_addr_in_dccm_r = lsu_lsc_ctl_io_addr_in_dccm_r; // @[lsu.scala 178:46]
+  assign dccm_ctl_io_addr_in_pic_d = lsu_lsc_ctl_io_addr_in_pic_d; // @[lsu.scala 179:46]
+  assign dccm_ctl_io_addr_in_pic_m = lsu_lsc_ctl_io_addr_in_pic_m; // @[lsu.scala 180:46]
+  assign dccm_ctl_io_addr_in_pic_r = lsu_lsc_ctl_io_addr_in_pic_r; // @[lsu.scala 181:46]
+  assign dccm_ctl_io_lsu_raw_fwd_lo_r = lsu_raw_fwd_lo_r; // @[lsu.scala 182:46]
+  assign dccm_ctl_io_lsu_raw_fwd_hi_r = lsu_raw_fwd_hi_r; // @[lsu.scala 183:46]
+  assign dccm_ctl_io_lsu_commit_r = lsu_lsc_ctl_io_lsu_commit_r; // @[lsu.scala 184:46]
+  assign dccm_ctl_io_ldst_dual_m = lsu_addr_m[2] != lsu_addr_m[2]; // @[lsu.scala 166:46]
+  assign dccm_ctl_io_ldst_dual_r = lsu_addr_r[2] != lsu_addr_r[2]; // @[lsu.scala 167:46]
+  assign dccm_ctl_io_lsu_addr_d = lsu_lsc_ctl_io_lsu_addr_d; // @[lsu.scala 185:46]
+  assign dccm_ctl_io_lsu_addr_m = lsu_addr_m[15:0]; // @[lsu.scala 186:46]
+  assign dccm_ctl_io_lsu_addr_r = lsu_lsc_ctl_io_lsu_addr_r; // @[lsu.scala 187:46]
+  assign dccm_ctl_io_end_addr_d = lsu_addr_d[15:0]; // @[lsu.scala 188:46]
+  assign dccm_ctl_io_end_addr_m = lsu_addr_m[15:0]; // @[lsu.scala 189:46]
+  assign dccm_ctl_io_end_addr_r = lsu_addr_r[15:0]; // @[lsu.scala 190:46]
+  assign dccm_ctl_io_stbuf_reqvld_any = stbuf_io_stbuf_reqvld_any; // @[lsu.scala 191:46]
+  assign dccm_ctl_io_stbuf_addr_any = stbuf_io_stbuf_addr_any; // @[lsu.scala 192:46]
+  assign dccm_ctl_io_stbuf_data_any = stbuf_io_stbuf_data_any; // @[lsu.scala 193:46]
+  assign dccm_ctl_io_stbuf_ecc_any = ecc_io_stbuf_ecc_any; // @[lsu.scala 194:46]
+  assign dccm_ctl_io_stbuf_fwddata_hi_m = stbuf_io_stbuf_fwddata_hi_m; // @[lsu.scala 195:46]
+  assign dccm_ctl_io_stbuf_fwddata_lo_m = stbuf_io_stbuf_fwddata_lo_m; // @[lsu.scala 196:46]
+  assign dccm_ctl_io_stbuf_fwdbyteen_lo_m = stbuf_io_stbuf_fwdbyteen_lo_m; // @[lsu.scala 197:46]
+  assign dccm_ctl_io_stbuf_fwdbyteen_hi_m = stbuf_io_stbuf_fwdbyteen_hi_m; // @[lsu.scala 198:46]
+  assign dccm_ctl_io_lsu_double_ecc_error_r = ecc_io_lsu_double_ecc_error_r; // @[lsu.scala 199:46]
+  assign dccm_ctl_io_single_ecc_error_hi_r = ecc_io_single_ecc_error_hi_r; // @[lsu.scala 200:46]
+  assign dccm_ctl_io_single_ecc_error_lo_r = ecc_io_single_ecc_error_lo_r; // @[lsu.scala 201:46]
+  assign dccm_ctl_io_sec_data_hi_r = ecc_io_sec_data_hi_r; // @[lsu.scala 202:46]
+  assign dccm_ctl_io_sec_data_lo_r = ecc_io_sec_data_lo_r; // @[lsu.scala 203:46]
+  assign dccm_ctl_io_sec_data_hi_r_ff = ecc_io_sec_data_hi_r_ff; // @[lsu.scala 204:46]
+  assign dccm_ctl_io_sec_data_lo_r_ff = ecc_io_sec_data_lo_r_ff; // @[lsu.scala 205:46]
+  assign dccm_ctl_io_sec_data_ecc_hi_r_ff = ecc_io_sec_data_ecc_hi_r_ff; // @[lsu.scala 206:46]
+  assign dccm_ctl_io_sec_data_ecc_lo_r_ff = ecc_io_sec_data_ecc_lo_r_ff; // @[lsu.scala 207:46]
+  assign dccm_ctl_io_store_data_m = lsu_lsc_ctl_io_store_data_m; // @[lsu.scala 211:46]
+  assign dccm_ctl_io_dma_dccm_wen = _T_11 & io_lsu_dma_dma_lsc_ctl_dma_mem_sz[1]; // @[lsu.scala 212:46]
+  assign dccm_ctl_io_dma_pic_wen = _T_10 & lsu_lsc_ctl_io_addr_in_pic_d; // @[lsu.scala 213:46]
+  assign dccm_ctl_io_dma_mem_tag_m = dma_mem_tag_m; // @[lsu.scala 214:46]
+  assign dccm_ctl_io_dma_dccm_wdata_lo = dma_dccm_wdata[31:0]; // @[lsu.scala 215:46]
+  assign dccm_ctl_io_dma_dccm_wdata_hi = dma_dccm_wdata[63:32]; // @[lsu.scala 216:46]
+  assign dccm_ctl_io_dma_dccm_wdata_ecc_hi = ecc_io_dma_dccm_wdata_ecc_hi; // @[lsu.scala 217:46]
+  assign dccm_ctl_io_dma_dccm_wdata_ecc_lo = ecc_io_dma_dccm_wdata_ecc_lo; // @[lsu.scala 218:46]
+  assign dccm_ctl_io_dma_dccm_ctl_dma_mem_addr = io_lsu_dma_dma_dccm_ctl_dma_mem_addr; // @[lsu.scala 221:27]
+  assign dccm_ctl_io_dma_dccm_ctl_dma_mem_wdata = io_lsu_dma_dma_dccm_ctl_dma_mem_wdata; // @[lsu.scala 221:27]
+  assign dccm_ctl_io_dccm_rd_data_lo = io_dccm_rd_data_lo; // @[lsu.scala 222:11]
+  assign dccm_ctl_io_dccm_rd_data_hi = io_dccm_rd_data_hi; // @[lsu.scala 222:11]
+  assign dccm_ctl_io_lsu_pic_picm_rd_data = io_lsu_pic_picm_rd_data; // @[lsu.scala 223:14]
   assign stbuf_clock = clock;
   assign stbuf_reset = reset;
-  assign stbuf_io_lsu_stbuf_c1_clk = clkdomain_io_lsu_stbuf_c1_clk; // @[lsu.scala 219:54]
-  assign stbuf_io_lsu_free_c2_clk = clkdomain_io_lsu_free_c2_clk; // @[lsu.scala 220:54]
-  assign stbuf_io_lsu_pkt_m_valid = lsu_lsc_ctl_io_lsu_pkt_m_valid; // @[lsu.scala 221:48]
-  assign stbuf_io_lsu_pkt_m_bits_store = lsu_lsc_ctl_io_lsu_pkt_m_bits_store; // @[lsu.scala 221:48]
-  assign stbuf_io_lsu_pkt_m_bits_dma = lsu_lsc_ctl_io_lsu_pkt_m_bits_dma; // @[lsu.scala 221:48]
-  assign stbuf_io_lsu_pkt_r_valid = lsu_lsc_ctl_io_lsu_pkt_r_valid; // @[lsu.scala 222:48]
-  assign stbuf_io_lsu_pkt_r_bits_by = lsu_lsc_ctl_io_lsu_pkt_r_bits_by; // @[lsu.scala 222:48]
-  assign stbuf_io_lsu_pkt_r_bits_half = lsu_lsc_ctl_io_lsu_pkt_r_bits_half; // @[lsu.scala 222:48]
-  assign stbuf_io_lsu_pkt_r_bits_word = lsu_lsc_ctl_io_lsu_pkt_r_bits_word; // @[lsu.scala 222:48]
-  assign stbuf_io_lsu_pkt_r_bits_dword = lsu_lsc_ctl_io_lsu_pkt_r_bits_dword; // @[lsu.scala 222:48]
-  assign stbuf_io_lsu_pkt_r_bits_store = lsu_lsc_ctl_io_lsu_pkt_r_bits_store; // @[lsu.scala 222:48]
-  assign stbuf_io_lsu_pkt_r_bits_dma = lsu_lsc_ctl_io_lsu_pkt_r_bits_dma; // @[lsu.scala 222:48]
-  assign stbuf_io_store_stbuf_reqvld_r = _T_33 & _T_38; // @[lsu.scala 223:48]
-  assign stbuf_io_lsu_commit_r = lsu_lsc_ctl_io_lsu_commit_r; // @[lsu.scala 224:49]
-  assign stbuf_io_dec_lsu_valid_raw_d = io_dec_lsu_valid_raw_d; // @[lsu.scala 225:49]
-  assign stbuf_io_store_data_hi_r = dccm_ctl_io_store_data_hi_r; // @[lsu.scala 226:62]
-  assign stbuf_io_store_data_lo_r = dccm_ctl_io_store_data_lo_r; // @[lsu.scala 227:62]
-  assign stbuf_io_store_datafn_hi_r = dccm_ctl_io_store_datafn_hi_r; // @[lsu.scala 228:49]
-  assign stbuf_io_store_datafn_lo_r = dccm_ctl_io_store_datafn_lo_r; // @[lsu.scala 229:56]
-  assign stbuf_io_lsu_stbuf_commit_any = dccm_ctl_io_lsu_stbuf_commit_any; // @[lsu.scala 230:52]
-  assign stbuf_io_lsu_addr_m = lsu_lsc_ctl_io_lsu_addr_m; // @[lsu.scala 232:64]
-  assign stbuf_io_lsu_addr_r = lsu_lsc_ctl_io_lsu_addr_r; // @[lsu.scala 233:64]
-  assign stbuf_io_end_addr_m = lsu_lsc_ctl_io_end_addr_m; // @[lsu.scala 235:64]
-  assign stbuf_io_end_addr_r = lsu_lsc_ctl_io_end_addr_r; // @[lsu.scala 236:64]
-  assign stbuf_io_ldst_dual_d = lsu_lsc_ctl_io_lsu_addr_d[2] != lsu_lsc_ctl_io_end_addr_d[2]; // @[lsu.scala 216:50]
-  assign stbuf_io_ldst_dual_m = lsu_lsc_ctl_io_lsu_addr_m[2] != lsu_lsc_ctl_io_end_addr_m[2]; // @[lsu.scala 217:50]
-  assign stbuf_io_ldst_dual_r = lsu_lsc_ctl_io_lsu_addr_r[2] != lsu_lsc_ctl_io_end_addr_r[2]; // @[lsu.scala 218:50]
-  assign stbuf_io_addr_in_dccm_m = lsu_lsc_ctl_io_addr_in_dccm_m; // @[lsu.scala 237:49]
-  assign stbuf_io_addr_in_dccm_r = lsu_lsc_ctl_io_addr_in_dccm_r; // @[lsu.scala 238:56]
-  assign stbuf_io_scan_mode = io_scan_mode; // @[lsu.scala 240:49]
+  assign stbuf_io_lsu_stbuf_c1_clk = clkdomain_io_lsu_stbuf_c1_clk; // @[lsu.scala 229:54]
+  assign stbuf_io_lsu_free_c2_clk = clkdomain_io_lsu_free_c2_clk; // @[lsu.scala 230:54]
+  assign stbuf_io_lsu_pkt_m_valid = lsu_lsc_ctl_io_lsu_pkt_m_valid; // @[lsu.scala 231:48]
+  assign stbuf_io_lsu_pkt_m_bits_store = lsu_lsc_ctl_io_lsu_pkt_m_bits_store; // @[lsu.scala 231:48]
+  assign stbuf_io_lsu_pkt_m_bits_dma = lsu_lsc_ctl_io_lsu_pkt_m_bits_dma; // @[lsu.scala 231:48]
+  assign stbuf_io_lsu_pkt_r_valid = lsu_lsc_ctl_io_lsu_pkt_r_valid; // @[lsu.scala 232:48]
+  assign stbuf_io_lsu_pkt_r_bits_by = lsu_lsc_ctl_io_lsu_pkt_r_bits_by; // @[lsu.scala 232:48]
+  assign stbuf_io_lsu_pkt_r_bits_half = lsu_lsc_ctl_io_lsu_pkt_r_bits_half; // @[lsu.scala 232:48]
+  assign stbuf_io_lsu_pkt_r_bits_word = lsu_lsc_ctl_io_lsu_pkt_r_bits_word; // @[lsu.scala 232:48]
+  assign stbuf_io_lsu_pkt_r_bits_dword = lsu_lsc_ctl_io_lsu_pkt_r_bits_dword; // @[lsu.scala 232:48]
+  assign stbuf_io_lsu_pkt_r_bits_store = lsu_lsc_ctl_io_lsu_pkt_r_bits_store; // @[lsu.scala 232:48]
+  assign stbuf_io_lsu_pkt_r_bits_dma = lsu_lsc_ctl_io_lsu_pkt_r_bits_dma; // @[lsu.scala 232:48]
+  assign stbuf_io_store_stbuf_reqvld_r = _T_33 & _T_38; // @[lsu.scala 233:48]
+  assign stbuf_io_lsu_commit_r = lsu_lsc_ctl_io_lsu_commit_r; // @[lsu.scala 234:49]
+  assign stbuf_io_dec_lsu_valid_raw_d = io_dec_lsu_valid_raw_d; // @[lsu.scala 235:49]
+  assign stbuf_io_store_data_hi_r = dccm_ctl_io_store_data_hi_r; // @[lsu.scala 236:62]
+  assign stbuf_io_store_data_lo_r = dccm_ctl_io_store_data_lo_r; // @[lsu.scala 237:62]
+  assign stbuf_io_store_datafn_hi_r = dccm_ctl_io_store_datafn_hi_r; // @[lsu.scala 238:49]
+  assign stbuf_io_store_datafn_lo_r = dccm_ctl_io_store_datafn_lo_r; // @[lsu.scala 239:56]
+  assign stbuf_io_lsu_stbuf_commit_any = dccm_ctl_io_lsu_stbuf_commit_any; // @[lsu.scala 240:52]
+  assign stbuf_io_lsu_addr_m = lsu_lsc_ctl_io_lsu_addr_m; // @[lsu.scala 242:64]
+  assign stbuf_io_lsu_addr_r = lsu_lsc_ctl_io_lsu_addr_r; // @[lsu.scala 243:64]
+  assign stbuf_io_end_addr_m = lsu_lsc_ctl_io_end_addr_m; // @[lsu.scala 245:64]
+  assign stbuf_io_end_addr_r = lsu_lsc_ctl_io_end_addr_r; // @[lsu.scala 246:64]
+  assign stbuf_io_ldst_dual_d = lsu_addr_d[2] != lsu_addr_d[2]; // @[lsu.scala 226:50]
+  assign stbuf_io_ldst_dual_m = lsu_addr_m[2] != lsu_addr_m[2]; // @[lsu.scala 227:50]
+  assign stbuf_io_ldst_dual_r = lsu_addr_r[2] != lsu_addr_r[2]; // @[lsu.scala 228:50]
+  assign stbuf_io_addr_in_dccm_m = lsu_lsc_ctl_io_addr_in_dccm_m; // @[lsu.scala 247:49]
+  assign stbuf_io_addr_in_dccm_r = lsu_lsc_ctl_io_addr_in_dccm_r; // @[lsu.scala 248:56]
   assign ecc_clock = clock;
   assign ecc_reset = reset;
-  assign ecc_io_lsu_c2_r_clk = clkdomain_io_lsu_c2_r_clk; // @[lsu.scala 245:52]
-  assign ecc_io_clk_override = io_clk_override; // @[lsu.scala 244:50]
-  assign ecc_io_lsu_pkt_m_valid = lsu_lsc_ctl_io_lsu_pkt_m_valid; // @[lsu.scala 246:52]
-  assign ecc_io_lsu_pkt_m_bits_load = lsu_lsc_ctl_io_lsu_pkt_m_bits_load; // @[lsu.scala 246:52]
-  assign ecc_io_lsu_pkt_m_bits_store = lsu_lsc_ctl_io_lsu_pkt_m_bits_store; // @[lsu.scala 246:52]
-  assign ecc_io_lsu_pkt_m_bits_dma = lsu_lsc_ctl_io_lsu_pkt_m_bits_dma; // @[lsu.scala 246:52]
-  assign ecc_io_stbuf_data_any = stbuf_io_stbuf_data_any; // @[lsu.scala 248:54]
-  assign ecc_io_dec_tlu_core_ecc_disable = io_dec_tlu_core_ecc_disable; // @[lsu.scala 249:50]
-  assign ecc_io_lsu_addr_m = lsu_lsc_ctl_io_lsu_addr_m[15:0]; // @[lsu.scala 254:58]
-  assign ecc_io_end_addr_m = lsu_lsc_ctl_io_end_addr_m[15:0]; // @[lsu.scala 255:58]
-  assign ecc_io_dccm_rdata_hi_m = dccm_ctl_io_dccm_rdata_hi_m; // @[lsu.scala 258:54]
-  assign ecc_io_dccm_rdata_lo_m = dccm_ctl_io_dccm_rdata_lo_m; // @[lsu.scala 259:54]
-  assign ecc_io_dccm_data_ecc_hi_m = dccm_ctl_io_dccm_data_ecc_hi_m; // @[lsu.scala 262:50]
-  assign ecc_io_dccm_data_ecc_lo_m = dccm_ctl_io_dccm_data_ecc_lo_m; // @[lsu.scala 263:50]
-  assign ecc_io_ld_single_ecc_error_r = dccm_ctl_io_ld_single_ecc_error_r; // @[lsu.scala 264:50]
-  assign ecc_io_ld_single_ecc_error_r_ff = dccm_ctl_io_ld_single_ecc_error_r_ff; // @[lsu.scala 265:50]
-  assign ecc_io_lsu_dccm_rden_m = dccm_ctl_io_lsu_dccm_rden_m; // @[lsu.scala 266:50]
-  assign ecc_io_addr_in_dccm_m = lsu_lsc_ctl_io_addr_in_dccm_m; // @[lsu.scala 267:50]
-  assign ecc_io_dma_dccm_wen = _T_11 & io_lsu_dma_dma_lsc_ctl_dma_mem_sz[1]; // @[lsu.scala 268:50]
-  assign ecc_io_dma_dccm_wdata_lo = dma_dccm_wdata[31:0]; // @[lsu.scala 269:50]
-  assign ecc_io_dma_dccm_wdata_hi = dma_dccm_wdata[63:32]; // @[lsu.scala 270:50]
-  assign ecc_io_scan_mode = io_scan_mode; // @[lsu.scala 271:50]
-  assign trigger_io_trigger_pkt_any_0_select = io_trigger_pkt_any_0_select; // @[lsu.scala 275:50]
-  assign trigger_io_trigger_pkt_any_0_match_pkt = io_trigger_pkt_any_0_match_pkt; // @[lsu.scala 275:50]
-  assign trigger_io_trigger_pkt_any_0_store = io_trigger_pkt_any_0_store; // @[lsu.scala 275:50]
-  assign trigger_io_trigger_pkt_any_0_load = io_trigger_pkt_any_0_load; // @[lsu.scala 275:50]
-  assign trigger_io_trigger_pkt_any_0_m = io_trigger_pkt_any_0_m; // @[lsu.scala 275:50]
-  assign trigger_io_trigger_pkt_any_0_tdata2 = io_trigger_pkt_any_0_tdata2; // @[lsu.scala 275:50]
-  assign trigger_io_trigger_pkt_any_1_select = io_trigger_pkt_any_1_select; // @[lsu.scala 275:50]
-  assign trigger_io_trigger_pkt_any_1_match_pkt = io_trigger_pkt_any_1_match_pkt; // @[lsu.scala 275:50]
-  assign trigger_io_trigger_pkt_any_1_store = io_trigger_pkt_any_1_store; // @[lsu.scala 275:50]
-  assign trigger_io_trigger_pkt_any_1_load = io_trigger_pkt_any_1_load; // @[lsu.scala 275:50]
-  assign trigger_io_trigger_pkt_any_1_m = io_trigger_pkt_any_1_m; // @[lsu.scala 275:50]
-  assign trigger_io_trigger_pkt_any_1_tdata2 = io_trigger_pkt_any_1_tdata2; // @[lsu.scala 275:50]
-  assign trigger_io_trigger_pkt_any_2_select = io_trigger_pkt_any_2_select; // @[lsu.scala 275:50]
-  assign trigger_io_trigger_pkt_any_2_match_pkt = io_trigger_pkt_any_2_match_pkt; // @[lsu.scala 275:50]
-  assign trigger_io_trigger_pkt_any_2_store = io_trigger_pkt_any_2_store; // @[lsu.scala 275:50]
-  assign trigger_io_trigger_pkt_any_2_load = io_trigger_pkt_any_2_load; // @[lsu.scala 275:50]
-  assign trigger_io_trigger_pkt_any_2_m = io_trigger_pkt_any_2_m; // @[lsu.scala 275:50]
-  assign trigger_io_trigger_pkt_any_2_tdata2 = io_trigger_pkt_any_2_tdata2; // @[lsu.scala 275:50]
-  assign trigger_io_trigger_pkt_any_3_select = io_trigger_pkt_any_3_select; // @[lsu.scala 275:50]
-  assign trigger_io_trigger_pkt_any_3_match_pkt = io_trigger_pkt_any_3_match_pkt; // @[lsu.scala 275:50]
-  assign trigger_io_trigger_pkt_any_3_store = io_trigger_pkt_any_3_store; // @[lsu.scala 275:50]
-  assign trigger_io_trigger_pkt_any_3_load = io_trigger_pkt_any_3_load; // @[lsu.scala 275:50]
-  assign trigger_io_trigger_pkt_any_3_m = io_trigger_pkt_any_3_m; // @[lsu.scala 275:50]
-  assign trigger_io_trigger_pkt_any_3_tdata2 = io_trigger_pkt_any_3_tdata2; // @[lsu.scala 275:50]
-  assign trigger_io_lsu_pkt_m_valid = lsu_lsc_ctl_io_lsu_pkt_m_valid; // @[lsu.scala 276:50]
-  assign trigger_io_lsu_pkt_m_bits_half = lsu_lsc_ctl_io_lsu_pkt_m_bits_half; // @[lsu.scala 276:50]
-  assign trigger_io_lsu_pkt_m_bits_word = lsu_lsc_ctl_io_lsu_pkt_m_bits_word; // @[lsu.scala 276:50]
-  assign trigger_io_lsu_pkt_m_bits_load = lsu_lsc_ctl_io_lsu_pkt_m_bits_load; // @[lsu.scala 276:50]
-  assign trigger_io_lsu_pkt_m_bits_store = lsu_lsc_ctl_io_lsu_pkt_m_bits_store; // @[lsu.scala 276:50]
-  assign trigger_io_lsu_pkt_m_bits_dma = lsu_lsc_ctl_io_lsu_pkt_m_bits_dma; // @[lsu.scala 276:50]
-  assign trigger_io_lsu_addr_m = lsu_lsc_ctl_io_lsu_addr_m; // @[lsu.scala 277:50]
-  assign trigger_io_store_data_m = lsu_lsc_ctl_io_store_data_m; // @[lsu.scala 278:50]
+  assign ecc_io_clk_override = io_clk_override; // @[lsu.scala 254:50]
+  assign ecc_io_lsu_pkt_r_valid = lsu_lsc_ctl_io_lsu_pkt_r_valid; // @[lsu.scala 257:52]
+  assign ecc_io_lsu_pkt_r_bits_load = lsu_lsc_ctl_io_lsu_pkt_r_bits_load; // @[lsu.scala 257:52]
+  assign ecc_io_lsu_pkt_r_bits_store = lsu_lsc_ctl_io_lsu_pkt_r_bits_store; // @[lsu.scala 257:52]
+  assign ecc_io_stbuf_data_any = stbuf_io_stbuf_data_any; // @[lsu.scala 258:54]
+  assign ecc_io_dec_tlu_core_ecc_disable = io_dec_tlu_core_ecc_disable; // @[lsu.scala 259:50]
+  assign ecc_io_lsu_dccm_rden_r = dccm_ctl_io_lsu_dccm_rden_r; // @[lsu.scala 260:56]
+  assign ecc_io_addr_in_dccm_r = lsu_lsc_ctl_io_addr_in_dccm_r; // @[lsu.scala 261:50]
+  assign ecc_io_lsu_addr_r = lsu_addr_r[15:0]; // @[lsu.scala 262:58]
+  assign ecc_io_end_addr_r = lsu_addr_r[15:0]; // @[lsu.scala 263:58]
+  assign ecc_io_dccm_rdata_hi_r = dccm_ctl_io_dccm_rdata_hi_r; // @[lsu.scala 266:54]
+  assign ecc_io_dccm_rdata_lo_r = dccm_ctl_io_dccm_rdata_lo_r; // @[lsu.scala 267:54]
+  assign ecc_io_dccm_data_ecc_hi_r = dccm_ctl_io_dccm_data_ecc_hi_r; // @[lsu.scala 270:50]
+  assign ecc_io_dccm_data_ecc_lo_r = dccm_ctl_io_dccm_data_ecc_lo_r; // @[lsu.scala 271:50]
+  assign ecc_io_ld_single_ecc_error_r = dccm_ctl_io_ld_single_ecc_error_r; // @[lsu.scala 274:50]
+  assign ecc_io_ld_single_ecc_error_r_ff = dccm_ctl_io_ld_single_ecc_error_r_ff; // @[lsu.scala 275:50]
+  assign ecc_io_dma_dccm_wen = _T_11 & io_lsu_dma_dma_lsc_ctl_dma_mem_sz[1]; // @[lsu.scala 278:50]
+  assign ecc_io_dma_dccm_wdata_lo = dma_dccm_wdata[31:0]; // @[lsu.scala 279:50]
+  assign ecc_io_dma_dccm_wdata_hi = dma_dccm_wdata[63:32]; // @[lsu.scala 280:50]
+  assign trigger_io_trigger_pkt_any_0_select = io_trigger_pkt_any_0_select; // @[lsu.scala 285:50]
+  assign trigger_io_trigger_pkt_any_0_match_pkt = io_trigger_pkt_any_0_match_pkt; // @[lsu.scala 285:50]
+  assign trigger_io_trigger_pkt_any_0_store = io_trigger_pkt_any_0_store; // @[lsu.scala 285:50]
+  assign trigger_io_trigger_pkt_any_0_load = io_trigger_pkt_any_0_load; // @[lsu.scala 285:50]
+  assign trigger_io_trigger_pkt_any_0_m = io_trigger_pkt_any_0_m; // @[lsu.scala 285:50]
+  assign trigger_io_trigger_pkt_any_0_tdata2 = io_trigger_pkt_any_0_tdata2; // @[lsu.scala 285:50]
+  assign trigger_io_trigger_pkt_any_1_select = io_trigger_pkt_any_1_select; // @[lsu.scala 285:50]
+  assign trigger_io_trigger_pkt_any_1_match_pkt = io_trigger_pkt_any_1_match_pkt; // @[lsu.scala 285:50]
+  assign trigger_io_trigger_pkt_any_1_store = io_trigger_pkt_any_1_store; // @[lsu.scala 285:50]
+  assign trigger_io_trigger_pkt_any_1_load = io_trigger_pkt_any_1_load; // @[lsu.scala 285:50]
+  assign trigger_io_trigger_pkt_any_1_m = io_trigger_pkt_any_1_m; // @[lsu.scala 285:50]
+  assign trigger_io_trigger_pkt_any_1_tdata2 = io_trigger_pkt_any_1_tdata2; // @[lsu.scala 285:50]
+  assign trigger_io_trigger_pkt_any_2_select = io_trigger_pkt_any_2_select; // @[lsu.scala 285:50]
+  assign trigger_io_trigger_pkt_any_2_match_pkt = io_trigger_pkt_any_2_match_pkt; // @[lsu.scala 285:50]
+  assign trigger_io_trigger_pkt_any_2_store = io_trigger_pkt_any_2_store; // @[lsu.scala 285:50]
+  assign trigger_io_trigger_pkt_any_2_load = io_trigger_pkt_any_2_load; // @[lsu.scala 285:50]
+  assign trigger_io_trigger_pkt_any_2_m = io_trigger_pkt_any_2_m; // @[lsu.scala 285:50]
+  assign trigger_io_trigger_pkt_any_2_tdata2 = io_trigger_pkt_any_2_tdata2; // @[lsu.scala 285:50]
+  assign trigger_io_trigger_pkt_any_3_select = io_trigger_pkt_any_3_select; // @[lsu.scala 285:50]
+  assign trigger_io_trigger_pkt_any_3_match_pkt = io_trigger_pkt_any_3_match_pkt; // @[lsu.scala 285:50]
+  assign trigger_io_trigger_pkt_any_3_store = io_trigger_pkt_any_3_store; // @[lsu.scala 285:50]
+  assign trigger_io_trigger_pkt_any_3_load = io_trigger_pkt_any_3_load; // @[lsu.scala 285:50]
+  assign trigger_io_trigger_pkt_any_3_m = io_trigger_pkt_any_3_m; // @[lsu.scala 285:50]
+  assign trigger_io_trigger_pkt_any_3_tdata2 = io_trigger_pkt_any_3_tdata2; // @[lsu.scala 285:50]
+  assign trigger_io_lsu_pkt_m_valid = lsu_lsc_ctl_io_lsu_pkt_m_valid; // @[lsu.scala 286:50]
+  assign trigger_io_lsu_pkt_m_bits_half = lsu_lsc_ctl_io_lsu_pkt_m_bits_half; // @[lsu.scala 286:50]
+  assign trigger_io_lsu_pkt_m_bits_word = lsu_lsc_ctl_io_lsu_pkt_m_bits_word; // @[lsu.scala 286:50]
+  assign trigger_io_lsu_pkt_m_bits_load = lsu_lsc_ctl_io_lsu_pkt_m_bits_load; // @[lsu.scala 286:50]
+  assign trigger_io_lsu_pkt_m_bits_store = lsu_lsc_ctl_io_lsu_pkt_m_bits_store; // @[lsu.scala 286:50]
+  assign trigger_io_lsu_pkt_m_bits_dma = lsu_lsc_ctl_io_lsu_pkt_m_bits_dma; // @[lsu.scala 286:50]
+  assign trigger_io_lsu_addr_m = lsu_lsc_ctl_io_lsu_addr_m; // @[lsu.scala 287:50]
+  assign trigger_io_store_data_m = lsu_lsc_ctl_io_store_data_m; // @[lsu.scala 288:50]
   assign clkdomain_clock = clock;
   assign clkdomain_reset = reset;
-  assign clkdomain_io_active_clk = io_active_clk; // @[lsu.scala 284:50]
-  assign clkdomain_io_clk_override = io_clk_override; // @[lsu.scala 285:50]
-  assign clkdomain_io_dec_tlu_force_halt = io_dec_tlu_force_halt; // @[lsu.scala 286:50]
-  assign clkdomain_io_dma_dccm_req = io_lsu_dma_dma_lsc_ctl_dma_dccm_req; // @[lsu.scala 287:50]
-  assign clkdomain_io_ldst_stbuf_reqvld_r = stbuf_io_ldst_stbuf_reqvld_r; // @[lsu.scala 288:50]
-  assign clkdomain_io_stbuf_reqvld_any = stbuf_io_stbuf_reqvld_any; // @[lsu.scala 289:50]
-  assign clkdomain_io_stbuf_reqvld_flushed_any = stbuf_io_stbuf_reqvld_flushed_any; // @[lsu.scala 290:50]
-  assign clkdomain_io_lsu_busreq_r = bus_intf_io_lsu_busreq_r; // @[lsu.scala 291:50]
-  assign clkdomain_io_lsu_bus_buffer_pend_any = bus_intf_io_lsu_bus_buffer_pend_any; // @[lsu.scala 292:50]
-  assign clkdomain_io_lsu_bus_buffer_empty_any = bus_intf_io_lsu_bus_buffer_empty_any; // @[lsu.scala 293:50]
-  assign clkdomain_io_lsu_stbuf_empty_any = stbuf_io_lsu_stbuf_empty_any; // @[lsu.scala 294:50]
-  assign clkdomain_io_lsu_bus_clk_en = io_lsu_bus_clk_en; // @[lsu.scala 295:50]
-  assign clkdomain_io_lsu_p_valid = io_lsu_p_valid; // @[lsu.scala 296:50]
-  assign clkdomain_io_lsu_pkt_d_valid = lsu_lsc_ctl_io_lsu_pkt_d_valid; // @[lsu.scala 297:50]
-  assign clkdomain_io_lsu_pkt_d_bits_store = lsu_lsc_ctl_io_lsu_pkt_d_bits_store; // @[lsu.scala 297:50]
-  assign clkdomain_io_lsu_pkt_m_valid = lsu_lsc_ctl_io_lsu_pkt_m_valid; // @[lsu.scala 298:50]
-  assign clkdomain_io_lsu_pkt_m_bits_store = lsu_lsc_ctl_io_lsu_pkt_m_bits_store; // @[lsu.scala 298:50]
-  assign clkdomain_io_lsu_pkt_r_valid = lsu_lsc_ctl_io_lsu_pkt_r_valid; // @[lsu.scala 299:50]
-  assign clkdomain_io_scan_mode = io_scan_mode; // @[lsu.scala 300:50]
+  assign clkdomain_io_active_clk = io_active_clk; // @[lsu.scala 294:50]
+  assign clkdomain_io_clk_override = io_clk_override; // @[lsu.scala 295:50]
+  assign clkdomain_io_dec_tlu_force_halt = io_dec_tlu_force_halt; // @[lsu.scala 296:50]
+  assign clkdomain_io_dma_dccm_req = io_lsu_dma_dma_lsc_ctl_dma_dccm_req; // @[lsu.scala 297:50]
+  assign clkdomain_io_ldst_stbuf_reqvld_r = stbuf_io_ldst_stbuf_reqvld_r; // @[lsu.scala 298:50]
+  assign clkdomain_io_stbuf_reqvld_any = stbuf_io_stbuf_reqvld_any; // @[lsu.scala 299:50]
+  assign clkdomain_io_stbuf_reqvld_flushed_any = stbuf_io_stbuf_reqvld_flushed_any; // @[lsu.scala 300:50]
+  assign clkdomain_io_lsu_busreq_r = bus_intf_io_lsu_busreq_r; // @[lsu.scala 301:50]
+  assign clkdomain_io_lsu_bus_buffer_pend_any = bus_intf_io_lsu_bus_buffer_pend_any; // @[lsu.scala 302:50]
+  assign clkdomain_io_lsu_bus_buffer_empty_any = bus_intf_io_lsu_bus_buffer_empty_any; // @[lsu.scala 303:50]
+  assign clkdomain_io_lsu_stbuf_empty_any = stbuf_io_lsu_stbuf_empty_any; // @[lsu.scala 304:50]
+  assign clkdomain_io_lsu_bus_clk_en = io_lsu_bus_clk_en; // @[lsu.scala 305:50]
+  assign clkdomain_io_lsu_p_valid = io_lsu_p_valid; // @[lsu.scala 306:50]
+  assign clkdomain_io_lsu_pkt_d_valid = lsu_lsc_ctl_io_lsu_pkt_d_valid; // @[lsu.scala 307:50]
+  assign clkdomain_io_lsu_pkt_d_bits_store = lsu_lsc_ctl_io_lsu_pkt_d_bits_store; // @[lsu.scala 307:50]
+  assign clkdomain_io_lsu_pkt_m_valid = lsu_lsc_ctl_io_lsu_pkt_m_valid; // @[lsu.scala 308:50]
+  assign clkdomain_io_lsu_pkt_m_bits_store = lsu_lsc_ctl_io_lsu_pkt_m_bits_store; // @[lsu.scala 308:50]
+  assign clkdomain_io_lsu_pkt_r_valid = lsu_lsc_ctl_io_lsu_pkt_r_valid; // @[lsu.scala 309:50]
   assign bus_intf_clock = clock;
   assign bus_intf_reset = reset;
-  assign bus_intf_io_scan_mode = io_scan_mode; // @[lsu.scala 304:49]
-  assign bus_intf_io_tlu_busbuff_dec_tlu_external_ldfwd_disable = io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[lsu.scala 305:26]
-  assign bus_intf_io_tlu_busbuff_dec_tlu_wb_coalescing_disable = io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu.scala 305:26]
-  assign bus_intf_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable = io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu.scala 305:26]
-  assign bus_intf_io_lsu_c1_r_clk = clkdomain_io_lsu_c1_r_clk; // @[lsu.scala 307:49]
-  assign bus_intf_io_lsu_c2_r_clk = clkdomain_io_lsu_c2_r_clk; // @[lsu.scala 308:49]
-  assign bus_intf_io_lsu_bus_ibuf_c1_clk = clkdomain_io_lsu_bus_ibuf_c1_clk; // @[lsu.scala 311:49]
-  assign bus_intf_io_lsu_bus_obuf_c1_clk = clkdomain_io_lsu_bus_obuf_c1_clk; // @[lsu.scala 312:49]
-  assign bus_intf_io_lsu_bus_buf_c1_clk = clkdomain_io_lsu_bus_buf_c1_clk; // @[lsu.scala 313:49]
-  assign bus_intf_io_lsu_free_c2_clk = clkdomain_io_lsu_free_c2_clk; // @[lsu.scala 314:49]
-  assign bus_intf_io_active_clk = io_active_clk; // @[lsu.scala 315:49]
-  assign bus_intf_io_lsu_busm_clk = clkdomain_io_lsu_busm_clk; // @[lsu.scala 316:49]
-  assign bus_intf_io_axi_aw_ready = io_axi_aw_ready; // @[lsu.scala 336:49]
-  assign bus_intf_io_axi_w_ready = io_axi_w_ready; // @[lsu.scala 336:49]
-  assign bus_intf_io_axi_b_valid = io_axi_b_valid; // @[lsu.scala 336:49]
-  assign bus_intf_io_axi_b_bits_resp = io_axi_b_bits_resp; // @[lsu.scala 336:49]
-  assign bus_intf_io_axi_b_bits_id = io_axi_b_bits_id; // @[lsu.scala 336:49]
-  assign bus_intf_io_axi_ar_ready = io_axi_ar_ready; // @[lsu.scala 336:49]
-  assign bus_intf_io_axi_r_valid = io_axi_r_valid; // @[lsu.scala 336:49]
-  assign bus_intf_io_axi_r_bits_id = io_axi_r_bits_id; // @[lsu.scala 336:49]
-  assign bus_intf_io_axi_r_bits_data = io_axi_r_bits_data; // @[lsu.scala 336:49]
-  assign bus_intf_io_axi_r_bits_resp = io_axi_r_bits_resp; // @[lsu.scala 336:49]
-  assign bus_intf_io_dec_lsu_valid_raw_d = io_dec_lsu_valid_raw_d; // @[lsu.scala 317:49]
-  assign bus_intf_io_lsu_busreq_m = _T_48 & _T_49; // @[lsu.scala 318:49]
-  assign bus_intf_io_lsu_pkt_m_valid = lsu_lsc_ctl_io_lsu_pkt_m_valid; // @[lsu.scala 327:49]
-  assign bus_intf_io_lsu_pkt_m_bits_by = lsu_lsc_ctl_io_lsu_pkt_m_bits_by; // @[lsu.scala 327:49]
-  assign bus_intf_io_lsu_pkt_m_bits_half = lsu_lsc_ctl_io_lsu_pkt_m_bits_half; // @[lsu.scala 327:49]
-  assign bus_intf_io_lsu_pkt_m_bits_word = lsu_lsc_ctl_io_lsu_pkt_m_bits_word; // @[lsu.scala 327:49]
-  assign bus_intf_io_lsu_pkt_m_bits_load = lsu_lsc_ctl_io_lsu_pkt_m_bits_load; // @[lsu.scala 327:49]
-  assign bus_intf_io_lsu_pkt_r_valid = lsu_lsc_ctl_io_lsu_pkt_r_valid; // @[lsu.scala 328:49]
-  assign bus_intf_io_lsu_pkt_r_bits_by = lsu_lsc_ctl_io_lsu_pkt_r_bits_by; // @[lsu.scala 328:49]
-  assign bus_intf_io_lsu_pkt_r_bits_half = lsu_lsc_ctl_io_lsu_pkt_r_bits_half; // @[lsu.scala 328:49]
-  assign bus_intf_io_lsu_pkt_r_bits_word = lsu_lsc_ctl_io_lsu_pkt_r_bits_word; // @[lsu.scala 328:49]
-  assign bus_intf_io_lsu_pkt_r_bits_load = lsu_lsc_ctl_io_lsu_pkt_r_bits_load; // @[lsu.scala 328:49]
-  assign bus_intf_io_lsu_pkt_r_bits_store = lsu_lsc_ctl_io_lsu_pkt_r_bits_store; // @[lsu.scala 328:49]
-  assign bus_intf_io_lsu_pkt_r_bits_unsign = lsu_lsc_ctl_io_lsu_pkt_r_bits_unsign; // @[lsu.scala 328:49]
-  assign bus_intf_io_lsu_addr_m = lsu_lsc_ctl_io_lsu_addr_m; // @[lsu.scala 322:49]
-  assign bus_intf_io_lsu_addr_r = lsu_lsc_ctl_io_lsu_addr_r; // @[lsu.scala 323:49]
-  assign bus_intf_io_end_addr_m = lsu_lsc_ctl_io_end_addr_m; // @[lsu.scala 324:49]
-  assign bus_intf_io_end_addr_r = lsu_lsc_ctl_io_end_addr_r; // @[lsu.scala 325:49]
-  assign bus_intf_io_ldst_dual_d = lsu_lsc_ctl_io_lsu_addr_d[2] != lsu_lsc_ctl_io_end_addr_d[2]; // @[lsu.scala 319:49]
-  assign bus_intf_io_ldst_dual_m = lsu_lsc_ctl_io_lsu_addr_m[2] != lsu_lsc_ctl_io_end_addr_m[2]; // @[lsu.scala 320:49]
-  assign bus_intf_io_ldst_dual_r = lsu_lsc_ctl_io_lsu_addr_r[2] != lsu_lsc_ctl_io_end_addr_r[2]; // @[lsu.scala 321:49]
-  assign bus_intf_io_store_data_r = dccm_ctl_io_store_data_r; // @[lsu.scala 326:49]
-  assign bus_intf_io_dec_tlu_force_halt = io_dec_tlu_force_halt; // @[lsu.scala 329:49]
-  assign bus_intf_io_lsu_commit_r = lsu_lsc_ctl_io_lsu_commit_r; // @[lsu.scala 330:49]
-  assign bus_intf_io_is_sideeffects_m = lsu_lsc_ctl_io_is_sideeffects_m; // @[lsu.scala 331:49]
-  assign bus_intf_io_flush_m_up = io_dec_tlu_flush_lower_r; // @[lsu.scala 332:49]
-  assign bus_intf_io_flush_r = io_dec_tlu_i0_kill_writeb_r; // @[lsu.scala 333:49]
-  assign bus_intf_io_lsu_bus_clk_en = io_lsu_bus_clk_en; // @[lsu.scala 337:49]
+  assign bus_intf_io_tlu_busbuff_dec_tlu_external_ldfwd_disable = io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[lsu.scala 315:26]
+  assign bus_intf_io_tlu_busbuff_dec_tlu_wb_coalescing_disable = io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu.scala 315:26]
+  assign bus_intf_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable = io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu.scala 315:26]
+  assign bus_intf_io_lsu_c1_r_clk = clkdomain_io_lsu_c1_r_clk; // @[lsu.scala 317:49]
+  assign bus_intf_io_lsu_c2_r_clk = clkdomain_io_lsu_c2_r_clk; // @[lsu.scala 318:49]
+  assign bus_intf_io_lsu_bus_ibuf_c1_clk = clkdomain_io_lsu_bus_ibuf_c1_clk; // @[lsu.scala 321:49]
+  assign bus_intf_io_lsu_bus_buf_c1_clk = clkdomain_io_lsu_bus_buf_c1_clk; // @[lsu.scala 323:49]
+  assign bus_intf_io_lsu_free_c2_clk = clkdomain_io_lsu_free_c2_clk; // @[lsu.scala 324:49]
+  assign bus_intf_io_active_clk = io_active_clk; // @[lsu.scala 325:49]
+  assign bus_intf_io_axi_aw_ready = io_axi_aw_ready; // @[lsu.scala 347:49]
+  assign bus_intf_io_axi_w_ready = io_axi_w_ready; // @[lsu.scala 347:49]
+  assign bus_intf_io_axi_b_valid = io_axi_b_valid; // @[lsu.scala 347:49]
+  assign bus_intf_io_axi_b_bits_resp = io_axi_b_bits_resp; // @[lsu.scala 347:49]
+  assign bus_intf_io_axi_b_bits_id = io_axi_b_bits_id; // @[lsu.scala 347:49]
+  assign bus_intf_io_axi_ar_ready = io_axi_ar_ready; // @[lsu.scala 347:49]
+  assign bus_intf_io_axi_r_valid = io_axi_r_valid; // @[lsu.scala 347:49]
+  assign bus_intf_io_axi_r_bits_id = io_axi_r_bits_id; // @[lsu.scala 347:49]
+  assign bus_intf_io_axi_r_bits_data = io_axi_r_bits_data; // @[lsu.scala 347:49]
+  assign bus_intf_io_axi_r_bits_resp = io_axi_r_bits_resp; // @[lsu.scala 347:49]
+  assign bus_intf_io_dec_lsu_valid_raw_d = io_dec_lsu_valid_raw_d; // @[lsu.scala 327:49]
+  assign bus_intf_io_lsu_busreq_m = _T_48 & _T_49; // @[lsu.scala 328:49]
+  assign bus_intf_io_lsu_pkt_m_valid = lsu_lsc_ctl_io_lsu_pkt_m_valid; // @[lsu.scala 337:49]
+  assign bus_intf_io_lsu_pkt_m_bits_by = lsu_lsc_ctl_io_lsu_pkt_m_bits_by; // @[lsu.scala 337:49]
+  assign bus_intf_io_lsu_pkt_m_bits_half = lsu_lsc_ctl_io_lsu_pkt_m_bits_half; // @[lsu.scala 337:49]
+  assign bus_intf_io_lsu_pkt_m_bits_word = lsu_lsc_ctl_io_lsu_pkt_m_bits_word; // @[lsu.scala 337:49]
+  assign bus_intf_io_lsu_pkt_m_bits_load = lsu_lsc_ctl_io_lsu_pkt_m_bits_load; // @[lsu.scala 337:49]
+  assign bus_intf_io_lsu_pkt_r_valid = lsu_lsc_ctl_io_lsu_pkt_r_valid; // @[lsu.scala 338:49]
+  assign bus_intf_io_lsu_pkt_r_bits_by = lsu_lsc_ctl_io_lsu_pkt_r_bits_by; // @[lsu.scala 338:49]
+  assign bus_intf_io_lsu_pkt_r_bits_half = lsu_lsc_ctl_io_lsu_pkt_r_bits_half; // @[lsu.scala 338:49]
+  assign bus_intf_io_lsu_pkt_r_bits_word = lsu_lsc_ctl_io_lsu_pkt_r_bits_word; // @[lsu.scala 338:49]
+  assign bus_intf_io_lsu_pkt_r_bits_load = lsu_lsc_ctl_io_lsu_pkt_r_bits_load; // @[lsu.scala 338:49]
+  assign bus_intf_io_lsu_pkt_r_bits_store = lsu_lsc_ctl_io_lsu_pkt_r_bits_store; // @[lsu.scala 338:49]
+  assign bus_intf_io_lsu_pkt_r_bits_unsign = lsu_lsc_ctl_io_lsu_pkt_r_bits_unsign; // @[lsu.scala 338:49]
+  assign bus_intf_io_lsu_addr_m = lsu_addr_m & _T_73; // @[lsu.scala 332:49]
+  assign bus_intf_io_lsu_addr_r = lsu_addr_r & _T_76; // @[lsu.scala 333:49]
+  assign bus_intf_io_end_addr_m = lsu_addr_m & _T_73; // @[lsu.scala 334:49]
+  assign bus_intf_io_end_addr_r = lsu_addr_r & _T_76; // @[lsu.scala 335:49]
+  assign bus_intf_io_ldst_dual_d = lsu_addr_d[2] != lsu_addr_d[2]; // @[lsu.scala 329:49]
+  assign bus_intf_io_ldst_dual_m = lsu_addr_m[2] != lsu_addr_m[2]; // @[lsu.scala 330:49]
+  assign bus_intf_io_ldst_dual_r = lsu_addr_r[2] != lsu_addr_r[2]; // @[lsu.scala 331:49]
+  assign bus_intf_io_store_data_r = dccm_ctl_io_store_data_r & _T_76; // @[lsu.scala 336:49]
+  assign bus_intf_io_dec_tlu_force_halt = io_dec_tlu_force_halt; // @[lsu.scala 339:49]
+  assign bus_intf_io_lsu_commit_r = lsu_lsc_ctl_io_lsu_commit_r; // @[lsu.scala 340:49]
+  assign bus_intf_io_is_sideeffects_m = lsu_lsc_ctl_io_is_sideeffects_m; // @[lsu.scala 341:49]
+  assign bus_intf_io_flush_m_up = io_dec_tlu_flush_lower_r; // @[lsu.scala 342:49]
+  assign bus_intf_io_flush_r = io_dec_tlu_i0_kill_writeb_r; // @[lsu.scala 343:49]
+  assign bus_intf_io_lsu_bus_clk_en = io_lsu_bus_clk_en; // @[lsu.scala 348:49]
 `ifdef RANDOMIZE_GARBAGE_ASSIGN
 `define RANDOMIZE
 `endif
diff --git a/lsu_dccm_ctl.anno.json b/lsu_dccm_ctl.anno.json
new file mode 100644
index 00000000..3789f822
--- /dev/null
+++ b/lsu_dccm_ctl.anno.json
@@ -0,0 +1,393 @@
+[
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_wren",
+    "sources":[
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_ld_single_ecc_error_r_ff",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_wen",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_stbuf_commit_any",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_reqvld_any",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_dccm_d",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_valid",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_load",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_store",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_addr_any",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_d",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_end_addr_d",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_word",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_dword"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_stbuf_commit_any",
+    "sources":[
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_reqvld_any",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_ld_single_ecc_error_r_ff",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_dccm_d",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_wen",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_valid",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_load",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_store",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_addr_any",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_d",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_end_addr_d",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_word",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_dword"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_store_datafn_lo_r",
+    "sources":[
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_data_any",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_stbuf_commit_any",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_lo_r",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_dccm_r",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_r",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_reqvld_any",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_addr_any",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_store_data_r",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_store",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_ld_single_ecc_error_r_ff",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_dccm_d",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_wen",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_valid",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_word",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_load",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_by",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_half",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_store",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_d",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_end_addr_d",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_word",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_dword"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_wr_data_lo",
+    "sources":[
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_ld_single_ecc_error_r_ff",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_wen",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_ecc_lo_r_ff",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_lo_r_ff",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_ecc_hi_r_ff",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_hi_r_ff",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_wdata_ecc_lo",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_wdata_lo",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_ecc_any",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_data_any"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pic_picm_wr_data",
+    "sources":[
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_pic_wen",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_ctl_dma_mem_wdata",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_store_datafn_lo_r",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_data_any",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_stbuf_commit_any",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_lo_r",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_dccm_r",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_r",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_reqvld_any",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_addr_any",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_store_data_r",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_store",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_ld_single_ecc_error_r_ff",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_dccm_d",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_wen",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_valid",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_word",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_load",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_by",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_half",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_store",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_d",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_end_addr_d",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_word",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_dword"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pic_picm_wren",
+    "sources":[
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_pic_wen",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_commit_r",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_pic_r",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_valid",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_store"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_wr_addr_hi",
+    "sources":[
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_ld_single_ecc_error_r_ff",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_wen",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_end_addr_d",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_addr_any"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_picm_mask_data_m",
+    "sources":[
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pic_picm_rd_data"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_data_ecc_lo_m",
+    "sources":[
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_rd_data_lo"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_rdata_lo_m",
+    "sources":[
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_rd_data_lo"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pic_picm_rden",
+    "sources":[
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_pic_d",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_valid",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_load"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_rdata_hi_m",
+    "sources":[
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_rd_data_hi"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_store_datafn_hi_r",
+    "sources":[
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_data_any",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_stbuf_commit_any",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_hi_r",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_dccm_r",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_r",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_reqvld_any",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_addr_any",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_store_data_r",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_store",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_ld_single_ecc_error_r_ff",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_dccm_d",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_wen",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_valid",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_word",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_load",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_by",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_half",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_store",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_d",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_end_addr_d",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_word",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_dword"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_data_ecc_hi_m",
+    "sources":[
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_rd_data_hi"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_ld_data_r",
+    "sources":[
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_r",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_pic_r",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_dccm_r",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_rdata_hi_r",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_rdata_lo_r"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_store_data_lo_r",
+    "sources":[
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_lo_r",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_r",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_store_data_r",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_store",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_word",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_by",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_half"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_rden",
+    "sources":[
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_dccm_d",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_valid",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_load",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_store",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_word",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_dword",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_d"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pic_picm_wraddr",
+    "sources":[
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_pic_wen",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_ctl_dma_mem_addr",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_r"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_wr_data_hi",
+    "sources":[
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_ld_single_ecc_error_r_ff",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_wen",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_ecc_hi_r_ff",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_hi_r_ff",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_ecc_lo_r_ff",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_lo_r_ff",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_wdata_ecc_hi",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_wdata_hi",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_ecc_any",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_data_any"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_store_data_hi_r",
+    "sources":[
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_hi_r",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_r",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_store_data_r",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_store",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_word",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_by",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_half"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_rd_addr_lo",
+    "sources":[
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_d"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pic_picm_mken",
+    "sources":[
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_pic_d",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_valid",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_store"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_ctl_dccm_dma_rdata",
+    "sources":[
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_ldst_dual_r",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_pic_r",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_dccm_r",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_hi_r",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_lo_r"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_wr_addr_lo",
+    "sources":[
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_ld_single_ecc_error_r_ff",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_wen",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_d",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_addr_any"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pic_picm_rdaddr",
+    "sources":[
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_d"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_ctl_dccm_dma_ecc_error",
+    "sources":[
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_double_ecc_error_r"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_ld_data_corr_r",
+    "sources":[
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_r",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_pic_r",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_dccm_r",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_hi_r",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_lo_r"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_rd_addr_hi",
+    "sources":[
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_end_addr_d"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_ld_single_ecc_error_r",
+    "sources":[
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_double_ecc_error_r",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_load",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_single_ecc_error_lo_r",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_raw_fwd_lo_r",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_single_ecc_error_hi_r",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_raw_fwd_hi_r"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_ctl_dccm_dma_rvalid",
+    "sources":[
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_dma",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_valid",
+      "~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_load"
+    ]
+  },
+  {
+    "class":"firrtl.EmitCircuitAnnotation",
+    "emitter":"firrtl.VerilogEmitter"
+  },
+  {
+    "class":"firrtl.transforms.BlackBoxResourceAnno",
+    "target":"lsu_dccm_ctl.gated_latch",
+    "resourceId":"/vsrc/gated_latch.sv"
+  },
+  {
+    "class":"firrtl.options.TargetDirAnnotation",
+    "directory":"."
+  },
+  {
+    "class":"firrtl.options.OutputAnnotationFileAnnotation",
+    "file":"lsu_dccm_ctl"
+  },
+  {
+    "class":"firrtl.transforms.BlackBoxTargetDirAnno",
+    "targetDir":"."
+  }
+]
\ No newline at end of file
diff --git a/lsu_dccm_ctl.fir b/lsu_dccm_ctl.fir
new file mode 100644
index 00000000..8a32abfb
--- /dev/null
+++ b/lsu_dccm_ctl.fir
@@ -0,0 +1,2435 @@
+;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
+circuit lsu_dccm_ctl : 
+  extmodule gated_latch : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch @[lib.scala 334:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 335:14]
+    clkhdr.CK <= io.clk @[lib.scala 336:18]
+    clkhdr.EN <= io.en @[lib.scala 337:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
+    
+  extmodule gated_latch_1 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr_1 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch_1 @[lib.scala 334:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 335:14]
+    clkhdr.CK <= io.clk @[lib.scala 336:18]
+    clkhdr.EN <= io.en @[lib.scala 337:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
+    
+  extmodule gated_latch_2 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr_2 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch_2 @[lib.scala 334:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 335:14]
+    clkhdr.CK <= io.clk @[lib.scala 336:18]
+    clkhdr.EN <= io.en @[lib.scala 337:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
+    
+  extmodule gated_latch_3 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr_3 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch_3 @[lib.scala 334:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 335:14]
+    clkhdr.CK <= io.clk @[lib.scala 336:18]
+    clkhdr.EN <= io.en @[lib.scala 337:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
+    
+  extmodule gated_latch_4 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr_4 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch_4 @[lib.scala 334:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 335:14]
+    clkhdr.CK <= io.clk @[lib.scala 336:18]
+    clkhdr.EN <= io.en @[lib.scala 337:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
+    
+  extmodule gated_latch_5 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr_5 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch_5 @[lib.scala 334:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 335:14]
+    clkhdr.CK <= io.clk @[lib.scala 336:18]
+    clkhdr.EN <= io.en @[lib.scala 337:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
+    
+  extmodule gated_latch_6 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr_6 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch_6 @[lib.scala 334:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 335:14]
+    clkhdr.CK <= io.clk @[lib.scala 336:18]
+    clkhdr.EN <= io.en @[lib.scala 337:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
+    
+  extmodule gated_latch_7 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr_7 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch_7 @[lib.scala 334:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 335:14]
+    clkhdr.CK <= io.clk @[lib.scala 336:18]
+    clkhdr.EN <= io.en @[lib.scala 337:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
+    
+  extmodule gated_latch_8 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr_8 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch_8 @[lib.scala 334:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 335:14]
+    clkhdr.CK <= io.clk @[lib.scala 336:18]
+    clkhdr.EN <= io.en @[lib.scala 337:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
+    
+  extmodule gated_latch_9 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr_9 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch_9 @[lib.scala 334:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 335:14]
+    clkhdr.CK <= io.clk @[lib.scala 336:18]
+    clkhdr.EN <= io.en @[lib.scala 337:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
+    
+  module lsu_dccm_ctl : 
+    input clock : Clock
+    input reset : AsyncReset
+    output io : {flip clk_override : UInt<1>, flip lsu_c2_m_clk : Clock, flip lsu_c2_r_clk : Clock, flip lsu_free_c2_clk : Clock, flip lsu_c1_r_clk : Clock, flip lsu_store_c1_r_clk : Clock, flip lsu_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_pkt_r : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip addr_in_dccm_d : UInt<1>, flip addr_in_dccm_m : UInt<1>, flip addr_in_dccm_r : UInt<1>, flip addr_in_pic_d : UInt<1>, flip addr_in_pic_m : UInt<1>, flip addr_in_pic_r : UInt<1>, flip lsu_raw_fwd_lo_r : UInt<1>, flip lsu_raw_fwd_hi_r : UInt<1>, flip lsu_commit_r : UInt<1>, flip ldst_dual_m : UInt<1>, flip ldst_dual_r : UInt<1>, flip lsu_addr_d : UInt<32>, flip lsu_addr_m : UInt<16>, flip lsu_addr_r : UInt<32>, flip end_addr_d : UInt<16>, flip end_addr_m : UInt<16>, flip end_addr_r : UInt<16>, flip stbuf_reqvld_any : UInt<1>, flip stbuf_addr_any : UInt<16>, flip stbuf_data_any : UInt<32>, flip stbuf_ecc_any : UInt<7>, flip stbuf_fwddata_hi_m : UInt<32>, flip stbuf_fwddata_lo_m : UInt<32>, flip stbuf_fwdbyteen_lo_m : UInt<4>, flip stbuf_fwdbyteen_hi_m : UInt<4>, dccm_rdata_hi_r : UInt<32>, dccm_rdata_lo_r : UInt<32>, dccm_data_ecc_hi_r : UInt<7>, dccm_data_ecc_lo_r : UInt<7>, lsu_ld_data_r : UInt<32>, lsu_ld_data_corr_r : UInt<32>, flip lsu_double_ecc_error_r : UInt<1>, flip single_ecc_error_hi_r : UInt<1>, flip single_ecc_error_lo_r : UInt<1>, flip sec_data_hi_r : UInt<32>, flip sec_data_lo_r : UInt<32>, flip sec_data_hi_r_ff : UInt<32>, flip sec_data_lo_r_ff : UInt<32>, flip sec_data_ecc_hi_r_ff : UInt<7>, flip sec_data_ecc_lo_r_ff : UInt<7>, dccm_rdata_hi_m : UInt<32>, dccm_rdata_lo_m : UInt<32>, dccm_data_ecc_hi_m : UInt<7>, dccm_data_ecc_lo_m : UInt<7>, lsu_ld_data_m : UInt<32>, flip lsu_double_ecc_error_m : UInt<1>, flip sec_data_hi_m : UInt<32>, flip sec_data_lo_m : UInt<32>, flip store_data_m : UInt<32>, flip dma_dccm_wen : UInt<1>, flip dma_pic_wen : UInt<1>, flip dma_mem_tag_m : UInt<3>, flip dma_dccm_wdata_lo : UInt<32>, flip dma_dccm_wdata_hi : UInt<32>, flip dma_dccm_wdata_ecc_hi : UInt<7>, flip dma_dccm_wdata_ecc_lo : UInt<7>, store_data_hi_r : UInt<32>, store_data_lo_r : UInt<32>, store_datafn_hi_r : UInt<32>, store_datafn_lo_r : UInt<32>, store_data_r : UInt<32>, ld_single_ecc_error_r : UInt<1>, ld_single_ecc_error_r_ff : UInt<1>, picm_mask_data_m : UInt<32>, lsu_stbuf_commit_any : UInt<1>, lsu_dccm_rden_m : UInt<1>, lsu_dccm_rden_r : UInt<1>, dma_dccm_ctl : {flip dma_mem_addr : UInt<32>, flip dma_mem_wdata : UInt<64>, dccm_dma_rvalid : UInt<1>, dccm_dma_ecc_error : UInt<1>, dccm_dma_rtag : UInt<3>, dccm_dma_rdata : UInt<64>}, flip dccm : {flip wren : UInt<1>, flip rden : UInt<1>, flip wr_addr_lo : UInt<16>, flip wr_addr_hi : UInt<16>, flip rd_addr_lo : UInt<16>, flip rd_addr_hi : UInt<16>, flip wr_data_lo : UInt<39>, flip wr_data_hi : UInt<39>, rd_data_lo : UInt<39>, rd_data_hi : UInt<39>}, lsu_pic : {picm_wren : UInt<1>, picm_rden : UInt<1>, picm_mken : UInt<1>, picm_rdaddr : UInt<32>, picm_wraddr : UInt<32>, picm_wr_data : UInt<32>, flip picm_rd_data : UInt<32>}, flip scan_mode : UInt<1>}
+    
+    node picm_rd_data_m = cat(io.lsu_pic.picm_rd_data, io.lsu_pic.picm_rd_data) @[Cat.scala 29:58]
+    node dccm_rdata_corr_r = cat(io.sec_data_hi_r, io.sec_data_lo_r) @[Cat.scala 29:58]
+    node dccm_rdata_corr_m = cat(io.sec_data_hi_m, io.sec_data_lo_m) @[Cat.scala 29:58]
+    node dccm_rdata_r = cat(io.dccm_rdata_hi_r, io.dccm_rdata_lo_r) @[Cat.scala 29:58]
+    node dccm_rdata_m = cat(io.dccm_rdata_hi_m, io.dccm_rdata_lo_m) @[Cat.scala 29:58]
+    wire lsu_rdata_r : UInt<64>
+    lsu_rdata_r <= UInt<1>("h00")
+    wire lsu_rdata_m : UInt<64>
+    lsu_rdata_m <= UInt<1>("h00")
+    wire lsu_rdata_corr_r : UInt<64>
+    lsu_rdata_corr_r <= UInt<1>("h00")
+    wire lsu_rdata_corr_m : UInt<64>
+    lsu_rdata_corr_m <= UInt<1>("h00")
+    wire stbuf_fwddata_r : UInt<64>
+    stbuf_fwddata_r <= UInt<1>("h00")
+    wire stbuf_fwdbyteen_r : UInt<64>
+    stbuf_fwdbyteen_r <= UInt<1>("h00")
+    wire picm_rd_data_r_32 : UInt<32>
+    picm_rd_data_r_32 <= UInt<1>("h00")
+    wire picm_rd_data_r : UInt<64>
+    picm_rd_data_r <= UInt<1>("h00")
+    wire lsu_ld_data_corr_m : UInt<64>
+    lsu_ld_data_corr_m <= UInt<1>("h00")
+    wire stbuf_fwddata_en : UInt<1>
+    stbuf_fwddata_en <= UInt<1>("h00")
+    wire lsu_double_ecc_error_r_ff : UInt<1>
+    lsu_double_ecc_error_r_ff <= UInt<1>("h00")
+    wire ld_single_ecc_error_hi_r_ff : UInt<1>
+    ld_single_ecc_error_hi_r_ff <= UInt<1>("h00")
+    wire ld_single_ecc_error_lo_r_ff : UInt<1>
+    ld_single_ecc_error_lo_r_ff <= UInt<1>("h00")
+    wire ld_sec_addr_hi_r_ff : UInt<16>
+    ld_sec_addr_hi_r_ff <= UInt<1>("h00")
+    wire ld_sec_addr_lo_r_ff : UInt<16>
+    ld_sec_addr_lo_r_ff <= UInt<1>("h00")
+    io.lsu_ld_data_m <= UInt<1>("h00") @[lsu_dccm_ctl.scala 121:20]
+    node _T = and(io.lsu_pkt_r.valid, io.lsu_pkt_r.bits.load) @[lsu_dccm_ctl.scala 124:62]
+    node _T_1 = and(_T, io.lsu_pkt_r.bits.dma) @[lsu_dccm_ctl.scala 124:87]
+    io.dma_dccm_ctl.dccm_dma_rvalid <= _T_1 @[lsu_dccm_ctl.scala 124:40]
+    io.dma_dccm_ctl.dccm_dma_ecc_error <= io.lsu_double_ecc_error_r @[lsu_dccm_ctl.scala 125:40]
+    node _T_2 = bits(io.ldst_dual_r, 0, 0) @[lib.scala 8:44]
+    node _T_3 = bits(lsu_rdata_corr_r, 31, 0) @[lsu_dccm_ctl.scala 126:103]
+    node _T_4 = cat(_T_3, _T_3) @[Cat.scala 29:58]
+    node _T_5 = mux(_T_2, lsu_rdata_corr_r, _T_4) @[lsu_dccm_ctl.scala 126:46]
+    io.dma_dccm_ctl.dccm_dma_rdata <= _T_5 @[lsu_dccm_ctl.scala 126:40]
+    node _T_6 = orr(io.stbuf_fwdbyteen_hi_m) @[lsu_dccm_ctl.scala 127:49]
+    node _T_7 = orr(io.stbuf_fwdbyteen_lo_m) @[lsu_dccm_ctl.scala 127:79]
+    node _T_8 = or(_T_6, _T_7) @[lsu_dccm_ctl.scala 127:53]
+    node _T_9 = or(_T_8, io.clk_override) @[lsu_dccm_ctl.scala 127:83]
+    stbuf_fwddata_en <= _T_9 @[lsu_dccm_ctl.scala 127:22]
+    node _T_10 = and(io.lsu_dccm_rden_m, io.ldst_dual_m) @[lsu_dccm_ctl.scala 129:77]
+    node _T_11 = or(_T_10, io.clk_override) @[lsu_dccm_ctl.scala 129:95]
+    node _T_12 = bits(_T_11, 0, 0) @[lib.scala 8:44]
+    node _T_13 = bits(io.scan_mode, 0, 0) @[lsu_dccm_ctl.scala 129:133]
+    inst rvclkhdr of rvclkhdr @[lib.scala 390:23]
+    rvclkhdr.clock <= clock
+    rvclkhdr.reset <= reset
+    rvclkhdr.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr.io.en <= _T_12 @[lib.scala 393:17]
+    rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg _T_14 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_12 : @[Reg.scala 28:19]
+      _T_14 <= io.dccm_rdata_hi_m @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    io.dccm_rdata_hi_r <= _T_14 @[lsu_dccm_ctl.scala 129:27]
+    node _T_15 = or(io.lsu_dccm_rden_m, io.clk_override) @[lsu_dccm_ctl.scala 130:75]
+    node _T_16 = bits(_T_15, 0, 0) @[lsu_dccm_ctl.scala 130:93]
+    node _T_17 = bits(io.scan_mode, 0, 0) @[lsu_dccm_ctl.scala 130:119]
+    inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 390:23]
+    rvclkhdr_1.clock <= clock
+    rvclkhdr_1.reset <= reset
+    rvclkhdr_1.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr_1.io.en <= _T_16 @[lib.scala 393:17]
+    rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg _T_18 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_16 : @[Reg.scala 28:19]
+      _T_18 <= io.dccm_rdata_lo_m @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    io.dccm_rdata_lo_r <= _T_18 @[lsu_dccm_ctl.scala 130:27]
+    node _T_19 = or(io.lsu_dccm_rden_m, io.clk_override) @[lsu_dccm_ctl.scala 131:78]
+    node _T_20 = bits(_T_19, 0, 0) @[lsu_dccm_ctl.scala 131:96]
+    node _T_21 = bits(io.scan_mode, 0, 0) @[lsu_dccm_ctl.scala 131:122]
+    inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 390:23]
+    rvclkhdr_2.clock <= clock
+    rvclkhdr_2.reset <= reset
+    rvclkhdr_2.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr_2.io.en <= _T_20 @[lib.scala 393:17]
+    rvclkhdr_2.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg _T_22 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_20 : @[Reg.scala 28:19]
+      _T_22 <= io.dccm_data_ecc_hi_m @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    io.dccm_data_ecc_hi_r <= _T_22 @[lsu_dccm_ctl.scala 131:27]
+    node _T_23 = or(io.lsu_dccm_rden_m, io.clk_override) @[lsu_dccm_ctl.scala 132:78]
+    node _T_24 = bits(_T_23, 0, 0) @[lsu_dccm_ctl.scala 132:96]
+    node _T_25 = bits(io.scan_mode, 0, 0) @[lsu_dccm_ctl.scala 132:122]
+    inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 390:23]
+    rvclkhdr_3.clock <= clock
+    rvclkhdr_3.reset <= reset
+    rvclkhdr_3.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr_3.io.en <= _T_24 @[lib.scala 393:17]
+    rvclkhdr_3.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg _T_26 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_24 : @[Reg.scala 28:19]
+      _T_26 <= io.dccm_data_ecc_lo_m @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    io.dccm_data_ecc_lo_r <= _T_26 @[lsu_dccm_ctl.scala 132:27]
+    node _T_27 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58]
+    reg _T_28 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_dccm_ctl.scala 133:64]
+    _T_28 <= _T_27 @[lsu_dccm_ctl.scala 133:64]
+    stbuf_fwdbyteen_r <= _T_28 @[lsu_dccm_ctl.scala 133:27]
+    node _T_29 = bits(stbuf_fwddata_en, 0, 0) @[lib.scala 8:44]
+    node _T_30 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44]
+    inst rvclkhdr_4 of rvclkhdr_4 @[lib.scala 390:23]
+    rvclkhdr_4.clock <= clock
+    rvclkhdr_4.reset <= reset
+    rvclkhdr_4.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr_4.io.en <= _T_29 @[lib.scala 393:17]
+    rvclkhdr_4.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg _T_31 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_29 : @[Reg.scala 28:19]
+      _T_31 <= io.stbuf_fwddata_hi_m @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    node _T_32 = bits(stbuf_fwddata_en, 0, 0) @[lib.scala 8:44]
+    node _T_33 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44]
+    inst rvclkhdr_5 of rvclkhdr_5 @[lib.scala 390:23]
+    rvclkhdr_5.clock <= clock
+    rvclkhdr_5.reset <= reset
+    rvclkhdr_5.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr_5.io.en <= _T_32 @[lib.scala 393:17]
+    rvclkhdr_5.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg _T_34 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_32 : @[Reg.scala 28:19]
+      _T_34 <= io.stbuf_fwddata_lo_m @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    node _T_35 = cat(_T_31, _T_34) @[Cat.scala 29:58]
+    stbuf_fwddata_r <= _T_35 @[lsu_dccm_ctl.scala 134:27]
+    node _T_36 = bits(picm_rd_data_m, 31, 0) @[lsu_dccm_ctl.scala 135:51]
+    node _T_37 = or(io.addr_in_pic_m, io.clk_override) @[lsu_dccm_ctl.scala 135:76]
+    node _T_38 = bits(_T_37, 0, 0) @[lib.scala 8:44]
+    node _T_39 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44]
+    inst rvclkhdr_6 of rvclkhdr_6 @[lib.scala 390:23]
+    rvclkhdr_6.clock <= clock
+    rvclkhdr_6.reset <= reset
+    rvclkhdr_6.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr_6.io.en <= _T_38 @[lib.scala 393:17]
+    rvclkhdr_6.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg _T_40 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_38 : @[Reg.scala 28:19]
+      _T_40 <= _T_36 @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    picm_rd_data_r_32 <= _T_40 @[lsu_dccm_ctl.scala 135:27]
+    node _T_41 = cat(picm_rd_data_r_32, picm_rd_data_r_32) @[Cat.scala 29:58]
+    picm_rd_data_r <= _T_41 @[lsu_dccm_ctl.scala 136:27]
+    reg _T_42 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_dccm_ctl.scala 137:77]
+    _T_42 <= io.dma_mem_tag_m @[lsu_dccm_ctl.scala 137:77]
+    io.dma_dccm_ctl.dccm_dma_rtag <= _T_42 @[lsu_dccm_ctl.scala 137:40]
+    node _T_43 = bits(stbuf_fwdbyteen_r, 0, 0) @[lsu_dccm_ctl.scala 138:95]
+    node _T_44 = bits(_T_43, 0, 0) @[lsu_dccm_ctl.scala 138:99]
+    node _T_45 = bits(stbuf_fwddata_r, 7, 0) @[lsu_dccm_ctl.scala 138:121]
+    node _T_46 = bits(io.addr_in_pic_r, 0, 0) @[lsu_dccm_ctl.scala 138:157]
+    node _T_47 = bits(picm_rd_data_r, 7, 0) @[lsu_dccm_ctl.scala 138:178]
+    node _T_48 = bits(io.addr_in_dccm_r, 0, 0) @[Bitwise.scala 72:15]
+    node _T_49 = mux(_T_48, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
+    node _T_50 = bits(dccm_rdata_corr_r, 7, 0) @[lsu_dccm_ctl.scala 138:238]
+    node _T_51 = and(_T_49, _T_50) @[lsu_dccm_ctl.scala 138:219]
+    node _T_52 = mux(_T_46, _T_47, _T_51) @[lsu_dccm_ctl.scala 138:139]
+    node _T_53 = mux(_T_44, _T_45, _T_52) @[lsu_dccm_ctl.scala 138:77]
+    node _T_54 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
+    node _T_55 = xor(UInt<8>("h0ff"), _T_54) @[Bitwise.scala 102:21]
+    node _T_56 = shr(_T_53, 4) @[Bitwise.scala 103:21]
+    node _T_57 = and(_T_56, _T_55) @[Bitwise.scala 103:31]
+    node _T_58 = bits(_T_53, 3, 0) @[Bitwise.scala 103:46]
+    node _T_59 = shl(_T_58, 4) @[Bitwise.scala 103:65]
+    node _T_60 = not(_T_55) @[Bitwise.scala 103:77]
+    node _T_61 = and(_T_59, _T_60) @[Bitwise.scala 103:75]
+    node _T_62 = or(_T_57, _T_61) @[Bitwise.scala 103:39]
+    node _T_63 = bits(_T_55, 5, 0) @[Bitwise.scala 102:28]
+    node _T_64 = shl(_T_63, 2) @[Bitwise.scala 102:47]
+    node _T_65 = xor(_T_55, _T_64) @[Bitwise.scala 102:21]
+    node _T_66 = shr(_T_62, 2) @[Bitwise.scala 103:21]
+    node _T_67 = and(_T_66, _T_65) @[Bitwise.scala 103:31]
+    node _T_68 = bits(_T_62, 5, 0) @[Bitwise.scala 103:46]
+    node _T_69 = shl(_T_68, 2) @[Bitwise.scala 103:65]
+    node _T_70 = not(_T_65) @[Bitwise.scala 103:77]
+    node _T_71 = and(_T_69, _T_70) @[Bitwise.scala 103:75]
+    node _T_72 = or(_T_67, _T_71) @[Bitwise.scala 103:39]
+    node _T_73 = bits(_T_65, 6, 0) @[Bitwise.scala 102:28]
+    node _T_74 = shl(_T_73, 1) @[Bitwise.scala 102:47]
+    node _T_75 = xor(_T_65, _T_74) @[Bitwise.scala 102:21]
+    node _T_76 = shr(_T_72, 1) @[Bitwise.scala 103:21]
+    node _T_77 = and(_T_76, _T_75) @[Bitwise.scala 103:31]
+    node _T_78 = bits(_T_72, 6, 0) @[Bitwise.scala 103:46]
+    node _T_79 = shl(_T_78, 1) @[Bitwise.scala 103:65]
+    node _T_80 = not(_T_75) @[Bitwise.scala 103:77]
+    node _T_81 = and(_T_79, _T_80) @[Bitwise.scala 103:75]
+    node _T_82 = or(_T_77, _T_81) @[Bitwise.scala 103:39]
+    node _T_83 = bits(stbuf_fwdbyteen_r, 1, 1) @[lsu_dccm_ctl.scala 138:95]
+    node _T_84 = bits(_T_83, 0, 0) @[lsu_dccm_ctl.scala 138:99]
+    node _T_85 = bits(stbuf_fwddata_r, 15, 8) @[lsu_dccm_ctl.scala 138:121]
+    node _T_86 = bits(io.addr_in_pic_r, 0, 0) @[lsu_dccm_ctl.scala 138:157]
+    node _T_87 = bits(picm_rd_data_r, 15, 8) @[lsu_dccm_ctl.scala 138:178]
+    node _T_88 = bits(io.addr_in_dccm_r, 0, 0) @[Bitwise.scala 72:15]
+    node _T_89 = mux(_T_88, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
+    node _T_90 = bits(dccm_rdata_corr_r, 15, 8) @[lsu_dccm_ctl.scala 138:238]
+    node _T_91 = and(_T_89, _T_90) @[lsu_dccm_ctl.scala 138:219]
+    node _T_92 = mux(_T_86, _T_87, _T_91) @[lsu_dccm_ctl.scala 138:139]
+    node _T_93 = mux(_T_84, _T_85, _T_92) @[lsu_dccm_ctl.scala 138:77]
+    node _T_94 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
+    node _T_95 = xor(UInt<8>("h0ff"), _T_94) @[Bitwise.scala 102:21]
+    node _T_96 = shr(_T_93, 4) @[Bitwise.scala 103:21]
+    node _T_97 = and(_T_96, _T_95) @[Bitwise.scala 103:31]
+    node _T_98 = bits(_T_93, 3, 0) @[Bitwise.scala 103:46]
+    node _T_99 = shl(_T_98, 4) @[Bitwise.scala 103:65]
+    node _T_100 = not(_T_95) @[Bitwise.scala 103:77]
+    node _T_101 = and(_T_99, _T_100) @[Bitwise.scala 103:75]
+    node _T_102 = or(_T_97, _T_101) @[Bitwise.scala 103:39]
+    node _T_103 = bits(_T_95, 5, 0) @[Bitwise.scala 102:28]
+    node _T_104 = shl(_T_103, 2) @[Bitwise.scala 102:47]
+    node _T_105 = xor(_T_95, _T_104) @[Bitwise.scala 102:21]
+    node _T_106 = shr(_T_102, 2) @[Bitwise.scala 103:21]
+    node _T_107 = and(_T_106, _T_105) @[Bitwise.scala 103:31]
+    node _T_108 = bits(_T_102, 5, 0) @[Bitwise.scala 103:46]
+    node _T_109 = shl(_T_108, 2) @[Bitwise.scala 103:65]
+    node _T_110 = not(_T_105) @[Bitwise.scala 103:77]
+    node _T_111 = and(_T_109, _T_110) @[Bitwise.scala 103:75]
+    node _T_112 = or(_T_107, _T_111) @[Bitwise.scala 103:39]
+    node _T_113 = bits(_T_105, 6, 0) @[Bitwise.scala 102:28]
+    node _T_114 = shl(_T_113, 1) @[Bitwise.scala 102:47]
+    node _T_115 = xor(_T_105, _T_114) @[Bitwise.scala 102:21]
+    node _T_116 = shr(_T_112, 1) @[Bitwise.scala 103:21]
+    node _T_117 = and(_T_116, _T_115) @[Bitwise.scala 103:31]
+    node _T_118 = bits(_T_112, 6, 0) @[Bitwise.scala 103:46]
+    node _T_119 = shl(_T_118, 1) @[Bitwise.scala 103:65]
+    node _T_120 = not(_T_115) @[Bitwise.scala 103:77]
+    node _T_121 = and(_T_119, _T_120) @[Bitwise.scala 103:75]
+    node _T_122 = or(_T_117, _T_121) @[Bitwise.scala 103:39]
+    node _T_123 = bits(stbuf_fwdbyteen_r, 2, 2) @[lsu_dccm_ctl.scala 138:95]
+    node _T_124 = bits(_T_123, 0, 0) @[lsu_dccm_ctl.scala 138:99]
+    node _T_125 = bits(stbuf_fwddata_r, 23, 16) @[lsu_dccm_ctl.scala 138:121]
+    node _T_126 = bits(io.addr_in_pic_r, 0, 0) @[lsu_dccm_ctl.scala 138:157]
+    node _T_127 = bits(picm_rd_data_r, 23, 16) @[lsu_dccm_ctl.scala 138:178]
+    node _T_128 = bits(io.addr_in_dccm_r, 0, 0) @[Bitwise.scala 72:15]
+    node _T_129 = mux(_T_128, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
+    node _T_130 = bits(dccm_rdata_corr_r, 23, 16) @[lsu_dccm_ctl.scala 138:238]
+    node _T_131 = and(_T_129, _T_130) @[lsu_dccm_ctl.scala 138:219]
+    node _T_132 = mux(_T_126, _T_127, _T_131) @[lsu_dccm_ctl.scala 138:139]
+    node _T_133 = mux(_T_124, _T_125, _T_132) @[lsu_dccm_ctl.scala 138:77]
+    node _T_134 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
+    node _T_135 = xor(UInt<8>("h0ff"), _T_134) @[Bitwise.scala 102:21]
+    node _T_136 = shr(_T_133, 4) @[Bitwise.scala 103:21]
+    node _T_137 = and(_T_136, _T_135) @[Bitwise.scala 103:31]
+    node _T_138 = bits(_T_133, 3, 0) @[Bitwise.scala 103:46]
+    node _T_139 = shl(_T_138, 4) @[Bitwise.scala 103:65]
+    node _T_140 = not(_T_135) @[Bitwise.scala 103:77]
+    node _T_141 = and(_T_139, _T_140) @[Bitwise.scala 103:75]
+    node _T_142 = or(_T_137, _T_141) @[Bitwise.scala 103:39]
+    node _T_143 = bits(_T_135, 5, 0) @[Bitwise.scala 102:28]
+    node _T_144 = shl(_T_143, 2) @[Bitwise.scala 102:47]
+    node _T_145 = xor(_T_135, _T_144) @[Bitwise.scala 102:21]
+    node _T_146 = shr(_T_142, 2) @[Bitwise.scala 103:21]
+    node _T_147 = and(_T_146, _T_145) @[Bitwise.scala 103:31]
+    node _T_148 = bits(_T_142, 5, 0) @[Bitwise.scala 103:46]
+    node _T_149 = shl(_T_148, 2) @[Bitwise.scala 103:65]
+    node _T_150 = not(_T_145) @[Bitwise.scala 103:77]
+    node _T_151 = and(_T_149, _T_150) @[Bitwise.scala 103:75]
+    node _T_152 = or(_T_147, _T_151) @[Bitwise.scala 103:39]
+    node _T_153 = bits(_T_145, 6, 0) @[Bitwise.scala 102:28]
+    node _T_154 = shl(_T_153, 1) @[Bitwise.scala 102:47]
+    node _T_155 = xor(_T_145, _T_154) @[Bitwise.scala 102:21]
+    node _T_156 = shr(_T_152, 1) @[Bitwise.scala 103:21]
+    node _T_157 = and(_T_156, _T_155) @[Bitwise.scala 103:31]
+    node _T_158 = bits(_T_152, 6, 0) @[Bitwise.scala 103:46]
+    node _T_159 = shl(_T_158, 1) @[Bitwise.scala 103:65]
+    node _T_160 = not(_T_155) @[Bitwise.scala 103:77]
+    node _T_161 = and(_T_159, _T_160) @[Bitwise.scala 103:75]
+    node _T_162 = or(_T_157, _T_161) @[Bitwise.scala 103:39]
+    node _T_163 = bits(stbuf_fwdbyteen_r, 3, 3) @[lsu_dccm_ctl.scala 138:95]
+    node _T_164 = bits(_T_163, 0, 0) @[lsu_dccm_ctl.scala 138:99]
+    node _T_165 = bits(stbuf_fwddata_r, 31, 24) @[lsu_dccm_ctl.scala 138:121]
+    node _T_166 = bits(io.addr_in_pic_r, 0, 0) @[lsu_dccm_ctl.scala 138:157]
+    node _T_167 = bits(picm_rd_data_r, 31, 24) @[lsu_dccm_ctl.scala 138:178]
+    node _T_168 = bits(io.addr_in_dccm_r, 0, 0) @[Bitwise.scala 72:15]
+    node _T_169 = mux(_T_168, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
+    node _T_170 = bits(dccm_rdata_corr_r, 31, 24) @[lsu_dccm_ctl.scala 138:238]
+    node _T_171 = and(_T_169, _T_170) @[lsu_dccm_ctl.scala 138:219]
+    node _T_172 = mux(_T_166, _T_167, _T_171) @[lsu_dccm_ctl.scala 138:139]
+    node _T_173 = mux(_T_164, _T_165, _T_172) @[lsu_dccm_ctl.scala 138:77]
+    node _T_174 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
+    node _T_175 = xor(UInt<8>("h0ff"), _T_174) @[Bitwise.scala 102:21]
+    node _T_176 = shr(_T_173, 4) @[Bitwise.scala 103:21]
+    node _T_177 = and(_T_176, _T_175) @[Bitwise.scala 103:31]
+    node _T_178 = bits(_T_173, 3, 0) @[Bitwise.scala 103:46]
+    node _T_179 = shl(_T_178, 4) @[Bitwise.scala 103:65]
+    node _T_180 = not(_T_175) @[Bitwise.scala 103:77]
+    node _T_181 = and(_T_179, _T_180) @[Bitwise.scala 103:75]
+    node _T_182 = or(_T_177, _T_181) @[Bitwise.scala 103:39]
+    node _T_183 = bits(_T_175, 5, 0) @[Bitwise.scala 102:28]
+    node _T_184 = shl(_T_183, 2) @[Bitwise.scala 102:47]
+    node _T_185 = xor(_T_175, _T_184) @[Bitwise.scala 102:21]
+    node _T_186 = shr(_T_182, 2) @[Bitwise.scala 103:21]
+    node _T_187 = and(_T_186, _T_185) @[Bitwise.scala 103:31]
+    node _T_188 = bits(_T_182, 5, 0) @[Bitwise.scala 103:46]
+    node _T_189 = shl(_T_188, 2) @[Bitwise.scala 103:65]
+    node _T_190 = not(_T_185) @[Bitwise.scala 103:77]
+    node _T_191 = and(_T_189, _T_190) @[Bitwise.scala 103:75]
+    node _T_192 = or(_T_187, _T_191) @[Bitwise.scala 103:39]
+    node _T_193 = bits(_T_185, 6, 0) @[Bitwise.scala 102:28]
+    node _T_194 = shl(_T_193, 1) @[Bitwise.scala 102:47]
+    node _T_195 = xor(_T_185, _T_194) @[Bitwise.scala 102:21]
+    node _T_196 = shr(_T_192, 1) @[Bitwise.scala 103:21]
+    node _T_197 = and(_T_196, _T_195) @[Bitwise.scala 103:31]
+    node _T_198 = bits(_T_192, 6, 0) @[Bitwise.scala 103:46]
+    node _T_199 = shl(_T_198, 1) @[Bitwise.scala 103:65]
+    node _T_200 = not(_T_195) @[Bitwise.scala 103:77]
+    node _T_201 = and(_T_199, _T_200) @[Bitwise.scala 103:75]
+    node _T_202 = or(_T_197, _T_201) @[Bitwise.scala 103:39]
+    node _T_203 = bits(stbuf_fwdbyteen_r, 4, 4) @[lsu_dccm_ctl.scala 138:95]
+    node _T_204 = bits(_T_203, 0, 0) @[lsu_dccm_ctl.scala 138:99]
+    node _T_205 = bits(stbuf_fwddata_r, 39, 32) @[lsu_dccm_ctl.scala 138:121]
+    node _T_206 = bits(io.addr_in_pic_r, 0, 0) @[lsu_dccm_ctl.scala 138:157]
+    node _T_207 = bits(picm_rd_data_r, 39, 32) @[lsu_dccm_ctl.scala 138:178]
+    node _T_208 = bits(io.addr_in_dccm_r, 0, 0) @[Bitwise.scala 72:15]
+    node _T_209 = mux(_T_208, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
+    node _T_210 = bits(dccm_rdata_corr_r, 39, 32) @[lsu_dccm_ctl.scala 138:238]
+    node _T_211 = and(_T_209, _T_210) @[lsu_dccm_ctl.scala 138:219]
+    node _T_212 = mux(_T_206, _T_207, _T_211) @[lsu_dccm_ctl.scala 138:139]
+    node _T_213 = mux(_T_204, _T_205, _T_212) @[lsu_dccm_ctl.scala 138:77]
+    node _T_214 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
+    node _T_215 = xor(UInt<8>("h0ff"), _T_214) @[Bitwise.scala 102:21]
+    node _T_216 = shr(_T_213, 4) @[Bitwise.scala 103:21]
+    node _T_217 = and(_T_216, _T_215) @[Bitwise.scala 103:31]
+    node _T_218 = bits(_T_213, 3, 0) @[Bitwise.scala 103:46]
+    node _T_219 = shl(_T_218, 4) @[Bitwise.scala 103:65]
+    node _T_220 = not(_T_215) @[Bitwise.scala 103:77]
+    node _T_221 = and(_T_219, _T_220) @[Bitwise.scala 103:75]
+    node _T_222 = or(_T_217, _T_221) @[Bitwise.scala 103:39]
+    node _T_223 = bits(_T_215, 5, 0) @[Bitwise.scala 102:28]
+    node _T_224 = shl(_T_223, 2) @[Bitwise.scala 102:47]
+    node _T_225 = xor(_T_215, _T_224) @[Bitwise.scala 102:21]
+    node _T_226 = shr(_T_222, 2) @[Bitwise.scala 103:21]
+    node _T_227 = and(_T_226, _T_225) @[Bitwise.scala 103:31]
+    node _T_228 = bits(_T_222, 5, 0) @[Bitwise.scala 103:46]
+    node _T_229 = shl(_T_228, 2) @[Bitwise.scala 103:65]
+    node _T_230 = not(_T_225) @[Bitwise.scala 103:77]
+    node _T_231 = and(_T_229, _T_230) @[Bitwise.scala 103:75]
+    node _T_232 = or(_T_227, _T_231) @[Bitwise.scala 103:39]
+    node _T_233 = bits(_T_225, 6, 0) @[Bitwise.scala 102:28]
+    node _T_234 = shl(_T_233, 1) @[Bitwise.scala 102:47]
+    node _T_235 = xor(_T_225, _T_234) @[Bitwise.scala 102:21]
+    node _T_236 = shr(_T_232, 1) @[Bitwise.scala 103:21]
+    node _T_237 = and(_T_236, _T_235) @[Bitwise.scala 103:31]
+    node _T_238 = bits(_T_232, 6, 0) @[Bitwise.scala 103:46]
+    node _T_239 = shl(_T_238, 1) @[Bitwise.scala 103:65]
+    node _T_240 = not(_T_235) @[Bitwise.scala 103:77]
+    node _T_241 = and(_T_239, _T_240) @[Bitwise.scala 103:75]
+    node _T_242 = or(_T_237, _T_241) @[Bitwise.scala 103:39]
+    node _T_243 = bits(stbuf_fwdbyteen_r, 5, 5) @[lsu_dccm_ctl.scala 138:95]
+    node _T_244 = bits(_T_243, 0, 0) @[lsu_dccm_ctl.scala 138:99]
+    node _T_245 = bits(stbuf_fwddata_r, 47, 40) @[lsu_dccm_ctl.scala 138:121]
+    node _T_246 = bits(io.addr_in_pic_r, 0, 0) @[lsu_dccm_ctl.scala 138:157]
+    node _T_247 = bits(picm_rd_data_r, 47, 40) @[lsu_dccm_ctl.scala 138:178]
+    node _T_248 = bits(io.addr_in_dccm_r, 0, 0) @[Bitwise.scala 72:15]
+    node _T_249 = mux(_T_248, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
+    node _T_250 = bits(dccm_rdata_corr_r, 47, 40) @[lsu_dccm_ctl.scala 138:238]
+    node _T_251 = and(_T_249, _T_250) @[lsu_dccm_ctl.scala 138:219]
+    node _T_252 = mux(_T_246, _T_247, _T_251) @[lsu_dccm_ctl.scala 138:139]
+    node _T_253 = mux(_T_244, _T_245, _T_252) @[lsu_dccm_ctl.scala 138:77]
+    node _T_254 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
+    node _T_255 = xor(UInt<8>("h0ff"), _T_254) @[Bitwise.scala 102:21]
+    node _T_256 = shr(_T_253, 4) @[Bitwise.scala 103:21]
+    node _T_257 = and(_T_256, _T_255) @[Bitwise.scala 103:31]
+    node _T_258 = bits(_T_253, 3, 0) @[Bitwise.scala 103:46]
+    node _T_259 = shl(_T_258, 4) @[Bitwise.scala 103:65]
+    node _T_260 = not(_T_255) @[Bitwise.scala 103:77]
+    node _T_261 = and(_T_259, _T_260) @[Bitwise.scala 103:75]
+    node _T_262 = or(_T_257, _T_261) @[Bitwise.scala 103:39]
+    node _T_263 = bits(_T_255, 5, 0) @[Bitwise.scala 102:28]
+    node _T_264 = shl(_T_263, 2) @[Bitwise.scala 102:47]
+    node _T_265 = xor(_T_255, _T_264) @[Bitwise.scala 102:21]
+    node _T_266 = shr(_T_262, 2) @[Bitwise.scala 103:21]
+    node _T_267 = and(_T_266, _T_265) @[Bitwise.scala 103:31]
+    node _T_268 = bits(_T_262, 5, 0) @[Bitwise.scala 103:46]
+    node _T_269 = shl(_T_268, 2) @[Bitwise.scala 103:65]
+    node _T_270 = not(_T_265) @[Bitwise.scala 103:77]
+    node _T_271 = and(_T_269, _T_270) @[Bitwise.scala 103:75]
+    node _T_272 = or(_T_267, _T_271) @[Bitwise.scala 103:39]
+    node _T_273 = bits(_T_265, 6, 0) @[Bitwise.scala 102:28]
+    node _T_274 = shl(_T_273, 1) @[Bitwise.scala 102:47]
+    node _T_275 = xor(_T_265, _T_274) @[Bitwise.scala 102:21]
+    node _T_276 = shr(_T_272, 1) @[Bitwise.scala 103:21]
+    node _T_277 = and(_T_276, _T_275) @[Bitwise.scala 103:31]
+    node _T_278 = bits(_T_272, 6, 0) @[Bitwise.scala 103:46]
+    node _T_279 = shl(_T_278, 1) @[Bitwise.scala 103:65]
+    node _T_280 = not(_T_275) @[Bitwise.scala 103:77]
+    node _T_281 = and(_T_279, _T_280) @[Bitwise.scala 103:75]
+    node _T_282 = or(_T_277, _T_281) @[Bitwise.scala 103:39]
+    node _T_283 = bits(stbuf_fwdbyteen_r, 6, 6) @[lsu_dccm_ctl.scala 138:95]
+    node _T_284 = bits(_T_283, 0, 0) @[lsu_dccm_ctl.scala 138:99]
+    node _T_285 = bits(stbuf_fwddata_r, 55, 48) @[lsu_dccm_ctl.scala 138:121]
+    node _T_286 = bits(io.addr_in_pic_r, 0, 0) @[lsu_dccm_ctl.scala 138:157]
+    node _T_287 = bits(picm_rd_data_r, 55, 48) @[lsu_dccm_ctl.scala 138:178]
+    node _T_288 = bits(io.addr_in_dccm_r, 0, 0) @[Bitwise.scala 72:15]
+    node _T_289 = mux(_T_288, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
+    node _T_290 = bits(dccm_rdata_corr_r, 55, 48) @[lsu_dccm_ctl.scala 138:238]
+    node _T_291 = and(_T_289, _T_290) @[lsu_dccm_ctl.scala 138:219]
+    node _T_292 = mux(_T_286, _T_287, _T_291) @[lsu_dccm_ctl.scala 138:139]
+    node _T_293 = mux(_T_284, _T_285, _T_292) @[lsu_dccm_ctl.scala 138:77]
+    node _T_294 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
+    node _T_295 = xor(UInt<8>("h0ff"), _T_294) @[Bitwise.scala 102:21]
+    node _T_296 = shr(_T_293, 4) @[Bitwise.scala 103:21]
+    node _T_297 = and(_T_296, _T_295) @[Bitwise.scala 103:31]
+    node _T_298 = bits(_T_293, 3, 0) @[Bitwise.scala 103:46]
+    node _T_299 = shl(_T_298, 4) @[Bitwise.scala 103:65]
+    node _T_300 = not(_T_295) @[Bitwise.scala 103:77]
+    node _T_301 = and(_T_299, _T_300) @[Bitwise.scala 103:75]
+    node _T_302 = or(_T_297, _T_301) @[Bitwise.scala 103:39]
+    node _T_303 = bits(_T_295, 5, 0) @[Bitwise.scala 102:28]
+    node _T_304 = shl(_T_303, 2) @[Bitwise.scala 102:47]
+    node _T_305 = xor(_T_295, _T_304) @[Bitwise.scala 102:21]
+    node _T_306 = shr(_T_302, 2) @[Bitwise.scala 103:21]
+    node _T_307 = and(_T_306, _T_305) @[Bitwise.scala 103:31]
+    node _T_308 = bits(_T_302, 5, 0) @[Bitwise.scala 103:46]
+    node _T_309 = shl(_T_308, 2) @[Bitwise.scala 103:65]
+    node _T_310 = not(_T_305) @[Bitwise.scala 103:77]
+    node _T_311 = and(_T_309, _T_310) @[Bitwise.scala 103:75]
+    node _T_312 = or(_T_307, _T_311) @[Bitwise.scala 103:39]
+    node _T_313 = bits(_T_305, 6, 0) @[Bitwise.scala 102:28]
+    node _T_314 = shl(_T_313, 1) @[Bitwise.scala 102:47]
+    node _T_315 = xor(_T_305, _T_314) @[Bitwise.scala 102:21]
+    node _T_316 = shr(_T_312, 1) @[Bitwise.scala 103:21]
+    node _T_317 = and(_T_316, _T_315) @[Bitwise.scala 103:31]
+    node _T_318 = bits(_T_312, 6, 0) @[Bitwise.scala 103:46]
+    node _T_319 = shl(_T_318, 1) @[Bitwise.scala 103:65]
+    node _T_320 = not(_T_315) @[Bitwise.scala 103:77]
+    node _T_321 = and(_T_319, _T_320) @[Bitwise.scala 103:75]
+    node _T_322 = or(_T_317, _T_321) @[Bitwise.scala 103:39]
+    node _T_323 = bits(stbuf_fwdbyteen_r, 7, 7) @[lsu_dccm_ctl.scala 138:95]
+    node _T_324 = bits(_T_323, 0, 0) @[lsu_dccm_ctl.scala 138:99]
+    node _T_325 = bits(stbuf_fwddata_r, 63, 56) @[lsu_dccm_ctl.scala 138:121]
+    node _T_326 = bits(io.addr_in_pic_r, 0, 0) @[lsu_dccm_ctl.scala 138:157]
+    node _T_327 = bits(picm_rd_data_r, 63, 56) @[lsu_dccm_ctl.scala 138:178]
+    node _T_328 = bits(io.addr_in_dccm_r, 0, 0) @[Bitwise.scala 72:15]
+    node _T_329 = mux(_T_328, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
+    node _T_330 = bits(dccm_rdata_corr_r, 63, 56) @[lsu_dccm_ctl.scala 138:238]
+    node _T_331 = and(_T_329, _T_330) @[lsu_dccm_ctl.scala 138:219]
+    node _T_332 = mux(_T_326, _T_327, _T_331) @[lsu_dccm_ctl.scala 138:139]
+    node _T_333 = mux(_T_324, _T_325, _T_332) @[lsu_dccm_ctl.scala 138:77]
+    node _T_334 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
+    node _T_335 = xor(UInt<8>("h0ff"), _T_334) @[Bitwise.scala 102:21]
+    node _T_336 = shr(_T_333, 4) @[Bitwise.scala 103:21]
+    node _T_337 = and(_T_336, _T_335) @[Bitwise.scala 103:31]
+    node _T_338 = bits(_T_333, 3, 0) @[Bitwise.scala 103:46]
+    node _T_339 = shl(_T_338, 4) @[Bitwise.scala 103:65]
+    node _T_340 = not(_T_335) @[Bitwise.scala 103:77]
+    node _T_341 = and(_T_339, _T_340) @[Bitwise.scala 103:75]
+    node _T_342 = or(_T_337, _T_341) @[Bitwise.scala 103:39]
+    node _T_343 = bits(_T_335, 5, 0) @[Bitwise.scala 102:28]
+    node _T_344 = shl(_T_343, 2) @[Bitwise.scala 102:47]
+    node _T_345 = xor(_T_335, _T_344) @[Bitwise.scala 102:21]
+    node _T_346 = shr(_T_342, 2) @[Bitwise.scala 103:21]
+    node _T_347 = and(_T_346, _T_345) @[Bitwise.scala 103:31]
+    node _T_348 = bits(_T_342, 5, 0) @[Bitwise.scala 103:46]
+    node _T_349 = shl(_T_348, 2) @[Bitwise.scala 103:65]
+    node _T_350 = not(_T_345) @[Bitwise.scala 103:77]
+    node _T_351 = and(_T_349, _T_350) @[Bitwise.scala 103:75]
+    node _T_352 = or(_T_347, _T_351) @[Bitwise.scala 103:39]
+    node _T_353 = bits(_T_345, 6, 0) @[Bitwise.scala 102:28]
+    node _T_354 = shl(_T_353, 1) @[Bitwise.scala 102:47]
+    node _T_355 = xor(_T_345, _T_354) @[Bitwise.scala 102:21]
+    node _T_356 = shr(_T_352, 1) @[Bitwise.scala 103:21]
+    node _T_357 = and(_T_356, _T_355) @[Bitwise.scala 103:31]
+    node _T_358 = bits(_T_352, 6, 0) @[Bitwise.scala 103:46]
+    node _T_359 = shl(_T_358, 1) @[Bitwise.scala 103:65]
+    node _T_360 = not(_T_355) @[Bitwise.scala 103:77]
+    node _T_361 = and(_T_359, _T_360) @[Bitwise.scala 103:75]
+    node _T_362 = or(_T_357, _T_361) @[Bitwise.scala 103:39]
+    wire _T_363 : UInt<8>[8] @[lsu_dccm_ctl.scala 138:61]
+    _T_363[0] <= _T_82 @[lsu_dccm_ctl.scala 138:61]
+    _T_363[1] <= _T_122 @[lsu_dccm_ctl.scala 138:61]
+    _T_363[2] <= _T_162 @[lsu_dccm_ctl.scala 138:61]
+    _T_363[3] <= _T_202 @[lsu_dccm_ctl.scala 138:61]
+    _T_363[4] <= _T_242 @[lsu_dccm_ctl.scala 138:61]
+    _T_363[5] <= _T_282 @[lsu_dccm_ctl.scala 138:61]
+    _T_363[6] <= _T_322 @[lsu_dccm_ctl.scala 138:61]
+    _T_363[7] <= _T_362 @[lsu_dccm_ctl.scala 138:61]
+    node _T_364 = cat(_T_363[6], _T_363[7]) @[Cat.scala 29:58]
+    node _T_365 = cat(_T_363[4], _T_363[5]) @[Cat.scala 29:58]
+    node _T_366 = cat(_T_365, _T_364) @[Cat.scala 29:58]
+    node _T_367 = cat(_T_363[2], _T_363[3]) @[Cat.scala 29:58]
+    node _T_368 = cat(_T_363[0], _T_363[1]) @[Cat.scala 29:58]
+    node _T_369 = cat(_T_368, _T_367) @[Cat.scala 29:58]
+    node _T_370 = cat(_T_369, _T_366) @[Cat.scala 29:58]
+    node _T_371 = shl(UInt<32>("h0ffffffff"), 32) @[Bitwise.scala 102:47]
+    node _T_372 = xor(UInt<64>("h0ffffffffffffffff"), _T_371) @[Bitwise.scala 102:21]
+    node _T_373 = shr(_T_370, 32) @[Bitwise.scala 103:21]
+    node _T_374 = and(_T_373, _T_372) @[Bitwise.scala 103:31]
+    node _T_375 = bits(_T_370, 31, 0) @[Bitwise.scala 103:46]
+    node _T_376 = shl(_T_375, 32) @[Bitwise.scala 103:65]
+    node _T_377 = not(_T_372) @[Bitwise.scala 103:77]
+    node _T_378 = and(_T_376, _T_377) @[Bitwise.scala 103:75]
+    node _T_379 = or(_T_374, _T_378) @[Bitwise.scala 103:39]
+    node _T_380 = bits(_T_372, 47, 0) @[Bitwise.scala 102:28]
+    node _T_381 = shl(_T_380, 16) @[Bitwise.scala 102:47]
+    node _T_382 = xor(_T_372, _T_381) @[Bitwise.scala 102:21]
+    node _T_383 = shr(_T_379, 16) @[Bitwise.scala 103:21]
+    node _T_384 = and(_T_383, _T_382) @[Bitwise.scala 103:31]
+    node _T_385 = bits(_T_379, 47, 0) @[Bitwise.scala 103:46]
+    node _T_386 = shl(_T_385, 16) @[Bitwise.scala 103:65]
+    node _T_387 = not(_T_382) @[Bitwise.scala 103:77]
+    node _T_388 = and(_T_386, _T_387) @[Bitwise.scala 103:75]
+    node _T_389 = or(_T_384, _T_388) @[Bitwise.scala 103:39]
+    node _T_390 = bits(_T_382, 55, 0) @[Bitwise.scala 102:28]
+    node _T_391 = shl(_T_390, 8) @[Bitwise.scala 102:47]
+    node _T_392 = xor(_T_382, _T_391) @[Bitwise.scala 102:21]
+    node _T_393 = shr(_T_389, 8) @[Bitwise.scala 103:21]
+    node _T_394 = and(_T_393, _T_392) @[Bitwise.scala 103:31]
+    node _T_395 = bits(_T_389, 55, 0) @[Bitwise.scala 103:46]
+    node _T_396 = shl(_T_395, 8) @[Bitwise.scala 103:65]
+    node _T_397 = not(_T_392) @[Bitwise.scala 103:77]
+    node _T_398 = and(_T_396, _T_397) @[Bitwise.scala 103:75]
+    node _T_399 = or(_T_394, _T_398) @[Bitwise.scala 103:39]
+    node _T_400 = bits(_T_392, 59, 0) @[Bitwise.scala 102:28]
+    node _T_401 = shl(_T_400, 4) @[Bitwise.scala 102:47]
+    node _T_402 = xor(_T_392, _T_401) @[Bitwise.scala 102:21]
+    node _T_403 = shr(_T_399, 4) @[Bitwise.scala 103:21]
+    node _T_404 = and(_T_403, _T_402) @[Bitwise.scala 103:31]
+    node _T_405 = bits(_T_399, 59, 0) @[Bitwise.scala 103:46]
+    node _T_406 = shl(_T_405, 4) @[Bitwise.scala 103:65]
+    node _T_407 = not(_T_402) @[Bitwise.scala 103:77]
+    node _T_408 = and(_T_406, _T_407) @[Bitwise.scala 103:75]
+    node _T_409 = or(_T_404, _T_408) @[Bitwise.scala 103:39]
+    node _T_410 = bits(_T_402, 61, 0) @[Bitwise.scala 102:28]
+    node _T_411 = shl(_T_410, 2) @[Bitwise.scala 102:47]
+    node _T_412 = xor(_T_402, _T_411) @[Bitwise.scala 102:21]
+    node _T_413 = shr(_T_409, 2) @[Bitwise.scala 103:21]
+    node _T_414 = and(_T_413, _T_412) @[Bitwise.scala 103:31]
+    node _T_415 = bits(_T_409, 61, 0) @[Bitwise.scala 103:46]
+    node _T_416 = shl(_T_415, 2) @[Bitwise.scala 103:65]
+    node _T_417 = not(_T_412) @[Bitwise.scala 103:77]
+    node _T_418 = and(_T_416, _T_417) @[Bitwise.scala 103:75]
+    node _T_419 = or(_T_414, _T_418) @[Bitwise.scala 103:39]
+    node _T_420 = bits(_T_412, 62, 0) @[Bitwise.scala 102:28]
+    node _T_421 = shl(_T_420, 1) @[Bitwise.scala 102:47]
+    node _T_422 = xor(_T_412, _T_421) @[Bitwise.scala 102:21]
+    node _T_423 = shr(_T_419, 1) @[Bitwise.scala 103:21]
+    node _T_424 = and(_T_423, _T_422) @[Bitwise.scala 103:31]
+    node _T_425 = bits(_T_419, 62, 0) @[Bitwise.scala 103:46]
+    node _T_426 = shl(_T_425, 1) @[Bitwise.scala 103:65]
+    node _T_427 = not(_T_422) @[Bitwise.scala 103:77]
+    node _T_428 = and(_T_426, _T_427) @[Bitwise.scala 103:75]
+    node _T_429 = or(_T_424, _T_428) @[Bitwise.scala 103:39]
+    lsu_rdata_corr_r <= _T_429 @[lsu_dccm_ctl.scala 138:27]
+    node _T_430 = bits(stbuf_fwdbyteen_r, 0, 0) @[lsu_dccm_ctl.scala 139:95]
+    node _T_431 = bits(_T_430, 0, 0) @[lsu_dccm_ctl.scala 139:99]
+    node _T_432 = bits(stbuf_fwddata_r, 7, 0) @[lsu_dccm_ctl.scala 139:121]
+    node _T_433 = bits(io.addr_in_pic_r, 0, 0) @[lsu_dccm_ctl.scala 139:157]
+    node _T_434 = bits(picm_rd_data_r, 7, 0) @[lsu_dccm_ctl.scala 139:178]
+    node _T_435 = bits(io.addr_in_dccm_r, 0, 0) @[Bitwise.scala 72:15]
+    node _T_436 = mux(_T_435, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
+    node _T_437 = bits(dccm_rdata_r, 7, 0) @[lsu_dccm_ctl.scala 139:233]
+    node _T_438 = and(_T_436, _T_437) @[lsu_dccm_ctl.scala 139:219]
+    node _T_439 = mux(_T_433, _T_434, _T_438) @[lsu_dccm_ctl.scala 139:139]
+    node _T_440 = mux(_T_431, _T_432, _T_439) @[lsu_dccm_ctl.scala 139:77]
+    node _T_441 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
+    node _T_442 = xor(UInt<8>("h0ff"), _T_441) @[Bitwise.scala 102:21]
+    node _T_443 = shr(_T_440, 4) @[Bitwise.scala 103:21]
+    node _T_444 = and(_T_443, _T_442) @[Bitwise.scala 103:31]
+    node _T_445 = bits(_T_440, 3, 0) @[Bitwise.scala 103:46]
+    node _T_446 = shl(_T_445, 4) @[Bitwise.scala 103:65]
+    node _T_447 = not(_T_442) @[Bitwise.scala 103:77]
+    node _T_448 = and(_T_446, _T_447) @[Bitwise.scala 103:75]
+    node _T_449 = or(_T_444, _T_448) @[Bitwise.scala 103:39]
+    node _T_450 = bits(_T_442, 5, 0) @[Bitwise.scala 102:28]
+    node _T_451 = shl(_T_450, 2) @[Bitwise.scala 102:47]
+    node _T_452 = xor(_T_442, _T_451) @[Bitwise.scala 102:21]
+    node _T_453 = shr(_T_449, 2) @[Bitwise.scala 103:21]
+    node _T_454 = and(_T_453, _T_452) @[Bitwise.scala 103:31]
+    node _T_455 = bits(_T_449, 5, 0) @[Bitwise.scala 103:46]
+    node _T_456 = shl(_T_455, 2) @[Bitwise.scala 103:65]
+    node _T_457 = not(_T_452) @[Bitwise.scala 103:77]
+    node _T_458 = and(_T_456, _T_457) @[Bitwise.scala 103:75]
+    node _T_459 = or(_T_454, _T_458) @[Bitwise.scala 103:39]
+    node _T_460 = bits(_T_452, 6, 0) @[Bitwise.scala 102:28]
+    node _T_461 = shl(_T_460, 1) @[Bitwise.scala 102:47]
+    node _T_462 = xor(_T_452, _T_461) @[Bitwise.scala 102:21]
+    node _T_463 = shr(_T_459, 1) @[Bitwise.scala 103:21]
+    node _T_464 = and(_T_463, _T_462) @[Bitwise.scala 103:31]
+    node _T_465 = bits(_T_459, 6, 0) @[Bitwise.scala 103:46]
+    node _T_466 = shl(_T_465, 1) @[Bitwise.scala 103:65]
+    node _T_467 = not(_T_462) @[Bitwise.scala 103:77]
+    node _T_468 = and(_T_466, _T_467) @[Bitwise.scala 103:75]
+    node _T_469 = or(_T_464, _T_468) @[Bitwise.scala 103:39]
+    node _T_470 = bits(stbuf_fwdbyteen_r, 1, 1) @[lsu_dccm_ctl.scala 139:95]
+    node _T_471 = bits(_T_470, 0, 0) @[lsu_dccm_ctl.scala 139:99]
+    node _T_472 = bits(stbuf_fwddata_r, 15, 8) @[lsu_dccm_ctl.scala 139:121]
+    node _T_473 = bits(io.addr_in_pic_r, 0, 0) @[lsu_dccm_ctl.scala 139:157]
+    node _T_474 = bits(picm_rd_data_r, 15, 8) @[lsu_dccm_ctl.scala 139:178]
+    node _T_475 = bits(io.addr_in_dccm_r, 0, 0) @[Bitwise.scala 72:15]
+    node _T_476 = mux(_T_475, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
+    node _T_477 = bits(dccm_rdata_r, 15, 8) @[lsu_dccm_ctl.scala 139:233]
+    node _T_478 = and(_T_476, _T_477) @[lsu_dccm_ctl.scala 139:219]
+    node _T_479 = mux(_T_473, _T_474, _T_478) @[lsu_dccm_ctl.scala 139:139]
+    node _T_480 = mux(_T_471, _T_472, _T_479) @[lsu_dccm_ctl.scala 139:77]
+    node _T_481 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
+    node _T_482 = xor(UInt<8>("h0ff"), _T_481) @[Bitwise.scala 102:21]
+    node _T_483 = shr(_T_480, 4) @[Bitwise.scala 103:21]
+    node _T_484 = and(_T_483, _T_482) @[Bitwise.scala 103:31]
+    node _T_485 = bits(_T_480, 3, 0) @[Bitwise.scala 103:46]
+    node _T_486 = shl(_T_485, 4) @[Bitwise.scala 103:65]
+    node _T_487 = not(_T_482) @[Bitwise.scala 103:77]
+    node _T_488 = and(_T_486, _T_487) @[Bitwise.scala 103:75]
+    node _T_489 = or(_T_484, _T_488) @[Bitwise.scala 103:39]
+    node _T_490 = bits(_T_482, 5, 0) @[Bitwise.scala 102:28]
+    node _T_491 = shl(_T_490, 2) @[Bitwise.scala 102:47]
+    node _T_492 = xor(_T_482, _T_491) @[Bitwise.scala 102:21]
+    node _T_493 = shr(_T_489, 2) @[Bitwise.scala 103:21]
+    node _T_494 = and(_T_493, _T_492) @[Bitwise.scala 103:31]
+    node _T_495 = bits(_T_489, 5, 0) @[Bitwise.scala 103:46]
+    node _T_496 = shl(_T_495, 2) @[Bitwise.scala 103:65]
+    node _T_497 = not(_T_492) @[Bitwise.scala 103:77]
+    node _T_498 = and(_T_496, _T_497) @[Bitwise.scala 103:75]
+    node _T_499 = or(_T_494, _T_498) @[Bitwise.scala 103:39]
+    node _T_500 = bits(_T_492, 6, 0) @[Bitwise.scala 102:28]
+    node _T_501 = shl(_T_500, 1) @[Bitwise.scala 102:47]
+    node _T_502 = xor(_T_492, _T_501) @[Bitwise.scala 102:21]
+    node _T_503 = shr(_T_499, 1) @[Bitwise.scala 103:21]
+    node _T_504 = and(_T_503, _T_502) @[Bitwise.scala 103:31]
+    node _T_505 = bits(_T_499, 6, 0) @[Bitwise.scala 103:46]
+    node _T_506 = shl(_T_505, 1) @[Bitwise.scala 103:65]
+    node _T_507 = not(_T_502) @[Bitwise.scala 103:77]
+    node _T_508 = and(_T_506, _T_507) @[Bitwise.scala 103:75]
+    node _T_509 = or(_T_504, _T_508) @[Bitwise.scala 103:39]
+    node _T_510 = bits(stbuf_fwdbyteen_r, 2, 2) @[lsu_dccm_ctl.scala 139:95]
+    node _T_511 = bits(_T_510, 0, 0) @[lsu_dccm_ctl.scala 139:99]
+    node _T_512 = bits(stbuf_fwddata_r, 23, 16) @[lsu_dccm_ctl.scala 139:121]
+    node _T_513 = bits(io.addr_in_pic_r, 0, 0) @[lsu_dccm_ctl.scala 139:157]
+    node _T_514 = bits(picm_rd_data_r, 23, 16) @[lsu_dccm_ctl.scala 139:178]
+    node _T_515 = bits(io.addr_in_dccm_r, 0, 0) @[Bitwise.scala 72:15]
+    node _T_516 = mux(_T_515, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
+    node _T_517 = bits(dccm_rdata_r, 23, 16) @[lsu_dccm_ctl.scala 139:233]
+    node _T_518 = and(_T_516, _T_517) @[lsu_dccm_ctl.scala 139:219]
+    node _T_519 = mux(_T_513, _T_514, _T_518) @[lsu_dccm_ctl.scala 139:139]
+    node _T_520 = mux(_T_511, _T_512, _T_519) @[lsu_dccm_ctl.scala 139:77]
+    node _T_521 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
+    node _T_522 = xor(UInt<8>("h0ff"), _T_521) @[Bitwise.scala 102:21]
+    node _T_523 = shr(_T_520, 4) @[Bitwise.scala 103:21]
+    node _T_524 = and(_T_523, _T_522) @[Bitwise.scala 103:31]
+    node _T_525 = bits(_T_520, 3, 0) @[Bitwise.scala 103:46]
+    node _T_526 = shl(_T_525, 4) @[Bitwise.scala 103:65]
+    node _T_527 = not(_T_522) @[Bitwise.scala 103:77]
+    node _T_528 = and(_T_526, _T_527) @[Bitwise.scala 103:75]
+    node _T_529 = or(_T_524, _T_528) @[Bitwise.scala 103:39]
+    node _T_530 = bits(_T_522, 5, 0) @[Bitwise.scala 102:28]
+    node _T_531 = shl(_T_530, 2) @[Bitwise.scala 102:47]
+    node _T_532 = xor(_T_522, _T_531) @[Bitwise.scala 102:21]
+    node _T_533 = shr(_T_529, 2) @[Bitwise.scala 103:21]
+    node _T_534 = and(_T_533, _T_532) @[Bitwise.scala 103:31]
+    node _T_535 = bits(_T_529, 5, 0) @[Bitwise.scala 103:46]
+    node _T_536 = shl(_T_535, 2) @[Bitwise.scala 103:65]
+    node _T_537 = not(_T_532) @[Bitwise.scala 103:77]
+    node _T_538 = and(_T_536, _T_537) @[Bitwise.scala 103:75]
+    node _T_539 = or(_T_534, _T_538) @[Bitwise.scala 103:39]
+    node _T_540 = bits(_T_532, 6, 0) @[Bitwise.scala 102:28]
+    node _T_541 = shl(_T_540, 1) @[Bitwise.scala 102:47]
+    node _T_542 = xor(_T_532, _T_541) @[Bitwise.scala 102:21]
+    node _T_543 = shr(_T_539, 1) @[Bitwise.scala 103:21]
+    node _T_544 = and(_T_543, _T_542) @[Bitwise.scala 103:31]
+    node _T_545 = bits(_T_539, 6, 0) @[Bitwise.scala 103:46]
+    node _T_546 = shl(_T_545, 1) @[Bitwise.scala 103:65]
+    node _T_547 = not(_T_542) @[Bitwise.scala 103:77]
+    node _T_548 = and(_T_546, _T_547) @[Bitwise.scala 103:75]
+    node _T_549 = or(_T_544, _T_548) @[Bitwise.scala 103:39]
+    node _T_550 = bits(stbuf_fwdbyteen_r, 3, 3) @[lsu_dccm_ctl.scala 139:95]
+    node _T_551 = bits(_T_550, 0, 0) @[lsu_dccm_ctl.scala 139:99]
+    node _T_552 = bits(stbuf_fwddata_r, 31, 24) @[lsu_dccm_ctl.scala 139:121]
+    node _T_553 = bits(io.addr_in_pic_r, 0, 0) @[lsu_dccm_ctl.scala 139:157]
+    node _T_554 = bits(picm_rd_data_r, 31, 24) @[lsu_dccm_ctl.scala 139:178]
+    node _T_555 = bits(io.addr_in_dccm_r, 0, 0) @[Bitwise.scala 72:15]
+    node _T_556 = mux(_T_555, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
+    node _T_557 = bits(dccm_rdata_r, 31, 24) @[lsu_dccm_ctl.scala 139:233]
+    node _T_558 = and(_T_556, _T_557) @[lsu_dccm_ctl.scala 139:219]
+    node _T_559 = mux(_T_553, _T_554, _T_558) @[lsu_dccm_ctl.scala 139:139]
+    node _T_560 = mux(_T_551, _T_552, _T_559) @[lsu_dccm_ctl.scala 139:77]
+    node _T_561 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
+    node _T_562 = xor(UInt<8>("h0ff"), _T_561) @[Bitwise.scala 102:21]
+    node _T_563 = shr(_T_560, 4) @[Bitwise.scala 103:21]
+    node _T_564 = and(_T_563, _T_562) @[Bitwise.scala 103:31]
+    node _T_565 = bits(_T_560, 3, 0) @[Bitwise.scala 103:46]
+    node _T_566 = shl(_T_565, 4) @[Bitwise.scala 103:65]
+    node _T_567 = not(_T_562) @[Bitwise.scala 103:77]
+    node _T_568 = and(_T_566, _T_567) @[Bitwise.scala 103:75]
+    node _T_569 = or(_T_564, _T_568) @[Bitwise.scala 103:39]
+    node _T_570 = bits(_T_562, 5, 0) @[Bitwise.scala 102:28]
+    node _T_571 = shl(_T_570, 2) @[Bitwise.scala 102:47]
+    node _T_572 = xor(_T_562, _T_571) @[Bitwise.scala 102:21]
+    node _T_573 = shr(_T_569, 2) @[Bitwise.scala 103:21]
+    node _T_574 = and(_T_573, _T_572) @[Bitwise.scala 103:31]
+    node _T_575 = bits(_T_569, 5, 0) @[Bitwise.scala 103:46]
+    node _T_576 = shl(_T_575, 2) @[Bitwise.scala 103:65]
+    node _T_577 = not(_T_572) @[Bitwise.scala 103:77]
+    node _T_578 = and(_T_576, _T_577) @[Bitwise.scala 103:75]
+    node _T_579 = or(_T_574, _T_578) @[Bitwise.scala 103:39]
+    node _T_580 = bits(_T_572, 6, 0) @[Bitwise.scala 102:28]
+    node _T_581 = shl(_T_580, 1) @[Bitwise.scala 102:47]
+    node _T_582 = xor(_T_572, _T_581) @[Bitwise.scala 102:21]
+    node _T_583 = shr(_T_579, 1) @[Bitwise.scala 103:21]
+    node _T_584 = and(_T_583, _T_582) @[Bitwise.scala 103:31]
+    node _T_585 = bits(_T_579, 6, 0) @[Bitwise.scala 103:46]
+    node _T_586 = shl(_T_585, 1) @[Bitwise.scala 103:65]
+    node _T_587 = not(_T_582) @[Bitwise.scala 103:77]
+    node _T_588 = and(_T_586, _T_587) @[Bitwise.scala 103:75]
+    node _T_589 = or(_T_584, _T_588) @[Bitwise.scala 103:39]
+    node _T_590 = bits(stbuf_fwdbyteen_r, 4, 4) @[lsu_dccm_ctl.scala 139:95]
+    node _T_591 = bits(_T_590, 0, 0) @[lsu_dccm_ctl.scala 139:99]
+    node _T_592 = bits(stbuf_fwddata_r, 39, 32) @[lsu_dccm_ctl.scala 139:121]
+    node _T_593 = bits(io.addr_in_pic_r, 0, 0) @[lsu_dccm_ctl.scala 139:157]
+    node _T_594 = bits(picm_rd_data_r, 39, 32) @[lsu_dccm_ctl.scala 139:178]
+    node _T_595 = bits(io.addr_in_dccm_r, 0, 0) @[Bitwise.scala 72:15]
+    node _T_596 = mux(_T_595, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
+    node _T_597 = bits(dccm_rdata_r, 39, 32) @[lsu_dccm_ctl.scala 139:233]
+    node _T_598 = and(_T_596, _T_597) @[lsu_dccm_ctl.scala 139:219]
+    node _T_599 = mux(_T_593, _T_594, _T_598) @[lsu_dccm_ctl.scala 139:139]
+    node _T_600 = mux(_T_591, _T_592, _T_599) @[lsu_dccm_ctl.scala 139:77]
+    node _T_601 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
+    node _T_602 = xor(UInt<8>("h0ff"), _T_601) @[Bitwise.scala 102:21]
+    node _T_603 = shr(_T_600, 4) @[Bitwise.scala 103:21]
+    node _T_604 = and(_T_603, _T_602) @[Bitwise.scala 103:31]
+    node _T_605 = bits(_T_600, 3, 0) @[Bitwise.scala 103:46]
+    node _T_606 = shl(_T_605, 4) @[Bitwise.scala 103:65]
+    node _T_607 = not(_T_602) @[Bitwise.scala 103:77]
+    node _T_608 = and(_T_606, _T_607) @[Bitwise.scala 103:75]
+    node _T_609 = or(_T_604, _T_608) @[Bitwise.scala 103:39]
+    node _T_610 = bits(_T_602, 5, 0) @[Bitwise.scala 102:28]
+    node _T_611 = shl(_T_610, 2) @[Bitwise.scala 102:47]
+    node _T_612 = xor(_T_602, _T_611) @[Bitwise.scala 102:21]
+    node _T_613 = shr(_T_609, 2) @[Bitwise.scala 103:21]
+    node _T_614 = and(_T_613, _T_612) @[Bitwise.scala 103:31]
+    node _T_615 = bits(_T_609, 5, 0) @[Bitwise.scala 103:46]
+    node _T_616 = shl(_T_615, 2) @[Bitwise.scala 103:65]
+    node _T_617 = not(_T_612) @[Bitwise.scala 103:77]
+    node _T_618 = and(_T_616, _T_617) @[Bitwise.scala 103:75]
+    node _T_619 = or(_T_614, _T_618) @[Bitwise.scala 103:39]
+    node _T_620 = bits(_T_612, 6, 0) @[Bitwise.scala 102:28]
+    node _T_621 = shl(_T_620, 1) @[Bitwise.scala 102:47]
+    node _T_622 = xor(_T_612, _T_621) @[Bitwise.scala 102:21]
+    node _T_623 = shr(_T_619, 1) @[Bitwise.scala 103:21]
+    node _T_624 = and(_T_623, _T_622) @[Bitwise.scala 103:31]
+    node _T_625 = bits(_T_619, 6, 0) @[Bitwise.scala 103:46]
+    node _T_626 = shl(_T_625, 1) @[Bitwise.scala 103:65]
+    node _T_627 = not(_T_622) @[Bitwise.scala 103:77]
+    node _T_628 = and(_T_626, _T_627) @[Bitwise.scala 103:75]
+    node _T_629 = or(_T_624, _T_628) @[Bitwise.scala 103:39]
+    node _T_630 = bits(stbuf_fwdbyteen_r, 5, 5) @[lsu_dccm_ctl.scala 139:95]
+    node _T_631 = bits(_T_630, 0, 0) @[lsu_dccm_ctl.scala 139:99]
+    node _T_632 = bits(stbuf_fwddata_r, 47, 40) @[lsu_dccm_ctl.scala 139:121]
+    node _T_633 = bits(io.addr_in_pic_r, 0, 0) @[lsu_dccm_ctl.scala 139:157]
+    node _T_634 = bits(picm_rd_data_r, 47, 40) @[lsu_dccm_ctl.scala 139:178]
+    node _T_635 = bits(io.addr_in_dccm_r, 0, 0) @[Bitwise.scala 72:15]
+    node _T_636 = mux(_T_635, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
+    node _T_637 = bits(dccm_rdata_r, 47, 40) @[lsu_dccm_ctl.scala 139:233]
+    node _T_638 = and(_T_636, _T_637) @[lsu_dccm_ctl.scala 139:219]
+    node _T_639 = mux(_T_633, _T_634, _T_638) @[lsu_dccm_ctl.scala 139:139]
+    node _T_640 = mux(_T_631, _T_632, _T_639) @[lsu_dccm_ctl.scala 139:77]
+    node _T_641 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
+    node _T_642 = xor(UInt<8>("h0ff"), _T_641) @[Bitwise.scala 102:21]
+    node _T_643 = shr(_T_640, 4) @[Bitwise.scala 103:21]
+    node _T_644 = and(_T_643, _T_642) @[Bitwise.scala 103:31]
+    node _T_645 = bits(_T_640, 3, 0) @[Bitwise.scala 103:46]
+    node _T_646 = shl(_T_645, 4) @[Bitwise.scala 103:65]
+    node _T_647 = not(_T_642) @[Bitwise.scala 103:77]
+    node _T_648 = and(_T_646, _T_647) @[Bitwise.scala 103:75]
+    node _T_649 = or(_T_644, _T_648) @[Bitwise.scala 103:39]
+    node _T_650 = bits(_T_642, 5, 0) @[Bitwise.scala 102:28]
+    node _T_651 = shl(_T_650, 2) @[Bitwise.scala 102:47]
+    node _T_652 = xor(_T_642, _T_651) @[Bitwise.scala 102:21]
+    node _T_653 = shr(_T_649, 2) @[Bitwise.scala 103:21]
+    node _T_654 = and(_T_653, _T_652) @[Bitwise.scala 103:31]
+    node _T_655 = bits(_T_649, 5, 0) @[Bitwise.scala 103:46]
+    node _T_656 = shl(_T_655, 2) @[Bitwise.scala 103:65]
+    node _T_657 = not(_T_652) @[Bitwise.scala 103:77]
+    node _T_658 = and(_T_656, _T_657) @[Bitwise.scala 103:75]
+    node _T_659 = or(_T_654, _T_658) @[Bitwise.scala 103:39]
+    node _T_660 = bits(_T_652, 6, 0) @[Bitwise.scala 102:28]
+    node _T_661 = shl(_T_660, 1) @[Bitwise.scala 102:47]
+    node _T_662 = xor(_T_652, _T_661) @[Bitwise.scala 102:21]
+    node _T_663 = shr(_T_659, 1) @[Bitwise.scala 103:21]
+    node _T_664 = and(_T_663, _T_662) @[Bitwise.scala 103:31]
+    node _T_665 = bits(_T_659, 6, 0) @[Bitwise.scala 103:46]
+    node _T_666 = shl(_T_665, 1) @[Bitwise.scala 103:65]
+    node _T_667 = not(_T_662) @[Bitwise.scala 103:77]
+    node _T_668 = and(_T_666, _T_667) @[Bitwise.scala 103:75]
+    node _T_669 = or(_T_664, _T_668) @[Bitwise.scala 103:39]
+    node _T_670 = bits(stbuf_fwdbyteen_r, 6, 6) @[lsu_dccm_ctl.scala 139:95]
+    node _T_671 = bits(_T_670, 0, 0) @[lsu_dccm_ctl.scala 139:99]
+    node _T_672 = bits(stbuf_fwddata_r, 55, 48) @[lsu_dccm_ctl.scala 139:121]
+    node _T_673 = bits(io.addr_in_pic_r, 0, 0) @[lsu_dccm_ctl.scala 139:157]
+    node _T_674 = bits(picm_rd_data_r, 55, 48) @[lsu_dccm_ctl.scala 139:178]
+    node _T_675 = bits(io.addr_in_dccm_r, 0, 0) @[Bitwise.scala 72:15]
+    node _T_676 = mux(_T_675, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
+    node _T_677 = bits(dccm_rdata_r, 55, 48) @[lsu_dccm_ctl.scala 139:233]
+    node _T_678 = and(_T_676, _T_677) @[lsu_dccm_ctl.scala 139:219]
+    node _T_679 = mux(_T_673, _T_674, _T_678) @[lsu_dccm_ctl.scala 139:139]
+    node _T_680 = mux(_T_671, _T_672, _T_679) @[lsu_dccm_ctl.scala 139:77]
+    node _T_681 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
+    node _T_682 = xor(UInt<8>("h0ff"), _T_681) @[Bitwise.scala 102:21]
+    node _T_683 = shr(_T_680, 4) @[Bitwise.scala 103:21]
+    node _T_684 = and(_T_683, _T_682) @[Bitwise.scala 103:31]
+    node _T_685 = bits(_T_680, 3, 0) @[Bitwise.scala 103:46]
+    node _T_686 = shl(_T_685, 4) @[Bitwise.scala 103:65]
+    node _T_687 = not(_T_682) @[Bitwise.scala 103:77]
+    node _T_688 = and(_T_686, _T_687) @[Bitwise.scala 103:75]
+    node _T_689 = or(_T_684, _T_688) @[Bitwise.scala 103:39]
+    node _T_690 = bits(_T_682, 5, 0) @[Bitwise.scala 102:28]
+    node _T_691 = shl(_T_690, 2) @[Bitwise.scala 102:47]
+    node _T_692 = xor(_T_682, _T_691) @[Bitwise.scala 102:21]
+    node _T_693 = shr(_T_689, 2) @[Bitwise.scala 103:21]
+    node _T_694 = and(_T_693, _T_692) @[Bitwise.scala 103:31]
+    node _T_695 = bits(_T_689, 5, 0) @[Bitwise.scala 103:46]
+    node _T_696 = shl(_T_695, 2) @[Bitwise.scala 103:65]
+    node _T_697 = not(_T_692) @[Bitwise.scala 103:77]
+    node _T_698 = and(_T_696, _T_697) @[Bitwise.scala 103:75]
+    node _T_699 = or(_T_694, _T_698) @[Bitwise.scala 103:39]
+    node _T_700 = bits(_T_692, 6, 0) @[Bitwise.scala 102:28]
+    node _T_701 = shl(_T_700, 1) @[Bitwise.scala 102:47]
+    node _T_702 = xor(_T_692, _T_701) @[Bitwise.scala 102:21]
+    node _T_703 = shr(_T_699, 1) @[Bitwise.scala 103:21]
+    node _T_704 = and(_T_703, _T_702) @[Bitwise.scala 103:31]
+    node _T_705 = bits(_T_699, 6, 0) @[Bitwise.scala 103:46]
+    node _T_706 = shl(_T_705, 1) @[Bitwise.scala 103:65]
+    node _T_707 = not(_T_702) @[Bitwise.scala 103:77]
+    node _T_708 = and(_T_706, _T_707) @[Bitwise.scala 103:75]
+    node _T_709 = or(_T_704, _T_708) @[Bitwise.scala 103:39]
+    node _T_710 = bits(stbuf_fwdbyteen_r, 7, 7) @[lsu_dccm_ctl.scala 139:95]
+    node _T_711 = bits(_T_710, 0, 0) @[lsu_dccm_ctl.scala 139:99]
+    node _T_712 = bits(stbuf_fwddata_r, 63, 56) @[lsu_dccm_ctl.scala 139:121]
+    node _T_713 = bits(io.addr_in_pic_r, 0, 0) @[lsu_dccm_ctl.scala 139:157]
+    node _T_714 = bits(picm_rd_data_r, 63, 56) @[lsu_dccm_ctl.scala 139:178]
+    node _T_715 = bits(io.addr_in_dccm_r, 0, 0) @[Bitwise.scala 72:15]
+    node _T_716 = mux(_T_715, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
+    node _T_717 = bits(dccm_rdata_r, 63, 56) @[lsu_dccm_ctl.scala 139:233]
+    node _T_718 = and(_T_716, _T_717) @[lsu_dccm_ctl.scala 139:219]
+    node _T_719 = mux(_T_713, _T_714, _T_718) @[lsu_dccm_ctl.scala 139:139]
+    node _T_720 = mux(_T_711, _T_712, _T_719) @[lsu_dccm_ctl.scala 139:77]
+    node _T_721 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
+    node _T_722 = xor(UInt<8>("h0ff"), _T_721) @[Bitwise.scala 102:21]
+    node _T_723 = shr(_T_720, 4) @[Bitwise.scala 103:21]
+    node _T_724 = and(_T_723, _T_722) @[Bitwise.scala 103:31]
+    node _T_725 = bits(_T_720, 3, 0) @[Bitwise.scala 103:46]
+    node _T_726 = shl(_T_725, 4) @[Bitwise.scala 103:65]
+    node _T_727 = not(_T_722) @[Bitwise.scala 103:77]
+    node _T_728 = and(_T_726, _T_727) @[Bitwise.scala 103:75]
+    node _T_729 = or(_T_724, _T_728) @[Bitwise.scala 103:39]
+    node _T_730 = bits(_T_722, 5, 0) @[Bitwise.scala 102:28]
+    node _T_731 = shl(_T_730, 2) @[Bitwise.scala 102:47]
+    node _T_732 = xor(_T_722, _T_731) @[Bitwise.scala 102:21]
+    node _T_733 = shr(_T_729, 2) @[Bitwise.scala 103:21]
+    node _T_734 = and(_T_733, _T_732) @[Bitwise.scala 103:31]
+    node _T_735 = bits(_T_729, 5, 0) @[Bitwise.scala 103:46]
+    node _T_736 = shl(_T_735, 2) @[Bitwise.scala 103:65]
+    node _T_737 = not(_T_732) @[Bitwise.scala 103:77]
+    node _T_738 = and(_T_736, _T_737) @[Bitwise.scala 103:75]
+    node _T_739 = or(_T_734, _T_738) @[Bitwise.scala 103:39]
+    node _T_740 = bits(_T_732, 6, 0) @[Bitwise.scala 102:28]
+    node _T_741 = shl(_T_740, 1) @[Bitwise.scala 102:47]
+    node _T_742 = xor(_T_732, _T_741) @[Bitwise.scala 102:21]
+    node _T_743 = shr(_T_739, 1) @[Bitwise.scala 103:21]
+    node _T_744 = and(_T_743, _T_742) @[Bitwise.scala 103:31]
+    node _T_745 = bits(_T_739, 6, 0) @[Bitwise.scala 103:46]
+    node _T_746 = shl(_T_745, 1) @[Bitwise.scala 103:65]
+    node _T_747 = not(_T_742) @[Bitwise.scala 103:77]
+    node _T_748 = and(_T_746, _T_747) @[Bitwise.scala 103:75]
+    node _T_749 = or(_T_744, _T_748) @[Bitwise.scala 103:39]
+    wire _T_750 : UInt<8>[8] @[lsu_dccm_ctl.scala 139:61]
+    _T_750[0] <= _T_469 @[lsu_dccm_ctl.scala 139:61]
+    _T_750[1] <= _T_509 @[lsu_dccm_ctl.scala 139:61]
+    _T_750[2] <= _T_549 @[lsu_dccm_ctl.scala 139:61]
+    _T_750[3] <= _T_589 @[lsu_dccm_ctl.scala 139:61]
+    _T_750[4] <= _T_629 @[lsu_dccm_ctl.scala 139:61]
+    _T_750[5] <= _T_669 @[lsu_dccm_ctl.scala 139:61]
+    _T_750[6] <= _T_709 @[lsu_dccm_ctl.scala 139:61]
+    _T_750[7] <= _T_749 @[lsu_dccm_ctl.scala 139:61]
+    node _T_751 = cat(_T_750[6], _T_750[7]) @[Cat.scala 29:58]
+    node _T_752 = cat(_T_750[4], _T_750[5]) @[Cat.scala 29:58]
+    node _T_753 = cat(_T_752, _T_751) @[Cat.scala 29:58]
+    node _T_754 = cat(_T_750[2], _T_750[3]) @[Cat.scala 29:58]
+    node _T_755 = cat(_T_750[0], _T_750[1]) @[Cat.scala 29:58]
+    node _T_756 = cat(_T_755, _T_754) @[Cat.scala 29:58]
+    node _T_757 = cat(_T_756, _T_753) @[Cat.scala 29:58]
+    node _T_758 = shl(UInt<32>("h0ffffffff"), 32) @[Bitwise.scala 102:47]
+    node _T_759 = xor(UInt<64>("h0ffffffffffffffff"), _T_758) @[Bitwise.scala 102:21]
+    node _T_760 = shr(_T_757, 32) @[Bitwise.scala 103:21]
+    node _T_761 = and(_T_760, _T_759) @[Bitwise.scala 103:31]
+    node _T_762 = bits(_T_757, 31, 0) @[Bitwise.scala 103:46]
+    node _T_763 = shl(_T_762, 32) @[Bitwise.scala 103:65]
+    node _T_764 = not(_T_759) @[Bitwise.scala 103:77]
+    node _T_765 = and(_T_763, _T_764) @[Bitwise.scala 103:75]
+    node _T_766 = or(_T_761, _T_765) @[Bitwise.scala 103:39]
+    node _T_767 = bits(_T_759, 47, 0) @[Bitwise.scala 102:28]
+    node _T_768 = shl(_T_767, 16) @[Bitwise.scala 102:47]
+    node _T_769 = xor(_T_759, _T_768) @[Bitwise.scala 102:21]
+    node _T_770 = shr(_T_766, 16) @[Bitwise.scala 103:21]
+    node _T_771 = and(_T_770, _T_769) @[Bitwise.scala 103:31]
+    node _T_772 = bits(_T_766, 47, 0) @[Bitwise.scala 103:46]
+    node _T_773 = shl(_T_772, 16) @[Bitwise.scala 103:65]
+    node _T_774 = not(_T_769) @[Bitwise.scala 103:77]
+    node _T_775 = and(_T_773, _T_774) @[Bitwise.scala 103:75]
+    node _T_776 = or(_T_771, _T_775) @[Bitwise.scala 103:39]
+    node _T_777 = bits(_T_769, 55, 0) @[Bitwise.scala 102:28]
+    node _T_778 = shl(_T_777, 8) @[Bitwise.scala 102:47]
+    node _T_779 = xor(_T_769, _T_778) @[Bitwise.scala 102:21]
+    node _T_780 = shr(_T_776, 8) @[Bitwise.scala 103:21]
+    node _T_781 = and(_T_780, _T_779) @[Bitwise.scala 103:31]
+    node _T_782 = bits(_T_776, 55, 0) @[Bitwise.scala 103:46]
+    node _T_783 = shl(_T_782, 8) @[Bitwise.scala 103:65]
+    node _T_784 = not(_T_779) @[Bitwise.scala 103:77]
+    node _T_785 = and(_T_783, _T_784) @[Bitwise.scala 103:75]
+    node _T_786 = or(_T_781, _T_785) @[Bitwise.scala 103:39]
+    node _T_787 = bits(_T_779, 59, 0) @[Bitwise.scala 102:28]
+    node _T_788 = shl(_T_787, 4) @[Bitwise.scala 102:47]
+    node _T_789 = xor(_T_779, _T_788) @[Bitwise.scala 102:21]
+    node _T_790 = shr(_T_786, 4) @[Bitwise.scala 103:21]
+    node _T_791 = and(_T_790, _T_789) @[Bitwise.scala 103:31]
+    node _T_792 = bits(_T_786, 59, 0) @[Bitwise.scala 103:46]
+    node _T_793 = shl(_T_792, 4) @[Bitwise.scala 103:65]
+    node _T_794 = not(_T_789) @[Bitwise.scala 103:77]
+    node _T_795 = and(_T_793, _T_794) @[Bitwise.scala 103:75]
+    node _T_796 = or(_T_791, _T_795) @[Bitwise.scala 103:39]
+    node _T_797 = bits(_T_789, 61, 0) @[Bitwise.scala 102:28]
+    node _T_798 = shl(_T_797, 2) @[Bitwise.scala 102:47]
+    node _T_799 = xor(_T_789, _T_798) @[Bitwise.scala 102:21]
+    node _T_800 = shr(_T_796, 2) @[Bitwise.scala 103:21]
+    node _T_801 = and(_T_800, _T_799) @[Bitwise.scala 103:31]
+    node _T_802 = bits(_T_796, 61, 0) @[Bitwise.scala 103:46]
+    node _T_803 = shl(_T_802, 2) @[Bitwise.scala 103:65]
+    node _T_804 = not(_T_799) @[Bitwise.scala 103:77]
+    node _T_805 = and(_T_803, _T_804) @[Bitwise.scala 103:75]
+    node _T_806 = or(_T_801, _T_805) @[Bitwise.scala 103:39]
+    node _T_807 = bits(_T_799, 62, 0) @[Bitwise.scala 102:28]
+    node _T_808 = shl(_T_807, 1) @[Bitwise.scala 102:47]
+    node _T_809 = xor(_T_799, _T_808) @[Bitwise.scala 102:21]
+    node _T_810 = shr(_T_806, 1) @[Bitwise.scala 103:21]
+    node _T_811 = and(_T_810, _T_809) @[Bitwise.scala 103:31]
+    node _T_812 = bits(_T_806, 62, 0) @[Bitwise.scala 103:46]
+    node _T_813 = shl(_T_812, 1) @[Bitwise.scala 103:65]
+    node _T_814 = not(_T_809) @[Bitwise.scala 103:77]
+    node _T_815 = and(_T_813, _T_814) @[Bitwise.scala 103:75]
+    node _T_816 = or(_T_811, _T_815) @[Bitwise.scala 103:39]
+    lsu_rdata_r <= _T_816 @[lsu_dccm_ctl.scala 139:27]
+    node _T_817 = bits(io.lsu_addr_r, 1, 0) @[lsu_dccm_ctl.scala 140:61]
+    node _T_818 = mul(UInt<4>("h08"), _T_817) @[lsu_dccm_ctl.scala 140:47]
+    node _T_819 = dshr(lsu_rdata_r, _T_818) @[lsu_dccm_ctl.scala 140:41]
+    io.lsu_ld_data_r <= _T_819 @[lsu_dccm_ctl.scala 140:27]
+    node _T_820 = bits(io.lsu_addr_r, 1, 0) @[lsu_dccm_ctl.scala 141:67]
+    node _T_821 = mul(UInt<4>("h08"), _T_820) @[lsu_dccm_ctl.scala 141:53]
+    node _T_822 = dshr(lsu_rdata_corr_r, _T_821) @[lsu_dccm_ctl.scala 141:47]
+    io.lsu_ld_data_corr_r <= _T_822 @[lsu_dccm_ctl.scala 141:27]
+    node _T_823 = bits(io.lsu_addr_d, 15, 2) @[lsu_dccm_ctl.scala 163:44]
+    node _T_824 = bits(io.lsu_addr_r, 15, 2) @[lsu_dccm_ctl.scala 163:77]
+    node _T_825 = eq(_T_823, _T_824) @[lsu_dccm_ctl.scala 163:60]
+    node _T_826 = bits(io.end_addr_d, 15, 2) @[lsu_dccm_ctl.scala 163:117]
+    node _T_827 = bits(io.lsu_addr_r, 15, 2) @[lsu_dccm_ctl.scala 163:150]
+    node _T_828 = eq(_T_826, _T_827) @[lsu_dccm_ctl.scala 163:133]
+    node _T_829 = or(_T_825, _T_828) @[lsu_dccm_ctl.scala 163:101]
+    node _T_830 = and(_T_829, io.lsu_pkt_d.valid) @[lsu_dccm_ctl.scala 163:175]
+    node _T_831 = and(_T_830, io.lsu_pkt_d.bits.store) @[lsu_dccm_ctl.scala 163:196]
+    node _T_832 = and(_T_831, io.lsu_pkt_d.bits.dma) @[lsu_dccm_ctl.scala 163:222]
+    node _T_833 = and(_T_832, io.addr_in_dccm_d) @[lsu_dccm_ctl.scala 163:246]
+    node _T_834 = bits(io.lsu_addr_m, 15, 2) @[lsu_dccm_ctl.scala 164:21]
+    node _T_835 = bits(io.lsu_addr_r, 15, 2) @[lsu_dccm_ctl.scala 164:54]
+    node _T_836 = eq(_T_834, _T_835) @[lsu_dccm_ctl.scala 164:37]
+    node _T_837 = bits(io.end_addr_m, 15, 2) @[lsu_dccm_ctl.scala 164:94]
+    node _T_838 = bits(io.lsu_addr_r, 15, 2) @[lsu_dccm_ctl.scala 164:127]
+    node _T_839 = eq(_T_837, _T_838) @[lsu_dccm_ctl.scala 164:110]
+    node _T_840 = or(_T_836, _T_839) @[lsu_dccm_ctl.scala 164:78]
+    node _T_841 = and(_T_840, io.lsu_pkt_m.valid) @[lsu_dccm_ctl.scala 164:152]
+    node _T_842 = and(_T_841, io.lsu_pkt_m.bits.store) @[lsu_dccm_ctl.scala 164:173]
+    node _T_843 = and(_T_842, io.lsu_pkt_m.bits.dma) @[lsu_dccm_ctl.scala 164:199]
+    node _T_844 = and(_T_843, io.addr_in_dccm_m) @[lsu_dccm_ctl.scala 164:223]
+    node kill_ecc_corr_lo_r = or(_T_833, _T_844) @[lsu_dccm_ctl.scala 163:267]
+    node _T_845 = bits(io.lsu_addr_d, 15, 2) @[lsu_dccm_ctl.scala 166:44]
+    node _T_846 = bits(io.end_addr_r, 15, 2) @[lsu_dccm_ctl.scala 166:77]
+    node _T_847 = eq(_T_845, _T_846) @[lsu_dccm_ctl.scala 166:60]
+    node _T_848 = bits(io.end_addr_d, 15, 2) @[lsu_dccm_ctl.scala 166:117]
+    node _T_849 = bits(io.end_addr_r, 15, 2) @[lsu_dccm_ctl.scala 166:150]
+    node _T_850 = eq(_T_848, _T_849) @[lsu_dccm_ctl.scala 166:133]
+    node _T_851 = or(_T_847, _T_850) @[lsu_dccm_ctl.scala 166:101]
+    node _T_852 = and(_T_851, io.lsu_pkt_d.valid) @[lsu_dccm_ctl.scala 166:175]
+    node _T_853 = and(_T_852, io.lsu_pkt_d.bits.store) @[lsu_dccm_ctl.scala 166:196]
+    node _T_854 = and(_T_853, io.lsu_pkt_d.bits.dma) @[lsu_dccm_ctl.scala 166:222]
+    node _T_855 = and(_T_854, io.addr_in_dccm_d) @[lsu_dccm_ctl.scala 166:246]
+    node _T_856 = bits(io.lsu_addr_m, 15, 2) @[lsu_dccm_ctl.scala 167:21]
+    node _T_857 = bits(io.end_addr_r, 15, 2) @[lsu_dccm_ctl.scala 167:54]
+    node _T_858 = eq(_T_856, _T_857) @[lsu_dccm_ctl.scala 167:37]
+    node _T_859 = bits(io.end_addr_m, 15, 2) @[lsu_dccm_ctl.scala 167:94]
+    node _T_860 = bits(io.end_addr_r, 15, 2) @[lsu_dccm_ctl.scala 167:127]
+    node _T_861 = eq(_T_859, _T_860) @[lsu_dccm_ctl.scala 167:110]
+    node _T_862 = or(_T_858, _T_861) @[lsu_dccm_ctl.scala 167:78]
+    node _T_863 = and(_T_862, io.lsu_pkt_m.valid) @[lsu_dccm_ctl.scala 167:152]
+    node _T_864 = and(_T_863, io.lsu_pkt_m.bits.store) @[lsu_dccm_ctl.scala 167:173]
+    node _T_865 = and(_T_864, io.lsu_pkt_m.bits.dma) @[lsu_dccm_ctl.scala 167:199]
+    node _T_866 = and(_T_865, io.addr_in_dccm_m) @[lsu_dccm_ctl.scala 167:223]
+    node kill_ecc_corr_hi_r = or(_T_855, _T_866) @[lsu_dccm_ctl.scala 166:267]
+    node _T_867 = and(io.lsu_pkt_r.bits.load, io.single_ecc_error_lo_r) @[lsu_dccm_ctl.scala 169:60]
+    node _T_868 = eq(io.lsu_raw_fwd_lo_r, UInt<1>("h00")) @[lsu_dccm_ctl.scala 169:89]
+    node ld_single_ecc_error_lo_r = and(_T_867, _T_868) @[lsu_dccm_ctl.scala 169:87]
+    node _T_869 = and(io.lsu_pkt_r.bits.load, io.single_ecc_error_hi_r) @[lsu_dccm_ctl.scala 170:60]
+    node _T_870 = eq(io.lsu_raw_fwd_hi_r, UInt<1>("h00")) @[lsu_dccm_ctl.scala 170:89]
+    node ld_single_ecc_error_hi_r = and(_T_869, _T_870) @[lsu_dccm_ctl.scala 170:87]
+    node _T_871 = or(ld_single_ecc_error_lo_r, ld_single_ecc_error_hi_r) @[lsu_dccm_ctl.scala 171:63]
+    node _T_872 = eq(io.lsu_double_ecc_error_r, UInt<1>("h00")) @[lsu_dccm_ctl.scala 171:93]
+    node _T_873 = and(_T_871, _T_872) @[lsu_dccm_ctl.scala 171:91]
+    io.ld_single_ecc_error_r <= _T_873 @[lsu_dccm_ctl.scala 171:34]
+    node _T_874 = or(io.lsu_commit_r, io.lsu_pkt_r.bits.dma) @[lsu_dccm_ctl.scala 172:81]
+    node _T_875 = and(ld_single_ecc_error_lo_r, _T_874) @[lsu_dccm_ctl.scala 172:62]
+    node _T_876 = eq(kill_ecc_corr_lo_r, UInt<1>("h00")) @[lsu_dccm_ctl.scala 172:108]
+    node ld_single_ecc_error_lo_r_ns = and(_T_875, _T_876) @[lsu_dccm_ctl.scala 172:106]
+    node _T_877 = or(io.lsu_commit_r, io.lsu_pkt_r.bits.dma) @[lsu_dccm_ctl.scala 173:81]
+    node _T_878 = and(ld_single_ecc_error_hi_r, _T_877) @[lsu_dccm_ctl.scala 173:62]
+    node _T_879 = eq(kill_ecc_corr_hi_r, UInt<1>("h00")) @[lsu_dccm_ctl.scala 173:108]
+    node ld_single_ecc_error_hi_r_ns = and(_T_878, _T_879) @[lsu_dccm_ctl.scala 173:106]
+    node _T_880 = or(io.lsu_pkt_d.bits.word, io.lsu_pkt_d.bits.dword) @[lsu_dccm_ctl.scala 175:125]
+    node _T_881 = eq(_T_880, UInt<1>("h00")) @[lsu_dccm_ctl.scala 175:100]
+    node _T_882 = bits(io.lsu_addr_d, 1, 0) @[lsu_dccm_ctl.scala 175:168]
+    node _T_883 = neq(_T_882, UInt<2>("h00")) @[lsu_dccm_ctl.scala 175:174]
+    node _T_884 = or(_T_881, _T_883) @[lsu_dccm_ctl.scala 175:152]
+    node _T_885 = and(io.lsu_pkt_d.bits.store, _T_884) @[lsu_dccm_ctl.scala 175:97]
+    node _T_886 = or(io.lsu_pkt_d.bits.load, _T_885) @[lsu_dccm_ctl.scala 175:70]
+    node _T_887 = and(io.lsu_pkt_d.valid, _T_886) @[lsu_dccm_ctl.scala 175:44]
+    node lsu_dccm_rden_d = and(_T_887, io.addr_in_dccm_d) @[lsu_dccm_ctl.scala 175:191]
+    node _T_888 = or(ld_single_ecc_error_lo_r_ff, ld_single_ecc_error_hi_r_ff) @[lsu_dccm_ctl.scala 178:63]
+    node _T_889 = eq(lsu_double_ecc_error_r_ff, UInt<1>("h00")) @[lsu_dccm_ctl.scala 178:96]
+    node _T_890 = and(_T_888, _T_889) @[lsu_dccm_ctl.scala 178:94]
+    io.ld_single_ecc_error_r_ff <= _T_890 @[lsu_dccm_ctl.scala 178:31]
+    node _T_891 = or(lsu_dccm_rden_d, io.dma_dccm_wen) @[lsu_dccm_ctl.scala 179:75]
+    node _T_892 = or(_T_891, io.ld_single_ecc_error_r_ff) @[lsu_dccm_ctl.scala 179:93]
+    node _T_893 = eq(_T_892, UInt<1>("h00")) @[lsu_dccm_ctl.scala 179:57]
+    node _T_894 = bits(io.stbuf_addr_any, 3, 2) @[lsu_dccm_ctl.scala 180:44]
+    node _T_895 = bits(io.lsu_addr_d, 3, 2) @[lsu_dccm_ctl.scala 180:112]
+    node _T_896 = eq(_T_894, _T_895) @[lsu_dccm_ctl.scala 180:95]
+    node _T_897 = bits(io.stbuf_addr_any, 3, 2) @[lsu_dccm_ctl.scala 181:25]
+    node _T_898 = bits(io.end_addr_d, 3, 2) @[lsu_dccm_ctl.scala 181:93]
+    node _T_899 = eq(_T_897, _T_898) @[lsu_dccm_ctl.scala 181:76]
+    node _T_900 = or(_T_896, _T_899) @[lsu_dccm_ctl.scala 180:171]
+    node _T_901 = eq(_T_900, UInt<1>("h00")) @[lsu_dccm_ctl.scala 180:24]
+    node _T_902 = and(lsu_dccm_rden_d, _T_901) @[lsu_dccm_ctl.scala 180:22]
+    node _T_903 = or(_T_893, _T_902) @[lsu_dccm_ctl.scala 179:124]
+    node _T_904 = and(io.stbuf_reqvld_any, _T_903) @[lsu_dccm_ctl.scala 179:54]
+    io.lsu_stbuf_commit_any <= _T_904 @[lsu_dccm_ctl.scala 179:31]
+    node _T_905 = or(io.dma_dccm_wen, io.lsu_stbuf_commit_any) @[lsu_dccm_ctl.scala 185:41]
+    node _T_906 = or(_T_905, io.ld_single_ecc_error_r_ff) @[lsu_dccm_ctl.scala 185:67]
+    io.dccm.wren <= _T_906 @[lsu_dccm_ctl.scala 185:22]
+    node _T_907 = and(lsu_dccm_rden_d, io.addr_in_dccm_d) @[lsu_dccm_ctl.scala 186:41]
+    io.dccm.rden <= _T_907 @[lsu_dccm_ctl.scala 186:22]
+    node _T_908 = bits(io.ld_single_ecc_error_r_ff, 0, 0) @[lsu_dccm_ctl.scala 188:57]
+    node _T_909 = eq(ld_single_ecc_error_lo_r_ff, UInt<1>("h01")) @[lsu_dccm_ctl.scala 189:36]
+    node _T_910 = bits(ld_sec_addr_lo_r_ff, 15, 0) @[lsu_dccm_ctl.scala 189:62]
+    node _T_911 = bits(ld_sec_addr_hi_r_ff, 15, 0) @[lsu_dccm_ctl.scala 189:97]
+    node _T_912 = mux(_T_909, _T_910, _T_911) @[lsu_dccm_ctl.scala 189:8]
+    node _T_913 = bits(io.dma_dccm_wen, 0, 0) @[lsu_dccm_ctl.scala 190:25]
+    node _T_914 = bits(io.lsu_addr_d, 15, 0) @[lsu_dccm_ctl.scala 190:45]
+    node _T_915 = bits(io.stbuf_addr_any, 15, 0) @[lsu_dccm_ctl.scala 190:78]
+    node _T_916 = mux(_T_913, _T_914, _T_915) @[lsu_dccm_ctl.scala 190:8]
+    node _T_917 = mux(_T_908, _T_912, _T_916) @[lsu_dccm_ctl.scala 188:28]
+    io.dccm.wr_addr_lo <= _T_917 @[lsu_dccm_ctl.scala 188:22]
+    node _T_918 = bits(io.ld_single_ecc_error_r_ff, 0, 0) @[lsu_dccm_ctl.scala 192:57]
+    node _T_919 = eq(ld_single_ecc_error_hi_r_ff, UInt<1>("h01")) @[lsu_dccm_ctl.scala 193:36]
+    node _T_920 = bits(ld_sec_addr_hi_r_ff, 15, 0) @[lsu_dccm_ctl.scala 193:63]
+    node _T_921 = bits(ld_sec_addr_lo_r_ff, 15, 0) @[lsu_dccm_ctl.scala 193:99]
+    node _T_922 = mux(_T_919, _T_920, _T_921) @[lsu_dccm_ctl.scala 193:8]
+    node _T_923 = bits(io.dma_dccm_wen, 0, 0) @[lsu_dccm_ctl.scala 194:25]
+    node _T_924 = bits(io.end_addr_d, 15, 0) @[lsu_dccm_ctl.scala 194:46]
+    node _T_925 = bits(io.stbuf_addr_any, 15, 0) @[lsu_dccm_ctl.scala 194:79]
+    node _T_926 = mux(_T_923, _T_924, _T_925) @[lsu_dccm_ctl.scala 194:8]
+    node _T_927 = mux(_T_918, _T_922, _T_926) @[lsu_dccm_ctl.scala 192:28]
+    io.dccm.wr_addr_hi <= _T_927 @[lsu_dccm_ctl.scala 192:22]
+    node _T_928 = bits(io.lsu_addr_d, 15, 0) @[lsu_dccm_ctl.scala 196:38]
+    io.dccm.rd_addr_lo <= _T_928 @[lsu_dccm_ctl.scala 196:22]
+    node _T_929 = bits(io.end_addr_d, 15, 0) @[lsu_dccm_ctl.scala 197:38]
+    io.dccm.rd_addr_hi <= _T_929 @[lsu_dccm_ctl.scala 197:22]
+    node _T_930 = bits(io.ld_single_ecc_error_r_ff, 0, 0) @[lsu_dccm_ctl.scala 199:57]
+    node _T_931 = eq(ld_single_ecc_error_lo_r_ff, UInt<1>("h01")) @[lsu_dccm_ctl.scala 200:36]
+    node _T_932 = bits(io.sec_data_ecc_lo_r_ff, 6, 0) @[lsu_dccm_ctl.scala 200:70]
+    node _T_933 = bits(io.sec_data_lo_r_ff, 31, 0) @[lsu_dccm_ctl.scala 200:110]
+    node _T_934 = cat(_T_932, _T_933) @[Cat.scala 29:58]
+    node _T_935 = bits(io.sec_data_ecc_hi_r_ff, 6, 0) @[lsu_dccm_ctl.scala 201:34]
+    node _T_936 = bits(io.sec_data_hi_r_ff, 31, 0) @[lsu_dccm_ctl.scala 201:74]
+    node _T_937 = cat(_T_935, _T_936) @[Cat.scala 29:58]
+    node _T_938 = mux(_T_931, _T_934, _T_937) @[lsu_dccm_ctl.scala 200:8]
+    node _T_939 = bits(io.dma_dccm_wen, 0, 0) @[lsu_dccm_ctl.scala 202:25]
+    node _T_940 = bits(io.dma_dccm_wdata_ecc_lo, 6, 0) @[lsu_dccm_ctl.scala 202:60]
+    node _T_941 = bits(io.dma_dccm_wdata_lo, 31, 0) @[lsu_dccm_ctl.scala 202:101]
+    node _T_942 = cat(_T_940, _T_941) @[Cat.scala 29:58]
+    node _T_943 = bits(io.stbuf_ecc_any, 6, 0) @[lsu_dccm_ctl.scala 203:27]
+    node _T_944 = bits(io.stbuf_data_any, 31, 0) @[lsu_dccm_ctl.scala 203:65]
+    node _T_945 = cat(_T_943, _T_944) @[Cat.scala 29:58]
+    node _T_946 = mux(_T_939, _T_942, _T_945) @[lsu_dccm_ctl.scala 202:8]
+    node _T_947 = mux(_T_930, _T_938, _T_946) @[lsu_dccm_ctl.scala 199:28]
+    io.dccm.wr_data_lo <= _T_947 @[lsu_dccm_ctl.scala 199:22]
+    node _T_948 = bits(io.ld_single_ecc_error_r_ff, 0, 0) @[lsu_dccm_ctl.scala 205:57]
+    node _T_949 = eq(ld_single_ecc_error_hi_r_ff, UInt<1>("h01")) @[lsu_dccm_ctl.scala 206:36]
+    node _T_950 = bits(io.sec_data_ecc_hi_r_ff, 6, 0) @[lsu_dccm_ctl.scala 206:71]
+    node _T_951 = bits(io.sec_data_hi_r_ff, 31, 0) @[lsu_dccm_ctl.scala 206:111]
+    node _T_952 = cat(_T_950, _T_951) @[Cat.scala 29:58]
+    node _T_953 = bits(io.sec_data_ecc_lo_r_ff, 6, 0) @[lsu_dccm_ctl.scala 207:34]
+    node _T_954 = bits(io.sec_data_lo_r_ff, 31, 0) @[lsu_dccm_ctl.scala 207:74]
+    node _T_955 = cat(_T_953, _T_954) @[Cat.scala 29:58]
+    node _T_956 = mux(_T_949, _T_952, _T_955) @[lsu_dccm_ctl.scala 206:8]
+    node _T_957 = bits(io.dma_dccm_wen, 0, 0) @[lsu_dccm_ctl.scala 208:25]
+    node _T_958 = bits(io.dma_dccm_wdata_ecc_hi, 6, 0) @[lsu_dccm_ctl.scala 208:61]
+    node _T_959 = bits(io.dma_dccm_wdata_hi, 31, 0) @[lsu_dccm_ctl.scala 208:102]
+    node _T_960 = cat(_T_958, _T_959) @[Cat.scala 29:58]
+    node _T_961 = bits(io.stbuf_ecc_any, 6, 0) @[lsu_dccm_ctl.scala 209:27]
+    node _T_962 = bits(io.stbuf_data_any, 31, 0) @[lsu_dccm_ctl.scala 209:65]
+    node _T_963 = cat(_T_961, _T_962) @[Cat.scala 29:58]
+    node _T_964 = mux(_T_957, _T_960, _T_963) @[lsu_dccm_ctl.scala 208:8]
+    node _T_965 = mux(_T_948, _T_956, _T_964) @[lsu_dccm_ctl.scala 205:28]
+    io.dccm.wr_data_hi <= _T_965 @[lsu_dccm_ctl.scala 205:22]
+    node _T_966 = bits(io.lsu_pkt_m.bits.store, 0, 0) @[Bitwise.scala 72:15]
+    node _T_967 = mux(_T_966, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
+    node _T_968 = bits(io.lsu_pkt_m.bits.by, 0, 0) @[Bitwise.scala 72:15]
+    node _T_969 = mux(_T_968, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
+    node _T_970 = and(_T_969, UInt<4>("h01")) @[lsu_dccm_ctl.scala 212:94]
+    node _T_971 = bits(io.lsu_pkt_m.bits.half, 0, 0) @[Bitwise.scala 72:15]
+    node _T_972 = mux(_T_971, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
+    node _T_973 = and(_T_972, UInt<4>("h03")) @[lsu_dccm_ctl.scala 213:38]
+    node _T_974 = or(_T_970, _T_973) @[lsu_dccm_ctl.scala 212:107]
+    node _T_975 = bits(io.lsu_pkt_m.bits.word, 0, 0) @[Bitwise.scala 72:15]
+    node _T_976 = mux(_T_975, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
+    node _T_977 = and(_T_976, UInt<4>("h0f")) @[lsu_dccm_ctl.scala 214:38]
+    node _T_978 = or(_T_974, _T_977) @[lsu_dccm_ctl.scala 213:51]
+    node store_byteen_m = and(_T_967, _T_978) @[lsu_dccm_ctl.scala 212:58]
+    node _T_979 = bits(io.lsu_pkt_r.bits.store, 0, 0) @[Bitwise.scala 72:15]
+    node _T_980 = mux(_T_979, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
+    node _T_981 = bits(io.lsu_pkt_r.bits.by, 0, 0) @[Bitwise.scala 72:15]
+    node _T_982 = mux(_T_981, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
+    node _T_983 = and(_T_982, UInt<4>("h01")) @[lsu_dccm_ctl.scala 216:94]
+    node _T_984 = bits(io.lsu_pkt_r.bits.half, 0, 0) @[Bitwise.scala 72:15]
+    node _T_985 = mux(_T_984, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
+    node _T_986 = and(_T_985, UInt<4>("h03")) @[lsu_dccm_ctl.scala 217:38]
+    node _T_987 = or(_T_983, _T_986) @[lsu_dccm_ctl.scala 216:107]
+    node _T_988 = bits(io.lsu_pkt_r.bits.word, 0, 0) @[Bitwise.scala 72:15]
+    node _T_989 = mux(_T_988, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
+    node _T_990 = and(_T_989, UInt<4>("h0f")) @[lsu_dccm_ctl.scala 218:38]
+    node _T_991 = or(_T_987, _T_990) @[lsu_dccm_ctl.scala 217:51]
+    node store_byteen_r = and(_T_980, _T_991) @[lsu_dccm_ctl.scala 216:58]
+    wire store_byteen_ext_m : UInt<8>
+    store_byteen_ext_m <= UInt<1>("h00")
+    node _T_992 = bits(store_byteen_m, 3, 0) @[lsu_dccm_ctl.scala 220:39]
+    node _T_993 = bits(io.lsu_addr_m, 1, 0) @[lsu_dccm_ctl.scala 220:61]
+    node _T_994 = dshl(_T_992, _T_993) @[lsu_dccm_ctl.scala 220:45]
+    store_byteen_ext_m <= _T_994 @[lsu_dccm_ctl.scala 220:22]
+    wire store_byteen_ext_r : UInt<8>
+    store_byteen_ext_r <= UInt<1>("h00")
+    node _T_995 = bits(store_byteen_r, 3, 0) @[lsu_dccm_ctl.scala 222:39]
+    node _T_996 = bits(io.lsu_addr_r, 1, 0) @[lsu_dccm_ctl.scala 222:61]
+    node _T_997 = dshl(_T_995, _T_996) @[lsu_dccm_ctl.scala 222:45]
+    store_byteen_ext_r <= _T_997 @[lsu_dccm_ctl.scala 222:22]
+    node _T_998 = bits(io.stbuf_addr_any, 15, 2) @[lsu_dccm_ctl.scala 225:51]
+    node _T_999 = bits(io.lsu_addr_m, 15, 2) @[lsu_dccm_ctl.scala 225:84]
+    node _T_1000 = eq(_T_998, _T_999) @[lsu_dccm_ctl.scala 225:67]
+    node dccm_wr_bypass_d_m_lo = and(_T_1000, io.addr_in_dccm_m) @[lsu_dccm_ctl.scala 225:101]
+    node _T_1001 = bits(io.stbuf_addr_any, 15, 2) @[lsu_dccm_ctl.scala 226:51]
+    node _T_1002 = bits(io.end_addr_m, 15, 2) @[lsu_dccm_ctl.scala 226:84]
+    node _T_1003 = eq(_T_1001, _T_1002) @[lsu_dccm_ctl.scala 226:67]
+    node dccm_wr_bypass_d_m_hi = and(_T_1003, io.addr_in_dccm_m) @[lsu_dccm_ctl.scala 226:101]
+    node _T_1004 = bits(io.stbuf_addr_any, 15, 2) @[lsu_dccm_ctl.scala 228:51]
+    node _T_1005 = bits(io.lsu_addr_r, 15, 2) @[lsu_dccm_ctl.scala 228:84]
+    node _T_1006 = eq(_T_1004, _T_1005) @[lsu_dccm_ctl.scala 228:67]
+    node dccm_wr_bypass_d_r_lo = and(_T_1006, io.addr_in_dccm_r) @[lsu_dccm_ctl.scala 228:101]
+    node _T_1007 = bits(io.stbuf_addr_any, 15, 2) @[lsu_dccm_ctl.scala 229:51]
+    node _T_1008 = bits(io.end_addr_r, 15, 2) @[lsu_dccm_ctl.scala 229:84]
+    node _T_1009 = eq(_T_1007, _T_1008) @[lsu_dccm_ctl.scala 229:67]
+    node dccm_wr_bypass_d_r_hi = and(_T_1009, io.addr_in_dccm_r) @[lsu_dccm_ctl.scala 229:101]
+    wire dccm_wr_bypass_d_m_hi_Q : UInt<1>
+    dccm_wr_bypass_d_m_hi_Q <= UInt<1>("h00")
+    wire dccm_wr_bypass_d_m_lo_Q : UInt<1>
+    dccm_wr_bypass_d_m_lo_Q <= UInt<1>("h00")
+    wire dccm_wren_Q : UInt<1>
+    dccm_wren_Q <= UInt<1>("h00")
+    wire dccm_wr_data_Q : UInt<32>
+    dccm_wr_data_Q <= UInt<32>("h00")
+    wire store_data_pre_r : UInt<64>
+    store_data_pre_r <= UInt<64>("h00")
+    wire store_data_pre_hi_r : UInt<32>
+    store_data_pre_hi_r <= UInt<32>("h00")
+    wire store_data_pre_lo_r : UInt<32>
+    store_data_pre_lo_r <= UInt<32>("h00")
+    wire store_data_pre_m : UInt<64>
+    store_data_pre_m <= UInt<64>("h00")
+    wire store_data_hi_m : UInt<32>
+    store_data_hi_m <= UInt<32>("h00")
+    wire store_data_lo_m : UInt<32>
+    store_data_lo_m <= UInt<32>("h00")
+    node _T_1010 = mux(UInt<1>("h00"), UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
+    node _T_1011 = bits(io.store_data_r, 31, 0) @[lsu_dccm_ctl.scala 243:64]
+    node _T_1012 = cat(_T_1010, _T_1011) @[Cat.scala 29:58]
+    node _T_1013 = bits(io.lsu_addr_r, 1, 0) @[lsu_dccm_ctl.scala 243:92]
+    node _T_1014 = mul(UInt<4>("h08"), _T_1013) @[lsu_dccm_ctl.scala 243:78]
+    node _T_1015 = dshl(_T_1012, _T_1014) @[lsu_dccm_ctl.scala 243:72]
+    store_data_pre_r <= _T_1015 @[lsu_dccm_ctl.scala 243:29]
+    node _T_1016 = bits(store_data_pre_r, 63, 32) @[lsu_dccm_ctl.scala 244:48]
+    store_data_pre_hi_r <= _T_1016 @[lsu_dccm_ctl.scala 244:29]
+    node _T_1017 = bits(store_data_pre_r, 31, 0) @[lsu_dccm_ctl.scala 245:48]
+    store_data_pre_lo_r <= _T_1017 @[lsu_dccm_ctl.scala 245:29]
+    node _T_1018 = bits(store_byteen_ext_r, 0, 0) @[lsu_dccm_ctl.scala 246:98]
+    node _T_1019 = bits(_T_1018, 0, 0) @[lsu_dccm_ctl.scala 246:102]
+    node _T_1020 = bits(store_data_pre_lo_r, 7, 0) @[lsu_dccm_ctl.scala 246:130]
+    node _T_1021 = and(dccm_wren_Q, dccm_wr_bypass_d_m_lo_Q) @[lsu_dccm_ctl.scala 246:162]
+    node _T_1022 = bits(_T_1021, 0, 0) @[lsu_dccm_ctl.scala 246:189]
+    node _T_1023 = bits(dccm_wr_data_Q, 7, 0) @[lsu_dccm_ctl.scala 246:211]
+    node _T_1024 = bits(io.sec_data_lo_r, 7, 0) @[lsu_dccm_ctl.scala 246:241]
+    node _T_1025 = mux(_T_1022, _T_1023, _T_1024) @[lsu_dccm_ctl.scala 246:148]
+    node _T_1026 = mux(_T_1019, _T_1020, _T_1025) @[lsu_dccm_ctl.scala 246:79]
+    node _T_1027 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
+    node _T_1028 = xor(UInt<8>("h0ff"), _T_1027) @[Bitwise.scala 102:21]
+    node _T_1029 = shr(_T_1026, 4) @[Bitwise.scala 103:21]
+    node _T_1030 = and(_T_1029, _T_1028) @[Bitwise.scala 103:31]
+    node _T_1031 = bits(_T_1026, 3, 0) @[Bitwise.scala 103:46]
+    node _T_1032 = shl(_T_1031, 4) @[Bitwise.scala 103:65]
+    node _T_1033 = not(_T_1028) @[Bitwise.scala 103:77]
+    node _T_1034 = and(_T_1032, _T_1033) @[Bitwise.scala 103:75]
+    node _T_1035 = or(_T_1030, _T_1034) @[Bitwise.scala 103:39]
+    node _T_1036 = bits(_T_1028, 5, 0) @[Bitwise.scala 102:28]
+    node _T_1037 = shl(_T_1036, 2) @[Bitwise.scala 102:47]
+    node _T_1038 = xor(_T_1028, _T_1037) @[Bitwise.scala 102:21]
+    node _T_1039 = shr(_T_1035, 2) @[Bitwise.scala 103:21]
+    node _T_1040 = and(_T_1039, _T_1038) @[Bitwise.scala 103:31]
+    node _T_1041 = bits(_T_1035, 5, 0) @[Bitwise.scala 103:46]
+    node _T_1042 = shl(_T_1041, 2) @[Bitwise.scala 103:65]
+    node _T_1043 = not(_T_1038) @[Bitwise.scala 103:77]
+    node _T_1044 = and(_T_1042, _T_1043) @[Bitwise.scala 103:75]
+    node _T_1045 = or(_T_1040, _T_1044) @[Bitwise.scala 103:39]
+    node _T_1046 = bits(_T_1038, 6, 0) @[Bitwise.scala 102:28]
+    node _T_1047 = shl(_T_1046, 1) @[Bitwise.scala 102:47]
+    node _T_1048 = xor(_T_1038, _T_1047) @[Bitwise.scala 102:21]
+    node _T_1049 = shr(_T_1045, 1) @[Bitwise.scala 103:21]
+    node _T_1050 = and(_T_1049, _T_1048) @[Bitwise.scala 103:31]
+    node _T_1051 = bits(_T_1045, 6, 0) @[Bitwise.scala 103:46]
+    node _T_1052 = shl(_T_1051, 1) @[Bitwise.scala 103:65]
+    node _T_1053 = not(_T_1048) @[Bitwise.scala 103:77]
+    node _T_1054 = and(_T_1052, _T_1053) @[Bitwise.scala 103:75]
+    node _T_1055 = or(_T_1050, _T_1054) @[Bitwise.scala 103:39]
+    node _T_1056 = bits(store_byteen_ext_r, 1, 1) @[lsu_dccm_ctl.scala 246:98]
+    node _T_1057 = bits(_T_1056, 0, 0) @[lsu_dccm_ctl.scala 246:102]
+    node _T_1058 = bits(store_data_pre_lo_r, 15, 8) @[lsu_dccm_ctl.scala 246:130]
+    node _T_1059 = and(dccm_wren_Q, dccm_wr_bypass_d_m_lo_Q) @[lsu_dccm_ctl.scala 246:162]
+    node _T_1060 = bits(_T_1059, 0, 0) @[lsu_dccm_ctl.scala 246:189]
+    node _T_1061 = bits(dccm_wr_data_Q, 15, 8) @[lsu_dccm_ctl.scala 246:211]
+    node _T_1062 = bits(io.sec_data_lo_r, 15, 8) @[lsu_dccm_ctl.scala 246:241]
+    node _T_1063 = mux(_T_1060, _T_1061, _T_1062) @[lsu_dccm_ctl.scala 246:148]
+    node _T_1064 = mux(_T_1057, _T_1058, _T_1063) @[lsu_dccm_ctl.scala 246:79]
+    node _T_1065 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
+    node _T_1066 = xor(UInt<8>("h0ff"), _T_1065) @[Bitwise.scala 102:21]
+    node _T_1067 = shr(_T_1064, 4) @[Bitwise.scala 103:21]
+    node _T_1068 = and(_T_1067, _T_1066) @[Bitwise.scala 103:31]
+    node _T_1069 = bits(_T_1064, 3, 0) @[Bitwise.scala 103:46]
+    node _T_1070 = shl(_T_1069, 4) @[Bitwise.scala 103:65]
+    node _T_1071 = not(_T_1066) @[Bitwise.scala 103:77]
+    node _T_1072 = and(_T_1070, _T_1071) @[Bitwise.scala 103:75]
+    node _T_1073 = or(_T_1068, _T_1072) @[Bitwise.scala 103:39]
+    node _T_1074 = bits(_T_1066, 5, 0) @[Bitwise.scala 102:28]
+    node _T_1075 = shl(_T_1074, 2) @[Bitwise.scala 102:47]
+    node _T_1076 = xor(_T_1066, _T_1075) @[Bitwise.scala 102:21]
+    node _T_1077 = shr(_T_1073, 2) @[Bitwise.scala 103:21]
+    node _T_1078 = and(_T_1077, _T_1076) @[Bitwise.scala 103:31]
+    node _T_1079 = bits(_T_1073, 5, 0) @[Bitwise.scala 103:46]
+    node _T_1080 = shl(_T_1079, 2) @[Bitwise.scala 103:65]
+    node _T_1081 = not(_T_1076) @[Bitwise.scala 103:77]
+    node _T_1082 = and(_T_1080, _T_1081) @[Bitwise.scala 103:75]
+    node _T_1083 = or(_T_1078, _T_1082) @[Bitwise.scala 103:39]
+    node _T_1084 = bits(_T_1076, 6, 0) @[Bitwise.scala 102:28]
+    node _T_1085 = shl(_T_1084, 1) @[Bitwise.scala 102:47]
+    node _T_1086 = xor(_T_1076, _T_1085) @[Bitwise.scala 102:21]
+    node _T_1087 = shr(_T_1083, 1) @[Bitwise.scala 103:21]
+    node _T_1088 = and(_T_1087, _T_1086) @[Bitwise.scala 103:31]
+    node _T_1089 = bits(_T_1083, 6, 0) @[Bitwise.scala 103:46]
+    node _T_1090 = shl(_T_1089, 1) @[Bitwise.scala 103:65]
+    node _T_1091 = not(_T_1086) @[Bitwise.scala 103:77]
+    node _T_1092 = and(_T_1090, _T_1091) @[Bitwise.scala 103:75]
+    node _T_1093 = or(_T_1088, _T_1092) @[Bitwise.scala 103:39]
+    node _T_1094 = bits(store_byteen_ext_r, 2, 2) @[lsu_dccm_ctl.scala 246:98]
+    node _T_1095 = bits(_T_1094, 0, 0) @[lsu_dccm_ctl.scala 246:102]
+    node _T_1096 = bits(store_data_pre_lo_r, 23, 16) @[lsu_dccm_ctl.scala 246:130]
+    node _T_1097 = and(dccm_wren_Q, dccm_wr_bypass_d_m_lo_Q) @[lsu_dccm_ctl.scala 246:162]
+    node _T_1098 = bits(_T_1097, 0, 0) @[lsu_dccm_ctl.scala 246:189]
+    node _T_1099 = bits(dccm_wr_data_Q, 23, 16) @[lsu_dccm_ctl.scala 246:211]
+    node _T_1100 = bits(io.sec_data_lo_r, 23, 16) @[lsu_dccm_ctl.scala 246:241]
+    node _T_1101 = mux(_T_1098, _T_1099, _T_1100) @[lsu_dccm_ctl.scala 246:148]
+    node _T_1102 = mux(_T_1095, _T_1096, _T_1101) @[lsu_dccm_ctl.scala 246:79]
+    node _T_1103 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
+    node _T_1104 = xor(UInt<8>("h0ff"), _T_1103) @[Bitwise.scala 102:21]
+    node _T_1105 = shr(_T_1102, 4) @[Bitwise.scala 103:21]
+    node _T_1106 = and(_T_1105, _T_1104) @[Bitwise.scala 103:31]
+    node _T_1107 = bits(_T_1102, 3, 0) @[Bitwise.scala 103:46]
+    node _T_1108 = shl(_T_1107, 4) @[Bitwise.scala 103:65]
+    node _T_1109 = not(_T_1104) @[Bitwise.scala 103:77]
+    node _T_1110 = and(_T_1108, _T_1109) @[Bitwise.scala 103:75]
+    node _T_1111 = or(_T_1106, _T_1110) @[Bitwise.scala 103:39]
+    node _T_1112 = bits(_T_1104, 5, 0) @[Bitwise.scala 102:28]
+    node _T_1113 = shl(_T_1112, 2) @[Bitwise.scala 102:47]
+    node _T_1114 = xor(_T_1104, _T_1113) @[Bitwise.scala 102:21]
+    node _T_1115 = shr(_T_1111, 2) @[Bitwise.scala 103:21]
+    node _T_1116 = and(_T_1115, _T_1114) @[Bitwise.scala 103:31]
+    node _T_1117 = bits(_T_1111, 5, 0) @[Bitwise.scala 103:46]
+    node _T_1118 = shl(_T_1117, 2) @[Bitwise.scala 103:65]
+    node _T_1119 = not(_T_1114) @[Bitwise.scala 103:77]
+    node _T_1120 = and(_T_1118, _T_1119) @[Bitwise.scala 103:75]
+    node _T_1121 = or(_T_1116, _T_1120) @[Bitwise.scala 103:39]
+    node _T_1122 = bits(_T_1114, 6, 0) @[Bitwise.scala 102:28]
+    node _T_1123 = shl(_T_1122, 1) @[Bitwise.scala 102:47]
+    node _T_1124 = xor(_T_1114, _T_1123) @[Bitwise.scala 102:21]
+    node _T_1125 = shr(_T_1121, 1) @[Bitwise.scala 103:21]
+    node _T_1126 = and(_T_1125, _T_1124) @[Bitwise.scala 103:31]
+    node _T_1127 = bits(_T_1121, 6, 0) @[Bitwise.scala 103:46]
+    node _T_1128 = shl(_T_1127, 1) @[Bitwise.scala 103:65]
+    node _T_1129 = not(_T_1124) @[Bitwise.scala 103:77]
+    node _T_1130 = and(_T_1128, _T_1129) @[Bitwise.scala 103:75]
+    node _T_1131 = or(_T_1126, _T_1130) @[Bitwise.scala 103:39]
+    node _T_1132 = bits(store_byteen_ext_r, 3, 3) @[lsu_dccm_ctl.scala 246:98]
+    node _T_1133 = bits(_T_1132, 0, 0) @[lsu_dccm_ctl.scala 246:102]
+    node _T_1134 = bits(store_data_pre_lo_r, 31, 24) @[lsu_dccm_ctl.scala 246:130]
+    node _T_1135 = and(dccm_wren_Q, dccm_wr_bypass_d_m_lo_Q) @[lsu_dccm_ctl.scala 246:162]
+    node _T_1136 = bits(_T_1135, 0, 0) @[lsu_dccm_ctl.scala 246:189]
+    node _T_1137 = bits(dccm_wr_data_Q, 31, 24) @[lsu_dccm_ctl.scala 246:211]
+    node _T_1138 = bits(io.sec_data_lo_r, 31, 24) @[lsu_dccm_ctl.scala 246:241]
+    node _T_1139 = mux(_T_1136, _T_1137, _T_1138) @[lsu_dccm_ctl.scala 246:148]
+    node _T_1140 = mux(_T_1133, _T_1134, _T_1139) @[lsu_dccm_ctl.scala 246:79]
+    node _T_1141 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
+    node _T_1142 = xor(UInt<8>("h0ff"), _T_1141) @[Bitwise.scala 102:21]
+    node _T_1143 = shr(_T_1140, 4) @[Bitwise.scala 103:21]
+    node _T_1144 = and(_T_1143, _T_1142) @[Bitwise.scala 103:31]
+    node _T_1145 = bits(_T_1140, 3, 0) @[Bitwise.scala 103:46]
+    node _T_1146 = shl(_T_1145, 4) @[Bitwise.scala 103:65]
+    node _T_1147 = not(_T_1142) @[Bitwise.scala 103:77]
+    node _T_1148 = and(_T_1146, _T_1147) @[Bitwise.scala 103:75]
+    node _T_1149 = or(_T_1144, _T_1148) @[Bitwise.scala 103:39]
+    node _T_1150 = bits(_T_1142, 5, 0) @[Bitwise.scala 102:28]
+    node _T_1151 = shl(_T_1150, 2) @[Bitwise.scala 102:47]
+    node _T_1152 = xor(_T_1142, _T_1151) @[Bitwise.scala 102:21]
+    node _T_1153 = shr(_T_1149, 2) @[Bitwise.scala 103:21]
+    node _T_1154 = and(_T_1153, _T_1152) @[Bitwise.scala 103:31]
+    node _T_1155 = bits(_T_1149, 5, 0) @[Bitwise.scala 103:46]
+    node _T_1156 = shl(_T_1155, 2) @[Bitwise.scala 103:65]
+    node _T_1157 = not(_T_1152) @[Bitwise.scala 103:77]
+    node _T_1158 = and(_T_1156, _T_1157) @[Bitwise.scala 103:75]
+    node _T_1159 = or(_T_1154, _T_1158) @[Bitwise.scala 103:39]
+    node _T_1160 = bits(_T_1152, 6, 0) @[Bitwise.scala 102:28]
+    node _T_1161 = shl(_T_1160, 1) @[Bitwise.scala 102:47]
+    node _T_1162 = xor(_T_1152, _T_1161) @[Bitwise.scala 102:21]
+    node _T_1163 = shr(_T_1159, 1) @[Bitwise.scala 103:21]
+    node _T_1164 = and(_T_1163, _T_1162) @[Bitwise.scala 103:31]
+    node _T_1165 = bits(_T_1159, 6, 0) @[Bitwise.scala 103:46]
+    node _T_1166 = shl(_T_1165, 1) @[Bitwise.scala 103:65]
+    node _T_1167 = not(_T_1162) @[Bitwise.scala 103:77]
+    node _T_1168 = and(_T_1166, _T_1167) @[Bitwise.scala 103:75]
+    node _T_1169 = or(_T_1164, _T_1168) @[Bitwise.scala 103:39]
+    wire _T_1170 : UInt<8>[4] @[lsu_dccm_ctl.scala 246:63]
+    _T_1170[0] <= _T_1055 @[lsu_dccm_ctl.scala 246:63]
+    _T_1170[1] <= _T_1093 @[lsu_dccm_ctl.scala 246:63]
+    _T_1170[2] <= _T_1131 @[lsu_dccm_ctl.scala 246:63]
+    _T_1170[3] <= _T_1169 @[lsu_dccm_ctl.scala 246:63]
+    node _T_1171 = cat(_T_1170[2], _T_1170[3]) @[Cat.scala 29:58]
+    node _T_1172 = cat(_T_1170[0], _T_1170[1]) @[Cat.scala 29:58]
+    node _T_1173 = cat(_T_1172, _T_1171) @[Cat.scala 29:58]
+    node _T_1174 = shl(UInt<16>("h0ffff"), 16) @[Bitwise.scala 102:47]
+    node _T_1175 = xor(UInt<32>("h0ffffffff"), _T_1174) @[Bitwise.scala 102:21]
+    node _T_1176 = shr(_T_1173, 16) @[Bitwise.scala 103:21]
+    node _T_1177 = and(_T_1176, _T_1175) @[Bitwise.scala 103:31]
+    node _T_1178 = bits(_T_1173, 15, 0) @[Bitwise.scala 103:46]
+    node _T_1179 = shl(_T_1178, 16) @[Bitwise.scala 103:65]
+    node _T_1180 = not(_T_1175) @[Bitwise.scala 103:77]
+    node _T_1181 = and(_T_1179, _T_1180) @[Bitwise.scala 103:75]
+    node _T_1182 = or(_T_1177, _T_1181) @[Bitwise.scala 103:39]
+    node _T_1183 = bits(_T_1175, 23, 0) @[Bitwise.scala 102:28]
+    node _T_1184 = shl(_T_1183, 8) @[Bitwise.scala 102:47]
+    node _T_1185 = xor(_T_1175, _T_1184) @[Bitwise.scala 102:21]
+    node _T_1186 = shr(_T_1182, 8) @[Bitwise.scala 103:21]
+    node _T_1187 = and(_T_1186, _T_1185) @[Bitwise.scala 103:31]
+    node _T_1188 = bits(_T_1182, 23, 0) @[Bitwise.scala 103:46]
+    node _T_1189 = shl(_T_1188, 8) @[Bitwise.scala 103:65]
+    node _T_1190 = not(_T_1185) @[Bitwise.scala 103:77]
+    node _T_1191 = and(_T_1189, _T_1190) @[Bitwise.scala 103:75]
+    node _T_1192 = or(_T_1187, _T_1191) @[Bitwise.scala 103:39]
+    node _T_1193 = bits(_T_1185, 27, 0) @[Bitwise.scala 102:28]
+    node _T_1194 = shl(_T_1193, 4) @[Bitwise.scala 102:47]
+    node _T_1195 = xor(_T_1185, _T_1194) @[Bitwise.scala 102:21]
+    node _T_1196 = shr(_T_1192, 4) @[Bitwise.scala 103:21]
+    node _T_1197 = and(_T_1196, _T_1195) @[Bitwise.scala 103:31]
+    node _T_1198 = bits(_T_1192, 27, 0) @[Bitwise.scala 103:46]
+    node _T_1199 = shl(_T_1198, 4) @[Bitwise.scala 103:65]
+    node _T_1200 = not(_T_1195) @[Bitwise.scala 103:77]
+    node _T_1201 = and(_T_1199, _T_1200) @[Bitwise.scala 103:75]
+    node _T_1202 = or(_T_1197, _T_1201) @[Bitwise.scala 103:39]
+    node _T_1203 = bits(_T_1195, 29, 0) @[Bitwise.scala 102:28]
+    node _T_1204 = shl(_T_1203, 2) @[Bitwise.scala 102:47]
+    node _T_1205 = xor(_T_1195, _T_1204) @[Bitwise.scala 102:21]
+    node _T_1206 = shr(_T_1202, 2) @[Bitwise.scala 103:21]
+    node _T_1207 = and(_T_1206, _T_1205) @[Bitwise.scala 103:31]
+    node _T_1208 = bits(_T_1202, 29, 0) @[Bitwise.scala 103:46]
+    node _T_1209 = shl(_T_1208, 2) @[Bitwise.scala 103:65]
+    node _T_1210 = not(_T_1205) @[Bitwise.scala 103:77]
+    node _T_1211 = and(_T_1209, _T_1210) @[Bitwise.scala 103:75]
+    node _T_1212 = or(_T_1207, _T_1211) @[Bitwise.scala 103:39]
+    node _T_1213 = bits(_T_1205, 30, 0) @[Bitwise.scala 102:28]
+    node _T_1214 = shl(_T_1213, 1) @[Bitwise.scala 102:47]
+    node _T_1215 = xor(_T_1205, _T_1214) @[Bitwise.scala 102:21]
+    node _T_1216 = shr(_T_1212, 1) @[Bitwise.scala 103:21]
+    node _T_1217 = and(_T_1216, _T_1215) @[Bitwise.scala 103:31]
+    node _T_1218 = bits(_T_1212, 30, 0) @[Bitwise.scala 103:46]
+    node _T_1219 = shl(_T_1218, 1) @[Bitwise.scala 103:65]
+    node _T_1220 = not(_T_1215) @[Bitwise.scala 103:77]
+    node _T_1221 = and(_T_1219, _T_1220) @[Bitwise.scala 103:75]
+    node _T_1222 = or(_T_1217, _T_1221) @[Bitwise.scala 103:39]
+    io.store_data_lo_r <= _T_1222 @[lsu_dccm_ctl.scala 246:29]
+    node _T_1223 = bits(store_byteen_ext_r, 4, 4) @[lsu_dccm_ctl.scala 247:98]
+    node _T_1224 = bits(_T_1223, 0, 0) @[lsu_dccm_ctl.scala 247:104]
+    node _T_1225 = bits(store_data_pre_hi_r, 7, 0) @[lsu_dccm_ctl.scala 247:130]
+    node _T_1226 = and(dccm_wren_Q, dccm_wr_bypass_d_m_hi_Q) @[lsu_dccm_ctl.scala 247:162]
+    node _T_1227 = bits(_T_1226, 0, 0) @[lsu_dccm_ctl.scala 247:189]
+    node _T_1228 = bits(dccm_wr_data_Q, 7, 0) @[lsu_dccm_ctl.scala 247:211]
+    node _T_1229 = bits(io.sec_data_hi_r, 7, 0) @[lsu_dccm_ctl.scala 247:241]
+    node _T_1230 = mux(_T_1227, _T_1228, _T_1229) @[lsu_dccm_ctl.scala 247:148]
+    node _T_1231 = mux(_T_1224, _T_1225, _T_1230) @[lsu_dccm_ctl.scala 247:79]
+    node _T_1232 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
+    node _T_1233 = xor(UInt<8>("h0ff"), _T_1232) @[Bitwise.scala 102:21]
+    node _T_1234 = shr(_T_1231, 4) @[Bitwise.scala 103:21]
+    node _T_1235 = and(_T_1234, _T_1233) @[Bitwise.scala 103:31]
+    node _T_1236 = bits(_T_1231, 3, 0) @[Bitwise.scala 103:46]
+    node _T_1237 = shl(_T_1236, 4) @[Bitwise.scala 103:65]
+    node _T_1238 = not(_T_1233) @[Bitwise.scala 103:77]
+    node _T_1239 = and(_T_1237, _T_1238) @[Bitwise.scala 103:75]
+    node _T_1240 = or(_T_1235, _T_1239) @[Bitwise.scala 103:39]
+    node _T_1241 = bits(_T_1233, 5, 0) @[Bitwise.scala 102:28]
+    node _T_1242 = shl(_T_1241, 2) @[Bitwise.scala 102:47]
+    node _T_1243 = xor(_T_1233, _T_1242) @[Bitwise.scala 102:21]
+    node _T_1244 = shr(_T_1240, 2) @[Bitwise.scala 103:21]
+    node _T_1245 = and(_T_1244, _T_1243) @[Bitwise.scala 103:31]
+    node _T_1246 = bits(_T_1240, 5, 0) @[Bitwise.scala 103:46]
+    node _T_1247 = shl(_T_1246, 2) @[Bitwise.scala 103:65]
+    node _T_1248 = not(_T_1243) @[Bitwise.scala 103:77]
+    node _T_1249 = and(_T_1247, _T_1248) @[Bitwise.scala 103:75]
+    node _T_1250 = or(_T_1245, _T_1249) @[Bitwise.scala 103:39]
+    node _T_1251 = bits(_T_1243, 6, 0) @[Bitwise.scala 102:28]
+    node _T_1252 = shl(_T_1251, 1) @[Bitwise.scala 102:47]
+    node _T_1253 = xor(_T_1243, _T_1252) @[Bitwise.scala 102:21]
+    node _T_1254 = shr(_T_1250, 1) @[Bitwise.scala 103:21]
+    node _T_1255 = and(_T_1254, _T_1253) @[Bitwise.scala 103:31]
+    node _T_1256 = bits(_T_1250, 6, 0) @[Bitwise.scala 103:46]
+    node _T_1257 = shl(_T_1256, 1) @[Bitwise.scala 103:65]
+    node _T_1258 = not(_T_1253) @[Bitwise.scala 103:77]
+    node _T_1259 = and(_T_1257, _T_1258) @[Bitwise.scala 103:75]
+    node _T_1260 = or(_T_1255, _T_1259) @[Bitwise.scala 103:39]
+    node _T_1261 = bits(store_byteen_ext_r, 5, 5) @[lsu_dccm_ctl.scala 247:98]
+    node _T_1262 = bits(_T_1261, 0, 0) @[lsu_dccm_ctl.scala 247:104]
+    node _T_1263 = bits(store_data_pre_hi_r, 15, 8) @[lsu_dccm_ctl.scala 247:130]
+    node _T_1264 = and(dccm_wren_Q, dccm_wr_bypass_d_m_hi_Q) @[lsu_dccm_ctl.scala 247:162]
+    node _T_1265 = bits(_T_1264, 0, 0) @[lsu_dccm_ctl.scala 247:189]
+    node _T_1266 = bits(dccm_wr_data_Q, 15, 8) @[lsu_dccm_ctl.scala 247:211]
+    node _T_1267 = bits(io.sec_data_hi_r, 15, 8) @[lsu_dccm_ctl.scala 247:241]
+    node _T_1268 = mux(_T_1265, _T_1266, _T_1267) @[lsu_dccm_ctl.scala 247:148]
+    node _T_1269 = mux(_T_1262, _T_1263, _T_1268) @[lsu_dccm_ctl.scala 247:79]
+    node _T_1270 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
+    node _T_1271 = xor(UInt<8>("h0ff"), _T_1270) @[Bitwise.scala 102:21]
+    node _T_1272 = shr(_T_1269, 4) @[Bitwise.scala 103:21]
+    node _T_1273 = and(_T_1272, _T_1271) @[Bitwise.scala 103:31]
+    node _T_1274 = bits(_T_1269, 3, 0) @[Bitwise.scala 103:46]
+    node _T_1275 = shl(_T_1274, 4) @[Bitwise.scala 103:65]
+    node _T_1276 = not(_T_1271) @[Bitwise.scala 103:77]
+    node _T_1277 = and(_T_1275, _T_1276) @[Bitwise.scala 103:75]
+    node _T_1278 = or(_T_1273, _T_1277) @[Bitwise.scala 103:39]
+    node _T_1279 = bits(_T_1271, 5, 0) @[Bitwise.scala 102:28]
+    node _T_1280 = shl(_T_1279, 2) @[Bitwise.scala 102:47]
+    node _T_1281 = xor(_T_1271, _T_1280) @[Bitwise.scala 102:21]
+    node _T_1282 = shr(_T_1278, 2) @[Bitwise.scala 103:21]
+    node _T_1283 = and(_T_1282, _T_1281) @[Bitwise.scala 103:31]
+    node _T_1284 = bits(_T_1278, 5, 0) @[Bitwise.scala 103:46]
+    node _T_1285 = shl(_T_1284, 2) @[Bitwise.scala 103:65]
+    node _T_1286 = not(_T_1281) @[Bitwise.scala 103:77]
+    node _T_1287 = and(_T_1285, _T_1286) @[Bitwise.scala 103:75]
+    node _T_1288 = or(_T_1283, _T_1287) @[Bitwise.scala 103:39]
+    node _T_1289 = bits(_T_1281, 6, 0) @[Bitwise.scala 102:28]
+    node _T_1290 = shl(_T_1289, 1) @[Bitwise.scala 102:47]
+    node _T_1291 = xor(_T_1281, _T_1290) @[Bitwise.scala 102:21]
+    node _T_1292 = shr(_T_1288, 1) @[Bitwise.scala 103:21]
+    node _T_1293 = and(_T_1292, _T_1291) @[Bitwise.scala 103:31]
+    node _T_1294 = bits(_T_1288, 6, 0) @[Bitwise.scala 103:46]
+    node _T_1295 = shl(_T_1294, 1) @[Bitwise.scala 103:65]
+    node _T_1296 = not(_T_1291) @[Bitwise.scala 103:77]
+    node _T_1297 = and(_T_1295, _T_1296) @[Bitwise.scala 103:75]
+    node _T_1298 = or(_T_1293, _T_1297) @[Bitwise.scala 103:39]
+    node _T_1299 = bits(store_byteen_ext_r, 6, 6) @[lsu_dccm_ctl.scala 247:98]
+    node _T_1300 = bits(_T_1299, 0, 0) @[lsu_dccm_ctl.scala 247:104]
+    node _T_1301 = bits(store_data_pre_hi_r, 23, 16) @[lsu_dccm_ctl.scala 247:130]
+    node _T_1302 = and(dccm_wren_Q, dccm_wr_bypass_d_m_hi_Q) @[lsu_dccm_ctl.scala 247:162]
+    node _T_1303 = bits(_T_1302, 0, 0) @[lsu_dccm_ctl.scala 247:189]
+    node _T_1304 = bits(dccm_wr_data_Q, 23, 16) @[lsu_dccm_ctl.scala 247:211]
+    node _T_1305 = bits(io.sec_data_hi_r, 23, 16) @[lsu_dccm_ctl.scala 247:241]
+    node _T_1306 = mux(_T_1303, _T_1304, _T_1305) @[lsu_dccm_ctl.scala 247:148]
+    node _T_1307 = mux(_T_1300, _T_1301, _T_1306) @[lsu_dccm_ctl.scala 247:79]
+    node _T_1308 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
+    node _T_1309 = xor(UInt<8>("h0ff"), _T_1308) @[Bitwise.scala 102:21]
+    node _T_1310 = shr(_T_1307, 4) @[Bitwise.scala 103:21]
+    node _T_1311 = and(_T_1310, _T_1309) @[Bitwise.scala 103:31]
+    node _T_1312 = bits(_T_1307, 3, 0) @[Bitwise.scala 103:46]
+    node _T_1313 = shl(_T_1312, 4) @[Bitwise.scala 103:65]
+    node _T_1314 = not(_T_1309) @[Bitwise.scala 103:77]
+    node _T_1315 = and(_T_1313, _T_1314) @[Bitwise.scala 103:75]
+    node _T_1316 = or(_T_1311, _T_1315) @[Bitwise.scala 103:39]
+    node _T_1317 = bits(_T_1309, 5, 0) @[Bitwise.scala 102:28]
+    node _T_1318 = shl(_T_1317, 2) @[Bitwise.scala 102:47]
+    node _T_1319 = xor(_T_1309, _T_1318) @[Bitwise.scala 102:21]
+    node _T_1320 = shr(_T_1316, 2) @[Bitwise.scala 103:21]
+    node _T_1321 = and(_T_1320, _T_1319) @[Bitwise.scala 103:31]
+    node _T_1322 = bits(_T_1316, 5, 0) @[Bitwise.scala 103:46]
+    node _T_1323 = shl(_T_1322, 2) @[Bitwise.scala 103:65]
+    node _T_1324 = not(_T_1319) @[Bitwise.scala 103:77]
+    node _T_1325 = and(_T_1323, _T_1324) @[Bitwise.scala 103:75]
+    node _T_1326 = or(_T_1321, _T_1325) @[Bitwise.scala 103:39]
+    node _T_1327 = bits(_T_1319, 6, 0) @[Bitwise.scala 102:28]
+    node _T_1328 = shl(_T_1327, 1) @[Bitwise.scala 102:47]
+    node _T_1329 = xor(_T_1319, _T_1328) @[Bitwise.scala 102:21]
+    node _T_1330 = shr(_T_1326, 1) @[Bitwise.scala 103:21]
+    node _T_1331 = and(_T_1330, _T_1329) @[Bitwise.scala 103:31]
+    node _T_1332 = bits(_T_1326, 6, 0) @[Bitwise.scala 103:46]
+    node _T_1333 = shl(_T_1332, 1) @[Bitwise.scala 103:65]
+    node _T_1334 = not(_T_1329) @[Bitwise.scala 103:77]
+    node _T_1335 = and(_T_1333, _T_1334) @[Bitwise.scala 103:75]
+    node _T_1336 = or(_T_1331, _T_1335) @[Bitwise.scala 103:39]
+    node _T_1337 = bits(store_byteen_ext_r, 7, 7) @[lsu_dccm_ctl.scala 247:98]
+    node _T_1338 = bits(_T_1337, 0, 0) @[lsu_dccm_ctl.scala 247:104]
+    node _T_1339 = bits(store_data_pre_hi_r, 31, 24) @[lsu_dccm_ctl.scala 247:130]
+    node _T_1340 = and(dccm_wren_Q, dccm_wr_bypass_d_m_hi_Q) @[lsu_dccm_ctl.scala 247:162]
+    node _T_1341 = bits(_T_1340, 0, 0) @[lsu_dccm_ctl.scala 247:189]
+    node _T_1342 = bits(dccm_wr_data_Q, 31, 24) @[lsu_dccm_ctl.scala 247:211]
+    node _T_1343 = bits(io.sec_data_hi_r, 31, 24) @[lsu_dccm_ctl.scala 247:241]
+    node _T_1344 = mux(_T_1341, _T_1342, _T_1343) @[lsu_dccm_ctl.scala 247:148]
+    node _T_1345 = mux(_T_1338, _T_1339, _T_1344) @[lsu_dccm_ctl.scala 247:79]
+    node _T_1346 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
+    node _T_1347 = xor(UInt<8>("h0ff"), _T_1346) @[Bitwise.scala 102:21]
+    node _T_1348 = shr(_T_1345, 4) @[Bitwise.scala 103:21]
+    node _T_1349 = and(_T_1348, _T_1347) @[Bitwise.scala 103:31]
+    node _T_1350 = bits(_T_1345, 3, 0) @[Bitwise.scala 103:46]
+    node _T_1351 = shl(_T_1350, 4) @[Bitwise.scala 103:65]
+    node _T_1352 = not(_T_1347) @[Bitwise.scala 103:77]
+    node _T_1353 = and(_T_1351, _T_1352) @[Bitwise.scala 103:75]
+    node _T_1354 = or(_T_1349, _T_1353) @[Bitwise.scala 103:39]
+    node _T_1355 = bits(_T_1347, 5, 0) @[Bitwise.scala 102:28]
+    node _T_1356 = shl(_T_1355, 2) @[Bitwise.scala 102:47]
+    node _T_1357 = xor(_T_1347, _T_1356) @[Bitwise.scala 102:21]
+    node _T_1358 = shr(_T_1354, 2) @[Bitwise.scala 103:21]
+    node _T_1359 = and(_T_1358, _T_1357) @[Bitwise.scala 103:31]
+    node _T_1360 = bits(_T_1354, 5, 0) @[Bitwise.scala 103:46]
+    node _T_1361 = shl(_T_1360, 2) @[Bitwise.scala 103:65]
+    node _T_1362 = not(_T_1357) @[Bitwise.scala 103:77]
+    node _T_1363 = and(_T_1361, _T_1362) @[Bitwise.scala 103:75]
+    node _T_1364 = or(_T_1359, _T_1363) @[Bitwise.scala 103:39]
+    node _T_1365 = bits(_T_1357, 6, 0) @[Bitwise.scala 102:28]
+    node _T_1366 = shl(_T_1365, 1) @[Bitwise.scala 102:47]
+    node _T_1367 = xor(_T_1357, _T_1366) @[Bitwise.scala 102:21]
+    node _T_1368 = shr(_T_1364, 1) @[Bitwise.scala 103:21]
+    node _T_1369 = and(_T_1368, _T_1367) @[Bitwise.scala 103:31]
+    node _T_1370 = bits(_T_1364, 6, 0) @[Bitwise.scala 103:46]
+    node _T_1371 = shl(_T_1370, 1) @[Bitwise.scala 103:65]
+    node _T_1372 = not(_T_1367) @[Bitwise.scala 103:77]
+    node _T_1373 = and(_T_1371, _T_1372) @[Bitwise.scala 103:75]
+    node _T_1374 = or(_T_1369, _T_1373) @[Bitwise.scala 103:39]
+    wire _T_1375 : UInt<8>[4] @[lsu_dccm_ctl.scala 247:63]
+    _T_1375[0] <= _T_1260 @[lsu_dccm_ctl.scala 247:63]
+    _T_1375[1] <= _T_1298 @[lsu_dccm_ctl.scala 247:63]
+    _T_1375[2] <= _T_1336 @[lsu_dccm_ctl.scala 247:63]
+    _T_1375[3] <= _T_1374 @[lsu_dccm_ctl.scala 247:63]
+    node _T_1376 = cat(_T_1375[2], _T_1375[3]) @[Cat.scala 29:58]
+    node _T_1377 = cat(_T_1375[0], _T_1375[1]) @[Cat.scala 29:58]
+    node _T_1378 = cat(_T_1377, _T_1376) @[Cat.scala 29:58]
+    node _T_1379 = shl(UInt<16>("h0ffff"), 16) @[Bitwise.scala 102:47]
+    node _T_1380 = xor(UInt<32>("h0ffffffff"), _T_1379) @[Bitwise.scala 102:21]
+    node _T_1381 = shr(_T_1378, 16) @[Bitwise.scala 103:21]
+    node _T_1382 = and(_T_1381, _T_1380) @[Bitwise.scala 103:31]
+    node _T_1383 = bits(_T_1378, 15, 0) @[Bitwise.scala 103:46]
+    node _T_1384 = shl(_T_1383, 16) @[Bitwise.scala 103:65]
+    node _T_1385 = not(_T_1380) @[Bitwise.scala 103:77]
+    node _T_1386 = and(_T_1384, _T_1385) @[Bitwise.scala 103:75]
+    node _T_1387 = or(_T_1382, _T_1386) @[Bitwise.scala 103:39]
+    node _T_1388 = bits(_T_1380, 23, 0) @[Bitwise.scala 102:28]
+    node _T_1389 = shl(_T_1388, 8) @[Bitwise.scala 102:47]
+    node _T_1390 = xor(_T_1380, _T_1389) @[Bitwise.scala 102:21]
+    node _T_1391 = shr(_T_1387, 8) @[Bitwise.scala 103:21]
+    node _T_1392 = and(_T_1391, _T_1390) @[Bitwise.scala 103:31]
+    node _T_1393 = bits(_T_1387, 23, 0) @[Bitwise.scala 103:46]
+    node _T_1394 = shl(_T_1393, 8) @[Bitwise.scala 103:65]
+    node _T_1395 = not(_T_1390) @[Bitwise.scala 103:77]
+    node _T_1396 = and(_T_1394, _T_1395) @[Bitwise.scala 103:75]
+    node _T_1397 = or(_T_1392, _T_1396) @[Bitwise.scala 103:39]
+    node _T_1398 = bits(_T_1390, 27, 0) @[Bitwise.scala 102:28]
+    node _T_1399 = shl(_T_1398, 4) @[Bitwise.scala 102:47]
+    node _T_1400 = xor(_T_1390, _T_1399) @[Bitwise.scala 102:21]
+    node _T_1401 = shr(_T_1397, 4) @[Bitwise.scala 103:21]
+    node _T_1402 = and(_T_1401, _T_1400) @[Bitwise.scala 103:31]
+    node _T_1403 = bits(_T_1397, 27, 0) @[Bitwise.scala 103:46]
+    node _T_1404 = shl(_T_1403, 4) @[Bitwise.scala 103:65]
+    node _T_1405 = not(_T_1400) @[Bitwise.scala 103:77]
+    node _T_1406 = and(_T_1404, _T_1405) @[Bitwise.scala 103:75]
+    node _T_1407 = or(_T_1402, _T_1406) @[Bitwise.scala 103:39]
+    node _T_1408 = bits(_T_1400, 29, 0) @[Bitwise.scala 102:28]
+    node _T_1409 = shl(_T_1408, 2) @[Bitwise.scala 102:47]
+    node _T_1410 = xor(_T_1400, _T_1409) @[Bitwise.scala 102:21]
+    node _T_1411 = shr(_T_1407, 2) @[Bitwise.scala 103:21]
+    node _T_1412 = and(_T_1411, _T_1410) @[Bitwise.scala 103:31]
+    node _T_1413 = bits(_T_1407, 29, 0) @[Bitwise.scala 103:46]
+    node _T_1414 = shl(_T_1413, 2) @[Bitwise.scala 103:65]
+    node _T_1415 = not(_T_1410) @[Bitwise.scala 103:77]
+    node _T_1416 = and(_T_1414, _T_1415) @[Bitwise.scala 103:75]
+    node _T_1417 = or(_T_1412, _T_1416) @[Bitwise.scala 103:39]
+    node _T_1418 = bits(_T_1410, 30, 0) @[Bitwise.scala 102:28]
+    node _T_1419 = shl(_T_1418, 1) @[Bitwise.scala 102:47]
+    node _T_1420 = xor(_T_1410, _T_1419) @[Bitwise.scala 102:21]
+    node _T_1421 = shr(_T_1417, 1) @[Bitwise.scala 103:21]
+    node _T_1422 = and(_T_1421, _T_1420) @[Bitwise.scala 103:31]
+    node _T_1423 = bits(_T_1417, 30, 0) @[Bitwise.scala 103:46]
+    node _T_1424 = shl(_T_1423, 1) @[Bitwise.scala 103:65]
+    node _T_1425 = not(_T_1420) @[Bitwise.scala 103:77]
+    node _T_1426 = and(_T_1424, _T_1425) @[Bitwise.scala 103:75]
+    node _T_1427 = or(_T_1422, _T_1426) @[Bitwise.scala 103:39]
+    io.store_data_hi_r <= _T_1427 @[lsu_dccm_ctl.scala 247:29]
+    node _T_1428 = bits(store_byteen_ext_r, 0, 0) @[lsu_dccm_ctl.scala 248:98]
+    node _T_1429 = bits(_T_1428, 0, 0) @[lsu_dccm_ctl.scala 248:102]
+    node _T_1430 = bits(store_data_pre_lo_r, 7, 0) @[lsu_dccm_ctl.scala 248:130]
+    node _T_1431 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_lo) @[lsu_dccm_ctl.scala 248:174]
+    node _T_1432 = bits(_T_1431, 0, 0) @[lsu_dccm_ctl.scala 248:199]
+    node _T_1433 = bits(io.stbuf_data_any, 7, 0) @[lsu_dccm_ctl.scala 248:223]
+    node _T_1434 = and(dccm_wren_Q, dccm_wr_bypass_d_m_lo_Q) @[lsu_dccm_ctl.scala 248:256]
+    node _T_1435 = bits(_T_1434, 0, 0) @[lsu_dccm_ctl.scala 248:283]
+    node _T_1436 = bits(dccm_wr_data_Q, 7, 0) @[lsu_dccm_ctl.scala 248:305]
+    node _T_1437 = bits(io.sec_data_lo_r, 7, 0) @[lsu_dccm_ctl.scala 248:335]
+    node _T_1438 = mux(_T_1435, _T_1436, _T_1437) @[lsu_dccm_ctl.scala 248:242]
+    node _T_1439 = mux(_T_1432, _T_1433, _T_1438) @[lsu_dccm_ctl.scala 248:148]
+    node _T_1440 = mux(_T_1429, _T_1430, _T_1439) @[lsu_dccm_ctl.scala 248:79]
+    node _T_1441 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
+    node _T_1442 = xor(UInt<8>("h0ff"), _T_1441) @[Bitwise.scala 102:21]
+    node _T_1443 = shr(_T_1440, 4) @[Bitwise.scala 103:21]
+    node _T_1444 = and(_T_1443, _T_1442) @[Bitwise.scala 103:31]
+    node _T_1445 = bits(_T_1440, 3, 0) @[Bitwise.scala 103:46]
+    node _T_1446 = shl(_T_1445, 4) @[Bitwise.scala 103:65]
+    node _T_1447 = not(_T_1442) @[Bitwise.scala 103:77]
+    node _T_1448 = and(_T_1446, _T_1447) @[Bitwise.scala 103:75]
+    node _T_1449 = or(_T_1444, _T_1448) @[Bitwise.scala 103:39]
+    node _T_1450 = bits(_T_1442, 5, 0) @[Bitwise.scala 102:28]
+    node _T_1451 = shl(_T_1450, 2) @[Bitwise.scala 102:47]
+    node _T_1452 = xor(_T_1442, _T_1451) @[Bitwise.scala 102:21]
+    node _T_1453 = shr(_T_1449, 2) @[Bitwise.scala 103:21]
+    node _T_1454 = and(_T_1453, _T_1452) @[Bitwise.scala 103:31]
+    node _T_1455 = bits(_T_1449, 5, 0) @[Bitwise.scala 103:46]
+    node _T_1456 = shl(_T_1455, 2) @[Bitwise.scala 103:65]
+    node _T_1457 = not(_T_1452) @[Bitwise.scala 103:77]
+    node _T_1458 = and(_T_1456, _T_1457) @[Bitwise.scala 103:75]
+    node _T_1459 = or(_T_1454, _T_1458) @[Bitwise.scala 103:39]
+    node _T_1460 = bits(_T_1452, 6, 0) @[Bitwise.scala 102:28]
+    node _T_1461 = shl(_T_1460, 1) @[Bitwise.scala 102:47]
+    node _T_1462 = xor(_T_1452, _T_1461) @[Bitwise.scala 102:21]
+    node _T_1463 = shr(_T_1459, 1) @[Bitwise.scala 103:21]
+    node _T_1464 = and(_T_1463, _T_1462) @[Bitwise.scala 103:31]
+    node _T_1465 = bits(_T_1459, 6, 0) @[Bitwise.scala 103:46]
+    node _T_1466 = shl(_T_1465, 1) @[Bitwise.scala 103:65]
+    node _T_1467 = not(_T_1462) @[Bitwise.scala 103:77]
+    node _T_1468 = and(_T_1466, _T_1467) @[Bitwise.scala 103:75]
+    node _T_1469 = or(_T_1464, _T_1468) @[Bitwise.scala 103:39]
+    node _T_1470 = bits(store_byteen_ext_r, 1, 1) @[lsu_dccm_ctl.scala 248:98]
+    node _T_1471 = bits(_T_1470, 0, 0) @[lsu_dccm_ctl.scala 248:102]
+    node _T_1472 = bits(store_data_pre_lo_r, 15, 8) @[lsu_dccm_ctl.scala 248:130]
+    node _T_1473 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_lo) @[lsu_dccm_ctl.scala 248:174]
+    node _T_1474 = bits(_T_1473, 0, 0) @[lsu_dccm_ctl.scala 248:199]
+    node _T_1475 = bits(io.stbuf_data_any, 15, 8) @[lsu_dccm_ctl.scala 248:223]
+    node _T_1476 = and(dccm_wren_Q, dccm_wr_bypass_d_m_lo_Q) @[lsu_dccm_ctl.scala 248:256]
+    node _T_1477 = bits(_T_1476, 0, 0) @[lsu_dccm_ctl.scala 248:283]
+    node _T_1478 = bits(dccm_wr_data_Q, 15, 8) @[lsu_dccm_ctl.scala 248:305]
+    node _T_1479 = bits(io.sec_data_lo_r, 15, 8) @[lsu_dccm_ctl.scala 248:335]
+    node _T_1480 = mux(_T_1477, _T_1478, _T_1479) @[lsu_dccm_ctl.scala 248:242]
+    node _T_1481 = mux(_T_1474, _T_1475, _T_1480) @[lsu_dccm_ctl.scala 248:148]
+    node _T_1482 = mux(_T_1471, _T_1472, _T_1481) @[lsu_dccm_ctl.scala 248:79]
+    node _T_1483 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
+    node _T_1484 = xor(UInt<8>("h0ff"), _T_1483) @[Bitwise.scala 102:21]
+    node _T_1485 = shr(_T_1482, 4) @[Bitwise.scala 103:21]
+    node _T_1486 = and(_T_1485, _T_1484) @[Bitwise.scala 103:31]
+    node _T_1487 = bits(_T_1482, 3, 0) @[Bitwise.scala 103:46]
+    node _T_1488 = shl(_T_1487, 4) @[Bitwise.scala 103:65]
+    node _T_1489 = not(_T_1484) @[Bitwise.scala 103:77]
+    node _T_1490 = and(_T_1488, _T_1489) @[Bitwise.scala 103:75]
+    node _T_1491 = or(_T_1486, _T_1490) @[Bitwise.scala 103:39]
+    node _T_1492 = bits(_T_1484, 5, 0) @[Bitwise.scala 102:28]
+    node _T_1493 = shl(_T_1492, 2) @[Bitwise.scala 102:47]
+    node _T_1494 = xor(_T_1484, _T_1493) @[Bitwise.scala 102:21]
+    node _T_1495 = shr(_T_1491, 2) @[Bitwise.scala 103:21]
+    node _T_1496 = and(_T_1495, _T_1494) @[Bitwise.scala 103:31]
+    node _T_1497 = bits(_T_1491, 5, 0) @[Bitwise.scala 103:46]
+    node _T_1498 = shl(_T_1497, 2) @[Bitwise.scala 103:65]
+    node _T_1499 = not(_T_1494) @[Bitwise.scala 103:77]
+    node _T_1500 = and(_T_1498, _T_1499) @[Bitwise.scala 103:75]
+    node _T_1501 = or(_T_1496, _T_1500) @[Bitwise.scala 103:39]
+    node _T_1502 = bits(_T_1494, 6, 0) @[Bitwise.scala 102:28]
+    node _T_1503 = shl(_T_1502, 1) @[Bitwise.scala 102:47]
+    node _T_1504 = xor(_T_1494, _T_1503) @[Bitwise.scala 102:21]
+    node _T_1505 = shr(_T_1501, 1) @[Bitwise.scala 103:21]
+    node _T_1506 = and(_T_1505, _T_1504) @[Bitwise.scala 103:31]
+    node _T_1507 = bits(_T_1501, 6, 0) @[Bitwise.scala 103:46]
+    node _T_1508 = shl(_T_1507, 1) @[Bitwise.scala 103:65]
+    node _T_1509 = not(_T_1504) @[Bitwise.scala 103:77]
+    node _T_1510 = and(_T_1508, _T_1509) @[Bitwise.scala 103:75]
+    node _T_1511 = or(_T_1506, _T_1510) @[Bitwise.scala 103:39]
+    node _T_1512 = bits(store_byteen_ext_r, 2, 2) @[lsu_dccm_ctl.scala 248:98]
+    node _T_1513 = bits(_T_1512, 0, 0) @[lsu_dccm_ctl.scala 248:102]
+    node _T_1514 = bits(store_data_pre_lo_r, 23, 16) @[lsu_dccm_ctl.scala 248:130]
+    node _T_1515 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_lo) @[lsu_dccm_ctl.scala 248:174]
+    node _T_1516 = bits(_T_1515, 0, 0) @[lsu_dccm_ctl.scala 248:199]
+    node _T_1517 = bits(io.stbuf_data_any, 23, 16) @[lsu_dccm_ctl.scala 248:223]
+    node _T_1518 = and(dccm_wren_Q, dccm_wr_bypass_d_m_lo_Q) @[lsu_dccm_ctl.scala 248:256]
+    node _T_1519 = bits(_T_1518, 0, 0) @[lsu_dccm_ctl.scala 248:283]
+    node _T_1520 = bits(dccm_wr_data_Q, 23, 16) @[lsu_dccm_ctl.scala 248:305]
+    node _T_1521 = bits(io.sec_data_lo_r, 23, 16) @[lsu_dccm_ctl.scala 248:335]
+    node _T_1522 = mux(_T_1519, _T_1520, _T_1521) @[lsu_dccm_ctl.scala 248:242]
+    node _T_1523 = mux(_T_1516, _T_1517, _T_1522) @[lsu_dccm_ctl.scala 248:148]
+    node _T_1524 = mux(_T_1513, _T_1514, _T_1523) @[lsu_dccm_ctl.scala 248:79]
+    node _T_1525 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
+    node _T_1526 = xor(UInt<8>("h0ff"), _T_1525) @[Bitwise.scala 102:21]
+    node _T_1527 = shr(_T_1524, 4) @[Bitwise.scala 103:21]
+    node _T_1528 = and(_T_1527, _T_1526) @[Bitwise.scala 103:31]
+    node _T_1529 = bits(_T_1524, 3, 0) @[Bitwise.scala 103:46]
+    node _T_1530 = shl(_T_1529, 4) @[Bitwise.scala 103:65]
+    node _T_1531 = not(_T_1526) @[Bitwise.scala 103:77]
+    node _T_1532 = and(_T_1530, _T_1531) @[Bitwise.scala 103:75]
+    node _T_1533 = or(_T_1528, _T_1532) @[Bitwise.scala 103:39]
+    node _T_1534 = bits(_T_1526, 5, 0) @[Bitwise.scala 102:28]
+    node _T_1535 = shl(_T_1534, 2) @[Bitwise.scala 102:47]
+    node _T_1536 = xor(_T_1526, _T_1535) @[Bitwise.scala 102:21]
+    node _T_1537 = shr(_T_1533, 2) @[Bitwise.scala 103:21]
+    node _T_1538 = and(_T_1537, _T_1536) @[Bitwise.scala 103:31]
+    node _T_1539 = bits(_T_1533, 5, 0) @[Bitwise.scala 103:46]
+    node _T_1540 = shl(_T_1539, 2) @[Bitwise.scala 103:65]
+    node _T_1541 = not(_T_1536) @[Bitwise.scala 103:77]
+    node _T_1542 = and(_T_1540, _T_1541) @[Bitwise.scala 103:75]
+    node _T_1543 = or(_T_1538, _T_1542) @[Bitwise.scala 103:39]
+    node _T_1544 = bits(_T_1536, 6, 0) @[Bitwise.scala 102:28]
+    node _T_1545 = shl(_T_1544, 1) @[Bitwise.scala 102:47]
+    node _T_1546 = xor(_T_1536, _T_1545) @[Bitwise.scala 102:21]
+    node _T_1547 = shr(_T_1543, 1) @[Bitwise.scala 103:21]
+    node _T_1548 = and(_T_1547, _T_1546) @[Bitwise.scala 103:31]
+    node _T_1549 = bits(_T_1543, 6, 0) @[Bitwise.scala 103:46]
+    node _T_1550 = shl(_T_1549, 1) @[Bitwise.scala 103:65]
+    node _T_1551 = not(_T_1546) @[Bitwise.scala 103:77]
+    node _T_1552 = and(_T_1550, _T_1551) @[Bitwise.scala 103:75]
+    node _T_1553 = or(_T_1548, _T_1552) @[Bitwise.scala 103:39]
+    node _T_1554 = bits(store_byteen_ext_r, 3, 3) @[lsu_dccm_ctl.scala 248:98]
+    node _T_1555 = bits(_T_1554, 0, 0) @[lsu_dccm_ctl.scala 248:102]
+    node _T_1556 = bits(store_data_pre_lo_r, 31, 24) @[lsu_dccm_ctl.scala 248:130]
+    node _T_1557 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_lo) @[lsu_dccm_ctl.scala 248:174]
+    node _T_1558 = bits(_T_1557, 0, 0) @[lsu_dccm_ctl.scala 248:199]
+    node _T_1559 = bits(io.stbuf_data_any, 31, 24) @[lsu_dccm_ctl.scala 248:223]
+    node _T_1560 = and(dccm_wren_Q, dccm_wr_bypass_d_m_lo_Q) @[lsu_dccm_ctl.scala 248:256]
+    node _T_1561 = bits(_T_1560, 0, 0) @[lsu_dccm_ctl.scala 248:283]
+    node _T_1562 = bits(dccm_wr_data_Q, 31, 24) @[lsu_dccm_ctl.scala 248:305]
+    node _T_1563 = bits(io.sec_data_lo_r, 31, 24) @[lsu_dccm_ctl.scala 248:335]
+    node _T_1564 = mux(_T_1561, _T_1562, _T_1563) @[lsu_dccm_ctl.scala 248:242]
+    node _T_1565 = mux(_T_1558, _T_1559, _T_1564) @[lsu_dccm_ctl.scala 248:148]
+    node _T_1566 = mux(_T_1555, _T_1556, _T_1565) @[lsu_dccm_ctl.scala 248:79]
+    node _T_1567 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
+    node _T_1568 = xor(UInt<8>("h0ff"), _T_1567) @[Bitwise.scala 102:21]
+    node _T_1569 = shr(_T_1566, 4) @[Bitwise.scala 103:21]
+    node _T_1570 = and(_T_1569, _T_1568) @[Bitwise.scala 103:31]
+    node _T_1571 = bits(_T_1566, 3, 0) @[Bitwise.scala 103:46]
+    node _T_1572 = shl(_T_1571, 4) @[Bitwise.scala 103:65]
+    node _T_1573 = not(_T_1568) @[Bitwise.scala 103:77]
+    node _T_1574 = and(_T_1572, _T_1573) @[Bitwise.scala 103:75]
+    node _T_1575 = or(_T_1570, _T_1574) @[Bitwise.scala 103:39]
+    node _T_1576 = bits(_T_1568, 5, 0) @[Bitwise.scala 102:28]
+    node _T_1577 = shl(_T_1576, 2) @[Bitwise.scala 102:47]
+    node _T_1578 = xor(_T_1568, _T_1577) @[Bitwise.scala 102:21]
+    node _T_1579 = shr(_T_1575, 2) @[Bitwise.scala 103:21]
+    node _T_1580 = and(_T_1579, _T_1578) @[Bitwise.scala 103:31]
+    node _T_1581 = bits(_T_1575, 5, 0) @[Bitwise.scala 103:46]
+    node _T_1582 = shl(_T_1581, 2) @[Bitwise.scala 103:65]
+    node _T_1583 = not(_T_1578) @[Bitwise.scala 103:77]
+    node _T_1584 = and(_T_1582, _T_1583) @[Bitwise.scala 103:75]
+    node _T_1585 = or(_T_1580, _T_1584) @[Bitwise.scala 103:39]
+    node _T_1586 = bits(_T_1578, 6, 0) @[Bitwise.scala 102:28]
+    node _T_1587 = shl(_T_1586, 1) @[Bitwise.scala 102:47]
+    node _T_1588 = xor(_T_1578, _T_1587) @[Bitwise.scala 102:21]
+    node _T_1589 = shr(_T_1585, 1) @[Bitwise.scala 103:21]
+    node _T_1590 = and(_T_1589, _T_1588) @[Bitwise.scala 103:31]
+    node _T_1591 = bits(_T_1585, 6, 0) @[Bitwise.scala 103:46]
+    node _T_1592 = shl(_T_1591, 1) @[Bitwise.scala 103:65]
+    node _T_1593 = not(_T_1588) @[Bitwise.scala 103:77]
+    node _T_1594 = and(_T_1592, _T_1593) @[Bitwise.scala 103:75]
+    node _T_1595 = or(_T_1590, _T_1594) @[Bitwise.scala 103:39]
+    wire _T_1596 : UInt<8>[4] @[lsu_dccm_ctl.scala 248:63]
+    _T_1596[0] <= _T_1469 @[lsu_dccm_ctl.scala 248:63]
+    _T_1596[1] <= _T_1511 @[lsu_dccm_ctl.scala 248:63]
+    _T_1596[2] <= _T_1553 @[lsu_dccm_ctl.scala 248:63]
+    _T_1596[3] <= _T_1595 @[lsu_dccm_ctl.scala 248:63]
+    node _T_1597 = cat(_T_1596[2], _T_1596[3]) @[Cat.scala 29:58]
+    node _T_1598 = cat(_T_1596[0], _T_1596[1]) @[Cat.scala 29:58]
+    node _T_1599 = cat(_T_1598, _T_1597) @[Cat.scala 29:58]
+    node _T_1600 = shl(UInt<16>("h0ffff"), 16) @[Bitwise.scala 102:47]
+    node _T_1601 = xor(UInt<32>("h0ffffffff"), _T_1600) @[Bitwise.scala 102:21]
+    node _T_1602 = shr(_T_1599, 16) @[Bitwise.scala 103:21]
+    node _T_1603 = and(_T_1602, _T_1601) @[Bitwise.scala 103:31]
+    node _T_1604 = bits(_T_1599, 15, 0) @[Bitwise.scala 103:46]
+    node _T_1605 = shl(_T_1604, 16) @[Bitwise.scala 103:65]
+    node _T_1606 = not(_T_1601) @[Bitwise.scala 103:77]
+    node _T_1607 = and(_T_1605, _T_1606) @[Bitwise.scala 103:75]
+    node _T_1608 = or(_T_1603, _T_1607) @[Bitwise.scala 103:39]
+    node _T_1609 = bits(_T_1601, 23, 0) @[Bitwise.scala 102:28]
+    node _T_1610 = shl(_T_1609, 8) @[Bitwise.scala 102:47]
+    node _T_1611 = xor(_T_1601, _T_1610) @[Bitwise.scala 102:21]
+    node _T_1612 = shr(_T_1608, 8) @[Bitwise.scala 103:21]
+    node _T_1613 = and(_T_1612, _T_1611) @[Bitwise.scala 103:31]
+    node _T_1614 = bits(_T_1608, 23, 0) @[Bitwise.scala 103:46]
+    node _T_1615 = shl(_T_1614, 8) @[Bitwise.scala 103:65]
+    node _T_1616 = not(_T_1611) @[Bitwise.scala 103:77]
+    node _T_1617 = and(_T_1615, _T_1616) @[Bitwise.scala 103:75]
+    node _T_1618 = or(_T_1613, _T_1617) @[Bitwise.scala 103:39]
+    node _T_1619 = bits(_T_1611, 27, 0) @[Bitwise.scala 102:28]
+    node _T_1620 = shl(_T_1619, 4) @[Bitwise.scala 102:47]
+    node _T_1621 = xor(_T_1611, _T_1620) @[Bitwise.scala 102:21]
+    node _T_1622 = shr(_T_1618, 4) @[Bitwise.scala 103:21]
+    node _T_1623 = and(_T_1622, _T_1621) @[Bitwise.scala 103:31]
+    node _T_1624 = bits(_T_1618, 27, 0) @[Bitwise.scala 103:46]
+    node _T_1625 = shl(_T_1624, 4) @[Bitwise.scala 103:65]
+    node _T_1626 = not(_T_1621) @[Bitwise.scala 103:77]
+    node _T_1627 = and(_T_1625, _T_1626) @[Bitwise.scala 103:75]
+    node _T_1628 = or(_T_1623, _T_1627) @[Bitwise.scala 103:39]
+    node _T_1629 = bits(_T_1621, 29, 0) @[Bitwise.scala 102:28]
+    node _T_1630 = shl(_T_1629, 2) @[Bitwise.scala 102:47]
+    node _T_1631 = xor(_T_1621, _T_1630) @[Bitwise.scala 102:21]
+    node _T_1632 = shr(_T_1628, 2) @[Bitwise.scala 103:21]
+    node _T_1633 = and(_T_1632, _T_1631) @[Bitwise.scala 103:31]
+    node _T_1634 = bits(_T_1628, 29, 0) @[Bitwise.scala 103:46]
+    node _T_1635 = shl(_T_1634, 2) @[Bitwise.scala 103:65]
+    node _T_1636 = not(_T_1631) @[Bitwise.scala 103:77]
+    node _T_1637 = and(_T_1635, _T_1636) @[Bitwise.scala 103:75]
+    node _T_1638 = or(_T_1633, _T_1637) @[Bitwise.scala 103:39]
+    node _T_1639 = bits(_T_1631, 30, 0) @[Bitwise.scala 102:28]
+    node _T_1640 = shl(_T_1639, 1) @[Bitwise.scala 102:47]
+    node _T_1641 = xor(_T_1631, _T_1640) @[Bitwise.scala 102:21]
+    node _T_1642 = shr(_T_1638, 1) @[Bitwise.scala 103:21]
+    node _T_1643 = and(_T_1642, _T_1641) @[Bitwise.scala 103:31]
+    node _T_1644 = bits(_T_1638, 30, 0) @[Bitwise.scala 103:46]
+    node _T_1645 = shl(_T_1644, 1) @[Bitwise.scala 103:65]
+    node _T_1646 = not(_T_1641) @[Bitwise.scala 103:77]
+    node _T_1647 = and(_T_1645, _T_1646) @[Bitwise.scala 103:75]
+    node _T_1648 = or(_T_1643, _T_1647) @[Bitwise.scala 103:39]
+    io.store_datafn_lo_r <= _T_1648 @[lsu_dccm_ctl.scala 248:29]
+    node _T_1649 = bits(store_byteen_ext_r, 4, 4) @[lsu_dccm_ctl.scala 249:98]
+    node _T_1650 = bits(_T_1649, 0, 0) @[lsu_dccm_ctl.scala 249:104]
+    node _T_1651 = bits(store_data_pre_hi_r, 7, 0) @[lsu_dccm_ctl.scala 249:130]
+    node _T_1652 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_lo) @[lsu_dccm_ctl.scala 249:174]
+    node _T_1653 = bits(_T_1652, 0, 0) @[lsu_dccm_ctl.scala 249:199]
+    node _T_1654 = bits(io.stbuf_data_any, 7, 0) @[lsu_dccm_ctl.scala 249:223]
+    node _T_1655 = and(dccm_wren_Q, dccm_wr_bypass_d_m_hi_Q) @[lsu_dccm_ctl.scala 249:256]
+    node _T_1656 = bits(_T_1655, 0, 0) @[lsu_dccm_ctl.scala 249:283]
+    node _T_1657 = bits(dccm_wr_data_Q, 7, 0) @[lsu_dccm_ctl.scala 249:305]
+    node _T_1658 = bits(io.sec_data_hi_r, 7, 0) @[lsu_dccm_ctl.scala 249:335]
+    node _T_1659 = mux(_T_1656, _T_1657, _T_1658) @[lsu_dccm_ctl.scala 249:242]
+    node _T_1660 = mux(_T_1653, _T_1654, _T_1659) @[lsu_dccm_ctl.scala 249:148]
+    node _T_1661 = mux(_T_1650, _T_1651, _T_1660) @[lsu_dccm_ctl.scala 249:79]
+    node _T_1662 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
+    node _T_1663 = xor(UInt<8>("h0ff"), _T_1662) @[Bitwise.scala 102:21]
+    node _T_1664 = shr(_T_1661, 4) @[Bitwise.scala 103:21]
+    node _T_1665 = and(_T_1664, _T_1663) @[Bitwise.scala 103:31]
+    node _T_1666 = bits(_T_1661, 3, 0) @[Bitwise.scala 103:46]
+    node _T_1667 = shl(_T_1666, 4) @[Bitwise.scala 103:65]
+    node _T_1668 = not(_T_1663) @[Bitwise.scala 103:77]
+    node _T_1669 = and(_T_1667, _T_1668) @[Bitwise.scala 103:75]
+    node _T_1670 = or(_T_1665, _T_1669) @[Bitwise.scala 103:39]
+    node _T_1671 = bits(_T_1663, 5, 0) @[Bitwise.scala 102:28]
+    node _T_1672 = shl(_T_1671, 2) @[Bitwise.scala 102:47]
+    node _T_1673 = xor(_T_1663, _T_1672) @[Bitwise.scala 102:21]
+    node _T_1674 = shr(_T_1670, 2) @[Bitwise.scala 103:21]
+    node _T_1675 = and(_T_1674, _T_1673) @[Bitwise.scala 103:31]
+    node _T_1676 = bits(_T_1670, 5, 0) @[Bitwise.scala 103:46]
+    node _T_1677 = shl(_T_1676, 2) @[Bitwise.scala 103:65]
+    node _T_1678 = not(_T_1673) @[Bitwise.scala 103:77]
+    node _T_1679 = and(_T_1677, _T_1678) @[Bitwise.scala 103:75]
+    node _T_1680 = or(_T_1675, _T_1679) @[Bitwise.scala 103:39]
+    node _T_1681 = bits(_T_1673, 6, 0) @[Bitwise.scala 102:28]
+    node _T_1682 = shl(_T_1681, 1) @[Bitwise.scala 102:47]
+    node _T_1683 = xor(_T_1673, _T_1682) @[Bitwise.scala 102:21]
+    node _T_1684 = shr(_T_1680, 1) @[Bitwise.scala 103:21]
+    node _T_1685 = and(_T_1684, _T_1683) @[Bitwise.scala 103:31]
+    node _T_1686 = bits(_T_1680, 6, 0) @[Bitwise.scala 103:46]
+    node _T_1687 = shl(_T_1686, 1) @[Bitwise.scala 103:65]
+    node _T_1688 = not(_T_1683) @[Bitwise.scala 103:77]
+    node _T_1689 = and(_T_1687, _T_1688) @[Bitwise.scala 103:75]
+    node _T_1690 = or(_T_1685, _T_1689) @[Bitwise.scala 103:39]
+    node _T_1691 = bits(store_byteen_ext_r, 5, 5) @[lsu_dccm_ctl.scala 249:98]
+    node _T_1692 = bits(_T_1691, 0, 0) @[lsu_dccm_ctl.scala 249:104]
+    node _T_1693 = bits(store_data_pre_hi_r, 15, 8) @[lsu_dccm_ctl.scala 249:130]
+    node _T_1694 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_lo) @[lsu_dccm_ctl.scala 249:174]
+    node _T_1695 = bits(_T_1694, 0, 0) @[lsu_dccm_ctl.scala 249:199]
+    node _T_1696 = bits(io.stbuf_data_any, 15, 8) @[lsu_dccm_ctl.scala 249:223]
+    node _T_1697 = and(dccm_wren_Q, dccm_wr_bypass_d_m_hi_Q) @[lsu_dccm_ctl.scala 249:256]
+    node _T_1698 = bits(_T_1697, 0, 0) @[lsu_dccm_ctl.scala 249:283]
+    node _T_1699 = bits(dccm_wr_data_Q, 15, 8) @[lsu_dccm_ctl.scala 249:305]
+    node _T_1700 = bits(io.sec_data_hi_r, 15, 8) @[lsu_dccm_ctl.scala 249:335]
+    node _T_1701 = mux(_T_1698, _T_1699, _T_1700) @[lsu_dccm_ctl.scala 249:242]
+    node _T_1702 = mux(_T_1695, _T_1696, _T_1701) @[lsu_dccm_ctl.scala 249:148]
+    node _T_1703 = mux(_T_1692, _T_1693, _T_1702) @[lsu_dccm_ctl.scala 249:79]
+    node _T_1704 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
+    node _T_1705 = xor(UInt<8>("h0ff"), _T_1704) @[Bitwise.scala 102:21]
+    node _T_1706 = shr(_T_1703, 4) @[Bitwise.scala 103:21]
+    node _T_1707 = and(_T_1706, _T_1705) @[Bitwise.scala 103:31]
+    node _T_1708 = bits(_T_1703, 3, 0) @[Bitwise.scala 103:46]
+    node _T_1709 = shl(_T_1708, 4) @[Bitwise.scala 103:65]
+    node _T_1710 = not(_T_1705) @[Bitwise.scala 103:77]
+    node _T_1711 = and(_T_1709, _T_1710) @[Bitwise.scala 103:75]
+    node _T_1712 = or(_T_1707, _T_1711) @[Bitwise.scala 103:39]
+    node _T_1713 = bits(_T_1705, 5, 0) @[Bitwise.scala 102:28]
+    node _T_1714 = shl(_T_1713, 2) @[Bitwise.scala 102:47]
+    node _T_1715 = xor(_T_1705, _T_1714) @[Bitwise.scala 102:21]
+    node _T_1716 = shr(_T_1712, 2) @[Bitwise.scala 103:21]
+    node _T_1717 = and(_T_1716, _T_1715) @[Bitwise.scala 103:31]
+    node _T_1718 = bits(_T_1712, 5, 0) @[Bitwise.scala 103:46]
+    node _T_1719 = shl(_T_1718, 2) @[Bitwise.scala 103:65]
+    node _T_1720 = not(_T_1715) @[Bitwise.scala 103:77]
+    node _T_1721 = and(_T_1719, _T_1720) @[Bitwise.scala 103:75]
+    node _T_1722 = or(_T_1717, _T_1721) @[Bitwise.scala 103:39]
+    node _T_1723 = bits(_T_1715, 6, 0) @[Bitwise.scala 102:28]
+    node _T_1724 = shl(_T_1723, 1) @[Bitwise.scala 102:47]
+    node _T_1725 = xor(_T_1715, _T_1724) @[Bitwise.scala 102:21]
+    node _T_1726 = shr(_T_1722, 1) @[Bitwise.scala 103:21]
+    node _T_1727 = and(_T_1726, _T_1725) @[Bitwise.scala 103:31]
+    node _T_1728 = bits(_T_1722, 6, 0) @[Bitwise.scala 103:46]
+    node _T_1729 = shl(_T_1728, 1) @[Bitwise.scala 103:65]
+    node _T_1730 = not(_T_1725) @[Bitwise.scala 103:77]
+    node _T_1731 = and(_T_1729, _T_1730) @[Bitwise.scala 103:75]
+    node _T_1732 = or(_T_1727, _T_1731) @[Bitwise.scala 103:39]
+    node _T_1733 = bits(store_byteen_ext_r, 6, 6) @[lsu_dccm_ctl.scala 249:98]
+    node _T_1734 = bits(_T_1733, 0, 0) @[lsu_dccm_ctl.scala 249:104]
+    node _T_1735 = bits(store_data_pre_hi_r, 23, 16) @[lsu_dccm_ctl.scala 249:130]
+    node _T_1736 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_lo) @[lsu_dccm_ctl.scala 249:174]
+    node _T_1737 = bits(_T_1736, 0, 0) @[lsu_dccm_ctl.scala 249:199]
+    node _T_1738 = bits(io.stbuf_data_any, 23, 16) @[lsu_dccm_ctl.scala 249:223]
+    node _T_1739 = and(dccm_wren_Q, dccm_wr_bypass_d_m_hi_Q) @[lsu_dccm_ctl.scala 249:256]
+    node _T_1740 = bits(_T_1739, 0, 0) @[lsu_dccm_ctl.scala 249:283]
+    node _T_1741 = bits(dccm_wr_data_Q, 23, 16) @[lsu_dccm_ctl.scala 249:305]
+    node _T_1742 = bits(io.sec_data_hi_r, 23, 16) @[lsu_dccm_ctl.scala 249:335]
+    node _T_1743 = mux(_T_1740, _T_1741, _T_1742) @[lsu_dccm_ctl.scala 249:242]
+    node _T_1744 = mux(_T_1737, _T_1738, _T_1743) @[lsu_dccm_ctl.scala 249:148]
+    node _T_1745 = mux(_T_1734, _T_1735, _T_1744) @[lsu_dccm_ctl.scala 249:79]
+    node _T_1746 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
+    node _T_1747 = xor(UInt<8>("h0ff"), _T_1746) @[Bitwise.scala 102:21]
+    node _T_1748 = shr(_T_1745, 4) @[Bitwise.scala 103:21]
+    node _T_1749 = and(_T_1748, _T_1747) @[Bitwise.scala 103:31]
+    node _T_1750 = bits(_T_1745, 3, 0) @[Bitwise.scala 103:46]
+    node _T_1751 = shl(_T_1750, 4) @[Bitwise.scala 103:65]
+    node _T_1752 = not(_T_1747) @[Bitwise.scala 103:77]
+    node _T_1753 = and(_T_1751, _T_1752) @[Bitwise.scala 103:75]
+    node _T_1754 = or(_T_1749, _T_1753) @[Bitwise.scala 103:39]
+    node _T_1755 = bits(_T_1747, 5, 0) @[Bitwise.scala 102:28]
+    node _T_1756 = shl(_T_1755, 2) @[Bitwise.scala 102:47]
+    node _T_1757 = xor(_T_1747, _T_1756) @[Bitwise.scala 102:21]
+    node _T_1758 = shr(_T_1754, 2) @[Bitwise.scala 103:21]
+    node _T_1759 = and(_T_1758, _T_1757) @[Bitwise.scala 103:31]
+    node _T_1760 = bits(_T_1754, 5, 0) @[Bitwise.scala 103:46]
+    node _T_1761 = shl(_T_1760, 2) @[Bitwise.scala 103:65]
+    node _T_1762 = not(_T_1757) @[Bitwise.scala 103:77]
+    node _T_1763 = and(_T_1761, _T_1762) @[Bitwise.scala 103:75]
+    node _T_1764 = or(_T_1759, _T_1763) @[Bitwise.scala 103:39]
+    node _T_1765 = bits(_T_1757, 6, 0) @[Bitwise.scala 102:28]
+    node _T_1766 = shl(_T_1765, 1) @[Bitwise.scala 102:47]
+    node _T_1767 = xor(_T_1757, _T_1766) @[Bitwise.scala 102:21]
+    node _T_1768 = shr(_T_1764, 1) @[Bitwise.scala 103:21]
+    node _T_1769 = and(_T_1768, _T_1767) @[Bitwise.scala 103:31]
+    node _T_1770 = bits(_T_1764, 6, 0) @[Bitwise.scala 103:46]
+    node _T_1771 = shl(_T_1770, 1) @[Bitwise.scala 103:65]
+    node _T_1772 = not(_T_1767) @[Bitwise.scala 103:77]
+    node _T_1773 = and(_T_1771, _T_1772) @[Bitwise.scala 103:75]
+    node _T_1774 = or(_T_1769, _T_1773) @[Bitwise.scala 103:39]
+    node _T_1775 = bits(store_byteen_ext_r, 7, 7) @[lsu_dccm_ctl.scala 249:98]
+    node _T_1776 = bits(_T_1775, 0, 0) @[lsu_dccm_ctl.scala 249:104]
+    node _T_1777 = bits(store_data_pre_hi_r, 31, 24) @[lsu_dccm_ctl.scala 249:130]
+    node _T_1778 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_lo) @[lsu_dccm_ctl.scala 249:174]
+    node _T_1779 = bits(_T_1778, 0, 0) @[lsu_dccm_ctl.scala 249:199]
+    node _T_1780 = bits(io.stbuf_data_any, 31, 24) @[lsu_dccm_ctl.scala 249:223]
+    node _T_1781 = and(dccm_wren_Q, dccm_wr_bypass_d_m_hi_Q) @[lsu_dccm_ctl.scala 249:256]
+    node _T_1782 = bits(_T_1781, 0, 0) @[lsu_dccm_ctl.scala 249:283]
+    node _T_1783 = bits(dccm_wr_data_Q, 31, 24) @[lsu_dccm_ctl.scala 249:305]
+    node _T_1784 = bits(io.sec_data_hi_r, 31, 24) @[lsu_dccm_ctl.scala 249:335]
+    node _T_1785 = mux(_T_1782, _T_1783, _T_1784) @[lsu_dccm_ctl.scala 249:242]
+    node _T_1786 = mux(_T_1779, _T_1780, _T_1785) @[lsu_dccm_ctl.scala 249:148]
+    node _T_1787 = mux(_T_1776, _T_1777, _T_1786) @[lsu_dccm_ctl.scala 249:79]
+    node _T_1788 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
+    node _T_1789 = xor(UInt<8>("h0ff"), _T_1788) @[Bitwise.scala 102:21]
+    node _T_1790 = shr(_T_1787, 4) @[Bitwise.scala 103:21]
+    node _T_1791 = and(_T_1790, _T_1789) @[Bitwise.scala 103:31]
+    node _T_1792 = bits(_T_1787, 3, 0) @[Bitwise.scala 103:46]
+    node _T_1793 = shl(_T_1792, 4) @[Bitwise.scala 103:65]
+    node _T_1794 = not(_T_1789) @[Bitwise.scala 103:77]
+    node _T_1795 = and(_T_1793, _T_1794) @[Bitwise.scala 103:75]
+    node _T_1796 = or(_T_1791, _T_1795) @[Bitwise.scala 103:39]
+    node _T_1797 = bits(_T_1789, 5, 0) @[Bitwise.scala 102:28]
+    node _T_1798 = shl(_T_1797, 2) @[Bitwise.scala 102:47]
+    node _T_1799 = xor(_T_1789, _T_1798) @[Bitwise.scala 102:21]
+    node _T_1800 = shr(_T_1796, 2) @[Bitwise.scala 103:21]
+    node _T_1801 = and(_T_1800, _T_1799) @[Bitwise.scala 103:31]
+    node _T_1802 = bits(_T_1796, 5, 0) @[Bitwise.scala 103:46]
+    node _T_1803 = shl(_T_1802, 2) @[Bitwise.scala 103:65]
+    node _T_1804 = not(_T_1799) @[Bitwise.scala 103:77]
+    node _T_1805 = and(_T_1803, _T_1804) @[Bitwise.scala 103:75]
+    node _T_1806 = or(_T_1801, _T_1805) @[Bitwise.scala 103:39]
+    node _T_1807 = bits(_T_1799, 6, 0) @[Bitwise.scala 102:28]
+    node _T_1808 = shl(_T_1807, 1) @[Bitwise.scala 102:47]
+    node _T_1809 = xor(_T_1799, _T_1808) @[Bitwise.scala 102:21]
+    node _T_1810 = shr(_T_1806, 1) @[Bitwise.scala 103:21]
+    node _T_1811 = and(_T_1810, _T_1809) @[Bitwise.scala 103:31]
+    node _T_1812 = bits(_T_1806, 6, 0) @[Bitwise.scala 103:46]
+    node _T_1813 = shl(_T_1812, 1) @[Bitwise.scala 103:65]
+    node _T_1814 = not(_T_1809) @[Bitwise.scala 103:77]
+    node _T_1815 = and(_T_1813, _T_1814) @[Bitwise.scala 103:75]
+    node _T_1816 = or(_T_1811, _T_1815) @[Bitwise.scala 103:39]
+    wire _T_1817 : UInt<8>[4] @[lsu_dccm_ctl.scala 249:63]
+    _T_1817[0] <= _T_1690 @[lsu_dccm_ctl.scala 249:63]
+    _T_1817[1] <= _T_1732 @[lsu_dccm_ctl.scala 249:63]
+    _T_1817[2] <= _T_1774 @[lsu_dccm_ctl.scala 249:63]
+    _T_1817[3] <= _T_1816 @[lsu_dccm_ctl.scala 249:63]
+    node _T_1818 = cat(_T_1817[2], _T_1817[3]) @[Cat.scala 29:58]
+    node _T_1819 = cat(_T_1817[0], _T_1817[1]) @[Cat.scala 29:58]
+    node _T_1820 = cat(_T_1819, _T_1818) @[Cat.scala 29:58]
+    node _T_1821 = shl(UInt<16>("h0ffff"), 16) @[Bitwise.scala 102:47]
+    node _T_1822 = xor(UInt<32>("h0ffffffff"), _T_1821) @[Bitwise.scala 102:21]
+    node _T_1823 = shr(_T_1820, 16) @[Bitwise.scala 103:21]
+    node _T_1824 = and(_T_1823, _T_1822) @[Bitwise.scala 103:31]
+    node _T_1825 = bits(_T_1820, 15, 0) @[Bitwise.scala 103:46]
+    node _T_1826 = shl(_T_1825, 16) @[Bitwise.scala 103:65]
+    node _T_1827 = not(_T_1822) @[Bitwise.scala 103:77]
+    node _T_1828 = and(_T_1826, _T_1827) @[Bitwise.scala 103:75]
+    node _T_1829 = or(_T_1824, _T_1828) @[Bitwise.scala 103:39]
+    node _T_1830 = bits(_T_1822, 23, 0) @[Bitwise.scala 102:28]
+    node _T_1831 = shl(_T_1830, 8) @[Bitwise.scala 102:47]
+    node _T_1832 = xor(_T_1822, _T_1831) @[Bitwise.scala 102:21]
+    node _T_1833 = shr(_T_1829, 8) @[Bitwise.scala 103:21]
+    node _T_1834 = and(_T_1833, _T_1832) @[Bitwise.scala 103:31]
+    node _T_1835 = bits(_T_1829, 23, 0) @[Bitwise.scala 103:46]
+    node _T_1836 = shl(_T_1835, 8) @[Bitwise.scala 103:65]
+    node _T_1837 = not(_T_1832) @[Bitwise.scala 103:77]
+    node _T_1838 = and(_T_1836, _T_1837) @[Bitwise.scala 103:75]
+    node _T_1839 = or(_T_1834, _T_1838) @[Bitwise.scala 103:39]
+    node _T_1840 = bits(_T_1832, 27, 0) @[Bitwise.scala 102:28]
+    node _T_1841 = shl(_T_1840, 4) @[Bitwise.scala 102:47]
+    node _T_1842 = xor(_T_1832, _T_1841) @[Bitwise.scala 102:21]
+    node _T_1843 = shr(_T_1839, 4) @[Bitwise.scala 103:21]
+    node _T_1844 = and(_T_1843, _T_1842) @[Bitwise.scala 103:31]
+    node _T_1845 = bits(_T_1839, 27, 0) @[Bitwise.scala 103:46]
+    node _T_1846 = shl(_T_1845, 4) @[Bitwise.scala 103:65]
+    node _T_1847 = not(_T_1842) @[Bitwise.scala 103:77]
+    node _T_1848 = and(_T_1846, _T_1847) @[Bitwise.scala 103:75]
+    node _T_1849 = or(_T_1844, _T_1848) @[Bitwise.scala 103:39]
+    node _T_1850 = bits(_T_1842, 29, 0) @[Bitwise.scala 102:28]
+    node _T_1851 = shl(_T_1850, 2) @[Bitwise.scala 102:47]
+    node _T_1852 = xor(_T_1842, _T_1851) @[Bitwise.scala 102:21]
+    node _T_1853 = shr(_T_1849, 2) @[Bitwise.scala 103:21]
+    node _T_1854 = and(_T_1853, _T_1852) @[Bitwise.scala 103:31]
+    node _T_1855 = bits(_T_1849, 29, 0) @[Bitwise.scala 103:46]
+    node _T_1856 = shl(_T_1855, 2) @[Bitwise.scala 103:65]
+    node _T_1857 = not(_T_1852) @[Bitwise.scala 103:77]
+    node _T_1858 = and(_T_1856, _T_1857) @[Bitwise.scala 103:75]
+    node _T_1859 = or(_T_1854, _T_1858) @[Bitwise.scala 103:39]
+    node _T_1860 = bits(_T_1852, 30, 0) @[Bitwise.scala 102:28]
+    node _T_1861 = shl(_T_1860, 1) @[Bitwise.scala 102:47]
+    node _T_1862 = xor(_T_1852, _T_1861) @[Bitwise.scala 102:21]
+    node _T_1863 = shr(_T_1859, 1) @[Bitwise.scala 103:21]
+    node _T_1864 = and(_T_1863, _T_1862) @[Bitwise.scala 103:31]
+    node _T_1865 = bits(_T_1859, 30, 0) @[Bitwise.scala 103:46]
+    node _T_1866 = shl(_T_1865, 1) @[Bitwise.scala 103:65]
+    node _T_1867 = not(_T_1862) @[Bitwise.scala 103:77]
+    node _T_1868 = and(_T_1866, _T_1867) @[Bitwise.scala 103:75]
+    node _T_1869 = or(_T_1864, _T_1868) @[Bitwise.scala 103:39]
+    io.store_datafn_hi_r <= _T_1869 @[lsu_dccm_ctl.scala 249:29]
+    reg _T_1870 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_dccm_ctl.scala 250:69]
+    _T_1870 <= io.lsu_stbuf_commit_any @[lsu_dccm_ctl.scala 250:69]
+    dccm_wren_Q <= _T_1870 @[lsu_dccm_ctl.scala 250:29]
+    node _T_1871 = or(io.lsu_stbuf_commit_any, io.clk_override) @[lsu_dccm_ctl.scala 251:82]
+    node _T_1872 = bits(_T_1871, 0, 0) @[lsu_dccm_ctl.scala 251:101]
+    node _T_1873 = bits(io.scan_mode, 0, 0) @[lsu_dccm_ctl.scala 251:127]
+    inst rvclkhdr_7 of rvclkhdr_7 @[lib.scala 390:23]
+    rvclkhdr_7.clock <= clock
+    rvclkhdr_7.reset <= reset
+    rvclkhdr_7.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr_7.io.en <= _T_1872 @[lib.scala 393:17]
+    rvclkhdr_7.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg _T_1874 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_1872 : @[Reg.scala 28:19]
+      _T_1874 <= io.stbuf_data_any @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    dccm_wr_data_Q <= _T_1874 @[lsu_dccm_ctl.scala 251:29]
+    reg _T_1875 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_dccm_ctl.scala 252:69]
+    _T_1875 <= dccm_wr_bypass_d_m_lo @[lsu_dccm_ctl.scala 252:69]
+    dccm_wr_bypass_d_m_lo_Q <= _T_1875 @[lsu_dccm_ctl.scala 252:29]
+    reg _T_1876 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_dccm_ctl.scala 253:69]
+    _T_1876 <= dccm_wr_bypass_d_m_hi @[lsu_dccm_ctl.scala 253:69]
+    dccm_wr_bypass_d_m_hi_Q <= _T_1876 @[lsu_dccm_ctl.scala 253:29]
+    reg _T_1877 : UInt, io.lsu_store_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_dccm_ctl.scala 254:72]
+    _T_1877 <= io.store_data_m @[lsu_dccm_ctl.scala 254:72]
+    io.store_data_r <= _T_1877 @[lsu_dccm_ctl.scala 254:29]
+    node _T_1878 = bits(io.dccm.rd_data_lo, 31, 0) @[lsu_dccm_ctl.scala 267:48]
+    io.dccm_rdata_lo_m <= _T_1878 @[lsu_dccm_ctl.scala 267:27]
+    node _T_1879 = bits(io.dccm.rd_data_hi, 31, 0) @[lsu_dccm_ctl.scala 268:48]
+    io.dccm_rdata_hi_m <= _T_1879 @[lsu_dccm_ctl.scala 268:27]
+    node _T_1880 = bits(io.dccm.rd_data_lo, 38, 32) @[lsu_dccm_ctl.scala 269:48]
+    io.dccm_data_ecc_lo_m <= _T_1880 @[lsu_dccm_ctl.scala 269:27]
+    node _T_1881 = bits(io.dccm.rd_data_hi, 38, 32) @[lsu_dccm_ctl.scala 270:48]
+    io.dccm_data_ecc_hi_m <= _T_1881 @[lsu_dccm_ctl.scala 270:27]
+    node _T_1882 = and(io.lsu_pkt_r.valid, io.lsu_pkt_r.bits.store) @[lsu_dccm_ctl.scala 272:58]
+    node _T_1883 = and(_T_1882, io.addr_in_pic_r) @[lsu_dccm_ctl.scala 272:84]
+    node _T_1884 = and(_T_1883, io.lsu_commit_r) @[lsu_dccm_ctl.scala 272:103]
+    node _T_1885 = or(_T_1884, io.dma_pic_wen) @[lsu_dccm_ctl.scala 272:122]
+    io.lsu_pic.picm_wren <= _T_1885 @[lsu_dccm_ctl.scala 272:35]
+    node _T_1886 = and(io.lsu_pkt_d.valid, io.lsu_pkt_d.bits.load) @[lsu_dccm_ctl.scala 273:58]
+    node _T_1887 = and(_T_1886, io.addr_in_pic_d) @[lsu_dccm_ctl.scala 273:84]
+    io.lsu_pic.picm_rden <= _T_1887 @[lsu_dccm_ctl.scala 273:35]
+    node _T_1888 = and(io.lsu_pkt_d.valid, io.lsu_pkt_d.bits.store) @[lsu_dccm_ctl.scala 274:58]
+    node _T_1889 = and(_T_1888, io.addr_in_pic_d) @[lsu_dccm_ctl.scala 274:84]
+    io.lsu_pic.picm_mken <= _T_1889 @[lsu_dccm_ctl.scala 274:35]
+    node _T_1890 = mux(UInt<1>("h00"), UInt<17>("h01ffff"), UInt<17>("h00")) @[Bitwise.scala 72:12]
+    node _T_1891 = bits(io.lsu_addr_d, 14, 0) @[lsu_dccm_ctl.scala 275:103]
+    node _T_1892 = cat(_T_1890, _T_1891) @[Cat.scala 29:58]
+    node _T_1893 = or(UInt<32>("h0f00c0000"), _T_1892) @[lsu_dccm_ctl.scala 275:62]
+    io.lsu_pic.picm_rdaddr <= _T_1893 @[lsu_dccm_ctl.scala 275:35]
+    node _T_1894 = mux(UInt<1>("h00"), UInt<17>("h01ffff"), UInt<17>("h00")) @[Bitwise.scala 72:12]
+    node _T_1895 = bits(io.dma_pic_wen, 0, 0) @[lsu_dccm_ctl.scala 276:109]
+    node _T_1896 = bits(io.dma_dccm_ctl.dma_mem_addr, 14, 0) @[lsu_dccm_ctl.scala 276:144]
+    node _T_1897 = bits(io.lsu_addr_r, 14, 0) @[lsu_dccm_ctl.scala 276:172]
+    node _T_1898 = mux(_T_1895, _T_1896, _T_1897) @[lsu_dccm_ctl.scala 276:93]
+    node _T_1899 = cat(_T_1894, _T_1898) @[Cat.scala 29:58]
+    node _T_1900 = or(UInt<32>("h0f00c0000"), _T_1899) @[lsu_dccm_ctl.scala 276:62]
+    io.lsu_pic.picm_wraddr <= _T_1900 @[lsu_dccm_ctl.scala 276:35]
+    node _T_1901 = bits(picm_rd_data_m, 31, 0) @[lsu_dccm_ctl.scala 277:44]
+    io.picm_mask_data_m <= _T_1901 @[lsu_dccm_ctl.scala 277:27]
+    node _T_1902 = bits(io.dma_pic_wen, 0, 0) @[lsu_dccm_ctl.scala 278:57]
+    node _T_1903 = bits(io.dma_dccm_ctl.dma_mem_wdata, 31, 0) @[lsu_dccm_ctl.scala 278:93]
+    node _T_1904 = bits(io.store_datafn_lo_r, 31, 0) @[lsu_dccm_ctl.scala 278:120]
+    node _T_1905 = mux(_T_1902, _T_1903, _T_1904) @[lsu_dccm_ctl.scala 278:41]
+    io.lsu_pic.picm_wr_data <= _T_1905 @[lsu_dccm_ctl.scala 278:35]
+    reg _T_1906 : UInt, io.lsu_c2_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_dccm_ctl.scala 280:61]
+    _T_1906 <= lsu_dccm_rden_d @[lsu_dccm_ctl.scala 280:61]
+    io.lsu_dccm_rden_m <= _T_1906 @[lsu_dccm_ctl.scala 280:24]
+    reg _T_1907 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_dccm_ctl.scala 281:61]
+    _T_1907 <= io.lsu_dccm_rden_m @[lsu_dccm_ctl.scala 281:61]
+    io.lsu_dccm_rden_r <= _T_1907 @[lsu_dccm_ctl.scala 281:24]
+    reg _T_1908 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_dccm_ctl.scala 282:73]
+    _T_1908 <= io.lsu_double_ecc_error_r @[lsu_dccm_ctl.scala 282:73]
+    lsu_double_ecc_error_r_ff <= _T_1908 @[lsu_dccm_ctl.scala 282:33]
+    reg _T_1909 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_dccm_ctl.scala 283:73]
+    _T_1909 <= ld_single_ecc_error_hi_r_ns @[lsu_dccm_ctl.scala 283:73]
+    ld_single_ecc_error_hi_r_ff <= _T_1909 @[lsu_dccm_ctl.scala 283:33]
+    reg _T_1910 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_dccm_ctl.scala 284:73]
+    _T_1910 <= ld_single_ecc_error_lo_r_ns @[lsu_dccm_ctl.scala 284:73]
+    ld_single_ecc_error_lo_r_ff <= _T_1910 @[lsu_dccm_ctl.scala 284:33]
+    node _T_1911 = bits(io.end_addr_r, 15, 0) @[lsu_dccm_ctl.scala 285:48]
+    node _T_1912 = or(io.ld_single_ecc_error_r, io.clk_override) @[lsu_dccm_ctl.scala 285:90]
+    node _T_1913 = bits(_T_1912, 0, 0) @[lib.scala 8:44]
+    node _T_1914 = bits(io.scan_mode, 0, 0) @[lsu_dccm_ctl.scala 285:128]
+    inst rvclkhdr_8 of rvclkhdr_8 @[lib.scala 390:23]
+    rvclkhdr_8.clock <= clock
+    rvclkhdr_8.reset <= reset
+    rvclkhdr_8.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr_8.io.en <= _T_1913 @[lib.scala 393:17]
+    rvclkhdr_8.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg _T_1915 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_1913 : @[Reg.scala 28:19]
+      _T_1915 <= _T_1911 @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    ld_sec_addr_hi_r_ff <= _T_1915 @[lsu_dccm_ctl.scala 285:25]
+    node _T_1916 = bits(io.lsu_addr_r, 15, 0) @[lsu_dccm_ctl.scala 286:48]
+    node _T_1917 = or(io.ld_single_ecc_error_r, io.clk_override) @[lsu_dccm_ctl.scala 286:90]
+    node _T_1918 = bits(_T_1917, 0, 0) @[lib.scala 8:44]
+    node _T_1919 = bits(io.scan_mode, 0, 0) @[lsu_dccm_ctl.scala 286:128]
+    inst rvclkhdr_9 of rvclkhdr_9 @[lib.scala 390:23]
+    rvclkhdr_9.clock <= clock
+    rvclkhdr_9.reset <= reset
+    rvclkhdr_9.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr_9.io.en <= _T_1918 @[lib.scala 393:17]
+    rvclkhdr_9.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg _T_1920 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_1918 : @[Reg.scala 28:19]
+      _T_1920 <= _T_1916 @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    ld_sec_addr_lo_r_ff <= _T_1920 @[lsu_dccm_ctl.scala 286:25]
+    
diff --git a/lsu_dccm_ctl.v b/lsu_dccm_ctl.v
new file mode 100644
index 00000000..cd985e6d
--- /dev/null
+++ b/lsu_dccm_ctl.v
@@ -0,0 +1,1436 @@
+module rvclkhdr(
+  input   io_clk,
+  input   io_en
+);
+  wire  clkhdr_Q; // @[lib.scala 334:26]
+  wire  clkhdr_CK; // @[lib.scala 334:26]
+  wire  clkhdr_EN; // @[lib.scala 334:26]
+  wire  clkhdr_SE; // @[lib.scala 334:26]
+  gated_latch clkhdr ( // @[lib.scala 334:26]
+    .Q(clkhdr_Q),
+    .CK(clkhdr_CK),
+    .EN(clkhdr_EN),
+    .SE(clkhdr_SE)
+  );
+  assign clkhdr_CK = io_clk; // @[lib.scala 336:18]
+  assign clkhdr_EN = io_en; // @[lib.scala 337:18]
+  assign clkhdr_SE = 1'h0; // @[lib.scala 338:18]
+endmodule
+module lsu_dccm_ctl(
+  input         clock,
+  input         reset,
+  input         io_clk_override,
+  input         io_lsu_c2_m_clk,
+  input         io_lsu_c2_r_clk,
+  input         io_lsu_free_c2_clk,
+  input         io_lsu_c1_r_clk,
+  input         io_lsu_store_c1_r_clk,
+  input         io_lsu_pkt_d_valid,
+  input         io_lsu_pkt_d_bits_fast_int,
+  input         io_lsu_pkt_d_bits_stack,
+  input         io_lsu_pkt_d_bits_by,
+  input         io_lsu_pkt_d_bits_half,
+  input         io_lsu_pkt_d_bits_word,
+  input         io_lsu_pkt_d_bits_dword,
+  input         io_lsu_pkt_d_bits_load,
+  input         io_lsu_pkt_d_bits_store,
+  input         io_lsu_pkt_d_bits_unsign,
+  input         io_lsu_pkt_d_bits_dma,
+  input         io_lsu_pkt_d_bits_store_data_bypass_d,
+  input         io_lsu_pkt_d_bits_load_ldst_bypass_d,
+  input         io_lsu_pkt_d_bits_store_data_bypass_m,
+  input         io_lsu_pkt_m_valid,
+  input         io_lsu_pkt_m_bits_fast_int,
+  input         io_lsu_pkt_m_bits_stack,
+  input         io_lsu_pkt_m_bits_by,
+  input         io_lsu_pkt_m_bits_half,
+  input         io_lsu_pkt_m_bits_word,
+  input         io_lsu_pkt_m_bits_dword,
+  input         io_lsu_pkt_m_bits_load,
+  input         io_lsu_pkt_m_bits_store,
+  input         io_lsu_pkt_m_bits_unsign,
+  input         io_lsu_pkt_m_bits_dma,
+  input         io_lsu_pkt_m_bits_store_data_bypass_d,
+  input         io_lsu_pkt_m_bits_load_ldst_bypass_d,
+  input         io_lsu_pkt_m_bits_store_data_bypass_m,
+  input         io_lsu_pkt_r_valid,
+  input         io_lsu_pkt_r_bits_fast_int,
+  input         io_lsu_pkt_r_bits_stack,
+  input         io_lsu_pkt_r_bits_by,
+  input         io_lsu_pkt_r_bits_half,
+  input         io_lsu_pkt_r_bits_word,
+  input         io_lsu_pkt_r_bits_dword,
+  input         io_lsu_pkt_r_bits_load,
+  input         io_lsu_pkt_r_bits_store,
+  input         io_lsu_pkt_r_bits_unsign,
+  input         io_lsu_pkt_r_bits_dma,
+  input         io_lsu_pkt_r_bits_store_data_bypass_d,
+  input         io_lsu_pkt_r_bits_load_ldst_bypass_d,
+  input         io_lsu_pkt_r_bits_store_data_bypass_m,
+  input         io_addr_in_dccm_d,
+  input         io_addr_in_dccm_m,
+  input         io_addr_in_dccm_r,
+  input         io_addr_in_pic_d,
+  input         io_addr_in_pic_m,
+  input         io_addr_in_pic_r,
+  input         io_lsu_raw_fwd_lo_r,
+  input         io_lsu_raw_fwd_hi_r,
+  input         io_lsu_commit_r,
+  input         io_ldst_dual_m,
+  input         io_ldst_dual_r,
+  input  [31:0] io_lsu_addr_d,
+  input  [15:0] io_lsu_addr_m,
+  input  [31:0] io_lsu_addr_r,
+  input  [15:0] io_end_addr_d,
+  input  [15:0] io_end_addr_m,
+  input  [15:0] io_end_addr_r,
+  input         io_stbuf_reqvld_any,
+  input  [15:0] io_stbuf_addr_any,
+  input  [31:0] io_stbuf_data_any,
+  input  [6:0]  io_stbuf_ecc_any,
+  input  [31:0] io_stbuf_fwddata_hi_m,
+  input  [31:0] io_stbuf_fwddata_lo_m,
+  input  [3:0]  io_stbuf_fwdbyteen_lo_m,
+  input  [3:0]  io_stbuf_fwdbyteen_hi_m,
+  output [31:0] io_dccm_rdata_hi_r,
+  output [31:0] io_dccm_rdata_lo_r,
+  output [6:0]  io_dccm_data_ecc_hi_r,
+  output [6:0]  io_dccm_data_ecc_lo_r,
+  output [31:0] io_lsu_ld_data_r,
+  output [31:0] io_lsu_ld_data_corr_r,
+  input         io_lsu_double_ecc_error_r,
+  input         io_single_ecc_error_hi_r,
+  input         io_single_ecc_error_lo_r,
+  input  [31:0] io_sec_data_hi_r,
+  input  [31:0] io_sec_data_lo_r,
+  input  [31:0] io_sec_data_hi_r_ff,
+  input  [31:0] io_sec_data_lo_r_ff,
+  input  [6:0]  io_sec_data_ecc_hi_r_ff,
+  input  [6:0]  io_sec_data_ecc_lo_r_ff,
+  output [31:0] io_dccm_rdata_hi_m,
+  output [31:0] io_dccm_rdata_lo_m,
+  output [6:0]  io_dccm_data_ecc_hi_m,
+  output [6:0]  io_dccm_data_ecc_lo_m,
+  output [31:0] io_lsu_ld_data_m,
+  input         io_lsu_double_ecc_error_m,
+  input  [31:0] io_sec_data_hi_m,
+  input  [31:0] io_sec_data_lo_m,
+  input  [31:0] io_store_data_m,
+  input         io_dma_dccm_wen,
+  input         io_dma_pic_wen,
+  input  [2:0]  io_dma_mem_tag_m,
+  input  [31:0] io_dma_dccm_wdata_lo,
+  input  [31:0] io_dma_dccm_wdata_hi,
+  input  [6:0]  io_dma_dccm_wdata_ecc_hi,
+  input  [6:0]  io_dma_dccm_wdata_ecc_lo,
+  output [31:0] io_store_data_hi_r,
+  output [31:0] io_store_data_lo_r,
+  output [31:0] io_store_datafn_hi_r,
+  output [31:0] io_store_datafn_lo_r,
+  output [31:0] io_store_data_r,
+  output        io_ld_single_ecc_error_r,
+  output        io_ld_single_ecc_error_r_ff,
+  output [31:0] io_picm_mask_data_m,
+  output        io_lsu_stbuf_commit_any,
+  output        io_lsu_dccm_rden_m,
+  output        io_lsu_dccm_rden_r,
+  input  [31:0] io_dma_dccm_ctl_dma_mem_addr,
+  input  [63:0] io_dma_dccm_ctl_dma_mem_wdata,
+  output        io_dma_dccm_ctl_dccm_dma_rvalid,
+  output        io_dma_dccm_ctl_dccm_dma_ecc_error,
+  output [2:0]  io_dma_dccm_ctl_dccm_dma_rtag,
+  output [63:0] io_dma_dccm_ctl_dccm_dma_rdata,
+  output        io_dccm_wren,
+  output        io_dccm_rden,
+  output [15:0] io_dccm_wr_addr_lo,
+  output [15:0] io_dccm_wr_addr_hi,
+  output [15:0] io_dccm_rd_addr_lo,
+  output [15:0] io_dccm_rd_addr_hi,
+  output [38:0] io_dccm_wr_data_lo,
+  output [38:0] io_dccm_wr_data_hi,
+  input  [38:0] io_dccm_rd_data_lo,
+  input  [38:0] io_dccm_rd_data_hi,
+  output        io_lsu_pic_picm_wren,
+  output        io_lsu_pic_picm_rden,
+  output        io_lsu_pic_picm_mken,
+  output [31:0] io_lsu_pic_picm_rdaddr,
+  output [31:0] io_lsu_pic_picm_wraddr,
+  output [31:0] io_lsu_pic_picm_wr_data,
+  input  [31:0] io_lsu_pic_picm_rd_data,
+  input         io_scan_mode
+);
+`ifdef RANDOMIZE_REG_INIT
+  reg [31:0] _RAND_0;
+  reg [31:0] _RAND_1;
+  reg [31:0] _RAND_2;
+  reg [31:0] _RAND_3;
+  reg [31:0] _RAND_4;
+  reg [31:0] _RAND_5;
+  reg [31:0] _RAND_6;
+  reg [31:0] _RAND_7;
+  reg [31:0] _RAND_8;
+  reg [31:0] _RAND_9;
+  reg [31:0] _RAND_10;
+  reg [31:0] _RAND_11;
+  reg [31:0] _RAND_12;
+  reg [31:0] _RAND_13;
+  reg [31:0] _RAND_14;
+  reg [31:0] _RAND_15;
+  reg [31:0] _RAND_16;
+  reg [31:0] _RAND_17;
+  reg [31:0] _RAND_18;
+  reg [31:0] _RAND_19;
+  reg [31:0] _RAND_20;
+`endif // RANDOMIZE_REG_INIT
+  wire  rvclkhdr_io_clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_io_en; // @[lib.scala 390:23]
+  wire  rvclkhdr_1_io_clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_1_io_en; // @[lib.scala 390:23]
+  wire  rvclkhdr_2_io_clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_2_io_en; // @[lib.scala 390:23]
+  wire  rvclkhdr_3_io_clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_3_io_en; // @[lib.scala 390:23]
+  wire  rvclkhdr_4_io_clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_4_io_en; // @[lib.scala 390:23]
+  wire  rvclkhdr_5_io_clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_5_io_en; // @[lib.scala 390:23]
+  wire  rvclkhdr_6_io_clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_6_io_en; // @[lib.scala 390:23]
+  wire  rvclkhdr_7_io_clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_7_io_en; // @[lib.scala 390:23]
+  wire  rvclkhdr_8_io_clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_8_io_en; // @[lib.scala 390:23]
+  wire  rvclkhdr_9_io_clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_9_io_en; // @[lib.scala 390:23]
+  wire [63:0] picm_rd_data_m = {io_lsu_pic_picm_rd_data,io_lsu_pic_picm_rd_data}; // @[Cat.scala 29:58]
+  wire [63:0] dccm_rdata_corr_r = {io_sec_data_hi_r,io_sec_data_lo_r}; // @[Cat.scala 29:58]
+  wire [63:0] dccm_rdata_r = {io_dccm_rdata_hi_r,io_dccm_rdata_lo_r}; // @[Cat.scala 29:58]
+  wire  _T = io_lsu_pkt_r_valid & io_lsu_pkt_r_bits_load; // @[lsu_dccm_ctl.scala 124:62]
+  reg [7:0] _T_28; // @[lsu_dccm_ctl.scala 133:64]
+  wire [63:0] stbuf_fwdbyteen_r = {{56'd0}, _T_28}; // @[lsu_dccm_ctl.scala 133:27]
+  reg [31:0] _T_31; // @[Reg.scala 27:20]
+  reg [31:0] _T_34; // @[Reg.scala 27:20]
+  wire [63:0] stbuf_fwddata_r = {_T_31,_T_34}; // @[Cat.scala 29:58]
+  reg [31:0] picm_rd_data_r_32; // @[Reg.scala 27:20]
+  wire [63:0] picm_rd_data_r = {picm_rd_data_r_32,picm_rd_data_r_32}; // @[Cat.scala 29:58]
+  wire [7:0] _T_49 = io_addr_in_dccm_r ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
+  wire [7:0] _T_51 = _T_49 & dccm_rdata_corr_r[7:0]; // @[lsu_dccm_ctl.scala 138:219]
+  wire [7:0] _T_52 = io_addr_in_pic_r ? picm_rd_data_r[7:0] : _T_51; // @[lsu_dccm_ctl.scala 138:139]
+  wire [7:0] _T_53 = stbuf_fwdbyteen_r[0] ? stbuf_fwddata_r[7:0] : _T_52; // @[lsu_dccm_ctl.scala 138:77]
+  wire [7:0] _T_57 = {{4'd0}, _T_53[7:4]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_59 = {_T_53[3:0], 4'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_61 = _T_59 & 8'hf0; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_62 = _T_57 | _T_61; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_10 = {{2'd0}, _T_62[7:2]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_67 = _GEN_10 & 8'h33; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_69 = {_T_62[5:0], 2'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_71 = _T_69 & 8'hcc; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_72 = _T_67 | _T_71; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_11 = {{1'd0}, _T_72[7:1]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_77 = _GEN_11 & 8'h55; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_79 = {_T_72[6:0], 1'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_81 = _T_79 & 8'haa; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_82 = _T_77 | _T_81; // @[Bitwise.scala 103:39]
+  wire [7:0] _T_91 = _T_49 & dccm_rdata_corr_r[15:8]; // @[lsu_dccm_ctl.scala 138:219]
+  wire [7:0] _T_92 = io_addr_in_pic_r ? picm_rd_data_r[15:8] : _T_91; // @[lsu_dccm_ctl.scala 138:139]
+  wire [7:0] _T_93 = stbuf_fwdbyteen_r[1] ? stbuf_fwddata_r[15:8] : _T_92; // @[lsu_dccm_ctl.scala 138:77]
+  wire [7:0] _T_97 = {{4'd0}, _T_93[7:4]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_99 = {_T_93[3:0], 4'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_101 = _T_99 & 8'hf0; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_102 = _T_97 | _T_101; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_12 = {{2'd0}, _T_102[7:2]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_107 = _GEN_12 & 8'h33; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_109 = {_T_102[5:0], 2'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_111 = _T_109 & 8'hcc; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_112 = _T_107 | _T_111; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_13 = {{1'd0}, _T_112[7:1]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_117 = _GEN_13 & 8'h55; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_119 = {_T_112[6:0], 1'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_121 = _T_119 & 8'haa; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_122 = _T_117 | _T_121; // @[Bitwise.scala 103:39]
+  wire [7:0] _T_131 = _T_49 & dccm_rdata_corr_r[23:16]; // @[lsu_dccm_ctl.scala 138:219]
+  wire [7:0] _T_132 = io_addr_in_pic_r ? picm_rd_data_r[23:16] : _T_131; // @[lsu_dccm_ctl.scala 138:139]
+  wire [7:0] _T_133 = stbuf_fwdbyteen_r[2] ? stbuf_fwddata_r[23:16] : _T_132; // @[lsu_dccm_ctl.scala 138:77]
+  wire [7:0] _T_137 = {{4'd0}, _T_133[7:4]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_139 = {_T_133[3:0], 4'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_141 = _T_139 & 8'hf0; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_142 = _T_137 | _T_141; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_14 = {{2'd0}, _T_142[7:2]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_147 = _GEN_14 & 8'h33; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_149 = {_T_142[5:0], 2'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_151 = _T_149 & 8'hcc; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_152 = _T_147 | _T_151; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_15 = {{1'd0}, _T_152[7:1]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_157 = _GEN_15 & 8'h55; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_159 = {_T_152[6:0], 1'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_161 = _T_159 & 8'haa; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_162 = _T_157 | _T_161; // @[Bitwise.scala 103:39]
+  wire [7:0] _T_171 = _T_49 & dccm_rdata_corr_r[31:24]; // @[lsu_dccm_ctl.scala 138:219]
+  wire [7:0] _T_172 = io_addr_in_pic_r ? picm_rd_data_r[31:24] : _T_171; // @[lsu_dccm_ctl.scala 138:139]
+  wire [7:0] _T_173 = stbuf_fwdbyteen_r[3] ? stbuf_fwddata_r[31:24] : _T_172; // @[lsu_dccm_ctl.scala 138:77]
+  wire [7:0] _T_177 = {{4'd0}, _T_173[7:4]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_179 = {_T_173[3:0], 4'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_181 = _T_179 & 8'hf0; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_182 = _T_177 | _T_181; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_16 = {{2'd0}, _T_182[7:2]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_187 = _GEN_16 & 8'h33; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_189 = {_T_182[5:0], 2'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_191 = _T_189 & 8'hcc; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_192 = _T_187 | _T_191; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_17 = {{1'd0}, _T_192[7:1]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_197 = _GEN_17 & 8'h55; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_199 = {_T_192[6:0], 1'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_201 = _T_199 & 8'haa; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_202 = _T_197 | _T_201; // @[Bitwise.scala 103:39]
+  wire [7:0] _T_211 = _T_49 & dccm_rdata_corr_r[39:32]; // @[lsu_dccm_ctl.scala 138:219]
+  wire [7:0] _T_212 = io_addr_in_pic_r ? picm_rd_data_r[39:32] : _T_211; // @[lsu_dccm_ctl.scala 138:139]
+  wire [7:0] _T_213 = stbuf_fwdbyteen_r[4] ? stbuf_fwddata_r[39:32] : _T_212; // @[lsu_dccm_ctl.scala 138:77]
+  wire [7:0] _T_217 = {{4'd0}, _T_213[7:4]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_219 = {_T_213[3:0], 4'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_221 = _T_219 & 8'hf0; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_222 = _T_217 | _T_221; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_18 = {{2'd0}, _T_222[7:2]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_227 = _GEN_18 & 8'h33; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_229 = {_T_222[5:0], 2'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_231 = _T_229 & 8'hcc; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_232 = _T_227 | _T_231; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_19 = {{1'd0}, _T_232[7:1]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_237 = _GEN_19 & 8'h55; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_239 = {_T_232[6:0], 1'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_241 = _T_239 & 8'haa; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_242 = _T_237 | _T_241; // @[Bitwise.scala 103:39]
+  wire [7:0] _T_251 = _T_49 & dccm_rdata_corr_r[47:40]; // @[lsu_dccm_ctl.scala 138:219]
+  wire [7:0] _T_252 = io_addr_in_pic_r ? picm_rd_data_r[47:40] : _T_251; // @[lsu_dccm_ctl.scala 138:139]
+  wire [7:0] _T_253 = stbuf_fwdbyteen_r[5] ? stbuf_fwddata_r[47:40] : _T_252; // @[lsu_dccm_ctl.scala 138:77]
+  wire [7:0] _T_257 = {{4'd0}, _T_253[7:4]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_259 = {_T_253[3:0], 4'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_261 = _T_259 & 8'hf0; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_262 = _T_257 | _T_261; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_20 = {{2'd0}, _T_262[7:2]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_267 = _GEN_20 & 8'h33; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_269 = {_T_262[5:0], 2'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_271 = _T_269 & 8'hcc; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_272 = _T_267 | _T_271; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_21 = {{1'd0}, _T_272[7:1]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_277 = _GEN_21 & 8'h55; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_279 = {_T_272[6:0], 1'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_281 = _T_279 & 8'haa; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_282 = _T_277 | _T_281; // @[Bitwise.scala 103:39]
+  wire [7:0] _T_291 = _T_49 & dccm_rdata_corr_r[55:48]; // @[lsu_dccm_ctl.scala 138:219]
+  wire [7:0] _T_292 = io_addr_in_pic_r ? picm_rd_data_r[55:48] : _T_291; // @[lsu_dccm_ctl.scala 138:139]
+  wire [7:0] _T_293 = stbuf_fwdbyteen_r[6] ? stbuf_fwddata_r[55:48] : _T_292; // @[lsu_dccm_ctl.scala 138:77]
+  wire [7:0] _T_297 = {{4'd0}, _T_293[7:4]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_299 = {_T_293[3:0], 4'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_301 = _T_299 & 8'hf0; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_302 = _T_297 | _T_301; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_22 = {{2'd0}, _T_302[7:2]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_307 = _GEN_22 & 8'h33; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_309 = {_T_302[5:0], 2'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_311 = _T_309 & 8'hcc; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_312 = _T_307 | _T_311; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_23 = {{1'd0}, _T_312[7:1]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_317 = _GEN_23 & 8'h55; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_319 = {_T_312[6:0], 1'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_321 = _T_319 & 8'haa; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_322 = _T_317 | _T_321; // @[Bitwise.scala 103:39]
+  wire [7:0] _T_331 = _T_49 & dccm_rdata_corr_r[63:56]; // @[lsu_dccm_ctl.scala 138:219]
+  wire [7:0] _T_332 = io_addr_in_pic_r ? picm_rd_data_r[63:56] : _T_331; // @[lsu_dccm_ctl.scala 138:139]
+  wire [7:0] _T_333 = stbuf_fwdbyteen_r[7] ? stbuf_fwddata_r[63:56] : _T_332; // @[lsu_dccm_ctl.scala 138:77]
+  wire [7:0] _T_337 = {{4'd0}, _T_333[7:4]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_339 = {_T_333[3:0], 4'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_341 = _T_339 & 8'hf0; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_342 = _T_337 | _T_341; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_24 = {{2'd0}, _T_342[7:2]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_347 = _GEN_24 & 8'h33; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_349 = {_T_342[5:0], 2'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_351 = _T_349 & 8'hcc; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_352 = _T_347 | _T_351; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_25 = {{1'd0}, _T_352[7:1]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_357 = _GEN_25 & 8'h55; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_359 = {_T_352[6:0], 1'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_361 = _T_359 & 8'haa; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_362 = _T_357 | _T_361; // @[Bitwise.scala 103:39]
+  wire [63:0] _T_370 = {_T_82,_T_122,_T_162,_T_202,_T_242,_T_282,_T_322,_T_362}; // @[Cat.scala 29:58]
+  wire [63:0] _T_374 = {{32'd0}, _T_370[63:32]}; // @[Bitwise.scala 103:31]
+  wire [63:0] _T_376 = {_T_370[31:0], 32'h0}; // @[Bitwise.scala 103:65]
+  wire [63:0] _T_378 = _T_376 & 64'hffffffff00000000; // @[Bitwise.scala 103:75]
+  wire [63:0] _T_379 = _T_374 | _T_378; // @[Bitwise.scala 103:39]
+  wire [63:0] _GEN_26 = {{16'd0}, _T_379[63:16]}; // @[Bitwise.scala 103:31]
+  wire [63:0] _T_384 = _GEN_26 & 64'hffff0000ffff; // @[Bitwise.scala 103:31]
+  wire [63:0] _T_386 = {_T_379[47:0], 16'h0}; // @[Bitwise.scala 103:65]
+  wire [63:0] _T_388 = _T_386 & 64'hffff0000ffff0000; // @[Bitwise.scala 103:75]
+  wire [63:0] _T_389 = _T_384 | _T_388; // @[Bitwise.scala 103:39]
+  wire [63:0] _GEN_27 = {{8'd0}, _T_389[63:8]}; // @[Bitwise.scala 103:31]
+  wire [63:0] _T_394 = _GEN_27 & 64'hff00ff00ff00ff; // @[Bitwise.scala 103:31]
+  wire [63:0] _T_396 = {_T_389[55:0], 8'h0}; // @[Bitwise.scala 103:65]
+  wire [63:0] _T_398 = _T_396 & 64'hff00ff00ff00ff00; // @[Bitwise.scala 103:75]
+  wire [63:0] _T_399 = _T_394 | _T_398; // @[Bitwise.scala 103:39]
+  wire [63:0] _GEN_28 = {{4'd0}, _T_399[63:4]}; // @[Bitwise.scala 103:31]
+  wire [63:0] _T_404 = _GEN_28 & 64'hf0f0f0f0f0f0f0f; // @[Bitwise.scala 103:31]
+  wire [63:0] _T_406 = {_T_399[59:0], 4'h0}; // @[Bitwise.scala 103:65]
+  wire [63:0] _T_408 = _T_406 & 64'hf0f0f0f0f0f0f0f0; // @[Bitwise.scala 103:75]
+  wire [63:0] _T_409 = _T_404 | _T_408; // @[Bitwise.scala 103:39]
+  wire [63:0] _GEN_29 = {{2'd0}, _T_409[63:2]}; // @[Bitwise.scala 103:31]
+  wire [63:0] _T_414 = _GEN_29 & 64'h3333333333333333; // @[Bitwise.scala 103:31]
+  wire [63:0] _T_416 = {_T_409[61:0], 2'h0}; // @[Bitwise.scala 103:65]
+  wire [63:0] _T_418 = _T_416 & 64'hcccccccccccccccc; // @[Bitwise.scala 103:75]
+  wire [63:0] _T_419 = _T_414 | _T_418; // @[Bitwise.scala 103:39]
+  wire [63:0] _GEN_30 = {{1'd0}, _T_419[63:1]}; // @[Bitwise.scala 103:31]
+  wire [63:0] _T_424 = _GEN_30 & 64'h5555555555555555; // @[Bitwise.scala 103:31]
+  wire [63:0] _T_426 = {_T_419[62:0], 1'h0}; // @[Bitwise.scala 103:65]
+  wire [63:0] _T_428 = _T_426 & 64'haaaaaaaaaaaaaaaa; // @[Bitwise.scala 103:75]
+  wire [63:0] lsu_rdata_corr_r = _T_424 | _T_428; // @[Bitwise.scala 103:39]
+  wire [63:0] _T_4 = {lsu_rdata_corr_r[31:0],lsu_rdata_corr_r[31:0]}; // @[Cat.scala 29:58]
+  wire  _T_6 = |io_stbuf_fwdbyteen_hi_m; // @[lsu_dccm_ctl.scala 127:49]
+  wire  _T_7 = |io_stbuf_fwdbyteen_lo_m; // @[lsu_dccm_ctl.scala 127:79]
+  wire  _T_8 = _T_6 | _T_7; // @[lsu_dccm_ctl.scala 127:53]
+  wire  stbuf_fwddata_en = _T_8 | io_clk_override; // @[lsu_dccm_ctl.scala 127:83]
+  wire  _T_10 = io_lsu_dccm_rden_m & io_ldst_dual_m; // @[lsu_dccm_ctl.scala 129:77]
+  wire  _T_11 = _T_10 | io_clk_override; // @[lsu_dccm_ctl.scala 129:95]
+  reg [31:0] _T_14; // @[Reg.scala 27:20]
+  wire  _T_15 = io_lsu_dccm_rden_m | io_clk_override; // @[lsu_dccm_ctl.scala 130:75]
+  reg [31:0] _T_18; // @[Reg.scala 27:20]
+  reg [6:0] _T_22; // @[Reg.scala 27:20]
+  reg [6:0] _T_26; // @[Reg.scala 27:20]
+  wire  _T_37 = io_addr_in_pic_m | io_clk_override; // @[lsu_dccm_ctl.scala 135:76]
+  reg [2:0] _T_42; // @[lsu_dccm_ctl.scala 137:77]
+  wire [7:0] _T_438 = _T_49 & dccm_rdata_r[7:0]; // @[lsu_dccm_ctl.scala 139:219]
+  wire [7:0] _T_439 = io_addr_in_pic_r ? picm_rd_data_r[7:0] : _T_438; // @[lsu_dccm_ctl.scala 139:139]
+  wire [7:0] _T_440 = stbuf_fwdbyteen_r[0] ? stbuf_fwddata_r[7:0] : _T_439; // @[lsu_dccm_ctl.scala 139:77]
+  wire [7:0] _T_444 = {{4'd0}, _T_440[7:4]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_446 = {_T_440[3:0], 4'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_448 = _T_446 & 8'hf0; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_449 = _T_444 | _T_448; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_31 = {{2'd0}, _T_449[7:2]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_454 = _GEN_31 & 8'h33; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_456 = {_T_449[5:0], 2'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_458 = _T_456 & 8'hcc; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_459 = _T_454 | _T_458; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_32 = {{1'd0}, _T_459[7:1]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_464 = _GEN_32 & 8'h55; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_466 = {_T_459[6:0], 1'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_468 = _T_466 & 8'haa; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_469 = _T_464 | _T_468; // @[Bitwise.scala 103:39]
+  wire [7:0] _T_478 = _T_49 & dccm_rdata_r[15:8]; // @[lsu_dccm_ctl.scala 139:219]
+  wire [7:0] _T_479 = io_addr_in_pic_r ? picm_rd_data_r[15:8] : _T_478; // @[lsu_dccm_ctl.scala 139:139]
+  wire [7:0] _T_480 = stbuf_fwdbyteen_r[1] ? stbuf_fwddata_r[15:8] : _T_479; // @[lsu_dccm_ctl.scala 139:77]
+  wire [7:0] _T_484 = {{4'd0}, _T_480[7:4]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_486 = {_T_480[3:0], 4'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_488 = _T_486 & 8'hf0; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_489 = _T_484 | _T_488; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_33 = {{2'd0}, _T_489[7:2]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_494 = _GEN_33 & 8'h33; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_496 = {_T_489[5:0], 2'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_498 = _T_496 & 8'hcc; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_499 = _T_494 | _T_498; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_34 = {{1'd0}, _T_499[7:1]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_504 = _GEN_34 & 8'h55; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_506 = {_T_499[6:0], 1'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_508 = _T_506 & 8'haa; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_509 = _T_504 | _T_508; // @[Bitwise.scala 103:39]
+  wire [7:0] _T_518 = _T_49 & dccm_rdata_r[23:16]; // @[lsu_dccm_ctl.scala 139:219]
+  wire [7:0] _T_519 = io_addr_in_pic_r ? picm_rd_data_r[23:16] : _T_518; // @[lsu_dccm_ctl.scala 139:139]
+  wire [7:0] _T_520 = stbuf_fwdbyteen_r[2] ? stbuf_fwddata_r[23:16] : _T_519; // @[lsu_dccm_ctl.scala 139:77]
+  wire [7:0] _T_524 = {{4'd0}, _T_520[7:4]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_526 = {_T_520[3:0], 4'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_528 = _T_526 & 8'hf0; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_529 = _T_524 | _T_528; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_35 = {{2'd0}, _T_529[7:2]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_534 = _GEN_35 & 8'h33; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_536 = {_T_529[5:0], 2'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_538 = _T_536 & 8'hcc; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_539 = _T_534 | _T_538; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_36 = {{1'd0}, _T_539[7:1]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_544 = _GEN_36 & 8'h55; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_546 = {_T_539[6:0], 1'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_548 = _T_546 & 8'haa; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_549 = _T_544 | _T_548; // @[Bitwise.scala 103:39]
+  wire [7:0] _T_558 = _T_49 & dccm_rdata_r[31:24]; // @[lsu_dccm_ctl.scala 139:219]
+  wire [7:0] _T_559 = io_addr_in_pic_r ? picm_rd_data_r[31:24] : _T_558; // @[lsu_dccm_ctl.scala 139:139]
+  wire [7:0] _T_560 = stbuf_fwdbyteen_r[3] ? stbuf_fwddata_r[31:24] : _T_559; // @[lsu_dccm_ctl.scala 139:77]
+  wire [7:0] _T_564 = {{4'd0}, _T_560[7:4]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_566 = {_T_560[3:0], 4'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_568 = _T_566 & 8'hf0; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_569 = _T_564 | _T_568; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_37 = {{2'd0}, _T_569[7:2]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_574 = _GEN_37 & 8'h33; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_576 = {_T_569[5:0], 2'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_578 = _T_576 & 8'hcc; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_579 = _T_574 | _T_578; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_38 = {{1'd0}, _T_579[7:1]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_584 = _GEN_38 & 8'h55; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_586 = {_T_579[6:0], 1'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_588 = _T_586 & 8'haa; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_589 = _T_584 | _T_588; // @[Bitwise.scala 103:39]
+  wire [7:0] _T_598 = _T_49 & dccm_rdata_r[39:32]; // @[lsu_dccm_ctl.scala 139:219]
+  wire [7:0] _T_599 = io_addr_in_pic_r ? picm_rd_data_r[39:32] : _T_598; // @[lsu_dccm_ctl.scala 139:139]
+  wire [7:0] _T_600 = stbuf_fwdbyteen_r[4] ? stbuf_fwddata_r[39:32] : _T_599; // @[lsu_dccm_ctl.scala 139:77]
+  wire [7:0] _T_604 = {{4'd0}, _T_600[7:4]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_606 = {_T_600[3:0], 4'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_608 = _T_606 & 8'hf0; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_609 = _T_604 | _T_608; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_39 = {{2'd0}, _T_609[7:2]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_614 = _GEN_39 & 8'h33; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_616 = {_T_609[5:0], 2'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_618 = _T_616 & 8'hcc; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_619 = _T_614 | _T_618; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_40 = {{1'd0}, _T_619[7:1]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_624 = _GEN_40 & 8'h55; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_626 = {_T_619[6:0], 1'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_628 = _T_626 & 8'haa; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_629 = _T_624 | _T_628; // @[Bitwise.scala 103:39]
+  wire [7:0] _T_638 = _T_49 & dccm_rdata_r[47:40]; // @[lsu_dccm_ctl.scala 139:219]
+  wire [7:0] _T_639 = io_addr_in_pic_r ? picm_rd_data_r[47:40] : _T_638; // @[lsu_dccm_ctl.scala 139:139]
+  wire [7:0] _T_640 = stbuf_fwdbyteen_r[5] ? stbuf_fwddata_r[47:40] : _T_639; // @[lsu_dccm_ctl.scala 139:77]
+  wire [7:0] _T_644 = {{4'd0}, _T_640[7:4]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_646 = {_T_640[3:0], 4'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_648 = _T_646 & 8'hf0; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_649 = _T_644 | _T_648; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_41 = {{2'd0}, _T_649[7:2]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_654 = _GEN_41 & 8'h33; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_656 = {_T_649[5:0], 2'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_658 = _T_656 & 8'hcc; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_659 = _T_654 | _T_658; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_42 = {{1'd0}, _T_659[7:1]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_664 = _GEN_42 & 8'h55; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_666 = {_T_659[6:0], 1'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_668 = _T_666 & 8'haa; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_669 = _T_664 | _T_668; // @[Bitwise.scala 103:39]
+  wire [7:0] _T_678 = _T_49 & dccm_rdata_r[55:48]; // @[lsu_dccm_ctl.scala 139:219]
+  wire [7:0] _T_679 = io_addr_in_pic_r ? picm_rd_data_r[55:48] : _T_678; // @[lsu_dccm_ctl.scala 139:139]
+  wire [7:0] _T_680 = stbuf_fwdbyteen_r[6] ? stbuf_fwddata_r[55:48] : _T_679; // @[lsu_dccm_ctl.scala 139:77]
+  wire [7:0] _T_684 = {{4'd0}, _T_680[7:4]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_686 = {_T_680[3:0], 4'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_688 = _T_686 & 8'hf0; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_689 = _T_684 | _T_688; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_43 = {{2'd0}, _T_689[7:2]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_694 = _GEN_43 & 8'h33; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_696 = {_T_689[5:0], 2'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_698 = _T_696 & 8'hcc; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_699 = _T_694 | _T_698; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_44 = {{1'd0}, _T_699[7:1]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_704 = _GEN_44 & 8'h55; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_706 = {_T_699[6:0], 1'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_708 = _T_706 & 8'haa; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_709 = _T_704 | _T_708; // @[Bitwise.scala 103:39]
+  wire [7:0] _T_718 = _T_49 & dccm_rdata_r[63:56]; // @[lsu_dccm_ctl.scala 139:219]
+  wire [7:0] _T_719 = io_addr_in_pic_r ? picm_rd_data_r[63:56] : _T_718; // @[lsu_dccm_ctl.scala 139:139]
+  wire [7:0] _T_720 = stbuf_fwdbyteen_r[7] ? stbuf_fwddata_r[63:56] : _T_719; // @[lsu_dccm_ctl.scala 139:77]
+  wire [7:0] _T_724 = {{4'd0}, _T_720[7:4]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_726 = {_T_720[3:0], 4'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_728 = _T_726 & 8'hf0; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_729 = _T_724 | _T_728; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_45 = {{2'd0}, _T_729[7:2]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_734 = _GEN_45 & 8'h33; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_736 = {_T_729[5:0], 2'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_738 = _T_736 & 8'hcc; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_739 = _T_734 | _T_738; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_46 = {{1'd0}, _T_739[7:1]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_744 = _GEN_46 & 8'h55; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_746 = {_T_739[6:0], 1'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_748 = _T_746 & 8'haa; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_749 = _T_744 | _T_748; // @[Bitwise.scala 103:39]
+  wire [63:0] _T_757 = {_T_469,_T_509,_T_549,_T_589,_T_629,_T_669,_T_709,_T_749}; // @[Cat.scala 29:58]
+  wire [63:0] _T_761 = {{32'd0}, _T_757[63:32]}; // @[Bitwise.scala 103:31]
+  wire [63:0] _T_763 = {_T_757[31:0], 32'h0}; // @[Bitwise.scala 103:65]
+  wire [63:0] _T_765 = _T_763 & 64'hffffffff00000000; // @[Bitwise.scala 103:75]
+  wire [63:0] _T_766 = _T_761 | _T_765; // @[Bitwise.scala 103:39]
+  wire [63:0] _GEN_47 = {{16'd0}, _T_766[63:16]}; // @[Bitwise.scala 103:31]
+  wire [63:0] _T_771 = _GEN_47 & 64'hffff0000ffff; // @[Bitwise.scala 103:31]
+  wire [63:0] _T_773 = {_T_766[47:0], 16'h0}; // @[Bitwise.scala 103:65]
+  wire [63:0] _T_775 = _T_773 & 64'hffff0000ffff0000; // @[Bitwise.scala 103:75]
+  wire [63:0] _T_776 = _T_771 | _T_775; // @[Bitwise.scala 103:39]
+  wire [63:0] _GEN_48 = {{8'd0}, _T_776[63:8]}; // @[Bitwise.scala 103:31]
+  wire [63:0] _T_781 = _GEN_48 & 64'hff00ff00ff00ff; // @[Bitwise.scala 103:31]
+  wire [63:0] _T_783 = {_T_776[55:0], 8'h0}; // @[Bitwise.scala 103:65]
+  wire [63:0] _T_785 = _T_783 & 64'hff00ff00ff00ff00; // @[Bitwise.scala 103:75]
+  wire [63:0] _T_786 = _T_781 | _T_785; // @[Bitwise.scala 103:39]
+  wire [63:0] _GEN_49 = {{4'd0}, _T_786[63:4]}; // @[Bitwise.scala 103:31]
+  wire [63:0] _T_791 = _GEN_49 & 64'hf0f0f0f0f0f0f0f; // @[Bitwise.scala 103:31]
+  wire [63:0] _T_793 = {_T_786[59:0], 4'h0}; // @[Bitwise.scala 103:65]
+  wire [63:0] _T_795 = _T_793 & 64'hf0f0f0f0f0f0f0f0; // @[Bitwise.scala 103:75]
+  wire [63:0] _T_796 = _T_791 | _T_795; // @[Bitwise.scala 103:39]
+  wire [63:0] _GEN_50 = {{2'd0}, _T_796[63:2]}; // @[Bitwise.scala 103:31]
+  wire [63:0] _T_801 = _GEN_50 & 64'h3333333333333333; // @[Bitwise.scala 103:31]
+  wire [63:0] _T_803 = {_T_796[61:0], 2'h0}; // @[Bitwise.scala 103:65]
+  wire [63:0] _T_805 = _T_803 & 64'hcccccccccccccccc; // @[Bitwise.scala 103:75]
+  wire [63:0] _T_806 = _T_801 | _T_805; // @[Bitwise.scala 103:39]
+  wire [63:0] _GEN_51 = {{1'd0}, _T_806[63:1]}; // @[Bitwise.scala 103:31]
+  wire [63:0] _T_811 = _GEN_51 & 64'h5555555555555555; // @[Bitwise.scala 103:31]
+  wire [63:0] _T_813 = {_T_806[62:0], 1'h0}; // @[Bitwise.scala 103:65]
+  wire [63:0] _T_815 = _T_813 & 64'haaaaaaaaaaaaaaaa; // @[Bitwise.scala 103:75]
+  wire [63:0] lsu_rdata_r = _T_811 | _T_815; // @[Bitwise.scala 103:39]
+  wire [3:0] _GEN_52 = {{2'd0}, io_lsu_addr_r[1:0]}; // @[lsu_dccm_ctl.scala 140:47]
+  wire [5:0] _T_818 = 4'h8 * _GEN_52; // @[lsu_dccm_ctl.scala 140:47]
+  wire [63:0] _T_819 = lsu_rdata_r >> _T_818; // @[lsu_dccm_ctl.scala 140:41]
+  wire [63:0] _T_822 = lsu_rdata_corr_r >> _T_818; // @[lsu_dccm_ctl.scala 141:47]
+  wire  _T_825 = io_lsu_addr_d[15:2] == io_lsu_addr_r[15:2]; // @[lsu_dccm_ctl.scala 163:60]
+  wire  _T_828 = io_end_addr_d[15:2] == io_lsu_addr_r[15:2]; // @[lsu_dccm_ctl.scala 163:133]
+  wire  _T_829 = _T_825 | _T_828; // @[lsu_dccm_ctl.scala 163:101]
+  wire  _T_830 = _T_829 & io_lsu_pkt_d_valid; // @[lsu_dccm_ctl.scala 163:175]
+  wire  _T_831 = _T_830 & io_lsu_pkt_d_bits_store; // @[lsu_dccm_ctl.scala 163:196]
+  wire  _T_832 = _T_831 & io_lsu_pkt_d_bits_dma; // @[lsu_dccm_ctl.scala 163:222]
+  wire  _T_833 = _T_832 & io_addr_in_dccm_d; // @[lsu_dccm_ctl.scala 163:246]
+  wire  _T_836 = io_lsu_addr_m[15:2] == io_lsu_addr_r[15:2]; // @[lsu_dccm_ctl.scala 164:37]
+  wire  _T_839 = io_end_addr_m[15:2] == io_lsu_addr_r[15:2]; // @[lsu_dccm_ctl.scala 164:110]
+  wire  _T_840 = _T_836 | _T_839; // @[lsu_dccm_ctl.scala 164:78]
+  wire  _T_841 = _T_840 & io_lsu_pkt_m_valid; // @[lsu_dccm_ctl.scala 164:152]
+  wire  _T_842 = _T_841 & io_lsu_pkt_m_bits_store; // @[lsu_dccm_ctl.scala 164:173]
+  wire  _T_843 = _T_842 & io_lsu_pkt_m_bits_dma; // @[lsu_dccm_ctl.scala 164:199]
+  wire  _T_844 = _T_843 & io_addr_in_dccm_m; // @[lsu_dccm_ctl.scala 164:223]
+  wire  kill_ecc_corr_lo_r = _T_833 | _T_844; // @[lsu_dccm_ctl.scala 163:267]
+  wire  _T_847 = io_lsu_addr_d[15:2] == io_end_addr_r[15:2]; // @[lsu_dccm_ctl.scala 166:60]
+  wire  _T_850 = io_end_addr_d[15:2] == io_end_addr_r[15:2]; // @[lsu_dccm_ctl.scala 166:133]
+  wire  _T_851 = _T_847 | _T_850; // @[lsu_dccm_ctl.scala 166:101]
+  wire  _T_852 = _T_851 & io_lsu_pkt_d_valid; // @[lsu_dccm_ctl.scala 166:175]
+  wire  _T_853 = _T_852 & io_lsu_pkt_d_bits_store; // @[lsu_dccm_ctl.scala 166:196]
+  wire  _T_854 = _T_853 & io_lsu_pkt_d_bits_dma; // @[lsu_dccm_ctl.scala 166:222]
+  wire  _T_855 = _T_854 & io_addr_in_dccm_d; // @[lsu_dccm_ctl.scala 166:246]
+  wire  _T_858 = io_lsu_addr_m[15:2] == io_end_addr_r[15:2]; // @[lsu_dccm_ctl.scala 167:37]
+  wire  _T_861 = io_end_addr_m[15:2] == io_end_addr_r[15:2]; // @[lsu_dccm_ctl.scala 167:110]
+  wire  _T_862 = _T_858 | _T_861; // @[lsu_dccm_ctl.scala 167:78]
+  wire  _T_863 = _T_862 & io_lsu_pkt_m_valid; // @[lsu_dccm_ctl.scala 167:152]
+  wire  _T_864 = _T_863 & io_lsu_pkt_m_bits_store; // @[lsu_dccm_ctl.scala 167:173]
+  wire  _T_865 = _T_864 & io_lsu_pkt_m_bits_dma; // @[lsu_dccm_ctl.scala 167:199]
+  wire  _T_866 = _T_865 & io_addr_in_dccm_m; // @[lsu_dccm_ctl.scala 167:223]
+  wire  kill_ecc_corr_hi_r = _T_855 | _T_866; // @[lsu_dccm_ctl.scala 166:267]
+  wire  _T_867 = io_lsu_pkt_r_bits_load & io_single_ecc_error_lo_r; // @[lsu_dccm_ctl.scala 169:60]
+  wire  _T_868 = ~io_lsu_raw_fwd_lo_r; // @[lsu_dccm_ctl.scala 169:89]
+  wire  ld_single_ecc_error_lo_r = _T_867 & _T_868; // @[lsu_dccm_ctl.scala 169:87]
+  wire  _T_869 = io_lsu_pkt_r_bits_load & io_single_ecc_error_hi_r; // @[lsu_dccm_ctl.scala 170:60]
+  wire  _T_870 = ~io_lsu_raw_fwd_hi_r; // @[lsu_dccm_ctl.scala 170:89]
+  wire  ld_single_ecc_error_hi_r = _T_869 & _T_870; // @[lsu_dccm_ctl.scala 170:87]
+  wire  _T_871 = ld_single_ecc_error_lo_r | ld_single_ecc_error_hi_r; // @[lsu_dccm_ctl.scala 171:63]
+  wire  _T_872 = ~io_lsu_double_ecc_error_r; // @[lsu_dccm_ctl.scala 171:93]
+  wire  _T_874 = io_lsu_commit_r | io_lsu_pkt_r_bits_dma; // @[lsu_dccm_ctl.scala 172:81]
+  wire  _T_875 = ld_single_ecc_error_lo_r & _T_874; // @[lsu_dccm_ctl.scala 172:62]
+  wire  _T_876 = ~kill_ecc_corr_lo_r; // @[lsu_dccm_ctl.scala 172:108]
+  wire  _T_878 = ld_single_ecc_error_hi_r & _T_874; // @[lsu_dccm_ctl.scala 173:62]
+  wire  _T_879 = ~kill_ecc_corr_hi_r; // @[lsu_dccm_ctl.scala 173:108]
+  wire  _T_880 = io_lsu_pkt_d_bits_word | io_lsu_pkt_d_bits_dword; // @[lsu_dccm_ctl.scala 175:125]
+  wire  _T_881 = ~_T_880; // @[lsu_dccm_ctl.scala 175:100]
+  wire  _T_883 = io_lsu_addr_d[1:0] != 2'h0; // @[lsu_dccm_ctl.scala 175:174]
+  wire  _T_884 = _T_881 | _T_883; // @[lsu_dccm_ctl.scala 175:152]
+  wire  _T_885 = io_lsu_pkt_d_bits_store & _T_884; // @[lsu_dccm_ctl.scala 175:97]
+  wire  _T_886 = io_lsu_pkt_d_bits_load | _T_885; // @[lsu_dccm_ctl.scala 175:70]
+  wire  _T_887 = io_lsu_pkt_d_valid & _T_886; // @[lsu_dccm_ctl.scala 175:44]
+  wire  lsu_dccm_rden_d = _T_887 & io_addr_in_dccm_d; // @[lsu_dccm_ctl.scala 175:191]
+  reg  ld_single_ecc_error_lo_r_ff; // @[lsu_dccm_ctl.scala 284:73]
+  reg  ld_single_ecc_error_hi_r_ff; // @[lsu_dccm_ctl.scala 283:73]
+  wire  _T_888 = ld_single_ecc_error_lo_r_ff | ld_single_ecc_error_hi_r_ff; // @[lsu_dccm_ctl.scala 178:63]
+  reg  lsu_double_ecc_error_r_ff; // @[lsu_dccm_ctl.scala 282:73]
+  wire  _T_889 = ~lsu_double_ecc_error_r_ff; // @[lsu_dccm_ctl.scala 178:96]
+  wire  _T_891 = lsu_dccm_rden_d | io_dma_dccm_wen; // @[lsu_dccm_ctl.scala 179:75]
+  wire  _T_892 = _T_891 | io_ld_single_ecc_error_r_ff; // @[lsu_dccm_ctl.scala 179:93]
+  wire  _T_893 = ~_T_892; // @[lsu_dccm_ctl.scala 179:57]
+  wire  _T_896 = io_stbuf_addr_any[3:2] == io_lsu_addr_d[3:2]; // @[lsu_dccm_ctl.scala 180:95]
+  wire  _T_899 = io_stbuf_addr_any[3:2] == io_end_addr_d[3:2]; // @[lsu_dccm_ctl.scala 181:76]
+  wire  _T_900 = _T_896 | _T_899; // @[lsu_dccm_ctl.scala 180:171]
+  wire  _T_901 = ~_T_900; // @[lsu_dccm_ctl.scala 180:24]
+  wire  _T_902 = lsu_dccm_rden_d & _T_901; // @[lsu_dccm_ctl.scala 180:22]
+  wire  _T_903 = _T_893 | _T_902; // @[lsu_dccm_ctl.scala 179:124]
+  wire  _T_905 = io_dma_dccm_wen | io_lsu_stbuf_commit_any; // @[lsu_dccm_ctl.scala 185:41]
+  reg [15:0] ld_sec_addr_lo_r_ff; // @[Reg.scala 27:20]
+  reg [15:0] ld_sec_addr_hi_r_ff; // @[Reg.scala 27:20]
+  wire [15:0] _T_912 = ld_single_ecc_error_lo_r_ff ? ld_sec_addr_lo_r_ff : ld_sec_addr_hi_r_ff; // @[lsu_dccm_ctl.scala 189:8]
+  wire [15:0] _T_916 = io_dma_dccm_wen ? io_lsu_addr_d[15:0] : io_stbuf_addr_any; // @[lsu_dccm_ctl.scala 190:8]
+  wire [15:0] _T_922 = ld_single_ecc_error_hi_r_ff ? ld_sec_addr_hi_r_ff : ld_sec_addr_lo_r_ff; // @[lsu_dccm_ctl.scala 193:8]
+  wire [15:0] _T_926 = io_dma_dccm_wen ? io_end_addr_d : io_stbuf_addr_any; // @[lsu_dccm_ctl.scala 194:8]
+  wire [38:0] _T_934 = {io_sec_data_ecc_lo_r_ff,io_sec_data_lo_r_ff}; // @[Cat.scala 29:58]
+  wire [38:0] _T_937 = {io_sec_data_ecc_hi_r_ff,io_sec_data_hi_r_ff}; // @[Cat.scala 29:58]
+  wire [38:0] _T_938 = ld_single_ecc_error_lo_r_ff ? _T_934 : _T_937; // @[lsu_dccm_ctl.scala 200:8]
+  wire [38:0] _T_942 = {io_dma_dccm_wdata_ecc_lo,io_dma_dccm_wdata_lo}; // @[Cat.scala 29:58]
+  wire [38:0] _T_945 = {io_stbuf_ecc_any,io_stbuf_data_any}; // @[Cat.scala 29:58]
+  wire [38:0] _T_946 = io_dma_dccm_wen ? _T_942 : _T_945; // @[lsu_dccm_ctl.scala 202:8]
+  wire [38:0] _T_956 = ld_single_ecc_error_hi_r_ff ? _T_937 : _T_934; // @[lsu_dccm_ctl.scala 206:8]
+  wire [38:0] _T_960 = {io_dma_dccm_wdata_ecc_hi,io_dma_dccm_wdata_hi}; // @[Cat.scala 29:58]
+  wire [38:0] _T_964 = io_dma_dccm_wen ? _T_960 : _T_945; // @[lsu_dccm_ctl.scala 208:8]
+  wire [3:0] _T_980 = io_lsu_pkt_r_bits_store ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
+  wire [3:0] _T_982 = io_lsu_pkt_r_bits_by ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
+  wire [3:0] _T_983 = _T_982 & 4'h1; // @[lsu_dccm_ctl.scala 216:94]
+  wire [3:0] _T_985 = io_lsu_pkt_r_bits_half ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
+  wire [3:0] _T_986 = _T_985 & 4'h3; // @[lsu_dccm_ctl.scala 217:38]
+  wire [3:0] _T_987 = _T_983 | _T_986; // @[lsu_dccm_ctl.scala 216:107]
+  wire [3:0] _T_989 = io_lsu_pkt_r_bits_word ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
+  wire [3:0] _T_991 = _T_987 | _T_989; // @[lsu_dccm_ctl.scala 217:51]
+  wire [3:0] store_byteen_r = _T_980 & _T_991; // @[lsu_dccm_ctl.scala 216:58]
+  wire [6:0] _GEN_55 = {{3'd0}, store_byteen_r}; // @[lsu_dccm_ctl.scala 222:45]
+  wire [6:0] _T_997 = _GEN_55 << io_lsu_addr_r[1:0]; // @[lsu_dccm_ctl.scala 222:45]
+  wire  _T_1000 = io_stbuf_addr_any[15:2] == io_lsu_addr_m[15:2]; // @[lsu_dccm_ctl.scala 225:67]
+  wire  _T_1003 = io_stbuf_addr_any[15:2] == io_end_addr_m[15:2]; // @[lsu_dccm_ctl.scala 226:67]
+  wire  _T_1006 = io_stbuf_addr_any[15:2] == io_lsu_addr_r[15:2]; // @[lsu_dccm_ctl.scala 228:67]
+  wire  dccm_wr_bypass_d_r_lo = _T_1006 & io_addr_in_dccm_r; // @[lsu_dccm_ctl.scala 228:101]
+  wire [63:0] _T_1012 = {32'h0,io_store_data_r}; // @[Cat.scala 29:58]
+  wire [126:0] _GEN_57 = {{63'd0}, _T_1012}; // @[lsu_dccm_ctl.scala 243:72]
+  wire [126:0] _T_1015 = _GEN_57 << _T_818; // @[lsu_dccm_ctl.scala 243:72]
+  wire [63:0] store_data_pre_r = _T_1015[63:0]; // @[lsu_dccm_ctl.scala 243:29]
+  wire [31:0] store_data_pre_hi_r = store_data_pre_r[63:32]; // @[lsu_dccm_ctl.scala 244:48]
+  wire [31:0] store_data_pre_lo_r = store_data_pre_r[31:0]; // @[lsu_dccm_ctl.scala 245:48]
+  wire [7:0] store_byteen_ext_r = {{1'd0}, _T_997}; // @[lsu_dccm_ctl.scala 222:22]
+  reg  dccm_wren_Q; // @[lsu_dccm_ctl.scala 250:69]
+  reg  dccm_wr_bypass_d_m_lo_Q; // @[lsu_dccm_ctl.scala 252:69]
+  wire  _T_1021 = dccm_wren_Q & dccm_wr_bypass_d_m_lo_Q; // @[lsu_dccm_ctl.scala 246:162]
+  reg [31:0] dccm_wr_data_Q; // @[Reg.scala 27:20]
+  wire [7:0] _T_1025 = _T_1021 ? dccm_wr_data_Q[7:0] : io_sec_data_lo_r[7:0]; // @[lsu_dccm_ctl.scala 246:148]
+  wire [7:0] _T_1026 = store_byteen_ext_r[0] ? store_data_pre_lo_r[7:0] : _T_1025; // @[lsu_dccm_ctl.scala 246:79]
+  wire [7:0] _T_1030 = {{4'd0}, _T_1026[7:4]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1032 = {_T_1026[3:0], 4'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1034 = _T_1032 & 8'hf0; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1035 = _T_1030 | _T_1034; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_58 = {{2'd0}, _T_1035[7:2]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1040 = _GEN_58 & 8'h33; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1042 = {_T_1035[5:0], 2'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1044 = _T_1042 & 8'hcc; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1045 = _T_1040 | _T_1044; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_59 = {{1'd0}, _T_1045[7:1]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1050 = _GEN_59 & 8'h55; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1052 = {_T_1045[6:0], 1'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1054 = _T_1052 & 8'haa; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1055 = _T_1050 | _T_1054; // @[Bitwise.scala 103:39]
+  wire [7:0] _T_1063 = _T_1021 ? dccm_wr_data_Q[15:8] : io_sec_data_lo_r[15:8]; // @[lsu_dccm_ctl.scala 246:148]
+  wire [7:0] _T_1064 = store_byteen_ext_r[1] ? store_data_pre_lo_r[15:8] : _T_1063; // @[lsu_dccm_ctl.scala 246:79]
+  wire [7:0] _T_1068 = {{4'd0}, _T_1064[7:4]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1070 = {_T_1064[3:0], 4'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1072 = _T_1070 & 8'hf0; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1073 = _T_1068 | _T_1072; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_60 = {{2'd0}, _T_1073[7:2]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1078 = _GEN_60 & 8'h33; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1080 = {_T_1073[5:0], 2'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1082 = _T_1080 & 8'hcc; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1083 = _T_1078 | _T_1082; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_61 = {{1'd0}, _T_1083[7:1]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1088 = _GEN_61 & 8'h55; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1090 = {_T_1083[6:0], 1'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1092 = _T_1090 & 8'haa; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1093 = _T_1088 | _T_1092; // @[Bitwise.scala 103:39]
+  wire [7:0] _T_1101 = _T_1021 ? dccm_wr_data_Q[23:16] : io_sec_data_lo_r[23:16]; // @[lsu_dccm_ctl.scala 246:148]
+  wire [7:0] _T_1102 = store_byteen_ext_r[2] ? store_data_pre_lo_r[23:16] : _T_1101; // @[lsu_dccm_ctl.scala 246:79]
+  wire [7:0] _T_1106 = {{4'd0}, _T_1102[7:4]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1108 = {_T_1102[3:0], 4'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1110 = _T_1108 & 8'hf0; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1111 = _T_1106 | _T_1110; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_62 = {{2'd0}, _T_1111[7:2]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1116 = _GEN_62 & 8'h33; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1118 = {_T_1111[5:0], 2'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1120 = _T_1118 & 8'hcc; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1121 = _T_1116 | _T_1120; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_63 = {{1'd0}, _T_1121[7:1]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1126 = _GEN_63 & 8'h55; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1128 = {_T_1121[6:0], 1'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1130 = _T_1128 & 8'haa; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1131 = _T_1126 | _T_1130; // @[Bitwise.scala 103:39]
+  wire [7:0] _T_1139 = _T_1021 ? dccm_wr_data_Q[31:24] : io_sec_data_lo_r[31:24]; // @[lsu_dccm_ctl.scala 246:148]
+  wire [7:0] _T_1140 = store_byteen_ext_r[3] ? store_data_pre_lo_r[31:24] : _T_1139; // @[lsu_dccm_ctl.scala 246:79]
+  wire [7:0] _T_1144 = {{4'd0}, _T_1140[7:4]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1146 = {_T_1140[3:0], 4'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1148 = _T_1146 & 8'hf0; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1149 = _T_1144 | _T_1148; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_64 = {{2'd0}, _T_1149[7:2]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1154 = _GEN_64 & 8'h33; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1156 = {_T_1149[5:0], 2'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1158 = _T_1156 & 8'hcc; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1159 = _T_1154 | _T_1158; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_65 = {{1'd0}, _T_1159[7:1]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1164 = _GEN_65 & 8'h55; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1166 = {_T_1159[6:0], 1'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1168 = _T_1166 & 8'haa; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1169 = _T_1164 | _T_1168; // @[Bitwise.scala 103:39]
+  wire [31:0] _T_1173 = {_T_1055,_T_1093,_T_1131,_T_1169}; // @[Cat.scala 29:58]
+  wire [31:0] _T_1177 = {{16'd0}, _T_1173[31:16]}; // @[Bitwise.scala 103:31]
+  wire [31:0] _T_1179 = {_T_1173[15:0], 16'h0}; // @[Bitwise.scala 103:65]
+  wire [31:0] _T_1181 = _T_1179 & 32'hffff0000; // @[Bitwise.scala 103:75]
+  wire [31:0] _T_1182 = _T_1177 | _T_1181; // @[Bitwise.scala 103:39]
+  wire [31:0] _GEN_66 = {{8'd0}, _T_1182[31:8]}; // @[Bitwise.scala 103:31]
+  wire [31:0] _T_1187 = _GEN_66 & 32'hff00ff; // @[Bitwise.scala 103:31]
+  wire [31:0] _T_1189 = {_T_1182[23:0], 8'h0}; // @[Bitwise.scala 103:65]
+  wire [31:0] _T_1191 = _T_1189 & 32'hff00ff00; // @[Bitwise.scala 103:75]
+  wire [31:0] _T_1192 = _T_1187 | _T_1191; // @[Bitwise.scala 103:39]
+  wire [31:0] _GEN_67 = {{4'd0}, _T_1192[31:4]}; // @[Bitwise.scala 103:31]
+  wire [31:0] _T_1197 = _GEN_67 & 32'hf0f0f0f; // @[Bitwise.scala 103:31]
+  wire [31:0] _T_1199 = {_T_1192[27:0], 4'h0}; // @[Bitwise.scala 103:65]
+  wire [31:0] _T_1201 = _T_1199 & 32'hf0f0f0f0; // @[Bitwise.scala 103:75]
+  wire [31:0] _T_1202 = _T_1197 | _T_1201; // @[Bitwise.scala 103:39]
+  wire [31:0] _GEN_68 = {{2'd0}, _T_1202[31:2]}; // @[Bitwise.scala 103:31]
+  wire [31:0] _T_1207 = _GEN_68 & 32'h33333333; // @[Bitwise.scala 103:31]
+  wire [31:0] _T_1209 = {_T_1202[29:0], 2'h0}; // @[Bitwise.scala 103:65]
+  wire [31:0] _T_1211 = _T_1209 & 32'hcccccccc; // @[Bitwise.scala 103:75]
+  wire [31:0] _T_1212 = _T_1207 | _T_1211; // @[Bitwise.scala 103:39]
+  wire [31:0] _GEN_69 = {{1'd0}, _T_1212[31:1]}; // @[Bitwise.scala 103:31]
+  wire [31:0] _T_1217 = _GEN_69 & 32'h55555555; // @[Bitwise.scala 103:31]
+  wire [31:0] _T_1219 = {_T_1212[30:0], 1'h0}; // @[Bitwise.scala 103:65]
+  wire [31:0] _T_1221 = _T_1219 & 32'haaaaaaaa; // @[Bitwise.scala 103:75]
+  reg  dccm_wr_bypass_d_m_hi_Q; // @[lsu_dccm_ctl.scala 253:69]
+  wire  _T_1226 = dccm_wren_Q & dccm_wr_bypass_d_m_hi_Q; // @[lsu_dccm_ctl.scala 247:162]
+  wire [7:0] _T_1230 = _T_1226 ? dccm_wr_data_Q[7:0] : io_sec_data_hi_r[7:0]; // @[lsu_dccm_ctl.scala 247:148]
+  wire [7:0] _T_1231 = store_byteen_ext_r[4] ? store_data_pre_hi_r[7:0] : _T_1230; // @[lsu_dccm_ctl.scala 247:79]
+  wire [7:0] _T_1235 = {{4'd0}, _T_1231[7:4]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1237 = {_T_1231[3:0], 4'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1239 = _T_1237 & 8'hf0; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1240 = _T_1235 | _T_1239; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_70 = {{2'd0}, _T_1240[7:2]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1245 = _GEN_70 & 8'h33; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1247 = {_T_1240[5:0], 2'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1249 = _T_1247 & 8'hcc; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1250 = _T_1245 | _T_1249; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_71 = {{1'd0}, _T_1250[7:1]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1255 = _GEN_71 & 8'h55; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1257 = {_T_1250[6:0], 1'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1259 = _T_1257 & 8'haa; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1260 = _T_1255 | _T_1259; // @[Bitwise.scala 103:39]
+  wire [7:0] _T_1268 = _T_1226 ? dccm_wr_data_Q[15:8] : io_sec_data_hi_r[15:8]; // @[lsu_dccm_ctl.scala 247:148]
+  wire [7:0] _T_1269 = store_byteen_ext_r[5] ? store_data_pre_hi_r[15:8] : _T_1268; // @[lsu_dccm_ctl.scala 247:79]
+  wire [7:0] _T_1273 = {{4'd0}, _T_1269[7:4]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1275 = {_T_1269[3:0], 4'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1277 = _T_1275 & 8'hf0; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1278 = _T_1273 | _T_1277; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_72 = {{2'd0}, _T_1278[7:2]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1283 = _GEN_72 & 8'h33; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1285 = {_T_1278[5:0], 2'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1287 = _T_1285 & 8'hcc; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1288 = _T_1283 | _T_1287; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_73 = {{1'd0}, _T_1288[7:1]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1293 = _GEN_73 & 8'h55; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1295 = {_T_1288[6:0], 1'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1297 = _T_1295 & 8'haa; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1298 = _T_1293 | _T_1297; // @[Bitwise.scala 103:39]
+  wire [7:0] _T_1306 = _T_1226 ? dccm_wr_data_Q[23:16] : io_sec_data_hi_r[23:16]; // @[lsu_dccm_ctl.scala 247:148]
+  wire [7:0] _T_1307 = store_byteen_ext_r[6] ? store_data_pre_hi_r[23:16] : _T_1306; // @[lsu_dccm_ctl.scala 247:79]
+  wire [7:0] _T_1311 = {{4'd0}, _T_1307[7:4]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1313 = {_T_1307[3:0], 4'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1315 = _T_1313 & 8'hf0; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1316 = _T_1311 | _T_1315; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_74 = {{2'd0}, _T_1316[7:2]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1321 = _GEN_74 & 8'h33; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1323 = {_T_1316[5:0], 2'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1325 = _T_1323 & 8'hcc; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1326 = _T_1321 | _T_1325; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_75 = {{1'd0}, _T_1326[7:1]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1331 = _GEN_75 & 8'h55; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1333 = {_T_1326[6:0], 1'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1335 = _T_1333 & 8'haa; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1336 = _T_1331 | _T_1335; // @[Bitwise.scala 103:39]
+  wire [7:0] _T_1344 = _T_1226 ? dccm_wr_data_Q[31:24] : io_sec_data_hi_r[31:24]; // @[lsu_dccm_ctl.scala 247:148]
+  wire [7:0] _T_1345 = store_byteen_ext_r[7] ? store_data_pre_hi_r[31:24] : _T_1344; // @[lsu_dccm_ctl.scala 247:79]
+  wire [7:0] _T_1349 = {{4'd0}, _T_1345[7:4]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1351 = {_T_1345[3:0], 4'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1353 = _T_1351 & 8'hf0; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1354 = _T_1349 | _T_1353; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_76 = {{2'd0}, _T_1354[7:2]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1359 = _GEN_76 & 8'h33; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1361 = {_T_1354[5:0], 2'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1363 = _T_1361 & 8'hcc; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1364 = _T_1359 | _T_1363; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_77 = {{1'd0}, _T_1364[7:1]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1369 = _GEN_77 & 8'h55; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1371 = {_T_1364[6:0], 1'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1373 = _T_1371 & 8'haa; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1374 = _T_1369 | _T_1373; // @[Bitwise.scala 103:39]
+  wire [31:0] _T_1378 = {_T_1260,_T_1298,_T_1336,_T_1374}; // @[Cat.scala 29:58]
+  wire [31:0] _T_1382 = {{16'd0}, _T_1378[31:16]}; // @[Bitwise.scala 103:31]
+  wire [31:0] _T_1384 = {_T_1378[15:0], 16'h0}; // @[Bitwise.scala 103:65]
+  wire [31:0] _T_1386 = _T_1384 & 32'hffff0000; // @[Bitwise.scala 103:75]
+  wire [31:0] _T_1387 = _T_1382 | _T_1386; // @[Bitwise.scala 103:39]
+  wire [31:0] _GEN_78 = {{8'd0}, _T_1387[31:8]}; // @[Bitwise.scala 103:31]
+  wire [31:0] _T_1392 = _GEN_78 & 32'hff00ff; // @[Bitwise.scala 103:31]
+  wire [31:0] _T_1394 = {_T_1387[23:0], 8'h0}; // @[Bitwise.scala 103:65]
+  wire [31:0] _T_1396 = _T_1394 & 32'hff00ff00; // @[Bitwise.scala 103:75]
+  wire [31:0] _T_1397 = _T_1392 | _T_1396; // @[Bitwise.scala 103:39]
+  wire [31:0] _GEN_79 = {{4'd0}, _T_1397[31:4]}; // @[Bitwise.scala 103:31]
+  wire [31:0] _T_1402 = _GEN_79 & 32'hf0f0f0f; // @[Bitwise.scala 103:31]
+  wire [31:0] _T_1404 = {_T_1397[27:0], 4'h0}; // @[Bitwise.scala 103:65]
+  wire [31:0] _T_1406 = _T_1404 & 32'hf0f0f0f0; // @[Bitwise.scala 103:75]
+  wire [31:0] _T_1407 = _T_1402 | _T_1406; // @[Bitwise.scala 103:39]
+  wire [31:0] _GEN_80 = {{2'd0}, _T_1407[31:2]}; // @[Bitwise.scala 103:31]
+  wire [31:0] _T_1412 = _GEN_80 & 32'h33333333; // @[Bitwise.scala 103:31]
+  wire [31:0] _T_1414 = {_T_1407[29:0], 2'h0}; // @[Bitwise.scala 103:65]
+  wire [31:0] _T_1416 = _T_1414 & 32'hcccccccc; // @[Bitwise.scala 103:75]
+  wire [31:0] _T_1417 = _T_1412 | _T_1416; // @[Bitwise.scala 103:39]
+  wire [31:0] _GEN_81 = {{1'd0}, _T_1417[31:1]}; // @[Bitwise.scala 103:31]
+  wire [31:0] _T_1422 = _GEN_81 & 32'h55555555; // @[Bitwise.scala 103:31]
+  wire [31:0] _T_1424 = {_T_1417[30:0], 1'h0}; // @[Bitwise.scala 103:65]
+  wire [31:0] _T_1426 = _T_1424 & 32'haaaaaaaa; // @[Bitwise.scala 103:75]
+  wire  _T_1431 = io_lsu_stbuf_commit_any & dccm_wr_bypass_d_r_lo; // @[lsu_dccm_ctl.scala 248:174]
+  wire [7:0] _T_1439 = _T_1431 ? io_stbuf_data_any[7:0] : _T_1025; // @[lsu_dccm_ctl.scala 248:148]
+  wire [7:0] _T_1440 = store_byteen_ext_r[0] ? store_data_pre_lo_r[7:0] : _T_1439; // @[lsu_dccm_ctl.scala 248:79]
+  wire [7:0] _T_1444 = {{4'd0}, _T_1440[7:4]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1446 = {_T_1440[3:0], 4'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1448 = _T_1446 & 8'hf0; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1449 = _T_1444 | _T_1448; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_82 = {{2'd0}, _T_1449[7:2]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1454 = _GEN_82 & 8'h33; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1456 = {_T_1449[5:0], 2'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1458 = _T_1456 & 8'hcc; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1459 = _T_1454 | _T_1458; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_83 = {{1'd0}, _T_1459[7:1]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1464 = _GEN_83 & 8'h55; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1466 = {_T_1459[6:0], 1'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1468 = _T_1466 & 8'haa; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1469 = _T_1464 | _T_1468; // @[Bitwise.scala 103:39]
+  wire [7:0] _T_1481 = _T_1431 ? io_stbuf_data_any[15:8] : _T_1063; // @[lsu_dccm_ctl.scala 248:148]
+  wire [7:0] _T_1482 = store_byteen_ext_r[1] ? store_data_pre_lo_r[15:8] : _T_1481; // @[lsu_dccm_ctl.scala 248:79]
+  wire [7:0] _T_1486 = {{4'd0}, _T_1482[7:4]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1488 = {_T_1482[3:0], 4'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1490 = _T_1488 & 8'hf0; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1491 = _T_1486 | _T_1490; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_84 = {{2'd0}, _T_1491[7:2]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1496 = _GEN_84 & 8'h33; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1498 = {_T_1491[5:0], 2'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1500 = _T_1498 & 8'hcc; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1501 = _T_1496 | _T_1500; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_85 = {{1'd0}, _T_1501[7:1]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1506 = _GEN_85 & 8'h55; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1508 = {_T_1501[6:0], 1'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1510 = _T_1508 & 8'haa; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1511 = _T_1506 | _T_1510; // @[Bitwise.scala 103:39]
+  wire [7:0] _T_1523 = _T_1431 ? io_stbuf_data_any[23:16] : _T_1101; // @[lsu_dccm_ctl.scala 248:148]
+  wire [7:0] _T_1524 = store_byteen_ext_r[2] ? store_data_pre_lo_r[23:16] : _T_1523; // @[lsu_dccm_ctl.scala 248:79]
+  wire [7:0] _T_1528 = {{4'd0}, _T_1524[7:4]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1530 = {_T_1524[3:0], 4'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1532 = _T_1530 & 8'hf0; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1533 = _T_1528 | _T_1532; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_86 = {{2'd0}, _T_1533[7:2]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1538 = _GEN_86 & 8'h33; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1540 = {_T_1533[5:0], 2'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1542 = _T_1540 & 8'hcc; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1543 = _T_1538 | _T_1542; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_87 = {{1'd0}, _T_1543[7:1]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1548 = _GEN_87 & 8'h55; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1550 = {_T_1543[6:0], 1'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1552 = _T_1550 & 8'haa; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1553 = _T_1548 | _T_1552; // @[Bitwise.scala 103:39]
+  wire [7:0] _T_1565 = _T_1431 ? io_stbuf_data_any[31:24] : _T_1139; // @[lsu_dccm_ctl.scala 248:148]
+  wire [7:0] _T_1566 = store_byteen_ext_r[3] ? store_data_pre_lo_r[31:24] : _T_1565; // @[lsu_dccm_ctl.scala 248:79]
+  wire [7:0] _T_1570 = {{4'd0}, _T_1566[7:4]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1572 = {_T_1566[3:0], 4'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1574 = _T_1572 & 8'hf0; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1575 = _T_1570 | _T_1574; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_88 = {{2'd0}, _T_1575[7:2]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1580 = _GEN_88 & 8'h33; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1582 = {_T_1575[5:0], 2'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1584 = _T_1582 & 8'hcc; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1585 = _T_1580 | _T_1584; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_89 = {{1'd0}, _T_1585[7:1]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1590 = _GEN_89 & 8'h55; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1592 = {_T_1585[6:0], 1'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1594 = _T_1592 & 8'haa; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1595 = _T_1590 | _T_1594; // @[Bitwise.scala 103:39]
+  wire [31:0] _T_1599 = {_T_1469,_T_1511,_T_1553,_T_1595}; // @[Cat.scala 29:58]
+  wire [31:0] _T_1603 = {{16'd0}, _T_1599[31:16]}; // @[Bitwise.scala 103:31]
+  wire [31:0] _T_1605 = {_T_1599[15:0], 16'h0}; // @[Bitwise.scala 103:65]
+  wire [31:0] _T_1607 = _T_1605 & 32'hffff0000; // @[Bitwise.scala 103:75]
+  wire [31:0] _T_1608 = _T_1603 | _T_1607; // @[Bitwise.scala 103:39]
+  wire [31:0] _GEN_90 = {{8'd0}, _T_1608[31:8]}; // @[Bitwise.scala 103:31]
+  wire [31:0] _T_1613 = _GEN_90 & 32'hff00ff; // @[Bitwise.scala 103:31]
+  wire [31:0] _T_1615 = {_T_1608[23:0], 8'h0}; // @[Bitwise.scala 103:65]
+  wire [31:0] _T_1617 = _T_1615 & 32'hff00ff00; // @[Bitwise.scala 103:75]
+  wire [31:0] _T_1618 = _T_1613 | _T_1617; // @[Bitwise.scala 103:39]
+  wire [31:0] _GEN_91 = {{4'd0}, _T_1618[31:4]}; // @[Bitwise.scala 103:31]
+  wire [31:0] _T_1623 = _GEN_91 & 32'hf0f0f0f; // @[Bitwise.scala 103:31]
+  wire [31:0] _T_1625 = {_T_1618[27:0], 4'h0}; // @[Bitwise.scala 103:65]
+  wire [31:0] _T_1627 = _T_1625 & 32'hf0f0f0f0; // @[Bitwise.scala 103:75]
+  wire [31:0] _T_1628 = _T_1623 | _T_1627; // @[Bitwise.scala 103:39]
+  wire [31:0] _GEN_92 = {{2'd0}, _T_1628[31:2]}; // @[Bitwise.scala 103:31]
+  wire [31:0] _T_1633 = _GEN_92 & 32'h33333333; // @[Bitwise.scala 103:31]
+  wire [31:0] _T_1635 = {_T_1628[29:0], 2'h0}; // @[Bitwise.scala 103:65]
+  wire [31:0] _T_1637 = _T_1635 & 32'hcccccccc; // @[Bitwise.scala 103:75]
+  wire [31:0] _T_1638 = _T_1633 | _T_1637; // @[Bitwise.scala 103:39]
+  wire [31:0] _GEN_93 = {{1'd0}, _T_1638[31:1]}; // @[Bitwise.scala 103:31]
+  wire [31:0] _T_1643 = _GEN_93 & 32'h55555555; // @[Bitwise.scala 103:31]
+  wire [31:0] _T_1645 = {_T_1638[30:0], 1'h0}; // @[Bitwise.scala 103:65]
+  wire [31:0] _T_1647 = _T_1645 & 32'haaaaaaaa; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1660 = _T_1431 ? io_stbuf_data_any[7:0] : _T_1230; // @[lsu_dccm_ctl.scala 249:148]
+  wire [7:0] _T_1661 = store_byteen_ext_r[4] ? store_data_pre_hi_r[7:0] : _T_1660; // @[lsu_dccm_ctl.scala 249:79]
+  wire [7:0] _T_1665 = {{4'd0}, _T_1661[7:4]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1667 = {_T_1661[3:0], 4'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1669 = _T_1667 & 8'hf0; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1670 = _T_1665 | _T_1669; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_94 = {{2'd0}, _T_1670[7:2]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1675 = _GEN_94 & 8'h33; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1677 = {_T_1670[5:0], 2'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1679 = _T_1677 & 8'hcc; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1680 = _T_1675 | _T_1679; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_95 = {{1'd0}, _T_1680[7:1]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1685 = _GEN_95 & 8'h55; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1687 = {_T_1680[6:0], 1'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1689 = _T_1687 & 8'haa; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1690 = _T_1685 | _T_1689; // @[Bitwise.scala 103:39]
+  wire [7:0] _T_1702 = _T_1431 ? io_stbuf_data_any[15:8] : _T_1268; // @[lsu_dccm_ctl.scala 249:148]
+  wire [7:0] _T_1703 = store_byteen_ext_r[5] ? store_data_pre_hi_r[15:8] : _T_1702; // @[lsu_dccm_ctl.scala 249:79]
+  wire [7:0] _T_1707 = {{4'd0}, _T_1703[7:4]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1709 = {_T_1703[3:0], 4'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1711 = _T_1709 & 8'hf0; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1712 = _T_1707 | _T_1711; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_96 = {{2'd0}, _T_1712[7:2]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1717 = _GEN_96 & 8'h33; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1719 = {_T_1712[5:0], 2'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1721 = _T_1719 & 8'hcc; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1722 = _T_1717 | _T_1721; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_97 = {{1'd0}, _T_1722[7:1]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1727 = _GEN_97 & 8'h55; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1729 = {_T_1722[6:0], 1'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1731 = _T_1729 & 8'haa; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1732 = _T_1727 | _T_1731; // @[Bitwise.scala 103:39]
+  wire [7:0] _T_1744 = _T_1431 ? io_stbuf_data_any[23:16] : _T_1306; // @[lsu_dccm_ctl.scala 249:148]
+  wire [7:0] _T_1745 = store_byteen_ext_r[6] ? store_data_pre_hi_r[23:16] : _T_1744; // @[lsu_dccm_ctl.scala 249:79]
+  wire [7:0] _T_1749 = {{4'd0}, _T_1745[7:4]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1751 = {_T_1745[3:0], 4'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1753 = _T_1751 & 8'hf0; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1754 = _T_1749 | _T_1753; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_98 = {{2'd0}, _T_1754[7:2]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1759 = _GEN_98 & 8'h33; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1761 = {_T_1754[5:0], 2'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1763 = _T_1761 & 8'hcc; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1764 = _T_1759 | _T_1763; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_99 = {{1'd0}, _T_1764[7:1]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1769 = _GEN_99 & 8'h55; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1771 = {_T_1764[6:0], 1'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1773 = _T_1771 & 8'haa; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1774 = _T_1769 | _T_1773; // @[Bitwise.scala 103:39]
+  wire [7:0] _T_1786 = _T_1431 ? io_stbuf_data_any[31:24] : _T_1344; // @[lsu_dccm_ctl.scala 249:148]
+  wire [7:0] _T_1787 = store_byteen_ext_r[7] ? store_data_pre_hi_r[31:24] : _T_1786; // @[lsu_dccm_ctl.scala 249:79]
+  wire [7:0] _T_1791 = {{4'd0}, _T_1787[7:4]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1793 = {_T_1787[3:0], 4'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1795 = _T_1793 & 8'hf0; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1796 = _T_1791 | _T_1795; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_100 = {{2'd0}, _T_1796[7:2]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1801 = _GEN_100 & 8'h33; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1803 = {_T_1796[5:0], 2'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1805 = _T_1803 & 8'hcc; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1806 = _T_1801 | _T_1805; // @[Bitwise.scala 103:39]
+  wire [7:0] _GEN_101 = {{1'd0}, _T_1806[7:1]}; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1811 = _GEN_101 & 8'h55; // @[Bitwise.scala 103:31]
+  wire [7:0] _T_1813 = {_T_1806[6:0], 1'h0}; // @[Bitwise.scala 103:65]
+  wire [7:0] _T_1815 = _T_1813 & 8'haa; // @[Bitwise.scala 103:75]
+  wire [7:0] _T_1816 = _T_1811 | _T_1815; // @[Bitwise.scala 103:39]
+  wire [31:0] _T_1820 = {_T_1690,_T_1732,_T_1774,_T_1816}; // @[Cat.scala 29:58]
+  wire [31:0] _T_1824 = {{16'd0}, _T_1820[31:16]}; // @[Bitwise.scala 103:31]
+  wire [31:0] _T_1826 = {_T_1820[15:0], 16'h0}; // @[Bitwise.scala 103:65]
+  wire [31:0] _T_1828 = _T_1826 & 32'hffff0000; // @[Bitwise.scala 103:75]
+  wire [31:0] _T_1829 = _T_1824 | _T_1828; // @[Bitwise.scala 103:39]
+  wire [31:0] _GEN_102 = {{8'd0}, _T_1829[31:8]}; // @[Bitwise.scala 103:31]
+  wire [31:0] _T_1834 = _GEN_102 & 32'hff00ff; // @[Bitwise.scala 103:31]
+  wire [31:0] _T_1836 = {_T_1829[23:0], 8'h0}; // @[Bitwise.scala 103:65]
+  wire [31:0] _T_1838 = _T_1836 & 32'hff00ff00; // @[Bitwise.scala 103:75]
+  wire [31:0] _T_1839 = _T_1834 | _T_1838; // @[Bitwise.scala 103:39]
+  wire [31:0] _GEN_103 = {{4'd0}, _T_1839[31:4]}; // @[Bitwise.scala 103:31]
+  wire [31:0] _T_1844 = _GEN_103 & 32'hf0f0f0f; // @[Bitwise.scala 103:31]
+  wire [31:0] _T_1846 = {_T_1839[27:0], 4'h0}; // @[Bitwise.scala 103:65]
+  wire [31:0] _T_1848 = _T_1846 & 32'hf0f0f0f0; // @[Bitwise.scala 103:75]
+  wire [31:0] _T_1849 = _T_1844 | _T_1848; // @[Bitwise.scala 103:39]
+  wire [31:0] _GEN_104 = {{2'd0}, _T_1849[31:2]}; // @[Bitwise.scala 103:31]
+  wire [31:0] _T_1854 = _GEN_104 & 32'h33333333; // @[Bitwise.scala 103:31]
+  wire [31:0] _T_1856 = {_T_1849[29:0], 2'h0}; // @[Bitwise.scala 103:65]
+  wire [31:0] _T_1858 = _T_1856 & 32'hcccccccc; // @[Bitwise.scala 103:75]
+  wire [31:0] _T_1859 = _T_1854 | _T_1858; // @[Bitwise.scala 103:39]
+  wire [31:0] _GEN_105 = {{1'd0}, _T_1859[31:1]}; // @[Bitwise.scala 103:31]
+  wire [31:0] _T_1864 = _GEN_105 & 32'h55555555; // @[Bitwise.scala 103:31]
+  wire [31:0] _T_1866 = {_T_1859[30:0], 1'h0}; // @[Bitwise.scala 103:65]
+  wire [31:0] _T_1868 = _T_1866 & 32'haaaaaaaa; // @[Bitwise.scala 103:75]
+  wire  _T_1871 = io_lsu_stbuf_commit_any | io_clk_override; // @[lsu_dccm_ctl.scala 251:82]
+  reg [31:0] _T_1877; // @[lsu_dccm_ctl.scala 254:72]
+  wire  _T_1882 = io_lsu_pkt_r_valid & io_lsu_pkt_r_bits_store; // @[lsu_dccm_ctl.scala 272:58]
+  wire  _T_1883 = _T_1882 & io_addr_in_pic_r; // @[lsu_dccm_ctl.scala 272:84]
+  wire  _T_1884 = _T_1883 & io_lsu_commit_r; // @[lsu_dccm_ctl.scala 272:103]
+  wire  _T_1886 = io_lsu_pkt_d_valid & io_lsu_pkt_d_bits_load; // @[lsu_dccm_ctl.scala 273:58]
+  wire  _T_1888 = io_lsu_pkt_d_valid & io_lsu_pkt_d_bits_store; // @[lsu_dccm_ctl.scala 274:58]
+  wire [31:0] _T_1892 = {17'h0,io_lsu_addr_d[14:0]}; // @[Cat.scala 29:58]
+  wire [14:0] _T_1898 = io_dma_pic_wen ? io_dma_dccm_ctl_dma_mem_addr[14:0] : io_lsu_addr_r[14:0]; // @[lsu_dccm_ctl.scala 276:93]
+  wire [31:0] _T_1899 = {17'h0,_T_1898}; // @[Cat.scala 29:58]
+  reg  _T_1906; // @[lsu_dccm_ctl.scala 280:61]
+  reg  _T_1907; // @[lsu_dccm_ctl.scala 281:61]
+  wire  _T_1912 = io_ld_single_ecc_error_r | io_clk_override; // @[lsu_dccm_ctl.scala 285:90]
+  rvclkhdr rvclkhdr ( // @[lib.scala 390:23]
+    .io_clk(rvclkhdr_io_clk),
+    .io_en(rvclkhdr_io_en)
+  );
+  rvclkhdr rvclkhdr_1 ( // @[lib.scala 390:23]
+    .io_clk(rvclkhdr_1_io_clk),
+    .io_en(rvclkhdr_1_io_en)
+  );
+  rvclkhdr rvclkhdr_2 ( // @[lib.scala 390:23]
+    .io_clk(rvclkhdr_2_io_clk),
+    .io_en(rvclkhdr_2_io_en)
+  );
+  rvclkhdr rvclkhdr_3 ( // @[lib.scala 390:23]
+    .io_clk(rvclkhdr_3_io_clk),
+    .io_en(rvclkhdr_3_io_en)
+  );
+  rvclkhdr rvclkhdr_4 ( // @[lib.scala 390:23]
+    .io_clk(rvclkhdr_4_io_clk),
+    .io_en(rvclkhdr_4_io_en)
+  );
+  rvclkhdr rvclkhdr_5 ( // @[lib.scala 390:23]
+    .io_clk(rvclkhdr_5_io_clk),
+    .io_en(rvclkhdr_5_io_en)
+  );
+  rvclkhdr rvclkhdr_6 ( // @[lib.scala 390:23]
+    .io_clk(rvclkhdr_6_io_clk),
+    .io_en(rvclkhdr_6_io_en)
+  );
+  rvclkhdr rvclkhdr_7 ( // @[lib.scala 390:23]
+    .io_clk(rvclkhdr_7_io_clk),
+    .io_en(rvclkhdr_7_io_en)
+  );
+  rvclkhdr rvclkhdr_8 ( // @[lib.scala 390:23]
+    .io_clk(rvclkhdr_8_io_clk),
+    .io_en(rvclkhdr_8_io_en)
+  );
+  rvclkhdr rvclkhdr_9 ( // @[lib.scala 390:23]
+    .io_clk(rvclkhdr_9_io_clk),
+    .io_en(rvclkhdr_9_io_en)
+  );
+  assign io_dccm_rdata_hi_r = _T_14; // @[lsu_dccm_ctl.scala 129:27]
+  assign io_dccm_rdata_lo_r = _T_18; // @[lsu_dccm_ctl.scala 130:27]
+  assign io_dccm_data_ecc_hi_r = _T_22; // @[lsu_dccm_ctl.scala 131:27]
+  assign io_dccm_data_ecc_lo_r = _T_26; // @[lsu_dccm_ctl.scala 132:27]
+  assign io_lsu_ld_data_r = _T_819[31:0]; // @[lsu_dccm_ctl.scala 140:27]
+  assign io_lsu_ld_data_corr_r = _T_822[31:0]; // @[lsu_dccm_ctl.scala 141:27]
+  assign io_dccm_rdata_hi_m = io_dccm_rd_data_hi[31:0]; // @[lsu_dccm_ctl.scala 268:27]
+  assign io_dccm_rdata_lo_m = io_dccm_rd_data_lo[31:0]; // @[lsu_dccm_ctl.scala 267:27]
+  assign io_dccm_data_ecc_hi_m = io_dccm_rd_data_hi[38:32]; // @[lsu_dccm_ctl.scala 270:27]
+  assign io_dccm_data_ecc_lo_m = io_dccm_rd_data_lo[38:32]; // @[lsu_dccm_ctl.scala 269:27]
+  assign io_lsu_ld_data_m = 32'h0; // @[lsu_dccm_ctl.scala 121:20]
+  assign io_store_data_hi_r = _T_1422 | _T_1426; // @[lsu_dccm_ctl.scala 247:29]
+  assign io_store_data_lo_r = _T_1217 | _T_1221; // @[lsu_dccm_ctl.scala 246:29]
+  assign io_store_datafn_hi_r = _T_1864 | _T_1868; // @[lsu_dccm_ctl.scala 249:29]
+  assign io_store_datafn_lo_r = _T_1643 | _T_1647; // @[lsu_dccm_ctl.scala 248:29]
+  assign io_store_data_r = _T_1877; // @[lsu_dccm_ctl.scala 254:29]
+  assign io_ld_single_ecc_error_r = _T_871 & _T_872; // @[lsu_dccm_ctl.scala 171:34]
+  assign io_ld_single_ecc_error_r_ff = _T_888 & _T_889; // @[lsu_dccm_ctl.scala 178:31]
+  assign io_picm_mask_data_m = picm_rd_data_m[31:0]; // @[lsu_dccm_ctl.scala 277:27]
+  assign io_lsu_stbuf_commit_any = io_stbuf_reqvld_any & _T_903; // @[lsu_dccm_ctl.scala 179:31]
+  assign io_lsu_dccm_rden_m = _T_1906; // @[lsu_dccm_ctl.scala 280:24]
+  assign io_lsu_dccm_rden_r = _T_1907; // @[lsu_dccm_ctl.scala 281:24]
+  assign io_dma_dccm_ctl_dccm_dma_rvalid = _T & io_lsu_pkt_r_bits_dma; // @[lsu_dccm_ctl.scala 124:40]
+  assign io_dma_dccm_ctl_dccm_dma_ecc_error = io_lsu_double_ecc_error_r; // @[lsu_dccm_ctl.scala 125:40]
+  assign io_dma_dccm_ctl_dccm_dma_rtag = _T_42; // @[lsu_dccm_ctl.scala 137:40]
+  assign io_dma_dccm_ctl_dccm_dma_rdata = io_ldst_dual_r ? lsu_rdata_corr_r : _T_4; // @[lsu_dccm_ctl.scala 126:40]
+  assign io_dccm_wren = _T_905 | io_ld_single_ecc_error_r_ff; // @[lsu_dccm_ctl.scala 185:22]
+  assign io_dccm_rden = lsu_dccm_rden_d & io_addr_in_dccm_d; // @[lsu_dccm_ctl.scala 186:22]
+  assign io_dccm_wr_addr_lo = io_ld_single_ecc_error_r_ff ? _T_912 : _T_916; // @[lsu_dccm_ctl.scala 188:22]
+  assign io_dccm_wr_addr_hi = io_ld_single_ecc_error_r_ff ? _T_922 : _T_926; // @[lsu_dccm_ctl.scala 192:22]
+  assign io_dccm_rd_addr_lo = io_lsu_addr_d[15:0]; // @[lsu_dccm_ctl.scala 196:22]
+  assign io_dccm_rd_addr_hi = io_end_addr_d; // @[lsu_dccm_ctl.scala 197:22]
+  assign io_dccm_wr_data_lo = io_ld_single_ecc_error_r_ff ? _T_938 : _T_946; // @[lsu_dccm_ctl.scala 199:22]
+  assign io_dccm_wr_data_hi = io_ld_single_ecc_error_r_ff ? _T_956 : _T_964; // @[lsu_dccm_ctl.scala 205:22]
+  assign io_lsu_pic_picm_wren = _T_1884 | io_dma_pic_wen; // @[lsu_dccm_ctl.scala 272:35]
+  assign io_lsu_pic_picm_rden = _T_1886 & io_addr_in_pic_d; // @[lsu_dccm_ctl.scala 273:35]
+  assign io_lsu_pic_picm_mken = _T_1888 & io_addr_in_pic_d; // @[lsu_dccm_ctl.scala 274:35]
+  assign io_lsu_pic_picm_rdaddr = 32'hf00c0000 | _T_1892; // @[lsu_dccm_ctl.scala 275:35]
+  assign io_lsu_pic_picm_wraddr = 32'hf00c0000 | _T_1899; // @[lsu_dccm_ctl.scala 276:35]
+  assign io_lsu_pic_picm_wr_data = io_dma_pic_wen ? io_dma_dccm_ctl_dma_mem_wdata[31:0] : io_store_datafn_lo_r; // @[lsu_dccm_ctl.scala 278:35]
+  assign rvclkhdr_io_clk = clock; // @[lib.scala 392:18]
+  assign rvclkhdr_io_en = _T_10 | io_clk_override; // @[lib.scala 393:17]
+  assign rvclkhdr_1_io_clk = clock; // @[lib.scala 392:18]
+  assign rvclkhdr_1_io_en = io_lsu_dccm_rden_m | io_clk_override; // @[lib.scala 393:17]
+  assign rvclkhdr_2_io_clk = clock; // @[lib.scala 392:18]
+  assign rvclkhdr_2_io_en = io_lsu_dccm_rden_m | io_clk_override; // @[lib.scala 393:17]
+  assign rvclkhdr_3_io_clk = clock; // @[lib.scala 392:18]
+  assign rvclkhdr_3_io_en = io_lsu_dccm_rden_m | io_clk_override; // @[lib.scala 393:17]
+  assign rvclkhdr_4_io_clk = clock; // @[lib.scala 392:18]
+  assign rvclkhdr_4_io_en = _T_8 | io_clk_override; // @[lib.scala 393:17]
+  assign rvclkhdr_5_io_clk = clock; // @[lib.scala 392:18]
+  assign rvclkhdr_5_io_en = _T_8 | io_clk_override; // @[lib.scala 393:17]
+  assign rvclkhdr_6_io_clk = clock; // @[lib.scala 392:18]
+  assign rvclkhdr_6_io_en = io_addr_in_pic_m | io_clk_override; // @[lib.scala 393:17]
+  assign rvclkhdr_7_io_clk = clock; // @[lib.scala 392:18]
+  assign rvclkhdr_7_io_en = io_lsu_stbuf_commit_any | io_clk_override; // @[lib.scala 393:17]
+  assign rvclkhdr_8_io_clk = clock; // @[lib.scala 392:18]
+  assign rvclkhdr_8_io_en = io_ld_single_ecc_error_r | io_clk_override; // @[lib.scala 393:17]
+  assign rvclkhdr_9_io_clk = clock; // @[lib.scala 392:18]
+  assign rvclkhdr_9_io_en = io_ld_single_ecc_error_r | io_clk_override; // @[lib.scala 393:17]
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+  integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+  `ifdef RANDOMIZE
+    `ifdef INIT_RANDOM
+      `INIT_RANDOM
+    `endif
+    `ifndef VERILATOR
+      `ifdef RANDOMIZE_DELAY
+        #`RANDOMIZE_DELAY begin end
+      `else
+        #0.002 begin end
+      `endif
+    `endif
+`ifdef RANDOMIZE_REG_INIT
+  _RAND_0 = {1{`RANDOM}};
+  _T_28 = _RAND_0[7:0];
+  _RAND_1 = {1{`RANDOM}};
+  _T_31 = _RAND_1[31:0];
+  _RAND_2 = {1{`RANDOM}};
+  _T_34 = _RAND_2[31:0];
+  _RAND_3 = {1{`RANDOM}};
+  picm_rd_data_r_32 = _RAND_3[31:0];
+  _RAND_4 = {1{`RANDOM}};
+  _T_14 = _RAND_4[31:0];
+  _RAND_5 = {1{`RANDOM}};
+  _T_18 = _RAND_5[31:0];
+  _RAND_6 = {1{`RANDOM}};
+  _T_22 = _RAND_6[6:0];
+  _RAND_7 = {1{`RANDOM}};
+  _T_26 = _RAND_7[6:0];
+  _RAND_8 = {1{`RANDOM}};
+  _T_42 = _RAND_8[2:0];
+  _RAND_9 = {1{`RANDOM}};
+  ld_single_ecc_error_lo_r_ff = _RAND_9[0:0];
+  _RAND_10 = {1{`RANDOM}};
+  ld_single_ecc_error_hi_r_ff = _RAND_10[0:0];
+  _RAND_11 = {1{`RANDOM}};
+  lsu_double_ecc_error_r_ff = _RAND_11[0:0];
+  _RAND_12 = {1{`RANDOM}};
+  ld_sec_addr_lo_r_ff = _RAND_12[15:0];
+  _RAND_13 = {1{`RANDOM}};
+  ld_sec_addr_hi_r_ff = _RAND_13[15:0];
+  _RAND_14 = {1{`RANDOM}};
+  dccm_wren_Q = _RAND_14[0:0];
+  _RAND_15 = {1{`RANDOM}};
+  dccm_wr_bypass_d_m_lo_Q = _RAND_15[0:0];
+  _RAND_16 = {1{`RANDOM}};
+  dccm_wr_data_Q = _RAND_16[31:0];
+  _RAND_17 = {1{`RANDOM}};
+  dccm_wr_bypass_d_m_hi_Q = _RAND_17[0:0];
+  _RAND_18 = {1{`RANDOM}};
+  _T_1877 = _RAND_18[31:0];
+  _RAND_19 = {1{`RANDOM}};
+  _T_1906 = _RAND_19[0:0];
+  _RAND_20 = {1{`RANDOM}};
+  _T_1907 = _RAND_20[0:0];
+`endif // RANDOMIZE_REG_INIT
+  if (reset) begin
+    _T_28 = 8'h0;
+  end
+  if (reset) begin
+    _T_31 = 32'h0;
+  end
+  if (reset) begin
+    _T_34 = 32'h0;
+  end
+  if (reset) begin
+    picm_rd_data_r_32 = 32'h0;
+  end
+  if (reset) begin
+    _T_14 = 32'h0;
+  end
+  if (reset) begin
+    _T_18 = 32'h0;
+  end
+  if (reset) begin
+    _T_22 = 7'h0;
+  end
+  if (reset) begin
+    _T_26 = 7'h0;
+  end
+  if (reset) begin
+    _T_42 = 3'h0;
+  end
+  if (reset) begin
+    ld_single_ecc_error_lo_r_ff = 1'h0;
+  end
+  if (reset) begin
+    ld_single_ecc_error_hi_r_ff = 1'h0;
+  end
+  if (reset) begin
+    lsu_double_ecc_error_r_ff = 1'h0;
+  end
+  if (reset) begin
+    ld_sec_addr_lo_r_ff = 16'h0;
+  end
+  if (reset) begin
+    ld_sec_addr_hi_r_ff = 16'h0;
+  end
+  if (reset) begin
+    dccm_wren_Q = 1'h0;
+  end
+  if (reset) begin
+    dccm_wr_bypass_d_m_lo_Q = 1'h0;
+  end
+  if (reset) begin
+    dccm_wr_data_Q = 32'h0;
+  end
+  if (reset) begin
+    dccm_wr_bypass_d_m_hi_Q = 1'h0;
+  end
+  if (reset) begin
+    _T_1877 = 32'h0;
+  end
+  if (reset) begin
+    _T_1906 = 1'h0;
+  end
+  if (reset) begin
+    _T_1907 = 1'h0;
+  end
+  `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+  always @(posedge io_lsu_c2_r_clk or posedge reset) begin
+    if (reset) begin
+      _T_28 <= 8'h0;
+    end else begin
+      _T_28 <= {io_stbuf_fwdbyteen_hi_m,io_stbuf_fwdbyteen_lo_m};
+    end
+  end
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      _T_31 <= 32'h0;
+    end else if (stbuf_fwddata_en) begin
+      _T_31 <= io_stbuf_fwddata_hi_m;
+    end
+  end
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      _T_34 <= 32'h0;
+    end else if (stbuf_fwddata_en) begin
+      _T_34 <= io_stbuf_fwddata_lo_m;
+    end
+  end
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      picm_rd_data_r_32 <= 32'h0;
+    end else if (_T_37) begin
+      picm_rd_data_r_32 <= picm_rd_data_m[31:0];
+    end
+  end
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      _T_14 <= 32'h0;
+    end else if (_T_11) begin
+      _T_14 <= io_dccm_rdata_hi_m;
+    end
+  end
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      _T_18 <= 32'h0;
+    end else if (_T_15) begin
+      _T_18 <= io_dccm_rdata_lo_m;
+    end
+  end
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      _T_22 <= 7'h0;
+    end else if (_T_15) begin
+      _T_22 <= io_dccm_data_ecc_hi_m;
+    end
+  end
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      _T_26 <= 7'h0;
+    end else if (_T_15) begin
+      _T_26 <= io_dccm_data_ecc_lo_m;
+    end
+  end
+  always @(posedge io_lsu_c1_r_clk or posedge reset) begin
+    if (reset) begin
+      _T_42 <= 3'h0;
+    end else begin
+      _T_42 <= io_dma_mem_tag_m;
+    end
+  end
+  always @(posedge io_lsu_free_c2_clk or posedge reset) begin
+    if (reset) begin
+      ld_single_ecc_error_lo_r_ff <= 1'h0;
+    end else begin
+      ld_single_ecc_error_lo_r_ff <= _T_875 & _T_876;
+    end
+  end
+  always @(posedge io_lsu_free_c2_clk or posedge reset) begin
+    if (reset) begin
+      ld_single_ecc_error_hi_r_ff <= 1'h0;
+    end else begin
+      ld_single_ecc_error_hi_r_ff <= _T_878 & _T_879;
+    end
+  end
+  always @(posedge io_lsu_free_c2_clk or posedge reset) begin
+    if (reset) begin
+      lsu_double_ecc_error_r_ff <= 1'h0;
+    end else begin
+      lsu_double_ecc_error_r_ff <= io_lsu_double_ecc_error_r;
+    end
+  end
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      ld_sec_addr_lo_r_ff <= 16'h0;
+    end else if (_T_1912) begin
+      ld_sec_addr_lo_r_ff <= io_lsu_addr_r[15:0];
+    end
+  end
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      ld_sec_addr_hi_r_ff <= 16'h0;
+    end else if (_T_1912) begin
+      ld_sec_addr_hi_r_ff <= io_end_addr_r;
+    end
+  end
+  always @(posedge io_lsu_free_c2_clk or posedge reset) begin
+    if (reset) begin
+      dccm_wren_Q <= 1'h0;
+    end else begin
+      dccm_wren_Q <= io_lsu_stbuf_commit_any;
+    end
+  end
+  always @(posedge io_lsu_free_c2_clk or posedge reset) begin
+    if (reset) begin
+      dccm_wr_bypass_d_m_lo_Q <= 1'h0;
+    end else begin
+      dccm_wr_bypass_d_m_lo_Q <= _T_1000 & io_addr_in_dccm_m;
+    end
+  end
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      dccm_wr_data_Q <= 32'h0;
+    end else if (_T_1871) begin
+      dccm_wr_data_Q <= io_stbuf_data_any;
+    end
+  end
+  always @(posedge io_lsu_free_c2_clk or posedge reset) begin
+    if (reset) begin
+      dccm_wr_bypass_d_m_hi_Q <= 1'h0;
+    end else begin
+      dccm_wr_bypass_d_m_hi_Q <= _T_1003 & io_addr_in_dccm_m;
+    end
+  end
+  always @(posedge io_lsu_store_c1_r_clk or posedge reset) begin
+    if (reset) begin
+      _T_1877 <= 32'h0;
+    end else begin
+      _T_1877 <= io_store_data_m;
+    end
+  end
+  always @(posedge io_lsu_c2_m_clk or posedge reset) begin
+    if (reset) begin
+      _T_1906 <= 1'h0;
+    end else begin
+      _T_1906 <= _T_887 & io_addr_in_dccm_d;
+    end
+  end
+  always @(posedge io_lsu_c2_r_clk or posedge reset) begin
+    if (reset) begin
+      _T_1907 <= 1'h0;
+    end else begin
+      _T_1907 <= io_lsu_dccm_rden_m;
+    end
+  end
+endmodule
diff --git a/lsu_lsc_ctl.anno.json b/lsu_lsc_ctl.anno.json
new file mode 100644
index 00000000..ac81a7bf
--- /dev/null
+++ b/lsu_lsc_ctl.anno.json
@@ -0,0 +1,372 @@
+[
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_store_data_m",
+    "sources":[
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_result_m",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_picm_mask_data_m",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_store_data_bypass_m",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_addr_in_pic_m",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_word",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_ld_data_r",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_half",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_by",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_unsign"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_word",
+    "sources":[
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_word",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_sz"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_load_ldst_bypass_d",
+    "sources":[
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_load_ldst_bypass_d",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_fast_int",
+    "sources":[
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_fast_int",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_addr_d",
+    "sources":[
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_result_m",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_load_ldst_bypass_d",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_exu_exu_lsu_rs1_d",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_addr",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_offset_d",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_load_ldst_bypass_d",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_word",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_ld_data_r",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_half",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_by",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_unsign"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_end_addr_r",
+    "sources":[
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_ldst_dual_r",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_addr_r"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_store",
+    "sources":[
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_store",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_write"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_half",
+    "sources":[
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_half",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_sz"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_fir_addr",
+    "sources":[
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_ld_data_corr_r"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_end_addr_m",
+    "sources":[
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_ldst_dual_m",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_addr_m"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_error_pkt_r_bits_mscause",
+    "sources":[
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_double_ecc_error_r"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_store_data_bypass_d",
+    "sources":[
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_store_data_bypass_d",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_dma",
+    "sources":[
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_dma",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_end_addr_d",
+    "sources":[
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_result_m",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_load_ldst_bypass_d",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_exu_exu_lsu_rs1_d",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_addr",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_load_ldst_bypass_d",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_word",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_ld_data_r",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_offset_d",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_half",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_by",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_unsign",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_dword",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_half",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_word",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_dword",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_half",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_word",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_sz"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_stack",
+    "sources":[
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_stack",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_valid",
+    "sources":[
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_dccm_req",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_valid",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_flush_m_up",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_fast_int"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_commit_r",
+    "sources":[
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_dma",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_valid",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_flush_r",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_store",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_load"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_unsign",
+    "sources":[
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_unsign",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_error_pkt_r_bits_addr",
+    "sources":[
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_addr_r"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_fir_error",
+    "sources":[
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_fast_int",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_double_ecc_error_r"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_error_pkt_r_bits_inst_type",
+    "sources":[
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_store"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_result_m",
+    "sources":[
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_word",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_ld_data_r",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_half",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_by",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_unsign"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_addr_in_dccm_d",
+    "sources":[
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_result_m",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_load_ldst_bypass_d",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_exu_exu_lsu_rs1_d",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_addr",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_load_ldst_bypass_d",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_offset_d",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_word",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_ld_data_r",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_half",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_by",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_unsign",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_dword",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_half",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_word",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_dword",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_half",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_word",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_sz"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_error_pkt_r_valid",
+    "sources":[
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_fast_int",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_valid",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_dma",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_double_ecc_error_r"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_load",
+    "sources":[
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_load",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_write"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_single_ecc_error_incr",
+    "sources":[
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_valid",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_single_ecc_error_r",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_commit_r",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_dma",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_double_ecc_error_r",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_flush_r",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_store",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_load"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_dword",
+    "sources":[
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_dword",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_sz"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_by",
+    "sources":[
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_by",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_sz"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_store_data_bypass_m",
+    "sources":[
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_store_data_bypass_m",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_addr_in_pic_d",
+    "sources":[
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_result_m",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_load_ldst_bypass_d",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_exu_exu_lsu_rs1_d",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_addr",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_load_ldst_bypass_d",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_offset_d",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_word",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_ld_data_r",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_half",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_by",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_unsign",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_dword",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_half",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_word",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_dword",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_half",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_word",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_sz"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_error_pkt_r_bits_single_ecc_error",
+    "sources":[
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_single_ecc_error_r",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_dma",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_error_pkt_r_valid",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_fast_int",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_valid",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_double_ecc_error_r"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_result_corr_r",
+    "sources":[
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_word",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_ld_data_corr_r",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_half",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_by",
+      "~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_unsign"
+    ]
+  },
+  {
+    "class":"firrtl.EmitCircuitAnnotation",
+    "emitter":"firrtl.VerilogEmitter"
+  },
+  {
+    "class":"firrtl.transforms.BlackBoxResourceAnno",
+    "target":"lsu_lsc_ctl.gated_latch",
+    "resourceId":"/vsrc/gated_latch.sv"
+  },
+  {
+    "class":"firrtl.options.TargetDirAnnotation",
+    "directory":"."
+  },
+  {
+    "class":"firrtl.options.OutputAnnotationFileAnnotation",
+    "file":"lsu_lsc_ctl"
+  },
+  {
+    "class":"firrtl.transforms.BlackBoxTargetDirAnno",
+    "targetDir":"."
+  }
+]
\ No newline at end of file
diff --git a/lsu_lsc_ctl.fir b/lsu_lsc_ctl.fir
new file mode 100644
index 00000000..61105311
--- /dev/null
+++ b/lsu_lsc_ctl.fir
@@ -0,0 +1,926 @@
+;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
+circuit lsu_lsc_ctl : 
+  module lsu_addrcheck : 
+    input clock : Clock
+    input reset : AsyncReset
+    output io : {flip lsu_c2_m_clk : Clock, flip start_addr_d : UInt<32>, flip end_addr_d : UInt<32>, flip lsu_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip dec_tlu_mrac_ff : UInt<32>, flip rs1_region_d : UInt<4>, flip rs1_d : UInt<32>, is_sideeffects_m : UInt<1>, addr_in_dccm_d : UInt<1>, addr_in_pic_d : UInt<1>, addr_external_d : UInt<1>, access_fault_d : UInt<1>, misaligned_fault_d : UInt<1>, exc_mscause_d : UInt<4>, fir_dccm_access_error_d : UInt<1>, fir_nondccm_access_error_d : UInt<1>, flip scan_mode : UInt<1>}
+    
+    node _T = bits(io.start_addr_d, 31, 28) @[lib.scala 365:27]
+    node start_addr_in_dccm_region_d = eq(_T, UInt<4>("h0f")) @[lib.scala 365:49]
+    wire start_addr_in_dccm_d : UInt<1> @[lib.scala 366:26]
+    node _T_1 = bits(io.start_addr_d, 31, 16) @[lib.scala 370:24]
+    node _T_2 = eq(_T_1, UInt<16>("h0f004")) @[lib.scala 370:39]
+    start_addr_in_dccm_d <= _T_2 @[lib.scala 370:16]
+    node _T_3 = bits(io.end_addr_d, 31, 28) @[lib.scala 365:27]
+    node end_addr_in_dccm_region_d = eq(_T_3, UInt<4>("h0f")) @[lib.scala 365:49]
+    wire end_addr_in_dccm_d : UInt<1> @[lib.scala 366:26]
+    node _T_4 = bits(io.end_addr_d, 31, 16) @[lib.scala 370:24]
+    node _T_5 = eq(_T_4, UInt<16>("h0f004")) @[lib.scala 370:39]
+    end_addr_in_dccm_d <= _T_5 @[lib.scala 370:16]
+    wire addr_in_iccm : UInt<1>
+    addr_in_iccm <= UInt<1>("h00")
+    node _T_6 = bits(io.start_addr_d, 31, 28) @[lsu_addrcheck.scala 42:37]
+    node _T_7 = eq(_T_6, UInt<4>("h0e")) @[lsu_addrcheck.scala 42:45]
+    addr_in_iccm <= _T_7 @[lsu_addrcheck.scala 42:18]
+    node _T_8 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 50:89]
+    node _T_9 = bits(_T_8, 31, 28) @[lib.scala 365:27]
+    node start_addr_in_pic_region_d = eq(_T_9, UInt<4>("h0f")) @[lib.scala 365:49]
+    wire start_addr_in_pic_d : UInt<1> @[lib.scala 366:26]
+    node _T_10 = bits(_T_8, 31, 15) @[lib.scala 370:24]
+    node _T_11 = eq(_T_10, UInt<17>("h01e018")) @[lib.scala 370:39]
+    start_addr_in_pic_d <= _T_11 @[lib.scala 370:16]
+    node _T_12 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 52:83]
+    node _T_13 = bits(_T_12, 31, 28) @[lib.scala 365:27]
+    node end_addr_in_pic_region_d = eq(_T_13, UInt<4>("h0f")) @[lib.scala 365:49]
+    wire end_addr_in_pic_d : UInt<1> @[lib.scala 366:26]
+    node _T_14 = bits(_T_12, 31, 15) @[lib.scala 370:24]
+    node _T_15 = eq(_T_14, UInt<17>("h01e018")) @[lib.scala 370:39]
+    end_addr_in_pic_d <= _T_15 @[lib.scala 370:16]
+    node start_addr_dccm_or_pic = or(start_addr_in_dccm_region_d, start_addr_in_pic_region_d) @[lsu_addrcheck.scala 54:60]
+    node _T_16 = bits(io.rs1_region_d, 3, 0) @[lsu_addrcheck.scala 55:49]
+    node _T_17 = eq(_T_16, UInt<4>("h0f")) @[lsu_addrcheck.scala 55:55]
+    node _T_18 = and(_T_17, UInt<1>("h01")) @[lsu_addrcheck.scala 55:74]
+    node _T_19 = bits(io.rs1_region_d, 3, 0) @[lsu_addrcheck.scala 55:109]
+    node _T_20 = eq(_T_19, UInt<4>("h0f")) @[lsu_addrcheck.scala 55:115]
+    node base_reg_dccm_or_pic = or(_T_18, _T_20) @[lsu_addrcheck.scala 55:91]
+    node _T_21 = and(start_addr_in_dccm_d, end_addr_in_dccm_d) @[lsu_addrcheck.scala 56:57]
+    io.addr_in_dccm_d <= _T_21 @[lsu_addrcheck.scala 56:32]
+    node _T_22 = and(start_addr_in_pic_d, end_addr_in_pic_d) @[lsu_addrcheck.scala 57:56]
+    io.addr_in_pic_d <= _T_22 @[lsu_addrcheck.scala 57:32]
+    node _T_23 = or(start_addr_in_dccm_region_d, start_addr_in_pic_region_d) @[lsu_addrcheck.scala 59:63]
+    node _T_24 = not(_T_23) @[lsu_addrcheck.scala 59:33]
+    io.addr_external_d <= _T_24 @[lsu_addrcheck.scala 59:30]
+    node _T_25 = bits(io.start_addr_d, 31, 28) @[lsu_addrcheck.scala 60:51]
+    node csr_idx = cat(_T_25, UInt<1>("h01")) @[Cat.scala 29:58]
+    node _T_26 = dshr(io.dec_tlu_mrac_ff, csr_idx) @[lsu_addrcheck.scala 61:50]
+    node _T_27 = bits(_T_26, 0, 0) @[lsu_addrcheck.scala 61:50]
+    node _T_28 = or(start_addr_in_dccm_region_d, start_addr_in_pic_region_d) @[lsu_addrcheck.scala 61:92]
+    node _T_29 = or(_T_28, addr_in_iccm) @[lsu_addrcheck.scala 61:121]
+    node _T_30 = eq(_T_29, UInt<1>("h00")) @[lsu_addrcheck.scala 61:62]
+    node _T_31 = and(_T_27, _T_30) @[lsu_addrcheck.scala 61:60]
+    node _T_32 = and(_T_31, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 61:137]
+    node _T_33 = or(io.lsu_pkt_d.bits.store, io.lsu_pkt_d.bits.load) @[lsu_addrcheck.scala 61:185]
+    node is_sideeffects_d = and(_T_32, _T_33) @[lsu_addrcheck.scala 61:158]
+    node _T_34 = bits(io.start_addr_d, 1, 0) @[lsu_addrcheck.scala 62:74]
+    node _T_35 = eq(_T_34, UInt<1>("h00")) @[lsu_addrcheck.scala 62:80]
+    node _T_36 = and(io.lsu_pkt_d.bits.word, _T_35) @[lsu_addrcheck.scala 62:56]
+    node _T_37 = bits(io.start_addr_d, 0, 0) @[lsu_addrcheck.scala 62:134]
+    node _T_38 = eq(_T_37, UInt<1>("h00")) @[lsu_addrcheck.scala 62:138]
+    node _T_39 = and(io.lsu_pkt_d.bits.half, _T_38) @[lsu_addrcheck.scala 62:116]
+    node _T_40 = or(_T_36, _T_39) @[lsu_addrcheck.scala 62:90]
+    node is_aligned_d = or(_T_40, io.lsu_pkt_d.bits.by) @[lsu_addrcheck.scala 62:148]
+    node _T_41 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58]
+    node _T_42 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58]
+    node _T_43 = cat(_T_42, _T_41) @[Cat.scala 29:58]
+    node _T_44 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 29:58]
+    node _T_45 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 29:58]
+    node _T_46 = cat(_T_45, _T_44) @[Cat.scala 29:58]
+    node _T_47 = cat(_T_46, _T_43) @[Cat.scala 29:58]
+    node _T_48 = orr(_T_47) @[lsu_addrcheck.scala 66:99]
+    node _T_49 = eq(_T_48, UInt<1>("h00")) @[lsu_addrcheck.scala 65:33]
+    node _T_50 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 67:49]
+    node _T_51 = or(_T_50, UInt<31>("h07fffffff")) @[lsu_addrcheck.scala 67:56]
+    node _T_52 = or(UInt<1>("h00"), UInt<31>("h07fffffff")) @[lsu_addrcheck.scala 67:121]
+    node _T_53 = eq(_T_51, _T_52) @[lsu_addrcheck.scala 67:88]
+    node _T_54 = and(UInt<1>("h01"), _T_53) @[lsu_addrcheck.scala 67:30]
+    node _T_55 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 68:49]
+    node _T_56 = or(_T_55, UInt<30>("h03fffffff")) @[lsu_addrcheck.scala 68:56]
+    node _T_57 = or(UInt<32>("h0c0000000"), UInt<30>("h03fffffff")) @[lsu_addrcheck.scala 68:121]
+    node _T_58 = eq(_T_56, _T_57) @[lsu_addrcheck.scala 68:88]
+    node _T_59 = and(UInt<1>("h01"), _T_58) @[lsu_addrcheck.scala 68:30]
+    node _T_60 = or(_T_54, _T_59) @[lsu_addrcheck.scala 67:153]
+    node _T_61 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 69:49]
+    node _T_62 = or(_T_61, UInt<29>("h01fffffff")) @[lsu_addrcheck.scala 69:56]
+    node _T_63 = or(UInt<32>("h0a0000000"), UInt<29>("h01fffffff")) @[lsu_addrcheck.scala 69:121]
+    node _T_64 = eq(_T_62, _T_63) @[lsu_addrcheck.scala 69:88]
+    node _T_65 = and(UInt<1>("h01"), _T_64) @[lsu_addrcheck.scala 69:30]
+    node _T_66 = or(_T_60, _T_65) @[lsu_addrcheck.scala 68:153]
+    node _T_67 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 70:49]
+    node _T_68 = or(_T_67, UInt<28>("h0fffffff")) @[lsu_addrcheck.scala 70:56]
+    node _T_69 = or(UInt<32>("h080000000"), UInt<28>("h0fffffff")) @[lsu_addrcheck.scala 70:121]
+    node _T_70 = eq(_T_68, _T_69) @[lsu_addrcheck.scala 70:88]
+    node _T_71 = and(UInt<1>("h01"), _T_70) @[lsu_addrcheck.scala 70:30]
+    node _T_72 = or(_T_66, _T_71) @[lsu_addrcheck.scala 69:153]
+    node _T_73 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 71:49]
+    node _T_74 = or(_T_73, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 71:56]
+    node _T_75 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 71:121]
+    node _T_76 = eq(_T_74, _T_75) @[lsu_addrcheck.scala 71:88]
+    node _T_77 = and(UInt<1>("h00"), _T_76) @[lsu_addrcheck.scala 71:30]
+    node _T_78 = or(_T_72, _T_77) @[lsu_addrcheck.scala 70:153]
+    node _T_79 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 72:49]
+    node _T_80 = or(_T_79, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 72:56]
+    node _T_81 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 72:121]
+    node _T_82 = eq(_T_80, _T_81) @[lsu_addrcheck.scala 72:88]
+    node _T_83 = and(UInt<1>("h00"), _T_82) @[lsu_addrcheck.scala 72:30]
+    node _T_84 = or(_T_78, _T_83) @[lsu_addrcheck.scala 71:153]
+    node _T_85 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 73:49]
+    node _T_86 = or(_T_85, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 73:56]
+    node _T_87 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 73:121]
+    node _T_88 = eq(_T_86, _T_87) @[lsu_addrcheck.scala 73:88]
+    node _T_89 = and(UInt<1>("h00"), _T_88) @[lsu_addrcheck.scala 73:30]
+    node _T_90 = or(_T_84, _T_89) @[lsu_addrcheck.scala 72:153]
+    node _T_91 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 74:49]
+    node _T_92 = or(_T_91, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 74:56]
+    node _T_93 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 74:121]
+    node _T_94 = eq(_T_92, _T_93) @[lsu_addrcheck.scala 74:88]
+    node _T_95 = and(UInt<1>("h00"), _T_94) @[lsu_addrcheck.scala 74:30]
+    node _T_96 = or(_T_90, _T_95) @[lsu_addrcheck.scala 73:153]
+    node _T_97 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 76:48]
+    node _T_98 = or(_T_97, UInt<31>("h07fffffff")) @[lsu_addrcheck.scala 76:57]
+    node _T_99 = or(UInt<1>("h00"), UInt<31>("h07fffffff")) @[lsu_addrcheck.scala 76:122]
+    node _T_100 = eq(_T_98, _T_99) @[lsu_addrcheck.scala 76:89]
+    node _T_101 = and(UInt<1>("h01"), _T_100) @[lsu_addrcheck.scala 76:31]
+    node _T_102 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 77:49]
+    node _T_103 = or(_T_102, UInt<30>("h03fffffff")) @[lsu_addrcheck.scala 77:58]
+    node _T_104 = or(UInt<32>("h0c0000000"), UInt<30>("h03fffffff")) @[lsu_addrcheck.scala 77:123]
+    node _T_105 = eq(_T_103, _T_104) @[lsu_addrcheck.scala 77:90]
+    node _T_106 = and(UInt<1>("h01"), _T_105) @[lsu_addrcheck.scala 77:32]
+    node _T_107 = or(_T_101, _T_106) @[lsu_addrcheck.scala 76:154]
+    node _T_108 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 78:49]
+    node _T_109 = or(_T_108, UInt<29>("h01fffffff")) @[lsu_addrcheck.scala 78:58]
+    node _T_110 = or(UInt<32>("h0a0000000"), UInt<29>("h01fffffff")) @[lsu_addrcheck.scala 78:123]
+    node _T_111 = eq(_T_109, _T_110) @[lsu_addrcheck.scala 78:90]
+    node _T_112 = and(UInt<1>("h01"), _T_111) @[lsu_addrcheck.scala 78:32]
+    node _T_113 = or(_T_107, _T_112) @[lsu_addrcheck.scala 77:155]
+    node _T_114 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 79:49]
+    node _T_115 = or(_T_114, UInt<28>("h0fffffff")) @[lsu_addrcheck.scala 79:58]
+    node _T_116 = or(UInt<32>("h080000000"), UInt<28>("h0fffffff")) @[lsu_addrcheck.scala 79:123]
+    node _T_117 = eq(_T_115, _T_116) @[lsu_addrcheck.scala 79:90]
+    node _T_118 = and(UInt<1>("h01"), _T_117) @[lsu_addrcheck.scala 79:32]
+    node _T_119 = or(_T_113, _T_118) @[lsu_addrcheck.scala 78:155]
+    node _T_120 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 80:49]
+    node _T_121 = or(_T_120, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 80:58]
+    node _T_122 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 80:123]
+    node _T_123 = eq(_T_121, _T_122) @[lsu_addrcheck.scala 80:90]
+    node _T_124 = and(UInt<1>("h00"), _T_123) @[lsu_addrcheck.scala 80:32]
+    node _T_125 = or(_T_119, _T_124) @[lsu_addrcheck.scala 79:155]
+    node _T_126 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 81:49]
+    node _T_127 = or(_T_126, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 81:58]
+    node _T_128 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 81:123]
+    node _T_129 = eq(_T_127, _T_128) @[lsu_addrcheck.scala 81:90]
+    node _T_130 = and(UInt<1>("h00"), _T_129) @[lsu_addrcheck.scala 81:32]
+    node _T_131 = or(_T_125, _T_130) @[lsu_addrcheck.scala 80:155]
+    node _T_132 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 82:49]
+    node _T_133 = or(_T_132, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 82:58]
+    node _T_134 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 82:123]
+    node _T_135 = eq(_T_133, _T_134) @[lsu_addrcheck.scala 82:90]
+    node _T_136 = and(UInt<1>("h00"), _T_135) @[lsu_addrcheck.scala 82:32]
+    node _T_137 = or(_T_131, _T_136) @[lsu_addrcheck.scala 81:155]
+    node _T_138 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 83:49]
+    node _T_139 = or(_T_138, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 83:58]
+    node _T_140 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 83:123]
+    node _T_141 = eq(_T_139, _T_140) @[lsu_addrcheck.scala 83:90]
+    node _T_142 = and(UInt<1>("h00"), _T_141) @[lsu_addrcheck.scala 83:32]
+    node _T_143 = or(_T_137, _T_142) @[lsu_addrcheck.scala 82:155]
+    node _T_144 = and(_T_96, _T_143) @[lsu_addrcheck.scala 75:7]
+    node non_dccm_access_ok = or(_T_49, _T_144) @[lsu_addrcheck.scala 66:104]
+    node regpred_access_fault_d = xor(start_addr_dccm_or_pic, base_reg_dccm_or_pic) @[lsu_addrcheck.scala 85:57]
+    node _T_145 = bits(io.start_addr_d, 1, 0) @[lsu_addrcheck.scala 86:70]
+    node _T_146 = neq(_T_145, UInt<2>("h00")) @[lsu_addrcheck.scala 86:76]
+    node _T_147 = eq(io.lsu_pkt_d.bits.word, UInt<1>("h00")) @[lsu_addrcheck.scala 86:92]
+    node _T_148 = or(_T_146, _T_147) @[lsu_addrcheck.scala 86:90]
+    node picm_access_fault_d = and(io.addr_in_pic_d, _T_148) @[lsu_addrcheck.scala 86:51]
+    wire unmapped_access_fault_d : UInt<1>
+    unmapped_access_fault_d <= UInt<1>("h01")
+    wire mpu_access_fault_d : UInt<1>
+    mpu_access_fault_d <= UInt<1>("h01")
+    node _T_149 = or(start_addr_in_dccm_d, start_addr_in_pic_d) @[lsu_addrcheck.scala 91:87]
+    node _T_150 = eq(_T_149, UInt<1>("h00")) @[lsu_addrcheck.scala 91:64]
+    node _T_151 = and(start_addr_in_dccm_region_d, _T_150) @[lsu_addrcheck.scala 91:62]
+    node _T_152 = or(end_addr_in_dccm_d, end_addr_in_pic_d) @[lsu_addrcheck.scala 93:57]
+    node _T_153 = eq(_T_152, UInt<1>("h00")) @[lsu_addrcheck.scala 93:36]
+    node _T_154 = and(end_addr_in_dccm_region_d, _T_153) @[lsu_addrcheck.scala 93:34]
+    node _T_155 = or(_T_151, _T_154) @[lsu_addrcheck.scala 91:112]
+    node _T_156 = and(start_addr_in_dccm_d, end_addr_in_pic_d) @[lsu_addrcheck.scala 95:29]
+    node _T_157 = or(_T_155, _T_156) @[lsu_addrcheck.scala 93:85]
+    node _T_158 = and(start_addr_in_pic_d, end_addr_in_dccm_d) @[lsu_addrcheck.scala 97:29]
+    node _T_159 = or(_T_157, _T_158) @[lsu_addrcheck.scala 95:85]
+    unmapped_access_fault_d <= _T_159 @[lsu_addrcheck.scala 91:29]
+    node _T_160 = eq(start_addr_in_dccm_region_d, UInt<1>("h00")) @[lsu_addrcheck.scala 99:33]
+    node _T_161 = eq(non_dccm_access_ok, UInt<1>("h00")) @[lsu_addrcheck.scala 99:64]
+    node _T_162 = and(_T_160, _T_161) @[lsu_addrcheck.scala 99:62]
+    mpu_access_fault_d <= _T_162 @[lsu_addrcheck.scala 99:29]
+    node _T_163 = or(unmapped_access_fault_d, mpu_access_fault_d) @[lsu_addrcheck.scala 111:49]
+    node _T_164 = or(_T_163, picm_access_fault_d) @[lsu_addrcheck.scala 111:70]
+    node _T_165 = or(_T_164, regpred_access_fault_d) @[lsu_addrcheck.scala 111:92]
+    node _T_166 = and(_T_165, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 111:118]
+    node _T_167 = eq(io.lsu_pkt_d.bits.dma, UInt<1>("h00")) @[lsu_addrcheck.scala 111:141]
+    node _T_168 = and(_T_166, _T_167) @[lsu_addrcheck.scala 111:139]
+    io.access_fault_d <= _T_168 @[lsu_addrcheck.scala 111:21]
+    node _T_169 = bits(unmapped_access_fault_d, 0, 0) @[lsu_addrcheck.scala 112:60]
+    node _T_170 = bits(mpu_access_fault_d, 0, 0) @[lsu_addrcheck.scala 112:100]
+    node _T_171 = bits(regpred_access_fault_d, 0, 0) @[lsu_addrcheck.scala 112:144]
+    node _T_172 = bits(picm_access_fault_d, 0, 0) @[lsu_addrcheck.scala 112:185]
+    node _T_173 = mux(_T_172, UInt<4>("h06"), UInt<4>("h00")) @[lsu_addrcheck.scala 112:164]
+    node _T_174 = mux(_T_171, UInt<4>("h05"), _T_173) @[lsu_addrcheck.scala 112:120]
+    node _T_175 = mux(_T_170, UInt<4>("h03"), _T_174) @[lsu_addrcheck.scala 112:80]
+    node access_fault_mscause_d = mux(_T_169, UInt<4>("h02"), _T_175) @[lsu_addrcheck.scala 112:35]
+    node _T_176 = bits(io.start_addr_d, 31, 28) @[lsu_addrcheck.scala 113:53]
+    node _T_177 = bits(io.end_addr_d, 31, 28) @[lsu_addrcheck.scala 113:78]
+    node regcross_misaligned_fault_d = neq(_T_176, _T_177) @[lsu_addrcheck.scala 113:61]
+    node _T_178 = eq(is_aligned_d, UInt<1>("h00")) @[lsu_addrcheck.scala 114:59]
+    node sideeffect_misaligned_fault_d = and(is_sideeffects_d, _T_178) @[lsu_addrcheck.scala 114:57]
+    node _T_179 = and(sideeffect_misaligned_fault_d, io.addr_external_d) @[lsu_addrcheck.scala 115:90]
+    node _T_180 = or(regcross_misaligned_fault_d, _T_179) @[lsu_addrcheck.scala 115:57]
+    node _T_181 = and(_T_180, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 115:113]
+    node _T_182 = eq(io.lsu_pkt_d.bits.dma, UInt<1>("h00")) @[lsu_addrcheck.scala 115:136]
+    node _T_183 = and(_T_181, _T_182) @[lsu_addrcheck.scala 115:134]
+    io.misaligned_fault_d <= _T_183 @[lsu_addrcheck.scala 115:25]
+    node _T_184 = bits(sideeffect_misaligned_fault_d, 0, 0) @[lsu_addrcheck.scala 116:111]
+    node _T_185 = mux(_T_184, UInt<4>("h01"), UInt<4>("h00")) @[lsu_addrcheck.scala 116:80]
+    node misaligned_fault_mscause_d = mux(regcross_misaligned_fault_d, UInt<4>("h02"), _T_185) @[lsu_addrcheck.scala 116:39]
+    node _T_186 = bits(io.misaligned_fault_d, 0, 0) @[lsu_addrcheck.scala 117:50]
+    node _T_187 = bits(misaligned_fault_mscause_d, 3, 0) @[lsu_addrcheck.scala 117:84]
+    node _T_188 = bits(access_fault_mscause_d, 3, 0) @[lsu_addrcheck.scala 117:113]
+    node _T_189 = mux(_T_186, _T_187, _T_188) @[lsu_addrcheck.scala 117:27]
+    io.exc_mscause_d <= _T_189 @[lsu_addrcheck.scala 117:21]
+    node _T_190 = eq(start_addr_in_dccm_d, UInt<1>("h00")) @[lsu_addrcheck.scala 118:66]
+    node _T_191 = and(start_addr_in_dccm_region_d, _T_190) @[lsu_addrcheck.scala 118:64]
+    node _T_192 = eq(end_addr_in_dccm_d, UInt<1>("h00")) @[lsu_addrcheck.scala 118:120]
+    node _T_193 = and(end_addr_in_dccm_region_d, _T_192) @[lsu_addrcheck.scala 118:118]
+    node _T_194 = or(_T_191, _T_193) @[lsu_addrcheck.scala 118:88]
+    node _T_195 = and(_T_194, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 118:142]
+    node _T_196 = and(_T_195, io.lsu_pkt_d.bits.fast_int) @[lsu_addrcheck.scala 118:163]
+    io.fir_dccm_access_error_d <= _T_196 @[lsu_addrcheck.scala 118:31]
+    node _T_197 = and(start_addr_in_dccm_region_d, end_addr_in_dccm_region_d) @[lsu_addrcheck.scala 119:66]
+    node _T_198 = eq(_T_197, UInt<1>("h00")) @[lsu_addrcheck.scala 119:36]
+    node _T_199 = and(_T_198, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 119:95]
+    node _T_200 = and(_T_199, io.lsu_pkt_d.bits.fast_int) @[lsu_addrcheck.scala 119:116]
+    io.fir_nondccm_access_error_d <= _T_200 @[lsu_addrcheck.scala 119:33]
+    reg _T_201 : UInt<1>, io.lsu_c2_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_addrcheck.scala 121:60]
+    _T_201 <= is_sideeffects_d @[lsu_addrcheck.scala 121:60]
+    io.is_sideeffects_m <= _T_201 @[lsu_addrcheck.scala 121:50]
+    
+  extmodule gated_latch : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch @[lib.scala 334:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 335:14]
+    clkhdr.CK <= io.clk @[lib.scala 336:18]
+    clkhdr.EN <= io.en @[lib.scala 337:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
+    
+  extmodule gated_latch_1 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr_1 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch_1 @[lib.scala 334:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 335:14]
+    clkhdr.CK <= io.clk @[lib.scala 336:18]
+    clkhdr.EN <= io.en @[lib.scala 337:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
+    
+  extmodule gated_latch_2 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr_2 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch_2 @[lib.scala 334:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 335:14]
+    clkhdr.CK <= io.clk @[lib.scala 336:18]
+    clkhdr.EN <= io.en @[lib.scala 337:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
+    
+  module lsu_lsc_ctl : 
+    input clock : Clock
+    input reset : AsyncReset
+    output io : {flip clk_override : UInt<1>, flip lsu_c1_m_clk : Clock, flip lsu_c1_r_clk : Clock, flip lsu_c2_m_clk : Clock, flip lsu_c2_r_clk : Clock, flip lsu_store_c1_m_clk : Clock, flip lsu_ld_data_r : UInt<32>, flip lsu_ld_data_corr_r : UInt<32>, flip lsu_single_ecc_error_r : UInt<1>, flip lsu_double_ecc_error_r : UInt<1>, flip lsu_ld_data_m : UInt<32>, flip lsu_single_ecc_error_m : UInt<1>, flip lsu_double_ecc_error_m : UInt<1>, flip flush_m_up : UInt<1>, flip flush_r : UInt<1>, flip ldst_dual_d : UInt<1>, flip ldst_dual_m : UInt<1>, flip ldst_dual_r : UInt<1>, lsu_exu : {flip exu_lsu_rs1_d : UInt<32>, flip exu_lsu_rs2_d : UInt<32>}, flip lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip dec_lsu_valid_raw_d : UInt<1>, flip dec_lsu_offset_d : UInt<12>, flip picm_mask_data_m : UInt<32>, flip bus_read_data_m : UInt<32>, lsu_result_m : UInt<32>, lsu_result_corr_r : UInt<32>, lsu_addr_d : UInt<32>, lsu_addr_m : UInt<32>, lsu_addr_r : UInt<32>, end_addr_d : UInt<32>, end_addr_m : UInt<32>, end_addr_r : UInt<32>, store_data_m : UInt<32>, flip dec_tlu_mrac_ff : UInt<32>, lsu_exc_m : UInt<1>, is_sideeffects_m : UInt<1>, lsu_commit_r : UInt<1>, lsu_single_ecc_error_incr : UInt<1>, lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, lsu_fir_addr : UInt<31>, lsu_fir_error : UInt<2>, addr_in_dccm_d : UInt<1>, addr_in_dccm_m : UInt<1>, addr_in_dccm_r : UInt<1>, addr_in_pic_d : UInt<1>, addr_in_pic_m : UInt<1>, addr_in_pic_r : UInt<1>, addr_external_m : UInt<1>, dma_lsc_ctl : {flip dma_dccm_req : UInt<1>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_write : UInt<1>, flip dma_mem_wdata : UInt<64>}, lsu_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, lsu_pkt_r : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip scan_mode : UInt<1>}
+    
+    wire end_addr_pre_m : UInt<29>
+    end_addr_pre_m <= UInt<29>("h00")
+    wire end_addr_pre_r : UInt<29>
+    end_addr_pre_r <= UInt<29>("h00")
+    wire dma_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 93:29]
+    wire lsu_pkt_m_in : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 94:29]
+    wire lsu_pkt_r_in : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 95:29]
+    wire lsu_error_pkt_m : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}} @[lsu_lsc_ctl.scala 96:29]
+    wire _T : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}} @[lsu_lsc_ctl.scala 97:37]
+    _T.bits.addr <= UInt<32>("h00") @[lsu_lsc_ctl.scala 97:37]
+    _T.bits.mscause <= UInt<4>("h00") @[lsu_lsc_ctl.scala 97:37]
+    _T.bits.exc_type <= UInt<1>("h00") @[lsu_lsc_ctl.scala 97:37]
+    _T.bits.inst_type <= UInt<1>("h00") @[lsu_lsc_ctl.scala 97:37]
+    _T.bits.single_ecc_error <= UInt<1>("h00") @[lsu_lsc_ctl.scala 97:37]
+    _T.valid <= UInt<1>("h00") @[lsu_lsc_ctl.scala 97:37]
+    lsu_error_pkt_m.bits.addr <= _T.bits.addr @[lsu_lsc_ctl.scala 97:20]
+    lsu_error_pkt_m.bits.mscause <= _T.bits.mscause @[lsu_lsc_ctl.scala 97:20]
+    lsu_error_pkt_m.bits.exc_type <= _T.bits.exc_type @[lsu_lsc_ctl.scala 97:20]
+    lsu_error_pkt_m.bits.inst_type <= _T.bits.inst_type @[lsu_lsc_ctl.scala 97:20]
+    lsu_error_pkt_m.bits.single_ecc_error <= _T.bits.single_ecc_error @[lsu_lsc_ctl.scala 97:20]
+    lsu_error_pkt_m.valid <= _T.valid @[lsu_lsc_ctl.scala 97:20]
+    node _T_1 = bits(io.dec_lsu_valid_raw_d, 0, 0) @[lsu_lsc_ctl.scala 100:52]
+    node lsu_rs1_d = mux(_T_1, io.lsu_exu.exu_lsu_rs1_d, io.dma_lsc_ctl.dma_mem_addr) @[lsu_lsc_ctl.scala 100:28]
+    node _T_2 = bits(io.dec_lsu_offset_d, 11, 0) @[lsu_lsc_ctl.scala 101:44]
+    node _T_3 = bits(io.dec_lsu_valid_raw_d, 0, 0) @[Bitwise.scala 72:15]
+    node _T_4 = mux(_T_3, UInt<12>("h0fff"), UInt<12>("h00")) @[Bitwise.scala 72:12]
+    node lsu_offset_d = and(_T_2, _T_4) @[lsu_lsc_ctl.scala 101:51]
+    node _T_5 = bits(io.lsu_pkt_d.bits.load_ldst_bypass_d, 0, 0) @[lsu_lsc_ctl.scala 104:66]
+    node rs1_d = mux(_T_5, io.lsu_result_m, lsu_rs1_d) @[lsu_lsc_ctl.scala 104:28]
+    node _T_6 = bits(rs1_d, 11, 0) @[lib.scala 92:31]
+    node _T_7 = cat(UInt<1>("h00"), _T_6) @[Cat.scala 29:58]
+    node _T_8 = bits(lsu_offset_d, 11, 0) @[lib.scala 92:60]
+    node _T_9 = cat(UInt<1>("h00"), _T_8) @[Cat.scala 29:58]
+    node _T_10 = add(_T_7, _T_9) @[lib.scala 92:39]
+    node _T_11 = tail(_T_10, 1) @[lib.scala 92:39]
+    node _T_12 = bits(lsu_offset_d, 11, 11) @[lib.scala 93:41]
+    node _T_13 = bits(_T_11, 12, 12) @[lib.scala 93:50]
+    node _T_14 = xor(_T_12, _T_13) @[lib.scala 93:46]
+    node _T_15 = not(_T_14) @[lib.scala 93:33]
+    node _T_16 = bits(_T_15, 0, 0) @[Bitwise.scala 72:15]
+    node _T_17 = mux(_T_16, UInt<20>("h0fffff"), UInt<20>("h00")) @[Bitwise.scala 72:12]
+    node _T_18 = bits(rs1_d, 31, 12) @[lib.scala 93:63]
+    node _T_19 = and(_T_17, _T_18) @[lib.scala 93:58]
+    node _T_20 = bits(lsu_offset_d, 11, 11) @[lib.scala 94:25]
+    node _T_21 = not(_T_20) @[lib.scala 94:18]
+    node _T_22 = bits(_T_11, 12, 12) @[lib.scala 94:34]
+    node _T_23 = and(_T_21, _T_22) @[lib.scala 94:30]
+    node _T_24 = bits(_T_23, 0, 0) @[Bitwise.scala 72:15]
+    node _T_25 = mux(_T_24, UInt<20>("h0fffff"), UInt<20>("h00")) @[Bitwise.scala 72:12]
+    node _T_26 = bits(rs1_d, 31, 12) @[lib.scala 94:47]
+    node _T_27 = add(_T_26, UInt<1>("h01")) @[lib.scala 94:54]
+    node _T_28 = tail(_T_27, 1) @[lib.scala 94:54]
+    node _T_29 = and(_T_25, _T_28) @[lib.scala 94:41]
+    node _T_30 = or(_T_19, _T_29) @[lib.scala 93:72]
+    node _T_31 = bits(lsu_offset_d, 11, 11) @[lib.scala 95:24]
+    node _T_32 = bits(_T_11, 12, 12) @[lib.scala 95:34]
+    node _T_33 = not(_T_32) @[lib.scala 95:31]
+    node _T_34 = and(_T_31, _T_33) @[lib.scala 95:29]
+    node _T_35 = bits(_T_34, 0, 0) @[Bitwise.scala 72:15]
+    node _T_36 = mux(_T_35, UInt<20>("h0fffff"), UInt<20>("h00")) @[Bitwise.scala 72:12]
+    node _T_37 = bits(rs1_d, 31, 12) @[lib.scala 95:47]
+    node _T_38 = sub(_T_37, UInt<1>("h01")) @[lib.scala 95:54]
+    node _T_39 = tail(_T_38, 1) @[lib.scala 95:54]
+    node _T_40 = and(_T_36, _T_39) @[lib.scala 95:41]
+    node _T_41 = or(_T_30, _T_40) @[lib.scala 94:61]
+    node _T_42 = bits(_T_11, 11, 0) @[lib.scala 96:22]
+    node full_addr_d = cat(_T_41, _T_42) @[Cat.scala 29:58]
+    node _T_43 = bits(io.lsu_pkt_d.bits.half, 0, 0) @[Bitwise.scala 72:15]
+    node _T_44 = mux(_T_43, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
+    node _T_45 = and(_T_44, UInt<3>("h01")) @[lsu_lsc_ctl.scala 109:58]
+    node _T_46 = bits(io.lsu_pkt_d.bits.word, 0, 0) @[Bitwise.scala 72:15]
+    node _T_47 = mux(_T_46, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
+    node _T_48 = and(_T_47, UInt<3>("h03")) @[lsu_lsc_ctl.scala 110:40]
+    node _T_49 = or(_T_45, _T_48) @[lsu_lsc_ctl.scala 109:70]
+    node _T_50 = bits(io.lsu_pkt_d.bits.dword, 0, 0) @[Bitwise.scala 72:15]
+    node _T_51 = mux(_T_50, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
+    node _T_52 = and(_T_51, UInt<3>("h07")) @[lsu_lsc_ctl.scala 111:40]
+    node addr_offset_d = or(_T_49, _T_52) @[lsu_lsc_ctl.scala 110:52]
+    node _T_53 = bits(lsu_offset_d, 11, 11) @[lsu_lsc_ctl.scala 113:39]
+    node _T_54 = bits(lsu_offset_d, 11, 0) @[lsu_lsc_ctl.scala 113:52]
+    node _T_55 = cat(_T_53, _T_54) @[Cat.scala 29:58]
+    node _T_56 = mux(UInt<1>("h00"), UInt<9>("h01ff"), UInt<9>("h00")) @[Bitwise.scala 72:12]
+    node _T_57 = bits(addr_offset_d, 2, 0) @[lsu_lsc_ctl.scala 113:91]
+    node _T_58 = cat(_T_56, _T_57) @[Cat.scala 29:58]
+    node _T_59 = add(_T_55, _T_58) @[lsu_lsc_ctl.scala 113:60]
+    node end_addr_offset_d = tail(_T_59, 1) @[lsu_lsc_ctl.scala 113:60]
+    node _T_60 = bits(rs1_d, 31, 0) @[lsu_lsc_ctl.scala 114:32]
+    node _T_61 = bits(end_addr_offset_d, 12, 12) @[lsu_lsc_ctl.scala 114:70]
+    node _T_62 = bits(_T_61, 0, 0) @[Bitwise.scala 72:15]
+    node _T_63 = mux(_T_62, UInt<19>("h07ffff"), UInt<19>("h00")) @[Bitwise.scala 72:12]
+    node _T_64 = bits(end_addr_offset_d, 12, 0) @[lsu_lsc_ctl.scala 114:93]
+    node _T_65 = cat(_T_63, _T_64) @[Cat.scala 29:58]
+    node _T_66 = add(_T_60, _T_65) @[lsu_lsc_ctl.scala 114:39]
+    node full_end_addr_d = tail(_T_66, 1) @[lsu_lsc_ctl.scala 114:39]
+    io.end_addr_d <= full_end_addr_d @[lsu_lsc_ctl.scala 115:24]
+    inst addrcheck of lsu_addrcheck @[lsu_lsc_ctl.scala 118:25]
+    addrcheck.clock <= clock
+    addrcheck.reset <= reset
+    addrcheck.io.lsu_c2_m_clk <= io.lsu_c2_m_clk @[lsu_lsc_ctl.scala 120:42]
+    addrcheck.io.start_addr_d <= full_addr_d @[lsu_lsc_ctl.scala 122:42]
+    addrcheck.io.end_addr_d <= full_end_addr_d @[lsu_lsc_ctl.scala 123:42]
+    addrcheck.io.lsu_pkt_d.bits.store_data_bypass_m <= io.lsu_pkt_d.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 124:42]
+    addrcheck.io.lsu_pkt_d.bits.load_ldst_bypass_d <= io.lsu_pkt_d.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 124:42]
+    addrcheck.io.lsu_pkt_d.bits.store_data_bypass_d <= io.lsu_pkt_d.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 124:42]
+    addrcheck.io.lsu_pkt_d.bits.dma <= io.lsu_pkt_d.bits.dma @[lsu_lsc_ctl.scala 124:42]
+    addrcheck.io.lsu_pkt_d.bits.unsign <= io.lsu_pkt_d.bits.unsign @[lsu_lsc_ctl.scala 124:42]
+    addrcheck.io.lsu_pkt_d.bits.store <= io.lsu_pkt_d.bits.store @[lsu_lsc_ctl.scala 124:42]
+    addrcheck.io.lsu_pkt_d.bits.load <= io.lsu_pkt_d.bits.load @[lsu_lsc_ctl.scala 124:42]
+    addrcheck.io.lsu_pkt_d.bits.dword <= io.lsu_pkt_d.bits.dword @[lsu_lsc_ctl.scala 124:42]
+    addrcheck.io.lsu_pkt_d.bits.word <= io.lsu_pkt_d.bits.word @[lsu_lsc_ctl.scala 124:42]
+    addrcheck.io.lsu_pkt_d.bits.half <= io.lsu_pkt_d.bits.half @[lsu_lsc_ctl.scala 124:42]
+    addrcheck.io.lsu_pkt_d.bits.by <= io.lsu_pkt_d.bits.by @[lsu_lsc_ctl.scala 124:42]
+    addrcheck.io.lsu_pkt_d.bits.stack <= io.lsu_pkt_d.bits.stack @[lsu_lsc_ctl.scala 124:42]
+    addrcheck.io.lsu_pkt_d.bits.fast_int <= io.lsu_pkt_d.bits.fast_int @[lsu_lsc_ctl.scala 124:42]
+    addrcheck.io.lsu_pkt_d.valid <= io.lsu_pkt_d.valid @[lsu_lsc_ctl.scala 124:42]
+    addrcheck.io.dec_tlu_mrac_ff <= io.dec_tlu_mrac_ff @[lsu_lsc_ctl.scala 125:42]
+    node _T_67 = bits(rs1_d, 31, 28) @[lsu_lsc_ctl.scala 126:50]
+    addrcheck.io.rs1_region_d <= _T_67 @[lsu_lsc_ctl.scala 126:42]
+    addrcheck.io.rs1_d <= rs1_d @[lsu_lsc_ctl.scala 127:42]
+    io.is_sideeffects_m <= addrcheck.io.is_sideeffects_m @[lsu_lsc_ctl.scala 128:42]
+    io.addr_in_dccm_d <= addrcheck.io.addr_in_dccm_d @[lsu_lsc_ctl.scala 129:42]
+    io.addr_in_pic_d <= addrcheck.io.addr_in_pic_d @[lsu_lsc_ctl.scala 130:42]
+    addrcheck.io.scan_mode <= io.scan_mode @[lsu_lsc_ctl.scala 137:42]
+    wire exc_mscause_r : UInt<4>
+    exc_mscause_r <= UInt<4>("h00")
+    wire fir_dccm_access_error_r : UInt<1>
+    fir_dccm_access_error_r <= UInt<1>("h00")
+    wire fir_nondccm_access_error_r : UInt<1>
+    fir_nondccm_access_error_r <= UInt<1>("h00")
+    wire access_fault_r : UInt<1>
+    access_fault_r <= UInt<1>("h00")
+    wire misaligned_fault_r : UInt<1>
+    misaligned_fault_r <= UInt<1>("h00")
+    wire lsu_fir_error_m : UInt<2>
+    lsu_fir_error_m <= UInt<2>("h00")
+    wire fir_dccm_access_error_m : UInt<1>
+    fir_dccm_access_error_m <= UInt<1>("h00")
+    wire fir_nondccm_access_error_m : UInt<1>
+    fir_nondccm_access_error_m <= UInt<1>("h00")
+    reg access_fault_m : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 149:75]
+    access_fault_m <= addrcheck.io.access_fault_d @[lsu_lsc_ctl.scala 149:75]
+    reg misaligned_fault_m : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 150:75]
+    misaligned_fault_m <= addrcheck.io.misaligned_fault_d @[lsu_lsc_ctl.scala 150:75]
+    reg exc_mscause_m : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 151:75]
+    exc_mscause_m <= addrcheck.io.exc_mscause_d @[lsu_lsc_ctl.scala 151:75]
+    reg _T_68 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 152:75]
+    _T_68 <= addrcheck.io.fir_dccm_access_error_d @[lsu_lsc_ctl.scala 152:75]
+    fir_dccm_access_error_m <= _T_68 @[lsu_lsc_ctl.scala 152:38]
+    reg _T_69 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 153:75]
+    _T_69 <= addrcheck.io.fir_nondccm_access_error_d @[lsu_lsc_ctl.scala 153:75]
+    fir_nondccm_access_error_m <= _T_69 @[lsu_lsc_ctl.scala 153:38]
+    node _T_70 = or(access_fault_m, misaligned_fault_m) @[lsu_lsc_ctl.scala 155:34]
+    io.lsu_exc_m <= _T_70 @[lsu_lsc_ctl.scala 155:16]
+    node _T_71 = eq(io.lsu_double_ecc_error_r, UInt<1>("h00")) @[lsu_lsc_ctl.scala 156:64]
+    node _T_72 = and(io.lsu_single_ecc_error_r, _T_71) @[lsu_lsc_ctl.scala 156:62]
+    node _T_73 = or(io.lsu_commit_r, io.lsu_pkt_r.bits.dma) @[lsu_lsc_ctl.scala 156:111]
+    node _T_74 = and(_T_72, _T_73) @[lsu_lsc_ctl.scala 156:92]
+    node _T_75 = and(_T_74, io.lsu_pkt_r.valid) @[lsu_lsc_ctl.scala 156:136]
+    io.lsu_single_ecc_error_incr <= _T_75 @[lsu_lsc_ctl.scala 156:32]
+    node _T_76 = or(access_fault_r, misaligned_fault_r) @[lsu_lsc_ctl.scala 160:49]
+    node _T_77 = or(_T_76, io.lsu_double_ecc_error_r) @[lsu_lsc_ctl.scala 160:70]
+    node _T_78 = and(_T_77, io.lsu_pkt_r.valid) @[lsu_lsc_ctl.scala 160:99]
+    node _T_79 = eq(io.lsu_pkt_r.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 160:122]
+    node _T_80 = and(_T_78, _T_79) @[lsu_lsc_ctl.scala 160:120]
+    node _T_81 = eq(io.lsu_pkt_r.bits.fast_int, UInt<1>("h00")) @[lsu_lsc_ctl.scala 160:147]
+    node _T_82 = and(_T_80, _T_81) @[lsu_lsc_ctl.scala 160:145]
+    io.lsu_error_pkt_r.valid <= _T_82 @[lsu_lsc_ctl.scala 160:30]
+    node _T_83 = eq(io.lsu_error_pkt_r.valid, UInt<1>("h00")) @[lsu_lsc_ctl.scala 161:77]
+    node _T_84 = and(io.lsu_single_ecc_error_r, _T_83) @[lsu_lsc_ctl.scala 161:75]
+    node _T_85 = eq(io.lsu_pkt_r.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 161:105]
+    node _T_86 = and(_T_84, _T_85) @[lsu_lsc_ctl.scala 161:103]
+    io.lsu_error_pkt_r.bits.single_ecc_error <= _T_86 @[lsu_lsc_ctl.scala 161:46]
+    io.lsu_error_pkt_r.bits.inst_type <= io.lsu_pkt_r.bits.store @[lsu_lsc_ctl.scala 162:39]
+    node _T_87 = not(misaligned_fault_r) @[lsu_lsc_ctl.scala 163:42]
+    io.lsu_error_pkt_r.bits.exc_type <= _T_87 @[lsu_lsc_ctl.scala 163:39]
+    node _T_88 = eq(misaligned_fault_r, UInt<1>("h00")) @[lsu_lsc_ctl.scala 164:75]
+    node _T_89 = and(io.lsu_double_ecc_error_r, _T_88) @[lsu_lsc_ctl.scala 164:73]
+    node _T_90 = eq(access_fault_r, UInt<1>("h00")) @[lsu_lsc_ctl.scala 164:97]
+    node _T_91 = and(_T_89, _T_90) @[lsu_lsc_ctl.scala 164:95]
+    node _T_92 = bits(_T_91, 0, 0) @[lsu_lsc_ctl.scala 164:114]
+    node _T_93 = bits(exc_mscause_r, 3, 0) @[lsu_lsc_ctl.scala 164:144]
+    node _T_94 = mux(_T_92, UInt<4>("h01"), _T_93) @[lsu_lsc_ctl.scala 164:45]
+    io.lsu_error_pkt_r.bits.mscause <= _T_94 @[lsu_lsc_ctl.scala 164:39]
+    node _T_95 = bits(io.lsu_addr_r, 31, 0) @[lsu_lsc_ctl.scala 165:55]
+    io.lsu_error_pkt_r.bits.addr <= _T_95 @[lsu_lsc_ctl.scala 165:39]
+    node _T_96 = bits(fir_nondccm_access_error_r, 0, 0) @[lsu_lsc_ctl.scala 166:68]
+    node _T_97 = bits(fir_dccm_access_error_r, 0, 0) @[lsu_lsc_ctl.scala 166:113]
+    node _T_98 = and(io.lsu_pkt_r.bits.fast_int, io.lsu_double_ecc_error_r) @[lsu_lsc_ctl.scala 166:162]
+    node _T_99 = bits(_T_98, 0, 0) @[lsu_lsc_ctl.scala 166:191]
+    node _T_100 = mux(_T_99, UInt<2>("h01"), UInt<2>("h00")) @[lsu_lsc_ctl.scala 166:133]
+    node _T_101 = mux(_T_97, UInt<2>("h02"), _T_100) @[lsu_lsc_ctl.scala 166:88]
+    node _T_102 = mux(_T_96, UInt<2>("h03"), _T_101) @[lsu_lsc_ctl.scala 166:40]
+    io.lsu_fir_error <= _T_102 @[lsu_lsc_ctl.scala 166:34]
+    reg _T_103 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 168:71]
+    _T_103 <= access_fault_m @[lsu_lsc_ctl.scala 168:71]
+    access_fault_r <= _T_103 @[lsu_lsc_ctl.scala 168:34]
+    reg _T_104 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 169:71]
+    _T_104 <= exc_mscause_m @[lsu_lsc_ctl.scala 169:71]
+    exc_mscause_r <= _T_104 @[lsu_lsc_ctl.scala 169:34]
+    reg _T_105 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 170:71]
+    _T_105 <= fir_dccm_access_error_m @[lsu_lsc_ctl.scala 170:71]
+    fir_dccm_access_error_r <= _T_105 @[lsu_lsc_ctl.scala 170:34]
+    reg _T_106 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 171:71]
+    _T_106 <= fir_nondccm_access_error_m @[lsu_lsc_ctl.scala 171:71]
+    fir_nondccm_access_error_r <= _T_106 @[lsu_lsc_ctl.scala 171:34]
+    reg _T_107 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 172:71]
+    _T_107 <= misaligned_fault_m @[lsu_lsc_ctl.scala 172:71]
+    misaligned_fault_r <= _T_107 @[lsu_lsc_ctl.scala 172:34]
+    dma_pkt_d.bits.unsign <= UInt<1>("h00") @[lsu_lsc_ctl.scala 190:27]
+    dma_pkt_d.bits.stack <= UInt<1>("h00") @[lsu_lsc_ctl.scala 191:26]
+    dma_pkt_d.bits.fast_int <= UInt<1>("h00") @[lsu_lsc_ctl.scala 192:27]
+    dma_pkt_d.valid <= io.dma_lsc_ctl.dma_dccm_req @[lsu_lsc_ctl.scala 193:22]
+    dma_pkt_d.bits.dma <= UInt<1>("h01") @[lsu_lsc_ctl.scala 194:27]
+    dma_pkt_d.bits.store <= io.dma_lsc_ctl.dma_mem_write @[lsu_lsc_ctl.scala 195:27]
+    node _T_108 = not(io.dma_lsc_ctl.dma_mem_write) @[lsu_lsc_ctl.scala 196:30]
+    dma_pkt_d.bits.load <= _T_108 @[lsu_lsc_ctl.scala 196:27]
+    node _T_109 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 197:56]
+    node _T_110 = eq(_T_109, UInt<3>("h00")) @[lsu_lsc_ctl.scala 197:62]
+    dma_pkt_d.bits.by <= _T_110 @[lsu_lsc_ctl.scala 197:27]
+    node _T_111 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 198:56]
+    node _T_112 = eq(_T_111, UInt<3>("h01")) @[lsu_lsc_ctl.scala 198:62]
+    dma_pkt_d.bits.half <= _T_112 @[lsu_lsc_ctl.scala 198:27]
+    node _T_113 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 199:56]
+    node _T_114 = eq(_T_113, UInt<3>("h02")) @[lsu_lsc_ctl.scala 199:62]
+    dma_pkt_d.bits.word <= _T_114 @[lsu_lsc_ctl.scala 199:27]
+    node _T_115 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 200:56]
+    node _T_116 = eq(_T_115, UInt<3>("h03")) @[lsu_lsc_ctl.scala 200:62]
+    dma_pkt_d.bits.dword <= _T_116 @[lsu_lsc_ctl.scala 200:27]
+    dma_pkt_d.bits.store_data_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 201:39]
+    dma_pkt_d.bits.load_ldst_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 202:39]
+    dma_pkt_d.bits.store_data_bypass_m <= UInt<1>("h00") @[lsu_lsc_ctl.scala 203:39]
+    wire lsu_ld_datafn_r : UInt<32>
+    lsu_ld_datafn_r <= UInt<32>("h00")
+    wire lsu_ld_datafn_corr_r : UInt<32>
+    lsu_ld_datafn_corr_r <= UInt<32>("h00")
+    wire lsu_ld_datafn_m : UInt<32>
+    lsu_ld_datafn_m <= UInt<32>("h00")
+    node _T_117 = bits(io.dec_lsu_valid_raw_d, 0, 0) @[lsu_lsc_ctl.scala 209:50]
+    node _T_118 = mux(_T_117, io.lsu_p, dma_pkt_d) @[lsu_lsc_ctl.scala 209:26]
+    io.lsu_pkt_d.bits.store_data_bypass_m <= _T_118.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 209:20]
+    io.lsu_pkt_d.bits.load_ldst_bypass_d <= _T_118.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 209:20]
+    io.lsu_pkt_d.bits.store_data_bypass_d <= _T_118.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 209:20]
+    io.lsu_pkt_d.bits.dma <= _T_118.bits.dma @[lsu_lsc_ctl.scala 209:20]
+    io.lsu_pkt_d.bits.unsign <= _T_118.bits.unsign @[lsu_lsc_ctl.scala 209:20]
+    io.lsu_pkt_d.bits.store <= _T_118.bits.store @[lsu_lsc_ctl.scala 209:20]
+    io.lsu_pkt_d.bits.load <= _T_118.bits.load @[lsu_lsc_ctl.scala 209:20]
+    io.lsu_pkt_d.bits.dword <= _T_118.bits.dword @[lsu_lsc_ctl.scala 209:20]
+    io.lsu_pkt_d.bits.word <= _T_118.bits.word @[lsu_lsc_ctl.scala 209:20]
+    io.lsu_pkt_d.bits.half <= _T_118.bits.half @[lsu_lsc_ctl.scala 209:20]
+    io.lsu_pkt_d.bits.by <= _T_118.bits.by @[lsu_lsc_ctl.scala 209:20]
+    io.lsu_pkt_d.bits.stack <= _T_118.bits.stack @[lsu_lsc_ctl.scala 209:20]
+    io.lsu_pkt_d.bits.fast_int <= _T_118.bits.fast_int @[lsu_lsc_ctl.scala 209:20]
+    io.lsu_pkt_d.valid <= _T_118.valid @[lsu_lsc_ctl.scala 209:20]
+    lsu_pkt_m_in.bits.store_data_bypass_m <= io.lsu_pkt_d.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 210:20]
+    lsu_pkt_m_in.bits.load_ldst_bypass_d <= io.lsu_pkt_d.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 210:20]
+    lsu_pkt_m_in.bits.store_data_bypass_d <= io.lsu_pkt_d.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 210:20]
+    lsu_pkt_m_in.bits.dma <= io.lsu_pkt_d.bits.dma @[lsu_lsc_ctl.scala 210:20]
+    lsu_pkt_m_in.bits.unsign <= io.lsu_pkt_d.bits.unsign @[lsu_lsc_ctl.scala 210:20]
+    lsu_pkt_m_in.bits.store <= io.lsu_pkt_d.bits.store @[lsu_lsc_ctl.scala 210:20]
+    lsu_pkt_m_in.bits.load <= io.lsu_pkt_d.bits.load @[lsu_lsc_ctl.scala 210:20]
+    lsu_pkt_m_in.bits.dword <= io.lsu_pkt_d.bits.dword @[lsu_lsc_ctl.scala 210:20]
+    lsu_pkt_m_in.bits.word <= io.lsu_pkt_d.bits.word @[lsu_lsc_ctl.scala 210:20]
+    lsu_pkt_m_in.bits.half <= io.lsu_pkt_d.bits.half @[lsu_lsc_ctl.scala 210:20]
+    lsu_pkt_m_in.bits.by <= io.lsu_pkt_d.bits.by @[lsu_lsc_ctl.scala 210:20]
+    lsu_pkt_m_in.bits.stack <= io.lsu_pkt_d.bits.stack @[lsu_lsc_ctl.scala 210:20]
+    lsu_pkt_m_in.bits.fast_int <= io.lsu_pkt_d.bits.fast_int @[lsu_lsc_ctl.scala 210:20]
+    lsu_pkt_m_in.valid <= io.lsu_pkt_d.valid @[lsu_lsc_ctl.scala 210:20]
+    lsu_pkt_r_in.bits.store_data_bypass_m <= io.lsu_pkt_m.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 211:20]
+    lsu_pkt_r_in.bits.load_ldst_bypass_d <= io.lsu_pkt_m.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 211:20]
+    lsu_pkt_r_in.bits.store_data_bypass_d <= io.lsu_pkt_m.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 211:20]
+    lsu_pkt_r_in.bits.dma <= io.lsu_pkt_m.bits.dma @[lsu_lsc_ctl.scala 211:20]
+    lsu_pkt_r_in.bits.unsign <= io.lsu_pkt_m.bits.unsign @[lsu_lsc_ctl.scala 211:20]
+    lsu_pkt_r_in.bits.store <= io.lsu_pkt_m.bits.store @[lsu_lsc_ctl.scala 211:20]
+    lsu_pkt_r_in.bits.load <= io.lsu_pkt_m.bits.load @[lsu_lsc_ctl.scala 211:20]
+    lsu_pkt_r_in.bits.dword <= io.lsu_pkt_m.bits.dword @[lsu_lsc_ctl.scala 211:20]
+    lsu_pkt_r_in.bits.word <= io.lsu_pkt_m.bits.word @[lsu_lsc_ctl.scala 211:20]
+    lsu_pkt_r_in.bits.half <= io.lsu_pkt_m.bits.half @[lsu_lsc_ctl.scala 211:20]
+    lsu_pkt_r_in.bits.by <= io.lsu_pkt_m.bits.by @[lsu_lsc_ctl.scala 211:20]
+    lsu_pkt_r_in.bits.stack <= io.lsu_pkt_m.bits.stack @[lsu_lsc_ctl.scala 211:20]
+    lsu_pkt_r_in.bits.fast_int <= io.lsu_pkt_m.bits.fast_int @[lsu_lsc_ctl.scala 211:20]
+    lsu_pkt_r_in.valid <= io.lsu_pkt_m.valid @[lsu_lsc_ctl.scala 211:20]
+    node _T_119 = eq(io.lsu_p.bits.fast_int, UInt<1>("h00")) @[lsu_lsc_ctl.scala 213:64]
+    node _T_120 = and(io.flush_m_up, _T_119) @[lsu_lsc_ctl.scala 213:61]
+    node _T_121 = eq(_T_120, UInt<1>("h00")) @[lsu_lsc_ctl.scala 213:45]
+    node _T_122 = and(io.lsu_p.valid, _T_121) @[lsu_lsc_ctl.scala 213:43]
+    node _T_123 = or(_T_122, io.dma_lsc_ctl.dma_dccm_req) @[lsu_lsc_ctl.scala 213:90]
+    io.lsu_pkt_d.valid <= _T_123 @[lsu_lsc_ctl.scala 213:24]
+    node _T_124 = eq(io.lsu_pkt_d.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 214:68]
+    node _T_125 = and(io.flush_m_up, _T_124) @[lsu_lsc_ctl.scala 214:65]
+    node _T_126 = eq(_T_125, UInt<1>("h00")) @[lsu_lsc_ctl.scala 214:49]
+    node _T_127 = and(io.lsu_pkt_d.valid, _T_126) @[lsu_lsc_ctl.scala 214:47]
+    lsu_pkt_m_in.valid <= _T_127 @[lsu_lsc_ctl.scala 214:24]
+    node _T_128 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 215:68]
+    node _T_129 = and(io.flush_m_up, _T_128) @[lsu_lsc_ctl.scala 215:65]
+    node _T_130 = eq(_T_129, UInt<1>("h00")) @[lsu_lsc_ctl.scala 215:49]
+    node _T_131 = and(io.lsu_pkt_m.valid, _T_130) @[lsu_lsc_ctl.scala 215:47]
+    lsu_pkt_r_in.valid <= _T_131 @[lsu_lsc_ctl.scala 215:24]
+    wire _T_132 : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 217:91]
+    _T_132.bits.store_data_bypass_m <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
+    _T_132.bits.load_ldst_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
+    _T_132.bits.store_data_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
+    _T_132.bits.dma <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
+    _T_132.bits.unsign <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
+    _T_132.bits.store <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
+    _T_132.bits.load <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
+    _T_132.bits.dword <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
+    _T_132.bits.word <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
+    _T_132.bits.half <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
+    _T_132.bits.by <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
+    _T_132.bits.stack <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
+    _T_132.bits.fast_int <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
+    _T_132.valid <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
+    reg _T_133 : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, io.lsu_c1_m_clk with : (reset => (reset, _T_132)) @[lsu_lsc_ctl.scala 217:65]
+    _T_133.bits.store_data_bypass_m <= lsu_pkt_m_in.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 217:65]
+    _T_133.bits.load_ldst_bypass_d <= lsu_pkt_m_in.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 217:65]
+    _T_133.bits.store_data_bypass_d <= lsu_pkt_m_in.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 217:65]
+    _T_133.bits.dma <= lsu_pkt_m_in.bits.dma @[lsu_lsc_ctl.scala 217:65]
+    _T_133.bits.unsign <= lsu_pkt_m_in.bits.unsign @[lsu_lsc_ctl.scala 217:65]
+    _T_133.bits.store <= lsu_pkt_m_in.bits.store @[lsu_lsc_ctl.scala 217:65]
+    _T_133.bits.load <= lsu_pkt_m_in.bits.load @[lsu_lsc_ctl.scala 217:65]
+    _T_133.bits.dword <= lsu_pkt_m_in.bits.dword @[lsu_lsc_ctl.scala 217:65]
+    _T_133.bits.word <= lsu_pkt_m_in.bits.word @[lsu_lsc_ctl.scala 217:65]
+    _T_133.bits.half <= lsu_pkt_m_in.bits.half @[lsu_lsc_ctl.scala 217:65]
+    _T_133.bits.by <= lsu_pkt_m_in.bits.by @[lsu_lsc_ctl.scala 217:65]
+    _T_133.bits.stack <= lsu_pkt_m_in.bits.stack @[lsu_lsc_ctl.scala 217:65]
+    _T_133.bits.fast_int <= lsu_pkt_m_in.bits.fast_int @[lsu_lsc_ctl.scala 217:65]
+    _T_133.valid <= lsu_pkt_m_in.valid @[lsu_lsc_ctl.scala 217:65]
+    io.lsu_pkt_m.bits.store_data_bypass_m <= _T_133.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 217:28]
+    io.lsu_pkt_m.bits.load_ldst_bypass_d <= _T_133.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 217:28]
+    io.lsu_pkt_m.bits.store_data_bypass_d <= _T_133.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 217:28]
+    io.lsu_pkt_m.bits.dma <= _T_133.bits.dma @[lsu_lsc_ctl.scala 217:28]
+    io.lsu_pkt_m.bits.unsign <= _T_133.bits.unsign @[lsu_lsc_ctl.scala 217:28]
+    io.lsu_pkt_m.bits.store <= _T_133.bits.store @[lsu_lsc_ctl.scala 217:28]
+    io.lsu_pkt_m.bits.load <= _T_133.bits.load @[lsu_lsc_ctl.scala 217:28]
+    io.lsu_pkt_m.bits.dword <= _T_133.bits.dword @[lsu_lsc_ctl.scala 217:28]
+    io.lsu_pkt_m.bits.word <= _T_133.bits.word @[lsu_lsc_ctl.scala 217:28]
+    io.lsu_pkt_m.bits.half <= _T_133.bits.half @[lsu_lsc_ctl.scala 217:28]
+    io.lsu_pkt_m.bits.by <= _T_133.bits.by @[lsu_lsc_ctl.scala 217:28]
+    io.lsu_pkt_m.bits.stack <= _T_133.bits.stack @[lsu_lsc_ctl.scala 217:28]
+    io.lsu_pkt_m.bits.fast_int <= _T_133.bits.fast_int @[lsu_lsc_ctl.scala 217:28]
+    io.lsu_pkt_m.valid <= _T_133.valid @[lsu_lsc_ctl.scala 217:28]
+    wire _T_134 : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 218:91]
+    _T_134.bits.store_data_bypass_m <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91]
+    _T_134.bits.load_ldst_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91]
+    _T_134.bits.store_data_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91]
+    _T_134.bits.dma <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91]
+    _T_134.bits.unsign <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91]
+    _T_134.bits.store <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91]
+    _T_134.bits.load <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91]
+    _T_134.bits.dword <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91]
+    _T_134.bits.word <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91]
+    _T_134.bits.half <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91]
+    _T_134.bits.by <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91]
+    _T_134.bits.stack <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91]
+    _T_134.bits.fast_int <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91]
+    _T_134.valid <= UInt<1>("h00") @[lsu_lsc_ctl.scala 218:91]
+    reg _T_135 : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, io.lsu_c1_r_clk with : (reset => (reset, _T_134)) @[lsu_lsc_ctl.scala 218:65]
+    _T_135.bits.store_data_bypass_m <= lsu_pkt_r_in.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 218:65]
+    _T_135.bits.load_ldst_bypass_d <= lsu_pkt_r_in.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 218:65]
+    _T_135.bits.store_data_bypass_d <= lsu_pkt_r_in.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 218:65]
+    _T_135.bits.dma <= lsu_pkt_r_in.bits.dma @[lsu_lsc_ctl.scala 218:65]
+    _T_135.bits.unsign <= lsu_pkt_r_in.bits.unsign @[lsu_lsc_ctl.scala 218:65]
+    _T_135.bits.store <= lsu_pkt_r_in.bits.store @[lsu_lsc_ctl.scala 218:65]
+    _T_135.bits.load <= lsu_pkt_r_in.bits.load @[lsu_lsc_ctl.scala 218:65]
+    _T_135.bits.dword <= lsu_pkt_r_in.bits.dword @[lsu_lsc_ctl.scala 218:65]
+    _T_135.bits.word <= lsu_pkt_r_in.bits.word @[lsu_lsc_ctl.scala 218:65]
+    _T_135.bits.half <= lsu_pkt_r_in.bits.half @[lsu_lsc_ctl.scala 218:65]
+    _T_135.bits.by <= lsu_pkt_r_in.bits.by @[lsu_lsc_ctl.scala 218:65]
+    _T_135.bits.stack <= lsu_pkt_r_in.bits.stack @[lsu_lsc_ctl.scala 218:65]
+    _T_135.bits.fast_int <= lsu_pkt_r_in.bits.fast_int @[lsu_lsc_ctl.scala 218:65]
+    _T_135.valid <= lsu_pkt_r_in.valid @[lsu_lsc_ctl.scala 218:65]
+    io.lsu_pkt_r.bits.store_data_bypass_m <= _T_135.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 218:28]
+    io.lsu_pkt_r.bits.load_ldst_bypass_d <= _T_135.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 218:28]
+    io.lsu_pkt_r.bits.store_data_bypass_d <= _T_135.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 218:28]
+    io.lsu_pkt_r.bits.dma <= _T_135.bits.dma @[lsu_lsc_ctl.scala 218:28]
+    io.lsu_pkt_r.bits.unsign <= _T_135.bits.unsign @[lsu_lsc_ctl.scala 218:28]
+    io.lsu_pkt_r.bits.store <= _T_135.bits.store @[lsu_lsc_ctl.scala 218:28]
+    io.lsu_pkt_r.bits.load <= _T_135.bits.load @[lsu_lsc_ctl.scala 218:28]
+    io.lsu_pkt_r.bits.dword <= _T_135.bits.dword @[lsu_lsc_ctl.scala 218:28]
+    io.lsu_pkt_r.bits.word <= _T_135.bits.word @[lsu_lsc_ctl.scala 218:28]
+    io.lsu_pkt_r.bits.half <= _T_135.bits.half @[lsu_lsc_ctl.scala 218:28]
+    io.lsu_pkt_r.bits.by <= _T_135.bits.by @[lsu_lsc_ctl.scala 218:28]
+    io.lsu_pkt_r.bits.stack <= _T_135.bits.stack @[lsu_lsc_ctl.scala 218:28]
+    io.lsu_pkt_r.bits.fast_int <= _T_135.bits.fast_int @[lsu_lsc_ctl.scala 218:28]
+    io.lsu_pkt_r.valid <= _T_135.valid @[lsu_lsc_ctl.scala 218:28]
+    reg _T_136 : UInt<1>, io.lsu_c2_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 219:65]
+    _T_136 <= lsu_pkt_m_in.valid @[lsu_lsc_ctl.scala 219:65]
+    io.lsu_pkt_m.valid <= _T_136 @[lsu_lsc_ctl.scala 219:28]
+    reg _T_137 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 220:65]
+    _T_137 <= lsu_pkt_r_in.valid @[lsu_lsc_ctl.scala 220:65]
+    io.lsu_pkt_r.valid <= _T_137 @[lsu_lsc_ctl.scala 220:28]
+    node _T_138 = bits(io.dma_lsc_ctl.dma_mem_wdata, 63, 0) @[lsu_lsc_ctl.scala 222:59]
+    node _T_139 = bits(io.dma_lsc_ctl.dma_mem_addr, 2, 0) @[lsu_lsc_ctl.scala 222:100]
+    node _T_140 = cat(_T_139, UInt<3>("h00")) @[Cat.scala 29:58]
+    node dma_mem_wdata_shifted = dshr(_T_138, _T_140) @[lsu_lsc_ctl.scala 222:66]
+    node _T_141 = bits(io.dma_lsc_ctl.dma_dccm_req, 0, 0) @[lsu_lsc_ctl.scala 223:63]
+    node _T_142 = bits(dma_mem_wdata_shifted, 31, 0) @[lsu_lsc_ctl.scala 223:91]
+    node _T_143 = bits(io.lsu_exu.exu_lsu_rs2_d, 31, 0) @[lsu_lsc_ctl.scala 223:122]
+    node store_data_d = mux(_T_141, _T_142, _T_143) @[lsu_lsc_ctl.scala 223:34]
+    node _T_144 = bits(io.lsu_pkt_d.bits.store_data_bypass_d, 0, 0) @[lsu_lsc_ctl.scala 224:73]
+    node _T_145 = bits(io.lsu_result_m, 31, 0) @[lsu_lsc_ctl.scala 224:95]
+    node _T_146 = bits(store_data_d, 31, 0) @[lsu_lsc_ctl.scala 224:114]
+    node store_data_m_in = mux(_T_144, _T_145, _T_146) @[lsu_lsc_ctl.scala 224:34]
+    reg store_data_pre_m : UInt, io.lsu_store_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 226:72]
+    store_data_pre_m <= store_data_m_in @[lsu_lsc_ctl.scala 226:72]
+    reg _T_147 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 227:62]
+    _T_147 <= io.lsu_addr_d @[lsu_lsc_ctl.scala 227:62]
+    io.lsu_addr_m <= _T_147 @[lsu_lsc_ctl.scala 227:24]
+    reg _T_148 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 228:62]
+    _T_148 <= io.lsu_addr_m @[lsu_lsc_ctl.scala 228:62]
+    io.lsu_addr_r <= _T_148 @[lsu_lsc_ctl.scala 228:24]
+    node _T_149 = bits(io.ldst_dual_m, 0, 0) @[lib.scala 8:44]
+    node _T_150 = bits(io.lsu_addr_m, 31, 3) @[lsu_lsc_ctl.scala 229:71]
+    node _T_151 = mux(_T_149, end_addr_pre_m, _T_150) @[lsu_lsc_ctl.scala 229:27]
+    node _T_152 = bits(io.end_addr_d, 2, 0) @[lsu_lsc_ctl.scala 229:128]
+    reg _T_153 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 229:114]
+    _T_153 <= _T_152 @[lsu_lsc_ctl.scala 229:114]
+    node _T_154 = cat(_T_151, _T_153) @[Cat.scala 29:58]
+    io.end_addr_m <= _T_154 @[lsu_lsc_ctl.scala 229:17]
+    node _T_155 = bits(io.ldst_dual_r, 0, 0) @[lib.scala 8:44]
+    node _T_156 = bits(io.lsu_addr_r, 31, 3) @[lsu_lsc_ctl.scala 230:71]
+    node _T_157 = mux(_T_155, end_addr_pre_r, _T_156) @[lsu_lsc_ctl.scala 230:27]
+    node _T_158 = bits(io.end_addr_m, 2, 0) @[lsu_lsc_ctl.scala 230:128]
+    reg _T_159 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 230:114]
+    _T_159 <= _T_158 @[lsu_lsc_ctl.scala 230:114]
+    node _T_160 = cat(_T_157, _T_159) @[Cat.scala 29:58]
+    io.end_addr_r <= _T_160 @[lsu_lsc_ctl.scala 230:17]
+    node _T_161 = bits(io.end_addr_d, 31, 3) @[lsu_lsc_ctl.scala 231:41]
+    node _T_162 = and(io.lsu_pkt_d.valid, io.ldst_dual_d) @[lsu_lsc_ctl.scala 231:69]
+    node _T_163 = or(_T_162, io.clk_override) @[lsu_lsc_ctl.scala 231:87]
+    node _T_164 = bits(_T_163, 0, 0) @[lib.scala 8:44]
+    node _T_165 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44]
+    inst rvclkhdr of rvclkhdr @[lib.scala 390:23]
+    rvclkhdr.clock <= clock
+    rvclkhdr.reset <= reset
+    rvclkhdr.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr.io.en <= _T_164 @[lib.scala 393:17]
+    rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg _T_166 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_164 : @[Reg.scala 28:19]
+      _T_166 <= _T_161 @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    end_addr_pre_m <= _T_166 @[lsu_lsc_ctl.scala 231:18]
+    node _T_167 = bits(io.end_addr_m, 31, 3) @[lsu_lsc_ctl.scala 232:41]
+    node _T_168 = and(io.lsu_pkt_m.valid, io.ldst_dual_m) @[lsu_lsc_ctl.scala 232:69]
+    node _T_169 = or(_T_168, io.clk_override) @[lsu_lsc_ctl.scala 232:87]
+    node _T_170 = bits(_T_169, 0, 0) @[lib.scala 8:44]
+    node _T_171 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44]
+    inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 390:23]
+    rvclkhdr_1.clock <= clock
+    rvclkhdr_1.reset <= reset
+    rvclkhdr_1.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr_1.io.en <= _T_170 @[lib.scala 393:17]
+    rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg _T_172 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_170 : @[Reg.scala 28:19]
+      _T_172 <= _T_167 @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    end_addr_pre_r <= _T_172 @[lsu_lsc_ctl.scala 232:18]
+    reg _T_173 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 233:62]
+    _T_173 <= io.addr_in_dccm_d @[lsu_lsc_ctl.scala 233:62]
+    io.addr_in_dccm_m <= _T_173 @[lsu_lsc_ctl.scala 233:24]
+    reg _T_174 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 234:62]
+    _T_174 <= io.addr_in_dccm_m @[lsu_lsc_ctl.scala 234:62]
+    io.addr_in_dccm_r <= _T_174 @[lsu_lsc_ctl.scala 234:24]
+    reg _T_175 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 235:62]
+    _T_175 <= io.addr_in_pic_d @[lsu_lsc_ctl.scala 235:62]
+    io.addr_in_pic_m <= _T_175 @[lsu_lsc_ctl.scala 235:24]
+    reg _T_176 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 236:62]
+    _T_176 <= io.addr_in_pic_m @[lsu_lsc_ctl.scala 236:62]
+    io.addr_in_pic_r <= _T_176 @[lsu_lsc_ctl.scala 236:24]
+    reg _T_177 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 237:62]
+    _T_177 <= addrcheck.io.addr_external_d @[lsu_lsc_ctl.scala 237:62]
+    io.addr_external_m <= _T_177 @[lsu_lsc_ctl.scala 237:24]
+    reg addr_external_r : UInt<1>, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 238:66]
+    addr_external_r <= io.addr_external_m @[lsu_lsc_ctl.scala 238:66]
+    node _T_178 = or(io.addr_external_m, io.clk_override) @[lsu_lsc_ctl.scala 239:77]
+    node _T_179 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44]
+    inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 390:23]
+    rvclkhdr_2.clock <= clock
+    rvclkhdr_2.reset <= reset
+    rvclkhdr_2.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr_2.io.en <= _T_178 @[lib.scala 393:17]
+    rvclkhdr_2.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg bus_read_data_r : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_178 : @[Reg.scala 28:19]
+      bus_read_data_r <= io.bus_read_data_m @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    node _T_180 = bits(io.lsu_ld_data_corr_r, 31, 1) @[lsu_lsc_ctl.scala 242:52]
+    io.lsu_fir_addr <= _T_180 @[lsu_lsc_ctl.scala 242:28]
+    io.lsu_addr_d <= full_addr_d @[lsu_lsc_ctl.scala 244:28]
+    node _T_181 = or(io.lsu_pkt_r.bits.store, io.lsu_pkt_r.bits.load) @[lsu_lsc_ctl.scala 246:68]
+    node _T_182 = and(io.lsu_pkt_r.valid, _T_181) @[lsu_lsc_ctl.scala 246:41]
+    node _T_183 = eq(io.flush_r, UInt<1>("h00")) @[lsu_lsc_ctl.scala 246:96]
+    node _T_184 = and(_T_182, _T_183) @[lsu_lsc_ctl.scala 246:94]
+    node _T_185 = eq(io.lsu_pkt_r.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 246:110]
+    node _T_186 = and(_T_184, _T_185) @[lsu_lsc_ctl.scala 246:108]
+    io.lsu_commit_r <= _T_186 @[lsu_lsc_ctl.scala 246:19]
+    node _T_187 = bits(io.picm_mask_data_m, 31, 0) @[lsu_lsc_ctl.scala 247:52]
+    node _T_188 = eq(io.addr_in_pic_m, UInt<1>("h00")) @[lsu_lsc_ctl.scala 247:69]
+    node _T_189 = bits(_T_188, 0, 0) @[Bitwise.scala 72:15]
+    node _T_190 = mux(_T_189, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
+    node _T_191 = or(_T_187, _T_190) @[lsu_lsc_ctl.scala 247:59]
+    node _T_192 = bits(io.lsu_pkt_m.bits.store_data_bypass_m, 0, 0) @[lsu_lsc_ctl.scala 247:133]
+    node _T_193 = mux(_T_192, io.lsu_result_m, store_data_pre_m) @[lsu_lsc_ctl.scala 247:94]
+    node _T_194 = and(_T_191, _T_193) @[lsu_lsc_ctl.scala 247:89]
+    io.store_data_m <= _T_194 @[lsu_lsc_ctl.scala 247:29]
+    node _T_195 = bits(addr_external_r, 0, 0) @[lib.scala 8:44]
+    node _T_196 = mux(_T_195, bus_read_data_r, io.lsu_ld_data_r) @[lsu_lsc_ctl.scala 251:33]
+    lsu_ld_datafn_r <= _T_196 @[lsu_lsc_ctl.scala 251:27]
+    node _T_197 = bits(addr_external_r, 0, 0) @[lib.scala 8:44]
+    node _T_198 = mux(_T_197, bus_read_data_r, io.lsu_ld_data_corr_r) @[lsu_lsc_ctl.scala 252:33]
+    lsu_ld_datafn_corr_r <= _T_198 @[lsu_lsc_ctl.scala 252:27]
+    node _T_199 = and(io.lsu_pkt_r.bits.unsign, io.lsu_pkt_r.bits.by) @[lsu_lsc_ctl.scala 254:66]
+    node _T_200 = bits(_T_199, 0, 0) @[Bitwise.scala 72:15]
+    node _T_201 = mux(_T_200, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
+    node _T_202 = bits(lsu_ld_datafn_r, 7, 0) @[lsu_lsc_ctl.scala 254:125]
+    node _T_203 = cat(UInt<24>("h00"), _T_202) @[Cat.scala 29:58]
+    node _T_204 = and(_T_201, _T_203) @[lsu_lsc_ctl.scala 254:94]
+    node _T_205 = and(io.lsu_pkt_r.bits.unsign, io.lsu_pkt_r.bits.half) @[lsu_lsc_ctl.scala 255:43]
+    node _T_206 = bits(_T_205, 0, 0) @[Bitwise.scala 72:15]
+    node _T_207 = mux(_T_206, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
+    node _T_208 = bits(lsu_ld_datafn_r, 15, 0) @[lsu_lsc_ctl.scala 255:102]
+    node _T_209 = cat(UInt<16>("h00"), _T_208) @[Cat.scala 29:58]
+    node _T_210 = and(_T_207, _T_209) @[lsu_lsc_ctl.scala 255:71]
+    node _T_211 = or(_T_204, _T_210) @[lsu_lsc_ctl.scala 254:133]
+    node _T_212 = eq(io.lsu_pkt_r.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 256:17]
+    node _T_213 = and(_T_212, io.lsu_pkt_r.bits.by) @[lsu_lsc_ctl.scala 256:43]
+    node _T_214 = bits(_T_213, 0, 0) @[Bitwise.scala 72:15]
+    node _T_215 = mux(_T_214, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
+    node _T_216 = bits(lsu_ld_datafn_r, 7, 7) @[lsu_lsc_ctl.scala 256:102]
+    node _T_217 = bits(_T_216, 0, 0) @[Bitwise.scala 72:15]
+    node _T_218 = mux(_T_217, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12]
+    node _T_219 = bits(lsu_ld_datafn_r, 7, 0) @[lsu_lsc_ctl.scala 256:125]
+    node _T_220 = cat(_T_218, _T_219) @[Cat.scala 29:58]
+    node _T_221 = and(_T_215, _T_220) @[lsu_lsc_ctl.scala 256:71]
+    node _T_222 = or(_T_211, _T_221) @[lsu_lsc_ctl.scala 255:114]
+    node _T_223 = eq(io.lsu_pkt_r.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 257:17]
+    node _T_224 = and(_T_223, io.lsu_pkt_r.bits.half) @[lsu_lsc_ctl.scala 257:43]
+    node _T_225 = bits(_T_224, 0, 0) @[Bitwise.scala 72:15]
+    node _T_226 = mux(_T_225, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
+    node _T_227 = bits(lsu_ld_datafn_r, 15, 15) @[lsu_lsc_ctl.scala 257:101]
+    node _T_228 = bits(_T_227, 0, 0) @[Bitwise.scala 72:15]
+    node _T_229 = mux(_T_228, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12]
+    node _T_230 = bits(lsu_ld_datafn_r, 15, 0) @[lsu_lsc_ctl.scala 257:125]
+    node _T_231 = cat(_T_229, _T_230) @[Cat.scala 29:58]
+    node _T_232 = and(_T_226, _T_231) @[lsu_lsc_ctl.scala 257:71]
+    node _T_233 = or(_T_222, _T_232) @[lsu_lsc_ctl.scala 256:134]
+    node _T_234 = bits(io.lsu_pkt_r.bits.word, 0, 0) @[Bitwise.scala 72:15]
+    node _T_235 = mux(_T_234, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
+    node _T_236 = bits(lsu_ld_datafn_r, 31, 0) @[lsu_lsc_ctl.scala 258:60]
+    node _T_237 = and(_T_235, _T_236) @[lsu_lsc_ctl.scala 258:43]
+    node _T_238 = or(_T_233, _T_237) @[lsu_lsc_ctl.scala 257:134]
+    io.lsu_result_m <= _T_238 @[lsu_lsc_ctl.scala 254:27]
+    node _T_239 = and(io.lsu_pkt_r.bits.unsign, io.lsu_pkt_r.bits.by) @[lsu_lsc_ctl.scala 260:66]
+    node _T_240 = bits(_T_239, 0, 0) @[Bitwise.scala 72:15]
+    node _T_241 = mux(_T_240, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
+    node _T_242 = bits(lsu_ld_datafn_corr_r, 7, 0) @[lsu_lsc_ctl.scala 260:130]
+    node _T_243 = cat(UInt<24>("h00"), _T_242) @[Cat.scala 29:58]
+    node _T_244 = and(_T_241, _T_243) @[lsu_lsc_ctl.scala 260:94]
+    node _T_245 = and(io.lsu_pkt_r.bits.unsign, io.lsu_pkt_r.bits.half) @[lsu_lsc_ctl.scala 261:43]
+    node _T_246 = bits(_T_245, 0, 0) @[Bitwise.scala 72:15]
+    node _T_247 = mux(_T_246, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
+    node _T_248 = bits(lsu_ld_datafn_corr_r, 15, 0) @[lsu_lsc_ctl.scala 261:107]
+    node _T_249 = cat(UInt<16>("h00"), _T_248) @[Cat.scala 29:58]
+    node _T_250 = and(_T_247, _T_249) @[lsu_lsc_ctl.scala 261:71]
+    node _T_251 = or(_T_244, _T_250) @[lsu_lsc_ctl.scala 260:138]
+    node _T_252 = eq(io.lsu_pkt_r.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 262:17]
+    node _T_253 = and(_T_252, io.lsu_pkt_r.bits.by) @[lsu_lsc_ctl.scala 262:43]
+    node _T_254 = bits(_T_253, 0, 0) @[Bitwise.scala 72:15]
+    node _T_255 = mux(_T_254, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
+    node _T_256 = bits(lsu_ld_datafn_corr_r, 7, 7) @[lsu_lsc_ctl.scala 262:107]
+    node _T_257 = bits(_T_256, 0, 0) @[Bitwise.scala 72:15]
+    node _T_258 = mux(_T_257, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12]
+    node _T_259 = bits(lsu_ld_datafn_corr_r, 7, 0) @[lsu_lsc_ctl.scala 262:135]
+    node _T_260 = cat(_T_258, _T_259) @[Cat.scala 29:58]
+    node _T_261 = and(_T_255, _T_260) @[lsu_lsc_ctl.scala 262:71]
+    node _T_262 = or(_T_251, _T_261) @[lsu_lsc_ctl.scala 261:119]
+    node _T_263 = eq(io.lsu_pkt_r.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 263:17]
+    node _T_264 = and(_T_263, io.lsu_pkt_r.bits.half) @[lsu_lsc_ctl.scala 263:43]
+    node _T_265 = bits(_T_264, 0, 0) @[Bitwise.scala 72:15]
+    node _T_266 = mux(_T_265, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
+    node _T_267 = bits(lsu_ld_datafn_corr_r, 15, 15) @[lsu_lsc_ctl.scala 263:106]
+    node _T_268 = bits(_T_267, 0, 0) @[Bitwise.scala 72:15]
+    node _T_269 = mux(_T_268, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12]
+    node _T_270 = bits(lsu_ld_datafn_corr_r, 15, 0) @[lsu_lsc_ctl.scala 263:135]
+    node _T_271 = cat(_T_269, _T_270) @[Cat.scala 29:58]
+    node _T_272 = and(_T_266, _T_271) @[lsu_lsc_ctl.scala 263:71]
+    node _T_273 = or(_T_262, _T_272) @[lsu_lsc_ctl.scala 262:144]
+    node _T_274 = bits(io.lsu_pkt_r.bits.word, 0, 0) @[Bitwise.scala 72:15]
+    node _T_275 = mux(_T_274, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
+    node _T_276 = bits(lsu_ld_datafn_corr_r, 31, 0) @[lsu_lsc_ctl.scala 264:65]
+    node _T_277 = and(_T_275, _T_276) @[lsu_lsc_ctl.scala 264:43]
+    node _T_278 = or(_T_273, _T_277) @[lsu_lsc_ctl.scala 263:144]
+    io.lsu_result_corr_r <= _T_278 @[lsu_lsc_ctl.scala 260:27]
+    
diff --git a/lsu_lsc_ctl.v b/lsu_lsc_ctl.v
new file mode 100644
index 00000000..bb2a3590
--- /dev/null
+++ b/lsu_lsc_ctl.v
@@ -0,0 +1,1382 @@
+module lsu_addrcheck(
+  input         reset,
+  input         io_lsu_c2_m_clk,
+  input  [31:0] io_start_addr_d,
+  input  [31:0] io_end_addr_d,
+  input         io_lsu_pkt_d_valid,
+  input         io_lsu_pkt_d_bits_fast_int,
+  input         io_lsu_pkt_d_bits_by,
+  input         io_lsu_pkt_d_bits_half,
+  input         io_lsu_pkt_d_bits_word,
+  input         io_lsu_pkt_d_bits_load,
+  input         io_lsu_pkt_d_bits_store,
+  input         io_lsu_pkt_d_bits_dma,
+  input  [31:0] io_dec_tlu_mrac_ff,
+  input  [3:0]  io_rs1_region_d,
+  output        io_is_sideeffects_m,
+  output        io_addr_in_dccm_d,
+  output        io_addr_in_pic_d,
+  output        io_addr_external_d,
+  output        io_access_fault_d,
+  output        io_misaligned_fault_d,
+  output [3:0]  io_exc_mscause_d,
+  output        io_fir_dccm_access_error_d,
+  output        io_fir_nondccm_access_error_d
+);
+`ifdef RANDOMIZE_REG_INIT
+  reg [31:0] _RAND_0;
+`endif // RANDOMIZE_REG_INIT
+  wire  start_addr_in_dccm_region_d = io_start_addr_d[31:28] == 4'hf; // @[lib.scala 365:49]
+  wire  start_addr_in_dccm_d = io_start_addr_d[31:16] == 16'hf004; // @[lib.scala 370:39]
+  wire  end_addr_in_dccm_region_d = io_end_addr_d[31:28] == 4'hf; // @[lib.scala 365:49]
+  wire  end_addr_in_dccm_d = io_end_addr_d[31:16] == 16'hf004; // @[lib.scala 370:39]
+  wire  addr_in_iccm = io_start_addr_d[31:28] == 4'he; // @[lsu_addrcheck.scala 42:45]
+  wire  start_addr_in_pic_d = io_start_addr_d[31:15] == 17'h1e018; // @[lib.scala 370:39]
+  wire  end_addr_in_pic_d = io_end_addr_d[31:15] == 17'h1e018; // @[lib.scala 370:39]
+  wire  start_addr_dccm_or_pic = start_addr_in_dccm_region_d | start_addr_in_dccm_region_d; // @[lsu_addrcheck.scala 54:60]
+  wire  _T_17 = io_rs1_region_d == 4'hf; // @[lsu_addrcheck.scala 55:55]
+  wire  base_reg_dccm_or_pic = _T_17 | _T_17; // @[lsu_addrcheck.scala 55:91]
+  wire [4:0] csr_idx = {io_start_addr_d[31:28],1'h1}; // @[Cat.scala 29:58]
+  wire [31:0] _T_26 = io_dec_tlu_mrac_ff >> csr_idx; // @[lsu_addrcheck.scala 61:50]
+  wire  _T_29 = start_addr_dccm_or_pic | addr_in_iccm; // @[lsu_addrcheck.scala 61:121]
+  wire  _T_30 = ~_T_29; // @[lsu_addrcheck.scala 61:62]
+  wire  _T_31 = _T_26[0] & _T_30; // @[lsu_addrcheck.scala 61:60]
+  wire  _T_32 = _T_31 & io_lsu_pkt_d_valid; // @[lsu_addrcheck.scala 61:137]
+  wire  _T_33 = io_lsu_pkt_d_bits_store | io_lsu_pkt_d_bits_load; // @[lsu_addrcheck.scala 61:185]
+  wire  is_sideeffects_d = _T_32 & _T_33; // @[lsu_addrcheck.scala 61:158]
+  wire  _T_35 = io_start_addr_d[1:0] == 2'h0; // @[lsu_addrcheck.scala 62:80]
+  wire  _T_36 = io_lsu_pkt_d_bits_word & _T_35; // @[lsu_addrcheck.scala 62:56]
+  wire  _T_38 = ~io_start_addr_d[0]; // @[lsu_addrcheck.scala 62:138]
+  wire  _T_39 = io_lsu_pkt_d_bits_half & _T_38; // @[lsu_addrcheck.scala 62:116]
+  wire  _T_40 = _T_36 | _T_39; // @[lsu_addrcheck.scala 62:90]
+  wire  is_aligned_d = _T_40 | io_lsu_pkt_d_bits_by; // @[lsu_addrcheck.scala 62:148]
+  wire [31:0] _T_51 = io_start_addr_d | 32'h7fffffff; // @[lsu_addrcheck.scala 67:56]
+  wire  _T_53 = _T_51 == 32'h7fffffff; // @[lsu_addrcheck.scala 67:88]
+  wire [31:0] _T_56 = io_start_addr_d | 32'h3fffffff; // @[lsu_addrcheck.scala 68:56]
+  wire  _T_58 = _T_56 == 32'hffffffff; // @[lsu_addrcheck.scala 68:88]
+  wire  _T_60 = _T_53 | _T_58; // @[lsu_addrcheck.scala 67:153]
+  wire [31:0] _T_62 = io_start_addr_d | 32'h1fffffff; // @[lsu_addrcheck.scala 69:56]
+  wire  _T_64 = _T_62 == 32'hbfffffff; // @[lsu_addrcheck.scala 69:88]
+  wire  _T_66 = _T_60 | _T_64; // @[lsu_addrcheck.scala 68:153]
+  wire [31:0] _T_68 = io_start_addr_d | 32'hfffffff; // @[lsu_addrcheck.scala 70:56]
+  wire  _T_70 = _T_68 == 32'h8fffffff; // @[lsu_addrcheck.scala 70:88]
+  wire  _T_72 = _T_66 | _T_70; // @[lsu_addrcheck.scala 69:153]
+  wire [31:0] _T_98 = io_end_addr_d | 32'h7fffffff; // @[lsu_addrcheck.scala 76:57]
+  wire  _T_100 = _T_98 == 32'h7fffffff; // @[lsu_addrcheck.scala 76:89]
+  wire [31:0] _T_103 = io_end_addr_d | 32'h3fffffff; // @[lsu_addrcheck.scala 77:58]
+  wire  _T_105 = _T_103 == 32'hffffffff; // @[lsu_addrcheck.scala 77:90]
+  wire  _T_107 = _T_100 | _T_105; // @[lsu_addrcheck.scala 76:154]
+  wire [31:0] _T_109 = io_end_addr_d | 32'h1fffffff; // @[lsu_addrcheck.scala 78:58]
+  wire  _T_111 = _T_109 == 32'hbfffffff; // @[lsu_addrcheck.scala 78:90]
+  wire  _T_113 = _T_107 | _T_111; // @[lsu_addrcheck.scala 77:155]
+  wire [31:0] _T_115 = io_end_addr_d | 32'hfffffff; // @[lsu_addrcheck.scala 79:58]
+  wire  _T_117 = _T_115 == 32'h8fffffff; // @[lsu_addrcheck.scala 79:90]
+  wire  _T_119 = _T_113 | _T_117; // @[lsu_addrcheck.scala 78:155]
+  wire  non_dccm_access_ok = _T_72 & _T_119; // @[lsu_addrcheck.scala 75:7]
+  wire  regpred_access_fault_d = start_addr_dccm_or_pic ^ base_reg_dccm_or_pic; // @[lsu_addrcheck.scala 85:57]
+  wire  _T_146 = io_start_addr_d[1:0] != 2'h0; // @[lsu_addrcheck.scala 86:76]
+  wire  _T_147 = ~io_lsu_pkt_d_bits_word; // @[lsu_addrcheck.scala 86:92]
+  wire  _T_148 = _T_146 | _T_147; // @[lsu_addrcheck.scala 86:90]
+  wire  picm_access_fault_d = io_addr_in_pic_d & _T_148; // @[lsu_addrcheck.scala 86:51]
+  wire  _T_149 = start_addr_in_dccm_d | start_addr_in_pic_d; // @[lsu_addrcheck.scala 91:87]
+  wire  _T_150 = ~_T_149; // @[lsu_addrcheck.scala 91:64]
+  wire  _T_151 = start_addr_in_dccm_region_d & _T_150; // @[lsu_addrcheck.scala 91:62]
+  wire  _T_152 = end_addr_in_dccm_d | end_addr_in_pic_d; // @[lsu_addrcheck.scala 93:57]
+  wire  _T_153 = ~_T_152; // @[lsu_addrcheck.scala 93:36]
+  wire  _T_154 = end_addr_in_dccm_region_d & _T_153; // @[lsu_addrcheck.scala 93:34]
+  wire  _T_155 = _T_151 | _T_154; // @[lsu_addrcheck.scala 91:112]
+  wire  _T_156 = start_addr_in_dccm_d & end_addr_in_pic_d; // @[lsu_addrcheck.scala 95:29]
+  wire  _T_157 = _T_155 | _T_156; // @[lsu_addrcheck.scala 93:85]
+  wire  _T_158 = start_addr_in_pic_d & end_addr_in_dccm_d; // @[lsu_addrcheck.scala 97:29]
+  wire  unmapped_access_fault_d = _T_157 | _T_158; // @[lsu_addrcheck.scala 95:85]
+  wire  _T_160 = ~start_addr_in_dccm_region_d; // @[lsu_addrcheck.scala 99:33]
+  wire  _T_161 = ~non_dccm_access_ok; // @[lsu_addrcheck.scala 99:64]
+  wire  mpu_access_fault_d = _T_160 & _T_161; // @[lsu_addrcheck.scala 99:62]
+  wire  _T_163 = unmapped_access_fault_d | mpu_access_fault_d; // @[lsu_addrcheck.scala 111:49]
+  wire  _T_164 = _T_163 | picm_access_fault_d; // @[lsu_addrcheck.scala 111:70]
+  wire  _T_165 = _T_164 | regpred_access_fault_d; // @[lsu_addrcheck.scala 111:92]
+  wire  _T_166 = _T_165 & io_lsu_pkt_d_valid; // @[lsu_addrcheck.scala 111:118]
+  wire  _T_167 = ~io_lsu_pkt_d_bits_dma; // @[lsu_addrcheck.scala 111:141]
+  wire [3:0] _T_173 = picm_access_fault_d ? 4'h6 : 4'h0; // @[lsu_addrcheck.scala 112:164]
+  wire [3:0] _T_174 = regpred_access_fault_d ? 4'h5 : _T_173; // @[lsu_addrcheck.scala 112:120]
+  wire [3:0] _T_175 = mpu_access_fault_d ? 4'h3 : _T_174; // @[lsu_addrcheck.scala 112:80]
+  wire [3:0] access_fault_mscause_d = unmapped_access_fault_d ? 4'h2 : _T_175; // @[lsu_addrcheck.scala 112:35]
+  wire  regcross_misaligned_fault_d = io_start_addr_d[31:28] != io_end_addr_d[31:28]; // @[lsu_addrcheck.scala 113:61]
+  wire  _T_178 = ~is_aligned_d; // @[lsu_addrcheck.scala 114:59]
+  wire  sideeffect_misaligned_fault_d = is_sideeffects_d & _T_178; // @[lsu_addrcheck.scala 114:57]
+  wire  _T_179 = sideeffect_misaligned_fault_d & io_addr_external_d; // @[lsu_addrcheck.scala 115:90]
+  wire  _T_180 = regcross_misaligned_fault_d | _T_179; // @[lsu_addrcheck.scala 115:57]
+  wire  _T_181 = _T_180 & io_lsu_pkt_d_valid; // @[lsu_addrcheck.scala 115:113]
+  wire [3:0] _T_185 = sideeffect_misaligned_fault_d ? 4'h1 : 4'h0; // @[lsu_addrcheck.scala 116:80]
+  wire [3:0] misaligned_fault_mscause_d = regcross_misaligned_fault_d ? 4'h2 : _T_185; // @[lsu_addrcheck.scala 116:39]
+  wire  _T_190 = ~start_addr_in_dccm_d; // @[lsu_addrcheck.scala 118:66]
+  wire  _T_191 = start_addr_in_dccm_region_d & _T_190; // @[lsu_addrcheck.scala 118:64]
+  wire  _T_192 = ~end_addr_in_dccm_d; // @[lsu_addrcheck.scala 118:120]
+  wire  _T_193 = end_addr_in_dccm_region_d & _T_192; // @[lsu_addrcheck.scala 118:118]
+  wire  _T_194 = _T_191 | _T_193; // @[lsu_addrcheck.scala 118:88]
+  wire  _T_195 = _T_194 & io_lsu_pkt_d_valid; // @[lsu_addrcheck.scala 118:142]
+  wire  _T_197 = start_addr_in_dccm_region_d & end_addr_in_dccm_region_d; // @[lsu_addrcheck.scala 119:66]
+  wire  _T_198 = ~_T_197; // @[lsu_addrcheck.scala 119:36]
+  wire  _T_199 = _T_198 & io_lsu_pkt_d_valid; // @[lsu_addrcheck.scala 119:95]
+  reg  _T_201; // @[lsu_addrcheck.scala 121:60]
+  assign io_is_sideeffects_m = _T_201; // @[lsu_addrcheck.scala 121:50]
+  assign io_addr_in_dccm_d = start_addr_in_dccm_d & end_addr_in_dccm_d; // @[lsu_addrcheck.scala 56:32]
+  assign io_addr_in_pic_d = start_addr_in_pic_d & end_addr_in_pic_d; // @[lsu_addrcheck.scala 57:32]
+  assign io_addr_external_d = ~start_addr_dccm_or_pic; // @[lsu_addrcheck.scala 59:30]
+  assign io_access_fault_d = _T_166 & _T_167; // @[lsu_addrcheck.scala 111:21]
+  assign io_misaligned_fault_d = _T_181 & _T_167; // @[lsu_addrcheck.scala 115:25]
+  assign io_exc_mscause_d = io_misaligned_fault_d ? misaligned_fault_mscause_d : access_fault_mscause_d; // @[lsu_addrcheck.scala 117:21]
+  assign io_fir_dccm_access_error_d = _T_195 & io_lsu_pkt_d_bits_fast_int; // @[lsu_addrcheck.scala 118:31]
+  assign io_fir_nondccm_access_error_d = _T_199 & io_lsu_pkt_d_bits_fast_int; // @[lsu_addrcheck.scala 119:33]
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+  integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+  `ifdef RANDOMIZE
+    `ifdef INIT_RANDOM
+      `INIT_RANDOM
+    `endif
+    `ifndef VERILATOR
+      `ifdef RANDOMIZE_DELAY
+        #`RANDOMIZE_DELAY begin end
+      `else
+        #0.002 begin end
+      `endif
+    `endif
+`ifdef RANDOMIZE_REG_INIT
+  _RAND_0 = {1{`RANDOM}};
+  _T_201 = _RAND_0[0:0];
+`endif // RANDOMIZE_REG_INIT
+  if (reset) begin
+    _T_201 = 1'h0;
+  end
+  `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+  always @(posedge io_lsu_c2_m_clk or posedge reset) begin
+    if (reset) begin
+      _T_201 <= 1'h0;
+    end else begin
+      _T_201 <= _T_32 & _T_33;
+    end
+  end
+endmodule
+module rvclkhdr(
+  input   io_clk,
+  input   io_en
+);
+  wire  clkhdr_Q; // @[lib.scala 334:26]
+  wire  clkhdr_CK; // @[lib.scala 334:26]
+  wire  clkhdr_EN; // @[lib.scala 334:26]
+  wire  clkhdr_SE; // @[lib.scala 334:26]
+  gated_latch clkhdr ( // @[lib.scala 334:26]
+    .Q(clkhdr_Q),
+    .CK(clkhdr_CK),
+    .EN(clkhdr_EN),
+    .SE(clkhdr_SE)
+  );
+  assign clkhdr_CK = io_clk; // @[lib.scala 336:18]
+  assign clkhdr_EN = io_en; // @[lib.scala 337:18]
+  assign clkhdr_SE = 1'h0; // @[lib.scala 338:18]
+endmodule
+module lsu_lsc_ctl(
+  input         clock,
+  input         reset,
+  input         io_clk_override,
+  input         io_lsu_c1_m_clk,
+  input         io_lsu_c1_r_clk,
+  input         io_lsu_c2_m_clk,
+  input         io_lsu_c2_r_clk,
+  input         io_lsu_store_c1_m_clk,
+  input  [31:0] io_lsu_ld_data_r,
+  input  [31:0] io_lsu_ld_data_corr_r,
+  input         io_lsu_single_ecc_error_r,
+  input         io_lsu_double_ecc_error_r,
+  input  [31:0] io_lsu_ld_data_m,
+  input         io_lsu_single_ecc_error_m,
+  input         io_lsu_double_ecc_error_m,
+  input         io_flush_m_up,
+  input         io_flush_r,
+  input         io_ldst_dual_d,
+  input         io_ldst_dual_m,
+  input         io_ldst_dual_r,
+  input  [31:0] io_lsu_exu_exu_lsu_rs1_d,
+  input  [31:0] io_lsu_exu_exu_lsu_rs2_d,
+  input         io_lsu_p_valid,
+  input         io_lsu_p_bits_fast_int,
+  input         io_lsu_p_bits_stack,
+  input         io_lsu_p_bits_by,
+  input         io_lsu_p_bits_half,
+  input         io_lsu_p_bits_word,
+  input         io_lsu_p_bits_dword,
+  input         io_lsu_p_bits_load,
+  input         io_lsu_p_bits_store,
+  input         io_lsu_p_bits_unsign,
+  input         io_lsu_p_bits_dma,
+  input         io_lsu_p_bits_store_data_bypass_d,
+  input         io_lsu_p_bits_load_ldst_bypass_d,
+  input         io_lsu_p_bits_store_data_bypass_m,
+  input         io_dec_lsu_valid_raw_d,
+  input  [11:0] io_dec_lsu_offset_d,
+  input  [31:0] io_picm_mask_data_m,
+  input  [31:0] io_bus_read_data_m,
+  output [31:0] io_lsu_result_m,
+  output [31:0] io_lsu_result_corr_r,
+  output [31:0] io_lsu_addr_d,
+  output [31:0] io_lsu_addr_m,
+  output [31:0] io_lsu_addr_r,
+  output [31:0] io_end_addr_d,
+  output [31:0] io_end_addr_m,
+  output [31:0] io_end_addr_r,
+  output [31:0] io_store_data_m,
+  input  [31:0] io_dec_tlu_mrac_ff,
+  output        io_lsu_exc_m,
+  output        io_is_sideeffects_m,
+  output        io_lsu_commit_r,
+  output        io_lsu_single_ecc_error_incr,
+  output        io_lsu_error_pkt_r_valid,
+  output        io_lsu_error_pkt_r_bits_single_ecc_error,
+  output        io_lsu_error_pkt_r_bits_inst_type,
+  output        io_lsu_error_pkt_r_bits_exc_type,
+  output [3:0]  io_lsu_error_pkt_r_bits_mscause,
+  output [31:0] io_lsu_error_pkt_r_bits_addr,
+  output [30:0] io_lsu_fir_addr,
+  output [1:0]  io_lsu_fir_error,
+  output        io_addr_in_dccm_d,
+  output        io_addr_in_dccm_m,
+  output        io_addr_in_dccm_r,
+  output        io_addr_in_pic_d,
+  output        io_addr_in_pic_m,
+  output        io_addr_in_pic_r,
+  output        io_addr_external_m,
+  input         io_dma_lsc_ctl_dma_dccm_req,
+  input  [31:0] io_dma_lsc_ctl_dma_mem_addr,
+  input  [2:0]  io_dma_lsc_ctl_dma_mem_sz,
+  input         io_dma_lsc_ctl_dma_mem_write,
+  input  [63:0] io_dma_lsc_ctl_dma_mem_wdata,
+  output        io_lsu_pkt_d_valid,
+  output        io_lsu_pkt_d_bits_fast_int,
+  output        io_lsu_pkt_d_bits_stack,
+  output        io_lsu_pkt_d_bits_by,
+  output        io_lsu_pkt_d_bits_half,
+  output        io_lsu_pkt_d_bits_word,
+  output        io_lsu_pkt_d_bits_dword,
+  output        io_lsu_pkt_d_bits_load,
+  output        io_lsu_pkt_d_bits_store,
+  output        io_lsu_pkt_d_bits_unsign,
+  output        io_lsu_pkt_d_bits_dma,
+  output        io_lsu_pkt_d_bits_store_data_bypass_d,
+  output        io_lsu_pkt_d_bits_load_ldst_bypass_d,
+  output        io_lsu_pkt_d_bits_store_data_bypass_m,
+  output        io_lsu_pkt_m_valid,
+  output        io_lsu_pkt_m_bits_fast_int,
+  output        io_lsu_pkt_m_bits_stack,
+  output        io_lsu_pkt_m_bits_by,
+  output        io_lsu_pkt_m_bits_half,
+  output        io_lsu_pkt_m_bits_word,
+  output        io_lsu_pkt_m_bits_dword,
+  output        io_lsu_pkt_m_bits_load,
+  output        io_lsu_pkt_m_bits_store,
+  output        io_lsu_pkt_m_bits_unsign,
+  output        io_lsu_pkt_m_bits_dma,
+  output        io_lsu_pkt_m_bits_store_data_bypass_d,
+  output        io_lsu_pkt_m_bits_load_ldst_bypass_d,
+  output        io_lsu_pkt_m_bits_store_data_bypass_m,
+  output        io_lsu_pkt_r_valid,
+  output        io_lsu_pkt_r_bits_fast_int,
+  output        io_lsu_pkt_r_bits_stack,
+  output        io_lsu_pkt_r_bits_by,
+  output        io_lsu_pkt_r_bits_half,
+  output        io_lsu_pkt_r_bits_word,
+  output        io_lsu_pkt_r_bits_dword,
+  output        io_lsu_pkt_r_bits_load,
+  output        io_lsu_pkt_r_bits_store,
+  output        io_lsu_pkt_r_bits_unsign,
+  output        io_lsu_pkt_r_bits_dma,
+  output        io_lsu_pkt_r_bits_store_data_bypass_d,
+  output        io_lsu_pkt_r_bits_load_ldst_bypass_d,
+  output        io_lsu_pkt_r_bits_store_data_bypass_m,
+  input         io_scan_mode
+);
+`ifdef RANDOMIZE_REG_INIT
+  reg [31:0] _RAND_0;
+  reg [31:0] _RAND_1;
+  reg [31:0] _RAND_2;
+  reg [31:0] _RAND_3;
+  reg [31:0] _RAND_4;
+  reg [31:0] _RAND_5;
+  reg [31:0] _RAND_6;
+  reg [31:0] _RAND_7;
+  reg [31:0] _RAND_8;
+  reg [31:0] _RAND_9;
+  reg [31:0] _RAND_10;
+  reg [31:0] _RAND_11;
+  reg [31:0] _RAND_12;
+  reg [31:0] _RAND_13;
+  reg [31:0] _RAND_14;
+  reg [31:0] _RAND_15;
+  reg [31:0] _RAND_16;
+  reg [31:0] _RAND_17;
+  reg [31:0] _RAND_18;
+  reg [31:0] _RAND_19;
+  reg [31:0] _RAND_20;
+  reg [31:0] _RAND_21;
+  reg [31:0] _RAND_22;
+  reg [31:0] _RAND_23;
+  reg [31:0] _RAND_24;
+  reg [31:0] _RAND_25;
+  reg [31:0] _RAND_26;
+  reg [31:0] _RAND_27;
+  reg [31:0] _RAND_28;
+  reg [31:0] _RAND_29;
+  reg [31:0] _RAND_30;
+  reg [31:0] _RAND_31;
+  reg [31:0] _RAND_32;
+  reg [31:0] _RAND_33;
+  reg [31:0] _RAND_34;
+  reg [31:0] _RAND_35;
+  reg [31:0] _RAND_36;
+  reg [31:0] _RAND_37;
+  reg [31:0] _RAND_38;
+  reg [31:0] _RAND_39;
+  reg [31:0] _RAND_40;
+  reg [31:0] _RAND_41;
+  reg [31:0] _RAND_42;
+  reg [31:0] _RAND_43;
+  reg [31:0] _RAND_44;
+  reg [31:0] _RAND_45;
+  reg [31:0] _RAND_46;
+  reg [31:0] _RAND_47;
+  reg [31:0] _RAND_48;
+  reg [31:0] _RAND_49;
+  reg [31:0] _RAND_50;
+  reg [31:0] _RAND_51;
+`endif // RANDOMIZE_REG_INIT
+  wire  addrcheck_reset; // @[lsu_lsc_ctl.scala 118:25]
+  wire  addrcheck_io_lsu_c2_m_clk; // @[lsu_lsc_ctl.scala 118:25]
+  wire [31:0] addrcheck_io_start_addr_d; // @[lsu_lsc_ctl.scala 118:25]
+  wire [31:0] addrcheck_io_end_addr_d; // @[lsu_lsc_ctl.scala 118:25]
+  wire  addrcheck_io_lsu_pkt_d_valid; // @[lsu_lsc_ctl.scala 118:25]
+  wire  addrcheck_io_lsu_pkt_d_bits_fast_int; // @[lsu_lsc_ctl.scala 118:25]
+  wire  addrcheck_io_lsu_pkt_d_bits_by; // @[lsu_lsc_ctl.scala 118:25]
+  wire  addrcheck_io_lsu_pkt_d_bits_half; // @[lsu_lsc_ctl.scala 118:25]
+  wire  addrcheck_io_lsu_pkt_d_bits_word; // @[lsu_lsc_ctl.scala 118:25]
+  wire  addrcheck_io_lsu_pkt_d_bits_load; // @[lsu_lsc_ctl.scala 118:25]
+  wire  addrcheck_io_lsu_pkt_d_bits_store; // @[lsu_lsc_ctl.scala 118:25]
+  wire  addrcheck_io_lsu_pkt_d_bits_dma; // @[lsu_lsc_ctl.scala 118:25]
+  wire [31:0] addrcheck_io_dec_tlu_mrac_ff; // @[lsu_lsc_ctl.scala 118:25]
+  wire [3:0] addrcheck_io_rs1_region_d; // @[lsu_lsc_ctl.scala 118:25]
+  wire  addrcheck_io_is_sideeffects_m; // @[lsu_lsc_ctl.scala 118:25]
+  wire  addrcheck_io_addr_in_dccm_d; // @[lsu_lsc_ctl.scala 118:25]
+  wire  addrcheck_io_addr_in_pic_d; // @[lsu_lsc_ctl.scala 118:25]
+  wire  addrcheck_io_addr_external_d; // @[lsu_lsc_ctl.scala 118:25]
+  wire  addrcheck_io_access_fault_d; // @[lsu_lsc_ctl.scala 118:25]
+  wire  addrcheck_io_misaligned_fault_d; // @[lsu_lsc_ctl.scala 118:25]
+  wire [3:0] addrcheck_io_exc_mscause_d; // @[lsu_lsc_ctl.scala 118:25]
+  wire  addrcheck_io_fir_dccm_access_error_d; // @[lsu_lsc_ctl.scala 118:25]
+  wire  addrcheck_io_fir_nondccm_access_error_d; // @[lsu_lsc_ctl.scala 118:25]
+  wire  rvclkhdr_io_clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_io_en; // @[lib.scala 390:23]
+  wire  rvclkhdr_1_io_clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_1_io_en; // @[lib.scala 390:23]
+  wire  rvclkhdr_2_io_clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_2_io_en; // @[lib.scala 390:23]
+  wire [31:0] lsu_rs1_d = io_dec_lsu_valid_raw_d ? io_lsu_exu_exu_lsu_rs1_d : io_dma_lsc_ctl_dma_mem_addr; // @[lsu_lsc_ctl.scala 100:28]
+  wire [11:0] _T_4 = io_dec_lsu_valid_raw_d ? 12'hfff : 12'h0; // @[Bitwise.scala 72:12]
+  wire [11:0] lsu_offset_d = io_dec_lsu_offset_d & _T_4; // @[lsu_lsc_ctl.scala 101:51]
+  wire [31:0] rs1_d = io_lsu_pkt_d_bits_load_ldst_bypass_d ? io_lsu_result_m : lsu_rs1_d; // @[lsu_lsc_ctl.scala 104:28]
+  wire [12:0] _T_7 = {1'h0,rs1_d[11:0]}; // @[Cat.scala 29:58]
+  wire [12:0] _T_9 = {1'h0,lsu_offset_d}; // @[Cat.scala 29:58]
+  wire [12:0] _T_11 = _T_7 + _T_9; // @[lib.scala 92:39]
+  wire  _T_14 = lsu_offset_d[11] ^ _T_11[12]; // @[lib.scala 93:46]
+  wire  _T_15 = ~_T_14; // @[lib.scala 93:33]
+  wire [19:0] _T_17 = _T_15 ? 20'hfffff : 20'h0; // @[Bitwise.scala 72:12]
+  wire [19:0] _T_19 = _T_17 & rs1_d[31:12]; // @[lib.scala 93:58]
+  wire  _T_21 = ~lsu_offset_d[11]; // @[lib.scala 94:18]
+  wire  _T_23 = _T_21 & _T_11[12]; // @[lib.scala 94:30]
+  wire [19:0] _T_25 = _T_23 ? 20'hfffff : 20'h0; // @[Bitwise.scala 72:12]
+  wire [19:0] _T_28 = rs1_d[31:12] + 20'h1; // @[lib.scala 94:54]
+  wire [19:0] _T_29 = _T_25 & _T_28; // @[lib.scala 94:41]
+  wire [19:0] _T_30 = _T_19 | _T_29; // @[lib.scala 93:72]
+  wire  _T_33 = ~_T_11[12]; // @[lib.scala 95:31]
+  wire  _T_34 = lsu_offset_d[11] & _T_33; // @[lib.scala 95:29]
+  wire [19:0] _T_36 = _T_34 ? 20'hfffff : 20'h0; // @[Bitwise.scala 72:12]
+  wire [19:0] _T_39 = rs1_d[31:12] - 20'h1; // @[lib.scala 95:54]
+  wire [19:0] _T_40 = _T_36 & _T_39; // @[lib.scala 95:41]
+  wire [19:0] _T_41 = _T_30 | _T_40; // @[lib.scala 94:61]
+  wire [2:0] _T_44 = io_lsu_pkt_d_bits_half ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
+  wire [2:0] _T_45 = _T_44 & 3'h1; // @[lsu_lsc_ctl.scala 109:58]
+  wire [2:0] _T_47 = io_lsu_pkt_d_bits_word ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
+  wire [2:0] _T_48 = _T_47 & 3'h3; // @[lsu_lsc_ctl.scala 110:40]
+  wire [2:0] _T_49 = _T_45 | _T_48; // @[lsu_lsc_ctl.scala 109:70]
+  wire [2:0] _T_51 = io_lsu_pkt_d_bits_dword ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
+  wire [2:0] addr_offset_d = _T_49 | _T_51; // @[lsu_lsc_ctl.scala 110:52]
+  wire [12:0] _T_55 = {lsu_offset_d[11],lsu_offset_d}; // @[Cat.scala 29:58]
+  wire [11:0] _T_58 = {9'h0,addr_offset_d}; // @[Cat.scala 29:58]
+  wire [12:0] _GEN_3 = {{1'd0}, _T_58}; // @[lsu_lsc_ctl.scala 113:60]
+  wire [12:0] end_addr_offset_d = _T_55 + _GEN_3; // @[lsu_lsc_ctl.scala 113:60]
+  wire [18:0] _T_63 = end_addr_offset_d[12] ? 19'h7ffff : 19'h0; // @[Bitwise.scala 72:12]
+  wire [31:0] _T_65 = {_T_63,end_addr_offset_d}; // @[Cat.scala 29:58]
+  reg  access_fault_m; // @[lsu_lsc_ctl.scala 149:75]
+  reg  misaligned_fault_m; // @[lsu_lsc_ctl.scala 150:75]
+  reg [3:0] exc_mscause_m; // @[lsu_lsc_ctl.scala 151:75]
+  reg  fir_dccm_access_error_m; // @[lsu_lsc_ctl.scala 152:75]
+  reg  fir_nondccm_access_error_m; // @[lsu_lsc_ctl.scala 153:75]
+  wire  _T_71 = ~io_lsu_double_ecc_error_r; // @[lsu_lsc_ctl.scala 156:64]
+  wire  _T_72 = io_lsu_single_ecc_error_r & _T_71; // @[lsu_lsc_ctl.scala 156:62]
+  wire  _T_73 = io_lsu_commit_r | io_lsu_pkt_r_bits_dma; // @[lsu_lsc_ctl.scala 156:111]
+  wire  _T_74 = _T_72 & _T_73; // @[lsu_lsc_ctl.scala 156:92]
+  reg  access_fault_r; // @[lsu_lsc_ctl.scala 168:71]
+  reg  misaligned_fault_r; // @[lsu_lsc_ctl.scala 172:71]
+  wire  _T_76 = access_fault_r | misaligned_fault_r; // @[lsu_lsc_ctl.scala 160:49]
+  wire  _T_77 = _T_76 | io_lsu_double_ecc_error_r; // @[lsu_lsc_ctl.scala 160:70]
+  wire  _T_78 = _T_77 & io_lsu_pkt_r_valid; // @[lsu_lsc_ctl.scala 160:99]
+  wire  _T_79 = ~io_lsu_pkt_r_bits_dma; // @[lsu_lsc_ctl.scala 160:122]
+  wire  _T_80 = _T_78 & _T_79; // @[lsu_lsc_ctl.scala 160:120]
+  wire  _T_81 = ~io_lsu_pkt_r_bits_fast_int; // @[lsu_lsc_ctl.scala 160:147]
+  wire  _T_83 = ~io_lsu_error_pkt_r_valid; // @[lsu_lsc_ctl.scala 161:77]
+  wire  _T_84 = io_lsu_single_ecc_error_r & _T_83; // @[lsu_lsc_ctl.scala 161:75]
+  wire  _T_87 = ~misaligned_fault_r; // @[lsu_lsc_ctl.scala 163:42]
+  wire  _T_89 = io_lsu_double_ecc_error_r & _T_87; // @[lsu_lsc_ctl.scala 164:73]
+  wire  _T_90 = ~access_fault_r; // @[lsu_lsc_ctl.scala 164:97]
+  wire  _T_91 = _T_89 & _T_90; // @[lsu_lsc_ctl.scala 164:95]
+  reg [3:0] exc_mscause_r; // @[lsu_lsc_ctl.scala 169:71]
+  reg  fir_nondccm_access_error_r; // @[lsu_lsc_ctl.scala 171:71]
+  reg  fir_dccm_access_error_r; // @[lsu_lsc_ctl.scala 170:71]
+  wire  _T_98 = io_lsu_pkt_r_bits_fast_int & io_lsu_double_ecc_error_r; // @[lsu_lsc_ctl.scala 166:162]
+  wire [1:0] _T_100 = _T_98 ? 2'h1 : 2'h0; // @[lsu_lsc_ctl.scala 166:133]
+  wire [1:0] _T_101 = fir_dccm_access_error_r ? 2'h2 : _T_100; // @[lsu_lsc_ctl.scala 166:88]
+  wire  dma_pkt_d_bits_load = ~io_dma_lsc_ctl_dma_mem_write; // @[lsu_lsc_ctl.scala 196:30]
+  wire  dma_pkt_d_bits_by = io_dma_lsc_ctl_dma_mem_sz == 3'h0; // @[lsu_lsc_ctl.scala 197:62]
+  wire  dma_pkt_d_bits_half = io_dma_lsc_ctl_dma_mem_sz == 3'h1; // @[lsu_lsc_ctl.scala 198:62]
+  wire  dma_pkt_d_bits_word = io_dma_lsc_ctl_dma_mem_sz == 3'h2; // @[lsu_lsc_ctl.scala 199:62]
+  wire  dma_pkt_d_bits_dword = io_dma_lsc_ctl_dma_mem_sz == 3'h3; // @[lsu_lsc_ctl.scala 200:62]
+  wire  _T_119 = ~io_lsu_p_bits_fast_int; // @[lsu_lsc_ctl.scala 213:64]
+  wire  _T_120 = io_flush_m_up & _T_119; // @[lsu_lsc_ctl.scala 213:61]
+  wire  _T_121 = ~_T_120; // @[lsu_lsc_ctl.scala 213:45]
+  wire  _T_122 = io_lsu_p_valid & _T_121; // @[lsu_lsc_ctl.scala 213:43]
+  wire  _T_124 = ~io_lsu_pkt_d_bits_dma; // @[lsu_lsc_ctl.scala 214:68]
+  wire  _T_125 = io_flush_m_up & _T_124; // @[lsu_lsc_ctl.scala 214:65]
+  wire  _T_126 = ~_T_125; // @[lsu_lsc_ctl.scala 214:49]
+  wire  _T_128 = ~io_lsu_pkt_m_bits_dma; // @[lsu_lsc_ctl.scala 215:68]
+  wire  _T_129 = io_flush_m_up & _T_128; // @[lsu_lsc_ctl.scala 215:65]
+  wire  _T_130 = ~_T_129; // @[lsu_lsc_ctl.scala 215:49]
+  reg  _T_133_bits_fast_int; // @[lsu_lsc_ctl.scala 217:65]
+  reg  _T_133_bits_stack; // @[lsu_lsc_ctl.scala 217:65]
+  reg  _T_133_bits_by; // @[lsu_lsc_ctl.scala 217:65]
+  reg  _T_133_bits_half; // @[lsu_lsc_ctl.scala 217:65]
+  reg  _T_133_bits_word; // @[lsu_lsc_ctl.scala 217:65]
+  reg  _T_133_bits_dword; // @[lsu_lsc_ctl.scala 217:65]
+  reg  _T_133_bits_load; // @[lsu_lsc_ctl.scala 217:65]
+  reg  _T_133_bits_store; // @[lsu_lsc_ctl.scala 217:65]
+  reg  _T_133_bits_unsign; // @[lsu_lsc_ctl.scala 217:65]
+  reg  _T_133_bits_dma; // @[lsu_lsc_ctl.scala 217:65]
+  reg  _T_133_bits_store_data_bypass_d; // @[lsu_lsc_ctl.scala 217:65]
+  reg  _T_133_bits_load_ldst_bypass_d; // @[lsu_lsc_ctl.scala 217:65]
+  reg  _T_133_bits_store_data_bypass_m; // @[lsu_lsc_ctl.scala 217:65]
+  reg  _T_135_bits_fast_int; // @[lsu_lsc_ctl.scala 218:65]
+  reg  _T_135_bits_stack; // @[lsu_lsc_ctl.scala 218:65]
+  reg  _T_135_bits_by; // @[lsu_lsc_ctl.scala 218:65]
+  reg  _T_135_bits_half; // @[lsu_lsc_ctl.scala 218:65]
+  reg  _T_135_bits_word; // @[lsu_lsc_ctl.scala 218:65]
+  reg  _T_135_bits_dword; // @[lsu_lsc_ctl.scala 218:65]
+  reg  _T_135_bits_load; // @[lsu_lsc_ctl.scala 218:65]
+  reg  _T_135_bits_store; // @[lsu_lsc_ctl.scala 218:65]
+  reg  _T_135_bits_unsign; // @[lsu_lsc_ctl.scala 218:65]
+  reg  _T_135_bits_dma; // @[lsu_lsc_ctl.scala 218:65]
+  reg  _T_135_bits_store_data_bypass_d; // @[lsu_lsc_ctl.scala 218:65]
+  reg  _T_135_bits_load_ldst_bypass_d; // @[lsu_lsc_ctl.scala 218:65]
+  reg  _T_135_bits_store_data_bypass_m; // @[lsu_lsc_ctl.scala 218:65]
+  reg  _T_136; // @[lsu_lsc_ctl.scala 219:65]
+  reg  _T_137; // @[lsu_lsc_ctl.scala 220:65]
+  wire [5:0] _T_140 = {io_dma_lsc_ctl_dma_mem_addr[2:0],3'h0}; // @[Cat.scala 29:58]
+  wire [63:0] dma_mem_wdata_shifted = io_dma_lsc_ctl_dma_mem_wdata >> _T_140; // @[lsu_lsc_ctl.scala 222:66]
+  reg [31:0] store_data_pre_m; // @[lsu_lsc_ctl.scala 226:72]
+  reg [31:0] _T_147; // @[lsu_lsc_ctl.scala 227:62]
+  reg [31:0] _T_148; // @[lsu_lsc_ctl.scala 228:62]
+  reg [28:0] end_addr_pre_m; // @[Reg.scala 27:20]
+  wire [28:0] _T_151 = io_ldst_dual_m ? end_addr_pre_m : io_lsu_addr_m[31:3]; // @[lsu_lsc_ctl.scala 229:27]
+  reg [2:0] _T_153; // @[lsu_lsc_ctl.scala 229:114]
+  reg [28:0] end_addr_pre_r; // @[Reg.scala 27:20]
+  wire [28:0] _T_157 = io_ldst_dual_r ? end_addr_pre_r : io_lsu_addr_r[31:3]; // @[lsu_lsc_ctl.scala 230:27]
+  reg [2:0] _T_159; // @[lsu_lsc_ctl.scala 230:114]
+  wire  _T_162 = io_lsu_pkt_d_valid & io_ldst_dual_d; // @[lsu_lsc_ctl.scala 231:69]
+  wire  _T_163 = _T_162 | io_clk_override; // @[lsu_lsc_ctl.scala 231:87]
+  wire  _T_168 = io_lsu_pkt_m_valid & io_ldst_dual_m; // @[lsu_lsc_ctl.scala 232:69]
+  wire  _T_169 = _T_168 | io_clk_override; // @[lsu_lsc_ctl.scala 232:87]
+  reg  _T_173; // @[lsu_lsc_ctl.scala 233:62]
+  reg  _T_174; // @[lsu_lsc_ctl.scala 234:62]
+  reg  _T_175; // @[lsu_lsc_ctl.scala 235:62]
+  reg  _T_176; // @[lsu_lsc_ctl.scala 236:62]
+  reg  _T_177; // @[lsu_lsc_ctl.scala 237:62]
+  reg  addr_external_r; // @[lsu_lsc_ctl.scala 238:66]
+  wire  _T_178 = io_addr_external_m | io_clk_override; // @[lsu_lsc_ctl.scala 239:77]
+  reg [31:0] bus_read_data_r; // @[Reg.scala 27:20]
+  wire  _T_181 = io_lsu_pkt_r_bits_store | io_lsu_pkt_r_bits_load; // @[lsu_lsc_ctl.scala 246:68]
+  wire  _T_182 = io_lsu_pkt_r_valid & _T_181; // @[lsu_lsc_ctl.scala 246:41]
+  wire  _T_183 = ~io_flush_r; // @[lsu_lsc_ctl.scala 246:96]
+  wire  _T_184 = _T_182 & _T_183; // @[lsu_lsc_ctl.scala 246:94]
+  wire  _T_188 = ~io_addr_in_pic_m; // @[lsu_lsc_ctl.scala 247:69]
+  wire [31:0] _T_190 = _T_188 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
+  wire [31:0] _T_191 = io_picm_mask_data_m | _T_190; // @[lsu_lsc_ctl.scala 247:59]
+  wire [31:0] _T_193 = io_lsu_pkt_m_bits_store_data_bypass_m ? io_lsu_result_m : store_data_pre_m; // @[lsu_lsc_ctl.scala 247:94]
+  wire [31:0] lsu_ld_datafn_r = addr_external_r ? bus_read_data_r : io_lsu_ld_data_r; // @[lsu_lsc_ctl.scala 251:33]
+  wire [31:0] lsu_ld_datafn_corr_r = addr_external_r ? bus_read_data_r : io_lsu_ld_data_corr_r; // @[lsu_lsc_ctl.scala 252:33]
+  wire  _T_199 = io_lsu_pkt_r_bits_unsign & io_lsu_pkt_r_bits_by; // @[lsu_lsc_ctl.scala 254:66]
+  wire [31:0] _T_201 = _T_199 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
+  wire [31:0] _T_203 = {24'h0,lsu_ld_datafn_r[7:0]}; // @[Cat.scala 29:58]
+  wire [31:0] _T_204 = _T_201 & _T_203; // @[lsu_lsc_ctl.scala 254:94]
+  wire  _T_205 = io_lsu_pkt_r_bits_unsign & io_lsu_pkt_r_bits_half; // @[lsu_lsc_ctl.scala 255:43]
+  wire [31:0] _T_207 = _T_205 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
+  wire [31:0] _T_209 = {16'h0,lsu_ld_datafn_r[15:0]}; // @[Cat.scala 29:58]
+  wire [31:0] _T_210 = _T_207 & _T_209; // @[lsu_lsc_ctl.scala 255:71]
+  wire [31:0] _T_211 = _T_204 | _T_210; // @[lsu_lsc_ctl.scala 254:133]
+  wire  _T_212 = ~io_lsu_pkt_r_bits_unsign; // @[lsu_lsc_ctl.scala 256:17]
+  wire  _T_213 = _T_212 & io_lsu_pkt_r_bits_by; // @[lsu_lsc_ctl.scala 256:43]
+  wire [31:0] _T_215 = _T_213 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
+  wire [23:0] _T_218 = lsu_ld_datafn_r[7] ? 24'hffffff : 24'h0; // @[Bitwise.scala 72:12]
+  wire [31:0] _T_220 = {_T_218,lsu_ld_datafn_r[7:0]}; // @[Cat.scala 29:58]
+  wire [31:0] _T_221 = _T_215 & _T_220; // @[lsu_lsc_ctl.scala 256:71]
+  wire [31:0] _T_222 = _T_211 | _T_221; // @[lsu_lsc_ctl.scala 255:114]
+  wire  _T_224 = _T_212 & io_lsu_pkt_r_bits_half; // @[lsu_lsc_ctl.scala 257:43]
+  wire [31:0] _T_226 = _T_224 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
+  wire [15:0] _T_229 = lsu_ld_datafn_r[15] ? 16'hffff : 16'h0; // @[Bitwise.scala 72:12]
+  wire [31:0] _T_231 = {_T_229,lsu_ld_datafn_r[15:0]}; // @[Cat.scala 29:58]
+  wire [31:0] _T_232 = _T_226 & _T_231; // @[lsu_lsc_ctl.scala 257:71]
+  wire [31:0] _T_233 = _T_222 | _T_232; // @[lsu_lsc_ctl.scala 256:134]
+  wire [31:0] _T_235 = io_lsu_pkt_r_bits_word ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
+  wire [31:0] _T_237 = _T_235 & lsu_ld_datafn_r; // @[lsu_lsc_ctl.scala 258:43]
+  wire [31:0] _T_243 = {24'h0,lsu_ld_datafn_corr_r[7:0]}; // @[Cat.scala 29:58]
+  wire [31:0] _T_244 = _T_201 & _T_243; // @[lsu_lsc_ctl.scala 260:94]
+  wire [31:0] _T_249 = {16'h0,lsu_ld_datafn_corr_r[15:0]}; // @[Cat.scala 29:58]
+  wire [31:0] _T_250 = _T_207 & _T_249; // @[lsu_lsc_ctl.scala 261:71]
+  wire [31:0] _T_251 = _T_244 | _T_250; // @[lsu_lsc_ctl.scala 260:138]
+  wire [23:0] _T_258 = lsu_ld_datafn_corr_r[7] ? 24'hffffff : 24'h0; // @[Bitwise.scala 72:12]
+  wire [31:0] _T_260 = {_T_258,lsu_ld_datafn_corr_r[7:0]}; // @[Cat.scala 29:58]
+  wire [31:0] _T_261 = _T_215 & _T_260; // @[lsu_lsc_ctl.scala 262:71]
+  wire [31:0] _T_262 = _T_251 | _T_261; // @[lsu_lsc_ctl.scala 261:119]
+  wire [15:0] _T_269 = lsu_ld_datafn_corr_r[15] ? 16'hffff : 16'h0; // @[Bitwise.scala 72:12]
+  wire [31:0] _T_271 = {_T_269,lsu_ld_datafn_corr_r[15:0]}; // @[Cat.scala 29:58]
+  wire [31:0] _T_272 = _T_226 & _T_271; // @[lsu_lsc_ctl.scala 263:71]
+  wire [31:0] _T_273 = _T_262 | _T_272; // @[lsu_lsc_ctl.scala 262:144]
+  wire [31:0] _T_277 = _T_235 & lsu_ld_datafn_corr_r; // @[lsu_lsc_ctl.scala 264:43]
+  lsu_addrcheck addrcheck ( // @[lsu_lsc_ctl.scala 118:25]
+    .reset(addrcheck_reset),
+    .io_lsu_c2_m_clk(addrcheck_io_lsu_c2_m_clk),
+    .io_start_addr_d(addrcheck_io_start_addr_d),
+    .io_end_addr_d(addrcheck_io_end_addr_d),
+    .io_lsu_pkt_d_valid(addrcheck_io_lsu_pkt_d_valid),
+    .io_lsu_pkt_d_bits_fast_int(addrcheck_io_lsu_pkt_d_bits_fast_int),
+    .io_lsu_pkt_d_bits_by(addrcheck_io_lsu_pkt_d_bits_by),
+    .io_lsu_pkt_d_bits_half(addrcheck_io_lsu_pkt_d_bits_half),
+    .io_lsu_pkt_d_bits_word(addrcheck_io_lsu_pkt_d_bits_word),
+    .io_lsu_pkt_d_bits_load(addrcheck_io_lsu_pkt_d_bits_load),
+    .io_lsu_pkt_d_bits_store(addrcheck_io_lsu_pkt_d_bits_store),
+    .io_lsu_pkt_d_bits_dma(addrcheck_io_lsu_pkt_d_bits_dma),
+    .io_dec_tlu_mrac_ff(addrcheck_io_dec_tlu_mrac_ff),
+    .io_rs1_region_d(addrcheck_io_rs1_region_d),
+    .io_is_sideeffects_m(addrcheck_io_is_sideeffects_m),
+    .io_addr_in_dccm_d(addrcheck_io_addr_in_dccm_d),
+    .io_addr_in_pic_d(addrcheck_io_addr_in_pic_d),
+    .io_addr_external_d(addrcheck_io_addr_external_d),
+    .io_access_fault_d(addrcheck_io_access_fault_d),
+    .io_misaligned_fault_d(addrcheck_io_misaligned_fault_d),
+    .io_exc_mscause_d(addrcheck_io_exc_mscause_d),
+    .io_fir_dccm_access_error_d(addrcheck_io_fir_dccm_access_error_d),
+    .io_fir_nondccm_access_error_d(addrcheck_io_fir_nondccm_access_error_d)
+  );
+  rvclkhdr rvclkhdr ( // @[lib.scala 390:23]
+    .io_clk(rvclkhdr_io_clk),
+    .io_en(rvclkhdr_io_en)
+  );
+  rvclkhdr rvclkhdr_1 ( // @[lib.scala 390:23]
+    .io_clk(rvclkhdr_1_io_clk),
+    .io_en(rvclkhdr_1_io_en)
+  );
+  rvclkhdr rvclkhdr_2 ( // @[lib.scala 390:23]
+    .io_clk(rvclkhdr_2_io_clk),
+    .io_en(rvclkhdr_2_io_en)
+  );
+  assign io_lsu_result_m = _T_233 | _T_237; // @[lsu_lsc_ctl.scala 254:27]
+  assign io_lsu_result_corr_r = _T_273 | _T_277; // @[lsu_lsc_ctl.scala 260:27]
+  assign io_lsu_addr_d = {_T_41,_T_11[11:0]}; // @[lsu_lsc_ctl.scala 244:28]
+  assign io_lsu_addr_m = _T_147; // @[lsu_lsc_ctl.scala 227:24]
+  assign io_lsu_addr_r = _T_148; // @[lsu_lsc_ctl.scala 228:24]
+  assign io_end_addr_d = rs1_d + _T_65; // @[lsu_lsc_ctl.scala 115:24]
+  assign io_end_addr_m = {_T_151,_T_153}; // @[lsu_lsc_ctl.scala 229:17]
+  assign io_end_addr_r = {_T_157,_T_159}; // @[lsu_lsc_ctl.scala 230:17]
+  assign io_store_data_m = _T_191 & _T_193; // @[lsu_lsc_ctl.scala 247:29]
+  assign io_lsu_exc_m = access_fault_m | misaligned_fault_m; // @[lsu_lsc_ctl.scala 155:16]
+  assign io_is_sideeffects_m = addrcheck_io_is_sideeffects_m; // @[lsu_lsc_ctl.scala 128:42]
+  assign io_lsu_commit_r = _T_184 & _T_79; // @[lsu_lsc_ctl.scala 246:19]
+  assign io_lsu_single_ecc_error_incr = _T_74 & io_lsu_pkt_r_valid; // @[lsu_lsc_ctl.scala 156:32]
+  assign io_lsu_error_pkt_r_valid = _T_80 & _T_81; // @[lsu_lsc_ctl.scala 160:30]
+  assign io_lsu_error_pkt_r_bits_single_ecc_error = _T_84 & _T_79; // @[lsu_lsc_ctl.scala 161:46]
+  assign io_lsu_error_pkt_r_bits_inst_type = io_lsu_pkt_r_bits_store; // @[lsu_lsc_ctl.scala 162:39]
+  assign io_lsu_error_pkt_r_bits_exc_type = ~misaligned_fault_r; // @[lsu_lsc_ctl.scala 163:39]
+  assign io_lsu_error_pkt_r_bits_mscause = _T_91 ? 4'h1 : exc_mscause_r; // @[lsu_lsc_ctl.scala 164:39]
+  assign io_lsu_error_pkt_r_bits_addr = io_lsu_addr_r; // @[lsu_lsc_ctl.scala 165:39]
+  assign io_lsu_fir_addr = io_lsu_ld_data_corr_r[31:1]; // @[lsu_lsc_ctl.scala 242:28]
+  assign io_lsu_fir_error = fir_nondccm_access_error_r ? 2'h3 : _T_101; // @[lsu_lsc_ctl.scala 166:34]
+  assign io_addr_in_dccm_d = addrcheck_io_addr_in_dccm_d; // @[lsu_lsc_ctl.scala 129:42]
+  assign io_addr_in_dccm_m = _T_173; // @[lsu_lsc_ctl.scala 233:24]
+  assign io_addr_in_dccm_r = _T_174; // @[lsu_lsc_ctl.scala 234:24]
+  assign io_addr_in_pic_d = addrcheck_io_addr_in_pic_d; // @[lsu_lsc_ctl.scala 130:42]
+  assign io_addr_in_pic_m = _T_175; // @[lsu_lsc_ctl.scala 235:24]
+  assign io_addr_in_pic_r = _T_176; // @[lsu_lsc_ctl.scala 236:24]
+  assign io_addr_external_m = _T_177; // @[lsu_lsc_ctl.scala 237:24]
+  assign io_lsu_pkt_d_valid = _T_122 | io_dma_lsc_ctl_dma_dccm_req; // @[lsu_lsc_ctl.scala 209:20 lsu_lsc_ctl.scala 213:24]
+  assign io_lsu_pkt_d_bits_fast_int = io_dec_lsu_valid_raw_d & io_lsu_p_bits_fast_int; // @[lsu_lsc_ctl.scala 209:20]
+  assign io_lsu_pkt_d_bits_stack = io_dec_lsu_valid_raw_d & io_lsu_p_bits_stack; // @[lsu_lsc_ctl.scala 209:20]
+  assign io_lsu_pkt_d_bits_by = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_by : dma_pkt_d_bits_by; // @[lsu_lsc_ctl.scala 209:20]
+  assign io_lsu_pkt_d_bits_half = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_half : dma_pkt_d_bits_half; // @[lsu_lsc_ctl.scala 209:20]
+  assign io_lsu_pkt_d_bits_word = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_word : dma_pkt_d_bits_word; // @[lsu_lsc_ctl.scala 209:20]
+  assign io_lsu_pkt_d_bits_dword = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_dword : dma_pkt_d_bits_dword; // @[lsu_lsc_ctl.scala 209:20]
+  assign io_lsu_pkt_d_bits_load = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_load : dma_pkt_d_bits_load; // @[lsu_lsc_ctl.scala 209:20]
+  assign io_lsu_pkt_d_bits_store = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_store : io_dma_lsc_ctl_dma_mem_write; // @[lsu_lsc_ctl.scala 209:20]
+  assign io_lsu_pkt_d_bits_unsign = io_dec_lsu_valid_raw_d & io_lsu_p_bits_unsign; // @[lsu_lsc_ctl.scala 209:20]
+  assign io_lsu_pkt_d_bits_dma = io_dec_lsu_valid_raw_d ? io_lsu_p_bits_dma : 1'h1; // @[lsu_lsc_ctl.scala 209:20]
+  assign io_lsu_pkt_d_bits_store_data_bypass_d = io_dec_lsu_valid_raw_d & io_lsu_p_bits_store_data_bypass_d; // @[lsu_lsc_ctl.scala 209:20]
+  assign io_lsu_pkt_d_bits_load_ldst_bypass_d = io_dec_lsu_valid_raw_d & io_lsu_p_bits_load_ldst_bypass_d; // @[lsu_lsc_ctl.scala 209:20]
+  assign io_lsu_pkt_d_bits_store_data_bypass_m = io_dec_lsu_valid_raw_d & io_lsu_p_bits_store_data_bypass_m; // @[lsu_lsc_ctl.scala 209:20]
+  assign io_lsu_pkt_m_valid = _T_136; // @[lsu_lsc_ctl.scala 217:28 lsu_lsc_ctl.scala 219:28]
+  assign io_lsu_pkt_m_bits_fast_int = _T_133_bits_fast_int; // @[lsu_lsc_ctl.scala 217:28]
+  assign io_lsu_pkt_m_bits_stack = _T_133_bits_stack; // @[lsu_lsc_ctl.scala 217:28]
+  assign io_lsu_pkt_m_bits_by = _T_133_bits_by; // @[lsu_lsc_ctl.scala 217:28]
+  assign io_lsu_pkt_m_bits_half = _T_133_bits_half; // @[lsu_lsc_ctl.scala 217:28]
+  assign io_lsu_pkt_m_bits_word = _T_133_bits_word; // @[lsu_lsc_ctl.scala 217:28]
+  assign io_lsu_pkt_m_bits_dword = _T_133_bits_dword; // @[lsu_lsc_ctl.scala 217:28]
+  assign io_lsu_pkt_m_bits_load = _T_133_bits_load; // @[lsu_lsc_ctl.scala 217:28]
+  assign io_lsu_pkt_m_bits_store = _T_133_bits_store; // @[lsu_lsc_ctl.scala 217:28]
+  assign io_lsu_pkt_m_bits_unsign = _T_133_bits_unsign; // @[lsu_lsc_ctl.scala 217:28]
+  assign io_lsu_pkt_m_bits_dma = _T_133_bits_dma; // @[lsu_lsc_ctl.scala 217:28]
+  assign io_lsu_pkt_m_bits_store_data_bypass_d = _T_133_bits_store_data_bypass_d; // @[lsu_lsc_ctl.scala 217:28]
+  assign io_lsu_pkt_m_bits_load_ldst_bypass_d = _T_133_bits_load_ldst_bypass_d; // @[lsu_lsc_ctl.scala 217:28]
+  assign io_lsu_pkt_m_bits_store_data_bypass_m = _T_133_bits_store_data_bypass_m; // @[lsu_lsc_ctl.scala 217:28]
+  assign io_lsu_pkt_r_valid = _T_137; // @[lsu_lsc_ctl.scala 218:28 lsu_lsc_ctl.scala 220:28]
+  assign io_lsu_pkt_r_bits_fast_int = _T_135_bits_fast_int; // @[lsu_lsc_ctl.scala 218:28]
+  assign io_lsu_pkt_r_bits_stack = _T_135_bits_stack; // @[lsu_lsc_ctl.scala 218:28]
+  assign io_lsu_pkt_r_bits_by = _T_135_bits_by; // @[lsu_lsc_ctl.scala 218:28]
+  assign io_lsu_pkt_r_bits_half = _T_135_bits_half; // @[lsu_lsc_ctl.scala 218:28]
+  assign io_lsu_pkt_r_bits_word = _T_135_bits_word; // @[lsu_lsc_ctl.scala 218:28]
+  assign io_lsu_pkt_r_bits_dword = _T_135_bits_dword; // @[lsu_lsc_ctl.scala 218:28]
+  assign io_lsu_pkt_r_bits_load = _T_135_bits_load; // @[lsu_lsc_ctl.scala 218:28]
+  assign io_lsu_pkt_r_bits_store = _T_135_bits_store; // @[lsu_lsc_ctl.scala 218:28]
+  assign io_lsu_pkt_r_bits_unsign = _T_135_bits_unsign; // @[lsu_lsc_ctl.scala 218:28]
+  assign io_lsu_pkt_r_bits_dma = _T_135_bits_dma; // @[lsu_lsc_ctl.scala 218:28]
+  assign io_lsu_pkt_r_bits_store_data_bypass_d = _T_135_bits_store_data_bypass_d; // @[lsu_lsc_ctl.scala 218:28]
+  assign io_lsu_pkt_r_bits_load_ldst_bypass_d = _T_135_bits_load_ldst_bypass_d; // @[lsu_lsc_ctl.scala 218:28]
+  assign io_lsu_pkt_r_bits_store_data_bypass_m = _T_135_bits_store_data_bypass_m; // @[lsu_lsc_ctl.scala 218:28]
+  assign addrcheck_reset = reset;
+  assign addrcheck_io_lsu_c2_m_clk = io_lsu_c2_m_clk; // @[lsu_lsc_ctl.scala 120:42]
+  assign addrcheck_io_start_addr_d = {_T_41,_T_11[11:0]}; // @[lsu_lsc_ctl.scala 122:42]
+  assign addrcheck_io_end_addr_d = rs1_d + _T_65; // @[lsu_lsc_ctl.scala 123:42]
+  assign addrcheck_io_lsu_pkt_d_valid = io_lsu_pkt_d_valid; // @[lsu_lsc_ctl.scala 124:42]
+  assign addrcheck_io_lsu_pkt_d_bits_fast_int = io_lsu_pkt_d_bits_fast_int; // @[lsu_lsc_ctl.scala 124:42]
+  assign addrcheck_io_lsu_pkt_d_bits_by = io_lsu_pkt_d_bits_by; // @[lsu_lsc_ctl.scala 124:42]
+  assign addrcheck_io_lsu_pkt_d_bits_half = io_lsu_pkt_d_bits_half; // @[lsu_lsc_ctl.scala 124:42]
+  assign addrcheck_io_lsu_pkt_d_bits_word = io_lsu_pkt_d_bits_word; // @[lsu_lsc_ctl.scala 124:42]
+  assign addrcheck_io_lsu_pkt_d_bits_load = io_lsu_pkt_d_bits_load; // @[lsu_lsc_ctl.scala 124:42]
+  assign addrcheck_io_lsu_pkt_d_bits_store = io_lsu_pkt_d_bits_store; // @[lsu_lsc_ctl.scala 124:42]
+  assign addrcheck_io_lsu_pkt_d_bits_dma = io_lsu_pkt_d_bits_dma; // @[lsu_lsc_ctl.scala 124:42]
+  assign addrcheck_io_dec_tlu_mrac_ff = io_dec_tlu_mrac_ff; // @[lsu_lsc_ctl.scala 125:42]
+  assign addrcheck_io_rs1_region_d = rs1_d[31:28]; // @[lsu_lsc_ctl.scala 126:42]
+  assign rvclkhdr_io_clk = clock; // @[lib.scala 392:18]
+  assign rvclkhdr_io_en = _T_162 | io_clk_override; // @[lib.scala 393:17]
+  assign rvclkhdr_1_io_clk = clock; // @[lib.scala 392:18]
+  assign rvclkhdr_1_io_en = _T_168 | io_clk_override; // @[lib.scala 393:17]
+  assign rvclkhdr_2_io_clk = clock; // @[lib.scala 392:18]
+  assign rvclkhdr_2_io_en = io_addr_external_m | io_clk_override; // @[lib.scala 393:17]
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+  integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+  `ifdef RANDOMIZE
+    `ifdef INIT_RANDOM
+      `INIT_RANDOM
+    `endif
+    `ifndef VERILATOR
+      `ifdef RANDOMIZE_DELAY
+        #`RANDOMIZE_DELAY begin end
+      `else
+        #0.002 begin end
+      `endif
+    `endif
+`ifdef RANDOMIZE_REG_INIT
+  _RAND_0 = {1{`RANDOM}};
+  access_fault_m = _RAND_0[0:0];
+  _RAND_1 = {1{`RANDOM}};
+  misaligned_fault_m = _RAND_1[0:0];
+  _RAND_2 = {1{`RANDOM}};
+  exc_mscause_m = _RAND_2[3:0];
+  _RAND_3 = {1{`RANDOM}};
+  fir_dccm_access_error_m = _RAND_3[0:0];
+  _RAND_4 = {1{`RANDOM}};
+  fir_nondccm_access_error_m = _RAND_4[0:0];
+  _RAND_5 = {1{`RANDOM}};
+  access_fault_r = _RAND_5[0:0];
+  _RAND_6 = {1{`RANDOM}};
+  misaligned_fault_r = _RAND_6[0:0];
+  _RAND_7 = {1{`RANDOM}};
+  exc_mscause_r = _RAND_7[3:0];
+  _RAND_8 = {1{`RANDOM}};
+  fir_nondccm_access_error_r = _RAND_8[0:0];
+  _RAND_9 = {1{`RANDOM}};
+  fir_dccm_access_error_r = _RAND_9[0:0];
+  _RAND_10 = {1{`RANDOM}};
+  _T_133_bits_fast_int = _RAND_10[0:0];
+  _RAND_11 = {1{`RANDOM}};
+  _T_133_bits_stack = _RAND_11[0:0];
+  _RAND_12 = {1{`RANDOM}};
+  _T_133_bits_by = _RAND_12[0:0];
+  _RAND_13 = {1{`RANDOM}};
+  _T_133_bits_half = _RAND_13[0:0];
+  _RAND_14 = {1{`RANDOM}};
+  _T_133_bits_word = _RAND_14[0:0];
+  _RAND_15 = {1{`RANDOM}};
+  _T_133_bits_dword = _RAND_15[0:0];
+  _RAND_16 = {1{`RANDOM}};
+  _T_133_bits_load = _RAND_16[0:0];
+  _RAND_17 = {1{`RANDOM}};
+  _T_133_bits_store = _RAND_17[0:0];
+  _RAND_18 = {1{`RANDOM}};
+  _T_133_bits_unsign = _RAND_18[0:0];
+  _RAND_19 = {1{`RANDOM}};
+  _T_133_bits_dma = _RAND_19[0:0];
+  _RAND_20 = {1{`RANDOM}};
+  _T_133_bits_store_data_bypass_d = _RAND_20[0:0];
+  _RAND_21 = {1{`RANDOM}};
+  _T_133_bits_load_ldst_bypass_d = _RAND_21[0:0];
+  _RAND_22 = {1{`RANDOM}};
+  _T_133_bits_store_data_bypass_m = _RAND_22[0:0];
+  _RAND_23 = {1{`RANDOM}};
+  _T_135_bits_fast_int = _RAND_23[0:0];
+  _RAND_24 = {1{`RANDOM}};
+  _T_135_bits_stack = _RAND_24[0:0];
+  _RAND_25 = {1{`RANDOM}};
+  _T_135_bits_by = _RAND_25[0:0];
+  _RAND_26 = {1{`RANDOM}};
+  _T_135_bits_half = _RAND_26[0:0];
+  _RAND_27 = {1{`RANDOM}};
+  _T_135_bits_word = _RAND_27[0:0];
+  _RAND_28 = {1{`RANDOM}};
+  _T_135_bits_dword = _RAND_28[0:0];
+  _RAND_29 = {1{`RANDOM}};
+  _T_135_bits_load = _RAND_29[0:0];
+  _RAND_30 = {1{`RANDOM}};
+  _T_135_bits_store = _RAND_30[0:0];
+  _RAND_31 = {1{`RANDOM}};
+  _T_135_bits_unsign = _RAND_31[0:0];
+  _RAND_32 = {1{`RANDOM}};
+  _T_135_bits_dma = _RAND_32[0:0];
+  _RAND_33 = {1{`RANDOM}};
+  _T_135_bits_store_data_bypass_d = _RAND_33[0:0];
+  _RAND_34 = {1{`RANDOM}};
+  _T_135_bits_load_ldst_bypass_d = _RAND_34[0:0];
+  _RAND_35 = {1{`RANDOM}};
+  _T_135_bits_store_data_bypass_m = _RAND_35[0:0];
+  _RAND_36 = {1{`RANDOM}};
+  _T_136 = _RAND_36[0:0];
+  _RAND_37 = {1{`RANDOM}};
+  _T_137 = _RAND_37[0:0];
+  _RAND_38 = {1{`RANDOM}};
+  store_data_pre_m = _RAND_38[31:0];
+  _RAND_39 = {1{`RANDOM}};
+  _T_147 = _RAND_39[31:0];
+  _RAND_40 = {1{`RANDOM}};
+  _T_148 = _RAND_40[31:0];
+  _RAND_41 = {1{`RANDOM}};
+  end_addr_pre_m = _RAND_41[28:0];
+  _RAND_42 = {1{`RANDOM}};
+  _T_153 = _RAND_42[2:0];
+  _RAND_43 = {1{`RANDOM}};
+  end_addr_pre_r = _RAND_43[28:0];
+  _RAND_44 = {1{`RANDOM}};
+  _T_159 = _RAND_44[2:0];
+  _RAND_45 = {1{`RANDOM}};
+  _T_173 = _RAND_45[0:0];
+  _RAND_46 = {1{`RANDOM}};
+  _T_174 = _RAND_46[0:0];
+  _RAND_47 = {1{`RANDOM}};
+  _T_175 = _RAND_47[0:0];
+  _RAND_48 = {1{`RANDOM}};
+  _T_176 = _RAND_48[0:0];
+  _RAND_49 = {1{`RANDOM}};
+  _T_177 = _RAND_49[0:0];
+  _RAND_50 = {1{`RANDOM}};
+  addr_external_r = _RAND_50[0:0];
+  _RAND_51 = {1{`RANDOM}};
+  bus_read_data_r = _RAND_51[31:0];
+`endif // RANDOMIZE_REG_INIT
+  if (reset) begin
+    access_fault_m = 1'h0;
+  end
+  if (reset) begin
+    misaligned_fault_m = 1'h0;
+  end
+  if (reset) begin
+    exc_mscause_m = 4'h0;
+  end
+  if (reset) begin
+    fir_dccm_access_error_m = 1'h0;
+  end
+  if (reset) begin
+    fir_nondccm_access_error_m = 1'h0;
+  end
+  if (reset) begin
+    access_fault_r = 1'h0;
+  end
+  if (reset) begin
+    misaligned_fault_r = 1'h0;
+  end
+  if (reset) begin
+    exc_mscause_r = 4'h0;
+  end
+  if (reset) begin
+    fir_nondccm_access_error_r = 1'h0;
+  end
+  if (reset) begin
+    fir_dccm_access_error_r = 1'h0;
+  end
+  if (reset) begin
+    _T_133_bits_fast_int = 1'h0;
+  end
+  if (reset) begin
+    _T_133_bits_stack = 1'h0;
+  end
+  if (reset) begin
+    _T_133_bits_by = 1'h0;
+  end
+  if (reset) begin
+    _T_133_bits_half = 1'h0;
+  end
+  if (reset) begin
+    _T_133_bits_word = 1'h0;
+  end
+  if (reset) begin
+    _T_133_bits_dword = 1'h0;
+  end
+  if (reset) begin
+    _T_133_bits_load = 1'h0;
+  end
+  if (reset) begin
+    _T_133_bits_store = 1'h0;
+  end
+  if (reset) begin
+    _T_133_bits_unsign = 1'h0;
+  end
+  if (reset) begin
+    _T_133_bits_dma = 1'h0;
+  end
+  if (reset) begin
+    _T_133_bits_store_data_bypass_d = 1'h0;
+  end
+  if (reset) begin
+    _T_133_bits_load_ldst_bypass_d = 1'h0;
+  end
+  if (reset) begin
+    _T_133_bits_store_data_bypass_m = 1'h0;
+  end
+  if (reset) begin
+    _T_135_bits_fast_int = 1'h0;
+  end
+  if (reset) begin
+    _T_135_bits_stack = 1'h0;
+  end
+  if (reset) begin
+    _T_135_bits_by = 1'h0;
+  end
+  if (reset) begin
+    _T_135_bits_half = 1'h0;
+  end
+  if (reset) begin
+    _T_135_bits_word = 1'h0;
+  end
+  if (reset) begin
+    _T_135_bits_dword = 1'h0;
+  end
+  if (reset) begin
+    _T_135_bits_load = 1'h0;
+  end
+  if (reset) begin
+    _T_135_bits_store = 1'h0;
+  end
+  if (reset) begin
+    _T_135_bits_unsign = 1'h0;
+  end
+  if (reset) begin
+    _T_135_bits_dma = 1'h0;
+  end
+  if (reset) begin
+    _T_135_bits_store_data_bypass_d = 1'h0;
+  end
+  if (reset) begin
+    _T_135_bits_load_ldst_bypass_d = 1'h0;
+  end
+  if (reset) begin
+    _T_135_bits_store_data_bypass_m = 1'h0;
+  end
+  if (reset) begin
+    _T_136 = 1'h0;
+  end
+  if (reset) begin
+    _T_137 = 1'h0;
+  end
+  if (reset) begin
+    store_data_pre_m = 32'h0;
+  end
+  if (reset) begin
+    _T_147 = 32'h0;
+  end
+  if (reset) begin
+    _T_148 = 32'h0;
+  end
+  if (reset) begin
+    end_addr_pre_m = 29'h0;
+  end
+  if (reset) begin
+    _T_153 = 3'h0;
+  end
+  if (reset) begin
+    end_addr_pre_r = 29'h0;
+  end
+  if (reset) begin
+    _T_159 = 3'h0;
+  end
+  if (reset) begin
+    _T_173 = 1'h0;
+  end
+  if (reset) begin
+    _T_174 = 1'h0;
+  end
+  if (reset) begin
+    _T_175 = 1'h0;
+  end
+  if (reset) begin
+    _T_176 = 1'h0;
+  end
+  if (reset) begin
+    _T_177 = 1'h0;
+  end
+  if (reset) begin
+    addr_external_r = 1'h0;
+  end
+  if (reset) begin
+    bus_read_data_r = 32'h0;
+  end
+  `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+  always @(posedge io_lsu_c1_m_clk or posedge reset) begin
+    if (reset) begin
+      access_fault_m <= 1'h0;
+    end else begin
+      access_fault_m <= addrcheck_io_access_fault_d;
+    end
+  end
+  always @(posedge io_lsu_c1_m_clk or posedge reset) begin
+    if (reset) begin
+      misaligned_fault_m <= 1'h0;
+    end else begin
+      misaligned_fault_m <= addrcheck_io_misaligned_fault_d;
+    end
+  end
+  always @(posedge io_lsu_c1_m_clk or posedge reset) begin
+    if (reset) begin
+      exc_mscause_m <= 4'h0;
+    end else begin
+      exc_mscause_m <= addrcheck_io_exc_mscause_d;
+    end
+  end
+  always @(posedge io_lsu_c1_m_clk or posedge reset) begin
+    if (reset) begin
+      fir_dccm_access_error_m <= 1'h0;
+    end else begin
+      fir_dccm_access_error_m <= addrcheck_io_fir_dccm_access_error_d;
+    end
+  end
+  always @(posedge io_lsu_c1_m_clk or posedge reset) begin
+    if (reset) begin
+      fir_nondccm_access_error_m <= 1'h0;
+    end else begin
+      fir_nondccm_access_error_m <= addrcheck_io_fir_nondccm_access_error_d;
+    end
+  end
+  always @(posedge io_lsu_c1_r_clk or posedge reset) begin
+    if (reset) begin
+      access_fault_r <= 1'h0;
+    end else begin
+      access_fault_r <= access_fault_m;
+    end
+  end
+  always @(posedge io_lsu_c1_r_clk or posedge reset) begin
+    if (reset) begin
+      misaligned_fault_r <= 1'h0;
+    end else begin
+      misaligned_fault_r <= misaligned_fault_m;
+    end
+  end
+  always @(posedge io_lsu_c1_r_clk or posedge reset) begin
+    if (reset) begin
+      exc_mscause_r <= 4'h0;
+    end else begin
+      exc_mscause_r <= exc_mscause_m;
+    end
+  end
+  always @(posedge io_lsu_c1_r_clk or posedge reset) begin
+    if (reset) begin
+      fir_nondccm_access_error_r <= 1'h0;
+    end else begin
+      fir_nondccm_access_error_r <= fir_nondccm_access_error_m;
+    end
+  end
+  always @(posedge io_lsu_c1_r_clk or posedge reset) begin
+    if (reset) begin
+      fir_dccm_access_error_r <= 1'h0;
+    end else begin
+      fir_dccm_access_error_r <= fir_dccm_access_error_m;
+    end
+  end
+  always @(posedge io_lsu_c1_m_clk or posedge reset) begin
+    if (reset) begin
+      _T_133_bits_fast_int <= 1'h0;
+    end else begin
+      _T_133_bits_fast_int <= io_lsu_pkt_d_bits_fast_int;
+    end
+  end
+  always @(posedge io_lsu_c1_m_clk or posedge reset) begin
+    if (reset) begin
+      _T_133_bits_stack <= 1'h0;
+    end else begin
+      _T_133_bits_stack <= io_lsu_pkt_d_bits_stack;
+    end
+  end
+  always @(posedge io_lsu_c1_m_clk or posedge reset) begin
+    if (reset) begin
+      _T_133_bits_by <= 1'h0;
+    end else begin
+      _T_133_bits_by <= io_lsu_pkt_d_bits_by;
+    end
+  end
+  always @(posedge io_lsu_c1_m_clk or posedge reset) begin
+    if (reset) begin
+      _T_133_bits_half <= 1'h0;
+    end else begin
+      _T_133_bits_half <= io_lsu_pkt_d_bits_half;
+    end
+  end
+  always @(posedge io_lsu_c1_m_clk or posedge reset) begin
+    if (reset) begin
+      _T_133_bits_word <= 1'h0;
+    end else begin
+      _T_133_bits_word <= io_lsu_pkt_d_bits_word;
+    end
+  end
+  always @(posedge io_lsu_c1_m_clk or posedge reset) begin
+    if (reset) begin
+      _T_133_bits_dword <= 1'h0;
+    end else begin
+      _T_133_bits_dword <= io_lsu_pkt_d_bits_dword;
+    end
+  end
+  always @(posedge io_lsu_c1_m_clk or posedge reset) begin
+    if (reset) begin
+      _T_133_bits_load <= 1'h0;
+    end else begin
+      _T_133_bits_load <= io_lsu_pkt_d_bits_load;
+    end
+  end
+  always @(posedge io_lsu_c1_m_clk or posedge reset) begin
+    if (reset) begin
+      _T_133_bits_store <= 1'h0;
+    end else begin
+      _T_133_bits_store <= io_lsu_pkt_d_bits_store;
+    end
+  end
+  always @(posedge io_lsu_c1_m_clk or posedge reset) begin
+    if (reset) begin
+      _T_133_bits_unsign <= 1'h0;
+    end else begin
+      _T_133_bits_unsign <= io_lsu_pkt_d_bits_unsign;
+    end
+  end
+  always @(posedge io_lsu_c1_m_clk or posedge reset) begin
+    if (reset) begin
+      _T_133_bits_dma <= 1'h0;
+    end else begin
+      _T_133_bits_dma <= io_lsu_pkt_d_bits_dma;
+    end
+  end
+  always @(posedge io_lsu_c1_m_clk or posedge reset) begin
+    if (reset) begin
+      _T_133_bits_store_data_bypass_d <= 1'h0;
+    end else begin
+      _T_133_bits_store_data_bypass_d <= io_lsu_pkt_d_bits_store_data_bypass_d;
+    end
+  end
+  always @(posedge io_lsu_c1_m_clk or posedge reset) begin
+    if (reset) begin
+      _T_133_bits_load_ldst_bypass_d <= 1'h0;
+    end else begin
+      _T_133_bits_load_ldst_bypass_d <= io_lsu_pkt_d_bits_load_ldst_bypass_d;
+    end
+  end
+  always @(posedge io_lsu_c1_m_clk or posedge reset) begin
+    if (reset) begin
+      _T_133_bits_store_data_bypass_m <= 1'h0;
+    end else begin
+      _T_133_bits_store_data_bypass_m <= io_lsu_pkt_d_bits_store_data_bypass_m;
+    end
+  end
+  always @(posedge io_lsu_c1_r_clk or posedge reset) begin
+    if (reset) begin
+      _T_135_bits_fast_int <= 1'h0;
+    end else begin
+      _T_135_bits_fast_int <= io_lsu_pkt_m_bits_fast_int;
+    end
+  end
+  always @(posedge io_lsu_c1_r_clk or posedge reset) begin
+    if (reset) begin
+      _T_135_bits_stack <= 1'h0;
+    end else begin
+      _T_135_bits_stack <= io_lsu_pkt_m_bits_stack;
+    end
+  end
+  always @(posedge io_lsu_c1_r_clk or posedge reset) begin
+    if (reset) begin
+      _T_135_bits_by <= 1'h0;
+    end else begin
+      _T_135_bits_by <= io_lsu_pkt_m_bits_by;
+    end
+  end
+  always @(posedge io_lsu_c1_r_clk or posedge reset) begin
+    if (reset) begin
+      _T_135_bits_half <= 1'h0;
+    end else begin
+      _T_135_bits_half <= io_lsu_pkt_m_bits_half;
+    end
+  end
+  always @(posedge io_lsu_c1_r_clk or posedge reset) begin
+    if (reset) begin
+      _T_135_bits_word <= 1'h0;
+    end else begin
+      _T_135_bits_word <= io_lsu_pkt_m_bits_word;
+    end
+  end
+  always @(posedge io_lsu_c1_r_clk or posedge reset) begin
+    if (reset) begin
+      _T_135_bits_dword <= 1'h0;
+    end else begin
+      _T_135_bits_dword <= io_lsu_pkt_m_bits_dword;
+    end
+  end
+  always @(posedge io_lsu_c1_r_clk or posedge reset) begin
+    if (reset) begin
+      _T_135_bits_load <= 1'h0;
+    end else begin
+      _T_135_bits_load <= io_lsu_pkt_m_bits_load;
+    end
+  end
+  always @(posedge io_lsu_c1_r_clk or posedge reset) begin
+    if (reset) begin
+      _T_135_bits_store <= 1'h0;
+    end else begin
+      _T_135_bits_store <= io_lsu_pkt_m_bits_store;
+    end
+  end
+  always @(posedge io_lsu_c1_r_clk or posedge reset) begin
+    if (reset) begin
+      _T_135_bits_unsign <= 1'h0;
+    end else begin
+      _T_135_bits_unsign <= io_lsu_pkt_m_bits_unsign;
+    end
+  end
+  always @(posedge io_lsu_c1_r_clk or posedge reset) begin
+    if (reset) begin
+      _T_135_bits_dma <= 1'h0;
+    end else begin
+      _T_135_bits_dma <= io_lsu_pkt_m_bits_dma;
+    end
+  end
+  always @(posedge io_lsu_c1_r_clk or posedge reset) begin
+    if (reset) begin
+      _T_135_bits_store_data_bypass_d <= 1'h0;
+    end else begin
+      _T_135_bits_store_data_bypass_d <= io_lsu_pkt_m_bits_store_data_bypass_d;
+    end
+  end
+  always @(posedge io_lsu_c1_r_clk or posedge reset) begin
+    if (reset) begin
+      _T_135_bits_load_ldst_bypass_d <= 1'h0;
+    end else begin
+      _T_135_bits_load_ldst_bypass_d <= io_lsu_pkt_m_bits_load_ldst_bypass_d;
+    end
+  end
+  always @(posedge io_lsu_c1_r_clk or posedge reset) begin
+    if (reset) begin
+      _T_135_bits_store_data_bypass_m <= 1'h0;
+    end else begin
+      _T_135_bits_store_data_bypass_m <= io_lsu_pkt_m_bits_store_data_bypass_m;
+    end
+  end
+  always @(posedge io_lsu_c2_m_clk or posedge reset) begin
+    if (reset) begin
+      _T_136 <= 1'h0;
+    end else begin
+      _T_136 <= io_lsu_pkt_d_valid & _T_126;
+    end
+  end
+  always @(posedge io_lsu_c2_r_clk or posedge reset) begin
+    if (reset) begin
+      _T_137 <= 1'h0;
+    end else begin
+      _T_137 <= io_lsu_pkt_m_valid & _T_130;
+    end
+  end
+  always @(posedge io_lsu_store_c1_m_clk or posedge reset) begin
+    if (reset) begin
+      store_data_pre_m <= 32'h0;
+    end else if (io_lsu_pkt_d_bits_store_data_bypass_d) begin
+      store_data_pre_m <= io_lsu_result_m;
+    end else if (io_dma_lsc_ctl_dma_dccm_req) begin
+      store_data_pre_m <= dma_mem_wdata_shifted[31:0];
+    end else begin
+      store_data_pre_m <= io_lsu_exu_exu_lsu_rs2_d;
+    end
+  end
+  always @(posedge io_lsu_c1_m_clk or posedge reset) begin
+    if (reset) begin
+      _T_147 <= 32'h0;
+    end else begin
+      _T_147 <= io_lsu_addr_d;
+    end
+  end
+  always @(posedge io_lsu_c1_r_clk or posedge reset) begin
+    if (reset) begin
+      _T_148 <= 32'h0;
+    end else begin
+      _T_148 <= io_lsu_addr_m;
+    end
+  end
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      end_addr_pre_m <= 29'h0;
+    end else if (_T_163) begin
+      end_addr_pre_m <= io_end_addr_d[31:3];
+    end
+  end
+  always @(posedge io_lsu_c1_m_clk or posedge reset) begin
+    if (reset) begin
+      _T_153 <= 3'h0;
+    end else begin
+      _T_153 <= io_end_addr_d[2:0];
+    end
+  end
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      end_addr_pre_r <= 29'h0;
+    end else if (_T_169) begin
+      end_addr_pre_r <= io_end_addr_m[31:3];
+    end
+  end
+  always @(posedge io_lsu_c1_r_clk or posedge reset) begin
+    if (reset) begin
+      _T_159 <= 3'h0;
+    end else begin
+      _T_159 <= io_end_addr_m[2:0];
+    end
+  end
+  always @(posedge io_lsu_c1_m_clk or posedge reset) begin
+    if (reset) begin
+      _T_173 <= 1'h0;
+    end else begin
+      _T_173 <= io_addr_in_dccm_d;
+    end
+  end
+  always @(posedge io_lsu_c1_r_clk or posedge reset) begin
+    if (reset) begin
+      _T_174 <= 1'h0;
+    end else begin
+      _T_174 <= io_addr_in_dccm_m;
+    end
+  end
+  always @(posedge io_lsu_c1_m_clk or posedge reset) begin
+    if (reset) begin
+      _T_175 <= 1'h0;
+    end else begin
+      _T_175 <= io_addr_in_pic_d;
+    end
+  end
+  always @(posedge io_lsu_c1_r_clk or posedge reset) begin
+    if (reset) begin
+      _T_176 <= 1'h0;
+    end else begin
+      _T_176 <= io_addr_in_pic_m;
+    end
+  end
+  always @(posedge io_lsu_c1_m_clk or posedge reset) begin
+    if (reset) begin
+      _T_177 <= 1'h0;
+    end else begin
+      _T_177 <= addrcheck_io_addr_external_d;
+    end
+  end
+  always @(posedge io_lsu_c1_r_clk or posedge reset) begin
+    if (reset) begin
+      addr_external_r <= 1'h0;
+    end else begin
+      addr_external_r <= io_addr_external_m;
+    end
+  end
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      bus_read_data_r <= 32'h0;
+    end else if (_T_178) begin
+      bus_read_data_r <= io_bus_read_data_m;
+    end
+  end
+endmodule
diff --git a/src/main/scala/lib/param.scala b/src/main/scala/lib/param.scala
index f83a2b50..3ad7a337 100644
--- a/src/main/scala/lib/param.scala
+++ b/src/main/scala/lib/param.scala
@@ -132,7 +132,7 @@ trait param {
   val INST_ACCESS_MASK5      = 	0xFFFFFFFF
   val INST_ACCESS_MASK6      = 	0xFFFFFFFF
   val INST_ACCESS_MASK7      = 	0xFFFFFFFF
-  val LOAD_TO_USE_PLUS1      = 	0x0
+  val LOAD_TO_USE_PLUS1      = 	0x1
   val LSU2DMA                = 	0x0
   val LSU_BUS_ID             = 	0x1
   val LSU_BUS_PRTY           = 	0x2
diff --git a/src/main/scala/lsu/lsu.scala b/src/main/scala/lsu/lsu.scala
index f87da91c..3f568b1c 100644
--- a/src/main/scala/lsu/lsu.scala
+++ b/src/main/scala/lsu/lsu.scala
@@ -37,7 +37,7 @@ class lsu extends Module with RequireAsyncReset with param with lib {
     val lsu_store_stall_any               = Output(Bool())
     val lsu_fastint_stall_any             = Output(Bool())
     val lsu_idle_any                      = Output(Bool())
-    val lsu_active                      = Output(Bool())
+    val lsu_active                       = Output(Bool())
     val lsu_fir_addr                      = Output(UInt(31.W))
     val lsu_fir_error                     = Output(UInt(2.W))
     val lsu_single_ecc_error_incr         = Output(Bool())
@@ -59,8 +59,13 @@ class lsu extends Module with RequireAsyncReset with param with lib {
   val lsu_raw_fwd_hi_r             = WireInit(0.U(1.W))
   val lsu_busm_clken               = WireInit(0.U(1.W))
   val lsu_bus_obuf_c1_clken        = WireInit(0.U(1.W))
-
-
+  val lsu_addr_d            = WireInit(0.U(32.W))
+  val lsu_addr_m            = WireInit(0.U(32.W))
+  val lsu_addr_r            = WireInit(0.U(32.W))
+  val end_addr_d            = WireInit(0.U(32.W))
+  val end_addr_m            = WireInit(0.U(32.W))
+  val end_addr_r            = WireInit(0.U(32.W))
+  val lsu_busreq_r          = WireInit(Bool(),false.B)
 
   val lsu_lsc_ctl    = Module(new lsu_lsc_ctl())
   io.lsu_result_m := lsu_lsc_ctl.io.lsu_result_m
@@ -107,9 +112,9 @@ class lsu extends Module with RequireAsyncReset with param with lib {
   // Bus signals
   val lsu_busreq_m = lsu_lsc_ctl.io.lsu_pkt_m.valid & ((lsu_lsc_ctl.io.lsu_pkt_m.bits.load | lsu_lsc_ctl.io.lsu_pkt_m.bits.store) & lsu_lsc_ctl.io.addr_external_m) & !flush_m_up & !lsu_lsc_ctl.io.lsu_exc_m & !lsu_lsc_ctl.io.lsu_pkt_m.bits.fast_int
   // Dual signals
-  val ldst_dual_d  = lsu_lsc_ctl.io.lsu_addr_d(2) =/= lsu_lsc_ctl.io.end_addr_d(2)
-  val ldst_dual_m  = lsu_lsc_ctl.io.lsu_addr_m(2) =/= lsu_lsc_ctl.io.end_addr_m(2)
-  val ldst_dual_r  = lsu_lsc_ctl.io.lsu_addr_r(2) =/= lsu_lsc_ctl.io.end_addr_r(2)
+  val ldst_dual_d  = lsu_addr_d(2) =/= end_addr_d(2)
+  val ldst_dual_m  = lsu_addr_m(2) =/= end_addr_m(2)
+  val ldst_dual_r  = lsu_addr_r(2) =/= end_addr_r(2)
   // PMU signals
   io.lsu_pmu_misaligned_m := lsu_lsc_ctl.io.lsu_pkt_m.valid & ((lsu_lsc_ctl.io.lsu_pkt_m.bits.half & lsu_lsc_ctl.io.lsu_addr_m(0)) | (lsu_lsc_ctl.io.lsu_pkt_m.bits.word & lsu_lsc_ctl.io.lsu_addr_m(1,0).orR))
   io.lsu_tlu.lsu_pmu_load_external_m  := lsu_lsc_ctl.io.lsu_pkt_m.valid & lsu_lsc_ctl.io.lsu_pkt_m.bits.load & lsu_lsc_ctl.io.addr_external_m
@@ -141,11 +146,16 @@ class lsu extends Module with RequireAsyncReset with param with lib {
   lsu_lsc_ctl.io.dec_lsu_offset_d            := io.dec_lsu_offset_d
   lsu_lsc_ctl.io.picm_mask_data_m            := dccm_ctl.io.picm_mask_data_m
   lsu_lsc_ctl.io.bus_read_data_m             := bus_intf.io.bus_read_data_m
-  lsu_lsc_ctl.io.dma_lsc_ctl         <> io.lsu_dma.dma_lsc_ctl
+  lsu_lsc_ctl.io.dma_lsc_ctl                 <> io.lsu_dma.dma_lsc_ctl
   lsu_lsc_ctl.io.dec_tlu_mrac_ff             := io.dec_tlu_mrac_ff
   lsu_lsc_ctl.io.scan_mode                   := io.scan_mode
   //Outputs
-
+  lsu_addr_d := lsu_lsc_ctl.io.lsu_addr_d
+  lsu_addr_m := lsu_lsc_ctl.io.lsu_addr_m
+  lsu_addr_r := lsu_lsc_ctl.io.lsu_addr_r
+  end_addr_d := lsu_lsc_ctl.io.lsu_addr_d
+  end_addr_m := lsu_lsc_ctl.io.lsu_addr_m
+  end_addr_r := lsu_lsc_ctl.io.lsu_addr_r
   io.lsu_single_ecc_error_incr                  := lsu_lsc_ctl.io.lsu_single_ecc_error_incr
   io.lsu_error_pkt_r                            <> lsu_lsc_ctl.io.lsu_error_pkt_r
   io.lsu_fir_addr                               <> lsu_lsc_ctl.io.lsu_fir_addr
@@ -172,12 +182,12 @@ class lsu extends Module with RequireAsyncReset with param with lib {
   dccm_ctl.io.lsu_raw_fwd_lo_r               := lsu_raw_fwd_lo_r
   dccm_ctl.io.lsu_raw_fwd_hi_r               := lsu_raw_fwd_hi_r
   dccm_ctl.io.lsu_commit_r                   := lsu_lsc_ctl.io.lsu_commit_r
-  dccm_ctl.io.lsu_addr_d                     := lsu_lsc_ctl.io.lsu_addr_d
-  dccm_ctl.io.lsu_addr_m                     := lsu_lsc_ctl.io.lsu_addr_m
-  dccm_ctl.io.lsu_addr_r                     := lsu_lsc_ctl.io.lsu_addr_r
-  dccm_ctl.io.end_addr_d                     := lsu_lsc_ctl.io.end_addr_d
-  dccm_ctl.io.end_addr_m                     := lsu_lsc_ctl.io.end_addr_m
-  dccm_ctl.io.end_addr_r                     := lsu_lsc_ctl.io.end_addr_r
+  dccm_ctl.io.lsu_addr_d                     := lsu_addr_d
+  dccm_ctl.io.lsu_addr_m                     := lsu_addr_m(DCCM_BITS-1,0)
+  dccm_ctl.io.lsu_addr_r                     := lsu_addr_r
+  dccm_ctl.io.end_addr_d                     := end_addr_d(DCCM_BITS-1,0)
+  dccm_ctl.io.end_addr_m                     := end_addr_m(DCCM_BITS-1,0)
+  dccm_ctl.io.end_addr_r                     := end_addr_r(DCCM_BITS-1,0)
   dccm_ctl.io.stbuf_reqvld_any               := stbuf.io.stbuf_reqvld_any
   dccm_ctl.io.stbuf_addr_any                 := stbuf.io.stbuf_addr_any
   dccm_ctl.io.stbuf_data_any                 := stbuf.io.stbuf_data_any
@@ -228,10 +238,10 @@ class lsu extends Module with RequireAsyncReset with param with lib {
   stbuf.io.store_datafn_hi_r                    := dccm_ctl.io.store_datafn_hi_r
   stbuf.io.store_datafn_lo_r	  	               := dccm_ctl.io.store_datafn_lo_r
   stbuf.io.lsu_stbuf_commit_any	  	           := dccm_ctl.io.lsu_stbuf_commit_any
-  stbuf.io.lsu_addr_d	   	  		               := lsu_lsc_ctl.io.lsu_addr_d
+  stbuf.io.lsu_addr_d	   	  		               := lsu_addr_d
   stbuf.io.lsu_addr_m	   	  		               := lsu_lsc_ctl.io.lsu_addr_m
   stbuf.io.lsu_addr_r	   	  		               := lsu_lsc_ctl.io.lsu_addr_r
-  stbuf.io.end_addr_d	   	  		               := lsu_lsc_ctl.io.end_addr_d
+  stbuf.io.end_addr_d	   	  		               := end_addr_d
   stbuf.io.end_addr_m	   	  		               := lsu_lsc_ctl.io.end_addr_m
   stbuf.io.end_addr_r	   	  		               := lsu_lsc_ctl.io.end_addr_r
   stbuf.io.addr_in_dccm_m                       := lsu_lsc_ctl.io.addr_in_dccm_m
@@ -249,10 +259,10 @@ class lsu extends Module with RequireAsyncReset with param with lib {
   ecc.io.dec_tlu_core_ecc_disable                := io.dec_tlu_core_ecc_disable
   ecc.io.lsu_dccm_rden_r        	               := dccm_ctl.io.lsu_dccm_rden_r
   ecc.io.addr_in_dccm_r                          := lsu_lsc_ctl.io.addr_in_dccm_r
-  ecc.io.lsu_addr_r	   	                         := lsu_lsc_ctl.io.lsu_addr_r
-  ecc.io.end_addr_r	   	                         := lsu_lsc_ctl.io.end_addr_r
-  ecc.io.lsu_addr_m	   	                         := lsu_lsc_ctl.io.lsu_addr_m
-  ecc.io.end_addr_m	   	                         := lsu_lsc_ctl.io.end_addr_m
+  ecc.io.lsu_addr_r	   	                         := lsu_addr_r
+  ecc.io.end_addr_r	   	                         := end_addr_r
+  ecc.io.lsu_addr_m	   	                         := lsu_addr_m
+  ecc.io.end_addr_m	   	                         := end_addr_m
   ecc.io.dccm_rdata_hi_r   	                     := dccm_ctl.io.dccm_rdata_hi_r
   ecc.io.dccm_rdata_lo_r   	                     := dccm_ctl.io.dccm_rdata_lo_r
   ecc.io.dccm_rdata_hi_m   	                     := dccm_ctl.io.dccm_rdata_hi_m
@@ -319,11 +329,11 @@ class lsu extends Module with RequireAsyncReset with param with lib {
   bus_intf.io.ldst_dual_d                       := ldst_dual_d
   bus_intf.io.ldst_dual_m                       := ldst_dual_m
   bus_intf.io.ldst_dual_r                       := ldst_dual_r
-  bus_intf.io.lsu_addr_m                        := lsu_lsc_ctl.io.lsu_addr_m
-  bus_intf.io.lsu_addr_r                        := lsu_lsc_ctl.io.lsu_addr_r
-  bus_intf.io.end_addr_m                        := lsu_lsc_ctl.io.end_addr_m
-  bus_intf.io.end_addr_r                        := lsu_lsc_ctl.io.end_addr_r
-  bus_intf.io.store_data_r                      := dccm_ctl.io.store_data_r
+  bus_intf.io.lsu_addr_m                        := lsu_addr_m & Fill(32,lsu_lsc_ctl.io.addr_external_m & lsu_lsc_ctl.io.lsu_pkt_m.valid)
+  bus_intf.io.lsu_addr_r                        := lsu_addr_r & Fill(32,lsu_busreq_r)
+  bus_intf.io.end_addr_m                        := end_addr_m & Fill(32,lsu_lsc_ctl.io.addr_external_m & lsu_lsc_ctl.io.lsu_pkt_m.valid)
+  bus_intf.io.end_addr_r                        := end_addr_r & Fill(32,lsu_busreq_r)
+  bus_intf.io.store_data_r                      := dccm_ctl.io.store_data_r &  Fill(32,lsu_busreq_r)
   bus_intf.io.lsu_pkt_m                         <> lsu_lsc_ctl.io.lsu_pkt_m
   bus_intf.io.lsu_pkt_r                         <> lsu_lsc_ctl.io.lsu_pkt_r
   bus_intf.io.dec_tlu_force_halt                := io.dec_tlu_force_halt
@@ -333,6 +343,7 @@ class lsu extends Module with RequireAsyncReset with param with lib {
   bus_intf.io.flush_r                           := flush_r
   //Outputs
   io.lsu_dec.dctl_busbuff <> bus_intf.io.dctl_busbuff
+  lsu_busreq_r := bus_intf.io.lsu_busreq_r
   io.axi                                        <> bus_intf.io.axi
   bus_intf.io.lsu_bus_clk_en                    := io.lsu_bus_clk_en
 
diff --git a/src/main/scala/lsu/lsu_dccm_ctl.scala b/src/main/scala/lsu/lsu_dccm_ctl.scala
index 4ea66912..c4fe5636 100644
--- a/src/main/scala/lsu/lsu_dccm_ctl.scala
+++ b/src/main/scala/lsu/lsu_dccm_ctl.scala
@@ -118,7 +118,7 @@ class  lsu_dccm_ctl extends Module with RequireAsyncReset with lib
   val ld_single_ecc_error_lo_r_ff = WireInit(UInt(1.W),0.U)
   val ld_sec_addr_hi_r_ff = WireInit(UInt(DCCM_BITS.W),0.U)
   val ld_sec_addr_lo_r_ff = WireInit(UInt(DCCM_BITS.W),0.U)
-
+  io.lsu_ld_data_m :=0.U
   //Forwarding stbuf
   if (LOAD_TO_USE_PLUS1 == 1){
     io.dma_dccm_ctl.dccm_dma_rvalid    := io.lsu_pkt_r.valid & io.lsu_pkt_r.bits.load & io.lsu_pkt_r.bits.dma
diff --git a/src/main/scala/lsu/lsu_lsc_ctl.scala b/src/main/scala/lsu/lsu_lsc_ctl.scala
index e2126b9e..9c9ad2af 100644
--- a/src/main/scala/lsu/lsu_lsc_ctl.scala
+++ b/src/main/scala/lsu/lsu_lsc_ctl.scala
@@ -1,10 +1,8 @@
 package lsu
-import include._
+import include.{lsu_error_pkt_t, _}
 import lib._
 import chisel3._
 import chisel3.util._
-
-
 import chisel3.experimental.chiselName
 @chiselName
 class  lsu_lsc_ctl extends Module with RequireAsyncReset with lib
@@ -77,7 +75,7 @@ class  lsu_lsc_ctl extends Module with RequireAsyncReset with lib
     val addr_in_pic_m     = Output(UInt(1.W))
     val addr_in_pic_r     = Output(UInt(1.W))
 
-    val addr_external_m   = Output(UInt(1.W))
+    val addr_external_m   = Output(Bool())
 
     // DMA slave
     val dma_lsc_ctl = new dma_lsc_ctl()
@@ -96,6 +94,7 @@ class  lsu_lsc_ctl extends Module with RequireAsyncReset with lib
   val lsu_pkt_m_in    = Wire(Valid(new lsu_pkt_t()))
   val lsu_pkt_r_in    = Wire(Valid(new lsu_pkt_t()))
   val lsu_error_pkt_m = Wire(Valid(new lsu_error_pkt_t()))
+  lsu_error_pkt_m  := 0.U.asTypeOf(lsu_error_pkt_m)
 
   val lsu_rs1_d       = Mux(io.dec_lsu_valid_raw_d.asBool,io.lsu_exu.exu_lsu_rs1_d,io.dma_lsc_ctl.dma_mem_addr)
   val lsu_offset_d    = io.dec_lsu_offset_d(11,0) & Fill(12,io.dec_lsu_valid_raw_d)
@@ -248,8 +247,8 @@ class  lsu_lsc_ctl extends Module with RequireAsyncReset with lib
 
   if (LOAD_TO_USE_PLUS1 == 1){
     //bus_read_data_r coming from bus interface, lsu_ld_data_r -> coming from dccm_ctl
-    lsu_ld_datafn_r       := Mux(addr_external_r.asBool, bus_read_data_r,io.lsu_ld_data_r)
-    lsu_ld_datafn_corr_r  := Mux(addr_external_r.asBool, bus_read_data_r,io.lsu_ld_data_corr_r)
+    lsu_ld_datafn_r       := Mux(addr_external_r, bus_read_data_r,io.lsu_ld_data_r)
+    lsu_ld_datafn_corr_r  := Mux(addr_external_r, bus_read_data_r,io.lsu_ld_data_corr_r)
     // this is really R stage but don't want to make all the changes to support M,R buses
     io.lsu_result_m       := ((Fill(32,io.lsu_pkt_r.bits.unsign  & io.lsu_pkt_r.bits.by))    & Cat(0.U(24.W),lsu_ld_datafn_r(7,0))) |
       ((Fill(32,io.lsu_pkt_r.bits.unsign  & io.lsu_pkt_r.bits.half))  & Cat(0.U(16.W),lsu_ld_datafn_r(15,0)))    |
@@ -265,7 +264,7 @@ class  lsu_lsc_ctl extends Module with RequireAsyncReset with lib
   }
 
   else  {
-    lsu_ld_datafn_m       := Mux(io.addr_external_m.asBool, io.bus_read_data_m,io.lsu_ld_data_m)
+    lsu_ld_datafn_m       := Mux(io.addr_external_m, io.bus_read_data_m,io.lsu_ld_data_m)
     lsu_ld_datafn_corr_r  := Mux(addr_external_r===1.U, bus_read_data_r,io.lsu_ld_data_corr_r)
     io.lsu_result_m       := ((Fill(32,io.lsu_pkt_m.bits.unsign  & io.lsu_pkt_m.bits.by))    & Cat(0.U(24.W),lsu_ld_datafn_m(7,0))) |
       ((Fill(32,io.lsu_pkt_m.bits.unsign  & io.lsu_pkt_m.bits.half))  & Cat(0.U(16.W),lsu_ld_datafn_m(15,0)))    |
diff --git a/target/scala-2.12/classes/exu/exu_div_ctl.class b/target/scala-2.12/classes/exu/exu_div_ctl.class
index 8064557b..cc11e0d0 100644
Binary files a/target/scala-2.12/classes/exu/exu_div_ctl.class and b/target/scala-2.12/classes/exu/exu_div_ctl.class differ
diff --git a/target/scala-2.12/classes/lib/param.class b/target/scala-2.12/classes/lib/param.class
index 2b3d92ba..bb016162 100644
Binary files a/target/scala-2.12/classes/lib/param.class and b/target/scala-2.12/classes/lib/param.class differ
diff --git a/target/scala-2.12/classes/lsu/lsc_ctl$.class b/target/scala-2.12/classes/lsu/lsc_ctl$.class
index ad18ccbd..21ac31c6 100644
Binary files a/target/scala-2.12/classes/lsu/lsc_ctl$.class and b/target/scala-2.12/classes/lsu/lsc_ctl$.class differ
diff --git a/target/scala-2.12/classes/lsu/lsc_ctl$delayedInit$body.class b/target/scala-2.12/classes/lsu/lsc_ctl$delayedInit$body.class
index 2a406ce1..050f2098 100644
Binary files a/target/scala-2.12/classes/lsu/lsc_ctl$delayedInit$body.class and b/target/scala-2.12/classes/lsu/lsc_ctl$delayedInit$body.class differ
diff --git a/target/scala-2.12/classes/lsu/lsu.class b/target/scala-2.12/classes/lsu/lsu.class
index 9b679ab2..94d8760e 100644
Binary files a/target/scala-2.12/classes/lsu/lsu.class and b/target/scala-2.12/classes/lsu/lsu.class differ
diff --git a/target/scala-2.12/classes/lsu/lsu_dccm_ctl.class b/target/scala-2.12/classes/lsu/lsu_dccm_ctl.class
index 578783ce..8ecb307f 100644
Binary files a/target/scala-2.12/classes/lsu/lsu_dccm_ctl.class and b/target/scala-2.12/classes/lsu/lsu_dccm_ctl.class differ
diff --git a/target/scala-2.12/classes/lsu/lsu_lsc_ctl$$anon$1.class b/target/scala-2.12/classes/lsu/lsu_lsc_ctl$$anon$1.class
index 6ff8a6b6..c8378277 100644
Binary files a/target/scala-2.12/classes/lsu/lsu_lsc_ctl$$anon$1.class and b/target/scala-2.12/classes/lsu/lsu_lsc_ctl$$anon$1.class differ
diff --git a/target/scala-2.12/classes/lsu/lsu_lsc_ctl.class b/target/scala-2.12/classes/lsu/lsu_lsc_ctl.class
index 7c3d3b1b..9a803013 100644
Binary files a/target/scala-2.12/classes/lsu/lsu_lsc_ctl.class and b/target/scala-2.12/classes/lsu/lsu_lsc_ctl.class differ
diff --git a/target/scala-2.12/classes/lsu/lsu_main$.class b/target/scala-2.12/classes/lsu/lsu_main$.class
index c308993a..2a219e2f 100644
Binary files a/target/scala-2.12/classes/lsu/lsu_main$.class and b/target/scala-2.12/classes/lsu/lsu_main$.class differ
diff --git a/target/scala-2.12/classes/lsu/lsu_main$delayedInit$body.class b/target/scala-2.12/classes/lsu/lsu_main$delayedInit$body.class
index a8bc3aa8..57b78280 100644
Binary files a/target/scala-2.12/classes/lsu/lsu_main$delayedInit$body.class and b/target/scala-2.12/classes/lsu/lsu_main$delayedInit$body.class differ