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Predictor Updated

This commit is contained in:
waleed-lm 2020-10-07 17:40:57 +05:00
parent b5e114bfc4
commit bed619330b
4 changed files with 25466 additions and 25400 deletions
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39182
el2_ifu_bp_ctl.fir
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11678
el2_ifu_bp_ctl.v
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6
src/main/scala/ifu/el2_ifu_bp_ctl.scala
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@ -372,9 +372,9 @@ class el2_ifu_bp_ctl extends Module with el2_lib with RequireAsyncReset {
btb_bank0_rd_data_way1_p1_f := Mux1H((0 until LRU_SIZE).map(i=>(btb_rd_addr_p1_f===i.U).asBool->btb_bank0_rd_data_way1_out(i))) btb_bank0_rd_data_way1_p1_f := Mux1H((0 until LRU_SIZE).map(i=>(btb_rd_addr_p1_f===i.U).asBool->btb_bank0_rd_data_way1_out(i)))
val bht_bank_clken = Wire(Vec(2, Vec(BHT_ARRAY_DEPTH/NUM_BHT_LOOP, Bool()))) val bht_bank_clken = Wire(Vec(2, Vec(BHT_ARRAY_DEPTH/NUM_BHT_LOOP, Bool())))
for(i<-0 until 2; k<- 0 until BHT_ARRAY_DEPTH/NUM_BHT_LOOP){ for(i<-0 until 2; k<- 0 until (BHT_ARRAY_DEPTH/NUM_BHT_LOOP)){
bht_bank_clken(i)(k) := (bht_wr_en0(i) & ((bht_wr_addr0===k.U) | BHT_NO_ADDR_MATCH.B)) | bht_bank_clken(i)(k) := (bht_wr_en0(i) & ((bht_wr_addr0(BHT_ADDR_HI-BHT_ADDR_LO,NUM_BHT_LOOP_OUTER_LO-1)===k.U) | BHT_NO_ADDR_MATCH.B)) |
(bht_wr_en2(i) & ((bht_wr_addr2===k.U) | BHT_NO_ADDR_MATCH.B)) (bht_wr_en2(i) & ((bht_wr_addr2(BHT_ADDR_HI-BHT_ADDR_LO,NUM_BHT_LOOP_OUTER_LO-1)===k.U) | BHT_NO_ADDR_MATCH.B))
} }
val bht_bank_wr_data = (0 until 2).map(i=>(0 until BHT_ARRAY_DEPTH/NUM_BHT_LOOP).map(k=>(0 until NUM_BHT_LOOP).map(j=> val bht_bank_wr_data = (0 until 2).map(i=>(0 until BHT_ARRAY_DEPTH/NUM_BHT_LOOP).map(k=>(0 until NUM_BHT_LOOP).map(j=>

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target/scala-2.12/classes/ifu/el2_ifu_bp_ctl.class
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