From c0504d57a09d92a0d784d060dd5b11bdcad1478a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E2=80=8BLaraib=20Khan?= <​laraib.khan@lampromellon.com> Date: Thu, 24 Dec 2020 10:49:31 +0500 Subject: [PATCH] end_addr_r updated --- lsu_lsc_ctl.fir | 2 +- lsu_lsc_ctl.v | 2 +- src/main/scala/lsu/lsu_lsc_ctl.scala | 2 +- .../scala-2.12/classes/lsu/lsu_lsc_ctl.class | Bin 329444 -> 329444 bytes 4 files changed, 3 insertions(+), 3 deletions(-) diff --git a/lsu_lsc_ctl.fir b/lsu_lsc_ctl.fir index 7234ac12..ee6e05f0 100644 --- a/lsu_lsc_ctl.fir +++ b/lsu_lsc_ctl.fir @@ -788,7 +788,7 @@ circuit lsu_lsc_ctl : node _T_161 = bits(io.lsu_addr_r, 31, 3) @[lsu_lsc_ctl.scala 230:71] node _T_162 = mux(_T_160, end_addr_pre_r, _T_161) @[lsu_lsc_ctl.scala 230:27] node _T_163 = bits(io.end_addr_m, 2, 0) @[lsu_lsc_ctl.scala 230:128] - reg _T_164 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 230:114] + reg _T_164 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 230:114] _T_164 <= _T_163 @[lsu_lsc_ctl.scala 230:114] node _T_165 = cat(_T_162, _T_164) @[Cat.scala 29:58] io.end_addr_r <= _T_165 @[lsu_lsc_ctl.scala 230:17] diff --git a/lsu_lsc_ctl.v b/lsu_lsc_ctl.v index a22bc1eb..16684074 100644 --- a/lsu_lsc_ctl.v +++ b/lsu_lsc_ctl.v @@ -1387,7 +1387,7 @@ end // initial end_addr_pre_r <= io_end_addr_m[31:3]; end end - always @(posedge io_lsu_c1_m_clk or posedge reset) begin + always @(posedge io_lsu_c1_r_clk or posedge reset) begin if (reset) begin _T_164 <= 3'h0; end else begin diff --git a/src/main/scala/lsu/lsu_lsc_ctl.scala b/src/main/scala/lsu/lsu_lsc_ctl.scala index 830ecf43..e2126b9e 100644 --- a/src/main/scala/lsu/lsu_lsc_ctl.scala +++ b/src/main/scala/lsu/lsu_lsc_ctl.scala @@ -227,7 +227,7 @@ class lsu_lsc_ctl extends Module with RequireAsyncReset with lib io.lsu_addr_m := withClock(io.lsu_c1_m_clk){RegNext(io.lsu_addr_d,0.U)} io.lsu_addr_r := withClock(io.lsu_c1_r_clk){RegNext(io.lsu_addr_m,0.U)} io.end_addr_m := Cat(Mux(io.ldst_dual_m,end_addr_pre_m,io.lsu_addr_m(31,3)), withClock(io.lsu_c1_m_clk){RegNext(io.end_addr_d(2,0),0.U)}) - io.end_addr_r := Cat(Mux(io.ldst_dual_r,end_addr_pre_r,io.lsu_addr_r(31,3)), withClock(io.lsu_c1_m_clk){RegNext(io.end_addr_m(2,0),0.U)}) + io.end_addr_r := Cat(Mux(io.ldst_dual_r,end_addr_pre_r,io.lsu_addr_r(31,3)), withClock(io.lsu_c1_r_clk){RegNext(io.end_addr_m(2,0),0.U)}) end_addr_pre_m := rvdffe(io.end_addr_d(31,3),((io.lsu_pkt_d.valid & io.ldst_dual_d) | io.clk_override),clock,io.scan_mode) end_addr_pre_r := rvdffe(io.end_addr_m(31,3),((io.lsu_pkt_m.valid & io.ldst_dual_m) | io.clk_override),clock,io.scan_mode) io.addr_in_dccm_m := withClock(io.lsu_c1_m_clk){RegNext(io.addr_in_dccm_d,0.U)} diff --git a/target/scala-2.12/classes/lsu/lsu_lsc_ctl.class b/target/scala-2.12/classes/lsu/lsu_lsc_ctl.class index aae7cca3a61409d86cc1a36563701daf131f5daf..be8084d8deaf7d02db7efafa2a3217ada2c5a4d0 100644 GIT binary patch delta 38 rcmaFTEApgQq+tu=WrfKN-_54qmuKW_7guBiVkRJF-Y%}la`q_zGj0w4 delta 38 rcmaFTEApgQq+tu=WrfKPo|sL)FVD!=F0RN3#7scUyj@(8