From c3b2a16201be1ea19fc69793b46abc26a5cb59dc Mon Sep 17 00:00:00 2001 From: waleed-lm Date: Sat, 7 Nov 2020 17:15:47 +0500 Subject: [PATCH] Bus-buffer testing start --- el2_lsu_bus_buffer.fir | 6 +++--- el2_lsu_bus_buffer.v | 5 +++-- src/main/scala/lsu/el2_lsu_bus_buffer.scala | 2 +- .../classes/lsu/el2_lsu_bus_buffer.class | Bin 494223 -> 494223 bytes 4 files changed, 7 insertions(+), 6 deletions(-) diff --git a/el2_lsu_bus_buffer.fir b/el2_lsu_bus_buffer.fir index f60c0765..ecc8df65 100644 --- a/el2_lsu_bus_buffer.fir +++ b/el2_lsu_bus_buffer.fir @@ -2516,9 +2516,9 @@ circuit el2_lsu_bus_buffer : obuf_merge_en <= _T_1764 @[el2_lsu_bus_buffer.scala 367:17] reg obuf_wr_enQ : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 374:55] obuf_wr_enQ <= obuf_wr_en @[el2_lsu_bus_buffer.scala 374:55] - node _T_1765 = eq(obuf_valid, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 375:79] - node _T_1766 = mux(obuf_wr_en, UInt<1>("h01"), _T_1765) @[el2_lsu_bus_buffer.scala 375:58] - node _T_1767 = and(_T_1766, obuf_rst) @[el2_lsu_bus_buffer.scala 375:92] + node _T_1765 = mux(obuf_wr_en, UInt<1>("h01"), obuf_valid) @[el2_lsu_bus_buffer.scala 375:58] + node _T_1766 = eq(obuf_rst, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 375:93] + node _T_1767 = and(_T_1765, _T_1766) @[el2_lsu_bus_buffer.scala 375:91] reg _T_1768 : UInt<1>, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 375:54] _T_1768 <= _T_1767 @[el2_lsu_bus_buffer.scala 375:54] obuf_valid <= _T_1768 @[el2_lsu_bus_buffer.scala 375:14] diff --git a/el2_lsu_bus_buffer.v b/el2_lsu_bus_buffer.v index bab54cb6..18bfca8f 100644 --- a/el2_lsu_bus_buffer.v +++ b/el2_lsu_bus_buffer.v @@ -1243,7 +1243,8 @@ module el2_lsu_bus_buffer( wire [7:0] _T_1535 = _T_1489 ? obuf_data1_in[55:48] : obuf_data1_in[55:48]; // @[el2_lsu_bus_buffer.scala 364:44] wire [7:0] _T_1540 = _T_1493 ? obuf_data1_in[63:56] : obuf_data1_in[63:56]; // @[el2_lsu_bus_buffer.scala 364:44] wire [55:0] _T_1546 = {_T_1540,_T_1535,_T_1530,_T_1525,_T_1520,_T_1515,_T_1510}; // @[Cat.scala 29:58] - wire _T_1766 = obuf_wr_en | _T_1157; // @[el2_lsu_bus_buffer.scala 375:58] + wire _T_1765 = obuf_wr_en | obuf_valid; // @[el2_lsu_bus_buffer.scala 375:58] + wire _T_1766 = ~obuf_rst; // @[el2_lsu_bus_buffer.scala 375:93] reg [1:0] obuf_sz; // @[Reg.scala 27:20] reg [7:0] obuf_byteen; // @[Reg.scala 27:20] reg [63:0] obuf_data; // @[el2_lib.scala 491:16] @@ -3510,7 +3511,7 @@ end // initial if (reset) begin obuf_valid <= 1'h0; end else begin - obuf_valid <= _T_1766 & obuf_rst; + obuf_valid <= _T_1765 & _T_1766; end end always @(posedge io_lsu_busm_clk or posedge reset) begin diff --git a/src/main/scala/lsu/el2_lsu_bus_buffer.scala b/src/main/scala/lsu/el2_lsu_bus_buffer.scala index 836cce0f..0cb334b3 100644 --- a/src/main/scala/lsu/el2_lsu_bus_buffer.scala +++ b/src/main/scala/lsu/el2_lsu_bus_buffer.scala @@ -372,7 +372,7 @@ class el2_lsu_bus_buffer extends Module with RequireAsyncReset with el2_lib { (ibuf_buf_byp & ldst_samedw_r & io.ldst_dual_r) val obuf_wr_enQ = withClock(io.lsu_busm_clk){RegNext(obuf_wr_en, false.B)} - obuf_valid := withClock(io.lsu_free_c2_clk){RegNext(Mux(obuf_wr_en, true.B, !obuf_valid) & obuf_rst, false.B)} + obuf_valid := withClock(io.lsu_free_c2_clk){RegNext(Mux(obuf_wr_en, true.B, obuf_valid) & !obuf_rst, false.B)} obuf_nosend := withClock(io.lsu_free_c2_clk){RegEnable(obuf_nosend_in, false.B, obuf_wr_en)} obuf_cmd_done := withClock(io.lsu_busm_clk){RegNext(obuf_cmd_done_in, false.B)} obuf_data_done := withClock(io.lsu_busm_clk){RegNext(obuf_data_done_in, false.B)} diff --git a/target/scala-2.12/classes/lsu/el2_lsu_bus_buffer.class b/target/scala-2.12/classes/lsu/el2_lsu_bus_buffer.class index 075b25d85be75e90c3994c62a75df9985d59db23..8dc75f3e0754b062dba972066557aadb83b0b4d1 100644 GIT binary patch delta 64 zcmeC5D%U?%uAzl-3)7CD(;xk0GMs+VfLVI_2Q6k^=5m4P>59rMa?@|GVdigl{KW*s R%s|Wn#H`yLf3f*Z0033^8Vdjb delta 57 zcmeC5D%U?%uAzl-3)7CDjQ-OLk20xE-};luWcnrxW|`><6PShC9e*(aF*6Xe05R)! J$6suI69B577nuM6