ICCM Done
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@ -45,7 +45,7 @@ class el2_ifu_aln_ctl extends Module with el2_lib {
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})
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})
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val MHI = 46+BHT_GHR_SIZE // 54
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val MHI = 46+BHT_GHR_SIZE // 54
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val MSIZE = 47+BHT_GHR_SIZE // 55
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val MSIZE = 47+BHT_GHR_SIZE // 55
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val BRDATA_SIZE = 12
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val error_stall_in = WireInit(Bool(),0.U)
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val error_stall_in = WireInit(Bool(),0.U)
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val alignval = WireInit(UInt(2.W), 0.U)
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val alignval = WireInit(UInt(2.W), 0.U)
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val q0final = WireInit(UInt(16.W), 0.U)
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val q0final = WireInit(UInt(16.W), 0.U)
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@ -84,15 +84,25 @@ class el2_ifu_aln_ctl extends Module with el2_lib {
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val brdata0 = WireInit(UInt(12.W), init = 0.U)
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val brdata0 = WireInit(UInt(12.W), init = 0.U)
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val brdata2 = WireInit(UInt(12.W), init = 0.U)
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val brdata2 = WireInit(UInt(12.W), init = 0.U)
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val q0 = WireInit(UInt(32.W), init = 0.U)
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val q1 = WireInit(UInt(32.W), init = 0.U)
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val q2 = WireInit(UInt(32.W), init = 0.U)
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val f1pc_in = WireInit(UInt(31.W), 0.U)
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val f1pc_in = WireInit(UInt(31.W), 0.U)
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val f0pc_in = WireInit(UInt(31.W), 0.U)
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val f0pc_in = WireInit(UInt(31.W), 0.U)
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val error_stall = WireInit(Bool(), 0.U)
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val error_stall = WireInit(Bool(), 0.U)
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val f2_wr_en = WireInit(Bool(), 0.U)
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val f1_shift_wr_en = WireInit(Bool(), 0.U)
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val f0_shift_wr_en = WireInit(Bool(), 0.U)
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val qwen = WireInit(UInt(3.W), 0.U)
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val brdata_in = WireInit(UInt(BRDATA_SIZE.W), 0.U)
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val misc_data_in = WireInit(UInt((MHI+1).W), 0.U)
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error_stall_in := (error_stall | io.ifu_async_error_start) & !io.exu_flush_final
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error_stall_in := (error_stall | io.ifu_async_error_start) & !io.exu_flush_final
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error_stall := withClock(io.active_clk) {RegNext(error_stall_in, init = 0.U)}
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error_stall := withClock(io.active_clk) {RegNext(error_stall_in, init = 0.U)}
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val wrptr = withClock(io.active_clk) {RegNext(wrptr_in, init = 0.U)}
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val wrptr = withClock(io.active_clk) {RegNext(wrptr_in, init = 0.U)}
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val rdptr = withClock(io.active_clk) {RegNext(wrptr_in, init = 0.U)}
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val rdptr = withClock(io.active_clk) {RegNext(rdptr_in, init = 0.U)}
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val f2val = withClock(io.active_clk) {RegNext(f2val_in, init = 0.U)}
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val f2val = withClock(io.active_clk) {RegNext(f2val_in, init = 0.U)}
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val f1val = withClock(io.active_clk) {RegNext(f1val_in, init = 0.U)}
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val f1val = withClock(io.active_clk) {RegNext(f1val_in, init = 0.U)}
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@ -114,56 +124,16 @@ class el2_ifu_aln_ctl extends Module with el2_lib {
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misc1 := RegEnable(misc_data_in, 0.U, qwen(1))
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misc1 := RegEnable(misc_data_in, 0.U, qwen(1))
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misc0 := RegEnable(misc_data_in, 0.U, qwen(0))
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misc0 := RegEnable(misc_data_in, 0.U, qwen(0))
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q2 := RegEnable(io.ifu_fetch_data_f, 0.U, qwen(2))
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q1 := RegEnable(io.ifu_fetch_data_f, 0.U, qwen(1))
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q0 := RegEnable(io.ifu_fetch_data_f, 0.U, qwen(0))
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val i0_shift = io.dec_i0_decode_d & ~error_stall
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f2_wr_en := fetch_to_f2
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f1_shift_wr_en := fetch_to_f1 | shift_f2_f1 | f1_shift_2B
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io.ifu_pmu_instr_aligned := i0_shift
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f0_shift_wr_en := fetch_to_f0 | shift_f2_f0 | shift_f1_f0 | shift_2B | shift_4B
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val aligndata = Mux1H(Seq(f0val(0).asBool -> q0final, (~f0val(1) & f0val(0)).asBool -> Cat(q1final,q0final)))
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val decompressed = Module(new el2_ifu_compress_ctl())
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decompressed.io.din := aligndata
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io.ifu_i0_instr := decompressed.io.dout
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// 16-bit compressed instruction from the aligner to the dec for tracer
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io.ifu_i0_cinst := aligndata(15,0)
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// Checking if its a 32-bit instruction or not
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//val first4B = decompressed.io.rvc
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val first4B = WireInit(Bool(), 0.U)
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val first2B = ~first4B
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val alignicaf = Mux1H(Seq(f0val(1).asBool -> f0icaf, (~f0val(1) & f0val(0)).asBool -> Cat(f1icaf,f0icaf)))
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io.ifu_i0_icaf := Mux1H(Seq(first4B.asBool -> alignicaf.orR, first2B.asBool -> alignicaf(0)))
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io.ifu_i0_valid := Mux1H(Seq(first4B.asBool -> alignval(1), first2B.asBool -> alignval(0)))
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io.ifu_i0_pc4 := first4B
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val shift_2B = i0_shift & first2B
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val shift_4B = i0_shift & first4B
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val f0_shift_2B = Mux1H(Seq(shift_2B.asBool -> f0val(0), shift_4B.asBool -> (!f0val(0) & f0val(0))))
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val f1_shift_2B = f0val(0) & !f0val(1) & shift_4B
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val fetch_to_f0 = !sf0_valid & !sf1_valid & !f2_valid & ifvalid
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val fetch_to_f1 = (!sf0_valid & !sf1_valid & f2_valid & ifvalid) |
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(!sf0_valid & sf1_valid & !f2_valid & ifvalid) |
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( sf0_valid & !sf1_valid & !f2_valid & ifvalid)
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val fetch_to_f2 = (!sf0_valid & sf1_valid & f2_valid & ifvalid) |
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( sf0_valid & sf1_valid & !f2_valid & ifvalid)
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val f2_wr_en = fetch_to_f2
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val f1_shift_wr_en = fetch_to_f1 | shift_f2_f1 | f1_shift_2B
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val f0_shift_wr_en = fetch_to_f0 | shift_f2_f0 | shift_f1_f0 | shift_2B | shift_4B
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val qren = Cat(rdptr === 2.U, rdptr === 1.U, rdptr === 0.U)
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val qren = Cat(rdptr === 2.U, rdptr === 1.U, rdptr === 0.U)
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val qwen = Cat(wrptr === 2.U & ifvalid, wrptr === 1.U & ifvalid, wrptr === 0.U & ifvalid)
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qwen := Cat(wrptr === 2.U & ifvalid, wrptr === 1.U & ifvalid, wrptr === 0.U & ifvalid)
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rdptr_in := Mux1H(Seq((qren(0) & io.ifu_fb_consume1 & !io.exu_flush_final).asBool -> 1.U,
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rdptr_in := Mux1H(Seq((qren(0) & io.ifu_fb_consume1 & !io.exu_flush_final).asBool -> 1.U,
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(qren(1) & io.ifu_fb_consume1 & !io.exu_flush_final).asBool -> 2.U,
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(qren(1) & io.ifu_fb_consume1 & !io.exu_flush_final).asBool -> 2.U,
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@ -210,6 +180,7 @@ class el2_ifu_aln_ctl extends Module with el2_lib {
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val misc1eff = misceff(misceff.getWidth-1,MHI+1)
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val misc1eff = misceff(misceff.getWidth-1,MHI+1)
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val misc0eff = misceff(MHI, 0)
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val misc0eff = misceff(MHI, 0)
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val f1dbecc = misc1eff(misc1eff.getWidth-1)
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val f1dbecc = misc1eff(misc1eff.getWidth-1)
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f1icaf := misc1eff(misc1eff.getWidth-2)
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f1icaf := misc1eff(misc1eff.getWidth-2)
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val f1ictype = misc1eff(misc1eff.getWidth-3,misc1eff.getWidth-4)
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val f1ictype = misc1eff(misc1eff.getWidth-3,misc1eff.getWidth-4)
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@ -224,7 +195,7 @@ class el2_ifu_aln_ctl extends Module with el2_lib {
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val f0poffset = misc0eff(BHT_GHR_SIZE+11, BHT_GHR_SIZE)
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val f0poffset = misc0eff(BHT_GHR_SIZE+11, BHT_GHR_SIZE)
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val f0fghr = misc0eff(BHT_GHR_SIZE-1, 0)
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val f0fghr = misc0eff(BHT_GHR_SIZE-1, 0)
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val brdata_in = Cat(io.ifu_bp_hist1_f(1),io.ifu_bp_hist0_f(1),io.ifu_bp_pc4_f(1),io.ifu_bp_way_f(1),io.ifu_bp_valid_f(1),
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brdata_in := Cat(io.ifu_bp_hist1_f(1),io.ifu_bp_hist0_f(1),io.ifu_bp_pc4_f(1),io.ifu_bp_way_f(1),io.ifu_bp_valid_f(1),
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io.ifu_bp_ret_f(1), io.ifu_bp_hist1_f(0),io.ifu_bp_hist0_f(0),io.ifu_bp_pc4_f(0),io.ifu_bp_way_f(0),
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io.ifu_bp_ret_f(1), io.ifu_bp_hist1_f(0),io.ifu_bp_hist0_f(0),io.ifu_bp_pc4_f(0),io.ifu_bp_way_f(0),
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io.ifu_bp_valid_f(0),io.ifu_bp_ret_f(0))
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io.ifu_bp_valid_f(0),io.ifu_bp_ret_f(0))
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@ -234,16 +205,6 @@ class el2_ifu_aln_ctl extends Module with el2_lib {
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val (brdata0eff,brdata1eff) = (brdataeff(11,0) , brdataeff(23,12))
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val (brdata0eff,brdata1eff) = (brdataeff(11,0) , brdataeff(23,12))
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val q0 = WireInit(UInt(32.W), init = 0.U)
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val q1 = WireInit(UInt(32.W), init = 0.U)
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val q2 = WireInit(UInt(32.W), init = 0.U)
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val qeff = Mux1H(Seq(qren(0).asBool->Cat(q1,q0),
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qren(1).asBool->Cat(q2,q1),
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qren(2).asBool->Cat(q0,q2)))
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val (q1eff, q0eff) = (qeff(63,32), qeff(31,0))
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val brdata0final = Mux1H(Seq(q0sel(0).asBool -> brdata0eff, q0sel(1).asBool -> brdata0eff(11,6)))
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val brdata1final = Mux1H(Seq(q1sel(0).asBool -> brdata1eff, q1sel(1).asBool -> brdata1eff(11,6)))
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val brdata1final = Mux1H(Seq(q1sel(0).asBool -> brdata1eff, q1sel(1).asBool -> brdata1eff(11,6)))
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val f0ret = Cat(brdata0final(6),brdata0final(0))
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val f0ret = Cat(brdata0final(6),brdata0final(0))
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@ -261,7 +222,6 @@ class el2_ifu_aln_ctl extends Module with el2_lib {
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val f1hist1 = Cat(brdata1final(11),brdata1final(5))
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val f1hist1 = Cat(brdata1final(11),brdata1final(5))
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f2_valid := f2val(0)
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f2_valid := f2val(0)
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sf1_valid := sf1val(0)
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sf1_valid := sf1val(0)
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sf0_valid := sf0val(0)
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sf0_valid := sf0val(0)
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@ -278,11 +238,18 @@ class el2_ifu_aln_ctl extends Module with el2_lib {
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shift_f2_f0 := !sf0_valid & !sf1_valid & f2_valid
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shift_f2_f0 := !sf0_valid & !sf1_valid & f2_valid
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shift_f2_f1 := !sf0_valid & sf1_valid & f2_valid
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shift_f2_f1 := !sf0_valid & sf1_valid & f2_valid
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//val f0pc = WireInit(UInt(31.W), 0.U)
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val fetch_to_f0 = !sf0_valid & !sf1_valid & !f2_valid & ifvalid
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// val f2pc = WireInit(UInt(31.W), 0.U)
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val fetch_to_f1 = (!sf0_valid & !sf1_valid & f2_valid & ifvalid) |
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(!sf0_valid & sf1_valid & !f2_valid & ifvalid) |
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( sf0_valid & !sf1_valid & !f2_valid & ifvalid)
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val fetch_to_f2 = (!sf0_valid & sf1_valid & f2_valid & ifvalid) |
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( sf0_valid & sf1_valid & !f2_valid & ifvalid)
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val f0pc_plus1 = f0pc + 1.U
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val f0pc_plus1 = f0pc + 1.U
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val f1pc_plus1 = f1pc + 1.U
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val sf1pc = (Fill(31, f1_shift_2B) & f0pc_plus1) | (Fill(31, !f1_shift_2B) & f0pc)
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val sf1pc = (Fill(31, f1_shift_2B) & f0pc_plus1) | (Fill(31, !f1_shift_2B) & f0pc)
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f1pc_in := Mux1H(Seq(fetch_to_f1.asBool->io.ifu_fetch_pc,
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f1pc_in := Mux1H(Seq(fetch_to_f1.asBool->io.ifu_fetch_pc,
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@ -303,6 +270,89 @@ class el2_ifu_aln_ctl extends Module with el2_lib {
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(shift_f2_f1 & !io.exu_flush_final).asBool->f2val,
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(shift_f2_f1 & !io.exu_flush_final).asBool->f2val,
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(!fetch_to_f1 & !shift_f2_f1 & !shift_f1_f0 & !io.exu_flush_final).asBool->sf1val))
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(!fetch_to_f1 & !shift_f2_f1 & !shift_f1_f0 & !io.exu_flush_final).asBool->sf1val))
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sf0val := Mux1H(Seq(shift_2B.asBool->Cat(0.U, f0val(1),)))
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val i0_shift = io.dec_i0_decode_d & ~error_stall
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io.ifu_pmu_instr_aligned := i0_shift
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val aligndata = Mux1H(Seq(f0val(0).asBool -> q0final, (~f0val(1) & f0val(0)).asBool -> Cat(q1final,q0final)))
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val decompressed = Module(new el2_ifu_compress_ctl())
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decompressed.io.din := aligndata
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io.ifu_i0_instr := decompressed.io.dout
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// 16-bit compressed instruction from the aligner to the dec for tracer
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io.ifu_i0_cinst := aligndata(15,0)
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// Checking if its a 32-bit instruction or not
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//val first4B = decompressed.io.rvc
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val first4B = WireInit(Bool(), 0.U)
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val first2B = ~first4B
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val alignicaf = Mux1H(Seq(f0val(1).asBool -> f0icaf, (~f0val(1) & f0val(0)).asBool -> Cat(f1icaf,f0icaf)))
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io.ifu_i0_icaf := Mux1H(Seq(first4B.asBool -> alignicaf.orR, first2B.asBool -> alignicaf(0)))
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io.ifu_i0_valid := Mux1H(Seq(first4B.asBool -> alignval(1), first2B.asBool -> alignval(0)))
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io.ifu_i0_pc4 := first4B
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val shift_2B = i0_shift & first2B
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val shift_4B = i0_shift & first4B
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val f0_shift_2B = Mux1H(Seq(shift_2B.asBool -> f0val(0), shift_4B.asBool -> (!f0val(0) & f0val(0))))
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val f1_shift_2B = f0val(0) & !f0val(1) & shift_4B
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val qeff = Mux1H(Seq(qren(0).asBool->Cat(q1,q0),
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qren(1).asBool->Cat(q2,q1),
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qren(2).asBool->Cat(q0,q2)))
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val (q1eff, q0eff) = (qeff(63,32), qeff(31,0))
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val brdata0final = Mux1H(Seq(q0sel(0).asBool -> brdata0eff, q0sel(1).asBool -> brdata0eff(11,6)))
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//val f0pc = WireInit(UInt(31.W), 0.U)
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// val f2pc = WireInit(UInt(31.W), 0.U)
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f0val := Mux1H(Seq(shift_2B.asBool -> f0val(1), (!shift_2B & !shift_4B).asBool -> f0val))
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f0val := Mux1H(Seq(shift_2B.asBool -> f0val(1), (!shift_2B & !shift_4B).asBool -> f0val))
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f0val_in := Mux1H(Seq((fetch_to_f0 & !io.exu_flush_final).asBool->io.ifu_fetch_val,
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f0val_in := Mux1H(Seq((fetch_to_f0 & !io.exu_flush_final).asBool->io.ifu_fetch_val,
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@ -385,9 +435,7 @@ class el2_ifu_aln_ctl extends Module with el2_lib {
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||||||
|
|
||||||
q2 := RegEnable(io.ifu_fetch_data_f, 0.U, qwen(2))
|
|
||||||
q1 := RegEnable(io.ifu_fetch_data_f, 0.U, qwen(1))
|
|
||||||
q0 := RegEnable(io.ifu_fetch_data_f, 0.U, qwen(0))
|
|
||||||
|
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
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Reference in New Issue