ICCM Done

src/main/scala/ifu/el2_ifu_aln_ctl.scala

@@ -45,7 +45,7 @@ class el2_ifu_aln_ctl extends Module with el2_lib {
   })
   val MHI = 46+BHT_GHR_SIZE // 54
   val MSIZE = 47+BHT_GHR_SIZE // 55
-
+  val BRDATA_SIZE = 12
   val error_stall_in = WireInit(Bool(),0.U)
   val alignval = WireInit(UInt(2.W), 0.U)
   val q0final = WireInit(UInt(16.W), 0.U)
@@ -84,15 +84,25 @@ class el2_ifu_aln_ctl extends Module with el2_lib {
   val brdata0 = WireInit(UInt(12.W), init = 0.U)
   val brdata2 = WireInit(UInt(12.W), init = 0.U)
 
+  val q0 = WireInit(UInt(32.W), init = 0.U)
+  val q1 = WireInit(UInt(32.W), init = 0.U)
+  val q2 = WireInit(UInt(32.W), init = 0.U)
+
   val f1pc_in = WireInit(UInt(31.W), 0.U)
   val f0pc_in = WireInit(UInt(31.W), 0.U)
   val error_stall = WireInit(Bool(), 0.U)
+  val f2_wr_en = WireInit(Bool(), 0.U)
+  val f1_shift_wr_en = WireInit(Bool(), 0.U)
+  val f0_shift_wr_en = WireInit(Bool(), 0.U)
+  val qwen = WireInit(UInt(3.W), 0.U)
+  val brdata_in = WireInit(UInt(BRDATA_SIZE.W), 0.U)
+  val misc_data_in = WireInit(UInt((MHI+1).W), 0.U)
 
   error_stall_in := (error_stall | io.ifu_async_error_start) & !io.exu_flush_final
 
   error_stall := withClock(io.active_clk) {RegNext(error_stall_in, init = 0.U)}
   val wrptr = withClock(io.active_clk) {RegNext(wrptr_in, init = 0.U)}
-  val rdptr = withClock(io.active_clk) {RegNext(wrptr_in, init = 0.U)}
+  val rdptr = withClock(io.active_clk) {RegNext(rdptr_in, init = 0.U)}
 
   val f2val = withClock(io.active_clk) {RegNext(f2val_in, init = 0.U)}
   val f1val = withClock(io.active_clk) {RegNext(f1val_in, init = 0.U)}
@@ -114,56 +124,16 @@ class el2_ifu_aln_ctl extends Module with el2_lib {
   misc1 := RegEnable(misc_data_in, 0.U, qwen(1))
   misc0 := RegEnable(misc_data_in, 0.U, qwen(0))
 
+  q2 := RegEnable(io.ifu_fetch_data_f, 0.U, qwen(2))
+  q1 := RegEnable(io.ifu_fetch_data_f, 0.U, qwen(1))
+  q0 := RegEnable(io.ifu_fetch_data_f, 0.U, qwen(0))
 
-  val i0_shift = io.dec_i0_decode_d & ~error_stall
+  f2_wr_en       := fetch_to_f2
-
+  f1_shift_wr_en := fetch_to_f1 | shift_f2_f1 | f1_shift_2B
-  io.ifu_pmu_instr_aligned := i0_shift
+  f0_shift_wr_en := fetch_to_f0 | shift_f2_f0 | shift_f1_f0 | shift_2B | shift_4B
-
-  val aligndata = Mux1H(Seq(f0val(0).asBool -> q0final, (~f0val(1) & f0val(0)).asBool -> Cat(q1final,q0final)))
-
-  val decompressed = Module(new el2_ifu_compress_ctl())
-
-  decompressed.io.din := aligndata
-
-   io.ifu_i0_instr := decompressed.io.dout
-
-  // 16-bit compressed instruction from the aligner to the dec for tracer
-  io.ifu_i0_cinst := aligndata(15,0)
-
-  // Checking if its a 32-bit instruction or not
-  //val first4B = decompressed.io.rvc
-  val first4B = WireInit(Bool(), 0.U)
-  val first2B = ~first4B
-  val alignicaf = Mux1H(Seq(f0val(1).asBool -> f0icaf, (~f0val(1) & f0val(0)).asBool -> Cat(f1icaf,f0icaf)))
-
-  io.ifu_i0_icaf := Mux1H(Seq(first4B.asBool -> alignicaf.orR, first2B.asBool -> alignicaf(0)))
-  io.ifu_i0_valid := Mux1H(Seq(first4B.asBool -> alignval(1), first2B.asBool -> alignval(0)))
-  io.ifu_i0_pc4 := first4B
-
-  val shift_2B = i0_shift & first2B
-  val shift_4B = i0_shift & first4B
-  val f0_shift_2B = Mux1H(Seq(shift_2B.asBool -> f0val(0), shift_4B.asBool -> (!f0val(0) & f0val(0))))
-  val f1_shift_2B =  f0val(0) & !f0val(1) & shift_4B
-
-
-
-
-
-
-  val fetch_to_f0        =  !sf0_valid & !sf1_valid & !f2_valid & ifvalid
-  val fetch_to_f1        = (!sf0_valid & !sf1_valid &  f2_valid & ifvalid)  |
-                           (!sf0_valid &  sf1_valid & !f2_valid & ifvalid)  |
-                           ( sf0_valid & !sf1_valid & !f2_valid & ifvalid)
-
-  val fetch_to_f2        = (!sf0_valid &  sf1_valid &  f2_valid & ifvalid)  |
-                           ( sf0_valid &  sf1_valid & !f2_valid & ifvalid)
-
-  val f2_wr_en       = fetch_to_f2
-  val f1_shift_wr_en = fetch_to_f1 | shift_f2_f1 | f1_shift_2B
-  val f0_shift_wr_en = fetch_to_f0 | shift_f2_f0 | shift_f1_f0 | shift_2B | shift_4B
 
   val qren = Cat(rdptr === 2.U, rdptr === 1.U, rdptr === 0.U)
-  val qwen = Cat(wrptr === 2.U & ifvalid, wrptr === 1.U & ifvalid, wrptr === 0.U & ifvalid)
+  qwen := Cat(wrptr === 2.U & ifvalid, wrptr === 1.U & ifvalid, wrptr === 0.U & ifvalid)
 
   rdptr_in := Mux1H(Seq((qren(0) & io.ifu_fb_consume1 & !io.exu_flush_final).asBool -> 1.U,
     (qren(1) & io.ifu_fb_consume1 & !io.exu_flush_final).asBool -> 2.U,
@@ -210,6 +180,7 @@ class el2_ifu_aln_ctl extends Module with el2_lib {
   val misc1eff = misceff(misceff.getWidth-1,MHI+1)
   val misc0eff = misceff(MHI, 0)
 
+
   val f1dbecc = misc1eff(misc1eff.getWidth-1)
   f1icaf := misc1eff(misc1eff.getWidth-2)
   val f1ictype = misc1eff(misc1eff.getWidth-3,misc1eff.getWidth-4)
@@ -224,7 +195,7 @@ class el2_ifu_aln_ctl extends Module with el2_lib {
   val f0poffset = misc0eff(BHT_GHR_SIZE+11, BHT_GHR_SIZE)
   val f0fghr = misc0eff(BHT_GHR_SIZE-1, 0)
 
-  val brdata_in = Cat(io.ifu_bp_hist1_f(1),io.ifu_bp_hist0_f(1),io.ifu_bp_pc4_f(1),io.ifu_bp_way_f(1),io.ifu_bp_valid_f(1),
+  brdata_in := Cat(io.ifu_bp_hist1_f(1),io.ifu_bp_hist0_f(1),io.ifu_bp_pc4_f(1),io.ifu_bp_way_f(1),io.ifu_bp_valid_f(1),
     io.ifu_bp_ret_f(1), io.ifu_bp_hist1_f(0),io.ifu_bp_hist0_f(0),io.ifu_bp_pc4_f(0),io.ifu_bp_way_f(0),
     io.ifu_bp_valid_f(0),io.ifu_bp_ret_f(0))
 
@@ -234,16 +205,6 @@ class el2_ifu_aln_ctl extends Module with el2_lib {
 
   val (brdata0eff,brdata1eff) = (brdataeff(11,0) , brdataeff(23,12))
 
-  val q0 = WireInit(UInt(32.W), init = 0.U)
-  val q1 = WireInit(UInt(32.W), init = 0.U)
-  val q2 = WireInit(UInt(32.W), init = 0.U)
-
-  val qeff = Mux1H(Seq(qren(0).asBool->Cat(q1,q0),
-                      qren(1).asBool->Cat(q2,q1),
-                      qren(2).asBool->Cat(q0,q2)))
-  val (q1eff, q0eff) = (qeff(63,32), qeff(31,0))
-  val brdata0final = Mux1H(Seq(q0sel(0).asBool -> brdata0eff, q0sel(1).asBool -> brdata0eff(11,6)))
-
   val brdata1final = Mux1H(Seq(q1sel(0).asBool -> brdata1eff, q1sel(1).asBool -> brdata1eff(11,6)))
 
   val f0ret = Cat(brdata0final(6),brdata0final(0))
@@ -261,7 +222,6 @@ class el2_ifu_aln_ctl extends Module with el2_lib {
   val f1hist1 = Cat(brdata1final(11),brdata1final(5))
 
 
-
   f2_valid := f2val(0)
   sf1_valid := sf1val(0)
   sf0_valid := sf0val(0)
@@ -278,11 +238,18 @@ class el2_ifu_aln_ctl extends Module with el2_lib {
   shift_f2_f0 := !sf0_valid & !sf1_valid &  f2_valid
   shift_f2_f1 := !sf0_valid &  sf1_valid &  f2_valid
 
-  //val f0pc = WireInit(UInt(31.W), 0.U)
+  val fetch_to_f0        =  !sf0_valid & !sf1_valid & !f2_valid & ifvalid
- // val f2pc = WireInit(UInt(31.W), 0.U)
+  val fetch_to_f1        = (!sf0_valid & !sf1_valid &  f2_valid & ifvalid)  |
+    (!sf0_valid &  sf1_valid & !f2_valid & ifvalid)  |
+    ( sf0_valid & !sf1_valid & !f2_valid & ifvalid)
+
+  val fetch_to_f2        = (!sf0_valid &  sf1_valid &  f2_valid & ifvalid)  |
+    ( sf0_valid &  sf1_valid & !f2_valid & ifvalid)
 
   val f0pc_plus1 = f0pc + 1.U
 
+  val f1pc_plus1 = f1pc + 1.U
+
   val sf1pc = (Fill(31, f1_shift_2B) & f0pc_plus1) | (Fill(31, !f1_shift_2B) & f0pc)
 
   f1pc_in := Mux1H(Seq(fetch_to_f1.asBool->io.ifu_fetch_pc,
@@ -303,6 +270,89 @@ class el2_ifu_aln_ctl extends Module with el2_lib {
     (shift_f2_f1 & !io.exu_flush_final).asBool->f2val,
     (!fetch_to_f1 & !shift_f2_f1 & !shift_f1_f0 & !io.exu_flush_final).asBool->sf1val))
 
+  sf0val := Mux1H(Seq(shift_2B.asBool->Cat(0.U, f0val(1),)))
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  val i0_shift = io.dec_i0_decode_d & ~error_stall
+
+  io.ifu_pmu_instr_aligned := i0_shift
+
+  val aligndata = Mux1H(Seq(f0val(0).asBool -> q0final, (~f0val(1) & f0val(0)).asBool -> Cat(q1final,q0final)))
+
+  val decompressed = Module(new el2_ifu_compress_ctl())
+
+  decompressed.io.din := aligndata
+
+   io.ifu_i0_instr := decompressed.io.dout
+
+  // 16-bit compressed instruction from the aligner to the dec for tracer
+  io.ifu_i0_cinst := aligndata(15,0)
+
+  // Checking if its a 32-bit instruction or not
+  //val first4B = decompressed.io.rvc
+  val first4B = WireInit(Bool(), 0.U)
+  val first2B = ~first4B
+  val alignicaf = Mux1H(Seq(f0val(1).asBool -> f0icaf, (~f0val(1) & f0val(0)).asBool -> Cat(f1icaf,f0icaf)))
+
+  io.ifu_i0_icaf := Mux1H(Seq(first4B.asBool -> alignicaf.orR, first2B.asBool -> alignicaf(0)))
+  io.ifu_i0_valid := Mux1H(Seq(first4B.asBool -> alignval(1), first2B.asBool -> alignval(0)))
+  io.ifu_i0_pc4 := first4B
+
+  val shift_2B = i0_shift & first2B
+  val shift_4B = i0_shift & first4B
+  val f0_shift_2B = Mux1H(Seq(shift_2B.asBool -> f0val(0), shift_4B.asBool -> (!f0val(0) & f0val(0))))
+  val f1_shift_2B =  f0val(0) & !f0val(1) & shift_4B
+
+
+
+  val qeff = Mux1H(Seq(qren(0).asBool->Cat(q1,q0),
+                      qren(1).asBool->Cat(q2,q1),
+                      qren(2).asBool->Cat(q0,q2)))
+  val (q1eff, q0eff) = (qeff(63,32), qeff(31,0))
+  val brdata0final = Mux1H(Seq(q0sel(0).asBool -> brdata0eff, q0sel(1).asBool -> brdata0eff(11,6)))
+
+
+
+
+
+
+
+
+  //val f0pc = WireInit(UInt(31.W), 0.U)
+ // val f2pc = WireInit(UInt(31.W), 0.U)
+
+
+
+
+
+
+
+
+
   f0val := Mux1H(Seq(shift_2B.asBool -> f0val(1), (!shift_2B & !shift_4B).asBool -> f0val))
 
   f0val_in := Mux1H(Seq((fetch_to_f0 & !io.exu_flush_final).asBool->io.ifu_fetch_val,
@@ -385,9 +435,7 @@ class el2_ifu_aln_ctl extends Module with el2_lib {
 
 
 
-  q2 := RegEnable(io.ifu_fetch_data_f, 0.U, qwen(2))
+
-  q1 := RegEnable(io.ifu_fetch_data_f, 0.U, qwen(1))
-  q0 := RegEnable(io.ifu_fetch_data_f, 0.U, qwen(0))
 
 
 }