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ICCM Done

This commit is contained in:
waleed-lm 2020-10-12 18:06:50 +05:00
parent 1d9661d2c5
commit c407c91aa9
4 changed files with 186 additions and 138 deletions
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324
src/main/scala/ifu/el2_ifu_aln_ctl.scala
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@ -45,7 +45,7 @@ class el2_ifu_aln_ctl extends Module with el2_lib {
})
val MHI = 46+BHT_GHR_SIZE // 54
val MSIZE = 47+BHT_GHR_SIZE // 55
val BRDATA_SIZE = 12
val error_stall_in = WireInit(Bool(),0.U)
val alignval = WireInit(UInt(2.W), 0.U)
val q0final = WireInit(UInt(16.W), 0.U)
@ -84,15 +84,25 @@ class el2_ifu_aln_ctl extends Module with el2_lib {
val brdata0 = WireInit(UInt(12.W), init = 0.U)
val brdata2 = WireInit(UInt(12.W), init = 0.U)
val q0 = WireInit(UInt(32.W), init = 0.U)
val q1 = WireInit(UInt(32.W), init = 0.U)
val q2 = WireInit(UInt(32.W), init = 0.U)
val f1pc_in = WireInit(UInt(31.W), 0.U)
val f0pc_in = WireInit(UInt(31.W), 0.U)
val error_stall = WireInit(Bool(), 0.U)
val f2_wr_en = WireInit(Bool(), 0.U)
val f1_shift_wr_en = WireInit(Bool(), 0.U)
val f0_shift_wr_en = WireInit(Bool(), 0.U)
val qwen = WireInit(UInt(3.W), 0.U)
val brdata_in = WireInit(UInt(BRDATA_SIZE.W), 0.U)
val misc_data_in = WireInit(UInt((MHI+1).W), 0.U)
error_stall_in := (error_stall | io.ifu_async_error_start) & !io.exu_flush_final
error_stall := withClock(io.active_clk) {RegNext(error_stall_in, init = 0.U)}
val wrptr = withClock(io.active_clk) {RegNext(wrptr_in, init = 0.U)}
val rdptr = withClock(io.active_clk) {RegNext(wrptr_in, init = 0.U)}
val rdptr = withClock(io.active_clk) {RegNext(rdptr_in, init = 0.U)}
val f2val = withClock(io.active_clk) {RegNext(f2val_in, init = 0.U)}
val f1val = withClock(io.active_clk) {RegNext(f1val_in, init = 0.U)}
@ -113,6 +123,178 @@ class el2_ifu_aln_ctl extends Module with el2_lib {
misc2 := RegEnable(misc_data_in, 0.U, qwen(2))
misc1 := RegEnable(misc_data_in, 0.U, qwen(1))
misc0 := RegEnable(misc_data_in, 0.U, qwen(0))
q2 := RegEnable(io.ifu_fetch_data_f, 0.U, qwen(2))
q1 := RegEnable(io.ifu_fetch_data_f, 0.U, qwen(1))
q0 := RegEnable(io.ifu_fetch_data_f, 0.U, qwen(0))
f2_wr_en := fetch_to_f2
f1_shift_wr_en := fetch_to_f1 | shift_f2_f1 | f1_shift_2B
f0_shift_wr_en := fetch_to_f0 | shift_f2_f0 | shift_f1_f0 | shift_2B | shift_4B
val qren = Cat(rdptr === 2.U, rdptr === 1.U, rdptr === 0.U)
qwen := Cat(wrptr === 2.U & ifvalid, wrptr === 1.U & ifvalid, wrptr === 0.U & ifvalid)
rdptr_in := Mux1H(Seq((qren(0) & io.ifu_fb_consume1 & !io.exu_flush_final).asBool -> 1.U,
(qren(1) & io.ifu_fb_consume1 & !io.exu_flush_final).asBool -> 2.U,
(qren(2) & io.ifu_fb_consume1 & !io.exu_flush_final).asBool -> 0.U,
(qren(0) & io.ifu_fb_consume2 & !io.exu_flush_final).asBool -> 2.U,
(qren(1) & io.ifu_fb_consume2 & !io.exu_flush_final).asBool -> 0.U,
(qren(2) & io.ifu_fb_consume2 & !io.exu_flush_final).asBool -> 1.U,
(!io.ifu_fb_consume1 & !io.ifu_fb_consume2 & !io.exu_flush_final).asBool -> rdptr))
wrptr_in := Mux1H(Seq((qwen(0) & !io.exu_flush_final).asBool -> 1.U,
(qwen(1) & !io.exu_flush_final).asBool -> 2.U,
(qwen(2) & !io.exu_flush_final).asBool -> 0.U,
(!ifvalid & !io.exu_flush_final).asBool->wrptr))
q2off_in := Mux1H(Seq((!qwen(2) & (rdptr===2.U)).asBool->(q2off.asUInt | f0_shift_2B),
(!qwen(2) & (rdptr===1.U)).asBool->(q2off.asUInt | f1_shift_2B),
(!qwen(2) & (rdptr===0.U)).asBool->q2off))
q1off_in := Mux1H(Seq((!qwen(1) & (rdptr===1.U)).asBool->(q1off.asUInt | f0_shift_2B),
(!qwen(1) & (rdptr===0.U)).asBool->(q1off.asUInt | f1_shift_2B),
(!qwen(1) & (rdptr===2.U)).asBool->q1off))
q0off_in := Mux1H(Seq((!qwen(0) & (rdptr===0.U)).asBool -> (q0off.asUInt | f0_shift_2B),
(!qwen(0) & (rdptr===2.U)).asBool -> (q0off.asUInt | f1_shift_2B),
(!qwen(0) & (rdptr===1.U)).asBool -> q0off))
val q0ptr = Mux1H(Seq((rdptr===0.U)->q0off,
(rdptr===1.U)->q1off,
(rdptr===2.U)->q2off))
val q1ptr = Mux1H(Seq((rdptr===0.U) -> q1off, (rdptr === 1.U) -> q2off, (rdptr === 2.U) -> q0off))
val q0sel = Cat(q0ptr, !q0ptr)
val q1sel = Cat(q1ptr, !q1ptr)
val misc_data_in = Cat(io.iccm_rd_ecc_double_err, io.ic_access_fault_f, io.ic_access_fault_type_f,
io.ifu_bp_btb_target_f(31,1), io.ifu_bp_poffset_f, io.ifu_bp_fghr_f)
val misceff = Mux1H(Seq(qren(0).asBool() -> Cat(misc1, misc0),
qren(1).asBool()->Cat(misc2, misc1),
qren(2).asBool()->Cat(misc0, misc2)))
val misc1eff = misceff(misceff.getWidth-1,MHI+1)
val misc0eff = misceff(MHI, 0)
val f1dbecc = misc1eff(misc1eff.getWidth-1)
f1icaf := misc1eff(misc1eff.getWidth-2)
val f1ictype = misc1eff(misc1eff.getWidth-3,misc1eff.getWidth-4)
val f1prett = misc1eff(misc1eff.getWidth-5,misc1eff.getWidth-35)
val f1poffset = misc1eff(BHT_GHR_SIZE+11, BHT_GHR_SIZE)
val f1fghr = misc1eff(BHT_GHR_SIZE-1, 0)
val f0dbecc = misc0eff(misc0eff.getWidth-1)
f0icaf := misc0eff(misc0eff.getWidth-2)
val f0ictype = misc0eff(misc0eff.getWidth-3,misc0eff.getWidth-4)
val f0prett = misc0eff(misc0eff.getWidth-5,misc0eff.getWidth-35)
val f0poffset = misc0eff(BHT_GHR_SIZE+11, BHT_GHR_SIZE)
val f0fghr = misc0eff(BHT_GHR_SIZE-1, 0)
brdata_in := Cat(io.ifu_bp_hist1_f(1),io.ifu_bp_hist0_f(1),io.ifu_bp_pc4_f(1),io.ifu_bp_way_f(1),io.ifu_bp_valid_f(1),
io.ifu_bp_ret_f(1), io.ifu_bp_hist1_f(0),io.ifu_bp_hist0_f(0),io.ifu_bp_pc4_f(0),io.ifu_bp_way_f(0),
io.ifu_bp_valid_f(0),io.ifu_bp_ret_f(0))
val brdataeff = Mux1H(Seq(qren(0).asBool->Cat(brdata1,brdata0),
qren(1).asBool->Cat(brdata2,brdata1),
qren(2).asBool->Cat(brdata0,brdata2)))
val (brdata0eff,brdata1eff) = (brdataeff(11,0) , brdataeff(23,12))
val brdata1final = Mux1H(Seq(q1sel(0).asBool -> brdata1eff, q1sel(1).asBool -> brdata1eff(11,6)))
val f0ret = Cat(brdata0final(6),brdata0final(0))
val f0brend = Cat(brdata0final(7),brdata0final(1))
val f0way = Cat(brdata0final(8),brdata0final(2))
val f0pc4 = Cat(brdata0final(9),brdata0final(3))
val f0hist0 = Cat(brdata0final(10),brdata0final(4))
val f0hist1 = Cat(brdata0final(11),brdata0final(5))
val f1ret = Cat(brdata1final(6),brdata1final(0))
val f1brend = Cat(brdata1final(7),brdata1final(1))
val f1way = Cat(brdata1final(8),brdata1final(2))
val f1pc4 = Cat(brdata1final(9),brdata1final(3))
val f1hist0 = Cat(brdata1final(10),brdata1final(4))
val f1hist1 = Cat(brdata1final(11),brdata1final(5))
f2_valid := f2val(0)
sf1_valid := sf1val(0)
sf0_valid := sf0val(0)
val consume_fb0 = !sf0val(0) & f0val(0)
val consume_fb1 = !sf1val(0) & f1val(0)
io.ifu_fb_consume1 := consume_fb0 & !consume_fb1 & !io.exu_flush_final
io.ifu_fb_consume2 := consume_fb0 & consume_fb1 & !io.exu_flush_final
ifvalid := io.ifu_fetch_val(0)
shift_f1_f0 := !sf0_valid & sf1_valid
shift_f2_f0 := !sf0_valid & !sf1_valid & f2_valid
shift_f2_f1 := !sf0_valid & sf1_valid & f2_valid
val fetch_to_f0 = !sf0_valid & !sf1_valid & !f2_valid & ifvalid
val fetch_to_f1 = (!sf0_valid & !sf1_valid & f2_valid & ifvalid) |
(!sf0_valid & sf1_valid & !f2_valid & ifvalid) |
( sf0_valid & !sf1_valid & !f2_valid & ifvalid)
val fetch_to_f2 = (!sf0_valid & sf1_valid & f2_valid & ifvalid) |
( sf0_valid & sf1_valid & !f2_valid & ifvalid)
val f0pc_plus1 = f0pc + 1.U
val f1pc_plus1 = f1pc + 1.U
val sf1pc = (Fill(31, f1_shift_2B) & f0pc_plus1) | (Fill(31, !f1_shift_2B) & f0pc)
f1pc_in := Mux1H(Seq(fetch_to_f1.asBool->io.ifu_fetch_pc,
shift_f2_f1.asBool->f2pc,
(!fetch_to_f1 & !shift_f2_f1).asBool -> sf1pc))
f0pc_in := Mux1H(Seq(fetch_to_f0.asBool->io.ifu_fetch_pc,
shift_f2_f0.asBool->f2pc,
shift_f1_f0.asBool->sf1pc,
(!fetch_to_f0 & !shift_f2_f0 & !shift_f1_f0).asBool->f0pc_plus1))
f2val_in := Mux1H(Seq((fetch_to_f2 & !io.exu_flush_final).asBool->io.ifu_fetch_val,
(!fetch_to_f2 & !shift_f2_f1 & !shift_f2_f0 & !io.exu_flush_final).asBool->f2val))
sf1val := Mux1H(Seq(f1_shift_2B.asBool->f1val(1), !f1_shift_2B.asBool->f1val))
f1val_in := Mux1H(Seq((fetch_to_f1 & !io.exu_flush_final).asBool -> io.ifu_fetch_val,
(shift_f2_f1 & !io.exu_flush_final).asBool->f2val,
(!fetch_to_f1 & !shift_f2_f1 & !shift_f1_f0 & !io.exu_flush_final).asBool->sf1val))
sf0val := Mux1H(Seq(shift_2B.asBool->Cat(0.U, f0val(1),)))
val i0_shift = io.dec_i0_decode_d & ~error_stall
@ -147,161 +329,29 @@ class el2_ifu_aln_ctl extends Module with el2_lib {
val fetch_to_f0 = !sf0_valid & !sf1_valid & !f2_valid & ifvalid
val fetch_to_f1 = (!sf0_valid & !sf1_valid & f2_valid & ifvalid) |
(!sf0_valid & sf1_valid & !f2_valid & ifvalid) |
( sf0_valid & !sf1_valid & !f2_valid & ifvalid)
val fetch_to_f2 = (!sf0_valid & sf1_valid & f2_valid & ifvalid) |
( sf0_valid & sf1_valid & !f2_valid & ifvalid)
val f2_wr_en = fetch_to_f2
val f1_shift_wr_en = fetch_to_f1 | shift_f2_f1 | f1_shift_2B
val f0_shift_wr_en = fetch_to_f0 | shift_f2_f0 | shift_f1_f0 | shift_2B | shift_4B
val qren = Cat(rdptr === 2.U, rdptr === 1.U, rdptr === 0.U)
val qwen = Cat(wrptr === 2.U & ifvalid, wrptr === 1.U & ifvalid, wrptr === 0.U & ifvalid)
rdptr_in := Mux1H(Seq((qren(0) & io.ifu_fb_consume1 & !io.exu_flush_final).asBool -> 1.U,
(qren(1) & io.ifu_fb_consume1 & !io.exu_flush_final).asBool -> 2.U,
(qren(2) & io.ifu_fb_consume1 & !io.exu_flush_final).asBool -> 0.U,
(qren(0) & io.ifu_fb_consume2 & !io.exu_flush_final).asBool -> 2.U,
(qren(1) & io.ifu_fb_consume2 & !io.exu_flush_final).asBool -> 0.U,
(qren(2) & io.ifu_fb_consume2 & !io.exu_flush_final).asBool -> 1.U,
(!io.ifu_fb_consume1 & !io.ifu_fb_consume2 & !io.exu_flush_final).asBool -> rdptr))
wrptr_in := Mux1H(Seq((qwen(0) & !io.exu_flush_final).asBool -> 1.U,
(qwen(1) & !io.exu_flush_final).asBool -> 2.U,
(qwen(2) & !io.exu_flush_final).asBool -> 0.U,
(!ifvalid & !io.exu_flush_final).asBool->wrptr))
q2off_in := Mux1H(Seq((!qwen(2) & (rdptr===2.U)).asBool->(q2off.asUInt | f0_shift_2B),
(!qwen(2) & (rdptr===1.U)).asBool->(q2off.asUInt | f1_shift_2B),
(!qwen(2) & (rdptr===0.U)).asBool->q2off))
q1off_in := Mux1H(Seq((!qwen(1) & (rdptr===1.U)).asBool->(q1off.asUInt | f0_shift_2B),
(!qwen(1) & (rdptr===0.U)).asBool->(q1off.asUInt | f1_shift_2B),
(!qwen(1) & (rdptr===2.U)).asBool->q1off))
q0off_in := Mux1H(Seq((!qwen(0) & (rdptr===0.U)).asBool -> (q0off.asUInt | f0_shift_2B),
(!qwen(0) & (rdptr===2.U)).asBool -> (q0off.asUInt | f1_shift_2B),
(!qwen(0) & (rdptr===1.U)).asBool -> q0off))
val q0ptr = Mux1H(Seq((rdptr===0.U)->q0off,
(rdptr===1.U)->q1off,
(rdptr===2.U)->q2off))
val q1ptr = Mux1H(Seq((rdptr===0.U) -> q1off, (rdptr === 1.U) -> q2off, (rdptr === 2.U) -> q0off))
val q0sel = Cat(q0ptr, !q0ptr)
val q1sel = Cat(q1ptr, !q1ptr)
val misc_data_in = Cat(io.iccm_rd_ecc_double_err, io.ic_access_fault_f, io.ic_access_fault_type_f,
io.ifu_bp_btb_target_f(31,1), io.ifu_bp_poffset_f, io.ifu_bp_fghr_f)
val misceff = Mux1H(Seq(qren(0).asBool() -> Cat(misc1, misc0),
qren(1).asBool()->Cat(misc2, misc1),
qren(2).asBool()->Cat(misc0, misc2)))
val misc1eff = misceff(misceff.getWidth-1,MHI+1)
val misc0eff = misceff(MHI, 0)
val f1dbecc = misc1eff(misc1eff.getWidth-1)
f1icaf := misc1eff(misc1eff.getWidth-2)
val f1ictype = misc1eff(misc1eff.getWidth-3,misc1eff.getWidth-4)
val f1prett = misc1eff(misc1eff.getWidth-5,misc1eff.getWidth-35)
val f1poffset = misc1eff(BHT_GHR_SIZE+11, BHT_GHR_SIZE)
val f1fghr = misc1eff(BHT_GHR_SIZE-1, 0)
val f0dbecc = misc0eff(misc0eff.getWidth-1)
f0icaf := misc0eff(misc0eff.getWidth-2)
val f0ictype = misc0eff(misc0eff.getWidth-3,misc0eff.getWidth-4)
val f0prett = misc0eff(misc0eff.getWidth-5,misc0eff.getWidth-35)
val f0poffset = misc0eff(BHT_GHR_SIZE+11, BHT_GHR_SIZE)
val f0fghr = misc0eff(BHT_GHR_SIZE-1, 0)
val brdata_in = Cat(io.ifu_bp_hist1_f(1),io.ifu_bp_hist0_f(1),io.ifu_bp_pc4_f(1),io.ifu_bp_way_f(1),io.ifu_bp_valid_f(1),
io.ifu_bp_ret_f(1), io.ifu_bp_hist1_f(0),io.ifu_bp_hist0_f(0),io.ifu_bp_pc4_f(0),io.ifu_bp_way_f(0),
io.ifu_bp_valid_f(0),io.ifu_bp_ret_f(0))
val brdataeff = Mux1H(Seq(qren(0).asBool->Cat(brdata1,brdata0),
qren(1).asBool->Cat(brdata2,brdata1),
qren(2).asBool->Cat(brdata0,brdata2)))
val (brdata0eff,brdata1eff) = (brdataeff(11,0) , brdataeff(23,12))
val q0 = WireInit(UInt(32.W), init = 0.U)
val q1 = WireInit(UInt(32.W), init = 0.U)
val q2 = WireInit(UInt(32.W), init = 0.U)
val qeff = Mux1H(Seq(qren(0).asBool->Cat(q1,q0),
qren(1).asBool->Cat(q2,q1),
qren(2).asBool->Cat(q0,q2)))
val (q1eff, q0eff) = (qeff(63,32), qeff(31,0))
val brdata0final = Mux1H(Seq(q0sel(0).asBool -> brdata0eff, q0sel(1).asBool -> brdata0eff(11,6)))
val brdata1final = Mux1H(Seq(q1sel(0).asBool -> brdata1eff, q1sel(1).asBool -> brdata1eff(11,6)))
val f0ret = Cat(brdata0final(6),brdata0final(0))
val f0brend = Cat(brdata0final(7),brdata0final(1))
val f0way = Cat(brdata0final(8),brdata0final(2))
val f0pc4 = Cat(brdata0final(9),brdata0final(3))
val f0hist0 = Cat(brdata0final(10),brdata0final(4))
val f0hist1 = Cat(brdata0final(11),brdata0final(5))
val f1ret = Cat(brdata1final(6),brdata1final(0))
val f1brend = Cat(brdata1final(7),brdata1final(1))
val f1way = Cat(brdata1final(8),brdata1final(2))
val f1pc4 = Cat(brdata1final(9),brdata1final(3))
val f1hist0 = Cat(brdata1final(10),brdata1final(4))
val f1hist1 = Cat(brdata1final(11),brdata1final(5))
f2_valid := f2val(0)
sf1_valid := sf1val(0)
sf0_valid := sf0val(0)
val consume_fb0 = !sf0val(0) & f0val(0)
val consume_fb1 = !sf1val(0) & f1val(0)
io.ifu_fb_consume1 := consume_fb0 & !consume_fb1 & !io.exu_flush_final
io.ifu_fb_consume2 := consume_fb0 & consume_fb1 & !io.exu_flush_final
ifvalid := io.ifu_fetch_val(0)
shift_f1_f0 := !sf0_valid & sf1_valid
shift_f2_f0 := !sf0_valid & !sf1_valid & f2_valid
shift_f2_f1 := !sf0_valid & sf1_valid & f2_valid
//val f0pc = WireInit(UInt(31.W), 0.U)
// val f2pc = WireInit(UInt(31.W), 0.U)
val f0pc_plus1 = f0pc + 1.U
val sf1pc = (Fill(31, f1_shift_2B) & f0pc_plus1) | (Fill(31, !f1_shift_2B) & f0pc)
f1pc_in := Mux1H(Seq(fetch_to_f1.asBool->io.ifu_fetch_pc,
shift_f2_f1.asBool->f2pc,
(!fetch_to_f1 & !shift_f2_f1).asBool -> sf1pc))
f0pc_in := Mux1H(Seq(fetch_to_f0.asBool->io.ifu_fetch_pc,
shift_f2_f0.asBool->f2pc,
shift_f1_f0.asBool->sf1pc,
(!fetch_to_f0 & !shift_f2_f0 & !shift_f1_f0).asBool->f0pc_plus1))
f2val_in := Mux1H(Seq((fetch_to_f2 & !io.exu_flush_final).asBool->io.ifu_fetch_val,
(!fetch_to_f2 & !shift_f2_f1 & !shift_f2_f0 & !io.exu_flush_final).asBool->f2val))
sf1val := Mux1H(Seq(f1_shift_2B.asBool->f1val(1), !f1_shift_2B.asBool->f1val))
f1val_in := Mux1H(Seq((fetch_to_f1 & !io.exu_flush_final).asBool -> io.ifu_fetch_val,
(shift_f2_f1 & !io.exu_flush_final).asBool->f2val,
(!fetch_to_f1 & !shift_f2_f1 & !shift_f1_f0 & !io.exu_flush_final).asBool->sf1val))
f0val := Mux1H(Seq(shift_2B.asBool -> f0val(1), (!shift_2B & !shift_4B).asBool -> f0val))
@ -385,9 +435,7 @@ class el2_ifu_aln_ctl extends Module with el2_lib {
q2 := RegEnable(io.ifu_fetch_data_f, 0.U, qwen(2))
q1 := RegEnable(io.ifu_fetch_data_f, 0.U, qwen(1))
q0 := RegEnable(io.ifu_fetch_data_f, 0.U, qwen(0))
}

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target/scala-2.12/classes/ifu/el2_ifu_aln_ctl.class
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target/scala-2.12/classes/ifu/ifu_aln$.class
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target/scala-2.12/classes/ifu/ifu_aln$delayedInit$body.class
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