From c438fae14afc3afe5e21acb37e1a98a53682c0c9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E2=80=8BLaraib=20Khan?= <​laraib.khan@lampromellon.com> Date: Thu, 24 Dec 2020 16:51:11 +0500 Subject: [PATCH] bus buffer added --- lsu_bus_buffer.fir | 14 +++++++------- lsu_bus_buffer.v | 14 +++++++------- src/main/scala/lib/lib.scala | 2 +- .../scala-2.12/classes/lib/lib$rvdffe$.class | Bin 10997 -> 10998 bytes .../classes/lib/lib$rvdffs_fpga$.class | Bin 3313 -> 3579 bytes 5 files changed, 15 insertions(+), 15 deletions(-) diff --git a/lsu_bus_buffer.fir b/lsu_bus_buffer.fir index 9c21b6e3..06a7b752 100644 --- a/lsu_bus_buffer.fir +++ b/lsu_bus_buffer.fir @@ -2540,34 +2540,34 @@ circuit lsu_bus_buffer : reg _T_1779 : UInt, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 377:33] _T_1779 <= obuf_rdrsp_tag_in @[lib.scala 377:33] obuf_rdrsp_tag <= _T_1779 @[lsu_bus_buffer.scala 353:18] - reg _T_1780 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + reg _T_1780 : UInt, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when obuf_wr_en : @[Reg.scala 28:19] _T_1780 <= obuf_tag0_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] obuf_tag0 <= _T_1780 @[lsu_bus_buffer.scala 354:13] - reg obuf_tag1 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + reg obuf_tag1 : UInt, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when obuf_wr_en : @[Reg.scala 28:19] obuf_tag1 <= obuf_tag1_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - reg obuf_merge : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + reg obuf_merge : UInt, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when obuf_wr_en : @[Reg.scala 28:19] obuf_merge <= obuf_merge_en @[Reg.scala 28:23] skip @[Reg.scala 28:19] - reg _T_1781 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + reg _T_1781 : UInt, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when obuf_wr_en : @[Reg.scala 28:19] _T_1781 <= obuf_write_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] obuf_write <= _T_1781 @[lsu_bus_buffer.scala 357:14] - reg _T_1782 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + reg _T_1782 : UInt, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when obuf_wr_en : @[Reg.scala 28:19] _T_1782 <= obuf_sideeffect_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] obuf_sideeffect <= _T_1782 @[lsu_bus_buffer.scala 358:19] - reg obuf_sz : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + reg obuf_sz : UInt, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when obuf_wr_en : @[Reg.scala 28:19] obuf_sz <= obuf_sz_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - reg obuf_byteen : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + reg obuf_byteen : UInt, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when obuf_wr_en : @[Reg.scala 28:19] obuf_byteen <= obuf_byteen_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] diff --git a/lsu_bus_buffer.v b/lsu_bus_buffer.v index 91f25979..babd62ec 100644 --- a/lsu_bus_buffer.v +++ b/lsu_bus_buffer.v @@ -3743,7 +3743,7 @@ end // initial buf_ageQ_3 <= {_T_2467,_T_2390}; end end - always @(posedge clock or posedge reset) begin + always @(posedge io_lsu_bus_obuf_c1_clk or posedge reset) begin if (reset) begin _T_1780 <= 2'h0; end else if (obuf_wr_en) begin @@ -3754,14 +3754,14 @@ end // initial end end end - always @(posedge clock or posedge reset) begin + always @(posedge io_lsu_bus_obuf_c1_clk or posedge reset) begin if (reset) begin obuf_merge <= 1'h0; end else if (obuf_wr_en) begin obuf_merge <= obuf_merge_en; end end - always @(posedge clock or posedge reset) begin + always @(posedge io_lsu_bus_obuf_c1_clk or posedge reset) begin if (reset) begin obuf_tag1 <= 2'h0; end else if (obuf_wr_en) begin @@ -4142,7 +4142,7 @@ end // initial _T_4305 <= buf_sideeffect_in[0]; end end - always @(posedge clock or posedge reset) begin + always @(posedge io_lsu_bus_obuf_c1_clk or posedge reset) begin if (reset) begin obuf_sideeffect <= 1'h0; end else if (obuf_wr_en) begin @@ -4209,7 +4209,7 @@ end // initial buf_samedw_0 <= buf_samedw_in[0]; end end - always @(posedge clock or posedge reset) begin + always @(posedge io_lsu_bus_obuf_c1_clk or posedge reset) begin if (reset) begin obuf_write <= 1'h0; end else if (obuf_wr_en) begin @@ -4336,7 +4336,7 @@ end // initial buf_dualhi_0 <= buf_dualhi_in[0]; end end - always @(posedge clock or posedge reset) begin + always @(posedge io_lsu_bus_obuf_c1_clk or posedge reset) begin if (reset) begin obuf_sz <= 2'h0; end else if (obuf_wr_en) begin @@ -4347,7 +4347,7 @@ end // initial end end end - always @(posedge clock or posedge reset) begin + always @(posedge io_lsu_bus_obuf_c1_clk or posedge reset) begin if (reset) begin obuf_byteen <= 8'h0; end else if (obuf_wr_en) begin diff --git a/src/main/scala/lib/lib.scala b/src/main/scala/lib/lib.scala index c1754997..1520e594 100644 --- a/src/main/scala/lib/lib.scala +++ b/src/main/scala/lib/lib.scala @@ -381,7 +381,7 @@ trait lib extends param{ def apply(din: UInt, en:Bool,clk: Clock, clken: Bool,rawclk:Clock):UInt = { if (RV_FPGA_OPTIMIZE) withClock (clk) {RegEnable (din, 0.U, clken & en)} - else RegEnable (din, 0.U,en) + else withClock (clk) {RegEnable (din, 0.U,en)} } } ////rvdffe /////////////////////////////////////////////////////////////////////// diff --git a/target/scala-2.12/classes/lib/lib$rvdffe$.class b/target/scala-2.12/classes/lib/lib$rvdffe$.class index 561c97b9f032fecaa8e01cd0d4edd5b02c248d79..1cf5f427fa60a286ffa4c9afb8f7e4aacf705eac 100644 GIT binary patch delta 84 zcmV-a0IUD?RrXb|YX}560RSbFu?ZBjg9rx(5)mX}Zf|a8b#5eKaBysSBr!0vn-2Q{ q0Wp)85KaLyljacp0W*{25l#U#vojJ-7zF_A0PO*jfhro4pej|admJPH delta 103 zcmews`ZaVzHV2CZBZKPXjhrHzn>pCo1O-$Q^YZi3O7m0_3kq^7RV+8p;rq?VXfSz( zfFGmbQ diff --git a/target/scala-2.12/classes/lib/lib$rvdffs_fpga$.class b/target/scala-2.12/classes/lib/lib$rvdffs_fpga$.class index d4ca4aeef376ee1957c0060bf1ef6ec63d0b44db..6a5cfca4d9ea975401a447a32d01215e3bd0ce9a 100644 GIT binary patch delta 1122 zcmZuvX-^YT6g{uYOgmH=P%EIam>RIfU=*d=sHl9=Q~?!Sz-1^?s7@Ct;D*!%Ma2!D z3+@~4Vx)=1V4}t^CjJNigMKt7#5+?kYHTvS_n!OiJ?Gu~zUTg&A$=JeeGi}AcNXbr_xZDCnV3G7i?RF{Y*hHU@8u+M>cXtpB&m3ytF#Vr!K ztqiQrf!***a9|I^q<2}VU6W+>=Cns1{H35Fs+`3{$%;HVu(aEy0~Rf~IYLZaX#gL6Xc z>S#C?($wl$dng)-i#WyLn8>Y)Ml}&<_%|_ZJBxD?`f#4_x2~LXQKCuo)5#LQ7HTS^ z&o{T8!CW%8-hmEWmSDjZ-eYTL*ZB|Ip!+6nNw|UAH0C=DS(*}VYF4V$xY`y{w9rA- zfqNLprbXQ6pY21_tu*{R%%J!oE%Ftt5Xdg$eUdvdHHrE2Jf)-91f;O`BmA!^XT~7? zi!ga=MELQDg2@Debz>S!z{8HUhY zS4fx@Pr$tyMG0M1H!_Svl}RY>B!cD?LMdpT(j@l2Lwsv?dlpN`i$<_Ng|3h2COC=X zDfAlQ=@c%caA{n<$q+2)LP)GGv@qQp+en`Nt3(4y(S=r`F<~fuLct_6oscOfqY<*4 z3wqDvQ(H^I_3JqQ(f5DW^mv@Z-HqRCbd=MKt>R>Hr_-sUxfN$ez!zvJY<0 z8_af(;Oa18>8+T-gg-XYg$&k%Ox9&wG)*c0-iVAGuGjC>PC&&e(z_A1!OR$vL1!bj`$k(b75|HAH4RRwDCg6eV@ Uqsc8qIn#$}+|+oC3@<5*UkicR>Hq)$ delta 924 zcmZ9K+fNfw5XQgLc6Zxtkp+~yLWoAvg%AYcK%&%kbb3f8(qdkH}Q`DEA5B(v+xQGqkd%KD|Tlq{7_{slII_Rb!%)B{qyoEy0X`-bi-Rtl!+Ab0 zHEfDuSf=0tL+0`kwugg}fT1@=`UBxmRKg_&&vI^CIBZB5<(1B$^9ruYxQuIj$(cnA zH)S|5#uZmTo8Y6aX)niJ8Fz3mRm6RUG(!uvcW4cIRPPIDMqohq;33A-!SIMT%WtzB zWJ!^3hHWO>Z^))YSCWpu^ltUIA$i%PTZB0h4^eT@*9P zhTygq)e)2T50hFFhcS;(TY5N+#gxifL=!l@h_fWeF_geXD;!DS`X73m1uU8%1Z#p8 zCTl|{JoBkTC!v_2b?Ay&q>~h+*lC4AIR#zxGDL9W*W_Bsn#WPpPY~FGSACBn?<{W3 zkd~a59ZdXdQiE`_5u~y~3m`MO`S+w0WFvG7ox@|m zyc5vfP4V88^*dgWZ=>iX*?jUE;KW8$p$3~#i!Jol-~nx~!Yf*l!59&iqry6l^*1m~ HQvyE$O`*8m