diff --git a/el2_ifu_bp_ctl.anno.json b/el2_ifu_bp_ctl.anno.json index dcf6b607..69285930 100644 --- a/el2_ifu_bp_ctl.anno.json +++ b/el2_ifu_bp_ctl.anno.json @@ -102,13 +102,6 @@ "~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_exu_i0_br_index_r" ] }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_test", - "sources":[ - "~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_addr_f" - ] - }, { "class":"firrtl.transforms.CombinationalPath", "sink":"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifu_bp_ret_f", diff --git a/el2_ifu_bp_ctl.fir b/el2_ifu_bp_ctl.fir index dd979c01..8a01d037 100644 --- a/el2_ifu_bp_ctl.fir +++ b/el2_ifu_bp_ctl.fir @@ -3,7 +3,7 @@ circuit el2_ifu_bp_ctl : module el2_ifu_bp_ctl : input clock : Clock input reset : AsyncReset - output io : {flip active_clk : Clock, flip ic_hit_f : UInt<1>, flip ifc_fetch_addr_f : UInt<31>, flip ifc_fetch_req_f : UInt<1>, flip dec_tlu_br0_r_pkt : {valid : UInt<1>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}, flip exu_i0_br_fghr_r : UInt<8>, flip exu_i0_br_index_r : UInt<8>, flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_flush_leak_one_wb : UInt<1>, flip dec_tlu_bpred_disable : UInt<1>, flip exu_mp_pkt : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, valid : UInt<1>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<32>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}, flip exu_mp_eghr : UInt<8>, flip exu_mp_fghr : UInt<8>, flip exu_mp_index : UInt<8>, flip exu_mp_btag : UInt<5>, flip exu_flush_final : UInt<1>, ifu_bp_hit_taken_f : UInt<1>, ifu_bp_btb_target_f : UInt<31>, ifu_bp_inst_mask_f : UInt<1>, ifu_bp_fghr_f : UInt<8>, ifu_bp_way_f : UInt<2>, ifu_bp_ret_f : UInt<2>, ifu_bp_hist1_f : UInt<2>, ifu_bp_hist0_f : UInt<2>, ifu_bp_pc4_f : UInt<2>, ifu_bp_valid_f : UInt<2>, ifu_bp_poffset_f : UInt<12>, test : UInt} + output io : {flip active_clk : Clock, flip ic_hit_f : UInt<1>, flip ifc_fetch_addr_f : UInt<31>, flip ifc_fetch_req_f : UInt<1>, flip dec_tlu_br0_r_pkt : {valid : UInt<1>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}, flip exu_i0_br_fghr_r : UInt<8>, flip exu_i0_br_index_r : UInt<8>, flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_flush_leak_one_wb : UInt<1>, flip dec_tlu_bpred_disable : UInt<1>, flip exu_mp_pkt : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, valid : UInt<1>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<32>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}, flip exu_mp_eghr : UInt<8>, flip exu_mp_fghr : UInt<8>, flip exu_mp_index : UInt<8>, flip exu_mp_btag : UInt<5>, flip exu_flush_final : UInt<1>, ifu_bp_hit_taken_f : UInt<1>, ifu_bp_btb_target_f : UInt<31>, ifu_bp_inst_mask_f : UInt<1>, ifu_bp_fghr_f : UInt<8>, ifu_bp_way_f : UInt<2>, ifu_bp_ret_f : UInt<2>, ifu_bp_hist1_f : UInt<2>, ifu_bp_hist0_f : UInt<2>, ifu_bp_pc4_f : UInt<2>, ifu_bp_valid_f : UInt<2>, ifu_bp_poffset_f : UInt<12>} wire leak_one_f : UInt<1> leak_one_f <= UInt<1>("h00") @@ -29568,5 +29568,4 @@ circuit el2_ifu_bp_ctl : wire _T_24155 : UInt<2> @[Mux.scala 27:72] _T_24155 <= _T_24154 @[Mux.scala 27:72] bht_bank0_rd_data_p1_f <= _T_24155 @[el2_ifu_bp_ctl.scala 397:26] - io.test <= bht_rd_addr_hashed_f @[el2_ifu_bp_ctl.scala 398:11] diff --git a/el2_ifu_bp_ctl.v b/el2_ifu_bp_ctl.v index 9317cf37..2e7eedf5 100644 --- a/el2_ifu_bp_ctl.v +++ b/el2_ifu_bp_ctl.v @@ -45,8 +45,7 @@ module el2_ifu_bp_ctl( output [1:0] io_ifu_bp_hist0_f, output [1:0] io_ifu_bp_pc4_f, output [1:0] io_ifu_bp_valid_f, - output [11:0] io_ifu_bp_poffset_f, - output [7:0] io_test + output [11:0] io_ifu_bp_poffset_f ); `ifdef RANDOMIZE_REG_INIT reg [31:0] _RAND_0; @@ -10042,7 +10041,6 @@ module el2_ifu_bp_ctl( assign io_ifu_bp_pc4_f = {_T_284,_T_287}; // @[el2_ifu_bp_ctl.scala 290:19] assign io_ifu_bp_valid_f = vwayhit_f & _T_342; // @[el2_ifu_bp_ctl.scala 292:21] assign io_ifu_bp_poffset_f = btb_sel_data_f[15:4]; // @[el2_ifu_bp_ctl.scala 305:23] - assign io_test = _T_566[9:2] ^ fghr; // @[el2_ifu_bp_ctl.scala 398:11] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif diff --git a/src/main/scala/ifu/el2_ifu_bp_ctl.scala b/src/main/scala/ifu/el2_ifu_bp_ctl.scala index f41289a5..941b046d 100644 --- a/src/main/scala/ifu/el2_ifu_bp_ctl.scala +++ b/src/main/scala/ifu/el2_ifu_bp_ctl.scala @@ -38,7 +38,7 @@ class el2_ifu_bp_ctl extends Module with el2_lib with RequireAsyncReset { val ifu_bp_pc4_f = Output(UInt(2.W)) val ifu_bp_valid_f = Output(UInt(2.W)) val ifu_bp_poffset_f = Output(UInt(12.W)) - val test = Output(UInt()) + //val test = Output(UInt()) }) val TAG_START = 16+BTB_BTAG_SIZE @@ -395,7 +395,7 @@ class el2_ifu_bp_ctl extends Module with el2_lib with RequireAsyncReset { bht_bank0_rd_data_f := Mux1H((0 until BHT_ARRAY_DEPTH).map(i=>(bht_rd_addr_f(BHT_ADDR_HI-BHT_ADDR_LO,0)===i.U).asBool->bht_bank_rd_data_out(0)(i))) bht_bank1_rd_data_f := Mux1H((0 until BHT_ARRAY_DEPTH).map(i=>(bht_rd_addr_f(BHT_ADDR_HI-BHT_ADDR_LO,0)===i.U).asBool->bht_bank_rd_data_out(1)(i))) bht_bank0_rd_data_p1_f := Mux1H((0 until BHT_ARRAY_DEPTH).map(i=>(bht_rd_addr_p1_f(BHT_ADDR_HI-BHT_ADDR_LO,0)===i.U).asBool->bht_bank_rd_data_out(1)(i))) - io.test := bht_rd_addr_f + // io.test := bht_rd_addr_f } object ifu_bp extends App { diff --git a/target/scala-2.12/classes/ifu/el2_ifu_bp_ctl$$anon$1.class b/target/scala-2.12/classes/ifu/el2_ifu_bp_ctl$$anon$1.class index 47f7a0d9..d87c86c9 100644 Binary files a/target/scala-2.12/classes/ifu/el2_ifu_bp_ctl$$anon$1.class and b/target/scala-2.12/classes/ifu/el2_ifu_bp_ctl$$anon$1.class differ diff --git a/target/scala-2.12/classes/ifu/el2_ifu_bp_ctl.class b/target/scala-2.12/classes/ifu/el2_ifu_bp_ctl.class index 2700fd4a..6d850aab 100644 Binary files a/target/scala-2.12/classes/ifu/el2_ifu_bp_ctl.class and b/target/scala-2.12/classes/ifu/el2_ifu_bp_ctl.class differ