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ahb to axi update

This commit is contained in:
​Laraib Khan 2020-12-02 15:58:23 +05:00
parent 76f0c4f9a9
commit c5414d6a20
6 changed files with 372 additions and 376 deletions
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480
ahb_to_axi4.fir
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@ -177,10 +177,6 @@ circuit ahb_to_axi4 :
ahb_hwdata_q <= UInt<64>("h00") ahb_hwdata_q <= UInt<64>("h00")
wire ahb_hresp_q : UInt<1> wire ahb_hresp_q : UInt<1>
ahb_hresp_q <= UInt<1>("h00") ahb_hresp_q <= UInt<1>("h00")
wire ahb_addr_in_iccm : UInt<1>
ahb_addr_in_iccm <= UInt<1>("h00")
wire ahb_addr_in_iccm_region_nc : UInt<1>
ahb_addr_in_iccm_region_nc <= UInt<1>("h00")
wire buf_rdata_en : UInt<1> wire buf_rdata_en : UInt<1>
buf_rdata_en <= UInt<1>("h00") buf_rdata_en <= UInt<1>("h00")
wire ahb_bus_addr_clk_en : UInt<1> wire ahb_bus_addr_clk_en : UInt<1>
@ -209,278 +205,276 @@ circuit ahb_to_axi4 :
wire cmdbuf_wdata : UInt<64> wire cmdbuf_wdata : UInt<64>
cmdbuf_wdata <= UInt<64>("h00") cmdbuf_wdata <= UInt<64>("h00")
wire bus_clk : Clock @[ahb_to_axi4.scala 98:35] wire bus_clk : Clock @[ahb_to_axi4.scala 98:35]
node _T = bits(ahb_haddr_q, 31, 28) @[el2_lib.scala 496:27] node _T = bits(ahb_haddr_q, 31, 28) @[el2_lib.scala 224:25]
node ahb_addr_in_dccm_region_nc = eq(_T, UInt<4>("h0f")) @[el2_lib.scala 496:49] node ahb_addr_in_dccm_region_nc = eq(_T, UInt<4>("h0f")) @[el2_lib.scala 224:47]
wire ahb_addr_in_dccm : UInt<1> @[el2_lib.scala 497:26] node _T_1 = bits(ahb_haddr_q, 31, 16) @[el2_lib.scala 227:14]
node _T_1 = bits(ahb_haddr_q, 31, 16) @[el2_lib.scala 501:24] node ahb_addr_in_dccm = eq(_T_1, UInt<16>("h0f004")) @[el2_lib.scala 227:29]
node _T_2 = eq(_T_1, UInt<16>("h0f004")) @[el2_lib.scala 501:39] node _T_2 = bits(ahb_haddr_q, 31, 28) @[el2_lib.scala 224:25]
ahb_addr_in_dccm <= _T_2 @[el2_lib.scala 501:16] node ahb_addr_in_iccm_region_nc = eq(_T_2, UInt<4>("h0e")) @[el2_lib.scala 224:47]
ahb_addr_in_iccm <= UInt<1>("h00") @[ahb_to_axi4.scala 109:24] node _T_3 = bits(ahb_haddr_q, 31, 16) @[el2_lib.scala 227:14]
ahb_addr_in_iccm_region_nc <= UInt<1>("h00") @[ahb_to_axi4.scala 110:34] node ahb_addr_in_iccm = eq(_T_3, UInt<16>("h0ee00")) @[el2_lib.scala 227:29]
node _T_3 = bits(ahb_haddr_q, 31, 28) @[el2_lib.scala 496:27] node _T_4 = bits(ahb_haddr_q, 31, 28) @[el2_lib.scala 224:25]
node ahb_addr_in_pic_region_nc = eq(_T_3, UInt<4>("h0f")) @[el2_lib.scala 496:49] node ahb_addr_in_pic_region_nc = eq(_T_4, UInt<4>("h0f")) @[el2_lib.scala 224:47]
wire ahb_addr_in_pic : UInt<1> @[el2_lib.scala 497:26] node _T_5 = bits(ahb_haddr_q, 31, 15) @[el2_lib.scala 227:14]
node _T_4 = bits(ahb_haddr_q, 31, 15) @[el2_lib.scala 501:24] node ahb_addr_in_pic = eq(_T_5, UInt<17>("h01e018")) @[el2_lib.scala 227:29]
node _T_5 = eq(_T_4, UInt<17>("h01e018")) @[el2_lib.scala 501:39]
ahb_addr_in_pic <= _T_5 @[el2_lib.scala 501:16]
wire buf_state : UInt<2> wire buf_state : UInt<2>
buf_state <= UInt<2>("h00") buf_state <= UInt<2>("h00")
wire buf_nxtstate : UInt<2> wire buf_nxtstate : UInt<2>
buf_nxtstate <= UInt<2>("h00") buf_nxtstate <= UInt<2>("h00")
buf_nxtstate <= UInt<2>("h00") @[ahb_to_axi4.scala 119:33] buf_nxtstate <= UInt<2>("h00") @[ahb_to_axi4.scala 118:33]
buf_state_en <= UInt<1>("h00") @[ahb_to_axi4.scala 120:33] buf_state_en <= UInt<1>("h00") @[ahb_to_axi4.scala 119:33]
buf_rdata_en <= UInt<1>("h00") @[ahb_to_axi4.scala 121:33] buf_rdata_en <= UInt<1>("h00") @[ahb_to_axi4.scala 120:33]
buf_read_error_in <= UInt<1>("h00") @[ahb_to_axi4.scala 122:33] buf_read_error_in <= UInt<1>("h00") @[ahb_to_axi4.scala 121:33]
cmdbuf_wr_en <= UInt<1>("h00") @[ahb_to_axi4.scala 123:33] cmdbuf_wr_en <= UInt<1>("h00") @[ahb_to_axi4.scala 122:33]
node _T_6 = eq(UInt<2>("h00"), buf_state) @[Conditional.scala 37:30] node _T_6 = eq(UInt<2>("h00"), buf_state) @[Conditional.scala 37:30]
when _T_6 : @[Conditional.scala 40:58] when _T_6 : @[Conditional.scala 40:58]
node _T_7 = mux(io.ahb_hwrite, UInt<2>("h01"), UInt<2>("h02")) @[ahb_to_axi4.scala 127:28] node _T_7 = mux(io.ahb_hwrite, UInt<2>("h01"), UInt<2>("h02")) @[ahb_to_axi4.scala 126:28]
buf_nxtstate <= _T_7 @[ahb_to_axi4.scala 127:22] buf_nxtstate <= _T_7 @[ahb_to_axi4.scala 126:22]
node _T_8 = bits(io.ahb_htrans, 1, 1) @[ahb_to_axi4.scala 128:51] node _T_8 = bits(io.ahb_htrans, 1, 1) @[ahb_to_axi4.scala 127:51]
node _T_9 = and(ahb_hready, _T_8) @[ahb_to_axi4.scala 128:36] node _T_9 = and(ahb_hready, _T_8) @[ahb_to_axi4.scala 127:36]
node _T_10 = and(_T_9, io.ahb_hsel) @[ahb_to_axi4.scala 128:55] node _T_10 = and(_T_9, io.ahb_hsel) @[ahb_to_axi4.scala 127:55]
buf_state_en <= _T_10 @[ahb_to_axi4.scala 128:22] buf_state_en <= _T_10 @[ahb_to_axi4.scala 127:22]
skip @[Conditional.scala 40:58] skip @[Conditional.scala 40:58]
else : @[Conditional.scala 39:67] else : @[Conditional.scala 39:67]
node _T_11 = eq(UInt<2>("h01"), buf_state) @[Conditional.scala 37:30] node _T_11 = eq(UInt<2>("h01"), buf_state) @[Conditional.scala 37:30]
when _T_11 : @[Conditional.scala 39:67] when _T_11 : @[Conditional.scala 39:67]
node _T_12 = bits(io.ahb_htrans, 1, 0) @[ahb_to_axi4.scala 131:59] node _T_12 = bits(io.ahb_htrans, 1, 0) @[ahb_to_axi4.scala 130:59]
node _T_13 = eq(_T_12, UInt<1>("h00")) @[ahb_to_axi4.scala 131:66] node _T_13 = eq(_T_12, UInt<1>("h00")) @[ahb_to_axi4.scala 130:66]
node _T_14 = or(io.ahb_hresp, _T_13) @[ahb_to_axi4.scala 131:43] node _T_14 = or(io.ahb_hresp, _T_13) @[ahb_to_axi4.scala 130:43]
node _T_15 = eq(io.ahb_hsel, UInt<1>("h00")) @[ahb_to_axi4.scala 131:80] node _T_15 = eq(io.ahb_hsel, UInt<1>("h00")) @[ahb_to_axi4.scala 130:80]
node _T_16 = or(_T_14, _T_15) @[ahb_to_axi4.scala 131:78] node _T_16 = or(_T_14, _T_15) @[ahb_to_axi4.scala 130:78]
node _T_17 = bits(_T_16, 0, 0) @[ahb_to_axi4.scala 131:94] node _T_17 = bits(_T_16, 0, 0) @[ahb_to_axi4.scala 130:94]
node _T_18 = mux(io.ahb_hwrite, UInt<2>("h01"), UInt<2>("h02")) @[ahb_to_axi4.scala 131:111] node _T_18 = mux(io.ahb_hwrite, UInt<2>("h01"), UInt<2>("h02")) @[ahb_to_axi4.scala 130:111]
node _T_19 = mux(_T_17, UInt<2>("h00"), _T_18) @[ahb_to_axi4.scala 131:28] node _T_19 = mux(_T_17, UInt<2>("h00"), _T_18) @[ahb_to_axi4.scala 130:28]
buf_nxtstate <= _T_19 @[ahb_to_axi4.scala 131:22] buf_nxtstate <= _T_19 @[ahb_to_axi4.scala 130:22]
node _T_20 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 132:26] node _T_20 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 131:26]
node _T_21 = or(_T_20, io.ahb_hresp) @[ahb_to_axi4.scala 132:39] node _T_21 = or(_T_20, io.ahb_hresp) @[ahb_to_axi4.scala 131:39]
buf_state_en <= _T_21 @[ahb_to_axi4.scala 132:22] buf_state_en <= _T_21 @[ahb_to_axi4.scala 131:22]
node _T_22 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 133:25] node _T_22 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 132:25]
node _T_23 = bits(io.ahb_htrans, 1, 0) @[ahb_to_axi4.scala 133:72] node _T_23 = bits(io.ahb_htrans, 1, 0) @[ahb_to_axi4.scala 132:72]
node _T_24 = eq(_T_23, UInt<2>("h01")) @[ahb_to_axi4.scala 133:79] node _T_24 = eq(_T_23, UInt<2>("h01")) @[ahb_to_axi4.scala 132:79]
node _T_25 = and(_T_24, io.ahb_hsel) @[ahb_to_axi4.scala 133:97] node _T_25 = and(_T_24, io.ahb_hsel) @[ahb_to_axi4.scala 132:97]
node _T_26 = or(io.ahb_hresp, _T_25) @[ahb_to_axi4.scala 133:55] node _T_26 = or(io.ahb_hresp, _T_25) @[ahb_to_axi4.scala 132:55]
node _T_27 = eq(_T_26, UInt<1>("h00")) @[ahb_to_axi4.scala 133:40] node _T_27 = eq(_T_26, UInt<1>("h00")) @[ahb_to_axi4.scala 132:40]
node _T_28 = and(_T_22, _T_27) @[ahb_to_axi4.scala 133:38] node _T_28 = and(_T_22, _T_27) @[ahb_to_axi4.scala 132:38]
cmdbuf_wr_en <= _T_28 @[ahb_to_axi4.scala 133:22] cmdbuf_wr_en <= _T_28 @[ahb_to_axi4.scala 132:22]
skip @[Conditional.scala 39:67] skip @[Conditional.scala 39:67]
else : @[Conditional.scala 39:67] else : @[Conditional.scala 39:67]
node _T_29 = eq(UInt<2>("h02"), buf_state) @[Conditional.scala 37:30] node _T_29 = eq(UInt<2>("h02"), buf_state) @[Conditional.scala 37:30]
when _T_29 : @[Conditional.scala 39:67] when _T_29 : @[Conditional.scala 39:67]
node _T_30 = mux(io.ahb_hresp, UInt<2>("h00"), UInt<2>("h03")) @[ahb_to_axi4.scala 136:28] node _T_30 = mux(io.ahb_hresp, UInt<2>("h00"), UInt<2>("h03")) @[ahb_to_axi4.scala 135:28]
buf_nxtstate <= _T_30 @[ahb_to_axi4.scala 136:22] buf_nxtstate <= _T_30 @[ahb_to_axi4.scala 135:22]
node _T_31 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 137:26] node _T_31 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 136:26]
node _T_32 = or(_T_31, io.ahb_hresp) @[ahb_to_axi4.scala 137:39] node _T_32 = or(_T_31, io.ahb_hresp) @[ahb_to_axi4.scala 136:39]
buf_state_en <= _T_32 @[ahb_to_axi4.scala 137:22] buf_state_en <= _T_32 @[ahb_to_axi4.scala 136:22]
node _T_33 = eq(io.ahb_hresp, UInt<1>("h00")) @[ahb_to_axi4.scala 138:25] node _T_33 = eq(io.ahb_hresp, UInt<1>("h00")) @[ahb_to_axi4.scala 137:25]
node _T_34 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 138:41] node _T_34 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 137:41]
node _T_35 = and(_T_33, _T_34) @[ahb_to_axi4.scala 138:39] node _T_35 = and(_T_33, _T_34) @[ahb_to_axi4.scala 137:39]
cmdbuf_wr_en <= _T_35 @[ahb_to_axi4.scala 138:22] cmdbuf_wr_en <= _T_35 @[ahb_to_axi4.scala 137:22]
skip @[Conditional.scala 39:67] skip @[Conditional.scala 39:67]
else : @[Conditional.scala 39:67] else : @[Conditional.scala 39:67]
node _T_36 = eq(UInt<2>("h03"), buf_state) @[Conditional.scala 37:30] node _T_36 = eq(UInt<2>("h03"), buf_state) @[Conditional.scala 37:30]
when _T_36 : @[Conditional.scala 39:67] when _T_36 : @[Conditional.scala 39:67]
buf_nxtstate <= UInt<2>("h00") @[ahb_to_axi4.scala 141:22] buf_nxtstate <= UInt<2>("h00") @[ahb_to_axi4.scala 140:22]
node _T_37 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 142:41] node _T_37 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 141:41]
node _T_38 = and(io.axi_rvalid, _T_37) @[ahb_to_axi4.scala 142:39] node _T_38 = and(io.axi_rvalid, _T_37) @[ahb_to_axi4.scala 141:39]
buf_state_en <= _T_38 @[ahb_to_axi4.scala 142:22] buf_state_en <= _T_38 @[ahb_to_axi4.scala 141:22]
buf_rdata_en <= buf_state_en @[ahb_to_axi4.scala 143:22] buf_rdata_en <= buf_state_en @[ahb_to_axi4.scala 142:22]
node _T_39 = bits(io.axi_rresp, 1, 0) @[ahb_to_axi4.scala 144:57] node _T_39 = bits(io.axi_rresp, 1, 0) @[ahb_to_axi4.scala 143:57]
node _T_40 = orr(_T_39) @[ahb_to_axi4.scala 144:64] node _T_40 = orr(_T_39) @[ahb_to_axi4.scala 143:64]
node _T_41 = and(buf_state_en, _T_40) @[ahb_to_axi4.scala 144:43] node _T_41 = and(buf_state_en, _T_40) @[ahb_to_axi4.scala 143:43]
buf_read_error_in <= _T_41 @[ahb_to_axi4.scala 144:27] buf_read_error_in <= _T_41 @[ahb_to_axi4.scala 143:27]
skip @[Conditional.scala 39:67] skip @[Conditional.scala 39:67]
node _T_42 = bits(buf_state_en, 0, 0) @[ahb_to_axi4.scala 147:101] node _T_42 = bits(buf_state_en, 0, 0) @[ahb_to_axi4.scala 146:101]
reg _T_43 : UInt, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] reg _T_43 : UInt, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_42 : @[Reg.scala 28:19] when _T_42 : @[Reg.scala 28:19]
_T_43 <= buf_nxtstate @[Reg.scala 28:23] _T_43 <= buf_nxtstate @[Reg.scala 28:23]
skip @[Reg.scala 28:19] skip @[Reg.scala 28:19]
buf_state <= _T_43 @[ahb_to_axi4.scala 147:33] buf_state <= _T_43 @[ahb_to_axi4.scala 146:33]
node _T_44 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 149:56] node _T_44 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 148:56]
node _T_45 = eq(_T_44, UInt<1>("h00")) @[ahb_to_axi4.scala 149:62] node _T_45 = eq(_T_44, UInt<1>("h00")) @[ahb_to_axi4.scala 148:62]
node _T_46 = bits(_T_45, 0, 0) @[Bitwise.scala 72:15] node _T_46 = bits(_T_45, 0, 0) @[Bitwise.scala 72:15]
node _T_47 = mux(_T_46, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] node _T_47 = mux(_T_46, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
node _T_48 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 149:94] node _T_48 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 148:94]
node _T_49 = dshl(UInt<1>("h01"), _T_48) @[ahb_to_axi4.scala 149:80] node _T_49 = dshl(UInt<1>("h01"), _T_48) @[ahb_to_axi4.scala 148:80]
node _T_50 = and(_T_47, _T_49) @[ahb_to_axi4.scala 149:72] node _T_50 = and(_T_47, _T_49) @[ahb_to_axi4.scala 148:72]
node _T_51 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 150:56] node _T_51 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 149:56]
node _T_52 = eq(_T_51, UInt<1>("h01")) @[ahb_to_axi4.scala 150:62] node _T_52 = eq(_T_51, UInt<1>("h01")) @[ahb_to_axi4.scala 149:62]
node _T_53 = bits(_T_52, 0, 0) @[Bitwise.scala 72:15] node _T_53 = bits(_T_52, 0, 0) @[Bitwise.scala 72:15]
node _T_54 = mux(_T_53, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] node _T_54 = mux(_T_53, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
node _T_55 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 150:94] node _T_55 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 149:94]
node _T_56 = dshl(UInt<2>("h03"), _T_55) @[ahb_to_axi4.scala 150:80] node _T_56 = dshl(UInt<2>("h03"), _T_55) @[ahb_to_axi4.scala 149:80]
node _T_57 = and(_T_54, _T_56) @[ahb_to_axi4.scala 150:72] node _T_57 = and(_T_54, _T_56) @[ahb_to_axi4.scala 149:72]
node _T_58 = or(_T_50, _T_57) @[ahb_to_axi4.scala 149:111] node _T_58 = or(_T_50, _T_57) @[ahb_to_axi4.scala 148:111]
node _T_59 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 151:56] node _T_59 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 150:56]
node _T_60 = eq(_T_59, UInt<2>("h02")) @[ahb_to_axi4.scala 151:62] node _T_60 = eq(_T_59, UInt<2>("h02")) @[ahb_to_axi4.scala 150:62]
node _T_61 = bits(_T_60, 0, 0) @[Bitwise.scala 72:15] node _T_61 = bits(_T_60, 0, 0) @[Bitwise.scala 72:15]
node _T_62 = mux(_T_61, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] node _T_62 = mux(_T_61, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
node _T_63 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 151:94] node _T_63 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 150:94]
node _T_64 = dshl(UInt<4>("h0f"), _T_63) @[ahb_to_axi4.scala 151:80] node _T_64 = dshl(UInt<4>("h0f"), _T_63) @[ahb_to_axi4.scala 150:80]
node _T_65 = and(_T_62, _T_64) @[ahb_to_axi4.scala 151:72] node _T_65 = and(_T_62, _T_64) @[ahb_to_axi4.scala 150:72]
node _T_66 = or(_T_58, _T_65) @[ahb_to_axi4.scala 150:111] node _T_66 = or(_T_58, _T_65) @[ahb_to_axi4.scala 149:111]
node _T_67 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 152:56] node _T_67 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 151:56]
node _T_68 = eq(_T_67, UInt<2>("h03")) @[ahb_to_axi4.scala 152:62] node _T_68 = eq(_T_67, UInt<2>("h03")) @[ahb_to_axi4.scala 151:62]
node _T_69 = bits(_T_68, 0, 0) @[Bitwise.scala 72:15] node _T_69 = bits(_T_68, 0, 0) @[Bitwise.scala 72:15]
node _T_70 = mux(_T_69, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] node _T_70 = mux(_T_69, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
node _T_71 = and(_T_70, UInt<8>("h0ff")) @[ahb_to_axi4.scala 152:72] node _T_71 = and(_T_70, UInt<8>("h0ff")) @[ahb_to_axi4.scala 151:72]
node _T_72 = or(_T_66, _T_71) @[ahb_to_axi4.scala 151:111] node _T_72 = or(_T_66, _T_71) @[ahb_to_axi4.scala 150:111]
master_wstrb <= _T_72 @[ahb_to_axi4.scala 149:33] master_wstrb <= _T_72 @[ahb_to_axi4.scala 148:33]
node _T_73 = eq(ahb_hready_q, UInt<1>("h00")) @[ahb_to_axi4.scala 155:68] node _T_73 = eq(ahb_hready_q, UInt<1>("h00")) @[ahb_to_axi4.scala 154:68]
node _T_74 = and(ahb_hresp_q, _T_73) @[ahb_to_axi4.scala 155:66] node _T_74 = and(ahb_hresp_q, _T_73) @[ahb_to_axi4.scala 154:66]
node _T_75 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 155:86] node _T_75 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 154:86]
node _T_76 = eq(buf_state, UInt<2>("h00")) @[ahb_to_axi4.scala 155:112] node _T_76 = eq(buf_state, UInt<2>("h00")) @[ahb_to_axi4.scala 154:112]
node _T_77 = or(_T_75, _T_76) @[ahb_to_axi4.scala 155:99] node _T_77 = or(_T_75, _T_76) @[ahb_to_axi4.scala 154:99]
node _T_78 = eq(buf_state, UInt<2>("h02")) @[ahb_to_axi4.scala 155:137] node _T_78 = eq(buf_state, UInt<2>("h02")) @[ahb_to_axi4.scala 154:137]
node _T_79 = eq(buf_state, UInt<2>("h03")) @[ahb_to_axi4.scala 155:156] node _T_79 = eq(buf_state, UInt<2>("h03")) @[ahb_to_axi4.scala 154:156]
node _T_80 = or(_T_78, _T_79) @[ahb_to_axi4.scala 155:144] node _T_80 = or(_T_78, _T_79) @[ahb_to_axi4.scala 154:144]
node _T_81 = eq(_T_80, UInt<1>("h00")) @[ahb_to_axi4.scala 155:125] node _T_81 = eq(_T_80, UInt<1>("h00")) @[ahb_to_axi4.scala 154:125]
node _T_82 = and(_T_77, _T_81) @[ahb_to_axi4.scala 155:123] node _T_82 = and(_T_77, _T_81) @[ahb_to_axi4.scala 154:123]
node _T_83 = eq(buf_read_error, UInt<1>("h00")) @[ahb_to_axi4.scala 155:169] node _T_83 = eq(buf_read_error, UInt<1>("h00")) @[ahb_to_axi4.scala 154:169]
node _T_84 = and(_T_82, _T_83) @[ahb_to_axi4.scala 155:167] node _T_84 = and(_T_82, _T_83) @[ahb_to_axi4.scala 154:167]
node _T_85 = mux(io.ahb_hresp, _T_74, _T_84) @[ahb_to_axi4.scala 155:39] node _T_85 = mux(io.ahb_hresp, _T_74, _T_84) @[ahb_to_axi4.scala 154:39]
io.ahb_hreadyout <= _T_85 @[ahb_to_axi4.scala 155:33] io.ahb_hreadyout <= _T_85 @[ahb_to_axi4.scala 154:33]
node _T_86 = and(io.ahb_hreadyout, io.ahb_hreadyin) @[ahb_to_axi4.scala 156:53] node _T_86 = and(io.ahb_hreadyout, io.ahb_hreadyin) @[ahb_to_axi4.scala 155:53]
ahb_hready <= _T_86 @[ahb_to_axi4.scala 156:33] ahb_hready <= _T_86 @[ahb_to_axi4.scala 155:33]
node _T_87 = bits(io.ahb_hsel, 0, 0) @[Bitwise.scala 72:15] node _T_87 = bits(io.ahb_hsel, 0, 0) @[Bitwise.scala 72:15]
node _T_88 = mux(_T_87, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] node _T_88 = mux(_T_87, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
node _T_89 = bits(io.ahb_htrans, 1, 0) @[ahb_to_axi4.scala 157:71] node _T_89 = bits(io.ahb_htrans, 1, 0) @[ahb_to_axi4.scala 156:71]
node _T_90 = and(_T_88, _T_89) @[ahb_to_axi4.scala 157:56] node _T_90 = and(_T_88, _T_89) @[ahb_to_axi4.scala 156:56]
ahb_htrans_in <= _T_90 @[ahb_to_axi4.scala 157:33] ahb_htrans_in <= _T_90 @[ahb_to_axi4.scala 156:33]
node _T_91 = bits(buf_rdata, 63, 0) @[ahb_to_axi4.scala 158:45] node _T_91 = bits(buf_rdata, 63, 0) @[ahb_to_axi4.scala 157:45]
io.ahb_hrdata <= _T_91 @[ahb_to_axi4.scala 158:33] io.ahb_hrdata <= _T_91 @[ahb_to_axi4.scala 157:33]
node _T_92 = bits(ahb_htrans_q, 1, 0) @[ahb_to_axi4.scala 159:50] node _T_92 = bits(ahb_htrans_q, 1, 0) @[ahb_to_axi4.scala 158:50]
node _T_93 = neq(_T_92, UInt<1>("h00")) @[ahb_to_axi4.scala 159:56] node _T_93 = neq(_T_92, UInt<1>("h00")) @[ahb_to_axi4.scala 158:56]
node _T_94 = neq(buf_state, UInt<2>("h00")) @[ahb_to_axi4.scala 159:78] node _T_94 = neq(buf_state, UInt<2>("h00")) @[ahb_to_axi4.scala 158:78]
node _T_95 = and(_T_93, _T_94) @[ahb_to_axi4.scala 159:65] node _T_95 = and(_T_93, _T_94) @[ahb_to_axi4.scala 158:65]
node _T_96 = or(ahb_addr_in_dccm, ahb_addr_in_iccm) @[ahb_to_axi4.scala 160:57] node _T_96 = or(ahb_addr_in_dccm, ahb_addr_in_iccm) @[ahb_to_axi4.scala 159:57]
node _T_97 = eq(_T_96, UInt<1>("h00")) @[ahb_to_axi4.scala 160:38] node _T_97 = eq(_T_96, UInt<1>("h00")) @[ahb_to_axi4.scala 159:38]
node _T_98 = and(ahb_addr_in_dccm, ahb_hwrite_q) @[ahb_to_axi4.scala 161:75] node _T_98 = and(ahb_addr_in_dccm, ahb_hwrite_q) @[ahb_to_axi4.scala 160:75]
node _T_99 = or(ahb_addr_in_iccm, _T_98) @[ahb_to_axi4.scala 161:55] node _T_99 = or(ahb_addr_in_iccm, _T_98) @[ahb_to_axi4.scala 160:55]
node _T_100 = bits(ahb_hsize_q, 1, 0) @[ahb_to_axi4.scala 161:109] node _T_100 = bits(ahb_hsize_q, 1, 0) @[ahb_to_axi4.scala 160:109]
node _T_101 = eq(_T_100, UInt<2>("h02")) @[ahb_to_axi4.scala 161:115] node _T_101 = eq(_T_100, UInt<2>("h02")) @[ahb_to_axi4.scala 160:115]
node _T_102 = bits(ahb_hsize_q, 1, 0) @[ahb_to_axi4.scala 161:138] node _T_102 = bits(ahb_hsize_q, 1, 0) @[ahb_to_axi4.scala 160:138]
node _T_103 = eq(_T_102, UInt<2>("h03")) @[ahb_to_axi4.scala 161:144] node _T_103 = eq(_T_102, UInt<2>("h03")) @[ahb_to_axi4.scala 160:144]
node _T_104 = or(_T_101, _T_103) @[ahb_to_axi4.scala 161:124] node _T_104 = or(_T_101, _T_103) @[ahb_to_axi4.scala 160:124]
node _T_105 = eq(_T_104, UInt<1>("h00")) @[ahb_to_axi4.scala 161:95] node _T_105 = eq(_T_104, UInt<1>("h00")) @[ahb_to_axi4.scala 160:95]
node _T_106 = and(_T_99, _T_105) @[ahb_to_axi4.scala 161:93] node _T_106 = and(_T_99, _T_105) @[ahb_to_axi4.scala 160:93]
node _T_107 = or(_T_97, _T_106) @[ahb_to_axi4.scala 160:78] node _T_107 = or(_T_97, _T_106) @[ahb_to_axi4.scala 159:78]
node _T_108 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 162:49] node _T_108 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 161:49]
node _T_109 = eq(_T_108, UInt<1>("h01")) @[ahb_to_axi4.scala 162:55] node _T_109 = eq(_T_108, UInt<1>("h01")) @[ahb_to_axi4.scala 161:55]
node _T_110 = bits(ahb_haddr_q, 0, 0) @[ahb_to_axi4.scala 162:77] node _T_110 = bits(ahb_haddr_q, 0, 0) @[ahb_to_axi4.scala 161:77]
node _T_111 = and(_T_109, _T_110) @[ahb_to_axi4.scala 162:64] node _T_111 = and(_T_109, _T_110) @[ahb_to_axi4.scala 161:64]
node _T_112 = or(_T_107, _T_111) @[ahb_to_axi4.scala 161:155] node _T_112 = or(_T_107, _T_111) @[ahb_to_axi4.scala 160:155]
node _T_113 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 163:49] node _T_113 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 162:49]
node _T_114 = eq(_T_113, UInt<2>("h02")) @[ahb_to_axi4.scala 163:55] node _T_114 = eq(_T_113, UInt<2>("h02")) @[ahb_to_axi4.scala 162:55]
node _T_115 = bits(ahb_haddr_q, 1, 0) @[ahb_to_axi4.scala 163:78] node _T_115 = bits(ahb_haddr_q, 1, 0) @[ahb_to_axi4.scala 162:78]
node _T_116 = orr(_T_115) @[ahb_to_axi4.scala 163:85] node _T_116 = orr(_T_115) @[ahb_to_axi4.scala 162:85]
node _T_117 = and(_T_114, _T_116) @[ahb_to_axi4.scala 163:64] node _T_117 = and(_T_114, _T_116) @[ahb_to_axi4.scala 162:64]
node _T_118 = or(_T_112, _T_117) @[ahb_to_axi4.scala 162:84] node _T_118 = or(_T_112, _T_117) @[ahb_to_axi4.scala 161:84]
node _T_119 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 164:49] node _T_119 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 163:49]
node _T_120 = eq(_T_119, UInt<2>("h03")) @[ahb_to_axi4.scala 164:55] node _T_120 = eq(_T_119, UInt<2>("h03")) @[ahb_to_axi4.scala 163:55]
node _T_121 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 164:78] node _T_121 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 163:78]
node _T_122 = orr(_T_121) @[ahb_to_axi4.scala 164:85] node _T_122 = orr(_T_121) @[ahb_to_axi4.scala 163:85]
node _T_123 = and(_T_120, _T_122) @[ahb_to_axi4.scala 164:64] node _T_123 = and(_T_120, _T_122) @[ahb_to_axi4.scala 163:64]
node _T_124 = or(_T_118, _T_123) @[ahb_to_axi4.scala 163:90] node _T_124 = or(_T_118, _T_123) @[ahb_to_axi4.scala 162:90]
node _T_125 = and(_T_95, _T_124) @[ahb_to_axi4.scala 159:89] node _T_125 = and(_T_95, _T_124) @[ahb_to_axi4.scala 158:89]
node _T_126 = or(_T_125, buf_read_error) @[ahb_to_axi4.scala 164:92] node _T_126 = or(_T_125, buf_read_error) @[ahb_to_axi4.scala 163:92]
node _T_127 = eq(ahb_hready_q, UInt<1>("h00")) @[ahb_to_axi4.scala 166:51] node _T_127 = eq(ahb_hready_q, UInt<1>("h00")) @[ahb_to_axi4.scala 165:51]
node _T_128 = and(ahb_hresp_q, _T_127) @[ahb_to_axi4.scala 166:49] node _T_128 = and(ahb_hresp_q, _T_127) @[ahb_to_axi4.scala 165:49]
node _T_129 = or(_T_126, _T_128) @[ahb_to_axi4.scala 165:51] node _T_129 = or(_T_126, _T_128) @[ahb_to_axi4.scala 164:51]
io.ahb_hresp <= _T_129 @[ahb_to_axi4.scala 159:33] io.ahb_hresp <= _T_129 @[ahb_to_axi4.scala 158:33]
reg _T_130 : UInt, buf_rdata_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 169:68] reg _T_130 : UInt, buf_rdata_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 168:68]
_T_130 <= io.axi_rdata @[ahb_to_axi4.scala 169:68] _T_130 <= io.axi_rdata @[ahb_to_axi4.scala 168:68]
buf_rdata <= _T_130 @[ahb_to_axi4.scala 169:33] buf_rdata <= _T_130 @[ahb_to_axi4.scala 168:33]
reg _T_131 : UInt<1>, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 170:62] reg _T_131 : UInt<1>, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 169:62]
_T_131 <= buf_read_error_in @[ahb_to_axi4.scala 170:62] _T_131 <= buf_read_error_in @[ahb_to_axi4.scala 169:62]
buf_read_error <= _T_131 @[ahb_to_axi4.scala 170:33] buf_read_error <= _T_131 @[ahb_to_axi4.scala 169:33]
reg _T_132 : UInt<1>, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 173:62] reg _T_132 : UInt<1>, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 172:62]
_T_132 <= io.ahb_hresp @[ahb_to_axi4.scala 173:62] _T_132 <= io.ahb_hresp @[ahb_to_axi4.scala 172:62]
ahb_hresp_q <= _T_132 @[ahb_to_axi4.scala 173:33] ahb_hresp_q <= _T_132 @[ahb_to_axi4.scala 172:33]
reg _T_133 : UInt<1>, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 174:62] reg _T_133 : UInt<1>, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 173:62]
_T_133 <= ahb_hready @[ahb_to_axi4.scala 174:62] _T_133 <= ahb_hready @[ahb_to_axi4.scala 173:62]
ahb_hready_q <= _T_133 @[ahb_to_axi4.scala 174:33] ahb_hready_q <= _T_133 @[ahb_to_axi4.scala 173:33]
reg _T_134 : UInt, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 175:62] reg _T_134 : UInt, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 174:62]
_T_134 <= ahb_htrans_in @[ahb_to_axi4.scala 175:62] _T_134 <= ahb_htrans_in @[ahb_to_axi4.scala 174:62]
ahb_htrans_q <= _T_134 @[ahb_to_axi4.scala 175:33] ahb_htrans_q <= _T_134 @[ahb_to_axi4.scala 174:33]
reg _T_135 : UInt, ahb_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 176:67] reg _T_135 : UInt, ahb_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 175:67]
_T_135 <= io.ahb_hsize @[ahb_to_axi4.scala 176:67] _T_135 <= io.ahb_hsize @[ahb_to_axi4.scala 175:67]
ahb_hsize_q <= _T_135 @[ahb_to_axi4.scala 176:33] ahb_hsize_q <= _T_135 @[ahb_to_axi4.scala 175:33]
reg _T_136 : UInt<1>, ahb_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 177:67] reg _T_136 : UInt<1>, ahb_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 176:67]
_T_136 <= io.ahb_hwrite @[ahb_to_axi4.scala 177:67] _T_136 <= io.ahb_hwrite @[ahb_to_axi4.scala 176:67]
ahb_hwrite_q <= _T_136 @[ahb_to_axi4.scala 177:33] ahb_hwrite_q <= _T_136 @[ahb_to_axi4.scala 176:33]
reg _T_137 : UInt, ahb_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 178:67] reg _T_137 : UInt, ahb_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 177:67]
_T_137 <= io.ahb_haddr @[ahb_to_axi4.scala 178:67] _T_137 <= io.ahb_haddr @[ahb_to_axi4.scala 177:67]
ahb_haddr_q <= _T_137 @[ahb_to_axi4.scala 178:33] ahb_haddr_q <= _T_137 @[ahb_to_axi4.scala 177:33]
node _T_138 = bits(io.ahb_htrans, 1, 1) @[ahb_to_axi4.scala 181:79] node _T_138 = bits(io.ahb_htrans, 1, 1) @[ahb_to_axi4.scala 180:79]
node _T_139 = and(ahb_hready, _T_138) @[ahb_to_axi4.scala 181:64] node _T_139 = and(ahb_hready, _T_138) @[ahb_to_axi4.scala 180:64]
node _T_140 = and(io.bus_clk_en, _T_139) @[ahb_to_axi4.scala 181:50] node _T_140 = and(io.bus_clk_en, _T_139) @[ahb_to_axi4.scala 180:50]
ahb_bus_addr_clk_en <= _T_140 @[ahb_to_axi4.scala 181:33] ahb_bus_addr_clk_en <= _T_140 @[ahb_to_axi4.scala 180:33]
node _T_141 = and(io.bus_clk_en, buf_rdata_en) @[ahb_to_axi4.scala 182:50] node _T_141 = and(io.bus_clk_en, buf_rdata_en) @[ahb_to_axi4.scala 181:50]
buf_rdata_clk_en <= _T_141 @[ahb_to_axi4.scala 182:33] buf_rdata_clk_en <= _T_141 @[ahb_to_axi4.scala 181:33]
inst rvclkhdr of rvclkhdr @[el2_lib.scala 483:22] inst rvclkhdr of rvclkhdr @[el2_lib.scala 483:22]
rvclkhdr.clock <= clock rvclkhdr.clock <= clock
rvclkhdr.reset <= reset rvclkhdr.reset <= reset
rvclkhdr.io.clk <= clock @[el2_lib.scala 484:17] rvclkhdr.io.clk <= clock @[el2_lib.scala 484:17]
rvclkhdr.io.en <= io.bus_clk_en @[el2_lib.scala 485:16] rvclkhdr.io.en <= io.bus_clk_en @[el2_lib.scala 485:16]
rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23]
ahb_clk <= rvclkhdr.io.l1clk @[ahb_to_axi4.scala 184:33] ahb_clk <= rvclkhdr.io.l1clk @[ahb_to_axi4.scala 183:33]
inst rvclkhdr_1 of rvclkhdr_1 @[el2_lib.scala 483:22] inst rvclkhdr_1 of rvclkhdr_1 @[el2_lib.scala 483:22]
rvclkhdr_1.clock <= clock rvclkhdr_1.clock <= clock
rvclkhdr_1.reset <= reset rvclkhdr_1.reset <= reset
rvclkhdr_1.io.clk <= clock @[el2_lib.scala 484:17] rvclkhdr_1.io.clk <= clock @[el2_lib.scala 484:17]
rvclkhdr_1.io.en <= ahb_bus_addr_clk_en @[el2_lib.scala 485:16] rvclkhdr_1.io.en <= ahb_bus_addr_clk_en @[el2_lib.scala 485:16]
rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23]
ahb_addr_clk <= rvclkhdr_1.io.l1clk @[ahb_to_axi4.scala 185:33] ahb_addr_clk <= rvclkhdr_1.io.l1clk @[ahb_to_axi4.scala 184:33]
inst rvclkhdr_2 of rvclkhdr_2 @[el2_lib.scala 483:22] inst rvclkhdr_2 of rvclkhdr_2 @[el2_lib.scala 483:22]
rvclkhdr_2.clock <= clock rvclkhdr_2.clock <= clock
rvclkhdr_2.reset <= reset rvclkhdr_2.reset <= reset
rvclkhdr_2.io.clk <= clock @[el2_lib.scala 484:17] rvclkhdr_2.io.clk <= clock @[el2_lib.scala 484:17]
rvclkhdr_2.io.en <= buf_rdata_clk_en @[el2_lib.scala 485:16] rvclkhdr_2.io.en <= buf_rdata_clk_en @[el2_lib.scala 485:16]
rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23]
buf_rdata_clk <= rvclkhdr_2.io.l1clk @[ahb_to_axi4.scala 186:33] buf_rdata_clk <= rvclkhdr_2.io.l1clk @[ahb_to_axi4.scala 185:33]
node _T_142 = and(io.axi_awvalid, io.axi_awready) @[ahb_to_axi4.scala 188:54] node _T_142 = and(io.axi_awvalid, io.axi_awready) @[ahb_to_axi4.scala 187:54]
node _T_143 = and(io.axi_arvalid, io.axi_arready) @[ahb_to_axi4.scala 188:90] node _T_143 = and(io.axi_arvalid, io.axi_arready) @[ahb_to_axi4.scala 187:90]
node _T_144 = or(_T_142, _T_143) @[ahb_to_axi4.scala 188:72] node _T_144 = or(_T_142, _T_143) @[ahb_to_axi4.scala 187:72]
node _T_145 = eq(cmdbuf_wr_en, UInt<1>("h00")) @[ahb_to_axi4.scala 188:111] node _T_145 = eq(cmdbuf_wr_en, UInt<1>("h00")) @[ahb_to_axi4.scala 187:111]
node _T_146 = and(_T_144, _T_145) @[ahb_to_axi4.scala 188:109] node _T_146 = and(_T_144, _T_145) @[ahb_to_axi4.scala 187:109]
node _T_147 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 188:144] node _T_147 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 187:144]
node _T_148 = and(io.ahb_hresp, _T_147) @[ahb_to_axi4.scala 188:142] node _T_148 = and(io.ahb_hresp, _T_147) @[ahb_to_axi4.scala 187:142]
node _T_149 = or(_T_146, _T_148) @[ahb_to_axi4.scala 188:126] node _T_149 = or(_T_146, _T_148) @[ahb_to_axi4.scala 187:126]
cmdbuf_rst <= _T_149 @[ahb_to_axi4.scala 188:33] cmdbuf_rst <= _T_149 @[ahb_to_axi4.scala 187:33]
node _T_150 = and(io.axi_awvalid, io.axi_awready) @[ahb_to_axi4.scala 189:68] node _T_150 = and(io.axi_awvalid, io.axi_awready) @[ahb_to_axi4.scala 188:68]
node _T_151 = and(io.axi_arvalid, io.axi_arready) @[ahb_to_axi4.scala 189:104] node _T_151 = and(io.axi_arvalid, io.axi_arready) @[ahb_to_axi4.scala 188:104]
node _T_152 = or(_T_150, _T_151) @[ahb_to_axi4.scala 189:86] node _T_152 = or(_T_150, _T_151) @[ahb_to_axi4.scala 188:86]
node _T_153 = eq(_T_152, UInt<1>("h00")) @[ahb_to_axi4.scala 189:50] node _T_153 = eq(_T_152, UInt<1>("h00")) @[ahb_to_axi4.scala 188:50]
node _T_154 = and(cmdbuf_vld, _T_153) @[ahb_to_axi4.scala 189:48] node _T_154 = and(cmdbuf_vld, _T_153) @[ahb_to_axi4.scala 188:48]
cmdbuf_full <= _T_154 @[ahb_to_axi4.scala 189:33] cmdbuf_full <= _T_154 @[ahb_to_axi4.scala 188:33]
node _T_155 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 191:88] node _T_155 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 190:88]
node _T_156 = mux(_T_155, UInt<1>("h01"), cmdbuf_vld) @[ahb_to_axi4.scala 191:68] node _T_156 = mux(_T_155, UInt<1>("h01"), cmdbuf_vld) @[ahb_to_axi4.scala 190:68]
node _T_157 = eq(cmdbuf_rst, UInt<1>("h00")) @[ahb_to_axi4.scala 191:112] node _T_157 = eq(cmdbuf_rst, UInt<1>("h00")) @[ahb_to_axi4.scala 190:112]
node _T_158 = and(_T_156, _T_157) @[ahb_to_axi4.scala 191:110] node _T_158 = and(_T_156, _T_157) @[ahb_to_axi4.scala 190:110]
reg _T_159 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 191:63] reg _T_159 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 190:63]
_T_159 <= _T_158 @[ahb_to_axi4.scala 191:63] _T_159 <= _T_158 @[ahb_to_axi4.scala 190:63]
cmdbuf_vld <= _T_159 @[ahb_to_axi4.scala 191:33] cmdbuf_vld <= _T_159 @[ahb_to_axi4.scala 190:33]
node _T_160 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 195:57] node _T_160 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 194:57]
reg _T_161 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] reg _T_161 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_160 : @[Reg.scala 28:19] when _T_160 : @[Reg.scala 28:19]
_T_161 <= ahb_hwrite_q @[Reg.scala 28:23] _T_161 <= ahb_hwrite_q @[Reg.scala 28:23]
skip @[Reg.scala 28:19] skip @[Reg.scala 28:19]
cmdbuf_write <= _T_161 @[ahb_to_axi4.scala 194:33] cmdbuf_write <= _T_161 @[ahb_to_axi4.scala 193:33]
node _T_162 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 198:56] node _T_162 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 197:56]
reg _T_163 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] reg _T_163 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_162 : @[Reg.scala 28:19] when _T_162 : @[Reg.scala 28:19]
_T_163 <= ahb_hsize_q @[Reg.scala 28:23] _T_163 <= ahb_hsize_q @[Reg.scala 28:23]
skip @[Reg.scala 28:19] skip @[Reg.scala 28:19]
cmdbuf_size <= _T_163 @[ahb_to_axi4.scala 197:33] cmdbuf_size <= _T_163 @[ahb_to_axi4.scala 196:33]
node _T_164 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 201:57] node _T_164 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 200:57]
reg _T_165 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] reg _T_165 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_164 : @[Reg.scala 28:19] when _T_164 : @[Reg.scala 28:19]
_T_165 <= master_wstrb @[Reg.scala 28:23] _T_165 <= master_wstrb @[Reg.scala 28:23]
skip @[Reg.scala 28:19] skip @[Reg.scala 28:19]
cmdbuf_wstrb <= _T_165 @[ahb_to_axi4.scala 200:33] cmdbuf_wstrb <= _T_165 @[ahb_to_axi4.scala 199:33]
node _T_166 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 204:59] node _T_166 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 203:59]
inst rvclkhdr_3 of rvclkhdr_3 @[el2_lib.scala 508:23] inst rvclkhdr_3 of rvclkhdr_3 @[el2_lib.scala 508:23]
rvclkhdr_3.clock <= clock rvclkhdr_3.clock <= clock
rvclkhdr_3.reset <= reset rvclkhdr_3.reset <= reset
@ -489,8 +483,8 @@ circuit ahb_to_axi4 :
rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
reg _T_167 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] reg _T_167 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
_T_167 <= ahb_haddr_q @[el2_lib.scala 514:16] _T_167 <= ahb_haddr_q @[el2_lib.scala 514:16]
cmdbuf_addr <= _T_167 @[ahb_to_axi4.scala 204:17] cmdbuf_addr <= _T_167 @[ahb_to_axi4.scala 203:17]
node _T_168 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 205:62] node _T_168 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 204:62]
inst rvclkhdr_4 of rvclkhdr_4 @[el2_lib.scala 508:23] inst rvclkhdr_4 of rvclkhdr_4 @[el2_lib.scala 508:23]
rvclkhdr_4.clock <= clock rvclkhdr_4.clock <= clock
rvclkhdr_4.reset <= reset rvclkhdr_4.reset <= reset
@ -499,44 +493,44 @@ circuit ahb_to_axi4 :
rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
reg _T_169 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] reg _T_169 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
_T_169 <= io.ahb_hwdata @[el2_lib.scala 514:16] _T_169 <= io.ahb_hwdata @[el2_lib.scala 514:16]
cmdbuf_wdata <= _T_169 @[ahb_to_axi4.scala 205:18] cmdbuf_wdata <= _T_169 @[ahb_to_axi4.scala 204:18]
node _T_170 = and(cmdbuf_vld, cmdbuf_write) @[ahb_to_axi4.scala 208:43] node _T_170 = and(cmdbuf_vld, cmdbuf_write) @[ahb_to_axi4.scala 207:43]
io.axi_awvalid <= _T_170 @[ahb_to_axi4.scala 208:29] io.axi_awvalid <= _T_170 @[ahb_to_axi4.scala 207:29]
io.axi_awid <= UInt<1>("h00") @[ahb_to_axi4.scala 209:29] io.axi_awid <= UInt<1>("h00") @[ahb_to_axi4.scala 208:29]
io.axi_awaddr <= cmdbuf_addr @[ahb_to_axi4.scala 210:29] io.axi_awaddr <= cmdbuf_addr @[ahb_to_axi4.scala 209:29]
node _T_171 = bits(cmdbuf_size, 1, 0) @[ahb_to_axi4.scala 211:55] node _T_171 = bits(cmdbuf_size, 1, 0) @[ahb_to_axi4.scala 210:55]
node _T_172 = cat(UInt<1>("h00"), _T_171) @[Cat.scala 29:58] node _T_172 = cat(UInt<1>("h00"), _T_171) @[Cat.scala 29:58]
io.axi_awsize <= _T_172 @[ahb_to_axi4.scala 211:29] io.axi_awsize <= _T_172 @[ahb_to_axi4.scala 210:29]
node _T_173 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] node _T_173 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
io.axi_awprot <= _T_173 @[ahb_to_axi4.scala 212:29] io.axi_awprot <= _T_173 @[ahb_to_axi4.scala 211:29]
node _T_174 = mux(UInt<1>("h00"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] node _T_174 = mux(UInt<1>("h00"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
io.axi_awlen <= _T_174 @[ahb_to_axi4.scala 213:29] io.axi_awlen <= _T_174 @[ahb_to_axi4.scala 212:29]
io.axi_awburst <= UInt<1>("h01") @[ahb_to_axi4.scala 214:29] io.axi_awburst <= UInt<1>("h01") @[ahb_to_axi4.scala 213:29]
node _T_175 = and(cmdbuf_vld, cmdbuf_write) @[ahb_to_axi4.scala 216:43] node _T_175 = and(cmdbuf_vld, cmdbuf_write) @[ahb_to_axi4.scala 215:43]
io.axi_wvalid <= _T_175 @[ahb_to_axi4.scala 216:29] io.axi_wvalid <= _T_175 @[ahb_to_axi4.scala 215:29]
io.axi_wdata <= cmdbuf_wdata @[ahb_to_axi4.scala 217:29] io.axi_wdata <= cmdbuf_wdata @[ahb_to_axi4.scala 216:29]
io.axi_wstrb <= cmdbuf_wstrb @[ahb_to_axi4.scala 218:29] io.axi_wstrb <= cmdbuf_wstrb @[ahb_to_axi4.scala 217:29]
io.axi_wlast <= UInt<1>("h01") @[ahb_to_axi4.scala 219:29] io.axi_wlast <= UInt<1>("h01") @[ahb_to_axi4.scala 218:29]
io.axi_bready <= UInt<1>("h01") @[ahb_to_axi4.scala 221:29] io.axi_bready <= UInt<1>("h01") @[ahb_to_axi4.scala 220:29]
node _T_176 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 223:45] node _T_176 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 222:45]
node _T_177 = and(cmdbuf_vld, _T_176) @[ahb_to_axi4.scala 223:43] node _T_177 = and(cmdbuf_vld, _T_176) @[ahb_to_axi4.scala 222:43]
io.axi_arvalid <= _T_177 @[ahb_to_axi4.scala 223:29] io.axi_arvalid <= _T_177 @[ahb_to_axi4.scala 222:29]
io.axi_arid <= UInt<1>("h00") @[ahb_to_axi4.scala 224:29] io.axi_arid <= UInt<1>("h00") @[ahb_to_axi4.scala 223:29]
io.axi_araddr <= cmdbuf_addr @[ahb_to_axi4.scala 225:29] io.axi_araddr <= cmdbuf_addr @[ahb_to_axi4.scala 224:29]
node _T_178 = bits(cmdbuf_size, 1, 0) @[ahb_to_axi4.scala 226:55] node _T_178 = bits(cmdbuf_size, 1, 0) @[ahb_to_axi4.scala 225:55]
node _T_179 = cat(UInt<1>("h00"), _T_178) @[Cat.scala 29:58] node _T_179 = cat(UInt<1>("h00"), _T_178) @[Cat.scala 29:58]
io.axi_arsize <= _T_179 @[ahb_to_axi4.scala 226:29] io.axi_arsize <= _T_179 @[ahb_to_axi4.scala 225:29]
node _T_180 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] node _T_180 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
io.axi_arprot <= _T_180 @[ahb_to_axi4.scala 227:29] io.axi_arprot <= _T_180 @[ahb_to_axi4.scala 226:29]
node _T_181 = mux(UInt<1>("h00"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] node _T_181 = mux(UInt<1>("h00"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
io.axi_arlen <= _T_181 @[ahb_to_axi4.scala 228:29] io.axi_arlen <= _T_181 @[ahb_to_axi4.scala 227:29]
io.axi_arburst <= UInt<1>("h01") @[ahb_to_axi4.scala 229:29] io.axi_arburst <= UInt<1>("h01") @[ahb_to_axi4.scala 228:29]
io.axi_rready <= UInt<1>("h01") @[ahb_to_axi4.scala 231:29] io.axi_rready <= UInt<1>("h01") @[ahb_to_axi4.scala 230:29]
inst rvclkhdr_5 of rvclkhdr_5 @[el2_lib.scala 483:22] inst rvclkhdr_5 of rvclkhdr_5 @[el2_lib.scala 483:22]
rvclkhdr_5.clock <= clock rvclkhdr_5.clock <= clock
rvclkhdr_5.reset <= reset rvclkhdr_5.reset <= reset
rvclkhdr_5.io.clk <= clock @[el2_lib.scala 484:17] rvclkhdr_5.io.clk <= clock @[el2_lib.scala 484:17]
rvclkhdr_5.io.en <= io.bus_clk_en @[el2_lib.scala 485:16] rvclkhdr_5.io.en <= io.bus_clk_en @[el2_lib.scala 485:16]
rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23]
bus_clk <= rvclkhdr_5.io.l1clk @[ahb_to_axi4.scala 234:29] bus_clk <= rvclkhdr_5.io.l1clk @[ahb_to_axi4.scala 233:29]

239
ahb_to_axi4.v
View File

@ -106,47 +106,48 @@ module ahb_to_axi4(
wire rvclkhdr_5_io_clk; // @[el2_lib.scala 483:22] wire rvclkhdr_5_io_clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_5_io_en; // @[el2_lib.scala 483:22] wire rvclkhdr_5_io_en; // @[el2_lib.scala 483:22]
wire rvclkhdr_5_io_scan_mode; // @[el2_lib.scala 483:22] wire rvclkhdr_5_io_scan_mode; // @[el2_lib.scala 483:22]
wire ahb_addr_clk = rvclkhdr_1_io_l1clk; // @[ahb_to_axi4.scala 85:35 ahb_to_axi4.scala 185:33] wire ahb_addr_clk = rvclkhdr_1_io_l1clk; // @[ahb_to_axi4.scala 85:35 ahb_to_axi4.scala 184:33]
reg [31:0] ahb_haddr_q; // @[ahb_to_axi4.scala 178:67] reg [31:0] ahb_haddr_q; // @[ahb_to_axi4.scala 177:67]
wire ahb_addr_in_dccm = ahb_haddr_q[31:16] == 16'hf004; // @[el2_lib.scala 501:39] wire ahb_addr_in_dccm = ahb_haddr_q[31:16] == 16'hf004; // @[el2_lib.scala 227:29]
wire ahb_clk = rvclkhdr_io_l1clk; // @[ahb_to_axi4.scala 84:35 ahb_to_axi4.scala 184:33] wire ahb_addr_in_iccm = ahb_haddr_q[31:16] == 16'hee00; // @[el2_lib.scala 227:29]
wire ahb_clk = rvclkhdr_io_l1clk; // @[ahb_to_axi4.scala 84:35 ahb_to_axi4.scala 183:33]
reg [1:0] buf_state; // @[Reg.scala 27:20] reg [1:0] buf_state; // @[Reg.scala 27:20]
wire _T_6 = 2'h0 == buf_state; // @[Conditional.scala 37:30] wire _T_6 = 2'h0 == buf_state; // @[Conditional.scala 37:30]
wire ahb_hready = io_ahb_hreadyout & io_ahb_hreadyin; // @[ahb_to_axi4.scala 156:53] wire ahb_hready = io_ahb_hreadyout & io_ahb_hreadyin; // @[ahb_to_axi4.scala 155:53]
wire _T_9 = ahb_hready & io_ahb_htrans[1]; // @[ahb_to_axi4.scala 128:36] wire _T_9 = ahb_hready & io_ahb_htrans[1]; // @[ahb_to_axi4.scala 127:36]
wire _T_10 = _T_9 & io_ahb_hsel; // @[ahb_to_axi4.scala 128:55] wire _T_10 = _T_9 & io_ahb_hsel; // @[ahb_to_axi4.scala 127:55]
wire _T_11 = 2'h1 == buf_state; // @[Conditional.scala 37:30] wire _T_11 = 2'h1 == buf_state; // @[Conditional.scala 37:30]
wire _T_13 = io_ahb_htrans == 2'h0; // @[ahb_to_axi4.scala 131:66] wire _T_13 = io_ahb_htrans == 2'h0; // @[ahb_to_axi4.scala 130:66]
wire _T_14 = io_ahb_hresp | _T_13; // @[ahb_to_axi4.scala 131:43] wire _T_14 = io_ahb_hresp | _T_13; // @[ahb_to_axi4.scala 130:43]
wire _T_15 = ~io_ahb_hsel; // @[ahb_to_axi4.scala 131:80] wire _T_15 = ~io_ahb_hsel; // @[ahb_to_axi4.scala 130:80]
wire _T_16 = _T_14 | _T_15; // @[ahb_to_axi4.scala 131:78] wire _T_16 = _T_14 | _T_15; // @[ahb_to_axi4.scala 130:78]
wire bus_clk = rvclkhdr_5_io_l1clk; // @[ahb_to_axi4.scala 98:35 ahb_to_axi4.scala 234:29] wire bus_clk = rvclkhdr_5_io_l1clk; // @[ahb_to_axi4.scala 98:35 ahb_to_axi4.scala 233:29]
reg cmdbuf_vld; // @[ahb_to_axi4.scala 191:63] reg cmdbuf_vld; // @[ahb_to_axi4.scala 190:63]
wire _T_150 = io_axi_awvalid & io_axi_awready; // @[ahb_to_axi4.scala 189:68] wire _T_150 = io_axi_awvalid & io_axi_awready; // @[ahb_to_axi4.scala 188:68]
wire _T_151 = io_axi_arvalid & io_axi_arready; // @[ahb_to_axi4.scala 189:104] wire _T_151 = io_axi_arvalid & io_axi_arready; // @[ahb_to_axi4.scala 188:104]
wire _T_152 = _T_150 | _T_151; // @[ahb_to_axi4.scala 189:86] wire _T_152 = _T_150 | _T_151; // @[ahb_to_axi4.scala 188:86]
wire _T_153 = ~_T_152; // @[ahb_to_axi4.scala 189:50] wire _T_153 = ~_T_152; // @[ahb_to_axi4.scala 188:50]
wire cmdbuf_full = cmdbuf_vld & _T_153; // @[ahb_to_axi4.scala 189:48] wire cmdbuf_full = cmdbuf_vld & _T_153; // @[ahb_to_axi4.scala 188:48]
wire _T_20 = ~cmdbuf_full; // @[ahb_to_axi4.scala 132:26] wire _T_20 = ~cmdbuf_full; // @[ahb_to_axi4.scala 131:26]
wire _T_21 = _T_20 | io_ahb_hresp; // @[ahb_to_axi4.scala 132:39] wire _T_21 = _T_20 | io_ahb_hresp; // @[ahb_to_axi4.scala 131:39]
wire _T_24 = io_ahb_htrans == 2'h1; // @[ahb_to_axi4.scala 133:79] wire _T_24 = io_ahb_htrans == 2'h1; // @[ahb_to_axi4.scala 132:79]
wire _T_25 = _T_24 & io_ahb_hsel; // @[ahb_to_axi4.scala 133:97] wire _T_25 = _T_24 & io_ahb_hsel; // @[ahb_to_axi4.scala 132:97]
wire _T_26 = io_ahb_hresp | _T_25; // @[ahb_to_axi4.scala 133:55] wire _T_26 = io_ahb_hresp | _T_25; // @[ahb_to_axi4.scala 132:55]
wire _T_27 = ~_T_26; // @[ahb_to_axi4.scala 133:40] wire _T_27 = ~_T_26; // @[ahb_to_axi4.scala 132:40]
wire _T_28 = _T_20 & _T_27; // @[ahb_to_axi4.scala 133:38] wire _T_28 = _T_20 & _T_27; // @[ahb_to_axi4.scala 132:38]
wire _T_29 = 2'h2 == buf_state; // @[Conditional.scala 37:30] wire _T_29 = 2'h2 == buf_state; // @[Conditional.scala 37:30]
wire _T_33 = ~io_ahb_hresp; // @[ahb_to_axi4.scala 138:25] wire _T_33 = ~io_ahb_hresp; // @[ahb_to_axi4.scala 137:25]
wire _T_35 = _T_33 & _T_20; // @[ahb_to_axi4.scala 138:39] wire _T_35 = _T_33 & _T_20; // @[ahb_to_axi4.scala 137:39]
wire _T_36 = 2'h3 == buf_state; // @[Conditional.scala 37:30] wire _T_36 = 2'h3 == buf_state; // @[Conditional.scala 37:30]
reg cmdbuf_write; // @[Reg.scala 27:20] reg cmdbuf_write; // @[Reg.scala 27:20]
wire _T_37 = ~cmdbuf_write; // @[ahb_to_axi4.scala 142:41] wire _T_37 = ~cmdbuf_write; // @[ahb_to_axi4.scala 141:41]
wire _T_38 = io_axi_rvalid & _T_37; // @[ahb_to_axi4.scala 142:39] wire _T_38 = io_axi_rvalid & _T_37; // @[ahb_to_axi4.scala 141:39]
wire _T_40 = |io_axi_rresp; // @[ahb_to_axi4.scala 144:64] wire _T_40 = |io_axi_rresp; // @[ahb_to_axi4.scala 143:64]
wire _GEN_1 = _T_36 & _T_38; // @[Conditional.scala 39:67] wire _GEN_1 = _T_36 & _T_38; // @[Conditional.scala 39:67]
wire _GEN_5 = _T_29 ? _T_21 : _GEN_1; // @[Conditional.scala 39:67] wire _GEN_5 = _T_29 ? _T_21 : _GEN_1; // @[Conditional.scala 39:67]
wire _GEN_10 = _T_11 ? _T_21 : _GEN_5; // @[Conditional.scala 39:67] wire _GEN_10 = _T_11 ? _T_21 : _GEN_5; // @[Conditional.scala 39:67]
wire buf_state_en = _T_6 ? _T_10 : _GEN_10; // @[Conditional.scala 40:58] wire buf_state_en = _T_6 ? _T_10 : _GEN_10; // @[Conditional.scala 40:58]
wire _T_41 = buf_state_en & _T_40; // @[ahb_to_axi4.scala 144:43] wire _T_41 = buf_state_en & _T_40; // @[ahb_to_axi4.scala 143:43]
wire _GEN_2 = _T_36 & buf_state_en; // @[Conditional.scala 39:67] wire _GEN_2 = _T_36 & buf_state_en; // @[Conditional.scala 39:67]
wire _GEN_3 = _T_36 & _T_41; // @[Conditional.scala 39:67] wire _GEN_3 = _T_36 & _T_41; // @[Conditional.scala 39:67]
wire _GEN_6 = _T_29 & _T_35; // @[Conditional.scala 39:67] wire _GEN_6 = _T_29 & _T_35; // @[Conditional.scala 39:67]
@ -155,81 +156,83 @@ module ahb_to_axi4(
wire _GEN_12 = _T_11 ? 1'h0 : _GEN_7; // @[Conditional.scala 39:67] wire _GEN_12 = _T_11 ? 1'h0 : _GEN_7; // @[Conditional.scala 39:67]
wire cmdbuf_wr_en = _T_6 ? 1'h0 : _GEN_11; // @[Conditional.scala 40:58] wire cmdbuf_wr_en = _T_6 ? 1'h0 : _GEN_11; // @[Conditional.scala 40:58]
wire buf_rdata_en = _T_6 ? 1'h0 : _GEN_12; // @[Conditional.scala 40:58] wire buf_rdata_en = _T_6 ? 1'h0 : _GEN_12; // @[Conditional.scala 40:58]
reg [2:0] ahb_hsize_q; // @[ahb_to_axi4.scala 176:67] reg [2:0] ahb_hsize_q; // @[ahb_to_axi4.scala 175:67]
wire _T_45 = ahb_hsize_q == 3'h0; // @[ahb_to_axi4.scala 149:62] wire _T_45 = ahb_hsize_q == 3'h0; // @[ahb_to_axi4.scala 148:62]
wire [7:0] _T_47 = _T_45 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] wire [7:0] _T_47 = _T_45 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
wire [7:0] _T_49 = 8'h1 << ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 149:80] wire [7:0] _T_49 = 8'h1 << ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 148:80]
wire [7:0] _T_50 = _T_47 & _T_49; // @[ahb_to_axi4.scala 149:72] wire [7:0] _T_50 = _T_47 & _T_49; // @[ahb_to_axi4.scala 148:72]
wire _T_52 = ahb_hsize_q == 3'h1; // @[ahb_to_axi4.scala 150:62] wire _T_52 = ahb_hsize_q == 3'h1; // @[ahb_to_axi4.scala 149:62]
wire [7:0] _T_54 = _T_52 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] wire [7:0] _T_54 = _T_52 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
wire [8:0] _T_56 = 9'h3 << ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 150:80] wire [8:0] _T_56 = 9'h3 << ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 149:80]
wire [8:0] _GEN_23 = {{1'd0}, _T_54}; // @[ahb_to_axi4.scala 150:72] wire [8:0] _GEN_23 = {{1'd0}, _T_54}; // @[ahb_to_axi4.scala 149:72]
wire [8:0] _T_57 = _GEN_23 & _T_56; // @[ahb_to_axi4.scala 150:72] wire [8:0] _T_57 = _GEN_23 & _T_56; // @[ahb_to_axi4.scala 149:72]
wire [8:0] _GEN_24 = {{1'd0}, _T_50}; // @[ahb_to_axi4.scala 149:111] wire [8:0] _GEN_24 = {{1'd0}, _T_50}; // @[ahb_to_axi4.scala 148:111]
wire [8:0] _T_58 = _GEN_24 | _T_57; // @[ahb_to_axi4.scala 149:111] wire [8:0] _T_58 = _GEN_24 | _T_57; // @[ahb_to_axi4.scala 148:111]
wire _T_60 = ahb_hsize_q == 3'h2; // @[ahb_to_axi4.scala 151:62] wire _T_60 = ahb_hsize_q == 3'h2; // @[ahb_to_axi4.scala 150:62]
wire [7:0] _T_62 = _T_60 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] wire [7:0] _T_62 = _T_60 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
wire [10:0] _T_64 = 11'hf << ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 151:80] wire [10:0] _T_64 = 11'hf << ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 150:80]
wire [10:0] _GEN_25 = {{3'd0}, _T_62}; // @[ahb_to_axi4.scala 151:72] wire [10:0] _GEN_25 = {{3'd0}, _T_62}; // @[ahb_to_axi4.scala 150:72]
wire [10:0] _T_65 = _GEN_25 & _T_64; // @[ahb_to_axi4.scala 151:72] wire [10:0] _T_65 = _GEN_25 & _T_64; // @[ahb_to_axi4.scala 150:72]
wire [10:0] _GEN_26 = {{2'd0}, _T_58}; // @[ahb_to_axi4.scala 150:111] wire [10:0] _GEN_26 = {{2'd0}, _T_58}; // @[ahb_to_axi4.scala 149:111]
wire [10:0] _T_66 = _GEN_26 | _T_65; // @[ahb_to_axi4.scala 150:111] wire [10:0] _T_66 = _GEN_26 | _T_65; // @[ahb_to_axi4.scala 149:111]
wire _T_68 = ahb_hsize_q == 3'h3; // @[ahb_to_axi4.scala 152:62] wire _T_68 = ahb_hsize_q == 3'h3; // @[ahb_to_axi4.scala 151:62]
wire [7:0] _T_70 = _T_68 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] wire [7:0] _T_70 = _T_68 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
wire [10:0] _GEN_27 = {{3'd0}, _T_70}; // @[ahb_to_axi4.scala 151:111] wire [10:0] _GEN_27 = {{3'd0}, _T_70}; // @[ahb_to_axi4.scala 150:111]
wire [10:0] _T_72 = _T_66 | _GEN_27; // @[ahb_to_axi4.scala 151:111] wire [10:0] _T_72 = _T_66 | _GEN_27; // @[ahb_to_axi4.scala 150:111]
reg ahb_hready_q; // @[ahb_to_axi4.scala 174:62] reg ahb_hready_q; // @[ahb_to_axi4.scala 173:62]
wire _T_73 = ~ahb_hready_q; // @[ahb_to_axi4.scala 155:68] wire _T_73 = ~ahb_hready_q; // @[ahb_to_axi4.scala 154:68]
reg ahb_hresp_q; // @[ahb_to_axi4.scala 173:62] reg ahb_hresp_q; // @[ahb_to_axi4.scala 172:62]
wire _T_74 = ahb_hresp_q & _T_73; // @[ahb_to_axi4.scala 155:66] wire _T_74 = ahb_hresp_q & _T_73; // @[ahb_to_axi4.scala 154:66]
wire _T_76 = buf_state == 2'h0; // @[ahb_to_axi4.scala 155:112] wire _T_76 = buf_state == 2'h0; // @[ahb_to_axi4.scala 154:112]
wire _T_77 = _T_20 | _T_76; // @[ahb_to_axi4.scala 155:99] wire _T_77 = _T_20 | _T_76; // @[ahb_to_axi4.scala 154:99]
wire _T_78 = buf_state == 2'h2; // @[ahb_to_axi4.scala 155:137] wire _T_78 = buf_state == 2'h2; // @[ahb_to_axi4.scala 154:137]
wire _T_79 = buf_state == 2'h3; // @[ahb_to_axi4.scala 155:156] wire _T_79 = buf_state == 2'h3; // @[ahb_to_axi4.scala 154:156]
wire _T_80 = _T_78 | _T_79; // @[ahb_to_axi4.scala 155:144] wire _T_80 = _T_78 | _T_79; // @[ahb_to_axi4.scala 154:144]
wire _T_81 = ~_T_80; // @[ahb_to_axi4.scala 155:125] wire _T_81 = ~_T_80; // @[ahb_to_axi4.scala 154:125]
wire _T_82 = _T_77 & _T_81; // @[ahb_to_axi4.scala 155:123] wire _T_82 = _T_77 & _T_81; // @[ahb_to_axi4.scala 154:123]
reg buf_read_error; // @[ahb_to_axi4.scala 170:62] reg buf_read_error; // @[ahb_to_axi4.scala 169:62]
wire _T_83 = ~buf_read_error; // @[ahb_to_axi4.scala 155:169] wire _T_83 = ~buf_read_error; // @[ahb_to_axi4.scala 154:169]
wire _T_84 = _T_82 & _T_83; // @[ahb_to_axi4.scala 155:167] wire _T_84 = _T_82 & _T_83; // @[ahb_to_axi4.scala 154:167]
wire [1:0] _T_88 = io_ahb_hsel ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] wire [1:0] _T_88 = io_ahb_hsel ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire buf_rdata_clk = rvclkhdr_2_io_l1clk; // @[ahb_to_axi4.scala 86:35 ahb_to_axi4.scala 186:33] wire buf_rdata_clk = rvclkhdr_2_io_l1clk; // @[ahb_to_axi4.scala 86:35 ahb_to_axi4.scala 185:33]
reg [63:0] buf_rdata; // @[ahb_to_axi4.scala 169:68] reg [63:0] buf_rdata; // @[ahb_to_axi4.scala 168:68]
reg [1:0] ahb_htrans_q; // @[ahb_to_axi4.scala 175:62] reg [1:0] ahb_htrans_q; // @[ahb_to_axi4.scala 174:62]
wire _T_93 = ahb_htrans_q != 2'h0; // @[ahb_to_axi4.scala 159:56] wire _T_93 = ahb_htrans_q != 2'h0; // @[ahb_to_axi4.scala 158:56]
wire _T_94 = buf_state != 2'h0; // @[ahb_to_axi4.scala 159:78] wire _T_94 = buf_state != 2'h0; // @[ahb_to_axi4.scala 158:78]
wire _T_95 = _T_93 & _T_94; // @[ahb_to_axi4.scala 159:65] wire _T_95 = _T_93 & _T_94; // @[ahb_to_axi4.scala 158:65]
wire _T_97 = ~ahb_addr_in_dccm; // @[ahb_to_axi4.scala 160:38] wire _T_96 = ahb_addr_in_dccm | ahb_addr_in_iccm; // @[ahb_to_axi4.scala 159:57]
reg ahb_hwrite_q; // @[ahb_to_axi4.scala 177:67] wire _T_97 = ~_T_96; // @[ahb_to_axi4.scala 159:38]
wire _T_98 = ahb_addr_in_dccm & ahb_hwrite_q; // @[ahb_to_axi4.scala 161:75] reg ahb_hwrite_q; // @[ahb_to_axi4.scala 176:67]
wire _T_101 = ahb_hsize_q[1:0] == 2'h2; // @[ahb_to_axi4.scala 161:115] wire _T_98 = ahb_addr_in_dccm & ahb_hwrite_q; // @[ahb_to_axi4.scala 160:75]
wire _T_103 = ahb_hsize_q[1:0] == 2'h3; // @[ahb_to_axi4.scala 161:144] wire _T_99 = ahb_addr_in_iccm | _T_98; // @[ahb_to_axi4.scala 160:55]
wire _T_104 = _T_101 | _T_103; // @[ahb_to_axi4.scala 161:124] wire _T_101 = ahb_hsize_q[1:0] == 2'h2; // @[ahb_to_axi4.scala 160:115]
wire _T_105 = ~_T_104; // @[ahb_to_axi4.scala 161:95] wire _T_103 = ahb_hsize_q[1:0] == 2'h3; // @[ahb_to_axi4.scala 160:144]
wire _T_106 = _T_98 & _T_105; // @[ahb_to_axi4.scala 161:93] wire _T_104 = _T_101 | _T_103; // @[ahb_to_axi4.scala 160:124]
wire _T_107 = _T_97 | _T_106; // @[ahb_to_axi4.scala 160:78] wire _T_105 = ~_T_104; // @[ahb_to_axi4.scala 160:95]
wire _T_111 = _T_52 & ahb_haddr_q[0]; // @[ahb_to_axi4.scala 162:64] wire _T_106 = _T_99 & _T_105; // @[ahb_to_axi4.scala 160:93]
wire _T_112 = _T_107 | _T_111; // @[ahb_to_axi4.scala 161:155] wire _T_107 = _T_97 | _T_106; // @[ahb_to_axi4.scala 159:78]
wire _T_116 = |ahb_haddr_q[1:0]; // @[ahb_to_axi4.scala 163:85] wire _T_111 = _T_52 & ahb_haddr_q[0]; // @[ahb_to_axi4.scala 161:64]
wire _T_117 = _T_60 & _T_116; // @[ahb_to_axi4.scala 163:64] wire _T_112 = _T_107 | _T_111; // @[ahb_to_axi4.scala 160:155]
wire _T_118 = _T_112 | _T_117; // @[ahb_to_axi4.scala 162:84] wire _T_116 = |ahb_haddr_q[1:0]; // @[ahb_to_axi4.scala 162:85]
wire _T_122 = |ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 164:85] wire _T_117 = _T_60 & _T_116; // @[ahb_to_axi4.scala 162:64]
wire _T_123 = _T_68 & _T_122; // @[ahb_to_axi4.scala 164:64] wire _T_118 = _T_112 | _T_117; // @[ahb_to_axi4.scala 161:84]
wire _T_124 = _T_118 | _T_123; // @[ahb_to_axi4.scala 163:90] wire _T_122 = |ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 163:85]
wire _T_125 = _T_95 & _T_124; // @[ahb_to_axi4.scala 159:89] wire _T_123 = _T_68 & _T_122; // @[ahb_to_axi4.scala 163:64]
wire _T_126 = _T_125 | buf_read_error; // @[ahb_to_axi4.scala 164:92] wire _T_124 = _T_118 | _T_123; // @[ahb_to_axi4.scala 162:90]
wire _T_145 = ~cmdbuf_wr_en; // @[ahb_to_axi4.scala 188:111] wire _T_125 = _T_95 & _T_124; // @[ahb_to_axi4.scala 158:89]
wire _T_146 = _T_152 & _T_145; // @[ahb_to_axi4.scala 188:109] wire _T_126 = _T_125 | buf_read_error; // @[ahb_to_axi4.scala 163:92]
wire _T_148 = io_ahb_hresp & _T_37; // @[ahb_to_axi4.scala 188:142] wire _T_145 = ~cmdbuf_wr_en; // @[ahb_to_axi4.scala 187:111]
wire cmdbuf_rst = _T_146 | _T_148; // @[ahb_to_axi4.scala 188:126] wire _T_146 = _T_152 & _T_145; // @[ahb_to_axi4.scala 187:109]
wire _T_156 = cmdbuf_wr_en | cmdbuf_vld; // @[ahb_to_axi4.scala 191:68] wire _T_148 = io_ahb_hresp & _T_37; // @[ahb_to_axi4.scala 187:142]
wire _T_157 = ~cmdbuf_rst; // @[ahb_to_axi4.scala 191:112] wire cmdbuf_rst = _T_146 | _T_148; // @[ahb_to_axi4.scala 187:126]
wire _T_156 = cmdbuf_wr_en | cmdbuf_vld; // @[ahb_to_axi4.scala 190:68]
wire _T_157 = ~cmdbuf_rst; // @[ahb_to_axi4.scala 190:112]
reg [2:0] _T_163; // @[Reg.scala 27:20] reg [2:0] _T_163; // @[Reg.scala 27:20]
reg [7:0] cmdbuf_wstrb; // @[Reg.scala 27:20] reg [7:0] cmdbuf_wstrb; // @[Reg.scala 27:20]
wire [7:0] master_wstrb = _T_72[7:0]; // @[ahb_to_axi4.scala 149:33] wire [7:0] master_wstrb = _T_72[7:0]; // @[ahb_to_axi4.scala 148:33]
reg [31:0] cmdbuf_addr; // @[el2_lib.scala 514:16] reg [31:0] cmdbuf_addr; // @[el2_lib.scala 514:16]
reg [63:0] cmdbuf_wdata; // @[el2_lib.scala 514:16] reg [63:0] cmdbuf_wdata; // @[el2_lib.scala 514:16]
wire [1:0] cmdbuf_size = _T_163[1:0]; // @[ahb_to_axi4.scala 197:33] wire [1:0] cmdbuf_size = _T_163[1:0]; // @[ahb_to_axi4.scala 196:33]
rvclkhdr rvclkhdr ( // @[el2_lib.scala 483:22] rvclkhdr rvclkhdr ( // @[el2_lib.scala 483:22]
.io_l1clk(rvclkhdr_io_l1clk), .io_l1clk(rvclkhdr_io_l1clk),
.io_clk(rvclkhdr_io_clk), .io_clk(rvclkhdr_io_clk),
@ -266,27 +269,27 @@ module ahb_to_axi4(
.io_en(rvclkhdr_5_io_en), .io_en(rvclkhdr_5_io_en),
.io_scan_mode(rvclkhdr_5_io_scan_mode) .io_scan_mode(rvclkhdr_5_io_scan_mode)
); );
assign io_axi_awvalid = cmdbuf_vld & cmdbuf_write; // @[ahb_to_axi4.scala 208:29] assign io_axi_awvalid = cmdbuf_vld & cmdbuf_write; // @[ahb_to_axi4.scala 207:29]
assign io_axi_awaddr = cmdbuf_addr; // @[ahb_to_axi4.scala 210:29] assign io_axi_awaddr = cmdbuf_addr; // @[ahb_to_axi4.scala 209:29]
assign io_axi_awsize = {1'h0,cmdbuf_size}; // @[ahb_to_axi4.scala 211:29] assign io_axi_awsize = {1'h0,cmdbuf_size}; // @[ahb_to_axi4.scala 210:29]
assign io_axi_awprot = 3'h0; // @[ahb_to_axi4.scala 212:29] assign io_axi_awprot = 3'h0; // @[ahb_to_axi4.scala 211:29]
assign io_axi_awlen = 8'h0; // @[ahb_to_axi4.scala 213:29] assign io_axi_awlen = 8'h0; // @[ahb_to_axi4.scala 212:29]
assign io_axi_awburst = 2'h1; // @[ahb_to_axi4.scala 214:29] assign io_axi_awburst = 2'h1; // @[ahb_to_axi4.scala 213:29]
assign io_axi_wvalid = cmdbuf_vld & cmdbuf_write; // @[ahb_to_axi4.scala 216:29] assign io_axi_wvalid = cmdbuf_vld & cmdbuf_write; // @[ahb_to_axi4.scala 215:29]
assign io_axi_wdata = cmdbuf_wdata; // @[ahb_to_axi4.scala 217:29] assign io_axi_wdata = cmdbuf_wdata; // @[ahb_to_axi4.scala 216:29]
assign io_axi_wstrb = cmdbuf_wstrb; // @[ahb_to_axi4.scala 218:29] assign io_axi_wstrb = cmdbuf_wstrb; // @[ahb_to_axi4.scala 217:29]
assign io_axi_wlast = 1'h1; // @[ahb_to_axi4.scala 219:29] assign io_axi_wlast = 1'h1; // @[ahb_to_axi4.scala 218:29]
assign io_axi_bready = 1'h1; // @[ahb_to_axi4.scala 221:29] assign io_axi_bready = 1'h1; // @[ahb_to_axi4.scala 220:29]
assign io_axi_arvalid = cmdbuf_vld & _T_37; // @[ahb_to_axi4.scala 223:29] assign io_axi_arvalid = cmdbuf_vld & _T_37; // @[ahb_to_axi4.scala 222:29]
assign io_axi_araddr = cmdbuf_addr; // @[ahb_to_axi4.scala 225:29] assign io_axi_araddr = cmdbuf_addr; // @[ahb_to_axi4.scala 224:29]
assign io_axi_arsize = {1'h0,cmdbuf_size}; // @[ahb_to_axi4.scala 226:29] assign io_axi_arsize = {1'h0,cmdbuf_size}; // @[ahb_to_axi4.scala 225:29]
assign io_axi_arprot = 3'h0; // @[ahb_to_axi4.scala 227:29] assign io_axi_arprot = 3'h0; // @[ahb_to_axi4.scala 226:29]
assign io_axi_arlen = 8'h0; // @[ahb_to_axi4.scala 228:29] assign io_axi_arlen = 8'h0; // @[ahb_to_axi4.scala 227:29]
assign io_axi_arburst = 2'h1; // @[ahb_to_axi4.scala 229:29] assign io_axi_arburst = 2'h1; // @[ahb_to_axi4.scala 228:29]
assign io_axi_rready = 1'h1; // @[ahb_to_axi4.scala 231:29] assign io_axi_rready = 1'h1; // @[ahb_to_axi4.scala 230:29]
assign io_ahb_hrdata = buf_rdata; // @[ahb_to_axi4.scala 158:33] assign io_ahb_hrdata = buf_rdata; // @[ahb_to_axi4.scala 157:33]
assign io_ahb_hreadyout = io_ahb_hresp ? _T_74 : _T_84; // @[ahb_to_axi4.scala 155:33] assign io_ahb_hreadyout = io_ahb_hresp ? _T_74 : _T_84; // @[ahb_to_axi4.scala 154:33]
assign io_ahb_hresp = _T_126 | _T_74; // @[ahb_to_axi4.scala 159:33] assign io_ahb_hresp = _T_126 | _T_74; // @[ahb_to_axi4.scala 158:33]
assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 484:17] assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 484:17]
assign rvclkhdr_io_en = io_bus_clk_en; // @[el2_lib.scala 485:16] assign rvclkhdr_io_en = io_bus_clk_en; // @[el2_lib.scala 485:16]
assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]

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src/main/scala/lib/ahb_to_axi4.scala
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@ -74,8 +74,8 @@ class ahb_to_axi4 extends Module with el2_lib with RequireAsyncReset {
val ahb_hresp_q = WireInit(Bool(), false.B) val ahb_hresp_q = WireInit(Bool(), false.B)
//Miscellaneous signals //Miscellaneous signals
val ahb_addr_in_iccm = WireInit(Bool(), false.B) // val ahb_addr_in_iccm = WireInit(Bool(), false.B)
val ahb_addr_in_iccm_region_nc = WireInit(Bool(), false.B) // val ahb_addr_in_iccm_region_nc = WireInit(Bool(), false.B)
// signals needed for the read data coming back from the core and to block any further commands as AHB is a blocking bus // signals needed for the read data coming back from the core and to block any further commands as AHB is a blocking bus
val buf_rdata_en = WireInit(Bool(), false.B) val buf_rdata_en = WireInit(Bool(), false.B)
@ -98,21 +98,20 @@ class ahb_to_axi4 extends Module with el2_lib with RequireAsyncReset {
val bus_clk = Wire(Clock()) val bus_clk = Wire(Clock())
// Address check dccm // Address check dccm
val (ahb_addr_in_dccm, ahb_addr_in_dccm_region_nc) = rvrangecheck_ch(ahb_haddr_q.asUInt,aslong(DCCM_SADR).asUInt(),DCCM_SIZE) val (ahb_addr_in_dccm_region_nc,ahb_addr_in_dccm) = rvrangecheck(DCCM_SADR,DCCM_SIZE,ahb_haddr_q)
val (ahb_addr_in_iccm_region_nc,ahb_addr_in_iccm) = if(ICCM_ENABLE) rvrangecheck(ICCM_SADR ,ICCM_SIZE,ahb_haddr_q) else (0.U,0.U)
// Address check iccm // Address check iccm
if (ICCM_ENABLE == 1) { // if (ICCM_ENABLE == 1) {
ahb_addr_in_iccm := rvrangecheck_ch(ahb_haddr_q.asUInt, aslong(ICCM_SADR).asUInt(), ICCM_SIZE)._1 // ahb_addr_in_iccm := rvrangecheck(ahb_haddr_q.asUInt, aslong(ICCM_SADR).asUInt(), ICCM_SIZE)._1
ahb_addr_in_iccm_region_nc := rvrangecheck_ch(ahb_haddr_q.asUInt, aslong(ICCM_SADR).asUInt(), ICCM_SIZE)._2 // ahb_addr_in_iccm_region_nc := rvrangecheck(ahb_haddr_q.asUInt, aslong(ICCM_SADR).asUInt(), ICCM_SIZE)._2
} // }
else { // else {
ahb_addr_in_iccm := 0.U // ahb_addr_in_iccm := 0.U
ahb_addr_in_iccm_region_nc := 0.U // ahb_addr_in_iccm_region_nc := 0.U
//
} // }
val (ahb_addr_in_pic_region_nc, ahb_addr_in_pic) = rvrangecheck(PIC_BASE_ADDR,PIC_SIZE,ahb_haddr_q)
// PIC memory address check // PIC memory address check
val (ahb_addr_in_pic, ahb_addr_in_pic_region_nc) = rvrangecheck_ch(ahb_haddr_q.asUInt,aslong(PIC_BASE_ADDR).asUInt(),PIC_SIZE)
// FSM to control the bus states and when to block the hready and load the command buffer // FSM to control the bus states and when to block the hready and load the command buffer
val buf_state = WireInit(idle) val buf_state = WireInit(idle)
val buf_nxtstate = WireInit(idle) val buf_nxtstate = WireInit(idle)

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target/scala-2.12/classes/lib/AHB_main$.class
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target/scala-2.12/classes/lib/AHB_main$delayedInit$body.class
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target/scala-2.12/classes/lib/ahb_to_axi4.class
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